Abstract:
A method of manufacturing a substrate including an electronic component, the method includes the steps of: preparing an electronic component having a terminal portion; preparing a first insulative sheet; mounting the electronic component to a surface of the first insulative sheet so that the terminal portion is opposed to the first insulative sheet; forming an opening portion in the first insulative sheet so that a surface of the terminal portion is exposed; and forming a conductive material that is extended from the terminal portion to an upper portion of the first insulative sheet.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a manufacturing method of an electronic components embedded substrate, in which electronic components such as an active element (for example, a transistor composing an electronic circuit) and a positive element (for example, a capacitor and a resistance) are embedded.  
         [0003]     This application is counterpart of Japanese patent application, Serial Number 330072/2003, filed Sep. 22, 2003, the subject matter of which is incorporated herein by reference.  
         [0004]     2. Description of the Related Art  
         [0005]     In recent years, in accordance with high density mounting of electronic components, an electronic components embedded substrate, in which electronic components such as an active element and a positive element are embedded, has been proposed.  
         [0006]     According to such a system for embedding the electronic components on the substrate, for example, in the event of incorporating a semiconductor chip and a chip component such as a resistance or a capacitor or the like are embedded together on the substrate, since thickness of each component is different, some countermeasures, for example, (1) embedding each component after forming a cavity on a mounted layer for each thickness and (2) using a spacer at a lower part of the mounted layer so that each thickness becomes equal are required.  
         [0007]     These methods (1) and (2) involve a problem such that the number of processes and components is increased due to formation of the cavity and mounting of the spacer, and this makes these methods technologically unsatisfying.  
         [0008]     In order to improve such a problem, JP-A-2002-110714 and JP-A-2002-290006 are suggested. In these suggestions, a method to seal a plurality of electronic components having different thickness by resin and to make an electronic components embedded substrate.  
         [0009]     [Patent Document] JP-A-2002-110714  
         [0010]     [Patent Document] JP-A-2002-290006  
         [0011]     However, according to the above-described JP-A-2002-110714, the electronic components are mounted on an insulative dummy sheet once to be provided with resin sealing, and then, the dummy sheet is peeled off. This dummy sheet is unnecessary in a final configuration.  
         [0012]     On the other hand, in JP-A-2002-290006, after setting up a bonding wire on an electrode of the electronic component and performing resin sealing, the resin layer is ground to expose a surface of the bonding wire and planarize it. Therefore, depending on a property of resin and how to perform the resin sealing process, the bonding wire may fall down or a front end position of the bonding wire may be deviated, and this makes difficult the front end of the bonding wire to be disposed at a predetermined position and this makes also difficult to accurately set a position where an outer terminal (a solder hall) is arranged. In this JP-A-2002-290006, restrains are placed on the property of the resin and the resin sealing process.  
         [0013]     Therefore, reduction of the number of the components and the processes and improvement of mass productivity are further expected.  
       SUMMARY OF THE INVENTION  
       [0014]     Accordingly, the present invention has been made taking the foregoing problems into consideration, and an object of the present invention is to provide a manufacturing method of an electronic components embedded substrate, which has less number of components and processes and is excellent in mass productivity.  
         [0015]     The above-described problems will be solved by the following means.  
         [0016]     Namely, the method of manufacturing a substrate including an electronic component, according to the present invention, may includes the steps of: preparing an electronic component having a terminal portion; preparing a first insulative sheet; mounting the electronic component to a surface of the first insulative sheet so that the terminal portion is opposed to the first insulative sheet; forming an opening portion in the first insulative sheet so that a surface of the terminal portion is exposed; and forming a conductive material that is extended from the terminal portion to an upper portion of the first insulative sheet.  
         [0017]     According to the method according to the present invention, electronic components are mounted on a first insulative sheet, this first insulative sheet may be used as it is without being peeled off, and an opening portion, through which a terminal portion is exposed, is provided by using the first insulative sheet as an interlayer insulative layer,. for example, by a buildup method. Further, a conductive member (for example, a wiring layer and an outer terminal) is provided, which is elongated from the terminal portion of the electronic component to the surface of the first insulative sheet through the foregoing opening portion. Thus, even if the electronic components having different thickness are embedded on the substrate, as compared to-the above-described methods using the dummy sheet or grinding the resin layer after resin sealing, it is possible to further reduce the number of the components and the processes and to improve its mass productivity.  
         [0018]     The method according to the present invention, as a process of protecting the electronic components, may have the step of burying the electronic components that are mounted on the foregoing first insulative sheet on a second insulative sheet and may have the step of sealing the electronic components that are mounted on the foregoing first insulative sheet by resin.  
         [0019]     The method according to the present invention, as the first insulative sheet, may use a prepreg or a photosensitive sheet.  
         [0020]     Here, a prepreg is obtained by soaking heat-curable resin (for example, epoxy resin, phenol resin or the like) in a base material (for example, paper, glass fabric, glass nonwoven fabric, synthetic resin or the like) and making the heat-curable resin into a half-cured condition.  
         [0021]     In addition, for example, a photosensitive sheet is a sheet that is composed of thermoplastic resin (for example, polyamide, polyamide or the like) having a photosensitive site and a sheet that is composed of a filler (for example, silica, calcium carbonate or the like) ingredient of the thermoplastic resin or the like.  
         [0022]     More specifically, the method of manufacturing a substrate including an electronic component, according to the present invention, may includes the steps of: preparing a first electronic component having a terminal portion on its main surface and having first thickness preparing a second electronic component having a terminal portion on its main surface and having second thickness that is thicker than the first thickness; preparing a first insulative sheet; mounting the first and second electronic components on the first insulative layer so that the terminal portion is opposed to the first insulative sheet; forming an opening portion in the first insulative sheet so that a surface of the terminal portions of the first and second electronic components are exposed; forming wiring patterns each of which is extended from the corresponding terminal portions of the first and second electronic components to the upper portion of the first insulative sheet; and covering the first and second electronic components by resin.  
         [0023]     In addition, the foregoing step of covering the foregoing first and second electronic components by resin may includes a step of preparing the foregoing second insulative sheet and a step of pressing the foregoing second insulative sheet against the foregoing first and second electronic components and burying the foregoing first and second electronic components in the foregoing second insulative sheet.  
         [0024]     In addition, the foregoing step of covering the foregoing first and second electronic components by resin may comprise a step of dripping liquid resin on the foregoing first and second electronic components.  
         [0025]     In addition, the foregoing step of forming an opening portion on the foregoing first insulative sheet may includes a step of using a photosensitive sheet as the foregoing first insulative sheet, directly exposing and developing the foregoing photosensitive sheet, and forming the foregoing opening portion through which the surfaces of the foregoing terminal portions of the foregoing first and second electronic components are exposed.  
         [0026]     The present invention may have a function to reduce the number of the components and the processes is less and to be excellent in mass productivity. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0027]      FIG. 1  is a process drawing showing a manufacturing method of an electronic components embedded substrate according to a first embodiment of the present invention; and  
         [0028]      FIG. 2  is a process drawing showing a manufacturing method of an electronic components embedded substrate according to a second embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0029]     The embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. With respect to the substantially identical functional parts, the identical reference numerals are given through the all drawings and the explanations thereof may be omitted according to the circumstance.  
       First Embodiment  
       [0030]      FIG. 1  is a process drawing showing a manufacturing method of an electronic components embedded substrate according to the first embodiment of the present invention.  
         [0031]     According to the present embodiment, at first, for example, a prepreg for mounting  14  (a first insulative sheet) for mounting the electronic components in a half-cured condition thereon, in which epoxy resin is soaked into glass nowoven fabric, a WCSP  10  (an electronic component) in which a semiconductor chip is packaged, and a rectangular chip component  12  (an electronic component) such as a capacitor and a resistance or the like are prepared ( FIG. 1A ). This WCSP  10  and the chip component  12  have different thickness, and according to the present embodiment, a first electronic component having first thickness may correspond to the chip component  12  and a second electronic component having second thickness thicker than the first thickness may correspond to the WCSP  10 .  
         [0032]     In this case, the WCSP (Wafer Level Chip Size Package or Wafer Level Chip Scale Package) and its MCP (Multi Chip Package) may have a substantially identical outer measurement as a chip size that is obtained by packaging in a wafer level and separating the package. Then, the WCSP is secured to be a completely good quality product in a package condition. Such WCSP is disclosed, for example, in JP-A-9-64049.  
         [0033]     In the next place, on the prepreg for mounting  14 , a plurality of the WCSP  10  and the chip component  12  having the different thickness is mounted ( FIG. 1B ). In this case, the WCSP  10  as the electronic component and the chip component  12  are mounted on the prepreg for mounting  14  so that their terminals  10   a  and  12   b  may face the prepreg for mounting  14 . In the case of the WCSP  10 , the terminal portion  10   a  is disposed on a main surface of the chip, where an integrated circuit is formed.  
         [0034]     As a fixing method of the WCSP  10  as the electronic component and the chip component  12 , a method to fix them by using an adhesive bond or a method to fix them by mounting the electronic components under the condition that the prepreg is heated over its softening temperature may be available, however, the fixing method is not limited to these.  
         [0035]     Then, a prepreg for burying  16  to bury the WCSP  10  and the chip component  12  (a second insulative sheet) and a prepreg for protecting  18  to protect the surface of the prepreg for burying  16  are prepared ( FIG. 1C ).  
         [0036]     In the next place, after superimposing the prepreg for mounting  14 , on which the WCSP  10  and the chip component  12  are mounted, the prepreg for burying  16 , and the prepreg for protecting  18 , for example, they are heated and pressurized over the softening temperature of the prepreg for burying  16  and the WCSP  10  and the chip component  12  are buried on the prepreg-for burying  16  to be protected. Further, three prepregs are laminated ( FIG. 1D ).  
         [0037]     After that, using the prepreg for mounting  14  as the interlayer insulative layer, the following buildup method will be applied ( FIG. 1E ).  
         [0038]     At first, a laser (for example, a CO 2  laser, a UV-YAG laser or the like) is irradiated on the portion of the prepreg for mounting  14  located on the terminal  10   a  of the WCSP  10  and the prepreg for mounting  14  located on the terminal  12   a  of the chip component  12  to form a via opening portion  20 , and further, to expose the terminal  10   a  of the WCSP  10  and the terminal  12   a  of the chip component  12 .  
         [0039]     In the next place, a conductive layer is formed by plating or the like on the surface of the prepreg for mounting  14  including the via opening portion  20 . Consequently, a photo resist is formed on this conductive layer, this photo resist is exposed and developed into a predetermined shape, and then, the conductive layer is patterned by using this photo resist as a mask. After that, the photo resist may be removed. As a result, a wiring layer  22  that is patterned into a predetermined shape is obtained. An end of this wiring layer  22  is located on the terminal  10   a  of the WCSP  10  and the terminal  12   a  of the chip component  12 , and the other end thereof is located on the surface of the prepreg for mounting  14 , which is remote from the WCSP  10  and the chip component  12 . In other words, the wiring layer  22  is elongated from the terminal of each electronic component to the surface of the prepreg for mounting  14 . The other end of the wiring layer  22  is a land portion  22   a  where a solder ball  24  (to be described later) is formed.  
         [0040]     In the next place, a solder resist film  26  as a surface protecting layer is formed all over the prepreg for mounting  14 . After that, a photo resist may be formed on the prepreg for mounting  14 , and then, this photo resist is exposed and developed, and by using this photo resist as a mask, a solder-resist film  26  placed on the land portion  22   a  (the other end) of the wiring layer  22  is removed by etching to form an opening portion  28 . Then, in this opening portion  28 , the solder ball  24  is provided.  
         [0041]     A buildup method of a single layer is described as above. If a multilayer configuration is needed, layer stack of the prepreg layer, formation of the via opening portion, and formation of the wiring layer may be repeated.  
         [0042]     According to the present embodiment, as the buildup method, an embodiment forming the via .opening portion  20  is described, however, an embodiment forming a through hall (th) and an inductor or the like may be possible.  
         [0043]     As described above, according to the present embodiment, the prepreg for mounting  14  (the first insulative sheet), on which the WCSP  10  and the chip component  12  are mounted on a predetermined position, is used as the interlayer insulative layer as it is, and by the buildup method, the wire configuration is formed on this prepreg for mounting  14 , and this makes it possible to reduce the number of the components and the processes.  
       Second Embodiment  
       [0044]      FIG. 2  is a process drawing showing a manufacturing method of an electronic components embedded substrate according to a second embodiment of the present invention.  
         [0045]     According to the present embodiment, without using the prepreg for burying  16 , a plurality of the WCSP  10  and the chip components  12  having the different thickness is mounted on the prepreg for mounting  14  ( FIG. 2B ), and then, the sealing resin  26 , which is obtained by dripping liquid resin from rear surface sides of these to the WCSP  10  and the chip component  12  and solidifying the liquid resin by heating (curing), may seal these ( FIG. 2C ). Then, preparing the prepreg for protecting  18  ( FIG. 2D ), in accordance to need, the surface of the sealing resin  26  is ground and planarized. After that, the prepreg for protecting  18  is laminated ( FIG. 2E ). Then, the buildup method is applied ( FIG. 2F ). Since the processes other than this is identical with those of the above-described first embodiment, there explanations are omitted.  
         [0046]     According to the present embodiment, since the WCSP  10  as the electronic component and the chip component  12  are simply resin-sealed by the sealing resin  26 , which is obtained by dripping liquid resin from rear surface sides of these to the WCSP  10  and the chip component  12  and solidifying the liquid resin by heating (curing), as compared to the first embodiment, it is possible to protect the WSCP  10  and the chip component  12  without adding pressure and to manufacture the electronic components embedded substrate without giving the stress to the WCSP  10  as the electronic component and the chip component  12 . Therefore, a highly reliable electronic components embedded substrate can be obtained.  
       Third Embodiment  
       [0047]     According to the present embodiment, an insulative photosensitive sheet may be used as the prepreg for mounting  14 , and upon forming the via opening portion  20  in the buildup method, as indicated below, a photo lithography method may be adopted (refer to  FIG. 1E  or  FIG. 2F ). Other than this, the present invention is identical with the above-described first or second embodiment, so that the explanation except for this is herein omitted.  
         [0048]     At first, in  FIG. 1E  or  FIG. 2F , after a pattern of a photo mask is exposed and copied directly on the prepreg for mounting  14 , the prepreg for mounting  14  is developed, a portion of the prepreg for mounting  14  placed on the terminal  10   a  of the WCSP  10  and a portion thereof placed on the terminal  12   a  of the chip component  12  are removed to form the via opening portion  20  and to expose the terminal  10   a  of the WCSP  10  and the terminal  12   a  of the chip component  12 .  
         [0049]     In the next place, a conductive layer is formed by plating or the like on the surface of the prepreg for mounting  14  including the via opening portion  20 . Consequently, a photo resist is formed on this conductive layer, this photo resist is exposed and developed into a predetermined shape, and then, the conductive layer is patterned by using this photo resist as a mask. After that, the photo resist may be removed. As a result, a wiring layer  22  that is patterned into a predetermined shape is obtained. An end of this wiring layer  22  is located on the terminal  10   a  of the WCSP  10  and the terminal  12   a  of the chip component  12 , and the other end thereof is located on the surface of the prepreg for mounting  14 , which is remote from the WCSP  10  and the chip component  12 . In other words, the wiring layer  22  is elongated from the terminal of each electronic component to the surface of the prepreg for mounting  14 . The other end of the wiring layer  22  is a land portion  22   a  where a solder ball  24  (to be described later) is formed.  
         [0050]     In the next place, a solder resist film  26  as a surface protecting layer is formed all over the prepreg for mounting  14 . After that, a photo resist may be formed on the prepreg for mounting  14 , and then, this photo resist is exposed and developed, and by using this photo resist as a mask, a solder-resist film  26  placed on the land portion  22   a  (the other end) of the wiring layer  22  is removed by etching to form an opening portion  28 . Then, in this opening portion  28 , the solder ball  24  is provided.  
         [0051]     A buildup method of a single layer is described as above. If a multilayer configuration is needed, layer stack of the prepreg layer, formation of the via opening portion, and formation of the wiring layer may be repeated. Further, as the prepreg layer from a second one and after, formation of coating by using a liquid photosensitive material in place of a layer of a sheet material may be adopted.  
         [0052]     Thus, according to the present embodiment, by using the photosensitive adhesive sheet as the prepreg for mounting  14 , the photo lithography method can be adopted upon forming the via opening portion  20 , and this results in more improvement of mass productivity as compared to the above-described first and second embodiment.  
         [0053]     According to any one of the above-described embodiments, the configuration with the solder ball  24  provided to the outer terminal, is explained, however, as same as normal daughter board and mother board, a connection within the system may be configured by a connector and a plug or the like.  
         [0054]     According to any one of the above-described embodiments, the configuration with the WCSP  10  embedded as the electronic component including the positive element, is explained, however, as this kind of electronic component, not only a MCP (Multi Chip Package) with a plurality of WCSP laminated but also a system packaged in a wafer condition and a pair of semiconductor chips may be adopted.  
         [0055]     According to any one of the above-described embodiments, the configuration using the rectangular component as the chip component  12  such as the capacitor and the resistance or the like is explained, however, the chip component  12  as the electronic component is not limited to this and the component having an outer terminal on a single plane may be available.  
         [0056]     According to any one of the above-described embodiments, the configuration with two electronic components having different thickness embedded is explained, however, the electronic component is not limited to this and the number and the sort of the electronic components to be embedded can be appropriately selected.  
         [0057]     According to any one of the above-described embodiments, the wire configuration of a single layer is explained, however, a multilayer wire configuration may be available.  
         [0058]     According to any one of the above-described embodiments, the configuration using, as the insulative sheet, the prepreg for mounting  14  and the photosensitive sheet are explained, and in the prepreg for mounting  14  and the photosensitive sheet, a copper foil layer may be formed in advance, or the electronic components may be embedded in advance.  
         [0059]     The present invention should not be interpreted in a limited way in any of the above-described embodiments, and it is a matter of course that the present invention can be realized within a range satisfying the requirements of the present invention.