Abstract:
The present invention provides an A/D converter. An upper comparison voltage generator divides a reference voltage into a plurality of large-level regions with series-connected first voltage-dividing elements, and outputs voltages at boundaries of the individual large-level regions as upper comparison voltages. Upper comparators compare an analog input voltage with the individual upper comparison voltages. An upper encoder determines, from output signals of the upper comparators, to which one of the large-level regions the analog input voltage belongs, and outputs a predetermined upper digital code corresponding to the determined large-level region. A lower comparison voltage generator divides the large-level region to which the analog input voltage is determined to belong by the upper encoder, into a plurality of small-level regions with second voltage-dividing elements and outputs voltages at boundaries of the individual small-level regions as lower comparison voltages. Lower comparators compare the analog input voltage with the individual lower comparison voltages. A lower encoder determines, from output signals of the lower comparators, to which one of the small-level regions the analog input voltage belongs, and outputs a predetermined lower digital code corresponding to the determined small-level region.

Description:
This application is a continuation of Ser. No. 08/140,558 filed Oct. 25, 1993, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an A/D converter for converting an analog signal into a digital signal. 
     2. Description of the Related Art 
     As the number of electronic devices which handle digital signal processing have greatly increased in recent times, there is a concomitant increase in the demand for A/D converters which convert analog signals into digital signals. A parallel comparison type (flash type) A/D converter, one type of A/D converter, needs 2 n −1 comparators to acquire an n-bit digital output signal. As the number of bits in the digital output signal increases, the circuit scale increases exponentially. However a series-parallel comparison type (2-step parallel type) A/D converter needs fewer comparators, and thus can utilize a smaller circuit scale than the parallel comparison type A/D converter. Due to the recent increase in the number of bits in the digital output signal of A/D converters, there is a strong demand to make the circuit scale of the parallel comparison type A/D converter smaller. 
     The conventional 2-step parallel A/D converter is described in detail in IEEE-ISSCC, Report No. WAM-36, February 1982. 
     FIG. 1 is a circuit diagram showing the structure of the conventional 4-bit 2-step parallel A/D converter. 
     A high reference voltage V RH  and a low reference voltage V RL  are divided by the resistor string formed by 16 series-connected resistors R. Those resistors R have the same resistance. The resistor string is separated into four blocks B 1  to B 4  each consisting of four series-connected resistors R. The nodes between the blocks B 1  and B 2 , B 2  and B 3 , and B 3  and B 4  are connected to the inverting input terminals of associated comparators  10  to  12 . Reference voltages V 1  to V 3  respectively output from those three nodes are input to the inverting input terminals of the associated comparators  10  to  12 . The reference voltages V 1  to V 3  each have a value obtained by dividing the potential difference between the high reference voltage V RH  and low reference voltage V RL  by four. 
     Three nodes between the four resistors R, which constitute each of the blocks B 1  to B 4 , are connected via an associated set of three switches S A , S B , S C  or S D  to the inverting input terminals of comparators  20  to  22 . Reference voltages Va to Vc are respectively applied to the inverting input terminals of the comparators  20  to  22 . 
     An analog input signal A in  is input to the non-inverting input terminals of the individual comparators  10  to  12  and  20  to  22 . The comparators  10  to  12  compare the associated reference voltages V 1  to V 3  with the analog input signal A in . Each comparator  10 ,  11  or  12  outputs a signal of a low (L) level when the voltage level of the analog input signal A in  becomes lower than that of the reference voltage V 1 , V 2  or V 3 , and outputs a signal of a high (H) level when the voltage level of the analog input signal A in  becomes higher than that of the reference voltage V 1 , V 2  or V 3 . The output signals (thermometer codes) of the comparators  10  to  12  are input to a first encoder  40 . The first encoder  40  determines to which one of four large-level regions the voltage level of the analog input signal A in  belongs: region V RB  to V 1 , V 1  to V 2 , V 2  to V 3  and V 3  to V RL . Those four regions are acquired by dividing the potential difference between the high reference voltage V RH  and low reference voltage V RL  by four. The first encoder  40  encodes the result of the decision into a binary code and converts the binary code into a 2-bit digital output en 11 , en 10 . 
     Based on the digital output en 11 , en 10 , a switch control circuit (not shown) closes (enables) one set of switches S A , S B , S C  or S D  respectively corresponding to the first, second, third or fourth large-level region. 
     The reference voltages Va to Vc, obtained by further dividing the potential differences of the four large-level regions by four, are applied to the inverting input terminals of the associated comparators  20  to  22  via the closed switches S A  to S D . The comparators  20  to  22  compare the associated reference voltages Va to Vc with the analog input signal A in . Each comparator  20 ,  21  or  22  outputs an L-level signal when the voltage level of the analog input signal A in  becomes lower than that of the reference voltage Va, Vb or Vc, and outputs an H-level signal when the voltage level of the analog input signal A in  becomes higher than that of the reference voltage Va, Vb or Vc. The output signals of the comparators  20  to  22  are input to a second encoder  50  having the same structure as the first encoder  40 . The second encoder  50  determines to which one of four small-level regions the voltage level of the analog input signal A in  belongs: reference voltage Va or above, between Va and Vb, between Vb and Vc, and Vc or below. These small-level regions are acquired by dividing the associated large-level regions by four. The second encoder  50  encodes the result of the decision into a binary code and converts the binary code into a 2-bit digital output en 21 , en 20 . 
     In the conventional 4-bit 2-step parallel A/D converter, as described above, the first A/D conversion is performed by the comparators  10  to  12  and the first encoder  40 , yielding the upper 2-bit digital output en 11 , en 10 . Then, based on the digital output en 11 , en 10 , the switches S A  to S D  are switched over, and the second A/D conversion is performed by the comparators  20  to  22  and the second encoder  50 , yielding the lower 2-bit digital output en 21 , en 20 . 
     FIG. 2 illustrates the circuit structure in the case where the aforementioned 4-bit 2-step parallel A/D converter is laid out on a semiconductor substrate. The resistors R and the switches S A  to S D  are laid out to form a rectangular pattern as a whole. The comparators  10  to  12  are arranged on the right side of the rectangle, with the first encoder  40  arranged outside the locations of the comparators. Arranged below the bottom side of the rectangle are the comparators  20  to  22  which perform the second A/D conversion. Arranged further outside the comparators  20  to  22  is the second encoder  50  which also performs the second A/D conversion. The layout on the substrate is given regularity by regularly arranging the comparators  10  to  12  and  20  to  22  and the encoders  40  and  50  around the regularly laid-out resistors R and switches S A  to S D . 
     If the comparator  11  shown in FIG. 2 is arranged to the left side of or above the rectangle formed by the resistors R and switches S A  to S D , wiring connecting the inverting input terminal of the comparator  11  and the node between the blocks B 2  and B 3  does not pass over the individual resistors R and switches S A  to S D , further facilitating the layout on the substrate. It should be noted that the order with which the voltages are applied to the inverting input terminals of the comparators  20  to  22  via the respective switches S A  to S D  in FIG. 2 differs from the order of the application of the voltages to the inverting input terminals of the comparators  20  to  22  via the respective switches S A  to S D  in FIG.  1 . This is because the order with which the voltages are supplied to the comparators  20  to  22  in the first row (block B 1 ) and the third row (block B 3 ) of the resistor string is reverse to that in the second row (block B 2 ) and the fourth row (block B 4 ). Therefore, the second encoder  50  should be designed to reverse the order of the comparison results, which are output from the individual comparators  20  to  22  depending on which of the switches S A  to S D  is closed. 
     The 2-step parallel A/D converter shown in FIGS. 1 and 2 needs a sample and hold circuit, not shown, which samples and latches the analog input signal A in  so that the level of the analog input signal A in  will not vary during the two A/D conversions. 
     If the number of bits is increased in the 2-step parallel A/D converter, the circuit scale inevitably increases. For instance, a 6-bit 2-step parallel A/D converter needs 64 resistors R, 56 switches and 14 comparators. The structure of each encoder becomes complex and the circuit scale becomes about four times that of the 4-bit type. An 8-bit 2-step parallel A/D converter needs 265 resistors R, 240 switches and 30 comparators. Consequently the structure of each encoder becomes more complex and the circuit scale increases to about 16 times that of the 4-bit type. Moreover, the increase in the number of comparators also increases the power consumed in operating the A/D converter. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a 2-step parallel A/D converter which is designed to minimize the circuit scale that is necessitated by increased multi-bit structure. 
     To achieve this object, according to the present invention, upper comparison voltage generating means divides a reference voltage into a plurality of large-level regions with series-connected first voltage-dividing elements and outputs voltages at boundaries of the individual large-level regions as upper comparison voltages. Upper comparators compare an analog input voltage with the individual upper comparison voltages. Upper determining means determines, from output signals of the upper comparators, to which one of the large-level regions the analog input voltage belongs, and by a further included convertor means outputs a predetermined upper digital code corresponding to the determined large-level region. Lower comparison voltage generating means divides the large-level region to which the analog input voltage is determined to belong by the upper determining means, into a plurality of small-level regions having second voltage-dividing elements and outputs voltages at boundaries of the individual small-level regions as lower comparison voltages. Lower comparators compare the analog input voltage with the individual lower comparison voltages. Lower determining means determines, from output signals of the lower comparators, to which one of the small-level regions the analog input voltage belongs, and by a further included comparison means outputs a predetermined lower digital code corresponding to the determined small-level region. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features of the present invention that are believed to be novel are set forth with particularity in the appended claims. The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which: 
     FIG. 1 is a circuit diagram showing a conventional 2-step parallel A/D converter; 
     FIG. 2 is a circuit diagram showing the conventional 2-step parallel A/D converter laid out on a semiconductor substrate; 
     FIG. 3 is a circuit diagram showing a 6-bit A/D converter according to one embodiment of the present invention; 
     FIG. 4 is a circuit diagram showing a first encoder; 
     FIG. 5 is an explanatory diagram illustrating the function of the first encoder; 
     FIG. 6 is a circuit diagram showing a second encoder; 
     FIG. 7 is an explanatory diagram illustrating the function of the second encoder; 
     FIG. 8 is a circuit diagram showing a third encoder; 
     FIG. 9 is an explanatory diagram illustrating the function of the third encoder; 
     FIG. 10 is a circuit diagram showing a clock generator; 
     FIG. 11 is a circuit diagram showing a crystal oscillator; 
     FIG. 12 is a waveform diagram illustrating the function of the clock generator; 
     FIG. 13 is a circuit diagram showing a sample and hold circuit; 
     FIG. 14 is a circuit diagram showing the structure of a switch; 
     FIG. 15 is a circuit diagram showing a switch control circuit; 
     FIG. 16 is an explanatory diagram illustrating the function of the switch control circuit; 
     FIG. 17 is a circuit diagram showing another switch control circuit; 
     FIG. 18 is an explanatory diagram illustrating the function of this switch control circuit; 
     FIG. 19 is an explanatory diagram illustrating the function of this embodiment; and 
     FIG. 20 is a circuit diagram of a 4-bit A/D converter according to another embodiment of this invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A 6-bit A/D converter according to a first embodiment of the present invention will now be described referring to FIGS. 3 to  19 . As shown in FIG. 3, a high reference voltage V RH  and a low reference voltage V RL  are divided by the resistor string formed by 16 series-connected resistors R 1 . Those resistors R 1  have the same resistance. The resistors R 1  are separated into four blocks B 5  to B 8  each consisting of four resistors R 1 . The nodes between the blocks B 5  and B 6 , B 6  and B 7 , and B 7  and B 8  are connected to the inverting input terminals of associated comparators  15  to  13 . Reference voltages V 1  to V 3  are respectively input to the non-inverting input terminals of the comparators  15  to  13 . In each of the blocks B 5  to B 8 , the left end of the leftmost resistors R 1 , the three nodes between the four resistors R 1 , and the right end of the rightmost resistor R 1  are connected to a set of five switches S A , S B , S C  and S D , respectively for each block. Left end switches S A5 , S B5 , S C5  and S D5  of the four sets of switches S A , S B , S C  and S D  are connected via a switch S E1  to a capacitor C 4 . Right end switches S A9 , S B9 , S C9  and S D9  of the switch sets S A , S B , S C  and S D  are connected via a switch S B2  to a capacitor C 1 . As the switches S B5  and S C5 , the switches S A9  and S B9 , and the switches S C9  and S D9  are respectively connected in parallel, one switch in each parallel circuit also serves as the other switch for an adjacent parallel circuit. 
     Switches S A6 , S B6 , S C6  and S D6  of the individual sets of switches S A , S B , S C  and S D  are connected to the inverting input terminal of a comparator  23 . The inverting input terminal of this comparator  23  is also connected via a switch S F1  to the capacitor C 4  and connected via a switch S E2  to the capacitor C 1 . Switches S A7 , S B7 , S C7  and S D7  of the individual sets of switches S A , S B , S C  and S D  are connected to the inverting input terminal of a comparator  24 . The inverting input terminal of this comparator  24  is also connected via a switch S G1  to the capacitor C 4  and is further connected via a switch S F2  to the capacitor C 1 . Switches S A8 , S B8 , S C8  and S D8  of the individual sets of switches S A , S B , S C  and S D  are connected to the inverting input terminal of a comparator  25 . The inverting input terminal of this comparator  25  is also connected via a switch S H1  to the capacitor C 4  and is further connected via a switch S G2  to the capacitor C 1 . The sets of the switches S E  to S H  each consists of two switches. The reference voltages which are applied to the inverting input terminals of the individual comparators  23  to  25  are respectively expressed by Vd to Vf. 
     An analog input signal A in  is input to the non-inverting input terminals of the individual comparators  15  to  13  via a sample and hold (S/H) circuit  80 . The comparators  15  to  13  compare the associated reference voltages V 1  to V 3  with the analog input signal A in . The individual comparators  15  to  13  output L-level signals CM 15  to CM 13  when the voltage level of the analog input signal A in  becomes lower than those of the reference voltages V 1  to V 3 . Comparators  15  to  13  output H-level signals CM 15  to CM 13  when the voltage level of the analog input signal A in  becomes higher than those of the reference voltages V 1  to V 3 . The output signals CM 15  to CM 13  of the comparators  15  to  13  are input to a first encoder  41 . The first encoder  41  determines to which one of four large-level regions the voltage level of the analog input signal A in  belongs: from V RH  down to V 1 , from less than V 1  down to V 2 , from less than V 2  down to V 3  and from less than V 3  down to V RL . These four regions are defined by the reference voltages V 1  to V 3 . The first encoder  41  encodes the result of the decision into a binary code and converts the binary code into an upper 2-bit digital output en 13 , en 12 . 
     Based on the digital output en 13 , en 12 , a switch control circuit  90  closes or enables one set of switches S A , S B , S C  or S D  respectively corresponding to the large-level region of the analog input signal A in . That is, the individual switches S A5  to S A8  in the switch set S A  are closed simultaneously based on a control signal S A  output from the switch control circuit  90 . Likewise, the individual switches S B5  to S B8 , S C5  to S C8 , and S D5  to S D8  in the switch sets S B , S C  and S D  respectively, are closed simultaneously based on respective control signals S B  to S D  output from the switch control circuit  90 . The reference voltage Vd to Vf, obtained by further dividing the large-level regions of the analog input signal A in  by four, are applied to the inverting input terminals of the associated comparators  23  to  25  via the closed switches S A  to S D . The analog input signal A in  is input via the sample and hold (S/H) circuit  80  to the non-inverting input terminals of the comparators  23  to  25 . The comparators  23  to  25  compare the associated reference voltages Vd to Vf with the analog input signal A in . The individual comparators  23  to  25  output L-level signals CM 23  to CM 25  when the voltage level of the analog input signal A in  becomes lower than those of the reference voltages Vd to Vf, and output H-level signals CM 23  to CM 25  when the voltage level of the analog input signal A in  becomes higher than those of the reference voltages Vd to Vf. 
     The output signals CM 23  to CM 25  of the comparators  23  to  25  and the lower part, en 12 , of the aforementioned 2-bit digital output en 13 , en 12  are input to a second encoder  51 . The second encoder  51  determines to which one of middle-level regions, acquired by dividing the large-level regions by four, the voltage level of the analog input signal A in  belongs. The second encoder  51  encodes the result of the decision into a binary code and converts the binary code into a middle 2-bit digital output en 23 , en 22 . The middle-level regions are the reference voltage Vd or above, between Vd and Ve, between Ve and Vf, and Vf or below for the blocks B 1  and B 3 , and are the reference voltage Vf or above, between Vf and Ve, between Ve and Vd, and Vd or below for the blocks B 2  and B 4 . 
     A switch control circuit  100  closes one set of switches S E , S F , S G  or S H  corresponding to the middle-level region of the analog input signal A in  based on the middle 2-bit digital output en 23 , en 22  and the lower part, en 12 , of the upper 2-bit digital output en 13 , en 12 . That is, the individual switches S E1  and S E2  of the switch set S E  are simultaneously closed based on a control signal S E  from the switch control circuit  100 . Likewise, the individual switches S F1  and S F2 , S G1  and S G2 , and S H1  and S H2  of the switch sets S F , S G  and S H  are simultaneously closed based on respective control signals S F , S G  and S H  from the switch control circuit  100 . 
     Four capacitors C 1  to C 4  having the same capacitance are connected in series. The potential difference of the aforementioned middle-level region is applied to both ends of the series circuit of the capacitors C 1  to C 4  via the switches S E  and S F . The applied voltage is divided by four by the capacitors C 1  to C 4 . The three nodes between the capacitors C 1  to C 4  are connected to the inverting input terminals of comparators  30  to  32 . Accordingly, applied to the inverting input terminals of the comparators  30  to  32  are voltages Vg to Vi which are acquired by dividing the middle-level region of the reference voltage by four. The analog input signal A in  is input to the non-inverting input terminals of the individual comparators  30  to  32  via the sample and hold (S/H) circuit  80 . The comparators  30  to  32  compare the associated reference voltages Vg to Vi with the analog input signal A in . The individual comparators  30  to  32  output L-level signals CM 30  to CM 32  when the voltage level of the analog input signal A in  becomes lower than those of the reference voltages Vg to Vi, and output H-level signals CM 30  to CM 32  when the voltage level of the analog input signal A in  becomes higher than those of the reference voltages Vg to Vi. The output signals CM 30  to CM 32  of the comparators  30  to  32  and the lower part, en 12 , of the upper 2-bit digital output en 13 , en 12  are input to a third encoder  60 . The third encoder  60  determines to which one of four small-level regions, obtained by dividing the middle-level region by four, the voltage level of the analog input signal A in  belongs. The third encoder  60  encodes the result of the decision into a binary code and converts the binary code into a lower 2-bit digital output en 31 , en 30 . The small-level regions are the voltage Vg or above, between Vg and Vh, between Vh and Vi, and Vi or below when a higher potential than that of the capacitor C 4  is supplied to the capacitor C 1 , and are the voltage Vi or above, between Vi and Vh, between Vh and Vg, and Vg or below when a higher potential than that of the capacitor C 1  is supplied to the capacitor C 4 . 
     The first encoder  41  comprises an AND gate  42  and a NOR gate  43 , as shown in FIG. 4, and outputs the digital signals en 12  and en 13  based on the output signals CM 15  to CM 13  output from the comparators  15  to  13  as shown in FIG.  5 . The second encoder  51  comprises NAND gates  52  to  55  and NOR gates  56  and  57 , as shown in FIG. 6, and outputs the digital signals en 22  and en 23  based on the output signals CM 23  to CM 25  output from the comparators  23  to  25  and the digital signal en 12  as shown in FIG.  7 . The third encoder  60  comprises NAND gates  61  to  64  and NOR gates  65  and  66 , as shown in FIG. 8, and outputs the digital signals en 30  and en 31  based on the output signals CM 30  to CM 32  output from the comparators  30  to  32  and the digital signal en 12  as shown in FIG.  9 . 
     The aforementioned sample and hold circuit  80  and individual switch control circuits  90  and  100  operate in accordance with clock signals CLK 1  to CLK 3  output from a clock generator  70 . As shown in FIG. 10, the clock generator  70  comprises a crystal oscillator  71 , D flip-flops  72  to  75 , AND gates  76  and  77  and an invertor  78 . When receiving a reset signal RESET from outside, the clock generator  70  generates clock signals CLK 1  to CLK 3  shown in FIG. 12 based on a reference clock signal CLK 0  output from the crystal oscillator  71 . 
     As shown in FIG. 11, the crystal oscillator  71  comprises CMOS inverters  71   a  and  71   b , a feedback resistor  71   c , a crystal oscillator  71   d  and capacitors  71   e  and  71   f . The crystal oscillator  71  amplifies the oscillation signal output from the crystal oscillator  71   d  and outputs the amplified signal as the reference clock signal CLK 0 . As shown in FIG. 12, after receiving the reset signal RESET from outside, the clock generator  70  first generates the clock signal CLK 1  having a length of one period of the reference clock CLK 0  from the crystal oscillator  71 . Two periods after the rise of clock signal CLK 1 , the clock generator  70  generates the clock signal CLK 2  having a length of two periods of the reference clock CLK 0 . Three periods after the rise of reference clock signal CLK 0 , the clock generator  70  generates the clock signal CLK 3  having a length of one period of the reference clock CLK 0 . 
     As shown in FIG. 13, the sample hold circuit  80  comprises a switch  81 , whose switching operation is controlled by the clock signal CLK 1 , a capacitor  82  and a buffer amplifier  83 . The buffer amplifier  83  is designed to have 100% feedback. When the clock signal CLK 1  is input to the sample hold circuit  80 , the switch  81  is closed, causing the capacitor  82  to be charged to the voltage level of the externally supplied analog input signal A in . When the switch  81  is opened, the capacitor  82  holds the charged voltage level of the analog input signal A in . The buffer amplifier  83  has a high input impedance, and thus prevents the discharging of the electric charges accumulated in the capacitor  82  so that the capacitor  82  can hold the voltage level of the analog input signal A in . In short, the sample hold circuit  80  samples and holds the externally supplied analog input signal A in  accordance with the clock signal CLK 1 , and supplies its output as the analog input signal A in  to the non-inverting input terminals of the individual comparators  12  to  10 ,  20  to  22  and  30  to  32 . 
     As shown in FIG. 14, each of the switches S A  to S H  is a well-known CMOS analog switch comprising a CMOS invertor  84  and a CMOS transfer gate  85 . The individual switches S A  to S H  are closed based on the control signals S A  to S H  output from the switch control circuits  90  and  100 , establishing a conductive state between terminals α and β of each switch. (For convenience, the reference characters of the switches S A  to S H  are used to denote the associated control signals.) The individual switches S A  to S H  are opened based on the control signals S A  to S H  output from the switch control circuits  90  and  100 , establishing a non-conductive state between the terminals α and β of each switch. The switch control circuit  90  comprises AND gates  91  to  97  and a NOR gate  98 , as shown in FIG. 15, and produces the control signals S A  to S D  shown in FIG. 16 based on the clock signal CLK 2  and the digital signals enl 2  and en 13 . The switch control circuit  100  comprises AND gates  101  to  116 , OR gates  117  to  120  and an invertor  121 , as shown in FIG. 17, and produces the control signals S E  to S H  shown in FIG. 18 based on the clock signal CLK 3  and the digital signals en 12 , en 22  and en 23 . 
     The function of this embodiment will now be described referring to FIG.  19 . According to this embodiment, the 6-bit A/D conversion of the analog input signal A in  is conducted in three operations, two bits in each operation, starting from the most significant bit (MSB). The first A/D conversion is executed by the comparators  15  to  12  and the first encoder  41 , yielding the upper 2-bit digital output en 13 , en 12 . When the analog input signal A in  belongs to the large-level region ranging from the reference voltage V 2  to V 3 , the output signals CM 15  and CM 14  of the comparators  15  and  14  both become an L level or “ 0 ” and the output signal CM 13  of the comparator  13  becomes an H level or “ 1 ”. Based on the individual output signals CM 15 , CM 14  and CM 13 , the first encoder  41  determines that the analog input signal A in  belongs to the large-level region of V 2  to V 3 , and outputs the digital output en 13  of “ 0 ” and the digital output en 12  of “ 1 ” as shown in FIG.  5 . Based on this upper 2-bit digital output en 13 , en 12 , the switch control circuit  90  closes the switches S C5  to SC C9  corresponding to the large-level region (between reference voltages V 2  and V 3 ) of the analog input signal A in  as shown in FIG.  16 . 
     The second A/D conversion is executed by the comparators  23  to  25  and the second encoder  51 , yielding the middle 2-bit digital output en 23 , en 22 . When the analog input signal A in  belongs to the middle-level region of between the reference voltages Vd and Ve, the output signal CM 23  of the comparator  20  becomes an L level or “ 0 ” and the output signals CM 24  and CM 25  of the comparators  24  and  25  become an H level or “ 1 ”. Based on the individual output signals CM 23 , CM 24  and CM 25  and the digital output en 12 , the second encoder  51  determines that the analog input signal A in  belongs to the middle-level region of Vd to Ve, and outputs the digital output en 23  of “ 1 ” and the digital output en 22  of “ 0 ” as shown in FIG.  7 . Based on this middle 2-bit digital output en 23 , en 22 , and the digital output en 12 , the switch control circuit  100  closes the switches S F1  and S F2  corresponding to the middle-level region (between reference voltages Vd and Ve) of the analog input signal A in  as shown in FIG.  18 . 
     The third A/D conversion is executed by the comparators  30  to  32  and the third encoder  60 , yielding the lower 2-bit digital output en 31 , en 30 . When the analog input signal A in  belongs to the small-level region of the reference voltage Vi or above, the output signals CM 30 , CM 31  and CM 32  of the individual comparators  30  to  32  all become “ 1 ”. Based on the individual output signals CM 30 , CM 31  and CM 32  and the digital output en 10 , the third encoder  60  determines that the analog input signal A in  belongs to the medium-level region between Vd and Ve, and outputs the digital output en 31  of “ 1 ” and the digital output en 30  of “ 1 ” as shown in FIG.  9 . As a result, the analog input signal A in  is converted into a 6-bit digital signal having a value of “011011” in accordance with the individual digital outputs en 13 , en 12 , en 24 , en 23 , en 31  and en 30 . 
     According to this embodiment, as described above, a 6-bit A/D converter can be constituted of sixteen resistors R, four sets of switches S A  to S D  each consisting of five switches, four sets of switches S E  to S H  each consisting of two switches, for a total of twenty-five switches, nine comparators  15  to  13 ,  23  to  25  and  30  to  32  and four capacitors C 1  to C 4 . It is apparent that the 6-bit A/D converter of this embodiment can have a significantly smaller circuit scale than the conventional 6-bit 2-step parallel A/D converter. Since this embodiment needs fewer comparators than the prior art, the consumed power will be reduced. The reduction in the circuit scale and the consumed power would become more prominent as the number of bits of an A/D converter having the structure of this embodiment is increased. 
     The present invention is not limited to the above-described embodiment, but may be modified in various manners as follows. 
     1) The capacitors C 1  to C 4  may be replaced with four resistors having the same resistance. In this case, the series-connected resistors are connected in parallel to the resistors R 1 , so that the replaced resistors should have a sufficiently large resistance to avoid influencing the resistance of the string resistance R 1 . 
     2) In the above embodiment, the third A/D conversion is performed on three bits or more. In this case, the third encoder  60  should be modified to have eight series-connected capacitors instead of the four capacitors C 1  to C 4  and seven comparators instead of the three comparators  30  to  32 . This modification allows the third A/D conversion to be performed on three bits. Accordingly, a total of seven bits can be subjected to A/D conversion in three A/D converting operations. If the third encoder  60  is modified to have sixteen series-connected capacitors replacing the four capacitors C 1  to C 4  and fifteen comparators replacing the three comparators  30  to  32  in the above embodiment, the third A/D conversion can be performed on four bits. Accordingly, a total of eight bits can be resolved in three A/D converting operations. By increasing the number of bits in the third A/D conversion in this manner, an A/D converter which can perform A/D conversion on a greater number of bits can be accomplished. 
     3) In the above embodiment, the first AD conversion may be combined with the third A/D conversion, thus realizing a 4-bit A/D converter. FIG. 20 presents a circuit diagram of this 4-bit A/D converter. The same reference numerals as used for the embodiment shown in FIG. 3 are given to those identical or corresponding components of this embodiment. In this case, while this embodiment uses the same number of comparators as used in the prior art shown in FIG. 1, the number of the resistors R 1  and the number of the switches can be reduced. 
     4) If the comparators  15  to  13 ,  23  to  25  and  30  to  32  are given a sample hold function, the sample hold circuit  80  becomes unnecessary. 
     5) The resistor string consisting of the resistors R may be replaced with a capacitor string consisting of series-connected capacitors having the same capacitance. 
     6) The above cases (1) to (5) may be combined as needed.