Abstract:
A floating-point normalizing circuit is adapted to receive two multi-bit numbers so as to generate a signal indicative of a shift amount for floating-point normalization. The normalizing comprises a plurality of unitary circuits each including a pair of binary inputs, a unitary shift signal output, a carry input, a carry output internally but disconnectably connected to the carry input. These unitary circuits are adapted to receive at their binary inputs different digit position bits of each of the two input numbers, respectively, but each of the unitary circuits receives at its one pair of binary inputs the same digit position bits of the two input numbers. The carry input of each unitary circuit is connected to the carry output of an adjacent more significant digit unitary circuit so that a carry signal is transferred from a more significant digit unitary circuit to a less significant digit unitary circuit. Each of the unitary circuit generates a unitary shift signal when a predetermined logic level is detected in at least one input of the binary inputs and a predetermined carry signal is received at its carry input, and also disconnects the internal connection between the carry input and output, whereby the position of the unitary circuit generating the unitary shift signal is indicative of the amount of required shift for normalization.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a high-speed floating-point normalizing circuit which can be easily incorporated in an integrated circuit. 
     2. Description of Related Art 
     In general, a floating-point arithmetic operation needs a floating-point normalization. FIG. 1 shows one example of the conventional floating-point arithmetic circuit which has a floating-point normalizing circuit. As shown in FIG. 1, the floating-point normalizing circuit 10 includes a comparator (CMP) 12 receiving two multi-bit numbers A and B to determine which is larger, A or B. This comparator 12 controls a multiplexer (MUX) 14 which also receives the two input numbers A and B, so that the multiplexor 14 outputs a larger one of the two input numbers to a shift and count circuit (SAC) 16. This SAC circuit 16 leftwardly shifts the input number until the shifted number has a nonzero leftmost digit, i.e., &#34;1&#34; at the most significant digit, and at the same time the SAC circuit 16 counts the amount of the shift, Thus, the SAC circuit 16 outputs the result of the count to an encoder 18, which is in turn converts the counted value into an exponent data in a floating-point representation. Further, the output of the SAC circuit 16 is supplied to a pair of shifters 20 and 22 which receive the input numbers A and B, respectively, so that the respective shifters shift the respective input numbers the same amount indicated by the SAC circuit 16. The two numbers A and B thus shifted are outputted from the respective shifters 20 and 22 to a processing unit 24, which in turn executes a designated arithmetic operation to the two input numbers so as to output the result of the arithmetic operation as a fraction or mantissa in a floating-point representation. 
     As seen from the above, the conventional floating-point normalizing circuit includes three different circuits, i.e., the comparator, the multiplexor and the shift and count circuit, and therefore, the normalizing circuit is inevitably complicated. In addition, the normalizing output is generated through the three sequential steps, i.e., the comparison, the selection and the shift, and so, the operation speed is not so fast. Therefore, the conventional floating-point normalizing circuit is not suitable for a high speed operation circuit in the form of an integrated circuit. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a floating-point normalizing circuit which has dissolved the aforementioned drawbacks of the conventional one. 
     Another object of the present invention is to provide a floating-point normalizing circuit of a simple structure which can operate at a high speed. 
     Still another object of the present invention is to provide a floating-point normalizing circuit including only circuits of the same structure, so that the normalizing circuit can be easily assembled in an integrated circuit. 
     A further object of the present invention is to provide a floating-point normalizing circuit consisting of only the same structure circuits arranged to receive the multi-bit number in parallel, so that the normalizing circuit can operate at a high speed. 
     A still further object of the present invention is to provide a floating-point arithmetic circuit incorporating such a floating-point normalizing circuit. 
     The above and other objects of the present invention are achieved in accordance with the present invention by a floating-point normalizing circuit adapted to receive two multi-bit numbers so as to generate a signal indicative of a shift amount for floating-point normalization, comprising a plurality of unitary circuits each including a pair of binary inputs, a unitary shift signal output, a carry input, and a carry output internally and disconnectably connected to the carry input, the unitary circuits being adapted to receive at their binary inputs different digit position bits of each of the two input numbers, respectively, but each of the unitary circuits receiving at its one pair of binary inputs the same digit position bits of the two input numbers, the carry input of each unitary circuit being connected to the carry output of an adjacent significant digit unitary circuit so that a carry signal is transferred from a more significant digit unitary circuit to a less significant digit unitary circuit, each of the unitary circuit functioning to disconnect the internal connection between the carry input and output and to generate a unitary shift signal when a predetermined logic level is detected in at least one input of the binary inputs and a predetermined carry signal is received at its carry input, whereby the position of the unitary circuit generating the unitary shift signal is indicative of the amount of required shift for normalization. 
     In one embodiment, each of the unitary circuits is adapted to generate a signal indicative of the comparison result of a pair of bits inputted to its binary inputs, and the normalizing circuit further includes a logic circuit receiving the comparison signals from the respective unitary circuits so as to generate a general comparison signal indicating which of the two numbers is large. 
     Further, each of the unitary circuits includes a transfer gate connected between the carry input and the carry output, and comparison means connected to the carry input and one of the binary inputs to control the transfer gate and to generate the unitary shift signal in accordance with a logical relation between the carry input and the one binary input. 
     Specifically, the comparison means includes an NAND gate having a first input connected to the carry input and a second input connected to receive the one binary input. An output of the NAND gate is connected to a control input of the transfer gate. In one embodiment, the other input of the NAND gate is directly connected to the one binary input. Alternatively, each unitary circuit includes an OR gate having two inputs connected to the pair of binary inputs, respectively, and the other input of the NAND gate is connected to an output of the OR gate. 
     The comparison means also includes an inverter connected at its input to the output of the NAND gate and at its output to the unitary shift signal output. The comparison means also includes a switching transistor connected between the carry output and ground and controlled by the output of the inverter. 
     In a preferred embodiment, each of the unitary circuit further includes a second comparison means receiving any one of the two binary inputs and a signal introduced from the carry input so as to generate a comparison output indicating which of the two binary input is large. In one embodiment, the second comparison means includes a NOR gate having a first input connected to any one of the two binary inputs and a second input connected to the output of the first comparison means, so that the NOR gate generates the comparison output from its output terminal. In another embodiment, the second comparison means includes an AND gate having a first input connected to any one of the two binary inputs and second input connected directly to the carry input, so that the AND gate generates the comparison output from its output terminal. 
     According to another aspect of the present ivnention there is provided a floating-point arithmetic circuit adapted to receive at least two multi-bit numbers, which includes a normalizing circuit receiving the two multi-bit numbers to generate a shift amount signal, a pair of shifters receiving the two multi-bit numbers, respectively, to shift the respective input numbers in accordance with the shift amount signal, a processing unit receiving the outputs of the pair of shifters to carry out a predetermined arithmetic operation to the inputted numbers and to output the result of operation in the form of a mantissa, and an encoder receiving the shift amount signal to generate an exponent part for the above mentioned arithmetic operation. The normalizing caircuit comprises a plurality of unitary circuits each including a pair of binary inputs, a unitary shift signal output, a carry input, and a carry output internally and disconnectably connected to the carry input. The unitary circuits are adapted to receive at their binary inputs different digit position bits of each of the two input numbers, respectively, but each of the unitary circuits receives at its one pair of binary inputs the same digit position bits of the two input numbers. The carry input of each unitary circuit is connected to the carry output of an adjacent more significant digit unitary circuit so that a carry signal is transferred from a more significant digit unitary circuit to a less significant digit unitary circuit. Each of the unitary circuit functions to disconnect the internal connection between the carry input and output and to generate a unitary shift signal when a predetermined logic level is detected in at least one input of the binary inputs and a predetermined carry signal is received at its carry input, whereby the position of the unitary circuit generating the unitary shift signal is indicative of the amount of required shift for normalization. 
     The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of the conventional floating-point arithmetic circuit; 
     FIG. 2 is a block diagram of one embodiment of the floating-point normalizing circuit in accordance with the present invention; 
     FIG. 3 is a circuit diagram of a unitary circuit which can be used in the floating-point normalizing circuit shown in FIG. 2; 
     FIG. 4 is a diagram similar to FIG. 2 but showing another embodiment of the normalizing circuit; and 
     FIG. 5 is a diagram similar to FIG. 3 but showing another embodiment of the unitary circuit which can be used in the normalizing circuit shown in FIG. 4. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 2, the floating-point normalizing circuit for two four-bit numbers, which embodies the present invention, comprises four unitary circuits 30 arranged to in parallel receive two four-bit numbers A and B which can be expressed as follows: 
     
         A=a.sub.4 ×2.sup.3 +a.sub.3 ×2.sup.2 +a.sub.2 ×2.sup.1 +a.sub.1 
    
     
         B=b.sub.4 ×2.sup.3 +b.sub.3 ×2.sup.2 +b.sub.2 ×2.sup.1 +b.sub.1 
    
     The shown normalizing circuit detects the most significant digit of &#34;1&#34; in the input two four-bit numbers A and B, and compares the effective digit numbers of the two input numbers to each other. For this purpose, the unitary circuit 30 receive difforont digits of each of the input numbers A and B, respectively, and each of the unitary circuits 30 receives the same digit (a 4  and b 4 , a 3  and b 3 , a 2  and b 2 , and a 1  and b 1 ) of the input numbers A and B. Further, each of unitary circuits 30 includes a carry input CI i  receiving a carry signal from an adjacent unitary circuit of more significant digit. But, the most significant digit (leftmost) circuit 30 receives at its carry input CI 4  a reference voltage Vcc indicative of the logical value &#34;1&#34;. Also, each unitary circuit has a carry output CO i  connected to the carry input of an adjacent less significant digit unitary circuit. Further, each unitary circuit has a unitary comparison output CMP i  and a unitary shift output E i . 
     With this arrangement, the carry signal of &#34;1&#34; is transferred to the most significant digit unitary circuit UNIT 4 towards the least significant digit unitary circuit UNIT 1, and in the course of the transmission of the carry signal, the most significant digit unitary circuit of unitary circuits receiving a nonzero binary signal, generates a unitary shift signal E i  and at the same time changes the carry signal from &#34;1&#34; to &#34;0&#34;, so that, less significant digit unitary circuits receiving a nonzero binary signal will not generate a unitary shift signal E i . Thus, the position of the unitary circuit generating the unitary shift signal is indicative of the amount of required shift for normalization. Therefore, the unitary comparison outputs CMP i  of all the unitary circuits 30 are fed to an OR gate G o , which in turn outputs a general comparison output CMP 0  indicating the result of the comparison of the effective digit numbers D A  and D B  of the input numbers A and B. Further, only the unitary circuit generating the unitary shift signal, also generates a unitary comparison signal CMP i  indicating which of the two binary inputs a i  and b i  is large. Thus, the unitary shift outputs E i  of all the unitary circuits 30 are supplied as the shift amount data to the encoder 18 and the shifters 20 and 22 as shown in FIG. 1. 
     Turning to FIG. 3, there is shown one example of the unitary circuit 30. The circuit 30 includes an OR gate G 1  receiving the bits a i  and b i  at the same digit position of the input numbers A and B. An output of the OR gate G 1  is connected to one input of a NAND gate G 2  whose other input is connected to a carry input CI i . The NAND gate G 2  is connected at its output through a node Pφ i  to a gate electrode of a transfer gate transistor N Ti  connected between the carry input CI i  and a carry output CO i . Further, the output of the NAND gate G 2  is connected to an input of an inverter G 3 , whose output is connected to a unitary shift output E 1  and a gate electrode of a switching transistor N i . This transistor N i  is connected between the carry output CO i  and ground. In addition, the output of the NAND gate G 2  is connected to one input of a NOR gate G 4 , which is connected at its other input to the binary input b i . An output of the NOR gate G 4  is connected to a unitary comparison output CMP i . 
     Next, operation will be explained with reference to an exemplary case of A=0101 and B=0011. 
     Namely, the most significant digit unitary circuit UNIT 4 receives a 4  of &#34;0&#34; b 4  of &#34;0&#34;. Therefore, the OR gate G 1  outputs the logic &#34;0&#34;. On the other hand, since the carry input CI 4  is clamped to the logic &#34;1&#34; (i.e., Vcc), the output of the NAND gate G 2 , i.e., the node Pφ 4  is brought to the logic &#34;1&#34;. Therefore, the transfer gate N Ti  is put in an ON condition, and so, the potential at the carry input CI 4  is transferred to the carry output CO 4 . Namely, the carry output CO 4  is put at the logic &#34;1&#34;. 
     Further, since the node Pφ 4  is at the logic &#34;1&#34;, the inverter G 3  outputs the logic &#34;0&#34;, and therefore, the transistor N 4  is maintained off. Accordingly, the shift output E 4  is at the logic &#34;0&#34;. In addition, since the binary input b 4  is at the logic &#34;0&#34; and the node Pφ 4  is at the logic &#34;1&#34;, the NOR gate G 4  outputs the comparison output CMP 4  of &#34;0&#34;. 
     The next more significant digit unitary circuit UNIT 3 receives a 3  of &#34;1&#34;, b 3  of &#34;0&#34; and CI 3  (=CO 4 ) of &#34;1&#34;. Therefore, the OR gate G 1  outputs the logic &#34;1&#34;, and so, the NAND gate G 2  generates the logic &#34;0&#34; at the node Pφ 3 . Accordingly, the transfer gate N Ti  is turned off, and the inverter G 3  outputs the logic &#34;1&#34; as the shift output E 3 , so that the transistor N 3  is turned on so as to generate the carry output CO 3  of &#34;0&#34;. On the other hand since the NOR gate G 4  receives the binary input b 3  of &#34;0&#34; and the node signal Pφ 3  of &#34;0&#34;, it generates the comparison output CMP 3  of &#34;1&#34;. Thus, the OR gate G o  generates the general comparison output CMP 0  of &#34;1&#34; which means D A  &gt;D B . 
     The third more significant digit unitary circuit UNIT 2 receives a 2  of &#34;0&#34;, b 2  of &#34;1&#34; and CI 2  (=CO 3 ) of &#34;0&#34;. Since CI 2  =&#34;0&#34;, the NAND gate G 2  generates the logic &#34;1&#34; at the node Pφ 2 , and so, the transfer gate N T2  is put ON, so that the CI 2  of &#34;0&#34; is transferred to the carry output CO 2 . In addition, the inverter G 3  generates the shift output E 2  of &#34;0&#34;, and the NOR gate G 4  produces the comparison output CMP 2  of &#34;0&#34;. 
     The least significant digit unitary circuit UNIT 1 receives a 1  of &#34;1&#34; and b 1  of &#34;1&#34;. But, since the carry input CI 1  is at the logic &#34;0&#34;, the carry output CO 1 , the comparison output CMP 1  and the shift output E 1  are brought into the logic &#34;0&#34;, similarly to the case of UNIT 2. 
     Namely, the result is E=0100, and CMP 0  =1 indicating A&gt;D (D A  &gt;D B ). 
     The following Table I shows the logical relation as mentioned above. 
     
                       TABLE I______________________________________     bit No.Point       4     3            2   1______________________________________a.sub.i     0     1            0   1b.sub.i     0     0            1   1CI.sub.i    1     1            0   0CO.sub.i    1     0            0   0E.sub.i     0     1            0   0Pφ.sub.i       1     0            1   1CMP.sub.i   0     1            0   0______________________________________ 
    
     As seen from the above, since the carry input CI 4  of the most significant digit (leftmost) unitary circuit UNIT 4 is clamped to the logic &#34;1&#34;, the carry signal of &#34;1&#34; is transferred downwardly to a unitary circuit which receives the logic &#34;1&#34; at either or both of the binary inputs a i  and b i , which unitary circuit will then outputs the carry output CO i  of &#34;0&#34;. This carry signal of &#34;0&#34; is transferred to the least significant digit (rightmost) unitary circuit UNIT 1. At this time, only the above mentioned unitary circuit which has received the logic &#34;1&#34; at its binary inputs, generates the shift output E i  of &#34;1&#34;, and therefore, the position of the shift output &#34;1&#34; indicates the necessary amount of shift for normalization. 
     Furthermore, when the carry input CI i  is at the logic &#34;1&#34;, the unitary circuit generates the comparison output CMP i  of &#34;1&#34; if a i  =1 and b i  =0. Otherwise, the CMP i  of &#34;0&#34; is outputted. Therefore, the general comparison output CMP o  of &#34;1&#34; (i.e., a high logical level) indicates D A  &gt;D B , and CMP 0  of &#34;0&#34; (i.e., a low logical level) means D A  ≦D B . 
     Further, with connection between the carry output CO i   and the carry input CO i-1  in each pair of adjacent unitary circuits, the logic &#34;1&#34; is transferred from the most significant digit unitary unit toward a less significant digit unitary circuit. In the course of the carry signal transmission, the carry signal &#34;1&#34; is changed to &#34;0&#34; in the most significant digit unitary circuit of the unitary circuits that detect the binary value of &#34;1&#34; at the binary inputs a i  and b i . Therefore, the NOR gate G 4  which receives the binary input b i  and the output of the NAND gate G 2  (the node Pφ i ), will generate a signal indicative of whether or not the logic &#34;1&#34; appears only the input a i  of the unitary circuit in which the carry signal is changed from &#34;1&#34; to &#34;0&#34;. Accordingly, if another NOR gate is provided to receive the binary input a i   and the signal of the node P 0i , the additional gate will generate a signal indicating whether or not the logic &#34;1&#34; appears only the input &#34;b i  &#34;. If such a signal is compared with the CMP i , it is possible to discriminate three conditions D A  &gt;D B , D A  =D B  and D A  &lt;D B . 
     Referring to FIG. 4, there is shown a modification of the normalizing circuit, which comprises four unitary circuits 40 as shown in FIG. 5. In the unitary circuit 40, the binary input a i  is directly connected to the one input of the NAND gate G 2 , and in place of the OR gate G 1  and the NOR gate G 4 , an AND gate G 5  is provided to receive the carry input CI i  and the binary input b i  and to output the comparison output CMP i . 
     As seen from the above, the circuit of FIG. 5 is adapted to detect the binary value &#34;1&#34; of only the input a i , i.e., only the input number A. 
     Next, operation of the normalizing circuit shown in FIG. 4 will be explained with reference to the above mentioned exemplary case of A=0101 and B=0011. 
     Namely, the most significant digit unitary circuit UNIT 4 receives a 4  of &#34;0&#34; b 4  of &#34;0&#34;. On the other hand, the carry input CI 4  is clamped to the logic &#34;1&#34;. Therefore, the NAND gate G 2  outputs a signal of the logic &#34;1&#34;. Therefore, the transfer gate N Ti  is put in an ON condition, and so, the carry signal of &#34;1&#34; is transferred from the carry input CI 4  to the carry output CO 4 . 
     Further, since the output of the NAND gate G 2  is at the logic &#34;1&#34;, the inverter G 3  outputs the logic &#34;0&#34;, and therefore, the transistor N 4  is maintained off, so that the shift output E 4  is at the logic &#34;0&#34;. In addition, since the binary input b 4  is at the logic &#34;0&#34; and the carry input CI i   is at the logic &#34;1&#34;, the AND gate G 5  outputs the comparison output CMP 4  of &#34;0&#34;. 
     The next more significant digit unitary circuit UNIT 3 receives a 3  of &#34;1&#34;, b 3  of &#34;0&#34; and CI 3  (=CO 4 ) of &#34;1&#34;. Therefore, the NAND gate G 2  generates the logic &#34;0&#34;. Accordingly, the transfer gate N T3  is turned off, and the inverter G 3  outputs the shift output E 3  of the logic &#34;1&#34;, so that the transistor N 3  is turned on so as to generate the carry output CO 3  of &#34;0&#34;. On the other hand, since the AND gate G 5  receives the binary input b 3  of &#34;0&#34; and the carry input signal CI 3  of &#34;0&#34;, it generates the comparison output CMP 3  of &#34;0&#34;. 
     The third more significant digit unitary circuit UNIT 2 receives a 2  of &#34;0&#34;, b 2  of &#34;1&#34; and CI 2  (=CO 3 ) of &#34;0&#34;. Since CI 2  =&#34;0&#34;, the AND gate G 5  produces the comparison output CMP 2  of &#34;0&#34;, and the NAND gate G 2  generates the logic &#34;1&#34;, and so, the transfer gate N T2  is put ON, so that the CI 2  of &#34;0&#34; is transferred to the carry output CO 2 . In addition, the inverter G 3  generates the shift output E 2  of &#34;0&#34;. 
     The least significant digit unitary circuit UNIT 1 receives a 1  of &#34;1&#34; and b 1  of &#34;1&#34;. But, since the carry signal applied to CI 1  is already at the logic &#34;0&#34;, the carry output CO 1 , the comparison output CMP 1  and the shift output E 1  are brought into the logic &#34;0&#34;, similarly to the case of UNIT 2. 
     Namely, the result of E=0100, and the NOR gate G 0  &#39;  outputs CMP 0  of &#34;1&#34;. 
     The following Table II shows the logical relation as mentioned above. 
     
                       TABLE II______________________________________     bit No.Point       4     3            2   1______________________________________a.sub.i     0     1            0   1b.sub.i     0     0            1   1CI.sub.i    1     1            0   0CO.sub.i    1     0            0   0E.sub.i     0     1            0   0CMP.sub.i   0     0            0   0______________________________________ 
    
     As seen from the above, since the carry input CI 4  of the most significant digit (leftmost) unitary circuit UNIT 4 is clamped to the logic &#34;1&#34;, the carry signl of &#34;1&#34; is transferred downwardly to a unitary circuit which receives the logic &#34;1&#34; at the binary inputs a i , which unitary circuit will then outputs the carry output CO i  of &#34;0&#34;. This carry signal of &#34;0&#34; is transferred through an adjacent less significant digit unitary circuit to the least significant digit (rightmost) unitary circuit UNIT 1. At this time, only the above mentioned unitary circuit which has received the logic &#34;1&#34; at its binary input a i , generates the shift output E i  of &#34;1&#34;, and therefore, the position of the shift output E i  of &#34;1&#34; indicates the necessary amount of shift for normalization. 
     As seen from the above, since the circuit of FIG. 5 detects only the binary input a i  to control the transmission of the carry signal, the logical product of the carry signal CI i  and the other binary input b i  is obtained by the AND gate G 5  to compare the digit numbers of the numbers A and B. The AND gate G 5  operates to consequently detect the condition D A  ≦D B , differently from the first embodiment. Accordingly, the outputs CMP i  are inputted to the NOR gate G 0  &#39;, which generates the signal of &#34;1&#34; under the condition D A  &gt;D B  and &#34;0&#34; under the condition D A  ≦D B , similarly to the first embodiment. 
     The invention has thus been shown and described with reference to specific embodiments. However, it should be noted that the invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.