Abstract:
An embedded memory on an integrated circuit has a memory cell array equipped with replacement cells and mapping logic for electronically substituting the replacement cells for defective cells at at least one location in the memory cell array. The memory also has programmable links for storing redundancy information in a compressed format, and decoding logic for decompressing the redundancy information and controlling the mapping logic.

Description:
FIELD  
         [0001]    The present document relates to the field of monolithic semiconductor storage devices having redundancy. In particular, the document relates to compression of redundancy control information in embedded memories, including cache memories, such as are commonly found on processor and other logical integrated circuits.  
         BACKGROUND  
         [0002]    Many available integrated circuits contain large memory arrays. During manufacture of integrated circuits, defects can arise in such memory arrays. It is known that many of these defects, known as “point defects,” prevent function of only a small number of cells. Many other defects, such as row or column defects, can arise in memory arrays and will prevent operation of cells in a particular column or row of the large memory array while permitting operation of other cells in the design.  
           [0003]    Memory arrays included in integrated circuits with substantial non-memory function are known herein as embedded memory arrays. Embedded memory arrays include cache memory, such as is often found in processor integrated circuits.  
           [0004]    Integrated circuits having unrepaired and/or unbypassed defects in embedded memory arrays are typically of no value in the marketplace. It is desirable to repair and/or bypass defects in embedded memory arrays to improve yield and reduce costs of functional circuits. The larger the percentage of die area occupied by memory arrays, the more likely the array is to have defects.  
           [0005]    Many memory arrays available in integrated circuits are equipped with a replacement group of cells intended to be electronically substituted for defective cells in the array; thereby repairing defects in the arrays. These replacement cells may take the form of additional cell rows in an array; these cell rows are accessed in place of rows having defective cells. Replacement cells may also take the form of extra columns in an array; data from these columns is substituted for data from defective columns. Block-organized memories may have entire replacement blocks, where an entire block of defective memory can be substituted with good memory. Replacement cells may also be organized as a small memory having mapping logic for substituting cells of the small memory for defective cells in a larger array. Provision of replacement cells in a memory system is known to significantly improve memory yield, thereby reducing production cost, despite a small die size increase.  
           [0006]    With all these techniques, replacement cells must be variably mapped onto the larger memory array of the embedded memory. This mapping requires storage of replacement-cell, column, row, or block mapping information within the integrated circuit. This required replacement-cell, column, row, or block, mapping information is known herein as redundancy information.  
           [0007]    It is known that memory defects may be “hard” defects, where cells fail to function under all conditions. Other defects may be speed or temperature related, where cells fail to function only under certain operating conditions. It is therefore desirable to store redundancy information in nonvolatile form within the integrated circuit rather than deriving this information from self-test results at system boot time.  
           [0008]    Most integrated circuit processes used for construction of static or dynamic random access memory (SRAM or DRAM) embedded memory arrays do not allow for fabrication of EEPROM or UV-EPROM cells for storage of redundancy information. Storage of redundancy information in nonvolatile form within integrated circuits made on these processes has been accomplished with laser-programmed or fusible link technologies; both types are herein known as programmable links. Laser-programmed links require large die area such that a production machine can locate and program selected links since laser spot size is large compared with line widths obtainable on modern submicron fabrication processes. Fusible-links also require substantial die area for each fusible link, since each link requires associated passivation openings, high-current drivers for fusing the link, and other associated components.  
           [0009]    It is therefore desirable to minimize the number of programmable links required to store redundancy information on an integrated circuit.  
           [0010]    Many integrated circuits, including processor integrated circuits, contain multiple embedded memory arrays of size sufficiently large that die yields can be improved by providing redundant cells, mapping hardware, and programmable links.  
           [0011]    It is common that embedded arrays are organized with a number of columns that is not a power of two. In particular, modern processors often incorporate multiple levels of cache memory, where each cache memory has separate embedded memory arrays for data and for cache tag information. Cache tag information memory arrays are often organized as memory having word length that is not a power of two. Recent processor designs often implement error correction coding (ECC) for cache data memory to protect against soft errors; adding ECC to a memory having word length equal to a power of two generally results in a memory having an internal word length that is not a power of two.  
         SUMMARY  
         [0012]    An embedded memory on an integrated circuit is equipped with replacement cells and has redundancy information for controlling substitution of the replacement cells for defective cells in the embedded memory.  
           [0013]    The redundancy information is stored within the integrated circuit in compressed form. On-chip decompression logic is provided to decompress the redundancy information so that substitution of replacement cells for defective cells can take place automatically on the integrated circuit.  
           [0014]    In a particular embodiment, the embedded memory serves as a portion of a cache memory array within a processor integrated circuit. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    [0015]FIG. 1 is an abbreviated, exemplary, block diagram of a processor integrated circuit having embedded memories serving as cache.  
         [0016]    [0016]FIG. 2 is an abbreviated, exemplary, block diagram of a cache memory having redundancy information, showing data and tag memories, redundancy information storage, and decompression logic.  
         [0017]    [0017]FIG. 3 is a flowchart of a decompressor for compressed redundancy information.  
         [0018]    [0018]FIG. 4 is an exemplary block diagram of on-chip decompression logic for decompressing redundancy information. 
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0019]    [0019]FIG. 1 is a block diagram of a modern processor integrated circuit  100  having embedded cache memories  102 ,  104 . Integrated circuit  100  has one or more processors  106 , each connected to first level instruction and data caches  102 . First level caches  102  may implement separate instruction and data caches, or may implement combined instruction-data cache. Memory references that miss in first level caches  102  are passed by interfaces  108  to second level combined instruction-and-data cache  104 . Memory references that hit in second level cache  104  are passed on to a memory bus interface  110 , and passed to higher-level memory. There may be a third, sometimes even a fourth, level cache in the system; processor integrated circuits  100  are known that implement a third level cache on the processor integrated circuit  100 . Processor integrated circuits  100  are known where the cache memory arrays, such as cache memories  102 ,  104 , are a substantial fraction—sometimes as much as three quarters—of total active die area. Manufacturing yield of these large and expensive processor integrated circuits is improved if these memories are equipped with replacement cells electrically mapable to replace defective cells of the array.  
         [0020]    [0020]FIG. 2 illustrates read pathways of a typical multiple-way cache memory system  200 , such as may be embodied in embedded first and higher level cache memories  102  and  104  of a processor integrated circuit  100 . An address  202  is broken into a higher address part  204  and a tag address part  206 . There may be additional address parts such as an address of a memory word in a cache line. The tag address part  204  is passed to a tag address decoder  210 , which addresses a tag memory array  212  and any replacement-cell columns  214  that are provided. Tag memory  212  and replacement-cell columns  214  are read to redundancy logic  216 , where defective tag memory  212  columns are replaced with replacement-cell columns  214 .  
         [0021]    Corrected cache tag information from redundancy logic  216  has multiple fields, including way one address  218 , way two address  220 , way one flags  222 , and way two flags  224 . The high address part  204  is compared by comparators  226  and  228  against the way addresses  218 ,  220 . Comparator  226 ,  228 , results and flags  222 ,  224 , are used by hit logic  230  to determine if the address has scored a hit in the cache, and if so, which ‘way’ of the cache has hit. A cache having multiple ways, as illustrated, is a set-associative cache.  
         [0022]    The tag address part  204 , and hit logic  230  ‘way-hit’ information, is used by cache data address decoder  232  to address cache data memory  234  and replacement-cell columns  236 . Data read from cache data memory  234  and replacement-cell columns  236  is read through redundancy logic  238  where data from hard-failed columns of cache data memory  234  are replaced with data from replacement-cell columns  236 . Data from redundancy logic  238  is then corrected for soft errors in error-correcting code logic  240 .  
         [0023]    Tag memory redundancy logic  216  is controlled by decompressed redundancy information provided by decompressor  246  from compressed redundancy information  248  stored in programmable links on the integrated circuit. Similarly, cache memory redundancy logic  238  is controlled by decompressed redundancy information provided by decompressor  250  from compressed redundancy information  252  stored in programmable links.  
         [0024]    Consider a processor integrated circuit where the word length of corrected data  254  from error-correcting code logic  240  is sixty-four bits; data from redundancy logic  238  is, in this embodiment seventy-two bits wide. Seven bits are therefore required to control which column is replaced by each column of replacement columns  236 . A disable code or a disable bit may be used to indicate that a particular column of replacement cells is unused. Assume that there are two replacement columns. Uncompressed redundancy information therefore requires fourteen to sixteen bits. The total number of possible combinations of replacement-cell column programming is therefore seventy-one squared plus seventy-three (with enable information), since it is not necessary to replace any one column with both replacement cell columns. This is only five thousand one hundred fourteen combinations which can be encoded in compressed form in thirteen bits. Similarly, if four replacement-cell columns are provided, uncompressed redundancy information requires thirty-two bits, while this information can be represented in compressed form in twenty-three bits. Similarly, the width of tag memory  212  is unlikely to be a power of two, and is therefore subject to potential compression.  
         [0025]    In an alternative embodiment, the word length of corrected data  254  from error-correcting code logic  240  is thirty-two bits; while data from redundancy logic  238  is thirty-eight bits wide. Six bits are required for to direct substitution of each replacement-cell column; therefore two replacement columns would require twelve redundancy bits. This information can be encoded in compressed form using ten bits.  
         [0026]    The width of corrected data, and width of tag memories, expressed herein are by way of example only. It is expected that the invention is applicable to memories of different widths, so long as memory width is not an exact power of two.  
         [0027]    Since the compression efficiency increases with the number of fields of redundancy information compressed, in an alternative embodiment decompressor  250  and compressed redundancy information  252  are deleted. In this embodiment, redundancy logic  238  is controlled by additional fields of decompressed redundancy information provided by decompressor  246  from compressed redundancy information  248  stored in programmable links.  
         [0028]    In a particular embodiment of the processor integrated circuit having two columns of replacement cells  236  associated with cache data memory  234 , the compressed redundancy information  252  is encoded according to the formula: 
         encoded=−(red0*red0)/2+(2*io_bits+3)*red0/2+red1−red0 
         [0029]    where:  
         [0030]    encoded=is the encoded redundancy information,  
         [0031]    red0=the column at which the first replacement cell column is substituted into the array, and  
         [0032]    red1=the column at which the second replacement cell column is substituted into the array, and red0 is less than red1.  
         [0033]    In an alternative embodiment having three replacement columns, the redundancy information is encoded according to the formula: 
         encoded=−red1*red1/2+(2*io_bits+3)*red0/2+red2−red1+(red0*red0/3−(io_bits+1)*red0+2/3+(io_bits+2)*io_bits)*red0/2 
         [0034]    where:  
         [0035]    encoded=is the encoded redundancy information,  
         [0036]    red0=the column at which the first replacement cell column is substituted into the array,  
         [0037]    red1=the column at which the second replacement cell column is substituted into the array, and  
         [0038]    red2=the column at which the third replacement cell column is substituted into the array.  
         [0039]    Redundancy information encoded according to this formula can be decoded by a digital state machine executing according to the exemplary flowchart of FIG. 3. In one embodiment, this state machine is implemented in firmware executed at boot time of the system. In another embodiment, this state machine is implemented in dedicated hardware. Alternative embodiments also include decoding the compressed redundancy information in logic gates or a programmed logic array (PLA).  
         [0040]    In the flowchart of FIG. 3, IO is the number of columns at which the first replacement cell column can be mapped onto the array, cnt is a loop counter initialized  302  to zero, and EN is a variable initially set to the encoded redundancy information. A loop is executed, where for each pass  304  of the loop the following statements are executed: 
         r0=cnt 
           r 1= en+cnt   
           en=en−io+cnt− 1 
           cnt=cnt+ 1 
         [0041]    The process ceases when either EN becomes negative  306  or the loop counter cnt  308  passes the number of encoded redundancy bits.  
         [0042]    [0042]FIG. 4 is an exemplary block diagram of on-chip decompression logic  400  such as may be used for decompressing redundancy information in implementations performing decompression in hardware instead of in firmware on a processor. This logic has four registers, including one initialized with the initial encoded number  402 , one for holding a decoded R0 redundancy code value  404 , one for holding a decoded R1 redundancy code value  406 , and another  408  initialized to the number of columns over which the redundancy codes may position the replacement columns. A comparator  410  and arithmetic-logic unit (ALU)  412  are also provided, as is a loop counter  414  and control logic  416 . The on-chip decompression logic  400  executes the method of FIG. 3 upon system boot.  
         [0043]    It is anticipated that alternative compression algorithms may be used without departing from the spirit of the invention.  
         [0044]    While the foregoing has been particularly shown and described with reference to particular embodiments thereof, it will be understood by those skilled in the art that various other changes in the form and details may be made without departing from the spirit and hereof. It is to be understood that various changes may be made in adapting the description to different embodiments without departing from the broader concepts disclosed herein and comprehended by the claims that follow: