Abstract:
A master slave flip-flop includes a data gate for receiving the input data and generating therefrom first and second internal data signals, and a master section for latching the internal data signals and for transmitting such signals to a slave section during predetermined portions of a clock signal. In order to render the internal data signals symmetrical with respect to each other and therefore substantially reduce the possibility of transmitting incorrect data to the slave as a result of a race condition in the master section, a Schottky diode is coupled within the data gate to complete a discharge path for one of the internal data lines and thus prevent it from exceeding a predetermined voltage.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates generally to master-slave flip-flops and, more particularly, to a master-slave flip-flop having an improved data gate for substantially reducing the possibility of transmitting incorrect data to the slave section due to a race condition in the master section without sacrificing performance speed. 
     A well known master-slave transistor comprises a data gate having a data input (D in ) for generating internal data signals (D and D), a master section for receiving D and D and a clock signal (C p ) and generating in response thereto first and second signals (A and B) indicative of D in , and a slave section responsive to A and B for storing the input data and generating the traditional Q and Q outputs. Unfortunately, this flip-flop suffers from several disadvantages. The internal data line or signal D when high is permitted to rise from approximately 2 volts to very near the supply voltage level (typically 5 volts) while D when high rises to only approximately 2.4 volts. This large voltage swing on the internal data line D may produce an adverse race condition in the master section which results in the transmission of incorrect data to the slave section. Furthermore, the high maximum voltage attainable at D causes a high voltage swing which in turn increases the propogation delays and set-up times. Finally, due to the non-symmetric high and low levels attainable on D and D, there is a substantial skew between the time it takes to set a &#34;0&#34; (T set0 ) and the time it takes to set a &#34;1&#34; (T set1 ). 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide an improved master-slave flip-flop. 
     It is a further object of the invention to provide an improved data gate for a master-slave flip-flop. 
     It is a still further object of the invention to provide a master-slave flip-flop including circuitry for reducing unwanted race conditions in the master section without reducing speed of operation. 
     Yet another object of the invention is to provide an improved master-slave flip-flop wherein the signals appearing on the internal data lines are symmetrical with respect to each other. 
     According to a broad aspect of the invention there is provided a master-slave flip-flop, comprising: data gate circuit means for receiving input data and for generating therefrom first and second complementary internal data signals representative of said input data; master circuit means coupled to said data gate circuit means for receiving a clock signal and for latching said internal data signals during a predetermined portion of said clock signals; slave circuit means coupled to said master circuit means for storing said internal data signals; and means for clamping at least one of said internal data signals to prevent said at least one of said internal data signals from exceeding a predetermined voltage so as to render said first and second internal data signal symmetrical with respect to each other. 
     According to a further aspect of the invention there is provided an improved master-slave flip-flop having an output which follows data present at a data input and of the type which includes a master section responsive to a clock signal for receiving internal data signals representative of the input data and a slave section for storing signals representative of said input data, the improvement comprising: data gate circuit means for receiving said input data and for generating therefrom first and second complementary internal data signals representative of said input data; and means for clamping at least one of said internal data signals to prevent it from exceeding a predetermined voltage so as to render said first and second internal data signals symmetrical with respect to each other. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above, and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the drawing which is a schematic diagram of the inventive flip-flop. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The flip-flop shown on the drawing comprises a data gate for receiving the input data signal (D in ) and for generating internal data signals D and D on internal data lines 4 and 6 respectively, a master section for receiving a clock pulse C p  at terminal 8 and responsive to D and D for generating signals A and B which, when the clock signal is low, correspond logically to Q and Q appearing at output terminals 10 and 12 respectively, and a slave portion 14 for storing the logic signals appearing at A and B when the clock pulse at C p  goes low and for generating the traditional Q and Q outputs. The clock pulse C p  must begin in its high state (a logical 1) in order to recognize changes in the input data (D in ). The data is latched at A and B on the trailing edge of the clock pulse. 
     The data gate includes Schottky transistors T 5  and T 6 , Schottky diodes S 1 , S 2 , S 3 , S 4 , and S 5 , diode D 1  and resistors R 3  and R 4 . Schottky diode S 4  has its anode coupled to the base of transistor T 6  and a cathode coupled to input terminal 2. Resistor R 4  is coupled between a source of supply voltage V CC  and the junction of the anode of S 4  and the base of T 6 . The emitters of transistors T 5  and T 6  are coupled together and, via the series combination of Schottky diode S 5  and diode D 1 , to ground. The collector of transistor T 6  is coupled to the cathode of Schottky diode S 2 , to the base of transistor T 5  and to the cathode of Schottky diode S 3 . Resistor R 3  is coupled between V CC  and the base of transistor T 5 . Finally, the collector of transistor T 5  is coupled to the anode of Schottky diode S 3  and the cathode of Schottky diode S 1 . 
     The flip-flop&#39;s master section includes Schottky transistors T 1 , T 2 , T 3 , and T 4  and resistors R 1  and R 2 . The emitters of transistors T 2  and T 3  are coupled together and to terminal 8 for receiving the clock signal C p . The base of transistor T 2  is coupled to the collector of transistor T 1  and to the anode of Schottky diode S 1 . The base of transistor T 3  is coupled to the collector of transistor T 4  and to the anode of Schottky diode S 2 . The emitter of transistor T 1  and the collector of transistor T 3  are coupled to node 16, and the collector of transistor T 2  and the emitter of transistor T 4  are coupled to node 18. The above described signals A and B appear at nodes 16 and 18 respectively. Finally resistors R 1  and R 2  are coupled between V CC  and the base electrode of transistors T 1  and T 4  respectively. 
     To illustrate how the problems described above arise, it will be assumed that Schottky diode S 3  is not in the circuit. Furthermore, throughout the following description, a logical high and a logical low will be represented by &#34;1&#34; and &#34;0&#34; respectively. Furthermore, it will be necessary to describe voltage levels appearing at various points in the circuit under certain conditions of D in  and C p . Thus, the voltage appearing across a standard diode or the base-emitter of any of the transistors will be referred to as .0.. The voltage across a Schottky diode will be represented by $ and the voltage drop across a transistor in saturation will be represented by &#34;SAT&#34;. 
     Assume first that Q is &#34;0&#34;, D in  is &#34;1&#34; and C p  is &#34;1&#34;. Current will flow through resistor R 4  turning transistor T 6  on. The voltage at the collector of transistor T 6  will then be approximately .0.+$+SAT. Since .0. is approximately 0.7 volts, $ is approximately 0.5 volts and SAT is approximately 0.2 volts, the voltage at the collector of transistor T 6  may be considered to be 2.0.. Therefore, the voltage of the internal data signal D appearing on line 6 will be 2.0.+$. Since the base of transistor T 5  is at a voltage 2.0., it remains off. The voltage of internal data signal D appearing on line 4 will be V CC  -$. The &#34;-$&#34; term which appears in the voltage equation at D is due to the Schottky clamp which appears across all of the transistors shown in the drawing. 
     With D equal to V CC  -$ and D equal to 2.0.+$, D may be considered high and D considered low. 
     When C p  begins to go low (i.e. on the trailing edge of the clock pulse), the base of transistor T 2  is at a higher voltage than the base of transistor T 3 . Thus, transistor T 2  turns on first pulling node 18 down and turning on transistor T 4 . This in turn prevents transistor T 3  from turning on. Thus, A may be considered to be a logical high while B is at a logical low. This information is passed into the slave section resulting in a high Q and a low Q. 
     Clock pulse at C p  is permitted to go all the way down to a SAT level and once there, changes in D in  will not effect the state of transistors T 2  or T 3 . When the clock pulse C p  again goes high, transistors T 2  and T 3  are turned off, the data which was at A and B when C p  was low is now stored in the slave, and A and B rise to a high level. 
     If now the data input signal were to go low (D in  =0), transistor T 6  would turn off and current would flow via resistor R 3  into the base of transistor T 5  turning it on and thereafter, via Schottky diode S 5  and diode D 1 , to ground. Now, the voltage at the collector of transistor T 6  equals the voltage at the base of transistor T 5  (2.0.+$). Thus, D equals 2.0.+2$. The voltage at the collector of transistor T 5  equals 2.0. and therefore D equals 2.0.+$. 
     It can now be seen that D may switch from a low level of 2.0.+$ to a higher level of V CC  -$ while D switches from a low level of 2.0.+$ to a high level of 2.0.+2$. Clearly the switching characteristics of D and D are non-symmetrical with respect to each other. 
     When C p  falls, the base of transistor T 3  is higher than the base of transistor T 2 . Therefore, T 3  turns on causing its collector (node 16) to go low which turns on transistor T 1  latching transistor T 2  off. Thus, A and Q go low, and B and Q go high. 
     The problem with this arrangement is that with D charged up to V CC  -$ and D to 2.0.+$, a condition is imposed on A and B which, with a very small differential voltage between the bases of transistors T 2  and T 3 , can result in an undesirable race condition. The problem may be illustrated as follows. The status of the circuit is: D in  is &#34;0&#34;, Q is &#34;0&#34; and C p  is again &#34;1&#34;. When C p  now goes to &#34;0&#34;, the voltage at the base of transistor T 6  is $, transistor T 6  turns off, the voltage at D is 2.0.+2$, and the voltage at D is 2.0.+$. The clock signal C p  is a low (is at a SAT), the base of transistor T 3  is at .0.+SAT, and node 16 is at 2 SAT since transistor T 3  is on. The base of transistor T 1  is at .0.+2 SAT and the base of transistor T 2  is at 3 SAT. Thus, the base of transistor T 2  is below its threshold and therefore transistor T 2  remains off. The base of transistor T 4  is at .0.+SAT+$ which is equivalent to 2.0.. Node 18 is connected to a transistor in the slave (not shown) the base of which is at 2.0.+$. Therefore, node 18 (and B) is at .0.+$. Thus, there is a differential voltage between A and B (i.e. nodes 16 and 18 respectively). 
     When the clock signals C p  again goes high, transistor T 2  and T 3  turn off. The voltage at the base of T 1  becomes 2.0.+2$, and the voltage at the base of T 4  becomes 2.0.+3$. The voltage at node 16 (A) becomes .0.+2$, and the voltage at node 18 (B) becomes .0.+3$. Thus, A and B are separated only by a $. Since the base of transistor T 3  is higher than that of transistor T 2 , T 3  should turn on faster when C p  again goes low. This is enhanced since the collector of T 3  is at a lower voltage than that of T 2  and therefore T 3  has a built-in advantage in the race against transistor T 2 . It should be clear by now that in the race between transistors T 2  and T 3 , in general, the transistor having the higher voltage at its base and the lower voltage on its collector will turn on first and latch the input data. 
     The problem manifests itself when the input voltage D in  now changes. With D in  equal to a &#34;1&#34;, transistor T 6  turns on, and transistor T 5  turns off. The clock pulse voltage is high (at V CC ), D is at 2.0.+$, D is at V CC  -$, node 16 (A) is at V CC  -.0., and node 18 (B) is at .0.+2$. If the input data should now change to a 0 (D in  =0), D becomes 2.0.+2$, node 18 (B) becomes .0.+3$, D becomes 2.0.+$, but A (node 16) does not change. It stays at V CC  -.0. since there is no way to discharge it. If the clock pulse C p  should now go low, the collector voltage of transistor T 3  is substantially higher than that of T 2 , and even though transistor T 3  may turn on first, it has to pull its collector all the way down from V CC  -$ and therefore may lose the race with transistor T 2  resulting in incorrect data being stored in the slave section. 
     This problem in addition to others described previously is solved by adding Schottky diode S 3 . Now when the input data (D in ) becomes high, and transistors T 6  and T 5  turn on and off respectively, the voltage at D cannot charge any higher than 2.0.+2$. Not only does this prevent the voltage at node 16 from being substantially greater than the voltage at node 18 as described previously, but now the signals appearing at D and D are symmetrical. That is, when D is high it is at 2.0.+2$ and when low it is at 2.0.+$. Similarly, when D is high it is at 2.0.+2$ and when low it is at 2.0.+$. Not only has the possibility of an unwanted race condition been substantially eliminated without increasing propogation delay or setup time, but the added symmetry has also substantially eliminated the skew between between T set0  and T set1 . 
     The above description is given by way of example only. Changes in form and details may be made by one skilled in the art without departing from the scope of the invention.