Abstract:
A power transistor design that eliminates thermally initiated secondary breakdown in fast, double-diffused transistors is described. The power dissipation capability is made independent of collector voltage, avoiding safe area restrictions below 0.9 BV CBO .

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to power transistor structures in which a large number of individual elements are coupled in parallel to act as a single unit. 
     In linear applications, maximum transistor stress occurs at higher voltages when considerable power is being dissipated for longer than 1 ms. Because the emitter base voltage of bipolar transistors has a negative temperature coefficient, the tendency is for maximum conduction where temperature is highest. The resulting hot spot formation can become unstable, leading to secondary breakdown. This can be avoided by ensuring uniform conduction. 
     The problem of localization can be better understood by considering two parallel connected transistors. The following equations account for the transconductance and thermal effects. ##EQU1## Where: g m  =base to collector transconductance 
     q=electron charge 
     k=Boltzmann&#39;s constant 
     T=Absolute temperature 
     θ j  =Thermal resistance of the transistor 
     φ B  =Temperature coefficient of the transistor base to emitter voltage. 
     I C  =Collector Current 
     V CE  =Collector to emitter voltage 
     V BE  =Base to emitter voltage. 
     Current sharing becomes potentially unstable when V BE  decreases with increasing I C . Without ballasting, this can occur for a temperature rise greater then 10° C. These equations are only valid when the g m  of the parallel connected transistors is equal. Once an instability is initiated, the mathematical description is less concise. The process exhibits hysteresis, and the destabilization will persist until ΔT is reduced to some lower value. 
     The situation can be improved with resistive ballasting in which a resistor is inserted in series with each emitter element. (A base ballast resistor can be moved to the emitter for analysis by dividing its resistance by transistor current gain.) The following related equations show that sufficient conditions for stability are simple and straightforward. ##EQU2## Where: R bal  is the ballast resistance 
     V bal  is the voltage across the ballast resistor 
     V B  is the combined V bal  and V BE . 
     A fraction of volt drop across the ballast resistor will insure uniform conduction for ΔT=300° C., even if low level injection is assumed (φ B  =2.5 mV/°C.) and mutual thermal coupling between elements is ignored. This shows the forward biased secondary breakdown can be completely eliminated for any reasonable set of operating conditions, suffering only an insignificant increase in transistor losses. 
     Standard bipolar power transistors rely upon high level effects rather than ballast to reduce g m  and φ B . The high level threshold can be lowered by using wide emitters and thick, lightly doped bases; but the improvement available is rather limited. Such structures are inherently slow. Single-diffused transistors also have the collector-base junction located close to the heat sink, which reduces thermal resistance and improves thermal coupling among elements. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to create a power transistor in which secondary breakdown is avoided by base resistor ballasting of the individual parallel connected elements that make up the structure. 
     It is a further object of the invention to incorporate a junction field effect transistor into the base of an element in a plural element power transistor whereby the collector voltage modulates the series base resistance which acts as a ballast. 
     These and other objects are realized using a cell structure that involves plural parallel-connected individual transistors. Each transistor is represented by a separate emitter diffused into a common base region. Opposing edges of the base region are coupled to a spaced apart base connection by means of an ion-implanted resistance layer, the backside of which forms a PN junction with the transistor collector. This means that the collector potential will deplete the resistor which will then be voltage variable as a function of collector voltage. The resistor thickness and doping density are established so that the resistor pinches off completely above the maximum collector voltage rating for the transistor. If desired, the resistor can be made to pinch off at a voltage below the maximum collector voltage and to include a short section of more highly doped material which acts as a shunt resistor. With this construction the resistor acts as if there were a shunt fixed section so that at pinch off the resistance goes up to some fixed value not infinity. 
     When a large number of such cells are parallel connected, the resulting device is base resistance ballasted with variable resistors that adjust themselves as a function of collector voltage. The resulting power transistor does not display the secondary breakdown characteristic. Such a device can be operated within its power rating at any desired collector voltage below BV CEO  without concern for instabilities. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 shows the cell layout of the invention. 
     FIG. 2 is a cross-section of the cell of FIG. 1 taken at line 2--2. 
     FIG. 3 is a schematic diagram of the cell of FIG. 1. 
     FIG. 4 is a graph plotting the resistance of the FET of FIG. 3 as a function of collector voltage. 
    
    
     DESCRIPTION OF THE INVENTION 
     FIG. 1 shows the topography of one form of power transistor cell constructed in accordance with the invention. FIG. 2 is a cross-section of the FIG. 1 structure taken at line 2--2. It is to be understood that the drawing is not to scale. In particular FIG. 2 is exaggerated dimensionally in order to better illustrate the invention. Also while the drawing shows four individual emitters, more or fewer could be used. 
     The transistor is constructed on an N +  type wafer 20, a fragment or chip of which is shown at 10. The substrate is of low resistivity to reduce series resistance and has an epitaxial surface layer 21 of a resistivity suitable for a transistor collector. In FIG. 1 the contact metallization has been omitted for clarity. 
     As shown in FIG. 2, the chip 10 is coupled to a heat sink surface 22 which also serves as a collector connection. This arrangement is typical of a double diffused bipolar silicon transistor. For example, heat sink 22 may be the typical T0-3 power transistor package. One complete power transistor cell is shown in FIG. 1 along with a portion of each of the adjacent cells. The central square 11 represents a transistor base diffusion of P-type conductivity normally created by a boron diffusion that typically extends about three microns into the semiconductor N-type epitaxial layer 21. 
     Four heavily doped emitters 12 are shown diffused into base 11. These emitters are small so that they individually have high frequency capability and a large periphery to area ratio. The dashed lines 13 inside the emitters represent the areas where the planar oxide will be removed and contact made to the silicon. It can be seen that a metallization finger 24 (not shown in FIG. 1) extended vertically on the drawing could be used to parallel connect all of the emitters in a plurality of cells in a row. 
     A pair of contact busses 14 and 15 are formed with P-type diffusions to extend across the device. They are spaced apart from base 11 and extend parallel with the edges thereof as shown. Two resistive strips 16 and 17 span the region between base 11 and busses 14 and 15 respectively. These resistive regions are preferably created using ion implantation to control their impurity content, but they are typically diffused after implantation so that they extend below the semiconductor surface to about the same extent as the base region 11. It can be seen that the undersides of resistors 16 and 17 will face the transistor N-type collector. Therefore the collector bias voltage will act to deplete or pinch off the resistors. This means that resistors 16 and 17 are voltage variable as a function of collector voltage and are coupled in series with base 11. Diffused busses 14 and 15 will be contacted by metallization 23 (not shown in FIG. 1) that will contact the silicon through contact 19 which is shown in dashed outline in FIG. 1. 
     Since resistors 16 and 17 are voltage variable and may pinch off completely within the normal transistor collector voltage, a more heavily doped section 18 is included within resistor 16. This section would ordinarily be created by an additional ion implant that will dope it sufficiently to raise its pinch off voltage above that of the transistor rating. 
     Section 18 can be regarded as a resistor that shunts the voltage variable resistor as shown in FIG. 3. This drawing is a schematic representation of the cell of FIG. 1. As can be seen, a bipolar junction transistor Q 1  has its base driven through a junction field effect transistor Q 2  which has resistor 18 in parallel between its source and drain. Q 2  has its gate connected to the collector of Q 1  because these devices are commonly fabricated into the silicon. As a practical matter resistor 18 could be portrayed as a second field effect transistor connected in parallel with Q 2 . However, if the pinch off of this second device is never exceeded, it will always be on and will act like a shunt resistor. 
     FIG. 4 is a graph that plots resistance as a function of voltage for a typical cell as shown in FIG. 1. It will be noted that at the lower voltage the resistance is about 1K ohms and rises with voltage to about 15K ohms which is the value of resistor 18. 
     EXAMPLE 
     Power transistors were constructed using the cell structure of FIG. 1. Typical die size was a 185 mil square with 316 such cells connected in parallel for a total of 1264 emitters. The resulting devices can dissipate 250 watts at voltages above 200 V. At 10 amperes the collector saturation was typically less than 1 volt. The f T  was over 50 MHz. Two different structures were prepared and optimized for different voltages by selecting the thickness and resistivity of layer 21. In the 200 volt version the typical current gain at ten amperes was about 25. In the 60 volt version the current gain was about 75 at ten amperes. 
     Neither structure displayed any secondary breakdown instabilities within their respective voltage ratings up to 250 watts. 
     The invention has been described and operating examples detailed. When a person skilled in the art reads the foregoing, there are alternatives and equivalents that will become apparent that are within the spirit and intent of the invention. Accordingly, it is intended that the scope of the invention be limited only by the following claims.