Abstract:
A memory cell is disclosed. The memory cell comprises a storage element including a first terminal and a second terminal, and a select transistor including a first terminal, a second terminal and a control terminal. The voltage at the control terminal of the select transistor affects a current flowing between the first terminal and the second terminal. The first terminal of the select transistor is coupled to the second terminal of the storage element. A bit line is coupled to the first terminal of the storage element, a first word line is coupled to the control terminal of the select transistor, and a second word line is coupled to the second terminal of the select transistor.

Description:
TECHNICAL FIELD 
       [0001]    This invention relates generally to semiconductor devices, and more particularly to a memory device and method. 
       BACKGROUND 
       [0002]    Semiconductors are used in integrated circuits for electronic applications, including radios, televisions, cell phones and personal computing devices, as examples. Types of semiconductor devices include dynamic random access memory (DRAM), static random access memory (SRAM) and flash memory which use charge to store memory, magnetic random access memory (MRAM), which uses a magnetic field to store memory, phase change random access memory (PCRAM), which uses a crystalline state to store memory, and conductive bridging random access memory (CBRAM), which uses a conducting path of silver atoms to store memory. 
         [0003]    Newer forms of memory such as MRAM, PCRAM and CBRAM contain memory elements whose memory state is read by measuring the impedance between two terminals. One common method of incorporating these memory elements into a functional memory is by creating a two dimensional array of these memory cells and placing each memory cell in series with a switch. Each row of the array represents a word in memory and each column of the array represents an output bit. To read a word from memory, each switch in the row to be read is closed while each switch in the remaining rows is kept open. All of the memory cells in a column are connected together in a wired-OR configuration, so that, in theory, the only bit in a column that draws current is the selected bit. By setting the bit line to a known voltage and measuring the current being drawn by a bit line, the memory state of a bit in a selected word can be determined. 
         [0004]    As electronic components are getting smaller and smaller, along with the internal structures in integrated circuits, the problem of device leakage becomes problematic. Transistor technology currently used in memory arrays suffers from the problem that a reduction in device size, while maintaining suitable on-currents, leads to increased off-currents in the device. The leakage currents of deselected devices along a bit line can reach levels high enough to disturb a read or a write operation in small geometry processes. 
         [0005]    One possible solution to the problem of leakage currents in memory arrays is to implement new transistor devices, such as finFETs, that exhibit lower leakage currents. These new transistor structures, however, can require considerable technology effort and are often more expensive to fabricate due to extra masks and processing steps. Thus, there is a need for improved memory array architectures and methods that exhibit lower leakage currents and do not require changes and advances in device technology to achieve this goal. 
       SUMMARY OF THE INVENTION 
       [0006]    In one embodiment, a memory cell comprises a storage element including a first terminal and a second terminal, and a select transistor including a first terminal, a second terminal and a control terminal. The voltage at the control terminal of the select transistor affects a current flowing between the first terminal and the second terminal. The first terminal of the select transistor is coupled to the second terminal of the storage element. A bit line is coupled to the first terminal of the storage element, a first word line is coupled to the control terminal of the select transistor, and a second word line is coupled to the second terminal of the select transistor. 
     
    
     
       DESCRIPTION OF THE DRAWINGS 
         [0007]    For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
           [0008]      FIG. 1  is a schematic diagram of an embodiment FET array memory; and 
           [0009]      FIGS. 2  is a flow chart of an embodiment method. 
       
    
    
       [0010]    Corresponding numerals and symbols in different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly illustrate certain embodiments, a letter indicating variations of the same structure, material, or process step may follow a figure number. 
       DETAILED DESCRIPTION 
       [0011]    The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention. 
         [0012]    The invention will be described with respect to preferred embodiments in a specific context, namely an NMOS FET and memory element memory structure. The invention may also be applied, however, to other semiconductor structures. 
         [0013]    Before discussing details of preferred embodiments, it will be instructive to consider conventional memory structures. Much of the discussion with respect to  FIG. 1  also applies to embodiments of the invention and, as a result, various details will not be repeated. 
         [0014]      FIG. 1  illustrates a first embodiment FET memory structure  100 . The structure is made up of memory cells  102   a - 102   i,  first word lines WLa k−1    114 , WLa k    112 , and WLa k+1    110 , second word lines WLb k−1    154 , WLb k    152 , and WLb k+1    150  and bit lines BL i−1    116 , BL i    118 , and BL i+1    120 . The memory cell in  FIG. 1  shows  9  representative memory cells configured in a 3×3 memory array for illustrative purposes, however, the bit lines and word lines can continue beyond the illustrated array and can support a memory array of any practical dimension. 
         [0015]    Each memory cell  102  is made up of a switch transistor  106 , typically implemented as an NFET device, and a memory element  104 . Each memory cell  102  has a common terminal  142  coupled to a controlled terminal of the switch transistor  106 , a control terminal  140  coupled to the control terminal of the switch transistor  106 , and an output terminal  144  coupled to the output terminal of the memory cell  102 . In a preferred embodiment of the present invention, switch transistor  106  is implemented as an NMOS device whereby the control terminal  140  is coupled to the gate of the NMOS device and the common terminal  142  is coupled to the source of the NMOS device. 
         [0016]    The memory element  104  can physically be implemented in a number of ways. For example, an MRAM element, a PCRAM element, or another memory element structure could be used to physically implement the memory element. For this memory structure, however, the resistance of the memory element is dependent on the state of the memory element. In an MRAM storage cell, for example, the spin of the electrons in the cell determines the state of the memory. A bit, e.g. a “0” or “1” may be stored in the storage element by changing the orientation of magnetic fields within layers present within the storage element. Because the resistance of the element is dependent on the orientation of the magnetic field within the layers of the storage element, the state of the element can be sensed by measuring the resistance of the element. For example, a binary “1” can be defined when the cell is programmed to have a low resistance and the binary “0” can be defined when the cell has a high resistance. Alternatively, a binary “0” can be defined when the cell is programmed to have a low resistance and the binary “1” can be defined when the cell has a high resistance. To read the memory, the resistance is measured by applying a voltage across the memory element and measuring the current with a sense amplifier. Switch transistor  106  is used as a switch to either select or deselect the memory cell  102  for reading or writing. 
         [0017]    Memory array  100  is arranged in a wired-or configuration. Each word in the array is selectable by a first word line. For example, the word made of memory cells  102   d,    102   e,  and  102   f  are selected by first word line, WLa k    112 . Each memory cell corresponding to a particular output bit is tied together on a bit line. For example, memory elements  102   b,    102   e  and  102   h  are all tied to bit line, BL i    118 . When the word of memory corresponding to first word line WLa k    112  is being read, WLa k    112  is set to a voltage that exceeds the threshold voltage of the switch transistors  106   d,    106   e,  and  106   f.  Remaining word first word lines WLa k−1    114  and WLa k+1    110  are set to ground so that NFET switches  104   a,    104   b,    104   c,    104   g,    104   h,  and  104   i  are turned off. Bit lines that are to be read, for example, BL i−1    116 , BL i    118 , and BL i+1    120  are set to a read voltage. 
         [0018]    As an example, the read method used in conventional art FET memories will be described. If this memory is configured as a conventional art FET memory, second word lines WLb k−1    154 , WLb k    152 , and WLb k+1    150  are all set to ground. Because the sources of memory switch transistors  106   a - i  are directly tied to ground, conventional art FET memories typically do not have second wordlines WLb k−1    154 , WLb k    152 , and WLb k+1    150  as depicted in  FIG. 1 . 
         [0019]    When the read voltage is applied, a measurable current I sk    122  in bit line BL i    118  will flow through memory element  104   e  and NFET switch  106   e  if memory element  104   e  is programmed to be in a low resistance state. For example, a binary “1” could be read if a binary “1” is defined to be represented by a low resistance state. A sense amplifier (not shown) can be used to detect the presence of I sk    122  so that the state of the memory element  102   e  can be determined. In binary memories, the sense amplifier typically compares the bit line current to a threshold. If the memory element  104   e  is programmed to be in a high resistance state, however, I sk    122  will be small and a binary “0” may be read from memory. Alternatively, in other embodiments of the present invention, a binary “1” could be defined to if the memory element is in a high resistance state and a binary “0” could be defined if the memory element is in a low resistance state. 
         [0020]    In modern, small geometry silicon process, where gate lengths are less than 100 nm, however, the FET switches may exhibit leakage current when the gate to source voltage is less than the threshold. This leakage may be, for example, the result of sub-threshold conduction. In large memory arrays with many word lines this leakage becomes problematic. If devices in the row connected to BL i  (i.e.  106   b  and  106   h ) each have a leakage current of 100 nA, then the read line will conduct 200 nA even when the memory is programmed to be in a high resistance state. If the bit line is connected to a significant number of memory devices, then the leakage current could become on the order of a programmed bit, thus either making the memory unreadable, or reducing the reliability and noise tolerance of the memory. 
         [0021]    In the preferred embodiment of the present invention, errors caused by leakage current of the switch transistors  106   a - i  are minimized by a method of reading the memory. When a memory cell is read, the source of the switch transistor  106  in the memory cell to be read is kept at ground, the gate of the switch transistor is set to a voltage exceeding the switch transistor&#39;s  106  threshold, and the bit line to be read is set to a read voltage so that a voltage is developed across the memory element resistance  104 . For example, if memory cell  102   e  is to be read, word line WLa k    112  is set to a voltage exceeding a read threshold, typically 400-500 mV in a 70 nm process technology, word line WLb k    152  is set to ground, and bit line BL i    118  is set to a read voltage, typically between about 0.1V and 1 V. 
         [0022]    In the preferred embodiment of the present invention, a memory cell is deselected by applying a voltage at the source terminal of the switch transistor  106  that approximates the read voltage applied at the bit line, and applying a voltage at the gate of the switch transistor  106  that turns off the switch. In preferred embodiments of the present invention, this gate voltage is ground voltage, but in other embodiments it could be voltages other than ground. By applying a voltage at the source of the switch transistor  106  close to the voltage applied at the bit line connected to the memory cell, the source-drain voltage of the switch transistor  106  is very small, which minimizes any leakage current developed as a result of a potential difference across the source and drain of the switch transistor  106 . In a preferred embodiment of the present invention, the source-drain voltage of a deselected switch transistor is kept at under 10 mV to 20 mV. Such a small source-drain voltage can keep the leakage current of switch transistor  106  to a factor of 10 to 50 less than the leakage current seen in the conventional embodiment described herein above, where the source-drain voltage of a deselected switch transistor is typically between 100 mV to 1V. 
         [0023]    For example, if the word consisting of memory cells coupled to word lines WLa k    112  and WLb k    152  is being read, bit lines BL i−1    116 , BL i    118 , and BL i+1    120  are set to a read voltage, word lines WLb k−1    154  and WLb k+1    150  are set to a voltage preferably within 10 mV to 20 mV of the read voltage, and word lines WLa k−1    114  and WLa k+1    110  are set to a voltage, preferably ground, that shuts off the switch transistor  106  in the deselected memory cells. In the illustration in  FIG. 2 , the source voltage of deselected switch transistors  106   a - c,  and  106   g - i  are kept within 10 mV to 20 mV of the drain voltage, so that leakage current through the deselected transistors are minimized. Bit line current flow I sk    122 , for example, will then be primarily dependent on the programmed resistance of memory element  104   e,  current flow I sk−1    124  will be primarily dependent on the programmed resistance of memory element  104   d,  and current flow I sk+1    126  will be primarily dependent on the programmed resistance of memory element  104   f.    
         [0024]    Turning to  FIG. 2 , a flowchart  200  describing a preferred embodiment method of reading a FET memory is shown. In the first step  202 , the first word line WLa k  on the k th  row, the row to be read, is set to select voltage. The first word lines WLa n≠k  on the remaining rows n≠k is set to ground. In step  204 , the second word line on the k th  row, the row to be read, WLb k  is set to ground. The second word lines WLb n≠k  on the remaining rows n≠k is set to a read voltage, typically between about 0.1V and 1 V. In step  206  all bit lines BL are set to a read voltage. Alternatively, only a subset of the bit lines may be set to a read voltage if not all of the bit lines need to be read for a particular application. In step  208 , the bit line currents are read to determine the state of the memory. 
         [0025]    The implementation of the control method described in  FIG. 2  is typically implemented by a memory controller and/or other circuitry known in the art. The specific implementation and timing details, however, are application, process and memory type specific. 
         [0026]    While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.