Abstract:
A semiconductor package having a heat sink attached to a substrate is provided. The semiconductor package includes a substrate for mounting at least one semiconductor chip thereon; wherein the semiconductor chip is electrically connected to the substrate and a plurality of positioning holes formed on the substrate for being engaged with a plurality of positioning portions formed on the heat sink, allowing the heat sink to be securely fixed to the substrate. Thus dislocation of the heat sink on the substrate can be effectively prevented during the molding process.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates to semiconductor packages and, more particularly to a semiconductor package having a heat sink for improving heat dissipating efficiency.  
         BACKGROUND OF THE INVENTION  
         [0002]    In recent years, semiconductor devices are in the rapid development for high integration, miniaturization and high performance with the trends of producing downsized electronic devices of high performance. The use of a ball-grid-array (BGA) substrate in a semiconductor device can maximize the number of input/output connections and allow a semiconductor chip adhered to the ball-grid-array substrate to have an increased density of built-in electronic components and electric circuits, contributing to the miniaturization and high performance of semiconductor devices. The semiconductor chip encapsulated in a ball-grid-array semiconductor device may contain higher density of electronic circuits and electronic components, but the heat generated therefrom during operation will significantly increase. Also the encapsulation body used to encapsulate the semiconductor chip is made of resin material with poor thermal conductivity. As a result, if the thermal dissipating efficiency of the ball-grid-array semiconductor device is not satisfactory, the electronic performance and operable life of the semiconductor device would be adversely affected.  
           [0003]    Various methods of providing satisfactory heat dissipation to BGA semiconductor devices have been proposed. An example of a semiconductor device with an incorporated heat sink is illustrated in FIG. 9. A semiconductor chip  10  is mounted on a substrate  20 , on which a heat sink  40  is mounted by thermosetting adhesive  30 . An encapsulation body  50  formed by molding resin is then used to encapsulate the semiconductor chip  10  and heat sink  40 . The heat sink  40  of the semiconductor device consists of a flat portion  401  and a supporting portion  400  connecting to the flat portion  401 . The supporting portion  400  of the heat sink  40  is arranged in a manner to allow the flat portion  401  of the heat sink to be separated from the substrate  20 . Thus after mounting the heat sink  40  onto the substrate  20 , the semiconductor chip  10  is positioned underlying the flat portion  401  of the heat sink  40 .  
           [0004]    The above-mentioned semiconductor package, however, still has drawbacks. During the process of adhering the heat sink  40  to the substrate  20 , the heat sink  40  tends to be dislocated form a predetermined position on the substrate  20 . The foregoing problem is usually caused by the vibration of the equipments used for adhering the heat sink  40  to the substrate  20  and inadvertent operation during adhering process. Moreover, the dislocation of the heat sink  40  may cause the heat sink  40  to be in contact with gold wires  50  that electrically connect the semiconductor chip  10  and the substrate  20 , thereby resulting in reliability problem of the product thus-obtained.  
         SUMMARY OF THE INVENTION  
         [0005]    It is therefore the objective of the present invention to provide a semiconductor package having a heat sink that can be securely positioned on the substrate. As the heat sink can be securely positioned on the substrate, dislocation problem of the heat sink can be eliminated and the reliability of the semiconductor devices can be enhanced.  
           [0006]    To achieve the above and other objectives of the present invention, a semiconductor device is provided to include: a substrate having a first surface, a second surface opposing the first surface, a die-attach region formed on the first surface of the substrate, a plurality of positioning holes formed on the substrate and arranged peripherally around the die-attach region; a semiconductor chip attached to the die-attach region of the substrate and electrically connected to the substrate; a heat sink composed of a flat portion, a supporting portion integrally formed with the flat portion so as to elevate the flat portion to a predetermined height above the semiconductor chip, and a plurality of positioning portions protruded form the bottom of the supporting portion for being engaged with the corresponding positioning holes of the substrate to thereby securely fix the heat sink in position to the substrate; a plurality of electrical conductive elements disposed on the second surface of the substrate; and an encapsulation body which encapsulates the entire semiconductor chip and at least a portion of the heat sink.  
           [0007]    The substrate usually consists of a core layer having a top surface, a bottom surface opposing the top surface, a plurality of electrically conductive traces formed on at least one of the top surface and the second surface of the core layer, and solder mask layers formed on the top and bottom surfaces of the core layer.  
           [0008]    In a preferred embodiment of the invention, a plurality of through holes are formed within an area of the core layer without formation of the electrically conductive traces. After the coating process of applying the solder mask onto the top surface and the bottom surface of the core layer is completed, a conventional etching process or the like is employed to remove the solder mask formed above the through holes and a portion of the solder mask filled within the through holes, so as to form the positioning holes that extend from the first surface of the substrate to an inner portion of the core layer. This allows each of the positioning holes to have one end exposed to the first surface of the substrate and another end closed by the solder mask.  
           [0009]    In another embodiment of the invention, a plurality of through holes are formed on an area of the core layer which is free of electrically conductive traces. By a conventional etching process or the like following applying the solder mask over the core layer, the solder mask above the through holes, within the through holes, and below the through holes is removed to form the positioning holes. Thus the positioning holes extend through the substrate.  
           [0010]    In still another embodiment of the present invention, on the ground pad formed on the terminal of each of the ground conductive traces an opening is formed, allowing a positioning hole to form by removing the solder mask above and within the opening by conventional etching technique. The positioning hole thus-formed therefore extends from the first surface of the substrate to the top surface of the core layer. As a result, the heat sink can be not only securely fixed to the substrate by the engagement of the positioning portions of the heat sink with the positioning holes formed on the substrate, but also electrically connected to the ground conductive traces on the substrate. Therefore, the electrical performance of the semiconductor package of this invention can be enhanced.  
           [0011]    In still another embodiment of the present invention, a plurality of through holes are formed on predetermined positions of the core layer. Each of the through holes is arranged to connect an opening formed on the terminal of each of the ground conductive traces on the core layer. Therefore, a positioning hole can be formed by removing the solder mask above the opening, within the opening and in the upper portion of the through hole via conventional etching technique or the like. By this arrangement, the heat sink is allowed to have an electrical-connection relationship with the ground conductive traces on the substrate, in addition to the secure fixing of the heat sink to the substrate.  
           [0012]    In still another embodiment of the present inventions, the formation of a positioning hole is achieved by removing the solder mask above and within an opening formed on the ground pad of the terminal of the ground conductive trace, the solder mask within a through hole formed in the substrate relative in position to the opening and the solder mask below the through hole. Therefore, the positioning hole extends through the substrate.  
           [0013]    In still another embodiment of the present invention, the formation of a positioning hole includes an opening formed on the ground pad connected to the terminal of the ground conductive trace formed on the bottom surface of the core layer, allowing a ground ball to be bonded to the opening of the ground pad on the bottom surface of the core layer. This makes the heat sink, ground conductive traces, positioning holes and the ground balls in combination form a grounding circuit so that the electrical performance of the semiconductor package of the present invention can be enhanced.  
           [0014]    In still another embodiment of the present invention, the positioning hole is formed in a manner that the diameter of an upper portion of the positioning hole is substantially larger than that of a lower portion of the positioning hole. Likewise, the positioning portions of the heat sink each is formed a corresponding stepped profile. Thus an enhanced anchoring effect is obtained between the positioning holes and the positioning portions. Moreover, an enhanced interconnection between the heat sink and the substrate is further achieved to prevent the delamination occurred therebetween. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:  
         [0016]    [0016]FIG. 1 is a cross sectional view of a semiconductor device in accordance with a first embodiment of the present invention;  
         [0017]    [0017]FIG. 2 is an enlarged cross sectional view of a portion of the semiconductor device in accordance with a second embodiment of the present invention;  
         [0018]    [0018]FIG. 3 is an enlarged cross sectional view of a portion of the semiconductor device in accordance with a third embodiment of the present invention;  
         [0019]    [0019]FIG. 4 is an enlarged cross sectional view of a portion of the semiconductor device in accordance with a forth embodiment of the present invention;  
         [0020]    [0020]FIG. 5 is an enlarged cross sectional view of a portion of the semiconductor device in accordance with a fifth embodiment of the present invention;  
         [0021]    [0021]FIG. 6 is an enlarged cross sectional view of a portion of the semiconductor device in accordance with a sixth embodiment of the present invention;  
         [0022]    [0022]FIG. 7 is an enlarged cross sectional view of a portion of the semiconductor device in accordance with a seventh embodiment of the present invention;  
         [0023]    [0023]FIG. 8 is an enlarged cross sectional view of a portion of the semiconductor device in accordance with an eighth embodiment of the present invention;  
         [0024]    [0024]FIG. 9 is a cross sectional view of a structure of a semiconductor device in accordance with the prior art; 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
     First Embodiment  
       [0025]    [0025]FIG. 1 illustrates a first embodiment of the semiconductor device according to the present invention. As shown in the drawing, the semiconductor device  2  is composed of a substrate  20 , a semiconductor chip  21  mounted on the substrate  20 , a heat sink  22  mounted on the substrate  20 , and an encapsulation body  23  used to encapsulate the entire semiconductor chip  21  and a portion of the heat sink  22 .  
         [0026]    The substrate  20  includes a core layer  200  made of resin material or the like. The core layer  200  has a top surface for a plurality of conductive traces  201  to be formed thereon and a corresponding bottom surface for a plurality of second conductive traces  202  to be formed thereon. The first conductive traces  201  are electrically connected to the second conductive traces  202  through a plurality of vias  203 . Further, the first conductive traces  201  of the core layer  20  are covered by a first solder mask  204  coated thereon, and similarly, the second conductive traces  202  of core layer  20  are covered by a second solder mask  205  coated thereon. The application of solder mask is used to protect the conductive traces  201  and  202  from exterior environment.  
         [0027]    A plurality of bonding fingers  206  formed on each terminal (not shown) of the first conductive traces  201  are exposed to the exterior of the first solder mask  204 . Similarly, a plurality of bonding fingers  207  formed on each terminal of the second conductive traces  202  are exposed to the exterior of the second solder mask  205 . A plurality of positioning holes  24  are peripherally formed around a die-attach region (not shown) of the substrate  20  for the semiconductor chip  21  to adhere thereto. It is to be noted that the solder mask in the positioning holes  24  is removed by conventional etching techniques, to the extent that the positioning holes  24  extend from the first solder mask  204  to an intermediate portion of the core layer  200 .  
         [0028]    A die bonding process is performed to adhere a semiconductor chip  21  onto the substrate  20  by a conventional adhesive  25  such as silver paste or polyimide tape. The semiconductor chip  21  is then electrically connected to the bonding fingers  206  on the terminals of the first conductive trace  201  via a plurality of gold wires  26  to thereby electrically connect the semiconductor chip  221  to the substrate  20 .  
         [0029]    The heat sink  22  of the semiconductor package according to the present invention is composed of a flat portion  220 ; a supporting portion  221  integrally formed with the flat portion  220  for elevating the flat portion  220  to a predetermined height above the semiconductor chip  21 ; and a plurality of positioning portions  222  protruded from bottoms of the supporting portion  221 . The supporting portion  221  is extended outwardly and downwardly from the flat portions  220  to a predetermined length. After mounting the heat sink  22  on a predetermined position of the substrate  20 , the supporting portion  221  and the flat portion  220  of the heat sink  22  together define a cavity for receiving the semiconductor chip  21  therewithin. Moreover, the supporting portion  221  of the heat sink  22  is elevated to a predetermined height such that the bottom of the flat portion  220  of the heat sink  22  is spaced with an appropriate distance from the top point of the wire loop of each gold wire  26 . The positioning portions  222  of the heat sink  22  are formed on the supporting portion  221  of the heat sink  22  by stamping or other conventional techniques. The diameter (l) of the positioning portions  222  is required to be smaller than the diameter ( ) of the positioning holes  24  on the substrate  20 . This arrangement allows the positioning portions  222  of heat sink  22  to be engaged with the positioning holes  24  of the substrate  20  and therefore preventing the heat sink  22  from dislocation from a desired position on the substrate  20 . Further, an adhesive  27  is applied to the positioning holes  24  to securely hold the positioning portions  222  of the heat sink  22  in place. As a result, the heat sink  22  is securely fixed to the substrate  20 .  
         [0030]    The heat sink  22  is made of conductive metal materials, such as copper, aluminum, copper alloy, aluminum alloy, or the combination thereof. According to the present invention, the top surface of the flat portion  220  of the heat sink  22  can be exposed to the exterior of the encapsulation body  23 , therefore significantly improving the efficiency of spreading heat generated from the semiconductor chip  21  during operation. Alternatively, the heat sink  22  may also be fully encapsulated by the encapsulation body  23 . However, such an arrangement will have a heat-dissipating efficiency inferior to the semiconductor device shown in FIG. 1.  
         [0031]    After the molding process for forming the encapsulation body  23  is completed, a plurality of solder bumps  28  are implanted on the lower solder pads  207  exposed on the second surface of the substrate  20  by conventional solder ball-implantation process. The solder bumps  28  are used for electrically connecting to the semiconductor chip  21  to external devices. As the implantation of the solder balls is conventional, detailed description thereto will be hereby omitted for simplification.  
       Second Embodiment  
       [0032]    [0032]FIG. 2 illustrates the semiconductor device according to a second embodiment of the present invention.  
         [0033]    In contrast to the first embodiment, the positioning holes  34  on the substrate  30  of the semiconductor device  3  has an enlarged upper portion. In other words, the diameter (l 1 ) of the upper portion of the positioning holes  34  disposed within the first solder mask  304  is larger than the diameter (l 2 ) of the lower portion of positioning holes  34  disposed in the core layer  300 . Likewise, the width L 1  of the upper portion  322   a  of the positioning members  322  is slightly smaller than the diameter (l 1 ) of the upper portion of the positioning holes  34  and the width L 2  of the lower portion  322   b  of the positioning members  322  is slightly smaller than the diameter ( 2 ) of the lower portion of the positioning holes  34 . Further, the diameter (l 1 ) of the upper portion  322   a  of the positioning members  322  is larger than the diameter (l 2 ) of the lower portion  322   b  thereof. This arrangement thus enables the positioning members  322  of the heat sink  32  to be more securely engaged with the positioning holes  34  of the substrate  30  and therefore results in an improved anchoring effect.  
       Third Embodiment  
       [0034]    [0034]FIG. 3 illustrates the semiconductor device according to a third embodiment of the present invention.  
         [0035]    The heat sink  42  of the third embodiment is composed of a flat portion  420 ; a supporting portion  421  integrally formed with the flat portion  420  for elevating the flat portion  420  to a predetermined height above the semiconductor chip (not shown); and a plurality of positioning portions  422  formed on the bottom of the supporting portion  421 . In contrast to the first embodiment, the positioning members  422  are formed by vertically and downwardly stamping the edge of the supporting portion  422 , thereby making the positioning members  422  in pillar shape when cross-sectionally viewed.  
       Fourth Embodiment  
       [0036]    [0036]FIG. 4 illustrates the semiconductor device according to a fourth embodiment of the present invention.  
         [0037]    The semiconductor device  5  illustrated in FIG. 4 is basically the same as that illustrated in FIG. 1, except that the positioning holes  54  in the substrate  50  are formed via conventional etching technique by removing a portion of the first solder mask  504 , the core layer  500 , and the second solder mask  505 , respectively, so as to allow the positioning holes  54  to penetrate the substrate  50 . Further, the positioning portions  522  of heat sink  52  are securely positioned within the positioning holes  54  of the substrate  50  by an adhesive  57 , allowing the position holes  54  to be sealed by the adhesive  57 .  
       Fifth Embodiment  
       [0038]    [0038]FIG. 5 illustrates the semiconductor device according to a fifth embodiment of the present invention.  
         [0039]    The semiconductor device  6  illustrated in FIG. 5 is basically the same as that illustrated in FIG. 1 except that for forming the positioning hole  64 , a through hole  606   a  is formed on the ground pad  606  of the terminal of the first conductive  601  formed on the top surface of the core layer  600 . The positioning holes  64  are formed by subsequently removing the first soldering mask  604  above and within the through hole  606   a.  Likewise, the positioning hole  64  extends from the top surface of substrate  60  to the top surface of core layer  600  but not to the inner portion of the core layer  600 . Further, the positioning portions  622  of heat sink  62  are securely engaged within the positioning holes  64  of the substrate  60  by an adhesive  67 , thereby enabling the heat sink  62  to be electrically connected to the ground pad  606 . This arrangement can further enhance the electrical performance and reliability of the packaged semiconductor product.  
       Sixth Embodiment  
       [0040]    [0040]FIG. 6 illustrates the semiconductor device according to a sixth embodiment of the present invention.  
         [0041]    The semiconductor device  7  illustrated in FIG. 6 is basically the same as that illustrated in FIG. 1, except that the positioning holes  74  in the substrate  70  are formed by removing a portion of the first solder mask  704 , a portion of the ground pad  706  formed on the terminal of the first conductive trace  701 , and a portion of the core layer  700  beneath the ground pad  706 , respectively. As the bottom end of the positioning hole  74  which is positioned within the core layer  700  is sealed by the second solder mask  705 , after the positioning portions  722  of heat sink  72  are securely engaged with the positioning holes  74  of the substrate  70 , the heat sink  72  is allowed to be securely fixed to the substrate  70  and therefore prevent the heat sink  72  from being dislocated from the desired position on the substrate  70 . Further, a grounding circuit is formed by the electrical connection of the heat sink  72  with the ground pads  706 , therefore enhancing the electrical performance and reliability of the packaged semiconductor product.  
       Seventh Embodiment  
       [0042]    [0042]FIG. 7 illustrates the semiconductor device according to a seventh embodiment of the present invention.  
         [0043]    The semiconductor device  8  illustrated in FIG. 7 is basically the same as that illustrated in FIG. 1, except that the positioning holes  84  in the substrate  80  are formed by removing a portion of the first solder mask  804 , a portion of the ground pad  806  formed on the terminal of the first conductive trace  801 , and a portion of the core layer  800  beneath the ground pad  806 , and a portion of the second solder mask  805 , respectively, thereby allowing the positioning holes  84  to extend through the substrate  80 . Further, the positioning portions  822  of heat sink  82  are securely positioned within the positioning holes  84  of the substrate  80  by a conductive adhesive  87 , while the positioning holes  84  are sealed by the adhesive  87 .  
       Eighth Embodiment  
       [0044]    [0044]FIG. 8 illustrates the semiconductor device according to an eighth embodiment of the present invention.  
         [0045]    The semiconductor device  9  illustrated in FIG. 8 is basically the same as that illustrated in FIG. 1 except that a plurality of bond pads  903  arrayedly arranged are disposed on the die-attach region (not shown) on the substrate  90 , allowing the semiconductor chip  91  to be electrically connected to the substrate  90  by solder bumps  99  rather than by gold wires used in the previous embodiment. Thus, the requirement of an apron area formed on the substrate in wire bonding process is prevented.  
         [0046]    In the eighth embodiment, by conventional etching technique, the positioning holes  94  in the substrate  90  are formed by removing in order, a portion of the first solder mask  904 , the ground pads  906  formed on the terminals of the first conductive traces  901 , the core layer  900  beneath the ground pads  906 , the lower ground pads  907  formed on the terminals of the second conductive traces  902 , and the second solder mask  905 , respectively. Further, a plurality of ground balls  98  are managed to be bonded to the ground pads  907 , thereby facilitating the formation of a grounding circuit formed by the heat sink  92 , the ground pads  906 ,  907 , and the ground balls  98 .  
         [0047]    The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.