Abstract:
A circuit and method for power converter for improved current monitoring, comprising a buck converter comprising a high side switch, a current sensing circuits parallel to the buck converter configured to sense a current through a low side switch, and a positive slope inductor coil estimator sensing circuit parallel to a buck converter configured to estimate a current magnitude.

Description:
BACKGROUND 
       [0001]    1. Field 
         [0002]    The disclosure relates generally to a buck controller and, more particularly, to a control method using inductor coil current estimation thereof. 
         [0003]    2. Description of the Related Art 
         [0004]    Voltage regulation is important where circuits are sensitive to transients, noise and other types of disturbances. The control of the regulated voltage is key in switched mode power supplies (SMPS) and in many hysteretic-based topologies. Switched mode power supply topologies include the buck converter topology. 
         [0005]    In hysteretic-based topologies, one of the topologies includes a hysteretic current-mode (CM) topology. 
         [0006]      FIG. 1  shows a typical hysteretic current-mode controller. The buck converter  100  consists of a SR flip-flop  105  with inputs SET  101  and RESET  102 . The SR flip-flop  105  provides a DUTY signal output  107  to pre-drive circuitry  110 . The signal VIN  115  provides power to the output circuit comprising of a p-channel metal oxide semiconductor field effect transistor (MOSFET) pull-up device  120  and an n-channel metal oxide semiconductor field effect transistor (MOSFET) pull-down device  125 . The p-channel MOSFET can be referred to as a PMOS transistor, and the n-channel MOSFET can be referred to as a NMOS transistor. The center node VLX is connected between the p-channel MOSFET  120  and n-channel MOSFET  125  providing a current to the output. The output node is connected to the inductor  140 , the output capacitor  145  for the output signal  150 , and output load  160 . 
         [0007]    Both MOSes can be replaced with BJTs or any other types of semiconductor switches. PMOS can be replaced with NMOS and vice-versa 
         [0008]    A feedback network establishes a sensing scheme to current sensing circuit  130 . Current in the inductor coil  140  is measured via current sensing circuits CSp  135  and CSn  137  where CSp  135  is active when PMOS P is ON and CSn  137  is active when NMOS N is ON. Both signals from the current sensing circuits are combined in the Current Sensing Block  130  and produce one signal ILint  139  which is an internal replica in the current in the coil. The circuit contains an Error amplifier  170  with the output signal  165 , reference signal  167  coupled to a compensation network. The output of the Error Amplifier  170  is coupled to a compensation network. The error amplifier compares the output voltage with the reference voltage Vref and generates error signal vError. This signal is a base for two signals vError_H  175 A and vError_L  175 B which are shifted up and down from the vError by Voff/2 respectively. Internal coil current replica ILint is then compared with the vError_H  175 A and vError_L  175 B signals and resets (signal  185 A) and sets (signal  185 B) the main RS Flip-Flop FF 1   105  which controls the switches. 
         [0009]      FIG. 2  shows the timing diagram  200  for the signals. The p-channel MOS (PMOS)  210  and n-channel MOS (NMOS)  220  shows the switching of the output stage. The signal vError_H  230  and vError  240 , and vError_L  250  describes the switching states of the error compensation network. The current through the inductor ILint  260  is overlaid on the switching states. In order to keep the frequency within given range several techniques can be implemented. The same is true for discontinuous current mode (DCM) mode of operation where current in the coil doesn&#39;t go below zero. 
         [0010]    The described topology in  FIG. 1 , is good during transient events. The disadvantage of this prior art embodiment is the high quiescent current due to dual current sensing circuit which causes lower efficiency at light loads. In addition, a second disadvantage is the current sensing circuitry are usually noisy and layout sensitive. Additionally, another disadvantage is that the current sensing circuitry can also introduce switching noise. 
         [0011]    U. S. Patent Application 2014/0247026 to Svorc describes a switched mode power supply having increased efficiency due to a loss-less coil current estimation for current control using a capacitor that has the same signal shape as the current through the coil inductor. 
         [0012]    U.S. Pat. No. 8,698,470 to Ju shows a buck voltage regulator with mode switching based on sensing an integrated inductor current sense signal with an integrated reference signal. The patent also discusses switching from PWM and PFM operation in a buck converter. 
         [0013]    U.S. Pat. No. 8,766,617 to Wan et al describes a method for improving voltage identification transient response by sensing the inductor current of a voltage regulator. 
         [0014]    U.S. Pat. No. 7,053,595 to Mei et al shows a method and circuit for compensating offset errors caused by propagation delays in hysteretic control loops. 
         [0015]    U.S. Pat. No. 6,707,281 to Solivan describes a voltage regulator that may include an inductor and a current detection circuit to detect current through the inductor. 
         [0016]    U.S. Pat. No. 6,037,754 to Harper shows a circuit with inductor maximum current computation, inductor current comparator, and a current magnitude sensor. 
         [0017]    In these prior art embodiments, the solution to establish a sampling circuit in switching regulator utilized various alternative solutions. 
       SUMMARY 
       [0018]    It is desirable to provide a solution to address an efficient voltage regulator with minimal power consumption at light loads. 
         [0019]    It is desirable to provide a solution does not impact the transient response of the controller. 
         [0020]    It is desirable to provide a solution which does not increase the noise induced by the current sensing circuitry. 
         [0021]    It is desirable to provide a solution that operates at higher switching frequency with an estimating circuit function with a smaller delay than a current sensing circuit. 
         [0022]    A principal object of the present disclosure is to propose a solution using inductor coil current estimation technique for the current mode control. 
         [0023]    In summary, a power converter, such as a buck converter, comprising a high side switch, a current sensing circuits parallel to the buck converter configured to sense a current through a low side switch, and a positive slope inductor coil estimator sensing circuit parallel to a buck converter configured to estimate a current magnitude. 
         [0024]    In addition, a power converter comprising a circuit providing switching regulation with an inductor coil current estimator with an improved current monitor comprising an output stage configured to provide switching comprising a first and second transistor, a pre-drive circuit block configured to provide a signal to the output stage, a SR flip-flop configured to establish a duty cycle for the pre-drive circuit block, an inductor configured to receive a signal from the output stage, a capacitor and load configured to provide a load on the output, an error amplifier configured to provide feedback from the output, a compensation network configured to shape the frequency response in order to achieve stable system, a current sensing network configured to provide a signal from the output stage, and, an inductor coil current estimator configured to receive signals from the input signal, the output signal and DUTY signal. 
         [0025]    In addition, a current estimator circuit comprises a transconductance network configured to provide an output current, a first switch configured to receive an output current, a second switch coupled to the first switch, an error signal configured to receive a signal from the second switch, and, an output node configured to be coupled between the first switch and the second switch. 
         [0026]    A method of providing an improved current estimation in a power converter comprises the steps of a first step (a) providing a power converter comprises a low side switch, a high side switch, a current sensing circuit, a positive slope inductor coil estimator, an error amplifier, a compensation network, and a first and second comparator, a second step (b) sensing a current in a signal low side switch, a third step (c) estimating a current in a positive slope inductor coil estimator, and a fourth step (d) adjusting a current in the output of the power converter. 
         [0027]    In addition, a method is disclosed in accordance with the embodiment of the disclosure. A method of providing an improved current estimation in a switching regulator comprises the steps of a first step (a) providing a hysteretic buck converter with a PMOS transistor pull-up, a NMOS transistor pull-down, a pre-drive circuit, a SR flip-flop, an inductor, a capacitor, an error amplifier, a compensation circuit, an NMOS Current Sensing block, a Positive Slope Coil Current Estimator, a SET comparator, and a RESET comparator, a second step (b) estimating the current in the inductor when the PMOS transistor pull-up is turned ON, a third step (c) increasing the voltage vILint along the current in the inductor, a fourth step (d) turning off the PMOS transistor when the voltage vILint reaches the high error voltage vError_H, a fifth step (e) sensing the current when the NMOS transistor is turned ON, using the current sensing circuit, a sixth step (t) evaluating the inductor voltage vILint when connected to low error voltage vError_L during this period of time; and, a seventh step turning off the NMOS transistor when the coil current reaches the low error voltage vError_L. 
         [0028]    Other advantages will be recognized by those of ordinary skill in the art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0029]    The present disclosure and the corresponding advantages and features provided thereby will be best understood and appreciated upon review of the following detailed description of the disclosure, taken in conjunction with the following drawings, where like numerals represent like elements, in which: 
           [0030]      FIG. 1  is a circuit schematic of a current mode hysteretic controller known to the inventor; 
           [0031]      FIG. 2  is a timing diagram of a current mode hysteretic controller known to the inventor; 
           [0032]      FIG. 3  is a circuit schematic in accordance with a first embodiment of the disclosure; 
           [0033]      FIG. 4  is a timing diagram in accordance with a first embodiment of the disclosure; 
           [0034]      FIG. 5  is a circuit schematic in accordance with a first embodiment of the disclosure of a PMOS current estimator; and, 
           [0035]      FIG. 6  is a method in accordance with a first embodiment of the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0036]      FIG. 3  is a circuit schematic in accordance with a first embodiment of the disclosure for a current mode voltage regulator. A simplified schematic of the controller is shown in  FIG. 3 . In this embodiment, the current in the coil for the positive current slope is not directly measured but it is estimated by the ‘Positive Slope Coil Current Estimator.’ The negative slope is measured via common current sensing circuitry marked as ‘CSn’ and ‘NMOS Current Sensing’ block.  FIG. 3  shows the positive slope estimation is evaluated from the “pull-up” device (e.g. PMOS transistor) and negative sensing from the “pull-down” device (e.g. NMOS transistor). Note that the first embodiment of the disclosure can be modified where the slope estimation is evaluated from the “pull-down” device (e.g. NMOS transistor), and the current sensing from the “pull-up” device (e.g. PMOS transistor). 
         [0037]      FIG. 3  shows a hysteretic current-mode controller  300 . The controller, which is preferably a buck converter  300 , consists of a SR flip-flop  305  with inputs SET  301  and RESET  302 . The SR flip-flop  305  provides a DUTY signal output  307  to pre-drive circuitry of the driver circuitry  310 . The signal VIN  315  provides power to the output circuit comprising a p-channel MOSFET pull-up device  320  and an n-channel MOSFET pull-down device  325 . The center node VLX is connected between the p-channel MOSFET  320  and n-channel MOSFET  325  providing a current IL to the output. The output node is connected to the inductor  340 , the output capacitor  345  for the output signal  350 , and output load  360 . 
         [0038]    A feedback network establishes a sensing scheme to current sensing circuit NMOS Current Sensing  330 . Current in the inductor coil  340  is measured via current sensing circuit NMOS Current Sensing CSn  337  when the NMOS is on. The circuit contains an Error amplifier  370 , with two input signals, feedback signal  365  and reference signal  367 ; the Error amplifier  370  is coupled to a compensation network. The error amplifier compares the output voltage with the reference voltage Vref and generates error signal vError. This signal is a base for two signals vError_H  375 A and vError_L  375 B which are shifted up and down from the vError by Voff/2 respectively. The signal vError_L is connected to a comparator  380 B producing an output signal SET  385 B. The signal vError_H  380 A is connected to a comparator  380 A producing an output signal Reset  385 A. The comparator  380 A receives a signal VILint  395  from the Positive Slope Coil Current Estimator  390 . The comparator  380 B receives a signal from the NMOS Current Sensing block  330 . The Positive Slope Coil Current Estimator  390  has three inputs of VOUT  350 , VIN  315 , and DUTY  307 . 
         [0039]      FIG. 4  shows the timing diagram  400  for the signals. The PMOS signal  410  and the NMOS signal  420  show the “ON” and “OFF” states of the output stage. The signal vError_H  430 , vError  440 , and vError_L  450  are shown during the timing cycle. The output voltage vILint  460  of the Positive Slope Coil Current Estimator  390  corresponds to the instantaneous current in the inductor during the PMOS period. 
         [0040]    The operation of the hysteretic buck converter includes a sequence of steps. The first step (a) PMOS is turned ON, and the current in the coil is being estimated in the estimator. The second step (b) The voltage vILint is increasing with the same shape as the current in the coil. The third step (c) When the vILint reaches the vError_H, the PMOS is turned OFF. The fourth step (d) NMOS is turned ON, and current sensing circuit measures the current. A fifth step (e) vILint  460  is connected to vError_L during the NMOS period. A sixth step (f) when the coil current reaches the vError_L, the NMOS is turned OFF. And, lastly the seventh step (g) the procedure then repeats to step (a). 
         [0041]      FIG. 5  is a circuit schematic in accordance with the first embodiment of the disclosure of the core estimator  390  shown in  FIG. 3 . The circuit  500 , showing the details of estimator  390 , contains two switches  520  and  525  which are turned ON when PMOS device  320  and NMOS  325  of  FIG. 3 ) are turned ON respectively. The core estimator  500  includes a transconductance block gm  530 , with inputs VIN  510  and VOUT  550  which provide current IC  560 . The output capacitor  545  is charged with the current IC  560  during PMOS period only. During the PMOS period the voltage vILint  527  is proportional to the instantaneous current in the coil. The capacitor  545  is connected to vError_L during NMOS period. 
         [0042]    To provide a signal with the same shape as the current in the coil, the following derivation illustrates the general behaviour. The following equation describes the general behaviour of the current in the coil. 
         [0000]    
       
         
           
             
               
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         [0000]    Given, the inductor voltage v L (t) does not vary in time, this can be simplified and replace v L  with Vin and Vout for each portion of the clock-cycle t 1  and t 2 .
 
For t 1  interval:
 
         [0000]    
       
         
           
             
               
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         [0000]    and for time interval t 2 : 
         [0000]    
       
         
           
             
               
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         [0000]    The voltages Vin and Vout are taken from the input and from the voltage feed-back node so no additional pin is necessary. For simple estimation of the current in the control circuit, a similar response that resembles the current in time variation is needed (as described in the prior section). A good candidate is a simple capacitor with basic equation of: 
         [0000]    
       
         
           
             
               
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         [0000]    This equation is similar to the original one for the current in the inductor. In order to get the same shape of the output voltage the capacitor must be charged with a current with the same shape as the voltage across the inductor (Vin−Vout). 
         [0000]    
       
         
           
             
               
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         [0000]    The equation for the voltage on capacitor resembles the equation for the current in the inductor. If the capacitor is charged with a current proportional to the (Vin−Vout) for interval t 1  or Vout for interval t 2 , then the same shape of the output voltage will be achieved, as the current in the coil. 
       Interval t 1 : 
       [0043]    
       
         
           
             
               
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         [0000]    and for time interval t 2 : 
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         [0000]    where gm is a trans-conductance which transfers the voltage to the current and it is assumed to be constant. Initial value v C (0) is the value where the charging started from. 
         [0044]      FIG. 6  is a method in accordance with the first embodiment of the disclosure. The hysteretic buck converter  600  providing a first step  610  ( a ) providing a hysteretic buck converter with a PMOS pull-up, a NMOS pull-down, a pre-drive circuit, a SR flip-flop, an inductor, a capacitor, an error amplifier, a compensation circuit, an NMOS Current Sensing block, a Positive Slope Coil Current Estimator, a SET comparator, and a RESET comparator, a second step  620  ( b ) estimating the current in the inductor when said PMOS transistor pull-up is turned ON, a third step  630  ( c ) increasing the voltage vILint which represents the current in the inductor (estimated inductor current), a fourth step  640  ( d ) turning off said PMOS transistor when the voltage vILint (estimated inductor current) reaches the high error voltage vError_H, the fifth step  650  ( e ) sensing the current when said NMOS transistor is turned ON, using said current sensing circuit, a sixth step  660  ( f ) evaluating the voltage vILint when connected to low error voltage vEiTor_L during this period of time, and a seventh step  670  ( g ) turning off said NMOS transistor when the coil current reaches the low error voltage vError_L. In the sequence, this is repeated, where the procedure then repeats to step (b)  620 . It should be noted that the description and drawings illustrate a method and system of a first process of evaluation of slope estimation as well as a second process for current sensing. This method can be modified by having the slope estimation process evaluated by the NMOS transistor, and the current sensing process sensed from the PMOS transistor. 
         [0045]    It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. The role of the transistors serve as “switches.” Hence it is in the spirit and scope of the application to have different types of switches from MOS switches, LDMOS switches to bipolar junction transistors. The method can include a reversal of the role of the “pull-up” transistor, and the “pull-down” transistor wherein it is in the spirit and scope of the invention to have a “negative slope inductor coil estimator.” For this methodology, the current estimator, for negative slope estimator, only requires an output voltage, Vout, as an input to the transconductance stage (e.g. GM stage since there is directly an output voltage across the inductor during the NMOS period of the operational cycle (e.g. note not the difference between the input and output voltage, Vin−Vout). For the positive slope estimator, both the input voltage Vin and the output voltage Vout are required for the input signals. 
         [0046]    It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the proposed methods and systems and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof. 
         [0047]    Other advantages will be recognized by those of ordinary skill in the art. The above detailed description of the disclosure, and the examples described therein, has been presented for the purposes of illustration and description. While the principles of the disclosure have been described above in connection with a specific device, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the disclosure.