Abstract:
In a switched-capacitor input sampling structure, a resistor connected in series with the input structure, but after the output of the input switch limits the noise bandwidth of the input structure. The selected placement of the resistor does not appreciably limit the slewing or settling time of downstream circuit elements, resulting in a low noise bandwidth, high speed system.

Description:
BACKGROUND 
     1. Field of the Invention 
     The invention relates to input structures for switched-capacitor circuits. More particularly, the invention relates to switched-capacitor input circuits for limiting input noise. Yet more particularly, the invention relates to input structures for switched-capacitor circuits which limit input noise while not appreciably distorting the sampled input signal and without degrading the settling time of circuits downstream of the input structure. 
     2. Related Art 
     Representative conventional switched-capacitor input structures are illustrated schematically in FIGS. 1 and 2. In both of these conventional switched-capacitor input structures, an input voltage V IN  is sampled onto. An input capacitor C IN  through switch S IN  during a first input phase. During a second input phase, switch S IN  changes state to disconnect the input voltage V IN  from capacitor C IN . Either the charge or the voltage accumulated on capacitor C IN  is then transferred from the input capacitor C IN  to a next stage of circuitry (not shown). In each of the circuits of FIGS. 1 and 2, the switch S SAMPLE  also switches state when the input structure switches between the first phase, referred to hereinafter as the sampling phase, and the second phase, referred to hereinafter as the hold phase. During the sample phase, switch S SAMPLE  is in a conductive state, while during hold phase, switch S SAMPLE  is in a substantially non-conductive state. Another switch S H  connects the input side of C IN  to a bias voltage V H  during hold phase and is substantially non-conducting during sample phase. Switches S IN , S H  and S SAMPLE  are controlled by a sampling clock (not shown). The clock signal may be connected to gate terminals of MOS transistors forming the switches. 
     In the circuit of FIG. 1 the voltage V IN  is sampled with respect to a bias voltage V B . In the circuit of FIG. 2 V IN  is sampled with respect to the offset voltage of op amp AMP, which will facilitate offset compensation of op amp AMP. When S SAMPLE  is in a substantially conducting state, i.e., sample phase, op amp AMP is connected in a unity gain configuration. Thus, any input offset voltage is subtracted from the voltage transferred to capacitor C IN . In this configuration, the input offset error voltage of op amp AMP is compensated because the inverting input of op amp AMP remains connected to input capacitor C IN  when switch S SAMPLE  is in a substantially non-conducting state, i.e., during hold phase. The input offset voltage previously subtracted from the voltage transferred is thus added back in during hold phase, fully compensating for the input offset voltage. 
     One important characteristic of these input structures is bandwidth. Components downstream of the input structures are usually required to have extremely wide bandwidths, in order to slew and settle quickly. For example, in the sample phase, sample and hold circuits or sigma-delta modulators are required to accurately track variations in the input signal. In addition, in hold phase, these circuits are required to settle rapidly. The input structure illustrated in FIG. 1 has a dominant pole at ##EQU1## The resistance R SWITCH  is the ON resistance of switch S IN , while the resistance R SAMPLE  is the ON resistance of switch S SAMPLE . Capacitance C S  is the value of capacitor C IN . The dominant pole of the circuit of FIG. 2 occurs at ##EQU2## In the definition of τ B , R SWITCH  and C S  are defined as above, while G M  is the transconductance of op amp AMP. As an example, for a switched capacitor input on a 12-bit analog-to-digital (A/D) converter sampling at a 10MHz rate, typical values achievable for the various components and typical target dominant pole frequencies are given in the table below. 
     
                       TABLE 1______________________________________             Value______________________________________  R.sub.SWITCH  10-50 Ω  R.sub.SAMPLE 100-500 Ω  C.sub.S       1-10 pF  G.sub.M       1-10 mA/V  ω.sub.A                20-400 MHz  ω.sub.B                20-400 MHz______________________________________ 
    
     In these prior art circuits, if the input voltage is noisy, then that noise is sampled by the input capacitor. Given a wide bandwidth system, the input noise is not significantly limited. Systems for certain applications require wide bandwidth for good distortion performance in the sample phase. In addition, systems typically are designed to have a bandwidth wide enough so that the system settles quickly enough during hold phase to suit a particular application. As a result, input noise may be sampled into the system, if not in some way limited or prevented from being present at the input. Sources of input noise can include thermal noise of a source circuit that drives the input voltage V IN  or noise from unrelated circuits coupling into the input voltage V IN . 
     In prior art circuits such as FIGS. 1 and 2, there is a tradeoff between noise and distortion depending on the value of R SWITCH . When the resistance R SWITCH  of switch S IN  is large, the bandwidth of the system is small and the system may not settle quickly enough. When R SWITCH  is small, the bandwidth of the system is large, and noise coupling may be introduced from the input voltage. The nominal value of R SWITCH  is a design parameter set by the designer, but the actual value of R SWITCH  during circuit operation varies substantially with the input voltage, V IN , producing distortion due to the input transfer function being non-linear. Typical prior art systems operating on an input signal having a spectral bandwidth of between 20 and 40 megahertz may have a bandwidth of approximately 400 megahertz to accommodate settling time requirements. However, the noise bandwidth of a system designed to the parameters described above is unacceptably large. 
     FIG. 3 schematically illustrates an example of a differential prior-art switched-capacitor input structure which samples an input voltage onto input capacitors C INP  and C INM  during the sample phase. The input voltage is impressed across the input terminals V INP  and V INM . The embodiment of FIG. 3 includes a differential sample switch S SAMPLE  which connect capacitors C INP  and C INM  together during the sample phase and also includes two additional switches, S SAMPLEP  and S SAMPLEM , which connect capacitors C INP  and C INM  to bias voltage V B  during the sample phase. Two switches, S HP  and S HM , are turned on during the hold phase to charge the input terminals of capacitors C INP  and C HM  to V HP  and V HM . In some implementations of this prior-art circuit, V HP  and V HM  may be at substantially the same potential. FIG. 4 illustrates another prior-art switched-capacitor input structure which is similar to the embodiment of FIG. 3. The embodiment of FIG. 4 differs from that of FIG. 3 in that a single switch, S H , is used in place of the two switches, S HP  and S HM , of the embodiment of FIG. 3. This single switch, S H , forces the input terminals of capacitors C INP  and C INM  to the same potential during hold phase by connecting them together. 
     FIG. 5 illustrates another prior-art differential switched-capacitor input structure. The circuit of FIG. 5 includes sample switches S SAMPLEP  and S SAMPLEM  which connect the amplifier AMP in unity-gain configuration during the sample phase in order to charge the input capacitors with respect to the offset voltage of the amplifier AMP. This allows offset compensation of the amplifier. Two switches, S HP  and S HM , are turned on during the hold phase to charge the input terminals of capacitors C INP  and C INM  to V HP  and V HM . In some implementations of this prior-art circuit, V HP  and V HM  may be at substantially the same potential. FIG. 6 illustrates another differential embodiment of a prior-art switched-capacitor input structure which is similar to the embodiment of FIG. 5. The embodiment of FIG. 6 differs from that of FIG. 5 in that a single switch, S H , is used in place of the two switches, S HP  and S HM , of the embodiment of FIG. 5. This single switch, S H , forces the input terminals of capacitors C INP  and C INM  to the same potential during hold phase by connecting them together. 
     FIGS. 7 and 8 schematically show prior art solutions to the noise coupling problems associated with FIG. 1. In FIG. 7, resistor R EXT  is added between the input voltage source and switch S IN  Resistor R EXT  is much larger than the resistance of switch S IN  and therefore dominates the input resistance. Thus, the external resistance dominates the pole ω A . However, non-linearities continue to plague the prior art systems. 
     The solution of FIG. 8 adds an external resistor R EXT  and external capacitor C EXT . By setting the values of the external capacitor and external resistor appropriately, the location of the pole ω B  can be set to suit a particular application. Here also, non-linearity plagues the system. 
     The drawbacks associated with the solutions of FIGS. 7 and 8 relate to the fact that when the external resistance is added upstream of the input switch S IN  the non-linear parasitic capacitances of the input switch become problematic. In other words, the non-linear parasitic capacitances of the input switch cause distortion. Typically the input switch S IN  is implemented as an MOS transmission gate switch. FIG. 9 schematically represents the input structure, showing some of the parasitic capacitances of a MOS-implemented transmission gate switch S IN  that cause non-linear behavior and distortion with the addition of the external resistance. 
     SUMMARY OF THE INVENTION 
     The present invention solves the problems identified in the conventional structures discussed above, as well as addressing such other problems and goals as will be apparent to those skilled in this art, by locating a bandwidth limiting resistor in the switched capacitor input structure downstream of an input sampling switch and upstream of circuits which receive the sampled signal from the switched capacitor. By locating additional resistances in accordance with the various aspects of the present invention, noise bandwidth is reduced without distorting the signal sampled on the input capacitor. 
     The present invention may be embodied as a switched capacitor input sampling structure having an output, comprising: an input switch having an input and an output; an input capacitor having a first plate connected to receive a signal from the output of the input switch and having a second plate connected to the output of the input sampling structure; and a resistor connected in series with the input structure, after the output of the input switch. Numerous variations are possible, in which a resistance is located in or distributed amongst one or more different portions of the input signal path. Further variations are possible in configurations for the biasing switches which bias the input or output side of the input capacitor during different phases of the operation of the input structure. 
     For example, the structure recited above, having a sample phase and a hold phase, may further comprise: a first biasing switch connected between the first plate of the input capacitor and a first biasing signal, the first biasing switch conducting during the hold phase and substantially non-conducting during the sample phase; wherein the input switch is conducting during the sample phase and substantially non-conducting during the hold phase. In a further variation, there is provided an op amp having an inverting input connected to receive a voltage from the second plate of the input capacitor and having an output; and a sampling switch connected between the output of the op amp and the inverting input of the op amp, the sampling switch conducting during the sample phase and substantially non-conducting during the hold phase. In yet another variation, there is provided a sampling switch connected to bias the second plate of the input capacitor to a second biasing voltage when the sampling switch is conducting, the sampling switch conducting during the sample phase and substantially non-conducting during the hold phase. In a variation having a specific resistor placement, the resistor is disposed in a branch of the structure in series between the output of the input sampling structure and the sampling switch. In another variation having a specific resistor placement, the resistor is disposed in a branch of the structure in series between the input switch and the first plate of the input capacitor. Finally, the structure may further comprise a second biasing switch, substantially larger than the first biasing switch, connected between the output of the input switch and the first biasing signal, the second biasing switch conducting during the hold phase and substantially non-conducting during the sample phase. 
     In a differential switched capacitor input sampling structure having a differential output, having a first branch and a second branch, the first and second brances may comprise corresponding ones of: first and second input switches, each having an input and an output; first and second input capacitors, each having a first plate connected to receive a signal from the output of a corresponding one of the first and second input switches and each having a second plate, the second plates of the first and second input capacitors forming the differential output; and first and second resistors, each connected in series with corresponding ones of the first and second branches. A variation of this structure, having a sample phase and a hold phase, may further comprise: a biasing switch connected between the first plate of the first input capacitor and the first plate of the second input capacitor, the biasing switch conducting during the hold phase and substantially non-conducting during the sample phase; wherein the input switch is conducting during the sample phase and substantially non-conducting during the hold phase. This structure may further comprise: an op amp having an inverting input connected to receive a voltage from the second plate of the first input capacitor, having a non-inverting input connected to receive a voltage from the second plate of the second input capacitor, having a non-inverting output and having an inverting output; a first sampling switch connected between the non-inverting output of the op amp and the inverting input of the op amp, the first sampling switch conducting during the sample phase and substantially non-conducting during the hold phase; and a second sampling switch connected between the inverting output of the op amp and the non-inverting input of the op amp, the second sampling switch conducting during the sample phase and substantially non-conducting during the hold phase. This structure may include variations with specific placement of resistors, such as wherein the first and second resistors are disposed in branches of the structure in series between corresponding outputs of the input sampling structure and corresponding sampling switches, or wherein the first and second resistors are disposed in branches of the structure in series between corresponding first and second input switches and the first plate of corresponding input capacitors. The structure may be further varied by including a second biasing switch, substantially larger than the first biasing switch, connected between the output of the first input switch and the output of the second input switch, the second biasing switch conducting during the hold phase and substantially non-conducting during the sample phase. 
     In a differential switched capacitor input sampling structure having a differential output, having a first branch and a second branch, the first and second branches may comprise corresponding ones of: first and second input switches, each having an input and an output; first and second input capacitors, each having a first plate connected to receive a signal from the output of a corresponding one of the first and second input switches and each having a second plate, the second plates of the first and second input capacitors forming the differential output; first and second sampling switches connected to bias the second plate of corresponding ones of the first and second input capacitors each to a biasing signal when the first and second sampling switches are conducting, the first and second sampling switches conducting during the sample phase and substantially non-conducting during the hold phase; and first and second resistors, each connected in series with corresponding ones of the first and second branches. Finally, this structure may be varied by providing first and second biasing switches connected respectively between the first plate of the first and second input capacitors and first and second biasing signals, the biasing switch conducting during the hold phase and substantially non-conducting during the sample phase. 
     Other variations will be apparent to those skilled in this art. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings in which like reference designations indicate like elements: 
     FIG. 1 is a schematic representation of a conventional, single-ended switched-capacitor input structure; 
     FIG. 2 is a schematic representation of an alternate conventional, single-ended switched-capacitor input structure; 
     FIG. 3 is a schematic representation of a conventional, differential switched-capacitor input structure similar to the single-ended structure of FIG. 1; 
     FIG. 4 is a schematic representation of an alternate conventional, differential switched-capacitor input structure; 
     FIG. 5 is a schematic representation of a conventional, differential switched-capacitor input structure similar to the single-ended structure of FIG. 2; 
     FIG. 6 is a schematic representation of an alternate conventional, differential switched-capacitor input structure; 
     FIG. 7 is a schematic representation of an improved conventional switched-capacitor input structure; 
     FIG. 8 is a schematic representation of an alternate improved conventional switched-capacitor input structure; 
     FIG. 9 is a schematic representation of either of the input structures of FIGS. 7 or 8, showing the effects of parasitic capacitances associated with input switch S IN  ; 
     FIGS. 10, 11, 12 and 13 are schematic representations of input structures according to various aspects of the invention, embodied in structures where input sampling is performed relative to a bias voltage V B  ; and 
     FIGS. 14, 15, 16, 17, 18 and 19 are schematic representations of input structures according to various aspects of the invention, embodied in structures where input sampling is performed relative to a virtual ground formed at the input to an op amp. 
    
    
     DETAILED DESCRIPTION 
     The present invention will now be better understood upon reading in connection with the figures the following detailed description of illustrative embodiments thereof. 
     FIG. 10 illustrates one embodiment of the invention. As seen in the schematic representation of FIG. 10, the circuit of FIG. 10 has five branches indicated by resistors R1-R5, in which a resistance may be introduced to produce bandlimiting in accordance with various aspects of the invention. Any one or more of the five resistors R1-R5 may have a non-zero value, and up to four of the five resistors R1-R5 may have a zero value, i.e. be essentially not present. The primary advantage of this invention over the prior art shown in FIG. 1 is that the bandlimiting resistance interacts only with the linear capacitor C IN , and not with the nonlinear parasitic capacitances of the input switch S IN . As discussed previously, the bandlimiting resistance in the prior art circuit of FIG. 1 precedes switch S IN  and therefore interacts with the nonlinear parasitics of S IN . This results in distortion of the voltage across the input capacitor C IN . The present invention avoids this interaction by placing the bandlimiting resistance after the input switch S IN . Therefore, the voltage across the input capacitor C IN  remains undistorted. 
     It should be appreciated that switch S H  also has nonlinear parasitics that can contribute to distortion. Specifically, the nonlinear parasitic capacitances of switch S H  can interact with resistor R1 to cause distortion in the voltage across capacitor C IN  during the sample phase. Therefore, either resistor R1 should be kept small or the nonlinear parasitic capacitances of switch S H  should be minimized, i.e. the devices used to implement switch S H  should be kept small. 
     It should be also appreciated that when the circuit is configured in hold phase, capacitor C IN  is charged to V H  through switch S H  and charge is transferred through resistors R2 and R3 to the rest of the circuit (not shown). Therefore to minimize the hold settling time, it is desirable to keep R2 and R3 as small as possible. Furthermore, during hold phase, the parasitic capacitances of switch S IN  must be charged to V H  through switch S H  and resistor R1. Therefore, for the additional reason of minimizing the hold settling time, it is desirable to keep R1, in addition to R2 and R3, as small as possible. This may be accomplished by bandlimiting primarily with resistors R4 and R5, i.e. using larger values of resistance for R4 and R5, in situations where hold settling time is important. 
     FIG. 11 illustrates another embodiment of the present invention which is useful in situations where hold settling time is important. This embodiment also reduces the distortion caused by the interaction of resistor R1 and the nonlinear parasitic capacitances of switch S H  of FIG. 10. The switch S H  in the circuit of FIG. 10 has been divided into two switches, S HBIG  and S HSMALL . Switch S HBIG  provides rapid charging of the parasitic capacitances of switch S IN  during the hold phase. Similarly, switch S HSMALL  permits the rapid charging of C IN  to V H  and the transfer of charge from C IN  to the rest of the circuit (not shown). The devices used to implement switch S HSMALL  should be kept small to minimize nonlinear parasitic capacitances and avoid distortion caused by the interaction of resistor R1 and the parasitic capacitances of switch S HSMALL  during sample phase. 
     FIG. 12 and 13 illustrate differential embodiments of the invention. FIG. 12 corresponds to prior art FIG. 3, and FIG. 13 corresponds to prior art FIG. 4. Resistors R1P-R6P and R1M-R6M of FIG. 12 and 13 illustrate how bandlimiting resistance can be added to the prior art circuits in FIG. 3 and FIG. 4 to implement various differential embodiments of the present invention. Resistors R6P and R6M in FIG. 12 and 13 bandlimit the differential noise of the input signal while resistors R1P-R5P and R1M-R5M bandlimit both the differential noise and the common-mode noise. 
     FIG. 14 illustrates another embodiment of the invention. As seen in the schematic representation of FIG. 14, the circuit of FIG. 14 has four branches indicated by resistors R1-R4, in which a resistance may be introduced to produce bandlimiting in accordance with various aspects of the invention. Any one or more of the four resistors R1-R4 may have a non-zero value, and up to three of the four resistors R1-R4 may have a zero value, i.e. be essentially not present. 
     The primary advantage of this invention over the prior art shown in FIG. 2 is that the bandlimiting resistance interacts only with the linear capacitor C IN , and not with the nonlinear parasitic capacitances of the input switch S IN . As discussed previously, the bandlimiting resistance in the prior art circuit of FIG. 2 precedes switch S IN  and therefore interacts with the nonlinear parasitics of S IN . This results in distortion of the voltage across the input capacitor C IN . The present invention avoids this interaction by placing the bandlimiting resistance after the input switch S IN . Therefore, the voltage across the input capacitor C IN  remains undistorted. 
     It should be appreciated that switch S H  also has nonlinear parasitics that can contribute to distortion. Specifically, the nonlinear parasitic capacitances of switch S H  can interact with resistor R1 to cause distortion in the voltage across capacitor C IN  during the sample phase. Therefore, either resistor R1 should be kept small or the nonlinear parasitic capacitances of switch S H  should be minimized, i.e. the devices used to implement switch S H  should be kept small. 
     It should be also appreciated that when the circuit is configured in hold phase, capacitor C IN  is charged to V H  through switch S H  and charge is transferred through resistors R2 and R3 to the rest of the circuit (not shown). Therefore to minimize the hold settling time, it is desirable to keep R2 and R3 as small as possible. Furthermore, during hold phase, the parasitic capacitances of switch S IN  must be charged to V H  through switch S H  and resistor R1. Therefore to minimize the hold settling time it also desirable to keep R1, in addition to R2 and R3, as small as possible. This may be accomplished by bandlimiting primarily with resistor R4, i.e. using a larger value of resistance for R4, in situations where hold settling time is important. 
     The resistor R4 in FIG. 14 interacts with a parasitic capacitance, C p , at the input node of op amp AMP to form a second pole. The frequency of this second pole, ƒ 2 , is determined by R4 and C p  as follows:ƒ 2  =1/(2πR4·C p ). This pole destabilizes op amp AMP. To maintain sufficient stability it is necessary that the value of R4 be kept small with respect to the closed-loop bandwidth, BW AMP , of op amp AMP as defined in the following relationship: R4&lt;&lt;1/(2πBW AMP  C P ). It is, however, also desirable as discussed earlier to have resistance R4 be as large as possible for noise limiting purposes. To maintain sufficient stability, it may be necessary for the value of R4 to be smaller than would otherwise be desired to bandlimit the input noise. 
     FIG. 15 illustrates another embodiment of the present invention which is useful in situations where hold settling time is important, and where resistance of R4 can not be made high enough to bandlimit the input signal without destabilizing op amp AMP. The embodiment in FIG. 15 is used to further bandlimit the input signal by increasing the value of R1. This embodiment reduces the distortion caused by the interaction of resistor R1 and the nonlinear parasitic capacitances of switch S H  of FIG. 14. The switch S H  in the circuit of FIG. 14 has been divided into two switches, S HBIG  and H SMALL . Switch S HBIG  provides rapid charging of the parasitic capacitances of switch S IN  during the hold phase. Similarly, switch S HSMALL  permits the rapid charging of C IN  to V H  and the transfer of charge from C IN  to the rest of the circuit (not shown). The devices used to implement switch S HSMALL  should be kept small to minimize nonlinear parasitic capacitances and avoid distortion caused by the interaction of resistor R1 and the parasitic capacitances of switch S HSMALL  during sample phase. 
     FIG. 16, 17, 18 and 19 illustrate differential embodiments of the invention. FIG. 16 corresponds to prior art FIG. 5, and FIG. 17 corresponds to prior art FIG. 6. Resistors R1P-R4P and R1M-R4M of FIG. 16, 17, 18, and 19 illustrate how bandlimiting resistance can be added to the prior art circuits in FIG. 5 and FIG. 6 to implement differential embodiments of the present invention. Resistors R1P-R4P and R1M-R5M bandlimit both the differential noise and the common-mode noise of the input signal. 
     The resistors R4P and R4M in FIG. 16 and in FIG. 17 interact with parasitic capacitance at the input node of op amp AMP to form a second pole. The frequency of this second pole,ƒ 2 , is determined by R4P, R4M, and the parasitic capacitance as follows:ƒ 2  =1/(2πR4·C p ), where R4 represents the value of resistors R4P and R4M and C p  represents the value of the parasitic capacitance between the input terminals of op amp AMP. This pole destabilizes op amp AMP. To maintain sufficient stability it is necessary that R4 be kept small with respect to the closed-loop differential bandwidth, BW AMP , of op amp AMP as defined in the following relationship: R4&lt;&lt;1/(2πBW AMP  C P ). It is, however, also desirable as discussed earlier to have the value, R4, of resistors R4P and R4M be as large as possible for noise limiting purposes. To maintain sufficient stability, it may be necessary for R4 to be smaller than would otherwise be desired to bandlimit the input noise. 
     The embodiments of the present invention in FIG. 18 and 19 incorporate the technique employed in the single-ended embodiment of FIG. 15, and are similarly useful in situations where hold settling time is important, and where R4 can not be made high enough to bandlimit the input signal without destabilizing op amp AMP. The embodiment in FIG. 18 and 19 are used to further bandlimit the input signal by increasing the value of R1P and R1M. These two embodiments reduce the distortion caused by the interaction of resistors R1P and R1M with the nonlinear parasitic capacitances of switches S HSMALLP  and S HSMALLM  in FIG. 18 and switch S HSMALL  in FIG. 19. 
     The embodiments of the present invention in FIG. 18 and 19 incorporate the technique employed in the single-ended embodiment of FIG. 15, and are similarly useful in situations where hold settling time is important. The embodiments of FIG. 18 and 19 reduce hold settling time by bandlimiting with resistor R1P and R1M while avoiding distortion caused by the interaction of resistors R1P and R1M with the nonlinear parasitic capacitances of switches  SHSMALLP  and S HSMALLM  in FIG. 18 and switch S HSMALL  in FIG. 19. 
     The present invention has now been described in connection with a number of specific embodiments thereof. However, numerous modifications which are contemplated as falling within the scope of the present invention should now be apparent to those skilled in the art. For example, the invention relates to the input sampling structure and the circuitry downstream of this input structure is not important. The circuit in which the inventive structure is used could be a sample and hold circuit or an integrator, or other. Therefore, it is intended that the scope of the present invention be limited only by the scope of the claims appended hereto.