Abstract:
In various embodiments, a tiered gate structure transistor is provided including a source, a drain, and a gate between the source and the drain. The tiered gate structure transistor including a gate foot having a top portion and sidewalls. A gate head is attached to the top portion of the gate foot. A passivation layer extends along and directly contacts an uppermost surface of the source, and extends along and directly contacts an uppermost surface of the drain, the passivation layer surrounds the sidewalls of the gate foot such that the top portion is not covered by the passivation layer and such that the passivation layer surrounding the sidewalls supports the gate head.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 11/517,685 by Milosavljevic, et al., entitled PASSIVATED TIERED GATE STRUCTURE TRANSISTOR AND FABRICATION METHOD, filed on Sep. 8, 2006 now U.S. Pat. No. 7,608,497 which is related to U.S. patent application Ser. No. 11/150,439, issued as U.S. Pat. No. 7,439,166, by Milosavljevic, et al., entitled METHOD FOR PRODUCING TIERED GATE STRUCTURE DEVICES, filed on Jun. 11, 2005, and to U.S. patent application Ser. No. 11/517,791, filed Sep. 8, 2006, by Milosavljevic et al.; entitled TIERED GATE DEVICE WITH SOURCE AND DRAIN EXTENSIONS, all herein incorporated by reference in their entireties. 
    
    
     BACKGROUND 
       FIG. 1  shows a cross section side view of a prior art T-gate structure transistor  100 . The T-gate structure transistor  100  has a T-shaped gate  125 , which is often referred to as simply a T-gate. In general a T-gate is any device which has a narrow gate foot  65  and a relatively wider gate head  165 . Sometimes the same or similar structures are referred to as Y-gates and/or mushroom gates due to their final shape. In yet another instance, a gamma-gate or asymmetric gate can be produced. A gamma-gate has a cross section similar to the Greek letter gamma. Accordingly, the terms T-gate, Y-gate, mushroom gate, gamma-gate, and asymmetric gate refer to a tiered gate structure with a narrow gate foot  65  and a relatively wider gate head  165 . In this disclosure the term T-gate, the most general and widely used term to refer to such tiered gate structure devices, is intended to encompass all of these structural variations. 
     Most T-gate processes utilize electron beam lithography to produce short gate length devices. While gate lengths less than 100 nanometers are commonly achievable, the short height of the gate foot  65  (the distance between the surface of the substrate  110  and the bottom of the gate head  165 ) required to produce such short gate lengths, creates unwanted parasitics between the gate head  165  and a source  120 , and between the gate head  165  and a drain  130 , indicated as C gs  and C gd , respectively. This occurs because of the aspect ratio limitation between feature size and resist thickness in electron beam lithography. Electrons undergo forward and back scattering during exposure which limit the minimum feature size to around half of the resist thickness at a 50 kV acceleration voltage. This short separation also hinders nitride coverage of the gate structure  125  during passivation. 
     Traditional fabrication methods of the T-gate structure  125  are performed with one or two exposure passes. In the two exposure pass method, during the first exposure, the top resist is exposed to define the gate head  165 . The lower resist which will define the gate foot  65 , is partially exposed in the first exposure, but not enough to develop it. The top resist is developed and a second exposure is used to define the gate foot  65 . This creates a history on the lower resist layer, which can cause non-uniformities in the gate foot  65  to occur across the wafer. 
     In addition to non-uniformities in the gate foot  65 , voids  167  and  168  will form on either side of the gate foot  65  during metal evaporation. The voids  167  and  168  extend upward between the gate foot  65  and gate head  165  and can present a reliability problem for the T-gate structure transistor  100 . Also, a downward extending recess  169  will form in the top of the gate head  165  during metal evaporation. The recess  169  may also present a reliability problem for the T-gate structure transistor  100 . 
     Once the T-gate structure transistor  100  is formed on the substrate  110 , a passivation layer is typically formed on the substrate  110  around the T-gate to protect the surface of the substrate  110 . For example, the passivation layer can insulate the surface of the substrate  110  from the ambient environment and prevent the surface from oxidizing. The passivation layer may be a nitride layer formed on the substrate  110  by using a plasma enhanced chemical vapor deposition process. Because the gate head  165  overhangs the gate foot  65 , the passivation layer may be non-uniform under the gate head  165  around the gate foot  65 . Consequently, the surface of substrate  110  under the gate head  165  is less protected, which may result in reliability and performance problems in a T-gate transistor including the T-gate. Moreover, the non-uniformity of the passivation layer around the gate foot  65  may increase the capacitance between the gate head  165  and the source  120 , as well as the capacitance between the gate head  165  and the drain  130 . These increases in capacitance may degrade the frequency response of the T-gate transistor. 
     In light of the above, there exists a need to improve passivation coverage of a substrate around the gate foot of a T-gate structure. Further, there exists a need to reduce the gate to source capacitance and the gate to drain capacitance of a T-gate structure transistor. 
     SUMMARY 
     In various embodiments, a tiered gate structure transistor is provided including a source, a drain, and a gate between the source and the drain. The tiered gate structure transistor including a gate foot having a top portion and sidewalls. A gate head is attached to the top portion of the gate foot. A passivation layer extends along and directly contacts an uppermost surface of the source, and extends along and directly contacts an uppermost surface of the drain, the passivation layer surrounds the sidewalls of the gate foot such that the top portion is not covered by the passivation layer and such that the passivation layer surrounding the sidewalls supports the gate head. 
     In various embodiments, a tiered gate structure transistor is provided including a source, a drain, and a gate between the source and the drain. The tiered gate structure transistor includes a gate foot having a top portion, the gate foot having a conductive layer. A passivation layer extends along an uppermost surface of the source and extends along an uppermost surface of the drain and on the gate foot and is recessed from the top portion of the gate foot such that the top portion is not covered by the passivation layer. The passivation layer directly contacts the uppermost surface of the source and the uppermost surface of the drain and surrounding sidewalls of the gate foot. A gate head is attached to the top portion of the gate foot and a portion of the passivation layer, wherein the passivation layer directly contacts the uppermost surface of the source and the uppermost surface of the drain and surrounding the sidewalls of the gate foot providing an additional support to the gate head and increasing a structure integrity of the tiered gate structure transistor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The features and advantages of the present invention will be better understood with regard to the following description, appended claims, and accompanying drawings where: 
         FIG. 1  shows a cross section side view of a prior art T-gate structure transistor. 
         FIGS. 2A-2C  are simplified illustrations in cross sectional side view illustrating fabrication of a gate foot of a T-gate device in accordance with an implementation of the present invention. 
         FIGS. 3A-3C  are simplified illustrations in cross sectional side view illustrating fabrication of a gate head of a T-gate device in accordance with an implementation of the present invention. 
         FIG. 4  is a cross section side view of a partially fabricated Y-gate structure transistor. 
         FIGS. 5A and 5B  are simplified illustrations in cross sectional side view illustrating fabrication of a gate foot of a T-gate device in accordance with an implementation of the present invention. 
         FIGS. 6A and 6B  are simplified illustrations in cross sectional side view illustrating fabrication of a gate head of a gamma gate device (not shown) in accordance with an implementation of the present invention. 
         FIG. 7  shows a cross section side view of a prior art T-gate structure transistor. 
         FIGS. 8A-8E  are simplified illustrations in cross sectional side view illustrating fabrication of a gate head of a T-gate device in accordance with an implementation of the present invention. 
     
    
    
     DESCRIPTION 
     In the description of the invention that follows, like numerals or reference designators will be used to refer to like parts throughout. Furthermore, the FIGS. are for illustrative purposes and are not necessarily to scale. 
     Disclosure of Related Application Ser. No. 11/150,439 
       FIGS. 2A-2C  are simplified illustrations in cross sectional side view illustrating fabrication of a gate foot  265  of a T-gate device (not shown) in accordance with an implementation of the present invention.  FIG. 2A  shows a substrate  210  with two dissimilar resist layers  240  and  250  overlying the source  220 , the drain  230 , and the substrate  210 . The dissimilar resist layers  240  and  250  are selected so that they are based on different solvents and will not intermix. For example, the lower resist layer  240  may be copolymer resist such as MMA/MAA, and the upper resist layer  250  may be PMMA 950K. The lower resist layer  240  is a high sensitivity resist while the upper resist layer  250  is a low sensitivity resist. It is possible in some implementations to use a single resist layer rather than two. 
     A first exposure (indicated as an arrow above a gaussian curve at the top of  FIG. 2A ) with a high acceleration e-beam having a single peak gaussian like profile defines a narrow gate foot opening  258  (shown in  FIG. 2B ) in the mask defined by upper and lower resist layers  255  and  245  (shown in  FIG. 2B ). The exposure acceleration voltage will depend on the desired thicknesses and types of resist in the upper and lower resist layers  250  and  240 . The exposure acceleration voltage indicated in  FIG. 2A  by the arrow, may be about 50 kV, for example. 
     After the first exposure, the resist layers  250  and  240  are developed using two different developers. The first developer does most of the developing of the upper resist layer  250 , while the second developer is selective to develop only the lower resist layer  240 . Thus, an under cut of the upper resist layer  255  by the lower resist layer  245  is possible to leave a well defined wider opening  258   b  in the lower resist layer  245  adjacent the substrate  210 , with the upper resist layer  255  overhanging the lower resist layer  245 , as shown in  FIG. 2B . The narrower opening  258   a  in the upper resist layer  255  defines the width of the gate foot  265 , i.e. the gate length, on the substrate  210 , shown in  FIG. 2C . 
     Shown in  FIG. 2C , a gate foot  265  is formed in the opening  258 . An optional gate etch may be performed with a wet etch, to etch slightly into the substrate  210  prior to formation of a gate foot  265 . The wider opening  258   b  (shown in  FIG. 2B ) in the lower resist layer  245  allows a uniform gate etch (not shown) across the surface of the substrate  210  where the gate foot  265  attaches to the substrate  210 . In addition, it allows the gate etch and gate foot formation with a single mask formed by resist layers  255  and  245 . Deposition of the gate foot material layer  260  results in the formation of the gate foot  265  on the substrate  210  through the opening  258  in the mask formed by the resist layers  255  and  245 . The gate material is a conductor material, which typically is a metal such as gold, TiPt, Al, chrome, or the like. 
     A lift-off process (known in the art) removes the gate foot material layer  260  with the removal of the resist layers  245  and  255 . After the lift-off process, the width (gate length) of the gate foot  265  and the height of the gate foot  265  may be measured, prior to formation of the gate head  365  (shown in  FIG. 3C ). This allows the gate length to be measured early in the manufacturing process, even in situ if desired, without requiring destruction of the T-gate device to perform the measurement. The gate etch length and the source-to-gate spacings can also be measured at this time. 
     Also, electrical measurements of the gate foot  265  may be conducted prior to completion of the T-gate device. For example, DC measurements may be made to determine if the gate foot  265  is functioning properly. Thus, it is possible to make measurements of the transconductance, resistance, etc., prior to completing fabrication of the T-gate device. 
       FIGS. 3A-3C  are simplified illustrations in cross sectional side view illustrating fabrication of a gate head  365  of a T-gate device (not shown) in accordance with an implementation of the present invention. After formation of the gate foot  265 , the gate head  365  is formed. Three layers of resist  370 ,  380 , and  390  are deposited over the gate foot  265 . Dissimilar resists can be used so that adjacent resist layers do not intermix. The lower resist layer  370  is deposited thick enough to cover the gate foot  265  and may be a medium sensitivity resist, such as PMMA 495k. The middle resist layer  380  acts as a spacer between upper and lower resist layers  390  and  370  and can be relatively thick as compared to resist layers  390  and  370 . The middle resist layer  380  may be a high sensitivity resist of copolymer, such as MMA(17.5)/MAA. The upper resist layer  390  can be an imaging layer and may be a medium sensitivity resist, such as PMMA 495k. 
     A second exposure, (indicated as three arrows above three gaussian curves at the top of  FIG. 3A ) exposes resist layers  390 ,  380 , and  370  shown in  FIG. 3A . After exposure, the resist layers  390 ,  380 , and  370  are developed leaving an opening  398  in the mask formed by the resist layers  395 ,  385 , and  375  as shown in  FIG. 3B . Although it is possible to use a single peak gaussian like profile to define the opening  398 , in the implementation of  FIG. 3A  the e-beam exposure may use overlapping sidelobe doses with a light centerline dose (as indicated by the smaller gaussian curve at the top of  FIG. 3A ). The resulting exposure forms a gaussian distribution in the resist layers  370 ,  380 , and  390 . This is depicted in  FIG. 3A  as three overlapping gaussian like profiles. For this second exposure, it is possible to use a low voltage, such as 20 kV. As discussed further below with reference to  FIG. 3C , the exposure energy and the develop time are selected so that the top surface  265   t  of the gate foot  265  is not covered by resist layers  390 ,  380  or  370  after developing, but does leave some of the lower resist layer  370  next to the gate foot  265 . Thus, the lower resist layer  370  is not developed all the way through to the substrate  210 , or expose the source  220  or drain  230 . Instead, some of the lower resist layer  370  will remain adjacent the sides of the gate foot  265  and over the source  220  and drain  230  after developing. 
     Turning to  FIG. 3B , after second exposure, a developer is selected which removes the exposed portion of the upper resist layer  395  and part of the middle resist layer  385 . For example, Methyl-isobutyl-ketone or MIBK may be used to remove the exposed portion of an upper resist layer  395  formed of PMMA and part of the exposed portion of a middle resist layer  385  formed of MMA(17.5)/MAA copolymer. Next the developed portion of the middle resist layer  385  of MMA(17.5)/MAA copolymer is removed with a PMGEA:ETOH (1:5) solution. This solution does not affect the PMMA of the lower resist layer  375  or the upper resist layer  395 . A dimple  378  in the lower resist layer  375  is formed using MIBK developer to uncover the top of the gate foot  265 . The second exposure energy, the type and strength of the developer, and the develop times, are selected to ensure that only a top portion  265   t  of the gate foot  265  is uncovered without uncovering the substrate layer  210 , the source  220 , or the drain  230 . 
     It should be noted that although the above implementation is discussed with reference to exposure followed by the develop stages, it is possible in other implementations to perform the exposure and develop of resist layers  390 ,  380 , and  370  in one or more alternating exposure and develop stages. In some implementations, it is possible to inspect resist layer  375  to determine if the top of the gate foot  265  is uncovered, before deposition of the gate head  365 . If it is not, an additional exposure and/or develop may be performed. The gate foot  265  is distinguishable from the resist by inspection, such as with an electron microscope, or other inspection tool. As such, it is possible to verify in situ whether the processes parameters, such as for example the exposure dosages and develop times are providing the best possible process uniformity. This provides process feedback that allows refinement of the parameters without having to complete fabrication of the device. It also allows for remedial action prior to complete fabrication of the device. 
     In one possible implementation, after developing the lower resist layer  375  to uncover a top portion of the gate foot  265 , an etch may be performed to remove any surface passivation, or oxidation, from the top portion of the gate foot  265  prior to gate head deposition. This ensures good electrical properties at the interface of the gate foot  265  and the gate head  365 . 
     The resist profile formed in the resist layers  395 ,  385 , and  375  define the gate head  365 . Since a continuous profile faces the deposition source, during deposition, no voids will form between the gate foot  265  and the gate head  365 . The gate head material may be deposited by various deposition techniques known in the art, such as for example by metal evaporation, sputtering, or other deposition technique. The opening  398  in the mask formed by resist layers  395 ,  385 , and  375  defines the gate head  365  during the gate head deposition process. After deposition, the gate head material layer  350  is removed with a lift-off process by stripping the resist layers  375 ,  385 , and  395  with a solvent, such as acetone. Other resists, developers, and stripper solutions are possible, but should be compatible with the particular substrate material being utilized, i.e. InP, GaAs, GaN, Si, SiC, etc. 
     Turning to  FIG. 4 , certain implementations of the present invention allow for reduced parasitic capacitances as compared to a conventional T-gate formed with conventional processes. The embodiment of  FIG. 4  is sometimes also referred to as a Y-gate structure. The lower resist layer  475  can be deposited over the gate foot  465   f  with a greater thickness than when forming the entire gate structure with one deposition, such as metallization. This increases the distance between the gate head  465   h  and the source  420  and between the gate head  465   h  and the drain  430 , thereby decreasing the gate-to-source and the gate-to-drain parasitic capacitances. Thus, in addition to reducing voids, reduced parasitic capacitances are achievable. 
     The e-beam exposure profile (not shown) is selected to provide a more narrow profile through the lower resist layer  475  to the gate foot  465   f . As in the above implementation, the upper resist layer  495  and gate material layer  450  are removed in a lift-off process when the middle resist layer  485  is stripped. 
       FIGS. 5A and 5B  are simplified illustrations in cross sectional side view illustrating fabrication of a gate foot  565  of an asymmetric gate etch device (not shown) in accordance with an implementation of the present invention. An asymmetric gate or gamma gate is illustrated in U.S. Pat. No. 5,693,548, by Lee, et al., entitled METHOD FOR MAKING T-GATE OF FIELD EFFECT TRANSISTOR, issued Dec. 2, 1997, herein incorporated by reference. In the implementation of  FIGS. 5A-6B , the gate etch of the substrate  510  etch is asymmetric, with the gate foot  565  being deposited on the substrate  510  closer to the source  520  side of the gate etch. This can improve the breakdown voltage by spreading the space charge layer on the drain side of the gate. Along with this, the short distance between the gate foot  565  and the source  520  reduces the source resistance. This structure can be created by adding a light exposure on the drain side of the gate foot exposure as indicated in  FIG. 6A  (as indicated by an arrow above the smaller gaussian curve  517   c  at the top of  FIG. 6A ). The exposure dose should be light enough to remove the underlying copolymer layer but not the overlying PMMA 950K layer when developed. 
     Referring to  FIGS. 5A and 5B , as above, two dissimilar resist layers  550  and  540  are exposed with an e-beam  515   a - c . In this implementation, in forming the gate foot  565 , the e-beam has a distribution with a larger dose  515   a  for developing the upper resist layer  550 , and lighter doses  515   b  and  515   c  for developing the lower resist layer  540  delivered at the side of the larger dose  515   a . For example, a total dose of 50 kV with the lighter doses  515   b  and  515   c  having peaks aligned to the right side of the peak of the larger dose  515   a  (indicated as three arrows above three gaussian curves at the top of  FIG. 5A ). 
     The larger dose  515   a  defines the opening  558   a  through the upper resist layer  555 , while the lighter doses  515   b  and  515   c  define an off set opening  558   b  in the lower resist layer  545 . The lighter doses  515   b  and  515   c  develop the copolymer of the lower resist layer  545  and leave behind the PMMA of the upper resist layer  555 . This is due to the relative sensitivities in developing of the two resists layers  555  and  545 . As shown in  FIG. 5B , the exposure pattern  515   a - c  can be used to create the asymmetric etch and provide a gate foot  565  that is off set away from the drain  530 . 
     Turning to  FIGS. 6A and 6B , the gate head  665  is formed on the gate foot  565 , off set from the gate foot  565 . Since the gate foot  565  and the gate head  665  are formed with separate exposures and depositions, the relative placement of the gate head  665  with respect to the gate foot  565  may be controlled. As above, three resist layers  670 ,  680 , and  690  are deposited over the gate foot  565 . The three resist layers are exposed with several e-beam doses (indicated as three arrows above three gaussian curves at the top of  FIG. 6A ). This defines an opening  598  in the resist layers  695 ,  685 , and  675 . The opening  598  is formed similar to the opening  398  discussed above with reference to  FIG. 3B . Although it is possible to use a single, or a double peak gaussian like profile, in the implementation of  FIG. 6A  the e-beam exposure takes place using several doses, with one  517   b  having its peak centered over the gate foot  565  and another  517   a  having its peak off set to a side of the gate foot  565 . Yet another, smaller dose  517   c  may be centered over the gate foot  565 , as illustrated in  FIG. 6A . For this exposure, it is possible to use a low voltage, such as 20 KV. 
     The resulting opening in the resist layers  695 ,  685 , and  675  uncovers the gate foot  565  and is off set to the side of the gate foot  565 . Thus, the gate head  665  is not centered above the gate foot  565  and centered between the source  520  and drain  530 . Instead, the gate head  665  is located closer to the source  520  than to the drain  530 . In this implementation, therefore, because the gate foot  565  and gate head  665  are created independently, the gate head  665  can be off set toward the source, reducing the gate-to-drain capacitance C gd . In power devices for example, since the gate-to-drain capacitance increases by the Miller effect (multiplied by the device&#39;s voltage gain), reducing the gate-to-drain capacitance can improve frequency response. In other embodiments, for example in a low noise device such as a low noise amplifier, the gate could be set off toward the drain to minimize the gate-to-source capacitance C gs . 
       FIG. 7  is a simplified cross section side view of a T-gate structure transistor  700  showing a non-uniform passivation layer  715  under the gate head  710 . Especially at smaller geometries, the passivation layer  715  coverage can be non-uniform near the T-gate structure transistors  700 . For example, in  FIG. 7  the passivation layer  715  is shown tapering and thinning as it extends under the gate head  710  and approaches the gate foot  735 . 
     As discussed above, the T-gate structure transistor  700  has a T-shaped gate  705  formed over a substrate  730 . The T-shaped gate  705  may be a T-gate, a Y-gate, a mushroom gate, a gamma-gate, or an asymmetric gate. The T-shaped gate  705  has a gate foot  735  and a relatively wider gate head  710 . While gate lengths less than 100 nanometers are commonly achievable, the short height of the gate foot  735  (the distance between a surface  740  of the substrate  730  and the bottom of the gate head  710 ) required to produce such short gate lengths, creates unwanted parasitics between the gate head  710  and a source  720 , and between the gate head  710  and a drain  725 , indicated as C gs  and C gd , respectively. The short separation between the gate head  710  and the substrate  730  also hinders coverage of a passivation layer  715  on the substrate  730  below the gate head  710 . 
     The gate foot  735  is typically formed on the semiconductor substrate  730  between the source  720  and the drain  725 , and the gate head  710  is then formed on the gate foot  735 . Once the T-gate structure transistor  700  is formed on the substrate  730 , the passivation layer  715  is typically formed on the substrate  730  around the T-shaped gate  705 . The passivation layer  715  can insulate the surface  740  of the substrate  730  from the ambient environment and inhibits oxidation of the surface  740 . The passivation layer  715  may be a silicon nitride layer formed on the substrate  730  by using a plasma enhanced chemical vapor deposition process. 
     The passivation layer  715  sometimes may be non-uniform under the gate head  710  around the gate foot  735  because the gate head  710  overhangs the gate foot  735 . In the extreme case, the passivation layer  715  will not properly coat and passivate the surface  740  next to the gate foot  735 . This can lead to reliability and performance problems over time. In addition, the passivation layer  705  coats the gate head  710 , increasing the input capacitance Csg and Cgd, which degrades the frequency response of the T-gate structure transistor  700 . 
     Improved Passivation of the T-Gate 
       FIGS. 8A-8E  are simplified illustrations in cross sectional side view illustrating fabrication of a gate head  860  of a T-gate device  800  ( FIG. 8E ) in accordance with an implementation of the present invention. The gate foot  265  is formed as described herein with reference to  FIGS. 2A-2C . After removal of the resist layer  245 , the resist layer  255 , and the gate foot material layer  260 , a passivation layer  840  is formed on the substrate  210  and the gate foot  265  as shown in  FIG. 8A . The passivation layer  840  may be a nitride layer, such as SiN, deposited on the substrate  210  and the gate foot  265  by using a plasma enhanced chemical vapor deposition process. For example, the nitride layer may have a thickness of 500 angstroms. As shown in  FIG. 8A , the passivation layer  840  is generally uniform over the substrate  210 , and, in particular, around the gate foot  265 . 
     Three layers of resist  870 ,  880 , and  890  are then deposited over the passivation layer  840 . Dissimilar resists can be used so that adjacent resist layers do not intermix. The lower resist layer  870  is deposited thick enough to cover the passivation layer  840  and may be a medium sensitivity resist, such as ZEP520A. The middle resist layer  880  acts as a spacer between upper and lower resist layers  890  and  870  and can be relatively thick as compared to resist layers  890  and  870 . The middle resist layer  880  may be a copolymer, such as MMA(17.5)/MAA. The upper resist layer  890  can be an imaging layer and may be a medium sensitivity resist, such as PMMA 495k. 
     A gate head exposure (indicated by an arrow above a gaussian curve at the top of  FIG. 8A ) is performed to expose resist layers  890 ,  880 , and  870  shown in  FIG. 8A . The gate head exposure can be a large area exposure (i.e., a broad exposure), and it is possible to use a low voltage for this exposure, such as 20 kV. The resulting exposure forms a gaussian distribution in the resist layers  870 ,  880 , and  890 . This is shown in  FIG. 8A  as a gaussian like profile. 
     Turning to  FIG. 8B , after the gate head exposure, the resist layers  890 ,  880 , and  870  are developed leaving an opening  898  in the mask formed by the resist layers  895 ,  885 , and  875 . The opening  898  unmask a portion of the passivation layer  840  on the top  265   t  of the gate foot  265 . The unmasked portion of the passivation layer  840  is then removed from the top  265   t  of the gate foot  265  to uncover the top  265   t  of the gate foot  265  as shown in  FIG. 8C . For example, the unmasked portion of the passivation layer  840  may be removed by using a dry etch process. The exposure energy and the develop time are selected so that a portion of the passivation layer  840  on the top surface  265   t  of the gate foot  265  is not covered by resist layers  875 ,  885  or  895 , but some of the passivation layer  840  and some of the lower resist layer  875  remain next to the gate foot  265 . Thus, the lower resist layer  875  is not developed all the way through to the substrate  210  to expose the source  220  or drain  230 . Instead, the passivation layer  840  and the lower resist layer  870  will remain adjacent the sides of the gate foot  265  and over the source  220  and drain  230  after developing. 
     Referring to  FIG. 8B , after the gate head exposure, a developer is selected which removes the exposed portion of the upper resist layer  895  and part of the middle resist layer  885 . For example, Methyl-isobutyl-ketone or MIBK may be used to remove the exposed portion of an upper resist layer  895  formed of PMMA and part of the exposed portion of a middle resist layer  885  formed of MMA(17.5)/MAA copolymer. Next the developed portion of the middle resist layer  885  of MMA(17.5)/MAA copolymer is removed with a PMGEA:ETOH (1:5) solution. This solution does not affect the ZEP520A of the lower resist layer  875  or the upper resist layer  895 . A dimple  878  in the lower resist layer  875  is formed using MIBK developer to uncover the portion of the passivation layer  840  on top of the gate foot  265 . As shown in  FIG. 8B , the dimple  878  may have an arcuate shape. 
     The energy of the gate head exposure, the type and strength of the developer, and the develop times are selected to ensure that only the portion of the passivation layer  840  on the top portion  265   t  of the gate foot  265  is uncovered without uncovering the substrate layer  210 , the source  220 , or the drain  230 . In another embodiment, the gate head exposure may include a broad exposure in conjunction with a narrower exposure to create a more tapered shape of the dimple  878 . 
     It should be noted that although the above implementation is discussed with reference to exposure followed by the develop stages, it is possible in other implementations to perform the exposure and develop of resist layers  890 ,  880 , and  870  in one or more alternating exposure and develop stages. In some implementations, it is possible to inspect resist layer  875  to determine if the top of the gate foot  265  is uncovered, before deposition of a gate head  860 . 
     Turning to  FIG. 8D , the resist profile formed in the resist layers  895 ,  885 , and  875  define the gate head  860 . Since a continuous profile faces the deposition source, during deposition, no voids will form between the gate foot  265  and the gate head  860 . Gate head material is deposited in the opening  898  and on the resist layer  895  by a deposition technique known in the art, such as for example by metal evaporation, sputtering, or other deposition technique. The opening  898  in the mask formed by resist layers  895 ,  885 , and  875  defines the gate head  860  during the gate head deposition process. 
     Referring now to  FIG. 8E , the gate head material layer  850  is removed with a lift-off process to expose the gate head  860  of the T-gate device  800  while leaving the passivation layer  840  around the gate foot  265 . The gate head material layer  850  may be removed by stripping the resist layers  875 ,  885 , and  895  with a solvent, such as acetone. Other resists, developers, and stripper solutions are possible, but should be compatible with the particular substrate material being utilized, i.e. InP, GaAs, GaN, Si, SiC, etc. 
     In addition to the gate foot  265 , the passivation layer  840  around the gate foot  265  may provide some additional support to the gate head  860 , which may increase the structural integrity and reliability of the T-gate device  800 . Thus, the gate head  860  is supported by a surface that is wider than the top portion  265   t  of the gate foot  265 . This is particularly advantageous at smaller geometries. For example, the gate length may be 60 nm, with the gate foot tapering to about 40-50 nm at its top. A passivation layer of 50 nm on either sidewall of the gate foot may be added to more than triple the width of the surface supporting the gate head. This can improve device reliability and manufacturing yields. 
     Further, in some embodiments, the improved uniformity and/or thickness of passivation layer  840  allow for decreased capacitance between the gate head  860  and the source  220 , and between the gate head  860  and the drain  230 . 
     As shown in  FIG. 8E , the gate head  860  may have an arcuate shape extending away from the gate foot  265 , formed by the dimple  878  shown in  FIG. 8C . The arcuate shape increases the distances between the gate head  860  and both the source  220  and the drain  230 . This allows for reduced capacitances between the gate head  860  and both the source  220  and the drain  230 . Further, the arcuate shape of the gate head  860  allows the gate foot to be located closer to the source  220  to provide lower source resistance for the T-gate device  800 . It is possible, in some embodiments, to form gate head with a more taper shape, or even concave shape as shown in  FIG. 4 , which allows for further reduction of capacitances and/or source resistance as discussed above. 
     In various embodiments, the distance between the gate foot  265  and the source  220  is about 300 nm, which results in a low source resistance of the T-gate device  800 . Similarly, in some embodiments, the distance between the gate foot  265  and the drain  230  is about 300 nm, which results in a low drain resistance of the T-gate device  800 . 
     In some embodiments, the T-gate transistor  800  will include the source  220  and the drain  230 . For example, the T-gate device  800  may be a T-gate transistor constructed of indium phosphide, gallium arsenide, gallium nitride, or antimonide. With some of the above described implementations, it is possible to produce ultra-short, low-resistance T-gate structures for HEMI, HFET, PHEMT, and MESFET devices to eliminate the problem of void formation during metal deposition. Certain implementations may be used to produce reliable T-gate structures for sub-millimeter devices. 
     As discussed above, some implementations provide the ability to increase distance between the gate head and substrate, to reduce the gate to source capacitance and the gate to drain capacitance. Furthermore, some implementations, allow in situ evaluation of gate length prior to complete fabrication, allowing verification of process parameters during processing, in situ, leading to greater uniformity and yields. Further, improved uniformity across a wafer is achievable. 
     The above implementations are not limited to the example resists and developers discussed above, or to specific exposure levels. Moreover, although described above with reference to T-gate, gamma gate, and Y-gate structures, the present invention is not limited to these types. Other types of resists and developers may be used. Further, the above implementations are not limited to soft masks and may include hard masks. 
     Having described this invention in connection with a number of implementations and embodiments, modification will now certainly suggest itself to those skilled in the art. The invention is not intended to be limited to the disclosed implementations and embodiments, except as required by the appended claims.