Abstract:
Synapse can be formed from a smaller number of elements in a low-power semiconductor device, which realize a highly integrated neural network. Precise modifications of synapse weighting become possible and a neuron computer chip of a practical level can be accomplished. 
     The semiconductor device includes a first electrode for charge injection, connected to a floating gate through a first insulating film; a second electrode for applying programming pulses, connected to the floating gate through a second insulating film, and a MOS transistor using the floating gate as its gate electrode, wherein the charge supplied from the source electrode of the MOS transistor sets the potential at the first electrode to a predetermined value determined by the potential of the floating gate, and charges are transferred between the floating gate and the first electrode through the first insulating film by applying a predetermined pulsating voltage to the second electrode.

Description:
SPECIFICATION 
     1. Technological Field 
     The present invention relates to a semiconductor device, and in particular, provides a highly functional semiconductor integrated circuit device for the realization of neural network computers (neuron computers). Furthermore, the present invention provides a highly functional semiconductor integrated circuit device for the realization of multivalent analog memory. 
     2. Background of the Invention 
     The pace of development in semiconductor integrated circuit technology has been startling, so that, for example, using dynamic memory as an example, memories from 4 megabits to 6 megabits are already in production, while ultra-high density memories having capacities of 64 megabits or more are being realized at the level of research. In 64 megabit memories, approximately 120 million MOS transistors are integrated on a silicon chip measuring at most 1 cm 2 . Such ultra LSI technology is applied not merely to memory circuits, but also to logical circuits; a variety of highly functional integrated circuits have been developed, beginning with CPUs of from 32 bits to 64 bits. 
     However, when such logical circuits are used to construct, for example, a computer employing a method in which digital signals, that is to say, signals having two values, &#34;1&#34; and &#34;0&#34;, are used to conduct calculations, it is necessary to employ the Neumann method, in which instructions are executed one by one in accordance with a previously determined program. When such a method is employed, extremely high speed calculations are possible with respect to simple arithmetical calculations; however, an enormous amount of time is required for, for example, the calculations of pattern recognition or image processing or the like. Furthermore, such a method is highly disadvantageous for the type of data processing at which human beings excel, such as, for example, association, learning, and the like, and research is currently being conducted into various software technologies; however, the current state of affairs is such that rapid results have not been obtained. Here, a separate branch of research has been conducted in order to solve all these problems; in this research, the functioning of animal brains is being studied, and attempts are being made to develop computers which are capable of conducting calculations and processing which imitates such functions, that is to say, to develop neural circuit computers (neuron computers). 
     This research began in the 1940&#39;s; however, the field has become extremely active in recent years. This is the case because, in concert with the development of LSI technologies, it has become possible to realize such neuron computers in hardware. 
     However, there remain a number of problems with the realization of such neuron computers on LSI chips using present semiconductor LSI technology, and the goal of practical application has not yet been reached. 
     A discussion of the technological problems involved in the realization of such computers in terms of LSI follows. 
     The human brain has an extremely complex structure, and the functions thereof are of an extremely high level; however, the basic composition of the brain is extremely simple. That is to say, the brain comprises nerve cells having a calculating function, termed neurons, and nerve fibers, which transmit the results of such calculations to other neurons, thus serving, so to speak, as wiring. 
     In FIG. 14, a simplified model of the composition of the fundamental units of the brain is shown. References 1401a, 1401b, and 1401c indicate neurons, while references 1402a, 1402b, and 1402c indicate nerve fibers. 1403a, 1403b, and 1403c are termed synapse junctions; these apply, for example, a weighting w a  to a signal transmitted from, for example, nerve fiber 1402a, and input this into neuron 1401a. Neuron 1401a calculates the linear sum of the signal strengths with are inputted thereinto, and when the total value thereof is in excess of a threshold value, the nerve cell becomes active, and outputs a signal to nerve fiber 1402b. If the total value is less than or equal to the threshold value, the neuron does not output a signal. The outputting of a signal by the neuron when this total value exceeds the threshold value is referred to as the `firing` of the neuron. 
     In an actual brain, such calculations, transmission of signals, application of weighting, and the like are all conducted by means of electrochemical phenomena; the signals are transmitted and processed as electrical signals. The process of learning in human beings can thus be understood as the process of the alteration of weighting in the synapse junctions. That is to say, the weightings are progressively revised so as to obtain a correct output in response to a combination of a variety of inputted signals, and the weightings finally settle at the optimum values. That is to say, human intelligence is engraved in the brain as weightings in synapses. 
     A large number of neurons are connected to one another via synapses and thus form one layer. It is known that in the human brain, there are 6 layers, one on top of the other. The realization of this type of structure and function as an LSI system employing semiconductor devices is the most important task in the realization of neuron computers. 
     FIG. 15(a) serves to explain the function of one nerve cell, that is to say, one neuron; this was proposed as a mathematical model in 1943 by McCullock and Pitts (Bull: Math. Biophys. Vol. 5, p.115(1943)). Currently, a great amount of research is being conducted into the realization of this model in semiconductor circuits and the construction thereby of a neuron computer. V 1 , V 2 , V 3 , . . . , V n  indicate a number n of input signals which are defined in terms of, for example, voltage sizes; these correspond to the signals which are transmitted from other neurons. References W 1 , W 2 , W 3 , . . . , W n  indicate coefficients which express the strength of the junctions between neurons; in biological terms, these are what are termed synapse junctions. The function of the neuron is to operate in such a manner that when a value Z comprising the linear sum of each input V i  multiplied by the appropriate weight W i  (i=1/n) is in excess of a fixed threshold value V TH  *, a value of `1` is outputted, while when this value Z is smaller than the threshold value, a value of `0` is outputted. This can be expressed in the following manner: ##EQU1## 
     FIG. 15(b) shows the relationship between Z and V out  ; when Z is sufficiently larger than V TH  *, a value of 1 is outputted, while when Z is sufficiently smaller than V TH  *, a value of 0 is outputted. 
     When an attempt is made to realize this type of neuron as a combination of transistors, it is not merely the case that a large number of transistors are required, but it is also necessary to conduct the addition operation by converting each signal into an electrical current value, so that a large number of electrical currents are caused to flow, and a very large amount of power is consumed. In such a state of affairs, large scale integration is impossible. This problem was solved by the invention of the neuron MOSFET (abbreviated to νMOS) (inventors: Tadashi Shibata, Tadahiro Ohmi, Japanese Patent Application No. Hei 1-141463). 
     This invention succeeded in realizing the main functions of the operation of a neuron while employing only one transistor, and moreover, it was possible to conduct the addition operations of the voltage signals in an unconverted state, so that almost no power was consumed, and the invention was thus epoch-making in that respect. FIG. 16 indicates in simplified form an example of the cross sectional structure of this νMOS; 1601 indicates, for example, a P type silicon substrate, references 1602 and 1603 indicate a source and a drain formed by means of N +   diffusion layers, reference 1604 indicates a gate insulating film (for example, SiO 2  or the like) which is provided on the channel region, reference 1606 indicates a floating gate which is electrically insulated and is in a potentially floating state, reference 1607 indicates an insulating film comprising, for example, SiO 2  or the like, and reference 1608 (G 1 , G 2 , G 3 , G 4 ) indicates input gates, which correspond to the inputs of the neuron. 
     FIG. 17 shows a further simplification of the above in order to explain the operation of the νMOS. If the capacitive coupling coefficient between each input gate and the floating gate is represented by C G , and the capacitive coupling coefficient between the floating gate and the silicon substrate is represented by C 0 , then the potential Z of the floating gate can be expressed as follows: 
     
         Z=-w(V.sub.1 +V.sub.2 +V.sub.3 +V.sub.4)                   (4) 
    
     
         w.tbd.C.sub.G /(C.sub.O +4C.sub.G)                         (5) 
    
     Here, V 1 , V 2 , V 3 , and V 4  represent voltages which are inputted into, respectively, input gates G 1 , G 2 , G 3 , and G 4 , and the potential of the silicon substrate is 0 V; in other words, it is grounded. 
     If the floating gate is viewed as a gate electrode, then this νMOS is a standard N channel MOS transistor, and if the threshold voltage as seen from the floating gate (the voltage at which an inversion layer is formed on the surface of the substrate) is represented by V TH  *, then when Z&gt;V TH  *, the νMOS enters an ON state, while when Z&lt;V TH  *, the transistor is in an OFF state. That is to say, if an inverter circuit such as that shown, for example, in FIG. 18 is built employing one such νMOS 1609, then it is possible to realize the functions of one neuron in a simple manner. References 1610 and 1611 indicate resistors which serve in the construction of the inverter, and reference 1612 indicates an NMOS transistor. FIG. 19 shows V out1  and V out2  as a function of Z; with respect to an input such that Z&gt;V TH  *, V out2  outputs a high level voltage of V DD . That is to say, the state of the firing of the neuron is realized. 
     As shown in Formula (4), it is possible to realize the fundamental operation of the neuron, in which the inputs into the neuron are added at the level of voltage and the neuron fires when the linear sum thereof is in excess of the threshold value, by means of only one νMOS. Voltage mode addition is conducted, so that the only current flowing in the input portion is the charge and the discharge current of the capacitor, and the size thereof is very small. In the inverter, a direct current is caused to flow when the neuron fires; however, this is because resistor 1610 is employed as a load, and if a νMOS gate having a CMOS structure in accordance with the above described invention (Japanese Patent Application No. Hei 1-141463) is employed, it is possible to eliminate this direct current. 
     FIGS. 20 and 21 show examples of the CMOS structure. FIG. 20 shows the cross sectional structure of the CMOS neuron gate in a schematic manner; reference 2001 indicates a P type silicon substrate, reference 2002 indicates an n type well, references 2003a and 2003b indicate, respectively, a N +   source and drain, references 2004a and 2004b indicate, respectively, a P +   type source and drain, reference 2005 indicates a floating gate, and references 2006a-d indicate, respectively, input gate electrodes. References 2007 and 2008 indicate insulating films comprising, for example, SiO 2 , while reference 2009 indicates a field oxide film. FIG. 21 indicates an example of the structure of one neuron circuit; reference 2010 indicates the CMOS neuron gate of FIG. 20, represented symbolically, and portions thereof which are numbered correspond to the numbering in FIG. 20. Reference 2011 indicates a CMOS inverter, while references 2012 and 2013 indicate, respectively, a NMOS transistor and PMOS transistor. Furthermore, reference 2014 indicates the output of the neuron. 
     It is possible to construct a neuron using a small number of elements in the above manner, and moreover, since the power consumption is extremely small, the νMOS is an indispensable element for the realization of a neuron computer. 
     However, in order to realize the neuron computer, another important element aside from the neuron is necessary, that is to say, the synapse. FIG. 22 shows an example of the basic structure of a neuron circuit which also contains synapse junctions constructed using conventional technology. 
     Reference 2201 indicates a neuron circuit such as that shown, for example, in FIG. 18, and reference 2202 indicates wiring which transmits output signals from other neurons. Reference 2203 indicates synapse junction circuitry; this circuitry serves to impart a weighting to the inputted signal. This comprises a source follower circuit in which a load resistance (R+R x ) is connected to the source 2206 of the NMOS transistor 2204. Accordingly, when the output signal V S  of a neuron which has fired is applied to the gate electrode 2205 of the NMOS transistor, a voltage of V S  -V TH  arises in source 2206 (here, V TH  indicates the threshold of the NMOS transistor 2204). 
     For example, if a MOS transistor in which V TH  =0 is employed, then the potential of source 2206 is equal to V s , this voltage is divided among the two resistors R and R x , and forms the output voltage of the synapse junction circuitry; this is transmitted to neuron 2201 by means of wiring 2207. The output voltage thereof is V s  ·R x  /(R+R x ); a weighting comprising R x  /(R+R x ) is thus multiplied by the signal voltage V s . It is possible to modify the weighting by means of the alteration of the value of R x . 
     FIG. 23 shows an example of a method for the realization of variable resistance. If a constant voltage V GG  is applied to the gate of one MOS transistor 2301, then this transistor will function as a single resistor. It is possible to modify the resistance value by means of changes in the value of V GG . 
     Furthermore, FIG. 23(b) shows an example of the circuitry for controlling the value of V GG  ; this comprises a 4 bit binary counter 2302 and a D/A converter 2303. The junction strength of the synapse is expressed as a 4 bit binary number; this is converted to an analog voltage by means of D/A converter 2303 and outputted as the value of V GG . In order to strengthen the synapse junction strength, a countdown is is effected in the value of the counter by means of a control signal, and the value of V GG  is thus reduced. On the other hand, when the synapse junction is to be weakened, a count-up is effected, and the value of V GG  thus increases. 
     The difficulties involved in the use of synapse junction circuitry such as that shown in FIGS. 22 and 23 will be discussed below. 
     First, the first difficulty involves the voltage division by means of resistors which generates the weighting in FIG. 22. When this method is employed, the output voltage multiplied by the weighting is maintained by means of continuously causing a current to flow to the resistors, so that power is constantly consumed in an amount of V S   2  /(R+R x ). When this is the case, even if the power consumption is reduced by means of the application of νMOS in the neuron 2201, the power consumption of the circuitry as a whole will not be sufficiently reduced. If a two layer neural network, in which one layer comprises a number n of neurons, is considered, then the number of synapse junctions reaches n 2 , and there are many more synapses then neurons. Accordingly, to the extent that synapse junction circuitry which requires that a current continually be caused to flow is employed, the construction of a neural network of a scale suited to practical application causes excessive power consumption, and it is thus in practice impossible to design such a system. It is possible to reduce the power consumption by means of setting R+R x  to a sufficiently high value; however, in such a case, the time constant required for the charging and discharging of C out  is extremely large and the operating speed of the synapse circuit is worsened significantly. 
     The second problem is that the circuitry shown in FIG. 23(b) which determines the weighting in question of the junctions requires a large number of elements, and can not be integrated on a large scale. In order to construct a neural network having a learning function, it is necessary that the strength of each synapse junction may be appropriately altered, and that the values altered in this manner may be stored. In FIG. 23(b), a 4 bit binary counter is employed for this purpose; however, even for this, a minimum of 30 MOS transistors are required. Additionally, a large number of elements are required to construct the D/A converter. Furthermore, these circuits consume a large amount of power per synapse junction, and this is also disadvantageous from the point of view of power consumption. 
     A method in which an EPROM or E 2  PROM non-volatile memory of a floating gate type is employed has been proposed as a method for the reduction of the number of elements necessary for synapse construction. In such devices, the threshold value changes based on the amount of charge within the floating gate, so that it is possible to store weighting in an analog manner by means of the amount of charge. The weighting is stored in one transistor, so that each individual synapse circuit can be made smaller in comparison with the circuitry shown in FIG. 23(b). However, in order to read this out as a weighting, and to multiply this by the output of the previous stage neuron, it is of course the case that correspondingly complex circuitry is required. For example, if a differential amplifier circuit using two E 2  PROM memory cells is constructed (D. Soo and R. Meyer, &#34;A Four-Quadrant NMOS Analogue Multiplier,&#34; IEEE J. Solid State Circuits, Vol. sc-17, No.6, December 1982) the results of the multiplication by the weighting are read out as electrical current signals. It is thus not merely the case that a large simplification of the circuitry can not be achieved but also that the power consumed in the process of multiplication by the weighting by means of a constantly flowing current is extremely large, so that such structures can not be used in the construction of a large scale neural network. 
     A further serious problem is shown in FIG. 24. 
     FIG. 24(a) shows the threshold voltage (V TH ) of a E 2  PROM cell having a tunnel junction as a function of the number of pulses used for data writing. The program voltage is 19.5 V, and the width of the pulse is 5 msec. When a positive pulse is applied to the control electrode for the program, electrons are injected into the floating gate, and the threshold value is shifted in a positive direction. In the opposite case, if a negative pulse is applied, electrons are released from the floating gate, and the threshold value is shifted in a negative direction. As is clear from the Figures, the threshold value is greatly shifted as a result of the initial pulse, and only extremely small variations are seen as a result of subsequent pulses. In this case, it is impossible to adjust the synapse weighting to a large number of levels by fine alterations in the threshold value. 
     The reason for this can explained in the following manner. 
     FIG. 24(b) shows the state of the change over time in the number (n) of electrons injected into the floating gate when a positive program voltage is applied in the form of a step function. It can be seen that a large number of electrons are injected at the initial period of voltage application, and this number subsequently exhibits almost no increase. This forms the basis of charge injection. This is so because the current flowing through the insulating film, termed Fowler-Nordheim tunneling, is dependent on a difference in potential V between the two ends of the insulating film, in accordance with the following formula: 
     (Arithmetical Formula 2) 
     
         I ∝V.sup.2 exp(-b/V)                                (6) 
    
     That is to say, when the number of electrons in the floating gate increases as a result of the initial tunneling current, the potential of the floating gate decreases as a result of this, V becomes smaller, and as a result, the tunneling current decreases exponentially. In order to regulate the tunneling current at a constant value, and to precisely modify the synapse weighting, it is necessary to precisely control the size of the pulse voltage or the pulse width in accordance with the amount of the charge within the floating gate, and this results in a need for further large amounts of circuitry. 
     In short, it must be said that the construction of a neural network using the conventionally known technology is essentially impossible from the point of view of a reduction in power consumption to a low level, large scale integration, and precision of synapse weighting. Accordingly, it is impossible to realize a neuron computer using conventional technology. 
     The present invention was created in order to solve the problems described above; it provides a semiconductor device which is capable of realizing synapse junctions having an extremely small power consumption and employing a small number of elements, and which is capable of realizing a neuron computer chip which is integrated on a large scale, allows highly precise synapse weighting, and which has a low level of power consumption. 
     DISCLOSURE OF THE INVENTION 
     The semiconductor device in accordance with the present invention is provided with: a floating gate which is electrically insulated; a first electrode for charge injection, which is connected via a first insulating film with the floating gate; at least one second electrode for programming pulse application, which is connected to the floating gate via a second insulating film; and at least one MOS type transistor which uses the floating gate as the gate electrode thereof; characterized in that a mechanism for setting the potential of the first electrode to a predetermined value determined by the potential of the floating gate, by means of a charge supplied from the source electrode of the MOS transistor; and a mechanism for the transferring of charges between the floating gate and the first electrode, via the first insulating film, by means of the application of predetermined voltage pulses to the second electrode, are provided. 
     The present semiconductor device makes possible the construction of synapse junctions using a small number of elements, and moreover, has extremely small power consumption, so that the large scale integration and reduction in power consumption to a low level of neural networks become possible. Furthermore, the highly precise modification of synapse weighting values becomes possible, and as a result of this, it is possible to realize for the first time a neuron computer chip having practical application. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram which plains a first embodiment of the present invention. 
     FIG. 2 is a circuit diagram which explains the first embodiment of the present invention. 
     FIG. 3 is a circuit diagram which explains the first embodiment of the present invention. 
     FIG. 4 is a circuit diagram which explains the first embodiment of the present invention. 
     FIG. 5 shows the results of measurements conducted with respect to the circuitry shown in FIG. 1. 
     FIGS. 6(a)-6(b) show actually measured data for the purposes of comparing the embodiment of the present invention with a conventional example. 
     FIG. 7 is a circuit diagram explaining the first embodiment of the present invention. 
     FIG. 8 is a circuit diagram explaining a second embodiment of the present invention. 
     FIG. 9 is a circuit diagram explaining a third embodiment of the present invention. 
     FIG. 10 is a circuit diagram explaining a fifth embodiment of the present invention. 
     FIG. 11 is a circuit diagram explaining a sixth embodiment of the present invention. 
     FIG. 12 is another circuit diagram explaining the sixth embodiment of the present invention. 
     FIG. 13 is a circuit diagram explaining a seventh embodiment of the present invention. 
     FIG. 14 shows a model of the fundamental unit of the brain. 
     In FIG. 15, FIG. 15(a) is a conceptual diagram explaining the function of one nerve cell, that is to say, one neuron; FIG. 15(b) is a graph showing the relationship between Z and V out . 
     FIG. 16 is a conceptual diagram showing a simplification of an example of νMOS structure. 
     FIG. 17 shows a further simplification of the structure of FIG. 16. 
     FIG. 18 is a circuit diagram of an inverter employing the neuron element of FIG. 16. 
     FIG. 19 is a graph showing the relationship between the V out , V in , and Z in the circuit of FIG. 18. 
     FIG. 20 shows the cross sectional structure of a CMOS neuron gate. 
     FIG. 21 is a circuit diagram showing the structure of one neuron circuit. 
     FIG. 22 is a circuit diagram showing an example of the fundamental structure of a neuron circuit containing synapse junctions which employ νMOS transistors in accordance with the conventional technology. 
     In FIG. 23, FIG. 23(a) is a circuit diagram showing an example of a method for the realization of variable resistance, while FIG. 23(b) is a circuit diagram showing an example of the control of the value of V GG . 
     In FIG. 24, FIG. 24(a) is a graph showing the threshold voltage of an EPROM cell having tunneling junctions as a function of the number of pulses used for data writing, while FIG. 24(b) is a graph showing the state of the change over time in the number (n) of electrons injected into the floating gate during the application of a positive program voltage in the form of a step function. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     (Embodiment 1) 
     A first embodiment of the present invention is shown in FIG. 1. In the Figure, V i  represents a control signal which can take the values of, for example, V DD , or 0. 
     Reference 101 indicates a floating gate; this forms the gate electrode of NMOS transistor 102. Reference 103 indicates a PMOS transistor, and references 104 and 105 indicate NMOS transistors. The gates of PMOS 103 and NMOS 104 are connected to the V i  signal line, while the gate of NMOS 105 is connected to the V s  signal line. V p  indicates an electrode for programming pulse application; this can also be used as an input gate for determining the potential of floating gate 101. Furthermore, V E  also represents an electrode for programming pulse application. A SiO 2  film of a thickness of, for example, 100 Å, is formed between floating gate 101 and writing electrode 107; when the difference in potential between these two is sufficiently large, for example, when this difference reaches a level of 10 V , a current flows as a result of the Fowler-Nordheim tunneling phenomenon, and the amount of charge Q F  within floating gate 101 changes. If the potential of the floating gate is represented by Φ F   S , then this is represented by the following formula: 
     
         Φ.sub.F.sup.S =(C.sub.P V.sub.P +C.sub.T V.sub.T +Q.sub.F)/(C.sub.P +C.sub.T +C.sub.0)                                        (6) 
    
     Here, C P  represents the capacity between V P  electrode 106 and floating gate 101, C T  represents the capacity between V T  electrode 107 and the floating gate, while C 0  represents the floating capacity. Furthermore, the capacity between V E  electrode 108 and electrode 107 is represented by C E . Next, the operation of this circuitry will be explained. 
     For the purposes of simplicity the threshold value of NMOS 105 is set to 0 V, and furthermore, C T , C 0  &lt;&lt;C P , and C E  are established so that C T  =C 0  =0, so that this may be ignored. At first, in the standby state, that is to say, when V P  =V E  =0, and V i  =V s  =V DD , PMOS 103 is in an OFF state, and NMOS 104 and 105 are in an ON state, and the circuitry can be written equivalently to that in FIG. 2. Next, if V i  is set equal to 0, then PMOS 103 enters an ON state, and NMOS 104 enters an OFF state, so that the circuit becomes equivalent to that in FIG. 3. At this time, a current flows from power source V DD  into V T  terminal 107 via NMOS transistors 102 and 105, so that the potential thereof rises, and this rise in potential continues until NMOS transistor 102 enters an OFF state. Accordingly, the final value thereof is Φ F   S  -V TN  *. Here, V TN  * represents the threshold value as seen from the floating gate of NMOS 102. At this time, if Φ F   S  -V TN  * is presumed to be within the range of the power source voltage, then the difference in potential between electrode 107 and floating gate 101 is not dependent on the amount of charge Q F  within the floating gate, and this is constantly at a level of V TN  * when viewing the floating gate from electrode 107. After this, V S  is set equal to 0, and when NMOS 105 enters an OFF state, then the V T  terminal enters a floating state while maintaining a potential of Φ F   S  -V TN  *. This is shown in FIG. 4. In this state, when electrons are injected into the floating gate, if the program voltage is set to V PP  (V PP  represents a voltage equivalent to, for example, 10 V -V TN  *), and V P  is set equal to V PP , and if Φ F   S  -V TN  * is within the range of the power source voltage, then the voltage which is applied to tunnel oxide film portion 109 is not dependent on the amount of charge Q F  within the floating gate, but rather, a constant voltage of V PP  +V TN  * (that is, 10 V), when viewing the floating gate from electrode 107, is applied, so that using fixed pulse conditions, fixed tunneling is produced, and a fixed amount of electrons, independent of the amount of charge Q F  within the floating gate, is injected into the floating gate. Furthermore, when electrons are removed from the floating gate, if the program voltage is set to V PP  &#39; (where V PP  &#39; is a voltage equivalent to 10 V+V TN  *), and V E  is set equal to V PP , then if Φ F   S  -V TN  * is within the range of the power source voltage, the voltage which is applied to the tunneling oxide film portion 109 is independent of the amount of charge Q F  within the floating gate, and a constant voltage of -V PP  &#39;+V TN  * (that is to say, -10 V), when viewing the floating gate from electrode 107, is applied, so that if fixed pulse conditions are employed, a fixed tunneling is produced, and a fixed amount of electrons, independent of the amount of charge Q F  within the floating gate, is removed from the floating gate. Furthermore, when removing electrons from the floating gate, the same process can be conducted even if V P  is set equal to -V PP . After injection or removal (after application of the program voltage, or after the voltage of the electrode applying the program voltage has been set to 0 V), V i  =V S  =V DD  (irrespective of the order of the switching) is set, and the device is thus placed in the standby state. 
     By means of repeating this series of operations, under identical conditions, a standardized amount of electrons is injected into or removed from the floating gate at each single pulse. FIG. 5 shows the results of a measurement with respect to the circuitry shown in FIG. 1 and these results confirm this; the floating gate voltage Φ F   S  in the standby state of operations is plotted along the horizontal axis, while the amount of change ΔΦ F   S  in the floating gate voltage when injection or removal of electrons is carried out by means of a single pulse under identical conditions in the floating gate voltage is plotted on the vertical axis. In the circuit in which the measurement results of FIG. 5 were obtained, a value of -2.5 V was used for V TN  *; however, insofar as Φ F   S  -V TN  * is within the range of the power source voltage, that is to say, so long as -2.5 V&lt;Φ F   S  &lt;2.5 V, the amount of change Δ Φ F   S  remains constant. The ΔΦ F   S  of the characteristics of a conventional E 2  PROM decreases exponentially with respect to the floating gate voltage, and this is plotted for reference proposes. The black arrows in the Figure indicate the direction of change in accordance with the carrying out of injection or removal of electrons. When Φ F   S  has other values, that is to say, when Φ F   S  -V TN  * is outside the range of the power source voltage, then the characteristics of a conventional E 2  PROM appear, and the constant value is lost; however, this presents no problem. The reason for this is that it is possible to prevent a breakdown in insulation of the oxide film which is produced by the excessive injection of charge into the floating gate or the excessive removal of charge therefrom. Furthermore, with respect to the synapses of the neural network, when hardware learning is conducted, the values of the synapse weighting, that is to say, the amount of charge within the floating gate, reaches a maximum or a minimum, these values automatically become incapable of further alteration, and this is a highly desirable result in a hardware learning algorithm. 
     In the measurement results shown in FIG. 5, a value of -2.5 V was used as V TN  *; however, at other threshold values, the region within which ΔΦ F   S  remains constant is merely shifted, so that identical results can be obtained. Additionally, FIG. 6 shows actually measured data comparing both a conventional example and the present embodiment. In FIG. 6, after conducting one continuous injection operation, the threshold value V TH  of the NMOS 102 as seen from terminal 106 was measured. The amount of change ΔV TH  in the threshold value and the amount of change ΔΦ F   S  in the floating gate voltage were identical, and using C as a constant, the relationship is one in which V TH  =Φ F   S  +C. 
     Here, at non-programming intervals, V P  =V E  =0 was established; however, V P  and V E  may represent other voltages. Additionally, with respect to C T , C 0  &lt;&lt;C P , and C E , C T  =C 0  =0, so that this could ignored; however, this was done in order to simplify the explanation, and it is of course the case that other values may be employed. Furthermore, the threshold value of NMOS 105 was set to 0 V; however, this may be set to other values. For example, if the threshold value of NMOS 105 is set to V TN , then when V TN  &gt;0, the maximum potential of electrode 107 only rises to V S  -V TN . However, for example, V S  may be set to a value of V DD  or more using a bootstrap circuit or the like. Alternatively, in place of NMOS 105, the so-called CMOS switch shown in FIG. 7 may be employed. In FIG. 7, reference 701 indicates an NMOS transistor, reference 702 indicates a PMOS transistor, and reference 703 indicates a standard inverter. 
     The highly precise control of the amount of charge within the floating gate using single pulses under identical conditions, which was conventionally impossible when using floating gate type E 2  PROM non volatile memory without an external control circuit, as a result of the dependence of the Fowler-Nordheim tunneling current on the difference of potential between the ends of the insulating film, has become possible by means of the present invention without the use of an external control circuit, and moreover, by means of simple circuitry. As a result, although in conventional neural networks the amounts of charge within E 2  PROM floating gates was monitored and precisely controlled one by one by means of a large scale computer, so that a very large amount of time was required, by means of the present invention, this is completed after only one programming pulse, and the learning time is greatly shortened. 
     (Embodiment 2) 
     FIG. 8 is a circuit diagram explaining a second embodiment of the present invention. 
     The points of difference from FIG. 1 are that the floating gate 101 in FIG. 1 is divided into a region having an NMOS transistor and region having V P  and V T , where these two regions are connected via a switching transistor 805, and that NMOS transistor 105 is omitted. 
     In the Figure, V i  represents a control signal; it has the values of, for example, V DD  or 0. References 801 and 801&#39; indicate floating gates which are divided by switching transistor 805. 801&#39; forms the gate electrode of NMOS transistor 802. Reference 803 indicates a PMOS transistor, while reference 804 indicates an NMOS transistor. The gates of PMOS transistor 803 and NMOS transistor 804 are connected to the V i  signal line, while the gate of switching transistor 805 is connected to the V S  line. Reference V P  indicates an electrode for programming pulse application; this can also be used as an input gate for determining the potential of floating gate 801. Furthermore, reference V E  also represents an electrode used for programming pulse application. A SiO 2  film having a thickness, for example, of 100 Å, is formed between floating gate 801 and writing electrode 807, and when the difference in potential in these becomes sufficiently large, for example, reaching a level of 10 V, then a current is caused to flow as a result of the Fowler-Nordheim tunneling phenomenon, and the amount of charge Q F  within the floating gate changes. Here, if the potential of the floating gate is represented by Φ F   S , then this is described by the following formula: 
     
         Φ.sub.F.sup.S =(C.sub.P V.sub.P +C.sub.T V.sub.T +Q.sub.F)/(C.sub.P +C.sub.T +C.sub.0)                                        (7) 
    
     Here, C P  represents the capacity between V P  electrode 806 and floating gate 801, C T  represents the capacity between V T  electrode 807 and the floating gate 801, and C 0  represents the floating capacity. Furthermore, the capacity between V E  electrode 808 and electrode 807 is represented by C E . 
     With respect to the operation, the NMOS 105 of Embodiment 1 is eliminated, and in its place, a switching transistor 805 is added, and the changes in potential of all electrodes V i , V P , V E , V S , and V T  are unaffected thereby. 
     The basic principle thereof is that, because if the switching transistor is placed in an OFF state, the floating gate is divided into the two portions 801 and 801&#39;, the potential of 801&#39; of NMOS 802 remains constant even if programming pulses are applied to V P  or V E  during the injection or removal of electrons. By means of this, the value Φ F   S  -V TN  * read out from electron 807 can be maintained at a constant level even while programming pulses are being applied to V P  or V E . Accordingly, effects identical to those of the first embodiment can be obtained. 
     (Embodiment 3) 
     FIG. 9 shows a third embodiment of the present invention. 
     The differences between this embodiment and that shown in FIG. 1 are that the PMOS transistor 103 in FIG. 1 is replaced by an NMOS transistor 904, the gate electrode of this NMOS transistor 904 is connected to the V S  signal line, and the NMOS transistor 105 is eliminated. 
     Reference 901 indicates a floating gate; this functions as the gate electrode of NMOS transistor 902. Reference 903 indicates an NMOS transistor. The gate of NMOS 903 is connected to the V i  signal line. V P  represents an electrode for the application of programming pulses; it may also be employed as an input gate for determining the potential of floating gate 901. Furthermore, V E  also represents an electrode which is employed for the application of programming pulses. A SiO 2  film having a thickness of, for example, 100 Å is formed between floating gate 901 and writing electrode 906, and when the difference in potential between these two is sufficiently large, for example, when this difference reaches approximately 10 V, then a current flows as a result of the Fowler-Nordheim tunnelling phenomenon, and the amount of charge Q F  within floating gate 901 changes. Here, if the potential of the floating gate is represented by Φ F   S , then this is described by the following formula: 
     
         Φ.sub.F.sup.S =(C.sub.P V.sub.P +C.sub.T V.sub.T +Q.sub.F)/(C.sub.P +C.sub.T +C.sub.0)                                        (8) 
    
     Here, C P  represents the capacity between the V P  electrode 905 and the floating gate 901, C T  represents the capacity between the V T  electrode 906 in the floating gate, while C 0  represents the floating capacity. Furthermore, the capacity between V E  electrode 907 and electrode 906 is represented by C E . 
     With respect to operations, the PMOS 103 and NMOS 105 of Embodiment 1 were eliminated, and in their place, a NMOS transistor 904 was added, and thereby, the changes in potential of all of the electrodes V i , V P , V E , V S , and V T  remain unaffected. 
     The basic principle thereof is that, if the NMOS transistor 904 is in an OFF state, the drain terminal of the NMOS transistor 902 is cut off from the power source, so that the potential of the source terminal NMOS terminal 902, that is to say, of V T  electrode 906, remains constant even if programming pulses are applied to V P  or V E  during the injection or removal of electrons. By means of this, the value Φ F   S  -V TN  * which was read out of electrode 906 remains constant even while programming pulses are being applied to V P  or V E . Accordingly, effects can be obtained which are identical to those of the first embodiment. 
     (Embodiment 4) 
     In Embodiments 1 through 3 described above, an NMOS transistor having a floating gate was replaced by a PMOS transistor, and the polarity of a transistor having a gate connected to the V i  signal line was reversed, that is to say, an NMOS transistor was replaced by an PMOS transistor, and a PMOS transistor was replaced by an NMOS transistor, and furthermore, the polarity of the two power supply lines was reversed, and the signal line V i  was made an inverted V i , and even when these things were carried out, effects could be obtained which were identical to those of Embodiment 1 by means of operations which were identical to those of Embodiment 1. 
     (Arithmetical Formula 3) 
     
         inverted V.sub.i . . . V.sub.i  (identical hereinbelow) 
    
     (Embodiment 5) 
     FIG. 10 is a circuit diagram showing a fifth embodiment of the present invention. 
     The differences between this embodiment and that shown in FIG. 1 are that the NMOS transistor 102 in FIG. 1 is replaced by a PMOS transistor 1002, the V T  electrode 107 in FIG. 1 is connected not to the source terminal of the NMOS transistor 102 in FIG. 1, but rather to the source terminal of the PMOS transistor 1002, and the NMOS transistor 105 in FIG. 1 is eliminated. 
     In FIG. 10, reference 1001 indicates a floating gate; this functions as the gate electrode of PMOS transistor 1002. Reference 1003 indicates a PMOS transistor, while reference 1004 indicates a NMOS transistor. The gates of PMOS 1003 and NMOS 1004 are connected to the V i  signal line. V P  represents an electrode for programming pulse application; this may also function as an input gate for determining the potential of floating gate 1001. Furthermore, V E  also represents an electrode for programming pulse application. A SiO 2  film having a thickness of, for example, 100 Å, is formed between floating gate 1001 and writing electrode 1006, and when the difference in potential between these is sufficiently large, for example, when this difference reaches a level of 10 V, a current is caused to flow as a result of the Fowler-Nordheim tunneling phenomenon, and the amount of charge Q F  within floating gate 1001 changes. Here, if the potential of the floating gate is represented by Φ F   S , then this is described by the following formula: 
     
         Φ.sub.F.sup.S =(C.sub.P V.sub.P +C.sub.T V.sub.T +Q.sub.F)/(C.sub.P +C.sub.T +C.sub.0)                                        (9) 
    
     Here, C P  represents the capacity between V P  electrode 1005 and floating gate 1001, C T  represents the capacity between V T  electrode 1006 and the floating gate, and C 0  represents the floating capacity. Furthermore, the capacity between V E  electrode 1007 and electrode 1006 is represented by C E . 
     With respect to the operation, the NMOS 105 of Embodiment 1 is eliminated, and the V S  signal line is also eliminated, and as a result, the changes in potential of V i , V P , and V E  remain unchanged. A point which should be noted is that the gates of PMOS 1003 and NMOS 1004 are connected not to the signal line of V i  but to the signal line of the inverted V i . By means of this, the potential V T  of electrode 1006 is such that when V i  =V DD , that is to say, when the inverted V i  =0, V T  =V DD  ; however, when V i  =0, V DD , that is to say, when the inverted V i  =V DD , then the potential V T  of electrode 1006 has a value of Φ F   S  -V TP  *, as in Embodiment 1. Here, V TP  * represents the threshold value of PMOS transistor 1002 as seen from the floating gate. In this state, a positive program voltage is applied to V P  or V E . 
     The basic operating principle is that, using the fact that when a positive voltage is applied to the floating gate of the PMOS transistor 1002, the PMOS transistor 1002 enters an ON state, after V i  has become equal to 0, that is to say, the inverted V i  has become equal to V DD , the potential of the source terminal of PMOS 1002, that is to say, the potential of V T  electrode 1006, remains constant even if positive programming pulses are applied to V P  or V E  during injection or removal of electrons. By means of this, the value Φ F   S  -V TP  * read out of electrode 1006 can be maintained at a constant value even during the application of programming pulses to V P  or V E . Accordingly, effects identical to those of the first embodiment can be obtained. 
     (Embodiment 6) 
     FIG. 11 is a circuit diagram explaining a sixth embodiment of the present invention. As shown in this diagram, the present invention may be employed in a differential manner. In FIG. 11, reference 1101 indicates a floating gate, which serves as the gate electrode of NMOS transistor 1102 and PMOS transistor 1103. V +   and V -   represent output voltages which appear in the terminals 1104 and 1104&#39;, respectively, of this circuit; these are coupled with electrode 1105 via capacitors C 1  and C 2 . Reference 1106 indicates an NMOS transistor, the gate electrode of which is connected to signal line V S . If NMOS 1106 enters an ON state when V S  =V DD , the potential of the floating gate 1101 is represented by Φ F   S , and the threshold values of NMOS transistor 1102 and PMOS transistor 1103 are represented by V TN  * and V TP  *, respectively, then when V i  =V DD , V +   becomes equal to 0 and V -   becomes equal to V DD , and for example, if C 1  =C 2 , and electrode 1105 is placed in a floating state, then the potential V E  of electrode 1105 becomes V DD  /2, and when V i  =0, V +   becomes equal to Φ F   S  -V TN  *, and V -  becomes equal to Φ F   S  -V TP  *, the potential V E  of electrode 1105 becomes equal to (2Φ F   S  -V TN  * -V TP  *) /2, and a value is read out which is the voltage of the floating gate shifted by a constant. If |V TN  *|=|V TP  *|, then V E  =Φ F   S , and the voltage of the floating gate is read out in an unchanged fashion to electrode 1105. 
     When injection or removal of electrons is conducted, an appropriate voltage is applied as V E , and effects identical to those of Embodiment 1 can be obtained by means of operations identical to those of Embodiment 1. 
     Furthermore, it is of course the case that the portion marked 1107 may be exchanged for that in Embodiments 2-4. Furthermore, identical effects can be obtained with the circuitry shown in FIG. 12. 
     (Embodiment 7) 
     FIG. 13 is a circuit diagram showing a seventh embodiment of the present invention. 
     In this embodiment, the electrode 108 in FIG. 1 of Embodiment 1 is made the gate electrode of a CMOSνMOS inverter of a neuron circuit 1302, and this is coupled with signal line V E  via switching transistor 1304. 
     The case is shown in which, in this circuit, reference 1301 is employed as a synapse of a neural network. 
     When electrons are injected or removed, the switching transistor 1304 is placed in an ON state, an appropriate voltage supplied as V E , and thus effects identical to those of Embodiment 1 can be obtained by means of operations identical to those in Embodiment 1. 
     When the potential of the floating gate 1306 is read out, the switching transistor 1304 is placed in an OFF state, electrode 1307 is placed in a floating state, and when V i  is set equal to 0 or V DD , the output of the neuron circuit 1302 is determined by means of the value read out by means of capacitive coupling with electrode 1307. 
     In electrode 1307, a switching transistor which divides 1301 and 1302 may be provided. 
     Furthermore, 1301 may be operated in a differential manner as in Embodiment 6. 
     In Embodiments 1-7 described above, a plurality of electrodes for the application of programming pulses may be provided. By means of providing a plurality of such electrodes, programming may be conducted selectively. Additionally, it is of course the case that superior effects may be obtained if a plurality of Embodiments 1-7 are appropriately combined. 
     INDUSTRIAL APPLICABILITY 
     By means of the present invention, it is possible to construct a synapse junction using a small number of elements, and moreover, the power consumption thereof is extremely small, so that the large scale integration and reduction in power consumption of neural networks becomes possible. Additionally, the highly precise modification of synapse weighting becomes possible, and by means of this, it becomes possible for the first time to realize a neuron computer chip on a practically applicable level.