Abstract:
The present invention involves a charge pump including an input node coupled to receive an input voltage from a power voltage source and an oscillator unit generates a periodic enable regulator signal and a periodic reset signal. A regulator clock unit is coupled to the oscillator unit generating a precharge (PC) signal and a reset regulator signal in response to the enable regulator signal. A pump clock unit receives a master clock signal and generating a plurality of pump clock signals. A charge pump unit is coupled to the input node and is operatively controlled by the plurality of pump clock signals, and coupled to the an output terminal coupled to produce an output signal (V PUMP ). A regulator unit is coupled to receive the V PUMP  signal, the PC signal, the reference signal and the enable regulator signal, where the regulator unit is responsive to the enable regulator signal to operate in either a precharge mode or a regulation mode.

Description:
This application is a provisional of 60/118,724 filed Feb. 5, 1999. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates, in general, to integrated circuits and, more particularly, to integrated circuits having charge pump circuits generating a power supply voltage from an external power supply voltage. 
     2. Relevant Background 
     Electronic systems usually comprise ICs manufactured with a variety of technologies. This has created a need for multiple power supply voltages to be supplied on a single printed circuit board to support the various types of devices on that board. Standard IC voltages required by typical devices range from 5.0 volts to 3.3 volts, or lower voltage. However, there are a number of devices that require power at voltages in addition to the standard available voltages. These include data communications circuits that often require negative voltages, and interface circuitry such an the RS232 interface that specifies voltages ranging from +/−25V. Moreover, some ICs have different voltage requirements internally although they receive power from an industry standard power supply level. Being able to generate a range of voltage levels, including negative voltages and voltages larger in magnitude that the supplied voltage provides a great deal of flexibility to the circuit designer. Also, higher voltage levels often enable faster switching for better performance. 
     A practical solution to this disparity is to provide DC/DC converter circuitry that changes an input DC voltage into a higher or lower DC voltage required by another device. A negative charge pump operates to generate a negative voltage by charging a pump capacitor during a first half-cycle of a clock to the level of a source voltage. During a second half-cycle the pump capacitor is disconnected from the source and coupled, with its polarity switched, to a reservoir capacitor, thereby pumping charge to the reservoir capacitor and providing an output that is approximately the negative of the input voltage. 
     A positive charge pump may also operate to generate a higher voltage than the supply voltage (i.e., a “step-up” converter) by coupling the pump capacitor to the source voltage during the first half-cycle. During the second half-cycle, the pump capacitor&#39;s positive terminal is disconnected from the source voltage and the capacitors negative terminal is coupled to the source voltage in its place. The pump capacitor&#39;s positive terminal is then coupled to the reservoir capacitor to charge it to approximately twice the source voltage. 
     Larger high output charge pumps usually run at lower frequencies and therefore are not optimized for size. The size of a large, low frequency charge pump may be a limiting factor in obtaining the smallest IC chips as possible. It is desirable to make on-chip charge pumps as small as possible especially when the charge pumps occupy a significant area of the chip. For a target output current, the smaller the size of the charge pump, the higher proportionately the operating frequency must be. Typically, for high-current-output (e.g., greater than 5-10 milliamp) charge pumps, the operating frequency of the pump is dictated by the peak operating current and the rate of change in operating current (di/dt), as well as the size of driver and support circuitry. 
     One problem with a higher frequency charge pump is that regulation of the output voltage level becomes harder since it might take multiple cycles to turn on and off the charge pump which would result in an unwanted hysteresis. A charge pump whose output capacity per pump cycle is large relative to the load it is driving could change the voltage on the load an appreciable amount. In this case, waiting multiple pump cycles after a regulation point is reached to turn on or off the charge pump is not acceptable. 
     To remedy this problem, high speed and high power regulation methods utilizing direct current (d.c.) differential amplifiers are used. In this solution, a small portion of time at the beginning of a pump cycle is used to sense whether the voltage on the load is at or below a reference level. If the voltage is below, then a pump is initiated. If the voltage is above, then no pump occurs. With the operating frequency approaching 30 Mhz (33ns period), less than about 20% of each clock cycle (i.e., 7 ns) could be devoted to regulation. Although a fast regulation scheme can be accomplished, a large portion of the total allotted charge pump current is used for regulation in this circumstance. When using a high speed d.c. differential regulation scheme, power consumption is a problem. 
     If a high frequency charge pump is implemented in an IC that uses an active and standby mode, operation can become more complex. Even if power consumption during the active mode can be tolerated, power consumption by the charge pump might still be a problem during standby mode. Typically the standby mode requires much lower power consumption yet the charge pump must be operational at least some of the time. To conserve power, which is the purpose of the stand-by mode, it is desirable to turn off high powered regulation circuitry when not in use. While still in standby mode, the high powered regulation circuitry must be turned on and stabilized before entering a pump cycle requiring more complicated control and timing circuitry. This stabilization time consumes power and quite possibly increase the current consumption specification during standby. 
     Another method to decrease the current consumption during standby, is to totally shut-off the high powered regulator and instead use a very low power regulator that is always on. This method requires critical circuitry to ensure that multiple or partial pumps do not occur since the low power regulator takes some time for decisions to be made. In another variant, a low power, low output current pump is operational during standby mode so that a slow turn on or off would only produce a small hysteresis on the output voltage. These prior solutions all require more circuitry and complicated control logic. 
     SUMMARY OF THE INVENTION 
     The present invention involves a dynamic regulation system that is both low power and high speed. The regulator in accordance with the present invention compares a reference voltage against an input-signal and has small devices that are clocked such that internal regulator quickly nodes transition to the power rail voltages. Once the internal nodes are at the power rail voltages, little power is consumed. In accordance with the present invention, loading from subsequent circuitry is kept to a minimum so that small devices can be used to implement the internal regulator circuitry. Smaller devices enable the regulator in accordance with the present invention to be faster and consume less power. Thought the present embodiment relates to positive charge pumps, all techniques discussed can be applied to negative charge pumps. 
     Briefly stated the present invention involves a charge pump including an input node coupled to receive an input voltage from a power voltage source and an oscillator unit generates a periodic enable regulator signal and a periodic reset signal. A regulator clock unit is coupled to the oscillator unit generating a precharge (PC) signal and a reset regulator signal in response to the enable regulator signal. A pump clock unit receives a master clock signal and generating a plurality of pump clock signals. A charge pump unit is coupled to the input node and is operatively controlled by the plurality of pump clock signals, and coupled to an output terminal coupled to produce an output signal (V PUMP ). A regulator unit is coupled to receive the V PUMP  signal, the PC signal, a reference signal and the enable regulator signal, where the regulator unit is responsive to the enable regulator signal to operate in either a precharge mode or a regulation mode. 
     In another aspect, the present invention involves a method of charge pump regulation in which a dynamic regulator is disabled in a precharged or “ready to fire” state. In this standby state, the dynamic regulator is shut down consuming essentially zero power. The internal nodes of the regulator are decoupled from the power supplies such that no power is consumed, but left connected to a reference voltage and an input signal. Before transition from the standby state to an enabled state, internal nodes of the dynamic regulator are already at a differential precharged level to avoid latency penalty required to slew the internal nodes to proper levels. Immediately after transition to the enable state, the dynamic regulator is clocked with no loss of time. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a portion of the present invention in block diagram form; 
     FIG. 2 a regulator unit of the system shown in FIG. 1 in greater detail in mixed block diagram/schematic form; 
     FIG. 3 shows the deglitch and MCLK latch portion of the regulator unit of FIG. 2 in greater detail in schematic form; 
     FIG. 4 illustrates exemplary waveforms describing the operation of the circuit shown in FIG.  1  and FIG. 2; and 
     FIG. 5; illustrates other exemplary waveforms describing the operation of the circuit shown in FIG.  1  and FIG.  2 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 illustrates in block diagram form a voltage up converter in accordance with the present invention. Electronic systems are usefully represented as an interacting collection of functional units as shown in FIG.  1 . Oscillator  102  is enabled by an externally generated ENABLE signal. Oscillator  102  outputs an enable regulator (ENREG) signal that is coupled to regulator clocks unit  104  and regulator unit  106 . The ENREG signal is used by regulator clocks unit  104  to derive a precharge (PC) signal and a reset regulator (RSTREG) signal that are coupled to regulator unit  106 . 
     Regulator clocks unit  104  operates such that when the ENREG signal is low (i.e., a disabled state), the PC signal from regulator clocks unit  104  is high to precharge dynamic regulator unit  106  as discussed in greater detail hereinbelow. The ENREG signal is also used in regulator unit  106  to isolate the regulator unit  106  from highly sensitive reference voltage (V REF ) and signal voltage (V PUMP ) nodes so that these sensitive nodes are not electrically disturbed during the amplification and latching process. In response to (or in synchronization with) the PC signal transition to a high state to precharge regulator unit  106  for the next cycle, the reset regulator signal (RSTREG) generated by regulator clocks unit  104  is pulsed low to reset the regulator unit  106 . 
     After ENREG transitions to a high state (i.e., an enabled state) and on all subsequent cycles so long as the charge pump is enabled, regulator clocks unit  104  is operative to cause the PC signal to rapidly pulse low (as shown in FIG. 4) to shutoff the precharge and “clock” regulator unit  106 . “Clocking” regulator unit  106  means to amplify and latch the difference between the V REF  and V PUMP  inputs of the dynamic regulator. The latched difference signal is processed (as described in greater detail with reference to FIG. 2) to generate the master clock (MCLK) signal. The MCLK signal is used by pump clocks unit  108  to generate all necessary clocks to drive charge pump unit  110 . Detailed understanding of the operation and implementation of pump clocks circuit  108  and charge pump circuit  110  is not necessary to understand the present invention. Accordingly these details are not provided so as to ease illustration and understanding of the present invention. 
     FIG. 2 shows regulator unit  106  including a dynamic regulator circuit  200  in accordance with the present invention in greater detail in a mixed schematic/block diagram form. One of the inputs to dynamic regulator  200  can be the pumped output V PUMP  itself. More typically, a voltage divided version of V PUMP  produced by divider unit  202  is used. The V REF  input to dynamic regulator  200  comprises a reference voltage generated by reference unit  204  against which V PUMP  is compared. In the example of FIG. 2, V PUMP  is divided down by divider unit  202  and operated near the positive power supply voltage of regulator unit  106 . In this manner, the V REF  may be provided by the positive supply voltage itself, avoiding the need for additional reference voltage generator circuitry. 
     It should be understood that V REF  does not have to be at the positive power supply, however, and the particular examples herein are readily adapted to other reference voltage techniques. For example, complementary circuitry is readily available such that V REF  and V PUMP  operate at or near a negative power supply to regulator unit  106 . Other circuitry is available such that the inputs operate at a selected level between the positive and negative supplies. These and similar alternatives are equivalent to the specific examples given herein. 
     Regulator unit  106  operates to generate an MCLK signal when the divided level of V PUMP  is less than V REF , signaling that V PUMP  is lower than the desired voltage. If V PUMP  is at an adequate level (i.e., higher than V REF ), no MCLK is generated. Dynamic regulator  200  comprises a pair of cross-coupled inverters forming a latch  212  coupled to a load  228  at node  214 . Nodes  216  and  218  form inverting and non-inverting outputs of latch  212 . Load  228  comprises an resistor-capacitor (RC) circuit that is readily implemented using conventional passive or active devices. 
     Regulator unit  106  includes a power supply source node that is coupled to the V cc  power source, or another available external power source. Node  214  serves as a power supply return node that completes a current flow path from the V cc  power source, through regulator unit  106 , to ground (or any available return current path to the V cc  power source). Load  228  coupled to return node  214  prevents node  214  from floating, but provides sufficient impedance that the voltage on node  214  can be controlled using precharge device  222  and clock devices  226  and  234 . Manipulation of the voltage on node  214  enables latch  212  to be operated in a sense mode with node  214  held at a voltage sufficiently near V cc  to disable latch  212 , and a latch mode in which node  214  is held to ground thereby enabling latch  212 . 
     Dynamic regulator  200  further comprises precharge device  222  and clocking devices  226  and  234 . Precharge device  222  is controlled by the PC signal from regulator clocks unit  104  (shown in FIG.  1 ). Switches  207  and  209  are responsive to the RSTREG signal to precharge output nodes  216  and  218 , respectively, to V cc . Desirably, output nodes  216  and  218  can be controllably decoupled or isolated from V PUMP  and V REF  by switches  206  and  208 , respectively. Switches  206  and  208  are controlled by the ENREG signal discussed hereinbefore. 
     The PC signal is coupled through inverter  224  to generate a sense (SEN) signal that controls clocking device  226 . The SEN signal is coupled through a first delay unit  232  to generate a SET signal that controls clocking device  234 . Delay unit  232  is conveniently implemented as two series coupled inverters to provide a two gate delay time difference between the SEN and SET signals, however, any available delay technology may be used to implement delay  232 . The SET signal is coupled through a second delay unit  236  to generate a latch (LAT) signal to deglitch unit  242 . 
     As shown in FIG. 2, inverting output  216  and non-inverting output  218  of latch  212  are coupled to deglitching unit  242 . The deglitched signal from deglitching unit  242  is coupled to a set input of output latch  244  that generates a master clock signal (MCLK). Latch  244  can be reset by application of the external RSTMCLKB signal to a reset input of latch  244 . 
     In a particular example, ENREG operates at approximately 30 Mhz with close to 50% duty cycle as shown in FIG.  4 . In operation, while the ENREG signal is low (steady state), the PC signal is high and SEN, SET and LAT (shown in FIG. 5) are low. Also a short time after ENREG is low, RSTMCLKB is pulsed low, and a short time after PC is high, RSTREGB has pulsed low and returns to high. The combination of these signals being in the above states places regulator unit  106  in precharge mode. Regulator unit  106  is in the precharge mode during standby and during the low time of the cycling ENREG. With ENREG low, the divided V PUMP  signal shown in FIG. 4 is coupled to latch  212  through device  206  and reference input V REF  is coupled to latch  212  through device  208 . Since the RSTREGB signal pulsed low prior to this, both node  216  and node  218  are precharged to substantially V cc . The high PC signal turns precharge device  222  on and clock devices  226  and  234  remain off. 
     Precharge device  222  is desirably provided by a minimum-length n-channel transistor. In this state, node  214  settles to a voltage substantially equal to a minimum length n-channel threshold drop below V cc . This voltage on node  214  turns off the inverters (shown in FIG. 2) within latch  212 . In a particular implementation, the inverters in latch  212  are implemented with non-minimum length transistors such that when node  216  and node  218  are near V cc , the inverters in latch  212  are off (i.e., not conducting current). Node  216  and node  218  are thus isolated from V cc  and node  214  and the only influence that nodes  216  and node  218  see is through devices  206  and  208  to the inputs. 
     FIG. 3 illustrates a preferred implementation of deglitch unit  242  and latch  244  that provide low standby power usage. As shown in FIG. 3, with node  216  and node  218  near V cc  (i.e., the precharge state described above) node  302  is high and node  304  is low. Both the low on node  304  and the low LAT signal turns off devices  306  and  310  so that no current path exist even though device  312  is on while RSTMCLKB low. The input to cross coupled inverters  314  is thus high and the generated MCLK signal is low. Hence, while regulator unit  106  is in the precharge mode no current path exist and dynamic regulator  200  is continuously sampling the V PUMP  (or the divided V PUMP ) and the V REF  inputs and ready for an immediate regulation when the PC signal goes low. 
     FIG. 5 shows two cycles, a first cycle without MCLK firing and second cycle with MCLK firing. When the charge pump in accordance with the present invention is enabled, ENREG goes high to turn off devices  206  and  208  shown in FIG.  2 . to hold the V PUMP (or the divided V PUMP ) and the V REF  input voltages on nodes  216  and  218 . PC immediately pulses low to turn off precharge device  222  and SEN goes high to turn on clock device  226 . In a particular example, clock device  226  is small relative to clock device  234 . Because node  214  is coupled to load  228 , node  214  starts to slew from a voltage equal to a minimum length N-channel threshold below V cc  slowly to ground. 
     In a particular embodiment, clocking of the dynamic regulator  106  comprises two stages: a first stage to slowly amplify the difference between the inputs and after a short delay, a second stage to quickly latch the regulator in a state reflecting the state of the inputs. In one embodiment this two stage clocking happens directly within regulator unit  106 . During clocking, when a differential existing on node  216  and node  218 , node  214  slews low and latch  212  will start to steer the voltage on one of node  216  or node  218  lower. Specifically, if node  216  starts out being lower than node  218 , node  218   216  slews low. Similarly, if node  218  starts out lower than node  216 , node  218  will initially slew low. Eventually, latch  212  causes the initially higher node to slew towards VCC. With node  216  and node  218  now going in opposite directions, the SET signal goes high a delay time after SEN and turns on relatively larger clock device  234  to cause output nodes  216  and  218  of latch  212  to slew rapidly to their set values. The size difference between clock device  226  and clock device  234  provides the differential slewing rate feature in accordance with the present invention. 
     Nodes  216  and  218  can be characterized as both starting high with only one node going low and the side that stays high glitches low momentarily. The circuitry shown in FIG. 3 implements deglitch unit  242  used to compensate for the momentary low-going drop on either of nodes  216  and  218 . As stated earlier, with both nodes  216  and  218  starting high, node  302  is high and  304  is low. Also, inverter  316  whose input is node  216  is provided with a very low switch point (determined by means of relative transistor sizes) while inverter  318  has a switch point that is below V cc /2. If node  216  is the side that goes low, node  304  goes high, and node  218  will experience a low glitch, but not lower than V cc /2 and so node  302  stays high. When LAT goes high a delay time after SET, the input to cross-coupled inverters  314  is pulled low. MCLK then sets to enable clock signals generated pump clocks unit  108  (shown in FIG. 1) to fire and drive charge pump  110 . 
     However, if node  216  is the side that stays high but momentarily glitches low but not lower than the switch point of inverter  316 , then node  304  stays low. Node  218  goes low and node  302  follows. When LAT goes high, both device  306  and device  308  are off and the input to inverters  314  remains high, preventing generation of the MCLK signal. It should be noted that in the event that  216  and  218  starts out equal to each other, nodes  216  and  218  could both glitch very low past the switch points of inverter  318  first and possibly inverter  316  second. The preference of the deglitch circuit is to not generate MCLK and so under the condition of both nodes  216  and  218  glitching low, inverter  318  would first cause node  302  to go low before inverter  316  possibly causing node  304  to go high. The condition of node  302  low and possibly node  304  high does not generate an MCLK pulse. At some point dynamic regulator  200  must make a decision and either node  216  or node  218  must go back high. If node  216  goes back high, node  304  goes low and no MCLK pulse results when LAT, but if node  218  goes back high, node  302  returns to a high with node  304  already high to generate a full MCLK pulse. With this deglitch scheme no material MCLK pulses are generated. 
     In the particular example, after ENREG goes high to enable regulation to start, MCLK can fire within approximately 7 ns. Hence, not only is the apparatus and method in accordance with the present invention efficient with low standby power use, it is fast. Moreover, the preferred implementation uses small devices that switch quickly, and once node  216  and  218  have transitioned to the power supply levels, substantially no power is consumed. Hence, the regulator in accordance with the present invention is efficient when active and when switching from standby to active also. 
     Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention, as hereinafter claimed.