Abstract:
A current-controlled output buffer circuit includes a control circuit, a charging circuit, and a discharging circuit. The control circuit is configured to receive a control signal, and in response produces a charging signal and a discharging signal. The charging circuit is configured to receive the charging signal and in response, supplies a charging current to an output terminal, the magnitude of said charging current producing a signal rise time. The discharging circuit is configured to receive the discharging signal and in response, sinks a discharging current from the output terminal, the magnitude of the discharging current producing a signal fall time.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority from the following U.S. Provisional Applications, the disclosure of which are incorporated by reference in their entirety for all purposes: 
     Application No. 60/061,696, filed Oct. 10, 1997, of Ismail H. Ozguc, entitled &#34;ADAPTIVE DRIVER WITH CAPACITIVE LOAD SENSING&#34;; and 
     Application No. 60/063,472, filed Oct. 10, 1997, of Ismail H. Ozguc, entitled &#34;CURRENT CONTROLLED OUTPUT BUFFER&#34;. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates in general to integrated circuits and in particular to an output driver or buffer circuit with current-controlled output rise and fall times. 
     In certain applications, an electronic system may require an integrated circuit (IC) to drive other circuitry that present variable load conditions. Output driver circuits have been designed that provide variable drive capability. One known approach, for example, is to switch in or out one or more output transistors in parallel to vary the current drive of the output buffer. This technique, however, usually requires more transistors with various sizes than the minimum size may require, which is costly. Further, connecting more transistors to the output node by itself often results in varying the output load. This approach is also sensitive to timing constraints. 
     There is a need for an output driver circuit that can provide variable drive capability while maintaining accurate control over rise and fall times of the output signal. 
     SUMMARY OF THE INVENTION 
     The present invention provides method and circuitry for controlling the output load current of an output driver circuit throughout the rise and fall time of the output signal. In one embodiment, the current-controlled output buffer circuit includes a control circuit, a charging circuit, and a discharging circuit. The control circuit is configured to receive a control signal, and in response produces a charging signal and a discharging signal. The charging circuit is configured to receive the charging signal and in response, supplies a charging current to an output terminal; the magnitude of the charging current produces a signal rise time. The discharging circuit is configured to receive the discharging signal and in response, sinks a discharging current from the output terminal. The magnitude of the discharging current produces a signal fall time. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified block diagram of the current-controlled output driver circuit according to one embodiment of the present invention. 
     FIG. 2 is an exemplary circuit implementation of the current-controlled output driver circuit of the present invention. 
     FIG. 3 illustrates one embodiment of the adjustable current source in accordance with the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 illustrates a simplified block diagram of a current-controlled output driver circuit 100 according to one embodiment of the present. The current-controlled output driver 100 includes a control circuit 110, a charging circuit 120 and a discharging circuit 150. The charging circuit 120 includes a first adjustable current source 122, a first current mirror 124, and a switch 128. The discharging circuit includes a second adjustable current source 152, a second current mirror 154, and a switch 158. 
     In operation, the control circuit 110 receives a control signal 102, and in response, produces a charging signal 106 and a discharging signal 108. The charging signal 106 is supplied to the first adjustable current source 122 which produces a first reference current I 1 . The first reference current I 1  is mirrored to a charging transistor MP1 to supply a charging current I chg  to the OUT terminal. 
     The discharging circuit 150 operates in a similar manner. The second adjustable current source 152 receives the discharging signal 108 and produces second reference current I 2 . The second reference current I 2  is mirrored to a discharging transistor MN1 to sink (remove) a discharging current I dis  from the load 160 coupled to OUT terminal. 
     An input signal 101 controls switches 128 and 158 to alternately activate the charging and discharging transistors MP1 and MN1. When the input signal 101 is high, switch 128 is turned off, allowing the charging transistor MP1 to conduct. Switch 158 is simultaneously turned on, pulling the gate terminal of the discharging transistor MNl to ground, rendering it non-conductive. Thus, I chg  supplied by transistor MP1 flows out of the circuit 100 and into the load impedance 160. The voltage developed across the load 160 during the high input signal level state will have a rise time proportional to the amount of current I chg  delivered. 
     The circuit 100 operates in the opposite fashion when the input signal 101 is low. The low input signal 101 turns switch 128 on, rendering the charging transistor MP1 non-conductive, while simultaneously turning switch 158 off, allowing the discharging transistor MN1 to conduct. Thus, I dis  flows from the load impedance 160 to ground through the discharging transistor MN1. The voltage developed across the load 160 during the low input signal level state will have a fall time proportional to the amount of current I dis  sunk by transistor MN1. Thus, the charging and discharging signals 106 and 108 are used to independently control the rise and fall times of the output signal. 
     FIG. 2 provides an exemplary circuit implementation of the present invention. The circuit includes a control circuit 210, a charging circuit and a discharging circuit. The control circuit 210 includes a current mirror 202, control transistors 204, 205, and 206, and a filtering capacitively-coupled transistor 208. The charging circuit includes a first adjustable current source 222, a current mirror 224, an output stage control transistor 228, and a charging transistor MP1. The discharging circuit includes a second adjustable current source 252, a current mirror 254, an output stage control transistor 258, and a discharging transistor MN1. In the preferred embodiment, the charging and discharging transistors MP1 and MN1 are PMOS and NMOS FET transistors, respectively, as shown. In alternative embodiments, one or both of the charging and discharging transistors MP1 and MN1 may be realized as multiple parallel-connected transistors and may be constructed in FET, BJT, or other transistor architectures. In this exemplary embodiment, the low supply rail is 0 V and the high supply rail is 2.5 V. Also preferred is a noise reduction capacitor 208 coupled to the gate terminal of the current source 202. 
     When the input signal (at SIGNAL) makes a rising transition, the NMOS transistor 206a is switched on. The NMOS transistor 206a pulls node INPB low, turning on transistors 204b and 205b on. Activated PMOS transistor 205b switches the adjustable current source 252 in the discharging circuit off. With a low signal at its gate, PMOS transistor 204b turns on, pulling node INPBB high. With INPBB at a high level, switch transistor 258 turns on, thereby turning the discharge transistor MN1 off. Transistors 205a and 228 are switched off when SIGNAL is high, allowing the charging circuit (222a, 222b, 224, and MP1) to supply the charging current I chg  to the load 160. Thus, the rise time of the output signal at OUT is defined by the magnitude of the charging current I chg  which is adjusted by the signal at the CONTROL terminal. 
     The circuits operate in the opposite manner when SIGNAL makes a falling transition, activating the discharging circuit while deactivating the charging circuit. When activated, the discharging circuit (252, 254, and MN1) sinks the discharging current I dis  from the load 160, which defines the fall time of the output signal OUT. 
     In the preferred embodiment, the magnitude of the currents I chg  and I dis  are set by a series of current mirrors. Referring again to FIG. 2, a first current mirror 202 within the control circuit 210 produces a charging signal and a discharging signal in the form of currents I csig  and I dsig . The magnitudes of currents I csig  and I dsig  are set by the signal CONTROL and the sizes of the two transistors 202a and 202b. The currents I csig  and I dsig  are sunk from the adjustable current sources 222 and 252 of the charging and discharging circuits, respectively. 
     The adjustable current source 252 responds to the discharge signal I dsig  by supplying the second reference current I 2  to a second current mirror 254 of cascode configuration. Accordingly, a current I dis  in the amount of K*I 2  is sunk from the output terminal via discharging transistor MN1, where K (e.g., 64) is the ratio between the gate sized of MN1 and the cascode configuration of the current source 254. The amount of current sunk from the output terminal determines the fall time of the output signal. Thus, the output signal fall time is controlled by I dis , which is, in turn determined by the magnitude of the discharging signal I dsig  and gate sizes of current source 202, the adjustable current source 252, and the discharging transistor MN1. 
     The charging circuit of FIG. 2 closely parallels the structure and operation of the discharging circuit, the exception being that the adjustable current source 222 includes two current mirrors 222a and 222b. The first current mirror 222a in the preferred embodiment is identical in structure and operation to the adjustable current source 252 of the discharging circuit. The second current mirror 222b is used to provide additional variability and control over the rise time of the output signal. By implementing an additional current source in the charging circuit, the charging and discharging circuits can be designed to supply and sink different amounts of current to and from the output load while receiving the same control signal (I csig  =I dsig ). In this way, independent control of the rise and fall times can be achieved. The charging and discharging circuits may be designed symmetrically so that the charging and discharging currents I chg  and I dis  are substantially equal, resulting in symmetrical rise and fall times. 
     The first current mirror 222a of the adjustable current source 222 responds to the charging signal I csig  by supplying a current I 1  &#39; to the second current mirror 222b. The second current mirror 222b receives the current I 1  &#39; and sinks the first reference current I 1  from a current mirror 224 of cascode configuration. A current I chg  in the amount of K*I 1  is supplied to the output terminal via charging transistor MP1, where K (e.g., 64) is the ratio between the gates sizes of MP1 and the cascode configuration of the current source 224. The amount of current supplied to the output terminal determines the rise time of the output signal. Thus, the output signal rise time is controlled by I chg , which is, in turn determined by the magnitude of the charging signal I csig  and the selection of gate sizes of current source 202, the adjustable current source 222, and the discharging transistor MP1. 
     FIG. 3 illustrates a second embodiment of the second current mirror 222b of the charging circuit&#39;s adjustable current source. In this embodiment, the current mirror 300 includes four cascode pairs of NMOS FETs, preferably of similar size. Nodes P8 and P9 and currents I 1  &#39; and I 1  are as indicated in FIG. 2. A source supply voltage VSS (e.g., 0 V) is connected to the FET source terminals. 
     The first cascode pair MASTER sinks I 1  &#39; from node P8 as shown in FIG. 2. The second cascode pair CENTER sinks a portion of the total first reference current I 1  as shown in FIG. 2. The cascode transistors 300 and 302 MASTER and CENTER cascode FET pairs remain on by connecting their gates to the high supply voltage. 
     The third cascode pair DOWN further contributes to the first reference current I 1  when a high signal is applied to the DNB terminal. In the preferred embodiment, activation of both the CENTER and DOWN FET pairs provides a 2:1 current multiplication factor between I 1  &#39; and I 1 . If a longer rise time and consequently, smaller I chg  is desired, I 1  can be decreased by replacing the high signal at DNB with a low signal, thereby switching the DOWN cascode FET pair off. The programming of the DNB terminal can be accomplished by a variety of methods including wire bonding to a pad connected to DNB, using metal mask options or using programmable elements (e.g., fusible links, reprogrammable memory cell, etc.) 
     The fourth cascode pair UP also contributes to the first reference current I 1  when a high signal is applied to the UP terminal. During normal operation, the UP terminal is held low to provide a 2:1 current multiplication between I 1  &#39; and I 1 . If a shorter rise time and accordingly a larger I chg , the UP cascode pair can be activated. Thus, in the manner described above, the current I 1 , and accordingly, the rise time can be adjusted up or down. The same or similar circuit could be implemented in the discharging circuit to provide control over the desired fall time of the output signal as well. 
     While the above description is complete with regards to the preferred embodiments of the invention, other variations, modifications and equivalents will be evident to those skilled in the art. For example, in the exemplary embodiments described, transistors 202a and 202b have substantially the same gate sizes so that I csig  =I dsig . Other embodiments are possible wherein the two transistors have substantially different gate sizes to sink different amounts of current in the charging and discharging circuits. Therefore, the above description is not intended to define the complete scope of the invention, which is appropriately defined by the following claims.