Abstract:
Charge trapping memory cells are protected from over-erasing in response to an erase command. For example, in response to an erase command, one bias arrangement is applied to program charge trapping memory cells, and another bias arrangement is applied to erase the charge trapping memory cells, such that the charge trapping memory cells have a higher net electron charge in the erased state than in the programmed state. In another example, an integrated circuit with an array of charge trapping memory cells has logic which responds to an erase command by applying similar bias arrangements to the charge trapping memory cells. In a further example, such an integrated circuit is manufactured.

Description:
BACKGROUND OF THE INVENTION 
   1. Field 
   This technology relates generally to semiconductor devices, and more specifically to nonvolatile memories with program and erase operations. 
   2. Description of Related Art 
   Both  FIGS. 1A and 1B  show a charge-trapping memory cell with a substrate  170 , first current-carrying terminal  150 , second current-carrying terminal  160 , bottom oxide  140 , charge-trapping structure  130 , top oxide  120 , and gate  110 .  FIGS. 1A and 1B  show a charge-trapping memory cell undergoing the establishment of a high threshold state in different parts of the charge-trapping structure. Representative top oxides include silicon dioxide and silicon oxynitride having a thickness of about 50 to 100 Angstroms, or other similar high dielectric constant materials including, for example Al2O3. Representative bottom oxides include silicon dioxide and silicon oxynitride having a thickness of about 30 to 100 Angstroms, or other similar high dielectric constant materials. Representative charge-trapping structures include silicon nitride having a thickness of about 30 to 90 Angstroms, or other similar high dielectric constant materials, including metal oxides such as Al2O3, HfO2, and others. The charge-trapping structure may be a discontinuous set of pockets or particles of charge-trapping material, or a continuous layer as shown in the drawing. 
   In  FIG. 1A , the right part of the charge-trapping structure  130  undergoes a program operation to establish a low threshold state. The voltage of the gate  110  is −5 V. The voltage of the drain  160  is 5 V. The voltage of the source  150  is 0 V. The voltage of the substrate  170  is 0V. Consequently, the right part of the charge-trapping structure  130  has trapped charge  133 . In  FIG. 1B , the left part of the charge-trapping structure  130  undergoes a program operation to establish a low threshold state. The voltage of the gate  110  is −5 V. The voltage of the drain  160  is 0 V. The voltage of the source  150  is 5 V. The voltage of the substrate  170  is 0 V. Consequently, the left part of the charge-trapping structure  130  has trapped charge  133 . 
   In  FIG. 2A , the nonvolatile memory cell undergoes an erase operation. The voltage of the gate  210  is −8 V. The voltage of the drain  260  is 10 V. The voltage of the source  250  is 10 V. The voltage of the substrate  270  is 10 V. Consequently, the electrons move from the gate  210  to the charge trapping structure  230  and from the charge trapping structure  230  towards the substrate  270 . In  FIG. 2B , the nonvolatile memory cell undergoes an erase operation with reversed voltage polarities. The voltage of the gate  210  is 10 V. The voltage of the drain  260  is −8 V. The voltage of the source  250  is −8 V. The voltage of the substrate  270  is −8 V. Consequently, the electrons move to the gate  210  from the charge trapping structure  230  and to the charge trapping structure  230  from the substrate  270 . The erase operation may also be carried out with a floating voltage at the drain  260  and/or the source  250 . 
     FIG. 3  shows an example process flow of erasing a nonvolatile memory cell. In  310 , a command to erase the nonvolatile memory cell is received. In  320 , in response to the erase command, a biasing arrangement for erasing the nonvolatile memory cell is applied to the terminals of the nonvolatile memory cell. In  330 , an erase verify test is performed to confirm that a sufficient amount of erasing has been performed. If the erase verify test fails, then the biasing arrangement for erasing the nonvolatile memory cell is applied again. If the erase verify test passes, then the erase process is successful and done  340 . 
     FIGS. 4A ,  4 B, and  4 C show graphs of the relative distribution of the number of nonvolatile memory cells at various threshold voltages corresponding to the programmed state and erased state.  FIG. 4A  shows, prior to an erase operation, some nonvolatile memory cells having threshold voltages in the range of 3.5 V to 4 V corresponding to the programmed state  410 , and some nonvolatile memory cells having threshold voltages in the range of 5 V to 6 V corresponding to the erased state  420 .  FIG. 4B  shows an erase operation being performed on both the nonvolatile memory cells having threshold voltages corresponding to the programmed state  410  and on the nonvolatile memory cells having threshold voltages corresponding to the erased state  420 . As a result, the distribution of the nonvolatile memory cells originally in the programmed state  410  shifts to the erased state  415 . Similarly, the distribution of the nonvolatile memory cells originally in the erased state  420  shifts to the erased state  425 .  FIG. 4C  shows the actual distribution of threshold voltages of the nonvolatile memory cells in the erased state after the erase operation, which is the sum of distribution  415  and distribution  425 , or distribution  430  in the range of 5 V to 7 V. Because the erase operation shifted not only the threshold voltages of the nonvolatile memory cells in the programmed state  410 , but also the threshold voltages of the nonvolatile memory cells in the erased state  420 , the result of the program-and-erase cycle is an undesirable wide distribution  430  of threshold voltages of nonvolatile memory cells in the erased state. 
   Therefore, it would be desirable to perform an erase operation on a nonvolatile memory cell while reducing the tendency of the distribution of threshold voltages of nonvolatile memory cells in the erased state to drift. 
   SUMMARY OF THE INVENTION 
   One embodiment is a charge-trapping integrated circuit comprising an array of charge-trapping memory cells and logic coupled to the array. Each charge-trapping memory cell has a charge trapping structure associated with a threshold voltage and a programmed state and an erased state. The value of the threshold voltage determines whether the memory cell is in the programmed state or the erased state. The logic is responsive to a command to erase charge trapping memory cells, by performing several actions. The logic applies a bias arrangement to program charge trapping memory cells whose threshold voltage is outside the programmed state. Then, the logic applies another bias arrangement to establish the erased state in the charge trapping memory cells. 
   In some embodiments, the charge trapping structure of each charge trapping memory cell takes advantage of the localized charge trapping nature of the charge trapping structure (unlike the uniform charge storage of a floating gate) by associating different charge trapping parts of the charge trapping part structure with a threshold voltage and a programmed state and an erased state. In one embodiment, the logic identifies nonvolatile memory cells of the plurality of charge trapping memory cells having a threshold voltage outside the programmed state, and the programming bias arrangement programs any charge trapping part having a threshold voltage outside the programmed state, and the erasing bias arrangement establishes the erased state in the charge trapping parts. In another embodiment, the programming bias arrangement programs all the charge trapping parts of all the charge trapping memory cells, and the erasing bias arrangement establishes the erased state in all the charge trapping parts of all the charge trapping memory cells 
   In some embodiments, each charge trapping part is associated with not just one erased state and one programmed state, but multiple programmed states. The multiple programmed states include a most programmed state and other, less programmed, states. In one embodiment, the programming bias arrangement programs any charge trapping part having a threshold voltage in either the erased state or any of the less programmed states. In another embodiment, the programming bias arrangement programs all charge trapping parts of all charge trapping memory cells. 
   In some embodiments, the programming bias arrangement adds holes to the charge trapping structure, and the erasing bias arrangement adds electrons to the charge trapping structure of the plurality of charge trapping memory cells. The holes can be added by band-to-band hot hole conduction. The electrons can be added by tunneling electrons. In other embodiments, the programming bias arrangement adds electrons to the charge trapping structure, and the erasing bias arrangement adds holes to the charge trapping structure. 
   Various embodiments of erasing nonvolatile memory cells successfully resist a drift in the threshold voltage of nonvolatile memory cells that are repeatedly erased in response to multiple erase commands. For example, after 100 program and erase cycles, the threshold voltage in the erased state of charge trapping memory cells changes by no more than a magnitude of about 0.7 V. 
   Other aspects of the technology include embodiments directed to a method for performing erasing as described, and a method for manufacturing a nonvolatile memory integrated circuit as described. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1A and 1B  show a charge-trapping memory cell undergoing programming of different parts of the charge-trapping structure. 
       FIGS. 2A and 2B  show a charge-trapping memory cell undergoing erasing of different parts of the charge-trapping structure. 
       FIG. 3  shows an example process flow of erasing a charge-trapping memory cell without preprogramming. 
       FIGS. 4A ,  4 B, and  4 C show graphs of the relative distribution of the number of charge-trapping memory cells at various threshold voltages corresponding to the programmed state and erased state, during an erase operation without preprogramming. 
       FIG. 5  shows an example process flow of erasing a charge-trapping memory cell with preprogramming. 
       FIGS. 6A ,  6 B, and  6 C show graphs of the relative distribution of the number of charge-trapping memory cells at various threshold voltages corresponding to the programmed state and erased state, during an erase operation with preprogramming. 
       FIG. 7  shows a graph of threshold voltage of a charge-trapping memory cell versus program and erase cycle # for repeated erase operations without preprogramming. 
       FIG. 8  shows a graph of threshold voltage of a charge-trapping memory cell versus program and erase cycle # for repeated erase operations with preprogramming. 
       FIG. 9  shows an example of a biasing arrangement for preprogramming an array of charge-trapping memory cells. 
       FIG. 10  is a schematic of threshold voltage, indicating two threshold states. 
       FIG. 11A  is a schematic of two-level state operation. 
       FIGS. 11B ,  11 C, and  11 D are schematics of multi-level threshold states for multi-level cell operation. 
       FIG. 12  is a schematic of an integrated circuit embodiment. 
   

   DETAILED DESCRIPTION 
     FIG. 5  shows an example process flow of erasing a nonvolatile memory cell according an embodiment. In  510 , a command to erase the nonvolatile memory cell is received. In  520 , in response to the erase command, biasing arrangement for programming the nonvolatile memory cell is applied to the terminals of the nonvolatile memory cell. In one embodiment, the biasing arrangement for programming is applied to an entire sector, regardless of which cells in the sector are in the programmed state and which cells are in the erased state. This has the advantage of simplicity, such as decreasing any overhead involved in communication of data about which cells are in the erased state. In another embodiment, the biasing arrangement for programming is applied only to cells which are in the erased state. This avoids the slight shift in the distribution of threshold voltages of nonvolatile memory cells which are already in the programmed state. In  530 , after applying the biasing arrangement for programming in response to the erase command, the biasing arrangement for erasing the nonvolatile memory cell is applied to the terminals of the nonvolatile memory cell. In  540 , an erase verify test is performed to confirm that a sufficient amount of erasing has been performed. If the erase verify test fails, then the biasing arrangement for erasing the nonvolatile memory cell is applied again. If the erase verify test passes, then the erase process is successful and done  540 . 
   In another embodiment, nonvolatile memory cells having a threshold voltage outside the programmed state are identified. For example, during regular operation, a memory keeping track of the particular state—programmed or erased—is accessed to identify the nonvolatile memory cells having a threshold voltage outside the programmed state. In another example, a read procedure is performed to identify nonvolatile memory cells in the erased state, and/or nonvolatile memory cells nominally in the programmed state but, due to nonideal behavior, have a threshold voltage outside the programmed state. An advantage of identifying nonvolatile memory cells having a threshold voltage outside the programmed state, is that during the erase procedure, rather than programming all the nonvolatile memory cells, some subset of the nonvolatile memory cells may be programmed in order to avoid programming already programmed cells. 
     FIGS. 6A ,  6 B, and  6 C show graphs of the relative distribution of the number of nonvolatile memory cells at various threshold voltages corresponding to the programmed state and erased state.  FIG. 6A  shows, prior to an erase operation, some nonvolatile memory cells having threshold voltages in the range of 3.5 V to 4 V corresponding to the programmed state  610 , and some nonvolatile memory cells having threshold voltages in the range of 5 V to 6 V corresponding to the erased state  620 .  FIG. 6B  shows a program operation being performed on both the nonvolatile memory cells having threshold voltages corresponding to the programmed state  610  and on the nonvolatile memory cells having threshold voltages corresponding to the erased state  620 . As a result, the distribution of the nonvolatile memory cells originally in the programmed state  610  shifts slightly to the programmed state  615 . Similarly, the distribution of the nonvolatile memory cells originally in the erased state  620  shifts to the programmed state  625 .  FIG. 6C  shows an erase operation being performed on both the nonvolatile memory cells having threshold voltages corresponding to the programmed state  615  and on the nonvolatile memory cells having threshold voltages corresponding to the programmed state  625 . The distribution of the threshold voltages of nonvolatile memory cells in the erased state after the erase operation is the distribution  630  in the range of 5 V to 6 V, which represents the sum of the threshold voltage distributions of cells in the erased state, from both distribution  615  and  625  after erasing. Because of the prior program operation which shifted the threshold voltages of cells in the erased state to the programmed state, the erase operation did not excessively shift the threshold voltage distribution of nonvolatile memory cells in the erased state. 
     FIG. 7  shows a graph of threshold voltage versus program and erase cycle # for a nonvolatile memory cell with two distinct parts in the charge trapping structure, each capable of holding data independently of the other part. Both bits are repeatedly erased, emulating the situation where both bits of the nonvolatile memory cell are in the erased state, and are not pre-programmed in response to an erase command. Because preprogramming is not performed in response to the erase command, the threshold voltage of bit 1   710  drifts upward from about 4 V to nearly 6 V after 100 cycles. The threshold voltage of bit 2   720  also drifts upward from about 4.5 V to nearly 6 V after 100 cycles. 
     FIG. 8  also shows a graph of threshold voltage versus program and erase cycle # for a nonvolatile memory cell with two distinct parts in the charge trapping structure, each capable of holding data independently of the other part. Both bits are repeatedly erased, emulating the situation where both bits of the nonvolatile memory cell are in the erased state, but first pre-programmed prior to erasing, in response to an erase command. Because preprogramming is performed in response to the erase command, the threshold voltage of bit 1   810  drifts upward much less, from about 4 V to slightly over 4 V after 100 cycles. The threshold voltage of bit 2   820  also drifts upward much less, from about 4 V to about 4.5 V after 100 cycles. 
     FIG. 9  shows an example of a biasing arrangement for preprogramming an array of nonvolatile memory cells. The nonvolatile memory cells are interconnected in a virtual ground array arrangement. The voltages of bit line BL 1 , V BL1    910 ; bit line BL 3 , V BL3    930 ; and bit line BL 5 , V BL5    950 ; are 0 V. The voltages of bit line BL 2 , V BL2    920 ; and bit line BL 4 , V BL4    940 ; are 5 V. The voltages of word line WL 1 , V WL1    901 ; and word line WL 2 , V WL2    902 ; are 0 V. The voltages of word line WL 3 , V WL3    903 ; word line WL 4 , V WL4    904 ; and word line WL 5 , V WL5    905 ; are −8 V. By selectively applying voltages to word lines, preprogramming is limited to nonvolatile memory cells in sector  960 . By selectively applying voltages to bit lines, preprogramming is limited to the parts of the charge trapping structures indicated by the dashed areas  970 . By switching the voltages applied to the bit lines, the remaining parts of the charge trapping structures of nonvolatile memory cells in the sector  960  can be preprogrammed. 
     FIG. 10  is a schematic of threshold voltage, indicating two threshold states. High threshold state  1010  is defined by a range of threshold voltages having a minimum threshold voltage of  1015 . Low threshold state  1020  is defined by a range of threshold voltages having a maximum threshold voltage of  1025 . 
   In one embodiment, the charge trapping structure has distinct parts which are each associated independently with a threshold state. In another embodiment, a low threshold state  1020  is stored in a charge-trapping memory cell by establishing the low threshold state  1020  in different parts of the charge-trapping structure. The high threshold state  1010  is stored in the charge-trapping memory cell by raising the threshold voltage of one part of the charge-trapping structure into the high threshold state  1010  and raising the threshold voltage of another part of the charge-trapping structure into the high threshold state  1010 . 
     FIGS. 11A ,  11 B,  11 C, and  11 D are threshold state schematics corresponding to 1 bit, 2 bits, 3 bits, and 4 bits, respectively.  FIG. 11A  shows a schematic for two-level threshold state operation. There are two states, the 1 state  1  f 01  and the 0 state  1102 .  FIG. 11B  shows a schematic for four-level threshold state operation. There are 4 states, the 11 state  1111 , the 10 state  1112 , the 01 state  1111 , and the 00 state  1114 .  FIG. 11C  shows a schematic for 8-level threshold state operation. There are 8 states, of which 4 states are shown, the 111 state  1121 , the 110 state  1122 , the 001 state  1123 , and the 000 state  1124 .  FIG. 11D  shows a schematic for 16-level threshold state operation. There are 16 states, of which 4 states are shown, the 1111 state  1131 , the 1110 state  1132 , the 0001 state  1133 , and the 0000 state  1134 . 
     FIG. 12  is a simplified block diagram of an integrated circuit according to an embodiment of the present invention. The integrated circuit  1250  includes a memory array  1200  implemented using localized charge-trapping memory cells on a semiconductor substrate. A row decoder  1201  is coupled to a plurality of word lines  1202  arranged along rows in the memory array  1200 . A column decoder  1203  is coupled to a plurality of bit lines  1204  arranged along columns in the memory array  1200 . Addresses are supplied on bus  1205  to column decoder  1203  and row decoder  1201 . Sense amplifiers and data-in structures in block  1206  are coupled to the column decoder  1203  via data bus  1207 . Data is supplied via the data-in line  1211  from input/output ports on the integrated circuit  1250 , or from other data sources internal or external to the integrated circuit  1250 , to the data-in structures in block  1206 . Data is supplied via the data-out line  1212  from the sense amplifiers in block  1206  to input/output ports on the integrated circuit  1250 , or to other data destinations internal or external to the integrated circuit  1250 . A biasing arrangement state machine  1209  controls the application of biasing arrangement supply voltages  1208 , such as for the erase verify and program verify voltages, and performing preprogramming in response to a command to erase sectors of the charge-trapping structure of a memory cell. 
   While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims. What is claimed is: