Abstract:
A manufacturing method for semiconductor devices having MOSFET gate insulation films. The method includes forming a silicon oxide film, forming a silicon nitride film, nitriding the silicon nitride film, and heat treatment.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a manufacturing method for semiconductor devices such as MOSFETs, and more particularly to a manufacturing method for semiconductor devices employing improved gate insulation film formation.  
         [0003]     2. Description of the Related Art  
         [0004]     The gate insulation films of MOSFETs have become thinner as semiconductor elements and devices become ever more microscopic. A silicon oxynitride film in which nitrogen has been introduced to control diffusion of boron in the silicon substrate is used in gate insulation films of surface channel type PMOS-FETs having boron-diffused gate electrodes. This silicon oxynitride film is formed primarily by nitriding a silicon oxide film with heat treatment in an atmosphere of N 2 O, NO, or NH 3 .  
         [0005]     However, nitrogen in the silicon oxynitride film is not evenly distributed in the gate insulation film and the silicon substrate. This deteriorates the device characteristics. In particular, as the gate insulation film becomes thinner, an increasing amount of nitrogen is distributed unevenly in the interface of the gate insulation film and the silicon substrate. This greatly deteriorates the device characteristics, and cancels out the benefits of reduced thickness of the gate insulation film. An example of such MOSFET gate insulation film is disclosed in Japanese Patent Kokai (Application Laid-open) No. 2002-222941.  
       SUMMARY OF THE INVENTION  
       [0006]     One object of the present invention is to provide a novel manufacturing method for semiconductor devices to solve the problem of uneven distribution of nitrogen in the interface between the gate insulation film and the silicon substrate, while permitting reduced thickness of the silicon oxynitride film. The silicon oxynitride film is a MOSFET gate insulation film. The uneven distribution of nitrogen causes major deterioration of the semiconductor device characteristics  
         [0007]     According to a first aspect of the present invention, there is provided a method that includes forming a silicon oxide film on a semiconductor substrate, forming a silicon nitride film on the silicon oxide film, nitriding the silicon nitride film, and performing a heat treatment after nitriding the silicon nitride film.  
         [0008]     According to a second aspect of the present invention, there is provided a method that includes forming a silicon oxide film on a semiconductor substrate, forming a silicon nitride film on the silicon oxide film, performing a heat treatment process following formation of the silicon nitride film, nitriding the silicon nitride film following the heat treatment process, and performing another heat treatment process following nitriding of the silicon nitride film.  
         [0009]     Preferably, the silicon nitride film is formed with the ALD (Atomic Layer Deposit) method.  
         [0010]     Preferably, the nitriding is radical nitriding employing nitrogen plasma.  
         [0011]     The silicon oxynitride film (i.e., MOSFET gate insulation film) is very thin, but entry of nitrogen into the interface between the gate insulation film and the silicon substrate is prevented. Thus, deterioration of a semiconductor device characteristics is prevented. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIG. 1  is a cross-sectional diagram of a MOS transistor according to first and second embodiments of the present invention;  
         [0013]      FIG. 2  is a diagram showing the relationship between gate leak current and EOT according to the present invention;  
         [0014]      FIG. 3  is a flowchart to form the MOS transistor according to the first embodiment of the present invention; and  
         [0015]      FIG. 4  is a flowchart to form the MOS transistor according to the second embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]     The embodiments of the present invention are described in detail with reference to  FIG. 1  through  FIG. 4 .  
       First Embodiment  
       [0017]     Referring to  FIG. 1  and  FIG. 3 , the isolated elements  2  are formed on the semiconductor substrate  1  with a known method (STI in this embodiment) (Step S 1  in  FIG. 3 ). Then, wells and channels are formed with the ion implantation method (not shown in  FIG. 1 ) (Step S 1  in  FIG. 3 ). STI stands for shallow trench isolation.  
         [0018]     Next, the silicon oxide film  3  is formed to a thickness of between 0.5 nm and 1.5 nm over the entire surface (Step S 2 ). The silicon oxide film is formed using the thermal oxidation method or plasma oxidation method or any other suitable method.  
         [0019]     Next, the silicon nitride film  4  is formed to a thickness of between 0.2 nm and 1 nm using the LPCVD (Low Pressure Chemical Vapor Deposition) method (Step S 3 ). Since formation of an extremely thin film is necessary in the LPCVD method, it is preferred that the ALD (Atomic Layer Deposition) method is used together with the LPCVD method.  
         [0020]     Next, the silicon nitride film  4  is nitrided using the plasma nitriding method (Step S 4 ). The silicon nitride film  4  is extremely thin. Thus, when nitriding is conducted with the high temperature thermal nitriding method, the nitrogen may be thermally diffused into the silicon oxide film  3 , and even into the semiconductor substrate  1 . In order to avoid this, use of the plasma nitriding method is preferred.  
         [0021]     Annealing is conducted in an inert gas atmosphere at a temperature of between 900° C. and 1100° C. for between 1 and 100 seconds (Step S 5 ).  
         [0022]     The gate electrode  5  is formed by diffusing an impurity in polysilicon, and patterning (Step S 6 ).  
         [0023]     Next, using a known method, the source and drain  6  are formed using the ion implantation method, and the interlaminar film  7  and the wires  8  formed sequentially, thus forming a MOS transistor (Step S 7 ).  
         [0024]      FIG. 2  is a diagram illustrating the effects of the embodiment of the present invention. This diagram shows the relationship between gate leak current (Ig) and film thickness (EOT). Samples A and B have silicon oxide films formed to a thickness of 0.9 nm with the plasma oxidation method. The sample A has a silicon nitride film formed to a thickness of 0.25 nm with the ALD method, and the sample B has a silicon nitride film formed to a thickness of 0.5 nm with the ALD method.  
         [0025]     The nitriding is then conducted on the samples A and B with the plasma nitriding method, followed by annealing at 1000° C. for 30 seconds in a nitrogen atmosphere. As reference, samples C and D are prepared. Each sample C, D has a silicon oxide film formed to a thickness of 0.9 nm, and a silicon nitride film formed to a thickness of 0.5 nm. The sample C is then annealed at 1000° C. for 30 seconds in a nitrogen atmosphere. The sample D is an example of simple formation of a silicon nitride film on the silicon oxide film. Ig is greater than SiO 2  in the sample D. One reason is because it is an extremely thin film.  
         [0026]     As understood from  FIG. 2 , Ig can be reduced by annealing (reduced from D to C). However, the present invention can achieve much greater improvement on the quality of the silicon nitride film (from C to B) by nitriding. The present invention can dramatically reduce Ig, far below SiO 2 . This is thought to be due to the fact that nitriding is conducted at a self-governing rate, and thus the weak part of the silicon nitride film, for example, the part reduced in thickness, is nitrided and restored first. In general, when nitrogen enters a silicon oxide film of a thickness of about 1 nm or less, film thickness is increased. However, in the present invention, since film thickness is reduced from C to B, nitrogen is not diffused into the silicon oxide film upon nitriding. In other words, since nitrogen is not dispersed in the interface between the silicon oxide film and the substrate during nitriding, the device characteristics do not deteriorate.  
         [0027]     As described above, a two-layer structure of the silicon oxide film  3  and the silicon nitride film  4  is made in the silicon oxynitride film by the method of the present embodiment. Therefore, nitrogen does not reach the interface of the gate insulation film and the silicon substrate  1 , and quality of the silicon nitride film  4  is improved. Accordingly, it is possible to reduce Ig and also possible to prevent deterioration of the device characteristics.  
       Second Embodiment  
       [0028]     The second embodiment is described with reference to  FIG. 1  and  FIG. 4 .  FIG. 4  shows the flowchart to form the MOS transistor. The second embodiment is similar to the first embodiment so that only the differences are described below.  
         [0029]     Steps S 21  to S 23  in  FIG. 4  (second embodiment) are similar to steps S 1  to S 3  in  FIG. 3  (first embodiment).  
         [0030]     After the silicon nitride film  4  is formed (Step S 23 ), annealing is performed in an inert gas atmosphere at a temperature of between 900° C. and 1100° C. for between 1 and 100 seconds (Step S 24 ). Nitriding is then performed (Step S 25 ), and again the annealing is performed in an inert gas atmosphere at a temperature of between 900° C. and 1100° C. for between 1 and 100 seconds (Step S 26 ).  
         [0031]     Next, the gate electrode  5  is formed by diffusing an impurity in polysilicon, and patterning (Step S 27 ).  
         [0032]     Next, using a known method, the source and drain  6  are formed using the ion implantation method, and the interlaminar film  7  and the wires  8  formed sequentially (Step S 28 ), thus forming a MOS transistor.  
         [0033]     In the second embodiment, since annealing is conducted prior to nitriding, the interface between the silicon nitride film  4  and the silicon oxide film  3  is stabilized, and the density of the silicon nitride film  4  is increased. Diffusion of nitrogen into the silicon oxide film  3  during nitriding is therefore further reduced, and diffusion of nitrogen in the interface between the gate insulation film and the silicon substrate  1  becomes increasingly difficult in the silicon oxynitride film. It is also possible to prevent deterioration of the device characteristics by improving the quality of the silicon nitride film  4 .  
         [0034]     In particular, when the gate insulation film is further reduced in thickness, and the silicon oxide film  3  and the silicon nitride film  4  become thinner, this method is effective in preventing defects such as pinholes and the like. The pinholes would cause diffusion of nitrogen.  
         [0035]     This application is based on a Japanese Patent application No. 2004-294982 filed on Oct. 7, 2004 and the entire disclosure thereof is incorporated herein by reference.