Abstract:
A data communications system having a radio modem includes a voltage controlled oscillator for varying the operating frequency of the system clock. Radio interference with the modem is thereby reduced.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to communications devices and more particularly to radio modems. 
     Radio receivers form an integral part of the radio modems used to transfer data between computers. Operating a radio receiver in proximity to a computing device, however, adversely affects the receiver performance. The square-wave clocks used throughout the computer frequently generate harmonic frequencies well into the radio frequency range. These harmonic frequencies are detected as narrow-band noise sources by the receiver and often have amplitudes large enough to completely overwhelm the incoming signal. Thus, these noise sources can prevent incoming data from reaching the receiving computer. 
     To compensate for this potential interference, systems including radio modems either shield the noise source from the receiver and/or employ data packet error correction and retry schemes to correct data corrupted by the interference. Shielding all of the circuitry in a computer system is complex, costly and adds weight to the device. Data correction methods are capable of correcting only a finite number of errors on either the packet or byte level. If a received packet of data contains too many errors to be corrected, the packet will not be acknowledged to the sending modem. The sending modem will then make another attempt at sending the message. The number of times the transmitting modem will &#34;re-try&#34; the transmission is defined by the network protocol and is also limited to a finite number. Thus, error detection and retry schemes alone are insufficient to ensure accurate exchange of data. 
     SUMMARY OF THE INVENTION 
     The present invention varies the frequency of the system clock such that any noise frequencies are present for only a limited period of time. According to one embodiment of the invention, a voltage controlled oscillator is used instead of the oscillating crystal of the typical computer system. The voltage controlled oscillator can thus vary the frequency of the system clock. 
     According to another embodiment of the present invention, the rate at which the voltage controlled oscillator varies the frequency of the system can also be controlled. In a data system having a packet retry protocol for retransmitting unacknowledged data packets, the oscillator may be controlled such that the system clock remains at a single frequency for less than the time needed to transmit a single data packet. Thus, the probability that two successive packet transmissions will be corrupted by noise is reduced. 
     According to another embodiment of the present invention, the frequency change rate is controlled to be less than the time needed to send one byte of information. This scheme allows the bit error correction protocols to correct the data without the need to implement the packet retry protocols. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a standard computer architecture having crystal driven system clock; 
     FIG. 2 is a block diagram of a computer architecture including a voltage controlled oscillator according to an embodiment of the present invention; 
     FIG. 3 is a schematic of a voltage controlled oscillator which may be used in connection with an embodiment of the present invention; and 
     FIG. 4 is a schematic of a triangle wave generator for use in an embodiment of the present invention; 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows a prior art computer architecture. The computer system of FIG. 1 includes a microprocessor unit 4 coupled to memories 6 and 8 through data and address buses 10 and 12, respectively. An input/output device 14, which may be a radio modem, exchanges data between the computer system and other systems or devices. Modem 14 operates under control of input/output controller 16. The entire system is driven by one or more clocks 18. Clock 18 in turn is driven by an oscillating crystal 20 and therefore operates at a single fixed frequency or derivatives of this frequency. The harmonics of these frequencies can interfere with the integrity of the data exchanges at modem 14. 
     FIG. 2 shows a computer system constructed according to an embodiment of the present invention. In the system of FIG. 2, clock 18 is driven by a voltage controlled oscillator (VCO) 24. The control input, or V in  of VCO 24 is coupled to a modulator signal 25. Modulator 25 may be used to control the VCO output frequency and rate of frequency deviation. 
     FIG. 3 is a schematic showing the construction of the system of FIG. 2 in greater detail. In FIG. 3, VCO 24 includes varactor diodes 27 used as voltage controlled capacitors. As the load capacitance at the crystal 20 (or ceramic resonator) changes, the operating frequency of the oscillator changes. The oscillator circuit of FIG. 2 is readily compatible with existing microcontrollers because many microcontrollers and microprocessor clock generator ICs have several components of the oscillator circuitry (less the crystal and load capacitors) incorporated internally. VCO 24 may be any VCO known to those skilled in the art. For example, VCO 24 may also be constructed from a standard TTL integrated circuit such as a 555 timer or from a CMOS circuit. 
     The voltage input to VCO 24 controls the frequency of the clock output. FIG. 4 shows a circuit 50 useful for controlling the voltage input to VCO 24 and hence the frequency output. Circuit 50 may also be used to control the rate of frequency deviation. The circuit of FIG. 4 is a triangle wave generator that runs at approximately 0.005 Hz (≈200 seconds/cycle). The triangle wave thus not only controls the frequency but the rate at which the frequency changes. The output of U1-D and resistors R1-R4 set the threshold voltage levels for the triangle wave output. The divider created by R1 and R2 set the approximate DC bias point of the output voltage. R3 and R4 determine the voltage swing of the output. 
     The output of U1-D is a square wave (0 to +10.7V). The charge current throughout C2 is determined by the voltage across R5. The voltage across R5 is a constant voltage (and therefore a constant current) because U1-C keeps its input at a constant, for example, 6V and the output of U1-D is one of two constant values. In the embodiment shown, the output of U1-D is either 0V of 10.7V. Therefore, R5 and C2 set the slope of the triangle wave. R6 and R7 set the symmetry of the output. For the triangle wave to be perfectly symmetrical, the voltage divider at R6 and R7 is set at one half U1-D&#39;s maximum output voltage. A simple divide by two divider may be used when symmetry is not important. U1-A and U1-B are used as unity gain buffers to isolate the three outputs to the circuitry on the terminal board. Modulator circuits known to those of skill in the art other than a triangle wave buffer on the circuit of FIG. 4 may also be used depending upon the desired VCO operating characteristics. 
     By replacing the computer&#39;s fixed frequency crystal oscillator with VCO 24, the operating frequency of the computer can be changed dynamically. System clock frequency changes are kept small relative to the computer&#39;s nominal operating frequency. For example, the modulation can be kept at less than 0.10% of the processor nominal operating frequency. In a preferred embodiment of the present invention, the modulation is kept at 0.08% of the nominal operating frequency. Furthermore, because the modulations are centered at the computer&#39;s nominal operating frequency, the effects of any time dependent software average out over time. Thus, operation of the computer is not adversely affected. These frequency changes, however, are large enough to move the harmonic of the operating frequency outside the bandwidth of the radio receiver. 
     The dynamic system clock therefore interferes with the radio receiver only during a limited period of time when the clock frequency and its associated harmonics pass through the receiver bandwidth. For example, if the radio&#39;s operating frequencies are in the 850 MHz band, a 12.5 KHz deviation at 15 MHz nominal operating frequency translates to ±708 KHz at 850 MHz. This deviation bandwidth represents approximately 28 radio channels that the noise frequencies move across. 
     The chance of the modem receiver failing to receive any one given data packet due to noise decreases as the system clock deviation bandwidth increases. Data packets not acknowledged by the receiving modem may be resent by the transmitting modem. The probability of losing a data packet due to system clock noise can thus be described by the equation below. ##EQU1## Where: #Noise Freq: Number of noise frequencies that fall within the range of the deviation bandwidth. 
     Rx BW: Receive channel Bandwidth 
     Dev BW: Amount of noise frequency deviation at the receive channel caused by the VCO. 
     # Tries: Number of times the radio modem protocol tries to send a given packet. 
     For example, given the following: 
     Radio Receiver Bandwidth=25 KHz 
     The VCO moves the harmonic of the processor clock between 800.0 MHz and 802.5 MHz 
     There are 7 noise frequencies in the range 800.0 MHz to 802.5 MHz 
     Radio data protocol tries to send a particular data packet 3 times before giving up. ##EQU2## 
     The probability of losing a data packet can be further influenced by controlling the rate at which the noise frequency deviation occurs. The triangle wave generator of FIG. 4, for example, may be used for this purpose. Clock frequency deviations are timed to keep the noise frequency within the receiver bandwidth for an amount of time equal to the time necessary to transmit a single data packet. This technique reduces the probability that the noise frequency will re-enter the receiver bandwidth during retransmission of an unacknowledged data packet. 
     In the example given above, seven noise frequencies exist. Suppose further that the transmitting modem transmits a data packet every 125 microseconds. The input voltage to VCO 24 can therefore be controlled by circuit 50 such that the processor clock remains on any one frequency for less than 125 microseconds. This procedure reduces the likelihood that a retransmitted packet will also fail to be received because of interference caused when the clock transitions through one of the seven noise frequencies. 
     Another approach for timing the frequency transitions of the system clock makes advantageous use of the radio modem&#39;s bit error correction algorithm. In this approach, the rate of noise frequency deviation is controlled to where the noise frequency remains in the receive channel bandwidth for only one byte of transmission time. If this rate corresponds to the amount of data that the error correction protocol can correct in a single packet, the packet re-try is not required. 
     Preferred embodiments of the invention have now been described. Variations and modifications will be readily apparent to those of skill in the art. For example, for purposes of describing the invention, a computer system with CPU was described herein. The present invention can be used for any circuitry with a clock signal that causes a reduction in the system&#39;s radio receiver sensitivity. Examples include display clocks, real-time clocks, discrete logic circuitry, address decode/encode logic, programmable array logic, digital signal processors, and gate array logic. For this reason, the invention should be construed in light of the appended claims.