Abstract:
A method and system for memory testers which detects the absence of contact between memory tester pins and memory module pins, and which identifies memory module pins which are shorted to a power supply terminal or to ground, pins which are shorted to other pins, and pins which are open.

Description:
RELATED APPLICATIONS 
     This Application is related to four U.S. patent applications entitled &#34;Tester Systems&#34; U.S. patent Application Ser. No. 09/033,364, &#34;Parametric Test System And Method&#34; U.S. patent application Ser. No. 09/032,968, &#34;Microsequencer for Memory Test System&#34;, U.S. patent application Ser. No. 09/033,363, and &#34;Programmable Pulse Generator&#34;, assigned to the assignee of the present invention, and filed on even date herewith. 
    
    
     FILED OF THE INVENTION 
     The invention relates generally to manufacturing verification systems for memory modules, and more particularly to test systems for verifying contact between pins of a memory tester and the I/O pins of a CMOS IC chip or module. 
     BACKGROUND OF THE INVENTION 
     Memory test systems typically test memory modules such as CMOS dynamic random access memories (DRAM) for shorted or open data lines and shorted or open address lines and shorted or open control lines. Before such tests may be conducted, however, a contact test is required to ensure that the test system is in contact with the pins of the DRAM, as well as whether the pins are shorted together or open. All known testers test with power applied to the memory I/O pins and a current of the order of 200 μamps to avoid damaging the memory module under test. 
     A recognized reference on contact tests is the text &#34;Testing Semiconductor Memories, Theory and Practice&#34;, by A. J. van de Goor, John Wiley &amp; Sons, copyrighted 1991, reprinted 1996. In the text, pages 295-297, van de Goor proposes a test circuit where all input and output pins of a memory chip are connected to the Vcc power line and the Vss ground line by way of protection diodes, which are said to ensure that the input and output pins cannot assume a voltage level on one diode voltage drop below Vss or one diode voltage drop above Vcc. A test algorithm for the contact test also is proposed which consists of the following steps: 
     1. Set all pins to 0 volts. 
     2. Force a forward biasing current through the diodes in the range of 100 μamps to 250 μamps. 
     3. Measure the voltage Vpin resulting from the forward biasing current, and 
     if |Vpin|&lt;0.1 V, a short is assumed; 
     if 0.1V≦|Vpin|≦1.5 V, contact is assumed; and 
     if |Vpin|&gt;1.5 V, an open is assumed. 
     In the above example, the tester cannot distinguish between a short to Vcc or ground, and a short to another pin. 
     U.S. Pat. No. 5,072,175 to Marek discloses a test method and system for identifying only pin contacts and opens. Pins shorts to a power supply terminal or to ground, and pin to pin shorts are not identified. Further, modification to the component under test is required to add diodes and a test terminal, whether component is a chip or a module. 
     SUMMARY OF THE INVENTION 
     An automated contact tester method and system is disclosed and claimed which detects the absence of contacts between I/O pins of the contact tester and I/O pins of a memory module under test, and identifies pins which are shorted to a power supply terminal or ground, pins which are shorted to other pins, and pins which are open. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate preferred embodiments of the invention, and together with the general description given above and the detailed description of preferred embodiments given below serve to explain the principles of the invention. 
     FIG. 1 is an electronic schematic diagram of a contact test circuit; and 
     FIGS. 2a-2g together are a logic flow diagram of the steps taken by a programmed computer in conducting a contact test. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring to FIG. 1, a contact test system is comprised of an analog measurement section 10 and a functional test section 11, which are electrically connected to a memory module 12 through embedded program controlled switches 17 1a  -17 na . 
     Sections 10 and 11 comprise a parametric measurement unit (PMU). More particularly, a 16-bit backplane bus 13 is in electrical communication with a digital-to-analog converter 14 by way of a 16-bit bus 15. The output of the converter 14 is applied to the input of a modified Howland voltage to current converter 16, the output of which is applied to the input of a single-pole-double-throw switch 17 1a , and to the input of a buffer amplifier 18. 
     The output of the buffer amplifier 18 is applied to the input of an analog-to-digital converter 19, the output of which is applied to the backplane 13 by way of a 16-bit bus 20. 
     The input of a second single-pole-single-throw switch 17 1b  is electrically connected to the output of a digital buffer 21 1 , the input of which is held to a logic zero, and the output of which is held to an analog ground. 
     The pole of switch 17 1a  is electrically connected to the pole of switch 17 1b , and to one of the diode protected I/O pins 22 1  of the memory module 12. 
     It is to be understood that there will be as many digital buffers such as buffer 21 1 , and as many pairs of switches such as switches 17 1a  and 17 1b , as there are I/O pins such as 22 1  for a memory module under test. Thus, by the three dotted lines, and use of the letters 1-n, we indicate that there are n pins 22 1  -22 n  as well n pairs of switches (17 1a , 17 1b  -17 na , 17 nb ) and n digital buffers 21 1  -21 n . 
     Continuing with the description of FIG. 1, the input of a digital buffer 21 n  is held at a logic zero, and the output of the digital buffer 21 n  is held to an analog ground and applied to the input of switch 17 nb . The pole of switch 17 nb  is electrically connected to the pole of switch 17 na  and to a diode protected pin 22 n  of the memory module 12. The input to switch 17 na  is electrically connected to the output of converter 16, to the input of amplifier 18, and to the input of the switch 17 1a . 
     In operation, the V CC  source for the memory module 12 is set to 0 volts, and the poles of grounding switches 17 1b  -17 nb  are closed to allow digital buffers 21 1  -21 n  to force all pins 22 1  -22 n  to ground. Thereafter, a voltage is applied by way of backplane 13 and converters 14 and 16, and grounding switch 17 1b  is opened and measurement switch 17 1a  is closed to cause a forward biasing current to flow through the pin 22 1 . If the voltage sensed at the output of converter 19 is within voltage tolerances, a normal contact between the pin under test and the PMU comprising sections 10 and 11 is presumed. If the voltage is above acceptable tolerance levels, however, an open at the pin 22 1  is identified. 
     If the voltage level sensed at the output of converter 19 is lower than acceptable tolerances, the pin 22 1  is presumed to have a short. However, because all other pins have been connected to ground by the closure of grounding switches 17 2b  -17 nb , it is not determined whether the short detected at pin 22 1  is to ground or to another externally grounded pin. In this event, all grounding switches 17 1b  -17 nb  would be opened, measurement switch 17 1a  would remain closed, and a second measurement would be conducted at pin 22 1 . Thereafter, if the voltage sensed at the output of converter 19 is lower than acceptable tolerances, the pin 22 1  is identified as shorted to ground. If, however, the voltage sensed is within acceptable tolerances, then it may be assumed that the previously sensed grounded condition was due to a short to another pin. A search is then conducted to find any pin shorted to pin 22 1  by sequentially connecting remaining pins 22 2  -22 n  to ground using grounding switches 17 2  -17 n , respectively, while sensing the voltage measured at pin 22 1 . During this search sequence, when the voltage sensed at pin 22 1  indicates a grounded condition, it may be identified as shorted to the pin grounded by the grounding switch currently closed. 
     The above sequence may be repeated for each pin that is determined to be shorted. That is, the measurement switch in electrical communication with the functional test section 11 and associated with the shorted pin remains closed, and the grounding switch of the switch pair is opened while the grounding switches for the remaining pins to be tested are sequentially closed for voltage measurement and then opened, pin after pin, until another shorted pin is discovered. 
     In the preferred embodiment, the pin voltage measurements are taken and the associated switches are opened and closed under computer program control by a system processor (not shown). FIGS. 2a-2f comprise a logic flow diagram of the logic control process executed by the system processor. 
     In the description of the logic flow diagrams of FIGS. 2a-2g, the following tables are referenced: 
     
                       TABLE I______________________________________    VOL-INDEX    TAGE    EXCLUDED  SHORTED.sub.P-P                               SHORTED.sub.GND______________________________________0                FALSE     FALSE    FALSE1                FALSE     FALSE    FALSE2                FALSE     FALSE    FALSE.        .       .             .        ..        .       .             .        ..        .       .             .        .MAX.sub.-- PIN-1 FALSE     FALSE    FALSE______________________________________ 
    
     
                       TABLE II______________________________________INDEX           FROM-PIN  TO-PIN______________________________________2.               .         ..               .         ..               .         .MAX.sub.-- PIN-1______________________________________ 
    
     The variables referred to in Tables I and II above are defined in the following Table III: 
     
                       TABLE III______________________________________NAME      DESCRIPTION______________________________________LOG.sub.-- INX     Index into list of shorted pins.                            When scanning is complete, contains     number of                             shorted pin-to-pin pairs.TEST.sub.-- INX          Primary loop counter, index into per-pin array, and                             pin selector.MILLIVOLTS                  Holds value read from A/D converter in     millivolts.SEARCH.sub.-- INX        Secondary loop counter, index into per-pin array,                            and pin selector.______________________________________ 
    
     The constant referred to in the description of the above Tables I and II is described in the following Table IV: 
     
                       TABLE IV______________________________________NAME      DESCRIPTION______________________________________MAX.sub.-- PIN     Equal to the maximum number of pins testable.______________________________________ 
    
     Referring to FIG. 2a, the logic control process begins at logic step 200, and thereafter moves to logic step 202 to initialize Tables I and II associated with the pin arrays of the memory module 12 by clearing all entries except the EXCLUDED entries, which are preset according to the memory module to be tested. Also, the logging index variable Log --  INX is reset to &#34;0&#34;. The logic control process then proceeds to logic step 204 where the inputs of the digital buffers 21a-21n are set to logic zero. This is in preparation for using the outputs as a ground, and being able to switch a ground onto any one of the test pins. 
     Following logic step 204, the logic control process continues to logic step 206 where the test supply voltage V CC  of the memory module 12 is set to 0.0 volts. The testing of pins now may occur with no voltage applied. The logic control process next proceeds from logic step 206 to logic step 208 where the digital-to-analog converter 14 and the voltage-to-current converter 16 are set to deliver a 200 μamp output to the pin of memory module 12 which is under test. Thereafter, at logic step 210 the loop counter variable TEST --  INX is set to &#34;0&#34; to signify the start of the first loop. From logic step 210 the logic control process continues to logic step 211 where a test is made to see if the pin under test is used by the memory module 12. That is, the memory test system typically has many more pins than the memory module. Thus, fewer than all pins of the memory test system will make contact with corresponding pins of the memory module. If the pin is to be excluded from testing, then the logic control process continues through node K to logic step 222 of FIG. 2b. If, however, the pin under test is to be included in testing, then the logic control process continues to step 212 where the functional test switch 17 1b  is opened for the pin identified by the variable TEST --  INX. 
     Following logic step 212, the logic control process moves to logic step 214 where the analog measurement switch associated with the pin under test is closed. From logic step 214, the logic flow process continues to logic step 216 where the voltage output of converter 19 is read into the VOLTAGE column of Table I as indexed by the variable TEST --  INX. The voltage measurement is thereby associated with the pin under test. The logic control process then continues through node A to logic step 218 of FIG. 2b, where the analog measurement switch associated with the pin under test is opened. 
     The logic flow process next proceeds from logic step 218 to logic step 220 where the functional test switch associated with the pin under test is closed to effectively ground it. Following logic step 220, the logic control process continues to logic step 222 to increment the loop index variable TEST --  INX. The logic control process then proceeds to logic step 224, where a test is made to see if the variable TEST --  INX has reached the maximum pin count at the end of the test loop as identified by the constant MAX --  PIN. If not, the logic control process loops back by way of node B to the beginning of the loop at logic step 211 of FIG. 2a. In the event that the variable has reached the maximum pin count, the logic control process flows to logic step 226 where all functional test switches for all pins are opened. From logic step 226, the logic flow process continues to logic step 228 where all analog measurement switches for all pins are opened to completely float the unit under test with respect to ground. 
     Following logic step 228, the logic flow process proceeds to logic step 230 where the loop counter index variable TEST --  INX is again set to &#34;0&#34; in preparation for reuse. The logic control then proceeds through node C to logic step 232 of FIG. 2c where a test is made to see if the pin under test is used by the memory module 12. At logic step 232 the logic control process accesses the EXCLUDED column of Table I to determine whether the pin indexed by the variable TEST --  INX is to be excluded from testing because there is no corresponding memory module pin, or whether the pin under test has a corresponding memory module pin that should be in contact. If a true exists in the EXCLUDED column of Table I in the row of the pin to which the logic control process has been indexed, the pin under test is not to be tested. The logic control process thus branches by way of node E to the end of the test loop at logic step 278 of FIG. 2f, and all testing for the pin under test is stopped. In the event that the pin is to be tested, a false entry will appear in the EXCLUDED column and the row of the pin to which the variable TEST --  INX has pointed the logic control process. In that event, the logic control process continues to logic step 233 to determine whether a non-shorted condition exists for the pin under test. At logic step 233, the output of converter 20 in the VOLTAGE column of Table I, and at the row corresponding to the pin under test as indicated by the variable TEST --  INX, is accessed to determine whether the converter 20 voltage measurement is more negative than -125 millivolts. If true, then the pin under test is assumed to be non-shorted, and the logic control process branches through node E to logic step 278 of FIG. 2f, where the variable TEST --  INX is indexed to point to a new pin of the memory module 12. If false, the pin under test is presumed shorted to ground, and because the supply pin V CC  is at 0.0 volts, to be shorted to V CC  or to another pin, and the logic control process continues to logic step 234 to determine whether a pin-to-pin short exists for the pin under test by accessing Table I and reviewing the SHORTED P-P  column in the INDEX row pointed to by the variable TEST --  INX. 
     If a true entry is found, the logic control process branches by way of node E to the end of the test loop at logic step 278 of FIG. 2f, and further testing on the pin under test is stopped. If the Table I entry is false, the logic control process continues to logic step 236 where the Table I column SHORTED GND  at the row pointed to by the variable TEST --  INX is accessed to determine whether a true entry indicating a short to ground exists. If so, the logic control process branches through node E to logic step 278 of FIG. 2f, where the variable TEST --  INX is indexed to point to a new pin of the memory module 12. If the Table I entry is false, however, the logic control process proceeds from logic step 236 to logic step 240 where the analog measurement switch for the pin identified in the INDEX column of Table I by the variable TEST --  INX is closed. 
     From logic step 240, the logic control process continues to logic step 242 where the output of the converter 19 is measured and stored in a storage variable MILLIVOLTS. From logic step 242, the logic control process branches by way of node D to logic step 244, where the storage variable MILLIVOLTS is tested to determine whether it has a value less than -125 millivolts. If no, the pin under test is presumed to be shorted to ground because all other pins are floating at the time of the previous measurement. The logic control process thus branches by way of node H to logic step 274 of FIG. 2f. At logic step 274, a TRUE entry is stored in Table I under the column SHORTED GND  at the location which is pointed to by the INDEX variable TEST --  INX. From logic step 274, the logic control process moves to logic step 276. 
     If the value stored in the variable MILLIVOLTS is found at logic step 244 to be less than -125 millivolts, the pin under test is not presumed to be shorted to ground, but to some other pin, and the logic control process proceeds to logic step 246 where a new search index SEARCH --  INX is initialized to a value equal to the TEST --  INX variable incremented by one. This allows an inner test loop to begin scanning pins from the point where the above described outer test loop branched to the end of the array of the memory modules pins. From logic step 246, the logic control process continues to logic step 248 where the column EXCLUDED of Table I is accessed under control of the SEARCH --  INX index variable to determine whether the pin under test is to be excluded from further testing. If a TRUE entry is found, the logic control process branches by way of node I to logic step 270 of FIG. 2f. 
     In the event that the pin under test is to be included in testing, the logic control process moves from logic step 248 to logic step 250 where the column SHORTED P-P  of Table I is accessed at the entry specified by the index variable SEARCH --  INX. If a TRUE entry is found, the pin under test is presumed to be previously discovered to be shorted to another pin, and the logic control process branches by way of node I to logic step 270. In the event that a FALSE entry is found, the pin is not presumed to be shorted to another pin, and the logic control process continues from logic step 250 to logic step 252 to test for a short to ground. More particularly, the column SHORTED GND  of Table I is accessed at the entry pointed to by the index variable SEARCH --  INX. If a TRUE entry is found which indicates that the pin under test is shorted to ground, the logic control process branches by way of node I to logic step 270. If a FALSE entry is found, however, the pin is not presumed to be shorted to ground, and the logic control process continues from logic step 252 to logic step 254. At logic step 254, the voltage value in the VOLTAGE column of Table I and at the location pointed to by the index variable SEARCH --  INX is tested to determine whether it is less than -125 millivolts. If yes, the pin is not shorted, and the logic control process branches by way of node I to logic step 270 of FIG. 2f. If greater than or equal to -125 millivolts, the logic control process continues from logic step 254 and through node G to logic step 256 of FIG. 2e. At logic step 256, the functional test switch for the pin under test, as identified by the index variable SEARCH --  INX for Table I, is closed. 
     From step 256, the logic control process flows to logic step 258 where the voltage value read measured at the output of converter 19 is written into the temporary storage variable MILLIVOLTS. Thereafter, the logic flow process transfers from logic step 258 to logic step 260 the voltage value stored in the variable MILLIVOLTS is compared with -125 millivolts. If the voltage value stored in variable MILLIVOLTS is less than or equal to -125 millivolts, the logic control process proceeds to logic step 268. However, if the voltage value is greater than -125 millivolts, the logic control process continues from logic step 260 to logic step 262, where the entry in the FROM-PIN column of Table II as indexed by the variable LOG --  INX is set equal to TEST --  INX. In other words the pin identified by the outer test loop at the time the inner test loop under the index variable SEARCH --  INX began is identified in the inner loop. Also, the pin identified by the SEARCH --  INX index variable is set in the index variable LOG --  INX to identify a particular location under the column TO-PIN of Table II. Lastly, the LOG --  INX index variable is indexed by one to point to the next succeeding pin. 
     Following logic step 262, the logic control process continues to logic step 264 where the location in the SHORTED P-P  column of Table I that is identified by the TEST --  INX index variable is loaded with a TRUE entry to indicate a pin-to-pin short. Thereafter, the logic control process moves from logic step 264 to logic step 266 where the location in the SHORTED P-P  column of Table I that is identified by the SEARCH --  INX index variable is set TRUE. This has the effect of marking the FROM-PIN and TO-PIN locations of Table II where the outer test loop ceased to test a pin under test, and where the inner test loop identified a new pin to test. The logic control process next proceeds to logic step 268 where the functional test switch for the pin identified by the index variable SEARCH --  INX is opened. The logic control process continues from logic step 268 and through node I to logic step 270 of FIG. 2f. 
     At logic step 270, the index variable SEARCH --  INX is incremented by one. Following logic step 270, the logic control process continues to logic step 272 to determine whether the index variable SEARCH --  INX has been incremented to a value equal to the maximum number of memory module pins that can be tested (MAX --  PIN). If not, the logic control process loops back through node J to logic step 248 of FIG. 2d at the beginning of the inner test loop. If the index variable SEARCH --  INX is determined at logic step 272 to have a value equal to MAX --  PIN, however, the logic flow process flows to logic step 276 where the analog measurement switch for the pin identified by the index variable TEST --  INX is opened. From logic step 276, the logic control process moves to the end of the outer test loop at logic step 278, where the index variable TEST --  INX is incremented by one. 
     From logic step 278, the logic control process proceeds to logic step 280 where the value stored in the variable TEST --  INX is compared with the maximum number of testable pins stored in MAX --  PIN. If the MAX --  PIN value has not been reached, the logic control process branches back by way of node C to logic step 232 of FIG. 2c at the beginning of the outer test loop. In the event that the variable TEST --  INX has reached the maximum constant stored in MAX --  PIN, the logic control process proceeds by way of node L to logic step 302 of FIG. 2g. 
     ALTERNATIVE EMBODIMENT 
     In the description of the logic flow diagram of FIG. 3, the following table is referenced: 
     
                       TABLE V______________________________________INDEX          OPEN______________________________________0              FALSE1                          FALSE2                          FALSE.                             ..                              ..                               .MAX.sub.-- PIN-1          FALSE______________________________________ 
    
     At logic step 302, the logic control process initializes loop counter variable TEST --  INX to &#34;0&#34; to signify the start of the first loop. From logic step 302, the logic control process continues at logic step 304 where a test is made to see if the pin under test was used by the memory module 12. If the pin was excluded from testing, then the logic control process continues to logic step 310 where the pin under test may also be flagged as &#34;open&#34;, that is, not electrically connected to the tester. If, however, the pin was included in testing, then the logic control process continues to logic step 306 to determine whether an open pin condition exists for the pin under test. At logic step 306, the output of converter 20 in the VOLTAGE column of Table I, and at the row corresponding to the pin under test as indicated by the variable TEST --  INX, is accessed to determine whether the converter 20 voltage measurement is more negative than -1500 millivolts. If false, then the pin under test is assumed to be either correctly connected or shorted, and the logic control process branches to logic step 308 where the location in the OPEN column of Table V that is identified by the TEST --  INX index variable is loaded with a FALSE entry to indicate a non-open pin. If true, the logic control process continues to logic step 310 where the location in the OPEN column of Table V that is identified by the TEST --  INX index variable is loaded with a TRUE entry to indicate an open pin. From either of logic steps 308 or 310, the logic control process continues at logic step 312 to increment the loop counter variable TEST --  INX. From logic step 312, the logic control process continues to logic step 314 where the value stored in the variable TEST --  INX is compared with the maximum number of testable pins stored in MAX --  PIN. If the MAX --  PIN value has not been reached, the logic control process branches back to logic step 304 at the beginning of the loop. In the event that the variable TEST --  INX has reached the maximum constant stored in MAX --  PIN, the logic control process exits the outer test loop at logic step 316 with &#34;TRUE&#34; entries in the OPEN column of Table V reflecting open pins of the memory module 12. 
     The invention has been described and shown with reference to particular embodiments, but variations within the spirit and scope of the general inventive concept will be apparent to those skilled in the art. Accordingly, it should be clearly understood that the form of the invention as described and depicted in the specification and drawings is illustrative only, and is not intended to limit the scope of the invention. All changes which come within the meaning and range of the equivalence of the claims are therefore intended to be embraced therein.