Abstract:
A multiple branching configuration for output driver which achieves a fast settling time is provided. The multiple branching configuration comprises breaking down a typical output buffer stage into multiple branches; and utilizing multiple unit area sized transistors connected in parallel.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates to achieving a quick settling time of an output Driver Output Signal under high frequency and high slew rate operation. An example of such an application is a CCD signal driver. More particularly, this invention relates to a method to allow the signal to be held stable while sampled by Analog Front End (AFE), mainly Analog-to-Digital-Converters (ADC). 
         [0002]    In an exemplary application, a high Slew Rate CCD Buffer/Driver showing overshoot undershoot required to settle down to a variation of amplitude of less than 120 uVpp (for a 12 bit ADC sampling a Signal of 1 Vpp) during a sampling window of 0.8 ns. Generally, the settling time of a system depends on the damping ratio of the system and the magnitude of the excitation to the system. For Transistors, the settling time also depends on its Size, due to its parasitic components and the charging and discharging current of the parasitic components. In the case of an open-loop system, whereby there is no feed-back involved, settling time depends largely on Layout and circuit configuration of the system. 
         [0003]    In Conventional Art,  FIG. 1A , a High Speed Class AB Output Buffer Stage  101  is used to provide a high speed response at the output. In  FIG. 1A , CC is a constant current source, Q 1 , Q 2 , Q 3  and Q 4  are transistors. Transistor Q 1  defines an npn emitter follower arrangement, transistor Q 2  defines a pnp emitter follower arrangement, and transistors Q 3  and Q 4  define a class AB output arrangement. An emitter area m of transistor Q 1  is M. Thus, it is indicated m=M for transistor Q 1 . Similarly emitter area m of transistors Q 2 , Q 3  and Q 4  are, respectively, N, R and S. It is noted that each of emitter area sizes M, N, R and S is relatively large. The output Vout is connected to a capacitive load in series with a resistive load, as shown in  FIG. 1C . 
         [0004]    In this example, the Output Signal tends to show Variations of more than 100 uV which is to be due to the large parasitic Capacitance present in the single large Output Transistors.  FIG. 1B  illustrates an example of the variation described and this variation is also known as “Ringing” effect. Technically, settling time of this “Ringing” effect is directly related to the parasitic Capacitance of the device. 
       SUMMARY OF THE INVENTION 
       [0005]    The purpose of this invention is to provide a method to provide a stable signal (variation of less than 100 uV) during sampling by an ADC (12-bit) without increasing the ICQ greatly while maintaining a reasonable change in size. 
         [0006]    According to a conventional output stage,  FIG. 1A , a single Large Class AB Output Buffer Stage  101  is used. Due to the large Device used, the parasitic components, mainly the parasitic capacitance, present would be large, resulting in a long settling time. 
         [0007]    The invention proposed here indicates a topology to reduce further the settling time by splitting the single Large Class AB Output Stage into several branches, where the device size of each branch multiplied by the number of branches used in the multiple-branched Output Stage is the same as the sum of devices used in the Large Single Output Stage. In  FIG. 2A , a multiple branched system is used for illustration. 
         [0008]    From a system point of view, by splitting the Output Stage into several branches, each branch will incur “Ringing” effect of different magnitude and phase. As the output is common, there will be an averaging effect due to different phase and magnitude. This effect can be observed better on the actual chip compared to in simulation. 
         [0009]    This topology can be further modified to reduce the magnitude of the variation, or “Ringing” by having different sizing on the components while maintaining the same component counts. Meaning, we can further improve the performance by having a different ratio between the different branches. In the Second Preferred Embodiment,  FIG. 3 , the ratio of the 2 branches is based on the ratio is 1:2. 
         [0010]    Further explanation accompanied by simulation results will be presented in the following detailed description. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIGS. 1A ,  1 B and  1 C are diagrams showing the conventional art of the application for a high speed output stage buffer; 
           [0012]      FIG. 2A  is a circuit diagram of the first preferred embodiment, according to the present invention. 
           [0013]      FIG. 2B  is a circuit diagram of the second preferred embodiment, according to the present invention. 
           [0014]      FIG. 3  is a circuit diagram of the third preferred embodiment, according to the present invention. 
           [0015]      FIGS. 4A ,  4 B and  4 C are illustrations of the inductive effect of an emitter-follower using npn transistor. 
           [0016]      FIGS. 5A and 5B  are illustrations of the averaging effect of using a multiple branching topology. 
           [0017]      FIGS. 6A and 6B  are illustrations of the usage of multiple parallel-connected unit sized transistors. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0018]    Before describing the embodiments of the present invention, the basic concept of the invention is first explained. 
         [0019]    The present invention provides a stable signal (variation of less than 100 uV for a 12-bit ADC) during sampling by an ADC (12-bit ADC) without increasing the ICQ greatly while maintaining a reasonable change in size. 
         [0020]    Technically, the settling time of the output signal depends on several factors, mainly, the parasitic components, the current flowing through the device, the magnitude of the excitation (overshoot or undershoot), and load property. To make clear the principle used behind the present invention, an explanation of the theory involved will first be furnished: 
         [0021]    In the case of an emitter follower (Class AB Output Transistors are connected in emitter follower configuration), the settling time of the output signal largely depends on the nature of its Output Impedance, Zout. 
         [0022]      FIG. 4A  shows an npn emitter follower used to illustrate the Zout nature of an emitter follower. Technically, the emitter follower can be redrawn in its small signal diagram as shown in  FIG. 4B . By small signal analysis, 
         [0000]        Z out=( Z   π   +R   s   +r   b )/(1 +gmZ   π ) 
         [0023]    Where,
       Zπ=r π /(1+sC π r π )   r b =base resistance   R s =Source resistance       
 
         [0000]      At low frequency,  Z   π   =r   π , and  Z out≈(1 /gm )+( R   s   +r   b )/β o   (Eqn. 1) 
         [0000]      At high frequency, Z π ≈0 , Z out≈ R   s   +r   b   (Eqn. 2) 
         [0027]    At very low collector current, 1/gm is large. If (1/gm)&gt;(R s +r b ), comparing (1) and (2) shows that |Zout| decreases as frequency increases and Zout therefore appears capacitive. In an application of the present invention, a very low collector current (uA) flows through the output transistors of the Output Buffer Stage when the signal is stable, or at constant signal level. 
         [0028]    At high collector current, 1/gm is small. Usually, (1/gm)&lt;(R s +r b ), comparing (1) and (2) shows that |Zout| increases as frequency increases and Zout therefore appears inductive. In an application of the mentioned invention, a high collector current (mA) flows through the output transistors of the Output Buffer Stage when there is a change in signal level. 
         [0029]      FIG. 4C  shows an equivalent circuit of Zout seen at the output transistors of the Output Buffer Stage of the npn emitter follower in  FIG. 4A , where: 
         [0030]    R 1 =(1/gm)+(R s /β o )=Zout (at low frequency), from Eqn. 1 
         [0031]    R 2 =R s =Zout (at high frequency), from Eqn. 2 
         [0032]    L=C π r π (R s /β o ) (a typical inductance component for the output impedance of an emitter follower) 
         [0033]    Assuming R s &gt;&gt;r b  for all cases. 
         [0000]    In the application of the present invention, a capacitive load is connected, and a RLC circuit is thus formed. This RLC circuit will contribute to the “ringing” of the Output Signal. It is an objective of the present invention to make reduce the overall ‘ringing’ effect by reducing the magnitude of these components. 
         [0034]    The current invention indicates a topology to reduce the settling time by breaking the Class AB Output Buffer Stage  101  into several branches, where the total device size of the branches used in the multiple-branch Output Buffer Stage is the same as the initial device size used in the initial Output Buffer Stage. 
         [0035]    Referring to  FIG. 2A , the first preferred embodiment according to the present invention is shown, where n branches are constructed. The relationship between the transistors of the two topologies (with and without branching) and the emitter area sizes are as follows. Here, m=emitter area size. 
         [0036]    In place of transistor Q 1  shown in  FIG. 1A , the first embodiment uses a plurality of transistors Q 1   a , Q 1   b , . . . Q 1 α, where Q 1 α is an nth branch component of Q 1 . A constant current source CC is provided to each transistor. 
         [0037]    In place of transistor Q 2  shown in  FIG. 1A , the first embodiment uses a plurality of transistors Q 2   a , Q 2   b , . . . Q 2 α, where Q 2 α is an nth branch component of Q 2 . A constant current source CC is provided to each transistor. 
         [0038]    In place of a pair of transistors Q 3  and Q 4  shown in  FIG. 1A , the first embodiment uses a plurality of pairs of transistors (Q 3   a  and Q 4   a ), (Q 3   b  and Q 4   b ), . . . (Q 3 α and Q 4 α) where (Q 3 α and Q 4 α) is an nth branch component of a transistor pair (Q 3  and Q 4 ). 
         [0039]    In other words, according to the present invention, a plurality of npn emitter follower sub-arrangements Q 1   a , Q 1   b , . . . Q 1 α are provided and connected in parallel to each other. Such a plurality of npn emitter follower sub-arrangements Q 1   a , Q 1   b , . . . Q 1 α taken together define the npn emitter follower arrangement, which corresponds to transistor Q 1  shown in  FIG. 1A . As explained above, transistor Q 1  has an emitter size M. In the first embodiment, the emitter size M is divided into n pieces of emitter sizes x 1 , x 2 , x 3 , xn which are used as emitter sizes for transistors Q 1   a , Q 1   b , . . . Q 1 α, respectively. As one example, emitter sizes for transistors Q 1   a , Q 1   b , . . . Q 1 α can be the same. In this case, x 1 =x 2 =x 3  . . . =xn, and M/n=x 1 . In another example emitter sizes for transistors Q 1   a , Q 1   b , . . . Q 1 α are different, or are grouped into different sizes. 
         [0040]    Thus, transistor Q 1  is branched or separated into Q 1   a , Q 1   b , . . . Q 1 α, (where Q 1 α=nth branch component of Q 1 ), with m=M=x 1 +x 2 + . . . +xn (values of x 2 , . . . , xn are multiples of x 1 , where x 1  is a positive Real number). 
         [0041]    Similarly, according to the present invention, a plurality of pnp emitter follower sub-arrangements Q 2   a , Q 2   b , . . . Q 2 α are provided and connected in parallel to each other. Such a plurality of pnp emitter follower sub-arrangements Q 2   a , Q 2   b , . . . Q 2 α taken together define the pnp emitter follower arrangement, which corresponds to transistor Q 2  shown in  FIG. 1A . 
         [0042]    Thus, transistor Q 2  is branched or separated into Q 2   a , Q 2   b , . . . Q 2 α, (where Q 2 α=nth branch component of Q 2 ), with m=N=y 1 +y 2 + . . . +yn (values of y 2 , . . . , yn are multiples of y 1 , where y 1  is a positive Real number). 
         [0043]    Similarly, according to the present invention, a plurality of class AB output sub-arrangements (Q 3   a  and Q 4   a ), (Q 3   b  and Q 4   b ), . . . (Q 3 α and Q 4 α) are provided and connected in parallel to each other. Such a plurality of class AB output sub-arrangements (Q 3   a  and Q 4   a ), (Q 3   b  and Q 4   b ), . . . (Q 3 α and Q 4 α) taken together define the class AB output arrangement, which corresponds to transistors Q 3  and Q 4  shown in  FIG. 1A . 
         [0044]    Thus, transistor Q 3  is branched or separated into Q 3   a , Q 3   b , . . . Q 3 α, (where Q 3 α=nth branch component of Q 3 ), with m=R=a 1 +a 2 + . . . +an (values of a 2 , . . . , an are multiples of a 1 , where a 1  is a positive Real number). 
         [0045]    Thus, transistor Q 4  is branched or separated into Q 4   a , Q 4   b , . . . Q 4 α, (where Q 4 α=nth branch component of Q 4 ), with m=S=b 1 +b 2 + . . . +bn (values of b 2 , . . . , bn are multiples of b 1 , where b 1  is a positive Real number). 
         [0046]    Referring to  FIG. 2B , a second embodiment is shown. In this second preferred embodiment, a doubled branched system is used as an example of an implementation of the multiple-branch Output Buffer Stage. Here, the Class AB Output Buffer Stage is split into 2 branches. The Output Buffer Stage drives an AFE, Analog Front End, modeled as a capacitive load in series with a resistive load, as earlier described (referring to  FIG. 1C ). 
         [0047]    For the exemplary embodiment shown in  FIG. 2B , the relationship between the transistors of the two topologies (with and without branching) and the emitter area sizes are as follows, where m=emitter area size: 
         [0048]    Q 1  is branched into Q 1   a  and Q 1   b , with m=M=x 1 +x 2  (value of x 2  is a multiple of x 1 , where x 1  is a positive Real number); 
         [0049]    Q 2  is branched into Q 2   a  and Q 2   b , with m=N=y 1 +y 2  (value of y 2  is a multiple of y 1 , where y 1  is a positive Real number); 
         [0050]    Q 3  is branched into Q 3   a  and Q 3   b , with m=R=a 1 +a 2  (value of a 2  is a multiple of a 1 , where a 1  is a positive Real number); 
         [0051]    Q 4  is branched into Q 4   a  and Q 4   b , with m=S=b 1 +b 2  (value of b 2  is a multiple of b 1 , where b 1  is a positive Real number). 
         [0052]    From a system point of view, splitting the Output Stage into several branches allows reduction of the “Ringing” caused by the parasitic components due to the following reason: During Operation, each branch will incur “Ringing” effect of different magnitude and phase. As the output node of each branch is common, i.e. they share the same output, the “Ringing” effects will be averaged effect due to each branch&#39;s different phase and magnitude. Generally, the effect describe above can be observed better using the actual chip compared to in simulation as they are more layout dependent effects. 
         [0053]      FIGS. 5A and 5B  show illustrations of the averaging effects mentioned above. 
         [0054]    Referring to  FIG. 3 , the third preferred embodiment of the present invention is described. The branching topology as described for the first and second embodiments can be further improved to reduce the magnitude of the variation, or “Ringing” by having different sizing on the components while maintaining the same component counts. Meaning, we can further improve the performance by having a different ratio between the different branches. 
         [0055]    For the third preferred embodiment shown in  FIG. 3 , the relationship between the emitter area sizes are as follows: 
         [0056]    x 1 ≠x 2 ; 
         [0057]    y 1 ≠y 2 ; 
         [0058]    a 1 ≠a 2 ; 
         [0059]    b 1 ≠b 2 . 
         [0060]    The fourth preferred embodiment assigns the ratio of the 2 branches based on the ratio 1:2. Referring to  FIG. 3  again, for the fourth embodiment, the relationship between the emitter area sizes are as follows: 
         [0061]    x 1 = 2 *(x 2 ); 
         [0062]    y 1 = 2 *(y 2 ); 
         [0063]    a 1 = 2 *(a 2 ); 
         [0064]    b 1 = 2 *(b 2 ). 
         [0065]    As mentioned in the beginning of this section, there is an RLC circuit contributing to the “Ringing”. By reducing the inductive nature of Zout, the variation seen at the output signal will be at a high frequency, but at smaller magnitude. From  FIG. 4C , the inductive nature of the Output Impedance can be related to its parasitic capacitance by L=C π r π (R s /β o ). By splitting the transistor into several branches, the parasitic capacitance, C π  can be reduced, hence decreasing the inductive nature. Also, by having the 2 branches to have different sizing, the RLC circuit would experience different settling time and magnitude. This will further average out the variation at the output signal. In the fourth preferred embodiment, a ratio of 1:2 is used for a 2 branched system. This ratio is chosen as it would ensure the difference in the inductive nature between the two branches to be about twice, allowing a smoother averaging effect to between the two branches. 
         [0066]      FIGS. 6A and 6B  show the fifth preferred embodiment according to the present invention. Multiple unit transistors are arranged in parallel to obtain an equivalent emitter area of the initial transistor. Hence, as an example, based on the third preferred embodiment, to construct Q 1   a , multiple Q 1   a ′ are combined in parallel such that the emitter area of Q 1   a ′ is a unit area. 
         [0067]    Hence, for emitter area, m=x, 
         [0000]    Number of Q 1   a ′ to combine in parallel=x/1 
         [0068]    According to the present invention, an output driver with less “Ringing” effect can be provided without substantially increasing the chip size of the integrated circuit, because the emitter size is maintained substantially the same even if the number of sub-arrangement increases.