Abstract:
A comparator with hysteresis having a simplified architecture such that the amount of hysteresis can be readily adjusted. In one aspect, a comparator with hysteresis comprises a first switch for coupling an analog input voltage to a signal node in response to a first clock signal; an inverter having an input port and an output port; a capacitor operatively coupled between the signal node and an input port of the inverter; a second switch operatively connected between the input port and the output port of the inverter, the second switch being responsive to the first clock signal; a latch having a clock port, an output signal port, an inverse output signal port, and an input data port, the input data port being coupled to the output port of the inverter; and a reference voltage control circuit for selectively outputting a first internal reference voltage and a second internal reference voltage to the signal node in response to the output signal and inverse output signal, respectively, received from the latch. Positive feedback holds a comparator in one of two states unless a sufficiently large input is applied to overcome the feedback.

Description:
BACKGROUND 
     1. Technical Field 
     The present invention relates generally to a comparator and, more particularly, to a CMOS comparator with hysteresis. 
     2. Description of Related Art 
     In general, a comparator is a device which compares an input voltage with a reference voltage, amplifies the voltage differential between the input voltage and the reference voltage, and outputs a voltage signal of a high or low level based on the voltage differential. A comparator is typically employed in an analog-digital converter (such as a flash A/D converter), wherein an analog input signal is converted to a digital output signal by comparing the analog input signal with a plurality of reference voltages by using a complimentary metal-oxide semiconductor (CMOS) flash analog-digital converter. 
     Because of their high speed, flash analog-digital converters are widely employed in video devices, radar devices, laboratory instruments, and other devices which are used in high-speed applications. Other advantages associated with CMOS flash analog-digital converters are their compact size and low power dissipation, which enables them to be fabricated as monolithic integrated circuits. 
     For the comparator output voltage to be maintained at a high level state at a zero point, hysteresis is used to prevent the output voltage from changing as the input voltage is reduced. When the input voltage drops to a lower reference voltage (a negative trip point), the output voltage changes from the high level state to a low level state. The comparator output voltage will remain in the low level state as the input voltage increases. When the input voltage reaches an upper reference voltage (a positive trip point), the output voltage will change from the low level state to the high level state. The difference in voltage between the upper reference voltage and the lower reference voltage is known as the amount of the hysteresis. It is to be understood that the terms “high level state” (or “high”) and “low level state” (or “low”) used herein in connection with signals and logic levels are equivalent to logic levels “1” and “0”, respectively. 
     Referring to FIG. 1, a circuit diagram illustrates a conventional comparator with hysteresis. Although there are many techniques known by those skilled in the art for providing hysteresis in a comparator, all of the conventional techniques employ some form of positive feedback. Consider the differential input stage as shown in FIG.  1 . In this circuit, there are two feedback paths. The first feedback path is a current-series feedback through the common-source node of transistors M 1  and M 2 , which is a negative feedback path. The second feedback path is the voltage-shunt feedback through the gate-drain connections of transistors M 10  and M 11 , which is a positive feedback path. It is understood by those skilled in the art that if the positive feedback factor is less than the negative feedback factor, the overall feedback will be negative, thus resulting in no hysteresis. On the other hand, If the positive feedback factor is greater than the negative feedback factor, the overall feedback will be positive, which results in hysteresis (such as illustrated by the voltage transfer curve of FIG.  5 ). 
     A comparator is typically employed in a noisy environment, thereby requiring hysteresis to ensure a noise margin. With the conventional comparator shown in FIG. 1, the desired amount of hysteresis can be determined in accordance with the ratio of size of MOS transistors. Unfortunately, in order to control the trip voltages (and, therefore, the amount of the hysteresis), the comparator must be entirely reconstructed or an additional process is required for changing the ratio of size of transistors. As a result, it difficult to control the amount of the hysteresis. Another problem is that the conventional comparator also includes bias circuitry, which adds to the difficulty in controlling the amount of hysteresis. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a comparator with hysteresis having a simplified architecture such that the amount of hysteresis can be readily adjusted. 
     In one aspect of the present invention, a comparator with hysteresis comprises: 
     a first switch for coupling an analog input voltage to a signal node in response to a first clock signal; 
     an inverter having an input port and an output port; 
     a capacitor operatively coupled between the signal node and the input port of the inverter; 
     a second switch operatively connected between the input port and the output port of the inverter, the second switch being responsive to the first clock signal; 
     a latch having a clock port, an output signal port, an inverse output signal port, and an input data port, the input data port being coupled to the output port of the inverter; and 
     a reference voltage control circuit for selectively outputting a first internal reference voltage and a second internal reference voltage to the signal node in response to the output signal and inverse output signal, respectively, received from the latch. 
     In another aspect of the present invention, the reference voltage control circuit has a logic circuit for outputting control signals responsive to a second clock signal and the output signals of the latch. A reference voltage generating circuit outputs selectively a first internal reference voltage and a second internal reference voltage among a plurality of the internal reference voltages based on a first and second external reference voltages to the signal node. Second analog switches outputs selectively one of the first and the second internal reference voltages to the signal node. 
     In yet another aspect of the present invention, the reference voltage control circuit of the comparator comprises: 
     a logic circuit for outputting one of a first and second control signal in response to a second clock signal and the output signal and inverse output signal of the latch; 
     a reference voltage generating circuit for outputting the first internal reference voltage and the second internal reference voltage to the signal node, the first internal reference voltage and the second internal reference voltage being selected from a plurality of available reference voltages generated by dividing a first and a second external reference voltage; and 
     a third and fourth switch for selectively outputting the first and second internal reference voltages, respectively, to the signal node, in response to the first and second control signals, respectively. 
     In another aspect of the present invention, a comparator having a controllable amount of hysteresis, comprises: 
     means for comparing an input voltage with one of an upper threshold voltage and a lower threshold voltage depending on an output state of the comparator, wherein the difference between the upper and lower threshold voltages is the amount of hysteresis; and 
     means for adjusting the amount of hysteresis by selecting a first one of a plurality of reference voltages as the upper threshold voltage and for selecting a second one of the plurality of reference voltages as the lower threshold voltage. 
     These and other aspects, features and advantages of the present invention will be described and become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram of a conventional comparator with hysteresis; 
     FIG. 2 is a diagram illustrating a comparator with hysteresis in accordance with an embodiment of the present invention; 
     FIG. 3 is a detailed circuit diagram illustrating a preferred embodiment of the reference voltage generating circuit of FIG. 2; 
     FIG. 4 is a timing diagram illustrating complementary clock signals used for operating the comparator of FIG. 2; and 
     FIG. 5 is a transfer characteristic graph of the comparator with the hysteresis. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring now to FIG. 2, diagram illustrates a comparator with hysteresis in accordance with one embodiment of the present invention. The comparator receives as input an analog input voltage Vin. The comparator generates a first and second internal reference voltage V RP  and V RN , which determine the amount of hysteresis. The comparator comprises analog switches  21  and  24 , a capacitor  25 , an inverter  26 , a latch  27 , and a reference voltage control circuit  40 . The reference voltage control circuit  40  includes a reference voltage generating circuit  10 , switches  22  and  23 , and a logic circuit  28 . The inverter  26  includes an input port N 2  (or alternatively referred to as “node N 2 ”) and an output port N 3  (alternatively referred to as “node N 3 ”). The inverter  26  generates a logic level signal which is output to node N 3 . The inverter  26  is preferably a CMOS inverter. The capacitor  25  is coupled between signal node N 1  and node N 3  (i.e., the input port of the inverter  26 ). The analog switch  21  supplies an analog input voltage Vin to the signal node N 1  in response to a first clock signal CLK 1 . The analog switch  24  is coupled between node N 2  and node N 3  of the inverter  26 . 
     The latch  27  comprises a clock port CK, output ports Q and Q, and an input data port D coupled to the output port N 3  of the inverter  26 . The latch  27  generates a signal and an inverse signal which are output from ports Q and {overscore (Q)}, respectively, in accordance with the logic level signal of the output port N 3  of the inverter  26 . 
     The reference voltage control circuit  40 , operatively coupled between the signal node N 1  and the output ports Q and {overscore (Q)} of the latch  27 , selectively outputs the first and second internal reference voltages V RP  and V RN  to the signal node N 1  based on the output signals of the latch  27 . In particular, the reference voltage control circuit  40  comprises a logic circuit  28  which generates switch control signals S 1  and S 2  in response to a second clock signal CLK 2  and the output signals of the latch  27  to selectively control switches  22  and  23 . In response to the switch control signals S 1  and S 2 , the reference voltage generating circuit  10  will selectively output the internal reference voltages V RP  and V RN  to the signal node N 1 . As explained in detail below, the magnitude of the internal reference voltages V RP  and V RN  can be varied to control the amount of hysteresis. The analog switches  22  and  23  selectively output one of the first and second internal reference voltages V RP  and V RN  to the signal node N 1 . The reference voltage generating circuit  10  generates the first and second internal reference voltages V RP  and V RN  in response to an externally applied control signal S 3 . 
     The logic circuit  28  comprises a first AND gate  29  and a second AND gate  30 . The first AND gate  29  receives the second clock signal CLK 2  and the inverse output signal {overscore (Q)} from the latch  27  and then outputs the first switch control signal S 1  to control switch  22 . The second AND gate  30  receives the second clock signal CLK 2  and output signal Q from the latch  27 , and then outputs the second control signal S 2  to control switch  23 . When activated, switch  22  and switch  23  couple the first and second internal reference voltages V RP  and V RN  to the signal node N 1 , respectively. In particular, the first control signal S 1  activates switch  22 , which causes the first internal reference voltage V RP  to be output from the reference voltage generating circuit  10  to the signal node N 1 . The second control signal S 2  activates switch  23 , which causes the second internal reference voltage V RN  to be output from the reference voltage generating circuit  10  to the signal node N 1 . 
     The first clock signal CLK 1  controls switches  21  and  24  by turning them on and off. When activated, switch  21  couples the analog input voltage Vin to the signal node N 1  and switch  24  couples the input node N 2  of the inverter  26  to the output node N 3  of the inverter  26 . The first and second clock signals CLK 1  and CLK 2  are complementary to each other. When the clock signal CLK 1  is high and the clock signal CLK 2  is low, the switch  21  is activated and switches  22  and  23  are deactivated. When the clock signal CLK 1  is low and the clock signal CLK 2  is high, switch  21  is deactivated and switches  22  and  23  are activated. The logic circuit  28  is controlled by the second (complementary) clock signal CLK 2 . 
     The latch  27  is controlled by the clock signal CLK 1  (which is input to the clock port CK). The latch  27  may be any conventional circuit comprising a data input port D and a clock port CK and two data output ports Q and {overscore (Q)}. When the clock signal CLK 1  is high, the signal from the data output port Q has the same logic level as the signal at the data input port D. When the clock signal CLK 1  goes low, the current logic level of the signal from the data output port Q is latched, and the signal level at the data output port Q remains at that logic level until the clock signal CLK 1  goes high again. 
     The logic circuit  28  comprises a first and second two-input AND gates  29  and  30  and is controlled by the second clock signal CLK 2 . In particular, the two inputs of the AND gate  29  are the clock signal CLK 2  and the output signal from the output port {overscore (Q)} of the latch  27 , respectively. Moreover, the two inputs of the AND gate  30  are the clock signal CLK 2  and the output signal from the output port Q of the latch  27 , respectively. The AND gates  29  and  30  generate the switch control signals S 1  and S 2 . The switch control signals S 1  and S 2  respectively drive switches  22  and  23 . 
     Referring now to FIG. 3, a diagram illustrates a preferred embodiment of the reference voltage generating circuit  10 . The reference voltage generating circuit  10  comprises a first node  1  for receiving a first external reference voltage Vref+, and a second node  2  for receiving a second external reference voltage Vref−. A plurality of resistors R 1 -R 4 , serially coupled between the first and second nodes  1  and  2 , are employed for dividing the external reference voltages Vref+ and Vref− into a plurality of internal reference voltages. 
     The internal reference voltages (which are divided by the resistors R 1 -R 4 ) are selectively output through the plurality of switches S 21 -S 26 , such that the first internal reference voltage V RP  is output to a first output port  3 , and the second internal reference voltage V RN  is output to a second output port  4 . The plurality of switches S 21 -S 26  are controlled by a plurality of select signals S 11 -S 13  from a select circuit  15 . The select circuit  15  is controlled by the externally applied control signal S 3 . The control signal S 3  is preferably a select signal (e.g., 2 bits) supplied from a main controller (not shown). 
     The plurality of switch S 21 -S 26  comprise two switch groups. As shown, the first switch group has M switches, e.g., switches S 21 -S 23 , and a second switch group has N switches, e.g., switches S 24 -S 26 . The first switch group outputs the first internal reference voltage V RP  to the first output port  3  in response to the select signals S 11 -S 13  from the select circuit  15 . The second switch group outputs the second internal reference voltage V RN  to the second output port  4  in response to the select signals S 11 -S 13  from the select circuit  15 . With this embodiment, it is to be appreciated that the trip voltages can be controlled by the switches, e.g., switches S 21 -S 26 , thereby controlling the amount of the hysteresis of the comparator. 
     It is to be understood that the reference voltage generating circuit has been described comprising 3 switches for the first and second switch groups solely for purposes of illustration and convenience and that one of skilled in the art may implement any number of the above described switches in the reference voltage generating circuit  10  depending on the application. It is to be further understood that the reference voltage generating circuit  10  may comprise any number of resistors for generating a plurality of divided voltages and outputting a desired voltage among the divided voltages. 
     Referring again to FIG. 2, when the reference voltage generating circuit  10  outputs the first and second internal reference voltages V RP  and V RN , the respective switches  22  and  23  is activated, thereby supplying one of the first and second internal reference voltage V RP  and V RN  to the signal node N 1 . The comparator generally operates by comparing the input analog voltage Vin with either the first and second internal reference voltages V RP  and V RN , whichever is currently supplied to node N 1 . Specifically, the switches  21  and  24  are simultaneously activated by clock signal CLK 1 , so that the analog input voltage Vin is supplied to the signal node N 1 . Since the input node N 2  of the inverter  26  is coupled to the capacitor  25 , the voltage of node N 2  is supplied by a self-bias voltage caused by properly controlling in the ratio of the size of the MOS transistors of the inverter  26 . For example, when the analog input voltage is 2 V and the voltage of the input node N 2  is 1.5 V caused by the self-bias voltage, the voltage of the capacitor  25  is Vin−V2 (2 V−1.5 V). The self-bias voltage is determined based on the ratio of the size of NMOS and PMOS transistors of the inverter  26 , which typically is approximately Vdd/2. 
     FIG. 4 is a timing diagram of the clock signals CLK 1  and CLK 2 . As shown, the clock signal CLK 1  is complementary to the clock signal CLK 2 . When the switch  21  is deactivated by the clock signal CLK 1  and the switch  22  is activated by the first control signal from the logic circuit  28 , the first internal reference voltage V RP , e.g. 1.6 V is supplied to the signal node N 1 . When switch  21  is deactivated, the switch  24  coupled between the input port N 2  and output port N 3  of the inverter  26  is also deactivated. The voltage of the input node N 2  applied by the self-bias voltage is dropped as much as the voltage of the signal node N 1 , e.g. 2 V−1.6 V, so that the voltage of the input node N 2  becomes 1.1 V. 
     The inverter  26  inverts the signal at node N 2  and outputs a logic 1 signal to the output node N 3  thereof. The latch  27  receives the logic 1 signal at the data input port D, and then outputs a logic 1 signal to the output port Q and outputs the inverse output signal (i.e., logic 0) to the output port. These output signals are supplied to the logic circuit  28  (i.e, the AND gates  29  and  30 ). 
     Although the AND gates  29  and  30  receive the clock signal CLK 2  (of logic 1) simultaneously, the output signal from the output port Q of the latch  27  is complementary to the output signal from the output port {overscore (Q)} such that the switch control signals S 1  and S 2  output from AND gates  29  and  30  are not output to the switches  22  and  23  simultaneously. 
     The switches  21  and  24  are simultaneously activated by the clock signal CLK 1  when the analog input voltage Vin is input. When the clock signal CLK 1  is logic 0 and the clock signal CLK 2  is logic 1, one of the switches  22  and  23  will be activated by one of the first and second control signals S 1  and S 2  from the logic circuit  28 . As a result, one of the first and second internal reference voltages V RP  and V RN  is output from the reference voltage generating circuit  10  to the signal node N 1 . 
     During operation of the comparator of FIG. 2, the analog input signal Vin will be compared with one of the first and second internal reference voltages V RP  and V RN . Assume that the analog input signal Vin is first compared with the first internal reference voltage V RP . The voltage V N2  of the input node N 2  becomes −(Vin−V RP ) pursuant to the theory of charge conservation. Since the switch  24  is deactivated, the voltage of the input node N 2  is shown as much as an amount of the voltage variation of the analog input signal Vin. 
     Accordingly, the output voltage V N3  of the inverter  26  becomes −A[V N2 −(Vin−V RP ). Thereafter, the voltage V N2  of the input node N 2  applied by the self-bias voltage is dropped as much as the voltage of the signal node N 1 , e.g. 2 V−1.6 V, so that the voltage V N2  of the input node N 2  becomes 1.1 V. Thus, the output voltage V N3  of the inverter  26  becomes the high level signal. Since this high level signal is input to the data input port D of the latch  27 , the latch  27  outputs the output signal from the output port Q. 
     When the output signal Q of the latch  27  is logic 1, the switch  23  is activated. The reference voltage generating circuit  10  then outputs the second internal reference voltage V RN , which is less than the first internal reference voltage V RP . Accordingly, the amount of the hysteresis of the comparator is based on the second internal reference voltage V RN . 
     The analog input signal Vin is higher than the second internal reference voltage V RN . Although the noise is input to the analog input signal Vin, the output signal of the latch  27  keeps the high level signal so long as the analog input signal Vin is greater than the second internal reference voltage V RN . When the analog input signal Vin becomes less than the second internal reference voltage V RN , the output signal Q of the latch  27  becomes logic 0. 
     The switch  22  is then activated by the high level signal (switch control signal S 1 ) output from AND gate  29 , and the reference voltage generating circuit  10  outputs the first internal reference voltage V RP , which is greater than the second internal reference voltage V RN . Accordingly, the amount of the hysteresis of the comparator is determined by the first internal reference voltage V RP . Therefore, as described above, the amount of the hysteresis ΔV H  may be controlled by the first internal reference voltage V RP  and the second internal reference voltage V RN . 
     Referring now to FIG. 5, a transfer characteristic graph illustrated hysteresis of the comparator of FIG.  2 . As explained above, hysteresis is a characteristic of the comparator in which the input threshold voltage changes as a function of the input or output level. In particular, when the analog input voltage passes the threshold, the output voltage changes and the input threshold voltage is subsequently reduced so that the analog input voltage must return beyond the previous threshold voltage before the comparator&#39;s output voltage changes state again. This is illustrated with the diagram of FIG.  5 . 
     Notice that as the analog input voltage Vin starts negative and goes positive, the output voltage Vo does not change until it Vin reaches the positive trip point V RP . Once the output voltage goes high, the effective trip point is changed. When the analog input voltage Vin decreases in the negative direction, the output voltage Vo does not switch from logic high to logic low until Vin reaches the negative trip point V RN . The advantage of hysteresis in a noisy environment may clearly be seen. 
     The first internal reference voltage V RP  is an upper threshold voltage (a positive trip point) with the hysteresis when the output voltage is changed from a low level to a high level, and the second internal reference voltage V RN  is a lower threshold voltage (a negative trip point) with the hysteresis when the output voltage is changed from the high level to the low level. 
     The output voltage of the comparator remains at logic 1 until the analog input voltage reaches to the lower threshold voltage, e.g. the second internal reference voltage V RN  from the initial state of logic 1. However, when the analog input voltage Vin decreases below the lower threshold voltage, e.g. the second internal reference voltage V RN , the output voltage switches to logic 0. As the analog input voltage Vin increases, the output voltage remains at logic 0 until the analog input voltage reaches to the upper threshold voltage, e.g. the first internal reference voltage V RP , at which time the output signal switches to logic 1. When the clock CLK 2  is active, the upper and lower threshold voltage is selected by the AND gates  29  and  30  of the logic circuit  28 . 
     As described above, the upper and lower threshold voltages are the first and second internal reference voltages V RP  and V RN  which are compared with the analog input voltage. The first and second internal reference voltages V RP  and V RN  are generated by voltage dividing a pair of external voltages using a plurality of resistors, and selected one of the first group switches and one of the second group switches. Since the amount of hysteresis ΔV H  can be selectively varied by modifying the difference of the upper and the lower threshold voltages, the select circuit  15  outputs the select signal which controls the switches in order to output the divided voltage to the first and second output ports  3  and  4 . 
     Advantageously, the comparator with hysteresis described above in accordance with the present invention comprises a reference voltage generating circuit which comprises a plurality of resistors that allows the magnitude of the internal reference voltages to be controlled, thereby controlling the amount of hysteresis of the comparator. Since the internal reference voltages of the reference voltage generating circuit may easily be generated, the comparator requires neither reconstruction nor additional processes to control the hysteresis, thereby simplifying the manufacture of the comparator. 
     Although illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those precise embodiments, and that various other changes and modifications may be affected therein by one skilled in the art without departing from the scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims.