Abstract:
The magnitude of successive peaks in a time varying electrical signal are measured by applying the signal to magnitude circuitry capable of providing an output related to signal magnitude. The circuitry has a first state during which the output is dependent of changes in signal magnitude and a second state during which the output is substantially independent of such changes. The circuitry enters the first state during a first time interval within which a first peak is applied to the magnitude circuitry, and during a second time interval within which a second peak is applied to the magnitude circuitry. During a third time interval intermediate the first and second time intervals, the circuitry enters the second state. The magnitude circuitry&#39;s output during the second time interval is independent of its output during the third time interval so that successive outputs of the circuitry are related to the respective magnitudes of said successive peaks.

Description:
This is a continuation of application Ser. No. 07/544,229, filed Jun. 26, 1990, now abandoned. 
    
    
     BACKGROUND OF INVENTION 
     This invention relates to an apparatus for producing a DC electrical signal whose level is representative of the magnitude of the most recent peak of a time varying signal. 
     Peak detectors receive an AC input signal and, in response, provide a DC signal whose level is approximately equal to the amplitude of the AC input. Capacitive peak detectors apply the received AC input to a diode connected in series with a capacitor. When the AC input voltage exceeds the capacitor&#39;s voltage, the diode turns on to charge the capacitor up to the voltage of the AC input. Once the AC input reaches its peak and begins falling, the diode shuts off, preventing the capacitor from discharging downward with the AC input. 
     Since capacitors tend to discharge internally, the capacitor voltage slowly decays below the peak level. However, if the next peak arrives relatively soon, the capacitor voltage will not decay substantially before rising upward with the new peak. Accordingly, if the frequency of the input signal is high relative to the rate of the capacitor&#39;s discharge, the capacitor will provide a DC voltage whose level is approximately equal to the magnitude of the most recent peak of the AC input. 
     If the amplitude of a low peak of the AC input is less than the capacitor voltage, the diode will remain off and the capacitor voltage will not change in response to the arrival of the peak. Since the capacitive peak detector has no mechanism for changing the capacitor voltage downward to match the relatively low peak, the capacitor voltage level will not be representative of the relatively low peaks. Further, if the frequency of the AC input signal is low relative to the rate of the capacitor&#39;s discharge, the capacitor voltage may discharge substantially between peaks such that its level between peaks is not representative of the amplitude of the AC input signal. 
     SUMMARY OF THE INVENTION 
     In general, the invention features magnitude circuitry that provides an output related to the magnitude of successive peaks during successive time intervals within which those peaks are applied to the magnitude circuitry; the output is independent of changes in signal magnitude during a time interval intervening between those successive time intervals. Similarly, during the intervals within which the peaks are applied, the output is independent of the output during the intervening interval. 
     In preferred embodiments the magnitude circuitry includes a track and hold amplifier which tracks signal magnitudes during successive time intervals within which signal peaks are expected to rise and does not track signal magnitudes between those successive time intervals. Peak arrival time is forecast by comparing the signal to a delayed version of itself and watching for magnitude cross-overs; when the signal is decaying from a peak, its magnitude will be smaller than that of its delayed version, whereas as the signal rises toward a new peak, its magnitude will eventually cross-over to become larger than its delayed version. The delayed signal is the one actually applied to the track and hold amplifier to give time to make the comparison just discussed and to activate the amplifier to its tracking mode. The track and hold amplifier is returned to its non-tracking mode quickly after passage of each peak, so that the amplifier output will bear a known relationship to peak magnitude; to that end, the amplifier is kept in the tracking mode for a preset time interval, the start of which is adjusted so that the interval ends when the signal substantially equals its peak. To prevent below-peak signal fluctuations from falsely triggering the tracking mode, a threshold qualifier prevents triggering when the signal level is below the expected peak ranges. 
     The invention provides several advantages. For example, the peak detector provides an output voltage level which adjusts upward in response to a relatively high peak, and downward in response to a relatively low peak. Further, if electrical noise is superimposed on the signal, the output will rise with peaks which are artificially high due to positive noise and fall with peaks which are artificially low due to negative noise. Accordingly, the noise tends to average out over time. 
     Further, since the peak detector maintains its output at a constant level during the time interval between adjacent peaks, the output level is largely independent of whether the peaks of the input signal are close together or far apart in time. 
     Other features and advantages of the invention will be apparent from the following description of the preferred embodiment and from the claims. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     We first briefly describe the drawings. 
     Drawings 
     FIG. 1 is a schematic diagram of a peak follower circuit. 
     FIGS. 2-4 are timing diagrams illustrating the operation of the peak follower circuit of FIG. 1. 
    
    
     The peak follower circuit 6 depicted in FIG. 1 provides a DC output signal V o  having a voltage level approximately equal to the most recent peak of an input signal V i . The input signal V i  is applied to an equalizer circuit 36 connected in series with a peak forecast circuitry 44 to produce a delayed form V d  of input signal V i . Delayed signal V d  is then applied to input 8 of magnitude circuitry 10 (here, a track and hold amplifier). 
     Magnitude circuitry 10 has two states of operation. While in the first state (the tracking state), magnitude circuitry 10 adjusts its output signal V o  to track changes in V d . When magnitude circuitry 10 switches to the second state (the hold state) it latches V o  at its current level and holds V o  at that level regardless of changes in V d . The state of magnitude circuitry 10 is determined by the logic level of track enable signal E generated by enable control circuitry (here, the combination of peak forecast circuitry 44 and duration control circuitry 54). 
     Referring to FIG. 2, at time T 0 , slightly before V d  reaches a peak 50, duration control circuitry 54 asserts enable signal E, thereby instructing magnitude circuitry 10 to enter the tracking state. Since, at time T 0 , V d  is greater than output signal V o , magnitude circuitry 10 begins raising V o  until it equals V d  at time T 1 . Once the two signals are equal, magnitude circuitry 10 continues to adjust V o  to follow changes in V d  for as long as enable signal E is asserted (i.e., for the duration of a first time interval). 
     Ideally, duration control circuitry removes enable signal E, thereby terminating the first time interval, at the time that V d  reaches its peak (at time T 2 ); as described below, however, the duration of enable signal E is established by the time delay imposed by delay circuit 18. In response, magnitude circuitry 10 changes to the holding state thereby latching V o  at time T 2 . Thus, as V d  drops away from its peak 50, V o  remains constant at the same level as at time T 2 . 
     At each subsequent peak of V d , duration control circuitry 54 briefly asserts enable signal E to allow V o  to adjust to the new peak level. For example, in the timing diagram of FIG. 2, the next peak 52 of V d  is slightly lower than the previous peak 50. Accordingly, when enable signal E becomes active at time T 0  &#39; (to initiate a second time interval), V o  tracks downward to meet V d  and follows V d  until enable signal E is removed at time T 2  &#39; (thereby terminating the second time interval). Thus, the output V o  in the second time interval is independent of its magnitude while in the preceding holding state (i.e., a third time interval between times T 2  and T o  &#39;). 
     If duration control circuitry 54 continues asserting track enable signal E after V o  has reached the new peak level, V o  will continue tracking V d  downward to a level below the peak. Thus, enable signal E is ideally removed just as V o  has reached the peak of V d . However, since magnitude circuitry 10 requires a certain response time to change its output from an old peak level to a new peak level, tracking must be enabled prior to the arrival of the new peak to allow sufficient time for magnitude circuitry to adjust to the new level. This requires predicting when the peak will arrive. Toward this end, peak forecast circuitry 44 monitors a non-delayed form V n  of input signal V i  (non-delayed form V n  is provided by equalizer circuitry 36 which will be explained below). Since V n  leads its delayed form V d , any peak of V d  will first arrive at V n . Thus, by detecting a peak on non-delayed form V n , peak forecast circuitry 44 is able to forecast the arrival of a peak of V d . 
     Forecast circuitry 44 includes delay line 12 for receiving V n  and generating delayed form V d . As illustrated in the timing diagram of FIG. 3, V n  begins rising toward a peak at time T 3  and reaches the peak at time T 4 . As V n  falls from the peak, V d  approaches V n  until crossover time T 5  when the two signals become equal. This crossover indicates that V n  has recently reached a peak which has yet to arrive on delayed form V d . 
     Peak forecast circuitry 44 further includes a comparator 14 to detect when a crossover has occurred. The delayed form V d  is applied to the inverting input of comparator 14 and the non-delayed form V n  is applied to its noninverting input. In response to these inputs, comparator 14 provides start signal S. As illustrated in FIG. 3, when V d  crosses V n  at time T 5 , comparator 14 switches start signal S from a logic 1 level to a logic 0 level. Soon after this transition, V d  reaches a peak at time T 6 . The falling edge of start signal S thus forecasts the arrival of a peak on V d . 
     &#34;Start&#34; signal S is applied to duration control circuitry 54. Shortly after receiving the falling edge of start signal S, duration control circuitry 54 asserts enable signal E for a preset tracking time interval TI. For reasons to be explained ahead, start signal S is first passed through delay line 20 to produce a deferred start signal S d . S d  is then applied to the clock input /CK of flip flop 16. On the falling edge of S d , flip flop 16 changes its output Q to match a reference logic level V 1  (i.e., logic 1) applied to input terminal D. The flip flop output Q thereby asserts enable signal E to initiate the tracking interval TI. Tracking interval TI must be sufficiently long (e.g., 3 nsec) to allow magnitude circuitry 10 to adjust its output to a new level. To provide the desired 3 nsec tracking interval, enable signal E is passed through a 3 nsec delay line 18 whose output E d   is connected to the reset input R of flip flop 16. The output E d  of delay line 18 thus resets flip flop 16 to remove the enable signal E 3 nsec after it was asserted. 
     Ideally, the 3 nsec tracking time interval should terminate just as V o  has reached a peak level (e.g., 50, 52). However, comparator 14 and flip flop 16 introduce delays which because of manufacturing variations cannot be precisely predicted. Since these variations operate to shift the tracking time interval, adjusting circuitry (here, a delay line 20) is manually adjusted by an operator to shift the 3 nsec tracking interval by an amount Δt (FIG. 3). Ideally, Δt shifts tracking interval TI such that the tracking interval terminates approximately when V o  has risen to the peak level. 
     As explained above, input signal V i  is applied to equalizer 36 to produce non-delay form V n . Equalizer 36 compensates for distortion introduced by delay line 12. More specifically, delayed form V d  generated by delay line 12 is slightly attenuated from the non-delayed form V n . The degree of attenuation is greater for high frequency components of V n  than for low frequency components. To compensate for this attenuation, capacitor 38 and resistors 40, 42 of equalizer 36 attenuate the low frequency components of the input signal V i  to a greater degree than the high frequency components. Accordingly, the nondelayed form V n  of the input signal V i  provided by equalizer 36 is deliberately distorted such that the attenuation introduced by delay line 12 simply cancels that of the equalizer. As a result, the amplitude of V d  is proportional to that of input signal V i  regardless of V i  &#39;s frequency. 
     Referring again to the timing diagram of FIG. 3, peak follower circuit 6 may be used in a disk/head tester device wherein input signal V i  may remain at zero for a protracted period of time between pulses. For example, at time T 7  the non-delayed form V n  of input signal V i  reaches zero and remains at that level for a length of time which exceeds the delay of delay line 12. At time T 8 , the zero level has propagated through delay line 12 so that the delayed form V d  is also equal to zero. Since the inputs to comparator 14 are thus equal, slight noise on either input will trigger comparator 14 to change the level of start signal S thereby sending false triggers 48 to duration control circuitry 54. 
     To suppress false triggers 48, threshold qualifier circuitry 22 disables comparator 14 during periods when false triggers might occur. Threshold qualifier 22 includes envelope follower circuitry 46 which essentially functions as a diode 26 connected in series with a capacitor 24. A second delayed form V d2  is applied to envelope follower circuitry 46 to rapidly charge capacitor 24 through diode 26. As shown in the timing diagram of FIG. 4, at time T 9 , V d2  rises above capacitor voltage V c  thereby turning on diode 26. Capacitor 24 rapidly charges through diode 26 such that the capacitor voltage V c  tracks V d2 . However, at time T 10 , V d2  reaches its peak and begins falling. Once V d2  falls below capacitor voltage V c , diode 26 shuts off and the capacitor begins discharging slowly through resistors 28, 30. The slow discharge rate causes capacitor 24 to remain near the peak voltage level of V d2 . 
     Resistors 28, 30 operate as a simple voltage divider to provide a voltage V T  representing a fraction of the capacitor voltage V c . Comparator 32 compares V T  with V d2  to determine when V d2  rises above threshold V T . At time T 11 , V d2  exceeds V T , causing the output V Q  of comparator 32 to switch positive (i.e., to logic one). At time T 12 , V d2  fall below V T  causing V Q  to return to a logic zero level. 
     Output V Q  is applied to an enable input of comparator 14 to disable comparator 14 while V Q  is at a logic zero level. While comparator 14 is disabled, start signal S is held at zero, thereby preventing false triggers caused by noise. The timing of the start signal S as qualified by threshold qualifier 22 (herein the &#34;qualified start signal&#34;) is shown in FIG. 4. The qualified start signal S switches to logic level one with the assertion of V Q  (see times T 11 , T 11  &#39;). However, qualified start signal S still falls to zero when V d  crosses V n  (see crossover times T 5  and T 5  &#39;). 
     Threshold voltage V T  is chosen to be sufficiently high that noise pulses on V i  which propagate to V d2  will not exceed V T  thereby enabling comparator 14 at an improper time. However, V T  is not so high that low level signal peaks are effectively ignored. For example, V T  may be chosen to be 25 to 50 percent of capacitor voltage V c . 
     If input signal V i  remains near zero for a sufficiently long period of time, capacitor 24 discharges through resistors 28,30, thereby lowering the threshold V T . However, if V T  were to fall to zero, comparator 32 would no longer disable comparator 14 while input V i  is near zero. In this event, while V i  was near zero, noise on its delayed form V d2  would then trigger comparator 32 to assert V Q  thereby intermittently enabling comparator 14. To prevent V T  from falling to zero, pull-up resistor 34 is connected between the inverting input terminal of comparator 32 and a DC pull-up voltage signal V DC . Resistors 34, 30 thus operate as a voltage divider to provide a minimum threshold voltage V T  representing a fraction of the DC pull-up voltage V DC . 
     It should be noted that the non-delayed form V n  may be applied to envelope follower 46 in lieu of delayed signal V d2 . Since both signals have essentially the same peak voltage, envelope follower circuitry 46 will generate the same threshold level V T  with either input. However, by using the delayed version V d2 , comparator 14 is not enabled until shortly after the nondelayed form V n  has passed the threshold V T . The enabling of comparator 14 can be further delayed by selecting a different tap of delay line 12 to be used in lieu of V d2 . 
     The above described threshold qualifier thus suppresses false triggers which might arise while input signal V i  remains near level zero for a protracted period of time, as is common when the threshold qualifier is used in a disk head/tester device. However, peak follower circuit 6 may be used in other devices which may generate input signals V i  which have plateaus at higher voltage levels (e.g., above V T ). Since a plateau at any level can cause the inputs of comparator 14 to be temporarily equal thereby generating false triggers, an alternative threshold qualifier may be used to disable comparator 14 during such high level plateaus. Like threshold qualifier 22, an alternative qualifier should effectively determine when the input signal has not varied for a significant period of time and then prevent this period from being mistaken as a peak by preventing enable signal E from being asserted. 
     The above described peak follower circuit 6 provides several advantages. For example, it generates an output signal whose level adjusts both upward and downward to match the magnitude of the most recently received peak. If a relatively low peak of input signal V i  arrives after a relatively high peak, the magnitude circuitry will decrease its output to a level corresponding to the magnitude of the low peak. Further, if electrical noise is superimposed on the output signal, the output will follow peaks which are artificially high due to positive noise and peaks which are artificially low due to negative noise. Accordingly, the noise tends to average out over time. 
     Since the track and hold circuit maintains its output at a constant level during the time interval between adjacent peaks, the output level is largely independent of whether the peaks of the input signal are close together or far apart in time. 
     Other embodiments are within the following claims.