Abstract:
The invention relates to a method for operating a sense amplifier connecting/disconnecting circuit arrangement, and to a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for connecting a sense amplifier device to a bit line or to a cell field region, respectively, and for disconnecting the sense amplifier device from the bit line or from the cell field region, respectively, as a function of the state of a control signal applied at a control line; a driver device for driving the control signal, wherein an additional device, in particular an additional switch is provided, by means of which a change of state of the control signal applied at the control line can be effected.

Description:
CLAIM FOR PRIORITY  
       [0001]     This application claims the benefit of priority to German application number 10339894.5, filed on Aug. 29, 2003, the contents of which are hereby incorporated by reference.  
       TECHNICAL FIELD OF THE INVENTION  
       [0002]     The invention relates to a sense amplifier connecting/disconnecting circuit arrangement, and to a method for operating such a circuit arrangement.  
       BACKGROUND OF THE INVENTION  
       [0003]     With semiconductor memory devices, one differentiates between so-called functional memory devices (e.g. PLAs, PALs, etc.), and so-called table memory devices, e.g. ROM devices (ROM=Read Only Memory), and RAM devices (RAM=Random Access Memory or write-read memory, respectively).  
         [0004]     A RAM device is a memory for storing data under a predetermined address and for reading out the data under this address later.  
         [0005]     The corresponding address may be input in the RAM device via so-called address input pins. For inputting and outputting the data, a plurality of, e.g.  16 , so-called data input/output pins (I/Os or Inputs/Outputs) are provided. By applying an appropriate signal (e.g. a Read/Write signal) to a write/read selection pin, it can be selected whether (currently) data are to be stored or to be read out.  
         [0006]     Since it is intended to accommodate as many memory cells as possible in a RAM device, one has been trying to realize same as simple as possible. In the case of so-called SRAMs (SRAM=Static Random Access Memory), the individual memory cells consist e.g. of few, for instance 6, transistors, and in the case of so-called DRAMs (DRAM=Dynamic Random Access Memory) in general only of one single, correspondingly controlled capacitor, with the capacitance of which one bit each can be stored as charge. This charge, however, remains for a short time only. Therefore, a so-called “refresh” must be performed regularly, e.g. approximately every 64 ms.  
         [0007]     For technological reasons, the individual memory cells in memory devices, in particular DRAM devices, are arranged positioned side by side in a plurality of rows and columns—in a rectangular matrix (regularly divided into a plurality of cell fields) or in a rectangular array (regularly divided into a plurality of cell fields).  
         [0008]     In order to obtain a correspondingly high total storage capacity, and/or to achieve a data read or write rate as high as possible, instead of one single array, there may be provided a plurality of, e.g. four—substantially rectangular—individual arrays in one single RAM device or chip (“multi-bank chip”) (so-called “memory banks”).  
         [0009]     In order to perform a write or read access, a particular, predetermined sequence of instructions must be gone through:  
         [0010]     For instance, by means of a word line activating instruction (activate instruction (ACT)), a corresponding word line—in particular assigned to a particular array—(and defined by the row address) is first of all activated.  
         [0011]     The result thereof is that the data values stored in the memory cells assigned to the corresponding word line are read out by the sense amplifiers assigned to the corresponding word line (“activated state” of the word line).  
         [0012]     Subsequently—by means of an appropriate read or write instruction (Read (RD) or Write (WT) instruction)—it is caused that the corresponding data—then exactly specified by the corresponding column address—are appropriately output by the corresponding sense amplifier(s)—assigned to the bit line specified by the column address—(or—vice versa—the data are read into the corresponding memory cells).  
         [0013]     Next—by means of a word line deactivating instruction (e.g. a precharge instruction (PRE instruction))—the corresponding word line is again deactivated, and the corresponding array is prepared for the next word line activating instruction (activate instruction (ACT)). The above-mentioned sense amplifiers are each arranged in a sense amplifier region positioned between two cell fields, wherein—for reasons of space—one and the same sense amplifier may be assigned to two different cell fields each (namely the two cell fields directly adjacent to the corresponding sense amplifier region) (so-called shared sense amplifiers).  
         [0014]     Depending on whether data are to be read out from the cell field positioned at the left or at the right next to the respective sense amplifier (or the cell field positioned above or below the respective sense amplifier), the corresponding sense amplifier is connected to the corresponding cell field by means of appropriate switches (in particular to the corresponding bit line assigned to the respective cell field) (or is connected electrically with the corresponding cell field, in particular the corresponding bit line assigned to the respective cell field), or is disconnected from the corresponding cell field (or the corresponding bit line assigned to the respective cell field) (or disconnected electrically from the corresponding cell field (or the corresponding bit line assigned to the respective cell field).  
         [0015]     The corresponding switches effecting the connecting or disconnecting, respectively, in particular transistors, are controlled by an appropriate control line (MUX lines, in particular a right MUX line (MUX R  line) and a left MUX line(MUX L  line))—positioned—parallel to the word lines—at the left or at the right next to the cell fields in the above-mentioned sense amplifier regions (and above or below regions adjacent thereto).  
         [0016]     The control signals (MUX R  or MUX L  signal, respectively) applied at the MUX lines are driven by a driver device (MUX driver device) connected with the corresponding MUX line, said driver device being arranged in a region positioned below or above (or at the right or at the left of) all cell fields of the corresponding array, e.g. a segment control region (i.e. an edge region of the array).  
         [0017]     The MUX lines may be relatively long. This results in relatively large signal delays of the control signals (MUX signals) applied at the MUX lines, and to a relatively low switching rate during the connecting and/or disconnecting of the sense amplifiers to or from the corresponding cell field (or the bit line assigned to the corresponding cell field, respectively).  
       SUMMARY OF THE INVENTION  
       [0018]     The invention provides a novel sense amplifier connecting/disconnecting circuit arrangement, and a novel method for operating a sense amplifier connecting/disconnecting circuit arrangement.  
         [0019]     In one embodiment of the invention, there is a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, is provided, including a switching device for connecting a sense amplifier device to a bit line or to a cell field region, respectively, and for disconnecting the sense amplifier device from the bit line or from the cell field region, respectively, as a function of the state of a control signal (MUXL, MUXR) applied at a control line, a driver device for driving the control signal (MUXL, MUXR), where an additional device, in particular an additional switch, is provided, by means of which a change of state of the control signal (MUXL, MUXR) applied at the control line can be effected.  
         [0020]     Advantageously, the additional device, in particular the additional switch, is positioned—in contrast to the driver device—relatively close to the sense amplifier device.  
         [0021]     By the—additional—providing of the switch, the corresponding sense amplifier device can—other than with prior art—be disconnected from the corresponding cell field region (or the corresponding bit line, respectively) relatively quickly. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]     In the following, the invention will be explained in detail with respect to exemplary embodiments and the enclosed drawings. In the drawings:  
         [0023]      FIG. 1  shows a schematic representation of the construction of a semiconductor memory device with a plurality of arrays, and of a memory controller according to a first and a second embodiment of the present invention.  
         [0024]      FIG. 2  shows a schematic detail representation of the construction of a section of one of the arrays of the semiconductor memory device illustrated in  FIG. 1 .  
         [0025]      FIG. 3 a  schematic representation of a shared sense amplifier provided in corresponding sense amplifier regions of the array or array section illustrated in  FIGS. 1 and 2 .  
         [0026]      FIG. 4  shows a circuit arrangement used in accordance with the first embodiment of the invention for the quick disconnecting of the MUX control lines illustrated in  FIG. 3 .  
         [0027]      FIG. 5  shows a schematic detail representation of the MUX control line driver devices illustrated in  FIG. 4  and  FIG. 6 .  
         [0028]      FIG. 6  shows a circuit arrangement used in accordance with the second embodiment of the invention for the quick disconnecting of the MUX control lines illustrated in  FIG. 3 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0029]      FIG. 1  is a schematic representation of the construction of a semiconductor memory device  1  or a semiconductor memory chip, respectively, and of a—central—memory controller  5 .  
         [0030]     The semiconductor memory device  1  may, for instance, be a table memory device based on CMOS technology, e.g. a RAM memory device (RAM=Random Access Memory or write-read memory, respectively), in particular a DRAM memory device (DRAM=Dynamic Random Access Memory or dynamic write-read memory, respectively).  
         [0031]     In the semiconductor memory device  1 —after the input of a corresponding address (e.g. by the memory controller  5 )—data may be stored under the respective address, and may be read out again later under this address.  
         [0032]     The address may be input in several steps, e.g. two successive steps (e.g. first of all a row address—and possibly parts of a column address) (and/or possibly further address parts, or parts thereof)—, and then the column address (or the remaining parts of the column address, respectively, and/or—only now—the above-mentioned further address parts (or the remaining parts thereof, respectively)).  
         [0033]     By applying an appropriate control signal (e.g. a read/write signal)—e.g. by the memory controller  5 —there may be selected whether data are to be stored or to be read out.  
         [0034]     The data input in the semiconductor memory device  1  are, as will be explained in more detail in the following, stored in corresponding memory cells there, and are read out from the corresponding memory cells later again.  
         [0035]     Every memory cell consists e.g. of few elements, in particular only of one single, correspondingly controlled capacitor, with the capacitance of which one bit each can be stored as charge.  
         [0036]     As results from  FIG. 1 , a particular number of memory cells each is arranged—in a plurality of rows and columns side by side—in a rectangular or square array (memory bank)  3   a ,  3   b ,  3   c ,  3   d , so that e.g. every 32 MBit, 64 MBit, 128 MBit, 256 MBit, etc. can be stored in an array  3   a ,  3   b ,  3   c ,  3   d —corresponding to the number of memory cells contained.  
         [0037]     As is further illustrated in  FIG. 1 , the semiconductor memory device  1  comprises a plurality of, e.g. four, memory cell arrays  3   a ,  3   b ,  3   c ,  3   d  (here: the memory banks  0 - 3 ), each being of substantially identical construction and being distributed regularly over the area of the device, and being controlled substantially independently of one another by the above-mentioned memory controller  5 , so that a total storage capacity of e.g. 128 MBit, 256 MBit, 512 MBit, or 1024 MBit (or 1 GBit, respectively) correspondingly results for the semiconductor memory device  1 .  
         [0038]     By providing a plurality of substantially independent arrays  3   a ,  3   b ,  3   c ,  3   d  there can be achieved that corresponding write or read accesses can be performed—in parallel or overlapping in time—with a plurality of different arrays  3   a ,  3   b ,  3   c ,  3   d.    
         [0039]     The above-mentioned address (input in the semiconductor memory device  1  or the memory controller  5 , respectively) comprises—as a part of the above-mentioned further address parts—a corresponding number of (here e.g. two) bits (array selection bits or bank address bits, respectively) serving to address the respectively desired array  3   a ,  3   b ,  3   c ,  3   d  during the storing or reading out of data.  
         [0040]     As will be explained in more detail in the following, the above-mentioned memory cells are arranged in the arrays  3   a ,  3   b ,  3   c ,  3   d  each in corresponding cell fields or cell field regions  7   a ,  7   b ,  7   c ,  7   d  that are positioned vertically one on top of the other or horizontally side by side, respectively (cf. e.g. the cell field regions  7   a ,  7   b ,  7   c ,  7   d  illustrated by way of example in  FIG. 2 , and a plurality of further cell field regions—not illustrated—positioned at the right or at the left, and above or below the cell field regions  7   a ,  7   b ,  7   c ,  7   d  in the representation pursuant to  FIG. 2 ).  
         [0041]     The cell field regions  7   a ,  7   b ,  7   c ,  7   d  each are of substantially identical construction, substantially of rectangular (or e.g. square) design, and each comprise a particular number of memory cells positioned side by side in a plurality of rows and columns.  
         [0042]     Between every two cell fields  7   a ,  7   b ,  7   c ,  7   d  (or—in the representation pursuant to  FIG. 2 —at the left or at the right of a cell field  7   a ,  7   b ,  7   c ,  7   d , respectively) there are positioned—here also substantially rectangular—sense amplifier regions  10   a ,  10   b ,  10   c ,  10   d ,  10   e ,  10   f . In each of the sense amplifier regions  10   a ,  10   b ,  10   c ,  10   d ,  10   e ,  10   f  a plurality of sense amplifiers  11  are arranged, wherein the corresponding sense amplifiers  11  (or more exactly: the sense amplifiers  11  arranged in the sense amplifier regions  10   a ,  10   b ,  10   c ,  10   d ,  10   e ,  10   f  positioned between every two different cell fields  7   a ,  7   b ,  7   c ,  7   d ) each are assigned to two different cell fields  7   a ,  7   b ,  7   c ,  7   d  (namely the cell fields  7   a ,  7   b  directly adjacent to the corresponding sense amplifier region—e.g. the sense amplifier region  10   b —, etc.). In the present embodiments, so-called shared sense amplifiers  11  are thus used.  
         [0043]     As results from  FIG. 1 , each array comprises a—here also substantially rectangular—array controller  6   a ,  6   b ,  6   c ,  6   d  (bank control) separately assigned to the respective array  3   a ,  3   b ,  3   c ,  3   d , the array controller  6   a ,  6   b ,  6   c ,  6   d  being positioned in an edge region of the respective array  3   a ,  3   b ,  3   c ,  3   d.    
         [0044]     In accordance with  FIG. 2 , segment or word line driver regions  8   a ,  8   b ,  8   c ,  8   d —here also of substantially rectangular design—are positioned between every two cell fields  7   a ,  7   b ,  7   c ,  7   d  (or—in the representation pursuant to  FIG. 2 —above or below a cell field  7   a ,  7   b ,  7   c ,  7   d , respectively.).  
         [0045]     In each of the segment driver regions  8   a ,  8   b ,  8   c ,  8   d , a plurality of corresponding segment or word line driver means are arranged.  
         [0046]     As results from  FIG. 1  and  FIG. 2 , at an edge region of the respective array  3   a ,  3   b ,  3   c ,  3   d —here positioned below (or above, respectively)—(or alternatively e.g. at the right (or at the left, respectively)) of the corresponding cell fields  7   a ,  7   c  or  7   b ,  7   d , respectively, there is positioned a segment or word line control region  9   a ,  9   b ,  9   c ,  9   d  in which—as will be explained in more detail below corresponding MUX control line driver device  20   a ,  20   b  are arranged (cf. e.g. also  FIG. 4 ).  
         [0047]     As results from  FIG. 2 , within each cell field region  7   a ,  7   b ,  7   c ,  7   d  there extend (e.g. from the segment driver region  8   a ,  8   b ,  8   c ,  8   d  respectively assigned to the respective cell field region  7   a ,  7   b ,  7   c ,  7   d ) a plurality of word lines  12  (in  FIG. 2 , only one single word line, namely the word line WL, is illustrated for the sake of clarity). The number of word lines  12  provided per cell field region  7   a ,  7   b ,  7   c ,  7   d  may, for instance, correspond to the number of memory cell rows in the respective cell field region  7   a ,  7   b ,  7   c ,  7   d  (or e.g.—for instance in the case of simultaneous reading out/storing of respectively several, e.g. 2, 4, or 8 bits—to a fraction thereof (e.g. half, a quarter, or an eighth)).  
         [0048]     The individual word lines  12  are—equidistantly—arranged in parallel to one another (and extend parallel to the outer edge of the respective cell field region  7   a ,  7   b ,  7   c ,  7   d ).  
         [0049]     As results further from  FIG. 2  and  FIG. 3 , there extend within each cell field region  7   a ,  7   b ,  7   c ,  7   d  (e.g. from the sense amplifier regions  10   a ,  10   b ,  10   c ,  10   d  respectively assigned to the respective cell field region  7   a ,  7   b ,  7   c ,  7   d ) a plurality of bit lines  13   a ,  13   b ,  13   c ,  13   d  (in  FIG. 2  only one single bit line, namely the bit line BL, is illustrated for the sake of clarity, and in  FIG. 3  the bit lines BLLt, BLLc, BLRt und BLRc).  
         [0050]     The number of bit lines  12  provided per cell field region  7   a ,  7   b ,  7   c ,  7   d  may, for instance, correspond to the number of memory cell columns in the respective cell field region  7   a ,  7   b ,  7   c ,  7   d , or e.g. to a multiple thereof.  
         [0051]     The individual bit lines or bit line pairs  13   a ,  13   b  or  13   c ,  13   d , respectively, are—equidistantly—arranged in parallel to one another (and extend parallel to the outer edge of the respective cell field region  7   a ,  7   b ,  7   c ,  7   d , and perpendicular to the above-mentioned word lines  12 ).  
         [0052]     The—central—memory controller  5  may—as is illustrated by way of example in  FIG. 1 —be designed as a separate semiconductor device communicating with the DRAM semiconductor memory device  1  via external pins.  
         [0053]     Alternatively, the memory controller  5  may e.g. also be arranged on one and the same chip  1  as the above-mentioned memory cell arrays  3   a ,  3   b ,  3   c ,  3   d  (memory banks  0 - 3 ).  
         [0054]     In order to perform a write or read access in the semiconductor memory device  1 , a particular, predetermined sequence of instructions must be gone through:  
         [0055]     For instance, by means of a word line activating instruction (activate instruction (ACT)), a corresponding word line  12  or row of memory cells, respectively, assigned to a particular array  3   a ,  3   b ,  3   c ,  3   d  determined by the above-mentioned address (in particular the above-mentioned array selection bits or bank address bits, respectively) (and also defined by the above-mentioned address, in particular the respective row address) is activated.  
         [0056]     This is e.g. effected by that—as is illustrated in  FIG. 1 —a corresponding word line activating instruction signal (ACT signal) is transmitted from the memory controller  5  via a control line  4   a ,  4   b ,  4   c ,  4   d  of a control line data bus  4 —assigned to the respective array  3   a ,  3   b ,  3   c ,  3   d  to be addressed (or the array controllers  6   a ,  6   b ,  6   c ,  6   d  thereof)—(or alternatively e.g. to all arrays  3   a ,  3   b ,  3   c ,  3   d  (or array controllers  6   a ,  6   b ,  6   c ,  6   d ) of the semiconductor memory device  1 ) (and—e.g. simultaneously—the above-mentioned address).  
         [0057]     As has already been explained above, a plurality of sense amplifiers  11  is arranged in each of the sense amplifier regions  10   a ,  10   b ,  10   c ,  10   d ,  10   e ,  10   f  of the respective array  3   a ,  3   b ,  3   c ,  3   d , wherein the corresponding sense amplifiers  11  (or more exactly: the sense amplifiers arranged in the sense amplifier regions  10   b ,  10   c  positioned between two different cell field regions  7   a ,  7   b ,  7   c ,  7   d  positioned side by side) each are assigned to two different cell field regions  7   a ,  7   b ,  7   c ,  7   d  (namely the cell field regions  7   a ,  7   b , etc. directly adjacent to the corresponding sense amplifier region  10   b ).  
         [0058]     Therefore, it must be ensured (e.g. by the memory controller  5 ) that word lines  12  are not activated—in parallel or simultaneously—that are assigned to two different cell field regions  7   a ,  7   b  which are, however, adjacent to one and the same sense amplifier region  10   b , or—in parallel or simultaneously—cell field regions  7   a ,  7   b  adjacent to one and the same sense amplifier region  10   b  (word lines  12  in at most every second cell field region  7   a ,  7   b —positioned side by side at the right or at the left, respectively, in the representation pursuant to  FIG. 2 —, or—alternatively—e.g. only one word line each per array  3   a ,  3   b ,  3   c ,  3   d ).  
         [0059]     In response to the receipt of the above-mentioned word line activating instruction signal (ACT signal), the respective array controller  6   a ,  6   b ,  6   c ,  6   d  provided separately for each array  3   a ,  3   b ,  3   c ,  3   d  and receiving the respective ACT signal, causes the data values stored in the respective row—defined by the respective row address—of memory cells arranged in the corresponding cell field region  7   a ,  7   b ,  7   c ,  7   d  to be read out from the sense amplifiers  11 —assigned to the corresponding word line  12 —of the respective sense amplifier region  10   a ,  10   b ,  10   c ,  10   d ,  10   e ,  10   f  (“activated state” of the word line  12 ).  
         [0060]     This word line  12  is kept in the activated state until an access to a further word line—arranged in the same array  3   a ,  3   b ,  3   c ,  3   d —is to be performed, or—alternatively—until an access to a further word line of a further cell field region  7   a ,  7   b ,  7   c ,  7   d  is to be performed, which is adjacent to one and the same sense amplifier region  10   b , such as the cell field region  7   a ,  7   b ,  7   c ,  7   d  of the—as explained above—activated word line  12  (or to a further word line—differing from the activated word line  12 —in the same cell field region  7   a ,  7   b ,  7   c ,  7   d  as the activated word line  12 ).  
         [0061]     Then—by means of a word line deactivating instruction (e.g. a precharge instruction (PRE instruction)) transmitted via a control line assigned to the respective array  3   a ,  3   b ,  3   c ,  3   d  to be addressed (or the array controller  6   a ,  6   b ,  6   c ,  6   d  thereof) (or alternatively e.g. to arrays  3   a ,  3   b ,  3   c ,  3   d  (or array controllers  6   a ,  6   b ,  6   c ,  6   d ) of the semiconductor memory device  1 )—the corresponding word line  12  deactivated again, and the corresponding array  3   a ,  3   b ,  3   c ,  3   d  is prepared for the next word line activating instruction (activate instruction (ACT)).  
         [0062]     As long as the word line  12  is left in the above-mentioned activated state, the memory controller  5  of the semiconductor memory device  1  will not send a corresponding word line deactivating instruction signal (precharge or PRE instruction signal) characterizing the word line  12  to be deactivated with a corresponding address.  
         [0063]     E.g. one or two clocks after the above-mentioned word line activating signal (ACT signal), the memory controller  5  sends, via a control line assigned to the respective array  3   a ,  3   b ,  3   c ,  3   d  to be addressed (or the array controller  6   a ,  6   b ,  6   c ,  6   d  thereof) (or alternatively e.g. to arrays  3   a ,  3   b ,  3   c ,  3   d  (or array controllers  6   a ,  6   b ,  6   c ,  6   d , respectively) of the semiconductor memory device  1 ) a corresponding read or write instruction signal (Read (RD) or Write (WT) instruction signal).  
         [0064]     In response to the receipt of the above-mentioned read or write instruction signal (Read (RD) or Write (WT) instruction signal), the respective array controller  6   a ,  6   b ,  6   c ,  6   d  provided separately for each array  3   a ,  3   b ,  3   c ,  3   d  and receiving the respective RD (or WT) instruction signal, causes the corresponding data—then exactly specified by the corresponding column address—to be correspondingly output by the corresponding sense amplifier(s)  11  assigned to the bit line BL or the bit line pair BLLt, BLLc or BLRt, BLRc, respectively, specified by the column address (or—vice versa—the data to be read into the corresponding memory cells).  
         [0065]     As already explained above, the sense amplifiers  11  each are arranged in a sense amplifier region  10  positioned between two cell field regions  7   a ,  7   b , wherein—for reasons of space—one and the same sense amplifier  11  is assigned to two different cell field regions  7   a ,  7   b  each (namely the two cell field regions  7   a ,  7   b  directly adjacent to the corresponding sense amplifier region  10   b ) (so-called shared sense amplifiers).  
         [0066]     Depending on whether—in the representation pursuant to  FIG. 2  and  FIG. 3 —data are to be read out from the cell field region  7   a ,  7   b  positioned at the right or at the left next to the respective sense amplifier  11 , the corresponding sense amplifier  11  is connected by means of corresponding switches  14   a ,  14   b ,  14   c ,  14   d  (here: corresponding transistors  14   a ,  14   b ,  14   c ,  14   d  positioned in the same sense amplifier region  10   b  as the respectively assigned sense amplifier  11 ) to the corresponding cell field region  7   a  or  7   b  (in particular to the corresponding bit line (BL) or bit line pair  13   a ,  13   b  or  13   c ,  13   d  (BLLt, BLLc or BLRt, BLRc) assigned to the respective cell field region  7   a  or  7   b ) (or is—by switching on the corresponding switches or transistors  14   a ,  14   b  or  14   c ,  14   d —electrically connected with the corresponding cell field region  7   a  or  7   b , in particular the corresponding bit line (BL) or bit line pair  13   a ,  13   b  or  13   c ,  13   d  (BLLt, BLLc or BLRt, BLRc) positioned in the respective cell field region  7   a  or  7   b ), or is disconnected from the corresponding cell field region  7   a  or  7   b  (or the corresponding bit line (BL) or bit line pair  13   a ,  13   b  or  13   c ,  13   d  (BLLt, BLLc or BLRt, BLRc) assigned to the respective cell field region  7   a  or  7   b ) (or is—by switching off the corresponding switches or transistors  14   a ,  14   b  or  14   c ,  14   d —electrically disconnected from the corresponding cell field region  7   a  or  7   b  (or the corresponding bit line (BL) or bit line pair  13   a ,  13   b  or  13   c ,  13   d  (BLLt, BLLc or BLRt, BLRc) positioned in the respective cell field region  7   a  or  7   b ).  
         [0067]     To this end, according to  FIG. 3 , the transistors  14   a ,  14   b  are switched on in parallel or simultaneously (and the transistors  14   c ,  14   d  are switched off), or the transistors  14   c ,  14   d  are switched on in parallel or simultaneously (and the transistors  14   a ,  14   b  are switched off).  
         [0068]     The corresponding switches, in particular transistors  14   a ,  14   b  or  14   c ,  14   d  (which are correspondingly switched on or off, as explained above), effecting the connecting or disconnecting of the cell field regions  7   a  or  7   b  or of the bit line/the bit line pair  13   a ,  13   b  or  13   c ,  13   d , respectively, to or from the corresponding sense amplifier  11 , are controlled by a corresponding control line  15 ,  16 .  
         [0069]     Whenever a “logically high” signal (i.e. a “logically high” MUXL signal for the transistors  14   a ,  14   b —positioned at the left of the sense amplifier  11  in the representation of  FIG. 3 —, or a “logically high” MUXR signal for the transistors  14   c ,  14   d —positioned at the right of the sense amplifier  11  in the representation of  FIG. 3 —) is applied at the control line  15  or  16 , respectively that is connected with a corresponding control input of the transistors  14   a ,  14   b  or  14   c ,  14   d , respectively, the corresponding transistors  14   a ,  14   b  or  14   c ,  14   d , respectively, are switched on (i.e. the sense amplifier  11  is electrically connected with the bit line pair  13   a ,  13   b  or  13   c ,  13   d , respectively, and, as will be explained in more detail below, with a corresponding equalizer or a corresponding equalizer device  17  or  18 , respectively).  
         [0070]     Correspondingly vice versa, whenever a “logically low” signal (i.e. a “logically low” MUXL signal for the transistors  14   a ,  14   b —positioned at the left of the sense amplifier  11  in the representation of  FIG. 3 —, or a “logically low” MUXR signal for the transistors  14   c ,  14   d —positioned at the right of the sense amplifier  11  in the representation of  FIG. 3 —) is applied at the corresponding control line  15  or  16 , respectively, the corresponding transistors  14   a ,  14   b  or  14   c ,  14   d , respectively, are switched off (i.e. the sense amplifier  11  is electrically disconnected from the bit line pair  13   a ,  13   b  or  13   c ,  13   d , respectively, and, as will be explained in more detail below, from the corresponding equalizer or a corresponding equalizer device  17  or  18 , respectively).  
         [0071]     The—in the representation of  FIG. 3 —control lines  15  of the sense amplifiers  11  of one and the same sense amplifier region  10   b , positioned “at the left” of the corresponding sense amplifiers  11  (as well as—alternatively—additionally the corresponding “left” control lines of the sense amplifiers of the sense amplifier regions  10   e  positioned, in the representation of  FIG. 2 , above or below the corresponding sense amplifier region  10   b , respectively) are, pursuant to  FIG. 4 , connected to a—central—control line  21  (MUXL line  21 ), and the—in the representation of  FIG. 3 —control lines  16  of all the sense amplifiers  11  of the corresponding sense amplifier region  10   b , positioned “at the right” of the corresponding sense amplifiers  11  (as well as—alternatively—additionally the corresponding “right” control lines of the sense amplifiers of the sense amplifier regions  10   e  positioned, in the representation of  FIG. 2 , above or below the corresponding sense amplifier region  10   b , respectively) to a further—central—control line  22  (MUXR line  22 ).  
         [0072]     The MUXL line  21  extends—parallel to the word lines  12 , and positioned at the left of the corresponding sense amplifiers  11  in the representation of  FIG. 3 —over the entire length of the sense amplifier region  10   b  assigned to the respective sense amplifiers  11  (and—therebeyond—(in the representations of  FIG. 2  and  FIG. 4 ) downwards in the direction of the segment or word line control region  9   a ,  9   b ,  9   c ,  9   d  in which—as has already been explained above—corresponding MUX control line driver devices  20   a ,  20   b  are arranged, and extends—alternatively—passing through further sense amplifier regions  10   e  positioned above the sense amplifier region  10   b —in addition also upwards (i.e. over the entire length of corresponding—not illustrated—master word lines (MWL))).  
         [0073]     Correspondingly, the MUXR line  22  extends—parallel to the word lines  12 , and positioned at the right of the corresponding sense amplifiers  11  in the representation of  FIG. 3 —over the entire length of the sense amplifier region  10   b  assigned to the respective sense amplifiers  11  (and—therebeyond—(in the representations of  FIG. 2  and  FIG. 4 ) downwards in the direction of the segment or word line control region  9   a ,  9   b ,  9   c ,  9   d , in which—as has already been explained above—corresponding MUX control line driver devices  20   a ,  20   b  are arranged, and extends—alternatively—passing through further sense amplifier regions  10   e  positioned above the sense amplifier region  10   b —in addition also upwards (i.e. over the entire length of corresponding—not illustrated—master word lines (MWL))).  
         [0074]     The MUXL line  21  is connected to the (central) MUX control line driver device  20   a , and the MUXR line  22  is connected to the (central) MUX control line driver device  20   b.    
         [0075]     As is illustrated in  FIG. 5 , each MUX control line driver device  20   a ,  20   b  comprises three transistors  24   a ,  24   b ,  24   c  adapted to be controlled separately by means of corresponding signals at corresponding transistor control lines  23   a ,  23   b ,  23   c  (namely an n-channel MOSFET  24   c , and—connected in series thereto—two p-channel MOSFETS  24   a ,  24   b  connected in parallel).  
         [0076]     The n-channel MOSFET  24   c  is connected with the mass potential via a line  25   a , and—via a line  25   b —with the corresponding MUXL or MUXR line  21  or  22 , and—via lines  25   c  or  25   d , respectively,—with the p-channel MOSFET  24   a  and the p-channel MOSFET  24   b.    
         [0077]     The p-channel MOSFET  24   b  is connected via a line  25   e  to a (first) supply voltage—having a first voltage level—, and the p-channel MOSFET  24   a  is connected via a line  25   f  to a (second) supply voltage—having a second voltage level differing from the first voltage level.  
         [0078]     If—by means of a corresponding signal applied at the transistor control line  23   c —the n-channel MOSFET  24   c  is placed in a conductive state, and—by means of corresponding signals applied at the transistor control lines  23   a ,  23   b —the p-channel MOSFETs  24   a ,  24   b  are placed in a locked state, a “logically low” MUXL or MUXR signal, respectively, is output at the corresponding MUXL or MUXR line  21  or  22  (and thus also at the control lines  15  or  16  connected thereto and shown in  FIG. 3 ).  
         [0079]     Accordingly, if—by means of a corresponding signal applied at the transistor control line  23   c —the n-channel MOSFET  24   c  is placed in a locked state, and—by means of corresponding signals applied at the transistor control lines  23   a ,  23   b —the p-channel MOSFET  24   b  is placed in a conductive state and the p-channel MOSFET  24   a  is placed in a locked state, a “logically high” MUXL or MUXR signal, respectively, having the above-mentioned first voltage level, is output at the corresponding MUXL or MUXR line  21  or  22  (and thus also at the control lines  15  or  16  connected thereto and shown in  FIG. 3 ).  
         [0080]     Correspondingly, if—by means of a corresponding signal applied at the transistor control line  23   c —the n-channel MOSFET  24   c  is placed in a locked state, and—by means of corresponding signals applied at the transistor control lines  23   a ,  23   b —the p-channel MOSFET  24   a  is placed in a conductive state and the p-channel MOSFET  24   b  is placed in a locked state, a “logically high” MUXL or MUXR signal, respectively, having the second voltage level differing from the first voltage level, is output at the corresponding MUXL or MUXR line  21  or  22  (and thus also at the control lines  15  or  16  connected thereto and shown in  FIG. 3 ).  
         [0081]     In order to be able to quickly place the MUXL or MUXR signal, respectively, from a “logically high” to a “logically low” state, there are, as is e.g. illustrated in  FIG. 4 ,—except from the central n-channel MOSFET  24   c  that will then have to be placed in a conductive state and that is provided in the MUX control line driver device  20   a  or  20   b , respectively—provided one or more additional switches each positioned locally adjacent to the respective sense amplifiers  11  or the corresponding sense amplifier regions  10   b ,  10   e , respectively, in particular transistors  26 ,  27  (here: corresponding n-channel MOSFETS  26 ,  27 ).  
         [0082]     The transistors  26 ,  27  may—as is illustrated in  FIG. 2 —e.g. be arranged in an intersection region  28  between the respective sense amplifier region  10   b —assigned to the respective sense amplifiers  11 —and the segment driver regions  8   a ,  8   b  assigned thereto—i.e. below the corresponding sense amplifiers  11  e.g. illustrated in  FIG. 3 —(or alternatively e.g. in a further intersection region  29 , etc.—positioned in the representation of  FIG. 2  above the corresponding sense amplifier region  10   b —, or—with a further alternative—e.g. within the corresponding sense amplifier region  10   b , etc.).  
         [0083]     For each MUXL or MUXR line  21 ,  22 , respectively, there may—as is illustrated in  FIG. 4 —be provided one single, local transistor  26  or  27 , respectively, or—alternatively—a plurality of transistors—connected correspondingly similar to the transistors  26  or  27 , respectively, illustrated in  FIG. 4 —(said transistors each being e.g. positioned in one single intersection region  28  (or sense amplifier region  10   b ), or—preferably—being distributed in a plurality of (preferably all) intersection regions  28 ,  29  (or sense amplifier regions  10   b ,  10   c ) passed through by the lines  21 ,  22 , wherein in each intersection region  28 ,  29  (or sense amplifier region  10   b ,  10   c )—for each of the lines  21 ,  22 —e.g. one single transistor, or several transistors—connected correspondingly similar to the transistors  26 ,  27  illustrated in  FIG. 4 —may be provided.  
         [0084]     As results from  FIG. 4 , the transistor  26 —which is adapted to draw the MUXL line  21  locally downwards or to a logically low state, respectively—(and possibly the above-mentioned further, additional transistors which are adapted to—additionally—draw the MUXL line  21  locally downwards or to a logically low state, respectively) is, by means of a line  30   a  (or the possibly provided, additional transistors are, by means of corresponding, further lines) connected to the MUXL line  21 , and—by means of a line  30   b  (or the possibly provided, additional transistors by means of corresponding, further lines)—to the mass potential.  
         [0085]     Correspondingly similar, the transistor  27 —which is adapted to draw the MUXR line  22  locally downwards or to a logically low state, respectively—(and possibly the above-mentioned further, additional transistors which are adapted to—additionally—draw the MUXR line  22  downwards or to a logically low state, respectively) is, by means of a line  31   a  (or the possibly provided, additional transistors are, by means of corresponding, further lines) connected to the MUXR line  22 , and—by means of a line  31   b  (or the possibly provided, additional transistors by means of corresponding, further lines)—to the mass potential. The transistors  26 ,  27  (and the possibly provided, further transistors) are adapted to draw the MUXL or MUXR line  21 ,  22 , respectively,—together with the corresponding MUX control line driver devices  20   a ,  20   b  (or, alternatively, independently thereof)—locally downwards or to a logically low state, respectively, by the fact that the corresponding transistors  26 ,  27  are placed in a conductive state, i.e. are switched on.  
         [0086]     To this end, a logically high control signal is applied to a control line input—connected with a corresponding transistor control line  30   c  or  31   c , respectively—of the corresponding transistor  26  or  27 , respectively.  
         [0087]     This renders it possible to quickly draw the MUXL or the MUXR signal, respectively, downwards or to a logically low state, respectively, without complete intermediate amplifiers having to be provided in the respective intersection regions  28  (or sense amplifier regions  10   b ) (the intermediate amplifiers having—other than the transistors  26 ,  27 —to be connected, except with the mass potential, additionally, e.g. via one or a plurality of further transistors, with the above-mentioned first supply voltage having the first voltage level (and possibly additionally with the above-mentioned second supply voltage having the above-mentioned second, differing voltage level).  
         [0088]     Advantageously, the same signals can be used as control signals for the transistors  26 ,  27  as are used for controlling the above-mentioned equalizer devices  17 ,  18  illustrated in  FIG. 3 .  
         [0089]     In particular—for controlling the transistors  27  drawing the MUXR line  22 ,  16  downwards or to a logically low state, respectively—an EQLL signal can be used that is applied at a control line  32 —positioned at the left of the corresponding sense amplifiers  11 —and is used to control the equalizer devices  17  positioned at the left of the corresponding sense amplifiers  11  and opposite to the MUXR line  16 ,  22  that is, in the representation of  FIGS. 3 and 4 , positioned at the right of the corresponding sense amplifiers  11 .  
         [0090]     Correspondingly—for controlling the transistor  26  drawing the MUXL line  21 ,  15  downwards or to a logically low state, respectively—an EQLR signal can be used that is applied at a control line  33 —positioned at the right of the corresponding sense amplifiers  11 —and is used to control the equalizer devices  18  positioned at the right of the corresponding sense amplifiers  11  and opposite to the MUXL line  15 ,  21  that is, in the representation of  FIGS. 3 and 4 , positioned at the left of the corresponding sense amplifiers  11 .  
         [0091]     By means of the equalizer devices  17 ,  18 —correspondingly similar as with conventional equalizer devices  17 ,  18 —depending on the state of the EQLL or EQLR signal applied at the control lines  32  or  33 , respectively—either i) the sense amplifier  11  assigned to the respective equalizer device  17 ,  18  is kept in a “precharge state” (wherein the corresponding cell field region  7   a ,  7   b  cannot be activated), or ii) the sense amplifier  11  assigned to the respective equalizer device  17 ,  18  is released again from the “precharge state” (so that the corresponding cell field region  7   a ,  7   b  may then be activated).  
         [0092]     Instead of with the above-mentioned EQLL or EQLR signals, respectively, applied at the control lines  32  or  33 , respectively, in the case of a second, alternative embodiment illustrated in  FIG. 6 , transistors  26   a ,  27   a ,  26   b ,  27   b ,  26   c ,  27   c —corresponding to the transistors  26 ,  27  illustrated in  FIG. 4 —may also be controlled by a control signal CON or /CON, respectively, the signal being generated separately or individually for controlling the transistors  26   a ,  27   a ,  26   b ,  27   b ,  26   c ,  27   c , being inverted by an inverter  34 , and being supplied to the control connections of the transistors  26   a ,  27   a ,  26   b ,  27   b ,  26   c ,  27   c  via transistor control lines  35  corresponding to the transistor control lines  30   c ,  31   c.    
         [0093]     In this embodiment, the local driver is provided at the beginning of the master word line (MWL)—as is indicated in  FIG. 6 —with an (additional) switch (—here: the transistor  26   a ,  27   a —) (which is adapted to very quickly draw the MUXL or MUXR line  21 ,  22 , respectively—driven centrally by the MUX control line driver device  20   a ,  20   b —downwards at the beginning of the master word line (MWL)). Furthermore, further switches (—here: the transistors  26   b ,  27   b ,  26   c ,  27   c , etc.—) are—additionally—provided—corresponding to the above-mentioned first embodiment—in the intersection regions  28  between corresponding segment driver regions  8   a ,  8   b  and corresponding sense amplifier regions  10   b , this rendering it possible that—also along the master word line (MWL)—the MUXL or MUXR line  21 ,  22  can be drawn downwards quickly.