Abstract:
A semiconductor integrated circuit device includes first to k-th decoders, and a MOS transistor switch group having a hierarchical structure of first to k-th hierarchies and operated on a second voltage level. An n-bit input signal of a first voltage level is divided into k groups (k is an integral number equal to or larger than 2) and input to the first to k-th decoders. The first to k-th decoders decode the input signal, shift the decode results to the second voltage level higher than the first voltage level and output the same. The MOS transistor switch group is supplied with 2 n  analog inputs at the first hierarchy, selects one of the 2 n  analog inputs and outputs the selected analog input from the k-th hierarchy.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-053607, filed Feb. 28, 2006, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     This invention relates to a decoder circuit having a level shifting function and a liquid crystal drive device using the decoder circuit.  
         [0004]     2. Description of the Related Art  
         [0005]     In a liquid crystal drive device such as a source driver LSI which drives a liquid crystal display device of an active matrix system such as a thin-film transistor (TFT) system, a digital-to-analog conversion process of converting n-bit digital input data into gradation display voltage of 2 n  gradations is performed to display gradations in the liquid crystal display device.  
         [0006]     In the digital-to-analog conversion circuit, a switch group using MOS transistors as analog switches is used. Generally, as the MOS transistors of the switch group, high-withstand voltage MOS transistors are used. Since digital input data is set at low voltage, a level shifter which converts the level of the digital input data from low voltage to high voltage is provided in the preceding stage of the digital-to-analog conversion circuit in the general source driver LSI (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 2002-196726).  
         [0007]     Further, it is proposed to realize the digital-to-analog conversion circuit by use of a decoder circuit (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. H06-303141). In the decoder circuit, switch groups of MOS transistors are arranged in a matrix form and the on/off states of the MOS transistors are controlled according to digital input data. Thus, the combination of the on/off states of the MOS transistors is switched according to digital input data and desired gradation display voltage is selected.  
         [0008]     That is, in the conventional source driver LSI, n-bit digital input data is level-shifted by a level shifter and then input to a decoder circuit configured by the switch groups of MOS transistors arranged in the matrix form and an output selected by the decoder circuit is supplied to the liquid crystal display device as 2 n  gradation voltage.  
         [0009]     However, in order to cope with the tendency of the recent liquid crystal display device to have multiple bits and multiple outputs, an extremely large number of transistors are required in the source driver LSI using the above level shifter and decoder circuit. For example, when input data is n-bit data, (n×2 n ) MOS transistors are required for each output only in the switch group of MOS transistors configuring the decoder circuit. Therefore, there may occur a problem that the chip size of the source driver LSI is increased and the manufacturing yield is lowered accordingly.  
       BRIEF SUMMARY OF THE INVENTION  
       [0010]     According to one aspect of this invention, there is provided a semiconductor integrated circuit including first to k-th decoders (k is an integral number not smaller than 2) to which an n-bit input signal of a first voltage level divided into k groups is input and which decode the input signal, shift decode results to a second voltage level higher than the first voltage level and output the same, and a MOS transistor switch group having a hierarchical structure of first to k-th hierarchies corresponding to the first to k-th decoders and controlled based on the decode results output from the first to k-th decoders corresponding to the first to k-th hierarchies, the MOS transistor switch group being configured to be operated on the second voltage level and supplied with 2 n  analog inputs at the first hierarchy, select one of the 2 n  analog inputs and output the selected analog input from the k-th hierarchy.  
         [0011]     Further, according to another aspect of this invention, there is provided a liquid crystal drive device including a reference voltage generation circuit which generates gradation display reference voltages of 2 n  gradations, first to k-th decoders (k is an integral number not smaller than 2) to which n-bit image data of a first voltage level divided into k groups is input and which decode the image data, shift decode results to a second voltage level higher than the first voltage level and output the same, a MOS transistor switch group having a hierarchical structure of first to k-th hierarchies corresponding to the first to k-th decoders and controlled based on the decode results output from the first to k-th decoders corresponding to the first to k-th hierarchies, the MOS transistor switch group being configured to be operated on the second voltage level and supplied with 2 n  gradation display reference voltages generated by the reference voltage generation circuit at the first hierarchy, select one of the 2 n  gradation display reference voltages and output the selected gradation display reference voltage from the k-th hierarchy, and a liquid crystal display which is supplied with the gradation display voltages and whose gradation is controlled according to the gradation display voltages.  
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING  
       [0012]      FIG. 1  is a block diagram schematically showing an example of the configuration of a decoder circuit according to a first embodiment of this invention and a liquid crystal drive device using the decoder circuit,  
         [0013]      FIG. 2  is a circuit diagram showing an example in which each of switch groups of the decoder circuit shown in  FIG. 1  is configured by PMOS transistors,  
         [0014]      FIG. 3  is a circuit diagram showing an example of the configuration of each of level-shifting decoders which controls the PMOS transistor switch group shown in  FIG. 2 ,  
         [0015]      FIG. 4  is a waveform diagram showing an example of the operation of the level-shifting decoder shown in  FIG. 3 ,  
         [0016]      FIG. 5  is a diagram showing a truth table of the level-shifting decoder shown in  FIG. 3 ,  
         [0017]      FIG. 6  is a circuit diagram showing an example in which each of switch groups of the decoder circuit shown in  FIG. 1  is configured by NMOS transistors,  
         [0018]      FIG. 7  is a circuit diagram showing an example of the configuration of each of level-shifting decoders which controls the NMOS transistor switch group shown in  FIG. 6 ,  
         [0019]      FIG. 8  is a waveform diagram showing an example of the operation of the level-shifting decoder shown in  FIG. 7 ,  
         [0020]      FIG. 9  is a diagram showing a truth table of the level-shifting decoder shown in  FIG. 7 ,  
         [0021]      FIG. 10  is a block diagram schematically showing an example of the configuration of a decoder circuit according to a second embodiment of this invention and a liquid crystal drive device using the decoder circuit,  
         [0022]      FIG. 11  is a circuit diagram showing an example in which each of switch groups of the decoder circuit shown in  FIG. 10  is configured by PMOS transistors,  
         [0023]      FIG. 12  is a circuit diagram showing an example of the configuration of each of level-shifting decoders which controls the PMOS transistor switch group shown in  FIG. 11 , and  
         [0024]      FIG. 13  is a diagram showing a truth table of the level-shifting decoder shown in  FIG. 12 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
     First Embodiment  
       [0025]      FIG. 1  is a block diagram schematically showing an example of the configuration of a decoder circuit according to a first embodiment of this invention and a liquid crystal drive device using the decoder circuit.  
         [0026]     A liquid crystal drive device  1000  of the first embodiment is a source driver LSI which supplies reference voltage selected by a decoder circuit  1  to an active matrix liquid crystal display device (liquid crystal display)  200  as gradation display voltage. The decoder circuit  1  is supplied with image data fetched into an image memory  300  as 6-bit input signals D 0  to D 5 . The decoder circuit  1  decodes the 6-bit input signals D 0  to D 5  and selects one of reference voltages V 1  to V 64  of 64 steps for 2 6  (=64) gradation display generated from a reference voltage generation circuit  100 . The voltage selected by the decoder circuit  1  is supplied to the liquid crystal display  200  as gradation display voltage.  
         [0027]     The decoder circuit  1  of the first embodiment includes three level-shifting decoders (LSDA)  21 A to  23 A and a MOS transistor switch group  3 A whose switching operation is controlled by output signals of the level-shifting decoders  21 A to  23 A. The MOS transistor switch group  3 A is formed of high-withstand voltage MOS transistors and has a hierarchical structure of three hierarchies (k=3).  
         [0028]     The level-shifting decoders  21 A to  23 A are supplied with 6-bit (n=6) input signals D 0  to D 5  which are divided into three (k=3) bit groups (the number of bits allocated to each bit group can be selectively set, but two bits are allocated to each of the three groups in this example) from the image memory  300 . The signal levels of the input signals D 0  to D 5  are set at a low-voltage level of 3.3V, for example. Each of the level-shifting decoders  21 A to  23 A decodes 2-bit input signals I 0 , I 1  of a corresponding bit group and outputs four decoded output signals S 1  to S 4 . The signal levels of the decoded output signals S 1  to S 4  are set at a high-voltage level of 10V, for example. The decoded output signals S 1  to S 4  are respectively supplied to MOS transistor switch groups of the hierarchies (first hierarchy to third hierarchy) corresponding to the level-shifting decoders  21 A to  23 A of the MOS transistor switch group  3 A.  
         [0029]     The first hierarchical MOS transistor switch group is configured by 64 MOS transistors which select 16 voltages from 64 reference voltages V 1  to V 64  input from the reference voltage generation circuit  100 . The second hierarchical MOS transistor switch group is configured by 16 MOS transistors which select four voltages from 16 output voltages of the first hierarchical MOS transistor switch group. The third hierarchical MOS transistor switch group is configured by four MOS transistors which select one voltage from four output voltages of the second hierarchical MOS transistor switch group. The output voltage of the third hierarchical MOS transistor switch group is used as gradation display voltage supplied to the liquid crystal display  200 .  
         [0030]     The above MOS transistor switch group of each hierarchy is configured by using a 4-transistor switch group (SWA) formed of four MOS transistors as one unit. The 64-MOS transistor switch group of the first hierarchy is configured by 4-transistor switch groups A 101  to A 116 . The 16-MOS transistor switch group of the second hierarchy is configured by 4-transistor switch groups A 201  to A 204 . The 4-MOS transistor switch group of the third hierarchy is configured by a 4-transistor switch group A 301 .  
         [0031]     The switching operations of the MOS transistor switch groups of the respective hierarchies are controlled by the decoded output signals S 1  to S 4  of the respective level-shifting decoders  21 A,  22 A and  23 A. That is, the 4-transistor switch groups A 101  to A 116  of the first hierarchy are commonly controlled by the decoded output signals S 1  to S 4  of the level-shifting decoder  21 A. The 4-transistor switch groups A 201  to A 204  of the second hierarchy are commonly controlled by the decoded output signals S 1  to S 4  of the level-shifting decoder  22 A. The 4-transistor switch group A 301  of the third hierarchy is controlled by the decoded output signals S 1  to S 4  of the level-shifting decoder  23 A.  
         [0032]     As described above, in the decoder circuit according to the first embodiment, first, input signals D 0  to D 5  input from the image memory  300  to the decoder circuit  1  are divided into three bit groups and supplied to the level-shifting decoders  21 A to  23 A and the input signals D 0  to D 5  of the respective bit groups are level-shifted and decoded. Then, the switching operation of the MOS transistor switch group  3 A is controlled by the output signals S 1  to S 4  of the level-shifting decoders  21 A to  23 A and one of the 64 reference voltages V 1  to V 64  input from the reference voltage generation circuit  100  is selected and supplied to the liquid crystal display  200  as gradation display voltage. At this time, 16 voltages among 16 groups each including four voltages are selected from the reference voltages V 1  to V 64  at the first hierarchy, four voltages are selected from four groups each including four voltages at the second hierarchy and one voltage is selected from four groups at the third hierarchy.  
         [0033]      FIG. 2  is a circuit diagram showing an example in which the 4-transistor switch group (SWA) in the circuit shown in  FIG. 1  is configured by high-withstand voltage PMOS transistors.  
         [0034]     The source electrodes of PMOS transistors PT 01 , PT 02 , PT 03 , PT 04  are connected to input terminals A 1 , A 2 , A 3 , A 4  and the drain electrodes thereof are commonly connected to an output terminal OT. Further, the decoded output signals S 1 , S 2 , S 3 , S 4  of each of the level-shifting decoders  21 A t  23 A are supplied to the gate electrodes of the PMOS transistors PT 01 , PT 02 , PT 03 , PT 04 .  
         [0035]     The signals S 1 , S 2 , S 3 , S 4  are controlled and only one of them is set to low level. Thus, only one of the PMOS transistors PT 01 , PT 02 , PT 03 , PT 04  is turned on and input voltage applied to one of the input terminals of the input terminals A 1 , A 2 , A 3 , A 4  which is connected to the source electrode of the PMOS transistor set in the on state is output to the output terminal OT.  
         [0036]     That is, one of the input voltages input to the input terminals A 1 , A 2 , A 3 , A 4  is selected according to the signals S 1 , S 2 , S 3 , S 4  and output to the output terminal OT.  
         [0037]      FIG. 3  is a circuit diagram showing an example of the configuration of the level-shifting decoder (LSDA) in the circuit shown in  FIG. 1 . The level-shifting decoder generates and supplies signals S 1 , S 2 , S 3 , S 4  which control the 4-transistor switch group SWA configured by the PMOS transistors shown in  FIG. 2 .  
         [0038]     The source electrodes of high-withstand voltage PMOS transistors PT 11 , PT 12 , PT 13 , PT 14  are connected to a high-withstand voltage power supply terminal VDDH and the signals S 1 , S 2 , S 3 , S 4  are output from the respective drain electrodes thereof. A precharge signal pre is commonly input to the gate electrodes of the PMOS transistors PT 11 , PT 12 , PT 13 , PT 14 .  
         [0039]     The current paths of high-withstand voltage NMOS transistors NT 111 , NT 112  and NMOS transistor NT 11  are serially connected between the drain electrode of the PMOS transistor PT 11  and a ground terminal. The current paths of high-withstand voltage NMOS transistors NT 121 , NT 122  and NMOS transistor NT 12  are serially connected between the drain electrode of the PMOS transistor PT 12  and the ground terminal. The current paths of high-withstand voltage NMOS transistors NT 131 , NT 132  and NMOS transistor NT 13  are serially connected between the drain electrode of the PMOS transistor PT 13  and the ground terminal. The current paths of high-withstand voltage NMOS transistors NT 141 , NT 142  and NMOS transistor NT 14  are serially connected between the drain electrode of the PMOS transistor PT 14  and the ground terminal.  
         [0040]     A precharge signal pre is commonly input to the gate electrodes of the NMOS transistors NT 11 , NT 12 , NT 13 , NT 14 . Further, an input signal I 0  is input to the gate electrodes of the NMOS transistors NT 122 , NT 142  and an input signal I 1  is input to the gate electrodes of the NMOS transistors NT 131 , NT 141 . Also, a signal obtained by inverting the input signal I 0  by an inverter IV 11  is input to the gate electrodes of the NMOS transistors NT 112 , NT 132  and a signal obtained by inverting the input signal I 1  by an inverter IV 12  is input to the gate electrodes of the NMOS transistors NT 111 , NT 121 .  
         [0041]     In this case, the signal levels of the input signals I 0 , I 1  are set at the low-voltage level and the inverters IV 11 , IV 12  are inverters operated on low voltage. Therefore, the signal levels of outputs of the inverters IV 11 , IV 12  are also set at the low-voltage level. When the threshold voltage Vth is set at 1V, for example, it is possible to identify and drive the high-withstand voltage NMOS transistor even if the input voltage level is set at the low-voltage level, for example, the binary 0 level is set at 0V and the binary 1 level is set at 3.3V.  
         [0042]      FIG. 4  is a waveform diagram showing an example of the operation of the level-shifting decoder LSDA shown in  FIG. 3 .  
         [0043]     A precharge period is set when the precharge signal pre is binary 0 and, at this time, all of the PMOS transistors PT 11 , PT 12 , PT 13 , PT 14  are turned on and all of the NMOS transistors NT 11 , NT 12 , NT 13 , NT 14  are turned off. As a result, the signal levels of all of the output signals S 1 , S 2 , S 3 , S 4  are high indicating the high-voltage level.  
         [0044]     When the precharge signal pre is binary 1, all of the PMOS transistors PT 11 , PT 12 , PT 13 , PT 14  are turned off and all of the NMOS transistors NT 11 , NT 12 , NT 13 , NT 14  are turned on. Thus, a decode output period in which the decode results of the input signals I 0 , I 1  are output is set. In this period, since all of the PMOS transistors PT 11 , PT 12 , PT 13 , PT 14  are off, only the output signal of the terminal of those of the NMOS transistors serially connected to the source terminals of the NMOS transistors NT 11 , NT 12 , NT 13 , NT 14  in the on state which are both turned on is made low. Each of the other output terminals is set in the high-impedance state and keeps the output high in the precharge period since the PMOS transistor and at least one of the NMOS transistors whose current paths are serially connected thereto are turned off.  
         [0045]     In the waveform diagram of  FIG. 4 , an example in which the input signals I 0 , I 1  are both binary 0 in the decode output period is shown.  
         [0046]     In the decode output period, since the input signals I 0 , I 1  are both binary 0, only the output signal S 1  of the terminal of the NMOS transistors NT 111 , NT 112  whose current paths are serially connected to the source terminal of the NMOS transistor NT 11  and which are both on is made low. Each of the other output signals S 2 , S 3 , S 4  is kept high since at least one of the NMOS transistors serially connected to the output terminal is turned off.  
         [0047]      FIG. 5  is a diagram showing a truth table indicating the relation between the input signal and output signal during the decode output period of the level-shifting decoder (LSDA) shown in  FIG. 3 .  
         [0048]     As shown in  FIG. 5 , one of the output signals S 1 , S 2 , S 3 , S 4  which is made low is output according to a combination of the signal levels of the input signals I 0 , I 1 . Then, one of the PMOS transistors in the 4-transistor switch group SWA can be turned on by controlling the 4-transistor switch group SWA configured by the PMOS transistors shown in  FIG. 2  by use of the output signals S 1 , S 2 , S 3 , S 4  in the decode output period.  
         [0049]     An example in which the 4-transistor switch group SWA is configured by the PMOS transistors is explained above, but the 4-transistor switch group SWA can be configured by use of high-withstand voltage NMOS transistors.  
         [0050]      FIG. 6  is a circuit diagram showing an example in which the 4-transistor switch group SWA is configured by high-withstand voltage NMOS transistors. The circuit configuration itself is attained by replacing the PMOS transistors PT 01 , PT 02 , PT 03 , PT 04  of the 4-transistor switch group SWA configured by the PMOS transistors shown in  FIG. 2  by NMOS transistors NT 01 , NT 02 , NT 03 , NT 04 .  
         [0051]     In this case, since the NMOS transistor is turned on when the a signal supplied to the gate electrode thereof is high, the polarities of the signals S 1 , S 2 , S 3 , S 4  must be inverted with respect to those set when the 4-transistor switch group SWA is configured by the PMOS transistors. That is, a high signal is supplied only to the gate electrode of one of the NMOS transistors NT 01 , NT 02 , NT 03 , NT 04  which is desired to be turned on.  
         [0052]      FIG. 7  is a circuit diagram showing an example of the configuration of the level-shifting decoder LSDA which outputs the signals S 1 , S 2 , S 3 , S 4  to control the 4-transistor switch group SWA configured by the NMOS transistors shown in  FIG. 6 .  
         [0053]     The level-shifting decoder LSDA shown in  FIG. 7  is different from the level-shifting decoder (LSDA) shown in  FIG. 3  in that the current paths of NMOS transistors NT 211  and NT 212  are connected in parallel between the drain terminal of the PMOS transistor PT 21  and the drain terminal of the NMOS transistor NT 21 , the current paths of NMOS transistors NT 221  and NT 222  are connected in parallel between the drain terminal of the PMOS transistor PT 22  and the drain terminal of the NMOS transistor NT 22 , the current paths of NMOS transistors NT 231  and NT 232  are connected in parallel between the drain terminal of the PMOS transistor PT 23  and the drain terminal of the NMOS transistor NT 23 , and the current paths of the NMOS transistors NT 241  and NT 242  are connected in parallel between the drain terminal of the PMOS transistor PT 24  and the drain terminal of the NMOS transistor NT 24 .  
         [0054]     Like the inverters IV 21 , IV 22  shown in  FIG. 2 , inverters IV 21 , IV 22  are operated on low voltage and output inverted signals of the input signals I 0 , I 1 .  
         [0055]      FIG. 8  is a waveform diagram showing an example of the operation of the level-shifting decoder (LSDA) shown in  FIG. 7 .  
         [0056]     Also, in this case, the precharge period is set when the precharge signal pre is binary 0, all of the PMOS transistors PT 21 , PT 22 , PT 23 , PT 24  are turned on and all of the NMOS transistors NT 21 , NT 22 , NT 23 , NT 24  are turned off. As a result, the signal levels of all of the output signals S 1 , S 2 , S 3 , S 4  are made high, indicating the high-voltage level.  
         [0057]     When the precharge signal pre is binary 1, all of the PMOS transistors PT 21 , PT 22 , PT 23 , PT 24  are turned off and all of the NMOS transistors NT 21 , NT 22 , NT 23 , NT 24  are turned on. Thus, a decode output period in which the decode results of the input signals I 0 , I 1  are output is set.  
         [0058]     However, in this case, in opposition to the case of  FIG. 4 , since both of the NMOS transistors NT 211  and NT 212  whose current paths are connected in parallel with the source electrode of the NMOS transistor NT 21  are turned off when both of the input signals I 0 , I 1  are binary 0, only the output signal S 1  is kept high and the other output signals S 2  to S 4  are made low.  
         [0059]      FIG. 9  is a diagram showing a truth table indicating the relation between the input signal and output signal during the decode output period shown in  FIG. 7  of the level-shifting decoder (LSDA).  
         [0060]     As shown in  FIG. 9 , one of the output signals S 1 , S 2 , S 3 , S 4  which is high is output according to a combination of the signal levels of the input signals I 0 , I 1 . One of the NMOS transistors in the 4-transistor switch group SWA can be turned on by controlling the 4-transistor switch group SWA configured by the NMOS transistors shown in  FIG. 6  by use of the output signals S 1 , S 2 , S 3 , S 4  in the decode output period.  
         [0061]     Thus, according to the first embodiment, it is not necessary to insert a level shifter since the level-shifting decoder outputs the decoded output of the input signal of the low-voltage level at the high-voltage level, and the circuit configuration can be simplified accordingly.  
         [0062]     Further, since the input signal is divided into three bit groups and decoded, the MOS transistor switch group can be formed with the hierarchical structure of three hierarchies and the number of MOS transistor switches can be significantly reduced in comparison with that in the conventional matrix-form arrangement. For example, in the case of a 6-bit input signal, the number of MOS transistors of the MOS transistor switch group is set to 384 (=6×2 6 ) for each output in the conventional matrix-form arrangement, but the number of MOS transistors is set to 84 (=64+16+4) in this embodiment.  
         [0063]     Further, since the MOS transistor switch group is formed with three hierarchies, the number of series-connection stages of the current paths of the MOS transistors in the decoder circuit can be reduced from six stages in the conventional case to three stages and the output delay with respect to the input from the reference voltage generation circuit  100  can be improved.  
       Second Embodiment  
       [0064]      FIG. 10  is a block diagram schematically showing an example of the configuration of a decoder circuit according to a second embodiment of this invention and a liquid crystal drive device using the decoder circuit.  
         [0065]     A decoder circuit  10  of the second embodiment includes two level-shifting decoders (LSDB)  21 B,  22 B and a MOS transistor switch group  3 B whose switching operation is controlled by output signals of the level-shifting decoders  21 B,  22 B. The MOS transistor switch group  3 B is formed of high-withstand voltage MOS transistors and has a hierarchical structure of two (k=2) hierarchies.  
         [0066]     The level-shifting decoders  21 B,  22 B are supplied with 6-bit input signals D 0  to D 5  which are divided into two (k=2) bit groups (the number of bits allocated to each bit group can be selectively set, but two groups of three bits are formed in this example) from an image memory  300 . The signal levels of the input signals D 0  to D 5  are set at a low-voltage level of 3.3V, for example. Each of the level-shifting decoders  21 B,  22 B decodes a 3-bit input signal (I 0 , I 1 , I 2 ) of a corresponding bit group and outputs eight decoded output signals (S 1  to S 8 ). The signal levels of the decoded output signals S 1  to S 8  are set at a high-voltage level of 10V, for example. The decoded output signals S 1  to S 8  are respectively supplied to MOS transistor switch groups of the hierarchies (first hierarchy and second hierarchy) corresponding to the level-shifting decoders  21 B,  22 B of the MOS transistor switch group  3 B.  
         [0067]     The first hierarchical MOS transistor switch group is configured by 64 MOS transistors which select eight voltages from 64 reference voltages V 1  to V 64  input from the reference voltage generation circuit  100 . The second hierarchical MOS transistor switch group is configured by eight MOS transistors which select one voltage from eight output voltages of the first hierarchical MOS transistor switch group. The output signal of the second hierarchical MOS transistor switch group is used as gradation display voltage supplied to the liquid crystal display  200 .  
         [0068]     The above MOS transistor switch group of each hierarchy is configured by using an 8-transistor switch group (SWB) formed of eight MOS transistors as one unit. The first hierarchical 64-MOS transistor switch group is configured by 8-transistor switch groups B 101  to B 108 . The second hierarchical MOS transistor switch group is configured by an 8-transistor switch group B 201 .  
         [0069]     Like the liquid crystal drive device  1000  of the first embodiment, the liquid crystal drive device  2000  of the second embodiment is a source driver LSI which supplies one reference voltage selected by a decoder circuit  10  from 64-step reference voltages V 1  to V 64  for 2 6  (=64) gradation display generated from a reference voltage generation circuit  100  to a liquid crystal display  200  as gradation display voltage.  
         [0070]      FIG. 11  is a circuit diagram showing an example in which the 8-transistor switch group SWB is configured by high-withstand voltage PMOS transistors.  
         [0071]     The source electrodes of PMOS transistors PT 31 , PT 32 , PT 33 , PT 34 , PT 35 , PT 36 , PT 37 , PT 38  are connected to input terminals A 1 , A 2 , A 3 , A 4 , A 5 , A 6 , A 7 , A 8  and the drain electrodes thereof are commonly connected to an output terminal OT. Further, input signals S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , S 8  are respectively supplied to the gate electrodes of the PMOS transistors PT 31 , PT 32 , PT 33 , PT 34 , PT 35 , PT 36 , PT 37 , PT 38 .  
         [0072]     The input signals S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , S 8  are controlled and only one of them is made low. Thus, only one of the PMOS transistors PT 31  to PT 38  is turned on and input voltage applied to one of the input terminals A 1  to A 8  which is connected to the source electrode of the PMOS transistor in the on state is output to the output terminal OT.  
         [0073]     That is, one of the input voltages input to the input terminals A 1  to A 8  is selected according to the signals S 1  to S 8  and output to the output terminal OT.  
         [0074]      FIG. 12  is a circuit diagram showing an example of the configuration of the level-shifting decoder (LSDB) which outputs the signals S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , S 8  to control the 8-transistor switch group SWB configured by the PMOS transistors shown in  FIG. 11 .  
         [0075]     The source electrodes of high-withstand voltage PMOS transistors PT 41  to PT 48  are connected to a high-voltage power supply terminal VDDH and the signals S 1  to S 8  are output from the drain electrodes thereof. A precharge signal pre is commonly input to the gate electrodes of the PMOS transistors PT 41  to PT 48 .  
         [0076]     The current paths of high-withstand voltage NMOS transistors NT 411 , NT 412 , NT 413  and NMOS transistor NT 41  are serially connected between the drain electrode of the PMOS transistor PT 41  and the ground node. The current paths of high-withstand voltage NMOS transistors NT 421 , NT 422 , NT 423  and NMOS transistor NT 42  are serially connected between the drain electrode of the PMOS transistor PT 42  and the ground node. The current paths of high-withstand voltage NMOS transistors NT 431 , NT 432 , NT 433  and NMOS transistor NT 43  are serially connected between the drain electrode of the PMOS transistor PT 43  and the ground node. The current paths of high-withstand voltage NMOS transistors NT 441 , NT 442 , NT 443  and NMOS transistor NT 44  are serially connected between the drain electrode of the PMOS transistor PT 44  and the ground node.  
         [0077]     Likewise, the current paths of high-withstand voltage NMOS transistors NT 451 , NT 452 , NT 453  and NMOS transistor NT 45  are serially connected between the drain electrode of the PMOS transistor PT 45  and the ground node. The current paths of high-withstand voltage NMOS transistors NT 461 , NT 462 , NT 463  and NMOS transistor NT 46  are serially connected between the drain electrode of the PMOS transistor PT 46  and the ground node. The current paths of high-withstand voltage NMOS transistors NT 471 , NT 472 , NT 473  and NMOS transistor NT 47  are serially connected between the drain electrode of the PMOS transistor PT 47  and the ground node. The current paths of high-withstand voltage NMOS transistors NT 481 , NT 482 , NT 483  and NMOS transistor NT 48  are serially connected between the drain electrode of the PMOS transistor PT 48  and the ground node.  
         [0078]     A precharge signal pre is commonly input to the gate electrodes of the NMOS transistors NT 41  to NT 48 . Further, an input signal I 0  is input to the gate electrodes of the NMOS transistors NT 423 , NT 443 , NT 463 , NT 483 , an input signal I 1  is input to the gate electrodes of the NMOS transistors NT 432 , NT 442 , NT 472 , NT 482  and an input signal I 2  is input to the gate electrodes of the NMOS transistors NT 451 , NT 461 , NT 471 , NT 481 . Further, a signal obtained by inverting the input signal I 0  by use of an inverter IV 41  is input to the gate electrodes of the NMOS transistors NT 413 , NT 433 , NT 453 , NT 473 , a signal obtained by inverting the input signal I 1  by use of an inverter IV 42  is input to the gate electrodes of the NMOS transistors NT 412 , NT 422 , NT 452 , NT 462  and a signal obtained by inverting the input signal I 2  by use of an inverter IV 43  is input to the gate electrodes of the NMOS transistors NT 411 , NT 421 , NT 431 , NT 441 .  
         [0079]     In this case, the signal levels of the input signals I 0 , I 1 , I 2  are set at the low-voltage level and the inverters IV 41 , IV 42 , IV 43  are inverters operated on low voltage. Therefore, the signal levels of the outputs of the inverters IV 41 , IV 42 , IV 43  are set at the low-voltage level. When the threshold voltage Vth is set at 1V, for example, it is possible to identify and drive the high-withstand voltage NMOS transistor even if the input voltage level is set at the low-voltage level, for example, the binary 0 level is set at 0V and the binary 1 level is set at 3.3V.  
         [0080]     Like the level-shifting decoder (LSDA) shown in  FIG. 3 , in the level-shifting decoder (LSDB), a precharge period is set when the precharge signal pre is binary 0 and a decode output period is set when the precharge signal pre is binary 1.  
         [0081]      FIG. 13  is a diagram showing a truth table indicating the relation between the input signal and output signal in the decode output period of the level-shifting decoder (LSDB) shown in  FIG. 12 .  
         [0082]     As shown in  FIG. 13 , one of the output signals S 1  to S 8  is made low and output according to a combination of the signal levels of the input signals I 0 , I 1 , I 2 . One of the PMOS transistors in the 8-transistor switch group (SWB) can be turned on by controlling the 8-transistor switch group (SWB) configured by the PMOS transistors as shown in  FIG. 11  according to the output signals S 1  to S 8  in the decode output period.  
         [0083]     Like the first embodiment, it is, of course, possible to configure the 8-transistor switch group (SWB) by use of NMOS transistors.  
         [0084]     According to the second embodiment, the MOS transistor switch group can be divided into two hierarchies by dividing the bit group of the input signals into two. As a result, the number of transistors of the MOS transistor group becomes 72 (=64+8) and can thus be further reduced in comparison with the case of the first embodiment.  
         [0085]     In addition, the number of successive connection stages of the MOS transistors in the decoder circuit can be further reduced from three stages in the first embodiment to two stages by dividing the hierarchies of the MOS transistor switch group into two hierarchies. Further, the output delay with respect to the input from the reference voltage generation circuit can be further improved.  
         [0086]     Therefore, according to one aspect of this invention, since the decoder circuit having the signal level conversion function can be configured by use of a less number of transistors, an increase in the chip size of the source driver LSI which is the liquid crystal drive device using the decoder circuit can be prevented and a lowering in the manufacturing yield can be prevented  
         [0087]     Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.