Abstract:
An image processing apparatus determines an image data of a selected area to be an image such as of characters having no halftone or an image such as of a photograph having halftones. An image processing mode optimal to the image data of the selected area is assigned to this area as attribute data. Based on the attribute data, the image data of the selected area is processed in the optimal mode. Each of such area includes at least one pixel, and an overall result of image processing carried out in respective optimal modes is output.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an image data processing apparatus for processing image data, and outputting the processed image data. 
     2. Description of Related Art 
     An image reader for reading an original by fragmenting it into pixels has been conventionally used as an image input device for a digital copying machine or facsimile machine, an OCR (optical character reader), an optical filing system, and a variety of display devices which form, store, and display an image by a combination of pixels having a fixed size. 
     With this type of image reader, image information is quantized and handled as digital image data to carry out various image processing with ease. Generally, the image reader is constructed for image processing to improve image quality such as by emphasizing edges (contours) for clear definition of an image and smoothing for a natural image, and for image processing to enable image editing. 
     Known image editing operations include trimming for extracting only a particular area of an original, masking for blanking a particular area, reversing between negative and positive (black and white), and color conversion for changing a particular color portion into a different color. 
     U.S. Pat. No. 4,750,044, for example, discloses an image reader capable of image editing which includes an attribute memory for storing attribute data corresponding to the nature of image processing. Attribute data corresponding to small image areas into which an original is segmented are stored in the attribute memory in advance, and image processing based on the attribute data is carried out in real time in parallel with image reading. 
     With this image reader, types of image processing may be designated for the respective image areas to enable complicated and diverse image editing. 
     As is well known, to realize high quality reproduction images in the image processing of binary multivalue data corresponding to density levels of respective pixels in an original (hereinafter referred to as binarizing processing), simple binarizing processing in which the multivalue level of one pixel is compared with a fixed threshold level is suited for line images such as characters. Pseudo-tone processing based on the dither method or error diffusion method, on the other hand, is better suited for halftone images such as photographs. 
     It is therefore necessary, when reading an original having a mixture of line images and halftone images, to change the binary processing modes in accordance with attributes of the images indicating whether the images are line images or halftone images (hereinafter referred to as binary attributes). 
     There are image readers including a device for discriminating the binary attributes by various methods as disclosed in Japanese Patent Publication Kokai No. 62-39978 and other publications. The image readers capable of color editing such as color conversion include a device for discriminating color attributes of images. 
     Since conventional image readers output only image data after it has been processed, attribute data used for processing are not output. Accordingly, there is a problem when an operator or an external apparatus handling the image data received from the image reader does not recognize how the image data has been processed. 
     SUMMARY OF THE INVENTION 
     The present invention has been made with regard to the state of the art noted above, and its object is to provide an image data processing apparatus which can output attribute data as well as image data having been processed. 
     The above object is fulfilled, according to the present invention by an image processing apparatus comprising generating means for generating attribute data indicative of information relating to image data processing based on image data representing at least one pixel included in a predetermined area; processing means for processing the image data based on the attribute data; and output means for outputting processed image data and the attribute data to the external device. 
     An image processing mode optimal to image data of a selected area is assigned to this area as attribute data. Based on the attribute data, the image processing means processes the image data of the selected area in the optimal mode, thereby assuring a high image quality. The attribute data for determining the image processing mode may include trimming, masking and negative/positive reversal commands. 
     The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a sectional front view schematically showing an image reader according to the present invention, 
     FIG. 2 is a block diagram of electric circuitry included in the image reader, 
     FIGS. 3A and 3B are views showing the construction of an attribute memory, 
     FIG. 4 is a block diagram of an image discriminator, 
     FIG. 5 is a block diagram of a binary attribute discriminator, 
     FIG. 6 is a block diagram of a color attribute discriminator, 
     FIG. 7 is a block diagram of an image processor, 
     FIG. 8 is a block diagram of an attribute data output controller, 
     FIG. 9 is a block diagram of an output controller, 
     FIG. 10 is a timing chart showing an attribute data outputting operation, 
     FIGS. 11 through 20 are flowcharts showing operations of the image reader, 
     FIG. 21 is a block diagram of a modified image processor, and 
     FIG. 22 is a flowchart of an attribute data writing process carried out by the image processor shown in FIG. 21. 
     What is illustrated in the drawings with a &#34;˜&#34; may be described in the specification using a &#34;-&#34;. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a sectional front view schematically showing an image reader according to the present invention, 
     The image reader 1 comprises a glass plate 2 acting as an original table attached to a top face of a box-shaped body for supporting originals whose maximum size is A3 in DIN standard. An original placed thereon is pressed down by an original cover 3. The glass plate 2 has a reference pattern 14 of a white image for shading correction mounted at a forward end in a scanning direction. 
     The box-shaped member contains an optical system arranged to scan the original in a direction of arrow M5 (an auxiliary scanning direction), and an electric circuitry 12 for generating image data corresponding to density levels of images on the original. 
     The optical system includes a first slider 13 having an exposure lamp 4, a reflecting mirror 5 and a mirror 6, a second slider 13a having mirrors 7 and 8, and a main lens 9. Assuming that the first slider 13 is movable at a velocity v, the second slider 13a is movable at a velocity v/2. 
     Scanning light having passed through the main lens 9 impinges upon an image sensor 10 mounted on a support 11, where the light is converted into an electric signal. The image sensor 10 includes a plurality of CCD chips arranged continuously in a main scanning direction for reading originals with a resolution of 400 pixels per inch. Each CCD chip has a plurality of light receiving elements arranged in a row. Each light receiving element is divided into three regions, and has a spectrofilter covering a surface thereof so that each region receives one of the three colors, R (red), G (green) and B (blue). One light receiving element corresponds to one pixel in an original, and each light receiving element outputs a photoelectric conversion signal to the electric circuitry 12, the signal corresponding to an intensity level of reflected light for a single color of each pixel in the original. 
     FIG. 2 is a block diagram of the electric circuitry 12. 
     The electric circuitry 12 includes a color separator 21 for separating the photoelectric conversion signal received from the image sensor 10 into R, G and B color signals and amplifying the latter to a suitable level, a digitalizer 22 for effecting A/D conversion (quantization) of the respective analog signals and outputting 8-bit image data DR7-0, DG7-0 and DB7-0 of the respective colors, a shading corrector 23 for correcting intensity variations in the main scanning direction of the color image data DR7-0, DG7-0 and DB7-0 and variations among the bits of the image sensor 10, an image discriminator 25 for discriminating binary attributes and color attributes, a density converter 26 for effecting density level adjustment and Υ conversion according to density characteristics (Υ characteristics) of external devices connected to the image reader, an image processor 28 for effecting image processing including image editing and binarization, an output controller 29 for controlling data output, an attribute memory 30 for storing designated attribute data aj (j=0, 1, 2) which will be described later, an attribute data output controller 31, a clock generator 41, a line memory 24 for storing image data DG17-10 for one line output from the shading corrector 23, a synchronizing signal generator 40 for outputting various synchronizing signals to various components, a lamp controller 4a for controlling on/off operations of the exposure lamp 4, a driver 16a for driving a scan motor 16, and a CPU 20 for effecting overall controls of the circuitry. 
     The CPU 20 includes a ROM 20a for storing processing programs, and a register 20b and a RAM 20c for temporarily storing various flags and status data. The CPU 20 communicates various commands (control command code data) and data showing an operating condition (status) of the image sensor 10 with an external host apparatus having a control device manipulated by an operator. In response to a command received, the CPU 20 generates designated attribute data aj specifying image processing and binarizing processing and stores the data in the attribute memory 30 prior to reading of an original. 
     The synchronizing signals output from the synchronizing signal generator 40 include a horizontal synchronizing signal Hsync output for each main scan line, a pixel clock signal SYNCK for providing a reference for pixel by pixel data transmission timing, and an enable signal VD showing validity periods of data output from the image sensor 10. 
     FIGS. 3A and 3B are views showing the construction of the attribute memory 30. 
     As shown in FIG. 3B, the attribute memory 30 is constructed to store the designated attribute data aj generated by the CPU 20 in each segmented area E comprising an 8×8 dot matrix corresponding to a portion of an image G segmented into 8 pixels in the main and auxiliary scanning directions. 
     In the image sensor 10, designated attribute data a0 specifies the binarizing processing, while designated attribute data a1 and a2 specify negative/positive reversal and trimming, respectively. 
     FIG. 4 is a block diagram of the image discriminator 25. 
     The image discriminator 25 includes a binary attribute discriminating section 251, a color attribute discriminating section 252 and a discriminated data output 253. 
     The binary attribute discriminating section 251 discriminates binary attributes for each segmented area E, i.e. whether the segmented area E corresponds to a character image or to a halftone image, and outputs a 1-bit discriminated attribute data α0. 
     The binary attribute discriminating section 251 detects density variations in the segmented area to discriminate between a character and a halftone. That is, in the case of a character, there is a clear distinction between a thin black line and a white base of the original document. Consequently, the density variations in the segmented area is outstanding. In the case of a halftone image (photograph), the same density often prevails throughout the segmented area. Thus, the variations in density, i.e. edge components of image data read, are detected for discriminating between a character and a halftone. 
     The binary attribute discriminating section 251 receives image data DG17-DG10 (G type image data) which, as shown in FIG. 5, are once stored in an 8-line memory 2511 to discriminate the segmented section E. The data stored in this memory are successively input to an edge detector 2512 for detecting edge components of an area corresponding to the segmented area E, the result being output as an edge detection amount. The edge detection amount is input to an edge discriminator 2513, from which the discriminated attribute α0 is output, i.e. an indication &#34;character area&#34; when the edge detection amount is greater than a discriminant threshold level, and an indication &#34;halftone&#34; area&#34; when the detection amount is less than the threshold level. 
     The color discriminating section 252 discriminates color attributes for each segmented area E, i.e. whether the segmented area E corresponds to a particular color image or not, and outputs a 1-bit discriminated attribute data α1 indicating a result of discrimination. 
     The color attribute discriminating section 252 detects a color density condition of the segmented area to discriminate a particular color. That is, the image signal data separated into the three colors, R, G and B, have different levels according to the color of the image read. A particular color is determined by detecting a combination of the level differences. 
     In this embodiment, the color attribute discriminating section is shown in block diagram in which the particular color is &#34;red&#34;. As shown in FIG. 6, the color attribute discriminating section receives the image data DR17-DR10 (R type image data) and DB17-DB10 (B type image data) which are once stored in 8-line memories 2521 and 2522, respectively, to discriminate the segmented section E. The data stored in the memories are successively input to average detector 2523 and 2524. The average detectors read image data corresponding to the segmented area E from the 8-line memories, and output averages derived from the pixel data (for 8×8=64 pixels). The output averages of the respective color types are input to binarizers 2525 and 2526, respectively, which output &#34;0&#34; or &#34;1&#34; (R type output being referenced DR and B type output DB). This binarizing step is carried out to facilitate the discriminating operation to follow. That is, &#34;1&#34; is output when the average is greater than a predetermined threshold level, and &#34;0&#34; when the average is less than the threshold level. The outputs DR and DB from the digitalizers are input to a discriminator 2527, which outputs the discriminated attribute data (color attribute data) α1 based on a combination of input data DR and DB as set out in the following table: 
     
         ______________________________________    DR      0            1______________________________________DB     0       a1 = 0 (black char.                         a1 = 1 (part. color, red)  1       a1 = 0 (blue)  a1 = 0 (white, base)______________________________________ 
    
     The discriminated attribute data (α0 is &#34;0&#34; when the segmented area E discriminated corresponds to a character image, and &#34;1&#34; when the area E corresponds to a halftone image. The discriminated attribute data α1 is &#34;1&#34; when the segmented area E discriminated corresponds to the particular color, and &#34;0&#34; when the area E corresponds to a different color. 
     FIG. 7 is a block diagram of the image processor 28. 
     The image processor 28 includes a filtering section 281, a trimming and masking section 282, a simple binarizing section 283, a pseudo-halftone processing section 284, a data selecting section 286, a selector 285 and a negative processing section 287. 
     The image processor 28 receives image data Dm27-20 transmitted serially in the order of pixel arrangement from the density converter 26. The input image data Dm27-20 are first subjected to processing for improvement of image quality such as edge highlighting and smoothing at the filtering section 281. Next, the trimming and masking section 282 operable in response to designated attribute data a2 carries out masking processing and outputs &#34;0&#34; corresponding to a blank portion when the data a2 is &#34;1&#34;. When the data a2 is &#34;0&#34;, it is output as it is from the trimming and masking section 282 (data through). 
     The image data output from the trimming and masking section 282 are binarized at the simple binarizing section 283 and pseudo-halftone processing section 284, respectively, and input simultaneously to the selector 285 as the binary image data DA and DB. 
     The selector 285, in response to an output data DSEL0 from the data selecting section 286, selectively outputs one of the binary data DA and DB. 
     The data selecting section 286 receives designated attribute data a0 for controlling the binarizing processing, along with the discriminated attribute data α0 resulting from the automatic discrimination of the binary attributes. The value of output data is determined according to the value of data a0. That is, if the data a0 is &#34;0&#34;, the discriminated attribute data α0 is output as it is. If the data a0 is &#34;1&#34;, the discriminated attribute data α0 is output as reversed. Thus, when the data a0 is &#34;0&#34;, the binarizing processing designation applied from outside is regarded as a default and the image processor 28 outputs binary image data based on the binary attributes automatically discriminated by the image discriminator 25. When the data a0 is &#34;1&#34;, binary image data having undergone binarizing processing different from the result of the automatic discrimination of binary attributes. 
     The negative processing section 287 outputs the binary image data as received from the selector 285 if the specified attribute data a1 is &#34;0&#34;, and as reversed if the data a1 is &#34;1&#34;. The negative processing section 287 successively outputs the data in the form of parallel video data VIDEO01-08 in units of 8 pixels. 
     To enable image discrimination for each segmented area E, the image processor 28 further includes a line memory for storing image data Dm27-20 for 8 lines, not shown, and an 8-bit serial/parallel converter, not shown. 
     FIG. 8 is a block diagram of the attribute data output controller 30. 
     This control 30 includes a synthesizing section 301 for combining the discriminated attribute data α0, α1 and designated attribute data aj, and outputting 5-bit attribute data a4-0. 
     The attribute data a4 and a3 correspond to the discriminated attribute data α0 and α1, respectively. 
     FIG. 9 is a block diagram of the output controller 29, and FIG. 10 is a timing chart showing an operation for outputting the attribute data a4-0. 
     The output controller 29 includes a divider 401 for outputting a signal 1/8.Hsync which is one eighth of the signal SYNCK, a latch circuit 402 for latching the signal VD in accordance with the signal Hsync, selectors 403 and 404 for outputting control signals S0 and S1 in response to output control data C0-1 from the CPU 20, respectively, and data latch circuits 405 and 406 operable under control of the signals S0 and S1 to select video data VIDEO1-8 or attribute data a4-0 to be output data DATA, respectively. 
     The signal 1/8 Hsync is input to clock terminals CK of the data latch circuits 405 and 406, applied as it is as an optional input to the selector 404 and as inverted by an inverter 407 as an optional input to the selector 404, and output externally through an inverter 408 as an output synchronizing signal DSYNC. 
     When the signal VD becomes active (&#34;L&#34;), the divider 401, and selectors 403 and 404 output signals 1/8.Hsync, S0 and S1, respectively, to enable output of the output data DATA. 
     An operation for outputting the output data DATA will be described referring to FIG. 10 and FIG. 2 also. 
     When scanning of the document is started, the color image data DR17-10, DG17-10 and DB17-10 of the leading pixel on the first line and onward are input to the image discriminator 25, the data DG17-10 being input to the density converter 26 as well. Since image discrimination is effected for each segmented area E embracing eight lines as noted hereinbefore, the image discriminator 25 stores the color image data DR17-10, DG17-10 and DB17-10 of eight lines. Consequently, the image discriminator 25 outputs invalid data during a scan up to the eighth line. In FIG. 10, the invalid data are marked with hatching. Thus, the signal VD becomes &#34;L&#34; in synchronism with the signal Hsync indicating start of a scan of the ninth line. The image discriminator 25 outputs the discriminated attribute data α0 and α1 corresponding to the segmented area E including the first line in synchronism with the signal 1/8.HSync after input of the color image data DR17-10, DG17-10 and DB17-10 of the first eight pixels on the ninth line. 
     The attribute memory 30 outputs the designated attribute data a2-0 with the same timing as output of the discriminated attribute data α0 and α1. 
     On the other hand, a delay corresponding to eight dots occurs at the density converter 26. 
     As a result, image data Dm27-20 of the ninth line are input to the image processor 28 with a delay corresponding to eight dots compared with the image discriminator 25. Since a delay corresponding to eight lines as noted above occurs at the image processor 28 also, image processing for the image data Dm27-20 of the first line is completed at a point of time at which the image data Dm27-20 of the ninth line are input. Further, a delay due to the serial/parallel conversion occurs at the image processor 28, and therefore the video data VIDEO1-8 corresponding to the first line are output in parallel in units of eight pixels with a further delay corresponding to eight dots after the input for the ninth line. 
     The attribute data output controller 31 outputs the attribute data a4-0 in timed relationship with the output of the video data VIDEO1-8. 
     The video data VIDEO1-8 and attribute data a4-0 thus output are latched by the data latch circuits 405 and 406 of the output controller 29, respectively, at the timing of a rise of the signal 1/8.Hsync. However, the data latch circuits 405, 406 do not output the latched data constantly from their output terminals Q, the data output being controlled by signals S0 and S1 corresponding to output control data C0 and C1 of 2 bits in total provided by the CPU 20 (active flow). 
     When the output control data C0 and C1 are both &#34;0&#34;, the signal S0 is set to &#34;L&#34; (grounding level), and the signal S1 to &#34;H&#34; (Vcc level). Consequently, the data latch circuit 405 becomes an output enable condition while the output terminal of the data latch circuit 406 becomes a high impedance condition. Then, the output controller 29 outputs the video data VIDEO1-8 as the output data DATA in the order of scanning. 
     When the output control data C0 is &#34;1&#34; and output control data C1 is &#34;0&#34;, the signals S0 and S1 are set to &#34;H&#34; and &#34;L&#34;, respectively. As a result, the attribute data a4-0 are successively output as the output data DATA. 
     When the output control data C0 is &#34;0&#34; and output control data C1 is &#34;1&#34;, the signals S0 and S1 are set to &#34;H&#34; or &#34;L&#34; depending on the signal 1/8.Hsync. As a result, the video data VIDEO1-8 and attribute data a4-0 are alternately output as the output data DATA. 
     Thus, by setting the output control data C0 and C1 by command designation from the host apparatus, the image reader 1 outputs the video data VIDEO1-8 as a normal mode, outputs the attribute data a4-0 for redesignating an area for image editing purposes, or alternately outputs the video data VIDEO1-8 and attribute data a4-0 for displaying an image and its attributes at the same time to enable confirmation of image discrimination. In this way, an output selection may be made in accordance with the purpose of using the output data DATA or the data processing mode at a receiving side. 
     As shown in FIG. 10, the image reader 1 outputs the video data VIDEO1-8 and attribute data a4-0 alternately in half a cycle of outputting the video data VIDEO1-8 only or attribute data a4-0 only. Thus, the period for outputting the video data VIDEO1-8 is never extended by output of the attribute data a4-0. The attribute data a4-0 are output through the same signal line as the video data VIDEO1-8, and there is no need for a special signal line for outputting the attribute data a4-0. 
     The way in which the image reader 1 operates will be described next with reference to the flowcharts shown in FIGS. 11 through 20. 
     FIG. 11 is a main flowchart schematically showing operations of the CPU 20. 
     When the image reader 1 is turned on and the program is started, initialization is carried out first at step #1. 
     Then, step #2 is executed to check presence or absence of a command from the host apparatus. If there is a command, the type of the command is determined (step #3). Depending on the type of the command, a reading process (step #4), a reading mode setting process (step #5), an attribute setting process (step #6) or an output data setting process (step #7) is carried out. 
     Thereafter, other processing (step #8) is carried out and the program returns to step #2 for repeating the steps #2 through #8. 
     FIG. 12 is a flowchart of reception processing, and FIG. 13 is a flowchart of transmission processing. 
     These routines are interrupt routines carried out upon access made by the host apparatus as necessary. 
     In the reception processing shown in FIG. 12, a code analysis is carried out of a signal received (step #11) If reception of a command is confirmed at step #12, the received command is stored in a predetermined region in the register 20b (step #13). 
     If the received signal requests a status notification (step #14), a status data indicating a standby state or a wait state is read from the register 20b for transmission to the host apparatus. 
     If the received signal agrees with none of predetermined commands and status requests, a code data indicating a reception error is transmitted at step #16. 
     In the transmission processing shown in FIG. 13, the program waits for completion of a transmission allowing a next transmission (step #21). A code data for transmission is set to the register 20b (step #22). 
     Thereafter, step #23 is executed to check if there is a further code data to be transmitted, i.e. whether a transmission is necessary. If a transmission is necessary, the program returns to step #21. 
     FIG. 14 is a flowchart of initialization carried out at step #1 in FIG. 11. 
     First, &#34;wait&#34; is set as a status to indicate that preparations for a scanning and reading operation are under way. That is, a data corresponding to &#34;wait&#34; is stored in a region for status in the register 20b (step #31). 
     Then, at step #32, a self test is carried out to check if all the components are operating normally. 
     Next, step #33 is executed to check if there is trouble. If a trouble is found, the program moves to step #37 for transmitting a disable code to the host apparatus. 
     In the absence of trouble, the program moves to step #34 for initializing the components. At this time &#34;0&#34; is written to the attribute memory 30 as designated attribute data a0, a1 and a2. Consequently, unless the designated data a0-a2 are rewritten, the image processor 28 does not effect image editing for trimming or negative/positive reversal, and the binarizing processing is carried out on the basis of the discriminated attribute data α0. 
     The density converter 26 is set for standard density. For the output controller 29, inputs to the selectors 403 and 404 are selected for the video data VIDEO1-8 and attribute data a4-0 to be output alternately. 
     After the initialization, step #35 is executed to move the first slider 13 to home position. Upon completion of this movement, step #36 is executed to change the status from &#34;wait&#34; to &#34;ready&#34; indicating a standby state. 
     FIG. 15 is a flowchart of the reading process mentioned hereinbefore. 
     First, &#34;busy&#34; is set to the status to indicate that a reading operation is in progress (step #41), and the exposure lamp 4 is lit (step #42). 
     Next, the scan motor 16 is turned on (step #43). The program waits for the first slider 13 to reach a shading position, i.e. a position directly under the reference pattern 14 (step #44). 
     When the first slider 13 reaches the reference pattern 14, the reference pattern 14 is read for a shading correction. The reference image data (white data) is stored in the line memory 24 (step #45). 
     Subsequently, at step #46, the program waits for the first slider 13 to reach the forward end of the document. At step #47, the synchronizing signal generator 40 is turned on to output the synchronizing signal. Then, various components come into operation in response to the synchronizing signal. After start of scanning of the ninth line, effective video data VIDEO1-8 and attribute data a4-0 are output alternately as described hereinbefore. 
     The program waits for completion of scanning of the document, i.e. for the first slider 13 to reach the rear end of the document (step #48). Then, the synchronizing signal generator 40 is turned off (step #49), the scan motor 16 is turned off for once (step #50), and the exposure lamp 4 is turned off (step #51). 
     Subsequently, the scan motor 16 is rotated backward to return the two sliders 13 and 13a (step #52). The program waits for the first slider 13 to return to home position (step #53). Then, the scan motor 16 is turned off (step #54) and, finally at step #55, &#34;ready&#34; is set to the status. 
     FIG. 16 is a flowchart of the reading mode setting carried out at step #5 in FIG. 11. 
     At step #61, &#34;wait&#34; is set to the status. At step #62, parameters included in the command are checked. Depending on the parameters, density setting (step #63) or other setting such as designation of an output device or the like (step #64) is carried out. At step #65, &#34;ready&#34; is set to the status. 
     FIG. 17 is a flowchart of the density setting carried out at step #63. 
     At step #71, checking is made whether a density level is to be set automatically or not. If the setting is not to be made automatically, the program jumps to step #74 for setting the density converter 26 in accordance with parameters transmitted from the host apparatus based on a designating operation by the operator. 
     If step #71 finds the method to be automatic, step #72 is executed to effect a preliminary scan for detecting density of the document and transfer the image data DG17-10 successively stored in the line memory 24 to the RAM 20c as appropriate. At step #73, the density of the document is detected from the data in the RAM 20c. Thereafter, step #74 is executed to set the density converter 26 in accordance with the detection results. 
     FIG. 18 is a flowchart of the attribute setting carried out at step #6 in FIG. 11. 
     First, &#34;wait&#34; is set to the status (step #81), and validity of a designation is checked (step #82). 
     If the designation is incorrect, e.g. an area outside a reading range is designated or there is an error in the order of designation of coordinates, the program moves to step #82 to transmit the error code to the host apparatus. 
     If the designation is correct, attribute data write processing is carried out to write the designated attribute data a0, a1 and a2 to the attribute memory 30 (step #83). Then, &#34;ready&#34; is set to the status (step #84). 
     FIG. 19 is a flowchart of the attribute data writing process carried out at step #83. 
     The type of command from the host apparatus is checked at step #91, and various processes are carried out at steps #92 through #98 according to the types thereof. 
     When an automatic discrimination of binary attributes is specified, step #92 is executed to set the specified attribute data a0 to &#34;0&#34; for a specified segmented area E. 
     If binary attributes are specified in advance, step #93 is executed to set the specified attribute data a0 to &#34;1&#34; for the specified segmented area E. 
     When positive, i.e. no black and white reversal, is specified, step #94 is executed to set the specified attribute data a1 to &#34;0&#34; for the specified segmented area E. On the other hand, when negative, i.e. the black and white reversal, is specified, step #95 is executed to set the specified attribute data a1 to &#34;1&#34; for the specified segmented area E. 
     When trimming is specified, step #96 is executed to set the specified attribute data a2 to &#34;1&#34; for the specified segmented area E. When masking is specified, step #97 is executed to set the specified attribute data a2 to &#34;1&#34; for the specified segmented area E. 
     When cancellation of trimming/masking is specified, step #98 is executed to set the specified attribute data a2 back to &#34;0&#34; for the specified segmented area E. 
     FIG. 20 is a flowchart of the output data setting process carried out at step #7 in FIG. 11. 
     In this routine, the type of output data DATA is checked first at step #101, and steps #102 through #104 are executed according to the type. 
     When output of only the video data VIDEO1-8 is selected, step #102 is executed to set both the output control data C0 and C1 to &#34;0&#34;. 
     When output of only the attribute data a4-0 is selected, step #103 is executed to set the output control data C0 to &#34;1&#34; and output control data C1 to &#34;0&#34;. 
     When output of both the video data VIDEO1-8 and attribute data a4-0 is selected, step #104 is executed to set the output control data C0 to &#34;0&#34; and output control data C1 to &#34;1&#34;. 
     FIG. 21 is a block diagram of a modified image processor 28a. 
     In this drawing, like components are labeled with like references with respect to FIG. 7, and their description will not be repeated. 
     The modified construction shown employs specified attribute data a3 for indicating the data to which priority is given, specified attribute data for specifying the binarizing process in the foregoing embodiment, and discriminated attribute data α0. Consequently, the attribute data output controller 30 in this example, though not shown in the drawing, outputs 6-bit attribute data a5-a0J combining the discriminated attribute data α0 and α1 and specified attribute data a0J, a1, a2 and a3. 
     The attribute data a5 and a4 correspond to the discriminated attribute data α0 and α1, respectively. 
     The image processor 28a includes a selector 285a and a data selecting section 286a in place of the selector 285 and data selecting section 286 in the image processor 28 shown in FIG. 7. 
     The data selecting section 286a receives the discriminated attribute data α0, and specified attribute data a0J specifying binary attributes for each segmented area E, both as optional inputs, as well as the specified attribute data a3 for controlling output selection. 
     When the value of specified attribute data a3 is &#34;0&#34;, priority is given to the discriminated attribute data α0 which is output as output data DSEL1. Conversely, when the value of specified attribute data a3 is &#34;1&#34;, priority is given to the specified attribute data a0J which is output as output data DSEL1. 
     The selector 285a selectively outputs one of the binary data DA and DB in accordance with the value of the output data DSEL1 from the data selecting section 286a. 
     That is, by storing the specified attribute data a3 in the attribute memory 30, the image processor 28a can select between automatic binarizing processing based on the result of discrimination by the image discriminator 28 and externally specified binarizing processing based on the binary attributes specified from outside. 
     FIG. 22 is a flowchart of an attribute data writing process carried out in the modified example. 
     FIG. 22 corresponds to the image processor 28a in FIG. 21. 
     The type of command from the host apparatus is checked at step #291, and various processes are carried out at steps #292 through #300 according to the types thereof. Steps #294 through #298 are identical to steps #94 through 98 in FIG. 19 and their description will not be repeated. 
     When the simple binary processing is specified, step #292 is executed to set the specified attribute data a0J to &#34;0&#34; for a specified segmented area E. When the pseudo-halftone processing is specified, step #293 is executed to set the specified attribute data a0J to &#34;1&#34; for the specified segmented area E. 
     When the automatic discrimination of the binary processing (discriminated attribute data α0) is given priority, step #299 is executed to set the specified attribute data a3 to &#34;0&#34; for the specified segmented area E. When the discrimination of the binary processing (discriminated attribute data a0J) based on an external specification is given priority, step #300 is executed to set the specified attribute data a3 to &#34;1&#34; for the specified segmented area E. 
     According to the foregoing embodiment and modified example, the discriminated attribute data α0 according to the result of discrimination of the binary attributes is output. Consequently, character recognition at the host apparatus has improved efficiency since recognizing processing is carried out only for the segmented area E corresponding to a character image based on the discriminated attribute data α0. When the image reader 1 is used with a filing system or a facsimile machine, data processing such as data compression of the video data VIDEO1-8 suited to line images or halftone images may be carried out based on the discriminated attribute data α0. 
     Although the present invention has been fully described by way of examples with reference to the accompanying drawings, it is to be noted that various changes and modifications will be apparent to those skilled in the art. Therefore, unless otherwise such changes and modifications depart from the scope of the present invention, they should be construed as being included therein.