Abstract:
A method for improving the reverse breakdown voltage between P-well and N-well and related semiconductor silicon devices are described herein. In one aspect, a semiconductor silicon device comprises a substrate; a P-well in said substrate; an N-well in said substrate; wherein said N-well and said P-well are separated by said substrate. In another aspect, a method for increasing the reverse breakdown voltage from P-well to N-well comprises: providing a substrate; forming an N-well and a P-well in said substrate and separating said N-well and said P-well by said substrate.

Description:
RELATED APPLICATIONS INFORMATION 
       [0001]    The application claims priority under 35 U.S.C. 119(a) to Chinese application number 201110076115.5, filed on Mar. 29, 2011, which is incorporated herein by reference in its entirety as if set forth in full. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The embodiments described herein relate to microelectronics, and more particularly, to a method for increasing reverse breakdown voltage between P-well and N-well and related semiconductor silicon devices. 
         [0004]    2. Related Art 
         [0005]    In the manufacturing process of the integrated circuit, there exits such a semiconductor silicon device,  FIG. 1A  is a plan view showing the semiconductor silicon device under the existing technologies.  FIG. 1B  is a cross-sectional view taken along line AA in  FIG. 1A . The semiconductor silicon device includes an N-well  11 , a P-well  12  and a P-type substrate  13 , the N-well  11  and the P-well  12  are located in the P-type substrate  13 , and the N-well  11  is adjacent to the P-well  12 . An N+ implant region  111  is formed in the N-well  11 , a voltage V 1  is applied to the N-well  11  via the N+ implant region  111 , a P+ implant region  121  is formed in the P-well  12 , and a voltage V 2  is applied to the P-well  12  via the P+ implant region  121 , V 1 &gt;V 2 . 
         [0006]    For example, for the 0.18 um process node, if the differentia between the voltage applied to the N-well  11  and the voltage applied to the P-well  12  exceeds 14 v, the diode formed by the P-well  12  and the N-well  11  would probably break down. In other words, the reverse breakdown voltage for the diode formed by P-well  12  and N-well  11  is only about 14 v. 
       SUMMARY 
       [0007]    A method for improving the reverse breakdown voltage between P-well and N-well and related semiconductor silicon devices are described herein and the described method increases the reverse breakdown voltage between P-well and N-well. 
         [0008]    In one aspect, a method for increasing the reverse breakdown voltage between P-well and N-well, the method comprises providing a substrate; forming an N-well and a P-well, wherein said N-well and said P-well are separated by said substrate. 
         [0009]    In another aspect, a semiconductor silicon device comprises: a substrate; a P-well formed in said substrate; an N-well formed in said substrate; wherein said N-well and said P-well are separated by said substrate. 
         [0010]    Because the N-well and the P-well are surrounded by the substrate, the N-well and the P-well are not connected directly, and the carrier concentration of the substrate is lower than the carrier concentration of the P-well and the N-well by several orders of magnitude, as a result, the reverse breakdown voltage between P-well and N-well is increased. 
         [0011]    These and other features, aspects, and embodiments are described below in the section entitled “Detailed Description.” 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0013]      FIG. 1A  is a plan view showing a semiconductor silicon device under the existing technologies; 
           [0014]      FIG. 1B  is a cross-section view taken along line AA in  FIG. 1A ; 
           [0015]      FIG. 2A  is a plan view showing a semiconductor silicon device according to a first embodiment; 
           [0016]      FIG. 2B  is a cross-section view taken along line BB in  FIG. 2A ; 
           [0017]      FIG. 3  is a plan view showing a PMOS transistor according to another embodiment; 
           [0018]      FIG. 4  is a cross-sectional view taken along line CC in  FIG. 3 ; 
           [0019]      FIG. 5  is a flow chart showing a method for increasing the reverse breakdown voltage between P-well and N-well according to one embodiment; 
           [0020]      FIG. 6  is a flow chart showing a method for increasing the reverse breakdown voltage between P-well and N-well according to another embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    Referring now to the drawings, a description will be made herein of embodiments herein. 
         [0022]      FIG. 2A  is a plan view showing a semiconductor silicon device according to a first embodiment;  FIG. 2B  is a cross-section view taken along line BB in  FIG. 2A ; the semiconductor silicon device can include an N-well  11 , a P-well  12  and a P-type substrate  13 . In particular, the N-well  11  and the P-well  12  are formed in the P-type substrate  13 , the N-well  11  and P-well  12  are separated by the P-type substrate  13 . 
         [0023]    In this embodiment, since the N-well  11  is surrounded by the P-type substrate  13  and the carrier concentration of the P-type substrate  13  is lower than the carrier concentration of the P-well  12  by several orders of magnitude, as a result, the reverse breakdown voltage between the P-well  12  and the N-well  11  is increased. In this embodiment, the P-type substrate could separate the N-well and the P-well, and the manufacturing process of the integrated circuit does not need to be changed and associated cost is reduced. 
         [0024]    In another embodiment, the P-type substrate may be replaced by an N-type substrate, in this instance, the P-well is surrounded by the N-type substrate and the carrier concentration of the N-type substrate is lower than the carrier concentration of the N-well by several orders of magnitude, as a result, the reverse breakdown voltage between P-well and N-well is increased. Additionally, in this embodiment, the N-type substrate can separate the N-well and the P-well, and the manufacturing process of the integrated circuit does not need to be changed and associated cost is reduced. 
         [0025]    In another embodiment, in order to further improve performance, the distance W p  between the N-well  11  and the P-well  12  satisfies the following relationship: 
         [0000]    
       
         
           
             
               W 
               P 
             
             &gt; 
             
               
                 [ 
                 
                   
                     
                       2 
                        
                       
                         ɛ 
                         s 
                       
                     
                     q 
                   
                    
                   
                     1 
                     
                       N 
                       A 
                     
                   
                    
                   
                     
                       ( 
                       
                         
                           V 
                           BJ 
                         
                         - 
                         
                           V 
                           A 
                         
                       
                       ) 
                     
                     
                       ( 
                       
                         1 
                         + 
                         
                           
                             N 
                             A 
                           
                           
                             N 
                             D 
                           
                         
                       
                       ) 
                     
                   
                 
                 ] 
               
               
                 1 
                 2 
               
             
           
         
       
     
         [0026]    Furthermore, in  FIG. 2A  and  FIG. 2B , in order to apply a voltage on the N-well  11  and the P-well  12 , an N+ implant region  111  is formed in the N-well  11  and a P+ implant region  121  is formed in the P-well  12 . 
         [0027]    In order to further improve performance, the distance W N1  between the N+ implant region  111  in the N-well  11  and the edge of N-well  11  satisfies the following relationship: 
         [0000]    
       
         
           
             
               W 
               
                 N 
                  
                 
                     
                 
                  
                 1 
               
             
             &gt; 
             
               
                 [ 
                 
                   
                     
                       2 
                        
                       
                         ɛ 
                         s 
                       
                     
                     q 
                   
                    
                   
                     1 
                     
                       N 
                       D 
                     
                   
                    
                   
                     
                       ( 
                       
                         
                           V 
                           BJ 
                         
                         - 
                         
                           V 
                           A 
                         
                       
                       ) 
                     
                     
                       ( 
                       
                         1 
                         + 
                         
                           
                             N 
                             D 
                           
                           
                             N 
                             A 
                           
                         
                       
                       ) 
                     
                   
                 
                 ] 
               
               
                 1 
                 2 
               
             
           
         
       
     
         [0028]    In particular, ε s  is the silicon absolute permittivity, q is the electron charge, N A  is the doping concentration of the P-type substrate  13 , N D  is the doping concentration of the N-well  11 , V BJ  is the built-in potential of the PN junction formed by the N-well  11  and the P-type substrate  13 , V A  is the potential difference between the P-well  12  and the N-well  11 . 
         [0029]    For example: when V A =−20V, the distance W p  between the N-well  11  and the P-well  12  satisfies the following relationship: 
         [0000]    
       
         
           
             
               
                 
                   
                     W 
                     P 
                   
                   &gt; 
                   
                     
                       [ 
                       
                         
                           
                             2 
                              
                             
                               ɛ 
                               s 
                             
                           
                           q 
                         
                          
                         
                           1 
                           
                             N 
                             A 
                           
                         
                          
                         
                           
                             ( 
                             
                               
                                 V 
                                 BJ 
                               
                               - 
                               
                                 V 
                                 A 
                               
                             
                             ) 
                           
                           
                             ( 
                             
                               1 
                               + 
                               
                                 
                                   N 
                                   A 
                                 
                                 
                                   N 
                                   D 
                                 
                               
                             
                             ) 
                           
                         
                       
                       ] 
                     
                     
                       1 
                       2 
                     
                   
                   ≈ 
                     
                    
                   
                     
                       [ 
                       
                         
                           
                             
                               
                                 
                                   2 
                                   × 
                                   1.04 
                                   × 
                                   
                                     10 
                                     
                                       - 
                                       12 
                                     
                                   
                                 
                                 
                                   1.6 
                                   × 
                                   
                                     10 
                                     
                                       - 
                                       19 
                                     
                                   
                                 
                               
                               × 
                               
                                 1 
                                 
                                   10 
                                   15 
                                 
                               
                               × 
                             
                           
                         
                         
                           
                             
                               20 
                               
                                 ( 
                                 
                                   1 
                                   + 
                                   
                                     
                                       10 
                                       15 
                                     
                                     
                                       3 
                                       × 
                                       
                                         10 
                                         17 
                                       
                                     
                                   
                                 
                                 ) 
                               
                             
                           
                         
                       
                       ] 
                     
                     
                       1 
                       2 
                     
                   
                 
               
             
             
               
                 
                   = 
                     
                    
                   
                     5.1 
                     × 
                     
                       10 
                       
                         - 
                         4 
                       
                     
                      
                     
                         
                     
                      
                     cm 
                   
                 
               
             
             
               
                 
                   = 
                     
                    
                   
                     5.1 
                      
                     
                         
                     
                      
                     um 
                   
                 
               
             
           
         
       
     
         [0030]    The distance W N1  between the N+ implant region  111  in the N-well  11  and the edge of N-well  11  satisfies the following relationship: 
         [0000]    
       
         
           
             
               
                 
                   
                     W 
                     
                       N 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   &gt; 
                   
                     
                       [ 
                       
                         
                           
                             2 
                              
                             
                               ɛ 
                               s 
                             
                           
                           q 
                         
                          
                         
                           1 
                           
                             N 
                             D 
                           
                         
                          
                         
                           
                             ( 
                             
                               
                                 V 
                                 BJ 
                               
                               - 
                               
                                 V 
                                 A 
                               
                             
                             ) 
                           
                           
                             ( 
                             
                               1 
                               + 
                               
                                 
                                   N 
                                   D 
                                 
                                 
                                   N 
                                   A 
                                 
                               
                             
                             ) 
                           
                         
                       
                       ] 
                     
                     
                       1 
                       2 
                     
                   
                   ≈ 
                     
                    
                   
                     
                       [ 
                       
                         
                           
                             
                               
                                 
                                   2 
                                   × 
                                   1.04 
                                   × 
                                   
                                     10 
                                     
                                       - 
                                       12 
                                     
                                   
                                 
                                 
                                   1.6 
                                   × 
                                   
                                     10 
                                     
                                       - 
                                       19 
                                     
                                   
                                 
                               
                               × 
                               
                                 1 
                                 
                                   3 
                                   × 
                                   
                                     10 
                                     17 
                                   
                                 
                               
                               × 
                             
                           
                         
                         
                           
                             
                               20 
                               
                                 ( 
                                 
                                   1 
                                   + 
                                   
                                     
                                       3 
                                       × 
                                       
                                         10 
                                         17 
                                       
                                     
                                     
                                       10 
                                       15 
                                     
                                   
                                 
                                 ) 
                               
                             
                           
                         
                       
                       ] 
                     
                     
                       1 
                       2 
                     
                   
                 
               
             
             
               
                 
                   = 
                     
                    
                   
                     1.7 
                     × 
                     
                       10 
                       
                         - 
                         6 
                       
                     
                      
                     
                         
                     
                      
                     cm 
                   
                 
               
             
             
               
                 
                   = 
                     
                    
                   
                     0.017 
                      
                     
                         
                     
                      
                     um 
                   
                 
               
             
           
         
       
     
         [0031]    Furthermore, a PMOS transistor is provided to further illustrate this embodiment.  FIG. 3  is a plan view showing a PMOS transistor according to another embodiment;  FIG. 4  is a cross-sectional view taken along line CC in  FIG. 3 . The differences from  FIGS. 1A and 1B  include that two P+ implant regions are further formed in the N-well  11 , a polysilicon gate  114  is further formed on the N-well  11 , the polysilicon gate  114  is formed between the two P+ implant regions. 
         [0032]    In one embodiment, for the PMOS transistor illustrated in  FIG. 3  and  FIG. 4 , the distance W N2  between the P+ implant region in the N-well  11  and the edge of the N-well  11  satisfies the following relationship: 
         [0000]    
       
         
           
             
               W 
               
                 N 
                  
                 
                     
                 
                  
                 2 
               
             
             &gt; 
             
               
                 [ 
                 
                   
                     
                       2 
                        
                       
                         ɛ 
                         s 
                       
                     
                     q 
                   
                    
                   
                     1 
                     
                       N 
                       D 
                     
                   
                    
                   
                     
                       ( 
                       
                         
                           V 
                           BJ 
                         
                         - 
                         
                           V 
                           A 
                         
                       
                       ) 
                     
                     
                       ( 
                       
                         1 
                         + 
                         
                           
                             N 
                             D 
                           
                           
                             N 
                             A 
                           
                         
                       
                       ) 
                     
                   
                 
                 ] 
               
               
                 1 
                 2 
               
             
           
         
       
     
         [0033]    In another embodiment, the distance between the edge of the N-well  11  and any device in the N-well  11  is greater than a pre-determined value and the pre-determined value is equal to 
         [0000]    
       
         
           
             
               
                 [ 
                 
                   
                     
                       2 
                        
                       
                         ɛ 
                         s 
                       
                     
                     q 
                   
                    
                   
                     1 
                     
                       N 
                       D 
                     
                   
                    
                   
                     
                       ( 
                       
                         
                           V 
                           BJ 
                         
                         - 
                         
                           V 
                           A 
                         
                       
                       ) 
                     
                     
                       ( 
                       
                         1 
                         + 
                         
                           
                             N 
                             D 
                           
                           
                             N 
                             A 
                           
                         
                       
                       ) 
                     
                   
                 
                 ] 
               
               
                 1 
                 2 
               
             
             . 
           
         
       
     
         [0034]    In this embodiment, since the N-well is surrounded by the P-type substrate and the carrier concentration of the P-type substrate is lower than the carrier concentration of the P-well by several orders of magnitude, as a result, the reverse breakdown voltage between P-well and N-well is increased. Additionally, in this embodiment, the P-type substrate can be applied to separate the N-well and the P-well, the manufacturing process of the integrated circuit does not need to be changed and associated cost is reduced. 
         [0035]      FIG. 5  is a flow chart showing a method for increasing the reverse breakdown voltage between P-well and N-well according to one embodiment. 
         [0036]    In step  51 , a P-type substrate is provided. 
         [0037]    In step  52 , an N-well and a P-well are formed in and separated by the P-type substrate. In one embodiment, an N-well is first formed in the silicon substrate and a separation zone is delineated around the N-well. Then a P-well is formed in the silicon substrate with the separation zone separating the N-well and the P-well. In one embodiment, a P-well is first formed in the silicon substrate and a separation zone is delineated around the P-well. Then an N-well is formed in the silicon substrate with the separation zone separating the N-well and P-well. 
         [0038]    In this embodiment, since the N-well is surrounded by the P-type substrate and the carrier concentration of the P-type substrate is lower than the carrier concentration of the P-well by several orders of magnitude, as a result, the reverse breakdown voltage between the P-well and the N-well is increased. Additionally, in this embodiment, the P-type substrate can be applied to separate the N-well and the P-well, the manufacturing process of the integrated circuit does not need to be changed and associated cost is reduced. 
         [0039]    In another embodiment, the P-type substrate can be replaced by an N-type substrate, in this case, the P-well is surrounded by the N-type substrate and the carrier concentration of the N-type substrate is lower than the carrier concentration of the N-well by several orders of magnitude, as a result, the reverse breakdown voltage between P-well and N-well is increased. Additionally, in this embodiment, the P-type substrate can be applied to separate the N-well and the P-well, the manufacturing process of the integrated circuit does not need to be changed and associated cost is reduced. 
         [0040]      FIG. 6  is a flow chart showing a method for increasing the reverse breakdown voltage between P-well and N-well according to another embodiment. Based on the embodiments as illustrated in  FIG. 5 , in order to further improve the performance, in step  52 , the distance W p  between N-well and P-well is calculated as follows: 
         [0000]    
       
         
           
             
               W 
               P 
             
             &gt; 
             
               
                 [ 
                 
                   
                     
                       2 
                        
                       
                         ɛ 
                         s 
                       
                     
                     q 
                   
                    
                   
                     1 
                     
                       N 
                       A 
                     
                   
                    
                   
                     
                       ( 
                       
                         
                           V 
                           BJ 
                         
                         - 
                         
                           V 
                           A 
                         
                       
                       ) 
                     
                     
                       ( 
                       
                         1 
                         + 
                         
                           
                             N 
                             A 
                           
                           
                             N 
                             D 
                           
                         
                       
                       ) 
                     
                   
                 
                 ] 
               
               
                 1 
                 2 
               
             
           
         
       
     
         [0041]    In particular, ε s  is the silicon absolute permittivity, q is the electron charge, N A  is the doping concentration of the P-type substrate, N D  is the doping concentration of the N-well, V BJ  is the built-in potential of the PN junction formed by the N-well and the P-type substrate, V A  is the potential difference between the P-well and the N-well. 
         [0042]    In this embodiment, in order to apply voltage on the N-well  11  and the P-well  12 , the following step can be included after the step  52 : 
         [0043]    In step  53 , an N+ implant region is formed in the N-well and a P+ implant region is formed in the P-well. 
         [0044]    In one embodiment, in the step  53 , the distance W N1  between the N+ implant region in the N-well and the edge of N-well is calculated according to the formula: 
         [0000]    
       
         
           
             
               W 
               
                 N 
                  
                 
                     
                 
                  
                 1 
               
             
             &gt; 
             
               
                 [ 
                 
                   
                     
                       2 
                        
                       
                         ɛ 
                         s 
                       
                     
                     q 
                   
                    
                   
                     1 
                     
                       N 
                       D 
                     
                   
                    
                   
                     
                       ( 
                       
                         
                           V 
                           BJ 
                         
                         - 
                         
                           V 
                           A 
                         
                       
                       ) 
                     
                     
                       ( 
                       
                         1 
                         + 
                         
                           
                             N 
                             D 
                           
                           
                             N 
                             A 
                           
                         
                       
                       ) 
                     
                   
                 
                 ] 
               
               
                 1 
                 2 
               
             
           
         
       
     
         [0045]    Furthermore, forming a PMOS transistor is provided to further illustrate this embodiment. As illustrated in  FIG. 6 , in order to form a PMOS transistor, the following steps can be included before the step  53 : 
         [0046]    In step  54 , a polysilicon gate is formed on the N-well. 
         [0047]    In step  55 , two P+ implant regions are formed in the N-well and the polysilicon gate is located in an area between the two P+ implant regions. 
         [0048]    It is noted that, there is no strict timing relationship between the step  55  and the step  53 . 
         [0049]    In one embodiment, in the step  55 , the distance W N2  between the P+ implant region in the N-well and the edge of the N-well satisfies the following relationship: 
         [0000]    
       
         
           
             
               W 
               
                 N 
                  
                 
                     
                 
                  
                 2 
               
             
             &gt; 
             
               
                 [ 
                 
                   
                     
                       2 
                        
                       
                         ɛ 
                         s 
                       
                     
                     q 
                   
                    
                   
                     1 
                     
                       N 
                       D 
                     
                   
                    
                   
                     
                       ( 
                       
                         
                           V 
                           BJ 
                         
                         - 
                         
                           V 
                           A 
                         
                       
                       ) 
                     
                     
                       ( 
                       
                         1 
                         + 
                         
                           
                             N 
                             D 
                           
                           
                             N 
                             A 
                           
                         
                       
                       ) 
                     
                   
                 
                 ] 
               
               
                 1 
                 2 
               
             
           
         
       
     
         [0050]    In another embodiment, the distance between the edge of the N-well  11  and any device in the N-well  11  is greater than a pre-determined value and the pre-determined value is equal to 
         [0000]    
       
         
           
             
               
                 [ 
                 
                   
                     
                       2 
                        
                       
                         ɛ 
                         s 
                       
                     
                     q 
                   
                    
                   
                     1 
                     
                       N 
                       D 
                     
                   
                    
                   
                     
                       ( 
                       
                         
                           V 
                           BJ 
                         
                         - 
                         
                           V 
                           A 
                         
                       
                       ) 
                     
                     
                       ( 
                       
                         1 
                         + 
                         
                           
                             N 
                             D 
                           
                           
                             N 
                             A 
                           
                         
                       
                       ) 
                     
                   
                 
                 ] 
               
               
                 1 
                 2 
               
             
             . 
           
         
       
     
         [0051]    In this embodiment, since the N-well is surrounded by the P-type substrate and the carrier concentration of the P-type substrate is lower than the carrier concentration of the P-well by several orders of magnitude, as a result, the reverse breakdown voltage between P-well and N-well is increased. Additionally, this embodiment only needs to apply the P-type substrate to separate the N-well and the P-well, the manufacturing process of the integrated circuit does not needs to be changed and associated cost is reduced. 
         [0052]    While certain embodiments have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the systems and methods described herein should not be limited based on the described embodiments Rather, the systems and methods described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.