Abstract:
A current-to-current impedance converter re-circulates the driver transistor collector current back into the output current path to generate an error current that has two portions including a DC offset portion and a second order in 1/β portion. Since the error current has no first order in 1/β portion, the current-to-current ronverter exhbits very low distortion.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to current-to-current impedance converter circuits, and more particularly to a current-to-current converter circuit and method to achieve very low distortion. 
     2. Description of the Prior Art 
     Current-to-current impedance converter circuits are intended to output a current from a high impedance node that is equal in magnitude to a current input into a separate low impedance node. The potential at this input node is ideally a circuit common mode voltage. Such impedance converter circuits are problematic in that there is presently no known way to implement such a device without the current path proceeding through collector-emitter junctions of transistors. 
     Conventional current-to-current converter circuit architectures therefore generate an output current that is distorted by errors due to variation of the finite gain (β) of the transistors with collector current. In the prior art, these errors are proportional to 1/β. Because β is a function of collector current, and hence, input signal level, distortion from these error terms will dominate the overall distortion of the circuit. 
     In view of the foregoing, a need exists for a technique that mitigates the effects of β on the foregoing error terms, and thus the error current to provide a current-to-current impedance converter that exhibits very low distortion. 
     SUMMARY OF THE INVENTION 
     To meet the above and other objectives, the present invention provides a current-to-current impedance converter that exhibits very low distortion due to ( effects. 
     According to one embodiment, a current-to-current impedance converter is implemented with a class ‘AB’ output stage such that the driver transistor collector currents are circulated through suitably chosen output current mirrors along with the collector currents of the class ‘AB’ output stage output transistors. The total collector current is folded around by the suitably chosen current mirrors, and the bias currents are subtracted, leaving the output current. The current mirrors can be implemented using any well-known mirror architecture and can be implemented to have any suitable gain so long as the selected gain is common to all the current mirrors. The resulting error current includes a DC offset portion and only a second order in 1/β portion, thereby providing a significant improvement over conventional current-to-current impedance converters that have a DC offset portion and a first order in 1/β portion. 
     According to another embodiment, a current-to-current impedance converter is implemented with a class ‘AB’ output stage such that the driver transistor collectors are connected to the input current summing node of the class ‘AB’ output stage output transistors. The driver collector currents here are also forced to proceed out through suitably chosen identical current mirrors, where error terms that are first order in 1/β are subtracted and cancelled at an output summing node. The resulting error current again includes a DC offset portion and only a second order in 1/β portion. 
     Another embodiment implements a current-to-current impedance converter using a class ‘AB’ output stage such that the driver transistor collectors are connected to their respective source and sink output transistor collectors. The collector currents associated with the source output transistor and its respective driver transistor are folded around a first current path by a first current mirror while the collector currents associated with the sink output transistor and its respective driver transistor are folded around a second current path by a second current mirror. The currents in the first and second current paths are combined at a common output node to generate an output current in which the resulting error current includes a DC offset portion and only a second order in 1/β portion, thereby providing a significant improvement over conventional current-to-current impedance converters that have a DC offset portion and a first order in 1/β portion. 
     In one aspect of the invention, a current-to-current impedance converter is implemented that exhibits very low distortion. 
     In another aspect of the invention, a current-to-current impedance converter is implemented that accommodates a plurality of applications and processes used to fabricate the converter. 
     In yet another aspect of the invention, a current-to-current impedance converter can be implemented that selectively minimizes the effects of Miller capacitance at the driver stage. 
     In still another aspect of the invention, a current-to-current impedance converter can be implemented that selectively minimizes the effects of driver transistor collector-substrate capacitance. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other aspects and features and many of the attendant advantages of the present invention will be readily appreciated, as the same become better understood by reference to the following detailed description, when considered in connection with the accompanying drawings in which like reference numerals designate like parts throughout the figures thereof, and wherein: 
     FIG. 1 is a schematic diagram illustrating a conventional current-to-current impedance converter circuit that is known in the prior art; 
     FIG. 2 is a schematic diagram illustrating a current-to-current impedance converter according to one embodiment of the present invention; and 
     FIG. 3 is a diagram illustrating a current-to-current impedance converter according to another embodiment of the present invention. 
    
    
     While the above-identified drawing figures set forth particular embodiments, other embodiments of the present invention are also contemplated, as noted in the discussion. In all cases, this disclosure presents illustrated embodiments of the present invention by way of representation and not limitation. Numerous other modifications and embodiments can be devised by those skilled in the art which fall within the scope and spirit of the principles of this invention. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Current-to-current impedance converter circuits are intended to output a current from a high impedance node that is equal in magnitude to a current input into a separate low impedance node, as stated herein before. The potential of this input node is ideally a circuit common mode voltage. In this regard, there is no presently known method or circuit architecture to implement such a device without the current path proceeding through collector-emitter junctions of transistors, also as stated herein before. The output current therefore, is distorted by errors due to the variation of the finite gain (β) of the transistors with variations in collector current. 
     FIG. 1 is a schematic diagram illustrating a conventional current-to-current impedance converter circuit  10  that is known in the prior art. The impedance converter circuit  10  is implemented via a class ‘AB’ amplifier output stage that is connected to a plurality of current mirrors (enumerated as  12  and  14 ). In the prior art current-to-current impedance converter circuit  10 , the output current includes an additional error term that is proportional to 1/β. Because β is a function of collector current, and hence, input signal level, distortion from these error terms will dominate the overall distortion of the circuit  10 . With continued reference now to FIG. 1, the output error current associated with the conventional current-to-current impedance converter circuit  10  can be shown to be: 
     
       
         
           I 
           OUT 
           +a=b 
         
       
     
     
       
         
           I 
           OUT 
           =b−a 
         
       
     
     
       
         
           I 
           IN 
           +p=q 
         
       
     
     
       
         
           I 
           IN 
           =q−p 
         
       
     
     
       
           I   OUT =[β p /(β p +1)]· i   e4 −[β n /(β n +1)]· i   e2   
       
     
     
       
         
           I 
           IN 
           =i 
           e4 
           −i 
           e2 
         
       
     
                   error   =         I   OUT     -     I   IN       =                    [       β   p     /     (       β   p     +   1     )       ]     ·     i   e4       -     i   e4     -       [       β   n     /     (       β   n     +   1     )       ]     ·     i   e2       -     i   e2                     =                    [       β   p     /     (       β   p     +   1     )       ]     ·     i   e4       -       [       (       β   p     +   1     )     /     (       β   p     +   1     )       ]          i   e4       -                                [       β   n     /     (       β   n     +   1     )       ]     ·       i   e2          [       (       β   n     +   1     )     /     (       β   n     +   1     )       ]       ·     i   e2                     =                    -     i   e4       /     (       β   p     +   1     )       +       i   e2     /     (       β   n     +   1     )           ,     and                 therefore                                 error current≡ I   OUT   −I   IN   =−I   IN /(β p +1)+[β p /(β p +1)−β n /(β n +1)] I   e2   (1) 
     where, for large β, and a bias current I: 
     
       
           i   e2   ≈I   IN /2{[1+4( I/I   IN ) 2 ] ½ −1},  
       
     
     and for large β, the last term in equation (1) is approximately zero, and contributes little additional distortion. 
     FIG. 2 is a schematic diagram illustrating a current-to-current impedance converter  100  according to one embodiment of the present invention. The impedance converter  100  is implemented using a class ‘AB’ output stage that is coupled to a sink current mirror  104  and source current mirror  106 . The output stage includes an upper or source NPN output transistor Q 2  and a lower or sink PNP output transistor Q 4 . The upper output transistor Q 2  is driven via a PNP driver transistor Q 1 . The lower output transistor Q 4  is driven via an NPN driver transistor Q 3 . The current mirrors  104  and  106  can be implemented using any well-known mirror architectures having any suitable gain so long as the selected gain is common to both current mirrors  104  and  106 . The impedance converter driver transistor Q 1 , Q 3  collector currents can be seen to be re-circulated back into the output current paths  102  and  103  respectively. The driver transistor Q 1 , Q 3  collector currents are circulated through the output current mirrors  104 ,  106  along with the collector currents of output transistors Q 2  and Q 4  themselves. The total collector current is then folded around by the suitably chosen current mirrors  104 ,  106 , and the bias currents are subtracted, leaving the output current I ouT  flowing in common current path  110 . It can be seen that the collector currents flowing in Q 1  and Q 4  folded around by current mirror  104  where they are combined in current path  102 ; and the collector currents flowing in Q 2  and Q 3  are folded around by current mirror  106  where they are combined in current path  103 . The total output current is then generated in a common output current path  110  where the error current is determined as: 
     
       
           I   OUT =(β p /(β p +1))· i   e4 +(β p /(β p +1)· I −[(β p   ·i   e2 )/(β p +1)(β n +1)]−(β n /(β n +1))· i   e2 −(β n /(β n +1))· I +[(β n   ·i   e4 )/(β n +1)(β p +1)] 
       
     
     Since each static current source I  112  is a constant and will contribute to a DC offset, it can be ignored, and 
     
       
           I   OUT =(β p /(β p +1)· i   e4 −[(β p   ·i   e2 )/(β p +1)(β n +1)]−(β n /(β n +1)· i   e2 +[(β n   ·i   e4 )/(β n +1)(β p +1)], 
       
     
     and then 
     
       
           I   OUT =( i   e4   −i   e2 )(β p ·β n +β p +β n )/[(β p +1)(β n +1)] 
       
     
     
       
           I   OUT   =I   IN ·(β p ·β n +β p +β n )/μ(β p +1)(β n +1)] 
       
     
     
       
           I   OUT   =I   IN   −I   IN /(β p +1)(β n +1), 
       
     
     and the error is 
     
       
           I   OUT   −I   IN   =I   IN /(β p +1)(β n +1) 
       
     
     The error current is then: 
     
       
         error current=− I   IN /(β p +1)(β n +1)+ I[β   p /(β p +1)−β n /(β n +1)]  (2) 
       
     
     where the second term is a DC offset as set forth above and the error currents are now second order in 1/β, a significant improvement over the prior art error current as set forth in equation (1). 
     FIG. 3 is a diagram illustrating a current-to-current impedance converter  200  according to another embodiment of the present invention. Again, the converter  200  is implemented via a class ‘AB’ output stage that is coupled to a plurality of suitably chosen current mirrors  206 ,  208 . The current mirrors  206 ,  208  can be implemented using any well-known mirror architecture and can have a unity gain or can have a gain other than unity so long as the selected gain is common to both current mirrors  206 ,  208 . The impedance converter driver transistor Q 1  and Q 3  collectors can be seen to be connected to a common input current summing node  202  along with the emitters of the output transistors Q 2  and Q 4 . The driver transistor Q 1 , Q 3  collector currents are also forced to proceed out through the current mirrors  206 ,  208 , where again, error terms that are first order in 1/β are subtracted and cancelled at the common output summing node  204 . The output current error is then: 
     
       
         
           a−I 
           OUT 
           =b 
         
       
     
     
       
         
           I 
           OUT 
           =b−a 
         
       
     
     
       
         
           p+q+I 
           IN 
           =r 
         
       
     
     
       
         
           I 
           IN 
           =r−p−q 
         
       
     
     error=I OUT −I IN , where 
     
       
           I   OUT =[β p /(β p +1)]· i   e4 −[β n /(β n +1)]· i   e2   
       
     
     and 
     
       
           I   IN   =i   e4   −i   e2 −{[β p /(β p +1)]( I−i   e2 /(β n +1))}+{[β n /(β n +1)]( I−i   e4 /(β p +1))} 
       
     
     The error is then: 
     
       
         error=[ i   e2   −i   e4   +I (β p −β n )]/[(β p +1)(β n +1)] 
       
     
     where, for large β,            i   e2     -     i   e4       ≈       -     I   IN       +     I        (       1     β   p       -     1     β   n         )       +       i   e2          (     1     β   n       )       -       i   e4          (     1     β   p       )                                
     The error is, after keeping terms that are 2 nd  order and 1 st  order in 1/β times the signal and bias current, respectively: 
     
       
         error current≈− I   IN /[(β p +1)(β n +1)]+ I {(β p −β n )/([(β p +1)(β n +1)]}  (3) 
       
     
     where again, the second term is a DC offset, and the error currents are now second order in 1/β, a significant improvement over the prior art. 
     The present low distortion current-to-current impedance converter circuits  100 ,  200  can accommodate a wide variety of applications and processing and fabrication technologies. The impedance converter circuit  200 , for example, can be used to minimize the well-known Miller effects, but at the expense of requiring the input current source to now also drive the collector-substrate capacitance of the driver transistors Q 1  and Q 3 . This collector-substrate capacitance may combine with the input impedance of the output transistors Q 2  and Q 4  to increase peaking at the upper limit of the circuit  200  bandwidth. The present low distortion current-to-current impedance converter circuit  100  presents neither of the foregoing issues, but now has a Miller effect at the driver (Q 1 , Q 3 ) stage. As stated above therefore, process and application specifications will determine where the driver collector impedance is to be connected within the output circuit comprising transistors Q 2  and Q 4 . 
     In view of the above, it can be seen the present invention presents a significant advancement in the art of current-to-current impedance converter circuit technology. Further, this invention has been described in considerable detail in order to provide those skilled in the data communication art with the information needed to apply the novel principles and to construct and use such specialized components as are required. In view of the foregoing descriptions, it should further be apparent that the present invention represents a significant departure from the prior art in construction and operation. However, while particular embodiments of the present invention have been described herein in detail, it is to be understood that various alterations, modifications and substitutions can be made therein without departing in any way from the spirit and scope of the present invention, as defined in the claims which follow. For example, although various embodiments have been presented herein with reference to particular transistor types, the present inventive structures and characteristics are not necessarily limited to particular transistor types or sets of characteristics as used herein. It shall be understood the embodiments described herein above can easily be implemented using many diverse transistor types so long as the combinations achieve a low distortion current-to-current impedance converter according to the inventive principles set forth herein above.