Abstract:
In an automatic gain control type demodulation apparatus, an orthogonal demodulation circuit receives an analog input signal to generate a first I-signal and a second Q-signal orthogonal to each other. An analog/digital converter circuit performs an analog/digital conversion operation upon the first I-signal and the first Q-signal to generate a second I-signal and a second Q-signal. An automatic gain control (AGC) circuit suppresses amplitude errors of the second I-signal and the second Q-signal to generate a third I-signal and a third Q-signal. A complex multiplier removes frequency and phase offset components of a carrier wave included in the third I-signal and the third Q-signal to generate a fourth I-signal and a fourth Q-signal. A phase detector detects first and second amplitude errors of the fourth I-signal and the fourth Q-signal, respectively, with respect to one normal signal point and calculates a phase error of the fourth I-signal and the fourth Q-signal. A numerical control oscillator converts the phase error into first and second angle signals orthogonal to each other. The AGC circuit controls the amplitude errors of the second I-signal and the second Q-signal in accordance with the first and second amplitude errors and the first and second angle signals.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an automatic gain control (AGC) type demodulation apparatus in a digital radio communication system. 
     2. Description of the Related Art 
     A prior art AGC type demodulation apparatus is generally constructed by an orthogonal demodulation circuit for receiving an analog input signal to generate a first I-signal (I-axis component or I-channel) and a first Q-signal (Q-axis component or Q-channel) orthogonal to each other. An analog/digital (A/D) converter circuit performs an A/D conversion operation upon the first I-signal and the first Q-signal to generate a second I-signal and a second Q-signal. A first AGC circuit suppresses the difference in amplitude between the second I-signal and the second Q-signal to generate a third I-signal and a third Q-signal. A complex multiplier rotates the third I-signal and the third Q-signal by a phase offset angle to remove the frequency and phase offset components of a carrier wave included in the third I-signal and Q-signal to generate a fourth I-signal and a fourth Q-signal. In this case, the phase offset angle is obtained by a loop circuit formed by a phase detector, a low-pass filter and a numerical control oscillator. A second AGC circuit compensates for the difference in amplitude between the fourth I-signal and the fourth Q-signal and one normal signal point in accordance with one amplitude error of the fourth I-signal and the fourth Q-signal with respect to one normal signal point. This will be explained later in detail. 
     In the prior art AGC-type demodulation apparatus however, an accurate automatic gain control cannot be expected. As a result, the I-signal and Q-signal regenerated by the second AGC circuit still show a circular locus around the normal signal point. In addition, since the combination of the two AGC circuits is large in size, the AGC demodulation apparatus is increased in size. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide an AGC-type demodulation apparatus capable of an accurate automatic gain control. 
     Another object is to decrease an AGC-type demodulation apparatus in size. 
     According to the present invention, in an AGC-type demodulation apparatus, an orthogonal demodulation circuit receives an analog input signal to generate a first I-signal and a first signal orthogonal to each other. An A/D converter circuit performing an A/D conversion operation upon the first I-signal and the first Q-signal to generate a second I-signal and a second Q-signal. An automatic gain control (AGC) circuit suppresses amplitude errors of the second I-signal and the second Q-signal to generate a third I-signal and a third Q-signal. A complex multiplier removes frequency and phase offset components of a carrier wave included in the third I-signal and the third Q-signal to generate a fourth I-signal and a fourth Q-signal. A phase detector detects first and second amplitude errors of the fourth I-signal and the fourth Q-signal, respectively, with respect to one normal signal point and calculates a phase error of the fourth I-signal and the fourth Q-signal. A numerical control oscillator converts the phase error into first and second angle signals orthogonal to each other. The AGC circuit controls the amplitude errors of the second I-signal and the second Q-signal in accordance with the first and second amplitude errors and the first and second angle signals. Thus, a single AGC circuit is provided in the AGC-type demodulation apparatus. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein: 
     FIG. 1 is a block circuit diagram illustrating a prior art AGC-type demodulation apparatus; 
     FIG. 2A is a diagram for explaining the operation of the AGC circuit  17  of FIG. 1; 
     FIG. 2B is a diagram for explaining the operation of the complex multiplier of FIG. 1; 
     FIG. 2C is a diagram for explaining the operation of the AGC circuit  22  of FIG. 1; 
     FIG. 3 is a diagram illustrating a constellation of a four-phase QPSK where the signals I 4  and Q 4  of the demodulation apparatus are illustrated; 
     FIG. 4 is a detailed block circuit diagram of the AGC circuit  17  of FIG. 1; 
     FIG. 5 is a detailed block circuit diagram of the low-pass filter of FIG. 4; 
     FIG. 6 is a detailed circuit diagram of the complex multiplier, the phase detector, the low-pass filter, and the numerical control oscillator of FIG. 1; 
     FIG. 7 is a detailed circuit diagram of the AGC circuit  72  of FIG. 1; 
     FIG. 8 is a block circuit diagram illustrating an embodiment of the AGC-type demodulation apparatus according to the present invention; 
     FIG. 9A is a diagram for explaining the operation of the AGC circuit of FIG. 8; 
     FIG. 9B is a diagram for explaining the operation of the complex multiplier of FIG. 8; 
     FIG. 10 is a detailed block circuit diagram of the AGC circuit of FIG. 8; 
     FIG. 11 is a diagram for explaining the complex multiplier of FIG. 10; 
     FIG. 12 is a block diagram of the low-pass filter of FIG. 10; 
     FIG. 13 is a block circuit diagram illustrating a modification of the AGC circuit of FIG. 10; and 
     FIG. 14 is a circuit diagram where the complex multipliers of FIGS. 8 and 13 are combined into a single complex multiplier. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before the description of the preferred embodiments, a prior art AGC-type demodulation apparatus will be explained with reference to FIGS. 1,  2 A,  2 B,  2 C,  3 ,  4 ,  5 ,  6  and  7 . 
     In FIG. 1, an orthogonal demodulation system is semi-coherent. Also, an input modulated signal is an orthogonal modulation signal of phase shift keying (PSK) or quadrature amplitude modulation (QAM) and its orthogonal components are called an I-axis component (or I-channel) signal and a Q-axis component (Q-channel) signal. 
     An intermediate frequency (IF) signal is supplied from a receiver (not shown) to multipliers  11  or  12 . The multiplier  11  multiplies the IF signal by a carrier wave signal from an oscillator  13 , and the multiplier  12  multiplies the IF signal by a π/2-shifted carrier wave signal from a π/2 phase shifter  14  which also receives the carrier wave signal from the oscillator  13 . In this case, note that the frequency of the oscillator  13  does not coincide with that of the frequency of a carrier wave included in the IF signal, so that the multipliers  11  and  12  generate semi-coherent baseband signals I 0  and Q 0 , respectively. 
     Analog/digital converters  15  and  16  perform analog/digital conversions upon the semi-coherent baseband signals I 0  and Q 0  to generate digital signals I 1  and Q 1 , respectively, which are supplied to an AGC circuit  17 . The AGC circuit  17  suppresses the difference in amplitude between the signals I 1  and Q 1 . That is, as indicated by a dotted line in FIG. 2A, the signals I 1  and Q 1  generally have an elliptical locus. Therefore, the AGC circuit  17  changes the elliptical locus of the signals I 1  and Q 1  to a circular locus of signals I 2  and Q 2  as indicated by a solid line in FIG.  2 A. The AGC circuit  17  will be explained later in detail. 
     The signals I 2  and Q 2  are supplied to a complex multiplier  18  for removing the frequency and phase offset components of a carrier wave included in the signals I 2  and Q 2 . The complex multiplier  18  rotates the signals I 2  and Q 2  by a phase offset angle θ to generate signals I 3  and Q 3  as shown in FIG.  2 B. The phase offset angle θ is obtained by a phase detector  19 , a low-pass filter  20  and a numerical control oscillator  21 , which will be explained later in detail. 
     The signals I 3  and Q 3  are supplied to an AGC circuit  22  for compensating for the difference in amplitude between the signals I 3  and Q 3  and one of normal signal points (0, 0), (0, 1), (1, 0) and (1, 1) as shown in FIG.  2 C. Note that FIG. 2C shows a constellation of a four-phase PSK (QPSK) where four normal signal points (0, 0), (0, 1), (1, 0) and (1, 1) are illustrated. The AGC circuit  22  will be explained later in detail. 
     If the AGC circuit  17  cannot completely suppress the difference in amplitude between the signals I 1  and Q 1 , the signals I 4  and Q 4  output from the AGC circuit  22  may show a circular locus around one of the normal signal points (0, 0), (0, 1), (1, 0) and (1, 1) as shown in FIG.  3 . In this case, the radius of the circular locus is equal to the difference in amplitude between the signals I 2  and Q 2  which is not zero. 
     In FIG. 4, which is a detailed block circuit diagram of the AGC circuit  17  of FIG. 1, an absolute calculating circuit  171  calculates an absolute value |I 1 | of the signal I 1 , and an absolute calculating circuit  172  calculates an absolute value |Q 1 | of the signal Q 1 . A subtracter  173  compares the absolute value |I 1 | with the absolute value |Q 1 |. That is, the subtracter  173  generates an output signal showing a value |I 1 |−|Q 1 |. A low-pass filter  174  accumulates the polarity of the output signal of the subtracter  173  to generate a sum signal S. Also, a multiplier  175  multiplies the signal Q 1  by the sum signal S of the low-pass filter  174 . 
     As illustrated in FIG. 5, the low-pass filter  174  is constructed by a flip-flop circuit  1741  for generating the sum signal S and an adder  1742 . In this case, the adder  1742  adds the output signal of the subtracter  173  to the sum signal S of the flip-flop circuit  1741  so that the sum signal S of the adder  1742  is again stored in the flip-flop circuit  1741 . 
     Thus, in FIG. 4, when |I 1 |≧|Q 1 |, the value of sum signal S of the low-pass filter  174  is increased so as to increase the magnitude of the signal Q 2 . On the other hand, when |I 1 |&lt;|Q 1 |, the value of sum signal S of the low-pass filter  174  is decreased so as to decrease the magnitude of the signal Q 2 . As a result, the magnitude of the signal Q 2  is brought close to that of the signal I 2  (=I 1 ). 
     FIG. 6 is a detailed circuit diagram of the complex multiplier  18 , the phase detector  19 , the low-pass filter  20  and the numerical control oscillator  21 . 
     The complex multiplier  18  receives angle signals cosθ and sinθ from the numerical control oscillator  21 . The complex multiplier  18  is constructed by multipliers  181  and  182  for multiplying the signal I 2  by the angle signals cosθ and sinθ, respectively, and multipliers  183  and  184  for multiplying the signal Q 2  by the angle signals cosθ and sin θ, respectively. A subtracter  185  subtracts the output signal (=Q 2  sinθ) of the multiplier  184  from the output signal (=I 2  cosθ) of the multiplier  181  to obtain 
     
       
           I   3   =I   2  cos θ− Q   2  sin θ. 
       
     
     Also, an adder  186  adds the output signal (=Q 2  cosθ) of the multiplier  183  to the output signal (=I 2  sinθ) of the multiplier  182  to obtain 
     
       
           Q   3   =I   2  sin θ+ Q   2  cos θ. 
       
     
     Thus, the signals I 2  and Q 2  are rotated by an angle θ to obtain the signals I 3  and Q 3 . 
     The phase detector  19  is constructed by error detectors  191  and  192  for detecting amplitude errors of the signals I 3  and Q 3 , respectively, with respect to one normal signal point, to thereby generate amplitude errors E i  and E q , respectively. For example, when the signal I 3  (Q 3 ) is shifted in a positive side from the corresponding value of the normal signal point, the amplitude error E i  (E q ) is negative. On the other hand, when the signal I 3  (Q 3 ) is shifted in a negative side from the corresponding value of the normal signal point, the amplitude error E i  (E q ) is positive. A multiplier  193  multiplies the amplitude error E i  by a most significant bit (MSB) D q  of the signal Q 3 , and a multiplier  194  multiplies the amplitude error E q  by a most significant bit (MSB) D i  of the signal I 3 . Then, a subtracter  195  subtracts the output signal (=D i ·E q ) of the multiplier  194  from the output signal (=D q ·E i ) of the multiplier  193 , to obtain a phase error detection P d1  by 
     
       
           P   d1   =D   q   ·E   i   −D   i   ·E   q . 
       
     
     The low-pass filter  20  is generally constructed by a secondary lag lead filter which includes multipliers  201  and  202  for multiplying the phase error detection signal P d1  by definite values α and β, respectively, an adder  203 , a flip-flop circuit  204  and an adder  205 . In this case, the adder  203  adds the output signal (=α·P d1 ) of the multiplier  201  to the output signal of the flip-flop circuit  204 , so that the addition result is again stored in the flip-flop circuit  204 . The adder  205  adds the output signal (=β·P d1 ) of the multiplier  202  to the output signal of the flip-flop circuit  204 . Thus, the low-pass filter  20  generates a phase error detection signal P d2  by 
     
       
           P   d2   =Σα·P   d1   +β·P   d2 . 
       
     
     As a result, a carrier wave regeneration loop is formed by the complex multiplier  18 , the phase detector  19 , the low-pass filter  20  and the numerical control oscillator  21 , so that a frequency offset can be compensated for. 
     The numerical control oscillator  21  is constructed by an integrator  211  for integrating the phase error detection signal P d2  to generate a frequency error signal F rq . The frequency error signal F rq  is supplied to angle signal converters  212  and  213  which generate angle signals cosθ and sinθ where θ=2πF rq . 
     In FIG. 7, which is a detailed circuit diagram of the AGC circuit  22  of FIG. 1, the AGC circuit  22  is constructed by a polarity determining circuit  221  for determining the polarity of the signal I 4 , a multiplier  222  for multiplying the error signal E i  by the polarity of the signal I 3  to generate an amplitude error signal E a , and for smoothing the amplitude error signal E a . In this case, since the difference in amplitude between the signals I 3  and Q 3  is suppressed, the polarity determining circuit  221  determines only the polarity of only one of the signals I 4  and Q 4 . The smoothed amplitude error signal is supplied to multipliers  224  and  225  which multiply the signals I 3  and Q 3  by the smoothed amplitude error signal. 
     In the AGC-type demodulation apparatus of FIG. 1, however, since the low-pass filter  174  uses only the polarity of the output signal of the subtracter  173 , an accurate automatic gain control cannot be expected. As a result, the regenerated signals I 4  and Q 4  still show a circular locus around the normal signal point as shown in FIG.  3 . 
     In addition, since the combination of the AGC circuits  17  and  22  are large in size, the AGC demodulation apparatus of FIG. 1 is increased in size. 
     In FIG. 8, which illustrates an embodiment of the present invention, the AGC circuits  17  and  22  of FIG. 1 are combined into an AGC circuit  23  which also receives the angle signals cosθ and sinθ from the numerical control oscillator  21  as the amplitude errors E i  and E q  from the phase detector  19 . The AGC circuit  23  suppresses the amplitude errors of the signals I 1  and Q 1  to generate signals I 2 ′ and Q 2 ′. That is, as indicated by a dotted line in FIG. 9A, the signals I 1  and Q 1  generally have an elliptical locus. Therefore, the AGC circuit  23  changes the elliptical locus of the signals I 1  and Q 1  to a circular locus of the signals I 2 ′ and Q 2 ′ as indicated by a solid line in FIG.  9 A. In this case, the radius of the signals I 2 ′ and Q 3 ′ is brought close to the radius of the normal signal points (0, 0), (0, 1), (1, 0) and (1, 1) as shown in FIG.  9 B. The AGC circuit  23  will be explained later in detail. 
     The signals I 2 ′ and Q 2 ′ are supplied to the complex multiplier  18  which rotates the signals I 2 ′ and Q 2 ′ by a phase offset angle θ to generate signals I 3 ′ and Q 3 ′ as shown in FIG.  9 B. The phase offset angle θ is obtained by the phase detector  19 , the low-pass filter  20  and the numerical control oscillator  21 . 
     In FIG. 10, which is a detailed block circuit diagram of the AGC circuit  23  of FIG. 8, polarity determining circuits  221 I and  221 Q for receiving the signals I 1  and Q 1  correspond to the polarity determining circuit  221  of FIG.  7 . Also, multipliers  222 I and  222 Q correspond to the multiplier  223  of FIG.  3 . Further, low-pass filters  223 I and  223 Q connected to the multipliers  224  and  225  correspond to the low-pass filter  223 . 
     Also, in the AGC circuit  23 , multipliers  2301 ,  2302 ,  2303 ,  2304 , an adder  2305  and a subtracter  2306  are provided to form a complex multiplier  18 A similar to that of the complex multiplier  18  of FIG.  6 . In this case, the multipliers  2301 ,  2302 ,  2303  and  2304  correspond to the multipliers  181 ,  182 ,  183  and  184 , respectively; the adder  2305  corresponds to the subtracter  185 ; and the subtracter  2306  corresponds to the adder  186 : Therefore, the complex multiplier  18 A rotates the error signals E i  and E q  by an opposite value of the phase offset angle θ, i.e., −θ. In more detail, the multipliers  2301  and  2302  multiply the signal E i  by the angle signals cosθ and sin θ, respectively, and the multipliers  2303  and  2304  multiply the signal E q  by the angle signals cosθ and sinθ, respectively. The adder  2305  adds the output signal (=E q  sin θ) of the multiplier  2304  from the output signal (=E i  cos θ) of the multiplier  2301  to obtain 
     
       
           E   i   ′=E   i  cos θ+ E   q  sin θ. 
       
     
     Also, a subtracter  2306  subtracts the output signal (=E q  cos θ) of the multiplier  2303  from the output signal (=E q  sin θ) of the multiplier  2302  to obtain 
     
       
           E   q   ′=−E   i  sin θ+ E   i  cos θ. 
       
     
     Thus, the signals E i  and E q  are rotated by an angle −θ to obtain the signals E i ′ and E q ′, as shown in FIG.  11 . 
     Since the error signals E i  and E q  include an accurate amplitude error in the signals I 3 ′ and Q 3 ′ after the phase rotation by an angle of θ, the error signals E i ′ and E q ′ include an accurate amplitude error in the signals I 2 ′ and Q 3 ′ before the phase rotation. Thus, as shown in FIG. 8A, the amplitude error included in the signals I 1  and Q 1  can be completely suppressed in the signals I 2 ′ and Q 2 ′. 
     In FIG. 10, the polarity signals obtained from the polarity determining circuits  221 I and  221 Q have to be synchronized with the error signals E i ′ and E q ′ from the complex multiplier  18 A. In order to comply with this requirement, delay circuits  2307 I and  2307 Q each having a delay time corresponding to a total delay time of the complex multiplier  18 , the phase detector  19 , the low-pass filter  20  and the numerical control oscillator  21  are provided between the polarity determining circuits  221 I and  221 Q and the multipliers  222 I and  222 Q. 
     In the AGC-type demodulation apparatus of FIG. 8, the error signals E i  and E q  (E i ′ and E q ′) are brought close to zero, thus carrying out an accurate AGC. If a 16-valued or more modulation system where the distance between signal points is much smaller is adopted, the characteristic of error rates can be further improved. 
     Each of the low-pass filters  223 I and  223 Q can be constructed by a low-pass filter as illustrated in FIG. 5 or the low-pass filter  20  of FIG.  6 . In the case of the low-pass filter  20  of FIG. 6, although the circuit configuration is large, the follow-up control characteristics for the fluctuation of amplitudes of the signals I 1  and Q 1  and the initial pull-in characteristics can be improved. Also, each of the low-pass filter  223 I and  223 Q can be constructed by a low-pass filter as illustrated in FIG.  12 . That is, in FIG. 12, a polarity determining circuit  1201  and an up/down counter  1202  are provided. When the polarity determined by the polarity determining circuit  1201  is positive, the content of the up/down counter  1202  is counted up. On the other hand, when the polarity determined by the polarity determining circuit  1201  is negative, the content of the up/down counter  1202  is counted down. 
     In FIG. 13, which illustrates a modification of the AGC circuit  23  of FIG. 10, the complex multiplier  18 A includes a subtracter  2305 ′ and an adder  2306 ′ instead of the adder  2305  and the subtracter  2306 , respectively, of FIG.  10 . Also, a polarity inverter  2308  is added to the complexer multiplier  18 A. As a result, a complex multiplier  18 ′ formed by the multipliers  2301 ,  2302 ,  2303 ,  2304 , the subtracter  2305 ′ and the adder  2306 ′ has the same configuration as the complex multiplier  18 . Note that the angle signal sinθ is generally represented by a binary code. Therefore, in order to obtain the angle signal −sinθ, all the bits of the angle signal sin θ are inverted and a value of +1 is added thereto. However, an angle signal −sinθ is approximately obtained by only inverting all the bits of the angle signal sinθ as illustrated in FIG. 13, allowing an error due to the LSB of the angle signal sinθ. 
     Also, in FIG. 13, as explained above, the complex multiplier  18 ′ has the same configuration as the complex multiplier  18 . Therefore, as illustrated in FIG. 14, if switches SW 1 , SW 2 , SW 3 , SW 4  and SW 5  operated on a time-division basis are added, the complex multipliers  18  and  18 ′ can be constructed by a single complex multiplier, thus decreasing the apparatus in size. 
     In the above-described embodiment, a semi-coherent detection system and an orthogonal modulation signal such as a PSK or QAM is illustrated; however, a detection system other than the semi-coherent detection system can be used, and a 2-phase PSK (BPSK) or amplitude phase modulation (APSK) signal can be used. 
     As explained hereinabove, according to the present invention, an accurate automatic gain control is carried out to thereby suppress the amplitude error in the I signal and the Q signal. Also, since only a single AGC circuit is provided, the circuit configuration can be simplified.