Abstract:
A displacement detecting apparatus includes an error correcting circuit through which a pair of sine wave signals detected by a detecting head unit are corrected. A signal detecting circuit receives the pair of sine wave signals whose phases are shifted by about 90°, and detects a magnitude of one of the two sine wave signal when the other one of the two sine wave signals crosses with a reference voltage level. The error correcting circuit calculates an error correction amount of each sine wave signal according to the detected magnitude of the signal and eliminates the calculated error correction amount from the signals. Therefore, the sine wave signals of position information are accurately corrected in direct-current component, voltage ratio and phase difference.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to improvements in a displacement detecting apparatus which includes an error correcting subsystem. 
     Generally, a displacement detecting apparatus (scale apparatus) utilizes an interpolation method for dividing a regenerated wave length λ of an incremental signal, in order to have a high-resolution that can distinguish the regenerated wave length λ of an incremental signal. As shown in FIGS. 16A to 16D, when an electromagnetic division (scale) are formed on a scale 1001, signals detected by detection heads 1002 and 1003 are represented as follows: 
     
         E.sub.A =A sin (2πX/λ), E.sub.B =B cos (2πX/λ) 
    
     where A and B are amplitudes of detected signals E A  and E B , and X is a postion of a detection head. 
     Assuming that B=A, the equation E A  /E B  =A sin (2πX/λ)/A cos (2πX/λ)=tan(2πX/λ) is derived. Accordingly, the equation X=(λ/2π)arctan(E A  /E B ) is obtained. This relationship by this equation forms a Lissajous figure of FIG. 16D. As shown in FIG. 16D, since A=B, the Lissajous figure becomes a circle. Assuming that the position X of the head is (λ/2π)θ(X=(λ/2π)θ), the phase θ thereof is represented by (E A  /E B ), that is, θ=arctan (E A  /E B ). At this time, the errors of the signals are generated if one of the following conditions is satisfied: a first condition that a direct current component is superposed on the incremental signal as shown in FIGS. 17A to 17C; a second condition that the amplitude of the signal a becomes different from that of the signal b, and a third condition that the phase 30 shift between the signals a and b is not accurately controlled at 90°. Signal values Ea and Eb of such signals a and b can be represented as follows: 
     
         E.sub.a =A sin (2πX/λ)+D.sub.1, E.sub.b =B sin {(2πX/λ)+δ}+D.sub.2 
    
     The head position X within one wave length λ is represented as follows: 
     
         X=(λ/2π) arctan (E.sub.a /E.sub.b) 
    
     In this case, the Lissajous figure forms an ellipse as shown in FIG. 17C. 
     In order to eleminate such direct-current components D 1  and D 2 , Japanese Patent Provisional Publication No. 2-251720 discloses a correction system as shown in FIG. 18. In this conventional system, signals a and b indicative of a scale detected from a scale 1 are sent to an A/D converter (analog-to-digital converter) wherein the signals a and b are converted into digital signals. The digital signals are sent to a digital signal processing circuit 8 of a CPU (Central Processing Unit) wherein the calculation for a correction is executed. As shown in FIG. 18, the detected signals a and b from detectors 2 and 3 on the scale 1 are supplied to a digital signal processing circuit 8 through amplifiers 4 and 5 and A/D converters 6 and 7. The digital signal processing circuit 8 samples the signals a and b as shown in FIG. 19 and stores them in a RAM 10. The digital signal processing circuit 8 obtains a maximum value and a minimum value of each signal data by comparing the newest data of the signals a and b with the previously stored data. Further, direct-current component (deviations) D 1  and D 2  are obtained by calculating a mid point between the maximum and minimum values of each signal. By subtracting the obtained direct-current components (deviations) D 1  and D 2  from the signals a and b, the digital signal processing circuit 8 generates corrected signals and supplies them to a data conversion circuit 11 wherein A/B phase signal is generated. 
     The overlapped errors on the detection sensors 2 and 3 are controlled by the above-mentioned circuit. In addition to this error correction, the scale apparatus further required to eliminate various error factors such as a deviation of the direct-current error component due to the external magnetic field as shown in FIG. 20A, an output deviation due to a clearance deviation between a storage medium and the detection head as shown in FIG. 20B and a deviation due to phase deviation caused by the waviness of a head-running standard surface as shown in FIG. 20C. In order to eliminate such errors, the scale apparatus of Japanese Patent Provisional Publication No. 2-251720 is provided with a direct-current component detecting circuit, an output amplitude detecting circuit and a phase detecting circuit for obtaining respective correction values. The scale apparatus including a correction circuit calculates the amount of error from the correction values. The digital signal processing circuit 8 executes a correction of errors according to the direct-current component, an output amplitude difference and a phase shift of the signals a and b. More particularly, the scale apparatus obtains a maximum value and a minimum value of each signal a, b and executes a correction of the signals a and b by calculations. The corrected signals are supplied to an interpolation circuit wherein arc-tangent of the corrected signals are obtained as an interpolation. 
     However, with this conventional correcting method of the scale apparatus, it is necessary to execute a high-speed sampling for detecting peak values of the signals a and b as shown in FIG. 19 and to frequently execute calculations of a complicated trigonometric function. Therefore, such a displacement detecting apparatus has to provide two high-speed A/D converters and a high-speed performing CPU or digital signal processor. Further, since the signals a and b from the scale is deviated due to the temperature deviation, it is necessary to provide a high-bit and high-accuracy A/D converter. These installations largely increase the cost of the correction circuit and therefore the displacement detecting apparatus including this correction circuit is largely increased in cost. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide an improved displacement detecting apparatus which is free from the above-mentioned drawbacks. 
     A displacement detecting apparatus according to the present invention comprises a detection head unit which detects two sine wave signals whose phases are shifted by about 90°. A signal detecting circuit detects a magnitude of one of the two sine wave signal when the other one of the two sine wave signals crosses with a reference voltage level. A correcting circuit calculates an error correction amount of each sine wave signal according to the detected magnitude of the signal and eliminates the calculated error correction amount from the signals. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing an example of a correction circuit of a displacement detecting apparatus according to the present invention; 
     FIG. 2 is a block diagram showing another example of the correction circuit of the displacement detecting apparatus according to the present invention; 
     FIGS. 3A and 3B are wave form charts for explaining a detection of zero-crossing of signals in the displacement detecting apparatus; 
     FIGS. 4A and 4B are wave form charts for explaining a detection of an absolute value correspondence between the signals; 
     FIG. 5 is a wave form chart which shows an interval between read-in signals; 
     FIG. 6 is a circuit diagram of a zero-crossing point detection circuit; 
     FIG. 7 is a circuit diagram of an absolute-value correspondence detection circuit; 
     FIG. 8 is a wave-form chart for explaining a reading point of an inversion signal; 
     FIG. 9 is a wave-form chart which shows a change between a signal and a scale-up signal; 
     FIG. 10 is a circuit diagram which shows a whole construction of the displacement detecting apparatus according to the present invention; 
     FIG. 11 is a flowchart showing a manner of an error correcting operation; 
     FIGS. 12A and 12B are flowcharts showing another manner of the error correcting operation; 
     FIGS. 13A and 13B are wave-form charts for explaining an improved error-component detecting manner; 
     FIGS. 14A and 14B are wave-form charts for explaining an improved error-component detecting manner; 
     FIGS. 15A and 15B are wave form charts for explaining an improved error-component detecting manner; 
     FIG. 16A is a schematic view which shows a scale and a pair of detection heads of a conventional displacement detection apparatus; 
     FIGS. 16B, 16C and 16D are wave form charts showing a relationship between the detection heads of FIG. 16A; 
     FIGS. 17A, 17B and 17C are wave form charts showing a relationship between the detection heads; 
     FIG. 18 is a block diagram showing a conventional correction circuit for a displacement detecting apparatus; 
     FIG. 19 is a wave form chart for explaining a signal sampling of a conventional displacement detecting apparatus; and 
     FIGS. 20A, 20B and 20C are views for explaining error deviation factors of a displacement detecting apparatus. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to drawings, preferred embodiments of a displacement detecting apparatus according to the present invention will be discussed. 
     First, as to a case that a deviation of a phase difference between signals a and b is smaller than a predetermined value and that a direct-current component and an amplitude ratio of the signals are corrected, the manner of correcting operation will be discussed hereinafter with reference to FIGS. 13A, 13B, 14A and 14B. 
     When the output voltages of the signals a and b are Ea and Eb and when θ=2πX/λ, the following equations (1) and (2) are obtained. 
     
         Ea=A sin θ+D.sub.1                                   (1) 
    
     
         Eb=B cos θ+D.sub.2                                   (2) 
    
     From the equations (1) and (2), values Ec, Ed, Ee and Ef at detection points c, d, e and f are obtained. If each phase at each of the detection points c, d, e and f is θc, θd, θe, θf as shown in FIG. 13A, four sets of the simultaneous equations are given. As to the detection point c, the following simultaneous equations are given: 
     
         Eac=A sin θc+D.sub.1 =0                              (3) 
    
     
         Ebc=B cos θc=D.sub.2 =Ec                             (4) 
    
     wherein Eac is a value of signal a at the detection point c, and Ebc is a value of signal b at the detection point c. 
     From the equation (3), the following equation is obtained: 
     
         sin θc=-D.sub.1 /A                                   (5) 
    
     The equation (5) can be deformed by the relationship in the trigonometric function as follows: ##EQU1## By substituting this equation (6) into the equation (4), the following equation is obtained: ##EQU2## 
     Similarly, as to the detection point e, the following simultaneous equations are obtained. 
     
         Eae=A sin θe+D.sub.1 =0                              (8) 
    
     
         Ebe=B cos θe+D2=Ee                                   (9) 
    
     wherein Eae is a value of signal a at the detection point e, and Ebe is a value of signal b at the detection point e. 
     Accordingly, the following equation is obtained; ##EQU3## 
     Finally, from the equations (7) and (10), the following equation is obtained. 
     
         D.sub.2 =(E.sub.c +Ee)/2                                   (11) 
    
     As to the detection point d, the following simultaneous equations are obtained: 
     
         Ead=A sin θd+D.sub.1 =Ed                             (12) 
    
     
         Ebd=B cos θd+D.sub.2 =0                              (13) 
    
     wherein Ead is a value of signal a at the detection point d, and Ebd is a value of signal b at the detection point d. 
     As to the detection point f, the following simultaneous equations are given: 
     
         Eaf=A sin θf+D.sub.1 =Ef                             (14) 
    
     
         Ebf=B cos θf+D.sub.2 =0                              (15) 
    
     wherein Eaf is a value of signal a at the detection point f, and Ebf is a value of signal b at the detection point f. 
     As is the same as that in the detection points c and e, from the two sets of the simultaneous equations (12) and (13), (14) and (15), the following equation indicative of the direct-current component is obtained. 
     
         D.sub.1 =(Ed+Ef)/2                                         (16) 
    
     Next, as to the output amplitudes A and B, the following equations are obtained. ##EQU4## 
     Although the output amplitudes A and B are obtained by the above equations (17) and (18), this solving calculation takes a long time. Therefore, only the correction as to the direct current component is carried out, and the correction as to the amplitude ratio of the signals a and b is not carried out. By the correction of the direction-current component, the signals a and b have a generally zero direct-current component. That is, D 1  =D 2  =0. Accordingly, as shown in FIGS. 14A and 14B, the read-in voltage values indicate output amplitudes of the respective signals a and b as follows: 
     
         A=Ed=Ef                                                    (19) 
    
     
         B=Ec=Ee                                                    (20) 
    
     Next, as to a case that the corrections of all components including the phase correction are executed, the manner of adjusting operation will be discussed hereinafter. 
     When Ea and Eb are output voltage values of the signals a and b, and θ=2πX/λ, the following equations are obtained. 
     
         Ea=A sin θ+D.sub.1                                   (21) 
    
     
         Eb=B cos (θ+δ)+D.sub.2                         (22) 
    
     As shown in FIGS. 13A and 13B, values Ec, Ed, Ee and Ef at detection points c, d, e and f are obtained. If each phase at each of the detection points c, d, e and f is θc, θd, θe, θf, four sets of the simultaneous equations are established. As to the detection point c, the following simultaneous equations are obtained: 
     
         Eac=A sin θc+D.sub.1 =0                              (23) 
    
     
         Ebc=B cos (θc+δ)+D.sub.2 =Ec                   (24) 
    
     wherein Eac is a value of signal a at the detection point c, and Ebc is a value of signal b at the detection point c. 
     From the equation (23), the following equation (25) is derived. 
     
         sin θc=-D.sub.1 /A                                   (25) 
    
     From the equation (25), the following equations (26) and (27) are derived. ##EQU5## 
     By substituting the equation (27) into the equation (24), the following equation is obtained. ##EQU6## 
     As to the detection point e, the following simultaneous equations are established. 
     
         Eae=A sin θe+D.sub.1 =0                              (29) 
    
     
         Ebe=B cos (θe+δ)+D.sub.2 =Ee                   (30) 
    
     wherein Eae is a value of the signal a at the detection point e, and Ebe is a value of signal b at the detection point e. 
     By the equation modulation similar to that as to the detection point c, the following equation is obtained. ##EQU7## 
     From the equations (28) and (31), the direct current component D 2  of the signal b is obtained as follows: 
     
         D.sub.2 =(Ec+Ee)/2-(D.sub.1 /A)sin δ                 (32) 
    
     As to the detection point d, the following simultaneous equations are established. 
     
         Ead=A sin θd+D.sub.1 =Ed                             (33) 
    
     
         Ebd=B cos (θd+δ)+D.sub.2 =0                    (34) 
    
     wherein Ead is a value of signal a at the detection point d, and Ebd is a value of signal b at the detection point d. 
     From the equation (34), the following equations are derived. ##EQU8## Accordingly, the direct-current component D 1  of the signal a is derived as follows: ##EQU9## 
     As to the detection point f, the following simultaneous equations are established. 
     
         Eaf=A sin θf+D.sub.1 =Ef                             (39) 
    
     
         Ebf=B cos (θf+δ)+D.sub.2 =0                    (40) 
    
     wherein Eaf is a value of signal a at the detection point f, and Ebf is a value of signal b at the detection point f. ##EQU10## From the equations (38) and (41), the following equation is obtained. 
     
         D.sub.1 ={(Ed+Ef)/2}-(D.sub.2 /B) sin δ              (42) 
    
     Since (D 1  /A) sin δ of the equation (32) and (D 2  /B) sin δ of the equation (42) are considerably smaller than D 1  and D 2 , the direct-current component is deceased by executing the correction. Accordingly, by repeatingly executing this correction within a predetermined interval (such as twice or three times), the direct-current components of the signals are corrected. By the correction of the direct-current components of the signals a and b, the values D 1  and D 2  are converged into zero. Therefore, the correction of the amplitude ratio of the signals a and b is executed thereafter. 
     From the equations (31) and (41), the amplitudes A and B are expressed as follows: 
     
         A=Ef/ cos δ                                          (43) 
    
     
         B=Ee/ cos δ                                          (44) 
    
     Although the output ratio is decreased according the shift amount δ of the phase, the output of the signals is also decreased with the same ratio as that of the output ratio. Therefore, the ratio between the amplitudes A and B is equally corrected. 
     The detection of the phase is executed as shown in FIGS. 15A and 15B after the corrections of the direct-current component and the amplitude. That is, the values Eg and Eh of the voltages at the detection point g and h are read. The voltage values Eg and Eh are expressed as follows: 
     
         Eg=A sin {(π/4)-δ}=A cos {(π/4)+δ}       (45) 
    
     
         Eh=A sin {(π/4)+δ}                                (46) 
    
     Therefore, the following equations are derived. 
     
         Eh/Eg=tan {(π/4)+δ}                               (47) 
    
     
         δ=arctan (Eh/Eg)-π/4                              (48) 
    
     The correction of the phase of the signal a, b is executed by using the phase shift amount of the equation (48). 
     Referring to FIG. 1, a first embodiment of a displacement detecting apparatus according to the present invention will be discussed hereinafter. The displacement detecting apparatus comprises a measuring scale 101 on which a pair of sensors 102 and 103 are slidably disposed. The sensor 102 outputs a detected signal a to an amplifier 104. The amplified signal a in the amplifier 104 is sent to an interpolation circuit 106, a comparator 107 and a multiplexer 108. Also, the sensor 103 outputs a detected signal b to an amplifier 105. The amplified signal b is sent to the interpolation circuit 106, the comparator 107 and the multiplexer 108. The amplifiers 104 and 105 are connected through a correction circuit 118 with a CPU (central processing unit) 114 which is connected with an EEPROM (electrically erasable and programmable ROM) 115, a RAM (random access memory) 116 and a ROM (read-only memory) 117. The amplifiers 104 and 105 amplify the detected signals a and b into a required level while controlling a direct-current component, a voltage ratio and a phase of each signal a, b according to preset values in the EEPROM 115. The interpolation circuit 106 interpolates the received signals a and b and outputs an A/B phase signal. The comparator 107 compares the signals a and b with a reference voltage to detect a zero-crossing point of the signals a and b. 
     FIG. 3A shows zero-crossing points of the signals a and b. That is, at a point c where the signal a first crosses with the reference voltage, a voltage value Ebc of the signal b is detected. At a point e where the signal a next crosses with the reference voltage, a voltage value Ebe of the signal b is detected. Similarly, at a point d where the signal b first crosses with the reference voltage, a voltage value Ead of the signal a is detected. At a point f where the signal b next crosses with the reference voltage, a voltage value Eaf of the signal a is detected. By plotting the voltage values Ebc, Ebe, Ead and Eaf on a-axis and b-axis which are perpendicularly crossed with each other, a Lissajous figure as shown in FIG. 3B is obtained. 
     FIG. 6 shows a detection circuit for detecting a zero-crossing point. The structure of the detection circuit for the signal a is the same as that for the signal b. The signal a inputted to an input terminal 601 is compared with a reference voltage in a comparator 603 as to whether the signal a is crossing with the reference voltage. When the signal a crosses with the reference voltage, the comparator 603 outputs a pulse signal indicative that the signal a is crossing with the reference voltage. The outputted signal is inputted to a first flip-flop circuit 605 according to a clock signal. The output of the first flip-flop circuit 605 is inputted to a second flip-flop circuit 607 according to a next clock signal. The outputs of the first and second flop-flip circuits 605 and 607 are supplied to an exclusive-OR circuit 609. The output of the exclusive-OR circuit 609 is supplied to an OR circuit 611. Similarly, the signal b inputted to an input terminal 602 is compared with a reference voltage in a comparator 604 as to whether the signal b is crossing with the reference voltage. When the signal b crosses with the reference voltage, the comparator 604 outputs a pulse signal indicative that the signal b is crossing with the reference voltage. The outputted signal is inputted to a first flip-flop circuit 606 according to a clock signal. The output of the first flip-flop circuit 606 is inputted to a second flip-flop circuit 608 according to a next clock signal. The outputs of the first and second flop-flip circuits 606 and 608 are supplied to an exclusive-OR circuit 610. The output of the exclusive-OR circuit 610 is supplied to the OR circuit 611. With this circuit, when the signal a or b crosses with the reference voltage, a signal indicative of the crossing of the signal a, b with the reference voltage is outputted. 
     As shown in FIG. 1, the output of the comparator 107 is supplied to a control circuit 109 which controls a multiplexer 108 so as to input the signals a and b into a sample-and-hold circuit 110. The sample-and-hold circuit 110 executes a sampling of a momentum value of each signal a, b and stores it. The stored signal in the sample-and-hold circuit 110 is supplied to a shift circuit 111 where the signal is shifted according to a signal from the CPU 114 and a necessary part of the signal is outputted to a scale-up circuit 112 wherein the necessary part of the signal is scaled up and the scale-up signal is outputted to an A/D converter (analog-to-digital converter) 113. The A/D converter 113 converts the received signal into a digital signal and supplies it to the CPU 114. The CPU 114 calculates amplitudes of the signals a and b for the A/D converter 113 with reference to data in the EEPROM 115, the RAM 116 and the ROM 117. The calculated amplitudes are supplied to a correction circuit 118 as a correction signal. The correction circuit 118 executes a correction of the amplitudes of the signals a and b by applying the amplitude correcting signal to the amplifiers 104 and 105. The corrected signals, which are corrected as to the reference voltage and the amplitude, are supplied to the interpolation circuit 106 wherein a correct A/B phase signal is obtained. 
     Next, as to a case that three deviations of a direct-current component, an output voltage ratio and a phase shift of the signals a and b are corrected, the manner of the correcting operation will be discussed hereinafter. 
     Referring again to FIG. 1, the signals a and b detected by the sensors 102 and 103 are supplied to amplifiers 104 and 105 wherein the signals are amplified to a necessary level. The amplified signals in the amplifiers 104 and 105 are supplied to the interpolation circuit 106, the comparator 107 and the multiplexer 108. In the amplifiers 104 and 105, the direct-current component, the output voltage ratio and the phase of the signals a and b are controlled according to the preset values in the EEPROM 115. The interpolation circuit 106 interpolates the signals a and b and outputs an A/B phase signal. The comparator 107 compares the signals a and b with the reference voltage for detecting a zero-crossing point. The comparator 107 executes a detection of an absolute amount correspondence. FIGS. 6 and 7 show a circuit for detecting a zero-crossing point and a circuit for detecting a correspondence between absolute amounts of the signals a and b. 
     The circuit for detecting absolute amount correspondence will be discussed hereinafter with reference to a circuit diagram of FIG. 7. The signal a inputted to a terminal 701 and the signal b inputted to a terminal 702 are compared in a comparator 703 wherein a signal is ouputted when the signals a and b take the same value. The output from the comparator 703 is inputted to a first flip-flop circuit 705 according to a clock signal. The output of the first flip-flop circuit 705 is inputted to a second flip-flop circuit 707 according to a next clock signal. During this time, the output pulse is outputted through an exclusive-OR circuit 709. On the other hand, the signal a inputted to a terminal 712 and an inversion signal of the signal b inputted to a terminal 713 are supplied to a comparator 704 wherein a signal is outputted only when the signal a and the inversion signal of the signal b take the same value. 
     FIG. 8 shows the absolute values of the sine-wave and the cosine-wave. The points g, h, i and j, where the amplitude of the sine wave and the amplitude of the cosine wave are correspondent with each other, are marked. Further, the points f, c, d and e, where the absolute value of the sine-wave or cosine-wave takes maximum value, are marked. The signals are read-in at π/4 intervals as shown in FIG. 5. 
     When the zero-crossing point and the absolute amount correspondence point are detected, the signal is supplied through the multiplexer 108 to the sample-and-hold circuit 110 wherein the data is sampled and stored. The sampled signal is supplied to the shift circuit 111 wherein the data is shifted so that a part higher than the point where the absolute values of the sine-wave and cosine-wave correspond with each other is picked up. The data processed by the shift circuit 111 is supplied to a scale-up circuit 112. The scale-up circuit 112 scales up the signal in the vicinity of the corresponding point and supplies the signal scaled-up into a dynamic range to the A/D converter 113. The A/D converter 113 converts the signal indicative of a scaled-up portion of the initial signal. Therefore, the conversion by the A/D converter 113 is accurately executed. The digital signal converted in the A/D converter 113 is supplied to the CPU 114. 
     When the zero-crossing points c, d, e and f and one of three pairs of the corresponded points g and h; h and i; i and j; or j and g shown in FIG. 3 are detected, the error amount of the direct-current component is calculated. According to the calculated error amount the correction of the electronic volume of the circuit shown in FIG. 10 is executed. In this situation, when the error amount of the direct-current component is smaller than an allowable value, the output voltage values A and B are calculated and corrected. Further, when the output voltage ratio is smaller than an allowable value, the phase amount is calculated and corrected. 
     FIG. 10 shows an example of an error correcting circuit of the displacement detecting apparatus according to the present invention. This circuit comprises a channel 1 (CH1) and a channel 2 (CH2) for the respective signals a and b detected by the detection heads 302 and 303. Each electronic volume at a first stage amplifier of each channel is arranged to receive a direct-current component control signal. Each electronic volume at a second stage amplifier of each channel is arranged to receive an output voltage control signal. An electronic volume of an impedance circuit between the channel 1 and the channel 2 receives a phase control signal. 
     Next, the manner of the error correcting operation of the displacement detecting apparatus according to the present invention will be discussed hereinafter with reference to a flowchart of FIG. 11. 
     In a step S1, the routine is started. 
     In a step S2, an initial resistance value of an electronic volume (E.V.) is set at a predetermined value. 
     In a step S3, it is judged whether signal data at either of the detection points c, d, e, f, g, h, i, j is detected or not. When no data is detected, the routine repeats the step 3 until the data at either of detection points is detected. When the data at either of the detection points is detected, the routine proceeds to a step S4. 
     In the step S4, the detected data is stored in a memory. 
     In a step S5, it is judged whether the data at all of the detection points is obtained or not. When the data at either of the detection points is not yet obtained, the routine returns to the step S3 and repeats the steps S3, S4 and S5 until the YES answer is obtained in the step S5. When the data at all detection points is obtained, the routine proceeds to a step S6 wherein the direct-current component of each signal is calculated. 
     In a step S7, it is judged whether the calculated direct-current component is smaller than an allowable value or not. When the calculated direct-current component is not smaller than the allowable value, the routine jumps to a step S12 wherein the correction of the direct-current component is executed. When the direct-current component is smaller than the allowable value, the routine proceeds to a step S8 wherein the output voltage ratio is calculated. 
     In a step S9, it is judged whether the output voltage ratio is smaller than an allowable value or not. When the judgment in the step S9 is &#34;NO&#34;, the routine jumps to a step S13 wherein the correction of the output voltage ratio is executed. When the judgment in the step S9 is &#34;YES&#34;, the routine proceeds to a step S1O wherein the phase difference is calculated. 
     Following this, in a step S11, the correction of the phase difference is executed. After the execution of the step S11, the routine returns to the step S3. 
     Referring to FIG. 2, there is shown a second embodiment of the displacement detecting apparatus according to the present invention. The structure of the second embodiment is generally similar to that of the first embodiment except that a multiplexer 219 is further added to the circuit of the second embodiment. 
     In case that the measuring scale 101 is put in a temperature outside of the predetermined range, or receives a dynamic impact larger than a predetermined value, it may happen that the scale signals a and b are largely deviated and therefore the input signal to the A/D converter 113 through the scale-up circuit 112 may take a large value outside of a predetermined range. 
     In contrast, according to the second embodiment, even if such signals are inputted in the apparatus, such signals are corrected without trouble. As shown in FIG. 2, the signals a and b detected by sensors 202 and 203 from a scale 201 is amplified at amplifiers (AMP) 204 and 205 at a necessary level. In the amplifiers 204 and 205, the direct-current component, the voltage ratio and the phase of the signals a and b are controlled according to a preset value stored in the EEPROM. 
     The amplified signals a and b in the amplifiers 204 and 205 are supplied to an interpolation circuit 206 wherein the signals are interpolated and an A/B phase signal is outputted. The amplified signals a and b are inputted to a comparator 207 wherein the signals are compared with a reference voltage for detecting a zero-crossing point and for detecting the absolute amount correspondence point of the sine-wave and cosine-wave of the signals. The circuit for detecting the zero-crossing point and the circuit for detecting the absolute amount correspondence point are shown in FIGS. 6 and 7, respectively. 
     The output indicative that the zero-crossing point and the absolute amount correspondence point are detected is inputted from the comparator 207 to a control circuit 209. The control circuit 209 outputs a control signal to a multiplexer 208 and a sample-and-hold circuit 210 so that the output signals from the amplifiers 204 and 205 at time when the zero-crossing point and the absolute amount correspondence point are detected are supplied to and stored in the sample-and-hold circuit 210 through the multiplexer 208. 
     The sample-and-hold signal is supplied to a shift circuit 211 wherein the signal is shifted so that the data in the vicinity of the detection point is outputted. The signal from the shift circuit 211 is supplied to a scale-up circuit 212 wherein the signal indicative of the data in the vicinity of the detection point is scaled up into a dynamic-range. Then, the scaled-up signal is supplied to an A/D converter 213. In case that the detected voltage (the signal supplied to the A/D converter) takes a value outside a range of the A/D converter 213, the sampled signal is not supplied to the scale-up circuit 212 and is supplied to the A/D converter 213 wherein the direct-current component and the gain of the signal is controlled in range so as to be within a range of the scale-up circuit. 
     The manner of operation of the displacement detecting apparatus of the second embodiment will be discussed hereinafter with reference to flowcharts of FIGS. 12A and 12B. 
     In a step S101, the routine is started. 
     In a step S102, an initial resistance value of an electronic volume (E.V.) is set at a predetermined value. 
     In a step S103, it is judged whether signal data at either of the detection point c, d, e, f g, h, i, j is detected or not. When no data is detected, the routine repeats the step 103 until the data at either of the detection points is detected. When the data at either of the detection points is detected, the routine proceeds to a step S104. 
     In the step S104, the detected data is stored in a memory. 
     In a step S105, it is judged whether the detected data is outside of a predetermined range or not. When the detected data is within the range, the routine proceeds to a step S106. When it is outside the range, the routine proceeds to a step S115. 
     In a step S106, it is judged whether the data at all of the detection points is obtained or not. When the data at either of the detection points is not yet obtained, the routine returns to the step S103 and repeats the steps S103 to S106 until the YES answer is obtained in the step S106. When the data at all detection points is obtained, the routine proceeds to a step S107 wherein the direct-current component of each signal is calculated. 
     In a step S108, it is judged whether the calculated direct-current component is smaller than an allowable value or not. When the calculated direct-current component is not smaller than the allowable value, the routine jumps to a step S113 wherein the correction of the direct-current component is executed. When the direct-current component is smaller than the allowable value, the routine proceeds to a step S109 wherein the output voltage ratio is calculated. 
     In a step S110, it is judged whether the output voltage ratio is smaller than an allowable value or not. When the judgment in the step S110 is &#34;NO&#34;, the routine proceeds to a step S114 wherein the correction of the output voltage ratio is executed. When the judgment in the step S110 is &#34;YES&#34;, the routine proceeds to a step S111 wherein the phase difference is calculated. 
     Following this, in a step S112, the correction of the phase difference is executed. After the execution of the step S112, the routine returns to the step S103. 
     When the judgment in the step S105 is &#34;YES&#34;, that is, when the detected data is out of the range, the routine proceeds to the step S115 wherein it is judged as to whether the data at the detection points c, d, e and f are detected by the sample-and-hold circuit 210 or not. When the judgment in the step S115 is &#34;YES&#34;, the routine proceeds to a step S116 wherein the detected data is stored. When the judgment in the step S115 is &#34;NO&#34;, the routine repeats the step S115 until the sample-and-hold circuit 210 detects the signal at the detection points c, d, e and f. 
     In a step S117, it is judged whether the data at all of the four detection points c, d, e and f is detected or not. When the judgement in the step S117 is &#34;NO&#34;, the routine returns to the step S115 and repeats the steps S115, S116 and S117 until the data at all four points is detected. When the judgment in the step S117 is &#34;YES&#34;, that is, when the data at all four detection points is detected, the routine proceeds to a step S118 wherein the direct-current component of each signal is calculated. 
     In a step S119, it is judged whether the calculated direct-current component is smaller than an allowable value or not. When the calculated direct-current component is not smaller than the allowable value, the routine proceeds to a step S122 wherein the correction of the direct-current component is executed. Following the step S122, the routine proceed to a step S123. When it is judged in the step S119 that the direct-current component is smaller than the allowable value, the routine proceeds to a step S120 wherein the output voltage ratio is calculated. 
     In a step S121, the correction of the output voltage is executed. 
     In a step S123, it is judged whether the data at the detection points c, d, e and f is detected by the sample-and-hold circuit 210 or not. When the judgment in the step S123 is &#34;YES&#34;, the routine proceeds to a step S124 wherein the detected data is read-in and stored. When the judgment in the step S123 is &#34;NO&#34;, the routine repeats the step S123 until the sample-and-hold circuit 210 detects the signal at the detection points c, d, e and f. 
     In the step S125, it is judged whether the detected data at the detection points c, d, e and f is within the range or not. When the judgment in the step S125 is &#34;YES&#34;, the routine returns to the step S103. When the judgment in the step S125 is &#34;NO&#34;, the routine returns to the step S115. 
     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the forgoing and other changes in form and details can be made therein without departing from the spirit and scope of the invention.