Abstract:
A device calibrates the frequency of an oscillator. The oscillatory has first and second inputs and generates an output frequency responsive to a first voltage signal at the first input. The calibration device generates a calibration signal applied at the second input of the oscillator for calibrating its output frequency and comprises a counter. The counter has a first input frequency proportional to a reference frequency and a second input frequency proportional to the output frequency. The counter counts the time window number given by the ratio of the second to first frequencies. The devices comprises a comparator that compares the counted time window numbers with a prefixed time window number. The calibration device changes the value of the calibration signal if the counted time window number is different from the prefixed time window number and until the counted time window number is equal to the prefixed time window number.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention refers to a device for calibrating the frequency of an oscillator, to a phase looked loop circuit comprising said calibration device and to the related frequency calibration method.  
         [0003]     2. Description of the Related Art  
         [0004]     In the present radio communication systems phase looked loop circuits (PLL) are generally utilized for generating oscillating electric signals. Generally the PLLs comprise a voltage controlled oscillator (VCO) generating an oscillating output signal as a response of a voltage level applied at the input. The specific parameters of the voltage/frequency relationship depend on the parameters of the VCO manufacturing process, the values of the electric components that it comprises, the ambient temperature and the other factors.  
         [0005]     For reducing the effects of the temperature variations and of the process parameters, devices for calibrating the frequency of the VCO are presently used.  
         [0006]     Such devices become very important for the following reasons.  
         [0007]     The reduction of the sizes of the integrated circuits which are due to the generation of MOS transistors having smaller and smaller channels imposes a reduction of the supply voltage and, for this reason, a reduction of the input voltage of the VCO.  
         [0008]     The need of increasing the rejection of the spur radiation emissions in PLL and the risk of frequency variations of the VCO which are due to the interferences given by the coupling with the rest of the circuitry when a complex system is formed on a chip, imposes a reduction of the gain of the VCO.  
         [0009]     A PLL having a device for calibrating a frequency of a VCO is disclosed in the article “A Fully Integrated PLL Frequency Synthesizer LSI for Mobile Communication System.”, 2001 IEEE Radio Frequency Integrated Circuits Symposium, pages 65-68. The PLL device comprises a programmable divider, a phase comparator, a filter, a delta-sigma converter, a VCO and a frequency error detector. The frequency band of the VCO is selected by means of a digital control signal and the resonant circuit of the VCO has N frequency bands of operation. When new frequency data are sent to the PLL the VCO has an input constant voltage. As a response of a starting digital signal one among the N bands of the resonator circuit is selected and the VCO oscillates at a frequency f 1  that is sent to the programmable divider having at the input the output signal of the sigma-delta converter; the output signal of the programmable divider is the signal fdiv. The error detector compares the frequency fdiv with a reference frequency fref and it generates a new digital signal for selecting another frequency band of the VCO. The process is iterated several times until the frequency difference between the signal fdiv and the signal fref becomes less than a prefixed value. When the corrected frequency band of the VCO has been determined-, the VCO does not have any longer at the input the constant signal but the output signal of the filter so that the PLL acts in closed loop condition.  
         [0010]     The precision of the frequency calibration in this device is due to the bit number of the digital signal; however the use of a digital signal with a large bit number brings to an increase of increases the convergence time of the calibration method. It is therefore necessary a trade-off between the bit number of the digital signal and the convergence time of the calibration method.  
       BRIEF SUMMARY OF THE INVENTION  
       [0011]     In view of the art described, it is an object to present invention to provide a device for calibrating the frequency of an oscillator which is more precise than the known devices and which has a small convergence time.  
         [0012]     According to the present invention, this object is obtained by means of a device for calibrating the frequency of an oscillator, said oscillator having a first and a second input and generating an output frequency as a response to a first voltage signal applied at said first input, said calibration device being adapted to generate an output digital signal applied at said second input of the oscillator for calibrating its output frequency, characterized in that said calibration device comprises at least one counter, said counter having a first input frequency proportional to a reference frequency and a second input frequency proportional to the output frequency of the oscillator, said counter counting a time window number given by the ratio of the second to first frequency and said device comprising means adapted to compare said counted time window number with a prefixed time window number, said calibration device being adapted to change the value of said frequency calibration digital signal if said counted time window number is different from said prefixed time window number and until it is obtained that said counted time window number is equal to said prefixed time window number.  
         [0013]     Still according to the present invention it is possible to provide to a phase looked loop circuit as defined in claim  8  that includes such a calibration device.  
         [0014]     Still in accordance with the present invention it is possible to provide a method for calibrating the frequency of an oscillator of a phase looked loop circuit as defined in claim  17 .  
         [0015]     Thanks to the present invention it is possible to provide a device for calibrating a frequency of an oscillator which allows the use of a VCO having a reduced voltage/frequency gain and a reduced input voltage level as required by the present radio communication systems.  
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0016]     The features and the advantages of the present invention will be made evident by the following detailed description of an embodiment thereof, shown as not limiting example in the annexed drawings, wherein:  
         [0017]      FIG. 1  is a schematic view of a phase looked loop circuit comprising a voltage controlled oscillator and a calibration device of the frequency of the oscillator according to the present invention;  
         [0018]      FIG. 2  is a flow diagram representing the method for calibrating the frequency of the oscillator in  FIG. 1 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]     With reference to  FIG. 1 a  phase-locked loop (PLL)  1  comprising a voltage-controlled oscillator (VCO)  2  and a device  3  for calibrating the frequency of the VCO  2  are shown. The PLL comprises a phase detector (PDF)  4  adapted to detect the phase difference between the input reference frequency fR and the frequency fo;. the The output voltage signal of the PDF  4  is sent to a charge pump  4  the  5  having an output signal of which that is filtered by a low-pass filter (LPF)  6 . The VCO  2  can have as input voltage level either a reference voltage Vref or the output voltage signal of the filter LPF  6 ; in fact there is a switch  5   7  that can be connected with the reference voltage Vref or with the output voltage signal of the filter LPF.  
         [0020]     The VCO  2  has an oscillating frequency given by L*S*fo that is calibrated by an output digital signal WD of the device  3 .  
         [0021]     The device  3  comprises at least one counter Ti having a first input frequency proportional to a reference frequency fR and a second input frequency S*fo proportional to the output frequency L*S*fo of the oscillator  2 . The counter counts the time window number Fi given by the ratio of the second to first input frequency and it comprises means  6   8  adapted to compare said counted time window number Fi with a prefixed time window number Bi. The device  3  is adapted to change the value of the frequency calibration digital signal WD if said counted time window number Fi is different from said prefixed time window number Bi and until it is obtained that said counted time window number Fi is equal to said prefixed time window number Bi.  
         [0022]     More precisely the device  3  comprises a first counter T 1  and a second counter T 2  which are placed in parallel to each other; the second counter T 2  has a precision higher than the first counter T 1  so that the prefixed time window number B 1  for the first counter T 1  is lower than the prefixed time window number B 2  for the second counter. The first counter T 1  has a reference frequency fR while the second counter has a reference frequency fR/ 2  provided by a divider  9 . The first counter TI and the second counter T 2  count simultaneously a first F 1  and a second F 2  time window numbers given by the ratio of the frequency fo*S respectively by fR and by fR/2. The first and the second counters comprise means  6   8  adapted to compare said first number F 1  and said second number F 2  with the respective prefixed time window numbers B 1 , B 2  and the device  3  is adapted to change the value of the digital signal WD if one between said time window numbers F 1 , F 2  is different from the respective prefixed time window number B 1 , B 2  and until it is obtained that both the first F 1  and the second F 2  window time numbers are equal to said prefixed time window numbers B 1 , B 2  or, in a similar way, when it is obtained that only the second time window number F 2  is equal to the respective prefixed time window number B 2 .  
         [0023]     Still more precisely the device  3  comprises a plurality of counters T 1 -Tk adapted to count the frequency fo*S with a time window number given by (fo*S/(fR/2 i−1 )) with i=1, . . . k. All the counters T 1 -Tk are activated simultaneously and have as clock signal the signal 1/fo*S. Each counter comprises means  6   8  adapted to send a reset pulse to a logic circutry circuitry  7   10  when the number Fi for counting the frequency fo*S is different from the value Bi given by(fo*S/(fR/2 i−1 )) with i=1, . . . k. where ft is the target frequency set by the outside in the logic circuitry  7   10  with ft=fR; the means  6   8  provide to reset the counter after having sent the reset pulse. Each counter T 1  . . . T comprises means  8   11  for setting the value Bi with i=1, . . . k. for each counter T 1  . . . Tk as a function of the frequency ft provided by the circuitry  7   10 .  
         [0024]     It is also possible, alternatively, that the circuitry  7   10  comprises the means  8   11  so that the same computes and provides the values B 1 -Bk to each counter T 1 -Tk.  
         [0025]     It is still possible, once again alternatively, that the circuitry  7   10  comprises the means  8  so that the same carries out the comparison between each value F 1 -Fk with the corresponding values B 1 -Bk; each one of the counters T 1 -Tk will provide the circuitry  7   10  only with the corresponding value Fi comprised among F 1 -Fk.  
         [0026]     The means  6   8  can be constituted by comparators o or by computer means and the means  8   11  are time period dividers.  
         [0027]     The logic circuitry  7   10  provides to send the reset pulse received from any counter to the other counters for resetting them. Also the logic circuitry  7   10  provides to decrease or to increase the output digital signal WD for at least one least significant bit (LSB) when it receives a reset pulse from any counter. The same circuitry  7   10  controls the switch  5   7  to connect with the voltage Vref during the frequency calibration process and to connect with the output signal of the filter LPF  6  at the end of the calibration process.  
         [0028]     The PLL  1  further comprises a frequency divider L  12  for obtaining a frequency fo*S from the input frequency fo*S*L and a second divider S  13  for obtaining the frequency fo from the input frequency fo*S.  
         [0029]     The frequency calibration apparatus operates in the following way, as shown in the diagram in  FIG. 2 .  
         [0030]     At the starting step A the circuitry  7   10  sets the switch  5   7  to connect with the reference voltage Vref;. at At the step B the circuitry  7   10  sends the digital signal WD corresponding preferably to the highest (high digital signal WD) or the lowest (low digital signal WD) frequency that may be set for the same VCO, that is one among the frequencies limiting the operating range of the VCO  2 , and it resets all the counters T 1 -Tk. When the frequency fo*S is computed by means of the S dividers S  13 , it is counted simultaneously by all the counters T 1 -Tk, arranged in parallel to each other, at the step C. When any counter Ti with i=1, . . . k counts the frequency fo*S with a time window number Fi different from the prefixed number Bi, it sends a reset pulse to the circuitry  7   10  at the step D. The circuitry  7   10  resets all the counters and decreases (in the case wherein the high digital signal WD has been set) or increases (in the case wherein the low digital signal WD has been set) of at least one least significant bit LSB the digital signal WD at the step E; the new frequency fo*S is counted by all the counters T 1 -Tk. The operation corresponding to the steps B-E is repeated more times until the frequency fo tends to coincide with the frequency fR and also the counter Tk counts the time window number (fo*S/(fR*2 k−1 )) corresponding to the value Bk;. In such a case, no reset signal is sent to the circuitry  7  that set in such case  10  and the circuitry  10  sets the switch  5   7  to connect the VCO  2  with the output signal of the filter LPF at the step F. Therefore the last counter Tk determines the precision of the calibration device  3 . The PLL  1  after this instant may operate as a known PLL.  
         [0031]     With such a method the convergence time of the calibration process is reduced for the use of various counters with different precision and with different counting time; more precisely the counters with lower precision employ a lower counting time and therefore the lasts will send to the circuitry  7   10  the reset pulses for the greatest part of the calibration process.  
         [0032]     Said method, which has been described in the case wherein the device  3  comprises a plurality of counters T 1 -Tk, is also valid in the case wherein the device  3  comprises only one counter or two counters.  
         [0033]     For example if it is imposed that the digital signal WD is a word with six bits and it sets initially WD=[111111], fR=32 Mhz, ft=256 Mhz, one considers k=5 and by selecting S=8 it is obtained B1=8, B2=16, B3=32, B4=64, B5=128 and imposes that the frequency fo*S corresponding to the word WD is of 335 Mhz, there will be the following situation.  
         [0034]     The counter T 1  will count  10  pulses equal to the entire number of 335/32 and because said number is higher than B 1 , it sends a reset pulse to the circuitry  7   10  which provides to reset all the counters and to decrease by a LSB the signal WD that is [111110]. Said operation with the only counter T 1  will continue until fo*S=288 Mhz corresponding to the signal [100000] that is when the counter will count a number equal to 9 pulses.  
         [0035]     The second counter T 2  with WD=[100000] will count more than 17 pulses, that is a number higher than B 2 , and it sends a reset pulse to the circuitry  7   10  which provides to reset all the counters and to decrease by a LSB the signal WD that is [011111]. Said operation of the counter T 3  T 2  will continue until fo*S=273 Mhz corresponding to the signal WD=[010110].  
         [0036]     The third counter T 3  with WD=[0101110] will count a pulse number higher than B 3  and it sends a reset pulse to the circuitry  7   10  which provides to reset all the counters and to decrease by a LSB the signal WD that is [010111]. Said operation with the only counter T 3  will continue until fo*S=263 Mhz corresponding to the signal WD=[0011111].  
         [0037]     The fourth counter T 4  with WD=[001111] will count a pulse number higher than B 4  and it sends a reset pulse to the circuitry  7   10  which provides to reset all the counters and to decrease by a LSB the signal WD that is [001110]. In such case the counter T 4  counts a pulse number higher than B 4  and it will provide to decrease by a LSB the signal WD. Said operation will continue until to reach a frequency fo*S corresponding to the signal WD=[001101].  
         [0038]     The fifth counter T 5  with WD=[001101] will count a pulse number higher than B 5  and it will send a reset pulse to the circuitry  7   10  which provides to reset all the counters and to decrease by a LSB the signal WD. Said operation of the counter T 5  will continue until fo*S=256.5 Mhz corresponding to the signal WD=[001011] with which the frequency calibration process ends.