Abstract:
The present invention discloses a soft-switching bidirectional phase-shift converter with an extended load range, which is in particularly applicable to system for the fast charging of electric vehicles in various occasions, comprising an inverter bridge, a rectifier bridge, a transformer connected between the output side of the inverter bridge and the input side of the rectifier bridge, and an equivalent inductor representing the leakage inductance of a primary side of the transformer, wherein a DC input voltage is applied to the input side of the inverter bridge, and an output load is connected to the output side of the rectifier bridge. The phase-shift converter provided by the present invention is applicable to light-load cases, without influencing the operation in heavy-load cases, so the available load range of the present charger is extended compared to conventional phase shift converters.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims priority to Chinese Patent Application No. CN201610294588.5, filed on May 5, 2016, the entire contents of which are incorporated herein by reference. 
       TECHNICAL FIELD 
       [0002]    The present invention relates to a phase-shift converter based on zero-voltage switching and zero-current switching technologies, in particular to a soft-switching bidirectional phase-shift converter which is applicable to a system for quickly charging an electric vehicle in various occasions and which can realize a linear control of an output voltage and has a wider output load range. 
       BACKGROUND 
       [0003]    At present, the electric vehicle industry is developing rapidly and has a promising prospect, and related fast charging technologies are indispensable. It is crucial to develop high-performance vehicle fast-charging piles. Among various types of DC-DC converters, phase-shift converters are widely used as the basic topological structures of the chargers for electric vehicles, due to their advantages of low loss, high power density, fixed switching frequency, easy control, etc. However, due to its own limitations, the phase-shift converter topology has low output efficiency in the light load case, which influences the stability of the converter, and has no capability of linear control of output voltage. 
         [0004]    Chinese Patent CN104333229A discloses a phase-shift full-bridge switch converter. A phase-shift full-bridge switch converter capable of improving the reliability of a power semiconductor switch device is provided in view of the defects in the prior art wherein a resonant transformer circuit and a resonant transformer controller are additionally provided between a leading bridge arm and its isolated driving circuit, and a high-frequency transformer, and an output current sampling circuit are additionally provided between the output ground terminal of an output filter circuit and a phase-shift control circuit. 
         [0005]    However, in the researches on phase-shift converters currently done in the social and academic circles, including the above invention, the problem that the efficiency of a phase-shift converter becomes lower in light-load cases has not yet been solved, and the linear control of output voltage cannot be realized. 
       SUMMARY OF THE INVENTION 
       [0006]    In view of this, a main objective of the present invention is to provide a soft-switching bidirectional phase-shift converter which can realize a linear control of output voltage and has a wider output load range. By changing the control mode of each switching transistor, the phase-shift converter is applicable to the light-load case, without influencing the operation in heavy-load case. 
         [0007]    To achieve this objective, the present invention discloses a soft-switching bidirectional phase-shift converter with an extended load range, including an inverter bridge, a rectifier bridge, a transformer connected between the output side of the inverter bridge and the input side of the rectifier bridge, and an equivalent inductor representing the leakage inductance of a primary side of the transformer, wherein a DC input voltage is applied to the input side of the inverter bridge, and an output load is connected to the output side of the rectifier bridge. 
         [0008]    The inverter bridge includes a leading bridge arm for realizing zero-current switching, and a lagging bridge arm for realizing zero-voltage switching. 
         [0009]    The leading bridge arm includes: an inverter-side MOSFET switching transistor Q 1  and an antiparallel diode D 1  and a stray capacitor C 1  respectively corresponding to the inverter-side MOSFET switching transistor Q 1 , which are all connected in parallel, and an inverter-side MOSFET switching transistor Q 2 , and an antiparallel diode D 2  and a stray capacitor C 2  respectively corresponding to the inverter-side MOSFET switching transistor Q 2 , which are all connected in parallel; and, the lagging bridge arm includes an inverter-side MOSFET switching transistor Q 3  and an antiparallel diode D 3  and a stray capacitor C 3  respectively corresponding to the inverter-side MOSFET switching transistor Q 3  which are all connected in parallel, and an inverter-side MOSFET switching transistor Q 4  and an antiparallel diode D 4  and a stray capacitor C 4  respectively corresponding to the inverter-side MOSFET switching transistor Q 4  which are all connected in parallel. 
         [0010]    The drain of the inverter-side MOSFET switching transistor Q 1  is connected to the anode of the antiparallel diode D 1  and one terminal of the stray capacitor C 1 , while the source thereof is connected to the cathode of the antiparallel diode D 1  and the other terminal of the stray capacitor C 1 ; the drain of the inverter-side MOSFET switching transistor Q 2  is connected to the anode of the antiparallel diode D 2  and one terminal of the stray capacitor C 2 , while the source thereof is connected to the cathode of the antiparallel diode D 2  and the other terminal of the stray capacitor C 2 ; the drain of the inverter-side MOSFET switching transistor Q 1  is connected to the source of the inverter-side MOSFET switching transistor Q 2 . 
         [0011]    The drain of the inverter-side MOSFET switching transistor Q 3  is connected to the anode of the antiparallel diode D 3  and one terminal of the stray capacitor C 3 , while the source thereof is connected to the cathode of the antiparallel diode D 3  and the other terminal of the stray capacitor C 3 ; the drain of the inverter-side MOSFET switching transistor Q 4  is connected to the anode of the antiparallel diode D 4  and one terminal of the stray capacitor C 4 , while the source thereof is connected to the cathode of the antiparallel diode D 4  and the other terminal of the stray capacitor C 4 ; and, the drain of the inverter-side MOSFET switching transistor Q 3  is connected to the source of the inverter-side MOSFET switching transistor Q 4 . 
         [0012]    The anode of the DC input voltage is connected to the sources of the inverter-side MOSFET switching transistors Q 1  and Q 3 , while the cathode thereof is connected to the drains of the inverter-side MOSFET switching transistors Q 2  and Q 4 . 
         [0013]    The inverter bridge further includes an input filter capacitor which is located on the input side of the inverter bridge and connected to the DC input voltage in parallel; and, the anode of the DC input voltage is connected to the anode of the input filter capacitor, while the cathode thereof is connected to the cathode of the input filter capacitor. 
         [0014]    The rectifier bridge includes: a rectifier-side MOSFET switching transistor M 1 , and an antiparallel diode Dm 1  and a stray capacitor Cm 1  respectively corresponding to the rectifier-side MOSFET switching transistor M 1 , which are all connected in parallel; a rectifier-side MOSFET switching transistor M 2 , and an antiparallel diode Dm 2  and a stray capacitor Cm 2  respectively corresponding to the rectifier-side MOSFET switching transistor M 2 , which are all connected in parallel; a rectifier-side MOSFET switching transistor M 3 , and an antiparallel diode Dm 3  and a stray capacitor Cm 3  respectively corresponding to the rectifier-side MOSFET switching transistor M 3 , which are all connected in parallel; and a rectifier-side MOSFET switching transistor M 4 , and an antiparallel diode Dm 4  and a stray capacitor Cm 4  respectively corresponding to the rectifier-side MOSFET switching transistor M 4 , which are all connected in parallel. 
         [0015]    One terminal of the equivalent inductor is connected to the drain of the inverter-side MOSFET switching transistor Q 1  of the leading bridge arm while the other terminal thereof is connected to one terminal of the primary side of the transformer, and the other terminal of the primary side of the transformer is connected to the drain of the inverter-side MOSFET switching transistor Q 3  of the lagging bridge arm; a secondary-side dotted-terminal of a terminal of the transformer connected to the primary-side equivalent inductor is connected to the drain of the rectifier-side MOSFET switching transistor M 1 , and connected to the source of the rectifier-side MOSFET switching transistor M 2 , the anode of the antiparallel diode Dm 1 , the cathode of the antiparallel diode Dm 2 , one terminal of the stray capacitor Cm 1  and one terminal of the stray capacitor Cm 2 ; a secondary-side dotted-terminal of a terminal of the transformer not connected to the primary-side equivalent inductor is connected to the drain of the rectifier-side MOSFET switching transistor M 3 , and connected to the source of the rectifier-side MOSFET switching transistor M 4 , the anode of the antiparallel diode Dm 3 , the cathode of the antiparallel diode Dm 4 , one terminal of the stray capacitor Cm 3  and one terminal of the stray capacitor Cm 4 ; the cathode of the antiparallel diode Dm 1  is connected to the cathode of the antiparallel diode Dm 3 , and connected to the cathode of the output load, the other terminal of the stray capacitor Cm 1  and the other terminal of the stray capacitor Cm 3 ; and, the anode of the antiparallel diode Dm 2  is connected to the anode of the antiparallel diode Dm 4 , and connected to the cathode of the output load, the other terminal of the stray capacitor Cm 2  and the other terminal of the stray capacitor Cm 4 . 
         [0016]    The rectifier further includes an output filter capacitor located on the output side; the cathode of the antiparallel diode Dm 1  and the cathode of the antiparallel diode Dm 3  are connected to the anode of the output filter capacitor, and the anode of the output filter capacitor is connected to the anode of the output load; and, the anode of the antiparallel diode Dm 2  and the anode of the antiparallel diode Dm 4  are connected to the cathode of the output filter capacitor, and the cathode of the output filter capacitor is connected to the cathode of the output load. 
         [0017]    For the phase-shift converter system for quickly charging an electric vehicle based on zero-voltage switching and zero-current switching in the present invention, by optimizing on basis of a typical topology and changing the control mode of each switching transistor, the phase-shift converter is applicable to light-load cases, without influencing the operation in heavy-load cases, so the available load range of the present charger is extended. Under the optimal control and topological conditions, the present invention can realize the linear control of output voltage of the phase-shift converter, so that it is more advantageous for the control of output characteristics of the charger. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]      FIG. 1  is a schematic diagram of a topological structure of a phase-shift converter based on the zero-voltage and zero-current switching technology according to the present invention; 
           [0019]      FIG. 2  is a schematic diagram of control of switching ransistors in the circuit according to the present invention; 
           [0020]      FIG. 3  is an equivalent circuit diagram of a power transfer stage according to the present invention; 
           [0021]      FIG. 4  is a schematic diagram of DC characteristics of an improved phase-shift converter according to the present invention; 
           [0022]      FIG. 5  is a comparison diagram of an improved output linear voltage control and a conventional output non-linear voltage control according to the present invention; 
           [0023]      FIG. 6  is a schematic diagram of the maximum load current under the boundary zero-current switching according to the present invention; 
           [0024]      FIG. 7  is an equivalent circuit diagram of a freewheeling stage according to the present invention; 
           [0025]      FIG. 8  is a schematic diagram of an extended output load range according to the present invention; and 
           [0026]      FIG. 9  is a comparison diagram of power conversion efficiency of full load range according to the present invention. 
           [0027]      FIG. 10  is a comparison diagram of power conversion efficiency in light load case according to the present invention. 
           [0028]      FIG. 11  is a diagram of transformer primary voltage and current of the present invention at an output power of 115 W. 
           [0029]      FIG. 12  is a diagram of drain-source voltage, drain current and gate voltage of transistor Q 2  which shows its switching under zero current condition. 
           [0030]      FIG. 13  is a diagram of drain-source voltage, drain current and gate voltage of transistor Q 4  which shows its switching under zero voltage condition. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0031]    To further understand the structure and implementation effects of the present invention, details will be described hereinafter by preferred embodiments with reference to the accompanying drawings. 
         [0032]      FIG. 1  is a schematic diagram of a topological structure of a phase-shift converter based on the zero-voltage and zero-current switching technology according to the present invention, which is a core component of an electric vehicle charger. As shown in  FIG. 1 , the topological structure provided by the present invention is based on a conventional DC-DC phase-shift converter, but on the output diode rectifier bridge side, control is changed to be performed by a switching transistor having a reverse diode. The bidirectional phase-shift converter provided by the present invention includes an inverter bridge, a rectifier bridge, a transformer T connected between the output side of the inverter bridge and the input side of the rectifier bridge, and an equivalent inductor L lk  (not shown) representing the linkage inductance of a primary side of the transformer T. The ratio of transformation of the transformer T is N1:N2. A DC input voltage V in  is applied to the input side of the inverter bridge, and an output load R L  is connected to the output side of the rectifier bridge. 
         [0033]    The inverter bridge includes a leading bridge arm (i.e., left arm) for realizing zero-current switching and a lagging bridge arm (i.e., right arm) for realizing zero-voltage switching. The inverter bridge may further include an input filter capacitor C in  which is located on the input side and connected to the DC input voltage V in  in parallel. 
         [0034]    The leading bridge arm includes: an inverter-side MOSFET switching transistor Q 1 , and an antiparallel diode D 1  and a stray capacitor C 1  respectively corresponding to the inverter-side MOSFET switching transistor Q 1 , which are all connected in parallel, and an inverter-side MOSFET switching transistor Q 2 , and an antiparallel diode D 2  and a stray capacitor C 2  respectively corresponding to the inverter-side MOSFET switching transistor Q 2 , which are all connected in parallel. The drain of the inverter-side MOSFET switching transistor Q 1  is connected to the anode of the antiparallel diode D 1  and one terminal of the stray capacitor C 1 , while the source thereof is connected to the cathode of the antiparallel diode D 1  and the other terminal of the stray capacitor C 1 . The drain of the inverter-side MOSFET switching transistor Q 2  is connected to the anode of the antiparallel diode D 2  and one terminal of the stray capacitor C 2 , while the source thereof is connected to the cathode of the antiparallel diode D 2  and the other terminal of the stray capacitor C 2 . The drain of the inverter-side MOSFET switching transistor Q 1  is connected to the source of the inverter-side MOSFET switching transistor Q 2 . The lagging bridge arm includes: an inverter-side MOSFET switching transistor Q 3  and an antiparallel diode D 3  and a stray capacitor C 3  respectively corresponding to the inverter-side MOSFET switching transistor Q 3  which are all connected in parallel, and an inverter-side MOSFET switching transistor Q 4  and an antiparallel diode D 4  and a stray capacitor C 4  respectively corresponding to the inverter-side MOSFET switching transistor Q 4  which are all connected in parallel. The drain of the inverter-side MOSFET switching transistor Q 3  is connected to the anode of the antiparallel diode D 3  and one terminal of the stray capacitor C 3 , while the source thereof is connected to the cathode of the antiparallel diode D 3  and the other terminal of the stray capacitor C 3 . The drain of the inverter-side MOSFET switching transistor Q 4  is connected to the anode of the antiparallel diode D 4  and one terminal of the stray capacitor C 4 , while the source thereof is connected to the cathode of the antiparallel diode D 4  and the other terminal of the stray capacitor C 4 , The drain of the inverter-side MOSFET switching transistor Q 3  is connected to the source of the inverter-side MOSFET switching transistor Q 4 . 
         [0035]    The anode of the DC input voltage V in  is connected to the anode of the input filter capacitor C in  and also connected to the sources of the inverter-side MOSFET switching transistors Q 1  and Q 3 , while the cathode thereof is connected to the cathode of the input filter capacitor C in  and also connected to the drains of the inverter-side MOSFET switching transistors Q 2  and Q 4 . 
         [0036]    The rectifier bridge in the present invention includes: a rectifier-side MOSFET switching transistor M 1 , and an antiparallel diode Dm 1  and a stray capacitor Cm 1  respectively corresponding to the rectifier-side MOSFET switching transistor M 1 , which are all connected in parallel; a rectifier-side MOSFET switching transistor M 2 , and an antiparallel diode Dm 2  and a stray capacitor Cm 2  respectively corresponding to the rectifier-side MOSFET switching transistor M 2 , which are all connected in parallel; a rectifier-side MOSFET switching transistor M 3 , and an antiparallel diode Dm 3  and a stray capacitor Cm 3  respectively corresponding to the rectifier-side MOSFET switching transistor M 3 , which are all connected in parallel; and a rectifier-side MOSFET switching transistor M 4 , and an antiparallel diode Dm 4  and a stray capacitor Cm 4  respectively corresponding to the rectifier-side MOSFET switching transistor M 4 , which are all connected in parallel. The rectifier may further include an output filter capacitor C out  which is located on the output side and connected to the output load R L  in parallel. 
         [0037]    One terminal of the equivalent inductor L lk  is connected to the drain of the inverter-side MOSFET switching transistor Q 1  of the left arm while the other terminal thereof is connected to one terminal of the primary side of the transformer T, and the other terminal of the primary side of the transformer T is connected to the drain of the inverter-side MOSFET switching transistor Q 3  of the right arm. A secondary-side dotted-terminal of a terminal of the transformer T connected to the primary-side equivalent inductor L lk  is connected to the drain of the rectifier-side MOSFET switching transistor M 1  and connected to the source of the rectifier-side MOSFET switching transistor M 2 , the anode of the antiparallel diode Dm 1 , the cathode of the antiparallel diode Dm 2 , one terminal of the stray capacitor Cm 1  and one terminal of the stray capacitor Cm 2 . A secondary-side dotted-terminal of a terminal of the transformer T not connected to the primary-side equivalent inductor L lk  is connected to the drain of the rectifier-side MOSFET switching transistor M 3 , and connected to the source of the rectifier-side MOSFET switching transistor M 4 , the anode of the antiparallel diode Dm 3 , the cathode of the antiparallel diode Dm 4 , one terminal of the stray capacitor Cm 3  and one terminal of the stray capacitor Cm 4 . The cathode of the antiparallel diode Dm 1  is connected to the cathode of the antiparallel diode Dm 3 , and connected to the anode of the output filter capacitor C out , the cathode of the output load R L , the other terminal of the stray capacitor Cm 1  and the other terminal of the stray capacitor Cm 3 . The anode of the antiparallel diode Dm 2  is connected to the anode of the antiparallel diode Dm 4 , and connected to the cathode of the output filter capacitor C out , the cathode of the output load R L , the other terminal of the stray capacitor Cm 2  and the other terminal of the stray capacitor Cm 4 . 
         [0038]      FIG. 2  is a schematic diagram of control of the switching transistors in the circuit according to the present invention, where V GS1  to V GS4  represent driving signals of the inverter-side MOSFET switching transistors Q 1  to Q 4 , respectively, and V M1  to V M4  represent driving signals of the rectifier-side MOSFET switching transistors M 1  to M 4 , respectively. In heavy-load cases, the operation of the phase-shift converter is the same as that of a conventional phase-shift converter. However, in light-load cases, as shown in  FIG. 2 , there are six stages in a positive half cycle. 
         [0039]    In a stage of t 0 &lt;t&lt;t 1 , all the switching transistors M 1  to M 4  of the rectifier bridge have been turned off. On the inverter bridge side, the MOSFET switching transistor Q 4  is turned on, and the MOSFET switching transistor Q 2  is turned off at zero current since the primary-side current of the transformer T is zero. The main significance of this stage is to avoid the shoot-through short circuit between the MOSFET switching transistors Q 1  and Q 2 . In a state of t 1 &lt;t&lt;t 2 , the MOSFET switching transistors Q 1 , M 1  and M 4  are turned on at zero current, the DC input voltage V in  is applied to the primary side of the transformer T, and the secondary-side voltage of the transformer T is maintained at the output voltage V out  by the output filer capacitor C out . This stage is called a “left-arm zero-current conversion stage”. In a state of t 2 &lt;t&lt;t 3 , the MOSFET switching transistors Q 1  Q 4 , M 1  and M 4  are maintained in the ON state. This stage is a main power transfer stage. In a state of t 3 &lt;t&lt;t 4 , the MOSFET switching transistor Q 1  is maintained in the ON state, the MOSFET switching, transistor Q 4  is turned off, the energy stored in the equivalent inductor L lk  starts to charge the stray capacitor C 4  and meanwhile discharge the C 3 , and the antiparallel diode D 3  is continuously turned on until the voltage of the stray capacitor C 3  becomes zero. Hereafter, the MOSFET switching transistor Q 3  is turned on at zero voltage, and the MOSFET switching transistors M 1  and M 4  are turned off at this stage. This stage is called a “right-arm zero-voltage conversion stage”. In a state of t 4 &lt;t&lt;t 5 , the MOSFET switching transistors Q 1  and Q 3  are continuously turned on, the primary-side voltage of the transformer T is zero, the energy stored in the equivalent inductor L lk  is continuously transferred to the rectifier bridge side through the antiparallel diodes Dm 1  and Dm 4  and then transferred to the load, and the secondary-side voltage of the transformer T is continuously maintained at V out . This stage is called a “freewheeling stage”. In a state of t 5 &lt;t&lt;t 6 , the MOSFET switching transistors Q 1  and Q 3  are maintained in the ON state, the primary-side current of the transformer T is reduced to zero, and the antiparallel diodes Dm 1  and Dm 2  are biased reversely, so the network consisting of the output filter capacitor C out  and the output load R L  is isolated from the rectifier bridge. As the output filter capacitor C out  is large enough, the output voltage V out  may remain almost unchanged. 
         [0040]    As shown in  FIG. 2 , the working principle and mode in the negative half cycle in the light-load case is completely the same as that in the positive half cycle. 
         [0041]      FIG. 3  is an equivalent circuit diagram of the power transfer stage according to the present invention. At this stage, energy is transferred from the output-side voltage to the load. i on (t) represents the primary-side current of the transformer at the power transfer stage, i off (t) represents the primary-side current of the transformer at the freewheeling stage, v c (t) represents the voltage of an equivalent output filter capacitor, i c (t) represents the current of the equivalent output filter capacitor, and i r (t) represents the current of an equivalent output load. The equivalent formulae of the circuits are as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       L 
                       lk 
                     
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                       d 
                       dt 
                     
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                         i 
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                         ( 
                         t 
                         ) 
                       
                     
                   
                   = 
                   
                     
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                           ( 
                           t 
                           ) 
                         
                       
                     
                   
                 
               
               
                 
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                   1 
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                       ( 
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                           ( 
                           t 
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                     + 
                     
                       
                         
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                           c 
                         
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                           ( 
                           t 
                           ) 
                         
                       
                       n 
                     
                   
                 
               
               
                 
                   ( 
                   2 
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                     n 
                     · 
                     
                       
                         v 
                         c 
                       
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                         ( 
                         t 
                         ) 
                       
                     
                   
                   = 
                   
                     
                       
                         
                           i 
                           r 
                         
                          
                         
                           ( 
                           t 
                           ) 
                         
                       
                       n 
                     
                     · 
                     
                       n 
                       2 
                     
                     · 
                     
                       R 
                       L 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       
                         i 
                         c 
                       
                        
                       
                         ( 
                         t 
                         ) 
                       
                     
                     n 
                   
                   = 
                   
                     
                       
                         C 
                         out 
                       
                       
                         n 
                         2 
                       
                     
                     · 
                     
                       
                         d 
                         dt 
                       
                        
                       
                         [ 
                         
                           n 
                           · 
                           
                             
                               v 
                               c 
                             
                              
                             
                               ( 
                               t 
                               ) 
                             
                           
                         
                         ] 
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0042]    The equations (1) to (4) are solved and then Laplace transform performed, so as to obtain the primary-side current i on (s): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       on 
                     
                      
                     
                       ( 
                       s 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         
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                             lk 
                           
                         
                         + 
                         
                           1 
                           
                             
                               C 
                               out 
                             
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                               R 
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                               out 
                             
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                               lk 
                             
                           
                         
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                             2 
                           
                           
                             
                               C 
                               out 
                             
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                           lk 
                         
                       
                       
                         
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                               out 
                             
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                               L 
                               lk 
                             
                           
                         
                         + 
                         
                           
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                               C 
                               out 
                             
                              
                             
                               L 
                               lk 
                             
                              
                             
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                               L 
                             
                           
                         
                       
                     
                      
                     
                       nV 
                       out 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0043]    wherein s=jω, ω=2πƒ, and 
         [0000]    
       
         
           
             f 
             = 
             
               
                 1 
                 t 
               
               . 
             
           
         
       
     
         [0044]    Therefore, inverse Laplace transform may be performed on equation (5) to obtain i on (t): 
         [0000]    
       
         
           
             
               
                 
                   
                     
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                       on 
                     
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                          
                         
                           ( 
                           
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                     + 
                     
                       
                         ( 
                         
                           
                             
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                                 n 
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                                   R 
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                                  
                                 
                                   ( 
                                   
                                     
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                                       in 
                                     
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                                   ) 
                                 
                               
                             
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                              
                             
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                              
                             
                               
                                 
                                   4 
                                    
                                   
                                     n 
                                     2 
                                   
                                    
                                   
                                     C 
                                     out 
                                   
                                    
                                   
                                     L 
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                         sin 
                          
                         
                           ( 
                           
                             θ 
                             · 
                             t 
                           
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0045]    Wherein 
         [0000]    
       
         
           
             θ 
             = 
             
               
                 
                   
                     
                       4 
                        
                       
                         n 
                         2 
                       
                        
                       
                         C 
                         out 
                       
                        
                       
                         L 
                         lk 
                       
                        
                       
                         R 
                         L 
                         2 
                       
                     
                     - 
                     
                       L 
                       lk 
                       2 
                     
                   
                 
                 
                   2 
                    
                   
                     C 
                     out 
                   
                    
                   
                     L 
                     lk 
                   
                    
                   
                     R 
                     L 
                   
                 
               
               . 
             
           
         
       
     
         [0046]    If it is assumed that the output filter capacitor C out  is large enough and the leakage inductance L lk  is small, the following in equations may be obtained: 
         [0000]      4n 2 C out L lk R L   2 &gt;&gt;L lk   2    
         [0000]      2n 2 C out R L   2 V in  &gt;&gt;L lk V in    
         [0000]      2C out R L &lt;&lt;1. 
         [0047]    Thus, the equation (6) may be simplified as follows (wherein ω s  represents the switching angular frequency, ω 0  represents the output resonance frequency, and 
         [0000]    
       
         
           
             
               
                 
                   ω 
                   o 
                 
                 = 
                 
                   n 
                   
                     
                       
                         L 
                         lk 
                       
                        
                       
                         C 
                         out 
                       
                     
                   
                 
               
               ) 
             
              
             
               : 
             
           
         
       
     
         [0000]    
       
         
           
             
               
                 i 
                 on 
               
                
               
                 ( 
                 t 
                 ) 
               
             
             ≈ 
             
               
                 
                   
                     V 
                     in 
                   
                   - 
                   
                     nV 
                     out 
                   
                 
                 
                   Z 
                   o 
                 
               
                
               
                 
                   sin 
                    
                   
                     ( 
                     
                       
                         ω 
                         o 
                       
                        
                       t 
                     
                     ) 
                   
                 
                 . 
               
             
           
         
       
     
         [0048]    At the end of this stage (t=DT/2, wherein D represents the phase-shift duty ratio and T represents the period), a peak value of the primary-side current is as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     peak 
                   
                   ≈ 
                   
                     D 
                      
                     
                         
                     
                      
                     π 
                      
                     
                       
                         ω 
                         o 
                       
                       
                         ω 
                         s 
                       
                     
                      
                     
                       
                         
                           V 
                           in 
                         
                         - 
                         
                           nV 
                           out 
                         
                       
                       
                         Z 
                         o 
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
         [0000]    wherein Z 0  represents the characteristic impedance, and 
         [0000]    
       
         
           
             
               Z 
               o 
             
             = 
             
               n 
                
               
                 
                   
                     
                       L 
                       lk 
                     
                     
                       C 
                       out 
                     
                   
                 
                 . 
               
             
           
         
       
     
         [0049]    If it is assumed that the input energy W in  is equal to the output energy W out , 
         [0000]    
       
         
           
             
               
                 W 
                 in 
               
               = 
               
                 
                   1 
                   2 
                 
                  
                 
                   V 
                   in 
                 
                  
                 
                   I 
                   peak 
                 
                  
                 D 
                  
                 
                   T 
                   2 
                 
               
             
             , 
             
               
                 W 
                 out 
               
               = 
               
                 
                   
                     V 
                     out 
                     2 
                   
                   
                     R 
                     L 
                   
                 
                  
                 
                   T 
                   2 
                 
               
             
             , 
           
         
       
     
         [0000]    then: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     peak 
                   
                   = 
                   
                     
                       2 
                        
                       
                         V 
                         out 
                         2 
                       
                     
                     
                       
                         DR 
                         L 
                       
                        
                       
                         V 
                         in 
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0050]    The equations (7) and (8) are solved to obtain the ratio of transformation of the voltage input and voltage output of the phase-shift converter (wherein ƒ s  represents the switching angular frequency, and 
         [0000]    
       
         
           
             
               
                 
                   f 
                   s 
                 
                 = 
                 
                   
                     ω 
                     s 
                   
                   
                     2 
                      
                     π 
                   
                 
               
               ) 
             
              
             
               : 
             
           
         
       
     
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       out 
                     
                     
                       V 
                       in 
                     
                   
                   = 
                   
                     
                       1 
                       2 
                     
                      
                     
                       [ 
                       
                         
                           
                             
                               
                                 ( 
                                 
                                   
                                     
                                       nR 
                                       L 
                                     
                                      
                                     
                                       D 
                                       2 
                                     
                                   
                                   
                                     4 
                                      
                                     
                                       L 
                                       lk 
                                     
                                      
                                     
                                       f 
                                       s 
                                     
                                   
                                 
                                 ) 
                               
                               2 
                             
                             + 
                             
                               4 
                                
                               
                                 ( 
                                 
                                   
                                     
                                       R 
                                       L 
                                     
                                      
                                     
                                       D 
                                       2 
                                     
                                   
                                   
                                     4 
                                      
                                     
                                       L 
                                       lk 
                                     
                                      
                                     
                                       f 
                                       s 
                                     
                                   
                                 
                                 ) 
                               
                             
                           
                         
                         - 
                         
                           ( 
                           
                             
                               
                                 nR 
                                 L 
                               
                                
                               
                                 D 
                                 2 
                               
                             
                             
                               4 
                                
                               
                                 L 
                                 lk 
                               
                                
                               
                                 f 
                                 s 
                               
                             
                           
                           ) 
                         
                       
                       ] 
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
         [0051]    To check whether there is a linear relation between the output voltage and the phase-shift duty ratio D, a differential operation is performed on the equation (9) with respect to D: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       d 
                       dD 
                     
                      
                     
                       ( 
                       
                         
                           V 
                           out 
                         
                         
                           V 
                           in 
                         
                       
                       ) 
                     
                   
                   = 
                   
                     
                       
                         
                           D 
                           2 
                         
                          
                         
                           n 
                           2 
                         
                          
                         
                           R 
                           L 
                         
                       
                       + 
                       
                         8 
                          
                         
                           L 
                           lk 
                         
                          
                         
                           f 
                           s 
                         
                       
                       - 
                       
                         
                           
                             D 
                             2 
                           
                            
                           
                             n 
                             2 
                           
                            
                           
                             
                               R 
                               L 
                             
                              
                             
                               ( 
                               
                                 
                                   16 
                                    
                                   
                                     L 
                                     lk 
                                   
                                    
                                   
                                     f 
                                     s 
                                   
                                 
                                 + 
                                 
                                   
                                     D 
                                     2 
                                   
                                    
                                   
                                     n 
                                     2 
                                   
                                    
                                   
                                     R 
                                     L 
                                   
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                     
                       
                         
                           4 
                            
                           
                             L 
                             lk 
                           
                            
                           
                             f 
                             s 
                           
                         
                         
                           DnR 
                           L 
                         
                       
                        
                       
                         
                           
                             D 
                             2 
                           
                            
                           
                             n 
                             2 
                           
                            
                           
                             
                               R 
                               L 
                             
                              
                             
                               ( 
                               
                                 
                                   16 
                                    
                                   
                                     L 
                                     lk 
                                   
                                    
                                   
                                     f 
                                     s 
                                   
                                 
                                 + 
                                 
                                   
                                     D 
                                     2 
                                   
                                    
                                   
                                     n 
                                     2 
                                   
                                    
                                   
                                     R 
                                     L 
                                   
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
         [0052]    As the denominator on the right side of the equation (10) is constantly greater than zero, it is only necessary to verify whether the value of the numerator is positive or negative. The value of the numerator is assigned to M: 
         [0000]        M=D   2   n   2   R   L +8 L   lk ƒ s −√{square root over ( D   2   n   2   R   L (16 L   lk ƒ s   D   2   n   2   R   L ))}  (11).
 
         [0053]    If M&lt;0, then: 
         [0000]        D   2   n   2   R   L +8 L   lk ƒ s −√{square root over ( D   2   n   2   R   L (16 L   lk ƒ s   D   2   n   2   R   L ))}         (8 L   lk ƒ s ) 2 &gt;0.
 
         [0054]    As (8L lk ƒ s ) 2  is constantly greater than zero, both M and 
         [0000]    
       
         
           
             
               d 
               dD 
             
              
             
               ( 
               
                 
                   V 
                   out 
                 
                 
                   V 
                   in 
                 
               
               ) 
             
           
         
       
     
         [0000]    are constantly greater than zero when 0≦D≦1. Therefore, the output voltage of the converter always increases with the increase of the phase-shift duty ratio D. 
         [0055]      FIG. 4  is a schematic diagram of DC characteristics of an improved phase-shift converter according to the present invention, and  FIG. 5  is a comparison diagram of an improved bidirectional phase-shift DC-DC converter (linear voltage control) and a typical directional phase-shift DC-DC converter (nonlinear voltage control) according to the present invention. The correctness of the mathematical calculations is verified by testing and simulating platforms. 
         [0056]      FIG. 6  is a schematic diagram of the maximum load current under the boundary zero-current switching according to the present invention, showing four typical primary-side current cases. In (a) of  FIG. 6 , the converter drives a light load in a left-arm zero-current switching mode. When the load is gradually increased to a boundary value, as shown in (b) of  FIG. 6 , the zero-current switching may still be maintained. However, if the load exceeds the boundary value, the switching transistor whose left arm is in the ON state cannot operate in a zero-current switching mode, as shown in (c) of  FIG. 6 . Of course, if the load is high enough, the converter will operate in a normal heavy-load mode, as shown in (d) of  FIG. 6 . 
         [0057]      FIG. 7  is an equivalent circuit diagram of the freewheeling stage according to the present invention. Based on the circuit diagram, by mathematical calculations, the maximum load current that can be withstood by the left arm while realizing zero-current switching is: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     
                       ZCS 
                        
                       
                         ( 
                         max 
                         ) 
                       
                     
                   
                   = 
                   
                     
                       
                         V 
                         in 
                       
                        
                       
                         ( 
                         
                           
                             
                               n 
                               2 
                             
                              
                             
                               R 
                               L 
                             
                           
                           - 
                           
                             4 
                              
                             
                               L 
                               lk 
                             
                              
                             
                               f 
                               s 
                             
                           
                         
                         ) 
                       
                     
                     
                       
                         n 
                         3 
                       
                        
                       
                         R 
                         L 
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
         [0058]    The minimum load current that can be withstood by the right arm while realizing zero-voltage switching is: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     
                       ZVS 
                        
                       
                         ( 
                         min 
                         ) 
                       
                     
                   
                   = 
                   
                     
                       2 
                        
                       
                         V 
                         in 
                       
                     
                     
                       
                         
                           nR 
                           L 
                         
                          
                         
                           V 
                           in 
                         
                       
                       + 
                       
                         
                           
                             
                               nR 
                               L 
                             
                              
                             
                               V 
                               in 
                             
                           
                           + 
                           
                             
                               
                                 4 
                                  
                                 
                                   R 
                                   L 
                                 
                               
                               
                                 
                                   C 
                                   sum 
                                 
                                  
                                 
                                   f 
                                   s 
                                 
                               
                             
                              
                             
                               
                                 ( 
                                 
                                   
                                     V 
                                     in 
                                   
                                   - 
                                   
                                     nV 
                                     out 
                                   
                                 
                                 ) 
                               
                               2 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
         [0000]    wherein C sum C 3 +C 4 C xƒmr , C xƒmr  represents the equivalent capacitance of the transformer T. 
         [0059]      FIG. 8  is a schematic diagram of an extended output load range according to the present invention, and also shows the boundary value of the load current in equations (12) and (13). The conventional phase-shift converter is merely applicable to the heavy-load mode. In contrast, by the zero-current and zero-voltage switching design of the left and right arms, the phase-shift converter of the present invention realizes the stable operation in the light-load case, so that the output load range, including light load and heavy load, of the phase-shift converter is extended. 
         [0060]      FIG. 9  is a comparison diagram of the power conversion efficiency of full load range according to the present invention, and  FIG. 10  is a comparison diagram of the power conversion efficiency at light load case according to the present invention. The experimental data indicates that the conventional phase-shift transformer has low efficiency in light-load cases. As shown in  FIG. 10 , the efficiency at a load of 115 W is about 76.5% only. However, in the present invention, the efficiency of the improved converter at the output power of 115 W may reach 83.4%. The improvement of the efficiency is made, mainly because the zero-current switching of the inverter-side switching transistors greatly reduces the switching loss in the light-load case. 
         [0061]    Experiments have proved that the improved phase-shift converter of the present invention may stably operate in the light-load case, and the output voltage linearly changes with the phase-shift duty ratio  0 . 
         [0062]      FIG. 11  is a diagram of transformer primary voltage and current of the present invention at output power of 115 W in the experiments.  FIG. 12  is a diagram of drain-source voltage, drain current and gate voltage of transistor Q 2  which shows its switching under zero current condition.  FIG. 13  is a diagram of drain-source voltage, drain current and gate voltage of transistor Q 4  which shows its switching under zero voltage condition. The primary current and voltage of transformer in  FIG. 11  conform to the proposed theory very well, and the ZCS and ZVS are perfectly accomplished by Q 2  at left-leg and Q 4  at right-leg of inverter bridge as illustrated in  FIG. 12  and  FIG. 13  respectively, where Q 2  switches on under zero current at t=0 μp, and Q 4  switches on under zero voltage at t=6 μs when the drain-source voltage of MOSFET already reaches 0V. 
         [0063]    The foregoing description merely shows preferred embodiments of the present invention and is not intended to limit the protection scope of the present invention.