Abstract:
A digital circuit and a method for operating the same. The digital circuit includes (a) M×N regular cells electrically arranged in M rows and N columns, (b) N reference cells corresponding one-to-one to the N columns, and (c) N comparing circuits corresponding one-to-one to the N columns. Each regular cell is electrically coupled to a comparing circuit. Each reference cell is electrically coupled to the associated comparing circuit. Each regular cell includes a first tap node. Each reference cell includes P tap nodes. If a first voltage of the first tap node of a regular cell is between two voltages of two tap nodes of the P tap nodes of the associated reference cell, then the associated comparing circuit is capable of generating a first signal. If the first voltage is not between the two voltages, then the associated comparing circuit is capable of generating a second signal.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates generally to semiconductor circuits and more particularly to semiconductor circuits capable of self detecting their own defects. 
       BACKGROUND OF THE INVENTION 
       [0002]    Conventional semiconductor circuits may have defects. Therefore, it is necessary to test the semiconductor circuits for those defects. As a result, there is a need for a semiconductor circuit (and a method for operating the same) that is capable of self testing. 
       SUMMARY OF THE INVENTION 
       [0003]    The present invention provides a digital circuit operation method, comprising providing (a) M×N regular cells electrically arranged in M rows and N columns, M and N being positive integers, (b) N reference cells corresponding one-to-one to the N columns, and (c) N comparing circuits corresponding one-to-one to the N columns, wherein each regular cell of the M×N regular cells is electrically coupled to a comparing circuit of the N comparing circuits associated with a column in which the regular cell resides, wherein each reference cell of the N reference cells is electrically coupled to the associated comparing circuit of the N comparing circuits, wherein each regular cell of the M×N regular cells comprises a first tap node, and wherein each reference cell of the N reference cells comprises P tap nodes, P being an integer greater than 1; selecting a regular cell of the M×N regular cells for testing; using a comparing circuit associated with the regular cell, in response to a first voltage of the first tap node of the regular cell being between two voltages of two tap nodes of the P tap nodes of the associated reference cell, to generate a first signal indicating that the regular cell is in good condition; and using the comparing circuit associated with the regular cell, in response to the first voltage of the first tap node of the regular cell not being between the two voltages of the two tap nodes of the P tap nodes of the associated reference cell, to generate a second signal indicating that the regular cell is not in good condition. 
         [0004]    The present invention provides a semiconductor circuit (and a method for operating the same) that is capable of self testing. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0005]      FIG. 1  shows a digital circuit, in accordance with embodiments of the present invention. 
           [0006]      FIG. 2  shows another digital circuit, in accordance with embodiments of the present invention. 
           [0007]      FIG. 2A  shows one embodiment of a MUX circuit of  FIG. 2 . 
           [0008]      FIG. 3  shows a comparator as one embodiment of comparators of comparing circuits of  FIGS. 1 and 2 , in accordance with embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0009]      FIG. 1  shows a digital circuit  100 , in accordance with embodiments of the present invention. More specifically, the digital circuit  100  comprises four regular cells  110 R 0 C 0 ,  110 R 0 C 1 ,  110 R 1 C 0 , and  110 R 1 C 1  (also collectively referred to as regular cells  110 ) arranged in two rows and two columns. The digital circuit  100  further comprises four pass gate circuits  120 R 0 C 0 ,  120 R 0 C 1 ,  120 R 1 C 0 , and  120 R 1 C 1  corresponding to the four regular cells  110 R 0 C 0 ,  110 R 0 C 1 ,  110 R 1 C 0 , and  110 R 1 C 1 , respectively. 
         [0010]    In one embodiment, the digital circuit  100  further comprises two reference cells  130 C 0  and  130 C 1  corresponding to the two columns of the regular cells  110 . More specifically, the reference cell  130 C 0  corresponds to the regular cells  110 R 0 C 0  and  110 R 1 C 0 , whereas the reference cell  130 C 1  corresponds to the regular cells  110 R 0 C 1  and  110 R 1 C 1 . The digital circuit  100  further comprises two comparing circuits  140 C 0  and  140 C 1  corresponding to the reference cells  130 C 0  and  130 C 1 , respectively. 
         [0011]    In one embodiment, the regular cell  110 R 0 C 0  comprises resistors R 00   a  and R 00   b  coupled together in series and coupled to Vcc and ground through a PFET (p-channel field effect transistor) T 00   b  and an NFET (n-channel field effect transistor) T 00   a  as shown in  FIG. 1 . The structures of the regular cells  110 R 0 C 1 ,  110 R 1 C 0 , and  110 R 1 C 1  are similar to the structure of the regular cell  110 R 0 C 0 . 
         [0012]    With reference to the regular cell  110 R 0 C 0 , in one embodiment, a tap node N 00  of the two resistors R 00   a  and R 00   b  is electrically connected to the comparing circuit  140 C 0  through the pass gate circuit  120 R 0 C 0 . More specifically, the tap node N 00  is electrically connected to (i) an input I 1   a  of a comparator  142 C 0   a  of the comparing circuit  140 C 0  and (ii) an input I 2   b  of a comparator  142 C 0   b  of the comparing circuit  140 C 0 . Similarly, tap nodes N 01 , N 10 , and N 11  of the regular cells  110 R 0 C 1 ,  110 R 1 C 0 , and  110 R 1 C 1 , respectively, are electrically connected to the corresponding comparing circuits  140 C 0  and  140 C 1  in a manner similar to the manner in which the tap node N 00  of the regular cell  110 R 0 C 0  is electrically connected to the comparing circuit  140 C 0 . 
         [0013]    In one embodiment, the reference cell  130 C 0  comprises resistors  130 R 0   a ,  130 R 0   b,  and  130 R 0   c  coupled together in series and coupled to Vcc and ground through a PFET  130 T 0   b  and a NFET  130 T 0   a,  respectively, as shown in  FIG. 1 . A tap node NC 01  of two resistors  130 R 0   a  and  130 R 0   b  is electrically connected to an input I 2   a  of the comparator  142 C 0   a  of the comparing circuit  140 C 0 . A tap node NC 02  of two resistors  130 R 0   b  and  130 R 0   c  is electrically connected to an input I 1   b  of the comparator  142 C 0   b  of the comparing circuit  140 C 0 . The structure of the reference cell  130 C 1  is similar to the structure of the reference cell  130 C 0 . Tap nodes of the reference cell  130 C 1  are electrically connected to the comparators  142 C 1   a  and  142 C 1   b  of the comparing circuit  140 C 1  in a manner similar to the manner in which the tap nodes NC 01  and NC 02  of the reference cell  130 C 0  are electrically connected to the comparators  142 C 0   a  and  142 C 0   b  of the comparing circuit  140 C 0 . 
         [0014]    In one embodiment, the resistors R 00   a  and R 00   b  of the regular cell  110 R 0 C 0  are two adjacent segments of a single regular metal line R 00   a +R 00   b  in an interconnect layer (not shown) of an integrated circuit (not shown). Similarly, the resistors R 10   a  and R 10   b  of the regular cell  110 R 1 C 0 , the resistors R 01   a  and R 01   b  of the regular cell  110 R 0 C 1 , and the resistors R 11   a  and R 11   b  of the regular cell  110 R 1 C 1  can be adjacent segments of single regular metal lines R 10   a +R 10   b , R 01   a +R 01   b,  and R 11   a +R 11   b,  respectively. 
         [0015]    In one embodiment, the resistors  130 R 0   a,    130 R 0   b,  and  130 R 0   c  of the reference cell  130 C 0  are three adjacent segments of a single reference metal line  130 R 0   a − 130 R 0   b + 130 R 0   c  in an interconnect layer (not shown) of the integrated circuit. Similarly, the resistors  130 R 1   a,    130 R 1   b,  and  130 R 1   c  of the reference cell  130 C 1  can be three adjacent segments of a single reference metal line  130 R 1   a + 130 R 1   b + 130 R 1   c.    
         [0016]    The digital circuit  100  is capable of testing the regular metal lines R 00   a +R 00   b,  R 10   a +R 10   b,  R 01   a +R 01   b,  and R 11   a +R 11   b.  For instance, if the regular metal line R 00   a +R 00   b  is in good condition, then the output signal OUT 0  of the comparing circuit  140 C 0  is pulled high. If the regular metal line R 00   a +R 00   b  is not in good condition (e.g., open circuit), then the output signal OUT 0  of the comparing circuit  140 C 0  is pulled low. 
         [0017]    In one embodiment, the line testing operation of the digital circuit  100  is as follows. Assume that the regular metal line R 00   a +R 00   b  is to be tested. Accordingly, a bitline BL 0  is pulled high and a wordline WL 0  is pulled low resulting in the regular metal line R 00   a +R 00   b  being selected for testing, whereas a wordline WL 1  is pulled high resulting in the regular metal line R 10   a +R 10   b  not being selected for testing. More specifically, as a result of the bitline BL 0  being high and the wordline WL 0  being low, the NFET T 00   a  and the PFET T 00   b  are both turned on resulting in the regular metal line R 00   a +R 00   b  being connected to ground and Vcc. Also as a result of the bitline BL 0  being high and the wordline WL 0  being low, the pass gate circuit  120 R 0 C 0  is turned on resulting in the tap node N 00  being electrically connected to (i) the input I 1   a  of the comparator  142 C 0   a  of the comparing circuit  140 C 0  and (ii) the input I 2   b  of the comparator  142 C 0   b  of the comparing circuit  140 C 0  through the pass gate circuit  120 R 0 C 0 . Also as a result of the bitline BL 0  being high, (i) the NFET  130 T 0   a  and the PFET I  30 T 0   b  are both turned on resulting in the reference metal line  13 ORO a + 13 OR 0   b + 130 R 0   c  being electrically connected to ground and Vcc and (ii) the comparators  142 C 0   a  and  142 C 0   b  are enabled. 
         [0018]    With reference to the reference cell  130 C 0 , assume further that (i) the tap nodes NC 01  and NC 02  are at locations such that the length ratio of the resistors  130 R 0   a ,  130 R 0   b , and  130 R 0   c  is 1:8:1 and (ii) the cross-section area of the reference metal line  130 R 0   a + 130 R 0   b + 130 RO c  is the same along the length of the reference metal line  130 R 0   a + 130 R 0   b + 130 R 0   c . As a result, the ratio of the resistances of the resistors  130 R 0   a ,  130 R 0   b , and  130 R 0   c  is also 1:8:1. Assume further that the Vcc=10V. As a result, the voltage at the tap node NC 02  V(NC 02 )&lt;9V (voltage divider rule) resulting in V(I 1   b )=9V. Also as a result of Vcc=10V, V(NC 01 )=1V (voltage divider rule) resulting in V(I 2   a )=1 V. 
         [0019]    Assume that the regular metal line R 00   a +R 00   b  is in good condition (e.g., no open circuit). Assume further that (i) the tap node N 00  is at middle point of the regular metal line R 00   a +R 00   b  and (ii) the cross-section area of the regular metal line R 00   a +R 00   b  is the same along the length of the regular metal line R 00   a +R 00   b . As a result, the ratio of the resistances of the resistors R 00   a  and R 00   b  is 5:5. As a result, V(N 00 )=5V resulting in the input I 2   b  of the comparator  142 C 0   b  and the input I 1   a  of the comparator  142 C 0   a  receiving the voltage of 5 volts from tap node N 00  through the pass gate circuit  120 R 0 C 0 . As a result of V(I 1   a )=5V and V(I 2   a )=1V, the output signal of the comparator  142 C 0   a  is pulled low, As a result of V(I 1   b )=9V and V(I 2   b )=5V, the output signal of the comparator  142 C 0   b  is pulled low. As a result of both the output signals of both the comparators  142 C 0   a  and  142 C 0   b  being low, the output signal OUT 0  of the NOR gate  144 C 0  is pulled high. This indicates that the regular metal line R 00   a +R 00   b  is in good condition. 
         [0020]    Assume alternatively that the regular metal line R 00   a +R 00   b  has an open circuit in the resistor R 00   a . As a result, V(N 00 )=10V (=Vcc) resulting in the input I 2   b  of the comparator  142 C 0   b  and the input I 1   a  of the comparator  142 C 0   a  receiving the voltage of 10 volts from tap node N 00  through the pass gate circuit  120 R 0 C 0 . As a result of V(I 1   a )=10V and V(I 2   a )=1V, the output signal of the comparator  142 C 0   a  is pulled low. As a result of V(I 1   b )=9V and V(I 2   b )=10V, the output signal of the comparator  142 C 0   b  is pulled high. As a result of the output signal of the comparator  142 C 0   a  being low and the output signal of the comparator  142 C 0   b  being high, the output signal OUT 0  of the NOR gate  144 C 0  is pulled low. This indicates that the regular metal line R 00   a +R 00   b  is not in good condition. 
         [0021]    Assume alternatively that the regular metal line R 00   a +R 00   b  has an open circuit in the resistor R 00   b . As a result, V(N 00 )=0V (the tap node N 00  is connected to ground) resulting in the input I 2   b  of the comparator  142 C 0   b  and the input I 1   a  of the comparator  142 C 0   a  receiving the voltage of 0 volt from tap node N 00  through the pass gate circuit  120 R 0 C 0 . As a result of V(I 1   a )=0V and V(I 2   a )=1V, the output signal of the comparator  142 C 0   a  is pulled high. As a result of V(I 1   b ) 9V and V(I 2   b )=0V, the output signal of the comparator  142 C 0   b  is pulled low. As a result of the output signal of the comparator  142 C 0   a  being high and the output signal of the comparator  142 C 0   b  being low, the output signal OUT 0  of the NOR gate  144 C 0  is pulled low. This indicates that the regular metal line R 00   a +R 00   b  is not in good condition. 
         [0022]    In one embodiment, the regular metal lines R 10   a +R 10   b , R 01   a +R 01   b , or R 11   a +R 11   b  can be tested in a manner similar to the manner in which the regular metal line R 00   a +R 00   b  is tested. It should be noted that the metal lines of regular cells in a same row can be tested simultaneously. For instance, the regular metal lines R 00   a +R 00   b  and R 01   a +R 01   b  can be tested simultaneously. More specifically, the bitlines BL 0  and BL 1  are pulled high and the wordline WL 0  is pulled low resulting in the regular metal lines R 00   a +R 00   b  and R 01   a +R 01   b  being selected for testing, whereas the wordline WL 1  is pulled high resulting in the metal lines R 10   a +R 10   b  and R 11   a +R 11   b  are not selected for testing. 
         [0023]    In summary, if V(N 00 ) &lt;V(NC 01 ) or V(N 00 )&gt;V(NC 02 ) (i.e., V(N 00 ) is not between V(NC 01 ) and V(NC 02 )), then the output signal OUT 0  of the comparing circuit  140 C 0  is pulled low indicating that the regular metal line R 00   a +R 00   b  is not in good condition. If V(N 00 )&gt;V(NC 01 ) and V(N 00 )&lt;V(NC 02 ) (i.e., V(N 00 ) is between V(NC 01 ) and V(NC 02 )), then the output signal OUT 0  of the comparing circuit  140 C 0  is pulled high and the regular metal line R 00   a +R 00   b  can be considered being in good condition. In other words, the output signal OUT 0  of the comparing circuit  140 C 0  indicates whether the selected regular metal line R 00   a +R 00   b  is in good condition. 
         [0024]    In one embodiment, the tap nodes N 00 , NC 01 , and NC 02  are disposed such that V(N 00 ) is between V(NC 01 ) and V(CN 02 ) in the case which the metal line R 00   a +R 00   b  is in good condition. Accordingly, the tap nodes N 00 , NC 01 , and NC 02  are disposed such that 
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         [0000]    wherein L(R) represents the length of resistor R provided that the segments of the resistors  130 R 0   a ,  130 R 0   b ,  130 R 0   c , R 00   a,  and R 00   b  are made of the same material. 
         [0025]      FIG. 2  shows a digital circuit  200 , in accordance with embodiments of the present invention. More specifically, the digital circuit  200  is similar to a column of the digital circuit  100  of  FIG. 1 , except that (i) the digital circuit  200  further comprises a MUX circuit  250  and (ii) a reference cell  230  of the digital circuit  200  comprises five resistors  230 R 1 ,  230 R 2 ,  230 R 3 ,  230 R 4 , and  230 R 5 . These five resistors can be five adjacent segments of a single reference metal line  230 R. It should be noted that the digital circuit  200  comprises multiple regular cells, but only one regular cell  210  is shown in  FIG. 2  for simplicity. 
         [0026]    In one embodiment, four tap nodes NA, NB, NC, and ND of the reference metal line  230 R are electrically connected to four inputs IA, IB, IC, and ID of the MUX Circuit  250 , respectively. Two outputs OA and OB of the MUX circuit  250  are electrically connected to an input I 1   b  of a comparator  242   b  and an input I 2   a  of a comparator  242   a,  respectively. Depending on four select signals SEL 0 - 3  from the controller circuit, the outputs OA and OB of the MUX circuit  250  receive two of four input signals IA, IB, IC, and ID such that voltage of the output OA is higher than voltage of the output OB. There are six different combinations of the outputs OA and OB from the inputs IA-ID. More specifically, the outputs OA and OB can receive the signals of the inputs IA and IB, the inputs IA and IC, the inputs IA and ID, the inputs IB and IC, the inputs IB and ID, or the inputs IC and ID. 
         [0027]    In one embodiment, the line testing operation of the digital circuit  200  is similar to the operation of the digital circuit  100  of  FIG. 1 . More specifically, the digital circuit  200  is capable of testing a regular metal line  21 OR+ 210 R 2  of a regular cell  210 . For instance, assume that the regular metal line  210 R 1 + 210 R 2  is to be tested. As a result, a bitline BL is pulled high and a wordline WL is pulled low resulting in the regular metal line  210 R 1 + 210 R 2  being selected for testing. More specifically, as a result of the bitline BL being high and the wordline WL being low, similar to the case of  FIG. 1 , a tap node N 1  of the regular metal line  210 R 1 + 210 R 2  is electrically connected to (i) the input I 1   a  of the comparator  242   a  of the comparing circuit  240  and (ii) the input I 2   b  of the comparator  242   b  of the comparing circuit  240  through the pass gate circuit  220 . Also as a result of the bitline BL being high, the comparators  242   a  and  242   b  are enabled in a manner similar to the case of  FIG. 1 . 
         [0028]    Assume further that (i) the tap node N 1  is at middle point of the regular metal line  210 R 1 + 210 R 2  and (ii) the cross-section area of the regular metal line  210 R 1 + 210 R 2  is the same along the length of the metal line  210 R 1 + 210 R 2 . Assume that the regular metal line  210 R 1 + 210 R 2  is nearly broken at a certain point of the resistor  210 R 2  such that the ratio of the resistances of the resistors  210 R 1  and  210 R 2  is 2:8. Assume further that (i) the tap nodes NA, NB, NC, and ND are at locations such that the length ratio of the resistors  230 R 1 ,  120 R 2 ,  130 R 3 ,  230 R 4 , and  230 R 5  is 1:2:4:2:1 and (ii) the cross-section area of the reference metal line  230 R is the same along the length of the reference metal line  230 R. As a result, the ratio of the resistances of the resistors  230 R 1 ,  120 R 2 ,  230 R 3 ,  230 R 4 , and  230 R 5  is also 1:2:4:2:1. Assume further that the Vcc−10V. As a result, the voltages at the tap nodes NA, NB, NC, and ND are 9V, 7V, 3V, and 1V (voltage divider rule), respectively, resulting in the voltages of the inputs IA, IB IC, and ID of the MUX circuit  250  are 9V, 7V, 3V, and 1V, respectively. 
         [0029]    Assume that the four select signals SEL 0 - 3  of the MUX circuit  250  are such that the outputs OA and OB receive the signals from IB and IC, respectively (i.e., the tap nodes NB and NC are selected). As a result, V(I 1   b )=V(NB)−7V and V(I 2   a) V(IC)= 3V. 
         [0030]    As a result of ratio of the resistances of the resistors  210 R 1  and  210 R 2  being 2:8 and Vcc=10V, V(N 1 )−8V (voltage divider rule). Because V(N 1 ) is not between the voltages of the selected tap nodes NB and NC (7V and 3V. respectively), the digital circuit  200  determines that the regular metal line  210 R 1 + 210 R 2  is not in good condition. 
         [0031]    The digital circuit  200  of  FIG. 2  is more sensitive than the digital circuit  100  of  FIG. 1 . More specifically, there are cases in which a regular metal line is nearly broken and is identified as not in good condition by the digital circuit  200  but is still identified as in good condition by the digital circuit  100 . More specifically, in the instance described above, V(N 1 )=8V which is not between the voltages of the selected tap nodes NB and NC resulting in the digital circuit  200  determining that the regular metal line  210 R 1 + 210 R 2  is not in good condition. With reference to  FIG. 1 , in the instance described above, assume that V(N 00 )−8V. As a result, V(N 00 ) is between V(NC 01 ) and V(NC 02 ) (1V and 9V, respectively) resulting in the digital circuit  100  determining that the regular metal line R 00   a +R 00   b  is in good condition. This indicates that the digital circuit  100  is not as sensitive as the digital circuit  200 . 
         [0032]      FIG. 2A  shows one embodiment of the MUX circuit  250  of  FIG. 2 . More specifically, the MUX circuit  250  comprises two multiplexers  252  and  254 . The four inputs IA, IB, IC, and ID are electrically connected to (i) four inputs IA 1 , IB 1 , IC 1 , and ID 1 , respectively, of the multiplexer  252  and (ii) four inputs IA 2 , IB 2 , IC 2 , and ID 2 , respectively, of the multiplexer  254 . The output OA is an output of the multiplexer  252  and the output OB is an output of the multiplexer  254 . The select inputs SEL 0  and SEL 1  are select inputs of the multiplexer  252  and the select inputs SEL 2  and SEL 3  are select inputs of the multiplexer  254 . 
         [0033]    In one embodiment, the operation of the MUX circuit  250  is as follows. Depending on the two select signals SEL 0  and SEL 1 , the output OA of the multiplexer  252  receives one of the four input signals IA 1 , IB 1 , IC 1 , and ID 1  (i.e., one of the four input signals IA, IB, IC, and ID). Depending on the two select signals SEL 2  and SEL 3  from the controller circuit, the output OB of the multiplexer  254  receives one of the four input signals IA 2 , IB 2 , IC 2 , and ID 2  (i.e., one of the four input signals IA, IB, IC, and ID. In one embodiment, the four select signals SEL 0 -SEL 3  are such that V(OA)&gt;V(OB). 
         [0034]      FIG. 3  shows a comparator  300  as one embodiment of the comparators  142 C 0   a  and  142 C 0   b  of the comparing circuit  140 C 0  of  FIG. 1  and the comparators  242   a  and  242   b  of the comparing circuit  240  of  FIG. 2 , in accordance with embodiments of the present invention. 
         [0035]    The operation of the comparator  300  is as follows. When EN signal is low, the comparator  300  is enabled. The output OUT of the comparator  300  is high when the input PLUS is higher than the input MINUS. The output OUT of the comparator  300  is low when the input PLUS is lower than the input MINUS. 
         [0036]    While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.