Abstract:
A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures with solder bumps are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that conductive traces, vias and solder bumps form a unique conductive path for signals, which are accessed individually. Additionally, the structural integrity of the chip stack module is enhanced through the use and position of the solder bumps.

Description:
RELATED APPLICATIONS  
       [0001]    The present application claims priority benefit under 35 USC §119(e) from U.S. Provisional Application No. 60/293,766 filed May 25, 2001, entitled “STACKED MEMORY” and U.S. Provisional Application 60/294,389 filed May 29, 2001, entitled “STACKED MEMORY”, which are herein incorporated by reference. The present application is related to applicant&#39;s co-pending application Ser. No. ______ (Attorney docket No. SIMTECH.221A) entitled “APPARATUS AND METHOD FOR STACKING INTERGRATED CIRCUITS” which is concurrently filed herewith. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The invention relates to the vertical stacking of integrated circuits to increase the density of components on a printed circuit board without increased footprint. More particularly, the present invention relates to apparatus and methods for the vertical stacking of memory integrated circuits on a surface mount printed circuit board.  
           [0004]    2. Description of the Related Art  
           [0005]    Modern electronic devices, such as computers and the like, typically include integrated circuits commonly referred to and will be referred to herein as “chips”. Integrated circuits or chips are microcircuits formed on a semiconductor substrate and packaged in a ceramic, plastic or epoxy package having multiple external terminals or “pins”. The microcircuits are wire-bonded within the package to the external terminals or pins. When the pins of the chip packages are connected to the printed circuit board, the integrated circuits are electrically connected to other integrated circuits and electrical components through or by way of traces on the printed circuit board to form system level electronic circuits.  
           [0006]    With advances in semiconductor device processing has come a continuing increase in device count and density within chips and this has driven a corresponding increase in the count and density of the external conducting pads. Current technology places a limit on how small external contacts can be made and how closely they can be placed adjacent one another while still maintaining circuit integrity. Limits are imposed, both by the limitations of machinery to form ever-smaller conductive elements and by the reduction in production yield as the limits are pushed.  
           [0007]    Additionally, as modern electronic devices are driven to ever increasing functionality and decreasing size, the printed circuit boards within the electronic devices are driven to increased integrated circuit densities. The desire to provide the capability of integrated circuits to be used in relatively small devices limits the extent to which multiple chips can be laterally interconnected while still fitting within the device. Lateral extension and interconnection of chips tends to lead to relatively long interconnects or traces between chips which increases the signal propagation delay and thus, decreases the circuit operating speed. Further, lengthy traces increase both the radio-frequency interference (RFI), and electromagnetic interference (EMI) emitted from the printed circuit board.  
           [0008]    From the foregoing, it can be appreciated that there is an ongoing need for structures and methods for interconnecting chips that increase circuit density without increasing the chip footprint and with minimal increase in interconnection length.  
         SUMMARY OF THE INVENTION  
         [0009]    The aforementioned needs are satisfied by the invention in which one aspect is various structures and methods for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack. The structures and methods include the aspect that the footprint of the stack does not exceed the sum of the individual footprints of the chips in the stack.  
           [0010]    A certain aspect of the invention is a chip stack assembly comprising a substrate having a plurality of contacts, a first chip having a plurality of contacts extending outward therefrom, a second chip having a plurality of contacts extending outward therefrom, a third chip having a plurality of contacts extending outward therefrom, a first support structure positioned adjacent the substrate and electrically connected thereto, the first support structure having a first and a second surface and defining a plurality of mounting pads on the first and second surface, wherein the contacts of the first chip are attached to the mounting pads on the first surface and the contacts of the second chip are attached to the mounting pads on the second surface so that the first and second chips are positioned so as to be stacked adjacent each other, a second support structure having a first and second surface wherein the first surface of the second support structure is positioned adjacent the second surface of the first support structure and wherein the second support structure defines a plurality of mounting pads that receive the plurality of contacts extending outward from the third chip such that the third chip is positioned adjacent the first and second chips, a plurality of conductive protrusion components positioned on the first surface of the second support structure so as to be interposed between the first and second support structure wherein the plurality of conductive protrusion components electrically interconnect the contacts from the third chip to the second support structure.  
           [0011]    The invention also includes the aspects of a chip stack assembly comprising a substrate having a set of contacts, a plurality of chips each having at least one set of contacts extending outward therefrom, a plurality of support structures mounted to each other wherein the at least one set of contacts of the plurality of chips are mounted to the plurality of support structures such that the plurality of support structures maintain the plurality of chips in a stacked configuration, wherein the plurality of support structures define interconnecting paths that interconnect at least some of the contacts of the plurality of chips to the contacts of the substrate, and a plurality of interconnecting protrusion components interposed between the interfaces of the plurality of support structures, wherein the plurality of interconnecting protrusion components form a portion of at least some of the interconnecting paths.  
           [0012]    A further aspect of the invention is a chip stack assembly comprising a first chip having a plurality of contacts extending outward therefrom, a second chip having a plurality of contacts extending outward therefrom, a third chip having a plurality of contacts extending outward therefrom, a first support structure having a first surface and a second surface and defining a plurality of mounting pads on the first and second surface, wherein the contacts of the first chip are attached to the mounting pads on the first surface and the contacts of the second chip are attached to the mounting pads on the second surface so that the first and second chips are positioned so as to be stacked adjacent each other, a second support structure having a first and second surface wherein the first surface of the second support structure is positioned adjacent the second surface of the first support structure and wherein the second support structure defines a plurality of mounting pads that receive the plurality of contacts extending outward from the third chip such that the third chip is positioned adjacent the first and second chips, a mounting structure having a first and a second surface and defining a plurality of mounting pads on the second surface, wherein the second surface of the mounting structure is positioned adjacent to the first surface of the first support structure wherein the contacts of the first chip are attached to the mounting pads of the second surface, wherein the mounting structure is positioned adjacent a substrate and electrically connected thereto.  
           [0013]    The invention also includes the aspects of a chip stack assembly comprising a substrate having a set of contacts, a plurality of chips each having at least one set of contacts extending outward therefrom, a plurality of support structures mounted to each other wherein the at least one set of contacts of the plurality of chips are mounted to the plurality of support structures such that the plurality of support structures maintain the plurality of chips in a stacked configuration, wherein the plurality of support structures define interconnecting paths that interconnect at least some of the contacts of the plurality of chips to the contacts of the substrate, and a plurality of interconnecting protrusion components interposed between the interfaces of the plurality of support structures, wherein the plurality of interconnecting protrusion components are positioned in a pattern so as to maintain the first and second sides of the plurality of support structures and in a generally parallel orientation.  
           [0014]    The invention further includes the aspects of a chip stack for mounting on a substrate having a plurality of contact pads comprising at least a first, a second, and a third chip and at least a first and a second support structure each comprising a first and a second surface and at least one via connection interposed between the first and second surfaces for interconnecting the chips and maintaining the chips in a stacked configuration so that the chips are interconnected with at least one isolated pathway whereby at least one of the contacts of the first chip is electrically connected to a contact pad on the substrate in a manner that isolates the contact of the first chip from the contacts of the second chip and third chip, the isolated pathway comprising a surface mount pad on the first surface of the first support structure electrically coupled to a first via connection on the first surface of the first support structure, wherein the at least one contact of the first chip is electrically coupled to the surface mount pad on the first surface of the first support structure, a first conductive protrusion component electrically coupled to the first via connection on the second surface of the first support structure, a surface pad on the first surface of the second support structure whereby the surface pad on the first surface of a second support structure electrically mates with the first conductive protrusion component on the second surface of the first support structure, the surface pad on the first surface of the second support structure electrically coupled to a second via connection on the first surface of the second support structure, a second conductive protrusion component on the second surface of the second support structure electrically coupled to the second via connection on the second surface of the second support structure whereby the second conductive protrusion component is electrically coupled to the substrate.  
           [0015]    For purposes of summarizing the invention, certain aspects, advantages and novel features of the invention have been described herein. Of course, it is to be understood that not necessarily all such aspects, advantages or features will be embodied in any particular embodiment of the invention.  
           [0016]    These and other objects and advantages of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    A general architecture that implements the various features of the invention will now be described with reference to the drawings. The drawings and the associated descriptions are provided to illustrate embodiments of the invention and not to limit the scope of the invention. Throughout the drawings, reference numbers are re-used to indicate correspondence between referenced elements.  
         [0018]    [0018]FIG. 1A is a perspective view illustrating a memory chip stack module of the present invention of a preformed support structure vertically interconnecting a first chip to a second chip, according to aspects of an embodiment of the invention;  
         [0019]    [0019]FIG. 1B is a detail, perspective view of a portion of the preformed support structure of FIG. 1A illustrating the connection path of an individually accessed signal, according to aspects of an embodiment of the invention;  
         [0020]    [0020]FIG. 1C is a detail, perspective view of a portion of the preformed support structure of FIG. 1A illustrating the connection path of a common signal, according to aspects of an embodiment of the invention;  
         [0021]    [0021]FIG. 2A is a top view the memory chip stack module of FIG. 1A, according to aspects of an embodiment of the invention;  
         [0022]    [0022]FIG. 2B is a side view the memory chip stack module of FIG. 1A, according to aspects of an embodiment of the invention;  
         [0023]    [0023]FIG. 2C is a front view of the memory chip stack module of FIG. 1A, further illustrating the preformed support structure vertically connecting the first chip with the second chip, according to aspects of an embodiment of the invention;  
         [0024]    [0024]FIG. 2D is a footprint of the memory chip stack module of FIG. 1A illustrating the area of the chip stack on a printed circuit board, according to aspects of an embodiment of the invention;  
         [0025]    [0025]FIG. 2E is a detail of the chip stack module footprint of FIG. 2D further illustrating spacing between pads of the chip stack module, according to aspects of an embodiment of the invention;  
         [0026]    [0026]FIG. 3A is a pin location map of the memory chip stack of FIG. 1A, according to aspects of an embodiment of the invention;  
         [0027]    [0027]FIG. 3B is pin symbol table of the memory chip stack of FIG. 1A, according to aspects of an embodiment of the invention;  
         [0028]    [0028]FIG. 3C is a pin function table of the memory chip stack of FIG. 1A, according to aspects of an embodiment of the invention;  
         [0029]    [0029]FIG. 4 is a functional block diagram of the memory chip stack of FIG. 1A, according to aspects of an embodiment of the invention;  
         [0030]    [0030]FIG. 5A is a front view of a chip stack module illustrating widened preformed support structures vertically connecting a first chip, a second chip, a third chip, and a fourth chip, according to aspects of an embodiment of the invention;  
         [0031]    [0031]FIG. 5B is an enlarged detail of the chip stack module of FIG. 5A illustrating the connection path of isolated signals, according to aspects of an embodiment of the invention;  
         [0032]    [0032]FIG. 5C is a detail, perspective view of a portion of the preformed support structures of FIG. 5B, according to aspects of an embodiment of the invention;  
         [0033]    [0033]FIG. 5D is a bottom surface view of a portion of the chip stack module of FIG. 5A illustrating the connection path of isolated signals, according to aspects of an embodiment of the invention;  
         [0034]    [0034]FIG. 5E is a detail of a footprint of the chip stack module of FIG. 5A, according to aspects of an embodiment of the invention;  
         [0035]    [0035]FIG. 6A is a front view of a chip stack tower illustrating a chip stack module mounted onto a ball grid array printed circuit board, according to aspects of an embodiment of the invention; and  
         [0036]    [0036]FIG. 6B is a is a detail, perspective view of a portion of the ball grid array printed circuit board of FIG. 6A and the preformed support structure mounted thereon, according to aspects of an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0037]    In accordance with one embodiment of the present invention, one multi-chip memory module design is described herein. In order to fully specify this preferred design, various embodiment specific details are set forth, such as the number of memory chips in the module, the capacity, the number of data bits, the pin-outs of the memory chips, the module footprint, and the like. It should be understood, however, that these details are provided only to illustrate one embodiment, and are not intended to limit the scope of the present invention.  
         [0038]    [0038]FIG. 1A illustrates a perspective view of a chip stack module  10  comprising two surface mount chips  12 ,  14  stacked in accordance with the present invention. The chip stack module  10  further comprises a support member or support structure  16 . The support structure  16  holds together and conductively interconnects the vertically stacked chips  12 ,  14 . The chip stack module  10  is configured to be surface mounted to a printed circuit board that has surface mount pads thereon. The chip stack module  10  further comprises a width B, a height C, and a spacing D between stacked chips  12 ,  14   
         [0039]    Surface mount chips  12 ,  14  comprise a pin  1  indicator  18 , a plurality of surface contacts  20 , and a width G. In one embodiment, the surface contacts  20  are distributed in two rows of contacts  20 , each row disposed along an opposing side of the chip  12 ,  14  as is generally well known in the art.  
         [0040]    The support structure  16  in this embodiment comprises a frame  22  and a plurality of surface mount pads  24 . Frame members across a front side without surface contacts  20  of chips  12 ,  14  are not shown in FIG. 1A in order to illustrate the stacking of chips  12 ,  14 . In another embodiment, frame  22  comprises two rails positioned parallel to each other and perpendicular to a top surface of the chips  12 ,  14 . The surface mount pads  24  are distributed in two rows on each opposing side of frame  22  with a top row of surface mount pads  24  placed along a top surface of the frame  22  and a bottom row of surface mount pads  24  placed along a bottom surface of the frame  22 , as shown in FIG. 1B. The top row of surface mount pads  24  aligns over and directly opposes the bottom row of surface mount pads  24 . Spacing and alignment of each row of surface mount pads  24  corresponds to the spacing and alignment of the rows of surface contacts  20  of the chips  12 ,  14 .  
         [0041]    The frame  22  may comprise a two-layer printed circuit board made of a rigid, non-conducting material such as glass epoxy, FR4, and the like. The frame  22  further comprises the length A, a width E and a height F.  
         [0042]    In one embodiment, the height F of the frame  22  is approximately equal to the thickness of one chip  12 ,  14  so that the stacked chips  12 ,  14  are nearly touching when the memory chip stack module  10  is assembled. Close spacing D between stacked chips  12 ,  14  advantageously provides the chip stack module  10  with a low profile, which is desirable in densely populated electronic devices. Alternatively, in another embodiment, the height F of the frame  22  may be advantageously adjusted to increase the spacing D between stacked chips  12 ,  14 , as may be desirable in certain applications to facilitate the cooling of the chips.  
         [0043]    When, in one embodiment, chip stack module  10  is assembled, surface contacts  20  of the signals common to both chips  12 ,  14  are conductively interconnected and all memory locations on both chips  12 ,  14  can be utilized. However, for proper operation of the chip stack module  10 , some signals on each chip  12 ,  14  are individually accessed and not interconnected. In an embodiment utilizing functionally identical stacked chips  12 ,  14 , the surface contact  20  of the isolated signal of chip  12  is directly below the surface contact of the corresponding isolated signal of chip  14 . Similarly, the surface contact  20  of the common signal of chip  12  is directly below the surface contact of the corresponding common signal of chip  14 . FIGS. 1B and 1C illustrate a conducting a path for an isolated signal and a common signal, respectively.  
         [0044]    [0044]FIG. 1B illustrates a perspective view of an enlarged portion of the support structure  16  of the present invention. Support structure  16  comprises the frame  22 , the surface mount pads  24 , a plurality conductive traces  26  and  32 , a plurality of vias  28 , and a plurality of solder bumps  30 . Vias  28  comprise via holes or openings filled with conductive material  29  such that vias  28  are electrically conductive from a top surface of the via  28  to a bottom surface of the via  28 .  
         [0045]    [0045]FIG. 1B further illustrates a conducting path through the frame  22  for the isolated signal of chip  14 . Conductive trace  26  on a top surface of frame  22  interconnects the surface mount pad  24  to the top surface of via  28 . Conductive trace  32  on a bottom surface of frame  22  interconnects the bottom surface of the via  28  to the solder bump  30 . When the chip stack module  10  is assembled, the individually accessed signal of chip  14  conductively connects through surface contact  20  to solder bump  30 . Additionally, when the chip stack module  10  is mounted to the printed circuit board, the solder bump  30  conductively connects to the printed circuit board. Thus, the isolated signal of chip  14  conductively connects to the printed circuit board without interconnecting to any other signal on chips  12 ,  14 . The surface contact  20  of the corresponding isolated signal of chip  12  conductively connects to the surface mount pad  24  on the bottom surface of the frame  22  directly below that of the isolated signal of chip  14 . When the chip stack module  10  is mounted to the printed circuit board, the surface contact  20  of the corresponding isolated signal of chip  12  conductively connects to the printed circuit board. The short conductive paths of the isolated signals of chips  12 ,  14  minimize propagation delays and timing problems.  
         [0046]    [0046]FIG. 1C illustrates a perspective view of an enlarged portion of the support structure  16  of the present invention. Support structure  16  comprises the frame  22 , the surface mount pads  24  comprising a first surface mount pad  25  and a second surface mount pad  27 , the plurality conductive traces  26 , a plurality of conductive traces  34 , and the plurality of vias  28 . Vias  28  comprise via holes or openings filled with conductive material  29  such that vias  28  are electrically conductive from the top surface of the via  28  to the bottom surface of the via  28 .  
         [0047]    [0047]FIG. 1C further illustrates a conducting path through the frame  22  for the common signal of chips  12 ,  14 . Conductive trace  26  on the top surface of frame  22  interconnects the first surface mount pad  25  to the top surface of the via  28 . Conductive trace  34  on the bottom surface of frame  22  interconnects the bottom surface of the via  28  to the second surface mount pad  27  directly below the first surface mount pad  25  on the frame  22 . Surface mount pads  25 ,  27  are conductively connected. When the chip stack module  10  is assembled, the common signal of chip  14  conductively connects through surface contact  20  to surface mount pad  25 , through the via  28 , to surface mount pad  27 . The corresponding common signal of chip  12  conductively connects through the corresponding surface contact  20  to surface mount pad  27 . When the chip stack module  10  is mounted on the printed circuit board, the surface contact  20  of the corresponding common signal of chip  12  is conductively connected to the printed circuit board. Thus, the common signals of chips  12 ,  14  are conductively connected to each other and the printed circuit board. The short conductive paths of the common signals of chips  12 ,  14  minimize propagation delays and timing problems.  
         [0048]    In one embodiment of frame  22 , surface mount pads  24  and conductive traces  26  are formed on the top surface, and surface mount pads  24  and conductive traces  32  and  34  are formed on the bottom surface using a film etching process. Via holes or openings are then drilled through the frame  22  with the via holes or openings positioned substantially perpendicular to the conductive traces  26 ,  32 ,  34 . A plating process is then used to form conductive material  29  into via cylinders within the vias  28 , to interconnect the via cylinders  29  to the appropriate traces  26 ,  32 ,  34 , and to interconnect the surface mount pads  24  to the appropriate traces  26 ,  34 . To provide good electrical conductivity, the traces  26 ,  32 ,  34  and the surface mount pads  24  are plated with approximately 1.4 mil thick conductive material, such as copper or the like, and the vias  28  are plated with approximately 1 mil thick conductive material, such as copper or the like.  
         [0049]    In one embodiment of frame  22 , solder bumps  30  are formed on the bottom surface of the frame  22 . The solder bumps  30  may comprise substantially hemispherical bumps of solder. In other embodiments the solder bumps  30  may comprise solder, a conductive adhesive material such as conductive epoxy, and the like, and may be shaped round, approximately spherical, approximately hemispherical, and the like. The solder bumps  30  are formed so as to substantially approximate the thickness of the surface contact  20  after the chip stack module  10  is mounted to the printed circuit board. This allows the chip stack module  10  to be approximately level when mounted to the printed circuit board. Additionally, the solder bumps  30  provide conductive material to aid in mechanically connecting the chip stack module  10  to the substrate or printed circuit board.  
         [0050]    [0050]FIG. 1A illustrates the positioning relationship between the chips  12 ,  14  and the support structure  16 . Referring to FIG. 1A, the support structure  16  is positioned over the surface contacts  20  along a first edge and a second edge of chip  12 . The surface mount pads  24  along a bottom surface of the support structure  16  are aligned with the surface contacts  20  along the first edge and the second edge of chip  12 . Chip  14  is positioned over the support structure  16 , such that the surface contacts  20  along a first edge and a second edge of chip  14  align with the surface mount pads  24  along a top surface of the support structure  16 . Additionally, chip  14  is positioned over chip  12  such that the pin  1  indicator  18  on chip  14  is aligned and directly over the pin  1  indicator  18  on chip  12 . The assembled chip stack module  10  is processed so as to induce conductive material, such as a high temperature solder, to connect to the surface contacts  20  and surface mount pads  24 . High temperature solder, such as SN63-PB37 and SN96-AG4, both by AIM Products, and the like, may be used so that the chip stack module  10  can be subsequently mounted to the substrate or printed circuit board using a solder with a lower melting point without melting the conductive material connecting the chips  12 ,  14  and the support structure  16  together. Other conductive materials that may be used are silver, copper, and the like.  
         [0051]    [0051]FIGS. 2A, 2B, and  2 C show a top view, a side view, and a front view, respectively, of the chip stack module  10  shown in FIG. 1A. As illustrated in FIG. 2A, the chip stack module  10  comprises a length A, a distance H between an end of the frame  22  and a longitudinal centerline of a first surface contact  20  of the second chip  14 , a distance I between the longitudinal centerlines of any two adjacent surface contacts  20 , and a surface contact width J. In the side view of chip stack module  10 , FIG. 2B illustrates the height C.  
         [0052]    In one embodiment, the length A of the chip stack module  10  is such that the frame  22  accommodates the surface mount pads  24  corresponding to the surface contacts  20  on each side of the chips  12 ,  14 . In another embodiment, the frame length A and/or the frame width E may be adjusted to accommodate other sizes and packages of integrated circuits. As illustrated in FIGS. 1A and 2A, the chip stack module  10  occupies only slightly more area on the substrate or printed circuit board as would a single one of the chips  12 ,  14 .  
         [0053]    [0053]FIG. 2C illustrates the chip stack module  10  mounted on a substrate or printed circuit board  90 . It can be seen that the width B of the chip stack module  10  is much less than the width that two chips  12 ,  14  would require if placed side by side on the substrate or printed circuit board. Of course, in other embodiments, the width B of the chip stack module may change to accommodate chip stacks of greater than two chips and chips with different packages and pin configurations than the chips  12 ,  14  of the chip stack module  10  specified herein.  
         [0054]    [0054]FIG. 2C further illustrates the structure of the chip stack module  10 . Chip  14  is stacked on top of chip  12  and support structure  16  is interposed between the surface contacts  20  of the stacked chips  12 ,  14  such that the surface mount pads  24  align with the surface contacts  20 . FIG. 2C also illustrates the solder bumps  30  and surface contacts  20  on the bottom surface of the support structure  16 . The solder bumps  30  are offset from the surface contacts  20  and are used to conduct isolated signals from chip  14  to the printed circuit board  90 . The surface contacts  20  have a thickness which is interposed between the surface mount pad  24  on the bottom surface of the support structure  16  and the printed circuit board  90 . The solder bumps  30  also have a thickness or radius, which is also interposed between the bottom surface of the support structure  16  and the printed circuit board  90 . The solder bumps  30  are formed so as to substantially approximate the thickness of the surface contacts  20 .  
         [0055]    [0055]FIG. 2D illustrates a footprint  40  of the chip stack module  10 . The footprint  40  comprises a plurality of surface mount pads  36 ,  38  on the substrate or printed circuit board  90  so as to be able to mechanically and conductively connect the chip stack module  10  to the printed circuit board  90 . Surface mount pads  36 ,  38  corresponds to the surface mount pads  24  and solder bumps  30  on the bottom surface of the stacked chip module  10 , respectively. The footprint  40  of the chip stack module  10  further comprises a distance K between an inside edge of the surface mount pad  36  and the inside edge of the opposing surface mount pad  36 , a distance L between an outside edge of the surface mount pad  36  and the outside edge of the opposing surface mount pad  36 , and a distance M between a centerline of the solder bump footprint  38  in a first row of solder bump footprints  38  and the centerline of the solder bump footprint  38  in a second row of solder bump footprints  38 . The footprint  40  of the chip stack module  10  further comprises a distance N between a longitudinal centerline of the surface mount pad  36  to the longitudinal centerline of the adjacent surface mount pad  36 .  
         [0056]    In one implementation, when the chip stack module  10  is mounted on the printed circuit board  90 , surface contact  20  of chip  12  is positioned on surface mount pad  36  of footprint  40 . Alternately, it may be appreciated that a separate solder bump  30  conductively connected to the surface contact  20  of chip  12  may be positioned on solder bump footprint  38 .  
         [0057]    As can be seen from FIGS. 2A, 2C, and  2 D, the footprint  40  of the chip stack module  10  requires much less area of the printed circuit board  90  than the area that would be required by both chips  12 ,  14  mounted individually and laterally on the printed circuit board  90 . The chip stack module  10  allows the chip density to increase without increasing the size of the printed circuit board  90 .  
         [0058]    [0058]FIG. 2E illustrates an enlarged detail of the footprint  40  of FIG. 2D. Surface mount pads  36  comprise a length O and a width P. The solder bump footprint  38  comprises a diameter Q. The footprint  40  further comprises a distance R between the outside edge of the surface mount pad  36  and the centerline of the solder bump footprint  38 , and a distance S between the longitudinal centerline of the surface mount pad  36  and the centerline of the solder bump footprint  38 . The distance R between the outside edge of the surface mount pad  36  and the centerline of the footprint  38  corresponds to the aforementioned offset between the row of surface mount pads  24  and the row solder bumps  30  on the frame  22 .  
         [0059]    In one embodiment, chip stack module  10  comprises an 81-terminal 4M bit×32 bit memory chip stack module comprising two vertically stacked memory chips  12 ,  14 . The memory chips  12 ,  14  are conventional 66-pin surface mount TSOP-II (thin small outline package) DDR SDRAM (double data rate synchronous dynamic random access memory) integrated circuits, available from Micron, Samsung, Elpida, and the like. Each memory chip  12 ,  14  has a capacity of 4M bits×16 bits×4 banks of memory and comprises a plurality of surface contacts  20  distributed in two rows of 33 pins in each row, along opposing sides of the chips as is generally well known in the art. In this embodiment, the length A and height F of the frame  22 , the number of surface mount pads  24 , the spacing of the surface mount pads  24  along the frame  22 , and the like, is such as to accommodate the standard 66-pin, 400 mil TSOP-II packages of the chips  12 ,  14 . Spacing and alignment of each row of surface mount pads  24  on the frame  22  corresponds to each row of  33  surface contacts  20  of the chips  12 ,  14 .  
         [0060]    Table A shows approximate dimensions A through S as illustrated in FIGS. 1A, 2A,  2 B,  2 C,  2 D, and  2 E, for one embodiment wherein chips  12 ,  14  are packaged in TSOP-II packages. All dimensions are approximate and are in inches. Dimensional tolerances are +/−0.004 inches.  
                                   TABLE A                                       A   0.890   K   0.379           B   0.568   L   0.4910           C   0.090   M   0.5310           D   0.005   N   0.026           E   0.064   O   0.056           F   0.043   P   0.016           G   0.440   Q   0.020           H   0.030   R   0.020           I   0.026   S   0.013           J   0.012                      
 
         [0061]    Of course, in other embodiments, the above dimensions may change to accommodate chip stack modules of greater than two chips and chips with different packages and pin configurations than the chips  12 ,  14  of the chip stack module  10  specified herein.  
         [0062]    [0062]FIGS. 3A, 3B, and  3 C illustrate a pin location diagram, a pin configuration table, and a pin function table, respectively, of the memory chip stack module  10 . As described earlier, the 81-terminal memory chip stack module  10  is one embodiment of the present invention and is a 4M×32 bits×4 banks of DDR SDRAM consisting of two 2.5V CMOS 4M×16 bits×4 banks DDR SDRAMs in 66-pin 400-mil TSOP-II packages. In one embodiment, the memory chips  12 ,  14  are interconnected such that both 4M bit×16 bit memory chips  12 ,  14  are selected simultaneously with each memory chip  12 ,  14  supplying or storing 16 bits of data. Also described earlier, some signals on each memory chip  12 ,  14  are individually accessed and not interconnected in order for memory chip stack module  10  to operate properly. From the pin location diagram shown in FIG. 3A, the signals on pins  67 - 81  connect from chip  14  through solder bumps  30  to the substrate or printed circuit board and are electrically isolated from the signals on chip  12 , aligned and located directly beneath. Referring to FIGS. 3B and 3C, the signals on memory chip stack module  10  pins  67 - 81  comprise data in/out signals from the upper 16 bits of the 32-bit word and a data mask signal.  
         [0063]    [0063]FIG. 4 is a functional block diagram of the memory chip stack module  10  and illustrates the interconnection of memory chips  12  and  14  within the memory chip stack module  10 . Pin symbols are shown to the left of FIG. 4. Referring to FIGS. 3C and 4, common signals such as address pins (A 0 -A 12 , BA 0 , BA 1 ), control pins (/RAS, /CAS, /WE, /CS, CKE), clock (CK, /CK), and voltage reference (VREF) of chips  12 ,  14  are connected together while individual signals such as data pins (DQ 0 -DQ 31 ) and control pins (LDM 0 - 1 , UDM 0 - 1 , LDQS 0 - 1 , UDQS 0 - 1 ) are not interconnected.  
         [0064]    The aforementioned description is one embodiment of the chip stack module of the present invention. It is possible to stack chips with different packaging than described above. Modifications in the frame dimensions, number of surface mount contacts, number of vias, number of solder bumps, and number of interconnecting traces of the support structures, and the like, can be made to accommodate stacking chips packaged in industry standard surface mount packages such as quadruple flat packs, and the like, custom surface mount packages, and the like.  
         [0065]    In another embodiment, the stacking method and apparatus described herein are used for stacking chips, such as SRAM and Flash RAM memory chips, and the like, and non-memory chips, such as buffer chips, logic driver chips, and the like.  
         [0066]    Another embodiment of the present invention comprises stacking chips in stacks of greater than two chips. The vertically stacked chips are held together and conductively connected by support structures. The support structures and chips are layered such that a first support structure is positioned over a first chip. Surface mount pads on a bottom surface of the first support structure are over and align with the surface contacts of the first chip. A second chip is positioned over the first support structure such that the surface contacts of the second chip are over and align with surface mount contacts on a top surface of the first support structure. A second support structure is positioned over the second chip. The surface mount pads on the bottom surface of the second support structure are over and align with the surface contacts of the second chip. A third chip is positioned over the second support structure such that the surface contacts of the third chip are aligned and over the surface mount pads on the top surface of the second support structure. It will be appreciated that in additional embodiments, additional layers of support structures and chips could be formed to extend the height of and the number of chips in the chip stack module  10  in the manner previously described.  
         [0067]    [0067]FIG. 5A illustrates the structure of a chip stack module  50  comprising greater than two vertically stacked chips, according to one embodiment of the present invention. FIG. 5A shows a front view of the chip stack module  50  comprising vertically stacked chips  51 ,  52 ,  53 ,  54  and support structures  55 ,  56 ,  57 . Stacked chips  51 ,  52 ,  53 ,  54  comprise surface contacts  20  distributed along a first and a second edge of each chip  51 ,  52 ,  53 ,  54  as is well known in the art. The support structures  55 ,  56 ,  57  in this embodiment comprises the frame  22 . Frame members across sides of chips  51 ,  52 ,  53 ,  54  without surface contacts  20  are not shown in FIG. 5A in order to illustrate the stacking of chips  51 ,  52 ,  53 ,  54 . Support structures  55 ,  56 ,  57  comprise a row of surface mount pads  24  disposed linearly along a top surface and a row of surface mount pads  24  disposed linearly along a bottom surface of each support structure  55 ,  56 ,  57 . In another embodiment, support structures  55 ,  56 ,  57  can be frames, pairs of rails, or the like. Support structure  55  is interposed between stacked chips  51 ,  52 ; support structure  56  is interposed between stacked chips  52 ,  53 ; and support structure  57  is interposed between stacked chips  53 ,  54 . The support structures  55 ,  56 ,  57  are interposed between stacked chips  51 ,  52 ,  53 ,  54  such that the surface mount pads  24  on the bottom surfaces of support structures  55 ,  56 ,  57  are over and align with the surface contacts  20  of chips  51 ,  52 ,  53 , respectively. In a similar manner, the surface mount pads  24  of the top surfaces of support structures  55 ,  56 ,  57  are under and align with the surface contacts  20  of chips  52 ,  53 ,  54 , respectively. The assembled chip stack module  50  is processed so as to induce conductive material, such as the aforementioned high temperature solder, to connect to the surface contacts  20  and surface mount pads  24  so that the chip stack module  50  can be subsequently mounted to the substrate or printed circuit board using a solder with a lower melting point without melting the conductive material connecting the chips  51 ,  52 ,  53 ,  54  and the support structures  55 ,  56 ,  57  together. Other conductive materials that may be used are silver, copper, and the like.  
         [0068]    A further embodiment of the present invention comprises a widened frame to accommodate additional vias and solder bumps to conductively isolate signals from greater than two stacked chips. In one aforementioned embodiment, vias  28 , filled with conductive material  29 , disposed vertically through the support structure  22  and solder bumps  30  on the bottom surface of the support structure  22  conduct signals from the upper chip  14  of the two chip stack to the printed circuit board without conductively connecting the signal to any other signals from the upper chip  14  or lower chip  12  in the two chip stack module  10 . In an embodiment comprising greater than two stacked chips, signals from the additional chips are conducted by additional vias  28  and solder bumps  30  through the stacked support structures  16  to the printed circuit board  90  without conductively connecting the signal to any other signals in the chip stack module. The additional solder bumps  30  are offset from the surface mount pads  24  and each other on the support structures  16 . The width E of the support structure  16  may be increased to accommodate as many solder bumps  30  and vias  28  as are required to conduct signals from the chip stack module to the substrate  90  without electrically connecting to any other signals.  
         [0069]    [0069]FIG. 5B shows an enlarged detail of the chip stack module  50  of FIG. 5A illustrating the connection path of isolated signals, according to aspects of an embodiment of the invention. Chip stack module  50  is shown mounted to printed circuit board  90  comprising surface mount pads  36  and solder bump footprints  38 . Support structure  57  further comprises a first solder bump  60 , a second solder bump  61 , and a third solder bump  62  of support structure  57 , conductive traces  26 ,  32 , and via  67 . Similarly, support structure  56  further comprises the first solder bump  60 , the second solder bump  61 , and the third solder bump  62  of support structure  56 , conductive traces  26 ,  32 , and vias  68 ,  70 . Support structure  56  further comprises a solder bump surface mount pad  81 . Likewise, support structure  55  further comprises the first solder bump  60 , the second solder bump  61 , and the third solder bump  62  of support structure  55 , conductive traces  26 ,  32 , and vias  69 ,  71 ,  72 . Support structure  55  further comprises a solder bump surface mount pad  82 ,  83 . Chips  51 ,  52 ,  53 ,  54  each further comprise a first isolated signal on a first isolated surface contact  66 ,  65 ,  64 ,  63 , respectively. Vias  67 - 72  comprise a via opening filled with conductive material  29  such that the vias  67 - 72  are electrically conductive from a top surface of vias  67 - 72  to a bottom surface of vias  67 - 72 , respectively.  
         [0070]    [0070]FIG. 5B shows a side view of chip stack module  50 . The traces  26  located on top surfaces of the support structures  55 ,  56 ,  57  and the traces  32  located on bottom surfaces of the support structures  55 ,  56 ,  57  are not shown. The traces  26 ,  32  and the solder bump surface contact  81  are further discussed with reference to FIG. 5C  
         [0071]    Referring to FIG. 5B, the isolated surface contact  63  of chip  54  conductively connects to the surface mount pad  24  on the top surface of support structure  57 . Conductive trace  26  conductively connects the surface mount pad  24  on the top surface of support structure  57  to the top surface of via  67  and conductive trace  32  conductively connects the bottom surface of via  67  to the first solder bump  60  of support structure  57 . The first solder bump  60  of support structure  57  conductively connects to the solder bump surface mount pad  81  on the top surface of support structure  56 . Conductive trace  26  conductively connects the solder bump surface mount pad  81  on the top surface of support structure  56  to the top surface of via  68 . Conductive trace  32  conductively connects the bottom surface of via  68  to the first solder bump  60  of support structure  56 . The first solder bump  60  of support structure  56  conductively connects to a solder bump surface mount pad  82  on the top surface of support structure  55 . Conductive trace  26  conductively connects the solder bump surface mount pad  82  on the top surface of support structure  55  to the top surface of via  69 . Conductive trace  32  conductively connects the bottom surface of via  69  to the first solder bump  60  of support structure  55 . The first solder bump  60  of support structure  55  conductively connects to the corresponding solder bump footprint  38  of the printed circuit board  90 . Thus, the first isolated signal of chip  54  conductively connects to the printed circuit board  90  through traces  26 ,  32 , vias  67 ,  68 ,  69 , first solder bumps  60  of support structures  55 ,  56 ,  57  and corresponding solder bump surface mount pads  81 ,  82  of support structures  56 ,  55 , respectively, without interconnecting to any other signal on chips  51 ,  52 ,  53 ,  54 .  
         [0072]    In a similar manner, the first isolated signal of chip  53  on the first isolated surface contact  64  conductively connects to the solder bump footprint  38  on printed circuit board  90  through traces  26 ,  32 , vias  70 ,  71 , second solder bumps of support structures  55 ,  56 , and the corresponding solder bump surface mount pad  83  of support structure  55 .  
         [0073]    Likewise, the first isolated signal of chip  52  on the first isolated surface contact  65  conductively connects to the solder bump footprint  38  on printed circuit board  90  through traces  26 ,  32 , via  72 , and the third solder bump of support structure  55 . The first isolated signal of chip  51  on the first isolated surface contact  66  conductively connects directly to the surface mount pad  36  on the printed circuit board  90 .  
         [0074]    In one embodiment, the width E of the frame  22  increases to accommodate the additional solder bumps  60 ,  61 , solder bump surface mount contacts  81 - 83 , and vias  67 - 71 . In another embodiment, the additional solder bumps  60 ,  61 , solder bump surface mount contacts  81 - 83 , and vias  67 - 71  may be located along the frame  22  in such a manner as not to increase width E of the frame  22 .  
         [0075]    [0075]FIG. 5C illustrates a detail, perspective view of a portion of the preformed support structures  56 ,  57  of FIG. 5B, according to aspects of an embodiment of the invention. Support structure  56  comprises surface mount pads  24 , traces  26 , vias  68 ,  70 , solder bump surface mount pad  81 , traces  32 , and the first solder bump  60 , the second solder bump  61 , and the third solder bump  62  of support structure  56 . As shown in FIG. 5B, the isolated surface contact  63  of chip  54  conductively connects from the surface mount pad  24  on the top surface of support structure  57  through conductive trace  26  to the top surface of via  67 . Referring to FIG. 5C, conductive trace  32  connects the first solder bump  60  of support structure  57  to the bottom surface of via  67 . The first solder bump  60  of support structure  57  conductively connects with the solder bump surface mount pad  81  on the top surface of support structure  56 . Conductive trace  26  on the top surface of support structure  56  conductively connects solder bump surface mount pad  81  to a top surface of via  68 . Conductive trace  32  on the bottom surface of support structure  56  conductively connects a bottom surface of via  68  to the first solder bump  60  on the support structure  56 .  
         [0076]    To complete the conductive path to the printed circuit board  90 , refer to FIG. 2B. The first solder bump  60  on the support structure  56  conductively connects through the solder bump surface mount pad  82  on the top surface of support structure  55 , through trace  26  on the top surface of support structure  55 , via  69 , trace  32  on the bottom surface of support structure  55  to the first solder bump  60  of support structure  55 . The first solder bump  60  of support structure  55  conductively connects to the printed circuit board  90  through solder bump footprint  38 .  
         [0077]    Solder bumps  60 ,  61 ,  62  and solder bump surface mount pads  80  are positioned on support structures  55 ,  56 ,  57  such that the solder bumps  60 ,  61 ,  62  on the bottom surface of support structures  55 ,  56 ,  57  are over and align with solder bump surface mount pads  80  on top surfaces of the support structure  55 ,  56 , or  57  which is located below and adjacent. More specifically, in one embodiment, the first solder bump  60  of support structure  57  is over and aligns with solder bump footprint  81 . The first solder bump  60  of support structure  56  is over and aligns with solder bump footprint  82  and the second solder bump  61  of support structure  57  is over and aligns with solder bump footprint  83 .  
         [0078]    [0078]FIG. 5C further illustrates the conduction path of the first isolated signal of chip  53  on the first isolated surface contact  64  through the support structure  56 . The first isolated signal of chip  53  on the first isolated surface contact  64  conductively connects to the surface mount pad  24  on the top surface of support structure  56 , shown in FIG. 5B. Referring to FIG. 5C, conductive trace  26  on the top surface of support structure  56  conductively connects the surface mount pad  24  to the top surface of via  70 . Conductive trace  32  on the bottom surface of support structure  56  conductively connects the bottom surface of via  70  to the second solder bump  61  of support structure  56 .  
         [0079]    As illustrated in FIGS. 5B and 5C, the solder bump surface mount pads  81 - 83  and the solder bumps  60 - 62  are offset from vias  67 - 72 . The solder bump surface mount pads  81 - 83  conductively connect to the top surfaces of vias  67 - 72  through traces  26  and the solder bumps  60 - 62  conductively connect to the bottom surfaces of vias  67 - 72  through traces  32 . However, in another embodiment, it is to be appreciated that a conductive pad may be located on the via to avoid conductive traces  26 ,  32  in some circumstances.  
         [0080]    [0080]FIG. 5D shows a bottom surface view of a portion of the chip stack module  50  of FIG. 5A further illustrating the connection path of isolated signals, according to aspects of an embodiment of the invention. The bottom of chip stack module  50  comprises surface contacts  20  from chip  51  and support structure  55 . Support structure  55  comprises the frame  22 , surface mount pads  24 , vias  28 , conductive traces  32 ,  34 , the first solder bump  60 , the second solder bump  61 , and the third solder bump  62 . Referring to FIG. 5D, the surface contacts  20  are conductively connected to the surface mount pads  24 . Conductive traces  28  conductively connect vias  28  to the surface mount pads  24  for interconnected signals common to chips  51 ,  52 ,  53 ,  54 . Conductive traces  32  conductively connect vias  28  to the solder bumps  60 ,  61 ,  62  for the individually accessed signal of chips  52 ,  53 ,  54 .  
         [0081]    [0081]FIG. 5E is shows a detail of a footprint of the chip stack module  50  of FIG. 5A, according to aspects of an embodiment of the invention. The footprint comprises surface mount pads  36  corresponding to the surface mount pads  24  and surface mount pads  38  corresponding to the solder bumps  60 ,  61 ,  62  of the chip stack module  50 . FIG. 5E illustrates the aforementioned offset between the surface mount pads  36  and a first row of surface mount pads  38 . FIG. 5E further illustrates the spacing between rows of surface mount pads  38  according to aspects of an embodiment of the invention.  
         [0082]    [0082]FIG. 6A illustrates a front view of a chip stack tower  100  comprising the chip stack module  50  mounted onto a substrate  110 , according to aspects of an embodiment of the invention. The chip interconnections, signal paths, and footprint of chip stack module  50  are described in detail in FIGS.  5 A- 5 E. The substrate  110  can be utilized to connect the chip stack module  50  to the printed circuit board  90 . The substrate  110  is an intermediate printed circuit board and has a footprint. The intermediate printed circuit board  110  may mount to the printed circuit board  90  using a ball grid array on to a plurality of surface contacts  112 , as illustrated in FIG. 6A. In another embodiment, the intermediate circuit board  110  may mount to the printed circuit board  90  using surface mount pads, surface mount contacts, pins, and the like. The chip stack tower  100  allows the area occupied by the frame  22  in the chip stack module  50  to be utilized for running traces or the like, on the printed circuit board  90 . The height of the chip stack tower  100 , however, is greater than the height of the chip stack module  50  by the thickness of the intermediate printed circuit board  110 .  
         [0083]    [0083]FIG. 6B is a is a detail, perspective view of a portion of the ball grid array printed circuit board  110  of FIG. 6A and the preformed support structure  55  mounted thereon, according to aspects of an embodiment of the invention. The printed circuit board  110  comprises a plurality of surface mount pads  114 , a plurality of traces  116 , a plurality of vias  118 , a plurality of solder mount pads  120 , and a plurality of solder balls  122 . The surface mount pads  114  receive the chip contact  20  and the solder mount pads  120  receive the solder bumps  60 ,  61 ,  62  of the support structure  55 . The traces  116  and vias  118  are utilized in routing the signals through the printed circuit board  110  to a bottom surface of the printed circuit board  110 . The solder balls  122  on the bottom surface of the printed circuit board  110  mount and conductively connect the chip stack tower  100  to the printed circuit board  90 . The signal routing through the printed circuit board  110  and utilization of the surface mount pads  114 , traces  116 , vias  118 , and surface mount pads  120  is very similar to the signal routing through the chip stack module  50 , which is described in detail in connection with FIG. 5C and would be obvious to one skilled in the art.  
         [0084]    While certain embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.