Abstract:
A method and apparatus are provided for implementing connections with circuits, such as very large scale integrated (VLSI) semiconductor integrated circuits. A physical connection assignment arrangement includes a plurality of connections, each having predefined, dual functions. A control signal identifies an orientation of the physical connection assignment arrangement. A selector logic circuit contained within the circuit is coupled to the plurality of predefined, dual function connections. The selector logic circuit receives the control signal and responsive to the control signal, selects one of the predefined dual functions for each of the plurality of connections.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to the data processing field, and more particularly, relates to a method and apparatus for implementing connections with circuits, such as very large scale integrated (VLSI) semiconductor integrated circuits. 
     DESCRIPTION OF THE RELATED ART 
     FIG. 1 illustrates a prior art arrangement of processor cards. Today the profile of processor cards is increasing due to the increased heat sink size required to cool the faster processors. FIGS. 2 and 3 illustrate processor cards that are inserted back-to-back. Note the wiring problem created in FIG. 2 when the cards are inserted back-to-back without any special card design. In order to keep backplane busses as short as possible, two unique processor cards, a right and left-handed version of the processor card are required as illustrated in FIG.  3 . 
     U.S. Pat. No. 5,701,234 discloses a surface mount component which can be mounted on the surface of a printed circuit board (PCB) in a selected one of a plurality of different positions. The surface mount component includes a puck having first and second wiring patterns and a plurality of electrical connectors. A first set of connectors is connected to the first wiring pattern and a second set of connectors is connected to a second wiring pattern. During the manufacturing process, a worker mounts the puck to a printed circuit board in a selected one of a plurality of different positions, with selected ones of the first and second sets of connectors being connected to respective ones of a plurality of bonding pads on the printed circuit board. 
     A need exists for an improved mechanism for implementing connections with circuits, such as very large scale integrated (VLSI) semiconductor integrated circuits. 
     SUMMARY OF THE INVENTION 
     A principal object of the present invention is to provide an improved method and apparatus for implementing connections with circuits, such as very large scale integrated (VLSI) semiconductor integrated circuits. Other important objects of the present invention are to provide such method and apparatus for implementing connections with circuits substantially without negative effects and that overcome some disadvantages of prior art arrangements. 
     In brief, a method and apparatus are provided for implementing connections with circuits, such as very large scale integrated (VLSI) semiconductor integrated circuits. A physical connection assignment arrangement includes a plurality of connections, each having predefined, dual functions. A control signal identifies an orientation of the physical connection assignment arrangement. A selector logic circuit contained within the circuit is coupled to the plurality of predefined, dual function connections. The selector logic circuit receives the control signal and responsive to the control signal, selects one of the predefined dual functions for each of the plurality of connections. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein: 
     FIGS. 1,  2  and  3  illustrate prior art processor card arrangements; 
     FIG. 4 is a diagram illustrating physical connection assignments in accordance with the preferred embodiment; 
     FIG. 5 is a diagram illustrating exemplary selector logic in accordance with the preferred embodiment; and 
     FIGS. 6,  7 ,  8  are diagrams illustrating exemplary applications for the physical connection assignments of FIG.  4  and the selector logic of FIG. 5 of the preferred embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Having reference now to the drawings, in FIG. 4 there is shown a physical connection assignment arrangement generally designated by the reference character  400  and arranged in accordance with the present invention. In accordance with features of the invention, the physical connection assignment arrangement  400  of multiple physical connections or pins  402  defines each of the signal pins D 1 , D 2 , D 3 , D 61 , D 62 , D 63 , for example, on the backplane connector, for one of two possible uses, depending on whether the card is plugged in to a right or left-handed slot. The selection for the function of each signal connector pin D 1 , D 2 , D 3 , D 61 , D 62 , D 63  is made with selection logic circuitry  500  illustrated and described with respect to FIG.  5 . The combination of the physical connection assignment arrangement  400  and selection logic circuitry  500  of the invention moves wiring congestion off of the backplane as illustrated in FIG.  2  and removes the need for a pair unique processor cards conventionally used to handle the reversed connector situation as illustrated in FIG.  3 . 
     Physical connection assignment arrangement  400  of the invention assigns the connector pins  402  in a mirror image layout as illustrated in FIG.  4 . The signal pins  402  are defined for example, such that the signal pins  402  D 0  of a first connector is connected to card pin D 0  in the mating connector  400  when placed upright and is connected to signal pin D 63  with the mating connector  400  rotated by 180 degrees or flipped vertically. Flipping the connector  400  by 180 degrees results in the power (P) and ground (G) pins  402  connecting correctly, while each of the signal pins  402  on the card would connect to one of two predefined signals. For example as illustrated in FIG. 4, one of D 0  or D 63 , D 1  or D 62 , D 2  or D 61  is connected to a respective connection D 0 , D 1 , or D 2  depending on a selected first or second orientation (such as, left or right) of the mating connector. In general, each signal pin  402  is assigned two functions, with one function selected by the left or right orientation of the connection. A pair of shared, dual function signal pins  402 , such as D 0 /D 63  and D 63 /D 0  are defined for all of the signal pins  402 , used with selection logic  500  as illustrated in FIG.  5 . 
     FIG. 5 shows an exemplary implementation for the selector logic generally designated by  500  and arranged in accordance with the preferred embodiment. FIG. 5 shows a pair of shared dual function signal pins  402  D 0 /D 63  and D 63 /D 0 . The dual function signal pins  402 , such as processor card connector pins, are routed directly into a chip containing selector logic  500 , such as a processor chip. A right/left control signal RIGHT/LEFT is used to select the correct function for each dual function signal pin  402 . Selector logic  500  includes a receiver  502  and a driver  504  coupled to each of the dual function signal pins  402  D 0 /D 63 , D 63 /D 0 . Each receiver  502  and each driver  504  is connected to a respective latch  510 ,  512 ,  514 ,  516  in the data flow path. Selector logic  500  includes a respective multiplexer  518 ,  520 ,  522 ,  524  connected with each latch  510 ,  512 ,  514 ,  516  in the data flow path, as shown. Internal to a particular chip containing selector logic  500 , the signals are routed to the correct function based on the control signal RIGHT/LEFT applied to each of the multiplexers  518 ,  520 ,  522 ,  524  that indicates the connection&#39;s orientation, for example, whether the card is in a right or left-hand slot. First and second inputs to multiplexer  518  are the respective latched outputs of latches  510  and  514  coupled to receivers  502 . First and second inputs to multiplexer  520  are the respective latched outputs of latches  514  and  510  coupled to receivers  502 . First and second inputs to multiplexers  520  and  522  coupled to the respective inputs of latches  512  and  516  coupled to the drivers  504  are respective data signals  0 ,  63  and  63 ,  0 . 
     As shown in FIG. 5, the selection logic  500  is kept out of the critical delay paths with selection by multiplexers  518  and  522  being done after the data signals are latched by latches  510  and  514  for receiver connections and selection by multiplexers  520  and  524  is done before being latched by latches  512  and  516  for driver connections. 
     The selector signal RIGHT/LEFT can be programmed by a service processor (not shown) at initial program load (IPL) time, or a card pin could be assigned that is connect to power (pulled-up) if the card is mounted in a right hand slot and connected to ground (pulled-down) if the card is mounted in a left-hand slot. The latter solution would require an extra chip input to handle the selection signal. 
     Connection pin arrangement  400  and selection logic  500  work best for large busses, but the shared pins  402 , such as D 0 /D 63 , D 63 /D 0  are not required to be part of the same bus. Shared pins that are not part of busses can be handled by backplane wiring. Keeping these signals pins near the center of the connector minimizes the wiring congestion. It should be understood that correct I/O placement would keep the multiplexed drivers and receivers  502  and  504  physically close so that extra wiring is localized. When the multiplexing is done on the inboard side of the driver/receiver latches  510 ,  512  and  514 ,  516  as shown in FIG. 5, the multiplexing is provided without impacting any critical timing paths. 
     FIGS. 6,  7  and  8  illustrate exemplary applications for the connection arrangement  400  and selection logic circuitry  500  of the preferred embodiment. In FIG. 6, a first application generally designated  600  includes a main board  602  connected to a computer slot  604  via the connection arrangement  400  and selection logic circuitry  500 . The selection logic circuitry  500  is contained inside a chip  606  on the main board  602 . Typically chip  606  is a very large scale integrated (VLSI) semiconductor integrated circuit chip. The dual function signal pins  402  of the connection arrangement  400  are routed directly into the chip  606  containing selector logic  500 . 
     In FIG. 7, a second application generally designated  700  includes a plurality of cards (0-N)  702 , each connected to a main board  602  via the connection arrangement  400  and selection logic circuitry  500 . Each of the cards  702  includes a chip  606  containing selection logic circuitry  500 . The dual function signal pins  402  of the connection arrangement  400  are routed directly into the chip  606  containing selector logic  500 . The application  700  of FIG. 7 eliminates the need for two unique card designs required in the conventional arrangement of FIG. 3, saving money in design time, manufacturing costs, and fewer unique part numbers to stock for field replacements. Application  700  allows the use of a single card design  702  to implement for example, back-to-back processors card connections to the main board  602 . 
     In FIG. 8, other applications generally designated  800  includes a module  802  connected to a circuit card  702  via the connection arrangement  400  and selection logic circuitry  500 . A chip  606  contained within the module  802  contains the selection logic circuitry  500 . The dual function signal pins  402  of the connection arrangement  400  are routed directly into the chip  606  containing selector logic  500 . 
     It should be understood that the present invention is not limited to the illustrated applications  600 ,  700  and  800  of FIGS. 6,  7 , and  8 . For example, the invention could be applied to any board that has multiple instances of a device installed in different orientations as long as the device includes the selection logic  500  to route the bits based on its connection slot orientation with connection arrangement  400 . 
     While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.