Abstract:
The temperature of a thermo-electric cooler that is used to cool a laser is effectively controlled using a monitor which accurately and continuously measures the temperature of the thermo-electric cooler and using apparatus that determines the difference between the measured temperature and a desired thermo-electric cooler temperature. A discriminator circuit causes the thermo-electric cooler to enter (a) a heating cycle when such difference is below a first reference level or (b) a cooling cycle when such difference reaches a reaches a second reference level. Power consumption within the associated cooling/heating system is also accurately controlled using a pulse width modulated power supply to provide the voltage signal that drives the thermoelectric cooler.

Description:
FIELD OF THE INVENTION 
     The invention relates to ThermoElectric Coolers (TEC), and more particularly relates to an efficient controller for a TEC. 
     BACKGROUND OF THE INVENTION 
     It is well-known that the temperature of the active layers of a semiconductor laser must be closely controlled to operate the laser within close tolerances for both wavelength and power. A so-called ThermoElectric Cooler (TEC) is often used for this purpose, since a TEC can be controlled to either add or extract heat from a laser depending on whether the desired operating temperature is above or below the ambient temperature. However, the amount of power used to cool a high power laser to a desired temperature could exceed the amount of power that is used to drive the laser. This could lead to thermal runaway, since the additional power supplied to cool the laser may increase the temperature of the operating environment of the laser, rather than decreasing it. 
     A number of controllers have been developed to control the operation of a TEC, and thus the cooling/heating of a semiconductor laser. Included among these prior art controllers is the so-called proportional controller illustrated in FIG.  1 . The proportional controller uses two power supplies,  5 - 1  and  5 - 2 , which output voltages of opposite polarities but nomially of equal levels, e.g., ±5 volts, which are supplied to TEC  6  via transistors Q 6  and Q 8 , respectively, under control of amplifier  4 . Transistors Q 6  and Q 8  are controlled by amplifier  4 , which is connected to TEC  6  via feedback loop  6 - 1 . The voltage level in the feedback loop changes as the resistance of a thermister in TEC  6  changes, which indicates the current level of cooling at TEC  6 . That is, the TEC thermister is connected to a conventional balanced bridge circuit in the RF filter and amplifier circuit. The amplifier circuit amplifies an error signal that is developed across the bridge when the bridge is not balanced, and uses the amplified signal to “turn on” either transistor Q 6  or Q 8  a certain amount to respectively increase the cooling or heating that TEC  6  is supplying to the laser (not shown). 
     Disadvantageously, we have recognized that the control arrangement of FIG. 1 is inefficient, since each of the power supplies  5 - 1  and  5 - 2  have to operate at full voltage, even when only a fraction of that voltage level is being supplied to TEC  6 . For example, assume that each power supply needs to be at 5 volts to provide maximum cooing. If TEC  6  currently needs only 1 volt of cooling, then the remaining  4  volts would be dissipated across the respective one of the transistors Q 6  or Q 8  that is currently delivering the 1 volt to TEC  6 . 
     Another prior art controller which uses just one power supply is shown in FIG.  2 . Power supply  9 , more particularly, supplies a voltage signal, +TEC, and RTN (return) signal, to the TEC and RTN inputs of conventional H-bridge  10 . H-bridge  10  switches its inputs (+TEC and RTN) to its TECA and TECB outputs based on a set of logic signals that it receives via logic inputs COOL and HEAT. For example, if the input designated Heat is at a first logic level, e.g., ground/return, and the input designated COOL is at an second logic level, e.g., +5 volts, then H-bridge  10  switches its +TEC input to its TECA output and switches its RTN input to its TECB output, which are directly supplied to TEC  12  and which causes TEC  12  to enter a heating cycle. For the reverse case, in which the input designated HEAT is at the second logic level and the input designated COOL is at the first logic level, then H-bridge  12  switches its TEC input to its TECB output and switches its RTN input to its TECA output, which causes TEC  12  to enter a cooling cycle. Similarly, the TEC  12  thermister serves as an element in a balanced bridge within RF filter and amplifier circuit  7  to control the amount of cooling/heating that is supplied to a system laser (not shown). Circuit  7  amplifies the signal that the bridge outputs, and supplies the amplified result to comparator  8 . Comparator  8 , in turn, compares the amplified signal with a control signal indicative of the desired level of such cooling to determine if the level of the amplified signal is above (cool) or below (heat) the level of the control signal, and then adjusts the COOL and HEAT logic levels accordingly. 
     We have recognized that the controller of FIG. 2, for the most part, continuously alternates between a cooling cycle and heating cycle. The reason for this is that power supply  9  continuously supplies a voltage level that provides maximum cooling (or heating). That is, when the latter voltage level is supplied to TEC  12 , TEC  12  cools the semiconductor laser toward a maximum level. Since there is a delay between the time such cooling occurs and the time that the thermister signal reaches a level indicative thereof, the cooling that TEC  12  provides significantly overshoots the target level. At that point, amplifier  7  and comparator  8  invoke a heating cycle to drive the overcooling of the laser to the target temperature. The heating cycle similarly overshoots the target level which drives the level of heating at the laser beyond the desired level. At that point amplifier  7  and comparator  8  invoke a cooling cycle, and so on. The power expended to alternately provide such heating and cooling can result in the loss of an appreciable level of power as is illustrated in FIG. 3 by the shaded portions of the power diagram. 
     SUMMARY OF THE INVENTION 
     We address the foregoing problems, in accordance with various aspects of the invention, by comparing a difference signal indicative of the difference between the temperature of the thermoelectric cooler and a desired thermoelectric cooler temperature against first and second reference levels such that when the level of the difference signal is below the first reference level then the discriminator circuit causes the thermoelectric cooler to enter a heating cycle and such that when the level of the difference signal reaches the second reference level then the discriminator circuit causes the thermo-electric cooler to enter a cooling cycle. 
     We also accurately control the power consumption within the associated cooling/heating system using a pulse width modulated power supply to provide the voltage signal that drives the thermo-electric cooler. 
     These and other aspects of the claimed invention will become more apparent from the following detailed description and corresponding drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawing: 
     FIGS. 1 and 2 show in block diagram form prior art TEC controllers; 
     FIG. 3 illustrates a power/temperature diagram for the controller of FIG. 2; and 
     FIG. 4 is a block diagram of a TEC controller arranged in accordance with the principles of the invention. 
    
    
     DETAILED DESCRIPTION 
     An illustrative embodiment of our invention is shown in FIG.  4  and includes a conventional Pulse Width Modulator (PWM)  20  which modulates Vin, e.g., +5 volts, in accordance with a duty cycle that is controlled as a function of the level of a control signal supplied via path  46 . The level of the voltage that PWM  20  outputs across its +TEC and RTN output terminals increases as the PWM  20  duty cycle increases and vice versa. The PWM  20  duty cycle increases and decreases as the level of the path  46  signal increases and decreases, respectively. The voltage signal that PWM  20  outputs to the aforementioned output terminals is supplied to dump gate  25  (discussed below) and conventional H-bridge  30 . When the level of a ‘C’ (cool) control signal supplied via lead  76  is at the aforementioned first logic level, then H-bridge  30  switches its +TEC and RTN inputs directly to its output terminals TECA and TECB, respectively. When the level of a ‘H’ (heat) control signal supplied via lead  71  is at the first logic level then the H-bridge switches its +TEC and RTN inputs to the circuit  30  output terminals TECB and TECA, respectively. 
     The TECA and TECB outputs connect directly to conventional Thermo-Electric Cooler (TEC)  35 , whose temperature increases during a heating cycle and decreases during a cooling cycle, as is well-known. The temperature of TEC  35  is monitored by a conventional termperature sensitive device, e.g., THermister (TH)  36 , which is wired directly into a conventional balanced bridge circuit contained in RF filter and amplifier  80 , as discussed above. As is also well-known, the resistance of a thermister is related to the temperature of the environment in which the thermister is located, i.e. TEC  35 . 
     Similarly, RF filter and amplifier circuit  80  using a conventional difference circuit measures the difference between the voltage level developed across the bridge and the level of a voltage signal, Vset, indicative of a desired temperature setting for TEC  35 . The amplifier of circuit  80  greatly amplifies the difference signal and supplies the amplified difference signal to conventional absolute circuit  65 , which outputs the absolute value of the amplified difference signal to path  66  extending to one input of summing circuit (Σ)  45 . The amplified difference signal is also supplied to comparators  70  and  75  in the manner shown in FIG.  4 . 
     The level of the signal supplied by absolute circuit  65  is summed at summing circuit  45  with (a) a reference signal, V BG , supplied by source  55  and (b) the level of the signal that PWM  20  outputs to its +TEC output terminal. The level of the reference signal/voltage, V BG , is set to, for example, 1.25 v, to offset a so-called band-gap voltage that is inherently developed in PWM  20 . In this way, an offset voltage is supplied to PWM  20  when the difference signal is close to zero, indicating that the TEC  35  temperature is substantially at the target level. 
     The level of the control (or feedback) signal that summing circuit  45  supplies to PWM  20  via path  46  is also restricted by clamp  40 —which means that the level of the control signal will vary by no more than V BG ±0.7 v established by the voltage drop across clamp  40 . 
     As mentioned above, the amplified signal supplied via the output of circuit  80  is also supplied to comparators  70  and  75 . Comparators  75  and  70 , gate  60  and the signal levels provided across resistors R 1 , R 2  and R 3  form a discriminator circuit which controls the switching at H-bridge  30 . As discussed above, such switching controls the heating and cooling at TEC  30 . Specifically, the voltage level that is set at point ‘b’ represents a high temperature limit and the voltage level that is set at point ‘c’ represents a low temperature limit. For example, if the TEC  35  target temperature is, e.g., 25° C., then the lower and upper limits may be, e.g., 24° C. and 26° C., respectively. The “b’ voltage level is supplied to the + input of comparator  75  and the ‘c’ voltage level is supplied to the − input of comparator  70 . In this way, The TEC  35  temperature, as characterized by the resistance of thermister  36  and ultimately the value of the difference signal, is compared simltaneously with the low and high limits. If the TEC  35  temperature is found to be low, then the comparison performed by comparator  70  will be true, which causes comparator  70  to supply a control signal, e.g., the aforementioned first logic level, to H-bridge  30  via path  71 . Receipt of the latter logic level at the H input of control bridge  30 , causes the bridge to connect its input terminals +TEC and RTN (and thus the input voltage signal) directly to the TECA and TECB terminals extending to TEC  35 . TEC  35 , in turn, enters a heating cycle. If the TEC  35  temperature reaches the high limit, then the comparison performed by comparator  75  will be true, thereby causing that comparator to similarly supply the first logic level to H-bridge  30  via path  76 . Receipt of the latter logic level at the C input of control bridge  30 , causes the bridge to connect input terminals +TEC and RTN in reverse order to the TECA and TECB output terminals, which effectively reverses the polarity of the voltage signal supplied to TEC  35 . TEC  35 , in response thereto, enters a cooling cycle, all in accordance with an aspect of the invention. 
     As mentioned above and as illustrated in FIG. 3 for prior art systems, there is a delay between the time that such cooling (heating) occurs and the time that the thermister signal reaches a level indicative thereof, which causes the cooling (heating) that TEC  12  provides to significantly overshoot the target level. At that point, the TEC controller invokes a heating (cooling) cycle to drive the overcooling (overheating) of the laser to the target temperature. We deal with this problem by shunting the PWM  20  output voltage toward zero using dump gate  25 , all in accordance with an aspect of the invention. We also shunt to zero any residual voltage contained in absolute circuit  50  using dump gate  50 . In an illustrative embodiment of the invention, gates  25  and  50  may be, for example, an FET switch that switches (shunts) an input signal to ground via a resistor. More particularly, when the level of the amplified difference signal is between the voltage levels at points ‘b’ and ‘c’, respectively, then the comparison performed at comparators  70  and  75  fails, which causes both of those comparators to output a control signal indicative of the second logic level. NAND gate  60 , responsive to both outputs of comparators  70  and  75  being concurrently at the latter logic level, switches its output level to a low logic level. The low logic level at the output of gate  60  activates dump gates  25  and  50 , which then operate in the manner described above. 
     It will thus be appreciated that, although the invention illustrated herein is described in the context of a specific illustrative embodiment, those skilled in the art will be able to devise numerous alternative arrangement which, although, not explicitly shown or described herein, nevertheless, embody the principles of the invention and are within its spirit and scope.