Abstract:
A microelectronic device with programmable memory ( 10 ) includes a first metallic electrode ( 2 ) deposited at least in part on a substrate ( 1 ), a doped chalcogenide layer ( 3 ) deposited on the first metallic electrode ( 2 ) and a second metallic electrode ( 4 ) deposited on the doped chalcogenide layer ( 3 ). The device further has an intermediate layer ( 5 ) positioned between the first metallic electrode ( 2 ) and the doped chalcogenide layer ( 3 ), the intermediate layer ( 5 ) being a layer of a metallic element having the following properties a and b: a) a coefficient of thermal conductivity greater than or equal to 60 W/m·K; and b) mechanical stress less than or equal to −1600 MPa.

Description:
RELATED APPLICATION 
       [0001]    This application claims the benefit of priority from French Patent Application No. FR 11 59124, filed on Oct. 10, 2011, the entirety of which is incorporated by reference. 
       BACKGROUND 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a microelectronic device with programmable memory, including a layer of doped chalcogenide that withstands high temperatures, and also to a method of fabricating said device. 
         [0004]    2. Description of Prior Art 
         [0005]    Microelectronic devices with programmable memory are typically, but not exclusively, programmable cells with ionic conduction (metallization) constituting so-called “non-volatile” computer memory. Such programmable cells having ionic conduction are also known as conductive-bridging random access memory (CBRAM) or programmable metallization cells (PMCs). 
         [0006]    This type of microelectronic structure (CBRAM or PMC) is well known to the person skilled in the art, and is described for example in document U.S. Pat. No. 6,084,796. 
         [0007]    Typically, a CBRAM (or PMC) comprises a vertical stack of layers made up of a substrate based on a silicon type semiconductor having the following successive layers located thereon forming a three-layer structure: a so-called “bottom” electrode, a layer of a chalcogenide glass doped with silver (i.e. solid electrolyte), and a so-called “top” electrode of silver. The layer of chalcogenide glass (or chalcogenide layer) is thus interposed between the bottom and top electrodes. 
         [0008]    Those electrodes are configured to cause a metal dendrite to grow (thereby forming an electrical conduction bridge) from the more negative of the two electrodes towards the more positive of the two electrodes through the layer of doped chalcogenide glass when a voltage is applied to said electrodes. By applying an opposite voltage between those two electrodes, the opposite phenomenon is obtained, i.e. the metal dendrite disappears (i.e. the electrical conduction bridge disappears) from within the layer of doped chalcogenide glass. 
         [0009]    Thus, when the electrical conduction bridge is created (a so-called “writing” step) the logic state of the device may be represented by “1”, or may correspond to a “ON” state, whereas when the electrical conduction bridge disappears, the logic state of the cell may be represented by a “0” or may correspond to the “OFF” state. 
         [0010]    When the three-layer structure of the CBRAM is made, the stack formed in that way is subjected to steps during which temperature may be relatively high while it is being fabricated. 
         [0011]    More particularly, once the active elements such as transistors, etc. have been implanted in steps subsequent to forming the three-layer CBRAM structure, they need to be interconnected in order to form an electrical circuit. Making interconnections of that type is performed at the end of the fabrication line (known as the “back-end-of-line” (BEOL)). At the BEOL, the CBRAM structure may be subjected to temperatures lying in the range 300° C. to 450° C. 
         [0012]    A GeS 2  type chalcogenide that is stoichiometric (i.e. a non-doped chalcogenide) is known to have a glass transition temperature that is relatively high, thereby enabling it to remain stable in an amorphous state up to 450° C. without being subjected to any crystallization. 
         [0013]    Nevertheless, when the chalcogenide is doped with silver, the presence of silver can lead to a significant drop in its glass transition temperature. 
         [0014]    Thus, the temperatures lying in the range 300° C. to 450° C. as the BEOL can cause the physiochemical properties of the silver doped chalcogenide to be degraded. 
         [0015]    For example, agglomerations of silver may appear within and around the layer of doped chalcogenide. These agglomerations of silver may lead to short circuits between a plurality of CBRAM cells, and thus to a loss of electrical performance. 
         [0016]    If the BEOL temperature exceeds 300° C., it is possible to observe not only undulations appearing within and around the layer of doped chalcogenide (i.e. precursors of possible crystallization), thereby weakening the CBRAM structure to such an extent as to run the risk of breaking it, but also crystallization of the doped chalcogenide, which thus passes from an amorphous state so a crystalline state. The CBRAM then becomes unusable. 
       OBJECTS AND SUMMARY 
       [0017]    The object of the present invention is to mitigate the drawbacks of the prior art, in particular by proposing a microelectronic device with programmable memory, having a layer of doped chalcogenide, while making it possible to limit significantly or even avoid degradation of said layer at high temperatures, which may in particular be as high as 450° C., or even more. 
         [0018]    The present invention provides a microelectronic device with programmable memory, comprising: 
         [0019]    a first metallic electrode deposited at least in part on a substrate; 
         [0020]    a doped chalcogenide layer deposited on the first metallic electrode; and 
         [0021]    a second metallic electrode deposited on the doped chalcogenide layer; 
         [0022]    the device being characterized in that it further comprises an intermediate layer positioned between the first metallic electrode and the doped chalcogenide layer, said intermediate layer being a layer of a metallic element having the following properties a and b: 
         [0023]    a. a coefficient of thermal conductivity greater than or equal to 60 watts per meter per kelvin (W/m·K or Wm −1 K −1 ), preferably greater than or equal to 70 W/m·K, preferably greater than or equal to 90 W/m·K, and more preferably greater than or equal to 100 W/m·K; and 
         [0024]    b. mechanical stress less than or equal to −1600 megapascals (MPa), and preferably less than or equal to −2000 MPa. 
         [0025]    The term “layer of a metallic element” is used to mean a layer including at least said metallic element, preferably a layer comprising essentially said metallic element, and in more particularly preferred manner a layer comprising only said metallic element in the substantially pure state. 
         [0026]    When the layer comprises only said metallic element, it should be considered that it comprises “substantially” only one metallic element. The term “substantially” means that the intermediate layer may include inevitable impurities in addition to said metallic element. By way of example, the intermediate layer may comprise at least 98% by weight of said metallic element and preferably at least 99% by weight of said metallic element, with the remainder of the intermediate layer being constituted by inevitable impurities. 
         [0027]    The term “inevitable impurities” covers all metallic or non-metallic elements included in the intermediate layer during fabrication of the metallic element. By way of example, these impurities may be one or more of the following elements: Ag, Cd, Cr, Fe, Mg, Mn, Pb, S, Si, Ti, V, Ni, S, Fe, and/or Zn. 
         [0028]    In the present invention, the coefficient of thermal conductivity of a metallic element is well known to the person skilled in the art, and in particular this value is specific to each element and can be obtained from the periodic table of elements. 
         [0029]    Mechanical stress is determined at ambient temperature (i.e. 25° C.) using an instrument of the Flexus type (Tencor). 
         [0030]    The instrument measures the radius of curvature of the substrate (before and after depositing the intermediate layer) by interferometry using a laser beam. Mechanical stress values are then calculated directly using Stoney&#39;s formula, given that the thickness of the intermediate layer and of the substrate, and their respective Young&#39;s moduluses and Poisson coefficients are known. 
         [0031]    The mechanical stress expressed in the present invention has a negative value, i.e. it corresponds to so-called “compressive” stress. When the value of the mechanical stress is positive, then it is conventional to refer to “tensile” stress. 
         [0032]    The Applicant has discovered, surprisingly, that by interposing an intermediate layer of a metallic element having said properties a and b, between the first metallic electrode (“bottom” electrode) and the doped chalcogenide layer, the chalcogenide layer is much better at withstanding the high temperatures required for the BEOL steps that are subsequent to depositing the second electrode (“top” electrode). 
         [0033]    More particularly, the intermediate layer serves to limit significantly or even to avoid degradation of the chalcogenide layer at high temperatures, which temperatures may be as high as 450° C. or even higher. Thus, at the BEOL, the temperatures applied do not run any significant risk of damaging the microelectronic device with programmable memory. 
         [0034]    In addition, the intermediate layer of the invention may also act as a diffusion barrier. It can thus serve to prevent the dopant element(s) (from the doped chalcogenide layer) from diffusing into the first electrode. As a result, because of this diffusion barrier, the electrical efficiency of the microelectronic device of the invention, and thus its electrical performance, are optimized. 
         [0035]    The metallic element of the intermediate layer may be a transition metal. The metallic element of the intermediate layer is preferably ruthenium (Ru). Ruthenium presents a coefficient of thermal conductivity of about 117 W/m·K (property a), and a mechanical stress of about −2600 MPa. 
         [0036]    The thickness of the intermediate layer may lie in the range 3 nanometers (nm) to 7 nm, and may preferably be equal to 5 nm. 
         [0037]    In a particular embodiment of the invention, the microelectronic device need not include an intermediate layer (with the properties a and b as defined in the present invention) positioned between the doped chalcogenide layer and the second metallic electrode. 
         [0038]    Preferably, the microelectronic device of the invention may include, as an intermediate layer as defined in the invention, only the intermediate layer that is positioned between the first metallic electrode and the doped chalcogenide layer. 
         [0039]    If an intermediate layer were to be positioned between the doped chalcogenide layer and the second electrode, that intermediate layer would act as a diffusion barrier, thereby preventing an electrical conduction bridge being formed within the doped chalcogenide when a voltage is applied between the first and second electrodes. 
         [0040]    The doped chalcogenide layer is conventionally in electrical contact with the first and second electrodes in order to be capable of forming electrical conduction bridges when a voltage is applied between those two electrodes. Consequently, since the intermediate layer is a layer of a metallic element, and thus an electrically conductive layer, electrical contact between the chalcogenide layer and the first electrode is maintained. 
         [0041]    In a particular embodiment, the intermediate layer is directly in physical contact with the first metallic electrode and with the doped chalcogenide layer. 
         [0042]    In the present invention, the term “substrate” designates any type of structure, such as semiconductor substrates in particular, that may conventionally be based on silicon and/or on quartz. By way of example, the semiconductor substrate may be selected from substrates of silicon, silicon oxide, and quartz. 
         [0043]    By way of example, the semiconductor substrate may comprise silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) type semiconductors, doped or non-doped semiconductors, and/or layers of silicon grown epitaxially on a semiconductor base. Steps of the method may be used to form regions or junctions in or above the semiconductor base. 
         [0044]    The substrate is not necessarily semiconductive, but may be any type of support structure suitable for supporting an integrated circuit. For example, the substrate may be made of ceramic or it may be based on polymer. 
         [0045]    By way of example, the substrate may have thickness lying in the range 150 micrometers (μm) to 400 μm, or possibly extending up to 800 μm. 
         [0046]    The first and second electrodes of the invention correspond respectively to an anode or a cathode, or vice versa. 
         [0047]    The first electrode (i.e. “bottom” electrode) may be defined as being an inert electrode. The to “inert” is used of an electrode to designate an electrode that does not contribute to forming the electrical conduction bridge. In other words, the material of the first electrode is different from the material constituting the metallic element doping the layer of doped chalcogenide material. 
         [0048]    The first electrode may typically be made of a material selected from nickel, tungsten, a nickel alloy, a tungsten alloy, titanium, titanium nitride, tantalum, tantalum nitride, and a mixture thereof. 
         [0049]    The second electrode (i.e. “top” electrode) may be defined as being a reactive electrode: said second electrode is preferably different from the first electrode. The term “reactive” is used of an electrode to designate an electrode that participates in forming the electrical conduction bridge. In other words, the material of the second electrode is different from the material constituting the metallic element doping the layer of doped chalcogenide material. 
         [0050]    The metal of the second metallic electrode is preferably identical to the metallic doping element used for doping the (previously non-doped) chalcogenide layer. In other words, the second electrode may be identical to the material of the ionizable metallic layer. 
         [0051]    The second electrode may typically be made of a material selected from silver (Ag), a silver alloy, copper (Cu), a copper alloy, zinc (Zn), a zinc alloy, and a mixture thereof. The particularly preferred material being silver or a silver alloy. 
         [0052]    By way of example, the first and second electrodes may have thickness lying in the range 100 nm to 300 nm for the first electrode and in the range 10 nm to 100 nm for the second electrode. 
         [0053]    In the invention, the material of the chalcogenide layer is constituted in particular by an amorphous material. 
         [0054]    It comprises a chalcogenide, which is preferably a chalcogenide glass. 
         [0055]    A chalcogenide is conventionally made up of at least one chalcogen ion and at least one electropositive element. 
         [0056]    The chalcogens that constitute chalcogen ions are located in group 16 (i.e. group VIA) of the periodic table of elements, and those that are preferably used in the invention are sulfur (S), selenium (Se), and tellurium (Te). 
         [0057]    The electropositive element constituting the chalcogenide may, more particularly, be: 
         [0058]    an element of group 14 (i.e. group IVA) of the periodic table of elements, such as in particular silicon (Si) or germanium (Ge); or 
         [0059]    an element of group 15 (i.e. group VA) of the periodic table of elements, such as in particular phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi). 
         [0060]    Said electropositive element is preferably germanium (Ge) or arsenic (As). 
         [0061]    The term chalcogenide glass is used typically when the electropositive element of the chalcogenide belongs to group 14 or to group 15 of the periodic table of elements. 
         [0062]    As examples of chalcogenides, mention may be made of germanium selenide Ge x Se 100-x , germanium sulfide Ge x S 100-x , or arsenic sulfide As x S 100-x , where x is an integer, in particular lying in the range 1 to 99, and preferably in the range 18 to 50. 
         [0063]    The preferred chalcogenide is germanium sulfide Ge x S 100-x , in particular with 33≦x≦44, and in more particularly preferred manner with x=33. 
         [0064]    By way of example, the thickness of the chalcogenide layer may lie in the range 15 nm to 100 nm, and preferably lies in the range 20 nm to 50 nm. 
         [0065]    The layer of doped chalcogenide includes at least one dopant element of the metallic element type. 
         [0066]    This metallic element may preferably be selected from silver (Ag), a silver alloy, copper (Cu), a copper alloy, zinc (Zn), a zinc alloy, or a mixture thereof, the particularly preferred element being silver or a silver alloy. 
         [0067]    In the invention, the layer of doped chalcogenide is more particularly an amorphous layer. 
         [0068]    In a preferred embodiment, the microelectronic device of the invention is a programmable cell with ionic conduction (CBRAM or PMC). 
         [0069]    As a result, the microelectronic device of the invention cannot be considered as being a phase-change material (PCM) in which the chalcogenide changes phase by going from an amorphous state to a crystalline state. 
         [0070]    More particularly, the first and second electrodes are configured to cause a metallic dendrite to grow (i.e. to form an electrical conduction bridge) from the more negative of the two electrodes towards the more positive of the two electrodes through the layer of doped chalcogenide when a voltage is applied between said electrodes. When applying an opposite voltage between those two electrodes, the phenomenon inverses, i.e. the metallic dendrite disappears (i.e. the electrical conduction bridge disappears) within the layer of doped chalcocenide. 
         [0071]    The invention also provides the method of fabricating a microelectronic device with programmable memory, as defined above, the method being characterized in that it comprises the following steps: 
         [0072]    i. depositing a first metallic electrode on a substrate; 
         [0073]    ii. depositing an intermediate layer of a metallic element having properties a and b on the first electrode; 
         [0074]    iii. depositing a chalcogenide layer on the intermediate layer; 
         [0075]    iv. depositing an ionizable metallic layer on the chalcogenide layer; 
         [0076]    v. diffusing metallic ions from the ionizable metallic layer of step iv in the chalcogenide layer in order to form the doped chalcogenide layer; and 
         [0077]    vi. depositing a second metallic electrode on the doped chalcogenide layer. 
         [0078]    In a particular implementation, step ii is performed by direct current (DC) or radiofrequency (RF) cathode sputtering. 
         [0079]    By way of example, when the metallic element that is to be deposited is ruthenium, step ii is performed by DC cathode sputtering under argon at a pressure of 0.2 millitorr (mTorr) to 1 mTorr and at a power density of 1.3 watts per square centimeter (W/cm 2 ) to 2 W/cm 2 . 
         [0080]    Steps i, iii, iv, v, and vi are steps well known to the person skilled in the art. 
         [0081]    A few non-limiting implementations of each of these steps are mentioned below. 
         [0082]    The first and second electrodes of the invention are in particular metallic electrodes deposited by a chemical technique (chemical vapor deposition (CVD)) or by cathode sputtering (physical vapor deposition (PVD)) for the first electrode, and by RF or DC cathode sputtering for the second electrode. 
         [0083]    In order to obtain a layer of doped chalcogenide, it is possible to begin by depositing a layer of non-doped chalcogenide by cathode sputtering, and then to deposit on said layer of chalcogenide a metallic layer that is ionizable by cathode sputtering. 
         [0084]    Thus, a layer of doped chalcogenide is formed by applying a diffusion step that serves to cause metallic ions from the ionizable metallic layer to diffuse through the chalcogenide layer. 
         [0085]    This diffusion step may be performed by irradiation using ultraviolet rays and/or heat treatment, where both these two types of diffusion are well known to the person skilled in the art. 
         [0086]    In a first variant, step iv that consists in depositing a second metallic electrode on the layer of doped chalcogenide may be an additional step after step iv. 
         [0087]    In a second variant, step iv that consists in depositing a second metallic electrode on the layer of doped chalcogenide may be included in step iv. In other words, step iii serves both to deposit an ionizable metallic layer on the layer of chalcogenide, and also to deposit the second electrode while there still remains a portion of the ionizable metallic layer that has not been diffused (consumed) during diffusion step v. 
         [0088]    The method of the invention may also include a heat treatment step vii, subsequent to step vi, consisting in heating the microelectronic device to a temperature higher than or equal to the glass transition temperature of the layer of doped chalcogenide. 
         [0089]    By way of example, heat treatment is performed at a temperature of at least 300° C. 
         [0090]    Thus, because of the intermediate layer of the invention, the layer of doped chalcogenide is substantially not degraded. 
         [0091]    The invention also provides the use of a metallic element having above-defined properties a and b in a microelectronic device with programmable memory, including a layer of doped chalcogenide. 
         [0092]    This use may serve to limit significantly or even avoid degradation of the layer of doped chalcogenide at high temperatures, which temperatures may possibly be as high as 450° C., or even higher. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0093]    Other characteristics and advantages of the present invention appear in the light of the following examples given with reference to the annotated figures, which examples and figures are given by way of non-limiting illustration. 
           [0094]      FIG. 1  is a fragmentary cross-section view of a stack of layers of a microelectronic device with programmable memory of the invention. 
           [0095]      FIG. 2  is a flow chart showing the method of fabricating the  FIG. 1  microelectronic device. 
           [0096]      FIGS. 3   a  and  3   b  are scanning electron microscope (SEM) images of a stack of layers of the prior art, before and after heat treatment at 300° C. for 10 minutes. 
           [0097]      FIG. 4  shows optical microscope images of stacks of the prior art and of the invention, after heat treatment at 350° C. for 15 minutes. 
           [0098]      FIG. 5  shows scanning electron microscope (SEM) images of a stack of the invention after heat treatment at 450° C. for 15 minutes. 
       
    
    
     DETAILED DESCRIPTION 
       [0099]    For reasons of clarity, only elements that are essential for understanding the invention are shown, and they are shown diagrammatically without necessarily being to scale. 
         [0100]      FIG. 1  shows a particular stack  10  forming a microelectronic device with programmable memory, in accordance with the invention. 
         [0101]    Said stack  10  comprises the following successive layers: 
         [0102]    a substrate  1  comprising at least one layer placed on silicon and optionally a succession of elements well known to the person skilled in the art, the thickness of the substrate being of the order of 300 micrometers (μm); 
         [0103]    a layer  2  of tungsten forming the first electrode (i.e. the “bottom” electrode), the thickness of this layer being about 300 nm; 
         [0104]    an intermediate layer  5  of ruthenium, the thickness of this layer being about 5 nm; 
         [0105]    a layer  3  of a chalcogenide glass of the GeS 2  type, doped with silver, the thickness of this layer being about 50 nm; and
       a layer  4  of silver forming the second electrode (i.e. the “top” electrode), the thickness of this layer being about 30 nm.       
 
         [0107]    Naturally, the microelectronic device with programmable memory of the invention may include other layers deposited on the second electrode. 
         [0108]    The stack of  FIG. 1  was made using the method steps shown in detail in the flow chart of  FIG. 2 . 
         [0109]    In a first step (step i), the tungsten electrode  2  is deposited on the silicon based substrate  1  by chemical vapor deposition (CVD). 
         [0110]    Thereafter, in a second step (step ii), the ruthenium layer  5  is deposited on the tungsten electrode  2  by cathode sputtering with a power density of 1.5 W/cm 2  in an argon atmosphere at a pressure of 0.4 mTorr. 
         [0111]    Thereafter, in a third step (step iii), a layer of non-doped GeS 2  type chalcogenide glass is deposited on the ruthenium layer, by cathode sputtering. 
         [0112]    In a fourth step (step iv), a 20 nm thick layer of silver (or silver alloy) is then deposited on the non-doped GeS 2  type chalcogenide glass layer by vacuum cathode sputtering in an argon atmosphere. 
         [0113]    In a fifth step (step v), this silver layer is then irradiated by ultraviolet radiation at sufficient intensity and for a sufficient duration to ensure that the silver ions coming from the silver layer diffuse into the chalcogenide layer, to form the doped chalcogenide layer  3 . 
         [0114]    Finally, in a sixth step (step vi), the electrode  4  of silver or silver alloy is deposited on the doped chalcogenide layer by cathode sputtering in a vacuum plasma reactor in the presence of argon. 
       EXAMPLES 
       [0115]    A series of tests were performed by simulating the heat budget encountered during industrial fabrication of a CBRAM stack by vacuum annealing for 15 minutes at temperatures lying in the range 300° C. to 450° C. 
         [0116]    The CBRAM stacks made were of the type shown in  FIG. 1 , with a few differences, namely: 
         [0117]    a stack E 1  identical to that of  FIG. 1 , except that it did not have an intermediate layer of ruthenium; 
         [0118]    a stack E 2  identical to that of  FIG. 1 , except that the intermediate layer of ruthenium (Ru) was replaced by a layer of tantalum (Ta); 
         [0119]    a stack E 3  identical to that of  FIG. 1 , except that the intermediate layer of ruthenium (Ru) was replaced by a layer of tantalum nitride (TaN); 
         [0120]    a stack E 4  identical to that of  FIG. 1 , except that the intermediate layer of ruthenium (Ru) was replaced by a layer of platinum (Pt); and 
         [0121]    a stack E 5  identical to that of  FIG. 1 , in accordance with the invention. 
         [0122]    The operating conditions for depositing the layers constituting the stacks were identical to those described for  FIG. 2 , the intermediate layer having a thickness of 5 nm in the stacks E 2  to E 5 . 
         [0123]    The thermal conductivity coefficients and the mechanical stresses of the various 5 nm thick intermediate metal layers (Ti, Ta, TaN, Pt, and Ru) are summarized in Table 1 below. 
         [0000]    
       
         
               
               
               
               
             
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                   
                 Mechanical stress 
                 Coefficient of 
               
               
                   
                 Intermediate 
                 at 25° C. 
                 thermal conductivity 
               
               
                   
                 layer 
                 (MPa) 
                 (W/m · K) 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 Ti 
                 −2600 
                 21.9 
               
               
                   
                 Ta 
                 −1600 
                 57.5 
               
               
                   
                 TaN 
                 −3700 
                 &lt;57.5 
               
               
                   
                 Pt 
                 +400 
                 71.6 
               
               
                   
                 Ru 
                 −2600 
                 117 
               
               
                   
                   
               
             
          
         
       
     
         [0124]    The respective thermal conductivity coefficients of the elements Ti, Ta, Pt, and Ru are taken from the periodic table of elements. 
         [0125]    The thermal conductivity coefficient of TaN depends both on the element Ta and on the element N, and also on their respective atomic weighting in TaN (conventionally 15 atomic percentage (at %) to 20 at % of N in TaN). Since the thermal conductivity coefficient of nitrogen is 0.026 (W/m·K), i.e. much less than the thermal conductivity coefficient of Ta (cf. 57.5 W/m·K), the thermal conductivity coefficient of TaN is therefore less than 57.5 W/m·k (being about 30 W/m·K to 40 W/m·K). 
         [0126]    It may be observed that tungsten (K), i.e. the metal used for fabricating the first electrode (the “bottom” electrode) in the example of  FIG. 1  has mechanical stress at 25° C. of +20 MPa and a coefficient of thermal conductivity of 174 W/m·K. Its mechanical stress is thus much greater than that of the present invention (property b). 
         [0127]    The CBRAM stacks E 1  to E 5  as formed in that way were placed in a low temperature vertical oven (≦600° C.) of the SVG VTR7000 type in the presence of nitrogen gas and they were subjected for 15 minutes to a temperature lying in the range 300° C. to 450° C. 
         [0128]    The surface of each stack as heat treated in that way was inspected optically using an optical microscope of the Leica INS1000i type and/or a scanning electron microscope (SEM). 
         [0129]      FIGS. 3   a  and  3   b  show scanning electron microscope (SEM) images of the stack E 1  in semi-inclined view (on the left-hand side) and in cross-section view (on the right-hand side). 
         [0130]      FIG. 3   a  shows the stack E 1  without heat treatment. 
         [0131]      FIG. 3   b  shows the stack E 1  after heat treatment at 300° C. for 10 minutes. It can clearly be seen that agglomerates of silver have appeared on the surface in  FIG. 3   b.    
         [0132]      FIG. 4  shows optical microscope images of the stacks E 2  ( FIG. 4   a ), E 3  ( FIG. 4   b ), E 4  ( FIG. 4   c ), and E 5  ( FIG. 4   d ), after heat treatment at 350° C. for 15 minutes. 
         [0133]      FIG. 5  shows scanning electron microscope (SEM) images of the stack E 5  after heat treatment at 450° C. for 15 minutes. 
         [0134]    It can be seen very clearly in  FIG. 4  that after heat treatment at 350° C. for 15 minutes, the stack E 2  with an intermediate layer of tantalum (Ta) presents advanced crystallization, and the stack E 3  with an intermediate layer of tantalum nitride (TaN) presents the beginning of silver defects (extrusions). The same observation applies to the intermediate layer of platinum (Pt) (i.e. stack E 4 ) as for the intermediate layer of tantalum nitride (i.e. stack E 3 ), with defects that are less apparent. 
         [0135]    The stack E 5  does not present any visible defect (e.g. no silver defect and no crystallization), both after heat treatment at 350° C. for 15 minutes (see  FIG. 4   d ) and after heat treatment at 450° C. for 15 minutes (see  FIG. 5 ).