Abstract:
A semiconductor device has a diffusion layer formed on a silicon substrate, an interlayer insulator which covers a surface of the silicon substrate and whose surface is planarized, and a dielectric capacitor composed of a lower electrode connected to the diffusion layer via a buried conductive layer which is buried within a contact hole opened in the interlayer insulator and which is formed of a barrier metal layer composed of a contact plug, a low resistance layer and tantalum silicon nitride, and a dielectric film formed on the lower electrode, and an upper electrode. The lower electrode has a side-wall sloped configuration that its cross-sectional area monotonously increases from the buried conductive layer side toward the upper dielectric film. Thus, a high-integration semiconductor device which allows the lower electrode to be micro-fabricated and enables lower-voltage operation and higher reliability can be obtained.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The present invention relates to a semiconductor device having a micro-fabricated dielectric capacitor, as well as a manufacturing method therefor. More particularly, the invention relates to a semiconductor storage device having a ferroelectric capacitor as well as a manufacturing method therefor.  
           [0002]    Nonvolatile ferroelectric memory devices using a ferroelectric typified by Pb(Zr, Ti)O 3 (PZT) or the like as a capacitor have particularly been receiving attention, in recent years, against the background of their characteristics such as high speed and low power consumption. For high integration of these devices, it is necessary to develop a memory cell structure suitable for microfabrication and to develop a microfabrication technique for a ferroelectric capacitor composed of an upper electrode, a ferroelectric film and a lower electrode. Conventionally, an upper electrode of a ferroelectric capacitor and a diffusion layer (source, drain) of a MOS transistor have been connected to each other by local interconnections. In the stack type memory cell structure, the lower electrode of the ferroelectric capacitor and the diffusion layer are connected to each other by a contact plug, thereby allowing the memory cell area to be reduced. In this case, however, in order to prevent the contact plug formed of polysilicon or the like from reacting with the lower electrode, a barrier metal layer of titanium nitride (TiN) or the like is inserted therebetween. This causes the step gap of the ferroelectric capacitor to increase, which in turn causes occurrence of problem in the later interlayer insulator process or wiring process. Also, in the terraced structure, which is a conventional ferroelectric capacitor structure formed by sequentially etching an upper electrode, a ferroelectric film and a lower electrode, the ferroelectric capacitor, particularly the lower electrode is made of a material of poor processibility such as platinum or iridium, being hard to etch, so that its side wall shows a very gentle slope (taper angle: about 40 degrees). Thus, the terraced structure is a structure which is very hard to micro-fabricate and which is a cause of short-circuit between upper and lower electrodes due to re-deposition of reaction product generated in the etching onto the ferroelectric capacitor.  
           [0003]    To solve these problems, Japanese Patent Laid-Open Publication HEI 9-162369 proposes a memory cell structure as shown in FIG. 16. In FIG. 16, there are shown a silicon substrate  1 , a gate electrode  2 , a diffusion layer (source, drain)  3 , a first interlayer insulator  4 , a titanium film  201 , a TiN plug  202 , a second interlayer insulator  8 , a lower electrode  9 , a ferroelectric film  11 , an upper electrode  12 , a third interlayer insulator  14 , a bit line  15 , and a plate line  16 .  
           [0004]    In the structure disclosed in the above publication, the Ti  201  and the TiN  202  are buried in the contact plug by CVD process so that the step gap of the ferroelectric capacitor can be reduced. Also, the lower electrode  9  is processed before the formation of the ferroelectric film  11  so that short-circuiting between the upper electrode  12  and the lower electrode  9  due to redeposition during the etching can be prevented.  
           [0005]    However, since normal etching technique is used for the processing of the lower electrode, occurrence of tapers at the lower electrode side wall is unavoidable as shown in FIG. 16, making it highly likely that the tapers would make an obstacle in further microfabrication. Also, the contact plug, for which TiN is used, has a thermal resistance of only up to a temperature of about 650° C. Therefore, when SrBi 2 Ta 2 O 9  (SBT), which is a ferroelectric material having lower-voltage operation capability and higher reliability than PZT, is used for a ferroelectric capacitor, its formation requires, generally, a temperature of 700° C. or higher, which inhibits the use of a TiN plug.  
         SUMMARY OF THE INVENTION  
         [0006]    The present invention having been accomplished with a view to solving these and other problems, an object of the invention is to provide a high-integration semiconductor device, as well as a manufacturing method therefor, which allows the lower electrode to be micro-fabricated, as could not be achieved by the prior art, and which enables lower-voltage operation and higher reliability.  
           [0007]    In order to achieve the above object, there is provided a semiconductor device comprising:  
           [0008]    a diffusion layer formed on a semiconductor substrate;  
           [0009]    an interlayer insulator which covers a surface of the semiconductor substrate and whose surface is planarized; and  
           [0010]    a dielectric capacitor comprising a lower electrode connected to the diffusion layer via a buried conductive layer which is buried within a contact hole opened in the interlayer insulator and which includes a lower plug member and an upper barrier layer, and a dielectric film formed on the lower electrode, and an upper  
           [0011]    electrode formed on the dielectric film wherein the lower electrode has a side-wall sloped configuration that its cross-sectional area monotonously increases from the buried conductive layer side toward the upper dielectric film.  
           [0012]    This semiconductor device and manufacturing method therefor can solve the problems of the prior art and are very useful.  
           [0013]    More specifically, according to the present invention, since the lower electrode is formed not by dry etching but by CMP process, a micro-fabricated ferroelectric capacitor structure having a lower electrode size of 1.3 μm and a capacitor ferroelectric size of 1.75 μm is formed up. In the structure shown in the prior art, given a taper angle of 40 degrees for processing of lower-electrode iridium, the machining size for the lower electrode (film thickness: 250 nm) including various process margins is 1.4 μm at minimum, which leads to a capacitor ferroelectric size of 1.85 μm. From this fact, the area occupied by the ferroelectric capacitor is about 90% of the prior-art counterpart, showing an effectiveness to further scale-down of microfabrication. Also, according to the present invention, since TaSiN is used for the barrier metal layer, SBT that requires thermal treatment of about 700° C. becomes usable, so that a ferroelectric memory device operable at low voltage and having high reliability can be formed. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:  
         [0015]    [0015]FIG. 1 is a sectional view showing the structure of a memory cell part in a semiconductor storage device which is an embodiment of the invention;  
         [0016]    [0016]FIG. 2 is a manufacturing-process sectional view showing a cross-sectional structure at a first-stage time point in a manufacturing process of a semiconductor storage device which is an embodiment of the invention;  
         [0017]    [0017]FIG. 3 is a manufacturing-process sectional view showing a cross-sectional structure at a second-stage time point in the manufacturing process of the semiconductor storage device which is an embodiment of the invention;  
         [0018]    [0018]FIG. 4 is a manufacturing-process sectional view showing a cross-sectional structure at a third-stage time point in the manufacturing process of the semiconductor storage device which is an embodiment of the invention;  
         [0019]    [0019]FIG. 5 is a manufacturing-process sectional view showing a cross-sectional structure at a fourth-stage time point in the manufacturing process of the semiconductor storage device which is an embodiment of the invention;  
         [0020]    [0020]FIG. 6 is a manufacturing-process sectional view showing a cross-sectional structure at a fifth-stage time point in the manufacturing process of the semiconductor storage device which is an embodiment of the invention;  
         [0021]    [0021]FIG. 7 is a manufacturing-process sectional view showing a cross-sectional structure at a sixth-stage time point in the manufacturing process of the semiconductor storage device which is an embodiment of the invention;  
         [0022]    [0022]FIG. 8 is a manufacturing-process sectional view showing a cross-sectional structure at a seventh-stage time point in the manufacturing process of the semiconductor storage device which is an embodiment of the invention;  
         [0023]    [0023]FIG. 9 is a manufacturing-process sectional view showing a cross-sectional structure at an eighth-stage time point in the manufacturing process of the semiconductor storage device which is an embodiment of the invention;  
         [0024]    [0024]FIG. 10 is a manufacturing-process sectional view showing a cross-sectional structure at a ninth-stage time point in the manufacturing process of the semiconductor storage device which is an embodiment of the invention;  
         [0025]    [0025]FIG. 11 is a manufacturing-process sectional view showing a cross-sectional structure at a tenth-stage time point in the manufacturing process of the semiconductor storage device which is an embodiment of the invention;  
         [0026]    [0026]FIG. 12 is a manufacturing-process sectional view showing a cross-sectional structure at an eleventh-stage time point in the manufacturing process of the semiconductor storage device which is an embodiment of the invention;  
         [0027]    [0027]FIG. 13 is a manufacturing-process sectional view showing a cross-sectional structure at a twelfth-stage time point in the manufacturing process of the semiconductor storage device which is an embodiment of the invention;  
         [0028]    [0028]FIG. 14 is a chart showing results of evaluating the thermal resistance on TaSiN and TiN;  
         [0029]    [0029]FIG. 15 is a chart showing hysteresis characteristics of the ferroelectric capacitor in the embodiment of the invention; and  
         [0030]    [0030]FIG. 16 is a sectional view showing the structure of a memory cell part in a semiconductor storage device according to the prior art. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0031]    Hereinbelow, the present invention is described in detail by way of embodiments thereof.  
         [0032]    [0032]FIG. 1 is a sectional structural view showing the structure of a memory cell part (composed of a ferroelectric capacitor and a switching MOS transistor) in a semiconductor storage device which is an embodiment of the invention.  
         [0033]    In FIG. 1, there are shown a silicon substrate  1 , a polysilicon gate electrode  2 , a diffusion layer (source, drain)  3 , a first interlayer insulator  4  made of silicon oxide, a contact plug  5  made of polysilicon, a low resistance layer  6  formed by processing titanium silicide for lower resistance, a barrier metal layer  7  made of tantalum silicon nitride, an interlayer insulator  8  made of silicon nitride, a lower electrode  10  made of iridium, a ferroelectric film  11  made of SBT, an upper electrode  12  made of iridium, a diffusion barrier film  13  made of titanium oxide, a second interlayer insulator  14  made of NSG (Nondoped Silicate Glass), a bit line  15 , and a plate line  16 .  
         [0034]    A first characteristic structure in the semiconductor storage device of this embodiment is that the lower electrode  10  has a side-wall sloped configuration (cone-shaped or bow-shaped or other configuration) that its cross-sectional area monotonously increases from the barrier metal layer  7  side toward the ferroelectric film  11 . Further, the semiconductor storage device has an insulator film  8  that covers the side wall of the lower electrode  10 , the surface of this insulator film  8  being flattened and flush with the surface of the lower electrode  10 .  
         [0035]    Another characteristic structure is that a barrier metal layer  7  composed of tantalum silicon nitride is formed as a barrier metal layer to be buried into the uppermost portion within the contact hole formed in the first interlayer insulator  4 .  
         [0036]    Next, the method for manufacturing the semiconductor storage device of the above embodiment of the invention is described with reference to FIGS.  2  to FIG. 13.  
         [0037]    First, by the prior art, a switching MOS transistor having a polysilicon gate electrode  2  and a diffusion layer  3  are formed on a silicon substrate  1 . Thereafter, a first interlayer insulator (silicon oxide)  4  is deposited, and a 0.6 μm dia. contact hole is formed by photolithography process and dry etching process. Next, polysilicon is deposited by low pressure CVD process and thereafter phosphorus is doped into the polysilicon by thermal diffusion. Next, the polysilicon is polished by CMP (Chemical Mechanical Polishing) process so that the polysilicon on the first interlayer insulator  4  is completely removed, by which a contact plug  5  is formed (FIG. 2).  
         [0038]    Next, an overall etchback is done by dry etching process (FIG. 3). For etchback conditions in this case, it is the only requirement that the etching rate of polysilicon has a selection ratio of not less than 10 with respect to silicon oxide. The etchback amount for polysilicon is preferably 80-100 nm. Too large amounts of etchback would result in an incomplete burying during the barrier metal deposition, while too small amounts of etchback conversely would make it impossible to ensure a film thickness at which the barrier metal functions.  
         [0039]    Next, titanium is deposited to 20 nm by DC magnetron sputtering process. Thereafter, titanium and silicon are reacted with each other by RTA (Rapid Thermal Anneal) process, by which titanium silicide is formed on the contact plug  5 . As to the conditions for this RTA process, the process is preferably carried out at a temperature of 600°-700° C. for a period of 30 sec.-1 minute in a nitrogen atmosphere. Too low temperatures would cause the reaction of titanium and silicon to be retarded, while too high temperatures conversely would cause excessive growth of titanium silicide to be developed. Next, to remove titanium except the titanium on the contact plug  5 , a wet process is performed with sulfuric acid solution. Next, RTA process is performed once more to make the formed titanium silicide low in resistance, by which a low resistance layer  6  is formed (FIG. 4). As to the conditions for this RTA process, the process is preferably carried out at a temperature of 800°-900° C. for a period of 10-20 sec. in a nitrogen atmosphere. Too low temperatures would cause an insufficient resistance lowering of titanium silicide, while too high temperatures conversely would adversely affect the MOS transistor. This low resistance layer  6  is not limited to titanium silicide, and needs only to be capable of lowering the resistance between polysilicon and barrier metal and have a thermal resistance of not less than 700° C. Cobalt silicide may be used as an example.  
         [0040]    Next, a tantalum silicon nitride (TaSiN) film  107  is deposited overall to 150 nm by reactive DC magnetron sputtering process (FIG. 5).  
         [0041]    Next, the TaSiN film  107  is polished by CMP process so that the TaSiN film on the first interlayer insulator  4  is completely removed, by which a barrier metal layer  7  is formed (FIG. 6). It has been found out that TaSiN is superior in thermal resistance to TiN. FIG. 14 shows results of evaluating the thermal resistance on TaSiN and TiN, where the axis of abscissas represents thermal treatment temperature in nitrogen and the axis of ordinates represents normalized sheet resistance. With the same film thickness (100 nm in this case), TiN shows a remarkable increase of sheet resistance at 600° C., the resulting value of sheet resistance being a double of its initial value, while TaSiN shows an increase of sheet resistance as low as about 20% even by the thermal treatment of around 700° C. Therefore, TaSiN can form a barrier metal that endures even the SBT formation temperature (700° C.).  
         [0042]    Next, silicon nitride  108  is deposited overall to 250 nm by known plasma CVD process. The process for forming the silicon nitride  108  is not limited to the above plasma CVD process, and may be low pressure CVD process. Subsequently, silicon oxide  109  is deposited to 20 nm by atmospheric pressure CVD process (FIG. 7).  
         [0043]    Next, the barrier metal layer  7  and the silicon oxide  109  on peripheral part of the barrier metal layer  7  are removed by photolithography process and wet etching process. While the silicon oxide  109  from which the barrier metal layer  7  and the silicon oxide  109  on peripheral part of the barrier metal layer  7  have been removed is used as a mask, the silicon nitride  108  is removed with phosphorus acid heated to 150° C., by which an insulating film  8  is formed. Since the part from which silicon nitride has been removed is 1.3 μm square, which has been obtained by wet etching with phosphorus acid, the silicon nitride has been removed isotropically, the resulting side-wall configuration being bow shaped. The method for removing the insulating film is not limited to the one shown in this embodiment, and normal photolithography process and dry etching process may also be used only if the side-wall portion of the removal part is bow-shaped or conical-shaped. Thereafter, the mask silicon oxide  109  is removed (FIG. 8).  
         [0044]    Next, iridium  110  to form the lower electrode is deposited overall to 300 nm by DC magnetron sputtering process (FIG. 9). In this case, since the side wall of the part from which silicon nitride has been removed is bow-shaped, the iridium  110  is deposited evenly also to the side wall portion.  
         [0045]    Next, the iridium  110  is polished by CMP process until the insulating film  8  is exposed so that the iridium  110  and the insulating film  8  become flush with each other. Thus, a configuration that the side wall of the lower electrode  10  is covered with the insulating film  8  is formed (FIG. 10).  
         [0046]    Thereafter, an SBT film  111  is formed as a ferroelectric film, and then an iridium film  112  to form an upper electrode is formed to 100 nm by DC magnetron sputtering process (FIG. 11). The method for forming the SBT film  111  is as follows. First, an organometallic solution containing individual metal element of Sr, Ta and Bi is applied by spin coating process and allowed to dry, and then a crystallization annealing process at 700° C. for 30 min. is performed in an atmospheric-pressure oxygen atmosphere. This processing is iterated until the thickness of the SBT film becomes a desired thickness. It is noted that the element ratio of the organometallic solution is set as Sr:Bi:Ta=0.8:2.4:2.0 in this case and that the final film thickness is 150 nm.  
         [0047]    Thereafter, an upper electrode  12  and a capacitor ferroelectric film  11  are patterned and formed by using photolithography process and dry etching process (FIG. 12). The size of the upper electrode and the capacitor ferroelectric film in this case is 1.75 μm square. After the formation of the capacitor ferroelectric film  11 , an electrode annealing process at 700° C. for 30 min. is performed in an atmospheric-pressure oxygen atmosphere.  
         [0048]    Subsequently, titanium oxide  13  as a diffusion barrier film and NSG  14  as a third interlayer insulator are deposited sequentially (FIG. 13). The titanium oxide  13  is formed by reactive DC magnetron sputtering process and the NSG  14  is formed by atmospheric pressure CVD process.  
         [0049]    Next, contact holes leading to the upper electrode  12  of the ferroelectric capacitor and the other diffusion layer  3  of the MOS transistor are opened by photolithography process and dry etching process. Subsequently, an interconnecting process is performed to form a bit line  15  and a plate line  16 , by which the device is completed (FIG. 1).  
         [0050]    [0050]FIG. 15 shows hysteresis characteristics of the ferroelectric capacitor formed by the manufacturing method of this embodiment. A ferroelectric capacitor exhibiting a relatively good characteristic of about 15 uC/cm 2  at 2 Pr, which represents the performance of the ferroelectric, with an applied voltage of ±3 V was able to be obtained.  
         [0051]    The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.