Abstract:
A device for measuring the probe impedance of a linear lambda probe of an internal combustion engine which is caused by an AC current measurement signal which is fed into the lambda probe, comprises a voltage amplifier for amplifying an AC voltage which drops across the probe impedance, and a rectifier for rectifying the amplified AC voltage, wherein the rectifier is a synchronous demodulator, by which in each case the upper and lower amplitude of the AC voltage signal is sampled with its frequency, filtered and stored, and by which the difference of the stored signals is amplified with a gain factor and made available as output signal at its output for controlling the temperature of the lambda probe.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
         [0001]    This application is a continuation-in-part of copending International Application No. PCT/DE01/02575 filed Jul. 10, 2001, which designates the United States.  
         BACKGROUND OF THE INVENTION  
         [0002]    The invention relates to a circuit for determining the internal resistance of a linear lambda probe.  
           [0003]    The transmission function of a linear lambda probe has a high degree of dependence on temperature, which has to be compensated by controlling the probe temperature. However, for reasons of cost the probe temperature is not measured by means of a separate sensor (for example Pt100) but instead the high temperature dependence of the probe impedance Ri is utilized. FIG. 1 shows the temperature dependence and equivalent circuit of the probe impedance. Here, R 1 /C 1  represents the contact resistance between electrodes and ceramic material, R 2 /C 2  represents the junction between the grain boundaries of the sintered ceramic grains, and R 3  represents the intrinsic resistance of the sintered material.  
           [0004]    R 1  is highly subject to ageing and therefore cannot be used for measuring temperature. Given a suitable selection of the measurement frequency—for example 3 kHz—R 1  is short-circuited in terms of AC voltage by means of C 1 ; it therefore makes no contribution to the overall impedance any more. The series connection of R 2 /C 2  and R 1  yields an absolute value of 100 ohms with this measuring frequency at approximately 500° C. and can be used for determining the temperature.  
           [0005]    The older patent application 2000 P 12334 DE (official file number not yet known) which was not published before the priority date describes a customary measurement method for determining the probe impedance R 1 . According to said method, a square-wave AC current, for example 500 μAss (peak-to-peak), is applied to the probe impedance.  
           [0006]    An AC voltage of 500 μAss*100 ohm=50 mVss is produced at R 1 . This AC voltage is amplified and rectified and can then be fed to a microprocessor for controlling the temperature.  
           [0007]    The AC current is generated according to FIG. 2, for example, by means of a 3 kHz square-wave oscillator which is supplied with 5 V. The signal is conducted to the probe impedance via a high impedance resistor Rv and a decoupling capacitor Cv.  
         SUMMARY OF THE INVENTION  
         [0008]    The object of the invention is to improve the measurement of the impedance (of the internal resistance) Ri of a linear lambda probe and to reduce the error in the rectification of the AC voltage signal, and to reduce the sensitivity to electromagnetic interference pulses (EMC). In general terms, the object of the invention is to acquire precisely the peak-to-peak amplitude value (Vss) of an AC voltage signal whose phase is known and on which a DC voltage is superimposed.  
           [0009]    This object can be achieved by a device for measuring the probe impedance of a linear lambda probe of an internal combustion engine which is caused by an AC current measurement signal which is fed into the lambda probe, having a voltage amplifier for amplifying an AC voltage which drops across the probe impedance, and having a rectifier for rectifying the amplified AC voltage, wherein the rectifier is a synchronous demodulator, by which in each case the upper and lower amplitude of the AC voltage signal is sampled with its frequency, filtered and stored, and by which the difference of the stored signals is amplified with a gain factor and made available as output signal at its output for controlling the temperature of the lambda probe.  
           [0010]    An oscillator can be provided from whose output signal both the AC current measurement signal and the control signals for the synchronous demodulator are acquired. The synchronous demodulator may comprise a first sample&amp;hold circuit in which the upper amplitude of the input signal is sampled and held, a second sample&amp;hold circuit in which the lower amplitude of the input signal is sampled and held, a decoupling amplifier connected downstream of each sample&amp;hold circuit, and a differential amplifier which forms a differential signal from the output signals of the two decoupling amplifiers and makes available as output signal at the output of the synchronous demodulator as control signal for controlling the temperature of the lambda probe. The resistor and the capacitor of each sample&amp;hold circuit may form, in the sampling phase, a low-pass filter for the integrated averaging of the input signal, and the capacitors may act as holding capacitors in the hold phase. Each of the two capacitors can be placed at a predefined potential. Both of the decoupling amplifiers can have a predefined gain factor. A resistor can be arranged between the output of each of the two decoupling amplifiers and the assigned input of the differential amplifier, and both resistors may have the same resistance value. A voltage divider may lead from the noninverting input of the differential amplifier to a reference potential, and a resistor can be arranged between the tap of the voltage divider and a predefined potential. The resistance value of the series connection of the resistors can be equal to that of a resistor which is arranged between the output and inverting input of the differential amplifier. By actuating the switches with control signals, the synchronous demodulator may sample in each case only a portion which is less than 50% of the period of the AC voltage signal with its frequency.  
           [0011]    A method for measuring the probe impedance of a linear lambda probe of an internal combustion engine, may comprise the steps of:  
           [0012]    feeding an AC current measurement signal into the lambda probe;  
           [0013]    amplifying an AC voltage which drops across the probe impedance, and  
           [0014]    rectifying the amplified AC voltage by means of a synchronous demodulator, by which in each case the upper and lower amplitude of the AC voltage signal is sampled with its frequency, filtered and stored, and by which the difference of the stored signals is amplified with a gain factor and made available as output signal at its output for controlling the temperature of the lambda probe.  
           [0015]    The method may further comprise the step of generating an oscillator signal from which both the AC current measurement signal and the control signals for the synchronous demodulator are acquired. The method may further comprise the steps of:  
           [0016]    sampling and holding the upper amplitude of the input signal;  
           [0017]    sampling and holding the lower amplitude of the input signal;  
           [0018]    decoupling the sampled and held signals, and  
           [0019]    forming a differential signal from the decoupled signals and making it available as an output signal at the output of the synchronous demodulator as a control signal for controlling the temperature of the lambda probe. The method can further comprise the step of providing, in the sampling phase, a low-pass filter for the integrated averaging of the input signal. The decoupling can be performed with a predefined gain factor. The step of sampling and holding can be performed in such a way that in each case only a portion which is less than 50% of the period of the AC voltage signal with its frequency is sampled. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]    [0020]FIG. 1 shows the temperature dependence and equivalent circuit of the probe impedance,  
         [0021]    [0021]FIG. 2 shows the circuit of a device for measuring the probe impedance,  
         [0022]    [0022]FIG. 3 shows a peak value rectifier,  
         [0023]    [0023]FIG. 4 shows a DC voltage which corresponds to the lower peak value of the input (AC+DC) voltage,  
         [0024]    [0024]FIG. 5 shows the circuit of a synchronous demodulator according to the invention with integrated filtering means,  
         [0025]    [0025]FIG. 6 shows the input signal and the signal downstream of the switches S 1  and S 2 ,  
         [0026]    [0026]FIG. 7 shows a detailed portion of the upper trace of FIG. 6, and  
         [0027]    [0027]FIG. 8 shows a circuit for generating the phase-shifted signals Phi 1  and Phi 2 . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0028]    In the known circuit, a peak value rectifier (illustrated in FIG. 3) is used to convert the AC voltage signal into a DC voltage. Said rectifier operates as follows: it will be assumed that there is a DC voltage of 2.5 V (center voltage Vm) at the input. The comparator V1 operates as a voltage follower; the voltage at the output is therefore also 2.5 V. This is achieved in that C 1  charges slowly via R 1 . As long as the voltage at the output is lower than the input voltage, the output transistor of the comparator V1 remains switched off. If the output voltage exceeds the input voltage, the transistor switches on and discharges C 1  via R 2  until the output voltage is below the input voltage again. The transistor then switches off again and the output voltage rises slowly again, driven by the charge current of R 1 .  
         [0029]    Oscillation occurs about Vout=Vin. The important factor here is that the time constants for the charging and discharging of the capacitor are very different:  
         τcharge= R   1   *C   1 , τdischarge= R   2   *C   1   
         [0030]    In a real circuit, the ratio τcharge/τdischarge of approximately 100/1 is selected, which results in a measuring error of 1%. If, for example, a square-wave signal with 500 mVss amplitude and with a DC voltage of Vm (2.5 V) superimposed on it is applied to the input, of the output will very quickly follow the lower peak value of the input signal (negative half wave) and rise only slowly again at the upper peak value. In the method of operation, a DC voltage which corresponds to the lower peak value of the input (AC+DC) voltage is thus produced at the output, see FIG. 4.  
         [0031]    The rectifier converts the AC voltage signal (500 mVss)—upper curve in FIG. 4—into a DC voltage signal (−250 mV)—lower curve. The zero point is at Vm=+2.5 V. The output signal is therefore on average  
         +2.50  V− 0.25  V=+ 2.25  V.    
         [0032]    The filter time constant has been greatly reduced in order to clarify the method of operation. The output signal therefore shows increased ripple in comparison to the typical application. This results in a simple, cost-effective design which uses standard components and fulfils the original precision requirements.  
         [0033]    However, this circuit gives rise to a falsification of the output value when there is a pulse tilt of the square-wave signal (for example owing to excessively small coupling capacitors or effects of the probe control loop) and it has a high degree of sensitivity to EMC interference pulses, due to the rapid response of the rectifier.  
         [0034]    According to the invention, the peak value rectifier is replaced by a synchronous demodulator with integrated filtering means. As the phase and frequency of the measurement signal are known, it is possible to perform rectification controlled by the oscillator signal.  
         [0035]    [0035]FIG. 5 shows the circuit of a synchronous demodulator according to the invention with integrated filtering means.  
         [0036]    The input of the circuit is connected to the output of the amplifier shown in FIG. 2. The inputs of the switches S 1 , S 2  are connected to the input of the switches. The output of S 1  is connected to a terminal of the capacitor C 10  and to the noninverting input of the amplifier AMP 1 . The other terminal of C 10  is connected to the DC voltage source Vm (2.5 V) shown in FIG. 2. The inverting input of AMP 1  is connected to its output.  
         [0037]    The output of S 2  is connected to a terminal of the capacitor C 11  and to the noninverting input of the amplifier AMP 2 . The other terminal of C 11  is connected to Vm. The inverting input of AMP 2  is connected to its output.  
         [0038]    The resistor R 12  is connected on the one hand to the output of AMP 1  and on the other hand to the noninverting input of AMP 3  and R 14 . The other terminal of R 14  is connected to R 15  and R 16 . The other terminal of R 15  is connected to 2.5 V, and that of R 16  to ground. R 13  is connected on the one hand to the output of AMP 2 , and on the other hand to the inverting input of AMP 3  and R 17 . R 17  is also connected to the output of AMP 3  where the output of the circuit is located.  
         [0039]    S 1 , R 10  and C 10  constitute a sample and hold circuit, as do S 2 , R 11  and C 11 . Phi 1  is the control signal of the switch S 1 , it corresponds for example to the signal of the oscillator shown in FIG. 2. S 1  is closed as long as the oscillator signal is 5 V, and open if the oscillator signal is 0 V.  
         [0040]    In this way, the capacitor C 10  is connected to the input via R 11  during the positive phase of the oscillator signal. Said capacitor will consequently slowly charge to the positive value of the input signal—in accordance with the time constant τ=R 10 *C 10 . Averaging to the positive signal value is carried out by synchronizing the switch activation and input signal. C 10  is not connected to ground but rather to Vm=2.5 V. As a result, the DC voltage present at the capacitor C 10  is reduced, which reduces the leakage current of the capacitor.  
         [0041]    The downstream amplifier AMP 1  has a gain 1 and is used for the high impedance decoupling of C 10  in order to avoid discharging in the hold phase (S 1  open). At the output of AMP 1  a DC voltage is produced which corresponds to the DC voltage Vm=+2.5 V and the positive peak value of the input signal. Vout (AMP 1 )=0.025 V+2.5 V=+2.525 V.  
         [0042]    The second sample&amp;hold circuit (S 2 , R 11 , C 11 ) is used to measure the negative signal value. The control signal Phi 2  is therefore inverted with respect to S 1 .  
         [0043]    The rest of the behavior corresponds otherwise to the first sample&amp;hold circuit, the voltage −0.025 V+2.5 V=2.475 V then being produced at the output of AMP 2 .  
         [0044]    The amplifier AMP 3  forms a differential amplifier together with the resistors R 12 , R 13 , R 14 , R 15 , R 16 , R 17 ). R 12  and R 13  have the same resistance value. The resistance of the series connection of R 14  with the parallel connection of R 15  and R 16  corresponds here to that of R 17 . The gain factor is determined by means of the ratio of R 17  and R 13  (Vu=R 17 /R 13 ). A further voltage (+2.5 V) is fed to the differential amplifier AMP 3  via R 15 . Given an appropriate selection of R 14 , R 15  and R 16 , a specific output voltage can thus be defined when there is no input voltage. This offset is necessary, like the DC voltage Vm=+2.5 V, for systems with no negative supply voltage as it is then impossible for the output of the amplifier AMP 3  to reach 0 V. Operation of the circuit in a 0/5 V power system is made possible only by Vm and the offset.  
         [0045]    The differential amplifier which is produced in this way then converts the difference between the output voltages of AMP 1  and Amp 2  into an output signal, the DC voltage (2.5 V) which is common to the input signals being suppressed and the difference being amplified by the value of the gain Vu.  
         [0046]    A rectified representation of the input signal which is amplified by Vu and which is still shifted by the offset is produced at the output of AMP 3 . This voltage can then be fed, for example, to the A/D converter of a microcontroller for further digital processing.  
         [0047]    In order to increase the precision of the synchronous rectifier further, it is possible to change the switch-on times of S 1  and S 2  as a function of the shape of the curve of the input signal.  
         [0048]    If the input signal has, for example, an exponential pulse tilt, it is appropriate to measure only the rear part of the positive or negative amplitude. To do this, a further circuit is necessary which generates further signals with a changed phase angle and pulse width (modified Phi 1  and Phi 2 ) from the oscillator signal. Phi 1  will in this case no longer be assumed to be 0% to 50% of the oscillator signal of 5 V but rather only 25% to 50% of said signal. Phi 2  in this case will no longer be assumed to be 50% to 100% but rather only 75% to 100%.  
         [0049]    Correspondingly, only the range of 25% to 50% of the positive amplitude value of the input signal will now be sampled in the first sample&amp;hold circuit, and the range of 75% to 100% of the negative amplitude value will be sampled.  
         [0050]    [0050]FIG. 6 shows the input signal and the signal downstream of the switches S 1  and S 2 .  
         [0051]    The upper trace (moved upward for better visibility) shows the signal at the output of S 1 . As long as S 1  is closed, it follows the curve profile of the input signal (e-function), and when S 1  is open the voltage is visible at C 10  (straight line).  
         [0052]    The central trace represents a—real—input signal as formed by the complex internal resistance of the linear lambda probe.  
         [0053]    The lower trace (moved downward for better visibility) shows the signal at the output of S 2 .  
         [0054]    [0054]FIG. 7 shows a detailed portion of the upper trace of FIG. 6:  
         [0055]    unbroken line: peak value of the signal,  
         [0056]    vertical center of diagram: voltage at C 10 ,  
         [0057]    horizontal center of diagram: 25% point of the signal,  
         [0058]    dashed line: new averaging interval.  
         [0059]    The measurement error of the synchronous demodulator is 14 mV or 7% referred to the signal amplitude of 200 mVss used here. The reason for this is the extremely high fluctuation of the positive amplitude value over which averaging is carried out (exponential function).  
         [0060]    When a sampling interval of 25% to 50% is used, this fluctuation is reduced to approximately 7 mV (difference between unbroken and dashed lines in FIG. 7) so that after the averaging a residual error of &lt;3 mV is obtained, which corresponds to 1.5%.  
         [0061]    [0061]FIG. 8 shows a circuit for generating the phase-shifted signals Phi 1  and Phi 2 , and of the 3 kHz signal.  
         [0062]    The output of the oscillator is connected to the clock input CLK of the flip-flop IC 1   a  and to the input  3  of the NOR gate IC 2 A, and to the input  6  of the NOR gate IC 2 B. The output Q of the flip-flip IC 1   a  is connected to the input  2  of the gate IC 2 A. The output Q transverse of the flip-flip IC 1   a  is connected to its data input D and to the input  5  of the gate IC 2   b;  it constitutes the 3 kHz signal. The output of the gate IC 2 A constitutes the signal Phi 1 , and the output of the gate IC 2 B constitutes the signal Phi 2 .  
         [0063]    Owing to the feeding back of the output Q transverse, the flip-flop IC 1 A operates on the data input as a frequency divider (:2). The 3 kHz signal, which is conducted to the probe impedance via Rv and Cv (FIG. 2), is correspondingly produced at the output Q transverse. IC 1  switches with the rising edge of the  6  kHz oscillator. The oscillator signal is fed, together with the output signal Q transverse (of IC 1 A), to the inputs of the gate IC 2 B. If both input signals are 0 V, its output is 5 V. Referred to the 3 kHz signal, this is the case from 75% to 100% of the clock phase, as required above for Phi 2 .  
         [0064]    The oscillator signal is then also fed, together with the output signal Q (of IC 1 A), to the inputs of the gate IC 2 A. If both input signals are 0 V, its output signal is 5 V. Referred to the 3 kHz signal, this is the case from 25% to 50% of the clock phase, as required above for Phi 1 .