Abstract:
A process creating a crown shaped storage node electrode, for high density, DRAM designs, has been developed. The process features the formation of an hemispherical grain, (HSG), silicon layer, only on the outside walls of the amorphous silicon vertical shapes, of the crown shaped storage node electrode. The HSG silicon layer is formed from HSG silicon seeds, and from undoped, or lightly doped amorphous silicon layers, or a combination of both. The amorphous silicon vertical shapes are comprised of an undoped, or lightly doped amorphous silicon layer, placed as the outside layer, while a heavily doped amorphous silicon layer is used for the inside layer. This configuration therefore only allows the formation of the HSG silicon layer on the outside walls of the amorphous silicon vertical shape, and therefore results in a crown shaped storage node electrode, with a minimum space between vertical shapes maintained, and not compromised by encroaching HSG silicon layers, that would have been formed on the inside surfaces of the vertical shapes, if a heavily doped amorphous silicon layer were not present.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method used to fabricate high density, semiconductor, DRAM cells, with stacked capacitor structures, and more specifically to a fabrication process used to increase the surface area of a storage node electrode, used in the stacked capacitor structure. 
     2. Description of the Prior Art 
     Device performance and cost reductions are the major objectives of the semiconductor industry. These objectives have been in part realized by the ability of the semiconductor industry to produce chips with sub-micron features, or micro-miniaturization. Smaller features allow the reduction in performance degrading capacitances and resistances to be realized. In addition smaller features result in a smaller chip, however still possessing the same level of integration obtained for semiconductor chips fabricated with larger features. This allows a greater number of the denser, smaller chips to be obtained from a specific size starting substrate, thus resulting in a lower manufacturing cost for an individual chip. 
     The use of smaller features, when used for the fabrication of dynamic random access memory, (DRAM), devices, in which the capacitor of the DRAM device is a stacked capacitor, (STC), structure, presents difficulties when attempting to increase STC capacitance. A DRAM cell is usually comprised of the STC structure, overlying a transfer gate transistor, and connected to the source of a source/drain of the transfer gate transistor. However the decreasing size of the transfer gate transistor, limits the dimensions of the STC structure. To increase the capacitance of the STC structure, comprised of two electrodes, separated by a dielectric layer, either the thickness of the dielectric layer has to be decreased, or the area of the capacitor has to be increased. The reduction in dielectric thickness is limited by increasing reliability and yield risks, encountered with ultra thin dielectric layers. In addition the area of the STC structure is limited by the area of the underlying transfer gate transistor dimensions. The advancement of the DRAM technology to densities of 256 million cells per chip, or greater, has resulted in a specific cell in which a smaller transfer gate transistor is being used, resulting in less of an overlying area for placement of overlying STC structures. 
     Two methods that can be used to increase STC capacitance, while still decreasing the lateral dimension of the capacitor, are the use of rough, or hemispherical grain (HSG), silicon layers, and the use of crown shaped STC structures. First, referring to the crown shaped STC structures, the creation of a polysilicon, or amorphous silicon, storage node electrode structure, comprised of both vertical and horizontal silicon features, results in a greater electrode surface area then would have been achieved with counterparts fabricated without vertical features. Secondly the use of an HSG silicon layer, comprised of convex and concave features, and used for the top layer of the storage node electrode structure, again results in a greater degree of surface area then counterparts fabricated with smooth silicon layers. Therefore the combination of a crown shaped STC structure, comprised with a top layer of HSG silicon, residing on the crown shaped storage node structure, is an attractive option for high density DRAM devices. However if a HSG silicon layer is used with a crown shaped storage node electrode, the space between the vertical features, of the crown shaped structure, has to be increased to accept the growth of the HSG silicon layer, on the inside walls of the vertical features. If this space were kept at a minimum, HSG silicon, residing on neighboring inside walls of the vertical features, may intersect, leaving little, or no space remaining for the capacitor dielectric layer, thus negating the advantage of increased surface area using the combination of HSG silicon and the crown shaped structures. If the space between vertical features, of the crown shaped structure, were increased to accept the additional growth of the HSG silicon layer, on the inside walls of the crown shaped storage node electrode, the final dimension of the DRAM capacitor structure may violate design groundrules. 
     This invention will describe a novel process for the fabrication of a crown shaped STC structure, however incorporating a selective growth of an HSG silicon layer, to occur only on the outside walls of the vertical features of the crown shaped STC structure. The selective growth of the HSG silicon layer, only on the outside walls of the vertical features, of the crown shaped STC, thus allows the minimum space between vertical features to still be maintained, and thus also allows a minimum lateral dimension for the DRAM capacitor structure, to be achieved. Prior art, such as Tseng, in U.S. Pat. No. 5,716,883, describes a fabrication method for a crown shaped STC structure, while Lou, et al, in U.S. Pat. No. 5,597,754, describe a method for forming an HSG silicon layer, for a DRAM storage node structure. However none of the prior art describe the process used in the present invention, in which selective growth of an HSG silicon layer, is achieved only on the outside walls. of vertical features, of a crown shaped STC structure. 
     SUMMARY OF THE INVENTION 
     It is an object of this invention to create a DRAM capacitor structure, in which the surface area the storage node electrode, of the DRAM capacitor structure is increased, without increasing the lateral dimension of the DRAM capacitor structure. 
     It is another object of this invention to use a crown shaped stacked capacitor structure, (STC), for DRAM devices, via the fabrication of a crown shaped storage node electrode, in which the crown shaped storage node electrode is comprised of both amorphous silicon horizontal and amorphous silicon vertical features. 
     It is yet another object of this invention to form the amorphous silicon vertical features, of the crown shaped storage node electrode, using a composite amorphous silicon layer, in which an undoped, or lightly doped silicon layer is used for the outside walls of the amorphous silicon vertical shapes, while a heavily doped amorphous silicon layer is used for the inside walls of the amorphous silicon vertical features. 
     It is still yet another object of this invention to selectively grow an HSG silicon layer, only on undoped, or lightly doped silicon layer, or only on the outside walls, of the amorphous silicon vertical features, of the crown shaped storage node electrode. 
     In accordance with the present invention a method for fabricating a DRAM device, with increased capacitance realized via the use of crown shaped storage node electrode, comprised using an HSG silicon layer on the outside walls of the amorphous silicon vertical features of the crown shaped storage node electrode, has been developed. A transfer gate transistor comprised of: a thin gate insulator; a polysilicon gate structure; a lightly doped source/drain region; insulator spacers on the sidewalls of the polysilicon gate structure; and a heavily doped source/drain regions; are formed on a semiconductor substrate. A composite insulator layer is deposited on the transfer gate transistor region, followed by the creation of a storage node contact hole, in the composite insulator layer, exposing a source region, of the transfer gate transistor. A doped polysilicon plug is formed in the storage node contact hole, contacting the source region of the transfer gate transistor. Two insulator shapes are formed on the top surface of the underlying composite insulator layer, with the top surface of the doped polysilicon plug, exposed between insulator shapes. A series of amorphous silicon layers are next deposited, coating the walls of the insulator shapes, and in the space between insulator shapes. The series of amorphous silicon layers consist of an underlying, first undoped amorphous silicon layer, a lightly doped silicon layer, a second undoped amorphous silicon layer, and an overlying, heavily doped amorphous silicon layer. A chemical mechanical polishing procedure is used to remove the series of amorphous silicon layers, from the top surface of the two insulator shapes, exposing the top surface of the insulator shapes. Selective removal of the two insulator shapes, results in a crown shaped storage node shape, comprised of two vertical features of amorphous silicon layers, formerly on the sides of the insulator spaces, connected to a horizontal feature of amorphous silicon layers, with the horizontal feature of amorphous silicon layers, overlying and contacting the doped polysilicon plug, in the storage node contact hole. The outside walls, of the amorphous silicon vertical features, expose the first undoped amorphous silicon layer, while the inside walls, of the amorphous silicon vertical features, expose the heavily doped amorphous silicon layer. Hemispherical grain, (HSG), silicon seeds are next formed on all surfaces of the crown shaped storage node shape, followed by an anneal procedure that results in the formation of an HSG silicon layer, only in regions in which the HSG silicon seeds overlaid the first undoped, or lightly doped amorphous silicon layer, or only on the outside walls, of the amorphous silicon vertical features. A second anneal is then used to crystallize all the amorphous layers, to increase the dopant level in the HSG silicon layer, due to the dopant diffusion from the heavily doped to the undoped/lightly doped layer, resulting in a crown shaped storage node electrode, comprised of doped silicon vertical features, and doped silicon horizontal features, with a doped HSG silicon layer located only on the outside walls of the vertical features, and with the doped silicon horizontal feature contacting the doped polysilicon plug. A capacitor dielectric layer is formed on the surface of the crown shaped storage node electrode, followed by the creation of an upper polysilicon electrode, completing the formation of a crown shaped, stacked capacitor structure. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The object and other advantages of this invention are best explained in the preferred embodiment with reference to the attached drawings that include: 
     FIGS. 1-11, which schematically, in cross-sectional style, shows the key fabrication stages used in the creation of a crown shaped storage node electrode, used as part of a DRAM, stacked capacitor structure, and with a HSG silicon layer located on the outside walls, of the amorphous silicon vertical features, of the crown shaped storage node electrode. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The method of forming a crown shaped storage node electrode, used as the bottom electrode of DRAM capacitor structure, and with an HSG silicon layer selectively formed on the outside walls, of the vertical features of a crown shaped storage node shape, will now be described. The transfer gate transistor, used for the DRAM device, of this invention, will be an N channel device. However this invention, using an HSG silicon layer on selective regions of a crown shaped storage node shape, used to increase the surface area of the DRAM capacitor, can also be applied to P channel, transfer gate transistor. In addition doped, and undoped, polysilicon layers, can be used in place of the doped, and undoped, amorphous silicon layers, for creation of the crown shaped storage node electrode. 
     Referring to FIG. 1, a P type, semiconductor substrate 1, with a &lt;100&gt;, single crystalline orientation, is used. Field oxide, (FOX), regions 2, are used for purposes of isolation. Briefly the FOX regions 2, are formed via thermal oxidation, in an oxygen-steam ambient, at a temperature between about 750 to 1050° C., to a thickness between about 2000 to 5000 Angstroms. A patterned oxidation resistant mask of silicon nitride-silicon oxide is used to prevent FOX regions 2, from growing on areas of semiconductor substrate 1, to be used for subsequent device regions. After the growth of the FOX regions 2, the oxidation resistant mask is removed via use of a hot phosphoric acid solution for the overlying, silicon nitride layer, and a buffered hydrofluoric acid solution for the underlying silicon oxide layer. If desired, FOX regions 2, can be replaced by insulator filled shallow trenches. This can be accomplished via forming a trench, between about 2000 to 5000 Angstroms in depth, in semiconductor substrate 1, using anisotropic reactive ion etching, (RIE), procedure, using Cl 2  as an etchant. A silicon oxide layer, obtained using a low pressure chemical vapor deposition, (LPCVD), or a plasma enhanced chemical vapor deposition, (PECVD), procedure, is used to completely fill the shallow trenches. Unwanted silicon oxide is removed via a anisotropic RIE procedure, or via a chemical mechanical polishing, (CMP), procedure. 
     After a series of wet cleans, a gate insulator layer 3, comprised of silicon dioxide, is thermally grown in an oxygen-steam ambient, at a temperature between about 750 to 1050° C., to a thickness between about 40 to 200 Angstroms. A first polysilicon layer 4, is next deposited using LPCVD procedures, at a temperature between about 500 to 700° C., to a thickness between about 500 to 4000 Angstroms. The polysilicon layer can either be grown intrinsically and doped via ion implantation of arsenic or phosphorous, or polysilicon layer 4, can be in situ doped during deposition via the incorporation of either arsine or phosphine to the silane, or disilane ambient. If lower word line, or gate resistance is desired, polysilicon layer 4, can be replaced by a polycide layer, comprised of a metal silicide layer, such as tungsten silicide or titanium silicide, residing on an underlying doped polysilicon layer. A silicon oxide layer 5, used as a cap insulator layer, is next grown via LPCVD or PECVD procedures, to a thickness between about 600 to 2000 Angstroms. Conventional photolithographic and reactive ion etching, (RIE), procedures, using CHF 3  as an etchant for silicon oxide layer 5, and using Cl 2  as an etchant for polysilicon or polycide layer 4, are used to create gate structure 6, with overlying cap insulator layer 5, shown schematically in FIG. 1. Photoresist removal is accomplished via plasma oxygen ashing and careful wet cleans. 
     A lightly doped source/drain region 7, is next formed via ion implantation of phosphorous, at an energy between about 5 to 60 KeV, at a dose between about 1E13 to 1E15 atoms/cm 2 , Another silicon oxide layer is then deposited, using either LPCVD or PECVD procedures, at a temperature between about 400 to 850° C., to a thickness between about 1500 to 4000 Angstroms, followed by an anisotropic RIE procedure, using CHF 3  as an etchant, creating insulator spacers 8, located on the sides of gate structure 6. A heavily doped source/drain region 9, is then formed via ion implantation of arsenic, at an energy between about 30 to 100 KeV, at a dose between about 1E14 to 5E16 atoms/cm 2 . The result of these procedures are again schematically shown in FIG. 1. 
     An insulator layer 10, of either silicon oxide, or boro-phosphosilicate glass, (BPSG), is next deposited via LPCVD or PECVD procedures, to a thickness between about 1000 to 5000 Angstroms. A chemical mechanical polishing, (CMP), procedure is next used to planarize insulator layer 10. If a BPSG layer is used, a reflow procedure, performed at a temperature between about 700 to 1000° C., is employed to create a smoother the top surface topography for the BPSG layer. A silicon nitride layer 11, is next deposited, via LPCVD or PECVD procedures, to a thickness between about 50 to 1000 Angstroms. Conventional photolithographic and RIE procedures, using CF 4  as an etchant for silicon nitride layer 11, and using CHF 3  as an etchant for silicon oxide layer 10, are used to open storage node contact hole 12, in the composite insulator layer, exposing the top surface of heavily doped source/drain region 9. This is schematically shown in FIG. 2. Removal of the photoresist shape, used as an etch mask for the creation of storage node contact hole 12, is performed via use of plasma oxygen ashing and careful wet cleans. 
     A polysilicon layer is next deposited, using LPCVD procedures, at a thickness between about 1000 to 6000 Angstroms. The polysilicon layer is in situ doped, during deposition, via the addition of arsine, or phosphine, to a silane, or disilane ambient, resulting in a bulk concentration for the polysilicon layer, between about 1E19 to 2E20 atoms/cm 3 . The formation of doped polysilicon plug 13, in storage node contact hole 12, shown schematically in FIG. 3, is accomplished via removal of unwanted polysilicon, from the top surface of silicon nitride layer 11, using either an anisotropic RIE procedure, using Cl 2  as an etchant, or using a CMP procedure. 
     FIG. 4, schematically shows the formation of two insulator shapes, that will be used to form a subsequent crown shaped storage node electrode. A thick silicon oxide layer is deposited using LPCVD or PECVD procedures, to a thickness between about 4000 to 20000 Angstroms. Photoresist shapes 15, are next formed on the top surface of the thick silicon oxide layer, and used as a mask to allow an anisotropic RIE procedure, using CHF 3  as an etchant, to pattern the thick silicon oxide layer, creating thick silicon oxide shapes 14, schematically shown in FIG. 4. The height, or thickness, of thick silicon oxide shapes 14, will subsequently determine the height of the amorphous silicon vertical features, used as a component of a crown shaped storage node electrode. 
     After removal of photoresist shapes 15, via plasma oxygen ashing and careful wet cleans, a series of amorphous silicon layers are deposited, and shown schematically in FIG. 5. A first, undoped amorphous silicon layer 16a, is deposited using LPCVD procedures, at a temperature below 550° C., to a thickness less than 200 Angstroms, using silane, or disilane as a source. Next a lightly doped amorphous silicon layer 17a, is in situ deposited in the same LPCVD furnace used for the first, undoped amorphous silicon layer 16a, Lightly doped amorphous silicon layer 17a, is deposited at a temperature below 550° C., to a thickness less than 400 Angstroms, and in situ doped, during deposition, via the addition of phosphine to a silane, or to a disilane, ambient, resulting in a bulk concentration, for lightly doped amorphous silicon layer 17a, between about 1E19 to 4E20 atoms/cm 3 . A second, undoped amorphous silicon layer 18a, is then deposited, again in situ in the LPCVD furnace, at a temperature below 550° C., to a thickness less than 200 Angstroms, using a silane or a disilane source. Finally heavily doped amorphous silicon layer 19a, is deposited in situ in the LPCVD furnace, at a temperature below 550° C., to a thickness between about 100 to 1000 Angstroms, and doped in situ, during deposition, via the addition of phosphine to a silane, or to a disilane ambient, resulting in a bulk concentration, for heavily doped amorphous silicon layer 19a, greater than 4E20 atoms/cm 3 . 
     A chemical mechanical polishing, (CMP), procedure is then employed, removing the composite, amorphous silicon layers, residing on the top surface of thick silicon oxide shapes 14, resulting in the creation of discontinuous layers of: first undoped amorphous silicon layer 16b; lightly doped amorphous silicon layer 17b; second undoped amorphous silicon layer 18b; and heavily doped amorphous silicon layer 19b. This is schematically represented in FIG. 6. The CMP procedure exposes the top surface of thick silicon oxide shapes 14. An etch procedure, using a buffered hydrofluoric acid solution, or using hydrofluoric gas with/without water vapor, is next used to selectively remove thick silicon oxide shapes 14, resulting in crown shape storage node shape 20a, comprised of two amorphous silicon vertical features, connected by an amorphous silicon horizontal feature. The horizontal feature, of crown shaped storage node shape 20a, overlays and contacts, doped polysilicon plug 13, located in storage node contact hole 12. This is schematically shown in FIG. 7. Of importance is the outer layers of crown shaped storage node shape 20a, are the first undoped amorphous silicon layers 16b, while the inner layers of crown shaped storage node shape 20a, are heavily doped amorphous silicon layers 19b, This configuration will be critical when subsequent, selective formation of an HSG silicon, only on the surface of first undoped amorphous silicon layers 16b, is attempted. Also shown in FIG. 7, are portions of additional crown shaped storage shapes 20b, and 20c, used with other underlying transfer gate transistors. For purposes of clarity, crown shaped storage node shape 20b, and 20c, will not be included in the final drawings. 
     FIG. 8, schematically shows the result of growing HSG silicon seeds 21, on exposed surfaces of crown shaped storage node shape 20a, This is accomplished via LPCVD, or UHVCVD, (ultra high vacuum CVD), deposition of the HSG silicon seeds 21, at a temperature between about 550 to 800°, at a pressure below 1.0 torr, for a time between about 10 sec to 120 min., and using a silane, or a disilane flow concentration below 1.0OE-3 moles/m 3 . A critical first anneal cycle is next performed, resulting in the formation of HSG silicon layer 22a, in regions in which HSG silicon seeds resided on first undoped amorphous silicon layer 16b, This selective growth, shown schematically in FIG. 9, did not occur in regions in which HSG silicon seeds overlaid heavily doped amorphous silicon layer 19b, The first anneal cycle, performed at a temperature between about 550 to 800° C., at a pressure below 1.0 torr, for a time between about 0 to 120 min, in a nitrogen ambient, forms HSG silicon layer 22a, via consumption of HSG silicon seeds 21, and of consumption of undoped/lightly doped/undoped amorphous silicon layers 16b, 17b and 18b. The inability to form an HSG silicon layer, using HSG silicon seeds 21, on heavily doped amorphous silicon layer 19b, resulted in the space between the amorphous silicon vertical features, of the crown shaped storage node shape, remaining at the designed dimension. If an HSG silicon layer were formed on the inside walls of the vertical features, of the crown shaped storage node shape, the space between the vertical features may have disappeared. The HSG silicon seeds 21, on heavily doped amorphous silicon layer 19b, were consumed by heavily doped amorphous silicon layer 22a, during the first anneal cycle. 
     A second anneal cycle, performed at a temperature between about 800 to 850° C., for a time between about 20 to 40 min., in a nitrogen ambient, allows the HSG silicon layer 22a, to be doped via diffusion from heavily doped amorphous silicon layer 19b, creating highly doped HSG silicon layer 22b, schematically shown in FIG. 10. The second anneal procedure also induces the crystallization of all amorphous layers, resulting in the stabilization of the HSG layer for the subsequent capacitor dielectric layer deposition. 
     A capacitor dielectric layer 23, such as ONO, (Oxidized--silicon Nitride--silicon Oxide), is next formed on crown shaped storage node electrode 20b, The ONO layer is formed by initially growing a silicon dioxide layer, between about 10 to 50 Angstroms, followed by the deposition of a silicon nitride layer, between about 10 to 60 Angstroms. Subsequent thermal oxidation of the silicon nitride layer results in the formation of a silicon oxynitride layer on silicon oxide, at a silicon oxide equivalent thickness of between about 40 to 80 Angstroms. Finally another layer of polysilicon is deposited, via LPCVD procedures, to a thickness between about 1000 to 2000 Angstroms. Doping of this polysilicon layer is accomplished using the situ doping, deposition procedure, via the addition of phosphine to a silane, or disilane ambient. Photolithographic and RIE procedures, using Cl 2  as an etchant, are next employed to create polysilicon upper electrode, or plate electrode 24, shown schematically in FIG. 11. Photoresist is again removed via plasma oxygen ashing and careful wet cleans. 
     While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of this invention.