Abstract:
A patterned gold bump structure for a semiconductor chip comprises at least a patterned gold bump disposed on an insulating layer of a semiconductor chip, wherein the gold bump is used as a circuit component or a passing line. In some embodiments, the circuit component is a capacitor, a resistor, or an inductor.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a structure of gold bump for a semiconductor chip, and more particularly, to a patterned gold bump structure applied to a semiconductor chip.  
       BACKGROUND OF THE INVENTION  
       [0002]     A conventional semiconductor chip  1  comprises a chip  25 , an insulating layer  23 , a plurality of aluminum (Al) pads  21 , and a plurality of gold bumps  10  as shown in  FIG. 1 . The gold bumps  10  are formed respectively corresponding to the Al pads  21 . Each gold bump  10  is isolated from other gold bumps  10 . A novel structure of gold bumps  10  is thus disclosed by the applicant and could be served as a portion of the circuit design.  
       SUMMARY OF THE INVENTION  
       [0003]     It is a primary object of the invention to provide a patterned gold bump structure, which can be used as a part of the circuit.  
         [0004]     In accordance with the objects of the invention, a patterned gold bump structure for a semiconductor chip is provided. The structure comprises at least a patterned gold bump disposed on an insulating layer of a semiconductor chip, wherein the gold bump is used as a circuit component or a passing line. In some embodiments, the circuit component is a capacitor, a resistor, or an inductor. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]     The foregoing aspects, as well as many of the attendant advantages and features of this invention will become more apparent by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:  
         [0006]      FIG. 1  shows a conventional gold bump structure disposed on a semiconductor chip;  
         [0007]      FIG. 2  illustrates a patterned gold bump structure according to the first embodiment of the invention;  
         [0008]      FIG. 3  illustrates a patterned gold bump structure according to the second embodiment of the invention;  
         [0009]      FIG. 4  illustrates a patterned gold bump structure according to the third embodiment of the invention; and  
         [0010]      FIG. 5  illustrates a patterned gold bump structure according to the fourth embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0011]      FIG. 2  illustrates a patterned gold bump structure according to the first embodiment of the invention. The patterned gold bump structure is applied to a semiconductor chip  2 . The semiconductor chip  2  includes a chip  25 , an insulating layer  23  and a plurality of Al pads  21 . Optionally, traditional gold bumps  10  are disposed on the semiconductor chip  2 . In this embodiment, a plurality of patterned gold bumps  20  function as passing lines. The patterned gold bumps  20  are connected with one another as illustrated in shaded area of  FIG. 2 . Since the patterned gold bumps  20  are conductive, they can serve as passing lines of signals. Furthermore, the patterned gold bumps  20  may be formed corresponding to the Al pads  21  on the semiconductor chip  2 .  
         [0012]     The patterned gold bumps  20  are characteristic of low resistance, and therefore RC delays of the passing lines in critical paths, which are made from the patterned gold bumps  20 , are reduced. Accordingly, the patterned gold bumps  20  can be applied to the passing lines of high-frequency or care-timing signals, so as to enhance the performance of the integrated circuit (IC).  
         [0013]     Because source driver IC has large volume and a rectangular form, IR drop of power passing lines in such IC is usually high. As a result, the pitch of the passing line is widened for low IR drop, and the area of source driver IC is occupied. Fortunately, the patterned gold bumps  20  of the invention can be used as portion of the power passing lines. The effective area of source driver IC is thus increased. Also, IR drop is decreased due to low resistance of the patterned gold bumps  20 , and the performance of source driver IC is improved.  
         [0014]     The conventional method to fabricate power passing lines for electrostatic discharge (ESD) includes surrounding the outer area of source driver IC that is in the form of rectangle, such that ESD is not high. Hence, additional areas are deployed for thunder to increase ESD. Since the patterned gold bumps  20  can further serve as power passing lines for ESD, the space of source driver IC is saved and ESD is also increased. In the trend to develop IC with high pin counts, the aforementioned advantages are more apparent for such long IC because the patterned gold bumps  20  occupy less space and aid in increasing ESD.  
         [0015]     Sometimes, more than one passing lines of source driver IC are required by the whole system. The common way to meet the requirement is to deploy the lines passing through the inner of IC, which wastes on the area thereof. Furthermore, the effective area of IC is decreased when passing lines are wider for low IR drop or RC delay. The area of IC can be utilized more efficiently by substituting the patterned gold bumps  20  for the traditional passing lines. Signal quality of the passing lines made from the patterned gold bumps  20  is also better.  
         [0016]     Additionally, the patterned gold bumps  20  may serve as the auxiliaries of film drawing. For example, the patterned gold bump  20  is applicable when a pad of Function Pin A is positioned at location Y for connection of film but is desired to be positioned at location X for better performance of IC. Under the circumstances, the pad of Function Pin A is deployed at location X, while the passing line of the patterned gold bump  20  is pulled to location Y for connection of film.  
         [0017]     The patterned gold bumps  20  of  FIG. 2  further provide various designs for the inner circuit of the chip  25 . The inner circuit may be modified its function, for example, by connecting the patterned gold bumps  20  to high voltage pins or by shorting some of the patterned gold bumps  20 .  
         [0018]      FIG. 3  illustrates a patterned gold bump structure according to the second embodiment of the invention. The semiconductor chip  2  includes a chip  25 , an insulating layer  23  and a plurality of Al pads  21 . Optionally, traditional gold bumps  10  are disposed on the semiconductor chip  2 . In this embodiment, a pair of patterned gold bumps  20 A and  20 B are disposed in parallel to form a capacitor as shown in the shaded part of  FIG. 3 . Since the patterned gold bumps  20 A and  20 B are conductive, they can be used as a plate of the capacitor. For instance, a capacitor is composed of the patterned gold bumps  20 A,  20 B, and a dielectric layer disposed there-between. The pair of the patterned gold bumps  20 A and  20 B may be formed on an upper surface of the insulating layer  23 .  
         [0019]      FIG. 4  illustrates a patterned gold bump structure according to the third embodiment of the invention. The semiconductor chip  2  includes a chip  25 , an insulating layer  23  and a plurality of Al pads  21 . Optionally, traditional gold bumps  10  are disposed on the semiconductor chip  2 . In this embodiment, a plurality of patterned gold bumps  20  serve as resistors as shown in shadows of  FIG. 4 . The resistors are manufactured by, for example, forming the material of patterned gold bumps  20  containing resistant substances on the upper surface of the insulating layer  23 .  
         [0020]      FIG. 5  illustrates a patterned gold bump structure according to the fourth embodiment of the invention. The semiconductor chip  2  includes a chip  25 , an insulating layer  23  and a plurality of Al pads  21 . Optionally, traditional gold bumps  10  are disposed on the semiconductor chip  2 . In this embodiment, a plurality of patterned gold bumps  20  are used as inductors. Because the patterned gold bumps  20  are conductive and include zigzag geometrical patterns, they can serve as inductors.  
         [0021]     The aforementioned embodiments may be employed on the semiconductor chip  2  spontaneously. Therefore, those devices like capacitors, resistors or inductors are formed on the insulating layer  23  of the semiconductor chip  2 , and these devices are electrically connected with one another by means of the passing lines of the patterned gold bumps.  
         [0022]     The patterned gold bump structure of the present invention can be used as a portion of circuits, which is different and superior to prior arts.  
         [0023]     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, these are, of course, merely examples to help clarify the invention and are not intended to limit the invention. It will be understood by those skilled in the art that various changes, modifications, and alterations in form and details may be made therein without departing from the spirit and scope of the invention, as set forth in the following claims.