Abstract:
A correlated double sampling unit within a CMOS imager employs an image sensor having a plurality of photodetectors arranged in a series of rows and columns with a row addressing circuit, a column addressing circuit, a first sample and hold circuit allocated for each of the columns, a transfer circuit operatively connecting each of the columns to the first sample and hold circuit for each of the columns, and a plurality of second sample and hold circuits, each of the second sample and hold circuits being operatively connected to a subset of the first sample and hold circuits.

Description:
FIELD OF THE INVENTION 
     The present invention relates to CMOS imagers and, more particularly, to correlated double sampling circuits employed by CMOS imagers. 
     BACKGROUND OF THE INVENTION 
     Present solid-state image sensors are created from essentially three different technologies. Self-scanned diode array; charge injection device (CID) arrays; and charge-coupled device (CCD) arrays. Each of these three technologies will be produced by a semiconductor process that has inherent limitations which limit the achievement of higher integration. The art of solid state image sensors has evolved to the point where a CMOS process can be employed in the production of solid state image sensors. The use of CMOS technology allows higher integration resulting in both analog and digital circuits being integrated within the same silicon chip as the sensor array. Higher integration, additionally, allows for the achievement of higher resolution and higher speed. During normal use, hundreds of different signals, representing individual channels are simultaneously present at the output of the sensor array. These signals need to be processed and then converted into a digital signal. However, process variations (which exist in any of the processes used to manufacture these devices and cannot be eliminated) create offsets between the various circuits that are dedicated to the individual columns generating what is referred to as “column pattern noise” or “fixed pattern noise”. 
     Imaging systems desiring high resolution and high speed, such as 10-bit resolution, 24 frame per second, need to have “fixed pattern noise” removed before analog to digital conversion can be performed for any large size image array. Prior art devices typically employ a double sampling circuit for each column within a sensor to remove fixed pattern noise. These prior art correlated double sampling circuits allocate a double sampling circuit for every column and as a result have disadvantages in terms of: higher power dissipation; slower speed; only a partial removal of fixed pattern noise; more silicon area needed to provide a double sampling for each column; a more complicated process involved to create the additional circuitry; and higher cost. 
     From the foregoing discussion, it should be apparent that there remains a need within the art for a method and apparatus that can be employed within a CMOS environment to perform CDS without requiring large amounts of silicon area and power. These and other problems are addressed by the present invention as discussed below. 
     SUMMARY OF THE INVENTION 
     The present invention pertains to a new Column Correlated Double Sampling (CDS) circuit that provides double sampling for each column by placing the first sampling circuit in the column itself and the second sampling circuit is shared between the various columns resulting in doubling sampling circuit that requires much less silicon space, is more economical to produce, requires less power dissipation, operates at higher speeds, improves the removal of fixed pattern noise, and requires less process steps to create than prior art devices. 
     The CDS circuit of the present invention is intended to satisfy various design parameters, including: very small size; a 70% increase in speed; lower power dissipation; and more importantly, a substantial reduction in fixed pattern noise compared to prior art devices. Except for the standard control clocks, including a reset clock, a signal clock and a column select clock, no other control clocks are required. These standard clocks are those typically required for any imager array application employing a semiconductor based imager and can be provided by a relatively simple digital control circuit. The CDS circuit as envisioned by the present invention can run at speeds as high as 30 million samples/second with power dissipation less than 13 mW (for 1200 column array). The present invention, potentially, removes up to 100% of the fixed pattern noise. 
     These and other features and advantages of the present invention are provided by a correlated double sampling unit comprising: an image sensor having a plurality of photodetectors arranged in a series of rows and columns; a row addressing circuit; a column addressing circuit; a first sample and hold circuit allocated for each of the columns; a transfer circuit operatively connecting each of the columns to the sample and hold circuit that is allocated to that column; and a plurality of second sample and hold circuits, each of the second sample and hold circuits being operatively connected to a subset of the first sample and hold circuits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram of an image sensor embodying the preferred embodiment of the invention. 
     FIG. 2 is a schematic diagram of the correlated double sampling unit of the present invention. 
     FIG. 3 is an illustration of the control clocks used by the present invention. 
     FIG. 4 is an illustration of the output waveforms as envisioned by the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 represents the preferred embodiment of the present invention, which is a CMOS based image sensor  5  on a signal silicon chip. The sensor  5  has an array of pixels  1  arranged in a plurality of rows and columns which can be individually selected by row select circuit  2  and column select circuit  3 . Each column has its pixels double sampled by correlated double sampling circuit  10  (CDS). Collectively, first sampling circuits  6  and second sampling circuits  7  comprise the correlated double sampling unit  10 . Columns have pixels initially sampled by a plurality of 1st sampling circuits  6  that are arranged such that is one 1st sampling circuit for each of the columns. After an initial sampling is provided by the 1st sampling circuits  6 , second sampling circuits  7  will perform a second sampling of each of the column outputs. 
     FIG. 2 is a schematic diagram for the double correlated double sampling circuit  10  that illustrates one of the first clamping circuit  6  for each of the odd and even columns. The odd column first clamping circuit  11  and even column first clamping circuit  12 , are identical and operate, respectively, with odd column second clamping circuit  21  and even column second clamping circuit  22 . FIG. 2 shows single odd and even first clamping circuits  11 ,  12 , for purpose of illustration only. First clamping circuits  6  are provided such there is one first clamping circuit for each column. The preferred embodiment employs only a single second clamping circuit  21  for the odd columns and a single second clamping circuit  22  for the even columns. However, it should be noted that numerous combinations of the number of second clamping circuits  7  with first clamping circuit  6  can be employed and that FIG. 2 only illustrates the preferred embodiment. The reasons for the selection of second clamping circuit  21 ,  22  for the odd and even columns, respectively, will be discussed further below. 
     Referring now to FIG. 1 in conjunction with FIG. 2, signals from image sensor  1  are provided to the CDS  10  once row select circuit  2  identifies a row of columns that are addressed. An entire addressed row of pixels have their stored photo-generated charges transferred into first sampling circuits  6  where their respective charges can be addressed on a column by column basis. Each column has a first clamping circuit associated with it such that there will be 1, 2, 3 . . . n−1, n first clamping circuits  6 , where n is the number of columns in the image sensor  1 . First clamping circuits  11 ,  12  in FIG. 2 are representative of first clamping circuits  6 , while only first clamping circuits  11 ,  12  are shown there are n first clamping circuits  6  equal to the number of columns as stated above. Electrical signals representative of the charges stored within the pixels will be output from the selected rows to nodes Vin n  and Vin n−1 , within first clamping circuits  11 ,  12  of the correlated double sampling unit  10  to sample and hold these signals. 
     Referring now to the timing diagram in FIG. 3, which illustrates clocking signals used in conjunction with the Correlated Double Sampling Unit  10  as shown in FIG. 2, the clocking signals employ CMOS clocking levels in the vicinity of 3 volts to the signals present at nodes Vin n  and Vin n−1  to provide sampling references for the CDS  10 . The references used with correlated double sampling unit  10  are (1) the reset value of each pixel which provides a reference value for that pixel; and (2) the actual signal level of that same pixel. A capacitor C s  is provided within each of the first clamping circuits  11 ,  12  for the storage of charge representative of the signals on nodes Vin n−1 , Vin n , respectively. A reset value is obtained as a reference for each pixel after the sample hold reset signal, φ shr , is applied to all the pixels in a given row. The sample hold reset signal, φ shr , is also applied as an active high clock to each of switches S 1 , S 2  to close switches S 1 , S 2 . Closure of switch S 1  in each of the n first clamping units  6  (only two first clamping units  11 ,  12  are shown) results in the signals currently at the Vin nodes being applied to that side of the capacitor C s  adjacent to the Vin node. Closure of switch S 2  results in the opposite side of the capacitor C s  having the reference voltage V ref  applied to it resulting in a voltage across capacitor C s  equal to V ref −V in  after the resetting of any given pixel. In FIG. 2 it should be understood that switches S 1 , S 2 , S 3 , S 4  Sa and Sb are conventional transistor configuration. 
     Still referring to FIG. 2 in conjunction with FIG. 3, switch S 3  is provided for each of the first clamping circuits  11 ,  12 . S 3  will only close when that respective column has been selected. For example the S 3  switch for the nth column will close when φ col     —     n (which in the preferred embodiment is an active high clocking signal) is applied to S 3  to indicate that the nth column has been selected. When the respective column is not selected, S 3  remains open preventing the reference signal V ref  from reaching the input to linear gain circuit  41 . The first clamping circuits  11 ,  12  provide for an initial sampling of signals Vin n , Vin n−1 , respectively. Once the signals Vin n , Vin n−1  have been sampled, they are input to an input to the first stage of a linear gain circuit which comprises a PMOS source follower. The second stage of the linear gain amplifier is NMOS source follower. 
     The reset voltage level of any pixel is first stored in capacitor C s  by applying reset signal, clock φ shr , on switches S 1  and S 2  which closes these switches resulting in reset voltage level being applied to one side capacitor C s  and clamping the side of the capacitor C s  on the same node as the PMOS source follower input to the d.c. voltage of Vref. The voltage across C s  is then V ref −V shr . Clock φ shr , then goes low resulting in the opening of switches S 1  and S 2  allowing Capacitor C s  to float with the voltage across it remaining at V ref −V shr  Signal clock φ sig , is then applied to switch S 4  (as seen in FIG. 3) closing switch S 4  resulting in the application of the signal voltage level of the pixel to the input node of capacitor C s . 
     During normal operation, when Column N− 1  is being read, the first clamping unit  12  is placed in what is called the OUTPUT phase, wherein it will output to the second clamping unit  22  associated with the first clamping unit  12 . While Column N− 1  is in the output phase, V ref  is applied to the input of PMOS source follower  52  by the closing of switch Sb. Also V ref  is inhibited from being applied to OUTPUT Buffer  75  by opening switch S d  at the output side of second clamping circuit  22 , this allows the charge already stored in the second clamping circuit to be applied to the OUT Buffer  75 . 
     The next column to be read is Column N, which is placed in what is termed the SETTLING phase. In the SETTLING phase, S 2  for first clamping circuit  11  is left open allowing the output of capacitor C s  for first clamping circuit  11  to apply its stored charge to the input to PMOS source follower  51 . NMOS source follower  61  within the linear gain amplifier  41  for Column N will be precharging the metal lines used on column bus  60 , OUT_ 1 , to overcome the parasitic capacitance C p  that is inherent in the metal lines. More importantly in terms of the present invention, in the SETTLING phase, switch S a  is left open isolating the second clamping circuit  21  from the OUTPUT Buffer  75 , and switch S c  is closed applying V ref  to the output side of the second clamping circuit  21 . Thus when the NMOS source follower  61  for the linear gain amplifier  41  precharges the output bus OUT_ 1 , the capacitor within the second clamp circuit  21  is precharged with respect to V ref  on its output side. To facilitate these design parameters, digital logic  31 ,  32  enables the linear gain amplifiers  41 ,  42  for both the present and the next column to be read out. Therefore, the linear gain amplifiers  41 ,  42  for both Columns N− 1  and N will be enabled when Column N− 1  is in the OUTPUT phase and Column N is in the SETTLING phase by decoding the column select signals φ col     —     n−1 , φ col     —     n (for columns N− 1  and N) via NOR gates  31 ,  32 . The digital logic uses the status of the current column being read and the next column to be read into a state wherein the linear gain amplifiers for both the present column being read and the next column being read are enabled. This basic scheme is repeated for each of the columns to increase the throughput of CDS  10 . 
     As previously stated, after the occurrence of the φ shr , clock the voltage across the capacitor C s , is V ref −V shr . Switches S 1 , S 2 , S 3 , and S 4  remain open leaving capacitor C s  floating, meaning that the accumulated charge in the capacitor has no dissipation path and therefore, remains the same which is Q 1 =C s *(V ref −V shr ). Accordingly, if V x  is allowed to represent the value of the voltage at the output side of the capacitor C s , after clock φ sig  is applied to switch S 4  and V sig  is the signal potential received at the Vin node, then the charge Q 2 =C s *(V x −V sig ) is equal the charge of Q 1 =C s *(V ref−V   shr ) since the charge stored in the floating capacitor C s  remains constant because the node on PMOS input side of capacitor C s  is floating. Therefore, V x =V ref −V shr +V sig  or V ref −(V shr −V sig ), is the potential level present at the input of each of the PMOS source followers. 
     Linear gain amplifiers  41 ,  42  have at least one PMOS source follower circuit  51 ,  52  and at least one NMOS source follower circuit  61 ,  62  to provide for level shift and voltage gain compensation. In the preferred embodiment, the linear gain amplifiers  41 ,  42  employ PMOS source follower circuits  51 ,  52  with small P-type transistors which reduce the signal error caused by transistor gate capacitance and NMOS source followers circuits  61 ,  62  large N-type transistors and functions as a buffer to drive the large capacitive load of column output circuits out 1 , out 2  which precharge and drive these output circuits out 1 , out 2  and the second clamping circuits  21 ,  22 . It shooed be understood that other configurations of CDS  10  may employ different designs due to different design parameters. For example the preferred embodiment of the present invention employs only second clamping circuits  21 ,  22 , one for each the odd and even columns. Other configurations employing a greater number of second clamping circuits would result in less capacitive load that is required to be driven and result different design considerations. These design modifications and others will be obvious to those skilled in the art. It should also be understood that while linear gain amplifiers are employed by the present invention, usage of different amplifiers is also envisioned and the linear gain amplifiers themselves, while part of the preferred embodiment are not a critical element of the present invention. 
     As stated above, during the time period when φ col(N−1)  is high Column N− 1  is in the OUTPUT phase and Column N is in the SETTLING phase, resulting in the linear gain amplifiers  41 ,  42  for both Column N− 1  and Column N being enabled. However switch S 3  is enabled only for that column that is in the OUTPUT phase, Column N− 1 , which places the V ref  potential level at the input to the PMOS source follower  52 , resulting in a voltage output on to the Out_ 2  Bus as shown by Equation 1. 
     
       
         Vout — 2=β·γ·V ref +γ·Δ p +Δ N   Equation 1 
       
     
     where β is the voltage gain of PMOS source follower, γ is the voltage gain of NMOS source follower, and Δp and ΔN are offsets for the PMOS and NMOS source followers, respectively. The offsets, Δp and ΔN, are D.C. values that are process dependent and vary widely by up to 20% from transistor to transistor and is a primary reason for employing capacitors Cs to store a difference in voltages with respect to a reset value. 
     During that period when φ col(N−1)  is high and Column N− 1  is in the OUTPUT phase placing the potential shown by Equation 1 on to the Out_ 2  bus, switch S B  is closed by Dec_ 0  which is the least significant bit of the column address buss and the charge storage in the second clamping circuit  22  is being read out of the capacitor within the second clamping circuit  22  to OUT Buffer  75  yielding an output as shown by Equation 2. 
     
       
         V out   32  V ref +β·γ·[V shr (N− 1 )−V sig (N− 1 )]  Equation 2 
       
     
     Concurrently, with Column N− 1  being in the OUTPUT phase as shown by the relationships in Equation 1 and Equation 2, Column N is in the SETTLING phase precharging the inherent parasitic capacitance C p . in the bus lines for the Column OUT_ 2  Bus, and also precharging the capacitive second clamping circuit  21  with the initially clamped signal stored in capacitor C s  representative of the charge stored within the N− 1  column pixel signal ready for being selected. The charge stored in the clamp capacitor inside second clamp circuit  21  is shown by Equation 3. 
     
       
         Q=C·{V ref −β·γ·V ref +β·γ·[V shr (N)−V sig (N)]−γ·Δ p −Δ N }  Equation 3 
       
     
     In the SETTLING phase, switches S 2  and S 3  of first clamping circuit  11  for Column N are left open leaving the input node of the PMOS source follower  51  floating at the level of the voltage drop across capacitor C s , which is set to V ref −V shr +V sig , as previously discussed this is the potential level set after the occurrence of the clocks φ shr  and φ sig  NMOS source follower  61  then drives the Channel OUT_ 1  Bus to a voltage level as shown by Equation 4: 
     
       
         V out     —     1 =βγ··[V ref −(V rst (N)−V sig (N))]+γ·Δ p +Δ N   Equation 4 
       
     
     where β and γ are voltage gains of the NMOS and PMOS source followers, and Δ p , Δ N  are the offsets of NMOS and PMOS source follower similar to the case for the Column N above. 
     In the next cycle, Column N will be in the OUTPUT phase, with φ col     —     N  “HIGH”, both Column N and Column (N+ 1 ) are selected. The Nth column is in the OUTPUT phase and the (N+ 1 )th column is in the SETTLING phase. The S a  switch selects the second clamping circuit  21  which places the charge stored within the internal capacitor in the second clamping circuit  21  to the OUT Buffer  75  generating the output voltage for CDS  10  as shown by Equation 5. 
     
       
         V out =V ref +β·γ·[V shr (N)−V sig (N)]  Equation 5 
       
     
     Concurrently with the output as shown in Equation 5, the capacitor within the second clamping circuit  22  for Column N+ 1  is charged in accordance with Equation 6. 
     
       
         Q=C·{V ref −β·γ·[V shr (N+ 1 )−V sig (N+ 1 )]−γ·Δ p −Δ N }  Equation 6 
       
     
     In the manner discussed above, each pixel for each column will output through OUTPUT Buffer  75  to a single analog to digital converter. A CMOS based imager conventional employs a great deal of silicon space for analog to digital converters. Additional space is required in conventional devices for second clamping circuits that are typically provided for each column. The present invention not only greatly reduces the number of second clamping circuits but also allows for the provision of only a single analog to digital converter. After the pixels for every column in a given row are output, the next row is selected and the pixels for that column are output as discussed previously. 
     As previously stated, the linear gain amplifiers  41 ,  42  for the preferred embodiment employs large transistor NMOS source followers  61 ,  62  and small transistor based PMOS source followers  51 ,  52 . Output buffer  75  in the preferred embodiment is also a large transistor NMOS source follower that can generate a 1 mA current with the voltage generated from charged stored within the second clamping circuits  21 ,  22 . The timing of the CDS  10  is such that initially clamped charge provided to the input of PMOS source followers  51 ,  52  will reach there respective second clamping circuit  21 ,  22  within 20 nanoseconds. The charge held within the second clamping circuits  21 ,  22  will (in the OUTPUT phase) arrive at the output of the OUTPUT Buffer within 5 nanoseconds. The signal based current that is available at the OUTPUT Buffer  75  will be valid for 25 nanoseconds within the preferred embodiment. This yields a total delay of 30 nanoseconds from the selected second clamping circuit ( 21  or  22 ) through OUTPUT Buffer  75  which is in accordance with the sampling frequency of 30 million samples that is envisioned by the preferred embodiment. It will be understood by those skilled in the art that capacitors C s  and capacitive second clamping circuits  21 ,  22  have no discharge path with the exception of leakage current, therefore, all charge stored in these circuits will be retained as long as the reference voltage V ref  is not applied to reset the voltage across the capacitor. Accordingly, the above discussed timing is for the preferred embodiment, however, numerous timing configurations will be readily apparent to those skilled in the art. 
     In the preferred embodiment that has been detailed herein, the CMOS power supply voltage is on the order of 3-3.3 volts and V ref  is envisioned to be approximately 1.8 volts. This value of V ref  is envisioned to provide the proper amount of level shift to the input to the PMOS source followers within the linear gain amplifiers as disclosed, herein. It will be readily apparent that other CMOS devices within the prior art will have 5 volt power supplies and future CMOS devices will have power supply voltages on the order of 1.5-1.6 volts and that embodiments of the present invention within these CMOS devices would have a V ref  equal to 0.8-0.9 volts and the size of the transistors used to make the PMOS source followers would then vary accordingly. 
     The foregoing description has detailed the embodiments most preferred by the inventor. However, numerous variations will be obvious to those skilled in the art, accordingly, the scope of in invention should be measured by the appended claims. 
     
       
         
               
             
               
               
               
             
           
               
                   
               
               
                 Parts List 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 1 
                 pixels 
               
               
                   
                 2 
                 row select circuit 
               
               
                   
                 3 
                 column select circuit 
               
               
                   
                 5 
                 image sensor 
               
               
                   
                 6 
                 first clamping circuits 
               
               
                   
                 7 
                 second clamping circuits 
               
               
                   
                 10 
                 correlated double sampling (CDS) 
               
               
                   
                 11 
                 first clamping circuit 
               
               
                   
                 12 
                 first clamping circuit 
               
               
                   
                 21 
                 second clamping circuit 
               
               
                   
                 22 
                 second clamping circuit 
               
               
                   
                 31 
                 digital logic 
               
               
                   
                 32 
                 digital logic 
               
               
                   
                 41 
                 linear gain amplifier 
               
               
                   
                 42 
                 linear gain amplifier 
               
               
                   
                 51 
                 PMOS source follower 
               
               
                   
                 52 
                 PMOS source follower 
               
               
                   
                 60 
                 column bus 
               
               
                   
                 61 
                 NMOS source follower 
               
               
                   
                 62 
                 NMOS source follower 
               
               
                   
                 75 
                 OUTPUT Buffer 
               
               
                   
                 C s   
                 sampling capacitor 
               
               
                   
                 C p   
                 parasitic capacitance 
               
               
                   
                 S1 
                 switch 
               
               
                   
                 S2 
                 switch 
               
               
                   
                 S3 
                 switch 
               
               
                   
                 S4 
                 switch 
               
               
                   
                 Sa 
                 switch 
               
               
                   
                 Sb 
                 switch 
               
               
                   
                 Sc 
                 switch 
               
               
                   
                 Sd 
                 switch 
               
               
                   
                 V in   
                 input voltage 
               
               
                   
                 Vin n   
                 input node 
               
               
                   
                 Vin n-1   
                 input node 
               
               
                   
                 V ref   
                 reference voltage 
               
               
                   
                 V shr   
                 sample hold reset voltage level 
               
               
                   
                 φ sig   
                 signal clock 
               
               
                   
                 φ shr   
                 sample hold reset clock 
               
               
                   
                 φ col     —     n   
                 Column N clock 
               
               
                   
                 φ col     —     n-1   
                 Column N-1 clock