Abstract:
The method is for powering an integrated circuit, said integrated circuit comprising a chip within a package assembly, said chip comprising a plurality of logic circuits each having at least one power input which should not receive a power voltage exceeding a predetermined maximum operating voltage. The method comprises the steps of:—measuring (in step  98 ) the power voltage supplied to the integrated circuit directly within the chip at the power input of at least one logic circuit, and—regulating (in step  96 ) this power voltage such that the voltage supplied to the power input of at least one logic circuit of the chip is equal to the predetermined maximum operating voltage of this logic circuit.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a method and a system for powering an integrated circuit, said integrated circuit comprising a chip within a package assembly, the chip comprising a plurality of logic circuits each having at least one power input which should not receive a power voltage exceeding a predetermined maximum operating voltage.  
         [0002]     More precisely, the invention relates to a method of powering an integrated circuit comprising the steps of: 
        measuring the power voltage supplied to the integrated circuit, and     regulating this power voltage in order to keep the difference between the measured voltage and a reference voltage as small as possible.        
 
         [0005]     The invention also relates to an integrated circuit especially designed to be used in the above method.  
         [0006]     A known solution for designing a faster integrated circuit that executes operations more rapidly is to build the integrated circuit with faster logic circuits. However, faster logic circuits are bigger than normal logic circuits. So this solution results in integrated circuits of increased size.  
         [0007]     Another solution is to increase the power voltage of the integrated circuit. Indeed, the higher the power voltage, the faster the integrated circuit.  
         [0008]     However, the power voltage should never exceed a nominal maximum operating voltage, otherwise this may result in the integrated circuit being definitely damaged.  
         [0009]     In order to power the integrated circuit with a voltage as close as possible to its nominal maximum operating voltage, power supply systems with active feedback are used.  
         [0010]     Such systems are also known as “remote sensing” circuits.  
         [0011]     According to typical prior systems, active feedback is used by power supplies to compensate for voltage drops caused by the impedances of the conductors via which power is transmitted to a load, which may be an integrated circuit. A power supply may include circuitry that compensates for such voltage drops by remotely sensing the voltage delivered to the load. The sensed voltage is typically compared with a voltage reference of the power supply. If the voltage at the integrated circuit is different from the voltage reference, the power supply adjusts its output power voltage, either upwards or downwards, until the sensed voltage is equal to the voltage reference.  
         [0012]     As a practical matter, the nominal maximum operating voltage for an integrated circuit as specified by the manufacturer of the integrated circuit is typically below the actual maximum operating voltage of the integrated circuit by an operating margin voltage, the maximum operating voltage being the voltage level above which the transistors or logics of an integrated circuit will be damaged. To better ensure continuous operation of the integrated circuit under different operating conditions, the manufacturer of the integrated circuit selects the operating margin voltage by taking into consideration a theoretical minimum voltage drop inside the chip of the integrated circuit and a theoretical minimum voltage drop at the electrical interface with the chip. The value of the operating margin voltage is also selected to account for inaccuracies of the testing equipment that rates the maximum voltage at which the integrated circuit continues to operate.  
         [0013]     Voltage drops in the chip of the integrated circuit are often referred to as “on-chip losses” and include voltage drops due to the inherent impedances of the semiconductor material from which the chip was manufactured. On-chip losses can vary for each semiconductor chip manufactured according to the same integrated circuit design. The actual on-chip losses of a particular semiconductor chip may, in fact, be much more than the best-case on-chip losses that are accounted for by the operating margin voltage, which means that the voltage supplied to such a semiconductor chip could be increased above the nominal maximum operating voltage if the actual on-chip losses were known.  
         [0014]     Voltage drops at the electrical interface with the chip of the integrated circuit are often referred to as “package losses” and include voltage drops caused by the impedance of the bond wires, the impedance of the package leads, the interface between the bond wires and the semiconductor chip, the interface between the bond wires and the package leads, and the interface between the leads of a package and the printed circuit board. Like on-chip losses, the actual package losses of a particular semiconductor chip may be worst than the best-case package losses that are accounted for by the operating margin voltage, which means that the voltage supplied to such a semiconductor chip could be increased to above the nominal maximum operating voltage if the actual package losses were known.  
         [0015]     Therefore, the method using remote sensing and other known methods are not optimal.  
       SUMMARY OF THE INVENTION  
       [0016]     It is accordingly an object of the invention to provide a method to power each integrated circuit with a voltage very close to its actual maximum operating voltage.  
         [0017]     With the above and other objects in view, the invention provides a method wherein during the measuring step the power voltage is directly measured within the chip at the power input of at least one of the logic circuits, and wherein the method comprises the step of setting the reference voltage such that the voltage supplied to the power input of at least one logic circuit of the chip is equal to the predetermined maximum operating voltage of this logic circuit.  
         [0018]     In the above method, the voltage used to regulate the power voltage supplied to the integrated circuit is directly measured within the chip of the integrated circuit and therefore bypasses at least the package losses. The regulated voltage supplied to the integrated circuit is thus automatically adjusted in upward direction in order to compensate for the actual package losses.  
         [0019]     Therefore, the voltage supplied to the integrated circuit according to the above method is higher than the one supplied according to the known method, and the integrated circuit will operate at higher speed than previously.  
         [0020]     The features as defined in claims  2  to  3  have the advantage that the method also compensates for the on-chip losses.  
         [0021]     The features as defined in claim  4  have the advantage that the method can be used with existing integrated circuits.  
         [0022]     Other features of the claimed invention are recited in the dependent claims.  
         [0023]     The invention also relates to a system for powering an integrated circuit by the above method.  
         [0024]     The invention also relate to an integrated circuit especially designed to be powered by the above method and having a sensing point at the power input of the first logic circuit that will be damaged in the case of a voltage increase over and above the predetermined maximum operating voltage of this logic circuit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]      FIG. 1  is a cross-section of an integrated circuit,  
         [0026]      FIG. 2  is a schematic diagram of a system for remote sensing according to the invention, and  
         [0027]      FIG. 3  is a flowchart of a method of powering an integrated circuit according to the invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0028]      FIG. 1  shows a cross-section of an integrated circuit  2 . This integrated circuit may be a microprocessor, a memory circuit, or the like.  
         [0029]     Integrated circuit  2  comprises a semiconductor chip  4  within a package assembly  6 .  
         [0030]     Semiconductor chip  4  is connected to package leads  8  via bond wires  10 . Each bond wire is connected at one end to one package lead  8  and at the other end to a bond pad  12 .  
         [0031]     Here, bond pads  12  are intended to receive a voltage supplied by a power supply through the package leads  8 .  
         [0032]     Chip  4  comprises a large number of logic circuits. Each logic circuit has a positive power input, which is connected to pad  12  through conductor tracks in order to be supplied with a positive voltage.  
         [0033]     Hereinafter, the term “logic circuit” will be understood to refer to any logic device or circuit which, when implemented at the transistor level, includes at least a positive power input. Such a logic circuit may be, for example, a logic gate such as an OR gate, AND gate, NOR gate, NAND gate, . . . etc, or an N channel or P channel transistor.  
         [0034]     To simplify  FIG. 1 , only two logic circuits  16  and  18  which are connected to pad  12  via conductor tracks  20  and  22  ( FIG. 2 ), respectively, are represented.  
         [0035]      FIG. 2  shows a remote sensing system  30  that comprises a power supply  32  with a regulating circuitry  33 , which is connected to integrated circuit  2 . Elements of integrated circuit  2  that have already been described with reference to  FIG. 1  have been given with the same references numerals.  
         [0036]     Power supply  32  includes a V CC  output pin  34 , which supplies the power voltage V CC  to lead  8  via a supply line  36 .  
         [0037]     Power supply  32  also includes a V SS  output pin which supplies a system ground voltage V SS  to a package lead  40  of integrated circuit  2  via a ground line  42 . Package lead  40  is connected via one bond wire to a bond pad  44  to which the ground input voltage of each logic circuit is connected.  
         [0038]     Power supply  32  also includes a sensing input pin  50  and a V ref  input pin  52 .  
         [0039]     Input pin  50  is connected to a sensing package lead  54  of the integrated circuit  2  via an input line  56 .  
         [0040]     Sensing lead  54  is connected to a bond pad  58  of the chip  4  via a bond wire  60 . Bond pad  58  is connected to a sensing point  61  via a conductor track  62 . Sensing point  61  is placed within chip  4  at the power input of the logic circuit which is known to be the first to be damaged in the case of a power voltage increase. This will be explained in more details with reference to  FIG. 3 .  
         [0041]     The input impedance of input pin  50  is very high, so the conduction path from sensing line  56  to sensing pin  50  appears to be an open circuit, and little or no current flows through sensing line  56 . Therefore, there are virtually no on-chip or package losses due to the impedance of bond wire  60  and track  62 .  
         [0042]     Pin  52  is connected to a constant reference voltage V ref . Reference voltage V ref  is set to be equal to the predetermined maximum operating voltage of logic circuit  16 . The predetermined maximum operating voltage of a logic circuit is determined by the manufacturer during the design process of chip  4 . Typically, the predetermined maximum operating voltage of a logic circuit is higher than the nominal maximum operating voltage of the integrated circuit  2  since on-chip losses and package losses are not taken into consideration for its determination.  
         [0043]     The way in which the remote sensing system  30  is designed and works will now be explained with reference to  FIG. 3  in the particular case in which all logic circuits of chip  4  have a same predetermined maximum operating voltage equal to 1.2V.  
         [0044]     During design, in step  80 , of the integrated circuit  2 , a conductor track is routed from each power input of each logic circuit to bond pad  12 . The impedances of these tracks are not the same. Indeed, for example, the impedance of track  22  will be higher that the impedance of track  20  since track  22  is longer than track  20 . Therefore, the voltage V 1  at the power input of logic circuit  16  will be higher than the voltage V 2  at the power input of logic circuit  18 . Therefore, sensing point  61  is placed within chip  4  at the power input of the logic circuit associated with the lowest on-chip losses. In other words, this corresponds here to the power input of the logic circuit which is designed to be supplied with the highest power voltage. Typically, the shortest power supply tracks are the ones that connect logic circuits near the external periphery of chip  4  to pad  12 .  
         [0045]     Sensing point  61  is placed here, for example, at the power input of logic circuit  16  in an operation  82 .  
         [0046]     Then conductor track  62  is routed in an operation  84  between sensing point  61  and sensing pad  58 , and sensing pad  58  is connected to sensing lead  54  via bond wire  60  in an operation  86   
         [0047]     In a step  88  for assembling the remote sensing system  30 , sensing lead  54  is connected to input pin  50  in an operation  90 .  
         [0048]     Then the value of voltage reference V ref  of regulating circuitry  33  is set to be equal to the predetermined maximum operating voltage of logic circuit  16  in an operation  92 .  
         [0049]     Once system  30  has been assembled, it works as follows.  
         [0050]     At power on, the voltage V CC  supplied to lead  8  is low, and below the predetermined maximum operating voltage of each of the logic circuits of the integrated circuit  2 .  
         [0051]     Then the regulating circuit  33  regulates the voltage V CC  in step  96  to be equal to reference voltage V ref .  
         [0052]     More precisely, the regulating circuitry measures the value of the voltage V 1  at sensing point  61  in an operation  98 .  
         [0053]     Then the measured voltage value is compared with the value of the reference voltage V ref  in an operation  100 .  
         [0054]     If the measured voltage V 1  is lower than the reference voltage V ref , then voltage V CC  is increased in step  102 .  
         [0055]     Otherwise, the regulating circuitry  33  maintains or decreases voltage V CC  in an operation  104 .  
         [0056]     After operation  102  or  104 , the regulating circuitry  33  returns to operation  98  in order to continuously regulate the voltage V CC  supplied to integrated circuit  2 .  
         [0057]     Since integrated circuit  2  in system  30 , is powered at the predetermined maximum operating voltage of logic circuit  16 , all logic circuits are operated at the maximum possible speed, and integrated circuit  2  operates faster than with known methods.  
         [0058]     As an alternative, integrated circuit  2  may be replaced by the integrated circuit described in U.S. Pat. No. 5,672,997. The integrated circuit disclosed in this document presents a sensing lead connected to a sensing point within the chip in order to measure the lowest power voltage within the chip of the integrated circuit.  
         [0059]     If such an integrated circuit is used, operation  92  in  FIG. 3  is replaced by two operations. The first one consists in establishing the value of the voltage drop caused by the on-chip losses between the sensing point and the power input of the logic circuit which is known to be the first to be damaged in the case of a power voltage increase. For example, if the sensing point is placed at the power input of logic circuit  18 , and the first logic circuit to be damaged is logic circuit  16 , the voltage drop between voltages V 2  and V 1  is determined. Here, this voltage drop is assumed to be equal to 0.1V.  
         [0060]     The second operation consists in setting the value of reference voltage V ref  to be equal to the predetermined maximum operating voltage of logic circuit  16  minus the previously determined voltage drop. Therefore, according to this alternative embodiment, the value of voltage V ref  is set to 1.1V.  
         [0061]     This alternative embodiment has the advantage that it uses the same sensing lead as the one eventually used to minimize the power supply of such an integrated circuit. However, the voltage drop between voltages V 2  and V 1  cannot be established with a very high accuracy. So any speed increase achieved with such an integrated circuit is not as good as with the integrated circuit  2  of the main embodiment.  
         [0062]     Depending on the accuracy of regulating step  96 , the value of the reference voltage V ref  may be set to be equal to a value below the predetermined maximum operating voltage of logic circuit  16  by an operating margin voltage in order always to remain below this predetermined maximum operating voltage established during the design of the integrated circuit design.