Abstract:
Provided are a temperature sensor for generating a sectional temperature code and sectional temperature detection method. In one embodiment, the temperature sensor includes a plurality of serially connected fixed delay cells inputting a temperature detection signal and delaying the temperature detection signal, a variable delay cell inputting the temperature detection signal and delaying the temperature detection signal; and a sectional discrimination logic unit latching outputs of the fixed delay cells in response to the variable delay cells and generating the sectional temperature code. The sectional discrimination logic unit discriminates the sectional temperatures based on temperatures where an output of the variable delay cell meets each of outputs of the fixed delay cells according to the change in the temperature, and generates temperature codes corresponding to the sectional temperatures.

Description:
This application claims the priority of Korean Patent Application No. 10-2006-0003098, filed on Jan. 11, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
   BACKGROUND 
   1. Field of the Invention 
   The present invention relates to a semiconductor integrated circuit, and more particularly, to a temperature sensor for generating a sectional temperature code and sectional temperature detection method. 
   2. Description of the Related Art 
   Semiconductor devices have temperature characteristics in terms of operations. Typical operational characteristics of semiconductor devices are a consumption current IDD and operation speed tACCESS.  FIG. 1  is a graph of temperature characteristics of a semiconductor device. Referring to  FIG. 1 , as the temperature increases, the operation speed increases (A), and the amount of the consumption current IDD decreases (B). 
   These temperature characteristics are of great importance to volatile memory devices such as dynamic random access memory (DRAMs). Since DRAM cells have an increase in the amount of leakage current as temperature rises, data maintenance abilities can be deteriorated due to charges, which reduce data maintenance time. To address this issue, DRAMs require a faster refresh operation. That is, it is necessary to provide a method of changing the refresh period of DRAMs according to temperatures because of the effect on data maintenance capabilities higher temperature changes has. To this end, a temperature sensor is required to sense the temperature inside DRAMs. 
     FIG. 2  is a circuit diagram of a conventional temperature sensor. Referring to  FIG. 2 , the temperature sensor  200  comprises a proportional to absolute temperature (PTAT) current generator  210 , a complementary to absolute temperature (CTAT) current generator  220 , and a comparator  230 . 
   The PTAT current generator  210  comprises first and second PMOS transistors MP 1  and MP 2 , first and second NMOS transistors MN 1  and MN 2 , a resistor R, and first and second diodes D 1  and D 2 . The first and second PMOS transistors MP 1  and MP 2  have the same size and include a first current mirror. The first and second NMOS transistors MN 1  and MN 2  have the same size and include a second current mirror. The size of the first and second diodes D 1  and D 2  has a ratio of 1:M. 
   Since the first current mirror of the first and second PMOS transistors MP 1  and MP 2  and the second current mirror of the first and second NMOS transistors MN 1  and MN 2  are symmetrical, amounts of currents Ia 1  and Ia 2  are identical to each other. That is, Ia 1 :Ia 2 =1:1. 
   A turned-on current ID of a general diode is indicated below,
 
 ID=Is *( e   VD/VT )= Is *( e   VD/VT )  (1)
 
   wherein, Is denotes a contrary directional saturized current of the diode, VD denotes a diode voltage, and VT is a temperature voltage indicated as kT/q. Therefore, the current Ia 1  flows through the first diode D 1  as indicated below,
 
 Ia 1 =Is *( e   VD1/VT )  (2)
 
   A first diode voltage VD 1  is
 
 VD 1 =VT *1 n ( Ia 1 /Is )  (3)
 
   A second diode voltage VD 2  is
 
 VD 2 =VT* 1 n ( Ia 2/( Is*M ))  (4)
 
   Since the amounts of the currents Ia 1  and Ia 2  are identical to each other, the first diode voltage VD 1  is almost the same as a present temperature voltage NOC 0 . Therefore,
 
 V ( NOC 0)= VD 1= VD 2+ Ia 2* R   (5)
 
   If equations 3 and 4 are substituted for equation 5,
 
 VT* 1 n ( Ia 1/ Is )= VT* 1 n ( Ia 2/( Is*M ))+ Ia 2* R   (6)
 
   Therefore, the current Ia 2  is
 
 Ia 2= VT* 1 n ( M )/ R   (7)
 
   Thus, the current Ia 1  is proportional to a temperature. That is, the PTAT current generator  210  generates the current Ia 1  proportional to a current temperature. 
   The CTAT current generator  220  comprises a third PMOS transistor MP 3 , a third NMOS transistor MN 3 , a plurality of resistors Raa, RU 1 ˜RU 5 , and RD 1 ˜RD 5 , and a plurality of switching transistors TU 1 ˜TU 5  and TD 1 ˜TD 5 . 
   The third NMOS transistor MN 3  connects to first and second NMOS transistors MN 1  and MN 2  and a current mirror. An amount of a current Ib is almost identical to the amounts of the currents Ia 1  and Ia 2 . The switching transistors TU 1 ˜TU 5  and TD 1 ˜TD 5  are selectively turned on/off in response to trip temperature control signals AU 1 ˜AU 5  and AD 1 ˜AD 5 , so that the resistors RU 1 ˜RU 5 , and RD 1 ˜RD 5  connected to the turned-on switching transistors TU 1 ˜TU 5  and TD 1 ˜TD 5  are selectively short-circuited. 
   If the amounts of the currents Ib, Ia 1 , and Ia 2  are almost identical to one another, VA and VB node voltages of the PTAT current generator  210  are almost the same as a VC node voltage of the CTAT current generator  220 . In equations 3 and 4, a VT voltage increases as the temperature increases; however, an amount of the current Is increases greater than the amount of the VT voltage. A diode voltage is reduced as the temperature decreases. Therefore, an amount of the current Ib that flows through the resistors Raa, RU 1 ˜RU 5 , and RD 1 ˜RD 5  is reduced as the temperature increases. That is, the current generated by the CTAT current generator  220  is in inverse proportional to the temperature. 
   The comparator  230  compares the present temperature voltage NOCO and a sensed temperature voltage NOC 1 . The present temperature voltage NOCO and a sensed temperature voltage NOC 1  are determined using the current Ia 1  and the current Ib, respectively. The temperature sensor  200  detects a present temperature at a point where the amount of the currents Ia 1  and Ib are identical to each other as illustrated in  FIG. 3 .  FIG. 3  is a graph explaining the temperature detection method using the temperature sensor illustrated in  FIG. 2 . 
   Referring to  FIG. 3 , the current Ia 1  is proportional to the temperature, whereas the current Ib is in inverse proportional to the temperature. For example, when a present temperature of a chip including the temperature sensor  200  is 45° C. If the amount of the Ib current is less than the amount of the current Ia 1 , the trip temperature signals AU 1 ˜AU 5  and AD 1 ˜AD 5  of the CTAT current generator  220  are selectively enabled to control a resistance value of the CTAT current generator  220  and to flow a great amount of the current Ib (C), so that the amounts of the currents Ib and Ia 1  are substantially identical to each other. 
   To the contrary, if the amount of the Ib current is greater than the amount of the current Ia 1 , the trip temperature signals AU 1 ˜AU 5  and AD 1 ˜AD 5  of the CTAT current generator  220  are selectively disabled to control the resistance value of the CTAT current generator  220  and to flow a small amount of the current Ib (D), so that the amounts of the currents Ib and Ia 1  are identical to each other. If the amounts of the currents Ib and Ia 1  are identical to each other, the temperature sensor  200  senses the present temperature of the chip, i.e. 45° C. 
   However, the temperature sensor  200  uses a bipolar transistor of an NPN transistor or a PNP transistor in order to realize the first and second diodes D 1  and D 2 . The NPN transistor or the PNP transistor have analog operational characteristics, where the temperature sensor  200  may sense a nonlinear change in the temperature of the chip. Also, because both the NPN transistor and the PNP transistors are large, their inclusion increases the area of the chip. 
   SUMMARY 
   The present invention provides a temperature sensor for generating a sectional temperature code and a sectional temperature detection method. 
   According to an embodiment of the present invention, a temperature sensor for generating a sectional temperature code may include a plurality of serially connected fixed delay cells inputting a temperature detection signal and delaying the temperature detection signal, a variable delay cell inputting the temperature detection signal and delaying the temperature detection signal, and a sectional discrimination logic unit latching outputs of the fixed delay cells in response to the variable delay cells and generating the sectional temperature code. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: 
       FIG. 1  is a graph of temperature characteristics of a semiconductor device; 
       FIG. 2  is a circuit diagram of a conventional temperature sensor; 
       FIG. 3  is a graph of explaining a temperature detection method using the temperature sensor Illustrated in  FIG. 2 ; 
       FIG. 4  is a block diagram of a temperature sensor according to an embodiment of the present invention; 
       FIG. 5  is a circuit diagram of the first fixed delay cell illustrated in  FIG. 4 ; 
       FIG. 6  is a graph of a simulation of the first fixed delay cell illustrated in  FIG. 5 ; 
       FIG. 7  is a circuit diagram of the variable delay cell illustrated in  FIG. 4 ; 
       FIG. 8  is a graph of a simulation of the variable delay cell illustrated in  FIG. 7 ; 
       FIG. 9  is a graph of the sectional discrimination logic unit illustrated in  FIG. 4 ; and 
       FIG. 10  is a timing diagram of the temperature sensor illustrated in  FIG. 4 . 
   

   DETAILED DESCRIPTION 
   The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Like reference numerals in the drawings denote like elements, and thus their description will be omitted. 
     FIG. 4  is a block diagram of a temperature sensor  400  according to an embodiment of the present invention. Referring to  FIG. 4 , the temperature sensor  400  includes fixed delay cells  411 ,  412 ,  413 , and  414 , a variable delay cell  420 , latch units  431 ,  432 ,  433 , and  434 , and a sectional discrimination logic unit  440 . 
     FIG. 5  is a circuit diagram of the first fixed delay cell  411  illustrated in  FIG. 4 . Referring to  FIG. 5 , the first fixed delay cell  411  comprises a first bias unit  510  and a plurality of delay terminals  520 ,  530 ,  540 , and  550  that input a temperature detection signal T_det. 
   The first bias unit  510  includes a first PMOS transistor  511  and a first NMOS transistor  512  serially connected between a power voltage Vcc and a ground voltage Vss. A gate and drain of the first NMOS transistor  512  are interconnected to generate a second bias signal VB 2 . 
   The first bias unit  510  further includes a second PMOS transistor  513  and second and third NMOS transistors  514  and  515  serially connected between the power voltage Vcc and the ground voltage Vss. A gate and drain of the second PMOS transistor  513  are interconnected, and the gate of the second PMOS transistor  513  is connected a gate of the first PMOS transistor  511  to generate a first bias signal VB 1 . A gate of the third NMOS transistor  515  is connected to the gate of the first NMOS transistor  512 . 
   The first bias unit  510  further includes a third PMOS transistor  516  and fourth NMOS transistors  517  serially connected between the power voltage Vcc and the ground voltage Vss. The gate of the third PMOS transistor  516  is connected to a gate of the first PMOS transistor  511 . A gate and drain of the fourth NMOS transistors  517  are interconnected. 
   In the first bias unit  510 , the first, second and third PMOS transistors  511 ,  513 , and  516  include a current mirror, the first and third NMOS transistor  512  and  515  include another current mirror, and the second and fourth NMOS transistors  514  and  517  include another current mirror. Therefore, the first bias unit  510  has a fixed amount of current that flows through the current mirrors in response to a change in the temperature. 
   The delay terminals  520 ,  530 ,  540 , and  550  are serially connected and receive an input of the temperature detection signal T_det. In response to this input, the delay terminals  520 ,  530 ,  540 , and  559  generate a first fixed delay signal CDI. 
   The first delay terminal  520  includes first and second PMOS transistors  521  and  522  and first and second NMOS transistors  523  and  524  serially connected between the power voltage Vcc and the ground voltage Vss. A gate of the first PMOS transistor  521  is connected to the first bias signal VB 1  and a gate of the second NMOS transistor  524  is connected to the second bias signal VB 2 . Gates of the second PMOS transistor  522  and the first NMOS transistor  523  are connected to the temperature detection signal T_det. Drains of the second PMOS transistor  522  and the first NMOS transistor  523  are output terminals of the first delay terminal  520 . The output of the first delay terminal is connected to an input of the second delay terminal  530 . 
   The other delay terminals  530 ,  540 , and  550  have the same constitution as the first delay terminal  520 . Further, the first PMOS transistors  521  of the delay terminals  520 ,  530 ,  540 , and  550  operate together with the second PMOS transistor  513  of the first bias unit  510  as a current mirror. In addition, the second NMOS transistors  524  of each of the delay terminals  520 ,  530 ,  540 , and  550  operate together with the first NMOS transistor  512  of the first bias unit  510  as a current mirror. 
   Since each of the delay terminals  520 ,  530 ,  540 , and  550  operates with the first bias unit  510  as current mirrors, a fixed current flows through each of the delay terminals  520 ,  530 ,  540 , and  550  regardless of the change in the temperature. Therefore, while each of the delay terminals  520 ,  530 ,  540 , and  550  has a fixed delay time that do not depend on changes in temperatures. Therefore, the first fixed delay signal CD 1  has a fixed period regardless of a change in the temperature. 
     FIG. 6  is a graph of a simulation of the first fixed delay cell  411 . Referring to  FIG. 6 , the first fixed delay signal CD 1  has a change in a delay time of several ns according to the temperature. The first fixed delay signal CD 1  has a fixed change in the delay time compared to a change in the delay time of several ns of the variable delay cell  420 . 
     FIG. 7  is a circuit diagram of the variable delay cell  420  illustrated in  FIG. 4 . Referring to  FIG. 7 , the variable delay cell  420  includes a second bias unit  710  and a plurality of delay terminals  720 ,  730 ,  740 ,  750 , and  760 . 
   The second bias unit  710  includes a first PMOS transistor  711  and a resistor  712  serially connected between a power voltage Vcc and a ground voltage Vss. A gate and drain of the first PMOS transistor  711  are interconnected. The second bias unit  710  further includes a second PMOS transistor  713  and an NMOS transistor  714  serially connected between the power voltage Vcc and the ground voltage Vss. A gate of the second PMOS transistor  713  is connected to the gate of the first PMOS transistor  711 , and the first and second PMOS transistors  711  and  713  operate as a current mirror. The gate and drain of the NMOS transistor  714  are interconnected. The gate of the first PMOS transistor  711  is connected to a third bias signal VB 3  and the gate of the NMOS transistor  714  is connected to a fourth bias signal VB 4 . 
   In the second bias unit  710 , the resistance value of the resistor  712  is increased as a temperature increases so that an amount of current of the first PMOS transistor  711  and the mirrored second PMOS transistor  713  is reduced, and an amount of current of the NMOS transistor  714  serially connected to the second PMOS transistor  713  is reduced. 
   Similarly, the resistance value of the resistor  712  is reduced as a temperature decreases so that an amount of current of the first PMOS transistor  711 , the second PMOS transistor  713 , and the NMOS transistor  714  is increased. 
   The delay terminals  720 ,  730 ,  740 ,  750 , and  760  are serially connected, input the temperature detection signal T_det, and output a variable delay signal VD. Each of the delay terminals  720 ,  730 ,  740 ,  750 , and  760  has the same constitution as each of the delay terminals  510 ,  520 ,  530 , and  540  illustrated in  FIG. 5 . Therefore, further description details will be omitted. 
   The first PMOS transistor  721  of each of the delay terminals  720 ,  730 ,  740 ,  750 , and  760  operates with the first PMOS transistor  711  of the second bias unit  710  as a current mirror. In addition, the second NMOS transistor  724  of each of the delay terminals  720 ,  730 ,  740 ,  750 , and  760  operates with the NMOS transistor  714  of the second bias unit  710  as a current mirror. 
   The operation of the variable delay cell  420  will now be described. 
   As the temperature increases, the amount of current of the first PMOS transistor  711  and the NMOS transistor  714  of the second bias unit  710  is reduced, and an amount of current of the first PMOS transistor  721  and the second NMOS transistor  724  of the delay terminals is also reduced. Thus, the amount of current in each of the delay terminals  720 ,  730 ,  740 ,  750 , and  760  is also reduced so that the operation speed is reduced; thereby increasing the delay time of each of the delay terminals  720 ,  730 ,  740 ,  750 , and  760 . 
   As the temperature decreases, the amount of current of the first PMOS transistor  711  and the NMOS transistor  714  of the second bias unit  710  is increased, and an amount of current of the first PMOS transistor  721  and the second NMOS transistor  724  of the delay terminals is also increased. Thus, the amount of current in each of the delay terminals  720 ,  730 ,  740 ,  750 , and  760  is also increased so that the operation speed is increased, thereby reducing the delay time of each of the delay terminals  720 ,  730 ,  740 ,  750 , and  760 . 
     FIG. 8  is a graph of a simulation of the variable delay cell  420  illustrated in  FIG. 7 . Referring to  FIG. 8 , the variable delay signal VD has a change in the delay time of several μs according to the temperature. 
   Referring again to  FIG. 4 , the plurality of latch units  431 ,  432 ,  433 , and  434  latch first through fourth fixed delay signals CD 1 , CD 2 , CD 3 , and CD 4 , respectively, from the first through fourth fixed delay cells  411 ,  412 ,  413 , and  414  in response to the variable delay signal VD. Each of the first through fourth latch units  431 ,  432 ,  433 , and  434  can include a D-flipflop that inputs the variable delay signal VD as a clock signal CK, and the first through fourth fixed delay signals CD 1 , CD 2 , CD 3 , and CD 4  as data D, respectively. 
     FIG. 9  is a graph of the sectional discrimination logic unit  440  illustrated in  FIG. 4 . Referring to  FIG. 9 , outputs of the first through fourth latch units  431 ,  432 ,  433 , and  434  are provided to the sectional discrimination logic unit  440 . The sectional discrimination logic unit  440  establishes a temperature section between 0° C. through 25° C. as a first section I, a temperature section between 25° C. through 50° C. as a second section II, a temperature section between 50° C. through 75° C. as a third section III, and a temperature section between 75° C. through  1001 C as a fourth section IV. 
   The graph shows that the temperature sections I through IV are divided according to four points where the variable delay signal VD meets each of the first through fourth fixed delay signals CD 1 , CD 2 , CD 3 , and CD 4 . Therefore, the sectional discrimination logic unit  440  latches the first through fourth fixed delay signals CD 1 , CD 2 , CD 3 , and CD 4  in response to the variable delay signal VD to generate temperature code signals T code . A temperature code signal of the first section I is indicated as “1000”, a temperature code of the second section II is indicated as “1100”, a temperature code of the third section III is indicated as “1110”, and a temperature code of the fourth section IV is indicated as “1111”. 
     FIG. 10  is a timing diagram of the temperature sensor  400  illustrated in  FIG. 4 . Referring to  FIG. 10 , the temperature detection signal T_det having a logic high is delayed to generate the first through fourth fixed delay signals CD 1 , CD 2 , CD 3 , and CD 4  and the variable delay signal VD having the logic high. Since the variable delay signal VD changes its delay time according to a temperature, the variable delay signal VD is generated at 0° C. faster than the variable delay signal VD at 100° C. The first through fourth fixed delay signals CD 1 , CD 2 , CD 3 , and CD 4  are generated after a fixed delay time regardless of a change in the temperature. Therefore, the temperature code signal T code  is “1000” at 0° C. indicating that a present temperature of a chip is in the first section I. The temperature code signal T code  is “1111” at 100° C. indicating that the present temperature of the chip is in the fourth section IV. 
   While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.