Abstract:
A variable delay path circuit having delay paths of different lengths is disclosed. Any of the delay paths can be selected to match the operating conditions of the system. In one embodiment of the invention, a delay path circuit having two delay paths connects a driver and receiver. Each of the two delay paths contains sites at both ends for placing zero ohm resistors, solder or copper slugs. To select one of the two delay paths, zero ohm resistors, solder or copper slugs are placed in the sites at the ends of the desired delay path. The delay is then dictated by the time it takes for a clocking signal to travel the length of selected delay path.

Description:
FIELD OF THE INVENTION 
     The present invention relates to electrical circuits, specifically to an assembly for configuring electrical circuits. 
     BACKGROUND OF THE INVENTION 
     Computer systems are increasingly using source synchronous bus designs, which have extremely narrow timing windows. To ensure the collection of correct data at a receiver, a driver must send a clocking signal that is centered as much as possible in a narrow timing window. Typically, the clocking signal arrives just after a data signal arrives at a receiver, and the clocking signal latches in the data into the receiver. The receiver needs a certain setup time to allow it to prepare to receive a data signal, and the receiver also has a hold time requirement which guarantees that the data signal is held at the receiver for a sufficient time to be sampled correctly. Thus, for the receiver to latch in valid data at the correct times, as dictated by the setup and hold times, the clocking signal must be closely centered in the timing window. 
     However, the operating frequencies of computer systems are always increasing, and timing problems can occur at the maximum and minimum operating frequencies of a given design. For example, at low frequencies setup time problems can occur, which means that the clocking signal arrives too quickly; at high frequencies hold time problems can occur, which means that the clocking signal arrives too slowly. In both situations, the clocking signal is not guaranteed to latch in the correct data. 
     A conventional solution to the timing problems is to compromise between the low and high frequencies such that one board can be used for a range of operating frequencies. However, this is not always possible or practical. Nonetheless, to achieve this compromise, the trace lengths of the clocking signal pathways and the data signal pathways must have some length differential among them. 
     In a source synchronous bus design, it is usually desirable to decrease trace length differences. Trace length differences can exacerbate setup problems at low frequencies and hold problems at high frequencies. A variable delay clock trace would help mitigate these timing problems by adjusting the clock delay for a given frequency. This would then allow a single board to be manufactured and used for applications at both low frequencies and high frequencies, thereby saving money by eliminating the need to manufacture multiple boards. 
     SUMMARY OF THE INVENTION 
     A variable delay path circuit that has at least two delay paths of different lengths is disclosed. In one embodiment, the circuit includes a central processing unit and a memory device that are connectable through either a first delay path or a second delay path. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by way of example and is not limited by the figures of the accompanying drawings, in which like references indicate similar elements, and in which: 
     FIG. 1A illustrates a variable delay circuit in accordance with one embodiment of the present invention. 
     FIG. 1B illustrates the circuit shown in FIG. 1A, wherein the shorter delay path is selected between a driver and a receiver. 
     FIG. 1C illustrates the circuit shown in FIG. 1A, wherein the longer delay path is selected between a driver and a receiver. 
     FIG. 2A illustrates a top view of a printed circuit board containing a variable delay circuit. 
     FIG. 2B illustrates the printed circuit board of FIG. 2A, wherein the shorter delay path is selected between a driver and a receiver. 
     FIG. 2C illustrates the printed circuit board of FIG. 2A, wherein the longer delay path is selected between a driver and a receiver. 
     FIG. 3A illustrates a top view another embodiment of the present invention. 
     FIG. 3B illustrates a cross-sectional view of the embodiment of FIG. 3A along line A—A. 
     FIG. 3C illustrates a top view of the embodiment of FIG. 3A, wherein the shorter delay path is selected between a driver and a receiver. 
     FIG. 3D illustrates a top view of the embodiment of FIG. 3A, wherein the longer delay path is selected between a driver and a receiver. 
     FIG. 4 illustrates a top view of yet another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     A variable delay path circuit with individually selectable delay paths of different lengths is described. In the following description, specific details are set forth, such as material types, in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known structures and processing steps have not been shown in particular detail in order to avoid unnecessarily obscuring the present invention. 
     With reference to FIG. 1A, a top view of one embodiment of the present invention is shown. A driver  1 , which, for example, can be a microprocessor, is electrically coupled to a terminal  7  by a trace  3 . A receiver  2 , which, for example, can be a memory device, is electrically coupled to a terminal  8  by a trace  4 . A first delay path  11  is electrically coupled to terminals  5  and  6 , which are separated from terminals  7  and  8  by spaces  13  and  14 , respectively. A second delay path  12  is electrically coupled to terminals  9  and  10 , which are separated from terminals  7  and  8  by spaces  15  and  16 , respectively. Delay path  12  is longer than delay path  11 . Terminals  5  through  10  can be, for example, mounting pads, which are made of exposed metal. Traces  3  and  4  and delay paths  11  and  12  are typically made of copper, but may be made of any electrically conductive material. 
     By being made of exposed metal, terminals  5  through  10  are readily electrically connectable to one another using any electrically conductive material to establish the electrical connection. Furthermore, being able to choose from more than one delay path by establishing electrical connections between different sets of terminals provides great flexibility and widespread application to systems of varying operating frequencies. 
     In FIG. 1B, a top view of the circuit shown in FIG. 1A is shown with the driver and receiver being coupled through the first delay path  11 . Terminals  7  and  5  are electrically coupled by an electrically conductive member  17 , which is disposed in space  13  so that electrically conductive member  17  makes contact with terminals  7  and  5 . Terminals  8  and  6  are electrically coupled by an electrically conductive member  18 , which is disposed in space  14  so that electrically conductive member  18  makes contact with terminals  8  and  6 . Driver  1  and receiver  2  are thereby connected via trace  3 , terminal  7 , electrically conductive member  17 , terminal  5 , delay path  11 , terminal  6 , electrically conductive member  18 , terminal  8 , and trace  4 . Electrically conductive members  17  and  18  can be, but are not limited to, zero ohm resistors, solder or copper slugs. 
     FIG. 1C illustrates a top view of the circuit shown in FIG. 1A with the second delay path  12  selected. Terminals  7  and  9  are electrically coupled by an electrically conductive member  19 , which is disposed in space  15  so that electrically conductive member  19  makes contact with terminals  7  and  9 . Terminals  8  and  10  are electrically coupled by an electrically conductive member  20 , which is disposed in space  16  so that electrically conductive member  20  makes contact with terminals  8  and  10 . Driver  1  and receiver  2  are thereby connected via trace  3 , terminal  7 , electrically conductive member  19 , terminal  9 , delay path  12 , terminal  10 , electrically conductive member  20 , terminal  8 , and trace  4 . Electrically conductive members  19  and  20  can be, but are not limited to, zero ohm resistors, solder or copper slugs. 
     FIGS. 2A through 2C illustrate a variable delay circuit located between a central processing unit  21  and a memory device  22  and disposed on a printed circuit board  37 . Printed circuit board  37  can consist of six alternating layers of fiberglass and copper. A significant advantage of the present invention is that, because more than one delay path is on the same board, it makes possible the manufacture of only one type of board that can be used for systems of different operating frequencies. 
     With reference to FIG. 3A, a top view of another embodiment of the present invention is shown. FIG. 3A is similar to FIG. 2A; however, in FIG. 3A, recesses  54  through  57  are provided in a printed circuit board  58  to separate terminals  46  and  48 ,  47  and  49 ,  48  and  50 , and  49  and  51 , respectively. 
     In FIG. 3B, a cross-sectional view of the embodiment of FIG. 3A is shown along line A—A. 
     FIG. 3C shows a top view of the circuit depicted in FIG. 3A with a first delay path  52  selected. Terminals  48  and  46  are electrically coupled by an electrically conductive member  59 , which is disposed in recess  54  so that electrically conductive member  59  makes contact with terminals  48  and  46 . Terminals  49  and  47  are electrically coupled by an electrically conductive member  60 , which is disposed in recess  55  so that electrically conductive member  60  makes contact with terminals  49  and  47 . A central processing unit  42  and a memory device  43  are thereby connected via a trace  44 , terminal  48 , electrically conductive member  59 , terminal  46 , first delay path  52 , terminal  47 , electrically conductive member  60 , terminal  49 , and a trace  45 . 
     FIG. 3D is a top view of the circuit shown in FIG. 3A with a second delay path  53  selected. Terminals  48  and  50  are electrically coupled by an electrically conductive member  61 , which is disposed in recess  56  so that electrically conductive member  61  makes contact with terminals  48  and  50 . Terminals  49  and  51  are electrically coupled by an electrically conductive member  62 , which is disposed in recess  57  so that electrically conductive member  62  makes contact with terminals  49  and  51 . Central processing unit  42  and memory device  43  are thereby connected via trace  44 , terminal  48 , electrically conductive member  61 , terminal  50 , second delay path  53 , terminal  51 , electrically conductive member  62 , terminal  49 , and trace  45 . 
     FIG. 4 illustrates a top view of yet another embodiment of the present invention. For descriptive purposes, the assembly shown in FIG. 4 is deemed to incorporate a source synchronous bus design. Located on a printed circuit board  79  are four main components: a central processing unit  63 , two memory devices  64 , and an addressing interface  80 . Clock lines  82  connect central processing unit  63  and addressing interface  80 . Addressing lines  83  connect each memory device  64  to addressing interface  80 . Data lines  81  also connect each memory device  64  to central processing unit  63 . For simplicity, only two data lines  81  are shown connecting each memory device  64  to central processing unit  63 . It is appreciated, however, that the number of data lines will typically correspond to the width of the corresponding data bus. Clock lines  82  and addressing lines  83  will typically consist of more than two lines. Furthermore, each memory device  64  is connected to central processing unit  63  through a first delay path  73  of a variable delay circuit similar to the one shown in FIG.  2 B. All of the traces on printed circuit board  79 , including traces  65  and  66 , delay paths  73  and  74 , data lines  81 , clock lines  82 , and addressing lines  83 , are approximately 0.005 inches wide and 1 to 4 inches long, depending on the placement of the four main components and the range of operating frequencies. For example, for a low operating frequency of 266 MHz, the longer delay path  74  would be approximately 3.5 to 4 inches long, and for a high operating frequency of 400 MHz, the shorter delay path would be approximately 2.5 inches long. 
     The advantages of the present invention become apparent by describing a data retrieval operation of the assembly of FIG. 4 in a source synchronous bus design. Central processing unit  63  may require data which it does not have. In such an instance, central processing unit  63  sends the address of the desired data to addressing interface  80  along clock lines  82 . Addressing interface  80  then converts the address of the desired data and sends the converted address to each of the memory devices  64  along addressing lines  83 . Just after central processing unit  63  sends the address of the desired data to addressing interface  80 , central processing unit  63  sends a clocking signal along one of the selected delay paths of the present invention. The typical problem at high frequency operation is that the clocking signal arrives at the memory devices  64  too slowly, which means that not all of the correct data is latched by the clocking signal. Thus, the arrival of the clocking signal needs to be hastened. As shown in FIG. 4, this is accomplished by selecting the shorter delay path  73 . After the clocking signal reaches the memory devices  64  and latches data, the memory devices  64  send back the latched data and a clock strobe to central processing unit  63  along data lines  81 . For low frequency operation, the longer delay path  74  would be selected. 
     With particular reference to computer systems using source synchronous bus designs, the present invention provides a solution to the timing problems in source synchronous bus designs that provides numerous advantages over the common solution of manufacturing a compromise board. For example, the present invention eliminates the need to manufacture multiple boards in order to optimize operation at varying frequencies by having selectable delay paths of different lengths on the same board. Being able to manufacture one board for a range of operating frequencies greatly decreases board costs. The compromise board can be used over a range of operating frequencies because the required length differential among the clocking signal pathways and the data pathways is achieved by adding excess length to the data pathways. However, because the number of data pathways is equal to the width of the data bus, the excess length added to each of the data pathways takes up an inordinate amount of space on the board. The present invention saves much of the space occupied by the excess length added to the data pathways by allowing the length of the delay path to be selected according to the operating frequency of the system. The space-saving feature of the present invention allows the saved space to be used for other purposes, and it also allows for the manufacture of smaller boards, which lowers costs. 
     The details, such as dimensions and materials, set forth within the specification are exemplary of the disclosed embodiments only. While numerous alterations and modifications to the present invention will no doubt become apparent to a person ordinarily skilled in the art having read the foregoing description, it is to be understood that the particular embodiments shown and described by way of illustration are in no way intended to be limiting. Therefore, reference to the details of the illustrated diagrams is not intended to limit the scope of the claims which themselves recite only those features regarded as essential to the invention.