Abstract:
A crystalline substrate based device including a crystalline substrate having formed thereon a microstructure and at least one packaging layer which is formed over the microstructure and defines therewith at least one gap between the crystalline substrate and the at least one packaging layer and at least one opening in the packaging layer communicating with the at least one gap.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to integrated circuits and similar devices generally.  
         BACKGROUND OF THE INVENTION  
         [0002]    U.S. Pat. Nos. 5,716,759 and 5,980,663 and U.S. patent application Ser. No. 09/725,166 of the present assignee relate to the field of the invention.  
         SUMMARY OF THE INVENTION  
         [0003]    The present invention seeks to provide improved packaged crystalline substrate based devices and methods for producing same.  
           [0004]    There is thus provided in accordance with a preferred embodiment of the present invention a crystalline substrate based device including a crystalline substrate having formed thereon a microstructure and at least one packaging layer which is formed over the microstructure and defines therewith at least one gap between the crystalline substrate and the at least one packaging layer and at least one opening in the packaging layer communicating with the at least one gap.  
           [0005]    There is also provided in accordance with another preferred embodiment of the present invention a packaged crystalline substrate including a substrate having formed thereon a microstructure and at least one package which is attached to the substrate over the microstructure and defines therewith at least one gap, the at least one package containing at least one opening communicating with the at least one gap.  
           [0006]    In accordance with a preferred embodiment of the present invention the at least one packaging layer is attached to the crystalline substrate using an adhesive. Preferably, the adhesive includes epoxy. Alternatively, the adhesive includes Thermoplastic materials. In another preferred embodiment, the adhesive includes Thermosetting materials.  
           [0007]    Alternatively, the at least one packaging layer is attached to the crystalline substrate using a soldering. Additionally or alternatively, the at least one packaging layer is attached to the crystalline substrate using intermetalic layer.  
           [0008]    Preferably, the crystalline substrate includes silicon. Alternatively, the crystalline substrate includes lithium niobate. Additionally, the crystalline substrate includes lithium tantalite. In accordance with another preferred embodiment, the crystalline substrate includes quartz. Alternatively, the crystalline substrate includes GaAs.  
           [0009]    In accordance with another preferred embodiment, the at least one packaging layer is at least partially transparent. Preferably, the at least one packaging layer is transparent at least in the spectral range of 100 nm-20 micron.  
           [0010]    In accordance with yet another embodiment the at least one cavity includes a plurality of cavities.  
           [0011]    Preferably, the microstructure includes a micromechanical structure. Alternatively, the microstructure includes a microelectronic structure. Additionally or alternatively, the microstructure includes an optoelectronic structure.  
           [0012]    In accordance with still another embodiment the gap is filled with fluid.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    [0013]FIGS. 1A and 1B are pictorial illustrations of a crystalline substrate based device having an internal cavity, constructed and operative in accordance with preferred embodiments of the present invention;  
         [0014]    [0014]FIGS. 2A and 2B are simplified sectional illustrations of the integrated circuit device shown in FIG. 1A, taken along lines IIA-IIA and IIB-IIB, respectively;  
         [0015]    [0015]FIGS. 3A and 3B are simplified illustrations of a packaging layer for use in crystalline substrate based device in accordance with a preferred embodiment of the present invention; and  
         [0016]    [0016]FIGS. 4A, 4B,  4 C,  4 D,  4 E,  4 F,  4 G,  4 H and  4 I are simplified illustrations of steps in a method for producing a crystalline substrate based device of the type shown in FIGS. 1A and 1B in accordance with a preferred embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0017]    Reference is now made to FIGS. 1A and 1B, which are pictorial illustrations of integrated circuit devices constructed and operative in accordance with preferred embodiments of the present invention. As seen in FIG. 1A, the integrated circuit device  100  includes a relatively thin and compact, environmentally protected and mechanically strengthened integrated circuit package  110  having a multiplicity of electrical contacts  112  plated along the edge surfaces  114  thereof.  
         [0018]    Preferably, contacts  112  extend over edge surfaces onto the underside planar surface  116  of the package. This contact arrangement permits both flat surface mounting and edge mounting of package  110  onto a circuit board. It is noted that the integrated circuit package  110  may include one or more of the following elements (not shown): an integrally formed dichroic filter, color filter, antireflective coating, polarizer, optical grating, integrated wave guide and optical coupling bumps.  
         [0019]    In accordance with a preferred embodiment of the present invention, the integrated circuit package  110  defines a cavity  118 , which is indicated in phantom lines. Integrated circuit package  110  also defines one or more openings  120  which allow fluid communication with the interior of cavity  118 .  
         [0020]    The embodiment shown in FIG. 1B is shown from an opposite orientation. Thus, as seen in the embodiment of FIG. 1B, contacts  112  extend over edge surfaces onto the top planar surface  116  of the package, corresponding to underside planar surface  116  of FIG. 1A. The embodiment of FIG. 1B also differs from that shown in FIG. 1A in that multiple communication openings  120  are defined on opposite sides of cavity  118 . It is appreciated that communication openings  120  may be located in any appropriate position in reference to cavity  118 .  
         [0021]    Reference is now made to FIGS. 2A and 2B, which are simplified sectional illustrations of the integrated circuit device shown in FIG. 1A, taken along lines IIA-IIA and IIB-IIB, respectively. As seen in FIG. 2A, an integrated circuit device  200  includes a crystalline substrate  202 . Underlying the substrate  202  and sealed thereto by electrically isolated material  204  is a packaging layer  206 , typically formed of ceramic, along edges of which are formed electrical contacts  208 , typically defining bumps  210 . Conductive pads  212  preferably connect substrate  202  to electrical contacts  208 .  
         [0022]    In accordance with a preferred embodiment of the present invention a packaging layer  214 , typically formed of ceramic, plastic or organic materials, and associated spacer elements  216 , are attached utilizing an attaching layer  218 , by a conventional attaching technique such as epoxy, soldering intermetalic, Thermoplastic, or Thermosetting process, to substrate  202 , so as to define openings  220  between the substrate  202  and layer  214 .  
         [0023]    As seen in FIG. 2B, integrated circuit device  200  also includes a cavity  222  defined between substrate  202  and layer  214 .  
         [0024]    Typically, openings  220  are provided to enable the introduction of biological fluids or other suitable fluids into cavity  222 , where they are analyzed by sensors located on substrate  202 , or to perform a suitable biological or chemical reaction in order to analyze or modify the fluids as necessary. Alternatively, openings  220  enable the introduction of liquid crystal for liquid crystal displays.  
         [0025]    It is appreciated that packaging layer  214  may be transparent and may have formed thereon a dichroic filter and/or anti-reflective coating. Packaging layer  214  may also be provided with one or more openings, to enable the introduction of biological fluids or other suitable fluids into cavity  222 .  
         [0026]    Reference is now made to FIGS. 3A and 3B, which are simplified illustrations of a packaging layer for use in crystalline substrate based device in accordance with a preferred embodiment of the present invention. The packaging layer consists of a substrate  300  typically formed of ceramic and spacers  306  shown in FIGS. 3A and 3B, which are typically of a partially rectangular configuration, as indicated in FIG. 3B.  
         [0027]    Reference is now made to FIGS. 4A, 4B,  4 C,  4 D,  4 E,  4 F,  4 G,  4 H &amp;  4 I, which are simplified illustrations of steps in a method for producing a crystalline substrate based device similar to that shown in FIG. 1A, clearly illustrating the formation of the openings described therein, in accordance with a preferred embodiment of the present invention.  
         [0028]    As seen in FIG. 4A, a packaging layer  400 , typically of the type shown in FIGS. 3A and 3B, is provided. Attaching layer  402  is applied thereto, preferably along the exposed surfaces of spacers  404  formed thereon. Attaching layer  402  is preferably a high temperature epoxy, soldering, or intermetalic layer.  
         [0029]    As shown in FIG. 4B, the packaging layer  400 , thus prepared, is attached to a crystalline substrate  406 , having defined thereon conductive pads  408  and circuitry  410 . It is appreciated that circuitry  410  may be comprised of electrical circuitry, optoelectric components, optomechanical components or any other suitable device. It is also appreciated that typically, circuitry  410  is in electrical communication with conductive pads  408 . As seen in FIG. 4B, a series of communicating openings  412  is this defined between the packaging layer  400  and the substrate  406 , in accordance with a preferred embodiment of the present invention.  
         [0030]    The crystalline substrate  406  is preferably lapped, as shown in FIG. 4C and etched, as shown in FIG. 4D, to define separate substrates  414 . Following etching, the substrates  414  are adhered via an epoxy layer  416  to an underlying packaging layer  418 , as shown in FIG. 4E.  
         [0031]    As seen in FIG. 4F, the packaging layer  418  and epoxy layer  416  are mechanically notched and thereafter electrical contacts  420  and typically bumps  422  are formed thereon, as seen in FIG. 4G. The resulting assembly is diced as shown in FIG. 4H to yield a plurality of packaged integrated circuit devices, as seen in FIG. 41. It is noted that electrical contacts  420  are in electrical contact with conductive pads  408  defined in substrate  406  as seen in the drawings.  
         [0032]    It is appreciated that here and throughout all of the examples described herein, the crystalline substrate may be any suitable crystalline substrate and may comprise, for example, silicon, lithium niobate, lithium tantalite, quartz, GaAs or any other suitable material.  
         [0033]    The manufacturing techniques described hereinabove and hereinbelow may but need not necessarily include techniques described in any of the following U.S. patent and patent applications of the present assignee, the disclosure of which is hereby incorporated by reference U.S. Pat. No. 5,716,759; 5,980,663 and Ser. No. 09/725,166.  
         [0034]    It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described hereinabove. Rather the scope of the present invention includes both combinations and subcombinations of various features described hereinabove as well as modifications and variations thereof which would occur to a person of skill in the art upon reading the foregoing description and referring to the drawings and which are not in the prior art.