Abstract:
A programmable logic device comprising one or more first stages and one or more second stages. The one or more first stages may comprise one or more gates of a first type each having a first number of inputs. The one or more second stages may comprise one or more gates of a second type each having a second number of inputs, wherein said first and second stages are interlaced.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a method and/or architecture for an AND plane of a programmable logic device generally and, more particularly, to a method and/or architecture for a degenerate network for an AND plane of a programmable logic device. 
     BACKGROUND OF THE INVENTION 
     Referring to FIG. 1, a schematic diagram of a circuit  10  illustrating an implementation of an AND plane is shown. The circuit  10  illustrates a row of a 39-input AND plane. The circuit  10  provides for each of the 39 inputs (e.g., IT 0 -IT 38 ) and a digital complement of each of 39 inputs (e.g., ITB 0 -ITB 38 ) to be wire NORed. Seventy-eight configuration bits M control which of the inputs IT 0 -IT 38  and complements ITB 0 -ITB 38  are NORed. A sense amplifier  12  generates a row output in response to the wired NOR result. 
     Disadvantages of the sense amplifier  12  based AND plane include (i) sensitivity to the switching of a number of pull down paths, (ii) susceptibility to glitching, and (iii) continuous DC power consumption. 
     SUMMARY OF THE INVENTION 
     The present invention concerns a programmable logic device comprising one or more first stages and one or more second stages. The one or more first stages may comprise one or more gates of a first type each having a first number of inputs. The one or more second stages may comprise one or more gates of a second type each having a second number of inputs, wherein said first and second stages are interlaced. 
     The objects, features and advantages of the present invention include providing a method and/or architecture for a degenerate network for an AND plane of a programmable logic device that may (i) provide minimal skew, (ii) use symmetric gates, (iii) use a particular type of gate for each stage, (iv) connect un-used inputs to a voltage or ground supply, (v) provide minimal propagation delay, (vi) provide zero DC power consumption, (vii) provide glitch free operation and/or (v) provide a fully CMOS, degenerate N-input AND plane. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
     FIG. 1 is a schematic diagram illustrating a sense amplifier based circuit for generating a product term; 
     FIG. 2 is a block diagram of a preferred embodiment of the present invention; 
     FIG. 3 is a block diagram illustrating a multiplexer circuit of FIG. 2; 
     FIG. 4 is a block diagram illustrating a logic circuit of FIG. 2; 
     FIG. 5 is a schematic diagram illustrating a tri-state multiplexer circuit of FIG. 3; 
     FIG. 6 is a schematic diagram illustrating a symmetric NAND gate circuit of FIG. 4; and 
     FIG. 7 is a schematic of a symmetric NOR gate circuit of FIG.  4 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 2, a block diagram of a circuit  100  is shown in accordance with a preferred embodiment of the present invention. The circuit  100  may be implemented, in one example, as a row of an AND array of a programmable logic device (PLD). The circuit  100  may have a number of inputs  102   a - 102   n  that may receive a signal (e.g., IT 0 -ITn), a number of inputs  104   a - 104   n  that may receive a digital complement of the signals IT 0 -ITn (e.g, ITB 0 -ITBn), an input  106  that may receive a logic level signal (e.g., a digital HIGH, or “1”), an input  108  that may receive a logic level (e.g., a digital LOW, or “0”), an input  110  that may receive a control signal (e.g., CONFIG), and an output  112  that may present a signal (e.g., PT_OUT). In one example, the circuit  100  may be configured to generate the signal PT_OUT in response to one or more of the signals IT 0 -ITn, the signals ITB 0 -ITBn, the logic level “1”, the logic level “0”, and the signal CONFIG. The signals IT 0 -ITn may be input terms of a programmable logic device. The signal PT_OUT may be, in one example, a product term signal. The signal CONFIG may be, in one example, N-bits wide where N is (i) an integer and (ii) generally twice the number of signals IT 0 -ITn. Each of the N bits may be a separate control signal. The signal CONFIG may comprise, in one example, configuration bits of a programmable logic device. 
     The circuit  100  may comprise a circuit  114  and a circuit  116 . The circuit  114  may be implemented, in one example, as a multiplexer circuit. The circuit  116  may be implemented, in one example, as a logic circuit. The signals IT 0 -ITn and ITB 0 -ITBn, the logic levels “1” and “0”, and the signal CONFIG may be presented to inputs of the circuit  114 . The circuit  114  may have a number of outputs  118   a - 118   n  that may present a signal (e.g., IN 0 -INn) to a number of inputs  120   a - 120   n  of the circuit  116 . The circuit  114  may be configured to select (i) one of the signals IT 0 -ITn, (ii) one of the signals ITB 0 -ITBn, (iii) the logic level “1”, or (iv) the logic level “0” as the signals IN 0 -INn in response to the signal CONFIG. 
     The circuit  116  may be configured to generate the signal. PT_OUT in response to the signals IN 0 -INn. The signal PT_OUT may be a logical combination of the signals IN 0 -INn. In one example, the signal PT_OUT may be a result of a logical AND of the signals IN 0 -INn. 
     Referring to FIG. 3, the circuit  114  may comprise, in one example, a number of multiplexer circuits  122   a - 122   n . In one example, the circuits  122   a - 122   n  may be implemented as tri-state multiplexer circuits. Each of the multiplexer circuits  122   a - 122   n  may have a first input that may receive the logic level “0”, a second input that may receive the logic level “1”, a third input that may receive one of the signals IT 0 -ITn, a fourth input that may receive one of the signals ITB 0 -ITBn, a control input that may receive a number of bits of the signal CONFIG, and an output that may present one of the signals IN 0 -INn. For example, a tri-state multiplexer circuit  122   i  may be configured to select the signal ITi, the signal ITBi, the logic level “0”, or the logic level “1” as the signal INi in response to the signal CONFIG. 
     Referring to FIG. 4, a detailed block diagram illustrating an implementation of the circuit  116  is shown. The circuit  116  may be implemented, in one example, as a degenerate network of logic gates. The logic gates may be implemented as CMOS logic gates. The circuit  116  may comprise a number of logic stages  124   a - 124   n . The number of logic stages  124   a - 124   n  may be varied to meet the design criteria of a particular application. The logic stages  124   a - 124   n  may be configured to generate a number of output signals in response to a logical combination of a number of input signals. The number of signals generated by a particular one of the stages  124   a - 124   n  may be smaller than the number of signals presented to the particular one of the stages  124   a - 124   n . The output signals of a particular stage may be presented to the inputs of a next stage (e.g.,  124   a - 124   b ,  124   b - 124   c , . . . ,  124 (n−1)- 124   n ). In one example, the logic stages  124   a - 124   n  may alternate between NAND stages (e.g.,  124   a ,  124   c , etc.) and NOR stages (e.g.,  124   b ,  124   d , etc.). In another example, the stages  124   a - 124   n  may be interlaced starting with a NOR stage followed by a NAND stage, etcetera. 
     The stage  124   a  may comprise, in one example, a number of gates  126   a - 126   n . The gates  126   a - 126   n  may be implemented, in one example, as 3-input symmetric NAND gates. However, other types of gates may be implemented accordingly to meet the design criteria of a particular application. Each of the signals IN 0 -INn may be presented to an input of the gates  126   a - 126   n . For example, the signals IN 0 -IN 2  may be presented to a first, a second and a third input of the gate  126   a , respectively. The signals IN 3 -IN 5  may be presented to a first, a second and a third input of the gate  126   b , respectively. Similarly, the remaining signals IN 6 -INn may be presented to inputs of the remaining gates  126   c - 126   n . In general, the gates  126   a - 126   n  may be chosen such that the total number of inputs of the gates  126   a - 126   n  matches the number of signals IN 0 -INn. Each of the gates  126   a - 126   n  may have an output that may present a signal to an input of the stage  124   b.    
     The stage  124   b  may be configured to generate a number of output signals in response to a logical combination of the signals received from the stage  124   a . The stage  124   b  may comprise, in one example, a number of gates  128   a - 128   n . The gates  128   a - 128   n  may be implemented, in one example, as 3-input symmetric NOR gates. However, other types of gates may be implemented accordingly to meet the design criteria of a particular application. Each of the signals received from the stage  124   a  may be presented to an input of the gates  128   a - 128   n . If the total number of inputs of the gates  128   a - 128   n  exceeds the number of signals presented by the circuit  124   a , the unused inputs of the NOR gates  128   a - 128   n  may be connected to a supply voltage ground (e.g., GND). Each of the gates  128   a - 128   c  may have an output that may present a signal to an input of the stage  124   c.    
     The stage  124   c  may be configured to generate a number of output signals in response to a logical combination of the signals received from the stage  124   b . The stage  124   c  may comprise, in one example, a number of gates  130   a - 130   n . The gates  130   a - 130   n  may be implemented, in one example, as 3-input symmetric NAND gates. However, other types of gates may be implemented accordingly to meet the design criteria of a particular application. Each of the signals received from the stage  124   b  may be presented to an input of the gates  130   a - 130   n . If the total number of inputs of the gates  130   a - 130   n  exceeds the number of signals presented by the circuit  124   b , the unused inputs of the NAND gates  130   a - 130   n  may be connected to a supply voltage (e.g., VCC). Each of the gates  130   a - 130   n  may have an output that may present a signal to an input of the stage  124   n.    
     The stage  124   n  may comprise, in one example, a gate  132 . The gate  132  may be implemented, in one example, as a 2-input NOR gate. However, other types of gates may be implemented accordingly to meet the design criteria of a particular application. The gate  132  may be configured to generate the signal PT_OUT in response to the signals received from the stage  124   c.    
     In one example, the circuit  100  may be configured to provide a 39-input AND gate. When the number of signals IN 0 -INn is 39, the stage  124   a  may comprise thirteen 3-input NAND gates, the stage  124   b  may comprise five 3-input NOR gates, the stage  124   c  may comprise two 3-input NAND gates, and the stage  124   n  may comprise a 2-input NOR gate. However, other numbers of stages and gates may be implemented to meet the design criteria of a particular application. 
     Referring to FIG. 5, a schematic diagram of an example tri-state multiplexer circuit  122  of FIG. 3 is shown. The multiplexer circuit  122  may comprise a transistor  134 , a transistor  136 , a transistor  138 , a transistor  140 , a transistor  142 , a transistor  144 , a transistor  146 , and a transistor  148 . The transistors  134 ,  140 ,  142 ,  148  may be implemented, in one example, as one or more PMOS transistors. The transistors  136 ,  138 ,  144 , and  146  may be implemented, in one example, as one or more NMOS transistors. However, other types and polarity transistors may be implemented to meet the design criteria of a particular application. The signal IT(x) may be presented to a gate of the transistors  134  and  136 . 
     The signal ITB(x) may be presented to a gate of the transistors  138  and  140 . A bit of the signal CONFIG may be presented to a gate of the transistors  142  and  144 . Another bit of the signal CONFIG may be presented to a gate of the transistors  146  and  148 . A source of the transistor  142  may be connected to a supply voltage (e.g., VCC). A drain of the transistor  142  may be connected to a source of the transistor  134 . A drain of the transistor  134  may be connected to a drain of the transistor  136 , a drain of the transistor  138 , a drain of the transistor  140 , and the output  118 . A source of the transistor  138  may be connected to a drain of the transistor  144 . A source of the transistors  144  and  146  may be connected to a ground voltage (e.g., GND). A drain of the transistor  146  may be connected to a source of the transistor  136 . A source of the transistor  140  may be connected to a drain of the transistor  148 . A source of the transistor  148  may be connected to the supply voltage VCC. Example operations of the circuit  122  may be summarized in the following TABLE 1: 
     
       
         
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 CONFIG (x) 
                 CONFIG (x + 1) 
                 IT (x) 
                 ITB (x) 
                 IN (x) 
               
               
                   
               
             
             
               
                 0 
                 0 
                 0 
                 X 
                 1 
               
               
                 0 
                 0 
                 X 
                 0 
                 1 
               
               
                 0 
                 0 
                 1 
                 1 
                 high-z 
               
               
                 0 
                 1 
                 X 
                 X 
                 IT (X) 
               
               
                 1 
                 0 
                 X 
                 X 
                 ITB (x) 
               
               
                 1 
                 1 
                 1 
                 X 
                 0 
               
               
                 1 
                 1 
                 X 
                 1 
                 0 
               
               
                 1 
                 1 
                 0 
                 0 
                 high-z 
               
               
                   
               
             
          
         
       
     
     Referring to FIG. 6, a schematic diagram illustrating a 3-input symmetric NAND gate of FIG. 3 is shown. The NAND gates  126  and  130  of FIG. 4 may comprise a transistor  150 , a transistor  152 , a transistor  154 , a transistor  156 , a transistor  158 , a transistor  160 , a transistor  162 , a transistor  164 , and a transistor  166 . The transistors  150 ,  152 , and  154  may be implemented, in one example, as one or more PMOS transistors. The transistors  156 ,  158 ,  160 ,  162 ,  164 , and  166  may be implemented, in one example, as one or more NMOS transistors. However, other types and polarity transistors may be implemented to meet the design criteria of a particular application. 
     A first input signal (e.g., A) may be presented to a gate of the transistors  150 ,  156 , and  166 . A second input signal (e.g., B) may be presented to a gate of the transistors  152 ,  158 , and  164 . A third input signal (e.g., C) may be present to a gate of the transistors  154 ,  160 , and  162 . A source of the transistors  150 ,  152 , and  154  may be connected to the supply voltage VCC. A drain of the transistors  150 ,  152 ,  154 ,  156 , and  162  may be connected together to form a node that may present an output signal (e.g., NAND (A, B, C)) that may be the logical NAND of the input signals A, B, and C. 
     A source of the transistor  156  may be connected to a drain of the transistor  158 . A source of the transistor  158  may be connected to a drain of the transistor  160 . A source of the transistor  160  may be connected to the voltage supply ground GND. A source of the transistor  162  may be connected to a drain of the transistor  164 . A source of the transistor  164  may be connected to a drain of the transistor  166 . A source of the transistor  166  may be connected to the voltage supply ground GND. 
     Referring to FIG. 7, a schematic diagram illustrating a 3-input symmetric NOR gate of FIG. 3 is shown. The NOR gate  128  may comprise a transistor  168 , a transistor  170 , a transistor  172 , a transistor  174 , a transistor  176 , a transistor  178 , a transistor  180 , a transistor  182 , and a transistor  184 . The transistors  168 ,  170 ,  172 ,  174 ,  176 , and  178  may be implemented, in one example, as one or more PMOS transistors. The transistors  180 ,  182 , and  184  may be implemented, in one example, as one or more NMOS transistors. However, other types and polarity transistors may be implemented to meet the design criteria of a particular application. 
     A first input signal (e.g., A) may be presented to a gate of the transistors  168 ,  178 , and  180 . A second input signal (e.g., B) may be presented to a gate of the transistors  170 ,  176 , and  182 . A third input signal (e.g., C) may be present to a gate of the transistors  172 ,  174 , and  184 . A source of the transistors  180 ,  182 , and  184  may be connected to the ground potential GND. A drain of the transistors  172 ,  178 ,  180 ,  182 , and  184  may be connected together to form a node that may present an output signal (e.g., NOR(A, B, C)) that may be the logical NOR of the input signals A, B, and C. 
     A source of the transistors  168  and  174  may be connected to the supply voltage VCC. A drain of the transistor  168  may be connected to a source of the transistor  170 . A drain of the transistor  170  may be connected to a source of the transistor  172 . A drain of the transistor  174  may be connected to a source of the transistor  176 . A drain of the transistor  176  may be connected to a source of the transistor  178 . 
     The present invention may provide, in one example, a full CMOS, degenerate 39-input AND gate. The AND gate may be configured, in one example, to generate a product term in response to (i) 39 true inputs, (ii) 39 complemented inputs, and (iii) 78 configuration bits. The present invention may provide the advantages of (i) minimal skew, (ii) minimal propagation delay, (iii) zero DC Power consumption, and/or (iv) glitch free operation. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.