Abstract:
A method of manufacturing an electrically actuable switch and comprising: depositing a first electrode on a surface; depositing an active layer or layers on top of said first electrode; and depositing a second electrode on top of said active layer(s), wherein said step of depositing an active layer or layers is performed in an atmosphere into which a reactive gas is introduced, the partial pressure of the reactive gas being varied during the process so as to introduce dopants into the active layer in a concentration which varies across the active layer.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to an electrically actuated switch and methods of manufacturing an electrically actuated switch. The invention is applicable in particular, though not necessarily, to memristors and their manufacture. 
       BACKGROUND 
       [0002]    The memory-resistor or “memristor” is a passive two-terminal circuit element that maintains a functional relationship between the time integrals of current and voltage. Such a device was originally predicted by L. O. Chua in the article, “memristor—The missing circuit element” (1971). In 2008, Hewlett Packard disclosed a memristor switch having a top and a bottom electrode and an active region comprising a TiO2/TiO2−x bi-layer. Such devices have enormous potential for non-volatile memory applications and neurally-inspired circuits, while they are likely to lend a much needed life extension to Moore&#39;s law. 
         [0003]    The observed memristive effect is believed to be due to charge displacement within a mainly insulating, nanoscale thickness layer of active material. In the initial Hewlett Packard devices, the active charge was shown to be oxygen vacancies within a TiO 2  layer. These vacancies tended to gather on one side of the active layer, depending on the applied bias, leaving the opposite side purely stoichiometric. Later, Hewlett Packard employed direct deposition of TiO 2  layers and they introduced positively charged oxygen vacancies TiO 2−x  by a temperature-annealing step. In a technologically much simpler implementation, a 60-nm-thick amorphous TiO 2  active layer was directly achieved by spinning a TiO 2  sol gel, with the resulting devices exhibiting electrical switching with memory characteristics that are consistent with the electrical behaviour expected of memristors. 
         [0004]    A memristor structure is illustrated schematically in  FIG. 1 . This comprises two electrodes  2 , 5  with an active region disposed in between. This active region  3  entails at least one material for hosting and transporting ions and another material  4  for providing a source/sink of ionic dopants (see  FIG. 1 ). Application of a relatively high biasing voltage to the electrodes causes the displacement of ions within the active region, forming disparate semiconducting  4  and insulating regions  3 , which are maintained when the biasing is ceased. However, if the device is subjected to a bias of reversed polarity, the mobile ions move towards their initial position with the overall resistivity of the device modulated accordingly. The state of the active region can be “read” using a relatively low voltage, insufficient to move ions within the active region. 
         [0005]    The device&#39;s ability to remember the last resistive state is due to the permanent displacement of charge under a DC bias and is empirically considered to be proportional to the inverse square of the layer thickness within which the charge is mobile. Clearly, this effect is substantially large in nanoscale devices, explaining why this behaviour had not been given much attention earlier. 
         [0006]    The memory effect of the memristor can be mathematically described by: 
         [0000]    
       
         
           
             
               
                 
                   
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         [0007]    For a varying charge q, memristance M(q(τ)) depends on the previous “state” of the device, M(q(τ−t)). However, at a given moment τ0, the instantaneous (static) memristance M(q(τ0)) of the device is its resistivity, as in a resistor. Likewise, if q is zero, then M(q(t)) is a constant, which can be considered to be a distinct case of Ohm&#39;s law. 
         [0008]    Ideally a memristor could be characterised in the generalised form of Ohm&#39;s law: 
         [0000]        J   1 =σ(ε 1 ) E   1   (2)
 
         [0000]    where J 1  is the current density at a given location, E 1  is the electric field at that location and σ(ε1) is the conductivity of the material. Equation 2 is particularly interesting in that non-linearity can be introduced by considering an anisotropic material. So far, all existing memristors depend upon a step charge distribution within the active region, by employing two or more layers, each with different ion concentrations. 
         [0009]    The quality of the interfaces  6  between layers within a memristor plays a significant role in the charge displacement, which defines the memristance of the device. Thus the manufacturing method used is of great importance for achieving reliable devices with repeatable characteristics. In previous manufacturing implementations, various layers are deposited at high vacuum, but in transferring between the different process steps required for manufacturing each layer, the interfaces  6  (i.e. the interfaces between the two electrodes and the active layer as well as the interfaces existing within the different regions of the active layer) are inevitably exposed to an ambient air environment. This approach could result in unwanted interfacial states that could potentially “screen” any applied bias, compromising the device&#39;s intrinsic characteristics. 
         [0010]    The following references provide background to memristor structures, properties, and fabrication methods:
   L. O. Chua, “memristor—The missing circuit element”, IEEE Trans. on Circuits Theory, vol. CT-18, no. 5, pp. 507-519, September 1971.   L. O. Chua and S. M. Kang, “Memristive Devices and Systems”, Proc. of the IEEE, vol. 64, no. 2, pp. 209-223, February 1976.   Qiangfei Xia et al, “Fabrication of Nanoscale Memristor Arrays with One Nanoimprint Lithography Step”, published on the WWW at “http://www.eipbn.org/data/papers/5A-4.pdf”   R. S. Williams, “Multi-terminal Electrically actuated switch”, US2008/0079029, Apr. 3, 2008.   R. S. Williams, “Electrically actuated switch”, US2008/0090337, Apr. 17, 2008.   J. Yang, M. D. Pickett, X. Li, D. A. A. Ohlberg, D. R. Stewart and R. S. Williams, “Memristive switching mechanism for metal/oxide/metal nanodevices”, Nature Nanotech., vol. 3, pp. 429-433, July 2008.   M. J. Rozenberg, I. H. Inoue, and M. J. Sanchez, “Nonvolatile Memory with Multilevel Switching: A Basic Model”, Physical Review Letters, vol. 92, no. 17, April 2004.   B. Linares-Barranco and T. Serrano-Gotarredona, “Memristance can explain Spike-Time-Dependent-Plasticity in Neural Synapses”, Nature Precedings, March 2009.   B. L. Moutett, “memristor crossbar neural interface”, US2009/0163826, Jun. 25, 2009.   R. Williams, “How We Found The Missing memristor”, Spectrum, IEEE, vol. 45, 2008, pp. 28-35.   N. Gergel-Hackett, B. Hamadani, B. Dunlap, J. Suchle, C. Richter, C. Hacker, and D. Gundlach, A flexible solution-processed memristor, IEEE Electron Device Lett., vol. 30, no. 7, pp. 706708, 2009. Nadine Gergel-Hackett, “Nonvolatile memory device and processing method”, US2009/0184397.   N. Gergel-Hackett, B. Hamadani, C. A. Richter, D. J. Gundlach, “Non-volatile memory device and processing method”, US2009/0184397, Jul. 23, 2009.   
 
       SUMMARY 
       [0023]    The present inventors have appreciated that it is possible to avoid the above manufacturing deficiencies with a novel process that also reduces the number and complexity of the steps. Hence costs can be reduced and quality can be improved. 
         [0024]    According to a first aspect of the invention there is provided a method of manufacturing an electrically actuable switch and comprising depositing a first electrode on a surface; depositing an active layer or layers on top of said first electrode; and depositing a second electrode on top of said active layer(s). The step of depositing an active layer or layers is performed in an atmosphere into which a reactive gas is introduced, the partial pressure of the reactive gas being varied during the process so as to introduce dopants into the active layer in a concentration which varies across the active layer. 
         [0025]    According to a second aspect of the invention there is provided a method of manufacturing an electrically actuable switch and comprising depositing a first electrode on top of a surface; depositing a first active layer on top of said first electrode; depositing a second active layer on top of said first active layer; and depositing a second electrode on top of said second active layer. The first and second active layers are deposited using respective different source materials, and the deposition steps are carried out within a single chamber without removing the switch from the chamber. 
         [0026]    According to a third aspect of the invention there is provided a method of manufacturing an electrically actuable switch and comprising depositing a first electrode on a surface; depositing a first active layer on top of said first electrode; depositing a second active layer on top of said first active layer; and depositing a second electrode on top of said second active layer. The method further comprises depositing a doping layer between said first electrode and said first active layer or between said second electrode and said second active region, whereby ionic dopants from the doping layer penetrate the first or second active layer to dope that layer. 
         [0027]    According to a fourth aspect of the invention there is provided an electrically actuable switch comprising a first electrode; an active layer or layers on top of said first electrode; and a second electrode on top of said active layer(s), wherein the active layer(s) contain a dopant at a concentration that varies substantially continuously across the active layer(s) between the electrodes. 
         [0028]    Further preferred aspects of the invention are set out in the accompanying dependent claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0029]      FIG. 1  is an illustration of a known memristor structure; 
           [0030]      FIG. 2  is an illustration of a manufacturing process according to an embodiment of the invention; 
           [0031]      FIG. 3  is an illustration of a manufacturing process according to an alternative embodiment; 
           [0032]      FIG. 4  is an illustration of a deposition process using two source materials; 
           [0033]      FIG. 5  is an illustration of a cross-section of a memristor having a stepped dopant profile; 
           [0034]      FIG. 6  is an illustration of a cross-section of a memristor having a continuously varying dopant profile; 
           [0035]      FIG. 7  shows an exemplary manufacturing technique showing a double-layer photoresist and the angle evaporation principle 
           [0036]      FIG. 8  is a graph of memristor characteristics, fabricated according to an embodiment of the invention showing current-voltage characteristics (a) in detail over a reduced range (b) over the entire tested range; and 
           [0037]      FIG. 9  is a graph of memristor, characteristics, fabricated according to an alternative embodiment of the invention showing current-voltage characteristics (a) in detail over a reduced range (b) over the entire tested range. 
       
    
    
     DETAILED DESCRIPTION 
       [0038]    The following presents a new method for fabricating an electrically actuated switch having, for example, applications as a memristor. As discussed above, a memristor is a device having at least a region or layer capable of hosting and transporting dopants and at least a second region or layer for providing the dopants. In contrast with previous manufacturing techniques which deposit the second region from a single material that contains the dopants or adds a material to remove dopants, the method described here deposits the second region from either a mixture of differently doped materials or a mixture of a material and an environment containing dopants. The two methods of mixing and depositing the second region may also be combined. Embodiments of the method allow all layers to be deposited using a single manufacturing process, thus removing the need for intermediate steps which add complexity and may expose the materials to oxidation. Such a method thus lends itself to continuous manufacturing. 
         [0039]    In one embodiment, the process is carried out with a single lithographic step. This could be realized in various ways such as: optical lithography, electron-beam lithography, nano-imprint lithography or substrate conformal imprint lithography. 
         [0040]    An example of such a process is illustrated in  FIG. 2 , and is described as follows:
       I. A photo-resist layer  8  is laid down on a substrate  7  and is exposed through a mask  9  to UV light  10 . Development of the resist removes certain portions of the photo-resist;   II. A bottom electrode  11  is deposited;   III. A first material is deposited in an environment containing an inert gas (such as Argon) to create the first active region  12 ;   IV. The same or different material is deposited in an environment where a reactive gas is present (such as Oxygen) to create the second active region  13 ;   V. A top electrode  14  is deposited.   VI. Lift-off removes material above the extant photo-resist to reveal the final memristor devices  15 .       
 
         [0047]    The deposition of all layers can be performed at room temperature, with no need for a temperature-annealing step as described in previous techniques. Each sub-layer can be of any thickness from a few nanometres (nm) to a micrometer. 
         [0048]    A variation of the process described above is shown in  FIG. 3 , where a masking layer  16  is laid down as a final layer, subsequently patterned using for example photolithography, and an etchant used to remove the undesired portions. 
         [0049]    The process may take place in a high-vacuum chamber. For example, the chamber may initially be at 10 −7  mbar for the deposition of the electrode. During the deposition of the active regions  12 , 13 , the pressure may increase to 2×10 −2  mbar as the inert and/or reactive gas is introduced. In one exemplary embodiment, the Argon flow is 12 SCCM (standard cubic centimeters per minute) for step iii above, becoming 12 SCCM of O 2  during step iv above. 
         [0050]    Deposition of materials may be done with any suitable technique, such as: electron beam evaporation, Knudsen Cell evaporation, RF sputtering from a target material, as well as other known chemical vapour deposition methods. The thickness of the first active region  12  may range from 1 nm to 100 nm and the range of the second region  13  may be the same. In one embodiment, the thickness is 75 nm for the whole active region  12 , 13 . 
         [0051]    Whilst previous devices have been limited to the nanometer scale because the memristance effect was believed to decrease with the square of active region thickness, using devices manufactured according to the processes described here it has been found that the memristance effect is even present on a micro-scale and varies with the volume of the active region. Thus memristors having larger cross-sectional areas are possible by compensating with a very thin film active region. For example a memristor may be made having plan-view dimension of 50 micrometers×50 micrometers, for a cross-sectional area of 2500 square micrometers. Memristors with plan-view dimensions of only a few nanometers have also been made. 
         [0052]    In an alternative embodiment, the process of fabricating the active layer illustrated in  FIG. 2  at step (iv) is:
       iv. Depositing material for the second region  13  concurrently from two or more materials, at least one of which provides a dopant species.       
 
         [0054]      FIG. 4  illustrates deposition of the second region from two source materials  17 , 18 , with the specimen identified by reference numeral  20 . In an exemplary embodiment, the first source material  17  is TiO 2  and the second source material  18  is TiO 2+x  (where “x” represents a fractional amount of extra oxygen atoms per TiO 2  structure), the resulting second region being a mixture of the two materials having a net excess of O 2  ions. In general, the combined utilisation of two or more source materials, one of which is conductive, results in the deposition of a composite layer that will contain conductive defects. Furthermore the concentration of the defects will depend on the relative concentration of the source materials which can be controlled by the deposition method. 
         [0055]    It is also possible to reverse the order of the deposition of the first and second regions. For example, the dopant-rich second region  13  may be deposited before the dopant-free first region  12 . 
         [0056]    It is also possible to combine the techniques described above to create a second region from two or more source materials deposited in an environment where a reactive gas  19 , for example oxygen, is present. The resulting concentration of dopants in this region will depend on the ratio of source materials and the partial pressure of the reactive gas. 
         [0057]    From the foregoing description of the fabrication of the first and second regions, it is possible to manufacture an electrically actuated switch having an active layer with two distinct regions with a dopant step-change interface therebetween or an active region with a continuously varying doping distribution. 
         [0058]      FIG. 5  is an illustration of a cross-section of an electrically actuated switch manufactured using a TiO 2  source target and an oxygen-rich environment. The switch has a step change in dopants within the active layer, creating a TiO 2  sub-layer  12  and TiO 2+x  sublayer  13 . The arrows indicate the displacement of the mobile charge on the upper layer, depending on the applied biasing. Such a switch is manufactured using the process above where there is a step change in the source materials and/or the environment. 
         [0059]    In one embodiment for fabricating the active layer of an electrically actuated switch, deposition of the active layer material begins in an environment where an inert gas is initially present. The flow is gradually reduced and at the same time the flow of a reactive gas (such as Oxygen) is gradually increased. 
         [0060]    In another embodiment for fabricating the active layer of an electrically actuated switch, deposition of the active layer material begins with a first material (e.g. an insulator). The rate of deposition of the first material is gradually reduced and, at the same time, the rate of deposition of a second material (e.g. conductive material) is gradually increased. 
         [0061]      FIG. 6  is an illustration of a cross-section of an electrically actuated switch manufactured using the novel technique. In contrast to  FIG. 5 , there is no step-change in dopant concentration. Rather, this switch has an active layer  21  where the relative TiO 2 /TiO 2+x  ratio changes substantially continuously across the device. The distribution may vary linearly or non-linearly depending on the characteristics desired. The arrows indicate the displacement of the mobile charge on the upper layer, according to the applied biasing. 
         [0062]    Since manufacturing is performed in an (initially) evacuated chamber, the individual interfaces are exposed to controlled gases in controlled amounts instead of air, thus resulting in greater control over the interface quality and greater consistency in device characteristics. 
         [0063]    In principle, the primary material for the first region can be any source material for depositing a material that acts as a host for the ions. A list of potential primary materials is summarised in Table 1. Similarly a secondary material (used in the case of depositing two source materials for the second region) may be any material which provides a dopant species. A list of potential secondary materials is also summarised in Table 1. It is also possible to choose a mixture of primary materials for the first region and/or a mixture of primary materials and secondary materials for the second region. 
         [0064]    The dopant species that results from the secondary material or reactive gas is listed also in Table 1. The reactive gas is any gas that contributes a dopant species by reacting with the primary or secondary material to create a new material with an excess of the dopants. For example, Oxygen, Nitrogen or Fluorine may be used. In contrast, the inert gas does not contribute a dopant and does not react with the primary or secondary material. For, example, Argon, Neon, Xenon or Krypton may be used. 
         [0065]    The following describes in more detail a method of manufacturing memristors, having two variants. These involve the use of a deposition chamber that includes both electron-gun and RF-sputtering evaporation sources and employs contact optical lithography and lift-off for depositing the platinum electrodes and the titanium oxide switching layers. More specifically, the top and bottom electrodes consist of electron-gun evaporated Ti/Pt bilayers with respective thicknesses of 5 and 15 nm. The switching layers consists of two successive 30 nm-thick titanium-oxide layers, sputtered off a stoichiometric TiO2 target at a pressure of 1.8×10 −2  mbar and a RF (13.56 MHz) power density of 8 W/cm2. The first region is deposited in the presence of 12 SCCM flow of Argon gas and the second region is deposited in the presence of 12 SCCM flow of Oxygen gas. 
         [0066]    Two distinct fabrication approaches have been tested using the above conditions. The first one involved deposition of the bottom memristor electrode together with the switching layers in a single lithography and lift-off step. The top intersecting electrode was then fabricated following a second lithography, evaporation and lift-off process. Both these lithographic steps were performed by using an enhanced photoresist profile consisting of a double layer of sub-micron resolution positive photoresist (AZ 5214 E, Clariant). In more detail, the first layer was flood-exposed prior to the spinning of the second layer, followed by exposure of the desired pattern through a photomask and subsequent development of both layers. As a result of this process, an undercut was formed in the first layer as shown in  FIG. 7 , the extent of which can be reproducibly controlled by varying the development time. 
         [0067]    According to this process, whilst the top layer can retain a dimension close to the nominal value, an undercut of over six microns can be formed within the bottom resist layer. This process makes it possible to lift-off sputter-evaporated layers, something not usually achievable with standard photoresist profiles, given the conformal step coverage of sputter deposition. Importantly, the resulting undercut profile can also be used to shrink electrode width towards nanoscale dimensions, if required, by employing angle evaporation, as shown in  FIG. 7 . In this case, the undercut in the photoresist profile, apart from facilitating lift-off, also serves to accommodate the offsets required to shrink electrode lateral dimensions. By using angle evaporation in combination with the enhanced photoresist profile, it is possible to shrink electrode lateral dimensions controllably to below 100 nm. 
         [0068]    A second memristor fabrication technique approach involves the deposition of the whole active stack (top and bottom electrodes and switching layers) in a single lithography and evaporation step, without exposing the unfinished device to ambient conditions, leading to high-quality interfaces with reproducibly controlled characteristics. In more detail, a Ti/Au contact pad is first made on a silicon substrate, onto which the whole stack is deposited via lift-off in a single lithography step. Then, a silicon nitride passivating layer is sputter-deposited and a window etched to uncover the memristor stack as well as the contact pad. Finally, a second contact pad is deposited onto the silicon nitride layer to provide a connection to the top end of the memristor stack. 
         [0069]    The first fabrication approach described above offers a cost-effective method of realising memristors by using standard photolithography and lift-off. These devices can be used for characterisation purposes as well as for integration up to a moderate density. As the method is compatible with the angle evaporation technique, it is possible to shrink electrode width down to under 100 nm without resorting to expensive tools. The device stack has to be exposed to ambient prior to the completion of the fabrication process, which may be a concern with regard to the quality and reproducibility of the interfaces. However, this interruption is designed to occur at the top interface, involving an oxygen-rich titanium oxide layer and the titanium layer of the memristor top electrode. 
         [0070]    The second fabrication approach also uses standard lithography and lift-off but offers higher interface quality, as the whole of the device stack is deposited in one continuous step without exposure to ambient conditions. The same method can be combined with Nanoimprint lithography to yield reliable nanoscale devices. 
         [0071]    Memristors, fabricated with both processing approaches described above, have been characterised. DC current-voltage measurements were performed “on-wafer” by contacting the top and bottom device electrodes with a pair of Wentworth probes, connected with a Keithley 4200 Semiconductor Characterisation System. Since the properties of the devices are dependent upon their previous state, the measurement procedure was of great significance. Thus, all devices were initially biased at the maximum negative voltage (−5V), then the applied bias was ramped up to the maximum voltage of 5V in 50 mV, 1 ms long steps and finally back to −5V again, in the same manner. For device protection purposes, current limiting to +/−100 mA was applied throughout all measurements. 
         [0072]    Typical current-voltage characteristics of 1 μm×1 μm memristors, fabricated with the first approach described above, are shown in the graphs of  FIG. 8  (with  FIG. 8A  illustrating a detail of the graph of  FIG. 8A ). Transition from a high-resistance state (off state) to a low resistance state (on state) occurs at a bias of around +/−1 V. Furthermore, there is an evident broadening of the hysteresis loop after each consecutive scan (three scans are illustrated in  FIG. 8 ). 
         [0073]    Similar memristive response was also observed on devices fabricated with the second method, as shown in the graphs of  FIG. 9  (for which two scans are illustrated). In this case, the device cross-section was 5 μm×5 μm and perhaps this was the reason that transition from an off to an on state is not as clear as in the devices of the first technique. However, the broadening of the hysteresis loop after the second scan is more pronounced and the characteristic curves for all scans are smoother, suggesting a better quality device core. 
         [0074]    These techniques make it possible to realise the full active stack in one continuous step and to controllably shrink the memristor electrodes towards nanoscale width dimensions in a cost-effective way. Devices of various dimensions have been fabricated and characterised. DC current-voltage measurements show reproducible electrical response that is consistent with memristive behaviour. 
         [0075]    The non-linear dynamics of the memristor as well as its “plasticity” are properties that resemble the chemical synapse and have recently attracted significant interest within the “neuromorphic” community. Artificial synaptic networks could in principle imitate the way the human brain functions, particularly the processing and storing of information perceived by the body&#39;s sensory network. Thus, networks comprising high-densities of interconnected memristors have great potential for imitating the large number of synapses between neighbouring neurons. 
         [0000]    
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 List of Potential materials for the active 
               
               
                 regions and the resulting dopant species. 
               
             
          
           
               
                   
                 Primary Material 
                 Secondary Material 
                 Dopant Species 
               
               
                   
                   
               
               
                   
                 TiO 2   
                 TiO 2+x   
                 Oxygen excess 
               
               
                   
                 ZrO 2   
                 ZrO 2+x   
                 Oxygen excess 
               
               
                   
                 HfO 2   
                 HfO 2+x   
                 Oxygen excess 
               
               
                   
                 SrTiO 3   
                 SrTiO 3+x   
                 Oxygen excess 
               
               
                   
                   
               
             
          
         
       
     
         [0076]    Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.