Abstract:
The present invention provides a CMOS (Complementary Metal Oxide Semiconductor) image sensor including a unit pixel, wherein the unit pixel includes photodiodes for receiving incident light and for generating photo charges, single sensing node for selectively receiving the photo charges outputted from the photodiodes; a reset transistor for resetting the single sensing node; and a drive transistor for outputting electrical signals corresponding to voltage levels of the single sensing node, and wherein the CMOS image sensor samples the electrical signals through the correlated double sampling and then outputs a final image value to an external device.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a CMOS (Complementary Metal Oxide Semiconductor) image sensor; and, more particularly, to a pixel array of the CMOS image sensor and a method for driving the pixel array. 
     DESCRIPTION OF THE PRIOR ART 
     Generally, an image sensor is an apparatus to capture images using light sensing semiconductor materials. Since brightness and wavelength of light from an object are different in their amount according to the reflection area, electrical signals from pixels are different from one another. These electrical signals are converted into digital signals, which can be processed in a digital circuit, by an analogue-to-digital converter. Thus, the image sensor needs a pixel array having tens to hundreds of thousands of pixels, a converter for converting analogue voltages into digital voltages, hundreds to thousands of storage devices and so on. 
     Referring to FIG. 1, a conventional CMOS image sensor includes a control and interface unit  10 , a pixel array  20  having a plurality of CMOS image sensing elements, and a single slope AD converter  30 . The single slope AD converter  30  also includes a ramp voltage generator  31  for generating a reference voltage, a comparator (operational amplifier)  32  for comparing the ramp voltage with an analogue signal from the pixel array  20  and a double buffer  40 . 
     The control and interface unit  10  controls the CMOS image sensor by controlling an integration time, scan addresses, operation modes, a frame rate, a bank and a clock division and acts as an interface with an external system. The pixel array  20  consisting of N×M unit pixels having excellent light sensitivity senses images from an object. Each pixel in the pixel array  20  includes a transfer transistor, a reset transistor and a select transistor. The single slope AD converter  30  converts analogue signals from the pixels array  20  into digital signals. This AD conversion is carried out by comparing the ramp voltage with the analogue signals. The comparator  32  searches for a point at which the analogue signals are the same as the falling ramp voltage with a predetermined slope. When the ramp voltage is generated and then starts falling, the control and interface unit  10  generated count signals to count the degree of the voltage drop. For example, the ramp voltage starting the voltage drop, the converted digital value may be “20” in the case where the analogue signals are the same as the falling ramp voltage at 20 clocks of the control and interface unit  10 . This converted digital value is stored in the double buffer  40  as digital data. 
     Where the CMOS image sensor supports the correlated double sampling (hereinafter, referred to as a CDS) in order to generate images of high quality, unit pixels  100  and  120  in the pixel array include a photodiode and four transistors, respectively, as shown in FIG.  2 . Also, the four transistors in the unit pixel  100  include a transfer transistor M 21 , a reset transistor M 11 , a drive transistor M 31  and a select transistor M 41 . The transfer transistor M 21  transfers photoelectric charges generated in the photodiode  101  to sensing node A, the reset transistor M 11  resets sensing node A in order to sense a next signal, the drive transistor M 31  acts as a source follower and the select transistor M 41  outputs the digital data to an output terminal in response to the address signals. 
     In accordance with the CDS, the unit pixel  100  obtains a voltage corresponding to a reset level by turning on the reset transistor M 11  and turning off the transfer transistor M 21 . Also, the unit pixel  100  obtains a data level voltage by turning off the transfer transistor M 21  in a turn-off state of the reset transistor M 11  and reading out photoelectric charges generated in the photodiode  101 . An offset, which is caused by the unit pixel  100  and the comparator  32 , may be removed by subtracting the data level from the reset level. This removal of the offset is essential to the CDS. That is, by removing an unexpected voltage in the unit pixel  100 , it is possible to obtain a net image data value. 
     FIG. 3 shows a timing chart illustrating control signals to control transistors of the unit pixel shown in FIG.  2 . The operation of the unit pixel  100  will be described with reference to FIG.  3 . 
     1) In section “A” of FIG. 3, the transfer transistor M 21  and the reset transistor M 11  are turned on and the select transistor M 41  is turned off, so that the photodiode  101  is fully depleted. 
     2) In section “B”, the turned-on transfer transistor M 21  is turned off, so that the photodiode  101  receives light from an object, generates photoelectric charges and integrates the photoelectric charges (Section “B” continues on regardless of the states of the reset transistor M 11  and the selector transistor M 41 , until the transfer transistor M 21  is again turned on). 
     3) In section “C”, the reset transistor M 11  and the transfer transistor M 21  keep on a turn-on state and a turn-off state, respectively, and the select transistor M 41  is turned on, so that reset voltage level is outputted through the select transistor M 41  and the drive transistor M 31  driven by the voltage level at sensing node A. 
     4) In section “D”, the resent transistor M 11  is turned off and then the reset voltage level generated in section “C” is settled. 
     5) In section “E”, the reset voltage level of section “D” is sampled. 
     6) In section “F”, the reset transistor M 11  and the select transistor M 41  keep on a turn-off state and a turn-on state, respectively, and the transfer transistor M 21  is turned on, so that a data voltage level corresponding to photoelectric charges integrated in the photodiode  101  during the time of section “B”, is transferred to the output terminal through the sensing node A, the drive transistor M 31  and the select transistor M 41 . 
     7) In section “G”, the transfer transistor M 21  is turned off and then the data voltage level generated in section “F” is settled. 
     8) In section “H”, the data voltage level of section “G” is sampled. The reset voltage level and the data voltage level sampled in sections “E” and “F”, respectively, are outputted to the AD converter  30  (FIG. 1) and converted into two digital signals. The difference of two digital signals becomes an output image value of the CMOS image sensor with respect to an image inputted from the photodiode  101  (FIG.  1 ). 
     This conventional unit pixel employs four transistors per pixel in order to support the CDS, thus increasing the chip size of the CMOS image sensor. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to provide a CMOS image sensor that may reduce its chip area by decreasing the number of transistor for a pixel array and a method for driving the CMOS image sensor. 
     In accordance with an aspect of the present invention, there is provided a CMOS (Complementary Metal Oxide Semiconductor) image sensor, comprising: a unit pixel, the unit pixel including: a plurality of photodiodes receiving incident light form an object for generating photoelectric charges; a plurality of transferring means corresponding to the plurality of photodiodes, for transferring the photoelectric charges from the plurality of photodiodes to a single sensing node in response to control signals from an external controller, wherein the control signals controls the plurality of transferring means so that the photoelectric charges from the plurality of photodiodes are selectively transferred to the single sensing node; a common reset means for resetting the single sensing node, wherein the reset means determines reset levels of the single sensing node corresponding to each of the plurality of photodiodes; and a common outputting means for outputting electrical signals corresponding to voltage levels of the single sensing node, wherein the CMOS image sensor samples the electrical signals through the correlated double sampling and then outputs a final image value to the external device. 
     In accordance with another aspect of the present invention, there is provided a method for driving a CMOS image sensor to obtain a single outputted by the correlated double sampling from photoelectric charges generated in a plurality of photodiodes using a single sensing node, wherein the plurality of photodiodes are electrically coupled to the single sensing node, the method comprising the steps of: (a) generating the photoelectric charges in each photodiode; (b) resetting the single sensing node and obtaining a first electrical signal from the single sensing node; (c) transferring the photoelectric charges from one of the photodiodes to the single sensing node and then obtaining a second electrical signal from the single sensing node; (d) resetting the single sensing node and obtaining a third electrical signal from the single sensing node; and (e) transferring the photoelectric charges from another of the photodiode to the single sensing node and then obtaining a fourth electrical signal from the single sensing node. 
     In according with further another aspect of the present invention, there is provided a unit pixel in a CMOS (Complementary Metal Oxide Semiconductor) image sensor, comprising: a first photodiode for receiving light from an object and for generating and integrating photoelectric charges; a first transfer transistor coupled between the first photodiode and a single sensing node, for transferring the photoelectric charges generated in the first photodiode to the single sensing node, in response to a first control signal; a second photodiode for receiving light from the object and for generating and integrating photoelectric charges; a second transfer transistor coupled between the second photodiode and the single sensing node, for transferring the photoelectric charges generated in the second photodiode to the single sensing node, in response to a second control signal; a reset transistor coupled between a power supply and the single sensing node, for outputting the photoelectric charges stored in the single sensing node, in the response to a third control signal; a drive transistor coupled to the power supply, for acting as a source follower in response to an output of the single sensing node; and a select transistor coupled to the drive transistor, for outputting an image data driven by the drive transistor in response to address signals. 
     In accordance with still another aspect of the present invention, there is provided a method for driving a unit pixel which comprises a first photodiode for receiving light from an object and for generating and integrating photoelectric charges; a first transfer transistor coupled between the first photodiode and a single sensing node, for transferring the photoelectric charges generated in the first photodiode to the single sensing node, in response to a first control signal; a second photodiode for receiving light from the object and for generating and integrating photoelectric charges; a second transfer transistor coupled between the second photodiode and the single sensing node, for transferring the photoelectric charges generated in the second photodiode to the single sensing node, in response to a second control signal; a reset transistor coupled between a power supply and the single sensing node, for outputting the photoelectric charges stored in the single sensing node, in the response to a third control signal; a drive transistor coupled to the power supply, for acting as a source follower in response to an output of the single sensing node; and a select transistor coupled to the drive transistor, for outputting an image data driven by the drive transistor in response to address signals, the method comprising the steps of: (a) fully depleting the first and second photodiodes; (b) receiving light in the first and second photodiodes and generating photoelectric charges; (c) turning on the reset transistor, turning off the first and second transfer transistors and outputting a reset voltage level through the single sensing node, the drive transistor and the select transistor; (d) turning off the reset transistor, turning on the first transfer transistor and outputting a data voltage level of the photoelectric charges generated in the first photodiode through the single sensing node, the drive transistor and the select transistor; (e) turning on the reset transistor, turning off the first and second transfer transistors and outputting the reset voltage level through the single sensing node, the drive transistor and the select transistor; and (f) turning off the reset transistor, turning on the second transfer transistor and outputting a data voltage level of the photoelectric charges generated in the second photodiode through the single sensing node, the drive transistor and the select transistor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a block diagram illustrating a conventional CMOS image sensor. 
     FIG. 2 is a circuit diagram illustrating a unit pixel according to the prior art. 
     FIG. 3 shows a timing chart illustrating control signals to control transistors of the unit pixel shown in FIG.  2 . 
     FIG. 4 is a circuit diagram illustrating a unit pixel according to the present invention. 
     FIG. 5 shows a timing chart illustrating control signals to control transistors of the unit pixel shown in FIG.  4 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 
     Referring to FIG. 4, a unit pixel  400  may have the same effect as two unit pixels according to the prior art. While the unit pixels  100  and  120  in FIG. 2 includes two photodiodes and eight transistors, the unit pixel  400  according to the present invention includes two photodiodes and five transistors. A photodiode  401  and a photodiode  402  are connected to a transfer transistor M 43  and a transfer transistor M 44 , respectively. The photodiodes  401  and  402  share a reset transistor M 1 , a drive transistor M 3  and a select transistor M 4 . The photodiode  401  receives light from an object, generates photoelectric charges and integrates the photoelectric charges. The transfer transistor M 43  is coupled between the photodiode  401  and single sensing node A, and transfers the photoelectric charges generated in the photodiode  401  to the single sensing node A in response to a control signal Tx 1 . 
     In similar, the photodiode  402  absorbs light from the object, generates photoelectric charges and integrates the photoelectric charges. The transfer transistor M 44  is coupled between the photodiode  402  and the single sensing node A, and transfers the photoelectric charges generated in the photodiode  402  to the single sensing node A in response to a control signal Tx 2 . 
     The reset transistor M 1  is coupled between a power supply Vdd and the single sensing node A and outputs the photoelectric charges on the single sensing node A in the response to a control signal Rx. The drive transistor M 3  is coupled to the power supply Vdd and acts as a source follower in response to an output of the single sensing node A. The select transistor M 4  is coupled to the drive transistor M 3  and outputs image data in response to a control signal Sx which is produced by address signals. 
     FIG. 5 shows a timing chart illustrating control signals to control transistors of a unit pixel shown in FIG.  4 . The operation of the unit pixel will be described with reference to FIG.  5 . 
     1) In section “A 1 ”, the transfer transistor M 43  and the reset transistor M 1  are turned on and the select transistor M 4  is turned off, so that the photodiode  401  is fully depleted (In section “A 1 ”, the transfer transistor M 43  keeps on a turn-on state, regardless of the state of the transfer transistor M 44 ). 
     2) In section “B 1 ”, the turned-on transfer transistor M 43  is turned off, so that the photodiode  401  generates photoelectric charges and integrates the photoelectric charges (Section “B 1 ” continues on regardless of the states of the reset transistor M 1 , the transfer transistor M 44  and the select transistor M 4 , until the transfer transistor M 43  is again turned on). 
     3) In similar, in section “A 2 ”, the transfer transistor M 44  and the reset transistor M 1  are turned on and the select transistor M 4  is turned off, so that the photodiode  402  is fully depleted (In section “A 2 ”, the transfer transistor M 44  keeps on a turn-on state, regardless of the state of the transfer transistor M 43 ). 
     4) In section “B 2 ”, the turned-on transfer transistor M 44  is again turned off, so that the photodiode  401  generates photoelectric charges and integrates the photoelectric charges (Section “B 2 ” continues on regardless of the states of the reset transistor M 1 , the transfer transistor M 43  and the select transistor M 4  until the transfer transistor M 44  is again turned on). 
     5) In section “C 1 ”, the reset transistor M 1 , the transfer transistors M 43  and M 44  keep on a turn-on state, a turn-off state and a turn-off state, respectively, and the select transistor M 4  is turned on, so that a reset voltage level is outputted through the select transistor M 4  and the drive transistor M 3  is driven by sensing node A. 
     6) In section “D 1 ”, the reset transistor M 1  is turned off and then the reset voltage level generated in section “C 1 ” is settled. 
     7) In section “E 1 ”, the reset voltage level of section “D 1 ” is sampled. 
     8) In section “F 1 ”, the reset transistor M 1  and the select transistor M 4  keep on a turn-off state and a turn-on state, respectively, and the transfer transistor M 43  is turned on, so that a data voltage level corresponding to the photoelectric charges integrated in the photodiode  401  during the time of section “B 1 ”, is transferred to the output terminal through the sensing node A, the drive transistor M 3  and the select transistor M 4 . 
     9) In section “G 1 ”, the transfer transistor M 43  is turned off and then the data voltage level generated in Section “F 1 ” is settled. 
     10) In section “H 1 ”, the data voltage level of section “G 1 ” is sampled. 
     11) In section “C 2 ”, the reset transistor M 1 , the transfer transistors M 44  and M 43  keep on a turn-on state, a turn-off state and a turn-off state, respectively, and the select transistor M 4  is turned on, so that the reset voltage level is outputted through the select transistor M 4  and the drive transistor M 3  is driven by the sensing node A. 
     12) In section “D 2 ”, the reset transistor M 1  is turned off and then the reset voltage level generated in section “C 2 ” is settled. 
     13) In section “E 2 ”, the reset voltage level of section “D 2 ” is sampled. 
     14) In section “F 2 ”, the reset transistor M 1  and the select transistor M 4  keep on a turn-off state and a turn-on state, respectively, and the transfer transistor M 44  is turned on, so that a data voltage level corresponding to the photoelectric charges integrated in the photodiode  402  during the time of section “B 2 ”, is transferred to the output terminal through the sensing node A, the drive transistor M 3  and the select transistor M 4 . 
     15) In section “G 2 ”, the transfer transistor M 44  is turned off and then the data voltage level generated in section “F 2 ” is settled. 
     16) In section “H 2 ”, the data voltage level of section “G 2 ” is sampled. 
     In sections “A 1 ” to “H 1 ”, an output image value of the CMOS image sensor is outputted with respect to an image inputted to the photodiode  401 . Also, in sections “A 2 ” to “H 2 ”, an output image value of the CMOS image sensor is outputted with respect to an image inputted to the photodiode  402 . 
     Especially, sections “A 1 ” and “A 2 ”, in which the photodiode  401  and  402  are fully depleted, may be overlapped each other, and also sections “B 1 ” and “B 2 ”, in which the photoelectric charges are generated and integrated, may be overlapped each other. A depletion time and the integration time of photoelectric charges may be adjusted by the control of a turn-on and a turn-off for the transfer transistors M 43  and M 44 . 
     As illustrated in the prior art, the reset voltage level and the data voltage level for the photodiode  101  sampled in sections “E 1 ” and “H 1 ”, respectively, are outputted to the AD converter  30  (FIG. 1) and converted into two digital signals. The difference of two digital signals becomes an output image value of the CMOS image sensor with respect to an image inputted to the photodiode  101  (FIG.  1 ). 
     Also, the reset voltage level and the data voltage level for the photodiode  102  sampled in sections “E 2 ” and “H 2 ”, respectively, are outputted to the AD converter  30  (FIG. 1) and converted into two digital signals. The difference of two digital signals becomes an output image value of the CMOS image sensor with respect to an image inputted to the photodiode  102  (FIG.  1 ). 
     Sections “D 1 ”, “G 1 ”, “D 2 ” and “G 2 ” are to remove a glitch error of the sensing node A which is caused in the process of a turn-on or a turn-off for the reset transistor M 1  and the transfer transistors M 43  and M 44 , the sensing node A may sample a level value in settled sections (sections “E 1 ”, “H 1 ”, “E 2 ” and “H 2 ”) after sections “D 1 ”, “G 1 ”, “D 2 ” and “G 2 ”. 
     The unit pixel according to the present invention is not limited to two photodiodes as described in an embodiment and may increase the number of photodiodes if necessary. Since the photodiodes of the unit pixel according to the present invention share the reset transistor M 1 , the drive transistor M 3  and the select transistor M 4 , the unit pixel according to the present invention may reduce its chip area as compared with the unit pixel according to the prior art. 
     In the case where a plurality of photodiodes are coupled to the single sensing node, the common reset transistor, which is connected to the single sensing node, is turned on the basis of the photodiode in order to output the reset voltage level of the corresponding photodiode and the transfer transistor is turned on in order to output the data voltage level corresponding to the photoelectric charges generated in the photodiode. That is, after the reset voltage level of the corresponding photodiode is first outputted, the transfer transistor is turned on in order to output the data voltage level. 
     Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.