Abstract:
A CMOS output driver circuit is disclosed which can tolerant an input voltage higher than power supply voltage of the CMOS output driver circuit without drawing excessive current through the output pull-up PMOS transistor.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of provisional application No. 60/124,104, filed Mar. 12, 1999. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to a method of design for a CMOS output circuit (which is also called a tristate, off-chip buffer circuit) which is used in an integrated circuit (IC). In this invention when the output circuit is in its tristate mode, the external terminal connection that is inside the output circuit can tolerate a voltage level exceeding the power supply voltage of the output circuit without significant leakage current flowing through the external terminal connection. 
     As the transistor feature sizes of the modern Complementary Metal Oxide Semiconductors (CMOS) technology has reduced progressively by physical scaling, the supply voltages of the integrated circuits has been reduced in order to reduce the voltage stress across the gate oxide. The gate oxide voltage is a key factor in determining the long term degradation of the transistor gate oxide. Furthermore, the lower power supply voltage of an integrated circuit reduces the power dissipation which allows designers to integrate more functional blocks into a single chip. Furthermore, it has become common to combine several integrated circuits within a system using different supply voltages (for an example, supply voltages can be 1.8 volts; 2.5 volts; 3.3 volts; 5 volts) all of which share the same communication bus inside a system. To perform the proper interface between chips operated on different power supply voltages requires special circuits or devices to avoid excessive leakage current and voltage stress to the input and output circuits. The addition of special devices which can tolerant higher voltage gate stress into input and output circuits of integrated circuit can increase the reliability of said circuits, but will increase the manufacture cost as well. Where possible, it is desirable to find circuit solutions to the problems created by input and output circuits operating in a multiple-power-supply system environment. 
     An examination of the U.S. Pat. No. 5,151,619, J. S. Austin, R. A. Piro, and D. W. Stout disclose a CMOS off-chip driver circuit having one PMOS transistor to bias the well potential of the output pull-up PMOS transistor, another two PMOS transistors and one NMOS transistor to bias the gate of output pull-up PMOS transistor to avoid any leakage when the input voltage exceeds the power supply voltage. However, this invention does allow leakage current to flow through the output pull-up PMOS transistor when the pad voltage is driven above the positive power supply voltage of output driver immediately after the off-chip driver switches from pad voltage driven-high mode to tristate mode. There is a direct current flow through the output pull-up PMOS transistor from the pad terminal to the power supply during the period when the pad terminal voltage rises from VDD to VDD+Vthp since the gate voltage of the output pull-up PMOS transistor is around VDD−Vthn, and the output pull-up PMOS transistor is conducting. 
     In U.S. Pat. Nos. 5,160 and 5,451,889 the output driver circuit does show similar leakage when the pad voltage rises from VDD to VDD+Vth under the same conditions. In U.S. Pat. No. 5,723,992 the author disclose a low-leakage output driver circuit, which can substantially reduce the leakage through the output pull-up PMOS transistor. However, this circuit requires an additional, high power supply to bias the well potential of the output pull-up PMOS transistor. 
    
    
     BRIEF DESCRIPTION OF THE VIEWS OF THE DRAWING 
     The FIGURE is a circuit diagram of a CMOS tristate, off-chip buffer which the invention is applied. 
    
    
     BRIEF SUMMARY OF THE INVENTION 
     This invention relates to a method of design for a CMOS output circuit (which is also called a tristate, off-chip buffer circuit) which is used in an integrated circuit (IC). When the output circuit is in its tristate mode, the off-chip pad inside the output circuit which can tolerate a voltage level exceeding the power supply voltage of the output circuit without significant leakage current. The tristate, off-chip buffer circuit may be configured for use as an output only port from the integrated circuit or as a bi-directional port in which case the tristate mode of operation is associated with the input mode. 
     DETAILED DESCRIPTION OF THE INVENTION 
     The sole FIGURE illustrates a circuit diagram of a CMOS tristate, off-chip buffer in which this invention is applied. The logic function of this tristate buffer is as follow: 
     
       
         
               
               
               
             
           
               
                   
               
               
                 Input signal 21 
                 Input signal 26 
                 State of pad node 30 
               
               
                   
               
             
             
               
                 0 
                 0 
                 Tristate (high impedance) 
               
               
                 1 
                 0 
                 1 
               
               
                 0 
                 1 
                 0 
               
               
                 1 
                 1 
                 Undetermined state 
               
               
                   
               
             
          
         
       
     
     Voltage level of logic “0” is defined as low or near ground level, voltage level of logic “1” is defined as near VDD. VDD is a positive power supply voltage appliked to the tristate, off-chip buffer circuit. 
     For the conditions of input voltage of node  21  and node  26  are near zero volts, both output driving transistors P 12  and N 15  are non-conducting and output pad  30  is in tristate mode which is also called the high impedance state or the input state. The impedance of pad node  30  to ground and to VDD in The sole figure, is very high because a change in the pad voltage from external sources neither sources nor sinks any appreciable current through devices P 12  and N 15  for the external source voltages between VDD and ground. In the tristate mode an external source may be applied to node  30 , pad in The sole figure, at a voltage level which exceeds VDD. As an example, VDD equals 3.3 volts and the external source voltage equals 5 volts. In this situation, when the external source voltage level is higher than VDD, no appreciable DC current (also called DC leakage or tristate leakage) should be allowed to flow from node  30  to either VDD or the ground terminals of the IC. 
     The operation of tristate, off-chip buffer circuit shown in the sole figure is described in what follows. Complementary Metal Oxide Silicon with P-type substrate, N-type well technology is used in the circuit diagram shown in the sole figure. Vthp is defined as threshold voltage of PMOS transistor and Vthn is defined as threshold voltage of NMOS transistor. 
     (1). Pad Voltage Driven Low Mode, Node  30  is Driven to Near Zero Volts by the Buffer 
     Vnode  21  and Vnode  26  are the signals delivered to the buffer from the IC&#39;s internal circuitry. As Vnode 21  is set to near 0 volts and Vnode 26  is set to near the VDD level, the internal nodes of the buffer become Vnode 22 =Vnode 24 =VDD and Vnode 23 =VDD−Vthn. The voltage level of node  25  is VDD minus Vthn which makes output pull-up transistor P 12  non-conducting as Vnode 22  rises to VDD from zero volts. Vnode 26  turns on the pull-down transistor N 15  which makes N 15  conducting and it discharges the pad node  30  to near zero volts. As the voltage of pad node  30  drops below VDD−Vthp, transistor P 7  conducts to charge node  25  to the VDD level. At nearly the same time, transistor P 13  conducts to charge Vnw, the voltage of the N-well of the PMOS transistors P 6 , P 7 , P 9 , P 10 , P 11 , P 12  and P 13 , to the VDD level. 
     (2). Pad Voltage Driven High Mode, Node  30  is Driven to Near VDD by the Buffer 
       
     As Vnode 21  is set to near VDD and Vnode 26  is set to be near zero volts, the internal nodes of buffer Vnode 22 =Vnode 25  =0 volts. The voltage at node  25  falls, which in turn makes pull-up transistor P 12  conducting, and charges pad node  30  up to near the VDD level. The voltage level of node  26  is near zero volts which keeps pull-down transistor N 15  from conducting appreciable current. Transistor P 9  conducts by means of the control voltage Vnode 25  to charge Vnw, the voltage at node NW, which connects the PMOS transistor wells to VDD. The transistor P 5  is conducting to charge node  23  to near the VDD level. 
     (3). Tristate Mode, Node  30  is Driven to the VDD Level Via an External Source 
     The two input signals delivered from the internal IC circuitry, Vnode 21  and Vnode 26  are set to be zero volts and pad node  30  is driven to VDD level from an external source. Transistor P 1  conducts and charges node  22  to near the VDD level. Transistor P 6  conducts and charges node  24  to near the VDD level. Vnode 25  is set to be at the VDD−Vthn level by conduction of transistor N 3  that in turn reduces the conduction of pull-up transistor P 12  as Vnode 22  rises to VDD. The pull-down transistor N 15  is non-conducting because the gate voltage Vnode 26  is near zero. Vnw; the voltage of N-well of the PMOS transistors is kept at the VDD level by transistor P 9 . When Vnode 22  rises from zero to VDD, the voltage of node  23  falls down to VDD−Vthn from the VDD level. 
     (4). Tristate Mode, Node  30  Rises from VDD to VDD+Vthp Via an External Source 
     The two input signals Vnode 21  and Vnode 26  are set to be near zero volts and pad node  30  is driven to VDD+Vthp level from an external source. Transistor P 1  conducts and charges node  22  to near the VDD level. Transistor P 6  conducts and charges node  24  to near the VDD level. All transistor N 3 , N 4  and P 7  are non-conducting. Vnode 25  rises from VDD−Vthn to VDD+Vthp since transistor P 11  is conducting to charge node 25  to the same voltage potential as pad node  30 . Both the pull-down transistor N 15  and pull-up transistor P 12  are non-conducting. Vnw, the voltage of the PMOS transistor wells, is kept between VDD and VDD+Vthp by a balance of conduction between transistor P 10  and the PN diode between node  30  to N-well of transistor P 12 . When node  22  rises from zero to VDD, Vnode 23  falls to VDD−Vthn from near the VDD level. 
     (5). Tristate Mode, Node  30  Rises Above VDD+Vthp Via an External Source 
     The two input signals Vnode 21  and Vnode 26  are set to be near zero volts and pad node  30  is driven above the VDD+Vthp level from an external source. Transistor P 1  conducts and charges node  22  to near the VDD level and transistor P 6  conducts and charges node  24  to near the VDD level. All transistor N 3 , N 4  and P 7  are non-conducting. Since transistor P 11  is conducting, Vnode 25  tracks Vnode 30 . Both the output pull-down transistor N 15  and output pull-up transistor P 12  are non-conducting. Vnw, voltage of N-well of the PMOS transistors, also tracks Vnode  30  through conduction of transistor P 11  and P 10 . When Vnode 22  rises from zero to VDD, Vnode 23  falls to VDD−Vthn from near the VDD level. 
     As described above, there are no DC leakage paths through the CMOS tristate buffer in all 5 situations. Meanwhile, all the voltage level of Vgs (gate to source), Vgd (gate to drain) of all the transistors shown in The sole figure are equal or below VDD in all 5 situations, which avoids potential transistor reliability failure from high gate-oxide-voltage stress.