Abstract:
A microcomputer logic development device realizing high speed sampling RAM monitoring by connecting an existing RAM measurement device, provided with a first block providing functions corresponding to a microcomputer core, a second block having functions corresponding to microcomputer resources, a bus connecting the first and second blocks, and a RAM measurement block provided with a common memory, connected with the bus and RAM measurement device, and realizing a RAM monitor function with respect to the first block, the RAM measurement block realizing a high speed RAM monitoring operation by dividing the timing for processing between the first block and common memory and the timing for processing between the common memory and RAM measurement device.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a microcomputer logic development device used when developing a built-in microcomputer, more particularly relates to a microcomputer logic development device adding a RAM monitor function.  
         [0003]     2. Description of the Related Art  
         [0004]     Electronic control units (ECU) for engine control and other electronic control devices have to be improved in performance along with enactment of tougher emission controls and other legal regulations and improvements in microcomputer performance. Therefore, electronic control devices have to be improved every year. New applications are being developed in advance of current levels of electronic control device performance (hereinafter called “advance logic”).  
         [0005]     Such advance logic is often developed targeting the next generation of microcomputers offering improved performance over the present. However, at the time of development of advance logic, there are no actual electronic control devices with the next generation microcomputers built in them.  
         [0006]     The inventors previously proposed a microcomputer logic development device able to provide the processing performance required for processing advance logic for CPU functions and able to provide resources matching the advanced device from peripheral resources of the microcomputer (for example, see Japanese Unexamined Patent Publication (Kokai) No. 2003-167756 and Japanese Unexamined Patent Publication (Kokai) No. 2004-013626).  
         [0007]     With this microcomputer logic development device, it becomes possible to develop a built-in microcomputer able to realize advanced logic in a short time. At the same time, the microcomputer logic development device can be repeatedly utilized.  
         [0008]      FIG. 1  will be used to explain the configuration of a conventional microcomputer logic development device. Note that  FIG. 1  shows an embodiment of the present invention. Therefore, it should be understood that  FIG. 1  includes parts of a configuration not existing in a conventional device.  
         [0009]     The microcomputer logic development device  1  is comprised of a mother board  2  realizing functions corresponding to a microcomputer core, a core board  3  realizing functions corresponding to microcomputer resources, and an interface board  4  realizing functions corresponding to ECU hardware.  
         [0010]     The mother board  2  and core board  3  are connected by a PCI bus  12  and communicate data of I/O information. The mother board  2  and core board  3  have I/O driver software  6  and  7  loaded in them and control communication of data of the I/O information.  
         [0011]     Next, one of the peripheral functions of a microcomputer is the RAM monitor function. This is a function for extracting RAM data of an address of the microcomputer and returning it to an externally connected RAM measurement device when an address is designated from the RAM measurement device.  
         [0012]      FIG. 2  shows the configuration of a RAM monitor in a built-in microcomputer of an ordinary ECU.  
         [0013]     In an ECU built-in microcomputer  24 , the CPU  25  is connected with the RAM  27  and ROM  28  through an internal bus  26 . The internal bus  26  is connected through a direct memory access (DMA)  29  to the RAM monitor function  30 .  
         [0014]     The RAM measurement device  14  is connected to a RAM monitor function  30 . The RAM measurement device  14  is known, designates RAM addresses and sends them to the monitor function  30 , and stores the RAM data returned from the monitor function  30 . The stored data is displayed processed to a suitable display format.  
         [0015]     The RAM monitor function  30  has a non-brake debugging (NBD) function. The RAM monitor function  30  is one of the on-chip debugging functions. It sets the sampling time in accordance with a specific communication protocol and, when requesting an address of the memory to be monitored, operates the DMA  29  and extracts and returns the data of the requested address.  
         [0016]     The DMA  29  is a function enabling the memory  1  to be directly read and written without software processing. Therefore, in the illustrated built-in microcomputer  24 , it is possible to monitor the RAM without stopping software in the middle of processing. Further, the DMA  29  is a hardware structure, so can perform processing at a high speed.  
         [0017]     When the RAM measurement device  14  is applied to the microcomputer logic development device  1  shown in  FIG. 1 , it is necessary to realize the part of the RAM monitor function  30  by a core board separate from the mother board. In this case, the processing when receiving a request for an address from the RAM measurement device  14  until extracting and returning data through the PCI bus is executed by software processing, so high speed response is impossible like in the conventional device shown in  FIG. 2 .  
       SUMMARY OF THE INVENTION  
       [0018]     An object of the present invention is to provide a microcomputer logic development device which realizes a high speed sampling RAM monitor by connecting an existing RAM measurement device.  
         [0019]     The control software in the microcomputer logic development device is an event driven type executing processing in accordance with outside events. A processing unit is defined by processing when begins and ends when any event is received. Therefore, the RAM values of the control software are updated for each processing unit. Accordingly, if monitoring by processing units of the control software, it becomes possible to monitor the latest values of the RAM values without loss. On the other hand, it is necessary to send the results for a request from the RAM measurement device within the time defined in the RAM measurement device.  
         [0020]     Therefore, the present invention provides a RAM measurement device comprised of a first block providing functions corresponding to a microcomputer core, a second block providing functions corresponding to microcomputer resources, a bus connecting the first and second blocks, and a RAM measurement block including a common memory and connecting the first block with a RAM measurement device. The processing for monitoring the RAM of the first block by the RAM measurement device is divided into processing for writing content of the RAM in the common memory and processing for sending content of the common memory to the RAM measurement device, and separating the processing timings. Due to this, an overall high speed, high performance RAM monitor function is realized.  
         [0021]     According to the present invention, it is possible to provide a microcomputer logic development device realizing high speed sampling RAM monitoring by connecting an existing RAM measurement device. Due to this, it is possible to improve the logic development environment. Further, it is possible to utilizing existing devices as they are and to reduce costs. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]     These and other objects and features of the present invention will become clearer from the following description of the preferred embodiments given with reference to the attached drawings, wherein:  
         [0023]      FIG. 1  is a view of the configuration of a microcomputer logic development device to which the present invention is applied;  
         [0024]      FIG. 2  is a view of the configuration for RAM monitoring in a conventional built-in microcomputer;  
         [0025]      FIG. 3  is a view of the processing timing by a RAM measurement board of  FIG. 1 ;  
         [0026]      FIG. 4  is a view of the concept of the operation of the RAM measurement operation of  FIG. 1 ;  
         [0027]      FIG. 5  is a view of the structure of the address table for a RAM monitor operation stored in the common memory of  FIG. 1 ;  
         [0028]      FIG. 6  is a view of the structure of tables of the mother board and common board of  FIG. 1 ;  
         [0029]      FIG. 7  is a state transition chart at the time of a RAM monitor operation in the RAM measurement board of  FIG. 1 ;  
         [0030]      FIG. 8  is a state transition chart at the time of a RAM monitor operation in the mother board of  FIG. 1 ;  
         [0031]      FIG. 9  is a view of the structure of the address table for a RAM write operation stored in the common memory of  FIG. 1 ;  
         [0032]      FIG. 10  is a view of the relationship between the address table of  FIG. 9  and an internal buffer;  
         [0033]      FIG. 11  is a state transition chart at the time of a RAM write operation in the RAM measurement board of  FIG. 1 ; and  
         [0034]      FIG. 12  is a state transition chart at the time of a RAM write operation in the mother board of  FIG. 1 . 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0035]     Preferred embodiments of the microcomputer logic development device to which the present invention is applied will be described in detail below while referring to the attached figures.  
         [0036]      FIG. 1  shows the configuration of a microcomputer logic development device  1  which realizes a virtual ECU.  
         [0037]     The microcomputer logic development device  1  is comprised of three boards, that is, a mother board  2  for realizing functions corresponding to a microcomputer, a core board  3  for realizing functions corresponding to microcomputer resources, and an interface board for realizing functions corresponding to ECU hardware. Their configurations are similar to those described in the above patent publications.  
         [0038]     As the processing device built in the mother board  2 , a general use CPU is used. This CPU processing performance is set with several levels better processing performance than that actually used for the built-in microcomputer. The microcomputer is loaded with an engine control application  5  and I/O drive software  6 .  
         [0039]     The core board  3  mounts a microcomputer  8  loaded with I/O drive software  7  and a microcomputer peripheral unit (FPGA).  
         [0040]     The interface board  4  mounts a plurality of standard circuits  10  and is connected to the core board  3  through a port assignment conversion port  11 .  
         [0041]     The mother board  2  and the core board  3  are connected by a PCI bus  12  and control data communication of the I/O information by I/O drive software  6 .  
         [0042]     The microcomputer does not mount I/O functions, but the built-in microcomputer requires a core and resources as the I/O functions. To obtain the equivalent, the core board  3  and the PCI bus  12  are combined to realize equivalent functions.  
         [0043]     In this example, to realize a RAM monitor, a RAM measurement board  13  is added to the microcomputer logic development device  1  and thereby enable connection with an existing RAM measurement device  14 .  
         [0044]     The RAM measurement board  13  realizes the RAM monitor function part by a configuration similar to the core board  3 . The RAM measurement board  13  is connected to the PCI bus  12  and is connected through the driver circuit  15  to the RAM measurement device  14 .  
         [0045]     The RAM monitor function of the RAM measurement board  13  extracts the RAM data of the address designated from the RAM measurement device  14  and returns it to the RAM measurement device  14 .  
         [0046]     The functions of the RAM measurement device  14  include a RAM monitor function and a RAM write function. The RAM monitor function reads out the designated address from the RAM measurement device  14  and returns the data value. The RAM write function writes the designated data at the designated address by the RAM measurement device  14 .  
         [0047]     The functions constitute independent processing, so will be explained separately below.  
         [0048]     (RAM Monitor Function)  
         [0049]      FIG. 3  and  FIG. 4  will be used to explain the RAM monitor operation of the RAM measurement board  13  of  FIG. 1 .  
         [0050]      FIG. 3  shows the timing of processing by the RAM measurement board  13 .  FIG. 4  shows the content of the processing.  
         [0051]     As shown in  FIG. 3 , the mother board  2  and the RAM measurement board  13  are connected by the PCI bus  12  and communicate data of the I/O information.  
         [0052]     The RAM measurement board  13  is provided with a common memory  16 . The mother board  2  and the common memory  16  perform update processing at timing  17  of processing units of the control application. The common memory  16  and RAM measurement device  14  communicate data at timing  18  requested from the RAM measurement device  14 .  
         [0053]     The RAM measurement board  13  outputs an INIT signal to the RAM measurement device  14 . The RAM measurement board  13  outputs control signals A and B to the mother board  2 . The mother board  2  outputs a control signal C to the RAM measurement board  13 . Details of the INIT signal and control signals A and B will be explained later.  
         [0054]     The engine control application in the mother board  2  is an event driven type executing software processing in accordance with external events.  
         [0055]     As shown in  FIG. 4 , when receiving events EA and EB at a timing during application processing, the processing is started at the next application processing timing. The processing from the start to the end becomes a processing unit. When receiving an event EC in the standby state, the processing is immediately started. Further, when receiving events EE, EF, and EG at the timing of processing of the event EC, the processing is started at the next application processing timing.  
         [0056]     The RAM values of the control application are updated every processing unit. The RAM measurement board  13  receives data at the final timing  17  of the application processing and stores the RAM values read from the mother board  2  in the common memory  16 . The content of the RAM stored in the common memory  16  does not change during the data reception timing  17  between the mother board  2  and RAM measurement board  13 .  
         [0057]     During this time, the common memory  16  and the RAM measurement board  14  perform processing for data communication at the timing  18  defined by the RAM measurement device  14 .  
         [0058]     The latest values of the RAM values can be monitored without loss by executing the RAM monitor operation in processing units of the control application.  
         [0059]      FIG. 5  shows the structure of the RAM monitor address table.  
         [0060]     The common memory  16  stores the address table  19 . The address table  19  records a plurality of addresses and data corresponding to the addresses.  
         [0061]     As the requested address, it is possible to set addresses up to a maximum number of monitor channels (CHMAX). In the illustrated example, the maximum number of monitor channels becomes  126 .  
         [0062]     The data portion has the data written from the RAM of the mother board  2  written into it corresponding to the requested address.  
         [0063]     The address table  19  includes a table counter counting the number of addresses actually used (number of channels).  
         [0064]     The data stored in the address table  19  becomes a fixed 4 bytes. At the RAM measurement device  14 , requests are set for viewing 1 byte of data or viewing 2 bytes of data. As the configuration for increasing the speed of processing, the data is fixed to 4 bytes. The lower 2 bytes of the address are fixed to 0.  
         [0065]     At the mother board  2 , data is always sent by a fixed 4 bytes, so processing for judging to read 1 byte of data, read 2 bytes, or 4 bytes becomes unnecessary. Therefore, the speed of the processing can be increased.  
         [0066]     The mother board  2  reads the addresses from the common memory  16 , so has an address table  20  in the processing application. The address table  20  is made a mirror structure identical to the address table  19  in the common memory  16 .  
         [0067]      FIG. 6  will be used to explain the relationship between the address table  20  of the mother board  2  and the address table  19  of the RAM measurement board  13 .  
         [0068]     In the mother board  2 , at the time of initialization, an address is read from the address table  19  of the common memory  16  and stored in the address table  20 . At this time, the value of the table counter is also read.  
         [0069]     In normal processing after the end of initialization, at the timing  17  of receiving the final data of the application processing, the data is extracted from the RAM corresponding to the designated address and written in the address table  20 . Further, data stored in the address table  20  is sent to the common memory  16  of the RAM measurement board  13  for exactly the amount counted by the table counter.  
         [0070]     The RAM measurement board  13  successively stores the received data in the address table  19 .  
         [0071]     In this way, in normal processing, the mother board  2  sends the RAM measurement board  13  only data and does not send addresses. Due to this, it is possible to realize higher speed processing.  
         [0072]      FIG. 7  will be used to explain the processing at the time of RAM monitoring in the RAM measurement board  13 .  
         [0073]     First, the processing of  FIG. 7  as a whole will be explained.  
         [0074]     The initialization is processing for preparing the address table  19  in the common memory  16 .  
         [0075]     When the address table preparation processing ends, normal processing is shifted to.  
         [0076]     During the normal processing, when receiving a request for change of settings from the RAM measurement device  14 , the routine returns to the initialization and redoes the address table preparation processing.  
         [0077]     Next, the details of the initialization will be explained.  
         [0078]     A1. Hold the INIT signal from the RAM measurement board  13  to the RAM measurement device ( FIG. 3 ) inactive. Due to this, the RAM measurement device  14  does not start the RAM monitor function until the INIT signal enters the active state.  
         [0079]     A2. Initially output the address table update request signal A from the RAM measurement board  13  to the mother board  2  ( FIG. 3 ).  
         [0080]     A3. Initialize the address table  19  of the common memory  16  and set the value of the table counter to “0”.  
         [0081]     A4. Turn off the table preparation flag (not shown).  
         [0082]     When the initialization is completed, the INIT signal to the RAM measurement device  14  is made active and the routine shifts to the address table preparation processing.  
         [0083]     The details of the address table preparation processing will be explained next.  
         [0084]     When receiving a monitor request from the RAM measurement device  14 , the following processing is performed:  
         [0085]     B1. Fetch the address from the received monitor request.  
         [0086]     B2. While the table preparation flag is off, return dummy data (0) to the RAM measurement device  14 . This is processing required by the RAM measurement device  14 .  
         [0087]     B3. Search the address table  19  in the range shown by the table counter. Here, if the table counter shows “0”, it is judged that there is no identical address. If there is an identical address, it is judged that the setter has mistakenly set the same address, so the processing for this address is not performed. If there is no identical address, add the requested address to the address table  19  and update the table counter.  
         [0088]     Next, whether the address table has finished being prepared is judged. Specifically, it is judged finished if either of the next conditions of C1 and C2 is satisfied.  
         [0089]     C1. After the address table preparation processing has been started, fetch the number of addresses of the set maximum number of channels (N. CHMAX) of the RAM measurement device  14 .  
         [0090]     C2. After the address table preparation processing has been started, fetch the addresses of the maximum sampling time (T. SMPMAX) of the RAM measurement device  14 .  
         [0091]     When checking the above conditions C1 and C2 and neither of the conditions is satisfied, the processing of the above B1 to B3 is repeated to thereby prepare the address table  19 .  
         [0092]     Note that just one of the above conditions C1 and C2 can also be made the judgment condition. In the above example, however, the two conditions are employed to judge the final determination by the conditions judged faster.  
         [0093]     When either condition of the above conditions C1 and C2 is satisfied, the processing of the following D1 to D4 is performed:  
         [0094]     D1. Return dummy date ( 0 ) to the RAM measurement device  14 .  
         [0095]     D2. Invert the address update request signal A to the mother board  2 . Due to this, the updating of the address table at the mother board  2  is confirmed.  
         [0096]     D3. After notifying the signal A, wait for the wait time (T. WAIT) corresponding to the time for the mother board  2  to recognize the address table.  
         [0097]     D4. Change the table preparation flag from off to on and shift the routine to normal processing. Note that while the table preparation flag is off, repeat the processing for returning dummy data (0) to the RAM measurement device  14  every predetermined period.  
         [0098]     Details of the normal processing will be explained next.  
         [0099]     When a monitor request is received from the RAM measurement device  14  after the address table preparation processing is finished, the processing of the following E1 and E2 is performed.  
         [0100]     E1. Fetch the address from the received monitor request.  
         [0101]     E2. Search through the address table of the range shown by the table counter to see whether it has the data of the fetched address.  
         [0102]     When the same address is detected, the processing of the next F1 to F3 is performed. When the same address is not detected, it is judged that the address has been updated, so the processing of the next G1 to G3 is performed.  
         [0103]     F1. Extract corresponding data (4-byte fixed length). Here, the data is written from the mother board  2  side.  
         [0104]     F2. Fetch the data covered from the 4-byte fixed length data based on the lower 2-bit information of the monitor request address and data size of the request from the RAM measurement device  14 . Due to this, data of the requested byte length set at the RAM measurement device  14  is taken out.  
         [0105]     F3. Send the extracted data to the RAM measurement device  14 .  
         [0106]     G1. Initialize the address table of the RAAM measurement board  13  (table counter→0).  
         [0107]     G2. Return the dummy data (0) to the RAM measurement device  14 .  
         [0108]     G3. Turn off the table preparation flag and shift to address table preparation processing.  
         [0109]      FIG. 8  will be used to explain the RAM monitor processing in the mother board  2 .  
         [0110]     If sending the address update request signal A ( FIG. 3 ) from the RAM measurement board  13 , the initialization is started.  
         [0111]     The initialization resets the table counter of the address table  20  of the mother board  2  to 0.  
         [0112]     When the initialization is completed, the normal processing is shifted to. The normal processing performs the processing H1 and H2.  
         [0113]     H1. Read the address update request signal A, compare the previous value data, and check for inversion. When inverted, perform the following J1 and J2 and when not inverted, do not perform processing.  
         [0114]     J1. Update value of address update request signal A to currently received value.  
         [0115]     J2. Read address table  19  from common memory  16  and copy on to internal RAM  1 . At this time, read address counter value and read data of amount of size shown by count.  
         [0116]     H2. Check the table counter and perform processing of next K1 to K3 based on check results.  
         [0117]     K1. When the counter value is 0, do not perform processing.  
         [0118]     K2. When the counter value is the table size or greater, the system is abnormal, so perform failsafe processing and initialize address table  19  (table counter →0).  
         [0119]     K3. When other than K1 and K2, perform next L1 and L2.  
         [0120]     L1. Read address of range indicated by address counter and store data in address table  20 . This processing is performed when updating address table.  
         [0121]     L2. Write data value of address table  20  of amount of size indicated by address counter in address table  19  of RAM measurement board  13 . As explained above, the data size is fixed at 4 bytes.  
         [0122]     (RAM Write Function)  
         [0123]     For the RAM write function as well, the timing of processing by the RAM measurement board  13  is divided as shown in  FIG. 3 . The content of the processing is as shown in  FIG. 4 . This point has already been explained, so here overlapping explanations will be omitted.  
         [0124]     In  FIG. 3 , at the time of a RAM write operation, the control signal A is not used. The control signals B and C and the INIT signal are used. The control signal B becomes the write request signal from the RAM measurement board  13  to the mother board  2  (hereinafter “write request signal B”), while the control signal C becomes the write completion signal from the mother board  2  to the RAM measurement board  13  (hereinafter “write completion signal C”).  
         [0125]      FIG. 9  shows the structure of the RAM write address table  21 .  
         [0126]     The address table  21  is for write use and is written with data one bit at a time, so the table becomes only one channel. Further, the content becomes the write address, data size, and write data.  
         [0127]     As shown in  FIG. 10 , the address table  21  is stored in the common memory  16 . At the time of a RAM data write operation, a write request from the RAM measurement device  14  arrives before the write operation at the mother board  2  is ended. Therefore, the RAM measurement board  13  is provided with an internal buffer  22  and stores the buffer table  23 . The buffer table  23  is structured similar to the address table  21 , but stores a plurality of data, so has a predetermined buffer size (N. WBUF).  
         [0128]     When a write request from the RAM measurement device  14  is received, the write content is stored in the buffer table  23 . When the RAM data finishes being written at the mother board  2 , a write request is issued to the mother board  2  in accordance with the address table  21  and the next data is shifted from the buffer table  23  to the address table  21 .  
         [0129]      FIG. 11  will be used to explain the content of processing at the time of RAM write processing in the RAM measurement board  13 .  
         [0130]     The illustrated processing is started in the RAM measurement device  14  when an operation is performed for the write processing and the signal is received.  
         [0131]     In the initialization, the processing of the next M1 to M4 is performed.  
         [0132]     M1. Initialize address table  21  and buffer table  23 .  
         [0133]     M2. Turn write completion flag off.  
         [0134]     M3. Initialize value (previous value) of write completion signal C.  
         [0135]     M4. Initially output write request signal B.  
         [0136]     In the normal processing, the processing of the following N1 and N2 is performed.  
         [0137]     N1. Fetch received RAM write content and add to buffer table  23 .  
         [0138]     N2. Read write completion signal C, compared previous value data, and check for inversion. If inverted, perform the following P1 to P3 while if not inverted, do not perform the processing.  
         [0139]     P1. Update the previous value data by the write completion signal C.  
         [0140]     P2. Set oldest data of buffer table  23  in address table  21 . This is performed by the FIFO.  
         [0141]     P3. Output the write request signal B inverted.  
         [0142]     Further, as periodic processing (for example, every 1 ms), the following Q1 and Q2 are executed.  
         [0143]     Q1. Search the buffer table  23  to determine if there is an unprocessed request. If there is an unprocessed request, do not perform any processing.  
         [0144]     Q2. When there is an unprocessed request, compare the write completion signal C with the read previous value data and check for inversion. If inverted, perform the following R1 to R3 while if not inverted, do not perform the processing.  
         [0145]     R1. Update the previous value data in accordance with the write completion signal C.  
         [0146]     R2. Set the oldest data of the buffer table  23  in the address table  21  and delete the set data from the buffer table  23 .  
         [0147]     R3. Output the write request signal B inverted.  
         [0148]      FIG. 12  will be used to explain the content of processing at the time of RAM write processing in the mother board  2 .  
         [0149]     In the initialization, when receiving a write request signal B, the previous value data is initialized. Further, the write completion signal C is initially output.  
         [0150]     When the initialization is completed, normal processing is shifted to.  
         [0151]     In normal processing, the processing of the next S1 is performed after completion of execution of the control application.  
         [0152]     Note that no similar mirror table as the address table  19  of the common memory  16  is provided in the mother board  2  for the write operation.  
         [0153]     S1. Read the write request signal B, compare the previous value data, and check for inversion. If inverted, perform the processing of the next T1 to T3. If not inverted, no processing is performed.  
         [0154]     T1. Update the previous value data by the write request signal B.  
         [0155]     T2. Read the write content from the address table  19  of the common memory  16  and writes the data in accordance with the content.  
         [0156]     T3. Output the write completion signal C inverted.  
         [0157]     While the invention has been described with reference to specific embodiments chosen for purpose of illustration, it should be apparent that numerous modifications could be made thereto by those skilled in the art without departing from the basic concept and scope of the invention.