Abstract:
A self-biased phase-locked loop circuit includes a phase detector, first and second charge pumps, first and second loop filters, and a voltage-controlled oscillator (VCO). The phase detector is configured to measure a phase offset between two input signals, and to generate pulses corresponding to the phase offset. The first and second charge pumps are configured to provide charge corresponding to the pulses. The first and second loop filters are coupled to outputs of the first and second charge pumps, respectively. The filters operate to provide a control signal responsive to the charge. The VCO is configured to adjust its output frequency in response to the control signal. The second loop filter capacitor considerably improves the output clock jitter.

Description:
BACKGROUND 
     This disclosure relates to self-biased phase-locked loops (SBPLLs) and more specifically, to a low jitter design for a SBPLL. 
     Conventional phase-locked loop (PLL)  100 , shown in FIG. 1, generally includes a phase detector  102  for monitoring a phase difference between a reference signal and the feedback signal (frequency divided output signal of a voltage-controlled oscillator—VCO  108 ). The phase detector  102  generates an UP control signal  110  and a DOWN control signal  112  for a charge pump  114  to respectively charge and discharge a loop filter  116 . The loop control voltage  118  developed across the loop filter  116  determines the output frequency of the VCO  108 . The UP and DOWN control signals  110 ,  112  driving the charge pump  114  set the proper loop filter control voltage  118  at the input of the VCO to maintain a minimal phase error between the signals applied to the phase detector  102 . 
     PLLs are widely used in data communications, local area networks in computer applications, microprocessors and data storage application to control data transfers. However, the rising demand for high-speed applications requires reduced clock period. As a consequence, increased accuracy of the clock frequency is requested. The clock frequency accuracy is affected by jitter. One source of jitter is the noisy environment in which PLLs must function. Another important source of jitter is the so-called ‘reference-feed-through jitter’ or ‘quiet jitter’. Even when the PLL is locked there is still a small amount of phase error that determines a short pulse at the steering line of the VCO. In response to this short pulse, the VCO changes its phase. Since these pulses occur every reference cycle, the spectral component of the ‘quiet jitter’ is the reference frequency. With a shrinking tolerance for jitter in the decreasing period of the output clock, the design of low jitter PLLs has become very challenging. 
     Self-biased techniques have been proposed for low-jitter PLLs in “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” John G. Maneatis, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, pp. 1723-1732, November 1996. The paper proposes a self-biased PLL “SBPLL” circuit. 
     SUMMARY 
     A self-biased phase-locked loop circuit includes a phase detector, charge pumps, loop filters, and a voltage-controlled oscillator (VCO). The phase detector is configured to measure a phase offset between two input signals, and to generate pulses corresponding to the phase offset. The first and second charge pumps are configured to provide charge corresponding to the pulses. The first and second loop filters are coupled to outputs of the first and second charge pumps, respectively. The filters operate to provide a control signal responsive to the charge. The VCO is configured to adjust its output frequency and phase in response to the control signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Different aspects of the disclosure will be described in reference to the accompanying drawings wherein: 
     FIG. 1 is a block diagram of a conventional phase-locked loop; 
     FIG. 2 is a simplified block diagram of current SBPLL having a bias generator; 
     FIG. 3 is a detailed diagram of the bias generator; 
     FIG. 4 is a block diagram of an improved SBPLL design; 
     FIG. 5 shows one example of a VCO timing jitter present in the current SBPLL design; 
     FIG. 6 shows one example of the VCO timing jitter present in the improved SBPLL design; and 
     FIG. 7 is a block diagram of a computer system including an improved SBPLL. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2 shows a simplified block diagram of a self-biased PLL (SBPLL) circuit having a bias generator  210 . The SBPLL further includes a phase detector  202 , charge pumps  204 ,  206 , a loop filter  208 , a voltage-controlled oscillator (VCO)  212 , and a frequency divider  228 . The bias generator  210  generates two bias voltages, V BN    226  and V BP    224 . V BN    226  controls the VCO  212  and the charge pumps  204 ,  206  to enable the self-biasing technique while V BP    224  is the control voltage of the VCO  212 . 
     The phase detector  202  uses inputs F ref    214  and F in    216 , and outputs UP  218  and DN  220 . The phase detector  202  measures the phase difference between the two inputs  214 ,  216  and outputs a pulse having a width substantially equal to the difference amount. The pulse is sent to the UP signal  218  if F ref  leads F in  and is sent to the DN signal  220  if F ref  lags F in . The outputs  218 ,  220  of the phase detector  202  are inputs to charge pumps  204 ,  206 . 
     Each charge pump uses an UP input to produce a negative current pulse at the output of charge pump module  204 . It uses a DN input to produce a positive current pulse at the output of charge pump module  204 . The output  222  of the charge pump  204  drives a loop filter  208 , and becomes a bias generator  210  control line, V cntl . The output of the charge pump  206  is coupled to the V BP  output  224  from the bias generator  210 , and serves as an input to the VCO  212 . 
     The loop filter  208  includes a capacitor that acts as a low pass filter. One terminal of the capacitor is connected to a supply voltage, V CC . The other terminal is connected to V cntl . The capacitor in the loop filter  208  integrates the current generated by the charge pump  204  to smooth the V cntl    222 . The filter  208  also provides stability to the operation of the SBPLL  200  by suppressing high frequency noise. 
     The loop filter  208  outputs a filtered voltage to the V cntl  input of the bias generator  210 . The bias generator  210  receives V cntl  and converts it to the proper bias (V BN )  226  for controlling current sources in the VCO  212  and in the charge pumps  204 ,  206 . The bias generator  210  together with the charge pump  206  also generates V BP    224 . 
     A detailed diagram of the bias generator  210 , along with the charge pump  206 , is shown in FIG.  3 . The bias generator  210  includes an N-bias generator  300  and a P-bias generator  302 . 
     The N-bias generator  300  receives the control voltage, V cntl    222 , and generates a bias voltage, V BN    226 . The bias voltage V BN    226  properly biases current sources in the VCO  212  and in the charge pumps  204 ,  206 . 
     The P-bias generator  302  receives the V BN  bias voltage  226  and generates a VCO steering voltage, V BP    224 . Transistors  304 ,  306  implement the loop filter resistor. The transistor  308  current, controlled by V BN , sets the resistance value. 
     The output resistance of the current sources in the charge pump  206 , in conjunction with transistors  304 ,  306 , produces an equivalent loop filter dynamic resistance on the VCO steering line, V BP    224 . Hence, when the loop is locked, the charge pump  206  produces current pulses that generate voltage pulses on the VCO steering line  224 . The amplitudes of these voltage pulses are a product of the charge pump current and the dynamic loop filter resistance. Further, these pulses modulate the VCO output phase at the reference frequency, F ref , and cause VCO output jitter. The pulses also cause the charge pump current to decrease, and momentarily reduce a phase detector gain. These results cause loop bandwidth and damping factor to momentarily drop. 
     A block diagram of another embodiment  400  is shown in FIG.  4 . The new design  400  includes an additional loop filter capacitor C 2 , at the output of the charge pump  206 . Adding the capacitor C 2  changes the SBPLL from second order to a third order SBPLL. The capacitor in the filter  402  prevents the VCO control voltage  224  from changing too rapidly, by integrating the charge pump current pulses. The resultant voltage pulse amplitudes at the VCO voltage steering line  224  are significantly reduced. Hence, the charge pump gain becomes stable over time. Further, the output jitter performance is significantly improved. 
     A VCO timing jitter that can be present in the SBPLL design  200  is illustrated in FIG.  5 . The timing jitter is based on a SBPLL chip running at 800 MHz. The operating frequency of the SBPLL chip running at 800 MHz translates into 1.25 nano-seconds or 1250 pico-seconds of the worst-case speed path. 
     The peak-to-peak timing jitter has been measured to be approximately 57 pico-seconds. This means that, in some clock cycles, the available propagation time for the logic paths is lower by approximately 57 pico-seconds (1250−57=1193 pico-seconds). Thus, in order to provide enough propagation time for the logic path, the clock cycle must be extended by that amount to 1307 pico-seconds (1250+57). The clock frequency in this case changes to about 765 MHz instead of the 800 MHz. Therefore, the maximum chip operating frequency decreases by about 35 MHz. 
     FIG. 6 illustrates the VCO timing jitter present in the third-order SBPLL design  400  shown in FIG.  4 . The timing jitter is again based on a chip running at 800 MHz. However, the peak-to-peak timing jitter is now measured to be about 7 pico-seconds. Thus, in order to provide enough propagation time for the logic paths with the new SBPLL design, the clock cycle must be extended 7 pico-seconds to 1257 pico-seconds. The clock frequency in this case changes to about 795 MHz instead of the 800 MHz. Therefore, the maximum chip operating frequency decreases only by about 5 MHz. This represents an improvement in the maximum chip frequency of 30 MHz over the SBPLL design  200 . 
     In order to obtain improvement in the maximum chip frequency, proper sizing of the capacitor C 2  with respect to capacitor C 1  is important. Proper sizing of the capacitor C 2  enables optimal tradeoff between loop stability and process variations. In a preferred embodiment, the capacitor C 2  is between approximately 1% and 2% of the main capacitor C 1 . Beyond about 2%, the timing jitter improvement decreases, yet the increase in the physical area occupied by the capacitor increases significantly. Also, with higher C 2  values, the loop stability may be affected. 
     FIG. 7 is a block diagram of a computer system  700 . In one embodiment, the computer system  700  includes a SBPLL  400  having a bias generator and a properly sized loop filter capacitor at the VCO steering line. The capacitor keeps the timing jitter of the SBPLL  400  low and improves the maximum operating frequency of the chip. 
     The SBPLL  400  receives a bus clock  702  from a bus system  704 . A phase detector in the SBPLL  400  compares the bus clock signal  702  with a feedback frequency from the VCO. The feedback frequency locks the output of the VCO to the exact multiple frequency of the bus clock  702 . 
     The output of the SBPLL  708  is used as a clock source for a processor  710 . The processor  710  is then able to interface with other components of the computer system  700 , such as a memory  712 , display  714 , and I/O devices  716 . Synchronized clocks in the processor  710  and the bus system  704  enable data in the processor  710 , the memory  712 , the display  714  and the I/O devices  716  to be transferred and shared across the bus system  704  with minimal data latency or data loss. 
     Other embodiments are within the scope of the following claims. For example, additional loop filter capacitors can be configured to provide filtering at the VCO control and steering lines. Further, the self-biased phase-locked loop can be used in applications other than the computer system described in FIG.  7 . For example, they can be used in data communication systems, local area networks, and data storage applications.