Abstract:
A digital-to-analog converter generates a monotonic sequence of reference voltages and selects an arbitrary pair of reference voltages, adjacent in the monotonic sequence. One of the selected reference voltages is supplied through a resistor and a switching device, connected in series, to the output terminal of the converter. The other selected reference voltage is supplied through another resistor and another switching device, connected in series,.to the same output terminal. This arrangement saves space, and enables variations in the output voltage levels to-be kept within tolerance by use of resistors with sufficiently high resistance values.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a digital-to-analog converter useful in, for example, a circuit that drives a liquid crystal display.  
         [0003]     2. Description of the Related Art  
         [0004]     With the recent increase in the size of liquid crystal display devices, various needs have arisen for improved performance in-their driving circuits. One need is for a gradation scale with more gradation levels, especially for the display of more vivid colors. The current state of the art is a liquid crystal display device that can reproduce over one billion different colors by using ten bits of data (1024 gradation levels) for each of the three primaries (red, green, blue). The increased number of gradation levels demands improved performance from the digital-to-analog (D/A).converters that convert digital signals received from an outside source to analog signals. D/A converters of the resistor string type are often employed.  
         [0005]     The simplest resistor string D/A converters have the structure shown in  FIG. 3 , which converts two-bit digital data (bits  1 D and  2 D and their complementary values  1 DB and  2 DB), and  FIG. 4 , which converts three-bit digital data (bits  1 D- 3 D and their complementary values  1 DB- 3 DB). An output decoder comprising transistor switches selects one of the voltage levels (V 0 , V 1 , V 2 , . . . ) generated by the resistor string (R 1 , R 2 , . . . ) for output (V out ). With this circuit configuration, each time the number of bits increases by one, the number of resistors and transistors substantially doubles, doubling the circuit area.  
         [0006]     Japanese Patent Application Publication No. 2000-183747 (U.S. Pat. No. 6,373,419) describes an alternative circuit configuration with fewer resistors and transistors, but the output decoder requires an averaging voltage-follower amplifier with two parallel differential input stages, an arrangement that consumes an undesirably large amount of current.  
         [0007]     Japanese Patent Application Publication No. 62-024713 describes a different circuit configuration in which the number of transistors and resistors increases more slowly with the number of bits, but this configuration tends to produce voltage level fluctuations when several hundred output decoders are connected in parallel to the same resistor string, as is the case in circuits for driving large liquid crystal displays.  
       SUMMARY OF THE INVENTION  
       [0008]     An object of the present invention is to provide a D/A converter that has a reduced number of circuit elements, does not consume excessive current, and can provide stable output voltage levels.  
         [0009]     The invented D/A converter includes a voltage generator that uses voltage drops in resistors to generate a plurality of reference voltages forming a monotonic sequence of voltage levels. A first control circuit and a second control circuit select two of the reference voltages, mutually adjacent in the monotonic sequence, as a first output and a second output. A third control circuit generates a third output from the first and second outputs. The third control circuit includes a first resistor and a first switching device connected in series between the first output and the third output, and a second resistor and a second switching device connected in series between the second output and the third output.  
         [0010]     Compared with the simplest conventional type of resistor string D/A converter, the invented D/A converter takes up less space because it requires fewer resistors and transistors. Moreover, the invented D/A converter does not require amplifiers that consume excessive current, and its output voltage fluctuations can be reduced to an arbitrary level by suitable selection of the resistance values of the resistors in the third control circuit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     In the attached drawings:  
         [0012]      FIG. 1  is a circuit diagram of a D/A converter illustrating a first embodiment of the present invention;  
         [0013]      FIG. 2  is a circuit diagram of a D/A converter illustrating a second embodiment;  
         [0014]      FIG. 3  is a circuit diagram of a conventional two-bit D/A converter; and  
         [0015]      FIG. 4  is a circuit diagram of a conventional three-bit D/A converter. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]     Embodiments of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters.  
       First Embodiment  
       [0017]     The first embodiment is a D/A converter that converts n-bit digital data to an analog signal. Referring to  FIG. 1 , the D/A converter  100  comprises a voltage generator  101  and three control circuits  102 ,  103 ,  104 . The illustrated circuit converts three-bit digital data comprising bits  1 D,  2 D,  3 D and their complementary values  1 DB,  2 DB,  3 DB.  
         [0018]     The voltage generator  101  is a string of resistors (R 0 , R 1 , R 2 , R 3 ) connected in series, receiving a voltage V 0  from a power source (not shown) and generating successively lower voltages (V 1  to V 4 ) by resistive voltage drops. Voltages V 0  to V 4  will be referred to below as reference voltages. In general, if n is the number of bits of digital input data, the voltage generator  101  in the first embodiment has 2 n-1  resistors generating 2 n-1 +1 reference voltages.  
         [0019]     The first control circuit  102  uses the upper two bits of input data ( 2 D,  3 D and their complementary values  2 DB and  3 DB) to select one of the even-numbered reference voltages (V 0 , V 2 , or V 4 ) as a first output V out1 . In general, the upper n-1 bits of input data are used to select an even-numbered one of the 2 n-1 +1 reference voltages generated by the voltage generator  101 .  
         [0020]     The second control circuit  103  uses the most significant bit ( 3 D and its complementary value  3 DB) to select an odd-numbered reference voltage (V 1  or V 3 ) adjacent to the even-numbered reference voltage selected by the first control-circuit  102 , and outputs it as a second output V out2 . In general, the upper n-2 bits are used to select an odd-numbered one of the 2 n-1 +1 reference voltages generated by the voltage generator  101 .  
         [0021]     The first control circuit  102  and second control circuit  103  may be any types of control circuits that can select two mutually adjacent reference voltages. They are not limited to the circuit configurations shown in  FIG. 1 .  
         [0022]     The first and second outputs V out1  and V out2  are supplied as first and second inputs V in1  and V in2  to the third control circuit  104 , which generates a third output V out3 . In the third control circuit  104 , a first resistor R 11  and first switch S 11  are connected in series between the first input V in1  and third output V out3 . Similarly, a second resistor R 12  and second switch S 12  are connected in series between the second input V in2  and third output V out3 . The first and second switches S 11 , S 12  are controlled by the least significant bit of the digital input data ( 1 D and its complementary value  1 DB, not shown). The first and second resistors R 11  and R 12  have identical resistance values.  
         [0023]     Here and in the description of the second embodiment, the term ‘identical’ means that the two resistance values are the same to within a tolerance that allows for normal fabrication process variations. As the number of voltage gradations increases, the voltage difference between the first and second outputs V out1  and V out2  decreases, so the error caused by process variations can be tolerated.  
         [0024]     The switching circuit  105  has first and second input terminals that receive the outputs V out1  and V out2  from the first and second control circuits  102 ,  103 ; first and second output terminals that supply the first and second input voltages V in1  and V in2  to the third control circuit  104 ; and switches S 13 , S 14  that can connect either input terminal to either output terminal. The switches S 13 , S 14  are controlled by the second least significant bit ( 2 D and its complementary value  2 DB) of the digital input signal.  
         [0025]     The switches S 11 , S 12 , S 13 , S 14  in the third control circuit  104  and switching circuit  105  are analog switching devices comprising metal-oxide-semiconductor (MOS) transistors (not shown).  
         [0026]     The values of the first and second resistors R 11  and R 12  are determined by taking into account the on-resistances of the MOS transistors in the first and second control circuits  102  and  103  and the input capacitance of the amplifier (not shown) connected to the third output V out3 .  
         [0027]     The first and second control circuits  102  and  103  obtain the first and second outputs V out1  and V out2  by selecting a path that leads through, in each case, just n-1 p-channel. MOS transistors. The total on-resistance of the selected MOS transistors in the first and second control circuits  102  and  103  is therefore the sum of the on-resistances of n-1 MOS transistors. In the present example (n=3), the total on-resistance is the sum of the on-resistances of two MOS transistors. To provide the same total on-resistance as in the first control circuit  102 , the second control circuit  103  includes transistors that are kept permanently turned on by holding their gate electrodes at the low logic level.  
         [0028]     The sizes of the MOS transistors controlled by bits  1 D or  1 DB,  2 D or  2 DB, and  3 D or  3 DB increase in this order, the corresponding on-resistances decreasing accordingly.  
         [0029]     In a D/A converter used in, for example, a liquid crystal display driver, some two hundred output channels, each including the control circuits  102 ,  103 ,  104  shown in  FIG. 1 , may be connected in parallel to a single resistor string  101 . To hold the voltage error caused by variation of the reference voltages generated by the resistor string under varying output conditions to less than one percent (1%), the resistance RC of resistors R 11  and R 12  must satisfy the condition 100·X·RA≦RB+RC, where X is the number of channels, RA is the resistance of a resistor in the resistor string, and RB is the total on-resistance of the MOS transistors on the selected path in the first control circuit  102  or second control circuit  103 .  
         [0030]     When switches S 11  and S 12  are both turned on, the first and second control circuits  102 ,  103  and first and second resistors R 11  and R 12  form a series circuit connected in parallel with one of the string resistors, so the resistance RC of the first and second resistors R 11  and R 12  must also satisfy the condition 100·X·RA≦2 (RB+RC). When there are two hundred channels (X=200), for example, the total series resistance of the first and second resistors R 11  and R 12  and the first and second control circuits should be about ten thousand times higher than the resistance RA of a resistor in the resistor string.  
         [0031]     If operating speed is taken into account, the input capacitance of the amplifier (not-shown) connected to the output stage of the D/A converter needs to be considered. If the input capacitance of the amplifier is denoted C, the rise time (the time taken for the input voltage to reach 90% of the desired value) is (ln10)(RB+RC)C, where ln10 denotes the natural logarithm of ten. The combined series resistance of the first control circuit and first resistor must therefore be equal to or less than T rise /(C·ln10), where T rise  is the maximum allowable rise time. If the maximum allowable rise time is one microsecond (1 μs), for example, and C is expressed in microfarads (μF), the necessary condition becomes 1≧(ln10)(RB+RC)C; that is, the required operating speed is obtained if the resistance values RB and RC satisfy the condition: 
 
 RB+RC≦ 1/( C ·ln10) 
 
         [0032]     The allowable variation of the reference voltages generated by the voltage generator  101  differs depending on the circuit specifications. If the allowable variation is Y percent, then the resistance RC of resistors R 11  and R 12  should-be selected so that the series resistance RB+RC is within the following range: 
 
(50/ Y )· X·RA≦RB+RC≦ 1/( C ·ln10) 
 
         [0033]     Next the operation-of the first embodiment will be described.  
         [0034]     The first control circuit  102  selects an even-numbered reference voltage as the first output voltage V out1 , according to digital input data  2 D,  2 DB,  3 D, and  3 DB. The second control circuit  103  selects an odd-numbered reference voltage as the second output voltage V out2 , according to digital input data  3 D and  3 DB. The first control circuit  102  and second control circuit  103  are configured so as to assure that the selected first and second outputs V out1  and Vou2 are mutually adjacent in the series of reference voltages generated by the voltage generator  101 .  
         [0035]     When the least significant bit of the input data is zero ( 1 D=0), the first switch S 11  in the third control circuit  104  is turned off, the second switch S 12  is turned on, and the second input V in2  is output as the third output V out3 . When the least significant bit is one ( 1 D=1), both the first and second switches S 11  and S 12  are turned on. Since the total on-resistances of the MOS transistors on the selected paths in the first and second control circuits are the same and the first and second resistors R 11  and R 12  have mutually identical resistances, a voltage halfway between the first and second inputs V in1  and V in2  is output as the third output V out3 .  
         [0036]     When the middle bit of the input data is zero ( 2 D=0), switches S 13  are turned on and switches S 14  are turned off in the switching circuit  105 , connecting the first output V out1  to the first input V in1  and the second output V out2  to the second input V in2 . When the middle bit of the input data is one ( 2 D=1), switches S 13  are turned off and switches S 14  are turned on, connecting the first output V out1  to the second input V in2  and the second output V out2  to the first input V in1 . This switchover causes the third output V out3  to increase monotonically from V 4  to (V 0 +V 1 )/2 as the digital input increases from ‘000’ to ‘111’, as shown in Table 1.  
                                   TABLE 1                                   Input   V out1     V out2     V out3                             111   V 0     V 1     (V 0  + V 1 )/2           110   V 0     V 1     V 1             101   V 2     V 1     (V 1  + V 2 )/2           100   V 2     V 1     V 2             011   V 2     V 3     (V 2  + V 3 )/2           010   V 2     V 3     V 3             001   V 4     V 3     (V 3  + V 4 )/2           000   V 4     V 3     V 4                        
 
         [0037]     As Table 1 shows, the first embodiment produces the same number of output voltage gradations as the conventional D/A converter shown in  FIG. 4 , using a resistor string with only about half as many resistors. More precisely, the first embodiment requires a string of 2 n-1  resistors, as noted above, whereas the conventional circuits shown in  FIGS. 3 and 4  require a string of 2 n-1  resistors.  
         [0038]     When the first embodiment is adapted to convert n-bit input data (n&gt;3), the first and second-control circuits  102 ,  103  require additional transistors, but the switching circuit  105  and third control circuit  204  do not. For large numbers of bits (n=10, for example), the first embodiment requires fewer transistors in all than a conventional D/A converter of the type shown in  FIGS. 3 and 4 , and also requires fewer resistors in all, even if there are two hundred output channels with two resistors R 11 , R 12  apiece in addition to the single resistor string in the voltage generator  101 .  
         [0039]     The above advantages become increasingly pronounced as the number of bits increases.  
         [0040]     In addition, the resistance values in the third control circuit  104  can be selected to hold variations in the output voltage levels to within a given tolerance. These-resistance values can also be selected to obtain a given operating speed. Accordingly, besides saving space, the first embodiment can easily be designed to satisfy a given set of circuit specifications.  
         [0041]     These advantages are moreover obtained without the use of an averaging voltage-follower amplifier with parallel differential input stages, thus without the consumption of extra current by the amplifier.  
       Second Embodiment  
       [0042]     The second embodiment is a modification of the first embodiment that operates as an (n+1)-bit D/A converter. In the example shown in  FIG. 2 , the second embodiment is a four-bit D/A converter receiving digital data bits  0 D,  1 D,  2 D,  3 D, and their complementary values  0 DB,  1 DB,  2 DB,  3 DB. The second embodiment has the same voltage generator  101 , first control circuit  102 , second control circuit  103 , and switching circuit  105  as the first embodiment, but has a modified third control circuit  204 , described below.  
         [0043]     As in the first embodiment, the third control circuit  204  connects the first input V in1  to the third output V out3  through a first resistor R 11  and first switch S 11 , and connects the second input V in2  to the third output V out3  through a second resistor R 12  and second switch S 12 . In addition, the third control circuit  204  connects a node disposed between the first resistor R 11  and first switch S 11  and a node disposed between the second resistor R 12  and second switch S 12  through a series circuit including a third resistor R 13 , a third switch  206 , a fourth switch  207 , and a fourth resistor R 14 . The third and fourth switches  206 ,  207  comprise the same type of p-channel MOS transistors as used in the first and second control circuits  102 ,  103 , having the same dimensions and fabrication process conditions, but the gate electrodes of the p-channel MOS transistors in the third and fourth switches  206 ,  207 ,receive the complementary value  0 DB of the least significant bit of the input data.  
         [0044]     The first switch S 11  is controlled by the second least significant bit  1 D and its complementary value  1 DB (not shown). The second switch S 12  is controlled by the two least significant bits  0 D,  1 D and their complementary values  0 DB,  1 DB. The switches S 13 , S 14  in the switching circuit  105  are again controlled by bit  2 D, which is now the third least significant bit, and its complementary value  2 DB.  
         [0045]     The operation of the second embodiment will now be described under the assumption that the on-resistance values of the p-MOS transistors in the third and fourth switches  206 ,  207  are negligibly small in comparison with the resistances of the third and fourth resistors R 13 , R 14 .  
         [0046]     When  1 D=0 and  0 D=0 ( 0 DB=1), the second switch S 12  is turned on and the first, third, and fourth switches S 11 ,  206 , and  207  are turned off, so the second input V in2  is output directly as the third output V out3 .  
         [0047]     When  1 D=0 and  0 D=1 ( 0 DB=0), the second, third, and fourth switches S 12 ,  206 , and  207  are turned on and the first switch S 11  is turned off., so the third output V out3  is a voltage higher than the second input voltage V in2  by one quarter of the voltage difference between the first and second inputs V in1  and V in2 .  
         [0048]     When  1 D=1 and  0 D=0, the first and second switches S 11  and S 12  are turned on and the third and fourth switches  206  and  207  are turned off, so the third output V out3  is a voltage halfway between the first and second input voltages V in1  and V in2 .  
         [0049]     When  1 D=1 and  0 D=1, the first, third, and fourth switches S 11 ,  206 , and  207  are turned on and the second switch. S 12  is turned off, so the third output V out3  is a voltage higher than the second input voltage V in2  by three-quarters of the voltage difference between the first and second inputs V in1  and V in2 .  
         [0050]     The output voltages V out1 , V out2 , V out3  have the values shown in Table 2.  
                                   TABLE 2                                   Input   V out1     V out2     V out3                             1111   V 0     V 1     (3V0 + V 1 )/4           1110   V 0     V 1     (V 0  + V 1 )/2           1101   V 0     V 1     (V 0  + 3V1)/4           1100   V 0     V 1     V 1             1011   V 2     V 1     (3V1 + V 2 )/4           1010   V 2     V 1     (V 1  + V 2 )/2           1001   V 2     V 1     (V 1  + 3V2)/4           1000   V 2     V 1     V 2             0111   V 2     V 3     (3V2 + V 3 )/4           0110   V 2     V 3     (V 2  + V 3 )/2           0101   V 2     V 3     (V 2  + 3V 3 )/4           0100   V 2     V 3     V 3             0010   V 4     V 3     (3V 3  + V 4 )/4           0011   V 4     V 3     (V 3  + V 4 )/2           0001   V 4     V 3     (V 3  + 3V4)/4           0000   V 4     V 3     V 4                        
 
         [0051]     Controlling the third control circuit  204  by the lower two bits of the digital input data  1 D and  0 D makes it possible to generate three additional voltage levels from the first and second inputs V in1  and V in2 , thereby obtaining five voltage levels in all from two adjacent reference voltages generated by the resistor string in the voltage generator  101 .  
         [0052]     Since the third and fourth switches that are inserted in the third control circuit  204  to increase the number of voltage gradations use the same type of MOS transistors as in the first and second control circuits  102  and  103 , they have the same on-resistance, back bias, and other characteristics. This uniformity of characteristics improves the accuracy of the output voltage levels. In particular, the voltage difference between two adjacent reference voltages output by the voltage generator  101  is divided into four equal parts because the combined resistance of the first control circuit and resistor R 11  (or R 12 ), the combined resistance of the second control circuit and resistor R 12  (or R 11 ), the combined resistance of the third switch and resistor R 13 , and the combined resistance of the fourth switch and resistor R 14  are all equal.  
         [0053]     Like the first embodiment, the second embodiment can be extended to an arbitrary number (n) of data bits by modifying the first and second control circuits. 102 ,  103 , without changing the topology of the switching circuit  105  and third control circuit  204 .  
         [0054]     Compared with the first embodiment, the second embodiment obtains twice as many output voltage levels from only a slightly larger number of transistors and resistors, adding only two resistors and four transistors to the third control circuit  204 .  
         [0055]     Compared with the conventional technology illustrated in  FIGS. 3 and 4 , the second embodiment provides substantial space savings. For n-bit input data, the second embodiment requires a resistor string with only 2 n-2  resistors, one-fourth the conventional number. For large numbers of bits (n=10, for example), the necessary number of transistors is less than half the conventional number. The amount of space saved increases with the number of bits.  
         [0056]     Like the first embodiment, the second embodiment can be easily designed to reduce voltage error to a specified level, and to provide a specified operating speed, and does not require amplifiers with high current consumption.  
         [0057]     The invention is not limited to the embodiments described above. For example, by adding further resistors and transistors to the third control circuit, it is possible to output seven voltage levels between each mutually adjacent pair of reference voltages produced by the voltage generator  101 . More generally, the above embodiments can be described as producing 2 n  output voltage levels from a first string of 2 n-m  resistors having a first resistance and a second string of 2 m  resistors having a second resistance, where m and n are arbitrary positive integers (0&lt;m&lt;n) and the second resistance is higher than the first resistance, by switchably connecting the second string of resistors in parallel with a selectable one of the resistors in the first string, and selecting one of the voltage levels produced by the second string of resistors.  
         [0058]     The multiple transistors with gate electrodes held at the low logic level in the second control circuit  103  can be replaced by a single transistor of the same type disposed on the single signal line leading to the V out2  output terminal.  
         [0059]     The switching circuit  105  can be omitted: an equivalent function can be provided by suitable control of the first and second switches S 11 , S 12  in the third control circuit. In the first embodiment, for example, with the first input V in1  connected to the first output V out1  and the second input V in2  connected to the second output V out2 , the first switch may be turned on whenever either bit  1 D or bit  2 DB is one ( 1 D=1 or  2 DB=1), the second switch being turned on whenever either bit  1 D or bit  2 D is one ( 1 D=1 or  2 D=1).  
         [0060]     The third and fourth resistors R 13 , R 14  in the second embodiment can be replaced by a single resistor with a resistance value equal to the combined series resistance of the third and fourth resistors. Similarly, the third and fourth switches  206 ,  207  can be replaced by a single switch having an on-resistance equal to the combined on-resistances of the third and fourth switches.  
         [0061]     The resistors may be resistance elements of any type.  
         [0062]     Those skilled in the art will recognize that further variations are possible within the scope of invention, which is defined by the appended claims.