Abstract:
A method of amplifying an analog low-frequency signal, and a switching amplifier implementing the method, wherein the maximum amplifiable voltage of the analog input signal is divided up into as many voltage bands as there are switching stages provided in the switching amplifier, and one switching stage is associated with each voltage band. Thereby the number of switching stages actuated and their switched-on period may be modulated in dependence upon the amplitude. In this way it is possible to reduce considerably the total number of switching processes during one period of the low-frequency input signal and the losses connected with each switching process.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a method of amplifying an analog low-frequency signal by a switching amplifier which contains a number of switching stages which can be actuated independently of one another and the outputs from which are connected to a lowpass filter. 
     2. Description of the Prior Art 
     The amplification of analog signals by a switching amplifier may, in spite of the necessary conversion of the analog control signal into a control signal in pulse form and the conversion of the amplified pulsed output signal back into an analog output signal, be advantageous because all of the steps of the method may be performed with modern solid-state components, which in general permits a more compact construction and a longer working life of the amplifier as well as a considerable reduction in the stray power. 
     In the case of the methods known hitherto the switch members in the switching stages are actuated by pulse trains, the pulses in which exhibit a constant repetition rate and are width-modulated in accordance with the converted analog signal. Preferably two pulse trains are generated, the pulses in which are shifted in phase by 180°. 
     Such a switching amplifier is described, for example, in British Pat. No. 1,248,209 (Plessey Co. Ltd.). In the case of this amplifier the amplitude-modulated analog input signal is converted into a pair of pulse trains having width-modulated pulses shifted in phase by 180°. Each pulse train controls one of the two switching transistors which are connected to the ends of the primary winding of a pulse transformer. The center tapping of this primary winding is connected to a source of supply voltage so that the pulse transformer is excited in push-pull. The secondary winding of the transformer is connected via a bridge rectifier to a lowpass filter at the output from which appears an analog signal which corresponds with the amplified input signal. 
     The output power from this switching amplifier is limited by the power which can be transformed by the one pulse transformer, and during amplification the pulses are deformed, wherefore the possibilities of employment of this switching amplifier are restricted. 
     That is why a switching amplifier has already been proposed (Swiss Patent Application No. 7307/79) which contains a plurality of switching stages for raising the switching power. In the case of this switching amplifier the analog input signal is converted into at least one pair of pulse trains, the two pulse trains shifted in phase by 180° consisting of width-modulated pulses of constant repetition rate. Each of the switching stages contains two switching channels independent of one another, and each switching channel contains one pulse transformer, the primary winding of which is connected to one switch member. The one pulse train of the pair of pulse trains is provided for the control of the switch members in the first switching channels of the switching stages and the other pulse train is provided for the control of the switch members in the second switching channels. The secondary windings of all of the pulse transformers are connected in series for summing up the pulses transformed. The one output from each secondary winding is connected via a rectifier to the series lead and a further rectifier is provided in the series lead between the connections of the two outputs from each secondary winding. 
     In the case of a practically tested embodiment of this switching amplifier the switch members in 48 switching stages were controlled by each pulse train. The supply voltage for the primary windings of the pulse transformers was 500 volts and the transformation ratio selected as 1:1.2, so that at the end of the series circuit of the secondary windings of the transformers, amplified pulses were obtained having a peak voltage of up to 28 kV. 
     The insulation required between the secondary and primary windings of the pulse transformers forms at the aforesaid peak voltage an undesirable capacitance which is charged up and discharged at each switching or transformation process. The reversal of charge is connected with a relatively high stray power and at high switching frequencies may even bring about a deformation of the pulse transformed and thereby a distortion of the amplified analog signal. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is therefore to create a method of amplification of an analog low-frequency signal in which the duration of switching-on of the switching stages is prolonged in each conversion period and in return the number of switching stages which have to be switched on is reduced. 
     In accordance with the invention this object is achieved by a method of the kind mentioned initially, wherein the permissible input voltage to the amplifier is divided up into a number of voltage bands of equal size and at least one switching stage is associated with each voltage band, and wherein at predetermined intervals of time the instantaneous value of the amplitude of the input signal is measured and the number of voltage bands is determined the sum of which is equal to this instantaneous value or less than it by less than one voltage band, and this sum is compared with the sum calculated in the same way in the case of the preceding measurement of the instantaneous value, after which a number of switching stages corresponding to the difference between these two sums is switched off or additionally switched on. 
     While in the case of the methods usual hitherto, in each conversation period all of the switching stages of the amplifier were switched by width-modulated control pulses, the method of the invention enables only a number of switching stages determined by the instantaneous value of the amplitude of the input signal to be switched on during an optimum period of time determined by the saturation of the transformer. The number of switching processes in each conversion period can thus be quite considerably reduced and thereby also the losses brought about by the switching processes and the deformations of the transformed pulse. 
     In a preferred embodiment of the method of the invention each voltage band is subdivided into a predetermined number of sub-bands, and upon measuring an instantaneous value which lies between two sums of the voltage bands, so that after determining the sum a remainder of amplitude is left, a further switching stage is pulse-duration modulated, ie. it is switched on with a time delay or switched off early, in doing which the ratio of the length of time switched on to the interval of time between successive measurements of the instantaneous value, is proportional to the ratio of the value of the remainder of amplitude to one voltage band. 
     This embodiment of the method, through the combination of the new modulation of the number of switching stages switched on during an optimum period of time with the additional pulse-duration modulation of at least one switching stage, permits a still more distortion-free amplification of the analog signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
     FIG. 1 is a block diagram of a switching amplifier according to the invention; 
     FIG. 2 is a timing chart illustrating one period of an analog input signal and the corresponding signal appearing at the series lead of the outputs from the switching stages and composed of signals in pulse form; 
     FIG. 3 is a block diagram of a tested embodiment of a low-frequency power amplifier; and 
     FIG. 4 is a timing chart illustrating one period of an analog input signal, the analog output signal appearing at the series lead from the amplifier channel outputs and composed of switching pulses, and the analog output signal appearing at the output from the filter. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, and more particularly to FIG. 1 thereof, the switching amplifier shown in FIG. 1 in the basic diagram contains an A/D converter 12, the input to which is connected to the input terminal 10 of the switching amplifier and the output from which is connected to the input of a store 14. At the output from the store a controllable roll-out circuit 16 is provided. The switching amplifier further contains a clock unit 17 which in the A/D converter determines the point in time of the conversion of the analog signal applied to the input terminal into a digital signal, the point in time of the storage of this digital signal in the store 14, and the point in time of the roll-out of the stored digital signals. The roll-out circuit exhibits a number of outputs each of which is connected to the switch member in a respective one of a number of switching stages of which in FIG. 1 only the three switching stages 18, 19 and 20 are shown. The outputs from the switching stages are connected to a series lead 21, the end of which is led of the input to a lowpass filter 22. The output from the lowpass filter is connected to the output terminal 23 of the power amplifier. 
     In order that each switching stage may be controlled by an associated control signal, the number of digital signals which can be generated by the A/D converter must be at least as great as the number of switching stages. FIG. 2 shows the range 31 of the maximum convertible analog signal, which is divided up into twelve voltage bands 311 to 322. With each of the voltage bands there is associated a digital signal, eg., one of the numerals 1 to 12. 
     For the description of the method of operation of the switching amplifier shown in FIG. 1 let it be assumed that the analog signal 33 shown in FIG. 2 is led to the input terminal 13 of the amplifier and thereby also to the input to the A/D converter 12. The converter controlled by the clock unit 17 scans at the points in time τ 0  to τ 9  the amplitude of the analog signal and generates a digital output signal which matches the number of voltage bands corresponding to the scanned instantaneous value of the amplitude. In the example shown, at the points in time τ 0  to τ 10  the digital output signals are 1, 4, 5, 5, 9, 10, 9, 4, 1, 0 and 1. These output signals are stored one after another in the store 14. Controlled again by the clock unit 17 the roll-out circuit 16 reads out the store and feeds the contents of the individual storage cells to the associated signal leads as control signals for the switch members of the switching stages. The output signals from the switching stages are superimposed in the series lead into the stepped signal 34 shown in FIG. 2, and in the lowpass filter 22 are re-formed into an amplified analog signal the time lapse of which largely corresponds to the analog signal at the input terminal of the amplifier. 
     Moreover it is to be understood that the matching between the analog signal 33 and the envelope of the signal 34 composed from the output signals from the switching stages superimposed in steps is the better the shorter the time intervals between successive scannings of the analog signal and the greater the number of the voltage bands in the maximum convertible analog range. In practice limits are set to these two requirements because the follow-up time of the A/D converter employed for the scanning of the analog value cannot be made arbitrarily small and the outlay for the amplification of the signals corresponding to the individual voltage bands has to be limited to a logical amount. 
     FIG. 3 shows the block diagram of a tested embodiment of a switching amplifier. In the case of the construction of this power amplifier it is assumed that for reaching the desired amplification 48 switching stages arranged side by side are necessary. For the independent actuation of these switching stages 48 control signal trains are necessary, which in accordance with the above statements with respect to FIGS. 1 and 2 requires dividing up of the maximum convertible analog signal into 48 voltage bands. In order to increase the accuracy in the determination of the scanned amplitude value an A/D converter 46 was employed which emits a 10-bit output signal, which corresponds to a dividing up of the maximum convertible analog value into 1024 digital values. Because the switching amplifier can process only 48 control signal trains, a divider circuit 47 is connected downstream of the A/D converter, which reduces the digital output signal from the converter by continuous subtraction of the quotient (1024:48), until the digital output signal is zero or corresponds to a remainder which is not further divisible. The divider circuit includes two outputs. At one output 48 appear the ordinal numbers of the subtractions performed one after another, at the other output 49 appears the remainder which may be left after the last subtraction. The ordinal numbers of the substractions which have been performed are led to a store 51, the storage locations in which can be addressed by these ordinal numbers and in which after completion of all of the subtractions each addressed storage location is set and each storage location which has not been addressed is reset. 
     The output from the store is connected via a rollout circuit 52 to a control pulse generator 53. The control pulse generator contains a plurality of switch members, each of which is associated with a respective storage location and upon the appearance of a switching cycle passes the contents of the respective storage location as a control pulse to the control lead for the amplifier channel connected downstream of it. In FIG. 3 there are shown only the control leads for five switching stages 71 to 75, each of which contains two switching channels 60, 61; . . . 68, 69. Further control leads are indicated by the dotted lines 57, 58. 
     The output 49 from the divider circuit 47 is connected to an arithmetic unit 54 which calculates a control signal duration the ratio of which to the time interval between successive clock pulses corresponds to the difference between the remainder from substraction and the subtrahend. This duration-modulated control signal is fed to the roll-out circuit 52 which contains an associated delay circuit for each storage location in the store 51, and controls that delay circuit which is associated with the set storage location having the highest ordinal number. By the delayed transmission of the contents of the &#34;last&#34; set storage location a width-modulation of the control pulse for a switching channel is brought about, this width-modulation enabling the envelope of the output signals from the switching channels, superimposed in steps, to be adapted better to the analog signal. 
     In the case of the embodiment described the clock unit 56 generates two timing trains. One timing train having a frequency of 80 kHz is fed to the A/D converter and to the roll-out circuit; the other timing train having a frequency of 100 MHz controls the divider circuit and the arithmetic unit. It is thus possible to scan the amplitude of the analog signal at time intervals of 12.5 μs and to emit the control pulses for the switching channels at the same intervals. For compensating the time of calculation and storage the control pulses, which correspond to a scanning of the analog signal effected at a given time cycle, are only released by the control pulse generator during the succeeding time cycle. 
     As is described in detail in the already mentioned Swiss Patent Application No. 7307/79, each switching channel contains a pulse transformer which because of the unavoidable saturation can only transform pulses of up to about 50 μs duration. For transforming pulses of longer duration, therefore, in the proposed switching amplifier two switching channels 60,61; 62,63; 64,65; 66,67 and 68,69 are connected together into each switching stage 71,72,73,74 and 75 respectively. The control pulse generator 53 now causes control pulses the duration of which is longer than 50 μs to be fed alternately to one or other switching channel of the associated switching stage. Further, the pulse generator 53 causes the control pulses fed to the individual switching stages to be shifted with respect to one another by a time cycle of 12.5 μs. The result of this is that the switching channels in the energized switching stages do not get switched over simultaneously. 
     In FIG. 4 there is shown the formation of an analog signal by means of the switching pulses generated by the switching channels of a switching amplifier in accordance with FIG. 3. For that purpose let it be assumed that the analog input signal 80 of simple sinewave shape, having a time duration of 200 μs, corresponding to a frequency of 5 kHz, is scanned in the A/D converter 46 every 12.5 μs, corresponding to a frequency of 80 kHz, and the scanned analog value appears as a digital value at the output from the converter. As has already been described above, the A/D converter enables the maximum convertible analog range 81 to be divided up into 1024 digital values, while the switching stages can only process 48 control pulses. The digital value appearing at the output from the A/D converter is therefore divided up in the succeeding divider circuit 47 into digital value stages, each of which contains 20 digital values. In FIG. 4 only the digital value stages are plotted on the ordinates. 
     For better understanding of the following description let it be again pointed out that the store 51 is built up in such a way that at each timing signal all of the storage locations which have not been set are reset. 
     Let it further be assumed that during the first time cycle at a zero point in time all of the storage locations are reset, ie., there exists no signal which can be rolled out. At this point in time the amplitude of the analog signal is also zero, wherefore after the scanning of the signal there appears at the output from the A/D converter the digital signal zero which is not further processed. 
     During the second time cycle at the point in time 12.5 μs all of the storage locations are still reset and no signal can be rolled out. In return, upon scanning the analog signal an analog value A is established which corresponds to about 18 digital values. At the output from the divider circuit there then appears on the lead 48 a &#34;1&#34; and on the lead 49 an &#34;18&#34;, which means that even at the first substraction of (1024:48) digital values a remainder of 18 is left. Consequently one storage location is set in the store 51 and the arithmetic unit 54 delivers to the roll-out circuit 52 a delay signal which brings about the rolling-out of the contents of the store with a delay of about 2/20 of the cycle time, thus in the present example 1.25 μs. 
     During the third time cycle at the point in time 25 μs the content of the store is read out with the aforesaid delay and passed as a control signal in the form of a pulse to a control lead for one of the switching channels. At the same time the analog signal is scanned and in doing so the analog value B is established, which corresponds to about 50 digital values. At the output from the divider circuit there then appears on the lead 48 a &#34;3&#34; and on the lead 49 a &#34;10&#34;, which means that upon substraction three times of (2024:48) digital values a remainder of 10 is left. Then three storage locations in the store 51 are set and the arithmetic unit 54 delivers to the roll-out circuit 52 a delay signal which during rolling-out of the contents of the store delays the contents of the third storage location by about 10/20 of the cycle time, ie., by 6.25 μs. 
     During the fourth time cycle at the point in time 37.5 μs the contents of the store are read out and a control signal is passed to each control lead which is associated with a storage location which has been set, in doing which the control signal corresponding to the storage location 3 is delayed as described above. At the same time the analog signal is scanned and the analog value C is converted into about 130 digital values. These digital values in the same way as already described above are divided into seven digital value stages which set seven storage locations in the store, of which the seventh is rolled out with a delay of 10/20 of the cycle time or 12.5 μs. 
     The analog signal is then scanned again during each of the succeeding time cycles 5 to 17, and the analog values D to Q determined are converted in the way described, stored in the store 51 and during the succeeding time cycle in each case, 6 to 18, are rolled-out from the store and passed as control pulses to the associated control signal leads. 
     The analog value I determined during the tenth time cycle corresponds to about 510 digital values. Therefore on the output lead 48 from the divider circuit there appears a &#34;26&#34; and on the output lead 49 a &#34;10&#34;. Consequently during the succeeding twelfth time cycle only 26 storage locations are set in the store 51 and for the twenty-sixth storage location a delay signal is calculated by the arithmetic unit 54, which corresponds to about half the cycle time and brings about the delayed control pulse I&#39;. The same goes for the control pulses K&#39;, L&#39;, N&#39;, O&#39; and P&#39;. 
     As has already been described above, to compensate the time of calculation and storage, the control pulses which correspond to a scanning of the analog signal effected during a given time cycle are released by the control pulse generator only during the succeeding time cycle. That has the result that the signal 82 composed of pulses on the series lead connecting the outputs from the switching channels and the output signal 83 from the switching amplifier are shifted with respect to the input signal to the amplifier by the duration of one time cycle by about one and a half time cycles respectively. 
     As has already been described above, the switched-on time for the pulse transformer in the switching channels is limited, for which reason the channels are combined in pairs into switching stages. The control pulse generator 53 is correspondingly designed so that the contents of one storage cell are passed alternately to the two control signal leads of the associated switching stage. The switching-over between the signal leads for the switching channels in the various switching stages is thereby effected not simultaneously but with a time shift, as is shown in FIG. 4 for the five switching stages 71 to 75 and the corresponding switched-on periods 60&#39;, 61&#39;; 62&#39;,63&#39;; 64&#39;,65&#39;; 66&#39;, 67&#39; and 68&#39;, 69&#39;. The result of this is that only a quarter of the energized switching channels get switched over at the same point in time. 
     As may be observed from FIG. 4, in the case of the new method the analog signal is converted not into a maximum processable number of width-modulated pulses, independent of the instantaneous value of the amplitude, but into a number of pulses of maximum width proportional to the instantaneous value of the analog signal. In this way it is possible to form an analog signal with a minimum number of signals in pulse form or to amplify it in a switching amplifier by a minimum number of switching processes. That the switching losses in the switching amplifier may thereby be quite considerably reduced has already been mentioned in the introduction. 
     It goes without saying that the new method and the switching amplifier described may be modified in a large number of ways and adapted to certain working conditions. For example, it is possible to employ instead of the described wide control pulses also very short control pulses, with a switching-on pulse corresponding to the leading edge of the wide control pulse and a switching-off pulse corresponding to the trailing edge. Again, it is not necessary to associate one or more control leads with each switching stage. The switching-on and switching-off pulses may instead be provided with addresses and be fed by the time-multiplex method along a single control lead to all of the associated switching stages or channels. It is also unnecessary that the actuated switching stages simulate the variation of the analog signal with time, as is shown in FIG. 4 for simpler explanation of the method of operation. Because the output signals from the switching stages are added on the series lead, the amplified analog signal appearing at the output terminal 44 is always the same independently of which switching stage was switched on by which control signal and also independently of whether a switching stage is switched on and off by the same control signal. 
     The device described for the performance of the new method may be realized with commercial components known to anyone skilled in the art, for which reason description of them is expressly dispensed with here. 
     Obviously, numerous additional modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.