Abstract:
A semiconductor integrated circuit includes a multi-chip package having a plurality of semiconductor chips. The semiconductor integrated circuit includes a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal. Here, the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. §119(a) to Korean Application No. 10-2009-0070139, filed on Jul. 30, 2009 in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as if set forth in full. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates to semiconductor circuit technology, and more particularly, to a semiconductor integrated circuit. 
         [0004]    2. Related Art 
         [0005]    As a semiconductor memory is highly integrated, necessity to enhance the memory capacity of a package has increased. As a way of enhancing the memory capacity of a package, a multi-chip package is widely used. 
         [0006]    In the multi-chip package, a plurality of semiconductor chips (hereinafter simply referred to as “chips”) should be electrically connected. Methods for electrically connecting the plurality of chips in the multi-chip package are divided into several categories, including a wire bonding type in which the plurality of chips are electrically connected using wires and a through-silicon via type in which the plurality of chips are electrically connected using silicon vias. 
         [0007]    The plurality of chips constituting the multi-chip package are respectively tested at a wafer level using probes. 
         [0008]    Since the chips are tested at a wafer level, signal loading at a multi-chip package level cannot be reflected. 
         [0009]    Therefore, when the chips are tested at a wafer level, the reliability of test results is likely to deteriorate due to timing errors of signals, and the operational performance of the multi-chip package can be degraded. 
       SUMMARY 
       [0010]    A semiconductor integrated circuit which can allow a test to be performed at a wafer level with a comparable precision as at a multi-chip package level is described herein. 
         [0011]    In one aspect of the present invention, a semiconductor integrated circuit including a multi-chip package having a plurality of semiconductor chips, comprises; a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal, wherein the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line. 
         [0012]    In another aspect of the present invention, a semiconductor integrated circuit comprises: a plurality of semiconductor chips; and a via formed through the plurality of semiconductor chips to electrically connect the plurality of semiconductor chips together, wherein one of the plurality of semiconductor chips comprises a signal line and is configured to apply a designed signal loading corresponding to an actual signal loading of the via, to the signal line in response to a test signal. 
         [0013]    In still another aspect of the present invention, a semiconductor integrated circuit comprises: a plurality of semiconductor chips; a wire configured to electrically connect the plurality of semiconductor chips together, wherein one of the plurality of semiconductor chips comprise a signal line, and is configured to apply a designed signal loading corresponding to an actual signal loading of the wire, to the signal line in response to a test signal. 
     
    
     
       is BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0015]      FIG. 1  is a layout diagram of a semiconductor integrated circuit of a through-silicon via type in accordance with an embodiment of the present invention; 
           [0016]      FIG. 2  is a circuit diagram of a test signal generation section shown in  FIG. 1 ; 
           [0017]      FIG. 3  is a circuit diagram of a signal loading compensation section shown in  FIG. 1 ; and 
           [0018]      FIG. 4  is a layout diagram of a semiconductor integrated circuit of a wire bonding type in accordance with another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    Hereinafter, a semiconductor integrated circuit according to the present invention will be described below with reference to the accompanying drawings through preferred embodiments. 
         [0020]    Before describing embodiments of the invention in detail, it is to be noted that the present invention can allow signal loading of entire chips constituting a multi-chip package to be implemented when performing a test for one chip and can be applied to various kinds of multi-chip packages including a wire bonding type and a through-silicon via type. 
         [0021]    Referring to  FIG. 1 , a semiconductor integrated circuit  100  in accordance with an embodiment of the present invention includes a plurality of chips CHIP 0 -CHIP 3 . 
         [0022]    The plurality of chips CHIP 0 -CHIP 3  can be classified, for example, into a master chip CHIP 0  and slave chips CHIP 1 -CHIP 3 . 
         [0023]    The master chip CHIP 0  manages signal transmission and reception with an external device such as a testing equipment or a memory controller, and may have a memory region. 
         [0024]    The major parts of the slave chips CHIP 1 -CHIP 3  are memory regions, and the slave chips CHIP 1 -CHIP 3  may have configuration for transmission and reception of signals. 
         [0025]    Silicon vias  101  are formed through the plurality of chips CHIP 0 -CHIP 3 . 
         [0026]    The semiconductor integrated circuit  100  includes, in one of the plurality of chips CHIP 0 -CHIP 3 , e.g., in the master chip CHIP 0 , a test signal generation section  110  and a plurality of signal loading compensation sections  120 - 140  as circuit components for implementing signal loading of the entire chips CHIP 0 -CHIP 3  when performing a testing operation. 
         [0027]      FIG. 2  is a circuit diagram of a test signal generation section shown in  FIG. 1 . As shown in  FIG. 2 , the test signal generation section  110  is configured to activate a test signal TM based on whether a fuse  111  is cut off or not and initialize the test signal TM to an inactivation level in response to a power-up signal PWRUPB. 
         [0028]    The power-up signal PWRUPB indicates a power-up state in which a power voltage VDD supplied to the semiconductor integrated circuit  100  is stabilized above a target level. In the present invention, it is assumed that the power-up signal PWRUPB has a high level before the power-up state and a low level after the power-up state. 
         [0029]    The test signal generation section  110  can be implemented by the fuse  111 , a plurality of inverters IV 1  and IV 2 , and a plurality of transistors M 1  and M 2 . 
         [0030]    In an initial operation of the test signal generation section  110  before the power-up state of the semiconductor integrated circuit  100 , since the transistor M 1  is turned on by the power-up signal PWRUPB of a high level, node A becomes a low level and the test signal TM is outputted at a low level. The test signal TM is maintained at the low level by the transistor M 2  and the inverter IV 1 . 
         [0031]    Since the transistor M 1  is turned off by the power-up signal PWRUPB of a low level after the power-up state, if the fuse  111  is not cut off, the test signal TM transits to a high level. Meanwhile, if the power-up signal PWRUPB becomes a low level with the fuse  111  cut off, the test signal TM is continuously maintained at the low level. 
         [0032]    In the present invention, a test signal TM can be provided from outside which is separate from the signal generation section  110 . That is to say, a circuit configuration is made in a manner such that the test signal TM can be received from an external signal terminal of a completed multi-chip package and can be provided to the signal loading compensation sections  120 - 140 . 
         [0033]    The plurality of signal loading compensation sections  120 - 140  are respectively connected to signal lines SL 1 -SL 3  and are configured in such a way as to internally realize capacitance values corresponding to signal loading components, e.g., capacitance values, of the silicon vias  101  respectively connected to the signal lines SL 1 -SL 3 . Here, each of the signal compensation sections  120 - 140  is configured to apply a designed signal loading to the signal line in response to the test signal TM. The plurality of signal loading compensation sections  120 - 140  are different from one another only in terms of capacitance values to be realized, and can be configured in a similar manner. Therefore, only the configuration of the signal loading compensation section  120  will be described below. 
         [0034]    The signal lines SL 1 -SL 3  are shown as parts of entire signal lines, and can include a data line, a control line and a power line. 
         [0035]      FIG. 3  is a circuit diagram of a signal loading compensation section shown in  FIG. 1 . Referring to  FIG. 3 , the signal loading compensation section  120  can be implemented by a plurality of transistors M 11  and M 12  and a capacitor C 11 . 
         [0036]    A drain of the transistor M 11  is connected to the signal line SL 1 , a source is connected to node B, and a gate receives the test signal TM. 
         [0037]    On the other hand, a source of the transistor M 12  receives the power voltage VDD, a drain is connected to node B, and a gate receives the test signal TM. 
         [0038]    The capacitor C 11  is connected to node B at one end and grounded at the other end. 
         [0039]    The capacitance values of the capacitors C 11  of the plurality of respective signal loading compensation sections  120 - 140  can be set to be the same or different from one another in consideration of capacitance of the silicon vias  101  connected to the signal lines SL 1 -SL 3  and coupling capacitance. 
         [0040]    Operations of the semiconductor integrated circuit  100  in accordance with the embodiment of the present invention, configured as mentioned above, will be described below. 
         [0041]    While the semiconductor integrated circuit of  FIG. 1  is illustrated in the form of a completely manufactured multi-chip package, a test for the master chip CHIP 0  at a wafer level (hereafter referred to as a “wafer test”) is performed solely for the master chip CHIP 0  in a state in which the silicon vias  101  are not formed. 
         [0042]    While the wafer test is performed, the fuse  111  of the test signal generation section  110  shown in  FIG. 2  is kept uncut. 
         [0043]    Thus after power-up of the semiconductor integrated circuit  100 , the test signal TM is applied to all the signal loading compensation sections  120 - 140  at a high level. 
         [0044]    Since the test signal TM is a high level, the transistors M 11  of all the signal loading compensation sections  120 - 140  are turned on, and the transistors M 12  are turned off. 
         [0045]    As the transistors M 11  are turned on, the capacitors C 11  are connected to the signal lines SL 1 -SL 3  and serve as loading of the signal lines SL 1 -SL 3 . In this state, the wafer test is performed. 
         [0046]    In other words, although it is the norm that the wafer test is performed for only the master chip CHIP 0  with the silicon vias  101  is not formed, in the embodiment of the present invention, it is possible to provide a comparable or same signal loading circumstances as in the case of the multi-chip package in which the master chip CHIP 0  and the slave chips CHIP 1 -CHIP 3  are electrically connected through the silicon vias  101 . 
         [0047]    After the wafer test is performed, the fuse  111  of the test signal generation section  110  shown in  FIG. 2  is cut off, and the silicon vias  101  are formed in the master chip CHIP 0  and the slave chips CHIP 1 -CHIP 3 . Then, by conducting the other processes, the manufacture of the multi-chip package as shown in  FIG. 1  is completed. 
         [0048]    In the state of the multi-chip package, after power-up, the test signal TM is locked at a low level as described above. 
         [0049]    Since the test signal TM has a low level, the transistors M 11  of all the signal loading compensation sections  120 - 140  are turned off, and the transistors M 12  are turned on. 
         [0050]    As the transistors M 11  are turned off, the capacitors C 11  are electrically disconnected from the signal lines SL 1 -SL 3  and do not serve any more as loading of the signal lines SL 1 -SL 3 . 
         [0051]    As the transistors M 12  are turned on, the power voltage VDD is applied to the capacitors C 11  to prevent the capacitors C 11  from floating. 
         [0052]    Namely, in the present invention, in a normal operation after the wafer test, since actual signal loading by the silicon vias  101  formed in the master chip CHIP 0  and the slave chips CHIP 1 -CHIP 3  is is effected, additional signal loading by the capacitors C 11  is prevented. 
         [0053]      FIG. 4  is a layout diagram of a semiconductor integrated circuit of a wire bonding type in accordance with another embodiment of the present invention. Referring to  FIG. 4 , the wafer testing scheme according to the present invention can also be adopted in a semiconductor integrated circuit  200  of a wire bonding type. 
         [0054]    In the semiconductor integrated circuit  200  of a wire bonding type in accordance with another embodiment of the present invention, in place of silicon vias, the same signal lines SL 1 -SL 3  of a master chip CHIP 0  and slave chips CHIP 1 -CHIP 3  are electrically connected with one another by means of wires  201 . 
         [0055]    Even in the semiconductor integrated circuit  200  of a wire bonding type, a wafer test is performed only for the master chip CHIP 0  in a state in which the wires  201  are not formed. 
         [0056]    Hence, similar to the master chip CHIP 0  shown in  FIG. 1 , by configuring a test signal generation section  110  and a plurality of signal loading compensation sections  120 - 140 , when performing the wafer test, it is possible to provide a comparable or same signal loading circumstances as in the case of the multi-chip package in which the master chip CHIP 0  and the slave chips CHIP 1 -CHIP 3  are electrically connected through the wires  201 . 
         [0057]    Meanwhile, in the semiconductor integrated circuit according to the present invention, as the occasion demands, a test can be performed even after the manufacture of the multi-chip package is completed. That is to say, after the test signal TM outputted from the test signal generation section  110  is inactivated to a low level, a test signal can be provided from outside to the signal loading compensation sections  120 - 140  such that the signal loading compensation sections  120 - 140  are activated. 
         [0058]    While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only Accordingly, the semiconductor integrated circuits described herein should not be limited based on the described embodiments. Rather, the semiconductor integrated circuits described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.