Abstract:
A component includes a carrier substrate having a coefficient of thermal expansion α p  and a chip mounted on the carrier substrate by a plurality of bumps. The chip has a first coefficient of thermal expansion α 1  in a first direction x 1  and a first expansion difference, Δα 1  equal to the absolute value of α p −α 1 . The chip also has a second coefficient of thermal expansion α 2  in a second direction x 2  and a second expansion difference Δα 2  is equal to the absolute value of α p −α 2 ,. The bumps are arranged such that a first distance, Δx 1 , corresponding to a normal projection of a line between centers of terminally situated bumps in the first direction onto an axis running parallel to direction x 1  is less than a second distance corresponding to a normal projection of a line between centers of terminally situated bumps in the second direction onto an axis parallel to direction x 2 .

Description:
FIELD OF THE INVENTION 
     An electrical component with a chip that is mounted on a carrier substrate in a flip chip arrangement is disclosed. 
     BACKGROUND 
     The chip plane equipped with component structures can have coefficients of thermal expansion α 1 , α 2  differing from one another in different directions, depending on the crystal axes. This is particularly the case for surface acoustic wave chips with a piezoelectric substrate whose physical properties exhibit anisotropy. The coefficients of thermal expansion α 1 , α 2 , are generally larger than the coefficient of thermal expansion α p  of the underlying carrier substrate. In case of a change in temperature, the change in length of the chip is greater than that of the carrier substrate. 
     The chip is mechanically fixed to the carrier substrate by means of solder joints (bumps). These solder joints are therefore subject to mechanical stresses that arise due to the difference Δα 1 =|α p −α 1 | and Δα 2 =|α p −α 2 | in the coefficients of thermal expansion of the chip and the carrier substrate. In case of differing coefficients of thermal expansion of the chip and the carrier substrate, the outermost bumps and the carrier substrate, in particular, are subject to the strongest stresses form the shearing force F(F 1 , F 2 ) acting on them. F 1  is the force component in the first preferred direction x 1 . F 2  is the force component in the second preferred direction x 2 . 
     SUMMARY 
     In some embodiments, an electrical component is formed with a flip chip arrangement in which the smallest shearing forces possible act on the outermost bumps. 
     The distance between the centers of the terminal bumps in the, direction x 1  is L 1  at a first temperature T 1  and L 2  at a second temperature T 2 . The linear thermal expansion ΔL=|L 1 −L 2 | of the chip area in direction x1 defined by the terminal bumps is ΔL=α 1 L 1 ΔT, where ΔT=|T 1 −T 2 |. A shearing force component F 1  that is proportional to ΔL arises in this direction. In some embodiments, it is sought to keep the shearing force component F 1  as low as possible. Taking into account the given coefficients of thermal expansion, a bump arrangement is sought in which the distance between the terminal bumps in the direction of the maximum expansion difference is smaller than the distance between the terminal bumps in the direction of minimum expansion difference. 
     An electrical component with a carrier substrate and a chip that is mounted on the carrier substrate with a flip-chip arrangement is disclosed. The carrier substrate has a coefficient of thermal expansion α p . The chip has a coefficient of thermal expansion α 1  in a first preferred direction x 1 , where Δα 1 =|α p −α 1 | is the first expansion difference. In a second preferred direction x 2 , the chip has a second coefficient of thermal expansion α 2 , where α 2 =|α p −α 2 | is the second expansion difference. 
     The distance between the orthogonal projections of the bump centers of the terminal bumps in direction x 1  onto the x 1  axis is Δx 1 . The distance between the orthogonal projections of the bump centers of the terminal bumps in direction x 2  onto the x 2  axis is Δx 2 . Here we have Δx 1 &lt;Δx 2  for Δα 1 &gt;Δα 2  and Δx 1 &gt;Δx 2  for Δα 1 &lt;Δα 2 . With such a bump arrangement, the shearing force arising from temperature changes and acting on the terminal bumps can be successfully minimized. 
     First preferred direction x 1  is preferably defined to be the direction in which the component has the largest expansion difference, Δα 1 . Second preferred direction x 2  is preferably defined to be the direction in which the component has the lowest expansion difference, Δα 2 . 
     Distances Δx 1 , Δx 2  are preferably selected relative to one another such that the components F 1 , F 2  of shearing force F are substantially equal to one another. 
     Axes x 1 , x 2  define a coordinate system {x 1 ,x 2 }, which corresponds to a two-dimensional space, on the surface of which the chips are arranged. 
     Axes x and y are oriented along the along the intersecting chip edges. The chip edges are preferably rectangular in form, i.e., the first and second chip edges are perpendicular to one another. In case of chip edges running parallel to one another, axes x, y define a rectangular coordinate system {x, y}. The first chip edge is oriented, for instance, along the x axis and the second chip edge along the y axis. 
     In general, axes x, y, x 1  and x 2  can be oriented at an arbitrary angle relative to one another. In one variant, at least one of axes x 1 , x 2  can run parallel to axis x or y, but that is not a necessary condition. The coordinate system {x 1 , x 2 } can coincide with coordinate system {x, y}. The (possibly rectangular) coordinate system. {x 1 , x 2 } can be rotated by an angle β 2 &gt;0 relative to coordinate system {x, y}; see  FIG. 11 . In one variant, coordinate system {x 1 , x 2 } can be obliquely angular, where angle β 1  between axes x 1  and x 2  differs from 90° (see  FIG. 12 ). 
     It is advantageous to arrange bump rows on the bottom side of the chip parallel to the respective chip edge. In one variant, several bumps can be arranged on a line parallel to a first chip edge (in direction x) and/or parallel to the second chip edge (in direction y). The bumps can also be arranged in a row that is preferably situated centrally on the lower surface of the chip. The bumps can also be arranged along the four chip edges in a peripheral area of the chip around the chip edges. 
     The bump rows are preferably arranged along direction x 1  of the maximal expansion difference. The distance between the bumps situated terminally in direction x 1  or optionally in the same row, is preferably smaller than the distance between the bump rows in which the terminally situated bumps in direction x 2  are situated. 
     In one variant, several bumps can be arranged on a line along first preferred direction x 1  and/or along second preferred direction x 2 . 
     In one variant, all bumps are arranged in two rows parallel to direction x 2  of minimal expansion difference. The distance between these rows is Δx 1 . Distance Δx 1  is smaller in this case than the length of the row (measured between the centers of the terminal bumps of the row). The length of the chip edges can be adapted to the bump arrangement in such a manner that the mutually parallel-oriented rows are arranged in the edge areas of the chip. The terminal bumps of the chip are preferably turned toward the corners of the chip surface here. In this case, the first chip edge (in direction x 1 ) is shorter than the second chip edge (in direction x 2 ). 
     The lower surface of the chip can be subdivided in at least one direction x, y (or x 1 , x 2 ) into wide peripheral areas and a central area, with the width of the respective peripheral area preferably exceeding or twice the cross-sectional size of bump. The bumps in this variant are arranged only in the central area. The wide peripheral areas have no bumps. 
     As a rule, the coefficient of thermal expansion α p  of the carrier substrate is less than α 1  and/or α 2 . The coefficient of thermal expansion of the basic material of the carrier substrate can also be modified, more particularly, raised, within certain limits by, for instance, the addition of an additive or filler, and thereby be adapted to the coefficient of thermal expansion α 1  and/or α 2 . Thus one obtains expansion differences Δα 1  and/or Δα 2  that are as small as possible. It is possible, for instance, to select the material of the carrier substrate such that α p =α 1  or α p =α 2 , i.e., Δα 1 =0 or Δα 2 =0. 
     In some embodiments, for example, it can be the case that Δα 2 =0, Δα 1 &gt;0. In this case it is advantageous to arrange the bumps in a row along the second preferred direction x 2 , so that Δx 1 =0. 
     A bump row is understood to be an arrangement of the bumps along one direction in which the bump centers of the bumps arranged in a row lie on a line in this direction. 
     In relation to direction x 1 , the bump row is preferably arranged centrally on the lower surface of the chip. In case the bumps are arranged in only one row, the chip can then be stabilized relative to the carrier substrate in the x 1  direction such that the lower surface of the chip runs substantially parallel to the surface of the carrier substrate. Spacers that are preferably arranged between the chip and the carrier substrate along first preferred direction x 1  in the peripheral areas of the chip can be provided. 
     In another variant, the material of the carrier substrate can be selected such that coefficient α p  lies between α 1  and α 2 . Here it can be the case that α 1 &gt;α 2  or that α 1 &lt;α 2 . Coefficient α p  is preferably matched to a lower coefficient of thermal expansion, where α p =min{α 1 , α 2 }. Coefficient α p  can also be matched to the larger coefficient of thermal expansion, where α p =max{α 1 , α 2 }. 
     The bumps (not necessarily the terminal bumps) are preferably arranged on the bottom side of the chip such that the larger bump spacings lie in the direction of the lowest expansion difference, α min =min{α 1 , α 2 }. The bump height and diameter is preferably small, for instance, &lt;100 μm or &lt;50 μm. 
     On the lower chip surface and the upper side of the carrier substrate, contact surfaces firmly joined to the bumps (UBM=under bump metallization) are provided. In some embodiments, larger contact surfaces are provided for terminal bumps that are more severely stressed during temperature changes than for the remaining bumps, which are less stressed. This variant has the advantage that the surface area of the chip&#39;s bottom side that is covered by the centrally arranged bumps can be kept small. 
     The component structures are preferably arranged on the chip&#39;s bottom side. It is also possible, however, to arrange the component structures at least in part in the interior of the chip. 
     The invention will be explained in detail below on the basis of embodiments and the associated figures. The figures show various embodiments of the invention on the basis of schematic representations not drawn to scale. Identical or identically functioning parts are labeled with the same reference numbers. Shown schematically are: 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
         FIG. 1 , the component with a chip mounted on the carrier substrate with a flip-chip construction, in a schematic cross section; 
         FIGS. 2 and 3 , the plan view, in each case, of a lower surface of a chip with a bump arrangement; 
         FIGS. 4 ,  5 ,  6 ,  7 , the plan view, in each case, of the lower surface of a chip with bump arrangement, active component structures and with wide peripheral areas along the first preferred direction; 
         FIG. 8 , the plan view of the lower surface of a chip with a wide peripheral area all around it that has no bumps; 
         FIG. 9 , the plan view of the lower surface of a chip in which the terminal bumps in one direction do not form bump rows in this direction; 
         FIG. 10 , the plan view of the lower surface of a chip with a bump arrangement; 
         FIGS. 11 ,  12 , the projection, in each case, of the bump centers onto axes x 1 , x 2  for a rectangular coordinate system ( FIG. 8 ) and an oblique-angled coordinate system ( FIG. 9 ) {x 1 ,x 2 }; and 
         FIG. 13 , the plan view of the lower surface of a chip with differently large contact surfaces that are assigned to the terminal and other bumps. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows the schematic cross section of the component, a carrier substrate  1  and a chip  2  mounted thereon via bumps  31 ,  32 . Arranged on its lower surface, the chip has, for instance, component structures operating with acoustic waves. The arrangement, for the sake of example, of component structures operating with surface acoustic waves on the underside of the chip is shown in  FIGS. 4-7 . 
       FIGS. 4-7  each show a filter that has two acoustic tracks. The first (upper) and the second (lower) acoustic track have several transducers  711 ,  712 ,  713  and  721 ,  722 ,  723 , respectively. Transducer  711  arranged in the first acoustic track serves as the input transducer and transducer  721  arranged in the second acoustic track serves as the output transducer of the filter. Transducers  712 ,  713 ,  722  and  723  are coupling transducers for input or output coupling of the electrical signal from one track to another. 
     Input transducer  711  is connected to an input port, and output transducer  721  is connected to an output port. The electrical terminals of the input transducer (or the output transducer) are arranged in  FIGS. 4 and 5  on different sides of the respective acoustic track. Input transducer  711  (or output transducer  721 ) is connected in  FIG. 4  via feed lines to a terminally situated bump  31  (or  32 , respectively) and an additional bump arranged centered between the two tracks. Input transducer  711  (or output transducer  721 ) is connected in  FIG. 5  to a terminally-arranged bump  34  (or  31 , respectively) and an additional bump arranged centered between the two tracks. 
     The coupling transducers  712  and  722 ,  713  and  723  of different tracks are electrically connected to one another and to a ground bump (to a terminally-arranged bump  33  or  34  in  FIG. 4 ; to a terminally-arranged bump  32  or  33  in  FIG. 5 ). 
     In  FIGS. 6 and 7 , input and output transducers  711 ,  721  are subdivided into two component transducers  711   a  and  711   b ,  721   a  and  721   b , respectively, that are electrically connected to one another in series. The bumps connected to the input and output port are arranged in the outer bump rows. 
     The ground bumps connected to the coupling transducers are arranged in the outer bump rows in  FIG. 6 . The ground bumps connected to the coupling transducers are arranged between the acoustic tracks in  FIG. 7 . 
     In the variant presented in  FIG. 6 , the bumps connected to the input port are arranged in different bump rows to the left and right of the acoustic tracks that are oriented along the x 1  axis. The same also applies to the bumps connected to the output port. 
     The bump rows are thus oriented along the direction of maximum expansion difference. The distance x 1  between the terminally situated bumps in the same row ( 31  and  32 ,  33  and  34 ) is smaller than the distance between the bump rows which contain the bumps situated terminally in the x 2  direction. 
     In the variant presented in  FIG. 7 , the bumps connected to the input port are arranged in a first bump row oriented along the x 1  axis and lying above the first acoustic track in the figure. Ground bumps  31 ,  32  connected to the coupling transducers are oriented along a second bump row oriented along the x 1  axis and lying between the two acoustic tracks in the figure. The bumps connected to the output port are arranged in a third bump row oriented along the x 1  axis and lying below the second acoustic track in the figure. Here, too, the distance between bumps  31  and  32  that are terminally situated (in the x 1  direction) is less than the distance between the bump rows in which bumps  33  and  34  that are situated terminally (in the x 2  direction) are situated. 
     Carrier substrate  1  shown in  FIG. 1  has several dielectric layers  11 ,  12 ,  13 , between which structured metal layers (not shown here) with hidden component structures are arranged. The metal layers are electrically connected via through hole contacts  17  to one another as well as to external contacts  18  of the component that are arranged on the bottom side of carrier substrate  1  and to contact surfaces  19  of the carrier substrate that are arranged on the upper side of carrier substrate  1 . 
     The chip preferably has component structures operating with surface acoustic waves that are arranged on the lower surface of the chip, but are not shown in the figure. Chip  2  has contact surfaces  29  that are electrically connected to contact surfaces  19  of the carrier substrate by means of bumps  31 ,  32 . The lower chip surface is subdivided in first preferred direction x 1  into a central area  20 , in which bumps  31 ,  32  are arranged, and peripheral areas  21 ,  22  (without bumps). 
       FIGS. 2-12  show the bottom side of a chip  2  with the novel arrangement of the bumps. The bumps are represented by circles. The terminally situated bumps are labeled with reference numbers  31   34 . In  FIGS. 3   7 , the subdivision of the lower chip surface into several areas is represented by means of dashed lines  51  and  52 . 
     Axis x is oriented along a first chip edge. Axis y is oriented along a second chip edge. First preferred direction x 1  is oriented parallel to axis x in the variants according to  FIGS. 2-10 . Second preferred direction x 2  is oriented parallel to axis y. Thus, the first chip edge is oriented parallel to direction x 1  and the second chip edge is oriented parallel to direction x 2 . 
     The terminally situated bumps  31 ,  32  in first preferred direction x 1  are spaced apart from one another by the amount Δx 1 . The terminally situated bumps in the second direction x 2  ( 31  and  33  in  FIGS. 2 ,  3 ,  5 ,  6 ,  8 ,  10  or  33  and  34  in  FIGS. 4 ,  7 ,  9 ) are spaced apart from one another by distance Δx 2 . The distance between the bumps is measured between bump centers  310 ,  320 ,  330 ,  340  of bumps  31 ,  32 ,  33 ,  34 . 
     First connecting line  41 , connecting the centers of the terminally situated bumps  31 ,  32  (or  33 ,  34 ) in direction x 1 , is directed parallel to direction x 1  in  FIGS. 2 and 3 . Second connecting line  42 , connecting the centers of terminally situated bumps  31 ,  33  (or  32 ,  34 ) in direction x 2 , is directed parallel to the direction x 2  in these figures. This means that the corresponding terminally situated bumps are arranged in rows running parallel to the respective direction x 1  or x 2 . 
     In the general case, e.g., in the variant according to  FIG. 9 , the terminally situated bumps in direction x 1  or x 2  are not arranged in rows relative to these directions. Connecting lines  41 ,  42  between the bumps do not run parallel to the preferred directions here. In this case, as shown in  FIGS. 11 and 12 , bump centers  310 ,  320 ,  330 ,  340  are mapped perpendicularly onto the respective preferred directions x 1  and x 2 . The projection rays run perpendicular to the respective preferred direction. The points that correspond to the images of the bump centers on the respective axis are labeled with reference numbers  311 ,  321 ,  331 ,  341 . The outermost imaged points (e.g.,  311  and  321  in direction x 1  and  331 ,  341  in direction x 2 ) correspond to the terminally situated bumps in this direction. 
     In  FIGS. 2 ,  3  and  5  the terminally situated bumps  31 ,  32  in direction x 1  are arranged parallel to the first chip edge. In  FIGS. 2 and 3 , terminally situated bumps  31  and  32  in direction x 1  are arranged along a line parallel to the chip edge in the peripheral area running along the chip edge. 
     The projections of points  31  and  33  (or  32  and  34 ) onto axis x 1  agree with one another in  FIGS. 2 ,  3 ,  5 . The projections of points  31  and  32  (or  33  and  34 ) onto axis x 2  also agree with one another. Therefore, in  FIGS. 2 ,  3  and  5 , all four bumps  31 - 34  are terminally situated in each direction x 1 , x 2 . 
     In the variant shown in  FIG. 7 , terminally situated bumps  31 ,  32  are not arranged in an outer row as in  FIGS. 2 ,  3 , and  5 , but in the central row running parallel to the first edge, or in direction x 1 . The projections onto axis x 1  of the bumps arranged in the outer rows here lie between the projections of the bumps arranged in the central row onto this axis. The distance between bumps  31 ,  32  arranged in the central row is thus greater that the distance between bumps arranged in the outer rows. Therefore, bumps  31 ,  32  form the terminally situated bumps in direction x 1 . Since bumps  31 ,  32  do not lie in an outer row relative to direction x 1 , they are not terminally situated in direction x 2 . 
     In the variants according to  FIGS. 2-10 , first expansion difference Δα 1  is greater than second expansion difference Δα 2 . Accordingly, the Δx 1  in direction x 1  of the larger expansion difference is selected to be less than distance Δx 2  in the direction of the smaller expansion difference. The lower chip surface is subdivided along direction x 1  in  FIGS. 3 ,  5  and  7  into a central area  20  with bumps arranged therein and two wide peripheral areas  21 ,  22  without bumps. 
     In  FIGS. 5 and 7 , the bumps are arranged in three rows with two bumps each, with the rows running parallel to the first chip edge, or to direction x 1 . The distance, measured between the bump centers, between the two outer rows corresponds to difference Δx 2 . In  FIG. 6 , the bumps are arranged in three rows with two bumps each, the rows running parallel to the second chip edge, or to direction x 2 . The distance between the outer two rows, measured between the bump centers, corresponds in  FIG. 6  to distance Δx 1 . 
     The cross-sectional size of the chip is a in direction x 1  and b in direction x 2 . In  FIGS. 2 and 9 , a&lt;b; in  FIG. 3 , a&gt;b; in  FIGS. 4-8 , a=b. 
     The formation of the chip with a larger cross-sectional size b in direction x 2  of the smaller expansion difference has the advantage that the chip surface can be utilized especially space-economically. 
     In  FIG. 3 , the chip surface is formed with a greater cross-sectional size a in direction x 1  of greater expansion difference Δα 2 . Distance Δx 1  is nevertheless selected to be small in order to keep the shearing force component in the direction small. In direction x 1 , the chip surface is subdivided into a central area  20  and two wide peripheral areas  21  and  22 . Width c of wide peripheral area  21 ,  22  exceeds the cross-sectional size of a bump. All bumps are arranged in central area  20 . Wide peripheral areas  21 ,  22  have no bumps. 
     The lower surface of chip  2  in  FIG. 8  is subdivided into a central area  20  and wide peripheral area  21  running completely around. Chip  2  has no bumps in wide peripheral area  21 . All bumps  31 - 33  are arranged in central area  20  of the lower chip surface. The width of wide peripheral area  21  here is greater in direction x 1  than in direction x 2 . The width of wide peripheral area  21  in direction x 2  exceeds the simple cross-sectional size of a bump and is essentially equal to twice the cross-sectional size of a bump. The width of wide peripheral area  21  in direction x 1  markedly exceeds the cross-sectional size of a bump. In this example, Δα 1 &gt;Δα 2 . Therefore, distance Δx 1  between terminally situated bumps  31 ,  32  in direction x 1  is greater than distance Δx 2  between terminally situated bumps  31 ,  33  in direction x 2 . 
     In  FIG. 10 , an embodiment in which Δα 2 =0 and Δα 1 &gt;0 is shown. All bumps are arranged in a single row running parallel to second preferred direction x 2 , so that Δx 1 =0. The bump row is arranged centrally relative to direction x 1  on the lower surface of the chip. The chip is stabilized in direction x 1  with respect to the chip surface by spacers  81 ,  82  such that the lower surface of the chip runs parallel to the upper surface of the carrier substrate. Spacers  81 ,  82  are arranged along first preferred direction x 1  in the peripheral areas of the chip. In one variant, spacers  81 ,  82  can be permanently connected either to the chip or to the carrier substrate. Spacers  81 ,  82  can be permanently connected to both the chip and the carrier substrate in another variant. 
     The position of the bump row relative to direction x 1  can also be shifted away from the center toward the second chip edge. 
     It is shown in  FIG. 11  that the {x 1 , x 2 } coordinate system is rotated by an angle β 2  relative to the {x, y} coordinate system defined by the chip.  FIG. 12  shows a chip with anisotropic properties regarding its thermal expansion behavior, wherein the directions x 1 , x 2  of maximum and minimum expansions are not perpendicular to one another, but rather form an angle β 1 &lt;90°. Axes x 1 , x 2  run at an acute angle to the chip edges. 
       FIG. 13  shows an an embodiment, in which different-sized contact surfaces are provided on the lower chip surface for the terminally situated bumps  31 - 34  and for the others  35 ,  36 . Larger contact surfaces  91 - 94  are assigned to terminally situated bumps  31 - 34 , which are more severely stressed, while smaller contact surfaces  95 ,  96  are assigned to the other, less stressed bumps  35 ,  36  of the component. 
     Corresponding, different-sized contact surfaces opposing the contact surfaces of the chip are provided for the different types of bumps on the carrier substrate (not shown here). The bumps are permanently joined to the contact surfaces of the chip and the carrier substrate. 
     The invention is not limited to the above-presented embodiments, specific materials or the number of illustrated elements.