Abstract:
Method and apparatus for providing a microprocessor with a divide by one frequency generator, while permitting the external clock driving the generator to vary in frequency without interruption of the operations of the microprocessor. A divide by two clock generator is also provided on the microprocessor chip. When a change in the frequency of the external clock is desired a request signal is provided to the chip. After a period of time has elapsed that permits the microprocessor to achieve a &#34;safe&#34; mode in which processing integrity is maintained even if the clock signal is interrupted, the divide by two clock generator is switched into operation. The external clock is then allowed to change frequency after which the divide by one clock generator is reactivated, following a period of time sufficient to allow the divide by one clock generator to stabilize.

Description:
This is a continuation of application Ser. No. 07/991,045 filed on Dec. 15, 1992, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to microprocessors having on-chip clock generators that are driven by external clock signals, and more particularly relates to such microprocessors in which the on board clock generator is a divide by one clock generator. 
     2. Background Art 
     Microprocessors are typically driven by quartz crystal oscillator clock signal sources that are external to the microprocessor chip itself. The reason for this is that quartz crystal oscillators are very stable in frequency, which is desirable in microprocessor operation. However, while very stable in frequency, it is well known that the duty cycle of quartz crystal oscillators varies considerably from crystal to crystal. As a consequence, the practice that has developed in the art is to provide a quartz crystal oscillator having a frequency that is twice that needed to drive the microprocessor itself, and then provide a divide by two clock generator on the microprocessor chip itself. The divide by two clock generator uses only the leading edge of the quartz crystal clock signal, which is, as described above, very stable, to trigger the rising and falling transitions, thereby providing an on board clock signal that is very stable both with respect to frequency and as to duty cycle. 
     However, recently microprocessor technology has advanced to the point where the frequency at which microprocessors can be operated has become so great that it is impractical to utilize the traditional divide by two on board clock generator, because the external clock frequency would simply be too high to permit the provision of practical circuitry therefore. Accordingly, sophisticated divide by one clock generators, incorporating phase lock loops or delay line clock generators, have been provided. These new clock macros have the advantage of operating the internal logic at divide by one speed versus the traditional divide by two mode. However these clock generators require the input clock frequency to remain constant in order to generate stable internal clocks. 
     Another trend in computer technology has been the incorporation of such high performance microprocessors in battery operated personal computers, such as so called lap top and notebook computers. In such computers, the battery life has become a critical design issue. This, in turn, has stimulated focus on power savings in such battery operated personal computers. A well known technique to save power in personal computers is to reduce the clock speed of the microprocessor wherever possible. However, in those instances where the microprocessor is one of the aforementioned high performance microprocessors having a divide by one on board clock generator, shifting the external clock frequency &#34;on the fly&#34;, i.e., dynamically, is, as mentioned above, not possible. Changing the input frequency to phase lock loop and delay line clock generators causes the internal clocks to be corrupted, most likely resulting in a code error. 
     Accordingly, there is a need for a microprocessor having a divide by one on board clock generator that has the ability to accept an external clock which can change frequency during operation, so as to permit such microprocessor to be utilized in low power consumption applications. 
     This need is met in the present invention. 
     SUMMARY OF THE INVENTION 
     According to the present invention a microprocessor is provided receiving a stream of data and instructions and, in response to said instructions, operating on the data, the microprocessor including a divide by one frequency generator that receives an external clock signal and in response thereto generates an internal clock signal having the same frequency as the external clock signal but having modified characteristics, as compared to the external clock signal, and being capable of having the frequency of the external clock signal applied thereto changed without effecting the integrity of the operations of the microprocessor. The invention includes a non-one divider type clock generator that receives the external clock signal and in response thereto generates an internal clock signal having a fractional frequency of the external clock signal. 
     An arrangement is provided for receiving a request signal indicating a request for a change in the external clock signal frequency, and in response thereto monitoring the microprocessor to determine when a mode of operation of the microprocessor has occurred in which the instruction stream can be stopped. In response to the determination that such mode has occurred, operation is switched from the divide by one clock generator to the non-one divider type generator. A ready signal is then generated indicating that the change in the external clock signal frequency can be made. 
     According to one aspect of the present invention, when a completion signal is received, indicating the external clock signal frequency change has been made, operation is switched from the non-one divider type generator to the divide by one generator, after a period of time has occurred that is sufficient to allow the divide by one clock generator to stabilize. 
     Thus the present invention provides a dynamic frequency protocol that allows a microprocessor to contain a divide by one generator, and still have the ability to respond to a dynamic frequency shift without impacting the software stream. The result is that systems can still attain the power savings of frequency shifting, and still have the higher system performance of divide by one clocking as needed. 
    
    
     These and other objects and advantages of the present invention will be more apparent from the following more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a microprocessor modified in accordance with a preferred embodiment of the present invention. 
     FIG. 2 is a logic diagram of the DFS Interface Unit 20 of FIG. 1. 
     FIG. 3 is a logic diagram of the DFS Control Unit 30 of FIG. 1. 
     FIG. 4 is a block diagram of the Clock Unit 40 of FIG. 1. 
     FIG. 5 is a flow diagram setting forth the sequence of steps implemented in the method of a preferred embodiment of the present invention. 
     FIG. 6 is a diagram of certain signals that occur during operation of the embodiment shown in FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a microprocessor 1 according to a preferred embodiment of the present invention. A novel dynamic frequency shift (&#34;DFS&#34;) subsystem 10 is shown, as well as a conventional bus state machine 50. Other aspects of microprocessor 1 are well known in the art. To avoid obscuring the invention, detailed description of these other aspects of microprocessor 1 will be omitted, except as necessary for an understanding of how the preferred embodiment 10 interfaces with and interacts with such other elements. 
     The DFS Subsystem 10 includes three units, a DFS Interface Unit 20, a DFS Control Unit 30, and a Clock Unit 40. An external clock signal, CLK, is received at the input 13 of the Clock Unit 40, which generates internal clock signals of two different phases which are output on lines 41 and 42. Clock Unit 40 includes a divide by two clock generator and a divide by one clock generator, as is discussed in detail below. It will be understood that, in general, the number of clock output signals and their relative phase are dependent upon the particular requirements of the microprocessor with which the clock unit is associated. These considerations are well known in the art and are not discussed further herein. The DFS Subsystem 10 receives a request that an external clock frequency shift be allowed by way of an internal request signal on line 11, DFS --  REQI, and also, alternatively, by way of an external signal on line 12, DFS --   REQE, which are applied as inputs to the DFS Interface Unit 20. DSF --  REQE is provided by the external system (not shown) in which the microprocessor operates. DFS --  REQI is provided by an internal control register (not shown) that the system software can set. 
     The DFS Subsystem 10 Interfaces with the bus state machine 50 of the microprocessor 1. The operation of the bus state machine 50 is microprocessor dependent, and the principals that are applied thereto are well known in the art. In general, the bus state machine 50 monitors internal and external requests for utilization of the microprocessor bus (not shown) and grants access depending upon whether the bus is idle. An external bus request signal is received on line 53, an external bus grant signal is provided on line 54, an internal bus request signal is received on line 55 and the internal bus grant is provided on line 56. A signal called BUS --  IDLE, which is active, i.e., 1, when the microprocessor bus is idle, is provided on line 51. A signal called BUS --  HOLD is provided on line 31, and is activated when it is desired that the microprocessor bus, when idle, be held, that is, blocked from granting access to the bus in response to either an internal or an external bus request. When the bus is successfully held, a signal called BUS --  HELD is provided on line 52. The signals on lines 31, 51 and 52 are utilized in conjunction with the operation of the preferred embodiment, as is discussed in detail below. 
     When a DFS request signal is received by the DFS Interface Unit 20, either on line 11 or 12, and signal line 51 is active, indicating that the bus is idle, an internal DFS --  REQ signal is passed to the DFS Control Unit 30 on line 23. This causes the BUS --  HOLD signal to be applied to line 31 by which it is transmitted to the bus state machine 50. When the bus state machine determines that the bus has, in fact, been held, it activates line 52 with BUS --  HELD, which is applied to the DFS Control Unit 30. 
     This causes a signal called SLOW --  MODE to appear on line 32, which causes a request for a switch from the divide by one clock in clock unit 40 to the divide by two clock therein. 
     At the same time, a DFS --  RDY signal is applied to line 38 and thence to line 21. The external clock, upon receiving the DFS --  RDY signal, begins its dynamic frequency shift to a lower frequency. Since, as this is occurring, the divide by two clock is operational to provide the microprocessor internal clock signals, no disruption occurs in microprocessor operation. 
     Once the frequency shift is completed, the DFS request line 11 or 12 is deactivated, i.e., goes to 0. This is communicated to the DFS control unit 30 by way of line 23. Once a sufficient period of time has passed to allow the divide by one clock in clock unit 40 to stabilize, line 32 is deactivated, causing the clock unit 40 to switch to operation using the divide by one clock generator. 
     The foregoing general description of the operation of the preferred embodiment 10 of the present invention is intended to provide a general understanding of such operation. A detailed description of the operation is set forth hereinbelow. In this detailed discussion, reference will be made to FIG. 1, which shows the overall interconnection of the various units of the DFS Subsystem 10, FIG. 2 which shows the internal logical structure of the DFS Interface Unit 20, FIG. 3 which shows the internal logical structure of the DFS Control Unit 30, FIG. 4 which shows the internal logical structure of the Clock Unit 40, and FIG. 5 which is a flow diagram showing all of the steps in the sequence of operation of the preferred embodiment in changes from fast mode to slow mode and back again to fast mode. In addition, FIG. 6 shows the relationship between the DFS --  REQ, DFS-RDY and CLK signals during a shift from a higher frequency, f1, to a lower frequency, f2. 
     In the following discussion, the primary reference figure will be FIG. 5, which sets forth the logical sequence of the steps. As these steps are described, reference will be made to FIG. 1, FIG. 2, FIG. 3 or FIG. 4, as the case may be to assist the reader in understanding which of the logical elements are involved in the particular step in FIG. 5. The logic elements shown in FIGS. 2, 3 and 4 are conventional, such as AND gates and OR gates. PLA 1 and PLA2, shown in FIG. 3, implement the functions shown in Table 1. Design of PLAs to a given function is a well known art, and therefore details of implementation are omitted herein. 
     
                       TABLE 1______________________________________PLA 1:IF DFS.sub.-- RDY goes to 0, AND IF BUS.sub.-- IDLE = 1,AND IF DFS.sub.-- REQ = 0,THEN generate BUS.sub.-- HOLD.IF SLOW.sub.-- MODE = 0, THEN release BUS.sub.-- HOLD.PLA 2:IF τ goes to 0, AND IF SLOW.sub.-- MODE = 1,AND IF BUS.sub.-- HELD = 1,THEN let output go to 0.IF τ goes to 1, THEN let output go to 1.______________________________________ 
    
     Referring now to FIG. 5, it is assumed that the DFS Subsystem 10 (FIG. 1) begins in fast mode 601. In this state the external clock signal CLK is provided on line 13 at the higher external clock frequency, and the DFS request lines 11, 12 are deactivated (FIG. 2). Note that block 24 represents a register. Thus, if line 11 is activated, the data is stored in register 24, and communicated to line 22. If a DFS request line 11, 12 goes active 602 (FIG. 5) the system waits for the bus idle signal to go active 603. Referring to FIG. 2, it will be seen that OR gate 25 communicates the signals on lines 11 and 12 to a single input of AND gate 26, where that signal is ANDed with the BUS --  IDLE signal line 51 to activate line 23, carrying DFS --  REQ. 
     If the DFS request signal line (output of OR gate 25) is still active when the BUS --  IDLE signal is detected on line 51, (step 604 in FIG. 5), then a request 605 is made for the BUS --  HELD signal to be activated. This is accomplished by the activation of the BUS --  HOLD signal line 31, as shown in FIG. 3. Once the BUS --  HELD line 52 is activated, provided that signal line 23, carrying the DFS --  REQ line, is still active, then AND gate 34 passes the slow mode request signal, SLOW --  MODE, through OR gate 35 to signal line 32. The signal on line 32 is applied to the multiplexer 45 shown in FIG. 4 to effect the change from the divide by one clock 43 to the divide by two clock 44. 
     Note, in FIG. 5, that steps 602 and 604 show that if the DFS request signal drops out at either of those steps, the DFS shift is aborted, and the microprocessor continues in fast mode. Similarly, as shown by the negative path in step 606, if the BUS --  HELD signal is not immediately forthcoming, both BUS --  IDLE and DFS --  REQ must continue active, or else the shift aborts and the system remains in fast mode, as shown by the negative path from step 604. 
     Note also, in FIG. 4, that divide by one clock generator 43 and divide by two clock generator 44 both output signals of different phases, indicated as as PH1 and PH2. Multiplexer 45 selects both of these output signals when a particular clock generator is selected. Phase 1 is output on line 41 and phase 2 is output on line 42. 
     Continuing now in FIG. 5 beginning with step 607, the subsystem is in slow mode. In slow mode, the DFS Subsystem 10 generates (step 608) the signal DFS-RDY which is provided on line 38 (FIG. 3) to register 24 (FIG. 2), where it is output on line 21. 
     Once DFS --  RDY is generated, the system can change the frequency of CLK. Once this change is complete, the system remains in Slow mode until the DSF --  REQ signal line 11 or 12 (FIG. 2) is deactivated 609. DFS --  RDY goes to 0 at this point. PLA 1 then waits for the BUS --  IDLE signal on line 51 (step 610) and if the DSF --  REQ line remains inactive 611 a BUS --  HOLD signal is generated 612. PLA 2 waits for the BUS --  HELD signal line 52 to go inactive and waits for the clock to stabilize (τ propagation, 37) 613. The circuitry that permits stabilization of the clock is implemented in time delay circuit 37 in FIG. 3. When signal line 38, which is the output of AND gate 34, goes low, the output of element 37 remains high for a period of time τ, holding output line 32 active for that period of time, at the end of which signal line 32 is released. Since SLOW --  MODE is 0, the output of PLA 2 goes to a 0, resulting in SLOW --  MODE going to 0, i.e., fast mode is invoked. 
     Thus, it has been shown that in accordance with the invention a microprocessor may be provided with a divide by one clock generator, while still having the capability of responding to a dynamic frequency shift of the external clock generator. Many variations and the circuitry and sequence may be made by those skilled in the art, once the principals of the invention, as expressed herein, are understood. For example, the preferred embodiment set forth above operates in conjunction with a microprocessor in which the switch from SLOW --  MODE to FAST --  MODE and from FAST --  MODE to SLOW --  MODE occurs in a single cycle. Thus, the same signal that triggered the shift from SLOW --  MODE to FAST --  MODE, and vice versa, was provided as the DFS --  RDY signal. In other microprocessors, if more than one cycle is required to effect such a switch an additional gate may be required to hold off the sending of the DSF --  RDY signal, pending activation of a single signal line indicating completion of the shift. 
     In addition, while the embodiment disclosed herein is implemented in a combination of PLAs and combinatorial logic, in general the implementation in silicon is widely variable depending on the design system and designer preferences. For example, it is conceivable that the entire embodiment might be implemented in a single PLA, or entirely in combinatorial logic. The following claims are intended to encompass all such modifications.