Abstract:
The present invention comprises a direct digital frequency synthesizer. A phase accumulator provides a normalized angle θ to a sine/cosine generator that outputs the value of the sine/cosine function at the provided angle. The she/cosine generator in a preferred embodiment comprises a plurality of multiplierless butterfly and carry-save stages in cascade that perform angle rotations on a phasor on the unit circle whose x and y coordinates correspond to cosine and sine values. To calculate the sine and cosine values at a particular angle θ=b 1  θ 1  +b 2  θ 2  +. . . +b N  θ N  where b k  ε {0, 1} are the binary bits and the θ k  =2 -k  are the associated positional weights, each of the butterfly and carry-save stages rotate the phasor by an amount θ k  =2 -k . The direction of the rotation, clockwise or counter-clockwise, depends upon the value of the binary bits b k . After undergoing all of the rotations, the phasor has x and y coordinates that approximate the desired cosine and sine values to a specified accuracy. In a preferred embodiment, the datapath of the present invention is multiplierless. The stages for angles where the approximation tan θ k  =θ k  is acceptable are multiplierless while for angles where this approximation does not hold, the x and y phasor coordinates are transformed through a multiplexer or a ROM.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to digital signal generators and more particularly to Direct Digital Frequency Synthesizers (DDFS). 
     2. Art Background 
     For many digital circuits, it is often necessary to generate a sequence of sample values of a sine or cosine function at a particular frequency that may be adjusted while the interval between samples remains fixed. Circuits known as Direct Digital Frequency Synthesizers (DDFS) perform this function. Many prior art DDFS&#39;s generate the sine and cosine values by performing a table-lookup in a read only memory (ROM) that contains the values of samples of a sine/cosine function at the required angle values, and then providing these values as the output. The sequence of desired angles is generated by a phase accumulator. More precisely, the phase accumulator produces a sequence of normalized angles that are used to address the ROM. The table-lookups are performed at a very precisely controlled rate, which is the sample rate, and the desired frequency of the generated sinusoid is determined by the rate, relative to this reference rate, at which angles generated by the phase accumulator cycle through a range of values corresponding. to 0 to 2π. 
     Although these prior art table-lookup DDFS&#39;s perform adequately for many purposes, the tables often are large and occupy a relatively large amount of chip area when implemented as integrated circuits. Various techniques have been developed to reduce the ROM table size, which is determined by the number of address bits (i.e., the phase accumulator output) and the precision of (i.e., the number of bits representing) the sine/cosine outputs. Truncation of the phase accumulator output is usually employed in order to reduce the lookup table size, as this size will double with each additional bit in the table address word. Truncation, however, creates imperfections in the output sine/cosine function since a truncated sine/cosine value will correspond to an effective angle that is different from the sine/cosine value at the exact angle. Furthermore, the truncated phase accumulator values can be viewed as values obtained by adding some sequence of error terms to the sequence of exact angle values. Thus, the output of the table-lookup process will consist of the superposition of the sine/cosine signal at the desired frequency and various other frequencies that result from the processing of the error sequence by the table-lookup. These undesired frequency components are referred to as &#34;spurious frequencies,&#34; or &#34;spurs.&#34; The amplitude of these spurs should be small, and the quality of the DDFS is often assessed by determining how small the spurs are. The &#34;spurious free dynamic range&#34; is the difference between the amplitude of the desired sinusoid and that of the largest spur. It is usually measured in decibels (dB). 
     DDFS designs recently reported achieve 80 to 90 dB spurious-free dynamic range (SFDR) using a 15-bit ROM address. It is well known that each additional ROM address bit typically reduces spurs by approximately 6 dB. In addition to the spurious frequency content due to phase accumulator truncation, another cause of spurs is the need to truncate the actual sine/cosine values stored in the table. Since it is impossible to store infinite precision values in the table, such error is inevitable. One must store enough bits that an adequate approximation is given, but increasing the output precision causes a linear expansion in the ROM size; that is the ROM size varies linearly with the number of bits in the data values. As the ROM table becomes larger, it is difficult to achieve high-speed operation and low power dissipation with small chip area. 
     One prior art technique for generating trigonometric functions such as sine and cosine, developed in the 1950&#39;s and known as CORDIC, avoids ROM table-lookups. CORDIC calculates the sine and cosine values of a particular angle through a series of rotations of a phasor, initially coincident with the X-axis on the unit circle. The X-axis and the Y-axis coordinates of the phasor at the final angle are the desired cosine and sine values, respectively, as shown in FIG. 1. In principle, the X.sub.θ =cos θ and Y.sub.θ =sin θ coordinates can be computed from an initial point X 0  =1, Y 0  =0 by ##EQU1## This computation cannot be implemented directly since the sin θ and cos θ coefficients are themselves the variables to be determined. However, the computation can be broken into a sequence of subrotation computations, as shown in FIG. 2, that can be implemented. If θ=α 1  θ 1  +α 2  θ 2  +. . . α N  θ N , where θ 1  =tan -1  2 -i  and α i  ε {-1, 1}, no multiplications are required to perform the rotations except for binary shifts since tan (tan -1  2 -i )=2 -i . The rotation by θ can now be written as ##EQU2## 
     However, according to the CORDIC methodology, at each rotation it must be determined whether to rotate clockwise or counter-clockwise, where a counter-clockwise rotation corresponds to α i  =1 and a clockwise rotation corresponds to α i  =-1. CORDIC tries to approximate an angle θ as a sum of angles Σθ i . At each stage, if the approximation generated by all previous stages is larger than the desired angle θ, then the current stage decreases the value of the approximation by θ i  ; otherwise the approximation is increased by θ i . Thus, at each stage the direction of the rotation is chosen such that the error between the desired angle θ and the approximation is reduced. In CORDIC, the α i  coefficients (which determine the direction of the rotation) are determined iteratively for each rotation stage and each one requires a comparator or its equivalent. 
     The present invention provides a new approach to DDFS that is superior to current ROM and CORDIC based approaches. 
     SUMMARY OF THE INVENTION 
     The present invention provides a high-speed DDFS integrated circuit with high precision sine and cosine output data and a chip area smaller than could be obtained using table-lookup-based or CORDIC approaches to the DDFS. According to the present invention, a phase accumulator provides a sequence of angles to a sine/cosine generator that outputs a sequence of values of the sine/cosine function at a desired frequency. The sine/cosine generator in a preferred embodiment comprises a plurality of multiplierless butterfly and carry-save stages in cascade that perform angle rotations to calculate the sine and cosine values for each desired angle. The angle rotations are chosen to implement a series of transformations that result in closer and closer approximations to the sine and cosine values of the desired angle. 
     As previously described, the computation of sin θ and cos θ for a given θ can be viewed as the computation of the X-axis and the Y-axis coordinates of a point on the unit circle. This point can be located by rotating a phasor counter-clockwise from an initial position coincident with the X-axis through an angle θ, which may be represented by the computations: ##EQU3## In this equation, b 1  θ 1  +b 2  θ 2  +. . . +b N  θ N  is the binary representation of θ where b k  ε {0,1} are the binary bits and the θ k  =2 -k  are the associated positional weights. The subangles are θ k  =2 -k  radians. Thus, unlike CORDIC, the coefficients b k  in the angle expansion are determined directly from the binary representation of the angle. Also, the angles themselves are different from those of CORDIC. For example, the first CORDIC rotation angle is (tan -1  1/2) radian while our first rotation angle is 1/2 radian. The binary b k  ε{0,1} can be recoded into signed digits r k  ε{-1,1} for an arbitrary angle θ by the mapping r k  =2b k-1  -1. Each butterfly and carry-save stage implements a transformation that corresponds to one of the rotation matrices in the above equation and the sign of the coefficient r k  dictates the direction of rotation. Since the coefficients r k  are determined from the binary coefficients b k , the present invention, unlike CORDIC, does not require an angle comparison at each stage to determine whether the angle rotation is clockwise or counter-clockwise. 
     For sufficiently small θ k  (i.e., for sufficiently large k) the approximation tan θ k  =θ k  =2 -k  reduces the corresponding multiplication performed by the butterfly and carry-save stages to a simple shift operation by a fixed number of bits (k bits). This approximation causes no loss of accuracy in the tan θ k  representation so long as θ k  is sufficiently small that the difference (θ k  -tan θ k ) is smaller than the finite-precision limits of the data. 
     In a preferred embodiment, a multiplexer provides sine and cosine values for an angle that is the sum of the first M subangles θ k , those that are not sufficiently small to employ the approximation tan θ k  =θ k . The angles become successively smaller for each successive stage and the remaining angles after these first M angles satisfy the approximation tan θ k  =θ k  to a desired accuracy. The sine and cosine values provided by the multiplexer are then input to the subsequent rotation stages, which perform the above rotations to calculate the sine and cosine values for the desired angle. Rather than using a multiplexer, a small ROM table can also be used to perform the same function. 
     Only angles in  0,π/4! need be provided to the rotation stages and the sine and cosine values for any angle in  0,2π! can be computed from these angles by well known trigonometric identities. The present invention includes methods and apparatus for converting an angle in  0,2π! to a related angle in  0,π/4!, performing the previously described rotations to calculate sine and cosine values for the transformed angle, and then deriving the sine and cosine values for the original angle in  0,2π! from the sine and cosine values for the transformed angle in  0,π/4!. 
     To summarize, an angle θ=b 1  θ 1  +b 2  θ 2  +. . . +b N  θ N  is generated where b k  ε {0,1} are the binary bits and the θ k  =2 -k  are the associated positional weights. Next, the sine and cosine values for a subangle ω, the sum of the first M rotation angles of θ, are obtained through a multiplexer or similar device (e.g., ROM table). In a preferred embodiment, ω is chosen such that the remaining subangles that are processed obey the approximation tan θ k  =θ k  and the binary b k  ε{0,1} are recoded into signed digits r k  ε{-1,1} for an arbitrary angle θ by the mapping r k  =2b k-1  -1. The following transformation formulae are then used: 
     
         X.sub.k =X.sub.k-1 -r.sub.k 2.sup.-k Y.sub.k-1 
    
     
         Y.sub.k =Y.sub.k-1 +r.sub.k 2.sup.-k X.sub.k-1 
    
     where X k-1  is the cosine value and Y k-1  is the sine value. The determined X k  cosine value and Y k  sine value are then successively provided as the X k-1  and Y k-1  inputs to the transformation formulae until the desired accuracy is reached. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The objects, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiment of the invention with references to the drawings in which: 
     FIG. 1 shows the computation of sin θ and cos θ for a given θ as the computation of the X-axis and the Y-axis coordinates of a point on the unit circle. 
     FIG. 2 shows the computation of sin θ and cos θ for a given θ as a series of subrotations. 
     FIG. 3 is a block diagram of a Direct Digital Frequency Synthesizer (DDFS) with a phase accumulator that provides an angle to a sine/cosine generator that outputs the value of the sine/cosine function at the provided angle. 
     FIG. 4 is a block diagram of the preferred embodiment of the Direct Digital Frequency Synthesizer (DDFS) of the present invention. 
     FIG. 5 illustrates the cascade of feed-forward butterfly stages that comprise the computation required by the sine/cosine generator illustrated in FIG. 3. 
     FIG. 6 illustrates the hardware implementation of the butterfly stages illustrated in FIG. 5. 
     FIG. 7 is a table showing 22-bit tangent values for particular angles and, in particular, that tan θ=θ to full 22-b accuracy for the angles in rows 7 through 10. 
     FIG. 8 illustrates output control select circuitry for the DDFS of FIG. 4. 
     FIG. 9 is a flow chart of the present invention. 
     FIG. 10 shows a general block diagram of the carry-save stages. 
     FIGS. 11a-11b show the carry-save stages of FIG. 4 in greater detail. 
     FIG. 12 is a block diagram of a vector merge adder that is used in conjunction with the carry save stages illustrated in FIG. 4. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention discloses an improved Direct Digital Frequency Synthesizer. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known circuits, structures, and the like are not described in detail so as not to obscure the present invention unnecessarily. 
     FIG. 3 is a block diagram of a Direct Digital Frequency Synthesizer (DDFS). A phase accumulator 10 provides a normalized angle θ to a sine/cosine generator 12 that outputs the value of the sine/cosine function at the desired angle. The sequence of normalized angle values is provided by the phase accumulator 10 at a very precisely controlled rate, which is the sample rate, provided by a clock (not shown). The desired output frequency of the generated sequence of sine/cosine function values is determined by the rate, relative to the sample rate, at which the values generated by the phase accumulator cycle through the (normalized) range of values corresponding to the range 0 to 2π. This rate and, hence, the output frequency of the generated sine/cosine signals may be adjusted by supplying different frequency control words f 0  to the phase accumulator, as shown in FIG. 3. 
     FIG. 4 is a block diagram of the preferred embodiment of the DDFS of the present invention. A normalized angle is provided by the phase accumulator 10 to a π/4-quadrant mirror 14 and a π/4-multiplier 13 whose functions will be described more fully below. Components of the output of the π/4-multiplier 13 (an angle θ in radians) are provided in parallel to a plurality of stages, including a ROM 16, a plurality of butterfly stages 18, and a plurality of carry-save stages 20. The ROM 16, butterfly 18 and carry-save stages 20 calculate cosine and sine functions from the angle θ provided by the π/4-multiplier 13. A vector merge adder (&#34;VMA&#34;) 21 is coupled to the last carry-save stage 20 and is further coupled to an output stage 22 that maps the computed cosine/sine values in  0,π/4! to the appropriate values in  0, 2π!. 
     As previously described, the computation of sin θ and cos θ for the angle θ provided by the π/4-multiplier 13 can be viewed as the computation of the X-axis and the Y-axis coordinates of a point on the unit circle, as shown in FIG. 1. The computation can be broken into a sequence of subrotation computations as shown in FIG. 2. In accordance with the present invention, each subrotation corresponds to a known angle. In general, the arbitrary angle θ(&lt;1 radian) can be expressed as θ=b 1  θ 1  +b 2  θ 2+ . . . +b N  θ N  where b k  ε{0, 1} are the binary bits of the angle θ and the θ k  =2 -k  are the associated positional weights. For example, for θ=0.5 radian, θ=(0)2 0  +(1)2 -1  +(0)2 -2  +. . . (0)2 -N  which is 010000 . . . 0 represented in binary. Thus b k  =1 corresponds to a subrotation by θ k  =2 -k  and b k  =0 corresponds to &#34;no rotation.&#34; The rotation by θ can now be written as: ##EQU4## This formula has the same form as the CORDIC transformation. However, unlike CORDIC, the coefficients b k  comprise the bits of the angle representation, expressed as a base-2 radian value, and thus each subrotation direction need not be determined iteratively by specialized circuitry as CORDIC requires. This is possible because the angles themselves are different from those of CORDIC. For example, the first CORDIC rotation angle is (tan -1  1/2) radian while our first rotation angle is 1/2 radian. 
     FIG. 5 illustrates a plurality of cascaded feed-forward butterfly stages which may be used to implement the above rotation. The stages illustrated in FIG. 5 effect a sequence of rotations that is always started from the fixed point X 0  =1, Y 0  =0, where the desired output precision determines the number of stages and the rotation angle at each stage is known (θ k  =2 -k ). Each butterfly stage corresponds to one of the transformation matrices in the above equation and the direction of rotation of each stage is determined directly by the binary representation of the angle θ expressed in radians. 
     According to a preferred embodiment of the present invention, various refinements are made on the butterfly stages illustrated in FIG. 5. It can be shown that the binary b k  ε{0,1} can be recoded into signed digits r k  ε{-1,1} for an arbitrary angle θ by the mapping r k  =2b k-1  -1 and thus each butterfly stage, for any θ, consists of either a positive or negative θ k  subrotation, depending upon the sign of r k . Therefore the product K=cos(r 2  θ 2 ) . . . cos(r N+1  θ N+1 ) becomes a constant. Thus, the rotations are started from the fixed point X 0  =Kcosφ 0 , Y 0  =Ksinφ 0  rather than at the point X 0  =1, Y 0  =0, where φ 0  is an initial rotation by (0.5-0.5 N+1 ) radians. This eliminates the need to scale the final results by K. 
     Multipliers may be eliminated from the butterfly stages illustrated in FIG. 5 by taking advantage of the approximation tan θ k  =θ k . For sufficiently small θ k  (i.e., for sufficiently large k), the approximation tan θ k  =θ k  =2 -k  reduces the multiplications performed by each butterfly stage to simple shift operations by a fixed number of bits (k bits). This approximation causes no loss in accuracy in the tan θ k  representation so long as θ k  is sufficiently small that the difference (θ k  -tan θ k ) is smaller than the finite-precision limits of the data. More precisely, given a B-bit internal word length, tan 2 -k  =2 -k  to the full precision of the data for all k&gt;B/3. For example, FIG. 7 shows values of tan 2 -k  and 2 -k  for k=1, . . . , 10 with 22-bit data. For all stages where k&gt;B/3=22/3 (i.e., for k&gt;7) there is no loss of accuracy when the butterfly computations of FIG. 5 are reduced to a pair of shift (by a fixed number of bits) and add operations. In a preferred embodiment, since the initial values X 0 , Y 0  are always the same, the first B/3 butterfly stages are merged together and implemented using the ROM 16, illustrated in FIG. 4, thereby avoiding the use of any tan θ k  multipliers. (While this would require a table containing 128=2 7  sine and cosine entries, simulations have shown that, in fact, the required accuracy can be maintained for the final output values if only the first four stages are replaced by the ROM 16. This introduces small errors in making the tan θ˜θ approximation for butterfly stages 5 through 7, but requires a table of just 16=2 4  sine and cosine values.) As will readily be appreciated, a multiplexer or other device may be employed instead of the ROM 16. 
     To minimize the size of the ROM 16, it is provided with the value θ in radians as opposed to the normalized value of θ provided by the phase accumulator 10. The ROM 16 may thus be smaller since the bit patterns that represent θ in radians are fewer than those of the normalized angle. For example, the value of π/4 in binary is 011001. . . . Thus, for radian angles used to access the 16-word ROM, the largest value the address bits can have is 1100, which implies that only a 13-word ROM is required. (The remaining three addresses are never used.) 
     FIG. 6 illustrates a preferred hardware implementation, including the refinements discussed above, of the butterfly stages 18 illustrated in FIG. 4. Each butterfly stage comprises two multipliers 24 and 26 and two adders 28 and 30. The multiplier coefficient c i  is equal to 2 -i  or -2 -i , depending upon the value of r i  =2b i-1  -1 as shown. Each b i  value corresponds to the binary value of the i-th bit of the angle and the b i  values are provided to the stages as illustrated in FIG. 4. 
     With reference to FIG. 4, the ROM 16 receives the four most significant bits of the angle provided by the π/4-multiplier 13 which are used to select one of thirteen 22-bit values that comprise the tangent of the angle that would otherwise result when rotating the input (K cos φ, K sin φ) through the angle ω using the first four butterflies. Simulation results show that 16-bit accuracy can be retained on the sine and cosine outputs while employing the tan 2 -k  =2 -k  approximation for all stages beyond Stage 4 with a 22-bit internal word length. 
     Additional savings in chip area can be obtained by employing carry-save arithmetic. According to the present invention, the m final butterflies after stage i=(B-1)/2 can be merged together such that X i+m  and Y i+m  can be obtained directly from X i  and Y i  as follows: ##EQU5## The above equations are obtained by applying the m butterfly rotations repeatedly until (X i+m , Y i+m ) are expressed in terms of (X i , Y i ). In doing this, all terms involving products of the form (r k )(r k+1 )(tan 2 -k-1 )(tan 2 -k ) can be discarded whenever k&gt;B/3 and k≧(B-1)/2. The first inequality allows the tan θ k  multipliers to be represented by a power-of-two and the second inequality ensures that the product corresponds to a shift fight by a number of bits greater than the word length of the datapath. FIG. 10 shows a general block diagram of the carry-save stages and FIGS. 11a-11b illustrate the carry-save stages of the preferred embodiment of FIG. 4 in greater detail. 
     As shown in FIG. 4, the &#34;1 st  -quadrant π/4 mirror&#34; 14 control block receives the third most significant bit of the normalized angle and the 19 least significant truncated phase accumulator bits, denoted by θ. The third most significant bit indicates whether the desired angle is in the upper or lower half of any quadrant. The &#34;1 st  -quadrant π/4 mirror&#34; 14 comprises a subtracter replacing θ by (1-θ) whenever the desired angle is in the upper half of any quadrant. 
     The π/4-multiplier 13 of FIG. 4 converts the normalized phase accumulator and π/4-mirror output θ to a value θ in radians. In the preferred embodiment it comprises five hard-wired partial products. 
     By putting the 1st-quadrant mirror 14 before the π/4-multiplier 13 it then deals with a normalized angle θ and hence its subtracter implements the replacement of θ by (1-θ) whenever θ is greater than 1/2. An alternate implementation would reverse the order of occurrence of the two blocks. This would require the π/4-mirror 14 to perform subtractions (π/2-θ). The (1-θ) subtraction requires less hardware to implement than the (π/2-θ) subtraction, as (1-θ) can be implemented by just performing exclusive-OR operations on the bits of θ. 
     The VMA 21 illustrated in FIG. 4 produces the final cosine/sine values from the datapath outputs. The VMA 21 combines the carry and sum outputs from the carry-save stages to produce two&#39;s complement values for the datapath&#39;s X n  and Y n  outputs. These output values are then used in the output-select circuit 22, as illustrated in FIG. 8, to map the computed X n  and Y n  values in  0,π/4! to the appropriate cosine/sine values in  0,2π!. FIG. 12 shows a block diagram of the VMA 21 of the preferred embodiment. 
     Since the computed angles lie in the interval  0,π/4!, and all angle rotations are performed in the first quadrant, the X k  and Y k  values computed by the butterfly stages 18 are always positive. This has the important architectural consequence that no sign-extensions are ever required when shifting the data by k bits (i.e., the 2 -k  multiplier), thereby reducing the load on the MSB&#39;s at each stage and facilitating high-speed operation. 
     For a DDFS where only one output is needed (either cosine or sine), further reduction in the amount of required hardware can be obtained. For example, to produce only the cosine output, the circuitry used to compute the sine output can be discarded after stage (B-1)/2 where &#34;butterflies&#34; are no longer required and the computation can be performed in parallel using carry-save arithmetic. This, however, requires that values be computed for angles in  0,π/2!, as opposed to  0,π/4!, because sine output values are not available to swap with cosine values whenever the angle is in the upper half of the quadrant. 
     An additional hardware reduction can be achieved for a DDFS which requires no butterflies after the ROM implementation of the initial stages. That is, for cases where a ROM is used for the initial (B-1)/2 stages and the remaining stages can be implemented using parallel carry-save arithmetic without butterflies. One example would be a DDFS with 10-bit output precision where a 26-word ROM is used for the first 5 stages and the remaining stages are implemented using carry-save arithmetic without butterflies. For such cases, the π/4-multiplier hardware that converts the normalized angle θ to a radian value θ can be eliminated by factoring out the radian conversion factor from the tan θ k  rotation multipliers and including that information in the values stored in the ROM table. This is valid since the stages following the ROM use the tan θ k  =θ k  approximation and the X N  and Y N  output values can be computed directly from the ROM outputs without butterflies. 
     To emphasize that the present invention may be implemented with hardware embodiments other than those described with reference to FIG. 4, FIG. 9 is a flow chart of the present invention. At block 40, θ=b 1  θ 1  +b 2  θ 2  +. . . +b N  θ N  is generated where b k  ε{0, 1} are the binary bits and the θ k  =2 -k  are the associated positional weights. At block 42, the sine and cosine values for a subangle ω of θ are obtained through a multiplexer, table-lookup, or similar device. In a preferred embodiment, ω is chosen such that subsequent subangles that are processed obey the approximation tan θ k  =θ k . At block 44, k is set equal to M+1 and at block 46, the binary b k  ε{0, 1} are recoded into signed digits r k  ε{-1,1} for an arbitrary angle θ by the mapping r k  =2b k-1  -1. The sine and cosine values determined at block 42 are inputs to the formulae: 
     
         X.sub.k =X.sub.k-1 -r.sub.k 2.sup.-k Y.sub.k-1 
    
     
         Y.sub.k =Y.sub.k-1 +r.sub.k 2.sup.-k X.sub.k-1 
    
     where X k-1  is the cosine value and Y k-1  is the sine value. The determined X k  cosine value and Y k  sine value are then provided as inputs to the formulae in block 48, repeatedly, as k is incremented, until the desired accuracy is reached, as shown at blocks 50 and 54. At block 52, the final X and Y values, corresponding to the desired cosine and sine values, are output. 
     Although the present invention has been described in terms of a preferred embodiment and with reference to FIGS. 1-12, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit and scope of the invention. The invention should therefore be measured in terms of the claims which follow.