Abstract:
Methods and apparatus for a non-invasive test tool for testing and monitoring the interactions between an embedded microprocessor and its programs, various input analog and discrete electrical signals, and an LCD output display screen. The test tool uses a physical probe, preferably coupled in a non-invasive manner to the pins of the LCD display screen, and specialized hardware to capture the LCD output of the software-under-test as an event interaction between the microprocessor and various inputs. The captured LCD output is converted to a standard pixel format and stored for testing. The standard pixel format comprises a color and/or intensity value for each pixel position of interest, stored into a data structure. One embodiment uses a conversion which includes adding the time-modulated pixel data of a plurality of frames to generate a single composite frame having a color and/or intensity value for each pixel position of interest.

Description:
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyrights whatsoever. 
     FIELD OF THE INVENTION 
     The present invention relates to methods and apparatus for testing computers, and more specifically to in-situ testing of computers having liquid-crystal graphics displays in order to determine whether specific displays of text and/or graphics result from specific input stimuli. 
     BACKGROUND OF THE INVENTION 
     Computer systems which output text and/or graphics to liquid-crystal display (&#34;LCD&#34;) graphics displays must be tested. Such testing can be assisted by test tools called software verification and validation (&#34;V&amp;V&#34;) or computer-aided software testing (&#34;CAST&#34;) tools. 
     Particularly crucial is the testing of medical devices (e.g., blood hematology cell count instruments, chemistry analyzers, and/or coagulation analyzers) having embedded controllers which output to color LCD screens such as are commonly used as visual output screens for lap-top computers. It is generally not sufficient to test such devices by testing the computer as connected to a cathode-ray tube (CRT) display device (i.e., checking the bit pattern as captured by a frame grabber which samples, for example, the scan-line output of a video-graphics adaptor (VGA) card), since regulating agencies frequently require testing of the actual complete systems in the configuration which they will be used, and the colors or graphical effects of LCD display screens generally differ from those produced on a CRT display screen. One of the main functions being verified in such tests is that the embedded software operates correctly and in response to a particular input stimulus properly outputs a particular image, color, and/or text to the LCD display screen. 
     Embedded microcomputers are computers which perform control and monitoring functions within some other device. Many embedded controllers are now having displays such as color LCD screens attached. Often, there is no computer-type interface (such as a alpha-numeric typewriter-style keyboard) for such computers. Examples of devices having such embedded microcomputers are electro-cardiac graphics (EGG) monitors, household appliances having &#34;smart&#34; controllers, and automobile engine controllers. 
     Because such embedded computers often do not have the keyboard typical of other computers, specialized equipment and methods must be used to test the programs which run in these computers. Although particularly suited for testing what are typically defined as embedded computers, such testing equipment can also be used to test other types of computers as well. 
     Some computers include analog subsystems which interface the microcomputer to and from various analog signals. Some computers include discrete subsystems which interface the microcomputer to and from various discrete electrical signals. 
     In the prior art are test systems which attach to the pins of a microprocessor while the microprocessor is attached to a circuit (thus being part of, for instance, a personal computer), and wherein the test system provides &#34;character-based&#34; stimulus-response testing and monitoring of the programs running on the microprocessor. For instance, the test system could simulate a keyboard subsystem and test the responses to various combinations of keyboard input without having to have a human press the various key combinations. Other &#34;character-based&#34; prior-art test systems have included testing computer character-display subsystems, and logic-state analyzers which monitor the addresses, data and instructions which come across the pins of the microprocessor being monitored. Such systems which test signals at the pins of the microprocessor-under-test, rather than at the pins of the LCD display cannot see effects which may be caused by the LCD controller electronics or from the interaction of the microprocessor with such electronics, and thus while the signals leaving the microprocessor may look correct, the actual display may not be correct. Other prior-art systems are capable of monitoring and analyzing signals driven by CRT adaptor circuits (e.g., such commonly available circuits as the standard VGA adaptor circuit which generates video-type signals to drive a VGA display CRT). 
     While certain individual types and combinations of LCD-display controllers and LCD display panels (or &#34;LCD display screens&#34;) may be susceptible of having their drive signals captured and analyzed by much the same circuitry and programming as can be used to capture and analyze the signals driving a standard CRT (i.e., because such LCD systems emulate or utilize the signals between a VGA adaptor card and a VGA display CRT), many, if not most, LCD-display controller/LCD-display panel combinations utilize unique signals which are quite different in format, timing, and protocol than those of a standard VGA. 
     What has been lacking in the prior art are test systems which provide easy, accurate, adequate or comprehensive testing of LCD displays connected to computers and embedded microcomputers in particular. 
     What is needed are reliable, accurate and repeatable test systems and methods for testing display outputs of computers which drive LCD graphics and textual displays. 
     SUMMARY OF THE INVENTION 
     The present invention provides a method and apparatus for a non-invasive test tool for testing and monitoring the interactions between an embedded microprocessor and its programs, various input analog and discrete electrical signals, and an LCD output display screen. The test tool uses a physical probe, preferably coupled in a non-invasive manner to the pins of the LCD display screen or elsewhere along the electronic path to the screen from the computer, and specialized hardware to capture the LCD output of the software-under-test as an event interaction between the microprocessor and various inputs. The LCD output signal for a particular pixel generally varies over time as a function of the desired intensity or color for that pixel, even for &#34;static&#34; displays of data. This time-varying signal is analyzed and converted into an intensity or color value (representing the intensity or color as perceived by a human observing the display) for each pixel of interest on the display, and inserted into a common data structure representing the entire display. The set of values in the common data structure are then compared to an expected set of values to determine whether portion of the software-under-test is functioning properly. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an exemplary generalized test system 80 for a device-under-test 100 according to the present invention for testing outputs to an LCD display screen from a computer. 
     FIG. 1A shows one embodiment of the present invention, wherein device-under-test 100 is a cardiac monitor system. 
     FIG. 2 shows details of some of the functions provided by LCD signal capture and conversion circuit 200. 
     FIG. 2A shows one embodiment of the present invention, wherein signal converter 260, which includes conversion circuit 200 or the software used to control the conversion process, or both, includes a bit-masked change filter 248. 
     FIG. 3 shows an overview of the functions provided, in one embodiment, by test software 350 running in test-control computer 300. 
     FIG. 4 shows a more detailed flow diagram of one embodiment of the make-bit-map software routine 351 according to the present 
     FIG. 4A shows a more detailed flow diagram of one embodiment of the make-bit-map software routine 351 according to the present invention. 
     FIG. 4B shows a more detailed flow diagram of one embodiment of the converting step 451 according to the present invention. 
     FIG. 4C shows a more detailed flow diagram of another embodiment of the converting step 451 according to the present invention. 
     FIG. 4D shows a more detailed flow diagram of yet another embodiment of the converting step 451 according to the present invention. 
     FIG. 4E shows a more detailed flow diagram of still another embodiment of the converting step 451 according to the present invention. invention. 
     FIG. 5 shows some details of the data flow and functions provided by the software and hardware of test-control computer 300 as used to capture outputs to an LCD display screen from target microprocessor 120. 
     FIG. 6 is a key drawing showing the association of FIGS. 6A-6G. 
     FIG. 6A-6G show a schematic of the hardware implementation of one embodiment of preprocessing circuit (PPC) 210. 
     FIG. 7 shows details of one embodiment of a data structure used to hold a standard bit map usable to hold the results of the LCD capture and conversion process, according to the present invention. 
     FIG. 8 is a key drawing showing the association of FIGS. 8A-8M. 
     FIG. 8A-8M show a schematic of the hardware implementation of one embodiment of graphics capture circuit (GCC) 220. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which are shown, by way of illustration, specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. 
     In this specification, the term &#34;flat panel display&#34; is defined to include both liquid-crystal displays, as well as other flat-panel displays using other technologies, such as field-emissive devices (&#34;FED&#34;) as described on page 52 of the October 1995 issue of Windows Sources, in which each individual pixel may be driven by a time-varying sequence of signals in order to achieve more levels of optical intensity than might be possible were the pixel to be driven by the same signal level each time that pixel is driven. While embodiments of the present invention utilizing LCD display devices are described in detail, identical or similar embodiments tailored for other flat panel display technologies, wherein individual pixels are driven by a time-varying sequence of signals in order to achieve more levels of optical intensity, are specifically contemplated. 
     Conventional test systems may test a CRT output screen by connecting a probe to the signal input to a video-graphics adaptor (VGA) RAMDAC (Random Access Memory, Digital-to-Analog Converter), and from there drive a frame grabber circuit to capture each pixel (each pixel may be represented by an 8-bit data value, for example, which is synchronized with a RAMDAC clock signal) which is driven to a CRT display screen, and wherein each pixel of the CRT screen has a plurality of bits (all associated with that one pixel) simultaneously available for capture. Such CRT systems generally provide the same multi-bit value for a given pixel over time in order to provide a particular color and intensity for that pixel. Unlike those systems, LCD display systems such as device-under-test 100 of FIG. 1 drive individual pixels with different signals at various times in order that the modulation of the LCD pixels produces a perception of a particular color and/or a particular intensity at a particular pixel. Also unlike CRT systems in which the pixel clock generally runs continuously and in which the synchronization (sync) pulses are part of or synchronous with the pixel clock, the pixel clock for LCD systems often starts and stops at various points in the frame time period, and the sync pulses are independent of the pixel clock. 
     It is desirable to test such systems &#34;non-invasively,&#34; that is, without disturbing any electrical or programming function or timing of the system-under-test. Thus, stimulation and sensing of responses to the stimulation are externally applied to the system-under-test, and are designed to insignificantly disturb that system. 
     FIG. 1 shows an exemplary generalized test system 80, according to the present invention, for testing outputs to an LCD display screen from a computer. Device-under-test (DUT) 100 includes target microprocessor 120, memory 90, LCD display controller 93 and LCD display unit (or &#34;LCD display panel&#34;) 95. One embodiment of DUT 100 also includes keyboard interface 92, digital input/output (I/O) 122, and analog-to-digital convertor (ADC) 124. In one embodiment, device 100 could be any device controlled by an embedded microprocessor and having an LCD display screen, such as cardiac monitors, household appliances having &#34;smart&#34; controllers, and automobile engine controllers. In real operation (as opposed to in a test environment), target software 110 running on target microprocessor 120 executes instructions which control LCD drive signals through LCD display controller 93 (which in turn control LCD display device 95) in response to stimulus from, e.g., discrete input electrical signals through keyboard interface 92 or digital I/O 122 or from analog input electrical signals through ADC 124. In one embodiment, keyboard interface 92 comprises the cable between a keyboard for manual input and target microprocessor 120. In one embodiment, digital I/O 122 is an Intel 8255 Programmable Peripheral Interface (&#34;PPI&#34;) chip which is programmable by software instructions to output or input discrete signals on various of its pins. 
     The present invention couples to the sync, clock, data, power and ground signals of device 100, detects and separately captures the sync, clock, and data signals through opto-isolators. 
     In order to test device 100, in one embodiment, LCD drive probe 140 is attached to many or all of the pins of the cable or connector connecting LCD display controller 93 to LCD display device 95 (as a parallel load and/or driver to the normal connections for the data, address and/or control signals). In one embodiment, a cable provides a portion of the connection between LCD display controller 93 and LCD display device 95, and LCD drive probe 140 is physically and electrically inserted between one of the connector sockets and this cable. In such an embodiment, CPU digital probe 130 is not actually part of device 100, but is connected to it for testing purposes, as shown in FIG. 1. Opto-isolator coupler 190 provides a degree of electrical isolation and couples LCD drive probe 140 the rest of conversion circuit 200. 
     In one embodiment, conversion circuit 200 captures, organizes, and arranges up to eight (8) bits of image information per pixel. In one embodiment, this image information is stored into successive bytes of frame storage 240. Various manufacturers of the electronics for LCD display controller 93 organize and time the data which produces a particular color at a particular pixel differently. For instance, one manufacturer may place into the first byte of a frame data four pixels in the upper half of the frame and four pixels in the lower half of the frame in the following bit-significant order for a monochrome (&#34;mono&#34;) LCD display (where &#34;cartesian pairs&#34; indicate the location of a pixel on the display of LCD display unit 95, and wherein generally the upper-most left-most pixel location is (0,0), and X coordinates increase toward the right and Y coordinates increase towards the lower edge of the screen): 
     first byte: (0,243),(0,242),(0,241),(0,240),(0,3),(0,2),(0,1),(0,0), 
     second byte: (0,247),(0,246),(0,245),(0,244),(0,7),(0,6),(0,5),(0,4), 
     third byte: (0,251),(0,250),(0,249),(0,248),(0,11),(0,10),(0,9),(0,8), etc. 
     Such an arrangement of data within bytes is sometimes termed &#34;dual-scan&#34;. In addition, during successive frames (each frame comprising a set of pixel data including one value for each pixel of the display), different values may be sent on successive frames for each same pixel location, in order to modulate the intensity or color differently for each of the twenty-four example pixels controlled by these three bytes, and indeed for the entire screen. In this manner, various shades of grey are achieved by various modulation patterns or duty cycles. 
     For a color LCD display, each pixel can comprise blue, green, and red components, (the term &#34;pixlettes&#34; is defined to mean each of the plurality of individual portions which collectively comprise a pixel; in order to distinguish the term &#34;pixel&#34; which is the combination of the individual pixlettes). (For other display-controller/display combinations, various other color combinations may be used, depending on whether the display is reflective, absorbancy, or emissive.) The data values for the blue (B), green (G), and red (R) pixlettes are generally packed next to one another in a byte. In such a system having one data bit for each of the three pixlettes, there are three color bits packed into eight bits per byte and because data for the upper half of the screen is interspersed with data for the lower half of the screen, the pattern is more complex than for monochrome LCD displays, and the following order may be used: 
     byte 0: G(0,2),R(0,2),B(0,1),G(0,1),R(0,1),B(0,0),G(0,0),R(0,0), 
     byte 1: G(0,242),R(0,242),B(0,241),G(0,241),R(0,241),B(0,240),G(0,240),R(0,240), 
     byte 2: R(0,5),B(0,4),G(0,4),R(0,4),B(0,3),G(0,3),R(0,3),B(0,2), 
     byte 3: R(0,245),B(0,244),G(0,244),R(0,244),B(0,243),G(0,243),R(0,243),B(0,242), etc. 
     In this encoding system, each pixel has three color bits, one each for the red, green, and blue pixlettes, for a total of up to eight colors. The even-numbered bytes contain data for the upper-half screen, and the odd-numbered bytes contain data for the lower-half screen. The bits for successive pixels must be gathered from different bit positions with each successive byte until the patterns repeat. Various manufacturers place the color bits in various patterns, and use various modulation patterns to achieve perceptions of particular colors from the LCD displays. 
     For example, one manufacturer may send from the LCD display controller 93 to the LCD display unit 95 a repeating pattern of three frames, in which &#34;bright&#34; pixels are driven with the same three-bit pattern for all three frames, and &#34;normal&#34; pixels are driven with two frames having the desired three-bit pattern followed by a third frame having all bits &#34;off&#34;; thus there are said to be sixteen colors available: eight bright colors and eight normal colors. (This may result in only fifteen different &#34;colors&#34; since the bright pattern with all bits &#34;off&#34; and the normal pattern with all bits &#34;off&#34; each result in three frames each having all bits &#34;off&#34; for that pixel.) 
     The patterns sent by a particular manufacturer&#39;s LCD controller electronics must match the pattern recognized by the LCD display unit made by another (generally a different) manufacturer. The temporally modulated pattern of bits sent to a particular triplet of color pixels (for example the red, green, and blue pixels at display pixel coordinate (0,0)) must be combined and then converted into a value representing the color of that display pixel. In one embodiment, the pixel is represented by an eight-bit value representing the color and intensity (or hue and saturation) of that pixel. In another embodiment, the pixel is represented by a 24-bit value corresponding to eight bits each of red, green and blue intensity. 
     In addition, various manufacturers may place a particular number of non-displayed scan-line times in each frame, for example sending 482 scan lines wherein the first 480 are displayed in a 640-by-480 pixel display, and the last 2 are not, or, in a different design, sending 500 scan lines wherein the last 480 are displayed in a 640-by-480 pixel display and the first 20 are not. 
     Certain electronics for LCD display controller 93 may be adaptable to drive differently to each of a plurality of different LCD display devices 95. A particular LCD display device 95 may work optimally with one particular LCD drive controller, but may also function, albeit with different color or intensity results, with other LCD display controllers 93. The electronics for conversion circuit 200 or the software used to control the conversion process, or both, must therefore be set up to some extent uniquely for each particular LCD display controller 93 and/or LCD display device 95 combination. 
     In one embodiment, the signal converter 260, which includes conversion circuit 200 or the software used to control the conversion process, or both, includes a bit-masked change filter 248. One such embodiment is shown in FIG. 2A. 
     In one embodiment, the number of throw-away lines, depending on the panel used for LCD display device 95, is set into conversion circuit 200, in order to control how many scan lines are thrown away before the scan lines of interest are saved. In one such embodiment, the number of throw-away lines is a parameter which is loaded into conversion circuit 200 by test software 350, which controls the tests running in test-control computer 300. In another such embodiment, the logic in conversion circuit 200 is permanently programmed or configured to control the number of throw-away lines and other functions of conversion circuit 200. In one embodiment, the number of throw-away lines which should be discarded is determined empirically, by programming DUT 100 to display a blank screen (i.e., a first test pattern), observing the LCD signals with probe 140, then programming DUT 100 to display different data (i.e., a second test pattern) at specified pixels on the screen, and comparing where the resultant LCD signals change. In one embodiment, other characteristics of LCD display controller 93--LCD display unit 95 combinations are also derived empirically; software routine query conversion circuit 200 in order to obtain a value for the number of frames captured (i.e., the number of frames which must now be combined, a value for the horizontal resolution (i.e., the number of pixels per scan line), a value for the vertical resolution (i.e., the number of scan lines per frame), and a value for starting address of the first frame; in one such embodiment, frame storage 240 is searched for the first non-zero/non-pad character in order to determine the starting address of the first data in the first frame, which is sometimes useful in order to debug the software 350 and the hardware of GCC 220 and PPC 210. 
     FIG. 2 shows a block diagram of one embodiment of conversion circuit 200 including opto-isolator coupler 190, preprocessing circuit (PPC) 210 and graphics capture circuit (GCC) 220. In the embodiment shown in FIG. 2, LCD drive probe 140 is interposed (e.g., the cable from LCD display controller 93 plugs into LCD drive probe 140, which in turn plugs onto LCD display unit 95) into the signal path between LCD display controller 93 and LCD display unit 95; in another embodiment, as shown in FIG. 1, LCD drive probe 140 couples to the cable between LCD display controller 93 and LCD display unit 95. In one embodiment, test-control computer 300 comprises a high-performance IBM-compatible personal computer having an EISA (Extended Industry-Standard Architecture) bus to EISA interface circuit 250 of GCC 220 of conversion circuit 200. In one embodiment, test-control computer 300 also comprises a visual output display for displaying test results, magnetic storage devices for storing the test results, and runs a WINDOWS-brand software operating system, available from Microsoft Corporation. PPC 210 comprises opto-isolator coupler 190, mux/reorder (multiplexor/reorder) circuit 215, and buffer 225. In one embodiment, test-control computer 300 must identify the EISA (Extended Industry Standard Architecture) slot in which the GCC 220 resides, in order to be able to send and receive data and/or commands between test-control computer 300 and GCC 220. In one embodiment, test-control computer 300 is coupled to and control more than one GCC 220, each of which is coupled to an EISA bus (one embodiment uses a separate EISA address for each GCC 220 in order to distinguish data and commands for each respective GCC 220). The function of PPC 210 is to extract a data bit stream from the signals passing from LCD display controller 93 to LCD display unit 95, and to start to format the data from that data bit stream. In one embodiment, GCC 220 comprises genlock circuit 230, FIFO (first-in, first-out buffer) 235, frame storage 240 (sometimes called &#34;graphics-card memory&#34;), and EISA interface 250. In one embodiment, frame storage 240 comprises 4 megabytes of 32-bit wide storage for a set of frames, including a plurality of frames 241.1 through 241.N. In one embodiment, GCC 220 also places, into frame storage 240, data which is indicative of one or more of the following values: the total number of bytes captured, the horizontal resolution in pixels, the vertical resolution in pixels, and/or the address offset of the first non-pad character of frame data. 
     In operation, for one embodiment of the present invention, test-control computer 300 sends a command across the EISA bus to EISA interface 250 in order to command GCC 220 to capture (or &#34;grab&#34;) one frame 241.1, or alternatively one set of frames 241.1-241.N, of the signals creating the image on LCD display device 95. GCC 220 then sends a command to PPC 210 to grab one frame set (comprising one or more frames 241.1-241.N) of the image of LCD display device 95, wherein one frame set is defined as the combination of N frames 241.1-241.N, wherein each frame 241 comprises a set of frame pixel data, and wherein N depends on how many frames 241 form one cycle of a modulation sequence (which corresponds to the frame set) for the particular electronics used for LCD display controller 93. The data thus captured is raw or partially formatted data representative of the signals between LCD display controller 93 and LCD display unit 95. 
     For example, an LCD having a 2-level monochromatic (&#34;mono&#34;) grey scale might be fully represented by a frame set having a single frame (e.g., 241.1), and wherein a pixel being &#34;on&#34; represents a &#34;dark&#34; grey-level, and that pixel being &#34;off&#34; represents a &#34;white&#34; grey-level. Successive frames (i.e., frame data sent in successive time periods) to such an LCD would have identical data for any given pixel, which is thus constantly driven either &#34;on&#34; or &#34;off.&#34; For a different example, LCDs having a 16-level mono grey scale might utilize a time-multiplexed scheme wherein a single cycle of the modulation sequence (which corresponds to the frame set) comprises sixteen frames 241.1-241.N (where N is 16), and wherein a pixel being &#34;on&#34; for all sixteen frames represents a &#34;black&#34; or &#34;dark&#34; grey-level, and that pixel being &#34;off&#34; for all sixteen frames represents a &#34;white&#34; grey-level, and wherein a pixel being &#34;on&#34; for every other of the sixteen frames represents a &#34;50% dark&#34; grey-level, and wherein a pixel being &#34;on&#34; for every fourth of the sixteen frames represents a &#34;25% dark&#34; grey-level, and wherein a pixel being &#34;on&#34; for fifteen of the sixteen frames represents a &#34;94% dark&#34; grey-level, and so on. The raw or partially formatted data placed in frame storage 240 comprises a frame set which includes one or more frames. 
     GCC 220 synchronizes to the start of the frame set as indicated by PPC 210 which monitors signals from LCD display controller 93 to the LCD display unit 95. For a conventional CRT frame grabber, the synchronization is determined by reference off of the vertical sync (&#34;vsync&#34;) pulse, and the first scan line of pixel data is the scan line next-following the vsync pulse. In contrast, the start of an LCD frame is indicated by either a vsync pulse signal, the first scan line signal, or a first line mark signal, depending on the particular electronics used in LCD display controller 93. In addition, the first scan line of pixel data generally coincides with the vsync pulse. 
     In one embodiment, GCC 220 for a particular combination (of LCD display device 95 and LCD display controller 93) is customized in order to capture the proper number of frames (to determine temporal modulation), and is based on the size of each frame (i.e., the horizontal and vertical resolution, and number of bits per pixel), the bit and byte order reorganization required (e.g., big-endian versus little-endian), the number of lines, if any, to be thrown away and whether these are at the start or end of the frame. Manufacturer data sheets for a combination of LCD display unit 95 and LCD display controller 93 provide some of the parameters needed. Since some manufacturers may not publish each of the parameters for their particular combination of LCD display device 95 and LCD display controller 93, these parameters are determined empirically by observing the signals between LCD display controller 93 and LCD display device 95. 
     
                       TABLE 1______________________________________Com-                          Bits/bination  Type    Scale  Resolution                         Pixel Scan Mode______________________________________1 X2   Color   16     640x480 3     Single2 X5   Mono    16     640x480 1     Dual (Post offset)3 X4   Mono    16     640x480 4     Single4 X6   Mono    16     640x480 1     Dual (Pre offset)5 X7   Mono     2     640x480 1     Single6 X8   Color   256    640x480 16    Single______________________________________ 
    
     One embodiment of Combination 1 uses a program code version denominated CARDX2 and shown in Appendix C, and is designed to analyze signals from an LCD display controller 93 which comprises a custom logic design of TOA Corporation, coupled to an LCD display unit 95 comprising a custom-designed panel. &#34;Appendix B, GCC-8U11.pds for CARDX2&#34; shows the PALASM (Programmable Array Logic Assembler language) programming for PLD 8U11 of an exemplary LCD genlock circuit 230 as shown in Combination 1 of Table 1. 
     One embodiment of Combination 2 uses a program code version denominated CARDX5 and shown in Appendix C, and is designed to analyze signals from an LCD display controller 93 which comprises a Cirrus Logic CL-GD6440 type chip, coupled to an LCD display unit 95 comprising a WACOM PL-100V type panel. This combination is a dual-scan display having a post-offset (i.e., blank scan lines are sent after the end of each frame, and are discarded or ignored by test-control computer 300 and/or conversion circuit 200). &#34;Appendix B, GCC-8U11.pds for CARDX5&#34; shows the PALASM programming for PLD 8U11 of an exemplary LCD genlock circuit 230 as shown in Combination 2 of Table 1. 
     One embodiment of Combination 4 uses a program code version denominated CARDX4 and shown in Appendix C, and is designed to analyze signals from an LCD display controller 93 which comprises a Cirrus Logic CL-GD6410 type chip, coupled to an LCD display unit 95 comprising a PLANAR EL640.480-A type panel. &#34;Appendix B, GCC-8U11.pds for CARDX4&#34; shows the PALASM programming for PLD 8U11 of an exemplary LCD genlock circuit 230 as shown in Combination 4 of Table 1. 
     One embodiment of Combination 5 uses a program code version denominated CARDX6 and shown in Appendix C, and is designed to analyze signals from an LCD display controller 93 which comprises a Cirrus Logic CL-GD6410 type chip, coupled to an LCD display unit 95 comprising a custom-designed panel. This combination is a dual-scan display having a pre-offset (i.e., blank scan lines are sent before the start of each frame, and are discarded or ignored by test-control computer 300 and/or conversion circuit 200). &#34;Appendix B, GCC-8U11.pds for CARDX6&#34; shows the PALASM programming for PLD 8U11 of an exemplary LCD genlock circuit 230 as shown in Combination 5 of Table 1. 
     One embodiment of Combination 6 uses a program code version denominated CARDX7, and is designed to analyze signals from an LCD display controller 93 which comprises a custom logic design of Intermedics Corp., coupled to an LCD display unit 95 comprising a FINLUX MD640.480 type panel. &#34;Appendix B, GCC-8U11.pds for CARDX7&#34; shows the PALASM programming for PLD 8U11 of an exemplary LCD genlock circuit 230 as shown in Combination 6 of Table 1. 
     One embodiment of Combination 7 uses a program code version denominated CARDX8, and is designed to analyze signals from an LCD display controller 93 which comprises a Chips &amp; Technologies OC65540/545 type chip coupled to an LCD display unit 95 comprising a HOSIDEN HLD1026-011000 SE type panel. &#34;Appendix B, GCC-8U11.pds for CARDX8&#34; shows the PALASM programming for PLD 8U11 of an exemplary LCD genlock circuit 230 as shown in Combination 7 of Table 1. 
     In some embodiments of device under test 100, certain keyboard stimuli from keyboard interface 92 cause a specified output to LCD display device 95 in response. For instance, one keystroke (i.e., the activation of a certain key by, e.g., a user manually depressing the key) might cause a pop-up window of a specified color and size to appear at a specified location on LCD display device 95. To test whether this function worked correctly, the test-control software 350 would cause a simulated keystroke at keyboard interface 92, then detect changes in the signals to LCD display, and compare those changes to a set of expected changes. This test is greatly facilitated by operation of the present invention which converts all display data signals, regardless of the type of display-under-test 100, into a standard format comprising an array of values representing the display image, wherein each element of the array includes a plurality of bits representing the color, intensity, or both, for one pixel of the display. This standard format allows verification of a variety of different displays, including LCD displays, made by different manufacturers which implement different techniques of modulation to generate a particular perceived color. 
     FIG. 3 shows an overview of the functions provided, in one embodiment, by software 350 running a test in test-control computer 300. In one embodiment, software 350 is implemented in the C-language, and uses a PASCAL calling protocol for certain variables. After software 350 is entered, control passes to block 321. The program code of block 321 triggers a stimulus signal 322 to stimulus processor 130, which in turn cause a stimulus (for example, one or more of the following: an analog signal from DAC (digital-to-analog converter) 133 to ADC (analog-to-digital converter) 124, a digital signal to digital I/O 122, and/or a digital signal to keyboard interface 92) to device-under-test 100. In one embodiment, a completion signal 323 indicates to the software in block 321 when the stimulus has been completed. In another embodiment, a timer is used instead to indicate when the stimulus should have completed in order that block 321 can be exited. Control then passes to the make-bit-map software of block 351. The program code of block 351 (shown in more detail in FIG. 4) causes a capture of the frame set of the LCD screen and makes a bit map, storing the results into a standard-bit-map structure. Control then passes to block 381. The program code of block 381 analyzes the bit map results, and in one embodiment compares the results to a predetermined set of expected results. Control then passes to block 411. The program code of block 411 generates a report of test results which indicates to a user whether or not the test passed. 
     FIG. 4A shows a more detailed flow diagram of one embodiment of the make-bit-map software routine 351 according to the present invention. In this embodiment, block 450 shows the step of Generating digital drive data representative of an electronic signal which drives the display screen, block 451 shows the step of Converting the digital drive data into pixel data, wherein each of the pixel data comprise a value representing an attribute for at least one pixel of the display, and block 452 shows the step of storing the pixel data. 
     FIG. 4B shows a more detailed flow diagram of one embodiment of the converting step 451 according to the present invention. In this embodiment, block 460 shows the step of Retrieving a plurality of pixel values within each of a plurality of frames of the digital drive data, block 461 shows the step of Combining at least one of the plurality of pixel values sampled from a first one of the plurality of frames with a corresponding one of the plurality of pixel values sampled from a second one of the plurality of frames in order to generate a combined pixel value, and block 462 shows the step of Saving the combined pixel value. 
     FIG. 4C shows a more detailed flow diagram of another embodiment of the converting step 451 according to the present invention. In this embodiment, block 463 shows the step of Sampling the digital drive data at a plurality of points in time in order to derive the pixel data for one combined pixel value. 
     FIG. 4D shows a more detailed flow diagram of yet another embodiment of the converting step 451 according to the present invention. In this embodiment, block 464 shows the step of Converting includes using a bit-masked change filter 
     FIG. 4E shows a more detailed flow diagram of still another embodiment of the converting step 451 according to the present invention. In this embodiment, block 465 shows the step of Sampling a plurality of scan lines within a frame of the digital drive data, wherein at least one of the plurality of scan lines sampled is discarded and at least one other of the plurality of scan lines sampled is saved. 
     FIG. 4 shows a more detailed flow diagram of one embodiment of the make-bit-map software routine 351 according to the present invention. After software 351 is entered, control passes to block 354. In one embodiment, the program code of block 354 zeros all portions of frame storage 240 which are to be filled with the raw data from the LCD data capture. The program code of block 354 also triggers a signal 352 which, in one embodiment, is coupled as a capture command on the EISA bus to EISA interface 250 of conversion circuit 200. In one embodiment, the capture command causes genlock circuit 230 to generate a lock at the beginning of a frame (e.g., at the start of the next whole frame detected), which results in a specified number of frames being stored in frame storage 240. (In one embodiment, an empirically-derived number of frames is determined, and the programmable logic of GCC 220 is permanently configured to store that predetermined number of flames whenever it is triggered.) In one embodiment, conversion circuit 200 generates a signal 353 which is coupled as an interrupt to the software of block 354 after a specified amount of frame data has been captured (in one embodiment, after a complete frame set has been captured and stored). In another embodiment, a timer is used to alert the software of block 354 when a sufficient amount of time has passed to capture the desired data. In one embodiment, up to five retries of the frame-set capture are performed, and if all five retries fail, an error message is displayed. Control then passes to block 356. The program code of block 356 calculates the address in frame storage 240 of a particular pixel, retrieves the data for that pixel. Control then passes to block 358. The program code of block 358 processes the pixel data (in one embodiment, an SBM (standard bit map) structure 420 is initially setup with zeros for every pixel in the bit map, every pixel value from the first frame is added to the corresponding pixel (initially zero) in the bit map by passing through blocks 356, 358, 360, and 362 for every pixel of the first frame, then the second through Nth frames are similarly added, so that N corresponding pixel values from N frames are added to calculate the corresponding pixel value in the bit map). Control then passes to block 360. The program code of block 360 stores the processed data into SBM structure 420, and block 362 determines whether all pixels of all frames have been processed, and if not, loops back to block 356. In one embodiment, the &#34;top&#34; scan line data is captured last (or, equivalently (since each scan line is added to the corresponding scan line from every other frame captured), the top scan line from every frame is stored as the last scan line of the previous frame), so blocks 356-362 move this &#34;top&#34; line from last position in each frame in frame storage 240 to first position in SBM structure 420, moving every other scan line down one position; since the corresponding scan lines are combined by block 358 by addition of the corresponding scan lines of every frame, it doesn&#39;t matter what order the addition is performed, the resultant value will be correct. In some embodiments, some or all of blocks 356-362 are coded in assembly code to achieve better performance. In one embodiment, the resultant pixel data array 429 comprises a one-byte pixel color value for every pixel of a 640-by-480 pixel display. Control then passes to block 366. The program code of block 366--block 372 are used in one embodiment to map values the processed SBM structure data resulting from the processing of blocks 356-362 into more-convenient or useful values. For example, in one embodiment, it is desired to have similar tests performed on both of two different LCD display controller 93--LCD display unit 95 combinations, each of which generate different numerical pixel values for the same colors, or to have similar tests used to test and compare an LCD-display implementation of DUT 100 with a CRT-display implementation of DUT 100. In one embodiment, block 366 calculates the address of the first (or next) pixel, and retrieves a one-byte pixel value from that address in the array in SBM structure 420, block 368 maps that value into a &#34;standard&#34; color value using a 256-entry table lookup, block 370 stores the resultant mapped byte value back into the SBM structure, and block 372 determines whether all pixels have been processed, and loops back to block 366 if not. The program code of block 374 is used in one embodiment to perform a run-length compression of the processed array of SBM structure 420 in order to save storage in test-control computer 300. Control then passes to the exit of make-bit-map software 351. 
     In one embodiment as shown in FIG. 7, the standard bit map (SBM) structure 420 includes the name of the structure (sBitMap) and its type (structure) 421, a pointer 422 that points to the pixel data array 429, and the pixel data array 429. Also included are parameters which characterize the data in the array, including scan-line width 423 (i.e., the x-dimension of the array), the number of scan lines 424 (i.e., the y-dimension of the array), the bit-map type 425, a compressed indicator 426 that shows whether the array data is compressed, a color/mono indicator 427, a color map pointer 428 that points to a color map 410, and a clip area indicator 430, that in one embodiment indicates X-MIN, X-MAX, Y-MIN, and Y-MAX of the clip area. 
     FIG. 5 shows some details of the data flow and functions provided by the software and hardware of test-control computer 300 as used to capture outputs to an LCD display screen from target microprocessor 120. 
     FIGS. 6A-6G show a schematic of the hardware implementation of one exemplary embodiment of preprocessing circuit (PPC) 210. FIGS. 6A-6F can be placed next to one another to form a single large schematic, with points &#34;A&#34; connected to one another. FIG. 6G shows pin connections for LCD probe 140. On FIG. 6A, input signals PI-1 through P1-26 are coupled to LCD drive probe 140 through an AMP brand type 499786-6 connector to capture up to as many signals as: an upper data byte, a lower data byte (since some color LCD controller chips 93 send 16 data bits per clock), and three clock/control signals. In one embodiment, low-pass filters, comprising resistor-capacitor pairs R1-C1 through R19-C19 are used to condition the input signals to reduce ringing and produce conditioned test signals TUD0 through TUD7, TLD0 through TLD7, TPCLK, TLCLK, and TFLM. In another embodiment, RC pairs R1-C1 through R19-C19 are omitted, replacing the resistors with zero-ohm conductors. 
     Referring to FIG. 6B, the sixteen data signals and three clock/control signals are optically isolated and coupled by opto-isolator circuits 6U1 through 6U19 (opto-isolator circuits 6U23 of FIG. 6F is used in one embodiment, to provide a reference ground signal), each of which, in one embodiment, are HP HCPL-7101 type parts available from Hewlett-Packard Corp, and which collectively form opto-isolator coupler 190. Separate voltage supplies T5V and D5V, and separate grounds T and D, are used for the two sides of the isolators. 
     Referring to FIG. 6C, the isolated sixteen data signals, UD0 through UD7 and LD0 through LD7, and three clock/control signals, PCLK (pixel clock), LCLK (line clock, or horizontal sync) and FLM (first line marker, or vertical sync), are coupled to programmable logic device 6U20, which in one embodiment is a MACH210-12JC programmable logic device available from AMD Corp, and which forms mux/reorder circuit 215. The upper and lower bytes of data, 6UD0 through UD7 and LD0 through LD7 respectively, are multiplexed onto signals P0 through P7 by programmable logic device 6U20. Clock signal PCLK is also coupled through delay line 6U21, which is as DS10005-050 type part available from Dallas Semiconductors Inc., 4401 South Builtwood Parkway, Dallas, Tex. 75244, and then coupled to programmable logic device 6U20. Programmable logic device 6U20 also conditions PCLK, the delayed PCLK, LCLK, and FLM, and produces PCLK1 (pixel clock for the first demultiplexed byte), PCLK2 (pixel clock for the second demultiplexed byte), LCLK1 and FLM1, respectively, therefrom, to be used as pixel clocks, vertical sync, and horizontal sync by GCC 220. Buffer 6U22, which in one embodiment is a 74AC16543DL056 type device available from Texas Instruments (TI) Corp, is used to buffer signals P0 through P7, PCLK1, PCLK2, LCLK1 and FLM1 to drive the signals through resistors R20 through R31 to GCC 220. FIGS. 6D and 6E show decoupling capacitors used on the T5V and D5V voltage supply connections to the various parts of preprocessing circuit (PPC) 210. 
     FIGS. 8A-8M show a schematic of the hardware implementation of one embodiment of graphics capture circuit (GCC) 220. FIGS. 8A-8M can be placed next to one another to form a single large schematic for the following discussion. 
     Programmable logic device 8U1 shown in FIG. 8B, which in one embodiment is a MACH230-12JC type programmable logic device available from AMD Corp, forms an address multiplexor for the address to frame storage 240, and drives this address from either the EISA interface 250 or the counter of the frame capture function. Appendix D shows the PALASM programming for an exemplary PLD 8U1, which is labeled GCC-8U1.pds. 
     Buffers 8U2 and 8U3 shown in FIG. 8A, each of which in one embodiment is a 74BCT2424AFN type part, available from Texas Instruments (TI) Corp, form a driver for the data paths between frame storage 240 and the input/output (I/O), i.e., frame capture from FIFO 235, and reads/writes from EISA interface 250. 
     Programmable logic device 8U4 shown in FIG. 8C, which in one embodiment is a MACH210-12JC type programmable logic device available from AMD Corp, forms a DRAM controller for controlling the memory cycles of frame storage 240, and thus controls refresh, frame capture from FIFO 235, and reads/writes from EISA interface 250. Appendix D shows the PALASM programming for an exemplary PLD 8U4, which is labeled GCC-8U4.pds. 
     Programmable logic device 8U5 shown in FIG. 8C, which in one embodiment is a MACH210-12JC type programmable logic device available from AMD Corp, forms the data path control and the status decode for FIFO 235. Appendix D shows the PALASM programming for an exemplary PLD 8U5, which is labeled GCC-8U5.pds. 
     Programmable logic device 8Y1 shown in FIG. 8C, which in one embodiment is a CTS MX045 clock oscillator type device by CTS, available from Digikey, 701 Brooks Av. S., Thief River Falls 56701, forms a timing clock signal for the DRAM controller of device 8U4 and the frame address counter of device 8U8. 
     NAND (not-AND logic) gates 8U6 shown in FIG. 8C, which in one embodiment is a 74AC00 type device available from TI Corp, generates a data-ready signal EXRDY for EISA interface 250, and generates a 32-bit access signal EX32#. 
     Programmable logic device 8U7 shown in FIG. 8D, which in one embodiment is a MACH230-12JC type programmable logic device available from AMD Corp, forms part of EISA interface 250 as an EISA decoder, providing chip selects, an EISA identifier, memory mapping, and a frame capture trigger signal which is sent from EISA interface 250 to genlock circuit 230. Appendix D shows the PALASM programming for an exemplary PLD 8U7, which is labeled GCC-8U7.pds. 
     Programmable logic device 8U8 shown in FIG. 8D, which in one embodiment is a MACH210-12JC type programmable logic device available from AMD Corp, forms a frame address counter, which specifies the location in frame storage 240 into which the next data from a frame capture is to be stored. Appendix D shows the PALASM programming for an exemplary PLD 8U8, which is labeled GCC-8U8.pds. 
     Programmable logic device 8U9 shown in FIG. 8E, which in one embodiment is a MACH210-12JC type programmable logic device available from AMD Corp, forms a horizontal resolution counter, which counts the number of pixels between horizontal sync signals, thus making available to software 350 the number of pixels per horizontal scan line. Appendix D shows the PALASM programming for an exemplary PLD 8U9, which is labeled GCC-8U9.pds. 
     Programmable logic device 8U10 shown in FIG. 8E, which in one embodiment is a MACH210-12JC type programmable logic device available from AMD Corp, forms a vertical resolution counter, which counts the number of scan lines between vertical sync signals, thus making available to software 350 the number of horizontal scan lines per frame. Appendix D shows the PALASM programming for an exemplary PLD 8U10, which is labeled GCC-8U10.pds. 
     Memory chips 8U16-8U23 shown in FIGS. 8F and 8G, each of which in one embodiment is a MT4C4001Z-70 type 1M-by 4-bit DRAM memory chip device available from Micron Technology Corp, together form a four-megabyte memory used for frame storage 240. 
     FIG. 8H shows pull-up resistors and decoupling capacitors for the indicated signals. 
     FIG. 8I shows termination resistors for the indicated signals. 
     FIG. 8J shows Programmable logic device (&#34;PLD&#34;) 8U11, which forms genlock circuit 230, and buffers 8U12-8U15. 
     Programmable logic device (&#34;PLD&#34;) 8U11, which in one embodiment is a MACH210-12JC type programmable logic device available from AMD Corp, forms genlock circuit 230. The genlock circuit 230 is generally customized for each combination of LCD display device 95 and LCD display controller 93 in order to properly couple the clock signals to the vertical sync, horizontal sync, pixel clock, and blanking functions of GCC 220. Appendix A shows the PALASM programming for PLD 8U11 of an exemplary prior-art genlock circuit 230 used to capture CRT frame data from the data signals driving a RAMDAC. Appendix D shows the PALASM programming for PLD 8U11 of several exemplary LCD genlock circuits 230, according to the present invention, explained further at TABLE 1, these are as follows: 
     1. &#34;Appendix D, GCC-8U11.pds for CARDX2&#34; shows the PALASM programming for PLD 8U11 of an exemplary LCD genlock circuits 230 as shown in Combination 1 of Table 1. 
     2. &#34;Appendix D, GCC-8U11.pds for CARDX5&#34; shows the PALASM programming for PLD 8U11 of an exemplary LCD genlock circuits 230 as shown in Combination 2 of Table 1. 
     3. &#34;Appendix D, GCC-8U11.pds for CARDX4&#34; shows the PALASM programming for PLD 8U11 of an exemplary LCD genlock circuits 230 as shown in Combination 3 of Table 1. 
     4. &#34;Appendix D, GCC-8U11 .pds for CARDX6&#34; shows the PALASM programming for PLD 8U11 of an exemplary LCD genlock circuits 230 as shown in Combination 4 of Table 1. 
     5. &#34;Appendix D, GCC-8U11.pds for CARDX7&#34; shows the PALASM programming for PLD 8U11 of an exemplary LCD genlock circuits 230 as shown in Combination 5 of Table 1. 
     6. &#34;Appendix D, GCC-8U11.pds for CARDX8&#34; shows the PALASM programming for PLD 8U11 of an exemplary LCD genlock circuits 230 as shown in Combination 6 of Table 1. 
     Buffers 8U12, 8U13, 8U14, and 8U15, each of which in one embodiment is a IDT7203j-15 type 2 k-by-9, 15 nanosecond (ns) asynchronous buffer, available from Integrated Device Technologies Inc. of 9275 Stender Way, Santa Clara, Calif. 95054, form the memory for FIFO 235. 
     FIGS. 8K, 8L, and 8M show external connector coupling for GCC 220 for the indicated signals. 
     Appendix C shows C-language coding for make-bit-map software 351 for various embodiments of the present invention corresponding to the combinations shown in TABLE 1. Appendix C also includes routines used by software 350 to manipulate the standard-bit-map structure 420, as well as a structure definition called BIT --  MAP in the header GRPHDLL.H (see in the middle of page 4 in &#34;Appendix C: GRPHDLL.C, GRPHDLL.H&#34;), of one embodiment of the standard-bit-map structure 420. 
     In one embodiment, test-control software 350 is driven by table 410 (shown in FIG. 7), in which are provided values for the table-lookup transformation of captured pixel data for a single combination of LCD display device 95 and LCD display controller 93. In another embodiment, table 410 comprises data for a plurality of combinations of LCD display devices 95 and LCD display controllers 93. 
     In one embodiment, the make-bit-map software 351 causes a trigger signal to initiate an LCD graphics capture which places one or more frames of LCD data into the frame storage 240 of GCC 220. Make-bit-map software 351 then retrieves data from the frame storage 240. In one embodiment a transformation (e.g., a table-lookup replacement of pixel values) is performed on the data. In another embodiment a summation on the data of one frame with data of the corresponding pixel of other frames is performed, and the result stored into standard-bit-map structure 420. In one embodiment, a second transformation (e.g., a table-lookup replacement of pixel values) is performed on the data to convert the summed pixel values into pixel standard color and/or intensity values. 
     In one embodiment used for Combination 7 of TABLE 1, it is desired to compute the address in frame storage 240 that the bit sequence starts in, as well as the bit position in the byte at that address, that the sequence starts in. In general, a number which is the smallest number which is evenly divisible by the both the number of bits per memory request (generally one byte, i.e., eight bits) and the number of bits per pixel (generally one, three, or five bits). Twenty-four (24) bits is the smallest value factorable by both 8 and 3, so the bit position re-synchronizes to bit position 0 of a byte every 3 bytes. Therefore, address of the three-byte sequence is found, and positions are then computed based from there. Since this particular algorithm (corresponding to a particular LCD display controller 93--LCD display unit 95 combination) is only interested in 3 consecutive bits, the 3-bit sequence will be either within a single byte, or will span one byte boundary, but will never span more than one byte boundary which implies that an integer pointer can be used. In one such embodiment, a switch statement is used, and an individual computation is performed for each possible pixel location in the 3-byte sequence since there are only eight possible pixel values (i.e., pixel values can assume values in the range of 000 to 111 binary). It is believed this should be the fastest way, since no more than the minimum amount appropriate for each location need be shifted. In order to handle 16-bit data, one embodiment of GCC 220 has been designed so odd bytes (i.e., bytes located at odd-numbered addresses) contain upper-half-screen data and even bytes (i.e., bytes located at even-numbered addresses)contain lower-half-screen data. As long as scan lines do not have odd lengths (i.e., an odd length is where the pixels for a scan line do not start and/or end on byte boundaries), this will hold true for the iX value passed as well. The start of a 3-byte sequence is obtained, and the pixel data is extracted from the byte stream, taking into account that upper-screen and lower-screen data resides in odd and even bytes, respectively. 
     In one embodiment, a clipping function is provided in order to isolate and analyze a portion of the LCD screen while ignoring the remainder of the screen. In one such embodiment, a rectangle subset of a 640-by-480 pixel screen as defined by an X-MIN, an X-MAX, a Y-MIN, and a Y-MAX value (each of which is specified in the SBM structure 420 in clip area field 430) is clipped and saved, while data from the remainder of the screen is ignored for certain operations. In one such embodiment, values of (0,0,0,0) in clip field 430 specifies to the searching code to use or search the entire bit map. The clipping function is useful when a specified stimulus is supposed to modify a specified section of the screen, but whether or not other areas of the screen change or do not change is a &#34;don&#39;t care&#34; condition, or when a search for specific text or graphics objects is to be concentrated in one area of the screen to save time. 
     In one embodiment, log routine 314 and snap routine 316 (see FIG. 5) associate header text with a set of filtered data. This header text includes information identifying the test procedure used to acquire the data, and parameters which are useful in analyzing the data, and/or repeating the test. Compare statements 318 provide the specifications and/or parameters for the compares to be performed in the collection and testing of the test data. In one embodiment, these compare statements 318 include: (a) the parameters which are loaded into conversion circuit 200 in order to program it to collect the data of interest, either before or as the testing is performed, or (b) programs or control parameters for testing the filtered signal data stored in log files 324 and snap files 326, or (c) both (a) and (b). Stimulus statements 320 provide the specifications and/or parameters for the stimuli to be provided in order to drive signals which enable controlled testing of device 100, thus stimulating device 100 in a controlled and timed manner to enable the collection and testing of the test data. In one embodiment, program code of block 321 triggers a stimulus signal 322 to stimulus processor 130 by calling a specified subroutine in stimulus statements 320. By correlating the stimulus provided and the response detected, the test system can provide comprehensive and repeatable tests. 
     It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. 
     Appendix A Listing: PALASM programming for PLD 8U11 of an exemplary prior-art genlock circuit 230 used to capture CRT frame data from the data signals driving a RAMDAC, 3 Pages. 
     Appendix B Listing: programming for programmable logic devices: 
     Appendix B, GCC-8U11.pds for CARDX2, 3 Pages, for PLD 8U11. 
     Appendix B, PPC-6U20.pds for CARDX2, 2 Pages, for PLD 6U20. 
     Appendix B, GCC-8U11.pds for CARDX4, 3 Pages, for PLD 8U11. 
     Appendix B, PPC-6U20.pds for CARDX4, 2 Pages, for PLD 6U20. 
     Appendix B, GCC-8U11.pds for CARDX5, 4 Pages, for PLD 8U11. 
     Appendix B, PPC-6U20.pds for CARDX5, 2 Pages, for PLD 6U20. 
     Appendix B, GCC-8U11.pds for CARDX6, 4 Pages, for PLD 8U11. 
     Appendix B, PPC-6U20.pds for CARDX6, 2 Pages, for PLD 6U20. 
     Appendix B, GCC-8U11.pds for CARDX7, 2 Pages, for PLD 8U11. 
     Appendix B, PPC-6U20.pds for CARDX7, 2 Pages, for PLD 6U20. 
     Appendix B, GCC-8U11.pds for CARDX8, 3 Pages, for PLD 8U11. 
     Appendix B, PPC-6U20.pds for CARDX8, 2 Pages, for PLD 6U20. 
     Appendix C Listing: C-code routines 
     Appendix C: CARDINTF.C 9 Pages, subroutines to interface to conversion circuit 200. 
     Appendix C: CARDX2.C 19 Pages, subroutines to capture a frame set and make a standard bit map structure 420 for the CARDX2 Combination 1 of TABLE 1. 
     Appendix C: CARDX4.C 11 Pages, subroutines to capture a frame set and make a standard bit map structure 420 for the CARDX4 Combination 2 of TABLE 1. 
     Appendix C: CARDX5.C 19 Pages, subroutines to capture a frame set and make a standard bit map structure 420 for the CARDX5 Combination 3 of TABLE 1. 
     Appendix C: CARDX6.C 19 Pages, subroutines to capture a frame set and make a standard bit map structure 420 for the CARDX6 Combination 4 of TABLE 1. 
     Appendix C: CARDX7.C 12 Pages, subroutines to capture a frame set and make a standard bit map structure 420 for the CARDX7 Combination 5 of TABLE 1. 
     Appendix C: CARDX8.C 25 Pages, subroutines to capture a frame set and make a standard bit map structure 420 for the CARDX8 Combination 6 of TABLE 1. 
     Appendix C: GRBITMAP.C, GRBITMAP.H 80 Pages, subroutines to handle and manipulate SBM structure 420. 
     Appendix C: EISA.C, EISA.H 14 Pages, subroutines to control and manipulate EISA interface 420 from software. 
     Appendix C: DPMI.C, DPMI.H 13 Pages, subroutines to allocate memory and selectors in order to access GCC 220. 
     Appendix C: GRPHDLL.C, GRPHDLL.H 12 Pages, a general entry point which &#34;registers&#34; with the Windows operating system so that the functions in this DLL are available to other functions within any software running under the Windows operating system within test-control computer 300. 
     Appendix D Listing: programming for programmable logic devices: 
     Appendix D, GCC-8U1.pds, 3 Pages, programming for PLD 8U1 
     Appendix D, GCC-8U4.pds, 4 Pages, programming for PLD 8U4. 
     Appendix D, GCC-8U5.pds, 2 Pages, programming for PLD 8U5. 
     Appendix D, GCC-8U7.pds, 5 Pages, programming for PLD 8U7. 
     Appendix D, GCC-8U8.pds, 3 Pages, programming for PLD 8U8. 
     Appendix D, GCC-8U9.pds, 3 Pages, programming for PLD 8U9. 
     Appendix D, GCC-8U10.pds, 3 Pages, programming for PLD 8U10. ##SPC1##