Abstract:
The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. The present invention does not require formation of a silicon interposer, therefore the overall cost of the final product is much reduced.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to semiconductor packages and a method of fabricating the same, and, more particularly, to a semiconductor package having wafer level circuits and a method of fabricating the same. 
         [0003]    2. Description of the Prior Art 
         [0004]    As the technology for developing electronic products is steadily growing, electronic products have now moved to multi-functionality and high functionality. The semiconductor packaging technology has been widely used nowadays to chip scale package (CSP), Direct Chip Attached (DCA), Multi Chip Module (MCM), and 3D-IC stacking technology. 
         [0005]      FIG. 1  is a schematic cross-sectional view of a conventional semiconductor package, wherein a through silicon interposer (TSI)  10  is formed between a substrate  18  and a semiconductor chip  11 . The TSI  10  has through-silicon vias (TSV)  100  and a redistribution layer (RDL)  15  formed on the through-silicon vias (TSV)  100 , allowing the redistribution layer  15  through each of the plurality of conductive elements  17  to be electrically connected with solder pads  180  on the substrate  18 . The spacing distance between any two of the solder pads  180  is greater than that of the conductive elements  17 . The conductive elements  17  are covered by an adhesive material, and the electrode pads  110  of the semiconductor chip  11  are electrically connected to the through-silicon via (TSV)  100  through a plurality of solder bumps  19 . An adhesive material is then applied to cover the solder bumps  19 . 
         [0006]    If the semiconductor chip  11  is directly attached to the substrate  18 , since the heat expansion coefficient difference between the smaller semiconductor chip and the larger circuit substrate is rather large, it is difficult to establish a good bonding between the solder bumps  19  on the periphery of the chip  11  and the corresponding solder pads  180 , causing the solder bumps  19  to be easily detached from the substrate  18 . In addition, due to problems associated with thermal stress and warpage as a result of mismatch of heat expansion coefficient between semiconductor chip and substrate, the reliability between the semiconductor chip and the substrate is decreased causing frequent failures in reliability test. 
         [0007]    Accordingly, by providing he interposer  10  made of silicon fabricating process of the semiconductor substrate, since the material thereof is similar to the semiconductor chip  11 , the conventional problems can be solved. 
         [0008]    The only concern in the foregoing fabricating method of the semiconductor package  1  is the fabrication cost of the through-silicon via (TSV)  100  in the silicon interposer  10 , which includes forming the via and the metal underfill process. The total cost of the through-silicon via (TSV)  100  is 40-50% of the total cost in the fabricating process. Hence, it is difficult to reduce the overall cost. 
         [0009]    Moreover, the technical difficulty in fabricating the silicon interposer  10  is high. Hence, under the same fabricating cost, the yield of the semiconductor package  1  is relatively low. 
         [0010]    Therefore, there is an urgent need in solving the foregoing problems. 
       SUMMARY OF THE INVENTION 
       [0011]    In light of the foregoing drawbacks of the prior art, the present invention proposes a semiconductor package, comprising: a semiconductor element having opposing active and non-active surfaces; a dielectric layer formed on the active surface of the semi element; and a circuit layer formed on the dielectric layer and electrically connected to the semiconductor element. 
         [0012]    In an embodiment, the semiconductor element further comprises side surfaces abutting the active surface and the non-active surface. The dielectric layer covers a periphery of the side surfaces of the semiconductor element. The dielectric layer is made of a non-organic material or an organic material. The dielectric layer comprises a supporting part surrounding the dielectric layer. 
         [0013]    In an embodiment, the semiconductor package further comprises an etch-stop layer such as silicon nitride and an opening to expose the semiconductor element, covered by the a dielectric material made of a non-organic material or an organic material, allowing the etch-stop layer to be formed between the active surface of the semiconductor element and the dielectric layer. The dielectric material further comprises a supporting part. 
         [0014]    In an embodiment, the supporting part is a silicon-containing frame, and the thickness of the semiconductor element can be greater than or not greater than the height of the supporting part. 
         [0015]    The present invention further proposes a method of fabricating a semiconductor package, comprising: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces; forming a dielectric layer on the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. 
         [0016]    In an embodiment, the carrier is a silicon-containing board. In an embodiment, the carrier has a plurality grooves, a singulation process is performed after the first portion of the carrier below the groove is removed, and the supporting part is also removed during the singulation. 
         [0017]    In an embodiment, the semiconductor element protrudes or does not protrude from the groove. 
         [0018]    In an embodiment, through the non-active surface, the semiconductor element is assembled in the groove via a bonding layer. The bonding layer is between 5 to 25 μm in thickness, and is removed when the first portion of the carrier below the groove. 
         [0019]    In an embodiment, the groove is filled with a dielectric layer. The semiconductor element further comprises side surfaces abutting the active surface and the non-active surface. The dielectric layer covers the periphery of the side surfaces of the semiconductor element and is made of a non-organic or an organic material. 
         [0020]    In an embodiment, the method further comprises forming an etch-stop layer on the active surface of the semiconductor element, allowing the dielectric layer to be formed on the etch-stop layer. For example, before the etch-stop layer is formed, a dielectric material is formed in the groove to cover the semiconductor element, then an opening is formed on the dielectric layer to expose the active surface of the semiconductor element, allowing the etch-stop layer to be formed on the active surface of the semiconductor element. The etch-stop layer is made of silicon nitride, and the dielectric material is an organic material or a non-organic material. 
         [0021]    In an embodiment, the semiconductor element is a multi-chip module or a single-chip package. 
         [0022]    In an embodiment, the thickness of the semiconductor element is between 10 to 300 μm. 
         [0023]    In an embodiment, the dielectric layer and the adhesive material are made of different materials, and the dielectric layer is made of an organic material or a non-organic material. 
         [0024]    In an embodiment, the circuit layer has a plurality of conductive vias for being electrically connected with the semiconductor element. 
         [0025]    In an embodiment, the method further comprises forming redistribution layer on the dielectric layer and the circuit layer. The redistribution layer is electrically connected with the circuit layer. After the first portion of the carrier below the groove is removed, the substrate is attached on and electrically connected to the redistribution layer. In an embodiment, the redistribution layer comprises stacked dielectric layer and circuit part and the dielectric part is made of an organic material or a non-organic material. 
         [0026]    In an embodiment, the method further comprises attaching and electrically connecting a substrate onto the circuit layer after the first portion of the carrier below the groove is removed. 
         [0027]    In an embodiment, the method further comprises forming an etch-stop layer on the active surface of the semiconductor element before forming the dielectric layer, allowing the dielectric layer to be formed on the etch-stop layer. For example, before the etch-stop layer is formed, a dielectric material is formed on the adhesive material and the active surface of the semiconductor element, covering the side surfaces of the semiconductor element. Then an opening is formed on the dielectric material to expose the active surface of the semiconductor element, allowing the etch-stop layer to be formed on the act e surface of the semiconductor element. In an embodiment, the etch-stop layer is made of silicon nitride, and the dielectric material is made of an organic material or a non-organic material. 
         [0028]    In an embodiment, the non-organic material is silicon oxide (SiO 2 ) or silicon nitride (Si x N y ), and the organic material is Polyimide (PI), Polybenzoxazole (PBO), or Benzocyclclobutene (BCB). 
         [0029]    Accordingly, in a semiconductor package and a method of fabricating the same according to the present invention, it is no longer required to have a conventional silicon interposer, as a result the overall fabricating cost is significantly reduced, and the fabricating process is simplified, ensuring the productivity and yield of the final semiconductor package to be significantly improved. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0030]    The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein: 
           [0031]      FIG. 1  is a schematic cross-sectional view of a conventional semiconductor package; 
           [0032]      FIGS. 2A-2H  are schematic cross-sectional views of a semiconductor package in accordance with a first embodiment of the present invention, wherein FIGS.  2 B′ and  2 B″ represent other embodiments of  FIG. 2B , FIGS.  2 G° and  2 G″ represent other embodiments of  FIG. 2G , and FIGS.  2 H′ and  2 H″ represent other embodiments of  FIG. 2H . 
           [0033]      FIGS. 3A-3E  are schematic cross-sectional views of a semiconductor package in accordance with a second embodiment of the present invention, wherein FIGS.  3 C′ and  3 C″ represent other embodiments of  FIG. 3C , and FIGS.  3 E′ and  3 E″ represent other embodiments of  FIG. 3E . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0034]    The present invention is described in the following with specific embodiments, an that one skilled in the pertinent art can easily understand other advantages and effects of the present invention from the disclosure of the present invention. 
         [0035]    It is to be understood that the scope of the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. In addition, words such as “on”, “top” and “a” are used to explain the preferred embodiment of the present invention only and should not limit the scope of the present invention. 
         [0036]      FIGS. 2A-2H  are schematic cross-sectional views showing a method of fabricating a semiconductor package  2   a - 2   f  in accordance with a first embodiment of the present invention. 
         [0037]    As shown in  FIG. 2A , a carrier  20  having a plurality of grooves is provided. 
         [0038]    In an embodiment, the carrier  20  is a silicon-containing board. The depth (d) of the groove  200  is a half of the thickness (T) of the carrier  20 . 
         [0039]    As shown in  FIG. 2B , a plurality of semiconductor elements  21  are placed in the groove  200  of the carrier  20 . 
         [0040]    In an embodiment, the semiconductor element  21  has opposing active surface  21   a  and non-active surface  21   b,  and side surfaces  21   a  abutting the active surface  21   a  and the non-active surface  21   b.  A plurality of electrode pads  210  are formed on the active surface  21   a.  Through the non-active surface  21   b,  the semiconductor element  21  is assembled in the groove  200  via a bonding layer  211 , allowing the active surface  21   a  of the semiconductor element  21  to be positioned lower than the surface  20   a  of the carrier  20 , without protruding from the groove  200 . The thickness (t) of the semiconductor element  21  is between 10 and 300 μm, preferably 20 to 150 μm. The thickness (m) of the bonding layer  211  is between 5 to 25 μm. 
         [0041]    Moreover, the bonding layer  211  can be a die attach film (DAF), which can be formed on the non-active surface  21   b  of the semiconductor element  21 , then the semiconductor element  21  is placed in the groove  200 . Alternatively, the bonding layer can be formed in the groove  200  (using a dispensing process shown in FIG.  2 B″), followed by attaching the semiconductor element  21  in the groove via the bonding layer  211 . 
         [0042]    In other embodiments, as shown in FIG.  2 B′, the semiconductor element  21  protrudes the groove  200 , i.e., the active surface  21   a  of the semiconductor element  21  is positioned higher than the surface  20   a  of the carrier  20  to form a height difference (h). 
         [0043]    In an embodiment, the semiconductior eoement is a single-chip structure, such as having two semiconductor elements  21  placed in a groiove  200 . However, the number of semiconductor elements placed in the groove is not limited by two. In other embodiments, as shown in  2 B″, the semiconductor element  21 ′ can be a multichip module. For example, two chips  212   a  and  212   b  are bonded together with the bonding material  212  (epoxy resin) to form a module which is then placed in the groove. 
         [0044]    As shown in  FIG. 2C , following the process described in  FIG. 2B , a dielectric layer  23  is formed on the carrier  20 , the adhesive material  22 , and the active surface  21   a  of the semiconductor element  21 , with a plurality of vias  230  to expose the electrode pads  210  from the vias  230 , 
         [0045]    In an embodiment, the groove  200  is filled with the dielectric layer  23 . 
         [0046]    In an embodiment, the dielectric layer  23  is made of a non-organic material such as silicon oxide (SiO 2 ) or silicon nitride (Si x N y ) or an organic material such as Polyimide (PI), Polybenzoxazole (PBO), or Benzocyclclobutene (BCB). The dielectric layer  23  and the adhesive material  22  are made of different materials. 
         [0047]    In addition, vias  230  can be formed using chemical reactions (such as etching) or physical methods (such as laser). 
         [0048]    As shown in  FIG. 2D , a circuit layer  24  is formed on the dieelctric layer  23 , to form the conductive blid vias  240  in the vias  230 , allowing the circuit layer  24  to be electrically conneceted with the electrode pads  210  of the active surface  21   a  of the semiconductor element  21  through the conductive vias  240 . 
         [0049]    In an embodiment, the circuit layer  24  is a wafer level circuit, not packaging substrate level circuit. The minimal width and spacing of the circuits for packaging substrate is 12 μm but the semiconductor process, it is possible to fabricate circuits below 3 μm in terms of width and spacing. In an embodiment, since the carrier  20  is made of a silicon-containing material, the heat expansion coefficient thereof is similar to that of the semiconductor element  21 . Therefore, it is possible to prevent the occourance of warpage of the carrier  20  leading to breakage of the semiconductor element  21 , resulted from tempearture shift during fabricating process, so as to prevent mismatch between the conductive vias  240  and the electrode pads  210 . 
         [0050]    As shown in  FIG. 2E , a redistribution lyer  25  is formed (RDL process) on the dielectric layer  23  and the circuit layer  24  and electrically connected with the circuit layer  24 . 
         [0051]    In an embodiment, the redistribution layer  24  comprises stacked dielectric part  250 , circuit part  251  and insulative protective layer  26 . The insulative protective layer  26  has a plurality of openings  260 , allowing the circuit part  251  to be exposed from the openings  260 , for the conductive elements  27  to be bonded thereon. 
         [0052]    Moreover, the dielectric layer  250  is made of a non-organic material such as silicon oxide (SiO 2 ) or silicon nitride (Si x N y  an organic material such as Polyimide (PI), Polybenzoxazole (PBO), or Benzocyclclobutene (BCB). 
         [0053]    As shown in  FIG. 2F , the first portion of the carrier below the groove  200  and the bonding layer  211  is removed to expose the non-active surface  21   b  of the semiconductor element and the adhesive matieral, so as to keep the second of the carrier on the side wall of the groove  200  intact, for the second portion to function as a supporting part  20 ′. 
         [0054]    In an embodiment, the supporting part  20 ′ is a frame, and the thickness (t) of the semiconductor element  21  is not greater than the height (H) of the supporting part  20 ′. In another example, the thickness (t′) of the semiconductor element  21  is greater than the height (H) of the supporting part  20 ′. 
         [0055]    In an embodiment, the non-organic material is silicon oxide (SiO 2 ) or silicon nitride (Si x N y ), and the organic material is Polyimide (PI), Polybenzoxazole (PBO), or Benzocyclclobutene (BCB). 
         [0056]    In summary, since it is no longer required to have a silicon interposer in the semiconductor package according to the present inventionas, the overall fabricating cost is significantly reduced, and the fabricating process is simpified, ensuring the productivity and yield of the final semiconductor package to be significantly improved. 
         [0057]    Moreover, since there is no silicon interposer in the semiconductor package according to the present invention, the overall thickness of the final product is much reduced, allowing the semiconductor element to operation faster. 
         [0058]    In addition, since the carrier is made of a silicon-containing material, the carrier is less likely to suffer from warpage. 
         [0059]    Moreover, the supporting part is able to increase the strength of the overall structure of the semiconductor package. 
         [0060]    The present invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.