Abstract:
Circuitry for adding a first binary number (A) having a plurality of bits (a 0 , a 1 , . . . ) to a second binary number (B) having a plurality of bits (b 0 , b 1 , . . . ) to produce a third binary number (A+B) having a plurality of bits (s 0 , s 1 , . . . ) and/or a fourth binary number (A+B+1) having a plurality of bits (s 0 ′, s 1 ′, . . . ) and corresponding to the addition of the third binary number and one. The circuitry includes a plurality of stages wherein each stage has a first input for receiving a bit (a i ) of the first binary number (A), a second input for receiving a bit (b i ) of the second binary number (B) having the same binary weight (i) as the bit received at the first input and output means for producing a bit (s i ) of the third binary number (A+B) and/or a bit (s′ i ) of the fourth binary number (A+B+1), wherein said output means comprises exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number and the first signal and a third signal to produce a bit of the fourth binary number wherein said third signal is equivalent to said second signal if both the bits received at the first and second inputs have a LOW logic value, or for any stage having a lower binary weight, both the bits received at the first and second inputs have a LOW logic value and is otherwise equivalent to a predetermined logic value.

Description:
TECHNICAL FIELD 
     The present invention relates to circuitry for adding a binary number A to a binary number B and/or for summing binary number A, the binary number B and the number  1 , and, more particularly, the invention relates to circuitry that simultaneously provides the sum of the binary numbers A and B and the sum of the binary numbers A, B and 1. Other embodiments of the invention include circuitry for selectively summing the binary numbers A and B or the binary numbers A, B, and 1. 
     BACKGROUND OF THE INVENTION 
     FIG. 1 illustrates known circuitry for summing the binary number A and the binary number B. The binary number A is represented as a series of bits a i  where i is the binary weight of the bit a i  and increases from the value zero for the least significant bit of A in steps of one to the value of the most significant bit of A. In the examples, A and B are eight bit numbers although only three bits are shown in FIG.  1 . The binary number B is a series of bits b i  where i is the binary weight of the bit. The summation of the numbers A and B is represented by the binary number S which is a series of bits s i  where i is the binary weight of the bit. The summation of the numbers A, B, and 1 is the number S′ which is a series of bits s′ i , where i is the binary weight of the bit. The addition circuitry illustrated in FIG. 1 receives as inputs the number A, the number B, and an initial carry-in value c 0 . The circuitry produces the number S if the initial carry-in value c 0  is zero and the number S′ if the initial carry-in value c 0  is one. The addition circuitry has a sequence of full adders. The first full adder receives the least significant bit of the numbers A and B and the initial carry-in value c 0 . It produces the least significant bit of the summation signal S or S′ and a first carry-in value c 1 . The second full adder has the binary weight of one, and receives the first carry signal c 1  and the bit values a 1  and b 1 . The second full adder produces as an output S 1  or S′ 1  and the second carry value c 2 . There will generally be as many full adders serially interconnected as there are bits in the numbers A and B. 
     The relationship of the bits s i  output from the full adders when the initial carry-in c 0  is zero to the bits a i  and b i  received is illustrated in equation 1. In this equation i represents the binary weight, a i  is the ith bit of A, b i  is the ith bit of B, g i  is the bit generate, p i  is the bit propagate, c i  is the carry produced by the ith full adder and s i  is the ith bit of S, the sum of A and B. 
     Equation 2 illustrates the relationship of the output of the ith full adder to the bit values a i  and b i  when the initial carry value c 0  is one. The symbol i represents the binary weight of a bit. a i  is the ith bit of A, b i  is the ith bit of B, g i  is the bit generate, p i  is the bit propagate, c i  is the carry produced by the ith full adder and S′ i  is the ith bit of the number S′ which is the sum of A, B and 1. 
     Addition circuitry is commonly used to round a fractional number up or down to the nearest full number. By controlling the value of the initial carry-in value c 0  the output from the circuitry can represent either the rounded up sum S′, i.e. A+B+1 or the rounded down sum A, i.e., A+B. 
     Addition circuitry is also commonly used to find the difference between two binary numbers A and B where A and B are expressed as two&#39;s complement. When a number is expressed in two&#39;s complement format, it can be negated by either inverting all the bits of the number and then adding one or by subtracting one and then inverting all the bits of that number. Consequently, by performing appropriate inversions, addition circuitry can be used to create an output signal which represents a difference of two numbers. 
     In current video encoding standards, it is often necessary to find the absolute difference (i.e., unsigned (+ve) difference) between two numbers. According to the MPEG video encoding standards, the video is encoded by comparing how a picture changes frame by frame rather than reproducing the whole picture frame by frame. It is consequently necessary to determine whether a picture has changed from one frame to the next. This may be achieved by comparing a block of pixels in a frame to a number of blocks in the next frame to establish the block with the smallest difference. A number can be used to represent the attributes of a pixel. As attributes of the pixel change so does the number. Consequently, by comparing such numbers for one frame with the equivalent numbers for the next frame it can be deduced how the picture has changed from one frame to the next. It is therefore important in video encoding to be able to find the difference between two numbers. Normally, two separate circuits will be provided, one circuit that calculates the value of the first number minus the second number and another circuit that calculates the value of the second number minus the first number. 
     FIG. 2 illustrates in more detail addition circuitry  30  for summing A and B to produce S. The bit a 0  and the bit b 0  are supplied as inputs to an AND gate  2   0  which produces the bit generate g 0 . The bit a 0  and the bit b 0  are also supplied as inputs to an XOR gate  4   0  which produces s 0  as its output. The bit a 1  and the bit b 1  are supplied as inputs to an XOR gate  4   1  which produces the first bit propagate signal p 1 . The bit generate signal g 0  and the first bit propagate signal p 1  are supplied as inputs to an XOR gate  24   1  which produces the bit s 1 . The bit a 1  and the bit b 1  are also supplied as inputs to an OR gate  6   1  which supplies its output as a first input to an AND gate  8   1 . The second input of the AND gate  8   1  is received from the output of the AND gate  2   0 . The output of the AND gate  8   1  provides a first input to an OR gate  10   1 . The second input to the OR gate  10   1  is received from an AND gate  2   1  which receives as inputs the bit a 1  and the bit b 1 . The bit a 2  and the bit b 2  are supplied as inputs to an XOR gate  4   2  which provides its output as a first input to a XOR gate  24   2 . The second input to the XOR gate  24   2  is provided by the output of the OR gate  10   1 . The output of the XOR gate  24   2  provides the bit S 2 . The bit a 2  and the bit b 2  are also combined in an OR gate  6   2  to produce a first input to an AND gate  8   2  which receives as a second input the output from the OR gate  10   1 . The output from the AND gate  8   2  supplied as a first input to a OR gate  10   2 . The second input to the OR gate  10   2  is supplied by a AND gate  2   2  which receives as an input the bits a 2  and b 2 . 
     The output of the OR gate  10   2  is supplied as a first input to a XOR gate  24   3 . The second input to the XOR gate  24   3  is supplied by the output of an XOR gate  4   3  which receives as inputs the bit a 3  and the bit b 3 . The output of the XOR gate  24   3  provides the bit s 3 . An AND gate  2   3  also receives the bits a 3  and b 3  and provides its output as a first input to a OR gate  16   3 . The second input to the OR gate  16   3  is provided by an AND gate  14   3  which receives as a first input the output from the AND gate  2   2  and as a second input the output from an OR gate  6   3  which receives as inputs the bit a 3  and bit b 3 . The output from the OR gate  6   3  is also provided as a first input to an AND gate  12   3  which receives as a second input the output from the OR gate  6   2 . 
     The output from the AND gate  12   3  is supplied as a first input to an AND gate  8   3  which receives as a second input the output from the OR gate  10   1 . The output from the AND gate  8   3  and the output from the OR gate  16   3  are combined in an OR gate  10   3 . A XOR gate  24   4  receives as a first input the output from the OR gate  10   3  and as a second input the output from an XOR gate  4   4  which receives as inputs the bit a 4  and the bit b 4 . The XOR gate  24   4  produces the bit S 4 . An OR gate  6   4  receives an inputs the bit a 4  and bit b 4  and provides its output as a first input to an AND gate  8   4 . The AND gate  8   4  receives as its second input the output from the OR gate  10   3  and provides its output to a OR gate  10   4 . The other input to the OR gate  10   4  is provided by an AND gate  2   4  which receives as inputs the bit a 4  and the bit b 4 . An XOR gate  24   5  produces the bit s 5  and receives as a first input the output from the OR gate  10   4  and receives as a second input the output from an XOR gate  4   5  which receives as inputs the bit a 5  and the bit b 5 . An AND gate  12   5  receives as a first input the output from the OR gate  6   4  and an output from an OR gate  6   5  which receives as inputs the bit a 5  and the bit b 5 . 
     An OR gate  16   5  receives as a first input the output from an AND gate  2   5  which receives as inputs the bit a 5  and the bit b 5  and as a second input receives the output from an AND gate  14   5  which itself receives as inputs the output from the AND gate  2   4  and the output from the OR gate  6   5 . The output from the AND gate  12   5  is combined with the output from the OR gate  10   3  in an AND gate  8   5  to produce a first input to a first OR gate  10   5 . The second input to the OR gate  10   5  is provided by the output from the OR gate  16   5 . The output from the OR gate  10   5  is provided as a first input to the XOR gate  24   6 . The XOR gate  24   6  receives as a second input the output from the XOR gate  4   6  which receives as inputs the bit a 6  and the bit b 6 . The XOR gate  24   6  produces as an output the bit S 6 . 
     An OR gate  6   6  receives as its inputs the bit a 6  and the bit b 6  and supplies its output as a first input to an AND gate  12   6 . The second input to the AND gate  12   6  is supplied by the output of the AND gate  12   5  and the output of the AND gate  12   6  is supplied as a first input to an AND gate  8   6 . The output from the OR gate  6   6  is supplied as a first input to an AND gate  14   6 . The AND gate  14   6  receives as a second input the output from the OR gate  16   5  and provides an output signal to a first input of an OR gate  16   6 . The second input to the OR gate  16   6  is supplied by an AND gate  2   6  which receives as inputs the bit a 6  and the bit b 6 . The AND gate  8   6  which receives as a first input the output from the AND gate  12   6  receives as a second input the output from the OR gate  10   3  and provides its output as a first input to an OR gate  10   6 . The second input to the OR gate  10   6  is provided by the output of the OR gate  16   6 . The output of the OR gate  10   6  is provided as a first input to an XOR gate  24   7 . The XOR gate  24   7  receives as a second input the output from an XOR gate  4   7  which receives as inputs the bit a 7  and the bit b 7 . The XOR gate  24   7  produces the bit s 7 . 
     The bit a 7  and the bit b 7  are combined in an OR gate  6   7  to produce a first input to an AND gate  18   7  which receives as a second input the output from the OR gate  6   6 . The output from the OR gate  6   7  is supplied as a first input to an AND gate  20   7 . The AND gate  20   7  receives as a second input the output from the AND gate  2   6 . The output from the AND gate  20   7  is supplied as a first input to an OR gate  22   7 . The second input to the OR gate  22   7  is provided by a AND gate  2   7  which receives as its inputs the bit signal a 7  and the bit signal b 7 . 
     An AND gate  14   7  receives as its inputs the output from the AND gate  18   7  and the output from the OR gate  16   5  and provides its output as a first input to an OR gate  16   7 . The second input to the OR gate  16   7  is supplied by the output of the OR gate  22   7 . The output of the OR gate  16   7  is provided as a first input to an OR gate  10   7 . An AND gate  12   7  receives as its inputs the output from the AND gate  12   5  and the output from the AND gate  18   7 . The output from the AND gate  12   7  is supplied as a first input to the AND gate  8   7 . The AND gate  8   7  receives as a second input the output from the OR gate  10   3 . The output from the AND gate  8   7  is supplied as a second input to the OR gate  10   7 . The output of the OR gate  10   7  produces the last carry value c 8 . 
     FIG. 3 illustrates addition circuitry for summing the numbers A, B and c 0 . The value of c 0  may be zero or one. When the value of c 0  is zero the circuitry of FIG. 3 is functionally equivalent to that of FIG.  2  and the output value from the circuit is S. When the value of the initial carry-in value c 0  is one, the circuitry produces an output signal S′. The summation circuitry illustrated in FIG. 3 has addition circuitry  30  illustrated in FIG.  2  and has additional circuitry  26  enclosed by the dotted line. The additional circuitry  26  has an OR gate  6   0  for receiving the bit a 0  and the bit b o . The OR gate  6   0  provides a first input to a first AND gate  8   0 . The second input to the AND gate  8   0  is provided by c 0 . The output from the AND gate  8   0  is provided as a first input to an OR gate  10   0 . The second input to the OR gate  10   0  is provided by the output of the AND gate  2   0 . The output of the OR gate  10   0  provides one of the inputs to an XOR gate  24   1  and one of the inputs to the AND gate  8   1  and in place of the output from the AND gate  2   0 . 
     It will be appreciated that the circuitry in FIG. 3 can produce as its output the value A+B or the value A+B+1 depending on the value of c 0 . It cannot however quickly switch between producing an output A+B and producing an output A+B+1. The value of c 0  when it changes must pass through the succession of gates  8   i ,  10   i  before it can effect a change in the output signal. 
     It would be desirable to provide circuitry which can quickly change between producing an output value A+B and output value A+B+1 or which can simultaneously provide an output value A+B and an output value A+B+1. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the invention there is provided circuitry for adding a first binary number (A) having a plurality of bits (a 0 , a 1 , . . . ) to a second binary number (B) having a plurality of bits (b 0 , b 1 , . . . ) to produce a third binary number (A+B) having a plurality of bits (s 0 , s 1 , . . . ) and/or a fourth binary number (A+B+1) having a plurality of bits (s 0 ′, s 1 ′ . . . ) and corresponding to the addition of the third binary number and one. 
     The circuitry further includes a plurality of stages wherein each stage has a first input for receiving a bit (a i ) of the first binary number (A), a second input for receiving a bit (b i ) of the second binary number (B) having the same binary weight (i) as the bit received at the first input and output means for producing a bit (s i ) of the third binary number (A+B) and/or a bit (s′ i ) of the fourth binary number (A+B+1), wherein said output means comprises Exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number and the first signal and a third signal to produce a bit of the fourth binary number wherein said third signal is equivalent to said second signal if both the bits received at the first and second inputs have a LOW logic value, or for any stage having a lower binary weight, both the bits received at the first and second inputs have a LOW logic value and is otherwise equivalent to a predetermined logic value. 
     Said second signal for a first stage can correspond to a high logic level if the bit of the first binary number and the bit of the second binary number received at the first and second inputs of the first stage are both high or, for a second stage having a lower binary weight, both the first and second bits received at the first and second inputs have a high logic value and in none of the stages intermediate between said first and second stage are the first and second bits input at the first and second inputs both low logic values. 
     Said second signal for a stage can correspond to a high logic value if the stage generates or if a preceding stage generates and one of the intermediate stages kill. 
     Ideally, each stage produces an output bit of the third binary number according to p m rc m  and the output bit of the fourth binary number according to p m r(c m:0 +k m:o ) where c m:0  is the group carry signal and k m:0  is the group carry signal for the stage having binary weight m, and p m  is the propagate bit. 
     According to another aspect of the invention there is provided addition circuitry for adding a first binary number (A) having a plurality of bits (a 0 , a 1 , . . . ) to a second binary number (B) having a plurality of bits (b 0 , b 1 , . . . ) to produce a third binary number (A+B) having a plurality of bits (s 0 , s 1 , . . . ) and/or a fourth binary number (A+B+1) having a plurality of bits (s 0 ′, s 1 ′, . . . ) and corresponding to the third binary number plus one. The circuitry includes a plurality of stages wherein each stage has a first input for receiving a bit (a i ) of the first binary number (A) and a second input for receiving a bit (b i ) of the second binary number (B) having the same binary weight (i) as the bit received at the first input and output means for producing a bit (s i ) of the third binary number (A+B) and/or a bit (s i ) of the fourth binary number (A+B+1). The output means includes Exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number and the first signal and a third signal to produce a bit of the fourth binary number and logic circuitry arranged to receive the second signal and a signal from the logic circuitry from the preceding stage and produce the third signal, wherein the logic circuitries of the plurality of stages emulate the application of a HIGH carry signal provided to the first stage of lowest binary weight. 
     The logic circuitry can include an AND gate and an OR gate. The AND gate in the preceding stage supplies a first input to the OR gate and the second input to the OR gate is the second signal. 
     The AND gate in each stage can produce an output with a low logic value if both the first and second bit received at that stage are low or both the first and second bit received at any preceding stage are low. 
     The exclusive OR means can include an XOR gate the output of which provides the bit of the third binary number or the bit of the fourth binary number in dependence on the value of a received control signal, wherein said control signal gates the first input to the OR gate of said logic circuitry. 
     According to a still further aspect of the invention there is provided addition circuitry for adding a first binary number (A) having a plurality of bits (a 0 , a 1 , . . . ) to a second binary number (B) having a plurality of bits (b 0 , b 1 , . . . ) to produce a third binary number (A+B) having a plurality of bits (s 1 , s 1 , . . . ) and/or a fourth binary number (A+B+1) having a plurality of bits (s 0 ′, s 1 ′, . . . ) and corresponding to the third binary number plus one. The circuitry includes a plurality of stages wherein each stage has a first input for receiving a bit (a i ) of the first binary number (A) and a second input for receiving a bit (b i ) of the second binary number (B) having the same binary weight (i) as the bit received at the first input and output means for producing a bit (s i ) of the third binary number (A+B) and/or a bit (s i ) of the fourth binary number (A+B+1). The output means includes Exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number and the first signal and a third signal to produce a bit of the fourth binary number and logic circuitry arranged to logically OR the second signal and a signal received from the logic circuitry of the preceding stage to produce the third signal and to provide a signal to the logic circuitry of the next stage dependent upon the logic value of the signal received from the preceding stage and the first and second bits received by the stage. 
     In one embodiment, the signal provided by the logic circuitry to the next stage has a high logic value if the signal received from the logic circuity at the preceding stage has a high logic value and one or both of the first and second bits have a high logic value. 
     According to a yet another aspect of the invention there is provided circuitry for adding a first binary number having a plurality of bits to a second binary number having a plurality of bits to produce a third binary number having a plurality of bits and a fourth binary number having a plurality of bits and corresponding to the third binary number plus one. The circuitry includes a plurality of stages wherein each stage includes: 
     a first input for receiving a bit of the first binary number; 
     a second input for receiving a bit of the second binary number having the same binary weight as the bit received at the first input; 
     first output means for producing a bit of the third binary number and comprising exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number; and 
     second output means for producing a bit of the fourth binary number comprising exclusive OR means for combining the first signal and a third signal to produce a bit of the fourth binary number, wherein said first and second output means produce the third and fourth binary numbers substantially simultaneously. 
     According to a still further aspect of the invention there is provided circuitry for adding a first binary number having a plurality of bits to a second binary number having a plurality of bits to produce a third binary number having a plurality of bits or a fourth binary number having a plurality of bits and corresponding to the third binary number plus one. The circuitry includes a plurality of stages wherein each stage includes: 
     a first input for receiving a bit of the first binary number; 
     a second input for receiving a bit of the second binary number having the same binary weight as the bit received at the first input; and 
     output means for producing a bit of the third binary number or a bit of the fourth binary number, wherein said output means comprises exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number or the first signal and the third signal to produce a bit of the fourth binary number, said exclusive OR means operating in dependence on the value of a single independent control signal being supplied directly to said output stage. 
     According to a still yet another aspect of the invention there is provided circuitry for adding a first binary number having a plurality of bits to a second binary number having a plurality of bits to produce a third binary number having a plurality of bits or a fourth binary number having a plurality of bits and corresponding to the third binary number plus one. The circuitry includes a plurality of stages wherein each stage includes: 
     a first input for receiving a bit of the first binary number; 
     a second input for receiving a bit of the second binary number having the same binary weight as the bit received at the first input; and 
     output means for producing a bit of the third binary number or a bit of the fourth binary number, wherein said output means comprises exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number or the first signal and a third signal to produce a bit of the fourth binary number, said exclusive OR means being supplied by logic circuitry comprising an AND gate and an inverter which are supplied in parallel with said second signal, said logic circuitry being operable to produce said second or third signal in dependence upon a control signal. 
     According to a further aspect of the invention there is provided circuitry for adding a first binary number having a plurality of bits to a second binary number having a plurality of bits to produce a third binary number having a plurality of bits or a fourth binary number having a plurality of bits and corresponding to the third binary number plus one. The circuitry includes a plurality of stages wherein each stage includes: 
     a first input for receiving a bit of the first binary number; 
     a second input for receiving a bit of the second binary number having the same binary weight as the bit received at the first input; and 
     output means for producing a bit of the third binary number or a bit of the fourth binary number, wherein said output means comprises exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number or a first signal and a third signal to produce a bit of the fourth binary number, said exclusive OR means being supplied by logic circuitry comprising an AND gate and an inverter which are supplied in parallel with said second signal, said logic circuitry being operable to produce said second or third signal in dependence upon the value of a control signal supplied from the most significant stage of carry and propagation circuitry disposed between said input and said output means. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a better understanding of the present invention and to understand how the same may be brought into effect reference will now be made by way of example only to the accompanying figures. 
     FIGS. 1A-1C illustrate prior art circuitry for producing A+B or A+B+1 and associated equations 1 and 2; 
     FIG. 2 illustrates prior art circuitry for producing A+B in more detail; 
     FIG. 3 illustrates circuitry, known in the prior art, suitable for producing A+B or A+B+1 in more detail; 
     FIG. 4 illustrates addition circuitry for simultaneously producing A+B and A+B+1 in accordance with a first embodiment of the present invention; 
     FIG. 5 illustrates addition circuitry according to a second embodiment of the present invention for selectively producing A+B or A+B+1; 
     FIG. 6 illustrates addition circuitry according to a third embodiment for simultaneously producing A−B and B−A; 
     FIG. 7 illustrates addition circuitry according to a fourth embodiment for selectively producing A−B or B−A; 
     FIG. 8 illustrates addition circuitry for “automatically” selecting the absolute value |A−B|; and 
     FIGS. 9A-9F are equations 3 through 6c corresponding to the embodiments of the invention illustrated in FIGS.  2  through  7 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 4 illustrates addition circuitry suitable for producing simultaneously the output S having bit values s i  corresponding to the addition of A and B and producing the number S′, having bit values s′ i , corresponding to the summation of the numbers A, B and 1. The circuitry illustrated in FIG. 4 has summation circuitry  30  equivalent to that illustrated in FIG.  2  and includes additional circuitry  32 , the boundary of which is illustrated by a dashed line. The additional circuitry  32  produces the output values s′ i . The additional circuitry has an inverter  36 , and OR gate  34   0 , an OR gate  34   1 , an XOR gate  40   1 , an AND gate  38   2 , an OR gate  34   2 , an XOR gate  40   2 , an AND gate  38   3 , an OR gate  34   3 , an XOR gate  40   3 , an AND gate  38   4 , an OR gate  34   4 , an XOR gate  40   4 , an AND gate  38   5 , an OR gate  34   5 , and XOR gate  40   5  an AND gate  38   6 , an OR gate  34   6 , an XOR gate  40   6 , an AND gate  38   7 , an OR gate  34   7 , an XOR gate  40   7 , an AND gate  38   8 , and an OR gate  34   8 . The inverter  36  receives as its input the output from the XOR gate  4   0  and produces as its output the bit s′ 0 . The OR gate  34   0  receives as its inputs the bit a 0  and the bit b 0 . The OR gate  34   1  receives as its inputs the output from the OR gate  34   0  and the output from the AND gate  2   0 . 
     The XOR gate  40   1  receives as its inputs the output from the OR gate  34   1  and the output from the XOR gate  4   1 . The output from the XOR gate  40   1  is the bit s′ 1 . The AND gate  38   2  receives as its input the output from the OR gate  34   0  and the output from the OR gate  6   1 . The OR gate  34   2  receives as its inputs the output from the AND gate  38   2  and the output from the OR gate  10   1 . The XOR gate  40   2  receives as its inputs the output from the OR gate  34   2  and the output from the XOR gate  4   2 . The output from the XOR gate  40   2  is the bit s′ 2 . The AND gate  38   3  receives as its inputs the output from the AND gate  38   2  and the output from the OR gate  6   2 . The OR gate  34   3  receives as its inputs the output from the AND gate  38   3  and the output from the OR gate  10   2 . 
     The XOR gate  40   3  receives as its inputs the output from the OR gate  34   3  and the output from the XOR gate  4   3 . The output of the XOR gate  40   3  provides the bit s′ 3 . The AND gate  38   4  receives as its inputs the output from the AND gate  38   2  and the output from the AND gate  12   3 . The OR gate  34   4  receives as its inputs the output from the AND gate  34   4  and the output from the OR gate  10   3 . The XOR gate  40   4  receives as its inputs the output from the OR gate  34   4  and the output from the XOR gate  4   4 . The output from the XOR gate  40   4  is the bit s′ 4 . The AND gate  38   5  receives as its inputs the output from the AND gate  38   4  and the output from the OR gate  6   4 . The OR gate  34   5  receives as its inputs the output from the AND gate  38   5  and the output from the OR gate  10   4 . The XOR gate  40   5  receives as its inputs the output from the OR gate  34   5  and the output from the XOR gate  4   5 . The output from the XOR gate  40   5  produces the bit s′ 5 . The AND gate  38   6  receives as its inputs the output from the AND gate  38   4  and the output from the AND gate  12   5 . The OR gate  34   6  receives as its inputs the output from the AND gate  38   6  and the output from the OR gate  10   5 . 
     The XOR gate  40   6  receives as its inputs the output from the OR gate  34   6  and the output from the XOR gate  4   6 . The output from the XOR gate  40   6  provides the bit s′ 6 . The AND gate  38   7  receives as its inputs the output from the AND gate  38   4  and the output from the AND gate  12   6 . The OR gate  34   7  receives as its inputs the output from the AND gate  38   7  and the output from the OR gate  10   6 . The XOR gate  40   7  receives as its inputs the output from the OR gate  34   7  and the output from the XOR gate  4   7 . The output from the XOR gate  40   7  provides the bit s′ 7 . The AND gate  38   8  receives as its inputs the output from the AND gate  38   4  and the output from the AND gate  12   7 . The OR gate  34   8  receives as its inputs the output from the AND gate  38   8  and the output from the OR gate  10   7 . The OR gate  34   8  produces the carry signal c 8 ′ that is the carry signal having a binary weight of 8 produced for the sum A+B+1. 
     FIG. 5 illustrates summation circuitry  50  which receives a control signal INC. The summation circuitry  50  sums the number A and the number B to produce either the number S, i.e. A+B, or the number S′, i.e. A+B+1 depending upon the value of a control signal INC. When the value of INC is zero, the output of this summation circuitry  50  is the sum of A and B, i.e. S. When the value of INC is one, the summation circuitry  50  produces as its output the value of A+B+1, i.e., S′. The summation circuitry  50  illustrated in FIG. 5 is an adaptation of the circuitry illustrated in FIG.  2  and where like numerals are used they refer to like features. The summation circuitry  50  can be considered to have a number of separate stages where a stage having binary weight i receives input bits a i  and b i  binary weight i and produces outputs s i  or s′ i  having binary weight i. For example, the i=0 stage produces the output bit s 0  or s′ 0  and the i=7 stage produces the output signal s 7  or s′ 7 . Comparing the summation circuitry  50  illustrated in FIG. 5 with circuitry illustrated in FIG. 2 it will be appreciated that the stage corresponding to i=0 has as additional circuitry an OR gate  34   0  and an XOR gate  54 . The i=1 stage has as additional circuitry an AND gate  52   1  and an OR gate  34   1 . The i=2 stage has as additional circuitry an AND gate  38   2 , an AND gate  52   2  and an OR gate  34   2 . The i=3 stage has as additional circuitry an AND gate  38   3 , an AND gate  52   3  and an OR gate  34   3 . The i=4 stage has as additional circuitry an AND gate  38   4 , and AND gate  52   4  and an OR gate  34   4 . The i=5 stage has as additional circuitry an AND gate  38   5 , an AND gate  52   5  and an OR gate  34   5 . The i=6 stage has as additional circuitry the AND gate  38   6 , an AND gate  52   6  and the AND gate  34   6 . The i=7 stage has as additional circuitry the AND gate  38   7 , an AND gate  52   7  and the OR gate  34   7 . The i=8 stage which produces the final carry value has as additional circuitry the AND gate  38   8 , an AND gate  52   8  and the OR gate  34   8 . 
     It will be appreciated that the above-mentioned additional circuitry in the summation circuitry  50  differs only from the additional circuitry  32  described in relation to FIG. 4 in that the inverter  36  has been replaced by the XOR gate  54  which receives as its second input the signal INC, and in the provision of the additional AND gates  52   i  where i=1,2 . . . 8. The AND gate  52   1  receives as a first input the output from the OR gate  34   0  and as a second input signal INC. It supplies its output to the OR gate  34   1 . The AND gate  52   i , where i=2,3 . . . 8, receives as a first input the output from the AND gate  38   i  and as a second input signal INC. The output from the gate  52   i , where i=2,3 . . . 8, is supplied as an input to the OR gate  34   i . 
     Formalism for Addition 
     Let A and B be binary words each of N bits, and let a i  and b i  be bits of those words such that a 0  and b 0  are the least significant bits and a N−1 , and b N+1  are the most significant bits. The addition process at each bit position can be defined as follows: 
     g i =a i .b i    
     p i =a i ⊕b i    
     k i =a i +b i    
     c i+1 =g i +k i ·c i    
     s i =p i ⊕c i    
     where ‘.’ is binary AND, ⊕ is binary EXOR, and overline indicates binary NOT. 
     c 1  is a binary carry bit. Each bit position receives a carry from the adjacent less significant bit position and passes a carry to the adjacent more significant bit position. The binary weight of c i  is the same as that of bits a i  and b i . 
     s i  is the sum bit; the corresponding word S is the result of the addition of A and B. 
     According to the convention used herein: 
     g i  is called the bit generate condition, because a value 1 indicates that the bits a i  and b i  produces an outgoing carry, irrespective of the incoming carry. 
     p i  is called the bit propagate condition because a value 1 indicates that the bits a i  and b i  produces an outgoing carry only if there is an incoming carry. 
     k i  is called the bit kill condition, because a value 1 indicates that the bits a i  and b i  produces no outgoing carry, irrespective of the incoming carry. 
     This formalism embodies a sequential propagation of carries from least significant to most significant bit position as illustrated in FIG.  1 . Frequently a literal implementation of this sequentiality yields a circuit which is too slow. The adder may be accelerated by forming “group generate” and “group kill” (or optionally “group propagate”) terms which represent the collective treatment of carries across a number of adjacent bit positions. A common form of accelerated adder is the prefix construction, one form of which is described in FIGS. 2 and 3. 
     A group generate is expressed as g i:j . A value of one indicates that the sequence of stages having binary weight j, j+1, . . . i−1, i where j&lt;i in combination produce an output carry value (c i+1 ) of one irrespective of the input of the carry value (c j ). A stage having a binary weight i is the part of the summation circuitry which receives the bits a i  and b i  and produces the output s i  or s′ i . 
     A group kill is expressed as k i:j . A value of one indicates that the sequence of stages having binary weight j, j+1, . . . i−1, i in combination produces an output carry value (c i+1 ) of zero irrespective of the input carry value (c j ). 
     A group carry is expressed as c i+1:j . It represents the output carry value of the combination of a sequence of stages having binary weight j, j+1, . . . i−1, i, where the combination of stages receives an input carry value (c j:0 ). 
     The bit s i  of the sum S of A and B can thus be expressed as shown in equation 3. 
     The functionality of embodiments of the invention will now be explained. Reference is made to equation 4 in which a bit operator “*” is defined. The group carry values c i:0  can be produced from bit kills and bit generates as shown in equation 5. These equations define a binary tree of cells which is implemented in the circuitries of FIGS. 2,  3 ,  4 ,  5 ,  6  and  7 . Referring to these figures, the outputs of the OR gates  6   i  where i equals 0, 1 . . . 7 produce the inverted bit kill values k i . The outputs of the AND gates  2   i  where i equals 0, 1, 2, . . . 7 produce the bit generate values g i . The outputs of the XOR gates  4   i  where i equals 0, 1, 2 . . . 7 produce the bit propagate values p i . The outputs of the OR gate  10   i  where i equals 1, 2, 3 . . . 7 produce the carry values c i+1:0  respectively. The output of the AND gate  12   3  produces the inverted group kill k 3:2  and the output of the OR gate  16   3  produces the group carry value c 4:2 . The output of the AND gate  12   5  produces the inverted group kill k 5:4  and the output of the OR gate  16   5  produces the group carry value c 6:4 . The output of the AND gate  12   6  produces the inverted group kill k 6:4  and the output of the OR gate  16   6  produces the group carry value c 7:4 . The output of the AND gate  18   7  produces the inverted group kill k 7:6  and the output of the OR gate  22   7  produces the carry value c 8:6 . The output of the AND gate  12   7  produces the inverted group kill k 7:4  and the output of the OR gate  16   7  produces the group carry value c 8:4 . 
     It will be realised that the bit operation “*” is achieved by the use of two AND gates and an OR gate in combination. Referring back to equation 4, the bit k i  is provided as a first input to a first AND gate and as a first input to a second AND gate, the bit k j  is supplied as a second input to the first AND gate, the bit g j  is supplied as a second input to the second AND gate, the output of the second AND gate is supplied as a first input to an OR gate, and the bit g i  is supplied as a second input to the OR gate. The output of the first AND gate gives inverted group kill k i:j  and the output of the OR gate provides a group carry value c i+1:j . The first AND gate is used to produce the inverted group kill and the combination of the second AND gate and the OR gate is used to produce the group carry. 
     Referring to FIG. 4, it will be appreciated that additional circuitry  32  comprises a plurality of stages each of which produces an output bit s′ j . The pairs of AND gates  38   i  and OR gate  34   i  where i equals 2, 3, 4 . . . 8 to produce group carry values c i+1:0 . The additional circuitry performs a function equivalent to replacing the value illustrated in equation  6   a  in the equations with the value illustrated in equation  6   b . It should be appreciated that the additional circuitry  32  effectively emulates the introduction of a carry value c 0 =1 at the first stage of a first full adder. 
     Referring to FIG. 5, the additional circuitry previously described in relation to that figure performs a function equivalent to replacing the term illustrated in equation  6   a  that are used equations  5  with the term illustrated in equation  6   c . When INC is zero the summation circuitry produces the value A+B and when INC is one the additional circuitry emulates the introduction of a carry value c 0 =1 at the first full adder and the summation circuitry  50  produces the output value A+B+1. 
     FIG. 6 illustrates addition circuitry suitable for producing as outputs the value s=B−A and the value s′=A−B. The addition circuitry in FIG. 6 is very similar to that in FIG.  4 . It comprises the additional circuitry: inverters  62   i , where i=0, 1 . . . 7, which invert the bit values b i  and the inverters  64   i , where i=0, 1, 2 . . . 8, where the inverters  64   i  where i=0, 1 . . . 7, invert the outputs from the XOR gate  24   i  to produce the bit values B−A and the inverter  64   8  inverts the output from the OR gate  10   7  to produce the carry value c 8 . 
     FIG. 7 illustrates addition circuitry suitable for selectively producing the output A−B or the output B−A depending upon-the value of signal NEG. The circuitry in FIG. 7, differs from that in FIG. 5 in that there are no AND gates  52   i  but there is additional circuitry including: inverters  62   i , where i=0, 1 . . . 7, which invert the bit values b i, ; and inverters  64   i , where i=1, 2 . . . 8, positioned in parallel with the OR gates  34   i  such that they receive as inputs the outputs from the OR gates  10   i  and selectively provide their outputs to the same input of the XOR gates  24   i  as the output of the OR gates  34   i . The circuitry of FIG. 7 additionally has multiplexors  66   i , where i=1, 2 . . . 8, which select in dependence upon signal NEG whether the output of the OR gate  34   i  or the output of the NOT gate (inverter)  64   i  is supplied as an input to the XOR gate  24   i . When the signal NEG is one, the output of the OR gates  34   i  is provided as inputs to the XOR gates  24   i  that in turn produces the bit value S i , which is a bit of the number A−B. When the signal NEG is zero, the output of the NOT gates  64   i  are supplied as inputs to the XOR gates  24   i , which in turn produces bit value s i , which are bits of the number S, namely B−A. 
     Referring to FIGS. 6 and 7, for the circuits to operate as subtractors, i.e. the values A−B and B−A as outputs, the inputs numbers A and B must be in twos complement format. When a number is in twos complement format it may be negated by either inverting all the bits of the number and then adding one or by subtracting one to produce a new number and then inverting all the bits of the new number. Consequently, if A and B are represented in twos complement format, the value A−B may be represented as A+NOT(B)+1 which is the output S′ in FIG.  6  and the value B−A may be represented as NOT(A+NOT(B)) which is the value S in FIGS. 6 and 7. 
     FIG. 8 illustrates addition circuitry that is similar to that illustrated in FIG. 7, except that the AND gate  38   8  and NOR gate  34   8  associated with the carry signals c 8 /c 8 ′ are not present. Also, the final multiplexor  66   8  is not present. Instead, the output of the inverter  64   8  in respect of the topmost bit is used to “automatically” select the positive result value *A−B* by using its output as the select signal NEG. In other respects, operation of the circuitry of FIG. 8 is the same as that of FIG.  7 .