Abstract:
The invention relates to a switching power supply circuit for optimum capacitor charging, wherein a power device is connected to a terminal node of a capacitor to be charged and has a control terminal connected to the output of an associated drive circuit. This circuit comprises a second power element being associated with the first power device, connected to said terminal node, and provided with a control terminal which is connected directly to the output of respective drive logic. Advantageously, the second power element is driven to turn off when a voltage below a predetermined minimum is present at the capacitor, thereby pulling the voltage at the terminal node to ground and further charging the capacitor.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
         [0001]    The present application claims priority from Italian patent application No. M12001A002605, filed Dec. 11, 2001, which is incorporated by reference.  
         TECHNICAL FIELD  
         [0002]    The present invention relates generally to a power supply circuit for optimum bootstrap capacitor charging. In particular, the invention relates to a switching power supply circuit for the optimum charging of a bootstrap capacitor, wherein a power device is connected to a terminal node of the capacitor to be charged and has a control terminal connected to the output of an associated drive circuit.  
         BACKGROUND OF THE INVENTION  
         [0003]    In a switching power supply of the step-down type employing an N-channel transistor for a power device, the power transistor is driven by a bootstrapping or charge-pump voltage boosting technique. FIG. 1 herewith is a basic diagram of a bootstrapped power supply  1 .  
           [0004]    The above technique comprises charging a capacitor, called the bootstrap capacitor, which is placed between the output of the power device and the supply V Drive  to the drive circuit or driver of the device. In FIG. 1, this bootstrap capacitor is referenced C b . The supply voltage to the drive circuit is approximately the combined values of the supply voltage V Pow  to the power device T 1  and the voltage at the capacitor C b , i.e.:  
             V   Drive   =V   Pow   +V   Cb   −V   D0 .  
           [0005]    Thus, the voltage drop V gs  across the gate and source terminals of the power device T 1  is always near-constant under varying conditions of operation, i.e., on/off switching of the power device always provides good overdrive.  
           [0006]    Assuming the capacitor C b  to be in a charged initial state, when the power device T 1  is turned on, the node V Pow  is at V cc , but the power device will stay on, since voltage V Drive  is equal to V cc +V cb −V D0 .  
           [0007]    Also, with the power device T 1  on, a current will be circulated such that, as the power device is switched off, the ratio dI I /dt makes the diode D 1  conductive and V Pow ≈0V. Accordingly, the capacitor C b  will be charged by the voltage generator connected to it through the link  2  comprised of components V Cb , D 0 , C b , and D 1 . Of course, this operation would be feasible only when the coil contains sufficient energy to pull the cathode of the diode D 1  below ground.  
           [0008]    The fundamental law for inductors, ΔV L =−L·dI L /dt, indicates that, in the above instance, with the output current I Out  being small, ΔIL will be low, and Δt finite, so that, when the power device changes over, the voltage variation across the coil will be insufficient to pull the cathode of diode D 1  below ground due to parasitic capacitances. Therefore, the capacitor C b  cannot be charged within time T off , and will keep being discharged due to a continual current draw from the drive circuit.  
           [0009]    Thus a condition is ultimately reached of the supply voltage to the drive circuit being unable to drive the power device T 1  as expected.  
           [0010]    An attempt at overcoming this problem is represented by European Patent Application No. EP 0 822 475, which is herein incorporated by reference.  
           [0011]    However, the proposal of that patent application cannot overcome the problem at 100% duty cycle.  
           [0012]    [0012]FIG. 2A is a plot with respect to time for a number of signals that are present in the power supply described in the above patent application. These signal plots clearly show that the above patent application will only drive the duty cycle of the PWM signal to 100% for one period, this PWM signal being the control signal to the power device T 1 . Basically, the coil current is raised to a sufficient ΔV for the cathode of diode D 1  to be pulled to ground and the capacitor C b  charged.  
           [0013]    At the following cycle, when the duty cycle is driven to 0%, the increase in the coil current ΔI L  is large enough at low duty cycles to produce a voltage differential ΔV L  that can place the diode D 1  in forward conduction (proper operation).  
           [0014]    [0014]FIG. 2B shows that at high duty cycles, the relative increase in the current ΔI L  is so small that the voltage differential ΔV L  is inadequate to place the diode D 1  in the forward mode. Thus, the aforementioned patent application cannot overcome the problem when conditions are as outlined above.  
           [0015]    Consequently, there is a need for a power supply that can keep the bootstrap capacitor charged under conditions of a small current I L  and a very high duty-cycle value (close to 100%). As discussed above, with prior art circuits the current will be so small that in this case it cannot pull the cathode of the loop diode below ground, and thus will inhibit the charge current to the bootstrap capacitor.  
         SUMMARY OF THE INVENTION  
         [0016]    An embodiment of the present invention is a circuit having a second power device associated with the power device, wherein the second power device is managed by a logic drive circuit for pulling the potential at the drain terminal of the power device to ground and enabling the charge current to the bootstrap capacitor only when the loop diode cannot be turned conductive.  
           [0017]    Advantageously, the second power device may be associated with any type of supply circuit that employs the bootstrapping technique. Based on this idea, the technical problem is solved by a power supply circuit, as previously indicated, being characterized in that it comprises a second power element, said second power element being associated with said power device, connected to said terminal node, and connected with a control terminal directly to the output of respective drive logic. Advantageously, the second power element is driven to turn off when a lower voltage than a predetermined minimum is present at the capacitor, thereby pulling the voltage at said terminal node to ground and further charging the capacitor. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]    The features and advantages of the power supply circuit according to this invention will become understood from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.  
         [0019]    [0019]FIG. 1 shows schematically a power supply circuit according to the prior art.  
         [0020]    [0020]FIG. 2A shows plots against time for several signals, such as would be present in the power supply circuit of FIG. 1 during low duty-cycle operation according to the prior art.  
         [0021]    [0021]FIG. 2B shows plots against time for several signals, such as would be present in the power supply circuit of FIG. 1 during high duty-cycle operation according to the prior art.  
         [0022]    [0022]FIG. 3 shows schematically a power supply circuit according to an embodiment of the invention.  
         [0023]    [0023]FIG. 4 is a more detailed view of the power supply circuit according an embodiment of to the invention.  
         [0024]    [0024]FIG. 5 shows plots against time for several signals, such as would be present in the power supply circuit of FIG. 4 during high duty-cycle operation according to an embodiment of the invention.  
         [0025]    [0025]FIG. 6 shows a second embodiment of a portion of the power supply circuit of FIG. 3.  
         [0026]    [0026]FIG. 7 shows plots against time for several signals, such as would be present in the power supply circuit of FIG. 6 during high duty-cycle operation according to an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0027]    The following discussion is presented to enable a person skilled in the art to make and use the invention. The general principles described herein may be applied to embodiments and applications other than those detailed below without departing from the spirit and scope of the present invention. The present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.  
         [0028]    With reference to the drawings, in particular to the example of FIG. 3, a power supply circuit for optimum bootstrap capacitor charging, according to an embodiment of this invention, is shown generally at  10  in schematic form.  
         [0029]    Preferably, the circuit  10  would be used as a step-down switching power supply. However, there is no reason why the circuit  10  could not be used in other applications where a capacitor of a given capacitance was to be charged in an optimum manner.  
         [0030]    As shown best in FIG. 3, the differences of the inventive circuit  10  from a conventional design like that shown in FIG. 1 are apparent. A power device T 1  is connected to a terminal node A of a capacitor C b , the latter also having an output circuit LC connected to it. A second power element, in particular a transistor T 2 , is associated with the power device T 1  of FIG. 1 and connected to the node A, it being driven directly from dedicated drive logic  11 .  
         [0031]    Generally, the second power element T 2  is controlled from a logic circuit  11  to pull to ground the potential at its drain terminal, thereby allowing the charge current to the capacitor C b  to go through the link  13  that includes elements such as V Cb , D 0 , C b , and T 2 . The second power element T 2  would take over whenever the diode D 1  is prevented from turning conductive. Thus, when the coil lacks sufficient energy to allow the capacitor C b  to be charged, i.e. when the voltage V Cb  at the bootstrap capacitor is below an admissible minimum for the system, the power element T 2  will be turned on and pull the voltage V Pow  at node A to ground, so that the capacitor C b  can be charged. This removes typical malfunctions of such circuit designs.  
         [0032]    [0032]FIG. 4 shows the construction of the logic circuit  11  in greater detail. The construction of the logic circuit  11  can be said to include the three parts specified here below:  
         [0033]    an output buffer stage  16  connected directly to a control terminal of the second power element T 2 ;  
         [0034]    a level-shift circuit  14  operative to raise the voltage to the buffer stage  16 , the circuit  14  shifting the voltage level to 12V from 5V;  
         [0035]    a logic network  15  driving the level-shift circuit  14  by appropriate outputs from the power supply.  
         [0036]    [0036]FIG. 4 also shows that the logic circuit  11  is input four signals, namely:  
         [0037]    OUT_COMP: this is the output from a comparator that is arranged to compare the value of the voltage V Cb  across the bootstrap capacitor; upon this voltage falling below a designed minimum, the comparator output is changed over, and is again changed over upon the voltage V Cb  exceeding a second set value “Hist”;  
         [0038]    PWM: this is the signal that drives the power device T 1  in the control loop;  
         [0039]    VREF_OK: this is a signal from a band-gap voltage regulator which will take a high value as the system supply voltage attains steady state; broadly in the circuit of this embodiment, this is an enable signal to the logic network  15  for a proper start-up of the logic circuit  11 ;  
         [0040]    MASK: this signal monitors the voltage at the terminal “Pow”; in practice, it detects the moment that the voltage V Pow  goes above a given value, i.e. that the bias of diode D, changes from reverse to forward.  
         [0041]    Let us see now the construction and operation of the logic circuit  11  in greater detail. As the signal OUT_COMP takes a high value, corresponding to the bootstrap voltage being below its designed minimum, the negation of PWM will generate a pulse through a delay block Delay 1  causing the negated output Q of a flip-flop FF to go low.  
         [0042]    This takes place over a sufficiently long time to ensure that the power device T 1  is off. Since the buffer stage  16  is to invert the output signal from the flip-flop FF, the power element T 2  will be conducting (ON). A reset signal is generated to the flip-flop FF through a second delay block Delay 2 , causing the power device T 2  to stop conducting.  
         [0043]    If before the resetting pulse comes in from the second delay block Delay 2  the potential V Pow  already is above the sensitivity threshold of the signal MASK, this signal is propagated to the flip-flop FF through a series of logic gates,  18  and  19 , and resets the logic network  15  such that the power element T 2  can be opened.  
         [0044]    It should be noted that this system maximizes the efficiency of charging the capacitor C b , because the time for closing the power element T 2  is not made longer than is strictly required for charging the capacitor by the provision of the two delay blocks, the network of logic gates connected to the blocks to generate the pulses, and the signal MASK.  
         [0045]    Should the power element T 2  be held on for a longer time than is required for the supply circuit to operate properly, i.e. until the voltage V Pow  is approximately 0V, then the node at potential “Pow” would see its voltage raised by the power element T 2  becoming current-saturated, I T2 =I Cb +I L . Under this condition, the capacitor C b  is no longer charged, and merely the output voltage from the supply circuit is discharged.  
         [0046]    [0046]FIG. 5 shows, by way of example only, waveforms plotted against time for a number of signals present in the logic network  15 . How the voltage V gate  at the gate terminal of the power element T 2  varies with the other signals is readily evinced from these plots.  
         [0047]    The first pulse of voltage V gate  goes high with a time delay over PWM, as due to the block Delayl. This voltage signal goes low again because it is assumed that the diode D 1  will change from a reverse bias to a direct bias. The second, shorter pulse of V gate  changes to low from high upon the voltage V Cb  at the bootstrap capacitor exceeding a threshold V Hist . Accordingly, OUT_COMP goes low again and resets the flip-flop FF.  
         [0048]    Briefly, the power supply circuit of this embodiment solves the technical problem and affords several advantages, foremost among which is the fact that the problems connected with charging the bootstrap capacitor C b  at any duty-cycle values of the system are now overcome.  
         [0049]    In addition, the system performance is improved by that the energy expended to charge the capacitor C b  is now minimized.  
         [0050]    A second embodiment of the logic circuit  11  associated with the second power element will now be described with reference to the example of FIG. 6. Compared to the previously described embodiment, this embodiment is no optimum as far as optimizing the system efficiency is concerned, yet does overcome the problem of discharging the bootstrap capacitor.  
         [0051]    Thus, the second embodiment further overcomes the problem of charging the capacitor C b  at values of the system duty cycle close to 100%.  
         [0052]    Compared to the previously described embodiment, the bootstrap capacitor C b  is not charged in an optimum manner because neither the signal MASK nor the delay blocks Delay 1  and Delay 2  for controlling the power element T 2  are utilized. This embodiment only uses two signals: OUT_COMP and OSC_scarica.  
         [0053]    These signals are each applied to a respective input of a logic gate  20 , preferably a NAND gate. The output of the logic gate  20  is connected directly to the input of the level shifter  14 .  
         [0054]    The signal OSC_scarica controls discharge of the sawtooth that, in switching power supplies of this type, is necessary in order to produce fixed-frequency PWM.  
         [0055]    As the signal OUT_COMP goes high, this corresponding to the bootstrap voltage being below its designed level, each pulse OSC_scarica will close the power element T 2  and hold it closed through the duration of the latter. Thus, the capacitor C b  is charged, and upon attaining steady state, OUT_COMP will go to a logic low. As a result, the following pulses OSC_scarica are disabled, thereby enabling the power element T 2  by short pulses only when required. Although efficiency is not optimized in this way, a significant step toward maximization is made.