Abstract:
A design method optimizes the dimensions (length and width) of power supply lines in a semiconductor integrated circuit. First, the power supply lines are analyzed to determine initial values for the lines. Then, a current-capacitance ratio of each of the power supply lines is calculated using the analysis results. Finally, a dimension of each of the poser supply lines is computed so that the corresponding current-capacitance ratio is within a predetermined range. The resulting power supply lines are as narrow as possible without causing a voltage drop violation or a current amount violation.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor integrated circuit, and more particularly, to a method and apparatus for designing the optimal power supply wiring in a semiconductor integrated circuit and to a recording medium storing a program for performing the method. 
     The optimization of the widths of power supply lines is important when laying out the power supply lines on an IC chip. Wide power supply lines occupy a large amount of area and thus limit the signal line area and the logic cell area. It is thus preferred that narrow power supply lines be used. However, the amount of current (current capacitance) that flows through a narrow power supply line is small. As a result, a current violation may occur. Current violation refers to a state in which wire breakage or deterioration (electromigration) may occur due to a large amount of current flowing through the line. Further, since the resistance of the line increases as the width of the line is narrowed, a voltage drop that exceeds a certain level (voltage drop violation) occurs. The voltage drop violation may cause the IC to function abnormally. Accordingly, there is a demand for a method that determines the minimum width of the power supply lines without causing a voltage drop violation or a current amount violation. 
     The optimal power supply line for an IC is one that does not have redundacy and has acceptable current capacitance and voltage drop levels. In a first prior art method for designing the optimal power supply line, the power supply network is analyzed to determine the assumed amount of current that will flow through the line. If the value of the assumed current amount exceeds the current capacitance of the line, the line width is increased from its originally designed width in order to increase the current capacitance. This avoids a current capacitance violation. The power supply network is then analyzed again to check whether the voltage drop is lower than a predetermined limit value. If there is a voltage drop violation, the width of certain lines are increased. Another check for violations is then made. These processes are repeated until the line width is optimized. 
     However, in the first prior art method, if the width of certain lines are increased to avoid a voltage drop violation when there is no current violation on any of the power supply lines, the increase in the width of the lines is not as effective as it should be for avoiding the voltage drop violation. The rate of current flowing through each power supply line changes by increasing the width of certain lines. As a result, current amount violations may occur at new locations. 
     In a second prior art method, the widths of all of the lines are increased to avoid voltage drop violations without changing the current rate. However, in this method, the widths of the lines having surplus current capacitance with respect to the actual current amount, or lines having redundant current capacitance are also increased. This increases redundancy and the amount of unnecessarily occupied area. 
     The second prior art method will now be described with reference to FIGS. 1A and 1B. FIG. 1A shows a power supply wiring having a node N 1  connected to a power supply E 1  and a node N 2  connected to a current supply I 1 . The nodes N 1  and N 2  are connected by power supply lines L 1 , L 2 , L 3 . The table of FIG. 1B shows the width and length of each of the lines L 1 -L 3 . A current of 2 mA flows through lines L 1 , L 2 , and a current of 3 mA flows through line L 3 . The potential at node N 2  is lower than the potential at node N 1  by 6 mV. In other words, the voltage drop value of the power supply wiring shown in FIG. 1A is 6 mV. 
     The voltage drop at node N 2  with respect to node N 1  may be changed to, for example, 4 mV or lower. Under such condition, if the width of line L 2  is doubled, the voltage drop value is 5 mV. If the width of line L 1  is doubled, the voltage drop is still no longer 4 mV or lower. 
     Line Li has a current capacitance of 4 mA. However, since a current of 2 mA flows through line L 1 , line L 1  has extra or redundant capacitance. Thus, an increase in the width of line L 1  further increases redundancy. This also increases the amount of current flowing through lines L 1 , L 2  and causes a current amount violation at line L 2 . 
     If the width of all of the lines L 1 , L 2 , L 3  are increased by 1.5 times, the voltage drop value at node N 2  is 4 mV. However, this line width increase would further increase the redundancy of lines L 1 , L 3  and the amount of unnecessarily occupied area on the IC chip. 
     When the width of line L 3  is increased by two times, the voltage drop value at node N 2  is 3.75 mV, which is an allowable voltage drop level. Thus, in the wiring of FIG. 1A, the most effective way to satisfy the voltage drop reference value is to increase the width of line L 3 . However, an actual IC is more complicated than the wiring of FIG.  1 A. Hence, determining the line which most effectively satisfies the voltage drop standard level when the width is changed is extremely difficult. 
     In other words, if the width of certain power supply lines are changed, the current amount at other lines changes. This may cause current amount violations at lines whose widths were not changed. Further, the change in voltage drop differs depending on the line whose width is changed. Thus, there may be cases in which power supply drop violations cannot be avoided. 
     If the width of every line is increased, the current amount rate between each line will not change but the width of lines already having redundancy will be further increased. Accordingly, such wire layout has many redundant portions. If every line width is decreased, the current amount rate between each line will not change, but the lines that do not have redundancy will also be narrowed. Accordingly, current amount violations are apt to occur in such a wire layout. 
     Additionally, in the prior art, although current amount violation and voltage drop violation were checked, reduction of redundancy in the wiring was difficult. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a method and apparatus for designing the optimal power supply wiring. 
     To achieve the above object, the present invention provides a design method for optimizing the dimensions of a plurality of power supply lines. The design method includes the steps of analyzing each of the power supply lines, computing a current-capacitance ratio of each of the power supply lines based on the analysis results, and computing a dimension of each of the power supply lines so that the corresponding current-capacitance ratio is within a predetermined range. 
     Another aspect of the present invention provides a design apparatus for optimizing the dimensions of a plurality of power supply lines. The apparatus includes a processor unit including an analyzing device for analyzing each of the plurality of power supply lines, a first computing device for computing a current-capacitance ratio of each of the power supply lines based on the analysis results, and a second computing device for computing a width of each of the power supply lines so that the corresponding current-capacitance ratio is within a predetermined range. 
     A further aspect of the present invention provides a computer readable medium for recording a program for optimizing the dimensions of a plurality of power supply lines. The program includes comprising the steps of analyzing each of the plurality of power supply lines, computing a current-capacitance ratio of each of the power supply lines based on the analysis results, and computing a dimension of each of the power supply lines so that the corresponding current-capacitance ratio is included in a predetermined range. 
     A further aspect of the present invention provides a method for optimally designing a plurality of power supply lines including the steps of checking a current value of each of the plurality of power supply lines, computing a current-capacitance ratio of each of the plurality of power supply lines from an allowable current value of the plurality of power supply lines and the corresponding current value, and computing a dimension of at least one of the plurality of power supply lines so that the corresponding current-capacitance ratio is within a predetermined range. 
     A further aspect of the present invention provides an apparatus for optimally designing a plurality of power supply lines. The apparatus includes a computation processing unit including a checking device for checking a current value of each of the plurality of power supply lines, a first computing device for computing a current-capacitance ratio of each of the plurality of power supply lines from an allowable current value and the corresponding current value, and a second computing device for computing a dimension of at least one of the plurality of power supply lines so that the corresponding current-capacitance ratio is within a predetermined range. 
     A further aspect of the present invention provides a computer readable recording medium having recorded thereon program code for optimally designing a plurality of power supply lines. The program code includes means for checking a current value of each of the plurality of power supply lines, means for computing a current-capacitance ratio of each of the power supply lines from an allowable current value and the corresponding current value, and means for computing the dimension of each of the plurality of power supply lines so that the corresponding current-capacitance ratio is within a predetermined range. 
     Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which: 
     FIG. 1A is a diagrammatic view showing a power supply circuit in order to describe the prior art power supply wiring design method; 
     FIG. 1B is a table showing the dimensions and electrical characteristics of the power supply circuit of FIG. 1A; 
     FIGS. 2A and 2B show a flowchart illustrating a power supply wiring design method according to the present invention; 
     FIG. 3 is a schematic block diagram showing a power supply wiring design apparatus according to the present invention; 
     FIG. 4A is a diagrammatic view showing a first example of a power supply circuit in order to describe the power supply wiring design method; 
     FIG. 4B is a table showing the dimensions and electrical characteristics of the power supply circuit of FIG. 4A; 
     FIG. 5 is a diagrammatic view showing a second example of a power supply circuit in order to describe the power supply wiring design method; 
     FIG. 6 is a diagrammatic view showing a third example of a power supply circuit network in order to describe the power supply wiring design method; 
     FIG. 7 is an equivalent circuit diagram of the power supply wiring pattern of FIG. 6; 
     FIG. 8 is a netlist of the power supply circuit network of FIG. 7; 
     FIG. 9 is a table showing the current-capacitance ratio and line width when the power supply circuit network of FIG. 7 is in an initial state; 
     FIG. 10 is a table showing the current-capacitance ratio and line width after the power supply circuit network of FIG. 7 undergoes a first process; 
     FIG. 11 is a netlist of the power supply circuit network of FIG. 7 after the first process is performed; 
     FIG. 12 is a table showing the current-capacitance ratio and line width after the power supply circuit network of FIG. 7 undergoes an optimization process; 
     FIG. 13 is a netlist of the power supply circuit network of FIG. 7 after the optimization process is performed; and 
     FIG. 14 is diagrammatic view showing a fourth example of a power supply circuit in order to describe the power supply wiring design method. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention will now be described with reference to FIGS. 2 to  14 . 
     As shown in FIG. 3, a power supply wiring design apparatus  11  is a CAD apparatus including a central processing unit (CPU)  12 , a memory  13 , a storage device  14 , a display device  15 , an input device  16 , a drive device  17 , and a bus  18  for connecting the devices  12 - 17  to one another. 
     The memory  13  stores programs and data used to design the power supply wiring and normally includes a cache memory, a system memory, and a display memory. The CPU  12  executes program instructions to design an IC power supply wiring in accordance with the program. 
     The display device  15  displays a layout picture and a parameter input picture. A cathode ray tube (CRT), a liquid crystal display (LCD), or a plasma display panel (PDP) may be used as the display device  15 . The input device  16  is used to input user commands and parameters. The input commands and parameters are sent to the CPU  12 . A keyboard and mouse device (not shown) may be used as the input device  16 . 
     The storage device  14  includes a magnetic disk device, an optical disk device, and a magneto-optical disk device. The storage device  14  stores power supply wiring design program data and first to seventh files  21 - 27 , shown in FIGS. 2A and 2B. In response to a user command, the CPU  12  transfers the program and data from the storage device  14  to the memory  13  and executes the program. The storage device  14  may also store a data base. 
     The drive device  17  reads information, including programs and data, stored on a recording medium  19 . The program and data recorded on the recording medium  19  are read by the drive device  17  and transferred to the storage device  14 , and then loaded into the memory  13 , as necessary. A computer readable recording medium, such as a magnetic tape (MT), a memory card, a floppy disk, an optical disk (CD-ROM, DVD-ROM), and a magneto-optical disk (MO, MD), may be used as the recording medium  19 . 
     With reference to FIGS. 2A and 2B, the first file  21  stores the design data of a semiconductor integrated circuit (IC) chip, the circuit layout of which has been designed by, for example, the CAD apparatus (not shown). The design data includes power supply network data (netlist). The CPU  12  shown in FIG. 3 receives the netlist from the first file  21  and designs the power supply wiring based on the netlist. 
     The second file  22  stores a current capacitance limit value. The CPU  12  checks for current violations in the power supply wiring based on the current capacitance limit value. 
     The third file  23  stores a minimum width value, which indicates the manufacturing limit. A power supply line having a width narrower than the manufacturing limit may be designed but cannot be manufactured. Hence, if the width of a power supply line computed through the power supply wiring design process is narrower than the limit, the CPU  12  uses the minimum width value instead. Accordingly, power supply lines having widths wide enough to allow manufacture are designed. 
     The fourth file  24  stores information of the power supply lines subject to optimization, and the fifth file  25  stores information of the power supply lines that are not subject to optimization. The power supply wiring includes lines having fixed widths, such as those defining standard cells. Therefore, power supply lines that are subject to optimization must be distinguished from those that are not subject to optimization. If all of the power supply lines are subject to optimization, the fourth and fifth files  24 ,  25  may be eliminated. 
     The sixth file  26  stores the current-capacitance ratio of each power supply line. The power supply lines are optimized when the current-capacitance ratio is included in a predetermined range. 
     The seventh file  27  stores the resulting netlist of the power supply network subsequent to optimization. 
     The first to seventh files  21 - 27  are distinguished from one another in accordance with the function of the stored data. Multiple types of data may be stored in a single file or a single type of data may be divided and stored in a multiple number of files. Among the files  21 - 27 , files storing temporary data may be provided in the memory  13  shown in FIG.  3 . 
     The power supply wiring design process includes a first process  31  for computing a candidate value of the line width, a second process  32  for checking voltage drop violation, and a third process  33  for correcting the line width candidate value. 
     In the first process  31 , the CPU  12  analyzes the power supply network based on the netlist stored in the first file  21 . The width of each power supply line is then changed in accordance with the analysis results so that the ratio of the current amount flowing through each line relative to the current capacitance is within a predetermined range. 
     The power supply wiring includes lines for providing the power along the surface of the IC chip substrate and via holes for providing the power in a direction perpendicular to the substrate. In this power supply wiring design process, the area of the via holes are handled in the same manner as the widths of the power supply lines. 
     The first process  31  includes steps S 41 -S 46 . 
     In step S 41 , the CPU  12  separates the power supply wiring included in the netlist into lines subject to optimization (hereafter referred to as subject lines) and lines that are not subject to optimization (hereafter referred to as non-subject lines). The widths of the subject lines are changed through the subsequent steps. 
     In step S 42 , the CPU  12  analyzes the power supply network. At step S 43 , the CPU  12  checks whether or not the width of each power supply line results in a current amount violation. If a current amount violation is found in the non-subject lines in step S 43 , the CPU  12  terminates the power supply wiring design process. In such case, the layout of the entire IC chip is redesigned since the widths of the non-subject lines are designated as fixed and are not to be changed. 
     If a current amount violation is not found in the non-subject lines in step S 43 , the CPU  12  proceeds to step S 44  and computes the current-capacitance ratio of each subject line as discussed below. The current-capacitance ratio refers to the ratio between the value of the current flowing through each subject line and the allowable current value (current capacitance) of the subject line. That is, current-capacitance ratio=current value/allowable current value. The CPU  12  stores the current-capacitance ratio of each line in the sixth file  26 . 
     In step S 45 , the CPU  12  checks whether the current-capacitance ratio of each subject line is within a predetermined range. If the current-capacitance ratio is not within the predetermined range, the CPU  12  proceeds to step S 46  and corrects the width of the lines having a current-capacitance ratio outside of the predetermined range. 
     The predetermined range is set in order to obtain the optimal power supply lines. The optimal power supply line refers to one that does not violate the current amount or voltage drop and has a width with small redundancy. A power supply line having small redundancy with respect to the current capacitance refers to one in which the current amount flowing through the wire is substantially the same as the current capacitance, that is, the current-capacitance ratio is one or lower, and close to one. If the current-capacitance ratio is greater than one, the current flowing through the line is more than the current capacitance. Such a line violates the allowable current amount. 
     For example, if the current-capacitance ratio is 0.5, the redundancy of that power supply line is two times greater with respect to the current capacitance of the line. Accordingly, the predetermined range is set to between one or lower and a value close to one (preferably about 0.8 to 1). 
     The width of each of the subject lines obtained in step S 46  puts the associated current-capacitance ratio in the predetermined range and optimizes the subject wires. The voltage drop value of each subject line is not taken into consideration in step S 46  so that the redundancy optimization is not hindered. 
     In step S 46 , if the obtained line width is narrower than the minimum width stored in the third file  23 , the value of the minimum width is employed as the width of that line. This prevents the design of a power supply wiring having lines with widths that cannot be manufactured. 
     After correcting the line width in step S 46 , the CPU  12  proceeds to step S 42  and analyzes the power supply network again. This is because new current amount violations may occur since the change in the line width varies the resistance of the subject lines and changes the current amount flowing through the subject lines. 
     The CPU  12  repeats steps S 42  to S 46  until there are no current amount violations in any of the power supply lines regardless of changes in the line widths. When there are no current amount violations and the current-capacitance ratio of each line is within the predetermined range, the CPU  12  proceeds to the second process  32  from the first process  31 . 
     The second process  32  checks whether or not there is a voltage drop violation in the power supply network. 
     At step S 47 , the CPU  12  analyzes the power supply network. At step S 48 , the CPU  12  determines whether or not the maximum voltage drop value obtained during the analysis exceeds a voltage drop limit value. If there is no voltage drop violation, the CPU  12  terminates the power supply wiring design process. In this case, the analyzed and optimized power supply network (netlist) is stored in the seventh file  27 . 
     If it is determined that there is a voltage drop violation in step S 48 , the CPU  12  proceeds to a third process  33 . 
     In the third process  33 , the CPU  12  increases the current capacitance of all of the subject wires based on the relationship between the maximum voltage drop value and the limit voltage drop value. The current capacitance of a power supply line may be increased by widening or thickening the line or by providing additional power supply lines. To increase the number of power supply lines, additional lines may be superimposed on different layers, be laid out on the same plane, or be both superimposed on different layers and laid out on the same plane. 
     In the third process  33 , the CPU  12  refers to each current-capacitance ratio stored in the sixth file  26 . The CPU  12  obtains the width of each subject line while maintaining the same current-capacitance ratio relationship between the subject lines. Otherwise, the CPU  12  obtains the width of each line so that the current-capacitance ratio of each subject line approaches a predetermined value (e.g., 1.0). 
     The CPU  12  recomputes the line widths using the computed values that were not employed in step S 46  (the value lower than the minimum width) in the third process  33 . The line widths employing the minimum width in step S 46  have redundancy since the computed value was not employed. Thus, the widening of the line to the minimum width would increase the redundancy of the line. To prevent an increase in redundancy, a new line width is obtained using the computed value that was not obtained in step S 46 . 
     If the newly computed value clears the minimum width condition, the CPU  12  updates the value of the line width with the computed value. If the computation value does not clear the minimum width condition (the computed value being smaller than the minimum width), the CPU  12  uses the minimum width as the new line width. This prevents the design of a power supply wiring having lines with widths that cannot be manufactured. 
     Referring now to FIGS. 1A-1B and  4 A- 4 B, the optimization performed through the power supply wiring design process will now be described using the example of the power supply wiring pattern shown in FIG.  1 A. 
     The power supply lines L 1 -L 3  each have a width, length, resistance, and current capacitance, as shown in FIG.  1 B. The voltage drop limit value is 4 mV. The CPU  12  first subjects all of the power supply lines L 1 , L 2 , L 3  to optimization and analyzes the power supply network of the power supply wiring pattern (step S 42 ). The current amounts 2 mA, 2 mA, 3 mA of the respective power supply lines L 1 , L 2 , L 3  are obtained during the analysis. Since the current amounts do not exceed the current capacitance of the associated power supply lines, there is no current amount violation. Thus, the CPU  12  proceeds to step S 44  and computes the current-capacitance ratio of each of the power supply lines L 1 -L 3  in the following manner. The current-capacitance ratio of line L 1 =current amount 2 mA/current capacitance 4 mA={fraction (1/2,)} the current-capacitance ratio of line L 2 =current amount 2 mA/current capacitance 2 mA=1, the current-capacitance ratio of line L 3 =current amount 3 mA current capacitance 4 mA=¾. 
     The CPU  12  then computes the line widths (step S 46 ) so that the associated current-capacitance ratio is included in the predetermined range (in this example, 0.8 to 1). The computation is performed for lines L 1  and L 3 , which current-capacitance ratio is out of the predetermined range. 
     To make the current-capacitance ratio take a value of  1 , the original line width is multiplied by the current-capacitance ratio. That is, the width of line L 1  is multiplied by 0.5, and the width of line L 3  is multiplied by 0.75. The resistance of each power supply line is inversely proportional to the line width. Thus, the resistance of line L 1  is 2Ω, and the resistance of line L 3  is 8/3Ω. Accordingly, the width, resistance, and current capacitance of new power supply lines L 1   a,  L 2 , L 3   a  are as follows: 
     line L 1   a;  width=1, resistance=2Ω, current capacitance=2 mA; 
     line L 2 ; width=1, resistance=2Ω, current capacitance=2 mA (no change); and 
     line L 3   a;  width=1.5, resistance=8/3Ω, current capacitance=3 mA. 
     When the power supply network is analyzed again under these conditions, the current-capacitance ratio of each of the power supply lines L 1   a,  L 2 , L 3   a  is computed as follows due to the change in the current amount flowing through the power supply lines: 
     current-capacitance ratio of line L 1   a  is 1 since the current capacitance is 2 mA and the current amount is 2 mA; 
     current-capacitance ratio of line L 2  is 1 since the current capacitance is 2 mA and the current amount is 2 mA; and 
     current-capacitance ratio of line L 3   a  is 1 since the current capacitance is 3 mA and the current amount is 3 mA. 
     Through the above process, the current-capacitance ratio of each of the power supply lines L 1   a,  L 2 , L 3   a  becomes included in the predetermined range (1 to 0.8). The image of the power supply lines L 1   a,  L 2 , L 3   a  is shown in FIG.  4 A. The broken lines show the original power supply lines L 1  and L 3 . The characteristics of the power supply lines L 1   a,  L 2 , L 3   a  are shown in FIG.  4 B. 
     In the second process  32 , the CPU  12  analyzes the modified power supply network formed by lines L 1   a,  L 2 , L 3   a.  The maximum voltage drop value of 8 mV at node N 2  is obtained through the analysis. Since the maximum value (8 mV) exceeds the voltage drop limit value (4 mV), the CPU  12  performs the third process. 
     In the third process  33 , the CPU  12  recomputes the widths of the power supply lines L 1   a,  L 2 , L 3   a  from the relationship between the voltage drop limit value (4 mV) and the voltage drop maximum value (8 mV). The new line width W 2  is obtained from the original line width W 1 , the voltage drop maximum value Vdrop, and the voltage drop limit value Vlimit using the equation W 2 =Vdrop/Vlimit×W 1 . 
     As a result, the new power supply lines have widths two times those of the power supply lines L 1   a,  L 2 , L 3   a.  FIG. 5 shows the power supply lines Ll b,  L 2   a,  L 3   b  having the new widths. The broken lines of FIG. 5 hypothetically show power supply lines that would be obtained when multiplying the widths of the original power supply lines L 1 , L 3  by two times. 
     The power supply lines L 1   b,  L 2   a,  L 3   b  obtained in this manner cause the voltage drop value at node N 2  to be 4 mV, which satisfies the voltage drop limit value condition. Further, the relative current-capacitance ratio relationship between the power supply lines is maintained. Thus, the current amount of lines L 1   b,  L 2   a  is 2 mA and the current amount of line L 3   b  is 3 mA. Thus, a current violation does not occur. 
     With reference to FIG. 6, the optimization performed through the power wiring design process will now be described using a second example of a power supply wiring pattern provided on an IC chip  51 . 
     The IC chip  51  has power supply lines L 11  to L 16  for providing the power to an internal circuit  60  via external terminals T 1 -T 4 . Although the internal circuit  60  requires multiple types of power supplies, only one type of power supply is shown. Among the power supply lines L 11 -L 16 , line L 12  is arranged on a different layer than the other lines L 11 , L 13 -L 16 . Line L 12  is shown with cross-hatchings extending in a direction differing from the cross-hatchings of the other lines L 11 , L 13 -L 16 . Via holes V 1 , V 2 , V 3  connect line L 12  to lines L 14 , L 15 , L 16 . The optimization process is performed on lines L 11  to L 16 . 
     In the second example, the current capacitance of each power supply line is obtained from the formula “line width×0.1e-3[A],” the voltage drop limit value is set at 0.5[V], and the minimum width condition of the power supply lines is one. 
     FIG. 7 shows an equivalent circuit diagram of the power supply wiring pattern of FIG.  6 . 
     In the power supply network of the IC chip  51 , each of the power supply lines L 11  to L 16  are divided at nodes n 1  to n 9  and represented as resistors connecting the associated nodes. The power supply line L 11  is represented by a resistor R_h 1  having a resistance between nodes n 1 , n 2  and a resistor R_h 2  having a resistance between nodes n 2 , n 3 . The power supply line L 12  is represented by resistors R_h 3 , R_h 4 . The power supply line L 13  is represented by resistors R_h 5 , R_h 6 . The power supply line L 14  is represented by resistors R_v 1 , R_v 2 . The power supply line L 15  is represented by resistors R_v 3 , R_v 4 . The power supply line L 16  is represented by resistors R_v 5 , R_v 6 . Current is supplied to the internal circuit  60  from current sources I 11 , I 12 , I 13 , I 14 , I 15  which are respectively connected to the nodes n 2 , n 4 , n 5 , n 6 , n 8  of the power supply lines L 12 , L 15 . 
     FIG. 8 is a netlist  52  corresponding to the power supply network of FIG.  7 . 
     The netlist  52  lists the resistor identifications (R_h 1  to R_h 6 ), the nodes associated with each resistor, the resistance R (unit [Ω]), the wire length L, the wire width W, the node associated with each of the current sources I 1 -I 5 , and the current value I (unit [A]). 
     In this example, all of the lines are subject to optimization. The CPU  12  analyzes the power supply network of the netlist  52  of FIG.  8  and obtains the current-capacitance ratio of each power supply line L 11 -L 16  (the current-capacitance ratio of the resistors R_h 1  to R_h 6  and R_v 1  to R_v 6  that correspond to the power supply lines L 11 -L 16 ). The results are shown in FIG.  9 . 
     The CPU  12  then changes the line widths so that the current-capacitance ratio of each of the power supply lines L 11 -L 16  is within the predetermined range. Afterward, the CPU  12  analyzes the power supply network one more time. 
     The predetermined range is 1 to 0.8. The width of a power supply line having a current-capacitance ratio outside the predetermined range is corrected in accordance with the current-capacitance ratio. The new wire width is obtained from the following equation: 
     
       
         new wire width=current-capacitance ratio×wire width. 
       
     
     The CPU  12  repeats the computation of the wire widths until the current/capacitance ratio of all of the lines is included in the range of 1 to 0.8 and obtains power supply lines L 11   a -L 16   a  having new widths. FIG. 10 shows an example of the width combination of the power supply lines L 11   a -L 16   a.  Other width combinations may also be obtained. 
     As shown in FIG. 10, all of the lines have a width greater than one and thus the minimum width condition is satisfied. The CPU  12  thus employs all of the computed values as the widths of the associated power supply lines L 11   a -L 16   a.    
     The netlist  52   a  subsequent to the first process is shown in FIG.  11 . The CPU  12  analyzes the power supply network using the netlist  52   a.  From the analysis, the CPU  12  confirms the location and value of the maximum voltage drop, which, in this case, is at node n 5  and has a value of about 0.9V. Since the voltage drop value at node n 5  is greater than the voltage drop limit value (0.5V), there is a voltage drop violation. The CPU  12  thus performs the third process. 
     To avoid a voltage drop violation at node n 5 , the CPU  12  increases the widths of all of the power supply lines L 11   a -L 16   a  in the third process. The current-capacitance ratio decreases when the line width is increased. The width of the lines that are to be widened are computed using, for example, the equation shown below so that the relative value of the current-capacitance ratio of each power supply line L 11   a L 16   a  approaches a predetermined value. The relative value of the current-capacitance ratio is set based on the current value of each of the power supply lines L 11   a -L 16   a.  FIG. 12 shows the relative ratio of each power supply line with respect to the current-capacitance ratio of line L 11   b.   
     
       
         new line width=voltage drop maximum value/voltage drop limit value/current-capacitance ratio. 
       
     
     The CPU  12  repeats the second process  32  and the third process  33  using the computed line widths until there are no voltage drop violations. The final current-capacitance ratio relative values of the power supply lines L 11   b -L 16   b  and the final line widths are shown in FIG.  12 . The final netlist is shown in FIG.  13 . The maximum voltage drop value subsequent to optimization is about 0.45V and taken at node n 5 . The voltage drop maximum value is smaller than the voltage drop limit value of 0.5V. Thus, voltage drop violations are avoided. 
     The preferred and illustrated embodiment has the advantages described below. 
     (1) In the first process  31 , the CPU  12  analyzes the power supply network based on the netlist stored in the first file  21 . The CPU  12  changes the line widths in accordance with the analysis results so that the ratio of the current amount relative to the current capacitance in each line is included in the predetermined ratio. As a result, the computed wire width is optimal with respect to the current amount. Accordingly, redundancy is minimized. 
     (2) In the second process  32 , the CPU  12  analyzes the power supply network and checks whether or not there are any voltage drop violations. In the third process  33 , the CPU  12  computes the line width based on the relationship between the maximum voltage drop value and the voltage drop limit value. This increases the current capacitance of all of the subject wires and causes the voltage drop of each line to be under the voltage drop limit. 
     (3) The power supply lines included in the netlist are divided into lines that are subject to optimization and lines that are not subject to optimization. The CPU  12  performs optimization on only the subject lines. Since the optimization is not performed on lines whose width cannot be changed, the time required for optimization is reduced. 
     (4) If the computed line width does not satisfy the minimum width condition, which is stored in the third file  23 , the value of the minimum width is employed as the line width. This prevents the designing of a power supply wiring that cannot be manufactured. 
     (5) For lines that employ the minimum width when correcting the line width in step S 46 , the CPU  12  computes a new line width based on the computed value that was not employed. This prevents an increase in the redundancy of the power supply wiring. 
     It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Particularly, it should be understood that the present invention may be embodied in the following forms. The preferred embodiment may be modified as described below. 
     The line width may be optimized for each resistor dividing the power supply lines L 11 -L 16  (e.g., the resistors R_h 1  and R_h 2  in the power supply line L 11 ). Among the power supply lines L 11 -L 16 , multiple power supply lines may be grouped together so that optimization is performed on only the lines of the group. 
     Certain power supply lines may be eliminated from the wires subject to optimization. For example, internal wiring data registered in the library data used for designing a standard cell (S/C) layout cannot be changed. Thus, the power supply lines corresponding to such data do not undergo optimization. The power supply lines can be classified into subject lines and non-subject lines in this manner when performing the first process. Subsequent to the first process  31 , an auxiliary line is added if an allowable current amount violation occurs in the non-subject lines. 
     In the power supply wiring pattern of FIG. 6, if the power supply line L 12  is not subject to optimization but violates the allowable current amount, an auxiliary line L 17  is added as shown in FIG. 14. A via hole V 4  connects the auxiliary line L 17  to the line L 12 . The added line ensures the optimization of the power supply lines. 
     In the preferred embodiment, optimization is performed on only the power supply lines L 11 -L 16 . However, the via holes V 1 -V 3  may also be subject to optimization. 
     If the line width computed in the third process  33  takes a value that is not allowed when designing the IC, the voltage drop limit value may be changed to a less severe value. 
     A maximum line width may be set so that the processing is temporarily interrupted when the computed value exceeds the value of the maximum line width. Power supply lines may be added and the processing may be started from the first process  31  again. 
     The present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.