Abstract:
A new and unique multiplication circuit solves the problems associated with digital multiplication circuits which operate on digital operands only. The multiplication circuit according to the present invention uses negative feedback in conjunction with an operational amplifier to maintain the output voltage of the operational amplifier at a level which depends on the logic level of the digital input datum applied to the gate of a field-effect transistor in the negative feedback loop. This unique multiplication circuit is capable of directly multiplying digital data with analog data.

Description:
BACKGROUND OF THE INVENTION 
     Recently, there have been concerns about limitations in the use of digital data processing equipment because of an exponential increase in the required investment in sophisticated digital equipment. 
     While analog data processing equipment may possess a cost advantage, there is a large volume of data conventionally stored in digital format. Therefore, a more practical solution is to use circuits capable of operating on both digital and analog data, in particular, a multiplier circuit capable of directly multiplying digital data with analog data. However, no such multiplication circuit has been taught previously. 
     FIELD OF THE INVENTION 
     The present invention relates to multiplication circuits, and more particularly, to multiplication circuits capable of directly multiplying digital data with analog data. 
     SUMMARY OF THE INVENTION 
     More specifically, the present invention solves the problems associated with conventional multipliers operating on digital data by directly multiplying analog data with digital data. 
     The multiplication circuit according to the present invention uses negative feedback in conjunction with an operational amplifier to maintain the output voltage of the operational amplifier at a level which depends on the logic level of the digital input datum applied to the gate of a field-effect transistor in the negative feedback loop, while applying the input analog signal to the non-inverting input of the operational amplifier. 
     Furthermore, the multiplication circuit according to the present invention uses a capacitor network to implement an adder capable of adding two or more analog signals. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit schematic illustrating an embodiment of the multiplication circuit relating to the present invention; 
     FIG. 2 is a block diagram illustrating the use of the multiplication circuit according to the present invention in a filter circuit with switchable Finite Impulse Response (F.I.R.) and Infinite Impulse Response (I.I.R.) characteristics; 
     FIG. 3 is a circuit schematic illustrating a sample-and-hold circuit to be used in conjunction with the multiplication circuit according to the present invention in a filter circuit; 
     FIG. 4 is a circuit schematic illustrating a capacitor network for adding analog signals, such as the outputs of several multiplication circuits realized according to the present invention; 
     FIG. 5 is a block diagram illustrating the use of multiplication circuits according to the present invention in a filter circuit with switchable F.I.R. and I.I.R. characteristics, utilizing a single adder; and 
     FIG. 6 is a schematic diagram illustrating a capacitor network for adding analog signals, such as the outputs of several multiplication circuits according to the present invention, in a filter circuit employing a single adder. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to the drawings, FIG. 1 illustrates a multiplication circuit M, having a pair of operational amplifiers Amp 3  and Amp 4 , and a pair of switching means such as field-effect transistors Tr 3  and Tr 4 . An analog input AX feeds the non-inverting input of Amp 3 . The drain and gate of Tr 3  are connected to the output of Amp 3  and the digital input datum B, respectively. The source of Tr 3  has a path to ground through the series connection of capacitors C 3  and C 4  forming a voltage divider means. The voltage at the junction of C 3  and C 4  is fed back to the inverting input of Amp 3 . 
     Tr 3  conducts when the digital input datum B is at a logic high level. The conduction of Tr 3  completes the negative feedback path around Amp 3 , forcing the voltage at the inverting input of Amp 3  (the voltage across capacitor C 4 ) to be substantially equal to the input voltage AX. This, in turn, results in the source voltage of Tr 3  to be substantially equal to {AX (C 3  -C 4 )/C 3  }. 
     The non-inverting input of Amp 4  is grounded. The output and inverting input of Amp 4  are connected to the source and drain of Tr 4 , respectively. The drain of Tr 4  is further connected to the source of Tr 3 . An inverter INV inverts the digital input datum B, and controls the gate of Tr 4  with this inverted signal. Therefore, Tr 4  conducts when input B is at a logic low level. The conduction of Tr 4  completes the negative feedback loop around Amp 4 , thus forcing the output voltage of Amp 4  to substantially zero volts (ground voltage). 
     The source of Tr 3  and the drain of Tr 4  are coupled to an output OUT through capacitor C 5 . The voltage at OUT is weighted by the capacitance of so that when input B is at a logic high level, the output of the circuit is determined by: 
     
         {(c.sub.3 -c.sub.4)/C.sub.3 }C.sub.cp AX, 
    
     where C cp  is a weight determined by capacitive coupling and is a function of the capacitance of C 5 . Conversely, a logic low level at input B results in an output substantially equal to zero. 
     FIG. 4 is the circuit diagram of a capacitive coupling network including a number of capacitors connected to a common node V s . In the particular implementation illustrated in FIG. 4, there are eight capacitors, C 51  to C 58 . Input voltages V 1  to V 8  are applied to capacitors C 51  -C 58 , respectively, resulting in a weighted output voltage V 8 , defined by: 
     
         v.sub.8 =(C.sub.51 V.sub.1 +C.sub.52 V.sub.2 + . . . +C.sub.58 V.sub.8)/(C.sub.1 +C.sub.2 + . . . +C.sub.8). 
    
     By applying each bit of an input digital operand to input B of a plurality of circuits such as that illustrated in FIG. 1, and defining {(C 3  -C 4 )/C 3}  } C cp  as 2 n , where n is the number of bits in the digital operand, direct multiplication of the analog input voltage AX and the digital input quantity is achieved. 
     The multiplication circuit described above is suitable for various applications, such as the filter circuit illustrated in FIG. 2. Each of the blocks labeled M 11  to M 18  and M 21  to M 28  in FIG. 2 is composed of a multiplication circuit such as the circuit illustrated in FIG. 1. 
     The filter in FIG. 2 has two calculation circuits, MC1 and MC2, respectively, each performing both addition and multiplication. The first calculation circuit, MC1, comprises a number of sample-and-hold circuits, H 11  to H 18 , connected in tandem. The output of each sample-and-hold circuit H 1k  is input to a multiplication circuit M 1k . Similarly, the second calculation circuit, MC2, comprises a number of sample-and-hold circuits, H 21   to H 28 , connected in tandem. The output of each sample-and-hold circuit H 2k  is input to a multiplication circuit M 2k . 
     An input datum Din is fed to the first sample-and-hold circuit H 11 , and is sequentially transferred to sample-and-hold circuits H 12  to H 18  through the application of succeeding clock pulses. This sequential datum is represented by X(t-k). Predetermined quantities a 1  to a 8  are applied to the remaining inputs of multiplication circuits M 11  to M 18  prior to the application of the clock pulses. Thus, the output of each multiplication circuit M 1k  is given by: 
     
         m.sub.1k =a.sub.k ×X(t-k). 
    
     The outputs of multiplication circuits M 1k  and M 1 (k+1) are added by an adder circuit A 1k , and the result of the addition is input to the succeeding adder circuit, A 1 (k+1). Thus, adder circuit A 17  calculates a sum of the outputs of all the multiplying circuits in calculation circuit MC1, defined by: ##EQU1## 
     Depending on the setting of switch SW, either the output of adder A 17  or the output of sample-and-hold circuit H 18  is input to the second calculation circuit MC2, and is sequentially transferred to sample-and-hold circuits H 21  to H 28  through succeeding clock pulses. This sequential datum is represented by Y(t-k). Predetermined quantities b 1  to b 8  are applied to the remaining inputs of multiplication circuits M 21  to M 28  prior to the application of the clock pulses. Thus, the output of each multiplication circuit M 2k  is defined by: 
     
         m.sub.2k =b.sub.k ×Y(t-k). 
    
     The outputs of multiplication circuits M 2k  and M 2 (k+1) are added by an adder circuit A 2k , and the sum is input to the following adder circuit A 2 (k-1). Thus, adder circuit A 27  calculates a sum of the outputs of all the multiplication circuits in calculation circuit MC2, defined by: ##EQU2## 
     The output of adder A 21  is input to adder A 17  in calculation circuit MC1. Thus, the output of adder A 17  is the sum of the multiplication results calculated by MC1 and MC2. 
     The circuit illustrated in FIG. 2 can realize a filter with either F.I.R. or I.I.R. characteristics, depending on the position of switch SW. When switch SW is set so as to connect the output of H 18  to the input of H 21 , D m  is equal to X(t-8). In this case, the output of calculation circuit MC2 is defined by: ##EQU3## Expressing b k  as a.sub.(k+8), the sum of the outputs of calculation circuits MC1 and MC2 is produced by the output of A 17 , defined by: ##EQU4## Thus, the circuit realizes an F.I.R. filter. 
     Conversely, when switch SW is set so as to connect the output of A 17  to the input of H 21 , D m  is defined by: ##EQU5## In this case, the circuit realizes an I.I.R. filter because Y(t) is equal to D m . 
     Therefore, a filter circuit which has the characteristics of either an F.I.R. filter or an I.I.R. filter depending on the position of a single switch can be realized by using multiplication circuits according to the present invention. 
     Using the multiplication circuits described above in conjunction with sample-and-hold circuits, high-speed filters with a relatively large number of stages can be realized for a wide variety of applications. 
     FIG. 3 illustrates a sample-and-hold circuit H jk , having a pair of operational amplifiers Amp 1  and Amp 2 , and a pair of field-effect transistors Tr 1  and Tr 2 . An input voltage d in  is connected to the non-inverting input of Amp 1 . The output of Amp 1  is connected to the drain of Tr 1 . The source of Tr 1  is coupled to ground through a capacitor C 1 . The source of Tr 1  is further connected to the inverting input of Amp 1 . 
     A clock source CLK 0  drives the gate of Tr 1 , such that Tr 1  conducts when CLK 0  is at a logic high level. Thus, a logic high level at the CLK 0  input completes the negative feedback path around Amp 1 , forcing the voltage across C 1  to be substantially equal to d in . 
     The network comprising amplifier Amp 2 , transistor Tr 2 , and capacitor C 2  forms a second stage of the sample-and-hold circuit. The output of Amp 2  is connected to the drain of Tr 2 . The source of Tr 2  is coupled to ground through a capacitor C 2 . The source of Tr 2  is further connected to the inverting input of Amp 2 . A clock source CLK 1  drives the gate of Tr 2 , such that Tr 2  conducts when CLK 1  is at a logic high level. Clock signals CLK 0  and CLK 1  are complementary logic signals. 
     Thus, when Tr 2  conducts, the voltage across C 2  is substantially equal to the voltage developed across C 1  when there was a logic high level present at the CLK 0  input. Capacitor C 2  stores electric charge until its terminal voltage becomes substantially equal to the input voltage d in . Therefore, after a full clock cycle, the output voltage d out  is substantially equal to the input voltage d in . The timing between clock signals CLK 0  and CLK 1  ensures that there is no influence on the following stage during the charging of C 2 . 
     The adders A jk  (A 11  to A 17  and A 21  to A 27  in FIG. 2) can be realized by a capacitive weighting network, as illustrated in FIG. 4. These adders can be designed so as to have either two or three inputs. 
     The output signal D out  of the filter circuit in FIG. 2 is the output of a sample-and-hold block H out . 
     FIG. 5 illustrates a second filter circuit which uses a single adder A t  rather than adders A jk . The output of each multiplication circuit M jk , denoted as m jk  in FIG. 5, drives a capacitor C jk  in a capacitor weighting network illustrated in FIG. 6. The second terminal of capacitor C jk  is connected to a common node V a . Adder A t  performs a weighted addition by using the capacitor network illustrated in FIG. 6. The steps of the calculation are similar to those of the circuit in FIG. 4.