Abstract:
In a video signal compression method, compression ratio control signals (K) and a previous sum (Csum) are added (AD 1 ) to generate a new sum, compression control signals (DC, en) are logically generated (CP, CNT) in dependence upon the previous sum (Csum) and the compression ratio control signals (K), and video signals are compressed (D) in dependence upon the compression control signals (DC, en) to generate compressed video signals.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to adaptive compression of video signals for, e.g., PIP or double window display. 
     Field of the Invention 
     Description of the Related Art 
     UK Patent Application GB-A-2,182,522, corresponding to U.S. Pat. No. 4,717,951, discloses an adaptive filtering system. A picture-in-picture television receiver, for which the viewer may change the size of the inset image, includes an adaptive anti-aliasing filter. The filter includes a variable delay element and an adder. Signals are applied to one input port of the adder and to the delay element. The signals provided by the delay element are applied to a second input port of the adder. The delay element provides time delays which may be expressed by the equation T=K 1 τ+PK 2 τ, where τ is a fixed amount of time, K 1  and K 2  are constants, and P is a variable. The frequency response characteristic of the filter is changed by a selection signal that changes the value of P. 
     SUMMARY OF THE INVENTION 
     It is, inter alia, an object of the invention to provide an adaptive filter having a simple control. To this end, a first aspect of the invention provides a method and device for video signal compression. A second aspect of the invention provides a display apparatus including such a video signal compression device. 
     In a video signal compression method in accordance with a primary aspect of this invention, compression ratio control signals and a previous sum are added to generate a new sum, compression control signals are logically generated in dependence upon the previous sum and the compression ratio control signals, and video signals are compressed in dependence upon the compression control signals to generate compressed video signals. 
     These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     In the drawing: 
     FIG. 1 shows a compression circuit in accordance with the invention; and 
     FIG. 2 shows a display apparatus comprising such a compression circuit. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     For a PIP (picture-in-picture) mode called linear zoom a digital filter is needed that compresses a video picture to a smaller size. The compression must be done in horizontal as well as in the vertical direction. The main issue of linear zoom is that the reduction, factor can be different for each new picture. For this problem a solution was found which can be applied to the horizontal and vertical compression filters. The basic scheme is shown in FIG.  1 . 
     FIG. 1, K is a number between 0 and M, where M is the number of possible reduction factors. If it is desired to zoom from 1 to 100% in 100 steps, M should be 100. The reduction factor is K/M. In the linear zoom application, K changes each field, or each two or more fields. In PIP applications, the very common reduction factors ½, ¼, ⅓ and ⅛ can be implemented using this circuit by choosing M=96 and K=48, 24, 32 and 12, respectively. 
     Suppose the circuit shown in FIG. 1 is used for a horizontal reduction. In the control path C, at the start of a line (indicated by the signal startlin), register REG A is reset to zero. For K&gt;0, the enable signal en at the output of the comparator CP will then be 1 as K exceeds the output signal Csum of the register REG A. At each following clock cycle, K is added to Csum by a modulo M adder AD 1 , and the modulo M value is stored in register REG A. If Csum is smaller than K, the enable signal en becomes 1, and otherwise it becomes 0. The result is a regular sequence of 1&#39;s and 0&#39;s at the enable output en. This is illustrated in the following tables. 
     Compression ratio is ¼, so that K/M=24/96 
     
       
         
               
               
               
             
               
               
               
             
           
               
                   
               
               
                 Output register REG A 
                 Output Modulo 
                 Output comparator CP 
               
               
                 Csum 
                 M adder AD1 
                 enable signal en 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 0 
                 24 + 0 = 24 
                 24 &gt; 0 = 1 
               
               
                 24 
                 24 + 24 = 48 
                 24 &gt; 24 = 0 
               
               
                 48 
                 24 + 48 = 72 
                 24 &gt; 48 = 0 
               
               
                 72 
                 24 + 72 = 96 → 0 
                 24 &gt; 72 = 0 
               
               
                 0 
                 24 + 0 = 24 
                 24 &gt; 0 = 1 
               
               
                   
               
             
          
         
       
     
     As a result of the enable signal en having a 1 following three 0&#39;s, each time, four input pixels are combined into one output pixel, so as to provide the compression ratio of ¼. 
     Compression ratio is ⅔, so that K/M=64/96 
     
       
         
               
               
               
             
               
               
               
             
           
               
                   
               
               
                 Output register REG A 
                 Output Modulo 
                 Output comparator CP 
               
               
                 CSUM 
                 M adder AD1 
                 enable signal en 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 0 
                 64 + 0 = 64 
                 64 &gt; 0 = 1 
               
               
                 64 
                 64 + 64 = 128 → 32 
                 64 &gt; 64 = 0 
               
               
                 32 
                 64 + 32 = 96 → 0 
                 64 &gt; 32 = 1 
               
               
                 0 
                 64 + O = 64 
                 64 &gt; 0 = 1 
               
               
                   
               
             
          
         
       
     
     As a result, alternatingly, two input pixels are combined into one output pixel (enable signal en having a 1 following one 0) and an input pixel is just passed (enable signal en having a 1 following no 0&#39;s), so as to provide the compression ratio of ⅔. 
     A counter CNT counts the number of zero&#39;s, and applies the result increased by one (hence, 4 in the first example and alternatingly 2 and 1 in the second example) as a division control signal DC to a controllable divider DIV in the data path D of the circuit. 
     In the data path D of the circuit, data samples DS, representing pixels of a line, arrive at the data input each clock cycle. The enable signal en is used to reset register REG B at zero, to enable register REG C, and to indicate a valid sample at the output (signal out-val at the output of the delay DL). Each clock cycle, if the enable signal en is 0, the adder AD 2  adds the value of the new input data sample DS data to the output signal Dsum of the register REG B, and the sum is stored in the register REG B. If enable is 1, the sum is divided by the controllable divider DIV and stored into the register REG C. 
     The circuit can be used for vertical reduction as well. Then, the register REG B is a line memory, and the register REG A is enabled once per line. 
     The display apparatus of FIG. 2 has a first or main channel input CH 1  and a second on PIP channel input CH 2 . The first channel input CH 1  is coupled to an input of a first horizontal reduction circuit HR 1  of the type shown in FIG.  1 . The second channel input CH 2  is coupled to an input of a second horizontal reduction circuit HR 2  which is also of the type shown in FIG.  1 . An output of the second horizontal reduction circuit HR 2  is coupled to an input of a vertical reduction circuit VR which is of the type shown in FIG. 1 with the above-mentioned modifications. In a double window display mode, a switch SW 1  alternatingly couples an input of an output processor OP to an output of the first horizontal reduction circuit HR 1  or an output of the vertical reduction circuit VR. In a PIP mode, the switch SW 1  couples the input of an output processor OP to the output of the vertical reduction circuit VR. A switch SW 2  couples an input of a display driver DD to the first or main channel input CH 1  or an output of the output processor OP. In a single display mode, the switch SW 2  couples the input of the display driver DD to the first or main channel input CH 1 . In a PIP mode, the switch SW 2  alternates between its two positions. In a double window mode, the switch SW 2  couples the input of the display driver DD to the output of the output processor OP. An output of the display driver DD is coupled to a display DP. 
     It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of other elements or steps than those listed in a claim. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In device claims enumerating several means, several of these means can be embodied by one and the same item of hardware.