Abstract:
A radio device includes phase discriminator with a phase locked loop. Where when there is no phase locking, the output voltage of the phase discriminator remains constant, which provides considerable gain for loop. When there is phase locking, the phase discriminator produces an error proportional to the phase difference. An output of the phase discriminator has a constant amplitude with an input signal and a reference signal have different frequencies.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a radio device comprising a frequency synthesizer that notably includes a phase discriminator for comparing the phase of a first signal with the phase of a second signal, the phase discriminator being formed by a first sequential circuit for producing output signals that represent the phase difference between said first and second signals. 
     The invention also relates to such a discriminator and a process for comparing the various phase levels of two signals. 
     BACKGROUND OF THE INVENTION 
     Such devices are well known and find many applications, notably in the field of portable telephones that use a great many frequency channels determined by the synthesizer. It will be recollected that a synthesizer is formed, in essence, by a voltage-controlled variable oscillator slaved to a reference frequency after a frequency division that ultimately determines the output frequency of the synthesizer. 
     When the device is in the stand-by mode, it is more or less periodically to be connected to the network and, for reasons of saving energy, it is desirable for the synthesizer to be longest possible in the state of rest, that is, that this implies that the variable oscillator is synchronized with the reference frequency in the fastest possible way. One of the elements that enable to obtain a fast synchronization is the phase discriminator. In patent document EP 0 500 014 the description of such a discriminator can be found. 
     If this known discriminator offers good indications as regards the phase differences between −π and +π, these indications are no longer sufficient for greater phase differences, thus for signals having different frequencies. 
     SUMMARY OF THE INVENTION 
     The invention proposes a device in which the discriminator features a good characteristic of the phase level, so as to notably obtain a fast synchronization of the variable oscillator. 
     Therefore, such a device is characterized in that the discriminator includes a second sequential circuit for producing a constant signal when said first and second signals have different frequencies. 
     Thus, thanks to the invention, when the frequencies of the signals are different, the DC signal whose value is equal to a maximum permits the rapid correction of the frequency of the voltage-controlled oscillator to obtain the synchronization of the oscillator in the fastest way. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other aspects of the invention are apparent from and will be elucidated, by way of non-limitative example, with reference to the embodiment(s) described hereinafter. 
     In the drawings: 
     FIG. 1 shows a device in accordance with the invention, 
     FIG. 2 shows the diagram of a synthesizer forming part of the device shown in FIG. 1, 
     FIG. 3 shows the diagram of a discriminator that forms part of the synthesizer shown in FIG. 2, 
     FIG. 4 is a first timing diagram intended for the explanation of the discriminator shown in FIG. 3, 
     FIG. 5 is a second timing diagram intended for the explanation of the discriminator shown in FIG. 3, and 
     FIG. 6 represents the discriminator response curve. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     In FIG. 1 is represented a radio device in accordance with the invention. It is formed by a transmission circuit  1  and a receiving circuit  2  coupled to an antenna  5  via a duplexer  8 . The transmission circuit  1  is formed by a microphone  11 , followed by an analog/digital converter  12  which produces the speech signals to be transmitted to a modulation system  15 . The receiving circuit  2  is formed by a demodulation system  20 , followed by a decoder  25  and a loudspeaker  27 . The receiving and transmission systems are controlled via the frequency channel by means of a synthesizer  30 . 
     FIG. 2 shows the structure of the synthesizer  30  of a conventional type. It is formed by a voltage-controlled oscillator  35  whose signals are frequency-divided by a frequency divider  37 . The frequency division rate determines the frequency channel on which the transport will take place. The signal E 1 , which is the output signal of the divider  37 , is compared by a phase discriminator  40  with a signal E 2 , which is the output signal of a quartz crystal oscillator  39 . The output signal S of this discriminator is applied to the voltage-controlled oscillator  35  via a control filter  42 . 
     FIG. 3 shows in detail the phase discriminator according to the invention. 
     The signals E 1  and E 2  are applied to the clock inputs of two D-type flip-flops referenced  51  and  52 , respectively. These flip-flops permanently receive a signal having the logic “1” value on their input D, whereas the input R receives the output signal of a NAND gate  55 . The output signals Q 1  and Q 2  of these flip-flops  51  and  52  are applied not only to the inputs of the gate  55 , but also to the inputs J of the flip-flops  61  and  62  of the type JK, to the inputs K of the flip-flops  61  and  62  and to the first inputs of the OR gates  71  and  72 . The outputs of these flip-flops  61  and  62  are applied to the inputs of a circuit known by the name of current pump  75  of a conventional type. The second inputs of these gates  71  and  72  are connected to the outputs of the latter flip-flops  61  and  62 . The clock inputs of the flip-flops  61  and  62  receive the respective signals E 1  and E 2  and their output Q produces the signals QQ 1  and QQ 2 , respectively. 
     In brief, this discriminator comprises a first sequential circuit formed by the flip-flops  51  and  52  which has the structure of known phase discriminators, a second sequential circuit formed by the flip-flops  61  and  62  and a coupling circuit mainly formed by the OR gates  71  and  72 , which coupling circuit enables to feed control signals to the current pump from these sequential circuits. 
     The operation of the discriminator is explained for a first embodiment with the aid of FIG.  4 . This mode relates to the case where the signals E 1  and E 2  have the same frequency. One starts from instant t 0  and considers that the signals Q 1  and Q 2  on the outputs of the flip-flops are in the logic “0” state. At the instant t 1  the low-to-high transition of the signal E 1  occurs to which the flip-flops are sensitive, so that the flip-flop  51  transfers the “1” value, which was present on its input D, to its output Q. The signal Q 1  then assumes the “1” value. At the instant t 2  it is the rising edge of the signal E 2  that occurs, which makes that the signal Q 2  on the output of the flip-flop  52  assumes the “1” value. But this state changes because of the fact that an active signal coming from the gate  55  having values “0” is applied to the inputs R of the flip-flops  51  and  52 . Thus after the instant t 2 , the signals Q 1  and Q 2  assume the “0” value. 
     As regards the flip-flops  61  and  62 , it should be observed that before the active transitions of the signal E 1 , the signal Q 1  has the “0” value and the signal Q 2  the “0” value, which makes that the signal QQ 1  retains its value. It should also be observed that before the active transitions of the signal E 2 , the signal Q 1  has the “1” value and the signal Q 2  the “0” value, which makes that the signal QQ 2  assumes the “0” value. Thus, the OR gates  71  and  72  are open and the operation of the discriminator remains that of the prior-art discriminators. 
     The operation of the discriminator according to another embodiment, for which the signals have different frequencies, is explained with the aid of FIG.  5 . Thus in this Figure, between a first transition of the signal E 1  that occurs at instant t 10  and a second transition of this same signal, there are two transitions of the signal E 2  which appear at the instants t 11  and t 12 . As the transition of E 2  occurring at the instant t 11  comes later than at the instant t 10 , one is thus certain that at the instant t 12  the signals Q 1  and Q 2  have the “0” value. Thus, after this instant t 12  one has Q 2 =“1” and Q 1 =“0”, so that at instant t 13 , where an active transition of E 1  appears, Q 1  assumes the “1” value and soon loses it due to the output signal of the gate  55 . After this instant t 13 , the signal QQ 1  assumes the “0” value. 
     After that, at instant t 14 , the active edge of the signal E 2  occurs, which edge will influence the flip-flops  52  and  62 , the signal Q 2  will change from the “0” value to the “1” value and because of this fact the signal QQ 2  will have the “1” value. 
     At the instant t 15  another active edge of the signal E 2  occurs, the signal Q 2  retains its “1” value, whereas the signal QQ 2  keeps its “1” value. 
     At the instant t 16 , an active edge of the signal E 1  occurs this time. Thus, the signal Q 1  assumes the “1” value and loses it soon because the NAND gate is rendered conductive by the signal Q 2 . Signal QQ 1  retains the “0” value acquired during the instant t 13 , because on its inputs J and K it receives the signals “0” and “0”, respectively. 
     At the instant t 17  a rising edge of the signal E 2  occurs. It is admitted that this edge occurs after the transient rise of the signal Q 1 , so that at the inputs J and K of the flip-flop  62  there are the signals “0” and “0”, thus the flip-flop keeps its state prior to the instant t 17 . At the instant t 18 , which is the instant at which a rising edge of the signal E 2  occurs, the signal QQ 2  still keeps the “1” value. The same state remains for this signal at the instant t 19  where there is still a rising edge of the signal E 2 . Before the instant t 20 , the signals at the inputs J and K of the flip-flop  62  had the respective values “0” and “1”, which keeps the signal QQ 1  at “0”. 
     Thus, it is taken into account that when the frequencies of the signals are different, the signals QQ 1  and QQ 2  remain constant, which makes it possible to have an error signal that causes the oscillator  35  (FIG. 2) to be synchronized fast. This is diagrammatically shown in FIG. 6, which shows the response of the discriminator of FIG. 3, that is, the variation of the signal S as a function of the phase error and/or frequency error of the signals E 1  &amp; E 2  Φ(E 1 , E 2 ). It will be noted that there is a hysteresis effect involved. Actually, if the frequencies are close together, the signals QQ 1  and QQ 2  do not change value. For making this obvious, FIG. 5 shows that the edges  18  and  19  no longer occur, the signals Q 1  and Q 2  thus keep the “0” value (dotted curve) which provides that neither of the flip-flops  61  and  62  changes state. When phase coincidence is reached, the solid-line curve of FIG. 6 is described. 
     It is possible to realize the circuits of the invention in a different manner. For example, by using logic circuits coupled to memory elements.