Abstract:
An nonvolatile memory device having improved endurance is comprised of an array of nonvolatile memory cells arranged in rows and columns. Each memory cell of each row is connected to a word line and a source select line, and each memory cell of each column connected to a first bit line and a second bit line. Each memory cell is composed of a first transistor and second transistor. The first and second transistors have control gate connected to the word line receive a word line voltage, a source connected the source select line to receive a source line voltage, and a floating gate onto which an electronic charge is placed representing a data bit stored within the nonvolatile memory device. The first transistor has a drain connected the first bit line to receive a first bit line voltage and the second transistor a drain connected to the second bit line to receive a second bit line voltage. Each memory cell has a floating gate connector joining the floating gate of the second transistor to the floating gate of the second transistor. The nonvolatile memory device has a voltage controller programs the each memory cell by programming the first transistor and reading the second transistor. Alternately the voltage controller employs a two step programming method by programming the first transistor for a short period of time and then programming the second transistor for second short period of time and then reading from the second transistor.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This invention relates generally to a class of non-volatile memory devices referred to as flash electrically erasable programmable read-only memory (flash EEPROM). More particularly, this invention relates two-transistor flash EEPROM cells and arrays. Even more particularly this invention relates to methods and means to read, program, and erase digital data from a two-transistor flash EEPROM cell to improve endurance of the flash EEPROM cell.  
           [0003]    2. Description of Related Art  
           [0004]    The structure and application of the flash EEPROM is well known in the art and illustrated in “Technical Comparison of Floating Gate Reprogrammable Nonvolatile Memories,” (SST White Paper) staff, Silicon Storage Technology, Inc., November, 2001 Technical Paper, found May 7, 2002 www.sst.com. The Flash EEPROM provides the density advantages of an erasable programmable read-only memory (EPROM) that employs ultraviolet light to eliminate the programming with the speed of a standard EEPROM. FIG. 1 a  illustrates a cross-sectional view of a stacked gate flash EEPROM cell of the prior art. The stacked gate flash EEPROM cell is formed within a p-type substrate  10 . An n+ drain region  12  and an n+ source region  14  are formed within the p-type substrate  10 .  
           [0005]    A relatively thin gate dielectric  16  is deposited on the surface of the p-type substrate  10 . The thin gate dielectric  16  is also referred to as a tunneling oxide. A poly-crystalline silicon floating gate  18  is formed on the surface of the gate dielectric  16  above the channel region  20  between the drain region  12  and source region  14 . An interpoly dielectric layer  22  is placed on the floating gate  18  to separate the floating gate  18  from a second layer of poly-crystalline silicon that forms a control gate  24 .  
           [0006]    The source region  14  is connected to a source voltage generator through the source line  30 . The control gate  28  is connected through the word line  28  to the word line voltage generator. And the drain region  12  is connected through the bit line  24  to the bit line voltage generator.  
           [0007]    According to conventional operation, the flash EEPROM cell is programmed by setting the word line voltage generator to a relatively high voltage (on the order of 10V). The bit line voltage generator is set to a moderately high voltage (on the order of 5V), while the source line voltage generator is set to the ground reference potential (0V).  
           [0008]    With the voltages as described above, hot electrons will be produced in the channel  20  near the drain region  12 . These hot electrons will have sufficient energy to be accelerated across the gate dielectric  16  and trapped on the floating gate  18 . The trapped hot electrons will cause the threshold voltage of the field effect transistor (FET) that is formed by the flash EEPROM cell to be increased by three to five volts. This change in threshold voltage by the trapped hot electrons causes the cell to be programmed.  
           [0009]    To erase the flash EEPROM cell a moderately high positive voltage (on the order of 5V) is generated by the source line voltage generator. Concurrently, the word line voltage generator is set to a relatively large negative voltage (on the order of −10V). The substrate  10  is set to the ground reference potential. The bit line voltage generator is usually disconnected from the bit line  26  to allow the drain region  12  to float. Under these conditions there is a large electric field developed across the tunneling oxide  16  in the source region  14 . This field causes the electrons trapped in the floating gate  18  to flow to portion of the floating gate  18  that overlaps the source region  16 . The electrons are then extracted to the source region  14  by the Fowler-Nordheim tunneling.  
           [0010]    The flash EEPROM functions based on the electronic charge stored on the floating gate  18  sets the memory transistor to a logical “1” or “0”. Depending on whether the memory structure is an enhancement or depletion transistor when the floating gate is neutral or contains electrons (negative charge), the memory cell will or will not conduct during read. When the floating gate  18  is neutral or has an absence of negative charge, the memory cell will conduct during read. The conducting or nonconducting state is output as the appropriate logical level. In the memory cell as shown the word line voltage generator and the control gate  28  is set to the voltage level of the power supply voltage source. The substrate  10  and the source line voltage generator and thus the source  14  are set to the level of the ground reference voltage. The bit line voltage generator and the drain  12  are set to a small voltage level sufficient to cause a small current to conduct in the bit line  26 . The small current is detected by a sense amplifier connected to the bit line  26  to detect the presence or absence of the electronic charge and therefore the digital data stored on the flash EEPROM cell. If the floating gate  18  has an electronic charge, the threshold voltage of the memory cell increases and the memory cell does not conduct at the voltage level of the power supply voltage source and the sense amplifier detects a logical “1.” Alternately, if there is no electronic charge present on the floating gate  18 , the memory cell turns on and the sense amplifier detects a logical “0.” 
           [0011]    As further described in the SST White Paper and illustrated in U.S. Pat. Nos. 6,314,022 (Kawata, et al.), 6,265,266 (Dejenfelt, et al.), 6,212,102 (Georgakos, et al.), 5,912,842 (Chang, et al.), and 5,612,913 (Cappelletti, et al.) a two-transistor thin oxide cell has a select transistor added to the cell to further control the read, program, and erase of the flash EEPROM cell. The source of the select transistor is formed of the drain  12  of the memory cell. The drain of the select transistor is formed of the n+ region  32 . A layer of poly-crystalline silicon is placed over the thin oxide layer  16  between the source region  12  and the drain region  32  of the select transistor to form the control gate  34  of the select transistor. The control gate  34  is connected to a gate select line  36 . The gate select line allows the control of the application of the higher voltages to the memory cell when the flash EEPROM cell is being selected or not selected and thus helps mitigate the effects of the higher voltages on the memory cell.  
           [0012]    A split gate flash EEPROM cells, as shown in FIG. 1 c , is described in the SST White Paper and illustrated in U.S. Pat. Nos. 6,212,100 (Choi), 6,103,576 (Deustcher, et al.), 6,034,892 (Choi), 5,859,454 (Choi, et al.), 5,852,577 (Kianian, et al.). The split gate flash EEPROM cell is formed within a p-type substrate  50 . An n+ drain region  52  and an n+ source region  54  are formed within the p-type substrate  50 .  
           [0013]    A relatively thin gate dielectric  56  is deposited on the surface of the p-type substrate  50 . A poly-crystalline silicon floating gate  58  is formed on the surface of the gate dielectric  56  above the channel region  60  between the drain region  52  and source region  54 . An interpoly dielectric layer  62  is placed on the floating gate  58  to separate the floating gate  58  from a second layer of poly-crystalline silicon that forms a control gate  64 . A field enhancing tunneling injector  63  is formed on the floating gate  58  to assist in erasure of the split gate EEPROM cell. The control gate  64  is formed in stepped fashion having a portion resting on the interpoly dielectric  62  above the floating gate  58  and another portion resting directly upon the gate dielectric  56  essentially forming a two-transistor memory cell as shown in FIG. 2. In FIG. 2, the split gate transistor is represented by the select transistor  72  and the memory transistor  74 . The portion of the split gate EEPROM cell representing the select transistor  72  is the region where the control gate  64  is placed on the gate dielectric  56 . The portion of the split gate EEPROM cell representing the memory transistor  74  is the region where the control gate is resting upon the interpoly dielectric  62  above the floating gate.  
           [0014]    The source region  54  is connected to a source voltage generator through the source line  70 . The control gate  68  is connected through the word line  68  to the word line voltage generator. And the drain region  52  is connected through the bit line  64  to the bit line voltage generator.  
           [0015]    The split gate flash EEPROM cell is programmed as described in “The Impacts of Control Gate Voltage on the Cycling Endurance of Split Gate Flash Memory,” (Huang, et al.), IEEE Electron Device Letters, VOL. 21, NO. 7, July 2000, pp. 359-361, by setting the word line voltage generator to a moderate positive voltage (on the order of 2V). The bit line voltage generator is set to a relatively low positive voltage (on the order of 0.5V), while the source line voltage generator is set to a relatively high positive voltage (on the order of 50V).  
           [0016]    With the voltages as described above, hot electrons will be produced in the channel  60  near the source region  54 . These hot electrons will have sufficient energy to be accelerated across the gate dielectric  56  and trapped on the floating gate  58 . The trapped hot electrons will cause the threshold voltage of the field effect transistor (FET) that is formed by the flash EEPROM cell to be increased by three to five volts. This change in threshold voltage by the trapped hot electrons causes the cell to be programmed.  
           [0017]    To erase the flash EEPROM cell the word line voltage generator is set to a relatively large negative voltage (on the order of −11.0 v-−13.0 v). The source line voltage generator, the bit line voltage generator and the substrate  50  is set to the ground reference potential. Under these conditions there is a large electric field developed across the inter poly dielectric  62 . This field causes the electrons trapped in the floating gate  58  to flow to portion of the floating gate  58  in the region of the field enhancing tunneling injector  63 . The electrons are then extracted to the control gate  64  by the Fowler-Nordheim tunneling.  
           [0018]    The read operation of the split gate flash EEPROM has the word line voltage generator set to approximate the voltage level of the power supply voltage source (on the order of 3.0V) and the bit line voltage generator set to the relatively moderate voltage level sufficient to cause a current to be sensed by sense amplifiers present on the bit line  66 . As described above, the charge present on the floating gate  64  determines the threshold voltage of the split gate flash EEPROM cell and whether the data discerned by the sense amplifier is a logical “1” or a logical “0.” 
           [0019]    “Reliability Considerations for Reprogrammable Nonvolatile Memories,” (SST Reliability Paper), staff, Silicon Storage Technology, Inc., November, 2001 Technical Paper found May 7, 2002 www.sst.com, describes the basic failure categories that effect EEPROM cell. The basic failure categories are read faults, retention faults, and endurance faults. The failure rates for read faults and retention faults in the present technologies are sufficiently low that expected failures are in the 100&#39;s to 1000&#39;s of years and are approaching the intrinsic failure rate of the materials. Thus, the major failure category is the endurance fault.  
           [0020]    Endurance is the ability of a flash EEPROM cell to meet its data sheet specifications as a function of accumulated program and erasure cycles over time. The data sheet specifications include write functionality, data retention, and read access time. The endurance faults encompass nine major types. Endurance faults, unlike other MOS reliability concerns, result even though the device is operated within the data sheet limits. The endurance faults occur because the insulators of the gate dielectric and the interpoly dielectric are subjected to electrical stress from the Erase and Programming operations. The basic endurance failure mechanisms are oxide damage and charge trapping caused by the cumulative effects of passing a current through the oxide and placing a high electric field across the oxide. The basic endurance fault modes are:  
           [0021]    1. A stuck bit where a bit is unable to change and can be stuck in either logic state. A stuck bit can be caused either by charge trapping or oxide rupture.  
           [0022]    2. Retention Degradation where the loss of charge of the floating gate is caused by either trapped charge or damage in the insulating oxide.  
           [0023]    3. Read Time Degradation is the gradual increase in the read access time caused by accumulated trapped charge or gradual charge loss reducing the cell current.  
           [0024]    4. Erase Time Degradation is the gradual increase in the time required to erase the memory caused by accumulated trapped charge.  
           [0025]    5. Program Time Degradation is the gradual increase in the time required to program the memory caused by accumulated trapped charge.  
           [0026]    6. Disturbs are an intrinsic phenomena of all memory arrays. A disturb occurs when reading, erasing, or programming one location causes an unwanted alteration at another location.  
           [0027]    7. Over erase occurs where device is unable to Read or Program correctly because of excessive memory transistor source to drain current, which grounds the bit line read or programming voltage.  
           [0028]    8. Erase Disturb occurs by unintentionally changing the contents in a non-accessed location, while erasing another location. This occurs because the high voltage required to erase may not be isolated from the non-accessed locations.  
           [0029]    9. Program Disturb occurs by unintentionally changing the contents in a non-accessed location, while programming another location. This occurs because the high voltage required to Program may not be isolated from the non-accessed locations.  
           [0030]    U.S. Pat. No. 5,329,487 (Gupta, et al.) describes a two transistor flash EPROM cell. The two-transistor flash EPROM cell includes a first floating gate transistor for programming the cell and a second merged transistor for reading the cell. The first transistor, a floating gate transistor, has a drain coupled to the write bit line, a gate coupled to the word line, and a source coupled to the source line. The merged transistor effectively consists of a floating gate transistor connected to the floating gate of the first transistor and in series with a NMOS enhancement transistor. The series NMOS transistor has a voltage threshold of about 1 to 2 volts, thus preventing cell activation caused by over erasure (negative voltage threshold) of the floating gate transistor.  
           [0031]    U.S. Pat. No. 4,403,307 (Maeda) illustrates an EEPROM cell composed of two double gate type field effect transistors, which each have control gate and floating gate. The structures of the two field effect transistors are essentially identical to that of the stacked gate EEPROM cell as described in FIG. 1 a . The sources of the two transistors are commonly connected to a source line, which is connected as described above to a source line voltage generator. The control gates of the two transistors are commonly connected to the word line, which is connected to the word line voltage generator. One of the drains of the two transistors is connected to a read bit line and the drain of the other transistor is connected to a write bit line. The two floating gates are connected such that charge placed on the floating gate of the transistor connected to the write bit line is placed on the floating gate of the transistor of the read bit line.  
           [0032]    The reading of the EEPROM cell of Maeda is accomplish through the read bit line voltage generator and sense amplifier connected to the read bit line. The writing of the EEPROM cell of Maeda is accomplished through the write bit line voltage generator connected to the write bit line. Erasure of the EEPROM cell is accomplished with irradiating the cell with ultraviolet light or other radiation.  
         SUMMARY OF THE INVENTION  
         [0033]    An object of this invention is to provide a nonvolatile memory having improved endurance.  
           [0034]    Another object of this invention is to provide a nonvolatile memory device having programming circuitry to program a nonvolatile memory and improve the endurance of the nonvolatile memory.  
           [0035]    To accomplish at least one of these object and other objects, a nonvolatile memory device is comprised of an array of nonvolatile memory cells arranged in rows and columns. Each memory cell of each row is connected to a word line and a source select line. Each memory cell of each column connected to a first bit line and a second bit line. Each memory cell is composed of a first transistor and second transistor. The first transistor has a control gate connected to the word line receive a word line voltage, a drain connected the first bit line to receive a first bit line voltage, a source connected the source select line to receive a source line voltage, and a floating gate onto which an electronic charge is placed representing a data bit stored within the nonvolatile memory device. The a second transistor has a control gate connected to the word line receive the word line voltage, a drain connected to the second bit line to receive a second bit line voltage, a source connected to the source select line to receive the source line voltage, and a floating gate from which the electronic charge is sensed to determine the data bit stored within the nonvolatile memory device.  
           [0036]    Each memory cell has a floating gate connector joining the floating gate of the first transistor to the floating gate of the second transistor. The electronic charge representing the data bit is thus present on the floating gate of the second transistor and the floating gate of the second transistor.  
           [0037]    The nonvolatile memory device has a voltage controller connected to the first and second transistors to regulate the word line voltage, the first bit line voltage, the second bit line voltage, and the source line voltage to control operation of the nonvolatile memory device. The voltage controller programs the nonvolatile memory device to transfer the electronic charge to the floating gates by adjusting a word line voltage applied to control gates of the first and second transistors to a first moderate positive voltage level, at a first program time. Simultaneously at the first program time, a source line voltage applied to sources of the first and second transistors to a second moderate positive voltage level. A first bit line voltage applied to a drain of the first transistor and a second bit line voltage applied to a drain of the second transistor to set the drains of the first and second transistors to the substrate biasing level.  
           [0038]    At a second program time the source line voltage is adjusted to a large positive voltage level. At a third program time, the first bit line voltage to a negative voltage level. At a fourth program time, the programming is continued by adjusting the first bit line voltages to the substrate biasing level. The programming is completed at a fifth program time by adjusting the source line voltage to the substrate biasing level.  
           [0039]    In a second embodiment of the nonvolatile memory device, the voltage controller selectively programs the nonvolatile memory cells of the array by controlling the transfer of electronic charge to the floating gates by adjusting a word line voltage applied to control gates of the first and second transistors to a first moderate positive voltage level. The source line voltage applied to sources of the first and second transistors to a second moderate positive voltage level. At a second program time, the source line voltage is adjusted to a large positive voltage level and the first bit line voltage to a first small positive voltage level. The first bit voltage is adjusted to a substrate biasing level at a first program time and the second bit line voltage is adjusted to a second small positive voltage level at a fourth program time. At a fifth program time, the second bit line voltage is adjusted to the substrate biasing level. The programming is completed at a sixth program time, by adjusting the word line voltage and the source line voltage to the substrate biasing level.  
           [0040]    The voltage controller performs a read of nonvolatile memory cells of array by adjusting the word line voltage to the first moderate positive voltage level and the source line voltage and the first and second bit line voltages to the substrate biasing level at a first read time. At a second read time, the second bit line voltage is adjusted to a relatively small positive voltage level. The read operation is completed at a third read time by adjusting the word line voltage and the second bit line voltage to the substrate biasing level.  
           [0041]    In the second embodiment of nonvolatile memory device, the voltage controller selectively performs a read of the nonvolatile memory cells of the array by adjusting the word line voltage to the first moderate positive voltage level and the source line voltage and the first and second bit line voltages to the substrate biasing level at a first read time. At a second read time, the second bit line voltage is adjusted to a relatively small negative voltage level. The read is completed at a first read time, by adjusting the word line voltage and the second bit line voltage to the substrate biasing level.  
           [0042]    The voltage controller selectively performs an erase of the nonvolatile memory cells of the array by adjusting the word line voltage to the second moderate positive voltage level and the source line voltage and the first and second bit line voltages to the substrate biasing level at a first erase time. The word line voltage is adjusted to the large positive voltage level at a second erase time. The erase is completed at a third erase time, by adjusting the word line voltage to the substrate biasing level.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0043]    [0043]FIGS. 1 a - 1   c  are diagrams of cross sections of the structure of nonvolatile flash memory cells of the prior art.  
         [0044]    [0044]FIG. 2 is schematic diagram of representing an equivalent circuit of a split gate flash memory cell of FIG. 1 c.    
         [0045]    [0045]FIGS. 3 a - 3   c  are diagrams of cross sections of a nonvolatile memory cell of this invention.  
         [0046]    [0046]FIG. 3 d  is a top plan view of the structure of the nonvolatile memory cell of this invention.  
         [0047]    [0047]FIG. 3 e  is a schematic diagram of the nonvolatile memory cell of this invention  
         [0048]    [0048]FIG. 4 is a schematic diagram of the nonvolatile memory array device of this invention.  
         [0049]    [0049]FIG. 5 a  is a timing diagram of a read operation of the nonvolatile memory cell of this invention.  
         [0050]    [0050]FIG. 5 b  is a timing diagram of a program operation of the nonvolatile memory cell of this invention.  
         [0051]    [0051]FIG. 5 c  is a timing diagram of a erase operation of the nonvolatile memory cell of this invention.  
         [0052]    [0052]FIG. 6 a  is a timing diagram of a second embodiment of a read operation of the nonvolatile memory cell of this invention.  
         [0053]    [0053]FIG. 6 b  is a timing diagram of a second embodiment program operation of the nonvolatile memory cell of this invention.  
         [0054]    [0054]FIG. 7 is a plot of the cell current versus the number of cells to show the change over time of the cell current for the programming of the first and second embodiments of the nonvolatile memory cells of this invention.  
         [0055]    [0055]FIG. 8 is a plot of the cell current versus the number of cells programmed and erased illustrating the change in the cell current over time for the nonvolatile memory cells of this invention compared with the nonvolatile memory cells of the prior art.  
         [0056]    [0056]FIG. 9 is plot of the cell current versus time comparing the nonvolatile memory cells of this invention with the nonvolatile memory cells of the prior art. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0057]    The nonvolatile memory cell of this invention is a formed of two split gate transistors. Each transistor has a floating gate and a control gate. The control gate overlapping the floating gate and having a portion placed on the thin gate dielectric similar to that shown in FIG. 1 c . The floating gates are joined with a floating gate connector. Generally the control gates are connected to a word line of an array and the sources of the two transistors are connected to a source line of the array. The drain of one transistor is connected to a bit line used for programming the memory cell and the drain of the second transistor is connected to a bit line used for reading the cell.  
         [0058]    In a first embodiment, the programming is accomplished by applying a large positive voltage to the source line and a small negative voltage to the bit line connected to the drain of the first transistor. A moderate positive voltage is applied to the word line and thus to the control gates of the two transistors. This causes electrical charges to traverse from the source of the first transistor to the floating gate of the first transistor and across the joining floating gate connector to the second connector.  
         [0059]    In a second embodiment, the programming is accomplished by first applying the moderate positive voltage to the drain of the first transistor for a shorter period of time, removing the voltage, and then applying the moderate positive voltage to the drain of the second transistor. This improves the endurance of the nonvolatile memory cell by decreasing the stress of gate dielectric between the source and the floating gate of the first transistor.  
         [0060]    Refer now to FIGS. 3 a - 3   d  for a description of the structure of the nonvolatile memory cell of this invention. In the preferred embodiment, n+ regions are diffused into a p-type substrate to form the sources  104  and  126  and drains  102  and  130  of the program cell  140  and the read cell  150  of the nonvolatile memory cell of this invention. The sources  104  and  126  and drains  102  and  130  are separated by a space that forms a channel  105 . Above the channel  105 , a gate dielectric or tunneling oxide  106  is deposited upon the substrate. Above the gate dielectric  106 , a first layer of polycrystalline silicon is formed to create the floating gates  108  and  120  and a floating gate connector  122 . The floating gate connector  122  joins the floating gates  108  and  120  of the transistor of the program cell  140  and the transistor of the read cell  150 .  
         [0061]    An interpoly dielectric  112  is formed above the floating gates  108  and  120  and a floating gate connector  122 . Openings  112  are formed in the interpoly dielectric  112  and then a second polycrystalline silicon layer is formed on the surface of the interpoly dielectric  112  to produce the control gates  110  and  124 . The control gates  110  and  124  are connected to the word line  116 .  
         [0062]    The sources  104  and  126  are connected to the source line  114  and drains  102  and  130  are connected respectively to the program bit line  118  and the read bit line  132 . The sources  104  and  126  are formed by the n+ diffusion to have a connector  128  thus joining the sources  104  and  126 .  
         [0063]    [0063]FIG. 3 e  is a schematic diagram of illustrating the equivalent circuit of the nonvolatile memory cell of this invention. The memory cell is formed of the program cell  140  and a read cell  150 . The program cell  140  is formed by the transistor TxP and the read cell is formed by the transistor TxR. The floating gates as described above are joined by the connector  122 . As described above, the sources of the transistors  140  and  150  are connected to the source line  114 . The control gates are connected to the word line  140 . The drain of the transistor TxP is connected to the program bit line  118  and the drain of the transistor TxR is connected to the read bit line  132 .  
         [0064]    Nonvolatile memory devices of this invention are formed, as shown in FIG. 4, as an array  200  of the nonvolatile memory cells  205   a , . . . ,  205   n ,  210   a , . . . ,  210   n  arranged in rows and columns. Each of the nonvolatile memory cells  205   a , . . . ,  205   n ,  210   a , . . . ,  210   n  is structured as described in FIGS. 3 a - 3   e . The control gates of each of the transistors TxP and TxR of each row of the nonvolatile memory cells  205   a , . . . ,  205   n ,  210   a , . . . ,  210   n  are connected to the word lines  215   a , . . . ,  215   n . The word lines  215   a , . . . ,  215   n  are all connected to the word line decoder  217 . The word line decoder  217  receives an address of the nonvolatile memory cells  205   a , . . . ,  205   n ,  210   a , . . . ,  210   n  to which a read, program, or erase operation is to be effected. Depending on the type of operation (read, program, or erase), the word line decoder  217  generates the necessary voltages that need to be applied to the gates of the nonvolatile memory cells  205   a , . . . ,  205   n ,  210   a , . . . ,  210   n.    
         [0065]    The sources of each of the transistors TxP and TxR of each row of the nonvolatile memory cells  205   a , . . . ,  205   n ,  210   a , . . . ,  210   n  are connected to the source lines  220   a , . . . ,  220   n . The source lines  220   a , . . . ,  220   n  are all connected to the source line control circuit  235 . The source line control circuit  235  receives appropriate address and control signals to select which of the source lines  220   a , . . . ,  220   n  are activated for which of the read, program, or erases operations. The source line control circuit  235  generates the necessary voltage for performing the desired operations on the selected nonvolatile memory cells  205   a , . . . ,  205   n ,  210   a , . . . ,  210   n.    
         [0066]    The drains of each of the program transistors TxP of each column of the nonvolatile memory cells  205   a , . . . ,  205   n ,  210   a , . . . ,  210   n  are connected to the program bit lines  225   a , . . . ,  225   n . Each of the program bit lines  225   a , . . . ,  225   n  are connected to the drain of one of the program control transistors  240   a , . . . ,  240   n . The source of each of the program control transistors  240   a , . . . ,  240   n  is connected to the write buffer circuit  250 .  
         [0067]    The drains of each of the read transistors TxR of each column of the nonvolatile memory cells  205   a , . . . ,  205   n ,  210   a , . . . ,  210   n  are connected to the read bit lines  225   a , . . . ,  225   n . Each of the read bit lines  230   a , . . . ,  230   n  are connected to the drain of one of the read control transistors  245   a , . . . ,  245   n . The source of each of the read control transistors  245   a , . . . ,  245   n  is connected to the write buffer cir 230 cuit  300  and to the sense amplifier  270 .  
         [0068]    The write buffer  250  receives the input data  280  and then generates the appropriate voltage levels and timings to be applied to selected nonvolatile memory cells  205   a , . . . ,  205   n ,  210   a , . . . ,  210   n  for programming these desired memory cells. The gates of the program control transistors  240   a , . . . ,  240   n  are connected through the program control bit lines  255   a , . . . ,  255   n  to the column decoder  265 . The gates of the read control transistors  240   a , . . . ,  240   n  are connected through the read control bit lines  260   a , . . . ,  260   n  to the column decoder  265 . The column decoder  265  receive a portion of the address that is used to select a column of the array  200  to apply the appropriate voltages from the write buffer for programming the selected nonvolatile memory cells  205   a , . . . ,  205   n ,  210   a , . . . ,  210   n.    
         [0069]    During a read operation, the column decoder  265  decodes the address to generate the appropriate selections signals to be applied to the nonvolatile memory cells  205   a , . . . ,  205   n ,  210   a , . . . ,  210   n  to connect the selected columns to the sense amplifier  270 . The sense amplifier  270  detects the presence or absence of electrical charge, as described above, to determine the digital data stored within the memory array  200 . The sense amplifier  270  regenerates the digital data from the memory array  200  to create the digital data output signals  285 .  
         [0070]    The word line decoder  217 , the source line control circuit  235 , the write buffer  250 , and the column decoder  265 , collectively act as a voltage generator and control circuit  290  that provides the necessary voltages and timings of those voltages to perform the read, program, and erase of selected nonvolatile memory cells  205   a , . . . ,  205   n ,  210   a , . . . ,  210   n  of the memory array  200 . A first embodiment of the voltage generator and control circuit  290  executes the read, program, and erase operations as shown in FIGS. 5 a - 5   c . The read operation as executed by the voltage generator  290  is shown in FIG. 5 a . At a first read time τ 1 , the word line decoder  217  adjusts the word line voltage of the selected word line  215   a , . . . ,  215   n  to a moderately high positive voltage. Generally, the word line voltage is on the order the voltage level of the power supply voltage source.  
         [0071]    At a second read time τ 2 , the column decoder activates a desired read control bit line  260   a , . . . ,  260   n  to activate the desired read control transistors  245   a , . . . ,  245   n  to effectively connect the read bit lines  230   a , . . . ,  230   n  to the write buffer  250 . The write buffer  250  generates a read bit line voltage that is a relatively small positive voltage. The relatively small positive voltage is approximately +0.6 v. The bit line voltage is further chosen such that the current through the selected read transistor TxR is sufficient for detection by the sense amplifier  270 .  
         [0072]    The source line control circuit  235  sets the source lines  215   a , . . . ,  215   n  to the voltage level substrate voltage reference source or approximately zero volts. Further program bit lines  225   a , . . . ,  225   n  are placed at the voltage level of the substrate voltage reference source during the read operation. At the time τ 3 , the read operation is completed by the voltage generator  290  setting the word lines  215   a , . . . ,  215   n  and the read bit lines  230   a , . . . ,  230   n  to the voltage level of the substrate voltage source. The read set up time is the elapsed time from the first read time τ 1  until the second read time τ 2  and is more than 20 μs. The read time is the elapsed time from the second read time τ 2  until the third read time τ 3  and is approximately 20 μs.  
         [0073]    The program operation as executed by the voltage generator  290  is shown in FIG. 5 b . At a first program time τ 1 , the word line decoder  217  adjusts the word line voltage of the selected word line  215   a , . . . ,  215   n  to a first moderately high positive voltage level and the source line control circuit  235  adjusts the source lines  220   a , . . . ,  220   n  to a second moderately high positive voltage level. Generally, the word line voltage is on the order the voltage level of the power supply voltage source. Similarly, the source line voltage level is on the order the voltage level of the power supply voltage source.  
         [0074]    At a second program time τ 2 , the source line control circuit  235  adjusts the source lines  220   a , . . . ,  220   n  to a relatively high positive voltage level. The relatively high positive voltage level of the source lines  220   a , . . . ,  220   n  is on the order +10.0 v.  
         [0075]    At a third program time τ 3 , the column decoder activates a desired program control bit line  255   a , . . . ,  255   n  to activate the desired program control transistors  240   a , . . . ,  240   n  to effectively connect the program bit lines  230   a , . . . ,  230   n  to the write buffer  250 . The write buffer  250  generates a program bit line voltage that is a relatively small negative voltage. The relatively small negative voltage is approximately −1.0 v. The bit line voltage is further chosen such that the current through the selected read transistor TxR is sufficient for detection by the sense amplifier  270 .  
         [0076]    The completion of the program operation begins at the program time τ 4  when the write buffer  250  generates a program bit line voltage to the voltage level of the substrate biasing voltage source (approximately 0V or the ground reference voltage). The completion of the program operation ends at the time τ 5 , when the word line decoder  217  returns the selected word line  215   a , . . . ,  215   n  and the source line control circuit returns the source lines  220   a , . . . ,  220   n  to the voltage level of the substrate biasing voltage source.  
         [0077]    The first program set up time is the elapsed time from the first program time τ 1  until the second program time τ 2  and is approximately 10 μs. The second program set up time is the elapsed time from the second program time τ 2  until the third program time τ 3  and is less than 10 μs. The program time is the elapsed time from the third program time τ 3  until the fourth program time τ 4  and is nominally 40 μs. The program completion time is the elapsed time for the termination of the program operation, which extends from the fourth program time τ 4  to the fifth program time τ 5 . The program completion time has a duration of approximately 10 μs.  
         [0078]    In the implementation of the first embodiment of the voltage control circuit  290 , the read bit lines  230   a , . . . ,  230   n  are set to the voltage level of the substrate biasing voltage source during a program operation.  
         [0079]    A second embodiment of the voltage generator and control circuit  290  executes the read, program, and erase operations as shown in FIGS. 6 a  and  6   b . The read operation as executed by the voltage generator  290  is shown in FIG. 6 a . At a first read time τ 1 , the word line decoder  217  adjusts the word line voltage of the selected word line  215   a , . . . ,  215   n  to a moderate high positive voltage. Generally, the word line voltage is on the order the voltage level of the power supply voltage source.  
         [0080]    At a second read time τ 2 , the column decoder activates a desired read control bit line  260   a , . . . ,  260   n  to activate the desired read control transistors  245   a , . . . ,  245   n  to effectively connect the read bit lines  230   a , . . . ,  230   n  to the write buffer  250 . The write buffer  250  generates a read bit line voltage that is a relatively small negative voltage. The relatively small negative voltage is approximately −1.0 v. The bit line voltage is further chosen such that the current through the selected read transistor TxR is sufficient for detection by the sense amplifier  270 .  
         [0081]    The source line control circuit  235  sets the source lines  215   a , . . . ,  215   n  to the voltage level substrate voltage reference source or approximately zero volts. Further program bit lines  225   a , . . . ,  225   n  are placed at the voltage level of the substrate voltage reference source during the read operation. At the time τ 3 , the read operation is completed by the voltage generator  290  setting the word lines  215   a , . . . ,  215   n  and the read bit lines  230   a , . . . ,  230   n  to the voltage level of the substrate voltage source. The read set up time is the elapsed time from the first read time τ 1  until the second read time τ 2  and is approximately 10 μs. The read time is the elapsed time from the second read time τ 2  until the third read time τ 3  and is approximately 20 μs.  
         [0082]    The program operation as executed by the second embodiment of the voltage generator  290  is shown in FIG. 6 b . At a first program time τ 1 , the word line decoder  217  adjusts the word line voltage of the selected word line  215   a , . . . ,  215   n  to a first moderately high positive voltage level and the source line control circuit  235  adjusts the source lines  220   a , . . . ,  220   n  to a second moderately high positive voltage level. Generally, the word line voltage is on the order the voltage level of the power supply voltage source. Similarly, the source line voltage level is on the order the voltage level of the power supply voltage source.  
         [0083]    At a second program time τ 2 , the source line control circuit  235  adjusts the source lines  220   a , . . . ,  220   n  to a relatively high positive voltage level. The relatively high positive voltage level of the source lines  220   a , . . . ,  220   n  is on the order +10.0 v.  
         [0084]    Simultaneously, at the second program time τ 2 , the column decoder activates a desired program control bit line  255   a , . . . ,  255   n  to activate the desired program control transistors  240   a , . . . ,  240   n  to effectively connect the program bit lines  225   a , . . . ,  225   n  to the write buffer  250 . The write buffer  250  generates a program bit line voltage that is a relatively small negative voltage. The relatively small negative voltage is approximately −1.0 v.  
         [0085]    At a third program time τ 3 , the write buffer  250  adjusts the program bit line voltage to the voltage level of the substrate biasing voltage source. At a fourth program time τ 4 , the column decoder activates a desired read control bit line  260   a , . . . ,  260   n  to activate the desired read control transistors  245   a , . . . ,  245   n  to effectively connect the read bit lines  230   a , . . . ,  230   n  to the write buffer  250 . The write buffer  250  generates a read bit line voltage that is the relatively small negative voltage as applied to the program bit lines  225   a , . . . ,  225   n  between the second program time τ 2  and the third program time τ 3 .  
         [0086]    The completion of the program operation begins at the fifth program time τ 5  when the write buffer  250  adjusts the read bit line voltage to the voltage level of the substrate biasing voltage source (approximately 0V or the ground reference voltage). The completion of the program operation ends at the sixth program time τ 6 , when the word line decoder  217  returns the selected word line  215   a , . . . ,  215   n  and the source line control circuit returns the source lines  220   a , . . . ,  220   n  to the voltage level of the substrate biasing voltage source.  
         [0087]    The first program set up time is the elapsed time from the first program time τ 1  until the second program time τ 2  less than 10 μs. The first program time is the time in which the initial programming is performed from the source to the floating gate of the program transistor TxP and has an elapsed time from the second program time τ 2  until the third program time τ 3 . The first program time duration is normally approximately 20 μs. The second program time is the time in which the programming operation is continued with the transfer of the electronic charge from the source to the floating gate of the read transistor TxR and is elapsed time from the fourth program time τ 4  until the fifth program time τ 5 . The second program time duration is normally approximately 20 μs. The program completion time is the elapsed time for the termination of the program operation, which extends from the fifth program time τ 5  to the sixth program time τ 6 . The program completion time has a duration less than 10 μs.  
         [0088]    The erase operation as executed by the first and second embodiments of the voltage generator  290  is shown in FIG. 5 c . At a first erase time τ 1 , the word line decoder  217  adjusts the word line voltage of the selected word line  215   a , . . . ,  215   n  to a first moderately high positive voltage level. At a second erase time τ 2 , the word line decoder  217  adjust the word line voltage of the selected word line  215   a , . . . ,  215   n  to a relatively large positive voltage. At a third erase time τ 3 , the erase operation is complete when the word line decoder  217  adjusts the word line voltage of the selected word line  215   a , . . . ,  215   n  to the voltage level of the substrate biasing voltage source.  
         [0089]    During the entire erase operation the voltage generator  290  sets the source lines  220   a , . . . ,  220   n , the program bit lines  225   a , . . . ,  225   n , and the read bit lines  230   a , . . . ,  230   n  to the voltage level of the substrate biasing voltage source. Having the selected word line  215   a , . . . ,  215   n  at the relatively large positive voltage causes any electronic charge present on the floating gates of the program transistor TxP and the read transistor TxR to flow to the selected word line  215   a , . . . ,  215   n  by Fowler-Nordheim tunneling. The relatively large positive voltage is approximately 13 v. The erase set up time is from the first erase time τ 1  to the second erase time τ 2  and has a duration less than 5 ms. The erase time is from the second erase time τ 2  to the third erase time τ 3  and has a duration of approximately 10 ms.  
         [0090]    [0090]FIG. 7 illustrates the comparison of the degradation of the cell currents versus the number of bits of a nonvolatile memory cell of the prior art subjected to a longer and a shorter program pulse. The current through the transistor of the nonvolatile memory cells are measured as programmed and erased and plotted. The plot  300  illustrates a distribution of the nonvolatile memory cells, as initially manufactured, having a 40 μs program pulse. This is similar to the program pulse between program time τ 2  and τ 5  of FIG. 5 b . The plot  305  illustrates the distribution of the nonvolatile memory cells, as initially manufactured, having a 20 μs program pulse. The plot  310  illustrates the nonvolatile memory cells having the 40 μs program pulse after 30,000 program/erase cycles and the plot  315  illustrates the distribution of the nonvolatile memory cells having the 20 μs program pulse after 30,000 program/erase cycles. It is apparent that the shorter program pulse of the nonvolatile memory cells causes less degradation of the cell current of the nonvolatile memory cells.  
         [0091]    [0091]FIG. 8 compares the distribution of the cell currents for the single split gate nonvolatile memory cells using the 40 μs program pulse similar to that described in FIG. 7. The three essentially overlaid plots  320  illustrate the distribution of the cell current of the single transistor split gate nonvolatile memory cell of FIG. 1 c , the current of the program transistor TxP, and the current of the TxR of the nonvolatile memory cell of this invention as initially manufactured. The plots  335 ,  340 , and  345  respectively are the distribution of the cell currents of the single transistor split gate nonvolatile memory cell of FIG. 1 c  and the program transistor TxP and the TxR of the nonvolatile memory cell of this invention after 600,000 program/erase cycles. The plot  340  shows that the distribution of the cell currents of the program transistor TxP has a greater degradation than cell currents of the single transistor of the nonvolatile memory cell of FIG. 1 c  of the plot  335 . Further, the plot  345  demonstrates that the read transistor TxR actually has only a marginal degradation after the 600,000 program/erase cycles.  
         [0092]    The results as demonstrated in FIGS. 7 and 8 show that the effects of a shorter program pulse prevents degradation as shown. This phenomena led to the development of the two stage program operation of the second embodiment of the voltage generator  290  of this invention. FIG. 9 contains plots of the minimum cell current for 4000 nonvolatile memory cells having 300,000 program/erase cycles. The plot  350  is the plot of the erased cell current for the two transistor nonvolatile memory cell of this invention and an overlaying plot of the erased cell current of the single transistor nonvolatile memory cell of FIG. 1 c . The plot  355  is the plot of the erased cell current for the first embodiment of the nonvolatile memory cell of this invention. It can be seen that the single programming pulse causes some degradation of the memory cell over the numbers of program/erase cycles.  
         [0093]    The plot  360  illustrates the programmed cell current of the single transistor nonvolatile memory cell of FIG. 1 c . The plot  365  is of the programmed cell current of the first embodiment of the two transistor nonvolatile memory cell of this invention and the plot  370  is of the programmed cell current of the second embodiment of the two transistor nonvolatile memory cell of the invention. As is known, the differential between the programmed cell current and the erased cell current determines the ability of the sense amplifier of the nonvolatile memory device to distinguish between a logical “1” and logical “0” of the digital data. A wider differential indicates that the nonvolatile memory has better endurance. The differential in the plots  350  and  360  of the nonvolatile memory cell of FIG. 1 c  indicates that the endurance of the device significantly deteriorates beyond 100,000 program erase cycles.  
         [0094]    Even though the erased current increases for the first embodiment of the nonvolatile memory of this invention, the differential between the plots  355  and  365  is significantly greater than those of the nonvolatile memory cell of the prior art. Further, the two stage programming of the second embodiment of this nonvolatile memory of this invention has an even greater differential as shown by the plots  350  and  370 , thus showing a greater improvement.  
         [0095]    While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.