Abstract:
In a method for manufacturing a semiconductor memory device including a plurality of field areas, a plurality of electrode areas, a plurality of source areas and drain areas sunrounded by the field areas and the electrode areas, before forming field insulating layers for isolating the source and drain regions, impurities are introduced into the field areas between the source regions, to create an additional source region below the field insulating layer for isolating the source regions. The additional source regions are linked between the source regions.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device such as a NOR---type electrically erasable and programmable readonly memory (EEPROM). 
     2. Description of the Related Art 
     Generally, an EEPROM cell includes a P-type semiconductor substrate having an N +  -type source region, an N +  -type drain region, a floating gate electrode via a first gate insulating layer, and a control gate electrode via a second insulating layer on the floating gate electrode. 
     In a NOR-type nonvolatile semiconductor memory device by using the above-described EEPROM cells, a plurality of word lines, a plurality of bit lines, and a plurality of source lines are provided, and each of the EEPROM cells has a control gate electrode connected to one of the word lines, a source connected to one of the source lines, and a drain connected to one of the bit lines. For example, the source lines are connected to a source circuit. Therefore, a plurality of the source regions are usually electrically connected to each other. 
     In a prior art method for manufacturing a NOR-type semiconductor memory device (see JP-A-HEI 3-211775), a plurality of field areas in parallel with each other along a first direction, a plurality of electrode areas in parallel with each other along a second direction approximately perpendicular to the first direction, a plurality of source areas surrounded by the field areas and the electrode areas, and a plurality of drain areas surrounded by the field areas and the electrode areas are provided in a semiconductor substrate. In this case, the source areas and the drain areas are alternately arranged with respect to the electrode areas. First, a plurality of thick insulating layers, so called field insulating layers, are formed in the field areas. Then, electrodes each formed by a floating gate electrode and a control gate electrode are formed in the electrode areas. Then, only the thick insulating layers between the source areas are etched. Finally, impurities are introduced not only into the source reas and the drain areas but also into the field areas between the source regions. As a result, all the source regions are electrically connected to each other. This will be explained later in detail. 
     In the above-described prior art method, however, the source areas of the semiconductor substrate are overetched simultaneously with etching of the field insulating layers therebetween. As a result, the source areas of the semiconductor substrate are damaged which invites a deterioration of characteristics. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to improve the characteristics of semiconductor memory devices. 
     According to the present invention, in a method for manufacturing a semiconductor memory device including a plurality of field areas, a plurality of electrode areas, a plurality of source areas and drain areas sunrounded by the field areas and the electrode areas, before forming field insulating layers for isolating the source and drain regions, impurities are introduced into the field areas between the source regions, to create an additional source region below the field insulating layer for isolating the source regions. The additional source regions are linked between the source regions.Thus, since the etching of the field insulating layers is unnecessary, the source regions are not damaged. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description as set forth below, in comparison with the prior art, with reference to the accompanying drawings, wherein: 
     FIG. 1 is a circuit diagram illustrating a prior art NOR-type nonvolatile semiconductor memory device; 
     FIGS. 2A, 3A, 4A, 5A and 6A are plan views illustrating a prior art method for manufacturing a NOR-type nonvolatile semiconductor memory device; 
     FIGS. 2B and 2C are cross-sectional views taken along the lines B--B and C--C in FIG. 2A; 
     FIGS. 3B and 3C are cross-sectional views taken along the lines B--B and C--C in FIG. 3A; 
     FIGS. 4B, 4C and 4D are cross-sectional views taken along the lines B--B, C--C and C&#39;--C&#39; in FIG. 4A; 
     FIGS. 5B and 5C are cross-sectional views taken along the lines B--B and C--C in FIG. 5A; 
     FIGS. 6B and 6C are cross-sectional views taken along the lines B--B and C--C in FIG. 6A; 
     FIG. 7A, 8A, 9A, 10A and 11A are plan views illustrating a first embodiment of the method for manufacturing a NOR-type nonvolatile semiconductor memory device according to the present invention; 
     FIGS. 7B, 7C and 7D are cross-sectional views taken along the lines B--B, C--C and C&#39;--C&#39; in FIG. 7A; 
     FIGS. 8B and 8C are cross-sectional views taken along the lines B--B and C--C in FIG. 8A; 
     FIGS. 9B and 9C are cross-sectional views taken along the lines B--B and C--C in FIG. 9A; 
     FIGS. 10B and 10C are cross-sectional views taken along the lines B--B and C--C in FIG. 10A; 
     FIGS. 11B and 11C are cross-sectional views taken along the lines B--B and C--C in FIG. 11A; 
     FIGS. 12A, 13A, 14A, 15A and 16A are plan views illustrating a second embodiment of the method for manufacturing a NOR-type nonvolatile semiconductor memory device according to the present invention; 
     FIGS. 12B and 12C are cross-sectional views taken along the lines B--B and C--C in FIG. 12A; 
     FIGS. 13B and 13C are cross-sectional views taken along the lines B--B and C--C in FIG. 13A; 
     FIGS. 14B and 14C are cross-sectional views taken along the lines B--B and C--C in FIG. 14A; 
     FIGS. 15B and 15C are cross-sectional views taken along the lines B--B and C--C in FIG. 15A; 
     FIGS. 16B and 16C are cross-sectional views taken along the lines B--B and C--C in FIG. 16A; and 
     FIGS. 17 is a graph showing the threshold voltage characteristics of a semiconductor memory device according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Before the description of the preferred embodiments, a prior art method for manufacturing a NOR-type nonvolatile semiconductor memory device will be explained with reference to FIGS. 1, 2A, 2B, 2C, 3A, 3B, 3C, 4A, 4B, 4C, 4D, 5A, 5B, 5C, 6A, 6B and 6C. 
     In FIG. 1, which illustrates a prior art NOR-type nonvolatile semiconductor memory device, four word lines WL 1 , WL 2 , WL 3  and WL 4 , four bit lines BL 1 , BL 2 , BL 3  and BL 4  are provided. Also, memory cells C 11 , C 12 , . . . ,C 44  are provided at intersections between the word lines WL 1 , WL 2 , WL 3  and WL 4 , the bit lines BL 1 , BL 2 , BL 3  and BL 4 , and the source lines SL 1 , SL 2 , SL 3  and SL 4 . For example, memory cell C 11  has a floating gate FG, a control gate CG connected to the word line WL 1 , a drain D connected to the bit line BL 1 , and a soure S connected to the source line SL 1 . 
     Also, usually, in an erase mode, all the voltages at the source lines SL 1 , SL 2 , SL 3  and SL 4  are at a high voltage V PP  (=20 to 25 V), while in a non-erase mode, all the voltages at the source lines SL 1 , SL 2 , SL 3  and SL 4  are at a low voltage GND (=0 V). 
     Also, in FIG. 2A, a monocrystalline silicon substrate 1 is divided into a plurality of field areas A 1  in parallel with each other along an X direction, a plurality of electrode areas A 2  in parallel with each other along a Y direction, a plurality of source areas A 3  surrounded by the field areas A 1  and the electrode areas A 2 , and a plurality of drain areas A 4  surrounded by the field areas A 1  and the electrode areas A 2 . In this case, the source areas A 3  and the drain areas A 4  are alternately arranged in the Y direction. 
     First, referring to FIGS. 2A, 2B and 2C, a silicon oxide layer 2 is formed by thermally oxidizing the silicon substrate 1. Also, a silicon nitride layer 3 is formed by a chemical vapor deposition (CVD) process, and the silicon nitride layer 3 is patterned by a photolithography process. That is, the field areas A 1  of the silicon nitride layer 3 are perforated. Then, a heating operation is carried out under an oxygen atmosphere, to create a thick field silicon layer 4. This is called a local oxidation of silicon (LOCOS). Then, the silicon nitride layer 3 and the exposed silicon oxide layer 2 are removed. 
     Next, referring to FIGS. 3A, 3B and 3C, the silicon subtrate 1 is thermally oxidized to grow an about 50 to 150 Å thick gate silicon oxide layer 5, and then, an about 1000 to 3000 Å thick phosphorus including polycrystalline silicon layer 6 is deposited on the silicon oxide layer 5 by a CVD process. Also, the polycrystalline silicon layer 6 is thermally oxidized to grow an about 100 to 300 Å thick gate silicon oxide layer 7, and then, a phosphorus including polycrystalline silicon layer 8 is deposited on the silicon oxide layer 7 by a CVD process. Then, the polycrystalline silicon layer 8, the silicon oxide layer 7 and the polycrystalline silicon layer 6 are patterned by a photolithography and etching process to form control gate electrodes CG and floating gate electrodes FG. Note that the control gates CG are connected to the word lines WL 1 , WL 2 , WL 3  and WL 4  of FIG. 1. 
     Next, referring to FIGS. 4A, 4B, 4C and 4D, a photoresist pattern 9 is formed to cover at least the drain areas A 4 . Then, the field silicon oxide layer 4 and the gate silicon oxide layer 5 are etched with a mask of the photoresist pattern 9 and the control gate electrodes 8 (CG). As a result, only the field silicon oxide layer 5 sandwiched by the source areas A 3  is removed. Then, the photoresist pattern 9 is removed. 
     Next, referring to FIGS. 5A, 5B and 5C, impurity ions such as arsenic ions are implanted into the silicon substrate 1 with a mask of the control gate electrodes 8 (CG) and the field silicon oxide layers 4. As a result, source regions 10S are formed in the source areas A 3  of the silicon substrate 1, and drain regions 10D are formed in the drain areas A 4  of the silicon substrate 1. 
     Finally, referring to FIGS. 6A, 6B and 6C, an insulating layer 11 is formed, and an aluminum wiring layer 12 which serves as the bit lines BL 1 , BL 2 , BL 3  and BL 4  of FIG. 1 is formed. Further, a cover insulating layer 13 is formed, thus completing a NOR-type nonvolatile semiconductor memory device. 
     The above-described prior art method is disclosed in JP-A-HEI3-211775, for example. 
     In the prior art method, when the field silicon oxide layers 4 are etched as indicated by X in FIGS. 3B and 4B, the silicon oxide layer 5 is also etched as indicated by Y in FIGS. 3B and 4B. In this case, the silicon substrate 1 indicated by Y may be overetched, and accordingly, the silicon substrate 1 is damaged, which invites a deterioration of characteristics such as threshold voltage characteristics. 
     A first embodiment of the present invention is explained next with reference to FIGS. 7A, 7B, 7C, 7D, 8A, 8B, 8C, 9A, 9B, 9C, 10A, 10B, 10C, 11A, 11B and 11C. 
     First, referring to FIGS. 7A, 7B, 7C and 7D, a silicon oxide layer 2 is formed by thermally oxidizing the silicon substrate 1. Also, a silicon nitride layer 3 is formed by a CVD process, and the silicon nitride layer 3 is patterned by a photolithography process. That is, the field areas A 1  of the silicon nitride layer 3 are perforated. Then, a photoresist pattern 21 is formed by a photolithography process to cover at least the field areas A 1  sandwiched by the drain areas A 4 . Then, impurity ions such as arsenic ions are implanted into the silicon substrate 1 with a mask of the silicon nitride layer 3 and the photoresist pattern 21. As a result, source regions 10S-1 are formed in the silicon substrate 1 surrounded by the source areas A 3 . Then, the photoresist pattern 21 is removed. 
     Next, referring to FIGS. 8A, 8B and 8C, a heating operation is carried out under an oxygen atmosphere, to create a thick field silicon layer 4. This is called LOCOS. Then, the silicon nitride layer 3 and the exposed silicon oxide layer 2 are removed. 
     Next, referring to FIG. 9A, 9B and 9C, in the same way as in FIGS. 3A, 3B and 3C, the silicon subtrate 1 is thermally oxidized to grow an about 50 to 150 Å thick gate silicon oxide layer 5, and then, an about 1000 to 3000 Å thick phosphorus including polycrystalline silicon layer 6 is deposited on the silicon oxide layer 5 by a CVD process. Also, the polycrystalline silicon layer 6 is thermally oxidized to grow an about 100 to 300 Å thick gate silicon oxide layer 7, and then, a phosphorus including polycrystalline silicon layer 8 is deposited on the silicon oxide layer 7 by a CVD process. Then, the polycrystalline silicon layer 8, the silicon oxide layer 7 and the polycrystalline silicon layer 6 are patterned by a photolithography and etching process to form control gate electrodes CG and floating gate electrodes FG. Note that the control gates CG are connected to the word lines WL 1 , WL 2 , WL 3  and WL 4  of FIG. 1. 
     Next, referring to FIG. 10A, 10B and 10C, in the same way as in FIGS. 5A, 5B and 5C, impurity ions such as arsenic ions are implanted into the silicon substrate 1 with a mask of the control gate electrodes 8 (CG) and the field silicon oxide layers 4. As a result, source regions 10S-2 are formed in the source areas A 3  of the silicon substrate 1, and drain regions 10D are formed in the drain areas A 4  of the silicon substrate 1. 
     Finally, referring to FIG. 11A, 11B and 11C, in the same way as in FIGS. 6A, 6B and 6C, an insulating layer 11 is formed, and an aluminum wiring layer 12 which serving as the bit lines BL 1 , BL 2 , BL 3  and BL 4  of FIG. 1 is formed. Further, a cover insulating layer 13 is formed, thus completing a NOR-type nonvolatile semiconductor memory device. 
     A second embodiment of the present invention is explained next with reference to FIGS. 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, 14C, 15A, 15B, 15C, 16A, 16B and 16C. 
     First, referring to FIGS. 12A, 12B and 12C, a silicon oxide layer 2 is formed by thermally oxidizing the silicon substrate 1. Then, a photoresist pattern 31 is formed. That is, the photoresist pattern 31 has openings defining a part of the field areas A 1  surrounded by the source areas A 3  and a part of the source areas A 3 . Then, impurity ions such as arsenic ions are implanted into the silicon substrate 1 with a mask of the photoresist pattern 31. As a result, source regions 10S-3 are formed in the silicon substrate 1 extending over the source areas A 3 . Then, the photoresist pattern 31 is removed. 
     Next, referring to FIGS. 13A, 13B and 13C, in a similar way to that as shown in FIGS. 2A, 2B and 2C, a silicon nitride layer 3 is formed by a CVD process, and the silicon nitride layer 3 is patterned by a photolithography process. That is, the field areas A 1  of the silicon nitride layer 3 are perforated. Then, a heat operation is carried out under an oxygen atmosphere, to create a thick field silicon layer 4. This is called LOGOS. Then, the silicon nitride layer 3 and the exposed silicon oxide layer 2 are removed. 
     Next, referring to FIG. 14A, 14B and 14C, in the same way as in FIGS. 3A, 3B and 3C, the silicon subtrate 1 is thermally oxidized to grow an about 50 to 150 Å thick gate silicon oxide layer 5, and then, an about 1000 to 3000 Å thick phosphorus including polycrystalline silicon layer 6 is deposited on the silicon oxide layer 5 by a CVD process. Also, the polycrystalline silicon layer 6 is thermally oxidized to grow an about 100 to 300 Å thick gate silicon oxide layer 7, and then, a phosphorus including polycrystalline silicon layer 8 is deposited on the silicon oxide layer 7 by a CVD process. Then, the polycrystalline silicon layer 8, the silicon oxide layer 7 and the polycrystalline silicon layer 6 are patterned by a photolithography and etching process to form control gate electrodes CG and floating gate electrodes FG. Note that the control gates CG are connected to the word lines WL 1 , WL 2 , WL 3  and WL 4  of FIG. 1. 
     Next, referring to FIG. 15A, 15B and 15C, in the same way as in FIGS. 5A, 5B and 5C, impurity ions such as arsenic ions are implanted into the silicon substrate 1 with a mask of the control gate electrodes 8 (CG) and the field silicon oxide layers 4. As a result, source regions 10S-4 are formed in the source areas A 3  of the silicon substrate 1, and drain regions 10D are formed in the drain areas A 4  of the silicon substrate 1. 
     Finally, referring to FIG. 16A, 16B and 16C, in the same way as in FIGS. 6A, 6B and 6C, an insulating layer 11 is formed, and an aluminum wiring layer 12 which serves as the bit lines BL 1 , BL 2 , BL 3  and BL 4  of FIG. 1 is formed. Further, a cover insulating layer 13 is formed, thus completing a NOR-type nonvolatile semiconductor memory device. 
     In the above-described embodiments, the etching of the field silicon oxide layer is not carried out, so that the overetching of the silicon substrate, particularly, the source regions thereof hardly occurs. 
     According to the experiments conducted by the inventor, the distribution of threshold voltages after a flash erasing operation can be narrowed as shown in FIG. 17. 
     As explained hereinbefore, according to the present invention, since the damage of semiconductor substrates by etching field insulating layers is eliminated, the characteristics of semiconductor devices such as threshold voltage characteristics can be improved.