Abstract:
A method of manufacturing a semiconductor device includes a device isolation layer. In the method, a hard mask may be formed on a semiconductor substrate, and the semiconductor substrate may be etched using the hard mask as a mask to form a trench. The hard mask may be removed, and a device isolation layer may be formed in the trench. A shallow trench isolation pattern having an excellent layer quality may be formed by reducing an aspect ratio of the trench in the semiconductor device and gap-filling a dielectric. Thus, the number of defects may be decreased.

Description:
[0001]    The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2007-0118341 (filed on Nov. 20, 2007), which is hereby incorporated by reference in its entirety. 
       BACKGROUND 
       [0002]    With the fast market penetration of information appliances such as the computer, remarkable development in semiconductor device technology has occurred in recent years. In terms of function, semiconductor devices are now required to have mass storage capacity and high-speed data processing ability. Responding to such requirements, manufacturing technologies for semiconductor devices are being rapidly developed with a focus on increasing integration, reliability, and response speed. 
         [0003]    As such, semiconductor devices have become more miniaturized by methods of manufacturing increasingly integrated semiconductor devices. In a miniaturizing method for semiconductor devices, a technology for miniaturizing both a device isolation layer and a metal interconnection has become an important factor in integrating many devices. 
       SUMMARY 
       [0004]    Embodiments provide a method of manufacturing a semiconductor device including a device isolation layer having excellent trench filling performance. In embodiments, a method of manufacturing a semiconductor device comprises: forming a hard mask on a semiconductor substrate, etching the semiconductor substrate using the hard mask as an etching mask to form a trench, removing the hard mask, and forming a device isolation layer in the trench. 
         [0005]    In embodiments, a shallow trench isolation pattern with an excellent layer quality may be formed by reducing an aspect ratio of a trench in a semiconductor device and gap-filling a dielectric. Thus, the number of defects may be decreased. 
     
    
     
       DRAWINGS 
         [0006]    Example  FIGS. 1 to 6  are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments. 
           [0007]    Example  FIG. 7  is a plan view illustrating line/space patterns using a method of manufacturing a semiconductor device according to embodiments. 
           [0008]    Example  FIGS. 8A and 8B  are optical microscope images illustrating semiconductor devices formed using the patterns of example  FIG. 7 . 
       
    
    
     DESCRIPTION 
       [0009]    Example  FIGS. 1 to 6  are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments. Referring to example  FIG. 1 , a pad oxide layer  120   a , a pad nitride layer  130   a , and a mask layer  140   a  are sequentially formed on a semiconductor substrate  110 . The pad oxide layer  120   a  may be formed through a chemical vapor disposition (CVD) process or a thermal oxidation process. The thermal oxidation process, for example, may be used to provide a thickness ranging from about 1 nm to 100 nm. The pad nitride layer  130   a  may be formed, for example, through a CVD process such as a low pressure CVD (LPCVD) process, to have a thickness ranging from about 10 nm to 1,000 nm. The pad oxide layer  120   a  may serve as a buffer layer to prevent a nitrogen component of the pad nitride layer  130   a  from permeating into the semiconductor substrate  110 . The mask layer  140   a  may be formed through a CVD process to have a thickness ranging from about 10 nm to 1,000 nm. The mask layer  140   a , used to etch the semiconductor substrate  110  to form a trench, may be formed of a hard mask material. For example, the mask layer  140   a  may be one of a silicon oxynitride (SiON) layer, a silicon oxide (SiO 2 ) layer and a tetraethylorthsilicate (TEOS) layer. 
         [0010]    Referring to example  FIG. 2 , a photoresist is applied on the mask layer  140   a  formed on the semiconductor substrate  110 . A region for forming a trench  170 , illustrated in  FIG. 4 , is exposed to light and developed to form a photoresist pattern  150 . Prior to the applying of the photoresist, an anti-reflective layer may be formed on the mask layer  140   a  to prevent diffused reflection when the photoresist is exposed to light. 
         [0011]    Referring to example  FIG. 3 , the mask layer  140   a , the pad nitride layer  130   a , and the pad oxide layer  120   a  may be etched using the photoresist pattern  150  as an etch mask, to form a hard mask  140 , a pad nitride pattern  130 , a pad oxide pattern  120 . 
         [0012]    Referring to example  FIG. 4 , the photoresist pattern  150  may be removed. Then, the semiconductor substrate  110  may be etched using the hard mask  140  as an etch mask through a reactive ion etching process, so that a trench  170  having a predetermined depth may be formed in the semiconductor substrate  110 . 
         [0013]    Referring to example  FIG. 5 , the hard mask  140  on the semiconductor substrate  110  may be removed. The hard mask  140  may be removed through a wet etching process using a hydro fluoric acid (HF) or buffered HF (BHF) solution. The BHF solution may be formed by adding NH 4 F to a HF solution. The semiconductor substrate  110  may be washed as part of the wet etching process. Etchants and reaction by-products generated in etching the trench  170  may be removed to improve the subsequent deposition of an oxide layer and product yield. A solution used to etch the hard mask  140  has an etch selectivity with respect to a silicon (Si) and a silicon nitride (SiN), which may substantially prevent damage to the semiconductor substrate  110  and wash-out of a portion of the semiconductor substrate  110  in the pad nitride pattern  130  and the trench  170 . The etch selectivity may range from about 1:20 to 1:50. As such, the hard mask  140  may be removed, the pad oxide pattern  120  and the pad nitride pattern  130  are disposed on the semiconductor substrate  10  including the trench  170 . 
         [0014]    A trench-filling material may be deposited over an entire surface of a structure including the trench  170 , to form a device isolation layer  180  filling the trench  170  and covering the pad nitride pattern  130 . The device isolation layer  180  may be deposited through an atmospheric pressure chemical vapor deposition (APCVD) method. A trench-filling material for filling the trench  170  may be an O 3 -tetraetylorthosilicate (O 3 -TEOS). Here, a trench gap-fill performance depends on an aspect ratio of the trench  170 , in which the aspect ratio is a value obtained by dividing a vertical length ‘b’ of the trench  170  by a horizontal length ‘a’ thereof. That is, when the aspect ratio is great, the trench  170  is deep, so that the trench gap-fill performance may be poor. When the aspect ratio is small, the trench  170  is shallow and wide, so that the trench gap-fill performance may be good to prevent a defect such as a void. In embodiments, since the hard mask  140  is removed, the aspect ratio is reduced, so that the gap-fill performance of the device isolation layer  180  is improved. Thereafter, the device isolation layer  180  is polished through a chemical mechanical polishing (CMP) process using the pad nitride pattern  130  as an etch stop layer until the pad nitride pattern  130  is exposed to form the device isolation layer  180  in the trench  170 . 
         [0015]    Example  FIG. 7  is a plan view illustrating split line/space patterns to understand a gap-fill performance in a method of manufacturing a semiconductor device according to embodiments. Example  FIGS. 8A and 8B  are optical microscope images illustrating semiconductor devices formed using the patterns of example  FIG. 7 . 
         [0016]    Referring to example  FIG. 8A , a trench is formed in a semiconductor substrate, and then a device isolation layer is formed without removing a hard mask. Referring to example  FIG. 8B , a trench is formed in a semiconductor substrate, then a hard mask is removed, and a device isolation layer is formed using a gap-fill process. 
         [0017]    Referring to example  FIG. 7 , the line/space patterns having different sizes from each other were formed as separated first through six patterns  200   a ,  200   b ,  200   c,    200   d,    200   e,  and  200   f . The first pattern  200   a  had line/space widths of about 0.1 μm/0.14 μm. The second pattern  200   b  had line/space widths of about 0.11 μm/0.13 μm. The third pattern  200   c  had line/space widths of about 0.115 μm/0.125 μm. The fourth pattern  200   d  had line/space widths of about 0.12 μm/0.12 μm. The fifth pattern  200   e  had line/space widths of about 0.125 μm/0.115 μm. The sixth pattern  200   f  had line/space widths of about 0.13 μm/0.11 μm. 
         [0018]    Referring again to example  FIG. 8A , the trench  170  may be formed in the semiconductor substrate  110  under each of the conditions of the first through the sixth patterns  200   a ,  200   b ,  200   c,    200   d,    200   e,  and  200   f.  The device isolation layer  180  may be formed, then polished through a CMP process to form the device isolation layer  180  in the trench  170 . Then, the pad nitride pattern  130  may be removed. Finally a poly-silicon layer may be formed. In this case, voids may be generated in the trenches  170  formed in a region A under the conditions of the third through the sixth patterns  200   c ,  200   d ,  200   e , and  200   f.  The poly-silicon layer may be deposited in these voids, which is illustrated as unevenness in the optical microscope image of  FIG. 8A . 
         [0019]    Referring again to example  FIG. 8B , the trench  170  may be formed on the semiconductor substrate  110  under each of the conditions of the first through the sixth patterns  200   a ,  200   b ,  200   c ,  200   d ,  200   e , and  200   f.  The device isolation layer  180  may be formed, then polished through a CMP process to form the device isolation layer  180  in the trench  170 . The pad nitride pattern  130  is removed. Finally a poly-silicon layer is formed. In this case, voids may be generated in the trenches  170  formed in a region B under the conditions of the fourth through the sixth patterns  200   d ,  200   e , and  200   f.  The poly-silicon layer is deposited in these voids, which is illustrated as unevenness in the optical microscope image of example  FIG. 8A . That is, when the hard mask  140  was removed, a void was not seen until 0.125 μm. Therefore, when the hard mask  140  is removed, the device isolation layer  180  may be formed in the trench  170 , thereby improving a shallow trench isolation gap-fill (STI) performance and improving process tolerance. 
         [0020]    Although embodiments have been described herein, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.