Abstract:
A process for checking, reading or writing memories of a programmed computer. The process selects a pre-selected logic space in a memory to be checked. The process triggers the addressing micro-instructions of a suitable micro-program related to a pre-selected checking procedure, so as to cause its execution by means of a pre-established number of clock strokes. The micro-instructions of the micro-program are executed according to an incremental sequence and repeated in a loop.

Description:
TECHNICAL FIELD 
     The present invention relates to a process for checking the memories of a programmed microcomputer, optimized as regards life and efficiency. 
     BACKGROUND OF THE INVENTION 
     In the production of microcomputers the finished products are subjected to testing operations, in order to check on their functionality. 
     Generally microcomputers have memories within them of not inconsiderable size, and the checking time depends on the size of the memory. The checking time also depends on the type of memory to be checked, and a minimum of three readings is required for a ROM (READ ONLY MEMORY) and a maximum of sixteen readings for an EPROM (ERASABLE READ ONLY MEMORY). It can be seen that checking operations involve problems of time and cost, especially because they are executed on very expensive machines. 
     With the current checking devices and procedures, based on programs formed by instructions, that require a discrete time for the process of reading any information contained in the memory, testing times are very long and involve substantial increases in production costs. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is a process for checking the memories of a microcomputer, that allows an improvement in the analysis of said memories, at the same time minimizing checking times, so as to reduce production costs. 
     According to this object a process has been developed for checking the memories of a programmed microcomputer, including: 
     read only memories and read-and-write memories (ROM, EPROM, EEPROM, RAM), mapped into logic spaces suitable for containing information related to programs and data; 
     a group of input and output ports; 
     a register file; 
     a central microprocessor unit (CPU) comprising in turn: 
     a control memory suitable for containing micro-programs constituted by micro-instructions; 
     a pre-processor suitable for addressing the input points of the micro--by means of decoded instructions; 
     a decoder circuit for decoding said addresses of the input points of the micro-program; 
     a pointer capable of addressing said micro-instructions of said micro-programs; 
     two scanning cell chains (latches) suitable for being triggered by means of pre-established operating signals and capable of providing control signals of said logic spaces of said memories and said micro-programs; 
     a decoding unit capable of transforming into operational signals said micro-instructions of the micro-programs contained in said control memory; 
     an arithmetic-logic unit (ALU) containing an indicator register (flag); 
     a program counter and an incrementer, capable of controlling the process of addressing the information contained in said read-only and read-and-write memories; 
     a circuit for the process of addressing, capable of providing the address of each register of said register file and each of said input and output ports; 
     the above process being characterized in that it comprises the following steps: 
     to trigger said scanning cell chains by means of pre-established operating signals to generate control signals indicative of the pre-selected logic space of one of said memories to be checked, according to a pre-selected checking procedure that can be executed by means of micro-instructions of a suitable micro-program stored in said control memory; 
     to select, through said scanning cell chains, said logic space where the memory access will be performed; 
     to initialize, through said scanning cell chains, said program counter, to define the starting point of said pre-selected memory to be checked; 
     to select, through said scanning cell chains, one of said ports as an output port, on which to send all information taken from said pre-selected memory; 
     to trigger, through said scanning cell chains, said control memory, said pre-processor, said decoding unit and said pointer, the process of addressing said micro-instructions of the micro-program related to said checking procedure, in order that it be executed by means of a pre-established number of clock strokes according to the size of the memory to be checked; 
     to send to said output gate information taken from said pre-selected memory; 
     to repeat in a loop, according to an incremental sequence, the execution of said micro-instructions of the micro-program so as to send in succession to said output port all the information contained in the same pre-selected memory; 
     to reset the micro-controller through a special signal to return it to normal operating conditions. 
     According to a preferred embodiment, said micro-program suitable for executing a pre-selected checking procedure is a micro-program formed by groups of micro-instructions for executing a procedure for reading said memories. 
     According to another preferred embodiment, said micro-program suitable for executing a pre-selected checking procedure is a micro-program formed by groups of micro-instructions to execute a process of writing during the testing step, of said memories. 
     With the checking process according to the invention, based on micro-program and on an infinite loop micro-procedure, it is possible to proceed to an incremental reading, or writing, of the memories of a micro-controller, analyzing all the information contained in them., in a very short time. 
     The process according to the invention is particularly advantageous because it is based on micro-programs incorporated into the microcomputer and of a general-purpose type, that may be used on any microcomputer of the same family without any changes and with no specific adaptations. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates, with a block diagram, a micro-processor that incorporates micro-programs suitable for executing the checking process according to the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 shows a micro-controller 10 including a central micro-processor unit (CPU) 11 a reading and writing memory (RAM) 12, an electrically-erasable programmable read-only memory (EEPROM) 13, an erasable programmable read-only memory (EPROM) 14, a read-only memory (ROM) 15, a group of input and output ports 16, a register file 17, a bus 18 operationally connected to the memories 12-15 and to the central micro-processor unit 11, and a bus 19 operationally connected to the same central micro-processor unit, to the group of input and output ports 16 and to the register file 17. 
     The central micro-processor unit 11 in turn comprises a read-only control memory (CROM) 20, a pre-processor 21, a decoding circuit 22, a pointer 23, two scanning cell chains 24 and 25, a decoding unit 26, an arithmetic logic unit (ALU) 27 containing an indicator register (flag) 27a and two data registers 27b and 27c (AD and AB), a program counter and incrementer 28, an address circuit 29 for the process of addressing the registers of the file 17 and the I-O ports 16, all connected operationally together. 
     The control memory 20 is suitable for containing micro-programs formed by micro-instructions suitable for executing the checking procedures, such as the process of reading of memories 12-15, and the process of writing during the testing step of memories 12-14. 
     The pre-processor 21 contains the instructions register and the logic that overcome the decision of which kind of processes have to be executed (a next input point or the sequential evolution of the micro-program) and provide to the pointer 23 the corresponding address of said micro-programs. The decoding circuit 22 executes the decoding of instructions generating the input points of the same micro-programs. The pointer 23 is capable of addressing said micro-instructions of said micro-programs. 
     The two scanning cell chains (latches) 24 and 25 are suitable for being triggered by means of pre-established operating signals, that are introduced into the micro-processor 11 through a reset port of the group 16, and are capable of supplying all control signals of the micro-controller 10, and particularly said read-only and read-and-write memories. 
     The decoding unit 26 is capable of transforming into operational signals said micro-instructions of the micro-programs contained in the control memory 20. 
     The arithmetic-logic unit 27 contains two data registers 27b and 27c (AD and AB) and an indicator register (flag) 27a suitable for identifying the logic space where the memory reading and writing will be performed according to the logic space mapping of the memories 12-15. 
     The program counter and incrementer 28 is capable of controlling the process of addressing the information contained in said read-only and read-and-write memories. 
     As has already been said, the control memory 20 contains micro-programs suitable for executing procedures for checking, reading from or writing to the memories. 
     The micro-program for executing the procedure for reading is formed by the following sequence of micro-instructions: 
     a first micro-instruction suitable for starting the reading operation with an address previously latched in an address master latch: u1) START READ (next u2); 
     a second micro-instruction to prepare the process of addressing the subsequent information to be read, in a buffer register (master latch) of the selected memory: u2) INC+→PC &amp; LIP, R* (next u3); 
     a third micro-instruction suitable for writing information read from the addressed memory to a pre-selected register that corresponds to an I-O port of the group 16, and to recharge the counter and incrementer 28 with the address of the subsequent information to be read: u3) MEM→DWR PC→INC SET INC (next u1). 
     The micro-program for executing the procedure for writing information identical with pre-selected addresses is formed by the following sequence of micro-instructions: 
     a first micro-instruction suitable for starting the operation of writing, with an address previously latched in an address master latch, an information identical with the low part of an address: u1) START WRITE PC1→LIP, RO (next u2); 
     a second micro-instruction suitable to prepare the process of addressing the subsequent information to be written, in a buffer register of the selected memory: u2) INC+→PC &amp; LIP, R* (next u3); 
     a third micro-instruction suitable for recharging the incrementer 28 with the address of the subsequent information to be written: PC→INC SET INC (next u1). 
     The micro-program for executing the matrix-type writing procedure of information identical with that contained in two ALU registers (AD and AB), is formed by the following sequence of micro-instructions: 
     a first micro-instruction suitable for starting the operation of writing, with an address previously latched in an address master latch, an information identical with that contained in the first register (AD): u1) START WRITE AD→LIP, RO (next u2); 
     a second micro-instruction suitable to prepare the process of addressing the subsequent information to be written, in a buffer register of the selected memory: u2) INC+→PC &amp; LIP, R* (next u3); 
     a third micro-instruction suitable for recharging the incrementer 28 with the address of the subsequent information to be written: PC→INC SET INC (next u4); 
     a fourth micro-instruction suitable for starting the operation of writing, with the address previously latched in the address master latch, information identical with that contained in the second register (AB): u4) START WRITE AB→LIP, RO (next u5); 
     a fifth micro-instruction to prepare the process of addressing the subsequent information to be written, in a buffer register of the selected memory: u5) INC+→PC &amp; LIP, R* (next u6); 
     a sixth micro-instruction suitable for recharging the incrementer 28 with the address of the subsequent information to be written: PC→INC SET INC (next u1). 
     To execute the process of checking the memories 12-15, by means of the reading procedure or by means of the reading and writing procedure, pre-established operating signals are introduced through a reset gate of the group 16. These operating signals that, for example, consist of two pre-selected voltage levels, 7.5 volts and 5 volts, sent in a given sequence, generate control signals that interrupt the normal operation of the micro-controller and trigger the scanning cell chains 24 and 25. Any one of many known scanning cell chains can be used for the scanning cells of 24 and 25. One acceptable type of scanning cell chains, with a &#34;scan path&#34; procedure is described in the Italian patent application No. 21820 A/90, and is described in U.S. patent application Ser. No. 07/781,360, in the name of the same Applicant, which has issued as U.S. Pat. No. 5,225,724. These scanning cells 24 and 25 select the logic space of one of the memories 12-15 to be checked that contain either program information or data information. The same scanning cell chains select the starting point of the memory to be tested, set the incrementer 28 with the information identifying the same starting point, set the master latch of the selected memory with the starting point information and select one of the I-O ports of the group 16. Selecting one port means that every time a writing operation will be performed in the Register space the corresponding register is the I-O ports selected. This means that the scanning cell chains configure in to the Address Register 29 the physical address of the port. The scanning cell chains configure the port selected as the output of the information taken from the selected logic space, so that the information is transferred into the pre-selected register that corresponds to the I-O port. 
     When executing a matrix-type writing procedure, the scanning cell chains define in the two ALU registers (AB and AD) the data for writing to the memory. 
     The same scanning cell chains 24 and 25 trigger the address of the input point of one of the micro-programs for checking, reading or writing, stored in the control memory 20. The address of the input point is triggered through the pointer 23. 
     Control of the reading and writing micro-programs is executed through the number of clock strokes necessary for the entire operation to be completed. Each set of micro-instructions of the same micro-program requires one clock stroke and three clock strokes are necessary for reading a piece of information, while from three to six clock strokes are necessary for writing a piece of information. 
     The checking process is executed with an infinite-loop micro-procedure, which in the minimum access time of three clock strokes for internal memories, executes an incremental reading, or writing, with the information returned on the selected output gate of the group 16. 
     To exit from the checking procedure the micro-controller 10 is reset. 
     The checking process described, based on micro-programs and on an infinite-loop micro-procedure, allows the execution of the reading and writing process of the memories of a micro-controller, in a complete manner, analyzing all the information contained in them, with a substantial time saving over the usual procedures, based on programs formed by instructions that, for the process of reading information contained in the memory, typically require ten clock strokes. 
     Another advantage of the proposed procedure is that of being based on micro-programs incorporated in the microcomputer and of the general-purpose type, that may be used on any microcomputer without any changes and with no specific adaptations. 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.