Abstract:
A double-balanced mixer is provided having a shorting switch connecting the signal inputs to the mixer core. A timer circuit provides pulses to close the switch, thereby shorting those inputs at times when the switches of the mixer core are switching. This is done because non-linear components in the output are produced at those times and therefore they can be removed if the signal input is shorted at those times.

Description:
The present invention relates to double-balanced mixers used in modulators and demodulators, especially linear modulators for wireless communications. 
     BACKGROUND OF THE INVENTION 
     Modulators for wireless transmission schemes such as EDGE or WCDMA, in which part or all of the information is carried in the signal amplitude, need to be linear. Non-linearity causes transmission in frequencies outside the intended channel, causing interference in neighbouring channels. These problems are acute in modulators providing relatively high power outputs, where large signal currents cannot be switched instantaneously. 
     A typical double-balanced mixer  1 , commonly used in a linear modulator, is shown in  FIG. 1 . A pair of nodes  2  and  3  is provided as an input for a differential modulating signal. The latter is marked as voltage V i  and −V i  being applied to  2  and  3 , respectively. Another pair of nodes  7  and  8  is provided as an input for a local oscillator signal. In the remainder of the text we will refer to the local oscillator signal actually applied to nodes  7  and  8  as the clock signal. This facilitates the description of the various versions of the local oscillator signal typically found in a modulator, such as the signals generated by the local oscillator or synthesizer (the LO signal), its phase shifted and possibly frequency-divided versions, and the final in-phase (I) and quadrature (Q) switching signals at the radio carrier frequency that actually open and close the commutating switches in a double balanced mixer. The output of the double-balanced mixer is also in differential form and is provided by nodes  10  and  11 . A first pair of transistors M 1  and M 2 , having their source terminals connected to node  4 , gate terminals respectively connected to  2  and  3 , and drain terminals respectively connected to nodes  5  and  6 , form a transconductor to convert the differential signal V i  into a differential current signal i. In  FIG. 1  the said differential current signal is marked together with the bias current I B  (connected between node  4  and ground) as I B /2+i for node  5  and I B /2−i for node  6 . A second pair of NMOS transistors M 3  and M 4  have their sources connected to node  5  and their drains respectively connected to outputs  10  and  11 . A third pair of NMOS transistors M 5  and M 6  have their sources connected to node  6  and their drains respectively connected to outputs  10  and  11 . A pair of clock signals LO +  and LO −  in antiphase is provided by a local oscillator  9  (or clock generator  9  if it receives the local oscillator signal and generates the clocking signals with appropriate phasing and delays). These are applied respectively to input nodes  7  and  8  of the double balanced mixer and used to open and close its switches, which are typically provided as MOSFET or BJT transistors and shown here as M 3 , M 4 , M 5  and M 6 . Clock signal LO +  at node  7  is connected to the gates of transistors M 3  and M 6 , while clock signal LO +  at node  8  is connected to the gates of transistors M 4  and M 5 . Since the clocks are in anti-phase transistors M 3  and M 6  are generally on while transistors M 4  and M 5  are off, in which state node  5  is connected to output node  10  via M 3  and node  6  is connected to output node  11  via M 6 , and vice versa, in which state node  5  is connected to node  11  via M 4  and node  6  is connected to node  10  via M 5 . 
     Ideally the transitions between the said two states should be instantaneous, so that mathematically the four commutating switches M 3 , M 4 , M 5  and M 6 , referred to as the mixer core, serve to realize a multiplication of the input current i by an alternating sequence of 1s and −1s at the frequency of the clock signal. In practical implementations, however, the transition time τ between the two states is non-zero and depends both on the dimensions of the switches and the magnitude of the current being switched. During the transition all four transistors M 3 , M 4 , M 5  and M 6  are on and harmonics of the signal current i are created in the output. With dimensions of the switching transistors limited by speed and noise considerations in a particular application, increasing magnitude of the signal current will result in increasing transition time τ, and consequently nonlinearity of the mixer core. 
     SUMMARY OF THE INVENTION 
     According to the present invention there is provided a mixer and a method of mixing as defined in the appended claims. 
     The invention substantially reduces the nonlinearity caused by switching transitions in double balanced mixers. By blanking out the output of the mixer core by shorting the inputs during the transition times no harmonics of the signal current will be created in the output. Any reduction of signal gain due to blanking is outweighed by improved mixer linearity and larger input signal that the mixer core is capable of processing. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Examples of the invention will now be described, with reference to the accompanying drawings, of which: 
         FIG. 1  is a circuit diagram of a known double balanced mixer, 
         FIG. 2  is a circuit diagram of a double balanced mixer in accordance with the invention, 
         FIG. 3  shows clock signal and shorting pulse waveforms to illustrate the operation of the new mixer, 
         FIG. 4  is a circuit diagram of another double balanced mixer in accordance with the invention, 
         FIG. 5   a  is a circuit diagram of an implementation of the control and clock generation circuit of the circuits of  FIGS. 2 and 4 . 
         FIG. 5   b  shows signal waveforms illustrating the generation of shorting pulses by the circuit of  FIG. 5   a.    
         FIG. 6   a  is a block diagram of another implementation of the control and clock generation circuit of  FIGS. 2 and 4 . 
         FIG. 6   b  is the logic diagram of a possible master-slave implementation of the phase shifting circuit  6  in  FIG. 6   a.    
         FIG. 6   c  is the logic diagram of another possible master-slave implementation of the phase shifting circuit  6  in  FIG. 6   a.    
         FIG. 6   d  is the logic diagram of a third possible master-slave implementation of the phase shifting circuit  6  in  FIG. 6   a.    
         FIG. 7  shows signal waveforms illustrating the generation of shorting pulses by the circuit of  FIG. 6   a ,  FIG. 8  and  FIG. 9 . 
         FIG. 8   a  is the block diagram of the edge detection circuit in  FIG. 6   a , defining its inputs and output. 
         FIG. 8   b  is the logic diagram of a possible realization of the edge detector circuit of  FIG. 8   a.    
         FIG. 8   c  is the logic diagram of another possible realization of the edge detector circuit of  FIG. 8   a.    
         FIG. 9   a  is a logic and block diagram of a possible realization of pulse duration circuit in  FIG. 6   a , combined with the edge detector circuit of  FIG. 8   b.    
         FIG. 9   b  is a logic diagram of a possible realization of the edge-triggered delay circuit in  FIG. 9   a.    
         FIG. 9   c  is a circuit schematic of a possible simplified realization of the combined circuit in  FIG. 9   a  and  FIG. 8   b.    
     
    
    
     DETAILED DESCRIPTION 
       FIG. 2  is a circuit diagram of a first example of a circuit according to the invention. The circuit is a double balanced mixer similar to that of  FIG. 1 . It has the same inputs  2  and  3  for the differential input signal, inputs  7  and  8  for anti-phase clocks, differential outputs  10  and  11 , a pair of transistors M 1  and M 2  forming a transconductor and four switching transistors M 3 , M 4 , M 5  and M 6  forming the mixer core, all having the same connections to those inputs and outputs. According to the present invention, the circuit has in addition a further switch transistor M 7  connected between nodes  5  and  6 , which nodes serve both as the differential output of the transconductor and the differential input of the mixer core. Switch M 7  is controlled to open and close by a control and clock generation circuit  9 . The control and clock generation circuit is connected to receive the local oscillator signals LO and in response to provide both clock signals LOI +  LOI −  (being a delayed version of the local oscillator signals LO) for the mixer core and pulses that cause switch M 7  to close for the transition period when the transistors M 3 , M 4 , M 5  and M 6  are switching.  FIG. 3  illustrates the timing of one set of clock signals (LOI + , LOI − ) relative to the shorting pulses provided by control and clock generation circuit  9 , as well as an example of their combined effect on the differential output current i out  of the double balanced mixer. In many applications an additional set of clock signals and shorting pulses are generated for a second double balanced mixer. This is optionally and preferably provided by the same control and clock generation circuit  9 , as shown in dotted form in  FIG. 2 . 
     The closing of switch M 7  shorts nodes  5  and  6 , which are the input terminals to the mixer core. This causes the differential signals i + , i −  to cancel each other out and the shorted node is then driven by the sum (I B ) of the drain currents of M 1  and M 2 , which equals their shared bias current. This combined current then passes through the mixer core, each of the two outputs receiving an equal share due to the symmetry between transistors M 3  and M 6  (they share the same gate and source voltages) and that between M 4  and M 5  (for the same reason). 
     These output currents being equal of course means that their difference—the differential output is zero and neither the signal nor its harmonics appear in the mixer response during these periods. The blanking of the signal during these periods means that the mixer core now effectively multiplies the signal current by an alternating sequence of 1s and −1s, separated by zeros, as illustrated also in  FIG. 3 . The resulting duty cycle reduction of the 1s and −1s reduces the gain of the mixer so there is a trade off between loss of gain and improved linearity. 
     The control and clock generation circuit needs to be fairly accurate in its timing with regard to when the shorting switch is closed relative to when the transistors of the mixer are switching but inaccuracies are tolerable. If the shorted period extends into the state when the switches have switched and are full on or off then gain is sacrificed; if the period is too short and there is no shorting during some of the period when the non-linearity is generated then the reduction of the non-linearity will be less effective. 
     The control signal for switch M 7  could be generated in various ways. Two suitable circuits are described later below. In these examples and as shown in  FIG. 4  the control circuit  9  generates both the shorting pulses that control M 7  and the clock signals that control switches of the mixer core. It would also be entirely possible for the local oscillator signals LO to be applied directly to the mixer core switches and arrange the control circuit  9  to provide the shorting pulses both in response to and aligned with the local oscillator signals LO. 
       FIG. 4  shows a second example of a circuit according to the invention. This is similar to the first example except that a pair of inductors L 1  and L 2  have been inserted between the transconductor output (drain terminals of M 1  and M 2 , which are now marked as  13  and  14 , respectively) and the input to the mixer core (marked  5  and  6  as before). This overcomes a potential limitation of the first example. The transconductor may require large transistors, for example large gate widths for M 1  and M 2 , in order to carry substantial current without significantly compromising the output voltage range. As a consequence the parasitic capacitances associated with the output connections of the transconductor, marked as C D1  and C D2  in  FIGS. 2 and 4  and shown as dotted to highlight their spurious nature, may also become too large for the blanking scheme outlined in the previous example to function effectively as may be desired. When the shorting switch is closing the said parasitic capacitors do not affect the shorting of the two nodes because the charges on them can redistribute quickly to allow their voltages to become equal with relatively little influence from the current sources. 
     After the shorting pulse transistor M 7  opens and nodes  5  and  6  become separated again. Signal current needs to be established in the pair of switches that are conducting after the transition, each of which carried half the bias current immediately before the end of the shorted period. This requires node  5  and node  6  in  FIG. 2  to resume the voltages appropriate for carrying the corresponding signal currents, which in turn requires C D1  and C D2  each to be charged by part of the corresponding transconductor output current. During such voltage resumption process that is input signal dependent, the said charging current is diverted from the corresponding conducting switch and goes missing from the desired output current. Secondary distortion may thus be introduced into the output. 
     The inductors introduced in the second example mitigate the voltage resumption problem by shielding C D1  and C D2  from the input of the mixer core that is periodically shorted. Acting as short-term current memories inductors L 1  and L 2  each absorbs the voltage jump at the corresponding mixer core input node  5  or  6 , while keeping the voltages on C D1  (now connected between node  13  and ground) and C D2  (now connected between node  14  and ground) substantially unchanged during the closing of M 7 . While large value inductors generally perform the said current memory/voltage isolation function better, small inductors (from a few to tens of nanohenries) easily realizable as spirals in an integrated circuit can already be very effective at frequency ranges specified for popular wireless applications such as EDGE, WCDMA and wireless LAN. In integrated circuit realizations spiral inductors L 1  and L 2  may be constructed to maximize the mutual inductance between them (i.e. forming a mutual inductor) so as to increase the effective value of each self-inductance for differential input currents, for example by integrating them overlaid. 
     There are two aspects to the shorting pulses that control the closing of transistor M 7 . The first is the alignment of the said pulses to both the rising and the falling edges of the clock signal and the second is a brief yet controlled duration for each pulse. There are a number of ways to construct a circuit that fulfils the requirements. 
       FIG. 5   a  shows a first example of the control and clock generation circuit of the circuit of  FIGS. 2 and 4  that generates both the clock signals and the shorting pulses, which are correctly aligned with one another for the purpose of the present invention. In  FIG. 5   a , control and clock generation circuit  9  receives a local oscillator signal LO at its input (node  901 ) and provides a first output P I  of shorting pulses at node  902 , a second output LOI at node  903  for opening and closing the switches in the mixer core of the double balanced mixer  1 . Optionally, a third output P Q  of shorting pulses is provided at node  904  and a fourth output LOQ is provided at node  905  for opening and closing the switches in the mixer core of a second double balanced mixer as may be required in a linear quadrature modulator. 
     A phase shifting circuit  6  is provided that generates a first signal I at node  906  and a second signal Q at node  907  from the said LO signal. Both I and Q are at the desired carrier frequency used to switch the double-balanced mixers but are shifted from each other in phase such that both the rising and falling edges of either I or Q can be extracted using an exclusive-or logic. Known quadrature phase generators used to create clock signals in a quadrature modulator, in which the I signal is shifted nominally by 90° (quarter of the period) ahead of the Q signal, can be used for the said phase shifting circuit  16 . According to one aspect of the present invention an exclusive-nor (XOR_B) logic gate, which receives signals I and Q respectively at its input nodes  906  and  907 , is used to detect both the rising and falling edges of I and convert them to falling edges in its output I F  at node  908 , as illustrated in  FIG. 5   b . A pulse duration circuit  17  receives the XOR_B output I F , detects its falling edges and provides an output of pulses of desired duration that are synchronized to the said falling edges. In the example shown in  FIG. 5   a  the pulse duration circuit  17  consists of a NOR gate receiving I F  on a first input at node  908  while its output P I  at node  902  is delayed by two delay elements (shown in  FIG. 5   a  as a cascade of two inverters), then fed back to the second input of the NOR gate (node  909 ), whose delay is preferably substantially smaller than those of the delay elements. The delay of each inverter is preferably set to τ/2, so that the resulting pulse duration τ is the expected transition time between the +1 state and −1 state of a double balanced mixer. To match the centre of P I  to the switching transition of the clock signal LOI at node  903 , the I output of the phase shifting circuit  6  is preferably delayed by an exclusive-nor gate (receiving I on its first input at node  906  and a logic one on the other) matching that used for edge detection, followed by a NOR gate (receiving the output of the exclusive_nor gate on its first input and a logic zero on the other) matching that in the pulse duration circuit  17 , and finally by the delay element between node  910  (input of the delay element and output of the NOR gate) and node  903  (output of the delay element) that is nominally identical to either of the two delay elements in the pulse duration circuit  17 . Both P I  and the clock signal LOI at node  903  are illustrated in  FIG. 5   b , where the rising edge of LOI is centred between the rising and falling edges of P I . The optional circuit  8  for generating the quadrature clock signal LOQ at node  905  and the corresponding shorting pulses P Q  at node  904  is similar to those boxed within  5 , except the roles of I and Q inputs are exchanged and that the exclusive-nor gates are replaced by exclusive-or (XOR) gates. 
       FIG. 6   a  shows a second example of the control and clock generation circuit. Generally it again consists of a phase shifting circuit  16 , an edge detection circuit  14  and a pulse duration circuit  17 . It enables full advantage to be taken of quadrature clock generator circuits typically already in place in quadrature modulators so that the additional hardware and power consumption for generating shorting pulses, which can be significant at radio frequencies, are kept low. The phase-shifting circuit  16  in  FIG. 6   a  is based on a well-known master-slave flip-flop, three examples of which are shown in  FIG. 6   b  with NOR gates,  FIG. 6   c  with NAND gates and  FIG. 6   d  employing inverters and transmission gates, respectively. Mater slave latches per se are, of course, well known to the skilled person and as can be seen each of the master and slave latches comprise a gating portion controlled by the clock signal and a latching portion comprising cross coupled gates. 
     Returning to their use in the invention, in  FIG. 6   b , for example, four NOR gates on the left half of the circuit form the master latch receiving the clock input CK on node  601  and the differential output of the slave latch (formed by the four NOR gates on the right hand half of the circuit) Q and Qb (which is also the output of the overall flip-flop) on its differential input nodes  602  and  603 , respectively, and provides a differential output I and Ib, on nodes  604  and  605 , respectively. The slave latch receives I and Ib, on its input nodes  604  and  605  as well as the inverse of CK, CKb, on its clock input node  606 . The feedback of the flip-flop output to its (inverted) input makes it toggle upon the rising edges of the clock so that the output Q of the flip-flop is a square wave at double the period, or half the frequency, of the clock. Symmetry dictates that the master latch output I is of the same waveform as Q except that the toggling is triggered at falling clock edges, half a clock period before Q, or a quarter of the toggling period.  FIG. 7  illustrates the timing relationship between the clock signal CK, the quadrature output Q and the in-phase output I. In standard quadrature modulators the local oscillator signal is often generated at twice the carrier frequency and applied to the CK input of the toggle flip-flop, and the differential outputs of the master stage, I, Ib, and those of the slave stage, Q, Qb, both at the carrier frequency, are the only signals of interest. In these examples signals at the internal nodes of the master latch, A at  607  and B at  608 , and those of the slave latch, C at  609  and D at  610 , are also provided as the outputs of the phase shifting circuit to simplify the realization of the edge detection and pulse duration circuits. 
     The edge detection circuit  14  receives I, Ib, A and B respectively at its four inputs  604 ,  605 ,  607  and  608  and provides an output P ID  at node  803 , as shown in  FIG. 8   a . Similarly a second copy of the edge detection circuit (see  FIG. 6   a ), when needed, receives Q, Qb, C and D at its inputs (signal names and corresponding connections to those in  FIG. 6   a  are marked in brackets in  FIG. 8   a ) and provides an output P QD . Two examples of the realization of the edge detection circuit  14  are given in  FIGS. 8   b  and  8   c , respectively. 
     The edge detection example in  FIG. 8   b  comprises a first AND logic gate, connected to receive I on its first input on node  604  and A on its second input on node  607 , and to provide an output P 1  on node  801 ; a second AND gate, connected to receive Ib on its first input on node  605  and B on its second input on node  608 , and to provide an output P 2  on node  802 ; an OR logic gate (shown in  FIG. 8   b  as a NOR gate followed by an inverter buffer) is connected to receive P 1  and P 2  respectively on its inputs at  801  and  802  and to provide an output P ID  at node  803 . Because the phase-shifting circuit output I is only a slightly delayed inversion (in  FIG. 6   b  by a NOR gate, for example) of A, the said output P 1  rises on the rising edge of A and falls on the corresponding falling edge of I, and remains zero otherwise. Similarly P 2  rises on the rising edge of B (occurring at about the same time as the falling edge of A) and falls on the corresponding falling edge of Ib (occurring at about the same time as the rising edge of I), and remains zero otherwise. The edge detector output P ID , being the sum (logic OR) of P 1  and P 2 , therefore contains narrow impulses aligned with both the rising and the falling edges of I, as illustrated also in  FIG. 7 . 
     The circuit of  FIG. 8   c  is an alternative to that of  FIG. 8   b  and provides the same function but uses NOR gates instead of AND gates. 
     To convert such impulses into pulses of defined duration an edge triggered delay (ETD) element is required for the pulse duration circuit  17 , as shown in  FIG. 9   a . The said pulse duration circuit comprises an ETD circuit connected to receive the edge detection circuit output P ID  on&#39;its first input at node  803 , the reset signal on its second (reset) input at node  901  and to provide a logic 1 in its output P I  at node  902  in response to each rising (or each falling) edge in P ID  and a logic zero in P I  in response to each reset signal on the second input; a delay circuit connected to receive P I  on its input at node  902  and in response to provide a delayed replica of P I  at its output on node  901 .  FIG. 9   b  shows an example of the realization of the said ETD circuit, which comprises a D-flip-flop receiving a logic 1 at its D input, its clock input providing a first input node  803 , its reset input providing a second input node  901  and its output providing the ETD output P I  at node  902 . 
     Although the diagrams in  FIGS. 9   a  and  9   b  give a working example and clearly illustrate the concepts of the second example of the pulse duration generation, in practical realizations many simplifications are possible to merge the edge detection circuit  14  and pulse duration circuit  17  into a single schematic with fewer transistors.  FIG. 9   c  illustrates an example of such simplification. There is provided a first NMOS transistor MN 1  with its source terminal connected to ground, its gate terminal providing a first input for the edge detection circuit  14  in  FIG. 6   a , its drain terminal connected to node  911 ; a second NMOS transistor MN 2  with its source terminal connected to node  911 , its gate terminal providing a second input for  14 , its drain terminal connected to node  912 ; a third transistor MN 3  with its source terminal connected to ground, its gate terminal providing a third input for  14  and its drain terminal connected to node  913 , a fourth transistor MN 4  with its source terminal connected to node  913 , gate terminal providing a fourth input for  14  and its drain terminal connected to node  912 . The said first and second inputs are used to receive A and I outputs of the phase shifting circuit  16  in  FIG. 6   a . Both pairing A to first input, I to second input or vice versa achieve the same objective. Similarly the third and fourth inputs are used to receive B and Ib. There is also provided a first PMOS transistor MP 1  with its source terminal connected to the voltage supply V DD , its gate terminal connected to node  914  and its drain terminal connected to node  912 ; a second PMOS transistor MP 2  with its source terminal connected to V DD , its gate terminal connected to node  912  and its drain terminal connected to node  915  that provides the output P I  of the pulse duration circuit  17  of  FIGS. 6   a  and  9   a ; a fifth NMOS transistor MN 5  with its source terminal connected to ground, its gate terminal connected to node  912  and its drain terminal connected to node  915 ; and a sixth NMOS transistor MN 6  with its source terminal connected to ground, its gate terminal connected to node  916  that provides the reset input of  FIGS. 9   a  and  9   b  and its drain terminal connected to node  915 ; a first logic inverter INV 1  having its input connected to node  915  and its output connected to node  917 ; a second logic inverter INV 2  having its input connected to node  917  and its output connected to node  916 ; and a third logic inverter INV 3  having its input connected to node  916  and it output connected to node  914 . 
     Each time the output P I  on node  915  rises from logic zero to logic one, it is followed by node  916  rising to logic one after a delay of τ (twice τ/2), causing transistor MN 6  to conduct and resetting P I  to logic zero. Node  916  continues to be high for a period of τ until the logic zero of P I  propagates through delaying inverters INV 1  and INV 2 , during which period transistor MP 1  is on, charging node  912  and setting its voltage Y to logic one, turning on MN 5  and turning off MP 2  at the same time. Once node  916  follows P I  to logic zero MN 6  is turned off and the output of INV 3  rises to logic one, turning off MP 1 . As long as inputs I, A, Ib, and B are not in transition, paths through MN 1  and MN 2 , MN 3  and MN 4 , as well as MP 1  are in high impedance state and the charge stored on the Parasitic capacitance (marked in dotted form as C Y ) at node  912  will keep Y at logic one, which keeps P I  latched to logic zero through the inverter formed by MN 5  and MP 2 . Either the rising transition of A followed by the falling transition of I or the rising transition of B followed by the falling transition of Ib (hence the rising transition of I) will short node  912  to ground through either MN 1  and MN 2  because of the brief moment during which both A and I are high or MN 3  and MN 4  because of the brief moment during which both B and Ib are high. The shorting of  912  to ground causes node  915  to rise through the inverter formed by MP 2  and MN 5 , which sets P I  to logic one, and the subsequent events will continue as have been described at the beginning of the present paragraph. 
     The delay in  FIG. 6   b  between B rising to logic one (A falling to logic zero), followed by Ib falling to logic zero, and I subsequently rising to logic one is the sum of two inversion delays by NOR-gate. In  FIG. 9   c  the delay between A (or B) rising to logic one, Y falling to logic zero and P I  rising to logic one is also the sum of two inversion delays by NOR gate. Hence the rising (and falling) edges of I are aligned with those of P I . Delaying I by one inverter matched to INV 1  (or INV 2 ) to generate LOI therefore will centre each of the latter&#39;s rising edges in the middle of the corresponding pulse in P I . 
     In the above examples the edge detector has used I and Q versions of the oscillator signals. If they are not being used (and it is not desired to add a phase shifting network to generate them) the control circuit can comprise an edge detector that is responsive to just a single phase of the local oscillator signals; this would comprise, for example, two edge detectors respectively for detecting the positive and negative going edges of the local oscillator signal and ORing together their outputs. 
     In  FIGS. 5 through 9  standard logic and circuit symbols in single ended notation have been used to illustrate the underlying ideas of the present invention. It will be clear to those skilled in the art, however, that the same ideas can be easily realized using differential or pseudo-differential logic, which is especially preferable in radio frequency applications.