Abstract:
A signal line driver circuit having an input signal buffer and an open collector output circuit configuration and a method are provided for receiving an input signal and causing the output to pull down the voltage potential of a signal bus line while sinking an output current therefrom at a substantially constant output voltage with a substantially constant input-to-output signal propagation delay variation over variations in operating temperatures. A portion of the output current which is to be sunk from the signal bus line is advantageously used as the current supply for the input signal buffer circuitry. The input signal buffer circuitry uses metal oxide semiconductor field effect transistors in parallel with a bipolar junction transistor to take advantage of their mutually inverse conductivity vs. temperature characteristics, thereby ensuring that the output current sinking capability, output voltage range and input-to-output signal propagation delay variation remain substantially constant over a wide operating temperature range.

Description:
This is a continuation of co-pending application Ser. No. 07/784,610 filed on Oct. 29, 1991, now abandoned which is a continuation of Ser. No. 07/453,984 filed on Dec. 20, 1989, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to digital signal buffer amplifiers, and in particular, to digital signal line drivers having an open collector output circuit configuration for sinking an output current and/or wired-OR operation. The present invention further relates to a method of buffering a digital signal and sinking an output current. 
     2. Description of the Prior Art 
     Digital signal systems, particularly computers and signal processors, typically communicate their binary instructions and data over some form of shared signal line. Such a shared signal line is often referred to as a &#34;bus,&#34; typically consisting of hard-wired connections between the digital signal subsystems which communicate thereby. A bus configuration is preferred so as to minimize interconnections between the various digital signal subsystems. 
     An example of a signal bus line configured for wired-OR operation is illustrated in FIG. 1. This type of bus line configuration 10 consists of a shared signal line 12 pulled up by a pullup voltage V PU  via pullup resistors R PU . The digital signal subsystems communicating over the bus line 12 do so by applying their respective output signals A 1  -A n  to circuits S 1  -S n  constituting the functional equivalents of electrical switches. When an output signal A m  (m=1, 2, 3, . . ., n) is active (e.g., a logical &#34;one&#34;), its associated switch S m  closes, thereby shorting the bus line 12 to circuit ground. This pulls the bus line 12, and therefore the bus line output signal B (e.g., output voltage V 0 ), down to a logical &#34;zero.&#34; 
     The bus line configuration 10 of FIG. 1 is a wired-OR configuration. Whenever any of the individual digital subsystem output signals A m  become active (i.e., A 1  or A 2  or A 3  or . . . or A n ), the associated switch S m  pulls the bus line 12 down to a logical zero. Such a configuration 10 is sometimes referred to as &#34;backplane logic&#34; since the backplane wiring interconnecting the switches S 1  -S n  and thereby constituting the bus line 12 is actually part of the logic constituting the wired-OR configuration 10. 
     In a wired-OR logic configuration 10 such as that illustrated in FIG. 1, the circuit constituting a switch S m  typically has an open collector output circuit configuration. The collector of the output transistor is coupled directly to the bus line 12 and the emitter is coupled to circuit ground. When the circuit&#39;s driving signal A m  is active, the output transistor is turned on in its saturated mode and its collector-to-emitter voltage (&#34;Vcr&#34;) becomes virtually zero, thereby causing its collector to pull the bus line 12 down to a logical zero. 
     In the bus line configuration 10 of FIG. 1, the pullup voltage V PU  is typically two volts and two pullup resistors R PU  are used, each being in the range of 30-40 ohms and physically located near opposing ends of the backplane wiring constituting the bus line 12. A typical configuration 10 includes 32 switches S m  (i.e., m=32) and each switch S m  must be capable of sinking up to 100 milliamperes of current from the bus line 12 at a low output voltage V 0 . Therefore, under dynamic circuit 10 operating conditions, regardless of whether only one or all 32 switches S m  are active, the pullup resistors R PU  with values in the range of 30-40 ohms will substantially match the bus line 12 to the net circuit impedance presented by the switches S m . 
     An example of a transistor-transistor logic (&#34;TTL&#34;) circuit constituting a switch S m  is illustrated in FIG. 2. This bus line driver circuit 20 consists of: an input resistor 22; an input bipolar junction transistor (&#34;BJT&#34;) 24; a biasing resistor 26; an output BJT 28; an output isolation diode 30; an output pullup resistor 32; and an output pullup diode 34. The input signal A m  is a voltage having nominal TTL values. The output signal B m  has an output voltage V o  having a logical zero value of approximately 800 millivolts which is primarily dependent upon the conduction characteristics of the output isolation diode 30 and output BJT 28, and a logical one value of approximately two volts which is primarily dependent upon the pullup voltage V PU  of the bus line 12. The biasing resistor 26 and output pullup resistor 32 are pulled up to a supply voltage V+, which is typically five volts for TTL types of signals. 
     When the input signal A m  is inactive, i.e., at a logical zero (e.g., a TTL &#34;low&#34; of approximately zero volts dc), no input current flows through the input resistor 22 into the base of the input BJT 24. Thus, the input BJT 24 is turned off and no emitter current flows therefrom, and therefore, no base current flows into the output BJT 28. With no base current, the output BJT 28 is also turned off. 
     With the output BJT 28 turned off, the output voltage V o  is at a logical one, the voltage value for which is determined by the pullup voltage V PU  for the bus line 12. This is because the output pullup voltage V+ is higher than the pullup voltage V PU  for the bus line 12, which causes the output pullup diode 34 to be forward-biased but the output isolation diode 30 to be reverse-biased. The reverse-biased output isolation diode 30 causes the bus line 12 to see a virtual open circuit at the anode of the output isolation diode 30. 
     When the input signal A m  is active, i.e., at a logical one (e.g., a TTL &#34;high&#34; of approximately two volts dc), an input current flows through the input resistor 22 into the base of the input BJT 24. This turns the input BJT 24 on, resulting in emitter current flowing therefrom, and therefore, base current flowing into the output BJT 28. With sufficient base current, the output BJT 28 turns on in a saturated mode, thereby causing its voltage at its collector V CE  to represent a logical zero. Based upon the known and/or designed electrical operating characteristics of the BJTs 24, 28 and the level of the input signal A m , appropriate values for the input 22 and biasing 26 resistors can be selected so as to cause the output BJT 28 to turn on in its saturated mode. 
     With the output BJT 28 turned on in its saturated mode, its output voltage V CE  is at a logical zero and current flows into its collector. This collector current is the sum of the currents flowing through the output pullup diode 34 and output isolation diode 30, which are now forward-biased by their respective pullup voltages V+, V PU . Thus, with the output isolation diode 30 and output BJT 28 both turned on, the output voltage V 0  becomes a logical zero, the value for which is determined by the &#34;on&#34; voltage V D  of the output isolation diode 30 and the saturated output voltage V CE  of the output BJT 28. The output isolation diode 30 typically consists of a Schottky diode. Therefore, the output voltage V 0  is typically less than one volt. 
     The output isolation diode 30 is connected as shown in order to reduce the capacitive loading of the bus line 12 otherwise caused by the collector of the output BJT 28. As described above, when the circuit 20 is in its &#34;off&#34; state the output pullup voltage V+ causes the output isolation diode 30 to be reverse-biased. When the diode is reverse-biased its depletion region at its p-n junction becomes wider, and therefore, its p-n junction&#39;s capacitance is reduced. With this reduced capacitance, the capacitive load on the bus line 12, as presented thereto by the &#34;off&#34; output isolation diode 30, is reduced. Thus, the signal line driver circuit 20 of FIG. 2 presents minimal capacitive loading to the bus line 12. 
     Using a signal line driver circuit 20 as shown in FIG. 2 presents three problems. First, to effectively sink current from the bus line 12 at a low output voltage V 0 , the output BJT 28 must operate in a fully saturated mode. This requires that a significant base current be supplied to the output BJT 28, which in turn, requires a significant emitter current from the input BJT 24. Therefore, the power supply providing the biasing voltage V+ must provide a significant current to the collector of the input BJT 24. This significant collector current is multiplied many times in practice since a typical digital system uses many circuits 20 of the type illustrated in FIG. 2. Thus, this power supply must have the capability of supplying a large current. 
     Having the capacity to produce a large supply current makes a power supply much more expensive. Moreover, as the current capacity increases, the waste heat generated as a result can increase exponentially. This results in greater cooling requirements which in turn often results in greater unit weight due to heavier heatsinks and larger blowers. Hence, the greater the current capacity is, the more expensive, hotter and heavier the power supply must be. 
     Second, as is well known in the art, the conductivity of a BJT varies proportionately with temperature. Therefore, at low temperatures the conductivity of a BJT is substantially reduced. This causes the BJT&#39;s forward-bias, base-emitter junction voltage (&#34;V BE  &#34;) to increase. This in turn causes the forward biasing of the base-emitter junction, for a given base current, to decrease, thereby producing a decrease in the collector and emitter currents. This further in turn causes the collector-emitter voltage (&#34;V CE  &#34;) of the BJT to increase. 
     Therefore, at low temperatures, the output voltage V 0  of the circuit 20 increases since the output voltage V CE  of the output BJT 28 increases, as described above. This is undesirable since often the specified voltage range of the circuit output voltage V 0  is quite narrow, and frequently has a maximum value which may easily be exceeded when the transistor&#39;s output voltage V CE  increases at low temperatures. 
     Third, due to the temperature dependent conductivities of the BJTs 24, 28 and the corresponding variations in the V BE  for each, the input-to-output signal propagation delay also varies with temperature. In other words, as the operating temperature varies, the time difference between when input signal A m  becomes active and when the output BJT 28 turns on (i.e., the input-to-output signal propagation delay) also varies. Typically, over the operating temperature range of -55° C. to +125° C. the input-to-output signal propagation delay variation will be in the range of 4-5 nanoseconds. This amount of variation may be undesirable, particularly if the circuit 20 must operate at high frequency. 
     SUMMARY OF THE INVENTION 
     The signal line driver circuit and method of the present invention take advantage of the fact that power supply current for the circuitry driving the output transistor is needed only when current from the signal bus line is being sunk by the output transistor. Thus, rather than draw current from an external power supply while at the same time wasting all of the current from the signal bus line by merely sinking it all to ground via the output transistor, the signal line driver circuit and method of the present invention use some of the current from the signal bus line to drive the output transistor into saturation so as to sink the remainder of the bus line current to circuit ground. In other words, the current supply requirement is substantially reduced by diverting and using a portion of the output current which is to be merely sunk to circuit ground anyway to drive the output stage performing the current sinking. 
     The signal line driver circuit and method of the present invention further take advantage of the fact that the conductivity of a bipolar junction transistor (&#34;BJT&#34;) varies inversely with respect to the conductivity of a metal oxide semiconductor field effect transistor (&#34;MOSFET&#34;) over temperature. Thus, the signal line driver circuit and method of the present invention use a MOSFET in parallel with a BJT for sourcing the base current for the output transistor. At low temperatures, where the conductivity of the BJT is low, the conductivity of the MOSFET is high. Conversely, at high temperatures, where the conductivity of the BJT is high, the conductivity of the MOSFET is low. Therefore, as the operating temperature varies and the conductivities of the BJT and MOSFET vary inversely with respect to one another, the resulting current provided by them to the base of the output BJT remains substantially constant. Furthermore, the time needed for this resulting current to appear after the input signal becomes active also remains substantially constant. This results in a substantially constant output voltage across the output BJT and on the signal bus line, and a substantially constant input-to-output signal propagation delay over variations in operating temperature. 
     These and other objectives, features and advantages of the present invention will be more readily understood upon consideration of the following detailed description of certain preferred embodiments and the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates, in simplified, combination schematic and functional block diagram form, an example of a signal bus line in a wired-OR configuration. 
     FIG. 2 illustrates in schematic form an example of a signal bus line driver having an open collector output circuit configuration. 
     FIG. 3 illustrates in schematic form a preferred embodiment of the signal line driver circuit of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3 illustrates in schematic form a preferred embodiment of the signal line driver circuit 40 of the present invention (connected to a signal bus line 12 as discussed above). This circuit 40 includes: an input resistor 22; an input bipolar junction transistor (&#34;BJT&#34;) 24; an input metal oxide semiconductor field effect transistor (&#34;MOSFET&#34;) 42; a current limit resistor 44; an auxiliary MOSFET 46; an output BJT 28; an output isolation diode 30; an output pullup resistor 32; and an output pullup diode 34. 
     When the input signal A m  is inactive, i.e., at a logical zero, and the circuit 40 is in its &#34;off&#34; state, the signal bus line 12 is pulled up by its pullup voltage V PU  and the output is isolated by the output isolation diode 30 as described above for the circuit of FIG. 2. However, when the input signal A m  is active, i.e., at a logical one, and the circuit 40 is in its &#34;on&#34; state, the objects and advantages of the signal line driver circuit 40 of the present invention become readily apparent. 
     When the input signal A m  is active, its positive voltage representing a logical one is applied simultaneously to the input resistor 22 and the gates of the input 42 and auxiliary 46 MOSFETs. This produces a current flow through the input resistor 22 and into the base of the input BJT 24, thereby producing an emitter current 48 from the input BJT 24. This positive voltage signal A m  at the gates of the MOSFETs 42, 46 further produces currents 50, 52 flowing through their N-channels and from their respective source terminals. (The MOSFETs 42, 46 are each an N-channel enhancement type of MOSFET. Thus, as will be readily appreciated by one of reasonable skill in the art, a voltage applied to the gate of such a device which is sufficiently positive with respect to the source, i.e., greater than the turn-on threshold voltage, will produce a current flowing through the drain-source channel and out of the source terminal.) These three currents 48, 50, 52 sum together to form a single base current 54 to drive the output BJT 28 
     As illustrated in FIG. 3, the collector of the input BJT 24 and drains of the MOSFETs 42, 46 are all coupled to and receive their current supply via the signal bus line 12. As discussed above, when the input signal A m  is inactive, the circuit 40 is in its &#34;off&#34; state and requires no supply current for driving the output BJT 28. When the input signal A m  is active and the circuit 40 is in its &#34;on&#34; state, the now conductive input BJT 24 and MOSFETs 42, 46 divert from the signal bus line 12 some of that current which would otherwise be merely shunted to ground through the output isolation diode 30 and output BJT 28. 
     At very low temperatures (e.g., -55° C.) the conductivity of the input BJT 24 is quite low. Its base-emitter junction conduction curve shifts such that the turn-on threshold voltage for the base-emitter junction increases. Therefore, its emitter current 48 at a given base-to-emitter bias voltage (&#34;V BE  &#34;) is substantially reduced. However, at such low temperatures, the conductivities of the MOSFETs 42, 46 are relatively high. In other words, at low temperatures and a given gate-to-source bias voltage (&#34;V GS  &#34;), the drain current (&#34;I D  &#34;) of a MOSFET is high since its transconductance (I D  /V GS ) is high. (Conversely, at high temperatures, the inverse is true.) Therefore their source currents 50, 52 are more substantial. Hence, the resulting current sum 54 remains high enough to provide sufficient base current for the output BJT 28 to remain in saturation. Thus, at lower temperatures, the &#34;saturation&#34; base current 54 of the output BJT 28 is primarily dependent upon the source currents 50, 52 of the MOSFETs 42, 46. 
     The current limit resistor 44 is included in the source circuit of the input MOSFET 42 so as to prevent an excessive current from flowing through the input MOSFET 42. This current limit resistor 44 typically has a value on the order of tens of ohms. 
     As per the discussion above, at very low temperatures, the conductivity of the input MOSFET 42 is quite high, thereby allowing a potentially large source current 50 to flow therefrom. Without a current limit resistor 44, this source current 50 could be excessive and, if allowed to reach the output BJT 28 as its base current 54, could overdrive the output BJT 28, causing it to saturate too deeply, too quickly. If the output BJT 28 is driven into deep saturation too quickly, signal reflections are produced on the signal bus line 12 and &#34;ringing&#34; will occur. This &#34;ringing&#34; (an undesired, exponentially decaying, oscillating high frequency signal), if allowed to occur, is often of such magnitude that the &#34;ringing&#34; falsely appears to be an actual signal. This is undesirable since other subsystems (not shown) sharing the signal bus line 12 often use voltage comparators (not shown) which are triggered by the signals appearing thereon. If the &#34;ringing&#34;  falsely appears as a signal, those comparators may be falsely triggered. Furthermore, the &#34;ringing&#34; often lasts so long, i.e., decays so slowly, that the true, desired signal is obscured. 
     The auxiliary MOSFET 46 is a lower power device with a lower turn-on threshold voltage than the input MOSFET 42. In an integrated version of this circuit 40, the auxiliary MOSFET 46 is a physically smaller device than the input MOSFET 42. The auxiliary MOSFET 46 is included in parallel with the input MOSFET 42 for contributing its source current 52 to the base current 54 of the output BJT 28 during the initial turn-on of the circuit 40. As the input signal A m  goes from its inactive state to its active state, i.e., goes from a logical zero to a logical one, the finite rise time of the input signal A m  and the higher turn-on threshold voltage of the larger input MOSFET 42 prevent a source current 50 from the input MOSFET 42 from immediately flowing. The smaller auxiliary MOSFET 46, having a lower turn-on threshold voltage, produces its source current 52 sooner. Therefore, a base current 54 becomes available earlier for the output BJT 28 to begin entering saturation. Thus, the time delay between when the input signal A m  becomes active and when the output BJT 28 enters saturation, i.e., the input-to-output signal propagation delay, remains substantially constant. 
     As the source current 52 of the auxiliary MOSFET 46 nears its maximum value, the input MOSFET 42 has become conductive and has begun to produce its source current 50. Therefore, when the source current 52 of the auxiliary MOSFET 46 can increase no more, sufficient source current 50 is available from the input MOSFET 42 to drive the output BJT 28. The net result from this is that the base current 54 for the output BJT 28 becomes available virtually immediately as the input signal A m  becomes active and may increase as necessary to maintain saturation of the output BJT 28. 
     At higher temperatures where the conductivity of the input BJT 24 is better and its turn-on threshold voltage for its base-emitter junction is reduced, its emitter current 48 becomes available earlier as the input signal A m  becomes active. Thus, the input-to-output signal propagation delay, as discussed above, remains substantially constant. 
     Furthermore, at higher temperatures, the conductivities of the input BJT 24 and auxiliary MOSFET 46 increase and decrease, respectively, thereby causing their emitter 48 and source 52 currents to increase and decrease, respectively. Therefore, at higher temperatures, as the input signal A m  becomes active, the &#34;early&#34; base current 54 of the output BJT 28 becomes more dependent upon the emitter current 48 of the input BJT 24 than upon the source current 52 of the auxiliary MOSFET 46. 
     Furthermore, at higher temperatures, where the conductivities of the input BJT 24 and input MOSFET 42 increase and decrease, respectively, their emitter 48 and source 50 currents also increase and decrease, respectively. Therefore, at higher temperatures, the &#34;saturation&#34; base current 54 of the output BJT 28 is primarily dependent upon the emitter current 48 of the input BJT 24, rather than the source currents 50, 52 of the MOSFETs 42, 46. 
     The net effect of the inverse temperature dependencies of the conductivities of the input BJT 24 as compared to the MOSFETs 42, 46 is that the input-to-output signal propagation delay remains substantially constant. A preferred embodiment of the circuit 40 of the present invention maintains an input-to-output signal propagation delay variation in the range of 1-1.5 nanoseconds over an operating temperature range of -55° C. to +125° C. 
     It should be understood that various alternatives to the embodiments of the present invention described herein may be employed in practicing the present invention. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.