Abstract:
An image processing system including an image processing device and a service providing device is provided. The image processing device includes a first processor and a first memory storing instructions that cause the image processing device to obtain parameters for receiving the service from the service providing device, request the service providing device to provide the service and implement a first or second function of the image processing device based on the parameters obtained from the parameter specifying unit. The service providing device includes a second processor and a second memory storing instructions that cause the service providing device to execute a service function to provide the service to the image processing device after receiving a request for the service from the image processing device.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation-In-Part of application Ser. No. 12/050,210, filed Mar. 18, 2008. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor chip package, and more particularly, relates to a semiconductor chip package with an increased amount of input/output connections. 
     2. Description of the Related Art 
     For semiconductor chip package design, an increased amount of input/output connections for multi-functional chips is required. For a conventional lead frame based semiconductor package, however, the amount of leads for input/output connections of a semiconductor chip are limited. To solve the aforementioned problem, a ball grid array (BGA) semiconductor package has been developed to provide a greater amount of input/output connections through solder balls on the bottom of a package substrate of the semiconductor chip package. Requirements for increased input/output connections can be achieved through a finer ball pitch. Compared with the conventional lead frame based semiconductor package, however, the BGA semiconductor package suffers from poorer yields and higher fabricating costs due to the additional electrical connections to the solder balls. 
     A novel semiconductor chip package with an increased amount of input/output connections and fabricating cost between the fabricating cost for lead frame and BGA semiconductor packages is desirable. 
     BRIEF SUMMARY OF INVENTION 
     A semiconductor chip package is provided. An exemplary embodiment of the semiconductor chip package comprises a lead frame having a chip carrier, wherein the chip carrier has a first surface and an opposite second surface. A semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the semiconductor chip has an area larger than that of the chip carrier. A package substrate comprising a central region is attached to the second surface, has an area larger than that of the semiconductor chip, wherein some of the bonding pads of the semiconductor chip are electrically connected to a marginal region of the package substrate. 
     Another exemplary embodiment of the semiconductor chip package comprises a lead frame having a chip carrier. A semiconductor chip is mounted on a side of the chip carrier, having a plurality of bonding pads thereon, wherein the semiconductor chip has an area larger than that of the chip carrier. A package substrate is attached on an opposite side of the chip carrier, having an area larger than that of the semiconductor chip, wherein some of the bonding pads of the semiconductor chip are electrically connected to a top surface of the package substrate, which faces the chip carrier. 
     Yet another exemplary embodiment of the semiconductor chip package comprises a lead frame having a chip carrier and leads. A semiconductor chip is mounted on one side of the chip carrier, having a plurality of bonding pads thereon. A package substrate has a top surface is attached on an opposite side of the chip carrier, wherein the chip carrier has an area smaller than that of the semiconductor chip and the package substrate. Some of the bonding pads are electrically connected to the top surface of the package substrate, and the remaining bonding pads are electrically connected to the leads, respectively. 
     Yet another exemplary embodiment of the semiconductor chip package comprises a lead frame having a chip carrier, wherein the chip carrier has a first surface and an opposite second surface. A first semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the first semiconductor chip has an area larger that that of the chip carrier. A package substrate has a central region attached to the second surface of the chip carrier, having an area larger than that of the first semiconductor chip, wherein the package substrate comprises a plurality of fingers on a top surface thereof in a marginal region of the package substrate, which are arranged in an array with a row of inner fingers adjacent to the first semiconductor chip and a row of outer fingers adjacent to an edge of the package substrate, wherein the inner fingers are electrically connected to the bonding pads of the first semiconductor chip, and the outer fingers are electrically connected to the lead frame. 
     Yet another exemplary embodiment of the semiconductor chip package comprises a package substrate comprising a central region and a marginal region. A first semiconductor chip comprising a plurality of bonding pads thereon is mounted on a top surface in the central region of the package substrate, having an area smaller than that of the package substrate. A lead frame without a chip carrier mounted is on top surface of the package substrate. A heat sink having a cavity is mounted on the top surface of the package substrate to accommodated the first semiconductor chip, an inner portion of the lead frame and a portion of the package substrate therein. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1   a  shows a top view of one exemplary embodiment of a semiconductor chip package of the invention. 
         FIG. 1   b  shows a cross section of one exemplary embodiment of a semiconductor chip package of the invention. 
         FIG. 2  shows an assembly diagram of an exemplary embodiment of a semiconductor chip package of the invention. 
         FIG. 3   a  to  FIG. 3   e  are lead frames showing various designs of the chip carrier. 
         FIG. 4   a  shows a top view of one exemplary embodiment of a substrate of a semiconductor chip package of the invention. 
         FIG. 4   b  illustrates an enlarged view of a portion of  FIG. 4   a.    
         FIG. 5   a  shows a top view of another exemplary embodiment of a semiconductor chip package of the invention showing a package substrate design. 
         FIG. 5   b  to  FIG. 5   f  are enlarged views of portions of  FIG. 5   a.    
         FIG. 6   a  shows a top view of another exemplary embodiment of a semiconductor chip package of the invention. 
         FIG. 6   b  shows a cross section of another exemplary embodiment of a semiconductor chip package of the invention. 
         FIG. 7   a  shows a top view of another exemplary embodiment of a semiconductor chip package of the invention. 
         FIG. 7   b  shows a cross section of another exemplary embodiment of a semiconductor chip package of the invention. 
         FIG. 8  is a cross section of another exemplary embodiment of a semiconductor chip package of the invention showing a stack-die semiconductor chip package. 
         FIG. 9   a  shows a bottom view of one exemplary embodiment of a substrate of a semiconductor chip package of the invention. 
         FIG. 9   b  shows a cross section along line A-A′ of  FIG. 9   a.    
         FIG. 10  is a flow diagram showing a fabricating process for assembly of a semiconductor chip package of the invention. 
     
    
    
     DETAILED DESCRIPTION OF INVENTION 
     The following description is of a mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer the same or like parts. 
     In accordance with an embodiment of the present invention, embodiments of a semiconductor chip package are provided.  FIGS. 1   a  and  1   b  show one exemplary embodiment of the semiconductor chip package  500  of the invention.  FIG. 2  shows an assembly diagram of an exemplary embodiment of the semiconductor chip package  500 . In one embodiment of the invention, semiconductor chip package  500  may comprise a low-profile quad flat package (LQFP). Semiconductor chip package  500  comprises a lead frame  200  comprising a plurality of discrete leads  204 , supporting bonds  202  and a chip carrier  206 . Chip carrier  206  is disposed in a central portion of lead frame  200 , electrically connecting to supporting bonds  202 . Chip carrier  206  has a first surface  232  and an opposite second surface  234 . 
     A semiconductor chip  208  is mounted on the first surface  232  by an adhesive material  214 . Semiconductor chip  208  has a plurality of bonding pads  210  thereon. In one embodiment of the invention, the bonding pads  210  may be positioned to adjacent edges of the semiconductor chip  208  as shown in  FIG. 1   a . As shown in  FIGS. 1   a  and  1   b , the semiconductor chip  208  may have an area larger than that of the chip carrier  206 . 
     A package substrate  218  comprises a central region  220  and a marginal region  222 , wherein central region  220  is attached to a second surface  234  of the chip carrier  206  by an adhesive material  216 , leaving the marginal region  222  exposed through the chip carrier  206 . In one embodiment of the invention, the package substrate  218  may comprise a ball grid array (BGA) substrate. The package substrate  218  has a top surface  242  and a bottom surface  244 , wherein the top surface  242  faces a second surface  234  of the chip carrier  206 . In one embodiment of the invention, package substrate  218  may have an area larger than that of the semiconductor chip  208 . A plurality of conductive planes  226 ,  227  and  252  may be formed on the top surface  242  in the marginal region  222 , and a conductive plane  227  may be formed on the top surface  242  in the central region  220 . A plurality of vias  224  are drilled through the package substrate  218 , wherein some of the vias  224  are electrically connected to conductive planes  226 ,  227  and  252 . The semiconductor chip package  500  may further comprise recesses  246  at an edge of the package substrate  218 , through the package substrate  218 . The recesses  246  may be positioned in the conductive plane  252 . As shown in  FIG. 1   b , a plurality of ball pads  228  on a bottom surface  244  of the package substrate  218 , is electrically connected to the vias  224 . In one embodiment of the invention, each of conductive planes  226 ,  227  and  252  may be electrically connected to the corresponding ball pad  228  through vias  224 , respectively. The semiconductor chip package  500  may further comprise solder balls (not shown) formed on the ball pads  228  to provide interconnection to an underlying printed circuit board (PCB) (not shown) of a final product. 
     As shown in  FIGS. 1   a  and  1   b , some of the bonding pads  210 , for example, bonding pads  210  positioned adjacent to edges of the semiconductor chip  208 , are electrically connected to conductive planes  226  in the marginal region  222  of the package substrate  218  by bonding wires  212   a , respectively. And the remaining bonding pads  210 , for example, bonding pads  210  positioned away from the semiconductor chip  208 , are electrically connected to the leads  204  by bonding wires  212   a , respectively. For electrical connections of bonding wires  212   b  between the semiconductor chip  208  and the package substrate  218 , chip carrier  206  may have an area smaller than that of the semiconductor chip  208  and the package substrate  218 , and the package substrate  218  may have an area larger than that of the semiconductor chip  208 . A covering material  230  may encapsulate the semiconductor chip  208 , an inner portion of lead frame  200  and a portion of the package substrate  218  by such as mold filling, leaving the bottom surface  244  of the package substrate  218  exposed from the covering material  230 . 
       FIGS. 3   a  to  3   e  are lead frames showing various designs of the chip carrier  206  of lead frame  200  to optimized adhesive strength among semiconductor chip  208 , chip carrier  206  and the package substrate  218 . As shown in  FIG. 3   a , chip carrier  206  may be an intersection area of the supporting bonds  202 . Chip carrier  206  may have a square shape as shown in  FIG. 3   b . In some embodiments of the invention, chip carrier  206  may have holes  250  formed inside of the chip carrier  206  as show in  FIGS. 3   c  to  3   e . Alternatively, additional supporting bonds  258  may be formed outside of the chip carrier  206 , connected to supporting bonds  202 , to improve adhesive strength between the chip carrier  206  and the package substrate  218 . The holes  250  may have various kinds of shapes, for example, square, ladder, circle or the like, which are dependent upon design requirements, and is not limited. 
       FIGS. 4   a  and  4   b  show one exemplary embodiment of a package substrate  218  design of a semiconductor chip package of the invention. The package substrate  218  not only provides amount of input/output connections of the semiconductor chip  208 , but also serves as a heat sink for the semiconductor chip  208 . The package substrate  218  may comprise a central region  220  and a marginal region  222 . The central region  220  on the top surface  242  of the package substrate  218  is attached to and electrically connected to the second surface  234  of the chip carrier  206 , having a conductive plane  227  thereon. In one embodiment of the invention, the central region  220  of the package substrate  218  may provide ground paths of the semiconductor chip  208 , such as, ground paths of digital circuits. Also, the vias  224  in the central region  220  may be used to reduce thermal resistance. Also, a plurality of conductive planes  226 ,  252 ,  256  and  258  may be disposed on the top surface  242  in the marginal region  222  of the package substrate  218 , electrically connecting to some bonding pads  210  of the semiconductor chip  208  as shown in  FIG. 1   a , respectively. In one embodiment of the invention, the conductive planes  226  and  252  may provide multiple power and/or ground paths of the semiconductor chip  208 , such as, power and/or ground paths of analog circuits. A plurality of vias  224  is drilled through the package substrate  218 , wherein some of vias  224  are electrically connected to the conductive planes  226 ,  227 ,  256  and  258 . Each of conductive planes  226 ,  227 ,  256  and  258  may be electrically connected to a corresponding ball pad  228  (of  FIG. 1   b ) on the bottom surface  244  through the vias  224 , respectively. 
     Additionally, conductive planes  256  and  258  of the package substrate  218  may provide device interface connections for transmitting data, for example, universal serial bus (USB), high definition multimedia interface (HDMI), serial advanced technology attachment (SATA) or the like. As shown in  FIG. 4   a , the conductive planes  256  and  258  in the marginal region  222  may serve differential net planes and impedance control planes of device interfaces, respectively. Compared with the conventional lead frame based semiconductor package, length of the bonding wires for input/output connections of the semiconductor chip  208  can be reduced to have better electrical performances, such as, reduced resistance and inductance. 
     Further, a plurality of electrical components  240  and  254  may be disposed on the package substrate  218 , electrically connecting to some of the bonding pads  210  through the bonding wires  212   b  and vias  224  as shown in  FIGS. 1   a  and  1   b . The aforementioned electrical components  240  and  254  may comprise passive components comprising power rings, ground rings, capacitors, resistors or inductors. For example, the electrical component  240 , may serve as a spiral inductor trace, and be disposed on the bottom surface  244  of the package substrate  218 , electrically connecting the bonding pads  210  through the vias  245  and bonding wires  212   b  as shown in  FIGS. 1   a  and  1   b . As the inductor  240  normally cannot be seen from a top view, the inductor  240  is profiled by dashed lines in  FIG. 4   a . Additionally, electrical component  254 , may serve as a de-coupling capacitor, and may be disposed on the top surface  242  between a ground plane and a power plane, for example, conductive planes  227  and  252 . The de-coupling capacitor  254  may be used to reduce noise generated by circuits. Compared with a conventional lead frame based semiconductor package, the package substrate  218  may provide additional electrical connections for the semiconductor chip  208 , for example, power and/or ground paths. The package substrate  218  may also provide an area for electrical components, for example, power rings, ground rings, capacitors, resistors or inductors, to be disposed thereon. Some electrical performances, for example, power circuit inductance or ground circuit inductance, can be improved. Compared with the conventional ball grid array semiconductor package, package substrate  218  may have simple layout, for example, large power and ground planes without fine pitch traces. Therefore, fabricating cost can be reduced and yield can be improved. 
       FIG. 4   b  illustrates an enlarged view of a portion of  FIG. 4   a . In one embodiment of the invention, the recesses  246  may be designed at an edge of the package substrate  218 , through the package substrate  218 . The recesses  246  may be formed by firstly drilling holes (not shown) in the package substrate  218 , and then sawing package substrate  218  through the holes. The recesses  246  may be positioned in conductive plane  252  as shown in  FIG. 4   b . The recesses  246  may provide additional electrical connection paths to the top surface  242  and bottom surface  244 . Also, the recesses  246  may increase surface roughness of the package substrate  218 . Therefore, bonding strength between the covering material  230  and the resulting package substrate  218  can be improved. 
     For the conventional lead frame based semiconductor package, the pin assignment allowed for each lead in a design rule is fixed. However, the lead frame based semiconductor chip package, which combines a package substrate with desirable signal trace routing designs of the invention, may achieve signal swapping without using a costly ball grid array semiconductor package.  FIG. 5   a  shows a top view of another exemplary embodiment of a semiconductor chip package  500   b  of the invention showing a package substrate  218   a  design. In one embodiment, a plurality of fingers and corresponding conductive traces may be disposed on the top surface  242  in the marginal region  222  of the package substrate  218   a . The fingers and the corresponding conductive traces may provide desirable signal trace routing between the bonding pads and the leads.  FIG. 5   b  is an enlarged view of a portion  310  of  FIG. 5   a . As shown in  FIG. 5   a  and  FIG. 5   b , in one embodiment, the package substrate  218   a  may comprise a plurality of fingers  518  and  520  on the top surface  242  in the marginal region  222  for signal swapping. The fingers  518  and  520  are arranged in an array with two rows, comprising inner fingers  518   a  to  518   d  and outer fingers  520   a  to  520   d , wherein the inner fingers  518   a  to  518   d  are arranged along one row adjacent to the bonding pads  210  of the semiconductor chip  208 , and the outer fingers  520   a  to  520   d  are arranged along another row adjacent to an edge of the package substrate  218   a . In one embodiment, the inner fingers  518   a  to  518   d  are used to electrically connect to the bonding pads  210  of the semiconductor chip  208 , and the outer fingers  520   a  to  520   d  are be used to electrically connect to the leads  204 . For signal swapping between the bonding pad adjacent to the inner finger  514   a  and the lead adjacent to the outer finger  520   a , a conductive trace  514   a  is disposed on the top surface  242  in the marginal region  222 , electrically connected to the inner finger  518   a  and outer finger  520   d , wherein a routing direction of the conductive trace  514   a  is substantially along an outer edge of the array. Therefore, the conductive trace  514   a  may not cross the conductive trace  514   c / 514   d , which is electrically connected between the inner finger  518   c / 518   d  and the outer finger  520   a / 520   b  respectively. Similarly, the conductive trace  514   b , which is electrically connected to the inner finger  518   b  and outer finger  520   c , with a routing direction substantially along an outer edge of the array may not cross the conductive trace  514   c / 514   d  electrically connected between the inner finger  518   c / 518   d  and the outer finger  520   a / 520   b  respectively. 
     Alternatively, signal swapping may be achieved by a package substrate with conductive traces on the bottom surface  244  of the package substrate.  FIG. 5   c  is an enlarged view of a portion  312  of  FIG. 5   a . As shown in  FIG. 5   a  and  FIG. 5   c , in one embodiment, the package substrate  218   a  may comprise a plurality of fingers  522  and  524  on the top surface  242  in the marginal region  222  for signal swapping. The fingers  522  and  524  are arranged in an array with two rows, comprising inner fingers  522   a  to  522   d  and outer fingers  524   a  to  524   d  respectively, wherein the inner fingers  522   a  to  522   d  are arranged along one row adjacent to the bonding pads  210  of the semiconductor chip  208 , and the outer fingers  524   a  to  524   d  are arranged along another row adjacent to an edge of the package substrate  218   a . In one embodiment, the inner fingers  522   a  to  522   d  are used to electrically connect to the bonding pads  210  of the semiconductor chip  208 , and the outer fingers  524   a  to  524   d  are used to electrically connect to the leads  204 . For signal swapping between the bonding pad adjacent to the inner finger  522   a  and the lead adjacent to the outer finger  524   a , a conductive trace  516   a   2  may be disposed on the bottom surface  244  in the marginal region  222 . The conductive trace  516   a   2  is electrically connected to the inner finger  522   a  through a via plug  526   a   1  drilled through the package substrate  218   a  and the conductive trace  516   a   1  on the top surface  242 . Also, the conductive trace  516   a   2  may be electrically connected to the outer finger  524   d  through a via plug  526   a   2  drilled through the package substrate  218   a  and the conductive trace  516   a   3  on the top surface  242 . Therefore, the conductive trace  516   a   2  may not cross the conductive traces  516   c / 516   d , which are electrically connected between the inner finger  522   c / 522   d  and the outer finger  524   a / 524   b  respectively. Similarly, the conductive trace  516   b   2 , which is disposed on the bottom surface  244  in the marginal region  222  and electrically connected to the inner finger  522   b  and the outer finger  524   c  through via plugs  526   b   1  and  526   b   2 , and conductive traces  516   b   1  and  516   b   3 , may not cross the conductive trace  516   c / 516   d  electrically connected between the inner finger  522   c / 522   d  and the outer finger  524   a / 524   b.    
     Alternatively, signal dividing from one bonding pad into isolated leads may be achieved by a package substrate having conductive traces with branches of the invention.  FIG. 5   d  is an enlarged view of a portion  314  of  FIG. 5   a . As shown in  FIG. 5   a  and  FIG. 5   d , in one embodiment, the package substrate  218   a  may comprise a plurality of fingers  502 ,  504  and  506 . The fingers  502  are disposed adjacent to the bonding pads  210  of the semiconductor chip  208 . The fingers  504  and  506  are disposed adjacent to an edge of the package substrate  218   a . For signal dividing from the bonding pad adjacent to the finger  502   a  into two isolated leads adjacent to the fingers  504   c  and  506   c , a conductive trace  512   a   1  having two branches  512   a   2  and  512   a   3  may be disposed on the top surface  242  in the marginal region  222 , electrically connected to the finger  502   a , wherein the two branches  512   a   2  and  512   a   3  are respectively electrically connected to the fingers  504   c  and  506   c , thereby allowing the finger  502   a  to be electrically connected to the fingers  504   c  and  506   c  at the same time. A resistor  508  provided as a damping element may be coupled to the conductive trace  512   a   1 . Alternatively, the branches of the conductive trace may not be coplanar. As shown in  FIG. 5   d , for signal dividing from the bonding pad adjacent to the finger  502   b  into two isolated leads adjacent to the fingers  504   b  and  506   b , a conductive trace  512   b   1  having two branches  512   b   2  and  512   b   3  may be electrically connected to the fingers  502   b ,  504   b  and  506   b  at the same time, wherein the two branches  512   b   2  and  512   b   3  are respectively on the top surface  242  and the bottom surface  244 . The branch  512   b   3  is electrically connected to the branch  512   b   2  through a via plug  510   b   1  drilled through the package substrate  218   a . Also, the branch  512   b   3  is electrically connected to the finger  506   b  through a via plug  510   b   2  and a conductive trace  512   b   4 , which is on the top surface  242 . Similarly, a conductive trace  512   c   1 , having branches  512   c   2  and  512   c   3 , may provide a signal dividing path from the bonding pad adjacent to the finger  502   c  into the leads adjacent to the fingers  504   a  and  506   a , wherein the branch  512   c   3  is electrically connected to the branch  512   c   2  and the finger  506   a  on the top surface  242  by via plugs  510   c   1 ,  510   c   2  and another conductive trace  512   c   4 . 
     Moreover, signal dividing from one binding pad into isolated leads may also be achieved by a package substrate having conductive traces and switching bonding wires of the invention.  FIG. 5   e  is an enlarged view of a portion  314  of  FIG. 5   a  showing a package substrate design with switching bonding wires  532 . As shown in  FIG. 5   a  and  FIG. 5   e , in one embodiment, the conductive trace  512   b   1  and a switching bonding wire  532   b  may provide a signal dividing path from the bonding pad adjacent to the finger  502   b  into the leads adjacent to the fingers  504   b  and  506   b . The switching bonding wire  532   b  is respectively electrically connected to the conductive trace  512   b   1  and finger  506   b  through the connecting fingers  530   b   1  and  530   b   2 . Similarly, the conductive trace  512   c   1  and a switching bonding wire  532   c  may provide a signal dividing path from the bonding pad adjacent to the finger  502   c  into the leads adjacent to the fingers  504   a  and  506   a . The switching bonding wire  532   c  is respectively electrically connected to the conductive trace  512   c   1  and finger  506   a  through the connecting fingers  530   c   1  and  530   c   2 . As shown in  FIG. 5   e , the switching bonding wire  532   b  is across the conductive trace  512   a   1  on the top surface  242  without electrically connecting to the conductive trace  512   a   1 . Also, the switching bonding wire  532   c  is across the conductive traces  512   a   1  and  512   b   1  on the top surface  242  without electrically connecting to the conductive traces  512   a   1  and  512   b   1 . 
     For the conventional lead frame based semiconductor chip package, as the semiconductor chip is scaled down in size, a bonding problem due to bonding wire length limitations occurs. The aforementioned problem can be solved with a fine pitch leadframe to reduce a bonding distance between the bonding pads and the leads. The fine pitch leadframe, however, results in high fabrication cost and low yield.  FIG. 5   f  is an enlarged view of a portion  314  of  FIG. 5   a  showing a package substrate design to solve the bonding wire length limitation problem. As shown in  FIG. 5   a  and  FIG. 5   f , fingers  536  and  538  are arranged in a two-row array on the top surface  242  in the marginal region  222 , wherein the fingers  536  are disposed adjacent to the semiconductor chip  208 , and the fingers  538  are disposed adjacent to an edge of the package substrate  218   a . The fingers  536  may be electrically connected to the bonding pads (not shown), the bonding wires  540  may be disposed, electrically connecting between the fingers  536  and  538 , and the bonding wires  542 , electrically connecting to the fingers  538  may be used to connect the leads. The bonding distance between the bonding pads and the leads may be reduced by multiple wirebondings provided by the package substrate  218   a  comprising fingers  536  and  538  and the bonding wires  540  and  542 . 
     Signal routing from the bonding pad to the lead, which are respectively adjacent to different sides of the semiconductor chip, may be achieved by a package substrate with fingers and conductive traces of the invention. As shown in  FIG. 5   a , fingers  610   a  to  610   d  and  612   a  to  612   d  are disposed on the top surface  242  in the marginal region  222 . The fingers  610   a  to  610   d  respectively adjacent to the bonding pads  210   a  to  210   d  are electrically connected to the bonding pads  210   a  to  210   d  through the bonding wires  212   b . The fingers  612   a  to  612   d  respectively adjacent to the leads  204   a  to  204   d  are electrically connected to the leads  204   a  to  204   d  through the bonding wires  616 . A plurality of conductive traces  614   a  to  614   d  may be disposed on the top surface  242 , wherein the conductive traces  614   a  to  614   d  are electrically connected between the fingers  610   a  to  610   d  and the fingers  612   a  to  612   d , respectively. Therefore, the signal from the bonding pad may be transmitted to the lead, which is on a different side from the bonding pad, through the conductive trace on the package substrate. For example, the signal from the bonding pad  210   a  may be transmitted to the lead  204   a , which is on a different side from the bonding pad  210   a , through the conductive trace  614   a  and corresponding fingers  610   a  and  612   a.    
     Additionally, other semiconductor chips, for example, electrically erasable programmable read-only memory chips (EEPROM) with bonding pads  304  thereon may be disposed on the package substrate  218   a , which electrically connected to the semiconductor chip  208  through the bonding wires, for example, bonding wires  212   b.    
       FIG. 6   a  to  FIG. 7   b  are other exemplary embodiments of a semiconductor chip packages  500   c  and  500   d  of the invention showing a semiconductor chip package with a heat sink. As shown in  FIG. 6   a  and  FIG. 6   b , for heat dissipation efficiency improvement, a heat sink  710   a  may be mounted on the top surface  242  of the package substrate  218 , having a cavity  712   a  to accommodate the semiconductor chip  208 , an inner portion of the lead frame  200  and a portion of the package substrate  218  therein. Alternatively, as shown in  FIG. 7   a  and  FIG. 7   b , a heat sink  710   b  may be mounted on the top surface  242  of the package substrate  218  with the semiconductor chip  208  and the supporting bonds  202  directly mounted thereon without the chip carrier. The heat sink  710   b  has a cavity  712   b  to accommodate the semiconductor chip  208  and a portion of the package substrate  218  therein. 
       FIG. 8  is a cross section of another exemplary embodiment of a semiconductor chip package  500   e  of the invention showing a stack-die semiconductor chip package. Another semiconductor chip  808  may be stacked on the semiconductor chip  208  and electrically connected to the package substrate  218  through the bonding wires  812 . 
       FIG. 9   a  and  FIG. 9   b  show one exemplary embodiment of a package substrate  218  of a semiconductor chip package of the invention. The package substrate  218  may further comprise a solder mask layer  902  on the bottom surface  244  of the package substrate  218 , wherein the solder mask layer  902  comprises grooves  910  substantially along an edge of the package substrate  218 , thereby preventing bleeding out of a mold resin used for encapsulating the semiconductor chip package. 
       FIG. 10  is a flow diagram showing a fabricating process for assembly of a semiconductor chip package  500  of the invention. As shown in step  1502 , the step of assembly of a semiconductor chip package  500  comprises mounting a semiconductor chip  208  on a first surface  232  of the chip carrier  206  by adhesive material  214 . As shown in step  1504 , the central region  220  of the package substrate  218  is mounted on the second surface  234  of the chip carrier  206  by an adhesive material  216 , leaving the marginal region  222  exposed through the chip carrier  206 . As shown in step  1506 , some bonding wires  212  are electrically connected to the bonding pads  210  and conductive planes  226  in the marginal region  222  of the package substrate  218 . The remaining bonding wires  212  bond the bonding pads  210  and leads  204 . As shown in step  1508 , the covering material  230  encapsulates the semiconductor chip  208 , an inner portion of lead frame  200  and a portion of the package substrate  218  by molding, leaving the bottom surface  244  of the package substrate  218  exposed from the covering material  230 . As shown in step  1510 , the resulting semiconductor chip package  500  is packaged for product delivery. 
     The semiconductor chip package  500  is illustrated. Some advantages of an exemplary embodiment of the semiconductor chip package  500  of the invention are described in the following. The package substrate  218  not only serves as a heat sink for the semiconductor chip  208 , but also provides amount of input/output connections of the semiconductor chip  208 . Compared with the conventional lead frame based semiconductor package, the package substrate  218  may provide additional electrical connections for the semiconductor chip  208 , for example, power and/or ground paths. The package substrate  218  may also provide an area for electrical components, for example, power rings, ground rings, capacitors, resistors or inductors, to be disposed thereon. Some electrical performances, for example, power circuit inductance or ground circuit inductance, can be improved. Compared with the conventional ball grid array semiconductor package, package substrate  218  may have simple layout. Therefore, fabricating cost can be reduced and yield can be improved. The vias  224  in the central region  220  may be used for reducing thermal resistance. The chip carrier  206  of the lead frame  200  may have various designs to optimized adhesive strength among the semiconductor chip  208 , chip carrier  206  and the package substrate  218 . Additionally, the package substrate of the semiconductor chip package  500  may have fingers, conductive traces or switching bonding wires thereon to provide additional signal routing paths for signal swapping and signal dividing. Also, the bonding distance between the bonding pads and the leads may be reduced by multiple wirebondings provided by the package substrate comprising fingers and the bonding wires, thereby reducing fabrication costs. Moreover, to improve heat dissipation efficiency, the semiconductor chip packages may further comprise a heat sink mounted on the top surface of the package substrate, having a cavity to accommodate the semiconductor chip, an inner portion of the lead frame and a portion of the package substrate therein. Alternatively, another semiconductor chip may be stacked on the semiconductor chip, electrically connected to the package substrate through the bonding wires to form a stack-die semiconductor chip package. Also, the package substrate may further comprise a solder mask layer comprising grooves substantially along an edge of the package substrate, thereby preventing bleeding of a mold resin used for encapsulating the semiconductor chip package. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.