Abstract:
In a spread spectrum receiver, a first despread signal is produced by a despreading circuit corresponding to a first symbol rate. The despreading circuit is responsive to a command signal for subsequently producing a second despread signal corresponding to the second symbol rate. A symbol rate estimation circuit is provided for estimating, from the first despread signal, the transmitted symbol rate of the spread spectrum signal as one of the first and second symbol rates. If the transmitted symbol rate is estimated as the first symbol rate, the despreading circuit continues producing the first despread signal. If the transmitted symbol rate is estimated as the second symbol rate, the estimation circuit supplies the command signal to the despreading circuit to produce the second despread signal. A decoding circuit decodes the first and second despread signals.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to CDMA receivers and CDMA receiving methods. In particular, the present invention relates to a CDMA receiver in which blind rate transmission is used and the pseudonoise (PN) codes used for spreading at transmit sites and those used for despreading at receive sites are structured in hierarchical order. 
     2. Description of the Related Art 
     In a spread spectrum channel, receiving and demodulating a signal that has been subject to spread spectrum modulation requires that the same pseudonoise (PN) code sequence be generated in the receiver, and correlated with received signals to extract data symbol values. These PN code sequences are hierarchically structured so that a PN code sequence corresponding to a low symbol rate can be determined from a PN code sequence corresponding to a higher symbol rate. Spread spectrum signals are transmitted at a symbol rate which is selected from a plurality of predetermined symbol rates so that the symbol rate selected for a given frame may differ from the rate used in another frame. No information is transmitted to receivers regarding the transmitted symbol rate. Rather, it is up to the receivers to determine the transmitted symbol rate. This mode of transmission is called blind-rate transmission. 
     In the current blind-rate transmission where two symbol rates are used, the transmitted spread spectrum signal is correlated, at a receive site, with a PN code sequence that corresponds to the high symbol rate to produce a first despread signal and the despread signal is decoded and tested for error. If an error is detected, a second despread signal is produced corresponding to the lower symbol rate and decoded and tested again. If an error is detected again, an alarm is given. Since the transmitted symbol rate is unknown, the receiver would frequently attempt to repeat the decoding process whenever the transmitted symbol rate varies from one frame to another. Since the decoding process is usually provided by a forward error correction (FEC) decoder which is complex, the frequent attempts to decode despread signals place a significant burden on the FEC decoder, resulting in an increase both in decoding time and power consumption. This is particularly disadvantageous for mobile spread spectrum receivers. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a spread spectrum receiver and method that reduces the number of decoding processes. 
     The stated object is attained by estimating the transmitted symbol rate from a received spread spectrum signal. 
     According to a first aspect, the present invention provides a spread spectrum receiver for receiving a spread spectrum signal transmitted at one of first and second symbol rates, comprising. despreading circuitry for receiving the spread spectrum signal and initially producing therefrom a first despread signal corresponding to the first symbol rate, the despreading circuitry being responsive to a command signal for subsequently producing a second despread signal corresponding to the second symbol rate, symbol rate estimation circuitry for estimating, from the first despread signal, the transmitted symbol rate of the received spread spectrum signal as one of the first and second symbol rates and causing the despreading circuitry to continue producing the first despread signal if the transmitted symbol rate is estimated as the first symbol rate and supplying the command signal to the despreading circuitry if the transmitted symbol rate is estimated as the second symbol rate, and decoding circuitry for decoding the first and second despread signals produced by the despreading circuitry. 
     According to a second aspect, the present invention provides a method of receiving a spread spectrum signal transmitted at one of first and second symbol rates, comprising the steps of (a) despreading the spread spectrum signal to initially produce a first despread signal corresponding to the first symbol rate, (b) estimating, from the first despread signal, the transmitted symbol rate of the received spread spectrum signal as one of the first and second symbol rates, (c) repeating the step (a) if the transmitted symbol rate is estimated as the first symbol rate, ( d) producing a second despread signal corresponding to the second symbol rate if the transmitted symbol rate is estimated as the second symbol rate, and (e) decoding the first and second despread signals. 
     According to a third aspect, the present invention provides a method of receiving a spread spectrum signal transmitted at one of first and second symbol rates, comprising the steps of (a) producing a first despread signal corresponding to the first symbol rate from the received spread spectrum signal, (b) estimating, from the first despread signal, the transmitted symbol rate of the received spread spectrum signal as one of the first and second symbol rates, (c) if the transmitted symbol rate is estimated as the first symbol rate, repeating the step (a), (d) decoding the first despread signal and performing a test on the decoded signal, (e) if the test indicates that the decoded signal is invalid, producing a second despread signal corresponding to the second symbol rate, (f) decoding the second despread signal and performing a test on the decoded signal, (g) if the transmitted symbol rate is estimated as the second symbol rate, producing the second despread signal, and repeating the step (f), and (h) if the test indicates that the decoded signal is invalid, producing the first despread signal from the received spread spectrum signal, and decoding the first despread signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be described in further detail with reference to the accompanying drawings, in which: 
     FIG. 1 is a block diagram of a CDMA receiver according to a first embodiment of the present invention; 
     FIG. 2 is a flowchart of the operation of the controller of FIG. 1; 
     FIG. 3 is a block diagram of a CDMA receiver according to a second embodiment of the present invention; and 
     FIG. 4 is a flowchart of the operation of the controller of FIG.  3 . 
    
    
     DETAILED DESCRIPTION 
     At a transmit site of a spread spectrum communication system, spreading PN codes are used for spread spectrum modulation of transmit data symbols. The PN codes are structured in hierarchical order so that a spreading code whose code length equals the symbol length of lower-rate symbols can be determined from a spreading code whose code length equals the symbol length of higher-rate symbols. 
     A CDMA receiver of the present invention is shown in FIG. 1 as a receive site of the spread spectrum communication system to receive a digitally demodulated, spread spectrum signal. In a typical example, this signal has been subject to spread spectrum modulation using one of two predetermined spreading pseudonoise (PN) codes whose code lengths are equal to the symbol lengths of high- and low-rate symbols, respectively. Because of the hierarchical organized PN code sequences, the higher symbol rate is twice as high as the lower symbol rate. If 64 kilosymbols per second (ksps) is used for the higher rate then the lower symbol rate is 32 ksps. The spread spectrum signal is subject to digital modulation such as phase shift keying and the digitally modulated signal is transmitted. At the receive site, the transmitted signal undergoes digital demodulation. 
     In FIG. 1, the CDMA receiver includes a correlator  100 , where the digitally demodulated signal is despread and correlated with a despreading PN code sequence supplied from a PN code generator  101 . Correlator  100  determines a symbol value of the despread signal, representing the correlation of the input symbol with the PN code. The output of the correlator  100  is supplied to a forward error correction (FEC) decoder  104  through one of two ways, one via a direct route connected between the higher positions of a switch  102  and the other through a symbol rate converter  103  connected between the lower positions of the switch  102 . 
     FEC decoder  104  decodes the input signal at one of the high and low symbol rates. A cyclic redundant check (CRC) test circuit  105  is connected to the FEC decoder  104  to test for the presence or absence of an error in the decoded signal. 
     Switch  102  and the FEC decoder  104  are controlled by a controller  106  according the result of the test from the CRC test circuit  105 . 
     According to the present invention, the controller  106  further responds to the output of a symbol rate estimator  107  for controlling the switch  102  and decoder  104 . Symbol rate estimator  107  is connected to the output of correlator  100  to provide estimation of the transmitted symbol rate based on power values of a frame signal transmitted at the higher rate of the system, i.e., 64 ksps, derived from the symbol values S H  of the high symbol rate frame signal. 
     The power value A of a 64-ksps frame is given by Equation (1) and the power value B of a 32-ksps frame is given by Equation (2), as follows:              A   =       ∑     i   =   0       2      N                         {       S   H                     (   i   )       }     2               (   1   )               B   =       ∑     i   =   0       N   -   1                         [       {         S   H          (     2   ×   i     )       -       S   H                     (       2   ×   i     +   1     )         }     /   2     ]     2               (   2   )                                
     where i represents the i-th symbol and N is the total number of symbols transmitted by a frame. Power value A is multiplied by a factor α which is greater than 0 and equal to or smaller than 0.5. 
     Symbol rate estimator  107  compares the product α×A with the power value B and determines the transmitted symbol rate according to the result of the comparison as follows: 
     (1) If α×A is smaller than the power value B, the transmitted symbol rate is estimated as 32 ksps, and 
     (2) If α×A is equal to or greater than B, the transmitted symbol rate is estimated as 64 ksps. 
     Alternatively, consider a function of U(x), where x=S H (2×i)×S H (2×i+1). Note that U(x)=1, if x≧0 and U=0, if x&lt;0. The function U(x) is a parameter indicating an amount by which the transmitted symbols are aligned in phase with the 32-ksps symbols. Symbol rate estimation is based on the summation of the function U(x) with respect to all symbols transmitted in a frame interval to obtain a phase alignment value as given by Equation (3).              C   =       ∑     i   =   0       N   -   1                       U                   {     (         S   H          (     2   ×   i     )       ×     S   H                     (       2   ×   i     +   1     )       }                   (   3   )                                
     It is seen that the phase alignment value C is small if the transmitted symbol rate is high, and large otherwise. Specifically, the phase alignment value C is compared with a reference value β (where 0&lt;β≦N), and the estimator  107  produces the following results: 
     (3) If C is smaller than β, the transmitted symbol rate is estimated as 64 ksps, and 
     (4) If C is equal to or greater than β, the transmitted symbol rate is estimated as 32 ksps. 
     In the illustrated embodiment, the transmitted spread spectrum signal has been subject to PN modulation using one of two spreading codes corresponding respectively to the 64 ksps and 32 ksps symbol rates. On the other hand, the despreading PN. code sequence provided by the generator  101  to the correlator  100  is one that corresponds to the higher symbol rate. 
     If the symbol rate estimator  107  determines that the transmitted symbol rate is high, the controller  106  sets the switch  102  to the higher positions for coupling the output of correlator  100  direct to the FEC decoder  104 . If the symbol rate estimator  107  determines that the transmitted symbol rate is low, the controller  106  sets the switch  102  to the lower positions for coupling the output of correlator  100  to the symbol rate converter  103 . 
     By denoting the value of the i-th symbol of the 64-ksps transmission as S L (i) and the value of the i-th symbol of the 32-ksps transmission as S H (i), the following equation holds: 
     
       
           S   L ( i )= S   H (2 ×i )− S   H (2× i− 1)  (4) 
       
     
     Equation (4) indicates that the symbol value of the lower rate transmission can be determined from the symbol value of the higher rate transmission. As shown in FIG. 1, the symbol rate converter  103  includes a shift register  108  and a subtractor  109  to implement Equation (4). Specifically, when the symbol values S H (0) to S H (2i) from the correlator  100  are stored in the shift register  108 , the difference between symbol values S H (2i) and S H (2i−1) is determined by the subtractor  109  as a lower rate symbol value S L (i). 
     The operation of the controller  106  will now be described in detail below with the aid of a flowchart shown in FIG.  2 . 
     Controller  106  monitors the output of symbol rate estimator  107  and determines whether the estimated symbol rate is high or low (step  201 ). 
     If the estimated symbol rate is the higher rate value, flow proceeds to step  202  to set the switch  102  to the higher positions and command the FEC decoder  104  to decode the output of correlator  100  at the higher symbol rate. The signal decoded at the higher rate is then CRC tested by the test circuit  105 . 
     Controller  106  proceeds to step  203  to check to see if the result of the CRC test is a valid or an invalid indication. If the test indicates that no error exists in the decoded signal, the latter is delivered from the CRC test circuit  105  to the output terminal of the receiver and the controller terminates the routine. 
     If the CRC test indicates that an error is detected in the decoded symbols, flow proceeds from step  203  to step  204  to set the switch  102  to the lower positions and command the FEC decoder  104  to decode the output of the symbol rate converter  103  at the lower symbol rate. The signal decoded at the lower rate is then CRC tested by the test circuit  105 . 
     Controller  106  proceeds from step  204  to step  205  to check the result of the CRC test to see if the decoding at the lower symbol rate produces a valid or invalid output sequence. If no error exists in the decoded signal, the latter is delivered to the output terminal of the receiver and the controller  106  terminates the routine. If an error is detected in the decoded signal, it is determined that the receiver has failed to decode the transmitted signal and controller  106  proceeds from step  205  to step  206  to generate an alarm before terminating the routine. 
     Returning to step  201 , if the estimated symbol rate is the lower rate value, controller  106  proceeds to step  207  to set the switch  102  to the lower positions and command the FEC decoder  104  to decode the output of symbol rate converter  103  at the lower symbol rate. The signal decoded at the lower rate is then CRC tested by the test circuit  105 . 
     Controller  106  proceeds to step  208  to check to see if the result of the CRC test is a valid or an invalid indication. If the test indicates that no error exists in the decoded signal, the latter is delivered from the CRC test circuit  105  to the output terminal of the receiver and the controller terminates the routine. If the CRC test indicates that an error is detected in the decoded symbols, flow proceeds from step  208  to step  209  to set the switch  102  to the higher positions and command the FEC decoder  104  to decode the output of the correlator  100  at the higher symbol rate. The signal decoded at the higher rate is then CRC tested by the test circuit  105 . 
     Controller  106  proceeds from step  209  to step  205  to check the result of the CRC test to see if the decoding at the higher symbol rate produces a valid or invalid output sequence. If no error exists in the signal decoded at the higher rate, the latter is delivered to the output terminal of the receiver and the controller  106  terminates the routine. If an error is detected in the decoded signal, it is determined that the receiver has failed to decode the transmitted signal and controller  106  proceeds from step  205  to step  206  to generate an alarm before terminating the routine. 
     FIG. 3 is a block diagram of a modified embodiment of the present invention in which elements corresponding in significance to those in FIG. 1 are marked with the same numerals. In this modification, a variable-rate PN sequence generator  300  is provided, instead of the PN sequence generator  101  and symbol rate converter  103  of the previous embodiment, to supply one of the 64-ksps and 32-ksps symbol rates associated PN code sequences to the correlator  100 . Controller  301  controls the variable-rate PN sequence generator  300  according to the output of symbol rate estimator  107  as well as the valid/invalid result indication of the CRC test circuit  105 . 
     The operation of the controller  301  proceeds according to the flowchart shown in FIG.  4 . 
     Controller  301  monitors the output of symbol rate estimator  107  and determines whether the estimated symbol rate is high or low (step  401 ). If the estimated symbol rate is the higher rate value, flow proceeds to step  402  to command the PN sequence generator  300  to supply the higher-rate PN code sequence to the correlator  100  and command the FEC decoder  104  to decode the output of correlator  100  at the higher symbol rate. The signal decoded at the higher rate is then CRC tested by the test circuit  105 . 
     Controller  301  proceeds to step  403  to check to see if the result of the CRC test is a valid or an invalid indication. If the test indicates that no error exists in the decoded signal, the latter is delivered from the CRC test circuit  105  to the output terminal of the receiver and the controller  301  terminates the routine. 
     If the CRC test indicates that an error is detected in the decoded symbols, flow proceeds from step  403  to step  404  to command the PN sequence generator  300  to supply the lower-rate PN sequence to the correlator  100  and command the FEC decoder  104  to decode the output of the correlator  100  at the lower symbol rate. The signal decoded at the lower rate is then CRC tested by the test circuit  105 . 
     Controller  301  proceeds from step  404  to step  405  to check the result of the CRC test to see if the decoding at the lower symbol rate produces a valid or an invalid output sequence. If no error exists in the decoded signal, the latter is delivered to the output terminal of the receiver and the controller  301  terminates the routine. If an error is detected in the decoded signal, it is determined that the receiver has failed to decode the transmitted signal and controller  301  proceeds from step  405  to step  406  to generate an alarm before terminating the routine. 
     Returning to step  401 , if the estimated symbol rate is the lower rate value, controller  301  proceeds to step  407  to command the PN sequence generator  300  to supply the lower-rate PN sequence to the correlator  100  and command the FEC decoder  104  to decode the output of the correlator  100  at the lower symbol rate. The signal decoded at the lower rate is then CRC tested by the test circuit  105 . 
     Controller  301  proceeds to step  408  to check to see if the result of the CRC test is a valid or an invalid indication. If the test indicates that no error exists in the decoded signal, the latter is delivered from the CRC test circuit  105  to the output terminal of the receiver and the controller terminates the routine. If the CRC test indicates that an error is detected in the decoded symbols, flow proceeds from step  408  to step  409  where the controller  301  commands the PN sequence generator  300  to supply the higher rate PN sequence to the correlator  100  and command the FEC decoder  104  to decode the output of the correlator  100  at the higher symbol rate. The signal decoded at the higher rate is then CRC tested by the test circuit  105 . 
     Controller  301  proceeds from step  409  to step  405  to check the result of the CRC test to see if the decoding at the higher symbol rate produces a valid or invalid output sequence. If no error exists in the signal decoded at the higher rate, the latter is delivered to the output terminal of the receiver and the controller  301  terminates the routine. If an error is detected in the decoded signal, it is determined that the receiver has failed to decode the transmitted signal and controller  106  proceeds from step  405  to step  406  to generate an alarm before terminating the routine.