Abstract:
A system is described for time synchronizing digitized measurement signals, such as vibration signals. The digitized signals, which are acquired asynchronously by multiple distributed measurement units, indicate the operational condition of a machine or a process. To measure the phase of the digitized signals relative to a pulse tachometer input, the time between the leading edge of the tachometer pulse and the digitized samples is measured. To achieve phase-coherent synchronization across the distributed measurement units, a local synchronization signal is embedded into the data produced by the measurement units. The systems uses the synchronization signal to align the data in post processing, which phase aligns the data and aligns the data in absolute time. The synchronization signal may be encoded with a timestamp to provide additional timing information.

Description:
FIELD 
     This invention relates to time synchronization of vibration waveforms in the time domain using synchronization pulses. 
     BACKGROUND 
     In making measurements of vibration characteristics of a machine having rotating components, the phase of a vibration signal is generally defined as the angular relationship between an amplitude peak in the vibration signal and a once-per-revolution reference signal, such as produced by a tachometer sensor. 
     In most vibration measurement systems, the vibration signal from a vibration sensor is converted to a digital signal using an analog-to-digital converter (ADC). Generally, to attain an accuracy of one degree at a rotational speed of 2 KHz, this time measurement must fix the tachometer leading edge relative to the ADC samples with a resolution of better than one microsecond. 
     In situations in which data are collected by multiple data acquisition systems running asynchronously, the data acquisition processes are not synchronized, and there is no way to directly compare the phase of the data collected by the asynchronous systems. In such a case, even if the tachometer edges are aligned, a comparison of data from the two systems would still be skewed, especially during non-steady-state operation. 
     What is needed, therefore, is a system for accurately aligning tachometer pulses associated with vibration signal data collected by multiple data acquisition systems that are running asynchronously. 
     SUMMARY 
     In systems incorporating preferred embodiments of the present invention, to measure the phase of a digitized signal, such as a vibration signal, relative to a pulse tachometer input, the time between the leading edge of the tachometer pulse and the ADC samples is measured as depicted in  FIG. 1 . Generally, to attain an accuracy of one degree at a rotational speed of 2 KHz, this time measurement must fix the tachometer leading edge relative to the digitized signal samples with a resolution of better than one microsecond. 
     Using an external synchronization pulse, when data is re-aligned in post processing, the data is both phase aligned and correctly aligned in absolute time. To provide extra timing information, it is possible to encode synchronization signals using a count code or timestamp. 
     To achieve phase coherent synchronization across distributed units, two additional functions are required. First a method must be added to embed a local synchronization signal into the data being produced by the data acquisition unit. Second, a method must be added to align the (asynchronous) synchronization signals across distributed units. 
     Some embodiments of the invention described herein provide an apparatus for time synchronizing measurement signals that are indicative of an operational condition of a machine or process. A preferred embodiment of the apparatus comprises at least a first measurement device and a second measurement device that are acquiring measurement signals asynchronously, and a host processor synchronizing and processing the measurement signals. 
     The measurement device includes a sensor, an ADC clock, a analog-to-digital converter, a tachometer sensor, a synchronization clock source, a signal processor, and a media access controller. The sensor is attached to the machine or process and generates a analog measurement signal. The ADC clock generates a ADC clock signal. The analog-to-digital converter receives the ADC clock signal and the analog measurement signal and generates a digital measurement signal. The tachometer sensor is attached to the machine or process and generates a tachometer signal comprising tachometer pulses. The synchronization clock source generates a synchronization signal comprising synchronization pulses. 
     The signal processor, which is preferably a Signal Processing FPGA, performs synchronization timing by measuring time between several inputs. A time delay is measured from the sync pulse edge to the next ADC sample. This delay measurement consists of the number of ADC clock cycles between the sync pulse and ADC sample. This measurement establishes a reference from the sync pulse to the ADC clock. A delay time is calculated from the sync pulse to the next filtered output data sample produced by the Signal Processing FPGA. This determines the total signal processing delay, including the group delay of the ADC and the group delay of the digital filters employed by the Signal Processing FPGA. A time delay is measured between the sync pulse edge and any tachometer pulses that occur within the sync pulse interval. 
     The sync pulse is also connected to the trigger input of an IEEE1588 Media Access Controller (MAC) of the host processor. Each sync pulse latches the current count of the IEEE1588 timer. IEEE1588 operates by synchronizing high speed counters in various devices on an IEEE1588 network. These counters are implemented in the Ethernet MAC (Media Access Controller) which supports this feature. Since these counters are all synchronized to the same global clock, these timers may be used as a timing reference between systems. In the Machinery Health Management (MHM) system, the synchronization pulse utilized by the Signal Processing FPGA is also fed to the trigger input of the IEEE1588 MAC. When the pulse is detected, the current IEEE1588 counter value is latched by the IEEE1588 MAC. The host processor may now read this latched timer value from the IEEE1588 MAC and construct a data record of synchronization pulses and IEEE1588 timestamps. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other embodiments of the invention will become apparent by reference to the detailed description in conjunction with the figures, wherein elements are not to scale so as to more clearly show the details, wherein like reference numbers indicate like elements throughout the several views, and wherein: 
         FIG. 1  depicts a phase measurement between a digitized signal and a tachometer pulse; 
         FIG. 2  depicts a data acquisition system for synchronizing data across distributed devices; 
         FIG. 3  depicts data processing performed by a signal processing FPGA to support synchronization; 
         FIG. 4  depict waveform, tachometer and timestamp data structures showing embedded synchronization timing; and 
         FIG. 5  depicts data alignment across distributed devices. 
     
    
    
     DETAILED DESCRIPTION 
     An exemplary system  10  for producing synchronized vibration information is shown in  FIG. 2 . In a preferred embodiment, the system shown incorporates multiple measurement devices referred to herein as Device M and Device N. Although only two measurement devices are depicted in  FIG. 2 , it will be appreciated that more than two measurement devices may be incorporated into the system  10 . 
     The measurement device N includes one or more analog sensors  12 , one or more tachometer sensors  14 , signal conditioning circuitry  16 , one or more sensor power sources  18 , one or more analog-to-digital converters (ADC)  20 , one or more ADC clock sources  22 , a synchronization clock source  28 , a signal processor  26 , which in a preferred embodiment is a field programmable gate array (FPGA), a host CPU  30 , and an Ethernet media access controller (MAC)  32  compatible with IEEE1588, including an external trigger input. The Ethernet MAC  32  is connected to an IEEE1588 Ethernet network  34 . 
     The analog sensors  12  are preferably sensory detection devices that translate sensory information into an electric voltage or an electric current. Analog sensors or other transducers suitable for use in the present invention may include various kinds For example, they may measure a machine or a process or an environment vibration, such as is commonly done using an eddy current probe or an accelerometer. These are examples of analog sensors  12  of preferred embodiments. Alternative embodiments of analog sensors  12  measure a machine or a process or an environment around a machine or a process, such as a motor current signature, a passive or a pulse-echo ultrasonic measure, a magnetic flux signature, a temperature, a pressure, a flow, a mass, a relative humidity, a load, a density, a composition, a physical property, a chemical property, an electrical property, a magnetic property, an optical property, or an electromagnetic property. Analog sensors  12  of preferred embodiments may be passive or active detector types. 
     The tachometer sensors  14  may comprise rotational encoders, linear encoders, or other devices that discern a coordinate or a position or a rate of change. However, it is not necessary for all distributed units to use the tachometer input as discussed in more detail hereinafter. 
     Other digital data sources may include digital data streams, such as a process characteristic or measure, a control aspect or status, a switching event such as an initiation of a switch or a valve opening or closure, a measure of loading or power or energy or other operational information, an adaptive logic related characteristic, or other input that relates to or supports parallel synchronized data streams. These other digital data streams may incorporate a tachometer, encoder, beacon, timestamp, or other synchronization related information. 
     In a preferred embodiment, the signal processors  26  are field programmable gate arrays (FPGAs), which are particularly valuable for highly precise synchronization due to its speed of processing, speed of parallel channel configuration, and speed of parallel channel reconfiguration. The FPGA is a flexible field programmable and reconfigurable processor that is operable to switch back and forth between selectable high-pass to low-pass to band-pass signal filter settings, to switch between multiple decimation rates, to perform selective decimation such as PeakVue™, and to perform digital integration or differentiation as needed. In accordance with preferred embodiments of the present invention, the FPGA does all these things with precise synchronization between data streams from different devices, sources, and geographic locations. Various signal processing techniques are suitable for processing in the present invention, including but not limited to decimation, selective decimation, and anti-aliasing, as disclosed by Garvey, et. al., in “SELECTIVE DECIMATION AND ANALYSIS OF OVERSAMPLED DATA”, U.S. patent application Ser. No. 14/252,943, filed Apr. 15, 2014, the entire contents of which are incorporated herein by reference. 
       FIG. 3  depicts an example of the data processing performed by the signal processor FPGAs  26  to enable synchronization. The FPGAs  26  perform synchronization timing by measuring time between the several inputs, including:
         Waveform (ADC) data  40 ;   ADC clock signal(s)  48 ;   Synchronization pulses  42 ; and   Tachometer pulses  44 .
 
When the periodic synchronization pulse  42  is detected by the FPGA  26 , several measurements are performed as shown in  FIG. 3 .
   A delay time  46  is measured from the synchronization pulse edge  42  to the next input ADC clock edge  48 . This measurement establishes a reference from the synchronization pulse  42  to the ADC clock edge  48 .   A delay time is calculated from the synchronization pulse  42  to the next filtered output data sample  48  produced by the FPGA  26 . This determines the total signal processing delay, including the group delay of the ADC  20  and the group delay of digital filters employed by the FPGA  26 .   A delay time is measured between the synchronization pulse edge  42  and any subsequent tachometer pulses.       

     These offset times, which are embedded into the time waveform data as shown in  FIG. 4 , allow the calculation of phase between a signal and any local tachometer. In addition, a synchronization reference can be embedded in the data that allows synchronization across distributed devices. 
     The time delay (DeltaT) between the filtered data sample and the tachometer pulse edge is calculated as follows. 
     Time from Sync pulse  42  to filtered sample:
 
 T 1 =T sync+( T ADCdelay+ T PhaseDelay)
 
     Time from Sync pulse  42  to tachometer edge  44 :
 
 T 2 =T sync+ T TachOffset
 
Delta T=T 1− T 2=( T ADCdelay+ T PhaseDelay)− T TachOffset
 
     To provide synchronization between devices, an IEEE1588 timestamp is added to the data. This is accomplished using an IEEE1588 subsystem that supports an external trigger input. The IEEE1588 subsystem synchronizes high-speed counters in various devices on the IEEE1588 network  34 . These counters are implemented in the Ethernet MAC  32  that supports this feature. Since these counters are all synchronized to the same global clock, these timers may be used as a timing reference between systems. 
     In preferred embodiments, the synchronization pulse  42  utilized by the FPGA  26  is also fed to the trigger input of the IEEE1588 Ethernet MAC  32 . When the pulse is detected, the current IEEE1588 counter value is latched by the MAC  32 . The host processor  30  may read this latched timer value from the MAC  32  and construct a data record of synchronization pulses and IEEE1588 timestamps as depicted in  FIG. 4 . 
     As shown in  FIG. 5 , data across devices (such as Device M and Device N) may be aligned using the IEEE1588 timestamp values to calculate the difference in time between the synchronization clocks on distributed devices. To align synchronization time across devices, the following calculation is performed:
 
Sync delay  M =IEEE1588 Time  N −IEEE1588 Time  M  
 
     This synchronization time delay is added to all Device M data to align Device M data with the Device N synchronization pulse. When this correction has been made, data from the various devices may be aligned in time, allowing phase coherent analysis. 
     It should be noted that a local tachometer is no longer required to perform a phase measurement. Using the synchronization method, tachometer data collected by any device on the network  34  may be used as a phase reference by any device on the network  34 . 
     In addition to enabling phase and orbit plotting and analysis, embodiments described herein support calculations of covariance and correlation analysis, as well as calculations and reporting for various types of parameters, such as the following machine vibration related parameters. Parameter marked with an asterisks (*) in the list below require two inputs for cross-channel calculations and graphical representations including orbits. 
     Exemplary Output Parameters:
         a. Total energy   b. Energy in a frequency band   c. Waveform Peak Value   d. Waveform Peak-to-Peak Value   e. Waveform 0-Peak Value   f. RMS of Waveform   g. SMAX*   h. SMAX p-p*   i. SMAX Change Vector*   j. nX Peak (up to 10 orders of turning speed)   k. nX Phase (up to 10 orders of turning speed)   l. Speed   m. Peak of Speed   n. Rotor Acceleration   o. Peak of PeakVue   p. Position   q. Absolute Position*   r. Thrust   s. Eccentricity   t. DC Gap   u. Scaled DC Gap (NGL)   v. Bias Voltage   w. Synchronous energy in a frequency band   x. Non-Synchronous energy in a frequency band   y. Relative synchronous harmonics   z. Variance of time waveform   aa. Skewness of time waveform   bb. Kurtosis of time waveform   cc. High frequency detection   dd. Variable high frequency detection   ee. Crest factor       

     The foregoing description of preferred embodiments for this invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiments are chosen and described in an effort to provide the best illustrations of the principles of the invention and its practical application, and to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.