Abstract:
A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    This invention relates generally to the cell structure and fabrication process of power semiconductor devices. More particularly, this invention relates to a novel and improved cell structure and improved process for fabricating a LDMOS (Laterally Diffused MOS transistors) with double LDD (Lightly Doped Drain) and trenched drain structure to provide a low resistance path for the current with enhanced FOM characteristic. 
         [0003]    2. The Prior Arts 
         [0004]    In U.S. Pat. No. 7,282,765, a LDMOS transistor cell with substrate having a first N semiconductor doping type of prior art was disclosed, as shown in  FIG. 1 . The transistor cell structure comprises: a highly N+ doped substrate  100  onto which formed a lightly doped epitaxial layer  102  having dopants of N or P dopant type; a body region  104  having P type dopants within which implanted an N+ source region  106 ; a LDD region  108  formed into epitaxial layer  102  while adjacent to the top surface of said epitaxial layer; a vertical drain contact region  110  where current flows through; a deep trench region  112  for the formation of vertical drain contact region  110  while its open; conductive gate including a doped polysilicon layer  114  and an upper silicide layer  115  formed over a gate dielectric  113 ; an insulating layer  116  covering the source region  106 , the conductive gate sidewalls and its upper surface, and the LDD region  108 . The illustrated structure further comprises a shallow trench region  118  by which body region  104  and source region  106  are connected to source metal  119 , while a body contact doping region  117  having a dopant concentration P++ greater than the concentration of body region is introduced to reduce the resistance between body region and source metal. 
         [0005]    As analyzed in prior art, the LDD region  108  increases the drain-to-source breakdown voltage (BV) of the LDMOS due to its lower doping concentration. However, the low concentration of drain region can not provide a low resistance path for current flow, that means the on resistance between drain and source (Rdson) is large due to low doping concentration in drain region, which will lead to a large conduction loss. Therefore, it is necessary to make a compromise between breakdown voltage and Rdson to optimize the device performance. 
         [0006]    Another disadvantage of the prior art is that, there is a high parasitic resistance R L   109  between surface of the LDD region  108  and N+ region  110  connected to bottom of LDD region  108  due to the lower doping concentration, causing high Rdson between drain and source. 
         [0007]    Another disadvantage of the prior is that, a parasitic bipolar N+PN in the prior art is easily triggered on due to existence of high base resistance R B   111  underneath source region  106 , resulting in device destroy. 
         [0008]    Accordingly, it would be desirable to provide a new LDMOS cell structure with low on-resistance between the source region and drain region while sustaining a high breakdown voltage without triggering on the parasitic bipolar. 
       SUMMARY OF THE INVENTION 
       [0009]    It is therefore an object of the present invention to provide new and improved LDMOS cell and manufacture process to reduce the on resistance and increase breakdown voltage, while remaining a lower fabricating cost. 
         [0010]    One aspect of the present invention is that, as shown in  FIG. 2 , and  FIGS. 4 to 8 , after the LDD-N1 implantation for the formation of drift drain region with a higher energy, another low energy LDD implantation with a higher doping concentration is introduced above said LDD-N1 region with the same mask to form LDD-N2. By employing the double LDD structure, the low energy implantation provides a low on-resistance path for the current flow, while the high energy implantation forms a lightly doped region to sustain a high breakdown voltage.  FIG. 3  shows doping profile of the double LDD in comparison with the single LDD in prior art. The simulation result of Rdson when Vg=10V is shown in Table 1, its value is reduced to about 41% comparing to the prior art in  FIG. 1 . Besides this, when considering the FOM (Figure of Merit) value which is defined by Rdson times Qg, it also can be seen from Table 1 that, the structure of the present invention is well optimized by reducing the FOM to 61% of prior art, thus a successfully compromise is achieved by employing the present invention. 
         [0000]    
       
         
               
             
               
               
               
               
               
               
             
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Simulated Parameters when Vgs = 10 V 
               
             
          
           
               
                   
                   
                   
                   
                   
                 FOM 
               
               
                   
                 BV 
                 Rdson 
                 Qgd 
                 Qg 
                 (Rdson * Qg) 
               
               
                 Device 
                 (V) 
                 (mohm · mm 2 ) 
                 (nC/mm 2 ) 
                 (nC/mm 2 ) 
                 (mohm · nC) 
               
               
                   
               
             
          
           
               
                 Single 
                 20 
                 10 
                 0.5 
                 2.2 
                 22 
               
               
                 LDD 
               
               
                 Double 
                 25 
                 5.9 
                 1.1 
                 1.9 
                 11.2 
               
               
                 LDD 
               
               
                   
               
             
          
         
       
     
         [0011]    Another aspect of the present invention is that, as shown in  FIG. 2 , and  FIGS. 3 to 8 , before the source implantation, a step of P+ implantation for the formation of avalanche improved region is carried out with a concentration from 1E18 to 5E19 atoms/cm 3  to form a P+ area underneath source region for reducing the base resistance in the parasitic bipolar. 
         [0012]    Another aspect of the present invention is that, in some preferred embodiments, as shown in  FIGS. 4 ,  6 , and  8 , Vth (threshold voltage) of the LDMOS is adjusted by Ion Implantation in channel region with dopant opposite to body region, e.g., N type dopant. The Rdson can be reduced further without having punch-through issue. 
         [0013]    Another aspect of the present invention is that, in some preferred embodiments, as shown in  FIG. 5  and  FIG. 6 , in order to reduce contact dimension, trench source-body contact structure which is same as the prior art, is employed to take place of traditional planar contact as used in  FIG. 2  and  FIG. 4 . 
         [0014]    Another aspect of the present invention is that, as shown in  FIG. 7  and  FIG. 8 , the contact CD can be further shrunk with filling tungsten plug into the source-body contact trench and metal step coverage is also thus significantly improved. 
         [0015]    Another aspect of the present invention is that, as no additional mask is required to implement the LDD-N2 implantation and P+ area during fabricating process, the device has better performance of high BV and low Rdson than the prior art without extra fabrication cost. 
         [0016]    Briefly, in a preferred embodiment, as shown in  FIG. 2 , the present invention disclosed a LDMOS cell comprising: a substrate having a first conductivity doping type, e.g., N doping type, with a resistivity of less than 3 mohm-cm onto which a lightly doped epitaxial layer with a second conductivity doping type is grown, e.g., P doping type; a body region of P doped formed inside said epitaxial layer near the upper surface, within which an N+ source region is formed above the P+ avalanche improved region; LDD-N1 region implanted within said epitaxial layer adjacent to said body region and separated from said source region by channel region; LDD-N2 region implanted near the top surface of LDD-N1 region to further reduce the path resistance for current flow; a conductive gate formed onto a first insulating layer over channel region and partially covers source region, LDD-N1 and LDD-N2 region with a layer of silicide thereon; a first trench serving as drain contact trench opened through said epitaxial layer adjacent to LDD region to enable the formation of drain contact region and filled with doped poly, Ti/TiN/W or Co/TiN/W plug; a highly N+ doped region surrounding sidewall of the drain contact trench and connecting the LDD-N1 and LDD-N2; a second insulating layer covering the source region, the conductive gate sidewalls and its upper surface, and the LDD region; P++ body contact doping region next to said source region near the top surface of body region above P+ avalanche improved region to provide a low resistance contact between front metal and body region; source metal formed over said second insulating layer to contact source region and said P++body contact doping region laterally. 
         [0017]    Briefly, in another preferred embodiment, as shown in  FIG. 4 , the present invention disclosed a similar LDMOS cell to structure in  FIG. 2  except that, the channel region of cell structure in  FIG. 4  was Ion Implanted with dopant of opposite doping type to body region to adjusted Vth to a lower value for Rdson reduction. 
         [0018]    Briefly, in another preferred embodiment, as shown in  FIG. 5 , the present invention disclosed a similar LDMOS cell to structure in  FIG. 2  except that, a second trench serving as source-body contact trench is etched through said second insulating layer and said source region, and into said the P+ avalanche improved region or through P+ avalanche improved region into P body region. Accordingly, said P++ body contact doping region area is formed around the bottom of said second trench to provide a low resistance contact between body region and source metal filled into said second trench. 
         [0019]    Briefly, in another preferred embodiment, as shown in  FIG. 6 , the present invention disclosed a similar LDMOS cell to structure in  FIG. 5  except that, the channel region of cell structure in  FIG. 6  was Ion Implanted with dopant of opposite doping type to body region to adjusted Vth to a lower value for Rdson reduction. 
         [0020]    Briefly, in another preferred embodiment, as shown in  FIGS. 7 and 8 , the present invention disclosed a similar LDMOS cell to structures in  FIGS. 5 and 6 , respectively. The devices further comprises the source-body contact trench padded with a barrier layer composed of Ti/TiN or Co/TiN and filled with tungsten contact plugs for contacting the body regions and source regions. Each of these source contact trenches further are extended into body regions having a body contact doping region implanted below the contact trenches to reduce the contact resistance. The top surface of the second insulation layer is covered with a metal resistance-reduction interlayer composed of Ti or Ti/TiN for reducing contact resistance between the tungsten plug and source metal. 
         [0021]    These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0022]    The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein: 
           [0023]      FIG. 1  is a side cross-sectional view of a LDMOS cell of prior art. 
           [0024]      FIG. 2  is a side cross-sectional view of a preferred embodiment in accordance with the present invention. 
           [0025]      FIG. 3  is doping profile comparison between single LDD and double LDD. 
           [0026]      FIG. 4  is a side cross-sectional view of another preferred embodiment in accordance with the present invention. 
           [0027]      FIG. 5  is a side cross-sectional view of another preferred embodiment in accordance with the present invention. 
           [0028]      FIG. 6  is a side cross-sectional view of another preferred embodiment in accordance with the present invention. 
           [0029]      FIG. 7  is a side cross-sectional view of another preferred embodiment in accordance with the present invention. 
           [0030]      FIG. 8  is a side cross-sectional view of another preferred embodiment in accordance with the present invention. 
           [0031]      FIGS. 9A to 9D  are a serial of side cross sectional views for showing the processing steps for fabricating LDMOS cell in  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0032]    Please refer to  FIG. 2  for a preferred embodiment of the present invention. The shown LDMOS cell is formed on an N+ substrate  200  onto which grown a P− epitaxial layer  202  wherein P body region  204  is implanted. Source region  206  is formed near the top surface of P body region  204  with a P+ avalanche improved region  217  underneath using the same source mask. Adjacent to LDD-N1 region  208  and LDD-N2 region  209  which is implanted successively near the top surface of epitaxial layer, a first trench is etched through epitaxial layer and filled with doped poly, Ti/TiN/W or Co/TiN/W as drain contact metal plug  212 . A highly doped region  210  of N+ doping type is formed next to said drain contact underneath LDD-N1 region to provide a low resistance path for current flow. Above a first insulating layer, which serves as gate oxide layer  213 , conductive gate  214  is formed over channel region with a layer of silicide  215  thereon, partially overlaps source region  206 , LDD-N1 region  208  and LDD-N2 region  209 . Source metal  219  is deposited on a second insulating layer  216  and contact source region  206  and body region  204  laterally through a P++ body contact doping region  218  which reduces the resistance between body region and front source metal. 
         [0033]      FIG. 4  shows another preferred embodiment of the present invention. Comparing to  FIG. 2 , the channel region  420  of the structure in  FIG. 4  is Ion Implanted with dopant of opposite doping type to body region to reduce the threshold voltage. 
         [0034]      FIG. 5  shows another preferred embodiment of the present invention. Comparing to  FIG. 2 , the structure in  FIG. 5  has a second trench etched through said second insulating layer  516 , said source region  506  and into the P+ avalanche improved region  517  to serve as source-body contact trench. Around the bottom of said second trench, a P++ body contact doping region  518  is accordingly formed to reduce the resistance between body region  504  and front source metal  519 . 
         [0035]      FIG. 6  shows another preferred embodiment of the present invention. Comparing to  FIG. 5 , the channel region  620  of the structure in  FIG. 6  is Ion Implanted with dopant of opposite doping type to body region to reduce the threshold voltage. 
         [0036]      FIGS. 7 and 8  show another preferred embodiments of the present invention. Comparing to  FIGS. 5 and 6 , the source-body contact trench is filled with Tungsten plug padded with a barrier layer composed of Ti/TiN or Co/TiN. The top surface of the second insulation layer is covered with a metal resistance-reduction interlayer composed of Ti or Ti/TiN for reducing contact resistance between the tungsten plug and the source metal. 
         [0037]      FIGS. 9A to 9D  show a series of exemplary steps that are performed to form the inventive LDMOS of the present invention shown in  FIG. 5 . In  FIG. 9A , a P− doped epitaxial layer  502  is grown on an N+ substrate  500 , e.g., Arsenic doped substrate, then, a trench mask (not shown) is applied, which is then conventionally exposed and patterned to leave mask portions. The patterned mask portions define the first trench  512 ′, which is dry silicon etched through mask to the interface between substrate and epitaxial layer. Next, a sacrificial oxide (not shown) is grown and then removed to eliminate the plasma damage may introduced during trenches etching process. After the trench mask removal, an angle As implantation is carried out above first trench  512 ′ with ±3 degree respecting to top surface of epitaxial layer to form the N+ region  510  adjacent to said first trench, as shown in  FIG. 9B . Next, doped poly, Ti/TiN/W or Co/TiN/W plug is deposited into trench  512 ′ to form drain contact plug  512  and is then CMP (Chemical Mechanical Polishing) or etched back to expose the epitaxial layer. After that, P body implantation is carried out above P body mask (not shown) to form body region  504 . Refer to  FIG. 9C , a first insulating layer, doped poly and silicide layer are deposited successively onto the top surface of epitaxial layer and then etched back to form gate oxide  513  and conductivity gate  514  with silicide  515  thereon. Then, a high energy LDD Arsenic or Phosphorus implantation with 150-300 KeV and 1E115E11 cm −3  dose; and low energy LDD Arsenic or phosphorus implantation with 60˜100 KeV and 1E12˜5E12 cm −3  dose are successively continued to form LDD-N1 region  508  and LDD-N2 region  509  followed by a step of LDD anneal process. Next, with the same source mask (not shown), Boron implantation is applied to form P+ avalanche improved region  517 , followed by Arsenic implantation for the formation of source region  506  and a step of source anneal. After that, in  FIG. 9D , a second insulating layer  516  is deposited along the whole surface of device onto which formed source contact mask (not shown) for the etching of second trench by dry oxide etching through second insulating layer  516  and dry silicon etching through source region  506  and into P+ avalanche improved region  517 . Above the second trench, BF2 Ion Implantation is implemented to form the P++body contact doping region  518  around the bottom of said second trench. At last, source metal  519  is deposited filling the second trench and covering the second insulating layer  516 . 
         [0038]    Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.