Abstract:
A method of detecting two bits of data transmitted with a single clock edge includes the step of assessing the value of a first data bit and a second data bit transmitted with a single clock edge to generate a first output bit indicative of the value of said first data bit. The assessing step may be implemented by integrating the first data bit and the second data bit, or by identifying signal transitions between the first data bit and the second data bit. The second output bit is produced by simply passing the second data bit.

Description:
BRIEF DESCRIPTION OF THE INVENTION 
     This invention relates generally to the transfer of data in digital systems. More particularly, this invention relates to a high throughput data transfer technique. 
     BACKGROUND OF THE INVENTION 
     It is well known to transmit bits of data between integrated circuit components according to a system clock. Typically, one data bit is transmitted on each clock edge, whereby sampling may occur on the rising or falling edge of the clock signal. Continuing improvements in microprocessor design allow for faster clock speeds, which allow for greater data transmission rates. However, there are practical constraints associated with increasing clock speeds. For example, faster clock speeds result in larger power consumption, thermal dissipation problems, and increased electromagnetic interference. 
     In view of the foregoing, it would be highly desirable to more fully utilize existing clock speeds. That is, it would be highly desirable to transport more information in response to a clock edge. Such a technique would allows improved processing speeds without increasing clock speed. 
     SUMMARY OF THE INVENTION 
     A method of detecting two bits of data transmitted with a single clock edge includes the step of assessing the value of a first data bit and a second data bit transmitted with a single clock edge to generate a first output bit indicative of the value of the first data bit. The assessing step may be implemented by integrating the first data bit and the second data bit, or by identifying signal transitions between the first data bit and the second data bit. The second output bit is produced by simply passing the second data bit. 
     A circuit to detect two bits of data transmitted with a single clock edge includes a first circuit module to assess the value of a first data bit and a second data bit transmitted with a single clock edge. The first circuit module generates a first output bit indicative of the value of the first data bit. A second circuit module passes the value of the second data bit to produce a second output bit. 
     The technology of the invention more fully utilizes existing clock speeds by transporting two bits of data every clock edge without using multi-level signaling. Thus, more information is transported in response to a clock edge signal. The technique allows improved processing speeds without increasing clock speed. Advantageously, the invention can be implemented using standard components and is otherwise compatible with most circuit architectures. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a better understanding of the invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 illustrates an embodiment of a master/slave system, such as a computer system, configured in accordance with an embodiment of the invention. 
     FIG. 2 illustrates a circuit for detecting two data bits on a clock edge in accordance with a first embodiment of the invention. 
     FIG. 3 illustrates combinatorial logic that is used in connection with the circuit of FIG.  2 . 
     FIG. 4 is a timing diagram illustrating how the circuit of FIG. 2 processes various signals. 
     FIG. 5 illustrates a circuit for detecting two data bits on a positive clock edge in accordance with an embodiment of the invention. 
     FIG. 6 illustrates a circuit for detecting two data bits on a negative clock edge in accordance with an embodiment of the invention. 
     FIG. 7 is a timing diagram illustrating how the circuit of FIG. 5 processes various signals. 
     FIG. 8 is a timing diagram illustrating how the circuit of FIG. 6 processes various signals. 
     FIG.  9 . illustrates a circuit for detecting two data bits on a clock edge in accordance with another embodiment of the invention. 
    
    
     LIKE REFERENCE NUMERALS REFER TO CORRESPONDING PARTS THROUGHOUT THE DRAWINGS 
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 illustrates a master/slave system  1  with a master device  10  and a set of slave devices  20 . By way of example, the master device  10  may be a memory controller and the set of slave devices  20  may be memory devices. The memory controller may form a portion of a central processing unit or other component. The memory devices may be DRAMs, SRAMs, or the like. Signal lines  30  form a bus that allows communication between the master device  10  and the set of slave devices  20 . The master device  10  includes an interface  11  for transmitting data to the slave devices  20  and for receiving data from the slave devices  20 . Each slave device  20  includes an interface  21  for receiving data from the master device  10  and for transmitting data to the master device  10 . 
     The present invention is directed toward an interface (e.g., the master device interface  11  or slave device interface  21 ) which allows the reception of two bits of data with a single clock transition. FIG. 2 illustrates a first embodiment of the invention. The basic principle of operation for the embodiment of FIG. 2 is to process both transmitted bits to determine whether the two transmitted bits are in a first group with a bit sequence of 00 or 11, or in a second group with a bit sequence of 01 or 10. Thereafter, either the first sampled bit or the second sampled bit is used to decide within the first group whether the bit sequence is 00 or 11 or decide within the second group whether the bit sequence is 01 or 10. 
     FIG. 2 illustrates a circuit  21  for processing data on a signal line. The circuit  21  is provided for each signal line connected to the interface circuit. The circuit  21  includes a first circuit portion  21   a  for processing data associated with a first clock edge and a second circuit portion  21   b  for processing data associated with a second clock edge. For the purpose of simplicity, the following discussion focuses on the first circuit portion  21   a . The second circuit portion  21   b  operates in the same manner but in response to a different clock edge. 
     Data received at the circuit portion  21   a  is compared to a reference voltage V REF  via a comparator circuit  22   a . The comparator circuit  22   a  provides a level shifted data signal DATA. The clock signal CLK 1  is routed to circuit portion  21   a , and the complementary clock signal CLK 1 !, generated by logically inverting the clock signal CLK 1  via an inverter  29 , is provided to complementary circuit portion  21   b . As demonstrated below, circuit portion  21   a  detects two data bits during the first half of the clock CLK 1  cycle, i.e., when the clock signal CLK 1  is high, and the circuit portion  21   b  detects two data bits during the second half of the clock CLK 1  cycle, i.e., when the complementary clock signal CLK 1 ! is high. 
     The signal DATA from the comparator  22   a  is provided as an input signal to a conventional integrator circuit  23   a . The DATA signal is also applied to a transmission gate  24   a . The transmission gate  24   a  may be implemented as a single transistor, with its gate controlled by the clock signal CLK 1 . As shown in FIG. 2, the integrator  23   a  and the transmission gate  24   a  are each clocked by the clock signal CLK 1 . 
     The integrator  23   a  provides an output voltage that is proportional to the length of time that the two bit input data signal is in a logical high state. The analog output voltage of the integrator  23   a  is applied to the positive terminals of comparators  25   a  and  26   a . Reference voltages V 1  and V 2  are provided to the negative input terminals of the comparators  25   a  and  26   a . In one embodiment, reference voltages V 1  and V 2  are approximately 2.5 volts and 2.0 volts, respectively. The comparator  26   a  outputs a logical high signal when the analog output from the integrator  23   a  corresponds to a digital input signal sequence of 01 or 10. Otherwise, a logical low signal is produced by the comparator  26   a . The comparator  25   a  outputs a logical high signal when the analog output from the integrator  23   a  corresponds to a digital input signal sequence of 11, and otherwise outputs a logical low signal. 
     The comparators  25   a  and  26   a  provide digital output signals A and B to a combinatorial logic circuit  28   a . The transmission gate  24   a  provides an output signal D to the logic circuit  28   a . The logic circuit  28   a  logically combines signals A, B, and D to produce a first output data bit B 0  and a second output data bit B 1 . As shown in FIG. 3, logic circuit  28  performs the following logical operation B 0 =A+B*D! and B 1 =D. 
     The components of the complementary circuit portion  21   b  are similarly configured, as shown in FIG. 2, to determine the two data bits on the following half-cycle of the clock, i.e., when the clock signal CLK 1  is low (and, thus, when the clock signal CLK 1 ! is high). 
     The operation of the circuit of FIG. 2 is more fully appreciated with reference to the timing diagrams of FIG.  4 . FIG. 4 illustrates a clock signal CLK. A clock signal with half the frequency, CLK 1 , is also shown in FIG.  4 . Further, a clock signal that is inverted and is at half the frequency of the clock signal CLK, CLK 1 !, is shown in FIG.  4 . Circuit portion  21   a  operates in response to the CLK 1  clock, while circuit portion 2 lb operates in response to the clock CLK 1 ! 
     FIG. 4 also illustrates a random data waveform (DATA). During a first half-cycle or first clock edge of the CLK 1  signal, a digital high data bit and a digital low data bit is processed by the circuit portion  21   a . The digital input signal pattern of 10 causes the integrator  23   a  to produce a corresponding analog voltage signal. The comparator  26   a  responds to this analog voltage signal by producing a digital high output signal “B”, as shown with arrow  30 . Comparator  25   a  generates a digital low signal, unless the analog voltage signal from the integrator  23   a  corresponds to a digital input pattern of 11. Since such a pattern does not exist in this example, the signal “A” from the comparator  25   a  remains in a digital low state. In sum, the digital signal input pattern of 10 produces an output signal of A=0 and B=1 after a half-cycle of the clock signal CLK 1 . 
     As shown with arrow  32 , the signal “D” follows the input signal. Thus, during the first half-cycle of the CLK 1  signal, the signal “D” is digital high, and then digital low (i.e, a binary 10). Therefore, at the end of the half-cycle, the value “D” is a digital low signal. In sum, at the end of the first half-cycle, the combinatorial logic  28   a  processes the following signals: A=0, B=1, and D=0. As shown with respect to FIG. 3, this input signal pattern results in output signals of B 0 =1 and B 1 =0, which is the same as the input signal pattern. Arrow  34  illustrates the signal transition for signal B 0 . 
     The circuit portion  21   b  is active during the next half-cycle of the clock. That is, when CLK 1 ! has a digital high value. During this half-cycle, a digital signal input pattern of 10 is once again processed. Since the circuit portion  21   b  operates in the same manner and the input signal is the same as in the previous example, all signal transitions are the same as in the previous example, as shown with arrows  36 ,  38 , and  40 . 
     During the next half-cycle of the clock, when CLK 1  is once again high, a digital signal input pattern of 11 is processed. This input pattern causes comparator  25   a  to generate a digital high “A” signal, as shown with arrow  42 . FIG. 4 also illustrates with arrow  44  that the signal “D” follows the input signal pattern. Thus, at the end of this half-cycle, the logic  28   a  processes the following signals: A=1, B=0, and D=1. As can be appreciated with reference to FIG. 3, this produces an output pattern of B 0 =1 and B 1 =1. FIG. 4 illustrates with arrow  46  how signal A generates signal B 0 . Similarly, arrow  48  shows how signal D generates signal B 1 . 
     Observe that the second output signal B 1  corresponds to the second input signal. That is, the value of the second output signal B 1  follows the value of the second input data bit. The first output signal B 0  is identified by processing both the first input data bit and the second input data bit. FIGS. 5 and 6 illustrate alternate circuits that implement the same functionality. The circuit of FIG. 5 functionally corresponds to the first circuit segment of FIG. 2, while the circuit of FIG. 6 functionally corresponds to the second circuit segment of FIG.  2 . The basic principle of operation for this embodiment of the invention is to use both transmitted bits to decide whether it is in a first group with a bit sequence of 01 or 11 or whether it is in a second group with a bit sequence of 10 or 00. Thereafter, either the first sampled bit or the second sampled bit is assessed to decide whether within the first group the bit sequence is 01 or 11 or whether within the second group the bit sequence is 10 or 00. 
     The circuit of FIG. 5 processes two data bits during a first clock edge or half-cycle, while the circuit of FIG. 6 processes two data bits during a second clock edge or half-cycle. The circuits of FIGS. 5 and 6 are identically configured, except they are responsive to different input clocks signals. Since the circuits are identical, attention will only be focused on the circuit of FIG.  5 . 
     The circuit of FIG. 5 includes a first level-sensitive latch  50   a  to identify a digital low-to-high signal transition during a clock half-cycle. In response to such a condition, the latch  50   a  generates a digital high output signal, otherwise it provides a digital low output signal. A second level-sensitive latch  52   a  is used to identify a digital high-to-low signal transition during a clock half-cycle. In the event of a digital high-to-low signal transition, the latch  52   a  generates a digital high output signal, otherwise it generates a digital low output signal. 
     The circuit of FIG. 5 also includes a transmission gate  54   a . As in the embodiment of FIG. 2, the transmission gate may simply be a transistor with its gate controlled by the clock signal, in this case the clock signal CLK 1 . A logical exclusive-OR gate  56   a  combines the output S 2  from the transmission gate  54   a  and the output S 1  from the latch  50   a . The output of the logical exclusive-OR gate  56   a  operates as an input to the logical OR gate  58   a . The other input to the logical OR gate  58   a  is the output of the latch  52   a . The output from the logical OR gate  58   a  is driven through a flip-flop  60   a , which is operative during the positive half-cycle defined by the clock signal CLK 1 . Similarly, the output from the transmission gate  54   a  is driven through a flip-flop  62   a , which is operative during the same positive half-cycle of clock signal CLK 1 . The circuit of FIG. 6 operates in the same manner, but it is responsive to the next half-cycle of the clock, that is, when the CLK 2  signal is positive. 
     The operation of the circuit of FIG. 5 is more fully appreciated with reference to the timing diagrams of FIG.  7 . The circuit of FIG. 5 is operative in response to a digital high CLK 1  signal, therefore, the signals associated with the digital low half-cycle of the CLK 1  signal are blocked out in FIG.  7 . FIG. 7 illustrates input data of a digital high and a digital low (i.e., a binary signal of 10) during the first half-cycle that CLK 1  is in a digital high state. The signal transition from a digital high state to a digital low state causes latch  52   a  to generate a digital high signal, as shown with arrow  70  in FIG.  7 . The digital high signal S 3  causes the OR gate  58   a  to generate a digital high output signal, which is passed by flip-flop  60   a  to produce a digital high “bit0” signal. 
     The transmission gate  54   a  simply passes the input data signal, thus, the S 2  signal at the output node of the transmission gate  54   a  follows the input data signal, as shown in FIG.  7 . At the end of the first half-cycle of the CLK 1  signal, the S 2  signal is a digital low, thus the “bit1+ signal at the output of the flip-flop  62   a  is a digital low. In sum, the “bit 0 ” signal is a digital low, while the “bit1” signal is a digital high, therefore reproducing the input signal. 
     During the next half-cycle that the CLK 1  signal is a digital high, a binary data input pattern of “11” is transmitted, as shown in FIG.  7 . Since there is no signal transition in this case, the level-sensitive latches  50   a  and  52   a  do not produce a digital high signal. As previously discussed, the transmission gate  54   a  passes the input signal. The first digital high data bit is applied to one input of the exclusive-OR gate  56   a , while the other input to the exclusive-OR gate remains low because the latch  50   a  has not identified a signal transition. This input pattern causes the exclusive-OR gate to generate a digital high signal, which causes the OR gate  58   a  to produce a digital high signal, resulting in a digital high “bit0” signal. The second digital high data bit is routed through the transmission gate  54   a  and through the flip-flop  62   a  to produce a digital “bit  1 ” signal. Thus, the “bit0” and “bit 1” signals reproduce the input signal pattern. 
     A digital low bit and a digital high bit are transported during the final half-cycle of the CLK 1  signal shown in FIG.  7 . The low-to-high transition causes latch  50   a  to generate a digital high signal, as shown with arrow  72 . This digital high signal is applied to one input node of the exclusive-OR gate  56   a . The other input node of the exclusive-OR gate also receives a digital high input signal because the transmission gate  54   a  causes the S 2  signal to follow the input signal. These inputs cause the exclusive-OR gate  56   a  to generate a digital low input, which is passed by the logical OR gate  58   a  and the flip-flop  60   a  to produce a digital low “bit0” value. The “bit1” value corresponds to the S 2  signal, which follows the input signal. Since the second bit of the input signal is a digital high signal, the “bit1” value is a digital high signal. In sum, the “bit0” and “bit1” signals reproduce the input signal. 
     FIG. 8 illustrates waveforms processed by the circuit of FIG.  6 . The circuit of FIG. 6 is operative when the CLK 2  signal is in a digital high state (and the CLK 1  signal is in a digital low state). Observe that the CLK 2  digital high signal enables the transmission gate  54   b , the flip-flop  60   b , while the digital low CKL 1  signal disables the corresponding components in FIG.  5 . 
     The first data input pattern transmitted in FIG. 8 has a first digital high bit and a second digital low bit. The high-to-low transition causes latch  52   b  to generate a digital high signal, as shown with arrow  74 . This digital high signal is passed through the OR gate  58   a  and the flip-flop  60   a  to produce a digital high “bit0”′ signal. As previously discussed, the S 2 ′ signal follows the input signal, thus the “bit1”′ signal has a digital low value at the end of the half-cycle. In sum, the “bit0”′ signal has a digital high value, while the “bit1”′ signal has a digital low value. 
     During the next digital high CLK 2  signal, two digital low data bits are transmitted. Since there is no signal transition, the latches  50   b  and  52   b  generate digital low signals. Similarly, the transmission gate  54   b  passes digital low signals. The exclusive-OR gate  56   a  processes digital low signals, and thereby generates a digital low signal. The exclusive-OR gate digital low output is applied to the OR gate  58   a  along with another digital low signal, producing a digital low signal as “bit0”′. Since signal S 2 ′ follows the input signal, the digital low second bit causes a digital low“bit1”′ signal. In sum, the “bit0”′ and “bit1”′ signals are low, replicating the input data bit pattern. 
     FIG. 9 illustrates an alternate embodiment of the invention. The embodiment of FIG. 9 corresponds to the embodiment of FIG. 2, except that delay elements  100   a  and  100   b  are incorporated into the embodiment of FIG.  9  and the gates  24   a  and  24   b  of FIG. 2 are replaced with edge triggered latches  102   a  and  102   b . The delay elements and latches are used to alter the sequence of processing of the individual input bits. That is, the bit B 0  is produced by latching the first data input bit after the delayed CKL 1  signal is received at the latch  80   a  from the delay element  100   a . Bit B 1  is produced by processing the two input bits. Similar processing occurs at circuit  21   b with the delay element  100   b  and the latch  102   b.    
     Thus, for the embodiment of FIG. 9, the output is defined as follows: B 0 =D and B 1 =A+B*D!. Observe that this is the opposite of the case of the embodiment of FIG. 2, where the output is defined as follows: B 1 =D and B 0 =A+B*D!. Similar components may be incorporated into the circuits of FIGS. 5 and 6 to establish a reversal of the sequence in which the bits are processed. 
     This alternate embodiment is introduced for the purpose of demonstrating that an individual output bit (e.g., B 0 ) may be produced by either processing two data bit signals (e.g., B 0 =A+B*D! in the embodiment of FIG. 2) or by simply passing a single data bit signal (e.g., B 0 =D in the embodiment of FIG.  9 ). Therefore, it should be appreciated that a reference to a “first output bit” in the claims designates either output bit (i.e., B 0  or B 1 ), and that a reference to a “second output bit” in the claims designates an opposite output bit (i.e., B 1  or B 0 ). 
     The technology of the invention facilitates full utilization of existing clock speeds by transporting two bits of data every clock edge. Thus, more information is transported in response to a clock edge signal. The technique of the invention allows improved processing speeds without increasing clock speed. Advantageously, the invention can be implemented using standard components and is otherwise compatible with most circuit architectures. 
     The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the specific details are not required in order to practice the invention. In other instances, well known circuits and devices are shown in block diagram form in order to avoid unnecessary distraction from the underlying invention. Thus, the foregoing descriptions of specific embodiments of the present invention are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, obviously many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.