Abstract:
For transmitting binary data at a data transmission speed of F=1/[(N+1)T] bits/second, where N represents a value selected in accordance with a given transmission speed and T represents a predetermined constant period, a transmitter station sends out a bipolar signal on a transmission line for the period T (seconds) corresponding to one of the states of the binary data independent of the data transmission speed, while no data is sent out on the transmission speed, while no data is sent out on the transmission line for the period NT (seconds) as well as for a period corresponding to the other state of the binary data. In a receiving station, the binary states of the data are discriminatively determined from the bipolar signal received through the transmission line in accordance with the data transmission speed F, the data being converted to a unipolar signal such as NRZ signal.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a data transmission method and a data transmission system and particularly to those systems suitable for use in transmitting data at different transmission speeds on the same transmission line. 
     In the prior art, NRZ signals, bipolar signals and the like are used for serially transmitting data in the form of base band signals. However, in transmitting serial data in such form of signal wave over a long distance, a significant pulse width included in the signal waveform is dependent on the transmission speed of the data, and thus the following problems may occur. 
     First, since long-distance transmission of a signal on the transmission line causes the signal waveform to be distorted due to the characteristic of the line, interference between codes may occur in the binary state of the signal, preventing the binary states from being accurately discriminated. 
     Secondly, when data is transmitted at different transmission speeds on the same transmission line, the significant pulse width included in the transmitted signal waveform is changed depending on the transmission speeds, and thus to prevent mismatching (reflection or the like) between the transmission line characteristic and signal waveform, it is necessary to provide a circuit to terminate the line for matching to the line characteristic at each transmission speed, in the data receiving circuit, or to restrict the transmission speed. 
     SUMMARY OF THE INVENTION 
     It is an object to provide a data transmission method and system with the above drawbacks obviated, and in which the interference between codes is almost prevented from occuring in the binary states of the signal so that the binary states of the signal can be discriminated accurately, or substantially no data error occurs, even if a distortion occurs in the transmitted signal waveform, and it is unnecessary to terminate the line, considering the line characteristic at each transmission speed even if data is transmitted at different transmission speeds. 
     Thus, according to this invention, there is provided a data transmission system for transmitting data at a transmission speed given by F=1/{(N+1)} (bits/sec) where N&gt;0, wherein on the transmitting side, a bipolar signal, for example, is sent on a transmission line during a constant period of time T (sec) forming part of the bit time of the data irrespective of the transmission speed of the data in response to one of the binary states of the data but no signal is sent on the line during the other portion N·T (sec) of the bit time, and in response to the other of the binary states, no signal is sent on the line; while on the receiving side, the binary states of the transmitted data are discriminated by the presence or absence of a bipolar signal on the line in accordance with the data transmission speed F, the data is converted to, for example, a NRZ signal and a receiving clock signal is generated for sampling this NRZ signal. 
     Thus, according to this invention, since no signal is sent during the N·T period after the bipolar data signal is sent, interference between codes is substantially eliminated even if a distortion is introduced in the signal waveform. Moreover, there is no need to consider the transmission line characteristic at each transmission speed. Particularly, if a bipolar signal is sent, the signal waveform distortion is reduced further. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows the whole of a data transmission system. 
     FIG. 2 is a detailed diagram of a data transmission system according to this invention. 
     FIG. 3 is a waveform diagram showing a waveform at each point in FIG. 2. 
     FIG. 4 is a specific arrangement of the transmitting logic circuit in FIG. 3. 
     FIG. 5 is a specific arrangement of the receiving logic circuit in FIG. 3. 
     FIG. 6 shows the relation between the transmission speed and the speed control signal. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows the overall data transmission system according to this invention. Referring to FIG. 1, a data transmission system 1 includes a transmitting circuit 4, a transmission line 5, and a receiving circuit 6. The transmitting circuit 4 sends a transmission clock signal (TXCLK) 3, and a serial data signal (TXDATA) 2 in the form of an NRZ signal is supplied to the transmitting circuit 4 in synchronism with the trailing edge of the clock signal 3. The receiving circuit 6 converts a signal on the transmission line 5 into a NRZ signal and produces the NRZ signal as a received data signal (RCVDATA) 8. In addition, the receiving circuit 6 produces a received clock signal (RCVCLK) 7 in synchronism with the data signal 8. The received data signal 8 is sample at the trailing edge of the received clock signal 7. 
     FIG. 2 is a detailed block diagram of the data transmission system of FIG. 1, and FIG. 3 is a waveform diagram showing each signal waveform in FIG. 2. It is assumed that 15 different data transmission speeds, F=1/{(N+1)·T} (bits/sec), where N=1, 2, 3, . . . 15 selected in accordance with the transmission speed and T is a constant independent of the transmission speed. FIG. 3 is an example for N=3. 
     A transmitting logic circuit 15 is supplied with a fundamental transmission clock signal of period T/4 (BASECLK) 17, so as to produce the transmission clock signal (TXCLK) 3 in response to the clock signal 17. The transmission data signal (TXDATA) 2 in the form of a NRZ signal is received by the logic circuit 15 in synchronism with this transmission clock signal 3. This transmitting logic circuit 15 produces first and second transmission outputs (TX1) 19 and (TX2) 20 during the period T of one bit time of the data (time necessary for 1 bit of data to be transmitted and received) which one bit time includes the two periods T and N·T as shown in FIG. 3 during the &#34;0&#34; state of the transmission data 2, the period T being independent of the transmission speed. These outputs 19 and 20 are supplied through voltage clamping circuits 101 and 102 to a pulse transformer 11, respectively. Then, the pulse transformer 11 sends the bipolar signal as a transmission data signal 22 to the transmission line 5. During the N·T period, which is dependent on the transmission speed, the transmission outputs 19 and 20 are generated from the logic circuit 15 and thus no significant signal is sent on the transmission line 5. When the transmission data signal 2 is &#34;1&#34;, the logic circuit 15 produces no outputs 19 and 20 during one bit time, or (N+1)·T of data, and thus no signal is sent on the line 5. The transmission line 5 is terminated by a terminal resistance 12. 
     The transmission data signal 22 from the transmission circuit 4 is transmitted on the line 5 and supplied to the receiving circuit 6. In the receiving circuit 6, the transmission data 22 is received by the pulse transformer 11, attenuated by an attenuator 13 and then supplied to a sense amplifier 14. The sense amplifier 14 converts the bipolar signal sent as the transmission data signal 22 from the circuit 4 into two pulses of the same polarity, which are then supplied as a received input signal (RCVIN) 21 to a receiving logic circuit 16. To the logic circuit 16 is also supplied a received sampling clock signal (SMPLCLK) 18 of period T/16. The received input 21 is sampled at each pulse of the clock 18. When two consecutive pulses of the same polarity are detected in the received input 21, the received data signal (RCVDATA) 8 is turned to &#34;0&#34; and also the received clock signal 7 is controlled to be in synchronism with the received data signal 8 so that the received data signal 8 can be sampled at the trailing edge of the received clock signal (RCVCLK) 7. Subsequently, when the two consecutive pulses of the same polarity are not detected in the received input 21 after a lapse of 1 bit time, the received data turns to &#34;1&#34;. 
     FIG. 4 shows a specific arrangement of the transmitting logic circuit 15. 
     Referring to FIG. 4, the fundamental transmission clock signal 17 of pulse width T/4 and duty ratio of 50% is applied to the T-input of a flip-flop 23 and a NOR circuit 28. This flip-flop 23 produces at its &#34;1&#34; output terminal the clock 17 divided in frequency by 2. The &#34;1&#34; output of the flip-flop 23 is connected to the T-inputs of a synchronous counter 25 and flip-flop 29. The &#34;1&#34; side output of the flip-flop 23 is inverted by an inverter 26 and then applied to the T-inputs of a flip-flop 27 and synchronous counter 30. The &#34;0&#34; side output of the flip-flop 23 is fed back to its own D-input. 
     The synchronous counter 25 is a programmable counter, the inputs of 2 3  to 2 0  of which are connected to a transmission speed control switch 24. This switch 24 specifies speed control signals 38 to 41 by using 4 bit digital values A to D. FIG. 6 shows the relation between the speed control signals A, B, C, D and transmission speed 1/{(N+1)·T} (N=1, 2, 3 . . . 15). H represents the high level, and L the low level. Also, the synchronous counter 30 is a programmable counter, the 2 3  to 2 0  inputs of which are fixed to &#34;L&#34; in advance. 
     The RC output of the synchronous counter 25 becomes &#34;H&#34; during T once at each (N+1)·T/2 in accordance with the speed control signals of the 2 3  to 2 0  inputs, and is applied to the D-input of the flip-flop 27. The &#34;0&#34; side output of the flip-flop 27 is fed back to the LD input of the synchronous counter 25. Also, the RC output of the synchronous counter 25 is applied to the ET input of the synchronous counter 30. As a result, the synchronous counter 30 produces at the 2 0  output the transmission clock (TXCLK) 3 of period (N+1)·T and duty ratio 50%. 
     On the other hand, the &#34;1&#34; side output of the flip-flop 27 is connected to the D-input of a flip-flop 29, and the &#34;1&#34; side output of the flip-flop 29 is connected to one input of a NAND circuit 33. To the other input of the NAND circuit 33 is applied a signal into which the 2 0  output of the synchronous counter 30 is inverted by an inverter 31. The flip-flop 29 shifts the RC output of the synchronous counter 25 by T/2 to produce &#34;H&#34; at the &#34;1&#34; side output during period T after a lapse of T/4 from the leading edge and trailing edge of the transmission clock 3. Thus, the output of the NAND circuit 33 becomes &#34;L&#34; during period T once at each period (N+1)·T of the clock 3 after a lapse of T/4 from the trailing edge of the clock 3. The output of the NAND circuit 33 and the transmission data 2 are applied to an OR circuit 35. 
     The transmission data 2 is changed in synchronism with the trailing edge of the clock 3. When the data 2 is &#34;0&#34; or &#34;L&#34;, the output of the OR circuit 35 becomes &#34;L&#34; during the period &#34;T&#34; after a lapse of T/4 from the trailing edge of the clock 3. The output of the OR circuit 35 and fundamental clock 17 are applied to a NOR circuit 28. As a result, the output of the NOR circuit 28 becomes &#34;H&#34; during T/4 after the lapse of T/2 from the trailing edge of the clock 3. The output of the NOR circuit 28 is applied to the first inputs of NAND circuits 36 and 37, and also through an inverter 32 to the T-input of a flip-flop 34. The &#34;0&#34; side output of the flip-flip 34 is fed back to its own D-input, and at the same time is applied to the other input of the NAND circuit 36. The &#34;1&#34; side output of the flip-flop 34 is applied to the other input of the NAND circuit 37. 
     If now the &#34;0&#34; side output of the flip-flop 34 is &#34;H&#34;, the first transmission output (TX1) 19 becomes &#34;L&#34;, as shown in FIG. 3, only when the NOR circuit 28 produces an output of &#34;H&#34;. When the output of the NOR circuit 28 falls, the &#34;1&#34; side output of the flip-flop 34 becomes &#34;H&#34; and the &#34;0&#34; side output thereof is &#34;L&#34;. The output of the NOR circuit 28 becomes &#34;H&#34; during T/4 after a lapse of T from the trailing edge of the clock signal 3. At this time, since the &#34;1&#34; side output of the flip-flop 34 is &#34;H&#34;, the second transmission output (TX2) 20 is &#34;L&#34;. During the period in which the transmission outputs 19 and 20 are &#34;L&#34;, the bipolar signal of transmission data 22 shown in FIG. 3 is sent from the circuit 4 to the line 5. During the remaining period in which the transmission data is &#34;0&#34;, that is, during the period of (N-1/4)T after the lapse of 5T/4 from the trailing edge (the fall) of the clock signal 3, and during the period in which the tarnsmission data is &#34;1&#34; or &#34;H&#34;, the output of the OR circuit 35 remains &#34;H&#34;, and thus the output of the NOR circuit 28 stays &#34;L&#34;, the transmission outputs 19 and 20 never becoming &#34;L&#34;. Therefore, no significant signal is sent on the line 5. 
     FIG. 5 shows a specific arrangement of the receiving logic circuit 16. Referring to FIG. 5, the received input signal (RCVIN) 21 is applied to the DA end of a flip-flop 43. The receiving sampling clock signal 18 is applied to the T-inputs of an inverter 42, flip-flop 43, and flip-flop 51. This received input signal 21 is synchronized with the received sampling clock signal (SMPLCLK) 18 of period T/16 which is applied to the T-input of the flip-flop 43, and produced at the UA-1 output of the flip-flop 43. The output at UA-1 of the flip-flop 43 is applied to the DA input of a flip-flop 47 and at the same time the UA-1 output of the flip-flop 43 and UA-1 output of the flip-flop 47 are applied to an AND circuit 46. The output of the AND circuit 46 is applied to the DB input of the flip-flop 47. The UA-1 output of the flip-flop 43 is fed back to the DB input of the flip-flop 43, and applied to a NAND circuit 44. To the other input ends of the NAND circuit 44 are applied the UB-0 output of the flip-flop 43 and the UA-0 output of the flip-flop 47, respectively. The clock signal 18 is inverted by an inverter 42 and then applied to the T inputs of synchronous counters 45, 48, 52 and 56. 
     When the received input 21 is changed from &#34;L&#34; to &#34;H&#34;, the UA-1 output of the flip-flop 43 is also &#34;H&#34;, and the output of the NAND circuit 44 becomes &#34;L&#34; during the interval of a single clock pulse from the leading edge of the clock 18, or during T/16. The output of the NAND circuit 44 is connected to the LD input of the synchronous counter 45. The synchronous counter 45 operates in synchronism with the received input which is synchronized with the leading edge of the receiving sampling clock signal 18, or the leading edge of the UA-1 output of the flip-flop 43, to produce 2 2  -output which is used for sampling the UA-1 output of the flip-flop 47 at time points 3T/32, and 19T/32 from the leading edge of the output. When the sampled results at the two points are both &#34;H&#34; and the RC output of the synchronous counter 45 is &#34;H&#34;, a NAND circuit 50 to which the RC output of the synchronous counter 45 and the UA-1 output of the flip-flop 47 are applied becomes &#34;L&#34;. Thus, the &#34;1&#34; side output of a flip-flop 51 connected to the NAND circuit 50 becomes &#34;L&#34; during the interval of a single clock (T/16) from the leading edge of the clock signal 18. Here, during the period in which the UA-0 output of the flip-flop 47 is &#34;L&#34;, the synchronous counter 45 is not synchronized with the received input signal 21 since the receiving logic circuit 16 is sampling two successive pulses. 
     The &#34;1&#34; side output of the flip-flop 51 is connected to the S-input of a flip-flop 53, the R-input of a flip-flop 47, and the LD input of a synchronous counter 56. When the &#34;1&#34; side output of the flip-flop 51 becomes &#34;L&#34;, the flip-flop 53 stores the received data of &#34;0&#34;. At the same time, since the received clock signal (RCVCLK) 7 is produced, the synchronous counters 48, 52 and 56 are synchronized with the received data. Thus, the &#34;0&#34; side output of the flip-flop 52 is applied through the NOR circuit 49 to the LD input of the synchronous counter 48, and the RC output of the synchronous counter 48 becomes &#34;H&#34; at each ·T/2. The RC-output of the synchronous counter 48 is connected to the NOR circuit 49 and the ET input of the synchronous counter 52. The &#34;0&#34; side output of the flip-flop 51 is connected through the NOR circuit 55 to the LD-input of the synchronous counter 52. The RC output of the synchronous counter 52 becomes &#34;H&#34; at each (N+1)·T/2 in response to the state of the speed control signals A, B, C and D as shown in FIG. 6. The RC output of the synchronous counter 52 is applied to the NOR circuit 55 and the ET input of the synchronous counter 56. The &#34;1&#34; side output of the flip-flop 51 is connected to the LD input of the synchronous counter 56, and the 2 3  to 2 0  inputs of the synchronous counter 56 are fixed to &#34;L&#34;. Thus, the 2 0  output of the synchronous counter 56 is the receiving clock signal (RCVCLK) 7 of the period (N+1)·T synchronized with the received data and a duty ratio of 50%. 
     The received clock signal 7 is applied to the T-inputs of the flip-flops 53 and 54, and the &#34;1&#34; side output of the flip-flop 53 is connected to the D-input of the flip-flop 54. Thus, at the leading edge of the clock signal 7, the contents of the flip-flop 53 are transferred to the flip-flop 54, which then produces at the &#34;1&#34; side output the received data (RCVDATA) 8 of &#34;0&#34; or &#34;L&#34;, and also the data stored in the flip-flop 53 is cleared. If the received input 21 remains &#34;L&#34; during 1 bit time, or (N+1)·T, the &#34;1&#34; said output of the flip-flop 51 stays also &#34;1&#34;, or &#34;H&#34;. The received data 8 thus generated can be sampled at the next trailing edge of the received clock signal 7. 
     While the illustrated embodiment is for N=1 to 15 the cases of larger values of N can be realized similarly. 
     Thus, according to this embodiment, since the bipolar signal is sent during the period T in accordance with one of the significant states of transmission data and data is not sent during the period N·T, it is not necessary to consider the transmission line characteristic for each transmission speed. In other words, as shown in FIG. 6, to increase the transmission speed, the transmission speed control switch 24 is set to correspond to a small value of N, for example, N=1. On the other hand, to decrease the transmission speed, the control switch 24 is set to correspond to a large value of N. In either case, since data is not sent during the N·T period, data transmission can be performed irrespective of the transmission speed of the data. 
     Other changes and modifications of the invention can be made. For example, when data is transmitted from a transmitter to a plurality of receivers, a plurality of the same receiving circuits as the receiving circuit 6 shown in FIG. 1 are connected to the transmission line 5. Also, the circuits as shown in FIGS. 4 and 5 can be modified in various ways. For example, the control switch for changing the data transmission speed is not limited to a digital type. Moreover, the signal sent from the transmitter is desirably a bipolar signal, but considering waveform distortion and so on it is not always limited thereto.