Abstract:
A liquid crystal panel ( 200 ) includes parallel gate lines ( 212 ), and parallel data lines ( 213 ) insulatingly intercrossing the gate lines. The gate lines and the data lines define a plurality of pixel regions ( 211 ). Each pixel region includes a first thin film transistor (TFT) ( 215 ), a second TFT ( 216 ), a first pixel electrode ( 217 ), and a second pixel electrode ( 218 ). The first TFT includes a first gate electrode connected with the gate line, a first source electrode connected with the data line, and a first drain electrode connected with the first pixel electrode. The second TFT includes a second gate electrode ( 2162 ), a second source electrode ( 2161 ), and a second drain electrode ( 2163 ). The second gate electrode is connected with a gate line via a voltage dividing element. The second drain electrode is connected with the second pixel electrode.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to liquid crystal panels, and particularly to a multi-domain vertical alignment (MVA) liquid crystal panel and a liquid crystal display (LCD) using the MVA liquid crystal panel. 
       GENERAL BACKGROUND 
       [0002]    LCDs have the advantages of portability, low power consumption, and low radiation, and have been widely used in various portable information products such as notebooks, personal digital assistants (PDAs), video cameras and the like. A conventional LCD such as a twisted nematic (TN) LCD provides a limited viewing angle. Thus, MVA LCDs were developed to improve the viewing angle. 
         [0003]    Referring to  FIG. 11 , a typical MVA liquid crystal panel is shown. The liquid crystal panel  100  includes a first substrate assembly (not shown), a second substrate assembly generally facing the first substrate assembly, and a liquid crystal layer (not labeled) sandwiched between the first substrate assembly and the second substrate assembly. The liquid crystal layer includes a plurality of liquid crystal molecules  131 . 
         [0004]    The first substrate assembly includes a color filter (not shown), a common electrode (not shown), and a plurality of first protrusions  119 , arranged in that order. The color filter includes a plurality of red filter units (not shown), a plurality of green filter units (not shown), and a plurality of blue filter units (not shown). The first protrusions  119  each are triangular in cross-section, and are arranged along a plurality of V-shaped paths. 
         [0005]    The second substrate assembly includes a plurality of parallel gate lines  112  that each extend parallel to a first axis, a plurality of first parallel data lines  113  that each extend parallel to a second axis orthogonal to the first axis, a plurality of parallel second data lines  114  each extending parallel to the second axis, a plurality of first thin film transistors (TFTs)  115 , a plurality of second TFTs  116 , a plurality of first pixel electrodes  117 , a plurality of second pixel electrodes  118 , and a plurality of second protrusions  129 . 
         [0006]    The first data lines  113  and the second data lines  114  are arranged alternately. Every two adjacent first data lines  113 , together with every two adjacent gate lines  112 , form a rectangular area, defined as a pixel region  111 . Each pixel region  111  corresponds to a filter unit of the color filter. Each second data line  114  is disposed across the middle of a corresponding pixel region  111 , and divides the pixel region  111  into a first sub-pixel region  101  and a second sub-pixel region  102 . 
         [0007]    In each pixel region  111 , the first TFT  115  is located in the vicinity of an intersection of the first data line  113  and the gate line  112 . The second TFT  116  is located in the vicinity of an intersection of the second data line  114  and the gate line  112 . Gate electrodes (not labeled) of the first TFT  115  and the second TFT  116  are connected to the same gate line  112 . A source electrode (not labeled) of the first TFT  115  is connected to the first data line  113 . A source electrode (not labeled) of the second TFT  116  is connected to the second data line  114 . The first pixel electrode  117  is located in the first sub-pixel region  101 , connected with a drain electrode (not labeled) of the first TFT  115 . The second pixel electrode  116  is located in the second sub-pixel region  102 , connected with a drain electrode (not labeled) of the second TFT  116 . The first data line  113  provides a plurality of first gray-scale voltages to the corresponding first pixel electrode  117  via the first TFT  115 . The second data line  114  provides a plurality of second gray-scale voltages to the corresponding second pixel electrode  118  via the second TFT  116 . The first gray-scale voltages and the second gray-scale voltages are applied thereto independently. 
         [0008]    The second protrusions  129  each are triangular in cross-section, arranged along a plurality of V-shaped paths. The second protrusions  129  and the first protrusions  119  are arranged alternately. 
         [0009]    Referring also to  FIG. 12 , an equivalent circuit diagram of one pixel region  111  of  FIG. 11  is shown. The first pixel electrode  117 , the common electrode, and the liquid crystal layer sandwiched therebetween cooperatively form a first liquid crystal capacitor  104 . The second pixel electrode  118 , the common electrode, and the liquid crystal layer sandwiched therebetween cooperatively form a second liquid crystal capacitor  105 . 
         [0010]    Referring also to  FIG. 13 , a top-down view of orientations of four of the liquid crystal molecules  131 , according to the first protrusions  119  and the second protrusions  129 , is shown. In each frame, when a first gray-scale voltage is applied to the first pixel electrode  117 , and a common voltage is applied to the common electrode, an electric field is generated therebetween. The liquid crystal molecules  131  in the first sub-pixel region  101  re-orient according to the electric field. The liquid crystal molecules  131  are guided by the protrusions  119 ,  129  and thereby become aligned along four different axes. Thus four domains are defined according to the protrusions  119 ,  129 . 
         [0011]    Similarly, in the same frame, when a second gray-scale voltage is applied to the second pixel electrode  118 , and a common voltage is applied to the common electrode, an electric field is generated therebetween. The liquid crystal molecules  131  in the second sub-pixel region  102  re-orient according to the electric field. The liquid crystal molecules  131  are guided by the protrusions  119 ,  129  and thereby align along four different axes. Thus four domains are defined according to the protrusions  119 ,  129 . Referring also to  FIG. 14 , because the voltages of the first pixel electrode  117  differ from the voltage of the second pixel electrode  118  in each frame, a tilt angle θ 3  of the liquid crystal molecules  131  in the first sub-pixel region  101  differs from a tilt angle θ 4  of the liquid crystal molecules  131  in the second sub-pixel region  102 . Thus, a total of eight domains are defined in each pixel region  111 . The liquid crystal panel  100  achieves 8-domain vertical alignment. 
         [0012]    However, each pixel region  111  requires a first data line  113  and a second data line  114  for the liquid crystal panel  100  to perform the 8-domain vertical alignment. The layout of the first data line  113  and the second data line  114  is complicated, resulting in an increase of cost thereof. 
         [0013]    It is desired to provide an improved liquid crystal panel and an LCD which can overcome the limitations described. 
       SUMMARY 
       [0014]    In one embodiment, a liquid crystal panel includes parallel gate lines with parallel data lines insulatingly intercrossing the gate lines. The gate lines and the data lines define a plurality of pixel regions, each including a first thin film transistor (TFT), a second TFT, a first pixel electrode, and a second pixel electrode. The first TFT includes a first gate electrode connected with the gate line, a first source electrode connected with the data line, and a first drain electrode connected with the first pixel electrode. The second TFT includes a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode is connected with a gate line via a voltage dividing element. The second drain electrode is connected with the second pixel electrode. 
         [0015]    Other novel features and advantages will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, all the views are schematic. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  is a top plan view of part of a liquid crystal panel according to a first embodiment of the present invention, the liquid crystal panel defining a plurality of pixel regions each divided into a first sub-pixel region and a second sub-pixel region, each pixel region including a plurality of liquid crystal molecules, a first TFT, a second TFT, and a coupling electrode. 
           [0017]      FIG. 2  is an enlarged, schematic view of a circled portion II of  FIG. 1 . 
           [0018]      FIG. 3  is a schematic, side view of one liquid crystal panel taken along line III-III of  FIG. 2 . 
           [0019]      FIG. 4  is an equivalent circuit diagram of one of the pixel regions of  FIG. 1 . 
           [0020]      FIG. 5  is a schematic, side view showing an active channel of the second TFT of  FIG. 1 . 
           [0021]      FIG. 6  is a top-down view of orientations of four of the liquid crystal molecules of  FIG. 1 . 
           [0022]      FIG. 7  is a schematic, side view of one of the liquid crystal molecules in the first sub-pixel region and one of the liquid crystal molecules in the second sub-pixel region of  FIG. 1 , the liquid crystal molecules having different tilt angles. 
           [0023]      FIG. 8  is similar to  FIG. 3 , but shows a corresponding view of a resistor of a liquid crystal panel according to a second embodiment of the present invention. 
           [0024]      FIG. 9  is an equivalent circuit diagram of the liquid crystal panel of  FIG. 8 . 
           [0025]      FIG. 10  is a schematic, side view of an LCD of the present invention using the liquid crystal panels of  FIG. 8 . 
           [0026]      FIG. 11  is a top plan view of a conventional liquid crystal panel, defining a plurality of pixel regions, each divided into a first sub-pixel region and a second sub-pixel region, each pixel region including a plurality of liquid crystal molecules. 
           [0027]      FIG. 12  is an equivalent circuit diagram of one of the pixel regions of  FIG. 11 . 
           [0028]      FIG. 13  is a top-down view of orientations of four of the liquid crystal molecules in the pixel region of  FIG. 12 . 
           [0029]      FIG. 14  is a schematic, side view of one of the liquid crystal molecules in the first sub-pixel region and one of the liquid crystal molecules in the second sub-pixel region of  FIG. 11 , the liquid crystal molecules having different tilt angles. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0030]    Reference will now be made to the drawings to describe preferred and exemplary embodiments of the present invention in detail. 
         [0031]    Referring to  FIG. 1 , a liquid crystal panel  200  according to a first embodiment of the present invention includes a first substrate assembly (not labeled), a second substrate assembly (not labeled) parallel to the first substrate assembly, and a liquid crystal layer (not labeled) sandwiched between the two substrate assemblies. The liquid crystal layer includes a plurality of liquid crystal molecules  231 . 
         [0032]    The first substrate assembly includes a color filter (not shown), a common electrode (not shown), and a plurality of first protrusions  219 , arranged in that order. The color filter includes a plurality of red filter units (not shown), a plurality of green filter units (not shown), and a plurality of blue filter units (not shown). The first protrusions  219  are parallel, each having a triangular cross-section and arranged along a plurality of V-shaped paths. 
         [0033]    The second substrate assembly includes a plurality of parallel gate lines  212 , each extending along a first axis, a plurality of parallel data lines  213 , each extending along a second axis orthogonal to the first axis, a plurality of first TFTs  215  (TFTs), a plurality of second TFTs  216 , a plurality of first pixel electrodes  217 , a plurality of second pixel electrodes  218 , and a plurality of second protrusions  229 . 
         [0034]    Every two adjacent gate lines  212  and every two adjacent data lines  213  cooperatively form a rectangular area defined as a pixel region  211 . Each pixel region  211  corresponds to a filter unit of the color filter. Each pixel region includes a first sub-pixel region  201  and a second sub-pixel region  202 . Each first sub-pixel region  201  includes one of the first TFTs  215  and one of the first pixel electrodes  217 . The first TFT  215  is disposed in the vicinity of an intersection of the gate line  212  and the data line  213 . The first TFT  213  includes a first gate electrode (not labeled), a first source electrode (not labeled), and a first drain electrode (not labeled). 
         [0035]    Referring also to  FIG. 2 , each second sub-pixel region  202  includes one second TFT  216 , one second pixel electrodes  218 , and a coupling electrode  210 . The second TFT  216  includes a second source electrode  2161 , a second gate electrode  2162 , and a second drain electrode  2163 . The second source electrode  2161  is electrically connected with the first pixel electrode  217 . The second gate electrode  2162  is electrically connected with the gate line  212  via the coupling electrode  210 . The coupling electrode  210  can be made from material the same as the first pixel electrode  217  and the second pixel electrode  218 , such as indium tin oxide (ITO) or indium zinc oxide (IZO). 
         [0036]    Referring also to  FIG. 3  and  FIG. 4 , an enlarged, side view of the liquid crystal panel  200  taken along line III-III, and an equivalent circuit diagram of one of the pixel regions  211  are shown. An insulating layer  2165  covers the gate line  212  and the second gate electrode  2162  of the second TFT  216 . The coupling electrode  210  is disposed on the insulating layer  2165 . The coupling electrode  210  includes a first part  2101  and a second part  2102 . The first part  2101  superposes a part of the gate line  212 . The second part  2102  superposes a part of the second gate electrode  2162 . The first part  2101 , the insulating layer  2165 , and the corresponding part of gate line  212  cooperatively form a first capacitor  250 . The second part  2102 , the insulating layer  2165 , and the corresponding part of the second gate electrode  2162  cooperatively form a second capacitor  260 . The first capacitor  250  and the second capacitor  260  are connected in series. That is, the second gate electrode  2162  is electrically connected with the gate line  212  via the second capacitor  260  and the first capacitor  250 . 
         [0037]    When the gate line  212  applies a scanning voltage to the first TFT  215  and the second TFT  216 , a voltage of the first gate electrode of the first TFT  215  is substantially equal to the scanning voltage. The first TFT  215  is completely switched on. A data voltage of the data line  213  is completely applied to the first pixel electrode  217  via the first TFT  215  without a voltage drop. The voltage of the first pixel electrode  217  is substantially equal to the data voltage of the data line  212 . 
         [0038]    Because the first capacitor  250  and the second capacitor  260  generate voltage drops, respectively, a voltage of the second gate electrode  2162  is less than the scanning voltage. That is, the second TFT  216  is incompletely switched on. Referring to  FIG. 5 , an active channel  216  of the second TFT  216  is shown. When the second gate electrode  2162  receives the scanning voltage having a voltage drop on the capacitors  250 ,  260 , a plurality of electrons are accumulated under a lower surface of the insulating layer  2165 , whereby the active channel  216  is formed. Because the actual scanning voltage applied thereto is less, accumulated electrons are correspondingly fewer, such that the active channel  216  is narrow. Accordingly, equivalent resistance of the active channel  216  increases, and when a current flows through the second TFT  216 , the active channel  216  generates a voltage drop, resulting in the data voltage of the data line  213  being partly applied to the second electrode  218 , with voltage thereof falling below that of the voltage of the first pixel electrode  217 . 
         [0039]      FIG. 6  and  FIG. 7  are a top-down view and a side view of orientations of certain of the liquid crystal molecules  231  in the pixel region  211  of  FIG. 4 . When corresponding voltages are applied to the first pixel electrode  217 , the second pixel electrode  218  and the common electrode, electric fields are generated. The liquid crystal molecules  231  re-orient according to the electric fields. The liquid crystal molecules  231  are guided by the first protrusions  219  and the second protrusions  229 , thereby aligning along four different axes. Thus four domains are defined accordingly. 
         [0040]    Because the voltage of the first pixel electrode  217  differs from that of the second pixel electrode  218  in each frame, tilt angles θ 1  of the liquid crystal molecules  231  corresponding to the first pixel electrode  217  differ from tilt angles θ 2  of the liquid crystal molecules  231  corresponding to the second pixel electrode  218 . Thus, a total of eight domains are defined in the pixel region  211 . The liquid crystal panel  200  achieves 8-domain vertical alignment. 
         [0041]    Unlike conventional liquid crystal panels, liquid crystal panel  200  employs the coupling electrode  210  to form the first capacitor  250  and the second capacitor  260 . The coupling electrode  210  functions as a voltage dividing element. The first capacitor  250  and the second capacitor  260  drop the voltage of the second pixel electrode  218  below that of the first pixel electrode  217  and incite a voltage difference between the first pixel electrode  217  and the second pixel electrode  218 . No auxiliary data line is needed to apply a different voltage to the second pixel electrode  218 . That is, each pixel region  211  of the liquid crystal panel  200  needs only one data line  213  to achieve 8-domain vertical alignment. Layout of the data lines  213  is simplified, and the cost of the liquid crystal panel  200  reduced correspondingly. 
         [0042]    Referring to  FIG. 8  and  FIG. 9 , a side view of a part of a liquid crystal panel according to a second embodiment of the present invention is shown, and an equivalent circuit diagram of one pixel region of the liquid crystal panel of  FIG. 8  is shown. The liquid crystal panel  300  is similar to the liquid crystal panel  200 , differing only in that the liquid crystal panel  300  includes a resistor  310  rather than a coupling electrode. The resistor  310  functions as a voltage dividing element. A second gate electrode  3162  of a second TFT  316  is connected with a gate line  312  via the resistor  310 . 
         [0043]    An insulating layer  3165  covers the gate line  312  and the second gate electrode  3162 . The insulating layer  3165  defines a first connecting hole  3166  and a second connecting hole  3167 . The resistor  310  is disposed on the insulating layer  3165 . An end of the resistor  310  is connected with the gate line  312  via the first connecting hole  3166 . The other end of the resistor  310  is connected with the second gate electrode  3162  via the second connecting hole  3167 . The resistor  310  can be semi-conductor material. 
         [0044]    When a scanning voltage is applied to the second gate electrode  3162  via the resistor  310 , the resistor  310  generates a voltage drop. That is, the voltage of the second gate electrode  3162  is reduced, and the second TFT  316  is incompletely switched on. The second TFT  316  generates a voltage drop when a data line applies a data voltage to a second pixel electrode. That is, the voltage of the second pixel electrode is less than the data voltage of the data line. Because the voltage of the first pixel electrode is substantially equal to the data voltage of the data line, the voltage of the second pixel electrode is less than the voltage of the first pixel electrode. The liquid crystal panel  300  can achieve 8-domain vertical alignment. 
         [0045]    Referring to  FIG. 10 , a liquid crystal display (LCD) according to the present invention is shown. The LCD  600  includes a liquid crystal panel  400  and a backlight module  500  parallel to the liquid crystal panel  400 . The backlight module  500  provides uniform light for the liquid crystal panel  400 . The liquid crystal panel  400  can be a liquid crystal panels  200 ,  300 . 
         [0046]    Further or alternative embodiments may include, in a first example, the second source electrodes of the second TFTs  216 ,  316  connecting with the same data lines as the first source electrodes of the first TFTs, and the second source electrodes of the second TFTs  216 ,  316  connecting with the corresponding first drain electrodes of the first TFTs. 
         [0047]    It is believed that the present embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit or scope of the invention or sacrificing all of its material advantages, the examples hereinbefore described merely being preferred or exemplary embodiments of the invention.