Abstract:
A voltage dropping circuit for a semiconductor device is provided. The voltage dropping circuit includes a control unit for producing a reference voltage from a first specified voltage, an output unit for generating a second specified voltage which is a half of the first specified voltage in accordance with the reference voltage, a timer circuit for generating a driving pulse which becomes active intermittently, and a switch circuit for operating the control unit when the driving pulse is active and stopping the operation of the control unit when the driving pulse is not active.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a voltage dropping circuit for a semiconductor device, and more particularly, it relates to a voltage dropping circuit with which power consumption during a standby time can be reduced. 
     2. Description of the Related Art 
     In recent years, semiconductor integrated circuits have been increasingly miniaturized. In particular, this tendency is most noticeable in dynamic RAMs. With the miniaturization of transistors, their supply voltage must be reduced for various reasons, such as lifetime shortening of transistors caused by hot electrons. For example, the supply voltage for transistors having a 0.6 μm gate length must be 4 V or less (e.g., 3.3 V),in general, while the supply voltage which has conventionally been widely used for ICs is 5 V. Consequently, an internal voltage dropping circuit has been used in ICs so that the supply voltage from outside is reduced from 5 V to 3.3 V to be applied to transistors inside. 
     FIG. 5 is a circuit diagram showing the constitution of a conventional (1/2) V CC  voltage generating circuit as the internal voltage dropping circuit for a semiconductor device. 
     As shown in FIG. 5, the conventional (1/2) V CC  voltage generating circuit for a semiconductor device is composed of an output transistor control unit 1 and an output transistor unit 2. The output transistor control unit 1 includes two resistors 1a and 1b for dividing a V CC  supply voltage, an n-channel FET 1c and a p-channel FET 1d which are connected therebetween. A voltage increase control terminal 1e outputs a reference voltage which is higher than half the V CC  supply voltage ((1/2) V CC  voltage) by the pinch-off voltage of the FET 1c, while a voltage decrease control terminal 1f outputs a reference voltage which is lower than the (1/2) V CC  voltage by the pinch-off voltage of the FET 1d. 
     The output transistor unit 2 includes an n-channel FET 2a which is connected between the V CC  power supply and a (1/2) V CC  power supply terminal 3 and a p-channel FET 2b which is connected between the (1/2) V CC  power supply terminal 3 and ground. The reference voltages from the voltage increase control terminal 1e and voltage decrease control terminal 1f are applied to the gates of the FETs 2a  and 2b, respectively. When the actual voltage at the (1/2) V CC  power supply terminal 3 becomes lower than the (1/2) V CC  voltage, the FET 2a is activated. In contrast, when the actual voltage at the (1/2) V CC  power supply terminal 3 exceeds the (1/2) V CC  voltage, the FET 2b is activated, thus maintaining the (1/2) V CC  voltage supplied from the (1/2) V CC  power supply terminal 3. 
     The foregoing conventional (1/2) V CC  voltage generating circuit is designed so that the output transistor control unit 1 always allows the passage of driving current therethrough. However, it has been desired particularly in recent years to minimize the power consumption of semiconductor devices on standby, because of their battery driving and for other reasons. 
     The conventional (1/2) V CC  voltage generating circuit is therefore disadvantageous in that the presence of driving current in the output transistor control unit 1 prevents the power consumption of a semiconductor device from decreasing during a standby time. 
     An application of the (1/2) V CC  voltage generating circuit to DRAMs as semiconductor devices is disclosed in Jun. 7th, 1990 IEEE Symposium on VLSI Circuits, A 1.5 V Circuit Technology for 64 Mb DRAMs, pp 17-18, which shows a schematic view of the conventional (1/2) V CC  voltage generating circuit in FIG. 15 thereof. 
     SUMMARY OF THE INVENTION 
     The present invention provides a voltage dropping circuit for a semiconductor device comprising: a control unit for producing a reference voltage from a first specified voltage; an output unit for generating a second specified voltage which is a half of said first specified voltage on the basis of said reference voltage; a timer circuit for generating a driving pulse which becomes active intermittently; and a switch circuit for operating said control unit when said driving pulse is active and stopping the operation of said control unit when said driving pulse is not active. 
     Said switch circuit preferably connects said control unit to the power source of said first specified voltage when said driving pulse is active and disconnects said control unit therefrom when said driving pulse is not active. 
     Said timer circuit preferably generates a driving pulse having a fixed duration at fixed time intervals. 
     According to the present invention, the power consumption in a standby state of a semiconductor device, for example, a dynamic random access memory can be reduced by intermittently generating the reference voltage for the second specified voltage, while the second specified voltage, which is a half of the first specified voltage, is maintained. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     An embodiment of the invention will now be described by way of example and with reference to the accompanying drawings, in which: 
     FIG. 1 is a block diagram schematically showing the constitution of a (1/2) V CC  voltage generating circuit for a dynamic random access memory, embodying the present invention; 
     FIG. 2 is a circuit diagram showing in detail the constitution of the embodiment of the invention; 
     FIG. 3 is a circuit diagram showing the constitution of a toggle-type flip-flop circuit used in the embodiment of the present invention; 
     FIG. 4 is a timing chart showing the wave forms of individual parts of a timer circuit in FIG. 2; and 
     FIG. 5 is a circuit diagram showing the constitution of a conventional (1/2) V CC  voltage generating circuit. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Preferred embodiments of the present invention will be described below with reference to the drawings in which like components that have the same functions as those of the known components shown above in FIG. 5 are designated by like reference numerals. 
     As shown in FIG. 1, when a driving pulse from a timer circuit 4 becomes active a switch circuit 5 connects an output transistor control unit 1 to a V CC  power supply. The output transistor control unit 1 then generates a reference voltage so that an output transistor unit 2, based on the reference voltage, supplies half the V CC  supply voltage ((1/2) V CC  voltage) to a (1/2) V CC  power supply terminal 3. 
     When the driving pulse from the timer circuit 4 becomes inactive, in contrast, the switch circuit 5 cuts off the output transistor control unit 1 from the V CC  power supply so as to prevent the driving current from passing through the output transistor control unit 1, thereby reducing the power consumption in the meantime. In the case that the voltage at the (1/2) V CC  power supply terminal 3 fluctuates from the (1/2) V CC  voltage during this period, the voltage can be corrected when the driving pulse from the timer circuit 4 becomes active again. 
     The constitution of the present embodiment will be described in detail with reference to FIG. 2. Similarly to the known circuit shown above in FIG. 5, the output transistor control unit 1 includes two resistors 1a and 1b for dividing the V cc  supply voltage, an n-channel FET 1c and a p-channel FET 1d which are connected therebetween. Also similarly to the known circuit the output transistor unit 2 includes an n-channel FET 2a connected between the V CC  power supply and the (1/2) V CC  power supply terminal 3 and a p-channel FET 2b connected between the (1/2) V CC  power supply terminal 3 and ground. The FETs 2a and 2b of the output transistor unit 2 are designed to operate in accordance with the reference voltages from the voltage increase control terminal 1e and the voltage decrease control terminal 1f of the output transistor control unit 1, so as to supply the (1/2) v CC  voltage from the (1/2) V CC  power supply terminal 3. However, the V CC  voltage supplied to the output transistor control unit 1 is controlled by the switch circuit 5. 
     Next, the constitution and operation of the timer circuit 4 will be described with reference to FIGS. 3 and 4. 
     The timer circuit 4 includes a ring oscillator 4a, four toggle-type flip-flop circuits 4b to 4e and an AND circuit 4f. The ring oscillator 4a is composed of a plurality of inverters connected in the shape of a ring and sequentially outputs pulses at an equal duty ratio, as shown in FIG. 4(1). 
     FIG. 3 shows the toggle-type flip-flop circuits 4b to 4e which, each time the input level is switched between HIGH and LOW, operate to input the output from one duplex inverter circuit to the other duplex inverter circuit, or vice versa. Thus, as shown in FIGS. 4(2) to 4(5), these toggle-type flip-flop circuits 4b to 4e perform a toggle operation in which the output level switches between HIGH and LOW each time the input level switches from LOW to HIGH, thereby successively dividing the frequency of an input pulse to half. The AND circuit 4f serves to calculate the AND logical product of the output from each of the toggle-type flip-flop circuits 4b to 4e. As shown in FIG. 4(6), the AND circuit 4f outputs a driving pulse which becomes active (HIGH level) during a time interval corresponding to one out of sixteen frequencies of the pulse oscillated by the ring oscillator 4a. The driving pulse outputted from the AND circuit 4f of the timer circuit 4 is inputted to the switch circuit 5. 
     Next, the constitution of the switch circuit 5 will be described. The switch circuit 5 includes a NOR circuit 5a, a p-channel FET 5b, an n-channel FET 5c and an inverter 5d. The driving pulse from the timer circuit 4 is inputted to the NOR circuit 5a. To the other input of the NOR circuit 5a is inputted an operation forcing signal (HIGH level), by which the output transistor control unit 1 can be activated irrespective of the output from the timer circuit 4. The output of the NOR circuit 5a, which is connected directly to the gate of the p-channel FET 5b, is also connected to the gate of the n-channel p-channel FET 5c via the inverter 5d. The FET 5b is connected between the resistor 1a and the n-channel FET 1c the output transistor control unit 1, while the n-channel FET 5c is connected between the p-channel FET 1d and resistor 1b in the output transistor control unit 1. Hence, the power supply to the output transistor control unit 1 is controlled by the switch circuit 5. 
     It should be noted that the operation forcing signal is inputted upon actuation of the semiconductor device. 
     Next,the operation of the (1/2) V CC  voltage generating circuit provided with the timer circuit 4 and the switch circuit 5 will be described. 
     When the driving pulse from the timer circuit 4 is inputted to the switch circuit 5, the output level of the NOR circuit 5a becomes LOW only during the period in which the driving pulse is active (HIGH level), thereby turning on both the FETs 5b and 5c. As a result, the output transistor control unit 1 is connected to the power supply and the reference voltages are outputted from the voltage increase control terminal 1e and voltage decrease control terminal 1f so that the output transistor unit 2 provides the (1/2) V CC  power supply terminal 3 with the (1/2) V CC  voltage, similarly to the known art. 
     When the driving pulse is not active, in contrast, the output level of the NOR circuit 5a of the switch circuit 5 becomes HIGH, thereby turning off both the FETs 5b and 5c. As a result, the output transistor control unit 1 is cut off from the power supply with no more driving current passing therethrough, so that the power consumption can be reduced in the meantime. Moreover, since the voltage increase control terminal 1e and the voltage decrease control terminal 1f are at high impedance during this period, the FETs 2a and 2b of the output transistor unit 2 are kept off, thus eliminating the risk that the (1/2) V CC  power supply terminal 3 is accidentally connected to the V CC  power supply or to ground. 
     Thus, in accordance with the present embodiment, the output transistor control unit 1 does not constantly allow the driving current to pass therethrough, for the output transistor control unit 1 operates only when the driving pulse from the timer circuit 4 becomes active intermittently, resulting in a reduced power consumption of a semiconductor device on standby. 
     While the present invention has been described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes may be made without departing from the spirit or scope of the invention.