Abstract:
A system is disclosed for coupling electrically isolated circuits in a monolithic integrated circuit. A signal coupler is integrated on a chip together with a primary circuit and a secondary circuit which is to be coupled to the primary circuit. The signal coupler comprises an integrated coupling capacitor which consists of a coplanar conductor path arrangement embedded into a passivation layer, the passivation layer being applied to an insulating substrate, preferably sapphire.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to a monolithically integrated circuit of high dielectric strength for electrically coupling isolated circuits. 
     In most cases circuits operated directly from the mains require electrical decoupling between the input side and the output side with high dielectric strength, e.g. 1.5 kV voltage difference between the two sides. Previously circuits of this kind have been constructed exclusively from discrete components, such as for example transformers, capacitors or opto-couplers. Known semiconductor relays are constructed for example with hybrid-integrated components in which case an opto-coupler consists of a photo-diode, a light conducting path, and a photo-transistor. The use of a capacitor for the aforementioned purpose is disclosed for example in the magazine &#34;Elektor&#34;, July/August 1976, 7-48/49 &#34;Kapazitiver Triac-Keppler&#34;. 
     One of the disadvantages of the known circuits is that they are relatively complicated and are also expensive. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a circuit which combines the advantages of high dielectric strength in the path between input side and output side, a small space requirement, and low production costs. 
     The object on which the invention is based is attained by a monolithically integrated circuit of high dielectric strength for electrically coupling isolated circuits. A signal coupler is integrated on a chip together with a primary circuit and a secondary circuit which is to be coupled to the primary circuit. The signal coupler comprises an integrated coupling capacitor which consists of a plurality of sub-capacitors formed of a coplanar arrangement of more than two conductors and is embedded into a passivation layer and is applied to an insulating substrate which preferably consists of sapphire. 
     A coplanar conductor path arrangement of only two conductors is known from the &#34;Siemens Forschungs- und Entwicklungsberichten&#34;, see Vol. 5 (1976) No. 2, page 72-75, H. Fritzsche: &#34;Capacitances of Coplanar Microstrip Lines in Integrated Circuits&#34;, incorporated herein by reference. 
     The invention offers the advantage that a relatively high dielectric strength can be achieved which, when solid silicon techniques are used, can otherwise only be reproduced with extreme difficulty. A further advantage consists in that the monolithically integrated circuit corresponding to the invention is small in volume and can be produced with favorable cost. 
     A further development of the invention is that a plurality of coupling sub-capacitors each consisting of coplanar conductor path arrangements are arranged on the chip. The coupling sub-capacitors are commonly interconnected in a series arrangement to form a capacitive voltage divider. The intervals between the conductor paths are reduced in comparison to the intervals between the conductor paths in the case of a coupling capacitor consisting of one single coplanar conductor path arrangement. The sub-capacitors are also created with a precise symmetrical design when integrated. 
     A further development of the invention offers the advantage that the dielectric strength of the path between the input and the output of the overall circuit can be increased. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is the block circuit diagram of an integrated solid body relay which is designed in accordance with the invention and the individual circuit zones of which are arranged in integrated fashion on one single chip; 
     FIG. 2 is the block circuit diagram of an integrated capacitive coupler for signal transmission which is designed in accordance with the invention; 
     FIG. 3 is a cross-sectional view of a portion of a circuit constructed in accordance with the invention illustrating the arrangement of coplanar conductor paths 1, 2 in a passivation layer and on a substrate; 
     FIG. 4 is a cross-section through an arrangement corresponding to the invention of a plurality of coplanar conductor paths 1, 2 . . . n; 
     FIG. 5 illustrates the qualitative curve of the breakthrough field strength E max  in dependence upon a spacing d between the conductor paths 1, 2; 
     FIG. 6 is a gate circuit diagram of an integrated capacitive coupler designed in accordance with the invention; 
     FIG. 7 is a detailed circuit diagram forming part of the gate circuit diagram shown in FIG. 6 of an integrated capacitive coupler constructed in accordance with the invention; 
     FIG. 8 is a block circuit diagram of an integrated capacitive coupler for power transmission constructed in accordance with the invention; and 
     FIG. 9 is a detailed circuit diagram of the coupler illustrated in FIG. 8. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     As already mentioned, FIG. 1 is a simplified block circuit diagram of a switch which is monolithically integrated on a chip CH, and which is to switch a load external to the chip at the secondary side and contains electrical isolation means GT (solid body relay). If the primary circuit PS is to be supplied from the secondary side, in addition to a signal coupler SK which influences the secondary circuit SS, an energy transmission circuit, i.e. a power coupler EK arranged on the chip and designed substantially the same as the signal coupler SK, is also required. The signal path is referenced SW whereas the power supply path is referenced EW. 
     As already mentioned, FIG. 2 is the block circuit diagram of a circuit for a capacitive signal coupler. At the primary side P a high-frequency signal is produced by an oscillator OSZ (which is controlled by the signal input E arriving external to the chip) transmitted via the coupling capacitor C K  to the secondary side S, where it is amplified and preferably rectified (output signal A). 
     FIG. 3 illustrates the arrangement of an integrated coupling capacitor which, embedded into a passivation layer PASS, lies on an insulating substrate SUB (e.g. ESFI-SOS technology). The capacitance is produced by the coplanar conductor path arrangement 1-a-2. An arrangement of this type produces very high dielectric strengths which, using solid silicon technology, can otherwise only be achieved with great difficulty. On passivated surfaces the dielectric strength is in the region of several kV and the capacitance values are in the 100 pF-range. 
     ESFI-SOS technology is described in the brochure &#34;Siemens Halbleiterbauelemente fur die Elektronik&#34;, order no. B 10/1431, pages 60 and 61, incorporated herein by reference. 
     Since, given small spacings d, the breakthrough field strength E max  displays a sharp increase A (see FIG. 5) it can be advantageous to connect a plurality of coplanar capacitors (conductor paths) in series while simultaneously reducing the spacing thereby achieving high dielectric strengths and greater coupling capacitances (see FIG. 4). In this case the inner conductor paths (2 . . . n-1) do not carry a fixed potential. An increased dielectric strength of the multi-conductor arrangement is subject to dependent upon precise symmetrical design of the conductor paths which can be achieved relatively easily with current technology. 
     In accordance with FIGS. 3, 4 and 5, the breakthrough voltage (U DB ) for two conductors and n conductors is governed by 
     
         U.sub.DB12 ≈E.sub.12 ·a                   (1) 
    
     and 
     
         U.sub.DB1n ≈nE.sub.12 ·a                  (2) 
    
     In order to achieve an equal dielectric strength with n conductor paths we must have ##EQU1## if 
     
         C.sub.K1n &gt;C.sub.K12 
    
     and 
     
         a*&lt;a 
    
     A genuine gain can be achieved with respect to the quality (U DB  and C K ) and area of the coupling capacitor. 
     In order to further increase the coupling capacitance, the passivation layer should possess as high as possible a relative dielectric constant. 
     FIGS. 6 and 7 illustrate an example of a capacitive coupling circuit constructed for signal transmission in ESFI-SOS technology. The circuit elements are conventional transistors, diodes, resistors and capacitors (with the exception of C K ), as are used in ESFI technology. As a transmission path of this type displays band-pass characteristics, it is effective to tune the oscillator frequency to the middle frequency. This can be achieved by virtue of the selection of the number of stages in the ring oscillator OSZ or by modifying the inverter transit time. In this arrangement the input and output stage are referenced STE and STA respectively, the amplifier is referenced VS, and the rectifier is referenced GL. 
     The oscillator comprises a ring oscillator of a logic-linking element and at least one inverter connected to an output of the logic-linking element. The number of inverters being selected so as to determine the oscillating frequency of the oscillator. The oscillator frequency may also be determined by the transit time of the inverter. 
     FIGS. 8 and 9 illustrate an example of a power supply circuit as the power coupler EK and consisting of a capacitive coupler. The voltage component U+1 of an oscillator signal of high frequency (f osc ) is amplified and the oscillator signal is transmitted via C K  to the primary side. Here a current of the value U H  ·2 f osc  ·C K  flows. The current is rectified and the storage capacitor ESP is charged as a power store. The stored energy is adequate to temporarily supply the primary circuit with current in the form of short duration pulses. 
     Although various minor modifications may be suggested by those versed in the art, it should be understood that we wish to embody within the scope of the patent warranted hereon, all such embodiments as reasonably and properly come within the scope of our contribution to the art.