Abstract:
A system and method for supplying power to a load and for controlling the power factor presented to the power line. Output voltage is controlled by a digital, outer, control loop, and inner, analog, control loop causes the input current to be substantially proportional to the input voltage at any particular point in the power line cycle. Thus, the system presents a load to the power line that appears to be purely resistive. The use of an analog multiplier is not required, nor is sampling of input voltage. Limiting of inrush current provides for brown-out protection and soft-start.

Description:
RELATED APPLICATIONS  
       [0001]     This application claims the benefit of earlier-filed provisional application Ser. No. 60/592,377, filed on Aug. 2, 2004 and entitled “Method and Controller Circuitry for Improved Performance Switch-Mode Converters”. 
     
    
     FIELD AND BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to the field of switching power converters. More particularly, the present invention relates to a method and circuitry for improving the input current and/or output voltage regulation of switching power converters.  
         [0003]     Currently, there are several types of power converters which are widely used for DC-to-DC, DC-to-AC, AC-to-DC and AC-to-AC power conversion. In some applications the purpose of the converter is to provide a regulated output voltage. In other applications the purpose of the power conversion scheme is to shape the input current at the input terminals of the converter so that the input current will follow the shape of the input voltage. For example, in a power converter known in the art as an Active Power Factor Correction (APFC) converter, the role of the converter is to ensure that the current drawn from the AC power line is in phase with the line voltage with minimum high-order harmonics. A typical and well-known implementation of an APFC converter is illustrated in  FIG. 1  (prior art). In  FIG. 1 , input voltage V ac  is rectified by diode bridge D 1  and fed to a “Boost” or “Step-up” converter that includes an input inductor L in , a transistor Q 1 , a high frequency rectifier D 2 , an output filter capacitor C o  and a load R L . A power switch Q 1  is driven by a high frequency control signal having a duty-cycle D ON  so as to force an input current I ina  to follow the shape of rectified input voltage V inR , in which case the power converter behaves essentially as a resistive load on the AC power line; i.e., the power factor (PF) is unity.  
         [0004]     The growing use of APFC converters is driven by the concern for the quality of AC power line supplies. Injection of high harmonics into the power line, and poor power factor in general, are known to cause many problems. Among these are lower efficiency of power transmission, possible interference to other electrical units connected to the power line and distorted shape of the line voltage. In light of the practical importance of APFC converters, many countries have adopted, or are in the process of adopting, voluntary and mandatory standard and statutes, which set limits on the permissible current line harmonics injected by any given electrical equipment powered by the AC mains, in order to maintain relatively high power quality. Another advantage of an APFC converter is that it allows a better exploitation of the power that can drawn from a given AC power line. Without power factor correction, the current drawn from AC power line includes a relatively high level of unwanted harmonics, which may be greater than the magnitude of the first harmonic of the current, the latter being the only component that contributes real power to the load. The generally undesirable I 2 R heating of wiring and motor and transformer windings is proportional to the square of the rms value of the current, which includes contributions from all harmonics. Additionally, protection elements, such as fuses and circuit breakers, generally respond to the rms value of the current. Consequently, the rms value of the current limits the maximum power that can be drawn from the line. In equipment having power factor correction the rms current essentially equals the rms value of the first harmonic of the current (due to the suppression of higher harmonics) and, hence, the power that can be drawn from the line essentially reaches the maximum theoretical value. It is thus evident that the need for APFC circuits is widespread and that economical implementation of such circuits is of prime importance. Cost is of great concern considering the fact that the APFC is generally an additional expense not directly related to the basic functionality of the equipment in which the APFC converter is included.  
         [0005]     Common APFC circuits generally operate in closed feedback configurations. For example, in the circuit illustrated in  FIG. 1  (prior art) a power factor correction (PFC) controller CONT samples an input current I ina  and generates pulses D ON  in order to drive a power switch Q 1  such as to force a current I ina  in an inductor L in  to follow the shape of a rectified input voltage V inR . Input current I ina  is adjusted for any given load R L  by monitoring output of the voltage divider R 1 , R 2  to form a low-voltage sense voltage V od  proportional to an output voltage V O , comparing it to a desired value for V O  and applying a resulting error signal to adjust D ON . Controller CONT could be based on analog circuitry.  
         [0006]     In the circuit illustrated in  FIG. 2  (prior art) a controller CONT_D is implemented as digital circuitry. In this system the shape of the rectified power line voltage V inR  is sampled by utilizing voltage V inR , which is obtained from voltage divider R a , R b . In this case V inR  is used as the reference voltage for the desired shape of input current I ina . Controller CONT_D also receives a voltage V Rs , measured across a sense resistor R s  and proportional to input current I ina . By applying a preprogrammed control algorithm, CONT_D generates pulses D ON  in order to drive power switch Q 1  such as to force inductor current I ina  to follow reference voltage shape V inR . Current I ina  is adjusted for any given load R L  by monitoring output voltage V o  via voltage divider R 1 , R 2  to generate a reference signal V od  that is applied in the algorithm of CONT_D to adjust D ON  so as to keep V o  close to a predetermined level.  
         [0007]     A digitally implemented controller has numerous advantages compared to an analog controller, such as the ability to adjust and optimize the control functions by re-programming the controller, even after installation, the robustness and stability of digital circuitry, as compared to analog circuitry, the ease of including remote control and monitoring functions via a communication interface, and the utilization of sophisticated new circuitry resulting from the rapid advanceme of digital VLSI technology. Notwithstanding the many advantages of digital controllers, cost is still an obstacle that makes wide usage of this approach uneconomical in many applications. The main reason for the high cost is the requirement for a relatively wide-bandwidth control loop. In an APFC system two feedback loops are recognized: an “inner” current-control loop and an “outer” voltage-control loop. In the inner, current, loop the input current is sensed and the required control signal having an appropriate duty-cycle is generated according to a predetermined algorithm. The bandwidth of this current-control loop must be wide, corresponding to a short response time. This helps to quickly correct any deviation of the current from the required value. On the other hand, the voltage-control loop needs to be slow-responding because its function is to correct the parameters of the inner loop so that the target input current will correspond to the power drawn by the load. In fact, a fast-responding outer loop is considered harmful because it will cause undesired distortion of the input current due to modulation by the ac ripple of the output voltage. This phenomenon is well known to persons trained in the art and this is why the design of the outer loop generally specifies a narrow bandwidth.  
         [0008]     The requirement for a wide bandwidth for the inner current-control loop implies that, in the case of a digital controller, the rate of sampling of the input current signal must be high. This implies that the analog-to-digital (A/D) converter of the digital controller (see  FIG. 2 ) must include fast-responding circuitry of high accuracy in order to provide the required performance of the inner loop. The need for a wide-bandwidth inner loop is demonstrated in detail by considering an APFC control algorithm that does not require sensing of input voltage, as seen in U.S. Pat. No. 6,307,361, to Ben-Yaakov et al., “Method and Apparatus for Regulating the Input Impedance of PWM Converters” incorporated by reference for all purposes as if fully set forth herein.  
         [0009]     In  FIGS. 1 and 2 , V a  (the voltage at node “a”) is a cyclic pulsating voltage having magnitude V o  during T OFF  when Q 1  is in a non-conductive state, and zero during T ON , when Q 1  is in a conductive state. Consequently, the average value of V a  is:  
               〈     V   a     〉     =         V   O     ⁢     T   OFF         T   S               (   1   )             
 
 wherein T S  is the Pulse Width Modulated (PWM) switching period, with T S =T OFF +T ON , and the angle-brackets (         ) imply an average value over a switching period. 
 
         [0010]     Equivalently,  
               〈     V   a     〉     =       V   O     ⁢     D   OFF     ⁢           ⁢   wherein             (   2   )                 D   OFF     =       T   OFF       T   S               (   3   )             
 
         [0011]     Similarly, D ON  is defined as:  
               D   OFF     =       T   ON       T   S               (   4   )             
 
 corresponding to when Q 1  is in a conductive state. 
 
         [0012]     The average voltage across inductor L in  is (V inR - &lt;V a &gt;) and the resulting average current &lt;I ina &gt; will be:  
               〈     I   ina     〉     =              V   inR     -     〈     V   a     〉         j2   ⁢           ⁢   π   ⁢           ⁢     L   in     ⁢   f                    (   5   )             
 
 wherein f is the first harmonic component of the input current. 
 
         [0013]     As has been shown in a number of publications (e.g., Ben-Yaakov, S. and Zeltser, I., “The dynamics of a PWM boost converter with resistive input.” IEEE Trans. Industrial Electronics, 46, pp. 613-619, 1999), the control law required to insure that the input terminal of the APFC will exhibit a resistive nature and be equivalent to a resistance R e  is:  
               D   off     =         R   e       V   o       ⁢     〈     I   ina     〉               (   6   )             
 
         [0014]     The block diagram of  FIG. 3  illustrates the interaction between Equations (5) and (6). The closed-loop response of this system is given by:  
                 I   ina       V   inR       =              1     R   e       ⁢     1     1   +       j2   ⁢           ⁢   π   ⁢           ⁢   f       2   ⁢           ⁢   π   ⁢           ⁢     f   o                    ⁢           ⁢   wherein   ⁢     :               (   7   )                 f   O     =       1     2   ⁢           ⁢   π       ⁢       R   e       L   in                 (   8   )             
 
         [0015]     Equation (8) implies that good tracking  
       (         I   ina       V   inR       ≅     1     R   e         )       
 
 is obtained up to the break frequency f o , at which point the loop gain of the system approaches unity. This implies that for proper operation, the controller should be capable of processing signals up to the frequency f o . This is illustrated by considering, for example, a 1 kW APFC stage operating from a 220 Vac line and with L in =1 mH. In this case:  
           R   e     ⁡     (     1   ⁢           ⁢   kW     )       =         220   2       10   3       =       48   ⁢           ⁢   Ω   ⁢           ⁢   and   ⁢           ⁢       f   o     ⁡     (     1   ⁢           ⁢   kW     )         =     7.6   ⁢           ⁢   kHz             
 
         [0016]     However, if the load power drops, say, to 5% of its nominal value, we find: 
 
f o (50 W)=153 kHz 
 
         [0017]     It will be clear to those trained in the art that the required sampling rate for this case is at least 500 kHz to avoid instabilities or poor dynamic response due to low sampling rates and sampling delays.  
         [0018]     In order for the inner, current-control loop to be sufficiently accurate, both the resolution of the A/D and that of the PWM circuitry of the digital controller of  FIG. 2 ) need to be high. Because the resolution of the PWM signal of a digital controller is limited by the clock signal, the requirement for a high-resolution PWM signal implies that the digital controller must have a high clock frequency. For example, if the converter runs at a switching frequency of 100 kHz and the required resolution of the PWM signal is 1:1000 (10 bits resolution) then the required clock frequency will be 100 MHz.  
         [0019]     In contrast to the strict requirements of the inner loop for a fast sampling rate, high accuracy of A/D conversion, and high clock frequency for generating a high-resolution PWM signal, the outer voltage loop can use a low sampling-rate A/D of relatively low accuracy. This is due to the fact, discussed above, that the required bandwidth for the outer loop is small. Typical values for bandwidth are 10 Hz (see again Ben-Yaakov, S. and Zeltser, I., “The dynamics of a PWM boost converter with resistive input.”). The resolution of the A/D needed for the outer loop is relatively low because, in most practical applications, the required accuracy of V o  is relaxed. This is possible because the APFC stage is normally followed by a DC-DC converter that controls the final output voltages of the system. Such a DC-DC converter is typically rather insensitive to variations in input voltage. Notwithstanding the relaxed requirements of the outer loop, it is the inner loop that sets the specification of the digital controller for an APFC per the prior art of  FIG. 2 . Consequently, in this prior art implementation, the required bandwidth for the inner, current-control loop, and the need for a high-resolution PWM signal dictate the selection of a digital controller with a very high clock frequency and a high-resolution, fast-sampling A/D. This significantly increases the cost of the digital solution as compared to the analog approach for APFC controllers.  
         [0020]     Another engineering issue that needs to attention in the design of AC-DC converters is the control of the inrush current. That is, limiting the high current that will develop when power is applied to the system while bus capacitor C o  is discharged or at low voltage. Prior-art solutions to this problem fall into two categories. One approach is to insert a thermistor having a negative temperature coefficient in series with the input terminals. Because the resistance of the thermistor is large when the thermistor is cold, the thermistor will limit the inrush current. Once capacitor C o  has been charged and the thermistor has warmed up the resistance of the thermistor will decrease and the power dissipated in the thermistor will be reduced. Nonetheless, the thermistor will dissipate power even when warm, and therefore reduce the overall efficiency of the system. Furthermore the high steady-state temperature of the thermistor can reduce the reliability of the converter by introducing a hot spot. Another problem with the thermistor solution is that after a short brown-out period (reduction of line voltage) the inrush current resulting from restoration of full line voltage can be high because the thermistor may not have had enoughtime to cool down sufficiently during the brown-out.  
         [0021]     A second approach to solving the inrush current problem is the introduction of an inrush-current control element activated by extra analog circuitry plus some logic circuitry operative to sense the instant of application of power to the system, as seen in U.S. Pat. No. 6,493,245 to Phadke, “Inrush Current Control for AC to DC Converters”, incorporated by reference for all purposes as if fully set forth herein. It is also desirable that the inrush-current control circuitry be capable of detecting a power-line brown-out so as to activate again the inrush current control element when full line voltage is restored. It is thus clear that the prior-art circuitry needs to be rather extensive, reducing the reliability, and increasing the manufacturing cost, of AC-DC converters.  
         [0022]     In the foregoing discussion, emphasis has been placed on AC-DC converters with respect to the alternative methods for controlling such systems. However, the control issues illustrated above for APFC systems are also relevant to DC-DC switch-mode converters. In a typical prior-art converter, as illustrated schematically in  FIG. 4 , the objective of controller CONT is to stabilize output voltage Vo despite changes in load and input voltage. A typical DC-DC converter will include at least one switching element Q 1 , an inductor L in , and an output capacitor C o . For enhanced performance, both inductor current I ina  and output voltage Vo are sensed by controller CONT and used to generate the gate PWM gate pulse (D on ). The purpose of sensing the inductor current is to make the inductor behave as a current source and thus reduce the small-signal transfer function of the power stage to that of a first-order system. This decreases the phase delay of the system and therefore helps to achieve a fast feedback response. As is well known in the art, the current-control feedback loop needs to have a wide bandwidth as compared to the voltage-control feedback loop. Hence, as in the case of the APFC systems detailed above, a digital controller for a DC-DC converter will require a high clock frequency and a high sampling-rate A/D converter.  
         [0023]     As in the cases of AC-DC and DC-DC converters, a digital controller for DC-AC inverters will suffer from similar drawbacks. It is thus clear that, notwithstanding the many potential advantages of a digital controller for power switch-mode systems, prior art implementations are complex and costly.  
       SUMMARY OF THE INVENTION  
       [0024]     There is thus a widely recognized need for, and it would be highly advantageous to have, controllers for switch-mode power systems that have the features of digital circuitry without the need for a high sampling-rate A/D and high-frequency clock. One, some or all of the below objectives may be realized in embodiments of the present invention.  
         [0025]     It may be further desirable that a controller for an APFC system be able to be operated in an advanced manner in which there is no need to sample the input voltage, and be able to cope with the large bandwidths required by such a control scheme.  
         [0026]     It is an objective of the present invention to provide circuitry for simplifying the construction, and increasing the reliability and flexibility, of controllers for switch-mode power systems.  
         [0027]     It is another objective of the present invention to provide economical digital circuitry for improving the performance of switch mode controllers.  
         [0028]     It is another objective of the present invention to eliminate the need for a high-resolution, high sampling-rate A/D and high-frequency clock presently associated with digital controllers for switch-mode power systems.  
         [0029]     It is yet another objective of the present invention to provide controller circuitry that can integrate other functions, such as inrush current control and soft start, to simplify the construction, increase the reliability, and reduce the overall cost, of switch-mode converters.  
         [0030]     Other objectives and advantages of the present invention will become apparent as the description proceeds.  
       Definitions  
       [0031]     As used herein, unless otherwise specified, the term “line” refers to an electric power line having at least two conductors. Such lines include DC power lines and AC power lines. DC power lines include, but are not limited to, power lines wherein one conductor, referred to herein as a “neutral” conductor, is substantially at ground potential. AC power lines include, but are not limited to, power lines wherein one conductor is substantially at ground potential, and is known as a “neutral” conductor, and wherein another conductor is at a varying potential and is known as a “phase” or “hot” conductor.  
         [0032]     As used herein, unless otherwise specified, the term “duty-cycle” refers to the ratio of the time a pulse signal is in an on state to the total of the time the pulse signal is in the on state and the time the pulse signal is in a temporally adjacent off state.  
         [0033]     As used herein, unless otherwise specified, the term “off-duty-cycle” refers to the ratio of the time a pulse signal is in an off state to the total of the time the pulse signal is in the off state and the time the pulse signal is in a temporally adjacent on state.  
         [0034]     Aspects of embodiments of the present invention are directed to a method for controlling the operation of a switch-mode converter stage such that, in the case of an APFC, the input current will follow the input line voltage, thus appearing to the power line as a resistive load, and/or, in the case of a voltage regulator, to regulate the output voltage or, in the case of a DC-AC converter, to produce a desired voltage waveform at the output terminals of the converter. This may be accomplished according to the present invention by use of mixed-mode circuitry combining an analog portion and a digital portion. Accordingly, certain embodiments of the present invention may make optimal use of both analog technology and digital technology and eliminate the need for extremely high A/ID sampling rates and high-frequency clocks that increase the complexity and cost of purely digital controllers. Furthermore, the present invention also allows increasing the reliability of switch-mode converter systems by enabling the inclusion of additional functions such as inrush current control without adding considerable complexity and/or cost to the controller circuitry. A simplified diagram of a controller according to embodiments of the present invention is illustrated schematically in  FIG. 5 . The controller illustrated includes mixed-mode circuitry including an analog portion that is primarily for implementing an inner, current-control loop, and a digital portion that is for implementing an outer, voltage-control loop, carrying out logical decisions concerning delays following power failures or brown-outs, driving a Controlled Current Conducting Device (CCCD) used to control inrush current, and other functions that will become clear below.  
         [0035]     Accordingly, embodiments of the present invention may be characterized by utilizing analog circuitry for fast control loops and digital control for slow control loops and supervisory circuitry.  
         [0036]     Embodiments of the present invention may feature some or all of a switch-mode converter apparatus which has improved reliability, programmability features, and lower cost, compared to prior art, for switch-mode power converters, including at least an inductor, a controllable power switch connected in tandem with the inductor, and a mixed-mode controller.  
         [0037]     In some embodiments of the invention, the switch mode converter may include some or all of:  
         [0038]     a) voltage sampling circuitry, for sampling the instantaneous value of the output voltage level;  
         [0039]     b) inductor-current sampling circuitry, for sampling the instantaneous value of the inductor current;  
         [0040]     c) analog control circuitry fed by a signal proportional to the input current and which controls the timing of the switching of the controllable switch in response to input current so as to cause the waveshape of the input current to be essentially similar to the waveshape of the input voltage.  
         [0041]     d) digital control circuitry fed by a signal proportional to the output voltage and which produces a control signal that affects the analog circuitry so as to adjust the input current level to the load and thereby stabilize the input current level and/or output voltage to desired values. The digital circuitry, which may be implemented as embedded firmware or as software running on a data processor such as a computer or microcontroller, can also, optionally, control the operation of the inrush circuitry and/or soft start of the power converter.  
         [0042]     e) inrush current control circuitry operative to limit input current following power-on, operation of the inrush current control circuitry being controlled by the digital control circuitry.  
         [0043]     Preferably, the switch-mode converter may further include:  
         [0044]     f) input voltage sensing circuitry operative to sense the input voltage of the system.  
         [0045]     g) logic-based circuitry or a program operative to utilize the sensed signals of input voltage, input current and output voltage to produce logic commands operative to shift the converter circuitry from one operational mode to another.  
         [0046]     The analog control circuitry can, optionally, further include an amplifier operative to increase the signal level of the sensed input current, a comparator operative to compare the input current signal to a ramp voltage developing across a ramp capacitor, a controlled current source operative to charge the ramp capacitor, interface circuitry operative to interface the digital control circuitry with control terminals of the controlled current source, and a gate driver fed by the comparator and operative to drive the gate of the power switch.  
         [0047]     The inrush current control circuitry can optionally further include a Controlled Current Conducting Device (CCCD) in series with inductor L in  and controlled by the digital circuitry. During start-up the CCCD is set by the digital circuitry to limit the input current. After the main capacitor is charged the digital circuitry is operative to change the setting of the CCCD such that the CCCD will carry the full current with minimal voltage drop across the CCCD.  
         [0048]     According to embodiments of the present invention there may be provided an active power factor correction power converter system comprising an analog control circuitry to control an input current of said system; a digital control circuitry to control an output voltage of said system; a current sampling device in the path of said input current to indicate an instantaneous value proportional to said input current being an input current indication, wherein said digital control circuitry is adapted to produce an analog signal responsive to variations in said output voltage, and wherein said analog control circuitry is responsive to said analog signal.  
         [0049]     According to some embodiments of the present invention, there may be provided a method of controlling an input current and an output voltage in an active power factor correction power converter system comprising controlling an input current of said system by an analog control circuitry; controlling an output voltage of said system by a digital control circuitry; wherein said digital control circuitry is adapted to produce an analog signal responsive to variations in said output voltage, and wherein said analog control circuitry is responsive to said analog signal.  
         [0050]     According to further embodiments of the present invention, there may be provided an active power factor correction power converter system comprising an analog control circuitry to control an input current of said system; a digital control circuitry to control an output voltage of said system; a current sampling device in the ground path of said input current to indicate an average of an instantaneous value proportional to said input current being an input current indication; a first voltage sampling branch to indicate an instantaneous value of said output voltage being an output voltage indication; a comparator unit responsive to a signal proportional to said input current indication and to a ramp-type signal driven by a controllable current source; a controllable current source to control the rise rate of said ramp-type signal to responsive to said output voltage indication; and a second voltage sampling branch to indicate an instantaneous value of a rectified input voltage of said system being an input voltage indication, wherein said digital control circuitry is adapted to produce an analog signal responsive to variations in said output voltage, wherein said analog control circuitry is responsive to said analog signal, wherein said digital control circuitry further comprises a digital controller comprising logic unit, a digitally controlled analog output, an analog-to-digital converter and an input/output unit.  
         [0051]     According to further embodiments of the invention, there may be provided a method of controlling an input current and an output voltage in an active power factor correction power converter system comprising controlling an input current of said system by an analog control circuitry; controlling an output voltage of said system by a digital control circuitry, said digital control circuitry is adapted to produce an analog signal responsive to variations in said output voltage, receiving a signal proportional to an average of said input current being an input current indication; receiving a signal proportional to an instantaneous value of said output voltage being an output voltage indication comparing said signal proportional to said input current indication to a ramp-type signal; switching a current controllable shunt switch on whenever said signal proportional to said input current indication is bigger than said ramp-type signal and off when it is smaller than said ramp-type signal; controlling a rise rate of said ramp-type signal responsive to a deviation of said output voltage indication from a predetermined value; and controlling a maximum value of said input current by a controllable switching device in response to a signal from said digital control circuitry.  
         [0052]     According to yet further embodiments of the present invention, there may be provided a power converter system comprising a rectifying circuitry to rectify an AC power to DC power; an analog control circuitry to control a current drawn from said rectifying circuitry; a digital control circuitry to control an output voltage of said system; a current sampling device in the ground path of said input current to indicate an average of an instantaneous value proportional to said input current being an input current indication; a first voltage sampling branch to indicate an instantaneous value of said output voltage being an output voltage indication; a comparator unit responsive to a signal proportional to said input current indication and to a ramp-type signal driven by a controllable current source; a controllable current source to control the rise rate of said ramp-type signal to responsive to said output voltage indication; and a second voltage sampling branch to indicate an instantaneous value of a rectified input voltage of said system being an input voltage indication, wherein said digital control circuitry is adapted to produce an analog signal responsive to variations in said output voltage, wherein said analog control circuitry is responsive to said analog signal, and wherein said digital control circuitry further comprises a digital controller comprising logic unit, a digitally controlled analog output, an analog-to-digital converter and an input/output-unit.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0053]     The above and other characteristics and advantages of the invention will be better understood through the following illustrative and non-limitative detailed description of preferred embodiments thereof, with reference to the appended drawings, wherein:  
         [0054]      FIG. 1  (prior art) illustrates schematically an APFC boost converter based on an analog controller;  
         [0055]      FIG. 2  (prior art) illustrates schematically an APFC boost converter based on a digital controller;  
         [0056]      FIG. 3  (prior art) illustrates schematically, as a block diagram, a current-control loop of an APFC based on a controller which does not directly sense input voltage;  
         [0057]      FIG. 4  (prior art) illustrates schematically two-loop control of a Buck converter;  
         [0058]      FIG. 5  illustrates schematically a control scheme for a switch-mode converter according to the present invention;  
         [0059]      FIG. 6  illustrates schematically an APFC stage according to a preferred embodiment of the present invention;  
         [0060]      FIG. 7  illustrates schematically an APFC stage according to another embodiment of the present invention;  
         [0061]      FIG. 8  illustrates schematically a possible series transistor connection for implementing the CCCD of the present invention;  
         [0062]      FIG. 9  illustrates schematically a second possible series transistor connection for implementing the CCCD of the present invention;  
         [0063]      FIG. 10  illustrates schematically a possible use of SCRs in implementing the CCCD of the present invention;  
         [0064]      FIG. 11  illustrates schematically a buck converter stage according to an embodiment of the present invention;  
         [0065]      FIG. 12  illustrates schematically a parallel connection of multiple APFC stages according to an embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0066]     The present invention is of a power converter which can provide a desired output voltage to a load while presenting the power line with a load having desired characteristics, such as, for example, unity power factor.  
         [0067]     Referring now to the drawings,  FIG. 6  illustrates a possible embodiment of an APFC stage according to the present invention. The power stage includes an inductor L in , a main switch Q 1 , a main diode D 2 , and an output capacitor C o . The power stage also includes a relay REL having contacts connected in series with inductor L in . A charging resistor R limit  is placed across the contacts of relay REL so that when those contacts are non-conducting current will flow will be limited by R limit . According to the present invention, a mixed mode controller CONT_M, having an analog section and a digital section, samples input voltage, input current I ina , and output voltage V o . The input current signal is processed according to a predetermined control algorithm by the analog section of CONT_M to produce pulses to be applied to the gate of Q 1 . The digital section or CONT_M senses output voltages V o  and compares V o  to a desired, pre-programmed value, and produces a correction signal applied to the inner loop analog circuitry so as to adjust the input current to the load power at any given time. The digital section of CONT_M also senses the input voltage to detect the need for inrush current control. Before the system enters the normal state of operation the “normally open” contacts of inrush control relay REL are non-conducting and resistor R limit  is thus in series with inductor L in . Consequently, during “power-on” bus capacitor C o  will charge via resistor R limit , thus limiting the inrush current. Further, during the charging of capacitor C o  the digital section of CONT_M disables the analog section of controller CONT_M such that main switch Q 1  will be kept in the “off” state. Once the digital section of CONT_M has sensed that capacitor C o  is sufficiently charged, and if input voltage is detected to be within a pre-determined allowable region, the digital section of CONT_M activates relay REL so as to effectively bypass R limit  from the circuit. At the same time the digital section gradually reduces the disabling command to the analog section of CONT_M such that the duty-cycle D ON  of Q 1  will be allowed to increase, in accordance with the method known in the art as “soft start”.  
         [0068]      FIG. 7  illustrates schematically another embodiment of an APFC stage according to the present invention. Input current I ina  is sensed by sense resistor R s  and amplified by an amplifier A 1  operative to produce a signal K·I ina .proportional to I ina . A ramp generator including a controlled current source I S , a capacitor C ramp , and a switch Q ramp  is operative to generate a triangular waveform V ramp  that is compared to K·I ina  by a comparator COMP 1  operative to produce a signal having an off-duty-cycle D OFF  according to equation (6):  
         D   OFF     =         R   e       V   o       ⁢     〈     I   ina     〉             
         [0069]     A digital controller  10  is operative to adjust coefficient R e /V o  so as to match input current I ina  to load power. This is accomplished by comparing a measurement of output voltage V o  to a desired value for output voltage V o  and adjusting I S  to change the rate at which V ramp  increases during the charging of C ramp . For example, if the measured value of V o  is less than the desired value of V o , as would be the case after a decrease in load resistance R L , digital controller  10  increases I S , causing comparator COMP 1  to turn on earlier in the V ramp  cycle, in turn increasing I ina  and causing V o  to increase toward the desired value for V o . On the other hand, if the measured value of V o  is greater than the desired value for V o , as would be the case after an increase in load resistance R L , digital controller  10  decreases I S , causing comparator COMP 1  to turn on later in the V ramp  cycle, in turn decreasing I ina  and causing V o  to decrease toward the desired value for V o . These changes in I ina  change the equivalent resistance R e  seen by the power line, and thus adjust coefficient R e /V o  until output voltage V o  equals the desired target value for V o . As discussed above, this correction need not be fast, so a low sampling rate will suffice. As an example, not to taken as limiting the present invention, a system according to the present invention operating with a power line frequency of 50 Hz can have a bandwidth of 10 Hz in the voltage-control loopand hence a sampling rate of let then 1000 samples per second will suffice. It will be readily apparent to those skilled in the art that adjustment of I S  by digital controller  10  as described above will compensate for changes in component values in the system, as may occur with aging or temperature changes, other than changes in the voltage-sensing circuitry, and for changes in such parameters as input voltage V ac  and output resistance R L .  
         [0070]     Inrush current limiting and protection against a short circuit at the output is provided by a series switch, Q 4 , that is controlled in PWM mode by controller  10  so as to limit the inrush current and to disconnect the circuit when an overcurrent is detected by comparator COMP 2 . The output of COMP 2  also disables the drive to main switch Q 1  for quick protection. Diode D 4  is operative to provide a current path for current flowing through inductor L in  when switch Q 4  is in a non-conductive state. Other possible arrangements for providing inrush current limiting protection are depicted in  FIGS. 8, 9  and  10 .  
         [0071]     In  FIGS. 8 and 9  series transistor Q 4  is placed in the ground branches. This lowers the common-mode noise injection. The advantage of the arrangement of  FIG. 8  is the common ground for both Q 1  and Q 4 , eliminating the need for gate drive isolation for Q 4 . The advantage of the connection of  FIG. 9  is that it does not break the connection between the ground of Q 1  and the ground of load R L .  
         [0072]     In the connection of  FIG. 10 , the inrush current is controlled by thyristors SCR 1  and SCR 2 . The control signal is generated by the digital portion of mixed-mode controller CONT_M and fed to a pulse transformer T 1  via a transistor Q 5 . Input voltage sensing is facilitated by auxiliary diodes D aux1  and D aux2 .  
         [0073]     Implementation of the present invention in a DC-DC converter is shown in  FIG. 11 . In this example the power stage is of the “buck” topology, and includes a power switch Q 4 , an inductor L M , a diode D 3  and an output filter capacitor C o  to which a load R L  is connected. Pulse transformers T 3  and T 4  are used to monitor current through inductor L M , generating a voltage across a sense resistor R p . Resistor R f  and capacitor C f  filter out the high-frequency components and amplifier AMP 1  amplifies this voltage to a level that is compatible with the input signal range of a multiplier M. This signal, which is proportional to the average current through inductor L M , is multiplied by an error signal generated by the digital portion of mixed-mode controller CONT_M to correct changes in output voltage V o . The output signal of multiplier M is fed to a comparator COMP 3  that generates the PWM signal. This is accomplished by comparing the output of multiplier M to a triangular wave generated by a current source I S  that feeds a ramp capacitor C ramp  which is discharged by transistor Q ramp  at the desired switching frequency. The digital portion of mixed-mode controller CONT_M includes, in this embodiment, a logic core, such as a programmable microprocessor or logic array and digital input/output ports. Mixed-mode controller CONT_M also includes an A/D section and a capture and compare port, and is operative to generate a PWM signal. The error signal, which is a function of the deviation of output voltage V o  from a desired value, is converted to a PWM signal which is then filtered by low pass filter LPF to form an analog signal that is fed to multiplier M. In the controller scheme of  FIG. 11 , amplifier AMP 1 , multiplier M and the PWM modulator built around comparator COMP 3 , provide the wide bandwidth required for the inner, current-control loop so that the converter can quickly respond to fast current changes. Overall voltage stabilization, which, as mentioned above, requires a lower bandwidth, is controlled by the digital portion of the controller. By sampling the amplified signal that represents the average current, I av , through inductor L M , controller CONT_M can detect a persistent overcurrent situation and adjust the PWM signal accordingly. Controller CONT_M can also, optionally, send information about the loading level to a supervisory device, such as a computer (not shown) via a communication link COMM.  
         [0074]     Another embodiment of the present invention is a multiple converter system as illustrated schematically in  FIG. 12 . This figure shows n converters PF# 1  . . . PF#n that are powered from the line and connected in parallel to feed a single load R L . Inter-unit communication, facilitated by the present invention, allows for current sharing between units PF# 1  . . . PF#n so as not to overload any one of the units PF# 1  . . . PF#n and to evenly distribute power losses.  
         [0075]     While the invention has been described with respect to a limited number of embodiments, it will be appreciated that many variations, modifications and other applications of the invention may be made.