Abstract:
A timer for measuring a time period including a high frequency generating unit, a low frequency generating unit and a controller connected to the high and low frequency generating units, wherein the controller deactivates the high frequency generating unit during at least a portion of the time period, detects and counts predetermined portions of the signals provided by the high and low frequency generating units and counts a plurality of the portions of the currently active frequency generating unit.

Description:
CROSS-REFERENCE TO PREVIOUS APPLICATIONS  
       [0001]    This application is a continuation-in-part of U.S. Ser. No. 08/906,089 filed Aug. 5, 1997. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The present invention relates to a method and system for low power precision timing, in general and to a method and a device for providing improved power consumption, while maintaining precise timing, of a communication system in waiting mode, in particular.  
         BACKGROUND OF THE INVENTION  
         [0003]    Methods and devices for providing precise timing and precise time counting are known in the art. Such devices conventionally include a crystal for providing a basic frequency and a controller for accumulating the clock signals generated by the crystal. When such a system attempts to increase the accuracy of the counting mechanism, it utilizes a high frequency crystal which increases the resolution in time.  
           [0004]    It would be appreciated that frequency and energy are associated in a way that producing a higher frequency requires higher power to be provided thereto. The basic quantum rule is presented by the expression: 
           
         E=h·f 
       
           [0005]    wherein E represents energy, h represents Plank&#39;s coefficient and f represents frequency.  
           [0006]    In CMOS design, the following expression is used: 
           
         P=C·V 
         2 
         ·f 
       
           [0007]    wherein P represents power, C represents capacity and V represents voltage.  
           [0008]    Methods for managing power of a communication system in waiting mode are known in the art. A conventional communication system, in waiting mode has to detect hailing signals and open a communication channel when it detects a hailing signal which is addressed thereto.  
           [0009]    Conventional communication protocols, such as TDMA, determine time periods in which hailing signals are transmitted. State of the art communication systems, attempt to shut down their receiver, when out of these time periods, so as to save power. Such systems are described in U.S. Pat. No. 5,568,513 to Thomas et al and U.S. Pat. No. 5,224,152 to Harte.  
         SUMMARY OF THE PRESENT INVENTION  
         [0010]    It is an object of the present invention to provide a novel method and device for reducing power consumption of a communication unit in waiting mode.  
           [0011]    It is a further object of the present invention to provide a novel method and system for low powered timing.  
           [0012]    According to the present invention there is thus provided a timer for measuring a time period including a high frequency generating unit, a low frequency generating unit and a controller connected to the high and low frequency generating units. The controller deactivates the high frequency generating unit during at least a portion of the time period. The controller further detects and counts predetermined portions of the signals provided by the high and low frequency generating units. Furthermore, the controller counts a plurality of the portions of the currently active frequency generating unit.  
           [0013]    The timer can also include means, connected to the controller, for estimating the frequency of the low frequency generating unit.  
           [0014]    According to another aspect of the present invention, there is provided a method for providing an indication of a time period T which commences at time t 1  and expires at time t 2  the method including the steps of:  
           [0015]    activating a high timing level at time t 1 ;  
           [0016]    counting a first predetermined number M of predetermined cycle portions of the high timing level for determining a first partial time period;  
           [0017]    activating a low timing level at the end of the first partial time period; and  
           [0018]    counting a second predetermined number N of predetermined cycle portions of the low timing level.  
           [0019]    According to the invention, the method can further include a step of indicating the expiration of the time period at time t 2 .  
           [0020]    For example, the first predetermined number M and the second predetermined number N satisfy the following equation: 
           
         T=N×T 
         L 
         +M×T 
         H 
       
           [0021]    wherein T H  represents a time period determined by the predetermined cycle portions of the high timing level and T L  represents a time period determined by the predetermined cycle portions of the low timing level.  
           [0022]    The method of the invention, can further include a step of deactivating the high timing level after the step of activating the low timing level.  
           [0023]    The method can further include a step of calculating the position of a synchronization signal every predetermined synchronization time period. This time period can be determined according to the time period of a repetitive synchronization sequence. For example, in the communication standard IS-95 this time period is approximately 26.6 milliseconds.  
           [0024]    To enhance accuracy, the method of the present invention, can further include a step of estimating the frequency of the low timing level.  
           [0025]    According to a further aspect of the present invention, there is provided a communication system which includes a receiver, and a timer for measuring a time period. The timer includes a high frequency generating unit, a low frequency generating unit and a controller connected to the high and low frequency generating units. The controller is further connected to the receiver.  
           [0026]    The controller deactivates the high frequency generating unit during at least a portion of the time period, deactivates the receiver during at least another portion of the time period, detects and counts predetermined portions of the signals provided by the high and low frequency generating units and counts a plurality of the portions of the currently active frequency generating unit.  
           [0027]    The communication system of the invention, can further include means, connected to the controller and to the receiver, for estimating the frequency of the low frequency generating unit.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]    The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the drawings in which:  
         [0029]    [0029]FIG. 1 is a schematic illustration of a timing diagram of two timing levels, in accordance with a preferred embodiment of the present invention;  
         [0030]    [0030]FIG. 2 is a schematic illustration of a method for providing a time count of a predetermined time period T using the two timing levels of FIG. 1, in accordance with a further preferred embodiment of the present invention;  
         [0031]    [0031]FIG. 3 is a schematic illustration of a timing diagram of two timing levels, in accordance with another preferred embodiment of the present invention;  
         [0032]    [0032]FIG. 4 is a schematic illustration of a method for providing a time count of a predetermined time period T using the two timing levels of FIG. 3, in accordance with another preferred embodiment of the present invention;  
         [0033]    [0033]FIG. 5 is a schematic illustration of a timing diagram of two timing levels, in accordance with yet another preferred embodiment of the present invention;  
         [0034]    [0034]FIG. 6 is a schematic illustration of a timing system, constructed and operative in accordance with another preferred embodiment of the present invention;  
         [0035]    [0035]FIG. 7 is a schematic illustration of a method for operating the system of FIG. 6, providing a time count of a predetermined time period T using the two timing levels of FIG. 5, operative in accordance with another preferred embodiment of the present invention; and  
         [0036]    [0036]FIG. 8 is a schematic illustration of a timing system, constructed and operative in accordance with a further preferred embodiment of the present invention;  
         [0037]    [0037]FIG. 9 is a schematic illustration of a method, operative in accordance with another preferred embodiment of the present invention; and  
         [0038]    [0038]FIG. 10 is a schematic illustration of a timing scheme, according to the present invention.  
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0039]    The present invention overcomes the disadvantages of the prior art by providing a timing mechanism which includes two levels of timing.  
         [0040]    A high timing level, which provides high resolution timing and a low timing level which provides low timing resolution, combined with a low power consumption. The combination of these two timing levels, according to the invention, reduces power consumption significantly.  
         [0041]    Reference is now made to FIG. 1, which is a schematic illustration of a timing diagram of two timing levels, in accordance with a preferred embodiment of the present invention.  
         [0042]    Time period  10 , from t 1  to t 3 , represents a predetermined time period which needs to be counted and indicated. Timing level  12  is a high frequency timing level. Timing level  14  is a precise low frequency timing level. Maintaining timing level  12  requires more power than maintaining timing level  14 .  
         [0043]    Time period  10  can not be represented by a natural number of half cycles of the low timing level  14 . When t 1  is aligned with the rising point of the first cycle of the low timing level  14  then, t 3  occurs within the last cycle  16  of low timing level  14 .  
         [0044]    t 3  does not align with either a rise or a fall of a cycle of the low timing level  14 . Thus, the low timing level  14  can not be used to indicate t 3 . It will be appreciated that time period  10  can be represented by the expression: 
         
       T=N×T 
       L 
       +M×T 
       H 
       +ε; ε&lt;T 
       H 
     
         [0045]    wherein T represents time period  10 , T H  represents half of a single cycle of the high timing level, T L  represents half of a single cycle of the low timing level and M and N are natural numbers.  
         [0046]    It will be appreciated that a conventional oscillators and for that matter, crystal, incorporates and error. Accordingly, the T H  and T L  have errors ΔT H  and ΔT L , respectively. Thus, N and M are evaluated according to these errors so that 
         | T− ( N×T   L   +M×T   H )|≦Δ T   
         [0047]    wherein ΔT is a maximal predetermined error of time period T.  
         [0048]    t 2  represents a point in time where the last rise or fall of the low timing level  14 , which occurs before t 3 . At t 2 , the high timing level  12  is activated and the low timing level  14  is deactivated. Then, the high timing level  12  counts the time period from t 2  to t 3  and provides an indication of t 3 .  
         [0049]    Accordingly, the present invention provides high resolution timing mechanism, using a combination low timing level and high timing level, wherein the overall resolution is determined according to the resolution of the high timing level.  
         [0050]    Reference is now made to FIG. 2, which is a schematic illustration of a method for providing a time count of a predetermined time period T using the two timing levels of FIG. 1, in accordance with a further preferred embodiment of the present invention.  
         [0051]    In step  20 , the low timing  14  is activated at the beginning of time period T.  
         [0052]    In step  22 , N half cycles of the low timing level are counted, wherein  
       N   =       int        (     T     T   L       )       .                           
 
         [0053]    Right after these N half cycles, the high timing level  12  is activated and the low timing level  14  is deactivated (step  24 )  
         [0054]    In step  26 , M half cycles of the high timing level are counted, wherein  
       M   =           frac        (     T     T   L       )       ·     T   L         T   H       .                           
 
         [0055]    It will be noted that a compatible calculation using an integer function is also applicable for this step.  
         [0056]    In step  28 , the end of time period T is indicated.  
         [0057]    Reference is now made to FIG. 3, which is a schematic illustration of a timing diagram of two timing levels, in accordance with another preferred embodiment of the present invention.  
         [0058]    Time period  30 , from t 1  to t 3 , represents a predetermined time period which needs to be counted and indicated. Timing level  32  is a high frequency timing level. Timing level  34  is a precise low frequency timing level. Maintaining timing level  32  requires more power than maintaining timing level  34 .  
         [0059]    Time period  30  can not be represented by a natural number of half cycles of the low timing level  34 . When t 3  is aligned with the rising point of the first cycle of the high timing level  32  then, t 1  occurs within a cycle  36  of low timing level  34 . t 1  does not align with either a rise or a fall of a cycle of the low timing level  34 . Thus, the low timing level  34  can not be used to indicate t 3 .  
         [0060]    t 2  represents a point in time where the first rise or fall of the low timing level  34 , which occurs right after t 1 . The time period from t 2  to t 3  can be represented by a natural number of half cycles of the low timing level  34 .  
         [0061]    At t 2 , the low timing level  34  is activated and the high timing level  32  is deactivated. Then, the low timing level  34  counts the time period from t 2  to t 3  and provides an indication of t 3 .  
         [0062]    Reference is now made to FIG. 4, which is a schematic illustration of a method for providing a time count of a predetermined time period T using the two timing levels of FIG. 3, in accordance with another preferred embodiment of the present invention.  
         [0063]    In step  50 , the high timing level  34  is activated at the beginning of time period T.  
         [0064]    In step  52 , M half cycles of the high timing level are counted, wherein  
       M   =           frac        (     T     T   L       )       ·     T   L         T   H       .                           
 
         [0065]    Right after these M half cycles, the low timing level  34  is activated and the high timing level  32  is deactivated (step  54 )  
         [0066]    In step  56 , N half cycles of the low timing level are counted, wherein  
       N   =       int        (     T     T   L       )       .                           
 
         [0067]    In step  28 , the end of time period T is indicated.  
         [0068]    Some oscillators, after they are activated, require at least a predetermined period of time to stabilize, before they can produce constant stable frequency signal. Accordingly, the present invention provides a solution which enables utilizing such oscillators.  
         [0069]    Reference is now made to FIG. 5, which is a schematic illustration of a timing diagram of two timing levels, in accordance with a further preferred embodiment of the present invention.  
         [0070]    Time period  100 , from t 1  to t 6 , represents a predetermined time period which needs to be counted and indicated. Timing level  102  is a high frequency timing level. Timing level  104  is a precise low frequency timing level. Maintaining timing level  102  requires more power than maintaining timing level  104 .  
         [0071]    According to the invention, once t 1  is detected, using high timing level  102 , then, the low timing level  104  is activated. t 2  represents a point in time where the high timing level  102  and the low timing level  104  align, after which the high timing level  102  can be deactivated. Accordingly, the high timing level  102  is deactivated at time point t 3 . The time period from t 1  to t 2  is represented by M 1  half cycles of the high timing level.  
         [0072]    According to the present example, t 6  occurs within a cycle of the low timing level  104 . Accordingly, the low timing level  104  can not indicate t 6  with sufficient accuracy.  
         [0073]    Low timing level  104  counts a time period from t 2  to t 4 , at low power consumption. At t 4 , after the low timing level  104  has counted a predetermined number of half cycles N, then, the high timing level  102  is reactivated. It will be appreciated by those skilled in the art that conventionally, when a crystal oscillator is activated, it requires some time to stabilize thereby producing a constant frequency, as required.  
         [0074]    t 5  represents a point in time in which the high timing level  102  and the low timing level align. The low timing level  104  can be deactivated after t 5 .  
         [0075]    Then, the high timing level  102  counts M 2  half cycles, after which, the end of time period  100  can be indicated.  
         [0076]    Time period  10  can be represented by the expression: 
           T=N×T   L +( M   1   +M   2 )× T   H   
         [0077]    wherein T represents time period  10 , T H  represents half of a single cycle of the high timing level, T L  represents half of a single cycle of the low timing level and M 1 , M 2  and N are natural numbers.  
         [0078]    Reference is made now to FIG. 6 which is a schematic illustration of a timing system, generally referenced  200 , constructed and operative in accordance with another preferred embodiment of the present invention.  
         [0079]    System  200  includes a fast clock  202 , for producing a high frequency, a slow clock  204 , for producing a low frequency and a controller  206 , connected to the fast clock  202  and the slow clock  204 .  
         [0080]    The controller  206  controls each of the clocks  202  and  204  so as to activate, deactivate, count and moderate them. The controller  206  is also connected to a receiver  208 . The controller  206  provides the receiver timing frequencies. In the present example, the controller  206  is also capable of activating, deactivating, enabling and disabling the receiver  208 .  
         [0081]    Reference is also made to FIG. 7, which is a schematic illustration of a method for operating the system  200  of FIG. 6, providing a time count of a predetermined time period T using the two timing levels of FIG. 5, in accordance with another preferred embodiment of the present invention.  
         [0082]    In step  150 , a high timing level  102  (FIG. 5) is maintained at the beginning (t 1 ) of time period T (time period  100 ). Then, the controller  206  counts half cycles of the signal provided by the fast clock  202 , from t 1  (step  152 ).  
         [0083]    In step  154 , a low timing level  104  (FIG. 5) is activated. In the present example, the controller  206  activates the slow clock  204  and detects when the signals, provided by the slow clock  204  and the fast clock  202 , align (step  156 ). In the present example t 2  of FIG. 5 represents this alignment point. Then, the system  200  stops counting the signal of the fast clock and starts counting the signal of the slow clock.  
         [0084]    In step  158 , the system  200  stores the number of counts of the fast clock, from t 1  to t 2 , in a variable M 1 .  
         [0085]    In step  160 , the high timing level, represented by the fast clock  202 , is deactivated. In the present example, the controller  206  shuts down the fast clock  206  at t 3 . It will be noted that when the power consumption of system  200  is considerably lower when the slow clock  204  is operative then power consumption achieved when the fast clock  202  is operative. It will be further appreciated that when the controller  206  is connected to an external device, such as receiver  208 , then, the controller  206  may disable this device or shut it down, for further power consumption decrease.  
         [0086]    In step  162 , the N half cycles of the low timing level, are counted. In the present example, the controller  206  counts N half cycles of the signal provided by the slow clock  204 , according to the expression:  
       N   =       int        (       T   -       M   1     ×     T   H           T   L       )       .                           
 
         [0087]    In step  164 , the high timing level  106  is reactivated at T STABILIZE , which is a point in time before N half cycles of the low timing level are completed, required for stabilizing the high timing level. In the present example, the controller  206  reactivates the fast clock  202  at t 4 .  
         [0088]    In step  166 , a point in time is detected, where the high timing level  102  and the low timing level  104  align. It will be noted that this point in time should also represent the completion of counting N half cycles of the low timing level. In the present example, the controller  206  detects when the fast clock  202  and the slow clock  204  align (t 4 ).  
         [0089]    In step  168 , M 2  half cycles of the high timing level  102  are counted. In the present example, the controller  206  counts the half cycles of the signal provided by the fast clock  202  according to the expression:  
         M   2     =           frac        (       T   -       M   1     ×     T   H           T   L       )       ·     T   L         T   H       .                           
 
         [0090]    In step  170 , after completing the count of M 2  high timing level half cycles, the end of the time period T is indicated. In the present example, the controller  206  indicates the end of time period  100  to the receiver  208 .  
         [0091]    For example, in a cellular TDMA implementation, the slow clock  204  comprises a clock of up to 100 KHz and the fast clock  202  comprises a clock of up to 20 MHz. Such clocks are manufactured and sold by DAISHINKU CORP., a Japanese company which is located in Tokyo and Vectron, a US company, which is located in New-York. It will be noted that any oscillating mechanism is applicable for the present invention.  
         [0092]    In TDMA, a hailing signal lasts for about 50 ms and may be detected once every 1 second. A conventional timer would use fast crystal, thereby requiring energy E OLD  which is given by the following expression: 
           E   OLD   =P   OLD   ·T=C·V   2 ·2·10 7 ·1 sec 
         [0093]    A timer constructed according to the present invention, use fast crystal (for example at a frequency of 20 MHz) and a slow crystal (for example at a frequency of 100 KHZ) combination, thereby requiring energy E NEW  which is given by the following expression: 
           E   NEW   =P   NEW   ·T=C·V   2 ·(2·10 7 ·0.005 sec+1·10 5 ·0.95 sec) 
         [0094]    Accordingly, the ratio  
           E   NEW       E   OLD       &lt;     6      %                           
 
         [0095]    defines that using a timer constructed and operative, in accordance with the present invention, would decrease the power consumption of a cellular unit, in wait mode, by at least ninety-four percent.  
         [0096]    Low frequency crystals are generally susceptible to frequency shifts due to environmental changes with respect to temperature, humidity and the like. In communication implementation of the invention, which will be discussed hereinbelow, the frequency of the low timing level has to be evaluated from time to time.  
         [0097]    Accordingly, the receiver  208  provides an indication of the frequency of a received signal, which was originally sent by a referenced station. In cellular communication, such a reference station can be a cellular base station which conventionally comprises a high precision high frequency timing crystal, incorporated in a precise and stable frequency mechanism.  
         [0098]    The controller  206  utilizes the reference frequency, provided by the receiver  208 , to evaluate the frequency of the low timing level. This process is performed, thoroughly, before the system  200  enters waiting mode and constantly, during this waiting mode, each time that the receiver  208  is activated.  
         [0099]    Since, a typical duty cycle of the system takes no more than several seconds, the controller  206  is able to evaluate the frequency of the slow clock  204 , with enhanced accuracy.  
         [0100]    Reference is made now to FIG. 8 which is a schematic illustration of a timing system, generally referenced  300 , constructed and operative in accordance with a further preferred embodiment of the present invention.  
         [0101]    System  300  includes a fast clock  302 , a slow clock  304  and a timing controller  306  which is connected to the fast clock  302  and the slow clock  304 . The timing controller  306  includes a processor  318 , two counters  314  and  316 , which are connected to the processor  318  and an estimator  310 , which is connected to the processor  318 .  
         [0102]    The counter  314  counts portions of the signal provided by the fast clock  302  and is connected thereto. The counter  316  counts portions of the signal provided by the slow clock  304  and is connected thereto.  
         [0103]    The estimator  310  is further connected to clocks  302  and  304  and to a receiver  308 . The processor  318  is also connected to the receiver  308  and controls it. The receiver  308  receives signals from and antenna  312 .  
         [0104]    According to the present example, system  300  controls receiver  308 , thereby activating, deactivating and supplying it with operating frequency. Furthermore, the system  300  performs timely estimations of the frequencies provided by clocks  302  and  304 .  
         [0105]    At first, the processor  318  activates the receiver  308 . The receiver  308  receives an incoming reference signal from the antenna  312  and provides it to the estimator  310 . This signal includes a base frequency which is considerably accurate. The reference signal also includes synchronization data.  
         [0106]    The estimator  310  further receives signals from the clocks  302  and  304 . Then, the estimator  310  provides frequency estimations to the processor  318  with respect to the frequencies generates by clocks  302  and  304 .  
         [0107]    The processor  318  calculates values M and N, according to the estimations provided thereto. After the receiver  308  finished receiving the reference signal, the processor  318  employs wait mode thereby deactivating the receiver  308  for a predetermined waiting time period T.  
         [0108]    Then, the processor  318  operates the fast clock  302  and the slow clock  304 , so as to measure this predetermined waiting time period T, according to any of the methods described hereinabove.  
         [0109]    After the processor  308  indicated the end of time period T, it reactivates the receiver  308 , which in turn receives a short hailing sequence in the above reference frequency. This hailing sequence often includes a synchronization sequence.  
         [0110]    According to the present invention, the receiver  308  may provide an indication of the frequency of the reference signal or the signal itself, to the estimator  310 , which in turn, utilizes it to re-estimate the frequencies of the clocks  302  and  304  and provides their estimations to the processor  318 .  
         [0111]    The receiver  308  further provides the synchronization sequence to the processor  318 . Then, the processor  318  utilizes the information received from the receiver  308  and the estimator  310  to reassess M and N.  
         [0112]    Finally, if the hailing signal did not include an indication of the identity of the receiver  308 , then the receiver provides a command to the processor  318 , so as to re-enter wait mode.  
         [0113]    It will be appreciated that the method of the present invention is applicable to any communication system such as a cellular telephone, a pager, a wireless telephone. In addition, the present invention is also applicable to any device which may require a low power high resolution timer such as computers, calculators, alarm detectors and the like.  
         [0114]    The following example demonstrates an implementation of the present invention for CDMA communication standards IS-95 and IS-98.  
         [0115]    In CDMA, the short PN sequence (SPN) is a PN sequence, having a length of 2 15 , which is generated by a modified fifteen bit linear feedback shift register. This sequence is the main spreading component of the transmitted spread spectrum signal, with respect to the down-link direction.  
         [0116]    The pilot signal is generally a predetermined PN sequence which is transmitted by all of the base stations. Since each base station uses a unique offset of the PN sequence, then each mobile can synchronize to a selected base station by detecting the predetermined PN sequence, at the unique offset of that base station. It will be noted that among the plurality of signals, which are transmitted by a base station, the pilot signal channel is the most powerful one.  
         [0117]    The long code is basically a PN sequence having a length of 2 42 −1, which is used, in the down-link direction (i.e. from the base station to the mobile) for encryption and scrambling purposes. Each of these transmitted CDMA symbol is multiplied by a decimated long code bit, before transmission.  
         [0118]    CDMA uses a group of orthogonal sequences, also known as Walsh sequences, to distinguish the signals which are transmitted to various mobile units. Accordingly, each mobile unit can detect a signal which is destined for it, by multiplying the received signal by the Walsh sequence, temporarily assigned thereto.  
         [0119]    These CDMA standards enable dual mode operation of a mobile unit both as a telephone (mode-T) and as a pager (mode pager).  
         [0120]    When operating in mode-T, in waiting mode, the time period between two subsequent hailing messages can be set to predetermined values, between 1.28 and 5.12 seconds. When operating in mode-pager, the time period between two subsequent hailing messages can reach a maximum of 163.8 seconds. The method according to the present invention addresses both modes, in a combined manner.  
         [0121]    These CDMA standards impose strict frequency accuracy requirements, which most oscillators do not meet. Accordingly, the receiver has to compensate for any inaccuracy and error which are caused by the oscillators.  
         [0122]    In conventional sleep modes, the voltage controlled temperature compensated crystal oscillator (VCTCXO) is running, thus enabling the receiver to keep track of time (keeping a continuous count of Long code, SPN and the like). It will be noted that in a receiver which includes a VCTCXO and a chip set, the power consumption of the chip set in waiting mode is (I VCTCXO +C·V·Z·M)·V, wherein Z denotes the number fast clock counts in a single slow clock count.  
         [0123]    The method of the present invention shuts down the VCTCXO, during sleep mode and so, the time managing hardware unit runs according to a slow clock and is able to recover from the sleep mode and receive the paging channel. The recovery stage puts the system in a position in which it would be, had it not gone into sleep mode.  
         [0124]    CDMA IS-95 traffic and paging channels operate according to 20 ms frames. The SPN sequence repeats every 26.6 ms. According to the present invention, the sleep mode mechanism operates according to time units (frames) of 26.6 ms. Inventors have found that operating the sleep mode mechanism according to the SPN sequence time period, yields enhanced efficiency, since it “freezes” the SPN. It will be noted that the present invention can be implemented using a sleep mechanism, which operates according to any time period.  
         [0125]    The prior art methods, disable selected units of the chip set for the entire sleep period and hence, are able to recover only when this time period has elapsed. This poses a disadvantage, when the user enters a waking-up command, before the end of the sleep time period.  
         [0126]    According to the present invention, the sleep mode mechanism performs a calculation of the current state, at the end of each time unit (26.6 ms frame). Hence, the sleep mode mechanism, is able to process a waking-up command, received from the user, at any stage of the sleep time period.  
         [0127]    Reference is now made to FIG. 9, which is a schematic illustration of a method, operative in accordance with another preferred embodiment of the present invention.  
         [0128]    In step  400 , the receiver estimates the frequency of the slow clock with reference to the frequency of the fast clock, during an operation of paging reception.  
         [0129]    In step  402 , the receiver disabled the activity of most of the chip units in the chip-set, thereby entering sleep mode. The only hardware that remains active is responsible for counting the slow clock and compensating for drifts thereof.  
         [0130]    In step  404 , the receiver activates the slow clock counter and comparator which are responsible for waking up the disabled chip units of the chip-set at the next receiving slot.  
         [0131]    In step  406 , the receiver stops all of the time managing hardware units at a selected point in time, at which the receiver is at a certain state.  
         [0132]    In step  408 , the receiver advances the sleep mode timing mechanism. The slow clock counts estimated 26.6 ms frames. After each such estimated frame, the sleep mode mechanism advances the system 26.6 frame counter by one and at the same time, re-adjusts the long code state by 32768 steps (i.e. which are the number of long code steps in a 26.6 ms frame)  
         [0133]    In step  410 , the sleep mode mechanism compensates for any drift of the slow clock during sleep mode time. The drift is calculated as follows: 
         
       T=N×T 
       L 
       +M×T 
       H 
     
         [0134]    Each time unit (26.6 ms) is represented by X×(slow clock counts)+Y×(fast clock counts). Z denotes the number fast clock counts in a single slow clock count. W accumulates the number of additional fast clock counts during the sleep period. For every count of X slow clock counts, the sleep time mechanism performs the following operations:  
         [0135]    the sleep time mechanism accumulates additional Y counts into W.  
         [0136]    When W is equal or greater then Z, then the following count of time units (26.6 ms) will be performed according to X+1 slow clock counts instead of X slow clock counts and the sleep mode mechanism decreases W by Z counts.  
         [0137]    In step  412 , the sleep mode mechanism operates according to a waking up command. This command can either be generated internally by the sleep mode mechanism, at the end of a predetermined time unit (26.6 frame), which indicates that the sleep mode time-period has elapsed or it can be provided from the host.  
         [0138]    At this stage the sleep mode mechanism, enables the VCTCXO, and after the VCTCXO is stable, the sleep mode mechanism enables some of the disabled units of the chip-set. It is noted that the sleep mode mechanism awakes the VCTCXO a few cycles sooner, so that it will have enough time to stabilize.  
         [0139]    In step  414 , the sleep mode mechanism sets the time managing hardware unit to a new position, as will be explained in further detail herein below. It will be noted that at this step, the sleep mode mechanism reverts from slow clock time resolution to fast clock time resolution and compensates according to the remaining W accumulated fast counts.  
         [0140]    In step  416 , the sleep mode mechanism enables [re-activates] the remaining disabled chip units.  
         [0141]    In step  418 , the receiver uses a searching module for final tuning the position of the time managing HW units and is thus ready to receive the paging channel.  
         [0142]    Reference is now made to FIG. 10, which is a schematic illustration of a timing scheme, according to the present invention.  
         [0143]    [0143]FIG. 10 presents the timing signals of the chip-set fast clock  440 , the DSP clock  442  and the VCTCXO  444 , which are all shut down at the same time, in the beginning of the sleep mode time period.  
         [0144]    In the last frame  450 , the VCTCXO is enabled before the DSP clock and the chip clock, a predefined time before it is needed for running the DSP. It will be noted that this is done because the VCTCXO requires time to stabilize.  
         [0145]    The VCTCXO is then used by the HW to compensate for the remaining fast clock cycles, before reactivating the time managing HW unit in the regular operation mode.  
         [0146]    It will be noted that the slow clock accuracy is very low, with comparison to the 813 ns (which is the value of T C ) requirement of the communication standards. The accuracy of the slow clock is thus measured &amp; estimated when ever the fast clock is active and accurate (CDMA receiving).  
         [0147]    As explained herein above, operating the slow clock in sleep mode requires some parameters, which are measured, calculated, estimated and stored before entering sleep mode. The measurement and estimation of these parameters can be performed in many ways.  
         [0148]    These parameters include the number of slow clock counts in a time unit (26.6 ms frame), the number of additional fast clock counts in a time unit (26.6 ms frame), the number of fast clock counts in a single slow clock count, and the like.  
         [0149]    It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described hereinabove. Rather the scope of the present invention is defined only by the claims which follow.