Abstract:
An integrator circuit is provided in the present invention, which utilizes a first capacitor and a first switching unit to sample an input signal and carries out distribution of charges between the first capacitor and a second capacitor. The second capacitor is larger than the first capacitor in capacitance. The integrator circuit transmits the charges stored in the second capacitor to a node of the first capacitor which is coupled to a ground previously. Accordingly, a direct current voltage level of the first capacitor may increase, facilitating an increase in a direct current voltage level at the second capacitor. Thereby, the accuracy and linearity of the integrator circuit may improve.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to an integrator circuit, and more particularly, to an integrator circuit that has a high resolution and a small phase difference. 
         [0003]    2. Description of Related Art 
         [0004]    An integrator is a commonly used analog circuit for performing a mathematical operation of integration. Typically, a voltage integrator is formed by an electric circuit composed of capacitors and resistors. Since a current passing through a capacitor is relative to a rate of voltage change, i.e., a result of differentiating voltage at a time, a voltage across the capacitor is considered as a result of the operation of integration for an input voltage and a voltage across the resistor is considered as a differential result for the input voltage. In the related art, an operational amplifier is often applied in an integrator circuit or a differentiator circuit for adjusting the input impedance and the output impedance of the integrator circuit. 
         [0005]    Another well-known low frequency integrator is equipped with an Analog to Digital Converter (ADC) to convert an analog signal to a digital signal before the operation of integration is performed. However, the accuracy of results obtained from the integrator circuit is restricted by the resolution of the ADC. Even though the accuracy of the integrator can be enhanced by utilizing the ADC of a higher resolution, the associated cost for the integrator circuit increases accordingly. In addition, the conventional integrators generally require a low-pass filter to filter out high-frequency portions of signals before the performance of the operation of the integration. However, for the lower-frequency portions of the signal to be filtered out the integrators require larger capacitance, increasing overall manufacturing costs of such integrators and causing larger difference in phase and low frequency oscillation destabilizing system control. 
       SUMMARY OF THE INVENTION 
       [0006]    The present invention provides an integrator circuit which utilizes the charge distribution principle of capacitors to implement a low-frequency hybrid integrator circuit. The integrator circuit of the present invention is associated with a higher resolution and a lower difference in phase with reduced manufacturing cost. 
         [0007]    The present invention is directed to an integrator circuit which comprises a first energy storage component, a first switching unit, a second switching unit, and a second energy storage component. The first energy storage component is coupled between a first node and a second node. The first switching unit is coupled to the first node, an input terminal, the second node, and a ground terminal, for selectively electrically connecting the first node to the input terminal and the second node to the ground terminal. The second switching unit is coupled to the first node, the second node, and a third node, for selectively electrically connecting the first node to the third node and selectively transmitting a voltage at the third terminal to the second node. The second energy storage component is coupled between the third node and the ground terminal. 
         [0008]    In one aspect of the present invention, when the first switching unit electrically connects the first node to the input terminal and the second node to the ground terminal, the second switching unit disconnects the first node from the third node. 
         [0009]    In another aspect of the present invention, when the second switching unit electrically connects the first node to the third node and transmits the voltage at the first node (also at the third node) to the second node, the first switching unit disconnects the first node from the input terminal and the second node form the ground terminal. 
         [0010]    In another aspect of the present invention, the first switching unit comprises a first switch and a second switch. The first switch is coupled between the first node and the input terminal. The second switch is coupled between the second node and the ground terminal. Herein, the first switch and the second switch are controlled by a first control signal. 
         [0011]    In another aspect of the present invention, the second switching unit comprises a third switch, a first unit gain amplifier, and a fourth switch. The third switch is coupled between the first node and the third node. The input of the first unit gain amplifier is coupled to the first node. The fourth switch is coupled between the output of the first unit gain amplifier and the second node. Therein, the third switch and the fourth switch are controlled by a second control signal. 
         [0012]    In another aspect of the present invention, as the aforementioned first control signal is enabled, the second control signal is disabled. 
         [0013]    In another aspect of the present invention, the aforementioned integrator circuit further comprises a fifth switch coupled between the third node and the ground terminal. The above-mentioned first energy storage component in one implementation is a first capacitor. The second energy storage component in one implementation is a second capacitor, and the capacitance of the first capacitor is smaller than the capacitance of the second capacitor. 
         [0014]    In another aspect of the present invention, the aforementioned integrator circuit further comprises an output buffer unit coupled between the third node and an output terminal. The output buffer unit comprises a second unit gain amplifier, a sixth switch, a third unit gain amplifier, and a third capacitor. The input of the second unit gain amplifier is coupled to the third node. The sixth switch has a terminal coupled to the output of the second unit gain amplifier. The input of the third unit gain amplifier is coupled to another terminal of the sixth switch and the output of the third unit gain amplifier is coupled to the output terminal. The third capacitor is coupled between the input of the third unit gain amplifier and the ground terminal. 
         [0015]    In summary, the integrator circuit in accordance with the present technique utilizes the charge distribution principle of the capacitors to compress and store voltage signals into the capacitors, wherein the voltage signals is generated by having an input voltage sampled at each time interval, so that the linearity of the integrator circuit may increase. Moreover, the proposed integrator circuit in comparison with the conventional counterpart is associated with a higher accuracy, which is no longer restricted by the resolution of the ADC as the result. Furthermore, the integrator circuit may be associated with a reduced difference in the phase also. 
         [0016]    In order to further the understanding regarding the present invention, the following embodiments are provided along with illustrations to facilitate the disclosure of the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIG. 1  illustrates a block diagram of an integrator circuit according to an embodiment of the present invention; 
           [0018]      FIG. 2  illustrates a circuit diagram of the integrator circuit according to the embodiment of the present invention; and 
           [0019]      FIG. 3  illustrates a waveform diagram according to the embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0020]    The aforementioned illustrations and following detailed descriptions are exemplary for the purpose of further explaining the scope of the present invention. Other objectives and advantages related to the present invention will be illustrated in the subsequent descriptions and appended drawings. 
         [0021]    Please refer to  FIG. 1 , in which a block diagram of an integrator circuit according to an embodiment of the present invention is illustrated. The integrator circuit  100  comprises a first switching unit  110 , a first energy storage component  120 , a second switching unit  130 , a second energy storage component  140 , and an output buffer unit  150 . The first energy storage component  120  is coupled between a first node T 1  and a second node T 2 . The first switching unit  110  is coupled to the first node T 1 , an input terminal TIN, the second node T 2 , and a ground terminal GND for selectively electrically connecting the first node T 1  to the input terminal TIN and the second node  12  to the ground terminal GND. The second switching unit  130  is coupled to the first node T 1 , the second node T 2 , and a third node T 3 , for selectively electrically connecting the first node T 1  and the third node T 3  and selectively transmitting a voltage at the third node T 3  to the second node  12 . The second energy storage component  140  is coupled between the third node T 3  and the ground terminal GND. The output buffer unit  150  is coupled between the third node T 3  and an output terminal TOUT. 
         [0022]    When the first switching unit  110  electrically connects the first node T 1  to the input terminal TIN and the second node T 2  to the ground terminal GND, the second switching unit  130  is configured to disconnect the first node T 1  from the third node T 3 . When the second switching unit  130  electrically connects the first node T 1  to the third node T 3  and transmits the voltage at the third node T 3  to the second node T 2 , the first switching unit  110  is configured to disconnect the first node T 1  from the input terminal TIN and the second node  12  from the ground terminal GND. The first switching unit  110  is used to primarily determine a sampling rate for sampling of an input signal VIN. When the first node T 1  and the input terminal TIN are conducted (i.e., connected to each other) and the second node  12  and the ground terminal GND are conducted (i.e., connected to each other), the input signal VIN is sampled once. The voltage of the input signal VIN may be stored in the first energy storage component  120 , and then the first switching unit  110  may stop the conduction between T 1  and TIN and T 2  and GND. The second switching unit  130  electrically connects the third node T 3  to the first node T 1  and transmits the voltage at the first node T 1  (also at the third node T 3 ) to the second node T 2  so as to boost up an original voltage of the first energy storage component  120 . Meanwhile, charges stored within the first energy storage component  120  may be distributed over the first energy storage component  120  and the second energy storage component  140  for boosting up the voltage at the third node T 3 , thereby achieving the effect of voltage integration. 
         [0023]    Additionally, it is worth noting that the first switching unit  110  and the second switching unit  130  are mainly used for switching conduction paths. In one implementation, the first switching unit  110  may be a plurality of switches, multiplexers, or switching components, but is not limited thereto. The first energy storage component  120  and the second energy storage component  140  may be implemented by a single capacitor or a plurality of capacitors in parallel or series connections, but is not limited thereto. The output buffer unit  150  is mainly used to adjust the output impedance. In one implementation, the output buffer unit  150  is a buffering circuit or a gain amplifier, but is not limited thereto. 
         [0024]    Any implementing details in accordance with the embodiment of the integrator circuit according to the present invention are further illustrated as following. Please refer to  FIG. 2  in conjunction with  FIG. 1 .  FIG. 2  illustrates a circuit diagram of the integrator circuit according to the embodiment of the present invention. In the integrator circuit  200  shown in  FIG. 2 , the first switching unit  110  comprises a first switch SW 1  and a second switch SW 2 . The second switching unit  130  comprises a third switch SW 3 , a fourth switch SW 4 , and a first unit gain amplifier GA 1 . The first energy storage component  120  is implemented by a first capacitor C 1  and the second energy storage component  140  is implemented by a second capacitor C 2 . The output buffer unit  150  comprises a second unit gain amplifier GA 2 , a third unit gain amplifier GA 3 , a sixth switch SW 6 , and a third capacitor C 3 . The integrator circuit  200  further comprises a fifth switch SW 5  coupled between the third node T 3  and the ground terminal GND, for transmitting the charges stored in the second capacitor C 2  to the ground terminal GND so as to reset the integrator circuit  200 . 
         [0025]    The first capacitor C 1  is coupled between the first node T 1  and the second node T 2 . The second capacitor C 2  is coupled between the third node T 3  and the ground terminal GND. The first switch SW 1  is coupled between the first node T 1  and the input terminal TIN. The second switch SW 2  is coupled between the second node T 2  and the ground terminal GND. The third node SW 3  is coupled between the first node T 1  and the third node T 3 . The input of the first unit gain amplifier GA 1  is coupled to the first node T 1 . The fourth switch SW 4  is coupled between the output of the first unit gain amplifier GA 1  and the second node T 2 . The second unit gain amplifier GA 2  is coupled between the third node T 3  and the sixth terminal SW 6 . The third unit gain amplifier GA 3  is coupled between another terminal of the sixth switch SW 6  and the output terminal TOUT. The first unit gain amplifier GA 1 , the second unit gain amplifier GA 2 , and the third unit gain amplifier GA 3  are implemented by operational amplifiers with negative feedback, but are not limited thereto. Moreover, it is worth noting that the connecting relationship of the aforementioned components includes direct connection, indirect connection, or a combination of the direct connection and the indirect connection, but is not limited thereto as long as the transmission function for the electronic signals can be achieved. 
         [0026]    The first switch SW 1  and the second switch SW 2  are controlled by a first control signal CON 1 , and the third switch SW 3  and the fourth switch SW 4  are controlled by a second control signal CON 2 . When the first control signal CON 1  is enabled, the first switch SW 1  and the second switch SW 2  are conducted (i.e., closed); on the other hand, when the first control signal CON 1  is not enabled the aforementioned switches SW 1  and SW 2  are not conducted (i.e., opened). When the second control signal CON 2  is enabled, the third switch SW 3  and the fourth switch SW 4  are conducted or closed with the aforementioned switches SW 3  and SW 4  opened when the second control signal CON 2  is not enabled. The waveforms of the first control signal CON 1  and the second control signal CON 2  are illustrated in  FIG. 3 , in which a waveform diagram of the embodiment according to the present invention is presented. Please refer to both  FIG. 2  and  FIG. 3 , when the operation of integration is performed, the first control signal CON 1  is used to control the sampling rate (frequency). Every time the first control signal CON 1  is enabled as shown in Waveform  310 , the voltage of the input signal VIN is stored in the first capacitor C 1  and the storing of the voltage of the input signal VIN may last for a period during which the first control signal CON 1  is enabled. As the first control signal CON 1  is enabled, the second control signal CON 2  is disabled. After the first control signal CON 1  is disabled, the second control signal CON 2  will be enabled as shown in waveform  240  so as to allow the charges stored in the first capacitor C 1  to be distributed to the second capacitor C 2 , so that the voltage of the input signal VIN may be stored in the second capacitor C 2 . 
         [0027]    As the second control signal CON 2  is enabled, the third switch SW 3  and the fourth switch SW 4  are conducted or closed. Therefore, the voltage at the third node T 3  may be transmitted to the second node T 2  so as to boost up a direct current voltage level of the first capacitor C 1 . Consequently, a voltage differential between two ends of the first capacitor C 1  (or the direct current voltage level of the first capacitor C 1 ) may be added to a direct voltage level at the third node T 3  before the second control signal CON 2  The operation of integration may be performed accordingly as a direct current voltage level at the second capacitor C 2  may increase as the result of the enablement of the second control signal CON 2 . The increase in the direct current voltage level at the second capacitor C 2  is considered as a compressed value of the input signal VIN and is proportional to a ratio of the first capacitor C 1  over the second capacitor C 2 . Assume C 1  represents the capacitance of the first capacitor C 1  and C 2  represents the capacitance of the second capacitor C 2 . After the first control signal CON 1  is enabled, a total amount of charges (Q) stored inside in the capacitor C 1  is illustrated in equation (1), and after the second control signal CON 2  is enabled, the increase in the direct current voltage level of the second capacitor C 2  may be represented in the following equation (2): 
         [0000]    
       
         
           
             
               
                 
                   Q 
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                       C 
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                       1 
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                       V 
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                       1 
                     
                     = 
                     
                       C 
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                       2 
                       × 
                       V 
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                        
                       
                         1 
                         ′ 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
             
               
                 
                   
                     V 
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                       1 
                       ′ 
                     
                   
                   = 
                   
                     
                       
                         C 
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                          
                         1 
                       
                       
                         C 
                          
                         
                             
                         
                          
                         2 
                       
                     
                     × 
                     V 
                      
                     
                         
                     
                      
                     1 
                   
                 
               
               
                 
                   ( 
                   2 
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         [0028]    Therein, in the aforementioned equations, V 1  represents the voltage value of the input signal VIN, while the input signal VIN is obtained, V 1 ′ represents an increase in a direct current voltage level at the third node T 3  after distribution of the charges (i.e., after the second control signal CON 2  is enabled). In other words, the direct current voltage level at the third node T 3  may increase because of the distribution of charges and V 1 ′ represents the increase. By controlling a time sequence of the first control signal CON 1 , the input signal VIN may be sampled accordingly. And by controlling a time sequence of the second control signal CON 2 , the charges will be redistributed to the second capacitor C 2 , increasing the direct current voltage level at the third node T 3  to ensure the operation of integration may be accomplished. When the input signal VIN is of a negative value (i.e., V 1  is negative), the increase in the direct current voltage level at the third node T 3  may be negative as well. In other words, a voltage difference across the two terminals of the second capacitor C 2  decreases, which also accomplishes the operation of integration. 
         [0029]    In addition, in the embodiment, the capacitance of the first capacitor C 1  is smaller than the capacitance of the second capacitor C 2 . For example, 100C 1 =C 2 . As such, the second capacitor C 2  may not cause an excessive voltage that falls outside an operating region of a circuit with the integrator circuit  200  of the present invention as the result of the operation of integration. 
         [0030]    Moreover, the fifth switch SW 5  can be used to reset the integrator circuit  200 . While the third control signal CON 3  is enabled, please refer to the waveform  360  in  FIG. 3 , the charges stored in the second capacitor C 2  may be transmitted to the ground terminal GNU so as to reset the integrator circuit  200 . Therefore, before the performance of the operation of integration, the third control signal CON 3  may be enabled to reset the direct current voltage level at the third node T 3 . 
         [0031]    In the output buffer unit  150 , the second unit gain amplifier GA 2  may transmit the direct current voltage level at the third node T 3  to the third capacitor C 3 , and the sixth switch SW 6  is used to maintain the charges stored in the third capacitor C 3  so as to avoid leakage current. The third unit gain amplifier GA 3  outputs a result of the operation of integration to the output terminal TOUT so as to generate the output signal VOUT. The output signal VOUT is proportional (i.e., the ratio of the capacitance of the first capacitor C 1  over the capacitance of the second capacitor C 2 ) to the result of the operation of integration for the input signal VIN. 
         [0032]    In summary, the principle of charge distribution of capacitors is applied to realize the low frequency integrator circuit in the present invention. The integrator circuit may compress, and store the sampled voltage into the capacitors, thereby enhancing the linearity of the integrator circuit. Furthermore, in the present invention, the operation of integration may be implemented in the absence of the ADC, so that the manufacturing cost of the entire circuitry may be reduced and an operation of integration of better accuracy may be achieved. 
         [0033]    The descriptions illustrated supra set forth simply the preferred embodiments of the present invention; however, the characteristics of the present invention are by no means restricted thereto. All changes, alternations, or modifications conveniently considered by those skilled in the art are deemed to be encompassed within the scope of the present invention delineated by the following claims.