Abstract:
A non-volatile semiconductor memory device includes a plurality of bit lines, a bit line contact corresponding to the bit lines, a first NAND string and a second NAND string, a first string selective transistor and a second string selective transistor, and a third string selective transistor and a fourth string selective transistor. The first and third string selective transistors are connected to each other, whereas the second and fourth string selective transistors are connected to each other. Each of the first and fourth string selective transistors has a first gate length and each of the second and third string selective transistors has a second gate length differing from the first gate length.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-218738, filed on Jul. 27, 2004, the entire contents of which are incorporated herein by reference. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a non-volatile semiconductor memory device configured so that a plurality of NAND strings are connected to each bit line. 
   2. Description of the Related Art 
   For example, NAND non-volatile memory devices have conventionally been formed with one active area AA (element isolation region) for each one bit line as shown in  FIG. 6 , and one row of NAND strings are controlled by the active area AA. In  FIG. 6 , reference symbol “SG” designates a selective gate, “WL” a word line, “CB” a forming region of a bit line contact. The active area AA includes a source/drain diffusion layer of a MOS transistor and a channel region. 
   With progress in high integration and refinement of a memory cell, an element isolation region has recently been narrowed and it has become difficult to ensure a forming region of a bit line contact CB. JP-A-H06-325581 discloses an arrangement of non-volatile semiconductor memory device to overcome the above-noted technical problem. According to the disclosed arrangement, two rows of NAND strings are formed so as to correspond to one bit line contact. Consequently, a forming region of a bit line contact which can be ensured corresponds to a total width of two rows of NAND strings, whereupon the bit line contact can readily be formed even when a conventional process is applied. 
   In a NAND non-volatile semiconductor memory device with two rows of NAND strings provided so as to correspond to one bit line, two selective gate transistors are provided for each NAND string. When each selective gate transistor is configured so that a threshold voltage differs between rows and columns, either one or any one of the NAND strings can be selected. In order that the NAND non-volatile semiconductor memory device may be arranged into such a configuration, when impurities are implanted during the forming of a selective gate transistor, dose is adjusted and ion implantation is then carried out, whereby a threshold voltage of the MOS transistor differs between rows and columns of NAND strings. 
     FIG. 7  shows an example of the above-described arrangement. A selective gate transistor as shown in  FIG. 7  includes enhancement mode MOS transistors TrE and depletion mode MOS transistors TrD both of which are formed alternately. Reference symbol “W” in  FIG. 7  designates a width of the word line WL, namely, a gate length of each MOS transistor. Each of the MOS transistors TrE and TrD can be formed by adjusting an amount of ion implantation of impurities (dose). 
   Conventionally, in a NAND non-volatile semiconductor memory device with two rows of NAND strings provided so as to correspond to one bit line, when impurities are ion-implanted in the forming of each selective gate transistor, dose is adjusted and ion implantation is then carried out, whereby a threshold voltage of the MOS transistor differs between rows and columns of NAND strings. However, when the design rule is rendered more strict, adjusting dose and then carrying out ion implantation becomes difficult due to misalignment of a mask. Moreover, since dopant is unnecessarily diffused during a thermal process, there is a possibility that memory cells and selective gate transistors in the vicinity of the diffused layer would adversely be affected. 
   BRIEF SUMMARY OF THE INVENTION 
   Therefore, an object of the present invention is to provide a non-volatile semiconductor memory device in which the bit line contact can be formed in a process similar to the conventional process and furthermore, adjusting dose and then carrying out ion implantation is unnecessary. 
   The present invention provides a non-volatile semiconductor memory device comprising a plurality of bit lines, a bit line contact provided so as to correspond to the bit lines, a first NAND string and a second NAND string both connected to a common bit line via the bit line contact, a first string selective transistor and a second string selective transistor both connected in series to the first NAND string between the first NAND string and the bit line contact, and a third string selective transistor and a fourth string selective transistor both connected in series to the second NAND string between the second NAND string and the bit line contact, wherein the first and third string selective transistors are connected to each other, whereas the second and fourth string selective transistors are connected to each other, and each of the first and fourth string selective transistors has a first gate length and each of the second and third string selective transistors has a second gate length differing from the first gate length. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects, features and advantages of the present invention will become clear upon reviewing the following description of the embodiment with reference to the accompanying drawings, in which: 
       FIG. 1  is a typical plan view of a memory cell region of a flash memory in accordance with the present invention; 
       FIG. 2  shows a schematic electrical arrangement of the memory cell region of the non-volatile semiconductor memory device; 
       FIG. 3  is a graph showing the gate length dependency of threshold voltage; 
       FIG. 4  is a view similar to  FIG. 1 , showing a second embodiment of the invention; 
       FIG. 5  is a view similar to  FIG. 1 , showing another embodiment of the invention; 
       FIG. 6  is a view similar to  FIG. 1 , showing a conventional arrangement; and 
       FIG. 7  is also a view similar to  FIG. 1 , showing another conventional arrangement. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   An embodiment of the present invention will be described with reference to  FIGS. 1 to 3 . The invention is applied to a NAND flash memory in the embodiment. 
     FIG. 2  schematically shows an electrical circuit arrangement of a memory cell region of a NAND flash memory device F of the embodiment. The NAND flash memory device F includes a plurality of bit lines BL 1  to BLn. A plurality of or two NAND strings AL 11  and AL 12  are connected to the bit line BL 1 . Each NAND string comprises a plurality of memory cells series connected into a NAND structure. The NAND string will hereinafter be abbreviated to “string.” A plurality of columns of the strings AL 11  and AL 12  are arranged in parallel to the bit line BL 1 , whereby a memory cell array MA is configured. Thus, in the memory cell array MA, strings AL 11  and AL 12  to ALn 1  and ALn 2  are formed so as to correspond to the bit lines BL 1  to BLn respectively. The strings AL 11  and AL 12  to ALn 1  and ALn 2  have the same configuration. More specifically, each string comprises a plurality of series-connected memory cell transistors Tr 1  to Trm the number of which is shown by “m” and as two squared by “k”, for example, 8, 16 or 32. In  FIG. 2 , subscripts “ 11 ” to “n 2 ” are affixed to the memory cell transistors Tr 1  to Trm so as to correspond to the NAND strings AL 11  to ALn 2  respectively. The memory cell transistors Tr 1  to Trm are arranged in a row direction and have gate terminals connected to word lines WL 1  to WLm respectively. 
   The bit lines BL 1  to BLn are provided with basic units U 1  to Un including the strings AL 11  and AL 12  to ALn 1  and ALn 2  respectively. The following will describe the basic unit U 2  including strings AL 21  and AL 22  corresponding to a bit line BL 2 . Two string selective transistors or selective gate transistors DSGT 121  and DSGT 221  are series-connected between a bit line contact CB 2  of the bit line BL 2  and a memory cell transistor Tr 121  provided at one end of the string AL 21 . Two string selective transistors or selective gate transistors DSGT 122  and DSGT 222  are series-connected between the memory cell transistor Tr 122  provided at one end of the string AL 22  and the bit line contact CB 2  of the bit line BL 2 . Each of the selective gate transistors DSGT 121  and DSGT 222  comprises a depletion mode MOS transistor, whereas each of the selective gate transistors DSGT 221  and DSGT 122  comprises an enhancement mode MOS transistor. 
   A source selective gate transistor SSGT 21  is provided between a memory cell transistor Trm 21  provided at the other end of the string AL 21  and a source line S. The source line S is set at a ground potential. 
   The following will describe the configurations of the selective gate transistors and memory cell transistors in the flash memory device F and regions occupied by the bit line contacts CB 1  to CBn with reference to  FIGS. 1 and 2 . Each of the memory cell transistors Tr 121  to Trm 21  constituting the string AL 21  has a source-drain diffusion layer (source-drain region) and a channel region both formed in an active area AA 21 . Furthermore, each of the memory cell transistors Tr 122  to Trm 22  constituting the string AL 22  has a source-drain diffusion layer (source-drain region) and a channel region both formed in an active area AA 22 . Furthermore, the selective gate transistors DSGT 121  and DSGT 221  have respective source-drain diffusion layers and channel regions formed in the active area AA 21 . The selective gate transistors DSGT 122  and DSGT 222  have respective source-drain diffusion layers and channel regions formed in the active area AA 22 . The source transistors SSGT 21  and SSGT 22  also have source-drain diffusion layers and channel regions formed in the active areas AL 21  and AL 22  respectively. 
   The transistor DSGT 121  has a drain diffusion layer connected structurally and electrically conductively to the bit line contact CB 2 , whereas the transistor DSGT 122  has a drain diffusion layer connected structurally and electrically conductively to the bit line contact CB 2 . A bit line selective voltage is applied between the bit line BL 2  and the source line S via the bit line contact CB 2 . In this case, two columns of the active areas AA 21  and AA 22  corresponding to the widths of two columns of strings AL 21  and AL 22  are ensured in the row direction as a forming region of the bit line contact CB 2 . The above-described configuration can ensure a wider forming region of bit line contact as compared with the conventional configuration in which only a forming region of the bit line contact CB corresponding to one column of active area AA as shown in  FIG. 6 . 
     FIG. 3  shows the gate length dependency of threshold voltage of the MOS transistor. In MOS transistors, a threshold voltage can be adjusted utilizing a short channel effect by adjustment of a gate length. Then, when a MOS transistor is formed so that the gate length L 1  (Lmask) becomes, for example, about 220 nm, as shown in  FIG. 3 , the threshold voltage Vt of the MOS transistor can be adjusted so as to be ranged from +0.2 to +0.4 V, whereupon an enhancement mode transistor can be configured. Furthermore, when a MOS transistor is formed so that the gate length L 2  becomes, for example, about 120 nm, which value is smaller than the gate length L 1 , the threshold value Vt of the MOS transistor can be adjusted so as to range from about −0.6 to −0.2 V, whereupon a depletion mode transistor can be configured. 
   The gate length L 2  can be set at 120 nm, for example, in order that each of the selective gate transistors DSGT 121  and DSGT 222  may be configured into a depletion mode transistor. Furthermore, in order that each of the selective gate transistors DSGT 221  and DSGT 122  may be formed into an enhancement mode transistor, the gate length L 1  of the transistor can be 220 nm, for example, so that the gate length L 1  is larger than gate lengths of the selective gate transistors DSGT 121  and DSGT 222 . Consequently, transistors having different threshold voltages Vt respectively can be configured. 
   In  FIG. 1 , the selective gates SG 4 , SG 5  and the like and the word lines WL 1  to WL 3  and the like are formed so as to be linearly symmetrical with respect to a direction in which the bit line contacts CB 1  to CBn are arranged. The description of this configuration will be eliminated since the configuration is similar to the configuration of the selective gates SG 1 , SG 2  and the like and word lines WL 1  to WL 3  and the like. 
   Returning to  FIG. 2 , row decoders and column decoders neither shown are connected to the word lines WL 1  to WLm and bit lines BL 1  to BLn respectively. Furthermore, a control circuit not shown supplies selective signals to gates of the drain selective gate transistors DSGT 111  and DSGT 112 , DSGT  211  and DSGT 212 , selective gate transistors DSGTT 1 n 1  and SSGTn 2 , DSGT 2 n 1  and DSGT 2 n 2 , source selective gate transistors SSGT 11  and SSGT 12  and selective gate transistors SSGTn 1  and SSGTn 2 , whereby the strings AL 11  and AL 12  to ALn 1  and ALn 2  are switchable between enable and disenable states. 
   The operation of the foregoing configuration will now be described. The following describes a case where the bit line BL 2  has been selected. Upon selection of the bit line BL 2 , the control circuit not shown supplies a H level voltage to the selective gate SG 1  and further supplies a L level voltage (0 V, for example) to the selective gate SG 2 . Furthermore, when the an H level voltage is applied to the source selective gate SG 3 , the selective gate transistors DSGT 121 , DSGT 122 , DSGT 222 , SSGT 21  and SSGT 22  are turned on, whereas the transistor DSGT 221  is turned off. In this case, the string AL 22  is enabled and the string AL 21  is disenabled. At this time, a predetermined voltage is applied to the word lines WL 1  to WLm so that one of the memory cells is selected by each of the transistors Tr 122  to TRm 22 , whereupon read/write and erasure of each memory cell constituting the array AL 22  can be performed. 
   On the other hand, the control circuit supplies a L level reference voltage (0 V, for example) to the gate of each of the selective gate transistors DSGT 121  and DSGT 122 , whereas the control circuit supplies an H level voltage to the gate of each of the selective gate transistors DSGT 221  and DSGT 222 . Furthermore, the control circuit supplies an H level voltage to the gate of each of the source selective gate transistors SSGT 21  and SSGT 22 . Then, the transistors DSGT 121 , DSGT 221 , DSGT 222 , SSGT 21  and SSGT 22  are turned on, whereas the transistor DSGT 122  is turned off. In this case, the string AL 21  is enabled and the string AL 22  is disenabled. At this time, when the predetermined voltage is applied to each of the word lines WL 1  to WLm as described above, one of the memory cells is selected by each of the transistors Tr 122  to TRm 22 , whereupon read/write and erasure of each memory cell constituting the array AL 21  can be performed. The same operation is achieved when one of the bit lines BL 1 , BL 3  to BLn is selected. Accordingly, the description will be eliminated. 
   According to the foregoing embodiment, two columns of NAND strings AL 21  and AL 22  are configured so as to correspond to the bit line contact CB 2 . The selective gate transistors DSGT 121  and DSGT 221  are series-connected between the bit line contact CB 2  of the bit line BL 2  and a memory cell transistor Tr 121  provided at one end of the string AL 21  in the row direction. The selective gate transistors DSGT 122  and DSGT 222  are series-connected between the memory cell transistor Tr 122  provided at one end of the string AL 22  and the bit line contact CB 2  of the bit line BL 2  in the row direction. The four selective gate transistors are formed so that the gate lengths of the transistors differ from one another both in the column direction and in the row direction. Accordingly, even when the design rule is rendered strict, a width of two columns of the strings AL 21  and AL 22  can be ensured as the region of the bit line contact CB 2 . As a result, the bit line contact CB 2  can readily be formed and the threshold voltage can be varied utilizing the short channel effect of each transistor. Consequently, adjusting dose of impurities and then carrying out an ion implantation is unnecessary when the selective gate transistors DSGT 121 , DSGT 221 , DSGT 122  and DSGT 222  are formed. 
     FIG. 4  illustrates a second embodiment of the invention. The second embodiment differs from the previous embodiment in the relationship in an arrangement of selective gate transistors in the bit lines BL 2  and BL 3 . In the second embodiment, identical or similar parts are labeled by the same reference symbols as those in the first embodiment and the description of these parts will be eliminated. Only the difference of the second embodiment from the first embodiment will be described. In the following description, the bit line BL 2  serves as a bit line in the present invention and the bit line BL 3  serves as a second bit line. 
   The bit line BL 3  is formed so as to be adjacent to the bit line BL 2  as shown in  FIG. 2 . Selective gate transistors DSGT 131 , DSGT 231 , DSGT 132  and DSGT 232  are provided so as to correspond to the bit line BL 3 . The selective gate transistors DSGT 131  and DSGT 231  are series-connected between the bit line contact CB 3  of the bit line BL 3  and a string AL 31 . Furthermore, the selective gate transistors DSGT 132  and DSGT 232  are series-connected between the bit line contact CB 3  of the bit line BL 3  and a string AL 32 . 
   The selective gate transistor DSGT 131  is formed so as to be adjacent to the selective gate transistor DSGT 122  in the row direction. Similarly, the transistor DSGT 231  is formed so as to be adjacent to the selective gate transistor DSGT 222  in the row direction.  FIG. 4  schematically illustrates a gate structure of the selective gate transistor and an array structure of the memory cell transistors in this case. As shown, the adjacent selective gate transistors DSGT 122  and DSGT 131  are formed into the enhancement mode transistors having the same gate length (length L 1 ). Furthermore, the adjacent selective gate transistors DSGT 222  and DSGT 231  are formed into the depletion mode transistors having the same gate length (length L 2 ). Since the adjacent selective gate transistors DSGT 122  and DSGT 131  have the same gate length, the selective gate transistors DSGT 122  and DSGT 131  can be formed using the active area corresponding to two columns. Consequently, the gates of the transistors can be formed easily in the process. Since the adjacent selective gate transistors DSGT 222  and DSGT 231  also have the same gate length, the gates of the transistors can be formed easily in the process. 
   According to the second embodiment, the gates of the adjacent selective gate transistors DSGT 122  and DSGT 131  and the adjacent selective gate transistors DSGT 222  and DSGT 231  are formed so as to have the same gate length in the same process, the gates can be formed more easily as compared with the first embodiment. 
   The invention should be limited to the foregoing embodiments. The embodiments may be modified or expanded as follows. Two columns of strings AL 21  and AL 22  are formed so as to correspond to the bit line BL 2  in the foregoing embodiments. However, for example, three or more columns of NAND strings may be formed so as to correspond to the bit line BL 2 . In the latter case, as shown in  FIG. 5 , it is desirable to form the selective gate transistors DSGT 121 , DSGT 221 , DSGT 321 , DSGT 122 , DSGT 222 , DSGT 322 , DSGT 123 , DSGT  223  and DSGT 323  so that one of the selective gate transistors has a different gate length from the other selective gate transistors in the row direction and so that one of the selective gate transistors has a different gate length from the other selective gate transistors in the column direction. Consequently, substantially the same effect can be achieved from the above modification as from the foregoing embodiments. Additionally, the forming region of the bit line contact CB 2  can be rendered wider. In other words, even when high integration and refinement of a memory cell further progress, the bit line contact CB 2  can easily be formed. 
   Furthermore, it is desirable that each of the selective gate transistors DSGT 321 , DSGT 222  and DSGT 123  which has the different gate length in the row and column directions is formed into the enhancement mode transistor and that each of the other selective gate transistors are formed into the depletion mode transistors. 
   The selective gate transistors are formed into the depletion and enhancement mode MOS transistors in the first and second embodiments. However, the selective gate transistors may be formed into either type if the transistors have different gate lengths. 
   The foregoing description and drawings are merely illustrative of the principles of the present invention and are not to be construed in a limiting sense. Various changes and modifications will become apparent to those of ordinary skill in the art. All such changes and modifications are seen to fall within the scope of the invention as defined by the appended claims.