Abstract:
A monitoring device on-chip. The monitoring device includes characteristic circuits, test circuits, and select circuits and is incorporated into an integrated circuit. The test circuit is cascaded by the characteristic circuit and a select circuit is incorporated to switch to output the test signal or the characteristic signal. There is another select circuit to switch the output signal of the integrated circuit in a normal mode or the signal of the output end of the characteristic circuit. Therefore, the output end of the select circuit can output the integrated circuit&#39;s signals, test signals, and characteristic signals without additional output pins.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The invention relates to a characteristic monitoring device on a chip. More particularly, the invention relates to the field of monitoring parameters of chips by measuring signal&#39;s delays. 
   2. Description of the Related Art 
   Conventional on-chip test circuits are used for testing parameters of chips, for example, utilizing a string of logic gates to test input levels Vil-Vih, output levels Vol-Voh, and connectivities of pads.  FIG. 8  shows a diagram of conventional strings of logic gates. A pulse signal sequence propagates through input pads I 1 -I 4  in order, changing one pin low at a time, and then going back high, in reverse order, changing one pin at a time. Delayed by the NAND gates  1 - 2 - 3 - 4 , the NANDout outputs the pulse signal sequence. The input levels Vil and Vih can be measured at the input pads I 1 -I 2 -I 3 -I 4 . The output level Vol and Voh can be measured at the output node NANDout. 
   The other characteristics of chips cannot be obtained by conventional strings of logic gates. There is a need for adding pads or changing test circuit structure for measuring the other characteristics. Under the condition without changing test circuit structure and adding too many pins overhead, a need therefore exists for a test circuit capable of measuring parameters of chips mentioned above and the other characteristics of chips. 
   SUMMARY OF THE INVENTION 
   It is therefore an object of the present invention to provide an on-chip device design that affords an ability to monitor parameters on a chip. 
   To achieve the above objects, the present invention provides an on-chip device incorporated into an integrated circuit. According to the embodiment of the invention, the monitoring device includes characteristic circuits, test circuits, and select circuits. 
   The characteristic circuits are of various kinds according to parameters to be characterized, such as inverter strings, long delay lines, and delay circuits. For example, threshold voltages of an inverter relate to delays of inverter strings, thus inverter strings can characterize inverter&#39;s threshold. 
   Besides measuring test signals, the embodiment of the invention is capable of measuring parameters of chips. The test circuit is cascaded by the characteristic circuit and a select circuit is incorporated in the characteristic circuit, thus the output end of the characteristic circuit can be switched by a select signal to output the test signal or the characteristic signal. There is another select circuit to switch the output signal of the integrated circuit in normal mode or the signal of the output end of the characteristic circuit. Therefore, the output end of the select circuit can output an integrated circuit&#39;s signals, test signals, and characteristic signals without additional output pins. 
   For high-speed requirements, the characteristic circuits are inserted into the test circuit, such as a tree structure of NAND gates. The characteristic circuits are arranged in branches of NAND gates. The select signals are used to enable or disable the characteristic circuits. Similarly, the output end of the tree structure can an output integrated circuit&#39;s signals, test signals, and characteristic signals without additional output pins. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The aforementioned objects, features and advantages of this invention will become apparent by referring to the following detailed description of the preferred embodiment with reference to the accompanying drawings, wherein: 
       FIG. 1  shows a structure diagram of the first embodiment of the present invention. 
       FIG. 2  shows a block diagram of the characteristic circuits  40  and  42 . 
       FIGS. 3A ,  3 B,  3 C shows schematic diagrams of monitoring circuits. 
       FIG. 4  shows a table for operation according the first embodiment of the present invention. 
       FIG. 5  shows the waveforms of the characteristic delays. 
       FIG. 6  shows a structure diagram of the second embodiment of the present invention. 
       FIG. 7  shows a structure diagram of the third embodiment of the present invention. 
       FIG. 8  shows a diagram of conventional strings of logic gates. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The First Embodiment 
     FIG. 1  shows a structure diagram of the first embodiment of the present invention. An integrated circuit  500  and plural input output lines are shown in  FIG. 1 . The input lines  101 - 103 - 105  and  106  can only provide input paths to the input terminals of the integrated circuit  500 . The output lines  120  and  122  can only provide output paths from the output terminals of the integrated circuit  500 . The pad  11  is coupled to the input line  101  and an input end of the NAND gate  201 . The pad  12  is coupled to the input line  103  and the other input end of the NAND gate  201 . The output end of the NAND gate  201  is coupled to an input end of the NAND gate  203 . The pad  13  is coupled to the input line  105  and the other input end of the NAND gate  203 . The output end of the NAND gate  203  is coupled to an input end of the NAND gate  205 . The pad  14  is coupled to the input line  106  and the other input end of the NAND gate  205 . The output end of the NAND gate  205  is coupled to an input end of the NAND gate  207 . The bidirectional pad B 1  is coupled to the other input end of the NAND gate  207  and the input line  108 . The output line  110  is coupled to the first input end of the select circuit  10 . The output end of the NAND gate  205  is coupled to the second input end of the select circuit  10 . The control end of the select circuit  10  receives a first select signal C 1 . The output end of the select circuit  10  is coupled to the input end of the buffer  22 . The output end of the buffer  22  is coupled to the bidirectional pad B 1 . The output line  112  is coupled between the output enable end of the integrated circuit  500  and the first input end of the select circuit  12 . The second input end of the select circuit  12  receives the third select signal C 3 . The control end of the select circuit  12  receives the first select signal C 1 . 
   The output end of the NAND gate  207  is coupled to an input end of the NAND gate  209 . The bidirectional pad B 2  is coupled to the other input end of the NAND gate  209  and the input line  114 . The output line  116  is coupled to the first input end of the select circuit  14 . The output end of the NAND gate  205  is coupled to the second input end of the select circuit  14 . The control end of the select circuit  14  receives the first select signal C 1 . The output end of the select circuit  14  is coupled to the input end of the buffer  24 . The output end of the buffer  24  is coupled to the bidirectional pad B 2 . The output line  118  is coupled between the output enable end of the integrated circuit  500  and the first input end of the select circuit  16 . The second input end of the select circuit  16  receives the third select signal C 3 . The control end of the select circuit  16  receives the first select signal C 1 . The output end of the select circuit  16  is coupled to the enable end of the buffer  24 . 
   The output line  120  is coupled between the output end of the integrated circuit  500  and the first input end of the select circuit  30 . The output end of the NAND gate  209  is coupled to the input end of the characteristic circuit  40 . The control end of the characteristic circuit  40  receives the second select signal C 2  for enabling. The output end of the characteristic circuit  40  is coupled to the second input end of the select circuit  30 . The output end of the select circuit  30  is coupled to the output pad  01 . 
   The output line  122  is coupled between the output end of the integrated circuit  500  and the first input end of the select circuit  32 . The output end of the NAND gate  209  is coupled to the input end of the characteristic circuit  42 . The control end of the characteristic circuit  42  receives the second select signal C 2  for controlling enabling of the characteristic circuit  42 . The output end of the characteristic circuit  42  is coupled to the second input end of the select circuit  32 . The output end of the select circuit  32  is coupled to the output pad O 2 . 
     FIG. 2  shows a block diagram of the characteristic circuits  40  and  42 . The characteristic circuit  40  includes monitoring circuit  53 , select circuit  51 . The input end of the characteristic circuit  40  is coupled to the input end of the monitoring circuit  53  and coupled to the first input end of the select circuit  51 . The output end of monitor circuit  53  is coupled the second input end of the select circuit  51 . The control end of the select circuit  51  is the control end of the characteristic circuit  40 . The output end of the select circuit  51  is the output end of the characteristic circuit  40 . The monitoring circuit  53  can be a delay cell, a string of inverters, or a long signal line, as shown in  FIG. 3A ,  FIG. 3B , and  FIG. 3C . 
   NAND gates  201 ,  203 ,  205 ,  207 , and  209  form a string of logic test circuit.  FIG. 4  shows a table for operation according the first embodiment of the present invention. When the first select signal C 1  is 0, i.e. low logic level, the characteristic monitoring device  400  operates in a normal mode. The select circuit  10  outputs the signal of the output line  110 . The select circuit  12  outputs the signal of the output line  112 . The select circuit  14  outputs the signal of the output line  116 . The select circuit  16  outputs the signal of the output line  118 . The select circuit  30  outputs the signal of the output line  120 . The select circuit  32  outputs the signal of the output line  122 . 
   When the first select signal C 1  is 1, i.e. high logic level, and the second select signal C 2  is 0, i.e. low logic level, the characteristic monitoring device  400  operates in a test mode. When the third select signal C 3  is 0, i.e. low logic level, the bidirectional pads B 1  and B 2  is set to be input pads. The select circuit  10  outputs the signal of the NAND gate  205 . The select circuit  12  outputs a low logic level, thus the buffer  22  is disabled and cannot output the signal of the select circuit  10 , i.e. cannot output the output signal of the NAND gate  205 . 
   The select circuit  14  outputs the signal of the NAND gate  205  and the select circuit  16  outputs a low level, thus the buffer  24  is disabled and cannot output the signal of the select circuit  14 , i.e. cannot output the output signal of the NAND gate  205 . The characteristic circuit  40  outputs the test signal of the NAND gate  209 . The select circuit  30  outputs the output signal of the characteristic circuit  40 , i.e., outputs the test signal of the NAND gate  209 . The characteristic circuit  42  outputs the test signal of the NAND gate  209 . The select circuit  32  outputs the output signal of the characteristic circuit  42 , i.e., outputs the test signal of the NAND gate  209 . 
   When the first select signal C 1  is 1, i.e. high logic level and the second select signal C 2  is 0, i.e. low logic level, the characteristic monitoring device  400  operates in a test mode. When the third select signal C 3  is 1, i.e. high logic level, the bidirectional pads B 1  and B 2  is set to be output pads. The select circuit  10  outputs the signal of the NAND gate  205 . The select circuit  12  outputs a high logic level, thus the buffer  22  is enabled and outputs the signal of the select circuit  10 , i.e. outputs the output signal of the NAND gate  205 . The select circuit  14  outputs the signal of the NAND gate  205  and the select circuit  16  outputs a high level, thus the buffer  24  is enabled and outputs the signal of the select circuit  14 , i.e. outputs the output signal of the NAND gate  205 . The characteristic circuit  40  outputs the test signal of the NAND gate  209 . The select circuit  30  outputs the output signal of the characteristic circuit  40 , i.e., outputs the test signal of the NAND gate  209 . The characteristic circuit  42  outputs the test signal of the NAND gate  209 . The select circuit  32  outputs the output signal of the characteristic circuit  42 , i.e., outputs the test signal of the NAND gate  209 . 
   When the first select signal C 1  is 1, i.e. high logic level and the second select signal C 2  is 1, i.e. high logic level, the characteristic monitoring device  400  operates in a characteristic mode. When the third select signal C 3  is 0, i.e. low logic level, the bidirectional pads B 1  and B 2  is set to be input pads. The select circuit  10  outputs the signal of the NAND gate  205 . The select circuit  12  outputs a low logic level, thus the buffer  22  is disabled and cannot output the signal of the select circuit  10 , i.e. cannot output the output signal of the NAND gate  205 . 
   The select circuit  14  outputs the signal of the NAND gate  205  and the select circuit  16  outputs a low level, thus the buffer  24  is disabled and cannot output the signal of the select circuit  14 , i.e. cannot output the output signal of the NAND gate  205 . The characteristic circuit  40  outputs the characteristic signal of the monitoring circuit  53 . The select circuit  30  outputs the output signal of the characteristic circuit  40 , i.e., outputs the characteristic signal of the monitoring circuit  53 . The characteristic circuit  42  outputs the characteristic signal of the monitoring circuit  53 . The select circuit  32  outputs the output signal of the characteristic circuit  42 , i.e., outputs the characteristic signal of the monitoring circuit  53 . 
     FIG. 5  shows the waveforms of the characteristic delays. When the first select signal C 1  is 1 and the second select signal C 2  is 0, the output pad O 1  outputs the test signal. When the first select signal C 1  is 1 and the second select signal C 2  is 1, the output pad O 1  outputs the characteristic signal. As shown in  FIG. 5 , there is a characteristic delay Δt between the characteristic signal and the test signal determined by the structure of the monitoring circuit  53 . By the relation between parameters of the monitoring circuit  53  and the characteristic delay Δt, the characteristics of the chip, the monitoring circuit is on, is obtained. 
   The Second Embodiment 
     FIG. 6  shows a structure diagram of the second embodiment of the present invention. The difference from the first embodiment is that the controlling structure for the characteristic signal only requires the first select signal to select the test mode or characteristic mode. 
   The output line  120  is coupled between the output end of the integrated circuit  500  and the first input end of the select circuit  30 . The output end of the NAND gate  209  is coupled to the input end of the monitoring circuit  53 . The output end of the monitoring circuit  53  is coupled to the second input end of the select circuit  30 . The output end of the select circuit  30  is coupled to the output pad O 1 . 
   The output line  122  is coupled between the output end of the integrated circuit  500  and the first input end of the select circuit  32 . The output end of the NAND gate  209  is coupled to the input end of the monitoring circuit  55 . The output end of the monitoring circuit  55  is coupled to the second input end of the select circuit  32 . The output end of the select circuit  32  is coupled to the output pad O 2 . 
   The output line  124  is coupled between the output end of the integrated circuit  500  and the first input end of the select circuit  34 . The output end of the NAND gate  209  is coupled to the second input end of the select circuit  34 . The output end of the select circuit  34  is coupled to the output pad O 3 . 
   When the first select signal C 1  is 0, i.e. low logic level, the characteristic monitoring device  402  operates in a normal mode. The select circuit  30  outputs the signal of the output line  120 . The select circuit  32  outputs the signal of the output line  122 . The select circuit  34  outputs the signal of the output line  124 . 
   When the first select signal C 1  is 1, i.e. high logic level, the characteristic monitoring device  402  operates in the test mode and the characteristic mode simultaneously. The select circuit  30  outputs the characteristic signal of the monitoring circuit  53 . The select circuit  32  outputs the characteristic signal of the monitoring circuit  55 . The select circuit  34  outputs the test signal of the NAND gate  209 . 
   The signal line L 1  is coupled between the output end of the NAND gate  209  and the monitoring circuit  53 . The signal line L 2  is coupled between the output end of the NAND gate  209  and the monitoring circuit  55 . The signal line Ls is coupled between the output end of the NAND gate  20  and the second input end of the select circuit  34 . The delays resulted from the signal lines L 1 , L 2 , and Ls must be the same. 
   The output pad O 1  outputs the test signal. The output pad O 2  outputs the characteristic signal. The output pad O 3  outputs the characteristic signal. As shown in  FIG. 5 , there is a characteristic delay Δt between the characteristic signal and the test signal, determined by the structure of the monitoring circuit  53 . By the relation between parameters of the monitoring circuit  53  and the characteristic delay Δt, the characteristics of the chip, the monitoring circuit is on, is obtained. 
   The Third Embodiment 
     FIG. 7  shows a structure diagram of the third embodiment of the present invention. As shown in  FIG. 7 , the NAND gates  207 ,  203 ,  205 , and  207 , the characteristic circuits  40 ,  42 , and  44 , and the select circuit  16  are included. 
   The input line  1   01  is coupled between the input pad  11  and the first input end of the NAND gate  201 . The input line  103  is coupled between the input pad  12  and the second input end of the NAND gate  201 . The output end of the NAND gate  201  is coupled to the input end of the characteristic circuit  40 . The control end of the characteristic  40  receives the second select signal C 1 . The output end of the characteristic circuit  40  is coupled to the first input end of the NAND gate  203 . The input line  105  is coupled between the input pad  13  and the second input end of the NAND gate  203 . The output end of the NAND gate  203  is coupled to the input end of the characteristic circuit  42 . The control end of the characteristic  42  receives the third select signal C 2 . The output end of the characteristic  42  is coupled to the first input end of the NAND gate  205 . The input line  107  is coupled between input pad  14  and the second input pad of the NAND gate  205 . The output end of the NAND gate  205  is coupled to the input end of the characteristic circuit  44 . The control end of the characteristic circuit  44  receives the fourth select signal C 3 . The output end of the characteristic circuit  44  is coupled to the first input end of the NAND  207 . The input line  109  is coupled between the input pad  15  and the second input end of the NAND gate  207 . The NAND gates  201 ,  203 ,  205 ,  207  and the characteristic circuit  40 ,  42 ,  44  form a tree structure. The first input end of the select circuit  16  is coupled to an input pad. The output end of the NAND gate  207  is couple to the second input end of the select circuit  16 . The control end of the select circuit  16  receives the first select signal CN. 
   When the first select signal CN is 0, i.e. low logic level, the characteristic monitoring device  404  operates in a normal mode. The select circuit  16  outputs the signal of the first input end. 
   When the first select signal CN is 1, the second, the third, and the fourth select signals C 1 , C 2 , and C 3  are 0, the characteristic monitoring device  404  operates in a test mode. The select circuit  16  outputs a test signal. 
   When the first select signal CN is 1, i.e. high logic level, the second select signal C 1  is 1, the third and the fourth select signals C 2  and C 3  are 0, the characteristic monitoring device  404  operates in a characteristic mode. The characteristic circuit  40  outputs the signal of monitoring circuit A. The select circuit  16  outputs a first characteristic signal. By the first characteristic signal and the test signal, the characteristic delay of the monitoring circuit A is obtained. 
   When the first select signal CN is 1, i.e. high logic level, the second select signal C 1  is 0, the third select signal C 2  is 1, and the fourth select signals C 3  is 0, the characteristic monitoring device  404  operates in a characteristic mode. The characteristic circuit  42  outputs the signal of monitoring circuit B. The select circuit  16  outputs a second characteristic signal. By the second characteristic signal and the test signal, the characteristic delay of the monitoring circuit B is obtained. 
   When the first select signal CN is 1, i.e. high logic level, the second select signal C 1  is 0, the third select signal C 2  is 0, and the fourth select signals C 3  is 1, the characteristic monitoring device  404  operates in a characteristic mode. The characteristic circuit  44  outputs the signal of monitoring circuit C. The select circuit  16  outputs a third characteristic signal. By the third characteristic signal and the test signal, the characteristic delay of the monitoring circuit B is obtained. 
   In the characteristic monitoring device  404 , the characteristic circuit  40 ,  42 , and  44  is arranged at the input ends of the tree structure, thus the loads of the normal mode are not affected. 
   It is suitable for high speed chips. 
   Although the present invention has been described in its preferred embodiment, it is not intended to limit the invention to the precise embodiment disclosed herein. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.