Abstract:
A circuit board structure and a method for fabricating the same are proposed. A plurality of conductive bumps and a first solder mask are formed on a carrier board, and the first solder mask is filled in the gaps between the conductive bumps and the conductive bumps are exposed. A first circuit layer and a first heat sink are formed on the first solder mask and the conductive bumps. A second heat sink is formed on the first heat sink, and a dielectric layer is formed on the first circuit layer and the first solder mask except the first and second heat sinks. A second circuit layer is formed on the dielectric layer and is electrically conductive to the first circuit layer. A third heat sink is formed on the second heat sink and a heat sink used for a chip mounting thereon is embedded in the dielectric layer. Therefore, the dimension of the circuit board is reduced and it is conformed to the dimension minimization progress of electronic devices.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     This invention relates to a circuit board structure and a method for fabricating the same, and more particularly, to a circuit board structure integrated with heat sinks and a method for fabricating the same.  
         [0003]     2. Description of Related Art  
         [0004]     With the rapid development of electronic industry, modern electronic products have various functions and better performance. In order to meet the requirements of small dimension but high integration for a semiconductor chip, a circuit board, which is used for carrying a plurality of active and passive components, is changed from having only one layer to having multiple layers.  
         [0005]     However, such a small-dimensiond but highly integrated semiconductor chip generates considerate amount of heat, which easily overheats or even makes unrecoverable damage on the semiconductor chip  
         [0006]     Adhering a plurality of heat dissipating spreaders onto the circuit board is one of the most popular ways to dissipate the heat generated by the semiconductor chip. Please refer to  FIG. 1 , which is a cross sectional view of a cavity-down ball grid array (CDBGA) package structure  10  according to the prior art. The package structure comprises a circuit board  11 , a cavity  113  formed on the circuit board  11 , a heat dissipating spreader  12  adhered to a first surface  11   a  of the circuit board  11 , a semiconductor chip  13  held in the cavity  113  and on the heat dissipating spreader  12 . The heat dissipating spreader  12  comprises a high heat conductivity material such as copper. The semiconductor chip  13  comprises an active surface  13   a  and an inactive surface  13   b . In a process to assembly the package structure  10 , the semiconductor chip  13  is disposed in the cavity  113  of the circuit board  11 , a non-electrically active surface  13   b  is adhered to the heat dissipating spreader  12 , a plurality of solder pads  17  are disposed on a second surface  11   b  of the circuit board  11 , a plurality of arc solder wires  14  are formed by a solder wire process to electrically connect the semiconductor chip  13  to a plurality of electrically conductive pads  114  disposed on the second surface  11   b  of the circuit board  11 , an encapsulant  15  is formed by an encapsulant process to covering the semiconductor chip  13  and the arc solder wires  14 , and a plurality of solder balls  16  are implanted by a ball implanting process on the second surface  11   b  of the circuit board  11 .  
         [0007]     Although the heat dissipating spreader  12  can effectively dissipate heat generated by the semiconductor chip  13 , the solder balls  16  have to be disposed higher than the arc solder wires  14  to ensure the solder balls can be soldered to the external electronic device such as a printed circuit board, this affecting a layout of the circuit board  11 . Moreover, the arc solder wires near the semiconductor chip  13  are crowded and easily short to each other. Further, in the encapsulant process, the circuit board  11 , on which the semiconductor chip  13  and the arc solder wires  14  are already disposed, is placed in a package mold, and then epoxy resin is injected into the mold to form the encapsulant  15  for covering the semiconductor chip  13  and the arc solder wires  14 . However, the semiconductor chip  13  generally does not fit the mold and will not be fixed in the mold tightly and closely, so the epoxy resin is easily injected to a region outside of the mold and part of the encapsulant  15  are formed on the second surface  11   b  of the circuit board  11 . In result, the package structure  10  is uneven and looks untidy and some of the solder pads  17  may get contaminated, affecting the electrical conductive quality of the package structure  10  because the contaminated solder pads  17  and the solder balls  16  thereon can not be conductive tightly. Moreover, the epoxy resin a kind of fluid, and affects the electrical conductive between the semiconductor chip  13  and the circuit board  11  when injected into the mold. If the epoxy resin is injected excessively in terms of quantity and speed into the mold, the arc solder wires  16  will be drawn too close or even contact to each other, resulting in a short problem and degrading the package structure  10 .  
         [0008]     Moreover, adhering the heat dissipating spreader  12  onto the circuit board  11  increases the thickness of the package structure  10 , which is contradictory to a development trend that a modern electronic device is required to have varieties of functions and compact dimension.  
         [0009]     Therefore, how to provide a circuit board structure having well heat dissipating capability, to solve the drawbacks of the prior art that the package structure  10  has too big the dimension because the heat dissipating spreader  12  is adhered to the circuit board  11 , has becoming one of the urgent errands in the art.  
       SUMMARY OF THE INVENTION  
       [0010]     In views of the above-mentioned problems of the prior art, it is a primary objective of the present invention to provide a circuit board structure and a method fabrication the same, for providing a chip disposed on the circuit board structure a well heat dissipating path and reducing the dimension of a circuit board.  
         [0011]     To achieve the above-mentioned and other objectives, a circuit board structure and a method for fabricating the same are provided according to the present invention. The method includes forming on a carrier board a plurality of conductive bumps and first solder masks filled in gaps between the conductive bumps for exposing the conductive bumps; forming on the first solder masks and the conductive bumps a conductive layer and on the conductive layer a first resistive layer having a plurality of openings for exposing part of the conductive layer; forming in the openings of the first resistive layer a first circuit layer and a first heat sink; forming on the first heat sink, the first resistive layer and the first circuit layer a second resistive layer having a plurality of openings for exposing the first heat sink; forming a second heat sink on the first heat sink exposed to a region outside of the openings of the second resistive layer; removing the second resistive layer, the first resistive layer and the conductive layer covered by the first resistive layer, and forming a dielectric layer on the first circuit layer and the first solder mask where neither the first heat sink nor the second heat sink is formed; and forming on the second heat sink a third heat sink, and forming on the dielectric layer a second circuit layer electrically conductive to the first circuit layer.  
         [0012]     The method further includes removing the carrier board. The method further includes forming on the second circuit layer a second solder mask having a plurality of openings for exposing an electrically conductive pads of the second circuit layer. The method further includes performing a circuit build-up process on the second circuit layer to form a circuit build-up structure.  
         [0013]     The circuit board structure fabricated by the method includes a dielectric layer having a first surface and a second surface; a plurality of heat sinks embedded in the dielectric layer and protruding to a region above the second surface of the dielectric layer; a first circuit layer embedded in the dielectric layer and disposed evenly with the first surface of the dielectric layer; and a second circuit layer formed on the second surface of the dielectric layer second surface and electrically conductive to the first circuit layer, wherein the first circuit layer is electrically conductive by a conductive via formed in the dielectric layer to the second circuit layer.  
         [0014]     The circuit board structure further includes a first solder mask formed on the first surface of the dielectric layer and having a plurality of openings for exposing part of the first circuit layer, a plurality of conductive bumps formed in the openings of the first solder mask, and a second solder mask formed on the second circuit layer and having a pluralities of openings for exposing the electrically conductive pads of the second circuit layer.  
         [0015]     Compared with the prior art, the circuit board structure and the method for fabricating the same integrate the heat sinks directly into the circuit board, which already has the first circuit layer, the dielectric layer and the second circuit layer. Therefore, the circuit board of the present invention is thin and can be applied to a modern electronic device required to be minimization.  
         [0016]     Moreover, embedded with heat sinks, the circuit board needs not to reserve a certain space for the installation of the heat sinks and has a larger circuit layout space, so as to overcome the drawback of the prior art that the circuit board does not have a big layer space because a certain space on the circuit board has to be reserved for a heat dissipating spreader ready to be adhered to the circuit board.  
         [0017]     Further, in the present invention the heat sinks are integrated into the circuit board to for a circuit board structure having well heat dissipating capability, such that heat dissipated by a semiconductor chip disposed on the heat sinks can be conducted over the heat sinks. A circuit build-up layer can be further formed on the circuit board structure of the present invention, so as to form a multi-layered circuit structure.  
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0018]     The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:  
         [0019]      FIG. 1  is a cross sectional view of a cavity-down ball grid array (CDBGA) package structure  10  according to the prior art;  
         [0020]      FIG. 2A-2J  are ten cross sectional views demonstrating a method for fabricating a circuit board structure of a first embodiment according to the present invention; and  
         [0021]      FIGS. 3A and 3B  are two cross sectional views demonstrating a method for fabricating a circuit board structure of a second embodiment according to the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0022]     The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparently understood by those in the art after reading the disclosure of this specification. The present invention can also be performed or applied by other different embodiments. The details of the specification may be on the basis of different points and applications, and numerous modifications and variations can be devised without departing from the spirit of the present invention.  
         [0023]      FIGS. 2A  to  2 J are ten cross sectional views demonstrating a method for fabricating a circuit board structure of a first embodiment according to the present invention.  
         [0024]     As shown in  FIG. 2A , the method comprises providing a carrier board  20 , and forming a plurality of conductive bumps  21  on the carrier board  20  by first forming on the carrier board  20  a resistive layer having a plurality of openings for exposure of the carrier board  20 , then forming the conductive bumps  21  on the carrier board  20  where the openings are formed, and finally removing the resistive layer. The conductive bumps  21  are used for connecting to an external electronic device. According to the first embodiment, at least one of the conductive bumps  21  comprises solder tin, the carrier board  20  is a metal board, and the conductive bumps  21  are electroplated on the carrier board  21 .  
         [0025]     The method further comprises forming a first solder mask  22  in gaps between the conductive bumps  21 .  
         [0026]     As shown in  FIG. 2B , the method further comprises forming on the first solder mask  22  and the conductive bumps  21  a conductive layer  23 , which is used as a current conductive path needed by an electroplated metal material subsequently formed on the circuit board structure. According to the first embodiment, the conductive layer  23  comprises metal, alloy, a couple of deposited metal or a conductive polymer material.  
         [0027]     As shown in  FIG. 2C , the method further comprises forming on the conductive layer  23  a first resistive layer  24  for covering part of the conductive layer  23  and exposing a plurality of openings  240  reserved for the formation of a plurality of circuit layers and heat sinks formed by an electroplating process. According to the first embodiment, the first resistive layer  24  is a photoresist layer, such as a liquid photoresist layer and a dry film layer, and formed on the conductive layer  23  by printing, spin-coating or adhering techniques and exposing and developing processes.  
         [0028]     As shown in  FIG. 2D , the method further comprises performing the electroplating process on the conductive layer  23 , which is conductive and serves as the current conductive path, to form a first circuit layer  25  and a first heat sink  251  in the openings  240 .  
         [0029]     As shown in  FIG. 2E , the method further comprises forming on the first heat sink  251 , the first resistive layer  24  and the first circuit layer  25  a second resistive layer  26  having a plurality of openings  260  for exposing the first heat sink  251  of the first circuit layer  25 . According to the first embodiment, the second resistive layer  26  is also a photoresist layer, such as the liquid photoresist layer and the dry film layer, and formed on the first resistive layer  24  and the first circuit layer  25  by the printing, spin-coating or adhering techniques and the exposing and developing processes. The method further comprises performing the electroplating process on the first heat sink  251  exposed from the openings  260  of the second resistive layer  26  to form a second heat sink  252 .  
         [0030]     As shown in  FIG. 2F , the method further comprises removing the second resistive layer  26 , the first resistive layer  24  and the conductive layer  23 , which is originally covered by the first resistive layer  24 .  
         [0031]     As shown in  FIG. 2G , the method further comprises forming a dielectric layer  28  on the first circuit layer  25  and the first solder mask  22  where neither the first heat sink  251  nor the second heat sink  252  is disposed, and forming a via  280  on the dielectric layer  28  by laser drilling, plasma etching or mechanically drilling techniques for exposing part of the first circuit layer  25 . According to the first embodiment, the dielectric layer  28  comprises FR-4 resin, FR-5 resin, epoxy resin, polyesters resin, cyanate ester, polyimide, bismaleimide Triazine (BT) or insulating materials, such as mixed epoxy resin and glass fiber.  
         [0032]     As shown in  FIG. 2H , the method further comprises forming on the dielectric layer  28 , the second heat sink  252  and the via  280  a conductive layer  29 , which is used as another current conductive path needed by an electroplated metal material subsequently form on the circuit board structure. According to the first embodiment, the conductive layer  29  comprises metal, alloy, a couple of deposited metal or a conductive polymer material.  
         [0033]     The method further comprises forming on the conductive layer  29  a pattered third resistive layer  30  for covering part of the conductive layer  29 . According to the first embodiment, the third resistive layer  30  is a photoresist layer, such as a liquid photoresist layer and a dry film layer, and formed on the conductive layer  29  by printing, spin-coating or adhering techniques and exposing and developing processes. Therefore, a plurality of openings  300  reserved for the formation of a plurality of circuit layers and heat sinks are formed on the third resistive layer  30 . At least one of the openings  300  is corresponding in position to the second heat sink  252 .  
         [0034]     As shown in  FIG. 21 , through the use of the conductive layer  29 , which is conductive and serves as the current conductive path, the method further comprises performing the electroplating process on the openings  300  of the third resistive layer  30  as previous description to form a third heat sink  253 , a conductive via  280   a  and a second circuit layer  31 , which is conductive via the conductive via  280   a  to the first circuit layer  25 . The method further comprises removing the third resistive layer  30  and the conductive layer  29  covered thereby.  
         [0035]     As shown in  FIG. 2J , the method further comprises forming on the second circuit layer  31  a second solder mask  32  having a plurality of openings  320  for exposing the third heat sink  253  and an electrically conductive pad  311  of the second circuit layer  31 . The method further comprises forming a metal protection layer such as a nickel/gold layer, and removing the carrier board  20 , so as to form the circuit board structure, which is embedded with heat sinks.  
         [0036]     The circuit board structure fabricated by the method demonstrated in the first embodiment comprises the dielectric layer  28  having a first surface  28   a  and a second surface  28   b , a plurality of stacked heat sinks embedded in the dielectric layer  28  and exposed to the second surface  28   b  of the dielectric layer  28 , the first circuit layer  25  embedded in the dielectric layer  28  and disposed evenly with the first surface  28   a  of the dielectric layer  28 , and the second circuit layer  31  formed on the second surface  28   b  of the dielectric layer  28  and electrically conductive to the first circuit layer  25 . The first circuit layer  25  is electrically conductive by the conductive via  280   a  formed in the dielectric layer  28  to the second circuit layer  31 . The stacked heat sinks include the first heat sink  251  and the second heat sink  252  embedded in the dielectric layer  28 , and third heat sink  253  exposed to the second surface  28   b  of the dielectric layer.  
         [0037]     The first surface  28   a  of the dielectric layer  28  is covered by the first solder mask  22 . The first solder mask  22  has the openings  22   a  for exposing part of the first circuit layer  25  and the first heat sink  251 . The conductive bumps  21  are formed in the openings  22   a  of the first solder mask  22  and is disposed evenly with the first solder mask  22 . At least one of the conductive bumps  21  comprises a metal material such as solder tin. Both the second surface  28   b  of the dielectric layer  28  and the second circuit layer  31  are covered by the second solder mask  32 , which has the openings  320  for exposing the third heat sink  253  and part of the second circuit layer  31  as the electrically conductive pad  311 . The metal protection layer such as the nickel/gold layer is covered on the third heat sink  253  and the second circuit layer  31  where the second solder mask  32  is not disposed.  
         [0038]     Please refer to  FIGS. 3A and 3B , which are another two cross sectional views demonstrating another method for fabricating a circuit board structure of a second embodiment according to the present invention. Compared with the method demonstrated in the first embodiment, the method demonstrated in the second embodiment further comprises performing a circuit build-up process on the second circuit layer  31 .  
         [0039]     As shown in  FIG. 3A , the method further comprises performing the circuit build-up process on the second circuit layer  31  and the third heat sink  253  of the circuit board structure fabricated by the method demonstrated in the first embodiment and already having the first circuit layer  25 , the second circuit layer  31 , the first heat sink  251 , the second heat sink  252 , the third heat sink  253 , the dielectric layer  28 , the first solder mask  22  and the conductive bumps  21  (referring to  FIG. 21 ), to form on the second circuit layer  31  a circuit build-up structure  34  electrically conductive to the second circuit layer  31 , and increasing the thickness of the heat sinks to form a fourth heat sink  254  on the third heat sink  253 .  
         [0040]     The circuit build-up structure  34  comprises a dielectric layer  340 , a circuit layer  342  stacked on the dielectric layer  340 , and a conductive via  342   a  passing through the dielectric layer  340  and electrically conductive to the circuit layer  342  and the second circuit layer  31 .  
         [0041]     As shown in  FIG. 3B , the method further comprises forming on the fourth heat sink  254  and the circuit layer on the external surface of the circuit build-up structure  34  a second solder mask  32 , which comprises the openings  320  for exposing the electrically conductive pad  344  and the fourth heat sink  254 , allowing a semiconductor chip (not shown) to be disposed on the fourth heat sink  254  and dissipating heat generated by the semiconductor chip in operation via the heat sinks  251  to  254  and the conductive bumps  21 . The method further comprises forming a metal protection layer (not shown) such as a nickel/gold layer on the electrically conductive pads  344  in the openings  320  of the second solder mask  32 . The method further comprises removing the carrier board  20 , so as to form a circuit board structure embedded with heat sinks.  
         [0042]     In summary, the circuit board structure and the method for fabricating the same provides a carrier board formed with a plurality of conductive bumps, a first solder mask formed on the carrier board for exposing the conductive bumps, a first circuit layer and a first heat sink formed on the first solder mask and the conductive bumps, a dielectric layer formed on first circuit layer and the first solder mask where neither the first heat sink nor the second heat sink is formed, a second circuit layer formed on the dielectric layer, a second circuit layer electrically conductive by the conductive vias to the first circuit layer, to integrate the heat sinks into the circuit board and decrease the thickness of the circuit board. Therefore, the package structure is compact and is suitable for a modern electronic device.  
         [0043]     Moreover, embedded with heat sinks, the circuit board needs not to reserve a certain space for the disposition of the heat sinks and has a larger circuit layout space, so as to overcome the drawback of the prior art that the circuit board does not have a big layer space because a certain space on the circuit board has to be reserved for a heat dissipating spreader ready to be adhered to the circuit board.  
         [0044]     Further, in the present invention the heat sinks are integrated into the circuit board to for a circuit board structure having well heat dissipating capability, such that heat dissipated by a semiconductor chip disposed on the heat sinks can be conducted over the heat sinks. A circuit build-up layer can be further formed on the circuit board structure of the present invention, so as to form a multi-layered circuit structure.  
         [0045]     The foregoing descriptions of the detailed embodiments are only illustrated to disclose the features and functions of the present invention and not restrictive of the scope of the present invention. It should be understood to those in the art that all modifications and variations according to the spirit and principle in the disclosure of the present invention should fall within the scope of the appended claims.