Abstract:
An SRAM cell and a method of forming an SRAM cell. The SRAM cell includes a first pass gate field effect transistor (FET) and a first pull-down FET sharing a first common source/drain (S/D) and a first pull-up FET having first and second S/Ds; a second pass gate FET and a second pull-down FET sharing a second common S/D and a second pull-up FET having first and second S/Ds; a first gate electrode common to the first pull-down FET and the first pull-up FET and physically and electrically contacting the first S/D of the first pull-up FET; a second gate electrode of the first pull-up FET; a third gate electrode common to the second pull-down FET and the second pull-up FET and physically and electrically contacting the first S/D of the second pull-up FET; and a fourth gate electrode of the first pull-up FET.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to the field of semiconductor devices; more specifically, it relates to SRAM cells having recessed storage node connections and methods of fabricating SRAM cells having recessed storage node connections. 
       BACKGROUND 
       [0002]    As the dimensions of field effect transistors (FETs) decrease, lithographic constraints are tending toward the gates of the FETs to be orientated in a single direction on a fixed pitch. When SRAM (static random access memory) cells are fabricated using these gate lithographic constraints it is becoming more difficult to fabricate storage node connections using the metal contact level. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove. 
       SUMMARY 
       [0003]    A first aspect of the present invention is a static random access memory (SRAM) cell comprising: a first pass gate field effect transistor (FET) and a first pull-down FET sharing a first common source/drain (S/D) and a first pull-up FET having first and second S/Ds; a second pass gate FET and a second pull-down FET sharing a second common S/D and a second pull-up FET having first and second S/Ds; a first gate electrode common to the first pull-down FET and the first pull-up FET and physically and electrically contacting the first S/D of the first pull-up FET; a second gate electrode of the first pull-up FET; a third gate electrode common to the second pull-down FET and the second pull-up FET and physically and electrically contacting the first S/D of the second pull-up FET; and a fourth gate electrode of the first pull-up FET. 
         [0004]    A second aspect of the present invention is a method of forming a static random access memory (SRAM) cell, comprising: forming a first pass gate field effect transistor (FET) and a first pull-down FET sharing a first common source/drain (S/D) and a first pull-up FET having first and second S/Ds; forming a second pass gate FET and a second pull-down FET sharing a second common S/D and a second pull-up FET having first and second S/Ds; forming a first gate electrode common to said first pull-down FET and said first pull-up FET and physically and electrically contacting said first S/D of said first pull-up FET; forming a second gate electrode of said first pull-up FET; a third gate electrode common to said second pull-down FET and said second pull-up FET and physically and electrically contacting said first S/D of said second pull-up FET; and forming a fourth gate electrode of said first pull-up FET. 
         [0005]    These and other aspects of the invention are described below. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein: 
           [0007]      FIG. 1  is schematic diagram of an exemplary SRAM cell; 
           [0008]      FIGS. 2 through 7  illustrate methods of fabricating a gate-to-gate strap according to embodiments of the present invention; 
           [0009]      FIGS. 8 and 9  illustrate detailed steps in the formation of NFETs and PFETs of SRAM cells according to embodiments of the present invention; and 
           [0010]      FIG. 10  illustrates an alternative strapping technique according to embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    The embodiments of the present invention provide SRAM cells having recessed storage node straps that are formed from gate electrode material (not contact level or metal wire level material) and formed during the gate electrode fabrication steps, thereby eliminating the need for complex contact shapes and processes currently used. 
         [0012]    A photolithographic process is defined as a process in which a photoresist layer is applied to a surface of a substrate, the photoresist layer exposed to actinic radiation through a patterned photomask and the exposed photoresist layer developed to form a patterned photoresist layer. When the photoresist layer comprises positive photoresist, the developer dissolves the regions of the photoresist exposed to the actinic radiation and does not dissolve the regions where the patterned photomask blocked (or greatly attenuated the intensity of the radiation) from impinging on the photoresist layer. When the photoresist layer comprises negative photoresist, the developer does not dissolve the regions of the photoresist exposed to the actinic radiation and does dissolve the regions where the patterned photomask blocked (or greatly attenuated the intensity of the radiation) from impinging on the photoresist layer. After processing (e.g., an etch or an ion implantation), the patterned photoresist is removed. The photoresist layer may optionally be baked at one or more of the following steps: prior to exposure to actinic radiation, between exposure to actinic radiation and development, after development. 
         [0013]      FIG. 1  is schematic diagram of an exemplary SRAM cell. In  FIG. 1 , an SRAM cell  100  comprises pass gate field effect transistors (FETs) T 0  and T 1  (which are illustrated as n-channel FETs (NFETs), NFETs N 1  and N 1  and p-channel FETs (PFETs) P 0  and P 1 . The sources of PFETs P 0  and P 1  are connected to VDD and the drains of PFETs P 0  and P 1  to nodes A and B respectively. The sources of NFETs N 0  and N 1  are connected to GND and the drains of NFETs N 0  and N 1  to nodes A and B respectively. The gates of PFET P 0  and NFET N 0  are connected to node B and the gates of PFET P 1  and NFET N 1  are connected to node A. The drain of NFET T 0  is connected to node A, the source of NFET T 0  is connected to a bitline true (BT) line and the gate of NFET T 0  is connected to a wordline WL. PFET P 0  and NFET N 0  form a first inverter and PFET P 1  and NFET N 1  form a second inverter. PFETS P 0  and P 1  are pull-up devices and NFETs N 0  and N 1  are pull-down devices in that they pull-up nodes A and B to VDD or pull-down nodes A and be to GND. The first and second inverters are cross-coupled. The drain of NFET T 1  is connected to node B, the source of NFET T 1  is connected to a bitline complement (BC) line and the gate of NFET T 1  is connected to wordline WL. Alternatively, pass gate FETs T 0  and T 1  may be PFETs. The connection between FET T 0  and node A and FET T 1  and node B is made by first recessed straps according to embodiments of the present invention. 
         [0014]      FIGS. 2 through 7  illustrate methods of fabricating a gate-to-gate strap according to embodiments of the present invention. In  FIGS. 2-7  (and  FIG. 10 ) labels T 0 , N 0 , P 0 , T 1 , N 1  and P 1  mark the channel regions of the six transistors of the SRAM cell  100  of  FIG. 1 . While only three cross-sections relative to FETS T 0 , N 0 , and P 0  are illustrated in  FIGS. 2-7  (and  FIG. 10 ), similar respective cross-sections may be drawn relative to FETs T 1 , N 1  an P 1 . 
         [0015]      FIG. 2  is a plan view and  FIGS. 2A ,  2 B and  2 C are cross-sectional views through lines  2 A- 2 A,  2 B- 2 B and a portion of line  2 C- 2 C respectively of  FIG. 2 . In  FIGS. 2 ,  2 A,  2 B and  2 C, P-type regions  105 A and  105 D and N-type regions  105 B and  105 C are formed in a semiconductor substrate  110  (e.g., a single crystal bulk silicon substrate as illustrated or a single crystal silicon layer of an silicon-on-insulator (SOI) substrate)  110 . P-type regions  105 A and  105 D and N-type regions  105 B and  105 C are respectively P-type and N-type doped regions of substrate  110 . Trench isolation  115  surrounds the P-type regions  105 A and  105 D and N-type regions  105 B and  105 C and a gate dielectric layer  120  is formed on P-type regions  105 A and  105 D and N-type regions  105 B and  105 C trench isolation  115 . In one example, trench isolation  115  comprises silicon dioxide (SiO 2 ). In one example, gate dielectric layer  120  comprises SiO 2 , silicon nitride (Si 3 N 4 ) or combinations of layers thereof. In one example gate dielectric layer  120  is a high-K (dielectric constant) material, examples of which include but are not limited to metal oxides such as Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3 , or metal silicates such as HfSi x O y  or HfSi x O y N z  or combinations of layers thereof. A high-K dielectric material has a relative permittivity above about 10. In one example, gate dielectric layer  120  is about 0.5 nm to about 20 nm thick. 
         [0016]      FIG. 3  is a plan view and  FIGS. 3A ,  3 B and  3 C are cross-sectional views through lines  3 A- 3 A,  3 B- 3 B and a portion of line  3 C- 3 C respectively of  FIG. 3 . In  FIGS. 3 ,  3 A,  3 B and  3 C, trenches  121 ,  122 ,  123  and  124  are formed in trench isolation using a photolithographic process as defined supra. As illustrated in  FIGS. 3 ,  3 A,  3 B and  3 C, a reactive ion etch (RIE) has removed regions of gate dielectric layer  120  and etched trenches  121 ,  122 ,  123  and  124  into trench isolation  115 . In one example, trenches  121 ,  122 ,  123  and  124  are etched using a RIE etch selective to substrate  110  (e.g., silicon) over trench isolation  115  (e.g., silicon oxide). Trenches  121 ,  122 ,  123  and  124  do not extend all the way through trench isolation  115 . 
         [0017]      FIG. 4  is a plan view and  FIGS. 4A ,  4 B and  4 C are cross-sectional views through lines  4 A- 4 A,  4 B- 4 B and a portion of line  4 C- 4 C respectively of  FIG. 4 . In  FIGS. 4 ,  4 A,  4 B and  4 C, gate electrodes  125 A,  125 B,  125 C and  125 D have been formed using a photolithographic process to define the horizontal (parallel to the top surface of substrate  110 ) extents of the gate electrodes  125 A,  125 B,  125 C and  125 D, followed by an etch (e.g., using an RIE process) to form gate electrodes  125 A,  125 B and  125 C and  125 D and straps  130 A,  130 B,  130 C and  130 D. Strap  130 C is a buried portion of gate electrode  125 C formed in trench  122  (see  FIGS. 3 and 3C ). Strap  130 B is a buried portion of gate electrode  125 B formed in a corresponding trench abutting N-type region  105 C. Strap  130 A is formed entirely within trench  121  (see  FIGS. 3 ,  3 A and  3 B). Note the RIE process used to etch gate electrodes  125 A,  125 B,  125 C and  125 D have recessed strap  130 A below the top surface  132  of trench isolation  115  and etched notches  133  and  134  into P-type region  105 A and N-type region  105 B respectively (e.g., when substrate  110  is silicon and the gate electrodes are polysilicon). Strap  130 D is similar to strap  130 A. 
         [0018]    Straps  130 A and  130 D were defined by the photomask used to etch trenches  121 ,  122 ,  123  and  124  (see  FIGS. 2 ,  2 A,  2 B and  2 C). Straps  130 A and  130 B are not defined by the photomask used to define gate electrodes  125 A,  125 B,  125 C and  125 D. Straps  130 A and  130 B are formed from the gate electrode layer that was not protected by the photoresist during the gate electrode RIE process and are a residual layer of that gate electrode layer that was not removed from trenches  121  and  123  (see  FIGS. 3 ,  3 A and  3 B) during the RIE process. The gate electrode RIE stopped on gate dielectric layer  120 . 
         [0019]    The major axis A 1  of gate electrode  125 A, the major axis A 2  of gate electrode  125 B, the major axis A 3  of gate electrode  125 C, and the major axis A 4  of gate electrode  125 D are all aligned in the same direction (i.e., are mutually parallel). 
         [0020]    While the illustrated embodiment shows both straps  130 A and  130 D and straps  130 C and  130 D, alternative embodiments include forming straps  130 A and  130 D but not  130 B and  130 C and forming straps  130 B and  130 C but not straps  130 A and  130 D. 
         [0021]      FIG. 5  is a plan view and  FIGS. 5A ,  5 B and  5 C are cross-sectional views through lines  5 A- 5 A,  5 B- 5 B and a portion of line  5 C- 5 C respectively of  FIG. 5 . In  FIGS. 5 ,  5 A,  5 B and  5 C, dielectric sidewall spacers  135 A are formed on the sidewalls of gate electrodes  125 A,  125 B,  125 C and  125 D. Sidewall spacers  135 B are also formed on exposed sidewalls of P-type region  105 A (and  105 D) and N-type region  105 D (and  105 C) the sidewalls of trench  140 . Sidewall spacers  135 C may also be formed on internal sidewalls of gate electrode  125 C (and  125 B) over strap  130 C (and  130 B). Formation or non-formation of sidewall spacers  135 C depends upon the exact geometry and dimensions of the actual structure. In one example, sidewall spacers  135 A,  135 B and  135 C comprise Si 3 N 4 . Sidewall spacers  135 A,  135 B and  135 C may be formed simultaneously by a blanket deposition of a conformal dielectric layer (e.g. Si 3 N 4 ) followed by an RIE to remove the dielectric material from horizontal surfaces (surfaces parallel to the top surface of substrate  110 ). 
         [0022]    Prior to sidewall spacer formation, optional source/drain (S/D) extensions may be formed by ion implantation as illustrated in  FIGS. 8A and 8B  and described infra. After sidewall spacer formation, S/Ds may be formed by ion implantation as illustrated in  FIGS. 9A and 9B  and described infra. In  FIGS. 5 ,  5 A,  5 B and  5 C, the label N+ indicates the S/D of an NFET and the label P+ indicates the S/D of a PFET. S/D extensions are not illustrated in  FIGS. 5 ,  5 A,  5 B and  5 C. 
         [0023]      FIG. 6  is a plan view and  FIGS. 6A ,  6 B and  6 C are cross-sectional views through lines  6 A- 6 A,  6 B- 6 B and a portion of line  6 C- 6 C respectively of  FIG. 6 . In  FIGS. 6 ,  6 A,  6 B and  6 C, sidewall spacers  135 B and  135 C (see  FIGS. 5 ,  5 A,  5 B and  5 C) are removed using a photolithographic/etch process. Sidewall spacers  135 A are not removed. For an alternative where sidewall spacers  135 B and  135 C are not removed, see  FIGS. 10 ,  10 A,  10 B and  10 C. Also any exposed gate dielectric  120  not protected by sidewall spacers  135 A or gate electrodes  125 A,  125 B,  125 C and  125 D is removed and optional metal silicide layers  140  formed on exposed surfaces S/Ds formed in P-type regions  105 A and  105 D, N-type regions  105 B and  105 C and straps  130 A and  130 D. Metal silicide layers  140  may be formed by blanket depositing a thin metal layer, followed by high temperature heating in an inert or reducing atmosphere at a temperature that will cause the metal to react with silicon, and followed by an etch to remove un-reacted metal. 
         [0024]      FIG. 7  is a plan view and  FIGS. 7A ,  7 B and  7 C are cross-sectional views through lines  7 A- 7 A,  7 B- 7 B and a portion of line  7 C- 7 C respectively of  FIG. 7 . In  FIGS. 7 ,  7 A,  7 B and  7 C, electrically conductive contacts  145 A,  145 B,  145 C,  145 D,  145 E and  145 F are formed in a dielectric layer  150  that is formed on exposed surfaces of trench isolation  115 , sidewall spacers  135 A and metal silicide layer  140 . Contact  145 A is typical of contacts  145 A,  145 B,  145 C,  145 D,  145 E and  145 F. In  FIG. 7D , contact  145 A extends from the top surface of dielectric layer  150  to a top surface of metal silicide layer  140 . The top surface of contact  145 A is coplanar with the top surface of dielectric layer  150 . Contact  145 A is shared with an adjacent SRAM cell not illustrated in  FIG. 7 , but a portion of which is shown in  FIG. 7D , so contact  145  also contacts a S/D  155  of an FET T 0  of the adjacent SRAM cell. In one example, contacts  145 A,  145 B,  145 C,  145 D,  145 E and  145 F comprise tungsten. In one example, dielectric layer  150  comprises SiO 2 . 
         [0025]    Comparing  FIG. 7  to  FIG. 1 , contact  145 A connects to the bitline true (BT), contact  145 F connects to the bitline complement (BC), contacts  145 C and  145 D connect to GND and contacts  145 B and  145 E connect to VDD. Transistors T 0  and N 0  share a common S/D and FETS N 1  and T 1  share a common S/D. Storage node A comprises the common S/D of FETS T 0  and N 0  which are connected to a S/D of FET P 0  by strap  130 A. Storage node A is connected to the gates of FETs P 1  and N 1  by strap  130 C and gate electrode  130 D. Storage node B comprises the common S/D of FETS T 1  and N 1  which are connected to a S/D of FET P 1  by strap  130 D. Storage node B is connected to the gates of FETs P 0  and N 0  by strap  130 B and gate electrode  125 C. Thus nodes A and B do not include any connection made at the contact level. 
         [0026]      FIGS. 8 and 9  illustrate detailed steps in the formation of NFETs and PFETs of SRAM cells according to embodiments of the present invention. In  FIG. 8A , prior to sidewall spacer formation, an angled extension ion implantation of species X 1  (an N dopant) for NFET N 0  where P-type region  105 A is not protected by gate electrodes  125 B to form S/D extension regions  160 . In  FIG. 8B , prior to sidewall spacer formation, an angled extension ion implantation of species X 2  (a P dopant) for PFET P 0  where N-type region  105 B is not protected by gate electrodes  125 B to form S/D extension regions  165 . In  FIG. 9A , after sidewall spacer formation, a S/Dion implantation of species X 3  (an N dopant) for NFET N 0  where P-type region  105 A is not protected by gate electrodes  125 B and spacers  135 A to form S/D regions  170 . In  FIG. 9B , after sidewall spacer formation, a S/Dion implantation of species X 4  (a P dopant) for PFET P 0  where N-type region  105 B is not protected by gate electrodes  125 B and spacers  135 A to form S/D regions  175 . 
         [0027]      FIG. 10  illustrates an alternative strapping technique according to embodiments of the present invention.  FIG. 10  is a plan view and  FIGS. 10A ,  10 B and  10 C are cross-sectional views through lines  10 A- 10 A,  10 B- 10 B and a portion of line  10 C- 10 C respectively of  FIG. 10 .  FIGS. 10 ,  10 A,  10 B and  120 C are similar to respective  FIGS. 6 ,  6   a ,  6 B and  6 C with the exception that metal silicide layer  140  is not formed on regions of P-type region  105 A and N-type region  105 B that are protected by sidewall spacers  135 A or  135 B. 
         [0028]    Thus the embodiments of the present invention provide SRAM cells having recessed storage node straps and method of fabricating SRAM cells having recessed storage node straps that are formed from gate electrode material (not metal contact or metal wire material) and defined during the gate electrode fabrication steps. 
         [0029]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.