Abstract:
A protective circuit for a push-pull power amplifier comprises a load current-detecting resistor connected between the emitters of two transistors jointly constituting the power amplifier, a switch connected between an intermediate point on the load current-detecting resistor and the ground to shut off load current, a load resistance-detecting circuit for detecting the resistance of the load, and a driving circuit for causing the switch to be opened by an output from the load resistance-detecting circuit when the resistance of the load falls below a prescribed level. The load resistance-detecting circuit includes means for drawing out a first signal from one end of the load current-detecting resistor and, means for drawing out a second signal with lower potential than the first signal from the other end of the detecting resistor. Further, control means is provided for controlling the potential of the first signal according to that of the second signal, thereby increasing the potential difference between the first and second signals above a prescribed value when the resistance of the load falls below a predetermined value. The driving circuit which is supplied with the first and second signals opens the switch when the potential difference between both signals rises above a prescribed level.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a protective circuit for protecting a push-pull type power amplifier, and more particularly to a protective circuit for a power amplifier which can decrease voltage impressed on a semiconductor element constituting the protective circuit. 
     An audio power amplifier used to date has the arrangement shown in FIG. 1. According to the prior art audio power amplifier, a load current-detecting resistor R E  (R E  =r E  +r E ) is connected between the emitter of a transistor of first conductivity type whose collector is connected to a positive power source +V CC  and the emitter of a transistor of second conductivity type whose collector is connected to a negative power source -V EE . A switch S is connected between an intermediate point on the resistor R E  and a load L (speaker SP), one end of which in grounded. A collector-emitter circuit of a transistor Q 3  for detecting the resistance of the load L, for example, the short-circuiting thereof is connected through a resistor between the intermediate point on the resistor R E  and the positive power source +V CC . The base of the transistor Q 3  is connected to a junction of resistors Ra, Rb collectively constituting an attenuator. A coil 17 for operating the switch S is connected to the positive power source +V CC  through a driving transistor Q 4 . The base of this driving transistor Q 4  is supplied with an output from the collector of the transistor Q 3 . Where the load L is shortcircuited, the transistor Q 4  is put into operation to open the switch S, thereby protecting the power amplifier. This protective operation is undertaken when the following formula is satisfied: 
     
         r.sub.E I.sub.0 -αv.sub.0 ≧V.sub.TH 
    
     where: 
     r E  =resistance of the resistor r E  of FIG. 1 
     I 0  =load current 
     α=coefficient defined mainly by the resistances Ra, Rb of the attenuator of FIG. 1 
     v 0  =interterminal voltage of the load L 
     V TH  =threshold voltage of the transistor Q 3 , namely, a detecting level of the load resistance. 
     As apparent from the above formula, the switch S is immediately opened when the load is short-circuited, and the load resistance is substantially reduced to zero to allow the passage of large load current. 
     Where the protective circuit is integrated, it is necessary to use a semiconductor element of low withstand voltage and reduce the power consumption of the protective circuit. In this connection, the transistor Q 3  of the prior art protective circuit of FIG. 1 is discussed below. The voltage applied between the collector and emitter of the transistor Q 3  varies between the voltage +V CC  of the positive power source and the voltage -V EE  of the negative power source, therefore the withstand voltage BV CEO  between the collector and emitter regions is required to have as large a value as V CC  +V EE , where, therefore, the protective circuit is integrated, the withstand voltage of the transistor Q 3  has to be raised to the above-mentioned high level. This means that a large chip has to be used, increasing the cost of an integrated protective circuit. Further drawbacks of the prior art protective circuit are that if high voltage has to be impressed on a semiconductor element, power consumption will rise, making it necessary to use a package of low thermal resistance; special means should be provided to promote heat dissipation; and the internal resistance of the semiconductor element itself should be decreased to admit of application of small operating current. Therefore, the arrangement of the prior art protective circuit shown in FIG. 1 can not be regarded as adapted for integration. 
     It is accordingly the object of this invention to provide a protective circuit for a power amplifier which can be formed of a semiconductor element having a relatively low withstand voltage. 
     SUMMARY OF THE INVENTION 
     According to this invention, there is provided a protective circuit which comprises a load currentdetecting resistor connected between two transistors jointly constituting a push pull power amplifier for detecting the load current of the power amplifier; a load connected to the power amplifier through the load current-detecting resistor; a switch for shutting off the load current; a load resistance-detecting circuit for detecting the resistance of the load; and a driving circuit for causing the switch to be opened by an output from the load resistance-detecting circuit when the load resistance falls to a lower level than prescribed; wherein the load resistance-detecting circuit comprises a circuit means for drawing out a first signal from one end of the load current-detecting resistor, circuit means for drawing out a second signal of lower potential than the first signal from the other end of the load current-detecting resistor, and control circuit means, which, when the load has a higher resistance than prescribed holds the potential difference between the first and second signals to be lower than a predetermined level by causing the potential of the first signal to drop by the second signal of lower potential than the first signal, and, when the load has a lower resistance than prescribed, increases the potential difference between the first and second signals over the predetermined level; and the driving circuit is supplied with the first and second signals, and includes circuit means for opening the switch, when the potential difference between the first and second signals has a larger value than the predetermined value. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows the arrangement of the prior art protective circuit for a power amplifier; 
     FIG. 2 indicates the arrangement of a protective circuit according to one embodiment of this invention which protects a power amplifier by detecting a load resistance during the positive halfwave period of load current; 
     FIG. 3 sets forth the arrangement of a protective circuit according to another embodiment of the invention which protects a power amplifier by detecting a load resistance during the positive and negative halfwave periods of load current; 
     FIG. 4 is a diagram of the driving circuit of FIG. 3; 
     FIG. 5 presents the arrangement of another type of protective circuit for a power amplifier, only the detecting circuit of which is different from that of FIG. 3. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 2, a detecting resistor R E  (R E  =2r E ) for detecting load current I 0  is connected between the emitter of an NPN transistor Q 1  and that of a PNP transistor Q 2 . The base of each of said transistors Q 1 , Q 2  receives an input signal. Positive voltage is impressed from a positive power source +V CC  on the collector of the NPN transistor Q 1 . Negative voltage is supplied from a negative power source -V EE  to the collector of the PNP transistor Q 2 . A switch S for cutting off a load current is connected between an intermediate point on the resistor R E  and a load L (speaker), one end of which is grounded. The switch S is actuated by a coil 17 through which current passes. Reference numeral 11 denotes a detecting circuit for detecting load resistance, and reference numeral 12 represents a driving circuit for driving the switch S. A potential at the junction 10a between the emitter of the NPN transistor Q 1  and resistor R E  is indicated by Vu; a potential at the junction 10b between the emitter of the PNP transistor Q 2  and resistor R E  by V L  ; a potential at an intermediate point of the resistor R E , numely, a nongrounded point 10c of the load L by v 0  ; and load current by I 0 . The junction 10a and a point 15 are connected together through a resistor R 1 . A first signal V 1  is drawn out from the terminal 15. The junction 10b and point 16 are connected together through a resistor R 2 . A second signal V 2  is drawn out from the point 16. The point 15 is connected to the base of a transistor Q 11 , whose collector is connected through a resistor R 6  to a positive power source +B having a lower voltage than +V CC , and whose emitter is connected to the point 16. A diode D 2  of the indicated polarity is connected between the points 15, 16. 
     The point 15 is grounded through diodes D 3  and D 4  with the indicated polarity and the point 16 is grounded through diodes D 5  and D 6  with the indicated polarity. The point 16 is connected to the base of a transistor Q 12  whose collector is connected to the positive power source +B, and whose emitter is grounded through a resistor R 3  and diode D 1  of the indicated polarity. The base of a transistor Q 13  is connected to a junction between the resistor R 3  and diode D 1  ; the collector thereof is connected to the point 15 and to the point 16 through the diode D 2  of the indicated polarity; and the emitter thereof is grounded. The base-emitter circuit of the transistor Q 13  is connected in parallel to the diode D 1  to form a current mirror. The collector of the transistor Q 11  is connected to the base of a transistor Q 14 , whose emitter is connected to the positive power source +B and whose collector is grounded through a resistor R 7 , and is also connected to the base of a transistor Q 15  : The collector of this transistor Q 15  is connected to the positive power source +B through a resistor R 8  and also to the base of a transistor Q 16  through a resistor R 9 . The emitter of the transistor Q 15  is grounded. The collector of the transistor Q 16  is connected to the positive power source +B through the coil 17 for driving the switch S and the emitter thereof is grounded. A capacitor C 1  is connected between the base of the transistor Q 16  and the ground. 
     There will not be described the operation of the embodiment of FIG. 2 For better understanding, brief description is given of the case where the load L has a prescribed resistance and the case where the load L is short-circuited. Description is first given of the case where the load has a normal resistance, and the nongrounded terminal has a positive polarity. In this case, there result Vu&gt;v 0  and V L  =v 0 . Accordingly, the transistors Q 12 , Q 13  are in active regions. Referring to the transistor Q 13 , current I 2  flows through the resistor R 1  in the indicated direction. Therefore, the potential V 1  at the point 15 decreases from the potential Vu by a voltage drop at the resistor R 1 . Accordingly, a potential difference V 1  -V 2  between the potential V 1  at the point 15 and the potential V 2  at the point 16 can be made to fall short of a threshold voltage V BE  between the base and emitter of the transistor Q 11 . This arrangement enables the transistor Q 11  to be nonconducting, and in consequence the transistors Q 14 , Q 15  to be nonconducting and the transistor Q 16  to be conducting. The switch S is closed when current is conducted through the coil 17, and is opened when no current passes through the coil 17. Therefore, the switch remains closed when the load has a higher resistance than prescribed. 
     Where the load L is short-circuited, a voltage drop appears at the junction 10a due to short circuit current running through the detecting resistor R E . As the result, the voltages V 0 , V L  are reduced to zero, the transistors Q 12 , Q 13  are rendered nonconductive and current I 2  ceases to run. Therefore, the potential V 1  at the point 15 is increased to the potential Vu at the junction 10a. Since the potential difference V 1  -V 2  increases over the threshold voltage V BE  of the transistor Q 11 , the transistor Q 11  is rendered conducting when the transistors Q 1 , Q 2  are supplied with a signal. In this case, the transistors Q 14 , Q 15  are rendered conducting and the transistor Q 16  is rendered nonconducting, and the switch is opened. 
     There will now be described the general case where the load L has an optional resistance. The potential Vu at the junction 10a is expressed by the following equation: 
     
         Vu=r.sub.E I.sub.0 +V.sub.0                                (1) 
    
     Assuming v 0  ≧2V BE  (V BE  denotes a voltage between the base and emitter or threshold voltage of the transistor Q 11 ) and with the ratio between current I 1  flowing through the diode D 1  and current I 2  flowing through the transistor Q 13  set at N, namely, I 1  =NI 2 , then the base potential V 1  of the transistor Q 11  is expressed by the following equation: ##EQU1## Since V 2  =v 0 , a potential difference V 1  -V 2  between the base and emitter of the transistor Q 11  is expressed by the following equation: ##EQU2## When the potential difference V 1  -V 2  increases over V BE , the transistor Q 11  is rendered conducting and the switch S is opened. The above equation (3) may be rewritten as follows ##EQU3## 
     As seen from the above equation (4), where an output voltage v 0  has a high level, large current can be conducted through the output transistors of a power amplifier where said putput voltage v 0  has a low level, the protective ciucuit is operated, even when small current flows through the output transistors of the power amplifier. 
     In the region expressed by the following equation (5) where the output voltage v 0  has a high level ##EQU4## the following equation results: ##EQU5## Derived from the above equation (6) is the following equation: ##EQU6## 
     It is seen from the above equation (7) that the resistance R L  of the load L is equal to or smaller than (NR 3  /R 1  )r E , the protective circuit is put into operation. 
     Referring to FIG. 2, the diode D 2  prevents the transmission of excess back bias between the base and emitter of the transistor Q 11 . A group of diodes D 3  and D 4  suppresses the supply of excess back bias to the base of the transistor Q 11 , and a group of diodes D 5  and D 6  suppresses the supply excess back bias to the emitter of the same transistor Q 11 . 
     The transistor Q 12  acts as a sort of a buffer element substantially to eliminate the effect of voltage drop at the resistor R 2  connected between the junction 10b and point 16, and may therefore be omitted. Further, it is possible to use a differential amplifier in place of the transistor Q 11 . This arrangement enables the potential difference V 1  -V 2  to be detected more minutely. Namely, the transistor Q 11  detects the potential difference V 1  -V 2  substantially to the extent of 600 mV, where as the differential amplifier detects the potential difference V 1  -V 2  to the extent of about 100 mV. 
     The embodiment of FIG. 2 is designed to detect load resistance during the positive halfwave period of output current. Where the polarity of the diodes and transistor is reversed, then the embodiment can be so modified as to detect load resistance during the negative halfwave period of output current. Further, where it is desired to detect load resistance only during the positive halfwave period of output current, then the resistor R 2  may obviously be connected to the point 10c in place of the junction 10b. 
     It is seen from the foregoing embodiment that this invention enables a withstand voltage demanded for the transistor Q 11  to be lower than a sum of absolute values of power source voltage levels +V CC  and -V EE , and in consequence withstand voltage demanded for other transistors included in a protective circuit to be lower than V CC  and V EE . Therefore, this invention decrease the power consumption of a protective circuit. For the foregoing reason, a protective circuit embodying this PG,13 invention can be easily integrated. Where the resistors R 1 , R 2  are provided as external elements of an integrated protective circuit, then the level for detecting a load resistance can be easily set. 
     There will now be described by reference to FIG. 3 a protective circuit according to another embodiment which can detect load resistance during the positive and negative halfwave periods of an output voltage v 0 . This embodiment is characterized in that the first and second signals are drawn out through the first and second attenuators from the corresponding terminals of a detecting resistor, thereby decreasing a withstand voltage demanded for the transistors constituting a protective circuit. 
     Referring to FIG. 3, one end 10a of a load currentdetecting resistor R E  is connected to a first attenuator ATT 1  consisting of resistors R 11 , R 15 . A first signal V 1  is conducted through a junction 20 between both resistors R 11 , R 15  and also through a resistor R 12  to be drawn out at a terminal 15. The other end 10b of the load current-detecting resistor R E  is connected to a second attenuator consisting of resistors R 13 , R 16 . A second signal V 2  passes through a junction 22 between both resistors R 13 , R 16  and also through a resistor R 14  to be drawn out at a terminal 16. A load L, one end of which is grounded is connected to an intermediate point 10c on the resistor R E  through a switch S. A voltage v 0  is impressed between both terminals of the load L. Connected between the free ends of the resistors R 15 , R 16  are a group of diodes D 11  -D 12  and another group of diodes D 13  -D 14  with opposite polarities as shown in FIG. 3. The base of a PNP transistor Q 18  is connected to the free end of the resistor R 15 , and the base-emitter circuit thereof is connected in parallel to the diode D 13 , thereby constituting a current mirror circuit. The collector of the PNP transistors Q 18  is connected to the output terminal 16 of the second signal V 2 . The base of an NPN transistor Q 19  is connected to the free end of the resistor R 16 , and the base-emitter circuit thereof is connected in parallel to the diode D 14 , thereby forming a current mirror circit. The collector of the NPN transistor Q 19  is connected to the output terminal 15 of the first signal V 1 . The emitters of the transistors Q 18 , Q 19  are jointly connected to the junction of the series-connected group of diodes D 11  -D 12  and also to the junction of the series-connected group of diodes D 13  -D 14 , and further grounded. The diode D 11  is rendered conducting during the positive halfwave period of load current. The diode D 12  is operated during the negative halfwave period of load current. The diode D 11  actuates the attenuator ATT 1  during the positive halfwave period of load current the diode D 14  puts the attenuator ATT 2  into operation during the negative halfwave period of load current. The output terminal 18 of the driving circuit 12a is connected to one end of the driving coil 17 of the switch S. The other end of the coil 17 is grounded. The driving circuit indicated by referential numeral 12 in FIG. 2 and that shown in FIG. 4 may be used as a driving circuit 12a shown in FIG. 3. 
     Referring to FIG. 4, the base of an NPN transistor Q 21  is connected to the output terminal 15 of the first signal V 1 , the collector thereof to the positive power source +B, and the emitter thereof to the negative power source -B through a resistor R 18 , NPN transistor Q 25  and resistor R 19  in turn. NPN transistors Q 23 , Q 24  jointly constitute a differential amplifier. The collector of the transistor Q 23  is directly connected to the positive power source +B. The collector of the transistor Q 24  is connected to the positive power source +B through the corresponding collector resistor. The emitter of both transistors Q 23 , Q 24  are jointly connected to the nagative power source -B through an NPN transistor Q 27 . The base of the transistor Q 22  is connected to the output terminal 16 of the second signal; the collector thereof directly to the positive power source +B; and the emitter thereof is connected to the base of the transistor Q 24 , and also to the negative power source -B through an NPN transistor Q 26 . The base of a PNP transistor Q 28  is connected to the collector of the transistor Q 23 , and the emitter thereof is connected to the nongrounded end of the driving coil 17 of the switch S through the output terminal 18. A constant current source 20, one end of which is grounded, is connected to the negative power source -B through the indicated diode. An output from the constant current source 20 is supplied in common to the bases of transistors Q 25 , Q 27 , Q 26  arranged in the order mentioned. 
     Reverting to FIG. 3, a potential V 1a  at the output terminal 20 of the first attenuator ATT 1  and a maximum potantial V 2a  at the output terminal 22 of the second attenuator ATT 2  are expressed by the following equations respectively with a voltage drop at the diodes D 11  to D 14  disregarded. ##EQU7## Therefore, source voltages +B, -B required for the driving circuit 12a are expressed as follows: ##EQU8## Assuming +V CC  =50 V, -V EE  =-50 V, and ##EQU9## the equation of +B≧10 V and -B≧-10 V are satisfied. The transistors constituting the driving circuit 12a have only to be provided with a withstand voltage of 24 V, even if a margin of ±20 V is allowed. Therefore, it will well serve the purpose if the transistors have a withstand voltage of 30 V. With the prior art protective circuit of FIG. 1, the transistor Q 3  is impressed with a voltage of ±50 V. That is, the transistor Q 13  must have a withstand voltage of 100 V. Therefore, the protective circuit of this invention arranged as shown in FIG. 3 is obviously more adapted for integration. To effect said integration, it is better to set the resistors R 11 , R 13  outside of an integrated protective circuit. 
     A potential difference V 1  -V 2  between the first signal V 1  and the second signal V 2  which arises during the positive halfwave period of load current is expessed by the following equation (8) (assuming R 11  =R 13  and R 15  =R 16 ): ##EQU10## where, Na is a ratio between current running through the diode D 14  and current flowing through the transistor Q 19 . Said ratio can generally be defined changing a ratio between the areas of the emitters of the diode D 14  and transistor Q 19  during their manufacture. V BE  denotes a voltage impressed across the base and emitter of the transistor Q 19 , namely a threshold voltage thereof. The potential difference V 2  -V 1  between the potential V 2  of the second signal and the potential V 1  of the first signal can be determined during the negative halfwave period of load current by modifying the above equation (8). In this case, it is advised to cause Na to represent a ratio between current flowing through the diode D 13  and current conducted through the transistor Q 18 . 
     The potentials V u , V L  of the emitters of the transistors Q 1 , Q 2  jointly constituting a power amplifier which appear during the positive halfwave period of load voltage (load current) are expressed as follows: 
     
         V.sub.u =r.sub.E ·I.sub.0 +V.sub.0 
    
     
         V.sub.L =V.sub.0 
    
     Where, therefore, the driving circuit 12a is designed to produce an output in case of V 1  -V 2  ≧V th  (V th  represents a detecting voltage of the driving circuit), then the follwoing equation (9) results: ##EQU11## where 1/K denotes ##EQU12## 
     If the resistances of the respective resistors and Na are so defined as to satisfy 1/K v 0  &gt;V&#39; th  then there results r E  I 0  &gt;1/K v O  and in consequence the following formula (10): 
     
         K·r.sub.E ≧R.sub.L 
    
     It is seen from the above formula (10) that where the load resistance R L  has a smaller value than K·r E , then the driving circuit 12a can be operated. The parallel connected diodes D 11 , D 13  and the parallel connected diodes D 12 , D 14  have opposite polarities to each other. The resistors R 15 , R 16  are designed to be operated during the positive and negative halfwave periods of load current respectively. Therefore, load resistance can be detected during the positive or negative halfwave period of load current. The resistors R 11 , R 12 , R 15  decrease the potential of the first signal during the positive halfwave period of load current as does the resistor R 1  of FIG. 2. The resistors R 13 , R 14 , R 16  act in the same manner during the negative halfwave period of load current. Since a group of the resistors R 11 , R 15  and a group of resistors R 13 , R 16  can effect a voltage drop without the resistors R 12 , R 14  during the positive and negative halfwave periods of load current respectively, the last mentioned two resistors R 12 , R 14  can be omitted. 
     Referring to FIG. 3, where the load L has a higher resistance than prescribed, the first signal V 1  has its voltage decreased during the positive halfwave period of load current by current passing through the transistor Q 19  controlled by the signal V 2a  and resistors R 11 , R 12 . However, the voltage of the second signal V 2  does not drop, because the transistor Q 18  is not rendered conducting. As the result, the transistors Q 21 , Q 23  are rendered nonconducting and the transistor Q 28  is rendered conducting. Therefore the switch S is held in closed state. Where the load L is short-circuited, then the transistor Q 19  is rendered nonconducting to prevent current from running through the resistors R 11 , R 12 , thereby raising the potential of the first signal V 1  substantially up to the potential V u . At this time, the transistors Q 21 , Q 23  are rendered conducting and the transistor Q 28  is turned off, thereby opening the switch S. The same operations as described above take place during the negative halfwave period of load current. 
     As described above, the embodiment of FIG. 3 can decrease a withstand voltage demanded for the semiconductor elements constituting a protective circuit. 
     A protective circuit utilizing a potential difference between the first and second signals may comprise the load resistance-detecting circuit of FIG. 5. A junction 10a is connected to a first attenuator ATT 1a  formed of resistors R 21 , R 22 . The free end of the resistor 22 is grounded. A diode D A  of the indicated polarity is connected in parallel to the resistor R 22  through a resistor R 23 . A first signal V 1  is drawn out from a junction 20 between the resistors R 21 , R 22 . A junction 10b is connected to a second attenuator ATT 2a  formed of resistors R 24 , R 25 . The free end of the resistor R 25  is grounded. A diode D B  of the indicated polarity is connected through a resistor R 26  in parallel to the resistor R 25 . A second signal V 2  is drawn out from a junction 22 between the resistors R 24 , R 25 . A driving circuit supplied with the first and second signals has the same arrangement as the driving circuit 12a of FIG. 3. Referring to FIG. 5, the diode D A  is rendered nonconducting and the diode D B  is rendered conducting during the negative halfwave period of load current. During the positive halfwave period of load current, the diode D A  is put into operation, and the diode D B  is turned off. Assuming R 21  =R 24 , R 22  =R 25 , R 23  =R 26  and ##EQU13## then the following equation results during the positive halfwave period of load current. ##EQU14## 
     When detected in case of V 1  -V 2  ≧0, the load resistance is expressed by the following equation: ##EQU15## where K&#39; denotes ##EQU16## 
     The same result as described above is also obtained during the negative halfwave period of load current.