Abstract:
A frequency synthesizer device has an input port for a digital code which defines the frequency to be synthesized and an accumulator circuit for successively counting the digital codes in the form of numbers in time with signals of an accumulation clock. An accumulation decoder is coupled to the accumulator circuit and supplies accumulation information relating to the counted number in the accumulator circuit. A variable divider circuit is controlled by this accumulation information to supply the synthesized frequency signals based upon the signals of a reference clock.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a frequency synthesizing device having an input access for a digital code which defines the frequency to be synthesized and an accumulator circuit for successively counting the digital codes, in the form of numbers, in time with signals of an accumulation clock. 
     A device of this type finds important applications, especially in the field of data transmission where the carrier frequency of the data is to be established with very great precision. 
     A device of this type is known from U.S. Pat. No. 4,514,696. 
     This device produces an output frequency f u  based upon an N-bit digital code C: 
     
         f.sub.u C×F.sub.R /2.sup.N 
    
     where F R  is the frequency of the signals of a reference clock preferably formed, as is common practice, by a quartz crystal. From this formula is derived the variation step Δf given by the formula: 
     
         Δf=F.sub.R /2.sup.N 
    
     while admitting that the variation of C is unitarian. 
     In the applications considered above, in which the device is used in a phase locked loop for restoring the carrier, this variation step is considered very important. 
     SUMMARY OF THE INVENTION 
     The invention proposes a device of the type defined in the opening paragraph which thus has a finer variation step for obtaining an output frequency based upon a reference frequency. 
     Therefore, such a device is characterized in that it comprises an accumulation decoder which, coupled to said accumulator circuit, supplies accumulation information relating to the number accumulated in this accumulator circuit and includes a variable divider circuit controlled by this accumulation information to supply the synthesized frequency signals based upon signals of a reference clock. 
     According to a preferred embodiment of the invention the accumulation clock signals are formed from synthesized frequency signals. In this manner the advantage is obtained that the operation of the device runs absolutely synchronous with the frequency of the synthesized frequency signals. This makes it possible to model the behaviour of the device, which facilitates its use in complex systems such as said phase control systems. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The following description, made with reference to the appended drawings, all given by way of non-limiting example, will make it better understood how the invention may be realised, in which 
     FIG. 1 shows a frequency synthesizing device according to the invention, 
     FIG. 2 shows a variant of an embodiment of a variable divider forming a part of a device according to the invention, and 
     FIG. 3 is a time diagram intended to explain the device shown in FIG. 2. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1 reference 1 indicates a device according to the invention. This device produces at its output 5 a signal whose frequency is determined by a digital code of, for example, N bits applied to the input terminals 10. This device comprises an accumulator circuit 15 formed by an adder 20 which has two code inputs A and B, and an accumulation register 22. Input A of the adder receives the digital code applied to the terminals 10 and input B is connected to the output of the adder 20 via register 22. An EXCLUSIVE-OR gate 25 serving as an accumulation decoder produces a logic &#34;1&#34; signal to indicate the changing of the value of the most significant bit of the accumulator. Therefore, the inputs of this gate are connected, respectively, to the input line MA and to the output line MP of the register 22 while transmitting the most significant bits. 
     According to the invention, a signal indicating certain contents of the accumulator circuit which is, for example, supplied at the output of the EXCLUSIVE-OR gate 25, is used for activating a variable divider circuit 40 which has an input connected to a reference oscillator 45 and an output 5 which forms the output of the device 1. Circuit 40 is formed by two fixed dividers 51 and 52 for dividing by N 1  and N 2 , respectively, the frequency of the oscillator 45. The two-position switch 54 connects the signal processed by one of these dividers to output 5. The choice of these positions is determined by the value of the output signal of gate 25. The accumulations take place according to an aspect of the invention in time with the signal present on output 5, which constitutes an accumulation clock signal. 
     For a better understanding of the purpose of the invention, it is appropriate to utilize the following considerations. Let M be the number of bits processed by the accumulator circuit 15. The N-bit code C on input 10 is such that: 
     
         0&lt;C&lt;2.sup.N -1. 
    
     This code is accumulated in the register 22 and causes the change of the value of the most significant bit in k accumulations when: 
     
         k·C&gt;2.sup.m-1. 
    
     If T u  is called the period of the signal on output 5, the time interval T SD  separating two &#34;1&#34; pulses is given by the relation: ##EQU1## 
     If there is admitted that if SD=0, one has: ##EQU2## and if SD=1: ##EQU3## a relation is formed between the user frequency F U  and the code C: During T SD  -T U2 , SD is &#34;0&#34; and the user frequency F U1  =F R  /N1. 
     During T U2 , SD is &#34;1&#34; and the user frequency F U2  =F R  /N2. 
     The mean user frequency has the value of: ##EQU4## or finally: ##EQU5## 
     It will be observed thus that the variation step Δf becomes: ##EQU6## and by choosing N1 and N2 this step is controlled as finely as one wishes. 
     FIG. 2 shows an embodiment for a variable divider circuit 40&#39; where N1=16 and N2=15.5, thus well adapted to phase controls. This circuit is formed by a divider 60 which divides by N 3  (N 3  =16) the frequency of the quartz crystal oscillator signals 45 transmitted via an EXCLUSIVE-OR gate 62 which has two inputs of which the first input is connected to the output of the oscillator 45 and the second input is connected to the output of a D-type flip-flop referenced 65. The output of this flip-flop is further connected to an input of another EXCLUSIVE-OR gate 67 of which another input forms the input of this circuit 40&#39; and is thus connected to the output of gate 25. The output of the EXCLUSIVE-OR gate 67 is connected to the input of the flip-flop 65. The input which permits the change of state of this flip-flop is connected to the output of the divider 60. 
     The operation of this circuit 40&#39; will be explained with the aid of FIG. 3. For this explanation it will be useful to consider the signals, F R , F U , SD, A and B occurring respectively on the outputs of the oscillator 45, divider 60, gate 25, flip-flop 65 and gate 62. 
     Let us consider instant t 0  and assume that signal SD has the &#34;0&#34; value as has signal A. Therefore, signal B is a copy of signal F R . Then one goes to instant t 1  where the signal SD assumes the value &#34;1&#34;. The signal on the output of the gate 67 is thus inverted to the input of flip-flop 65 which is prepared to change state. This happens at t 2  when the divider 60 has finished its counting cycle. Because of this switching, signals B now represent the inverted signals F R . It will be noted that this inversion never coincides with an edge of the signals F R  which is due to the delay caused by the various circuits. In this manner an additional half pulse is created to be divided by the divider 60. If the signal SD retains its value &#34;1&#34;, the end of the dividing cycle of this same divider 60 will entail the switching of the flip-flop 65 and hence the creation of a half pulse for the divider 60.