Abstract:
A power amplifier includes: an active device having at least one heterojunction bipolar transistor based on a compound semiconductor; a diode connected between the base and the emitter of the bipolar transistor in reverse direction with respect to the base-emitter diode; a resistor connected in series between the diode and the base of the bipolar transistor; and a bias circuit connected between the diode and the resistor. A power amplifier may alternatively includes: an active device having at least one heterojunction bipolar transistor based on a compound semiconductor; a diode connected between the base and the emitter of the bipolar transistor in reverse direction with respect to the base-emitter diode; two resistors connected in series between the diode and the base of the bipolar transistor; and a bias circuit connected between the two resistors. A power amplifier may alternatively includes: a substrate; an active device region provided on the substrate and having at least one heterojunction bipolar transistor based on a compound semiconductor; a diode region provided on the substrate and including a diode connected between the base and the emitter of the bipolar transistor in reverse direction with respect to the base-emitter diode; a resistor region provided on the substrate and including a resistor connected in series between one electrode of the diode and the base of the bipolar transistor; a device isolation region provided on the substrate for isolating the active device region, the diode region, and the resistor region; and a power supply terminal provided on the substrate and connected to the resistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2005-371513, filed on Dec. 26, 2005; the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     This invention relates to a power amplifier having an ESD protection circuit and formed on a semiconductor chip based on bipolar transistors.  
         [0004]     2. Background Art  
         [0005]     In recent years, there is a growing demand for downsizing on compact information devices as typified by mobile phones. Small peripheral components (such as chip capacitors and inductors) are incorporated and modularized into corresponding key components, and the number of peripheral components is being reduced. Thus such modules are directly exposed to the external environment. What particularly matters in this situation is the tolerance to ESD (electrostatic discharge). ESD is a phenomenon in which electric charge accumulated in a device or human body external to a circuit is instantaneously discharged to the circuit. When a circuit is installed in a device or is in use, electric charge is inevitably produced due to the motion of the device or human body. Therefore, in a device exposed to the external environment, it is necessary to ensure ESD tolerance on the circuit side.  
         [0006]     The main cause of ESD breakdown is believed to be thermal breakdown due to the instantaneous flow of electric charge accumulated at high energy (high potential) into the circuit. Thus the ESD protection circuit serves to prevent the high-energy electric charge from flowing into the thermally weak semiconductor device.  
         [0007]     Conventionally, a circuit having such function is realized by a circuit having a diode connected in series between a terminal to be protected and a ground terminal for passing current when a prescribed voltage is exceeded. When a voltage above the turn-on voltage of the diode is applied to its terminal, the diode becomes conducting to prevent electric charge from flowing into the circuit to be protected. Here, the prescribed voltage needs to be set to a value higher than voltages required for operation of the circuit such as the power supply voltage and the operating voltage. To this end, a plurality of stages of diodes are used as disclosed in JP 2003-023084A.  
         [0008]     However, this type of circuit has a problem that the diode itself constituting the protection circuit is broken by the inflow of high energy. To prevent this, it may be contemplated as disclosed in JP 8-236637A that a resistor is inserted in series with the protection device (such as a diode) to cause voltage drop and reduce current flowing into the protection device. In this case, the voltage drop increases as the value of resistance increases, and thereby the tolerance is improved. However, because energy inflow to the protection circuit side is disturbed, the operation as a protection circuit becomes uncertain. Thus a resistor with several to ten and several ohms is required. Furthermore, because the resistor itself must withstand large energy loss, it is necessary to use a resistor having a high current capacity realized by a semiconductor rather than a resistor having a small current capacity realized by a metal thin film.  
         [0009]     However, the value of sheet resistance of a semiconductor resistor is ten and several Ω/□ even with high-concentration doping. To achieve several Ω requires a large aspect ratio, which consumes a large area on the chip. Then the chip area is increased, and the increase of packaging area adversely affects downsizing. Furthermore, when the wafer price is high as in the case of compound semiconductors, there is also a problem of cost.  
         [0010]     As described above, conventional diode-connected circuits require a large area for achieving high ESD tolerance and have problems in pellet size and cost.  
         [0011]     On the other hand, JP 2001-274636A discloses an amplifier which is excellent in uniformity of current distribution in spite of a small ballast resistance and has high efficiency and low distortion, exhibiting little deterioration of distortion even when a digital modulation wave is input thereto. This amplifier is a high frequency power amplifier based on bipolar transistors, comprising at least two or more blocks. Each block includes a bias generation circuit for generating a base bias potential and a capacitor device for high frequency input. Each bias generation circuit comprises a second bipolar transistor for impedance conversion and a diode circuit having a current mirror transistor, the diode circuit being subjected to constant current biasing for temperature detection.  
       SUMMARY OF THE INVENTION  
       [0012]     According to an aspect of the invention, there is provided a power amplifier including: an active device having at least one heterojunction bipolar transistor based on a compound semiconductor; a diode connected between the base and the emitter of the bipolar transistor in reverse direction with respect to the base-emitter diode; a resistor connected in series between the diode and the base of the bipolar transistor; and a bias circuit connected between the diode and the resistor.  
         [0013]     According to other aspect of the invention, there is provided a power amplifier including: an active device having at least one heterojunction bipolar transistor based on a compound semiconductor; a diode connected between the base and the emitter of the bipolar transistor in reverse direction with respect to the base-emitter diode; two resistors connected in series between the diode and the base of the bipolar transistor; and a bias circuit connected between the two resistors.  
         [0014]     According to other aspect of the invention, there is provided a power amplifier including: a substrate; an active device region provided on the substrate and having at least one heterojunction bipolar transistor based on a compound semiconductor; a diode region provided on the substrate and including a diode connected between the base and the emitter of the bipolar transistor in reverse direction with respect to the base-emitter diode; a resistor region provided on the substrate and including a resistor connected in series between one electrode of the diode and the base of the bipolar transistor; a device isolation region provided on the substrate for isolating the active device region, the diode region, and the resistor region; and a power supply terminal provided on the substrate and connected between the diode and the resistor. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]      FIGS. 1A and 1B  are circuit diagrams of a power amplifier formed on a semiconductor substrate according to a first embodiment of the invention.  
         [0016]      FIG. 2  is a characteristic diagram showing the result of an ESD tolerance test (negative side) for the power amplifier of  FIG. 1 .  
         [0017]      FIG. 3  is a characteristic diagram showing the result of an ESD tolerance test (positive side) for the power amplifier of  FIG. 1 .  
         [0018]      FIG. 4  is a cross section of a semiconductor chip having the bipolar transistor and the diode of the power amplifier shown in  FIG. 1 .  
         [0019]      FIG. 5  is a plan view of the semiconductor chip shown in  FIG. 4 .  
         [0020]      FIG. 6  is a circuit diagram of a power amplifier formed on a semiconductor substrate according to a second embodiment of the invention.  
         [0021]      FIG. 7  is a circuit diagram of a power amplifier formed on a semiconductor substrate according to a third embodiment of the invention.  
         [0022]      FIG. 8  is a characteristic diagram illustrating the generation of negative voltage due to ringing.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0023]     Embodiments of the invention will now be described.  
       FIRST EMBODIMENT  
       [0024]     The first embodiment is described with reference to FIGS.  1  to  5  and  8 .  
         [0025]      FIG. 1  is a circuit diagram of a power amplifier formed on a semiconductor substrate according to this embodiment.  FIG. 2  is a characteristic diagram showing the result of an ESD tolerance test (negative side) in this embodiment.  FIG. 3  is a characteristic diagram showing the result of an ESD tolerance test (positive side).  FIG. 4  is a cross section of a semiconductor chip having the bipolar transistor and the diode of the power amplifier shown in  FIG. 1 .  FIG. 5  is a plan view of the semiconductor chip shown in  FIG. 4 .  FIG. 8  is a characteristic diagram illustrating the generation of negative voltage due to ringing. The cross section taken along line A-A′ in  FIG. 5  is shown in  FIG. 4 . For simplicity of description,  FIG. 5  does not show the insulating film  18  and the interconnect layer (second metal)  13   a  shown in  FIG. 4 .  
         [0026]     As shown in  FIGS. 4 and 5 , the semiconductor substrate with a semiconductor chip formed thereon comprises a GaAs semi-insulating substrate, on which an epitaxial growth layer is laminated. A heterojunction bipolar transistor (hereinafter referred to as HBT) is provided in this laminated structure. An n + -GaAs epitaxial layer  3  having a high-concentration collector region and an n − -GaAs epitaxial layer  4  having a low-concentration collector region are successively formed directly on the GaAs semi-insulating substrate  1 . A base region (p-GaAs epitaxial layer)  5  and an emitter region (n − -InGaP epitaxial layer)  6  are successively laminated on the low-concentration collector region of the epitaxial layer  4 . The emitter region  6 , the collector region  4 , and the base region  5  collectively constitute an npn-bipolar transistor  10 . On this HBT  10 , a collector electrode  7  is formed on the collector region constituting the epitaxial layer  3 , a base electrode  8  on the base region  5 , and an emitter electrode  9  on the emitter region  6 .  
         [0027]     A diode D is formed on the semiconductor substrate  1 . The diode D is connected between the base region  5  and the emitter region  6  in reverse to the base-emitter diode. The diode D is composed of the epitaxial layer constituting the base region  5  and the epitaxial layer  4 . Electrodes  11 ,  11   a  are formed on the epitaxial layer  3  and on the base region  5 , respectively (see  FIG. 4 ). The epitaxial layer  3  between electrodes  16  and  16   a  constitutes a resistor R (see  FIG. 5 ). Furthermore, a MIM capacitor C is provided on the semiconductor substrate. The MIM capacitor C uses a metal interconnect layer (first metal)  13  as one of its electrodes and a silicon nitride film or other interlayer insulating film (not shown) as its dielectric.  
         [0028]     As shown in  FIGS. 4 and 5 , the HBT  10 , the diode D, and the resistor R are formed in a device region defined by a device isolation region. The HBT  10  and the diode D are covered with an interlayer insulating film  18  made of polyimide or the like. The emitter electrode  9  of the HBT  10  and the electrode  11   a  of the diode D are electrically connected to the metal interconnect layer (second metal)  13   a  formed on the interlayer insulating film  18 . As shown in  FIG. 5 , the electrodes  16 ,  16   a  of the resistor R are electrically connected to the metal interconnect layer (first metal)  13  formed on the interlayer insulating film (not shown). Furthermore, a plurality of HBTs  10  are formed on the semiconductor substrate. While  FIG. 1  is a circuit diagram having one HBT in the circuit to be protected, this embodiment may include more than one HBT (the amplifier of  FIG. 5  corresponds to this circuit diagram).  
         [0029]     Next, the circuit configuration of the power amplifier of this embodiment is described with reference to  FIG. 1A . The circuit to be protected is shown as including one HBT  10 , and the other configuration of the circuit to be protected is not shown. The HBT  10  of the circuit to be protected has a collector terminal  12  coupled to the collector  4  and a ground terminal  14  coupled to the emitter  6 . A bias circuit  17  is coupled to the base  5 . A ballast resistor R of about 4 Ω, for example, for the bias circuit  17  is inserted between the bias circuit  17  and the base  5 . The base  5  is connected to the input circuit of an external RF circuit via the MIM capacitor C. The bias circuit  17  is connected also to the emitter  6 . A diode D is inserted between the bias circuit  17  and the emitter  6  or between the bias circuit  17  and the ground terminal  14  in the reverse direction with respect to the base-emitter junction. According to this configuration, the resistor R can prevent the diode D from being broken by ESD.  
         [0030]     As compared with the power amplifier having a protection circuit (series circuit of a resistor and a diode) of  FIG. 1 , ESD tolerance in the case of no protection circuit is determined by a negative voltage applied to the collector terminal of the transistor in the circuit to be protected. The value of the voltage is about −30 V. In this case, the base-emitter pn-junction is damaged by ESD and loses the function of a transistor.  
         [0031]     In this embodiment, a diode with a size of 10 μm×30 μm serving as an ESD protection device is placed between the base and the emitter of the HBT. The diode is formed from the base region and the collector region of the HBT. Thus no additional wafer structure or process is required for forming the diode. Furthermore, a resistor is connected in series as a protection resistor for the diode. This can prevent damage to the device in the case of negative ESD by allowing discharge through the current path shown in the figure.  
         [0032]     Moreover, to configure a circuit, an appropriate bias voltage needs to be applied to the base terminal of the transistor. In particular, a high power circuit such as a power amplifier may be based on a technique of inserting a resistor, called a ballast resistor, between the bias circuit and the base terminal for ensuring thermal stability. When the HBT is about to fall into thermal runaway and to allow a large current to flow into the base terminal of the transistor, the ballast resistor serves to cause voltage drop and lower the bias point of the transistor which would otherwise lead to thermal runaway. This embodiment has a circuit configuration where the ballast resistor also serves as a diode protection resistor. Thus, addition of an ESD protection circuit requires no additional devices other than the diode. Therefore the increase of the chip area can be reduced. Furthermore, insertion of the protection resistor also prevents the diode itself from being broken by ESD. Thus the required ESD tolerance can be ensured.  
         [0033]      FIG. 2  shows the result of an ESD test conducted by using the protection circuit shown in  FIG. 1A . Because a transistor is used in the ESD discharge path, the withstand capability depends on the size of the transistor. However, it is seen that the withstand capability is higher than in the case of no protection circuit. It is also seen that, because a ballast resistor is used as a protection resistor, the circuit achieves, without an additional protection resistor, a withstand capability of over −400 V, which is the withstand capability of an ESD protection diode itself.  
         [0034]     Furthermore, the base-emitter diode configured as a heterojunction for improving the characteristics of the HBT transistor allows the pn-junction to achieve steeper switching than the base-emitter junction formed by homojunction. Here, the base-emitter diode has the tendency to cause steep (hard) breakdown for ESD with relatively low reverse voltages.  
         [0035]     On the other hand, at the base-collector junction, a collector layer doped with low concentration is formed for reducing the base-collector parasite capacitance. Therefore the base-collector junction has the form of a pin-diode. As a result, the base-collector junction has high ESD tolerance irrespective of whether it is homojunction or heterojunction.  
         [0036]     Because of such HBT characteristics, only a protection circuit for protecting the base-emitter junction is inserted in this embodiment. As shown in  FIG. 1A , this protection circuit is configured with only a protection path for negative ESD. However, because the base-collector junction has high ESD tolerance, the withstand capability for positive ESD is also effectively improved. Specifically, as described above, even in the case of no protection circuit, the base-collector diode of the HBT has high ESD withstand capability also against reverse applied voltage and does not result in breakdown. However, the applied ESD waveform exhibits ringing due to an external circuit (inductance component), and the voltage waveform is also caused to swing into the negative side even when the voltage is applied to the positive side (see  FIG. 8 ). Thus the base-emitter diode is broken because of its insufficient withstand capability. Consequently, in spite of the ESD withstand capability test on the positive side, the breakdown of the base-emitter junction having a small ESD withstand capability on the negative side determines the ESD withstand capability on the positive side. In this embodiment, because an ESD protection circuit with a protection resistor is formed between the base and the emitter, the base-emitter junction is protected even under the influence of ringing. As a result, a high withstand capability can be achieved also on the positive side.  
         [0037]      FIG. 3  shows the experimental verification of improved withstand capability for positive ESD that is achieved even when the current path for ESD is prepared only on the negative side. With regard to breakdown locations, it is found that the base-emitter diode is broken, suggesting that the ESD withstand capability is determined by the principle described above. In this case again, the effect of the protection resistor remains unchanged. The protection circuit of this embodiment achieves high withstand capability for both positive and negative ESD.  
         [0038]     As described above, the ESD tolerance of an HBT-based circuit can be significantly improved both on the positive and negative side simply by protecting the base-emitter junction. Thus it is possible to provide a protection circuit achieving high ESD tolerance while solving the problem of increased cost and area in the conventional circuits.  
         [0039]     While  FIG. 1A  shows a single HBT in the circuit to be protected, the circuit to be protected shown in  FIG. 5  has a plurality of HBTs. These HBTs have common terminals (collector terminal and ground terminal) and a common bias circuit. The bias circuit is connected to the base of each HBT via a ballast resistor. Therefore any number of one or more HBTs can be used in the circuit to be protected in this embodiment.  
         [0040]     Here, a circuit configuration having separately a ballast resistor and a diode protection resistor is described.  FIG. 1B  is a circuit diagram thereof. The ballast resistor R 11  has a resistance value determined so as to prevent thermal runaway of the bipolar transistor. To prevent thermal runaway, R 11  is preferably 1 Ω or more. Furthermore, to improve breakdown tolerance while maintaining the operation of the protection circuit against high energy, the sum of the additional diode resistance R 12  and the ballast resistance R 11 , R 11 +R 12 , is preferably 3 to 7 Ω. Thus the ballast resistance R 11  and the additional diode resistance R 12  can be appropriately determined. For example, by setting R 11  to 4 Ω and R 12  to 2 Ω, the circuit can be protected against high energy while preventing thermal runaway. Thus the breakdown tolerance of the diode can be improved.  
       SECOND EMBODIMENT  
       [0041]     The second embodiment is described with reference to  FIG. 6 .  
         [0042]      FIG. 6  is a circuit diagram of a power amplifier formed on a semiconductor substrate according to this embodiment. The protection circuit of the second embodiment, which has a circuit configuration similar to that of the first embodiment, is characterized in that an emitter follower circuit is used as a bias circuit.  
         [0043]     Next, the circuit configuration of the power amplifier of this embodiment is described with reference to  FIG. 6 . The circuit to be protected is shown as including one HBT  20 , and the other configuration is not shown. The HBT  20  of the circuit to be protected has a collector terminal  22  coupled to the collector and a ground terminal  23  coupled to the emitter. A bias circuit  27  is coupled to the base. A ballast resistor R of about 4 Ω, for example, for the bias circuit is inserted between the bias circuit  27  and the base. A diode D is inserted between the bias circuit  27  and the emitter or between the bias circuit  27  and the ground terminal  23  in the reverse direction with respect to the base-emitter junction. According to this configuration, the resistor R can prevent the diode D from being broken by ESD. The base of the transistor  20  is connected to the input circuit of an external RF circuit via the MIM capacitor C. One end of the resistor R is connected between the MIM capacitor C and the base  5 , and the other end is connected to the bias circuit  27 .  
         [0044]     As compared with the power amplifier having a protection circuit (series circuit of a resistor and a diode) of  FIG. 6 , in the case of no protection circuit, ESD tolerance of the transistor in the circuit to be protected is determined by a negative voltage applied to the collector terminal. The value of the voltage is about −30 V. In this case, the base-emitter pn-junction is damaged by ESD and loses the function of a transistor.  
         [0045]     In this embodiment, a diode D with a size of 10 μm×30 μm serving as an ESD protection device is placed between the base and the emitter of the HBT. The diode D is formed from the base region and the collector region of the HBT formed on the semiconductor substrate. Thus no additional wafer structure or process is required for forming the diode. Furthermore, a resistor R is connected in series as a protection resistor for the diode D. This can prevent damage to the device in the case of negative ESD by allowing discharge through the collector terminal.  
         [0046]     In a high power circuit such as a power amplifier, a ballast resistor is inserted between the bias circuit and the base terminal for ensuring thermal stability. In this embodiment, the ballast resistor also serves as a diode protection resistor. Thus, addition of an ESD protection circuit requires no additional devices other than the diode. Therefore the increase of the chip area can be reduced. Furthermore, insertion of the protection resistor also prevents the diode itself from being broken by ESD. Thus the required ESD tolerance can be ensured.  
         [0047]     The bias circuit is further described with reference to  FIG. 6 .  
         [0048]     The bias circuit  27  of  FIG. 6  comprises a bipolar transistor  21 . The bipolar transistor  21  has a collector terminal  24  coupled to the collector, a ground terminal  25  coupled to the emitter, and a control terminal  26  coupled to the base. A diode Dl is inserted between the base and the emitter of the bipolar transistor  21  in the reverse direction with respect to the base-emitter junction. A diode D 4  is inserted between the emitter of the bipolar transistor  21  and the ground terminal  25 . Diodes D 2 , D 3  are inserted between the base of the bipolar transistor  21  and the ground terminal  25 . The diode D 1  is connected between the diode D 2  and the base of the bipolar transistor  21 .  
         [0049]     The control terminal  26  is connected between the diodes D 1  and D 2  via a resistor R 1 . A coil L connected between the emitter of the bipolar transistor  21  and the diode D 4  is connected between the diode D and the resistor R that are connected between the base and the emitter of the bipolar transistor  20 .  
         [0050]     In the emitter follower circuit constituting the bias circuit  27 , the ESD withstand capability for the collector terminal  24  is the lowest. Therefore a protection circuit is required for the collector terminal  24 . In this embodiment, a diode Dl is connected as a protection circuit between the base and the emitter of the emitter follower circuit. The discharge path upon application of negative ESD to the collector terminal  24  of the emitter follower circuit is indicated by a dotted arrow.  
         [0051]     Because this discharge path includes a plurality of diodes (diodes D, D 1 ), it has a parasite resistance component. This component can serve as a protection resistance. Thus it is not necessary to additionally insert a protection resistance. Conversely, the direct connection of the protection diode to the circuit advantageously improves the withstand capability. Protection for negative ESD to the control terminal  26  is also achieved.  
         [0052]     As described above, in addition to the advantageous effect described in the first embodiment, this embodiment also achieves a protection effect on the bias circuit. Thus the circuit as a whole can achieve higher ESD tolerance.  
       THIRD EMBODIMENT  
       [0053]     The third embodiment is described with reference to  FIG. 7 .  
         [0054]      FIG. 7  is a circuit diagram of a power amplifier formed on a semiconductor substrate according to this embodiment. The circuit to be protected is shown as including HBTs  30 , and the other configuration is not shown. The HBTs  30  comprise a plurality of HBTs Q 1 , Q 2 , Q 3 , . . . The HBTs  30  have a common collector terminal  32  connected to the collector of each HBT Q 1 , Q 2 , Q 3 , . . . and a common ground terminal  33  connected to the emitter of each HBT Q 1 , Q 2 , Q 3 , . . . The base of each HBT Q 1 , Q 2 , Q 3 , . . . is connected to the bias circuit  31 .  
         [0055]     In this embodiment, ballast resistors R 1 , R 2 , R 3 , . . . for the bias circuit  31  are each inserted between the bias circuit  31  and the base of each HBT Q 1 , Q 2 , Q 3 , . . . The ballast resistors R 1 , R 2 , R 3 , . . . are used as a protection resistor. One end of the ballast resistor R 1 , R 2 , R 3 , . . . is connected to the base of the HBT Q 1 , Q 2 , Q 3 , . . . , respectively. To the other end is connected a diode D in the reverse direction with respect to the base-emitter junction. According to this configuration, the ballast resistors R 1 , R 2 , R 3 , . . . can prevent the diode D from being broken by ESD. The plan view of the semiconductor substrate of  FIG. 5  described in the first embodiment shows one ballast resistor R for a plurality of HBTs. However, in the present embodiment, although not shown, ballast resistors are formed so that a ballast resistor is connected to the base of each HBT on the semiconductor substrate.  
         [0056]     In this embodiment, like the first and second embodiment, the diode is formed from the base region and the collector region of the HBT. Thus no additional wafer structure or process is required for forming the diode. Furthermore, a resistor is connected in series as a protection resistor for the diode. This can prevent damage to the device in the case of negative ESD by allowing discharge.  
         [0057]     Moreover, to configure a circuit, an appropriate bias voltage needs to be applied to the base terminal of the transistor. In particular, a high power circuit such as a power amplifier may be based on a technique of inserting a resistor, called a ballast resistor, between the bias circuit and the base terminal for ensuring thermal stability. When the HBT is about to fall into thermal runaway and to allow a large current to flow into the base terminal of the transistor, the ballast resistor serves to cause voltage drop and lower the bias point of the transistor which would otherwise lead to thermal runaway. This embodiment has a circuit configuration where the ballast resistor also serves as a diode protection resistor.