Abstract:
This disclosure concerns a semiconductor device comprising a switching transistor provided on a semiconductor substrate; an interlayer dielectric film formed on the switching transistor; a ferroelectric capacitor including an upper electrode, a ferroelectric film, and a lower electrode formed on the interlayer dielectric film; a contact plug provided in the interlayer dielectric film and electrically connected to the lower electrode; a diffusion layer connecting between the contact plug and the switching transistor; a trench formed around the ferroelectric capacitor; and a barrier film filling in the trench and provided on a side surface of the ferroelectric capacitor and on an upper surface of the interlayer dielectric film, the barrier film suppressing percolation of hydrogen, wherein a thickness of the barrier film on the side surface of the ferroelectric capacitor is larger than a thickness of the barrier film on the upper surface of the interlayer dielectric film.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2007-154949, filed on Jun. 12, 2007, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor device, and relates to a ferroelectric memory having a ferroelectric capacitor, for example. 
         [0004]    2. Related Art 
         [0005]    Along with the miniaturization of a ferroelectric memory device, damage to a ferroelectric capacitor becomes remarkable. As one of causes for this, there is an influence of hydrogen entering from a contact portion of an upper electrode. For example, there is a process of embedding tungsten into a contact hole formed on the upper electrode. The tungsten deposition process is performed in the atmosphere containing a large amount of hydrogen. Therefore, hydrogen enters from a side surface of a ferroelectric film, and degrades a ferroelectric material. 
         [0006]    To solve this problem, a barrier film blocking hydrogen is provided to cover the ferroelectric capacitor. However, along the progress of high integration, a taper angle of the side surface of the ferroelectric capacitor and an aspect ratio between the ferroelectric capacities becomes high. Therefore, it becomes difficult to deposit a barrier film having a sufficient film thickness on the side surface of the ferroelectric capacitor, and degrades the ferroelectric material by hydrogen. 
       SUMMARY OF THE INVENTION 
       [0007]    A semiconductor device according to an embodiment of the present invention comprises a switching transistor provided on a semiconductor substrate; an interlayer dielectric film formed on the switching transistor; a ferroelectric capacitor including an upper electrode, a ferroelectric film, and a lower electrode formed on the interlayer dielectric film; a contact plug provided in the interlayer dielectric film and electrically connected to the lower electrode; a diffusion layer connecting between the contact plug and the switching transistor; a trench formed around the ferroelectric capacitor; and a barrier film filling in the trench and provided on a side surface of the ferroelectric capacitor and on an upper surface of the interlayer dielectric film, the barrier film suppressing percolation of hydrogen, wherein a thickness of the barrier film on the side surface of the ferroelectric capacitor is larger than a thickness of the barrier film on the upper surface of the interlayer dielectric film. 
         [0008]    A method of manufacturing a semiconductor device according to an embodiment of the present invention, the semiconductor device including a ferroelectric capacitor including an upper electrode, a ferroelectric film, and a lower electrode, the manufacturing method comprises forming a switching transistor on a semiconductor substrate and forming a diffusion layer connected to the switching transistor; forming a first interlayer dielectric film on the switching transistor; forming a contact plug connected to the diffusion layer in the first interlayer dielectric film; forming the ferroelectric capacitor on the contact plug; depositing a first barrier film suppressing percolation of hydrogen on the ferroelectric capacitor and on the first interlayer dielectric film; depositing a second interlayer dielectric film on the first barrier film; forming a trench between the side surface of the ferroelectric capacitor and the second interlayer dielectric film by etching the second interlayer dielectric film around the ferroelectric capacitor; and filling a second barrier film into the trench. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is a cross-sectional view showing a configuration of a ferroelectric memory according to a first embodiment of the present invention; 
           [0010]      FIG. 2  is a cross-sectional view showing one example of the ferroelectric memory according to the first embodiment; 
           [0011]      FIGS. 3 to 9  are cross-sectional views showing a method of manufacturing the ferroelectric memory according to the first embodiment; 
           [0012]      FIG. 10  is a cross-sectional view of a ferroelectric memory according to a second embodiment of the present invention; 
           [0013]      FIGS. 11 to 15  are cross-sectional views showing a method of manufacturing the ferroelectric memory according to the second embodiment; 
           [0014]      FIG. 16  is a cross-sectional view of a ferroelectric memory according to a third embodiment of the present invention; 
           [0015]      FIG. 17  is a top plan view of a layer along a line  17 - 17  in  FIG. 16 ; 
           [0016]      FIG. 18  is a cross-sectional view of a ferroelectric memory according to a fourth embodiment of the present invention; 
           [0017]      FIG. 19  is a cross-sectional view of a ferroelectric memory according to a fifth embodiment of the present invention; 
           [0018]      FIG. 20  is a cross-sectional view of a ferroelectric memory according to a sixth embodiment of the present invention; 
           [0019]      FIGS. 21A and 21B  are top plan views showing a relationship between a barrier film BM 4  and the contact plug CP 3 ; 
           [0020]      FIG. 22  is a cross-sectional view of a ferroelectric memory according to a seventh embodiment of the present invention; 
           [0021]      FIG. 23  is a cross-sectional view showing a contact portion of the peripheral circuit region of the ferroelectric memory according to the seventh embodiment; and 
           [0022]      FIGS. 24 and 25  are cross-sectional views showing a method of manufacturing the ferroelectric memory according to the seventh embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0023]    Embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. Note that the invention is not limited thereto. 
       First Embodiment 
       [0024]      FIG. 1  is a cross-sectional view showing a configuration of a ferroelectric memory according to a first embodiment of the present invention. The ferroelectric memory according to the present embodiment includes a silicon substrate  10 , a switching transistor ST provided on the silicon substrate  10 , an interlayer dielectric film ILD 1  formed on the switching transistor ST, and a ferroelectric capacitor FC provided on the interlayer dielectric film ILD 1 . The ferroelectric capacitor FC is two-dimensionally laid out in a matrix above the silicon oxide film substrate  10 . 
         [0025]    The ferroelectric capacitor FC includes a lower electrode BE provided on the interlayer dielectric film ILD 1 , a ferroelectric film FE provided on the lower electrode BE, and an upper electrode TE provided on the ferroelectric film FE. The switching transistor ST includes source and drain diffusion layers DL 1  and DL 2 . A contact plug CP 1  is embedded into the interlayer dielectric film ILD 1  beneath the lower electrode BE. The contact plug CP 1  connects between the lower electrode BE and the diffusion layer DL 1 . Accordingly, the switching transistor ST is electrically connected to the lower electrode BE via the contact plug CP 1 . The lower electrode material includes a single-layer film such as Ti, TiN, TiAlN, Pt, Ir, IrO 2 , SrRuO 3  (hereinafter, also called SRO), Ru, and RuO 2 , or includes a lamination film including at least two of them. A ferroelectric material FE includes PZT (Pb(Zr x Ti (1-x) O 3 ), SBT (Sr x Bi y Ta z O a ), and BLT (Bi x La y O z ). In the above, x, y, z, a are positive numerals. In the present embodiment, the ferroelectric material FE includes PZT. An upper electrode material TE includes a single-layer film such as Pt, Ir, IrO 2 , SRO, Ru, and RuO 2 , or a lamination film including at least two of them. 
         [0026]    A barrier film BM 1  is provided on the side surface and the upper surface of the ferroelectric capacitor FC, and on the interlayer dielectric film ILD 1 . The barrier film BM 1  includes a single-layer film of Al 2 O 3 , SiN, and TiO 2 , or a lamination film of two or more of these films. The barrier film BM 1  including these materials has a characteristic of suppressing percolation of hydrogen, and interrupting hydrogen. 
         [0027]    Further, a barrier film BM 2  is provided on the side surface of the ferroelectric capacitor FC via the barrier film BM 1 . The barrier film BM 2  includes Al 2 O 3 , SiN, or TiO 2 . The barrier film BM 2  can be made of the same material as that of the barrier film BM 1 , or a different material. The barrier film BM 2  is a single continuous layer folded down into a trench  50  between a side surface of the barrier film BM 1  and a side surface of the interlayer dielectric film ILD 2 . Therefore, the barrier film BM 2  includes a seam  101  extending along with the side surface of the barrier film BM 1  and with the side surface of the interlayer dielectric film ILD 2 . The seam  101  is provided at an intermediate portion between the side surface of the barrier film BM 1  and the side surface of the interlayer dielectric film ILD 2 . 
         [0028]    An interlayer dielectric film ILD 2  is provided on the barrier films BM 1  and BM 2 . The interlayer dielectric film ILD 2  includes P-TEOS, O 3 -TEOS, SOG (Spin On Glass), and Low-k films (SiOF, SiOC). The interlayer dielectric film ILD 1  includes BPSG (Boron Phosphorous Silicate Glass), and P-TEOS (Plasma-Tetra Ethoxy Silane). Contact plugs CP 2  and CP 3  are embedded into the interlayer dielectric film ILD 2 . The contact plug CP 2  is electrically connected to a diffusion layer DL 2 . The contact plug CP 3  is connected to the upper electrode TE. The contact plugs CP 2  and CP 3  are connected to each other by a wiring  90  provided on the interlayer dielectric film ILD 2 . The contact plug CP 1  includes tungsten or doped polysilicon. The contact plugs CP 2  and CP 3  include materials of W, Al, TiN, Cu, Ti, Ta, and TaN. 
         [0029]      FIG. 2  is a cross-sectional view showing one example of the ferroelectric memory according to the first embodiment.  FIG. 2  shows a memory which consists of series connected memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor inbetween said two terminals, hereafter named “Series connected TC unit type ferroelectric RAM” The present embodiment can be also applied to an optional memory having a ferroelectric capacitor, not only to the TC parallel unit series-connection-type ferroelectric memory. 
         [0030]    While the side surface of the ferroelectric capacitor FC is etched substantially perpendicularly in  FIG. 1 , the side surface is actually formed in a sequentially tapered shape as shown in  FIG. 2 . In  FIG. 2 , the barrier films BM 1  and BM 2  are omitted.  FIG. 1  is a cross-sectional view along a first direction (a bit line direction) having plural unit cells connected in series. 
         [0031]    Referring back to  FIG. 1  again, in the present embodiment, a thickness T 2  of the barrier films BM 1  and BM 2  on the side surface of the ferroelectric capacitor FC is larger than a thickness T 1  of the barrier film BM 1  on the upper surface of the interlayer dielectric film ILD 1 . The thickness T 2  is a thickness in a direction perpendicular to the side surface of the ferroelectric capacitor FC. The thickness T 1  is a thickness in a direction perpendicular to the upper surface of the interlayer dielectric film ILD 1 . Accordingly, in the process of forming the contact plugs CP 2  and CP 3 , hydrogen can be prevented from entering the side surface of the ferroelectric film FE. 
         [0032]    A method of manufacturing the ferroelectric memory according to the first embodiment is explained with reference to  FIG. 3  to  FIG. 9 . In the drawings, a capacitor region and a peripheral circuit region are displayed together. First, as shown in  FIG. 3 , ST 1  (Shallow Trench Isolation) is formed on a silicon substrate  10  as an element isolation part  20 . A gate dielectric film  25  is formed on a surface of the silicon substrate  10 , and a gate electrode  32  is formed on the gate dielectric film  25 . Source and drain layers DL 1  and DL 2  are formed at both sides of the channel region by introducing an impurity, using the gate electrode  32  as a mask. As a result, the switching transistor ST is formed in the capacitor region, and a transistor Tr as an element configuring a circuit is formed in the peripheral circuit region. Next, the interlayer dielectric film ILD 1  is deposited on the silicon substrate  10 , the switching transistor ST, and the transistor Tr. The surface of the interlayer dielectric film ILD 1  is ground flat by using CMP (Chemical Mechanical Polishing). As a result, a structure shown in  FIG. 3  is obtained. The gate dielectric film, and both or either one of the gate electrode and the source and drain layers can be simultaneously formed in the capacitor region and the peripheral circuit region, or can be formed in individual processes. 
         [0033]    A contact hole communicating to the diffusion layers DL 1  and DL 2  is formed within the interlayer dielectric film ILD 1  by using lithography and RIE (Reactive Ion Etching). Further, metal or doped polysilicon is embedded into the contact hole, and the metal or the doped polysilicon is flattened using CMP. As a result, a contact plug CP 1  is formed, as shown in  FIG. 4 . The contact plug CP 1  in the capacitor region and the contact plug CP 1  in the peripheral circuit region can be formed simultaneously, or can be formed in individual processes. 
         [0034]    Next, as shown in  FIG. 4 , the lower electrode material BE, the ferroelectric material FE, and the upper electrode material TE are deposited on the interlayer dielectric film ILD 1  and the contact plug CP 1 . As described above, the lower electrode material BE includes a single-layer film such as Ti, TiN, TiAlN, Pt, Ir, IrO 2 , SRO, Ru, and RuO 2 , or includes a lamination film including at least two of them. The ferroelectric material FE includes PZT, SBT, or BLT, for example. The upper electrode material TE includes a single-layer film such as Pt, Ir, IrO 2 , SRO, Ru, and RuO 2 , or a lamination film of these. 
         [0035]    Next, a mask material (not shown) is deposited on the upper electrode material TE. The mask material includes a P-TEOS film, an O 3 -TEOS film, or an Al 2 O 3 . The mask material is processed into a pattern of a ferroelectric capacitor by using lithography or RIE. The upper electrode material TE, the ferroelectric material FE, and the bottom electrode material BE are etched by RIE, using the processed mask material as a mask. As a result, as shown in  FIG. 5 , the ferroelectric capacitor FC is formed on the contact plug CP 1 . The upper electrode material TE, the ferroelectric material FE, and the bottom electrode material BE after the processing are called an upper electrode TE, a ferroelectric FE, and a bottom electrode BE. 
         [0036]    Next, as shown in  FIG. 6 , a barrier film BM 1  is deposited on the side surface and the upper surface of the ferroelectric capacitor FC, and on the interlayer dielectric film ILD 1 . The barrier film BM 1  includes a single-layer film such as Al 2 O 3 , SiN, and TiO 2 , or a lamination film of two or more of these films. A film thickness of the barrier film BM 1  is T 1 . The interlayer dielectric film ILD 2  is deposited on a barrier film BM 1 , and the interlayer dielectric film ILD 2  is flattened using CMP. 
         [0037]    Next, as shown in  FIG. 7 , the interlayer dielectric film ILD 2  around the ferroelectric capacitor FC and the interlayer dielectric film ILD 2  in the peripheral circuit regions are etched by using lithography and RIE. In this case, the barrier film BM 1  is used as an etching stopper. Accordingly, a trench  50  is formed around the ferroelectric capacitor FC, while leaving the barrier film BM 1  as it is. The trench  50  is formed to surround the ferroelectric capacitor FC on the plane surface as observed from above the front surface of the silicon substrate  10 . The trench  50  is provided to form a space between the ferroelectric capacitor FC and the interlayer dielectric film ILD 2 . 
         [0038]    Next, as shown in  FIG. 8 , the barrier film BM 2  is filled into the trench  50 . In this case, the barrier film BM 2  is also deposited on the barrier film BM 1  of the peripheral circuit region. The barrier film BM 2  includes Al 2 O 3 , SiN, and TiO 2 , for example. While the barrier film BM 2  is sufficiently filled into the trench  50 , the film thickness of the barrier film BM 2  deposited into the peripheral circuit region is preferably sufficiently small. This is because when the barrier film BM 2  is thin in the peripheral circuit region, the contact (the contact plug CP 2 ) connected to the contact plug CP 1  can be formed easily. Further, in this step, the barrier film BM 2  is simultaneously deposited on the side surface of the barrier film BM 1  and on the side surface of the interlayer dielectric film ILD 2 . Accordingly, the barrier film BM 2  which is a single continuous layer is deposited in the trench  50  so as to be folded down between a side surface of the barrier film BM 1  and a side surface of the interlayer dielectric film ILD 2 . As a result, a seam  101  is formed in the barrier film BM 2 . 
         [0039]    An embedded insulation film  60  is deposited onto the barrier film BM 2  and the interlayer dielectric film ILD 2 . The embedded insulation film  60  includes a P-TEOS film, an O 3 -TEOS film, an SOG, or a Low-k film (SiOF, SiOC), for example. The embedded insulation film  60  is flattened using CMP. At the same time, the barrier film BM 2  is also flattened. As a result, a structure as shown in  FIG. 8  is obtained. The barrier films BM 1 , BM 2  formed on the side surface of the ferroelectric capacitor FC have the thickness T 2 , and this T 2  is larger than the thickness T 1 . 
         [0040]    Next, a contact hole is formed on the upper electrode TE of the ferroelectric capacitor FC and on a part of the contact plug CP 1  by using lithography and RIE. A metal material is embedded into a contact hole, and this metal material is flattened using CMP. In this CMP process, the metal material is ground until when the upper surface of the interlayer dielectric film ILD 2  and the embedded material  60  is exposed. As a result, as shown in  FIG. 9 , the contact plugs CP 2  and CP 3  are formed. A metal material of the contact plugs CP 2  and CP 3  includes any one of W, Al, TiN, Cu, Ti, Ta, and TaN, for example. The metal material can be deposited by MOCVD, sputtering, plating, or sputter-reflow. 
         [0041]    Next, a wiring material is deposited onto the contact plugs CP 2  and CP 3 , the interlayer dielectric film ILD 2 , and the embedded insulation film  60 , and this wiring material is processed in a desired wiring pattern. Accordingly, as shown in  FIG. 9 , the wiring  90  is formed. The wiring material is a metal material including any one of W, Al, TiN, Cu, Ti, Ta, and TaN, for example. 
         [0042]    According to the present embodiment, not only the barrier film BM 1  but also the barrier film BM 2  is also provided on the side surface of the ferroelectric capacitor FC. Therefore, the film thickness T 2  of the barrier films BM 1  and BM 2  on the side surface of the ferroelectric capacitor FC is larger than the film thickness T 1  of the barrier film BM 1  on the upper surface of the interlayer dielectric film ILD 1 . Accordingly, in the tungsten deposition process of forming the contact plugs CP 1 , CP 2 , and CP 3 , the barrier films BM 1  and BM 2  on the side surface of the ferroelectric capacitor FC can sufficiently suppress the hydrogen from entering the side surface of the ferroelectric capacitor FC. 
         [0043]    In the present embodiment, the thickness T 1  of the barrier film BM 1  on the upper surface of the interlayer dielectric film ILD 1  is smaller than the thickness T 2 . Accordingly, in the process of forming the contact hole, the etching amount of the barrier film BM 1  can be small. Because the etching of the barrier film takes a long time, a small etching amount of the barrier film can shorten the etching process. 
         [0044]    Conventionally, the barrier film BM 1  has a large thickness to form the barrier film in a large thickness on the side surface of the ferroelectric capacitor. In this case, to deposit the barrier film of the desired thickness T 2  on the side surface of the ferroelectric capacitor, it has been necessary to deposit a barrier film having a larger thickness than T 2  on the upper surface of the interlayer dielectric film ILD 1 . This not only consumes a large amount of the barrier film material but also requires a long time in the etching process to form the contact hole. 
         [0045]    In the present embodiment, the barrier film BM 1  is deposited on the side surface of the ferroelectric capacitor FC, and further, the barrier film BM 2  is filled into the trench  50  formed around the ferroelectric capacitor FC. Accordingly, the barrier films BM 1  and BM 2  having a sufficient thickness can be formed on the side surface of the ferroelectric capacitor FC to suppress the entering of hydrogen, while depositing the barrier film BM 1  in a sufficiently small thickness on the interlayer dielectric film ILD 1 . The ferroelectric memory and the manufacturing method thereof according to the present embodiment do not have the above conventional inconveniences. 
         [0046]    According to the present embodiment, the barrier film BM 2  is formed to fill in the trench  50  formed around the ferroelectric capacitor FC. In this case, the barrier film BM 2  is deposited on both the side surface of the trench  50  (the side surface of the interlayer dielectric film ILD 2 ) and the side surface of the ferroelectric capacitor FC. Therefore, the trench  50  is filled in fast with the barrier film BM 2 . When a barrier film is deposited on the side surface of the ferroelectric capacitor FC in a state that the trench  50  and the interlayer dielectric film ILD 2  are not provided, for example, the barrier film BM 2  is deposited on only the side surface of the ferroelectric capacitor FC. On the other hand, in the present embodiment, the barrier film BM 2  is deposited on both the side surface of the trench  50  (the side surface of the interlayer dielectric film ILD 2 ) and the side surface of the ferroelectric capacitor FC. Therefore, in the present embodiment, the barrier film BM 2  can be formed fast (or in a large thickness) on the side surface of the ferroelectric capacitor FC. For example, in a case that the barrier film BM 2  consisting of an ALD-Al 2 O 3  layer having 60 nm thickness is deposited only on a side surface of the ferroelectric capacitor FC, it takes 30 minutes. In contrast, in the present embodiment, it is sufficient that the ALD-Al 2 O 3  layer is deposited 30 nm thickness to obtain the ALD-Al 2 O 3  layer having 60 nm thickness. Therefore, it takes approximately 15 minutes. 
         [0047]    Thus, because the barrier film BM 2  is simultaneously deposited on the side surface of the barrier film BM 1  and the side surface of the interlayer dielectric film ILD 2 , the thickness of the barrier film BM 2  in the present invention can be around half of that of the conventional technique. 
         [0048]    In the present embodiment, a single layer of the barrier film BM 2  is formed so as to be folded down into a trench  50 , and the seam  101  is formed inside of the barrier film BM 2 . Therefore, it is possible to reduce a probability that a defect in the barrier film BM 2  extends and reaches to the ferroelectric capacitor FC. For example, even if a pin-hole is generated at an interface between the barrier film BM 2  and the interlayer dielectric film ILD 2 , the pin-hole can be stopped at the seam  101 . 
       Second Embodiment 
       [0049]      FIG. 10  is a cross-sectional view of a ferroelectric memory according to a second embodiment of the present invention. In the second embodiment, the ferroelectric memory further includes a bottom barrier film BM 3  within the interlayer dielectric film ILD 1  beneath the ferroelectric capacitor FC. Further, in the second embodiment, the barrier film BM 2  extends to below the ferroelectric capacitor FC along the side surface of the ferroelectric capacitor FC, and reaches the barrier film BM 3  piercing through a part of the barrier film BM 1  and the interlayer dielectric film ILD 1 . Other configurations according to the second embodiment can be similar to those according to the first embodiment. 
         [0050]    The barrier film BM 3  includes a single-layer film of Al 2 O 3 , SiN, and TiO 2 , or a lamination film of two or more layers of these films. The barrier film BM 3  also has a characteristic of suppressing percolation of hydrogen, and interrupting hydrogen. When the barrier film BM 3  is provided beneath the ferroelectric capacitor FC, hydrogen is suppressed from entering the lower part of the ferroelectric capacitor FC. The barrier film BM 2  is connected to the barrier film BM around the ferroelectric capacitor FC. Accordingly, the ferroelectric capacitor FC is completely covered by the barrier films BM 1  to BM 3 , except the contact portion between the contact plugs CP 1  and CP 3 . Therefore, in the second embodiment, hydrogen can be more sufficiently suppressed from entering the ferroelectric capacitor FC. 
         [0051]    A method of manufacturing the ferroelectric memory according to the second embodiment is explained with reference to  FIG. 11  to  FIG. 15 . First, the structure as shown in  FIG. 3  is formed, like in the first embodiment. Next, the barrier film BM 3  is deposited, and the interlayer dielectric film ILD 1  is deposited on the barrier film BM 3 , as shown in  FIG. 11 . A contact hole communicating to the diffusion layers DL 1  and DL 2  is formed within the interlayer dielectric film ILD 1  and the barrier film BM 3  by using lithography and RIE. Further, metal or doped polysilicon is embedded into the contact hole, and the metal or the doped polysilicon is flattened using CMP. As a result, the contact plug CP 1  is formed as shown in  FIG. 11 . The contact plug CP 1  in the capacitor region and the contact plug CP 1  in the peripheral circuit region can be formed simultaneously, or can be formed in separate processes. 
         [0052]    Next, the ferroelectric capacitor FC is formed on the contact plug CP 1 , like in the first embodiment. The barrier film BM 1  is deposited on the side surface and the upper surface of the ferroelectric capacitor FC, and on the interlayer dielectric film ILD 1 . The interlayer dielectric film ILD 2  is deposited on the barrier film BM 1 , and the interlayer dielectric film ILD 2  is flattened using CMP. As a result, a structure as shown in  FIG. 12  is obtained. 
         [0053]    The interlayer dielectric film ILD 2  around the ferroelectric capacitor FC and the interlayer dielectric film ILD 2  in the peripheral circuit region are etched by using lithography and RIE, as shown in  FIG. 7 . The barrier film BM 1  exposed to the bottom of the trench is etched. The interlayer dielectric film ILD 1  exposed by etching the barrier film BM 1  is also etched. As a result, a trench  51  reaching the barrier film BM 3  is formed around the ferroelectric capacitor FC, as shown in  FIG. 13 . In this case, the upper parts of the barrier film BM 1  and the upper parts of the interlayer dielectric film ILD 1  in the peripheral circuit region are also removed in self-alignment. 
         [0054]    Next, the barrier film BM 2  is filled into the trench  51 , as shown in  FIG. 14 . In this case, the barrier film BM 2  is also deposited on the barrier film BM 1  in the peripheral circuit region. While sufficiently filling the barrier film BM 2  into the trench  51 , it is preferable that the barrier film BM 2  deposited in the peripheral circuit region is as thin as possible. This is because the contact (the contact plug CP 2 ) connected to the contact plug CP 1  is formed easily in the peripheral circuit region. Further, in this step, the barrier film BM 2  is simultaneously deposited on the side surface of the barrier film BM 1  and on the side surface of the interlayer dielectric film ILD 2 . Accordingly, the barrier film BM 2  which is a single continuous layer is deposited in the trench  50  so as to be folded down between a side surface of the barrier film BM 1  and a side surface of the interlayer dielectric film ILD 2 . As a result, a seam  101  is formed in the barrier film BM 2 . 
         [0055]    Thereafter, the embedded insulation film  60  is deposited onto the barrier film BM 2  and the interlayer dielectric film ILD 2 , like in the first embodiment. The embedded insulation film  60  is flattened using CMP. At the same time, the barrier film BM 2  is also flattened. The contact plugs CP 2  and CP 3 , and the wiring  90  are formed. As a result, a structure as shown in  FIG. 15  is obtained. 
         [0056]    The ferroelectric capacitor FC is completely covered by the barrier films BM 1  to BM 3 , except the contact portion between the contact plugs CP 1  and CP 3 . Therefore, in the second embodiment, hydrogen can be more sufficiently suppressed from entering the ferroelectric capacitor FC. In the second embodiment, effects similar to those in the first embodiment can be obtained. 
       Third Embodiment 
       [0057]      FIG. 16  is a cross-sectional view of a ferroelectric memory according to a third embodiment of the present invention.  FIG. 16  corresponds to a cross section along a line  16 - 16  in  FIG. 1 . That is,  FIG. 16  shows a cross section in a second direction (a word line direction) perpendicular to a bit line direction.  FIG. 17  is a top plan view of a layer along a line  17 - 17  in  FIG. 16 .  FIG. 17  is simplified to make clear a layout relationship among the trench  50 , the ferroelectric capacitor FC, and the contact plug CP 2 . 
         [0058]    In the third embodiment, the barrier film BM 2  is filled into between the side surfaces of plural adjacent ferroelectric capacitors FC arranged in the word line direction. 
         [0059]    The barrier film BM 2  is a single continuous layer folded down into a trench  50  between two ferroelectric capacitors FC adjacent to each other. The barrier film BM 2  is provided on side surfaces of the two ferroelectric capacitors FC via the barrier film BM 1 . The barrier film BM 2  includes a seam  101  extending along with a side surface of the ferroelectric capacitors FC and a side surface of the barrier film BM 1 . The seam  101  is provided at an intermediate portion between the two ferroelectric capacitors FC. 
         [0060]    The barrier film BM 2  extends to the word line direction corresponding to each row of the plural ferroelectric capacitors FC arranged in the word line direction, and is isolated between the ferroelectric capacitors FC adjacent in the bit line direction. While the contact plug CP 2  is present between the ferroelectric capacitors FC adjacent in the bit line direction, the barrier film BM 2  is not provided around the contact plug CP 2 . Other configurations of the third embodiment can be similar to those of the first embodiment. 
         [0061]    In a method of manufacturing a ferroelectric memory according to the third embodiment, in the forming process of trench  50 , the trench  50  extending to the word line direction is formed to correspond to each row of plural ferroelectric capacitors FC arranged in the word line direction. More specifically, in the cross section along the line  16 - 16  in  FIG. 7 , the trench  50  is formed in a line shape to include the whole rows of ferroelectric capacitors on the plane surface as shown in  FIG. 17 . Other processes of the manufacturing method in the third embodiment can be similar to the processes of the manufacturing method in the first embodiment. As a result, the ferroelectric memory according to the third embodiment is completed. 
         [0062]    The barrier film BM 2  is simultaneously deposited on the barrier film BM 1  between the two ferroelectric capacitors FC adjacent to each other. Accordingly, the barrier film BM 2  which is a single continuous layer is deposited in the trench  50  so as to be folded down between the side surfaces of the two ferroelectric capacitors FC. As a result, a seam  101  is formed in the barrier film BM 2 . 
         [0063]    In the third embodiment, the trench  50  is not provided for each ferroelectric capacitor FC, but is provided in a line shape to include a whole row of ferroelectric capacitors including plural ferroelectric capacitors. Therefore, the trench  50  can be formed relatively easily. Further, effects similar to those in the first embodiment can be obtained in the third embodiment. 
       Fourth Embodiment 
       [0064]      FIG. 18  is a cross-sectional view of a ferroelectric memory according to a fourth embodiment of the present invention. The fourth embodiment is different from the first embodiment in that the barrier film BM 2  has a lamination structure of an insulation layer IL and the metal layer ML. Other configurations of the fourth embodiment can be similar to those of the first embodiment. 
         [0065]    In the fourth embodiment, the insulation layer IL is provided on the side surface of the ferroelectric capacitor FC via the barrier film BM 1 , and the metal layer ML is provided at the outside of the insulation layer IL. The insulation layer IL includes Al 2 O 3 , SiN, or TiO 2 , for example. The metal layer ML includes any one of Al, Ti, TiN, and TiAlN. Because the metal layer ML is provided on the side surface of the insulation layer IL, diffusion of hydrogen to the ferroelectric capacitor FC can be further suppressed. 
       Fifth Embodiment 
       [0066]      FIG. 19  is a cross-sectional view of a ferroelectric memory according to a fifth embodiment of the present invention. In the fifth embodiment, the contact plug CP 2  provided between the side surfaces of the ferroelectric capacitors FC adjacent in the bit line direction is formed in self-alignment contact using the barrier film BM 2  as a mask. Therefore, the barrier film BM 2  is filled in around the second contact plug between the side surfaces of the ferroelectric capacitors FC adjacent in the bit line direction. Other configurations according to the fifth embodiment can be similar to those according to the first embodiment. 
         [0067]    When the contact plug CP 2  is formed in self-alignment contact, an interval G 1  between the ferroelectric capacitors FC adjacent in the bit line direction can be decreased. Accordingly, the size of the memory cell can be more decreased. 
         [0068]    As shown in  FIG. 7 , at the time of forming the trench  50 , the interlayer dielectric film ILD 2  can be formed in a forward tapered shape. Accordingly, when the barrier film BM 2  is embedded into the trench  50 , the barrier film BM 2  can be formed in an inverse tapered shape. That the barrier film BM 2  is in the inverse tapered shape is preferable as the mask of the contact plug CP 2 . If the mask is in the forward tapered shape, the thickness of the mask at the upper part of the ferroelectric capacitor is smaller than the thickness at the lower part of the ferroelectric capacitor. Therefore, when the contact hole is formed in self-alignment, the upper part of the mask is etched more than the lower part of the mask. As a result, there is a risk that the contact plug CP 2  is short-circuited with the ferroelectric capacitor FC. In the fifth embodiment, the barrier film BM 2  is in the inversely tapered shape. That is, the thickness of the mask at the upper part of the side surface of the ferroelectric capacitor is larger than the thickness of the mask at the lower part of the side surface of the ferroelectric capacitor. As a result, in the fifth embodiment, even when the contact plug CP 2  is formed in self-alignment contact, there is small risk that the contact plug CP 2  is short-circuited with the ferroelectric capacitor FC. 
       Sixth Embodiment 
       [0069]      FIG. 20  is a cross-sectional view of a ferroelectric memory according to a sixth embodiment of the present invention. In the sixth embodiment, on the plane surface as observed from above the front surface of the silicon substrate  10 , an upper barrier film BM 4  surrounds the contact plug CP 3  connected to the upper electrode TE, within the interlayer dielectric film ILD 2  between the wiring  90  and the upper electrode TE, as shown in  FIG. 21A  or  FIG. 21B . A number of the contact plug CP 3  that the upper barrier film BM 4  surrounds can be one as shown in  FIG. 21A , or can be plural as shown in  FIG. 21B . Other configurations of the sixth embodiment can be similar to the configurations of the first embodiment. The barrier film BM 4  includes a single-layer film of Al 2 O 3 , SiN, and TiO 2 , or a lamination film of two or more layers of these materials. 
         [0070]    When the upper barrier film BM 4  is not present, hydrogen entering the region not provided with the wiring  90  is diffused to the ferroelectric capacitor FC via a boundary between the contact plug CP 3  and the barrier film BM 1 . However, according to the sixth embodiment, because the upper barrier film BM 4  encircles the contact plug CP 3 , the hydrogen entering the region not provided with the wiring  90  is not diffused to the ferroelectric capacitor FC via the boundary between the contact plug CP 3  and the barrier film BM 1 . To sufficiently exhibit this effect, as shown in  FIG. 21A  and  FIG. 21B , on the plane surface as observed from above the front surface of the silicon substrate  10 , the region R 1  surrounded by the upper barrier film BM 4  is covered with the wiring  90 . It is preferable that the upper surface of the interlayer dielectric film ILD 2  is not exposed within this region R 1 . The upper barrier film BM 4  can be formed before or after the process of forming the contact plug CP 3 . 
       Seventh Embodiment 
       [0071]      FIG. 22  is a cross-sectional view of a ferroelectric memory according to a seventh embodiment of the present invention. In the seventh embodiment, on the plane surface as observed from above the front surface of the silicon substrate  10 , an upper barrier film BM 5  surrounds the contact plug CP 3  connected to the upper electrode TE, within the interlayer dielectric film ILD 2 , like the upper barrier film BM 4  in the sixth embodiment. A number of the contact plug CP 3  that the upper barrier film BM 5  surrounds can be one as shown in  FIG. 21A , or can be plural as shown in  FIG. 21B . Other configurations of the seventh embodiment can be similar to those of the first embodiment. The upper barrier film BM 5  includes a single-layer film of Al 2 O 3 , SiN, and TiO 2 , or a lamination film of two or more layers of these materials. 
         [0072]    According to the seventh embodiment, because the upper barrier film BM 5  surrounds the contact plug CP 3 , effects similar to those of the sixth embodiment can be obtained. To sufficiently exhibit these effects, on the plane surface as observed from above the front surface of the silicon substrate  10 , the region surrounded by the barrier film BM 5  is covered by the wiring  90 . In this region, the upper surface of the interlayer dielectric film ILD 2  is preferably not exposed. 
         [0073]      FIG. 23  is a cross-sectional view showing a contact portion of the peripheral circuit region of the ferroelectric memory according to the seventh embodiment. In the seventh embodiment, the upper barrier film BM 5  also surrounds the periphery of the contact portion of the peripheral circuit region. Accordingly, hydrogen can be suppressed from entering the contact region of the peripheral circuit. 
         [0074]    A manufacturing method according to the seventh embodiment is explained. The structure shown in  FIG. 8  in the first embodiment is obtained. Thereafter, the interlayer dielectric film is deposited on the barrier film BM 2  and the interlayer dielectric film ILD 2 . Accordingly, the interlayer dielectric film ILD 2  is made thicker. Next, the interlayer dielectric film ILD 2  in the formation region of the upper barrier film BM 5 , and the barrier film BM 2  are removed, thereby forming a trench  52 . As a result, a structure as shown in  FIG. 24  is obtained. 
         [0075]    Next, as shown in  FIG. 25 , the upper barrier film BM 5  is deposited thinly, and thereafter, the interlayer dielectric film ILD 3  is deposited. The interlayer dielectric film ILD 3  is flattened using CMP. Next, a contact hole CH is formed by etching the barrier film BM 5  and the barrier film BM 1 . As a result, a structure as shown in  FIG. 25  is obtained. A metal material is filled into the control hole to form the contact plug CP 3 . Thereafter, the ferroelectric memory as shown in  FIG. 22  and  FIG. 23  is completed, through a process similar to that of the first embodiment. 
         [0076]    According to the seventh embodiment, the contact hole can be formed easily by forming the barrier film BM 1  and the upper barrier film BM 5  thin. Further, effects similar to those in the first embodiment can be obtained in the seventh embodiment. 
         [0077]    The second embodiment can be combined with any one of the third to the seventh embodiment. In this case, the third to the seventh embodiments can also obtain the effects of the second embodiment. The barrier film BM 2  in the fourth to the seventh embodiments can be filled into between the ferroelectric capacitors FC adjacent in the word line direction, like the barrier film BM 2  in the third embodiment. Accordingly, the fourth to seventh embodiments can also obtain the effects of the third embodiment.