Abstract:
An apparatus and method for displaying a television signal on a computer monitor first receives a selected first field data block of the television signal for display by the monitor. The television signal preferably includes a stream of first field data blocks and second field data blocks that are intended for display by respective first and second sets of lines on the computer monitor. After receipt of the first field data block, an immediately preceding second field data block is faded to produce a faded second block. The faded second block then is displayed on the second set of lines of the monitor, and the first field data block is displayed on the first set of lines of the monitor.

Description:
PRIORITY 
     This application claims priority from provisional United States patent application identified as serial No. 60/093,182, filed Jul. 17, 1998, entitled “SYSTEM FOR DISPLAYING A TELEVISION SIGNAL ON A COMPUTER MONITOR”, the disclosure of which is incorporated herein, in its entirety, by reference. 
    
    
     FIELD OF THE INVENTION 
     The invention generally relates to computer systems and, more particularly, the invention relates to displaying television signals on computer display devices. 
     BACKGROUND OF THE INVENTION 
     The National Television Standards Committee sets the standards for television signal transmission (the “NTSC standard”) in the United States. In particular, the NTSC standard requires that a television signal include sixty interlaced half-frames for each second of a motion picture displayed by a television. To that end, a television signal in the United States includes a sequential series of alternating “odd” half-frames and “even” half-frames that are to be displayed on respective odd and even lines of a television display. Upon receipt of a television signal in which the first half frame is odd, for example, a television draws the entire first odd half-frame, followed by the entire first even half-frame, followed by the entire second odd half-frame, etc . . . 
     As is known in the art, a television includes a phosphor element on a display face of a cathode ray tube, and an electron gun for energizing the phosphor as specified by a received television signal. The energy emitted by the energized phosphor element produces a visible display of the television signal. The total time that elapses between the time that the phosphor is first energized, and the time that the energy in the phosphor dissipates (known as “phosphor persistence”) is the entire time that a half-frame is viewable on a television display face. Typically, a half-frame is drawn while an immediately preceding half-frame is fading, but still visible. Together, the faded preceding half-frame and the half-frame being drawn produce a motion picture effect upon the display face of the cathode ray tube. 
     Unlike televisions, computer monitors draw entire frames instead of a series of half-frames. Specifically, a computer monitor is configured to consecutively draw each line on a monitor display face and thus, no lines on a computer monitor are skipped. Moreover, phosphor elements in a computer monitor typically have a much lower phosphor persistence than those in a television, thus enabling more frames to be displayed by a monitor each second. For example, many known types of computer monitors can draw sixty full frames each second while a television can only draw sixty half-frames each second. Accordingly, use of a television signal for display by a computer monitor typically does not produce the quality that a television signal produces on a television since half frames fade too rapidly on a computer monitor. 
     SUMMARY OF THE INVENTION 
     In accordance with one aspect of the invention, an apparatus and method for displaying a television signal on a computer monitor first receives a selected first field data block of the television signal for display by the monitor. The television signal preferably includes a stream of first field data blocks and second field data blocks that are intended for display by respective first and second sets of lines on the computer monitor. After receipt of the first field data block, an immediately preceding second field data block is faded to produce a faded second block. The faded second block then is displayed on the second set of lines of the monitor, and the first field data block is displayed on the first set of lines of the monitor. 
     In accordance with another aspect of the invention, the first field data block has an immediately following second field data block that is displayed on the second set of lines after the faded second block is displayed by such lines. The first field data block also may be faded to produce a faded first data block that is displayed on the first set of lines after the first field data block is displayed by such lines. The faded first data block preferably is displayed at the same time as the immediately following second field data block. 
     In preferred embodiments, the first field data blocks include even field line data and the second field blocks include odd field line data. The first set of lines thus are even lines and the second set of lines thus are odd lines. In other embodiments, the first field data blocks include odd field line data and the second field blocks include even field line data. The first set of lines thus are odd lines and the second set of lines thus are even lines. 
     In yet other embodiments of the invention, the television signal is in a NTSC (National Television Standards Committee) format or in a PAL (phase alternating line) format. In some embodiments, the immediately preceding data block is faded by first retrieving such data block from a front buffer in a double buffer frame buffer, and then applying alpha blending to such data block to produce the faded second block. Once produced, the faded block is copied into a back buffer of the frame buffer. 
     In accordance with another aspect of the invention, and apparatus and method of processing a television signal for simulating a television image on a computer monitor selectively fades data blocks. The television signal includes a stream of alternating first and second data blocks. More particularly, a first data block and second data block are received at an input. The first data block immediately precedes the second data block in the television signal. The first data block then is faded to produce a faded first data block. The faded first data block then is combined with the second data block to produce a frame. The frame then is forwarded to the computer monitor. 
     Alternative embodiments of the invention are implemented as a computer program product having a computer usable medium with computer readable program code thereon. The computer readable code may be read and utilized by the computer system in accordance with conventional processes. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects and advantages of the invention will be appreciated more fully from the following further description thereof with reference to the accompanying drawings wherein: 
     FIG. 1 schematically shows a portion of an exemplary computer system on which preferred embodiments of the invention may be implemented. 
     FIG. 2 shows a preferred graphics accelerator that may be utilized in accord with preferred embodiments of the invention. 
     FIG. 3 shows a preferred process for displaying a television signal on a computer display device. 
     FIG. 4 schematically shows the a preferred embodiment of the invention in which a resolver shown in FIG. 2 is configured to execute the process shown in FIG.  3 . 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 1 shows a portion of an exemplary computer system  100  on which a preferred apparatus and method for displaying a television signal (i.e., a video signal) may be implemented. More particularly, the computer system  100  includes a video input device  102  for receiving a video signal, a host processor  104  (i.e., a central processing unit) for executing application level programs and system functions, a graphics accelerator  106  for processing the video signal in accord with preferred embodiments of the invention (see FIG.  3 ), and a bus coupling all of the other noted elements of the system  100 . A display device  108  is coupled to the graphics accelerator  106  for displaying the video signal. The graphics accelerator  106  preferably utilizes any well known graphics processing application program interface such as, for example, the OPENGL™ application program interface (available from Silicon Graphics, Inc. of Mountain View, Calif.) to display the video signal and other graphical items. 
     The video signal may be any known video format such as, for example, those defined by the National Television Standards Committee (“NTSC format”), or the Phase Alternating Line format (“PAL format”). Of course, preferred embodiments are not limited by those formats and may be applied to other interlaced video formats. As known by those skilled in the art, such video signals typically include a data stream having a sequential series of alternating data blocks. Specifically, every other data block is an identical type of data block. For example, the data blocks in the data stream may include alternating odd line frame data and even line frame data. Accordingly, each even line data block has an immediately preceding and immediately succeeding odd line frame data block. In a similar manner, each odd line data block has an immediately preceding and immediately succeeding even line frame data block. A given data block described herein is considered to be immediately preceding or succeeding another given data block when no other data blocks are between such given data blocks. 
     FIG. 2 shows several elements of the graphics accelerator  106  shown in FIG.  1 . In preferred embodiments, the graphics accelerator  106  includes a double buffered frame buffer  200  (i.e., having a back buffer  200 A and a front buffer  200 B, FIG. 4) for displaying the video signal in accord with the OPENGL™ interface. Among other things, the graphics accelerator  106  also preferably includes a geometry accelerator  202  for performing geometry operations that commonly are executed in graphics processing, a rasterizer  204  for rasterizing pixels on the display device  108 , and a resolver  206  for storing data in the frame buffer  200  and transmitting data from the frame buffer  200  to the display device  108 . The graphics accelerator  106  preferably is adapted to process both two dimensional and three dimensional graphical data. 
     In preferred embodiments, graphics processing is executed by a plurality of processors (e.g., rasterizers, geometry accelerators, etc . . . ) that together comprise the graphics accelerator  106 . For additional information relating to preferred embodiments of the graphics accelerator  106 , see, for example, copending patent application entitled “MULTI-PROCESSOR GRAPHICS ACCELERATOR”, filed on even date herewith and naming Steven J. Heinrich, Stewart G. Carlton, Mark A. Mosley, Matthew E. Buckelew, Clifford A. Whitmore, Dale L. Kirkland, and James L. Deming as inventors, the disclosure of which is incorporated herein, in its entirety, by reference. For additional information relating to preferred embodiments of the graphics accelerator  106 , see, for example, “WIDE INSTRUCTION WORD GRAPHICS PROCESSOR,” filed on even date herewith and naming Vernon Brethour, Dale Kirkland, William Lazenby, and Gary Shelton as inventors, the disclosure of which is incorporated herein, in its entirety, by reference. 
     FIG. 3 shows a preferred process for displaying a television signal on the computer display device  108 . The process is described in terms of a video signal having even and odd half-frames. As is known in the art, an even half-frame includes each of the even lines in a frame, while an odd half-frame includes each of the odd lines in a frame. The NTSC format, for example, defines a composite signal with a refresh rate of sixty half-frames per second (i.e., thirty odd half-frames and thirty even half-frames). 
     The process begins at step  300  in which the system  100  receives a input video signal having alternating odd and even half-frames. In accord with conventional processes, the first half-frame is processed by the graphics accelerator  106 , stored in the back buffer  200 A, and then swapped to the front buffer  200 B for display on the display device  108  (step  302 ). The process continues to step  304  in which the half-frame in the front buffer  200 B (i.e., the data representing such half-frame) is faded by means of conventional alpha fading processes. 
     To that end, the resolver  206  preferably includes a multipler (FIG. 4, discussed below) that fades a given half-frame by applying an alpha fading value, as defined by OPENGL™, to the given half-frame. This fading process produces a faded half-frame. In preferred embodiments, the faded half-frame is faded by a percentage that is comparable to the amount of fading that occurs between half-frames on a conventional television. More particularly, the approximate decay of a phosphor element in a television is modeled to determine the alpha value. To date, no experimental alpha values representing this decay have been determined. It is expected that alpha values of between about 0.2 and 0.8 should suffice. In preferred embodiments, the alpha fade value is configurable by a programmer or user of the graphics accelerator  106 . For example, the alpha value may range from zero to one, where a value of zero completely fades the given half frame (i.e., it causes the given half frame to be transparent), and a value of one does not fade the given half frame at all. Preferred implementations divide this alpha value range into 256 different values for additional granularity. 
     As it is produced, the faded half frame is written to the back buffer  200 A (step  306 ). Once the complete faded half frame is in the back buffer  200 A, the process then continues to step  308  in which the next succeeding half-frame in the video signal also is stored in the back buffer  200 A (the “unfaded half-frame”). Since the faded half-frame and unfaded half-frame are complimentary frames (i.e., the unfaded half-frame has odd lines only while the faded half-frame has even lines only, or the unfaded half-frame has even lines only while the faded half-frame has odd lines only), each of the lines of the display device  108  can be utilized upon a subsequent buffer swap. In some embodiments, the faded half frame and unfaded half frame are written to the back buffer  200 A substantially simultaneously, while in other embodiments, they are serially written to the back buffer  200 A. 
     The data in the back buffer  200 A (i.e., the faded and unfaded half frames) then is moved to the front buffer  200 B in step  310 , thus causing the faded half-frame and unfaded half-frame to be displayed simultaneously on the display device  108 . This data transfer may be executed by a conventional buffer swap. It then is determined at step  312  if the end of the video signal has been reached. If the end of the signal has been reached, then the process ends. If the video signal has additional half-frames, however, then the process loops back to step  304  in which the unfaded half-frame in the front buffer  200 B is faded. As can be deduced, the process continues by fading the unfaded half-frame to produce a new faded half-frame, and then displaying that new faded half-frame with the next succeeding half-frame in the video signal. 
     In preferred embodiments, the process shown in FIG. 3 is implemented substantially entirely in hardware. For example, the resolver  206  may be configured (i.e., “hardwired”) to execute the display process. In other embodiments, the process may be implemented in both hardware and software. 
     FIG. 4 schematically shows the a preferred embodiment of the invention in which the resolver  206  is configured to execute the process shown in FIG.  3 . Specifically, the resolver  206  includes an input  400  for receiving data from the rasterizer  204 , and alpha multiplier  402  for executing the fade operations of step  304  (above), and an output  404  to the back buffer  200 A of the frame buffer  200 . The alpha multiplier  402  has an input  406  coupled with the front buffer  200 B of the frame buffer  200  for receiving frame data from the front buffer  200 B, and an output  408  coupled to the resolver output  404 . The resolver output  404  correspondingly is coupled with the back buffer  200 A to forward the faded half frame to the back buffer  200 A. 
     Accordingly, in conformance with FIG. 3, new frame data is written directly to the back buffer  200 A, while frame data in the front buffer  200 B is faded by the alpha multiplier  402  prior to being written to the back buffer  200 A. As noted above, the graphics accelerator  106  preferably includes a plurality of parallel geometry accelerators  202 , rasterizers  204 , and resolvers  206  that process data on a pixel by pixel basis. Details of this parallel configuration are disclosed in the above noted patent applications. 
     Alternative embodiments of the invention may be implemented as a computer program product for use with a computer system. Such implementation may include a series of computer instructions fixed either on a tangible medium, such as a computer readable media (e.g., a diskette, CD-ROM, ROM, or fixed disk), or transmittable to a computer system via a modem or other interface device, such as a communications adapter connected to a network over a medium. The medium may be either a tangible medium (e.g., optical or analog communications lines) or a medium implemented with wireless techniques (e.g., microwave, infrared or other transmission techniques). The series of computer instructions embodies all or part of the functionality previously described herein with respect to the system. Those skilled in the art should appreciate that such computer instructions can be written in a number of programming languages for use with many computer architectures or operating systems. Furthermore, such instructions may be stored in any memory device, such as semiconductor, magnetic, optical or other memory devices, and may be transmitted using any communications technology, such as optical, infrared, microwave, or other transmission technologies. It is expected that such a computer program product may be distributed as a removable media with accompanying printed or electronic documentation (e.g., shrink wrapped software), preloaded with a computer system (e.g., on system ROM or fixed disk), or distributed from a server or electronic bulletin board over the network (e.g., the Internet or World Wide Web). 
     Although various exemplary embodiments of the invention have been disclosed, it should be apparent to those skilled in the art that various changes and modifications can be made which will achieve some of the advantages of the invention without departing from the true scope of the invention. These and other obvious modifications are intended to be covered by the appended claims.