Abstract:
A mixer includes an input stage to convert an RF input signal to an output signal, and a mixer core to mix the output signal from the input stage with a local oscillator signal. The input stage may include an input cell having a first differential pair of cross-connected transistors, and a linearizer coupled to the input cell. The linearizer may include a second differential pair of transistors having first and second inputs coupled to the input terminals and first and second outputs coupled to the output terminals.

Description:
RELATED APPLICATION 
     This application claims benefit of U.S. Provisional Patent Application Ser. No. 61/299,321 entitled “Mixer with Linearized Input,” filed Jan. 28, 2010, which is incorporated by reference. 
    
    
     BACKGROUND 
     Mixers are specialized modulator circuits that multiply their input signals frequency-pair by frequency-pair, often producing very complex products in the process. A typical mixer includes an input stage, which converts a voltage input to a current mode signal, and a mixer core, which essentially commutates the polarity of the current mode signal in response to a local oscillator signal, although the commutation may not be completely binary. 
     An important characteristic of a mixer is its small-signal linearity which defined by the 1 dB gain compression and the 3rd order intercept. The input stage of a standard mixer may include a simple differential pair of transistors. The linear range of such an input stage, however, is typically quite small which limits the attainable dynamic range. One prior art technique for extending the linear input range involves the use of multi-tanh input cells which can typically handle larger input signals without significant distortion. See, e.g., U.S. Pat. No. 5,589,791. Another prior art technique for extending the linear input range of a mixer involves the use of a class-AB as shown in U.S. Pat. No. 5,826,182. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an embodiment of a mixer according to some inventive principles of this patent disclosure. 
         FIG. 2  illustrates an embodiment of an input stage according to some inventive principles of this patent disclosure. 
         FIGS. 3 and 4  illustrate some example curves illustrating the operation of the embodiment of  FIG. 2 . 
         FIG. 5  illustrates another embodiment of an input stage according to some inventive principles of this patent disclosure. 
         FIG. 6  illustrates an example implementation of a digitally adjustable capacitor network suitable for use with the embodiment of  FIG. 5 . 
         FIG. 7  illustrates an example implementation of a digitally adjustable resistor network suitable for use with the embodiment of  FIG. 5 . 
         FIG. 8  illustrates an embodiment of a technique for isolating the transistor switches shown in  FIGS. 6-7 . 
         FIG. 9  illustrates another embodiment of an input stage according to some inventive principles of this patent disclosure. 
         FIG. 10  illustrates another embodiment of an input stage according to some inventive principles of this patent disclosure. 
         FIG. 11  illustrates another embodiment of an input stage according to some inventive principles of this patent disclosure. 
         FIG. 12  illustrates a mixer core that may be suitable for use with the input stages described above according to some inventive principles of this patent disclosure. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  illustrates an embodiment of a mixer according to some inventive principles of this patent disclosure. The mixer of  FIG. 1  includes an input stage  10  that converts an input signal IN to a form that may be used by a mixer core  12 . The mixer core  12  mixes the output  10  from the input stage with a local oscillator signal LO to generate the final output signal OUT. The input stage  10  includes an input cell  14  that contributes to processing the input signal IN, and a linearizer  16  that provides a distortion cancellation effect. 
       FIG. 2  illustrates an embodiment of an input stage according to some inventive principles of this patent disclosure. The embodiment of  FIG. 2  is arranged in a voltage-to-current converter configuration and may be used, for example, to implement the input stage  10  of  FIG. 1 . 
     In the embodiment of  FIG. 2 , a differential input RFIP/N is received at nodes N 1  and N 2  and coupled to a differential output IOP/N at nodes N 3  and N 4  through impedances Z 1  and Z 2 . In this example, the impedances Z 1  and Z 2  include series RC networks R 1 C 1  and R 2 C 2 , respectively. A differential pair of transistors Q 1  and Q 2  form an input cell in which the bases of Q 1  and Q 2  are connected to input nodes N 1  and N 2 , respectively, while the collectors of Q 1  and Q 2  are cross-connected to nodes N 4  and N 3 , respectively. The emitters of Q 1  and Q 2  are connected to a common node COM through resistors R 3  and R 4 . The input impedance looking into nodes N 1  and N 2  is defined by R 1  and R 2 . For example, R 1  and R 2  may each be set to 25Ω to provide a 50Ω input impedance. 
     Transistors Q 3  and Q 4  are arranged as a linearizer to cancel third-order distortion terms from transistors Q 1  and Q 2 . The bases of Q 3  and Q 4  are connected to the bases of Q 1  and Q 2 , respectively, while the collectors of Q 3  and Q 4  are connected to output nodes N 3  and N 4 , respectively. The emitters of Q 3  and Q 4  are connected through two resistors with value R LIN1  to a node N 5 , which in turn is connected to the common node COM through another resistor R LIN2 . A capacitor C 3  is connected between the emitters of Q 3  and Q 4  to facilitate adjustment of the phase of the linearizer transconductance. 
     DC bias current may be established in the circuit of  FIG. 2 , for example, by applying a bias voltage to nodes N 1  and N 2  through suitable resistors. Capacitors C 1  and C 2  may provide isolation from the input voltage to the output voltage. Additional DC blocking capacitors may be used to isolate the input voltage from the source of the bias voltage. 
     The overall transconductance gm (output current/input voltage) of the input stage can be expressed as:
 
 gm=gm 1 −gm 4 +gm 2 −gm 3  (Eq. 1)
 
where gm 1 / 2 / 3 / 4  represent the degenerated transconductance of transistors Q 1 / 2 / 3 / 4 , respectively. The degeneration resistors with value RLIN 1  as well as bias current through RLIN 2  may be adjusted to optimize the magnitude of gm 3 / 4 , and ultimately improve the input third-order intercept point (IIP 3 ).
 
     Depending on the implementation details, the values of RLIN 1  and RLIN 2  may have various effects on the third-order intercept.  FIG. 3  illustrates some example curves showing the dependency of IIP 3  on RLIN 1  and RLIN 2  at a given frequency, which in this example is 550 MHz, and at a given bias current. In general, IIP 3  increases as RLIN 2  decreases, and IIP 3  also increases as RLIN 1  increases. However, as RLIN 2  continues to decrease, and the current through the linearizer transistors increases, the value of IIP 3  becomes less sensitive to the value of RLIN 1 . 
     In addition to adjusting the magnitude of the linearizer transconductance, the phase of Q 3  and Q 4  may also be optimized to obtain more complete cancellation of third-order distortion terms over a wide frequency range. This may be accomplished by adjusting the value of C 3  which is connected between the emitters of Q 3  and Q 4 .  FIG. 4  illustrates how IIP 3  can be optimized, e.g., maximized, for a given frequency range based on the value of C 3  at a given bias current. Depending on the implementation details, C 3  may provide greater improvement within certain frequency ranges. Capacitor C 3  may also be more effective with higher mixer core currents. 
     The cross-coupling of the input differential pair Q 1  and Q 2  may provide double the gain of a simple differential pair without cross-coupling. An increase in RFIP leads to a decrease in the negative output voltage V(ION) through Q 1 , while a decrease in RFIN also leads to a decrease in V(ION) through the input impedance. 
     Another potential advantage is that the mixer core current may be arranged to flow through the emitter degeneration resistors R 3  and R 4  for transistors Q 1  and Q 2 . This may reduce or eliminate current flow through the RF inputs, thereby allowing a wider selection of input balanced-unbalanced (balun) converters. 
       FIG. 5  illustrates another embodiment of an input stage according to some inventive principles of this patent disclosure. The embodiment of  FIG. 5  is similar to the embodiment of  FIG. 2 , but C 3 , RLIN 1  and RLIN 2  are replaced with variable components CDAC, RDAC 1  and RDAC 2 , respectively. This enables the magnitude of the linearizer transconductance and/or the phase to be adjusted for different operating frequencies and bias currents. These components may be made variable through any suitable technique. For example, in a monolithic implementation, these components may be connected via fuses to be blown or kept, and thus, adjustable by a user. Alternatively, they may be implemented as continuously or digitally adjustable components. 
       FIG. 6  illustrates an example implementation of a digitally adjustable capacitor network suitable for use as CDAC. Various combinations of the capacitors may be selected by driving the gates of the MOS transistors high or low. The capacitors in  FIG. 6  are shown with binary weighting for convenience of selecting values, but any other weighting may be used, and any number of bits may be used. 
       FIG. 7  illustrates an example implementation of a digitally adjustable resistor network suitable for use as RDAC 1  and/or RDAC 2 . Various combinations of the resistors may be selected by driving the gates of the MOS transistors high or low. The resistors in  FIG. 7  are shown with binary weighting for convenience of selecting values, but any other weighting may be used, and any number of bits may be used. 
       FIG. 8  illustrates an embodiment of a technique for isolating transistor switches such as those shown above in  FIGS. 6-7 . The isolation resistors R I  between the complementary select lines bsel/bselb serve to isolate the transistor switches from noise that may be present on select lines. 
       FIG. 9  illustrates another embodiment of an input stage according to some inventive principles of this patent disclosure. The embodiment of  FIG. 9  is similar to the embodiment of  FIG. 5 , but resistors RLIN 1  are now fixed components, and a variable resistor RDAC is coupled between the emitters of Q 3  and Q 4 . This may be beneficial for example, to retain the adjustability provided by RDAC 1  in  FIG. 5 , but in an inherently balanced configuration that eliminates any inaccuracies due to differences between the two different RDAC 1  components. 
       FIG. 10  illustrates another embodiment of an input stage according to some inventive principles of this patent disclosure. The embodiment of  FIG. 10  is similar to the embodiment of  FIG. 9 , but the fixed resistor RLIN 2  is replaced with an adjustable current source Ibias. 
       FIG. 11  illustrates another embodiment of an input stage according to some inventive principles of this patent disclosure. The embodiment of  FIG. 11  is similar to the embodiment of  FIG. 10 , but the variable components RDAC and CDAC are replaced with fixed components. 
     The various combinations of components in the embodiments described above may enable optimization of the input stage and/or mixer core depending on the specific application. For example, in some implementations, it may be beneficial to use a resistor rather than current source for Ibias because of better linearity and/or reduced noise from a current source transistor. In other implementations, it may be preferable to have the flexibility of a continuously variable current source. 
     Although the inventive principles relating to input stages are not limited to any particular mixer core,  FIG. 12  illustrates a mixer core that may be suitable for use with the input stages described above according to some inventive principles of this patent disclosure. In the embodiment of  FIG. 12 , any suitable components such as inductors L 1  and L 2  may be implemented as external components. 
     The embodiments described herein can be modified in arrangement and detail without departing from the inventive concepts. For example, some embodiments have been described and illustrated in the context of BJT transistors of specific polarities, but the same inventive principles may be realized in other embodiments with CMOS or J-FET transistors, with different polarities, etc. Thus, references to various elements and configurations of one type of transistor also encompasses the corresponding elements and configurations of other types of transistors, e.g., emitter-follower is understood to also refer to source-follower, emitter degeneration also refers to source degeneration, base is understood to also refer to gate, etc. Accordingly, such changes and modifications are considered to fall within the scope of the following claims.