Abstract:
The present invention relates to a method of reducing a clock speed of a host bus to extend battery life and its operating time when a battery is supplying electric energy for a portable computer. A bus clock controlling apparatus according to the present invention includes power mode detecting means detecting a current power mode, the power mode indicative of which power source supplies the portable computer with electric energy; and clock adjusting means adjusting frequency of an applied clock from a clock generator based on the detected power mode by said power mode detecting means, and applying the frequency-adjusted clock to one or more controlling devices. Due to this invention, an electric energy stored in a battery equipped in a portable computer is saved, as a result, the battery life is extended.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to an apparatus and a method of controlling clock frequency generation, and more particularly, to an apparatus and a method for a portable device.  
           [0003]    2. Background of the Related Art  
           [0004]    In general, a portable device such as a notebook computer can be supplied with its necessary electric energy either by a battery or an AC power line. However, because battery capacity is limited, a notebook cannot be used for more than a few hours if its power is supplied from the battery.  
           [0005]    [0005]FIG. 1 is a simplified block diagram of a related art notebook. The notebook of FIG. 1 comprises a CPU  11  conducting ordinary well-known operations and functions; a bridge controller  12  conducting both assistant operations of the CPU  11  and management of memories, a video port, a bus, etc.; a video processor  13  for processing video data and outputting the processed data for video presentation; and a clock generator  10  providing a 100 MHz clock signal  1  for the CPU  11  and the bridge controller  12 , and a 66 MHz clock signal  2  for the video processor  13 .  
           [0006]    A PLL (Phase Lock Loop) circuit  110  is embedded in the CPU  11 . The PLL circuit  110  multiplies the 100 MHz clock from the clock generator  10  differently based on a current power supplying mode. For example, the PLL circuit  110  multiplies the 100 MHz clock  1  by a factor of six to produce a 600 MHz internal clock if an AC power mode (PWR mode) is detected, and it multiplies the 100 MHz clock  1  by a factor of five to produce a 500 MHz clock if a battery power mode is detected.  
           [0007]    Because power consumption of a CPU  11  is proportional to the speed of a clock driving the CPU  11 , if a 500 MHz internal clock is used in a battery supplying mode, processing speed is lowered and power dissipation is decreased in comparison with a 600 MHz internal clock. Therefore, battery life is extended.  
           [0008]    However, in a related portable computer, a host bus  3  to which both a CPU  11  and a bridge controller  12  are connected is driven by a bus clock to bridge controller  12  whose speed is fixed regardless of power supplying mode. Therefore, power saving in a battery supplying mode is less effective.  
           [0009]    The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.  
         SUMMARY OF THE INVENTION  
         [0010]    An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.  
           [0011]    Another object of the present invention is to provide a method of reducing clock speed of a bus in order to extend battery suppliable time longer when electric energy is fed to a portable computer such as a notebook from an equipped battery.  
           [0012]    In order to achieve at least the above-described objects of the present invention in a whole or in part, there is provided a portable device having a CPU and a bridge controller operating in one of AC power mode or battery power mode, wherein the improvement includes a clock generator generating a first clock signal for the CPU and a second clock signal for the bridge controller, wherein first and second clock signals are two distinct clock signals outputted by the clock generator and have different frequencies.  
           [0013]    To further achieve at least the above-described objects of the present invention in a whole or in parts, there is provided a portable device having a CPU and a bridge controller, wherein the improvement includes a clock generator generating a first clock signal, and a clock adjustor operating in one of AC power mode or battery power mode, said clock adjustor generating a second clock signal for the CPU and a third clock signal for the bridge controller, wherein the second and third clock signals are two distinct clock signals outputted by the clock adjustor and have different frequencies.  
           [0014]    To further achieve at least the above-described objects of the present invention in a whole or in parts, there is provided a method for optimizing clock speed generation, including receiving a base clock signal, multiplying the base clock signal by a first factor to produce a first higher frequency clock signal, wherein the first higher frequency clock signal is phase-locked with the base clock signal, receiving a power mode signal indicating either an AC or a battery source, and selectively outputting the first higher frequency clock signal to a first device when the AC source is indicated and outputting the base clock signal to the first device when the battery source is indicated.  
           [0015]    Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:  
         [0017]    [0017]FIG. 1 is a partial block diagram of a related art computer;  
         [0018]    [0018]FIG. 2 is a partial block diagram of a portable computer in which a bus clock controlling apparatus in accordance with a preferred embodiment of the present invention is embedded;  
         [0019]    [0019]FIG. 3 is a detailed block diagram of the PLL circuit built in a controlling device according to the embodiment of FIG. 2;  
         [0020]    [0020]FIG. 4 is a block diagram of a portable computer in which another bus clock controlling apparatus in accordance with a preferred embodiment the present invention is embedded; and  
         [0021]    [0021]FIG. 5 is a detailed block diagram of the PLL block applying each clock to each device according to the embodiment of FIG. 4. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0022]    In order that the invention may be fully understood, preferred embodiments thereof will now be described with reference to the accompanying drawings.  
         [0023]    [0023]FIG. 2 is a block diagram of a portable computer in which a bus clock controlling apparatus in accordance with the present invention is embedded. The portable computer of FIG. 2 includes a CPU  11 , a bridge controller  22 , and a video processor  23 . The portable computer of FIG. 2 further comprises a clock generator  20  which may provide CPU  11 , bridge controller  22  and video processor  23  with necessary clock signals.  
         [0024]    The clock generator  20  may provide the CPU  11  with a 100 MHz CPU clock signals  101 , the bridge controller  22  with a 66.7 MHz host clock signals  102  (lower in frequency than the 100 MHz CPU clock  101 ), and the video processor  23  with a 33.33 MHz clock signal  103  (lower in frequency than a conventional 66 MHz AGP clock).  
         [0025]    A PLL circuit  210  may be included in the CPU  11 . As aforementioned, the PLL circuit  110  may multiply the 100 MHz CPU clock  101  from the clock generator  20  selectively based on the current power supplying mode. For example, the PLL circuit  110  may multiply the frequency of a 100 MHz clock  101  by six if an external AC power is fed, and it may multiply the frequency by five if a battery is supplying necessary electric energy.  
         [0026]    In addition, another PLL circuit  220  may be embedded in the bridge controller  22 . The PLL circuit  220  may multiply the frequency of the 66.7 MHz host clock  102  from the clock generator  20  by one and a half to produce a 100 MHz PCI bus clock in an AC power supplying mode, and may use the 66.7 MHz host clock  102  as it is without frequency multiplication in a battery supplying mode.  
         [0027]    [0027]FIG. 3 is a detailed block diagram of the PLL circuit  220 . The PLL circuit  220  may include a phase comparator  221  outputting a DC voltage proportional to the phase difference between the 66.7 MHz host clock  102  and a divided internal oscillating clock; a voltage controlled oscillator (VCO)  222  generating the internal oscillating clock of about 400 MHz whose frequency varies in proportion to the level of the DC voltage applied from the phase comparator  221 ; a ⅙ frequency divider  223  dividing the 400 MHz internal oscillating clock by 6 to produce a 66.7 MHz clock; a ¼ frequency divider  224  dividing the 400 MHz internal clock by 4 to produce a 100 MHz clock; and a switch  225  selecting the inputted 66.7 MHz host clock  102  or the divided 100 MHz clock  102   a  in accordance with the power supplying mode to output a host bus clock or to use it as an internal operation clock.  
         [0028]    The PLL comparator  221  may output a DC signal to increase or decrease the frequency of the internal oscillating clock generated by VCO  222  in proportion to the phase difference between two applied signals, so that the two applied signals become in phase exactly. Therefore, the frequency of the internal oscillating clock may be six times as high as that of the inputted 66.7 MHz host clock  102  while its phase is locked with the host clock  102 . Accordingly, if the internal oscillating clock frequency is divided by  4 , a 100 MHz clock whose phase is locked with the inputted host clock  102  may be produced and it can be used as a bus clock of a host bus through the bridge controller  22 .  
         [0029]    The switch  225  may select the 66.7 MHz host clock  102  when the power supplying mode is indicative of the battery mode, while it may select the 100 MHz clock  102   a  divided from the internal oscillating clock in the external AC supplying mode. If a battery is supplying electric energy, the above elements  221 ,  222 ,  223 , and  224  need not be operative, thus it may be preferable to cut off power supply for them in that mode.  
         [0030]    The video processor  23  may also include PLL circuit  230 . The PLL circuit  230  of the video processor  23  may multiply the 33.33 MHz clock from the clock generator  20  by two to produce a 66.7 MHz AGP video clock in AC power supplying mode, and may use the 33.33 MHz clock without frequency multiplication in battery supplying mode.  
         [0031]    The structure of the PLL circuit  230  may be similar to that shown in FIG. 3 except for the frequency dividing ratio and other respects. In the PLL circuit  230  whose input frequency is 33.33 MHz, a 200 MHz-oscillating clock may be generated from an internal clock generator (corresponding to the element  222  of FIG. 3), and a ⅓ frequency divider (corresponding to the element  224  of FIG. 3) may be used. In this instance a clock output by the ⅓ frequency divider is at a frequence of 66.7 MHz.  
         [0032]    In the portable computer configured as above, if a battery is supplying electric energy, the frequency of a bus clock provided to a host bus by the bridge controller  22  may be decreased to 66.7 MHz from 100 MHz, and the frequency of an internal clock used by the video processor  23  may also be decreased to 33.33 MHz from 66.7 MHz. This clock speed reduction results in extension of battery life.  
         [0033]    A detecting means, which outputs a signal indicating power supplying mode after detecting which power source between an external AC power and a battery is supplied at present, can be integrated into the bridge controller  22  or may be implemented as a separate device.  
         [0034]    [0034]FIG. 4 is a block diagram of a portable computer in which another bus clock controlling apparatus in accordance with the present invention is embedded. In the block diagram of FIG. 4, PLL circuits for reducing clock speed in battery mode may not be included in the bridge controller  32  and the video processor  33 . Instead, a separate PLL block  40  may be included in the embodiment of FIG. 4. The PLL block  40 , which can be manufactured with a customized semiconductor such as an ASIC (Application Specific Integrated Circuit), may provide each element with respective necessary clocks of mutually different frequency. A clock generator  30  may be further included in the embodiment of FIG. 4 to supply the PLL block  40  with a basic clock  114  of 33.33 MHz.  
         [0035]    However, a PLL circuit  110  for producing 600 MHz or 500 MHz by multiplying 100 MHz differently may be embedded in the CPU  11  as mentioned above.  
         [0036]    The frequency 33.33 MHz of the basic clock  114  applied to the PLL block  40  from the clock generator  30  may be equal to the lowest among clock frequencies the PLL block  40  provides in battery supplying mode. The PLL block  40  may be configured as in FIG. 5 to supply all clocks, namely, 100 MHz clock necessary to the CPU  11  regardless of power supplying mode, and 33.33 MHz, 66.7 MHz and 100 MHz clocks which are selectively provided to the bridge controller  32  and video processor  33  according to power supplying mode.  
         [0037]    A phase comparator  421  of FIG. 5 may adjust the frequency of the approximately 200 MHz oscillating clock of a VCO  422  in proportion to a detected phase difference between the 33.33 MHz clock  114  from clock generator  30  and a ⅙ divided clock from the 200 MHz oscillating clock. As a result, the phase of the 200 MHz oscillating clock may be locked with the applied 33.33 MHz clock  114  from clock generator  30 .  
         [0038]    In phase-locked state of the 200 MHz clock, a 100 MHz clock may be produced from a ½ divider  423  dividing the 200 MHz clock by two, and 66.7 MHz clock may also be produced from a ⅓ divider  425  dividing the 200 MHz clock by three. Therefore, the 100 MHz clock  111  from the ½ divider  423  may be applied to the CPU  11  at all times.  
         [0039]    In the circuit of FIG. 5, switches  426   a  and  426   b  select ‘A’ terminals as input if power supplying mode is indicative of external AC, so that the 100 MHz clock is applied to the bridge controller  32  as host clock  112  and the 66.7 MHz clock is applied to the video processor  33  as AGP clock  113 . If electric power is fed from a battery, ‘B’ terminals are chosen; therefore, the host clock  112  and the AGP clock  113  become 66.7 MHz and 33.33 MHz, respectively.  
         [0040]    Accordingly, lower frequency clocks in battery mode than in AC mode may be provided for corresponding devices, which means that power consumption is reduced when a battery is supplying necessary electric energy.  
         [0041]    In the embodiments of FIGS. 2 and 4, the output clocks of the clock generators  20  and  30  may be applied without regard to power supplying mode. Furthermore, in the embodiments of FIGS. 2 and 4, clock frequency adjusting means may be embedded in the CPU, bridge controller, and video processors or implemented as a separate device.  
         [0042]    As can be appreciated, based on the disclosure of the preferred embodiments, the output of the clock generators  20  and  30  of FIGS. 2 and 4, respectively, may be applied without raising the frequency during the battery power mode but increasing the clock frequency if an AC power mode is detected. Alternatively, the output of the clock generators  20  and  30  may be applied without frequency adjustment in the AC power mode but decreasing the clock frequency if a battery power mode is detected.  
         [0043]    In another embodiment, the clock frequency adjusting means may be integrated into a clock generator  30 . The clock frequency adjusting means mentioned here is a device which adjusts or maintains frequency of an input clock based on which power source is feeding electric energy, and applies the frequency-adjusted or -maintained clock to external devices.  
         [0044]    An alternative embodiment of the invention, the frequency adjusting means may be embedded in other combinations of the clock generator, PLL ASIC, CPU, bridge controller, video processor, and/or other devices.  
         [0045]    The bus clock controlling apparatus of a portable computer according to the present invention reduces speed of a bus clock and a device clock in battery mode. Therefore, electric energy stored in a battery is saved, extending battery life.  
         [0046]    In addition, the present invention can be applied to a PCI bus for data communication among peripheral devices connected to the PCI bus by providing the clock to another Bridge controller for a PCI bus in the same way as for the host bus.  
         [0047]    The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.