Abstract:
The multiple-channel clock and data recovery scheme of the present invention derives a single clock signal from multiple mis-matched data streams. The single clock is phased to provide a clocking signal such that the data sampler of the clock and data recovery scheme performs bit center sampling of the data at the bit center average of all channels. The phase of the recovery clock is the average of all the data stream phases, and is the optimal sampling phase for minimum combined bit error rate of all the channels.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority under 35 USC § 119 to U.S. Pat. application Ser. No. 60/061,319, filed Oct. 7, 1997, which is incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to fiber optic communication, and more particularly, to a multiple-channel clock and data recovery scheme for re-timing fiber optic data input streams into a synchronous state. 
     2. Description of Related Art 
     With the advent of parallel ribbon fiber cable and optical component array integration, high-speed optical data communication links are becoming increasingly practical and desirable. It is a challenge in achieving low-cost parallel modules for formatting fiber optic data, however, to incorporate a data receiver that performs clock and data recovery on multiple data input channels simultaneously. A typical data communications receiver for a single-channel input system requires a clock recovery circuit to extract timing information from an incoming data bit stream. 
     The recovery clock provides synchronous sampling off of the input data bits. 
     Carrying this approach to a multi-channel input system, however, induces error into the system. The application of the typical single-channel approach to a multi-channel input system typically requires integrating multiple clocks, e.g. one clock per channel. However, integrating one clock per channel results in multiple clocks that are competing on a single integrated circuit. The multiple clocks each tend to accumulate jitter due to the cross-coupling of the associated relatively high-power signals. 
     A need exists, therefore, for a multiple-channel clock and data recovery scheme that is capable of outputting a single clock signal to re-time all of the multiple channel data and that is thereby able to reduce the jitter and channel crosstalk that can occur with multiple clocks. 
     SUMMARY OF THE INVENTION 
     The problems outlined above are in large measure solved by a multiple-channel clock and data recovery scheme according to the present invention. The multiple-channel clock and data recovery scheme is a data synchronization system for a fiber optics data communication receiver. The fiber optics data communication receiver has a plurality of fiber optic data inputs. Each data input is received by a data sampler. The data sampler samples the input data according to a transition in a clocking signal received from a single clock. Each data sampler produces a data output for each fiber optic data input sampled. A phase detector is provided for each data input channel and compares this data output with the single clock signal. The phase detector determines a phase difference between the data output and the clock signal for each data input channel. The single clock averages the phase differences for all of the data input channels and determines an average data center for all of the data input channels. The single clock then produces the clocking signal, which is directed to the data sampler and phase detector, such that the data sampler samples the input data at the average data center. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a multiple-channel clock and data recovery scheme according to an embodiment of the present invention. 
     FIG. 2 is an input data signal timing diagram depicting 1 through N channels of binary encoded input data. 
     FIG. 3 depicts an embodiment of a data sampler utilized in the present invention. 
     FIG. 4A depicts an embodiment of a phase detector utilized in the present invention. 
     FIG. 4B depicts the input waveforms DATA and CLOCK to the phase detector of FIG.  4 A and depicts the output waveforms UPN and DOWN from the phase detector of FIG.  4 A. 
     FIG. 5A depicts an embodiment of a charge pump circuit utilized in the present invention. 
     FIG. 5B depicts the input and output waveforms of the charge pump circuit of FIG.  5 A. 
     FIG. 6 depicts an embodiment of a loop filter utilized in the present invention. 
     FIG. 7A depicts an embodiment of a voltage controlled oscillator utilized in the present invention. The voltage controlled oscillator includes a voltage control circuit and a plurality of delay cells. 
     FIG. 7B depicts the output waveforms of each of the delay cells of FIG.  7 A. 
     FIG. 7C depicts a circuit diagram of the delay cell of FIG.  7 A. 
     FIG. 8 is a schematic illustration of a single integrated circuit containing the clock and data recovery scheme according to the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 1 is a block diagram reflecting a multiple-channel clock and data recovery scheme  10  according to an embodiment of the invention. Scheme  10  generally incorporates N input channels  12 , each input channel  12  being directed into an associated data sampler  14  whose output is directed to an associated data output  16  and into an associated phase detector  18 . The output of each phase detector  18  is coupled to an associated charge pump  20 . In this embodiment, there are N data samplers  14 , N phase detectors  18  and N charge pumps  20 . The outputs of each of the charge pumps  20  are directed to a single loop filter  22  whose output is input to a voltage controlled oscillator (VCO)  24 . The output of VCO  24  is input to each data sampler  14  and each phase detector  18 . Clock  26  generally comprises the components of VCO  24  and loop filter  22 . 
     FIG. 2 provides an example of N input signals that are fed into N input channels  12 . As shown, the N input signals are binary encoded signals having two distinct electrical levels representing logic “1” and “0”. Each input binary encoded signal, channel  1 ,  2 ,  3 , . . . N, steps to logical level “1” at time t 1 , t 2 , t 3 , . . . t N , respectively, as measured from time t 0 . Due to transmission path mismatch, the data channels are not necessarily perfectly aligned in time, i.e. t 1  does not necessarily equal t 2  which does not necessarily equal t 3 . The phase, or time, difference between the fastest and slowest channels is defined as the phase skew. The average phase of all N channels is defined as the sum of all the phase transition times divided by N, the number of channels. In other words, 
     
       
         average phase=[t 1 +t 2 +t 3 +. . . +t N ]/N.  (1) 
       
     
     Data sampler  14 , depicted in detail in FIG. 3, is preferably implemented with a d-type flip-flop. Each of the N data samplers  14  receives and re-times its data input signal from N-input channel  12  according to the clock signal received from clock  26 . 
     As such, DATA IN is preferably sampled at the “0” to “1” transition of the clock signal from clock  26  and presented at DATA OUT. Note that the d-type flip-flop operates such that the next state of the flip-flop is equal to its present excitation. For example, if a one is applied to DATA IN, at the next transition of CLOCK signal, Q (DATA OUT) will be a logic level one. This operation of data sampler  14  synchronizes the data with clock  26 . 
     The data out of each data sampler  14  is received by a phase detectors  18 , depicted in detail in FIG.  4 A. Phase detector  18  preferably comprises a first d-type flip-flop  181  and a second d-type flip-flop  182 . As shown, data output from data sampler  14  is input to flip-flop  181 . The clock signal from clock  26  is input to flip-flop  181  and is also sent through NOT gate  183  and input to flip-flop  182 . The output of flip-flop  181 , designated Q 181 , is input to exclusive OR gate  184  with the data input signal from data sampler  181  and is also input to exclusive OR gate  185  with the output, designated Q 182 , of flip-flop  182 . The output of exclusive OR gate  184  is input to a NOT gate  186  whose output is designated UPN. The output of exclusive OR gate  185  is designated DOWN. Outputs UPN and DOWN drive the input to charge pump  20 . 
     FIG. 4B provides example waveforms to help explain the operation of phase detector  18 . Phase detector  18  compares the phase transitions of the INPUT DATA from data sampler  14 , which is non-return-to-zero (NRZ) data, with the reference CLOCK signal from clock  26 . The rising edge of INPUT DATA causes the UPN output to transition active, i.e. “0”, and is reset to non-active, i.e. “1”, on a rising edge of CLOCK. The rising edge of CLOCK causes DOWN to transition active, i.e. “1”, for one half of a CLOCK cycle. The difference in the active pulse widths of UPN and DOWN represents the phase difference between INPUT DATA and CLOCK (Note that when clock and data recovery scheme  10  is in steady state, the pulse widths are equal to one half of a clock cycle). As such, each phase detector  18  operates to determine the phase error of its N input channel  12  and generates phase error voltage pulses. 
     Charge pump  20 , depicted in detail in FIG. 5A, receives signals UPN and DOWN from phase detector  18 . Signal UPN is tied to the gate of transistor T 6  while the source of T 6  is tied to the drain of transistor T 5  and the drain of T 6  is tied to the drain of T 3  and provides the output signal IOUT. The source of T 5  is connected to the source of transistor T 4  and to voltage V DD . The gate of T 5  is connected to the gate of T 4  and to the drain of T 4 . The drain of T 4  is also connected resistor R 1 . The value of R 1  is determined by specific system and circuit parameters. As an example, for N=4, a data rate of 1.25 Gbit per channel and a typical commercially available integrated circuit process, a typical value for R 1  would be 130 kohms. This would result in 10 microampere output current pulses. R 1  is further connected to the drain and gate of transistor T 1  while the source of T 1  is connected to the source of T 2  and voltage V SS . The gates of T 1  and T 2  are tied together as are the source of transistor T 3  and the drain of T 2 . The gate of T 3  is connected to the input DOWN from phase detector  18 . 
     As indicated by the output waveforms IOUT and−IOUT, shown in FIG. 5B, charge pump  20  generates positive and negative current pulses when triggered by digital pulses at inputs UPN and DOWN, respectively. Bias resistor R 1  feeds current into NMOS transistor T 1 . This current is mirrored by T 2  and is switched, as a negative current, to the output IOUT, by switch T 3 , which is controlled by the input DOWN. In a similar manner, R 1  feeds an identical current into PMOS transistor T 4 . This current is mirrored by T 5  and is switched, as a positive current, to the output IOUT, through switch T 6 . T 6  is controlled by input UPN. In this manner, charge pump  20  converts the phase error voltage pulses from phase detector  18  to current pulses. These current pulses are preferably hard-wired together and, as such, are mathematically summed and input to single loop filter  22 . 
     Loop filter  22  is depicted in detail in FIG.  6 . The mathematically summed current input from charge pumps  20 , indicated CURRENT IN, are tied to the series sequence of resistor R 2  and capacitor C 1  and to capacitor C 2 , all of which operate to convert the CURRENT IN to a low frequency, control voltage, VOLTAGE OUT, for VCO  24 . As such, a closed clock and data recovery feedback loop results. The values of R 2 , C 1  and C 2  are determined by specific system requirements and circuit parameters. As an example, for N equal to 4, a data rate of 1.25 Gbit per channel, typical values would be R 2  equal to 100 ohms, C 1  equal to 1 nanoFarad, and C 2 =10 picofarads. It should be noted, these values are only illustrative of one embodiment and are not meant to be limiting. 
     VCO  24 , depicted in detail in FIG. 7A, preferably comprises four delay cells,  241 ,  242 ,  243  and  244  connected as a ring oscillator  245 , and a voltage control circuit  246 . The voltage from loop filter  22 , VOLTAGE OUT, is input to voltage control circuit  243  as VCON. VCON is tied to the gate of transistor T 7  whose source is tied to voltage V ss  and to the source of T 8 . The drain of T 7  is connected to the drain and gate of T 9 . The source of T 9  is connected to voltage V DD  and to the source of transistor T 10 . The gate of T 10  is tied to the gate of T 9  and is provided as the input BIASP to each of the delay cells,  241 ,  242 ,  243 , and  244 . The drain of T 10  is connected to the drain of T 8 , to the gate of T 8  and provides the input BIASN to each of the delay cells,  241 ,  242 ,  243  and  244 . The output OUTP of delay cell  241  is tied to the input INP of delay cell  242 . The output OUTN of delay cell  241  is tied to the input INN of delay cell  242 . Likewise, the output OUTP of delay cell  242  is input to input INP of delay cell  243  and the output OUTP of delay cell  243  is input to the input INP of delay cell  244 . The output OUTN of delay cell  242  is input to the input INN of delay cell  243  and the output OUTN of delay cell  243  is input to the input INN of delay cell  244 . The output OUTP of delay cell  244  provides the output clock signal, CLOCK OUT, and is tied back to the input INN of delay cell  241 . The output OUTN of delay cell  244  is tied back to the input INP of delay cell  241 . 
     Due to the time delay of each cell,  241 ,  242 ,  243  and  244 , and the overall positive feedback of the loop, the circuit depicted in FIG. 7A will oscillate resulting in a digital square wave output, CLOCK OUT. Each delay cell output switches sequentially based on the cell delay. Voltage control of VCO  24  is achieved by modulating the bias current of the delay cell,  241 ,  242 ,  243  and  244 . T 7  acts as a voltage to current converter and feeds current into T 9 , which generates a bias voltage BIASP for PMOS transistors in delay cells,  241 ,  242 ,  243  and  244 . The current control is also mirrored into T 8  via T 10  to generate the bias voltage BIASN for NMOS transistors in delay cells  241 ,  242 ,  243  and  244 . 
     FIG. 7B provides a view of how the output of VCO  24  is delayed by each of the delay cells: delay cell  241  at stage  1 , delay cell  242  at stage  2 , delay cell  243  at stage  3  and delay cell  244 , the output clock signal CLOCK OUT, at stage  4 . 
     A schematic of a delay cell, i.e. delay cell  241 ,  242 ,  243  and  244 , is depicted in FIG.  7 C. Voltage BIASN is connected to the gate of transistor T 11  while the source of T 11  is connected to voltage V ss . The drain of T 11  is connected to the source of both transistor T 12  and T 13 . The gate of T 12  is tied to input INP and the gate of T 13  is tied to the input INN. The drain of T 12  is connected to the drain of T 14  and provides the signal OUTN. The drain of T 13  is connected to the drain of T 15  and provides the signal OUTP. The gates of transistors T 14  and T 15  are tied to voltage BIASP while the sources of T 14  and T 15  are tied to voltage V DD . 
     As shown in FIG. 7C, the delay cell preferably comprises an NMOS differential pair, T 12  and T 13 , which steer bias current from T 11  into PMOS loads, T 14  and T 15 . T 14  and T 15  are biased in the linear transistor region of operation and hence, appear as linear resistive loads. As the bias current through T 11  increases, more current is provided at the outputs to drive the circuit capacitance higher resulting in a higher slew rate. Simultaneously, the voltage at BIASP is decreased causing the effective resistance of T 14  and T 15  to decrease. The decrease in load resistance is compensated by an increase in drive current resulting in a stable output signal amplitude with changing cell delay. 
     The result of clock and data recovery scheme  10  is a recovery clock  26  that averages the phase transition times of all data channels and that samples the data at the average data bit center of all channels  12 , which is the optimal sampling phase for minimum combined bit error rate of all the channels. Other advantages provided by scheme  10  include reducing overall power consumption, since only a single VCO  24  is used for all input channels  12 , and reducing overall integrated circuit chip area since a single loop filter may be used for all input channels  12 . Furthermore, the jitter that would usually result from multiple competing high-power clock crosstalk on a single integrated circuit is substantially eliminated. C 1 ock and data recovery scheme  10  is preferably contained as part of single integrated circuit that may or may not contain additional circuitry. An example of a single integrated circuit  300  containing clock and data recovery scheme  10  is illustrated schematically in FIG.  8 . It should be noted that the integrated circuit  300  may include one or more of the circuits embodying the present invention. In addition, integrated circuit  300  may also include other integrated circuitry not shown. Note that while a single integrated circuit is preferred, other appropriate manners of establishing clock and data recovery scheme, e.g. individual components, may be used without departing from the spirit or scope of the invention. 
     The present invention may be embodied in other specific forms without departing from the spirit of the essential attributes thereof; therefore, the illustrated embodiment should be considered in all respects as illustrative and not restrictive, reference being made to the appended claims rather than to the foregoing description to indicate the scope of the invention.