Abstract:
In a step-up apparatus, a first level shift circuit receives a first clock signal to generate two phase-opposite second clock signals, and a second level shift circuit receives the first clock signal to generate two phase-opposite third clock signals. A charge pump circuit steps up a power supply voltage at a power supply voltage terminal using the second clock signals to generate a positive voltage, and a polarity inverting circuit inverts the positive voltage using the third clock signals to generate a negative voltage whose absolute value is the same as the positive voltage. A high level of the second clock signals is not higher than the positive voltage, and a low level of the second clock signals is not lower than a voltage at a ground terminal. A high level of the third clock signals is not higher than the power supply voltage, and a low level of the third clock signals is not lower than the negative voltage.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a step-up apparatus or a DC-DC converter. 
     2. Description of the Related Art 
     Generally, a step-up apparatus is constructed by a charge pump circuit. On the other hand, in a liquid crystal display (LCD) apparatus, a positive voltage and a negative voltage are required to maintain the quality of the liquid crystal. 
     A first prior art step-up apparatus for generating a positive voltage and a negative voltage is constructed by a first level shift circuit for receiving a first clock signal to generate two second clock signals opposite in phase with each other, a K (K=2, 3, . . . )-multiple charge pump circuit for generating the positive voltage of K·V DD  using the second clock signals where V DD  is a power supply voltage, a second level shift circuit for receiving the first clock signal to generate two third clock signals opposite in phase with each other, and a (−K)-multiple charge pump circuit for generating the negative voltage of −K·V DD  using the third clock signals. This will be explained later in detail. 
     In the above-described first prior art step-up apparatus, however, since the (−K)-multiple charge pump circuit is complex, the step-up apparatus is high in cost. 
     A second prior art step-up apparatus for generating a positive voltage and a negative voltage is constructed by a level shift circuit for receiving a clock signal to generate two phase-opposite clock signals, a K(K=2, 3, . . . )-multiple charge circuit for generating the positive voltage of K·V DD  using the two phase-opposite clock signals, and a (−1)-multiple charge pump circuit for generating the negative voltage of −K·V DD  using the positive voltage and the two phase-opposite clock signals. This also will be explained later in detail. 
     In the above-described second prior art step-up apparatus, the number of circuit elements is decreased to simplify the apparatus. However, since the transistors within the level shift circuit need to have a much higher breakdown voltage than that of the level shift circuits of the above-described first prior art step-up apparatus, the thickness of gate insulating layers of the transistors, the gate length and/or gate width of the transistors need to be large, which would degrade the integration. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a step-up apparatus including level shift circuits capable of a low breakdown voltage. 
     According to the present invention, in a step-up apparatus, a first level shift circuit receives a first clock signal to generate two phase-opposite second clock signals, and a second level shift circuit receives the first clock signal to generate two phase-opposite third clock signals. A charge pump circuit steps up a power supply voltage at a power supply voltage terminal using the second clock signals to generate a positive voltage, and a polarity inverting circuit inverts the positive voltage using the third clock signals to generate a negative voltage whose absolute value is the same as the positive voltage. A high level of the second clock signals is not higher than the positive voltage, and a low level of the second clock signals is not lower than a voltage at a ground terminal. A high level of the third clock signals is not higher than the power supply voltage, and a low level of the third clock signals is not lower than the negative voltage. 
     Also, in a step-up apparatus, a first level shift circuit receives a first clock signal to generate two phase-opposite second clock signals, and a second level shift circuit receives the first clock signal to generate a third clock signal. A charge pump circuit steps up a power supply voltage at a power supply voltage terminal using the second clock signals to generate a positive voltage. A polarity inverting circuit inverts the positive voltage using the third clock signal to generate a negative voltage whose absolute value is the same as the positive voltage. A high level of the second clock signals is not higher than the positive voltage, and a low level of the second clock signals is not lower than a voltage at a ground terminal. A high level of the third clock signal is not higher than the voltage at the ground voltage, and a low level of the third clock signal is not lower than the negative voltage. 
     Further in a step-up apparatus, a level shift circuit receives a first clock signal to generate a 2nd clock signal, a 3rd clock signal, . . . , a K-th clock signal (K=2, 3, . . . ) having a definite voltage swing. A charge pump circuit steps up a power supply voltage at a power supply voltage terminal using said first, second, . . . , K-th clock signals to generate a positive voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will be more clearly understood from the description set forth below, ad compared with the prior art, with reference to the accompanying drawings, wherein: 
         FIG. 1  is a block circuit diagram illustrating a first prior art step-up apparatus; 
         FIGS. 2A ,  2 B,  2 C,  2 D and  2 E are timing diagrams showing the clock signals of the step-up apparatus of  FIG. 1 ; 
         FIG. 3  is a detailed circuit diagram of the level shift circuit of  FIG. 1 ; 
         FIG. 4  is a detailed circuit diagram of the level shift circuit of  FIG. 1 ; 
         FIG. 5  is a detailed circuit diagram of the K-multiple charge pump circuit of  FIG. 1 ; 
         FIG. 6  is a detailed circuit diagram of the (−K)-multiple charge pump circuit of  FIG. 1 ; 
         FIG. 7  is a block circuit diagram illustrating a second prior art step-up apparatus; 
         FIGS. 8A ,  8 B and  8 C are timing diagrams showing the clock signals of the step-up apparatus of  FIG. 7 ; 
         FIG. 9  is a detailed circuit diagram of the level shift circuit of  FIG. 7 ; 
         FIG. 10  is a detailed circuit diagram of the (−1)-multiple charge pump circuit of  FIG. 7 ; 
         FIG. 11  is a block circuit diagram illustrating a first embodiment of the step-up apparatus according to the present invention; 
         FIGS. 12A and 12B  are detail circuit diagrams of the (−1)-multiple charge pump circuit of  FIG. 11 ; 
         FIG. 13  is a table for explaining the ON gate voltages and OFF gate voltages of the transistors of  FIGS. 12A and 12B ; 
         FIG. 14  is a block circuit diagram illustrating a second embodiment of the step-up apparatus according to the present invention; 
         FIGS. 15A ,  15 B,  15 C and  15 D are timing diagram showing the clock signals of the step-up apparatus of  FIG. 14 ; 
         FIG. 16  is a detailed circuit diagram of the level shift circuit of  FIG. 14 ; 
         FIG. 17  is a detailed circuit diagram of the (−1)-multiple charge pump circuit of  FIG. 14 ; 
         FIG. 18  is a table for explaining the ON gate voltages and OFF gate voltages of the transistors of  FIG. 17 ; 
         FIG. 19  is a circuit diagram illustrating a first modification of the step-up apparatus of  FIG. 10 ; 
         FIG. 20  is a circuit diagram of the L-multiple charge pump circuit of  FIG. 19 ; 
         FIG. 21  is a circuit diagram illustrating a second modification of the step-up apparatus of  FIG. 10 ; 
         FIG. 22  is a circuit diagram of the K-multiple charge pump circuit of  FIG. 21 ; 
         FIG. 23  is a circuit diagram illustrating a first modification of the step-up apparatus of  FIG. 14 ; 
         FIG. 24  is a circuit diagram illustrating a second modification of the step-up apparatus of  FIG. 14 ; 
         FIG. 25  is a circuit diagram illustrating a modification of the level shift circuit and the K-multiple charge pump circuit of  FIGS. 11 and 14 ; 
         FIGS. 26A ,  26 B,  26 C,  26 D and  26 E are timing diagrams showing the clock signals of  FIG. 25 ; 
         FIG. 27  is a detailed circuit diagram of the level shift circuit of  FIG. 25 ; 
         FIG. 28  is a block circuit diagram illustrating a third embodiment of the step-up apparatus according to the present invention; 
         FIG. 29  is a detailed circuit diagram of the K-multiple charge pump circuit of  FIG. 28 ; 
         FIG. 30  is a table for explaining the ON gate voltages and OFF gate voltages of the transistors of  FIG. 29 ; and 
         FIG. 31  is a circuit diagram of the step-up apparatus of  FIG. 28  applied to an LCD apparatus. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before the description of the preferred embodiments, prior art step-up apparatuses will be explained with reference to  FIGS. 1 ,  2 A,  2 B,  2 C,  2 D,  2 E,  3 ,  4 ,  5 ,  6 ,  7 ,  8 A,  8 B,  8 C,  9  and  10 . 
     In  FIG. 1 , which illustrates a first prior art step-up apparatus for generating a positive voltage of K·V DD  (K=2, 3, . . . ) and a negative voltage of −K·V DD , a level shift circuit  1  is powered by the ground voltage GND and the positive voltage K·V DD  to level-shift a clock signal φ 0  having a voltage swing V DD  as shown in  FIG. 2A , and thus generates clock signals φ 1  and {overscore (φ 1 )} having a voltage swing K·V DD  as shown in  FIGS. 2B and 2C . On the other hand, a level shift circuit  2  is powered by the negative voltage −K·V DD  and the positive voltage V DD  to level-shift the clock signal φ 0  having the voltage swing V DD  as shown in  FIG. 2A , and thus generates clock signals φ 2  and {overscore (φ 2 )} having a voltage swing (K+1)·V DD  as shown in  FIGS. 2D and 2E . 
     A K-multiple charge pump circuit  3  steps up the positive voltage V DD  using the clock signals φ 1  and {overscore (φ 1 )} to generate the positive voltage K·V DD . On the other hand, a (−K)-multiple charge pump circuit  4  steps up the positive voltage V DD  using the clock signals φ 2  and {overscore (φ 2 )} to generate the negative voltage −K·V DD . 
     The voltage K·V DD  and −K·V DD  are held in capacitors  5  and  6 , respectively. 
     In  FIG. 3 , which is a detailed circuit diagram of the level shift circuit  1  of  FIG. 1 , a CMOS level shifter formed by cross-coupled load P-channel MOS transistors  101  and  102  and drive N-channel MOS transistors  103  and  104  is powered by the ground voltage GND and the positive voltage K·V DD . The gate of the transistor  103  receives the clock signal φ 0  while the gate of the transistor  104  receives an inverted signal of the clock signal φ 0  via a CMOS inverter  105 . As a result, the CMOS level shifter generates clock signals φ 1  and {overscore (φ 1 )} having the voltage swing of K·V DD  via CMOS inverters  106  and  107 . In this case, the CMOS inverters  105 ,  106  and  107  are powered by the ground voltage GND and the positive voltage K·V DD . Therefore, the transistors within the level shift circuit  1  need to have a breakdown voltage higher than K·V DD . 
     In  FIG. 4 , which is a detailed circuit diagram of the level shift circuit  2  of  FIG. 1 , a CMOS level shifter formed by cross-coupled load N-channel MOS transistors  201  and  202  and drive P-channel MOS transistors  203  and  204  is powered by the negative voltage −K·V DD  and the positive voltage V DD . The gate of the transistor  203  receives the inverted signal of the clock signal φ 0  via a CMOS inverter  205  while the gate of the transistor  204  receives the inverted signal {overscore (φ 0 )}. As a result, the CMOS level shifter generates clock signals φ 2  and {overscore (φ 2 )} having the voltage swing of (K+1)·V DD  via CMOS inverters  206  and  207 . In this case, the inverters  205 ,  206  and  207  are powered by the negative voltage −K·V DD  and the positive voltage V DD . Therefore, the transistors within the level shift circuit  2  need to have a breakdown voltage higher than (K+1)·V DD . 
     In  FIG. 5 , which is a detailed circuit diagram of the K-multiple charge pump circuit  3  of  FIG. 1 , the K-multiple charge pump circuit  3  is constructed by circuits  31 ,  32 ,  33 , . . . ,  3 K. The circuit  31  is formed by a step-up P-channel MOS transistor  311 . On the other hand, the circuits  32 ,  33 , . . . ,  3 K have the same configuration. That is, the circuit  3   i  (i=2, 3, . . . , K) is formed by a charging capacitor  3   i   1 , a charging N-channel MOS transistor  3   i   2 , a charging P-channel MOS transistor  3   i   3  and a step-up P-channel transistor  3   i   4 . 
     The operation of the K-multiple charge pump circuit  3  is explained next. 
     First, when the clock signal φ 1  is made high (=K·V DD ) and the clock signal {overscore (φ 1 )} is made low (=0V), the charging transistors  322 ,  323 ,  332 ,  333 , . . . ,  3 K 2  and  3 K 3  are turned ON, so that the voltages at nodes N 2 , N 3 , . . . , and N K  of the circuits  32 ,  33 ,  3 K are made V DD . Thus, the capacitors  321 ,  331 , . . . ,  3 K 1  are positively charged by V DD . Note that the voltage at node N 1  of the circuit  31  is always V DD . 
     Next, when the clock signal φ 1  is made low (=0V) and the clock signal {overscore (φ 1 )} is made high (K·V DD ), the charging transistors  322 ,  323 ,  332 ,  333 , . . . ,  3 K 2  and  3 K 3  are turned OFF, while the step-up transistors  311 ,  324 ,  334 , . . . , and  3 K 4  are turned ON. As a result, the circuit  31  generates a positive voltage of V DD . In the circuit  32 , V DD  is added to the voltage V DD  at node N 2 , so that the voltage at node N 2  becomes 2·V DD  (=V DD +V DD ). Thus, the circuit  32  generates a voltage of 2·V DD . In the circuit  32 , 2·V DD  is added to the voltage V DD  at node N 2 , so that the voltage at node N 2  becomes 3·V DD  (=V DD  +2·V DD ). Thus, the circuit  32  generates a voltage of 3·V DD . In the circuit  3 K, (K−1)·V DD  is added to the voltage V DD  at node N 2 , so that the voltage at node N 2  becomes K·V DD  (=V DD +(K−1)·V DD ). Thus, the circuit  3 K generates a voltage of K·V DD . 
     In  FIG. 6 , which is a detailed circuit diagram of the (−K)-multiple charge pump circuit  4  of  FIG. 1  (see: FIG. 10 of JP-A-6-165482 where a (−2)-multiple charge pump circuit is disclosed), the (−K)-multiple charge pump circuit  4  is constructed by circuits  40 ,  41 ,  42 , . . . ,  4 K. The circuit  40  is formed by a step-up N-channel MOS transistor  401 . On the other hand, the circuits  41 ,  42 , . . . ,  4 K have the same configuration. That is, the circuit  4   i  (i=1, 2, . . . , K) is formed by a charging capacitor  4   i   1 , a charging P-channel MOS transistor  4   i   2 , a charging N-channel MOS transistor  4   i   3  and a step-up N-channel transistor  4   i   4 . 
     The operation of the (−K)-multiple charge pump circuit  4  is explained next. 
     First, when the clock signal φ 2  is made low (=−K·V DD ) and the clock signal {overscore (φ 2 )} is made high (=V DD ), the charging transistors  412 ,  413 ,  422 ,  423 , . . . ,  4 K 2  and  4 K 3  are turned ON, so that the voltages at nodes N 1 , N 2 , . . . , and N K  of the circuit  41 ,  42 , . . . ,  4 K are made V DD . Thus, the capacitors  411 ,  421 , . . . ,  4 K 1  are negatively charged by V DD . 
     Next, when the clock signal φ 2  is made low (=−K·V DD ) and the clock signal {overscore (φ 2 )} is made high (=V DD ), the charging transistors  412 ,  413 ,  422 ,  423 , . . . ,  4 K 2  and  4 K 3  are turned OFF, while the step-up transistors  401 ,  414 ,  424 , . . . , and  4 K 4  are turned ON. As a result, the circuit  40  generates the ground voltage 0V. In the circuit  41 , −V DD  is added to the voltage 0V at node N 1 , so that the voltage at node N 1  becomes −V DD  (=0−V DD ). Thus, the circuit  41  generates a voltage of −V DD . In the circuit  42 , (−V DD −V DD ) is added to the voltage 0V at node N 2 , so that the voltage at node N 2  becomes −2−V DD  (=0−V DD −V DD ). Thus, the circuit  32  generates a voltage of −2−V DD . In the circuit  4 K, −(K−1)·V DD −V DD  is added to the voltage 0V at node N 2 , so that the voltage at node N 2  becomes −K·V DD  (=0V−(K−1)·V DD −V DD ). Thus, the circuit  4 K generates a voltage of −K·V DD . 
     In the push-up apparatus of  FIG. 1 , however, since the (−K)-multiple charge pump circuit  4  is complex, the step-up apparatus of  FIG. 1  is high in cost. 
     In  FIG. 7 , which illustrates a second prior art step-up apparatus, the level shift circuit  1  of  FIG. 1  is deleted, and the level shift circuit  2  of  FIG. 1  is modified to a level shift circuit  2 A. Also, a (−1)-multiple charge pump circuit (or a polarity inverting circuit)  7  is provided instead of the (−K)-multiple charge pump circuit  4  of  FIG. 1  (see: FIG. 13 of JP-A-6-165482 where K=2). 
     The level shift circuit  2 A is powered by a negative voltage −K·V DD  and a positive voltage K−K DD  to level-shift a clock signal φ 0  having a voltage swing V DD  as shown in  FIG. 8A  to generate clock signals φ 3  and {overscore (φ 3 )} having a voltage swing 2K·V DD  as shown in  FIGS. 8B and 8C . 
     In  FIG. 9 , which is a detailed circuit diagram of the level shift circuit  2 A of  FIG. 7 , a first CMOS level shifter formed by cross-coupled load P-channel MOS transistors  201   a  and  202   a  and N-channel drive MOS transistors  203   a  and  204   a  is powered by the negative voltage −K·V DD  and the positive voltage K·V DD , and also, a second CMOS level shifter formed by cross-coupled load N-channel MOS transistors  205   a  and  206   a  and drive P-channel drive MOS transistors  207   a  and  208   a  is powered by the negative voltage −K·V DD , and the positive voltage K·V DD . The gate of the transistor  203   a  receives the clock signal φ 0  while the gate of the transistor  204   a  receives an inverted signal of the clock signal φ 0  via a CMOS inverter  209   a . Also, the gate of the transistor  207   a  receives a voltage at the drain of the transistor  201   a  while the gate of the transistor  208   a  receives a voltage at the drain of the transistor  202   a . As a result, the second CMOS level shifter generates clock signals φ 3  and {overscore (φ 3 )} having a voltage swing 2K·V DD  via CMOS inverters  210   a  and  211   a . In this case, the inverters  209   a ,  210   a  and  211   a  are powered by the negative voltage −K·V DD  and the positive voltage K·V DD . Therefore, in the transistors within the level shift circuit  2 A need to have a breakdown voltage higher than 2K·V DD . 
     In  FIG. 10 , which is a detailed circuit diagram of the (−1)-multiple charge pump circuit  7  of  FIG. 7 , the (−1)-multiple charge pump circuit  7  is constructed by a charging capacitor  701 , a charging P-channel MOS transistor  702 , a charging N-channel MOS transistor  703 , a step-up N-channel MOS transistor  704  and a step-up N-channel MOS transistor  705 . 
     The operation of the (−1)-multiple charge pump circuit  7  of  FIG. 10  is explained next. 
     First, when the clock signal φ 3  is made low (=−K·V DD ) and the clock signal {overscore (φ 3 )} is made high (=K·V DD ), the transistors  702  and  703  are turned ON, so that the capacitor  701  is charged by 2·V DD . 
     Next, when the clock signal φ 3  is made high (=K·V DD ) and the clock signal {overscore (φ 3 )} is made low (−K·V DD ), the charging transistors  702  and  703  are turned OFF, while the step-up transistors  704  and  705  are turned ON. As a result, the (−1)-multiple charge pump circuit  7  generates the voltage −K·V DD  which is stored in the capacitor  6  of  FIG. 7 . 
     In the step-up apparatus of  FIG. 7 , although the number of circuit elements is decreased to simplify the apparatus, the transistors within the level shift circuit  2 A need to have a breakdown voltage higher than 2K·V DD , which increases the thickness of gate insulating layers, the gate length and/or width of gate electrodes of the transistors, thus degrading the integration of the apparatus. 
     In  FIG. 11 , which illustrates a first embodiment of the step-up apparatus according to the present invention, the (−K)-multiple charge pump circuit  4  of  FIG. 1  is replaced by a (−1)-multiple charge pump circuit (or a polarity inverting circuit)  7 A which receives the positive voltage K·V DD  from the K-multiple charge pump circuit  3  to generate a negative voltage −K·V DD  using the clock signals φ 1 , φ 2  and {overscore (φ 2 )}. 
     The (−1)-multiple charge pump circuit  7 A is illustrated in detail in  FIGS. 12A and 12B  which correspond to  FIG. 10 . 
     In  FIG. 12A , the gates of the transistors  702  and  704  receive the clock signal φ 1 . On the other hand, the gate of the transistor  705  receives the clock signal φ 2  while the gate of the transistor  703  receives the clock signal {overscore (φ 2 )}. That is, as shown in  FIG. 13 , the transistor  702  can be switched between a gate voltage of K·V DD −|V tp | and a gate voltage of K·V DD , and the transistor  704  can be switched between a gate voltage of 0V and a gate voltage of V tn . Note that V tp  designates a threshold voltage of the P-channel MOS transistors, and V tn  designates a threshold voltage of the N-channel MOS transistors. Therefore, the transistors  702  and  704  can be switched between a gate voltage of 0V and a gate voltage of K·V DD , so that the transistors  702  and  704  can be switched by the clock signal φ 1 . Also, as shown in  FIG. 13 , the transistor  705  can be switched between a gate voltage of −K·V DD  and a gate voltage of V tn −K·V DD . Therefore, the transistor  705  can be switched between a gate voltage of −K·V DD  and a gate voltage of V DD , so that the transistor  705  can be switched by the clock signal φ 2 . Further, as shown in  FIG. 13 , the transistor  703  can be switched between a gate voltage of −K·V DD  and a gate voltage of V tn . Therefore, the transistor  703  can be switched between a gate voltage of −K·V DD  and a gate voltage of V DD , so that the transistor  703  can be switched by the clock signal {overscore (φ 2 )}. 
     In  FIG. 12B , the gates of the transistor  702  receive the clock signal φ 1 . On the other hand, the gates of the transistors  704  and  705  receive the clock signal φ 2  while the gate of the transistor  703  receives the clock signal {overscore (φ 2 )}. That is, as shown in  FIG. 13 , the transistor  502  can be switched between a gate voltage of K·V DD −|V tp | and a gate voltage of K·V DD . Therefore, the transistor  702  can be switched between a gate voltage of 0V and a gate voltage of K·V DD , so that the transistor  702  can be switched by the clock signal φ 1 . Also, as shown in  FIG. 13 , the transistor  705  can be switched between a gate voltage of −K·V DD  and a gate voltage of V tn −K·V DD , and the transistor  704  can be switched between a gate voltage of 0V and a gate voltage of V tn . Therefore, the transistors  704  and  705  can be switched between a gate voltage of −K·V DD  and a gate voltage of V DD , so that the transistors  704  and  705  can be switched by the clock signal φ 2 . Further, as shown in  FIG. 13 , the transistor  703  can be switched between a gate voltage of −K·V DD  and a gate voltage of V tn . Therefore, the transistor  703  can be switched between a gate voltage of −K·V DD  and a gate voltage of V DD , so that the transistor  703  can be switched by the clock signal {overscore (φ 2 )}. 
     In  FIG. 13 , note that since V tp  is negative, an ON gate voltage of a P-channel MOS transistor is defined by a gate-to-source voltage of the P-channel MOS transistor equal to |V tp |, and an OFF gate voltage is defined by a gate-to-source voltage of the P-channel MOS transistor equal to 0V. Similarly, since V tn  is positive, an ON gate voltage of an N-channel MOS transistor is defined by a gate-to-source voltage of the N-channel MOS transistor equal to V tn , and an OFF gate voltage is defined by a gate-to-source voltage of the N-channel MOS transistor equal to 0V. 
     Thus, in the step-up apparatus of  FIG. 11 , although the two level shift circuits  1  and  2  are necessary, the transistors within the level shift circuits do not need to have a very high breakdown voltage and the (−1)-multiple charge pump circuit  5 A is simple, which would decrease the apparatus in cost. 
     In  FIG. 14 , which illustrates a second embodiment of the step-up apparatus according to the present invention, the level shift circuit  2  of  FIG. 11  is replaced by a level shift circuit  2 B, and the (−1)-multiple charge pump circuit  7 A of  FIG. 11  is replaced by a (−1)-multiple charge pump circuit  7 B. 
     The level shift circuit  2 B is powered by the negative voltage −K·V DD  and the ground voltage GND to level-shift the clock signal φ 1  as shown in  FIG. 15A  and, thus generates a clock signal φ 4  as shown in  FIG. 15D . 
     The (−1)-multiple charge circuit  7 B steps up the positive voltage K·V DD  using the clock signals φ 1  and φ 4  as shown in  FIGS. 15B and 15D  to generate the negative voltage −K·V DD . 
     In  FIG. 16 , which is a detailed circuit diagram of the level shift circuit  2 B of  FIG. 14 , a capacitor  208  and a diode  209  which also form a (−1)-multiple charge pump circuit or a polarity inverting circuit are added to the elements of the level shift circuit  2  of  FIG. 4 , and the CMOS inverter  207  of  FIG. 4  is deleted. That is, the polarity inverting circuit formed by the capacitor  208  and the diode  209  generates a clock signal φ 0 ′ having a voltage swing of V DD  between −V DD  and 0V. As a result, the CMOS level shifter formed by the transistors  203  to  204  generates the clock signal φ 4  via the CMOS inverter  206 . In this case, the transistors  203  to  204  and the CMOS inverters  205  and  206  are powered by the negative voltage −K·V DD  and the ground voltage GND. Therefore, the transistors within the level shift circuit  2 B need to have a breakdown higher then K·V DD . In other words, the transistors within the level shift circuit  2 B do not need to have a higher breakdown voltage than those within the level shift circuit  2  of  FIG. 1 , which would improve the integration of the apparatus. 
     In  FIG. 17 , which is a detailed circuit diagram of the (−1)-multiple charge pump circuit  7 B of  FIG. 14 , the charging N-channel MOS transistor  703  of  FIG. 10  is replaced by a charging P-channel MOS transistor  703 ′. 
     In  FIG. 17 , the gates of the transistors  702  and  704  receive the clock signal φ 1 . On the other hand, the gates of the transistors  703 ′ and  725  receive the clock signal φ 4 . That is, as shown in  FIG. 18 , the transistor  702  can be switched between a gate voltage of K·V DD −|V tp | and a gate voltage of K·V DD , and the transistor  704  can be switched between a gate voltage of 0V and a gate voltage of V tn . Therefore, the transistors  702  and  704  can be switched between a gate voltage of 0V and a gate voltage of K·V DD , so that the transistors  702  and  704  can be switched by the clock signal φ 1 . Also, as shown in  FIG. 18 , the transistor  705  can be switched between a gate voltage of −K·V DD  and a gate voltage of V tn −K·V DD , and the transistor  703 ′ can be switched between a gate voltage of −|V tp | and a gate voltage of 0V. Therefore, the transistors  703 ′ and  705  can be switched between a gate voltage of −K·V DD  and a gate voltage of 0V, so that the transistors  703 ′ and  705  can be switched by the clock signal φ 4 . 
     In  FIG. 19 , which illustrates a first modification of the step-up apparatus of  FIG. 11 , this step-up apparatus generates a positive voltage of L·V DD  (L=3, 4, . . . ) and a negative voltage −K·V DD  (K=2, 3, . . . ) where L&gt;K. In this case, the K-multiple charge pump circuit  3  of  FIG. 11  is replaced by an L-multiple charge pump circuit  3 A as illustrated in  FIG. 20 . That is, the circuit  3 K of  FIG. 20  generates the positive voltage K·V DD  and transmits it to the (−1)-multiple charge pump circuit  7 A. On the other hand, a circuit  3 L of  FIG. 20  generates a positive voltage L·V DD  and transmits it to the level shift circuit  1  and the capacitor  5 . 
     In  FIG. 21 , which illustrates a second modification of the step-up apparatus of  FIG. 11 , this step-up apparatus generates a positive voltage of L·V DD  (L=2, 3, . . . ) and a negative voltage −K·V DD  (K=3, 4, . . . ) where L&lt;K. In this case, the K-multiple charge pump circuit  3  of  FIG. 11  is replaced by a K-multiple charge pump circuit  3 B as illustrated in  FIG. 22 . That is, a circuit  3 L of  FIG. 22  generates the positive voltage L·V DD  and transmits it to the capacitor  5 . On the other hand, a circuit  3 K of  FIG. 22  generates a positive voltage K·V DD  and transmits it to the level shift circuit  1  and the (−1)-multiple charge circuit  7 A. 
     Thus, according to the modifications of the first embodiment as illustrated in  FIGS. 19 and 21 , the absolute values of the positive voltage and the negative voltage can be different from each other. 
     In  FIG. 23 , which illustrates a first modification of the step-up apparatus of  FIG. 14 , this step-up apparatus generates a positive voltage of L·V DD  (L=3, 4, . . . ) and a negative voltage −K·V DD  (K=2, 3, . . . ) where L&gt;K. In this case, the K-multiple charge pump circuit  3  of  FIG. 14  is replaced by an L-multiple charge pump circuit  3 A as illustrated in  FIG. 20 . That is, the circuit  3 K of  FIG. 20  generates the positive voltage K·V DD  and transmits it to the (−1)-multiple charge pump circuit  7 B. On the other hand, a circuit  3 L of  FIG. 20  generates a positive voltage L·V DD  and transmits it to the level shift circuit  1  and the capacitor  5 . 
     In  FIG. 24 , which illustrates a second modification of the step-up apparatus of  FIG. 14 , this step-up apparatus generates a positive voltage of L·V DD  (L=2, 3, . . . ) and a negative voltage −K·V DD  (K=3, 4, . . . ) where L&lt;K. In this case, the K-multiple charge pump circuit  3  of  FIG. 14  is replaced by a K-multiple charge pump circuit  3 B as illustrated in  FIG. 22 . That is, a circuit  3 L of  FIG. 22  generates the positive voltage L·V DD  and transmits it to the capacitor  5 . On the other hand, a circuit  3 K of  FIG. 22  generates a positive voltage K·V DD  and transmits it to the level shift circuit  1  and the (−1)-multiple charge circuit  7 B. 
     Thus, according to the modifications of the second embodiments as illustrated in  FIGS. 23 and 24 , the absolute values of the positive voltage and the negative voltage can be different from each other. 
     In  FIG. 25 , which illustrates a modification of the level shift circuit  1  and the K-multiple charge pump circuit  3  of  FIGS. 11 and 14 , the level shift circuit  1  of  FIGS. 11 and 14  is replaced by level shift circuits  12 ,  13 , . . . ,  1 K corresponding to the circuits  32 ,  33 , . . . ,  3 K of the K-multiple charge circuit  3 . The level shift circuit  12  receives a clock signal φ( 1 ) (=φ 0 ) having a voltage swing of V DD  as shown in  FIG. 26A  to generate a clock signal φ( 2 ) having a voltage swing of 2·V DD  as shown in  FIG. 26B . The level shift circuit  13  receives a clock signal φ( 2 ) to generate a clock signal φ( 3 ) having a voltage swing of 2·V DD  as shown in  FIG. 26C . Generally, the level shift circuit  1   i  (i=4, 5, . . . , K) receives a clock signal φ(i−1) having a voltage swing of 2·V DD  between (i−3)·V DD  and (i−1)·V DD  as shown in  FIG. 26D  to generate a clock signal (i) having a voltage swing of 2·V DD  between (i−2)·V DD  and i·V DD  as shown in  FIG. 26E . 
     Also, in  FIG. 25 , the P-channel transistors  323 ,  333 , . . . ,  3 K 3  of  FIG. 5  are replaced by N-channel MOS transistors  323 ′,  333 ′ . . . ,  3 K 3 ′, respectively. The gates of the step-up transistors  322 ,  332 , . . . ,  3 K 2  are controlled by the clock signal φ( 1 ) (=φ 0 ) as shown in  FIG. 26A . The gates of the charging transistors  323 ′,  333 ′, . . . ,  3 K 3 ′ are controlled by the clock signal φ( 2 ) as shown in  FIG. 26B . The gates of the step-up transistors  324 ,  334 , . . . ,  3 K 4  are controlled by the clock signals φ( 2 ), φ( 3 ), . . . , φ(K), respectively. 
     The operation of the K-multiple charge pump circuit  3  of  FIG. 25  is explained next. 
     First, when the clock signal φ( 1 ) is made high (=V DD ) so that the clock signal φ( 2 ) is made high (=2·V DD ), the charging transistors  322 ,  323 ′,  332 ,  333 ′,  3 K 2  and  2 K 3 ′ are surely turned ON, so that the voltages at nodes N 2 , N 3 , . . . , and N K  of the circuits  32 ,  33 , . . . ,  3 K are made V DD . Thus, the capacitors  321 ,  331 , . . . ,  3 K 1  are positively charged by V DD . Note that the voltage at node N 1  of the circuit  31  is always V DD . 
     In this case, since the clock signals φ( 2 ), φ( 3 ), . . . , φ(K) are at 2·V DD , 3·V DD , . . . , K·V DD , the transistors  324 ,  334 , . . . ,  3 K 4  are surely turned OFF. 
     Next, when the clock signal φ( 1 ) is made low (=0V) so that the clock signal φ( 2 ) is made low (=0V), the charging transistors  322 ,  323 ′,  332 ,  333 ′, . . . ,  3 K 2  and  3 K 3 ′ are turned OFF. On the other hand, when the clock signals φ( 2 ), φ( 3 ), . . . , φ(K) are at 0V, V DD , . . . , (K−2)·V DD , the step-up transistors  324 ,  324 , . . . ,  3 K 4  are turned ON while the step-up transistor  311  is turned ON. As a result, the circuit  31  generates a positive voltage of V DD . In the circuit  32 , V DD  is added to the voltage V DD  at node N 2 , so that the voltage at node N 2  becomes 2·V DD  (=V DD +V DD ). Thus, the circuit  32  generates a voltage of 2·V DD . In the circuit  32 , 2·V DD  is added to the voltage V DD  at node N 2 , so that the voltage at node N 2  becomes 3·V DD  (=V DD +2·V DD ). Thus, the circuit  32  generates a voltage of 3·V DD . In the circuit  3 K, (K−1)·V DD  is added to the voltage V DD  at node N 2 , so that the voltage at node N 2  becomes K·V DD  (=V DD +(K−1)·V DD ). Thus, the circuit  3 K generates a voltage of K·V DD . 
     Thus, in  FIG. 25 , the charging transistors  322 ,  323 ′,  332 ,  333 ′, . . . ,  3 K 2  and  3 K 3 ′ are controlled by the clock signal φ( 1 ) and φ( 2 ), regardless of their step-up voltages 2·V DD , 3·V DD , . . . , K·V DD . On the other hand, the step-up transistors  311 ,  324 ,  334 , . . . ,  3 K 4  are controlled by the clock signals φ( 1 ), φ( 2 ), . . . , φ(K), respectively depending on their step-up voltages V DD , 2·V DD , 3·V DD , . . . , K·V DD . 
     In  FIG. 27 , which is a detailed circuit diagram of the level shift circuit  1   i  (i=2, 3, . . . , K) of  FIG. 25 , a first CMOS level shifter formed by cross-coupled load N-channel MOS transistors  271  and  272  and P-channel drive MOS transistors  273  and  274  is powered by a voltage (i−2)·V DD  and a voltage (i−1)·V DD , and also, a second CMOS level shifter formed by cross-coupled load P-channel MOS transistors  275  and  276  and drive N-channel drive MOS transistors  277  and  278  is powered by the voltage (i−2)·V DD  and the voltage i·V DD . The gate of the transistor  273  receives an inverted signal of the clock signal φ(i−1) via a CMOS inverter  279  while the gate of the transistor  274  receives the clock signal φ(i−1). Also, the gate of the transistor  277  receives a voltage at the drain of the transistor  273  while the gate of the transistor  278  receives a voltage at the drain of the transistor  274 . As a result, the second CMOS level shifter generates the clock signal φ(i) having a voltage swing 2K·V DD  via a CMOS inverter  280 . In this case, the CMOS inverter  279  is powered by the voltage (i−2)·V DD  and the voltage (i−1)·V DD , while the CMOS inverter  280  is powered by the voltage (i−2)·V DD  and the voltage i·V DD . Therefore, the transistors within the level shift circuit  2  need to have a breakdown voltage higher than 2·V DD . 
     Thus, in  FIG. 25 , although the number of level shift circuits is increased, the transistors therein do not need to have a high breakdown voltage, thus improving the integration. Additionally, in the level shift circuit as illustrated in  FIG. 3  or  4 , the power consumption is proportional to (K·V DD ) 2  (=K 2 ·V DD   2 ). On the other hand, in the level shift circuit as illustrated in  FIG. 25 , the power consumption is proportional to (K−1)·(2·V DD ) 2  (=4(K−1)·V DD   2 ). Therefore, if K&gt;3, the power consumption can be decreased. 
     In  FIG. 28 , which illustrates a third embodiment of the step-up apparatus according to the present invention, the clock signals φ 2  and {overscore (φ 2 )} generated from the level shift circuit  2  of  FIG. 11  are also supplied to the K-multiple charge pump circuit  3 . In more detail, as illustrated in  FIG. 29 , which is a detailed circuit diagram of the K-multiple charge up circuit  3  of  FIG. 28 , the clock signal φ 2  is supplied to the gate of the P-channel MOS transistor  311  and the clock signal {overscore (φ 2 )} is supplied to the P-channel MOS transistor  323 . 
     As shown in  FIG. 30 , all the transistors  311 ,  322 ,  323  and  324  can be switched between a gate voltage of 0V and a gate voltage of K·V DD . Additionally, the transistors  311  and  323  can be switched between a gate voltage of −K·V DD  and a gate voltage of V DD . In  FIG. 28 , use is made of this fact, so that the gate-to-source voltage can be increased to decrease the ON-resistance of the transistors  311  and  323  when they are turned ON. 
     An example of the push-up apparatus of  FIG. 28  applied to a step-up circuit of an LCD apparatus is illustrated in  FIG. 31 . 
     In  FIG. 31 , a voltage 2·V DD  is generated from the circuit  32  and stored in a capacitor  5 ′. The voltage 2·V DD  is supplied to a data line driving circuit of the LCD apparatus. On the other hand, a voltage 3·V DD  is generated from the circuit  33  and is stored in the capacitor  5 . The voltage 3·V DD  is supplied to a gate line driving circuit of the LCD apparatus. Also, the voltage 2·V DD , not the voltage 3·V DD , is supplied to the (−1)-multiple charge pump circuit (polarity inverting circuit)  7 A to generate a voltage −2·V DD . The voltage −2·V DD  is supplied to the gate line driving circuit of the LCD apparatus. 
     As explained hereinabove, according to the present invention, since the breakdown voltage of transistors within the level shift circuits can be lowered, the integration can be improved.