Abstract:
A method for manufacturing a semiconductor device with a dual damascene structure is comprising the steps of preparing a semiconductor substrate, forming a first wiring layer over said semiconductor substrate, forming an inorganic insulating film over said first wiring layer, forming a via hole in said inorganic insulating film by forming a first resist pattern with an opening on said inorganic insulating film and by etching said inorganic insulating film with said first resist pattern as an etching mask, eliminating said first resist pattern, forming an organic insulating film so that said organic insulting film covers an upper side of said inorganic insulating film and an interior of said via hole, forming a hard mask on said organic insulating film, forming a hard mask pattern by forming a second resist pattern with an opening on said hard mask and by etching said hard mask with said second resist pattern as an etching mask, forming a wiring groove by etching said organic insulating film with said second resist pattern and said hard mask pattern as etching masks until said organic insulating film inside said via hole is eliminated and simultaneously eliminating said second resist pattern, and implanting a conductive substance into said via hole and said wiring groove.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a method for manufacturing a semiconductor device and a method for etching the same.  
         [0003]     2. Background Information  
         [0004]     Recently, the performance and function of semiconductor devices has been advanced. For example, the operating frequency of microprocessors has entered a new “GHz band” era, and a system that mounts a plurality of circuits with different functions on one semiconductor chip, a so-called a system-on-chip (SOC), has entered the field. This semiconductor device employs a multilayer wiring structure in which wirings are formed in a plurality of layers in the thickness direction of the semiconductor device in order to improve its degree of integration. In particular, a multilayer wiring structure referred to as a dual damascene structure has been developed in these years. A dual damascene structure is a further advancement of the damascene structure. In the damascene structure, Cu is used as a wiring material because of its low-resistance and high electromigration resistance properties, and wiring is implanted with the chemical mechanical polishing (CMP) method. On the other hand, in the dual damascene method, a wiring groove and a via hole are formed in the interlayer insulating film, and a conductive substance such as Cu is simultaneously implanted in the groove and the hole. Thus, an upper layer wiring and a via plug are formed at one time. Therefore, the manufacturing cost of a semiconductor device is reduced in the dual damascene method, compared to a normal damascene method, a so-called single damascene method, in which a wiring groove and a via hole are separately formed.  
         [0005]     In a semiconductor device with a multilayer wiring structure, the operation speed of the semiconductor device is highly influenced by not only the resistance value of the wiring itself, but also by the inter-wiring capacitance formed by an interlayer insulating film that is formed in a place between a lower layer wiring and an upper layer wiring. Therefore, the resistance of the wiring itself and the inter-wiring capacitance have to be reduced in order to realize an increase in the operation speed of a semiconductor device. To reduce the inter-wiring capacitance, it is required to reduce the dielectric constant of an interlayer insulating film by using a low dielectric constant film, a so-called a low-k film, as an interlayer insulating film. Also, it is required to take the wiring structure into consideration from the perspective of reducing the effective dielectric constant (keff). In general, the dual damascene structure is classified roughly into two structures. One is the so-called homogeneous structure. This is a unitary structure in which the same type of low-k film is used as the insulating film for a wiring portion and for a via hole portion. The other is the so-called hybrid structure. This is a heterogeneous structure in which different types of low-k films are used as the insulating film for a wiring portion and for a via hole portion. In the homogeneous structure, the depth of the wiring grooves is controlled. Therefore, it is required to use a film with a high dielectric constant, such as a silicon nitride film (relative dielectric constant: k=7.0) and a silicon carbide film (k=4.5) as an etching stopper layer. Because of this, the homogeneous structure has a disadvantage in that the value of the effective dielectric constant (keff) becomes high. On the other hand, in the hybrid structure, it is easy to set the etch selectivity between substances of different low-k film to be higher. Therefore, it is not required to use an etching stopper layer with a high dielectric constant, such as silicon nitride film and silicon carbide film. Because of this, the hybrid structure has an advantage in that the effective dielectric constant (keff) of the whole wiring structure can be reduced, compared to the homogeneous structure.  
         [0006]     Japanese Patent Publication JP-A-2002-124568 (especially pages 6-7 and FIG. 2) describes a method for manufacturing a semiconductor device with the hybrid type dual damascene structure. Generally, in manufacturing a dual damascene structure of a semiconductor device, the corners of a hard mask used for forming a wiring groove and a via hole tend to be eliminated and inclined from the perpendicular during the process of etching an interlayer insulating film. This state is called the facet of a hard mask. If a facet state is produced, the wiring size of the hard mask will be wider than the design value. In some cases, this causes a short circuit between a wiring and its adjacent wiring. Because of this, there is a possibility that reliability will be lowered and the yield will be negatively influenced. In a method for manufacturing a semiconductor device described in Japanese Patent Publication JP-A-2002-124568, a facet of a hard mask is prevented in the process of etching by forming at least a layer of a dummy film, which does not exist in the structure at the end of the process of forming a semiconductor device, on the hard mask.  
         [0007]     As described above, in manufacturing a dual damascene structure, there is a problem in that a facet of a hard mask is produced in the process of etching an interlayer insulating film. If a facet of a hard mask is produced, acceleration of etching will begin in the portion where the facet is produced, and this will cause a retrograde phenomenon in the hard mask. This phenomenon makes it difficult to form wiring sized at the desired design value. Because of this, there is a possibility that reliability will be lowered and the yield will be negatively influenced.  
         [0008]     In the method for manufacturing a semiconductor device described in Japanese Patent Publication JP-A-2002-124568, a protective hard mask is further formed on a hard mask that is required to form a wiring groove and a via hole. Therefore, the number of processes to manufacturing a semiconductor device and the cost thereof are increased in the method.  
         [0009]     In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved method for manufacturing a semiconductor device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.  
       SUMMARY OF THE INVENTION  
       [0010]     It is therefore an object of the present invention is to resolve the above-described problems, and to provide a method for manufacturing a semiconductor device in which a facet or a retrograde of a hard mask is prevented.  
         [0011]     In accordance with the present invention, a method for manufacturing a semiconductor device with a dual damascene structure comprises the steps of preparing a semiconductor substrate, forming a first wiring layer over said semiconductor substrate, forming an inorganic insulating film over said first wiring layer, forming a via hole in said inorganic insulating film by forming a first resist pattern with an opening on said inorganic insulating film and by etching said inorganic insulating film with said first resist pattern as an etching mask, eliminating said first resist pattern, forming an organic insulating film so that said organic insulting film covers an upper side of said inorganic insulating film and an interior of said via hole, forming a hard mask on said organic insulating film, forming a hard mask pattern by forming a second resist pattern with an opening on said hard mask and by etching said hard mask with said second resist pattern as an etching mask, forming a wiring groove by etching said organic insulating film with said second resist pattern and said hard mask pattern as etching masks until said organic insulating film inside said via hole is eliminated and simultaneously eliminating said second resist pattern, and implanting a conductive substance into said via hole and said wiring groove.  
         [0012]     According to the method for manufacturing a semiconductor device of the present invention, before an organic insulating film, which becomes an inter-wiring insulating film, is formed, a via hole is formed by etching an inorganic insulating film, which becomes an inter-via layer insulating film. Therefore, a hard mask is not needed for patterning a via hole, and the number of times a hard mask is exposed to the etching gas can be reduced. Thus, a facet and a retrograde of a hard mask can be inhibited, and the wiring can be sized at a desired design value. Therefore, reliability and yield can be improved.  
         [0013]     These and other objects, features, aspects, and advantages of the present invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses a preferred embodiment of the present invention.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     Referring now to the attached drawings which form a part of this original disclosure:  
         [0015]      FIGS. 1A through 1H  are views of diagrams showing a process of manufacturing a semiconductor device in accordance with a first embodiment of the present invention;  
         [0016]      FIGS. 2A through 2H  are views of diagrams showing a process of manufacturing a semiconductor device in accordance with a second embodiment of the present invention;  
         [0017]      FIGS. 3A through 3I  are views of diagrams showing a process of manufacturing a semiconductor device in accordance with a third embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0018]     Selected embodiments of the present invention will now be explained with reference to the drawings. It will be apparent to those skilled in the art from this disclosure that the following descriptions of the embodiments of the present invention are provided for illustration only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.  
         [0019]     Referring now to the drawings, preferred embodiments of the present invention will be described in detail.  
       First Embodiment  
       [0020]      FIGS. 1A  though  1 H are cross-section diagrams to explain a method for manufacturing a semiconductor device with a dual damascene structure in accordance with the first embodiment of the present invention.  
         [0021]     First, as shown in  FIG. 1A , a semiconductor substrate  100  is prepared. The semiconductor substrate  100  has an electronic circuit (not shown in the diagram) formed by a semiconductor element such as a transistor on its main surface. Then, an insulating film  101  is formed on the semiconductor substrate  100 , and a lower layer wiring  102 , which is made of Cu, is formed on the insulating film  101 . Next, a diffusion barrier film  103  is formed on the lower layer wring  102 . For example, the diffusion barrier film  103  is made of a silicon nitride film and its thickness is set to be 500 Å. The diffusion barrier film  103  protects diffusion of Cu, which is the material of the lower layer wiring  102 , and functions as an etching stopper layer with respect to the lower layer wiring  102 . Also, the diffusion barrier film  103  is not necessarily required in the method of manufacturing a semiconductor device in accordance with the first embodiment of the present invention. For example, the diffusion barrier film  103  does not have to be formed, if the etch selectivity between the lower layer wiring  102  and an inorganic insulating film  104  (i.e., an object of an etching) can be set to be a larger value in the process of forming a via hole  106  by etching in the process shown below in  FIG. 1C . Next, the inorganic insulating film  104  is formed. The inorganic insulating film  104  becomes a inter-via layer insulating film in which a via hole  106  is formed in a process shown below in  FIG. 1C . For example, the inorganic insulating film  104  is made of methyl-silsequioxane (MSQ) film and its thickness is set to be 3000 Å. For example, a MSQ film can be formed with a method of spin-coating an MSQ substance and hardening it with a heat treatment in an inert gas atmosphere such as N 2 . The MSQ film is a type of inorganic low-k film, and its relative dielectric constant (k) is low (k=2.7˜2.9). Therefore, the inter-wiring capacitance can be reduced by using the MSQ film as the inorganic insulating film  104 . Also, a hydrogen-silsequioxane (HSQ) film can be used as a substance of the inorganic insulating film  104 , instead of the MSQ film.  
         [0022]     Next, as shown in  FIG. 1B , a resist is applied on the inorganic insulating film  104  and a resist pattern  105  with an opening  105   a  is formed by photolithoetching the resist. For example, the diameter of the opening  105   a  is set to be 0.12 μm.  
         [0023]     Next, as shown in  FIG. 1C , a via hole  106  is formed by etching the inorganic insulating film  104  with the resist pattern  105  as an etching mask. The diameter of the via hole  106  is as large as that of the opening  105   a , and it is set to be 0.12 μm, for instance. For example, in etching the inorganic insulating film  104 , octafluocyclobutane (C 4 F 8 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas. The etching conditions are set as follows. That is, the gas flow rate (sccm) of C 4 F 8 , O 2 , and Ar are set to be 20, 10, and 500 respectively, and the RF Power is set to be 1.5 kW, and the chamber pressure is set to be 40 mTorr. In the process of etching the inorganic insulating film  104  to form the via hole  106 , the diffusion barrier film  103  functions as an etching stopper layer toward the lower layer wiring  102 . Therefore, the lower layer wiring  102  is not etched. Next, the resist pattern  105  is eliminated with ashing.  
         [0024]     Next, as shown in  FIG. 1D , an organic insulating film  107  is formed so that it covers the inorganic insulating film  104  and the inside of the via hole  106 . The organic insulating film  107  becomes an inter-wiring layer insulating film in which a wiring groove is formed in a process shown below in  FIG. 1F . For example, the organic insulating film  107  is made of silicon low-k polymer (SiLK™ of Dow Chemical Company), and its thickness is set to be 3000 Å. The silicon low-k polymer film can be formed by spin-coating the silicon low-k polymer substance and hardening it with a heat treatment in an inert gas atmosphere, such as N 2 , for instance. The silicon low-k polymer film is a type of organic low-k film, and its relative dielectric constant is low (k=2.6˜2.8). Therefore, the inter-wiring capacitance can be reduced by using the silicon low-k polymer as the organic insulating film  107 . Also, GX-3™ of Honeywell International Inc. can be used as the material of the organic insulating film  107 , instead of using SiLK™. Next, a silicon dioxide film, which becomes a hard mask  108 , is formed with the chemical vapor deposition (CVD) method. Here, the thickness of the hard mask  108  is set so that its designated thickness can remain even after the diffusion barrier film  103  is eliminated with an etching in a process shown below in  FIG. 1G .  
         [0025]     Next, a resist is applied on the hard mask  108 , and a resist pattern  109  with an opening  109   a  is formed with photolithoetching, as shown in  FIG. 1E . Next, a hard mask  108   a  is formed by etching a silicon dioxide film (the hard mask  108 ) with the resist pattern  109  as an etching mask. For example, in etching the hard mask  108 , octafluocyclobutane (C 4 F 8 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas. The etching conditions are set as follows. That is, the gas flow rate (sccm) of C 4 F 8 , O 2 , and Ar are set to be 20, 10, and 500 respectively, and the RF Power is set to be 1.5 kW, and the chamber pressure is set to be 40 mTorr.  
         [0026]     Next, as shown in  FIG. 1F , a wiring groove  110  is formed by etching the organic insulating film  107  with the resist pattern  109  and the hard mask pattern  108   a  as etching masks. Also, a via hole  106  is exposed by eliminating the organic insulating film  107  that is implanted in the via hole  106 . For example, in etching the organic insulating film  107 , ammonia (NH 3 ) is used as the etching gas. The etching conditions are set as follows. That is, the gas flow rate of NH 3  is set to be 100 sccm, and the RF Power is set to be 500 W, and the chamber pressure is set to be 60 mTorr. Also, in this etching process, the resist pattern  109  can also be eliminated simultaneously. This is because the resist pattern  109  and the organic insulating film  107  (the SiLK™ film) are made of an organic substance. Because of this, an ashing treatment to eliminate the resist pattern  109  is not required. Therefore, the number of processes required for the method for manufacturing a semiconductor device can be reduced. Also, the hard mask pattern  108   a  is covered with the resist pattern  109  throughout the etching process. Because of this, it is possible to prevent the etching gas from causing the facet and the retrograde of the hard mask  108   a.    
         [0027]     Next, as shown in  FIG. 1G , a portion of the diffusion barrier film  103  made of a silicon nitride film, which is exposed at the bottom of the via hole  106 , is eliminated. For example, in etching the diffusion barrier film  103 , trifluoromethane (CHF 3 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas. The etching conditions are set as follows. That is, the gas flow rate (sccm) of CHF 3 , O 2 , and Ar are set to be 30, 2, and 150 respectively, and the RF Power is set to be 800 W, and the chamber pressure is set to be 30 mTorr. In the process of etching the diffusion barrier film  103 , the hard mask pattern  108   a , which is made of a silicon dioxide film, is simultaneously etched to the designated thickness.  
         [0028]     Next, as shown in  FIG. 1H , a barrier layer  111 , which blocks invasion of Cu, and a seed layer  112  are sequentially formed so that they can cover the inside surface of the via hole  106  and the wiring groove  110 . The barrier layer  111  is a laminated layer that is made of tantalum (Ta) and tantalum nitride (TaN). The layers of the barrier layer  111  are sequentially comprised of a Ta layer, a TaN layer, and a Ta layer. The thickness (Å) of the Ta layer, the TaN layer, and the Ta layer are set to be 50, 400, 50, respectively. Also, the seed layer  112  is made of Cu and its thickness is set to be 1000 Å, for instance. Next, Cu is implanted into the via hole  106  and the wiring groove  110  with the electrolytic plating method, and the excess portion of the implanted Cu is eliminated with the CMP method. Thus, a via plug  113  and an upper layer wiring  114 , which are made of Cu, are simultaneously formed.  
         [0029]     In the first embodiment of the present invention, a method was described in which a dual damascene structure is formed between the first wiring layer (i.e., the lower layer wiring  102 ) on the semiconductor substrate (i.e., the semiconductor substrate  100 ) and the second wiring layer (i.e., the upper layer wiring  114 ). However, it is possible to form the dual damascene structure of the embodiment between other layers, and a desired multi-layer wiring structure can be formed by conducting the process described in  FIGS. 1A through 1H  repeatedly.  
         [0030]     According to the method for manufacturing a semiconductor device of the first embodiment of the present invention, as shown in  FIG. 1C , the via hole  106  is formed by etching the inorganic insulating film  104  that becomes the inter-via layer insulating film, before the organic insulating film  107  that becomes an inter-wiring layer insulating film is formed. Therefore, a hard mask is not required to conduct a patterning of the via hole  106 , and the number of times the hard mask is exposed to the etching gas can be reduced. Because of this, the facet and the retrograde of the hard mask pattern  108   a  are inhibited, the wiring can be sized at the desired design value, and reliability and yield can be improved. Also, as shown in  FIG. 1F , in the process of forming the wiring groove  110  and the via hole  106  by eliminating the organic insulating film  107  by etching, the hard mask pattern  108   a  is covered with the resist pattern  109  throughout the etching process. Therefore, the facet and the retrograde of the hard mask pattern by the etching gas can be inhibited. Also, the resist pattern  109  can be used for patterning the hard mask pattern  108   a  as shown in  FIG. 1E , and also can be used as an etching protective film of the hard mask pattern  108   a  at the same time as shown in  FIG. 1F . Because of this, it is not required to form a dummy film (e.g., a second hard mask pattern) to protect the hard mask pattern  108   a , and the number of steps in the process of manufacturing a semiconductor device and the cost thereof can be reduced. Also, as shown in  FIG. 1F , in the process of forming the wiring groove  110  and the via hole  106  by eliminating the organic insulating film  107  by etching, the resist pattern  109  can also be eliminated at the same time, because the resist pattern  109  is made of an organic substance, as with the organic insulating film  107  that is made of the SiLK™ film. Therefore, it is not required to conduct an ashing treatment to eliminate the resist pattern  109 , and the number of steps in the process of manufacturing a semiconductor device and manufacturing cost thereof can be reduced.  
       Second Embodiment  
       [0031]      FIGS. 2A  though  2 H are cross-section diagrams to explain a method for manufacturing a semiconductor device with a dual damascene structure in accordance with the second embodiment of the present invention.  
         [0032]     First, as shown in  FIG. 2A , a semiconductor substrate  200  is prepared. The semiconductor substrate  200  has an electronic circuit (not shown in the diagram) formed by a semiconductor element such as a transistor on its main surface. Then, an insulating film  201  is formed on the semiconductor substrate  200 , and a lower layer wiring  202 , which is made of Cu, is formed on the insulating film  201 . Next, a diffusion barrier film  203  is formed on the lower layer wring  202 . For example, the diffusion barrier film  203  is made of a silicon nitride film and its thickness is set to be 500 Å. The diffusion barrier film  203  protects diffusion of Cu, which is the material of the lower layer wiring  202 , and functions as an etching stopper layer with respect to the lower layer wiring  202 . Also, the diffusion barrier film  203  is not necessarily required in the method of manufacturing a semiconductor device in accordance with the second embodiment of the present invention. For example, the diffusion barrier film  203  does not have to be formed, if the etch selectivity between the lower layer wiring  202  and an inorganic insulating film  204  (i.e., an object of an etching) can be set to be a larger value in the process of forming a via hole  206  by etching in the process shown below in  FIG. 2C . Next, the inorganic insulating film  204  is formed. The inorganic insulating film  204  becomes a inter-via layer insulating film in which a via hole  206  is formed in a process shown below in  FIG. 2C . For example, the inorganic insulating film  204  is made of methyl-silsequioxane (MSQ) film and its thickness is set to be 3000 Å. For example, a MSQ film can be formed with a method of spin-coating an MSQ substance and hardening it with a heat treatment in an inert gas atmosphere such as N 2 . The MSQ film is a type of inorganic low-k film, and its relative dielectric constant (k) is low (k=2.7˜2.9). Therefore, the inter-wiring capacitance can be reduced by using the MSQ film as the inorganic insulating film  204 . Also, a hydrogen-silsequioxane (HSQ) film can be used as a substance of the inorganic insulating film  204 , instead of using the MSQ film.  
         [0033]     Next, as shown in  FIG. 2B , a resist is applied on the inorganic insulating film  204  and a resist pattern  205  with an opening  205   a  is formed by photolithoetching the resist. For example, the diameter of the opening  205   a  is set to be 0.12 μm.  
         [0034]     Next, as shown in  FIG. 2C , a via hole  206  is formed by etching the inorganic insulating film  204  with the resist pattern  205  as an etching mask. The diameter of the via hole  206  is as large as that of the opening  205   a , and it is set to be 0.12 μm, for instance. For example, in etching the inorganic insulating film  204 , octafluocyclobutane (C 4 F 8 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas. The etching conditions are set as follows. That is, the gas flow rate (sccm) of C 4 F 8 , O 2 , and Ar are set to be 20, 10, and 500 respectively, and the RF Power is set to be 1.5 kW, and the chamber pressure is set to be 40 mTorr. Next, the resist pattern  205  is eliminated with ashing.  
         [0035]     Next, as shown in  FIG. 2D , an organic insulating film  207  is formed so that it covers the inorganic insulating film  204  and the inside of the via hole  206 . The organic insulating film  207  becomes an inter-wiring layer insulating film in which a wiring groove  211  is formed in a process shown below in  FIG. 2F . For example, the organic insulating film  207  is made of silicon low-k polymer (SiLK™ of Dow Chemical Company), and its thickness is set to be 3000 Å. The silicon low-k polymer film can be formed by spin-coating the silicon low-k polymer substance and hardening it with a heat treatment in an inert gas atmosphere, such as N 2 , for instance. The silicon low-k polymer film is a type of organic low-k film, and its relative dielectric constant is low (k=2.6˜2.8). Therefore, the inter-wiring capacitance can be reduced by using the silicon low-k polymer as the organic insulating film  207 . Also, GX-3™ of Honeywell International Inc. can be used as the material of the organic insulating film  207 , instead of using the SiLK™. Next, a silicon dioxide film that becomes a hard mask  208  and a silicon nitride film that becomes an upper layer hard mask  209  are sequentially formed with the chemical vapor deposition (CVD) method. For example, the thickness of the silicon dioxide film that becomes a lower layer hard mask  208  is set to be 500 Å. Also, the thickness of the silicon nitride film that becomes an upper layer hard mask  209  is set to be the same value with that of the diffusion barrier film  203 . For example, the thickness is set to be 500 Å.  
         [0036]     Next, a resist is applied on the upper layer hard mask  209 , and a resist pattern  210  with an opening  210   a  is formed with photolithoetching, as shown in  FIG. 2E . Next, an upper layer hard mask pattern  209   a  and a lower layer hard mask pattern  208   a  are formed by etching a silicon dioxide film (i.e., the upper layer hard mask  209 ) and a silicon dioxide film (i.e., the lower layer hard mask  208 ) sequentially with the resist pattern  210  as an etching mask. For example, in etching the upper layer hard mask  209 , trifluoromethane (CHF 3 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas. The etching conditions are set as follows. That is, the gas flow rate (sccm) of CHF 3 , O 2 , and Ar are set to be 30, 2, and 150 respectively, and the RF Power is set to be 800 W, and the chamber pressure is set to be 30 mTorr. Also, in etching the lower layer hard mask  208 , octafluocyclobutane (C 4 F 8 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas. The etching conditions are set as follows. That is, the gas flow rate (sccm) of C 4 F 8 , O 2 , and Ar are set to be 20, 10, and 500 respectively, and the RF Power is set to be 1.5 kW, and the chamber pressure is set to be 40 mTorr.  
         [0037]     Next, as shown in  FIG. 2F , a wiring groove  211  is formed by etching the organic insulating film  207  with the resist pattern  210 , the upper layer hard mask pattern  209   a , and the lower layer hard mask pattern  208   a  as etching masks. Also, a via hole  206  is exposed by eliminating the organic insulating film  207  that is implanted in the via hole  206 . For example, in etching the organic insulating film  207 , ammonia (NH 3 ) is used as the etching gas. The etching condition is set as follows. That is, the gas flow rate of NH 3  is set to be 100 sccm, and the RF Power is set to be 500 W, and the chamber pressure is set to be 60 mTorr. Also, in this etching process, the resist pattern  210  can also be eliminated simultaneously. This is because the resist pattern  210  and the organic insulating film  207  (the SiLK™ film) are made of an organic substance. Because of this, an ashing treatment to eliminate the resist pattern  210  is not required, and the number of processes required for the method for manufacturing a semiconductor device can be reduced. Also, the upper layer hard mask pattern  209   a  and the lower layer hard mask pattern  208   a  are covered with the resist pattern  209  throughout the etching process. Because of this, it is possible to prevent the etching gas from causing the facet and the retrograde of the upper layer hard mask pattern  209   a  that is made of a silicon nitride film.  
         [0038]     Next, as shown in  FIG. 2G , the upper layer hard mask pattern  209   a  made of a silicon nitride film is eliminated by etching, and a portion of the diffusion barrier film  203  made of a silicon nitride film, which is exposed at the bottom of the via hole  206 , is simultaneously eliminated in this etching. For example, in etching the diffusion barrier film  203 , trifluoromethane (CHF 3 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas. The etching conditions are set as follows. That is, the gas flow rate (sccm) of CHF 3 , O 2 , and Ar are set to be 30, 2, and 150 respectively, and the RF Power is set to be 800 W, and the chamber pressure is set to be 30 mTorr.  
         [0039]     Next, as shown in  FIG. 2H , a barrier layer  212 , which blocks invasion of Cu, and a seed layer  213  are sequentially formed so that they can cover the inside surface of the via hole  206  and the wiring groove  211 . The barrier layer  212  is a laminated layer that is made of tantalum (Ta) and tantalum nitride (TaN). The layers of the barrier layer  212  are sequentially comprised of a Ta layer, a TaN layer, and a Ta layer. The thickness (Å) of the Ta layer, the TaN layer, and the Ta layer are set to be 50, 400, 50, respectively. Also, the seed layer  213  is made of Cu and its thickness is set to be 1000 Å, for instance. Next, Cu is implanted into the via hole  206  and the wiring groove  211  with the electrolytic plating method, and the excess portion of the implanted Cu is eliminated with the CMP method. Thus, a via plug  214  and an upper layer wiring  215 , which are made of Cu, are simultaneously formed.  
         [0040]     In the second embodiment of the present invention, a method is described in which a dual damascene structure is formed between the first wiring layer (i.e., the lower layer wiring  202 ) on the semiconductor substrate (i.e., the semiconductor substrate  200 ) and the second wiring layer (i.e., the upper layer wiring  215 ). However, it is possible to form the dual damascene structure of the embodiment between other layers, and a desired multi-layer wiring structure can be formed by conducting the process described in  FIGS. 2A through 2H  repeatedly.  
         [0041]     The method for manufacturing a semiconductor device of the second embodiment of the present invention has the same effects of the first embodiment of the present invention. That is, as shown in  FIG. 2C , the via hole  206  is formed by etching the inorganic insulating film  204  that becomes the inter-via layer insulating film, before the organic insulating film  207  that becomes an inter-wiring layer insulating film is formed. Therefore, a hard mask is not required to conduct a patterning of the via hole  206 , and the number of times the hard mask is exposed to the etching gas can be reduced. Because of this, the facet and the retrograde of a hard mask, especially of the hard mask pattern  209   a  that is made of a silicon nitride film, are inhibited, the wiring can be sized at the desired design value, and reliability and yield can be improved. Also, as shown in  FIG. 2F , in the process of forming the wiring groove  211  and the via hole  206  by eliminating the organic insulating film  207  with etching, the upper layer hard mask pattern  209   a  and the lower layer hard mask pattern  208   a  are covered with the resist pattern  210  throughout the etching process. Therefore, the facet and the retrograde of the hard mask pattern by the etching gas can be inhibited. Also, the resist pattern  210  can be used for patterning the upper layer hard mask pattern  209   a  and the lower layer hard mask pattern  208   a  as shown in  FIG. 2E , and also can be used as an etching protective film of the upper layer hard mask pattern  209   a  and the lower layer hard mask pattern  208   a  at the same time as shown in  FIG. 2F . Because of this, it is not required to form a dummy film (e.g., a third hard mask pattern) to protect the upper layer hard mask pattern  209   a  and the lower layer hard mask pattern  208   a , and the number of steps in the process of manufacturing a semiconductor device and the cost thereof can be reduced. Also, as shown in  FIG. 2F , in the process of forming the wiring groove  211  and the via hole  206  by eliminating the organic insulating film  207  with etching, the resist pattern  210  can also be eliminated at the same time, because the resist pattern  210  is made of an organic substance, as with the organic insulating film  207  that is made of the SiLK™ film. Therefore, it is not required to conduct an ashing treatment to eliminate the resist pattern  210 , and the number of steps in the process of manufacturing a semiconductor device and the manufacturing cost thereof can be reduced.  
       Third Embodiment  
       [0042]      FIGS. 3A  though  3 H are cross-section diagrams to explain a method for manufacturing a semiconductor device with a dual damascene structure in accordance with the third embodiment of the present invention.  
         [0043]     First, as shown in  FIG. 3A , a semiconductor substrate  300  is prepared. The semiconductor substrate  300  has an electronic circuit (not shown in the diagram) formed by a semiconductor element such as a transistor on its main surface. Then, an insulating film  301  is formed on the semiconductor substrate  300 , and a lower layer wiring  302 , which is made of Cu, is formed on the insulating film  301 . Next, a diffusion barrier film  303  is formed on the lower layer wring  302 . For example, the diffusion barrier film  303  is made of a silicon nitride film and its thickness is set to be 500 Å. The diffusion barrier film  303  protects diffusion of Cu, which is the material of the lower layer wiring  302 , and functions as an etching stopper layer with respect to the lower layer wiring  302 . Also, the diffusion barrier film  303  is not necessarily required in the method of manufacturing a semiconductor device in accordance with the third embodiment of the present invention. For example, the diffusion barrier film  303  does not have to be formed, if the etch selectivity between the lower layer wiring  302  and an organic insulating film  304  (i.e., an object of an etching) can be set to be a larger value in the process of forming a via hole  306  by etching in the process shown below in  FIG. 3C . Next, the organic insulating film  304  is formed. The organic insulating film  304  becomes a inter-via layer insulating film in which a via hole  306  is formed in a process shown below in  FIG. 3C . For example, the organic insulating film  304  is made of a SiLK™ film and its thickness is set to be 3000 Å. For example, a SiLK™ film can be formed with a method of spin-coating a SiLK™ substance and hardening it with a heat treatment in an inert gas atmosphere such as N 2 . The SiLK™ film is a type of organic low-k film, and its relative dielectric constant (k) is low (k=2.6˜2.8). Therefore, the inter-wiring capacitance can be reduced by using the SiLK™ film as the organic insulating film  304 . Also, a GX-3™ film can be used as the material of the organic insulating film  304 , instead of the SiLK™ film.  
         [0044]     Next, as shown in  FIG. 3B , a resist is applied on the organic insulating film  304  and a resist pattern  305  with an opening  305   a  is formed by photolithoetching the resist. For example, the diameter of the opening  305   a  is set to be 0.12 μm.  
         [0045]     Next, as shown in  FIG. 3C , a via hole  306  is formed by etching the organic insulating film  304  with the resist pattern  305  as an etching mask. The diameter of the via hole  306  is as large as that of the opening  305   a , and it is set to be 0.12 μm, for instance. For example, in etching the organic insulating film  304 , ammonia (NH 3 ) is used as the etching gas. The etching conditions are set as follows. That is, the gas flow rate of NH 3  is set to be 100 sccm, and the RF Power is set to be 500 W, and the chamber pressure is set to be 60 mTorr. In this etching process, the resist pattern  305  can also be eliminated, because the resist pattern  305  is made of an organic substance as with the SiLK™ film that comprises the organic insulating film  304 . Because of this, an ashing treatment is not required to eliminate the resist pattern  305  and the number of manufacturing processes of a semiconductor device can be reduced.  
         [0046]     As shown in  FIG. 3D , a portion of the diffusion barrier film  303  made of a silicon nitride film, which is exposed at the bottom of the via hole, is eliminated. For example, in etching the diffusion barrier film  303 , trifluoromethane (CHF 3 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas. The etching conditions are set as follows. That is, the gas flow rate (sccm) of CHF 3 , O 2 , and Ar are set to be 30, 2, and 150 respectively, and the RF Power is set to be 800 W, and the chamber pressure is set to be 30 mTorr. Also, in this etching process, a surface modification layer  307  is formed by modifying the surface of the organic insulating film  304  that is made of the organic SiLK™ film with a plasma treatment. The surface modification layer  307  has the effect of enhancing its adhesiveness with an inorganic insulating film  308  formed in a process shown below in  FIG. 3E .  
         [0047]     Next, as shown in  FIG. 3E , the inorganic insulating film  308  is formed so that it covers the organic insulating film  304  and the inside of the via hole  306 . The inorganic insulating film  308  becomes an inter-wiring layer insulating film in which a wiring groove  312  is formed in a process shown below in  FIG. 3H . For example, the inorganic insulating film  308  is made of a methyl-silsequioxane (MSQ) film and its thickness is set to be 3000 Å. For example, a MSQ film can be formed with a method of spin-coating a MSQ substance and hardening it with a heat treatment in an inert gas atmosphere such as N 2 . The MSQ film is a type of inorganic low-k film, and its relative dielectric constant (k) is low (k=2.7˜2.9). Therefore, the inter-wiring capacitance can be reduced by using the MSQ film as the inorganic insulating film  308 . Also, a hydrogen-silsequioxane (HSQ) film can be used as the material of the inorganic insulating film  308 , instead of the MSQ film. Next, a silicon dioxide film that becomes a lower layer hard mask  309  and a silicon nitride film that becomes an upper layer hard mask  310  are sequentially formed. For example, the thickness of the silicon dioxide film that becomes the lower layer hard mask  309  is set to be 500 Å. Also, the thickness of the silicon nitride film that becomes the upper layer hard mask  310  is set to be that of the diffusion barrier film  303 , for example, 500 Å.  
         [0048]     Next, a resist is applied on the upper layer hard mask  310 , and a resist pattern  311  with an opening  311   a  is formed with photolithoetching, as shown in  FIG. 3F . Next, an upper layer hard mask pattern  310   a  and a lower layer hard mask pattern  309   a  are formed by etching a silicon nitride film (i.e., the upper layer hard mask  310 ) and a silicon dioxide film (i.e., the lower layer hard mask  309 ) with the resist pattern  311  as an etching mask. For example, in etching the upper layer hard mask  310 , trifluoromethane (CHF 3 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas. The etching conditions are set as follows. That is, the gas flow rate (sccm) of CHF 3 , O 2 , and Ar are set to be 30, 2, and 150 respectively, and the RF Power is set to be 800 W, and the chamber pressure is set to be 30 mTorr. For example, in etching the lower layer hard mask  309 , octafluocyclobutane (C 4 F 8 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas. The etching conditions are set as follows. That is, the gas flow rate (sccm) of C 4 F 8 , O 2 , and Ar are set to be 20, 10, and 500 respectively, and the RF Power is set to be 1.5 kW, and the chamber pressure is set to be 40 mTorr.  
         [0049]     Next, as shown in  FIG. 3G , the resist pattern  311  is eliminated with an ashing treatment. In a process shown below in  FIG. 3H , if an ashing treatment is conducted for the resist pattern  311  after the formation of the inorganic insulating film  308  made of the MSQ film, there is a possibility that the lower layer wiring  302 , which is made of Cu and exposed at the bottom of the via hole  306 , will be damaged. Therefore, damage of the lower layer wiring by this ashing treatment is prevented by eliminating the resist pattern  311 .  
         [0050]     Next, as shown in  FIG. 3H , a wiring groove  312  is formed by etching the inorganic insulating film  308  with the upper layer hard mask pattern  310   a  and the lower layer hard mask pattern  309   a  as etching masks. Also, a via hole  306  is exposed by eliminating the inorganic insulating film  308  that is implanted in the via hole  306 . For example, in etching the inorganic insulating film  308 , octafluocyclobutane (C 4 F 8 ), oxygen (O 2 ), and argon (Ar) are used as the etching gas. The etching conditions are set as follows. That is, the gas flow rate (sccm) of C 4 F 8 , O 2 , and Ar are set to be 20, 10, and 500 respectively, and the RF Power is set to be 1.5 kW, and the chamber pressure is set to be 40 mTorr. Also, in this etching process, the upper layer hard mask pattern  310   a  made of a silicon nitride film can also be eliminated simultaneously. Also, in this etching process, the value of the etch selectivity between the inorganic insulating film  308  made of the MSQ film and the organic insulating film  304  made of the SiLK™ film is more than 50. Therefore, only the inorganic insulating film  308  made of the MSQ film can be effectively eliminated.  
         [0051]     Next, as shown in  FIG. 3I , a barrier layer  313 , which blocks invasion of Cu, and a seed layer  314  are sequentially formed, so that they can cover the inside surface of the via hole  306  and the wiring groove  312 . The barrier layer  313  is a laminated layer that is made of tantalum (Ta) and tantalum nitride (TaN). The layers of the barrier layer  313  are sequentially comprised of a Ta layer, a TaN layer, and a Ta layer. The thickness (Å) of the Ta layer, the TaN layer, and the Ta layer are set to be 50, 400, 50, respectively. Also, the seed layer  314  is made of Cu and its thickness is set to be 1000 Å, for instance. Next, Cu is implanted into the via hole  306  and the wiring groove  312  with the electrolytic plating method, and the excess portion of the implanted Cu is eliminated with the CMP method. Thus, a via plug  315  and an upper layer wiring  316 , which are made of Cu, are simultaneously formed.  
         [0052]     In the third embodiment of the present invention, a method is described in which a dual damascene structure is formed between the first wiring layer (i.e., the lower layer wiring  302 ) on the semiconductor substrate (i.e., the semiconductor substrate  300 ) and the second wiring layer (i.e., the upper layer wiring  316 ). However, it is possible to form the dual damascene structures of the embodiment between other layers, and a desired multi-layer wiring structure can be formed by conducting the process described in  FIGS. 3A through 3I  repeatedly.  
         [0053]     According to the method for manufacturing a semiconductor device of the third embodiment of the present invention, as shown in  FIG. 3C , the via hole  306  is formed by etching the organic insulating film  304  that becomes an inter-via layer insulating film, before the inorganic insulating film  308  that becomes an inter-wiring layer insulating film is formed. Therefore, a hard mask is not required to conduct a patterning of the via hole  306 , and the number of times the hard mask is exposed to the etching gas can be reduced. Because of this, the facet and the retrograde of the upper layer hard mask pattern  310   a  made of a silicon nitride film are inhibited, the wiring size can be formed at the desired design value, and reliability and yield can be improved. Also, in a process of eliminating the diffusion barrier film  303  that is exposed at the bottom of the via hole  306  shown in  FIG. 3D , the surface modification layer  307  is formed by modifying the surface of the organic insulating film  304  made of the organic SiLK™ film with a plasma treatment. Therefore, its adhesiveness with an inorganic insulating film  308  formed on the organic insulating film can be enhanced, and reliability and yield can be improved. Also, as shown in  FIG. 3C , in the process of forming the via hole  306  by eliminating the organic insulating film  304  by etching, the resist pattern  305  can also be eliminated at the same time, because the resist pattern  305  is made of an organic substance, as with the organic insulating film  304  that is made of the SiLK™ film. Therefore, it is not required to conduct an ashing treatment to eliminate the resist pattern  305 , and the number of steps in the process of manufacturing a semiconductor device and the manufacturing cost thereof can be reduced.  
         [0054]     This application claims priority to Japanese Patent Application No. 2004-368064. The entire disclosure of Japanese Patent Application No. 2004-368064 is hereby incorporated herein by reference.  
         [0055]     The terms of degree such as “nearly” used herein mean a reasonable amount of deviation of the modified term such that the end result is not significantly changed. For example, the terms can be construed as including a deviation of at least ±5% of the modified term if this deviation would not negate the meaning of the word it modifies.  
         [0056]     While only selected embodiments have been chosen to illustrate the present invention, it will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made herein without departing from the scope of the invention as defined in the appended claims. Furthermore, the foregoing descriptions of the embodiments according to the present invention are provided for illustration only, and not for the purpose of limiting the invention as defined by the appended claims and their equivalents. Thus, the scope of the invention is not limited to the disclosed embodiments.