Abstract:
A complementary waveform driver is disclosed that generates output signals S OUT  with arbitrary high and low drive states with respect to an independently controlled baseline signal S BL . Accordingly, the driver can generate very fast and flexible waveforms with multiple levels and baseline components. The driver implements complementary differential pairs of transistors that alternately source and sink programmable currents to an output port, creating an output waveform with excellent rising and falling edge symmetry, and greatly improved fidelity, especially at low level voltage swings. A complementary amplifier stage defines the baseline voltage level. When combined with a programmable active load and window comparator, the driver is particularly suited for pin electronics in automatic test equipment (ATE) applications.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to waveform drivers and, more particularly, to their use in pin electronics for automatic test equipment (ATE). 
     2. Description of the Related Art 
     An exemplary use of transistor waveform drivers can be found in the field of ATE where test waveforms are generated and applied to leads of devices under test (DUTs). Because these waveforms are typically applied via an ATE “pin” (i.e., a probe), circuits configured for this purpose are also referred to as “pin drivers” and comprise a more general class of support circuitry commonly referred to as ATE “pin electronics”. Preferably, the magnitudes and baseline components of pin-driver waveforms can be individually adjusted over ranges that accommodate a variety of DUTs and, in addition, the waveforms should have fast, symmetric rising and falling edges with minimal transients. Because ATE systems typically employ a large number (e.g., 1024) of pin drivers, the drivers are preferably realized with simple, inexpensive circuits. 
     A first exemplary pin driver is shown in U.S. Pat. No. 4,572,971 to couple a level selector circuit to a DUT with a buffer circuit. The level selector circuit is arranged to accommodate reference voltages that represent both small and large voltage swings. In response to first and second reference voltages and a current switch, the level selector circuit generates a signal equal to a selected one of the reference voltages at an output node. The output node signals are applied to the DUT through a unity-gain buffer circuit having two stages that each comprise a complementary emitter follower. 
     A second exemplary pin driver is disclosed in U.S. Pat. No. 5,842,155 which couples a pulse forming circuit to a DUT with buffer and amplifier stages. The pulse forming network responds to high and low signal inputs by respectively charging and discharging a network node with currents of equal and opposite magnitudes so as to achieve pulses having equal positive and negative slew rates between pulse magnitudes equal to the high and low inputs. The pulses thus formed at the network node are then applied to the DUT through unity-gain buffer and amplifier stages which each comprise a complementary emitter follower structure. 
     Although these exemplary pin drivers can generate pulse signals with controlled amplitudes, they fail to provide for independent adjustment of a baseline component and are relatively complex (e.g., the pulse forming circuit and buffer and amplifier stages of U.S. Pat. No. 5,842,155 include 11 transistors and the components of U.S. Pat. No. 4,572,971 are even more numerous. 
     FIG. 1A shows another pin driver  5  that is formed with a buffer amplifier  6 , a differential pair  7  and a resistor  8 . The resistor couples a DUT to the output  9  of the buffer amplifier and a collector of one of the differential pair&#39;s transistors is also coupled to the DUT. A level-controlling signal can then be applied to the input  10  of the buffer amplifier and a data signal (e.g., a digital signal) applied to the differential control terminals  11  of the differential pair. In response to the data signal, the differential pair steers the current  12  of a programmable current source  13  to and away from the collector that is coupled to the DUT. Thus, the level of the signal applied to the DUT can be controlled with the level-controlling signal and its amplitude controlled with the programmed current of the current source. 
     Although this latter pin driver circuit facilitates the automatic control required in ATEs and is much simpler and accordingly less expensive than the first and second exemplary pin drivers, its generated waveforms depart from the desired symmetry and amplitude. For example, FIG. 1B illustrates a typical waveform  14 . The differential pair of the pin driver pulls the programmed current across the resistor ( 8  in FIG. 1A) and, accordingly, the falling edge  15  of the waveform  14  is steep and linear as it descends to the lower waveform level  16 . There is a pronounced overshoot  17 , however, as the falling edge transitions to the lower level  16 . 
     In addition, the rising waveform edge  18  exhibits an exponential characteristic as it returns to the upper level  19  of the waveform  14 . The rising waveform is generated when the differential pair steers the programmed current away from the resistor. Current to bring the waveform to the upper level  19  is then limited by the resistor ( 8  in FIG.  1 A), and the exponential shape results as this current charges stray circuit capacitance (e.g., collector capacitance of the differential pair). 
     It is anticipated that the depth of the lower waveform level  16  is given by the product of the steered current ( 12  in FIG. 1A) and the resistance of the resistor. It has been observed, however, that the lower level typically assumes an error level  16 E that differs from the anticipated level  16 . The error level is generated because the output impedance of the amplifier ( 6  in FIG. 1A) typically has a nonzero value and current flow across this impedance adds an additional error term. Furthermore, this error term has a nonlinear characteristic, making it difficult to correct with conventional system calibration techniques. 
     Because the performance of modern electronic circuits is constantly increasing, there is a demand for test circuits that can generate waveforms whose precision is superior to that of the waveform  14 . In addition to applying test waveforms to DUTs, modern ATEs are also generally required to verify that the DUT can sink or source specified pin currents and to verify that the DUT provides specified response waveforms. To provide these functions at each DUT lead, the respective ATE pin electronics preferably includes a waveform driver, an active load and a comparator. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to waveform driver structures that generate precise, controllable waveforms and is further directed to ATE pin electronics formed with these structures. 
     These goals are realized with an amplifier and complementary-arranged first and second differential pairs of transistors. The first and second pairs are coupled to steer first and second currents to an output port in response to first and second input signals, and the amplifier is coupled to generate a baseline output signal at the output port in response to a baseline input signal. The first and second currents are preferably generated with programmable first and second current sources. 
     In an exemplary operation, all of the first and second currents are sequentially steered to and away from the output port in response to first and second input signals so that upper and lower levels of the output signal are determined by programming the magnitudes of the first and second currents. Thus, a variety of different waveforms can be synthesized in response to the programmed current sources, the first and second input signals, and the baseline input signal. 
     Transients of the generated waveforms are reduced by preferably referencing one input of each of the differential pairs to a fixed reference signal. To further enhance their operation, other waveform drivers of the invention buffer the first and second differential pairs with cascode transistors and include keep-alive current sources to improve dynamic response. To enhance variability of their output signals, other waveform drivers of the invention buffer the first and second differential pairs with inhibit switches formed with inhibit differential pairs. 
     The complementary structure of the waveform drivers generates steep, linear, symmetric waveform edges. In addition, this structure reduces the transistor currents required for a given voltage swing so that device power dissipation is greatly reduced. Accordingly, smaller devices can be used which generally improves waveform fidelity. 
     In another waveform driver embodiment, currents from the first and second differential pairs are coupled into the output of the amplifier to reduce waveform errors caused by the amplifier&#39;s nonzero output impedance. 
     ATE pin electronics of the invention are realized by adding active loads and comparators to the waveform drivers and coupling all of these components to a common pin for interface with DUT leads. 
     The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A illustrates a conventional pin driver; 
     FIG. 1B illustrates a typical waveform generated by the pin driver of FIG. 1A; 
     FIG. 2 is a schematic of a waveform driver embodiment of the present invention; 
     FIGS. 3A-C illustrate exemplary waveforms generated by the waveform driver of FIG. 2; 
     FIG. 4 is a block diagram of an ATE pin electronics embodiment of the present invention; 
     FIG. 5 is a conceptual diagram of a programmable active load for use in the pin electronics of FIG. 4; 
     FIGS. 6,  7  and  8  are schematics of other waveform driver structures of the present invention; 
     FIG. 9 illustrates exemplary waveforms generated by the waveform driver of FIG. 8; 
     FIG. 10 is a schematic of another waveform driver of the present invention; and 
     FIG. 11 illustrates exemplary waveforms generated by the waveform driver of FIG.  10 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2 illustrates a waveform driver embodiment  20  that generates an output signal S OUT  at an output port  22  in independent response to first and second data signals S D1  and S D2  at data input ports  24  and  26  and a baseline signal S BL  at a baseline input port  28 . Because the output signal S OUT  responds independently to these input signals, a variety of different output waveforms can be generated. 
     In particular, a first current source  29  generates a current I 1  whose amplitude responds to a signal S P  and this current source is coupled between a positive supply voltage V CC  and the emitters of a differential pair  30  of transistors  32  and  34 . The base and collector of transistor  32  are coupled respectively to data input port  24  and a negative supply voltage V EE . The base and collector of transistor  34  are coupled respectively to a first reference voltage V REF1  and the output port  22 . 
     In a similar manner, a second current source  49  generates a current I 2  whose amplitude responds to a signal S N  and this current source is coupled between negative supply voltage V EE  and the emitters of a differential pair  50  of transistors  52  and  54 . The base and collector of transistor  52  are coupled respectively to data input port  26  and the positive supply voltage V CC . The base and collector of transistor  54  are coupled respectively to a second reference voltage V REF2  and the output port  22 . 
     An output impedance device in the form of a resistor  58  may be added between a potential  57  (e.g., ground) and the output port  22  and a coupling impedance device in the form of a resistor  56  couples an amplifier  60  to the output port  22 . The input of the amplifier  60  is connected to the baseline input port  28 . 
     In operation of the waveform driver  20 , the differential pair  30  receives a current I 1  of the current source  29  and responds to the first data signal S D1  by steering this current through one or the other of its collectors as indicated by currents  68  and  70 . The output impedance of the amplifier  60  is substantially zero so that the current  70  flows through a parallel impedance (R 56 ∥R 58 ) of the resistors  56  and  58  and generates a positive signal S 1  equal to (current  70 )×(R 56 ∥R 58 ). 
     The differential pair  50  complements the differential pair  30  and responds to the second data signal V D2  by steering currents  78  or  80  through one or the other of its collectors to supply a current I 2  of the current source  49  and thereby generate a negative signal S 2  equal to (current  80 )×(R 56 ∥R 58 ). 
     The amplifier  60  responds to its input signal S BL  by generating an output signal V O  that is related to the baseline signal S BL  by the gain of the amplifier. This gain need not be greater than one, but the amplifier  60  it is preferably a complementary buffer amplifier (i.e., one capable of actively sourcing and sinking currents). 
     The output signal S OUT  at the output port  22 , therefore, is a sum of the signals S 1 , S 2  and V O . Accordingly, the baseline component of the output signal is linearly responsive to the baseline signal S BL  while the output signal is varied in a positive direction in response to the data signal S D1  and varied in a negative direction in response to the data signal S D2 . In a particular case in which the data signals S D1  and S D2  are of equal magnitude but have translated voltage levels, a signal is generated symmetrically at the output port  22  about a signal mid-point that is determined by the baseline signal S BL . 
     Circuit simulations were run on the waveform driver  20  in which realistic circuit parasitics (e.g., capacitances) were assumed. With I 1 =I 2 =500 microamps, S BL =0 and source and load resistances of 50 ohms, the 25 millivolt peak-to-peak waveform  90  of FIG. 3A was generated with steep, linear, symmetric rising and falling edges  92  and  93  between upper and lower levels  94  and  95 . In addition, the waveform  90  exhibited only a slight undershoot  96  at the bottom of the falling edge and a slight overshoot  97  at the top of the rising edge. 
     When I 1  and I 2  were increased to 20 milliamps, the 1000 millivolt peak-to-peak waveform  100  of FIG. 3B was produced. The rising and falling edges  102  and  103  were still steep, linear and symmetric with respective overshoots  104  and  105  that were slightly increased from the overshoot  97  of FIG.  3 A. Although the simulation was based on a baseline component  98  equal to zero volts, the waveforms of FIGS. 3A and 3B can be shifted about various positive and negative baseline levels by appropriate baseline signals S BL  at the baseline input port ( 28  in FIG.  2 ). 
     In the configuration of FIG. 2, all of the current I 1  is typically steered to sequentially form currents  68  and  70 . Thus, the upper level  94  of FIG. 3A is adjusted by programming the magnitude of the current I 2  of FIG.  2 . Similarly, all of the current I 2  is typically steered to sequentially form currents  78  and  80  so that the lower level  95  is adjusted by programming the magnitude of the current I 2  of FIG.  2 . The baseline level of the output signal is responsive to the baseline input signal S BL . 
     The improved waveforms of FIGS. 3A and 3B are realized because of the complementary relationship of the differential pairs  30  and  50  of FIG.  2 . This is illustrated in FIG. 3C which repeats the waveform  14  of FIG. 1B in broken lines. This waveform will be generated at the output port  22  of FIG. 2 with the differential pair  50  in response to an appropriate input pulse at input port  26 . FIG. 3C also shows a broken-line waveform  110  that would be generated at the output port  22  of FIG. 2 with the differential pair  30  in response to the same input pulse at input port  24  (with its level adjusted to account for the difference between reference voltages V REF1  and V REF2 ). 
     For comparison, the waveform  90  of FIG. 3A is superimposed over the waveforms  14  and  110 . It is theorized that the steep falling edge  93  is primarily due to the falling edge ( 15  in FIG. 1B) of the waveform  14  and that the exponential shape  111  of the waveform  110  accounts for the absence in the waveform  90  of the pronounced overshoot ( 17  in FIG. 1B) of the waveform  14 . 
     Similarly, it is theorized that the steep rising edge  92  is primarily due to the rising edge of the waveform  110  and that the exponential shape ( 18  in FIG. 1B) of the waveform  14  causes the waveform  90  to have only a slight overshoot ( 97  in FIG. 3A) at the top of its rising edge. 
     Several other advantageous features are facilitated by the structure of the waveform driver  20 . Transistors  34  and  54  of FIG. 2 generally have parasitic capacitances C p  across their base-collector junctions. It has been found that if the differential pairs  30  and  50  are driven with differential signals, these capacitances act as current pumps to introduce significant transients into the output signal (e.g., at locations  96  and  97  in FIG.  3 A). By coupling the bases of transistors  34  and  54  to fixed reference signals (V REF1  and V REF2  in FIG.  2 ), it has been found that this pumping effect is significantly reduced with consequent reduction of output transients. In this configuration, the transistors  34  and  54  essentially act as cascode transistors that isolate the driver output from the changing input signals S D1  and S D2 . 
     Because the upper and lower signal levels  94  and  95  of FIGS. 3A and 3B are generated with complementary active currents, the magnitude of the currents (I 1  and I 2  in FIG. 2) are one half that required by a conventional class-A driver for a given voltage swing. Accordingly, power dissipation in each of the differential pairs is reduced by a factor of two so that the use of smaller transistors is facilitated. These smaller devices typically have lower parasitic impedances with consequent improvement in waveform fidelity, especially for small output signal swings (e.g., 25 mv). 
     Finally, because components of the output signal respond independently to first and second input signals S D1  and S D2  and an input baseline signal S BL , output signals of various shapes, baseline components, phases and frequencies can be synthesized. 
     FIG. 4 illustrates a pin electronics circuit  120  that combines a programmable active load  122  and a response comparator  124  with the waveform driver  20  of FIG.  2 . The active load positions a diode bridge  126  between programmable current sources  128  and  129 . One side of the bridge is supplied with a commutation voltage V COM  and the other side is coupled to a pin  130  that is configured to contact a DUT component, e.g., a DUT lead. The current sources are arranged to source and sink current to and from the bridge and are typically implemented with current mirrors  132  whose current magnitudes respond to programmable voltages V PROM . 
     The response comparator  124  is typically a window comparator formed with first and second comparators  134  and  136  that each have an input coupled to the pin  130  and another input respectively connected to programmable high and low input reference voltages V H  and V L . Comparator output signals appear at ports Q H  and Q L  and indicate whether DUT response signals are within the range V H -V L  or not. The output port  22  of the waveform driver  20  may be coupled to the output pin  130  by an impedance-matching resistor  138  that reduces reflections of DUT signals as they travel to and from the pin. 
     Because it includes the waveform driver  20 , the comparator  124  and the active load  122 , the pin electronics circuit  120  might also be referred to as a driver/comparator/load or DCL. 
     In its operation, the pin electronics circuit  120  generates and applies test waveforms with its waveform driver  20 , measures DUT response signals with its response comparator  124  and applies specified current sinks or sources with its active load  122 . All of these functions are coupled to a DUT by the pin  130 . The flexible but relatively straightforward structure of the pin electronics circuit  120  facilitates its use in large numbers in ATEs for simultaneous testing of multiple DUT leads. 
     In an exemplary test of a DUT that is to source 1 milliamp while delivering 5 volts at the pin  130 , the current source  129  would be set to sink 1 milliamp and the commutation voltage V COM  set to a voltage less than 5 volts. If the DUT meets its specifications, its source current I S  flows as shown to the current source  129  while a second current I 2  flows from the current source  128  and through the other side of the bridge  126 . If the DUT cannot source the specified 1 milliamp, a third current I 3  flows through diode  142  so that I S +I 3  equals the 1 milliamp sink current of the current source  129 . Because diodes  142  and  144  are now both in conduction, the voltage at the pin  130  must equal V COM . The fact this is below the DUTs specified 5 volts is sensed by the comparator  124 . 
     The teachings of the pin electronics circuit  120  can be practiced with a variety of conventional active loads. For example, FIG. 5 illustrates another active load  150  which couples current sources  152  and  154  to the pin  130  with switches  153  and  155 . The potential of the pin is measured with a comparator  156 . A specified source or sink current can thus be switched to the pin  130  while a DUT voltage at the pin  130  is measured and compared to a specified voltage. 
     In the waveform driver  20  of FIG. 2, the steered currents  68  and  78  return to the power supplies that generate the supply voltages V CC  and V EE . Because this wasted current decreases the efficiency of the driver, it may be preferable to use the waveform driver  200  of FIG.  6 . This driver is similar to the driver  20  of FIG. 2 with like elements indicated by like reference numbers. However, the collector of transistor  32  and the collector of transistor  52  are connected to the output port of the amplifier  60  to increase efficiency. 
     In addition, this arrangement reduces the amplifier&#39;s static current load and enhances waveform accuracy. For example, if the differential pair  50  steers the current  80  across the resistor  56 , the output signal S OUT  falls to a lower level such as the level  16  shown earlier in FIG.  1 B. Although the output impedance of the amplifier  60  can be assumed to be zero for most purposes, it typically has a nonzero value. With reference to FIG. 1B, it was stated above that current flow across this nonzero output impedance introduces an error component so that the waveform floor falls to an error level ( 16 E in FIG.  1 B). 
     In the waveform driver  200 , however, the differential pair  30  steers the current  68  into the output of the buffer amplifier  60  to generate a compensating voltage drop across the nonzero output impedance and this substantially nulls out the error component. Accordingly, the waveform floor will be substantially where it is anticipated to be (i.e, at  16  in FIG.  1 B). In particular, if I 1 =I 2  and the output load impedance (e.g., resistor  58 ) is infinite, then the static current load of the amplifier  60  is zero and error in the lower waveform level is eliminated. 
     The waveform driver  220  of FIG. 7 is similar to the driver  200  of FIG. 6 with like elements indicated by like reference numbers. The driver  220 , however, has diodes  222  coupled between the current source  29  and the emitters of the differential pair  30  and diodes  224  coupled between the current source  49  and the emitters of the differential pair  50 . This facilitates coupling of current sources  226  to the emitters of the differential pair  30  and current sources  228  to the emitters of the differential pair  50 . 
     If the data signals S D1  and S D2  drive the currents  68  and  78  to zero in the driver  20  of FIG. 2, the performance of transistors  32  and  52  is degraded because the unity-gain frequency f T  of transistors drops with lowered currents. This lowering of f T  is mitigated in the waveform driver  220  because these transistors continue to conduct the keep-alive currents of their respective current sources  226  and  228 . Each keep-alive current source is directed into an appropriate transistor by its respective diode. 
     Because they continue to conduct current, and because potentials of their terminals is established at all times, the turn-on response of the transistors  32  and  52  is improved. A similar improvement is realized for transistors  34  and  54  in situations in which currents  70  and  80  would otherwise drop to zero. These circuit structures also improve response performance of the cascode transistors  230 . To further enhance the speed of the waveform driver  220 , the diodes  222  and  224  are preferably Schottky diodes. 
     In the waveform driver  200  of FIG. 6, the transistors of the differential pairs  30  and  50  operate with collector-emitter voltages and collector currents that vary with the signal levels at the output port  22 . Accordingly, the thermal heating of these transistors is a function of signal levels and duty cycles, and this induces differences in their characteristics (e.g., base-to-emitter voltage) and their performance (e.g., turn-on and turn-off times) which may cause the waveform driver to exhibit undesirable traits (e.g., timing skews). 
     Accordingly, the waveform driver  220  also has transistors  230  coupled in cascode configuration (common base) with the collectors of the differential pairs  30  and  50 . The cascode transistors have a reference voltage V R  coupled to their bases which sets a known and unchanging potential at the collectors of the differential pairs  30  and  50 . Because their collector-to-emitter voltages are substantially reduced and are now constant, the thermal variations (and possible degraded performance) of the waveform driver  200  are also substantially reduced. The cascode transistors  230  now differ in their thermal heating but this does not affect driver performance because these transistors are not involved in the steering of currents I 1  and I 2 . 
     FIG. 8 shows a waveform driver  240  that is similar to the driver  200  of FIG. 6 with like elements indicated by like reference numbers. The driver  240  also includes differential pairs  242  that are arranged so that a first transistor  244  of each differential pair acts as the cascode transistor  230  of FIG. 7, and a second bypass transistor  246  of each differential pair is coupled to a potential  247 . 
     The bases of the differential pairs  242  form switch ports  248  at which inhibit signals S I     1    and S I     2    can be applied. In a first polarity mode of the inhibit signals, currents (e.g., the current  78 ) are steered through the first cascode-arranged transistor  244  of each differential pair  242  and in a second polarity mode, currents are steered through the second bypass transistor  246  of each differential pair. 
     In response to the first polarity mode, the waveform driver  240  operates similarly to the waveform driver  200 —the signal at the output port  22  would respond to the baseline input signal at the input port  28  and would also respond to the first and second data signals at the input ports  24  and  26 . 
     In response to the second polarity mode, the steered currents of the differential pairs  30  and  50  flow through the second transistors  246  of each differential pair  242  so that the operational action of the differential pairs  30  and  50  are inhibited. In this inhibited mode, the signal at the output port  22  would only respond to the baseline input signal at the input port  28 . 
     Alternatively, the polarities of the inhibit signals S I     1    and S 2     2    can be opposite so that the output signal at the output port  22  would then respond to the baseline input signal and to one of the first and second data signals. 
     These operational modes are exemplified in the output waveform  250  of FIG. 9 which has signal portions  252  in which only positive pulses are generated, signal portions  254  in which only negative pulses are generated, signal portions  256  in which both positive and negative pulses are generated and signal portions  258  which have no pulses but which demonstrate various baseline signal levels. 
     In the driver  200  of FIG. 6, current is generally steered at any given time through only one transistor (e.g., the transistor  32 ) of each differential pair  30  and  50 . Preferably, the second transistor (e.g., the transistor  34 ) of the pair responds rapidly in response to a data signal that is intended to steer the current through the second transistor. This response is enhanced if the second transistor is conducting at least a keep-alive current. Accordingly, the driver  240  of FIG. 8 also includes keep-alive current sources  259  that are coupled to the differential pairs  240 . Even when not carrying one of the steered currents I 1  and I 2 , therefore, a cascode-arranged transistor  244  will still be carrying a small keep-alive current when not in the inhibited mode of operation. 
     The waveform driver  320  of FIG. 10 represents a differential version of the waveform driver  220  of FIG.  7 . The waveform driver  320  is similar to the driver  220  with like elements indicated by like reference numbers. However, the amplifier  60  is coupled to a differential output port  326  by series resistors  324  and Q and Q-bar terminals of the output port  326  are each connected to a parallel load resistor  328 . Each resistor  324  and a respective side of the output port  326  are coupled to respective sides of the differential pairs  30  and  50 . 
     FIG. 11 illustrates a differential waveform  340  obtained in performance simulations on a circuit similar to the waveform driver  320  of FIG.  10 . Traces  342  and  344  are the differential signals generated at Q and Q-bar of the differential output port ( 326  in FIG. 10) in response to the data inputs (S D1  and S D2  in FIG.  10 ). To generate this waveform, a common signal was used for both data inputs while the baseline input signal (S BL  in FIG. 10) was varied to establish two baseline levels  352  and  354 . It has been found that attributes (e.g., symmetry) of differential waveforms may be enhanced by driving the differential pairs  30  and  50  in a differential fashion (e.g., with differential data signals S D1  and S D1 -bar and differential data signals S D2  and S D2 -bar as shown in FIG.  10 ). 
     It is noted that the traces exhibit steep, linear, symmetric rising and falling edges  346  and  348  with minimal overshoots  350 . The signal levels  352  and  354  demonstrate rapid changes in the baseline component of the waveform  340  in response to the baseline input signal (S BL  in FIG.  10 ). In the differential driver  320 , the baseline component of the output signal is the common-mode signal between Q and Q-bar and the fidelity of the common-mode transistions is determined by the amplifier  60 . The waveform  340  particularly demonstrates the fidelity, rapid response and flexibility of complementary waveform drivers of the invention. 
     The teachings of the invention have been illustrated with particular reference to bipolar transistors but they may be practiced with various transistor types. For example, the bipolar transistors of the waveform drivers may be replaced with equivalent CMOS transistors. This is exemplified in FIG. 10 where a CMOS transistor  330  replaces a bipolar transistor  54  as indicated by a replacement arrow  332 . 
     Buffer amplifiers (e.g., amplifier  60  of FIG. 2) of the invention may be any of various conventional low-output-impedance, high-frequency complementary amplifiers, e.g., as shown in FIG. 3 of U.S. Pat. No. 5,179,293 to Hilton and FIG. 2 of U.S. Pat. No. 5,842,155 to Bryson, et al. 
     Waveform drivers of the invention include differential pairs of transistors. As is well known, one current terminal of each of these transistors is typically coupled to a current source and the source&#39;s current is steered to other transistor current terminals in response to control signals at transistor control terminals. 
     These waveform drivers may be used for the generation of waveforms with various amplitudes and baseline components and having fast rising and falling edges (e.g., ˜200-300 picoseconds) and high frequencies (e.g., ˜1 GHz). They are particularly suited for use as ATE pin drivers. They are also suitable for realization as high-speed application specific integrated circuits (ASICs) which can reduce their size and cost when produced in large volumes. 
     The preferred embodiments of the invention described herein are exemplary, and numerous modifications, variations and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be embraced within the spirit and scope of the invention as defined in the appended claims.