Abstract:
A method and apparatus for predict-ahead pulse-to-pulse voltage control in a pulsed power supply system is disclosed. A DC power supply network is coupled to a resonant charging network via a first switch. The resonant charging network is coupled at a node to a storage capacitor. An output load is coupled to the storage capacitor via a second switch. A de-Q-ing network is coupled to the resonant charging network via a third switch. The trigger for the third switch is a derived function of the initial voltage of the power supply network, the initial voltage of the storage capacitor, and the present voltage of the storage capacitor. A first trigger closes the first switch and charges the capacitor. The third trigger is asserted according to the derived function to close the third switch. When the third switch is closed, the first switch opens and voltage on the node is regulated. The second trigger may be thereafter asserted to discharge the capacitor into the output load.

Description:
The United States Government has rights in this invention pursuant to Contract No. W-7405-ENG-48 between the United States Department of Energy and the University of California for the operation of Lawrence Livermore National Laboratory. 
    
    
     BACKGROUND 
     The present invention relates to voltage control in pulsed power systems, and more particularly, to a predict-ahead controller for achieving increased pulse-to-pulse stability in pulsed power systems and especially those that use command-resonant-charge (CRC) architecture. 
     CRC architecture is typically used in pulsed systems to transfer energy from one capacitor bank to a second capacitor bank of lower capacity to achieve voltage gain. CRC architecture is common in devices which power Linear Induction Accelerators (LIA&#39;s), RADAR systems, EMP simulators, accelerator power sources, and Laser Isotope Separator (LIS) systems. 
     LIA&#39;s are used to produce high average power charged particle beams. These accelerators have been operated at high current (greater than 1 kA), moderate energy (on the order of tens of MeV), and at high repetition rates (on the order of 5 KHz). Operation of the LIA depends on the time rate of change of magnetic flux through the magnetic material (typically ferrite) within the accelerator cells. The changing flux produces an acceleration gradient along the accelerator axis that imparts energy to the charged particle beam. 
     Pulse-to-pulse voltage stability is fundamental to the high power operation of a Free Electron Laser (FEL) driven by an LIA. Such technology is being used to heat plasmas using electron cyclotron resonance heating (ECRH). Magnetic modulators, which use nonlinear, voltage dependent magnetics, are also among the devices which require a stable voltage source for stable pulse-to-pulse timing control and voltage regulation. 
     LIA technology has been proposed for hazardous waste treatment, product sterilization, and X-ray lithography. The success of these concepts depends in part upon stable operation of the LIA, which requires exceptional pulse-to-pulse voltage stability in the accelerator pulsed-power system. 
     Industrial applications of CRC architecture include high frequency annealing, E-beam and conventional welding, and magneforming. Pulse-to-pulse voltage stability in these systems can lead to better quality control. CRC architecture is also used in the medical industry. Applications include RF heating (diathermy), X-ray systems, and magnetic resonance imaging (MRI) systems. Pulse-to-pulse voltage stability in these systems can potentially improve instrument accuracy as well as patient safety. 
     SUMMARY OF THE INVENTION 
     A method and apparatus for predict-ahead voltage control for pulsed power supply systems is disclosed. A DC power supply network, including a charging capacitor, is coupled to a resonant charging network via a first switch. The resonant charging network is coupled to an Intermediate Energy Storage (IES) capacitor. An output load is coupled to the IES capacitor via a second switch. A de-Q-ing network is coupled to the resonant charging network via a third switch. 
     The first, second, and third switches are triggered by first, second, and third trigger pulses, respectively. The timing of the third trigger pulse is determined from a prediction V 2  *(t) of V 2  (t+Δ) as a function of the initial voltage V 1  (0) of the power supply network, the initial voltage V 2  (0) of the IES capacitor, and the present voltage V2(t) of the IES capacitor. Preferably, V 2  *(t)=V&#39; 2  (t)+(K 5  dV&#39; 2  (t)/dt) 2 , where V&#39; 2  (t)=K 1  V 2  (t)+K 2  dV 2  (t)/dt+K 3  V 1  (0)+K 4  V 2  (0), where K 1  =cos ωδ 1 , K 2  =(sin ωδ 1 )/ω, K 3  =C 1  (1-cosωδ 1 )/(C 1  +C 2 ), K 4  =C 2  (1-cos ωδ 1 )/(C 1  +C 2 ), K 5  =√C 2  /2α, and ω=1/√LC where C=C 1  C 2  /(C 1  +C 2 ). 
    
    
     A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic circuit diagram of a pulsed power unit according to the present invention. 
     FIG. 2a is a graphical plot of circuit conditions in FIG. 1, namely charging current at node 1, predicted voltage at node 2, and actual voltage at node 2, said voltages being inverted for convenient illustration. 
     FIG. 2b is a timing diagram illustrating the assertion of trigger pulses for the thyratron switches. 
     FIG. 3 is a block diagram of an analog computer implementation of the trigger pulse generator according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 depicts a simplified schematic diagram of a pulsed power supply system 8. The described embodiment is capable of supplying a 25 kV, 20 kA, 4 μS output pulse at a 5 kHz repetition rate. 
     An unregulated DC power supply 10 provides 20 kV, 250 kW of primary power. In a typical configuration, twenty 50 μF capacitors provide energy storage capacity. The power supply 10 is coupled by a shielded cable 12 to the cathode of a first thyratron switch S 1  at node 1. The anode of thyratron S 1  is coupled to one terminal of inductor L 2  - The other terminal of inductor L 2  is coupled to one terminal of inductor L 1  and to one terminal of network N 1 . The other terminal of inductor L 1  is coupled to one terminal of capacitor C 2 , to the cathode of thyratron S 2 , and to the cathode of thyratron S 3  at node 2. The anode of thyratron S 3  is coupled to the other terminal of network N 1 . The inductor L 2  is biased into a saturation state by a biasing network (not shown). The anode of thyratron switch S 2  is coupled to an output load 14. 
     The thyratron switches S 1 , S 2 , and S 3  are closed by supplying a current to respective grids of the thyratron switches in the form of trigger pulses V T1 , V T2 , and V T3 , respectively. The trigger pulses V T1 , V T2 , and V T3  are generated by individual trigger generators 16, 17, 18. 
     When inductor L 2  is in a saturated state, it has a very low inductance for forward current, but a large inductance for reverse current. Thus, immediate reverse voltage is developed across the inductor L 2  rather than across the thyratron tube S 1 , thereby providing time for the tube to recover between pulses. 
     The basic operation of the circuit will now be described. The thyratron switch S 1  closes when trigger pulse V T1  is applied to the grid of thyratron S 1 , thereby resonantly charging capacitor C 2  through inductor L 1 . Capacitor C 2  is also called the Intermediate Energy Storage (IES) capacitor. Ideally, the charging voltage V 2  (t) across the IES capacitor C 2  (in the absence of losses) is given by: ##EQU1## where V 1  (0) and V 2  (0) are the initial voltages at nodes 1 and 2, respectively, at the moment when switch S 1  closes, namely t=0; and ω=1/√LC, where C=C 1  C 2  /(C 1  +C 2 ), L is the total inductance of the charging loop, and 0≦ωt≦π. For the described embodiment, ω=2.88×10 4  seconds -1 , C 1  =20 μF, C 2  =2 μF. Ideally, the IES capacitor C 2  will charge to a peak value of approximately 1.8 V 1  (0), according to equation (1), provided switch S 1  remains closed and V 2  (0)=0. At this peak value, current flow reaches zero and begins to reverse. Simultaneously, L 2  transitions from a saturated, low inductance state to an unsaturated, high inductance state. While in the high inductance state, sufficient delay is provided at the zero current to allow the thyratron switch S 1  to cease conduction and open. Thus, in the absence of losses, V 2  remains approximately 1.8 V 1  (0). 
     Even with some means for voltage control at node 1, the initial voltage V 1  (0) on the charging capacitor C 1  may vary sufficiently to prevent a high degree of regulation at the output of the pulsed power system 8. Alternatively, absent some means of voltage control at node 1, and, as is typically done in a short burst system, use of a &#34;trickle&#34; low power DC power supply to charge the large power supply capacitors, the initial voltage V 1  (0) on the charging capacitor C 1  may vary as much as twenty to thirty percent. 
     Regulation of the voltage at node 2 is accomplished through the thyratron S 3  and the network N 1 . The network N 1  is a &#34;de-Q-ing&#34; network, and a complete description thereof can be found in the article &#34;Timing and Voltage Control of Magnetic Modulators on ETA II&#34; by M. A. Newton and J. A. Watson, Digest of Technical Papers, Seventh IEEE Pulsed Power Conference, June 1989, pp. 175-77. 
     A trigger pulse V T3  is applied to the grid of thyratron switch S 3  thereby closing the switch, and thyratron switch S 1  becomes reverse biased. Thyratron switch S 1  subsequently opens, thereby stopping the flow of charging current and maintaining V 2  at the desired voltage level. 
     Thus, it can be appreciated that the proper timing of the trigger pulse V T3  for switch S 3  is crucial for obtaining accurate voltage regulation at node 2. 
     The trigger pulse V T3  must be timed to account for inherent system delays, such as the delay in the trigger pulse amplifier, the hysteresis of the voltage comparator, the turn-on time of thyratron S 3 , and the turn-off time of thyratron S 1 . In the described embodiment, these delays are constant. 
     Therefore, the present invention discloses a controller for generating the trigger pulse of thyratron S 3  that predicts the IES capacitor voltage at some future time t+Δ, where Δ is the total inherent system delay between the time t when a command is issued to trigger switch S 3  and the time t+Δ when the charging current through L 1  actually ceases to flow. The total delay Δ is equal to δ 1  +δ 2 , where δ 1  is the delay between the assertion of trigger pulse V T1  and the closing of switch S 3 , and δ 2  is the delay between the closing of switch S 3  and the opening of switch S 1 . 
     It can been shown that a good prediction for V 2*  (t) is given by: 
     
         V.sub.2 (t+Δ)≈V.sub.2 *(t)=V&#39;.sub.2 (t)+(K.sub.5 dV&#39;.sub.2 (t)/dt).sup.2                                             (2) 
    
     where V&#39; 2  (t) is given by: 
     
         V&#39;.sub.2 (t)=K.sub.1 V.sub.2 (t)+K.sub.2 dV.sub.2 (t)/dt+K.sub.3 V.sub.1 (0)+K.sub.4 V.sub.2 (0)                                   (3) 
    
     where 
     K 1  =cos δ 1   
     K 2  =(sin ωδ 1 )/ω 
     K 3  =C 1  (1-cos ωδ 1 )/(C 1  +C 2 ) 
     K 4  =C 2  (1-cos ωδ 1 )/(C 1  +C 2 ) 
     K 5  =√C 2  /2α 
     ω=1/√LC 
     C=C 1  C 2  /(C 1  +C 2 ). 
     where α is the approximate magnitude of the charging current during the time interval from (t+δ) to (t+Δ). Therefore, the command to issue the trigger pulse V T3  for switch S 3  is issued at the time t=T at which V 2  *(T) equals the desired IES voltage. 
     It can be appreciated that expressions having greater or fewer terms than equations (2) and (3) can be derived which may provide varying degrees of accuracy. For example, we have published an article describing the present invention with a three term solution. See &#34;Precision Voltage Regulation on the 5 KHz 3.125 mW ETA-II Pulsed Power System&#34; by J. A. Watson, A. N. Payne, S. E. Sampayan and C. W. Ollis, Digest of Technical Papers, Eighth IEEE Pulsed Power Conference, June 1991, pp. 221-223. 
     The net effect of the present invention is illustrated in FIGS. 2a and 2b. At time t=0, the first trigger pulse V T1  is asserted, thereby closing thyratron switch S 1 . The charging capacitor C 1  then discharges a charging current I 1  to the IES capacitor C 2 . At time t=T, the predicted voltage V 2  *, shown as a dotted line in FIG. 2a, reaches the desired &#34;predict-ahead&#34; voltage at node 2, and the third trigger pulse V T3  is initiated, thereby closing thyratron switch S 3 . This causes switch S 1  to become reverse-biased, thereby stopping the flow of charging current I 1  and allowing the de-Q-ing network to regulate the voltage V 2  at node 2 at the desired level. At some later time, trigger pulse V T2  can be initiated to allow the IES voltage V 2  at node 2 to be discharged to the output load 14. 
     A circuit to implement Equations (2) and (3) is easily realized as illustrated in the block diagram of FIG. 3. The voltage V 2  at node 2 is coupled to signal conditioning network 20. The signal conditioning network 20 scales down the input signal to facilitate handling by conventional signal processing circuitry. The output of the signal conditioning network 20 is then passed in parallel through a differentiator network 22, a sample/hold network 23, and a first amplifier 24. The first amplifier has a gain constant K 1  as described above. The differentiator network 22 generates an output signal which is the time derivative of the voltage function for V 2  (t), which is then passed through a second amplifier 26. The second amplifier has a gain constant K 2  as described above. The sample/hold network 23 samples the input when the trigger pulse V T1  is asserted and provides the signal to amplifier 25. The amplifier 25 has a gain constant K 4  as described above. 
     The voltage V 1  at node 1 is coupled to a second signal conditioning network 28 which scales down the input signal to facilitate handling by conventional signal processing circuitry. The signal is then passed through a sample/hold network 30, where the signal is sampled at the time that trigger pulse V T1  is asserted. The signal is then amplified with gain constant K 3  through a third amplifier 32. The gain constant K 3  is described above. 
     The outputs of amplifiers 24, 25, 26, and 32 are coupled to a summer 34 where the signals are summed. The output of the summer 34 is V&#39; 2  (t). This signal is coupled to differentiator 36, where the time derivative of the voltage function for V&#39; 2  (t) is obtained. The differentiated signal is then passed through amplifier 38, which has a gain constant K 5  as described above. Next, the signal is multiplied by itself in multiplier 40 in order to realize the square function of equation (2). Finally, a summer 42 adds the signal back to V&#39; 2 , and the resultant output V 2  *(t) accurately approximates the predicted voltage V 2  (t+Δ). The output is compared to a reference voltage V ref  by comparator 44. When the output of summer 42 is equal to V ref , trigger amplifier 46 generates the trigger pulse V T3 . 
     The specific details for realization of the blocks illustrated in FIG. 3 are well known to one with ordinary skill in analog circuit design and are therefore not provided herein. Further, it should be clear that FIG. 3 may be implemented numerically by utilization of a fast digital computer. 
     It should be understood that the invention is not intended to be limited by the specifics of the above-described embodiment, but rather defined by the accompanying claims.