Abstract:
An analog-to-digital converter (ADC) is used for dynamic tracking nonlinearity correction. The correction employs an analog sampling technique to determine the signal derivative by measuring the derivative current arising from sampling an analog input signal undergoing analog-to-digital conversion, at the sampling instant. The analog derivative sampling technique achieves significant reduction in power consumption with less complexity compared with a digital approach, with strong improvements in HD 3 , SDFR, and IM 3  measures.

Description:
PRIORITY CLAIM 
     This application claims priority to provisional application Ser. No. 62/298,580, filed Feb. 23, 2016, which is entirely incorporated by reference. 
    
    
     TECHNICAL FIELD 
     This disclosure relates to analog-to-digital converters. 
     BACKGROUND 
     Rapid advances in electronics and communication technologies, driven by immense customer demand, have resulted in the widespread adoption of electronic devices of every kind. The analog-to-digital converter (ADC) is a fundamental circuit component of these devices. ADCs have a wide range of circuit applications, and for instance provide a key building block for full band capture and other applications in devices such as cable modems, set-top boxes, WiFi, cellular handsets, cellular base stations, Ethernet, and many other devices. At high input frequency and large signal amplitude, ADCs experience dynamic tracking non-linearity which limits overall linearity of the ADC. Because dynamic tracking non-linearity is frequency dependent, it cannot be calibrated with static non-linearity correction mechanisms. Improvements in ADC design that determine and calibrate for dynamic tracking error will further enhance the capabilities of ADCs and the devices that rely on analog to digital conversion. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows analog-to-digital sample-and-hold circuitry. 
         FIG. 2  illustrates analog-to-digital sample-and-hold circuitry with derivative current measurement. 
         FIG. 3  illustrates differential analog-to-digital sample-and-hold circuitry with derivative current measurement. 
         FIG. 4  illustrates main-path analog to digital conversion and auxiliary path analog to digital conversion for derivative current measurement and error correction circuitry. 
         FIG. 5  shows a flow diagram for dynamic tracking calibration. 
         FIG. 6  shows one-tone calibration results. 
         FIG. 7  shows two-tone calibration results. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows analog-to-digital sample-and-hold circuitry  100 . An analog signal input  102  connects to an input buffer  104 . Following the buffer  104  is a bootstrap circuit  106  that controls the gate of a bottom-plate switch  108 . The input voltage sampling transistor  108  has a non-linear channel resistance, R on , that is a physical operating characteristic of the bottom-plate switch  108 . Also present is a sampling capacitor  110  followed by a top-plate switch  112 . 
     The bootstrap circuit  106  may, for instance, generate a late clock on a late clock input  114  coupled to the bottom-plate switch  108 . Note also that an early clock input  116  is coupled to the top-plate switch  112 . The early clock input  116  carries an early clock that is advanced with respect to the late clock to perform bottom-plate sampling. The late clock for the bottom-plate switch  108  is labeled φs, and the early clock is labeled φse. 
       FIG. 2  shows analog-to-digital sample-and-hold circuitry  200  with derivative current measurement. In  FIG. 2 , a current sampling analog-to-digital converter (ADC)  202  is in series with the sampling capacitor  110 . The current sampling ADC  202  converts a derivative current, I ds , flowing through the non-linear resistance and the sampling capacitor  110  to a digital representation. The current sampling ADC  202  provides the digital representation on a sampling output  204  to error correction circuitry (discussed below). In one implementation the current sampling ADC  202  is a 7 bit ADC. Note however that the current sampling ADC  202  may convert to fewer or additional bits depending on the conversion resolution used in the error correction circuitry. 
     The derivative current is labeled in  FIG. 2  as the current I ds . Note that the analog input voltage, V in , is sampled on to the sampling capacitor  110  as a digital output, V out . Given the non-linear resistance R on  and the derivative current I ds , the relationship between V in  and V out  includes a dynamic tracking error:
 
 V   in   =V   out   +R   on(Vout)   ·I   ds  
 
     and, because I ds  is a current due to the time derivative of the voltage across the sampling capacitor  110 :
 
 V   in   =V   out   +R   on(Vout)   ·C   s ·( dV   out   /dt )
 
     The current sampling ADC  202  measures the derivative current at the sampling instant (when φse falls) in order to facilitate correction, by succeeding error correction circuitry, to the output of a main-path ADC that converts V in . The current sampling ADC  202  does so in a less complex and costly manner that consumes less power compared, e.g., to a complex multi-tap digital interpolation filter that determines an approximation to the signal derivative, particularly at high sample rates and under-sampled scenarios. 
       FIG. 3  illustrates differential analog-to-digital sample-and-hold circuitry  300  with derivative current measurement.  FIG. 4  depicts a system overview of dynamic tracking calibration  400 .  FIGS. 3 and 4  are described in detail below with reference also to  FIG. 5 , which shows the signal processing flow diagram for tracking calibration  500  that circuitry may implement for derivative current measurement and correction. 
       FIG. 3  shows a differential implementation of the auxiliary path for derivative current measurement. In the differential implementation, the differential analog input voltage is provided on the V in+  and V in−  differential inputs  302  ( 502 ). A differential input buffer  304  buffers and drives the differential inputs  302  to the differential analog-to-digital sample-and-hold circuitry  306  (“circuitry  306 ”) ( 504 ). The circuitry  306  includes independent sampling branches  308  and  310 . 
     Each of the independent sampling branches  308 ,  310  may replicate, e.g., the analog-to-digital sample-and-hold circuitry  100 . The branches  308  and  310  provide differential derivative current sampling outputs  312  and  314  to the differential input ADC  316  (which has a singled ended digital output). In more detail, the independent sampling branches  308 ,  310  include the bootstrap circuitry, the bottom-plate switches (with non-linear channel resistance, R on ), sampling capacitors, and top-plate switches. Together, the late clock for the bottom-plate switch, φs, and the early clock, φse, control sampling of the analog input voltage. Clock generation circuitry controls the relationship between φs and φse, and the differential input ADC  316  receives the early clock, φse, for measuring the derivative current at the sampling instant of the analog input voltage ( 506 ). 
     In addition, the independent sampling branches  308 ,  310  also include current-to-voltage conversion circuitry  318 ,  320  between the sampling capacitors and the differential input ADC  316 . The current-to-voltage conversion circuitry  318 ,  320  converts the individual differential derivative current components to a voltage representation ( 508 ). Note that the current sources  322 ,  324  preferably have high output impedance. 
     The voltage representations are inputs to the level-shifting circuitry  326 ,  328  that is between the current-to-voltage conversion circuitry  318 ,  320  and the differential input ADC  316 . The level-shifting circuitry  326 ,  328  adjusts the voltages for voltage level compatibility with the differential input ADC  316 , and may also provide drive for those voltages into the differential input ADC  316  ( 510 ). The current-to-voltage conversion circuitry  318 ,  320  and the level-shifting circuitry  326 ,  328  are circuit and implementation dependent features, and either or both may be omitted in other designs. 
     The differential input ADC  316  converts the level shifted voltage representations to digital form ( 512 ), thereby providing a measurement, at the sampling instant, of the derivative current. The ADC  316  provides the digital measurement to error correction circuitry ( 514 ). 
       FIG. 4  illustrates main-path analog to digital conversion with derivative current measurement and error correction circuitry  400 . A main-path ADC  402  (e.g., a 12 bit ADC) samples the analog input voltage, while the derivative current ADC  404  (e.g., a 7 bit ADC) generates digital measurements of the derivative current on the measurement output  406  at the sampling instant, e.g. using the circuitry shown in  FIG. 3 . 
     The main-path ADC  402  and derivative current ADC  404  may implement other bit resolutions. In some implementations, the 7 bit derivative current ADC  404  covers, e.g., 100 mV of derivative current signal level, quantized to the same noise level of the main-path ADC  402 . That is, the error term may often be small compared to the main-path sample, and fewer bits (e.g., 7 bits) may cover a range that corrects a pre-determined number of least significant bits (e.g., 4) in the main-path sample. 
     The measurement output  406  provides derivative current measurements to the error correction circuitry  408 . The error correction circuitry  408  includes an error calculation circuit  410  that receives the derivative current measurements and the main-path sample of the analog input voltage, after equalization by the equalization circuitry  412  ( 516 ). The error calculation circuit  410  outputs an error correction term to adder circuitry  414  ( 518 ), which in turn outputs the calibrated digital voltage sample of the analog input voltage on the calibrated sample output  416  ( 520 ). The calibrated sample returns to the error correction circuitry  410  through the least mean square (LMS) processor  418  and a gain circuit  420 . 
     A digital-to-analog (DAC) converter  422  provides a linear reference for the calibration. To linearize the reference further, the analog output of the DAC  422  passes through a low pass filter (LPF)  424  to the LMS processor  418  and, through the buffer  426 , to the subsequent circuitry shown in  FIG. 4 . The LMS processor  418  responsively determines the coefficients for the error calculation circuit  410  to minimize error in the calibrated sample output  416  compared to the reference input ( 522 ). 
     The equalization circuitry  412  calibrates for errors that may occur during the holding phase, such as gain error, incomplete settling, and leakage. The gain circuit  420  sets the step size of the LMS algorithm. The larger the step size, the faster the LMS algorithm converges, but with larger calibration inaccuracy. The error calculation circuit  410  evaluates the dynamic tracking error R on(Vout) ·C s ·(dV out /dt). 
       FIG. 6  shows single tone calibration results  600 .  FIG. 6  shows a comparison of a single tone signal input to the system, before and after calibration, using the techniques described above. The HD 3  distortion measure, the strength of the third harmonic of the tone input, was reduced 20 dB. The spurious free dynamic range (SFDR) measure was reduced by 13 dB, dominated by higher order harmonics instead of HD 3 . 
       FIG. 7  shows two tone calibration results  700 .  FIG. 7  also shows a comparison of a two tone signal input to the system, before after calibration, using the techniques described above. The IM 3  intermodulation distortion measure was reduced by 18 dB. 
     The methods, devices, processing, circuitry, and logic described above may be implemented in many different ways and in many different combinations of hardware and software. For example, all or parts of the implementations may be circuitry that includes discrete logic or other circuit components, including analog circuit components, digital circuit components or both; or any combination thereof. The circuitry may include discrete interconnected hardware components or may be combined on a single integrated circuit die, distributed among multiple integrated circuit dies, or implemented in a Multiple Chip Module (MCM) of multiple integrated circuit dies in a common package, as examples. 
     Various implementations have been specifically described. However, many other implementations are also possible.