Abstract:
A semiconductor logic integrated circuit device comprising a signal selection means and a storing means, which is capable of adjusting the logic levels of an output signal therefrom. With such a circuit device, the signal selection means and the storing means are controlled in normal operation mode so that a parallel input signal is allowed to be output as a parallel output signal from output terminals of the circuit device after subjecting the parallel input signal to logical signal processing. On the other hand, the signal selection means and the storing means are controlled in a testing opertion mode so that the parallel input signal are output in serial mode from a serial signal output terminal of the circuit device, and a serial input signal to the signal selection means is allowed to be stored in the storing means to adjust the logic levels of the output signal from the circuit device at desired levels voluntarily.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a semiconductor logic integrated circuit device, and more particularly to a signal selection circuit included therein. 
     BACKGROUND OF THE INVENTION 
     In order to explain the background of the present invention, reference will be first made to FIG. 1 which is a block diagram showing a conventional semiconductor logic integrated circuit device ( hereinafter referred to as an IC device ). In FIG. 1, input buffers (IB 1 ) to (IB 4 ) receive input signals in parallel, respectively, which are supplied from an external signal supply unit ( not shown ) to input terminals (I 1 ) to (I 4 ), and the parallel outputs of the input buffers (IB 1 ) to (IB 4 ) are then applied to a logic unit (LG) to be subjected to logical signal processing. Output signals P 1  to P 4  of the logic unit (LG) are output through output buffers (OB 1 ) to (OB 4 ) to output terminals (O 1 ) to (O 4 ), respectively. Electric power is supplied to the above described elements through a common power supply terminal and a common power supply line ( not shown ). 
     To test and evaluate the IC device, the IC device is coupled to a testing device ( hereinafter referred to as a tester ) so that a test pattern signal is applied to the input terminals (I 1 ) to (I 4 ), and the logical verification of the IC device is accomplished based on the output logic levels at the output terminals (O 1 ) to (O 4 ) in response to the input of the test pattern signal. 
     With such a conventional IC device as described above, variation in power supply current--which may be caused by variations in the output logic levels of the output buffers (OB 1 ) to (OB 4 )--is relatively larger than that which may be caused by the other circuit elements. Therefore, when a large number of output signals switch their logic levels to either high logic level (H) or low logic level (L) simultaneously the power supply current varies remarkably in response to the switch. This results in variation in power voltage which may be caused by the above described transient variation of the power supply current and a distributed inductance which exists along circuit elements including coupling members for coupling the IC to be tested to the tester, jigs such as a performance board and wiring in the tester. 
     Since the logic levels of the test pattern signal which is applied to the input terminals (I 1 ) to (I 4 ) are determined based on the voltage level of a voltage appearing at a common terminal of the tester, there is a possibility that the variation in the power supply voltage may be superposed on the test pattern signal as noise, resulting in a decrease in the input operation margin of the IC device. In the worst case, this results in an occurrence of errors in the logical operation thereof. 
     In order to overcome the above described drawbacks, a test pattern signal may be used which does not cause the output levels of the output signals from the IC device to vary simultaneously. In this case, however, such a test pattern signal may not meet the logical processing condition of the IC device to be tested, and therefore is not practical to use for fully testing the IC. 
     The conventional semiconductor logic integrated circuit device thus constructed is disadvantageous in that, since it is necessary to apply a test pattern signal to the input terminals of the IC device successively in order to determine the logic levels of the output signal therefrom, a relatively long period of time is required to carry out the test operation, and a decrease in the input operation margin may occur due to the variation in the power supply voltage which may be caused by the abrupt and simultaneous variation of the output signal levels in the same potential direction. 
     SUMMARY OF THE INVENTION 
     To overcome the above described drawbacks and difficulties accompanying the prior art devices, the present invention provides a semiconductor logic integrated circuit device having a signal selection circuit which is capable of freely adjusting the logic levels of an output signal therefrom to thereby shorten a period of time required for a test operation. The signal selecting circuit is thus capable of preventing the occurrence of decreasing of an input operation margin caused by simultaneous variation in logic levels of output signals from output buffers in the same potential direction. 
     According to one embodiment of the present invention, shift registers each having a signal selection function, which are coupled in a cascade connection, are connected to output terminals of a logic unit contained in a semiconductor logic integrated circuit device, respectively, and further temporary storing circuits are coupled between the shift registers and output buffers of the IC device, respectively. 
     A semiconductor logic integrated circuit device according to the present invention is provided with such shift registers and temporary storing circuits. An output parallel signal from the logic unit can be output in a serial mode from a shift-out terminal of the IC device, and logic input signals which are applied through shift-in terminals of the shift registers can be stored in the temporary storing circuits--whereby it is possible to maintain the output levels of output signals from the output buffers unchanged even though the logic levels of the output signals from the logic unit vary. 
     To this end, it is possible to prevent the logic levels of the parallel output signals from the output buffers from varying simultaneously. Further, since the logic levels thereof from the output buffers can be determined voluntarily by setting the logic levels of the logic input signals to the shift-in terminals of the shift registers voluntarily, it is unnecessary to apply a test pattern signal to the respective input terminals of the logic unit in order to determine the logic levels of the output signal during a DC test, resulting in shortening the test period duration. 
     The above and other objects, features and advantages of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings in which a preferred embodiment of the present invention is shown by way of illustrative example. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawings: 
     FIG. 1 is a circuit diagram of a conventional semiconductor logic integrated circuit device; 
     FIG. 2 is a circuit diagram showing a presently preferred exemplary embodiment of a semiconductor logic integrated circuit device according to the present invention; 
     FIG. 3 is a timing chart graphically illustrating the operation of the device shown in FIG. 2; and 
     FIG. 4 is a circuit diagram schematically showing shift registers (SR 1 ) to (SR 4 ) shown in FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A preferred embodiment of the present invention will be described hereinbelow with reference to FIGS. 2 to 4. 
     FIG. 2 is a circuit diagram showing the preferred embodiment of the present invention and FIG. 3 is a timing chart showing waveforms of signals appearing in the embodiment of FIG. 2. 
     In FIG. 2, designated by reference characters (SR 1 ) to (SR 4 ) are shift registers, respectively, each detailed circuit construction of which is shown in FIG. 4. (L 1 ) to (L 4 ) denote latches each having a signal transmission function. (C 1 ) to (C 4  are input terminals for receiving control signals, (SI) is a shift-in terminal for receiving logic input signals, and (B 1 ) to (B 5 ) are input buffers. 
     In FIG. 2, circuit components which are identical or correspond to those in FIG. 1 bear the same reference numerals or characters. 
     In FIG. 4 (which shows an exemplary configuration for each of shift registers SR1-SR4 of FIG. 2) reference characters (TR 1 ) and (TR 2 ) denote transmission gates; (Inv 1 ) and (Inv 2 ) are inverters constituting a latch (LT), and (L 5 ) is a data latch. 
     The operation of the circuit shown in FIG. 4 will now be described with reference to FIG. 4. 
     Each of the shift registers (SR 1 ) to (SR 4 ) operates as follows. When a normal mode signal NM applied to the input terminal (C 4 ) is &#34;L&#34; (logic level &#34;low&#34;), a serial data SD input to the shift-in terminal (SI) is held in the latch (LT) in synchronization with a shift mode signal SM applied to the input terminal (C 1 ). On the other hand, when the signal SM is at level &#34;L&#34;, an output signal P 1 , P 2 , P 3  or P 4  from the logic unit (LG), which is applied to the terminal (D), is held in the latch (LT) in synchronization with the signal NM from the input terminal (C 4 ). The signal which has been held in the latch (LT), is then allowed to be transmitted to the data latch (L 5 ) in synchronization with an input signal T 2  applied to the input terminal (C 2 ) so as to be held therein. The signal held in the latch (L 5 ) is transmitted to the following latch (L 1 ), (L 2 ), (L.sub. 3) or (L 4 ) in synchronization with an input signal T 3  applied to the input terminal (C 3 ) to be held therein. 
     In the device as shown in FIG. 2, during a normal operation (not testing operation ), the shift mode signal SM applied to the input terminal (C 1 ) is set to &#34;L&#34; whereas the input signals T 2  and T 3  applied to the input terminals C 2  and C 3 , respectively, and the normal mode signal NM applied to the input terminal C 4  are set to &#34;H&#34;. As a result, the transmission of the output signal P 1 , P 2 , P 3  or P 4  which is output from the logic unit LG is allowed from the input terminal (D) to the output terminal (Q) in each of the shift registers SR 1  to SR 4 . Further, in the respective latches L 1  to L 4 , the output signals of the respective shift registers SR 1  to SR 4  which are applied to input terminals of the latches L 1  to L 4  are allowed to pass therethrough to output terminals Q thereof. Consequently the output signals P 1  to P 4  from the logic unit LG can be transmitted to the output terminals (O 1 ) to (O 4 ) of the circuit device (the shift registers SR and data latches L being transparent during normal use) and therefore a desired normal operation of the circuit device is carried out. More concretely, when the output signals P 1  to P 4  are &#34;H&#34;, &#34;L&#34;, &#34;L&#34; and &#34;H&#34; respectively as shown in FIG. 3, the output levels of the signals from the buffers (OB 1 ) to (OB 4 ) are also &#34;H&#34;, &#34;L&#34;, &#34;L&#34; and &#34;H&#34;. 
     The operation when the normal mode signal NM applied to the input terminal (C 4 ) is set to &#34;L&#34;, will be described. 
     In this case the application of the output signals P 1  to P 4  from the logic unit LG is blocked by the transmission gate TR 1  (FIG. 4), output is accomplished by applying input signals as a clock signal to the input terminals (C 1 ) and (C 2 ) to shift-in logic input signals through the shift-in terminals (SI) or to shift-signals out through the serial output terminal SO. 
     When the normal mode signal NM is set to &#34;L&#34;, the output signals P 1  to P 4  from the logic unit (LG) are held in the latches (LT) in the shift registers (SR 1 ) to (SR 4 ), respectively. Then, upon the application of the following clock signal (T 2 ) to the input terminal (C 2 ), the signals P 1  to P 4  are transmitted to the latches (L 5 ) to be held therein. At the same time, the output signal (P 1 )( &#34;H&#34; in FIG. 2(e)) is output from the output terminal (SO). 
     Assuming that the serial input signal of &#34;H&#34;, &#34;H&#34;, &#34;L&#34; and &#34;L&#34; in this order is applied to the shift-in terminal (SI), when the clock signal (SM) applied to the input terminal (C 1 ) advances once, the input logic signal of &#34;H&#34; from the shift-in terminal (SI) is transmitted to the latch (LT) of the shift register (SR 4 ) to be held therein. At the same time, applied to the latches (LT) of the shift registers (SR 3 ) to (SR 1 ) are the output signals (P 4  ) to (P 2 ), respectively. That is, the signals of &#34;H&#34;, &#34;L&#34; and &#34;L&#34; are held in the latches (LT) of the shift registers (SR 3 ) to (SR 1 ) in this order. As described above, by applying the clock signals of &#34;H&#34; to the input terminals (C 1 ) and (C 2 ) alternately, the logic input signals &#34;H&#34;, &#34;H&#34;, &#34;L&#34; and &#34;L&#34; which are applied to the shift-in terminals of the shift registers (SR 1 ) to (SR 4 ) in this order, can be held in the latches (L 5 ) thereof, respectively. Simultaneously, the output signals P 1  to P 4  from the logic unit (LG) can be read out from the output terminal (SO) in serial mode. 
     In FIG. 2, upon the application of the next clock signal T 2 , the signals which have been held in the latches (L 5 ) of the shift registers (SR 1 ) to (SR 4 ), respectively, are allowed to be output through the respective output terminals (Q) resulting in variations of the logic levels. In this case, however, if the input signal T 3  applied to the input terminal (C 3 ) is set to &#34;L&#34;, the output levels of the buffers (OB 1 ) to (OB 4 ) are continuously held at the levels, respectively, that are same as those which are obtained upon the application of the preceding clock signal T 2 . On the other hand, if the input signal T 3  is applied to the input terminal (C 3 ) as a new clock signal, as shown in FIG. 2, the signals of &#34;H&#34;, &#34;H&#34;, &#34;L&#34; and &#34;L&#34; which have been held in the data latches (L 5 ) of the shift registers (SR 1 ) to (SR 4 ), are allowed to be transmitted to the latches (L 1  ) to (L 4 ) to be held therein. Consequently, the signals of &#34;H&#34;, &#34;H&#34;, &#34;L&#34; and &#34;L&#34; can be output from the output terminals (O 1 ) to (O 4 ), respectively as outputs Q 1  to Q 4 . 
     While a data latch is employed as a temporary storing circuit in the above described embodiment, modifications therefor are possible. That is, another logic circuit which has the same function can be used to realize the same function of the IC device. 
     Further, although a concrete example of a shift register which is employed in the present invention is shown in FIG. 4, the shift register can be also replaced by another logic circuit having the same shift-function. 
     As is apparent from the above, according to the present invention, a shift register and a temporary storing circuit are provided between an output terminal of a logic unit and an output buffer corresponding to the output terminal, the shift registers being coupled in a cascade manner. With such a circuit construction described above, it is possible to read out the parallel outputs from the logic unit in serial mode by the function of the shift registers under the condition that the output levels appearing at output terminals of a semiconductor logic IC device are maintained unchanged. Consequently, there is no possiblity that the output levels of the IC device are varied in the same potential direction simultaneously--thereby eliminating undesired variation in a power supply current. As a result, the variation in the power supply voltage is also suppressed to thereby prevent an occurrence of errors in the operation of the IC device. Further, since voluntary signals can be held in the temporary storing circuits through the shift registers, it is possible to adjust the output logic levels of the output signal from the output buffers at desired levels. Accordingly, it is unnecessary to supply a false signal to the IC device for testing the IC device. This results in shortening a period of time required for such a testing operation.