Abstract:
An oscillator having a tank circuit, an amplifier circuit and a switching circuit. The switching circuit switches the oscillator between a normal power consumption mode and a lower power consumption mode. The amplifier circuit includes an emitter biased transistor. The switching circuit switches between power consumption modes by switching between two selected voltages at the base of the transistor. When in the lower power consumption mode, the oscillator has sufficient current to sustain oscillation but insufficient current to meet the phase noise requirements for good fidelity and high data rates. When in the normal power consumption mode, the oscillator has sufficient current to meet the phase noise requirements for good

Description:
This application claims the benefit under 35 U.S.C. §119(e) of the U.S. provisional patent application No. 60/093,460 filed Jul. 20, 1998. 
    
    
     TECHNICAL FIELD 
     This invention relates to electronic oscillators and more particularly to an electronic oscillator switchable between a normal power consumption mode and a lower power consumption mode. 
     BACKGROUND ART 
     There are a great variety of wireless communication systems being used in the world today, such as Global System for Mobile Communication (GSM), Digital Advanced Mobile Phone Service (DAMPS), Personal Handy System (PHS), Personal Communication Services (PCS), Land Mobile Radio (LMR), Special Mobile Radio (SMR) and two way paging to name a few. The consumer would like their phone or pager to reliably work anywhere in the world for a long time. One of the keys to the amount of time that a phone can go without being recharged is the amount of current the oscillator draws when the phone is in receive mode. 
     Typically, the Voltage Controlled Oscillator (VCO) generates the Local Oscillator (LO) signal for transmit and receive functions in mobile radio RF circuitry. The VCO is typically left on in the standby mode when the phone is neither transmitting or receiving. 
     The prior known methods to conserve current in VCO designs or implementation in a phone have consisted of putting a phase shift network in the feedback circuitry or switching the transmit VCO off along with the power transmitter to conserve dc power. U.S. Pat. No. 4,621,241 to Kiser discloses a VCO with a phase shift network in the feedback circuitry. 
     The disadvantage of using a phase shift network in the feedback network is the current consumption is fixed and the oscillator current and performance must be optimized to meet the performance requirements when operating in the normal power consumption mode. 
     The oscillator is typically used in a phase locked loop (PLL). The disadvantage of turning the transmitter oscillator off with the power transmitter is that the PLL takes time to lock after the oscillator is turned back on, meaning lost transmit time and channel inefficiency. 
     A known power level is needed in the oscillator to meet the phase noise requirements for good fidelity and high data rates when the phone is transmitting and receiving. This is the normal power consumption mode. Oscillation will be sustained in the oscillator and the PLL will remain locked at a lower power level when the phone is not transmitting or receiving. The phase noise is, however, degraded in this lower power consumption mode. An oscillator is needed with switching means to switch between the normal and lower power consumption modes in order to conserve power without loss of transmit time or loss of channel efficiency. 
     DISCLOSURE OF THE INVENTION 
     An electronic oscillator having a DC power consumption switching circuit for switching the oscillator between a normal power consumption mode and a lower power consumption mode is disclosed. The oscillator includes a tank circuit and a signal amplifier circuit. The current flow through the signal amplifier circuit is controlled by the voltage at the control terminal of an amplifying element in the signal amplifying circuit. The circuitry that switches the oscillator to a lower DC power includes a switching element and resistive elements which change the voltage at the control terminal of the amplifying element. The voltage change decreases the current through the amplifying element and thereby decreases the power consumption of the oscillator while sustaining oscillation. The oscillator, while in the lower power consumption mode, consumes approximately half the power consumed in the normal power consumption mode and is able to provide enough feedback power to a PLL to keep the PLL locked. The oscillator extends the battery life of a phone without degrading transmit time or channel efficiency. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Details of this invention are described in connection with the accompanying drawing: 
     The drawing is an electric circuit diagram of a voltage controlled oscillator with a power consumption switching circuit embodying features of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to the drawing, there is shown a voltage controlled oscillator embodying features of this invention which includes a tank circuit, a signal amplifier circuit and a switching circuit. 
     Describing the specific embodiments herein chosen for illustrating the invention, certain terminology is used which will be recognized as being employed for convenience and having no limiting significance. Terminology consistent with conventional current flow, not electron flow, will be used. The terms &#34;input&#34; and &#34;output&#34; will refer to conventional current flow into and out of the device. Further, all of the terminology above-defined includes derivatives of the word specifically mentioned and words of similar import. 
     The tank circuit shown is a parallel tuned resonant circuit in a Colpitts type configuration. Other types of tank circuit, such as Pierce or Hartley or a series tuned Colpitts, would be suitable for use in the invention. The tank circuit includes a resonating inductor L2 connected in parallel with a DC blocking capacitor C2 that is connected in series with a tuning capacitor CR1, shown as a varactor diode. The resonating inductor L2 is connected to ground on the side opposite the connection to DC blocking capacitor C2. The tuning capacitor CR1 is connected to ground on the side opposite the connection to DC blocking capacitor C2. The tank circuit includes a first signal divider capacitor C3 connected to the connection of the first resonating inductor L2 and the DC blocking capacitor C2 on one side, and connected to a second signal divider capacitor C4 on an opposite side. The side of second signal divider capacitor C4 opposite the connection to the first signal divider capacitor C3 is connected to ground. 
     A DC voltage tuning input terminal V T  is connected through an impedance Z1 to the connection of the tuning capacitor CR1 and the DC blocking capacitor C2. A voltage, typically from 0 to 8 volts, is applied to terminal V T  to tune the capacitance of the tuning capacitor CR1. The impedance Z1 is of a high value so as not to load the Q of the tank circuit, and may be an RF choke, a high impedance active device such as a transistor, or another network presenting a high RF impedance and a controlled DC resistance. An RF bypass capacitor C1 is connected to input terminal V T  and to ground to provide a low pass filter and thereby short out any RF signals. 
     The signal amplifier circuit for the voltage controlled oscillator includes an amplifying element, shown as an NPN transistor Q1. The transistor Q1 has a collector terminal C as an input for the amplifying element, a base terminal B as control terminal for the amplifying element and an emitter terminal E as an output for the amplifying element. A DC voltage supply terminal V CC  connects through an inductive impedance L3 to collector terminal C to supply DC power to transistor Q1. A voltage, typically from 0 to 5 volts, is applied to DC voltage supply terminal V CC . An RF bypass capacitor C7 connects between the DC voltage supply terminal V CC  and ground to provide an RF ground. 
     The power output is shown as being taken from the collector terminal C of the transistor Q1. The output coupling and impedance matching can be accomplished in a number of ways to match the active device to the desired output load. In the illustrated embodiment, a capacitor C9, a resistor R5 and a capacitor C11 are connected in series respectively from the collector terminal C to an output terminal RF out . A resistor R7 is connected at one side between resistor R5 and capacitor C11, and connected at the other side to ground. 
     A bias impedance in the form of a resistor R4 is connected between the emitter terminal E of the transistor Q1 and ground. The feedback loop for sustaining the oscillations in the tank circuit includes the transistor Q1, first signal divider capacitor C3, and a capacitor C5. The emitter terminal E connects between the first and second signal divider capacitors C3 and C4. The one side of the capacitor C5 connects to the base terminal B of transistor Q1 and the other side of capacitor C5 connects to the common connection of first signal divider capacitor C3, DC blocking capacitor C2 and resonating inductor L2. 
     The switching circuit provides a switching means for switching the oscillator between the normal power consumption mode and the lower power consumption mode and includes resistors R2, R3, R102 and R103, and a switching element, shown as a field-effect transistor Q2 in the illustrated embodiment. A bipolar transistor or a diode would also be suitable for use as the switching element in the present invention. Resistor R3 connects on one side to a DC voltage supply, shown in the illustrated embodiment as the DC voltage supply terminal V CC . One side of resistor R2 connects to the other side of resistor R3 and the other side of resistor R2 connects to ground. The drain of field-effect transistor Q2 connects to the common connection of resistors R2 and R3. The source of field-effect transistor Q2 connects through resistor R102 to ground. The gate of field-effect transistor Q2 is connected through resistor R103 to a switching voltage terminal V SW . Voltage is selectively applied to the switching voltage terminal V SW  by a power management controller PMC. The common connection of resistors R2 and R3 and the drain of field-effect transistor Q2 is connected to the base terminal B of transistor Q1. The field-effect transistor and resistors R2 and R102 thereby form a selecting means for selecting the resistance from the base terminal B to ground. 
     By way of example, and not limitation, the table below lists exemplary values for the components of the above described circuit for a frequency of about 900 MHz. 
     
         ______________________________________C1             47 pFC2             4.3 pFC3             2.0 pFC4             3.9 pFC5             1.0 pFC7             33 pFC9             39 pFC11            33 pFCR1            19 to 10 pF over 1 to 4 voltsL2             8 nHR2             2 kΩR3             2 kΩR4             91 ΩR5             68 ΩR7             68 ΩR103           10 kΩR102           2 kΩVcc            3 VVsw            3 VVt             0-5V______________________________________ 
    
     The switching circuit functions by reducing the voltage at the base terminal B when the field-effect transistor Q2 is on, thereby reducing the voltage at the emitter terminal E and thereby reducing the current through the transistor Q1. The voltage V B  at the base terminal B is the potential between the common connection of field-effect transistor Q2, resistor R2 and resistor R3, and ground. When field-effect transistor Q2 is off, the voltage V B  is the potential across resistor R2 which equals V CC  ×R2/(R2+R3). 
     For the above illustrative values, V B  can be calculated to be 3V×2 kΩ/(2 kΩ+2 kΩ)=1.5V. The voltage difference between the base and emitter in a transistor is known to be about 0.7V so the voltage V E  at the emitter terminal is 0.8V. The current I C  through the collector terminal C is approximately the current I E  through the emitter terminal C which is V E  /R4, so I C  =0.8V/91 Ω=8.8 mA. This is the current level for the normal power consumption mode and is sufficient to meet the phase noise requirements for good fidelity and high data rates. 
     When field-effect transistor Q2 is on, the voltage V B  is the potential across the parallel resistance R2&#39; of resistors R2 and R102. The parallel resistance R2&#39;=(R2×R102)/(R2+R102) and V B  =V CC  ×R2&#39;/(R2&#39;+R3). For the illustrative values R2&#39;=(2 kΩ×2 kΩ)/(2 kΩ+2 kΩ)=1 kΩ and V B  =1 kΩ/(1 kΩ+2 kΩ)=1.0V. The emitter voltage V E  =1.0V-0.07V=0.3V and the collector current I C  =0.3V/91 Ω=3.4 mA. This is the current level for the lower power consumption mode and is sufficient to sustain oscillation. The current is reduced by more than 50% with a proportionate decrease in power consumption. 
     Although the present invention has been described with a certain degree of particularity, it is understood that the present disclosure has been made by way of example and that changes in details of structure may be made without departing from the spirit thereof.