Abstract:
Apparatus for efficiently supplying energy to a device in a circuit, the apparatus comprising a powered device having a critical path delay; delay line operative to model said critical path delay; control logic responsive to output from said delay line and operative to generate control output; and a power converter operative to adjust supply voltage to said powered device in response to said generated control output, wherein the delay line, the control logic, and the power converter cooperate to provide first order bang-bang control of said critical path delay.

Description:
RELATED APPLICATIONS  
       [0001]    This application claims the benefit of U.S. Provisional Application No. 60/345,127, filed Nov. 9, 2001, entitled “ADAPTIVE VOLTAGE REGULATOR FOR DIGITAL VLSI PROCESSORS”, the disclosure of which application is hereby incorporated herein by reference. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates in general to power consumption of powered devices in integrated circuits and in particular to the active control of such power consumption.  
           [0004]    2. Statement of the Problem  
           [0005]    The strong demand for low-power computing has been driven by a growing class of portable, battery-operated applications that demand ever-increasing functionalities with low-power consumption. The power consumption is also a limiting factor in integrating more transistors in VLSI (Very Large Scale Integration) chips for portable applications. The resulting heat dissipation also limits the feasible packaging and performance of the VLSI chip and system. Because of the quadratic dependence of power consumption on the supply voltage, reducing the supply voltage level is an effective way to reduce power consumption. However, lower supply voltage for a given technology leads to increased gate delay, and consequently, a powered device has to be operated at a reduced clock rate. More recently, adaptive (or dynamic) voltage scaling (AVS) has been proposed as an effective power management technique. Using this approach, the system supply voltage and the clock frequency of a digital VLSI application are dynamically adjusted to meet the requirements of the powered device. By reducing the supply voltage and the clock frequency of a powered device, adaptive voltage scaling offers, in principle, superior power savings compared to simple on/off power management. Successful applications have included digital signal processing systems, I/O (Input/Output) interface, and general-purpose microprocessors. At a system level, AVS requires a voltage/frequency scheduler that can intelligently vary the speed depending on requirements of a powered device. At the hardware implementation level, a desired AVS component is a controller that automatically generates the minimum voltage required for the desired speed. Desirable features of an AVS controller include: high efficiency of the power converter used to generate the variable supply voltage; an ability to make voltage adjustments over a very wide range of clock frequencies to accommodate processing speeds from stand-by to maximum throughput; and stable and fast transient response to minimize latency and losses when switching between different speed levels. Voltage regulation systems for adaptive voltage scaling include frequency locked loop (FLL) based schemes, phase locked loop (PLL) based schemes, and a delay line based speed detector. In these approaches, the control loop design requires a careful compromise between the loop stability and dynamic response times. In addition, the capture range of PLL or FLL based schemes may limit the achievable range of operating system clock frequencies. Also, since the system clock in a PLL/FLL scheme is generated by a Voltage Controlled Oscillator (VCO) operating from the supply voltage, the system clock suffers from variable clock jitter due to supply voltage noise.  
           [0006]    One existing voltage regulation system employs a delay line based clock frequency detector. This system compares the extent of propagation of a signal through two circuits. The first circuit is a replica of a device being powered by the controlled supply voltage, V DD , and the second circuit includes the described replica and one additional component which introduces an additional delay. The result of a comparison of signal propagation in the two circuits generates a value supplied to an accumulator. The accumulator value is appropriately updated with the supplied value, and in turn, supplies the updated accumulator value to a duty cycle controller within a Buck converter. Thereafter, the Buck converter employs a second order system to produce a voltage output based on the updated accumulator value.  
           [0007]    The above-described approach involves a third order system which introduces several problems. One problem is that the disclosed delay line requires many system clock cycles to complete an evaluation of the instant clock speed sufficiency. The time needed to update the accumulator and establish a modified duty cycle adds more delay to the system. Finally, the second order circuit located between the duty cycle controller and the voltage output introduces still more delay.  
           [0008]    The various processing stages of the existing system risk incurring instability in the control loop which controls the voltage supplied to both the powered device and the delay line circuit. Accordingly, the bandwidth of this voltage regulation system is deliberately limited to provide stability. However, limited regulation bandwidth introduces performance limitations. Specifically, during a high-to-low voltage transition, a slower-than-needed reduction in supply voltage will incur excess power consumption, thereby partially defeating the purpose of voltage control. Moreover, during a low-to-high voltage transition, an excessively slow supply voltage increase runs the risk of disabling proper operation of the powered device.  
           [0009]    Separately, it is a problem that twice replicating the circuitry of the powered device in a delay line requires the allocation of much valuable space within an integrated circuit. Therefore, there is a need in the art for a system and method for device voltage regulation which is compact, inherently stable over a wide range of system frequencies, and highly responsive to the instantaneous voltage supply requirements of a powered device.  
         SOLUTION  
         [0010]    The present invention advances the art and helps to overcome the aforementioned problems by providing voltage regulation to a powered device employing a first order system which is highly responsive and stable over a wide range of frequencies. The voltage regulation system (adaptive voltage scaling system) preferably employs first order bang-bang control to control the critical path delay of a device powered by a regulated voltage. This control system approach effectively forces the critical path delay to remain within a defined working delay range. Controlling the critical path delay as described is accomplished by forcing the voltage supplied to a powered device to remain as low as possible for a desired system clock frequency. The disclosed bang-bang control system is both inherently stable and highly responsive to transient conditions over a wide range of system clock frequencies. Moreover, in the embodiments disclosed herein, the system clock frequency and supply voltage (to the powered device) are generated independently, thereby minimizing the problem of system clock jitter.  
           [0011]    In one embodiment, the critical path delay of a powered device is controlled by measuring propagation of a test signal through a delay line and providing a voltage control output responsive to the measured test signal propagation. For example, an excessively long critical path delay of a powered device is measured by detecting a shorter-than-desired extent of test signal propagation through a delay line. The voltage regulation system preferably increases the supply voltage to the powered device in response to this condition.  
           [0012]    Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings in which: 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    [0013]FIG. 1A is a plot of supply voltage V DD  as a function of time;  
         [0014]    [0014]FIG. 1B is a plot of critical path delay as a function of time;  
         [0015]    [0015]FIG. 2 is a block diagram of a system for controlling the critical path delay of a powered device;  
         [0016]    [0016]FIG. 3 is a more detailed block diagram of the delay line shown in simplified form in FIG. 2;  
         [0017]    [0017]FIG. 4 is a schematic diagram of a typical delay cell shown in simplified form in the delay line of FIG. 3;  
         [0018]    [0018]FIG. 5 is a plot of the relation between a test clock signal and precharge signals;  
         [0019]    [0019]FIG. 6 is a schematic diagram of the control logic used to generate control signals for input to a power converter;  
         [0020]    [0020]FIG. 7A is a state diagram showing the state of the CONT_IN signal as a function of data outputs from the delay line of FIG. 3;  
         [0021]    [0021]FIG. 7B is a state diagram showing the state of the CONT_DIS signal as a function of a set of data outputs from the delay line of FIG. 3;  
         [0022]    [0022]FIG. 8 is a schematic diagram of the power converter shown in FIG. 2;  
         [0023]    [0023]FIG. 9A is a schematic of a network for modeling the response of the power converter of FIG. 8 to a step change from a low value to a high value of an external clock frequency;  
         [0024]    [0024]FIG. 9B is a schematic representation of a network for modeling the response of the power converter of FIG. 8 to a step change from a high value to a low value of an external clock frequency;  
         [0025]    [0025]FIG. 10 is a block diagram of a fabricated chip with an external power converter providing voltage supply regulation for a 6×6 multiplier with registered outputs;  
         [0026]    [0026]FIG. 11 is a plot of V DD  as a function of external clock frequency;  
         [0027]    [0027]FIG. 12 is a plot of power consumption versus frequency for different voltage supply conditions;  
         [0028]    [0028]FIG. 13 is a plot of power efficiency of an external voltage regulator versus external clock frequency when using a closed loop control scheme as disclosed herein;  
         [0029]    [0029]FIG. 14 is a plot of a supply voltage, control signal CONT_IN, and inductor current i L  for the transient time period for a step change in an external clock signal frequency from 20 KHz to 40 MHz; and  
         [0030]    [0030]FIG. 15 is a flow chart of a critical path delay control scheme. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0031]    In one embodiment, “bang-bang control” is a type of control in which a control output value is either at its maximum, zero, or minimum. In another embodiment, bang-bang control is a type of control in which the output assumes only two possible values: a maximum value or a minimum value. In this disclosure, a first order control system is a system in which a “high” or “maximum” control signal value changes the output variable of interest in a first direction, and a “low” or “minimum” control signal value changes the output variable in a second direction opposite the first direction. In this disclosure, “control output” is one or more control signals output from a control logic circuit. In this disclosure, a control signal is preferably an output from a control logic circuit and an input to a power converter. Preferably, the output from a power converter or other system receiving one or more control signals is an output variable.  
         [0032]    In this disclosure, a “powered device” is a device being powered by a supply voltage. A “task” is an operation performable by the powered device. A “critical path delay” is the time required for a signal to propagate through the longest path in the powered device. “Test signal propagation” is the propagation of a test signal along a path. A “critical path model” is a sequence of cells (integrated circuit components) which models at least a portion of the critical path delay of a powered device.  
         [0033]    A discussion of elements of a selection of the FIGS. is presented in this section. The function associated with matter depicted in all of FIGS.  1 - 14  is discussed thereafter. FIG. 2 is a block diagram  200  of a system for controlling critical path delay  152  of powered device  204 . In FIG. 2, signal C extclk    208  feeds into clock logic  202  which in turn provides output signals C prec    212 , C test    214 , and {overscore (C prec )}  216  to delay line  300 . Signal C sysdlk    210  is directed from clock logic  202  to powered device  204 . Delay line  300  is preferably coupled to level shifter array  350 , which in turn provides signals DATA2  220 , DATA1  222 , and DATAH  224  to control logic  600 . Signal C test    214  is also directed to control logic  600 . DATAL  226  is directed from level shifter array  350  to clock logic  202 .  
         [0034]    In one embodiment, signals CONT_IN  602 , CONT_OUT  604 , and CONT_DIS  606  are directed from control logic  600  through drivers  206  to power converter  800 . Voltage V DDH    218  is supplied to power converter  800 , and voltage V DD  is directed from power converter  800  to power device  204  and delay line  300 .  
         [0035]    [0035]FIG. 4 is a schematic of a typical delay cell 400 shown in simplified form in the delay line of FIG. 3. In FIG. 4, M1  406 , M2  410 , M3  414 , and M4  416  maybe any type of transistor or other switch. For the sake of the following discussion, each of transistors M1-M4 is considered to have one switching connection, or gate, and two switched connections. V DD    102  is preferably connected to the upper switched connections of both M1  406  and M3  414 . The lower switched connection of M1 is connected to node “a”  408  and to the upper switched connection of M2  410 . The lower switched connection of M2  408  is preferably connected to ground  418 . Node “a”  408  is preferably connected through an inverter to the gate of M3  414 . The lower switched connection of M3  414  is preferably connected to node “b”  412  and to the upper switched connection of M4  416 . The lower switched connection of M4  416  is preferably connected to ground  418 .  
         [0036]    In one embodiment, signal C prec    212  is connected through an inverter to the gate of M1  406 . Signal “in”  402  is preferably connected to the gate of M2  410 . Signal  216  corresponding to {overscore (C prec )} is preferably connected to the gate of M4  416 .  
         [0037]    [0037]FIG. 6 is a schematic representation of control logic  600  used to generate control signals  602 ,  604 , and  606  for input to power converter  800 . In FIG. 6, DATA1  222  and feedback from CONT_IN signal  602  are preferably directed to AND gate  608 . Output  618  from AND gate  608  is preferably directed to OR gate  610  along with DATA2  220 . The output  620  from OR gate  610  is preferably directed to clocked flip-flop  614  which is clocked by C test    214 . CONT_IN signal  602  is the output from flip-flop  614 .  
         [0038]    In one embodiment, signal {overscore (DATAH)}  622  is directed to clocked flip-flop  616 , which flip-flop is clocked by signal C test  signal  214 . The output from flip-flop  616  is CONT_DIS signal  606 . Preferably, CONT_IN signal  606  and CONT_IN signal  602  are directed to OR gate  612 , which produces OR gate  612  output signal CONT_OUT  604 .  
         [0039]    [0039]FIG. 8 is a schematic diagram of power converter  800  shown in FIG. 2. In the context of FIG. 8, diodes D1-D4 are preferably Schottky diodes. V DDH    218  is preferably applied across node  820  (positive side of V DDH ) and node  822  (negative side of V DDH ). Signal CONT_IN  602  is supplied to the gate of transistor Q1  806  which connects node  820  to node  824 . Diode D4  808  is preferably connected in parallel with transistor Q1  806 , in between node  820  and node  824 , with the diode oriented to allow current flow from node  824  to node  820 . Inductor  802  is located between node  824  and node  826 . Diode D2  810  is preferably located in a separate conductive path. between node  820  and node  826 , in parallel with the sequence of the parallel combination of D4  808  and Q1  806 , followed by inductor  802 . Diode D2  810  is preferably oriented to allow current flow from node  826  to node  820 .  
         [0040]    Preferably, signal CONT_DIS is directed to the gate of transistor Q3  812  which couples node  824  to node  822 . Diode D1  814  is preferably located on a separate conductive path between node  824  and node  822 , in parallel with transistor Q3  812 . Diode D1  814  is preferably oriented to allow current flow from node  822  to node  824 . Preferably, diode D3  816  is located on a conductive path between node  826  and node  822 . Diode D3  816  is preferably oriented to allow current flow from node  822  to node  826 . Preferably, signal CONT_OUT  604  is directed to the gate of transistor Q2  818  which transistor&#39;s switched connections are coupled to node  826  and node  828 . Capacitor  804  and powered device  204  are connected in parallel between node  828  and node  822 .  
         [0041]    In one embodiment, the critical path delay of a powered device is controlled by controlling the supply voltage V DD    102  for the powered device. One way of controlling critical path delay  152  of powered device  204  (FIG. 2) is illustrated by the waveforms in FIG. 1. For a particular clock frequency of powered device  204 , a change of V DD    102  within the limits V DDmax    104  and V DDmin    106  results in critical path delay  152  varying non-linearly between limits t dmin    166  and t dmax    164 .  
         [0042]    A preferred bang-bang control scheme for critical path delay t d    152  operates as described below. Reference is made to FIG. 1 and FIG. 15 in the following discussion. Operation preferably starts at step  1502  of flow chart  1500 . Preferably, an upper limit t dmax    164  and a lower limit t dmin    166  are established  1504 . Critical path delay t d    152  is then preferably measured  1506 . The measured critical path delay t d    152  is then preferably compared  1508  to the lower limit t dmin    166 . If critical path delay  152  is greater than the lower limit t dmin    166 , a control signal is preferably activated to increase  1514  supply voltage V DD    102  . Measurement  1506  and comparison  1508  of critical path delay  152  with lower limit t dmin    166  is then preferably repeated. The control signal activated to increase  1514  supply voltage V DD    102  preferably remains unchanged until critical path delay  152  is at lower limit t dmin    166 . When critical path delay  152  becomes equal to lower limit t dmin    166 , the control signal is preferably activated to reduce  1516  supply voltage V DD    102 . Preferably, critical path delay  152  is then measured  1512  and compared  1510  to upper limit t dmax    164 . The control signal to reduce  1516  supply voltage V DD    102  preferably remains unchanged until critical path delay  152  equals upper limit t dmax    164 . When critical path delay  152  is at upper limit t dmax    164 , the control signal is preferably activated to increase  1514  supply voltage V DD    102 . The range of critical path delay  152  which is less than upper limit t dmax    164  and greater than lower limit t dmin    166  is the “working delay range.” As long as time variations of V DD    102  are monotonic (increasing or decreasing depending on the control signal), and t d    152  is a monotonic function of VDD  102 , the control loop is stable, and the transient response is determined by the system open-loop response.  
         [0043]    [0043]FIG. 2 is a block diagram of a system  200  for controlling the critical path delay  152  of a powered device  204 . System  200  preferably includes five components. A first component is power converter  800  which preferably receives V DDH    218  as the input voltage and produces the supply voltage V DD    102 , which is generally less than V DDH    218 , for powered device  204 . A second preferred component is delay line  300  which is powered by supply voltage V DD    102  and which is preferably driven by the test clock signal C TEST    214  and precharge clocks C PREC    212  and {overscore (C PREC )}  216  at a desired system clock frequency  210  for powered device  204 . Clock frequencies between 10 KHz (Kilohertz) and 40 MHz (MegaHertz) have been employed. A third preferred component is level shifter array  350  which converts the test signal voltages taken from various taps across delay line  300  to voltage levels compatible with control logic  600 .  
         [0044]    In one embodiment, a fourth preferred component is control logic  600  which completes a control loop and which is preferably updated with every falling edge of C TEST    214 . A fifth preferred component is clock logic  202  which preferably generates test clock signal C TEST    214  which is non-overlapping with the precharge clocks, C PREC    212  and {overscore (C PREC )}  216 , and the system clock signal  210 .  
         [0045]    In one embodiment, delay line  300  in system  200  is made up of several identical cells grouped in two sections as shown in FIG. 3. Section 1  310  preferably includes N cells, which include critical path model  324 , which models half the critical path delay  152  of powered device  204 . Section 1  310  preferably also includes a small safety margin  162  (FIG. 1). Section 2  312  preferably includes K cells. A first part of Section 2  312  preferably includes ΔN cells (ending with cell  306 ) that model delay ripple Δ t d  160=t dmax  164−t dmin  166. The remaining K−ΔN cells are used, to determine when V DD    102  has exceeded its desired level according to the above-described control scheme.  
         [0046]    Operation of delay line  300  is understood by referring to the device level schematic of exemplary delay cell  400  shown in FIG. 4 and clock waveforms  500  of FIG. 5. When precharge clock C prec    212  is at logic 0, devices M1  406  and M4  416  preferably precharge node “a”  408  and node “b”  412  to logic 1 (i.e., V DD ), and 0 (ground), respectively. When test signal C TEST    214  is at logic 1, test signal  214  preferably propagates from node “in”  402  to node “out”  412  via devices M 2    410  and M 3    414 .  
         [0047]    For first cell  310  in delay line  300 , input node in  402  is preferably connected to signal C TEST    214 . For the remaining cells, the node out i−1  is connected to the node in i . Referring to FIG. 3, signal taps are taken from delay cells S  312 , N+1  304 , N+ΔN  306 , and N+K  308  and are preferably level-shifted for compatibility with control logic  600 , which is preferably powered by V DDH    218 . These signals drive the transistors Q Li ( 314 ,  316 ,  318 , and  320  ) and pull nodes DATAi ( 220 ,  222 ,  224 , and  226 ) to logic 0 if C TEST    214  propagates through delay line  300  within system clock period  154  (FIG. 1). In desired steady state operation, V DD 102  is sufficient for C TEST    214  to propagate through cell N  302  but not high enough for it to propagate through cell N+K  308 .  
         [0048]    It is known in the art that the delay of a simple logic gate can accurately represent the delay in more complicated structures. Therefore, a delay line, such as delay line  300  in FIG. 4, can be used to model the critical path delay of a powered device. Modeling a critical path delay may be accomplished by testing the powered device at a process corner which allows the application to work at its maximum speed under worst-case input data conditions, i.e., at a maximum supply voltage, and at a maximum clock frequency f sysclk.max . Preferably, a delay cell is then designed using the model parameters for that process corner. Next, a delay line length N+ΔN is selected such that a test clock signal, such as C test    214  in FIG. 3, at the maximum system clock frequency, is just able to propagate through the selected delay line when the supply voltage to the delay line is at its maximum value. The selected delay. line length N+ΔN is a product of the sizes and associated propagation delays of the individual cells selected for inclusion in the delay line.  
         [0049]    The selection of device sizes also affects the output voltage ripple ΔV DD    108 . Since testing critical path delay  152  of powered device  204  takes one half of system clock period  154  (i.e. when C TEST    214  is at logic 1), a preferred critical path model effectively captures half of the worst-case critical path delay of a particular powered device. Where a delay line is fabricated on the same chip as a powered device, the delay line characteristics preferably scale with the application for voltage, process, or temperature variations.  
         [0050]    It should be noted that for proper testing of the V DD    102  value, C TEST    214  preferably has a 50% duty cycle. Instead of placing this responsibility on the external clock, in a preferred embodiment, the test clock and the system clock are obtained by dividing an external clock (at f extclk =2f Sysclk ) by 2.  
         [0051]    [0051]FIG. 6 shows the implementation of the control logic  600  which receives level-shifted delay line taps DATA2  220 , DATA1  222 , and {overscore (DATAH)}  622  as inputs and outputs control signals CONT_IN  602 , CONT_OUT  604 , and CONT_DIS  606  to power converter  800 . Preferably, a logic “1” at a representative input DATAi implies that C test    214  did not propagate to that input within system clock period  154 .  
         [0052]    Signals  602 ,  604 , and  606  are explained below with reference to the power converter  800  shown in FIG. 8. In the following, Q1-Q3 may be transistors or other types of switches. CONT_IN signal  602  preferably controls input side switch Q 1    806 . When turned on, switch Q 1    806  preferably connects V DDH  to the converter network. CONT_OUT signal  604  controls output side switch Q 2    818 . When turned on, switch Q 2    818  allows the charging or discharging of output capacitor  804  through power converter  800 . CONT_DIS signal  606  preferably controls output discharge switch Q 3    812 . When turned on in conjunction with switch Q 2    818 , it allows capacitor  804  to discharge through inductor  802 .  
         [0053]    [0053]FIGS. 7A and 7B are state diagrams for control outputs CONT_IN  602  and CONT_DIS  606 . CONT_OUT  604  preferably equals the logic sum of control signals CONT_IN  602  and CONT_DIS  606  (see FIG. 6). For example, during steady state operation, inputs to control logic  600  (DATA2  220 , DATA1  222 , and {overscore (DATAH)}  622 ) have values (0,1,1) which indicate that V DD    102  is high enough for C test    214  to propagate through delay cell N  302  (FIG. 2), but not high enough to propagate through the additional delay ripple of ΔN cells ending with cell N+ΔN  306  (FIG. 2 ). Depending on the previous state of the converter switches  808  and  812  and the supply voltage limit (V DDmin  or V DDmax ) reached, power converter switches  808  and/or  812  are turned on or off.  
         [0054]    While any step-down switch-mode power converter should suffice, a desirable property of power converter  800  is that in steady state operation V DD    102  should start increasing when control signal CONT_OUT  604  is at logic “1” and start decreasing when CONT_OUT  604  is at logic “0”. This allows for a simple, stable bang-bang control of critical path delay  152  and therefore of the output voltage ripple.  
         [0055]    Power converter  800  (FIG. 8) is preferably a modified Watkins-Johnson (WJ) converter. The WJ converter has the desirable property that the output voltage will always decrease when the converter switches are turned off as compared to a standard step-down (buck) converter. Power converter  800  is preferably operated in the discontinuous conduction mode (DCM) in steady state so that converter switches Q 1    806  and Q 2    818  only turn on for short time periods. Current through inductor  802  is generally discontinuous and is preferably zero at the end of converter  800  switching period.  
         [0056]    To minimize latency and/or additional losses, it is desirable to have fast transient response to step changes in system clock frequency  210 . The transient response of power converter  800  to a step change from low to high f Extclk  is preferably determined by a simple open loop model shown in FIG. 9A. Where power converter  800  operates sin DCM, current through inductor  802  is initially zero. During a voltage transient, supply voltage V DD    102  is too low to enable operation of powered device  204 , and system clock signal C sysclk    210  (FIG. 2) is disabled. During this time, powered device  204  consumes almost no current (i≈0). As a result, i L (t)=i C (t) during the transient. Capacitor  804  voltage V DD (t) is at some initial value V DD0 . At t=0, switches Q 1    806  and Q 2    818  are closed, and voltage V DDH    218  is applied across terminals  820 ,  822  of the network  800 . Equation (1) enables determination of the time taken for the capacitor voltage to reach a value V DD1 &gt;V DD0 .  
               t     low              →              high       =       LC     ·       cos     -   1            (         V   DDH     -     V   DD1           V   DDH     -     V   DD0         )                 (   1   )                               
 
         [0057]    Similarly, the transient response of power converter  800  to a step change from high to low f Extclk  is determined by the simple open-loop model shown in FIG. 8( b ). Preferably, inductor  802  current is initially zero. Preferably, capacitor  804  is at some initial voltage V DD0  and discharges with load current i. At t=0, switches Q 2    818  and Q 3    812  are turned off, and capacitor  804  also discharges through inductor  802 . It is desired to determine the time needed for capacitor  804  voltage to reach a value V DD1  &lt;V DD0 . Where load current is ignored for the sake of simplicity, the solution is provided by equation (2).  
               t     high              →              low       =       LC     ·       cos     -   1            (       V   DD1       V   DD0       )                 (   2   )                               
 
         [0058]    Generally, the actual transient time is less than that indicated by equation (2), since capacitor  804  may also discharge through powered device  204 . Equations (1) and (2) show that the transient responses are of the order of the square root of LC.  
         [0059]    In steady state operation, switches  806 ,  812 ,  818  turn on for a short time interval t ON , charging capacitor C  804  to V DDmax    104 , followed by a longer period t OFF  over which capacitor  804  discharges to V DDmin    106 . Where t off  is much longer than t on , the capacitor  804  charging period can be ignored, and the switching period of the converter T sw  equals t OFF .  
               T   sw     =       t   OFF     =         C   ·   Δ                     V   DD       I               (   3   )                               
 
         [0060]    Consequently the converter switching frequency f sw  can be given as:  
               f   sw     =       I       C   ·   Δ                     V   DD         =     P         V   DD     ·   C   ·   Δ                     V   DD                   (   4   )                               
 
         [0061]    where P is the power consumption of powered device  204 . However, ΔV DD    108  depends on the delay line parameters (N and ΔN) and V DD    102 . This dependence can be found as follows. At the minimum value of V DD    102 , V DDmin , the delay through the critical path model is provided by equation (5):  
           t   N   =N·t   cell   =N·g ( V   DD )   (5)  
         [0062]    where t cell  is the delay through a delay-cell and is a function of V DD , i.e., t cell =g(V DD ).  
         [0063]    At the peak value of V DD    102 , V DDmax , the delay through the delay line is given by equation (6).  
           t   N   +ΔN =( N+ΔN )· g ( V   DD   +ΔV   DD )   (6)  
         [0064]    Since the delays shown in equations (5) and (6) represent the test portion of C TEST    214 , the two delays are equal. Equating the two sides and simplifying by keeping only the linear terms in the Taylor expansion gives us:  
               Δ                   V   DD       ≈         Δ                 N     N     ·       g        (     V   DD     )           g   ′          (     V   DD     )                   (   7   )                               
 
         [0065]    Furthermore, the relation between t cell  and V DD    102  was obtained by a curve-fit to be approximated as:  
                 g        (     V   DD     )       =     K       (       V   DD     -     V   0       )     1.5         ,             K   =     2.736   ·     10     -   9           ,                 V   0     =   0.74                   (   8   )                               
 
         [0066]    Taking the derivative and substituting in equation (7), we have:  
               Δ                   V   DD       ≈       2   3     ·       Δ                 N     N     ·     (       V   DD     -     V   0       )               (   9   )                               
 
         [0067]    As V DD    102  increases, so does ΔV DD . The delay line parameters N and ΔN can thus be set to limit the output voltage ripple at the maximum supply voltage. The output voltage ripple is not determined by the converter parameters, which is an advantage of the scheme since it allows for straightforward design of power converter  800 . To a first order, the power consumption P of powered device  204  is given by equation (10).  
           P≈C   pd   ·V   DD   2   ·f   Sysclk    (10)  
         [0068]    where C pd  (capacitance of powered device) is a constant. Substituting for P and ΔV DD  in equation (4) yields:  
               f   sw     ≈       3   2     ·       C   pd     C     ·     N     Δ                 N       ·       V   DD       (       V   DD     -     V   0       )       ·     f   Sysclk               (   11   )                               
 
         [0069]    Since the test period is also one half of the system clock period  154 , f sysclk  can be related to V DD    102  using equation (8), which yields:  
               f   Sysclk     =       1     2   ·   N   ·     g        (     V   DD     )           ≈         (       V   DD     -     V   0       )     1.5       2   ·   N   ·   K                 (   12   )                               
 
         [0070]    Substituting in equation (11) gives us:  
               f   sw     ≈       3   4     ·       C   pd     C     ·         V   DD              V   DD     -     V   0             Δ                   N   ·   K                   (   13   )                               
 
         [0071]    This relation indicates that the converter switching frequency increases with V DD  (and f Sysclk ). This is desirable, because it implies that the converter switching frequency scales with system clock frequency. As a result, switching losses in the converter also scale with powered device  204  load power, and power converter  800  can maintain relatively high efficiency over a wide range of operating conditions.  
         [0072]    As shown in equations (1), (2), and (13), f sw  (power converter  800  switching frequency) is inversely proportional to the capacitance of capacitor  804 , and the transient responses are of the order of the square root of LC. Hence, C (the capacitance value of capacitor  804  ) can be selected to set the switching frequency. It is desirable to have a small capacitance value for capacitor  804  so that the transient response is faster, and losses during the transient period smaller. However, a higher switching frequency generally results in higher switching losses, which reduce the steady-state power efficiency of the converter. Using equation (10), C pd  can be determined from power consumption of the application for the measured V DD  and f Sysclk . N and ΔN have already been selected to limit the output voltage ripple. Hence, the capacitance value of capacitor  804  (“C”) can be selected to set the maximum switching frequency at the maximum supply voltage. Once C has been selected, L (the inductance of inductor  802  ) is selected to adjust the transient response time. The lower limit on transient time is constrained only by the ability of power switches to conduct increased peak inductor current and the conduction losses in the converter switches.  
         [0073]    One preferred embodiment of system  200 , except for external L and C, was designed in a standard Complementary Metal Oxide Semiconductor (CMOS) process. Extensive Spice simulations were performed on system  200 . A chip implementing the system  200  was designed in a 1.5 micron standard CMOS process. In one embodiment, the area taken up by system  200  including pads is 0.88 mm 2 .  
         [0074]    In one exemplary embodiment of a critical path delay control system, shown in FIG. 10, the chip contains a 6×6 array multiplier, which was used as an exemplary powered device for the system. The outputs of multiplier  1002  are registered and are updated at the rising edge of system clock  1004 . A model extracted from the layout of the multiplier was simulated at the typical process corner to determine that under worst-case input data conditions, and at an operating frequency of 20 MHz, the multiplier needed a supply voltage of 2.8V.  
         [0075]    The parameters used in the typical process corner model were then used to design the critical path model of the delay line  1006 , with appropriate sizing of the devices in the delay-cell such that for delay line length N+ΔN=20, (ΔN=2), a test clock pulse  1004  at 20 MHz and V DD =2.8 V was just able to propagate to the level-shifted tap DATA2  1008 . With these parameters, the maximum ΔV DD  is about 150 mV at a V DD  value of 2.8V (see equation (7)).  
         [0076]    A test circuit for voltage control of multiplier  1002  was designed with power converter  1010  closing a control loop externally as shown in FIG. 10. The delay line for the fabricated chip does not include the delay cells to detect high V DD    1014 . Also, during a step change from high to low f Etclk , the capacitor is simply allowed to discharge to the lower supply voltage value. From power consumption measurements of the multiplier, C m  (capacitance of the multiplier) was estimated to be about 4 pF (picoFarad). It was desired to have a converter  1010  switching frequency of about 50 kHz at the maximum supply voltage. A capacitance value of 47 nF (nanoFarad) for capacitor  1012  was selected by substituting for values in equation (13).  
         [0077]    Separately, it was desired to have a worst-case transient response of less than 15 microseconds for a step change from the lowest system clock frequency of 10 kHz, with V DD =0.8 V, to the highest system clock frequency of 20 MHz, where V DD =2.8 V. Using equation (1), a value of 750 microHenries was selected for the value of inductor  1016 .  
         [0078]    A plot  1104  of V DD    1014  as a function of f Extclk    1102  is shown in FIG. 11. It is observed that the control loop provides V DD    1014  over a very wide range of f Exclk    1102 , which is an advantage of the proposed controller. It is possible to realize very low power stand-by operation at very low clock frequency. The proposed controller also makes it possible to maintain the supply voltage close to the threshold voltage of the devices.  
         [0079]    [0079]FIG. 12 shows the measured power consumption  1202  as a function of f Extclk    1102  of the powered device  1002  (FIG. 10) compared to fixed V DD  operation. For illustration, plot  1208  shows the power consumption  1202  of powered device  1002  alone as a function of external clock frequency  1102 . In contrast, plot  1206  shows the power consumption  1202  of powered device  1002  in addition to power consumed by converter  1010  losses.  
         [0080]    The power consumption levels shown in FIG. 12 are low due to the relatively low level of complexity of multiplier  1002 . The power efficiency η  1302  of power converter  1010  over this range of frequencies is plotted  1300  in FIG. 13. Due to low output power levels from converter  1010 , converter  1010  losses become significant only at very low frequencies, resulting in low η  1302 .  
         [0081]    A second test was designed to demonstrate the fast transient response of the control loop from the lowest operating supply voltage to the maximum supply voltage. Two external clock frequencies, f 1,ext =20 kHz and f 2,ext =40 MHz, were applied to a switch that alternated between the two frequencies. Details of this transient response around the vicinity of the step change in frequency are plotted  1400  in FIG. 14. The transient from V DD =0.8 V  1402  to V DD =2.8 V  1404  takes about 12 microseconds, which compares favorably with results described in the prior art.  
         [0082]    Adaptive voltage scaling (AVS) of a supply voltage is emerging as an effective power management technique for digital VLSI applications. This disclosure describes a delay line based regulation scheme which is simple to implement and which allows fast transient response to step changes in speed and stable operation over a very wide range of system clock frequencies. The delay is preferably measured at the system clock rate, which minimizes the system latency. The Watkins-Johnson converter has been shown to be well suited for closed loop delay line regulation. The design criteria for the selection of the converter components is straightforward and is described. A chip including the AVS controller and a small test application has been fabricated in a standard CMOS process. Experimental results demonstrate operation over the clock frequency range from 10 KHz to 20 MHz, and a 12 microsecond transient response for a step change in system clock frequency from 10 kHz to 20 MHz.  
         [0083]    There have been described what are, at present, considered to be the preferred embodiments of the invention. It will be understood that the invention can be embodied in other specific forms without departing from its spirit or essential characteristics. For instance, each of the inventive features mentioned above may be combined with one or more of the other inventive features. That is, while all possible combinations of the inventive features have not been specifically described, so as the disclosure does not become unreasonably long, it should be understood that many other combinations of the features can be made. The present embodiments are, therefore, to be considered as illustrative and not restrictive. The scope of the invention is indicated by the appended claims.