Abstract:
A method of manufacturing an electronic structure, which structure comprises a first power device and a second unidirectional device, both integrated in the same protective package. The first device having at least first and second electrodes of the first device, with said first electrode of the first device being attached to the package. The second device having first and second electrodes of the second device, wherein the first electrode of the second device is superposed on the second electrode of the first device and connected electrically to the second electrode of the first device.

Description:
FIELD OF APPLICATION  
         [0001]    The present invention relates to a method for manufacturing an electronic power device and a diode in a same protective package. Specifically, the invention relates to a method of manufacturing an electronic structure, which structure comprises a first power device and a second unidirectional device, both integrated in the same package; said first device having first and second electrodes of said first device, with said first electrode being attached to said package; and said second device having first and second electrodes of said second device. The invention also relates to an electronic structure which comprises a first power device and a second unidirectional device realized in package.  
           [0002]    The invention relates, particularly but not exclusively, to a method of manufacturing a power device of the IGBT type and a feedback diode in the same package, and the following description is made with reference to this application field, with the only aim to simplify its explanation.  
         BACKGROUND  
         [0003]    Electronic devices of the IGBT (Insulated Gate Bipolar Transistor) type can be used in place of MOS-type field-effect transistors. IGBT devices are used in preference of P-MOS transistors on account of improved electrical characteristics in particular conditions of use. Especially in applications where medium to high voltages, e.g. above 400 V, are provided, a lower voltage drop in the “on” state can be obtained for an IGBT, typically at a working frequency on the order of tens of kHz.  
           [0004]    A limitation to the use of IGBT components comes from the lack of a feedback diode therein which be effective to pass a current as the collector-to-emitter bias voltage is reversed, e.g. in motor control applications as shown in FIGS. 1 and 2. (This diode is instead inherent to the structure of P-MOS devices.) Specifically, in motor control applications, each line of a three-phase motor M is controlled by a microcontroller, through an IGBT device having a feedback diode connected in parallel with it.  
           [0005]    Solutions to the problem of providing an IGBT component with a feedback diode have been offered.  
           [0006]    A first approach provides a feedback diode connected between the collector and the emitter of the IGBT, and is illustrated by FIGS. 3 a  and  3   b . The feedback diode is mounted to a common heat-sink type of holder P within a common package. This construction is referred to as “chip-to-chip”.  
           [0007]    [0007]FIG. 3 a  is a sectional view of a portion of a first chip  1  of a semiconductor material, such as monocrystalline silicon. This chip I comprises a substrate  2  doped with P type impurities in a relativity high concentration; an epitaxial layer  3  doped with N type impurities in a relativity low concentration, and denoted with N−; and an N+ buffer layer  4  between the substrate  2  and the epitaxial layer  3 . At least a diffused region  5  of the P type extends from the surface of the chip  9  into the epitaxial layer  3 .  
           [0008]    Regions  6  having a high concentration of N dopant are formed within the diffused region  5 . Strips of a conductive material, such as doped polycrystalline silicon, denoted  7 , extend across the surface of region  5 , from region  6  to the epitaxial layer  3 , and are isolated from the front surface of the chip by a thin layer of a dielectric material.  
           [0009]    A metal electrode  8 , in contact with the bottom of the substrate  2 , forms the collector electrode of the transistor. A metal electrode  9  on the front surface of the chip contacts the P+ regions  5  and N+ regions  6 , but is isolated from strip  7  by a dielectric layer, e.g. of silicon oxide. The electrode  9  forms the emitter electrode of the IGBT. A metal electrode  11 , in contact with a peripheral portion of a region  7 , forms the gate electrode of the IGBT.  
           [0010]    A second chip  12  comprises a substrate  13  doped with N-type impurities at a relatively high concentration, denoted as N+, and an epitaxial layer  14  doped with N-type impurities at a relatively low concentration, denoted as N−. A diffused region  15  of the P type extends from the chip  12  surface into the epitaxial layer  14 .  
           [0011]    A metal electrode  16 , in contact with the bottom of the substrate  13 , forms the cathode of the diode. A metal electrode  17 , in contact with the diffused region in the front surface of the chip, forms the anode of the diode.  
           [0012]    [0012]FIG. 3 b  is a perspective view, not drawn to scale, of the chips  1  and  12  as bonded to the same holder in the package. Also shown are connections of the two interconnected devices to terminals GL, EL of the package P.  
           [0013]    Although advantageous on several aspects, this solution has a drawback in that, when the devices are realized with comparable geometries and compatible locations of the connection pads, the space inside the package is not optimized. Thus, packages having a much larger chip-accommodating area than the silicon (IGBT plus diode) area typically used. Even if an “ad hoc” design is implemented, such as by forming the IGBT and diode with rectangular outlines, the maximum silicon area inside the package would still be less than ideal, by reason of such assembly constraints as chip spacings, relative locations of pads, etc.  
           [0014]    A second solution, directed to obviate the above drawback, provides for the feedback diode to be formed in the same chip as the IGBT, utilizing an EQR (EQuipotential Ring) present on the IGBT chip and, accordingly, the diode which forms between an edge structure and the EQR, as shown in FIGS. 4 a  and  4   b.    
           [0015]    The device of these FIGS. has identical elements with those of the structure shown in FIG. 3 a  denoted by the same reference numerals. As mentioned above, this device differs from the previously described one in that the diode is formed in the same substrate as the IGBT.  
           [0016]    In particular, a diffused region  18  of the P-type is provided about the periphery of one of the diffused regions  5 . An additional metal electrode  19  establishes ohmic contact to the epitaxial layer  3  through a diffused region  20  which is heavily doped with N dopant and formed in the epitaxial layer  3 .  
           [0017]    While substantially achieving its object, this solution also has drawbacks. In fact, the diode&#39;s design dimension is restricted by the device being required to support high voltages, so that the side dimension of the diode has to be sufficiently large (greater than 60 μm), while its perimeter is limited by the package size.  
           [0018]    In addition, where the device manufacturing process includes a so-called “lifetime killing” step, the diode DC voltages are greatly increased by a diminished injection of carriers from the IGBT backside.  
           [0019]    In view of the foregoing, there is a need for power devices having feedback diodes electrically connected in parallel therewith, with appropriate structural and functional features to optimize the size and geometries of individual devices, as well as to overcome the limitations of the prior art methods.  
         SUMMARY OF THE INVENTION  
         [0020]    A principle on which one embodiment of the present invention stands is one of arranging for an IGBT device and NP diode to be stacked together in mutual electrical contact.  
           [0021]    Based on the above principle, the technical problem is solved by a method as previously indicated and defined in the characterizing part of claim 1.  
           [0022]    The problem is further solved by a structure as previously indicated and defined in the characterizing part of claim 9.  
           [0023]    The features and advantages of a device according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limited example with reference to the accompanying drawings, in the several FIGS. of which like referenced numerals identify like elements. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]    In the drawings  
         [0025]    [0025]FIG. 1 illustrates an exemplary application of a power device incorporating a feedback diode.  
         [0026]    [0026]FIG. 2 is a detail view of the application shown in FIG. 1.  
         [0027]    [0027]FIG. 3 a  is a sectional view taken through a portion of a semiconductor material chip containing a conventional device.  
         [0028]    [0028]FIG. 3 b  is a perspective view of the chip shown in FIG. 3 a , as mounted to a holder structure.  
         [0029]    [0029]FIG. 4 a  is a sectional view taken through a portion of a semiconductor material chip containing a conventional device.  
         [0030]    [0030]FIG. 4 b  is a perspective view of the chip shown in FIG. 4 a , as mounted to a holder structure.  
         [0031]    [0031]FIG. 5 a  is a sectional view taken through a portion of a semiconductor material chip containing a device formed according to an embodiment of the invention.  
         [0032]    [0032]FIG. 5 b  is a perspective view of the chip shown in FIG. 5 a , as mounted to a holder structure.  
     
    
     DETAILED DESCRIPTION  
       [0033]    [0033]FIGS. 5 a  and  5   b  show an electronic structure that comprises a power device  1 , such as an IGBT, connected in parallel with a unidirectional device  120 , such as a feedback diode, according to an embodiment of the invention. In the structure shown in these FIGS., elements that are like those of FIGS. 3 a  and  4   a , are denoted by the same reference numerals.  
         [0034]    [0034]FIG. 5 a  shows a cross-section of a portion of a chip  1  made of a semiconductor material, such as monocrystalline silicon. The chip  1  comprises: a substrate  2  doped with impurities of the P type at a relatively high concentration, denoted as P+; an epitaxial layer  3  doped with impurities of the N type at a relatively low concentration, denoted as N−; and an N+ buffer layer  4  provided between the substrate  2  and the epitaxial layer  3 . At least a diffused region  5  of the P type extends from the surface of the chip  9  into the epitaxial layer  3 .  
         [0035]    Formed within the at least a diffused region  5  are high doped regions  6  of the N type. Strips  7  of a conductive material, e.g. doped polycrystalline silicon, are locate above the surface of regions  5  and extend from region  6  into the epitaxial layer  3 , being isolated from the front surface of the chip by a thin layer of a dielectric material.  
         [0036]    A metal electrode  8 , in contact with the bottom of the substrate  2 , forms the collector electrode of the transistor. This electrode is bonded to the frame PF of the protective package.  
         [0037]    A metal electrode  9 , in contact with the P+ regions  5  and N+ regions  6  on the front surface of the chip, but being isolated from the strip  7  by a dielectric layer  10 , e.g. of silicon oxide, forms the emitter electrode of the IGBT. A metal electrode  11 , in contact with a peripheral portion of one region  7 , forms the gate electrode of the IGBT.  
         [0038]    According to an aspect of the invention, a conductive layer  180  is deposited onto a portion of the last-mentioned metal electrode  11  and aligned with it.  
         [0039]    Advantageously, in one embodiment, this conductive layer  180  is also a layer of a bonding compound or conductive glue.  
         [0040]    A chip  120  is placed onto the conductive layer  180 . This device  120  comprises: a substrate  130  which is doped with impurities of the P type at a relatively high dopant concentration, denoted as P+; and an epitaxial layer  140  which is doped with impurities of the P type at a relatively low dopant concentration, denoted as P−. A diffused region  150  of the N type extends into the epitaxial layer  140  from the surface of the chip  120 . A first metal electrode  170  is bonded on a first side to the substrate  130 , and glued onto the layer  180  with the opposite side from the first. A second metal electrode  160 , in contact with the top surface of the substrate  130 , forms the diode cathode. The electrode  160  includes an area set aside for conventional bonding to connect the cathode to a respective terminal.  
         [0041]    Advantageously, in one embodiment, the electrode  170  comprises a triad of chromium, nickel and gold layers.  
         [0042]    A conventional chip-on-chip assembly procedure is followed in this embodiment of the invention, whereby the conductive layer  180  includes a layer of a conductive adhesive material for attaching the IGBT emitter electrode to the anode of the diode NP. The cathode of the diode is bonded conventionally to the collector through its respective terminal CL, as shown schematically in FIG. 5 b.    
         [0043]    Advantageously, the diode  120  is of a comparable size with that area of the IGBT  1  which is reserved for accommodating the diode in conformity with known rules of the chip-on-chip technique.  
         [0044]    A preferred embodiment of the IGBT  1  and diode  120  has been disclosed for simplicity; alternatively, these devices could be realized using standard techniques.  
         [0045]    According to an embodiment of the invention, there is provided on the IGBT emitter electrode an area for bonding to the gate electrode lead, an area for bonding to the emitter electrode lead, and an area for accommodating the diode in place. The relative positions of the above three areas will vary with the package type. By way of example only, the contact areas may be situated as shown in the drawings. All three areas may be obtained from standard metal and passivating layers provided by the IGBT manufacturing process. The electrode-forming conductive layer may be aluminum, and the passivating layer nitride. The area for the diode may contain fingers of the gate electrode, on condition that such fingers are covered with the passivating layer in a suitable way to keep them electrically isolated from the conductive adhesive material used for diode emplacement.  
         [0046]    Advantageously, in one embodiment, a second metal layer (wettable metal)  190 , e.g. comprising triple layers of titanium, nickel and gold, may be deposited onto the surface of the diode accommodating area to improve the quality of the emitter electrode-to-diode contact. Where this is the choice, the IGBT manufacturing process should be altered to include the following additional steps:  
         [0047]    forming the second metal layer  190 ;  
         [0048]    masking to define the area for diode accommodation; and  
         [0049]    selectively etching away the metal layer  190  to uncover the diode accommodating area.  
         [0050]    To summarize, a method of manufacturing the structure according to an embodiment of this invention comprises the following steps:  
         [0051]    positioning the IGBT device onto the package frame PF, and bonding it thereto by any standard techniques for electronic devices;  
         [0052]    coating the IGBT area which is to accommodate the diode with a layer of a conductive adhesive material, in conformity with the chip-on-chip technique; (advantageously, the adhesive material will be a variety which can be normally used for bonding the IGBT to the package frame)  
         [0053]    positioning the diode on the die-attach area of the IGBT, and applying the required curing procedure;  
         [0054]    completing the structure by bonding the gate, cathode, and emitter leads to their respective gate GL, collector CL, and emitter EL terminals on the package.  
         [0055]    Advantageously, the package should provide, as by a special lead, for shorting the diode cathode to the IGBT collector.  
         [0056]    To summarize, the embodiments of the invention typically have the following advantages:  
         [0057]    the IGBT is allowed to fill the package area completely; and  
         [0058]    either devices, being independent of each other, can be realized by their most appropriate techniques.  
         [0059]    In conclusion, an embodiment of the invention provides a hybrid diode integration whereby all the package area is utilized, for improved performance of both the IGBT and the diode.  
         [0060]    A method according to an embodiment of this invention can be advantageously applied to establish connection of a power device to a unidirectional device in a stacked arrangement. In a preferred embodiment of the invention, the unidirectional device is connected between the collector electrode and the emitter electrode of the power device. Alternatively, the unidirectional device could be connected to other terminals of the power device or connected to different terminals of the protective package.  
         [0061]    While particular embodiments of the present invention have been shown and described, modifications may be made. It is therefor intended in the appended claims to cover all such changes and modifications which fall within the true spirit and scope of the invention.