Abstract:
The disclosure relates to a link bandwidth management which is initiated either by software or hardware, and related negotiation failure or unreliable management, and also related hardware autonomous negotiation priority. By introducing flexible bandwidth management, this invention can resolve the problems of prior art. Different link bandwidth can be set for different applications, which can help to achieve both good performance and power savings.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a method for link bandwidth management, and more particularly to a method for link bandwidth management applied to a PCI express bus. 
       BACKGROUND OF THE INVENTION 
       [0002]    As shown in  FIG. 1 , it is a computer system architecture. In a modern computer system, CPU  20 , memory  22 , and graphic chip  24  work very closely and they need to have faster data access to each other. As a result, requests and responses issued from three devices are all controlled and managed by the northbridge chip  26 . The northbridge chip  26  is tied to the southbridge chip  28 , which routes traffic from the different I/O devices on the system, such as hard disk drive 30 , optical disk drive  32 , and ethernet port  34 . The traffic from these devices is routed through the southbridge chip  28  to the northbridge chip  26  and then on to the CPU and/or memory  22 . 
         [0003]    In 2002, a new PCI express bus specification was finished and then a PCI express bus  40  communicated between the graphic chip  24  and the northbridge chip  26  was implemented in the computer system. Generally speaking, a connection between a graphic chip  24  and the northbridge chip  26  on a PCI express bus  40  is called a link. Each link is composed of one or more lanes, and each lane is capable of transmitting one byte at a time 
         [0004]    Please again refer to  FIG. 3 . If unreliable speed change  120  is happening, PCI express bus with Link A/B  100  will be negotiated to target Link A/C  150  if the speed C passing the following failure speed management  110  and unreliable speed management  112 . Similarly, if unreliable width change  124  is happening, PCI express bus with Link A/B  100  will be negotiated to target Link D/B  160  if the width D passing the following failure width management  126  and unreliable width management  128 . 
         [0005]    Please again refer to  FIG. 3 . Base on failure speed management  110  and failure width management  126 , if initial link width/speed tries to negotiate to the target width/speed but fails, PCI express bus will remain to the initial width/speed. The failed width/speed will be recorded, and either software or hardware speed transition to that bandwidth is unattainable. Similarly, Base on unreliable speed management  112  and unreliable width management  128 , if the target link width/speed is detected as unreliable link width/speed, PCI express bus will remain to the initial width/speed. The unreliable width/speed will be recorded, and either software or hardware speed transition to that bandwidth is unattainable. 
         [0006]    By introducing the method of link bandwidth management, this invention can resolve the problems of prior art. Different link bandwidth can be set for different applications, which can help to achieve both good performance and power savings. Another problem resolved is that, in bandwidth change, there is no need to enter link down state, or device re-initialization/configuration state, therefore, the transition time between different bandwidths is much shortened. in both directions. That means each lane is itself composed of one pair of signals: send and receive. In order to transmit PCI express packets, which are composed of multiple bytes, one device using a one-lane link on the transmitting end must break down each packet into a series of bytes, and then transmit the bytes in rapid succession. The device on the receiving end has to collect all of the bytes and then reassemble them into the original packet. 
         [0007]    One of PCI express bus  40  features is the ability to aggregate multiple individual lanes together to form a signal link. In other words, two lanes could be coupled together to form a single link capable of transmitting two bytes at a time, this doubling the link bandwidth. Also, four lanes, or eight lanes could be combined to form a single link. A link composes of a single lane is called an x1 link; a link composed of two lanes is called x2 link; a link composed of four lanes is called x4 link, etc. PCI express bus  40  supports x1, x2, x4, x8, x12, x16, and x32 link widths. Furthermore, PCI express bus supports two different link speeds. One is called PCI express generation  1  (Gen  1 ) having clock data rate to 2.5 GHz, and the other is called PCI express generation  2  (Gen  2 ) having clock data rate to 5 Ghz. 
         [0008]    As depicted in  FIG. 2 , it is a conventional method for devices connecting on a PCI express bus to negotiate a link width/speed. Conventionally, link width/speed is reset when link is down or initial power up. The first state is called link down state or initial power up state  50 , which is set at the time of powering up the computer system. Then, the state changes to set maximum link width/speed state  52 , which is activated by two devices connected on the PCI express bus. In the state  52 , two devices individually set the maximum link widths/speeds they support for transmitting and receiving on the bus. Then, the state change to negotiate maximum allowed link width/speed state  54 . In state  54 , two devices negotiate to an allowed maximum link width/speed according to the physical layer electrical characteristic, and channel features of both devices. For example, in state  52 , the respective maximum link bandwidths of graphic chip and northbridge chip are x32/Gen 1  and x16/Gen 2 . After negotiation process of state  54 , the maximum allowed link width/speed of PCI express bus is x16/Gen 1 . After the maximum allowed link width/speed is determined, there is generally also device initiation/configuration state  56  for devices to be useful in real application. After state  56 , it goes to link normal operation state  58 , which means the maximum allowed link bandwidth is the final operation bandwidth for the two devices to communicate normally with each other. 
         [0009]    According to  FIG. 2 , to change link width/speed, it should disable the link or power down for the state goes from link normal operation state  58 , through link down/initial power up state  50 , then set maximum link width/speed state  52 , then negotiated to maximum allowed width/speed state  54 , then device initiation/configuration state  56 . Since it is related with link down/initial power up state  50 , and device initial/configuration state  56 , to change link width/speed process is complicated and time consuming. In real practice, the maximum allowed speed/width is always to set for all applications. In another word, link bandwidth never changes, and there is no bandwidth management needed in the prior art. Furthermore, according to the conventional method, the final operation bandwidth is always the maximum allowed link width/speed if the link bandwidth is tried to be changed. However, for bandwidth eager applications, e.g. 3D game software, the determined bandwidth may be too little; and for applications with few packets traffic, e.g. document software, the determined bandwidth is often too luxury for them, which in most cases mean power consumptions waste. 
       SUMMARY OF THE INVENTION 
       [0010]    The present invention provides a method for link bandwidth management targeted to achieve both good performance and high power savings for any specific application and to have a fast link bandwidth change time for improving the above-mentioned defects of conventional technology. 
         [0011]    In accordance with an aspect of the present invention, the method for link bandwidth management in a computer system, which is used on a bus having a link comprising selectable widths and selectable speeds for accessing data by two devices on both ends of the bus, includes when the bus is operated at a first bandwidth having a first width and a first speed and a change condition is activated, changing the first bandwidth to a target bandwidth having a second width and the first speed or the first width and a second speed without disabling said link or powering down the computer system. 
         [0012]    The above contents of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  is a computer system architecture; 
           [0014]      FIG. 2  is a diagram depicts a conventional link width/speed negotiation sequence; 
           [0015]      FIG. 3  is a block diagram schematically illustrating a link bandwidth management sequence of this present invention; 
           [0016]      FIG. 4  is a block diagram schematically illustrating a logic idle calculation bases hardware autonomous bandwidth mechanism of this present invention; 
           [0017]      FIG. 5  is a block diagram schematically illustrating a hardware autonomous bandwidth negotiation priority with an option of this present invention; and 
           [0018]      FIG. 6  is a block diagram schematically illustrating a link unreliable management process of this present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0019]    As depicted in  FIG. 3 , it is a link bandwidth management for the PCI express bus according to the present invention. In an embodiment, the PCI express bus will change link width/speed when a change condition is activated. The change condition according to the invention can be a hardware autonomous change, a software-directed change, or an unreliable change; and each change can also be divided to link width change and link speed change. 
         [0020]    As depicted in  FIG. 3 , software-directed change can be divided to software-directed speed Change  104  and software-directed width change  122 . When a computer system executing a software application, the software application will store a required link width/speed for PCI express bus in a register of northbridge chip, and then link width/speed will be changed if the link width/speed stored in register is different from the present link width/speed. For example, if the initial link width/speed of PCI express bus is link A/B  100 , and the link width/speed stored in a register by a software application is link A/C, the software-directed speed change  104  will be executed. Link speed B will be changed to link speed C after negotiation between two ends (Northbride and Graphic Chip) if the target link speed C passing the following failure speed management  110  and unreliable speed management  112 . The link width/speed of PCI express bus will be finally changed to link A/C  150 , and the link is supposed to attain target link speed C whenever possible. 
         [0021]    Similarly, if the initial link width/speed of PCI express bus is link A/B  100 , and the link width/speed stored in a register by a software application is link D/B, the software-directed width change will be executed. Link width A will be changed to link width D after negotiation between two ends (Northbride and Graphic Chip) if the target link width D passing the following failure width management  126  and unreliable width management  128 . The link width/speed of PCI express bus will be finally changed to link D/B  160 , and the link is supposed to attain target link width D whenever possible. 
         [0022]      FIG. 4  depicts a state diagram schematically illustrating hardware autonomous change of the present invention. In Operation state  130 , northbridge chip will monitor logic idle symbol for counting the number of continuous logic idle symbol in transmitter and receiver of northbridge chip. If continuous logic idle symbol number is greater than a first programmable limit, northbridge chip will enter a calculate state  132 . 
         [0023]    In calculate state  132 , northbridge chip will periodically monitor its logic idle symbol at the most busy lane in a multi-lane link (lane  0  or starting lane) and calculate a percentage of non-logic idle (PNI) to indicate link bandwidth behaviors. PNI is OK means packet traffic is acceptable in current link bandwidth, and link bandwidth has no need to change. PNI too high means traffic is busy, and link bandwidth needs upgrade. PNI too low means traffic is little, and link bandwidth needs downgrade. For example, when PNI is greater than a second programmable value of 87.5%, link bandwidth needs to be upgraded. When PNI is lower than a third programmable value of 12.5%, link bandwidth needs to be downgraded. When PNI is lower than 87.5% and greater than 12.5%, means PNI is OK and there is no needed to change link bandwidth. Therefore, the state will change from calculation state  132  to operation state  130 . 
         [0024]    When PNI is too high or too low based on above method, either speed or width change needs to be executed. Northbridge chip may enter speed change state  134  for negotiating target speed, and then enter speed change sequence state  136  for setting target speed; or northbridge chip may enter width change state  140  for negotiating target width, and then enter width change sequence state  142  for setting target width. After link speed or link width is changed, northbridge chip will move back to operation state  130  with a new link bandwidth. 
         [0025]    In addition, entering whether speed change state  134  or width change state  140  is carried on can base on hardware autonomous bandwidth negotiation priority as depicted in  FIG. 5 . When an option is set to 1, speed negotiation priority is higher; when the option is set to 0, width negotiation priority is higher. For example, if option is set to 1, link Gen  1  /x1 will be upgraded to link Gen  2 /x1 first, and then width will be upgraded from x1 to x2, x4 . . . x32, if necessary; link Gen  2 /x32 will be downgraded to link Gen  2 /x32 . . . x1 first, and then speed will be downgraded to Gen  1  , if necessary. Here the option can be seen as power consumption option in a link, where a wider link consumes more power than a higher speed link with a half width. 
         [0026]    Similarly. if option is set to 0, width of link Gen  1  /x1 will be upgraded to link Gen  1  /x2 . . . x32 first, and then speed will be upgraded Gen  2 /x2 . . . x32, if necessary. If option is set to 1, speed of link Gen  2 /x2 . . . x32 will be downgraded to link Gen  1  /x2 . . . x32 first, and then width will be downgraded to Gen  1  /x1, if necessary. 
         [0027]    Please refer again to  FIG. 3 . hardware autonomous change  106  is divided to hardware speed change  108  and hardware width change  120 . After hardware speed change  108  is completed, Link A/B  100  will be changed to target Link A/C  150  if speed C passing the following failure speed management  110  and unreliable speed Management  112 . Similarly, after hardware width change  120  is completed, Link A/B  100  will be changed to target Link D/B  160  if speed C passing the following failure width management  126  and unreliable speed management  128 . 
         [0028]      FIG. 6  depicts a state diagram illustrating unreliable change of the present invention. When PCI express bus is operated with specified link width/speed  200 , if same TLP (Transition Layer Packet) has been resent several times exceeding a limit (a fourth programmable value) by transmitter and still fail to be ACKed (Acknowledged) by receiver, the transmitter will be defined as transmitter unreliable  202 ; If receiver gets the same sequence number TLP and CRC (Cycle Redundancy Check) error case several times exceeding a limit (a fifth programmable value), the receiver will be defined as receiver unreliable  204 . Either transmitter unreliable  202  or receiver unreliable  204  can be seen as unreliable link bandwidth. 
         [0029]    Since bandwidth is related with both link speed and link width, when a specific bandwidth is unreliable, it cannot say if the link speed is too high, or link width is too large. Here another option (speed unreliable option) is added. When the speed unreliable option is 0, transmitter unreliable  202  or receiver unreliable  204  will enter width unreliable state  208 , and then enter width transition process state  210  for changing link width and PCI express bus will be operated with new link width. When the speed unreliable option is 1, transmitter unreliable  202  or receiver unreliable  204  will enter speed unreliable state  206 , and then enter speed transition process state  212  for changing link speed, and PCI express bus will be operated with new link speed. 
         [0030]    The present invention is intended to cover various modifications and similar arrangements included to within the spirit and scope of the appended claims, which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.