Abstract:
A method of fabricating a semiconductor device which includes introducing, after a step of patterning a gate electrode, nitrogen atoms into an oxide film covering a device region on a semiconductor substrate, by exposing said oxide film to an atmosphere containing-nitrogen, such that said nitrogen atoms do not reach a region underneath said gate electrode, covering, after said step of introducing nitrogen atoms, said oxide film including said gate electrode by a CVD oxide film continuously without taking out said semiconductor substrate out of a processing chamber and forming a sidewall oxide film on a sidewall surface of said gate electrode by etching back said CVD oxide film

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The present invention generally relates to fabrication of semiconductor devices and more particularly to fabrication and construction of a high speed field-effect transistor.  
           [0002]    High-speed logic integrated circuits generally use high-speed CMOS circuits. CMOS circuits consume little electric power and are particularly suited for this purpose. In order to increase the operational speed of high-speed CMOS circuits further, a very fast field-effect transistor is needed.  
           [0003]    Conventionally, the operational speed of a field-effect transistor has been increased mainly by reducing the gate length, which in turn is achieved by a device miniaturization. For example, MOS transistors having a gate length as small as 0.35 μm, are used these days for such high performance applications.  
           [0004]    On the other hand, further reduction of gate length is generally difficult in MOS transistors, as carriers tend to experience excessive acceleration in a channel region immediately under a gate electrode of the MOS transistor when the gate length of the MOS transistor is thus reduced. The carriers thus accelerated tend to penetrate into a gate oxide film and form fixed electric charges therein, while such fixed electric charges tend to modify the threshold characteristics of the MOS transistor.  
           [0005]    In more detail, the carriers thus penetrated into the gate oxide film enter the SiO 2  structure that form the gate oxide film, wherein the carriers thus penetrated into the SiO 2  structure are held stably when the carriers are captured by the dangling bonds of the SiO 2  structure.  
           [0006]    Thus, it has been practiced conventionally in the art of MOS transistors to terminate any dangling bonds existing in the gate oxide film by introducing N atoms thereinto, so that the number of the sites which may capture the carriers is reduced as much as possible.  
           [0007]    FIGS.  1 A- 1 D show a conventional fabrication process of a MOS transistor.  
           [0008]    Referring to FIG. 1A, a field oxide film  2  is formed on a Si substrate  1  doped to the p-type or n-type, such that the field oxide film  2  defines a device region  1 A on the surface of the substrate  1 . The field oxide film  2  is typically formed by a wet etching process with a thickness of 300-400 nm. Further, a thermal oxide film  3  is formed on the Si substrate  1  so as to cover the device region  1 A with a thickness of typically about 6 nm. The thermal oxide film  3  acts as a gate oxide film of the MOS transistor to be formed.  
           [0009]    The structure of FIG. 1A is then annealed in an N 2 O atmosphere at a temperature of typically 800° C., such that N atoms in the atmosphere are incorporated into the gate oxide film  3 .  
           [0010]    Next, in the step of FIG. 1B, a polysilicon film  4  is deposited on the structure of FIG. 1A by a CVD process conducted at a temperature of 800-900° C., typically with a thickness of about 150 nm. Further, the polysilicon film  4  is patterned in the step of FIG. 1C by an anisotropic etching process such as an RIE (reactive ion etching) process, and a gate electrode  4 A is formed as a result.  
           [0011]    After the gate electrode  4 A is thus formed, an ion implantation process of a p-type dopant such as B or an n-type dopant such as As or P is introduced into the substrate  1  while using the gate electrode  4 A as a mask. Thereby, diffusion regions  1 B and  1 C are formed in the substrate  1  respectively in correspondence to a source region and a drain region of the MOS transistor to be formed. Further, a CVD-SiO 2  film  5  is deposited on the structure thus obtained by a CVD process conducted at the temperature of 800-900° C., typically with a thickness of about 100 nm.  
           [0012]    Next, in the step of FIG. 1D, the CVD-SiO 2  film  5  is subjected to an anisotropic etching process that acts substantially vertically to the principal surface of the substrate  1 , and side wall oxides  5 A and  5 B are formed at respective lateral sides of the gate electrode  4 A. Further, by carrying out the ion implantation process of the p-type dopant or the n-type dopant once more into the substrate  1  in the state that the gate electrode  4 A carries the side wall oxides  5 A and  5 B, further diffusion regions  1 B′ and  1 C′ having a higher dopant level are formed inside the diffusion regions  1 B and  1 C. In other words, the MOS transistor thus formed has a so-called LDD (lightly doped drain) structure.  
           [0013]    It should be noted that, in the MOS transistor of the foregoing structure, the gate oxide film  3  acts as an etching stopper when patterning the gate electrode  4 A. Thereby, the part of the gate oxide film  3  not protected by the gate electrode  4 A may experience an increased degree of damage during the etching process. For example, the Si—O bonds in the SiO 2  structure of the gate oxide film  3  may be broken.  
           [0014]    When such breaking of the Si-O bond occurs, dangling bonds are formed inevitably in the structure of the gate oxide film  3 , while it is known that the dangling bonds tend to capture H or OH ions. In the case of the high speed MOS transistor of FIG. 1D that has a short channel length, there is a substantial risk that the dangling bonds in the gate oxide film  3  capture the hot carriers that are accelerated at the edge of drain region  1 C and penetrated into the gate oxide film  3  as indicated in FIG. 2, wherein FIG. 2 shows the drain region  1 C in an enlarged scale.  
           [0015]    In order to overcome the problem, it has been proposed to introduce N atoms into the gate oxide film  3  in the process of FIG. 1A, such that the N atoms thus introduced terminate the dangling bonds in the gate oxide film  3 . As a result of such a process, the trapping of the hot electrons by the dangling bonds is reduced substantially.  
           [0016]    On the other hand, the conventional process of FIGS.  1 A- 1 D raises a problem in that, because the N atoms are introduced at a relatively early phase of the process, the N atoms thus incorporated easily escape in the following processes, particularly those including thermal annealing processes. In other words, it has been necessary in the conventional process of FIGS.  1 A- 1 D to incorporate a very large amount of N atoms into the gate oxide film  3  in order that such a doping by the N atoms is effective for suppressing the trapping of the hot carriers by the dangling bonds.  
           [0017]    When the N atoms are introduced in the step of FIG. 1A, it should be noted that the N atoms are introduced not only into the part of the gate oxide film  3  corresponding to the edge part of the drain region as shown in FIG. 2 but also into the part immediately underneath the gate electrode  4 A. Thereby, the MOS transistor thus obtained tends to show a threshold characteristic substantially different from the desired or designed threshold characteristic.  
           [0018]    [0018]FIGS. 3A and 3B show a flat-band voltage V FB  and a threshold voltage V TH  of the MOS transistor for the case in which the gate oxide film, formed as a result of a thermal oxidation process in a dry O 2  environment, is exposed to various N-containing atmospheres at a temperature of about 800° C.  
           [0019]    Referring to FIGS. 3A and 3B, it will be noted that both the V FB  and the V TH  are modified significantly as a result of the thermal annealing process conducted in the NO or N 2 O atmospheres for various durations. As already noted, the concentration of the N atoms in the gate oxide film  3  is changed substantially by the heating processes included in the steps of FIGS.  1 A- 1 D. Thus, it has been difficult in the conventional MOS transistor, fabricated according to the process of FIGS.  1 A- 1 D, to control the characteristics thereof exactly, and there has been a problem in that the transistor shows a large scattering of the characteristics. This problem becomes particularly acute in the MOS transistors in which a very large amount of N atoms are introduced into the gate oxide film for effective termination of the dangling bonds therein.  
         SUMMARY OF THE INVENTION  
         [0020]    Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated.  
           [0021]    Another and more specific object of the present invention is to provide a semiconductor device and a fabrication process thereof, wherein the problem of trapping of the hot carriers in the gate oxide film is successfully eliminated while simultaneously realizing a stable and reproducible device characteristic.  
           [0022]    Another object of the present invention is to provide a semiconductor device, comprising:  
           [0023]    a substrate;  
           [0024]    a gate oxide film formed on said substrate;  
           [0025]    a gate electrode provided on said gate oxide film;  
           [0026]    first and second diffusion regions formed in  
           [0027]    said substrate at both lateral sides of said gate electrode;  
           [0028]    said gate electrode including a first region located immediately underneath said gate electrode and a second region adjacent to said first region, said first and second regions containing N atoms with respective concentrations such that said second region contains N with a higher concentration as compared with said first region.  
           [0029]    According to the present invention, the variation of the threshold or other characteristic of the semiconductor device is successfully suppressed while simultaneously suppressing the problem of the trapping of the hot carriers in the gate oxide film in the vicinity of the drain edge.  
           [0030]    Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:  
           [0031]    forming a gate oxide film on a substrate;  
           [0032]    forming a gate electrode pattern on said gate oxide film; and  
           [0033]    introducing N atoms into said gate oxide film while using said gate electrode pattern as a mask.  
           [0034]    According to the present invention, the N atoms are introduced into the gate oxide film selectively in correspondence to the edge part of the drain region where the acceleration of the carriers, and hence the formation of the hot carriers, is maximum, while the gate oxide film immediately underneath the gate electrode pattern is maintained substantially free form the N atoms. Thereby, the problem of trapping of the hot carriers in the gate oxide film is successfully avoided in the part where the creation of the hot carriers is maximum. As the gate oxide film is substantially free from the N atoms in the part immediately underneath the gate electrode pattern, the designed operational characteristic is obtained for the semiconductor device with reliability and reproducibility.  
           [0035]    Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0036]    FIGS.  1 A- 1 D are diagrams showing a conventional fabrication process of a semiconductor device;  
         [0037]    [0037]FIG. 2 is a diagram explaining the problem pertinent to the conventional semiconductor device;  
         [0038]    [0038]FIGS. 3A and 3B are further diagrams explaining the problem of the conventional semiconductor device;  
         [0039]    [0039]FIG. 4 is a diagram showing the principle of the present invention;  
         [0040]    FIGS.  5 A- 5 G are diagrams showing a fabrication process of a semiconductor device according to a first embodiment of the present invention;  
         [0041]    [0041]FIG. 6 is a diagram showing a distribution profile of N atoms in a gate oxide film of the semiconductor device of the first embodiment;  
         [0042]    FIGS.  7 A- 7 G are diagrams showing a fabrication process of a semiconductor device according to a second embodiment of the present invention; and  
         [0043]    [0043]FIG. 8 is a diagram showing the effect of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0044]    [Principle] 
         [0045]    [0045]FIG. 4 shows the principle of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.  
         [0046]    Referring to FIG. 4, the present invention introduces N atoms into a part of the gate oxide film  3  indicated by a hatched region selectively with respect to the adjacent region located immediately underneath the gate electrode pattern  4 A. Thereby, it should be noted that the N atoms are contained mostly in the hatched region and the concentration of the N atoms in the adjacent region is held minimum. Thus, the problem of modification of the threshold characteristics of the semiconductor device by the N atoms thus doped into the gate oxide film  3  is effectively and successfully minimized.  
         [0047]    In the construction of FIG. 4, it should be noted that the N atoms are introduced selectively and with a high concentration level into the region that tends to experience most severe damages during the patterning process of the gate electrode pattern  4 A. Further, the region of the gate oxide film  3  where the N atoms are introduced selectively corresponds to the part of the channel region where the creation of the hot carriers is maximum. Thus, any dangling bonds that are created as a result of the damage are immediately terminated by the N atoms and the problem of trapping of the hot carriers by the dangling bonds is successfully eliminated.  
         [0048]    As the foregoing doping of the N atoms into the gate oxide film  3  is achieved after the deposition and patterning of the gate electrode pattern  4 A, the problem of escaping of the N atoms by the heat caused during the deposition of the gate electrode pattern  4 A is successfully avoided.  
         [0049]    Further, when the doping of the N atoms is conducted by exposing the gate oxide film  3  to the NO atmosphere, the subsequent process of depositing the side wall oxides  5 A and  5 B may be conducted immediately thereafter, in the same deposition apparatus, continuously and without exposing the substrate to the environment. It should be noted that the annealing process for introducing the N atoms is conducted at the temperature of about 800° C., while this temperature is the temperature used for depositing the side wall oxides  5 A and  5 B by way of a CVD process.  
         [0050]    [First Embodiment] 
         [0051]    FIGS.  5 A- 5 G show the fabrication process of a MOS transistor according to a first embodiment of the present invention.  
         [0052]    Referring to FIG. 5A, a Si substrate  11  corresponding to the Si substrate  1  of FIG. 1A is formed with a well  11   a  of the p-type or n-type, and a field oxide film  12  is formed on the substrate  11  by a wet oxidation process with a thickness of typically 300-400 nm, such that the field oxide film  12  defines a device region  11 A on the surface of the substrate  11 . Further, a thermal oxide film  13  is formed on the substrate  11  so as to cover the device region  11 A with a thickness of typically 6 nm.  
         [0053]    Further, in the step of FIG. 5B, a polysilicon film  14  corresponding to the polysilicon film  4  of FIG. 1B is deposited on the structure of FIG. 5A typically with a thickness of about 15 nm by a CVD process conducted at a temperature of 800-900° C. The polysilicon film  14  thus formed is then subjected to an anisotropic etching process such as an RIE process in the step of FIG. 5C and a gate electrode  14 A is formed.  
         [0054]    In the step of FIG. 5C, a p-type dopant such as B or an n-type dopant such as As or P is further introduced into the substrate  11  by an ion implantation process while using the gate electrode  14 A as a mask, and diffusion regions  11 B and  11 C are formed in the substrate  11 .  
         [0055]    Further, the substrate  11  thus processed is introduced into a CVD apparatus and exposed to an atmosphere containing No for a duration of typically 5-20 minutes. Because of the toxic nature of NO, it is preferable to use a diluted gas of NO for the foregoing exposure process in which NO is diluted in an Ar carrier gas with a volumetric concentration of about 30%. Further, it is desirable, for the sake of safety, to carry out the exposure under a reduced pressure environment of about 40 Pa, for example.  
         [0056]    As a result of the thermal annealing applied during the exposure process, the impurity elements introduced previously by the ion implantation process cause a diffusion into the substrate  11  and the diffusion regions  11 B and  11 C noted previously are formed as a result of such a diffusion of the impurity element. Thus, the annealing process associated with an ion implantation process is achieved simultaneously to the thermal annealing process for introducing the N atoms in the present embodiment.  
         [0057]    Next, in the step of FIG. 5D, a CVD-SiO 2  film  15  is deposited on the structure of FIG. 5C by a CVD process conducted in the same CVD apparatus at a temperature of typically about 800° C., with a thickness of about 100 nm. It should be noted that the CVD process of FIG. 5D is conducted continuously to the exposure process of FIG. 5C.  
         [0058]    Next, in the step of FIG. 5E, the CVD-SiO 2  film  15  is subjected to an anisotropic etching process such as an RIE process acting substantially perpendicularly to the principal surface of the substrate  11 , and side wall oxides  15 A and  15 B are formed at both lateral sides of the gate electrode  14 A, similarly to the side wall oxides  5 A and  5 B of FIG. 1D. Further, by conducting an ion implantation process-of the foregoing p-type or n-type dopant into the substrate  11  in the state that the gate electrode  14 A carry the side wall oxides  15 A and  15 B, an LDD structure including diffusion regions  11 B′ and  11 C′ having a higher impurity concentration level inside the diffusion regions  11 B and  11 C, are obtained.  
         [0059]    Next, in the step of FIG. 5F, an interlayer insulation film  16  of SiO 2  is deposited on the structure of FIG. 5E with an appropriate thickness, and ohmic electrodes  17 A and  17 B are provided on the interlayer insulation film  16  in ohmic contact with the diffusion regions  11 C and  11 B respectively via contact holes formed in the interlayer insulation film  16 .  
         [0060]    In the present embodiment, the process of FIG. 5C for introducing the N atoms into the gate oxide film  13  is carried out while using the gate electrode  14 A as a mask. Thus, the incorporation of the N atoms does not occur in the part of the gate oxide film  13  located immediately underneath the gate electrode  14 A and covering the channel region. Thus, no substantial change occurs in the threshold characteristic or flatband characteristic of the MOS transistor even when the N atoms are introduced into the gate oxide film  13 .  
         [0061]    As the N atoms are introduced with a high concentration level selectively into the part of the gate oxide film  13  corresponding to the drain edge where the creation of the hot-carriers is most prominent, the dangling bonds in the SiO 2  structure forming the gate oxide film  13  are effectively terminated, and the sites for trapping hot-carriers are annihilated. Thus, the problem of trapping of the electrons or holes by the gate oxide film  13  is successfully avoided.  
         [0062]    In the step of FIG. 5C, it should be noted that the exposure process may be conducted in an atmosphere containing N 2 O in place of NO. In this case, it is preferable to use the annealing temperature of about 900° C., rather than 800° C. Generally, the amount of the N atoms incorporated into the gate oxide film  13  is reduced when the exposure is carried out in the N 2 O atmosphere rather than in the No atmosphere. When N 2 O is used in the step of FIG. 5C, it is necessary to lower the temperature of the CVD apparatus to about 800° C. when carrying out the CVD process of FIG. 5D. Such thermal annealing processes at different temperatures can be conducted efficiently by using a cluster-type processing apparatus.  
         [0063]    [0063]FIG. 6 shows the distribution profile of N atoms in the depth direction of the gate oxide film  13  as measured by a SIMS (secondary ion mass spectroscopy) analysis.  
         [0064]    Referring to FIG. 6, it should be noted that the concentration level of the N atoms is much higher when the thermal annealing process is conducted in the NO atmosphere rather than the case in which the thermal annealing process is conducted in the N 2 O atmosphere. Further, FIG. 6 indicates that the N atoms thus introduced are primarily concentrated in the vicinity of the interface between the gate oxide film  13  and the substrate  11 . In other words, the N atoms introduced in the step of FIG. 5C into the gate oxide film  13  tend to show a concentration to the interface to the substrate  11 . It will be noted that the peak concentration level of the N atoms in the gate oxide film  13  is in the range of about 0.5% to about 2% or more.  
         [0065]    In the present embodiment, the thermal annealing process of FIG. 5C in the NO or N 2 O atmosphere is carried out after the ion implantation process for forming the diffusion regions  11 B and  11 C. This, however, is not a mandatory condition and it is also possible to carry out the thermal annealing process before the ion implantation process. In this case, however, it is necessary to carry out a separate thermal annealing process for activating the introduced impurity elements in the diffusion regions  11 B and  11 C.  
         [0066]    [Second Embodiment] 
         [0067]    FIGS.  7 A- 7 G show the fabrication process of a MOS transistor according to a second embodiment of the present invention.  
         [0068]    Referring to FIG. 7A, a Si substrate  21  corresponding to the Si substrate  1  of FIG. 1A is formed with a well  21   a  of the p-type or n-type, and a field oxide. film  22  is formed on the substrate  21  by a wet oxidation process with a thickness of typically 300-400 nm, such that the field oxide film  22  defines a device region  21 A on the surface of the substrate  21 . Further, a thermal oxide film  23  is formed on the substrate  21  so as to cover the device region  21 A with a thickness of typically 6 nm.  
         [0069]    Further, in the step of FIG. 7B, a polysilicon film  24  corresponding to the polysilicon film  4  of FIG. 1B is deposited on the structure of FIG. 7A typically with a thickness of about 15 nm by a CVD process conducted at a temperature of 800-900° C. The polysilicon film  24  thus formed is then subjected to an anisotropic etching process such as an RIE process in the step of FIG. 7C and a gate electrode  24 A is formed.  
         [0070]    In the step of FIG. 7C, a p-type dopant such as B or an n-type dopant such as As or P is further introduced into the substrate  21  by an ion implantation process while using the gate electrode  24 A as a mask, and diffusion regions  21 B and  21 C are formed in the substrate  21 .  
         [0071]    In the step of FIG. 7C, the substrate  21  thus processed is subjected to an ion implantation process in which N +  ions are introduced into the gate oxide film  23  while using the gate electrode  24 A as a mask. In the ion implantation process of N +  atoms, the acceleration voltage is set such that the N +  atoms do not reach the substrate  21 . For example, the acceleration voltage is set to 100 keV or less, and the ion implantation may be made with a dose of 1-3×10 14  cm− 2  such that substantially the entire dangling bonds in the film  23  are terminated.  
         [0072]    Next, in the step of FIG. 7D, a CVD-SiO 2  film  25  is deposited on the structure of FIG. 7C by a CVD process conducted in the same CVD apparatus at a temperature of typically about 800° C., with a thickness of about 100 nm.  
         [0073]    Next, in the step of FIG. 7E, the CVD-SiO 2  film  25  is subjected to an anisotropic etching process such as an RIE process acting substantially perpendicularly to the principal surface of the substrate  21 , and side wall oxides  25 A and  25 B are formed at both lateral sides of the gate electrode  24 A, similarly to the side wall oxides  5 A and  5 B of FIG. 1D. Further, by conducting an ion implantation process of the foregoing p-type-or n-type dopant into the substrate  21  in the state that the gate electrode  24 A carry the side wall oxides  25 A and  25 B, an LDD structure including diffusion regions  21 B′ and  21 C′ having a higher impurity concentration level inside the diffusion regions  21 B and  21 C, are obtained.  
         [0074]    Next, in the step of FIG. 7F, an interlayer insulation film  26  of SiO 2  is deposited on the structure of FIG. 7E with an appropriate thickness, and ohmic electrodes  27 A and  27 B are provided on the interlayer insulation film  26  in ohmic contact with the diffusion regions  21 C and  21 B respectively via contact holes formed in the interlayer insulation film  26 .  
         [0075]    In the present embodiment, too, the process of FIG. 7C for introducing the N atoms into the gate oxide film  23  is carried out while using the gate electrode  24 A as a mask. Thus, the incorporation of the N atoms does not occur in the part of the gate oxide film  23  located immediately underneath the gate electrode  24 A and hence covering the channel region. Thus, no substantial change or modification occurs in the threshold characteristic or flat-band characteristic of the MOS transistor even when the N atoms are introduced into the gate oxide film  23 .  
         [0076]    As the N atoms are introduced with a high concentration level selectively into the part of the gate oxide film  23  corresponding to the drain edge where the creation of the hot-carriers is most prominent, the dangling bonds in the SiO 2  structure forming the gate oxide film  23  are effectively terminated, and the sites for trapping hot-carriers are annihilated. Thus, the problem of trapping of the electrons or holes by the gate oxide film  23  is successfully avoided.  
         [0077]    [0077]FIG. 8 shows, by a thick continuous line designated by “X,” the degradation or variation  Δ Id of a drain current Id with a stress time, for a 64M bit DRAM that uses the MOS transistor of FIG. 5G. Further, FIG. 8 shows also a similar change of the drain current, by open circles and designated as “REF,” for the case in which the MOS transistor is formed without incorporation of N atoms into the gate oxide film. Further, FIG. 8 shows by solid circles the change of the drain current Id for the case in which the gate oxide film is annealed in an oxygen atmosphere. In any of the cases, the gate oxide film of the MOS transistor has a thickness of about 10 nm.  
         [0078]    Referring to FIG. 8, it should be noted that the variation or degradation of the drain current  Δ Id with time is significantly suppressed by incorporating the N atoms into the gate oxide film excluding the region located immediately underneath the gate electrode.  
         [0079]    Further, the present invention is not limited to the embodiments described heretofore, but various variations and modifications may be made without departing from the scope of the invention.