Abstract:
An input buffer circuit consumes a small amount of power and operates rapidly. The input buffer circuit includes a differential amplifier, a buffer, and a switched current path connected to the differential amplifier. The differential amplifier receives an input signal and a reference voltage and generates an internal signal from a node in the differential amplifier. The buffer generates an output signal from the internal signal. The switched current path can include a current source and/or a current sink that includes series connected transistors with gates that respectively receive the input and output signals. The switched current path is temporarily activated to provide a current that reduces charging or discharging time of the node in the amplifier. The current thus reduces the delay time between edges in the input signal and corresponding edges in the output signal. Accordingly, the input buffer circuit operates rapidly. Additionally, the current path only conducts current during a limited time so that the input buffer circuit uses power efficiently.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device and more particularly, to an input buffer circuit in a semiconductor device. 
     2. Description of the Related Art 
     A clock signal typically has the highest operational frequency of any of the signals input into a semiconductor device, and the operational frequency of the clock signal increases with an increase in the operational speed of a system connected to the semiconductor device. Thus, semiconductor devices require a fast input buffer circuit to accept the clock signal. 
     FIG. 1 is a circuit diagram of a conventional input buffer circuit for a clock signal. Referring to FIG. 1, the conventional input buffer circuit includes a differential amplifier  11  and a buffer. The differential amplifier  11  uses a reference voltage VREF and in response to an input clock signal CLK, generates a signal OUTB having a phase that is approximately opposite to the phase of the clock signal CLK. The differential amplifier  11  outputs the signal OUTB from a node A in differential amplifier  11 , to the buffer  13 . The buffer  13  buffers the signal OUTB and changes the voltage level of the signal OUTB to output a CMOS-level signal DCLKB. 
     To operate the conventional input buffer circuit at a high frequency, a DC current through the differential amplifier  11  is increased by decreasing the resistance of a resistor R. Reducing the resistance R increases current that charges and discharges the node in the differential amplifier  11  when the input clock signal CLK changes voltage levels. However, when the DC current increases, power consumption increases. Also, the transconductance of a short-channel transistor is independent of the level of current and is proportional to the width of a channel, so that the operation speed does not increase past a certain critical point even if the resistance of the resistor R is zero. 
     SUMMARY OF THE INVENTION 
     An embodiment of the present invention provides an input buffer circuit that consumes a small amount of power and operates quickly. The input buffer circuit includes a differential amplifier, a buffer, and a switched current path (typically including a current source and/or a current sink). The differential amplifier receives an input signal and a reference voltage and outputs an internal signal having a phase approximately opposite to the phase of the input signal. The current source conducts a charging current to the differential amplifier to reduce the time required for the internal signal to transit from a logic “low” level to a logic “high” level. The current sink conducts a discharging current from the differential amplifier to reduce the time required for the internal signal to transit from the logic “high” level to the logic “low” level. In one embodiment, the input buffer circuit includes only one of the current source and the current sink in the switched current path. 
     In one embodiment, the differential amplifier includes a differential amplification unit for generating the internal signal in response to the input signal and the reference voltage, and a resistive device between one end of the differential amplification unit and ground. 
     According to one embodiment, the current source is between a power supply voltage and the node in the differential amplifier, and supplies a current to the node for a predetermined short period of time following the falling edge of the input signal. The current sink is between the differential amplification unit and ground and discharges a current from the differential amplification unit for a short period of time following the rising edge of the input signal. 
     According to another embodiment, the current source is between a power supply voltage and the node in the differential amplifier, and the current sink is between the node of the differential amplifier and ground. The current sink thus directly discharges a current from the node in the differential amplifier to ground for the short period of time following the rising edge of the input signal. 
     In the above embodiments, the current source can include first and second PMOS transistors connected in series between the power supply voltage and the output node of the differential amplifier. The output signal of the buffer is applied to the gate of the first PMOS transistor, and the input signal is applied to the gate of the second PMOS transistor. 
     The current sink includes first and second NMOS transistors connected in series between the differential amplifier and the ground voltage. The input signal is applied to the gate of the first NMOS transistor, and the output signal of the buffer is applied to the gate of the second NMOS transistor. The current sink can connect to an end of the differential amplifier or directly to the node in the differential amplifier. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: 
     FIG. 1 is a circuit diagram of a conventional input buffer circuit that accepts a clock signal; 
     FIG. 2 is a circuit diagram of an input buffer circuit according to an embodiment of the present invention; 
     FIG. 3 is a timing diagram illustrating the operation of the input buffer circuit of FIG. 2; 
     FIG. 4 is a circuit diagram of an input buffer circuit according to another embodiment of the present invention; 
     FIGS. 5A,  5 B, and  5 C show waveforms illustrating comparisons of simulations of the conventional input buffer circuit of FIG.  1  and the input buffer circuit of FIG. 2; and 
     FIG. 6 is a graph showing delay times versus the power supply voltage VDD in the conventional input buffer circuit of FIG.  1  and the input buffer circuit of FIG.  2 . 
     Use of the same reference symbols in different figures indicates similar or identical items. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, these embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not restricted to the embodiments disclosed. 
     FIG. 2 is a circuit diagram of an input buffer circuit according to an embodiment of the present invention. The input buffer circuit includes a differential amplifier  21  and a buffer  27 . The input buffer circuit also includes a current source  23  that reduces the rise time of the signal OUTB output from the differential amplifier  21 . More particularly, the current source  23  reduces the time taken for a transition of the signal OUTB from a logic “low” level to a logic “high” level. A current sink  25  reduces the fall time of the signal OUTB, that is, the time taken for a transition from the logic “high” level to the logic “low” level. 
     In the embodiment of FIG. 2, the input buffer circuit includes both the current source  23  and the current sink  25 . An alternative embodiment includes only the current source  23  or the current sink  25 . 
     The differential amplifier  21  receives a reference voltage VREF and the input clock signal CLK and outputs the signal OUTB from a node C. The differential amplifier  21  is a typical differential amplifier or a differential amplification unit. In the embodiment of FIG. 2, the differential amplifier  21  includes PMOS transistors P 21  and P 22 , NMOS transistors N 21  and N 22 , and resistors R 1  and R 2  acting as a resistive element. 
     A power supply voltage VDD is applied to the source of the PMOS transistor P 21 , which has a gate and drain connected together. The power supply voltage VDD is also applied to the source of the PMOS transistor P 22 , which has a gate connected to the gate of the PMOS transistor P 21 . The drain of the PMOS transistor P 22  is connected to the node C. 
     The drain of the NMOS transistor N 21  is connected to the drain of the PMOS transistor P 21 , and the reference voltage VREF is applied to the gate of the NMOS transistor N 21 . The drain of the NMOS transistor N 22  is connected to the node C, and the clock signal CLK is applied to the gate of the NMOS transistor N 22 . The sources of the NMOS transistors N 21  and N 22  are both connected to a node D. The resistors R 1  and R 2  are connected in series between the node D and a ground voltage VSS. 
     The NMOS transistor N 22  and the resistors R 1  and R 2  pull down the signal OUTB when the input signal CLK is at a voltage above the reference voltage VREF. The PMOS transistor P 22  pulls up the signal OUTB when the input signal CLK is at a voltage below the reference voltage VREF. The reference voltage VREF and the relative sizes of transistors P 21 , P 22 , N 21 , and N 22  and resistors R 1  and R 2  can be selected according to the desired trip point and amplification of the differential amplifier  21  using known circuit design techniques. Alternatively, the differential amplifier  21  can have various configurations, which are known to those skilled in the art. 
     The buffer  27  delays and buffers the signal OUTB output from the differential amplifier  21  and thereby generates a CMOS-level output clock signal DCLKB. In the embodiment of FIG. 2, the buffer  27  includes two inverters I 21  and I 22 , which are connected in series, but the buffer  27  alternatively can include other logic gates including, for example, a Schmitt trigger logic gate. 
     As described above, the current source  23  reduces the time required for the transition of the signal OUTB from the logic “low” level to the logic “high” level. More particularly, the current source  23  temporarily supplies a current to the node C in the differential amplifier  21  in response to the input clock signal CLK and the output signal DCLKB. The current source  23  includes first and second PMOS transistors P 23  and P 24 , which are connected in series between the power supply voltage VDD and the node C. The gate of the first PMOS transistor P 23  receives the output signal DCLKB, and the gate of the second PMOS transistor P 24  receives the input clock signal CLK. 
     The current sink  25  reduces the time required for the transition of the signal OUTB from the logic “high” level to the logic “low” level. In particular, the current sink  25  temporarily discharges a current from the node D in response to the input clock signal CLK and the output signal DCLKB. The current sink  25  includes first and second NMOS transistors N 23  and N 24 , which are connected in series between the node D and the ground voltage VSS. The gate of the first NMOS transistor N 23  receives the input clock signal CLK, and the gate of the second NMOS transistor N 24  receives the output signal DCLKB of the buffer  27 . In the embodiment of FIG. 2, the current sink  25  is between the junction of the resistors R 1  and R 2  and the ground voltage VSS. Alternative connections can also discharge current from the node D and are in accordance with the invention. 
     FIG. 3 is a timing diagram illustrating the operation of the input buffer circuit of FIG.  2 . As shown in FIG. 3, the phase of the clock signal CLK is nearly opposite to that of the output signal DCLKB of the buffer, and a delay time t corresponds to a phase difference between the signal CLK and the complement of the signal DCLKB. 
     During an initial time interval Si shown in FIG. 3, the input clock signal CLK is in the logic “low” state, and the output signal DCLKB of the buffer  27  is in the logic “high” state. The logic “high” state of the output signal DCLKB turns on the second NMOS transistor N 24  of the current sink  25 , but the logic “low” state of the clock signal CLK turns off the first NMOS transistor N 23  of the current sink  25 . Accordingly, no current flows through the current sink during the interval S 1 . Also during the interval S 1 , the clock signal CLK turns on the second PMOS transistor P 24 , but the output signal DCLKB turns off the first PMOS transistor P 23  so that no current flows through the current source  23 . That is, during the interval S 1 , no current flows via the current source  23  or the current sink  25 . 
     A time interval S 2  extends from the rising edge of the clock signal CLK, when the clock signal CLK transitions from the logic “low” level to the logic “high” level until the falling edge of the output signal DCLKB, when the output signal DCLKB transitions from the logic “high” level to the logic “low” level. The logic “high” levels of the clock signal CLK and the output signal DCLKB respectively turn on the NMOS transistors N 23  and N 24  of the current sink  25 , and a current flows through the current sink  25 . Accordingly, the current sink  25  discharges the node D of the differential amplifier  21  to the ground VSS during the interval S 2 . In response, the voltage level of the node C of the differential amplifier  21  quickly falls, which reduces the time required for the transition of the signal OUTB from the logic “high” level to the logic “low” level. While the signals CLK and DCLKB are at the logic “high” level, the first and second PMOS transistors P 23  and P 24  of the current source  23  are off, so that no current flows through the current source  23 . The fast drop in the signal OUTB makes the delay t between the rising edge of the clock signal CLK and the falling edge of the output signal DCLKB approximately equal to the delay time of the buffer  27 . 
     A time interval S 3  extends from the falling edge of the output signal DCLKB and the falling edge of the clock signal CLK. Accordingly, during the interval S 3 , the output signal DCLKB is at the logic “low” level and turns off the second NMOS transistor N 24  of the current sink  25 . Again, no current flows through the current sink  25  during the interval S 3 . Also, during the interval S 3 , the clock signal CLK is at the logic “high” level and turns off the second PMOS transistor P 24  of the current source  23 , so that no current flows through the current source  23 . Accordingly, no current flows through the current sink  25  or the current source  23  during the interval S 3 . 
     A time interval S 4  extends from the falling edge of the clock signal CLK until the next rising edge of the output signal DCLKB. During the time interval S 4 , the clock signal CLK and the output signal DCLKB respectively turn on the PMOS transistors P 24  and P 23  of the current source  23 , so that a current flows through the current source  23 . Accordingly, the current source  23  supplies a current from the power supply voltage VDD to the node C of the differential amplifier  21 . The current through the current source  23  quickly increases the voltage level of the node C of the differential amplifier  21 , and the current source  23  thereby reduces the time required for the signal OUTB to transition from the logic “low” level to the logic “high” level. Accordingly, the delay between the falling edge of the clock signal CLK and the rising edge of the output signal DCLKB is approximately equal to the delay time of the buffer  27 . 
     A time interval S 5  extends from the rising edge of the output signal DCLKB until the next rising edge of the clock signal CLK. During the time interval S 5 , the signals CLK and DCLKB are at the same levels as in the initial interval S 1 . In particular, the output signal DCLKB of the buffer is at a logic “high” level and turns off the first PMOS transistor P 23  of the current source  23 . Thus, no current flows through the current source  23  during the time interval S 5 . Also, the clock signal CLK is at the logic “low” level and turns off the first NMOS transistor N 23  of the current sink  25 , so that no current flows through the current sink  25 . Accordingly, no current flows through the current sink  25  or the current source  23  during the time interval S 5 . 
     Consequently, the input buffer circuit of FIG. 2 uses the current sink  25  to quickly discharge the node D of the differential amplifier  21  to the ground voltage VSS. Thus, the high-to-low transition time of the signal OUTB is reduced. Further, during each period of the clock signal CLK, the current sink  25  only draws current during the short time interval S 2  between the rising edge of the clock signal CLK and falling edge of the output signal DCLKB. Similarly, the current source  23  quickly supplies current from the power supply voltage VDD to the node C of the differential amplifier  21  to reduce the low-to-high transition time of the signal OUTB. During each period of the clock signal CLK, the current source  23  only supplies current during the short time interval S 4  between the falling edge of the clock signal CLK and the rising edge of the output signal DCLKB. Thus, the current source  23  uses only a relatively small amount of power to increase the transition speed and the response time of the input buffer circuit of FIG.  2 . 
     FIG. 4 is a circuit diagram of an input buffer circuit according to another embodiment of the present invention. The constituents of the input buffer circuit of FIG. 4 are the same as those of the input buffer circuit of FIG. 2, except for the connection of a current sink  45 . In the input buffer circuit of FIG. 4, the current sink  45  connects to the node C in the differential amplifier  21 . FIG. 4, like FIG. 2, shows an input buffer circuit that includes both a current source  23  and a current sink  45 . Alternatively, only one of them is included. 
     The operation of the input buffer circuit of FIG. 4 is the same as that of the input buffer circuit of FIG. 2, except that the current sink  45  directly discharges a current from the node C in the differential amplifier  21  to the ground voltage VSS. Thus, the operation of the input buffer circuit of FIG. 4 is not further described here. 
     The current source and the current sink can be adopted in a general input buffer and an internal circuit that operate at high speed, and in the differential amplification input buffer such as shown in FIGS. 2 and 4. 
     FIGS. 5A through 5C are graphs of waveforms illustrating the results of simulations of the conventional input buffer circuit of FIG.  1  and the input buffer circuit of FIG.  2 . FIG. 5A shows a clock signal CLK as input to either buffer circuit, FIG. 5B shows the signals OUTB output from the differential amplifiers  11  and  21 , and FIG. 5C shows the output signals DCLKB of the buffers  13  and  27 . 
     The simulation conditions were: a power supply voltage VDD of 2.4V, a reference voltage VREF of 1.4V, a resistance R 1  of 1.5KΩ, a resistance R 2  of 3.5KΩ, and a level of the clock signal CLK ranging from 0.7 to 2.1V. Also, the channel lengths of the NMOS transistors N 21  through N 24  were 0.7μm, the channel length of the PMOS transistors P 21  through P 24  were 0.8μm, and the width of the channel of each transistor is shown in Table 1. 
     
       
         
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                   
                 Width of channel 
                   
                 Width of channel 
               
               
                   
                 Transistor 
                 (μm) 
                 Transistor 
                 (μm) 
               
               
                   
                   
               
             
             
               
                   
                 N21 
                 12 
                 P21 
                 4 
               
               
                   
                 N22 
                 18 
                 P22 
                 6 
               
               
                   
                 N23 
                  3 
                 P23 
                 6 
               
               
                   
                 N24 
                  3 
                 P24 
                 6 
               
               
                   
                   
               
             
          
         
       
     
     In FIG. 5B, the curve B 1  represents the signal OUTB from the differential amplifier  21  of FIG. 2, and the curve B 2  represents the signal OUTB from the differential amplifier  11  of FIG.  1 . Comparison of curves B 1  and B 2  shows that the time during which the signal OUTB transitions from the logic “high” level to the logic “low” level is faster in the curve B 1  than in curve B 2 . Similarly, the time during which the signal OUTB transitions from the logic “low” level to the logic “high” level is faster in the curve B 1  than in the curve B 2 . 
     In FIG. 5C, a curve C 1  represents the output signal DCLKB from the buffer  27  of FIG. 2, and the curve C 2  represents the output signal DCLKB from the buffer  13  of FIG.  1 . Referring to FIG. 5C, the curves C 1  and C 2  show that the output signal DCLKB from the buffer  27  falls and rises more rapidly than the output signal DCLKB from the buffer  13 . Accordingly, the input buffer circuit according of FIG. 2 operates faster than the conventional input buffer circuit of FIG.  1 . 
     FIG. 6 contains graphs illustrating the dependence of time delays on the power supply volta ge VDD. A graph D 1  denotes the time interval from the rising edge of the clock signal CLK to the falling edge of the output signal DCLKB in the conventional input buffer circuit of FIG. 1. A graph D 2  denotes the time interval from the rising edge of the clock signal CLK to the falling edge of the output signal DCLKB in the input buffer circuit of FIG. 2. A graph D 3  denotes the time interval from the falling edge of the clock signal CLK to the rising edge of the output signal DCLKB in the conventional input buffer circuit of FIG. 1. A graph D 4  denotes the time interval from the falling edge of the clock signal CLK to the rising edge of the output signal DCLKB in the input buffer circuit of FIG.  2 . Referring to FIG. 6, the time delay of the input buffer circuit of FIG. 2 is short compared to the conventional input buffer circuit of FIG.  1 . 
     As described above, input buffer circuits according to embodiments of the present invention employ switched current paths including current sources and/or current sinks that only operate for a limited time. More particularly, a current sink quickly discharges a node to the ground voltage VSS during a short time following the rising edge of the clock signal CLK, and thereby reduces the time required for the node to transit from the logic “high” level to the logic “low” level. A current source supplies a current from the power supply voltage VDD during a short time following the falling edge of the clock signal CLK and thereby reduces the time required for the node to transit from the logic “low” level to the logic “high” level. Accordingly, the input buffer circuits according to embodiments of the present invention have higher operating speeds. Also, since the current sink and the current source do not continuously conduct current, the input buffer circuits according to embodiments of the present invention consume less power when compared to a conventional input buffer circuit, having the same operation speed. 
     Although the invention has been described with reference to a particular embodiment, it will be apparent to one of ordinary skill in the art that modifications of the described embodiment may be made without departing from the spirit and scope of the invention.