Abstract:
In one aspect of the present invention, a semiconductor device may include an isolation region provided in a semiconductor substrate and defining an active region, a gate electrode provided on the semiconductor substrate via a gate dielectric layer in the active region, a channel region provided below the gate electrode, a strain supplying layer provided between the channel region and the isolation region and being epitaxially grown, and configured to generate a strain in the channel region, a silicide layer provided on the strain supplying layer, a reformed layer provided between the silicide layer and the semiconductor substrate near the isolation region, and provided under the strain supplying layer, a source/drain region provided in a part of the strain supplying layer and a part of the reformed layer.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2007-3496, filed on Jan. 11, 2007, the entire contents of which are incorporated herein by reference. 
       BACKGROUND 
       [0002]    In a conventional semiconductor device, a recess is formed in the Si substrate and a SiGe crystal which has a different lattice constant to the Si substrate is epitaxially grown on the recess so as to induce a strain to the channel. 
         [0003]    However, a gap may be provided between the isolation region (STI) and the grown SiGe layer, since the SiGe crystal is grown toward a predetermined direction and the SiGe crystal is not grown from the isolation region. 
         [0004]    So when the SiGe layer which has a gap near the isolation region is silicided, a silicide may be formed even in a deeper portion along the gap. When the silicide is in contact with the Si substrate, the silicidation reaction is proceeded radically toward inside of the Si substrate, since the ternary compound NiSiGe or the like is thermal dynamically unstable. So the silicide layer may be also provided in the Si substrate below the source/drain region. In such case, the junction current from the silicide to the Si substrate may me increased. 
       SUMMARY 
       [0005]    Aspects of the invention relate to an improved semiconductor device. 
         [0006]    In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, an isolation region provided in the semiconductor substrate and defining an active region, a gate electrode provided on the semiconductor substrate via a gate dielectric layer in the active region, a channel region provided below the gate electrode, a strain supplying layer provided between the channel region and the isolation region and being epitaxially grown, and configured to generate a strain in the channel region, a silicide layer provided on the strain supplying layer, a reformed layer provided between the silicide layer and the semiconductor substrate near the isolation region, and provided under the strain supplying layer, a source/drain region provided in a part of the strain supplying layer and a part of the reformed layer. 
         [0007]    In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, an isolation region provided in the semiconductor substrate and defining an active region, a gate electrode provided on the semiconductor substrate via a gate dielectric layer in the active region, a channel region provided below the gate electrode, a strain inducing layer provided between the channel region and the isolation region and being epitaxially grown, and configured to generate a strain in the channel region, and having a slanted surface which is in contact with the isolation region, a silicide layer provided on the strain inducing layer, an interposed layer provided between the silicide layer and the semiconductor substrate near the isolation region, and provided under the strain inducing layer, and having an element in the semiconductor substrate, a source/drain region provided in a part of the strain inducing layer and a part of the interposed layer. 
     
    
     
       BRIEF DESCRIPTIONS OF THE DRAWINGS 
         [0008]    A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings. 
           [0009]      FIG. 1  is a cross sectional view of a semiconductor device in accordance with a first embodiment. 
           [0010]      FIGS. 2A-2M  are cross sectional views showing a manufacturing process of the semiconductor device in accordance with a first embodiment. 
           [0011]      FIG. 3  a cross sectional view of a semiconductor device in accordance with the second embodiment. 
           [0012]      FIG. 4  a cross sectional view of a semiconductor device in accordance with a third embodiment. 
           [0013]      FIGS. 5A-5F  are cross sectional views showing a manufacturing process of the semiconductor device in accordance with the third embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    Various connections between elements are hereinafter described. It is noted that these connections are illustrated in general and, unless specified otherwise, may be direct or indirect and that this specification is not intended to be limiting in this respect. 
         [0015]    Embodiments of the present invention will be explained with reference to the drawings as next described, wherein like reference numerals designate identical or corresponding parts throughout the several views. 
       First Embodiment 
       [0016]    A first embodiment of the present invention will be explained hereinafter with reference to  FIGS. 1-2D . 
         [0017]      FIG. 1  is a cross sectional view of a semiconductor device  1  in accordance with the first embodiment. In the semiconductor device  1 , a transistor provided in an active region defined by an isolation region  4 . 
         [0018]    The transistor is a p type transistor, which has a gate electrode  8  provided on a Si substrate  2  via a gate dielectric layer  7 , a gate sidewall  9 , a SiGe layer  3 , a source/drain region  5  provided in the Si substrate  2  and the SiGe layer  3 , a gate silicide layer  10  provided on the gate electrode  8 , and a source/drain silicide layer  6  provided on the source/drain region  5 . The source/drain region  5  includes an extension region  5   a.    
         [0019]    The isolation region  4  is made of, for example, a dielectric such as a SiO 2  or the like and has a STI (Shallow Trench Isolation) structure. 
         [0020]    The gate electrode  8  is made of, for example, polycrystalline silicon. The gate silicide layer  10  is made of, for example, a silicide having a metal such as a Ni, Pt, Co, Er, NiPt, CoNi or the like. 
         [0021]    The gate dielectric layer  7  is made of, for example, a SiO 2 , SiN, or high dielectric constant material (high-k material; Hf based material such as HfSiON, HfSiO and HfO; Zr based material such as ZrSiON, ZrSiO, ZrO; Y based material Y 2 O 3 ). 
         [0022]    The gate sidewall  9  is made of, for example, a single layered SiN, a two layered structure having SiN and SiO 2  or a three layered structure. An offset spacer may be provided between the gate electrode  8  and the gate sidewall  9 . 
         [0023]    The source/drain region  5  and the extension region  5   a  is formed by, for example, implanting a p type impurity ion such as B, BF2 or the like into the Si substrate  2  and SiGe layer  3 . 
         [0024]    The ion implantation region  3   a  of the SiGe layer  3  is formed by implanting a Ge ion into the Si substrate  2 . The SiGe layer  3  has an ion implantation region  3   a  which is abutting to the isolation region  4  and an epitaxial growth region  3   b  which is formed by an epitaxially growth. It may be preferable that the Ge concentration in the ion implantation region  3   a  and the epitaxial growth region  3   b  is 10-30 atom %. When the Ge concentration is less than 10 atom %, the stress to the channel may be small. When the Ge concentration is more than 30 atom %, the crystal defect in the SiGe layer  3  may be large. 
         [0025]    The SiGe crystal has a different lattice constant to the Si crystal. So, a strain is induced from the SiGe layer  3  to the channel region in the Si substrate  2 . Especially, the epitaxial growth region  3   b  improves the electron mobility in the channel region by providing a compressive stress to the channel region. The depth of the epitaxial growth region  3   b  is preferably no more than 100 nm. Even if the depth of the epitaxial growth region  3   b  is more than 100 nm, the strain generated in the channel region is not increased as much and manufacturing time and throughput may be worsened. 
         [0026]    A slanted portion is provided in the epitaxial growth region  3   b  near the isolation region  4 . A gap is provided the isolation region  4  and the source/drain silicide layer  6  on the epitaxial growth region  3   b.    
         [0027]    The source/drain silicide layer  6  is made of, for example, a compound of SiGe and a metal such as a Ni, Pt, Co, Er, NiPt or the like. 
         [0028]    The source/drain silicide layer  6  is provided on the SiGe layer  3  and not in contact with the Si substrate  2 . In other words, the SiGe layer  3  is interposed between the source/drain silicide layer  6  and the Si substrate  2 . 
         [0029]    The lower part of the source/drain silicide layer  6  is provided above the bottom of bottom part of the source/drain region  5 . 
         [0030]    Next, a manufacturing process of the semiconductor device  1  will be explained hereinafter with reference to  FIGS. 2A-2M . 
         [0031]    As shown in  FIG. 2A , a resist  11  is provided on the Si substrate  2 . 
         [0032]    As shown in  FIG. 2B , a first trench  12  is provided by etching with the resist  11  as a mask. 
         [0033]    As shown in  FIG. 2C , the Ge is implanted into the Si substrate  2  from the surface of the first trench  12  by ion implantation method. So the ion implantation region  3   a  of the SiGe layer  3  is provided near the surface of the first trench  12 . 
         [0034]    As shown in  FIG. 2D , a dielectric material is provided so as to fill the first trench  12  and a planarization is provided such that the resist  11  is exposed. 
         [0035]    As sown in  FIG. 2E , the resist  11  is removed by etching. 
         [0036]    As shown in  FIG. 2F , the gate dielectric layer  7 , the gate electrode  8  and a dummy sidewall  13  is provided on the Si substrate  2 . 
         [0037]    As shown in  FIG. 2G , a second trench  14  is provided in the Si substrate  2  by etching with the dummy sidewall  13  as a mask edge. The second trench  14  is provided with self-aligned to the isolation region  4  and the gate electrode  8 . 
         [0038]    As shown in  FIG. 2H , the SiGe crystal is epitaxially grown on the exposed surface of the Si substrate  2  and the SiGe layer  3 . So the epitaxial growth region  3   b  is provided. The epitaxial growth is provided in the chemical deposition chamber, and an ambient with monosilane (SiH 4 ) or dichlorosilane (SiHCl 2 ), germanium tetrahydride (GeH 4 ), hydrogen gas and the like in 700-750 Centigrade. 
         [0039]    The SiGe crystal is grown toward in a predetermined direction by the crystal characteristic. The SiGe crystal is not grown from the isolation region  4 . So a facet  3   c  is provided on a top surface of the SiGe layer  3 . The facet  3   c  is slanted from the main surface of the Si substrate  2 . And the gap is provided between the isolation region  4  and the facet  3   c  of the SiGe layer  3 . 
         [0040]    As shown in  FIG. 2I , after the dummy sidewall  13  is removed, an impurity such as boron (B) or the like is implanted into the Si substrate  2  and the SiGe layer  3 , and the extension region  5   a  of the source/drain region  5  is formed. 
         [0041]    As shown in  FIG. 2J , the gate sidewall  9  is formed on a side of the gate electrode  8 . 
         [0042]    As shown in  FIG. 2K , the impurity such as boron (B) or the like is implanted into the Si substrate  2  and the SiGe layer  3  to the deeper portion than the extension region  5   a,  and the source/drain region  5  is formed. The source/drain region  5  near the isolation region  4  is formed in a deeper portion along the facet  3   c  of the SiGe layer  3   
         [0043]    As shown in  FIG. 2L , a metal layer  15  which is made of a Ni or the like is provided on the surface of the gate electrode  8  and the SiGe layer  3  by sputtering. 
         [0044]    As shown in  FIG. 2M , a heat treatment is provided, the metal layer  15  and the gate electrode  8  are reacted, and the metal layer  15  and the SiGe layer  3  are reacted. So the gate electrode  8  and the SiGe layer  3  are silicided. Thus the gate silicide layer  10  and the source/drain silicide layer  6  are formed on the gate electrode  8  and the SiGe layer  3 , respectively. 
         [0045]    In case the ion implantation region  3   a  of the SiGe layer  3  is not provided, the source/drain silicide layer  6  may be in contact with the Si substrate  2 . When there is a portion where the silicide layer  6  and the Si substrate  2  are in touch, the silicidation reaction proceeds to the inside of the Si substrate  2 . In such case, a junction leak current from the source/drain silicide layer  6  to the Si substrate  2  is increased. 
         [0046]    In case the source/drain silicide layer  6  is a Ni silicide, the Ni in the source/drain silicide layer  6  is agglomerated toward the Si in the Si substrate  2  so as to form stable NiSi and the silicidation reaction proceeds to the Si substrate 2 , since the ternary compound NiSiGe is thermal-dynamically unstable. The degration of the surface morphology in the source/drain silicide layer  6  may occur with the agglomeration of Ni, and the variation of the resistivity in the source/drain silicide layer  6  may be increased. 
         [0047]    On the other hand, in the semiconductor device  1  of the first embodiment, the source/drain silicide layer  6  is not in contact with the Si substrate  2 , since a reformed layer of the Si substrate  2  (interposed layer) which is the ion implantation region  3   a  is provided under the epitaxial growth region  3   b  of the SiGe layer  3 . So the silicidation reaction does not proceed to the Si substrate  2 . Namely, the ion implantation region  3   a  may function as the interposed layer between the source/drain silicide layer  6  and the Si substrate  2 . 
         [0048]    According to the semiconductor device in the first embodiment, the junction leak current from the source/drain silicide layer  6  to the Si substrate  2  and the variation of the resistivity may be reduced, since the source/drain silicide layer  6  is not in contact with the Si substrate  2 . 
       Second Embodiment 
       [0049]    A second embodiment is explained with reference to  FIG. 3 . 
         [0050]    In the second embodiment, the position (depth) of the source/drain region  5  is different from that in the first embodiment. 
         [0051]      FIG. 3  a cross sectional view of a semiconductor device in accordance with the second embodiment. 
         [0052]    The bottom part of the source/drain region  5  is deeper than the bottom part of the epitaxial growth region  3   b  of the SiGe layer  3  and is provided in the Si substrate  2  under the epitaxial growth region  3   b.    
         [0053]    The source/drain silicide layer  6  is provided on the SiGe layer  3  and is not in contact with the Si substrate  2 . The source/drain silicide layer  6  is not provided in a deeper portion than the source/drain region  5 . Namely, the lower part of the source/drain silicide layer  6  is provided above the bottom of bottom part of the source/drain region  5 . 
         [0054]    The semiconductor device  1  as shown in  FIG. 3  is manufactured such that the impurity for source/drain region  5  is implanted to deeper portion the bottom surface of epitaxial growth region  5   b  of the SiGe layer  3  during the process shown in  FIG. 2K . 
         [0055]    When the source/drain silicide layer  6  is provided in a deeper portion than the source/drain region  5 , the leak current may occur from the source/drain silicide layer  6  to the Si substrate  2  even if the source/drain silicide layer  6  is not in contact with the Si substrate  2 . So the source/drain region  5  is provided enough deep to interpose between the source/drain silicide layer  6  and the Si substrata  2 . 
       Third Embodiment  
       [0056]    A third embodiment is explained with reference to  FIGS. 4-5B . 
         [0057]    In this third embodiment, the source/drain region  5  is different in shape and formation process from the source/drain region  5  in the first and second embodiment. 
         [0058]      FIG. 4  a cross sectional view of a semiconductor device in accordance with a third embodiment. 
         [0059]    The bottom of the source/drain region  5  is provided deeper than the epitaxial growth region  3   b  of the SiGe layer  3  and is provided in the Si substrate  2  under the epitaxial growth region  3   b.    
         [0060]    Near the isolation region  4 , the shape of the source/drain region  5  is not corresponding to the top surface (facet  3   c ) of the SiGe layer  3  with comparing to that in the first embodiment. The bottom of the source/drain region  5  near the isolation region  4  is substantially horizontal. 
         [0061]    The source/drain region  5  is formed by diffusing and activating a p type impurity ion (B, BF 2  or the like) in the epitaxial growth region  3   b  of the SiGe layer  3  with a heat treatment. 
         [0062]    The source/drain silicide layer  6  is formed on the SiGe layer  3  and not in contact with the Si substrate  2 . The source/drain silicide layer  6  is not provided in a deeper portion than the source/drain region  5 . 
         [0063]    Next, a manufacturing process of the semiconductor device  1  in accordance with the third embodiment will be explained hereinafter with reference to  FIGS. 5A-5F . 
         [0064]      FIGS. 5A-5F  are cross sectional views showing a manufacturing process of the semiconductor device in accordance with the third embodiment. 
         [0065]    A process as shown  FIGS. 2A-2G  is provided, and the second trench  14  is provided in the Si substrate 2 . 
         [0066]    As shown in  FIG. 5A , the SiGe crystal including a p type impurity ion such as B or the like is epitaxially grown on the exposed surface of the Si substrate  2  and the SiGe layer  3 . So the epitaxial growth region  3   b  is provided. The epitaxial growth is provided in the chemical deposition chamber, and an ambient with monosilane (SiH 4 ) or dichlorosilane (SiHCl 2 ), germanium tetrahydride (GeH 4 ), hydrogen gas and the like in 700-750 Centigrade. 
         [0067]    The SiGe crystal is grown toward in a predetermined direction by the crystal characteristic. The SiGe crystal is not grown from the isolation region  4 . So a facet  3   c  is provided on a top surface of the SiGe layer  3 . The facet  3   c  is slanted from the main surface of the Si substrate  2 . And the gap is provided between the isolation region  4  and the facet  3   c  of the SiGe layer  3 . 
         [0068]    As shown in  FIG. 5B , after the dummy sidewall  13  is removed, an impurity such as boron (B) or the like is implanted into the Si substrate  2  and the SiGe layer  3 , and the extension region  5   a  of the source/drain region  5  is formed. 
         [0069]    As shown in  FIG. 5C , the gate sidewall  9  is formed on a side of the gate electrode  8 . 
         [0070]    As shown in  FIG. 5D , the p type impurity ion in the SiGe layer  3  is diffused to the Si substrate  2  by a heat treatment, and the source/drain region  5  is provided. For example, the bottom of the source/drain region  5  may be provided no more than 10 nm from the bottom of the SiGe layer  3  by the heat treatment in about 900-1100 Centigrade ambient. The shape of the source/drain region  5  is not corresponding to the facet  3   c  of the SiGe layer  3 . 
         [0071]    As shown in  FIG. 5E , a metal layer  15  which is made of a Ni or the like is provided on the surface of the gate electrode  8  and the SiGe layer  3  by sputtering. 
         [0072]    As shown in  FIG. 5F , a heat treatment is provided, the metal layer  15  and the gate electrode  8  are reacted, and the metal layer  15  and the SiGe layer  3  are reacted. So the gate electrode  8  and the SiGe layer  3  are silicided. Thus the gate silicide layer  10  and the source/drain silicide layer  6  are formed on the gate electrode  8  and the SiGe layer  3 , respectively. 
         [0073]    Embodiments of the invention have been described with reference to the examples. However, the invention is not limited thereto. 
         [0074]    For example, a SiC layer or other layer having Si may be provided the substitute of the SiGe layer  3 . The SiC layer may be used in n type transistor, since the SiC layer provides a tensile stress to the channel so as to improve mobility of electron. The n type impurities for the source/drain region  5  are As, P or the like in the n type transistor. 
         [0075]    A raised source/drain structure, in which the top surface of the source/drain region is provided higher than the bottom of the gate dielectric layer  7 , is applied in the semiconductor device  1 . 
         [0076]    Other embodiments of the present invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and example embodiments be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following.