Abstract:
A solid-state imaging device includes a plurality of pixels, which convert light into signal voltages, and a plurality of analog-digital (AD) converters, which convert the signal voltages into a plurality of digital signals. Each of the plurality of AD converters includes an analog circuit, which receives a same power as a power of the plurality of pixels, and a digital circuit, which receives power having a voltage lower than a voltage of the analog circuit. The solid-state imaging device further includes a controller configured to suspend supplying the same power to the analog circuit, which is included in one of the plurality of AD converters that has finished a conversion.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is a continuation application of pending U.S. application Ser. No. 12/212,328, filed on Sep. 17, 2008, the contents of which are expressly incorporated by reference herein in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    (1) Field of the Invention 
         [0003]    The present invention relates to solid-state imaging devices, and more particularly, to a solid-state imaging device including an AD converting circuit for each of columns. 
         [0004]    (2) Description of the Related Art 
         [0005]    Solid-state imaging devices, converting light into electric signals, are utilized in various electric appliances, such as digital video cameras, digital still cameras, and fax machines. CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal-Oxide Semiconductor) image sensors are well known as solid-state imaging devices. 
         [0006]    A CMOS image sensor AD-converts an electric signal read from pixels arranged in a matrix, and outputs the converted electric signal, a resulting digital signal, out of the sensor. 
         [0007]    As a conventional CMOS image sensor, there is a solid-state imaging device including an AD converting circuit for each of columns and outputting an AD converted digital signal on a line-to-line basis (See Japanese Unexamined Patent Application Publication No. 2005-303648). 
         [0008]    A conventional solid-state imaging device, including an AD converting circuit for each of columns, shall be described hereinafter. 
         [0009]      FIG. 1  is a block diagram exemplifying a structure of the conventional solid-state imaging device. A conventional solid-state imaging device  500  in  FIG. 1  includes a pixel array  501 , a column scanning unit  502 , an AD converting unit  503 , a reference voltage generating unit  504 , a row scanning unit  505 , an output unit  506 , and a timing controlling unit  507 . 
         [0010]    The pixel array  501  includes pixels  508  arranged in a matrix. Each of the pixels  508  converts received light into a signal voltage, and provides the converted signal voltage to a column signal line provided on each of columns. 
         [0011]    The column scanning unit  502  sequentially selects lines of the pixels  508 . 
         [0012]    The AD converting unit  503  dynamically converts each of signal voltages provided to associated column signal lines into a digital signal. The AD converting unit  503  includes an AD converting circuit on each column, and each of AD converting circuits includes a comparator  509 , and a counter  511 . 
         [0013]    Each comparator  509  compares the signal voltage provided to the column signal line and a reference voltage RAMP, and then outputs an output signal showing the greater voltage, either the signal voltage or the reference voltage RAMP. 
         [0014]    Using a clock ADCLK, the counter  511  counts a count value. The counter  511  suspends the counting, upon the output signal outputted from the comparator  509  inverting. 
         [0015]    The reference voltage generating unit  504  generates the reference voltage RAMP. 
         [0016]    The row scanning unit  505  sequentially selects columns of the associated pixels  508 . 
         [0017]    The output unit  506  outputs the digital signals converted by the AD converting unit  503  out of the conventional solid-state imaging device  500 . 
         [0018]    The timing controlling unit  507  controls operational timing of the column scanning unit  502 , the AD converting unit  503 , the reference voltage generating unit  504 , and the row scanning unit  505 . 
         [0019]    The above structure allows the conventional solid-state imaging device  500  to AD-convert the signal voltages generated the pixels  508  on a line-to-line basis, and then to outputs the AD-converted signal voltages; namely digital signals. 
         [0020]    The solid-state imaging device  500 , however, includes as many AD converting circuits as the number of columns of the pixel  508 . Thus, unfortunately, a consumption current of the AD converting unit  503  is large. Specifically, a bias current of the comparator  509  on each column is approximately 10 μA. Having approximately 2500 columns, the consumption current of the AD converting unit  503  is 25 mA. This increases the power consumption of the conventional solid-state imaging device  500 . Moreover, in the case where the number of the pixels increases in the future, the power consumption of the AD converting unit  503  increases further. 
         [0021]    In addition, a typical digital still camera and a digital video camera are battery-powered. Hence, in order to realize long recording time on digital still cameras and digital video cameras, solid-state imaging devices in the digital still cameras and the digital video cameras are desired to consume small amount of electricity. 
       SUMMARY OF THE INVENTION 
       [0022]    The present invention is conceived in view of the above problems and has as an objective to provide a solid-state imaging device reducing power consumption. 
         [0023]    In order to solve the above problems, a solid-state imaging device in the present invention includes: pixels, arranged in a matrix, each of which converts light into a signal voltage; column signal lines each of which is provided for corresponding one of columns on which the pixels are arranged, so that the signal voltage generated by the pixel is provided to corresponding one of the column signal lines; and AD converting units each of which is provided for the corresponding one of the column signal lines, and configured to convert the signal voltage into a digital signal, wherein each of the AD converting units includes: a comparing unit configured to generate an output signal indicating a greater voltage of the signal voltage and a reference voltage; and a counting unit configured to count a count value to measure an elapsed time until logic of the output signal is inverted, and the solid-state imaging device further includes a suspending unit configured to suspend power supply to the comparing units after the logic of the output signals is inverted. According to this structure, the solid-state imaging device of the present invention can reduce power consumption by suspending power supply to the comparing unit. Here, in the solid-state imaging device, different kinds of supply power voltage are used for an analogue circuit and a digital circuit. The supply power voltage used for the analogue circuit is greater than the supply power voltage used for the digital circuit. Thus, the reduction of the power consumption of the comparing unit; namely the analogue circuit, significantly contributes to reduction of power consumption of the entire solid-state imaging device. 
         [0024]    In addition, the suspending unit may simultaneously suspend the power supply to all of the comparing units after elapse of the predetermined time since the counting unit starts the counting. 
         [0025]    According to this structure, power supply to all the comparing units is simultaneously suspended, which contributes reduction of power consumption of the solid-state imaging device. Further, comparing with sequential suspension of power supply to each of the comparing units during an AD converting operation, the simultaneous power suspension reduces a fluctuation of power supply voltage and ground potential. This allows the solid-state imaging device of the present invention to reduce deterioration of picture quality. 
         [0026]    Moreover, the suspending unit may suspend the power supply to each of the comparing units upon inversion of the logic of the output signal generated by the comparing unit. 
         [0027]    According to this structure, the solid-state imaging device of the present invention sequentially suspends power supply to the comparing units in a column of which AD conversion operation has completed. This allows the solid-state imaging device of the present invention to reduce power consumption. 
         [0028]    Further, the suspending unit may include flip-flops which are provided for each of the corresponding AD converting units, and each of which has a clock input terminal and a data input terminal, the clock input terminal receiving the output signal generated by the comparing unit, and the data input terminal receiving a signal having predetermined logic, and the suspending unit may suspend the power supply to each of the comparing units upon inversion of logic of a signal provided to a data output terminal of the each of flip-flops, and the counting unit may count a time for the logic of the signal to invert, the signal being provided to the data output terminal of the each of flip-flops. 
         [0029]    This allows the solid-state imaging device of the present invention to avoid a metastable effect occurring when the output signal of the comparing unit changes. 
         [0030]    In addition, the suspending unit may include transistors which are provided for each of the corresponding AD converting units, and each of the transistors may fix the output signal, generated by the comparing unit, to logic shown as a result of the inversion of the logic of the output signal. 
         [0031]    Moreover, the suspending unit may further include inverting units which are provided for each of the corresponding AD converting units, and each of the inverting units may invert the logic of the output signal generated by the comparing unit, and each of the transistors may receive: the signal of which logic is inverted by the inverting unit into a gate; a signal having logic as the result of inverting the logic of the output signal into a source, and a drain in the transistor may be connected to an output terminal of the comparing unit. 
         [0032]    This structure allows circuit area of the solid-state imaging device of the present invention to be reduced, compared with a structure including a flip-flop. 
         [0033]    Further, the suspending unit may include a switching unit switching between a first suspending operation and a second suspending operation, the first suspending operation suspending the power supply to each of the comparing units upon the inversion of the logic of the output signal generated by the comparing unit is inverted, and the second suspending operation simultaneously suspending the power supply to all of the comparing units after the predetermined time elapses since the counting unit starts counting. 
         [0034]    According to this structure, the solid-state imaging device of the present invention can switch between an operation mode having priority on low power consumption and an operation mode having priority on high picture quality. 
         [0035]    Moreover, the present invention includes a controlling method for a solid-state imaging device which has: pixels, arranged in a matrix, each of which converts light into a signal voltage; column signal lines each of which is provided for corresponding one of columns on which the pixels are arranged, so that the signal voltage generated by the pixel is provided to corresponding one of the column signal lines; and AD converting units each of which is provided for the corresponding one of the column signal lines, and configured to convert the signal voltage into a digital signal, wherein each of the AD converting units includes: a comparing unit configured to generate an output signal indicating a greater voltage of the signal voltage and a reference voltage; and a counting unit configured to count a count value to measure an elapsed time until logic of the output signal is inverted, and the controlling method comprises suspending power supply to the comparing units after the logic of the output signals is inverted. 
         [0036]    This allows the solid-state imaging device of the present invention to reduce power consumption by suspending power supply to the comparing unit. It is noted that the present invention can be implemented as: a controlling method of a solid-state imaging device having characteristic units included in the solid-state imaging device as steps; and a program which causes a computer to execute the characteristic steps, as well as the solid-state imaging device as described above. As a matter of course, the program can be distributed thorough a recording medium, such as a CD-ROM, and a transmission medium, such as the Internet. 
         [0037]    As described above, the present invention can provide a solid-state imaging device which can reduce power consumption. 
       FURTHER INFORMATION ABOUT TECHNICAL BACKGROUND TO THIS APPLICATION 
       [0038]    The disclosure of Japanese Patent Application No. 2007-334715 filed on Dec. 26, 2007 including specification, drawings and claims is incorporated herein by reference in its entirety. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0039]    These and the other objects, advantages and features of the invention will become apparent from the following description thereof taken in conjunction with the accompanying drawings which illustrate a specific embodiment of the invention. In the drawings: 
           [0040]      FIG. 1  is a block diagram showing a structure of a conventional solid-state imaging device; 
           [0041]      FIG. 2  is a block diagram showing a structure of a solid-state imaging device in a first embodiment of the present invention; 
           [0042]      FIG. 3  shows a structure of an AD converting unit in the first embodiment of the present invention; 
           [0043]      FIG. 4  shows a structure of a comparator in the first embodiment of the present invention; 
           [0044]      FIG. 5  shows an operation of the AD converting unit in the first embodiment of the present invention; 
           [0045]      FIG. 6  shows an example of an output signal and a power down signal of the comparator in the first embodiment of the present invention; 
           [0046]      FIG. 7  shows a structure of an AD converting unit in a second embodiment of the present invention; 
           [0047]      FIG. 8  shows an operation of the AD converting unit in the second embodiment of the present invention; 
           [0048]      FIG. 9  shows an operation of the AD converting unit in the second embodiment of the present invention; 
           [0049]      FIG. 10  shows a structure of an AD converting unit in a third embodiment of the present invention; 
           [0050]      FIG. 11  shows an operation of the AD converting unit in the third embodiment of the present invention; 
           [0051]      FIG. 12  shows a structure of a modification example of the AD converting unit in the third embodiment of the present invention; 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0052]    Embodiments of a solid-state imaging device in the present invention shall be described in detail, referring to the drawings, hereinafter. 
       First Embodiment 
       [0053]    A solid-state imaging device in a first embodiment of the present invention sequentially causes comparators of AD converting circuits, of which AD conversion has completed, to go into a suspension state. This allows the solid-state imaging device in the first embodiment of the present invention to reduce power consumption. 
         [0054]    First, the solid-state imaging device in the first embodiment of the present invention shall be described. 
         [0055]      FIG. 2  is a block diagram showing a structure of a solid-state imaging device  100  in the first embodiment of the present invention. 
         [0056]    The solid-state imaging device  100  in  FIG. 2  is a CMOS image sensor, and includes a pixel array  101 , a column scanning unit  102 , an AD converting unit  103 , a reference voltage generating unit  104 , a row scanning unit  105 , an output unit  106 , and a timing controlling unit  107 . 
         [0057]    The pixel array  101  includes pixels  108  arranged in a matrix. Each of the pixels  108  converts received light into a signal voltage, and forwards the converted signal voltage to a column signal line provided to each of columns. 
         [0058]    The column scanning unit  102  performs column scanning sequentially selecting lines of associated pixels  108 . AD conversion unit  103  simultaneously converts signal voltages provided to the column signal lines into digital signals. 
         [0059]    The reference voltage generating unit  104  generates a reference voltage RAMP. 
         [0060]    The row scanning unit  105  performs row scanning sequentially selecting columns of associated pixels  108 . 
         [0061]    The output unit  106  outputs the digital signals converted by the AD conversion unit  103  out of the solid-state imaging device  100 . 
         [0062]    The timing controlling unit  107  controls operational timing of the column scanning unit  102 , the AD conversion unit  103 , the reference voltage generating unit  104 , and the row scanning unit  105 . 
         [0063]      FIG. 3  shows a structure of the AD converting unit  103 . 
         [0064]    AD converting unit  103  includes AD converting circuits  120  each of which is provided on an associated column signal line. Each of the AD conversion unit  120  converts a signal voltage  131 , provided to the associated column signal line, into a digital signal. The AD converting circuit  120  includes a comparator  109 , a power-down controlling unit  110  and a counter  111 . 
         [0065]    The comparator  109  compares the signal voltage  131  provided to the column signal line with the reference voltage RAMP, and then outputs an output signal  132  showing the greater voltage, either the signal voltage or the reference voltage RAMP. Specifically, the comparator  109  outputs: a low-level output signal  132  in the case where the signal voltage  131  is greater than the reference voltage RAMP; and a high-level output signal  132  in the case where the signal voltage  131  is smaller than the reference voltage RAMP. 
         [0066]    The power-down controlling unit  110  turns a power-down signal  133  into low-level upon logic of the output signal  132  inverting from low-level to the high-level. The power-down signal  133  is inputted into the comparator  109 . When the power-down signal  133  is in the high-level, the comparator  109  is in an operation state. When the power-down signal  133  is in low-level, the comparator  109  is in a suspension state (power-down state). In other words, the power-down controlling unit  110  suspends power supply to the comparator  109  upon logic of the output signal  132  inverting from low-level to the high-level. Specifically, the power-down controlling unit  110  suspends supplying driving current to the comparator  109 . 
         [0067]    The power-down controlling unit  110  includes a buffer  121  and a flip-flop  122 . 
         [0068]    The buffer  121  converts the output signal  132 , having amplitude of analogue circuit-based power supply voltage (3.3V, for example), into a signal having amplitude of digital circuit-based power supply voltage (1.2V, for example), and then inputs the signal into a clock input terminal of the flip-flop  122 . It is noted that the analogue circuit-based power supply voltage is supplied to the comparator  109 , and the digital circuit-based power supply voltage is supplied to the flip-flop  122  and the counter  111 . 
         [0069]    An output terminal of the buffer  121  is connected to the clock input terminal of the flip-flop  122 , and power supply voltage VDD is connected to a data input terminal of the flip-flop  122 . The flip-flop  122  outputs the power-down signal  133  to an inverted data output terminal. 
         [0070]    Using a clock ADCLK, the counter  111  counts a count value. The counter  111  counts the count value until the output signal  132  outputted from the comparator  109  inverts, so that a time is counted until the logic of the output signal  132  inverts. In other words, the counter  111  suspends the counting upon the output signal  132  reversing. 
         [0071]    The counter  111  includes an OR circuit  123  and a counter circuit  124 . To two input terminals of the OR circuit  123 , the clock ADCLK and the power-down signal  133  are connected, respectively. An output terminal of the OR circuit  123  is connected to a clock input terminal of the counter circuit  124 . 
         [0072]      FIG. 4  is a circuit diagram exemplifying a structure of the comparator  109 . 
         [0073]    When the power-down signal  133  is in the low-level, a transistor  128  turns on and a transistor  129  turns off. This turns a transistor  127  off. Hence, the driving current is not supplied to the comparator  109 , so that the comparator  109  goes into a suspension state. 
         [0074]    Further, the comparators  109  are connected to one driving current supplying circuit  126  supplying driving current to the comparators  109 . 
         [0075]    It is noted that the structure of the comparator  109  is not limited to the structure shown in  FIG. 4 , and may be structured to include a similar structure. For example, the transistor  129  is connected in series to a drain side of a p-type transistor structuring a current mirror with the driving current supplying circuit  126 ; meanwhile, the transistor may be connected in series to a source side. 
         [0076]    Next, an operation of the solid-state imaging device  100  in the first embodiment of the present invention shall be described. 
         [0077]      FIG. 5  shows AD converting operations on the AD converting unit  103 . 
         [0078]    First, when an AD converting process starts, the flip-flop  122  and the counter circuit  124  are reset. In addition, the clock ADCLK is supplied to the AD converting unit  103 . The reset causes the flip-flop  122  to generate the high-level power-down signal  133 . 
         [0079]    Since the power-down signal  133  is in the high-level, the comparator  109  is in the operation state. Further, the reference voltage (lamp signal) RAMP is smaller than the signal voltage  131  before a time t 0 . Thus, the comparator  109  outputs the low-level output signal  132 . 
         [0080]    Further, the power-down signal  133  is in the high-level, the clock ADCLK is supplied to the counter circuit  124 . This causes the counter circuit  124  to count the count value. 
         [0081]    At the time t 0 , the signal voltage  131  and the reference voltage RAMP meet each other. This changes the output signal  132  of the comparator  109  from the low-level to the high-level. 
         [0082]    From a rising edge of the output signal  132 , the flip-flop  122  holds the high-level. After rising of the edge, the flip-flop  122  generates the low-level power-down signal  133 . 
         [0083]    Since the power-down signal  133  is in the low-level, the clock ADCLK is not supplied to the counter circuit  124 . This causes the counter circuit  124  to hold the count value as of the time t 0 . 
         [0084]    Further, since the power-down signal  133  is in the low-level, the comparator  109  goes into the suspension state. In the suspension state, the comparator  109  outputs either the high-level or the low-level output signal  132 . 
         [0085]    Here, the signal voltage  131  to be provided to the associated column signal line differs depending on an amount of incident light (luminance) into the pixels  108 . Thus, each of the comparators  109  goes into the suspension state at a different timing. 
         [0086]    As described above, the AD converting unit  103  in the first embodiment of the present invention sequentially causes the AD converting circuits  120 , of which AD conversion has completed, to go into the suspension state. This reduces the consumption current of the AD converting unit  103 . Thus, the solid-state imaging device  100  in the first embodiment of the present invention can reduce power consumption. Assuming that an average time required for the AD conversion process for each column is approximately half as long as a time required for the longest AD conversion process, the AD converting unit  103  in the first embodiment of the present invention can cut power consumption in half, compared to the conventional AD conversion unit  503 . 
         [0087]    Further, since including the flip-flop  122 , the AD converting unit  103  can avoid a metastable effect occurring when the output signal  132  of the comparator  109  changes. 
         [0088]      FIG. 6  shows the output signal  132  and the power-down signal  133  when the output signal  132  changes.  FIG. 6  ( a ) shows the output signal  132 .  FIG. 6  ( b ) is a diagram showing, for comparison, the power-down signal  134  when flip-flop  122  is not used.  FIG. 6  ( c ) shows the power-down signal  133  in the AD converting unit  103  in the first embodiment of the present invention. 
         [0089]    As shown in  FIG. 6  ( a ), the output signal  132  swings when changing. As shown in  FIG. 6  ( b ), the swing causes the change of the power-down signal  134  based on logical threshold values Vth of the buffer  121  and the flip-flop  122 . Thus, the power-down signal  134  cannot be controlled. This destabilizes the operations of the counter  111  and the comparator  109  into which the power-down signal  134  is inputted. 
         [0090]    Meanwhile, as shown in  FIG. 6  ( c ), use of flip-flop  122 : changes the power-down signal  133  at the first moment that the output signal  132  exceeds the logical threshold value Vth; and holds the logic of the power-down signal  133  regardless of the swing caused by the output signal  132  after the change. 
         [0091]    Thus, the AD converting unit  103  in the first embodiment of the present invention can avoid the effect of the swing caused by the output signal  132 . 
       Second Embodiment 
       [0092]    In a second embodiment of the present invention, a structural modification example shall be described with regard to the power-down controlling unit  110  of the solid-state imaging device  100  in the first embodiment. 
         [0093]    First, a structure of a solid-state imaging device in the second embodiment shall be described. 
         [0094]    The structure of the solid-state imaging device  100  in the second embodiment is similar to the structure of the solid-state imaging device  100  in the first embodiment in  FIG. 2 , and thus, the description shall be omitted. 
         [0095]      FIG. 7  shows a structure of an AD converting unit  203  included in the solid-state imaging device  100  in the second embodiment of the present invention. It is noted that, in  FIG. 7 , the same elements as the elements in  FIG. 3  share the same numerical references, and thus detailed descriptions of the elements in  FIG. 7  shall be omitted. 
         [0096]    The AD converting unit  203  includes AD converting circuits  220  provided on each of column signal lines. Each of the AD converting circuits  220  includes a comparator  209 , a power-down controlling unit  210 , and a counter  111 . 
         [0097]    The comparator  209  compares the signal voltage  131  provided to the column signal line and the reference voltage RAMP, and then outputs an output signal  232  showing the bigger voltage, either the signal voltage  131  or the reference voltage RAMP. Other than putting an output into a high-impedance state in a suspension state, operations of the comparator  209  are similar to the operations of the comparator  109  in the first embodiment. 
         [0098]    The power-down controlling unit  210  changes a power-down signal  233  into a low-level upon logic of an output signal  232  inverting from the low-level to a high-level. 
         [0099]    The power-down controlling unit  210  includes the buffer  121 , an NAND circuit  222 , and a transistor  223 . 
         [0100]    The buffer  121  converts the output signal  232 , having amplitude of analogue circuit-based power supply voltage, into a signal having amplitude of digital circuit-based power supply voltage, and then forwards the signal to the NAND circuit  222 , and the OR circuit  123 . 
         [0101]    A reset signal PDRST and the signal provided from the buffer  121  are respectively provided to two input terminals of the NAND circuit  222  as inputs. The NAND circuit  222  generates the power-down signal  233 . The reset signal PDRST is, for example, generated by the timing controlling unit  107 . 
         [0102]    The transistor  223  is a type-P MOS transistor. The transistor  223  receives: the power-down signal  233  into a gate as an input; and power supply voltage VDD into a source. Further, a drain of the transistor  223  is connected to an output terminal of the comparator  209 . The transistor  223  fixes the output signal  232  to the high-level after the output signal  232  inverts from the low-level to the high-level. 
         [0103]    Next, an operation of the solid-state imaging device  100  in the second embodiment of the present invention shall be described. 
         [0104]      FIGS. 8 and 9  show AD converting operations on the AD converting unit  203 . It is noted that description of similar AD converting operations of the AD converting unit  203  to the AD converting operation of the AD converting unit  103  are omitted, and thus, only differences of operations between the AD converting unit  103  and the AD converting unit  203  shall be described. 
         [0105]    First, when starting the AD converting operations, the reset signal PDRST temporarily becomes active (low-level), and the power-down signal  233  goes into the high-level. This causes the comparator  209  to go into an active state, and the comparator  209  generates a low-level output signal  232 . Further, the counter circuit  124  counts a count value. 
         [0106]    The signal voltage  131  and the reference voltage RAMP meet at the time t 0 . This changes the output signal  232  from the comparator  209  from the low-level to the high-level. 
         [0107]    This causes the power-down signal  233  to go into the low-level, and the counter circuit  124  holds the count value at the time t 0 . 
         [0108]    Meanwhile, the comparator  209 : goes into a suspension state; and puts the output into the high-impedance state. Further, turning the transistor  223  on causes the output signal  232  to stay in the high-level. 
         [0109]    As described above, the AD converting unit  203  in the second embodiment of the present invention, as well as the AD converting unit  103  in the first embodiment, sequentially causes the AD converting circuits  220 , of which AD conversion has completed, to go into the suspension state. This reduces the consumption current of the AD converting unit  203 . Thus, the solid-state imaging device  100  in the second embodiment of the present invention can reduce power consumption. 
         [0110]    It is noted that approximately 20 transistors are included in the power-down controlling unit  110  of the AD converting unit  103  in the first embodiment; meanwhile, just as many as five transistors are included in the power-down controlling unit  210  of the AD converting unit  203  in the second embodiment. This reduces the circuit area of the AD converting unit  203  in the second embodiment. 
         [0111]    Here, the number of flip-flops which the counter circuit  124  has is determined based on the AD conversion accuracy. Typical conversion accuracy of the counter circuit  124  is approximately a dozen bits. In this case, the circuit area of the AD converting unit  203  can be decreased by as large as five percent by using the AD converting unit  203  in the second embodiment, compared with the case where the AD converting unit  103  in the first embodiment is used. 
         [0112]    Moreover, a smaller pixel cell size increases the area, of the solid-state imaging device  100 , which the AD converting unit  203  occupies. This further increases the effect of the decreased circuit area. In other words, the AD converting unit  203  in the second embodiment achieves a greater effect in response to higher picture quality which the solid-state imaging device  100  achieves. 
       Third Embodiment 
       [0113]    A solid-state imaging device in a third embodiment of the present invention includes a first mode and a second mode. The first mode sequentially causes comparators, of which AD conversion has completed, to go into a suspension state. The second mode simultaneously stops power supply to the comparators upon passing an AD conversion period. 
         [0114]    First, a structure of the solid-state imaging device in the third embodiment shall be described. 
         [0115]    The structure of the solid-state imaging device  100  in the third embodiment is similar to the structure in  FIG. 2 , and thus, the description shall be omitted. 
         [0116]      FIG. 10  shows a structure of an AD converting unit  303  included in the solid-state imaging device  100  in the third embodiment of the present invention. It is noted, in  FIG. 10 , that the same elements as the elements in  FIG. 7  share the same numerical references, and thus detailed descriptions of the elements in  FIG. 10  shall be omitted. 
         [0117]    The AD converting unit  303  includes AD converting circuits  320  provided on each of column signal lines. Each of the AD converting circuits  320  includes the comparator  209 , the power-down controlling unit  310 , and the counter  111 . 
         [0118]    A power-down controlling unit  310  can be switched between the first mode and the second mode in response to a mode selecting signal MODSEL. The first mode sequentially causes the comparators  209 , of which AD conversion has completed, to go into the suspension state. The second mode simultaneously stops power supply to the comparators  209 . 
         [0119]    In addition to the structural elements of the AD converting circuit  220  in the second embodiment, the AD converting circuit  320  additionally includes a selector  324 . 
         [0120]    In the case where the mode selecting signal MODSEL is in a low-level, the selector  324  selects an all power-down signal ALLPD, and then forwards the selected all power-down signal ALLPD as a power-down signal  333 . In the case where the mode selecting signal MODSEL is in a high-level, meanwhile, the selector  324  selects a signal provided from the NAND circuit  222 , and then forwards the selected signal as the power-down signal  333 . In other words, the selector  324  switches between the first mode and the second mode in response to the mode selecting signal MODSEL. 
         [0121]    The all power-down signal ALLPD is generated by the timing controlling unit  107 . The mode selecting signal MODSEL is generated by the timing controlling unit  107  based on a mode selection operation by the user. 
         [0122]    Next, operations of the solid-state imaging device  100  in the third embodiment of the present invention shall be described. 
         [0123]      FIG. 11  shows AD converting operations on the AD converting unit  303 . It is noted that similar AD converting operations of the AD converting unit  303  to the AD converting operations of the AD converting unit  203  are omitted, and thus, only differences shall be described. 
         [0124]    In a period TO, in which the mode selecting signal MODSEL is in the low-level, the all power-down signal ALLPD changes from the low-level to the high-level before an AD conversion period starts. Upon ending the AD conversion period, the all power-down signal ALLPD changes from the high-level to the low-level. 
         [0125]    Since the mode selecting signal MODSEL is in the low-level, each of power-down controlling units  310  supplies the all power-down signal ALLPD to the associated comparator  209  as the power-down signal  333 . This simultaneously causes all the comparators  209  to go into the suspension state at a time t 3  after the AD conversion period ends. 
         [0126]    Here, an ending time of the AD conversion period is the time at which the AD converting operations by all the AD converting circuit  320  end. In other words, after inverting logics of output signals  332 , the power-down controlling units  310  suspends power supply to the corresponding comparators  209 . 
         [0127]    During a period T 1  in which the mode selecting signal MODSEL is in the high-level, the AD converting unit  303  performs similar operations to the operations on the AD converting unit  203  in the above described second embodiment. In other words, the power-down controlling unit  310  sequentially causes the AD converting circuits  320 , of which AD conversion has completed, to go into the suspension state during an AD conversion period T 2 . 
         [0128]    It is noted that each of the periods T 0  and T 1  shown in  FIG. 11  is as long as a single row scanning period (a period to read signals for one line) in length. Further, single row scanning periods for the respective first and second modes may be different in length. 
         [0129]    As described the above, the solid-state imaging device  100  in the third embodiment of the present invention can selectively utilize the first mode and the second mode. The first mode sequentially causes the comparators  209 , of which AD conversion has completed, to go into the suspension state. The second mode simultaneously stops power supply to the comparators  209 . 
         [0130]    Here, in the case where the AD converting circuits  320 , of which AD conversion has completed, sequentially go into the suspension state, high impedance on power supply and a GND line is assumed to causes a slight fluctuation of power supply voltage and ground potential during the AD conversion. This possibly causes degradation of picture quality. 
         [0131]    Hence, when low power consumption is prioritized, the first mode is used, and when high picture quality is prioritized, the second mode is used. Thus, a more appropriate mode can be used based on usage of the solid-state imaging device  100  in the third embodiment of the present invention 
         [0132]    Further, the first mode may be a moving picture mode to record a moving picture, and the second mode may be a still mode to record a still picture. 
         [0133]    The above has described the solid-state imaging device in the embodiments of the present invention; meanwhile, the present invention shall not be limited to the embodiments. 
         [0134]    In the above third embodiment, for example, the first mode and the second mode can be switched therebetween. In the meantime, the third embodiment may implement only the second mode simultaneously suspending power supply to the comparators  209 . This can also reduce power consumption of the solid-state imaging device  100  since the power supply to the comparators  209  is suspended upon ending the AD converting operation. 
         [0135]      FIG. 12  is a modification example of the third embodiment showing a structure of an AD converting unit  403 . The AD converting unit  403  only functions to simultaneously suspend power supply to the comparators  109 . 
         [0136]    As shown in  FIG. 12 , all the comparators  109  may simultaneously be suspended with the all power-down signal ALLPD generated by a power-down controlling unit  410 . 
         [0137]    In the above embodiments the structures of the AD converting units  103 ,  203 , and  303  have been described; meanwhile, the present invention shall not be limited to the structures as far as a structure can implement similar functions. For example, all or part of signal logic may be inverted, so that the structure of the circuit can be modified accordingly. 
         [0138]    Further, in the above second embodiment, the power-down controlling unit  210  includes the transistor  223 ; meanwhile, the power-down controlling unit  210 , without the transistor  223 , and, in the suspension state, the comparator  209  may output the high-level output signal  232 . Although only some exemplary embodiments of this invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention. 
       INDUSTRIAL APPLICABILITY 
       [0139]    The present invention is applicable to solid-state imaging devices, and more particularly, to a solid-state imaging device including an AD converting circuit for each of columns. In addition, the present invention can be applied to digital still cameras and digital video cameras including solid-state imaging devices.