Abstract:
A fully balanced transconductor circuit, such as by utilizing two 5 transistor tranconductors in a single circuit sharing the common mode node and operating them 180 degrees out of phase, to realize a current source in saturation under all conditions. The present invention may be utilized in a low power circuit with good jitter performance and large output swings.

Description:
PRIORITY CLAIM  
       [0001]     This application claims priority of U.S. Provisional application Ser. No. 60/583,796 entitled “Fully Balanced, Large Swing Transconductor” filed Jun. 28, 2004, the teaching of which are incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention is generally related to hard disk drive amplifiers, and more specifically to transconductors operable therein.  
       BACKGROUND OF THE INVENTION  
       [0003]     In data communication or linear applications, it is crucial to develop circuits with high bandwidth and low jitter. Additionally, having an amplifier with variable gain allows for circuit topologies which can handle large input dynamic ranges without performance degradation. To this end, fully differential circuits are well known for realizing low jitter circuits due to their inherent common-mode rejection and supply rejection characteristics.  
       SUMMARY OF THE INVENTION  
       [0004]     The present invention achieves technical advantages as a fully balanced transconductor circuit. In one embodiment of the invention, a fully balanced transconductor is realized utilizing two 5 transistor tranconductors in a single circuit sharing a common mode node and operable 180 degrees out of phase, such as to realize a current source in saturation under all conditions. The present invention may be utilized in a low power circuit with good jitter performance and large output swings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]      FIG. 1  is a schematic of a fully balanced differential circuit according to one embodiment of the present invention; and  
         [0006]      FIG. 2  is a waveform diagram of signals at various nodes of the circuit of  FIG. 1 .  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0007]     Standard five transistor transconductor circuits have been used as differential to single ended converters (CML to CMOS converters), but due to their inherent imbalances the jitter performance suffers since the current source will usually be pulled in and out of saturation. These transconductors are very simple, well understood, small, and low-power though so it is preferable to try and use these circuits.  
         [0008]     Referring to  FIG. 1 , there is shown a circuit  10  according to a first embodiment of the invention. Circuit  10  can be functionally viewed as two 5 transistor transconductors each labeled at  12  and  14 , each transconductor sharing a common bias current source provided by transistor MN 21 . The first transconductor  12  is composed of transistors MN 18 , MN 19 , MP 14 , and MP 15 , while the second transconductor  14  is composed of transistors MN 262 , MN 266 , MP 73 , and MP 74 . These two transconductor circuits  12  and  14  are operated 180 degrees out of phase to advantageously form a balanced, fully-differential, high gain, large output swing amplifier  10 .  
         [0009]     Transistor MN 21  sets a fixed bias current for the circuit  10 . The amount of current is user selectable, and is controlled through the gate connection to transistor MN 21  denoted as ‘VBIASN’ in  FIG. 1 . The drain of transistor MN 21  forms the common mode node needed for proper differential functionality of the two circuits  12  and  14 .  
         [0010]     Two differential pairs are formed by transistor pairs MN 18 /MN 19  and MN 262 /MN 266 , respectively. Current mirror pairs are formed by transistor pairs MP 14 /MP 15  and MP 73 /MP 74 , respectively.  
         [0011]     Circuit operation is as follows. The logic value of output node OP follows IP and node ON follows input node IN. When node IP is ‘high’ and node IN is ‘low’, the bias current provided by the current source MN 21  flows in transistors MN 266 /MP 74  and MN 19 . No current is flowing in transistors MN 18 /MP 14  and MN 262 . The result is that the current flowing through transistor MP 74  is mirrored to transistor MP 73 . Since node IN is ‘low’, no current is flowing in transistor MN 262 , therefore, current flows through transistor MP 73  long enough to pull output node OP ‘high’ or to VDD. Similarly, no current is flowing in transistors MN 18 /MP 14  since input node IN is ‘low’, therefore, current flows through transistor MP 19  long enough to pull node ON ‘low’ or to the common mode node voltage. For this circuit, ‘low’ is defined as the voltage on the common mode node defined by the drain of transistor MN 21 , and the sources of transistors MN 18 /MN 19 /MN 262 /MN 266 .  
         [0012]     After the circuit  10  stabilizes, all the bias current sourced by transistor MN 21  is flowing through the leg containing transistors MN 266 /MP 74 . Advantageously, this function keeps the bias current flowing properly through the current source.  
         [0013]     When node IP switches to ‘low’ and thus node IN switches to ‘high’, the bias current begins to flow through transistors MN 18 /MP 14  and MN 262 . Current is being shut off in transistors MN 19  and MN 266 /MP 74 . Therefore, the current in transistor MP 14  is being mirrored to that in transistor MP 15 . This pulls output node ON ‘high’. Similarly, the current through transistor MP 73  is cut off so that the current flows through transistor MN 262  long enough to pull node OP ‘low’ or to the common mode node voltage.  
         [0014]     After the circuit  10  stabilizes, all the bias current sourced by transistor MN 21  is flowing through the leg containing transistors MN 18 /MP 14 . This function keeps the current flowing properly through the current source.  
         [0015]     Referring now to  FIG. 2 , there is shown at  20  waveforms of various nodes of circuit  10 , depicting the bias current of transistor MN 21  in saturation at all times, and circuit  10  operating as a fully differential circuit with low jitter.  
         [0016]     The problems solved by this circuit are:  
         [0017]     Keeps the current flowing through the current source without interruption. This increases the bandwidth and improves jitter performance. This circuit remains in fully differential operation to take advantage of common mode rejection and power supply rejection. Finally, large output swings are maintained while achieving the above, from Vcommon mode to VDD.  
         [0018]     Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.