Abstract:
Disclosed is a semiconductor device. For instance, the semiconductor device includes a main via formed on a dielectric and a ground via formed in a circular arc shape and spaced apart from the main via. The semiconductor device is superior in electric characteristics such as insertion loss or reflection loss and allows efficient use of space.

Description:
TECHNICAL FIELD 
     The present invention relates to a semiconductor device. 
     BACKGROUND 
     Increasing integration density of various electronic devices is used as a mechanism to improve performance and/or reduce size. Integration density be enhanced by reducing a minimum device size or a stacking a plurality of dies. 
     Recently, a method of forming a penetration silicon via has been widely used to improve integration density. In general, a penetration silicon via is formed by forming a vertical via through a substrate and filling the via with a conductive material such as Cu. 
     Such a via is formed using a laser or an etching process, and the via is used to connect patterns of different layers. A ground via is formed around such a via, and the impedance of a pattern varies according to the position and shape of the ground via. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In order to understand the invention and to see how it may be carried out in practice, embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which: 
         FIG. 1A  is a plan view illustrating a semiconductor device according to an embodiment of the present invention; 
         FIG. 1B  is a sectional view taken along line  1 B- 1 B of  FIG. 1A ; 
         FIG. 1C  is a sectional view taken along line  1 C- 1 C of  FIG. 1A ; 
         FIG. 2A  is a plan view illustrating a semiconductor device according to another embodiment of the present invention; 
         FIG. 2B  is a sectional view taken along line  2 B- 2 B of  FIG. 2A ; 
         FIG. 3  is a plan view illustrating a semiconductor device of the related art; 
         FIG. 4  is a graph illustrating insertion loss of a related-art semiconductor device and insertion loss of the semiconductor devices of the present invention; 
         FIG. 5  is a graph illustrating reflection loss of the related-art semiconductor device and reflection loss of the semiconductor devices of the present invention; and 
         FIG. 6  is a flow chart diagram illustrating an exemplary method of manufacture of a semiconductor device of the present invention. 
     
    
    
     Common reference numerals are used throughout the drawings and the detailed description to indicate the same elements. 
     DETAILED DESCRIPTION 
     Referring to  FIG. 1A , a plan view of a semiconductor device is shown according to an embodiment of the present invention, and referring to  FIG. 1B , a sectional view taken along line  1 B- 1 B of  FIG. 1A  is shown. Referring to  FIG. 1C , a sectional view taken along line  1 C- 1 C of  FIG. 1A  is shown. 
     As shown in  FIGS. 1A through 1C , according to one embodiment of the present invention, a semiconductor device  100  includes a dielectric  110 , a main via  120 , and at least one ground via  130 . Here, the dielectric  110 , the main via  120 , and the at least one ground via  130  may be formed on a wafer, a semiconductor die, or a circuit board. 
     The dielectric  110  has approximately flat top and bottom surfaces. The main via  120  and the ground via  130  may be formed through the top and bottom surfaces of the dielectric  110 . The dielectric  110  may be formed of a material selected from polyimide (Pi), benzo cyclo butene (BCB), poly benz oxazole (PBO), bismaleimide triazine (BT), phenolic resin, epoxy, silicone, SiO2, Si3N4 and an equivalent thereof, but the present invention is not limited thereto. 
     In addition, a first signal pattern  111  may be formed on the top surface of the dielectric  110 , and a second signal pattern  112  may be formed on the bottom surface of the dielectric  110 . The first signal pattern  111  and the second signal pattern  112  are paths through which signals are transmitted. The first signal pattern  111  and the second signal pattern  112  may include Cu, Ti, Ni, Pd or a equivalent thereof, but not limited thereto. 
     The main via  120  is formed through the top and bottom surfaces of the dielectric  110 . The main via  120  is electrically connected to the first signal pattern  111  and the second signal pattern  112 . That is, the main via  120  electrically connects the first signal pattern  111  formed on the top surface of the dielectric  110  and the second signal pattern  112  formed on the bottom surface. In addition, the main via  120  may be formed of a conductive material for electrically connecting the first signal pattern  111  and the second signal pattern  112 . For example, the main via  120  may be formed of a material selected from Au, Ag, Cu, and a combination thereof. 
     The at least one ground via  130  is formed in a circular arc shape at a position spaced apart from the main via  120 . For example, two ground vias  130  are formed at both sides of the main via  120  by using a laser or an etching process. In addition, the ground vias  130  formed at both sides of the main via  120  are not connected to each other so that the first and second signal patterns  111  and  112  electrically connected to the main via  120  can pass between the ground vias  130 . That is, the radian angles of the ground vias  130  are great than 0 but smaller than 7E. In the description of the semiconductor device  100  of the current embodiment, the case where the radian angles of the ground vias  130  are π/2 will be explained. 
     The ground vias  130  include a first ground via  131  and a second ground via  132 . 
     The first ground via  131  is formed at one side of the main via  120 , and the second ground via  132  is at the other side of the main via  120 . The first ground via  131  and the second ground via  132  are symmetric in shape and position with reference to the main via  120 . 
     In the semiconductor device  100  of the current embodiment of the present invention, a certain capacitance value exists between the main via  120  and the ground vias  130 . Also, in the semiconductor device  100  of the current embodiment of the present invention, a certain inductance value exists between the main via  120  and the ground vias  130 . 
     In  FIG. 1A , d denotes the radius of the main via  120 , and D denotes a distance from the center of the main via  120  to the ground via  130 . 
     Referring to  FIG. 2A , a plan view of a semiconductor device is shown according to another embodiment of the present invention, and referring to  FIG. 2B , a sectional view taken along line  2 B- 2 B of  FIG. 2A  is shown. 
     Herein, a semiconductor device  200  shown in  FIGS. 2A and 2B  is similar to the semiconductor device  100  shown in  FIGS. 1A through 1C . Thus, a description will be given on the difference. 
     As shown in  FIGS. 2A and 2B , according to the other embodiment of the present invention, the semiconductor device  200  includes a dielectric  110 , a main via  120 , and ground vias  230 . 
     The ground vias  230  are formed in a circular arc shape and spaced apart from the main via  120 . The ground vias  230  are formed at both sides of the main via  120 . In addition, the ground vias  230  formed at both sides of the main via  120  are not connected to each other such that signal patterns  111  and  112  electrically connected to the main via  120  can pass between the ground vias  230 . That is, the radian angles of the ground vias  230  are greater than 0 but smaller than π. In the description of the semiconductor device  200  of the other embodiment of the present invention, the case where the radian angles of the ground vias  230  are π/4 will be explained. 
     The ground vias  230  include a first ground via  231  and a second ground via  232 . 
     The first ground via  231  is formed at one side of the main via  120 , and the second ground via  232  is formed at the other side of the main via  120 . The first ground via  231  and the second ground via  232  are symmetric in shape and position with respect to the main via  120 . 
     In the semiconductor device  200  of the other embodiment of the present invention, a capacitance value and an inductance value exist between the main via  120  and the ground vias  230 . 
     If the radian angles of the ground vias  230  become smaller from π/2 to π/4, the capacitance value decreases but the inductance value increases between the main via  120  and the ground vias  230 . Of course, it is assumed that d and D are not varied although the radian angles of the ground via  230  are varied. 
     As the radian angles of the ground vias  230  gets smaller, the areas of the ground vias  230  become smaller. 
     Next, insertion loss and reflection loss of a semiconductor device of the present invention will be described in comparison with those of a semiconductor device of the related art. 
     Referring to  FIG. 3 , a plan view of a semiconductor device of the related art is shown. Referring to  FIG. 4 , insertion loss of the semiconductor devices of the present invention and insertion loss of the semiconductor device of the related art are shown in a graph. Referring to  FIG. 5 , reflection loss of the semiconductor devices of the present invention and reflection loss of the semiconductor device of the related are shown in a graph. 
     As illustrated in  FIG. 3 , in a semiconductor device  300  of the related art, ground vias  330  are formed in all directions around a main via  120 . That is, four ground vias  330  are formed. 
     Referring to  FIG. 4 , insertion losses of the semiconductor devices  100  and  200  of the present invention and insertion loss of the related-art semiconductor device  300  are shown by using S-parameter. It can be understood that that the semiconductor devices  100  and  200  of the present invention have lower insertion loss than the related-art semiconductor device  300 . 
     Referring to  FIG. 4 , in the semiconductor device of the embodiment of the present invention, if a signal having a frequency of 0 to 80 GHz is input to the main via  120 , the insertion loss ranges between 0 dB and −0.5 dB. At this time, the radian angles of the ground vias  130  are π/2. 
     Also, in the semiconductor device  200  of the other embodiment of the invention, if a signal having a frequency of 0 to 80 GHz is input to the main via  120 , the insertion loss ranges between 0 dB and −0.5 dB. At this time, the radian angles of the ground vias  230  are n/ 4 . 
     Here, S 21  indicates an insertion loss from a port  1  to a port  2 . For example, if S 21  is −3 dB, it means that the loss of a signal is 3 dB while the signal is transmitted from the port  1  to port  2 , and if S 21  is −10 dB, it means that the loss of a signal is 10 dB while the signal is transmitted from the port  1  to port  2 . Thus, a large value of S 21  (that is, a low absolute value of S 21 ) indicates a low insertion loss. 
     As shown in  FIG. 5 , reflection losses of the semiconductor devices  100  and  200  of the present invention and reflection loss of the related-art semiconductor device  300  are shown by using S-parameter. It can be understood that the semiconductor devices  100  and  200  of the present invention have lower reflection losses than the related-art semiconductor device  300 . 
     Referring to  FIG. 5 , in the semiconductor device  100  of the embodiment of the present invention, when a signal having a frequency of 0 to 80 GHz is input to the main via  120 , the reflection loss is lower than −20 dB. At this time, the radian angles of the ground vias  120  are π/2. Specifically, in the semiconductor device  100  of the embodiment of the present invention, when a signal having a frequency of 10 to 20 GHz is input to the main via  120 , the reflection loss is less than −60 dB. Furthermore, in the semiconductor device  100  of the embodiment of the present invention, when a signal having a frequency of 70 to 80 GHz is input to the main via  120 , the reflection loss ranges between −30 dB and −50 dB. That is, the semiconductor device  100  of the embodiment of the present invention resonates in a frequency range of 10 to 20 GHz or a frequency range of 70 to 80 GHz. That is, the impedance matching of the semiconductor device  100  is good at the frequency range. 
     In the semiconductor device  200  of the other embodiment of the present invention, when a signal having a frequency of 0 to 80 GHz is input to the main via  120 , the reflection loss ranges between about −10 dB and about −30 dB. At this time, the radian angles of the ground vias  230  are π/4. 
     Here, S 21  indicates a reflection loss at the port  1 . The case where S 21  is zero means that all input signal is reflected (total reflection). That is, a low value of S 21  (that is, a large absolute value of S 21 ) indicates low reflection. 
     As described above, the semiconductor device  100  of the embodiment of the invention has the ground vias  130  formed in a circular arc shape and spaced apart from the main via  120 . Thus, the electric characteristics of the semiconductor device  100  such as insertion loss and reflection loss can be improved. 
     In addition, since the semiconductor device  100  of the embodiment of the invention has the ground vias  130  formed in a circular arc shape and spaced apart from the main via  120 , spaces can be efficiently used. 
     Referring to  FIG. 6 , an exemplary method of manufacture for a semiconductor device, such as semiconductor device  100 , is illustrated. The method begins (step  602 ) by forming a dielectric (step  604 ). A main via is formed at the dielectric (step  606 ). A ground via is formed in a circular arc shape and spaced apart from the main via (step  608 ). The method then ends (step  610 ). 
     This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process, may be implemented by one skilled in the art in view of this disclosure.