Abstract:
A simultaneous bi-directional data transferring method includes obtaining a combined signal from a portion of a data line proximate a host device. The combined signal is a signal that combines input and output signals that are being transmitted over the data line. The output signal is a signal transmitted by the host device, and the input signal is a signal transmitted by a remote device. The combined signal is provided to first and second receivers of the host device. A first fixed reference voltage is inputted to the first receiver, and a second fixed reference voltage is inputted to the second receiver. The first and second fixed reference voltages are independent of values of the output signal. A first output receiver signal is outputted from the first receiver using the first fixed reference voltage and the combined signal, and a second output signal is outputted from the second receiver using the second fixed reference voltage and the combined signal. The input signal is reproduced using the first and second output receiver signals. A length of the data line is set to enable the input signal transmitted by the remote device to arrive at an input point of the host device at an integer multiple of a clock cycle.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS  
       [0001]    The present application relates to and claims priority from Japanese Patent Application No. 2001-258202, filed on Aug. 28, 2001. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    The present invention relates to simultaneous bi-directional data transfer over data lines.  
           [0003]    Data transmission and reception techniques enabling simultaneous bi-directional signal transmission and reception over a single data line have heretofore been known, for example, those described in JP-A-98052-1981 and JP-A-186033-1991. A simultaneous bi-directional data transfer technology involves transmitting and receiving data signals simultaneously over the same data line. In JP-A-98052-1981, the output of a transmitter in a transceiver at one station is connected via a resistor to the data line that carries the output signal to another station having a similar transceiver. In addition, the output signal from the transmitter passes through a resistor, is combined with a base voltage, and is input to a differential receiver as a reference voltage. The signal transmitted over the data line is input to a differential receiver. In this previous technique, the differential receiver filters out the output signal generated by the home station and reproduces the input signal received from the remote station.  
           [0004]    In JP-A-186033-1991, after signals transmitted by two stations are combined by signal combining means, signal separation means separates the combined signal into an output signal of the home station and an input signal of the remote station. The home station filters out the output signal and allows the input signal from the remote station to be inputted and processed by the circuits in the home station.  
           [0005]    [0005]FIG. 2 is a block diagram showing the structure of bi-directional data transceiver at each station configured according to conventional techniques. FIG. 3 is a timing chart of signals transmitted and received at an input point  40  (Line_L) of the circuitry shown in FIG.  2 , at where the rising and falling edges of an input signal received from the remote station (remote device) coincide with the corresponding edges of an output signal of the home station (host device). FIG. 4 is a timing chart of the above signals in which delay control is exerted, so that the corresponding edges of input and output signals do not coincide. In FIG. 2, numerals  2   a  and  2   b  denote transmitters, numeral  2   c  denotes a data line, and numerals  2   d  and  2   e  denote differential receivers.  
           [0006]    As used herein, the host device refers to a device including a circuit or component being discussed, and the remote device refers to a device that is transmitting an input signal to the host device. Generally, the description provided herein uses the device on the left side as the reference point. Accordingly, the device on the left side is generally referred to as either “host device” or “home station,” and the device on the right side is generally referred to as either “remote device” or “remote station.” However, these terms are used merely for illustrative purposes and should not be used to limit the scope of the invention.  
           [0007]    The bi-directional data transceiver in FIG. 2 supplies a variable reference voltage to the differential receiver. That is, the reference voltage Vref_L is obtained by combining a constant voltage with the output signal of the transmitter. Therefore, the reference voltage is dependent on the output signal. A transceiver  50  includes a transmitter  2   a  and a differential receiver  2   d.  A transceiver  52  includes a transmitter  2   b  and a differential receiver  2   e.  A data line  2   c  couples the two transceivers  50  and  52 .  
           [0008]    In the transceiver  50 , the transmitter  2   a  outputs send data Sdata 2 _L via a resistor Rtt_L to the data line  2   c.  In the transceiver  52 , the transmitter  2   b  outputs send data Sdata 2 _R via a resistor Rtt_R to the data line  2   c.  The resistances of the resistors Rtt_L and Rtt_R are set equally at characteristic impedance Zo of the data line  2   c.  The send data Sdata 2 _L and Sdata 2 _R output by the transmitters  2   a  and  2   b  are combined on the data line into a signal having three states or voltage levels: H, H/2, L.  
           [0009]    A voltage source Vbb in the transceiver  50  is set at potential that is one half the amplitude level of the output signal of the transmitter  2   a,  namely, H/2. When a “0” signal is output from the transmitter  2   a,  a reference voltage Vref_L that is input to the differential receiver  2   d  will be a quarter of the amplitude of the output signal from the transmitter  2   a,  namely, H/4. When a “1” signal is output, the reference voltage Vref_L will be three quarter, namely 3H/4. As a result, the differential receiver  2   d  compares the reference voltage Vref_L and the triple-valued voltage signal transmitted over the data line  2   c,  cancels only the output signal transmitted by the host device, and reproduces the input data received from the remote device, thereby obtaining the receive data Rdata 2 _L as the input data from the remote device. The transceiver  52  including the transmitter  2   b  and the differential receiver  2   e  at the remote device performs similar operations. The simultaneous bi-directional data transfer technology is also described in U.S. Pat. No. 5,499,269, which is incorporated by reference.  
           [0010]    The transceivers  50  and  52  can implement bi-directional data handling operations without problem if the corresponding edges of the signals transmitted by both host and remote devices do not coincide at the input point  40  or  42 . However, such a situation frequently occurs in data transfer operations as illustrated in FIG. 3 unless specific precautions are taken. The falling and rising edges of the signals with respect to Line_L and Line_R are marked with circles.  
           [0011]    [0011]FIG. 3 illustrates the voltage signal waveforms of the send data Sdata 2 _L of the transmitter  2   a  and the send data Sdata 2 _R of the remote transmitter received respectively at the input points  40  and  42  of the differential receivers  2   d  and  2   e.  FIG. 3 also illustrates the receive data Rdata 2 _L and the Rdata 2 _R at the input points  40  and  42 . In addition, dotted lines denote the reference voltages Vref_L and Vref_R. Assume that the Sdata 2 _R signal output from the transmitter  2   b  of the right-hand station or device  52  is delayed by time “t” as it travels over the data line  2   c  and arrives at the input point  40  of the differential receiver on the left-hand station (host device or home station) when the falling edge of the Sdata 2 _R signal coincides with the falling edge of the Sdata 2 _L signal output from the host device  50 .  
           [0012]    At this time, the fall time of the signal Sdata 2 _R from the transmitter  2   b  of the device  52  becomes slow when it has arrived at the input point  40  of the differential receiver  2   d  of the host device. This falling edge coincides with the falling edge of the signal Sdata 2 _L output from the host device  50 . Consequently, the Sdata 2 _R signal level changes from H to L without transition to ½H level. On the other hand, the reference voltage Vref_L sharply changes from 3H/4 to H/4.  
           [0013]    As a result, the differential receiver  2   d  has difficulty in comparing the reference voltage Vref_L and the triple-valued voltage signal transmitted over the data line  2   c  for a period (indicated by a shaded portion  54 ) because of the difference between the fall time of the reference signal and that of the signal transmitted over the data line. This causes a delay variation, e.g., a temporary signal processing error during when it is difficult to determine the state of the signal. The above phenomenon also occurs at the rising edges of the input and output signals.  
           [0014]    Accordingly, the transceivers  50  and  52  use delay control mechanisms to prevent the corresponding edges of the signals from coinciding. The delay variation resulting from the edge coinciding occurs in the receive circuit because there is a difference between the fall or rise time of the reference voltage signal that is input to the differential receiver and that of the signal transmitted over the data line as described above. Rise or fall time of the input signal at the home station becomes slow as a result of the line resistance and parasitic capacitance of the data line and the input capacitance of the receiver. On the other hand, the reference voltage of the home station does not experience such a delay so it changes fast from H/4 to 3H/4 or 3H/4 to H/4. Thus, when these two signals with different fall or rise time are input to the differential receiver, the receiver cannot compare them properly due to the jitter in the falling and rising edges.  
           [0015]    To avoid the above-described problem, a delay control mechanism is applied to prevent the corresponding edges of signals from coinciding. FIG. 4 shows a timing chart of the signals for which delay control is exerted. As shown in FIG. 4, if coincidence of the corresponding edges of input and output signals is avoided at the input point, a delay variation does not occur in the receive circuit. Thus, the above problem described can be solved. However, a new problem arises.  
           [0016]    As shown in FIG. 4, the timing at which both stations transmit data differs by a half cycle from the timing for shown in FIG. 3, and delay control is exerted to prevent the corresponding edges of input and output signals from coinciding. As a result, the clock timing to receive a signal from the remote device, for example, the rising timing of CLK to transmit in parallel (L−&gt;R) shown in FIG. 4, coincides with the timing to transmit a signal from the host device. When the home station transmits a signal, multiple parallel signals rise or fall simultaneously (since home station has many transceivers), resulting in fluctuation of the current flowing across the line. This current fluctuation produces simultaneous switching output (SSO) noise.  
           [0017]    In other words, if multiple signal bits change in synchronization with the timing of level change of the Sdata 2 _L and Sdata 2 _R, the SSO noise may be added to the signal-receiving clock signals. This noise contributes to the deterioration of the waveform quality of the clock signals. Therefore, the delay control mechanism that does not add the SSO noise to the clock signals is needed when the circuitry shown in FIG. 2 is used.  
         BRIEF SUMMARY OF THE INVENTION  
         [0018]    With rapid popularization of the Internet in recent years, information-processing devices such as computers and network devices such as routers are required to operate at higher speed. To achieve higher speed operation of these devices, means for increasing operating frequencies or extending bit width have been explored. Communication devices, e.g., ASICs and LSIs, used in the information processing devices and network devices are designed to operate faster and faster and provided with increasing numbers of pins.  
           [0019]    However, it is desirable to use less pins in the communication devices for cost reduction. Accordingly, the above-described simultaneous bi-directional device can be applied to reduce the number of data signal pins provided on the semiconductor communication device by half. The problems described above, however, needs to be solved to effectively implement the simultaneous bi-directional data transfer technology.  
           [0020]    In one embodiment, a device configured to provide simultaneous bi-directional data transfer includes a transceiver. The transceiver includes a transmitter to transmit an output signal to a data line, first and second receivers, and a selector. The first receiver has first and second input nodes. The first input node of the first receiver is configured to receive a first fixed reference voltage, and the second input node of the first receiver is configured to receive a combined signal from the data line. The combined signal is a signal resulting from combining the output signal of the transmitter and an input signal from a remote device. The second receiver has first and second input nodes. The first input node of the second receiver is configured to receive a second fixed reference voltage, and the second input node of the second receiver is configured to receive the combined signal from the data line. The selector includes an output node and first, second, and third input nodes. The first input node of the selector is configured to receive a signal output by the first receiver. The second input node of the selector is configured to receive the output signal. The third input node is configured to receive a signal output by the second receiver. The output node of the selector is configured to output the input signal received from the remote device that has been reproduced by the selector.  
           [0021]    In another embodiment, a communication system is configured to provide simultaneous bi-directional data transfer. The system includes a first device comprising n number of transceivers configured to provide simultaneous bi-directional data transfer. A second device comprises n number of transceivers configured to provide simultaneous bi-directional data transfer. N-number of data lines are coupled to the transceiver of the first device with the transceiver of the second device.  
           [0022]    Each one of the n numbers of the transceivers in the first device comprises a transmitter to transmit an output signal to one of the n data lines. A first receiver has first and second input nodes. The first input node of the first receiver is configured to receive a first fixed reference voltage, and the second input node of the first receiver is configured to receive a combined signal from the one of the n data lines. The combined signal is a signal that combines the output signal of the transmitter and an input signal to the transceiver transmitted by a transceiver of the second device. A second receiver has first and second input nodes. The first input node of the second receiver is configured to receive a second fixed reference voltage, and the second input node of the second receiver is configured to receive the combined signal from the data line. A selector includes an output node and first, second, and third input nodes. The first input node of the selector is configured to receive a signal output by the first receiver, the second input node of the selector is configured to receive the output signal, the third input node of the selector is configured to receive a signal output by the second receiver. The selector is configured to reproduce the input signal from the second device and output the reproduced input signal via the output node of the selector.  
           [0023]    In anther embodiment, a communication circuit is configured to provide simultaneous bi-directional data transfer over a data line. The circuit includes a transmitter to transmit an output signal to the data line. A first receiver has first and second input nodes. The first input node of the first receiver is configured to receive a first fixed reference voltage, and the second input node of the first receiver is configured to receive a combined signal from the data line. The combined signal is a signal resulting from combining the output signal of the transmitter and an input signal from a remote device. The combined signal is a triple-valued signal. A second receiver has first and second input nodes. The first input node of the second receiver is configured to receive a second fixed reference voltage, and the second input node of the second receiver is configured to receive the combined signal from the data line. A selector includes an output node and first, second., and third input nodes. The first input node of the selector is configured to receive a signal output by the first receiver. The second input node of the selector is configured to receive the output signal. The third input node of the selector is configured to receive a signal output by the second receiver. The output node of the selector is configured to output a signal representing the input signal received from the remote device.  
           [0024]    In yet another embodiment, a method of transmitting and receiving data simultaneously over a data line connecting first and second stations includes providing the data line with a given length so that a signal transmitted from the first station reaches the second station after a signal delay time that is an integral multiple of a clock cycle of signal transfer.  
           [0025]    In yet another embodiment, a simultaneous bi-directional data transferring method includes obtaining a combined signal from a portion of a data line proximate a host device. The combined signal is a signal that combines input and output signals that are being transmitted over the data line. The output signal is a signal transmitted by the host device and the input signal is a signal transmitted by a remote device. The combined signal is provided to first and second receivers of the host device. A first fixed reference voltage is inputted to the first receiver, and a second fixed reference voltage is inputted to the second receiver. The first and second fixed reference voltages are independent of values of the output signal. A first output receiver signal is outputted from the first receiver using the first fixed reference voltage and the combined signal, and a second output signal is outputted from the second receiver using the second fixed reference voltage and the combined signal. The input signal is reproduced using the first and second output receiver signals. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0026]    [0026]FIG. 1A is a block diagram of a router including a plurality of bi-directional data communication devices according to one embodiment of the present invention.  
         [0027]    [0027]FIG. 1B is a block diagram showing the structure of a system of bi-directional data transmission and reception configured according to one embodiment of the present invention.  
         [0028]    [0028]FIG. 2 is a block diagram showing the structure of conventional bi-directional data TX/RX circuitry.  
         [0029]    [0029]FIG. 3 is a timing chart of signals transmitted and received by the circuitry shown in FIG. 2.  
         [0030]    [0030]FIG. 4 is a timing chart of the signals in which delay control is exerted so that the corresponding edges of send/receive signals do not coincide.  
         [0031]    [0031]FIG. 5 is a block diagram showing the structure of bi-directional data TX/RX circuitry configured according to one embodiment of the present invention.  
         [0032]    [0032]FIG. 6 is a timing chart of signals transmitted and received by the circuitry shown in FIG. 5 for explaining the circuit operation.  
         [0033]    [0033]FIG. 7 is a block diagram showing exemplary circuitry structure for detecting and correcting difference by delay variation between the LSIs, using a typical one of the n bits of data.  
         [0034]    [0034]FIG. 8 is a timing chart of signals transmitted and received by the circuitry shown in FIG. 7 for explaining the circuit operation.  
         [0035]    [0035]FIG. 9 provides a table for explaining what waveform patterns appears according to comparison between the combination of delay variations in the distant LSI and the data line and the delay variation in the home LSI.  
         [0036]    [0036]FIG. 10 is a block diagram showing an exemplary variable delay circuit configuration.  
         [0037]    [0037]FIG. 11 provides a table for explaining the characteristics of the variable delay circuit shown in FIG. 10.  
         [0038]    [0038]FIG. 12 provides a table for explaining exemplary result values of detecting delay variation using the circuitry shown in FIG. 7, which have been stored into the register circuit.  
         [0039]    [0039]FIG. 13 is a timing chart of typical signal waveforms for comparison between previous technique and the preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0040]    [0040]FIG. 1A is illustrates a network system  100  including a plurality of routers  102   a - 102   d  and a network  104 , e.g., the Internet, linking the routers. The routers may have substantially the same or different configurations. The router  102   a  is described herein as a representative router.  
         [0041]    The router  102   a  includes a plurality of routing processors  105  that includes various components used to communicate with other routers  102 , a plurality of crossbar switches  106  that transfer data received from one point to another point (e.g., from one routing processor to another routing processor) in the router, and a routing manager  108  that provides information needed by the switches  106  to transfer data.  
         [0042]    The routing processor  105  includes one or more network interface cards or adaptors (NIFs)  110  that receive and transmit data to and from the network  104 , a forwarding device  112 , and a routing device  114 . The forwarding device  112  forwards data received from the NIF  110  to the crossbar switch  106  and that received from the switch  106  to the NIF  110 . The routing device  114  provides the forwarding device  112  with the information as to where to forward the data. The forwarding and routing devices are generally application specific integrated circuits (ASICs) or large scale integrated circuits (LSIs) that are formed on semiconductor substrates. Detailed description of the router architecture is omitted herein since it is well known by those skilled in the art.  
         [0043]    [0043]FIG. 1B is a block diagram showing the structure of a bi-directional communication system  120  including data interfaces  122  and  124  according to one embodiment of the present invention. The data interfaces  122  and  124  are provided in communication devices, such as, the forwarding device  112  and the routing device  114 . They may also be provided in the crossbar switch  106  and the routing manager. The data interfaces  122  and  124  are also referred to as home and remote interfaces, left and right stations, or home or remote stations.  
         [0044]    In FIG. 1B, numerals  1   a  and  1   a ′ denote transmit flip-flop (FF) circuits, numerals  1   b  and  1   b ′ denote variable delay circuits, a numeral  1   c  denotes a bi-directional TX/RX circuit, numerals  1   d,    1   d ′ and  1   d ″ denote signal lines, a numeral  1   e  denotes a receive flip-flop (FF) circuit, and a numeral  1   f  denotes a register circuit.  
         [0045]    In the illustrative system shown in FIG. 1B, the host and remote devices are provided with n-bit data lines, a line  1   d ′ for clock signals from the left to right stations, and a line  1   d ″ for clock signals from the right to left stations. In one embodiment, the n-bit of data lines represent  160  lines, and the bi-directional communication system  120  is capable of transmitting 560 Mbs. The signal lines  1   d,    1   d ′, and  1   d ″ connecting the left and right stations are configured to be of equal length. The output signal travels through the transmit FF circuit  1   a,  the variable delay circuit  1   b,  and the bi-directional data TX/RX circuit  1   c.  The transmitter of the TX/RX circuit on the host device transmits the output signal over the n-bit data lines  1   d.  The output signal experiences some delay as it travels over the data line  1   d  and arrives at the receive circuit of the bi-directional data TX/RX circuit  1   c  of the remote device. The receive circuit transfers the data to the receive FF circuit  1   e.  The receive FF circuit  1   e  receives the data in synchronization with signal-receiving clock signals traveling in a separate route: from the transmit FF circuit  1   a ′−&gt; variable delay circuit  1   b ′, −&gt; bi-directional data TX/RX circuit  1   c −&gt; data line  1   d ′−&gt; bi-directional data TX/RX circuit  1   c.  The register circuit If stores result output (e.g., see FIG. 12) from the receive circuit in the bi-directional data TX/RX circuit  1   c  for use in providing an appropriate delay time to the output signal. The bi-directional data TX/RX circuit  1   c  receives both input data from the remote device and output data from the host device and filters out the output data to reproduce the input data from the remote device.  
         [0046]    [0046]FIG. 5 is a block diagram showing configurations of transceivers  126  and  128  included in the bi-directional TX/RX circuitry  1   c  of FIG. 1B according to one embodiment of the present invention. The transceivers  126  and  128  are configured to receive and transmit  1  bit of data. As used herein below, the term “transceiver” is generally used to refer one of a plurality of circuits provided within the TX/RX circuitry. Accordingly, the TX/RX circuitry that is configured to receive and transmit n-bits simultaneously includes n number of transceivers. FIG. 6 is a timing chart of signals transmitted and received by the transceivers in FIG. 5. In FIG. 5, numerals  5   a  and  5   b  denote transmitters, numeral  5   c  denotes data line, numerals  5   d  to  5   g  denote differential receivers, numerals  5   h  and  5   i  denote delay adjusting circuits, and numerals  5   j  and  5   k  denote selectors.  
         [0047]    The transmitters  5   a  and  5   b  of the transceivers  126  and  128  have similar configuration as those illustrated in FIG. 2 according to one embodiment of the present invention. However, in the present embodiment, each of the transceivers  126  and  128  have a plurality of differential receivers (numerals  5   d  and  5   e  for the transceivers  126  and numerals  5   f  and  5   g  for the transceivers  128 ) for receiving a triple-valued voltage signal (H, H/2, and L) transmitted over the data line  5   c.  In the transceiver  126  on the left side, reference voltages Vref_L 1  and Vref_L 2  having fixed potentials are supplied to the differential receivers  5   d  and  5   e,  respectively. The reference voltages are directly applied to the differential receivers so they are not affected by the changes in the output signal, contrary to the conventional technology. That is, they are independent of the output signal. The differential receivers  5   d  and  5   e  receive signals having triple values. The output signals of the host device are transferred to the selector circuit  5   j  via the delay adjusting circuit  5   h.  Thereafter, the selector circuit  5   j  filters out the output signal from the triple-valued signal received from the differential receivers  5   d  and  5   e  to obtain the receive data (or input data) Rdata 5 _L. A similar operation is performed on the transceiver  128  on the right side to obtain the receive data Rdata 5 _R.  
         [0048]    The circuit components shown in FIG. 5 that operate as described above transmit and receive signals as illustrated in the time chart in FIG. 6. Because of fixed reference voltage signal input to each differential receiver in the circuitry shown in FIG. 5, the problem due to fall or rise time difference is eliminated and signal jitter does not occur in the differential receivers.  
         [0049]    The transceivers  126  and  128  uses the data line  5   c  that is provided with a specific length, so that the signal delay from the host device to the remote device is such that an output signal arrives at the remote device at a time equal to an integral multiple of a clock cycle. As a result, the SSO noise is prevented from being superimposed to the signal-receiving clock signals. Setting the data line length to make delay equal to an integral multiple of a clock cycle of signal transfer causes the corresponding edges of input and output signals to coincide. However, the signal jitter does not occur in the receive circuits because fixed reference voltages are applied to the differential receivers. Accordingly, the SSO noise generation timing and signal-receiving clock timing can be made asynchronous.  
         [0050]    In another embodiment, the input and output signals from the host and remote devices are transmitted with an offset. However, the delay induced by the data line should be set so that the corresponding edges of an input signal from a remote device and an output signal from a host device coincide at the input point of the differential receiver of the host device. For example, timing at which one device transmits signals is delayed by a half cycle relative to the timing at which the other device transmits signals. Then, the delay of signals traveled over the data line will be an integral multiple of a clock cycle of signal transfer plus 0.5 cycle, and the corresponding edges of the input and output signals coincides at the input point  40  to the receive circuit of the home station.  
         [0051]    As illustrated above, the transceivers  126  and  128  can be used to avoid both delay variation or signal processing errors in the receive circuit resulting from the coincidence of the corresponding edges of input and output signals and the superimposition of the SSO noise to the clock signals.  
         [0052]    A method of correcting delay variation between the communication devices using a variable delay circuit is described below.  
         [0053]    [0053]FIG. 7 depicts a block diagram of components of communication devices involved in detecting and correcting delay variation according to one embodiment of the present invention. The circuits in FIG. 7 are used to handle a single bit so the communication devices have n number of such circuits. FIG. 8 is a timing chart of signals transmitted and received by the circuitry shown in FIG. 7. In FIG. 7, a numeral  7   a  denotes a transmit FF circuit, a numeral  7   b  denotes a variable delay circuit, a numeral  7   c  denotes a transceiver, a numeral  7   d  denotes a data line, a numeral  7   e  denotes a receive FF circuit, and a numeral  7   f  denotes a register circuit. The transmit FF circuit  7   a,  variable delay circuit  7   b,  receive FF circuit  7   e,  and register circuit  7   f  correspond to the transmit FF circuit  1   a,  variable delay circuit  1   b,  receive FF circuit  1   e,  and register circuit  1   f  in FIG. 1, respectively.  
         [0054]    In the circuitry shown in FIG. 7, the variable delay circuits  7   b  at both the left and right stations are provided first with an intermediate delay value. For the transceiver for signal-receiving clock signals (to transmit in parallel), which have similar configuration as the data signal circuitry of the transceiver  7   c,  the variable delay circuits are provided with at an intermediate delay value. The delay values are provided an intermediate value since the delay can be set either longer or shorter, relative to the value.  
         [0055]    Then, the transmit FF circuit  7   a  transmits a string of data of known value (e.g., “01000000” in the time chart in FIG. 8), one of the bits containing a different value than the other bits, as an output data Sdata 7 _L from the left station. The output data Sdata 7 _L is delayed as it travels across the host device and over the data line (e.g., by three clock cycles of signal transfer in the illustrative case shown in FIG. 8) and arrives at an input point Line_R of the differential receiver of the remote device. The remote device transmits data Sdata 7 _R to the host device, delayed by three cycles relative to the send data transmission from the left station, so that the data Sdata 7 _R coincides with the signal from the left station. The Sdata 7 _R data has a string bits that are inverse of the bits of Sdata 7 _L, for example, string “11110111” is applied. The first three bits are provided to compensate for the delay.  
         [0056]    As a result, if there is no delay variation in the communication devices and the data line, the data Sdata 7 _L and the data Sdata 7 _R meet at the input point Line_R and the potential at the input point Line_R will be a half the H level of signal (an intermediate value of the triple-valued voltage levels). However, “0” or “1” signals actually appear at the Line_R point, affected by the delay variations in the communication devices and the data line, according to the variation range, as shown in the circle drawn with a dotted line in FIG. 8.  
         [0057]    [0057]FIG. 9 provides a table  140  for explaining what waveform patterns appear according to comparison between the combination of delay variations in the remote device and the data line and the delay variation in the host device. The table in FIG. 9 shows possible voltage signal waveforms that may appear at the input point Line_R and the output points of the differential receivers in FIG. 7. The table also shows a comparison between a combination of delay variations in the host and remote devices and in the data line. A row  142  of the table  140  depicts exemplary waveforms where the delay variation in the left device+ the delay variation in the data line=the delay variation in the right device. A row  144  illustrates exemplary waveforms where the delay variation in the left device+ the delay variation in the data line is greater than the delay variation in the right device. A row  146  illustrates exemplary waveforms where the delay variation in the left device+ the delay variation in the data line is smaller than delay variation in the right device. The values of the Rcv_R 1  and Rcv_R 2  signals shown in the middle column of the table  140  are stored into the register circuit  7   f  and are used for delay control by the variable delay circuit  7   b  when actual data reception is subsequently performed by software.  
         [0058]    [0058]FIG. 10 is a block diagram showing an exemplary configuration of the variable delay circuit  150 . FIG. 11 provides a table for explaining the characteristics of the variable delay circuit shown in FIG. 10. FIG. 12 provides a table for explaining exemplary result values of detecting delay variation using the circuitry shown in FIG. 7, which have been stored into the register circuit. In FIG. 10, numeral  10   a  denotes a buffer and numeral  10   b  denotes a selector.  
         [0059]    The variable delay circuit  150  is comprised of four selectors  10   b  and buffers  10   a  located on the input line to each selector  10   b,  where the selectors and buffers are connected in series. Specifically, one stage, two stages, four stages, and eight stages of buffers  10   a  are connected in series to the input of the first, second, third, and fourth selectors, respectively. Arbitrary delay values are input to the selectors using delay setting pins a, b, c, and d as inputs connected to each selector, thereby obtaining values shown in the table in FIG. 11.  
         [0060]    For example, by assigning values such that a=0, b=1, c=1, d=0, the variable delay circuit shown would provide a delay of four stages of selectors+two stages of buffers+four stages of buffers. Additional selectors may be added to the circuit  150  to provide additional delay time. Storing values into the register circuit  7   f  is performed sequentially by incrementing the set values on the variable delay circuit for signal-receiving clock signals (to transmit in parallel). The values of Rcv_R 1  and Rcv_R 2  are stored into Reg_R 1  and Reg_R 2  respectively. On the host device, a similar operation as described above is performed, and the values of Rcv_L 1  and Rcv_L 2  are stored into Reg_L 1  and Reg_L 2  respectively.  
         [0061]    After a series of operations described above, data is stored into the register circuit as exemplified in the table in FIG. 12. The table shows that difference by delay variation lies in the data in the shaded fields. In this example, the values stored in the registers_R show no difference by delay variation, whereas the values stored in the registers_L show difference by delay variation. This can take place, for example, when the host device has longer delay, the data line has shorter delay, and the remote device has no delay variation. This example indicates that there is a little time margin between data signal level change timing (simultaneous switching timing) and signal-receiving clock timing at the host device. Therefore, the variable delay circuit should be set to shorten the delay in the host device and store the new delay values of the variable delay circuit into the register circuit again.  
         [0062]    The above delay adjustment operation is repeated to provide the registers with the values specified in the right-hand columns of the table shown in FIG. 12, labeled “after delay setting.” Eventually, the values on the variable delay circuit for signal-receiving clock signals are set as specified in the boldly framed fields in the table shown in FIG. 12 (the values balancing the timing margins ahead of and behind clock timing).  
         [0063]    While bit string “01000000” transmitted from the host device and bit string “11110111” transmitted from the remote device were used in this embodiment, other bit strings may be used for purposes of the present embodiment. In the example above, predetermined, known bit strings are used for detecting and correcting delay variation between the communication devices; however, other methods may be used to compensate the delay.  
         [0064]    The system  120  of the present embodiment in FIG. 1 commences actual data transfers after a delay setting have been performed to correct the delay variation between the communication devices. Accordingly, the system  120  can avoid the signal processing errors resulting from the coincidence of the corresponding edges of the input and output signals and the superimposition of the SSO noise to the signal-receiving clock signals, thereby enabling high-speed data communication.  
         [0065]    [0065]FIG. 13 is a timing chart of the signal waveforms comparing the conventional technique and the present embodiment of the present invention. As seen in FIG. 13, in the case of a previous method, a timing margin or window is reduced because of delay variation or skew in the receive circuit due to the coincidence of the corresponding edges of the input and output signals and the superimposition of the SSO noise onto the signal-receiving clock signals. A signal waveform  160  represents a timing chart of a conventional technique, and a signal waveform  162  represents a timing chart of a present embodiment. The signal waveform  160  is provided with signal noise/skew portions  164  that reduce the timing window; however, such a portion is not present in the signal waveform  162  of the present embodiment.  
         [0066]    In the bi-directional TX/RX method of the preferred embodiment of the invention, as described above, the corresponding edges of send/receive signals coincide at the input point to the receive circuit, but this does not cause jitter in the receive circuit. To prevent jitter, a fixed voltage of reference signal is input to the receive circuit and the data line length is set so that an output signal form a communication device arrives at an input point of another communication device at a time equaling an integral multiple of a clock cycle. In one embodiment, the delay difference between the two communications is detected by using the variable delay circuit and receive circuit for clock signals and corrected by using the variable delay circuit for data signals. Furthermore, the delay setting on the variable delay circuit for clock signals is set within time allowed for settling a signal level.  
         [0067]    The above detailed descriptions are provided to illustrate specific embodiments of the present invention and are not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. Accordingly, the present invention is defined by the appended claims.