Abstract:
An analogue amplifier with multiplexing capability, without the need to incorporate a multiplexor, comprising an input port, a test input port, an output port, a control input to switch the amplifier between a normal amplifying mode and a test mode, wherein a analogue signal introduced to the input port is amplified to the output port in normal mode, and a test signal on the test port is routed to the output port when the amplifier is in test mode.

Description:
FIELD OF THE INVENTION 
   The invention refers to an analogue amplifier to increase circuit testability by featuring additional multiplexing capability. 
   DESCRIPTION OF PRIOR ART 
   Any procedure carried out upon an integrated circuit intended to establish its quality, performance or reliability is commonly called testing. 
   Testing can be carried out at different stages during the development of an integrated circuit; different procedures are followed, according to particular goals and circuit type, for each development stage. 
   The degree to which an integrated circuit facilitates the establishment of test criteria and the performance of tests to determine whether those criteria have been met is commonly referred as testability. 
   According to existing literature, integrated circuits testability can be quantified by means of existing capacity to control and or to observe voltages on relevant nodes in the integrated circuit. These magnitudes are commonly referred as controllability and observability. 
   The twin requirements of high precision and accuracy in signal measurement are superimposed to those basic requirements of controllability and observability to establish proper test criteria for modern high-speed communication circuits. On the other hand, new technologies make more and more defects to be non-visible, new failure mechanisms emerge and a relevant number of circuit features are unsimulatable. 
   As a consequence, test cost and complexity increases, but also a higher risk exist to produce delays in bringing products to market or just to suffer from yield detractors that lead to higher manufacturing cost. 
   Setting up design procedures that include some constrains to increase circuit testability is a common approach to address that problem. 
   Testability can be improved either by increasing the controllability or the observability of some internal nodes. Identifying a testability issue, and therefore choosing proper nodes upon which to act in order to improve their observability or their controllability is most of the times an ad hoc issue. 
   Conventional approach to raise up internal nodes controllability or observability uses multiplexors to provide alternative signal paths. However, because of the ad-hoc nature of the task, top level floor plan layout constrains may lead to situations where it is not possible to include new multiplexor blocks in the original design without severe impact upon schedule because of the re-design effort due. 
     FIG. 1  shows a not accessible node in the signal path which is driven by an analogue amplifier. To test such a not accessible node a design for test solution according to the state of the art is shown in  FIG. 2 . For access to the node a multiplexor is provided so that a test signal can be applied directly to the node (e.g. from an external signal generator). The multiplexor is controlled by a mode control signal which switches between a test signal T and the amplified normal signals S of the signal path. All signals are differential signals. 
   The drawback of a multiplexor-based solution is that the load capacitance is increased. Further providing a multiplexor increases the necessary area on the chip such increasing production costs. A further drawback is that because of the additional multiplexor the power consumption is increased. 
   SUMMARY OF THE INVENTION 
   Accordingly it is the object of the present invention to provide means which allow a better testability by increasing internal controllability. 
   Further advantages of the present invention are that the redesign effort is minimal, that the silicon area overhead is minimal and that the increase of the power supply current consumption is minimal. 
   The basic idea of the present invention is that in the main signal propagation path of analogue integrated circuits a number of amplifiers are provided to drive proper internal nodes in order and to guarantee the required signal to noise ratio. Whenever a controllability issue is detected the design of some amplifier is modified to include multiplexing capabilities that allow injecting test signals within the main signal propagation path with minimal redesign effort and minimal impact upon normal operation mode of the required amplification function. 
   In accordance with one aspect, the invention provides an analogue amplifier with multiplexing capability comprising an input port, a test input port, an output port, a control input to switch the amplifier between a normal amplifying mode and a test mode, wherein a analogue signal introduced to the input port is amplified to the output port in normal mode, and a test signal on the test port is routed to the output port when the amplifier is in test mode. 
   The test signal is generated in a first embodiment by a built in test pattern generator. 
   The test signal is applied in an alternative embodiment via a pad from an external test pattern generator. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows the signal path in an analogue circuit according to the state of the art; 
       FIG. 2  shows a conventional approach to increase the controllability of an internal node non accessible from any primary input/output of the circuit under test. 
       FIG. 3  shows a pll circuit with added multiplexor according to the state of the art to increase controllability by bypassing the amplified VCO output. 
       FIG. 4  shows a fully differential amplifier, tail current and bias generation according to the state of the art; 
       FIG. 5  shows an arrangement comprising an amplifier according to the present invention in order to increase the controllability of the circuit node driven by said amplifier; 
       FIG. 6  shows a preferred embodiment of the analogue amplifier according to the present invention; 
       FIG. 7   b  shows a differential output voltage from an amplifier according to the state of the art as shown in  FIG. 4  and  FIG. 7   a  shows a differential output voltage from an ADfT-analogue amplifier according to the present invention as shown in  FIG. 6 ; 
       FIG. 8  shows the spectral content of the output voltages of a conventional amplifier and of the analogue amplifier according to the present invention; 
       FIG. 9  shows noise figure curves of a conventional amplifier and of the analogue amplifier according to the present invention; 
       FIG. 10  shows the 1 dB compression point of the conventional amplifier according to the state of the art; 
       FIG. 11  shows the 1 dB compression point of the analogue amplifier according to the present invention; 
       FIG. 12  shows the IP3 (3 rd  order intersection point) for the conventional amplifier; 
       FIG. 13  shows the IP3 for the amplifier according to the present invention. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3  shows a conventional approach for testing a phase locked loop, (pLL), circuit within mixed signal circuits. A phase locked loop is a system with induced feedback to maintain an output signal in a specific phase relationship with a reference signal. The pll-circuit shown in  FIG. 3  comprises of phase frequency detector PFD controlling a charge pump CP which supplies a deviation signal to the low pass filter LP. The filtered signal is supplied to a voltage controlled oscillator VCO. The voltage controlled oscillator VCO is a circuit that produces an AC-output signal whose frequency is proportional to the input control voltage. The VCO output signal is amplified by a conventional amplifier as shown in  FIG. 4 . For test purposes a multiplexor is provided at the output of the amplifier in the conventional approach as shown in  FIG. 3 . In the feedback loop a division circuit is provided which produces an output signal whose frequency is an integer division of the input signal frequency. The VCO signal is fed back within the pLL-circuit through a high speed 1/N frequency divider. The proper operation of these frequency divider is essential to guarantee a good pLL-performance. 
   By providing a multiplexor to the output of amplifier A the load capacitance, the area overhead and the power supply consumption are increased. 
     FIG. 4  shows a conventional state of the art differential amplifier A. The amplifier A is connected to a biasing circuit. The conventional amplifier A as shown in  FIG. 4  comprises two input terminals and two output terminals. The input terminals are connected to the gate terminals of amplifying MOS-transistors T a . The source nodes of the amplifying transistors T a  are connected at a common node to a tail current sink implemented by transistor T b  having a gate which is biased by a reference voltage. The drain terminals of the amplifying transistors T a  are connected via resistors to a positive supply voltage VDD. 
   According to the present invention the design of the conventional amplifier A as drawn in  FIG. 4  is modified to increase the controllability of an internal node driven by said amplifier. Thus the testability of the circuit under test including said amplifier is increased too. 
     FIG. 5  shows a block diagram of an analogue amplifier  1  according to the present invention. The analogue amplifier  1  according to the present invention as shown in  FIG. 5  can be switched via a control mode signal between a first normal amplifying mode and a second test mode. A control mode signal is used to switch between both modes. The signal generator can be located externally or be built in. 
   The function of the amplifier  1  in the normal mode can be described as:
 
 Z ( S,T )= K   1   ×S+K   2   ×T 
 
wherein S is the signal of the signal path,
     T is the test signal and   K 1 , K 2  are constants.   

   Since the function of the conventional amplifier to be modified can be described as:
 
 Z ( S )= K   1   ×S 
 
the first constant K 1  of the modified amplifier according to the invention is as close as possible to the original amplifying constant K 1  of the conventional amplifier.
 
   In the normal test node the constant K 2  of the analogue amplifier  1  according to the present invention is as small as possible (K 2 →0). 
   When the analogue amplifier  1  according to the present invention is switched to the test mode its operation can be described as:
 
 Z ( S,T )= K   3   ×S+K   4   ×T 
 
   In an ideal implementation of the differential amplifier  1  according to the present invention, the constant K 3  is zero to isolate the signal S of the signal path from the injected test signal T. The constant K 4  is close to or lower than one in an ideal implementation (K 3 =0; K 4 ≦1). 
     FIG. 6  shows a circuit diagram of a preferred embodiment of a differential analogue amplifier  1  according to the present invention. The analogue amplifier  1  is fully differential. 
   The differential analogue amplifier  1  comprises an input port  2 - 1 ,  2 - 2  for receiving an analogue signal S. The amplifier  1  further comprises a test input port  3 - 1 ,  3 - 2  for receiving a test signal T. Further a control input port  4  is provided for receiving a test control signal switching the amplifier  1  between a normal amplifying mode and a test mode. In the normal amplifying mode the amplifier  1  as shown in  FIG. 6  amplifies the analogue signal S and transmits the amplified signal via an output port  5 - 1 ,  5 - 2  to an internal node within the integrated circuit. In the test mode the test signal T is transmitted to that internal node. 
   The amplifier  1  comprises an amplifying transistor  6 - 1 ,  6 - 2  having a gate terminal  7 - 1 ,  7 - 2 , a source terminal  8 - 1 ,  8 - 2  and a drain terminal  9 - 1 ,  9 - 2 . The gate terminals  7 - 1 ,  7 - 2  of the amplifying transistors  6 - 1 ,  6 - 2  are connected via lines  10 - 1 ,  10 - 2  and first switches  11 - 1 ,  11 - 2  to the signal input terminals  2 - 1 ,  2 - 2 . 
   The drain terminals  9 - 1 ,  9 - 2  of the amplifying transistors  6 - 1 ,  6 - 2  are connected via lines  13 - 1 ,  13 - 2  to the output port  5 - 1 ,  5 - 2  of the amplifier  1 . Connected to lines  13 - 1 ,  13 - 2  are resistors  14 - 1 ,  14 - 2 . The source terminals  8 - 1 ,  8 - 2  of the amplifying transistors  6 - 1 ,  6 - 2  are connected via a line  15  to a drain terminal  16  of a tail current sink comprising a transistor  17  having a source terminal  18  connected to a second negative supply voltage V ss . The current tail transistor  17  comprises a gate  20  connected via a line  21  and via a second switch  22  to a biasing reference voltage supplied to a terminal  23  of the amplifier  1 . Line  21  further connects gate  20  of current tail transistor  17  to a drain terminal of a switching transistor  24 .The gate  20  of the tail current transistor  17  can be switched by the third switch  24  to the negative supply voltage V SS . 
   The load devices  14 - 1 ,  14 - 2  connected to the amplifying transistor  6 - 1 ,  6 - 2  are connected via lines  26 - 1 ,  26 - 2  and fourth switches  27 - 1 ,  27 - 2  to a positive supply voltage. The load devices  14 - 1 ,  14 - 2  a further connected via fifth switches  28 - 1 ,  28 - 2  to the test signal input port. All switches  11 - 1 ,  11 - 2 ,  22 ,  24 ,  27 - 1 ,  27 - 2 ,  28 - 1 ,  28 - 2  of the amplifier  1  are controlled by a test control mode signal applied to the amplifier by terminal  4 . Two inverter circuits  29 - 1 ,  29 - 2  invert the test control mode signal, wherein the inverter circuit  29 - 1  supplies the signal not (T-CTRL) to switches  28 - 1 ,  28 - 2 , and to switch  22 , and wherein inverter circuit  29 - 2  supplies the signal T-CTRL to switches  11 - 1 ,  11 - 2 , switch  24  and switches  27 - 1  and  27 - 2 . 
   The following table shows the states of the switches within the amplifier  1  drawn in  FIG. 6  according to the present invention. 
   
     
       
             
             
             
             
           
         
             
                 
                 
             
             
                 
               switch 
               test mode 
               normal mode 
             
             
                 
                 
             
           
           
             
                 
               S 28-1 , S 28-2   
               On 
               Off 
             
             
                 
               S 27-1 , S 27-2   
               Off 
               On 
             
             
                 
               S 11-1 , S 11-2   
               Off 
               On 
             
             
                 
               S 22   
               Off 
               On 
             
             
                 
               S 24   
               On 
               off 
             
             
                 
                 
             
           
        
       
     
   
   In the normal amplifying mode switch  24  and switch  28 - 1 ,  28 - 2  are switched off and switches  27 - 1 ,  27 - 2 ,  11 - 1 ,  11 - 2 ,  22  are switched on. By means of the switch  28 - 1 ,  28 - 2  the test signal is cut off from the output terminal  5  of the amplifier  1 . The gate  7 - 1 ,  7 - 2  of the amplifying transistor  6 - 1 ,  6 - 2  receives the analogue signal via a switch  11 - 11 ,  11 - 2  and transmits the amplified signals to output port  5 - 1 ,  5 - 2  of the amplifier  1 . In the normal amplifying mode the gate  20  of the tail current transistor  17  receives the biasing reference voltage via closed switch  22 . Since switch  27  is also closed in the normal amplifying mode the amplifying transistor  6  receives the positive supply voltage V DD  via the loading resistors  14 - 1 ,  14 - 2 . 
   When switched to the test mode switches  28 - 1  and  28 - 2 , and switch  24  are closed. At the same time switches  27 - 1 ,  27 - 2 ,  11 - 1 ,  11 - 2  and  22  are opened. While switching off switch  27  the amplifying transistor  6  is disconnected from the positive supply voltage V DD  and cut off. By opening switch  11 - 1 ,  11 - 2  no input signal is supplied to the gate  7 - 1 ,  7 - 2  of the amplifying transistor  6 - 1 ,  6 - 2 . By isolating gates of the amplifying transistors  6 - 1 ,  6 - 2  from the input signal via switches  11 - 1 ,  11 - 2  the signal S is isolated from the output port  5 - 1 ,  5 - 2 . This ensures that the test signal T supplied to the output port  5 - 1 ,  5 - 2  via the load resistors  14 - 1 ,  14 - 2  is not affected by spurious signals coming from the input terminals  2 - 1 ,  2 - 2 . 
   By switching off switch  22  the transistor  17  does not get a biasing reference voltage. Furthermore its gate  20  is switched to the negative supply voltage V SS  by closing switch  24 . In this manner the transistor  17  is cut off completely and the tail current going to ground is nullified. The amplifier design as shown in  FIG. 6  focus on the tail current sink and loads of the amplifier  1  which are modified by the switches to reconfigure the operation of the amplifier. The design of a conventional amplifier is modified by adding switches that disconnect the amplifying transistor from the incoming signal and the tail current sink transistor from the bias circuitry. The design is modified in such a way that the injection of the test signal T in the signal path has a minimal impact upon the circuit normal operation. 
     FIGS. 7–12  come from simulation analysis carried out at the operational frequency of 1.6 GHz. 
     FIG. 7   a ,  7   b  show the differential output wave forms of an original differential amplifier as shown in  FIG. 4  in comparison to the differential output of the amplifier  1  according to the present invention as shown in  FIG. 6 . The input signal used is a monotonic sinusoidal at 1,562 GHz. 
     FIG. 8  shows the spectral content of the output voltages of the conventional amplifier (a) shown in  FIG. 4  and the amplifier (b) according to the present invention as shown in  FIG. 6 . 
   The increase of the noise figure at the operation frequency is due mainly to the drop in conversion gain related to the attenuation effect of transistors  11 - 1  and  11 - 2 . The second largest contribution to the relative increase in the noise figure at the operation frequency is coming from transistor switches  27 - 1 ,  27 - 2  accounting to less than a quarter of the contribution of transistor switches  11 - 1 ,  11 - 2 . 
     FIG. 9  shows the plot of noise figures with a measurement mark at a operating frequency (conventional amplifier a; amplifier according to the present invention b). 
     FIGS. 10 to 13  show different plots of measuring inter-modulation distortion products. The performance of the amplifier according to the present invention it is about 1.5 to 2 dBm better than the original amplifier according to the state of the art. 
   Parasitic capacitance to ground together with the on resistance in transistors  11 - 1 ,  11 - 2  implement a low past filter at the inputs  2 - 1 ,  2 - 2  of the differential amplifier in the modified circuit. The attenuation provided by this filter at the operating frequency which accounts for the gain drop depicted in  FIG. 7  is also responsible for the improvement observed in the circuit linearity. Since the filter attenuation reduces the input power to the differential amplifier it behaves better in terms of intermodulation distortion. 
   Area overhead due to the amplifier design according to the invention accounts for about 9% of the original area due to the original amplifier design. This figure expressed in terms of a total pLL-area, where the amplifier is located, represents about only 0.023% since the amplifier itself takes only about 0.25% of the total pLL-area. In the test mode a low impedance propagation path exist between the test port  3 - 1 ,  3 - 2  and the corresponding circuit output nodes  5 - 1 ,  5 - 2 , respectively. 
   Transistors  28 - 1 ,  28 - 2  used to disconnect the test ports  3 - 1 ,  3 - 2  are dimensioned according to the impedance requirements. These elements are placed in series with the loading resistors. 
   According to the present invention a device under test can be reconfigured and its outputs multiplexed to inject test signals. Consequently it is possible to increase the controllability of relevant nodes of the circuit under test, and therefore is testability is also enhanced. 
   The present invention can be adapted to different operating frequencies, ranging from DC to frequencies in the order of tens of GHZ typically used in optical communication circuits. The present invention is applicable to any analogue circuit whose controllability is to be increased. 
   The modification of the design of a conventional amplifier makes possible to inject a test signal (T) with a minimum impact upon the circuit performances. Further the area overhead due to the circuit modification remains below 10% of that of the differential amplifier. 
   While this invention has been described in terms of several preferred embodiments, there are alterations, permutations, and equivalents which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and compositions of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and equivalents as fall within the true spirit and scope of the present invention.