Abstract:
A low voltage folded metal oxide semiconductor field effect transistor (MOSFET) amplifier circuit for use in a ring oscillator. Operation at a reduced minimum power supply voltage is achieved via a circuit topology with selectively coordinated transistor biasing and channel dimensions.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to low voltage metal oxide semiconductor field effect transistor (MOSFET) amplifier circuits, and in particular, to low voltage folded MOSFET amplifier circuits for use in ring oscillators. 
   2. Description of the Related Art 
   Referring to  FIG. 1 , ring oscillators are well known in the art and are used in many applications. In this particular example  10 , three stages A1, A2, A3 of fully differential amplifiers  12  are serially coupled in a loop in a negative feedback configuration. During normal operation, this ring will bias the differential nodes, i.e., the positive Vip and negative Vin input signal nodes and positive Vop and negative Von output signal nodes, to the metastable point at which all node voltages are mutually equal. 
   Referring to  FIG. 2 , a conventional embodiment  12  of the fully differential amplifier circuits  12  used in such a ring oscillator  10  includes P-type MOSFETs P 1   a , P 1   b  and N-type MOSFETs N 1   a , N 1   b  interconnected substantially as shown between a tail current source  22  and the lower power supply rail VSS/GND. The tail current source  22 , in turn, is coupled between the higher power supply rail VDD and the source electrodes of transistors P 1   a  and P 1   b . This tail current source  22  provides a tail current I 1  which is a product of two, a reference current Iref and the sum of unity and a common mode factor Δ, i.e., I 1 =2*Iref*(1+Δ). Lower current sources  24   a ,  24   b  each sink a current I 2  equal to the reference current Iref, while the N-type MOSFETs N 1   a , N 1   b , connected as diodes with their drain and gate electrodes mutually connected, each sink a common mode current I 3 , which is used to maintain proper biasing of the circuit and is equal to the reference current Iref multiplied by the factor Δ, i.e., I 3 =Δ*Iref. 
   As is well known in the art, a typical MOSFET threshold voltage VT is 0.4 volt, while a typical output operating voltage, often referred to as the drain-to-source saturation voltage VDSAT, is 0.2 volt. Accordingly, such a conventional amplifier circuit  12  requires a power supply voltage VDD−VSS equal to 2*VT+3*VDSAT, which is equal to 1.4 volt. While such a minimum power supply voltage requirement is relatively low, as transistor dimensions continue to decrease in an effort to reduce overall integrated circuit sizes and increase circuit densities, power supply voltage decrease as well, thereby making a 1.4 volt minimum power supply voltage begin to look relatively high. Accordingly, it would be desirable to have an amplifier circuit for use in a ring oscillator which is capable of operating at a lower minimum power supply voltage. 
   SUMMARY OF THE INVENTION 
   In accordance with the presently claimed invention, a low voltage folded metal oxide semiconductor field effect transistor (MOSFET) amplifier circuit for use in a ring oscillator is provided. Operation at a reduced minimum power supply voltage is achieved via a circuit topology with selectively coordinated transistor biasing and channel dimensions. 
   In accordance with one embodiment of the presently claimed invention, a low voltage folded MOSFET amplifier circuit includes power supply electrodes and amplifier circuitry. First and second power supply electrodes are to convey a power supply voltage with a minimum magnitude approximately equal to a sum of a transistor threshold voltage and four transistor output saturation voltages. Input amplifier circuitry is coupled between the first and second power supply electrodes and responsive to the minimum power supply voltage magnitude and an input signal by providing an intermediate signal. Output amplifier circuitry is coupled to the input amplifier circuitry and between the first and second power supply electrodes, and responsive to the minimum power supply voltage magnitude, a bias voltage, the input signal and the intermediate signal by providing an output signal. 
   In accordance with another embodiment of the presently claimed invention, a low voltage folded MOSFET amplifier circuit includes: power supply means for providing a power supply voltage with a minimum magnitude approximately equal to a sum of a transistor threshold voltage and four transistor output saturation voltages; input amplifier means for receiving the minimum power supply voltage magnitude and an input signal and in response thereto generating an intermediate signal; and output amplifier means for receiving the minimum power supply voltage magnitude, a bias voltage, the input signal and the intermediate signal and in response thereto generating an output signal. 
   In accordance with still another embodiment of the presently claimed invention, a low voltage folded MOSFET amplifier circuit includes power supply electrodes, current source circuitry and amplifier circuitry. First and second power supply electrodes are to convey a power supply voltage. First current source circuitry is coupled to the first power supply electrode and responsive to the power supply voltage by conveying a first current. Second current source circuitry is coupled to the second power supply electrode and responsive to the power supply voltage by conveying a second current. Input amplifier circuitry is coupled to the first current source circuitry and the second current source circuitry, and responsive to at least a portion of at least one of the first and second currents, and an input signal by providing an intermediate signal. Output amplifier circuitry is coupled to the first power supply electrode, the second current source circuitry and the input amplifier circuitry, and responsive to the power supply voltage, a bias voltage, at least a portion of the second current, the input signal and the intermediate signal by providing an output signal. 
   In accordance with yet another embodiment of the presently claimed invention, a low voltage folded MOSFET amplifier circuit includes: first current source means for receiving a power supply voltage and in response thereto generating a first current; second current source means for receiving the power supply voltage and in response thereto generating a second current; input amplifier means for receiving at least a portion of at least one of the first and second currents, and an input signal, and in response thereto generating an intermediate signal; and output amplifier means for receiving the power supply voltage, a bias voltage, at least a portion of the second current, the input signal and the intermediate signal and in response thereto generating an output signal. 
   In accordance with still yet another embodiment of the presently claimed invention, a low voltage ring oscillator includes power supply electrodes and a plurality of folded MOSFET amplifier circuits. First and second power supply electrodes are to convey a power supply voltage with a minimum magnitude approximately equal to a sum of a transistor threshold voltage and four transistor output saturation voltages. The folded MOSFET amplifier circuits are serially coupled in a loop and coupled between the first and second power supply electrodes, wherein each one of the plurality of folded MOSFET amplifier circuits includes oscillator amplifier circuitry responsive to the minimum power supply voltage magnitude and a respective input signal by providing a respective output signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a functional block diagram of a conventional 3-stage ring oscillator circuit. 
       FIG. 2  is a schematic diagram of a conventional fully differential amplifier circuit for use in a ring oscillator. 
       FIG. 3  is a schematic diagram of a low voltage folded MOSFET amplifier circuit in accordance with one embodiment of the presently claimed invention. 
   

   DETAILED DESCRIPTION 
   The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
   Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. 
   In conformance with the discussion herein, it will be appreciated and understood by one of ordinary skill in the art that a MOSFET amplifier circuit in accordance with the presently claimed invention can be implemented with P-MOSFET circuitry as discussed herein, or alternatively, with N-MOSFET circuitry with appropriate reversals in drain and source terminal connections and power supply voltage polarity as appropriate in accordance with well known conventional circuit design techniques. 
   Referring to  FIG. 3 , a low voltage folded MOSFET amplifier circuit in accordance one embodiment  100  of the presently claimed invention includes P-type MOSFETs P 1   a , P 1   b , P 2   a , P 2   b , P 3   a , P 3   b , N-type MOSFETS N 1   a , N 1   b  and current source circuits  102 ,  104   a ,  104   b , all interconnected substantially as shown. (The current source circuits  102 ,  104   a ,  104   b  are depicted using generic schematic symbols and, as well understood by one of ordinary skill in the art, can be implemented in accordance with well known current source circuit designs.) This circuit  100  can be described as having an input amplifier circuit formed primarily by transistors P 1   a  and P 1   b , and an output amplifier circuit formed primarily by transistors P 2   a , P 2   b , NIa and N 1   b , both of which are driven or biased by current sources  102 ,  104   a  and  104   b  and diode-connected transistors P 3   a  and P 3   b . Input transistors P 1   a  and P 1   b  have channel widths W′ and lengths L′ such that their width-to-length ratio is equal to 16 times that of a selected normalized ratio W/L, i.e., 16*W/L. A tail current I 1  equal to two times a reference current Iref, i.e., I 1 =2*Iref, is provided by current source  102 . 
   Cascode output transistors N 1   a  and N 1   b  have their gate electrodes biased by an external bias voltage Vbias. Output pull-up transistors P 2   a  and P 2   b , with their gate electrodes driven by the input signal phases Vip, Vin, conduct a current I 3  equal to the reference current Iref and have channel dimensions such that their width-to-length ratios are equal to four times the normalized ratio W/L, i.e., 4*W/L. Additional biasing is provided by transistors P 3   a  and P 3   b  whose channel dimensions caused them to have the normalized width-to-length ratio W/L, and which conduct a bias current I 4  equal to the reference current Iref multiplied by the factor Δ, i.e., I 4 =Δ*Iref. Current sources  104   a  and  104   b  each conduct a current I 2  equal to the reference current Iref multiplied by the sum of 2 and the factor Δ, i.e., I 2 =Iref*(2+Δ). The common mode factor Δ is selected, e.g., Δ=0.25, so as to maintain a common mode current for the amplifier circuit  100 . 
   Operation and considerations for design of this amplifier circuit  100  can be described as follows. A primary requirement is to have the tail current source  102  operate in saturation. It is expected that the input transistors P 1   a , P 1   b  will operate with a saturation voltage VDSAT of 0.2 volt, the tail current source  102  will need 0.15 volt to stay in saturation, and the threshold voltage VT for the transistors is 0.4 volt. Symmetric rise and fall times for the input and output signals Vi, Vo will be achieved if the pull-up current and pull-down currents are equal. However, such equality of such currents cannot always be achieved, thereby requiring some additional current for common mode biasing, as discussed above. Accordingly, the pull-up current (=I 1 +I 3 +I 4 ) is designed to be equal to the ideal pull-down current plus the common mode current (=2*I 2 ). 
   As noted above, current I 3  equals the reference current Iref, and the common mode current I 4  through the diode-connected transistors P 3   a , P 3   b  is equal to Δ*Iref. For the example of Δ=0.25, this means that transistors P 2   a  and P 2   b  must have channel dimensions such that their width-to-length ratios are four times larger (i.e., 1/Δ) than those of transistors P 3   a  and P 3   b . With the tail current I 1  equal to 2*Iref, the current through each of transistors P 1   a  and P 1   b  is equal to Iref. Accordingly, if the ratio of the width-to-length ratio of transistors P 1   a  and P 1   b  to the width-to-length ratio of transistors P 2   a  and P 2   b  is set at 4:1, it can be shown (as discussed in more detail below) that the difference in the gate-to-source voltages VGS of these transistors will be equal to 0.2 volt. As a result, the voltage Vtail at the mutually-connected source electrodes of transistors P 1   a  and P 1   b  is equal to VDD-0.2 volt, thereby providing 0.05 volt of headroom for the tail current source  102 . As the oscillator output signals Vop, Von vary differentially, they operate in opposition to keep this voltage Vtail constant. 
   As a result, this amplifier circuit  100  requires a power supply voltage VDD−VSS having a minimum voltage of only VT+4*VDSAT. This minimum power supply voltage value can be found by summing the voltages between power supply rails VDD and VSS through transistors P 3   a  and N 1   a  and current source  104   a  as follows. The voltage across current source  104   a  equals one saturation voltage VDSAT, as does the voltage across transistor N 1   a . For diode-connected transistor P 3   a , its gate-to-source voltage VGS (which is also equal to its drain-to-source voltage VDS) is equal to the sum of one threshold voltage VT and two saturation voltages VDSAT, i.e., VGS=VT+2VDSAT. Hence, the minimum power supply voltage, which is the sum of these voltages, is VDD−VSS=VDSAT+VDSAT+VT+2*VDSAT=VT+4VDSAT. 
   As noted above, in accordance with a well-known circuit design technique (e.g., see U.S. Pat. No. 4,583,037, the disclosure of which is incorporated herein by reference), transistor dimensions can be scaled in proportion to one another to control and maintain their respective inter-electrode voltages. This can be demonstrated in accordance with well-known MOSFET circuit operating characteristics. As is well-known, drain currents ID 1  and ID 2  of transistors T 1  and T 2 , respectively, can be computed based upon the majority carrier mobility u, the gate capacitance per unit area Cox, the channel width W, channel length L, threshold voltage VT, transistor scaling factor N and the respective gate-to-source voltages VGS 1  (transistor T 1 ), VGS 2  (transistor T 2 ), as follows: 
   
     
       
         
           
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   Setting these currents equal to each other (id 1 =id 2 ) produces Equation 3, which can be simplified and reduced as follows, for scaling factors of N=4 and N=9: 
             Equation   ⁢           ⁢   3   ⁢     :     ⁢           ⁢         u   ·   Cox     2     ·       N   ·   W     L       ⁢       (       VGS   1     -   VT     )     2       =           u   ·   Cox     2     ·     W   L       ⁢       (       VGS   2     -   VT     )     2               N ( VGS   1   −VT ) 2 =( VGS   2   −VT ) 2   Equation 4   √{square root over (N)} ( VGS   1   −VT )=( VGS   2   −VT )  Equation 5   VGS   2   =√{square root over (N)} ( VGS   1   −VT )+ VT   Equation 6   VGS   2   −VGS   1   =√{square root over (N)} ( VGS   1   −VT )+ VT−VGS   1   Equation 7   VGS   2   −VGS   1   =√{square root over (N)} ( VGS   1   −VT )−( VGS   1   −VT )  Equation 8   VGS   2   −VGS   1 =( √{square root over (N)} −1)( VGS   1   −VT )  Equation 9 Example:  N= 4 , VGS   2   −VGS   1 =( VGS   1   −VT )= VDSAT   1   Equation 10 Example:  N= 9 , VGS   2   −VGS   1 =2( VGS   1   −VT )=2 VDSAT   1   Equation 11 
   Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.