Abstract:
An exemplary method includes forming a vertical pillar overlying or laterally displaced from a bond pad overlying a semiconductor substrate, and applying a discrete solder sphere in combination with one of a solder paste or flux on a top surface of the pillar, wherein the one of the solder paste or flux is defined by at least one photoresist layer. The method may include applying a solder sphere and/or solder flux in different combinations on top surfaces of different first and second pillars.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation In part of U.S. patent application Ser. No. 12/828,003, filed Jun. 30, 2010, entitled Methods And Structures For A Vertical Pillar Interconnect, which claims the benefit of priority of U.S. Provisional patent application Ser. No. 61/222,839, filed Jul. 2, 2009, the disclosures of which are hereby incorporated by reference in their entirety. 
     
    
     FIELD 
       [0002]    The present disclosure generally relates to a structure and method for semiconductor devices, and more particularly to a structure and method for electronic wafer-level chip-scale packaging and flip-chip packaging and assembly. 
       BACKGROUND 
       [0003]    Copper pillar bumps, which are one type of vertical interconnect technology, can be applied to semiconductor chips or other microelectronic device bond pads via copper pillar bumping technologies that are known to those familiar with the art. The copper pillar bumps are placed on the chips/devices while the chips/devices are still in their wafer form. All solder-based flip-chip and/or chip scale package (CSP) style interconnects (bumps) require suitable under bump metallurgy (UBM) to act as adhesion layers/diffusion barriers between the wafer/substrate metallization and the solder bump itself. Pillar bumps (copper, gold, or other metals/alloys) have the potential to be used as functional UBMs, provided that reliable/manufacturable methods are used to form the solder bumps on wafers. 
         [0004]    A copper pillar bump offers a rigid vertical structure when compared to a typical solder bump or CSP interconnect. In applications where control of the stand-off between two surfaces, such as a device and its associated substrate, is required, the copper pillar bump acts as a fixed standoff to control that distance, while the solder performs the joint connection between the two surfaces. Controlling this stand-off is critical to overall system performance and reliability. Copper pillar bump structures also offer improved thermal transfer and resistivity compared to equivalent flipchip or CSP solder bump stand-offs. Use of preformed solder spheres increases overall solder volume in the joint, thereby enhancing joint connection strength. 
         [0005]    Cu pillar bump structures have the potential to be a cost-effective, reliable interconnect option for certain markets in the microelectronics industry. However, reliable and low cost manufacturable methods are needed for building versatile fixed stand-off bump structures. Most pillar bump manufacturing methods use a photo-definable mask material to electroplate the pillar structure followed by an electroplated solder. Plating the solder is a slow, expensive process that requires considerable process control and strictly limits the solder to a common binary alloy. Typically, electroplating more than a binary solder alloy to form the solder portion of the pillar bump is very difficult to control in a manufacturing environment. In the semiconductor industry however, using various multiple element alloys or alloys doped with trace elements are desirable to improve the reliability of the interconnect. 
       SUMMARY OF THE DISCLOSURE 
       [0006]    The present disclosure provides an enhanced solder based wafer bumping technology with variable height underbump metallizations (UBM), thereby providing a functional vertical interconnect structure that can be used to connect a semiconductor chip or other microelectronic device to a circuit board, or other substrate for use in 2D and 3D packaging solutions. 
         [0007]    An exemplary method in accordance with the present disclosure includes forming a vertical pillar overlying or laterally displaced from, yet electrically connected to, a bond pad overlying a semiconductor substrate, and applying a discrete solder sphere in combination with one of a solder paste or flux on a top surface of the pillar, wherein the one of the solder paste or flux is defined by at least one photoresist layer, or an overlying metal stencil. Preferably the pillar is defined by the at least one photoresist layer. In one embodiment the at least one photoresist layer has a first aperture to define the solder paste or flux, the pillar is defined by a second aperture in an additional photoresist layer. In one embodiment the at least one photoresist layer is formed overlying the additional photoresist layer and the first aperture has a greater lateral dimension than the second aperture. 
         [0008]    Another exemplary embodiment of a method in accordance with the present disclosure includes forming first and second vertical pillars each overlying a respective bond pad, wherein the respective bond pad overlies a semiconductor substrate, forming at least one photoresist layer having a first aperture and a second aperture, applying a solder sphere and solder flux or solder paste on a top surface of each of the first and second pillars, wherein the solder sphere and solder flux or paste on the first pillar is defined by the first aperture and the solder on the second pillar is defined by the second aperture, and performing a reflow to form a first solder cap on the first pillar and a second solder cap on the second pillar, wherein the combined height of the first pillar and first solder cap is greater than the combined height of the second pillar and second solder cap. In one embodiment the at least one photoresist layer is a single photoresist layer or a multi-layer photoresist stack. In one embodiment the combined height of the first pillar and first solder cap is greater than the combined height of the second pillar and second solder cap by at least about 5 microns. 
         [0009]    Still another exemplary embodiment of a method in accordance with the present disclosure includes forming a vertical pillar having a height less than that in an exemplary method, said pillar overlying or laterally displaced from, yet electrically connected to, a bond pad overlying a semiconductor substrate, and applying a solder sphere/flux mixture using printing methods, into an opening defined by at least one photoresist layer. 
         [0010]    Completion of the above referenced embodiments is done by heating of the solder to at or near melting temperatures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    For a more complete understanding of the present disclosure, reference is now made to the following figures: 
           [0012]      FIG. 1  illustrates a cross-sectional view of a portion of a wafer  100  substrate  102  with I/O bond pads  104 . This view also shows the deposited plating seed layer  106  and the dual purpose photoresist masking material  108  following exposure and develop. This forms the necessary apertures  110  for the copper plating, flux dispense, solder paste print and solder sphere placement processes. 
           [0013]      FIG. 2  illustrates the cross-sectional view of the wafer  100  shown in  FIG. 1  following copper plating of the pillar  112  with the upper portion of the aperture  110  which may be reserved for flux  114  deposition. 
           [0014]      FIG. 3  illustrates the cross-sectional view of the wafer  100  shown in  FIG. 2  after the deposition of the flux  114  into the resist apertures  110  and placement of solder spheres  116  upon the flux  114 . This affords the use of multi-element solder alloys with options of various trace elements to improve the reliability of the solder. 
           [0015]      FIG. 4  illustrates the cross-sectional view of the wafer  100  shown in  FIG. 3  following solder reflow where the solder spheres  116  have formed hemisphere like solder bumps on top of the Cu pillars  112 . 
           [0016]      FIG. 5  illustrates the cross-sectional view of the completed wafer  100  following the strip removal of the photoresist material  108  and the etch removal of the non-pillar plated seed layer  106 . 
           [0017]      FIG. 6  illustrates a cross sectional view of a wafer  200  during an alternate process for filling the apertures  210  with flux  214  and preformed solder spheres  216  using stencil printing methods. 
           [0018]      FIG. 7  illustrates deposition of solder flux  214  and scraping of preformed solder spheres  216  into apertures  210  in the photoresist  208  in this alternative. 
           [0019]      FIG. 8  illustrates the wafer  200  shown in  FIGS. 6 and 7  after reflow of the flux and preformed spheres to form hemispherical pillar caps. 
           [0020]      FIG. 9  illustrates the same wafer  200  after resist and seed layer strip operations. 
           [0021]      FIG. 10  illustrates a wafer  300  formed by another alternate process where the apertures  310  may be partially filled with plated Cu, followed by solder paste  314  deposition atop the pillars  312  which may fill the openings, then placement of solder spheres  316  atop the paste  314  to create greater solder volume. 
           [0022]      FIG. 11  illustrates the embodiment shown in  FIG. 10  after reflow, resist and seed layer removal. 
           [0023]      FIG. 12  illustrates a cross-sectional view of an assembled structure including the Cu pillar bumps with a corresponding board or other substrate. 
       
    
    
     DETAILED DESCRIPTION 
       [0024]    The present disclosure provides an enhanced solder based wafer bumping technology with variable height underbump metallizations (UBM), thereby providing a functional vertical interconnect structure that can be used to connect a semiconductor chip or other microelectronic device to a circuit board, or other substrate for use in 2D and 3D packaging solutions. Copper pillar bumps, as one type of vertical interconnect technology, can be applied to semiconductor chips or other microelectronic device bond pads via copper pillar bumping technologies that are known to those familiar with the art. The copper pillar bumps can be placed on the chips/devices while the chips/devices are still in wafer form. All solder based flip chip and/or CSP style interconnects (bumps) require suitable under bump metallurgy (UBM) to act as adhesion layers/diffusion barriers between the wafer/substrate metallization and the solder bump itself. Pillar bumps (copper, gold, Pd or other metals/alloys) have the potential to be used as functional UBMs, provided reliable/manufacturable methods are used to form solder bumps on wafers. 
         [0025]    A reliable and manufacturable method for forming solder caps on vertical pillar structures is disclosed. The method in accordance with this disclosure provides a means to significantly simplify the manufacturing flow and reduce the cost of manufacturing vertical interconnection structures by the use of a dual purpose photoresist process, which serves as a plating mold, solder paste and/or flux vessel, and solder sphere in-situ stencil template. The present disclosure also includes a method of printing various solder pastes atop a vertical pillar structure, and in other embodiments, placement of preformed solder spheres of varying compositions, atop a dispensed flux or paste, followed by a subsequent reflow to form the solder cap. Furthermore, the present disclosure includes formation of capped vertical pillar structures of differing heights and with differing sphere cap compositions. 
         [0026]    The method of using solder pastes and/or preformed solder spheres in accordance with this disclosure may also include using various multiple-element alloys and trace elements within the solder paste and/or spheres that can enhance the reliability or performance of the solder cap. These methods apply to copper pillar bump-like structures and other vertical interconnection schemes of various sizes and shapes including but not limited to the following metals: Copper and its alloys, Gold and its alloys, Aluminum and its alloys, Silver and its alloys, Palladium and its alloys. The pillar may also include a solder wettable cap finish including but not limited to Ni, NiAu, NiPdAu, NiPd, Pd, NiSn. 
         [0027]    These methods can be used to build Cu pillar bump structures positioned atop or laterally displaced from an I/O bond pad, yet maintaining electrical connection. Because the methods described herein employ a printed solder paste and/or preformed solder sphere, an end product can be produced with a much broader range of solder alloys than the existing method of using a plated solder. 
         [0028]    In the method in accordance with this disclosure the solder paste portion of the pillar bump includes but is not limited to the following alloys/metals: SnPb alloys, SnPbCu alloys, SnAgCu alloys, SnNiAgCu alloys, AuSn alloys, AuSi alloys, SnSb alloys, SnSbBi alloys, PbSnSb alloys, PbSnSb alloys, PbIn alloys, PbSnAg alloys, SnAg alloys, PbSb alloys, SnInAg alloys, SnCu alloys, PbAg alloys, SnAs alloys, PbSbGa alloys, SnAs alloys, SnGe alloys, ZnAl alloys, CdAg alloys, GeAl alloys, AuIn alloys, AgAuGe alloys, AlSi alloys, AlSiCu alloys, AgCdZnCu alloys, and AgCuZnSn alloys. This method also can include any solder sintering alloys deposited in the “in situ” aperture such as Ag sintering material. 
         [0029]    Because the method in accordance with this disclosure employs a printed solder paste and/or preformed solder sphere, it offers the option for an end product with various trace elements in the solder including, but not limited to; Bi, Ni, Sb, Fe, Al, Ag, Cu, Sn, In, and Pb. The resulting pillar and solder cap structure using the methods disclosed herein can have a preferred overall height ranging between 5 and 400 microns and a preferred pitch as low as 10 microns. Furthermore, the x and y dimensional limits of the pillars produced using these methods can have pillars as small as Sum and up to 2 mm. 
         [0030]    An exemplary embodiment of a method in accordance with this disclosure for forming solder bumps using solder paste and/or preformed solder spheres or combinations of solder paste and preformed solder spheres on vertical interconnect structures with various iterations proceeds as follows: 
       Without Redistribution: 
       [0031]    Step 1. A seed layer of metal is deposited on a wafer/substrate by a conventional method such as sputtering, evaporation, electroless plating, immersion plating, etc. to provide a continuous seed layer on the wafer/substrate for plating. 
         [0032]    Step 2. A photoresist layer or other resist type material is applied over the entire surface of the wafer/substrate. This can be achieved by dry film lamination, spin or spray coating methods. 
         [0033]    Step 3. Apertures are then formed through the photoresist layer. The photoresist layer is generally defined by UV exposure through an appropriate photomask based on the design, but the creation of the aperture is not limited to UV exposure/develop and might include but is not limited to laser ablation, dry etch, or lift-off processes. 
         [0034]    For alternate configurations of this method, multiple layers of photoresist materials or other resist type materials can be applied to form varied aperture heights and aperture sizes within the same resist stack that can facilitate varied columnar structures and varied solder volumes deposited on top of the columnar structure. 
         [0035]    Step 4. The photoresist layer(s) covering the seed layer is developed, or otherwise opened, forming open “in-situ” apertures for the plating of the pillar or columnar structure and subsequent solder paste printing, flux deposition or preformed solder sphere placement. The overall depth of the “in-situ” apertures can range between 2-200 um. 
         [0036]    Step 5. Pillar structures are preferably electroless or electroplated onto the seed metal layer surface in the apertures formed in the photoresist layer(s). 
         [0037]    Step 6. Solder paste is printed into the “in-situ” apertures in the photoresist stencil with the solder paste covering the top of the copper pillars; alternatively, flux is applied into the “in-situ” apertures in the photoresist stencil, followed by placement of preformed solder spheres using technology known to those skilled in the art. Furthermore, solder flux and preformed solder spheres together may be applied into or atop the “in-situ” apertures. This can result in capped pillars of different heights as may be called for in different applications. An alternate method for depositing preformed spheres uses stencil printing technology to direct the sphere/flux mixture into the designated apertures, as shown in  FIG. 6 . Alternatively, a metal stencil could also be used to further define the area where solder paste or flux can be applied over the pillar bump structure both in and above the “in-situ” photoresist material, or to maintain positional accuracy of the preformed solder spheres prior to reflow. 
         [0038]    Step 7. The wafer or other substrate with printed solder, and/or solder sphere preforms in place is then reflowed and cooled, forming solder caps on top of the copper pillar columns. 
         [0039]    Step 8. The “in-situ” photoresist stencil material is stripped away or otherwise removed. 
         [0040]    Step 9. The un-plated seed layer is selectively etched away leaving behind individual pillars capped with solder. 
         [0041]    Step 10. A second reflow operation may be performed on the wafer or other substrate to optimize the bump shape. Also, a coining or flattening process can be used to further reduce bump to bump resolution beyond that possible with Cu pillar technology developed as part of the prior art. 
       With Redistribution: 
       [0042]    Step 1. A dielectric layer or other resist type material is applied over the entire surface of the wafer/substrate. This can be achieved by dry film lamination, spin or spray coating methods. 
         [0043]    Step 2. Apertures are then formed through the dielectric layer corresponding to bond pad locations, and thus exposing underlying bond pad structures. The dielectric layer is generally defined by UV exposure through an appropriate photomask based on the design, but the creation of the aperture is not limited to UV exposure/develop and might include but is not limited to laser ablation, dry etch, or lift-off processes. 
         [0044]    Step 3. A redistribution layer of metal is formed and patterned on the dielectric layer by either subtractive or removal patterning methods or semi-additive, plating techniques. Conventional methods such as sputtering, evaporation, electroless plating, immersion plating, etc. may be used to provide a continuous layer on the wafer/substrate for plating. 
         [0045]    Step 4. A second dielectric layer is applied over the entire surface of the wafer/substrate. This can be achieved by dry film lamination, spin or spray coating methods. 
         [0046]    Step 5. Apertures are then formed through the dielectric layer, overlying the RDL metallization layer and corresponding to the final pillar bump locations. The dielectric layer is generally defined by UV exposure through an appropriate photomask based on the design, but the creation of the aperture is not limited to UV exposure/develop and might include but is not limited to laser ablation, dry etch, or lift-off processes. 
         [0047]    Step 6. Under bump metallization (UBM) layer/s are deposited via sputtering, evaporation, electroless plating, immersion plating, etc. into the aperture, atop the second dielectric layer. 
         [0048]    Step 7. A photoresist layer is applied over the entire surface of the wafer/substrate. This can be achieved by dry film lamination, spin or spray coating methods. 
         [0049]    For alternate configurations of this method, multiple layers of photoresist materials or other resist type materials can be applied to form varied aperture heights and aperture sizes within the same resist stack that can facilitate varied columnar structures and varied solder volumes deposited on top of the columnar structure. 
         [0050]    Step 8. The photoresist layer(s) covering the dielectric layer is developed, or otherwise opened, forming open “in-situ” apertures for the plating of the pillar or columnar structure and subsequent solder paste printing, flux deposition or preformed solder sphere placement. The overall depth of the “in-situ” apertures can range between 2-200 um. 
         [0051]    Step 9. Pillar structures are preferably electroless or electroplated onto the UBM metal layer surface in the apertures formed in the photoresist layer(s). 
         [0052]    Step 10. Solder paste is printed into the “in-situ” apertures in the photoresist stencil with the solder paste covering the top of the copper pillars after which preformed solder spheres may be placed into the paste; alternatively, flux is applied into the “in-situ” apertures in the photoresist stencil, followed by placement of preformed solder spheres using technology known to those skilled in the art. Furthermore, solder flux and preformed solder spheres together may be applied into or atop the “in-situ” apertures. This can result in capped pillars of different heights as may be called for in different applications. An alternate method for depositing preformed spheres uses stencil printing technology to direct the sphere/flux mixture into the designated apertures, as shown in  FIG. 6 . Alternatively, a metal stencil could also be used to further define the area where solder paste or flux can be applied over the pillar bump structure both in and above the “in-situ” photoresist material, or to maintain positional accuracy of the preformed solder spheres prior to reflow. 
         [0053]    Step 11. The wafer or other substrate with printed solder, and/or solder sphere preforms in place is then reflowed and cooled, forming solder caps on top of the copper pillar columns. 
         [0054]    Step 12. The “in-situ” photoresist stencil material is stripped away or otherwise removed. 
         [0055]    Step 13. The UBM layer is selectively etched away leaving behind individual pillars capped with solder. 
         [0056]    Step 14. A second reflow operation may be performed on the wafer or other substrate to optimize the bump shape. Also, a coining or flattening process can be used to further reduce bump to bump resolution beyond that possible with Cu pillar technology developed as part of the prior art. 
         [0057]    Steps 1-10 and steps 1-14 above are all performed using processing methods and tool sets known to those experienced in the art with photo-imaging, plating, and solder bumping processes. 
         [0058]    One example of the method according to the present disclosure is shown with reference to  FIGS. 1-5 . In  FIG. 1 , a cross sectional view of a portion of a wafer  100  is shown that has a substrate  102  with I/O bond pads  104  thereon. This view also shows the deposited plating seed layer  106  and the dual purpose photoresist masking material  108  following exposure and develop operations. The patterned masking material  108  forms the necessary apertures  110  for the copper plating, flux dispense, solder paste print and solder sphere placement processes that follow. 
         [0059]      FIG. 2  illustrates the cross sectional view of the wafer  100  shown in  FIG. 1  following copper plating of the pillar  112  with the upper portion of the aperture  110 . 
         [0060]    Next, a layer of solder paste or flux  114  is squeegeed into the apertures  110 . Then a solder sphere  116  is placed on the solder paste or flux  114  as is shown in  FIG. 3 . 
         [0061]    Next a reflow operation is performed heating the solder spheres so that they deform plastically as is shown in  FIG. 4  such that they form generally hemispherical caps on top of the pillars  112 . Following the reflow operation, the photoresist material  108  is removed and the seed layer  106  is etched to remove the exposed seed layer  106  adjacent the pillars  112 , leaving the capped pillars  112  as shown in  FIG. 5 . 
         [0062]    An alternate configuration is shown in  FIGS. 6-9  formed utilizing the method in accordance with the present disclosure.  FIG. 6  illustrates a cross sectional view of a wafer  200  during this alternate process for filling the apertures  210  with flux  214  and solder spheres  216  using stencil printing methods. The wafer  200  again has a substrate  202  and bond pads  204  overlying the substrate  102 . A seed layer  206  overlies the bond pads  104 . In this embodiment, deposition of the plated copper  212  is only done to a lesser depth than in the embodiment illustrated in  FIGS. 1-5 .  FIG. 7 , in this second embodiment, shows deposition of solder flux  214  and solder spheres  216  together into the spaces above the copper pillars  212  below the upper edges of the photoresist  208 . A squeegee  218  is used to push the spheres  216  in direction  220  into the recessed spaces above the pillars  212 . 
         [0063]      FIG. 8  shows the wafer  200  following a reflow operation to form the solder spheres  216  into hemispherical caps on the pillars  212 . Then, as is shown in  FIG. 9 , the photoresist  208  is removed and the seed layer  206  etched away as was done previously with reference to  FIGS. 1-5 . 
         [0064]      FIGS. 10 and 11  illustrate another alternate process in which the apertures are filled with plated copper, followed by solder paste deposition, then placement of solder spheres atop the paste to create greater solder cap volume. As is shown in  FIG. 10 , wafer  300  has, similar to that shown in  FIGS. 1-9 , a substrate  302 , bond pads  304 , seed layer  306 , and patterned photoresist  308  defining apertures  310  into which copper pillars  312  are plated so as to fill a portion of the apertures  310 . Then a solder paste  314  that may include a flux material, is applied into the apertures  310 , or into apertures in an overlying metal stencil (not shown). Solder spheres  316  are then placed over the apertures  310 , and a reflow operation performed. After the photoresist  308  is removed and the seed layer  306  etched, the resultant capped pillars remain standing as shown in  FIG. 11 . In this particular alternative, note that the height of the solder portion is much higher than in the embodiment shown in  FIG. 9 . These alternatives may be interspersed such that variable height pillars  212 ,  312  may be incorporated on a single wafer depending on the completed configuration desired. 
         [0065]    Finally, a cross sectional view of a completely assembled package  400  is shown prepared in accordance with the method set forth above. 
         [0066]    The method in accordance with the present disclosure may also be utilized with multiple layers of photoresist and or other resist type materials to create variations in the columnar structure and thereby in the solder paste volume and/or solder sphere diameter in order to achieve the desired pillar and solder dimensional parameters. Additionally, although the embodiments shown in  FIGS. 1-12  illustrate pillar and photoresist heights and diameters that are the same, it is to be understood that they may be of different heights and diameters. Additionally, multiple photoresists  308  may be applied with different heights and diameters such that the pillars formed thereby will have different shapes than straight sidewalls as is shown. The exemplification set out herein illustrates particular embodiments, and such exemplification is not intended to be construed as limiting in any manner.