Abstract:
A sample-and-hold circuit includes a transconductance cell and an inductive-capacitive (L-C) resonator circuit acting as a bandpass filter.

Description:
TECHNICAL FIELD 
     This disclosure relates to sample-and-hold circuits and more particularly to a new concept for a bandpass sample-and-hold circuit utilizing a transconductance cell and an inductor. 
     BACKGROUND 
     Bandpass sample-and-hold circuits are modern low-cost, high-performance solutions for directly sampling an RF signal and are often found in the front end of direct-sampling RF analog-to-digital converters (ADCs) to hold the signal steady during the conversion period for the ADC to process. Thus, many communication systems employ such circuits, including but not limited to commercial wireless communication systems. 
     To directly digitize a high-frequency RF signal, one solution is to use high-speed sample-and-hold circuits, which are able to track the fast-changing signal during the track period as well as to hold the sampled signal long enough during the hold period. Conventional sample-and-hold circuits are wideband sample-and-hold circuits that pass through all the signals, from DC all the way to the frequencies of interest. They not only collect all out-of-band interference but also self-generated circuit noise (including, e.g., white noise, flicker noise, shot noise, etc). When the frequencies of interest are high, the self-generated circuit noise will adversely impact the signal-to-noise ratio (SNR) of the circuit and thus limit its sample-and-hold resolution. Furthermore, to maintain the voltage gain and linearity for wide bandwidths, typical sample-and-hold circuits have to use significant power. 
       FIG. 1  is a schematic depiction of a typical sample-and-hold (also referred to in the art as track-and-hold) circuit architecture  100  commonly used in high-speed, wide-bandwidth applications that employs transconductance cells (or Gm-Cells)  110  that converts an input voltage to current. The skilled reader will recognize this as an open-loop track-and-hold circuit with hold signal feedback to isolate the input signal feed-through. The input signal or input voltage V in  is first converted into current I in  by a first transconductance cell  110 , which is then fed through a first switch  112  and converted back to a voltage V m  by a resistor  114  having a resistance value of R. The converted voltage V m  is sampled by a second switch  116  and accumulated by a capacitor  118  having a capacitance value of C. The signal accumulated in capacitor  118  is buffered by a unity-gain amplifier/buffer  120  and subsequently fed as output voltage V out . A second Gm cell  130  is connected between the buffered output of the buffer  120  and the first switch  112  to stabilize the accumulated signal during the circuit&#39;s HOLD mode (i.e. while the converted voltage V m  is not being accumulated). The use of the second Gm cell  130  also decouples the leak-through noise from the input caused by the parasitic capacitance present in the second switch  116 . 
     In this circuit architecture the voltage gain of the circuit is defined by the transconductance gain of the first Gm cell  110  and the resistance value R of the resistor  114 . The bandwidth is determined by R, C and the bias current of the second switch  116 . To present a wider operational bandwidth, R and C need to be reduced. However, a small R value will produce a small converted voltage V m  and therefore will necessitate a higher transconductance gain from the first Gm cell  110  to compensate, which in turn will lead to higher overall power consumption by the circuit. On the other hand, a low value of C will cause more KT/C switching noise and also a worse droop rate because the signal V m  cannot be held steady, thereby causing error. Conversely, a higher value of C will require a higher bias current for the second switch  116  to charge, to discharge, and to minimize signal distortion. Thus, to sample and hold very high frequency, this circuit architecture requires comparatively large amounts of power. 
     In addition to less-than-optimal power consumption, this wideband sample-and-hold circuit architecture also presents excessive noise collection because it collects all out-of-band interference along with the self-generated circuit noise (white, flicker, shot noise, etc), leading to the reduced SNR performance and attendant limited resolution previously mentioned. 
     What is now needed is an improved archotecture for wideband sample-and-hold circuits that offer improved SNR performance and higher sampling resolution. The embodiments of the present disclosure answer these and other needs. 
     SUMMARY 
     In a first embodiment disclosed herein a circuit comprises a transconductance cell disposed to receive an input signal and generate a corresponding output signal; an inductive-capacitive (L-C) resonator circuit connected to the transconductance cell to sample the output signal of the transconductance cell and attenuate predetermined frequencies in the sampled signal; and an amplifier connected to buffer the sampled signal and provide the buffered sampled signal at an output. 
     In another embodiment disclosed herein, a method of sampling a signal comprises disposing a transconductance cell to receive an input signal and generate a corresponding output signal; connecting an inductive-capacitive (L-C) resonator circuit to the transconductance cell to sample the output signal of the transconductance cell and attenuate predetermined frequencies in the sampled signal; and connecting an amplifier to buffer the sampled signal and provide the buffered sampled signal at an output. 
     In a further embodiment disclosed herein, the resonator circuit comprises a capacitor and an inductor connected in parallel with the capacitor between the output of the transconductance cell and ground. 
     In still further embodiments disclosed herein, the resonator circuit comprises a sampling switch connected to selectively feed the transconductance cell output signal to the resonator or to ground. 
     These and other features and advantages will become further apparent from the detailed description and accompanying figures that follow. In the figures and description, numerals indicate the various features, like numerals referring to like features throughout both the drawings and the description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic depiction of a typical sample-and-hold (also referred to in the art as track-and-hold) circuit architecture as known in the art; and 
         FIG. 2  is schematic depiction of a novel sample-and-hold circuit architecture according to the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     An embodiment of sample-and-hold circuit as disclosed herein uses an inductor-capacitor (L-C) resonator to attenuate the out-of-band signal and uses the associated capacitor to hold the input information for the sample-and-hold circuit. The bandpass property of the L-C resonator attenuates the out-of-band interference as well as the self-generated circuit noise (white, flicker, shot noise, etc), which effectively improves the signal-to-noise ratio (SNR) of the sample-and-hold circuit. The L-C resonator also offers improved voltage gain for the input signal, which further improves the signal-to-noise ratio and reduces overall circuit power consumption. 
     With reference to  FIG. 2 , an embodiment of a bandpass sample-and-hold circuit  200  according to the present disclosure includes a Gm cell  210  that receives the continuous-time input signal to be sampled and converts it from voltage V in  into current I in , which is then fed to an inductor  212  having an inductance value of L. During the sample mode of the circuit (illustrated in  FIG. 2 ), the inductor  212  is shorted through a switch  214  to a capacitor  216  having a capacitance value of C. The L-C combination of the inductor  212  and the capacitor  216  forms a L-C resonator that, when connected in this configuration, functions as a bandpass filter and attenuates out-of-band signals and offers voltage gain to the in-band signals. 
     As shown in  FIG. 2 , during the hold cycle the switch  214  shorts the inductor  212  to ground, and thereby resets the inductor to prepare it for the next sample cycle. During the hold cycle (that is, while the switch  214  is disconnected from the capacitor  216  and is connected to ground) the sampled signal is accumulated by the capacitor  216 . The accumulated signal is then buffered by a unity-gain amplifier/buffer  220  to drive the next stage  230 , which is typically another sample-and-hold circuit that has a smaller operating bandwidth. A common clock signal preferably drives both circuit  200  by actuating the switch  214  as well as the second stage  230 . 
     In circuit  200 , the voltage gain is defined by the transconductance gain of Gm cell  210  and the impedance L of the L-C resonator (functioning as bandpass filter) combination of the inductor  212  and the capacitor  216 . In the pass band of this L-C bandpass filter, the impedance L is very high as it depends on the Q-factor of the inductor. Therefore, sample-and-hold circuit  200  can achieve high voltage gain without the use of a high-gain Gm cell. This property relaxes the linearity and power consumption requirements for the input Gm cell and leads to reduced power consumption and sampled signal distortion. The holding capacitor  216  for the circuit may be larger to reduce the KT/C thermal noise and the droop rate by reducing the inductance L required of the inductor  212 . 
     The L-C bandpass filter may be designed to only pass the frequency band of interest and reject the out-of-band interference and circuit noise. Because the capacitance C of the capacitor  216  may be larger, the bandpass filter my be designed to offer reduced droop rate and hence may employ a slower (narrower bandwidth) output buffer  220  to buffer the sample-and-hold output. Use of such a narrower bandwidth output buffer  220  will serve to further reduce the circuit noise and improve the signal-to-noise ratio of the circuit  200 . 
     Having now described the invention in accordance with the requirements of the patent statutes, those skilled in this art will understand how to make changes and modifications to the present invention to meet their specific requirements or conditions. Such changes and modifications may be made without departing from the scope and spirit of the invention as disclosed herein. 
     The foregoing Detailed Description of exemplary and preferred embodiments is presented for purposes of illustration and disclosure in accordance with the requirements of the law. It is not intended to be exhaustive nor to limit the invention to the precise form(s) described, but only to enable others skilled in the art to understand how the invention may be suited for a particular use or implementation. The possibility of modifications and variations will be apparent to practitioners skilled in the art. No limitation is intended by the description of exemplary embodiments which may have included tolerances, feature dimensions, specific operating conditions, engineering specifications, or the like, and which may vary between implementations or with changes to the state of the art, and no limitation should be implied therefrom. Applicant has made this disclosure with respect to the current state of the art, but also contemplates advancements and that adaptations in the future may take into consideration of those advancements, namely in accordance with the then current state of the art. It is intended that the scope of the invention be defined by the Claims as written and equivalents as applicable. Reference to a claim element in the singular is not intended to mean “one and only one” unless explicitly so stated. Moreover, no element, component, nor method or process step in this disclosure is intended to be dedicated to the public regardless of whether the element, component, or step is explicitly recited in the Claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for . . . ” and no method or process step herein is to be construed under those provisions unless the step, or steps, are expressly recited using the phrase “comprising the step(s) of . . . ”