Abstract:
The present invention relates to a semiconductor memory circuit enabling stable data transmission in a high frequency operation and a data processing system using the same. The data processing system includes a semiconductor memory circuit configured to output data, corresponding to a read command, in response to an external strobe signal, and a controller configured to provide the semiconductor memory circuit with the read command and the strobe signal related to the read command.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2012-0035019, filed on Apr. 4, 2012, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates to a semiconductor circuit, and more particularly, to a semiconductor memory circuit and a data processing system using the same. 
         [0004]    2. Related Art 
         [0005]    A data processing system may include semiconductor integrated circuits, such as a semiconductor memory circuit and a controller, e.g. a CPU or a GPU. 
         [0006]    When a read command is received from the controller, the semiconductor memory circuit outputs data stored therein to the controller with the assistance of an internal clock signal. 
         [0007]    When a write command is received, the semiconductor memory circuit writes data, provided from the controller, into an internal memory block in response to a strobe signal provided by the controller. 
         [0008]    Electronic devices, such as mobile phones and computers, require high speed operation, and thus, higher operating frequencies. 
         [0009]    Accordingly, it is necessary for a semiconductor memory circuit to sufficiently secure a timing margin in a data transfer process and to maintain stable performance even during a high speed operation. 
       SUMMARY 
       [0010]    A semiconductor memory circuit enabling stable data transmission in a high frequency operation and a data processing system using the same are described herein. 
         [0011]    In an embodiment of the present invention, a data processing system includes a semiconductor memory circuit configured to output data, corresponding to a read command, in is response to an external strobe signal, and a controller configured to provide the semiconductor memory circuit with the read command and the strobe signal related to the read command. 
         [0012]    In an embodiment of the present invention, a semiconductor memory circuit includes a command decoder configured to generate a read command by decoding a command signal, a data path activation unit configured to generate a selection signal in response to an address signal and the read command, a memory block configured to provide a signal line with data corresponding to the selection signal, an output latch unit configured to output the data of the signal line in response to data output enable signals, and an output timing adjustment unit configured to both adjust the timing of the read command received based on a clock signal and to generate the data output enable signals used for a strobe signal based on the adjusted timing. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0014]      FIG. 1  is a block diagram showing the construction of a data processing system  1  according to an embodiment of the present invention, 
           [0015]      FIG. 2  is a circuit diagram showing the construction of an output latch unit  150  of  FIG. 1 , 
           [0016]      FIG. 3  is a block diagram showing the construction of a data is processing system  2  according to an embodiment of the present invention, 
           [0017]      FIG. 4  is a circuit diagram showing the construction of a timing clock generator  220  of  FIG. 3 , 
           [0018]      FIGS. 5 and 6  are timing diagrams illustrating the operation of a timing clock generator  220  of  FIG. 4 , 
           [0019]      FIG. 7  is a circuit diagram showing the construction of a command register  230  of  FIG. 3 , 
           [0020]      FIG. 8  is a timing diagram illustrating a read operation according to an embodiment of the present invention, and 
           [0021]      FIG. 9  is a block diagram showing the construction of a data processing system  3  according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0022]    Hereinafter, a semiconductor memory circuit and a data processing system using the same according to the present invention will be described below with reference to the accompanying drawings through various embodiments. 
         [0023]      FIG. 1  is a block diagram showing the construction of a data processing system  1  according to an embodiment of the present invention. 
         [0024]    As shown in  FIG. 1 , the data processing system  1  according to the embodiment of the present invention may include a controller  101  and a semiconductor memory circuit  102 . 
         [0025]    The controller  101  may provide an address signal ADD, a command signal CMD, a clock signal CLK, and a strobe signal RWDQSQ to the semiconductor memory circuit  102 . 
         [0026]    The controller  101  may provide the strobe signal RWDQSQ to the semiconductor memory circuit  102  when a read or write command is received. 
         [0027]    The controller  101  may include a CPU or a GPU. 
         [0028]    The semiconductor memory circuit  102  may perform a read operation in response to the strobe signal RWDQSQ provided from the outside, such as from the controller  101 . 
         [0029]    If the command signal CMD defines a read command, the semiconductor memory circuit  102  may output data, corresponding to the address signal ADD, to the outside, such as to the controller  101 , in response to the strobe signal RWDQSQ. 
         [0030]    The semiconductor memory circuit  102  may include a plurality of buffers  110 , a command decoder  120 , a data path activation unit  130 , a memory block  140 , an output latch unit  150 , a shift register  160 , and a multiplexing unit  170 . 
         [0031]    The plurality of buffers  110  may receive the address signal ADD, the command signal CMD, the clock signal CLK, and the strobe signal RWDQSQ, and transmit data that is output from the multiplexing unit  170  to the controller  101  via a pad DQ. 
         [0032]    The clock signal CLK may output as an internal clock signal ICLK via one of the plurality of buffers  110 . 
         [0033]    The strobe signal RWDQSQ may output as phase separation strobe signals RCLK and FCLK via one of the plurality of buffers  110 . 
         [0034]    The command decoder  120  may generate an internal read command IREAD by decoding the command signal CMD. 
         [0035]    The data path activation unit  130  may generate a selection signal CY to activate the data transfer path of the memory block  140 , in response to the internal read command IREAD and the address signal ADD. 
         [0036]    The memory block  140  may output data, corresponding to the selection signal CY, through a global data line GIO. 
         [0037]    The memory block  140  may output an information signal RSTROBE to inform that data has been sent through the global data line GIO. 
         [0038]    The shift register  160  may generate data output enable signals OE and OE 05  in response to the internal read command IREAD, a CAS latency signal CL, and the internal clock signal ICLK. 
         [0039]    The output latch unit  150  may latch the data loaded on the global data line GIO to generate output data (hereinafter referred to as ‘read data RDO and FDO,’ according to a read command, in response to data output enable signals OE and OE 05 . 
         [0040]    The multiplexing unit  170  may output the read data RDO and FDO selectively in response to the phase separation strobe signals RCLK and FCLK. 
         [0041]      FIG. 2  is a circuit diagram showing the construction of the output latch unit  150  of  FIG. 1 . 
         [0042]    As shown in  FIG. 2 , the output latch unit  150  may be formed as a first-in first-out (FIFO) register. 
         [0043]    The output latch unit  150  may include a plurality of flip-flops FF  151 ˜ 153 , a plurality of ring counters CNTR  154  and  158 , a plurality of switches  155 ˜ 157 , and a demultiplexing unit  159 . 
         [0044]    The ring counter  154  may generate count signals dpin&lt;0:2&gt; in response to the information signal RSTROBE provided from the memory block  140 . 
         [0045]    The plurality of flip-flops  151 ˜ 153  may sequentially latch data outputted through the global data line GIO in response to the count signals dpin&lt;0:2&gt;. 
         [0046]    The ring counter  158  may generate count signals dpout&lt;0:2&gt; in response to the data output enable signal OE. 
         [0047]    The plurality of switches  155 ˜ 157  may output the data, latched in the plurality of flip-flops  151 ˜ 153 , sequentially in response to the count signals dpout&lt;0:2&gt;. 
         [0048]    The demultiplexing unit  159  may output the output of the plurality of switches  155 ˜ 157  as the read data RDO and FDO in response to the data output enable signal OE 05 . 
         [0049]      FIG. 3  is a block diagram showing the construction of a data processing system  2  according to an embodiment of the present to invention. 
         [0050]    As shown in  FIG. 3 , the data processing system  2  according to an embodiment of the present invention may include a controller  101  and a semiconductor memory circuit  201 . 
         [0051]    The controller  101  may provide an address signal ADD, a is command signal CMD, a clock signal CLK, and a strobe signal RWDQSQ to the semiconductor memory circuit  201 . 
         [0052]    The controller  101  may provide the strobe signal RWDQSQ to the semiconductor memory circuit  201  when a read or write command is received. 
         [0053]    When a read operation is performed, the strobe signal RWDQSQ may be used as a signal when the semiconductor memory circuit  201  outputs data. 
         [0054]    When a write operation is performed, the strobe signal RWDQSQ may be used as a signal when the semiconductor memory circuit  201  reads in data provided from the controller  101 . 
         [0055]    The controller  101  may include a CPU or a GPU. 
         [0056]    The semiconductor memory circuit  201  may perform a read operation in response to the strobe signal RWDQSQ provided from the outside, such as from the controller  101 . 
         [0057]    The semiconductor memory circuit  201  may adjust the output timing of data, corresponding to the address signal ADD, on the basis of the strobe signal RWDQSQ when a read operation is performed. 
         [0058]    The semiconductor memory circuit  201  may include a plurality of buffers  110 , a command decoder  120 , a data path activation unit  130 , a memory block  140 , an output latch unit  150 , a multiplexing unit  170 , and an output timing adjustment unit  210 . 
         [0059]    The plurality of buffers  110  may receive the address signal ADD, the command signal CMD, the clock signal CLK, and the strobe signal RWDQSQ, and transmit data that is output from the multiplexing unit  170  to the controller  101  via a pad DQ. 
         [0060]    The clock signal CLK may output as the internal clock signal ICLK via any one of the plurality of buffers  110 . 
         [0061]    The strobe signal RWDQSQ may output as a strobe signal IRWDQSQ to which the same delay time as the internal clock signal ICLK has been applied via any one of the plurality of buffers  110 . 
         [0062]    The strobe signal IRWDQSQ may output as phase separation strobe signals RCLK and FCLK via one of the plurality of buffers  110 . 
         [0063]    The command decoder  120  may generate an internal read command IREAD by decoding the command signal CMD. 
         [0064]    The data path activation unit  130  may generate a selection signal CY to activate the data transfer path of the memory block  140  in response to the internal read command IREAD and the address signal ADD. 
         [0065]    The memory block  140  may output data, corresponding to the selection signal CY, through a global data line GIO. 
         [0066]    The memory block  140  may generate an information signal RSTROBE to inform that data has been sent through the global data line GIO. 
         [0067]    The output latch unit  150  may latch data loaded on the global data line GIO, in response to data output enable signals OE and OE 05 , to generate output data (hereinafter referred to as ‘read data RDO and FDO’) according to a read command. 
         [0068]    The multiplexing unit  170  may output the read data RDO and FDO selectively in response to the phase separation strobe signals RCLK and FCLK. 
         [0069]    The output timing adjustment unit  210  is a domain crossing block, and it may adjust the timing of a read command received on the basis of the internal clock signal ICLK to generate the data output enable signals OE and OE 05 , which are both used for the strobe signal RWDQSQ based on the adjusted timing. 
         [0070]    The output timing adjustment unit  210  may generate the data output enable signals OE and OE 05  in response to preamble signals PR&lt;1:2&gt;, postamble signals PO&lt;1:2&gt;, the internal read command IREAD, an internal clock signal ICLK, and the strobe signal IRWDQSQ. 
         [0071]    The preamble signals PR&lt;1:2&gt; may define preamble information, such as information about the number of preamble pulses supported by a system. For example, if the number of preamble pulses supported by a system is 0˜2, the number of preamble pulses may be defined by using the preamble signals PR&lt;1:2&gt;. 
         [0072]    The postamble signals PO&lt;1:2&gt; may define postamble information by using a similar method as that used in the preamble signals PR&lt;1:2&gt;. 
         [0073]    The output timing adjustment unit  210  may include a timing clock generator  220  and a command register  230 . 
         [0074]    The timing clock generator  220  may shift the internal read command IREAD based on the preamble signals PR&lt;1:2&gt; and the postamble signals PO&lt;1:2&gt; in response to the internal clock signal ICLK to generate a plurality of timing clocks RDIN and CMDCLK based on the shifted internal read command IREAD. 
         [0075]    The number of pulses of the timing clock CMDCLK is equal to the number of preamble pulses+the number of postamble pulses+1 for one command. For example, if one read command is received and there are two preamble pulses and two postamble pulses, the number of pulses of the timing clock CMDCLK is 5. 
         [0076]    If preamble pulses or postamble pulses overlap with each other because a previous read command or a subsequent read command is received, the number of pulses of the timing clock CMDCLK may be reduced by the overlap amount. 
         [0077]    The command register  230  may latch the timing clock RDIN on the basis of the timing clock CMDCLK and output the latched timing clock RDIN as the data output enable signals OE and OE 05  on the basis of the strobe signal IRWDQSQ. 
         [0078]      FIG. 4  is a circuit diagram showing the construction of the timing clock generator  220  of  FIG. 3 . 
         [0079]    As shown in  FIG. 4 , the timing clock generator  220  may include a ring counter CNTR  221 , a plurality of flip-flops FF  222 ˜ 225 , a plurality of multiplexers MUX  226  and  227 , and a plurality of logic gates OR 1  and AND 1 ˜AND 5 . 
         [0080]    The ring counter  221  may count the internal read command IREAD in response to the internal clock signal ICLK to generate a preliminary timing clock RDCMD 0  based on the count. 
         [0081]    The plurality of flip-flops  222 · 225  may shift the preliminary timing clock RDCMD 0  in response to the output signals of the plurality of internal logic gates AND 1 ˜AND 4  to generate a plurality of preliminary timing clocks RDCMD&lt;1:4&gt; based on the shifted preliminary timing clock RDCMD 0 . 
         [0082]    The plurality of multiplexers  226  and  227  may output the plurality of preliminary timing clocks RDCMD&lt;0:2&gt; selectively in response to the respective preamble signals PR&lt;1:2&gt;. 
         [0083]    The multiplexer  226  may output the preliminary timing clock RDCMD&lt;0&gt; or the preliminary timing clock RDCMD&lt;1&gt; in response to the preamble signal PR&lt;2&gt;. 
         [0084]    Similarly, the multiplexer  227  may output the preliminary timing clock RDCMD&lt;0&gt; or the preliminary timing clock RDCMD&lt;2&gt; as the timing clock RDIN in response to the preamble signal PR&lt;1&gt;. 
         [0085]    The plurality of logic gates AND 1 ˜AND 4  may provide the internal clock signal ICLK to the plurality of flip-flops  222 ˜ 225  in response to the postamble signals PO&lt;1:2&gt; and the preamble signals PR&lt;1:2&gt;. 
         [0086]    The logic gates OR 1  and AND 5  may perform an OR operation on the plurality of preliminary timing clocks RDCMD&lt;0:4&gt;, and perform an AND operation on the result of the OR operation and the internal clock signal ICLK, respectively, to generate a result of the AND operation as the timing clock CMDCLK. 
         [0087]      FIGS. 5 and 6  are timing diagrams illustrating the operation of the timing clock generator  220  of  FIG. 4 . 
         [0088]    For example, assuming that each of the number of preamble pulses and the number of postamble pulses is 2, preamble signal PR 1 =H, the preamble signal PR 2 =H, the postamble signal PO 1 =H, and the postamble signal PO 2 =H. 
         [0089]    Accordingly, as shown in  FIG. 5 , the timing clock generator  220  may activate the plurality of preliminary timing clocks RDCMD&lt;1:4&gt; in response to the preamble signals PR&lt;1:2&gt; and the postamble signals PO&lt;1:2&gt; having the above-described values to generate the timing clock CMDCLK having five pulses. 
         [0090]    In another example, assuming that each of the number of preamble pulses and the number of postamble pulses is 1, the preamble signal PR 1 =H, the preamble signal PR 2 =L, the postamble signal PO 1 =H, and the postamble signal PO 2 =L. 
         [0091]    Accordingly, as shown in  FIG. 6 , the timing clock generator  220  may activate the plurality of preliminary timing clocks RDCMD&lt;0, 2, 3&gt; in response to the preamble signals PR&lt;1:2&gt; and the postamble signals PO&lt;1:2&gt; having the above-described values to generate the timing clock CMDCLK having three pulses. 
         [0092]      FIG. 7  is a circuit diagram showing the construction of the command register  230  of  FIG. 3 . 
         [0093]    As shown in  FIG. 7 , the command register  230  may be formed as a first-in first-out (FIFO) register. 
         [0094]    The command register  230  may include a plurality of flip-flops FF  231 ˜ 233 , a plurality of ring counters CNTR  234  and  238 , a plurality of switches  235 ˜ 237 , and a demultiplexing unit  239 . 
         [0095]    The ring counter  234  may generate count signals cpin&lt;0:2&gt; in response to the timing clock CMDCLK. 
         [0096]    The plurality of flip-flops  231 ˜ 233  may sequentially latch the timing clock RDIN in response to the count signals cpin&lt;0:2&gt;. 
         [0097]    The ring counter  238  may generate count signals cpout&lt;0:2&gt; in response to the strobe signal IRWDQSQ. 
         [0098]    The plurality of switches  235 ˜ 237  may sequentially output data, latched in the respective flip-flops  231 ˜ 233 , to the count signals cpout&lt;0:2&gt;. 
         [0099]    The demultiplexing unit  239  may output the outputs of the plurality of switches  235 ˜ 237  as the data output enable signals OE and OE 05  in response to the strobe signal IRWDQSQ. 
         [0100]      FIG. 8  is a timing diagram illustrating a read operation according to an embodiment of the present invention. 
         [0101]    First, it is assumed that a read command, a no operation (NOP), and a read command are sequentially received, and each of the number of preamble pulses and the number of postamble pulses are 1. 
         [0102]    The two internal read commands IREAD are generated at a predetermined delay time (tCMD) interval from the read command. 
         [0103]    The timing clock CMDCLK is generated in response to the internal read command IREAD, and the timing clock RDIN is generated after 1tCK on the basis of each internal read command IREAD. 
         [0104]    The data output enable signal OE is generated in response to the strobe signal RWDQSQ generated after CAS latency (CL). 
         [0105]    Data is output via the pad DQ in response to the data output enable signal OE. 
         [0106]    In accordance with the above-described method, the data output enable signal OE may be generated as the domain of the strobe signal RWDQSQ, and a timing error in the strobe signal RWDQSQ and the clock signal CLK due to tDQSS and power noise may be compensated for. 
         [0107]      FIG. 9  is a block diagram showing the construction of a data processing system  3  according to an embodiment of the present invention. 
         [0108]    As shown in  FIG. 9 , the data processing system  3  according to an embodiment of the present invention may include a controller  101  and a semiconductor memory circuit  301 . 
         [0109]    The controller  101  may provide an address signal ADD, a command signal CMD, a clock signal CLK, and a strobe signal RWDQSQ to the semiconductor memory circuit  301 . 
         [0110]    The controller  101  may provide the strobe signal RWDQSQ to the semiconductor memory circuit  301  when a read or write command is received. 
         [0111]    When a write operation is performed, the strobe signal RWDQSQ may be used as a signal when the semiconductor memory circuit  301  reads in data provided from the controller  101 . 
         [0112]    When a read operation is performed, the strobe signal RWDQSQ may be used as a signal when the semiconductor memory circuit  301  outputs data. 
         [0113]    The controller  101  may include a CPU or a GPU. 
         [0114]    The semiconductor memory circuit  301  may perform a write operation in response to the strobe signal RWDQSQ provided from the outside, such as the controller  101 . 
         [0115]    The semiconductor memory circuit  301  may adjust the write timing of data on the basis of the strobe signal RWDQSQ when a write operation is performed. 
         [0116]    The semiconductor memory circuit  301  may include a plurality of buffers  111 , a command decoder  120 , a data path activation unit  302 , a memory block  140 , an input latch unit  350 , a latch  340 , and an input timing adjustment unit  310 . 
         [0117]    The plurality of buffers  111  may receive the address signal ADD, the command signal CMD, the clock signal CLK, and the strobe signal RWDQSQ, and can receive data via a pad DQ. 
         [0118]    The clock signal CLK may output as an internal clock signal ICLK via any one of the plurality of buffers  111 . 
         [0119]    The strobe signal RWDQSQ may be output as a strobe signal IRWDQSQ to which the same delay time as the internal clock signal ICLK has been applied via any one of the plurality of buffers  111 . 
         [0120]    The strobe signal IRWDQSQ may be output as phase separation strobe signals DQSRP and DQSFP via any one of the plurality of buffers  111 . 
         [0121]    The command decoder  120  may generate an internal write command IWRITE by decoding the command signal CMD. 
         [0122]    The data path activation unit  302  may generate a selection signal CY to activate the data transfer path of the memory block  140  in response to the internal write command IWRITE and the address signal ADD. 
         [0123]    The data path activation unit  302  may output an information signal DINSTROBE that informs the input of data according to a write operation. 
         [0124]    The memory block  140  may write data, received through a global data line GIO, into a region corresponding to the selection signal CY. 
         [0125]    The latch  340  may latch data DINR and DINF, received through the pad DQ, in response to the phase separation strobe signals DQSRP and DQSFP. 
         [0126]    The input latch unit  350  may latch the data DINR and DINF, latched in the latch  340 , in response to the information signal DINSTROBE and data write enable signals WE and WE 05  and input the latched data into the memory block  140  through the global data line GIO. 
         [0127]    The input timing adjustment unit  310  is a domain crossing block, and it may adjust the timing of a write command received on the basis of the internal clock signal ICLK and to generate the data write enable signals WE and WE 05  which are both used for the strobe signal RWDQSQ based on the adjusted timing. 
         [0128]    The input timing adjustment unit  310  may generate the data write enable signals WE and WE 05  in response to preamble signals PR&lt;1:2&gt;, postamble signals PO&lt;1:2&gt;, the internal write command signal IWRITE, the internal clock signal ICLK, and the strobe signal IRWDQSQ. 
         [0129]    The preamble signals PR&lt;1:2&gt; may define preamble information, such as information about the number of preamble pulses supported by a system. For example, if the number of preamble pulses supported by a system is 0˜2, the number of preamble pulses may be defined by using the preamble signals PR&lt;1:2&gt;. 
         [0130]    The postamble signals PO&lt;1:2&gt; may define postamble information by using a similar method as that used in the preamble signals PR&lt;1:2&gt;. 
         [0131]    The input timing adjustment unit  310  may include a timing clock generator  320  and a command register  330 . 
         [0132]    The timing clock generator  320  may shift the internal write command IWRITE based on the preamble signals PR&lt;1:2&gt; and the postamble signals PO&lt;1:2&gt; in response to the internal clock signal ICLK to generate a plurality of timing clocks WTIN and CMDCLK based on the shifted internal write command IWRITE. 
         [0133]    The number of pulses of the timing clock CMDCLK is equal to the number of preamble pulses+the number of postamble pulses+1 for one command. For example, if one read command is received and there are two preamble pulses and two postamble pulses, the number of pulses of the timing clock CMDCLK is 5. 
         [0134]    If preamble pulses or postamble pulses overlap with each is other because a previous read command or a subsequent read command is received, the number of pulses of the timing clock CMDCLK may be reduced by the overlap amount. 
         [0135]    The timing clock generator  320  may be configured like the timing clock generator  220  of  FIG. 4 . 
         [0136]    The command register  330  may latch the timing clock WTIN on the basis of the timing clock CMDCLK and output the latched timing clock WTIN as the data write enable signals WE and WE 05  on the basis of the strobe signal IRWDQSQ. 
         [0137]    The command register  330  may be configured like the command register  230  of  FIG. 7 . 
         [0138]    In accordance with the above-described method, the data write enable signal WE may be generated as the domain of the strobe signal RWDQSQ, and a timing error in the strobe signal RWDQSQ and the clock signal CLK due to tDQSS and power noise may be compensated for. 
         [0139]    In accordance with the embodiments of the present invention, data may be stably read and written at high speed by using the strobe signal provided by the controller. 
         [0140]    While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the semiconductor memory circuit and the data processing system using the same described herein should not be limited based on the described embodiments. Rather, the semiconductor memory circuit and the data processing system described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.