Abstract:
Current mode current sense circuits and methods that may provide a current output proportional to the sensed current, and that provide current sensing at a fixed voltage drop. Sensing is by way of a transistor coupled in series with the load, with circuitry clamping the voltage drop across the transistor to a predetermined level, and providing a current output proportional to the current in that transistor. Various embodiments are disclosed, including circuits for high side and low side sensing, and which are capable of operation in the presence of short circuits.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to the field of current sensing circuits and methods. 
   2. Prior Art 
   The common prior art technique used for current sensing is based on a sense resistor. The sense resistor is placed in series with the load whose current is to be sensed, with the sensed current developing a voltage across the resistor (see FIG.  1 ). The voltage is amplified and delivered at the output. This current measurement technique is “voltage mode”, as the input signal is a voltage (V SENSE ): V OUT =A·V SENSE , where V SENSE =R 1 ·I IN . 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a circuit diagram illustrating a prior art voltage mode current sense circuit. 
       FIG. 2  is a circuit diagram for one embodiment of a current mode current sensing circuit using p-channel transistors in accordance with the present invention. 
       FIG. 3  is an embodiment similar to that of  FIG. 2 , but using n-channel transistors instead of n-channel transistors. 
       FIG. 4  is a circuit diagram for a modified version of the current mode current sensing circuit of the present invention using p-channel transistors. 
       FIG. 5  is an embodiment for minimizing the error that may occur if the input becomes shorted. 
       FIG. 6  is a diagram showing the circuit architecture that may be used for precision current sensing of the current delivered to a load connected between IN and GND. 
       FIG. 7  illustrates the connection of a current mode current sense circuit such as that of  FIG. 2  between the positive power supply terminal and a current utilizing circuit (load). 
       FIG. 8  illustrates the connection of a current mode current sense circuit such as that of  FIG. 3  between the current utilizing circuit (load) and a circuit ground. 
       FIG. 9  illustrates the use of two “high side” current mode current sense circuits coupled in parallel to sense both positive and negative currents. 
       FIG. 10  presents a simplified diagram of one embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   In the description to follow, the basic principles of the present invention shall be described in relation to high side unidirectional current sense circuits as perhaps being the most common application thereof. However, the invention is not so limited, as shall subsequently be described, as the same is applicable to low side sensing and/or bi-directional current sensing. 
   Now referring to  FIG. 2 , one embodiment of the present invention may be seen. In this embodiment, for simplicity and not as a necessity, it will be assumed that the current sources are equal, that is:
 
I B1 =I B2 =I B3 =I B4 =I B5 =I B  
 
However, in the description to follow, for greater clarity, frequently a specific current source will be referred to rather than simply I B  generally. Also it is assumed that p-channel transistors P 3  through P 7  are matched transistors having the same W/L ratio and sizes. Also, p-channel transistors P 1  and P 2  are assumed matched by the ratio N, with transistor P 1  being N times the size of transistor P 2 , where N can be less than, equal to or more frequently, substantially greater than 1.
 
   The load or current drawing component or circuit (herein generally referred to simply as the load) is connected between the terminals IN and GND. Consequently, the entire current provided to the load from the power supply VCC flows through p-channel transistor P 1 . With the foregoing assumptions, the voltage at the source of transistor P 5  is equal to R 1  times I B3 , or R 1 *I B . Since current sources I B1 , I B2  and I B3  are equal and transistors P 3 , P 4  and P 5  are matched, all three transistors will have the same source to gate voltage, and thus the same source voltage. Consequently the input voltage VIN will be equal to the VCC minus the voltage drop across resistor R 1 , namely VIN=VCC−R 1 *I B . 
   Also, transistors P 1  and P 2  will have the same source to drain voltages, so that the current in transistor P 2  mirrored or replicated from transistor P 1  will be N times less than the current in transistor P 1 , namely (I IN +I B1 )/N. If the current through transistor P 3  varies from I B1 , the gate voltages on transistors P 3 , P 4  and P 5  will change, changing the current through resistor R 1 . The current difference between the current through resistor R 1  and current source I B3  is coupled to the gate of transistor P 6 . This disturbs the current balance between the current through resistor R 2  and current source I B4 , with the difference being fed back to control the gate voltages of transistors P 1  and P 2  to rebalance the circuit. Thus, transistors P 1 , P 2 , P 3 , P 5  and P 6  form a first closed loop. 
   Since the current in transistor P 2  is (I IN +I B1 )/N, and the current through transistor P 4  is only I B2 , the current passed to the source of transistor P 8  is (I IN +I B1 )/N−I B2 . Also, because transistors P 3 , P 4  and P 5  are matched and conduct equal currents, the voltage drop across resistor R 3  will be the same as the voltage drop across Resistor R 1 . Consequently the current through resistor R 3  will be I B *R 1 /R 3 . 
   The total current I O  through transistor P 8  to the out put will be: 
                 I   O     =         (       I   IN     +     I   B       )     /   N     -     I   B     +       I   B     ⁢     R1   /   R3           )               =         I   IN     /   N     +       I   B     ⁡     (       R1   /   R3     +     1   /   N     -   1     )                   
 
   Thus, the output current I O  varies linearly with the input current I N . The input voltage VIN=(I B *R 1 ) is independent of the input current, and can be set as low as the size of the sense device (P 1 ) allows. Also if:
 
 R   1 / R   3 =1−1/ N  
 
then the output current is proportional to the in put current as follows:
 
 I   O   =I   i   /N  
 
   In the circuit of  FIG. 2 , if transistor P 8  conducts less than the above output current, then the excess current through transistor P 2  will cause the source voltage of transistor P 4  to increase so that transistor P 4  will conduct current in excess of I B2 . This raises the voltage on the gate of transistor P 7 , reducing the current flow in resistor R 4  so that the current source I B5  will pull down the voltage on the gate of transistor P 8  to increase the current flow through transistor P 8 . Thus, transistors P 1 , P 2 , P 3 , P 4 , P 7  and P 8  form a second closed loop to provide an output current independent of the output voltage as stated before, thereby providing a very high impedance current source output. 
   The circuit of  FIG. 2  may be modified to sense current not between VCC and IN, but rather between IN and GND by flipping the circuit over and substituting n-channel devices for the p-channel devices of  FIG. 1  (the direction of the current sources not being changed). 
     FIG. 3  presents another embodiment of a current mode current sensing circuit in accordance with the present invention. This circuit using n-channel transistors is also based on the matching properties of two MOS devices having the same V DS  and V GS  voltage. Transistor MN 1  is scaled to transistor MN 2  by a multiple of M. Thus transistor MN 1  may consist of M transistors, each identical to transistor MN 2 . For simplicity of explanation, though as shall be ovbvious to one skilled in the art, not as a limmitation of the invention, assume that current sources  11 ,  12 ,  13  and  14  force the same current I into the respective nodes. It is also assumed that transistors MN 3 , MN 4  and MN 5 , MN 6  are, respectively, matched. 
   The circuit comprises two negative feedback loops. One loop consists of transistors MN 1 , MN 2  and MN 4 . This loop sets the voltage at the input, IN. Assuming V GS3 =V GS4 , V IN =I·R 1 . The second loop consists of transistors MN 5 , MN 6  and MN 7 . This loop enables the same V DS  for both transistors MN 1  and MN 2 , assuming that V GS5 =V GS6 . Due to negative feedback, the output current, I OUT , is:
 
 I   OUT   =I   D2   +I   R2   −I  
 
   Assuming that V GS5 =V GS6  and V GS3 =V GS4 , I·R 1 =I R2 ·R 2 . The current I D1  is set by the currents flowing at IN node:
 
 I   D1   =I   IN +2 ·I  
 
   Based on scaling between transistors MN 1  and MN 2 , I D2 =I D1 /M. Using the results for I D1 , I D2  and I R2  the output current expression becomes: I OUT =I IN /M+I·(R 1 /R 2 +2/M−1) If resistors R 1  and R 2  satisfy the condition R 1 /R 2 =1−2/M, then I OUT =I IN /M. Thus the circuit in  FIG. 2  senses the input current I IN , and may generate an output current I OUT =I IN /M. Additionally, the circuit sets the voltage at the input V IN =I·R 1 , independent of the input current I IN . 
     FIG. 4  is an embodiment similar to that of  FIG. 3 , but using p-channel transistors instead of n-channel transistors. Thus the circuit of  FIG. 3  senses current between IN and GND while the circuit of  FIG. 4  senses current between VCC and IN. 
     FIG. 5  is a circuit diagram for a modified version of the current mode current sensing circuit of the present invention using p-channel transistors. This circuit is able to measure the input current I IN  when the input IN is shorted to ground GND. In normal operation (no short-to-GND), the voltage at the input is set such that V CC −V IN =I·R 1 . The input current I IN  is sensed by transistor MP 1  and then scaled at the output through transistor MP 2 , i.e. I OUT =I IN /M. The buffer provides fast charging of the gate-source capacitances of transistors MP 1  and MP 2 . The block composed of transistors MP 11 , MP 12 , MN 1 , MN 2  and MN 8  acts as a supplemental negative feedback loop in parallel with the loop composed of transistors MP 3 , MP 4  and MP 7 . The supplemental loop is active when the input (IN) is electrically pulled down to GND. Then transistor MP 6  is off and the gates of transistors MP 1  and MP 2  are pulled to GND. Transistor MP 3  is off and the loop formed of transistors MP 3 , MP 4  and MP 7  is no longer able to achieve its function. At this point, the supplemental loop is active such that the potential at the drain of transistor MP 2  follows the potential at the drain of transistor MP 1 , so that V DS1 =V DS2 . This can be achieved provided that V OUT ≦V IN . However, V OUT  is always greater than 0. Thus, if V IN =0, the previous condition cannot be met. Consequently under these conditions, V DS1 &gt;V DS2 . Therefore, if input (IN) is shorted to ground (GND), current scaling accuracy of transistors MP 1  relative to transistor MP 2  is affected by the different drain-source voltage V DS1 , V DS2  values. However, the error can be minimized if the voltage at the output (OUT) is small (10 mV to 100 mV range) compared to the supply voltage (&gt;1.8V). This can be possible using the circuit presented in FIG.  6 . 
   The circuit architecture presented in  FIG. 6  is used for precision current sensing of the current delivered to a load connected between IN and GND. In normal operation (no input short-to-ground), the voltage drop between VCC and IN is set by the block B  1  (see FIG.  5 ). The voltage V 1  is set by the block B 2  (see FIG.  3 ). The block B 3  transfers I 2  current to the ouput (I OUT =I 2 ). This allows current to voltage conversion through the resistor R. The output voltage V OUT  is proportional to the input current I IN  over a wide range. Three to six decades of input current variation can be covered. 
     FIG. 7  illustrates the connection of a current mode current sense circuit such as that of  FIG. 2  between the positive power supply terminal and a current utilizing circuit (load), while  FIG. 8  illustrates the connection of a current mode current sense circuit such as that of  FIG. 3  between the current utilizing circuit (load) and a circuit ground. Two circuits in accordance with the present invention may also be used to sense bi-directional current. By way of example,  FIG. 9  illustrates the use of two “high side” current mode current sense circuits coupled in parallel as part of an exemplary battery circuit wherein charging and discharging currents may be sensed. 
     FIG. 10  presents a simplified diagram of an embodiment of the present invention. While I 1 ,  12  and  13  may be equal current sources with p-channel transistors MP 3  and MP 4  being matched transistors (including size), this is not a requirement. If the current sources  11  and  12  are in the ratio of the size of transistors MP 3  and MP 4  (so that the transistors have the same current density), the voltage of the sources of transistors MP 3  and MP 4  will be equal. Since amplifier A 1  forces the voltage of the source of transistor MP 4  to equal VCC minus the voltage drop across resistor R 1  (which is I 3 *R 1 ), and the source voltages of transistors MP 3  and MP 4  are equal, the amplifier indirectly forces the voltage on the terminal IN to also equal VCC minus the voltage drop across resistor R 1 . 
   In preferred designs, the ratio of the current sources I 1  and I 2  and the ratio of the size of transistors MP 3  and MP 4 , if not one to one, will not be large. With transistor MP 1  being N times as large as transistor MP 2  where N is usually substantial, when the current IN is zero, the current through transistor MP 2  will be I 1 /N. Picking the value of resistor R 2  to supply a current to transistor MP 4  of I 2 −I 1 /N, the current if I 1 =I 2 =I 3  
 
R 1 /R 2 =1−1/ N  
 
for any values of I 1 , I 2  and I 3 : 
       R2   =     R1   ⁢     I3     I2   -     I1   N               
 
   As current IN is supplied to a load connected to the IN terminal, the current through transistor MP 2  will increase by IN/N, all of which will be provided to the output OUT through transistor MP 6 . Note that the output OUT is a high impedance current source output. In particular, assume that a steady current IN is being supplied to a load, but that the voltage on the OUT terminal suddenly decreases. This suggests that more of the current through transistor MP 2  will be delivered to the output OUT. However, if the current through transistor MP 4  decreases, current source  12  will pull the negative input to amplifier A 2  lower, reducing the current through transistor MP 6  as required to maintain the current through transistor MP 4  equal to the current through current source  12 . Thus, amplifier A 2  and current source MP 6  act as a current regulator, maintaining the current at the output OUT equal to IN/N, independent of the voltage on the output terminal OUT. 
   The embodiments disclosed herein have been MOS embodiments. Preferably in other embodiments, the input devices will also be MOS devices, though other parts of the circuit may be comprised of bipolar transistors, as desired. 
   While certain preferred embodiments of the present invention have been disclosed herein, such disclosure is only for purposes of understanding the exemplary embodiments and not by way of limitation of the invention. It will be obvious to those skilled in the art that various changes in form and detail may be made in the invention without departing from the spirit and scope of the invention as set out in the full scope of the following claims.