Abstract:
A dual power mode transmitter is provided to save power when the transmitter switches from normal operating mode to low power operating mode. The dual power mode transmitter achieves power savings by controlling the amount of current draw in the input stage. Alternatively, the transmitter saves power by regulating the voltage at the output node of the input stage.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 60/801,399 filed May 19, 2006, which is incorporated herein by reference in its entirety. 
     
     FIELD OF THE INVENTION  
       [0002]    The present invention relates to dual power mode transmitter. Specifically, the invention relates to a transmitter capable of operating in a normal power mode and a low power mode. 
       BACKGROUND OF THE INVENTION  
       [0003]    Battery size is one of the main constraints that limits how small mobile devices can be made. One way to design around this limitation and to make a mobile device even smaller is to use a small battery and at the same time increase the power efficiency of the mobile device. In mobile devices equipped with wireless communication such as mobile phones, personal digital assistants (PDAs), and laptops, the amplifying stage in such systems is typically one of the main circuit elements that drain the most power. 
         [0004]    Generally, mobile devices include an amplifying stage that consists of a programmable gain amplifier or a buffer, a power amplifier driver or driver-amplifier, and a power amplifier. The amplifying stage is typically configured to provide a certain power output that is optimized for the mobile device&#39;s purpose. This power output optimization is, however, constant. Thus, when the mobile device enters a low power mode, the amplifying stage still consumes the same amount of power as if it is in a normal or high power mode. 
         [0005]    Accordingly, it is desirable to have an amplifying stage with various power operating modes such as normal and low power modes. It is further desirable to have an amplifying stage that consumes less power while in the low power mode. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES  
         [0006]    The present invention is described with reference to the accompanying drawings. 
           [0007]      FIG. 1  illustrates a block circuit diagram of a transmitter. 
           [0008]      FIG. 2A  illustrates a chart showing the relationship between input and output power of an amplifier. 
           [0009]      FIG. 2B  illustrates the relationship between frequency amplitude and time in various operating modes of an amplifier. 
           [0010]      FIG. 3  illustrates a chart showing the relationship between input and output power of an amplifier. 
           [0011]      FIG. 4  illustrates a chart showing the relationship between input and output power of an amplifier operating in various modes. 
           [0012]      FIG. 5A  illustrates a block circuit diagram of a transmitter according to an embodiment of the present invention 
           [0013]      FIG. 5B  illustrates a block circuit diagram of the transmitter in  FIG. 5A  in an exemplary application environment. 
           [0014]      FIG. 6  illustrates a differential amplifier implemented by the transmitter shown in  FIG. 1 . 
           [0015]      FIG. 7A  illustrates a circuit diagram of a differential input stage in accordance to an embodiment of the present invention. 
           [0016]      FIG. 7B  illustrates a circuit diagram of a differential input stage in accordance to another embodiment of the present invention. 
           [0017]      FIG. 8  illustrates a chart showing the relationship between input and output power of an amplifier in the transmitter shown in  FIG. 5A . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]    This specification discloses one or more embodiments that incorporate the features of this invention. The embodiment(s) described, and references in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment(s) described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. An embodiment of the present invention is now described. While specific methods and configurations are discussed, it should be understood that this is done for illustration purposes only. A person skilled in the art will recognize that other configurations and procedures may be used without departing from the spirit and scope of the invention. 
         [0019]      FIG. 1  illustrates a wireless transmitter  100  that includes a modulator  102 , a pair of digital to analog converters  110 A and  110 B (DAC), a pair of low pass filters  130 A and  130 B, a summer  140 , a programmable gain amplifier or buffer stage  150 , an power amplifier driver or driver-amplifier  160 , a transformer  170 , a power amplifier  180 , and an antenna  190 . 
         [0020]    Modulator  102  is adapted to receive and encode raw data signals (not shown). After modulating and encoding the raw data signals, modulator  102  outputs an in-phase (I) data signal  104  and a quadrature-phase (Q) data signal  106 . Data signals  102  and  104  can be signals evenly spaced from an intermediate frequency (IF) or can be baseband signals. 
         [0021]    DAC  110 A is set to receive signals  104  and convert them into analog signals  112  which are supplied to low pass filter  120 A. Filter  120  is used to reject unwanted frequency portions of signals  112 . The signals passed by filter  120 A are then directed to mixer  130 A as signals  122 . 
         [0022]    Mixer&#39;s  130 A main function is to up-convert signals  122 . The up-conversion is done by mixing signals  122  with signals from a local oscillator (not shown). Once the up-conversion is completed, mixer  130 A passes the up-converted signals  132  to summer  140 . The functionalities of DAC  110 B, low pass filter  120 B, and mixer  130 B are similar to the functionalities of DAC  110 A, filter  120 A, and mixer  130 A. The main distinction is the processing of Q signals instead of I signals. 
         [0023]    As shown in  FIG. 1 , summer  140  is coupled to mixers  130 A and  130 B. Summer  130  is configured to receive signals from both mixers  130 A and  130 B. Summer  130  combines signals  132  and  134  to produce signals  142 , which are feed to programmable gain amplifier (PGA)  150 . 
         [0024]    The buffer stage or PGA  150  has 2 main functions. One of the main functions is to serve as an impedance variations isolator between all of the circuit elements to the left of PGA  150  (summer  140 , mixers  130 A-B, filters  120 A-B, DACs  110 A-B) and the power amplifier driver (PAD)  160 . The other function is to provide the proper amount of signal amplification in order for PAD  160  and power amplifier  180  to produce a required amount of output power. 
         [0025]    Transmitter  100  further includes PAD  160  that amplifies output of PGA/buffer  150 . PAD  160  provides pre-amplified signals  162  at a specific power amount to enable power amplifier  180  to output amplified signals  182  with a predetermined amount of power. In transmitter  100 , transformer  170  matches the impedance at the output PAD  160  with the input of power amplifier  180 . Transformer  170  also converts differential signals  162  outputted by PAD  160  into single-ended signals  164 . Once signals  164  are amplified by power amplifier  180 , the signals are then transmitted by antenna  190 . 
         [0026]    As shown in  FIG. 1 , line  165  shows which portion of transmitter  100  is on-chip and which portion is off-chip. Power amplifier  180  is typically located off chip. However, transmitter  100  could be also configured such that power amplifier  180  is located on chip. 
         [0027]    Transmitter  100  can be configured to work with various multiplexing systems such as time division multiple access (TDMA), code division multiple access (CDMA), and orthogonal frequency division multiplexing (OFDM). In one embodiment of an OFDM application, power amplifier driver  160  is typically adapted to output at approximately 6 dBm. As a design rule of thumb, the 1-dB compression point of power amplifier driver  160  should be 10 dBm above the operating output level. It follows that power amplifier driver  160  in an OFDM system should have a 1-dB compression point at 16 dBm. 
         [0028]    At the 1-dB compression point, power amplifier driver  160  starts to go into compression mode.  FIG. 2A  illustrates an input power vs. output power chart in dBm. Line  202  is the power gain line of an ideal amplifier. Line  204  is the power gain line of a typical amplifier such as power amplifier  180 . As shown in  FIG. 2 , point  220  shows the start of the 1-dB compression point for power amplifier driver  160 . Power amplifier driver  160  remains in the linear operating region for any datum point to the left of point  220 . To the right of datum point  220 , power amplifier driver  160  is non-linear. The 1-dB compression point is determined by finding the input power value where there is a 1 dB difference between the ideal amplifier and non-ideal amplifier output power. In this case, point  210  is approximately 1 dB higher than point  220 . 
         [0029]      FIG. 2B  illustrates a signal at various stages of amplification in the time domain. Signal  260  is an un-amplified signal. Signal  270  is an amplified signal of signal  260  with the power amplifier operating in the linear region. Signal  280  is an amplified signal of  260  with the power amplifier in compression. As shown in  FIG. 2B , signal  280  has a clipped portion  285  near the peak of its amplitude. When clipping occurs during the amplification of a data signal, data will be lost or adversely affected. 
         [0030]      FIG. 3  illustrates a gain chart showing the operating region of power amplifier  180 . Point  320  shows the 1-dB compression point. For OFDM application, a power amplifier is selected to have a 1-dB compression point of approximately 16 dBm. Point  330  is the 6 dBm point; the desired power output of power amplifier driver  160 . The 10 dB buffer between points  320  and  330  serves to prevent data loss, which is especially useful for 802.11a, 802.11b, 802.11g, and OFDM data signals. 
         [0031]    As mentioned, for normal operation, power amplifier driver  160  is set to output approximately 6 dBm. However, for certain lower power application, power amplifier driver  160  only needs to output 0 dBm, which is approximately 1 mW. In another exemplary low power application, power amplifier driver  160  only needs to output −5 dBm. In these low power scenarios, high power output is not necessary because an external power amplifier is likely used to augment the signals&#39; power level to a desired level. 
         [0032]      FIG. 4  illustrates how low power mode is generally achieved. Point  430  is the 6 dBm operating point, shown with respect to the 1-dB compression point  420  and 0 dBm operating point  440 . Generally, one can reduce the power output of power amplifier driver  160  by reducing the input signals at the input of power amplifier driver  160 . Even though the signal amplitude or intensity at the input of power amplifier driver  160  may be reduced, the current consumption of driver-amplifier  160  remains the same. Consequently, the power consumption of the power amplifier driver  160  is the same for both normal and low power modes. 
         [0033]      FIG. 5A  illustrates a wireless transmitter  500  according to an embodiment of the present invention. Transmitter  500  that includes a modulator  502 , a pair of digital to analog converters  510 A and  510 B (DAC), a pair of low pass filters  530 A and  530 B, a summer  540 , a programmable gain amplifier or buffer stage  550 , a variable power amplifier driver or variable driver-amplifier  560 , a transformer  570 , a power amplifier  580 , and an antenna  590 . 
         [0034]    Modulator  502  is adapted to receive and encode raw data signals (not shown). After modulating and encoding the raw data signals, modulator  502  outputs an in-phase (I) data signals  504  and a quadrature-phase (Q) data signals  506 . Data signals  502  and  504  can be signals evenly spaced from an intermediate frequency (IF) or can be baseband signals. 
         [0035]    DAC  510 A is set to receive signals  504  and convert them into analog signals  512  which are supplied to low pass filter  520 A. Filter  550  is used to reject unwanted frequency portions of signals  512 . The signals passed by filter  520 A are then directed to mixer  530 A as signals  522 . 
         [0036]    Mixer&#39;s  530 A main function is to up-convert signals  522 . The up-conversion is done by mixing signals  522  with signals from a local oscillator (not shown). Once the up-conversion is completed, mixer  530 A passes the up-converted signals  532  to summer  540 . The functionalities of DAC  510 B, low pass filter  520 B, and mixer  530 B are similar to the functionalities of DAC  510 A, filter  520 A, and mixer  530 A. The main distinction is the processing of quadrature (Q) signals instead of in-phase (I) signals. 
         [0037]    Summer  540  is coupled to mixers  530 A and  530 B. Summer  530  is configured to receive signals from both mixers  530 A and  530 B. Summer  530  combines signals  532  and  534  to produce signals  542 , which are feed to programmable gain amplifier (PGA)  550 . 
         [0038]    The buffer stage or PGA  550  has  2  main functions. One of the main functions is to serve as an impedance variations isolator between all of the circuit elements to the left of PGA  550  (summer  540 , mixers  530 A-B, filters  520 A-B, DACs  510 A-B) and the power amplifier driver (PAD)  560 . The other function is to provide the proper amount of signal amplification in order for PAD  560  to produce the required amount of output power. 
         [0039]    Transmitter  500  further includes variable PAD  560  with selectable power output. In low power mode, variable PAD&#39;s  560  circuitry is re-configured through internal switching means to provide a lower powered pre-amplified signal while pulling less current from the battery. This re-configuration may be done in real-time when PAD  560  is in use, or after the manufacturing of PAD  560 . In contrast, PAD  160  maintains the same amount of current usage regardless of whether transmitter  100  is in normal or low power mode. 
         [0040]      FIG. 5B  illustrates transmitter  500  in an exemplary normal power mode (non-low power mode) application where no external power amplifier is needed. As shown in  FIG. 5B , the output signals of PAD  560  are not amplified. When transmitter  500  is in normal power mode, it is operating with high linearity. In certain applications where the intended receiver is at a close range, high linearity is required from PAD  560  to ensure that the signal&#39;s strength is strong enough to reach the receiver because in such application an external power amplifier is not used. 
         [0041]      FIG. 6  illustrates an exemplary differential input stage  600  implemented in PAD  160  of transmitter  100 . Differential input stage  600  is a cascode input stage that is optimized such that PAD  160  output is at approximately 6 dBm. In low power mode, where the output of PAD  160  is adjusted down to 0 dBm, differential input stage  600  outputs a lower power signal, but the current usage of input stage  600  remains the same. 
         [0042]    Differential input stage  600  includes transistors  610 ,  620 ,  630 , and  640 . The gates of transistors  630  and  640  are commonly biased by a biasing source (not shown). The gates of transistors  610  and  620  are coupled to differential input signals  152  from programmable gain amplifier  150 . Differential input stage  600  produces a differential current pair based on differential input signals  552 . The magnitude of the each differential current depends on the relative size of transistor pairs  610 ,  630  and  620 ,  640 . Generally, the size of transistor pairs  610 ,  630  and  620 ,  640  are selected such that power amplifier driver  160  yields the desired power output. As a result, the current consumption of the two transistor pairs remains constant whether or not transmitter  100  is in normal or low power mode. 
         [0043]      FIG. 7A  illustrates a differential cascode input stage  700  that is implemented in one embodiment of variable PAD  560 . Differential input stage  700  comprises many cascode input stages coupled in parallel. Differential input stage  700  includes transistors  710 A-D,  720 A-D,  730 A-D, and  740 A-D. Transistors  720 A and  740 A, together, form an input stage. Similarly, transistors  710 A and  730 A form another input stage. The gates of transistors  710 A-D receive a portion of differential pre-amplified signals  552  (e.g. quadrature portion). Similarly, the gates of transistors  720 A-D receive another portion of differential pre-amplified signals  552  (e.g. in-phase portion). Each gate of transistors  730 A-D and  740 A-D is biased by a bias control circuits  750 A and  750 B. Although bias control circuits  750 A and  750 B are shown as two separate circuits in  FIG. 7 , bias control circuit  750 A-B can be implemented as a single circuit. 
         [0044]    In differential input stage  700 , bias control circuit  750  biases the gates of transistors  730 A-D and  740 A-D in pair such that an equal number amount of transistor is biased on each differential branch. For example, if the gate of transistor  730 A is biased, then the gate of transistor  740 A is also biased. In another example, if the gates of transistors  730 A-B are biased, then the gates of transistors  740 A-B are also biased. In this way, differential input stage  700  can output two approximately equal differential currents—one on each differential branch. Other biasing arrangement could be utilized based on discussions given herein. 
         [0045]    The multiple cascode input stages configuration of differential input stage  700  allows variable PAD  560  to selectively turn on and off one or more cascode stages as desired. As mentioned, an equal amount of cascode stage must be selected to be active on each differential side of the amplifier. This configuration allows variable PAD  560  to turn on as many cascode branches as needed to meet a specified amount of power output. For example, if the maximum power output is desired such that PAD  560  outputs 6 dBm, then variable PAD  560  will select all of the cascode branches. Selection of a cascode branch is done through biasing control circuit  750 . Cascode branches that are selected to be active will be biased; cascode branches not biased will be off. Stated another way, corresponding pair of transistors  730 A-D and  740 A-D are biased on/off to provide a desired gain and output power. 
         [0046]    When transmitter  500  is in low power mode, bias control circuits  750 A-B will select a number of cascode branches required for 0 dBm output. The size of each of the transistors in the cascode branches will determine the amount of branches to be turned on. For example, cascode branches  765 A-B could be optimized to allow power amplifier  580  to output approximately 0 dBm. In this situation, bias control circuit  750 A-B will bias the gate of transistor  740 A and  730 A, respectively. When this occurs, the differential signal input at the gate of transistor  710 A will drive transistors  710 A and  730 A and causes a current flow through output node  760 A. Similarly, the differential signal input at the gate of transistor  720 A will drive transistors  720 A and  740 A and causes a current flow through output node  760 B. Further, by limiting the number of transistors being biased, variable PAD  560  can effectively control the amount of current being drawn from the power supply. In this way, power saving may be realized by reducing the current usage in low power mode. 
         [0047]    In an alternative embodiment, differential input stage  700  can have multiple levels of cascode stages such as differential input stage  790 , shown in  FIG. 7B . Instead of having one level of parallely connected cascode stages, differential input stage  790  has two levels of cascode stages,  792  and  794 . In this way, the power output of differential input stage  790  can be more accurately controlled by turning on and off a certain amount of cascode branches within any level or by turning on and off the cascode branches of a level or levels as a whole. 
         [0048]      FIG. 8  illustrates the gain curve for power amplifier  580 . Line  804  shows the gain curve of power amplifier  580  in normal or high power mode with point  830  as the 6 dBm point. Line  806  shows the gain curve in low power mode with point  840  as the 0 dBm point. This translates into an overall low powered amplifying stage as opposed to driving a more powerful amplifying stage with less intensity as being implemented in the amplifying stage of  FIG. 4 . 
         [0049]    Even though the present invention is described in the context of npn transistors, it should be understood by one skilled in the art that other types of transistor could also be used to implement the invention. 
       Conclusion 
       [0050]    While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.