Abstract:
A method for data window centering a multifrequency data separator (12) based on having the frequency of a voltage-controlled oscillator (20) at least twice that of read data window frequency, and setting delay of a delay line (14) used in the data separating process so that arriving raw data pulses will be more accurately assigned to their corresponding windows. The method is realized by providing the multifrequency data separator with a phase comparator emulator (30) and a counter (28). According to another embodiment, the apparatus comprises a counter (28b) combined with a delay setting logic unit (40). The method and apparatus described above result in window centering which does not essentially depend on timing characteristics of circuitry used in the construction of the data separator.

Description:
BACKGROUND 
     Field of the Invention 
     The present invention relates to digital recording and data transmission, more particularly to a method for centering the data window in multifrequency data separators and to an apparatus for carrying out the method. Data separators are used for processing and recovering data read from various recording media, such as magnetic or optical, or received over transmission lines. 
     BACKGROUND OF THE INVENTION 
     The explanation of prior art is presented below with reference to FIGS. 1-5, wherein: 
     FIG. 1 is a diagram of a data separator typical of prior art. 
     FIG. 2A is a timing diagram of a typical transmitted data message. 
     FIG. 2B is a timing diagram of a received data message with jitter and ideal data window grid. 
     FIG. 2C is a timing diagram of a received data message with jitter and shifted window grid. 
     FIG. 2D is a timing diagram of a recovered data message. 
     FIGS. 3A, B, C, D, E, F, G, H, J, K, L, and P are timing diagrams illustrating the operation of the apparatus of FIG. 1. 
     FIGS. 4A, B, C, D, E, F, G, and H are timing diagrams illustrating the detection of raw read data pulses by the apparatus of FIG. 1 when its delay line setting is correct. 
     FIGS. 5A, B, C, D, E, F, G, and H are timing diagrams illustrating the detection of raw read data pulses by the apparatus of FIG. 1 when its delay line setting is incorrect. 
     The apparatus of FIG. 1, discussed below, is representative of the prior art but is not to be identified with any specific prior art reference. The description of this model data separator is intended to elucidate the data separator of the present invention. 
     Digital data transmission and reproduction processes involve noise, non-linearities, and bandwidth limitations (all such distortion hereafter referred to as noise) which could cause loss of information. Reading or receiving systems circuits which remove timing noise from the signal and make it available for further digital processing are called data separators. A typical data separator is shown in FIG. 1. The main purpose of data separators is to recover the original signal and present it in the form in which it was originally transmitted with the lowest probability of errors. 
     A typical serial data message consists of a preamble and a data transmission part. FIG. 2A shows an ideal transmitted message. The PREAMBLE portion of the message consists of n regularly spaced pulses with period T, namely P1, P2 . . . Pn, where n is an integer which is determined by the particular system. The pulses of the PREAMBLE carry timing synchronization information. 
     As can be seen from FIG. 2A, the time during which the message is transmitted can be subdivided into timing increments that will further be referred to as detents and characterized by detent frequency f d . In FIG. 2A the length of a detent is designated by T d . The leading edge of the preamble pulse P1 occurs exactly in the center of detent 1, and the leading edge of the preamble pulse P2 occurs exactly in the center of detent 3. Therefore, in this particular preamble pulses are spaced by two T d . 
     As shown in FIG. 2A the distance between the data pulses D1 and D2 is equal to three T d , and the distance between the data pulses D2 and D3 is equal to four T d , and every data pulse is generated exactly in the center of a detent. Any detent may contain a data pulse, and all generated data pulses have to be separated by an integer number of detents. Therefore, a detent is the minimum parcel of time in which the presence or absence of a pulse indicates a data bit. 
     FIG. 2B illustrates the message of FIG. 2A after it has been read or received. In the presence of noise, the distance in time between the received pulses of the preamble in this example will remain equal to two detents on the average. The timing positions when the pulses of the preamble are received are averaged over n pulses by a phase locked loop and the oscillator of the phase locked loop originates data windows. Pulses are recognized as belonging to a particular window when they arrive within plus or minus 1/2 of the detent from the center of the window. 
     If the center of the window is shifted right or left in time with respect to the statistical timing average of received data pulses, the probability of incorrect interpretation is increased. This condition is called incorrect window centering. It is illustrated in FIG. 2C. 
     In FIG. 2B, the received versin of the data pulse D1 arrives early within its ideal window IWD1. The window grid of FIG. 2B is centered correctly and this pulse is assigned to its proper window. The correctly assigned data pulse D1 can be seen in FIG. 2D which illustrates the received message after timing noise has been removed by a data separator. 
     The window grid of FIG. 2C is shifted off center. As a result the received version of D1 is assigned to the wrong window and an error results, as shown by the dashed line in FIG. 2D. 
     The model data separator of FIG. 1 consists of a phase locked loop, a delay line, a decoder, and control logic. The phase locked loop includes a phase comparator formed by the D flip-flops F1 and F2 and gate G2; flip-flop F3 which enables the phase comparator when the harmonic-lock signal is &#34;low&#34;; a voltage-controlled oscillator (VCO); a charge pump with a filter which translates the timing error outputs of the phase comparator into an analog signal which controls the VCO; and a binary divider flip-flop F5; a multiplexer M2 which selects either the output of the VCO (2F VCO, where 2F is the detent frequency or in alternative notation, f d ), or the output of flip-flop F5 (1F VCO, where 1F is 1/2 of the detent frequency) to be applied to the phase comparator. The operation of the decoder depends on the particular coding scheme and is not described in detail. The decoder provides two outputs, read data and read clock for further data processing. 
     The delay line is nominally set to 1/2 of the detent. Multiplexer M1 selects either raw read data signal or the output signal of an external reference phase lock oscillator (not shown), 1F PLO. The 1F PLO signal is used for the initial frequency setting of the VCO. 
     In the general case, the external reference phase lock oscillator frequency (here represented by the signal 1F PLO) is related to f d  by a factor 1/j, e.g. (1/j) F ref  =f d , where j is a positive integer. It is also possible to use reference signals for which the frequency is expressible as m/n f d  or (1/p) f d  to set the initial frequency of the VCO where m, n and q are positive integers. 
     In FIG. 3 some signals have only their triggering edges shown by vertical bars. 
     In the stand-by mode of operation the control signal LOCK-TO-PLO is set &#34;high&#34; (Sec. 1 of FIG. 3A) and, as a result the reference signal 1F PLO, alternate notation, f ref  (Sec. 1 of FIG. 3B) is selected to the input of the phase locked loop by multiplexer M1 (Sec. 1 of FIG. 3D). The control signal HARMONIC-LOCK is set &#34;low&#34; during this stage (Sec. 1 of FIG. 3Q). As a result, the 1F VCO signal (eg., 1/2 f d ) is selected to the clock CL input of the phase comparator flip-flop F2 by multiplexer M2 (Sec. 1 of FIG. 3K). The D input of flip-flop F2 is set &#34;high&#34; throughout the frequency lock stage (Sec. 1 of FIG. 3P). In this mode every 1F VCO rising edge is compared with every 1F PLO rising edge delayed by the delay line. As a result, the signals on the clock inputs of flip-flops F1 and F2 are aligned in frequency and phase as shown in Sec. 1 of FIGS. 3K and 3L. When the phase locked loop is in equilibrium, the UP and DOWN pulses are of the same length (Sec. 1 of FIGS. 3E and F). 
     In the general case the frequency of the signal here represented as 1F VCO may bear a relation to f d  as (1/p) f d , where p is a positive integer. 
     When an external controller (not shown) determines that the preamble of a raw read data message is being received, it sets the control signal LOCK-TO-PLO &#34;low&#34; as shown in Sec. 2 of FIG. 3A. This causes the raw read data signal to be applied to the input of the delay line (Sec. 2 of FIG. 3D). Even though the frequency of the VCO is equal to the frequency of the preamble pulses, their phases are not necessarily the same. In the case shown, this results in the UP pulses (Sec. 2 of FIG. 3E) being longer than the DOWN pulses (Sec. 2 of FIG. 3F). This causes a transient in the frequency of the VCO output which, when settled, results in the phases of the 1F VCO signal and the data pulses at the clock input of flip-flop F1 being aligned (Sec. 2 of FIGS. 3E and F). 
     When enough time has elapsed to achieve the proper phase alignment the HARMONIC-LOCK signal is set &#34;high&#34; (Sec. 3 of FIG. 3F). This results in the data or harmonic mode of operation of the phase locked loop. In this mode when a data pulse arrives and sets flip-flop F3 it enables a phase comparison between the delayed data pulse and the rising edge of the 2F VCO signal which is now being selected by multiplexer M2 (Sec. 3 of FIGS. 3K and L). 
     In the data message described by this example the end of the preamble is indicated by a change in pattern (Sec. 3 of FIG. 3C). Now data pulses may occur within any data window whose centers are indicated by   above Sec. 3 of FIG. 3C. Presence of a DOWN pulse at the end of a window indicates to the decoder that a data pulse has been recovered during that window. 
     The operation of the model data separator in this mode can be better described by referring to FIG. 4 which magnifies Sec. 3 of some of the timing diagrams of FIG. 3. In FIG. 4 all components of FIG. 1 are idealized. All gates have zero propagation delays; all flip-flops have zero set-up times; flip-flop F3 has zero propagation delay between the clock input and the output Q; flip-flops F1 and F2 have equal propagation delays between their respective clock inputs and outputs Q; and the charge pump is symmetrical. The window grid at the top of FIG. 4 has windows numbered from 1 to 17. 
     The delay between the time when flip-flop F2 is enabled by an arriving data pulse (which sets flip-flop F3) and when flip-flop F1 is clocked is set to 1/2 of the detent by the delay line. 
     In FIG. 4A all raw read data pulses except for DP2 are shown arriving without jitter. That is, the rising edges of these pulses, excepting DP2 are aligned with the centers of the windows. When the data pulse DP1 arrives, it sets flip-flop F3 (FIG. 4B) thereby enabling the phase comparison. Its delayed version (FIG. 4C) is compared with the rising edge of the 2F VCO signal (FIG. 4D) resulting in equal UP and DOWN pulses (FIGS. 4F and G). 
     The data pulse DP2 is late in its data window 15 (FIG. 4A). Because the leading edge of the DOWN pulse or recovered data occurs during the correct data window the decoder is able to correctly assign pulse DP2. 
     An example of data processing when the delay of the delay line is set shorter than 1/2 of the detent by the amount T err  is shown in FIG. 5. The timing positions of signals in the case of the correct delay setting are indicated by dashed lines. There are two window grids at the top of FIG. 5. One of them corresponds to the correct delay setting and is the same as in FIG. 4. The other one corresponds to the incorrect delay of FIG. 5 and is shifted with respect to the correct window grid by the amount T err . 
     The data pulse DP1A arrives without jitter (FIG. 5A) and is correctly decoded. The data pulse DP2A (FIG. 5A) arrives later than the statistical average of the previous data pulses by less than than 1/2 of the detent. That places it within correct window 15. If the window setting is shifted due to incorrect setting of the delay line, the enabling flip-flop F3 is not set early enough for the rising edge of the 2F VCO signal corresponding to window 15 (FIG. 5D) to set flip-flop F2. This results in the flip-flop F2 being set by the following rising edge of the 2F VCO signal and the DOWN pulse or normalized data is erroneously identified with window 16 instead of 15, e.g., an error. 
     Therefore, it has been demonstrated that the correct setting of the delay of the delay line is very important in the typical prior art data separator represented by the model apparatus of FIG. 1. In practice, all gates and flip-flops have non-zero set-up times and propagation delays, and these cannot be completely matched among different gates and flip-flops. As a result, the optimum setting of the delay of the delay line depends on the particular components used. However, conventional data separators have no internal means to monitor the correctness of the setting of the delay line, i.e., they have no internal means for window centering. To set the delay line, for example, one would have to produce a data signal with simulated jitter and look for a setting of the delay line resulting in the least number of errors. This method is cumbersome because it requires a calibrating signal and procedure and is difficult to automate. 
     In practice conventional methods such as the one described above have never been completely successful in digital recording/reproducing systems such as magnetic disk drives or the like. As a result, the effective window margin is reduced. This imposes stringent bit jitter tolerances on drive mechanisms, thereby making these devices more expensive to manufacture. 
     With increased speeds of digital data transmission in modern data recording/reproducing systems, the size of the window has become about the same order of magnitude as time delays or timing parameters of devices used in the circuitry of data separators. Thus window centering has become the &#34;bottle neck&#34; of the industry because of the necessity to utilize devices with constantly increasing accuracy of matching. In practice this is not achievable in mass production. 
     This problem becomes even more complicated in systems with variable recording frequencies because in such systems window centering has to be done every time the frequency is changed. 
     Therefore there is a demand in the industry for data separators equipped with improved means for data window centering. 
     Objects and Advantages 
     Accordingly, it is an object of the present invention to provide a method for data window centering in a multi-frequency data separator essentially without relying on time delays and timing parameters of devices used in its construction. Another object is to provide a method for data window centering which is characterized by high accuracy, reliability and improved noise immunity. Still another object is to provide a simple and reliable apparatus for carrying out the above-mentioned method. Other objects and advantages of the invention will be apparent to those skilled in the art from the ensuing description and accompanying drawings. 
     The Essence of the invention 
     The essence of the invention is compactly described as follows. For centering of the window of a data separator, a reference crystal controlled signal is applied to its data input. Two sets of windows are generated. The first one for data processing, as described in the background section above and the second one advanced with respect to the first one by 1/2 of the detent interval T d . Centering of the window is performed by automatically adjusting the relative time delay between the two window sets while referencing the data pulses with respect to the shifted window set. 
    
    
     DRAWINGS REPRESENTATIVE OF THE INVENTION 
     FIG. 6 is an embodiment of an apparatus for realization of the method of the present invention. 
     FIGS. 7A, B, C, D, E, F, G, H, J, K, L, P, Q, and R are timing diagrams illustrating the operation of the apparatus of FIG. 6. 
     FIG. 8 is another embodiment of an apparatus of the invention. FIGS. 9A, B, C, D, E, F, G, H, J, K, L, P, Q, R, S, and T are timing diagrams illustrating the operation of the apparatus of FIG. 8. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention can be realized by means of an apparatus shown in FIG. 6. In the description of the apparatus of the invention those parts which are similar to corresponding parts of conventional apparatus of FIG. 1 are designated by the same reference numerals but with addition of suffix &#34;a&#34;. 
     The apparatus comprises a data separator designated generally by reference numeral 12. Data separator 12 comprises a phase comparator 13 (described in detail later) which compares the raw read data stream coming from read circuitry (not shown) or a signal from a phase lock oscillator (PLO) (also not shown in the drawings) through a multiplexer M1a and a delay line 14 with the phase or frequency of a voltage-controlled oscillator (VCO) 20. The VCO suitable for the purpose of the present invention may be one described in MECL Device Data Book, Motorola Inc., 1983, p. 4-3. Multiplexer M1a is controlled by the LOCK-TO-PLO input from external control circuitry (not shown). The UP and DOWN outputs of phase comparator 13 are connected to a charge pump 22. A suitable charge pump, whose operation is not described in detail, is shown in FIG. 10. It comprises two differential pairs controlled by buffer gates G20 and G21 each of which has inputs 1 and 2 and outputs 3 and 4. The first differential pair comprises two PNP transistors Q2 and Q3. They are biased by a current source formed by a PNP transistor Q1 and resistor R6. The bases of tranistors Q2 and Q3 are connected to outputs 4 and 3 respectively of gate G20 which buffers the UP signal. 
     The second differential pair comprises two NPN transistors Q4 and Q5. 
     They are biased by a current source formed by an NPN transistor Q6 and a resistor R5. The base of transistor Q4 is connected to the anode of a Zener diode CR2 and to a resistor R4. The base of transistor Q5 is connected to the anode of a Zener diode CR1 and to a resistor R3. The cathodes of diodes CR1 and CR2 are connected to outputs 4 and 3 respectively of gate G21 which buffers the DOWN signal. 
     The collector of transistor Q2 is connected to the -5.2 V power supply and the collector of transistor Q4 is connected to ground. The collectors of transistors Q3 and Q5 are connected together. 
     The output of charge pump 22 is connected to a filter 24 which is also shown in FIG. 10. It comprises a frequency-response shaping network consisting of capacitors C3 and C4 and a resistor R7 as well as a level shifting amplifier comprising an operational amplifier OPAMP1 (such as an LF353 manufactured by the National Semiconductor Corp.) and resistors R9 and R8 and a potentiometer R10. The operation of filter 24 is not described as it is known to a person skilled in the art. 
     Referring back to FIG. 6, the output of filter 24 is connected to the input of VCO 20. The DOWN output of phase detector 13 is connected to a decoder 26 which converts the detected data into the NRZ format. The decoder can be of any type suitable for this purpose. It could, for instance, be an MFM or a run length limited code decoder. The technique of construction of such decoders is known to a person skilled in the art. The output of VCO 20 is applied to a counter 28 which is formed by flip-flops F5a and F6 (each of which has a D input, clock CL input, and positive and negative Q outputs), gates G6, G7 and G8 (each of which has inputs 1 and 2, and an output 3) and a muliplexer M2a. 
     More specifically, the output of VCO 20 is connected to the clock CL input of flip-flop F5a and input 2 of gate G8. The input D of flip-flop F5a is connected to its negative Q output as well as to input 2 of gate G7 and input 1 of multiplexer M2a. The output Q of flip-flop F5a is connected to input 1 of gate G8 as well as to input 2 of gate G6 and to decoder 26. Output 3 of gate G8 is connected to clock CL input of flip-flop F6. The negative Q output of flip-flop F6 is connected to its D input as well as to input 1 of gate G7 and input 1 of gate G6. The output 3 of gate G6 is connected to input 0 of multiplexer M2a. The output of multiplexer M2a is connected to input 1 of gate G3 of phase comparator 13. Multiplexer M2a is controlled by the HARMONIC-LOCK signal. The output 3 of gate G7 is connected to input 2 of gate G4 of an emulator 30 which is described in detail later. 
     Now phase comparator 13 will be described in detail. It consists of flip-flops F1a, F2a and F3a (each of which has a D input, clock CL input, reset R input and an output Q), gates G1a, G2a and G3 each of which has inputs 1 and 2 and an output 3. The UP output of flip-flop F1a is connected to input 1 of gate G2a. The DOWN output of flip-flop F2a is connected to input 2 of gate G2a. Output 3 of gate G2a is connected to the reset R inputs of flip-flops F1a, F2a and F3a. The D input of flip-flop F3a is held &#34;high&#34; and the clock input of flip-flop F3a is connected to the output of multiplexer M1a. The Q output of flip-flop F3a is connected to input 2 of gate G1a. Input 1 of gate G2a is connected to output 2 of inverter INV1a wich inverts the harmonic-lock signal. Output 3 of gate G1a is connected to the D input of flip-flop F2a and to the D input of flip-flop F4 of emulator 30. Output 3 of gate G3 is connected to the clock CL input of flip-flop F2a. The D input of flip-flop F1a is held &#34;high&#34;. The clock input of flip-flop F1a is connected to the output of a delay line 14. 
     Gate G4 (which has inputs 1 and 2, and an output 3) and flip-flop F4 (having a D input, clock CL input, and an output Q) form emulator 30 for gates G3 and flip-flop F2a respectively of phase comparator 13. Input 1 of gate G4 is connected to the 4F VCO output of VCO 20 as well as to input 2 of gate G3 of phase comparator 13. Output 3 of gate G4 is connected to the clock CL input of flip-flop F4. The Q output of flip-flop F4 is connected to inputs 1 and 2 of a gate G5 of a feedback averaging unit 32 which will now be described. 
     Outputs 3 of gate G5 is connected to an integrator formed by a resistor R1 and a capacitor C1. Output 4 of gate G5 is connected to an integrator formed by a resistor R2 and a capacitor C2. The two filters are in turn connected to the positive and negative inputs respectively of a comparator COMP1 (which could be an LM392 comparator manufactured by the National Semiconductor Corp.). 
     The averaged feedback output of comparator COMP1 is applied to a delay line control 16 which also accepts the SET-WINDOW signal from an external controller (not shown) applied to it. 
     The operation of the apparatus of FIG. 6 is described with reference to the timing diagram (FIG. 7) of the data window centering sequence according to the method of the invention. In this description charge pump 22 is assumed to be symmetrical. 
     The apparatus of FIG. 6 has internal capabilities to monitor the correctness of the setting of delay line 14 by means of flip-flop F4 and gate G4. 
     The sequence of window centering occurs as follows: 
     First, the period of the 4F VCO signal (FIG. 7A) is set to 1/2 of the detent by phase and frequency locking the VCO to the external signal 1F PLO (FIG. 7F). The frequency lock mode is set by setting the control signal HARMONIC-LOCK &#34;low&#34; and setting the control signal LOCK-TO-PLO &#34;high&#34;. In this case phase comparator flip-flop F2a is clocked by the output signal of gate G6 of counter 28 having freqency 1F (FIG. 7E) selected by multiplexer M2a and strobed by the leading edge of the 4F VCO signal. 
     The HARMONIC-LOCK signal is then set &#34;high&#34; resulting in the data or harmonic mode of operation (described earlier for the apparatus of FIG. 1) and in flip-flop F2a being clocked by the negative 2F VCO signal (FIG. 7B) selected by multiplexer M2a and strobed by the leading edge of the 4F VCO signal. 
     Flip-flop F4 of emulator 30 is clocked by the output signal of gate G7 of counter 28 having frequency 1F (FIG. 7D) strobed by the leading edge of the 4F VCO signal. As can be seen by comparing FIGS. 7J and 7Q, flip-flop F4 is clocked exactly 1/2 of the detent interval earlier than flip-flop F2a. 
     The control signal SET-WINDOW is then set &#34;high&#34;. As a result, delay line control 16 sets the delay of delay line 14 to the minimum value. The phase-locked loop aligns the signals on the clock inputs of phase comparator flip-flops F1a and F2a as can be seen from the INITIAL DELAY section of FIGS. 7G and J. 
     If the delay of delay line 14 is set short, the D input of flip-flop F4 is low when its clock signal arrives (INITIAL DELAY and SHORT DELAY sections of FIGS. 7H and Q). Therefore, the FEEDBACK output of flip-flop F4 remains &#34;low&#34; (INITIAL DELAY and SHORT DELAY sections of FIG. 7R). The AVERAGED FEEDBACK output of comparator COMP1 also remains &#34;low&#34; indicating to delay line control 16 that the delay of delay line 14 has to be increased. 
     Delay line control 16 increases the delay slowly enough to allow the phase-locked loop to realign the signals on the clock inputs of phase comparator flip-flops F1a and F2a. When that delay is increased just to the point where the D input of flip-flop F4 becomes &#34;high&#34; early enough to enable the setting of flip-flop F4 (CORRECT DELAY section of FIGS. 7H and Q), flip-flop F4 gets set intermittently, as determined by the system noise (CORRECT DELAY section of FIG. 7R). The FEEDBACK output of flip-flop F4 is bufferred by gate G5 and sent to comparator COMP1 through integrators formed by R1 and C1 and by R2 and C2. The averaged feedback output is &#34;high&#34; if the feedback signal is &#34;high&#34; more than 50% of the time, and &#34;low&#34; if the feedback signal is &#34;low&#34; more than 50% of the time. This mode of operation results in the FEEDBACK signal being &#34;high&#34; essentially 50% of the time indicating that proper window centering is achieved. 
     For the purposes of illustration, the case of setting the delay too long is also illustrated. In this case the FEEDBACK output of flip-flop F4 remains high as illustrated in the LONG DELAY section of FIG. 7R. Therefore in this case the delay has to decreased to achieve window centering. 
     Two sets of windows are generated during the sequence of window centering described above. The first one is generated by the signal clocking phase comparator flip-flop F2a, and it is used for data processing. The second one is generated by the signal clocking phase comparator emulator flip-flop F4, and it is advanced with respect to the first one by exactly 1/2 of the detent. As shown, centering of the first window was judged by the timing of the reference signal with respect to the advanced window in accordance with the method of the invention. 
     The accuracy of window centering in the apparatus of FIG. 6 depends on matching the D input setup times of flip-flops F2a and F4 and on matching the propagation delays of gates G3 and G4. Tight matching can be obtained by using, for example, an ECL integrated circuit, MC10131, manufactured by Motorola Inc., which contains two D-type flip-flops and two OR gates. 
     The apparatus of FIG. 6 is an attractive embodiment of the method of the invention because of the simplicity of additional circuit components compared with traditional data separators. 
     In general, the signal produced for clocking F4 (FIG. 7Q) may exhibit a frequency of j/q f d  where q is a positive integer less than (or equal to) j, j is a positive integer as hereinbefore set forth and j is an integer multiple of q. Similarly for the general case, the signal apllied to F2A (FIG. 7J) may exhibit a frequency of (j/k) f d , where k is a positive integer less than (or equal to) j and j is an integer multiple of k. 
     The method of the present invention can also be realized with the use of an apparatus shown in FIG. 8. In FIG. 8 those parts and elements which correspond to similar parts and elements of FIG. 6 are designated by the same reference numerals but with an addition of suffix &#34;b&#34;. 
     The apparatus comprises a data separator designated generally by reference numeral 12b. The data separator comprises a phase comparator 13b (described in detail later) which compares the raw read data stream coming from read circuitry (not shown) or from a phase lock oscillator (PLO) (also not shown in the drawings) through a multiplexer M1b with the phase or frequency of a voltage-controlled oscillator (VCO) 20b. The VCO can be the same as described above in connection with the apparatus of FIG. 6. Multiplexer M1b is controlled by the LOCK-TO-PLO input from external control circuitry (not shown). 
     Outputs 3 of gates G10 and G11 of phase detector 13b are connected to charge pump 22b which in turn is connected to a filter 24b. Filter 24b is connected to VCO 20b. The DOWN output of phase detector 13b is connected to a decoder 26b which converts the detected data into the NRZ format. The decoder can be the same as the one mentioned above in connection with apparatus of FIG. 6. The output of VCO 20b is connected to a counter 28b which is formed by flip-flops F5b and F6b, gates G6b, G7b and G8b and multiplexer M2b and M3. The above-mentioned elements are of the same type used in counter 28a described in connection with FIG. 6, i.e., they have similar inputs, outputs, etc. The only difference between counters 28a and 28b is that an additional multiplexer M3 is introduced into counter 28b. The output of multiplexer M2b is connected to input 1 of multiplexer M3 and the output 3 of gate G7b is connected to input 0 of multiplexer M3. The output of multiplexer M3 is connected to input  1 of gate G3b of phase comparator 13b which will now be described. 
     Phase comparator 13b consists of flip-flops F1b, F2b and F3b as well as gates G1b, G2b, G3b, G9, G15, G10 and G11. The UP output of flip-flop F1b is connected to input 1 of gate G10, input 1 of gate G2b as well as to input 1 of gate G12 of delay setting logic unit 40. The DOWN output of flip-flop F2b is connected to input 1 of gate G11 as well as to input 2 of gate G2b and the D input of flip-flop F12 of delay setting unit 40 which will be described later. Output 3 of gate G2b is connected to input 1 of gate G15. Input 2 of gate G15 is connected to output 3 of gate G12 as well as to CL clock of flip-flop F12 and input 1 of a buffer BUF1 of a delay setting logic unit 40. Output 3 of gate G15 is connected to reset R inputs of flip-flops F1b, F2b, and F3b as well as to input 1 of inverter INV2 of delay logic unit 40. Inputs 2 of gates G10 and G11 are connected to each other and to the negative Q output of flip-flop F11 of delay setting logic unit 40. 
     The D input of flip-flop F3b is &#34;held&#34; high and the clock CL input of flip-flop F3b is connected to the output of multiplexer M1b as well as to delay line 14b. The Q output of flip-flop F3b is connected to input 2 of gate G1b. Input 1 of gate G1b is connected to output 3 of gate G9. Output 3 of gate G1b is connected to the D input of flip-flop F2b while the clock CL input of flip-flop F2b is connected to output 3 of gate G3b. Input 2 of gate G3b is connected to the output of VCO 20b. The D input of flip-flop F1b is held &#34;high&#34; whereas the clock CL input of flip-flop F1b is connected to the output of delay line 14b. 
     Now the above-mentioned delay setting logic unit (40) will be described. It comprises: a modulo N counter C1 having a clock CL input, an enable G input, and a carry out CO output; flip-flops F10, F11 and F12; and gate G12. The Q output of flip-flop F10 is connected to input D of flip-flop F11. The D input of flip-flop 10 is held &#34;high&#34;. The clock CL input of flip-flop F10 is connected to carry out CO output of counter C1. The clock CL input of counter C1 is connected to 1F PLO signal similar to the one described in connection with FIG. 6. The SET-WINDOW signal is applied to the enable G input of counter C1, to the delay line control 16b, and to input 1 of gate G9. This SET-WINDOW signal may be supplied from an external source such as a computer (not shown). 
     The clock CL input of flip-flop F11 is connected to output 2 of inverter INV2. The output Q of flip-flop F11 is connected to input 2 of gate G12 as well as to the control input of multiplexer M3 of counter 28b. The output 2 of buffer BUF1 is connected to input 1 of buffer BUF2. The output 2 of buffer BUF2 is connected to the reset R inputs of flip-flops F10 and F11. The output Q of flip-flop F12 is connected to the second input of delay line control 16b. 
     The LOCK-TO-PLO signal coming from the external control circuitry (not shown) is connected to the control input of multiplexer M1b. The HARMONIC-LOCK signal also coming from the external control circuitry is connected to input 2 of gate G9 and the control input of multiplexer M2b. 
     Two external signals (1F PLO and raw read data) coming from the external control circuitry (not shown) are applied to the inputs of  multiplexer M1b. 
     The connections between charge pump 22b, filter 24b, and VCO 20b are the same as between the corresponding units of the apparatus shown in FIG. 6. 
     The apparatus of FIG. 8 is similar in principle of operation to that of FIG. 6. It has a more complicated control system and its data window centering sequence is slower, but it offers absolute accuracy which does not depend on the matching of timing characteristics of circuit components. 
     The sequence of window centering occurs as follows: 
     First, the period of the 4F VCO signal (FIG. 9A) is set to 1/2 of the detent by phase and frequency locking the VCO to the external signal 1F PLO (FIG. 9D). The frequency lock mode is set by setting the control signals HARMONIC-LOCK and SET-WINDOW &#34;low&#34; and setting the control signal LOCK-TO-PLO &#34;high&#34;. In this case phase comparator flip-flop F2b is clocked by the output signal of gate G6b of counter 28b having frequency 1F (FIG. 9B) selected by multiplexers M2b and M3 and strobed by the leading edge of the 4F VCO signal. 
     The control signal SET-WINDOW is then set &#34;high&#34; resulting in the following conditions: 
     (a) data or harmonic mode of operation described earlier for the apparatus of FIG. 1; 
     (b) enabling of modulo N counter C1; 
     (c) delay line control 16 setting the delay of delay line 14 to the minimum value. 
     The phase-locked loop aligns the signals on the clock inputs of phase comparator flip-flops F1b and F2b as can be seen from the PHASE LOCKING section of FIGS. 9E and F. 
     To verify the correctness of window centering, after N pulses of the 1F PLO signal following the setting of control signal SET-WINDOW &#34;high&#34;, the carry output (SAMPLE output) of counter C1 becomes high (START SAMPLING section of FIG. 9L) and thereby sets flip-flop F10 (START SAMPLING section of FIG. 9P). Then the inverted (by inverter INV2) falling edge of the COMPARATOR-RESET signal (START SAMPLING section of FIG. 9T) sets flip-flop F11 (START SAMPLING section of FIG. 9Q) thereby initiating the following conditions: 
     (a) Charge pump 22b is set on hold as a result of a &#34;low&#34; signal being applied to inputs 2 of gates G10 and G11; 
     (b) Multiplexer M3 selects the output signal of gate G6b (FIG. 9B) instead of the output signal of gate G7b (FIG. 9C) to input 1 of gate G3B. 
     The output signal of gate G6b, having frequency 1F, is advanced by 1/2 of the detent with respect to the 1F frequency output signal of gate G7b. The output signal of gate G7b generates a window set for data processing and the output signal of gate G6b generates a window set advanced by 1/2 of the detent with respect to the first one. To achieve the shift of exactly 1/2 of the detent, the signals on input 1 of gate G3b are strobed by the leading edge of the 4F VCO signal. 
     If the delay of delay line 14b is shorter than required for proper window centering, then the DOWN output of flip-flop F2B (shown by the solid line in the SAMPLING section of FIG. 9J) will remain low. This DOWN pulse is applied to the D input of flip-flop F12, whose FEEDBACK output signal will remain &#34;low&#34; (shown by the solid line in the SAMPLING section of FIG. 9R) when clocked by the following UP pulse (SAMPLING section of FIG. 9H) through the output of gate G12 (SAMPLING section of FIG. 9S). This UP pulse resets flip-flops F10 and F11 through gate G12 and buffers BUF1 and BUF2 thereby finishing the sampling operation and returning the phase locked loop to the normal mode of operation. The sampling operation can be repeated as many times as necessary. 
     The &#34;low&#34; state of the FEEDBACK signal indicates that the delay of delay line 14b needs to be increased. It is increased step by step by delay line control 16b, allowing the phase locked loop to realign the signals on the clock inputs of phase comparator flip-flops F1b and F2b. 
     When in a particular setting of delay line 14b the FEEDBACK signal will alternate between &#34;high&#34; and &#34;low&#34; states with a 50% probability (shown by the dashed line in the SAMPLING section of FIG. 9R), the delay line setting is correct and windows are centered. 
     Conclusion, Ramification and Scope 
     Thus it has been shown that a method and apparatus of the present invention provide for centering the data window in a multifrequency data separator which essentially does not depend on time delays and timing parameters of devices used in its construction. In addition, the method and apparatus are characterized by high accuracy, reliability and improved noice immunity. 
     Although the invention has been described and shown with reference to specific circuits and circuit components, as far as we know, window centering of all known data separators can be verified by creating a window shifted by 1/2 of the detent. Thus, the scope of the invention should be determined, not by the examples given, but by appended claims and their legal equivalents.