Abstract:
There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line includes a first multiplexer for multiplexing the data and supplying a first multiplexed data to the global I/O line and a second multiplexer for multiplexing the first multiplexed data supplied to the global I/O line, wherein the first and second multiplexers are formed at either side of the global I/O line.

Description:
This application is a continuation of U.S. patent application Ser. No. 11/529,286 filed on Sep. 29, 2006 now U.S. Pat. No. 7,577,038, which claims priority of Korean patent application number 10-2005-0091548 filed on Sep. 29, 2005 and Korean patent application number 10-2006-0049113 filed on May 31, 2006. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a semiconductor design technology; and, more particularly, to a multiplexer for multiplexing input/output data. 
     DESCRIPTION OF RELATED ART 
     Recently, a semiconductor device is designed such that it has an input/output path of multi-bit structure according to a data option mode for increasing data transmission rate. Herein, the data option mode, e.g., x4, x8, x16, etc, represents the number of data bits which are simultaneously read from or written onto a memory at one-time addressing. Thus, semiconductor devices may be differently configured even though they have the same capacity. That is, ‘x4’, ‘x8’, and ‘x16’ operation modes mean that the semiconductor devices have 4-bit, 8-bit and 16-bit architecture, respectively. Therefore, after the semiconductor device is fabricated such that it satisfies all of the ‘x4’, ‘x8’, and ‘x16’ operation modes, the semiconductor device is constructed such that it operates in the ‘x4’, ‘x8’, or ‘x16’ operation mode according to a selected option. 
       FIGS. 1A to 1C  are block diagrams showing a conventional flow of data multiplexed according to ‘x4’, ‘x8’, and ‘x16’operation modes. 
     For the sake of illustrative convenience, global input/output (I/O) lines GIO_L&lt;0:7&gt; and GIO_U&lt;0:7&gt; are divided into bottom global I/O lines GIO_L&lt;0:7&gt;, and upper global I/O lines GIO_U&lt;0:7&gt;. Likewise, data input/output (I/O) pads LDQ&lt;0:7&gt; and UDQ&lt;0:7&gt; are divided into bottom data I/O pads LDQ&lt;0:7&gt; and upper data I/O pads UDQ&lt;0:7&gt;. Also, local input/output (I/O) lines LIO_L&lt;0:7&gt; and LIO_U&lt;0:7&gt; are divided into bottom local I/O lines LIO_L&lt;0:7&gt;, and upper local I/O lines LIO_U&lt;0:7&gt;. 
     Referring to  FIGS. 1A to 1C , input/output data of the semiconductor device are transferred via each different data path according to the ‘x4’, ‘x8’, and ‘x16’ operation modes. Referring to  FIG. 1A , in case of inputting the data in the ‘x16’ operation mode, the data are transferred to respective local I/O lines LIO_L&lt;0:7&gt; and LIO_U&lt;0:7&gt; through respective global I/O lines GIO_L&lt;0:7&gt; and GIO_U&lt;0:7&gt; corresponding to respective data I/O pads LDQ&lt;0:7&gt; and UDQ&lt;0:7&gt;. Conversely, in case of outputting the data in the ‘x16’ operation mode, the data of the respective local I/O lines LIO_L&lt;0:7&gt; and LIO_U&lt;0:7&gt; are outputted to the respective data I/O pads LDQ&lt;0:7&gt; and UDQ&lt;0:7&gt; through the respective corresponding global I/O lines GIO_L&lt;0:7&gt; and GIO_U&lt;0:7&gt;. 
     Referring to  FIG. 1B , in case of inputting the data in the ‘x8’ operation mode, 8-bit data inputted through the bottom data I/O pads LDQ&lt;0:7&gt; are applied to the bottom global I/O lines GIO_L&lt;0:7&gt; or the upper global I/O lines GIO_U&lt;0:7&gt; in response to a row address signal RA&lt;13&gt;. Thereafter, the data supplied to the bottom global I/O lines GIO_L&lt;0:7&gt; or the upper global I/O lines GIO_U&lt;0:7&gt; are transferred to the corresponding bottom local I/O lines LIO_L&lt;0:7&gt; or upper local I/O lines LIO_U&lt;0:7&gt;. Contrariwise, in case of outputting the data in the ‘x8’ operation mode, the 8-bit data supplied to the bottom or upper local input output lines LIO_L&lt;0:7&gt; or LIO_U&lt;0:7&gt; are applied to the corresponding bottom or upper global I/O lines GIO_L&lt;0:7&gt; or GIO_U&lt;0:7&gt; and thereafter, they are outputted to the bottom data I/O pads LDQ&lt;0:7&gt;. 
     Referring to  FIG. 1C , in case of inputting the data in the ‘x4’ operation mode, 4-bit data may be applied to the respective global I/O lines GIO_L&lt;0:3&gt;, GIO_L&lt;4:7&gt;, GIO_U&lt;0:3&gt;, or GIO_U&lt;4:7&gt; in response to a row address signal RA&lt;13&gt; and a column address signal CA&lt;11&gt;. Thereafter, the applied 4-bit data are transferred to the corresponding local I/O lines LIO_L&lt;0:3&gt;, LIO_L&lt;4:7&gt;, LIO_U&lt;0:3&gt; or LIO_U&lt;4:7&gt; through the respective global I/O lines GIO_L&lt;0:3&gt;, GIO_L&lt;4:7&gt;, GIO_U&lt;0:3&gt;, or GIO_U&lt;4:7&gt;. Conversely, in case of outputting the data in the ‘x4’ operation mode, the 4-bit data supplied to the respective local I/O lines LIO_L&lt;0:3&gt;, LIO_L&lt;4:7&gt;, LIO_U&lt;0:3&gt; or LIO_U&lt;4:7&gt; are applied to the corresponding global I/O lines GIO_L&lt;0:3&gt;, GIO_L&lt;4:7&gt;, GIO_U&lt;0:3&gt;, or GIO_U&lt;4:7&gt;, and the data are then outputted to the bottom data I/O pads LDQ&lt;0:3&gt;. 
       FIG. 2A  is a block diagram illustrating a conventional input multiplexer  10 . 
     Referring to  FIG. 2A , 4-bit, 8-bit or 16-bit data inputted according to the data option mode, i.e., the ‘x4’, ‘x8’, or ‘x16’ operation mode, are inputted into the conventional input multiplexer  10  through the data I/O pads LDQ&lt;0:7&gt; and UDQ&lt;0:7&gt;. The conventional input multiplexer  10  applies the data to predetermined global I/O lines GIO_L&lt;0:7&gt; and GIO_U&lt;0:7&gt;, and transfers the data to corresponding local I/O lines LIO_L&lt;0:7&gt; and LIO_U&lt;0:7&gt; through the global I/O lines GIO_L&lt;0:7&gt; and GIO_U&lt;0:7&gt;. 
       FIG. 2B  is a block diagram illustrating a conventional output multiplexer  20 . 
     Referring to  FIG. 2B , the 4-bit, 8-bit or 16-bit data to be outputted from the local I/O lines LIO_L&lt;0:7&gt; and LIO_U&lt;0:7&gt; are applied to the global I/O lines GIO_L&lt;0:7&gt; and GIO_U&lt;0:7&gt; which are correspondingly connected to the local I/O lines LIO_L&lt;0:7&gt; and LIO_U&lt;0:7&gt;. The conventional output multiplexer  20  selects the global I/O lines GIO_L&lt;0:7&gt; and GIO_U&lt;0:7&gt; to which the data have been applied, and outputs the data through the corresponding data I/O pads LDQ&lt;0:7&gt; and UDQ&lt;0:7&gt;. 
       FIG. 3  is a block diagram illustrating the conventional input multiplexer  10  shown in  FIG. 2A . In  FIG. 3 , there is illustrated only a representative portion of the conventional input multiplexer  10 . That is, in the conventional input multiplexer  10 , there are employed an input multiplexer  11  corresponding to a zeroth bottom data I/O pad LDQ&lt;0&gt; of the bottom data I/O pads LDQ&lt;0:7&gt;, an input multiplexer  12  corresponding to a fourth bottom data I/O pad LDQ&lt;4&gt;, and drivers DRV 7  and DRV 8  corresponding to zeroth and fourth upper data I/O pads UDQ&lt;C&gt; and UDQ&lt;4&gt; of the upper data I/O pads UDQ&lt;0:7&gt;. Herein, although the input multiplexer  11  corresponding to the zeroth data I/O pad LDQ&lt;0&gt; has the same configuration as other input multiplexers (not shown) which are correspondent to first to third bottom data I/O pads LDQ&lt;1:3&gt;, they are connected to respective different global I/O lines. In detail, the outputs of the multiplexer  11  corresponding to the zeroth data I/O pad LDQ&lt;0&gt; are connected to the global I/O lines GIO_L&lt;0&gt;, GIO_L&lt;4&gt;, GIO_U&lt;0&gt; and GIO_U&lt;4&gt;, respectively. The outputs of the multiplexer (not shown) corresponding to the first bottom data I/O pad LDQ&lt;1&gt; are connected to the global I/O lines GIO_L&lt;1&gt;, GIO_L&lt;5&gt;, GIO_U&lt;1&gt; and GIO_U&lt;5&gt;, respectively. Likewise, the outputs of the multiplexer (not shown) corresponding to the second bottom data I/O pad LDQ&lt;2&gt; are connected to the global I/O lines GIO_L&lt;2&gt;, GIO_L&lt;6&gt;, GIO_U&lt;2&gt; and GIO_U&lt;6&gt;, respectively. The outputs of the multiplexer (not shown) corresponding to the third bottom data I/O pad LDQ&lt;3&gt; are connected to the global I/O lines GIO_L&lt;3&gt;, GIO_L&lt;7&gt;, GIO_U&lt;3&gt; and GIO_U&lt;7&gt;, respectively. 
     In addition, although the input multiplexer  12  corresponding to the fourth data I/O pad LDQ&lt;4&gt; has the same configuration as other input multiplexers (not shown) which are correspondent to fifth to seventh bottom data I/O pads LDQ&lt;5:7&gt;, they are connected to respective different global I/O lines. That is, the outputs of the multiplexer  12  corresponding to the LDQ&lt;4&gt; are connected to the global I/O lines GIO_L&lt;4&gt; and GIO_U&lt;4&gt;, respectively. The outputs of the multiplexer (not shown) corresponding to the fifth bottom data I/O pad LDQ&lt;5&gt; are connected to the global I/O lines GIO_L&lt;5&gt; and GIO_U&lt;5&gt;, respectively. The outputs of the multiplexer (not shown) corresponding to the sixth bottom data I/O pad LDQ&lt;6&gt; are connected to the global I/O lines GIO_L&lt;6&gt; and GIO_U&lt;6&gt;, respectively. Likewise, the outputs of the multiplexer (not shown) corresponding to the seventh bottom data I/O pad LDQ&lt;7&gt; are connected to the global I/O lines GIO_L&lt;7&gt; and GIO_U&lt;7&gt;, respectively. Similarly, the outputs of the drivers corresponding to the upper data I/O pads UDQ&lt;0:7&gt; are connected to the corresponding upper global I/O lines GIO_U&lt;0:7&gt;, respectively. 
     The input multiplexer  11 , which is configured with four drivers DRV 1 , DRV 2 , DRV 3  and DRV 4  for receiving respective control signals A, B, C and D therethrough, applies the data to one of the global I/O lines GIO_L&lt;0&gt;, GIO_L&lt;4&gt;, GIO_U&lt;0&gt; and GIO_U&lt;4&gt; in response to the control signal A, B, C or D. That is, the input data applied through the zeroth bottom data I/O pad LDQ&lt;0&gt; are applied to the zeroth and fourth bottom global I/O lines GIO_L&lt;0&gt; and GIO_L&lt;4&gt; in response to the control signals A and B, respectively. Similarly, the input data applied through the zeroth bottom data I/O pad LDQ&lt;0&gt; are applied to the first and fourth upper global I/O lines GIO_U&lt;0&gt; and GIO_U&lt;4&gt; in response to the control signals C and D, respectively. 
     The input multiplexer  12  corresponding to the fourth bottom data I/O pad LDQ&lt;4&gt;, which is configured with two drivers DRV 5  and DRV 6  for receiving control signals E and F, respectively, applies the data to one of the global I/O lines GIO_L&lt;4&gt; and GIO_U&lt;4&gt; in response to the control signals E and F, respectively. That is, the data inputted into the fourth bottom data I/O pad LDQ&lt;4&gt; are applied to the fourth bottom global I/O line GIO_L&lt;4&gt; and the fourth upper global I/O line GIO_U&lt;4&gt; in response to the control signals E and F, respectively. 
     In addition, other drivers (not shown) corresponding to the upper data I/O pads UDQ&lt;0:7&gt; receive a data option signal ‘x16’ according to a data option mode, so as apply the data to the corresponding upper global I/O lines GIO_U&lt;0:7&gt;, respectively. 
     Following tables 1 and 2 illustrate the state of logic level of the control signal A, B, C, D, E and F generated in response to the data option signal x4, x8 and x16, the row address signal RA&lt;13&gt; and the column address signal CA&lt;11&gt;. 
     
       
         
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 RA&lt;13&gt; 
                 CA&lt;11&gt; 
                 A 
                 B 
                 C 
                 D 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 x4 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
               
               
                   
                   
                 0 
                 1 
                 0 
                 0 
                 0 
                 1 
               
               
                   
                   
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
               
               
                   
                   
                 1 
                 1 
                 0 
                 1 
                 0 
                 0 
               
               
                   
                 x8 
                 0 
                 x 
                 0 
                 0 
                 1 
                 0 
               
               
                   
                   
                 1 
                 x 
                 1 
                 0 
                 0 
                 0 
               
               
                   
                 x16 
                 x 
                 x 
                 1 
                 0 
                 0 
                 0 
               
               
                   
                   
               
             
          
         
       
     
     
       
         
               
               
               
               
               
             
               
               
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 RA&lt;13&gt; 
                 CA&lt;11&gt; 
                 E 
                 F 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 x4 
                 x 
                 x 
                 0 
                 0 
               
               
                   
                 x8 
                 0 
                 x 
                 0 
                 1 
               
               
                   
                   
                 1 
                 x 
                 1 
                 0 
               
               
                   
                 x16 
                 x 
                 x 
                 1 
                 0 
               
               
                   
                   
               
             
          
         
       
     
     Considering the data input operation with reference to the tables 1 and 2, the 8-bit data is inputted to a corresponding data input sense amplifier  30  through the bottom data I/O pads LDQ&lt;0:7&gt; in the ‘x8’ operation mode. Thereafter, the amplified data is inputted to the corresponding input multiplexers  11  and  12 , respectively. Afterwards, the data inputted to the input multiplexers  11  and  12  is applied to the bottom global I/O lines GIO_L&lt;0:7&gt; in response to the control signals A and E, or applied to the upper global I/O lines GIO_U&lt;0:7&gt; in response to the control signals C and F. Then, the applied 8-bit data are transferred to the bottom or upper local I/O lines LIO_L&lt;0:7&gt; or LIO_U&lt;0:7&gt; through a write driver  40  corresponding to the bottom or upper global I/O lines GIO_L&lt;0:7&gt; or GIO_U&lt;0:7&gt;. 
     Meanwhile, since the input operations of the ‘x16’ and ‘x4’ operation modes are similar to those of the ‘x8’ operation mode, detailed descriptions about the input operations will be omitted herein. 
       FIG. 4  is a block diagram illustrating the conventional output multiplexer  20  shown in  FIG. 2B . In  FIG. 4 , there is illustrated only a representative portion of the conventional output multiplexer  20 . In the output multiplexing unit  20 , there are employed an output multiplexer  21  corresponding to the zeroth bottom data I/O pad LDQ&lt;0&gt;, and an output multiplexer  22  corresponding to the fourth bottom data I/O pad LDQ&lt;4&gt;. Herein, although the output multiplexer  21  corresponding to the zeroth bottom data I/O pad LDQ&lt;0&gt; has the same configuration as other output multiplexers (not shown) which are correspondent to the first to third bottom data I/O pads LDQ&lt;1:3&gt;, they are connected to respective different global I/O lines. In detail, the output multiplexer  21  corresponding to the zeroth bottom data I/O pad LDQ&lt;0&gt; receives the data supplied to the global I/O lines GIO_L&lt;0&gt;, GIO_L&lt;4&gt;, GIO_U&lt;0&gt; and GIO_U&lt;4&gt;, and an output multiplexer (not shown) corresponding to the first bottom data I/O pad LDQ&lt;1&gt; receives the data supplied to the global I/O lines GIO_L&lt;1&gt;, GIO_L&lt;5&gt;, GIO_U&lt;1&gt; and GIO_U&lt;5&gt;. Likewise, an output multiplexer (not shown) corresponding to the second bottom data I/O pad LDQ&lt;2&gt; receives the data supplied to the global I/O lines GIO_L&lt;2&gt;, GIO_L&lt;6&gt;, GIO_U&lt;2&gt; and GIO_U&lt;6&gt;, and an output multiplexer (not shown) corresponding to the third bottom data I/O pad LDQ&lt;3&gt; receives the data supplied to the global I/O lines GIO_L&lt;3&gt;, GIO_L&lt;7&gt;, GIO_U&lt;3&gt; and GIO_U&lt;7&gt;. 
     Furthermore, although the output multiplexer  22  corresponding to the fourth data I/O pad LDQ&lt;4&gt; has the same configuration as other output multiplexers (not shown) which are correspondent to the fourth to seventh bottom data I/O pads LDQ&lt;4:7&gt;, they are connected to different global I/O lines, respectively. In detail, the output multiplexer  22  corresponding to the fourth bottom data I/O pad LDQ&lt;4&gt; receives the data supplied to the global I/O lines GIO_L&lt;4&gt; and GIO_U&lt;4&gt;, and an output multiplexer (not shown) corresponding to the fifth bottom data I/O pad LDQ&lt;5&gt; receives the data supplied to the global I/O lines GIO_L&lt;5&gt; and GIO_U&lt;5&gt;. Likewise, an output multiplexer (not shown) corresponding to the sixth bottom data I/O pad LDQ&lt;6&gt; receives the data supplied to the global I/O lines GIO_L&lt;6&gt; and GIO_U&lt;6&gt;, and an output multiplexer (not shown) corresponding to the seventh bottom data I/O pad LDQ&lt;7&gt; receives the data supplied to the global I/O lines GIO_L&lt;7&gt; and GIO_U&lt;7&gt;. 
     The output multiplexer  21  corresponding to the zeroth bottom data I/O pad LDQ&lt;0&gt; has a 4-input multiplexer MUX1 receiving the data option signal x4, x8 and x16, the row address signal RA&lt;13&gt; and the column address signal CA&lt;11&gt;. Herein, the output multiplexer  21  outputs one of the data supplied to the global I/O lines GIO_L&lt;0&gt;, GIO_L&lt;4&gt;, GIO_U — &lt;0&gt; and GIO_U&lt;4&gt; in response to a predetermined control signal. 
     In addition, the output multiplexer  22  corresponding to the fourth bottom data I/O pad LDQ&lt;4&gt; has a 2-input multiplexer MUX2 receiving the data option signal x4, x8 and x16, the row address signal RA&lt;13&gt; and the column address signal CA&lt;11&gt;. The output multiplexer  21  outputs one of the data supplied to the global I/O lines GIO_L&lt;0&gt;, GIO_L&lt;4&gt;, GIO_U&lt;0&gt; and GIO_U&lt;4&gt; in response to a predetermined control signal. 
     Table 3 illustrates the global I/O line GIO_L&lt;0&gt;, GIO_L&lt;4&gt;, GIO — &lt;0&gt; and GIO — &lt;4&gt; selected according to the data option signal x4, x8 and x16, the row address signal RA&lt;13&gt; and the column address signal CA&lt;11&gt;, wherein the data option signal x4, x8 and x16, the row address signal RA&lt;13&gt; and the column address signal CA&lt;11&gt; control the output multiplexer  21 . 
     
       
         
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 3 
               
               
                   
                   
               
               
                   
                 RA&lt;13&gt; 
                 CA&lt;11&gt; 
                 OUT1 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 x4 
                 0 
                 0 
                 GIO_U&lt;0&gt; 
               
               
                   
                   
                 0 
                 1 
                 GIO_U&lt;4&gt; 
               
               
                   
                   
                 1 
                 0 
                 GIO_L&lt;0&gt; 
               
               
                   
                   
                 1 
                 1 
                 GIO_L&lt;4&gt; 
               
               
                   
                 x8 
                 0 
                 x 
                 GIO_U&lt;0&gt; 
               
               
                   
                   
                 1 
                 x 
                 GIO_L&lt;0&gt; 
               
               
                   
                 x16 
                 x 
                 x 
                 GIO_L&lt;0&gt; 
               
               
                   
                   
               
             
          
         
       
     
     Table 4 illustrates the global I/O line GIO_L&lt;4&gt; and GIO_U&lt;4&gt; selected according to the data option signal x4, x8 and x16, the row address signal RA&lt;13&gt; and the column address signal CA&lt;11&gt;, wherein the data option signal x4, x8 and x16, the row address signal RA&lt;13&gt; and the column address signal CA&lt;11&gt; control the output multiplexer  22 . 
     
       
         
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 4 
               
               
                   
                   
               
               
                   
                 RA&lt;13&gt; 
                 CA&lt;11&gt; 
                 OUT2 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 x4 
                 0 
                 0 
                 GIO_U&lt;4&gt; 
               
               
                   
                   
                 0 
                 1 
                 GIO_U&lt;4&gt; 
               
               
                   
                   
                 1 
                 0 
                 GIO_L&lt;4&gt; 
               
               
                   
                   
                 1 
                 1 
                 GIO_L&lt;4&gt; 
               
               
                   
                 x8 
                 0 
                 x 
                 GIO_U&lt;4&gt; 
               
               
                   
                   
                 1 
                 x 
                 GIO_L&lt;4&gt; 
               
               
                   
                 x16 
                 x 
                 x 
                 GIO_L&lt;4&gt; 
               
               
                   
                   
               
             
          
         
       
     
     Considering the data output operation with reference to the tables 3 and 4, the data to be outputted from the local I/O lines LIO_L&lt;0:7&gt; and LIO_U&lt;0:7&gt; are amplified at a sense amplifier  50  and then inputted to a driver  60 . At this time, each driver  60  receives one of the data option signals x4, x8 and x16, the row address signal RA&lt;13&gt; and the column address signal CA&lt;11&gt;, and applies the output data to the corresponding global I/O lines GIO_L&lt;0:7&gt; and GIO_U&lt;0:7&gt;. The conventional output multiplexer  20  selects the data supplied to the predetermined global I/O lines GIO_L&lt;0:7&gt; and GIO_U&lt;0:7&gt; in response to the data option signal x4, x8 and x16, the row address signal RA&lt;13&gt; and the column address signal CA&lt;11&gt;. Thereafter, the output data is latched at a corresponding pipe latch  70 , and then outputted to the corresponding data I/O pad LDQ&lt;0:7&gt; and UDQ&lt;0:7&gt;. 
     For instance, the 8-bit data, which is outputted through the bottom or upper local I/O lines LIO_L&lt;0:7&gt; or LIO_U&lt;0:7&gt;, is applied to the upper or bottom global I/O lines GIO_L&lt;0:7&gt; or GIO_U&lt;0:7&gt; in response to the data option signal x4, x8 and x16, the row address signal RA&lt;13&gt; and the column address signal CA&lt;11&gt;, in the ‘x8’ operation mode. The conventional output multiplexer  20  selects the bottom or upper global I/O lines GIO_L&lt;0:7&gt; or GIO_U&lt;0:7&gt; in response to the data option signal x4, x8 and x16, the row address signal RA&lt;13&gt; and the column address signal CA&lt;11&gt;, to output the 8-bit data to the bottom data I/O pads LDQ&lt;0:7&gt;. 
     In the meantime, the output operations of the ‘x16’ and ‘x4’ operation modes are similar to the ‘x8’ operation mode so that further descriptions will be omitted herein. 
     Referring back to  FIG. 3  for explaining the problem of the prior art, each of the input multiplexers  11  corresponding to the first to third data I/O pads LDQ&lt;0:3&gt; is configured with four drivers DRV 1 , DRV 2 , DRV 3  and DRV 4 . This configuration causes a layout area to be relatively increased in comparison with areas around the other data I/O pads. In particular, as the number of prefetch bits increases in a DDR 2  SDRAM or a DDR 3  SDRAM, it is burdensome to design a layout within a restricted area. For example, because of 8-bit prefetch architecture of the DDR 3  SDRAM, the number of drivers required in the input multiplexer  11  corresponding to the data I/O pads LDQ&lt;0:3&gt; should be 32, which is calculated by multiplying the number of drivers per one multiplexer  11 , i.e., 4, by the number of the prefetch bits, i.e., 8. 
     In addition, because it is necessary to employ the 4-input multiplexer MUX1 around the zeroth bottom data I/O pad LDQ&lt;0&gt; shown in  FIG. 3 , it is relatively difficult to secure appropriate layout area around the zeroth bottom data I/O pad LDQ&lt;0&gt;. 
     In other words, since the four drivers DRV 1 , DRV 2 , DRV 3  and DRV 4  (not considering the prefetch), and the 4-input multiplexer MUX1 should be densely concentrated around the bottom data I/O pads LDQ&lt;0:3&gt;, it is difficult to design the layout of the device appropriately. Further, this problem of the layout design becomes more serious in consideration of the number of prefetch bits, and resultingly, this makes the chip size increased after all. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to provide an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output pad. 
     In accordance with an aspect of the present invention, there is provided an apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line, including a first multiplexer for multiplexing the data and supplying a first multiplexed data to the global I/O line and a second multiplexer for multiplexing the first multiplexed data supplied to the global I/O line, wherein the first and second multiplexers are formed at either side of the global I/O line. 
     In accordance with another aspect of the present invention, there is provided a semiconductor device, including a data input/output (I/O) pad for receiving data, a first input multiplexer for multiplexing the data inputted through the data I/O pad and supplying a first multiplexed data to a global I/O line, wherein the first input multiplexer is located between the data I/O pad and the global I/O line, and a second input multiplexer for multiplexing the first multiplexed data supplied to the global I/O line and supplying a second multiplexed data to a local input/output (I/O) line, wherein the second input multiplexer is disposed between the global I/O line and the local I/O line. 
     In accordance with still another aspect of the present invention, there is provided a semiconductor device, including a local I/O line, a first output multiplexer for multiplexing data inputted to the local I/O line and supplying a first multiplexed data to the global I/O line, wherein the first output multiplexer is formed between the local I/O line and the global I/O line, and a second output multiplexer for multiplexing the first multiplexed data supplied to the global I/O line and providing a second multiplexed data to the data I/O pad, wherein the second output multiplexer is located between the global I/O line and the data I/O pad. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects and features of the present invention will become better understood with respect to the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: 
         FIGS. 1A to 1C  are block diagrams showing a conventional flow of data multiplexed according to ‘x4’, ‘x8’, and ‘x16’ operation modes; 
         FIGS. 2A and 2B  are block diagrams describing a conventional input/output multiplexer; 
         FIG. 3  is a block diagram illustrating a conventional input multiplexer shown in  FIG. 2A ; 
         FIG. 4  is a block diagram illustrating a conventional output multiplexer shown in  FIG. 2B ; 
         FIG. 5  is a block diagram depicting first and second input multiplexers in accordance with an embodiment of the present invention; 
         FIG. 6  is a schematic circuit diagram illustrating a control signal generator for controlling the first input multiplexer shown in  FIG. 5 ; 
         FIGS. 7A and 7B  are schematic circuit diagrams showing the second input multiplexer shown in  FIG. 5 ; 
         FIG. 8  is a block diagram illustrating first and second output multiplexers in accordance with an embodiment of the present invention; 
         FIG. 9  is a schematic circuit diagram illustrating a control signal generator for controlling the first output multiplexer shown in  FIG. 8 ; and 
         FIG. 10  is a schematic circuit diagram illustrating the second output multiplexer shown in  FIG. 8 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A data input/output multiplexer of a semiconductor device in accordance with exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
       FIG. 5  is a block diagram depicting first and second input multiplexers  100   a  and  100   b  in accordance with the present invention. 
     Referring to  FIG. 5 , there are shown only representative portions of the first and second input multiplexers  100   a  and  100   b . In the first input multiplexer  100   a , there are employed a first input multiplexer  110   a  corresponding to a zeroth bottom data input/output (I/O) pad LDQ&lt;0&gt;, a first input multiplexer  120   a  corresponding to a fourth bottom data I/O pad LDQ&lt;4&gt; among bottom data I/O pads LDQ&lt;0:7&gt;, and drivers DRV 15  and DRV 16  corresponding to zeroth and fourth upper data I/O pads UDQ&lt;0&gt; and UDQ&lt;4&gt;. 
     Herein, the first input multiplexer  110   a  corresponding to the zeroth bottom data I/O pad LDQ&lt;0&gt; is configured with a driver DRV 11  receiving a control signal A, and a driver DRV 12  receiving a control signal B. Although the first input multiplexers (not shown) corresponding to first to third bottom data I/O pads LDQ&lt;1:3&gt; are configured like the first input multiplexer  110   a , they are connected to different global I/O lines, respectively. That is, the first input multiplexer  110   a  corresponding to the zeroth bottom data I/O pad LDQ&lt;0&gt; is connected to the global I/O lines GIO_L&lt;0&gt; and GIO_U&lt;0&gt;, and the first input multiplexer (not shown) corresponding to a first bottom data I/O pad LDQ&lt;1&gt; is connected to the global I/O lines GIO_L&lt;1&gt; and GIO_U&lt;1&gt;. Likewise, the first input multiplexer (not shown) corresponding to a second bottom data I/O pad LDQ&lt;2&gt; is connected to the global I/O lines GIO_L&lt;2&gt; and GIO_U&lt;2&gt;, and the first input multiplexer (not shown) corresponding to a third bottom data I/O pad LDQ&lt;3&gt; is connected to the global I/O lines GIO_L&lt;3&gt; and GIO — &lt;3&gt;. Meanwhile, the first input multiplexer  120   a  corresponding to the fourth bottom data I/O pad LDQ&lt;4&gt; is configured with a driver DRV 13  receiving a control signal C and a driver DRV 14  receiving a control signal D. Although first input multiplexers (not shown) corresponding to fifth to seventh bottom data I/O pads LDQ&lt;5:7&gt; also have the same configuration as the first multiplexer  120   a , they are connected to different global I/O lines, respectively. In detail, the first input multiplexer  120   a  corresponding to the fourth bottom data I/O pad LDQ&lt;4&gt; is connected to the global I/O lines GIO_L&lt;4&gt; and GIO_U&lt;4&gt;, and the first input multiplexer (not shown) corresponding to a fifth bottom data I/O pad LDQ&lt;5&gt; is connected to the global I/O lines GIO_L&lt;5&gt; and GIO_U&lt;5&gt;. Likewise, the first input multiplexer (not shown) corresponding to a sixth bottom data I/O pad LDQ&lt;6&gt; is connected to the global I/O lines GIO_L&lt;6&gt; and GIO_U&lt;6&gt;, and the first input multiplexer (not shown) corresponding to a seventh bottom data I/O pad LDQ&lt;7&gt; is connected to the global I/O lines GIO_L&lt;7&gt; and GIO_U&lt;7&gt;. In addition, other drivers (not shown) corresponding to upper data I/O pads UDQ&lt;0:7&gt; are connected to corresponding upper global I/O lines GIO_U&lt;0:7&gt;, respectively. 
     In the second input multiplexer  100   b , there are employed a second input multiplexer  110   b  corresponding to a fourth bottom local I/O line LIO_L&lt;4&gt;, and a second input multiplexer  120   b  corresponding to a fourth upper local I/O line LIO_U&lt;4&gt;. 
     Herein, the second input multiplexers  110   a  and  120   b , of which each one has a 2-input input multiplexer MUX11 or MUX12 responsive to a ‘x4’ data option signal, are connected different global I/O lines, respectively. That is, the 2-input multiplexer MUX11 corresponding to the fourth bottom local I/O line LIO_L&lt;4&gt; is connected to the global I/O lines GIO_L&lt;0&gt; and GIO_L&lt;4&gt;, and the 2-input multiplexer (not shown) corresponding to a fifth bottom local I/O line LIO_L&lt;5&gt; is connected to the global I/O lines GIO_L&lt;1&gt; and GIO_L&lt;5&gt;. Likewise, the 2-input multiplexer (not shown) corresponding to a sixth bottom local I/O line LIO_L&lt;6&gt; is connected to the global I/O lines GIO_L&lt;2&gt; and GIO_L&lt;6&gt;, and the 2-input multiplexer (not shown) corresponding to a seventh bottom local I/O line LIO_L&lt;7&gt; is connected to the global I/O lines GIO_L&lt;3&gt; and GIO_L&lt;7&gt;. 
     In addition, the 2-input multiplexer MUX12 corresponding to a fourth upper local I/O line LIO_U&lt;4&gt; is connected to the global I/O lines GIO_U&lt;0&gt; and GIO_U&lt;4&gt;, and the 2-input multiplexer MUX11 (not shown) corresponding to a fifth upper local I/O line LIO_U&lt;5&gt; is connected to the global I/O lines GIO_U&lt;1&gt; and GIO_U&lt;5&gt;. Likewise, the 2-input multiplexer (not shown) corresponding to a sixth upper local I/O line LIO_U&lt;6&gt; is connected to the global I/O lines GIO_U&lt;2&gt; and GIO_U&lt;6&gt;, and the 2-input multiplexer MUX11 (not shown) corresponding to a seventh upper local I/O line LIO_U&lt;7&gt; is connected to the global I/O lines GIO_U&lt;3&gt; and GIO — &lt;7&gt;. 
     Tables 5 illustrates the state of logic level of the control signal A, B, C and D generated in response to the data option signal x4, x8 and x16, the row address signal RA&lt;13&gt; and the column address signal CA&lt;11&gt;. 
     
       
         
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 5 
               
               
                   
                   
               
               
                   
                 RA&lt;13&gt; 
                 CA&lt;11&gt; 
                 A 
                 B 
                 C 
                 D 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 x4 
                 0 
                 0 
                 0 
                 1 
                 0 
                 0 
               
               
                   
                   
                 0 
                 1 
                 0 
                 1 
                 0 
                 0 
               
               
                   
                   
                 1 
                 0 
                 1 
                 0 
                 0 
                 0 
               
               
                   
                   
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
               
               
                   
                 x8 
                 0 
                 x 
                 0 
                 1 
                 0 
                 1 
               
               
                   
                   
                 1 
                 x 
                 1 
                 0 
                 1 
                 0 
               
               
                   
                 x16 
                 x 
                 x 
                 1 
                 0 
                 1 
                 0 
               
               
                   
                   
               
             
          
         
       
     
     Table 6 illustrates the global I/O lines GIO_L&lt;0:7&gt; and GIO_U&lt;0:7&gt; selected by the second input multiplexer  100   b  in response to the data option signal x4, x8 and x16, the row address signal RA&lt;13&gt; and the column address signal CA&lt;11&gt;. 
     
       
         
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 6 
               
               
                   
                   
               
               
                   
                 RA&lt;13&gt; 
                 CA&lt;11&gt; 
                 OUT1 
                 OUT2 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 x4 
                 0 
                 0 
                 x 
                 x 
               
               
                   
                 0 
                 1 
                 x 
                 GIO_U&lt;0&gt; 
               
               
                   
                 1 
                 0 
                 x 
                 x 
               
               
                   
                 1 
                 1 
                 GIO_L&lt;0&gt; 
                 x 
               
               
                 x8 
                 0 
                 x 
                 x 
                 GIO_U&lt;4&gt; 
               
               
                   
                 1 
                 x 
                 GIO_L&lt;4&gt; 
                 x 
               
               
                 x16 
                 x 
                 x 
                 GIO_L&lt;4&gt; 
                 GIO_U&lt;4&gt; 
               
               
                   
               
             
          
         
       
     
     Considering the data input operation with reference to the tables 5 and 6, 8-bit data inputted through the bottom data I/O pad LDQ&lt;0:7&gt; is amplified at a corresponding data input amplifier  300  in the ‘x8’ operation mode. The amplified data is then inputted to the first input multiplexer  100   a . Afterwards, the input data of the first input multiplexer  100   a  is applied to the bottom global I/O lines GIO_L&lt;0:7&gt; in response to the control signals A and C, or applied to the upper global I/O lines GIO_U&lt;0:7&gt; in response to the control signals B and D. The second input multiplexer  100   b  transfers the 8-bit data supplied to the global I/O lines GIO_L&lt;0:7&gt; or GIO_U&lt;0:7&gt;, to the bottom local I/O lines LIO_L&lt;0:7&gt; through the bottom global I/O lines GIO_L&lt;0:7&gt; in response to the data option signal ‘x4’. Otherwise, the 8-bit data is transferred to the upper local I/O lines LIO_U&lt;0:7&gt; through the upper global input/output lines GIO_U&lt;0:7&gt;. 
     For example, in case of the ‘x4’ operation mode, the 4-bit data is inputted to the first input multiplexer  110   a  through the third bottom data I/O pad LDQ&lt;3&gt; among the bottom data I/O pads LDQ&lt;0:7&gt;, and applied to the global I/O lines GIO_L&lt;0:3&gt; and GIO_U&lt;0:3&gt; in response to the control signals A and B, respectively. 
     At this time, the 4-bit data, which is applied to the bottom global I/O lines GIO_L&lt;0:3&gt; in response to the control signal A, may be transferred to the bottom local I/O lines LIO_L&lt;0:3&gt; through a write driver  400  corresponding to the bottom local I/O lines LIO_L&lt;0:3&gt;. Alternatively, the 4-bit data may be transferred to the local I/O lines LIO_L&lt;4:7&gt; through the 2-input multiplexer MUX11 of the second input multiplexer  110   b.    
     In addition, the 4-bit data, which is applied to the upper global I/O lines GIO_U&lt;0:3&gt; in response to the control signal B, may be transferred to the upper local I/O lines LIO_U&lt;0:3&gt; through a write driver  400  corresponding to the upper local I/O lines LIL_U&lt;0:3&gt;. Alternatively, the 4-bit data may be transferred to the upper local I/O lines LIO_U&lt;4:7&gt; through the 2-input multiplexer MUX12 of the second input multiplexer  120   b . Further descriptions for the ‘x16’ operation mode will be omitted herein. 
       FIG. 6  is a schematic circuit diagram illustrating a control signal generator for generating the control signal A, B, C and D for controlling the first input multiplexer  100   a  shown in  FIG. 5 . 
     Referring to  FIG. 6 , a control signal generator is configured with a Nlogic OR gate NOR 1 , an inverter INV 1 , a logic AND gate AND 1 , a logic OR gate OR 1 , an inverter INV 2 , and a logic AND gate AND 2 . Herein, the Nlogic OR gate NOR 1  receives the data operation signal x16 and the row address signal RA&lt;13&gt; to output the control signal B. The inverter INV 1  inverts the control signal B to output the control signal A. The logic AND gate AND 1  receives the row address signal RA&lt;13&gt; and the data option signal x8. The logic OR gate OR 1  receives the output signal of the logic AND gate AND 1  and the data option signal x16 so as to output the control signal C. The inverter INV 2  inverts the row address signal RA&lt;13&gt;. The logic AND gate AND 2  receives the output signal of the inverter INV 2  and the data option signal x8 to thereby output the control signal D. 
       FIGS. 7A and 7B  are schematic circuit diagrams showing the second input multiplexer  100   b  shown in  FIG. 5 . 
     Referring to  FIG. 7A , the second input multiplexer  110   b  is configured with an inverter INV 3  for inverting the data option signal x4, a transfer gate TG 1  for receiving the data of the fourth bottom global I/O line GIO_L&lt;4&gt;, and a transfer gate TG 2  for receiving the data of the zeroth bottom global I/O line GIO_L&lt;0&gt;. Herein, the transfer gates TG 1  and TG 2  are controlled by the data option signal x4. 
     Referring to  FIG. 7B , the second input multiplexer  120   b  is configured with an inverter INV 4  for inverting the data option signal x4, a transfer gate TG 3  for receiving the data of the fourth upper global I/O line GIO_U&lt;4&gt;, and a transfer gate TG 4  for receiving the data of the zeroth upper global I/O line GIO_U&lt;0&gt;. Herein, the transfer gates TG 3  and TG 4  are controlled by the data option signal x4. 
       FIG. 8  is a block diagram illustrating first and second output multiplexers  200   a  and  200   b  in accordance with the present invention. 
     Referring to  FIG. 8 , there are shown only representative portions of the first and second output multiplexers  200   a  and  200   b . In the first input multiplexer  200   a , there are employed a first input multiplexer  220   a  corresponding to the zeroth upper local I/O line LIO_U&lt;0&gt;, a first input multiplexer  210   a  corresponding to the fourth upper local I/O line LIO_U&lt;4&gt;, and drivers DRV 15  and DRV 16  corresponding to bottom local I/O lines LIO_L&lt;4&gt; and LIO_L&lt;0&gt;. 
     Herein, the first output multiplexer  220   a  corresponding to the zeroth upper local I/O line LIO_U&lt;0&gt; is configured with a driver DRV 14  responsive to a control signal G, and a driver DRV 13  responsive to a control signal H. Although the first output multiplexers (not shown) corresponding to the first to third upper local I/O lines LIO_U&lt;1:3&gt; are also similarly configured, they are connected to different global I/O lines, respectively. That is, the first output multiplexer  220   a  is connected to the global I/O lines GIO_L&lt;0&gt; and GIO_U&lt;0&gt;. Similarly, the first output multiplexer (not shown) corresponding to the first upper local I/O line LIO_U&lt;1&gt; is connected to the global I/O lines GIO_L&lt;1&gt; and GIO_U&lt;1&gt;, and the first output multiplexer (not shown) corresponding to the second upper local I/O line LIO_U&lt;2&gt; is connected to the global I/O lines GIO_L&lt;2&gt; and GIO_U&lt;2&gt;. Likewise, the first output multiplexer (not shown) corresponding to the third upper local I/O line LIO_U&lt;3&gt; is connected to the global I/O lines GIO_L&lt;3&gt; and GIO_U&lt;3&gt;. 
     Meanwhile, the first output multiplexer  210   a  corresponding to the fourth upper local I/O line LIO_U&lt;4&gt; is configured with a driver DRV 12  responsive to a control signal I and a driver DRV 11  responsive to a control signal J. Although the first output multiplexers (not shown) corresponding to the fifth to seventh upper local I/O lines LIO_U&lt;5:7&gt; also have the same configuration as the first output multiplexer  210   a , they are connected to different global I/O lines, respectively. In detail, the first output multiplexer  210   a  corresponding to the fourth upper local I/O line LIO_U&lt;4&gt; is connected to the global I/O lines GIO_L&lt;4&gt; and GIO_U&lt;4&gt;, and the first output multiplexer (not shown) corresponding to the fifth upper local I/O line LIO_U&lt;5&gt; is connected to the global I/O lines GIO_L&lt;5&gt; and GIO_U&lt;5&gt;. Likewise, the first input multiplexer (not shown) corresponding to the sixth upper local I/O line LIO_U&lt;6&gt; is connected to the global I/O lines GIO_L&lt;6&gt; and GIO_U&lt;6&gt;, and the first input multiplexer (not shown) corresponding to the seventh upper local I/O line LIO_U&lt;7&gt; is connected to the global I/O lines GIO_L&lt;7&gt; and GIO_U&lt;7&gt;. In addition, other drivers (not shown) corresponding to the bottom local I/O lines LIO_L&lt;0:7&gt; are connected to the bottom global I/O lines GIO_L&lt;0:7&gt;, respectively. 
     In the second output multiplexer  200   b , a second output multiplexer  210   b  corresponding to the zeroth bottom data I/O pad LDQ&lt;0&gt; is representatively illustrated, wherein the second output multiplexer  210   b  is configured with a 2-input multiplexer MUX33 controlled by the column address signal CA&lt;11&gt; and the data option signal x4. 
     Herein, although the second output multiplexers (not shown) corresponding to the bottom data I/O pads LDQ&lt;1:3&gt; have the same configuration as the second output multiplexer  210   b , they are connected to different global I/O lines, respectively. Namely, the second output multiplexer  210   b  corresponding to the zeroth bottom data I/O pad LDQ&lt;0&gt; is connected to the global I/O lines GIO_L&lt;0&gt; and GIO_L&lt;4&gt;, and the second output multiplexer (not shown) corresponding to the first bottom data I/O pad LDQ&lt;1&gt; is connected to the global I/O lines GIO_L&lt;1&gt; and GIO_L&lt;5&gt;. Likewise, the second output multiplexer (not shown) corresponding to the second bottom data I/O pad LDQ&lt;2&gt; is connected to the global I/O lines GIO_L&lt;2&gt; and GIO_L&lt;6&gt;, and the second output multiplexer (not shown) corresponding to the third bottom data I/O pad LDQ&lt;3&gt; is connected to the global I/O lines GIO_L&lt;3&gt; and GIO_L&lt;7&gt;. 
     Table 7 illustrates the state of logic level of the control signal G, H, I and J which is generated in response to the data option signal x4, x8 and x16, the row address signal RA&lt;13&gt; and the column address signal CA&lt;11&gt;. The first output multiplexer  200   a  may select a predetermined global I/O line according to the control signal G, H, I and J, and apply the data to the predetermined global I/O line. 
     
       
         
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 7 
               
               
                   
                   
               
               
                   
                 RA&lt;13&gt; 
                 CA&lt;11&gt; 
                 G 
                 H 
                 I 
                 J 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 x4 
                 0 
                 0 
                 1 
                 0 
                 0 
                 0 
               
               
                   
                   
                 0 
                 1 
                 0 
                 0 
                 1 
                 0 
               
               
                   
                   
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                   
                   
                 1 
                 1 
                 0 
                 0 
                 0 
                 0 
               
               
                   
                 x8 
                 0 
                 x 
                 1 
                 0 
                 1 
                 0 
               
               
                   
                   
                 1 
                 x 
                 0 
                 0 
                 0 
                 0 
               
               
                   
                 x16 
                 x 
                 x 
                 0 
                 1 
                 0 
                 1 
               
               
                   
                   
               
             
          
         
       
     
     Table 8 illustrates the global I/O line GIO_L&lt;4&gt; and GIO_L&lt;0&gt; selected according to the data option signal x4 and the column address signal CA&lt;11&gt;, wherein the data option signal x4 and the column address signal CA&lt;11&gt; control the second output multiplexer  200   b . 
     
       
         
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 8 
               
               
                   
                   
               
               
                   
                 RA&lt;13&gt; 
                 CA&lt;11&gt; 
                 OUT 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 x4 
                 0 
                 0 
                 GIO_L&lt;0&gt; 
               
               
                   
                   
                 0 
                 1 
                 GIO_L&lt;4&gt; 
               
               
                   
                   
                 1 
                 0 
                 GIO_L&lt;0&gt; 
               
               
                   
                   
                 1 
                 1 
                 GIO_L&lt;0&gt; 
               
               
                   
                 x8 
                 0 
                 x 
                 GIO_L&lt;0&gt; 
               
               
                   
                   
                 1 
                 x 
                 GIO_L&lt;0&gt; 
               
               
                   
                 x16 
                 x 
                 x 
                 GIO_L&lt;0&gt; 
               
               
                   
                   
               
             
          
         
       
     
     Considering the data output operation with reference to the tables 7 and 8, for example, 8-bit data of the bottom or upper local I/O lines LIO_L&lt;0:7&gt; or LIO_U&lt;0:7&gt; are amplified by a corresponding sense amplifier  80 , in case of ‘x8’ operation mode outputting the 8-bit data. Herein, when the 8-bit data are applied to the bottom local I/O lines LIO_L&lt;0:7&gt;, the data are applied to the bottom global I/O lines GIO_L&lt;0:7&gt; by means of the drivers DRV 15  and DRV 16  corresponding to the bottom local I/O lines LIO_L&lt;0:7&gt;. The global I/O lines GIO_L&lt;0:3&gt; are selected by the second multiplexer  200   b  and the data of the global I/O lines GIO_L&lt;0:3&gt; are then inputted to a corresponding pipe latch  110 . Likewise, the data of the global I/O lines GIO_L&lt;4:7&gt; are inputted to a corresponding pipe latch  110 . The pipe latch  110  outputs the data to the corresponding bottom data I/O pads LDQ&lt;0:7&gt;. In addition, when the 8-bit data are applied to the upper local I/O lines LIO_U&lt;0:7&gt;, the 8-bit data are applied to the bottom global I/O lines GIO_L&lt;0:7&gt; by means of the first output multiplexer  200   a , and they are outputted to the bottom data I/O pads LDQ&lt;0:7&gt; through the same path. 
     Considering the ‘x4’ operation mode in detail, 4-bit data to be outputted from the local I/O lines LIO_L&lt;0:3&gt;, LIO_L&lt;4:7&gt;, LIO_U&lt;0:3&gt; or LIO_U&lt;4:7&gt; are outputted to the bottom data I/O pads LDQ&lt;0:3&gt; by the first and second output multiplexers  200   a  and  200   b . For instance, the 4-bit data to be outputted from the local I/O lines LIO_L&lt;0:3&gt; are applied to the global I/O lines GIO_L&lt;0:3&gt; through the driver DRV 16 . The 4-bit data supplied to the global I/O lines GIO_L&lt;0:3&gt; may be selected by the 2-input multiplexer MUX33 of the second multiplexer, and then outputted to the data I/O pads LDQ&lt;0:3&gt; through the corresponding pipe latch  110 . Furthermore, the 4-bit data to be outputted from the local I/O lines LIO_L&lt;4:7&gt; are applied to the global I/O lines GIO_L&lt;4:7&gt; through the driver DRV 15 . The 4-bit data supplied to the global I/O lines GIO_L&lt;4:7&gt; may be selected by the 2-input multiplexer MUX33 of the second multiplexer, and then outputted to the data I/O pads LDQ&lt;0:3&gt; through the corresponding pipe latch  110 . Likewise, the 4-bit data to be outputted from the local I/O lines LIO_U&lt;0:3&gt; are applied to the global I/O lines GIO_L&lt;0:3&gt; through the driver DRV 14  in response to the control signal G. The 4-bit data supplied to the global I/O lines GIO_L&lt;0:3&gt; may be selected by the 2-input multiplexer MUX33, and then outputted to the data I/O pads LDQ&lt;0:3&gt; through the corresponding pipe latch  110 . The 4-bit data to be outputted from the local I/O lines LIO_U&lt;4:7&gt; are applied to the global I/O lines GIO_L&lt;4:7&gt; through the driver DRV 12  in response to the control signal I. The 4-bit data supplied to the global I/O lines GIO_L&lt;4:7&gt; may be selected by the 2-input multiplexer MUX33, and then outputted to the data I/O pads LDQ&lt;0:3&gt; through the corresponding pipe latch  110 . 
     The ‘x16’ operation mode may be fully understood by those skilled in the art through the aforementioned descriptions for the ‘x4’ and ‘x8’ operation modes, and thus further descriptions will be omitted herein. 
       FIG. 9  is a schematic circuit diagram illustrating an output control signal generator for generating the control signals G, H, I, and J which are inputted to the first output multiplexer  200   a  shown in  FIG. 8 . 
     Referring to  FIG. 9 , the output control signal generator includes an inverter INV 5 , a logic AND gate AND 3 , a logic OR gate OR 2 , an inverter INV 6 , a logic AND gate AND 4 , a logic AND gate AND 5 , a logic OR gate OR 3 , an inverter INV 7 , and logic AND gate AND 6 . The inverter INV 5  inverts the column address signal CA&lt;11&gt;. The logic AND gate AND 3  receives the output signal of the inverter INV 5  and the data option signal x4. The logic OR gate OR 2  receives the output signal of the logic AND gate AND 3  and the data option signal x8. The inverter INV 6  inverts the row address signal RA&lt;13&gt;. The logic AND gate AND 4  receives the output signals of the logic OR gate OR 2  and the inverter INV 6  to output the control signal G. The logic AND gate AND 5  receives the column address signal CA&lt;11&gt; and the data option signal x4. The logic OR gate OR 3  receives the output signal of the logic AND gate AND 5  and the data option signal x8. The inverter INV 7  inverts the row address signal RA&lt;13&gt;. The logic AND gate AND 6  receives the output signal of the inverter INV 7  and the output signal of the logic OR gate OR 3  to output the control signal I. Herein, the data option signal x16 is used for outputting the control signals H and J. 
       FIG. 10  is a schematic circuit diagram illustrating the second output multiplexer  200   b  shown in  FIG. 8 . 
     Referring to  FIG. 10 , the second output multiplexer  200   b  connected to the zeroth and fourth bottom global I/O lines GIO_L&lt;0&gt; and GIO_L&lt;4&gt;, includes a logic AND gate AND 6  for receiving the data option signal x4 and the column address signal CA&lt;11&gt;, an inverter INV 8  for inverting the output signal of the logic AND gate AND 6 , a transfer gate TG 6  for outputting the data supplied to the zeroth bottom global I/O line GIO_L&lt;0&gt; in response to the output signal of the logic AND gate AND 6  and the output signal of the inverter INV 8 , and a transfer gate TG 7  for outputting the data supplied to the fourth bottom global I/O line GIO_L&lt;4&gt;. 
     As described above, the inventive I/O multiplexer includes the first and second I/O multiplexers at both sides of the global I/O lines, wherein the first one is opposite to the second one. Therefore, the I/O multiplexers are evenly spaced apart from each other by an appropriate distance in the present invention, whereas they are densely disposed around a specific data I/O pad according to the prior art. 
     That is, referring to  FIG. 5 , each of the first input multiplexers  110   a  corresponding to the bottom data I/O pads LDQ&lt;0:3&gt; is configured with the two drivers DRV 11  and DRV 12 . Such an inventive configuration enables the layout area to be reduced to more than half thereof in comparison with the conventional multiplexer employing four drivers therein. In addition, referring to  FIG. 8 , since each of the second multiplexers  210   b  corresponding to the respective bottom data I/O pads LDQ&lt;0:3&gt; may be configured with the 2-input multiplexer MUX33 instead of the conventional 4-input multiplexer, it is possible to reduce the layout area, too. 
     In conclusion, the present invention has such an advantageous merit that a chip size of a semiconductor decreases by reducing the layout area because the first and second I/O multiplexers are disposed at both sides of the global I/O lines. Further, it is possible to maintain internal circuits of the chip to be evenly spaced apart by an appropriate distance from each other, which helps the interference of the internal circuits and malfunction to be effectively prevented. 
     The present application contains subject matter related to the Korean patent applications Nos. KR 10-2005-0091548 and KR 10-2006-0049113, filed in the Korean Patent Office on Sep. 29, 2005 and on May 31, 2006 respectively, the entire contents of which being incorporated herein by reference. 
     While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.