Abstract:
An analog-to-digital converting apparatus includes an analog controllable gain amplifier (A 1 ) connected to an input of an analog-to-digital converter A/N. A gain control signal of the amplifier (A 1 ) is obtained from at least one comparator (D16, D240, D224) for making a binary comparison between an output level of the analog-to-digital converter (A/N) and at least one predetermined threshold, and circuitry (SEL2, S 2 , I 2 ) for controlling with respect to time the gain of the amplifier (A 1 ) as a function of the result of the comparison.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to an analog-to-digital converting apparatus having an automatic gain control circuit comprising an analog gain controllable amplifier and an analog-to-digital (A/D) converter coupled to an output of the analog amplifier, a gain control loop of said analog amplifier receiving output signals from the A/D converter. 
     Such an analog-to-digital converting apparatus is known from the French Patent Application No. 2 536 620 (RCA Corp.), which corresponds to U.S. Pat. No. 4,517,586. Herein, the values of the digital samples from the A/D converter are digitally compared to a reference level, in order to produce a digital difference signal which is converted by a digital-to-analog converter into an analog gain control signal of the gain controllable amplifier. This solution leads to a complicated and thus costly circuitry. 
     SUMMARY OF THE INVENTION 
     The present invention has for its object to provide an analog-to-digital converting apparatus of the type stated before, in which no digital-to-analog converter is utilized for controlling the amplifier gain. Hence, the A/D converting apparatus is simplified and thus less costly. 
     To this end, the analog-to-digital converting apparatus according to the invention is characterized in that it comprises at least one comparator for making a binary comparison between an output level of the analog-to-digital converter and at least one given threshold, and means for controlling the amplifier gain in a time-controlled fashion as a function of a result of said comparison. 
     The above comparator comprises advantageously a decoder of a logic level corresponding to at least one white level of at least one television transmission system. 
     The means for controlling the amplifier gain in a time-controlled fashion can comprise a first controllable current source effecting the charging and discharging of a first capacitor, which is coupled to a gain control input of said amplifier. 
     The above first controllable current source can comprise a first differential stage having a first and a second transistor whose emitters are coupled to a first control current source, the collector of the first transistor being coupled to a supply voltage source and that of the second transistor to said first capacitor as well as a second control current source, the bases of the first and second transistors receiving a first differential signal corresponding to the result of said comparison, the first control current source having a current value distinctly superior to that of the second control current source, so that the first capacitor is charged with a given time constant across the second control current source for a first logic state of the first differential signal, and for a second logic state of the said signal, said first capacitor is discharged with a shorter time constant across the first control current source. 
     The A/D converting apparatus according to the invention can also comprise means for controlling, in a time-controlled fashion, a continuous level at a signal input of the amplifier as a function of the result of a comparison produced by a second decoder of a logic level, corresponding to a continuous level standardized by at least one television transmission system. Said means for controlling the continuous level in a time-controlled fashion can also comprise a second controllable current source effecting the charging and discharging of a second capacitor, which is coupled in series to the signal input of said amplifier. 
     In a preferred embodiment, the second controllable current source comprises a second differential stage having a third and a fourth transistor whose emitters are coupled to a third control current source, the collector of the third transistor being coupled to that of a fifth transistor whose emitter is coupled to said supply voltage source, the collector of the fourth transistor being coupled to said second capacitor as well as the collector of a sixth transistor whose emitter is coupled to said supply voltage source, the bases of the fifth and sixth transistors being intercoupled, and the base and the collector of the fifth transistor being coupled so that the fifth and sixth transistors form a current mirror circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be better understood when reading the description given hereinbelow as a non-limiting example, with reference to the following Figures, in which: 
     FIG. 1 shows a general diagram of an A/D converting apparatus according to the invention; 
     FIG. 2 shows a diagram of an embodiment of automatic gain correcting logic in universal television receivers; 
     FIG. 3 shows a diagram of an embodiment of continuous level correcting logic in universal television receivers; 
     FIGS. 4 and 5 show embodiments of the controllable current sources corresponding to an automatic gain control and a continuous level correction, respectively; 
     FIGS. 6, 7a and 7b show, respectively, PAL or SECAM luminance signals, a signal according to the MAC television transmission system, and a detail of a luminance signal of last lines of a picture according to the MAC television transmission system; 
     FIG. 8 shows logic stages of a GRAY encoding provided by outputs G 1  . . . G 8  of the A/D converters; 
     FIG. 9 shows a decoder operating on the basis of this code; and 
     FIGS. 10 and 11 show an embodiment of a circuit producing signals S 2  and S 1  of the respective FIGS. 2 and 3 from outputs of the decoder of FIG. 9. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     According to FIG. 1, a gain control input of an amplifier A 1  of the variable gain type is connected to one of two terminals of a capacitor C 2 , whose other terminal is connected to ground. 
     The charging and discharging of the capacitor C 2  is obtained from a controllable current source I 2  which allows the realization of a counter reaction of automatic gain control. An output of the amplifier A 1  drives an analog-to-digital (A/D) converter A/N having outputs S which produce a digital signal whose level is to be controlled according to certain parameters, more specifically, in order to avoid saturation at the output of the A/D converter A/N. In this specific case, an analog-to-digital converting apparatus is shown for a television receiver which can be used for the classical PAL and SECAM reception as well as for satellite reception according to the MAC television transmission system. Thereto, the signals S are applied to decoders D 16 , D 240  and D 224  whose output signals s 16 , s 240  (for the MAC television transmission system) and s 224  (PAL or SECAM) each have a logic 1 or 0 level depending on the condition of the output signals S of the A/D converter A/N. The signals s 16 , s 240  and s 224  are applied to a selecting circuit SEL2, which receives a logic selecting signal S 0  indicating whether the receiver operates on a transmission according to the PAL or SECAM television transmission system, or a transmission according to the MAC television transmission system. The selecting circuit SEL2 also receives control pulses p 2  of the automatic gain control. 
     The output signal S 2  of the selecting circuit SEL2 controls a controllable current source I 2  in one direction or the other with an intensity which can vary with the direction, in order to attain a time-controllable charging or discharging of the capacitor C 2 , with time constants which may be different. 
     According to the invention, a correction of a continuous level can also be realized in an analog manner by controlling a time-controlled charging and discharging of a capacitor C 1  connected in series to a signal input of the amplifier A 1  with the aid of a controllable current source I 1 . 
     While reference is always made to the preceding example, concerning a universal television receiver, the output signals S of the analog-to-digital converter A/N are applied to the inputs of the two decoders D 32  and D 128  producing at their outputs, the signals s 32  (PAL or SECAM) and s 128  (for the MAC standard) each having a logic 1 or 0 level depending on the value of the output signals S. The signals s 32  and s 128  are applied to a selecting circuit SEL1 receiving the logic selecting signal S 0  indicating whether the receiver operates according to a PAL or SECAM television transmission system or otherwise according to the MAC television transmission system. The controllable current source I 1  also receives control pulses p1 to correct the continuous level (see FIG. 6). Such a pulse is present in the PAL or SECAM television transmission system at the beginning of each line at the moment when the signal has reached a level equal to one-eighth of the maximum amplitude (32 for an 8-bit encoding). According to the MAC television transmission system, the signal p1 is a pulse 750  ns in length at the beginning of each line during which the signal has a level equal to one-half the maximum amplitude, which is 128 for 8-encoding (see FIG. 7a). The output signal S 1  of the selecting circuit SEL1 controls the current source I 1  in one direction or in the other in order to attain a time-controlled charging or discharging of the capacitor C 1 . 
     With reference to FIG. 2, it will now be described in a more precise way how the automatic gain control signal S 2  is generated. According to the MAC television transmission system, the correction takes place when a signal occurs produced on the line 624 of each picture (see FIG. 7b), which is reversed to the white, black and grey reference signals. As the signal is symmetrical, automatic gain control is achieved controlling the white level as well as the black level. The black level is obtained when decoding the 16-value and the white level by decoding the 240 value. Owing to the symmetry of the reference signal of line 624 (MAC television transmission system), the automatic gain control is controlled by a signal s 16  which has, in the present case, the 1-value when the output of the analog-to-digital converter A/N has a value of ≦15 and the 0-value if this is not the case, and by a signal s 240  which has the 1-value when the output of the A/D converter has a value of ≧240 and 0 if this is not the case. The signal s 240  is an output signal of an AND gate 20, four inputs of which receive the four high-order bits from the output of the converter, that is to say Q 5 , Q 6 , Q 7  and Q 8 , respectively. The signal s 16  is an output signal of an inverting OR gate 21, four inputs of which also receive the bits Q 5 , Q 6 , Q 7  and Q 8 , respectively. 
     The signals s 16  and s 240  are applied to two inputs of an OR gate 22, an output signal of which forms a signal s 17  and drives one of the two inputs of an AND gate 23 whose other input receives the pulses p2 representative of the line 624 (see FIG. 7b). An output of the AND gate 23 is applied to an input of an AND gate 24, a further input of which receives the selecting signal S 0  inverted by an invertor 14. 
     According to the PAL or SECAM television transmission systems, the reference level for realizing the automatic gain control is the level 224 from the output of the A/D converter. In contradistinction to the MAC television transmission system, the automatic gain control is realized line by line. The signal s 224  is chosen so as to have a logic 1 level for an A/D converter output level ≧224, and a logic 0 level if this is not the case. In order to achieve this, the three highest order bits Q 6 , Q 7  and Q 8 , respectively, are applied to three inputs of an AND gate 25, an output of which, supplying signal s 224 , drives one of two inputs of an AND gate 26 whose other input receives the selecting signal S 0 . Outputs of the AND gates 24 and 26 are applied to respective inputs of an OR gate 27, an output of which supplies the signal S 2 . 
     With reference to FIG. 3, it will now be described in a more precise manner how the continuous level correcting signal S 1  is generated. In the PAL or SECAM television transmission systems, the black background level corresponds to the 32 value at the output of the 8-bit analog-to-digital converter A/N. The 32 value is attained when one of the three first high order bits Q 6 , Q 7 , Q 8  has the value of 1. Consequently, the detection (decoder D 32 ) of the continuous reference background level is realized by connecting the outputs Q 6 , Q 7  and Q 8  to inputs of the respective invertors 1, 2 and 3, outputs of which drive three inputs of an inverting AND gate 10. Thus, the output signal s 32  has the 0 level when Q 6  =Q 7  =Q 8  =0 and the 1 level in all the other cases, that is to say, as soon as the black background level reaches the digital 32 value. In the MAC television transmission system, the correction of the continuous level is not effected on the black background level but on the grey level which corresponds to a value of 128 at the output of an 8-bit analog-to-digital converter. For the decoder (decoder D 128 ). it will be sufficient to take the high-order output Q 8  of the converter, producing directly the signal s 128 . s 128  has the 1 level as soon as the grey level reaches the 128 value. The signal S 32  is applied to one of two inputs of an AND gate 11 whose other input receives a logic signal S 0 , while S 0  has the logic 0 level when the reception takes place according to the MAC television transmission system and the logic 1 level for the PAL and SECAM television transmission systems. The signal s 128  is applied to one of two inputs of an AND gate 12, whose other input receives the logic signal S 0  reversed by an inverter 4. Outputs of the AND gates 11 and 12 are connected to inputs of an OR gate 13 delivering at an output the control signal S 1  for the current source I 1 . When S 0  =0 (MAC television transmission system) we have S 1  =s 128  ; and S 1  =s 32  when S 0  =1  (PAL or SECAM television transmission systems). The authorization signal p 1  appears at the beginning of each line by way of a 750 ns pulse for the MAC television transmission system and a pulse of 4 microseconds in the PAL or SECAM television transmission systems and is utilized for authorizing the control of the current source I 1  as will be discussed hereinafter. 
     FIG. 4 shows the operation of the automatic gain control from signal S 2  onwards. The signal S 2  is preferably a differential signal whose high level and low level are for example 200 mV apart, so as to drive the bases of transistors T 10  and T 11  constituting the inputs of a differential stage (signals e 10  and e 11 ). The emitters of transistors T 10  and T 11  are interconnected and connected to a current source I 12 . The collector of transistor T 10  is directly connected to a positive supply voltage source +V, while that of the transistor T 11  is connected to a current source I 11 . For example, when S 2  has a high level, the respective values of 2.2 V and 2 V can be obtained for e 10  and e 11  and vice versa for a low-level S 2 . The current source values of I 11  and I 12  are chosen differently so as to obtain different time constants for charging and discharging the capacitor C 2 . 
     A low value is chosen for the value of the current source I 11  in order to obtain a slow charging of the capacitor C 2 , for example, with a time constant t 1  of a few seconds, and a value which is distinctly higher for the current source I 12  so as to obtain a rapid discharging of the capacitor C 2  while avoiding complete saturation, for example, with a time constant t 2  of 500 microseconds. By way of example, I 11  =100 nA and I 12  =500 μA are possible for a capacitor C 2  having a value of 0.47 μF. 
     When the signal S 2  has the logic 1 value, e 11  &gt;e 10 , the transistor T 11  is conducting and the transistor T 10  is non-conducting. The capacitor C 2  is rapidly discharged owing to the current source I 12  because its current exceeds by far that of the current source I 11 . 
     When the signal S 2  has the logic 0 level, e 10  &gt;e 11 , the transistor T 10  is then in the conducting state and the transistor T 11  in the non-conducting state. The capacitor C 2  is slowly charged due to the low current value produced by the current source I 11 . 
     It should be noted, by way of variant, that the differential stage constituted by the transistors T 10  and T 11  can be replaced by two differential stages in a cascade arrangement. 
     FIG. 5 shows how the signal S 1  is utilized for controlling the current source I 1 . The signal S 1  is preferably a differential signal of which the high and low levels are 200 mV apart, for example, so as to drive the bases of the transistors T 1  and T 2  of a differential stage. For example, for the 1 level, the values of the signals e 1  and e 2  applied to the respective bases of the transistors T 1  and T 2  are 2.5 and 2.7 V, respectively, and 2.7 and 2.5 V, respectively, for the 0 level. The interconnected emitters of the transistors T 1  and T 2  are connected to the collector of a transistor T 4  whose emitter is connected to ground and whose base is connected to that of a transistor T 3 , forming therewith a current mirror circuit, whose emitter is connected to ground, whose base and collector are interconnected and which receives pulse p 1  across a resistor R 3  , so as to enable a correction of the continuous level only during a planned time interval. 
     Two transistors T 5  and T 6  are arranged in a current mirror circuit with the collectors of transistors T 1  and T 2 . The emitters of these transistors T 5  and T 6  are connected to a supply voltage source +V (for example 5 V), their bases are interconnected and their collectors are connected to those of transistors T 1  and T 2 . Furthermore, the base and the collector of the transistor T 5  can be directly interconnected or also, as shown, through the emitter-base path of a transistor T 7  whose collector is connected to ground. If one of the two signals selected by S 0 , S 32  or s 128 , has the 1 level, then e 2  &gt;e 1 , and the transistor T 2  is conducting while the transistor T 1  is non-conducting, and a discharging of the capacitor C 1  is achieved through transistor T 4  operating as the current source for the duration of the pulse p 1  which lowers a DC current level of the signal input of the amplifier A 1 . In contradistinction thereto, if one of the two selected signals s 32  or s 128  has the 0 level, then e 1  &gt;e 2 , and the transistor T 1  is conducting while the transistor T 2  is non-conducting. As the transistors T 5  and T 6  constitute a current mirror circuit, the capacitor C 1  is charged by the current of the same intensity as that passing through transistor T 4  and which passes through the transistor T 6  for the duration of the pulse p 1 , which makes the DC current level at the signal input of the amplifier A 1  rise again. 
     FIG. 8 shows the logic levels of the four high order outputs in the GRAY code of the analog-to-digital converter. It will be remembered that the GRAY code is a code for which any incrementation by a positive or negative unit of a number only changes one of the bits. In this special case, the GRAY code is chosen for its property of simplifying the logic for the logic levels to be processed. 
     A G 5  bit has the 0 level for the logic values between 0 and 15, and changes to the 1 level for the 16 value. It changes again each time a multiple of 32 is added to the 16 value, the last change, a return to zero, taking place for the 240 value. A G 6  bit has the 0 level for the logic values between 0 and 31 and changes to the 1 level for the 32 value. It changes again each time a multiple of 64 is added to the 32 value, the last change, a return to zero, taking place for the 224 value. A G 7  bit has the 0 level for the logic values between 0 and 63 and changes to the 1 level for the 64 value and returns to the zero level for the values superior to 192. A G 8  bit has the 0 level for the logic values between 0 and 127, and to the 1 level for the logic values between 128 and 256. 
     The signal s 17  must have the 0 level for the values between 0 and 15 and 240 and 256, and the 1 level if this is not the case. The latter happens when G 5  =G 6  =G 7  =0. The signal s 224  has the 0 level for the values between 0 and 223 and the 1 level for those comprised between 224 and 256. The latter happens when G 6  =G 7  =0 and G 8  =1. The signal s 32  has the 0 level for the values comprised between 0 and 31 and the 1 level for those comprised between 32 and 256. The latter happens when G 6  =G 7  =G 8  =0. 
     The signal s 128  finally corresponds directly to the logic output G 8 . 
     According to FIG. 9, the decoding of the stages discussed hereinbefore is realized from logic outputs G 5  to G 8  and their complements available in a logic TTL form. The general organization of the decoder consists in differential transmitter pairs coupled and spread out over three levels, with two differential pairs per level and switching current sources. The signals G 5 , G 6 , G 7  and G 8  are applied to the base of the respective transistors T 15 , T 16 , T 17 , T 18 , T&#39; 15 , T&#39; 16 , T&#39; 17  and T&#39; 18  whose collectors are connected to a supply voltage V, having the value of 5 V. 
     Eleven transistors T 60  to T 70  form eleven current sources and each receives on it base a same reference voltage V&#39;, and their emitters are connected to ground. The collectors of transistors T 60  and T 70  are connected to the emitters of respective transistors T 15  and T&#39; 15  across three level shifting diodes arranged in series and in the forward direction. The collectors of transistors T 61  and T 69  are connected to the respective emitters of the transistors T 16  and T&#39; 16  across two level shifting diodes arranged in series and in the forward direction. The collectors of the transistors T 62  and T 68  are connected to the respective emitters of the transistors T 17  and T&#39; 17  across one level shifting diode arranged in the forward direction. The collectors of transistors T 63  and T 67  are connected directly to the emitters of the respective transistors T 18  and T&#39; 18 . 
     The two differential pairs of each level are constituted by emitter-coupled transistors T 30 , T 31  and T 32 , T 33  for the first level, T 40 , T 41  and T 42 , T 43  for the second level and T 50 , T 51  and T 52 , T 53  for the third level. The interconnected emitters of the transistors T 30  and T 31 , T 32  and T 33 , T 40  and T 41 , T 42  and T 43 , T 50  and T 51 , and T 52  and T 53  are connected to the collectors of the respective transistors T 41 , T 43 , T 51 , T 53 , T 64  and T 65 . The collectors of the transistors T 30 , T 40  and T 50  are interconnected and connected to the base of a transistor T 20 , which is further connected to the supply voltage V via a resistor R. The collector of the transistor T 20  is connected to the supply voltage V. The collector of the transistor T 31  is connected to the base of a transistor T 21 , which is further connected to the supply voltage V via a resistor R. The collector of the transistor T 21  is connected to the supply voltage V. The collectors of the transistors T 32  and T 33  are connected to the bases of respective transistors T 22  and T 23 , which are further connected to the supply voltage V via respective two resistors R. The collectors of the transistors T 42  and T 52  are connected to the supply voltage source V. 
     The collectors of the transistors T 60  to T 63  are connected to the bases of the respective transistors T 50  ; T 40  and T 52  ; T 30  and T 42  ; and finally T 32 . The collectors of the transistors T 67  to T 70  are connected to the bases of the respective transistors T 33  ; T 31  and T 33  ; T 41  and T 53  ; and finally T 51 . The base of a transistor T 24  is connected to the collector of transistor T 66  and to the supply voltage V via a resistor having the value of R, its collector also being connected to the supply voltage V. 
     The signal s 17  is available between the emitters of the transistors T 20  and T 21 . This signal s 17  is a combination of two signals s 20  and s 21 , available at these emitters. As a matter of fact, when G 5  =G 6  =G 7  =0, the transistors T 31 , T 41  and T 51  are conducting and the transistors T 30 , T 40  and T 50  are non-conducting. The signal s 224  is available between the emitters of the transistors T 22  and T 24 . This signal s 224  is a combination of two signals s 22  and s 24 , available at these emitters. When G 6  =G 7  =0 and G 8  =1, the transistors T 32 , T 43  and T 53  are conducting. 
     The signal s 32  is available between the emitters of the transistors T 23  and T 24 . This signal s 32  is a combination of two signals s 23  and s 24  available at these emitters. 
     When G 6  =G 7  =G 8  =0, the transistors T 37 , T 43  and T 53  are conducting. 
     Finally, the signal s 128  is directly available between the emitters of the transistors T 18  and T&#39; 18 . This signal s 128  is a combination of two signals s 18  and s&#39; 18   available at the emitters of these transistors. 
     As shown in FIG. 10, an output signal s&#39; 2  is obtained from the signals s 20 , s 21 , s 22 , s 24 , p 2  and S 0 . 
     Two differential pairs, constituted by emitter-coupled transistors T 71  and T 72 , T 73  and T 74  respectively, receiving on their bases the respective signals s 20 , s 21 , s 22  and s 24 , form a control level. The collectors of the transistors T 71  and T 73  are interconnected and coupled to the supply voltage V via a resistor R&#39;. Also, the collectors of the transistors T 72  and T 74  are interconnected and coupled to the supply voltage V via a resistor R&#39;. 
     A first switching level is formed by a differential pair comprising two emitter-coupled transistors T 75  and T 76  receiving on their bases the signal p 2  and a reference voltage signal V REF .sbsb.1, respectively. The collector of the transistor T 75  is connected to the coupled emitters of the transistors T 71  and T 72 , while the collector of the transistor T 76  is connected to the interconnected collectors of the transistors T 71  and T 73 . 
     A second switching level is formed by a differential pair comprising two emitter-coupled transistors T 77  and T 78  receiving on their respective bases a reference voltage signal V REF .sbsb.2 and the signal S 0  level-shifted by a diode voltage. 
     The collectors of the transistors T 77  and T 78  are connected to the coupled emitters of the transistor T 75  and T 76 , on the one hand, and T 73  and T 74 , on the other hand, respectively. A current source I 4  referenced to earth is connected to the coupled emitters of the transistors T 77  and T 78 . 
     When S 0  has a high level (operation according to the PAL or SECAM television transmission system); the transistor T 78  is conducting and the output signal s&#39; 2  corresponds to the logic state of the signal s 224  (signals s 22  and s 24 ). When S 0  has a low level, the transistor T 77  is conducting and the output signal s&#39; 2  corresponds to the logic state of the signal s 17  (signal s 20  and s 22 ). When the signal p 2  has the 1 level, the transistor T 75  is conducting. When the signal p 2  has the 0 level, the transistor T 76  is conducting and the collector of the transmitter T 71  retains the low level whatever logic state the inputs s 20  and s 21  have, and the signal s&#39; 2  is kept at the 0 level, producing a slow charging of the capacitor C 2  by the current source I 11  (FIG. 4). 
     To obtain the signal S 2 , from the signal s&#39; 2  the signals present at the collectors of the transistors T 71  and T 72  are applied to the bases of respective transistors T 79  and T 80  inserted as emitter-followers, whose collectors are connected to the voltage source V, and whose emitters are coupled to ground via resistors R&#34;, to whose terminals are connected capacitors C&#34; in parallel and respective current sources J 1  and J 2 , the points A and B denoting the terminals common to the resistors R&#34; and the current source J 1  and J 2 , respectively. 
     In the couplings of collectors of the transistors T 71  and T 72  to the supply voltage V, resistors R&#39; are used for adjusting the differential voltage of S 2 . For example, with R&#39;=1.6 kΩ and I 1  =150 μA, a differential voltage of 240 mV is obtained. 
     Assuming that V A  and V B  are the voltages at points A and B, 
     
         V.sub.A =V-V.sub.be -R&#34;J.sub.1 -R&#39;I.sub.1 k 
    
     
         V.sub.B =V-V.sub.be -R&#34;J.sub.2 -R&#39;I.sub.1 (1-k) 
    
     in which V be  denotes the base-emitter voltage drop of a transistor and k has the 0 or 1 value according to the switching direction of the differential pairs. When V=5 Volts, R&#34;=9.7 kΩ, J 1  =J 2  100 μA, R&#39;=1.6 kΩ I 1  =150 μA and V be  =0.8 V we obtain: 
     
         for k=0 V.sub.A =2.4648 V V.sub.b =2.408 V 
    
     
         for k=1 V.sub.A =2.408 V V.sub.b =2.648 V. 
    
     As shown in FIG. 11, the output signal s&#39; 1  is obtained from the signals s 23 , s 24 , s 18 , s&#39; 18  and S 0 . 
     Two differential pairs constituted by emitter-coupled transistors T 81  and T 82 , T 83  and T 84 , respectively, receiving on their bases the respective signals s 23  and s 24  (together s 32 ), on the one hand, and s 18  and s&#39; 18  (together s 128 ), form a control level. The collectors of the transistors T 81  and T 82 , on the one hand, and T 82  and T 84 , on the other, are interconnected and coupled to the supply voltage V via resistors R&#39;. 
     A switching level is constituted by a differential pair comprising two emitter-coupled transistors T 85  and T 86  receiving on their bases the respective signal S 0  and reference voltage signal V REF .sbsb.2. The collector of transistor T 85  is connected to the interconnected emitters of the transistors T 81  and T 82 , while the collector of the transistor T 86  is connected to the interconnected emitters of transistors T 83  and T 84 . A current source I 3 , which has a first terminal being connected to ground, has a second terminal connected to the interconnected emitters of the transistors T 85  and T 86 . When S 0  has a high level (operation according to the PAL or SECAM television transmission system), the transistor T 85  is conducting and the output signal S i  corresponds to the logic state of the signal s 32  (signals s 23  and s 24 ). When S 0  has a low level (operation according to the MAC standard), the transistor T 86  is conducting and the output signal s 1  corresponds to the logic state of the signal s 128  (signals s 18  and s&#39; 18 ). 
     The signal S 1  can be obtained from the signal S&#39; 1  in the same manner as the signal S 2  is obtained from the signal S&#39; 2 .