Abstract:
Control method and related controller, applicable to a power supply with a switch and an inductive device. The inductive current through the inductive device is sensed. An operating frequency of the switch is controlled to make an average of the inductive current substantially equal to a predetermined portion of the peak of the inductive current and to make the inductive device operated in continuous conduction mode.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention is related to a switched-mode power supply (SMPS), and more particularly, to an SMPS which provides constant voltage and constant current functions. 
         [0003]    2. Description of the Prior Art 
         [0004]    A power supply is used as a power management device for converting a power source to be supplied to other electronic devices or components. Certain power converters are required to have both constant voltage and constant current functions. For instance, a battery charger requires both constant voltage and constant current functions. The battery charger shall provide an approximately constant output current for charging a rechargeable battery that is not fully charged; it, nevertheless, shall provide an approximately constant output voltage when a rechargeable battery is fully charged, or when the rechargeable battery is non-existent. In other cases, LED drivers are also required to possess both constant voltage and constant current functions. 
         [0005]    U.S. Pat. No. 7,414,865 discloses an SMPS which has constant current functionality. In an embodiment of U.S. Pat. No. 7,414,865, discharge time for a transformer to completely discharge its magnetic energy is detected in a power converter. However, as shown in the cover page of U.S. Pat. No. 7,414,865, when applied to an integrated circuit, the integrated circuit requires one pin to perform the detecting action. 
       SUMMARY OF THE INVENTION 
       [0006]    The present invention discloses a control method for a power supply with a switch and an inductive device. The control method comprises detecting an inductive current flowing though the inductive device; and controlling an operating frequency of the switch for causing an average of the inductive current to substantially equal a predetermined portion of a peak current of the inductive current, wherein the predetermined portion approximately allows the inductive device to operate in a continuous conduction mode. 
         [0007]    The present invention further discloses a controller for a switched-mode power supply (SMPS). The SMPS comprises an inductive device and a switch for energizing or de-energizing the inductive device. The controller comprises an average current comparator and a frequency-controllable oscillator. The average current comparator is for determining if an average of the inductive current is higher than a predetermined portion of a peak current of the inductive current and generating an output signal. The frequency-controllable oscillator is for generating an operating frequency of the switch, wherein when the SMPS provides a constant output current, the output signal affects the operating frequency, the average of the inductive current approximately equals the predetermined portion of the peak current of the inductive current, and the inductive device operates in a continuous conduction mode. 
         [0008]    The present invention further discloses a control method for a power supply with a switch and an inductive device. The control method comprises detecting an inductive current flowing though the inductive device; checking if an output current exceeds a predetermined value, using an OFF time of the switch and a representative substantially representing an average of the inductive current; and controlling an operating frequency of the switch for causing the inductive device to operate in a continuous conduction mode if the output current exceeds the predetermined value. 
         [0009]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1  is a diagram illustrating SMPS for converting alternating-current (AC) power source to output power source of a desired specification. 
           [0011]      FIG. 2  is a diagram illustrating controller and feedback circuit to be used in SMPS of  FIG. 1 . 
           [0012]      FIG. 3  illustrates an embodiment of average current comparator for controller in  FIG. 2 . 
           [0013]      FIG. 4  illustrates an embodiment of constant current examining circuit for controller in  FIG. 2 . 
           [0014]      FIG. 5  illustrates an embodiment of frequency determining circuit for controller in  FIG. 2 . 
           [0015]      FIG. 6  is a diagram illustrating SMPS according to another embodiment of the present invention. 
           [0016]      FIG. 7  illustrates controller for SMPS in  FIG. 6 . 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    An embodiment of the present invention provides an SMPS for which it is unnecessary to detect the discharge time of a transformer, so as to achieve constant current functionality. 
         [0018]    It is known by those skilled in the art that an SMPS operates in two modes: discontinuous conduction mode (DCM) and continuous conduction mode (CCM). DCM indicates that an inductive device, such as a transformer, in an SMPS is completely de-energized in every switch cycle. In other words, the inductive device in DCM has no current flowing through it for a period of time every switch cycle. On the other hand, the inductive device in CCM does not de-energize completely in one switch cycle. A critical mode or boundary mode is an operation mode approximately between DCM and CCM, indicating that the inductive device starts being energized almost right after the completion of being de-energized. 
         [0019]    An SMPS according to an embodiment of the present invention can operate in DCM or CCM when providing a constant voltage function. 
         [0020]    An SMPS according to another embodiment of the present invention approximately operates in CCM when providing a constant current function. Therefore, the discharge time of an inductive device, the time period during that the inductive device is de-energized to charge a load, approximately equals a turned off time of a power switch in the SMPS. Once the average current inputted to the inductive device during a turned on time of the power switch is detected, the average output current for the inductive device outputting to the load can be approximately derived. By comparing the average output current with an expected constant current, the result can be fed back to control or alter the magnitude of the average output current, thereby, achieving constant current control. 
         [0021]      FIG. 1  is a diagram illustrating SMPS  60  for converting alternating-current (AC) power source V AV  to output power source V OUT  of a desired specification. Bridge rectifier  62  roughly rectifies AC power source V AC . Power switch  72 , which is controlled by gate signal S G , controls current of primary coil L p  in transformer  64 . When power switch  72  is turned on, transformer  64  is energized; when power switch  72  is turned off, transformer  64  is de-energized via secondary coil L s . Through rectifier  66 , the de-energized electrical energy is stored in output capacitor  69  for generating output power source V OUT . Feedback circuit  68  monitors magnitude of output power source V OUT  (e.g. current, voltage or power) , so as to provide compensation signal V COM  to controller  74  accordingly. Controller  74  further receives detection signal V CS  generated by current sense resistor CS to switch power switch  72  periodically. According to different embodiments of the present invention, controller  74  can be an integrated circuit alone, or be integrated with power switch  72  to be an integrated circuit. 
         [0022]      FIG. 2  is a diagram illustrating controller  74   a  and feedback circuit  68   a  to be used in SMPS  60  of  FIG. 1 . Feedback circuit  68   a  comprises photo coupler  280  and compensation capacitor  282 . For instance, brightness of a light emitting diode (LED) in photo coupler  280  increases with the voltage level of output power source V OUT , subsequently increasing the current drained from controller  74   a  and decreasing the voltage level of compensation signal V COM . When switch  218  is turned on (e.g. shorted), resistor  202  and light coupler  280  in combination approximately determine the voltage level of compensation signal V COM  while compensation capacitor  282  keeps compensation signal V COM  approximately at a quasi-steady state. 
         [0023]    In controller  74   a,  voltage level of compensation signal V COM  is stepped down by diode  214 , and divided by resistors  208 ,  209  and  210 , to generate restricted compensation signal V COMR . Restricted compensation signal V COMR  is compared with detection signal V CS  by comparator  204  and the comparison result is outputted to control power switch  72  via driving circuit  206 . Therefore, voltage level of restricted compensation signal V COMR  approximately corresponds to peak voltage of detection signal V CS , which roughly determines the amount of electrical energy converted by transformer  64  in one switch cycle. 
         [0024]    Controller  74   a  further comprises average current comparator  228 , constant current examining circuit  222 , frequency determining circuit  224  and voltage-controlled oscillator (VCO)  226 . Average current comparator  228  receives detection signal V CS  and signal V COMR-MEAN , and determines if average voltage of detection signal V CS  is higher than voltage level of signal V COMR-MEAN , so as to output indication signal S OVER  accordingly. Logic “1” of indication signal S OVER  indicates that average voltage of detection signal V CS  is higher than the voltage level of signal V COMR-MEAN . According to signal V COMR-MEAN  and clock signal S CLK , constant current examining circuit  222  determines if average output current of secondary coil L s  in a current cycle exceeds a predetermined current value, so as to output limit signal S LIMIT . When limit signal S LIMIT  is logic “1”, meaning average output current of secondary coil L s  in the current switch cycle has exceeded the predetermined current value, limit signal S LIMIT  of logic “1” turns off switch  218 , so voltage levels of compensation signal V COM  and signal V COMR-MEAN  drop gradually, consequently decreasing average output current in following switch cycles. Frequency determining circuit  224  generates frequency voltage V FRG  according to limit signal S LIMIT  and indication signal S OVER . VCO  226  determines frequency of clock signal S CLK  according to frequency voltage V FRG . 
         [0025]    When executing constant current function, average current comparator  228 , frequency determining circuit  224  and VCO  226  as well form a negative feedback loop, causing average voltage of detection signal V CS  to approximately equal signal V COMR-MEAN , and SMPS  60  to operate in CCM. For ensuring SMPS  60  is operating in CCM, voltage level of signal V COMR-MEAN  should be at least equal, or above, half of voltage level of restricted compensation signal V COMR . Taking signal delay into account, resistance ratio of resistors  210  and  209  can be selected to cause signal V COMR-MEAN =0.6* restricted compensation signal V COMR . Average voltage of detection signal V CS  approximately corresponds to average current of primary coil L p ; restricted compensation signal V COMR  approximately corresponds to peak current of primary coil L p . In other words, when executing constant current function, average current of primary coil L p  is approximately proportional to peak current of primary coil L p  by a predetermined ratio, which, for operating in CCM, should be approximately between 0.5 and 1, such as 0.6. 
         [0026]      FIG. 3  illustrates an embodiment of average current comparator  228   a  for controller  74   a  in  FIG. 2 . Simply put, average current comparator  228   a  compares the duration when detection signal V CS  is higher than signal V COMR-MEAN , with the duration when detection signal V CS  is lower than signal V COMR-MEAN . If the former duration (i.e. the duration of when voltage level of detection signal V CS  is higher than that of signal V COMR-MEAN ) is longer, voltage level of capacitor  366  increases as the switch cycle increases; and vice versa. Therefore, if voltage level of capacitor  366  is higher than reference voltage V REF-MEAN  after a few switch cycles, average voltage of detection signal V CS  can be determined to be approximately higher than signal V COMR-MEAN . Otherwise if voltage level of capacitor  366  is lower than reference voltage V REF-MEAN , average voltage of detection signal V cs  can be determined to be lower than signal V COMR-MEAN . D flip-flop causes indication signal S OVER  to be updated once per switch cycle, so logic level of indication signal S OVER  indicates if average voltage of detection signal V cs  is higher than signal V COMR-MEAN . 
         [0027]      FIG. 4  illustrates an embodiment of constant current examining circuit  222   a  for controller  74   a  in  FIG. 2 . When operating in CCM, average output current of secondary coil L s  is approximately proportional to average voltage of detection signal V CS  when power switch  72  is turned off. As mentioned above, when executing constant current function, signal V COMR-MEAN  approximately represents average voltage of detection signal V CS . Therefore, signal V COMR-MEAN  can be utilized to determine if total output electrical charge output from secondary coil L s  equals that of a predetermined output current. The following formula can be extrapolated from the circuit in  FIG. 4 : 
         [0000]      Δ V   CC-CAP   =I   COMP-MEAN   *T   OFF   I   SET   *T   CYCLE  
 
         [0000]    where ΔV CC-CAP  represents the variation of voltage V CC-CAP  after a switch cycle; I COMR-MEAN  represents current converted from signal V COMR-MEAN l T OFF  represents the duration when power switch  72  is turned off, equivalent to the discharge time of secondary coil L s ; I SET  is a predetermined current corresponding to an expected constant output current for the load; T CYCLE  represents the period of a switch cycle. If voltage V CC-CAP  is higher than constant current reference voltage V REF-CC , then the average output current of secondary coil L s  can be determined to be higher than the expected constant output current for the load. Accordingly, D flip-flop causes limit signal S LIMIT  to be logic “1”, stopping voltage level of restricted compensation signal V COMR  from increasing. At this moment, voltage level of restricted compensation signal V COMR  decreases due to discharging of light coupler  280  or resistors  208 ,  209 . 
         [0028]      FIG. 5  illustrates an embodiment of frequency determining circuit  224   a  for controller  74   a  in  FIG. 2 . In frequency determining circuit  224   a,  when indication signal S OVER  is logic “1”, frequency of clock signal S CLK  approaches minimum frequency f MIN  which corresponds to minimum voltage V FRG-MIN , causing average voltage of detection signal V CS  to drop gradually. When limit signal S LIMIT  is logic “0” (e.g. average output current of secondary coil L s  has not exceeded a predetermined value) and indication signal S OVER  is also logic “0”, it can be deemed that SMPS  60  is required to approach constant voltage operation, so the frequency of clock signal S CLK  approaches normal operating frequency f FIX . When limit signal S LIMIT  is logic “1” (e.g. average output current of secondary coil L s  is assumed to have exceeded a predetermined value) and indication signal S OVER  is logic “0”, frequency of clock signal S CLK  approaches maximum frequency f MAX  which corresponds to maximum voltage V FRG-MAX , causing average voltage of detection signal V CS  to increase gradually. Alternatively, it is recommended that frequency voltage V FRG  approaches minimum voltage V FRG-MIN  or maximum voltage V FRG-MAX  higher than it does normal operating voltage V FRG-FIX , which corresponds to operating frequency f FIX . For instance, assuming G FIX , G MAX  and G MIN  represent transconductance gain of transconductance (GM) amplifier  150  when frequency of clock signal S CLK  approaches operating frequencies f FIX , f MAX  and f MIN , respectively, gain G FIX  is less than gains G MAX  and G MIN  in one embodiment. In  FIG. 5 , when frequency of clock signal S CLK  approaches normal operating frequency f FIX , transconductance gain of GM amplifier  150  decreases accordingly. 
         [0029]    The following scenarios can be acquired according to the logic of frequency determining circuit  224 . 
         [0000]    1. Average voltage of detection signal V CS  is approximately not higher than voltage level of signal V COMR-MEAN , since when indication signal S OVER  is logic “1”, frequency of clock signal S CLK  drops, further decreasing average voltage of detection signal V CS  in the next switch cycle.
 
2. Limit signal S LIMIT  is fixed at logic “0” and SMPS  60  may approximately operate at normal operating frequency f FIX  when average output current of secondary coil L s  is continuously lower than expected constant output current for the load, such as under light load or no load.
 
3. Constant current function is achieved when limit signal S LIMIT  switches between logic “1” and “0” frequently. At this time, frequency of clock signal S CLK  may increase or decrease, so as to approach the frequency that makes the average voltage of detection signal V CS  equal to signal V COMR-MEAN . Both voltage variation of compensation signal V COMR  and frequency variation of clock signal S CLK  cause subsequent limit signal S LIMIT  to change state, achieving constant output current.
 
         [0030]    One of the advantages of the present embodiment is elimination of detecting the discharge time of secondary coil L s . If the present embodiment is applied to a low-voltage startup integrated circuit, SMPS  60  may only require 5 pins, named respectively as CS, COM, GATE, VCC and GND, for achieving constant output current and constant output voltage functions. 
         [0031]    Although the above embodiment is exemplified by a secondary-side control circuit, the present invention is also applicable to a primary-side control circuit, as shown by SMPS  61  in  FIG. 6 . The difference between  FIG. 6  and  FIG. 1  is that controller  75  of SMPS  61  detects voltage of secondary coil L s , which is substantially equal to the voltage of output power source V OUT , via a voltage divider (e.g. consisting of two resistors) and auxiliary coil L a .  FIG. 7  illustrates controller  75   a  for SMPS  61  in  FIG. 6 . Sampling circuit  292  samples voltage at node FB. GM amplifier  290  compares voltage held by sampling circuit  292  with reference voltage V REF-CV  for generating current to charge or discharge compensation capacitor  282 . When limit signal S LIMIT  is logic “1”, GM amplifier  290  is disabled, so voltage level of compensation signal V COM  decreases due to the discharge of resistors  208 ,  209  and  210 . Other components in  FIG. 6  and  FIG. 7  are similar to the embodiments mentioned before, or can be extrapolated by those skilled in the art according to the above description, so relative description is omitted hereinafter. SMPS  61  in  FIG. 6  can also provide constant current and constant voltage functions. 
         [0032]    Although the invention is exemplified as applied to an SMPS having flyback architecture, it is not limited thereto, and can be applied to SMPSs having other architectures, such as buck converters, boost converters and the like. 
         [0033]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.