Abstract:
Certain GaAs FET devices are employed to accomplish low noise performance and simultaneous high power handling capability, i.e. high dynamic range performance, in an amplifier using larger GaAs FET devices. Such devices are incorporated in different circuit configurations to achieve amplifiers having, simultaneously, a low noise figure, higher input/output intercept performance, higher output power, and improved ruggedness toward high input interfering signals, while not sacrificing other highly desirable terminal characteristics, (i.e. gain, VSWR, etc.).

Description:
FIELD OF THE INVENTION 
     This invention relates to low noise wide dynamic range electronic amplifiers. 
     DESCRIPTION OF THE PRIOR ART 
     Low noise wide dynamic range amplifiers are used where a desired signal must be detected and amplified in the presence of spurious noise signals. GaAs FET transistors are low noise semiconductor devices and have been employed in low noise, low power amplifiers. Bipolar transistors have also been used in medium and high power amplifiers but these bipolar transistors are not used where low noise performance is required; hence, only low power amplifiers are known in the prior art for low noise applications. 
     SUMMARY OF THE INVENTION 
     Noise is a broadband electromagnetic field, generated by various environmental effects and artificial devices. Noise can be categorized as either natural or man-made. Natural noise may be either thermal or electrical in origin. All objects radiate noise as a result of their thermal energy content. This is known a black-body radiation. 
     Electromagnetic noise is produced by many different man-made devices. In general, any circuit or appliance that produces electric arcing will produce noise. 
     The level of electromagnetic noise affects the ease with which radio frequency communications can be carried out. The higher the noise level, the stronger a signal must be if it is to be received. The signal-to-noise ratio can be maximized in a variety of ways. The narrower the bandwidth of the transmitted signal, and the narrower the passband of the receiver, the better the signal-to-noise ratio at a given frequency. This improvement occurs, however, at the expense of data transmission speed capability. Circuits such as noise blankers and limiters are sometimes helpful in improving the signal-to-noise ratio. Noise reducing antennas can also be used to advantage in some cases. There is a limit to how much the noise level can be reduced; a certain amount of noise always exists. 
     This invention is a high power electronic amplifier which has excellent low noise performance which is commensurate with the prior art low noise, low power amplifiers. 
     Many electronic systems such as radar communications receivers require the capability to receive low level signals in the presence of large spurious signals. Most modern low noise solid state receivers operating in the frequency ranges of VHF through microwave employ GaAs field effect transistors as the input stages of the amplifier chain. These transistors are designed with very fine line geometries which improve the high frequency performance and enhance the inherent low noise characteristics of such devices. An attendant characteristic of GaAs FET (MESFET) designed in this way is that the power handling capability is relatively small. Typical state of the art low noise MESFETs with 0.3 to 0.5 micron gate widths provide low noise operation when biased for a drain current, I ds , in the 5 to 15 mA range and a drain to source voltage, VDS, of 2-4 volts. This low level bias condition results in low power handling capability (approximately +5 to +1-dBm for the bias point range specified). One method to improve the low power performance is to parallel a number of such stages thereby splitting the incoming signal to be processed by each cell of the parallel combination. The separately amplified signals are then recombined at the output port of the paralleled transistors. The invention employs such combining to prove that the power handling capability increases by approximately 3 dB each time the number of cells is doubled while the intrinsic noise figure of the combination remains essentially constant. Paralleling devices has limitations due to differences in processing parameters during fabrication. Discrete device parameters such as g m , V p , I dss , etc., can vary as much as ±30% from the typical values. These differences cause the bias conditions as well as the RF performance of the various cells of the parallel combination to vary. For optimum performance, each of the cells should be as identical as possible. This can be accomplished by fabricating the parallel configuration in a single chip. Such devices have been fabricated and already exist as commercially available transistors which were designed and intended for use as power amplifiers rather than in low noise applications. The manufacturers do not list noise figure in the specification sheets for such transistors and one would not expect large signal devices to display good low noise performance. 
     These devices are employed to accomplish low noise performance and simultaneous high power handling capability, i.e. high dynamic range performance. The wide dynamic range performance can be achieved in an amplifier using power GaAs FET devices by incorporating them in any one of the circuit configurations described herein to achieve simultaneously, a low noise figure, higher input/output intercept performance, higher output power, and improved ruggedness toward high input interfering signals, while not sacrificing other desirable terminal characteristics, (i.e. gain, VSWR, etc.). 
     A principal object of our invention is the provision of a low noise wide dynamic range amplifier. Another object and advantage of our invention is the provision of high power amplifiers which have excellent low noise performance. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These as well as further objects and advantages of the invention will become apparent to those skilled in the art from a review of the following detailed specification reference being made to the accompanying drawings in which: 
     FIG. 1 is a schematic diagram of the circuit of the invention; 
     FIG. 2 is a block diagram of a single stage configuration using the circuit of FIG. 1 according to the invention, with the value of R f  =∞; 
     FIG. 3 is a block diagram of a feedback circuit using the schematic of FIG. 1 in another embodiment of the invention; and 
     FIG. 4 is a block diagram of a multipath circuit employing the schematic of FIG. 1 
     FIG. 5 is a schematic diagram of the circuit of FIG. 1. with active feedback elements. 
     FIG. 6 is a schematic diagram of a circuit which may be employed having an active input impedance matching element. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 is a schematic diagram of one embodiment of the invention employing a GaAs FET, Q1, connected in the configuration shown in FIG. 3. The RF input terminal is coupled to the gate of transistor Q1 via capacitors C1, C2, C3 and inductors L1 and L3. Capacitor C1 serves as a DC blocking capacitor and also provides some impedance matching at low frequencies. Inductor L1 together with capacitors C2 and C3 act as a low pass impedance matching circuit. Inductor L2 can serve as either an RF choke, or an impedance matching element depending on the frequency, and/or the bandwidth requirements. 
     The connection node &#34;P&#34;, at the junction of L1, L3 and C3 also is fed by a voltage divider comprised of resistors R1 and R2 to set the gate to source voltage and thus, the DC operating point of Q1. All inductors may be lumped or distributed depending on the operating frequency range and serve to adjust the gain slope of Q1 and provide for impedance matching. 
     A feedback network comprised of capacitor C5, resistor Rf, and inductor L5 is connected between node &#34;P&#34; and the junction of inductor L4, L6 and L7. Capacitor C5 is a large value DC blocking capacitor. Resistor Rf and inductor L5 serve to adjust the gain and terminal impedance of the amplifier. In the RF output portion of the circuit, inductor L6 and capacitor C6 serve as a low pass output matching circuit. AC bypass capacitors C4, C9, C7 and C8 are selected in the usual manner. Capacitor C10 is typically selected as a DC blocking capacitor, but can serve as an impedance matching element as well. Resistor R3 sets the DC operating voltage of Q1. 
     Additional circuit configurations are provided in other embodiments of the invention shown in FIGS. 2-4. FIG. 2 shows a single stage implementation. FIG. 3 is a feedback network and FIG. 4 is a multi-path network. In FIGS. 2-4. IMN=input matching network; OMN=output matching network; FET=GaAs FET device; and FBN=feedback network. Examples of such combinations are cascade connection, parallel connection in (N×M) matrix connections. Input and output matching networks IMN and OMN refer to any combination of passive elements (resistors, capacitors, inductors, transformers, transmission line couplers, etc.), or active elements (transistors). Feedback networks can be any combination of circuit elements similar to the aforementioned input matching networks or output matching networks. Location of the connection points of any feedback networks is considered arbitrary and optional; however, in certain applications, such as those shown in FIGS. 1-3, feedback networks are required as a significant part of the circuit scheme needed to realize the full advantage of the invention. The N-way signal splitting and combining networks in FIG. 4 is any combination of passive circuit elements which provide the signal splitting and combining function. 
     FIG. 5 is a schematic diagram of the circuit of FIG. 1 with active feedback elements in the circuit. In FIG. 5, a second transistor Q2 is connected in the feedback loop across Q1. 
     FIG. 6 is a schematic diagram of a circuit which may be employed having an active input impedance matching element. The following table described the circuit elements of FIG. 5: 
     
         ______________________________________ELEMENT    FUNCTION______________________________________C1         DC BLOCKING CAPACITORC6         &#34;C7         &#34; C10       &#34;L1         INPUT MATCHINGC2         &#34;L4         INTER STAGE MATCHINGC5         &#34;C8         OUTPUT MATCHINGL6         &#34;L2         RF BLOCKING CHOKEL3         &#34;L5         &#34;C3         RF BYPASSC4         &#34;C9         &#34;RB         SOURCE SELF-BIAS RESISTORR1         DRAIN BIAS RESISTOR (Q1)RF         Q2 FEEDBACK RESISTORR2         DRAIN BIAS RESISTOR (Q2)Q1         ACTIVE INPUT IMPEDANCE      TRANSFORMERQ2         GaAs FET amplifier akin to Q1 of FIG. 1______________________________________ 
    
     The following are examples of circuits constructed in accordance with our invention: 
     EXAMPLES 
     
         ______________________________________  EXAMPLES  1         2           3______________________________________C1       0           100 pf      1000 pf 470 pfC2       2 pf        0           6.8 pfC3       0           0           0C4       100 pf      .01 uf      1000 pfC5       10 pf       .10 uf      1000 pfC6       0           0           1 pfC7       100 pf      .01 uf      1000 pfC8       .1 uf       .1 uf       .1 ufC9       .01 uf      .1 uf       .1 ufC10      100 pf      1000 pf     33 pfL1       0           8 nH        18 nHL2       5 nH        10K ohms    25 nHL3       P.L.        P.L.        P.L.    .2&#34; L × .1&#34; W                .3&#34; L × .1&#34; W                            .2&#34; L × .1&#34; WL4       0           P.L.        P.L.                .2&#34; L × .1&#34; W                            .2&#34; L × .1&#34; WL5       22 nH       24 nH       22 nHL6       3 nH        1:2 transformer                            1:4 transformerL7       3.5 nH      .22 uH      18 nHR1       10K ohms    10K ohms    10k ohmsR2       select @ test                select @ test                            select @ testRf       10K ohms    330 ohms    750 ohmsR3       20 ohms     6.5 ohms    13 ohms-Vg      -5V         -5V         -5V+V       12 V        12 V        12 VELECTRICAL PERFORMANCE ACHIEVEDFreq.    1025-1150 MHz                60-100 MHz  400-625 MHzGain     15 dB       16 dB       17 dBNoise    1.9 dB      2.0 dB      1.7 dBFigureVSWR     2.0:1 in/out                1.5:1/1.7:1 2.0:1 in/out(in/out)             in/outPwr. Output    +24 dBm     +28 dBm     +29 dBm3rd OrderIntercept    +36 dBm     +40 dBm     +41 dBmPoint______________________________________ 
    
     Typical characteristics of GaAs FET devices used in the above examples are: 
     
         ______________________________________Max. drain - source voltage (Vds)                 12-17     Vmax. power dissipation (watts @25° C.)                 4-8       WSaturated drain current (Idss)                 .25       minimumMax. gate-source voltage (Vgs)                 -5        VTransconductance (gm) 120-350   mSPinch-off voltage     -1 to -5  V______________________________________ 
    
     The upper ranges for the GaAs FET devices set forth above are not limiting but may increase by 50% from the values in the table above. 
     As modifications to the invention may be made without departing from the spirit and scope of our invention, what is sought to be protected is set forth in the appended claims.