Abstract:
A controller for interfacing a host and storage device is provided. The controller includes a channel that can receive data from the storage device in a first format and store the data in an intermediate buffer memory in a second format. The channel includes conversion logic that converts data from the first format to the second format and from the second format to the first format depending upon whether data is being read or written from the buffer memory. The conversion logic uses a shuttle register and shuttle counter for aligning data that is being transferred between the storage device and the buffer memory by appropriately concatenating data to meet the first and second format requirements. The first format is based on 10-bit symbols and the second format is based on 8-bits.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field Of the Invention  
         [0002]     The present invention relates generally to storage device controllers, and more particularly, to reading and writing data using a buffer controller.  
         [0003]     2. Background  
         [0004]     Conventional computer systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives) (referred to herein as “storage device”). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.  
         [0005]     The storage device is coupled to the host system via a controller that handles complex details of interfacing the storage devices to the host system. Communications between the host system and the controller is usually provided using one of a variety of standard I/O bus interfaces.  
         [0006]     Typically, when data is read from a storage device, a host system sends a read command to the controller, which stores the read command into the buffer memory. Data is read from the device and stored in the buffer memory.  
         [0007]     Previously data from a storage device was sent to the controller in 8-bit sizes (i.e. byte oriented where 1 byte is equal to 8 bits) and the controllers were designed to operate with 8-bit format. However, changes by some storage device manufacturers, for example, hard disk manufacturers, will now provide data in 10-bit format (i.e., symbol oriented where one symbol is equal to 10 bits). Other storage device manufacturers, for example, tape drives manufacturers, will continue to provide data in 8-bit format. Due to the disparity in data formats, conventional controllers fail to efficiently handle 8-bit to 10 bits and 10 bit to 8 bit conversion.  
         [0008]     Therefore, there is a need for a controller that can efficiently handle data transfer where data may enter the controller in more than one format.  
       SUMMARY OF THE INVENTION  
       [0009]     A controller for interfacing between a host and storage device is provided, according to one aspect of the present invention. The controller includes a channel that can receive data from the storage device in a first format and store the data in an intermediate buffer memory in a second format. The channel includes conversion logic that converts data from the first format to the second format and from the second format to the first format depending upon whether data is being read or written from the buffer memory.  
         [0010]     The conversion logic uses a shuttle register and shuttle counter for aligning data that is being transferred between the storage device and the buffer memory by appropriately concatenating data to meet the first and second format requirements. The first format is based on 10-bit symbols and the second format is based on 8-bits.  
         [0011]     In yet another aspect, a system for transferring data between a host system and a storage device is provided. The system includes, a controller that is coupled to a buffer memory and includes a channel that can receive data from the storage device in a first format and store the data in the buffer memory in a second format and the channel includes the conversion logic that converts data from the first format to the second format and from the second format to the first format depending upon whether data is being read or written from the buffer memory.  
         [0012]     In yet another aspect of the present invention, a method for transferring data between a storage device and a host system via a controller that is coupled to a buffer memory is provided. The method includes, determining if any conversion is required based on whether a storage device and the buffer memory support different data format; enabling data format conversion, if required; and converting data format conversion based on whether data is being read or written to the buffer memory.  
         [0013]     This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof concerning the attached drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures:  
         [0015]      FIG. 1A  shows a block diagram of a storage system used according to one aspect of the present invention;  
         [0016]      FIG. 1B  is a block diagram of a buffer controller, used according to one aspect of the present invention;  
         [0017]      FIG. 2A  shows the data path between a disk formatter and a buffer memory, according to one aspect of the present invention;  
         [0018]      FIG. 2B  shows the data path for Read-Long data, according to one aspect of the present invention;  
         [0019]      FIG. 3A  shows a block diagram of conversion logic, according to one aspect of the present invention;  
         [0020]     FIGS.  3 B(i)-(iv) (referred to as  FIG. 3B ) shows a table that aligns data into a shuttle register, according to one aspect of the present invention;  
         [0021]      FIG. 3C  shows a schematic of a MUX producing an output, according to one aspect of the present invention;  
         [0022]      FIG. 4  shows the read path during a buffer read operation, according to one aspect of the present invention;  
         [0023]      FIG. 5  shows the write path during a buffer read operation, according to one aspect of the present invention;  
         [0024]      FIG. 6  shows a block diagram for a channel (CH0) that facilitates buffer read and write operations, according to one aspect of the present invention;  
         [0025]      FIG. 7  shows a schematic of CH0 control logic with a state machine that interfaces with conversion logic, according to one aspect of the present invention;  
         [0026]      FIGS. 8 and 9  show the timing diagrams for the various signal for buffer write and read operations, according to one aspect of the present invention; and  
         [0027]      FIG. 10  shows a process flow diagram for data conversion and alignment, according to one aspect of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0028]     Controller Overview:  
         [0029]     To facilitate an understanding of the preferred embodiment, the general architecture and operation of a controller will initially be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture.  
         [0030]     The system of  FIG. 1A  is an example of a storage drive system (with an optical disk or tape drive), included in (or coupled to) a computer system. The host computer (not shown) and the storage device  110  (also referred to herein as disk  110 ) communicate via a port using a disk formatter “DF”  104 . In an alternate embodiment (not shown), the storage device  110  is an external storage device, which is connected to the host computer via a data bus. The data bus, for example, is a bus in accordance with a Small Computer System Interface (SCSI) specification. Those skilled in the art will appreciate that other communication buses known in the art can be used to transfer data between the drive and the host system.  
         [0031]     As shown in  FIG. 1A , the system includes controller  101 , which is coupled to buffer memory  111  and microprocessor  100 . Interface  109  serves to couple microprocessor bus  107  to microprocessor  100  and a micro-controller  102 . A read only memory (“ROM”) omitted from the drawing is used to store firmware code executed by microprocessor  100 . Host interface  103  in controller  101  interfaces with interface  104 A to communicate with a host system (not shown).  
         [0032]     Controller  101  can be an integrated circuit (IC) that comprises of various functional modules, which provide for the writing and reading of data stored on storage device  110 . Microprocessor  100  is coupled to controller  101  via interface  109  to facilitate transfer of data, address, timing and control information. Buffer memory  111  is coupled to controller  101  via ports to facilitate transfer of data, timing and address information. Buffer memory  111  may be a double data rate synchronous dynamic random access memory (“DDR-SDRAM”) or synchronous dynamic random access memory (“SDRAM”), or any other type of memory.  
         [0033]     Disk formatter  104  is connected to microprocessor bus  107  and to buffer controller  108 . A direct memory access (“DMA”) DMA interface (not shown) is connected to microprocessor bus  107  and to data and control port (not shown).  
         [0034]     Buffer controller (also referred to as “BC”)  108  connects buffer memory  111 , channel one (CH1)  105 , error correction code (“ECC”) module  106  and to bus  107 . Buffer controller  108  regulates data movement into and out of buffer memory  111 .  
         [0035]     Data flow between a host and disk passes through buffer memory  111 . ECC module  106  generates the ECC that is saved on disk  110  writes and provides correction mask to BC  108  for disk  110  read operation.  
         [0036]     Plural channels may be used to allow data flow. Channels (for example, channel 0 (“CH0”), channel 1 (“CH1”) and channel 2 (“CH2”)) are granted arbitration turns when they are allowed access to buffer memory  111  in high speed burst write or read for a certain number of clocks. The plural channels use first-in-first out (“FIFO”) type memories to store data that is in transit. CH1  105  may be inside BC  108  or outside BC  108 , as shown in  FIG. 1 . Another channel (CH2) may also be provided so that controller  101  can be used with different systems. Firmware running on processor  100  can access the channels based on bandwidth and other requirements. CH0  108 D within BC  108 , can process new symbol based (i.e. 10-bit) data format, according to one aspect of the present invention, as described below.  
         [0037]     To read data from device  110 , a host system sends a read command to controller  101 , which stores the read commands in buffer memory  111 . Microprocessor  100  then reads the command out of buffer memory  111  and initializes the various functional blocks of controller  101 . Data is read from device  110  and is passed to buffer controller  108 .  
         [0038]     To write data, a host system sends a write command to disk controller  101  and is stored in buffer  111 . Microprocessor  100  reads the command out of buffer  111  and sets up the appropriate registers. Data is transferred from the host and is first stored in buffer  111 , before being written to disk  110 . CRC values are calculated based on the logical block address (“LBA”) for the sector being written. Data is read out of buffer  111 , appended with ECC code and written to disk  110 .  
         [0039]     Buffer Controller  108 :  
         [0040]      FIG. 1B  shows a block diagram of BC  108  with CH0  108 D that interfaces with DF  104  for moving data to and from buffer  111 . BC  108  includes register(s)  108 E and an Arbiter  108 C. Arbiter  108 C arbitrates between plural channels in BC  108 , for example, CH0  108 D, and CH1  105  and CH2 (not shown). CH0  108 D interfaces with DF  104 , ECC module  106  and a DMA module (not shown).  
         [0041]     Register  108 E is coupled to interface  109  via bus  107  that allows microprocessor  100  and BC  108  to communicate. Data  108 G and status  108 F is moved in and out of register  108 E. Interface  108 K and  108 L allow BC  108  to interface with CH1  105  and CH2.  
         [0042]     BC  108  uses a data wedge format table “DWFT”  108 H to process a data wedge for disk operations.  
         [0043]     BC  108  also includes a memory controller  108 B that interfaces with buffer  111  through a synchronous dynamic random access memory (“SDRAM”) interface  108 J or DDR-SDRAM interface  108 A (referred to as DDR-EXT I/F in  FIG. 1B ). Interrupts  108 I are sent from buffer controller  108  to processor  100 .  
         [0044]     Data Format:  
         [0045]     Before describing CH0  108 D, the following provides a description of the data format as used by disk  110 . As stated earlier data to and from disk  110  is now preferably moved in a 10-bit format. Table 1 below shows a mapping between four symbols into five bytes. Symbol based data comes from DF  104  (i.e. disk  110 ). Symbol pairs are grouped and stored as sectors on disk  110 , i.e., the size of the sectors is an integer of the number of symbol pairs.  
                                                                 TABLE I                           Symbol   Bit Number            No.   9   8   7   6   5   4   3   2   1   0               0   B1-1   B1-0   B0-7   B0-6   B0-5   B0-4   B0-3   B0-2   B0-1   B0-0       1   B2-3   B2-2   B2-1   B2-0   B1-7   B1-6   B1-5   B1-4   B1-3   B1-2       2   B3-5   B3-4   B3-3   B3-2   B3-1   B3-0   B2-7   B2-6   B2-5   B2-4       3   B4-7   B4-6   B4-5   B4-4   B4-3   B4-2   B4-1   B4-0   B3-7   B3-6                  
 
         [0046]     The format of the data in buffer memory  111  is still in 8-bit sizes, i.e., byte oriented. Table II below shows the format of the data that is stored in buffer memory  111 . Data is aligned on a Mod 4 buffer address with a Mod 4 byte size. Data includes 4 bytes of cyclic redundancy code (“CRC”), if CRC is enabled.  
         [0047]     Table II below assumes a starting address of 0, however, the starting address could be any even multiple of 4.  
         [0048]     n=number of DWORDS in sector—a 516 byte sector has 129 (516/4=129) or 0-128.  
         [0049]     DWn=last DWORD in a sector  
         [0050]     Bn=last byte of data in the sector not including CRC  
         [0051]     Data represented in buffer memory  111  is typically the host data block. This data is written and read from disk  110 . The host data is in bytes and is written to and read from the disk  110  across a symbol based interface.  
                                                 TABLE II                           Dword   Bit   Buffer            Number   BD[31:24]   BD{23:16]   BD[15:8]   BD[7:0]   Address               0   B3   B2   B1   B0   0       1   B7   B6   B5   B4   3       .   .   .   .   .   .       .   .   .   .   .   .       .   .   .   .   .   .       DWn-1   Bn   Bn-1   Bn-2   Bn-3   (DWn-1 ×                           4) − 1       DWn   CRC-B3   CRC-B2   CRC-B1   CRC-B0   (DWn ×                           4) − 1                  
 
         [0052]     CH0  108 D logic provides access to buffer memory  111  with the byte based data format, and access the DF  104  symbol based format, and translates between the two formats, according to one aspect of the present invention, as described below.  
         [0053]     Channel 0  108 D:  
         [0054]     It is noteworthy that although the description below is based on a data format size of 10 bit and 8 bit, the adaptive aspects of the present invention are not limited to these two sizes. For example, data from disk  110  can be in X-bit format and stored in buffer  111  in Y-bit format, and CH0  108 D architecture allows translation between the two formats (i.e. X and Y bit formats).  
         [0055]      FIG. 2A  shows a block diagram with the data path between DF  104  and buffer memory  111 . Data  200  as 10-bit symbols is sent or read from DF  104  via bus  200 A. CH0 FIFO  201  is used to store data when it is being transferred between buffer memory  111  and DF  104 . Logic  202  converts the data format from 10-bit to 8-bit and 8-bit to 10-bit. Logic  203  receives data to and from buffer  111  and logic  202 . Data  204  is 8-bit bytes that is received from or sent to buffer memory  111  via bus  204 A. Bus  202 A is 80-bit wide and  203 A is 64-bit wide.  
         [0056]     Buffer  111  Read Operations:  
         [0057]     When data is read from buffer memory  111  and sent to DF  104 , it can start at any memory address. CH0 logic  203  reads data from interface  108 J or  108 A (may be referenced interchangeably as interface  108 J) and passes the data to logic  202 . Logic  202  assembles 80-bit words to write into FIFO  201 . The last symbol that is written into FIFO  201  includes pad bits if the transfer size length in bits (plus CRC bits) is not MOD10. Filler bits may also be used to achieve MOD8 symbol size on a last FIFO write, as described below. “MOD” in this context, as used throughout this specification, means the data alignment.  
         [0058]     Buffer  111  Write Operations:  
         [0059]     Buffer write operation involves moving data from DF  104  (as shown in  FIG. 2A ) to buffer memory  111 . Data is first written into CH0 FIFO  201  beginning at the even MOD-4 boundary (i.e. the start of a FIFO word). CH0  108 D aligns data from DF  104  so that the first data block is written into FIFO  201  with even MOD4 boundary. Logic  202  then reads 8 symbols at a time and assembles data into an 8-bit MOD-4 format. This conversion removes even symbol boundary (“ESB”) pad bits, if any, that were appended to the last data symbol ( FIG. 2B ).  
         [0060]     During Read-Long commands, CH0  108 D does not remove ESB pad bits, since all data from disk  110  is sent to buffer memory  111 . During a normal read operation, only data moves from disk  110  to buffer  111 , however, during a read-long operation, data with ECC bytes and CRC bytes are sent to buffer  111  as well.  FIG. 2B  shows the data path for Read-Long data. ESB pad bits  208  and MOD-4 pad bits  207  are sent with the data to CH0 FIFO  201 . Data that is sent into buffer memory  111  is shown as  205  and  206 . Block  205  includes data and CRC, while block  206  includes ESB pad bits and the ECC.  
         [0061]     Conversion Logic  202 :  
         [0062]      FIG. 3A  shows a block diagram of logic  202 , according to one aspect of the present invention. Logic  202  interfaces to a 64-bit bus  204 A on one side and 80-bit bus  202 A on another side. Logic  202  uses DATAIN register  303 , shuttle register  305  and DATAOUT register  309  to perform bus width conversions.  
         [0063]     Data that is read from buffer  111  is shown as  300 . Data that is written to buffer  111  is shown as  301  that is stored in FIFO  201  before being written.  
         [0064]     DATAIN register  303  receives data  300  from buffer  111  or data  301  from FIFO  301  through a multiplexer (“Mux”)  307 . Thereafter, register  303  provides data to conversion logic. In one aspect of the present invention, DATAIN register  303  is  10  bytes wide during a read operation. It is noteworthy that the present invention is not limited to any particular size of any of the registers that are described herein.  
         [0065]     Buffer write signal  302  provides a control input to Mux  307  so that data can be written to buffer  111 .  
         [0066]     Shuttle register  305  holds data temporarily before it is sent out to DATAOUT register  309 . Shuttle register  305  uses shuttle Mux  304  to concatenate data that is received from register  303  with data that is being held in shuttle register  305 . A counter  306  counts the number of valid data bytes in shuttle register  305 .  
         [0067]      FIG. 3B  shows a table that illustrates how Mux  304  aligns data into the shuttle register  305 . The table is divided in two parts, one for a write operation and another for a read operation. The following describes the various column headings that are used in  FIG. 3B  table:  
         [0068]     “In_Datain”: This column shows the number of bytes in DATAIN register  303 ;  
         [0069]     “In_Shuttle”: This column shows the number of bytes in shuttle register  305  at any given time;  
         [0070]     “Word_Sel”: This column shows the word lane within DATAIN register  303  where the data starts;  
         [0071]     “B_Wr”: This column indicates buffer write operation;  
         [0072]     “sh7 to sh0”: This column shows the output of shuttle Mux  304 ; and  
         [0073]     “d09-d00”: This column represents the data that is going into DATAOUT register  309  and shows how data is concatenated.  
         [0074]     Buffer  111  write operations start from low word. In one aspect for buffer write  111 , only 8 bytes are used and hence d08 and d09 columns are not used, as shown in  FIG. 3B  table. For write operations FIFO data  301  is in 10 bytes and data from DATAOUT register  309  is 8 bytes. Hence, each time FIFO data  301  is read, there is a remainder of 2 bytes. This remainder of 2 bytes is stored and accumulated in shuttle register  305 . Once the number of accumulated bytes in shuttle register  305  reaches 8, then shuttle register  305  data is written into DATAOUT register  309  without reading FIFO data  301 . This is shown as overflow entry  312  in  FIG. 3B .  
         [0075]     In buffer  111  read operation, logic  202  using the shuttle mechanism can start or end in either D-word of the 64 bit bus  204 A. Since sector size is MOD4, only 4 or 8 bytes are used.  
         [0076]      FIG. 3C  shows a schematic of MUX  304 , with inputs  304 A and  304 B producing output  304 C. Signals In_Datain, In_Shuttle, Word_Select and Buffer_Write have been described above with respect to  FIG. 3B .  
         [0077]     Tables III-V below show the byte count present at three stages and the progress of the residue (i.e., last byte in shuttle register  305 ) left in shuttle register  305 . The illustration is based on when the read operation starts at an odd D_word boundary and ends in an Odd D_word boundary (Table III), starts on an odd boundary but ends in an even boundary (Table IV), and then starts on an even boundary and ends in an odd boundary (Table V).  
         [0078]     Tables III and IV show the first cycle with 4 bytes where a transfer of data from buffer  111  starts on the odd D-Word boundary. Tables III and IV also show 4 bytes on the last cycle where BC interface  108 J is able to end on a single D-Word transfer. The highest byte count in shuttle register  305  is still 8 bytes.  
                                           TABLE III                           BC Odd-Start, Odd-End            BYTES_IN_DataIn   BYTES_IN_SHUTTLE   BYTES_IN_DataOut                    4   0   0       8   4   0       8   2   10       8   0   10       8   8   0       8   6   10       8   4   10       4   2   10       0   6   0                  
 
         [0079]    
       
         
               
             
               
               
               
             
               
               
               
             
           
               
                 TABLE IV 
               
             
             
               
                   
               
               
                   
               
               
                 BC Odd-Start, Even-End 
               
             
          
           
               
                 BYTES_IN_DataIn 
                 BYTES_IN_SHUTTLE 
                 BYTES_IN_DataOut 
               
               
                   
               
             
          
           
               
                 4 
                 0 
                 0 
               
               
                 8 
                 4 
                 0 
               
               
                 8 
                 2 
                 10 
               
               
                 8 
                 0 
                 10 
               
               
                 8 
                 8 
                 0 
               
               
                 8 
                 6 
                 10 
               
               
                 8 
                 4 
                 10 
               
               
                 0 
                 2 
                 10 
               
               
                   
               
             
          
         
       
     
         [0080]    
       
         
               
             
               
               
               
             
               
               
               
             
           
               
                 TABLE V 
               
             
             
               
                   
               
               
                   
               
               
                 BC Even-Start, Odd-End 
               
             
          
           
               
                 BYTES_IN_DataIn 
                 BYTES_IN_SHUTTLE 
                 BYTES_IN_DataOut 
               
               
                   
               
             
          
           
               
                 8 
                 0 
                 0 
               
               
                 8 
                 8 
                 0 
               
               
                 8 
                 6 
                 10 
               
               
                 8 
                 4 
                 10 
               
               
                 8 
                 2 
                 10 
               
               
                 4 
                 0 
                 10 
               
               
                 0 
                 4 
                 0 
               
               
                   
               
             
          
         
       
     
         [0081]     As discussed above, DATAOUT register  309  holds data before it is moved out. In one aspect register  309  is 10 bytes wide and only 8 bytes are used for buffer  111  write operations. Register  309  is written when shuttle register  305  and the number of bytes in DATAIN register  303  is equal to the bus width needed or the operation (i.e., 10 bytes during buffer  111  reads and 8 bytes during buffer  111  write). Mux  308  is used to align data into the proper bus width. (See  FIG. 3B  table).  
         [0082]     Padding: If the length of a data block is not MOD10, then padding may be used on the last symbol so that it can be written in FIFO  201 . During buffer  111  read operations, the pad bits allow ECC insertion at ESB. Logic  202  removes the ESB pad bits during buffer  111  write operations. ESB pad bits are not removed during Read-Long commands as raw data from DF  104  is sent to buffer  111  (see  FIG. 2B ).  
         [0083]     Filler Bits: Filler bits are bits that are added at the end of a FIFO word, but are not sent to disk  110 . Logic  202  accesses FIFO  201  8 symbols at a time. This allows writing the first symbol of a transfer into even MOD4 boundary of FIFO  201  (at the beginning of a FIFO word). If data transfer length is not MOD8 symbols, the last FIFO  201  write is accompanied by filler strobes to FIFO  201 , if needed, at the end of disk reads.  
         [0084]     Sector Count: Logic  202  uses a counter  201 G ( FIG. 6 ) to stop data conversion at a sector boundary. Counter  201 G loads the sector size in bytes from a transfer counter register (not shown) and logic  202  accesses data  301 . Counter  201 G is decremented by 10 for each access (10 byte access) and when FIFO sector count is zero, the conversion by logic  202  stops. Conversion resumes when state machine  203 A sends a signal.  
         [0085]     Packing Symbols During Read Operations:  
         [0086]     To create symbols from bytes, logic  202  packs data from a 64-bit bus  204 A into an 80-bit bus  202 A. Shuttle register  305  is used to store data temporarily. Data  300  from buffer  111  comes into register  303  and then shuttle register  305  data and register  303  data is concatenated and assembled into an 80-bit bus  202 A.  FIG. 4  shows the read path  400  during buffer  111  read operation. Data moves from buffer  111  to register  311 .  
         [0087]     Table VI below shows the byte count present during the operation. Register  309  is written when Bytes_IN_DataIn (register  303  bytes) and BYTES_IN_Shuttle (data in shuttle register  305 ) reach a count of 10 or more. The last row in Table VI shows that 6 bytes are left in shuttle register  305 . Logic  202  uses FIFO sector counter  201 G to detect the end of the sector and force the residual shuttle bytes into FIFO  201 . Firmware can also force the residue into FIFO  201 .  
                                           TABLE VI                           Even_Start, Even End            BYTES_IN_DataIn   BYTES_IN_SHUTTLE   BYTES_IN_DataOut                    8   0   0       8   8   0       8   6   10       8   4   10       8   2   10       8   0   10       8   8   0       8   6   10       8   4   10       8   2   10       8   0   10       8   8   0       0   6   10                  
 
         [0088]     Unpacking Symbols During Write Operation:  
         [0089]     To create bytes from symbols, logic  202  unpacks 80-bit bus  202 A data into 64-bit bus  204 A data. FIFO data  301  enters DATAIN register  303 . Data from shuttle register  305  and register  303  are concatenated and assembled into 64-bit bus  204  data. Register  309  writes into register  310 , 8 bytes at a time.  FIG. 5  shows the data path  500  for the write operation. Table VII below shows the byte count during the write operation. Register  310  is provided 8 bytes of data continuously to avoid delay. FIFO data  301  is not read when shuttle register  305  count reaches 8, as discussed above. Table VII shows a byte count table for data  301  movement to register  310 .  
                                     TABLE VII                       BYTES_IN_DataIn   BYTES_IN_SHUTTLE   BYTES_IN_DataOut                                10   0   0       10   2   8       10   4   8       10   6   8       0   8   8       10   0   8       10   2   8       10   4   8       10   6   8       0   8   8       10   0   8       10   2   8       10   4   8       10   6   8       0   8   8       10   0   8       10   2   8       10   4   8                  
 
         [0090]     CH0 Logic  203 :  
         [0091]      FIG. 6  shows another block diagram f or CH0  108 D that facilitates buffer  111  read and write operations. Control logic  203  interacts with buffer  111  and DF  104  through interfaces  602 ,  108 J and  601 . Control information  607 ,  608  and  609  is passed between logic  203 , DF  104 , buffer  111  and ECC module  106 .  
         [0092]     Logic  203  handles protocols for DF  104 , buffer  111 , ECC  106  and the FIFO interfaces. Data is moved via FIFO  201  that in one aspect has a dual port random access memory (“RAM”) address pointers  201 C and  201 F, FIFO counter  201 A and interface logic  201 B to interface with DF  104 . FIFO  201  includes memory (“RAM”)  201 D that is used to store data blocks. The term FIFO as used throughout this specification means “first-in-first out”. Data  201 E (on 80 bit bus  202 A) is passed to logic  202  as discussed above. Data  604  from logic  202  leaves on a 64-bit bus  203 A (see  FIG. 2A ). CRC module  603  provides CRC data when needed. It is noteworthy that FIFO  201  throughout this specification means the entire module  201  that includes memory  201 D.  
         [0093]      FIG. 7  shows a detailed schematic of CH0 control logic  203  with a state machine  203 A that interfaces with logic  202 . Data path  700  has been described above. The following provides a description of various signals that are used in  FIG. 7  to accomplish the adaptive aspects of the present invention:  
         [0094]     Signal  701  (CH0_SHUT_EN) enables the shuttle function in CH0  108 H and allows byte to symbol translation, as described above. Upon reset, logic  202  is disabled and logic  203  accesses FIFO  201  as a 64 bit wide FIFO.  
         [0095]     Signal  702  (SM_SHUT_GO) is generated by state machine  203 A and when active indicates that logic  202  should start processing data. This signal is set active when state machine  203 A is ready to process a next sector and set inactive once data transfer begins between logic  202  and interface  108 J.  
         [0096]     Signal  703  (CH0_BUFFER_WR): This signal is generated from state machine  203 A and indicates the transfer direction for data movement (i.e. from to buffer  111  or from buffer  111 ). When signal  701  is high it indicates that data moves from DF  104  to buffer  111 .  
         [0097]     Signal  704  (SM_DATA_EN) is driven by state machine  203 A and is the data transfer strobe for accessing logic  202 /FIFO  201 . Data is transferred each clock this signal is active (high).  
         [0098]     Signal  705  (SM_FIFO_WR) is used by state machine  203 A during logic  202  bypass mode to write to FIFO RAM  201 D.  
         [0099]     Signal  706  (SHUT_EMPTY) originates from logic  202  and is sent to state machine  203 A. Signal  706  is used to hold off state machine  203 A from starting buffer  111  data bursts until logic  202  is ready to start executing data transfers. When signal  706  is high during disk  110  read, it indicates that shuttle register  305  is empty and state machine  203 A may not start a current sector since no data is available for buffer  111 . During disk  110  write operation, signal  706  indicates that logic  202  is still busy on a current sector and the state  203 A may not start the protocol for the next sector.  
         [0100]     Signal  707  (SHUT_DATEN) is also driven by logic  202  to access FIFO  201 . When active, signal  707  indicates an access to  201 D. FIFO counter  201 A increments by one on disk  110  write decrement on disk reads.  
         [0101]     Signal  708  (CH0_FIFO_DOUT) is driven from logic  202  when enabled to provide byte alignment, as described above.  
         [0102]     Signal  709  (CH0_FIFO_DIN) is the data driven from data path logic  700  (located at interface  108 J) and is sent to logic  202  for conversion, as described above.  
         [0103]     Signal  710  (SHUT_FIFO_WR) is generated by logic  202  for FIFO  201  write.  
         [0104]     Signal  711  is generated from Mux  711 A and sent to FIFO RAM  201 D.  
         [0105]     Signal (RAMDIN)  712  is data in to FIFO RAM  201 D and signal (RAMDOUT)  713  is data out from FIFO RAM  201 D to the data path logic  700 .  
         [0106]     Signal (SHUT_OUT)  714  is the data out from logic  202 .  
         [0107]     Signal (RAMADR)  715  is the RAM address from counters  201 A. Signals  716  are various error correction signals that are received by state machine  203 A and logic  202 .  
         [0108]     Counter(s)  201 A counts FIFO  201  entries. The value in counter  201 A represents FIFO  201  half words that have been written and not yet read.  
         [0109]      FIG. 8  and  9  show the timing diagrams for the various signals (that are described above with respect to  FIG. 7 ) for buffer  111  write and read operations, respectively. Signal TSC_TERM defines the time when FIFO sector count is zero.  
         [0110]      FIG. 10  shows a process flow diagram of executable process steps, according to one aspect of the present invention. In step S 1000 , the process receives data. If data is being written to buffer  111 , then data is received from DF  104  to FIFO  201 , otherwise data is received by FIFO  201  from buffer  111 .  
         [0111]     In step S 1001 , the process determines if any format conversion is required. This is based on the data format supported by the storage device  110 . For example, if data is coming from a tape drive ( 110 ), then no conversion is required and data is processed as 8-bit data in step S 1004 . If data is coming from a hard disk ( 110 ) that operates in a 10-bit format (or a format different from buffer  111 ), then conversion is required and logic  202  is enabled. This is achieved by signal  701  that is generated by state machine  203 a ( FIG. 7 ).  
         [0112]     In step S 1003 , data is aligned by logic  202 . In this case if data is being written from DF  104 , then data is received in 10-bit format. Data from FIFO  201  is stored in shuttle register  305  and sent over bus  204 A. Shuttle register  305  paces data transfer from FIFO  201  to avoid an overflow condition ( FIG. 3B ).  
         [0113]     If data is being read from buffer  111 , then logic  202 , as described above moves the 8-bit data to a 10-bit format. Logic  202  is capable of moving data through buses with varying widths (bus  202 A and  203 A).  
         [0114]     In step S 1003 , data is transferred after the conversion logic  202  has aligned the data based on storage device  110  and buffer memory  111  format requirements.  
         [0115]     In one aspect of the present invention, same piece of logic is used to move data to and from buffer  111  in two different formats. This saves overall chip cost and improves data transfer performance.  
         [0116]     Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure.