Abstract:
An apparatus comprises a plurality of Analog to Digital Converter circuits (ADCs) and a skew detector configured to determine a plurality of indicators corresponding to a plurality of sampling time skews of the plurality of ADCs, respectively. The plurality of ADCs is configured to adjust the plurality of sampling time skews according to the plurality of indicators, respectively. The apparatus is configured to reach an equilibrium state wherein the plurality of indicators are substantially equal. In an embodiment, the apparatus comprises a Time-Interleaved ADC including the plurality of ADCs. A method comprises measuring a plurality of indicators of a plurality of sampling time skews, respectively. The plurality of sampling time skews are associated with a plurality of ADCs, respectively. The plurality of sampling time skews are adjusted according to respective indicators of the plurality of indicators.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This present disclosure claims the benefit of U.S. Provisional Application No. 61/894,189, filed on Oct. 22, 2013, which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. 
     In a high speed serial communication link, such as a 10 Gigabit (10 G) or 100 Gigabit (100 G) Ethernet connection, a transmitter transmits a data signal into a communication channel (channel). The data signal includes a sequence of symbols, each symbol carrying information from some number of bits, such as one, two, or more bits, or in some cases fractions of bits. The data signal may be an analog data signal. 
     The symbols are transmitted at a modulation rate expressed in baud, where one baud is one symbol per second. The duration of each symbol is known as the Unit Interval (UI). 
     In order to receive the data on the communication link, a receiver converts the analog data signal into a digital signal using an Analog to Digital Converter circuit (ADC). The ADC may perform one analog to digital conversion during each UI or may perform a plurality of analog to digital conversions during each UI. 
     At high sampling rates, a Time-Interleaved ADC (TI-ADC) may be used to perform the analog to digital conversions. A TI-ADC includes a plurality of ADCs that operate in parallel. In a TI-ADC performing one analog to digital conversion per sampling period with a duration of S nanoseconds and including N ADCs, that is, an “N-times TI-ADC,” the TI-ADC may operate using N sampling clocks each having a period of N·S nanoseconds and each lagging the previous sampling clock by S nanoseconds, each of the N sampling clocks controlling a respective one of the N ADCs. The output of the TI-ADC is a composition of the N ADCs of the TI-ADC. When all of the N ADCs operate identically, the composition of all N ADC outputs is equivalent to a single ADC performing sampling and conversion once every S nanoseconds. 
     That is, in the N-time TI-ADC, each of N ADCs samples the analog data signal once every N·S nanoseconds and then perform a conversion on the sampled signal: a first ADC samples the analog data signal at 0, N·S, 2N·S, . . . nanoseconds; a second ADC samples the analog data signal at S, (N+1)·S, (2N+1)·S, . . . nanoseconds; and so on; and an N th  ADC samples the analog data signal at (N−1)·S, (2N−1)·S, (3N−1)·S, . . . nanoseconds. Because each ADC of the TI-ADC performs sampling and conversion for only 1/N of the sampling periods, each ADC may operate at a substantially slower speed than an ADC capable of performing conversions at a rate corresponding to the sampling period. 
     The quality of the output of the TI-ADC depends on the individual ADCs of the TI-ADC operating with a high degree of uniformity. However, because of manufacturing and environmental variations, operational characteristics that affect uniformity of an ADC&#39;s operation may vary among the individual ADCs of the TI-ADC. 
     SUMMARY 
     In an embodiment, an apparatus comprises a plurality of Analog to Digital Converter circuits (ADCs) and a skew detector configured to determine a plurality of indicators corresponding to a plurality of sampling time skews of the plurality of ADCs, respectively. 
     In an embodiment, the plurality of ADCs is configured to adjust the plurality of sampling time skews according to the plurality of indicators, respectively. 
     In an embodiment, the apparatus is configured to reach an equilibrium state wherein the plurality of indicators are substantially equal. 
     In an embodiment, the plurality of indicators includes a plurality of outputs of a plurality of Timing Error Detection circuits (TEDs) coupled to the plurality of ADCs, respectively. 
     In an embodiment, the apparatus comprises a plurality of equalizer circuits coupled to the plurality of ADCs, respectively. The plurality of indicators include a plurality of precursor powers of the plurality of equalizer circuits, respectively. 
     In an embodiment, the apparatus comprises a Time-Interleaved ADC including the plurality of ADCs. 
     In an embodiment, a method comprises measuring a plurality of indicators of a plurality of sampling time skews, respectively. The plurality of sampling time skews are associated with a plurality of Analog to Digital Converter circuits (ADCs), respectively. The method further comprises adjusting the plurality of sampling time skews according to respective indicators of the plurality of indicators. 
     In an embodiment, adjusting the plurality of sampling time skews includes adjusting the plurality of sampling time skews according to integrals of the respective indicators. 
     In an embodiment, adjusting the plurality of sampling time skews includes delaying a plurality of sampling clocks of the plurality of ADCs according to the plurality of indicators, respectively. 
     In an embodiment, the method further includes producing an equilibrium state wherein the plurality of indicators is substantially equal to each other. 
     In an embodiment, the plurality of indicators includes a plurality of outputs of Timing Error Detection circuits (TEDs) coupled to the plurality of ADCs, respectively. 
     In an embodiment, measuring the plurality of indicators includes determining a plurality of precursor powers of a plurality of equalizer circuits coupled to the plurality of ADCs, respectively. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a communication link according to an embodiment. 
         FIG. 2  is a diagram of a receiver circuit according to an embodiment. 
         FIGS. 3A and 3B  illustrate effects of sampling time skew. 
         FIG. 4  is a diagram of an Analog to Digital Converter circuit (ADC) according to an embodiment. 
         FIG. 5  is a diagram of another receiver circuit according to an embodiment. 
         FIGS. 6A and 6B  are diagrams of skew detector circuits according to embodiments. 
         FIG. 7  is a diagram of another receiver circuit according to an embodiment. 
         FIG. 8  is a flowchart of a process of adjusting sampling time skews of a time-interleaved ADC according to an embodiment. 
         FIG. 9  is a flowchart of a process of adjusting sampling time skews of a time-interleaved ADC according to an embodiment. 
         FIG. 10  is a flowchart of process of adjusting sampling time skews of a time-interleaved ADC according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows a communication link  100  according to an embodiment. The communications link includes a transmitter  102 , a channel  104 , and a receiver  1 - 106 . The receiver  1 - 106  includes an Analog to Digital Converter circuit (ADC)  1 - 110 , an equalizer circuit (EQ)  1 - 112 , a slicer circuit  1 - 114 , and a Clock and Data Recovery circuit (CDR)  1 - 120 . In an embodiment, the receiver  1 - 106  is included in an integrated circuit. 
     The transmitter  102  receives input data DIN and a transmit clock TxCLK. The transmitter  102  generates symbols based on the input data DIN and transmits the symbols into the channel  104  at a rate determined by the transmit clock TxCLK, each symbol being transmitted in a Unit Interval (UI) equal to the inverse of a frequency of the transmit clock TxCLK. 
     The channel  104  propagates the symbols from the transmitter  102  to the receiver  1 - 106 . As the symbols are propagated, properties of the channel  104  cause modification of the symbols. In particular, dispersions and reflections in the channel  104  may change the propagation time of portions of energy used to transmit the symbol. As a result, energy from more than one symbol may arrive simultaneously at the receiver  1 - 106 , producing Inter-Symbol Interference (ISI). In addition, the channel  104  may introduce noise and other distortions into the symbols. 
     The ADC  1 - 110  receives the energy from the channel  104 , samples it, and converts the samples into a digital signal. A frequency and a phase of the conversions performed by the ADC  1 - 110  is determined by a clock signal the ADC  1 - 110  receives from the CDR  1 - 120 . In an embodiment, the ADC  1 - 110  is a Time-Interleaved ADC (TI-ADC). 
     Because of ISI and other imperfections introduced by the channel, the phase (that is, the temporal offset within the UI) at which the ADC  1 - 110  samples the output of the channel  104  substantially affects the accuracy and noise rejection of the conversion performed by the ADC  1 - 110 . Accordingly, the CDR  1 - 120  is configured to adjust the phase of the clock signal provided to the ADC  1 - 110  so that the ADC  1 - 110  samples the output of the channel  104  at a time within the sampling interval when the Signal-to-Noise Ratio (SNR) is near a peak. In an embodiment, the sampling interval is substantially equal to the UI. 
     The EQ  1 - 112  processes the signals produced by the ADC  1 - 110  to reduce an effect of ISI and other properties of the channel  104 . The slicer  1 - 114  evaluates the output of the EQ  1 - 112  to produce a data out signal DOUT corresponding to the received symbols. In an embodiment, the slicer  1 - 114  determines the data out signal DOUT by comparing the output of the EQ  1 - 112  to one or more thresholds. 
       FIG. 2  is a block diagram of a receiver circuit (or receiver)  2 - 106  suitable for use in the receiver  1 - 106  according to an embodiment. The receiver circuit  2 - 106  includes a TI-ADC  2 - 110 , a Time-Interleaved Equalizer (TI-EQ)  2 - 112 , a Time-Interleaved slicer (TI-slicer)  2 - 114 , and a Time-Interleaved Timing Error Detection circuit (TI-TED)  2 - 116 . The receiver circuit  2 - 106  also includes a CDR  2 - 120 . 
     The TI-ADC  2 - 110  includes first through N th  ADCs,  2 - 110 - 1  through  2 - 110 -N, each sampling and converting an input signal INP during respective first through N th  sampling intervals. Corresponding first through N th  sampling clocks for each of the first through N th  ADCs,  2 - 110 - 1  through  2 - 110 -N, are generated according to the sampling clock SCLK, which determines a phase of the first through N th  sampling clocks. 
     Each of the first through N th  ADCs,  2 - 110 - 1  through  2 - 110 -N, may have a different gain and a different DC offset relative to each other. A person of skill in the art in light of the teachings and disclosures herein would understand how to compensate for the different gain and DC offset of the first through N th  ADCs,  2 - 110 - 1  through  2 - 110 -N, to improve the operational uniformity of the first through N th  ADCs,  2 - 110 - 1  through  2 - 110 -N. 
     Each of the first through N th  ADCs,  2 - 110 - 1  through  2 - 110 -N, may have a different sampling time skew relative to each other. That is, the difference between the phase of the sampling clock SCLK and a time at which sampling of the input signal INP is performed may vary among the first through N th  ADCs,  2 - 110 - 1  through  2 - 110 -N. 
     The non-uniform sampling time skews of the first through N th  ADCs,  2 - 110 - 1  through  2 - 110 -N, may introduce distortion into the sampled signals and degrade the performance of the receiver  2 - 106 . Embodiments of the present disclosure operate to adjust the sampling time skews of the first through N th  ADCs,  2 - 110 - 1  through  2 - 110 -N, in order to reduce or substantially eliminate the non-uniformity in the sampling time skew. 
     The TI-EQ  2 - 112  includes first through N th  equalizers (EQs),  2 - 112 - 1  through  2 - 112 -N, each receiving and equalizing an output of the respective first through N th  ADCs,  2 - 110 - 1  through  2 - 110 -N. Each of the first through N th  EQs,  2 - 112 - 1  through  2 - 112 -N, equalizes the respective received signals using a respective coefficient set that includes a plurality of coefficients. In an embodiment, all of the first through N th  EQs,  2 - 112 - 1  through  2 - 112 -N, use the same coefficient set. 
     In an embodiment, the correspondence between the first through N th  EQs,  2 - 112 - 1  through  2 - 112 -N, and the first through N th  ADCs,  2 - 110 - 1  through  2 - 110 -N, is a logical correspondence, and the outputs of the first through N th  ADCs,  2 - 110 - 1  through  2 - 110 -N, are multiplexed into a single composite ADC signal and then de-multiplexed for delivery to the respective first through N th  EQs,  2 - 112 - 1  through  2 - 112 -N. In another embodiment, each of the first through N th  EQs,  2 - 112 - 1  through  2 - 112 -N, receives the output of the respective first through N th  ADCs,  2 - 110 - 1  through  2 - 110 -N, through respective first through N th  connections. 
     The TI-slicer  2 - 114  includes first through N th  slicers,  2 - 114 - 1  through  2 - 114 -N, each receiving an output of the respective first through N th  EQs,  2 - 112 - 1  through  2 - 112 -N. Each of the first through N th  slicers,  2 - 114 - 1  through  2 - 114 -N, produces a respective data out signal by performing a comparison of the output of the respective first through N th  EQs,  2 - 112 - 1  through  2 - 112 -N, to one or more thresholds. The data out signals of the first through N th  slicers,  2 - 114 - 1  through  2 - 114 -N, may be combined to produce a received data out signal of the receiver  2 - 106 . 
     First through N th  summing circuits,  2 - 115 - 1  through  2 - 115 -N, determine first through N th  differences between the outputs of the first through N th  EQs,  2 - 112 - 1  through  2 - 112 -N, and the data out signal produced by the corresponding first through N th  slicers,  2 - 114 - 1  through  2 - 114 -N, respectively. First through N th  Timing Error Detection circuits (TEDs),  2 - 116 - 1  through  2 - 116 -N, produce first through N th  timing error signals using the first through N th  differences. The first through N th  timing error signals are summed by adder  2 - 118  to produce a total timing error signal TERR. 
     The receiver  2 - 106  thus time-interleaves the processing of the input signal INP using N logical lanes, each lane including an ADC, an equalizer, a slicer, and a TED. Lane  1  includes the first ADC  2 - 110 - 1 , first EQ  2 - 112 - 1 , first slicer  2 - 114 - 1 , first summing circuit  2 - 115 - 1 , and first TED  2 - 116 - 1 ; Lane  2  includes the second ADC  2 - 110 - 2 , second EQ  2 - 112 - 2 , second slicer  2 - 114 - 2 , second summing circuit  2 - 115 - 2 , and second TED  2 - 116 - 2 ; and so on. 
     The CDR  2 - 120  produces the sampling clock SCLK according to the total timing error signal TERR. In an embodiment, the CDR  2 - 120  adjusts the phase of the sampling clock SCLK until the total timing error signal TERR is substantially zero. 
       FIGS. 3A and 3B  demonstrate the effects of sampling time skews.  FIG. 3A  shows a  2 -times TI-ADC  3 - 110  including first and second ADCs  3 - 110 - 1  and  3 - 110 - 2 . A sampling clock t operates to have edges occurring once each first sampling period, and first and second interleaved sampling clocks t 0  and t 1  operate to have edges occurring once each second sampling period, the second interleaved sampling clock t 1  being delayed by one sampling period relative to the first interleaved sampling clock t 0 . 
     The first ADC  3 - 110 - 1  performs a sampling and conversion of an input signal INP at each edge of the first interleaved sampling clock t 0 , and the second ADC  3 - 110 - 2  performs a sampling and conversion of the input signal INP at each edge of the second interleaved sampling clock t 1 . A circle on a graph of the input signals INP indicates a time when the input signals INP is sampled and converted by the first ADC  3 - 110 - 1 , and an “X” marks a time when the input signals INP is sampled and converted by the second ADC  3 - 110 - 2 . 
     In  FIG. 3A , the first and second interleaved sampling clocks t 0  and t 1  have identical sampling time skews. As a result, the input signal INP is sampled at times substantially identical to times the input signal INP would be sampled by a single high-speed ADC performing sampling at each edge of the sampling clock t. Therefore, the composition of the output from the first and second ADCs  3 - 110 - 1  and  3 - 110 - 2  is substantially identical to the output that would have been obtained using the single high-speed ADC. 
     In  FIG. 3B , the first and second interleaved sampling clocks t 0  and t 1  have different sampling time skews. The first interleaved sampling clocks t 0  is early, and the second interleaved sampling clock t 1  is late. Therefore, the input signal INP is sampled at times other than times the input signal INP would be sampled by a single high-speed ADC performing sampling at each edge of the sampling clock t, and the difference in the sampling times cannot be corrected by adjusting the timing of the sampling clock t. As a result, the composition of the outputs of the first and second ADCs  3 - 110 - 1  and  3 - 110 - 2  is substantially different from the output that would have been obtained using the single high-speed ADC. 
       FIG. 4  is a diagram of an Analog to Digital Converter circuit (ADC)  4 - 110 - n  according to an embodiment. The ADC  4 - 110 - n  is suitable for use as each of the first through N th  ADCs,  2 - 110 - 1  through  2 - 110 -N, of  FIG. 2 . The ADC  4 - 110 - n  includes a Sample and Hold circuit (S/H)  402 , a converter circuit  404 , and an actuator  406 . 
     The S/H  402  receives an analog input signal IN and samples it according to a phase of an output signal CLKd of the actuator  406 . The S/H  402  then produces an analog output equal to the value of the input signal IN at the time of the sampling until the next sample is taken. 
     The converter circuit  404  converts the analog output of the S/H  402  to a digital output OUT. The converter circuit  404  may include one or more of a flash conversion circuit, a successive approximation conversion circuit, a delta-sigma conversion circuit, a pipelined conversion circuit, and the like. 
     The actuator  406  receives a clock signal CLK and produces an output signal CLKd having a phase determined according to the clock signal CLK and an adjustment signal Tadj. A delay between a phase of the clock signal CLK and the phase of the output signal CLKd is determined using the adjustment signal Tadj. As a result, the time at which the ADC  4 - 110 - n  samples and converts the input signal IN is determined by the clock signal CLK and the adjustment signal Tadj. 
     In an embodiment, the actuator  406  produces the output signal CLKd by selecting a tap of a chain of buffers according to the adjustment signal Tadj, wherein an initial input of the chain of buffers is connected to the clock signal CLK. In another embodiment, the actuator produces the output signal CLKd by varying a capacitance according to the adjustment signal Tadj. A person of ordinary skill in the art in light of the teachings and disclosures herein would understand other techniques for producing the output signal CLKd having a phase delayed from a phase of the clock signal CLK according to the adjustment signal Tadj. 
       FIG. 5  is a block diagram of a receiver circuit  5 - 106  suitable for use in the receiver  1 - 106  according to an embodiment. The receiver circuit  5 - 106  is configured to substantially eliminate differences in timing sampling skew between a plurality of ADCs of a time-interleaved ADC. Although  FIG. 5  shows a receiver circuit  5 - 106  including two time-interleaved lanes, embodiments are not limited thereto. 
     The receiver circuit  5 - 106  includes first and second time-interleaved lanes. The first lane included a first Analog to Digital Converter circuit (ADC)  5 - 110 - 1 , a first equalizer circuit (EQ)  5 - 112 - 1 , a first slicer  5 - 114 - 1 , a first summing circuit  5 - 115 - 1 , and a first Timing and Error Detection circuit (TED)  5 - 116 - 1 . The second lane included a second ADC  5 - 110 - 2 , a second EQ  5 - 112 - 2 , a second slicer  5 - 114 - 2 , a second summing circuit  5 - 115 - 2 , and a second TED  5 - 116 - 2 . The receiver circuit  5 - 106  also includes a Clock and Data Recovery circuit (CDR)  5 - 120  and an adder  5 - 118 . These components of receiver circuit  5 - 106  operate similarly to the like-numbered components of receiver circuit  2 - 106  described above with reference to  FIG. 2 . 
     An interleaved clock generating circuit (CLKGEN)  5 - 510  generates first and second interleaved clocks C 1  and C 2  for the first and second ADCs  5 - 110 - 1  and  5 - 110 - 2 , respectively. Each of the first and second interleaved clocks C 1  and C 2  includes sample-triggering edges occurring once every two sampling periods. The second interleaved clock C 2  is substantially identical to the first interleaved clock C 1  delayed by one sampling period. 
     The first and second ADCs  5 - 110 - 1  and  5 - 110 - 2  each incorporate circuits such as those incorporated in the ADC  4 - 110 - n  of  FIG. 4 . Therefore, the time at which the first and second ADCs  5 - 110 - 1  and  5 - 110 - 2  sample and convert the input signal IN is determined by the first and second clock signals C 1  and C 2  and the first and second adjustment signals Tadj 1  and Tadj 2 , respectively. 
     The receiver circuit  5 - 106  further includes a skew detector  5 - 520 . The skew detector  5 - 520  receives information from the first and second EQs  5 - 112 - 1  and  5 - 112 - 2  and/or the first and second TEDs  5 - 116 - 1  and  5 - 116 - 2 , and determines first and second skew feedback signals Sk 1  and Sk 2  corresponding to sampling time skews for the first and second ADCs  5 - 110 - 1  and  5 - 110 - 2 , respectively. 
     First and second loop filters  5 - 524 - 1  and  5 - 524 - 2  generate the first and second adjustment signals Tadj 1  and Tadj 2  using the first and second skew feedback signals Sk 1  and Sk 2 , respectively. Each of the first and second loop filters  5 - 524 - 1  and  5 - 524 - 2  includes a feedback integrator and/or other feedback controls. The first and second loop filters  5 - 524 - 1  and  5 - 524 - 2  control the first and second adjustment signals Tadj 1  and Tadj 2  in order to drive the first and second skew feedback signals Sk 1  and Sk 2  towards zero. 
     The skew detector  5 - 520  and the first and second loop filters  5 - 524 - 1  and  5 - 524 - 2  are configured to produce first and second adjustment signals Tadj 1  and Tadj 2  that cause the sampling time skews of the first and second ADCs  5 - 110 - 1  and  5 - 110 - 2  to be substantially identical. As a result, the composition of the output from the first and second ADCs  5 - 110 - 1  and  5 - 110 - 2  is substantially identical to the output that would have been obtained using a single ADC. 
     In an embodiment, the skew detector  5 - 520  and the first and second loop filters  5 - 524 - 1  and  5 - 524 - 2  are configured to correct differences in the sampling time skews between the first and second ADCs  5 - 110 - 1  and  5 - 110 - 2 , and the sampling timing of the first and second ADCs  5 - 110 - 1  and  5 - 110 - 2  is also jointly adjusted by the CDR  5 - 120  controlling the SCLK. 
       FIG. 6A  shows a skew detector  6 - 520 A suitable for use as the skew detector  5 - 520  in the receiver circuit  5 - 106  of  FIG. 5 . The skew detector  6 - 520 A includes first and second precursor power calculators (PPCs)  604  and  614 , averaging circuit  610 A, and first and second summing circuits  606  and  616 . In the skew detector  6 - 520 A, a difference between outputs PP 1  and PP 2  of the first and second PPCs  604  and  614  operates as an indirect measure of a difference in the sampling times of the first and second ADCs  5 - 110 - 1  and  5 - 110 - 2 . 
     The first and second PPCs  604  and  614  receive the coefficients from the first and second equalizers (EQs)  6 - 112 - 1  and  6 - 112 - 2 . In an embodiment, the coefficients of the first and second EQs  6 - 112 - 1  and  6 - 112 - 2  are determined using first and second Least Mean Square (LMS) adaptation loops, respectively. 
     The first PPC  604  calculates a first precursor power PP 1  using the coefficients of the first EQ  6 - 112 - 1 . The first precursor power PP 1  may be determined using Equation 1, below, wherein c1[k] is the k th  coefficient of the first EQ  6 - 112 - 1 , cursor represents the position of the cursor within the coefficients, and c1[0] is the earliest of the precursor coefficients: 
     
       
         
           
             
               
                 
                   
                     PP 
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     The second PPC  614  operates similarly to the first PPC  604  to calculate a second precursor power PP 2  using the coefficients of the second EQ  6 - 112 - 2 . The second precursor power PP 2  may be determined using Equation 2, below, wherein c2[k] is the k th  coefficient of the second EQ  6 - 112 - 2 , cursor represents the position of the cursor within the coefficients, and c2[0] is the earliest of the precursor coefficients: 
     
       
         
           
             
               
                 
                   
                     PP 
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     The averaging circuit  610 A determines an average precursor power PPA by averaging together the first and second precursor powers PP 1  and PP 2 . The average precursor power PPA is subtracted from the first and second precursor powers PP 1  and PP 2  by the first and second summing circuits  606  and  616  to produce the first and second skew feedback signals Sk 1  and Sk 2 , respectively. 
     In the receiver circuit  5 - 106  of  FIG. 5 , the first and second skew feedback signals Sk 1  and Sk 2  of the skew detector  6 - 520 A act on the first and second ADCs  5 - 110 - 1  and  5 - 110 - 2  to produce an equilibrium condition wherein the first and second precursor powers PP 1  and PP 2  are substantially identical, and the first and second skew feedback signals Sk 1  and Sk 2  are substantially zero. The receiver circuit  5 - 106  using the skew detector  6 - 520 A is configured to drive the coefficients of the first and second EQs  5 - 112 - 1  and  5 - 112 - 2  to have equal partial power. However, the coefficients of the first and second EQs  5 - 112 - 1  and  5 - 112 - 2  are not necessarily driven to be identical. 
       FIG. 6B  shows a skew detector  6 - 520 B similar to the skew detector  6 - 520 A of  FIG. 6A , but scaled up for use in a four-way time-interleaved receiver. Compared to the skew detector  6 - 520 A of  FIG. 6A , the skew detector  6 - 520 B further includes third and fourth PPCs  624  and  634  and third and fourth summing circuits  626  and  636  to generate third and fourth skew feedback signals Sk 3  and Sk 4 . 
     The third and fourth PPCs  624  and  634  receive coefficients from third and fourth EQs  6 - 112 - 3  and  6 - 112 - 4  and determine third and fourth precursor powers PP 3  and PP 4 , respectively, in the same manner as the first and second PPCs  604  and  614 . The averaging circuit  610 B computes the average precursor power PPA of the first through fourth precursor powers PP 1  through PP 4 . The first through fourth skew feedback signals Sk 1  through Sk 4  are determined by subtracting the average precursor power PPA from the first through fourth precursor powers PP 1  through PP 4 , respectively. 
       FIG. 7  shows a receiver circuit  7 - 106  according to an embodiment.  FIG. 7  is similar to  FIG. 5 , and like-numbered elements of  FIG. 7  are substantially identical to like-numbered components shown in  FIG. 5 . Accordingly, descriptions of the like-number components of  FIG. 7  are omitted in the interest of brevity. 
     In the skew detector  720  of  FIG. 7 , the individual outputs of the first and second TED  7 - 116 - 1  and  7 - 116 - 2  are used to generate the first and second skew feedback signals Sk 1  and Sk 2 . In an embodiment of the receiver circuit  7 - 106 , the first and second EQ  7 - 112 - 1  and  7 - 112 - 2  use identical coefficients, and a difference in the outputs of the first and second TED  7 - 116 - 1  and  7 - 116 - 2  is attributable to a difference in the sampling time skews between first and second ADCs  7 - 110 - 1  and  7 - 110 - 2 . 
     A first feedback loop including a CDR  7 - 120  drives the total timing error signal TERR produced by the adder  7 - 118  to be substantially zero. However, the first feedback loop including the CDR  7 - 120  may not drive the outputs of the first and second TED  7 - 116 - 1  and  7 - 116 - 2  to be substantially zero. 
     The output of the first TED  7 - 116 - 1  is used as the first skew feedback signals Sk 1 . Using the first skew feedback signals Sk 1 , the loop filter  7 - 524 - 1  generates the first adjustment signals Tadj 1 . The action of the first adjustment signals Tadj 1  on the first ADC  7 - 110 - 1  drives the output of the first TED  7 - 116 - 1  towards zero. That is, a second feedback loop including the first loop filter  7 - 524 - 1  is configured to achieve an equilibrium condition where the output of the first TED  7 - 116 - 1  is substantially zero. 
     The output of the second TED  7 - 116 - 2  is used as the second skew feedback signals Sk 2 . Using the second skew feedback signals Sk 2 , the loop filter  7 - 524 - 2  generates the second adjustment signals Tadj 2 . The action of the second adjustment signals Tadj 2  on the second ADC  7 - 110 - 2  drives the output of the second TED  7 - 116 - 2  towards zero. That is, a third feedback loop including the second loop filter  7 - 524 - 2  is configured to achieve an equilibrium condition where the output of the second TED  7 - 116 - 2  is substantially zero. 
       FIG. 8  is a flowchart of a process  800  of adjusting sampling time skews in a time-interleaved ADC according to an embodiment. 
     At S 802 , an indicator of a sampling time skew is measured for each of a plurality of lanes. In an embodiment, the indicator includes a timing error measured using a timing error detection circuit of each lane. In another embodiment, the indicator includes a precursor power of an equalizer circuit of each lane. 
     At S 804 , the sampling time skew of an ADC of each lane is adjusted according to the respective measured indicator. In an embodiment, each measured indicator is provided to a respective loop filter, and each loop filter produces an adjustment signal that adjusts the sampling time skew of the respective ADC. In an embodiment, the loop filter includes an integrator. 
     In an embodiment, repetition of the process  800  drives the indicator for each lane to be substantially zero. In an embodiment, repetition of the process  800  drives the indicator for each lane to be substantially equal to the indicator for each other lane. 
       FIG. 9  is a flowchart of a process  900  of adjusting sampling time skews in a time-interleaved ADC according to an embodiment. 
     At S 902 , a timing error is measured for each of a plurality of lanes. In an embodiment, the timing error is measured using a Timing Error Detection circuit (TED). A sum of the timing errors of each lane may be used to drive a Clock and Data Recovery (CDR) circuit. 
     In an embodiment, an equalizer of each lane uses the same coefficients as each equalizer of each other lane. In an embodiment, the coefficients are determined using a Least Means Square (LMS) adaptation. 
     At S 904 , the sampling time skew of an ADC of each lane is adjusted according to the respective timing error. In an embodiment, each timing error is provided to a respective loop filter, and each loop filter produces an adjustment signal that adjusts the sampling time skew of the respective ADC. In an embodiment, each loop filter includes an integrator. 
     In an embodiment, repetition of the process  900  drives the timing error for each lane to be substantially zero. 
       FIG. 10  is a flowchart of a process  1000  of adjusting sampling time skews in a time-interleaved ADC according to an embodiment. 
     At S 1002 , a precursor power of the coefficients (PPC) of an equalizer (EQ) of each lane is determined. Each equalizer of each lane uses independently determined coefficients. The PPC of each equalizer is determined by summing the squares of the pre-cursor coefficients of the equalizer. In an embodiment, the coefficients of each equalizer are determined using a Least Means Square (LMS) adaptation for each lane. 
     At S 1004 , a precursor power average (PPA) is determined using the PPCs of each lane. At S 1006 , a difference is determined for each lane between the respective PPC of the lane and the PPA. 
     At S 1008 , the differences are filtered using respective loop filters. In an embodiment, each loop filter includes a respective integrator. In an embodiment, each loop filter includes a respective feedback control. 
     At S 1010 , sampling time skews of ADCs of each lane are adjusted using the respective filtered differences. 
     In an embodiment, repetition of the process  1000  drives the PPC for each lane to be substantially identical to the PPC of each other lane. 
     Aspects of the present disclosure have been described in conjunction with the specific embodiments thereof that are proposed as examples. Numerous alternatives, modifications, and variations to the embodiments as set forth herein may be made without departing from the scope of the claims set forth below. Accordingly, embodiments as set forth herein are intended to be illustrative and not limiting.