Abstract:
In an electronic fuze for a projectile the ignition energy, upon firing of the projectile, is produced by a generator and stored in a storage capacitor. An electronic circuit serving for the barrel safety i.e. to prevent premature detonation of the projectile in front of the barrel, delaying ignition upon impact, the delay-free ignition upon impact and the self-destruction of the projectile, controls the delivery of the energy stored in the capacitor to the detonator or ignition cap. To ensure that the energy of the storage capacitor is sufficient the electronic circuit of the fuze must work with extremely low current. This is realized by providing for the circuit a stabilizer, a switching-on element, resetting elements, blocking elements and time-delay elements, the stabilizer and time-delay elements being structured as solid-state circuits.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a new and improved construction of an electronic fuze for a projectile, which is of the type comprising a generator for generating the ignition energy, a storage capacitor in which there is stored the energy produced by the generator upon firing of the projectile, an ignition or detonator cap which is ignited by the energy stored in the storage capacitor, and an electronic circuit which serves for the barrel safety when the projectile is in front of the firing barrel, for delaying ignition upon impact, for the delay-free ignition upon impact and the self-destruction of the projectile. 
     SUMMARY OF THE INVENTION 
     It is a primary object of the present invention to provide a new and improved construction of an electronic fuze having an electronic circuit for the weapon barrel safety when the projectile is located in front of the barrel after firing, for self-destruction and selectively for delaying the ignition upon impact or for the immediate ignition upon impact, the electronic fuze requiring so little current that there suffices the energy of a single storage capacitor. 
     Yet a further significant object of the present invention aims at a new and improved construction of an electronic fuze working with very low energy requirements, which is extremely simple in design, highly reliable in operation, and not readily subject to breakdown or malfunction. 
     Now in order to implement these and still further objects of the invention, which will become more readily apparent as the description proceeds, the electronic fuze of the present development contains an electronic circuit of the previously mentioned type which, according to important aspects of the present invention, embodies a stabilizer which exclusively is constructed of elements which collectively form a solid-state circuit. Further, the electronic circuit comprises a switching-on element operatively connected with resetting elements and blocking elements, and time-delay elements which likewise are composed of elements which collectively form a solid-state circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be better understood and objects other than those set forth above, will become apparent when consideration is given to the following detailed description thereof. Such description makes reference to the annexed drawings wherein: 
     FIG. 1 is a circuit diagram of an electronic fuze constructed according to the teachings of the present invention; 
     FIG. 2 is a circuit diagram illustrating details of a stabilizer used in the electronic fuze of FIG. 1; 
     FIG. 3 is a circuit diagram illustrating details of the switch-on elements used in the circuit arrangement of fuze of FIG. 1; and 
     FIG. 4 is a schematic illustration of time-delay elements used in the circuit arrangement of electronic fuze of FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     (1) The General Construction of the Electronic Fuze 
     (FIG. 1) 
     Describing now the drawings, the electronic fuze as shown in FIG. 1, and constructed according to the teachings of the present invention, will be seen to comprise a generator 1 constituted, for instance, by a surge generator which produces the energy required by the fuze by the firing acceleration of the projectile. There also can be used, however, a rotating generator which generates the energy needed by the electronic fuze due to the spin acceleration of the projectile. 
     A bridge-connected rectifier 2 is connected with the generator 1 and renders possible storage of the energy produced by the generator 1 in a storage capacitor 3. 
     Since the electrical energy stored in the storage capacitor 3 rapidly decreases upon its removal and thus is not constant, and for the purpose of reducing the current consumption, there is connected to the storage capacitor 3 a stabilizer 4 which regulates the supply voltage to a low level. This stabilizer or stabilizer circuit 4 has been illustrated in detail in FIG. 2 and will be described more fully in conjunction therewith. 
     Connected with the stabilizer 4 is a switching-on element or circuit 8 and a final stage 5 for igniting a detonator or ignition cap 7. A blocking element 6 ensures that the detonator or ignition cap 7 will be not prematurely ignited. 
     The blocking element or circuit 6 has been shown in greater detail in the circuit arrangement of FIG. 3 and will be described more fully hereinafter. The end or final stage 5 contains a thyristor or a transistor as the power switch. Connected with the switching-on element or circuit 8 are three reset or restoring switches 10, 11 and 12 by means of which it is possible to reset a counter 19 and an element 18 serving for the barrel safety when the projectile is located in front of or near the mouth of the barrel in its starting position. The counter 19 is connected with a decoder 9 by means of which it is possible to trigger the aforementioned detonator or ignition cap 7. 
     The last-mentioned elements, shown enclosed in a phantom or dash-line block 22, have been illustrated more fully in FIG. 3 and will be described in greater detail hereinafter. 
     Futhermore, connected with the switching-on element 8 are two oscillators 16 and 17 whose oscillations can be counted by two counters 19 and 20, in order to ensure for, for instance, the above-mentioned barrel safety and the self-destruction of the projectile. Elements or circuit 21 serving for providing a time-delay program are connected both with the oscillator 17 and with the blocking device 6. The counter 19 can be set in accordance with the desired barrel safety and the desired self-destruction time and the counter 19 can be set in accordance with the desired impact delay time i.e. the ignition delay upon impact. 
     The decoder 9 has programming inputs or input means 9a in order to set the self-destruction time. 
     Both of the oscillators 16 and 17, the counter 20 and the elements or circuit 21 for the time-delay program, which have been enclosed by a broken line block 23, have been illustrated more fully in FIG. 4 and will be described in detail in conjunction therewith. 
     Finally, the electronic fuze will be seen to also encompass an impact switch 13 which is connected by means of two blocking devices 14 and 15 with the elements 21 for the time-delay program. The blocking device 14 is controlled by the reset switches 10 and 11 and the blocking device 15 is controlled by the element 18 for the barrel safety. 
     The elements 21 for the time-delay program render possible, also upon impact ignition, by means of the impact switch 13 a time-delay of the ignition in order that, for instance, the projectile can penetrate the target. 
     (2) The Stabilizer 
     (FIG. 2) 
     According to the showing of FIG. 2 the stabilizer will be seen to contain eight MOSFET-transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , T 7  and T 8  (metal-oxide-semiconductor-field-effect-transistors). The construction and operation of such type transistors are well known in the electronics art and therefore need not here be further considered. Each of the transistors T 1  to T 8  will be seen to have three terminals, conventionally designated as the source S, the drain D and the gate G. The transistors T 1 , T 2 , T 4  and T 6  have P-type channels and the transistors T 3 ,T 5 , T 7  and T 8  possess N-type channels. These transistors all may be of the enhancement type. 
     A voltage source, particularly the storage capacitor 3 illustrated in FIG. 1, is connected with the terminals 24 and 25, whereas at the terminals 26 and 27 there is connected the load, i.e., the elements which have been enclosed by the phantom or dash lines 22 and 23 in FIG. 1. The storage capacitor 3 supplies the voltage U 1 . The load requires a voltage U 2 . 
     The terminals 24 and 25 are interconnected, on the one hand, by the two transistors T 2  and T 8  and, on the other hand, in parallel thereto by the six transistors T 1 , T 3 , T 4 , T 5 , T 6  and T 7 . The terminals 26 and 27 are interconnected by means of the four transistors T 4 , T 5 , T 6  and T 7 . 
     As to the transistor T 1  the gate G and drain D are connected with one another, thus producing an approximately constant voltage U 4  between the terminal 24 and the terminal 28. At this terminal 28 there is connected the gate G of the transistor T 2 . The transistor T 1  thus controls the transistor T 2  and causes a constant current to flow in the circuit connection between the transistor T 2  and the transistor T 8 . 
     In the case of the transistors T 4 , T 5  and T 6  the respective gates G and drains D are connected with one another, producing a constant potential drop between the terminal 26 and the terminal 26&#39;. The voltage U 5  is therefore dependent upon the voltage U 2 . By means of the voltage or potential difference U 5  the transistor T 8  is controlled. 
     The mode of operation of the described stabilizer or stabilizer circuit is as follows: 
     The current requirements of the load alters and causes fluctuations of the voltage U 2 , and thus, also fluctuations in the voltage or potential difference U 5 . With a large current requirement of the load the voltage U 2  drops and there also is a drop in the potential or voltage difference U 5 . This reduction of the voltage U 5  causes the resistance of the transistor T 8  to increase, and therefore, also produces an increase of the voltage at the terminal 29 and at the gate G of the transistor T 3  and a greater amount of current flows through the transistor T 3 . As a consequence the voltage U 2  again increases. 
     In the case of smaller current requirements of the load the voltage U 2  increases, and therefore, also the voltage U 5  increases. This increase of the voltage difference U 5  causes the resistance of the transistor T 8  to become smaller, and therefore, there is also a reduction of the voltage at the terminal 29 and at the gate G of the transistor T 3  and less current flows through the transistor T 3 . As a consequence the voltage U 2  again drops. 
     The voltage drop U 4 , apart from being dependent upon the characteristics of the transistor T 1 , also depends upon the load current i L  of the load. With large current i L  the potential difference U 4  become greater, and thus, the resistance of the transistor T 2  becomes smaller. A greater amount of current flows through the transistor T 2  and therefore more current flows through the transistor T 1 . With small current i L  the voltage difference U 4  becomes smaller, and thus, the resistance of the transistor T 2  becomes greater. Almost the same amount of current flows through the transistor T 2  as through the transistor T 1 . 
     The transistors T 1 , T 2 , T 4 , T 5 , T 6  and T 7  work in the saturation region. The transistor T 3  functions as an impedance converter. The reference voltage is the threshold voltage of the transistor T 8 . The transistor T 1  produces in accordance with its characteristics and the magnitude of the load current i i  +i L  the voltage or potential difference U 4 . In analogous manner the transistor T 7  generates the potential of voltage difference U 5  in accordance with its characteristics and the current i i  flowing through the transistors T 4 , T 5 , T 6  and T 7  the voltage difference U 5 . 
     The potential or voltage difference U 4  renders possible the control of the transistor T 2  which serves as a current source. The potential difference U 5  renders possible the control of the transistor T 8 . The transistors T 4 , T 5 , T 6  and T 7  serve as voltage dividers. 
     (3) The Switching-On and Resetting Elements (FIG. 3) 
     The switching-on circuit or element 8 (FIG. 1), as best seen by referring to FIG. 3, comprises three inverters J 1 , J 2  and J 3 , two transistors T 10  and T 11  and a constant current source 30. The supply voltage for the three inverters J 1 , J 2  and J 3  is delivered by the stabilizer 4 (FIG. 1), and therefore, the inverters J 1  J 2  and J 3  are connected with the output terminals 26 and 27 of the stabilizer 4 according to FIG. 2. As shown, the inputs of the three inverters J 1 , J 2  and J 3  are connected with the constant current source 30 which, in turn, is connected with the input terminal 24 of the stabilizer 4 and by means of the transistor T 10  also with the output terminal 27. The outputs of the three inverters J 1 , J 2  and J 3  are connected by means of a resistor R 3  and via transistor T 11  with the output terminal 26 of the stabilizer 4. 
     At the output of the switching-on element or circuit 8, i.e., at the outputs of the inverters J 1 , J 2  and J 3  there is connected the first resetting switch 10 (FIG. 1) composed of a fourth inverter J 4 , the supply voltage of which likewise is delivered by the stabilizer 4, i.e., by the terminals 26 and 27. 
     Apart from the switching-on element 8 and the resetting switch 10 there is furthermore provided a second resetting switch 11 composed of two switching elements 31 and 32 and a gate 33. The first switching element 31 has two inputs d and e, wherein the input d is connected to the terminal 26 and the other input e to the output of the switching-on element 8, i.e., with the outputs of the inverters J 1 , J 2  and J 3 . Further, the first switching element 31 has two outputs, one of which is connected with gate 33 and the other with the first input g of the switching element 32. The second switching element 32 likewise has two inputs g, f wherein the one is connected with an output of the switching element 31 and the other with the oscillator 16 (FIGS. 1 and 3). Additionally, the second switching element 32 has two outputs, wherein the one is connected with the third input of the first switching element 31 and the other with the aforementioned gate 33. 
     The third resetting switch 12 consists of two gates 35 and 36 forming an intermediate storage and further comprises two gates 37 and 38 which form a flip-flop circuit. A further gate 39 is arranged in circuit between the gates 35, 36 and 37, 38. The reset circuit 12 is connected with the reset switch 10, i.e., with the inverter J 4  and with the reset switch 11, i.e., at the common gate 33 of both switching elements 31 and 32. In the case of the reset switch 12 and the output of one gate 35 is connected with an input of the other gate 36, whose output likewise is connected with the input of the gate 35. Equally, in the case of the resetting or reset switch 12 the output of the one gate 37 is connected with one input of the other gate 38, the output of which again is connected with an input of the gate 37. Hence, the gates 35 and 36, on the one hand, and the gates 37 and 38, on the other hand, each form a respective flip-flop circuit. The gate 39 located between the gates 35, 36 and 37, 38 is connected with its output at an input of the gate 38 and with its two inputs this gate 39 is connected, on the one hand, with the gates 35, 36 and, on the other hand, with the aforementioned common gate 33 of both switching elements 31 and 32 of the resetting switch 11, as shown. The mode of operation of the described switching-on or switching and resetting elements is as follows: 
     Upon firing of the projectile the generator 1 (FIG. 1) produces a current which by means of the bridge-connected rectifier 2 (FIG. 2) and by means of the internal resistance of the generator 1 charges the storage capacitor 3 (FIG. 1), with the result that there is built-up the voltage U 1  (FIG. 3). The constant current source 30 (FIG. 3), which need not here be further described, delivers a current as long as the transistor T 10  is still in its non-conductive state, and which current also causes a rise of the potential at the inputs of the three inverters J 1 , J 2  and J 3  approximately to the voltage or potential U 1 . The aforementioned input voltage U 1  causes the inverters J 1 , J 2  and J 3  to become conductive and there is formed at their outputs the mass or ground potential U o . Since the outputs of the inverters J 1 , J 2  and J 3  are connected by means of the resistor R 3  also with the gates of the transistors T 10  and T 11 , the transistor T 11  becomes conductive as soon as the stabilizer 4 has generated the voltage U 2 . Consequently, a current flows from the terminal 26 through the transistor T 11  to the outputs of the three inverters J 1 , J 2  and J 3 . This current increases and causes the transistor T 10  to also become conductive, so that the input voltage of the inverters J 1 , J 2  and J 3  drops from the value U 1  to the value null. The disappearance of the input voltage U 1  at the inverters J 1 , J 2  and J 3  and the build-up of its supply voltage U 2  has as a consequence thereof that the voltage U 3  also builds-up at its outputs. This procedure is accelerated by the resistance R which acts as a coupling element. 
     At the inverter J 4  there occurs the converse procedure. At the input of the inverter J 4  there initially prevails the voltage U o , which, as further explained above, is produced at the outputs of the three inverters J 1 , J 2  and J 3 . Thus, there appears at the output of the inverter J 4  likewise the voltage U 2  and generates a first resetting pulse. This first resetting pulse disappears as soon as there appears at the outputs of the inverters J 1 , J 2  and J 3  the voltage U 2 . 
     The aforementioned first resetting or reset pulse has the following effect: 
     (1) The switching element 32 receives the first resetting or reset pulse at the input a (the reset input). 
     (2) The switching element 31 furthermore receives a voltage pulse U 2  at the input d. 
     (3) This voltage pulse U 2  first is effective however when the switching element 31 receives at its input e the voltage pulse U 3  from the switching-on element 8. 
     (4) The switching element 31 synchronously changes its state in accordance with the pulse U 3  from the value 0 to the value 1. 
     (5) The voltage U 3  also turns-on the oscillator 16. 
     (6) As soon as the oscillator 16 delivers a first oscillation pulse at location f to the switching element 32, then the output pulse &#34;1&#34; of the switching element 31 is delivered further at location g by the switching element 32 and the output h of the switching element 32 delivers a logic pulse &#34;1&#34; to the gate 33. 
     (7) The switching element 31, as discussed above in sub-paragraph (3), has received at its input e the voltage pulse U 3  and thus produces an output pulse which likewise is delivered to the gate 33. 
     (8) As soon as the oscillator 16 delivers a second oscillation pulse then the switching element 32 is switched and delivers a logic pulse &#34;0&#34; to the gate 33. 
     (9) The switching element 31 thus delivers continuously pulses &#34;0&#34; to the gate 33, and the switching element 32, during the second oscillation pulse of the oscillator 16, likewise delivers a logic pulse &#34;0&#34; to the gate 33, so that the gate 33 delivers a second resetting or reset pulse. 
     Both of the resetting pulses have the following effect: 
     (1) The gates 35 and 36 of the resetting switch 12 are turned-on by means of the first resetting pulse and are switched back by means of the second resetting pulse. They serve only as an intermediate storage, since the edge slope of the switching-on element 8 causes a delay of the second resetting pulse. 
     (2) The gates 37 and 38 on the other hand are either turned-on by the first resetting pulse or by the second resetting pulse and only upon disappearance of the second resetting pulse are again switched back. 
     (3) The signal generated by the resetting switch 12 annihilates the blocking action of the counter 19. 
     The function of the resetting switch 12 is well known and need not be here further considered. 
     (4) The Time-Delay Elements (FIG. 4) 
     The time-delay elements of FIG. 4 will be seen to comprise the two oscillators 16 and 17 which have been shown separately in FIG. 1, but however have a partially common RC-element. This RC-element for the oscillator 16 consists of the capacitor C and the resistor R 1  and for the oscillator 17 consists of the same capacitor C and a different resistor R 2 . The remaining parts of both oscillators 16 and 17 are arranged in a housing designated by reference characters 16/17. With the broken line block 16 there is indicated the complete oscillator 16 and with the broken line block 17 there is indicated the complete oscillator 17. 
     The oscillator 16 is connected at location a by means of two gates 60 and 61 with the counter 19 (FIG. 1) for the barrel safety. The oscillator 17 is connected at location b by means of two gates 63 and 64 at the time-delay program 21 illustrated in FIGS. 1 and 4. 
     A group of eight transistors T 21 , T 22 , T 23 , T 24 , T 25 , T 26 , T 27  and T 28  in conjunction with the three gates 62, 63 and 64 serves for switching both of the oscillators 16 and 17, for instance, for turning-off the oscillator 16 and for turning-on the oscillator 17. 
     This switching operation is needed since there is required for the barrel safety a different frequency than for the impact time-delay. For the barrel safety there is employed, for instance, a frequency of 500 Hz and for the impact time-delay there is used, for instance, a frequency of 35 kHz. 
     In order to avoid any feedback effects of the oscillator 16 at the voltage source, which causes a frequency change, the aforementioned eight transistors T 21  to T 28  are connected, on the one hand, by means of two diodes D 13  and D 14  with the voltage U 3  and, on the other hand, with the voltage U o . 
     Apart from both of the oscillators 16 and 17 the time-delay elements also have a group of ten gates 50 to 59. Of these ten gates 50 to 59 the gate 50 is connected on the one hand by means of both inputs with the impact switch 13 (FIG. 1), and, on the other hand, with the element 18 for the barrel safety (FIG. 1). 
     The flip-flop circuit of the gates 51 and 52 is connected with the gate 50 and the element 18. 
     The gate 53 is connected, on the one hand, with a first of its inputs at the output of the flip-flop circuit 51, 52 and, on the other hand, is connected by means of a second input at a program switch P 4 . This program switch P 4  delivers a logic &#34;1&#34; signal or pulse when there is desired an impact time-delay i.e. a delay in the ignition upon impact and it delivers a logic signal or pulse &#34;0&#34; when there is not desired any impact delay. Furthermore, connected with this program switch P 4  are both inputs of the gate 54. The output of the gate 53 leads to the gates 62 and 60 of the oscillators 16 and 17 and to the time-delay counter 20. 
     The gate 56 is connected with the output of the flip-flop circuit 51, 52 and with the gate 54. 
     The gate 55 is connected by means of one of its inputs with the program switch P 4  and by means of its other input with the time-delay counter 20 (FIGS. 1 and 4) which exclusively counts the pulses of the oscillator 17. 
     Both of the inputs of the gate 57 lead to the outputs of the gates 55 and 56. The one input of the gate 58 leads to the output of the gate 57, whereas the other input of the gate 58 leads to the decoder 9 for the self-destruction. Finally, the one input of the gate 59 leads to the output of the gate 58, whereas the other input of the gate 59 leads to the element 18 for the barrel safety. The output of the gate 59 is connected with the end or final stage 5 (FIG. 1) which contains a thyristor for igniting the detonator or ignition cap 7 (FIG. 1). A not particularly illustrated blocking device 70 is connected with the end stage 5. Blocking 70 is controllable by means of the resetting switch 12 (FIG. 1). This blocking device 70 is capable of preventing a pulse delivered by the gate 59 from reaching the end or final stage 5. 
     The mode of operation of the described time-delay elements is as follows: 
     (1) Initially it is assumed that no impact delay i.e. delay in ignition upon projectile impact is desired. The program switch P 4  thus delivers a logic signal &#34;0&#34; or binary pulse &#34;0&#34;. As soon as the projectile strikes the target then the impact switch 13 generates a logic pulse &#34;1&#34;. If after impact the projectile is at a sufficiently great distance from the gunner, then the element 18 for the barrel safety also delivers a logic pulse &#34;1&#34;. Thus, the gate 50 switches from the logic pulse &#34;1&#34; to the logic pulse &#34;0&#34;, and the flip-flop circuit 51 and 52 likewise switches and delivers the logic pulse &#34;1&#34; to the inputs of the gates 53 and 56. As mentioned, the program switch P 4  delivers to the gates 53 and 54 the logic pulse &#34;0&#34;. Therefore, at the output of the gate 53 there appears the logic pulse &#34;1&#34;. As a result the oscillator 16 is in operation while the oscillator remains blocked. Since the output of inverter 62 is at null the transistors T 27  and T 28  are blocked. The output of the inverter 64 is also null. At the output of the inverter 53 there is present a logic signal &#34;1&#34;. The transistors T 21  and T 22   are blocked. The output of the inverter, formed by the transistors T 23  and T 26 , is thus sufficiently highly ohmic that the resistor R 2  does not have any influence upon the frequency behavior of the oscillator 16. At the output of the gate 54 there appears, however, the pulse &#34;1&#34; and at the output of the gate 56 there likewise appears the pulse &#34;0&#34;. 
     The gate 55 receives from the program switch P 4  the logic pulse &#34;0&#34; and from the counter 20 the logic pulse &#34;1&#34; and thus produces a logic pulse &#34;1&#34;. Thus, the gate 57 receives a logic pulse &#34;1&#34; from the gate 55 and from the gate 56 receives a logic pulse &#34;0&#34; and therefore produces a logic pulse &#34;1&#34;. 
     Prior to the self-destruction time the decoder 9 delivers a logic pulse &#34;0&#34; and the gate 58 receives from the gate 57 a logic pulse &#34;1&#34; and from the decoder 9 a logic pulse &#34;0&#34; and produces, in turn, a logic pulse &#34;0&#34;. As above-mentioned the element 8 for the barrel safety produces the logic pulse &#34;1&#34; and after expiration of the barrel safety time switches to the logic signal &#34;0&#34;. Thus, the gate 59 receives from the gate 58 and also from the element 18 the logic pulse &#34;0&#34; and produces a logic pulse &#34;1&#34; which is conducted to the end stage 5 provided that the blocking action of the blocking device 70 is eliminated. The ignition is thus accomplished without any time-delay. 
     (2) If an impact or ignition time-delay is desired, then the program switch P 4  delivers the logic pulse &#34;1&#34;. 
     As soon as the projectile has hit the target then the impact switch 13 produces a logic pulse &#34;1&#34;. As soon as after impact the projectile is at a sufficient distance from the gunner, then also the element 18 for the barrel safety delivers a logic pulse &#34;1&#34;. Hence, the gate 50 switches from the logic pulse &#34;1&#34; to the logic pulse &#34;0&#34; and the flip-flop circuit 51 and 52 likewise switches and delivers a logic pulse &#34;1&#34; to the inputs of the gates 53 and 56. As mentioned, the program switch P 4  likewise delivers to the gates 53 and 54 the logic pulse &#34;1&#34;. At the output of the gate 53 there thus appears the logic pulse &#34;0&#34; which is further delivered to the oscillator 17. At the output of the gate 54 there appears a logic pulse &#34;0&#34;, and thus, also the gate 56 produces a logic pulse &#34;1&#34; and there is not possible any ignition without a time-delay, since now the gate 57 is blocked. 
     The logic pulse &#34;0&#34; from the gate 53 arrives at the gate 60, and the gate 60 thus blocks and counter 19 is turned-off. Additionally, the logic pulse &#34;0&#34; of the gate 53 is applied to the gate 62 and the transistors T 21  and T 22  and by means of the gate 62 to the transistors T 27  and T 28 . The oscillator output b is conductively connected by means of the gates 63 and 64 with the transistors T 23 , T 24 , T 25  and T 26 . These transistors work as inverters and their common output is connected with resistor R 2 , whereby R 2  is R 1 . The oscillator 17 now oscillates at the greater frequency of, for instance, 35 kHz and delivers pulses to the counter 20. The program switch P 4  delivers the logic pulse &#34;1&#34; and the output of the inverter 51 likewise delivers the logic pulse &#34;1&#34;, and thus, the inverter 53 delivers at the output the logic pulse &#34;0&#34; and the counter 20 can begin to count. As soon as there have been counted the requisite number of pulses by the counter 20 then a logic pulse &#34;1&#34; is conducted to the gate 55 which likewise receives a logic pulse &#34;1&#34; from the program switch P 4 . Thus, as above described, by means of the gates 57, 58 and 59 it is possible to energize the end or final stage 5 and to ignite the detonator or fuze 7. 
     While there are shown and described present preferred embodiments of the invention, it is to be distinctly understood that the invention is not limited thereto, but may be otherwise variously embodied and practiced within the scope of the following clams. ACCORDINGLY,