Abstract:
An embodiment of a method for forming silicide areas of different thicknesses in a device comprising first and second silicon areas, comprising the steps of: implanting antimony or aluminum in the upper portion of the first silicon areas; covering the silicon areas with a metallic material; and heating the device to transform all or part of the silicon areas into silicide areas, whereby the silicide areas formed at the level of the first silicon areas are thinner than the silicide areas formed at the level of the second silicon areas.

Description:
PRIORITY CLAIM  
       [0001]     This application claims priority from French patent application No. 05/53317, filed Nov. 2, 2005, which is incorporated herein by reference.  
       TECHNICAL FIELD  
       [0002]     An embodiment of the invention relates to a method for manufacturing silicide areas of different thicknesses in a device such as an integrated circuit.  
       DISCUSSION OF THE RELATED ART  
       [0003]      FIGS. 1A  to  1 E illustrate a known method for forming a CMOS transistor of a “totally silicided” type (TOSI). The gate of such a transistor is totally silicided and the silicide thickness is approximately 100 nm. The source and drain areas of this transistor are covered with a thin silicon layer of an approximately 10-nm thickness.  
         [0004]     In an initial step, illustrated in  FIG. 1A , a conventional transistor structure is formed on a silicon substrate  1 . The transistor comprises a polysilicon gate  2  insulated from substrate  1  by a thin insulating layer  3 . Spacers  4  and  5  are placed against the sides of the stacking of thin insulating layer  3  and of gate  2 . Source/drain areas  6  and  7  are formed in the upper portion of substrate  1  on either side of gate  2 .  
         [0005]     In a next step, illustrated in  FIG. 1B , the previously-obtained structure is covered with a metal layer, for example, a nickel layer  10 . The entire structure is heated up to have nickel layer  10  react with the silicon areas in contact therewith. Silicide areas  11  and  12  at the surface of source/drain areas  6  and  7 , as well as a silicide area  13  at the surface of gate  2 , are obtained after anneal. Nickel layer  10  is then removed.  
         [0006]     At the next step, illustrated in  FIG. 1C  the previously-obtained structure is covered with an insulating layer  20 . A chem.-mech. polishing of insulating layer  20  is then performed to expose silicon area  13  at the surface of gate  2 .  
         [0007]     At the next step, illustrated in  FIG. 1D , a nickel layer  30  is deposited again on the previously-obtained structure. The entire structure is then heated up to have nickel layer  30  react with the silicon of gate  2 .  
         [0008]      FIG. 1E  illustrates the transistor structure after anneal and removal of nickel layer  30 . Silicon gate  2  is then replaced with a silicide gate  40 .  
         [0009]     A potential disadvantage of the previously-described method is that it may require a large number of steps. Further, the method may require a chem.-mech. polishing step, which may be difficult to implement industrially.  
       SUMMARY  
       [0010]     An embodiment of the present invention is a method comprising a small number of steps to form silicide areas of different thicknesses.  
         [0011]     Another embodiment is a method which is easy to implement.  
         [0012]     Yet another embodiment is a method for forming silicide areas of different thicknesses in a device comprising first and second silicon areas, comprising the steps of: implanting antimony or aluminum in the upper portion of the first silicon areas; covering the silicon areas with a metallic material; and heating the device to transform all or part of the silicon areas into silicide areas, whereby the silicide areas formed at the level of the first silicon areas are thinner than the silicide areas formed at the level of the second silicon areas.  
         [0013]     In an embodiment of the above-mentioned method, after implantation, the antimony or aluminum concentration in the first silicon areas is smaller than or equal to 5*10 15  atoms/cm 3 .  
         [0014]     In an embodiment of the above-mentioned method, after implantation, the antimony concentration in the first silicon areas is smaller than or equal to 10 15  atoms/cm 3 .  
         [0015]     According to a variation of the above-mentioned method, the method further comprises a step of removal of the metallic material.  
         [0016]     Another embodiment is a method for forming a CMOS transistor comprising the steps of: forming, in and above a silicon substrate of a first doping type, a transistor structure comprising a silicon gate insulated from the substrate by a thin insulating layer, and source/drain areas of a second doping type placed in the upper portion of the substrate on either side of the gate; and transforming the silicon gate into a silicide gate and forming silicide areas at the surface of the source/drain areas according to the above-mentioned method, the source/drain areas and the silicon gate respectively forming first silicon areas and a second silicon area.  
         [0017]     In an embodiment of the above-mentioned method, the heating step is performed at high temperature and the method further comprises an anneal at very high temperature.  
         [0018]     In an embodiment of the above-mentioned method, intended to form an NMOS-type transistor, antimony is implanted in the source/drain areas comprising N-type dopant elements.  
         [0019]     In an embodiment of the above-mentioned method, intended to form a PMOS-type transistor, aluminum is implanted in the upper portion of the source/drain areas comprising P-type dopant elements.  
         [0020]     In an embodiment of the above-mentioned method, the silicon gate comprises dopant elements of the second doping type.  
         [0021]     Still another embodiment provides a CMOS transistor structure formed in and above a doped silicon substrate of a first doping type, comprising a silicon gate insulated form the substrate by a thin insulating layer and source/drain areas of a second doping type placed in the upper portion of the substrate on either side of the gate, and such that the source/drain areas contain antimony or aluminum by a concentration smaller than 5.10 15  atoms/cm 3 .  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]     Features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.  
         [0023]      FIGS. 1A  to  1 E are cross-section views of structures obtained at the end of successive steps of a known method for forming a “TOSI” transistor; and  
         [0024]      FIGS. 2A  to  2 G are cross-section views of structures obtained at the end of successive steps of an example of embodiment of the method of the present invention applied to the forming of a TOSI transistor. 
     
    
     DETAILED DESCRIPTION  
       [0025]     For clarity, the same elements have been designated with the same reference numerals in the different drawings and further, as usual in the representation of semiconductor devices, the various drawings are not to scale.  
         [0026]     An embodiment of the invention comprises a single siliciding step, or more specifically, a single deposition of a metal layer on silicon areas to form silicide in a subsequent anneal. Prior to this siliciding step, antimony or aluminum is implanted in the upper portion of the silicon areas at the surface of which a thin silicide layer is desired to be formed. No antimony or aluminum implantation is performed in the silicon areas in which a thick silicide layer is desired to be formed.  
         [0027]     The presence of antimony or aluminum in relatively small quantity enables “slowing down” the forming of silicide and accordingly limiting the thickness of the silicide areas formed at the surface of silicon areas comprising antimony or aluminum.  
         [0028]     An example of implementation is described hereafter in relation with  FIGS. 2A  to  2 G in the case of the forming of an NMOS-type TOSI transistor.  
         [0029]     In an initial step, illustrated in  FIG. 2A , a thin insulating layer  101 , a polysilicon layer  102 , and a protection layer  103  are successively formed above a silicon substrate  100 . The protection layer is for example formed of silicon oxide or titanium nitride. Thin insulating layer  101  is for example formed of silicon oxide or of any other dielectric material exhibiting a high permittivity value.  
         [0030]     At the next step, illustrated in  FIG. 2B , the stacking of layers  101  to  103  is etched to keep a gate stack  110  comprising a thin insulating portion  111 , a silicon gate portion  112 , and a protection portion  113 .  
         [0031]     At the next step, illustrated in  FIG. 2C , spacers  120  and  121  are formed against the sides of gate stack  110 . Source/drain areas  122  and  123  are then formed, in the upper portion of substrate  100  on either side of gate stack  110 . Source/drain areas  122  and  123  are, in this example, N-type doped.  
         [0032]     At the next step, illustrated in  FIG. 2D , an antimony implantation is performed in the upper portion of source/drain areas  122  and  123 . It should be noted that gate portion  112  is protected by protection portion  113  in this antimony implantation.  
         [0033]     At the next step, illustrated in  FIG. 2E , protection portion  113  is removed to expose gate portion  112 .  
         [0034]     At the next step, illustrated in  FIG. 2F , the previously-obtained structure is covered with a metal layer  130 , for example, formed of nickel. An anneal is then performed to have metal layer  130  react with the silicon areas in contact therewith, that is, source/drain areas  122  and  123  and gate portion  112 .  
         [0035]      FIG. 2G  illustrates the structure of the transistor obtained after anneal and removal of metal layer  130 . Thin. silicide areas  140  and  141  are formed at the surface of source/drain areas  122  and  123 . Gate portion  112  has become a totally silicided gate portion  142 .  
         [0036]     As a non-limiting indication, the features of the transistor shown in  FIG. 2G  are the following:  
         [0037]     gate “length” or distance between source and drain areas  122 / 123 : 120 nm;  
         [0038]     thickness of insulating portion  111 : 2 nm; thickness of gate portion  142 : 100 nm;  
         [0039]     thickness of silicide areas  140  and  141 : 12 nm.  
         [0040]     It should be noted that in this embodiment, the ratio between the thickness of gate portion  142  and the thickness of each of silicide areas  140  and  141  is close to 10. This ratio may be greater or smaller by adjusting the antimony concentration implanted in the source/drain areas prior to the siliciding step. The higher the antimony concentration, the thinner silicidation areas  140  and  141 . For example, a thickness ratio of 10 may be obtained with an antimony concentration of approximately 3.10 15  atoms/cm 3 . When a thickness ratio smaller than 5 is desired to be obtained, antimony concentrations smaller than 10 15  atoms/cm 3  may be used.  
         [0041]     According to a variation of the previously-described method, instead of antimony, aluminum is implanted in source/drain areas  122  and  123  prior to the siliciding step. The aluminum present in source/drain areas  122  and  123  enables limiting the forming of silicide at their surface. However, it should be noted that the “limiting” power of aluminum may be weaker than that of antimony. To have a thickness ratio of 5 between the thin and thick silicide areas, an aluminum concentration of approximately 5.10 15  atoms/cm 3  may be used. An advantage, however, of aluminum over antimony, is that aluminum is a P-type dopant element conversely to antimony, which is an N-type dopant. Thus, in the case where N-type dopant elements are not desired to be introduced into the silicon area at the surface of which a thin silicide layer is formed, one may use.  
         [0042]     It should however be noted that, given the small quantites of antimony that “slow down” the forming of silicide, its use should not be disturbing in the case of a PMOS transistor. Indeed, the P-type dopant element concentrations in the source/drain areas conventionally are 10 16  atoms/cm 3  and an antimony concentration smaller than or equal to 10 15  atoms/cm 3  typically has but little effect on the doping.  
         [0043]     According to an implementation mode of the siliciding step previously described in relation with  FIGS. 2F and 2G , the siliciding is performed in two phases. The first phase comprises the reacting of source/drain areas  122 ,  123  and gate portion  112  with metal layer  130  in a “high-temperature” enclosure, for example, equal to 250° C., for a time enabling transforming an upper portion of gate  112  into an Ni 2 Si-type silicide. The transistor structure is then removed from the heating enclosure and the metal layer  130  is removed. Then, in a second phase, the transistor structure is placed back in a heating enclosure at a higher temperature, for example, equal to 400° C., to carry on the siliciding method. A portion of the Ni 2 Si silicide present in the upper portion of gate  112  then reacts with the lower portion of the silicon gate portion to form an NiSi-type silicon. A totally silicided gate portion  112  is finally obtained. The lower portion of the gate portion is formed of an NiSi-type silicide and the upper portion is formed of an Ni 2 Si-type silicide. Further, “thin” silicide areas  140  and  141  formed at the surface of source/drain areas  122  and  123  are entirely formed of Ni 2 Si-type silicide.  
         [0044]     An advantage of this siliciding method in two phases is that it may avoid the spacers  120  and  121  reacting with metal layer  130  to form on the spaces a thin conductive silicide layer that may short-circuit the gate and the source/drain areas of the transistor.  
         [0045]     Another advantage of this siliciding method in two phases is that may enable obtaining an NiSi-type silicide, which is typically less resistive than an Ni 2  Si-type silicide.  
         [0046]     Further, silicon layer  102  intended to form gate portion  112  may be P- or N-type doped before being covered with protection layer  103 . The doping of gate portion  112  enables adjusting the transistor threshold voltage. The implantation of P-type dopant elements on forming of a PMOS transistor or the implantation of N-type dopants on forming of an NMOS transistor enables having a greater capacitive coupling between the gate portion and the substrate.  
         [0047]     Of course, the present invention has embodiments other than those described here in detail.  
         [0048]     For example, in the case where silicide areas exhibiting more than two different thicknesses are desired to be formed, different antimony concentrations may be implanted prior to the siliciding step. Different elements, e.g., antimony or aluminum, may further be implanted, to obtain silicide areas of different thicknesses.  
         [0049]     Further, metallic materials other than nickel may be used to form the silicide areas. Cobalt, titanium, tungsten, ytterbium, or an alloy based on one or several of these metals such as nickel/cobalt or nickel/ytterbium, may, for example, be used.  
         [0050]     Such other embodiments are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting.