Abstract:
A method and apparatus for digital automatic frequency control includes circuitry for frequency controlling a first information portion of a digital input signal, correlating the output with a known characteristic of the first information portion, and outputting a timing signal and channel estimation signal. The digital input signal is also decimated using the timing signal and frequency controlled into a frequency controlled output signal. This signal is used, along with a signal quality estimate derived from the channel estimation signal and first information portion, to determine an estimated frequency correction signal. The estimated frequency correction signal is used to control the frequency correction steps.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to frequency control and more particularly to a system for automatic frequency control of a digital signal. 
     BACKGROUND OF THE INVENTION 
     Automatic frequency controls (AFCs) are well known, and have been used in a wide variety of applications. In conventional applications, an AFC functions by adjusting a system variable control oscillator (VCO) based on the detected input signal frequency (e.g., by detecting the peak value following bandpass filtering). Even in applications using digital input signals it is common to rely partially upon analog circuitry to implement an AFC. Thus, one may typically find digital AFCs implemented with an analog VCO preceded by a DAC (digital to analog converter). 
     A problem with such conventional AFCs is their reliance on analog circuitry in the feedback loop. Where the AFC is used with digital signaling, the analog components add both size and cost to the AFC, and limits the full processing capabilities achieved by an all digital implementation. In other words, an all digital implementation will typically yield both higher accuracy and speed than one relying on analog circuitry. 
     One possible solution for an all digital implementation in the field of communications, described in N. Sollenberger, Low-Overhead Symbol Timing and Carrier Recovery for TDMA Portable Radio Systems, IEEE Transactions on Communications, October 1990. This proposed digital AFC provides for a one symbol delay from the output of a differential demodulator for received coherent symbols, and has a frequency offset estimator using differential phase error magnitudes from the differential constellation points accumulated on a per symbol basis, along with a symbol timing estimate, to output an offset estimate to feedforward first-order carrier recovery loop. However, a major drawback with this AFC is its requirement of a relatively high C/I (carrier to interference) ratio, as much as 17 to 25 dB in Rayliegh fading, and it relies on a solely data driven approach (i.e., it assumes no knowledge of the data being communicated). In many communications environments, such as digital cellular radiotelephony, requiring a 17 dB would lead to unacceptable frequency drift since the communications systems are designed to operate at much lower C/Is, sometimes as low as 3 dB. 
     There remains therefore a need for an improved digital AFC that overcomes these problems. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a digital AFC according to a first embodiment of the invention. 
     FIG. 2 is a graph illustrating frequency control performance of a digital AFC according to FIG. 1 using a first constant μ. 
     FIG. 3 is a graph illustrating frequency control performance of a digital AFC according to FIG. 1 using a second constant μ. 
     FIG. 4 is a block diagram of a digital AFC according to a second embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     These problems and others are met with a method and apparatus for digital automatic frequency control according to the present invention. FIG. 1 shows a block diagram of a digital AFC according to a first embodiment for use in a cellular radiotelephone receiver. It should be understood, however, that the invention has application to other types of systems, including but not limited to other communication systems (computer, broadcast radio, television, etc.), control devices, and other digital electronic devices using frequency control. The following description, of a presently preferred embodiment for one type a cellular system, is thus meant for illustration and not limitation on the scope of the invention. 
     In FIG. 1 a received digital signal 115 is input to a buffer 120. Signal 115 has earlier been digitized by an A/D (analog to digital) converter (not shown), and is shown as a typical TDMA (time division multiple access) time slot. In this first embodiment, the TDMA slot has a mid-amble pilot signal of 10 symbols, with 17 data symbols preceding and following the mid-amble. Because the pilot signal is in the mid-amble, as opposed to a preamble, position a buffer 120 is used to buffer the received signal while the pilot symbols are being processed by the AFC. This buffer is not essential, particularly where the pilot signal is in the preamble position, as illustrated by the second embodiment in FIG. 4. 
     The pilot symbols are inputted to a peak correlator 132 and signal quality (C/I) estimator 144 via frequency controller/adjuster 130. On initialization, where there is no prior phase information, frequency adjuster 130 leaves the pilot signal information unchanged. Otherwise, the frequency adjuster 130 takes frequency change information from frequency estimator 148, which is described in more detail below. Each frequency-adjusted pilot symbol is still an oversampled bitstream, the embodiment of FIG. 1 showing a 16 times oversampling. The frequency-adjusted pilot symbol information is then correlated in peak correlator 132, using known information about the pilot signal, to obtain peak timing information, and output that information to decimator 134. Decimator 134 receives from buffer 120 the original input signal bitstream (data and pilot symbols) along with the timing information from peak correlator 132, and decimates the bitstream in order to output a decimated or downsampled signal at timing corresponding to that of the pilot symbol peaks. 
     Peak correlator 132 is also adapted to output channel estimate information to C/I estimator 144. C/I estimator 144 receives both the frequency-adjusted pilot signal (having both C and I information) and the channel estimate information and outputs an estimate of signal quality, or in other words a weighted C/I information signal. The channel estimate information is also normalized and conjugated in circuitry 136, 138 and applied to the frequency-adjusted, decimated signal via multiplier 142, to output a phase-adjusted signal. This signal is further adjusted by multiplying it with the estimated C/I information at multiplier 146 to yield a weighted signal output. 
     The weighted signal is then input to frequency estimator 148, along with the estimated C/I from C/I estimator 144. The frequency estimator 148 extracts each received pilot symbol r n  received at time n, and processes the received pilots by conjugating (x n  =r n  r* n-1 ) and normalizing (s n  =(x n/ | x n  |)) them into received pilot vector S=[s 1  s 2  . . . s n  ]. Similarly, frequency estimator 148 processes the known transmitted pilot symbols p n , corresponding to received pilot symbols r n , into known pilot vector Y=[y 1  y 2  . . . y n  ], where y n · =p n  p* n-1 . These two vectors are then processed to derive the estimated frequency correction Δω t  as follows: 
     
         sin (Δθ)=(1/N-1) Imag (S·Y*.sup.T) approx.=Δθ; 
    
     
         Δθ=ΔωT; 
    
     
         and 
    
     
         Δω.sub.t =Δω.sub.t-1 +μ·η·Δθ, 
    
     where η is the estimated C/I per slot (or hop in a slow frequency hopping system) and μ is a constant for controlling the adaptation rate. It has also been assumed that the symbol to symbol rotation in constellation is small, such that sin (Δθ) can be approximated with Δθ. For example, a 9 KHz frequency offset (i.e., 5 ppm (parts per million) at 1.8 GHz) corresponds to about a 13 degree shift between adjacent symbols (assuming a symbol rate of 250 Ksymbols per second), which satisfies the above condition. 
     The processed Δω n  then becomes the next Δω n-1  and applied to frequency adjusters 130 and 134. For a given data vector r=[r 1  r 2  . . . r m  ] of size M, the phase rotation performed by frequency adjusters 130 and 134 is ##EQU1## where r&#39; denotes the phase rotated vector. It should also be noted that the phase rotation is referenced to the middle symbol (center of the pilot vector) in the above equations. 
     Turning to FIGS. 2 and 3, the variation in the step response of a system is illustrated for different values of μ. FIG. 2 illustrates the step response for μ=1, assuming 500 Hops (or time slots) per second, C/I of 4 dB, and a transmitting unit traveling at 97 kilometers per hour. FIG. 3 illustrates the step response for the same conditions except for a reduced μ=0.1. Thus, it is clear that the larger the value of μ used, the faster the response time will be. On the other hand, there will also be a substantially increased jitter in the frequency offset at a higher μ. Consequently, it is presently preferred to use a larger μ on starting up the system for a faster step response, and then switch to smaller values to establish a more constant frequency offset. 
     FIG. 4 shows an AFC according to a second embodiment of the invention. In this AFC the circuitry has remained substantially the same, with similar elements retaining the same numbering as in FIG. 1. Where this AFC differs from that of FIG. 1 is the removal of frame buffer 120, and replacement of multiplier 146 with multiplier 446 on the input line to frequency estimator 148. As noted above, frame buffer 120 may be omitted when the pilot signal is found in a preamble position in the time slot. Further, while it is considered advantageous in many applications to weight the frequency and phase corrected data stream output, where a weighted output is not desired one may do the weighting via a multiplier 446 on the input to frequency estimator 148. 
     The invention has thus been described with reference to illustrative embodiments thereof. It will be apparent to one skilled in the art that various modifications and changes can be made without departing frown the spirit and the scope of the invention. For example, the invention is not limited to systems using TDMA signals, as any signal having a known information portion may be used in correcting other data portions. Rather, the spirit and scope of the invention should be understood in view of the claims below.