Abstract:
A coprocessor architecture specifically adapted for parallel operation as one of an array of coprocessors is described. Each of the coprocessors of the array are commonly responsive to a host processor. The coprocessor architecture preferably includes a selector for enabling the responsiveness of the coprocessor architecture to instructions from the host processor including an enabled responsiveness unique among the plurality of coprocessors and enabled responsiveness that is in common with that of the plurality of the coprocessors. The coprocessor architecture further includes a microengine for qualifying the responsiveness of the coprocessor to instructions provided by the host processor including qualification of the enabled responsiveness of the coprocessor architecture as provided for by the selector. Consequently, the coprocessors of the array are readily managed both individually and, from the perspective of the host processor, as a single entity operating as a single instruction, multiple data machine. As such, the coprocessor array requires little, if any, managerial support from the host processor, regardless of the specific number of coprocessors participating in the coprocessor array.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention. 
     The present invention generally relates to computer architectures that employ coprocessors closely coupled to a host processor and, in particular, to a coprocessor architecture that allows multiple coprocessors to be functionally configured to selectably implement a highly parallel single instruction, multiple data machine by the utilization of close inter-coprocessor coupling to obtain concurrency in operations on respective coprocessor data. 
     2. Description of the Related Art. 
     Computer coprocessors are utilized in a wide variety of computer systems, though typically in conjunction with micro, super-micro, mini and super-mini computer systems, to implement an equally varied number of fairly specific functions. Typically, the specific functions performed by these coprocessors are closely tailored or dedicated to a particular type of operation, such as servicing a particular end device, while presenting a very high level interface to the host processor of the computer system. Typically, the dedicated functions supported by coprocessors include direct hardware supported numerical data computations, support of a specific high-level communications network and management of high speed data channels further in support of, perhaps, other dedicated coprocessors. 
     Conventionally, each coprocessor within a computer system is a largely separate entity particularly from the perspective of the host processor. That is, each high level function of the various coprocessors within a computer system must be separately initiated, and where required, specifically managed by the host processor itself. Consequently, the host processor is significantly burdened since it is required to effectively function as the primary communication conduit between coprocessors performing interdependent tasks or functions. 
     With the advent of coprocessors, an immediate and continuing desire has been to increase their respective performance in executing their corresponding dedicated functions. However, coprocessors are typically fully defined chip-level devices. Therefore, specific aspects of their design are rigorously set from the outset. Fixed bus width and maximum processing speeds results in a hard limit on the performance of the coprocessor. This, in turn, leads to the necessary development of subsequent generations of coprocessors to provide incremental improvements over the previous generation coprocessors. However, the hard upper limit on the processing performance of each coprocessor remains fixed for its generation, regardless of its generation of development. 
     A somewhat simplistic appearing alternative to awaiting subsequent coprocessor generations is to utilize several coprocessors in parallel. There are, however, a number of rather fundamental difficulties in a realizing any significant performance gain in this manner. Each coprocessor is an integral, functionally complete unit and, therefore, not readily adaptable to truly parallel operation. Consequently, execution of the function requested of paralleled coprocessors cannot be efficiently performed unless the function is conveniently partitionable to independent, parallel subfunctions in number equaling or less than the number of paralleled coprocessors. 
     Another problem with the simple paralleling of conventional coprocessors is that the nominally minimum initialization and any subsequent management functions performed by the host processor increases in at least direct proportion to the increased number of the coprocessors utilized. Indeed, the burden on the host processor likely increases at a greater than linear rate due to the increasing complexity of the initialization and management functions required of the host processor due to the increasing number of the coprocessors. 
     The foregoing problems are substantially compounded in any application where the paralleled coprocessors are performing processes that are in any way interdependent. For example, if a single end result is required from the function performed globally by conventional, paralleled coprocessors, the host processor is required to collect the respective interim process results from the paralleled coprocessors and distribute it globally at each processing step where a final result might be obtained. Further, if the execution timing of the paralleled coprocessors is in any way data dependent, the host processor is further burdened with the responsibility of ensuring that the paralleled coprocessors ar synchronized for contributing properly corresponding interim results. 
     Alternately, the data dependent execution speed of the paralleled coprocessors might be masked by the enforced treatment of all data dependent execution operations as occurring at their worst case execution speed. Such an enforced lock-step execution would relieve the host processor of a substantial coprocessor management burden. However, the typically wide variance in actual to worst-case execution speed would result in a corresponding loss in the possible net performance gain obtained through the utilization of paralleled coprocessors participating in the performance of a single dedicated function. 
     SUMMARY OF THE INVENTION 
     Therefore, a purpose of the present invention is to provide a coprocessor architecture particularly suited for use in a multiple, parallel coprocessor architecture configuration while requiring little, if any, additional initialization and managerial processing participation by the host processor. 
     This is accomplished in the present invention by the provision of a coprocessor architecture specifically adapted for parallel operation among a plurality of such coprocessors, where each coprocessor is responsive to a common host processor. The coprocessor architecture preferably includes a selector means for enabling the responsiveness of the coprocessor architecture to instructions from the host processor including an enabled responsiveness unique among the plurality of coprocessors and an enabled responsiveness that is in common with that of the plurality of the coprocessors. Preferably, the coprocessor architecture further includes a microengine means for qualifying the responsiveness of the coprocessor to instructions provided by the host processor including qualification of the enabled responsiveness of the coprocessor architecture as provided for by the enabling means. 
     Thus, an advantage of the present invention is that it achieves the ability to operate both individually and in parallel with other coprocessors in the performance of a dedicated coprocessor function. 
     Another advantage of the present invention is that it provides for the operation of an array of like coprocessors as a single instruction, multiple data machine, thereby allowing wide flexibility in the specific configuration and maximum execution performance achievable jointly by the array. The manner of selecting either single instruction, multiple data or multiple instruction, multiple data modes of operation is reduced by way of the present invention to a very low-level task quite easily performed by the host processor. 
     A further advantage of the present invention is that it fully accommodates the execution of data dependent operations when executing a single instruction, multiple data function. This is achieved in the present invention without requiring any intervention or direct participation by the host processor. Data dependent operations are performed by the coprocessor architecture at an effective maximum speed corresponding to the longest actual execution period required by any of the coprocessors for the respective actual data processed. Consequently, instruction synchronization is maintained by the present invention while execution proceeds in the paralleled coprocessors at a jointly maximum rate. 
     Still another advantage of the present invention is that it provides for the coprocessor wide, or global, exchange of corresponding interim results at decision points during the execution of an instruction. This too is achieved in the present invention without any intervention or managerial participation by the host processor. 
     A still further advantage of the present invention is that it implements a global prioritization scheme to coordinate the execution of dedicated subfunctions of the multiple parallel coprocessor architecture. Additionally, the prioritization scheme of the present invention specifically allows the participation of other devices of the computer system, including conventional coprocessors and the host processor itself, in obtaining priority access to the resources nominally managed by the multiple parallel coprocessor architecture. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other attendant advantages and further features of the present invention will become apparent and better understood by reference to the following detailed description of the invention particularly when considered in conjunction with the accompanying drawings, wherein like reference numerals designate like parts throughout the figures thereof, and wherein: 
     FIG. 1 is a simplified block diagram of a computer system including a paralleled coprocessor array utilizing a coprocessor architecture in accordance with a preferred embodiment of the present invention; 
     FIG. 2 is a block diagram of a coprocessor architecture constructed in accordance with a preferred embodiment of the present invention; 
     FIG. 3 is a detailed block diagram of the parallel coprocessor array interconnections between coprocessor architectures and a conventional coprocessor interfaced therewith as implemented in accordance with a preferred embodiment of the present invention; 
     FIG. 4 is a simplified timing diagram illustrating the operation of the present invention in optimally maintaining instruction synchronization throughout the execution of the data dependent operations in accordance with a preferred embodiment with the present invention; 
     FIG. 5 is a simplified timing diagram illustrating the operation of the present invention in providing the the global exchange of interim result information in accordance with a preferred embodiment of the present invention; 
     FIG. 6 is a simplified timing diagram illustrating the prioritization of coprocessor architecture subfunctions in accordance with a preferred embodiment of the present invention; and 
     FIG. 7 is a simplified timing diagram illustrating the prioritization of coprocessor architecture functions in combination with an external device in accordance with a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A computer system, generally indicated by the reference numeral 10 and utilizing a number of coprocessors paralleled in accordance with the present invention, is shown in FIG. 1. The computer system 10 preferably includes a host processor 12 coupled to a system bus 16 via a host interface bus 18 for the transfer of control, address and data signals. A system memory 14 is similarly coupled to the system bus 16 by a system memory interface bus 20. In accordance with the present invention, multiple paralleled coprocessors (MPCP) 26, 28, 30 are also respectively coupled to the system bus 16. Together, these coprocessors form a multiple, parallel coprocessor architecture array 25. 
     A substantially conventional coprocessor (CPX) 22 is provided to perform a dedicated function such as direct memory address control. Accordingly, the conventional coprocessor 22 is coupled to the system bus 16 via a DMA interface bus 24 and directly to the host processor 12 via interrupt request and acknowledge control lines 72. In accordance with a preferred embodiment of the present invention, the conventional DMA coprocessor 22 is preferably configured to provide address and control signals to a direct I/O channel buffer 96 via a control line 76. Thus, data corresponding to specific addresses selected by the conventional DMA coprocessor 22 may be transferred between the system memory 14 and the direct I/O channel buffer 96 via the system bus 16 and a direct I/O data channel interface bus 78. 
     In a preferred embodiment of the present invention, the multiple parallel coprocessors of the array 25 provides for high level, graphics oriented management of respective sets of video display memory planes and, further, for providing various display memory and video control functions associated with the presentation of a video graphic data stream. Thus, in accordance with the present invention, the multiple parallel coprocessors, 26, 28, 30 are coupled by respective display control, address and data busses 50, 52, 54 to respective display memory buffers 32, 34, 36. The display buffers 32, 34, 36 each preferably provide four display memory bit planes for the storage of graphics and display information. The bit planes of the display memories 32, 34, 36 are, in turn, preferably connected to respective video circuit 38, 40, 42 by video memory data busses, 56, 58, 60. The video circuits 38, 40, 42 preferably include control circuitry, such as data serializers, color palettes, and digital to analog converters, as desired to provide respective video data streams on the video circuit output lines 62, 64, 66. The selection and control of the various functions present within the video circuits 38, 40, 42 is preferably selected by the respectively associated multiple parallel coprocessor 26, 28, 30 via the provision of control signals on the respective video circuit control lines 86, 88, 90. 
     In accordance with the present invention, the multiple parallel coprocessors 26, 28, 30 are closely interconnected for sharing control information regarding the synchronized execution of data dependent operations, corresponding interim or parallel partial results, synchronized performance of prioritized subfunctions, synchronized admittance of an external device to access other devices nominally managed exclusively by coprocessor array 25 and common synchronization to an external timing source. Specifically, the multiple parallel coprocessors 26, 28, 30 effectively share a control bus 68 for communicating directly among themselves substantially independent of the host processor 12. However, other devices, such as the host processor 12 and the conventional coprocessor 22, may be coupled to the communication bus 68 specifically for providing requests to access the display memory 32, 34, 36. Grant of an external device request is acknowledged in unison by the multiple parallel coprocessors 26, 28, 30 by provision of an acknowledge status signal on an acknowledge control line 70. Once an external device is granted access, the direct I/O data channel buffer 96 becomes a gateway for data operations directly on the devices attached to and nominally managed by the coprocessor array 25, while the individual multiple parallel coprocessors 26, 28, 30 remain largely idle. 
     The preferred nominal mode of operation of the present invention, however, only utilizes the host processor 12 to provide a high level instruction and related data to each of the multiple parallel coprocessor array 25 via the system bus 16 and coprocessor instruction data busses 44, 46, 48. In order to minimize the processing burden on the host processor in distributing the various instructions and data, the present invention provides for two basic host selectable modes of instruction transfer operation. An address decoder 13 is preferably provided coupled to the address lines of the system bus 16 to provide respective chip select control signals to the multiple parallel. coprocessors 26, 28, 30. Thus, as indicated in Table I, a host processor 12 memory access operation directed to an address recognized by the address decoder 13 results in the generation of a corresponding chip select signal In accordance with a preferred embodiment of the present invention, a write operation directed to an address A 6  of binary one and A 5-2  of binary zero, the address decoder 13 preferably provides respective chip select signals simultaneously to each of the multiple parallel coprocessors 26, 28, 30. 
     
                       TABLE I______________________________________A.sub. 6A.sub. 5       A.sub. 4              A.sub. 3                   A.sub. 2                       -R/W   Mode______________________________________1    0      0      0    0   1      Broadcast Write1    0      0      0    0   0      Broadcast Read1    0      0      0    1   1      Write MPCP #11    0      0      0    1   0      Read MPCP #11    0      0      1    0   1      Write MPCP #21    0      0      1    0   0      Read MPCP #21     n             1        Write MPCP #n1    n              0        Read MPCP #n0    X      X      X    X   X      No Coprocessor Access______________________________________ 
    
     As a result, the instruction and data provided by the host processor 12 is simultaneously broadcast and received by all of the coprocessors 26, 28, 30 of the array 25. Thus, where the multiple parallel coprocessors 26, 28, 30 are to perform the same sequences of instructions, the burden on the host processor 12 in sourcing those instructions and data is fully independent of the number of multiple parallel coprocessors 26, 28, 30 present within the array 25. 
     If, instead, a broadcast read operation is performed, in accordance with a preferred embodiment of the invention, each of the mutltiple parallel coprocessors of the array 25 provide a respectively corresponding portion of a composite data word to be effectively read by the host processor 12. That is, in a preferred embodiment of the present invention, each four memory planes, as associated with respective coprocessors of the array 25, are logically stacked such that each pixel includes a positionally corresponding bit in each memory plane. In response to a broadcast read operation, each coprocessor may just provide four bits of a preselected pixel to the host processor 12 in parallel with respective sets of four bits from other coprocessors of the array 25. Consequently, the array 25 can provide a complete pixel data word to the host in response to a single read operation. 
     Where it is necessary to provide or obtain individualized information and data with regard to any specific one of the multiple parallel coprocessors of the array 25, in accordance with the present invention, the host processor 12 selects a unique multiple parallel coprocessor mode of addressing by merely directing its access operation against the address of the specifically chosen multiple parallel coprocessor. 
     The significant architectural blocks of a multiple parallel coprocessor 26, as constructed in accordance with a preferred embodiment of the present invention, are shown in FIG. 2. The principle block is a micro-engine 100. Preferably, the micro-engine 100 is a micro-coded sequencer that operates specifically to implement the high level instructions provided by the host processor 12. The micro-engine 100 includes or is intimately associated with a number of data storage registers 98 for storing configuration and operation defining data. The instructions and their corresponding data are preferably provided onto an internal instruction and data bus 106 from the instruction and data interface bus 44. Actual transfer of specific instructions and data from the instruction and data bus 44 to the internal instruction and data bus 106 is qualified for each multiple parallel coprocessor 26 by the presence or the absence of its corresponding chip select control signal as provided on its respective chip select line 19 1 . 
     Preferably, the data stored by the data storage registers 98 is used to further qualify the operation of the micro-engine 100 upon micro-engine receipt of instructions and data. In accordance with the preferred embodiment of the present invention, one register of the data storage registers 98 is utilized to store an array position code. Preferably, this position code is assigned directly in response to the receipt of a host instruction. A &#34;Set Position&#34; instruction is preferably realized as a single 16 bit instruction word having an instruction unique operand at instruction bits I 6-0  and a position code at instruction bits I 15-10 . Upon receipt of this instruction, the micro-engine 100 copies the position code into a position code register (QPR) 98 1 . Since each multiple parallel coprocessor of the array 25 is assigned a unique position code, the &#34;Set Position&#34; instruction is individually issued by the host processor 12 to each of the multiple parallel coprocessors 26, 28, 30. 
     In the preferred embodiment of the present invention, another of the registers 98 is preferably utilized to store four activity status bits to respectively define the activity status of its associated four display memory bit planes. The activity status bits allow instructions directed generally against all four display memory planes to be specifically disregarded with respect to any display memory plane whose corresponding activity status bit is reset to zero, i.e. is inactive. That is, on receipt of an instruction, the micro-engine 100 checks the data stored in the activity status register (QSR) 98 2  and then effectively executes the instruction only with respect to the display memory planes whose corresponding activity status bit is set by simply not writing the results of the instruction to the inactive memory planes. 
     Preferably, data is stored to the activity status register 98 2  in response to a &#34;Set Activity Bits&#34; instruction. In accordance with the preferred embodiment of the present invention, the host processor 12 need not individually address each coprocessor of the array 25. Instead, the activity status register 98 2  is set in up to four multiple parallel coprocessors 26 simultaneously by the issuance of a single instruction. This is achieved by utilizing an instruction having a position sensitive broadcast format as generally indicated in Table II. 
     
                       TABLE II______________________________________POSITION CODE SENSITIVEBROADCAST FORMAT______________________________________ ##STR1##______________________________________ 
    
     The &#34;Set Activity Bits&#34; instruction is issued in broadcast mode with a host processor specified position code mask in the high order four bits (QPH) of its 16 bit instruction word. As before, the low order seven bits of the instruction word contain the unique opcode specifying &#34;the Set Activity Bits instruction&#34;. An intimately associated 16 bit data word is provided immediately after the instruction by the host processor. The data word is logically partitioned into four fields of four bits each. Each field preferably contains the four activity bits that are to be stored in four respective activity bit registers. The selection of a particular four bit data field for storage in the activity status register 98 2  of a specific multiple parallel coprocessor 26 is determined upon receipt of the instruction and data by the micro-engine 100. Preferably, the micro-engine 100 examines the QPH field of the instruction and determines whether the value found matches that of the four high order bits of its own currently &#34;Set Position&#34; code. If the two values match, the value formed by the two least significant bits of the micro-engine&#39;s position code register 98 1  is used as a pointer to one of the four data fields accompanying the instruction. The four activity status bits of the corresponding data field are then loaded into the micro-engine&#39;s activity status register 98 2 . However, if the micro-engine 100 did not obtain an exact match between the four bit position code value of the instruction and the value formed by the high order four bits of its position code register 98 1 , the instruction is effectively ignored and the micro-engine 100 does not alter the data stored by its activity status register 98 2 . 
     Much in the same way that the activity status bits define whether instructions are to be effectively executed with regard to specific display memory planes, the present invention also provides for the use of additional registers 98 n  for respectively qualifying various preselected aspects of instruction execution by the micro-engine 100. For example, in a preferred embodiment of the present invention, a color bit register 98 3  is utilized to define an active drawing color for each of the four memory planes of the display memory 32. That is, each display memory plane has a corresponding single bit color field for defining the current or default color memory value to be written into pixel corresponding memory locations of its corresponding display memory plane. Preferably, the color bit register is set in response to a &#34;Set Color Bits&#34; instruction issued in broadcast mode by the host processor 12 utilizing the position sensitive broadcast format given in Table II. 
     In accordance with the present invention, status bits within any of the registers 98 may be also utilized by the micro-engine 100 as a basis for further qualifying any action qualified by the status bits present in any other of the registers 98. Thus, in a preferred embodiment of the present invention, a video graphic function known conventionally as a seed fill operation is supported by the coprocessor array 25. This operation is performed to typically change the color of all pixels located within an arbitrarily shaped border defined by a known pixel search color value. As the seed fill operation is executed, beginning at a pixel location known to be within the border, the color value of an adjacent pixel memory location is obtained, compared against the search color value, and, if different, the drawing color register 98 3  pixel color value is written back to the display memory. Where a pixel having the boundary color value is found, the direction of the search is effectively altered and the execution of the seed fill operation continued until the pixel area effectively defined by the boundary is filled As before, each coprocessor of the array 25 is provided with a search color value by the broadcast mode issuance of an appropriate position code sensitive broadcast format instruction. Accordingly, the present invention provides for a search color value register 98 4  to store a single data bit per display memory plane as a respective search color value. That is, a data bit of the display memory color value accessed is compared against its respective display plane search color data bit in determining a search color value match. 
     In a preferred embodiment of the present invention, a listen data bit register 98 5  is also provided. The preferably four data bits in this register again correspond to the respective display memory planes associated with a multiple parallel coprocessor 26. The listen bit register 98 5  is preferably set in response to a set listen register instruction and associated data word. This instruction and data word are preferably broadcast issued by the host processor 12 in the position sensitive broadcast format of Table II. The preferred use of the listen data bits is in conjunction with the execution of the seed fill instruction. Significantly, the effect of the individual listen data bits on the operation of the micro-engine 100 is qualified by their corresponding activity status bits as stored by the status bit register 98 1 . Preferably, the micro-engine 100 examines the listen data bit for each display memory plane and, where reset, simply reports a pixel and search color value bit match for that particular display memory plane. Alternately, if the listen bit is set, then the the pixel and search color are compared and a match is reported only if they are identical. 
     There is, in the preferred embodiment of the present invention, a distinct difference in the result obtained for display memory planes where the activity status bit is reset and where both the activity status bit and listen data bit are set. The preferred effect of the activity status bit is to control whether write operations to the corresponding display memory plane will be allowed. Thus, in seed fill operations, the display memory plane bit values will change only for the planes that have their activeity bit set. In distinction, the effect of the listen status bit, when reset, is simply to exclude its corresponding display memory plane from participating in the pixel color matching operation. 
     Finally, the micro-engine 100 provides match-out (MO) and receives match-in (MI) control signals or control lines 116, 118, respectively. For purposes described in greater detail below, the match-out control signal is preferably provided on completion of execution of each data dependent instruction. Additionally, the match-out signal may be provided at a decision point during the execution of any instruction to specify a current decision point interim result as developed by the execution of the instruction upto the corresponding decision point. The match-in signal is sensed by the micro-engine 100 either to determine when to start execution of the next instruction or to receive an overriding decision point interim result for us in the further execution of the current instruction. 
     In order to explain the operation of the present invention, the additional functional blocks of the multiple parallel coprocessor 26 must be considered. As stated above for a preferred embodiment of the present invention, each multiple parallel coprocessor 26 preferably manages a respective display memory. Each display memory is preferably implemented as an array of dynamic random access memory (DRAM) cells. Accordingly, a DRAM refresh control block 102 is implemented in the multiple parallel coprocessor 26 for timing and controlling DRAM refresh cycles on the display memory 32. Similarly, the display memory 32 must be periodically accessed and provided to the video circuit 38 in order to refresh the video data shown. Accordingly, a video refresh controller 104 is also provided within the multiple parallel coprocessor 26. 
     In the performance of a DRAM or video refresh or any operation of the micro-engine 100 requiring an access of the display memory 32, the appropriate address and data signals are passed from the DRAM or video refresh controllers 102, 104 or micro-engine 100 to the internal bus 106 and then to a display memory access controller 110 before being provided onto the display memory address and data bus 50. Accesses of the display memory 32 by any of these three blocks 100, 102, 104 are, of necessity, mutually exclusive. Therefore, an arbitration control block 108 is provided to prioritize all display memory access operations. Preferably, the arbitration control block 108 receives DRAM refresh requests (RD) from the DRAM refresh controller 102, video refresh requests (RV) from the video refresh controller 104, and micro-engine access requests (RE) from the micro-engine 100. In turn, the arbitration control block 108 selectively provides respective acknowledge DRAM refresh (AD), acknowledge video refresh (AV) and acknowledge micro-engine (AE) control signals. Additionally, the arbitration control block 108 allows for the receipt of externally sourced display memory access request signals (XI) on a memory request control line 120 and a memory access control signal (XO) on the output control line 122. Each block or source of a request proceeds with its desired accesses of the display memory only on receipt of its respective acknowledge control signal. In accordance with a preferred embodiment of the present invention, the relative priority of the various requests submitted to the arbitration control block 108 are as shown in Table III. 
     
                       TABLE III______________________________________DISPLAY MEMORY ACCESS PRIORITY______________________________________Highest:   VIDEO REFRESH REQUEST      DRAM REFRESH REQUEST      EXTERNAL ACCESS REQUESTLowest:    mENGINE ACCESS REQUEST______________________________________ 
    
     FIG. 3 illustrates the inter-connection of multiple parallel coprocessor architecture within the array 25 in combination with a relatively conventional external device (CPX&#39;) 22&#39;, such as the host processor 12 or direct memory access controller 22. The various inter-connections, in accordance with the present invention, permit essentially any number of the multiple parallel coprocessors 26, 28 to synchronously execute identical data dependent instructions at the optimum rate for the actual data affected, to effectively share interim, decision point result information, to identify a specific priority task to be performed by each of the multiple parallel coprocessors 26, 28 and to provide for the inclusion of the external device 22&#39; within the priority scheme of the multiple parallel coprocessor array 25. 
     The significant advantage of the array of multiple parallel coprocessors 26, 28 synchronously executing identical instructions is that it becomes, in effect, a single instruction, multiple data machine. Consequently, the array 25 appears as a single entity to the host-processor 12 largely independent of the number of multiple parallel coprocessors actually implemented in the array and whose performance is largely limited only by the number of multiple parallel coprocessors provided in the array 25. The single instruction, multiple data operation of the multiple parallel coprocessor array 26, 28 must take into account the fact that each multiple parallel coprocessor 26, 28 will obtain varying execution times in the performance of data dependent instruction. In accordance with the preferred embodiment of the present invention, each multiple parallel coprocessor 26, 28 utilizes a first-in, first-out register file (not separately shown) for buffering instructions and data as received from the host processor 12. This effectively removes any possible burden on the host processor 12 as to when any specific instruction could be broadcast for the array of multiple parallel coprocessors 26, 28. However, the instruction execution integrity of the array of multiple parallel coprocessors 26, 28, operating as a single instruction, multiple data machine, requires that all of the multiple parallel coprocessors 26, 28 execute each data dependent instruction within a respective time frame, common to the entire array 25. In accordance with the present invention the data dependent instruction execution time frame is minimized to the longest period actually required by any individual multiple parallel coprocessor 26, 28 for its proper execution of the instruction. Thus, depending on the actual data operated on, every instruction is executed in the minimum period required by the array of multiple parallel coprocessors 26, 28 as a whole. This result is accomplished in the present invention by utilizing the match output signals as provided on the respective MO control lines 132, 134 to determine that the execution of the current instruction has been completed by the array 25. Each MO control line 132, 134 is provided as a respective input to an AND gate 150. The respective MO control lines from other multiple parallel coprocessors of the array 25 are indicated collectively by the single MO control line 136. Consequently, in accordance with the present invention, the AND gate 150 provides a composite execute complete signal on its output line 138 for distribution to each multiple parallel coprocessor 26, 28 of the array 25. 
     This instruction synchronization feature of the present invention is illustrated in greater detail in the timing diagram of FIG. 4. The CLK 1  and CLK 2  signals represent the respective internal execution synchronous clock signals of the two respective multiple parallel coprocessors 26, 28 illustrated in FIG. 3. Although the CLK 1  and CLK 2  signals may be ultimately derived from the same system clock source, a relative timing skew of the execution synchronous clock signals of each of the coprocessors, due to propogation delay and other factors, must be expected and tolerated. 
     As indicated, the first multiple parallel coprocessor 26 concludes the execution of an operation at t 1  and immediately thereafter provides its match-out signal (MO 1 ). The first multiple parallel coprocessor then begins sensing for the composite execution complete signal (MI) on its match-in control line 138. Thus, for example, during the second half of a CLK 1  cycle, such as beginning at t 4 , the first coprocessor 26 determines that the composite execution complete control signal is not present. At the leading edge of the CLK 2  signal occurring at t 8  the second multiple parallel coprocessor completes the execution of its instruction. An execution complete signal (MO 2 ) is provided on the match out control line 134 following t 8 . Assuming that all other multiple parallel coprocessors of the array 25 have similarly completed the execution of their instructions, AND gate 150 provides the composite execution complete signal on the MI control line 138. The composite execution complete signal is sensed by the multiple parallel coprocessors 26, 28 at about t 10  and t 11 , respectively. As a result, with the next rising clock edge of the CLK 1  and CLK 2  signals, the MO 1 , MO 2  and execution complete signals are withdrawn and synchronous execution of the next instruction beings. Consequently, the present invention optimally provides for the essentially simultaneous beginning of instruction execution as soon as the last of the multiple parallel coprocessors of the array 25 has completed execution of its prior instruction independent of whether the instructions have fixed or data dependent execution periods. 
     Another requirement of a single instruction, multiple data machine is that the individual multiple parallel coprocessors 26, 28 effectively share interim results information at each instruction execution decision point as may occur for the proper execution of an instruction. That is, a single instruction may require a specific data condition to obtain commonly throughout the single instruction, multiple data machine. Efficient execution of this instruction requires communication among the individual multiple parallel coprocessors 26, 28 at each possible data condition decision point until the condition is satisfied for the entire machine. 
     The sharing of a data condition at a decision point during the execution of an instruction is implemented in a preferred embodiment of the present invention by utilizing the same match-out and match-in control signals as utilized in the above described instruction synchronization process. Further, in a preferred embodiment of the present invention, an example of an instruction requiring the sharing of decision point data condition information is the seed fill instruction. Specifically, the seed fill instruction requires a determination of whether the current pixel value corresponds to that of the specified boundary pixels Since the data corresponding to a complete single pixel lies across numerous bit planes and is, therefore, managed in part by each of the individual coprocessors of the array 25, each multiple parallel coprocessor 26, 28 is required to determine whether its respective portion of the boundary and the search pixel values match. However, only when all of the multiple parallel coprocessors of the array 25 obtain a match result can it be determined that a border pixel has been found. 
     The operation of the present invention, in determining a match condition, is illustrated in the timing diagram of FIG. 5. As before, the two CLK 1  and CLK 2  signals represent the potentially skewed internal execution clocks of two multiple parallel coprocessors 26, 28. The multiple parallel coprocessor 26 corresponding to CLK 1 , as shown, has determined at t 1  that a match data condition exists, at least with respect to itself, by a comparison between the pixel value accessed from its display memory and the search pixel value provided by the host processor 12. Consequently, shortly after t 1 , the first multiple parallel coprocessor provides its match out (MO 1 ) signal on the MO line 132 as the first step in obtaining a consensus determination of the array wide data condition. 
     Similarly, the second multiple parallel coprocessor 28 determines a match, at least with respect to itself, at about t 2 . Accordingly, the second multiple parallel coprocessor 28 provides its MO 2  signal shortly thereafter. Assuming that all other multiple parallel coprocessors of the array 25 likewise detect respectively local matches, the AND gate 150 provides a composite match found signal on the composite result control line 138 to all of the multiple parallel coprocessors of the array 25. As before, during the second half of the CLK 1  and CLK 2  signal cycles, the multiple parallel coprocessors 26, 28 sense the state of the composite match found signal from the composite result control line 138. As a result, all of the multiple parallel coprocessors of the array 25 jointly determine that a full pixel value match has occurred. The individual micro-engines 100 within the multiple parallel coprocessors of the array 25 therefore conclude the decision point determination by continuing the execution of the seed fill operation in an identical manner as appropriate to the finding of a border pixel. 
     Alternately, only one or a few of the multiple parallel coprocessors of the array 25 may determine that respectively local matches exist. As shown in FIG. 5, a first multiple parallel coprocessor 26 may appropriately determine that a match, at least with respect to itself, exists at t 13 . The second multiple parallel coprocessor 28, however, determines no local match. Thus, shortly after t 16  the coprocessors of the array 25 correctly observe the absence of a composite match found control signal. Consequently, the micro-engines 100 of the array 25 conclude this decision point determination by continuing the execution of the seed fill instruction in identical manners as appropriate for filling a pixel within the seed fill boundaries. 
     The utilization of the same MO control signals and AND gate 150 both for synchronization of data dependent instructions and the sharing of decision point data condition information is particularly achievable in the present invention due to the mutual exclusivity of instructions performing data dependent operations and those requiring the sharing of decision point interim result information. However, where such complete mutual exclusivity does not exist, each multiple parallel coprocessor of the array 25 may be readily implemented with respective sets of match-out and match-in control lines to allow instruction execution synchronization and the sharing of decision point information independently for the execution of any instruction. That is, in accordance with the present invention, the synchronization of instruction execution is readily extended to permit synchronization of the respective micro-engines 100 within the execution of an instruction. Thus, at any decision point, the micro-engines 100 are first synchronized to a common point in the execution of the current instruction. Then the respective decision point data conditions are combined by an external AND gate and shared among the coprocessors of the array 25. Execution of the data dependent instruction by each micro-engine 100 then proceeds to the next decision point or to completion in a manner consistent with the array wide consensus data condition. 
     Another aspect of the present invention regarding operation as a single instruction multiple data machine is an ability to appropriately deal with contention for access to the individual resources attached to the respective multiple parallel coprocessors 26, 28. As discussed above with regard to FIG. 2, a preferred embodiment of the present invention implements an arbitration control circuit 108 to resolve access contention directed to the display memory 32 as may occur between the DRAM refresh 102, video refresh 104 and micro-engine 100 blocks. However, access contention for each of the display memories 32, 34, 36 associated with the respective multiple parallel coprocessors of the array 25 must be handled in a like manner by each of the multiple parallel coprocessors 26, 28, 30, if operation is a single instruction multiple data machine is to be obtained. Otherwise, processing efficiency would significantly degrade as various portions of the array 25 simply wait for the completion of non-instruction execution related processing to be completed by any of the multiple parallel coprocessors 26, 28, 30 as necessary to maintain concurrency of instruction execution. 
     Accordingly, the present invention implements priority request/grant synchronization among all of the multiple parallel coprocessors of the array 25. This is accomplished by determining, through arbitration, a particular pending priority request to be granted by each of the multiple parallel coprocessors of the array 25. In a preferred embodiment of the present invention, priority request/grant occurs during each machine cycle to determine the actual priority operation to be performed during the next machine cycle. A machine cycle, in this preferred embodiment, is composed of six consecutive clock cycles. This machine-cycle arbitration allows the execution of an instruction to be temporarily halted for the one or more, coprocessor machine cycles required for a video refresh, for example. As soon as the micro-engine again becomes the highest priority requestor, the execution of the current instruction is resumed. 
     Priority arbitration by the entire array 25 begins immediately with the first clock cycle of each coprocessor array machine cycle. Arbitration selection is effectively concluded whenever each of the multiple parallel coprocessors has provided its priority request signal (TO) on a respective priority request control line 140, 142, and generically for other coprocessors of the array 25, line 144. The priority request control signals are provided as the respective inputs to a multiple input AND gate 152. As soon as all of the multiple parallel coprocessors of the array 25 have issued their respective priority requests for arbitration, the AND gate 152 provides a composite priority task selected (TI) control signal to each of the multiple parallel coprocessors of the array 25 via the AND gate output line 146. Identification of the particular priority task requested is determined from the specific clock cycle that the priority request control signal is provided onto a priority request line. In turn, output of the composite priority task selected control signal during any one clock cycle of a machine cycle specifically identifies the priority task granted by consensus of the entire array 25. However, the assignment of a particular cycle with any one of the priority requests is essentially arbitrary. 
     In a preferred embodiment of the present invention, the first four identification clock cycles correspond to priority task requests in the order given in Table III with the highest priority video refresh task request and grant being associated with the first clock cycle of a machine cycle. 
     The operation of the priority task synchronization function of the present invention is illustrated by the timing diagram provided in FIG. 6. As shown, a first machine cycle begins at t 1  and a second begins at t 13 . At t 1 , a first multiple parallel coprocessor 26 issues a video refresh request by providing its TO 1  signal on its priority request line 140. A second multiple parallel coprocessor 28, however, has not yet determined a need to perform a video refresh. Instead, the second coprocessor 28 internally recognizes the need for a DRAM refresh and, accordingly, issues a priority task request at about t 3  corresponding to the beginning of the second clock cycle of the current machine cycle. While this circumstance is generally rare, the possibility of its occurrence is provided for in the present invention. Assuming that all other coprocessors of the array 25 are similarly issuing at least a DRAM refresh priority task request on their respective priority synchronization request lines, as generally indicated by the request line 144, the AND gate 152 provides its composite priority task selected signal on its output line 146 
     As before, each of the multiple parallel coprocessors of the array 25 sense the state of the priority task selected signal on control line 146 during the second half of each clock cycle following the issuance of their respective priority task request signals. Thus, the consensus arbitration result for the array 25 is actually sensed shortly after t 4 . Consequently, the next machine cycle operation to be performed by the entire array 25 is determined to be a DRAM refresh. The present arbitration machine cycle concludes with the priority task request signals TO 1 , TO 2  being withdrawn during the fifth clock cycle at about t 9 . 
     At about t 15 , priority arbitration begins for the next subsequent machine cycle while the coprocessors of the array 25 jointly perform the DRAM refresh operation. As indicated, the first multiple parallel coprocessor 26 reasserts is still pending priority task request for a video refresh. Also as shown, the second multiple parallel coprocessor similarly issues a request for the performance of a video refresh. Assuming that all other multiple parallel coprocessors of the array 25 are now also requesting video refreshes, the composite priority task selected control signal is provided shortly after t 13  and prior to the sensing thereof by each of the multiple parallel coprocessors of the array 25 during the second half of the first clock cycle. Consequently, a video refresh priority task is identified to all of the multiple parallel coprocessors of the array 25 as the consensus task to be performed in the next succeeding machine cycle 
     The present invention specifically provides for the effective inclusion of conventional coprocessors, such as the coprocessor 22&#39; shown in FIG. 3 or any logical equivalent, into the architecture of the multiple parallel coprocessor array 25. This is preferably accomplished by permitting a coprocessor 22&#39; to enter into the competition for consensus selection as a priority task to be performed. In a preferred embodiment of the present invention, each multiple parallel coprocessor 26, 28 allows for the receipt of an external request (XI) and the provision of an external request grant (XO) signals. The conventional coprocessor 22&#39; preferably provides a memory request control signal commonly to each of the external request inputs of the multiple parallel coprocessors of the array 25 via a external request control line 164. Based on the presence or absence of this external request signal, each multiple parallel coprocessor of the array 25 preferably internally arbitrates whether t provide its priority task request control signal during the third or any other appropriately corresponding clock cycle of an array arbitration machine cycle. 
     Consensus selection to grant an external request, as indicated by the provision of the composite priority task selected control signal during the third clock cycle, results in each of the multiple parallel coprocessors of the array 25 providing an external grant control signal on their respective external grant control lines 156, 158, 160. An AND gate 154, respectively receiving each of the external grant control signals, provides a composite external request acknowledge control signal on its composite external grant output line 162 to the conventional coprocessor 22&#39;. Additionally, each of the multiple parallel coprocessors of the array 25 preferably place their address and data bus outputs, as coupled to their respective display memory address and data busses 50, 52, in a high impedance state. The conventional coprocessor 22&#39; is thereby free to place its desired addresses and data onto the display memory address and data busses 50, 52 via the inter-connecting address and data busses 76, 84, 80. Thus, the conventional coprocessor 22&#39; has full access to the display memories otherwise associated with the multiple parallel coprocessors of the array 25. 
     Preferably, the conventional coprocessor 22&#39; maintains its memory request control signal on the external request control line 164 of the array 25 for whatever length of time access to the display memory of the array 25 is required. Referring now to FIG. 7, a sequence of consensus arbitrated priority tasks are shown as they occur during the operation of the coprocessor array 25 in accordance with the present invention. During a first machine cycle (M1), a consensus DRAM refresh request is granted priority for the next machine cycle. Thus, during machine cycle M2, a DRAM refresh operation is performed by each coprocessor of the array 25. 
     The only arbitration priority request during M2 is for a micro-engine access of the display memory. Since the micro-engine is the lowest priority task and in view of the first-in, first-out buffering of instructions, a micro-engine request is essentially always pending. Consequently, a micro-engine operation occurs during machine cycle M3. 
     As indicated in FIG. 7, a video refresh request occurs internally in at least one, but not all, of the coprocessors of the array 25 as described above in reference to FIG. 6. The consensus result of arbitration during machine cycle M3 is, therefore, the grant of an external request, since all of the coprocessors appear to have an external request pending. Access to the display memories of the array 25 by the external conventional coprocessor 22&#39; occurs during machine cycle M4. Since multiple machine cycles are required by the conventional coprocessor 22&#39;, the external request is continuously submitted for arbitration. However, during M4 where all of the coprocessors of the array 25 issue a video refresh request, the array 25 recognizes the video refresh request as the consensus priority task to be performed during M5. Consequently, the array 25 withdraws the external request grant control signal and the conventional coprocessor 22&#39; is forced to give up access to the display memory. That is, the address, data and control outputs of the conventional coprocessor 22&#39; are placed in a high impedance state and the display memory is effectively returned to the array 25 for the performance of a video refresh during M5. 
     Arbitration during both M5 and M6 again results in the consensus grant of the still pending external request. Consequently, the composite external grant control signal is provided and the conventional coprocessor 22&#39; is again allowed to obtain access to the display memory of the array 25. External operations on the display memory occur during both M6 and M7. During M7, however, the external request is no longer pending. Consequently, the micro-engine request becomes the consensus priority task with its corresponding operation being performed during M8. 
     Lastly, highly parallel, synchronous operation of the present invention is extended to allow for the matching of the consensus internal control functions of the array 25 to an external synchronization clock source. That is, in a preferred embodiment of the present invention, the specific timing of video control features are externally controllable by the application of vertical and horizontal reset control signals on external timing control lines 128, 130, as shown in FIG. 2. These external timing signals are respectively accepted by a video timing block within each coprocessor of the array 25, as shown in FIG. 3. The effect of these external reset control signals is to override the self-generated timing of the video refresh block 104. Thus, the start of both horizontal and vertical video refreshes occur synchronously with whatever device, external to the array 25, is the source of the external timing signals. 
     Thus, an extremely flexible multiple coprocessor computer architecture that specifically provides for both the independent and highly parallel operation of an array of coprocessors, as appropriate for optimal operation as a single instruction, multiple data machine, yet that requires little if any additional initialization or managerial support by any associated host processor has been described. 
     Naturally, many modifications and variations of the present invention are possible in light of the above teachings. For example, the AND gates could be completely replaced through the use of open collector type output gates for providing the match-out and similar signals. Also, the instruction functionallity of the coprocessors could be realized to perform numberical computations on data stored in the respective memory planes. An alternate instruction functionallity could be to perform virtual-to-real data address conversions in support of a multiply partitioned data area, mass storage device. Accordingly, it is to be understood that, within the scope of the appended claims, the present invention may be practiced otherwise than is specifically described above.