Abstract:
The collector resistance of a bipolar junction transistor that is formed in a CMOS process is substantially reduced by forming a heavily-doped collector extension region that extends from a heavily-doped collector contact region down to a deep well of the same conductivity type to a point that lies close to the base of the transistor.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a bipolar junction transistor and, more particularly, to a bipolar junction transistor with a low collector resistance, and a method of forming the bipolar junction transistor in a CMOS process flow. 
         [0003]    2. Description of the Related Art 
         [0004]    A complementary metal-oxide semiconductor (CMOS) circuit is a circuit that utilizes both n-channel metal-oxide semiconductor (NMOS) and p-channel MOS (PMOS) transistors. One simple CMOS circuit is an inverter.  FIG. 1  shows a cross-sectional view that illustrates an example of a prior-art CMOS inverter structure  100 . 
         [0005]    As shown in the  FIG. 1  example, CMOS inverter structure  100  includes a p− semiconductor material  110 , such as single-crystal silicon, and a trench isolation region  112  that is formed in p− semiconductor material  110 . In addition, CMOS inverter structure  100  includes a PMOS transistor  114  and an NMOS transistor  116 . 
         [0006]    As further shown in  FIG. 1 , PMOS transistor  114  includes an n− well  120  that is formed in p− semiconductor material  110 , spaced-apart p+ source and drain regions  122  and  124  that are formed in n− well  120 , and a channel region  126  that lies between the source and drain regions  122  and  124 . PMOS transistor  114  also includes a gate oxide region  128 , and a gate  130  that sits on gate oxide region  128  over channel region  126 . 
         [0007]    NMOS transistor  116 , in turn, includes a p− well  132  that is formed in p− semiconductor material  110 , spaced-apart n+ source and drain regions  134  and  136  that are formed in p− well  132 , and a channel region  138  that lies between the source and drain regions  134  and  136 . NMOS transistor  116  also includes a gate oxide region  140 , and a gate  142  that sits on gate oxide region  140  over channel region  138 . (P− well  132  is optional, but commonly used to control the threshold voltage of NMOS transistor  116 .) 
         [0008]    Although not shown in the  FIG. 1  example, the gates  130  and  142  of the PMOS and NMOS transistors  114  and  116 , respectively, are electrically connected together, the drains  124  and  136  of the PMOS and NMOS transistors  114  and  116 , respectively, are electrically connected together, the source  122  of PMOS transistor  114  is electrically connected to a power supply line, and the source  134  of NMOS transistor  116  is electrically connected to a ground line. 
         [0009]      FIG. 2  shows a cross-sectional view that illustrates another example of a prior-art CMOS inverter structure  200 . CMOS inverter structure  200  is similar to CMOS inverter structure  100  and, as a result, utilizes the same reference numerals to designate the elements which are common to both structures. 
         [0010]    As shown in the  FIG. 2  example, inverter structure  200  differs from inverter structure  100  in that the NMOS transistor  116  of inverter structure  200  also includes a deep n− well  210  that lies between p− semiconductor material  110  and p− well  132 . In operation, deep n− well  210  allows p− well  132  to be biased differently than p− substrate  110 . 
         [0011]    A BiCMOS circuit is a circuit that includes both CMOS transistors and bipolar junction transistors.  FIG. 3  shows a cross-sectional view that illustrates an example of a prior-art BiCMOS structure  300 . BiCMOS structure  300  is similar to CMOS inverter structure  200  and, as a result, utilizes the same reference numerals to designate the elements which are common to both structures. 
         [0012]    As shown in the  FIG. 3  example, BiCMOS structure  300  includes inverter structure  200 , an npn bipolar transistor  310 , and a pnp bipolar transistor  312 . NPN transistor  310  includes a deep n− well  314  that is formed in semiconductor material  110 , and a p− well  316  that is formed in semiconductor material  110  to touch and lie above deep n− well  314 . 
         [0013]    As further shown in  FIG. 3 , NPN transistor  310  also includes a p+ region  320  and an n+ region  322  that are spaced-apart and formed in p− well  316 . NPN transistor  310  further includes an n− well  324  that is formed in semiconductor material  110  to touch and lie above deep n− well  314 , and an n+ region  326  that is formed in n− well  324 . In operation, deep n− well  314 , n− well  324 , and n+ region  326  function as the collector, p− well  316  functions as the base, p+ region  320  functions as the base contact, and n+ region  322  functions as the emitter. 
         [0014]    PNP transistor  312 , in turn, includes an n− well  330  that is formed in semiconductor material  110 , along with an n+ region  332  and a p+ region  334  that are spaced apart and formed in n− well  330 . PNP transistor  312  further includes a p− well  336  that is formed in semiconductor material  110 , and a p+ region  338  that is formed in p− well  336 . In operation, semiconductor material  110 , p− well  336 , and p+ region  338  function as the collector, n− well  330  functions as the base, n+ region  332  functions as the base contact, and p+ region  334  functions as the emitter. 
         [0015]    One of the advantages of npn and pnp transistors  310  and  312  is that transistors  310  and  312  can be formed utilizing the same process steps as are used to form PMOS and NMOS transistors  114  and  116 . Thus, transistors  310  and  312  can be incorporated into a CMOS process flow without any additional masks. 
         [0016]    However, one of the disadvantages of npn and pnp transistors  310  and  312  is that since the conventional buried layer is missing, the collector resistance of npn and pnp transistors  310  and  312  is undesirably high. Thus, there is a need for a method of forming npn and pnp transistors in a CMOS process flow that reduces the collector resistance. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIG. 1  is a cross-sectional view illustrating an example of a prior-art CMOS inverter structure  100 . 
           [0018]      FIG. 2  is a cross-sectional view illustrating another example of a prior-art CMOS inverter structure  200 . 
           [0019]      FIG. 3  is a cross-sectional view illustrating an example of a prior-art BiCMOS structure  300 . 
           [0020]      FIG. 4  is a cross-sectional view illustrating an example of a BiCMOS structure  400  in accordance with the present invention. 
           [0021]      FIGS. 5A-10A  and  5 B- 10 B are views illustrating an example of a method of forming a BiCMOS structure in accordance with the present invention.  FIGS. 5A-10A  are plan views.  FIGS. 5B-10B  are cross-sectional views taken along lines  5 B- 5 B to  10 B- 10 B shown in  FIGS. 5A-10A , respectively. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0022]      FIG. 4  shows a cross-sectional view that illustrates an example of a BiCMOS structure  400  in accordance with the present invention. As described in greater detail below, BiCMOS structure  400  significantly reduces the collector resistance of the bipolar junction transistors by forming a heavily-doped region that extends along a side wall of the trench isolation region. 
         [0023]    As shown in  FIG. 4 , BiCMOS structure  400  is similar to BiCMOS structure  300  and, as a result, utilizes the same reference numerals to designate the elements which are common to both structures. BiCMOS structure  400  differs from BiCMOS structure  300  in that BiCMOS structure  400  utilizes an npn transistor  410  and a pnp transistor  412  in lieu of npn transistor  310  and pnp transistor  312 , respectively. 
         [0024]    NPN transistor  410 , in turn, is similar to npn transistor  310  and, as a result, utilizes the same reference numerals to designate the structures which are common to both transistors. As further shown in  FIG. 4 , npn transistor  410  differs from npn transistor  310  in that npn transistor  410  further includes an n+ collector extension region  414  that touches trench isolation region  112 , deep n− well  314 , and n+ region  326 . In addition, n− well  324  may optionally be omitted. In the present example, no n-type region lies between any deep n− well (e.g.,  210  and  314 ) and a region of a bottom side  110 B of semiconductor material  110  that lies directly below. 
         [0025]    PNP transistor  412  is similar to pnp transistor  312  and, as a result, utilizes the same reference numerals to designate the structures which are common to both transistors. As further shown in  FIG. 4 , pnp transistor  412  differs from pnp transistor  312  in that pnp transistor  412  further includes a p+ collector extension region  416  that touches semiconductor material  110 , trench isolation region  112 , and p+ region  338 . In addition, p− well  336  may optionally be omitted. In the present example, no p-type region with a dopant concentration greater than a dopant concentration of p− semiconductor material  110  lies between p+ collector extension region  416  and a region of bottom side  110 B of semiconductor material  110  that lies directly below. 
         [0026]    PMOS transistor  114 , NMOS transistor  116 , npn transistor  410 , and pnp transistor  412  operate in a conventional fashion. NPN transistor  410  and pnp transistor  412 , however, have significantly lower collector resistances due to the presence of n+ collector extension region  414  and p+ collector extension region  416 , respectively. 
         [0027]      FIGS. 5A-10A  and  5 B- 10 B show views that illustrate an example of a method of forming a BiCMOS structure in accordance with the present invention.  FIGS. 5A-10A  show a series of plan views, while  FIGS. 5B-10B  show a series of cross-sectional views taken along lines  5 B- 5 B to  10 B- 10 B of  FIGS. 5A-10A . 
         [0028]    As shown in  FIGS. 5A-5B , the method, which utilizes a conventionally-formed p− semiconductor material  510 , such as single-crystal silicon, begins by forming a trench isolation region in p− semiconductor material  510 . Conventionally, the process to form a trench isolation region begins with the formation and patterning of a mask  512  on the top surface of p− semiconductor material  510 . Mask  512  can be formed from, for example, silicon nitride. Following this, the exposed regions of semiconductor material  510  are then etched to form a trench  514 . 
         [0029]    In accordance with the present invention, as shown in  FIGS. 6A-6B , after trench  514  has been formed, a mask  516  is formed and patterned on the top surface of mask  512 . Following this, an n-type dopant, such as arsenic, is implanted into p− semiconductor material  510  at an angle of, for example, 30° to form a heavily-doped (n+) collector extension region  520 . Due to the angled implant and masks  512  and  516 , n+ collector extension region  520  is only formed along one sidewall and a portion of the bottom surface of an exposed trench  514 . Mask  516  is then removed. 
         [0030]    As shown in  FIGS. 7A-7B , once mask  516  has been removed, a mask  522  is formed and patterned on the top surface of mask  512 . Following this, a p-type dopant, such as boron, is implanted into p− semiconductor material  510  at an angle of, for example, 30° to form a heavily-doped (p+) collector extension region  524 . Due to the angled implant and masks  512  and  522 , p+ collector extension region  524  is only formed along one sidewall and a portion of the bottom surface of an exposed trench  514 . Mask  522  is then removed. 
         [0031]    As shown in  FIGS. 8A-8B , once mask  522  has been removed, conventional steps are again followed to form a trench isolation region  526  in trench  514 . The conventional steps form a non-conductive material in trench  514 , remove the non-conductive material from the top surface of p− semiconductor material  510 , and remove mask  512  from the top surface of p− semiconductor material  510 . 
         [0032]    Next, as shown in  FIGS. 9A-9B , once trench isolation region  526  has been formed, a number of deep n− wells  530 , including deep n− well  530 - 1  and  530 - 2 , are formed in p− semiconductor material  510  in a conventional manner. For example, a mask  532  can be formed and patterned on the top surface of semiconductor material  510 . Following this, the exposed regions of semiconductor material  510  are implanted with an n-type dopant to form the deep n− wells  530 . Mask  532  is then removed. In the present example, no n-type region lies between any deep n− well  530  and a region of a bottom side  510 B of semiconductor material  510 . 
         [0033]    Once mask  532  has been removed, as shown in  FIGS. 10A-10B , a number of n− wells  534 , including n− well  534 - 1 , n− well  534 - 2 , and n− well  534 - 3 , and a number of p− wells  536 , including p− well  536 - 1 , p− well  536 - 2 , and p− well  536 - 3  are formed in p− semiconductor material  510  in a conventional manner. For example, the wells can be formed by masking and then implanting semiconductor material  510 . (N− well  534 - 3  and p− well  536 - 3  are optional.) 
         [0034]    Following this, a layer of gate oxide is formed on the top surface of semiconductor material  510 , followed by the conventional formation of a number of MOS transistor gates. After this, a number of shallow p+ regions and n+ regions are formed in a conventional manner. The regions include spaced-apart p+ source and drain regions that are formed in n− well  534 - 1  to form a PMOS transistor, like PMOS transistor  114 . The regions also include spaced-apart n+ source and drain regions that are formed in p− well  536 - 1  to form an NMOS transistor, like NMOS transistor  116 . 
         [0035]    In addition, the regions include an n+ collector that is formed in n− well  534 - 3  (or p− semiconductor material  510  if n− well  534 - 3  has been omitted) to touch n+ collector extension region  520 , like n+ collector  326 , a p+ contact that is formed in p− well  536 - 2 , like p+ contact  320 , and an n+ emitter that is formed in p− well  536 - 2 , like n+ emitter  322 , which together form an npn transistor, like npn transistor  410 . 
         [0036]    Further, the regions include a p+collector that is formed in p− well  536 - 3  (or p− semiconductor material  510  if p− well  536 - 3  has been omitted), to touch p+ collector extension region  524 , like p+ collector  338 , an n+ contact that is formed in n− well  534 - 2 , like n+ contact  332 , and a p+ emitter that is formed in n− well  534 - 2 , like p+ emitter  334 , which together form a pnp transistor, like pnp transistor  412 . 
         [0037]    Thus, a method has been described for forming a bipolar transistor with a low collector resistance in a CMOS process flow that only requires two additional masks (one for the n+ collector extension implant and one for the p+ collector extension implant). 
         [0038]    It should be understood that the above descriptions are examples of the present invention, and that various alternatives of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.