Abstract:
A method of improving voltage detection accuracy and precision by employing a switchable resistor epi bias design, which consists of switches to control connection of resistor epi bias. By constantly maintaining the resistor epi bias to its own resistor terminal bias via switches, higher accuracy detection than conventional resistor bias method can be achieved.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates to a voltage detection circuit that detects an input voltage in first and second periods to average by using a switch circuit and a sample and hold circuit. 
         [0002]    An example of an application of such a voltage detection circuit is for purposes of over-current detection. Referring to  FIG. 1C , for an IC being supplied from a DC source VDC, the supply current is made to pass through resistor Rsense. The voltage detection circuit measures the potential across the resistor Rsense via input terminals TI 1  and TI 2 . The outputs of the voltage detection circuit, TO 0  and TO 1 , are next sent to a sample and hold circuit where it is determined if over-current has occurred. If over-current has occurred, the sample and hold circuit will output a signal to open the switch S 1 , hence effectively disconnecting the DC source VDC to the IC. 
         [0003]    As disclosed in U.S. Publication 2006/0113969, an example of such a voltage detection circuit is described. In the switch circuit, with reference to  FIG. 1A , the resistor connection between the input voltage and the ground is reversed at different timing periods in order to implement offset element cancellation at the sampling circuit stage. In this example, during the first period, signal ‘a’ will close switches  01 A,  02 A,  03 A and  04 A simultaneously, and signal ‘b’ opens  01 B,  02 B,  03 B and  04 B simultaneously at the same time. Similarly, in the second period, signal ‘a’ will close switches  01 B,  02 B,  03 B and  04 B, and signal ‘b’ opens switches  01 A,  02 A,  03 A and  04 A simultaneously at the same time. First and second periods do not overlap with each other. A timing chart is as shown in  FIG. 1B  to illustrate the first and second periods&#39; timing. During each period, the input voltages are halved by the resistor ratio to prevent any undesirable limitation due to insufficient dynamic range. By adding the output voltage difference of the switch circuit in the first period to the output voltage difference in the second period, which had its resistor connection reversed, offsets in terms of the relative error of the resistors in the switch circuit can be mutually cancelled. 
         [0004]    However, in implementing the present invention using diffusion-type resistors, the method of reversing the resistor connection cannot be done simply. The first problem that needs to be taken into consideration is the biasing of the wells or isolation pockets containing the diffusion-type resistors, so as to prevent the occurrence of any parasitic diodes. The second problem that needs to be taken into consideration is that with non-ideal switches, it will be even more difficult to achieve high accuracy capability considering the addition of more switches due to the variation in the on-resistance of the switches under the influence of different conditions. 
         [0005]    The present invention is intended to solve such problems, and it is an object of the present invention to provide switching means to implement offset element cancellation at the sampling circuit stage, as well as ensuring that no parasitic diodes result during that cancellation process. 
       SUMMARY OF THE INVENTION 
       [0006]    The purpose of this invention is to provide a method to solve the above problem so that high-accuracy voltage detection can be achieved, with the capability to allow offset cancellation in terms of relative error in its resistor divider network. 
         [0007]    According to this invention, two switches are incorporated at the terminal of the well or isolation pocket containing the diffusion-type resistor to establish a connection to each side of the resistor&#39;s terminal. The switches are controlled sequentially such that the terminal of the well or isolation pocket is only connected to the side of the resistor terminal with higher voltage at any one time, while corresponding to the switching of the resistor divider network when it is reversed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1A  is a circuit diagram of a switching voltage divider circuit based on prior art U.S. Publication 2006/0113969. 
           [0009]      FIG. 1B  is a Timing Chart showing signals ‘a’ and ‘b’ during first and second periods based on prior art of U.S. Publication 2006/0113969. 
           [0010]      FIG. 1C  is an exemplary system application using a voltage detection circuit. 
           [0011]      FIG. 1D  is an exemplary composition of Voltage Detection Circuit comprising a Digital Control Signal Block Circuit and Switching Voltage Divider Circuit. 
           [0012]      FIG. 1E  is a drawing illustrating an exemplary composition of Digital Control Signal Block Circuit and Switching Voltage Divider Circuit in a single IC. 
           [0013]      FIG. 2A  is a circuit diagram of a switching voltage divider circuit with switching resistor epi connection configuration. 
           [0014]      FIG. 2B  is a cross-sectional view of an exemplary diffusion-type resistor based on the present invention (case of a p-type diffusion contained in an n-type epi layer). 
           [0015]      FIG. 2C  is a cross-sectional view of another exemplary diffusion-type resistor based on the present invention (case of an n-type diffusion contained in a p-type epi layer). 
           [0016]      FIG. 2D  is a cross-sectional view of another exemplary diffusion-type resistor based on the present invention (case of a p-well resistor). 
           [0017]      FIG. 2E  is a cross-sectional view of another exemplary diffusion-type resistor based on the present invention (case of an n-well resistor). 
           [0018]      FIG. 2F  is a typical transmission gate. 
           [0019]      FIG. 3  is the control signal waveform for the switch devices in the switching voltage divider circuit. 
       
    
    
       [0020]    It will be recognized that some or all of the Figures are schematic representations for purposes of illustration and do not necessarily depict the actual relative sizes or locations of the elements shown. 
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0021]    Referring to  FIG. 1D , a first embodiment of the present invention has a voltage detection circuit  1000  which comprises a switching voltage divider circuit  1001  and a digital control signal block  1002 . Control signals to the switching voltage divider circuit  1001  from digital control signal block  1002  are conveyed via electrical connection  1003 . For this case, the switching voltage divider circuit  1001  and the digital control signal block  1002  make up a system. The voltage detection circuit  1000  is employed in the voltage detection circuit shown in  FIG. 1C . The electrical connection  1003  is for second various ON and OFF signals to switches  11 B,  12 A,  13 B,  14 A,  15 A,  16 B,  17 A and  18 B, as well be explained later. 
         [0022]    Referring to  FIG. 1E , both the switching voltage divider circuit  1001  and digital control signal block  1002  may exist as 2 separate systems, but assembled within a single IC chip  1007 . Control signals to the switching voltage divider circuit  1001  from digital control signal block  1002  are conveyed via electrical connection  1003 . 
         [0023]    The switching voltage divider circuit  1001  is realized as shown in  FIG. 2A . 
         [0024]    The resistors used in the present invention are of the diffusion-type resistors. There are several types of diffusion-type resistors. Examples are the base-diffused resistors, where the resistor is in the form of a p-type (or n-type) diffusion contained in an n-type (or p-type) epitaxial (herein also referred to as epi) layer; p-well resistors, where the resistor is in the form of a p-well contained in an n-well further contained in a p-type epi layer or p-type substrate; n-well resistors, where the resistor is in the form of an n-well contained in a p-type epi layer or p-well. 
         [0025]    For the following description, base-diffused resistors are used. Specifically, the case of a p-type diffusion contained in an n-type epi layer is described. 
         [0026]    As shown in  FIG. 2A , the switching voltage divider circuit  1001  has two input terminals VIN 1  and VIN 2 , and a resistor divider network at each side of the input terminals, a resistor divider network  1  for input voltage VIN 1  and a resistor divider network  2  for input voltage VIN 2 , to half the input voltages respectively. 
         [0027]    The resistor divider network  1  has two same valued resistors  22  and  23  connected in series, four switch devices  11 B,  12 A,  13 B and  14 A which reverses the resistor divider network connection between the input terminal VIN 1 /VIN 2  and ground at different timing period, and another four switch devices  15 A,  16 B,  17 A and  18 B which alternates the connection of the resistor N-well contact to one of the resistor contacts with the higher voltage at any particular point in time. A more detailed explanation of the contacts will be described later. 
         [0028]    The resistor divider network  2  has two same valued resistors  24  and  25  connected in series. In the resistor divider network  2 , switch devices are connected in the same manner as the switch devices connected in the resistor divider network  1 . 
         [0029]    Examples of switch devices that may be used are transmissions gates (as shown in  FIG. 2F ) and simple transistor switches. As transmission gates are well known, its operation will not be described here. 
         [0030]    The switches in  FIG. 2A  are controlled in a sequential order with control signals shown in  FIG. 3 . 
         [0031]    These control signals may be generated within the system, such as described before with reference to  FIG. 1D ; or may be obtained outside of the system in another system block within the same IC chip, such as described before with reference to  FIG. 1E ; or may be obtained externally (that is, outside of the IC chip in which the current system is located) via digital logic controllers, microprocessors, microcontrollers, or other means where such control signals may be derived from. 
         [0032]    During Timing  1  as shown in  FIG. 3 , signal A is high and signal B is low, hence switches  12 A,  14 A,  15 A and  17 A are turned on while switches  11 B,  13 B,  16 B and  18 B are off. The operation is vice versa in Timing  2 . Thus, signal A is low and signal B is high, hence inversing the state of the switches respectively. The on period of the switches in Timing  1  and Timing  2  must not be allowed to overlap as it will cause the input voltages VIN 1 /VIN 2  to be shorted to GND. 
         [0033]    Switch devices  12 A and  14 A serve as a first switch assembly for connecting the input terminal VIN 1 , the first diffusion type resistor  22 , the second diffusion type resistor  23  and the ground terminal GND serially in said order. Switch devices  11 B and  13 B serve as a second switch assembly for connecting the ground terminal GND, the first diffusion type resistor  22 , the second diffusion type resistor  23  and the input terminal VIN 1  serially in said order. 
         [0034]      FIG. 2B  shows a cross-sectional view of an exemplary combination of the diffused resistor and switches as used in realizing the above mentioned resistor divider network. For the purpose of this description, a base-diffused resistor is used as an example. Specifically, a p-type diffusion contained in an n-type epi layer is used. 
         [0035]    In particular, resistor  22  and switches  15 A and  16 B are described in this example. The n-type epi layer contact  200  is always connected to a potential that is high enough to prevent the conduction of the parasitic diode. Based on the present invention, n-type epi layer contact  200  is always connected to the higher of the two resistors&#39; contact terminals&#39; potentials, namely resistor contacts  201  and  202 . The connections to either of the two contact potentials are made via switches  15 A and  16 B. 
         [0036]    For example, when switch  15 A is turned on, switches  12 A and  14 A are also turned on to provide high voltage from terminal VIN 1  to terminal  101 , so that in  FIG. 2B  a path  101 ,  15 A,  200 , n+, p+,  202 ,  102  is established to realize the reverse bias connection in diffusion type resistor  22 . Similarly, when switch  16 B is turned on, switch  11 B and  13 B are also turned on to provide high voltage from terminal VIN 1  to terminal  102  via resistor  23 , so that in  FIG. 2B  a path  102 ,  16 B,  200 , n+, p+,  201 ,  101  is established to realize the reverse bias connection in diffusion type resistor  22 . Thus, switches  15 A and  16 B serve as a first control switch arrangement for connecting the first diffusion type resistor  22  in a reverse bias direction. Similarly, switches  17 A and  18 B serve as a second control switch arrangement for connecting the second diffusion type resistor  23  in a reverse bias direction. Thus, a voltage produced between the output terminals VOUT 1  and VOUT 2  of the first and second resistor divider networks  1  and  2 , respectively, is accurately relative to a voltage applied between the input terminals VIN 1  and VIN 2  of the first and second resistor divider networks  1  and  2 , respectively. 
         [0037]    The switch  15 A of the first control switch arrangement has its one end connected to epi contact segment  200  provided on resistor  22 , and its other end connected to diffusion contact segment  201  provided on resistor  22 . Similarly, switch  16 B of the first control switch arrangement has its one end connected to epi contact segment  200  provided on resistor  22 , and its other end connected to diffusion contact segment  202  provided on resistor  22 . Diffusion contact segments  201  and  202  are separated, but provided on the same p-type diffusion area. 
         [0038]    These switches are controlled via control signals. These may be generated within the system, as described before with reference to  FIG. 1D ; or may be obtained outside of the system in another system block within the same IC chip, as described before with reference to  FIG. 1E ; or may be obtained externally (that is, outside of the IC chip in which the current system is located) via digital logic controllers, microprocessors, microcontrollers, or other means where such control signals may be derived from. 
         [0039]    The above mentioned exemplary resistor configuration is also applicable for a N-well type resistor in a P-well in an N-substrate. The only difference is that the switches will connect the P-well biasing to the lower of the two resistor contact terminals&#39; potentials. 
         [0040]    The above mentioned exemplary resistor configuration is also applicable for an n-type diffusion contained in a p-type epi layer, as shown in  FIG. 2C . The only difference is that, to bias the p-type epi layer, the switches will connect the p-type epi layer contact  2001  to the lower of the two resistor contact terminals&#39; potentials. 
         [0041]    The n-type epi layer contact  200  of the p-type diffusion contained in an n-type epi layer, and the p-type epi layer contact  2001  of the n-type diffusion contained in a p-type epi layer may be referred to in general as the ‘epi contact’. 
         [0042]    Similarly, the above mentioned exemplary resistor configuration is also applicable for a p-well resistor, as shown in  FIG. 2D . The only difference is that, to bias the n-well, the switches will connect the n-well contact  2002  to the higher of the two resistor contact terminals&#39; potentials. 
         [0043]    Also, the above mentioned exemplary resistor configuration is also applicable for an n-well resistor, as shown in  FIG. 2E . The only difference is that, to bias the p-well, the switches will connect the p-well contact  2003  to the lower of the two resistor contact terminals&#39; potentials. 
         [0044]    As described above, in general, besides the two contacts normally associated with a typical resistor, there is a third contact made to the diffusion immediately adjacent to the diffusion in which the resistors&#39; terminals are connected to. 
         [0045]    That is, for based diffused resistors, the third contact is the n-type epi layer contact  200  of the p-type diffusion contained in an n-type epi layer, and the p-type epi layer contact  2001  of the n-type diffusion contained in a p-type epi layer. 
         [0046]    Also, for a p-well resistor the third contact is the n-well contact  2002 . 
         [0047]    As for n-well resistor, the third contact is the p-well contact  2003 . 
         [0048]    As we are referring to diffusion-type resistors, all 3 contacts may be generally referred to as diffusion contacts. 
         [0049]    With reference to  FIG. 2A , the operation of the present invention shall now be described. Again, for the purpose of this description, a base-diffused resistor is used as an example. Specifically, a p-type diffusion contained in an n-type epi layer is used. 
         [0050]    In Timing  1  period, switches  11 B,  13 B,  16 B and  18 B are off as described earlier. At the same time, switch  12 A and  14 A will be closed to connect node  101  of resistor  22  to VIN 1  and node  103  of resistor  23  to GND respectively. Switch  15 A is also closed to connect the n-type epi layer contact  200  of resistor  22  to node  101  which is the side of resistor  22  that has a higher voltage compared to node  102 , during this period. Similarly switch  17 A is closed to connect the corresponding n-type epi layer contact of resistor  23  to node  102  which is the side of resistor  23  that has a higher voltage compared to node  103 . 
         [0051]    The same conditions are applied to resistor divider network  2  such that one end of the resistor divider network with resistor  24  is connected to VIN 2  and the other end of the resistor divider network with resistor  25  is connected to GND. Correspondingly, the corresponding n-type epi layer contact of each resistor in network  2  is connected to its own resistor terminal with higher voltage. 
         [0052]    During this period of Timing  1 , VOUT 1  terminal takes a voltage at node  102  of the resistor divider network  1  which is half the voltage of VIN 1  including the relative error of the resistors  22  and  23 , while VOUT 2  terminal outputs a voltage at node  102  of the resistor divider network  2  which is half of VIN 2  including the relative error of the resistors  24  and  25 . The difference between VOUT 1  and VOUT 2 , together with the respective relative errors, is stored by a sampling circuit in the following stage. 
         [0053]    Next in Timing  2  period, the resistor divider network connections are reversed, with switches  12 A,  14 A,  15 A and  17 A being opened. On the other hand, switches  13 B and  11 B are now closed to connect node  101  of resistor  22  to GND and node  103  of resistor  23  to VIN 1  respectively. Switch  16 B is also closed to connect the epi-terminal of resistor  22  to node  102  which is the side of resistor  22  that has a higher voltage compared to node  101 , during this period. Similarly switch  18 B is closed to connect the epi-terminal of resistor  23  to node  103  which is the side of resistor  23  that has a higher voltage compared to node  102 . 
         [0054]    The same conditions are applied to resistor divider network  2  such that one end of the resistor divider network with resistor  24  is now connected to GND and the other end of the resistor divider network with resistor  25  is connected to VIN 2 . The epi-terminal of each resistor in network  2  is also switched accordingly so that it is connected to its own resistor terminal with higher voltage. 
         [0055]    During this period of Timing  2  with the resistor divider network connections reversed, VOUT 1  terminal again takes a voltage at node  102  of the resistor divider network  1  which is half the voltage of VIN 1  including the relative error of resistors  22  and  23 , while VOUT 2  terminal outputs a voltage at node  102  of the resistor divider network  2  which is half of VIN 2  including the relative errors of resistors  24  and  25 . With that, the voltage difference between VOUT 1  and VOUT 2  in Timing  2  is now added to the voltage difference stored during Timing  1  by the sampling circuit. By summing the voltage difference between VOUT 1  and VOUT 2  in Timing  1  and the voltage difference in Timing  2 , the relative errors of the resistors  22 ,  23 ,  24  and  25  can be mutually cancelled as demonstrated in the following example: 
         [0056]    Let the resistance value of resistors  22 ,  23 ,  24  and  25  to be “R”, and the resistor  22  has a relative error “ΔR”, the voltage difference of the two output terminals during Timing  1 , ΔV( 1 ), is expressed as follows, 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           Δ 
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                            
                           
                             V 
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                               ( 
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                         = 
                         
                           
                             VOUT 
                              
                             
                                 
                             
                              
                             1 
                              
                             
                               ( 
                               1 
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                              
                             2 
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                               ( 
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                         = 
                         
                           
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                   ( 
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         [0000]    whereas in Timing  2 , the voltage difference of the two output terminals, ΔV( 2 ), is expressed as follows, 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
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         [0000]    And the sum of the output voltage difference at both Timing  1  and  2  is as follows. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           
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                         = 
                           
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         [0000]    As shown in equation (3), the resulting sum of the output voltage difference of the switch circuit at two different timing periods simply gives the actual voltage difference between the two input voltages VIN 1  and VIN 2  without the influence of the relative error in the resistors. The summing of the output voltage differences in Timings  1  and  2  can be achieved by using a sample-and-hold circuit which is able to retain the voltage difference in Timing  1 , and subsequently adds it to the next voltage difference during Timing  2 . 
         [0057]    Correspondingly, the description of the operation above applies for other diffusion-type resistors as well. 
         [0058]    For example and purpose of clarity, the following associations are described. 
         [0059]    For the case of an n-type diffusion contained in a p-type epi layer ( FIG. 2C ), nodes  1011  and  1021 , as well as contacts  2001 ,  2011  and  2021  correspond to nodes  101  and  102 , as well as contacts  200 ,  201  and  202  of the p-type diffusion contained in an n-type epi layer. 
         [0060]    For the case of a p-well resistor ( FIG. 2D ), nodes  1012  and  1022 , as well as contacts  2002 ,  2012  and  2022  correspond to nodes  101  and  102 , as well as contacts  200 ,  201  and  202  of the p-type diffusion contained in an n-type epi layer. 
         [0061]    For the case of an n-well resistor ( FIG. 2E ), nodes  1013  and  1023 , as well as contacts  2003 ,  2013  and  2023  correspond to nodes  101  and  102 , as well as contacts  200 ,  201  and  202  of the p-type diffusion contained in an n-type epi layer. 
         [0062]    Having described the above embodiment of the invention, various alternations, modifications or improvement could be made by those skilled in the art. Such alternations, modifications or improvement are intended to be within the spirit and scope of this invention. The above description is by ways of example only, and is not intended as limiting. The invention is only limited as defined in the following claims.