Abstract:
Disclosed is a contactor interconnect in an integrated circuit device test fixture comprises a plurality of contactor pins enabled to provide electrical contact with the contact points of an integrated circuit device, the contactor pins being mounted in the test fixture; and an electrical circuit coupled to two or more of the contactor pins of the test fixture, wherein the electrical circuit is isolated from other contactor pins of the plurality of contactor pins and wherein the electrical circuit is coupled to the two or more contactor pins by an electronically direct pathway.

Description:
FIELD OF THE INVENTION 
     The present application relates generally to integrated circuits, and in particular, to an integrated circuit testing apparatus and methods. 
     BACKGROUND OF THE INVENTION 
     Modern integrated circuit devices continue to shrink in size as they accelerate in speed. More and more functionality is demanded of less and less device “real estate” or available circuit space, whether on the printed circuit board of an electronic appliance or on the semiconductor die in which integrated circuits are formed. 
     One result of the shrinking of integrated circuits is the increasing density of the arrays of contacts that connect the circuit to the outside world. Typically formed of ball grid arrays (BGAs), a device&#39;s contacts can number in the thousands and be packed into an area of a few square centimeters. 
     In a typical integrated circuit package, a package substrate provides connection between the BGA and a solder bump array 
     Testing of a packaged integrated circuit is affected by this contact density. The production testing of packaged devices is done using automated handlers that load each of the devices into contactors on a test board, then sort them based on the results of testing. These contactors are designed to provide an interconnection for the path between the packaged device and the printed circuit board (PCB). The contactor path is both a mechanical and electrical element. The mechanical aspect of the contactor provides a certain amount of force to break through the oxide on the package ball as well as provides a means to form a connection given the planarity of the package balls. The electrical connection between the specific package balls or pins is designed to be extremely short and near the package pins. To make this possible, the path is isolated from the lower half of the contact element to minimize the electrical length. This improves the bandwidth and high speed performance of the signal paths, and could improve the lifetime of the contactor in production testing. There currently are no solutions that provide the mechanical travel of the contactor, with the electrical performance needed to test our increasing high speed I/Os. 
     SUMMARY OF THE INVENTION 
     Embodiments of the present invention provide a high-speed interconnect for testing integrated circuit assemblies. Disclosed embodiments enable the testing of integrated circuits in production testing using an internal path in the contactor or socket for connecting two or more package pins while maintaining the standard contact path for the rest of the device package pins. Additionally, electronic circuitry can be placed in a cavity under the interconnect to provide decoupling, or filtering, for high or low speed applications. Currently we use a socket only to provide a connection from the packaged device to the printed circuit board functioning as an interposer. By connecting a path from one package ball to another in the socket, we would shorten the electrical path and maximize the bandwidth for production testing. 
     Disclosed is a contactor interconnect that enables high-speed, short-path, testing of selected contact pins of an integrated circuit device. The contactor interconnect is included in a testing apparatus that includes a plurality of contactor pins that are enabled to provide electrical contact with the contact points of the integrated circuit device. The contactor pins are mounted in a test fixture with an electrical circuit coupled to two or more of the contactor pins by a pathway that is not electronically long and the electrical circuit is isolated from other contactor pins. 
     In one embodiment, the substrate is a packaging substrate that also enables carrying and handling the semiconductor wafer. This allows the substrate to stay attached to the mother die and results in a packaged integrated circuit assembly upon singulation. 
     These and other advantages of the present invention will be obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments, which are illustrated in the various drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention, and together with the description, serve to explain the principles of the invention. In the drawings: 
         FIG. 1  illustrates a contact array in a test fixture with interconnected contact pads, in accordance with an embodiment of the present invention; 
         FIG. 2  illustrates the contact of interconnected contactor pins of a test fixture on solder balls of an integrated circuit device, in accordance with an embodiment of the present invention. 
         FIG. 3  illustrates an alternative interconnect between a pair of contactor pins, in accordance with an embodiment of the present invention; 
         FIGS. 4A-4C  illustrate a test fixture with a pair of interconnected contactor pins in a carrier, in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous specific details are set forth to provide a more thorough description of the specific embodiments of the invention. It should be apparent, however, to one skilled in the art, that the invention may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the invention. For ease of illustration, the same number labels are used in different diagrams to refer to the same items; however, in alternative embodiments the items may be different. 
       FIG. 1  illustrates a contact array in a test fixture with interconnected contact pads, in accordance with an embodiment of the present invention. In the embodiment illustrated, test fixture  100  is a plain rectangular shaped platform with a rectangular array of contact pads  110 . Two pairs of contact pads  110  are interconnected  120  at the contacting surface of the test fixture. 
     It is noted here that the test fixture  100  is shown here as a generic rectangle with an array of plain contact points. This generic illustration comports with a mathematical model of a real-world test fixture. However, an actual test fixture is somewhat more complex. For example, turn to  FIG. 2 . 
       FIG. 2  illustrates the contact of interconnected contactor pins of a test fixture on solder balls of an integrated circuit device, in accordance with an embodiment of the present invention. In this embodiment, test fixture  210  features contact pins  214 , which are enabled to make a reliable electrical contact with solder balls  202  of integrated circuit device  204 . Contactor pins  214 A and  214 B are, in this embodiment, of a type often called “pogo pins.” Pogo pins have a contact head  208 A and  208 B that is configured to break through any resistive oxide that forms on a solder ball and the contact head  208  is mounted on a spring in the contact pin body such that solder balls of different heights can all be made to effect electrical conductivity. While contact heads  208 A and  208 B are, in this illustration, configured as multi-pointed heads, other configurations are also employed. Contactor pins  214 A and B also have a means  216  of connection to test circuitry associated with test fixture  210 . 
     Solder balls  202  are illustrated here as being mounted on contact pads  206  of integrated circuit device  204 . Contact pads  206  can be, in some implementations, formed on the under side of a package substrate. Another set of contact pads, formed to match the contact pads and solder bumps of the integrated circuit chip, are formed in the opposite or upper surface of the substrate and the integrated circuit chip is mounted to the substrate by means of the solder bumps. Integrated circuit device  204  can comprise an integrated circuit chip mounted to a package substrate and, in another embodiment, a stacked daughter chip mounted to the integrated circuit chip by solder bumps. The integrated circuit device assembly is typically encapsulated in a packaging material. 
     In the embodiment of the present invention shown in  FIG. 2 , contactor pin interconnect  212  is shown as a direct short between contactor pins  214 A and  214 B. In some test operations, a simple loop-back between I/O pins enables speedy, high frequency testing. A direct short, as shown at  212  in  FIG. 2 , is a very direct and expedient loop-back connection between pins  214 A and  214 B. 
     In another embodiment, illustrated in  FIG. 3 , interconnection is established by an interconnecting wire  312  between contactor pins represented by contactor springs  320 A and  320 B.  FIG. 3  illustrates this alternative interconnect between a pair of contactor pins, in accordance with an embodiment of the present invention. Here, test fixture  310  is shown with contactor pins  314  and contactor springs  320 A and  320 B. The contactor pins effect electrical contact with integrated circuit device  304  solder balls  302  and the contactor springs effect electrical contact with integrated circuit device  304  solder balls  322 A and  322 B. Interconnection  312  is shown connecting the back end of contactor springs  320 A and  320 B. In some test operations, providing a short distance in the electrical length between solder balls  322  A and  322 B is beneficial in the timing characteristics of the test. 
       FIGS. 4A-4C  illustrate a test fixture with a pair of interconnected contactor pins in a carrier, in accordance with an embodiment of the present invention. In  FIG. 4A , a test fixture  410  is shown with an array of contactor pins  414  which are enabled to make electrical contact with solder balls  402  on integrated circuit device  404  by means of contact heads. Two solder balls  422 A and  422 B, illustrated here to represent I/O contacts intended for test, are contacted by interconnection  412  mounted on a separate carrier  408 . Carrier  408  is mounted on springs  420  such that it is able to accommodate height differences in solder balls  402 , much like contactor pins  414 . The travel that allows this accommodation is represented in travel space  418 . 
       FIG. 4B  illustrates the closure of travel space  418 . By compressing the springs  420 , as well as springs in the pogo pins  414 , robust electrical contact with the solder balls  402  and  422  is assured. The height of travel shown in  FIG. 4B  is not drawn to any scale and is exaggerated for illustrative purposes. 
     It is noted here that in-process and post-process oxidation of solder bumps is ever-present. The materials used in solder bumps are typically resistant to excessive oxidation, but the small size of bumps makes even a very small amount of oxide significant. Oxides are typically highly resistive if not insulating materials. For this reason, the contact point of a contactor pin is typically a hardened point or an array of points as shown at the contact points of contactor pins  414 . The points are able to scratch through any oxide on the surface of solder balls  402  and assure electrical conductivity. 
     Another embodiment is illustrated in  FIG. 4C . Here, test fixture  410  is equipped with carrier  610  which is enabled to adjust to different height solder balls  602 A and  602 B. Carrier  610  is mounted on springs  420  which apply pressure to contact heads  609  on interconnect  608 . Also shown is test circuit  612 . 
     Electrical conductivity with solder balls  602 A and  602 B is assured by contact points  609  on interconnect  608 . In this embodiment, the different heights of solder balls  602 A and  602 B would make difficult the attainment of reliable electrical contact with interconnect  608  if the interconnect were not mounted to adaptable interconnect carrier  610 . Interconnect carrier  610  is enabled to adjust to different height solder balls for this reason. 
     The high speed contactor interconnect illustrated in these embodiments enables the connection of specific I/O contacts or pins in an integrated circuit, essentially an internal interconnect at the integrated circuit itself. By connecting the I/O pins together, certain testing, including loop-back testing is enabled. By providing this close-in connection in a test fixture, the testing of many test articles can be accomplished relatively rapidly. The interconnect can connect a pair of package pins or a plurality, all while maintaining a standard contact path for the remaining device package pins. The provision of components adjacent to the interconnect can provide decoupling, or filtering, for various applications. By providing a shorter electrical path between package pins, the bandwidth for production testing is increased. 
     A high speed contactor interconnect has been disclosed herein. It will be recognized by those of ordinary skill in the art that numerous alternative embodiments and equivalents will be seen to exist which incorporate the disclosed invention. As a result, this description of the invention is not to be limited by the foregoing embodiments, but only by the following claims.