Abstract:
An anti-reflective coating layer which is used to provide better control over the photolithographic process during the contact masking step is removed using high-temperature fluorine containing chemistry to reduce the amount of thickness variations that remain after the metal contact is filled in the contact hole and planarized by polishing. As a result, post-polish defect inspections are facilitated.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates generally to a method of forming metal contacts in a semiconductor device, and, more particularly, to a method of removing an anti-reflective coating layer using a high-temperature fluorinated chemistry to provide a semiconductor device having a more consistent planar surface at the conclusion of the metal contact forming step. 
     2. Description of the Related Art 
     Anti-reflective coatings have been used in the fabrication of small dimension integrated circuits (ICs) to provide better control over the photolithographic process. In particular, inorganic BARCs (bottom anti-reflective coatings) have been used during the contact hole masking step to reduce the reflections from the underlying topography substrate and thereby provide better control over the width of the photoresist mask openings which are used to form contact holes of a desired width. 
     FIGS. 1A-1D illustrate a conventional method of forming metal contacts for a semiconductor device in which an anti-reflective coating layer is used to reduce the reflections from the underlying topography substrate. The semiconductor device includes a substrate  10 , an active region  15  formed in the substrate  10 , an insulating layer  20 , which is typically a silicon dioxide (SiO 2 ) layer, disposed on top of the substrate  10 , a BARC layer  30  disposed on top of the insulating layer  20 , and a photoresist layer  40  in which mask openings  45  are formed by a conventional photolithographic process. 
     The semiconductor device illustrated in FIG. 1A is etched to form openings  50  through the BARC layer  30  and the insulating layer  20 . FIG. 1B illustrates the semiconductor device having the openings  50  and the photoresist layer  40  removed. On top of the semiconductor device illustrated in FIG. 1B, a metal layer  60 , e.g., tungsten (W), is deposited on its surface. The resulting structure is shown in FIG.  1 C. 
     Subsequently, the metal layer  60  is planarized by a conventional polishing process. The metal layer  60  is polished until the entire surface of the BARC layer  30  is exposed and the metal contacts  70  remain. The resulting structure is illustrated in FIG.  1 D. 
     In the conventional method of forming metal contacts, the BARC layer  30  that remains after the metal layer  60  is polished has thickness variations and surface inconsistencies  80  that make post-polish defect inspections extremely difficult. It is thus desirable to provide a semiconductor device having a more consistent planar surface at the conclusion of the metal contact forming step to improve the rate and the quality of post-polish defect inspections. 
     SUMMARY OF THE INVENTION 
     The invention provides a method of forming metal contacts in a semiconductor device in which an anti-reflective coating layer used to provide better control over the photolithographic process is removed by high-temperature fluorinated chemistry. The removing step may be carried out just after the metal layer for forming the metal contacts has been deposited and polished, or before the metal layer for forming the metal contacts is deposited and polished. The removal of the anti-reflective coating layer in this manner, reduces the amount of thickness variations on the planar surface of the semiconductor device and leads to an improved and less difficult post-polish defect inspection. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention is described in detail herein with reference to the drawings in which: 
     FIGS. 1A-1D illustrate the conventional steps of forming metal contacts in a semiconductor device; 
     FIGS. 2A-2E illustrate a method of forming metal contacts in a semiconductor device in accordance with a first embodiment of the invention; and 
     FIGS. 3A-3E illustrate a method of forming metal contacts in a semiconductor device in accordance with a second embodiment of the invention. 
    
    
     The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred exemplary embodiments of the invention, and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2A illustrates a semiconductor device having a silicon substrate  10 , an active region  15  formed in the substrate  10 , an insulating layer  20  (e.g., an SiO 2  layer, a thermal oxide layer, a plasma-enhanced chemical vapor deposition (PECVD) oxide layer, a high temperature furnace deposited oxide layer, or the like), formed on top of the substrate  10 , an inorganic BARC layer  30 , preferably a silicon oxynitride (SiON) layer, formed on top of the insulating layer  20 , and a photoresist layer  40  formed on top of the BARC layer  30 . Within the photoresist layer  40 , mask openings  45  have been formed by a conventional photolithographic process. 
     The semiconductor device illustrated in FIG. 2A is subjected to an etchant that removes the BARC layer  30  and the insulating layer  20  at a faster rate than the photoresist layer  40  and the semiconductor substrate  10 . This etching process is continued until the substrate  10  is exposed through the openings  50  that are formed through the BARC layer  30  and the insulating layer  20 . The photoresist layer  40  is then removed. The resulting structure is illustrated in FIG.  2 B. 
     Subsequently, a metal layer  60  is deposited on the surface of the semiconductor device. The metal layer  60  typically includes titanium (Ti), titanium nitride (TiN), and tungsten (W), where Ti is the lowermost layer and W is the uppermost layer, and fills the openings  50 . The resulting structure is shown in FIG.  2 C. The metal layer  60  is then polished until the entire surface of the BARC layer  30  is exposed and metal contacts  70  are formed. The polishing process is preferably a chemical-mechanical polish (CMP). 
     At the conclusion of the polishing step, in accordance with the first embodiment of the present invention, the semiconductor device of FIG. 2D is subjected to a high-temperature fluorine containing chemistry, for example, CF 4 , SF 6 , NF 3 , etc. The preferred temperature range is between 60° C. and 240° C. and the fluorine containing chemistry is typically in a gaseous form at these temperatures. At these temperatures, the fluorine chemistry etches the BARC layer  30  at a rate that is much higher than the insulating layer  20 , generally about 3-15 times higher, depending on the SiON composition and the insulating layer type. Such a high etch selectivity of the BARC layer  30  with respect to the insulating layer  20  permits good control of the removal of the BARC layer  30  and thereby limits any attack on the insulating layer  20  after the BARC layer  30  has been removed. The semiconductor device having the BARC layer  30  removed is illustrated in FIG.  2 E. 
     At the conclusion of the BARC layer removing step, an additional polishing step to planarize the upper surface of the semiconductor device illustrated in FIG. 2E may be necessary, because the metal contacts  70  may have etched at a different rate than the BARC layer  30  and consequently a bump or a depression may be formed by the metal contacts  70  along the upper surface of the semiconductor device at the conclusion of the BARC layer removal step. 
     Further, where the BARC layer comprises silicon oxynitride, there may be differing amounts of oxygen and nitrogen in its chemical composition, SiO x N y . For example, it is possible to increase the concentration of nitrogen or decrease the concentration of oxygen in the silicon oxynitride so as to increase its etch rate in the fluorine containing chemistry relative to the underlying insulating layer  20 . However, there is an upper limit to an increase of the nitrogen concentration (or decrease in the oxygen concentration) because the increase in the nitrogen concentration (or decrease in the oxygen concentration) increases the internal reflectivity of the BARC layer and thus decreases its level of performance as an anti-reflective coating. In a similar manner, the concentration of nitrogen in the silicon oxynitride layer may be decreased (or the concentration of oxygen increased) to improve its level of performance as an anti-reflective coating so long as its etch rate in the fluorine containing chemistry relative to that of the underlying insulating layer  20  is sufficiently high. 
     FIGS. 3A-3E illustrate the steps of forming metal contacts in a semiconductor device in accordance with the second embodiment of the invention. The semiconductor device illustrated in FIG. 3A is identical to the semiconductor device illustrated in FIG. 2A, and the steps of forming the openings  50  through the BARC layer  30  and the insulating layer  20 , as illustrated in FIG. 3B, are identical as illustrated and explained in connection with FIGS. 2A and 2B. 
     In this embodiment, however, after the openings  50  are formed, the BARC layer  30  is removed in a high temperature fluorine containing chemistry, for example, CF 4 , SF 6 , NF 3 , etc. The preferred temperature range is between 60° C. and 240° C. and the fluorine containing chemistry is typically in a gaseous form at these temperatures. At higher temperatures, a higher etch selectivity of the BARC layer  30  can be achieved with respect to the underlying insulating layer  20  and the exposed active region  15  of the substrate  10 , generally about 3-15 times higher, depending on the SiON composition and the insulating layer type. Even though the active region  15  of the substrate  10  is exposed to the fluorine containing chemistry, any attack on the exposed active region  15  is limited because of the high etch selectivity to the BARC layer  30  with respect to the underlying insulating layer  20  and the exposed active region  15 . 
     After the BARC layer removing step, a metal layer  60  is disposed on the surface of the semiconductor device illustrated in FIG.  3 C. The metal layer is preferably tungsten (W) and is illustrated in FIG.  3 D. Thereafter, the upper surface of the metal layer  60  is polished by CMP until an entire surface of the insulating layer  20  is exposed and metal contacts  70  are formed. 
     In the second embodiment, as in the first embodiment, it is possible to increase the concentration of nitrogen in the silicon oxynitride so as to increase its etch rate in the fluorine containing chemistry relative to the underlying insulating layer  20  and the active region  15  of the substrate  10 , without significantly increasing its reflectivity to harm its function as an anti-reflective coating. In a similar manner, the concentration of nitrogen in the silicon oxynitride layer may be decreased to improve its level of performance as an anti-reflective coating so long as its etch rate in the fluorine containing chemistry relative to those of the underlying insulating layer  20  and the active region  15  of the substrate  10  are sufficiently high. 
     All particular embodiments according to the invention have been illustrated and described above, it will be clear that the invention can take a variety of forms in embodiments within the scope of the appended claims.