Abstract:
A modified UTOPIA interface for inter-board applications is provided where the address timing generated by a polling master is extended to be two clock cycles long with no NULL address being driven onto the address line in between addresses. Output and input circuitry is provided in conjunction with the polling master and user ATM boards to accommodate hot insertion and to help drive the circuit. The master preferably includes an outgoing address latch and address latch control associated with the address bus, and a register associated with the enable signal. The master also includes a hot insertion buffer on the incoming cell available signal. The user device(s) include hot insertion buffers on the address bus, the data bus, and the enable signal. A remapping function is also preferably provided in associated with the user board which permits the user board to map received addresses into desired addresses. With the extended address timing and the provided circuitry, a workable inter-board hot-insertable UTOPIA interface is established.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to telecommunications. More particularly, the present invention relates to the passing of high speed Asynchronous Transfer Mode (ATM) data over a standardized Universal Test and Operations Physical Interface for ATM (UTOPIA) bus. 
     2. State of the Art 
     Perhaps the most awaited, and now fastest growing technology in the field of telecommunications in the 1990&#39;s is known as ATM technology. ATM is providing a mechanism for removing performance limitations of local area networks (LANs) and wide area networks (WANs) and providing data transfers at a speed of on the order of gigabits/second. Within the ATM technology, a commonly used interface specification between chips on a board for passing ATM cells is the UTOPIA interface. The UTOPIA interface is specified in ATM Forum standard specification af_phy — 0039.000 (UTOPIA Level 2, Version 1, June 1995) which is hereby incorporated by reference herein in its entirety. 
     Prior art FIG. 1 shows a typical intraboard ATM application of the UTOPIA interface. In particular, on a single board  11 , an ATM layer chip  15  is coupled to a physical layer chip  17  which is shown to include a plurality of physical devices  19   a - 19   d . The ATM layer chip  15  and physical layer chip  17  utilize the UTOPIA interface, which includes a five bit address bus  21 , a seventeen bit data/start-of-cell bus  23  (sixteen bits used for data), an enable line (one bit signal)  25 , and a cell available line (one bit signal)  27 . The physical layer chip  17  is provided with two address registers  31 ,  33 , a multiplexer  35  and a demultiplexer  37 . 
     The application shown in prior art FIG. 1 functions in the following manner using the timing shown in prior art FIG.  2 . The ATM layer chip  17  utilizes a clock such as a 50 MHz clock, and polls the physical layer devices for data by sequentially sending an address (of a physical device), followed by a NULL address (all ones), followed by a next address, followed by a NULL address, followed by a next address, etc. According to the UTOPIA interface standard, when a physical device is in a state in which it can receive data, it provides a cell available signal to the multiplexer  35 . The address received by the address register  31  is used as a select for the multiplexer  35 . Thus, when a particular physical device is selected, if it can receive data, a cell available signal is provided back to the ATM layer chip over the cell available line  27 . After polling is completed, the ATM layer chip  17  (or a processor coupled thereto) determines which physical device (address) is to receive the data. It then sends the address of the recipient over the address bus  21  in conjunction with an enable signal over line  25 . The selected address is clocked by the enable line into the address register  33 . The address register  33  is used as a control for the demultiplexer  37  which selects the physical device  19  which is to receive the data. The data (including the forty-eight byte payload of a cell) is then sequentially forwarded over the data bus  23  while a next sequential polling is performed over the address bus. 
     While the UTOPIA interface has proved to be very useful for interfacing two chips on a single board (intra-board), the UTOPIA interface has not been applicable across boards (inter-board) apparently because of both timing and “hot insertion” problems which can be encountered. In particular, OC-12 (622 Mbps) and four-port OC-3 (155 Mbps) standards require that the UTOPIA interface operate at up to a 50 MHz clock rate. However, many existing devices with UTOPIA interfaces have large propagation delays and inadequate drive capability for backplane applications (i.e., inter-board connections) operating at this clock rate. In addition, in inter-board applications, it is possible that one board is already functioning as the other board is being inserted (“hot insertion”), leading to the possibility of electrical shorting and damaging of components, and the provided UTOPIA interface standard does not provide a mechanism to deal with this problem. Thus, the UTOPIA specification is inadequate to cover inter-board interfaces. Indeed, the ATM Forum Standard committee apparently understood this problem and specifically stated in the standard that the backplane applications of the UTOPIA bus are “for further study”. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the invention to provide a UTOPIA interface enhancement which permits inter-board UTOPIA interfaces to function properly. 
     It is another object of the invention to provide a modified UTOPIA interface which is hot insertion tolerant. 
     In accord with the objects of the invention, a modified UTOPIA interface for inter-board applications is provided where the address timing generated by a polling master is extended to be two clock cycles long with no NULL address being driven onto the address line in between addresses. In addition, additional output and input circuitry is provided in conjunction with the master and user ATM boards to accommodate hot insertion and to help drive the circuit. The output circuitry provided in conjunction with the master preferably includes an outgoing address latch and address latch control associated with the address bus, and registers associated with the enable signal and the data bus. The input circuitry preferably provided in conjunction with the master includes a buffer on the cell available signal. The input circuitry preferably provided in conjunction with the user device(s) includes buffers on the address bus, the enable signal and the data bus. A remapping function is also preferably provided in associated with the user board which permits the user board to map received addresses into desired addresses. With the extended address timing and the provided circuitry, a workable inter-board hot-insertable UTOPIA interface is established. 
     Additional objects and advantages of the invention will become apparent to those skilled in the art upon reference to the detailed description taken in conjunction with the provided figures. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a prior art UTOPIA intraboard interface. 
     FIG. 2 is a prior art standard UTOPIA timing diagram associated with the UTOPIA interface of FIG.  1 . 
     FIGS. 3 a  and  3   b  are schematic diagrams of the inter-board UTOPIA interface of the invention implementing transmit and receive functions respectively. 
     FIGS. 4 a  and  4   b  are timing diagrams for the inter-board UTOPIA interface in the transmit and receive directions respectively. 
     FIGS. 5 a  and  5   b  are charts relating to certain important timings noted in FIGS. 4 a  and  4   b.   
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Turning to FIG. 3 a , a schematic diagram of the presently preferred modified UTOPIA interface is seen. In FIG. 3 a , two boards  50  and  52  are provided and are coupled together by, e.g., a connector  53 . For purposes of illustration, one board  50  is shown to contain an ATM layer device  55  and associated modified-UTOPIA circuitry, while the other board  52  is shown to contain physical layer devices  60  and associated modified-UTOPIA circuitry. The circuitry on board  50  preferably includes an address latch  66  and address latch control  68  for the address bus  121 , a buffer  69  for the cell available line  127 , register  70  for the enable line  125 , a register  72  for the data/start-of-cell bus  123 , and a clock buffer  74 . The circuitry on board  52  preferably includes a buffers  76 ,  78 ,  79  and  80  for the address bus, the enable line, the clock signal, and the data/start-of-cell bus respectively, two address remappers  82 ,  84 , an automatic protection switch control block  86 , a register  88  and multiplexer  92  associated with the cell available line  127 , and a demux  94 . 
     The functioning of the modified UTOPIA interface may be understood with reference to both FIGS. 3 a  and  4   a . In accord with the UTOPIA interface specifications, the ATM layer device  55  outputs an address. According to the invention, this address is latched into the address latch  66 . The address latch control  68  and address latch  66  represent a toggle circuit (signal TXLE of FIG. 4 a  representing the signal provided by latch control  68  to latch  66 ) such that the address provided during one clock cycle is held for two clock cycles (as seen in FIG. 4 a  as the transmitted latched output TXLO) by the address latch, while the NULL value provided in alternate clock cycles (as required by the UTOPIA standard and seen as “1F” in FIG. 4 a ) is effectively discarded. The latched address is provided via a buffer  76  (for hot insertion purposes) to the address remapper  82  which controls multiplexer  92 . The address remapper  82  receives information from the automatic protection switch control block  86  which is coupled to the physical devices  60 . With the provided arrangement, the address remapper  82  effects a remapping. More particularly, when a physical layer device is “down” and a redundant device of different address is available, the redundant device is utilized to service the data and data is remapped to the address of the redundant device. 
     When a physical device  60  is ready to receive a cell, a cell available signal is provided to the register  88  by the physical device. When a polling address is received by the address remapper  82  (and possibly remapped by the remapper  82 ), the remapper  82  controls the multiplexer  92  such that a cell available signal is provided by the appropriate physical device. The output from register  88  is high or low depending upon whether the physical device is ready to receive a cell. The cell available signal (TxClav in FIG. 4 a ) is provided via buffer  69  to the ATM layer device  55 . 
     It should be appreciated that the ATM layer device  55  sequentially polls all of the physical devices  60  (as indicated by different addresses N+2, N+1, N−2, etc. in TxAddr of FIG. 4 a ). The time taken for polling may occur in a single frame or multiple frames, depending upon the number of physical devices which are being polled. 
     After the ATM layer device  55  has polled the physical devices  60 , the ATM layer device  55 , or a processor or circuitry coupled thereto, determines to which device it will send a cell of data. After the last byte or multiple-byte of data of the previous cell has been sent over the data bus  123 , the address of the newly selected device is provided during the selection cycle (shown in FIG. 4 a ) to the address latch  66 , and the enable register  70  is enabled (TxEnbReg of FIG. 4 a ). The receiving address is provided via buffer  76  to the address remapper  84  which controls the demultiplexer  94 . When the enable signal is received by the demultiplexer  94  via hot insertion buffer  78  from the register  70 , the physical device  60  corresponding to the receiving address is enabled. A new cell of data (TxData in FIG. 4 a ) is then sent via register  72 , bus  123 , and hot insertion buffer  80  to the enabled address. A start-of-cell signal (TXSOC in FIG. 4 a ) is provided for one clock cycle with the first word of the new cell (it being appreciated that the start-of-cell signal is preferably provided on its own thread of the data bus  123 ). It is noted that the cell enable register  70  is preferably provided in order to delay the enable signal from reaching the demultiplexer  94  until after the address as remapped by the address remapper  84  has had the opportunity to set the appropriate address, as discussed in more detail below. 
     The timing associated with the address polling, cell available signaling, enable signaling, and sending of data is a critical aspect of the present invention. In particular, according to the previously incorporated ATM Forum UTOPIA standard specification Section 2.5, the parallel interface should run at up to 50 MHz. With a 50 MHz clock rate, each clock cycle is equivalent to twenty nanoseconds. According to the requirements of the ATM Forum UTOPIA specification af-phy-0039.000, a cell available response sequence must be completed within forty nanoseconds from when the address is generated by the ATM layer device. According to the UTOPIA specification, the addressing and cell available response is a two-step process. In a first step, an address is generated and output from the ATM layer device and persists for twenty nanoseconds. During this period, the physical layer device must capture and store the address for use during the next twenty nanosecond period. In a second step, the cell available response from the physical layer is placed on the bus and captured by the ATM layer device within a twenty nanosecond period. Thus, each step must be accomplished in twenty nanoseconds. However, in inter-board communications, it is often not possible to accomplish the first step in twenty nanoseconds because of the amount of time it takes the ATM layer device to put the address on the bus (e.g., fifteen nanoseconds) plus the delays associated with the path as well as connector capacitive loading. In addition, in inter-board communications, hot insertion capability is desirable, and this capability typically adds additional delay. According to the invention, timing issues are resolved by extending the address clocking to two clock lengths, such that a cell available signal can be properly associated with the address of the physical device being polled. This is preferably accomplished through the use of the address latch control  68  and address latch  66  so that the ATM Forum UTOPIA standard requiring an address followed by a null address (1F) can be utilized. With the extended address clocking, forty nanoseconds are now available to complete the combination address output—cell available response sequence in one step. The forty nanoseconds accommodates a typical maximum fifteen nanosecond delay in generating the address for output by the ATM layer device  55 , a typical maximum four nanosecond delay introduced by the address latch  66 /latch control  68  circuit, a typical 0.25 nanosecond delay introduced by hot insertion buffer  76 , a typical maximum five nanosecond delay introduced by the address remapper  82 , a typical maximum seven nanosecond delay introduced by the multiplexer  92  in outputting the cell available signal, a typical 0.25 nanosecond delay introduced by hot insertion buffer  69 , and a typical maximum additional two nanosecond delay introduced by the ATM layer device  55  in receiving the cell available signal; i.e., (15+4+0.25+5+7+0.25+2=33.5&lt;40). This permits several nanoseconds delay for the connector  53  and buses carrying signals to and from the connector. 
     As aforementioned, register  70  is provided to introduce sufficient delay to permit the alignment of the enable signal with the last twenty nanoseconds of the address. This is seen in FIG. 4 a , where the TxEnbReg signal is derived from the delayed TxEnb signal, and timing  6  of FIG. 4 a  which is noted in note  6  of FIG. 5 a.    
     After the appropriate physical device has been enabled, data (represented in FIG. 4 a  by words W 1 , W 2 , W 3  . . . ) may be sent by the ATM layer device  55  via register  72  and buffer  80  to the enabled physical device. While the data is being sent, the ATM layer device  55  starts the address polling process again, and the entire polling, response, selection, enabling, and data sending sequence is repeated. 
     The preferred exact timing of various signals utilized in the invention is shown in FIG. 4 a  which shows the end of one frame cycle, and the beginning of another frame cycle. Thus, FIG. 4 a  shows the last three words of data (W 25 , W 26 , W 27 ) of an ATM cell being generated (TxData) and transmitted (TxDataReg) on e.g., sixteen threads of the data bus  123 ; a seventeenth thread being reserved for the start of cell signal—TxSOCReg. The end of this cell is followed by a selection cycle, which is followed by transmission of data (words W 1 , W 2 , W 3  . . . ) to the newly selected address. During transmission of data, the polling of the various physical layer devices continues. Various important timing intervals are noted in FIG. 4 a  by reference numerals “1” through “10) and various arrows. The import of these timing intervals is set forth in FIG. 5 a  and will be understood by those skilled in the art. 
     While FIGS. 3 a  and  4   a  are directed to the transmission of data from the ATM layer device  55  to the physical devices  60  (i.e., the “transmit” direction), it will be appreciated that the apparatus of the invention preferably includes circuitry which permits data to be directed from the physical devices  60  to the ATM layer device  55 . The “receive” direction circuitry shown in FIG. 3 b  (with timing shown in FIG. 4 b , and important timing intervals explained in FIG. 5 b ). The receive direction circuitry is substantially identical to the “transmit” direction circuitry except that (i) the data register  72  is located on the physical layer board  52  instead of on the ATM layer board  50 ; (ii) the associated data buffer  80  is located on the ATM layer board  50  instead of the physical layer board; (iii) the hot insertion clock buffer  79  is located on the ATM layer board  50  instead of the physical layer board  52 ; and (iv) the clock buffer  74  is located on  52 . 
     As will be appreciated by those skilled in the art, the receive direction circuitry functions in substantially the same manner as the transmit direction circuitry, and the timing is nearly identical. The ATM layer board  50  generates polling addresses which are received by the physical layer board  52 . If any of the physical devices have data to send (as registered in register  88 ), when the address of the physical device is polled, a cell available signal is generated and returned to the ATM layer board  50 . After polling, the ATM layer board, or a processor associated therewith, determines which physical device will be enabled to send data. At an appropriate time, the address of the selected physical device is provided by the ATM layer board  50  to the physical layer board, and data is sent from the physical layer  52  to the ATM layer  50  over the data bus  123 . 
     There have been described and illustrated herein a hot insertable UTOPIA interface for backplane applications. While particular embodiments of the invention have been described, it is not intended that the invention be limited exactly thereto, as it is intended that the invention be as broad in scope as the art will permit. Thus, while the invention has been described with respect to certain hardware, it will be appreciated that various functions can be carried in different hardware. For example, while an address latch and address latch control have been provided in order to accommodate the address followed by null address scheme of the prior art, it will be appreciated that if backwards compatibility is not required, different circuitry can be utilized to hold the provided address for two clock cycles; or, the polling addresses can be repeated twice. Further, while the invention was described as preferably enabling hot insertion, the invention can be utilized without certain buffers which enable the hot insertion. Similarly, while the invention was described as preferably enabling address remapping, such is not required. Therefore, it will be apparent to those skilled in the art that other changes and modifications may be made to the invention as described in the specification without departing from the spirit and scope of the invention as so claimed.