Abstract:
Some microprocessors and microcontrollers have a bi-directional reset pin. In such devices, output signals on the reset pin are decoded by reset reason decode logic circuitry. The output of the reset reason decode logic can be provided to another device or processor, which generates a readily recognizable output signal indicative of a reason why the processor reset. Output signals that can indicate why a processor was reset can include a high or low state of different durations, serial bit streams or a number of pulses, each of which correspond to and therefore identify a reason why the processor was reset.

Description:
BACKGROUND 
       [0001]    Most microprocessors and microcontrollers have bi-directional external reset pins. Bi-directional reset pins act as both an input and an output. When used as an input, driving (forcing) the reset pin to a logic one or logic zero forces the processor to restart or reset. When used as an output, the signal or state of the reset pin provides an indication as to why an event or condition occurred which caused the processor to reset itself 
         [0002]    A processor can reset itself for a variety of reasons. Such reasons include but are not limited to the expiration of a hardware “watchdog timer,” a clock pulse frequency monitor, a voltage range monitor and a memory protection unit. Signals that are output on a processor reset pin can thus be evaluated with specialized equipment, i.e., “debug” tools, to determine why a processor reset. Unfortunately, tools that are capable of reading signals on reset pin are costly and cumbersome to operate. A cost efficient and real time evaluation of a reset pin output signal is thus problematic. An apparatus for, and a method of evaluating signals on a reset pin would be an improvement over the prior art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]      FIG. 1  is a block diagram of a prior art microprocessor or microcontroller; 
           [0004]      FIG. 2  is a block diagram of a microprocessor or microcontroller having reset reason decode logic and a reset pin output signal generator; and 
           [0005]      FIG. 3  is a block diagram of a method for communicating to the exterior of a processor having a reset reason register, a reason for the processor being reset. 
       
    
    
     DETAILED DESCRIPTION 
       [0006]      FIG. 1  is a block diagram of a prior art microprocessor or microcontroller  100 , both of which are collectively referred hereinafter simply as a processor. The processor  100  is comprised of a CPU or central processing unit  102 , which is the computational and control unit of the processor  100 . The CPU  102  reads instructions and data in memory devices that are coupled to the CPU  102  via busses  112 ,  114  and  116 , which are described more fully below. It then interprets and executes instructions and performs mathematical operations using one or more accumulator registers, not shown but well known to those of ordinary skill in the computer art. 
         [0007]    Executable instructions for the CPU  102  are stored in a random access memory or RAM  104 . Executable program instructions are also be stored in read only memory or ROM  106 . Executable instructions can also be stored in both the RAM  104  and the ROM  106 . In one embodiment, the RAM  104  and ROM  106  are resident on the same semiconductor die as the CPU  102 . In alternate embodiments, however, the RAM and ROM that store program instructions can be physically separate devices that are coupled to the CPU  102  via busses. 
         [0008]    The processor  100  controls and responds to external devices, examples of which are too numerous to list or describe but are collectively referred to simply as peripheral devices  108 . Communications between the CPU  102  and peripheral devices  108  takes place through interface circuitry  110 . The interface circuitry  110 , the RAM  104  and ROM  106  are coupled to the CPU  102  through an address bus  112 , a data bus  114 , and a control bus  116 . 
         [0009]    A “bus” is considered herein to be a conductor or group of conductors that serve or provide common connections between circuits that include the CPU  102 , memory devices, interface circuitry and other addressable circuits. A bus is also considered to be a controlled network technology by which circuits connected to the bus are able to read signals on the bus and respond thereto. In  FIG. 1 , the address bus  112  carries binary-valued signals that identify locations or addresses of memory locations. The data bus  114  carries non-address information to and from an accumulator in the CPU  102 . The control bus  116  carries signals that determine, among other things, memory read and write cycles and access to input/output devices. The busses  112 ,  114  and  116  couple the CPU  102 , the RAM  104 , the ROM  106  and the interface circuitry  110  together. 
         [0010]    The interface circuitry  110  is attached to the busses and includes, but is not limited to, parallel-to-serial and serial-to-parallel data converters. Such devices are well known in the art. The interface circuitry  110  also includes analog-to-digital (A/D) and digital-to-analog (D/A) converters, which are also well known in the art. 
         [0011]    The RAM  104  can be either static RAM or dynamic RAM both of which are well known in the art. The ROM  106  can be a so-called “mask” ROM but can also be EPROM or EEPROM or flash memory. 
         [0012]    A reset reason status register  118  is attached to all three busses  112 ,  114  and  116 . It is a multi-bit register that is loaded by either the CPU  102  or other device on the busses that cause the processor  100  to reset. The register  118  is loaded with a binary value or pattern of binary digits that identifies the device or event that caused the processor to reset. 
         [0013]      FIG. 2  is a block diagram of a processor  200  provided with a reset reason status register  118 , reset reason decoding logic  202  and a reset pin output signal generator  206 . Together, the reset reason decode logic  202  and the reset pin output signal generator  206  comprise a reset decoding device for the processor  200  and which provides an output signal on a reset pin which can be directly decoded or read to determine why the processor reset itself internally. Stated another way, the reset reason decode logic  202  evaluates the binary-valued signal from the reset reason status register  118  and from the contents of that register, identifies the event that caused the processor to be reset. The reset pin output signal generator  206  provides on a reset pin  208 , a signal that identifies an event that caused the processor to be reset. 
         [0014]    As stated above, the reset status register  118  is preferably a multi-bit, i.e., having more than one binary digit, data latch operatively coupled to the address bus  112 , the data bus  114 , and the control bus  116 . It is therefore responsive to signals placed on those buses by the CPU  102  as it executes instructions. The reset status register  118  is therefore responsive to program instructions executed by the CPU  102 . 
         [0015]    The contents of the reset reason status register  118  are loaded by one or both the CPU  102  or the mechanism that caused the reset with one or more patterns of binary digits, the particular values or patterns of which correspond to a reason why the processor  200  was reset internally. Stated another way, some processor embodiments have a CPU  102  that can load the reset reason status register  118 . Other processor embodiments are configured with a reset reason status register  118  that is loaded by a device other than the CPU  102 . Still other processor embodiments are configured to have the reset reason status register loaded by either the CPU  102  or other mechanisms. 
         [0016]    The output of the reset reason status register  118  is provided to a reset reason decode logic circuit  204  via a reset reason bus  204 . The reset reason decode logic  204  is comprised of combinational logic gates that decode the contents of the reason status register  118  and provide one or more output signals on a reset output bus  205  that correspond to, i.e., they identify, a reason why the processor  200  was reset internally. 
         [0017]    The reset output bus  205  can be comprised of a single pin or a multi-pin bus. The signals on the reset output bus  205  correspond to, i.e., identify, a reason why the processor  200  was reset. Examples of signals on the reset output bus  205  include but are not limited to a number of clock cycles, or fixed-durations during which the signal level on the pin  205  is held a logic one or a logic zero. Properly evaluation of the signals on the reset output bus  205  provides a reason why the processor  200  reset itself. 
         [0018]    By way of example, the reset output but  205  can be held low for say, 100 clock cycles, or perhaps 100 milliseconds, if the processor  200  resets itself because the power supply voltage was determined to be too low. An illegal address fetch on the address bus  112  might cause the processor  100  to reset itself and as a result, the hardware reset pin  205  can be held “low” for 200 clock cycles or perhaps 200 milliseconds. 
         [0019]    A binary-valued signal on the hardware reset pin  205  can also be comprised of a serial bit stream, the time or synchronization of which is based off the processor&#39;s clock signal. By way of example, a low voltage reset reason might be represented on the hardware reset pin  205  by a series of four logic zeros followed by a series of four logic ones, to with 00001111. An illegal address fetch on the address bus  112  might be comprised of eight binary-valued zeros or eight binary-valued ones, to with 11111111 or 00000000. In yet another embodiment, reset reason decode logic circuitry  204  provides a parallel set of output pins, the parallel contents of which correspond to a reset reason. 
         [0020]    In one preferred embodiment, the hardware reset pin  205  is coupled to a processor denominated as a reset pin output function generator  206 . The reset pin output function generator  206  acquires or “reads” the signals on the hardware reset pin  205  (or reset pins  205 ) and provides one or more of the aforementioned output signals onto an externally available bi-directional reset pin  208 . In another preferred embodiment, the reset pin output signal generator  208  sends a reset signal to the CPU  102 , which causes the CPU  102  to reconfigure itself after the reset even occurred. 
         [0021]      FIG. 3  is a block diagram of a method of communicating to the exterior of the processor  200 , a reason for the processor  200  being reset. The method  300  begins at step  302 , proceeds to step  304  and waits at step  304  until a processor internal reset event occurs. After an internal reset event occurs, such as an attempt to write data into ROM  106 , the method  300  proceeds to step  306  whereat the CPU  102  loads the reset reason status register  118  with a binary pattern or binary-valued signal, which corresponds to the reason for the processor  200  being reset. 
         [0022]    Once the reset reason status register  118  is loaded with a binary-valued signal or bit pattern, the contents of the reset reason status register  118  are asynchronously evaluated by the reset reason decode logic  204 . Step  308  thus indicates that the next step of the method is to evaluate the reset reason status register  118 . Once a reset reason has been evaluated by the decode logic  204 , the next step of the method is to generate or output a signal on the processor reset pin  208  which is indicative of a particular reason why the processor  200  was reset. 
         [0023]    As stated above, outputting a signal on the reset pin includes outputting one or more binary-valued signals. Such signals can be either parallel binary digits or a serial binary stream. The output signal can also be embodied as a time-dependent duration signal on a single processor pin or a series of pulses. In yet another embodiment, multiple different output reset pins can be provided to the processor  200 . 
         [0024]    The reset pin output signal generator  206  is preferably resident on the same die as the other functional elements of the processor  200 . In another embodiment however the reset pin output signal generator  206  can be resident on a separate integrated die or substrate and coupled to a reset reason decode logic circuit  204  through externally available pins on the package on which the processor  200  is resident. 
         [0025]    The foregoing is for purposes of illustration only. The true scope of the invention is set forth by the appurtenant claims.