Abstract:
Externally input voltages IN(−) and IN(+) are input to the input terminal of a differential amplifier unit ( 1 ) not directly, but after being shifted by voltage shift units ( 2, 3 ). The input voltages IN(−) and IN(+) are decreased by α when they are at high level, and by β when they are at low level. In this case, α&gt;β. The voltage difference of the external input voltage IN between high and low levels is relatively reduced, and then the external input voltage IN is input to the differential amplifier unit ( 1 ). This widens the substantial in-phase input voltage range in the differential amplifier unit ( 1 ).

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims benefit of priority under 35 USC 119 to Japanese Patent Application No. 2001-5346, filed on Jan. 12, 2001, the entire contents of which are incorporated by reference herein. 
     BACKGROUND OF THE INVENTION 
     The present invention relates to a differential amplifier circuit. 
     A differential amplifier circuit is used to amplify a voltage difference between two signals. The average of the voltages of two signals is called an in-phase input voltage, and the range of in-phase input voltages within which the differential amplifier circuit can normally operate is called an in-phase input voltage range. The differential amplifier circuit is more convenient with higher performance in a wider in-phase input voltage range. 
     FIG. 4 shows an example of a differential amplifier circuit concerning the present invention. The source and back gate of a P-channel MOS transistor MP 3  are connected as a current source to a first power supply terminal VDD, and its gate receives a reference voltage Vref 1 . 
     The drain of the transistor MP 3  is connected to the sources of P-channel MOS transistors MP 1  and MP 2 ; and its back gate, to the first power supply terminal VDD. The gate of the transistor MP 1  is connected to an input terminal IN(−); and that of the transistor MP 2 , to an input terminal IN(+). 
     The drain and gate of an N-channel MOS transistor MN 1  are connected to the drain of the transistor MP 1 ; and its source and back gate, to a second power supply terminal VSS. The drain of an N-channel MOS transistor MN 2  is connected to that of the transistor MP 2 ; its gate, to the gate and drain of the transistor MN 1 ; and its source and back gate, to the second power supply terminal VSS. 
     Voltages, currents, and the like when the transistors MP 1  to MP 3 , MN 1 , and MN 2  are generically called a transistor MXK will be called as follows: 
     VGSXK: gate-source voltage of MXK 
     VDSXK: drain-source voltage of MXK 
     IDXK: drain current of MXK 
     μSXK: mobility of MXK 
     WXK: gate width of MXK 
     LXK: gate length of MXK 
     VthXK: threshold voltage of MXK 
     An in-phase input voltage CMVIN in this differential amplifier circuit is calculated from a “second power supply terminal VSS→transistor MN 1 →transistor MP 1 →input terminal IN(−)” path: 
     
       
           CMVIN=VSS+VGSN   1 +| VDSP   1 |− VGSP   1 |  (1) 
       
     
     As the input voltage is decreased, |VDSP 1 | decreases. The case wherein the operating point of the transistor MP 1  coincides with the boundary between a saturation range and a non-saturation range can be regarded as a lower limit value CMVIN(L) 1  of the in-phase input voltage range. 
     Assuming that the drain-source voltage VDS of the transistor MP 1  at this time be an ON voltage VDS(ON)P 1 , we have 
     
       
         | VDS ( ON ) P   1 |=| VGS|−|Vth|   (2) 
       
     
     as shown in FIG.  5 . 
     Substituting equation (2) into equation (1) yields 
     
       
           CMVIN ( L ) 1 = VSS+VGSN   1 +| VDS ( ON ) P   1 |−| VGSP   1 |  (3) 
       
     
     
       
           CMVIN ( L ) 1 = VSS+VGSN   1 −| VthP   1 |  (4) 
       
     
     On the other hand, a MOS transistor which operates in the saturation range satisfies 
     
       
           VGS =(2 ID/μS*C   0   X* ( W/L )) 1/2   +Vth   (5) 
       
     
     where ID: drain current, μS: mobility, C 0 X: gate capacitance, W: gate width, and L: gate length. 
     The transistor MN 1  always operates in the saturation range because the gate and drain voltages are the same. Substituting equation (5) into equation (4) yields the lower limit value CMVIN(L) 1  of the final in-phase input voltage range: 
       CMVIN ( L ) 1 = VSS +(2 IDN   1 /μ SN   1 * C   0   X *( WN   1 / LN   1 )) 1/2   +VthN   1 −| VthP   1 |  (6) 
     The lower limit value CMVIN is calculated from a “first power supply terminal VDD→transistor MP 3 →transistor MP 1 →input terminal IN(−)” path: 
     
       
           CMVIN=VDD−|VDSP   3 |−| VGSP   1 |  (7) 
       
     
     As the input voltage is raised, the voltage |VDSP 3 | decreases. The case wherein the operating point of the transistor MP 3  coincides with the boundary between the saturation range and the non-saturation range can be regarded as an upper limit value CMVIN(H) 1  of the in-phase input voltage range. This value is given by 
     
       
           CMVIN ( H ) 1 = VDD−|VDS ( ON ) P   3 |−| VGSP   1 |  (8) 
       
     
     From equations (2) and (8), the upper limit value CMVIN(H) 1  is 
     
       
           CMVIN ( H ) 1 = VDD−|VGSP   3 |+| VthP   3 |−| VGSP   1 |  (9) 
       
     
     The operating point of the transistor MP 1  is in the saturation range. Equation (5) for the saturation range also holds for MP 3  whose operating point is at the boundary. Thus, from equations (5) and (9), the upper limit value CMVIN(H) 1  is: 
     
       
           CMVIN ( H ) 1 = VDD +(2 |IDP   3 |/(μ SP   3 * C   0   X*WP   3 )/ LP   3 )) 1/2 −(2 |IDP   1 |/(μ SP   1 * C   0   X*WP   1 )/ LP   1 ) 1/2   −|VthP   1 |  (10) 
       
     
     The in-phase input voltage range CMVIN 1  is given by 
     
       
           CMVIN   1 = CMVIN ( H ) 1 − CMVIN ( L ) 1   (11) 
       
     
     Assuming that the threshold voltages of the P- and N-channel MOS transistors are equal and VthN 1 =VthP 1 , the in-phase input voltage range is from CMVIN(H) 1  to CMVIN(L) 1 , as shown in FIG.  6 . Near the second power supply voltage VSS or the first power supply voltage VDD out of this range, some transistor operates in the non-saturation range and does not normally operate as a differential amplifier circuit. 
     The differential amplifier circuit suffers a problem that it cannot normally operate upon reception of a voltage exceeding the in-phase input voltage range given by equation (11). 
     SUMMARY OF THE INVENTION 
     A differential amplifier circuit according to an aspect of the present invention comprises a differential amplifier unit which has first and second input terminals and differentially amplifies first and second input signals respectively input to the first and second input terminals, a first voltage shift unit which is connected to a first external input terminal and the first input terminal, decreases the first external input signal by a first voltage when a first external input signal input from the first external input terminal is at high level or decreases the first external input signal by a second voltage smaller than the first voltage when the first external input signal is at low level, and supplies the resultant first external input signal as the first input signal to the first input terminal, and a second voltage shift unit which is connected to a second external input terminal and the second input terminal, decreases the second external input signal by the first voltage when a second external input signal input from the second external input terminal is at high level or decreases the second external input signal by the second voltage when the second external input signal is at low level, and supplies the resultant second external input signal as the second input signal to the second input terminal. 
     A differential amplifier circuit according to another aspect of the present invention comprises a differential amplifier unit which has first and second input terminals and differentially amplifies first and second input signals respectively input to the first and second input terminals, a first voltage shift unit which is connected to a first external input terminal and the first input terminal, reduces a range of high to low levels of a first external input signal input from the first external input terminal, and supplies the resultant first external input signal as the first input signal to the first input terminal, and a second voltage shift unit which is connected to a second external input terminal and the second input terminal, reduces a range of high to low levels of a second external input signal input from the second external input terminal, and supplies the resultant second external input signal as the second input signal to the second input terminal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing the arrangement of a differential amplifier circuit according to the first embodiment of the present invention; 
     FIG. 2 is a circuit diagram showing the arrangement of a differential amplifier circuit according to the second embodiment of the present invention; 
     FIG. 3 is a circuit diagram showing the arrangement of a differential amplifier circuit according to the third embodiment of the present invention; 
     FIG. 4 is a circuit diagram showing the arrangement of a differential amplifier circuit concerning the present invention; 
     FIG. 5 is a graph showing the relationship between the drain-source voltage and drain current of a MOSFET; and 
     FIG. 6 is a view showing the in-phase input voltage range in the differential amplifier circuit shown in FIG.  4 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. 
     (1) First Embodiment 
     FIG. 1 shows the arrangement of a differential amplifier circuit according to the first embodiment of the present invention. 
     This differential amplifier circuit comprises a differential amplifier unit  1 , and voltage shift units  2  and  3 . The voltage shift unit  2  outputs a voltage by decreasing it by level α for a high-level voltage IN(−) externally input via an input terminal IN(−), and outputs a voltage by decreasing it by level β for a low-level voltage IN(−). Levels α and β satisfy α&gt;β. That is, the voltage shift unit  2  outputs a voltage by reducing by α−β the range of the externally input voltage IN(−) between high and low levels. 
     Similarly, the voltage shift unit  3  outputs a voltage by decreasing it by level α for a high-level voltage IN(+) externally input via an input terminal IN(−), and outputs a voltage by decreasing it by level β for a low-level voltage IN(+). 
     The input voltages IN(−) and IN(+) shifted in this manner are input to the differential amplifier unit  1 , which outputs from an output terminal OUT a voltage amplified in correspondence with the difference between the input voltages IN(−) and IN(+). 
     If the externally input voltages IN(−) and IN(+) are directly input to the differential amplifier unit  1 , like the above-mentioned differential amplifier circuit concerning the present invention, the in-phase input voltage range is limited to the one given by equation (11), as described above. 
     To the contrary, in the first embodiment, a voltage decreased by level α is input to the differential amplifier unit  1  when the externally input voltages IN(−) and IN(+) are at high level. Regarding high level, the differential amplifier unit  1  can cope with a higher external input. When the externally input voltages IN(−) and IN(+) are at low level, a voltage decreased by level β is input to the differential amplifier unit  1 . This decrease is smaller than α, so that the influence on the input width for low level in the differential amplifier unit  1  is smaller than that for high level. 
     More specifically, according to the first embodiment, the voltage shift units  2  and  3  reduce by α−β the ranges of the input voltages IN(−) and IN(+) between high and low levels, and input the resultant voltages to the differential amplifier unit  1 . This widens the in-phase input voltage range. 
     The first embodiment can widen the in-phase input voltage range in comparison with the above-mentioned apparatus concerning the present invention. 
     (2) Second Embodiment 
     FIG. 2 shows the arrangement of a differential amplifier circuit according to the second embodiment of the present invention. 
     The second embodiment exemplifies the arrangement of the first embodiment. A differential amplifier unit  1  comprises transistors MP 1  to MP 3 , MN 1 , and MN 2 , similar to the circuit shown in FIG.  4 . 
     A voltage shift unit  2  comprises N-channel MOS transistors MN 3  and MN 4 . The drain of the transistor MN 3  is connected to a first power supply terminal VDD; its gate, to an external input terminal IN(−); and its source, to the gate of the transistor MP 1  serving as the input terminal of the differential amplifier unit  1 . The drain of the transistor MN 4  is connected to the gate of the transistor MP 1 , its gate receives a reference voltage Vref 2 , and its source is connected to a second power supply terminal VSS. The back gates of both the transistors MN 3  and MN 4  are connected to the second power supply terminal VSS. 
     A voltage shift unit  3  comprises N-channel MOS transistors MN 5  and MN 6 . The drain of the transistor MN 5  is connected to the first power supply terminal VDD; its gate, to an external input terminal IN(+); and its source, to the gate of the transistor MP 2  serving as the input terminal of the differential amplifier unit  1 . The drain of the transistor MN 6  is connected to the gate of the transistor MP 2 , its gate receives the reference voltage Vref 2 , and its source is connected to the second power supply terminal VSS. The back gates of both the transistors MN 5  and MN 6  are connected to the second power supply terminal VSS. 
     The transistors MN 4  and MN 6  flow a predetermined drain current and operate as a constant current source by inputting the reference voltage Vref 2  to their gates. 
     In the second embodiment, the in-phase input voltage CMVIN 2  is the sum of an in-phase input voltage CMVIN 1  in the circuit shown in FIG. 4 and a gate-source voltage VGSN 3  of the transistor MN 3  for the external input terminals IN(−) and IN(+). A lower limit value CMVIN(L) 2  of the in-phase input voltage range and an upper limit value CMVIN(H) 2  of the in-phase input range are given by 
     
       
           CMVIN ( L ) 2 = CMVIN ( L ) 1 + VGSN   3   (12) 
       
     
     
       
           CMVIN ( H ) 2 = CMVIN ( H ) 1 + VGSN   3   (13) 
       
     
     The in-phase input voltage range shifts upward by the voltage VGSN 3 , compared to the above-mentioned apparatus concerning the present invention. 
     The voltage VGSN 3  changes between high and low levels of the external input voltages IN(−) and IN(+). The voltage VGSN 3  for a high-level external input voltages IN(−) will be first described. 
     If the external input voltage IN(−) rises, the gate voltage of the transistor MN 3  rises. Since the drain current of the transistor MN 4  is a constant current, the drain current of the transistor MN 3  is also a constant current. The gate-source voltage VGSN 3  of the transistor MN 3  becomes constant, and the source voltage of the transistor MN 3  rises. 
     The back gate of the transistor MN 3  is connected to the second power supply terminal VSS. This widens the potential difference VSBN 3  between the back gate and source of the transistor MN 3 . As a result, a substrate bias effect occurs, and the threshold voltage Vth of the transistor MN 3  rises as given: 
     
       
           Vth=Vth   0 +γ((2 Φf+VSB ) 1/2 −(2 Φf ) 1/2 )  (14) 
       
     
     where Vth 0  is the threshold voltage for VSB= 0 , Φf is the Fermi level, and γ=1/(C 0 X)*(2qεNA) 1/2  (q: charge, ε: permittivity, NA: impurity concentration). 
     As is apparent from equation (14), the threshold voltage VthN 3  (H) for a high-level external input voltage IN(−) rises as the (VSB) 1/2  value increases. For a low-level external input voltage IN(−), the (VSB) 1/2  value is small, and the threshold voltage VthN 3  (L) hardly rises because of a small rise width of the source potential of the transistor MN 3 . 
     From this, the threshold voltage VthN 3  (H) of the transistor MN 3  for a high-level external input voltage IN(−) (in-phase input voltage is high), and the threshold voltage VthN 3  (L) of the transistor MN 3  for a low-level external input voltage IN(−) (in-phase input voltage is low) satisfy 
     
       
           VthN   3  ( H )&gt; VthN   3  ( L )  (15) 
       
     
     This relation holds not only for the transistor MN 3  but also for the transistor MP 5 . 
     Substituting equation (5) into equations (12) and (13) yields the lower and upper limit values CMVIN(L)2 and CMVIN(H) 2  of the in-phase input voltage: 
     
       
           CMVIN ( L ) 2 = CMVIN ( L ) 1 +(2 IND   3 / μSN   3 * C   0   X *( WN   3 / LN   3 )) 1/2   +VthN   3  ( L )  (16) 
       
     
     
       
           CMVIN ( H ) 2 = CMVIN ( H ) 1 +(2 IND   3 /μ SN   3 * C   0   X* ( WN   3 / LN   3 )) 1/2   +VthN   3  ( H )  (17) 
       
     
     Hence, the in-phase input voltage range CMVIN 2  is given by                    CMVIN2   =                  CMVIN                   (   H   )        2     -     CMVIN                   (   L   )        2                   =                  CMVIN                   (   H   )        1     -     CMVIN                   (   L   )        1     +     VthN3                   (   H   )       -                              VthN3                   (   L   )                   =                  CMVIN1   +     VthN3                   (   H   )       -     VthN3                   (   L   )         &gt;   CMVIN1                   (   18   )                                
     The second embodiment widens the in-phase input voltage range by increases in the threshold voltages Vth of the transistors MN 3  and MP 5  caused by the substrate bias effect, compared to the differential amplifier circuit shown in FIG.  4 . 
     (3) Third Embodiment 
     FIG. 3 shows the arrangement of a differential amplifier circuit according to the third embodiment of the present invention. 
     The third embodiment also exemplifies the arrangement of the first embodiment. The second embodiment uses the MOSFETs MP 1  to MP 3 , MN 1 , and MN 2  to constitute the differential amplifier unit  1 , whereas the third embodiment uses bipolar transistors QP 1  to QP 3 , QN 1 , and QN 2 . 
     The emitter of the PNP bipolar transistor QP 3  serving as a current source is connected to a first power supply terminal VDD, and its base receives a reference voltage Vref 1 . 
     The collector of the transistor QP 3  is connected to the emitters of the PNP bipolar transistors QP 1  and QP 2 . The base of the transistor QP 1  is connected to an input terminal IN(−) ; and that of the transistor QP 2 , to an input terminal IN(+). 
     The collector and base of the NPN bipolar transistor QN 1  are connected to the collector of the transistor QP 1 ; and its emitter, to a second power supply terminal VSS. The collector of the NPN bipolar transistor QN 2  is connected to that of the transistor QP 2 ; its base, to the base and collector of the transistor QN 1 ; and its emitter, to the second power supply terminal VSS. The collectors of the transistors QP 2  and QN 2  are commonly connected to an output terminal OUT. 
     Also in the third embodiment, the differential amplifier unit operates similarly to the second embodiment. Since voltage shift units  2  and  3  are connected to the bases of the transistors QP 1  and QP 1 , the in-phase input voltage range CMVIN 2  is widened as given by equation (18), similar to the second embodiment. 
     The differential amplifier circuit according to the above-described embodiments becomes more convenient with a larger in-phase input voltage width by connecting voltage shift units to the input terminal of a differential amplifier unit, reducing the voltage width of an externally input voltage between high and low levels, and supplying the resultant voltage to the input terminal of the differential amplifier unit. 
     The above embodiments are merely examples and do not limit the present invention. For example, the detailed circuit arrangements of the differential amplifier unit and voltage shift unit shown in FIGS. 2 and 3 are merely examples, and can be variously modified as needed.