Abstract:
A display system using a display panel in which scan signal electrodes and information signal electrodes are arranged like a matrix and a liquid crystal having a memory characteristic is sandwiched between both of the electrodes. Scan signals and information signals are respectively applied to the scan signal electrodes and the information signal electrodes to thereby drive said electrodes. The display system includes a memory for storing image data to be displayed by the display panel, a display mode memory for storing the driving condition defining a display mode with respect to the image data to be displayed by the display panel, and a display controller for reading out the image data to be displayed from the memory, for controlling a drive controller in accordance with the memory stored display mode.

Description:
This application is a continuation, of application Ser. No. 07/959,461 filed Oct. 9, 1992, now abandoned which is a continuation of application Ser. No. 07/480,570 filed Feb. 15, 1990, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a display system to display image data using a liquid crystal display panel in which scan signal lines and information signal lines are arranged like a matrix and a liquid crystal having a memory characteristic sandwiched between the scan signal lines and the information signal lines. 
     2. Related Background Art 
     Recently, in displays such as liquid crystal display devices and the like which are required for personal computers, work stations, and the like, the screen size and the resolution has increased yearly. Accordingly, improved compatibility with conventional displays is also needed. For instance, an IBM PC/AT personal computer may utilize several display modes in order to display due to CGA (Color Graphics Adapter), EGA (Enhanced Graphics Adapter), VGA (Video Graphics Adapter), 8514/A, etc. as specifications of adapters for images. The resolution of these various display modes and the numbers of expressionable colors, and the like differ. 
     A CRT such as Multisync II, Multisync 3D, 4D, or 5D made by NEC Ltd., or the like has been konwn as a product in which it is possible to display in many display modes by a single display. For instance, Table 1 in FIG. 8 shows video modes (display modes) which are supported by the Multisync 4D and 5D. 
     Comparatively, the fundamental operating principle of the display having the memory characteristic such as a ferroelectric liquid crystal display or the like differs from various fundamental operation principles which are used in the conventional displays such as CRT, STN-LCD (super twisted liquid crystal display), and PDP (plasma display). Therefore, the partial writing scanning method using the memory characteristic which has been proposed by Kanbe et al. in U.S. Pat. No. 4,655,561 is intended to be realized by combining &#34;low frame frequency driving + partial writing scanning&#34; to execute the display at a high resolution by the liquid crystal display having the memory characteristic described in JP-A-63-65494, or JP-A-285141 proposed by the inventors et al. of the present invention. 
     However, a new driving method is obviously necessary to meet the request to support the foregoing various display modes using a liquid crystal display having the memory characteristic such as a ferroelectric liquid crystal display (FLC display). Therefore, such a request cannot be realized by the conventional methods. There is proposed a total control method which allows the user to use either one of the various display modes from the turn-on of a power source by using the ferroelectric liquid crystal display coupled to a computer to change the display mode as necessary is proposed. 
     A method of realizing the above object of the present invention will now be clarified hereinbelow by providing a whole construction and its control method for supporting various display modes for use in, particularly, the IBM PC/AT and more generally for supporting a high precision mode of a resolution of 1280 (dots)×1024 (dots) by using the ferroelectric liquid crystal display as an example. 
     The ferroelectric liquid crystal display maintaining a memory characteristic and temperature dependent driving conditions is represented in FIG. 2. In the example, FIG. 2 shows that a frame frequency is set to 7 Hz at 10° C., 10 Hz at 25° C., and 20 Hz at 40° C. (the number of scan lines: 1024, driving voltage: 24 V, KMT-408 made by Nippon Nitrogen Co., Ltd. was used). Thus, in the case of 10° C. at the time of turn-on of the power source, the flicker can be prevented by an interlacing process of eight scan lines in the low frame frequency driving which has already been proposed. However, if the environmental temperature of the display rose together with the start of the operation, for instance, if the environmental temperature rose due to the heating by the back light or the forced use of an external heater or the like, assuming that the temperature rose to 25° C., the flicker can be sufficiently prevented by executing the interlacing process of four scan lines. Further, a division phenomenon of the display screen upon display of an animation screen, for instance, upon scroll display or the like, the only one drawback in the interlacing eight scan lines can be also reduced. Moreover, even at the same temperature, the driving method further changes depending on the video mode. For instance, in the FLC display at 10 Hz in the foregoing display mode of 1024 scan lines in Table 1 in FIG. 8, the number of scan lines is set to 480 in the VGA display mode and the frame frequency is set to 20 Hz or higher. The flicker can be sufficiently prevented by the ordinary (two scan lines) interlacing process and the division of the screen upon animation can be further reduced. However, according to the conventional method, although a method of determining the display mode exists, a method which can change the frame frequency of the display together with the environmental temperature of the display does not exist. 
     On the other hand, since the FLC display is the X-Y matrix display as mentioned above, the change in number of pixels depending on the display mode cannot be realized by simply changing the beam frequency of the CRT display. The physical number of pixels in the X-Y matrix display is unconditionally determined at the time of production and cannot be changed. Therefore, it is necessary to convert the logic number of pixels which is required in the display mode into the physical number of pixels. 
     Further, in the case where the color which can be displayed on the display side and the number of gradient levels do not coincide with those of the input data. For instance, in the case where in spite of monochrome fact that the display side has the display performance and eight gradient levels, the input data side requested 256 gradient levels with respect to each of R, G, and B, the relations among the colors and the numbers of gradient levels of the input data and output data must be previously determined in correspondence to each display mode. 
     Generally, as shown in FIG. 3, an effective display area and an external frame portion of the effective display area exist in the display area on the display. The portion which is surrounded by a point (x 1 , y 1 ) and a point (x 2 , Y 2 ),defining a square away from the physical coordinate origin (x 0 , y 0 ) on the display is used as an effective display screen. The logic screen area which is required by the display mode is set to the effective display area. In the case of assuring the VGA display mode area of 640 (in the x direction)×480 (in the y direction) in the physical screen display of 1280 (x direction)×1024 (y direction), the following two cases are considered where the external frame sizes differ. 
     Case 1: 
     Logical one pixel = Physical one pixel 
     (x 1 , y 1 )=(319, 271) 
     (x 2 , y 2 )=(959, 751) 
     Case 2: 
     Logical one pixel = Physical two pixels 
     (x 1 , y 1 )=(0, 31) 
     (x 2 , y 2 )=(1279, 991) 
     It should be noted that even if no image data exists, the external frame portion of the effective display portion of the display having the memory characteristic, such as an FLC display, must be driven by predetermined display data and such a point is different from the conventional display. Due to the memory characteristic, the drive data is also transferred to the frame portion, the display state of the frame portion is not aligned to, for instance, either white or black because of the memory characteristic. Therefore, when the display mode is decided, the size, color, and gradient level of the frame portion must be determined and in addition to the image data, the frame portion drive data must be generated for display. 
     On the other hand, when the display which is connected has two functions for the ordinary CRT or the like and for the FLC display, if the user desires to display in full colors even if the space utility is sacrificed. Accordingly, the system must be constructed in a manner such that when the user changes the connection to exchange the display or the like, the data transfer method and data transfer format of a graphics adapter can be changed. The data transfer method and data transfer format of the FLC display in the foregoing patent essentially differ from those of the conventional CRT or the like. 
     On the other hand, in the case where the driving conditions of the FLC display are not fully satisfied, for instance, when the environmental temperature does not reach a value in the display operating temperature range, the generation of the image data is also postponed by sending a wait request from the display side to the image data generating side. On the other hand, if the user wants to return the display mode to the display mode displayed prior to reset, it is necessary to reconstruct the previous state of those various control and drive parameters before resetting and, if necessary, the image data as well can be read out. 
     Even if individually preparing the means for satisfying the necessary conditions as mentioned above, it is desirable that the user can actually easily make a change on the basis of a predetermined procedure not only at the time of turn-on of the power source but also upon operation. Unless otherwise, each time the display mode is changed and used, the power source must be shut off and turned on or the system reset. 
     Particularly, when changing the display mode which has been previously set, there is a case where it is insufficient even when the display mode is merely reset to a new display mode. For instance, it is assumed that the display mode has been set to the VGA mode and is reset to the EGA display mode by a certain application software request. When the user tries to reset the display mode to the inherent VGA mode after completion of the application software, if the various FLC VGA display control parameters is changed have not been stored in some memory area, the display cannot be returned to the VGA mode. In such a case, the previous image data would need to be again developed. Therefore, the control or drive parameters of the FLC display and the image data before conversion need to be read out in accordance with a predetermined programming. 
     Since the FLC display has the memory characteristic, attention needs to be paid upon turn-on, resetting, and turn-off of the power source. For instance, with respect to the orientation control of the FLC display, if the supply of a DC voltage is not properly controlled, prolonged orientation deterioration and an after-image or &#34;sticking&#34; phenomenon occur. Therefore, a drive control circuit must be designed so as to avoid such a DC voltage supply problem upon turn-on or turn-off of the power source. However, when the drive control circuit is integrated with a computer, in many cases, generally, the power source is supplied from the main body side and the power source is also turned on or off by the user from the main body side. Therefore, it is necessary that the power on/off state initiated from the user side be sent to the drive control circuit of the FLC display and a predetermined on/off control necessary for the FLC display is executed and, thereafter, the ordinary power on/off control is performed. 
     To manufacture a computer product having the FLC display which satisfies the foregoing necessary requirements, it is necessary to prepare a ROM (called an ROM BIOS) in which the necessary parameters have previously been programmed in accordance with the product. The ROM BIOS actually acts as the interface between the control and display of the computer main body and FLC display. The user can control the display mode or the like without needing the detailed knowledge, particularly, to control and drive the FLC display. 
     SUMMARY OF THE INVENTION 
     It is the first object of the invention to provide a display system using a liquid crystal display panel having the memory performance, in which the image display can be totally controlled in accordance with various display modes. 
     The second object of the invention is to provide a display system using a liquid crystal display panel having the memory performance, in which driving conditions of the liquid crystal display panel can be properly determined upon turn-on or resetting of a power source of the system. 
     The third object of the invention is to provide a display system using a liquid crystal display panel having the memory performance, in which driving conditions of the liquid crystal display panel can be properly determined in correspondence to a change in environmental temperature. 
     The fourth object of the invention is to provide a display system using a liquid crystal display panel having the memory performance, in which information necessary to drive the liquid crystal display panel is previously stored as display modes in memory means and the liquid crystal display panel is driven and controlled in accordance with the display mode. 
     The fifth object of the invention is to provide a display system using a liquid crystal display panel having the memory performance, in which the user can totally control the image display in accordance with various display modes under control of a host computer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram showing a whole construction including a display, a main apparatus, and an ROM BIOS according to the present invention; 
     FIG 1A is a schematic representation of a cross-section of the display panel; 
     FIG. 2 is a graph showing a temperature dependency of a frame frequency as one of driving conditions of an FLC display unit; 
     FIG. 3 is a diagram showing the relation between an effective display area and an external frame portion in the display unit; 
     FIG. 4 is a timing chart showing communicating operations in the case where drive data and video data are transferred from a graphics controller on the main apparatus side to the display; 
     FIG. 5 is a timing chart showing communicating operations in the case where the graphics controller on the main apparatus side reads out the drive data of the display; 
     FIG. 6 is a timing chart showing communicating operations in the case where the graphics controller on the main apparatus side switches a display mode of the display; 
     FIG. 7 is a diagram showing the relation between the physical pixels and the logic pixels in the display area of a ferroelectric liquid crystal display according to the invention; 
     FIG. 8 is a diagram of a Table 1 showing schematic functions of the Multisync 4D and 5D (trade names) made by NEC Ltd. having the representative display mode switching function among CRTs; and 
     FIG. 9 is a diagram of a Table 2 showing an outline of functions and a part of driving conditions of the FLC display upon support of various CRT graphics modes based on IBM Corporation among display modes which the FLC display system has according to the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a hardware construction of a display panel 2 (1280×1024 pixels), display drivers 3 and 4, for driving electrodes 100 and 101 a display unit controller 8, and a graphics controller 9 having a VRAM 10 as an image data storage memory which construct a display system using a ferroelectric liquid crystal display according to an embodiment of the present invention. FIG. 1 also shows a hardware construction of a host CPU 11 and a host bus 12 showing the PC/AT machine made by IBM Corporation. FIG. 1 also shows an ROM BIOS 13 having therein a whole control monitor program as the present invention. FIG. 1A is a schematic cross-sectional view of the display panel illustrating the liquid crystal 122, disposed between an upper surface 121 and a lower surface 123. 
     (1) Functions of signal lines 
     The functions of signal lines provided between the host CPU 11 and the graphics controller 9 in FIG. 1 will now be described hereinbelow. 
     Host bus: 
     Standard interface hardware bus which is specified by IBM Corporation and is called an AT bus in the PC/AT machine made by IBM Corporation. 
     In FIG. 1, the functions of the signal lines provided between the FLC display unit controller 8 and the graphics controller 9 will now be described herein-below. 
     1) PD 0  to PD 7  : 
     Data buses. Bidirectional buses of eight bits. Data transfer rate is 10 MHz/8 bits. 
     2) CLK: 
     Transfer clocks. 20 MHz. 
     3) AH/DL: 
     ID signal between the drive data and the video data. High level in the case of the drive data. Low level in the case of the video data. 
     4) IH/OL: 
     Input/output ID signal of the data bus. 
     When the data buses PD 0  to PD 7  are set into the input mode when they are seen from the graphics controller, High level. 
     When they are set into the output mode, Low level. 
     5) INT: 
     Interruption signal from the display side to the graphics controller. 
     6) FLG: 
     Data output permission signal from the display side to the graphics controller. 
     When the output is permitted, High level. 
     7) Hsync: 
     Horizontal sync signal. Data reception permission signal from the display side to the graphics controller. 
     8) Vsync: 
     Vertical sync signal. Sync signal for each display screen. 
     (2) Fundamental operaiton 
     The function which was defined in the ROM BIOS 13 is called from the video data generating side, that is, from the host CPU 11 side in accordance with a predetermined calling rule. If necessary, parameters which are necessary to realize the function are transmitted to the graphics controller 9. If the function was called by a normal procedure, in order to realize the requested function, the translation is made by a GCPU (graphics control central processing unit) 14 or the graphics controller 9 is directly accessed. The contents and the outline of the operations in the case of translation or direct access operative will now be practically explained hereinbelow. 
     The graphics controller 9 transfers the drive data and video data to the FLC display unit by use of bidirectional data buses PD 0  to PD 7 . However, to transmit the drive data and video data by the same transmission path, the two kinds of data must be distinguished. An AH/DL signal is used to distinguish time. When the AH/DL signal is set to the High level, the data on the PD 0  to PD 7  indicates the &#34;drive data&#34;. If the AH/DL signal is at the low level, the data indicates the &#34;video data&#34;. 
     The FLC display unit controller 8 extracts the drive data from the video signal with the drive data which is transferred on the PD 0  to PD 7  and executes the process based on the drive data. On the other hand, the video data is sent to a shift register 6 on the information electrode drive circuit side on the basis of transfer clocks. 
     On the other hand, in the embodiment, since the FLC driving and display and the generation of the drive data and video data in the graphics controller 9 are asynchronously executed, it is necessary to synchronize the apparatuses upon transmission of the display data. The signals Hsync and Vsync are used to realize such synchronization. The Hsync signal is generated in the FLC display unit controller 8 every horizontal scan period, while the Vsync signal is generated in the controller 8 every vertical scan period upon refreshing. The Hsync and Vsync signals are sent to the graphics controller 9. The graphics controller 9 always monitors the Hsync and Vsync signals. When the Vsync signal is at the High level and the Hsync signal is at the Low level, the display data (drive data + video data) is transferred. In the other cases, after completion of the transfer of the one display data, the graphics controller 9 waits until the next transfer permission signal is input. 
     FIG. 4 is a timing chart for the fundamental communication when the display data is sent from the graphics controller 9 side to the FLC display unit controller 8 side of an FLC display unit 1. The operation will now be described. 
     When the graphics controller 9 detects that the Hsync signal is at the Low level (at the same time, the following conditions must be satisfied: namely, INT=high and Vsync=High and IH/OL=Low), the AH/DL signal is immediately set to the High level, thereby starting the transfer of the display data. The display controller 8 of the FLC display unit 1 sets the Hsync to the High level during the display data transfer period of time. After completion of a series of processes based on the transferred drive data, the controller 8 of the FLC display 1 again sets the Hsync to the Low level and enters the standby mode to receive the next display data. 
     FIG. 5 is a timing chart for the fundamental communication when the graphics controller 9 side reads out the display data from the controller 8 side of the FLC display unit 1. The operation will now be described hereinbelow. 
     First, the graphics controller 9 sends &#34;information read request data&#34; which has been predetermined between the controller 8 of the FLC display unit 1 and the controller 9. Such data acts as the drive data to the controller 8 of the FLC display unit 1 in accord with the timings of A 0  to A 15  in FIG. 5. The graphics controller 9 sets the IH/OL signal to the High level, thereby setting the data input mode. At this time, the data buses PD 0  to PD 7  are set in the high impedance state (Z) when they are seen from the side of the graphics controller 9. When the controller 8 of the FLC display unit 1 recognizes the &#34;information read request data&#34;, it confirms that the IH/OL line is at the High level and, thereafter, the controller 8 sends the data onto the data buses PD 0  to PD 7  and, further, sets the FLG signal to the High level. When the graphics controller 9 detects that the FLG line is set to the High level, it reads the data then existing on the data buses PD 0  to PD 7  and stores into the GCPU 14. 
     (3) Communicating operation in the video display mode 
     In the video display mode, the display data is sent from the graphics controller 9 side to the display side in a manner similar to the case of the communication in FIG. 4. At this time, the scan line address data is used as the drive data and is sent to the positions of A 0  to A 15  in FIG. 4 and is transferred to the display controller 8. 
     Explaining in more detail, the scan line address data is extracted by the controller 8 of the FLC display unit 1 and is input to a decoder 7 on the scan line electrode drive circuit side. This in accordance with the timing to drive the designated scan line, so that the designated scan line on the display is selected. On the other hand, the video data is transferred to the shift register 6 on the information electrode drive circuit side and is shifted on an 8-pixel unit basis by transfer clocks (CLK). After completion of the shifting process by one scan line in the horizontal direction by the shift register 6, the video data of 1280 pixels is transferred to a line memory 5 provided for the shift register 6 and is stored for one horizontal scan period of time. After the writing of the video data to the display panel 2 for one predetermined horizontal scan period of time is finished, the controller 8 of the display unit again sets the Hsync to the Low level and receives the display data of the next scan line. 
     By repeating the above series of communicating operations, the writing operation and the partial writing operation to the display panel screen are executed. 
     (4) Operation in the display mode setting 
     Upon setting from the host side 
     The display mode for the display is fundamentally set and changed on the basis of a request from the host side and fundamentally in accordance with a timing chart shown in FIG. 6. Explanation will now be made practically hereinbelow. 
     1 When a display mode change request is generated from the host CPU 11 side, the graphics controller 9 sends &#34;display mode change request data&#34; to the drive data portion when the display data is transferred to the controller 8 of the display unit 1 (when the AH/DL line is at the High level, that is, at the timings of A 0  to A 15  in FIG. 6). 
     2 After the controller 8 of the display unit 1 recognizes predetermined &#34;display mode change request data&#34;, it sets the Hsync line to the Low level. 
     3 Then, the graphics controller 9 sends &#34;display mode number&#34; as the drive data to the controller 8 of the display unit 1 in accord with the timing of A 0  to A 15  in FIG. 6 and sets the IH/OL signal to the High level, thereby switching the data buses PD 0  to PD 7  to the input mode. 
     4 The controller 8 of the display unit 1 receives the &#34;display mode number&#34; and determines the driving conditions of the display panel in accordance with the display mode. The controller 8 decides the relation between the number of physical pixels and the number of logical pixels and the relation of either one of the color and the number of gradient levels or the relation between both of the color and the number of gradient levels. The controller 8 determines the size of the effective display screen and the size of the external frame portion of the display area in the display screen. The controller 8 decides the relation of either one of the color of the external frame portion and the number of gradient levels or the relation between both of the color of the external frame portion and the number of gradient levels. The controller 8 determines the transfer format or the timing of the data from the image data memory section to the display or both of the transfer format and the timing of such data. In order to confirm that the communication has correctly been executed or not, the controller 8 checks that the IH/OL line is at the High level and, thereafter, sends the received &#34;display mode number&#34; to the data buses PD 0  to PD 7  and sets the FLG signal to the High level. 
     5 After the graphics controller 9 confirmed that the FLG line was at the High level, it stores the &#34;display mode number&#34; data which was output to the data buses PD 0  to PD 7  into the GCPU 14. 
     6 The GCPU 14 compares the received data with the &#34;display mode number&#34; which has previously been transferred and, after completion of the confirmation it sets the IH/OL signal to the Low level. 
     7 After the controller 8 of the display unit 1 confirms that the IH/OL line was set to the Low level, it sets the Hsync line to the Low level and waits for the next display data. 
     8 After the graphics controller 9 confirms that the Hsync line was set to the Low level, if a check of the display mode determines it is normal, the graphics controller 9 sends the ordinary scan line address + video data alternatively, if it is abnormal, the graphics controller 9 again sends &#34;display mode change request data&#34; and again executes the processes from step 1. 
     By the above procedure, the change of the display mode and the drive control of the display panel according to each display mode can be executed. 
     (5) Operation in the display mode setting 
     When setting from the display side 
     For instance, in the case where the graphics controller 9 and the controller 8 of the display unit 1 are contain different power sources and the power source on the side of the controller 8 of the display unit 1 is used with the graphics controller 9 (on the host side), the controller 8 side of the display unit 1 cannot know in which display mode the graphics controller 9 has been operating. In such a case, the controller 8 of the display unit 1 sends the INT signal to the graphics controller 9 and requests to set the display mode. When the graphics controller 9 receives the INT signal from the display unit controller 8, it checks the FLG line. If the FLG line is at the Low level, the graphics controller 9 recognizes a request for display mode set. Subsequently, the display mode is set in accordance with a procedure similar to the case of step (4) for operation after setting of the display mode--the operation upon setting from the host side. 
     (6) Operation upon temperature data read request 
     To know the temperature data of the display unit 1 by the host side, a method is used where the graphics controller 9 side in FIG. 5 reads the temperature data as a part of the display data from the controller 8 side of the FLC display unit 1. The operation will be further practically described hereinbelow. 
     1 The graphics controller 9 adds &#34;temperature data read request data&#34; to the drive data portion (when the AH/DL line is at the High level) when the display data is transferred to the display and sets the IH/OL signal to the High level. Thus, the data buses PD 0  to PD 7  can be switched into the input mode. 
     2 After the controller 8 of the display unit 1 recognizes the predetermined &#34;temperature data read request data&#34;, it confirms that the IH/OL line is at the High level. Then, the controller 8 sends the &#34;temperature data&#34; to the data buses PD 0  to PD 7  and sets the FLG signal to the High level. 
     3 After the graphics controller 9 confirms that the FLG line was set to the High level, it stores the &#34;temperature data&#34; which was output to the data buses PD 0  to PD 7  into the GCPU 14. 
     On the other hand, a read request can be also sent from the display side to the main apparatus as necessary. In such a case, in a manner similar to the case of setting the display mode, the display first sends the INT signal to the graphics controller 9. When the graphics controller 9 receives the INT signal from the display side, it checks the FLG line. If the FLG line is at the High level, the graphics controller 9 recognizes that the reading of the temperature data is requested. After that, the reading process of the temperature data is executed in a manner similar to the case where the request was generated from the main apparatus side. 
     Table 2 presents the IBM support mode list. There, the alphanumeric mode 1 and graphics mode 2 are defined by the adapter names, characters and resolutions, colors the numbers of gradient levels, and the FLC display drive data. In Table 2, an expression &#34;b/p&#34; is used to decide the color and the number of gradient levels in the output data for the input data. In the video data format stored in the video data storage memory VRAM 10 in FIG. 1, the expression &#34;b/p&#34; represents the color for one pixel (one logical pixel) and the number of bits define the binary expression of the gradient data amount. An expression &#34;ratio&#34; in Table 2 indicates the relation between the number of physical pixels and the number of logical pixels and the relation is shown in FIG. 7. According to the FLC display in the embodiment, two physical pixels having different area ratios are set into one pixel unit. Therefore, when the ratio=1, it corresponds to the minimum one logical pixel construction and the number of expressionable gradient levels is set to 4. (The FLC display is fundamentally a binary expression display and a method in which two physical pixels having different area ratios are set into one pixel unit as mentioned above has already been proposed as one of methods of realizing the multi-value expression by the FLC display, namely, the gradation expression.) When the ratio=2, one logical pixel is constructed by two minimum pixel units based on four physical pixels and the number of gradient levels can be set to 8. Similarly, when the ratio=4, one logical pixel is constructed by four minimum pixel units based on eight physical pixels and the number of gradient levels can be set to 16. 
     As mentioned above, either one of various display modes is used from the time of the turn-on of the power source and the total control method necessary to change the display mode in accordance with the necessity is set in the ROM. There is provided a control monitor section in which the display mode can be further changed from the host side in accordance with a predetermined required procedure. Thus, it is possible to satisfy the request to support various display modes as in the foregoing Multisync machines by use of the ferroelectric liquid crystal display which also needs the control of drive data, not possible using a conventional method. 
     The invention is not limited to the ferroelectric liquid crystal display but can be applied to any display system which has a memory characteristic and in which the driving conditions are temperature dependent.