Abstract:
The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V 0  programmable on the basis of command signals supplied to the switches.

Description:
TECHNICAL FIELD 
     The invention relates to a programmable voltage generator, particularly for programming multilevel non-volatile memory cells. 
     BACKGROUND OF THE INVENTION 
     As is known, a multilevel memory cell, of the flash type for example, may be programmed so as to exhibit one of N threshold voltages (or more precisely one of N distributions of the threshold voltage) and is therefore capable of storing a number M=log 2 N. 
     The requirements for programming a multilevel memory are much more stringent compared with two level memories: in particular, to obtain an adequate accuracy of the programmed levels it is necessary for the cells to have threshold voltages distributed in intervals which are sufficiently narrow and spaced in a reduced time. 
     For example, according to a known solution, a stepped voltage which increases linearly with a pre-determined increment is supplied to the selected word line connected to the gate terminal of the cell to be programmed. 
     This increment must be defined with the utmost accuracy in view of the fact that there is a linear relationship between the increase in the threshold voltage ΔV T  of the cell to be programmed and the increment of the gate voltage ΔV GP  applied, if the drain voltage of the cell to be programmed is kept constant. 
     To program four level cells for example it is possible to use a stepped voltage which increases from a minimum value equal to 1.5 V up to a maximum value equal to 9 V, with constant increment equal to approx. 300 mV. 
     According to a known solution, a voltage generator of the type shown in FIG. 1 is used to obtain the above-mentioned stepped voltage. 
     In detail, FIG. 1 shows a voltage generator  2  included in a memory device  1  of multilevel type and having an input terminal  2   a  connected to a reference generator  3 , of the band-gap type for example, supplying a reference voltage V BG , and an output terminal  2   b  at which an output voltage V 0  is present. 
     The voltage generator  2  comprises a differential amplifier  4 , an operational amplifier for example, having a power supply terminal  4   a  connected to a power supply line  5  set at a supply voltage V PP , a non inverting input  4   b  connected to the reference generator  3  and an inverting input  4   c  connected to a feedback node  6 . The operational amplifier  4  further has an output terminal coincident with the output terminal  2   b  of the voltage generator  2 . 
     A voltage divider  9  is connected between the output terminal  2   b  of the voltage generator  2  and a ground terminal GND and comprises a feedback resistor  8 , having a constant resistance R 1 , and a programmable resistor  10 , having a variable resistance R 2 , as illustrated in detail below. The feedback resistor  8  is connected between the ground terminal GND and the feedback node  6 , the programmable resistor  10  is connected between the feedback node  6  and the output terminal  2   b.    
     The voltage generator  2  operates as follows. 
     During each programming phase of the memory device  1 , because of the feedback supplied at the inverting input  4   c  of the operational amplifier  4 , the output voltage V 0  depends on the reference voltage V BG  and on the resistances R 1  and R 2  according to the expression:                V   0     =       V   BG          (     1   +       R   2       R   1         )               (   1   )                                
     By increasing the resistance of the programmable resistor  10  by a value R 2 *, a corresponding increment in the output voltage V 0  is obtained, which is equal to:                Δ                   V   0       =       V   BG          (       R   2   *       R   1       )               (   2   )                                
     The voltage divider  9  is generally produced as shown in FIG. 2, in which the programmable resistor  10  comprises a fixed resistor  21 . 0 , of resistance R 0 , and a plurality of additional resistors  21 . 1 ,  21 . 2 , . . . ,  21 .n, of resistance R. 1 , R. 2 , . . . , R.n and disposed in series with each other between the output terminal  2   b  and the fixed resistor  21 . 0 . For example, the additional resistors  21 . 1 ,  21 . 2 , . . . ,  21 .n may be constituted by a string of resistors having a resistance which increases with the powers of two, i.e., for example, if the additional resistor  21 . 1  has a resistance Rx, the successive additional resistors  21 . 2 ,  21 . 3 , . . . ,  21 .n have a resistance of 2Rx, 4Rx, . . . , 2 N−1 Rx. A selection switch  26 . 1 ,  26 . 2 , . . . ,  26 .n, produced as a CMOS switch for example, controlled by a respective command signal, is connected in parallel with each additional resistor  21 . 1 ,  21 . 2 , . . . ,  21 .n. 
     The number of selection switches  26 . 1 ,  26 . 2 , . . . ,  26 .n which must be opened or closed from time to time depends on the value of R 2  it is desired to program, given that the additional resistors  21 . 1 ,  21 . 2 , . . . ,  21 .n which do not contribute to the desired resistance value R 2  are each short circuited by a respective selection switch  26 . 1 ,  26 . 2 , . . . ,  26 .n. 
     This known solution does, however, have a number of disadvantages. Primarily the output voltage V 0  is not linear. 
     In fact, although the selection switches  26 . 1 ,  26 . 2 , . . . ,  26 .n individually have a small resistance which is negligible compared to the resistances of the respective additional resistors  21 . 1 ,  21 . 2 , . . . ,  21 .n, they introduce a resistance error which causes a mismatching between the resistance R 1  of the feedback resistor  8  and the resistance R 2  of the programmable resistor  10 . Furthermore, the resistance error is not constant but depends on the number of closed selection switches  26 . 1 ,  26 . 2 , . . . ,  26 .n, and cannot therefore easily be compensated. If a large number of selection switches  26 . 1 ,  26 . 2 , . . . ,  26 .n is closed the resistance error becomes substantial and comprises a substantial error on the output voltage V 0 . 
     In this connection reference is made to FIG. 3 which shows, as a function of the number n of programming steps, the plot of the ideal voltage V 0ID  (unbroken line) and of the actual voltage V 0RE  obtained at the output of the voltage generator  2  (dashed line). 
     The non linearity of the output voltage V 0  may be quantified by means of the non linearity error ε d  defined by the expression:          ɛ   d     =                V     0      ID            (   i   )       -       V     0      RE            (   i   )                Δ                   V   GP                                
     where V 0ID  (i) and V 0RE  (i) are the ideal and actual values of the output voltage V 0  at the i&#39;th programming step and ΔV GP  is the programmed increment of the gate voltage of the cell to be programmed and coincides with ΔV 0 . 
     In practice, the use of the voltage divider  9  of FIG. 2 results in a differential error ε d  on the order of approx. ±15%. 
     A further disadvantage of this known solution is due to the presence of a voltage spike at the feedback node  6  following the switching of the selection switches  26 . 1 ,  26 . 2 , . . . ,  26 .n. This voltage spike, which slows down the rise of the output voltage V 0 , is due to the injection of charge at the feedback node  6  and its amplitude depends on the number of selection switches which switch contemporaneously with the change in the value to be programmed. Furthermore the injection of charge is particularly high when the selection switches are of large dimensions, as may be demanded by linearity requirements. 
     On the other hand, to ensure that the output voltage V 0  assumes a correct value in a reduced time, as required for programming multilevel cells, it is necessary to reduce the voltage spike at the feedback node  6  to a minimum. 
     SUMMARY OF THE INVENTION 
     A voltage generator is provided which drastically reduces the disadvantages described. 
     The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V 0  programmable on the basis of command signals supplied to the switches. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a better understanding of the invention, two embodiments will now be described, purely by way of non-exhaustive example and with reference to the accompanying drawings in which: 
     FIG. 1 shows a simplified circuit diagram of a known voltage generator; 
     FIG. 2 shows a circuit diagram of a known voltage divider included in the voltage generator of FIG. 1; 
     FIG. 3 shows plots of an electrical variable taken at the output of the voltage generator of FIG. 1; 
     FIG. 4 shows a first circuit embodiment of a voltage divider according to the invention; and 
     FIG. 5 shows a second circuit embodiment of a voltage divider according to the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 4 shows a first embodiment according to the invention of the voltage divider  9  of FIG.  1 . The voltage divider  9  comprises a feedback resistor  14 , having constant resistance R 1 , and a programmable resistor  16 , having variable resistance R 2 . 
     The programmable resistor  16  comprises a fixed resistor  31 . 0 , having resistance R 0 , and a plurality of additional resistors  31 . 1 ,  31 . 2 , . . .  31 .n, having equal resistance R E  and disposed reciprocally in series, between the output terminal  2   b  and the fixed resistor  31 . 0 . 
     Intermediate nodes  32 . 0 ,  32 . 1 , . . . ,  32 .n−1 connected to the output terminal  2   b  by means of respective selection switches  36 . 0 ,  36 . 1 , . . . ,  36 .n−1 are present between pairs of adjacent resistors  31 . 0 ,  31 . 1 ,  31 . 2 , . . .  31 .n; furthermore a selection switch  36 .n is interposed between the additional resistor  31 .n and the output terminal  2   b . Each selection switch  36 . 0 ,  36 . 1 , . . .  36 .n is controlled by a respective closure signal S 0 , S 1 , . . . , S n , where n is equal to the number of additional resistors  31 . 1 ,  31 . 2 , . . .  31 .n which are present. The closure signals S 0 , S 1 , . . . , S n  are generated by a control unit  18  so as to control the closure of one only of the selection switches  36 . 0 ,  36 . 1 , . . .  36 .n at a time, keeping all the other switches open. 
     When, for example, the selection switch  36 .j controlled by the closure signal S j  (j being a number between 0 and n inclusive) is closed, the corresponding intermediate node  32 .j is connected directly to the output terminal  2   b . Consequently the fixed resistor  31 . 0  and j additional resistors  31 . 1 ,  31 . 2 , . . . ,  31 .j are connected in series between the feedback node  6  and the output terminal  2   b  while the remaining additional resistors  31 .j+1, . . . ,  31 .n are excluded. In this way a single selection switch  36 .j, of resistance r on , is connected in series with the fixed resistor  31 . 0  and the j additional resistors  31 . 1 ,  31 . 2 , . . . ,  31 .j. Therefore the overall resistance R 2  of the programmable resistor  16  is given by the expression: 
     
       
         
           R 
           2 
           =R 
           0 
           +jR 
           E 
           +r 
           on 
         
       
     
     and varies between R 0 +r on  and R 0 +nR E +r on . 
     In this way, during each programming phase of the memory device  1  of FIG. 1, because of the feedback supplied to the inverting input of the operational amplifier  4 , the output voltage of the voltage generator  2  is given by the expression:          V   0     =         V   BG          (     1   +         R   0     +     j                   R   E       +     r   on         R   1         )                       (       j   =   0     ,   1   ,   …              ,   n     )                              
     The error on the output voltage V 0  due to the resistance r on  may be compensated either by reducing the fixed resistance R 0  or by disposing a dummy switch  40 , always closed, in series with the feedback resistor  14 , as shown in FIG. 4 by a dashed line. In particular the resistance R on1  of the dummy switch  40  is dimensioned so that the following equation is valid:              R   2     +     r   on           R   1     +     r   on1         =       R   2       R   1                              
     In this way the values of the resistances R 2  and R 1  are matched and a minimal non-linearity error (approx. 1%) is guaranteed. 
     The voltage peaks on the feedback node  6  are also greatly reduced because a single selection switch  36 . 0 ,  36 . 1 , . . . ,  36 .n is being opened and switched off at all times. 
     FIG. 5 shows a second embodiment of the voltage divider  9  in which k additional resistors  31 . 1 ,  31 . 2 , . . . ,  31 .k are present; furthermore the intermediate node  32 . 0  between the fixed resistor  31 . 0  and the first additional resistor  31 . 1  is divided into two nodes  32 . 0   a  and  32 . 0   b  and a circuit network  50  is present between the nodes  32 . 0   a  and  32 . 0   b.    
     The circuit network  50  comprises a plurality of branches  49 . 0 ,  49 . 1 , . . . ,  49 .m connected reciprocally in parallel between the nodes  32 . 0 a and  32 . 0 b. The branch  49 . 0  comprises a parallel switch  48 . 0  only. The branches  49 . 1 ,  49 . 2 , . . . ,  49 .m each comprise a parallel resistor  51 . 1 ,  51 . 2 , . . . ,  51 .m and a parallel switch  48 . 1 ,  48 . 2 , . . . ,  48 .m, reciprocally in series. The parallel resistors  51 . 1 ,  51 . 2 , . . . ,  51 .m have multiple resistance R Ei  with respect to a resistance R EP  equal to the sum of the resistances of the additional resistors  31 . 1 , . . . ,  31 .k, i.e., R EP =kR E . Consequently the parallel resistor  51 . 1  has a resistance equal to R EP , the parallel resistor  51 . 2  has a resistance equal to 2R EP , . . . and the parallel resistor  51 .m has a resistance equal to mR EP . 
     Each parallel switch  48 . 0 ,  48 . 1 ,  48 . 2 , . . . ,  48 .m is controlled by a respective closure signal P 0 , P 1 , . . . , P m , where m is equal to the number of parallel resistors  51 . 1 ,  51 . 2 , . . .  51 .m which are present and has a resistance r on  equal to the resistance of the selection switches  36 . 0 ,  36 . 1 , . . . ,  36 .k. 
     The closure signals P 0 , P 1 , P m  are generated by the same control unit  18  which generates the closure signals S 0 , S 1 , . . . , S k . In particular, the control unit  18  causes the closure of a single selection switch  36 . 0 ,  36 . 1 , . . . ,  36 .k and of a single parallel switch  48 . 0 ,  48 . 1 ,  48 . 2 , . . . ,  48 .m to obtain the desired resistance value R 2 . 
     In the circuit of FIG. 5 the overall resistance values R 2  of the programmable resistor  16  can be found by the expression: 
     
       
         
           
             
               R 
               2 
             
             = 
             
               
                 R 
                 0 
               
               + 
               
                 
                   ∑ 
                   
                     i 
                     = 
                     0 
                   
                   m 
                 
                  
                 
                     
                 
                  
                 
                   
                     ∑ 
                     
                       j 
                       = 
                       0 
                     
                     k 
                   
                    
                   
                       
                   
                    
                   
                     ( 
                     
                       
                         jR 
                         E 
                       
                       + 
                       
                         iR 
                         EP 
                       
                     
                     ) 
                   
                 
               
             
           
         
                 
         
             
         
      
     
     and the overall number of obtainable resistor values is equal to (m+1)k+1=n. 
     Because a single selection switch  36 . 0 ,  36 . 1 , . . . ,  36 .k and a single parallel switch  48 . 0 ,  48 . 1 ,  48 . 2 , . . . ,  48 .m are closed at the same time and they have equal resistance, as noted above, the contribution which the switches  36 . 0 ,  36 . 1 , . . . ,  36 .k,  48 . 0 ,  48 . 1 ,  48 . 2 , . . . ,  48 .m make to the value of the overall resistance R 2  is given by 2r on . 
     Therefore, in a similar manner to the description for the embodiment of FIG. 4, in order to obtain an adequate match between the overall resistance of the feedback resistor  14  and the resistance of the programmable resistor  16  and hence guarantee a minimum non-linearity error —d , two dummy switches  54  each having a resistance R on1  of value such that:              R   2     +     2        r   on             R   1     +     2        r   on1           =       R   2       R   1                              
     in which r on  represents the resistance of the switches  36 . 0 ,  36 . 1 , . . . ,  36 .k,  48 . 0 ,  48 . 1 ,  48 . 2 , . . . ,  48 .m in this case also, are connected in series to the feedback resistor  14 . 
     Compared to the first embodiment of the programmable resistor  16  this second embodiment has the further advantage of reducing the overall number of selection switches and of relative control lines, thereby reducing the dimensions of the memory device  1 . 
     Finally it will be evident that modifications and variants may be introduced to the voltage generator described without thereby departing from the scope of the invention. 
     For example, in the second embodiment of the voltage divider  9  the plurality of parallel resistors  51 . 1 ,  51 . 2 , . . . ,  51 .m may be inserted between the plurality of additional resistors  31 . 1 ,  31 . 2 , . . . ,  31 .k and the output terminal  2   b  of the voltage generator  2  instead of in the position shown. 
     Furthermore, although the description of the present generator refers to use as a stepped voltage generator for programming multilevel memory cells it may be employed in a plurality of applications, such as in a digital/analogue converter, and generally wherever a stable and accurate programmable voltage is required to be available.