Abstract:
A bidirectional word length converter for use in transferring data between a first data processing unit and second data processing unit each using a word format of a different length. The converter includes a buffer connected between the first and second units and a converter control. The converter control is adapted to accept a plurality of mode signals from the first unit to control the transfer of data in a first length word format from the first unit to the second unit in a second length word format. The converter control is further adapted to accept an alternative plurality of mode signals to transfer data from the second unit to the first unit in a similar manner.

Description:
BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     The present invention relates to word length converters and, more particularly to a word length converter employed between a first and a second data processing unit each utilizing a different word length. 
     (2) Background Art 
     Work length converters are very well known to those skilled in the art. In this regard word converters are known which transfer data from a unit using a given word format to a second unit using a larger word format. Such converters transfer a received smaller word in the format of a larger word filling in high-order bits with blank data. Such an arrangement while operating generally satisfactorily requires the second unit to store and process nonmeaningful blank information. 
     Other arrangements are known which transmit data words serially between units one bit at a time. In this regard, transfers both to the unit using the larger word format and to the unit using the smaller word format reception processing of each bit of information separately and additional processing to format the received data bits into data words. Such an arrangement, while operating generally satisfactorily, requires the expenditure of large amounts of data processing capability to effect the transfer of data. 
     Accordingly, it is the object of the present invention to provide a new and useful word length converter that provides reformated data to the second unit without resorting to the use of blank filler data or large amounts of data processing capability as found in previously utilized designs. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention overcomes the above cited problems by providing a bidirectional word length converter for use in transferring data between a first data processing unit utilizing a word format of a first length and a second data processing unit uitlizing a word format of a second length. The converter includes a buffer connected between the first and the second units and a converter control. 
     The converter control includes a buffer control connected between the first unit and the buffer. The buffer control, in response to receipt of a plurality of mode signals from the first unit, generates a plurality of first control signals to operate the buffer to accept data in the first length word format from the frist unit and transmit the data in the second length word format to the second unit. 
     The converter also includes a second unit control connected between the buffer control and the second unit. The second unit control is operated in response to receipt of a plurality of second control signals from the buffer control to extend a plurality of command signals to the second unit to operate the second unit to accept data in the second length word format. 
     In the alternative, the buffer control in response to the receipt of a plurality of alternative mode signals from the first unit, generates an alternative plurality of second control signals to the second unit control which is operated in response to receipt of the above alternative plurality of second control signals from the buffer control to extend an alternative plurality of command signals to the second unit to operate the second unit to transmit data in the second length word format to the buffer and to extend a plurality of third control signals to the buffer control. 
     The buffer control is further operated in the alternative in response to receipt of the plurality of alternative mode signals from the first unit and the plurality of third control signals from the second unit control, to generate an alternative plurality of first control signals to operate the buffer to accept data in the second length word format from the second unit and transmit the data in the first length word format to the first unit. 
     The present invention additionally may in alternative embodiments be adapted to transmit data only from the first unit to the second unit or adapted to transmit data only from the second unit to the first unit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The single sheet of drawings comprises a schematic diagram of a word length converter employing the operational principles of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to the figure there is shown a first data processing unit 1, a second data processing unit 2 and a word length converter 3 in accordance with the present invention connected therebetween. The word length converter 3 includes a write buffer 5, a read buffer 6 and a converter control including a buffer control 8 and a second unit control 9. The write buffer 5 and the read buffer 6 are connected between the first unit 1 and the second unit 2. The buffere control 8 is connected to the first unit 1, to the write buffer 5, and to the read buffer 6. The second unit control 9 is connected between the buffer control 8 and the second unit 2. 
     The write buffer 5 includes a write register 11 including a first portion 12 and a second portion 13, and a write multiplexer 15. The first portion 12 and the second portion 13 of the write register 11 each include a plurality of inputs connected to the first unit 1, a plurality of outputs and a store lead. The write multiplexer 15 includes a plurality of outputs connected to the second unit 2 and a plurality of input groups, each input group including a plurality of inputs connected to predetermined ones of the write register outputs. Similarly, the read buffer 6 includes a read register 21 including a first portion 22 and a second portion 23, and a read multiplexer 25. 
     The first portion 22 and the second portion 23 of the read register 21 each include a plurality of inputs connected to the second unit 2, a plurality of outputs and a store lead. The read multiplexer 25 includes a plurality of outputs connected to the first unit and a plurality of input groups, each input group including a plurality of inputs connected to predetermined ones of the read register 21. 
     The buffer control 8 includes a timing sequence generator 30, a multiplexer control 40, a write register control 50 and a read register control 60. The timing sequence generator 30 includes an oscillator 31, a four bit shift register 32, a write cycle latch 33 a read cycle latch 34 an OR gate 35, an inverter 36 and an OR gate 37. The shift register 32, includes a shift clock input connected to an output of the OR gate 35 and four outputs. The first output of the shift register 32 is unconnected, the second output is connected to a first input of the OR gate 37, and the fourth output is connected to a second input of the OR gate 37 and an input of the inverter 36. The write cycle latch 33 and the read cycle latch 34 each include a mode signal data input, a stobe signal clock input, a latch reset input and a latch output. The mode signal data inputs and the strobe signal clock inputs of the write cycle latch 33 and the read cycle latch 34 are connected to the first unit 1, the latch reset inputs are connected to an output of the inverter 36, and the outputs are connected to a first input and a second input of the OR gate 35 respectively. 
     The multiplexer control 40 includes a two bit binary counter 41 including a clock input and a first and a second output. The clock input of the two bit binary counter 41 is connected to the fourth output of the shift register 32. 
     The write register control 50 includes an AND gate 51 and inverter 52 and an AND gate 53. The AND gate 51 includes an output connected to the store input of the first portion 12 of the write register 11, and the AND gate 33 includes an output connected to the store input of the second portion 13 of the write register 11. The AND gates 51 and 52 each include a first input connected to the second output of the shift register 32. The first output of the two bit binary counter 41 is connected to a second input of the AND gate 53 and an input of the inverter 52. 
     The read register control 60 includes an AND gate 61 and inverter 62 and an AND gate 63. The AND gate 61 includes an output connected to a store input of the first portion 22 of the read register 21 and the AND gate 63 includes an output connected to the store input of the second portion 23 of the read register 21. The AND gate 61 and the AND gate 63 each include a first input, the first inputs connected together. The inverter 62 includes an output connected to a second input of the AND gate 61 and an input connected to a second input of the AND gate 63 and the first output of the two bit binary counter 41. 
     The second unit control 9 includes a write control 70 and a read control 80. The write control 70 includes an &#34;OR&#34; gate 71, an AND gate 72 and an AND gate 73. The AND gate 71 includes a first and a second input each connected to corresponding outputs of the two bit binary counter 41 and an output connected to a first input of the AND gates 72 and 73. The AND gates 72 and 73 each include a second input connected to the mode signal data input of the write cycle latch 33 and an output connected to the second unit 2. The AND gate 72 includes a third input connected to the output of the OR gate 37, and the AND gate 73 includes a third input connected to the third output of the shift register 32. 
     The read control 80 includes a NAND gate 81, an AND gate 82 and an AND gate 83. The AND gate 81 includes a first and a second input connected to corresponding outputs of the two bit binary counter 41 and an output connected to a first input of the AND gate 82 and the AND gate 33. The AND gates 82 and 83 each include a second input connected to the mode signal data input of the read cycle latch 34. 
     The AND gate 82 includes a third input connected to the output of the OR gate 37 and an output connected to the second unit 2. The AND gate 83 includes a third input connected to the third output of the shift register 32 and an output connected to the first inputs of the read register control AND gates 61 and 63. 
     The timing sequence generator 30 is operated in accordance with the present invention by receipt of mode signals from the first unit 1. In this regard, receipt of a write request signal coincident with a write strobe signal on the data and clock inputs respectively, of the write cycle latch 33 will set the write cycle latch 33. Alternately, receipt of a read request signal coincident with a read strobe signal on the data and clock inputs respectively of the read cycle latch 34 will set the read cycle latch 34. The write cycle latch 33 or the read cycle latch 34 will act with the OR gate 35, the shift register 32, the oscillator 31, and the inverter 36 as a &#34;Johnson&#34; counter. The &#34;Johnson&#34; counter in cooperation with the OR gate 37 will generate a first, a second, a third and a fourth timing signal. The second timing signal and the third timing signal will commence at the same time followed by commencement of the fourth timing signal and followed later yet by commencement of the first timing signal. The second timing signal will then cease followed by the fourth timing signal ceasing and lastly the first and third timing signals will cease simultaneously thus completing one cycle of the timing sequence generator. 
     The multiplexer control 40 is operated by receipt of a series of a first timing signal to generate on its outputs a two bit binary address, the control 40 initially outputing an address of &#34;zero&#34; followed in sequence by the addresses &#34;one&#34;, &#34;two&#34;, &#34;three&#34; and the address &#34;zero&#34; again. The addresses &#34;zero&#34;, &#34;one&#34;, &#34;two&#34;, and &#34;three&#34; comprise gating signals for the write multiplexer 15 and the read multiplexer 25. The write register control 50 is operated in response to receipt of the first timing signal coincident with an address of &#34;zero&#34; or &#34;two&#34; from the multiplexer control 40 to generate a store signal to the first portion 12 of the write register 11. The write register control 50 is further responsive to the second timing signal coincident with an address of &#34;one&#34; or &#34;three&#34; from the multiplexer control 40 to generate a store signal to the second portion 13 of the write register 11. 
     The write control 70 is responsive to the third timing signal coincident with the write signal from the first unit and an address of &#34;one&#34;, &#34;two&#34;, or &#34;three&#34; from the multiplex control 40 to generate a write request signal to the second unit 2. The write control 70 is further responsive to a fourth timing signal coincident with the write signal from the first unit 1 and an address of &#34;one&#34;, &#34;two&#34;, or &#34;three&#34; from the multiplexer control 40 to generate a write request strobe signal to the second unit 2. The write request signal and the write request strobe comprise a write command signal sent to the second unit 2. 
     The read control 80 is responsive to a read signal coincident with the third timing signal and an address of &#34;zero&#34;, &#34;one&#34;, or &#34;two&#34; from the multiplex control 40 to generate a read request signal to the second unit 2. The read control 80 is further responsive to the fourth timing signal from the timing sequence generator 30 coincident with the read signal from the first unit 1 and an address of &#34;zero&#34;, &#34;one&#34;, or &#34;two&#34; from the multiplex control 40 to generate a read request strobe signal to the read register control 60. The read request signal comprises a read command signal sent to the second unit 2 and the read command signal and write command signal comprise command signals sent to the second unit 2. Further, the timing signals, the multiplexer gating signals, the write signal, and the read signal comprise second control signals. Finally, the read request strobe signal comprises the third control signal. 
     The read register control 60 is operated in response to a read request strobe signal from the read control 80 coincident with an address of &#34;zero&#34; or &#34;two&#34; from the multiplex control 40 to generate a store signal to the first portion 22 of the read register 21. The read register control 60 is further operated in response to the read request strobe signal from the read control 80 coincident with an address of &#34;one&#34; or &#34;three&#34; from the multiplex control 40 to generate a store signal to the second portion 23 of the read register 21. 
     Write multiplex 15 and the read multiplex 25 are both responsive to adresses of &#34;zero&#34;, &#34;one&#34;, &#34;two&#34;, and &#34;three&#34; from the multiplex control 40 to gate the zero grouping, first grouping, second grouping, and third grouping of inputs to their respective outputs. The write register first and second portion store signals together with the multiplexer gating signals comprise write control signals, the read register first and second portion store signals together with the multiplexer gating signals comprise read control signals, and the write and read control signals comprise first control signals. 
     The word length converter of the present invention may be operated to transmit a series of words in the first length word format from the first unit 1 to the second unit 2 in the second length word format in groups of four words. In this regard, the multiplex control will initially output an address &#34;zero&#34; to the write multiplex 15 thereby gating its zero input group to the second unit 2. The first unit 1 will start transmitting a group of words by transmitting the write signal to the timing sequence generator 30 and the write control 70. Simultaneously, the first unit 1 will transmit a first data word to a write register 11 and a write strobe signal to the timing sequence generator 30. The timing sequence generator 30 will generate the second timing signal which, when received by the write register control 50 coincident with the address &#34;zero&#34; from the multiplex control 40 will generate a store signal to the first portion 12 of the write register 11 thereby storing the data word presented by the first unit 1 therein. At this time the presence of the address &#34;zero&#34; from the multiplexer control 40 on the inputs of the gate 71 of the write control will prevent any signals from being generated and extended to the second unit 2. Upon occurrence of the first timing signal from the timing sequence generator 30 on the input to the multiplexer control 40, the multiplexer control 40 will increment its address to the address &#34;one&#34;. 
     The first unit 1 will then extend a second data word to the write register 11 and a second strobe signal to the timing sequence generator 30; this while maintaining the write signal to both the timing sequence generator 30 and the write control 70. The timing sequence generator 30 will again generate timing pulses and the write register control 50, upon receipt of the second timing signal from the timing sequence generator 30 coincident with the address &#34;one&#34; from the multiplexer control 40, will generate a store signal to the second portion 13 of the write register 11 to store the extended data word therein. Upon occurrence of the third timing signal the write control will extend a write request signal to the second unit instructing it to prepare to receive the first converted data word. Upon the occurrence of the fourth timing signal from the timing sequence generator 30 the write control will generate a write strobe signal to the second unit 2 instructing the second unit 2 to accept the first converted data word consisting of the data in the first portion 12 and the first third of the second portion 13 of the write register 11. Upon the occurrence of the first timing signal the multiplexer control 40 will increment its address to the address &#34;two&#34; thereby disabling the first multiplexer input group and gating the second multiplexer input group to the second unit in preparation for the next converted data word to be tranmitted. 
     The first unit 1 will then extend a third data word to the write register 11 and a third strobe signal to the timing sequence generator 30, this with the write signal extended as above. The write register control 50 upon receipt of the second timing signal coincident with the address &#34;two&#34; from the multiplexer control 40 will generate a store signal to the first portion 12 of the write register to store the extended data word therein. Upon the occurrence of the third and fourth timing signals the write control 70 will extend first a request signal then a strobe signal to the second unit instructing the second unit to accept a second converted data word consisting of the second two-thirds of the second portion of the write register plus the first two-thirds of the first portion of the write register. Upon the occurrence of the first timing signal, the multiplexer control will increment its address to &#34;three&#34;. 
     The first unit 1 will then extend a fourth data word to the write register 11 and a fourth strobe signal to the timing sequence generator 30 as above. The write register control 15 will upon the occurrence of the second timing signal and the adress &#34;three&#34; from the multiplex control 40 generate a store signal to the second portion 13 of the write register 11 to store the extended data word therein. Upon the occurrence of the third and fourth timing signals, the write control 70 will extend a request and a strobe signal to the second unit 2 to instruct it to receive the third converted data word consisting of the last third of the second portion of the write register and the entire first portion of the write register. Upon the occurrence of the first timing signal the multiplexer control will increment its address to &#34;zero&#34; thus completing transmission of four words from the first unit in a first length word format to the second unit as three words of a second length word format. Additional words may be transmitted in groups of four in the manner described. 
     The word length converter of the present invention may be operated to receive a group of three data words in a second length word format as four data words in a first length word format. In this regard, the first unit 1 will extend a read signal to the timing sequence generator 30 and the read control 80 followed by and coincident with a read strobe signal to the timing sequence generator 30. The timing sequence generator 30 will generate timing signals as described above and the read control 80 upon receipt of an initial address of &#34;zero&#34; from the multiplexer control 40 coincident with the third timing signal and the read mode signal from the first unit 1 will generate a read request to the second unit 2 whereupon the second unit 2 will present a first data word in the second length word format to the read register 21. Upon the occurrence of the fourth timing signal coincident with the address &#34;zero&#34; from the multiplexer control 40 and the read mode signal from the first unit 1, the read control 80 will extend a strobe signal to the read register control 60. The read register control 60 will, upon receipt of the read register store signal coincident with the address &#34;zero&#34; from the multiplexer control 40, will extend a store signal to the first portion 22 of the read register 21 to store the first data word therein. Upon the occurrence of the first timing signal the multiplexer control 40 will increment its address to the address &#34;one&#34; and extend that address to the read multiplexer 25 gating the first input group consisting of the first three-quarters of the first portion of the read register to the first unit 1. The first unit 1 will then read the first converted data word. 
     The first unit 1 will then request a second and a third converted data word and read the same as described above. The second converted data word will consist of the last quarter of the first portion of the read register together with the first half of the second portion of the read register, while the third converted data word will consist of the last half of the second portion of the read register together with the first quarter of the first portion of the read register. Following the reading of the third data word the multiplexer control will output the address &#34;three&#34;. 
     The first unit 1 will then extend a fourth read strobe signal to the timing sequence generator 30 to request a fourth converted data word as described above and again the timing sequence generator 30 will generate the above mentioned timing signals. The read control 80 upon detection of the address &#34;three&#34; from the multiplexer control 40 via the gate 81 will be prevented from generating a read request to the second unit and a strobe signal to the read register control 60. The multiplexer control 40 upon occurrence of the first timing signal will extend the address &#34;zero&#34; to the read multiplex 25 gating the fourth converted data word consisting of the last three-quarters of the first portion of the read register 21 to the first unit 1 thus completing a read sequence of four data words. Additional data words may be read in a like manner in groups of four. 
     While but a single embodiment of the present invention has been disclosed, it will be obvious to those skilled in the art that numerous modifications may be made without departing from the spirit of the invention which shall be limited only by the scope of the claims appended hereto.