Abstract:
There is provided an address-while-display driving method for a surface discharge type triode plasma display panel, which includes sequentially performing resetting and addressing on each XY-electrode line pair while alternately and consecutively applying display voltages to all XY-electrode line pairs of the panel. The panel includes a front substrate and a rear substrate that are separately formed to face each other, X- and Y-electrode lines that are alternately arranged in parallel between the front and rear substrates to form the XY-electrode line pairs, and address electrode lines that are formed in perpendicular to the X- and Y-electrode lines. The address-while-display driving method includes lowering the display voltages during an addressing time for each XY-electrode line pair.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to an address-while-display driving method for a plasma display panel, and more particularly, to an address-while-display driving method for a surface discharge type triode plasma display panel. 
   2. Description of the Related Art 
     FIG. 1  shows the structure of a conventional surface discharge type triode plasma display panel (PDP)  1 .  FIG. 2  shows an example of a display cell of the PDP  1  shown in  FIG. 1 . Referring to  FIGS. 1 and 2 , address electrode lines A 1 , A 2 , . . . , A m-1 , A m ; front and rear dielectric layers  11  and  15 ; Y-electrode lines Y 1 , . . . , Y n ; X-electrode lines X 1 , . . . , X n ; phosphor layers  16 ; partition walls  17 ; and a magnesium oxide (MgO) layer  12  as a protective layer are provided between front and rear glass substrates  10  and  13  of a general surface discharge PDP  1 . 
   The address electrode lines A 1  through A m  are formed on the front surface of the rear glass substrate  13  in a predetermined pattern. A rear dielectric layer  15  is formed on the entire surface of the rear glass substrate  13  having the address electrode lines A 1  through A m . The partition walls  17  are formed on the front surface of the rear dielectric layer  15  to be parallel to the address electrode lines A 1  through A m . These partition walls  17  define the discharge areas of respective display cells and serve to prevent cross talk between display cells. The phosphor layers  16  are deposited between partition walls  17 . 
   The X-electrode lines X 1  through X n  and the Y-electrode lines Y 1  through Y n  are formed on the rear surface of the front glass substrate  10  in a predetermined pattern to be orthogonal to the address electrode lines A 1  through A m . The respective intersections define display cells. Each of the X-electrode lines X 1  through X n  is composed of a transparent electrode line X na  ( FIG. 2 ) formed of a transparent conductive material, e.g., indium tin oxide (ITO), and a metal electrode line X nb  ( FIG. 2 ) for increasing conductivity. Each of the Y-electrode lines Y 1  through Y n  is composed of a transparent electrode line Y na  ( FIG. 2 ) formed of a transparent conductive material, e.g., ITO, and a metal electrode line Y nb  ( FIG. 2 ) for increasing conductivity. A front dielectric layer  11  is deposited on the entire rear surface of the front glass substrate  10  having the rear surfaces of the X-electrode lines X 1  through X n  and the Y-electrode lines Y 1  through Y n . The protective layer  12 , e.g., a MgO layer, for protecting the PDP  1  against a strong electrical field is deposited on the entire surface of the front dielectric layer  1 . A gas for forming plasma is hermetically sealed in a discharge space  14 . 
     FIG. 3  shows a typical address-display separation driving method with respect to Y-electrode lines of the PDP  1  shown in  FIG. 1 . Referring to  FIG. 3 , to realize time-division gray scale display, a unit frame is divided into 8 subfields SF 1  through SF 8 . In addition, the individual subfields SF 1  through SF 8  are composed of address periods A 1  through A 8 , respectively, and display periods S 1  through S 8 , respectively. 
   During each of the address periods A 1  through A 8 , display data signals are applied to the address electrode lines A 1  through A m  of  FIG. 1 , and simultaneously, a scan pulse is sequentially applied to the Y-electrode lines Y 1  through Y n . If a high-level display data signal is applied to some of the address electrode lines A 1  through A m  while the scan pulse is applied, wall charges are induced from address discharge only in relevant display cells. 
   During each of the display periods S 1  through S 8 , a display discharge pulse is alternately applied to the Y-electrode lines Y 1  through Y n , and the X-electrode lines X 1  through X n , thereby provoking display discharge in display cells in which wall charges are induced during each of the address periods A 1  through A 8 . Accordingly, the brightness of a PDP is proportional to a total length of the display periods S 1  through S 8  in a unit frame. The total length of the display periods S 1  through S 8  in a unit frame is 255T (T is a unit time). Accordingly, including the case where the display is not performed in a unit frame, 256 gray scales can be displayed. This is explained below. 
   Here, the display period S 1  of the first subfield SF 1  is set to a time 1T corresponding to 2 0 . The display period S 2  of the second subfield SF 2  is set to a time 2T corresponding to 2 1 . The display period S 3  of the third subfield SF 3  is set to a time 4T corresponding to 2 2 . The display period S 4  of the fourth subfield SF 4  is set to a time 8T corresponding to 2 3 . The display period S 5  of the fifth subfield SF 5  is set to a time 16T corresponding to 2 4 . The display period S 6  of the sixth subfield SF 6  is set to a time 32T corresponding to 2 5 . The display period S 7  of the seventh subfield SF 7  is set to a time 64T corresponding to 2 6 . The display period S 8  of the eighth subfield SF 8  is set to a time 128T corresponding to 2 7 . 
   Accordingly, if a subfield to be displayed is appropriately selected from among 8 subfields, a total of 256 gray scales can be displayed including a gray level of zero at which display is not performed in any subfield. 
   According to the above-described address-display separation display method, the time domains of the respective subfields SF 1  through SF 8  are separated, so the time domains of respective address periods of the subfields SF 1  through SF 8  are separated, and the time domains of respective display periods of the subfields SF 1  through SF 8  are separated. Accordingly, during a given address period, an XY-electrode line pair is kept waiting after being addressed until all of the other XY-electrode line pairs are addressed. Consequently, in each subfield, an address period increases, and a display period decreases. As a result, the brightness of light emitted from a PDP decreases. An existing method proposed for overcoming this problem is an address-while-display driving method as shown in  FIG. 4 . 
     FIG. 4  shows a typical address-while-display driving method with respect to the Y-electrode lines of the PDP  1  shown in  FIG. 1 . Referring to  FIG. 4 , to realize time-division gray scale display, a unit frame is divided into 8 subfields SF 1  through SF 8 . Here, the subfields SF 1  through SF 8  overlap with respect to the Y-electrode lines Y 1  through Y n  and constitute a unit frame. Since all of the subfields SF 1  through SF 8  exist at any time point, address time slots are set among display discharge pulses in order to perform each address step. 
   In each of the subfields SF 1  through SF 8 , a reset step, address step, and display discharge step are performed. A time allocated to each of the subfields SF 1  through SF 8  depends on a display discharge time corresponding to a gray scale. For example, in the case of displaying 256 gray scales with 8-bit image data in units of frames, if a unit frame (usually, 1/60 second) is composed of 256 unit times, the first subfield SF 1  driven according to image data of the least significant bit has 1 (2 0 ) unit time, the second subfield SF 2  has 2 (2 1 ) unit times, the third subfield SF 3  has 4 (2 2 ) unit times, the fourth subfield SF 4  has 8 (2 3 ) unit times, the fifth subfield SF 5  has 16 (2 4 ) unit times, the sixth subfield SF 6  has 32 (2 5 ) unit times, the seventh subfield SF 7  has 64 (2 6 ) unit times, and the eighth subfield SF 8  driven according to image data of the most significant bit has 128 (2 7 ) unit times. Since the sum of unit times allocated to the subfields SF 1  through SF 8  is 255, 255 gray scale display can be accomplished. If a gray scale at which there is no display discharge in any subfield is included, 256 gray scale display can be accomplished. 
     FIG. 5  shows a typical driving apparatus for the PDP  1  shown in  FIG. 1 . Referring to  FIG. 5 , the typical driving apparatus for the PDP  1  includes an image processor  66 , a logic controller  62 , an address driver  63 , an X-driver  64 , and a Y-driver  65 . The image processor  66  converts an external analog image signal into a digital signal to generate an internal image signal composed of, for example, 8-bit red (R) image data, 8-bit green (G) image data, 8-bit blue (B) image data, a clock signal, a horizontal synchronizing signal, and a vertical synchronizing signal. The logic controller  62  generates drive control signals S A , S Y , and S X  in response to the internal image signal from the image processor  66 . The address driver  63  processes the address signal S A  among the drive control signals S A , S Y , and S X  output from the logic controller  62  to generate a display data signal and applies the display data signal to address electrode lines. The X-driver  64  processes the X-drive control signal S X  among the drive control signals S A , S Y , and S X  output from the logic controller  62  and applies the result of processing to X-electrode lines. The Y-driver  65  processes the Y-drive control signal S Y  among the drive control signals S A , S Y , and S X  output from the logic controller  62  and applies the result of processing to Y-electrode lines. 
     FIG. 6  shows driving signals applied to electrode lines according to a conventional address-while-display driving method. In  FIG. 6 , a reference character S X1  denotes a driving signal applied to an X-electrode line of an XY-electrode line pair performing initial resetting and addressing in a unit frame FR 1 , and a reference character S Y1  denotes a driving signal applied to the Y-electrode line of the XY-electrode line pair performing the initial resetting and addressing in the unit frame FR 1 . A reference character S X2  denotes a driving signal applied to an X-electrode line of an XY-electrode line pair performing second resetting and addressing in the unit frame FR 1 , and a reference character S Y2  denotes a driving signal applied to the Y-electrode line of the XY-electrode line pair performing the second resetting and addressing in the unit frame FR 1 . A reference character S Xn  denotes a driving signal applied to an X-electrode line of an XY-electrode line pair performing last resetting and addressing in the unit frame FR 1 , and a reference character S Yn  denotes a driving signal applied to the Y-electrode line of the XY-electrode line pair performing the last resetting and addressing in the unit frame FR 1 . A reference character S A1 . . . m  denotes a display data signal applied from the address driver  63  of  FIG. 5  to all address electrode lines. 
   The conventional address-while-display driving method will be described in detail with reference to  FIG. 6 . 
   As shown in  FIG. 6 , in an address-while-display driving method for a PDP, resetting and addressing are performed on the XY-electrode line pairs X 1 Y 1 , X 2 Y 2 , . . . , X n Y n  while a positive voltage Vsh of a third level and a negative voltage Vs 1  of a first level are alternately applied to all of the X- and Y-electrode lines X 1  through X n  and Y 1  through Y n  shown in  FIG. 1   
   A resetting process includes a line discharge step ta–t 1 , an erasure step tb–tc, and iteration steps. Since a second subfield corresponding to a first XY-electrode line pair starts after a first subfield corresponding to the first XY-electrode line pair performing initial resetting and addressing in a unit frame FR 1 , during a first pulse width period t 0 –t 1 , the negative voltage Vs 1  of the first level is applied to all of the X-electrode lines X 1  through X n , and simultaneously, the positive voltage Vsh of the third level is applied to all of the Y-electrode lines Y 1  through Y n . In the line discharge step ta–t 1 , during the first pulse width period t 0 –t 1 , a negative voltage Vsc of a second level higher than the first level is applied to the X-electrode line X 1  of the first XY-electrode line pair X 1 Y 1 , and simultaneously, a positive voltage Vre of a sixth level higher than the third level is applied to the Y-electrode line Y 1  of the first XY-electrode line pair X 1 Y 1 . Accordingly, discharges are provoked in all display cells corresponding to the first XY-electrode line pair X 1 Y 1 , thereby uniformly forming wall charges and satisfactorily forming space charges. 
   During a second pulse width period t 1 –t 2 , immediately after the first pulse width period t 0 –t 1  during which the line discharge step ta–t 1  is performed, the positive voltage Vsh of the third level is applied to all of the X-electrode lines X 1  through X n , and simultaneously, the negative voltage Vs 1  of the first level is applied to all of the Y-electrode lines Y 1  through Y n , so that wall charges are uniformly formed and space charges are satisfactorily formed in all of the display cells corresponding to the first XY-electrode line pair X 1 Y 1 . 
   In an erasure step performed for a predetermined time tb–tc, during a third pulse width period t 2 –t 3  immediately after the second pulse width period t 1 –t 2 , a positive voltage Veh of a seventh level lower than the third level is applied to the X-electrode line X 1  of the first XY-electrode line pair X 1 Y 1 , and simultaneously, a negative voltage Vel of an eighth level lower than the first level is applied to the Y-electrode line Y 1  of the first XY-electrode line pair X 1 Y 1 . Accordingly, wall charges are erased from all of the display cells corresponding to the first XY-electrode line pair X 1 Y 1 . However, the space charges satisfactorily remain in the display cells. 
   The steps of forming and erasing wall charges are sequentially performed on each of the remaining XY-electrode line pairs (see driving signals S X2  and S Y2  of  FIG. 6 ). 
   In  FIG. 6 , durations td–te, th–ti, and ty–tz are addressing times, during which wall charges are formed in selected display cells, after resetting. These addressing times td–te, th–ti, and ty–tz correspond to times t 3 –t 4 , t 5 –t 6 , and t 2   n+ 1–t 2   n+ 2, respectively, during which the negative voltage Vs 1  of the first level is applied to all of the Y electrode lines Y 1  through Y n . During these addressing times td–te, th–ti, and ty–tz, the negative scan voltage Vsc of the second level higher than the first level is applied to the respective Y-electrode lines of XY-electrode line pairs X 1 Y 1 , X 2 Y 2 , and X n Y n  to be addressed, and simultaneously, positive display data signals are applied to all of the address electrode lines A 1  through A m  shown in  FIG. 1 . Accordingly, opposite discharges occur among the Y-electrode line of an XY-electrode line pair to be addressed and selected address electrode lines, thereby forming positive wall charges around the Y-electrode of selected display cells. In the selected display cells, display discharges are performed in response to pulses due to a wall voltage induced from the wall charges. 
   According to the conventional address-while-display driving method, display voltages that are alternately applied to the X- and Y-electrode lines of each of all XY-electrode line pairs are constant. Accordingly, a voltage that is applied to each XY-electrode line pair is relatively higher during the addressing times td–te, th–ti, and ty–tz than during other times, and thus a maximum of the address voltage Va applied to selected lines among all address electrode lines A 1  through A m  decreases. In other words, an applicable range, i.e., margin, of the address voltage Va is narrowed. When the margin of the address voltage Va is narrowed, display performance may be degraded due to incorrect and inaccurate addressing. 
   SUMMARY OF THE INVENTION 
   To solve the above-described problems, it is an object of the present invention to provide an address-while-display driving method for increasing the margin of an address voltage in a surface discharge type triode PDP in order to increase the accuracy of addressing, thereby increasing display performance. 
   To achieve the above object of the present invention, there is provided an address-while-display driving method of sequentially performing resetting and addressing on each XY-electrode line pair while alternately and consecutively applying display voltages to all XY-electrode line pairs in a surface discharge type triode PDP, which includes a front substrate and a rear substrate that are separately formed to face each other, X- and Y-electrode lines that are alternately arranged in parallel between the front and rear substrates to form the XY-electrode line pairs, and address electrode lines that are formed perpendicular to the X- and Y-electrode lines. The address-while-display driving method of an embodiment of the present invention includes lowering the display voltages during an addressing time for each XY-electrode line pair. 
   According to the address-while-display driving method of an embodiment of the present invention, since a voltage applied to each XY-electrode line pair is lowered during a corresponding addressing time, a maximum of an address voltage that is applied to selected lines among all address electrode lines increases. As a result, the margin of the address voltage increases, and thus accuracy of addressing increases. Consequently, display performance is increased. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above object and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which: 
       FIG. 1  is a perspective view of the internal structure of a typical surface discharge type triode PDP; 
       FIG. 2  is a sectional view of an example of a display cell in the PDP shown in  FIG. 1 ; 
       FIG. 3  is a timing chart of a typical address-display separation driving method with respect to Y-electrode lines of the PDP shown in  FIG. 1 ; 
       FIG. 4  is a timing chart of a typical address-while-display driving method with respect to Y-electrode lines of the PDP shown in  FIG. 1 ; 
       FIG. 5  is a block diagram of a typical driving apparatus for the PDP shown in  FIG. 1 ; 
       FIG. 6  is a timing chart showing driving signals that are applied to electrode lines according to a conventional address-while-display driving method; 
       FIG. 7  is a timing chart showing driving signals that are applied to electrode lines according to an address-while-display driving method according to a first embodiment of the present invention; 
       FIG. 8  is a circuit diagram of X- and Y-drivers that can perform the address-while-display driving method of  FIG. 7 ; 
       FIG. 9  is a timing chart showing driving signals that are applied to electrode lines according to an address-while-display driving method in a second embodiment of the present invention; 
       FIG. 10  is a circuit diagram of X- and Y-drivers which can perform the address-while-display driving method of  FIG. 9 ; and 
       FIG. 11  is a graph showing the margin of an address voltage with respect to a voltage Vpb shown in  FIG. 7 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 7  shows driving signals that are applied to electrode lines according to an address-while-display driving method according to a first embodiment of the present invention. In  FIGS. 6 and 7 , the same reference characters denote the same functional element.  FIG. 8  shows X- and Y-drivers that can perform the address-while-display driving method of  FIG. 7 . In  FIG. 8 , a circuit at the left side of a PDP  1  corresponds to the Y-driver  65  shown  FIG. 5 , and a circuit at the right side of the PDP  1  corresponds to the X-driver  64  shown  FIG. 5 . 
   Referring to  FIG. 8 , the Y-driver  65  of  FIG. 5  includes upper transistors YU 1  through YU n , lower transistors YL 1  through YL n , a Y-energy regeneration circuit ER Y , a Y-display discharge circuit SP Y , and a Y-resetting/addressing circuit RA. The upper transistors YU 1  through YU n  and the lower transistors YL 1  through YL n  are connected to Y-electrode lines Y 1  through Y n . The Y-energy regeneration circuit ER Y  collects charges around the Y-electrode lines Y 1  through Y n  during the falling time of display discharge pulses simultaneously applied from the Y-display discharge circuit SP Y  to the Y-electrode lines Y 1  through Y n  and applies the collected charges to the Y-electrode lines Y 1  through Y n  during the rising time of the display discharge pulses. The Y-display discharge circuit SP Y  alternately applies a positive voltage Vsh of a third level and a negative voltage Vs 1  of a first level to the Y-electrode lines Y 1  through Y n . The Y-energy regeneration circuit ER Y  and the Y-display discharge circuit SP Y  are commonly applied to all of the Y-electrode lines Y 1  through Y n  through the upper transistors YU 1  through YU n . The Y-resetting/addressing circuit RA outputs voltages Vre and Vel for resetting according to the present invention and a voltage Vsc for addressing during resetting time and addressing time for each Y-electrode line. Accordingly, the Y-resetting/addressing circuit RA is independently applied to each of the Y-electrode lines Y 1  through Y n  through each of the lower transistors YL 1  through YL n . 
   Similarly, the X-driver  64  of  FIG. 5  includes upper transistors XU 1  through XU n , lower transistors XL 1  through XL n , an X-energy regeneration circuit ER X , an X-display discharge circuit SP X , and an X-resetting circuit RE. The upper transistors XU 1  through XU n  and the lower transistors XL 1  through XL n  are connected to X-electrode lines X 1  through X n . The X-energy regeneration circuit ER X  collects charges around the X-electrode lines X 1  through X n  during the falling time of display discharge pulses simultaneously applied from the X-display discharge circuit SP X  to the X-elcctrode lines X 1  through X n  and applies the collected charges to the X-electrode lines X 1  through X n  during the rising time of the display discharge pulses. The X-display discharge circuit SP X  alternately applies the positive voltage Vsh of the third level plus a positive voltage Vpb of a fourth level and the negative voltage Vs 1  of the first level to the X-electrode lines X 1  through X n . The X-energy regeneration circuit ER X  and the X-display discharge circuit SP X  are commonly applied to all of the X-electrode lines X 1  through X n  through the upper transistors XU 1  through XU n . The X-resetting circuit RE outputs voltages Veh and Vsc for resetting according to the present invention during resetting time for each X-electrode line. Accordingly, the X-resetting circuit RE is independently applied to each of the X-electrode lines X 1  through X n  through each of the lower transistors XL 1  through XL n . 
   An address-while-display driving method according to an embodiment of the present invention will be described in detail with reference to  FIGS. 7 and 8 . 
   As shown in  FIG. 7 , in an address-while-display driving method for a PDP  1 , resetting and addressing are performed on the XY-electrode line pairs X 1 Y 1 , X 2 Y 2 , . . . , X n Y n  while the positive voltage Vsh of the third level plus the positive voltage Vpb of the fourth level and the negative voltage Vs 1  of the first level are alternately applied to all of the X- and Y-electrode lines X 1  through X n  and Y 1  through Y n . 
   A resetting process includes a line discharge step ta–t 1 , an erasure step tb–tc, and iteration steps. Since a second subfield corresponding to a first XY-electrode line pair starts after a first subfield corresponding to the first XY-electrode line pair performing initial resetting and addressing in a unit frame FR 1 , during a first pulse width period t 0 –t 1 , the negative voltage Vs 1  of the first level is applied to all of the X-electrode lines X 1  through X n , and simultaneously, the positive voltage Vpb of the third level is applied to all of the Y-electrode lines Y 1  through Y n . In the line discharge step ta–t 1 , during the first pulse width period t 0 –t 1 , the upper transistors (for example, XU 1  and YU 1 ) of the first XY-electrode line pair (for example, X 1 Y 1 ) are turned off, the lower transistors (for example, XL 1  and YL 1 ) thereof are turned on, a transistor ST 13  of the X-resetting circuit RE is turned on, and a transistor ST 5  of the Y-resetting/addressing circuit RA is turned on. As a result, the negative voltage Vsc of a second level higher than the first level is applied to the X-electrode line X 1  of the first XY-electrode line pair X 1 Y 1 , and simultaneously, a positive voltage Vre of a sixth level higher than the third level is applied to the Y-electrode line Y 1  of the first XY-electrode line pair X 1 Y 1 . Accordingly, discharges are provoked in all discharge cells corresponding to the first XY-electrode line pair X 1 Y 1 , thereby uniformly forming wall charges and satisfactorily forming space charges. 
   During a first time t 1 –t 1   a  of a second pulse width period t 1 –t 2 , immediately after the first pulse width period t 0 –t 1  during which the line discharge step ta–t 1  is performed, the upper transistors XU 1  through YU n  of all of the XY-electrode line pairs X 1 Y 1  through X n Y n  are turned on, the lower transistors XL 1  through YL n  thereof are turned off, a transistor ST 10  of the X-display discharge circuit SP X  is turned on, and a transistor ST 4  of the Y-display discharge circuit SP Y  is turned on. As a result, the positive voltage Vsh of the third level is applied to all of the X-electrode lines X 1  through X n , and simultaneously, the negative voltage Vs 1  of the first level is applied to all of the Y-electrode lines Y 1  through Y n , so that wall charges are uniformly formed and space charges are satisfactorily formed in all of the discharge cells corresponding to the first XY-electrode line pair X 1 Y 1 . 
   An operation performed during a second time t 1   a –t 2  is different from the operation performed during the first time t 1 –t 1   a  in that a transistor ST 10   a , instead of the transistor ST 10  in the X-display discharge circuit SP X , is turned on so that the positive voltage Vpb of the fourth level lower than the positive voltage Vsh of the third level is applied to all of the X-electrode lines X 1  through X n . The reason a display voltage applied to the X-electrode lines X 1  through X n  is lowered will be described in detail when describing an addressing operation below. 
   In an erasure step performed for a predetermined time tb–tc, during a third pulse width period t 2 –t 3  immediately after the second pulse width period t 1 –t 2 , the upper transistors XU 1  and YU 1  of the first XY-electrode line pair X 1 Y 1  are turned off, the lower transistors XL 1  and YL 1  thereof are turned on, a transistor ST 12  of the X-resetting circuit RE is turned on, and a transistor ST 7  of the Y-resetting/addressing circuit RA is turned on. As a result, a positive voltage Veh of a seventh level lower than the fourth level is applied to the X-electrode line X 1  of the first XY-electrode line pair X 1 Y 1 , and simultaneously, a negative voltage Vel of an eighth level lower than the first level is applied to the Y-electrode line Y 1  of the first XY-electrode line pair X 1 Y 1 . Accordingly, wall charges are erased from all of the discharge cells corresponding to the first XY-electrode line pair X 1 Y 1 . However, the space charges satisfactorily remain in the discharge cells. 
   The steps of forming and erasing wall charges are sequentially performed on each of the remaining XY-electrode line pairs (see driving signals S X2  and S Y2  of  FIG. 7 ). 
   In  FIG. 7 , durations td–te, th–ti, and ty–tz are addressing times, during which wall charges are formed in selected display cells, after resetting. These addressing times td–te, th–ti, and ty–tz correspond to pulse width periods t 3 –t 4 , t 5 –t 6 , and t 2   n+ 1–t 2   n+ 2, respectively, during which the negative voltage Vs 1  of the first level is applied to all of the Y-electrode lines Y 1  through Y n . Each of the pulse width periods t 3 –t 4 , t 5 –t 6 , and t 2   n+ 1–t 2   n+ 2, during which addressing is performed, is divided into a first time t 3 –t 3   a , t 5 –t 5   a , or t 2   n +1–t 2   n +1a, respectively, that does not include an addressing time and a second time t 3   a –t 4 , t 5   a –t 6 , or t 2   n +1a–t 2   n+ 2, respectively, that includes an addressing time. 
   During the first time t 3 –t 3   a , t 5 –t 5   a , or t 2   n+ 1–t 2   n +1 a  that does not include an addressing time, the upper transistors XU 1  through YU n  of all of the XY-electrode line pairs X 1 Y 1  through X n Y n  are turned on, the lower transistors XL 1  through YL n  thereof are turned off, the transistor ST 10  of the X-display discharge circuit SP X  is turned on, and the transistor ST 4  of the Y-display discharge circuit SP Y  is turned on. As a result, the positive voltage Vsh of the third level is applied to all of the X-electrode lines X 1  through X n , and simultaneously, the negative voltage Vs 1  of the first level is applied to all of the Y-electrode lines Y 1  through Y n . 
   An operation performed during the second time t 3   a –t 4 , t 5   a –t 6 , or t 2   n +1a–t 2   n+ 2 is different from the operation performed during the first time t 3 –t 3   a , t 5 –t 5   a , or t 2   n+ 1–t 2   n +1 a  in that the transistor ST 10   a , instead of the transistor ST 10  in the X-display discharge circuit SP X , is turned on so that the positive voltage Vpb of the fourth level lower than the positive voltage Vsh of the third level is applied to all of the X-electrode lines X 1  through X n . 
   During the addressing times td–te, th–ti, and ty–tz included in the second times t 3   a –t 4 , t 5   a –t 6 , and t 2   n +1a–t 2   n+ 2, respectively, the lower transistors of the respective Y-electrode lines of XY-electrode line pairs X 1 Y 1 , X 2 Y 2 , and X n Y n  and a transistor ST 6  of the Y-resetting/addressing circuit RA are turned on. Accordingly, the negative scan voltage Vsc of the second level higher than the first level is applied to the Y-electrode line of each XY-electrode line pair to be addressed, and simultaneously, positive display data signals are applied to all of the address electrode lines A 1  through A m  shown in  FIG. 1 . Accordingly, opposite discharges occur among the Y-electrode line of an XY-electrode line pair to be addressed and selected address electrode lines, thereby forming positive wall charges around the Y-electrode of selected display cells. In the selected display cells, display discharges are performed in response to pulses due to a wall voltage induced from the wall charges. 
   During the above-described addressing times td–te, th–ti, and ty–tz, the voltage Vpb, lower than the voltage Vsh applied during the first times t 3 –t 3   a , t 5 –t 5   a , and t 2   n +1t 2   n +1a, is applied to all of the X-electrode lines X 1  through X n . Accordingly, a voltage that is applied to an XY-electrode line pair during each of the addressing times td–te, th–ti, and ty–tz is lowered so that a maximum of an address voltage Va that is applied to selected lines among the address electrode lines A 1  through A m  increases. In other words, an applicable range, i.e., margin, of the address voltage Va is broadened. When the margin of the address voltage Va is broadened, accurate addressing can be accomplished, thereby increasing display performance. 
     FIG. 9  shows driving signals that are applied to electrode lines in an address-while-display driving method according to a second embodiment of the present invention. In  FIGS. 7 and 9 , the same reference characters denote the same functional element.  FIG. 10  shows X- and Y-drivers that can perform the address-while-display driving method of  FIG. 9 . In  FIGS. 8 and 10 , the same reference characters denote the same functional element. The circuit shown in  FIG. 10  is different from the circuit shown in  FIG. 8  in that the circuit of the transistor ST 10   a , which is provided for applying the positive voltage Vpb of the fourth level to all of the X-electrode lines X 1  through X n  in  FIG. 8 , is removed and that the circuit of a transistor ST 4   a  for applying a negative voltage Vnb of a fifth level lower than the first level to all of the Y-electrode lines Y 1  through Y n  is added. 
   Differences between the first embodiment shown in  FIGS. 7 and 8  and the second embodiment shown in  FIGS. 9 and 10  will be described in detail below. 
   During the second times t 3   a –t 4 , t 5   a –t 6 , and t 2   n +1a–t 2   n+ 2 including an addressing time, instead of applying the positive voltage Vsh, which is applied during the first times t 3 –t 3   a , t 5 –t 5   a , and t 2   n +1–t 2   n +1a, to all of the X-electrode lines X 1  through X n , the negative voltage Vnb of the fifth level lower than the negative voltage Vs 1 , which is applied during the first times t 3 –t 3   a , t 5 –t 5   a , and t 2   n +1–t 2   n +1a, is applied to all of the Y-electrode lines Y 1  through Y n  by turning on the transistor ST 4   a  of the Y-display discharge circuit SP Y . 
   Accordingly, a voltage that is applied to an XY-electrode line pair during each of the addressing times td–te, th–ti, and ty–tz is lowered so that a maximum of an address voltage Va that is applied to selected lines among the address electrode lines A 1  through A m  increases. In other words, an applicable range, i.e., margin, of the address voltage Va is broadened. When the margin of the address voltage Va is broadened, accurate addressing can be accomplished, thereby increasing display performance. 
     FIG. 11  shows the margin Amar of the address voltage Va with respect to the voltage Vpb shown in  FIG. 7 . Here, the voltage Vpb indicates a display voltage that is applied to all of the X-electrode lines X 1  through X n  according to an address-while-display driving method. In  FIG. 11 , a reference character Cmin denotes a characteristic curve of a minimum of the address voltage Va with respect to the voltage Vpb, and a reference character Cmax denotes a characteristic curve of a maximum of the address voltage Va with respect to the voltage Vpb. 
   Referring to  FIG. 11 , when the voltage Vpb is set to a high level according to conventional technology, a maximum of the address voltage Va is very low, and thus the margin Amar of the address voltage Va is narrowed. When the voltage Vpb is set to a low level according to an embodiment of the present invention, however, the margin Amar of the address voltage Va is broadened. It will be apparent that it is not necessary to remarkably increase a minimum of the address voltage Va by setting the voltage Vpb to a very low level. 
   As described above, according to an address-while-display driving method for a PDP according to the present invention, since a voltage applied to an XY-electrode line pair is lowered during an addressing time, a maximum of an address voltage that is applied to selected lines among all address electrode lines increases. As a result, the margin of the address voltage increases, and thus accuracy of addressing increases, thereby increasing display performance. 
   The present invention is not restricted to the above-described embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.