Abstract:
A new single-stage, single-switch, input-current-shaping technique which combines the boost-like input-current shaper with a continuous-conduction-mode dc/dc output stage is described. Due to the ability to keep a relatively low voltage (&lt;450 Vdc) on the energy-storage capacitor, this technique is suitable for the universal line-voltage applications. The voltage on the energy-storage capacitor is kept within the desirable range by the addition of two transformer windings. One winding appears in series with the boost inductor during the on time, whereas the other winding appears in series with the same inductor during the off time. By connecting the windings so that the voltages across them when they conduct the inductor current are in opposition to the input voltage, the volt-second balance of the boost-inductor core is achieved at a substantially lower voltage of the energy-storage capacitor compared to the other known approaches. In addition, for the forward-converter-type single-stage, single-switch input-current shapers, a direct transfer of a part of the input energy is achieved by the winding which appears in series with the boost inductor during the on time, while for the flyback implementation a direct transfer of a part of the input energy is achieved by the winding which appears in series with the boost inductor during the off time.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This is a continuation-in-part of application Ser. No. 08/669,001 filed June 21, 1996 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to an improved single-stage, single-switch, isolated power-supply technique with input-current shaping and fast output-voltage regulation and, more particularly, to circuit topology which reduces the maximum voltage on the energy- storage capacitor. 
     2. Description of the Prior Art 
     A number of standards regulate the harmonic content of the line current drawn from the ac mains by a piece of electronic equipment. The specific requirements of these standards depend on the type of the equipment and its power level (see, Electromagnetic Compatibility (EMC) - Part 3: Limits - Section 2: Limits for harmonic current emissions (equipment input current ≦16 A per phase), IEC 1000-3-2 Document, First Edition, 1995). To comply with these standards, input-current shaping (ICS) of off-line power supplies is necessary. So far, a variety of passive and active ICS techniques have been proposed in the prior art. While passive techniques can be the best choice in many cost-sensitive applications, the active ICS techniques are used in the majority of applications due to their superior performance. 
     The most commonly used active approach, which meets high power-quality requirements, is a &#34;two-stage&#34; approach (see L. H. Dixon, Jr., &#34;High power factor preregulators for off-line power supplies,&#34; Unitrode Switching Regulated Power Supply Design Seminar Manual, Paper I2, SEM-700, 1990). In this approach, a non-isolated boost-like converter, which is controlled so that the rectified line current follows the rectified line voltage, is used as the input stage that creates an intermediate dc bus with a relatively large second-harmonic ripple. This first ICS stage is then followed by a dc/dc converter which provides isolation and high-bandwidth voltage regulation. For high-power levels, the ICS stage is operated in the continuous-conduction mode (CCM), while the discontinuous-conduction-mode (DCM) operation is commonly used at lower power levels due to a simpler control. 
     Although relatively simple, mature, and viable in wide power-range applications, the two-stage approach suffers from several drawbacks. First, due to two-stage power processing, conversion efficiency is reduced. Second, a separate ICS stage adds components and complexity and, consequently, increases the cost. The cost increase is especially undesirable for low-power supplies used in consumer electronic products such as, for example, personal computers, low-end printers, home appliances, etc. 
     In an effort to reduce the component count and also improve the performance, a number of &#34;single-stage&#34; ICS techniques have been introduced recently (see M. Madigan, R. Erickson, E. Ismail, &#34;Integrated high-quality rectifier-regulators,&#34; IEEE Power Electronics Specialists Conf. (PESC) Record, pp. 1043-1051, June 1992; L. D. Stevanovic, S. Cuk,. &#34;Input current shaping and regulation of multiple outputs in a single isolated converter,&#34; IEEE International Telecommunication Energy Conf. (INTELEC) Proc., pp. 326-333, September 1993; M. Brkovic, S. Cuk, &#34;Novel Single Stage AC-to-DC Converters with Magnetic Amplifiers and High Power Factor,&#34; IEEE Applied Power Electronics Conference (APEC) Proc., pp. -453, March 1995; R. Redl, L. Balogh, &#34;Design Considerations for Single-Stage Isolated Power-Factor-Corrected Power Supplies with Fast Regulation of the Output Voltage,&#34; IEEE Applied Power Electronics Conference (APEC) Proc., pp. 454-458, March 1995; and H. Watanabe, Y. Kobayashi, Y. Sekine, M. Morikawa, T. Ishii, &#34;The Suppressing Harmonic Currents, MS (Magnetic-Switch) Power Supply,&#34; IEEE International Telecommunication Energy Conf. (INTELEC) Proc., pp. 783-790, October 1995). In a single-stage approach, input-current shaping, isolation, and high-bandwidth control are performed in a single step, i.e., without creating an intermediate dc bus. Generally, these converters use an internal energy-storage capacitor to handle the differences between the varying instantaneous input power and a constant output power. 
     Among the single-step circuits, a number of prior art circuits described in Madigan, Brkovic and Watanabe and shown in FIGS. 1 through 3 seem particularly attractive because they can be implemented with only one semiconductor switch and a simple control. FIGS. 1 and 3 show the forward-converter implementations of the single-stage, single-switch (S 4 ) ICS concepts described in Madigan and Watanabe, while FIG. 2 shows the Cuk-converter implementation of the idea introduced in Brkovic. Except for the circuit in FIG. 3, all other S 4  ICS circuits employ the DCM boost converter in the ICS stage. In fact, in these circuits, low input-current harmonic distortions are achieved through the inherent property of the DCM boost converter to draw a near sinusoidal current if its duty cycle during a line period is held relatively constant. 
     While boost inductor L 1  in the ICS stage of the converter in FIG. 1 must operate in DCM (i.e., during a part of a switching cycle the current in L 1  has to be zero), output inductor L 2  can be designed to operate either in DCM or CCM. According to the analysis in Redl, if L 2  operates in CCM, the voltage on energy-storage capacitor C B  shows a strong dependence on the line voltage and output current. In fact, the energy-storage-capacitor voltage increases as the rms of the line voltage increases and/or output current decreases. When the load current is decreased while L 2  operates in CCM, the duty cycle will not change in direct response to the change of the current. Because initially the duty cycle stays constant, the input source will add more charge to energy-storage capacitor C B  than the charge withdrawn from the capacitor by the load. As a result, the energy-storage capacitor voltage will increase, forcing the voltage control loop to decrease the duty cycle so that a new charge balance is established at a higher energy-storage-capacitor voltage. As explained in Redl, for a converter in FIG. 1 designed for universal line-voltage range from 90 Vac to 270 Vac, the voltage on C B  can exceed 1000 Vdc at high line voltage and light load current if L 2  operates in CCM. As a result, the approach proposed in Madigan is not practical for applications with the universal line-voltage range. The voltage stress on the energy-storage capacitor can be substantially reduced by employing the variable switching-frequency CVSF) control as described in M. M. Jovanovic, D.M.C. Tsang, F. C. Lee, &#34;Reduction of Voltage Stress in Integrated High-Quality Rectifiers-Regulators by Variable-Frequency Control,&#34; IEEE Applied Power Electronics Conference (APEC) Proc., pp. 569-575, March 1994. However, even with a wide-range of switching frequency, the energy-storage capacitor voltage cannot be kept below 500 Vdc. As a result, energy-storage capacitors with voltage ratings above 600 Vdc must be used. This makes the circuit in FIG. 1 and any other S 4  ICS circuit using the same approach impractical because high-voltage-rated storage capacitors are more expensive and bulky compared to desirable 450-V-rated capacitors which are typically used in conventional ICSs. The voltage on C B  in the circuit in FIG. 1 can be kept below 450 Vdc only if output inductor L 2  is designed to operate in DCM. As explained in Redl, in that case the voltage on C B  is independent of the load current. However, for low-voltage, high-current applications, the DCM operation of L 2  is not desirable because it results in much higher stresses in semiconductor components compared to the CCM operation. 
     The circuit in FIG. 2 can also operate with inductor L 2  in CCM. Because Magnetic Amplifier (MagAmp) MA1 operates as a switch, the output-voltage control and energy-storage capacitor voltage control can be done with two independent loops. Voltage across energy-storage capacitor C str  in this circuit is kept within the desired voltage range (&lt;450 Vdc) by a slow MagAmp regulation loop, while the semiconductor switch is used in the fast output-voltage regulation loop. In addition, another fast control loop is used to shape the input current. The major drawbacks of this approach are the complexity of control and the need for a relatively expensive square-loop magnetic material for the implementation of the MagAmp. In addition, the energy transfer in the circuit in FIG. 2 is done through capacitor C 3 , which is a less desirable energy-transfer mechanism than the energy transfer through a rectifier. 
     The circuit in FIG. 3 employs the Magnetic-Switch (MS) concept to achieve ICS with CCM operation of both ICS inductor L 1  and output-filter inductor L,. The MS is implemented with an additional winding of the transformer so that its voltage is proportional to the primary-winding voltage. The MS winding is connected in the circuit with the polarity in opposition to the energy-storage capacitor voltage when the switch is on. As a result, when the switch is on, a substantial voltage is applied to the series combination of C 1  and choke L 1  forcing the flow of the input current. When the switch is off, the L 1  energy is discharged to capacitor C in  through diode D 1 , while the transformer is reset through the resonance of its magnetizing inductance L m  and capacitor C 1 . Since the MS is not independently controllable, but it is controlled by the primary switch, this circuit suffers from a relatively high voltage on C in  even when a VSF control is employed, as reported in Watanabe. 
     Finally, it should be noted that in the forward-converter S 4  ICSs in FIGS. 1 and 3 no energy is directly transferred from the input to the output. In fact, during the switch on time, the input energy is stored in the boost choke first, and then transferred to the energy-storage capacitor during the subsequent off time of the switch. The energy transferred to the output during the on time of the switch is the energy stored in the capacitor. The efficiency of the operation would be improved if a part of the energy is directly transferred to the output. 
     SUMMARY OF THE INVENTION 
     An object of this invention is a new S 4  ICS technique which combines the boost-like ICS with a CCM dc/dc output stage coupled with an ability to keep a relatively low voltage (&lt;450 Vdc) on the energy-storage capacitor, making this technique suitable for the universal line-voltage applications. 
     Briefly, this invention contemplates the provision of a single-stage, single-switch, isolated power-supply technique with input-current shaping and fast output-voltage regulation in which the voltage on the energy-storage capacitor is kept within a desirable range by the addition of two transformer windings. One winding appears in series with the boost inductor during the on time, whereas the other winding appears in series with the same inductor during the off time. These two additional transformer windings are connected so that the voltages across them, when they conduct the (boost) inductor current, are in opposition to the input voltage, so that the volt-second balance of the boost-inductor core is achieved at a substantially lower voltage of the energy-storage capacitor compared to the other known prior art approaches. In addition, for the forward-converter-type S 4  ICSs, a direct transfer of a part of the input energy is achieved by the winding which appears in series with the boost inductor during the on time. Likewise, for the flyback-type S 4  ICSs, a direct transfer of a part of the input energy is achieved by the winding which appears in series with the boost inductor during the off time. 
     Although, in the next section, the invention is described for the forward-converter implementation, this technique can be applied to any other single-ended, single-switch, isolated, single- or multiple-output topology such as the flyback, Cuk, sepic, zeta, and other converters. Furthermore, the concept described in this invention can be extended to &#34;hard-switched&#34; and &#34;soft-switched&#34; multi-switch converters such as two-switch forward and flyback converters, as well as the bridge-type topologies. 
     The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which: 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic drawing of a prior art forward-converter implementation of the S 4  ICS. 
     FIG. 2 is a schematic drawing of a prior art Cuk-converter implementation of the S 4  ICS. 
     FIG. 3 is a schematic drawing of a prior art forward-converter implementation of the S 4  ICS. 
     FIG. 4 is a schematic drawing of a specific embodiment of an S 4  ICS forward converter proposed in this invention. 
     FIG. 5a-c shows the topological stages of the S 4  ICS forward converter withL B  operating in DCM shown in FIG. 4. 
     FIG. 6 shows the key waveforms of the S 4  ICS forward converter withL B  operating in DCM shown in FIG. 4. 
     FIG. 7 shows the line voltage and current waveforms of the S 4  ICS forward converter with L B  operating in DCM shown in FIG. 4. 
     FIG. 8a-e shows the topological stages of the S 4  ICS forward converter with L B  operating in CCM. 
     FIG. 9a-g shows the key waveforms of the S-ICS forward converter with L B  operating in CCM. 
     FIG. 10 shows the line voltage and current waveforms of the S 4  ICS forward converter with L B  operating in CCM. 
     FIG. 11 is a circuit diagram of a flyback implementation of the S 4  ICS using the concept described in this invention. 
     FIG. 12a and b shows oscillograms of line voltage and current of DCM implementation of experimental converter. 
     FIG. 13a and b shows oscillograms of line voltage and current of CCM implementation of experimental converter. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 4 shows a circuit diagram of an S 4  ICS in accordance with this invention which combines a boost-converter input stage with a CCM forward-converter output stage. In FIG. 4, the core of transformer T 1  is reset by reset winding N R . Transformer windings N 1  and N 2  are used to reduce the voltage of energy-storage capacitor C B . In addition, winding N 1  is utilized for the direct energy transfer from the input to the output. Inductances L 1k1  and L 1k2  represent the leakage inductances of windings N 1  and N 2 , respectively. A small input capacitor C in  is used to filter out the switching-frequency ripple of the ICS-inductor current. Consequently, the rectified line current is the average of the current flowing from ICS inductor L B . 
     One side (node X) of boost inductor L B  is coupled to full-wave rectified input v in   rec . Winding N 2  of isolation transformer T 1  is coupled, via diode D 2 , between the other side (node Y) of boost inductor L B  and one side of primary winding N P  of isolation transformer T 1 . Winding N 1  of isolation transformer T 1  is coupled, via diode D 1 , between node Y and the other side of primary winding N P . The control circuit, as in prior art S 4  ICS circuits, controls the opening and closing of a semiconductor switch SW in order to maintain a desired output voltage V o  across load R L . Output inductor L B  and diode D F  couple secondary winding N S  of transformer T 1  to load R L . Filter capacitor C F  is connected across load R L . Free wheeling diode D FW  provides a conduction path for output inductor L F  when the switch SW is off. 
     In operation, when switch SW is closed, the polarity of winding N 1  is such that the induced voltage across N 1  is in opposition to rectified input voltage v in   rec . This reduces the volt-second product across boost inductor L B  during on time (i.e. switch closed) of switch SW, and hence reduces the energy stored in boost inductor L B  compared to a corresponding circuit without winding N 1 . This in turn reduces the voltage of energy storage capacitor C B  needed to reset the core of boost inductor L B  during the switch off time. In addition, it should be noted that during the switch on time, winding N 1  couples input power to the load. Transformer winding N 2  is in series between the boost inductor L B  and the energy storage capacitor when switch SW is open. The polarity of N 2  is such, that during the switch open time, N 2  &#39;s induced voltage opposes rectified input voltage v in   rec  and aids the reset of L B , thus further reducing voltage V B  across the energy storage capacitor necessary to reset boost inductor L B . 
     To simplify the analysis, it is assumed that all semiconductor components are ideal. According to this assumption, the primary switch and the rectifiers do not have parasitic capacitances and represent ideal short and open circuits in their on and off states, respectively. Finally, in the following analysis, the input voltage of the converter is considered constant during a switching cycle because the switching frequency is much higher than the line frequency. 
     To further simplify the explanation of the circuit operation, it is assumed that the inductance of ICS inductor L B  in FIG. 4 is small so that inductor L B  operates in DCM, and that the inductance of output-filter inductor L F  is large enough so, that inductor L F  operates in CCM. Since in the DCM operation, the leakage inductances of the auxiliary windings N 1  and N 2  have no effect on the circuits operation, they are neglected in the following analysis by assuming that L 1k1  =L 1k2  = ). To facilitate the analysis of operation, FIGS. 5 and 6 stages of the converter during a switching cycle and its key waveforms, respectively. 
     Due to the DCM operation of L B  and the CCM operation of L F , at the moment immediately before primary switch SW is turned on, current i LB  is zero, while current i LF  is freewheeling through freewheeling diode D FW , inductor L F , and the output. When switch SW is closed at t=T 0 , current i LB  starts flowing through transformer winding N 1 , rectifier D 1 , and switch SW, as shown in FIG. 5(a). The slope of this current is determined by ##EQU1## where v in   rec  is the instantaneous rectified line voltage for the switching cycle commencing at t=T 0 , N 1  is the number of turns of auxiliary winding N 1 , N p  is the number of turns of the primary winding, and V B  is the energy-storage (bulk) capacitor voltage. 
     Also, at t=T 0 , output-filter inductor current i LF  is commutated from freewheeling diode D FW  to forward diode D F  because of the induced positive secondary voltage. The rate of the increase of current i LF  =i S  is given by ##EQU2## where N S  is the number of secondary turns. 
     Finally, during the on time of the switch, transformer magnetizing current i M  increases according to ##EQU3## where L M  is the magnetizing inductance. 
     From FIG. 5(a), during the on time, switch current i SW  is given by the sum of ICS-inductor current i LB , primary-winding current i P , and magnetizing current i M , i.e., 
     
         i.sub.SW =i.sub.LB +ip+i.sub.M.                            (4) 
    
     To help visualize the components of switch current i SW , FIG. 6 uses different hatching patterns for each component. 
     Also, from FIG. 5(a) and Ampere&#39;s law, the currents flowing in the transformer are related as 
     
         Npip+N.sub.1 i.sub.LB -N.sub.s i.sub.s =i.sub.M            (5) 
    
     By neglecting magnetizing current i M  in Eq. 5 because it is much smaller compared to the other currents, secondary current i s  during on time can be expressed as ##EQU4## From Eq. 6, it can be seen that the secondary current, which during on time supplies output energy, is composed of two components which obtain energy from different sources. The energy transferred to the secondary which is associated with primary current i P  is obtained from the discharging energy-storage capacitor C B , while the energy associated with ICS inductor current i LB  is drawn directly from the input line. The hatched areas in the i LF  waveform in FIG. 6 indicate the two current components. 
     When primary switch SW is turned off at t=T 1 , primary current i P  and, consequently, secondary current i s  cease to flow. As a result, i LF  is commutated into freewheeling rectifier D FW , as shown in FIG. 5(b). Due to the negative voltage V o  applied across L F , i LF  decreases during this interval. Also, at t=T 1 , current i LB , which was flowing through switch SW, is diverted to energy-storage capacitor C B , as indicated in FIG. 5(b). The downslope of i LB  is given by ##EQU5## Since during off time, i LB  needs to decrease to zero to completely reset the L B  core, the voltage applied across L B  must be negative, i.e., 
     
         (1+N.sub.2 /N.sub.R)V.sub.B &gt;v.sub.in.sup.rec              (8) 
    
     From Eq. 7, it can be seen that with winding N 2  the required reset voltage for L B  can be obtained with a smaller V B  because of induced voltage (N 2  /N R )V B  across winding N 2 . 
     The reset of the transformer core is done by reset winding N R . Namely, after switch SW is turned off, the magnetizing current is transferred to this winding. In addition, the reset winding also carries reflected input current i LB  because of the magnetic coupling between windings N 2  and N R . According to Ampere&#39;s law, reset winding current is given by ##EQU6## As it can be seen from FIG. 5(b), during the off time, energy stored in L B  is discharged to C B  through two paths. One path is the direct path through rectifier D 2 , whereas the other path is the indirect path through the reset winding. The ratio of the directly and indirectly discharged energy is determined by turns ratio N 2  /N R . In FIG. 6, the energy stored in L B  completely discharges at t=T 2 . 
     Finally, during the reset of the transformer, the voltage stress on switch SW is ##EQU7## When the flux in the core of the transformer is completely reset at t=T 3 , the voltage across the transformer collapses to zero and reflected magnetizing current (N P  /N s )i M  starts flowing through the secondary, as indicated in FIG. 5(c). The topological stage in FIG. 5(c) lasts until the initiation of the next switching cycle. 
     It should be noted that in FIG. 6 the energy stored in L B  is discharged (i LB  falls to zero at t=T 2 ) before the reset of the transformer is completed at t=T 3 . However, the operation of the circuit remains unchanged if the transformer reset is completed before L B  is completely discharged. 
     To ensure a proper operation of the circuit, the number of turns of windings N 1  and N 2  must be selected so that rectifier D 2  is off during the time switch SW is closed. From FIG. 4, this condition requires that ##EQU8## 
     To maximize the direct energy transfer, it is desirable to select ratio N 1  /N P  large as possible. However, a larger ratio causes larger input-current harmonic distortions, as illustrated in FIG. 7. Namely, i LB  current, and therefore, the input current, can not flow until the line voltage, exceeds the N 1  -winding voltage (N 1  /N P )V B . Therefore, by increasing N 1  /N P , the zero-crossing distortions are Increased due to a larger dead angle, i.e., a longer period with i LB  =0. The dead angle, θ, can be calculated from ##EQU9## where V in  is the rms input voltage. The relationships between θ and total harmonic distortions (THD) is discussed in M. K. Nablant, &#34;Power Factor Calculations and Measurements,&#34; IEEE Applied Power Electronics Conference (APEC) Proc., pp. 543-552, March 1990. In addition to these crossover harmonic distortions, the input current contains the harmonic distortions caused by the finite downslope of i LB , as explained and quantified in K. H. Liu, Y. L. Lin, &#34;Current Waveform Distortion in Power Factor Correction Circuits Employing Discontinuous-Mode Boost Converters,&#34; IEEE Power Electronics Specialists Conf. (PESC) Record, pp. 825-829, June 1989. Generally, these distortions decrease as the i LB  downslope increases. As a rule of thumb, to meet current harmonic-limit specifications (defined in the IEC 1000-3-2 document) dead angle θ should not exceed 45°. 
     During the time interval where the instantaneous line voltage exceeds the induced voltage on winding N 1 , the peak of current i LB  is given by ##EQU10## where ω L  is the line frequency (50 or 60 Hz), ∫s is the switching frequency, and D is the duty cycle. The average of i LB  represents the rectified input current, as illustrated in FIG. 7. 
     The duty cycle of the switch is determined by the fast (wide-bandwidth) output-voltage control loop. If the voltage ripple on C B  is small, the duty cycle is essentially constant during a half of a line cycle. Due to the CCM operation of the output-filter inductor, duty cycle D is given by ##EQU11## 
     To use the above equations, energy-storage-capacitor voltage V B  needs to be known. By applying the input-output power balance principle to the circuit in FIG. 4, this voltage can be expressed in an implicit form as ##EQU12## where θ is the assumed efficiency of the converter and I o  is the output (load) current. 
     As it can be concluded by inspecting Eq. 16, V B  increases as the line voltage increases and/or the output current decreases. Therefore, V B  is the highest at high line and light load. Depending on the minimum load specifications, V B  may exceed the desired voltage level (&lt;450 Vdc) even with the maximum possible induced voltage on winding N 2  which according to Eq. 16 reduces V B . In that case, the desired V B  can be achieved either by VSF control or by operating L F  in DCM at light loads. Namely, from Eq. 16, it can be seen that V B  is inversely proportional to ∫s. Therefore, by increasing the switching frequency as the load decreases and/or line voltage increases, the energy-storage-capacitor voltage can be limited to the desired level. One implementation of the VSF control is described in Jovanovic. At light loads, voltage V B  can also be li L F . As described in Redl, when both L B  and L F  operate in DCM, V B  is independent of the output current but only depends on the L B  /L F  ratio. 
     In the preceding explanation, it was arbitrarily assumed, for the sake of description simplifications, that the inductance of boost inductor L B  is small so that L B  always operates in DCM. However, the proposed ICS circuit shown in FIG. 4 can also properly operate for larger values of boost inductance L B  which result in the CCM operation of L B . To facilitate the explanation of the circuit operation with L B  operating in CCM, FIGS. 8 and 9 show the topological stages and the key waveforms, respectively. It should be noted that while the leakage inductances of the transformer have no significant effect on the operation of the circuit with L B  operating in DCM and, consequently, were neglected in the preceding explanation, the leakage inductances of auxiliary windings N 1  and N 2  play a major role in the operation of the circuit with L B  operating in CCM and cannot be neglected. As a result, in FIG. 8 the leakage inductances of windings N 1  and N 2  are shown as leakage inductance L 1kl  in series with winding N 1  and leakage inductance L 1k2  in series with winding N2. 
     Due to the CCM operation of L B , at the moment immediately before primary switch SW is turned on (closed), the entire boost-inductor current i LB  is flowing through winding N 2  and rectifier D 2  into bulk capacitor C B . At the same time, transformer secondary winding N S  is shorted because a part of the transformer magnetizing current flows through winding N S  and rectifier D F , while current i LF  is freewheeling through rectifier D FW , inductor L F , and the output, as shown in FIG. 8(e). After switch SW is closed at t=T 0 , current i LB  starts commutating from winding N 2  to winding N 1 , while current i LF  commutates from rectifier D FW  to rectifier D F . According to FIG. 8(a) which represents the circuit in FIG. 4 during the commutation interval  T.sub.)-T 1  !, the i LB  commutation is governed by ##EQU13## 
     Since during the commutation interval  T 0  -T 1  !, boost-inductor current i LB  does not change significantly due to a relative large inductance of boost inductor L B  required for the CCM operation, it can be assumed that 
     
         i.sub.LB =i.sub.1 +i.sub.2 ≅const.,              (18) 
    
     i.e., ##EQU14## 
     From Eqs. 17 and 19, the slopes of current i 1  and i 2  during the commutation interval  T 0  -T 1  ! are approximately given by ##EQU15## 
     The commutation of i LF  from D FW  to D F  can be analyzed in a similar fashion. However, this commutation is well understood and it is not important for the description of ICS properties of the analyzed circuit. Therfore, in this analysis, by neglecting the leakage inductance between primary winding N P  and secondary winding N S  of the transformer, it is assumed that this commutation is instantaneous. 
     Also, it should be noted that during the commutation interval  T 0  -T 1  !, the voltage of the common node of the boost inductor, winding N 1 , and winding N 2  (node Y in FIG. 8 (a)), is given by ##EQU16## as indicated in FIG. 9(b). The above equation was derived from Eqs. 17 and 20. 
     After the commutation of i LB  is completed at t=T 1 , the entire i LB  flows through winding N 1  as shown in FIG. 8(b). During the  T 1  -T 2  ! interval, the boost-inductor current i LB  is given by ##EQU17## where the approximation assumes L B  &gt;L 1k1 . 
     From Eq.22, it can be seen that if the instantaneous rectified-line voltage v in   rec  is smaller than the dc voltage across winding N 1 , i.e., if ##EQU18## no i LB  can build up in inductor L B . As a result, the line current (average of i LB ) contains zero-crossing distortions caused by dead angle Θ (which can be calculated by Eq. 13) of current i LB . 
     On the other hand, for ##EQU19## i LB  can flow after the commutation period  T 0  -T 1  ! is completed, as shown in FIG. 9(c). However, during the time intervals for which v in   rec  is only slightly higher than winding N 1  voltage, (N 1  /N P )V B , i LB  is discontinuous. Therefore, during one half of a line period, the boost inductor operates in both DCM and CCM as illustrated in FIG. 10. The DCM region is more pronounced, i.e., lasts for a larger portion of a line half period, for designs with larger N 1  /N P  ratios. 
     Due to the assumed instantaneous commutation of i LF  from D FW  to D F  at t=T 0 , i LF  and magnetizing current i M  linearly increase during the time period from t=T 0  to t=T 2 , as illustrated in FIGS. 9 (d) and (e). From FIG. 8 (b), the rate of i LF  increase is given by ##EQU20## while the up-slope of i M  is given by ##EQU21## 
     From FIGS. 8(a) and (b), the total switch current i SW  during the on time is given by the sum of boost-inductor current i LB , primary-winding current i P , and magnetizing current i M . To help visualize the components of i SW , FIG. 9(f) uses different hatching patterns for each component. 
     Also, from FIGS. 8(a) and (b) and Ampere&#39;s law, it follows that secondary-winding current i S  is given by ##EQU22## during the commutation period  T 0  -T 1  !, and ##EQU23## during the  T 1  -T 2  ! period. 
     As it can be seen from Eq.28, during the  T 1  -T 2  ! time interval, the output energy is supplied from bulk capacitor C B  by current i P , and directly from the source by current i LB . 
     After switch SW is turned off at t=T 2 , FIG. 9, boost-inductor current i LB  begins commutating from winding N 1  to winding N 2 , while output-filter-inductor current i LF  instantaneously commutates from rectifier D F  to rectifier D FW  because the leakage inductance between windings N P  and N S  is assumed zero. At the same time, the transformer core starts the reset phase by transferring magnetizing inductance i M  to the reset winding N R , thus, discharging the energy stored in the core into bulk capacitor C B . 
     From FIG. 8(c), using the assumption stated in Eq. 18, the slopes of currents i 1  and i 2  during the commutation period  T 2  -T 3  ! can be calculated as ##EQU24## 
     Also, from FIG. 8(c), the downslope of magnetizing current i M  is ##EQU25## while, from FIG. 8(c) and Ampere&#39;s law, reset-winding current i R  during the  T 2  -T 3  ! interval is given by ##EQU26## 
     Using Eqs. 29-31, the downslope of i R  during the commutation interval  T 2  -T 3  ! is ##EQU27## 
     Since according to Eq. 12, for proper operation of the circuit N P  &gt;N 1  +N 2 , and for a typical design N R  ≈N P , the di R  /dt rate is indeed negative, as shown in FIG. 9(g). 
     The voltage of note Y during the commutation interval  T 2  -T 3  !, V Y   OFF , can be calculated from the circuit in FIG. 8(c), with the help of Eq. 29, as ##EQU28## 
     After the commutation period is completed at t=T 3 , the entire boost-inductor currenti LB  flows through auxiliary winding N 2  into bulk capacitor C B , as shown in FIG. 8(d). As the transformer continues to reset after t=T 3 , reset current i R  continues to decrease with the slope given by ##EQU29## which is obtained from Eq.3 1 by setting i 1  =0 and i 2  =i LB , and by using expression for di LB  /dt during the  T 3  -T 4  ! interval given in Eq. 36. Since the slope of i LB  in Eq. 36 is much smaller than the slope of i 1  and i 2  in Eq. 29 due to a relative large value of L B , the di R  /dt rate during the  T 3  -T 4  ! interval is much smaller than that during the commutation interval  T 2  -T 3  !, as indicated in FIG. 9(g). 
     The transformer reset is completed at t=T 4 , when reset current i R  becomes zero. It should be noted that when i R  reaches zero at t=T 4 , magnetizing current i M  is negative and equal to ##EQU30## as shown in FIG. 9(e). Expression in Eq.35 was obtained from Eq.31 by setting i R  (t=T 4 )=0, and recognizing from FIG. 9(c) that i 1  (t=T 4 )=0, i 2  (t=T 4 )=i LB  (t=T 4 ). 
     During the  T 3  -T 4  ! interval, the downslopes of boost-inductor current i LB  and output-filter-inductor current i LF  are constant and given by ##EQU31## 
     The downslope of magnetizing current i M  during this time interval is given by Eq.30, as shown in FIG. 9(e). 
     After the reset of the transformer core is completed at t=T 4 , the voltages across all transformer windings become zero. As a result, the voltage across switch SW becomes equal to the voltage V B  of bulk capacitor C B , as shown in FIG. 9(b). At the same time, a part of magnetizing current i M  which is negative at t=T 4  starts flowing through secondary winding N S  and rectifier D F . Since the voltage across the transformer windings is zero, i M  stays constant until the next switching cycle is initiated at t=T 5 . From FIG. 8(e), applying Ampere&#39;s law for the final time, secondary winding current i S  during the  T 4  -T 5  ! interval is given by ##EQU32## 
     Also, during the  T 4  -T 5  ! interval, shown in FIG. 8(e), i LF  continues to decrease with the downslope given in Eq.37, while i LB  continues to decrease with a smaller downslope given by ##EQU33## as shown in FIG. 9(c). 
     From the preceding analysis of the proposed S 4  ICS circuit operating with L B  in CCM, it can be seen that the leakage inductances L 1k1  and L 1k2  of auxiliary windings N 1  and N 2  only play significant roles during the commutation periods  T 0  -T 1  ! and  T 2  -T 3  !. Namely, assuming negligible leakage inductances, i.e., L 1k1  =L 1k2  =0 in FIG. 8, the volt-second-product balance of L B  during the on and off times is given by ##EQU34## where Λ ON  and Λ OFF  are the volt-second products of L B  during the on and off times, respectively, and T rset  is the reset time of the transformer core, indicated in FIG. 9(b). 
     Since, for the fast output-voltage control, the duty cycle of switch SW is constant over a half of a line period (see Eq.15), T ON  and T OFF  are also constant. Therefore, as rectified-line voltage v in   rec  increases towards its peak, the volt-second-product during the on time, Λ ON , increases, while the volt-second-product during the off time, Λ OFF , decreases. As a result, a volt-second-product (flux) balance of the L B  core cannot be maintained. the resulting large imbalance eventually leads to the saturation of the L B  core. To maintain the required volt-second-product balance, it is necessary to proportionally reduce Λ ON  and proportionally increase Λ OFF  as v in   rec  increases. The desired reduction of Λ ON  and increase of Λ OFF  in the proposed circuit in FIG. 4 is brought about by leakage inductances L 1k1  and L 1k2  Namely, the volt-second-product balance which takes into account the leakage-inductance effect, is ##EQU35## where V Y   ON  and V Y   OFF  are the voltages of node Y in FIG. 8(a) given in Eqs. 21 and 33, respectively, while ΔT com   ON  and ΔT com   OFF  are the commutation periods  T 0  -T 1  ! and  T 2  respectively, as indicated in FIG. 9(b). 
     Eq. 41 can be rewritten as ##EQU36## 
     As it can be seen comparing Eqs. 40 and 42, leakage inductances L 1k1  and L 1k2  decrease Λ ON  for ##EQU37## and increase Λ OFF  for ##EQU38## where ΔΛ ON  and ΔΛ OFF  are the hatched areas in FIG. 9(b). 
     Because, according to Eqs. 20 and 29, the slopes of currents i 1  and i 2  are constant, commutation times ΔT com   ON  and ΔT com   OFF  are proportional to the instantaneous values of i LB  at the moment switch SW is closed and open, respectively. As a result, |ΔΛ ON  | and |ΔΛ OFF  | (hatched areas in FIG. 9(b)) increase as the line voltage increases toward its peak because i LB  increases, as illustrated in FIG. 10. Therefore, with properly selected leakage inductances L 1k1  and L 1k2 , the volt-second-product balance on the L B  core can be maintained during a half of a line period even with a constant duty cycle of switch SW. To obtain the desirable results, the total leakage inductance L 1k  =L 1k1  +L 1k2  should be typically 10% to 20% of the L B  inductance. 
     Finally, the number of turns of the transformer reset winding N R  is determined by the required volt-second-product balance at maximum duty cycle. Generally, at maximum duty cycle, the volt-second-product balance requires ##EQU39## where T ON  is the switch on-time, T OFF  is the off time of the switch, and V R  is the reset voltage. If the maximum duty cycle D max  =50% (T ON  =T OFF ), which occurs at low line and full load, is assumed, then from Eq. 45 follows that 
     
         N.sub.R =N.sub.P                                           (46) 
    
     because T ON  =T OFF . As a result, the voltage across switch SW during off time is ##EQU40## The maximum stress occurs at high line when V B  is maximum. Therefore, for universal line-voltage-range applications, the required rating of the switch is in the 800- to 900-V range. The circuit proposed in this invention can be used with a lower voltage-rated switch (e.g. 600 V) in universal line-voltage applications if a different transformer resetting technique as, for example, RCD-clamp or active-clamp technique is used. 
     It should be noted that the concept explained in this invention can be extended to any other single- or multiple-switch topology. FIG. 11 shows the implementation with the flyback topology. As can be seen from FIG. 11, this implementation does not require a separate reset winding because the transformer reset is done by the output voltage through the secondary-winding. Also, it should be noted that in the flyback implementation a direct energy transfer from the input to the output occurs during the off time. 
     To verify the operation and performance of the proposed S 4  ICS technique for both the DCM and CCM operation of L B , a 100-W/5-V, universal line-voltage range (90-265 Vac), forward converter S 4  ICS shows in FIG. 4 was built. The following components were used for the implementation of the circuit with L B  operating in DCM C in  -1 μF; D 1 , D 2 , &amp; D R  -BYM26E; D F  &amp; D FW  -IR40CPQ045; SW-IXTK21N100; C B  -330 μF/450 V; L F  -1.4 μH; C F  -3×2200 μF, L B  -58 μH, and T 1  -EER35 core with N P  =N R  &#39;=48 turns, N 1  =20 turns, N 2  =26 turns, and N S  =4 turns, leakage inductance L 1k1  +L 1k2  ≈4.6 μH. For the implementation with L B  operating in CCM, except for boost inductor L B  and transformer T 1  windings, all other components were the same as for the DCM operation. In the CCM implementation, L B  =240 μH and T 1  with N P  =N R  =48 turns, N 1  =18 turns, N 2  =12 turns, and N S  =4 turns, and L 1k1  +Lp 1k2  ≈50 μH were taken. In both implementations the same, low-cost, current-mode, PWM IC controller (UC3845) was used to implement a fast output-voltage feedback control. The switching frequencies of both implementations were 75 kHz. 
     FIGS. 12 and 13 show the typical line voltage and current waveforms of the built converter for the DCM and CCM implementations, respectively. Table 1 summarizes the power-factor, total-harmonic-distortion (THD), bulk-capacitor-voltage (V B ), and efficiency measurements for the two implementations. As it can be seen from the oscillograms and Table 1, both implementations work with a high power factor and low THD, while keeping bulk-capacitor voltage V B  below 450 Vdc. However, the efficiency of the CCM implementation is slightly higher. Also, it should be noted that there is a trade-off between the power factor and maximum V B . The DCM implementation can achieve a higher power factor (&gt;0.9), but the maximum V B  is slightly over 400 V. The CCM implementation has a lower power factor (&lt;0.9), but also the maximum voltage on V B  always stays below 400 V. 
     
                       TABLE 1______________________________________Measured Performance Comparisons BetweenThe DCM and CCM Implementations(V.sub.0 = 5 V, I.sub.0 = 20 A, fs = 74 kHz)DCM                 CCMV.sub.in  V! PF      THD    V.sub.B  V!                      η %!                           PF   THD  V.sub.B  V!                                           η %!______________________________________90    0.927   37.1   149   74.9 0.895                                43.7 145   76.0100   0.927   37.2   158   75.5 0.894                                46.3 150   77.5120   0.927   37.9   191   75.9 0.889                                47.9 179   78.5220   0.919   38.6   349   74.2 0.891                                45.6 318   78.2230   0.919   38.7   358   74.0 0.892                                44.8 333   78.1265   0.916   37.8   409   73.4 0.889                                43.0 381   77.2______________________________________ 
    
     While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.