Abstract:
One of the embodiments for a package substrate discloses a molding compound having plurality of metal pillar with middle portion embedded therein; a top end of the metal pillar protrudes above the molding compound; a bottom end of the metal pillar protrudes below the molding compound; a bottom RDL is configured on bottom of the molding compound; the RDL has a plurality of top metal pad and a plurality of bottom metal pad; a density of the plurality of bottom metal pad is higher than the density of the plurality of top metal pad; each metal pillar metal pad is electrically coupled to a corresponding first top metal pad.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present invention relates to a redistribution layer (RDL) for IC package, especially relates to an RDL supported by molding compound. 
         [0003]    2. Description of Related Art 
         [0004]      FIG. 1A  shows a prior art substrate for IC package 
         [0005]      FIG. 1A  shows a prior art substrate for IC package disclosed in US2014/0102777A1 which has an embedded silicon interposer  20 . The silicon interposer  20  has four lateral sides  206 . A molding compound  22  wraps the silicon interposer  20  around the four lateral sides  206 . A plurality of via metal  200  is made through the silicon interposer  20 . An insulation liner  201  is made between the through via  200  and the silicon interposer  20  for an electrical insulation there-between. A top redistribution layer  21  is made on top of the silicon interposer  20  with a plurality of metal pad  210  exposed on top. The plurality of metal pad  210  on top is provided for accommodating an IC chip (not shown) to mount. A circuit built-up layer  25  is made on bottom of the silicon interposer  20  with a plurality of metal pad  220  configured on bottom. A plurality of solder ball  24  is configured and each solder ball  24  is configured on bottom of a corresponding bottom metal pad  220 . 
         [0006]      FIG. 1B  shows a reversed view of  FIG. 1A .  FIG. 1B  is made to present the prior art of  FIG. 1A  in a position similar to a package substrate of the present invention to facilitate a comparison there between.  FIG. 1B  shows an up-down view of  FIG. 1A . The top solder ball  24  is configured for mounting the package substrate onto a mother board (not shown). The bottom metal pad  210  is configured for a chip or chips to mount. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1A ˜ 1 B show a prior art substrate for IC package 
           [0008]      FIGS. 2A ˜ 2 L and  3 A˜ 3 C, shows a manufacturing process according to the present invention. 
           [0009]      FIG. 3D  is a first embodiment of the present invention. 
           [0010]      FIG. 3E  is a second embodiment of the present invention. 
           [0011]      FIG. 3F  shows an IC chip mounted on bottom of  FIG. 3D   
           [0012]      FIG. 3F ′ shows an IC chip mounted on bottom of  FIG. 3E   
           [0013]      FIG. 3G  shows an IC package unit obtained through singulating the product of  FIG. 3F . 
           [0014]      FIG. 3G ′ shows an IC package unit obtained through singulating the product of  FIG. 3F ′ 
           [0015]      FIGS. 2A ˜ 2 L and  4 A˜ 4 C, shows a manufacturing process according to the present invention. 
           [0016]      FIG. 4D  is a third embodiment of the present invention. 
           [0017]      FIG. 4E  is a fourth embodiment of the present invention. 
           [0018]      FIG. 4F  shows an IC chip mounted on bottom of  FIG. 4D   
           [0019]      FIG. 4F ′ shows an IC chip mounted on bottom of  FIG. 4E   
           [0020]      FIG. 4G  shows an IC package unit obtained through singulating the product of  FIG. 4F . 
           [0021]      FIG. 4G ′ shows an IC package unit obtained through singulating the product of  FIG. 4F ′ 
           [0022]      FIGS. 2A ˜ 2 L and  5 A˜ 5 C, shows a manufacturing process according to the present invention. 
           [0023]      FIG. 5D  is a fifth embodiment of the present invention. 
           [0024]      FIG. 5E  is a sixth embodiment of the present invention. 
           [0025]      FIG. 5F  shows an IC chip mounted on bottom of  FIG. 5D   
           [0026]      FIG. 5F ′ shows an IC chip mounted on bottom of  FIG. 5E   
           [0027]      FIG. 5G  shows an IC package unit obtained through singulating the product of  FIG. 5F . 
           [0028]      FIG. 5G ′ shows an IC package unit obtained through singulating the product of  FIG. 5F ′ 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0029]      FIGS. 2A ˜ 2 L and  3 A˜ 3 C, shows a manufacturing process according to the present invention. 
         [0030]      FIG. 3D  is a first embodiment of the present invention. 
         [0031]      FIG. 3E  is a second embodiment of the present invention. 
         [0032]    A molding compound supported RDL for IC package is fabricated, includes the following steps: 
         [0033]      FIG. 2A  shows: preparing a temporary carrier; applying a release layer  31  on top of the temporary carrier; and applying a bottom seed layer  32  on top of the release layer  31 . 
         [0034]      FIG. 2B  shows: applying a patterned photo resist  33  on top of the bottom seed layer  32 . 
         [0035]      FIG. 2C  shows: forming a patterned first bottom metal pad  341 . 
         [0036]      FIG. 2D  shows: stripping the photo-resist  33 . 
         [0037]      FIG. 2E  shows: stripping the bottom seed layer  32  between the first bottom metal pads  341 . 
         [0038]      FIG. 2F  shows: forming a bottom RDL (RDL  1 ) using the first bottom metal pad  341  as a starting point; forming a plurality of first top metal pad  343  on top of the bottom RDL (RDL  1 ), wherein at least one circuit layer  342  is made between the first bottom metal pad  341  and the first top metal pad  343 . A first top dielectric layer  353  is formed on top of the first top metal pad  343  and a plurality opening is made to expose a top of each first top metal pad  343 . The first bottom metal pad  341 , circuit layer  342 , and the first top metal pad  343  are embedded in the dielectric layers  351 ,  352 ,  353 ; forming a first top dielectric layer with a plurality of opening, each opening exposes a top of a corresponding first top metal pad; 
         [0039]      FIG. 2G  shows: applying a seed layer  352  on top of the first top dielectric layer  353  and the first top metal pad; 
         [0040]      FIG. 2H  shows: forming a patterned photo resist  332  on top of the seed layer  352 ; 
         [0041]      FIG. 2I  shows: forming a plurality of metal pillar  36 , each is formed on top of a corresponding first top metal pad  343 ; 
         [0042]      FIG. 2J  show: stripping the photo resist  332  and leaving the metal pillar  36  exposed; 
         [0043]    stripping the top seed layer  322  between metal pillars  36 ; 
         [0044]    revealing the plurality of metal pillar; 
         [0045]      FIG. 2K  shows: applying a molding compound  37  to encapsulate the plurality of metal pillar  36 ; 
         [0046]      FIG. 2L  shows: thinning from top of the molding compound  37 ; and 
         [0047]    revealing a top surface of each metal pillar  36 . 
         [0048]      FIG. 3A  shows: removing portion of the molding compound  37  from top; 
         [0049]    revealing a top end of each metal pillar  36 ; 
         [0050]      FIG. 3B  shows: forming a protection layer  361 , such as an Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), on each revealed top of the metal pillar  36 ; 
         [0051]      FIG. 3C  shows: planting a plurality of solder ball  38 , each is planted on top of a corresponding ENEPIG  361  which brackets a top end of a corresponding metal pillar  36 ; 
         [0052]      FIG. 3D  shows: removing the temporary carrier; and removing the bottom seed layer  32  from bottom of each first bottom metal pad  341 .  FIG. 3D  shows a molding compound  37  wrapping a plurality of metal pillar  36 , a protection layer  361  is configured on top of a corresponding metal pillar  36 ; a solder ball is configured on top of each protection layer  361 ; a bottom RDL (RDL  1 ) is made on bottom of the molding compound  37 . 
         [0053]      FIG. 3E  shows: forming a bottom protection layer  39  on bottom of a corresponding first bottom metal pad  341 . The protection layer is ENEPIG. The protection layer prevents oxidation of the exposed end of the metal pillar  36  before next step.  FIG. 3E  shows a molding compound  37  wrapping a plurality of metal pillar  36 , a protection layer  361  is configured on top of a corresponding metal pillar  36 ; a solder ball is configured on top of each protection layer  361 ; a bottom RDL (RDL  1 ) is made on bottom of the molding compound  37 ; a bottom protection layer  39  is made on bottom of a corresponding first bottom metal pad  341 . 
         [0054]      FIG. 3F  shows an IC chip mounted on bottom of  FIG. 3D   
         [0055]      FIG. 3F  shows a chip  391  mounted on bottom of  FIG. 3D ; the chip  391  is electrically coupled to the first bottom metal pad  341  through a plurality of solder ball. An under fill  392  can be made between the chip  391  and the first bottom metal pad  341 . 
         [0056]      FIG. 3F ′ shows an IC chip mounted on bottom of  FIG. 3E   
         [0057]      FIG. 3F ′ shows a chip  391  mounted on bottom of  FIG. 3E ; the chip  391  is electrically coupled to the bottom protection layer  39  through a plurality of solder ball. An under fill  392  can be made between the chip  391  and the bottom protection layer  39 . 
         [0058]      FIG. 3G  shows an IC package unit obtained through singulating the product of  FIG. 3F . 
         [0059]      FIG. 3G  shows an IC package which is a package based on the molding compound supported RDL of the first embodiment according to the present invention. 
         [0060]      FIG. 3G ′ shows an IC package unit obtained through singulating the product of  FIG. 3F ′ 
         [0061]      FIG. 3G ′ shows an IC package which is a package based on the molding compound supported RDL of the second embodiment according to the present invention. 
         [0062]      FIGS. 2A ˜ 2 L and  4 A˜ 4 C, shows a manufacturing process according to the present invention. 
         [0063]      FIG. 4D  is a third embodiment of the present invention. 
         [0064]      FIG. 4E  is a fourth embodiment of the present invention. 
         [0065]    The manufacturing process of  FIGS. 2A ˜ 2 L is the same as described in previous paragraph and omitted here for simplification. 
         [0066]      FIG. 4A  shows: removing portion of the molding compound  37  from top; 
         [0067]    revealing a top end of each metal pillar  36 ; 
         [0068]      FIG. 4B  shows: forming a protection layer  362 , such as an Organic Solderability Preservatives (OSP), on each revealed top of the metal pillar  36 . The protection layer prevents oxidation of the exposed end of the metal pillar  36  before next step. 
         [0069]      FIG. 4C  shows: planting a plurality of solder ball  38 , each is planted on top of a corresponding protection layer  362 , however OSP is cleaned out by soldering flux and heat; therefore, the solder ball  38  can be seen planted directly on a top of a corresponding metal pillar  36 . 
         [0070]      FIG. 4D  shows: removing the temporary carrier; and removing the seed layer  32  from bottom of each first bottom metal pad  341 . 
         [0071]      FIG. 4E  shows: forming a bottom protection layer  39  on bottom of a corresponding first bottom metal pad  341 . The protection layer is ENEPIG.  FIG. 4E  shows a molding compound  37  wrapping a plurality of metal pillar  36 ; a solder ball is configured on top of a corresponding metal pillar  36 ; a bottom RDL (RDL  1 ) is made on bottom of the molding compound  37 ; a bottom protection layer  39  is made on bottom of a corresponding first bottom metal pad  341 . 
         [0072]      FIG. 4F  shows an IC chip mounted on bottom of  FIG. 4D   
         [0073]      FIG. 4F  shows an IC chip mounted on bottom of  FIG. 4D ; the chip  391  is electrically coupled to the first bottom metal pad  341  through a plurality of solder ball. An under fill  392  can be made between the chip  391  and the first bottom metal pad  341 . 
         [0074]      FIG. 4F ′ shows an IC chip mounted on bottom of  FIG. 4E   
         [0075]      FIG. 4F ′ shows an IC chip  391  mounted on bottom of  FIG. 4E ; the chip  391  is electrically coupled to the bottom protection layer  39  through a plurality of solder ball. An under fill  392  can be made between the chip  391  and the bottom protection layer  39 . 
         [0076]      FIG. 4G  shows an IC package unit obtained through singulating the product of  FIG. 4F . 
         [0077]      FIG. 4G  shows an IC package which is a package based on the molding compound supported RDL of the third embodiment according to the present invention. 
         [0078]      FIG. 4G ′ shows an IC package unit obtained through singulating the product of  FIG. 4F ′ 
         [0079]      FIG. 4G ′ shows an IC package which is a package based on the molding compound supported RDL of the fourth embodiment according to the present invention. 
         [0080]      FIGS. 2A ˜ 2 L and  5 A˜ 5 C, shows a manufacturing process according to the present invention. 
         [0081]      FIG. 5D  is a fifth embodiment of the present invention. 
         [0082]      FIG. 5E  is a sixth embodiment of the present invention. 
         [0083]    The manufacturing process of  FIGS. 2A ˜ 2 L is the same as described in previous paragraph and omitted here for simplification. 
         [0084]      FIG. 5A  shows: forming a second bottom metal pad  441  on top of a corresponding metal pillar  36 ; 
         [0085]      FIG. 5B  shows: forming a top RDL (RDL  2 ) on top of the molding compound  37 ; forming a plurality of second top metal pad  443  on top of the top RDL (RDL  2 ); 
         [0086]      FIG. 5C  shows: planting a plurality of solder ball  38 , each is planted on top of a corresponding second top metal pad; 
         [0087]      FIG. 5D  shows: removing the temporary carrier; and removing the bottom seed layer  32  from bottom of each first bottom metal pad  341 . 
         [0088]      FIG. 5E  shows: forming a bottom protection layer  39  on bottom of a corresponding first bottom metal pad  341 . 
         [0089]      FIG. 5F  shows an IC chip mounted on bottom of  FIG. 5D   
         [0090]      FIG. 5F  shows an IC chip mounted on bottom of  FIG. 5D ; the chip  391  is electrically coupled to the first bottom metal pad  341  through a plurality of solder ball. An under fill  392  can be made between the chip  391  and the first bottom metal pad  341 . 
         [0091]      FIG. 5F ′ shows an IC chip mounted on bottom of  FIG. 5E   
         [0092]      FIG. 5F ′ shows an IC chip  391  mounted on bottom of  FIG. 5E ; the chip  391  is electrically coupled to the bottom protection layer  39  through a plurality of solder ball. An under fill  392  can be made between the chip  391  and the bottom protection layer  39 . 
         [0093]      FIG. 5G  shows an IC package unit obtained through singulating the product of  FIG. 5F . 
         [0094]      FIG. 5G  shows an IC package which is a package based on the molding compound supported RDL of the fifth embodiment according to the present invention. 
         [0095]      FIG. 5G ′ shows an IC package unit obtained through singulating the product of  FIG. 5F ′ 
         [0096]      FIG. 5G ′ shows an IC package which is a package based on the molding compound supported RDL of the sixth embodiment according to the present invention. 
         [0097]    While several embodiments have been described by way of example, it will be apparent to those skilled in the art that various modifications may be configured without departs from the spirit of the present invention. Such modifications are all within the scope of the present invention, as defined by the appended claims.