Abstract:
Methods and systems for split voltage domain transmitter circuits are disclosed and may include a two-branch output stage including a plurality of CMOS transistors, each branch of the two-branch output stage comprising two stacked CMOS inverter pairs from among the plurality of CMOS transistors; the two stacked CMOS inverter pairs of a given branch being configured to drive a respective load, in phase opposition to the other branch; and a pre-driver circuit configured to receive a differential modulating signal and output, to respective inputs of the two stacked CMOS inverters, two synchronous differential voltage drive signals having a swing of half the supply voltage and being DC-shifted by half of the supply voltage with respect to each other. The load may include a series of diodes that are driven in differential mode via the drive signals. An optical signal may be modulated via the diodes.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE 
       [0001]    This application is a continuation of application Ser. No. 14/922,916 filed on Oct. 26, 2015, which is a continuation of application Ser. No. 14/229,243 filed on Mar. 28, 2014, which is a continuation of application Ser. No. 12/208,650 filed on Sep. 11, 2008, now U.S. Pat. No. 8,687,981, which in turn makes reference to, claims priority to and claims the benefit of U.S. Provisional Patent Application No. 60/997,282 filed on Oct. 2, 2007. 
         [0002]    This application also makes reference to:
   U.S. Pat. No. 7,039,258; and   U.S. patent application Ser. No. 12/208,668 (Attorney Docket No. 19509US01) filed on Sep. 11, 2008.   
 
         [0005]    Each of the above stated applications is hereby incorporated herein by reference in its entirety. 
     
    
     FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
       [0006]    [Not Applicable] 
       MICROFICHE/COPYRIGHT REFERENCE 
       [0007]    [Not Applicable] 
       FIELD OF THE INVENTION 
       [0008]    Certain embodiments of the invention relate to integrated circuit power control. More specifically, certain embodiments of the invention relate to a method and system for split voltage domain transmitter circuits. 
       BACKGROUND OF THE INVENTION 
       [0009]    Electronic circuits typically require a bias voltage for proper operation. The voltage level required by a circuit depends on the application. A circuit for signal transmission may require a higher voltage than a circuit used for processing data. The optimum voltage may be determined by the bias voltage requirements of the transistors, or other active devices, within the circuit. 
         [0010]    A bipolar transistor circuit may require a higher voltage in amplifier applications to avoid saturation of the amplifier, as opposed to switching operations, for example. CMOS circuits may require a lower voltage to drive the MOSFETs in the circuit. 
         [0011]    Furthermore, as device sizes continue to shrink for higher speed and lower power consumption, a high voltage may degrade performance and cause excessive leakage. With thinner gate oxides, gate leakage current may become significant using historical bias voltages, thus driving gate voltages lower. However, if a transmitter/receiver may be integrated in the same device, a higher bias voltage may also be required. Bias voltages are typically DC voltage, and may be supplied by a battery. However, there may be noise in the bias voltage, which may be mitigated by capacitive filters. The variable output voltage of batteries my affect operation of battery powered devices. Devices generally must be capable of operating over a large range of voltage due to the variable output voltage capability of batteries. 
         [0012]    Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings. 
       BRIEF SUMMARY OF THE INVENTION 
       [0013]    A system and/or method for split voltage domain transmitter circuits, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. 
         [0014]    Various advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings. 
     
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
         [0015]      FIG. 1A  is a block diagram of a photonically enabled CMOS chip, in accordance with an embodiment of the invention. 
           [0016]      FIG. 1B  is a diagram illustrating an exemplary CMOS chip, in accordance with an embodiment of the invention. 
           [0017]      FIG. 1C  is a diagram illustrating an exemplary CMOS chip coupled to an optical fiber cable, in accordance with an embodiment of the invention. 
           [0018]      FIG. 1D  is a block diagram of an exemplary n-type field effect transistor circuit, in accordance with an embodiment of the invention. 
           [0019]      FIG. 1E  is a block diagram of an exemplary p-type field effect transistor circuit, in accordance with an embodiment of the invention. 
           [0020]      FIG. 2  is a block diagram of an exemplary split domain Mach-Zehnder modulator, in accordance with an embodiment of the invention. 
           [0021]      FIG. 3  is a schematic of an exemplary transmission line driver with a domain splitter circuit, in accordance with an embodiment of the invention. 
           [0022]      FIG. 4  is an exemplary stacked inverter unit driver, in accordance with an embodiment of the invention. 
           [0023]      FIG. 5  is a block diagram of exemplary coupled transmission lines, in accordance with an embodiment of the invention. 
           [0024]      FIG. 6  is a flow chart illustrating exemplary steps in the operation of a Mach-Zehnder modulator with partial voltage domains, in accordance with an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0025]    Certain aspects of the invention may be found in a method and system for split voltage domain transmitter circuits. Exemplary aspects of the invention may comprise amplifying a received signal in a plurality of partial voltage domains. Each of the partial voltage domains may be offset by a DC voltage from the other partial voltage domains. A sum of the plurality of partial domains may be equal to a supply voltage of the integrated circuit. A series of diodes may be driven in differential mode via the amplified signals. An optical signal may be modulated via the diodes, which may be integrated in a Mach-Zehnder modulator or a ring modulator, for example. The diodes may be connected in a distributed configuration. The amplified signals may be communicated to the diodes via even-mode coupled transmission lines. The partial voltage domains may be generated via stacked source follower or emitter follower circuits. The voltage domain boundary value may be at one half the supply voltage due to symmetric stacked circuits. 
         [0026]      FIG. 1A  is a block diagram of a photonically enabled CMOS chip, in accordance with an embodiment of the invention. Referring to  FIG. 1A , there is shown optoelectronic devices on a CMOS chip  130  comprising high speed optical modulators  105 A- 105 D, high-speed photodiodes  111 A- 111 D, monitor photodiodes  113 A- 113 H, and optical devices comprising taps  103 A- 103 K, optical terminations  115 A- 115 D, and grating couplers  117 A- 117 H. There is also shown electrical devices and circuits comprising transimpedance and limiting amplifiers (TIA/LAs)  107 A- 107 E, analog and digital control circuits  109 , and control sections  112 A- 112 D. Optical signals are communicated between optical and optoelectronic devices via optical waveguides fabricated in the CMOS chip  130 . 
         [0027]    The high speed optical modulators  105 A- 105 D comprise Mach-Zehnder or ring modulators, for example, and enable the modulation of the CW laser input signal. The high speed optical modulators  105 A- 105 D are controlled by the control sections  112 A- 112 D, and the outputs of the modulators are optically coupled via waveguides to the grating couplers  117 E- 117 H. The taps  103 D- 103 K comprise four-port optical couplers, for example, and are utilized to sample the optical signals generated by the high speed optical modulators  105 A- 105 D, with the sampled signals being measured by the monitor photodiodes  113 A- 113 H. The unused branches of the taps  103 D- 103 K are terminated by optical terminations  115 A- 115 D to avoid back reflections of unwanted signals. 
         [0028]    The grating couplers  117 A- 117 H comprise optical gratings that enable coupling of light into and out of the CMOS chip  130 . The grating couplers  117 A- 117 D are utilized to couple light received from optical fibers into the CMOS chip  130 , and the grating couplers  117 E- 117 H are utilized to couple light from the CMOS chip  130  into optical fibers. The optical fibers may be epoxied, for example, to the CMOS chip, and may be aligned at an angle from normal to the surface of the CMOS chip  130  to optimize coupling efficiency. 
         [0029]    The high-speed photodiodes  111 A- 111 D convert optical signals received from the grating couplers  117 A- 117 D into electrical signals that are communicated to the TIA/LAs  107 A- 107 D for processing. The analog and digital control circuits  109  may control gain levels or other parameters in the operation of the TIA/LAs  107 A- 107 D. The TIA/LAs  107 A- 107 D then communicate electrical signals off the CMOS chip  130 . 
         [0030]    The control sections  112 A- 112 D comprise electronic circuitry that enable modulation of the CW laser signal received from the splitters  103 A- 103 C. The high speed optical modulators  105 A- 105 D require high-speed electrical signals to modulate the refractive index in respective branches of a Mach-Zehnder interferometer (MZI), for example. The voltage swing required for driving the MZI is a significant power drain in the CMOS chip  130 . Thus, if the electrical signal for driving the modulator may be split into domains with each domain traversing a lower voltage swing, power efficiency is increased. 
         [0031]      FIG. 1B  is a diagram illustrating an exemplary CMOS chip, in accordance with an embodiment of the invention. Referring to  FIG. 1B , there is shown the CMOS chip  130  comprising electronic devices/circuits  131 , optical and optoelectronic devices  133 , a light source interface  135 , CMOS chip surface  137 , an optical fiber interface  139 , and CMOS guard ring  141 . 
         [0032]    The light source interface  135  and the optical fiber interface  139  comprise grating couplers that enable coupling of light signals via the CMOS chip surface  137 , as opposed to the edges of the chip as with conventional edge-emitting devices. Coupling light signals via the CMOS chip surface  137  enables the use of the CMOS guard ring  141  which protects the chip mechanically and prevents the entry of contaminants via the chip edge. 
         [0033]    The electronic devices/circuits  131  comprise circuitry such as the TIA/LAs  107 A- 107 D and the analog and digital control circuits  109  described with respect to  FIG. 1A , for example. The optical and optoelectronic devices  133  comprise devices such as the taps  103 A- 103 K, optical terminations  115 A- 115 D, grating couplers  117 A- 117 H, high speed optical modulators  105 A- 105 D, high-speed photodiodes  111 A- 111 D, and monitor photodiodes  113 A- 113 H. 
         [0034]      FIG. 1C  is a diagram illustrating an exemplary CMOS chip coupled to an optical fiber cable, in accordance with an embodiment of the invention. Referring to  FIG. 1C , there is shown the CMOS chip  130  comprising the electronic devices/circuits  131 , the optical and optoelectronic devices  133 , the light source interface  135 , the CMOS chip surface  137 , and the CMOS guard ring  141 . There is also shown a fiber to chip coupler  143 , an optical fiber cable  145 , and a light source module  147 . 
         [0035]    The CMOS chip  130  comprising the electronic devices/circuits  131 , the optical and optoelectronic devices  133 , the light source interface  135 , the CMOS chip surface  137 , and the CMOS guard ring  141  may be as described with respect to  FIG. 1B . 
         [0036]    In an embodiment of the invention, the optical fiber cable may be affixed, via epoxy for example, to the CMOS chip surface  137 . The fiber chip coupler  143  enables the physical coupling of the optical fiber cable  145  to the CMOS chip  130 . 
         [0037]    The light source module  147  may be affixed, via epoxy or solder, for example, to the CMOS chip surface  137 . In this manner a high power light source may be integrated with optoelectronic and electronic functionalities of one or more high-speed optoelectronic transceivers on a single CMOS chip. 
         [0038]    The power requirements of optoelectronic transceivers is an important parameter. Minimizing voltage swings is one option for reducing power usage, and modulating light at multi-gigabit speeds typically requires higher voltages than needed for high-speed electronics. Thus, a multi-voltage domain architecture in the modulator driver circuitry reduces the voltage requirements, and thus improved power efficiency, by driving the circuitry in each domain over a smaller voltage range than the entire voltage swing. 
         [0039]      FIG. 1D  is a block diagram of an exemplary n-type field effect transistor circuit, in accordance with an embodiment of the invention. Referring to  FIG. 1D , there is shown a source follower circuit  55  comprising an n-channel field effect transistor (NFET)  50 , a resistor  33 , a high rail  20 , and a low rail  10 . There is also shown a circuit input  100  and a circuit output  200 . 
         [0040]    The source follower circuit  55  has two power rails, comprising the high rail  20  biased at a voltage V f , or full voltage, and the low rail  10 , marked with the customary symbol of “ground”. The circuit has an input  100  on the gate of the NFET  50 , while the circuit output  200  is on the NFET source side, or simply source. The NFET  50  drain side, or drain, is connected to the high rail  20 . The resistor  33  is coupled between the source terminal of the NFET  50  and the low rail  10 , completing an electrical path between the high  20  and low  10  rails. 
         [0041]    In operation, an input signal is applied to the input  100 . The source follower circuit  55  may be utilized to lower the impedance level in the signal path, drive resistive loads, or to provide DC level shifting, since the gate-source DC voltage drop may be controllable by the bias current. The gain of the source follower circuit  55  may be near unity, resulting in a AC output signal at the circuit output  200 , but with a configurable DC output level. 
         [0042]      FIG. 1E  is a block diagram of an exemplary p-type field effect transistor circuit, in accordance with an embodiment of the invention. Referring to  FIG. 1E , there is shown a source follower circuit  65  comprising a p-channel field effect transistor (PFET)  60 , a resistor  33 ′, a high rail  20 , and a low rail  10 . There is also shown a circuit input  100 ′ and a circuit output  200 ′. 
         [0043]    The PFET source follower has two power rails, comprising a high rail  20  at a voltage V f , or full voltage, and a low rail  10 , marked with the “ground” symbol. The circuit has an input  100 ′ on the PFET  60  gate, while the circuit output  200 ′ is on the PFET  60  source side, or simply source. The PFET  60  drain side, or drain, is connected to the low rail  10 . The current source  33 ′ is coupled to the high rail  20  and the PFET  60  source, completing an electrical path between the high  20  and low  10  rails. 
         [0044]    In operation, an input signal is applied to the input  100 ′. The source follower circuit  65  may be utilized to lower the impedance level in the signal path, drive resistive loads, or to provide DC level shifting, since the gate-source DC voltage drop may be controllable by the bias current. The gain of the source follower circuit  65  may be near unity, resulting in a similar AC output signal at the circuit output  200 ′, but with a configurable DC output level. 
         [0045]      FIG. 2  is a block diagram of an exemplary split domain Mach-Zehnder modulator, in accordance with an embodiment of the invention. Referring to  FIG. 2 , there is shown a split-domain Mach-Zehnder modulator (MZM)  250  comprising a transmission line driver  209 , waveguides  211 , transmission lines  213 A- 213 D, diode drivers  215 A- 215 H, diodes  219 A- 219 D, and transmission line termination resistors R TL1 -R TL4 . There is also shown voltage levels V dd , V d , and Gnd. In an embodiment of the invention, V d  is equal to a voltage of V dd /2, thus generating two voltage domains, due to the symmetric nature of the stacked circuits. However, the invention is not limited to two voltage domains. Accordingly, any number of voltage domains may be utilized, dependent on the desired voltage swing of each domain and the total voltage range, defined here as V dd  to ground. Similarly, the magnitude of the voltage range in each voltage domain may be a different value than other domains. 
         [0046]    The transmission line (T-line) driver  209  comprises circuitry for driving transmission lines in an even-coupled mode, where the signal on each pair of transmission lines is equal except with a DC offset. In this manner, two or more voltage domains may be utilized to drive the diodes that generate index changes in the respective branches of the MZM  250 . In another embodiment of the invention, the T-line driver  209  may drive transmission lines in odd-coupled mode. Even-coupled mode may result in a higher impedance in the transmission line, whereas odd-coupling may result in lower impedance. 
         [0047]    The waveguides  211  comprise the optical components of the MZM  250  and enable the routing of optical signals around the CMOS chip  130 . The waveguides  211  comprise silicon and silicon dioxide, formed by CMOS fabrication processes, utilizing the index of refraction difference between Si and SiO 2  to confine an optical mode in the waveguides  211 . The transmission line termination resistors R TL1 -R TL4  enable impedance matching to the T-lines  213 A- 213 D and thus reduced reflections. 
         [0048]    The diode drivers  215 A- 215 H comprise circuitry for driving the diodes  219 A- 219 D, thereby changing the index of refraction locally in the waveguides  211 . This index change in turn changes the velocity of the optical mode in the waveguides  211 , such that when the waveguides merge again following the driver circuitry, the optical signals interfere constructively or destructively, thus modulating the laser input signal. By driving the diodes  219 A- 219 D with a differential signal, where a signal is driven at each terminal of a diode, as opposed to one terminal being tied to AC ground, both power efficiency and bandwidth may be increased due to the reduced voltage swing required in each domain. 
         [0049]    In operation, a CW optical signal is coupled into the “Laser Input”, and a modulating differential electrical signal is communicated to the T-line driver  209 . The T-line driver  209  generates complementary electrical signals to be communicated over the T-lines  213 A- 213 D, with each pair of signals offset by a DC level to minimize the voltage swing of each diode driver  215 A- 215 H, while still enabling a full voltage swing across the diodes  219 A- 219 D. 
         [0050]    Reverse biasing the diodes  219 A- 219 D generates field effects that change the index of refraction and thus the speed of the optical signal propagating through the waveguides  213 A- 213 D. The optical signals then interfere constructively or destructively, resulting in the “Modulated Light” signal. 
         [0051]      FIG. 3  is a schematic of an exemplary transmission line driver with a domain splitter circuit, in accordance with an embodiment of the invention. Referring to  FIG. 3 , there is shown a transmission line (T-line) driver  300  and transmission lines  307 A-D. The T-line driver  300  may be substantially similar to the T-line driver  209  described with respect to  FIG. 2  and comprises a domain splitter  310 , amplifiers  305 A/ 305 B, current sources  303 A- 303 E, a comparator  301 , bias resistors R B1  and R B2 , resistors R T1  and R T2 , a capacitor C 1 , and MOSFET transistors M 1 -M 5 . The domain splitter  310  may be a pair of stacked source-follower pairs comprising the MOSFET transistors M 6 -M 9 . 
         [0052]    The T-line driver  300  comprises a cascode circuit that may be enabled to generate the complementary inputs V+ and V− to be communicated to the domain splitter  310 , although a cascode circuit is not required. The outputs V+ and V− are inverted relative to V in + and V in −, and may be of smaller magnitude. Components of the circuit, such as NFETs, resistors, capacitors, and others may be so selected that the output voltages V+ and V− are approximately centered around the voltage V d  in  FIG. 2 , typically set to be half of the full range voltage: V d =V dd /2, due to the symmetric nature of the stacked circuits. 
         [0053]    The cascode T-line driver  300  may employ elements for feedback to assure the stability of the outputs, and to correct for processing variations in the circuits. Such a feedback element may be the differential amplifier  301  controlling the gate of MOSFET transistor M 1 , which may act like an adjustable resistance in parallel with the capacitor C 1 . In another embodiment of the invention, the MOSFET transistor M 1  may act as an adjustable current source. 
         [0054]    The differential amplifier  301  is sensitive to the magnitude and to the imbalances of the outputs V+ and V−, sampling the voltage via the two tap resistors R T1  and R T2  and comparing the sampled voltage to a reference voltage, which may be chosen to be V d , which is equal to V dd /2 in this exemplary embodiment. However, V d , could be chosen to be any voltage within the voltage range defined by V dd  and ground. 
         [0055]    The domain splitter  310  comprises a pair of stacked NFET and PFET source follower circuits. The drain side of the NFET M 7  and the drain side of the PFET M 6  are commonly connected to V d , or V dd /2 in this exemplary embodiment. In this manner, the NFET source followers M 7  and M 9  are in the lower voltage domain, powered by V dd /2 to ground, while the PFET source followers M 6  and M 8  are in the higher voltage domain, powered by V dd  to V dd /2. 
         [0056]    The input voltages to the amplifiers  305 A and  305 B are coupled by electrically connecting the gate of the NFET M 7  to the gate of the PFET M 6 , and the gate of the NFET M 9  to the gate of the PFET M 8 . This arrangement results in the tracking of output voltages, such that if voltage V+ rises, then both voltages V H  and V L  will rise, and conversely, if voltage V+ falls, voltages V H  and V L  will also fall, thus exhibiting identical AC characteristics, but with a DC offset configured by the domain splitter  310 . The full range of voltage V+ is generally not restricted to either the lower or the upper voltage domain. The rate of voltage movement, or swing, on V+, in general, is not the same as for V H  and V L . The ratios of the swings between voltages V+ and V H  and V L , respectively, depend on particular design and characteristics of the NFET and PFET source followers. However, this arrangement allows for voltage V L  to essentially cover the span of the lower voltage domain, namely between “ground” and V d , and for voltage V H  to essentially cover the span of the upper voltage domain, namely between V dd  and V d . 
         [0057]    The transmission lines  307 A- 307 D are even-coupled, in that the “+” output of both the amplifiers  305 A and  305 B drive coupled transmission lines. Similarly, the “−” output of both amplifiers  305 A and  305 B drive another pair of coupled transmission lines, as described further with respect to  FIG. 5 . 
         [0058]      FIG. 4  is a schematic of an exemplary stacked inverter unit driver circuit, in accordance with an embodiment of the invention. Referring to  FIG. 4 , there is shown the unit driver circuit  400  comprising the inverters  401 A- 401 Q. The unit driver circuit  400  is substantially similar to one stage of diode drivers,  215 A-D or  215 E- 215 H, as described with respect to  FIG. 2 . 
         [0059]    The input signals to the unit driver circuit  400  comprise the signals received from transmission lines, such as the transmission lines  307 A- 307 D, described with respect to  FIG. 3 . The outputs of each pair of stages, such as  401 A- 410 H, and  401 I- 401 Q, may be coupled to a diode, indicated by D 1 +/D 1 − and D 2 +/D 2 −. The voltage powering the upper stages of the unit driver circuit  400  is defined by V dd  to V dd /2, and V dd /2 to ground for the lower stages. In this manner, each inverter stage only swings across half the entire voltage range, V dd /2 in this exemplary embodiment, while the diodes coupled to D 1 +/D 1 − and D 2 +/D 2 − are driven across the entire voltage range V dd  to ground. 
         [0060]      FIG. 5  is a block diagram of exemplary coupled transmission lines, in accordance with an embodiment of the invention. Referring to  FIG. 5 , there is shown ground plane  501 , coupled line positive  503 , coupled line negative  505 , and coupling ports  507 A- 507 H. The transmission lines comprise a coupled line positive  503  and a coupled line negative  505  transmission line and may be defined by coplanar conductive lines on the CMOS chip  130 , described with respect to  FIG. 1 , and surrounded on both sides by the ground plane  501 . In this manner, high frequency electrical signals may be communicated over the transmission lines of a characteristic impedance, with each pair of complementary signals being identical but with a DC offset. Driving the transmission lines in even-coupled mode may result in a higher characteristic impedance. The coupling ports  507 A- 507 H enable the coupling of signals out of the transmission lines to unit drivers, such as the unit drivers described with respect to  FIG. 4 . 
         [0061]      FIG. 6  is a flow chart illustrating exemplary steps in the operation of a Mach-Zehnder modulator with partial voltage domains, in accordance with an embodiment of the invention. In step  603 , after start step  601 , a differential electrical signal may be applied to the T-line driver  209  and a CW optical signal may be coupled to the waveguide  211  of the MZM  250 . In step  605 , the electrical signal may be amplified by different voltage domain circuitry to reduce the voltage swing in each domain and the signal may be communicated via transmission lines  213 A- 213 D. In step  607 , the signal received from the transmission lines  213 A- 213 D may be utilized to drive stacked inverter stages  215 A- 215 H, which in turn drive the MZM diodes  219 A- 219 D. In step  609 , the MZM diodes  219 A- 219 D may cause constructive and/or destructive interference of the optical signals in the waveguides  211 , such that a modulated optical signal may be generated, followed by end step  611 . 
         [0062]    In an embodiment of the invention, a method and system are disclosed for amplifying a received signal in a plurality of partial voltage domains. Each of the partial voltage domains may be offset by a DC voltage from the other partial voltage domains. A sum of the plurality of partial domains may be equal to a supply voltage of the integrated circuit  130 . A series of diodes  215 A- 215 H may be driven in differential mode via the amplified signals. An optical signal may be modulated via the diodes  215 A- 215 H, which may be integrated in a Mach-Zehnder modulator  250  or a ring modulator. The diodes  215 A- 215 H may be connected in a distributed configuration. The amplified signals may be communicated to the diodes  215 A- 215 H via even-mode coupled transmission lines  307 A- 307 D. The partial voltage domains may be generated via stacked source follower M 6 -M 9  or emitter follower circuits. The voltage domain boundary value may be at one half the supply voltage due to symmetric stacked circuits. 
         [0063]    While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.