Abstract:
A logic circuit for checking the parity of many bit groups simultaneously and jointly. The parity bits generated by the parity generators are interchanged crosswise, combined with the parity bits contained in the bit groups and applied to a single common output terminal. Consequently, only one specific output must be checked. The checking circuit itself is checked by inverting one of the parity generators periodically.

Description:
This is a continuation of application Ser. No. 696,628, filed Jan. 31, 1985, and now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     The invention relates to an arrangement for checking the parity of parity bit-containing bit groups. 
     Such an arrangement is generally known. 
     If in a system such as a telephone exchange, the parity of a bit group has to be determined in a large number of places, or the parity of many bit groups have to be checked in one place, this requires a large investment in equipment, such as parity generators and convertors. In addition, the result of the comparison between the transmitted parity of the bit group and the parity generated by the parity generator has to be checked, which requires additional hardware. To ensure the reliability of the system all the additional equipment must also be supervised. 
     SUMMARY OF THE INVENTION 
     The invention has for its object to provide an arrangement for checking the parity of parity bit-containing bit groups, with the aid of which the parity can be checked using only few means and with which also the reliability of these means can be supervised. According to the invention, an arrangement for checking the parity of parity bit-containing bit groups is characterized in that a number of n bit groups are checked in parallel. The arrangement comprises n parity generators (PG1, PG2, PG3) each coupled to one bit group for generating the parity of the relevant bit group, and the arrangement further comprises n comparison circuits each having first and second inputs and an output. An output of a parity generator is always connected to a first input of a comparison circuit, and the parity bit of each of the bit groups is applied to the second input of the comparison circuit but in such manner that at a specific comparison circuit the generated parity bit applied to the first input is derived from a different bit group than the parity bit applied to the second input. The outputs of the comparison circuits are connected to a logic network for generating, at a single output terminal of the logic network, a logic signal which has a first value if all the generated parity bits are in agreement with the parity bit contained in the bit groups and a second value if one of the generated parity bits is not in agreement with the parity bit of the associated bit group. 
     An advantageous embodiment of such an arrangement for checking the parity of parity bit-containing bit groups is characterized in that one of the parity generators may have a test input for inverting the parity bit generated at the output of that parity generator, as a result of which the signal generated at the output of the logic network will be inverted if the logic network is correctly operating in the prescribed way. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawing, the sole FIGURE of which shows in block schematic form an arrangement for checking the parity of parity bit containing bit groups. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     References R 1 , R 2  and R 3  denote a number of binary registers for storing a bit group consisting of a data portion D 1 , D 2  and D 3 , respectively and a parity portion P 1 , P 2  and P 3 , respectively. The invention is however not limited to embodiments comprising three registers. The invention can also be used without any drawbacks for any other number of registers. Parity generators PG1, PG2 and PG3 for generating the parity of the bit group data portion present in the data portion of the register are connected to an output of each data portion D 1 , D 2  and D 3  of the registers R 1 , R 2  and R 3 , respectively. 
     An output of each of the parity generators PG 1 , PG 2  and PG 3  and an output of each of the parity portions P 1 , P 2  and P 3  of the registers R 1 , R 2  and R 3  are together connected to a logic circuit LC of which the exclusive OR-circuits EX-OR 1 , EX-OR 2 , EX-OR 3  form part. This is effected in such a way that the inputs of these circuits are connected in a cyclic sequence to outputs of different parity portions and parity generators. This means that the output of the parity portion P 1  of register R 1  is connected to a first input of the exclusive OR-circuit EX-OR 1 , while the output of parity generator PG 2  is connected to a second input of the exclusive OR-circuit EX-OR 1 . Similarly, the output of the parity portion of register R 2  is connected to the first and the output of parity generator PG 3  to the second input of EX-OR 2  and the output of the parity portion of register R 3  is connected to the first and the output of parity generator PG 1  to the second input of EX-OR 3 . Outputs of the exclusive OR-circuits EX-OR 1  and EX-OR 2  are connected to first and second inputs, respectively of a further exclusive OR-circuit EX-OR 4 , while an output of the exclusive OR-circuit EX-OR 3  and an output of EX-OR 4  are connected to a fifth exclusive OR-circuit EX-OR 5 . The output of EX-OR 5  is connected to an output terminal OUT which constitutes the output terminal of the logic circuit LC. 
     The checking circuit operates as follows. If the parities generated by the parity generators PG 1 , PG 2  and PG 3  correspond to the parity which was transmitted and stored in the parity portions P 1 , P 2  and P 3  of the registers, then at output OUT a logic value of a first type will be supplied. In the example shown in the drawing PG 1  =P 1  =&#34;1&#34;, PG 2=P   2  =&#34;0&#34; and PG 3  =P 3  =&#34;1&#34; a signal having the logic value &#34;0&#34; will occur at output OUT. In all cases in which each generated parity (PG i ) corresponds to the parity contained in the corresponding parity portion P i  a logic value &#34;0&#34; will always appear at the output OUT. Consequently, this circuit has the advantage that for every three bit groups (n-bit groups in general) only a single output terminal need to be checked. If an error occurs, so that any of the parity generators generates a parity which differs from the parity bit stored in the register, then the output OUT will assume the second logic value (&#34;1&#34;), which is indicative of the occurrence of an error. 
     Now it may happen that a malfunction occurs in the logic circuit LC causing a logic signal of the first type to be always supplied from the output, so that prevailing errors cannot be indicated anymore. To check this, one of the parity generators PG 1 , PG 2  or PG 3  (in the drawing PG 1 ) is given a test input TST. Applying a suitable signal to the test input TST causes the output of the relevant parity generator (PG 1  in the drawing) to be inverted. When the logic circuit is supplying from the output OUT a logic signal of a first value (e.g. a zero), application of such a test signal should result in this value being inverted to a second value (e.g. a one). If no such inversion occurs, this indicates that the logic circuit LC is operating incorrectly. Inverting one of the parity generators at regular time intervals prevents a the logic circuit LC which becomes defective remaining unnoticed.