Abstract:
An improved technique for mixing picture signals directed at a monitor screen. Two analog video signals (such as an analog VGA input and an analog RGB signal produced in response to a stored digital still or moving image) may be multiplexed in analog form. An analog chromakey mixer detects a background color in the first video signal (such as the analog VGA input), and replaces the portion of that first video signal with the second video signal. The time delays of the first video signal and the second video signal may be adjusted so that they reach the monitor screen (by means of an a multiplexer output) at the same time. An alignment detector may attempt to align two known signals (such as a VGA sync signal and a signal generated for this purpose), and may adjust a set of time delays in the analog chromakey mixer until the time difference between the first and second video signals falls below a threshold.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This invention relates generally to an analog video chromakey mixer and to a method for calibrating and using the same.  
           [0003]    2. Description of Related Art  
           [0004]    When still or moving images in digital form are displayed in a computer system, the digital images must generally be decoded and displayed as images on a computer monitor screen. Typically, the monitor screen is the only monitor screen in the computer system. However, those decoded and displayed images must be coordinated with other display signals directed at the same monitor screen, such as those signals directed that the monitor screen by an RGB or VGA monitor driver. Typically, the two sets of signals directed at the monitor screen must be multiplexed in some way.  
           [0005]    Generally, it is desired that the two sets of signals must be smoothly multiplexed, with no breaks that would be visible to the human eye. It is also generally desired that the two sets of signals should be multiplexed quickly, so that high quality, high speed images may be displayed. It is also generally desired that any method for multiplexing the two sets of signals should work with a wide variety of computer systems and with a minimum of adaptation required for any of them.  
           [0006]    However, one problem that has arisen in the art is that high quality, high speed multiplexing of analog and digital video signals can be difficult. For example, if it were desired to digitize the analog video signals and multiplex them with the digital signals entirely digitally, it could require an A/D converter that produced 16 million colors (24 bits) at a 75 MHz pixel rate. Present A/D converters do not operate at this combination of precision and speed, at least not at anything near a reasonable cost for a personal computer system.  
           [0007]    One method of the prior art has been to multiplex the digital data provided by the computer system&#39;s processor (or CPU) to the monitor driver. While this method sometimes achieves the goal of synchronizing digital and analog video sources, it has the drawback that it requires substantial information about the method of color encoding used by the VGA monitor driver. As monitor drivers have been changed with improvements in monitors and in drivers, this method also has the drawback [that] that it may fall to work for certain classes of monitor drivers.  
           [0008]    Accordingly, it is an object of the invention to provide an improved technique for mixing picture signals directed at a monitor screen.  
         SUMMARY OF THE INVENTION  
         [0009]    The invention provides an improved method for mixing picture signals directed at a monitor screen. In a preferred embodiment, the time delays of the first video signal and the second video signal may be adjusted so that they reach the monitor screen at the same time. An alignment detector may attempt to align two known signals (such as a VGA signal and a video signal), and may adjust a set of time delays until the time difference between the first and second video signals falls below a threshold. Adjustable time delays may include coarse and fine time delays, and may include time delays between any two of—input ports for the first and second video signals, a chromakey detector, an analog multiplexer, and an output port. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    [0010]FIG. 1 shows a video system architecture.  
         [0011]    [0011]FIG. 2 shows a block diagram of an analog chromakey mixer.  
         [0012]    [0012]FIG. 3A shows a preferred calibration process.  
         [0013]    [FIG. 3A] FIG. 3B shows a flowchart for mixing the first video signal  107  and the second video signal  123 .  
         [0014]    [FIG. 3B] FIG. 3C shows a set of display screens before and after chromakey detector calibration.  
         [0015]    [0015]FIG. 4A shows a flowchart for mixing a VGA signal with a video signal to perform the pixel clock frequency calibration.  
         [0016]    [0016]FIGS. 4B and 4C show a VGA signal comprising a uniformly black VGA signal for filling a first window, and a video signal comprising a uniformly white for filling a second window  412 . FIG. 4B shows the two signals before coarse adjustment of the frequency of the pixel clock; and FIG. 4C shows the two signals after coarse adjustment.  
         [0017]    [0017]FIG. 5A shows a flowchart for synchronizing the control signal VRDY with a video signal.  
         [0018]    [0018]FIG. 5B shows the relative positions of the control signal VRDY before and after synchronization with a video signal on the path t 2 .  
         [0019]    [0019]FIG. 6A shows a flowchart for vertical synchronization.  
         [0020]    [0020]FIG. 6B shows a VGA signal comprising a uniformly black VGA signal for filling a first window, and the video signal  123  comprising a uniformly black MPEG signal for filling a second window before the fine adjustment of the left border and the synchronization of the VGA signal with the video signal  123 .  
         [0021]    [0021]FIG. 6C shows the two signals after the fine adjustment of the left border and the synchronization of the VGA signal  107  with the video signal  123 .  
         [0022]    [0022]FIG. 7A shows a flowchart for horizontal synchronization.  
         [0023]    [0023]FIG. 7B shows a VGA signal comprising a uniformly black VGA signal for filling a first window, and a video signal  123  comprising a uniformly black second window before the adjustment of the top border.  
         [0024]    [0024]FIG. 7C shows the two windows after the adjustment of the top border.  
         [0025]    [0025]FIG. 8A shows a flowchart for mixing a VGA signal  107  with a video signal to perform the fine pixel clock calibration.  
         [0026]    [0026]FIG. 8B shows a VGA signal  107  comprising a uniformly black VGA signal for filling a first window, and a video signal comprising a uniformly black for filling a second window.  
         [0027]    [0027]FIG. 8C shows the two signals after the fine adjustment of the pixel clock PCLK. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     System Architecture  
       [0028]    [0028]FIG. 1 shows a video system architecture.  
         [0029]    In a preferred embodiment, a video system  101  embedded in a computer system comprises a VGA input  102 , having a sync input  103  for a horizontal sync (HS) signal  104  and a vertical sync (VS) signal  105 , and having a first video input  106  for a first analog signal  107  (such as an analog RGB video signal). In a preferred embodiment, the VGA input  102  may be coupled to a VGA monitor driver, such as a personal computer system comprising a monitor driver card or another monitor driver circuit. VGA monitor drivers are known in the art. The sync input  103  is coupled to a sync output  108 .  
         [0030]    The sync input  103  and the first analog signal  107  are coupled to an analog chromakey mixer  109 , which detects a key color in the analog RGB video signal and multiplexes the first analog signal  107  with a second analog RGB signal.  
         [0031]    The analog chromakey mixer  109  is coupled to a set of reference voltages  110 , comprising a +5 volt source and a −5 volt source in a preferred embodiment, to a CCLK signal  111  and a CDATA signal  112 , for communication with the computer system, to a PCLK signal  113  and a VRDY signal  114 , and to a second video input  115 . The analog chromakey mixer  109  provides an output FBLANK signal  116  and an output FCLOCK signal  117 , and a video output  118 .  
         [0032]    The sync input  103  is coupled to a digital signal processor (DSP)  119 , which provides a digital video signal  120  having a sequence of digital pixels. The DSP  119  is coupled to the FBLANK signal  116  and the FCLOCK signal  117  from the analog chromakey mixer  109 . The DSP  119  provides the PCLK signal  113  and the VRDY signal  114 .  
         [0033]    The digital video signal  120  is coupled to a video D/A converter  121 , which converts the digital video signal  120  to a second analog signal  122  having a sequence of analog pixels. The second analog signal  122  is coupled to the analog chromakey mixer  109  at the second video input  115 .  
       System Operation  
       [0034]    In a preferred embodiment, the HS signal  104  and the VS signal  105  provide sync information for the first analog signal  107 , and for the multiplexed video signal coupled to the video output  118 .  
         [0035]    The analog chromakey mixer  109  is described in further detail with reference to FIG. 2.  
         [0036]    The reference voltages  110  provide power and logical references for the analog chromakey mixer  109 . Reference voltages are known in the art. In a preferred embodiment, the reference voltages  110  may also be coupled to other circuits for similar purposes.  
         [0037]    The CCLK signal  111  and a CDATA signal  112  are for communication with the computer system. These signals are used by the computer system to program voltage reference levels and internal registers of the analog chromakey mixer chip  109 . Programming [refer ence] reference levels and internal registers of a chip by means of input signals is known in the art.  
         [0038]    The PCLK signal  113  is a clock for the VRDY signal  114 . The VRDY signal  114  indicates whether a digital pixel in a digital video signal  120  comprises valid data.  
         [0039]    The FBLANK signal  116  provides a composite blanking signal for the DSP  119 . The FCLOCK signal  117  provides a pixel clock for the DSP  119 .  
         [0040]    In a preferred embodiment, the DSP  119  may comprise the Piccolo chip (available from Sigma Designs, Inc., of Fremont, Calif.).  
         [0041]    In a preferred embodiment, the digital video signal  120  comprises a sequence of digital pixels, each having 8 bits of precision for each of three colors (red, green, and blue), at a rate of about 20 nanoseconds per digital pixel.  
         [0042]    The D/A converter  121  converts each digital pixel to a set of three analog voltages, one for each of three colors. D/A converters are known in the art. In a preferred embodiment, the D/A converter  121  may comprise the BT 121  device (available from Brooktree Corporation of San Diego, Calif.).  
       Analog Chromakey Mixer  
       [0043]    [0043]FIG. 2 shows a block diagram of an analog chromakey mixer.  
         [0044]    In a preferred embodiment, the HS signal  104  is coupled to a line locked phase locked loop (PLL)  201 , which recovers a clock signal from the HS signal  104 . Phase locked loops are known in the art. The line locked PLL  201  is coupled to a phase adjuster  202 , which provides an adjustable delay. An output of the phase adjuster  202  provides the FCLOCK signal  117 . The phase adjuster  202  is coupled to a counter  203 , which provides the FBLANK signal  116 .  
         [0045]    The HS signal  104  and the VS signal  105  are coupled to a polarity detector  204 . In a preferred embodiment, the HS signal  104  and the VS signal  105  may have any polarity. The polarity detector  201  uses the FCLOCK signal  117  to sample the HS signal  104 ; if the same value is sampled for more than  256  consecutive clock pulses, that value is considered to represent the inverse of the polarity of the HS signal  104 . Similarly, the polarity detector  201  uses the FCLOCK signal  117  to sample the VS signal  105 ; if the same value is sampled for more than 256 consecutive clock pulses, that value is considered to represent the inverse of the polarity of the VS signal  105 .  
         [0046]    The first analog signal  107  is coupled to a chromakey detector  205 , which determines whether a present analog pixel of the analog RGB video signal matches the color to be replaced (the chromakey). The chromakey detector  205  is coupled to a set of six D/A converters  206  that provide a set of three minimum/maximum values for the red (R), green (G), and blue (B) color components of the analog RGB video signal. The chromakey detector  205  determines a color match when the detected color falls within the minimum/maximum values for all three color components, and generates a match signal  208 .  
         [0047]    The first analog signal  107  is coupled by means of a delay  207  to a first input of an analog multiplexer  209 .  
         [0048]    The CCLK signal  111  and the CDATA signal  112  are coupled to a control circuit  210 , for programming voltage reference levels and internal registers of the analog chromakey mixer chip  109 . Programming reference levels and internal registers of a chip by means of input signals is known in the art.  
         [0049]    The PCLK signal  113  is used to clock the VRDY signal  114  to an input of a programmable delay  211 , which provides an output VRDY  1  signal  212 . The VRDY 1  signal  212  is coupled to a fine delay  213 , which provides an output VRDY 2  signal  214 . The VRDY 2  signal  214  is coupled to an input of a logical AND gate  215 .  
         [0050]    The match signal  208  is coupled to another input of the logical AND gate  215 . An output of the logical AND gate  215  is coupled to a select input of the analog multiplexer  209 . The second analog signal  122  is coupled to a second input of the analog multiplexer  209 . An output of the analog multiplexer  209  is coupled to the video output  118 .  
       Analog Chromakey Mixer Operation  
       [0051]    In a preferred embodiment, the chromakey detector  205  detects the chromakey in the first analog signal  107 ; the match signal  208  indicates that the chromakey detector  205  found a match. When a match is found, at the next valid pixel from the D/A converter  121 , the match signal  208  and VRDY signal  114  will both be logical “1”, and the logical AND gate  215  will cause the analog multiplexer  209  to select the second analog signal  122  instead of the first analog signal  107 . This mixing operation requires a series of calibration steps to ensure that the two signals mix seamlessly, thereby avoiding offset or blurred images of the combined signals as displayed on a monitor. Note that VRDY  114  is triggered whenever the second video signal  123 , such as an MPEG video stream comprised of signals  120  and  122 , is available for D/A conversion, mixing, and display.  
       Seamless Mixing and Synchronization  
       [0052]    Achieving seamless mixing of the two analog signals  107 ,  122  requires synchronizing control signal VRDY  114  with video signal  123  which travel down paths t 1  and t 2 , respectively; and synchronizing first analog signal  107  with second signal  122  which travel along paths t 3  and t 4 , respectively.  
         [0053]    Synchronizing control signal VRDY  114  with video signal [ 123 ]  122  is achieved by introducing adjustable delays along path t 1 . Time delays t 284 , t 285 , t 273 , t 274  comprise the [cumumlative] cumulative time delay for path t 1 , where programmable delay  211  and fine delay adjustment  213  provide adjustable time delays t 284 , t 285 . Time delays t 264 ,  1265  comprise the cumulative time delay for path t 2  and are not adjustable. Since the two signals are mixed only when the logical AND gate  215  is triggered by match signal  208  and VRDY 1   212 , VRDY  114  must be delayed sufficiently along path t 1  to allow the digital video signal to “catch-up” or arrive at the mulitiplexer at the moment VRDY  114  triggers logical AND gate  215 . Consequently, programmable delay  211  and fine delay adjustment  213  are used to delay VRDY  114  along path t 1  by producing adjustable delay times  1284  and t 285 , respectively.  
         [0054]    Synchronizing the VGA signal  107  with the video signal  123  is achieved by introducing adjustable delays serially along paths t 3  and t 4 . Time delays t 251 , t 252 , and t 253  comprise the cumulative time delay for path t 3 , with delay matching  207  providing time delay  1252  which is adjustable. Time delays t 261 , t 262 , t 283 ,  1264  and t 265  comprise the cumulative time delay for path t 4 . Time delay  1262  is adjustable and is provided by phase adjustment  202 .  
         [0055]    For each of the adjustable time delay elements, including programmable delay  211 , fine delay adjustment  213 , delay matching  207 , and phase adjustment  202 , a register (not shown) is provided for setting the amount of time delay required for synchronization. Each of the registers can be adjusted to provide or can receive a time delay amount by external means.  
       Calibration  
       [0056]    In the following description, a preferred embodiment of the calibration techniques used in the invention is described with regard to preferred process steps and data structures. However, those skilled in the art would recognize, after perusal of this application, that embodiments of the invention may be implemented using a general purpose processor coupled to a memory and operating under program control, or other suitable test equipment, which selects signals and data for use by apparatus shown in FIG. 1 and FIG. 2, and that modification of a general purpose processor to implement the process steps and data structures described herein would not require undue invention.  
         [0057]    For example, as described in further detail with regard to FIG. 4A, FIG. 413, and FIG. 4C, the processor tests the chromakey detector  205  by selecting one or more digital values for input to the D/A converters  206  and storing those selected digital values in registers used by the D/A converters  206 . Storing selected digital values in registers is known in the art of semiconductor chip design.  
         [0058]    For another example, as described in further detail with regard to FIG. 6A and FIG. 6B, as well as with regard to FIG. 7A and FIG. 713, and FIG. 8A and FIG. 813, the processor tests the synchronization of VGA input signals with video input signals by selecting VGA input signals to be presented at the “VGA RGB in” node and by selecting video input signals to be presented at the “video RGB in” node. In a preferred embodiment, the selected VGA input signals and the selected video input signals are retrieved from the memory and transmitted from the processor to the “VGA  
         [0059]    RGB in” node and to the “video RGB in” node. Selecting and transmitting VGA or video signals from a processor to an input node is known in the art.  
         [0060]    [0060]FIG. 3A shows a preferred synchronization process.  
         [0061]    At a step  301 , the chromakey detector  205  is calibrated by selecting a chromakey having a selected white level (thus, a shade of grey), and by presenting a set of VGA input signals having selected white levels, and by detecting the resultant first analog signal  107 . The step  301  is described in further detail with regard to FIG. 3B.  
         [0062]    At a step  302 , the frequency of the pixel clock PCLK  113  is calibrated by coarse adjustment of a left border of a video input. The step  302  is described in further detail with regard to FIG. 4A and FIG. 4B and FIG. 4C.  
         [0063]    At a step  303 , the analog mux  209  is calibrated by synchronizing the control signal VRDY  114  on path t 1  and the video signal  123  on path t 2 , respectively. The step  303  is described in further detail with regard to figure  5 A and FIG. 5B.  
         [0064]    At a step  304 , the VGA input signal and the video input signal are vertically synchronized by adjusting a left border of the VGA signal  107  on the path t 3  and the video signal  123  on the path t 4 . The step  304  is described in further detail with regard to FIG. 6A, FIG. 6B and FIG. 6C.  
         [0065]    At a step  305 , the VGA input signal and the video input signal are horizontally synchronized by adjusting a left border of the VGA signal  107  on the path t 3  and the video signal  123  on the path t 4 . The step  304  is described in further detail with regard to FIG. 7A, FIG. 7B and FIG. 7C.  
       Chromakey Detector Calibration  
       [0066]    [0066]FIG. 3B shows a flowchart for mixing the VGA signal  107  and the video signal  123 .  
         [0067]    [0067]FIG. 3C shows a set of display screens before and after chromakey detector calibration.  
         [0068]    The VGA signal  107  comprises a VGA signal filling a rectilinear window on the display screen; this VGA signal is uniformly black in color (thus, it has red, green, and blue components each equal to zero). The video signal  123  comprises an MPEG video signal which is also uniformly black in color.  
         [0069]    As used herein, the term “window” includes any set of VGA or video data sized to fit in a selected set of pixels on the screen. Video data includes any stream of selected pixel data such as a pixel stream in the MPEG format.  
         [0070]    In a preferred embodiment, the following steps are performed as part of chromakey detector calibration.  
         [0071]    At a step  350 , a uniformly black MPEG image is selected for input as the video signal  123 , for filling a first window  312 , and a uniformly white VGA image is selected for input as the VGA signal, for filling a second window  310 .  
         [0072]    At a step  352 , the minimum key color for the chromakey detector  205  is set to zero. Thus, the minimum red color at the D/A converter  206  is set to zero, the minimum green color at the D/A converter  206  is set to zero, and the minimum blue color at the D/A converter  206  is set to zero.  
         [0073]    At a step  353 , the maximum key color for the chromakey detector  205  is set to 128 (thus, the maximum key colors for red, green, and blue at the D/A converter  206  are each set to 128), and the alignment detection circuit  216  is examined to determine if the white VGA image is detected. The maximum key color is repeatedly incremented from 128 to its maximum possible value of 255 until the alignment detection circuit  216  detects the white VGA image.  
         [0074]    At a step  354 , if the white VGA image signal was detected, the maximum key color is further incremented a few more steps (such as about 2 to about 4 steps out of 256 possible steps) to obtain a margin of error.  
         [0075]    At a step  355 , the minimum key color is similarly scanned from 0 to 255 until the alignment detection circuit  216  detects the white VGA image, and if so, decremented a few more steps (such as about 2 to about 4 steps) to obtain a margin of error.  
       Pixel Clock Frequency Calibration  
       [0076]    [0076]FIG. 4A shows a flowchart for mixing the VGA signal  107  with the video signal  123  to perform the pixel clock frequency calibration.  
         [0077]    [0077]FIGS. 4B and 4C show the VGA signal  107  comprising a uniformly black VGA signal for filling a first window  410 , and the video signal  123  comprising a uniformly white signal for filling a second window  412 . The second window  412  comprises a small white square. FIG. 4B shows the two signals before coarse adjustment of the frequency of the pixel clock PCLK  113 ; FIG. 4C shows the two signals after coarse adjustment.  
         [0078]    In a preferred embodiment, the following steps are performed as part of coarse adjustment of the frequency of the pixel clock PCLK  113 .  
         [0079]    At a step  401 , the VGA signal is selected so that the top and left border of the first window  410  are aligned with (thus, offset zero pixels from) from an upper left corner of the display screen, and so that the size of the first window  410  covers the entire display screen.  
         [0080]    At a step  402 , the video signal  123  is selected to comprise a 25% white MPEG signal for filling a second window  412  (thus, the red value for this MPEG signal is 25% of the maximum possible value, the green value is 25% of the maximum possible value, and the blue value is 25% of the maximum possible value). The second window  412  comprises a relatively small white square.  
         [0081]    At a step  403 , the second window  412  is positioned so that it lies under a black area  416  of the the first window  410 , so that if the pixel clock frequency is correct, only a single vertical white line  420  on the right side will overlap a grey area  418  of the first window  410 . Otherwise, if the pixel clock frequency is too low, the second window  412  will be at a (detectable) position  422  within the black area  424 .  
         [0082]    At a step  404 , the pixel clock frequency is repeated decremented from about 65 MHz to about 20 MHz, and the alignment detection circuit  216  is examined to determine if it detects the second window  412 . When the alignment detection circuit  216  does detect the second window  412 , the frequency of the pixel clock PCLK  113  is then known to be approximately correct. In a preferred embodiment, the actual time per frame is determined by averaging over several frames, preferably about twenty frames.  
         [0083]    At a step  405 , if the pixel clock frequency reaches 20 MHz without the pulse detection circuit detecting a pulse, the Piccolo Chip  119  zooms the MPEG window by a factor of two and the process returns to repeat the step  404 .  
       Analog Mux Synchronization  
       [0084]    [0084]FIG. 5A shows a flowchart for synchronizing the control signal VRDY  114  with the video signal  123 .  
         [0085]    [0085]FIG. 5B shows the relative positions of the control signal VRDY  114  before and after synchronization with the video signal  123  on the path t 2 .  
         [0086]    In a preferred embodiment, the following steps are performed as part of synchronizing the control signal VRDY  114  with the second signal  123 .  
         [0087]    At a step  501 , video signal is aligned with the upper left comer (thus, the offsets from the top and left borders are set to zero). The video signal is selected to comprise a primarily black MPEG signal for a first window  510 , having a uniformly white vertical line  512  superimposed thereon.  
         [0088]    At a step  502 , the VGA signal is selected to comprise a primarily black first window  514 .  
         [0089]    At a step  503 , a control signal is entered to temporarily disable the chromakey detector  205 .  
         [0090]    At a step  504 , the video signal is selected so as to comprise a tall and narrow, two pixel wide source window and destination window  516 .  
         [0091]    At a step  505 , the coarse delay  1284  is set to zero and the fine delay t 285  is set to eight pixels (thus about 320 nanoseconds).  
         [0092]    At a step  506 , the coarse delay  1284  is measured by repeatedly incrementing the destination window horizontal position by one until the alignment detection circuit  216  detects the white vertical line  512 . When the white vertical line  512  is detected, the coarse delay t 284  is approximately known.  
         [0093]    At a step  507 , the coarse delay t 284  is set according to the value determined in the step  506 .  
         [0094]    At a step  508 , the fine delay t 285  is similarly adjusted. The video signal is selected so as to comprise a one pixel wide source and destination window; the horizontal position of the destination window is repeatedly incremented until the alignment detection circuit  216  detects the white vertical line  512 . When the white vertical line  512  is detected, the fine delay t 285  is known.  
       Vertical Synchronization  
       [0095]    [0095]FIG. 6A shows a flowchart for vertical synchronization.  
         [0096]    [0096]FIG. 6B shows the VGA signal  107  comprising a uniformly black VGA signal for filling a first window  610 , and the video signal  123  comprising a uniformly black MPEG signal for filling a second window  612  before the fine adjustment of the left border and the synchronization of the VGA signal  107  with the video signal  123 .  
         [0097]    [0097]FIG. 6C shows the two signals after fine adjustment of the left border and synchronization of the VGA signal  107  with the video signal  123 .  
         [0098]    In the preferred embodiment, adjustment of the left border and synchronization of the VGA signal  107  with second video signal  123  include the following steps.  
         [0099]    At a step  601 , the VGA signal  107  is aligned with the upper left comer of the display screen (thus, the offsets from the top and left borders are set to zero).  
         [0100]    At a step  602 , the fine delay t 285  for the clock is programmed to a midrange value such as eight pixels (thus, about 320 nanoseconds).  
         [0101]    At a step  603 , the-video signal  123  is selected to comprise a primarily black MPEG picture  612  with a white vertical line  614 .  
         [0102]    At a step  604 , the VGA signal  107  is selected to comprise a larger black VGA window  610  with a two pixel wide  25 % white vertical line  616 .  
         [0103]    At a step  605 , the chromakey detector is set to use a chromakey of 25% white (thus, 25% red, 25% green, and 25% blue).  
         [0104]    At a step  606 , the left border of the video signal  123  generated by the Piccolo is adjusted until the alignment detection circuit  216  detects a pulse, thereby completing the left border adjustment.  
         [0105]    In a preferred embodiment, fine synchronization of the VGA signal  107  with the video signal  123  includes the steps  610  through  611 .  
         [0106]    At a step  610 , the VGA window  610  is redrawn with a 1 pixel wide 25% white vertical line  516 .  
         [0107]    At a step  611 , the clock fine delay  1285  is adjusted until the alignment detection circuit  216  detects a pulse.  
         [0108]    In the preferred embodiment of the present invention, the adjustments immediately above take place on the left side of the screen, so that any inaccuracy caused by an inaccurate pixel clock frequency will minimize any error.  
         [0109]    An MPEG picture  618  with a white [horizontal] vertical line  620  is shown after completion of the above calibration steps.  
       Horizontal Synchronization  
       [0110]    [0110]FIG. 7A shows a flowchart for horizontal synchronization.  
         [0111]    [0111]FIG. 7B shows the VGA signal  107  comprising a uniformly black VGA signal for filling a first window  710 , and the video signal  123  comprising a uniformly black second window  712  before the adjustment of the top border.  
         [0112]    [0112]FIG. 7C shows the two windows after the adjustment of the top border.  
         [0113]    In the preferred embodiment, the following steps are performed as part of the adjustment of the top border  710 .  
         [0114]    At a step  701 , the left border is programmed to zero by selecting a VGA signal  107  so that the left border of the first window  710  are zero pixels offset from the left side of the display screen.  
         [0115]    At a step  702 , the video signal  123  is selected so that a primarily black second window  712  is drawn with a white horizontal line  714  stretching horizontally across the top of the second window  712  is displayed.  
         [0116]    At a step  703 , a VGA signal  107  is selected so that the first window  710  is uniformly black and has a 25% white horizontal line  716  stretching across the top of the first window  710 . Thus, the pixels representing the 25% white horizontal line  716  are comprised of a red value is 25% of the maximum possible value, the green value is 25% of the maximum possible value, and the blue value is 25% of the maximum possible value.  
         [0117]    At a step  704 , the key color for the chromakey detector  205  is set to 25% white by setting the minimum red color at the D/A converter  206  to 25% of the maximum possible value, the minimum green color at the D/A converter  206  is set to 25% of the maximum possible value, and the minimum blue color at the D/A converter  206  is set to 25% of the maximum possible value.  
         [0118]    And at step  705 , the Piccolo Chip  119  is adjusted to create a video signal  123  having pixels matching the 25% white key color set for the chromakey detector  205  in step  704  so that the pulse detection circuit  216  detects a pulse.  
         [0119]    MPEG picture  718  with a white horizontal line  720  is shown after completion of the above calibration steps.  
       Fine Pixel Clock Calibration  
       [0120]    [0120]FIG. 8A shows a flowchart for mixing the VGA signal  107  with video signal  123  to perform the fine pixel clock calibration.  
         [0121]    [0121]FIG. 8B shows the VGA signal  107  comprising a uniformly black VGA signal for filling a first window  810 , and the video signal  123  comprising a uniformly black for filling a second window  812 .  
         [0122]    [0122]FIG. 8C shows the two signals after the fine adjustment of the pixel clock PCLK  113 .  
         [0123]    The VGA signal  107  comprises a VGA signal filling a rectilinear window on the display screen; this VGA signal is uniformly black in color (thus, it has zero red, green, and blue components). The second video signal  123  comprises an MPEG video signal which is also uniformly black in color.  
         [0124]    As used herein, the term “window” includes any set of VGA or video data sized to fit in a selected set of pixels on the screen. Video data includes any stream of selected pixel data such as a pixel stream in the MPEG format.  
         [0125]    In the preferred embodiment, the following steps are performed as part of the fine adjustment of the pixel clock frequency using PCLK  113 .  
         [0126]    At a step  801 , a uniformly black VGA image is selected for input as the VGA signal  107 , for filling a first window  810 , and a uniformly white MPEG image is selected for input as the video signal, for filling a second window  812 .  
         [0127]    At a step  802 , the left border is offset by the number of pixels determined by the previous calibration steps [ 701  through  708 ]  601  through  611 .  
         [0128]    At a step  802 , the top border is offset by the number of pixels determined in the previous calibration steps  701  through [ 706 ]  705 .  
         [0129]    At a step  803 , a first window  810  that spans the whole screen is drawn using the VGA signal  107 .  
         [0130]    At a step  804 , a small white square  812  for the second window  812  is created using the video signal  123 .  
         [0131]    At a step  805 , the key color for the chromakey detector  205  is set to 25% white by setting the minimum red color at the D/A converter  206  to 25% of the minimum possible value, the minimum green color at the D/A converter  206  is set to the minimum possible value, and the minimum blue color at the D/A converter  206  is set to the minimum possible value. This creates a grey border  814  around the first window  810 .  
         [0132]    At a step  806 , the white square  812  created by the video signal  123  is offset by a number of pixels so that the white square  812  is positioned under the black area  816 , so that if the frequency of the pixel clock PCLK  113  is correct, one vertical white line  818  on the right side of the small white square  812  overlaps the inside edge of the grey border of the first window area  820 , as shown in FIG. 8C.  
         [0133]    At a step  807 , the frequency of the pixel clock PCLK  113  is decreased from slightly higher than the coarse pixel clock found in calibration steps  501  through  505  until the pulse detection is active, thereby giving an accurate clock frequency.  
         [0134]    In the preferred embodiment of the present invention, the alignment detection circuit  216  senses the VGA RGB output  118  and is enabled for detection when VRDY  114  is at a logical “1” state. Once enabled, the alignment detection circuit  216  senses when the GREEN video signal exceeds a selected threshold voltage. In a preferred embodiment, the alignment detection circuit  216  detects a pulse any time the GREEN video signal exceeds 0.5 volts for more than a selected threshold time period, such as about 40 nanoseconds:  
         [0135]    While preferred embodiments are disclosed herein, many variations are possible which remain within the concept and scope of the invention, and these variations would become clear to one of ordinary skill in the art after perusal of the specification, drawings and claims herein.