Abstract:
A circuit for processing the control signal inputs for a control data signal decoder wherein a reference voltage and a reference current are generated for use in processing a stream of control signal bits. The control signal data stream is filtered, buffered and exponentialed. The processing serves to cancel out variations in temperature, resistance, process variations and circuit voltages to yield a stable control signal current.

Description:
BACKGROUND OF THE INVENTION 
     This invention pertains to a temperature and process variation compensation technique and a circuit incorporating said technique for use in processing a stream of control signal bits. The control signal data stream is filtered, buffered an exponentialed. The processing serves for use in a delta modulation decoder integrated circuit for high quality audio systems. The integrated circuit of this invention is a decoder for the receiver of a digital audio broadcasting system, the decoder having input logic and linear circuits capable of decoding two channels of delta modulated digital data. 
     The decoder receives three data bit streams that represent the audio information to be decoded. Two of these streams are control data bits, while one stream is the audio data bit stream. Clock bits are also received by the decoder. Each of the three data bit streams can be several channels of time multiplexed data. The clock is used as a strobe to select two of the channels . The circuit disclosed herein is suitable for the decoder. 
     The input logic of the decoder includes a number of edge triggered D flip-fops which are used as input latches to store the two channels of audio and control data. 
     The two control data bit streams for each channel are for step-size and system de-emphasis control. A current I SS  is used to generate the amplitude of the output signal. A current I SB  is used to control the frequency response. Since both currents are generated by the same circuit, this specification will discuss only one of them, I SS . Information for the control data is encoded logarithmically in the duty cycle of the bit stream. For each of the control data bit streams, a three-pole, 80 Hz., low-pass filter is used to detect the average or DC value of the duty cycle. The resulting control voltage is then exponentiated to expand the control signal into a 48 dB range. 
     SUMMARY OF THE INVENTION 
     To maintain the system accuracy it is necessary to have precise control of the pulse height to be filtered. This is accomplished by using a switching amplifier to drive the low-pass filter. The latch output of the flip-flop sets the switching rate between two voltage levels, V L  and V H . These voltages are generated in a bandgap reference circuit which produces a voltage V B  that is nearly independent of temperature, supply and process variations. VBG is scaled up to a voltage V 3  and results in a fixed reference voltage V L . V M  is chosen to be 40% of V H  -V L . A low temperature coefficient reference current I REF  is generated by an external resistor and is used in the exponentiator circuit. The control signal at the output of the low pass filter is buffered by an amplifier and attenuated by resistors to reduce any accumulated offset errors. The collector current of the actual exponentiating transistor is the control signal current I SS . To properly bias this transistor and the other exponentiating transistors, a reference voltage generator circuit is incorporated. 
     The temperature and process spread compensation technique discolsed in this application allows the control signal I SS  within the integrated circuit to be relatively independent of variations in temperature, process spreadings, resistance and V CC . The effect of this compensation is to allow the use of the IC over a wide temperature range without the loss of performance and to increase the manufacturing yield of the IC. 
     The rest of the circuit is devoted to the processing of the audio signal as a function of the control data which has passed through the compensation technique of the present invention. The circuit is designed such that by use of a reference voltage and a reference current, variations of internal resistance and temperature can be cancelled to yield control signals that are independent of temperature, voltage and resistance as well as manufacturing variations. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The FIGURE is a circuit diagram of the input logic, the reference generator and the exponentiator circuits used in the compensation technique of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Before discussing in detail the preferred embodiment as illustrated in the FIGURE, the definitions and equations used in the design of the circuit will be presented. 
     A. Definitions 
     a=duty cycle 
     c=constant 
     I s  =transistor saturation current 
     V T  =KT/q, the voltage equivalent of temprature 
     I PTAT  =current proportional to absolute temperature 
     V BG  =band gap reference voltage 
     R EX  =external resistor 
     V be  =base to emitter voltage 
     The part of a delta demodulation decoder shown in the FIGURE is designed for use in a digital audio broadcasting system. The FIGURE illustrates that part of the circuit which generates control currents. The decoder receives three data bit streams which represent the audio information to be decoded. Two of these are the control data bit streams, and one is the audio data bit stream. A clock signal is also received. Each of the data bit streams can be several channels of time multiplexed data. The clock is used as a strobe to select two of the channels of time multiplexed data for the decoder. In the discussion that follows duplicate components for the various channels will not be discussed and are not shown in the drawings. 
     The input to the temperative compensation section of the delta demodulation decoder using the present invention are two channels of audio and control data. A number of edge triggered D flip-flops 12, of which one is shown in FIG. 1, are used as input latches to store two channels of audio and control data. The clock is inverted internally to strobe the second channel. The FIGURE shows the configuration of the input logic circuits. The input buffers 14 have TTL thresholds and high input impedance which allows interfacing with both TTL and CMOS logic families. Since the present invention pertains to a compensation technique which allows the control signals within the decoder IC to be relatively independent of temperature, resistance, process variations and VCC, the description of the preferred embodiment will concentrate on the handling of the control bit streams in the circuit illustrated in the FIGURE. The control current I SS , which is used to generate the amplitude of the output signal will be used as an example. 
     The two control data bits for each channel are for the step-size (SSB) and system de-emphasis (SBD) control. The information for the control data is encoded logarithmically in the duty cycle of the bit stream. For each of the control data bit streams, a three-pole 80 Hz., low-pass filter 16 is used to detect the average or DC value of the duty cycle. The resultant voltage is then exponentiated to expand the control signal into a 48 dB range. 
     To maintain system accuracy it is necessary to have precise control of the pulse height to be filtered. This is accomplished by using a switching amplifier 18 to drive the low-pass filter 16. As shown in the FIGURE, the latch output flip-flop 12 sets the switching rate between two voltage levels V L  and V H . These voltages are generated in the bandgap reference circuit 20 which produces a voltage VBG that is nearly independent of temperature, supply, the process variations. VBG is scaled up to a voltage V 3  and results in the fixed reference voltage V L  as follows: 
     
         I.sub.10 =V.sub.BG /R.sub.10 
    
     
         I.sub.11 =I.sub.10 +I.sub.B, 
    
     where I B  is the base current and considered negligible therefore I 10  =I 11  ##EQU1## Q 7  collector current is I PTAT  and ideally Q 6  collector current should be I PTAT . Under these conditions V L  would have the same temperature dependence as V 3  if the temperature coefficeint of NPN&#39;s equals the TC of PNP&#39;s. Therefore V 3  is proportional to V BG  and has the same temperature coefficient. V M  is chosen to be 40% of V H  -V L . V H  is a temperature sensitive voltage chosen to compensate for the temperature changes in V be  discussed infra. A low temperature coefficient current I REF  is generated by resistor R EX , an external resistor, and is used in the exponentiator circuit. 
     
         V.sub.4 =V.sub.3 +V.sub.be (Q.sub.A)-V.sub.be (Q.sub.5) 
    
     setting 
     
         V.sub.be (Q.sub.4)=V.sub.be (Q.sub.5), 
    
     then 
     
         V.sub.4 =V.sub.3 
    
     and ##EQU2## 
     The control signal at the ouput of the low-pass filter 16 is buffered by amplifier 22 and attenuated by resistors R 4  and R 5 . The voltage buffered by amplifier 22 is aV H  which is the average DC value of the bit stream of the duty cycle. R 4  and R 5  are chosen such that ##EQU3## Hence the attenuated voltage, whcih is the input to the exponentiator, is aV H  /9. This voltage is temperature dependent. 
     The actual exponentiating transistor is Q 1  and its collector current is the control signal current. This current is in effect I SS . To properly bias Q 1  and the other exponentiating transistors, a V R  generator circuit is provided using transistor Q 2 , amplifier A 2  and the reference current I REF . Amplifier A 2  forces the base of Q 2  to be equal to V M  /9 and the emitter voltage to be ##EQU4## Therefore the base emitter voltage ##EQU5## Since the current in Q 2  is fixed (for a given temperature), the V be  of Q 2  is constant, which sets a constant reference voltage, V R , for the exponentiating transistor Q 1 . 
     The output of the exponentiating transistor Q 1  is a current I 1 , which, depending on the circuit, is either I SS  (step-size control) or I SB  (system de-emphasis control) and which is independent of temperature, internal resistance and power supply. The circuit achieves this goal in the following fashion. Referring to the definitions where &#34;a&#34; is the duty cycle, &#34;c&#34; is a constant and the equation V T  =KT/q, for the voltage equivalent of temperature, the difference between the base emitter voltage of transistors Q 1  and Q 2  is expressed: ##EQU6## Since: I 1  =collector current of Q 1   
     I 2  =collector current of Q 2   
     I s1  =I s2  for purposes of this exposition, and 
     
         I.sub.2 =I.sub.REF                                         (2) 
    
       (the reference current); 
     therefore, referring to equations (2) into equation (1) yields: ##EQU7## 
     Since the actual voltage at the bases of Q 1  and Q 2  is known, substituting these values in equation (3) yields: ##EQU8## From which equation (5) follows: ##EQU9## 
     At this point it should be remarked that the base currents of transistors Q 1  and Q 2  have been neglected because they have no substantial impact on the value of the current I 1 , which is the output of the exponentiator. Equation (5) yields the value of I 1 . To show that this value is independent of resistance and temperature we consider equations (6) through (9). ##EQU10## where R=an internal resistor. ##EQU11## 
     From equation (7) it can be shown that V H  is not changed from variations in resistance. ##EQU12## 
     Then substituting equation (9) into equation (5) yields equation (10) for the output current of the exponentiator. ##EQU13## 
     From equation 10 it can be shown that I 1  is not changed from variations in temperature or resistance. Then, cancelling ##EQU14## 
     The input signals to the exponentiator are purposely made temperature dependent and in particular dependent on the absolute temperature because the conversion of a voltage to a current is temperature dependent. Therefore, the two temperature dependencies are cancelled in the exponentiator. V H  is temperature dependent because of I PTAT . The resistance is cancelled out in the generation of I PTAT  through R 1  and R 2  as shown in equation (7). Therefore V H  is independent of the resistance. 
     The result of this technique is that the performance of the IC will be constant in spite of variations of temperature, process spreadings, internal resistance and V CC . The frequency response and the gain of the circuit are controlled by the transmitted control bits, which have now been made independent of these variable since the output of the various exponentiators will be either I SS . 
     Once the audio data is put into two channels in the circuit, it is sent to a multiplier circuit or variable impedance circuit. In a delta modulation system encoder, the audio data bits represent the signal slope of the input samples. 
     Thus the circuit and technique of the present invention provide the basis for a two channel decoder for use in a digital audio broadcasting system.