Abstract:
A method and system for compressing an asynchronous transfer mode (ATM) header suitable for wireless ATM systems is provided. The ATM Virtual Path Identifier (VPI) and Virtual Channel Identifier (VCI) are replaced with four and eight bit pointers, respectively. In addition, Generic Flow Control (GFC) and Header Error Control (HEC) fields are removed.

Description:
CLAIM OF PRIORITY FROM A COPENDING PROVISIONAL PATENT APPLICATION 
   This patent application claims priority from U.S. Provisional Patent Application No. 60/375,097, filed 22 Apr. 2002, incorporated by reference herein in its entirety. 

   FIELD OF THE INVENTION 
   This invention relates to wireless communications systems and, more particularly, to wireless data communication systems that use asynchronous transfer mode (ATM) data packets. 
   BACKGROUND OF THE INVENTION 
   An ATM switch receives an ATM cell (i.e., packet) across a link with a known virtual channel identifier (VCI), or virtual path identifier (VPI) value. The ATM switch looks up a connection value in a local translation table to determine the outgoing port (or ports) of the connection, as well as the new VPI/VCI value of the connection on that link. The ATM switch then retransmits the cell on that outgoing link with the new connection identifiers (VPI/VCI values). An ATM signaling process is used to set up the local translation tables prior to the transmittal of any data. The ATM signaling is initiated by an ATM node that desires to set up a connection through an ATM network. The signaling is then routed through the ATM network, from ATM switch to ATM switch, setting up the connection identifiers (VPI/VCI) as it goes, until it reaches the destination (end) ATM node. The end node can either accept and confirm the connection request, or it can reject it and clear the connection. In general, the ATM is a cell switching technology that uses fixed-size cells (53 bytes). 
   However, in bandwidth-constrained ATM links, such as those encountered using wireless (i.e., RF) ATM links, it is desirable to provide a method and system that allows ATM cell traffic, but with a reduced number of bits in order to conserve bandwidth. 
   SUMMARY OF THE INVENTION 
   A method is disclosed for compressing an ATM header having a virtual path identifier (VPI) and a virtual channel identifier (VCI). The method includes storing a plurality of VPIs, and associating a unique ATM 4-bit VPI pointer with each of the plurality of stored VPIs. The method also includes storing a plurality of 16-bit VCIs, and associating a unique ATM 8-bit VCI pointer with each of the plurality of stored VCIs. The method then determines the unique ATM 4-bit VPI pointer associated with a VPI stored in an ATM header VPI location, and determines the unique ATM 8-bit VCI pointer associated with a VCI stored in the ATM header VCI location, and uses these determined values for processing the ATM header. 
   This invention also provides a two byte asynchronous transfer mode (ATM) header structure suitable for wireless ATM communication systems. The two data bytes include a 12-bit virtual path identifier (VPI) and virtual channel identifier (VCI), a 3-bit payload type identifier (PTI); and a 1-bit cell loss priority (CLP). 
   A method is disclosed for reducing transmission overhead over wireless links. The method includes providing an ATM cell having an ATM header and then compressing the ATM header. The ATM cell with the compressed ATM header is then transmitted, such as over a wireless link, to an end destination, where, upon receiving the ATM cell with the compressed ATM header, the header is decompressed. 
   In a further embodiment this invention provides a system for reducing overhead in a wireless data communications system that employs ATM cells. The system includes a first memory for storing a plurality of VPIs, where each of the plurality of VPIs is associated with a corresponding unique first memory storage address. The system also includes a second memory for storing a plurality of VCIs, where each of the plurality of VCIs is associated with a corresponding unique second memory storage address. The system further includes an address translation unit (ATU) for receiving and translating an ATM header, according to the corresponding unique memory storage addresses. The ATU operates to clear the VPI and VCI fields and to store the unique first and second memory addresses in the least significant bits of the respective VPI and VCI fields. The system includes a framer device for truncating the VPI and VCI field bit locations, removing a header error correction (HEC) field and/or a Generic Flow Control (GFC) Field. The system also includes a receiver for decompressing the compressed ATM header. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing aspects and other features of this invention are explained in the following description, intended to be read in conjunction with the accompanying drawings, wherein: 
       FIG. 1  represents an Asynchronous Transfer Mode (ATM) network diagram incorporating features of the present invention; 
       FIG. 2  is a flow diagram showing ATM header compression and decompression in accordance with features of the present invention shown in  FIG. 1 ; 
       FIG. 3  is a method flow chart of one embodiment of the compression features shown in  FIG. 2 ; 
       FIG. 4  is a method flow chart of one embodiment of the decompression features shown in  FIG. 2 ; 
       FIG. 5A  is a pictorial illustration of an ATM header shown in tabular byte form and compressed in accordance with features of the present invention; and 
       FIG. 5B  is a pictorial illustration of an ATM header shown in serial bit form and compressed in accordance with features of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Referring to  FIG. 1 , there is shown a network diagram of a network  16  having nodes  10 A,  10 B,  10 C, and  10 D; with an expanded view of ATM node  10 A that incorporates aspects of this invention. Although this invention will be described with reference to the embodiments shown in the drawings, it should be understood that this invention can be embodied in many alternate forms and embodiments. For example, while four ATM network nodes  10  are shown in  FIG. 1 , it will be appreciated that any suitable of nodes may be used. 
   Referring to  FIG. 1 , an ATM network node  10 A includes an ATM Cell Decompressor  11  that produces an ATM cell  12 , and an ATM Cell Compressor  15 . The input/output of ATM wireless network node  10 A can be provided to other ATM wireless network nodes either directly or indirectly, such as the ATM wireless network nodes  10 B,  10 C and  10 D. 
   Referring now to  FIGS. 2 and 3 , features of the ATM Cell Compressor  15  are described.  FIG. 2  shows a block diagram of the compression of either a user-network-interface (UNI) ATM cell  21  or a network-network-interface (NNI) ATM cell  22 . NNI and UNI ATM cells are well known and need not be discussed here. Referring as well to the logic flow diagram of  FIG. 3 , an Address Translation Unit (ATU)  23  receives, step  31 , the ATM cell  21  or  22 , reads the value in the VPI field  21 A,  22 A, and maps, step  32 , the value to a VPI Address-to-VPI Pointer in memory  24 . The ATU  23  also reads the value in the VCI field  21 B,  22 B and maps, step  33 , the value to a VCI Address-to-VCI Pointer stored in memory  25 . Steps  35  and  37  load the 4-bit VPI Pointer and the 8-bit VCI Pointer values into the ATM header  26 A. In alternate embodiments, the ATU  23  may zero the VPI and VCI fields of the ATM header  26 A, prior to loading the VPI and VCI pointers, steps  34  and  36 , respectively. A Data Link Framer  27  removes the eight leading bits from the VPI field if the cell is a NNI ATM cell, or removes four leading bits if the cell is an UNI ATM Cell, steps  301 , and  302 , respectively; leaving the 4-bit VPI Pointer in the remainder of the VPI field. In addition, the Data Link Framer  27  removes eight leading bits from the VCI field; leaving the 8-bit VCI pointer in the remainder of the VCI field. It will be appreciated that in this embodiment the number of possible VCI/VPI pointer combinations is 4096. In alternate embodiments a suitable number of VCI/VPI pointer combinations may be selected by changing the bit lengths of the VCI and VPI pointers. The Data Link Framer  27  also removes the HEC field  21 C,  22 C and, in a UNI ATM cell, the GFC field  21 D, thereby creating the compressed ATM cell  28  having, in this embodiment, a two byte (16-bit) compressed ATM cell header  28 A. The compressed ATM cell  28  is now in an advantageously smaller form, but with the same information payload (payload  1 - 48 ) for transmission, step  304 , over a wireless ATM network, such as shown in  FIG. 1 . 
   Referring to  FIGS. 5A and 5B  there is shown the compressed ATM Cell  28  in cell form (i.e. tabular byte form) or serial form  28 B, respectfully. It will be appreciated that in alternate embodiments the VPI and the VCI pointers  51  and  52 , respectively, may be any suitable bit length. 
   It will be appreciated that removal of the HEC  21 C,  22 C and the GFC  21 D is a feature of this invention. The HEC  21 C,  22 C may be removed since the higher layer ATM adaptation layers may be relied upon for error detection. For example, if a compressed ATM cell header  28 A has an incorrect bit in either the VPI or VCI pointers, an incorrect VPI and/or VCI address may be selected by the ATU  23 . An ATM switch, or node, ( FIG. 1 , item  10 A) would then direct the compressed header further into the network  16 , such as to node  10 B rather than, for example, to the intended node  10 C; or the ATM switch may forward the ATM packet directly to an end user segmentation and reassembly (SAR) device. However, in order for a misdirected cell to have appreciable negative effect on applications or network performance, the header value with errors would need to be decoded into another virtual circuit that is active within the network. To mitigate this effect certain restrictions may be placed upon the type of information flow across an interface (UNI or NNI). In a preferred embodiment the higher layer protocol is the ATM Adaptation Layer 5 (AAL-5) standard. Each AAL-5 Protocol Data Unit (PDU) (i.e., ATM packet) utilizes a 32-bit Cyclic Redundancy Check (CRC) to validate data integrity. Thus, the result of a misdirected cell on an AAL-5 PDU is a loss of CRC continuity. The receiving end station checks the CRC, and a CRC failure results in the packet being discarded. In alternate embodiments, there is a finite probability that a single cell AAL-PDU will be falsely decoded onto an active Virtual Channel (VC) connection, and delivered to an end station where the PDU passes the CRC. However, the probability of this occurring is low, and may be handled by local error handling routines. 
   In one embodiment, the information flowing across the AAL-5 interface includes primarily classical Internet Protocol (IP) over ATM AAL-5 packets; or in other words, a logical IP structure is mapped to the ATM network. In alternate embodiments, any suitable ATM protocol such as, for example, Interim Local Management Interface (ILMI) and UNI and NNI signaling, utilizing ATM AAL-5, may be used. 
   Referring now to  FIGS. 2 and 4 , features of the ATM Packet Decompressor  11  ( FIG. 1 ) are described. Step  41  receives the compressed ATM Cell  28  through the Data Link Framer  27 . The Data Link Framer  27  adds, or pads, eight bits to the VCI field, step  44 , and four bits to the VPI field for a UNI ATM cell, step  42 , or eight bits to the VPI field, step  43  for a NNI ATM cell. In an alternate embodiment the Data Link Framer  27  may also add a HEC field, step  49 , and/or a GFC field, step  401 , in a UNI ATM cell. The ATU  23  reads the VPI and VCI pointer values and retrieves the corresponding VPI and VCI values from the VCI Address-to-VCI Pointer database  25 , and the VPI Address-to-VPI Pointer database  24 , steps  402  and  45 , respectively. These values are then loaded, steps  46  and  47 , into the respective ATM header fields to reproduce the standard UNI or NNI ATM cell,  21  or  22 , respectively. The ATM Cell is then ready for normal ATM wire use, step  48 . 
   It will be appreciated that compression of the ATM header from five bytes to two bytes reduces ATM overhead from 10.42% to 4.17%. The resulting throughput increase equates to approximately 6.25%, which is a significant improvement for applications that operate over a bandwidth constrained link. 
   Another advantage of the invention is in retaining ATM Quality of Service (QoS) across a connection through use of a fixed length ATM cell structure. This combination of ATM QoS, with reduced overhead, can be used to provide real time services across bandwidth constrained wireless links. In addition, this invention may be used as an alternative to low-overhead transmission techniques such as Simple Data Link (SDL), which cannot provide QoS guarantees. 
   It should be understood that the foregoing description is only illustrative of the invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the invention. For example, the present invention advantageously reduces the size of the ATM header  28 A from 5 bytes to 2 bytes (16 bits). However, in alternate embodiments any suitable number of reduced bytes may be used. Accordingly, the present invention is intended to embrace all such alternatives, modifications and variances which fall within the scope of the appended claims.