Abstract:
A complex ternary correlator and method for adaptive gradient computation in an adaptive equalizer and including four ternary operation circuits, four ternary multiplier circuits for obtaining the cross products of the ternary operation outputs, a subtractor circuit for developing a signal commensurate with the difference between two of the ternary multiplier outputs, an adder circuit for developing a signal commensurate with the sum of the remaining two ternary multiplier outputs and two identical integrating circuits for obtaining the real and imaginary adaptive tap coefficient update increments in an adaptive equalizer.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to communications signal handling methods and apparatus and more particularly to a complex ternary correlator method and apparatus for use in developing the tap coefficient update increments in an adaptive equalizer. 
     2. Description of the Prior Art 
     A typical prior art communication system adaptive equalizer is illustrated generally at 10 in FIG. 1 and has as its functional objective the restoration of channel distorted data x(t) to a very close approximation y(t) of the originally transmitted data z(t) which is then input to a detector 16. FIG. 1 illustrates a decision feedback equalizer, but similar correlation and gradient computation is required for feedforward or hybrid feedforward/feedback equalizers. The feedback equalizer is comprised of three principal components: a transversal filter portion 14 which linearly processes prior detected symbols z(t); a gradient computation portion 18 which adjusts the tap coefficients 24 of the transversal filter; and a detector (or decision) portion 16 which identifies an input signal as one of a predetermined set of signals. An example of one such detector is the V.29 constellation detector disclosed in the copending application of Bruce M. Sifford, Ser. No. 960,851, filed Nov. 15, 1978. 
     Adaptive equalizers of the type illustrated at 10 in FIG. 1 of the drawing have their tap coefficients 24 adaptively adjusted on the basis of the pseudo-error signal e(t) which is generated by subtracting the equalized data y(t) from the complex data output z(t). Ideally, this error signal would be generated by comparing the equalizer output y(t) with the true data z(t). However, for practical communication systems this is impossible, and the pseudo-error signal e(t) is formed using the data detector output z(t) instead of z(t). Under normal circumstances this is acceptable since z(t) and z(t) almost always agree. 
     The decision feedback equalizer of a typical receiver system exploits the fact that at the output of the communication channel 12 there is residual intersymbol interference from previous symbols transmitted. Assuming that correct decisions have already been made on these past symbols, the late-arriving contributions can then be subtracted from the current-received signal x(t). The mechanism for accomplishing this is to excite a complex tapped-delay-line filter with the complex decision signals that have been made and then subtract the weighted filter tap outputs from the incoming complex signal. The taps are continuously adjusted to minimize the average error signal e(t) produced at the receiver output. 
     The tap coefficients may be updated at each sampling instant, and each new tap coefficient is the old value plus a new increment (which might be 0); that is, 
     
         a.sub.i (t+1)=a.sub.i (t)+Δa.sub.i (t+1)             (1) 
    
     for i=1 to n where n is the number of taps. 
     The increment is calculated on the basis of the adaptive gradient algorithm 
     
         a(t+1)=a(t)+k·e(t)·z*(t-1)               (2) 
    
     where 
     a(t), e(t) and z(t) are complex-valued functions, 
     e(t) is the complex pseudo-error signal, 
     z(t) is the complex detector output, 
     k is a scaling factor, and 
     the * denotes complex conjugate. 
     It may thus be shown that the gradient is proportional to the cross correlation between the pseudo-error and the detector output data, i.e., e(t)z(t-i), where the superbar denotes an averaging process that is performed by the above equation (1). The new increment, Δa i , is then based directly on this cross correlation. This approach is generally referred to as an analog correlator method even though in this disclosure it is implemented in an integer, fixed-word-length realization. 
     The disadvantage of this &#34;analog&#34; correlator method is that it requires one p-bit (typically p=8) multiplier for each of the n taps of the transversal filter. Since n is frequently greater than 16, and may be as high as 64, this is a very costly requirement. The purpose of this invention is to substantially reduce the complexity of these correlators. 
     SUMMARY OF THE INVENTION 
     It is therefore a principal object of the present invention to provide a relatively simple signal correlation method and apparatus for computing adjustments to be made to the taps of an adaptive feedback equalizer. 
     Another object of the present invention is to provide a correlation means as described above which does not require expensive multiple-bit digital multiplication components. 
     Still another object of the present invention is to provide a correlation means of the type described which is substantially faster in operation than prior art correlation devices and therefore decreases the computational load. 
     Briefly, a preferred embodiment of the present invention in which it is assumed that the complex equalizer inputs z and e are represented by p-bit real and imaginary components includes four ternary operation circuits, four ternary multiplier circuits for obtaining the cross products of the ternary operation outputs, a subtractor circuit for developing a signal commensurate with the difference between two of the ternary multiplier outputs, an adder circuit for developing a signal commensurate with the sum of the remaining two ternary multiplier outputs and two identical integrating circuits for obtaining the real and imaginary adaptive tap coefficients. 
     An important advantage of the present invention is that it enables equalizer update increments to be obtained much faster and at substantially less cost than was the case using prior art techniques. 
     These and other objects and advantages of the present invention will no doubt become apparent to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the several figures of the drawing. 
    
    
     IN THE DRAWING 
     FIG. 1 is a diagram schematically illustrating an adaptive equalizer system including complex ternary correlator circuits in accordance with the present invention; 
     FIG. 2 is a block diagram illustrating the principal operative components of a ternary correlator in accordance with the present invention; and 
     FIG. 3 is a diagram schematically illustrating the ternary operators and ternary multipliers shown in FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now again to FIG. 1 of the drawing, it will be noted that in order to perform in accordance with the decision feedback algorithm of equation (2) above, the gradient computation portion 18 must have conjugating and delay circuits 20 for developing the appropriate conjugates of z(t), and correlator circuits 22 for correlating e(t) with the conjugates to develop the complex update increments Δa i  (t) for adjusting respective tap values 24 of the delay line 26. In the typical case, e(t) and z(t) are 8-bit digital words where one of the bits is a sign bit. 
     The present invention provides a novel ternary correlator method and circuitry which substantially decreases the computational load as compared to prior art methods and apparatus. The ternary correlator method may be best understood as an extension of the binary or polarity correlator method. 
     The polarity correlator concept is that a real 8-bit-by-8-bit multiplication of R and S is replaced by a simple exclusive OR operation on the sign of R and the sign of S. In effect, the 8-bit multiplication is replaced by a 1-bit multiplication which is much simpler. 
     These statements are true, assuming that R and S are available in analog form such that the probability of obtaining a value of zero for either of these functions is zero. However, for the present application, R and S are digitized, and the probability of obtaining a zero value is reasonably high. Consequently, it is necessary to modify the polarity correlator to include the zero value. This modification results in what we call the ternary correlator. 
     As noted above, the R and S functions used in the correlation process can assume a zero value. Rather than assigning zero value a polarity, which would tend to create a bias, the signum operation is replaced with the &#34;tern&#34; (for ternary) operation. The tern operative (i.e., tern(R)) is equal to the sign of R unless R=0, in which case the tern (R)=0. The truth table for the ternary multiplication tern(R).tern(S) is as follows: 
     
                       TABLE 1______________________________________   S &gt; 0     S = 0       S &lt; 0______________________________________R &gt; 0     +1          0           -1R = 0      0          0            0R &lt; 0     -1          0           30 1______________________________________ 
    
     The above of course assumes that the variables are real valued. However, for most applications, they are complex valued, and it is necessary to be concerned with what is meant by the sign, or rather the tern, of the complex number. The complex tern operation can be defined as 
     
         tern{W}=tern{W.sub.r +jW.sub.j }=tern{W.sub.r }+jtern{W.sub.j }(3) 
    
     for any complex number W. Thus, by defining e(t) and z(t-i) in Equation 2 as 
     
         e(t)=a+jb                                                  (4) 
    
     and 
     
         z(t-i)=c+jd                                                (5) 
    
     and if the results of the ternary correlation multiplication operation is designated ΔΨ(t), then 
     
         ______________________________________ΔΨ(t)    =     tern [a + jb] . tern [c + jd]                                  (6)    =     [terna . ternc - ternb . ternd]          +j[ternb . ternc + terna . ternd].______________________________________ 
    
     Thus, ΔΨ(t) is a five-level complex number; that is, both the real and imaginary parts can take on values of ±1, ±2, or 0. Furthermore, note that ΔΨ(t) differs from the ternary operation on the direct product; that is, 
     
         tern[e·z]=tern[ac-bd]+jtern[bc+ad]. 
    
     This latter operation comes closer to providing the true gradient. However, it requires far more computation. On the average, the two approaches should give approximately the same result, but the approach of Equation (6) has been chosen because of its computational simplicity. 
     The ternary correlator output ΔΨ(t) is used to generate the tap coefficient update increment Δa i  (t). For steady-state operation, Δa i  (t) affects only the least significant bit of a i  (t), thereby improving noise performance further. However, during acquisition, which can be sensed by the higher mean square error, a larger step size can be used to reduce the acquisition time. 
     Turning now to FIG. 2 of the drawing, a block diagram of a ternary correlator in accordance with the present invention is shown. The correlator includes four ternary operating circuits 44-50, four ternary multiplying circuits 52-58, a subtraction circuit 60, and an adder circuit 62. In addition, two accumulator circuits 64 and 66 are also shown for accomplishing the updating operation. Each of these accumulators is preceded by an operational amplifier of gain k representing the scaling factor of Equation (2). It will be noted that the circuit as illustrated is a direct implementation of equation (6) above. In this implementation, it is assumed that the input e(t) is available as real and imaginary components e r  (t) and e j  (t). The tern operator circuit 44 operates on e r  (t) to develop the factor above-identified as terna, while the operator 46 operates on e j  (t) to develop the above factor ternb. 
     Simultaneously, the tern operator 48 develops ternc from the real part of z(t-i) and the tern operator 50 develops ternd from the negative of the imaginary part of z(t-i). The ternary outputs a through d are then input to the multipliers 52-58 to develop on line 70 the product terna·ternc; to develop on line 72 the product ternb·ternd; to develop on line 74 the product terna·ternd; and to develop on line 76 the product ternb·ternc. 
     The signal developed on line 72 is then subtracted from that on line 70 by the subtraction circuit 60, and the signals developed on line 74 and 76 are added together by the adder circuit 62. The signal developed on lines 57 and 59 may either be used to directly generate the tap coefficient update increments or it may be compared to certain threshold levels to improve noise performance. But in either case the resulting signal developed on lines 57 and 59 are fed into the accumulators 64 and 66 to develop the real and imaginary tap coefficients a ri  (t) and a ji  (t). 
     In FIG. 3 the internal components of the tern operators and ternary multipliers are schematically illustrated for the case where the real and imaginary inputs are 8-bit binary words. More specifically, the tern operator 44 may be embodied to include an 8-bit shift register 90 for receiving seven data bits and one sign bit. From register 90 the seven data bits are input to a NAND gate 92, the output of which is normally low but goes high if all 7 magnitude bits representing zero values are shifted into register 90. The sign bit is input to a switch 93 which in response thereto selects either a +1 voltage level or a -1 voltage level for output on line 96. A switch 94 normally couples the sign bit input on line 96 to its output 98, but in the event that the output of NAND gate 92 goes high, as would be the case where each of the 7 bits in register 90 were zeros, the switch contact 95 will be moved to terminal 100 to couple a zero-voltage level to the output terminal 98. Accordingly, the output of tern operator 44 will either be a +1, a -1 or a 0. 
     The ternary multiplier 52 includes a pair of comparators 102 and 104, an OR gate 106, an exclusive OR gate 108, and a switch 110. It will be appreciated from the drawing that with the switch 110 normally in the position indicated, the output of gate 108 will be either a +1 or a -1, depending upon the nature of the inputs applied to terminals 98 and 112. 
     However, in the event that either of the comparators 102 or 104 detects a zero level appearing on either the line 98 or 112, an output will be developed for passage through OR gate 106 which will cause contactor 109 of switch 110 to contact the terminal 114 and output a zero level at terminal 70. Accordingly, the output developed at terminal 70 will be either a +1, a -1 or a 0. 
     Although only one ternary operator/ternary multiplier pair is illustrated in FIG. 3, it will be appreciated that the other like units are similar and function in a similar fashion. 
     Returning now to FIG. 2, it will be appreciated that by subtracting the output developed on line 72 from that developed on line 70, an output will be developed on line 57 which is either +2, +1, 0, -1 or -2. And by the same reasoning, the addition of the signals developed on lines 74 and 76 will also develop a similar one-out-of-five level signal on line 54. 
     As indicated above, the real and imaginary increments Δa ri  (t) and Δa ji  (t) are then fed into the accumulators 64 and 66 which form the complex tap coefficient a i  (t). 
     Although the present invention has been described above in terms of a schematic diagram intended to be representative of a digital embodiment of the invention, it will be appreciated that analog or microprocessor embodiments and other forms of implementation may likewise be chosen. It is therefore intended that the following claims be interpreted as covering all such alternative embodiments and implementations as fall within the true spirit and scope of the invention.