Abstract:
A circuit for use in comparing input voltages includes switching elements initially configured in a reset mode to minimize charge or current conduction before entering a comparison mode. A strobe signal reconfigures the switching elements to transition from the reset mode to the comparison mode. Finally, a determination is made as to which of the input voltages is larger or smaller.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims benefit of the priority of U.S. Provisional Application Ser. No. 60/080,497, filed Apr. 2, 1998 and entitled “Strobed CMOS Comparator”. 
    
    
     BACKGROUND 
     This specification generally relates to voltage comparators. More specifically, the present specification describes method and apparatus for comparing input voltages having a small voltage difference. 
     Voltage comparators determine which of the two input voltages are larger or smaller. Since a voltage comparator often senses small differences between the input voltages and generates a digital output, a large amplification may be needed. The large amplification necessary for sensing small differences is constructed using a differential amplifier operating in a non-linear region. The differential amplifier has two transistors connected as a source-coupled pair with one of the transistors turned-off and the other transistor turned-on. Therefore, the amplifier has one transistor turned-on and drawing current even under static condition when the transistors are in a stable non-switching state. 
     As amplification circuits, comparators are susceptible to influence of noise on the input voltages. The noise on the input voltages causes erratic switching and false triggering of the comparator output. Thus, positive feedback can be applied to reduce the influence of noise on the comparison and to increase the flexibility of the differential threshold of switching. The flexibility of the threshold is increased by making the threshold less sensitive to the difference in input voltages and more sensitive to the previous levels of the input voltages. However, the feedback also tends to slow the response of the comparator and limits the lowest differential voltage which can be sensed. 
     The voltage comparators are used in various different applications such as in analog-to-digital converters (ADCs), signal generators, and image arrays and ADCs of complementary metal-oxide semiconductor (CMOS) active pixel sensors (APSs). 
     The voltage comparators used in the CMOS APSs are sensitive to a high fixed-pattern noise. The fixed-pattern noise is an unvarying display pattern resulting from the difficulty in exactly matching transistor thresholds on CMOS circuits for photocurrent amplification and transfer circuitry. 
     SUMMARY 
     The inventor noticed that by placing switches across the source-drain terminals of the cross-coupled load transistors and closing the switches during the reset mode, the load transistors are disabled. This prevents any charge or current conduction through the load transistors during the reset mode and effectively reduces the adverse effect of the load transistor threshold mismatch during the comparison mode. 
     In addition, this technique produces much smaller input-referred offset with a desired effect of much less erroneous comparison. 
     In one aspect, the present disclosure compares input voltages that are relatively close to each other. Initially, switching elements are configured in a reset mode to prevent any charge or current conduction. A strobe signal reconfigures the switching elements to transition from the reset mode to the comparison mode. Finally, a determination is made as to which of the input voltages is larger or smaller. 
     In some embodiments, an output result of the comparison is a positive number if a first input voltage is larger than a second input voltage, and a negative number if the second input voltage is larger than the first input voltage. In further embodiments, the output result is correctly determined with magnitude of an input voltage difference as small as 1.5 mV. 
     In other embodiments, the input voltages are sampled for comparison to prevent input voltages from changing for the duration of the comparison. In further embodiments, the output result of the comparison is buffered. 
     In another aspect, the disclosure features a CMOS active pixel image sensor system for use in detecting images through photocurrent picked up by an image pixel array. The system also includes an analog-to-digital converter which includes the improved voltage comparators. 
     In yet another aspect, the disclosure features a CMOS APS camera system for use in detecting and displaying images. This system also includes the improved voltage comparators. 
     Among the advantages of the present disclosure is the small input-referred offset. As a result, input voltages of small difference can be compared accurately. 
     The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a schematic diagram of a CMOS voltage comparator. 
     FIG. 1B is charge-surface potential diagrams of an input-load transistor pair at the initial stage of the comparison. 
     FIG. 2A is a schematic diagram of the improved CMOS voltage comparator. 
     FIG. 2B is charge-surface potential diagrams of an input-load transistor pair of the improved CMOS voltage comparator at the initial stage of the comparison. 
     FIG. 3 is a detailed schematic diagram of one implementation of the present invention. 
     FIG. 4 is one implementation of the conventional voltage comparator. 
     FIG. 5A illustrates an insertion of a 10% mismatch in the thresholds of the load transistors. 
     FIG. 5B is an input-referred offset, ΔV, for the improved comparator resulting from the 10% mismatch. 
     FIG. 5C is the input-referred offset for the conventional comparator resulting from the 10% mismatch. 
     FIG. 6A is a block diagram of a CMOS image sensor system. 
     FIG. 6B is a block diagram of a CMOS image sensor camera system. 
     Like reference numbers and designations in the various drawings indicate like elements. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1A shows a schematic diagram of a voltage comparator. Since input voltages  108 ,  110  can change rapidly and at different rates, comparator outputs  114 ,  116  are disabled until some predetermined time after the input voltages are stabilized. Switches S 1  through S 3  are used to disable the output and to turn-off load transistors  104 ,  106 . The switches are controlled by a strobe signal. 
     In a reset mode, i.e. before comparison, the switch S 1  is open and the switches S 2  and S 3  are closed. This prevents the current from flowing through p-channel metal-oxide semiconductor (PMOS) load transistors  104 ,  106 . However, the PMOS transistors  104 ,  106  are on and conducting because the gate terminals of the PMOS transistors are tied to a ground voltage by the switches S 2  and S 3 . 
     In a comparison mode, the strobe signal turns the switch S 1  closed and the switches S 2  and S 3  open. This configuration starts the comparison of the two input voltages  108 ,  110 . If the input voltage at input node  108  is higher than the input voltage at input node  110 , an n-channel metal-oxide semiconductor (NMOS) input transistor  100  turns on more than the other NMOS input transistor  102 . This pulls the node  114  to a lower voltage than the voltage at the node  116 . The lower voltage on the node  114  turns PMOS transistor  106  on and brings the node  116  higher up toward Vdd. Thus, the comparator output at node  116  indicates that the voltage difference is positive. 
     However, when the input voltage difference is small, the voltage at the comparator output can depend on which load transistor reacts faster and conducts more efficiently rather than on the value of the voltage difference. The output of the comparator becomes particularly sensitive to the load mismatching in the load transistors because the positive feedback of the cross-coupled pair  104 ,  106  multiplies the mismatch and destabilizes the comparison. 
     FIG. 1B illustrates the above mentioned issue when the input voltage difference is small. The figure shows charge-surface potential diagrams at the initial stage of the comparison for one of the input-load transistor pair. Charges  122  build up on the input transistor because the transistors were conducting prior to the comparison. Once the comparison starts, the charges keep the input transistor in a linear region and prevent the input transistor from having a strong dependence on the input gate voltage. This allows the current through the load transistor to quickly charge up  124  the common-drain terminal  126 . This reset configuration allows a load transistor with higher conductivity to take control of the common-drain terminal  124  by charge injection when the input voltage difference is small. Therefore, even a slight mismatch in the thresholds of the load transistors results in a large input-referred offset (i.e. the smallest input voltage difference necessary to achieve a correct comparator output) or an erroneous comparator output. 
     The present disclosure describes a strobed CMOS voltage comparator capable of operating with a small input voltage difference. This circuit operates by completely disabling the load transistors prior to the voltage comparison. During a reset mode, the load transistors are prevented from any charge conduction to reduce the effect of threshold mismatch in the load transistors on the comparator output during a comparison mode. 
     FIG. 2A show a schematic diagram of the improved CMOS voltage comparator with above described advantages. Switches for the strobe signal are connected to minimize the effects from the characteristics of the individual components. This makes the comparison between the input voltages much more fair than the conventional comparator (i.e. based more on the input voltages). 
     In the reset mode, the switch S 1  is open and the switches S 2  and S 3  are closed. Both the source and the drain terminals of the load transistors  204 ,  206  are tied to a supply voltage Vdd, when the strobe signal closes the switches S 2  and S 3 . This prevents any charge or current from conducting through the PMOS transistors  204 ,  206 . 
     The strobe signal sends a pulse to close the switch S 1  and open the switches S 2  and S 3  to enter the comparison mode. This configuration allows the voltage at the gate terminal of the input transistor to control the amount of current filling up the wells in the load transistors. Even a slightly higher input voltage at the gate terminal of one of the input transistors pulls a common drain node  208  or  210  lower toward a ground voltage. The load transistor that fills up its well first brings the common-drain node  208  or  210  higher up toward the supply voltage, Vdd, and prevents the other load transistor from further current conduction. 
     The output current has a strong dependence on the input voltages at the gate terminals of the NMOS transistors  200 ,  202 . The output of the comparator is less sensitive to the threshold mismatch of the load transistors. The multiplication of the mismatch for the improved comparator is significantly reduced in the feedback of the cross-coupled pair  204 ,  206  than for the conventional comparator. Therefore, the voltage comparison is more stable and fair. 
     FIG. 2B shows the charge-surface potential diagrams at the initial stage of the comparison for one of the two input-load transistor pairs of the improved comparator. The input transistor is initially in a sub-threshold state characterized by high sensitivity to the input voltage at the gate terminal. Unlike the conventional comparator, there is no built-up charge on the input transistor due to charge conduction. 
     When the strobe signal indicates the start of the comparison mode, an input transistor with a lower barrier (i.e. higher input voltage at the gate terminal) sinks more current through the load and fills its drain-well before the other input transistor. The charge-surface potential of the load transistor stays static until the internal potential exceeds the PMOS threshold voltage. Therefore, any threshold mismatch between the load transistors has significantly less effect on the output of the comparator than it would in the conventional comparator. 
     FIG. 3 shows an implementation of the improved voltage comparator shown in FIG.  2 A. The switch S 1  is implemented with an NMOS transistor  314 . The switches S 2  and S 3  are implemented with PMOS transistors  310 ,  312 . 
     In the reset mode, the strobe signal  370  is disabled and applies a low voltage at the gate terminals of the PMOS transistors  310 ,  312  and the NMOS transistor  314 . The low voltage at the gate terminals of the PMOS transistors  310 ,  312  turns on those transistors. The low voltage at the gate terminal of the NMOS transistor  314  turns off that transistor because the source terminal node  350  is biased at a higher voltage than the low voltage at the gate terminal. The node  350  is biased to some voltage above the ground voltage by an NMOS transistor  316  which is always turned on by a bias voltage at the gate terminal. In this configuration, there is no current or charge flowing through load transistors  304 ,  306  into input transistors  300 ,  302 . 
     The strobe signal  370  is enabled by a pulse of some predetermined time duration. The input voltages, V in + and V in −, are compared during this time duration. The strobe pulse  370  turns off transistors  310 ,  312  and turn on transistor  314  to allow current to flow through the load transistors  304 ,  306  into the input transistors  300 ,  302 . The strobe pulse  370  also cuts off PMOS pass-through transistors  340 ,  342  to prevent the input voltages from changing during the time duration of the comparison. 
     The input voltages, V+ and V−, sampled by capacitors  360 ,  362 , respectively, drive the NMOS input transistors  300 ,  302  during the comparison mode. If the voltage at the V+ input is higher, the channel of the input transistor  300  is opened wider and the node  354  is driven lower than the node  352 . This immediately turns on the PMOS load transistor  306  and drives node  352  to a logic high, which turns off the PMOS load transistor  304 . Therefore, the node  352  enters a stable logic high state indicating a positive input voltage difference. 
     A transistor pair  330 ,  332  operates as an inverter. A logic high at the node  352  turns off PMOS transistor  330  and turns on NMOS transistor  332 . This pulls down the node  356  to a logic low. A transistor pair  334 ,  336  is another inverter. A logic low at the node  356  turns on PMOS transistor  334  and turns off NMOS transistor  336 . This pulls the output node, OUT, to a logic high and the output node follows the node  352 . Therefore, the transistors  330  through  336  act as a buffer. The transistors  320  through  326  act as a buffer for the other output node, {overscore (OUT)}. 
     FIG. 4 shows one implementation of the conventional voltage comparator shown in FIG.  1 A. Transistors  414 ,  410 ,  412  implement switches S 1 , S 2 , and S 3 , respectively. NMOS transistors  400 ,  402  are input transistors operating to compare input voltages at V+ and V− nodes. PMOS transistors  404 ,  406  are cross-coupled load transistors. Transistors  430  through  436  and  420  through  426  are buffers for output nodes, OUT and {overscore (OUT)}, respectively. 
     FIGS. 5A through 5C illustrate the advantages of the improved CMOS voltage comparator shown in FIG. 3 over the conventional CMOS voltage comparator shown in FIG.  4 . 
     FIG. 5A shows a deliberate insertion of a slight mismatch in the load transistors. The mismatch is inserted by varying the channel width by 10% in only one of the two load transistors. This results in the channel width of the load transistor  304  or  404  to be 2.4 μm and the other load transistor  306  or  406  to be 2.6 μm. 
     FIG. 5B shows an input-referred offset, ΔV, for the improved comparator. The input-referred offset is a smallest input voltage difference necessary to achieve a correct comparator output. FIG. 5C shows the input-referred offset for the conventional comparator. The V− input voltage is held constant at 4.0 volts for both cases. 
     The improved comparator output breaks down at V+ input voltage of 4.0015 volts while the conventional comparator output breaks down at V+ input voltage of 4.0680 volts. Therefore, the improved comparator shows the significantly advantageous lower input-referred offset of 1.5 mV, versus 68.0 mV for the conventional comparator. 
     FIGS. 6A and 6B show block diagrams of a CMOS image sensor system and a CMOS image sensor camera system. The sensor system and the camera system are two examples among the systems that may include the improved voltage comparator described above. 
     A number of embodiments of the present invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, the switch may be implemented in various ways, such as with one or more transistors, a digital logic array, or a programmed microprocessor. Accordingly, other embodiments are within the scope of the following claims.