Abstract:
The rectifier circuit includes: three terminals A, K, VR; voltage comparator including a positive input terminal, a negative input terminal, and a comparative output terminal; current switching unit including source terminal, drain terminal, and control terminal; first switching unit that conducts or cuts off between source terminal and control terminal of the current switching unit; second switching unit that conducts or cuts off between control terminal of the current switching unit and terminal VR; and reference voltage generator that uses terminal A and terminal VR as input terminals, and includes a voltage output terminal. The voltage output terminal of reference voltage generator is connected to the negative input terminal of the voltage comparator, terminal K is connected to the positive input terminal of voltage comparator, and current flow between first switching unit and second switching unit is exclusively allowed or interrupted by a signal output from the comparative output terminal of voltage comparator).

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a rectifier circuit, in particular, to a rectifier circuit including a current switching unit that allows a current to flow in one direction in response to an output signal from a voltage comparator and interrupts a reverse current, and to a contactless power supply device that includes a power supply part having the rectifier circuit. 
         [0003]    2. Description of the Related Art 
         [0004]    Smart cards and RFID (Radio Frequency Identifier) tags which have no battery as a power source communicate by drawing, via an antenna, power from an electromagnetic field produced by a communication device. 
         [0005]    In recent years, there is a trend that smart cards store more biological information than ever on a non-volatile memory to provide secure authentication. To enable such smart cards to process more data in a short time, a faster internal CPU (Central Processing Unit) and faster access to a memory have been demanded. Generally, increases in a speed of a CPU and in a speed of access to a memory are accompanied by an increase in power consumption, which requires such smart cards to draw power from an electromagnetic field more efficiently. 
         [0006]    With the spread of NFC (Near Field Communication)-enabled mobile devices, RFID tags are now in widespread use. For example, RFID tags are used in authentication between devices. A mobile device, which is required to operate for many hours, needs to produce a smaller electromagnetic field that enables communication between an RFID tag and the mobile device, so as to suppress an amount of power consumed by a built-in battery. Because a margin of positional discrepancy and a margin of distance between devices in communication are necessary, an RFID tag is required to efficiently draw power from a small electromagnetic field and to operate at low power. 
         [0007]    Drawing power from an electromagnetic field requires generating a DC power source from an AC voltage generated across a terminal of an antenna. To enable this function, a rectifier circuit is used. Generally, an IC (Integrated Circuit) chip for a smart card and for a RFID tag is produced using a CMOS (Complementary Metal-Oxide Semiconductor) process, and thus a rectifier circuit in such an IC chip is formed of MOS transistors. A circuit illustrated in  FIG. 12  described in PTL 1 has been conventionally used. 
         [0008]    In the rectifier circuit illustrated in  FIG. 12 , terminal A is connected to a source of P-channel MOS transistor Tr 1 , and terminal K is connected to a gate to which a drain is commonly connected. Terminal A is connected to a source of P-channel MOS transistor Tr 2  for selecting a connection destination of a back gate of P-channel MOS transistor Tr 1 , and terminal K is connected to a gate of P-channel MOS transistor Tr 2 . Terminal K is connected to a source of P-channel MOS transistor Tr 3  for selecting a connection destination of the back gate of P-channel MOS transistor Tr 1 , and terminal A is connected to a gate of P-channel MOS transistor Tr 3 . A drain of P-channel MOS transistor Tr 2  and a drain of P-channel MOS transistor Tr 3  are commonly connected to the back gate of P-channel MOS transistor Tr 1 . 
         [0009]    In the circuit of  FIG. 12 , when a voltage across terminal A is greater than a voltage across terminal K by at least threshold voltage Vtp of P-channel MOS transistor Tr 1 , P-channel MOS transistor Tr 1  is brought into a conductive state, allowing a current to flow from terminal A to terminal K. At this time, P-channel MOS transistor Tr 2  is also brought into a conductive state. This causes the back gate and the source of P-channel MOS transistor Tr 1  to have an identical voltage, preventing a leak voltage caused by parasitic diode D 1  and thus preventing power losses. When a voltage across terminal A is less than a voltage across terminal K, P-channel MOS transistor Tr 1  is cut off, interrupting a current flowing from terminal K to terminal A. At this time, if a voltage across terminal A drops by greater than threshold voltage Vtp relative to a voltage across terminal K, P-channel MOS transistor Tr 3  is brought into a conductive state. This causes the back gate and the drain of P-channel MOS transistor Tr 1  to have an identical voltage, preventing a leak voltage caused by parasitic diode D 2  and thus preventing power losses. Because circuits are each formed of a MOS transistor, a decrease in speed due to a reverse recovery time of a PN junction diode does not occur during current switching, enabling a high-speed switching. 
         [0010]    In the circuit of  FIG. 12 , however, for current Id to flow from terminal A to terminal K, a voltage across terminal A is required to be increased by threshold voltage Vtp of the MOS transistor relative to a voltage across terminal K, resulting in a power loss of Vtp×Id. 
         [0011]    As a unit that reduces power losses due to the threshold voltage, a rectifier circuit is described in PTL 2 in which a MOS switch is used in place of a diode constituted by a MOS transistor.  FIG. 13  illustrates the rectifier circuit described in PTL 2. 
         [0012]    In the rectifier circuit illustrated in  FIG. 13 , terminal A, terminal K, and output node  65  of voltage comparator  62  are respectively connected to a source, a drain, and a gate of N-channel MOS transistor  61 . Voltage comparator  62  has two bipolar transistors  68 ,  69  each having an emitter, a collector, and a base, and two resistors  66 ,  67 . The emitter of bipolar transistor  68  is a positive input of voltage comparator  62 , while the emitter of bipolar transistor  69  is a negative input of voltage comparator  62 . Two resistors  66  and  67  are connected in series between the collectors of bipolar transistors  68  and  69 . The collector of bipolar transistor  68  is output node  65  of voltage comparator  62 , and the bases of two bipolar transistors  68  and  69  are connected to the collector of bipolar transistor  69 . 
         [0013]    In the circuit illustrated in  FIG. 13 , when a voltage across terminal A is greater than a voltage across terminal K, bipolar transistor  68  is cut off, and output node  65  of voltage comparator  62  is pulled up by resistor  66 . Consequently, MOS transistor  61  is brought into a conductive state, allowing a current to flow from terminal A to terminal K. When a voltage across terminal A is less than a voltage across terminal K, bipolar transistor  68  is brought into a conductive state, allowing a current to flow through resistor  66 , resulting in reduced voltage at output node  65  of voltage comparator  62 . Consequently, MOS transistor  61  is cut off, interrupting a current flowing from terminal K to terminal A. If bipolar transistors  68  and  69  have shapes identical to each other, and resistors  66  and  67  are of identical resistance, when terminal A has a voltage that allows a current to flow from terminal A to terminal K and that interrupt a current flowing in a reverse direction, the voltage of terminal A is substantially identical to a voltage across terminal K. Thus, power losses due to a threshold voltage of a MOS transistor, which is the disadvantage of the circuit of  FIG. 12 , are reduced. 
         [0014]    Other than PTL 2, NPL 1 and NPL 2 also describe a method for implementing a rectifier circuit that uses a MOS switch. 
       CITATION LIST 
     Patent Literatures 
       [0000]    
       
         PTL 1: Unexamined Japanese Patent Publication No. 11-233730 
         PTL 2: Japanese Translation of PCT Publication No. 2002-511692 Non-Patent Literatures 
         NPL 1: C.-S. A. Gong, et al., “Efficient CMOS Rectifier for Inductively Power-Harvested Implants”, Electron Devices and Solid-State Circuits, IEEE International Conference 2008. 
         NPL 2: S. Guo, et al., “An Efficiency-Enhanced CMOS Rectifier With Unbalanced-Biased Comparators for Transcutaneous-Powered High-Current Implants”, IEEE J. Solid-State Circuits, Vol. 44, No. 6, pp. 1796-1804, June 2009. 
       
     
       SUMMARY 
       [0019]    To mount the circuit illustrated in  FIG. 13  on an IC chip for a smart card and for an RFID tag, the IC chip needs to be produced through the CMOS process so that the IC chip is produced at low cost. Accordingly, bipolar transistors  68  and  69  need to be replaced with N-channel MOS transistors.  FIG. 14  illustrates a circuit configured by replacing bipolar transistors  68  and  69  of the circuit illustrated in  FIG. 13  with N-channel MOS transistors. Generally, a relative variation in threshold voltages of two MOS transistors is greater than a relative variation in threshold voltages of two bipolar transistors. Therefore, with bipolar transistors replaced with MOS transistors, an input-offset voltage of voltage comparator  62  increases, and when a voltage across terminal A is less than a voltage across terminal K, a reverse current flowing from terminal K to terminal A is not interrupted, producing power losses. Reducing a variation in threshold voltages of the MOS transistors, which variation causes the power losses, requires gate areas of the MOS transistors to be increased. Consequently, gate capacitances of N-channel MOS transistors  70  and  71  increase, and when an AC voltage is applied to terminal K, a delay in a response of voltage comparator  62  increases. The delay in the response of voltage comparator  62  generates a reverse current, leading to power losses. 
         [0020]    NPL 1 and NPL 2 each describe a different method for implementing a rectifier circuit. However, the rectifier circuits in NPL 1 and NPL 2 operate at frequencies ranging from about 1.5 MHz to about 2 MHz, and thus do not operate at frequencies greater than 13.56 MHz or more necessary to allow the rectifier circuits to be applied to a smart card and an RFID tag. 
         [0021]    The present disclosure provides a rectifier circuit that has low power losses and that operates at high frequencies, and a contactless power supply device, typified by a smart card and an RFID tag, which has an improved power supply capability achieved by mounting the rectifier circuit to a power supply circuit. 
         [0022]    A first rectifier circuit that overcomes the above disadvantage includes first terminal (A), second terminal (K), and third terminal (VR). The first rectifier circuit allows a current to flow in a direction from first terminal (A) to second terminal (K), and interrupts a reverse current flowing from second terminal (K) to first terminal (A). A voltage across third terminal (VR) is set to be greater than a voltage across first terminal (A). The first rectifier circuit includes: voltage comparator (B 1 ) including a positive input terminal, a negative input terminal, and a comparative output terminal; current switching unit (SW 0 ) including source terminal (S), drain terminal (D), and control terminal (G); first switching unit (SW 1 ) that conducts or cuts off between source terminal (S) and control terminal (G) of the current switching unit; second switching unit (SW 2 ) that conducts or cuts off between control terminal (G) of the current switching unit and third terminal (VR); and reference voltage generator (B 2 ) that uses first terminal (A) and third terminal (VR) as input terminals, and includes a voltage output terminal. The voltage output terminal of reference voltage generator (B 2 ) is connected to the negative input terminal of voltage comparator (B 1 ). Second terminal (K) is connected to the positive input terminal of voltage comparator (B 1 ). The comparative output terminal of voltage comparator (B 1 ) is connected to first switching unit (SW 1 ) and second switching unit (SW 2 ). When a difference in voltage between the positive input terminal and the negative input terminal of voltage comparator (B 1 ) is greater than a threshold, the first rectifier circuit causes first switching unit (SW 1 ) to be in a conductive state, and causes second switching unit (SW 2 ) to be cut off, so that current switching unit (SW 0 ) is cut off. When a difference in voltage between the positive input terminal and the negative input terminal of voltage comparator (B 1 ) is less than the threshold, the first rectifier circuit causes first switching unit (SW 1 ) to be cut off, and causes second switching unit (SW 2 ) to be in a conductive state, so that current switching unit (SW 0 ) is brought into a conductive state. 
         [0023]    A second rectifier circuit, which is another unit that overcomes the disadvantage, includes first terminal (A), second terminal (K), and third terminal (VR). The second rectifier circuit allows a current to flow in a direction from first terminal (A) to second terminal (K) and interrupts a reverse current flowing from second terminal (K) to first terminal (A). A voltage across third terminal (VR) is set to be less than a voltage across second terminal (K). The second rectifier circuit includes: voltage comparator (B 1 ) including a positive input terminal, a negative input terminal, and a comparative output terminal; current switching unit (SW 0 ) including source terminal (S), drain terminal (D), and control terminal (G); first switching unit (SW 1 ) that conducts or cuts off between source terminal (S) and control terminal (G) of the current switching unit; second switching unit (SW 2 ) that conducts or cuts off between control terminal (G) of the current switching unit and third terminal (VR); and reference voltage generator (B 2 ) that uses second terminal (K) and third terminal (VR) as input terminals, and includes a voltage output terminal. The voltage output terminal of reference voltage generator (B 2 ) is connected to the negative input terminal of voltage comparator (B 1 ). First terminal (A) is connected to the positive input terminal of voltage comparator (B 1 ). The comparative output terminal of voltage comparator (B 1 ) is connected to first switching unit (SW 1 ) and second switching unit (SW 2 ). When a difference in voltage between the positive input terminal and the negative input terminal of voltage comparator (B 1 ) is greater than a threshold, the second rectifier circuit causes first switching unit (SW 1 ) to be cut off, and causes second switching unit (SW 2 ) to be in a conductive state, so that current switching unit (SW 0 ) is brought into a conductive state. When a difference in voltage between the positive input terminal and the negative input terminal of voltage comparator (B 1 ) is less than the threshold, the second rectifier circuit causes first switching unit (SW 1 ) to be in a conductive state, and causes second switching unit (SW 2 ) to be cut off, so that current switching unit (SW 0 ) is cut off. 
         [0024]    The present disclosure enables a rectifier circuit to have low power losses and to operate at high frequencies, and a contactless power supply device to have an improved power supply capability. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0025]      FIG. 1  illustrates an example configuration of a rectifier circuit according to a first exemplary embodiment of the present disclosure; 
           [0026]      FIG. 2  illustrates an example configuration of a rectifier circuit according to a second exemplary embodiment of the present disclosure; 
           [0027]      FIG. 3  illustrates an example configuration of a rectifier circuit according to a third exemplary embodiment of the present disclosure; 
           [0028]      FIG. 4  illustrates an example configuration of a rectifier circuit according to a fourth exemplary embodiment of the present disclosure; 
           [0029]      FIG. 5  illustrates a rectifier circuit configured by applying, to a second conventional example, a part of the example configuration according to the third exemplary embodiment of the present disclosure; 
           [0030]      FIG. 6  illustrates a rectifier circuit configured by applying, to the second conventional example, a part of the example configuration according to the fourth exemplary embodiment of the present disclosure; 
           [0031]      FIG. 7  illustrates an example of a half-wave rectifier according to a fifth exemplary embodiment of the present disclosure; 
           [0032]      FIG. 8  illustrates an example of a multiplying rectifier according to a sixth exemplary embodiment of the present disclosure; 
           [0033]      FIG. 9  illustrates an example of a full-wave rectifier according to a seventh exemplary embodiment of the present disclosure; 
           [0034]      FIG. 10  illustrates another example of the full-wave rectifier according to the seventh exemplary embodiment of the present disclosure; 
           [0035]      FIG. 11  illustrates an example of a contactless power supply device according to an eighth exemplary embodiment of the present disclosure; 
           [0036]      FIG. 12  illustrates, as a first conventional example, a rectifier circuit in which MOS transistors are used; 
           [0037]      FIG. 13  illustrates, as a second conventional example, a rectifier circuit in which a MOS transistor and bipolar transistors are used; and 
           [0038]      FIG. 14  illustrates a rectifier circuit configured by replacing the bipolar transistors of the rectifier circuit (the second conventional example) with MOS transistors. 
       
    
    
     DETAILED DESCRIPTION 
     First Exemplary Embodiment 
       [0039]      FIG. 1  illustrates an example configuration of a rectifier circuit according to a first exemplary embodiment of the present disclosure. The rectifier circuit of  FIG. 1  includes three terminals A, K, VR and is formed of N-channel MOS transistor SW 0  as a current switching unit, voltage comparator B 1 , and reference voltage generator B 2 . N-channel MOS transistor SW 1  operating as a switch is connected between a source and a gate of N-channel MOS transistor SW 0 . P-channel MOS transistor SW 2  operating as a switch is connected between the gate of N-channel MOS transistor SW 0  and terminal VR. N-channel MOS transistor SW 0  is formed on a triple well, with a back gate connected to the source and to an N-well substrate. QN indicates a parasitic bipolar transistor incorporated inside N-channel MOS transistor SW 0 . 
         [0040]    Reference voltage generator B 2  is formed of N-channel MOS transistor M 2  in which a gate and a drain are commonly connected, and resistor R 2 . Resistor R 2  is connected between terminal VR and the drain of N-channel MOS transistor M 2 . Terminal A is connected to the source of N-channel MOS transistor M 2 . The drain of N-channel MOS transistor M 2  is an output terminal. Capacitor C 0  is connected between terminal VR and the output terminal. Voltage comparator B 1  is formed of N-channel MOS transistor M 1  and resistor R 1 . Terminal K as a positive input terminal is connected to a source of N-channel MOS transistor M 1 . A negative input terminal, to which the output terminal of reference voltage generator B 2  is connected, is connected to a gate of N-channel MOS transistor M 1 . The output terminal commonly connected to gates of N-channel MOS transistor SW 1  and P-channel MOS transistor SW 2  is connected to a drain of N-channel MOS transistor M 1 . The drain of N-channel MOS transistor M 1  is a comparative output terminal. Resistor R 1  is connected between the drain of N-channel MOS transistor M 1  and terminal VR. 
         [0041]    An operation of the rectifier circuit of  FIG. 1  will now be described. An effective DC voltage is applied between terminal A and terminal VR, and an AC voltage is applied to terminal K. A voltage across terminal VR is set to be greater than a voltage across terminal A so that N-channel MOS transistor M 2  can operate. At this time, reference voltage generator B 2  outputs a voltage Vpa+Vgsn 2 , that is, a voltage greater than voltage Vpa across terminal A by voltage Vgsn 2  between the gate and the source of N-channel MOS transistor M 2 . The output voltage from reference voltage generator B 2  is input to a negative input terminal of voltage comparator B 1 . In the case where a threshold voltage of N-channel MOS transistor M 1  is set to Vtn 1 , when AC voltage Vpk across terminal K is greater than Vpa+Vgsn 2 −Vtn 1 , N-channel MOS transistor M 1  is cut off, and an amount of a current flowing through resistor R 1  decreases, so that an output voltage from voltage comparator B 1  approaches the voltage across terminal VR. Correspondingly, P-channel MOS transistor SW 2  is cut off, and N-channel MOS transistor SW 1  is brought into a conductive state. This causes N-channel MOS transistor SW 0  to be cut off, interrupting a current flowing from terminal K to terminal A. At this time, a forward voltage is not applied to an effective diode constituted by parasitic bipolar transistor QN, so that power losses due to a reverse current are negligible. Conversely, when AC voltage Vpk across terminal K is less than Vpa+Vgsn 2 −Vtn 1 , N-channel MOS transistor M 1  is brought into a conductive state, and an amount of a current flowing through resistor R 1  increases, so that an output voltage from voltage comparator B 1  approaches a voltage across terminal K. Correspondingly, P-channel MOS transistor SW 2  is brought into a conductive state, and N-channel MOS transistor SW 1  is cut off. This causes N-channel MOS transistor SW 0  to be in a conductive state, allowing a current to flow from terminal A to terminal K. At this time, a forward voltage is applied to the effective diode constituted by parasitic bipolar transistor QN, with no adverse effect on a rectifying operation. 
         [0042]    The higher a frequency of an AC voltage across terminal K is, the larger a charge-discharge current that flows to the gate of N-channel MOS transistor M 1  when N-channel MOS transistor M 1  is switched. The charge-discharge current is supplied from capacitor C 0 , enabling a high-speed switching of N-channel MOS transistor M 1  and thus enabling the rectifier circuit to operate at high frequencies. Although capacitor C 0  of  FIG. 1  is connected between an output of reference voltage generator B 2  and terminal VR, a similar effect can be achieved by connecting capacitor C 0  between the output of reference voltage generator B 2  and terminal A. If a parasitic capacitance to be added to the output of reference voltage generator B 2  is sufficiently large, the parasitic capacitance arising from, for example, the gate of N-channel MOS transistor M 2 , capacitor C 0  is not necessarily required. 
         [0043]    As described above, the configuration of the rectifier circuit of  FIG. 1  enables the rectifier circuit to operate at high frequencies. However, depending on gate lengths and gate widths of N-channel MOS transistors M 1 , M 2 , a variation in a threshold voltage of voltage comparator B 1  increases, which may result in power losses due to a reverse current flowing from terminal K to terminal A. In that case, a ratio of the gate width to the gate length of N-channel MOS transistor M 1  is selected to be effectively lower than a ratio of the gate width to the gate length of N-channel MOS transistor M 2 . Accordingly, occurrence of a reverse current is prevented by adjusting N-channel MOS transistor SW 0  to be in the conductive state when a voltage across terminal K decreases by greater than fixed offset voltage Vofs relative to a voltage across terminal A and selecting offset voltage Vofs to be greater than or equal to a variation in the threshold voltage of voltage comparator B 1 . 
       Second Exemplary Embodiment 
       [0044]      FIG. 2  illustrates an example configuration of a rectifier circuit according to a second exemplary embodiment of the present disclosure. The rectifier circuit of  FIG. 2  includes three terminals A, K, VR, and is formed of P-channel MOS transistor SW 0  as a current switching unit, voltage comparator B 1 , and reference voltage generator B 2 . P-channel MOS transistor SW 1  operating as a switch is connected between a source and a gate of P-channel MOS transistor SW 0 , and N-channel MOS transistor SW 2  operating as a switch is connected between the gate of P-channel MOS transistor SW 0  and terminal VR. A back gate of P-channel MOS transistor SW 0  is connected to the source. QP indicates a parasitic bipolar transistor incorporated inside P-channel MOS transistor SW 0 . 
         [0045]    Reference voltage generator B 2  is formed of P-channel MOS transistor M 2  in which a gate and a drain are commonly connected, and resistor R 2 . Resistor R 2  is connected between terminal VII and the drain of P-channel MOS transistor M 2 . Terminal K is connected to a source of P-channel MOS transistor M 2 . The drain of P-channel MOS transistor M 2  is an output terminal. Capacitor C 0  is connected between the output terminal and terminal VR. Voltage comparator B 1  is formed of P-channel MOS transistor M 1  and resistor R 1 . Terminal A as a positive input terminal is connected to a source of P-channel MOS transistor M 1 . A negative input terminal, to which the output terminal of reference voltage generator B 2  is connected, is connected to a gate of N-channel MOS transistor M 1 . The output terminal commonly connected to gates of P-channel MOS transistor SW 1  and N-channel MOS transistor SW 2  is connected to a drain of P-channel MOS transistor M 1 . The drain of P-channel MOS transistor M 1  is a comparative output terminal. Resistor R 1  is connected between the drain of P-channel MOS transistor M 1  and terminal VR. 
         [0046]    An operation of the rectifier circuit of  FIG. 2  will now be described. An effective DC voltage is applied between terminal K and terminal VR, and an AC voltage is applied to terminal A. A voltage across terminal VR is set to be less than a voltage across terminal K so that P-channel MOS transistor M 2  can operate. Reference voltage generator B 2  outputs a voltage Vpk−Vgsp 2 , that is, a voltage less than voltage Vpk across terminal K by voltage Vgsp 2  between the gate and the source of P-channel MOS transistor M 2 . The output voltage from reference voltage generator B 2  is input to the negative input terminal of voltage comparator B 1 . In the case where a threshold voltage of P-channel MOS transistor M 1  is set to Vtp 1 , when AC voltage Vpa across terminal A is greater than Vpk−Vgsp 2 +Vtp 1 , P-channel MOS transistor M 1  is brought into a conductive state, and an amount of a current flowing through resistor R 1  increases, so that an output voltage from voltage comparator B 1  approaches a voltage across terminal A. Correspondingly, P-channel MOS transistor SW 1  is cut off, and N-channel MOS transistor SW 2  is brought into a conductive state. This causes P-channel MOS transistor SW 0  to be in a conductive state, allowing a current to flow from terminal A to terminal K. At this time, if a voltage drop of P-channel MOS transistor SW 0  is greater than a threshold voltage between a base and an emitter of parasitic bipolar transistor QP, a collector current flows through parasitic bipolar transistor QP, resulting in power losses. Therefore, a voltage drop of P-channel MOS transistor SW 0  needs to be sufficiently small. Conversely, when AC voltage Vpa across terminal A is less than Vpk−Vgsp 2 +Vtp 1 , P-channel MOS transistor M 1  is cut off, and an amount of a current flowing through resistor R 1  decreases, so that an output voltage from voltage comparator B 1  approaches a voltage across terminal VR. Correspondingly, P-channel MOS transistor SW 1  is brought into a conductive state, and N-channel MOS transistor SW 2  is cut off. This causes P-channel MOS transistor SW 0  to be cut off, interrupting a current flowing from terminal K to terminal A. At this time, a forward voltage is not applied to a voltage between the base and the emitter of parasitic bipolar transistor QP, and thus power losses due to a collector current are negligible. 
         [0047]    The higher a frequency of an AC voltage across terminal A is, the larger a charge-discharge current that flows to the gate of P-channel MOS transistor M 1  when P-channel MOS transistor M 1  is switched. The charge-discharge current is supplied from capacitor C 0 , enabling a high-speed switching of P-channel MOS transistor M 1  and thus enabling the rectifier circuit to operate at high frequencies. Although capacitor C 0  of  FIG. 2  is connected between an output of reference voltage generator B 2  and terminal VR, a similar effect can be achieved by connecting capacitor C 0  between the output of reference voltage generator B 2  and terminal K. If a parasitic capacitance to be added to the output of reference voltage generator B 2  is sufficiently large, the parasitic capacitance arising from, for example, the gate of P-channel MOS transistor M 2 , capacitor C 0  is not necessarily required. 
         [0048]    As described above, the configuration of the rectifier circuit of  FIG. 2  enables the rectifier circuit to operate at high frequencies. However, depending on gate lengths and gate widths of P-channel MOS transistors M 1 , M 2 , a variation in a threshold voltage of voltage comparator B 1  increases, which may result in power losses due to a reverse current flowing from terminal K to terminal A. In that case, a ratio of the gate width to the gate length of P-channel MOS transistor M 1  is selected to be effectively lower than a ratio of the gate width to the gate length of P-channel MOS transistor M 2 . Accordingly, occurrence of a reverse current is prevented by adjusting P-channel MOS transistor SW 0  to be in a conductive state when a voltage across terminal A increases by greater than fixed offset voltage Vofs relative to a voltage across terminal K and selecting offset voltage Vofs to be greater than or equal to a variation in the threshold voltage of voltage comparator B 1 . 
       Third Exemplary Embodiment 
       [0049]      FIG. 3  illustrates an example configuration of a rectifier circuit according to a third exemplary embodiment of the present disclosure. In the rectifier circuit of  FIG. 3 , resistor R 1  and resistor R 2 , which are used in the rectifier circuit of  FIG. 1 , are respectively replaced with P-channel MOS transistors M 3  and M 4  each operating as a constant current source. The rectifier circuit of  FIG. 3  differs from the rectifier circuit of  FIG. 1  in that: a drain and a source of N-channel MOS transistor SW 4  are respectively connected to a source and a back gate of N-channel MOS transistor SW 0 ; a drain and a source of N-channel MOS transistor SW 3  are respectively connected to a drain and the back gate of N-channel MOS transistor SW 0 ; an N-well substrate of N-channel MOS transistor SW 0  formed on a triple well is connected to terminal VR; a gate of N-channel MOS transistor SW 0  is connected to a gate of N-channel MOS transistor SW 3 ; and a comparative output terminal of voltage comparator B 1  is connected to a gate of N-channel MOS transistor SW 4 . P-channel MOS transistors M 3 , M 4 , together with P-channel MOS transistor M 5  in which a gate and a drain are commonly connected, constitute a current mirror circuit. A value of a current flowing through P-channel MOS transistor M 5  is determined from a voltage difference between terminal VII and terminal A, a voltage between the gate and a source of P-channel MOS transistor M 5 , and resistor R 0  connected between the drain of P-channel MOS transistor M 5  and terminal A. 
         [0050]    An operation of the rectifier circuit of  FIG. 3  will now be described. An effective DC voltage is applied between terminal A and terminal VR, and an AC voltage is applied to terminal K. A voltage across terminal VR is set to be greater than a voltage across terminal A so that N-channel MOS transistor M 2  and P-channel MOS transistors M 4 , M 5  can operate. At this time, reference voltage generator B 2  outputs a voltage Vpa+Vgsn 2 , that is, a voltage greater than voltage Vpa across terminal A by voltage Vgsn 2  between a gate and a source of N-channel MOS transistor M 2 . The output voltage from reference voltage generator B 2  is input to a negative input terminal of voltage comparator B 1 . In the case where a threshold voltage of N-channel MOS transistor M 1  is set to Vtn 1 , when AC voltage Vpk across terminal K is greater than Vpa+Vgsn 2 −Vtn 1 , N-channel MOS transistor M 1  is cut off, causing an output voltage from voltage comparator B 1  to be pulled up by P-channel MOS transistor M 3 , so that the output voltage approaches a voltage across terminal VR. Correspondingly, P-channel MOS transistor SW 2  is cut off, and N-channel MOS transistor SW 1  is brought into a conductive state. This causes N-channel MOS transistor SW 0  to be cut off, interrupting a current flowing from terminal K to terminal A. At this time, N-channel MOS transistor SW 4 , as well as N-channel MOS transistor SW 1 , is brought into a conductive state, so that a forward voltage is not applied to a voltage between a base and an emitter of parasitic bipolar transistor QN. Consequently, power losses due to a collector current are negligible. Conversely, when AC voltage Vpk across terminal K is less than Vpa+Vgsn 2 −Vtn 1 , N-channel MOS transistor M 1  is brought into a conductive state, and when an amount of a drain current flowing through M 1  exceeds a predetermined constant current value of P-channel MOS transistor M 3 , an output voltage from voltage comparator B 1  approaches a voltage across terminal K. Correspondingly, P-channel MOS transistor SW 2  is brought into a conductive state, and N-channel MOS transistor SW 1  is cut off. This causes N-channel MOS transistor SW 0  to be in a conductive state, allowing a current to flow from terminal A to terminal K. At this time, N-channel MOS transistor SW 3 , as well as N-channel MOS transistor SW 0 , is brought into a conductive state, so that a forward voltage is not applied to a voltage between the base and the emitter of parasitic bipolar transistor QN. Consequently, power losses due to a collector current are negligible. 
         [0051]    The higher a frequency of an AC voltage across terminal K is, the larger a charge-discharge current that flows to the gate of N-channel MOS transistor M 1  when N-channel MOS transistor M 1  is switched. The charge-discharge current is supplied from capacitor C 0 , enabling a high-speed switching of N-channel MOS transistor M 1  and thus enabling the rectifier circuit to operate at high frequencies. Although capacitor C 0  of  FIG. 3  is connected between an output of reference voltage generator B 2  and terminal VR, a similar effect can be achieved by connecting capacitor C 0  between the output of reference voltage generator B 2  and terminal A. If a parasitic capacitance to be added to the output of reference voltage generator B 2  is sufficiently large, the parasitic capacitance arising from, for example, a gate of N-channel MOS transistor M 2 , capacitor C 0  is not necessarily required. 
         [0052]    The configuration of the rectifier circuit of  FIG. 3  has advantages over the configuration of the rectifier circuit of  FIG. 1 . With the configuration of the rectifier circuit of  FIG. 3 , a transfer gain of voltage comparator B 1  is enhanced by P-channel MOS transistor M 3  that operates at a constant current. Consequently, voltage comparator B 1  is faster. Additionally, the N-well substrate of N-channel MOS transistor SW 0  and a back gate, of a P-channel MOS transistor, connected to terminal VR, can be connected in common, resulting in reduced footprint. 
         [0053]    As described above, the configuration of the rectifier circuit of  FIG. 3  enables the rectifier circuit to operate at high frequencies. However, depending on gate lengths and gate widths of N-channel MOS transistors M 1 , M 2 , a variation in a threshold voltage of voltage comparator B 1  increases, which may result in power losses due to a reverse current flowing from terminal K to terminal A. In that case, a ratio of the gate width to the gate length of N-channel MOS transistor M 1  is selected to be effectively lower than a ratio of the gate width to the gate length of N-channel MOS transistor M 2 . Accordingly, occurrence of a reverse current is prevented by adjusting N-channel MOS transistor SW 0  to be in a conductive state when a voltage across terminal K decreases by greater than fixed offset voltage Vofs relative to a voltage across terminal A and selecting offset voltage Vofs to be greater than or equal to a variation in the threshold voltage of voltage comparator B 1 . 
         [0054]    With regard to offset voltage Vofs, a similar effect can be achieved by setting the constant current value of P-channel MOS transistor M 3  to be greater than a constant current value of P-channel MOS transistor M 4 , and by adjusting the constant current value of P-channel MOS transistor M 3  to coincide with the drain current of P-channel MOS transistor M 1  obtained when a voltage across K decreases by voltage Vofs relative to a voltage across terminal A. 
         [0055]    By adding N-channel MOS transistor  50  and P-channel MOS transistor  51  to a conventional rectifier circuit of  FIG. 14  in which bipolar transistors are replaced with MOS transistors, the modifications in the configuration of the rectifier circuit of  FIG. 3  made to the configuration of the rectifier circuit of  FIG. 1  can be applied to the rectifier circuit of  FIG. 14 .  FIG. 5  illustrates a configuration of a rectifier circuit configured by adding N-channel MOS transistor  50  and P-channel MOS transistor  51  to the rectifier circuit of  FIG. 14 . With the configuration illustrated in  FIG. 5 , resistor R 0  is connected to terminal A on the assumption that an AC voltage is applied to terminal K, and that an effective DC voltage is applied to terminal A. However, if an AC signal is applied to terminal A, and an effective DC voltage is applied to terminal K, a connection terminal for resistor R 0  is changed from terminal A to terminal K, and then the rectifier circuit of  FIG. 5  operates. 
       Fourth Exemplary Embodiment 
       [0056]      FIG. 4  illustrates an example configuration of a rectifier circuit according to a fourth exemplary embodiment of the present disclosure. In the rectifier circuit of  FIG. 4 , resistor R 1  and resistor R 2 , which are used in the rectifier circuit of  FIG. 2 , are respectively replaced with N-channel MOS transistors M 3  and M 4  each operating as a constant current source. Specifically, the rectifier circuit of  FIG. 4  differs from the rectifier circuit of  FIG. 2  in that: a drain and a source of P-channel MOS transistor SW 4  are respectively connected to a source and a back gate of P-channel MOS transistor SW 0 ; a drain and a source of P-channel MOS transistor SW 3  are respectively connected to a drain and the back gate of P-channel MOS transistor SW 0 ; a gate of P-channel MOS transistor SW 0  is connected to a gate of P-channel MOS transistor SW 3 ; and an output terminal of voltage comparator B 1  is connected to a gate of P-channel MOS transistor SW 4 . N-channel MOS transistors M 3 , M 4 , together with N-channel MOS transistor M 5 , in which a gate and a drain are commonly connected, constitute a current mirror circuit such that a value of a current flowing through N-channel MOS transistor M 5  is determined from a voltage difference between terminal VII and terminal A, a voltage between a gate and a source of P-channel MOS transistor M 5 , and resistor R 0  connected between a drain of N-channel MOS transistor M 5  and terminal K. 
         [0057]    An operation of the rectifier circuit of  FIG. 4  will now be described. An effective DC voltage is applied between terminal K and terminal VR, and an AC voltage is applied to terminal A. A voltage across terminal VR is set to be less than a voltage across terminal K so that P-channel MOS transistor M 2  and N-channel MOS transistors M 4 , M 5  can operate. At this time, reference voltage generator B 2  outputs a voltage Vpk−Vgsp 2 , that is, a voltage less than voltage Vpk across terminal K by voltage Vgsp 2  between a gate and a source of P-channel MOS transistor M 2 . The output voltage from reference voltage generator B 2  is input to a negative input terminal of voltage comparator B 1 . In the case where a threshold voltage of P-channel MOS transistor M 1  is set to Vtp 1 , when AC voltage Vpa across terminal A is greater than Vpk−Vgsp 2 +Vtp 1 , P-channel MOS transistor M 1  is brought into a conductive state. With this configuration, when an amount of a drain current flowing through P-channel MOS transistor M 1  exceeds a predetermined constant current value of N-channel MOS transistor M 3 , an output voltage from voltage comparator B 1  approaches a voltage across terminal A. Correspondingly, P-channel MOS transistor SW 1  is cut off, and N-channel MOS transistor SW 2  is brought into a conductive state. This causes P-channel MOS transistor SW 0  to be in a conductive state, allowing a current to flow from terminal A to terminal K. At this time, P-channel MOS transistor SW 3 , as well as P-channel MOS transistor SW 0 , is brought into a conductive state, so that a forward voltage is not applied between a base and an emitter of parasitic bipolar transistor QP. Consequently, power losses due to a collector current are negligible. Conversely, when AC voltage Vpa across terminal A is less than Vpk−Vgsp 2 +Vtp 1 , P-channel MOS transistor M 1  is cut off. This causes N-channel MOS transistor M 3  to pull down an output voltage of voltage comparator B 1 , so that the output voltage of voltage comparator B 1  approaches a voltage across terminal VR. Correspondingly, P-channel MOS transistor SW 1  is brought into a conductive state, and N-channel MOS transistor SW 2  is cut off. This causes P-channel MOS transistor SW 0  to be cut off, interrupting a current flowing from terminal K to terminal A. At this time, P-channel MOS transistor SW 4 , as well as P-channel MOS transistor SW 1 , is brought into a conductive state, so that a forward voltage is not applied between the base and the emitter of parasitic bipolar transistor QP. Consequently, power losses due to a collector current are negligible. 
         [0058]    The higher a frequency of an AC voltage across terminal A is, the larger a charge-discharge current that flows to the gate of P-channel MOS transistor M 1  when P-channel MOS transistor M 1  is switched. The charge-discharge current is supplied from capacitor C 0 , enabling a high-speed switching of P-channel MOS transistor M 1  and thus enabling the rectifier circuit to operate at high frequencies. Although capacitor C 0  of  FIG. 4  is connected between an output of reference voltage generator B 2  and terminal VR, a similar effect can be achieved by connecting capacitor C 0  between the output of reference voltage generator B 2  and terminal K. If a parasitic capacitance to be added to the output of reference voltage generator B 2  is sufficiently large, the parasitic capacitance arising from, for example, the gate of P-channel MOS transistor M 2 , capacitor C 0  is not necessarily required. 
         [0059]    The configuration of the rectifier circuit of  FIG. 2  has advantages over the configuration of the rectifier circuit of  FIG. 4 . With the configuration of the rectifier circuit of  FIG. 4 , a transfer gain of voltage comparator B 1  is enhanced by N-channel MOS transistor M 3  that operates at a constant current. Consequently, voltage comparator B 1  is faster. When P-channel MOS transistor SW 0  is brought into a conductive state, P-channel MOS transistor SW 3  is also brought into a conductive state, so that a forward voltage is not applied between the base and the emitter of parasitic bipolar transistor QP. Consequently, power losses due to a collector current are negligible even when a voltage drop of P-channel MOS transistor SW 0  is large. 
         [0060]    As described above, the configuration of the rectifier circuit of  FIG. 4  enables the rectifier circuit to operate at high frequencies. However, depending on gate lengths and gate widths of P-channel MOS transistors M 1 , M 2 , a variation in a threshold voltage of voltage comparator B 1  increases, which may result in power losses due to a reverse current flowing from terminal K to terminal A. In that case, a ratio of the gate width to the gate length of P-channel MOS transistor M 1  is selected to be effectively lower than a ratio of the gate width to the gate length of P-channel MOS transistor M 2 . Accordingly, occurrence of a reverse current is prevented by adjusting P-channel MOS transistor SW 0  to be in a conductive state when a voltage across terminal A increases by greater than fixed offset voltage Vofs relative to a voltage across terminal K and selecting offset voltage Vofs to be greater than or equal to a variation in the threshold voltage of voltage comparator B 1 . 
         [0061]    With regard to offset voltage Vofs, a similar effect can be achieved by setting the constant current value of N-channel MOS transistor M 3  to be greater than a constant current value of N-channel MOS transistor M 4 , and by adjusting the constant current value of P-channel MOS transistor M 3  to coincide with a drain current of P-channel MOS transistor M 1  obtained when a voltage across terminal K increases by offset voltage Vofs relative to a voltage across terminal A. 
         [0062]    By adding N-channel MOS transistor  50  and P-channel MOS transistor  51  to the conventional rectifier circuit of  FIG. 14 , in which bipolar transistors are replaced with MOS transistors, with an N-channel MOS transistor of the conventional rectifier circuit replaced with a P-channel MOS transistor, modifications in the configuration of the rectifier circuit of  FIG. 4  made to the configuration of the rectifier circuit of  FIG. 2  can be applied to the rectifier circuit of  FIG. 14 .  FIG. 6  illustrates a configuration of a rectifier circuit configured by adding N-channel MOS transistor  50  and P-channel MOS transistor  51  to the conventional rectifier circuit of the configuration. With the configuration illustrated in  FIG. 6 , resistor R 0  is connected to terminal K on the assumption that an AC voltage is applied to terminal A, and that an effective DC voltage is applied to terminal K. However, if an AC signal is applied to terminal K, and an effective DC voltage is applied to terminal A, a connection terminal for resistor R 0  is changed from terminal K to terminal A, and then the rectifier circuit of  FIG. 6  operates. 
       Fifth Exemplary Embodiment 
       [0063]      FIG. 7  illustrates an example configuration of a half-wave rectifier according to a fifth exemplary embodiment of the present disclosure. The half-wave rectifier illustrated in  FIG. 7  includes two input terminals VA, VB, and one output terminal VC, and is formed of rectifier circuit  100  of the present disclosure and smoothening capacitor  110 . Any one of the configurations of  FIGS. 2, 4, and 6  can be applied to rectifier circuit  100 . Terminal A, terminal K, and terminal VR of rectifier circuit  100  are respectively connected to input terminal VB, output terminal VC, and a ground terminal. Smoothening capacitor  110  is connected between output terminal VC and the ground terminal. 
         [0064]    When a voltage across input terminal VB is greater than a voltage across output terminal VC after an AC voltage is applied between input terminals VA and VB, a current flows from terminal A to terminal K of rectifier circuit  100 , causing an electrical charge to accumulate in smoothening capacitor  110 . Conversely, when a voltage across input terminal VB is less than a voltage across output terminal VC, a current flowing from terminal K to terminal A of rectifier circuit  100  is interrupted, so that the electrical charge accumulated in smoothening capacitor  110  is retained, and an effective DC voltage is output to output terminal VC. 
         [0065]    As described above, the rectifier circuit of the present disclosure can operate at high frequencies and has small power losses. Accordingly, applying rectifier circuit  100  of the present disclosure to a half-wave rectifier enables the half-wave rectifier to operate at high frequencies and to be highly efficient. 
       Sixth Exemplary Embodiment 
       [0066]      FIG. 8  illustrates an example configuration of a multiplying rectifier according to a sixth exemplary embodiment of the present disclosure. The multiplying rectifier illustrated in  FIG. 8  includes two input terminals VA, VB, and one output terminal VC, and is formed of rectifier circuits  100 ,  101  of the present disclosure and smoothening capacitors  110 ,  111 . Any one of the configurations of  FIGS. 2, 4, and 6  can be applied to rectifier circuit  100 , and any one of the configurations of  FIGS. 1, 3, and 5  can be applied to rectifier circuit  101 . Terminal A, terminal K, and terminal VR of rectifier circuit  100  are respectively connected to input terminal VB, output terminal VC, and a ground terminal. Terminal A, terminal K, and terminal VR of rectifier circuit  101  are respectively connected to the ground terminal, input terminal VB, and output terminal VC. Smoothening capacitor  110  is connected between output terminal VC and input terminal VA, while smoothening capacitor  111  is connected between input terminal VA and the ground terminal. 
         [0067]    When a voltage across input terminal VB is greater than a voltage across output terminal VC after an AC voltage is applied between input terminals VA and VB, rectifier circuit  100  is brought into a conductive state, allowing a current to flow from input terminal VB to input terminal VA, which causes an electrical charge to accumulate in smoothening capacitor  110 . Conversely, when a voltage across input terminal VB is less than a voltage across output terminal VC, rectifier circuit  100  is cut off, so that the electrical charge accumulated in smoothening capacitor  110  is retained. When a voltage across input terminal VB decreases to be less than a ground potential, rectifier circuit  101  is brought into a conductive state, allowing a current to flow from input terminal VA to input terminal VB, which causes an electrical charge to accumulate in smoothening capacitor  111 . When a voltage across input terminal VB is greater than the ground potential, rectifier circuit  101  is cut off, and the electrical charge accumulated in smoothening capacitor  111  is retained. As a result of the above operation, effective DC voltages across smoothening capacitors  110  and  111  are output in series to output terminal VC, whereby a high DC voltage is obtained. 
         [0068]    As described above, the rectifier circuit of the present disclosure can operate at high frequencies and has small power losses. Accordingly, applying rectifier circuits  100 ,  101  of the present disclosure to a multiplying rectifier enables the multiplying rectifier to operate at high frequencies and to be highly efficient. 
       Seventh Exemplary Embodiment 
       [0069]      FIG. 9  illustrates an example configuration of a full-wave rectifier according to a seventh exemplary embodiment of the present disclosure. The full-wave rectifier illustrated in  FIG. 9  includes two input terminals VA, VB, and one output terminal VC, and is formed of rectifier circuits  100 ,  101 ,  102 , and  103  of the present disclosure and smoothening capacitor  110 . Any one of the configurations of  FIGS. 2, 4, and 6  can be applied to rectifier circuits  100  and  102 , and any one of the configurations of  FIGS. 1, 3, and 5  can be applied to rectifier circuits  101  and  103 . Terminal A, terminal K, and terminal VR of rectifier circuit  100  are respectively connected to input terminal VB, output terminal VC, and a ground terminal. Terminal A, terminal K, and terminal VR of rectifier circuit  101  are respectively connected to the ground terminal, input terminal VB, and output terminal VC. Likewise, terminal A, terminal K, and terminal VR of rectifier circuit  102  are respectively connected to input terminal VA, output terminal VC, and the ground terminal. Terminal A, terminal K, and terminal VR of rectifier circuit  103  are respectively connected to the ground terminal, input terminal VA, and output terminal VC. Smoothening capacitor  110  is connected between output terminal VC and the ground terminal. 
         [0070]    When a voltage across input terminal VB is greater than a voltage across output terminal VC and a voltage across input terminal VA is less than a ground potential after an AC voltage is applied between input terminals VA and VB, rectifier circuits  100  and  103  are brought into the conductive state, allowing a current to flow from input terminal VB to input terminal VA, which causes an electrical charge to accumulate in smoothening capacitor  110 . At this time, rectifier circuits  101  and  102  are cut off. Conversely, when a voltage across input terminal VB is less than the ground potential, and a voltage across input terminal VA is greater than a voltage across output terminal VC, rectifier circuits  101  and  102  are brought into the conductive state, allowing a current to flow from input terminal VA to input terminal VB, which causes an electrical charge to accumulate in smoothening capacitor  110 . At this time, rectifier circuits  100  and  103  are cut off. As a result of the above operation, an effective DC voltage across smoothening capacitor  110  can be obtained from output terminal VC. 
         [0071]    As illustrated in  FIG. 10 , replacing rectifier circuit  101  and rectifier circuit  103  of the full-wave rectifier according to the seventh exemplary embodiment of the present disclosure with N-channel MOS transistor  53  and N-channel MOS transistor  52 , respectively, achieves an operation similar to the operation of the full-wave rectifier according to the seventh exemplary embodiment of the present disclosure. 
         [0072]    As described above, the rectifier circuit of the present disclosure can operate at high frequencies and has small power losses. Accordingly, applying the rectifier circuit of the present disclosure to a full-wave rectifier enables the full-wave rectifier to operate at high frequencies and to be highly efficient. 
       Eighth Exemplary Embodiment 
       [0073]      FIG. 11  illustrates a contactless power supply for an smart card as an example of a contactless power supply device according to an eighth exemplary embodiment of the present disclosure. A contactless smart card incorporates IC chip  200  and antenna  206 , and communicates with host computer  210  via controller  211  and antenna  212 . For a command and data to be transmitted from host computer  210 , controller  211  encodes and modulates the command and the data, superimposes information on a carrier, and radiates an electromagnetic field from antenna  212 . Antenna  206  of the contactless smart card is adjusted by tuning capacitor  207  to be able to receive a carrier frequency easily. Upon reception of the electromagnetic field, rectifier  205  in analog circuit  201  included in IC chip  200  converts an AC voltage of the carrier to an effective DC voltage, and supplies, via a regulator circuit in analog circuit  201 , a DC power source to logic circuit  203 , CPU  202 , and memory circuit  204 . The command and the data from host computer  210  which have been superimposed on the carrier are retrieved from the carrier by a demodulation circuit in analog circuit  201 . After being decoded by logic circuit  203 , the command and the data are transferred to CPU  202 . Based on the command and the data, CPU  202 , for example, executes a program recorded on memory circuit  204  and writes and reads the data. Then, CPU  202  transfers, to logic circuit  203 , a response to host computer  210 . Logic circuit  203  encodes the response to host computer  210 , varies a carrier amplitude via a load modulation circuit in analog circuit  201 , and transfers the response to antenna  212 . The response transferred to antenna  212  is demodulated and decoded by controller  211  and transferred to host computer  210 . 
         [0074]    Applying the rectifier circuit of the present disclosure to rectifier  205  of  FIG. 11  reduces an amount of power consumed by the rectifier circuit. Therefore, enabling CPU  202  to operate at high speeds and increasing a speed of access to memory circuit  204  do not increase an amount of power consumed by overall IC chip  200 , thus enabling a contactless smart card which is faster and which operates at low power. 
         [0075]    The rectifier circuit of the present disclosure is applicable to a contactless power supply device, typified by a contactless smart card and an RFID tag, and to products that generate a DC power source from an AC voltage.