Abstract:
The present invention provides a current detection circuit, a controlling circuit using the current detection circuit and a power conversion circuit using the controlling circuit, the current detection circuit comprises a sample keeping circuit, a rising edge detection circuit, a falling edge detection circuit, a sequential controlling circuit, a synchronous detection circuit and a lowpass filter. The inventive current detection circuit for the power conversion circuit obtains signals of the output current by detecting loop current of the master switch and processing the loop current.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Technical Field 
         [0002]    The present invention relates to circuit technology, and more particularly, to a current detection circuit, a controlling circuit and a power conversion circuit. 
         [0003]    2. Description of Related Art 
         [0004]    A power conversion circuit, such as an AC-DC conversion circuit, can be used to convert AC to DC to provide electricity to relative devices. However, a power conversion circuit in the prior art generally doesn&#39;t possess the function of detecting output current thereof. 
       BRIEF SUMMARY OF THE INVENTION 
       [0005]    The object of the present invention is to provide a current detection circuit for a power conversion circuit in order to detect output current thereof, the current detection circuit has the advantages of high reliable, simple structure and low cost. 
         [0006]    The present invention adopts the following technical solutions to solve the technical problem: a current detection circuit for a power conversion circuit, wherein the current detection circuit includes a sample keeping circuit, a rising edge detection circuit, a falling edge detection circuit, a sequential controlling circuit, a synchronous detection circuit and a lowpass filter, a first end of the sample keeping circuit is connected to a third of the drive controlling transistor S 2 , a second end of the sample keeping circuit is connected to a first end of the sequential controlling circuit, a third end of the sample keeping circuit is connected to a first end of the synchronous detection circuit, a first end of the rising edge detection circuit is connected to a second end of a master switch S 1 , a second end of the rising edge detection circuit is connected to a second end of the sequential controlling circuit, a first end of the falling edge detection circuit is connected to a second end of the master switch S 1 , a second end of the falling edge detection circuit is connected to a third end of the sequential controlling circuit, a fourth end of the sequential controlling circuit is connected to a second end of the synchronous detection circuit, a third end of the synchronous detection circuit is connected to is a first end of the lowpass filter, and a second end of the lowpass filter is an output end of the current detection circuit. 
         [0007]    Another object of the embodiment of the present invention is to provide a controlling circuit using the above-mentioned current detection circuit. 
         [0008]    Another object of the embodiment of the present invention is to provide a power conversion circuit using the above-mentioned controlling circuit, the power conversion circuit further includes: 
         [0009]    a filter circuit  12  connected to an external AC, wherein the filter circuit is used to filter the noise in the AC, 
         [0010]    a rectification circuit  13  connected to the filter circuit and used for converting AC to DC, and 
         [0011]    a single stage power conversion circuit  14  comprising a capacitor Cl, an inductor or switching transformer L, a diode D 1 , a capacitor C 2 , a master switch S 1 , a drive controlling transistor S 2 , a resistor R 2 , a controlling circuit and an auxiliary power supply circuit, a first end of the capacitor C 1  is connected to both of the rectification circuit and a cathode of a DC load, a second of the capacitor C 1  is grounded, a first end of the inductor or switching transformer L is connected to a cathode of the DC load, a second end of the inductor or switching transformer L is connected to an anode of a diode D 1 , a cathode of the diode D 1  is connected to an anode of the DC load, the capacitor C 2  is connected between the anode and cathode of the DC load, a first end of the master switch Si is connected to the cathode of the DC load by the auxiliary power supply circuit, a first end of the master switch S 1  is connected to the anode of the diode D 1 , a first end of the drive controlling transistor S 2  is connected to the controlling circuit, a second end of the drive controlling transistor S 2  is connected to a third end of the master switch S 1 , a third end of the drive controlling transistor S 2  is grounded by the resistor R 2  and connected to the controlling circuit, the controlling circuit is further connected to a second end of the master switch S 1 , the single stage power conversion circuit is used to adjust a power factor and obtain signals of output current by detecting loop current of the master switch and processing the loop current. 
         [0012]    The inventive current detection circuit of the power conversion circuit obtains the signals of the output current by detecting loop current of the master switch and processing the loop current. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0013]      FIG. 1  is a circuit diagram of a power conversion circuit using the current detection circuit according to the present invention; 
           [0014]      FIG. 2  is a schematic circuit diagram of a controlling circuit using the current detection circuit in  FIG. 1  according to the present invention; 
           [0015]      FIG. 3  is a circuit diagram of the current detection circuit according to a first preferable embodiment; 
           [0016]      FIG. 4  is a circuit diagram of the current detection circuit according to a second preferable embodiment; 
           [0017]      FIG. 5  is a schematic waveform view of each node in  FIG. 1  and  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0018]    In order to make clearer the objects, technical solutions and advantages of the invention, the present invention will be explained below in detail with reference to the accompanying drawings and embodiments. It is to be understood that the following description of the embodiments is merely to explain the present invention and is no way intended to limit the invention. 
         [0019]    The current detection circuit for a power conversion circuit provided by the embodiments of the present invention can be used to detect output current of the power conversion circuit, and the current detection circuit has the advantages of high reliable and simple structure. 
         [0020]    Referring to  FIG. 1 , the inventive power conversion circuit includes a filter circuit  12 , a rectification circuit  13  and a single stage power conversion circuit  14 . 
         [0021]    The filter circuit  12  is connected to a live wire L and a null line N of an external AC. 
         [0022]    The rectification circuit  13  is connected to the external AC by the filter circuit  12 . 
         [0023]    The single stage power conversion circuit  14  is connected between a positive output end of the rectification circuit  13  and a DC load  15 . A node between the positive output end of the rectification circuit  13  and the DC load  15  can be referred as “C”. 
         [0024]    The filter circuit  12  can use a filter circuit well known and the rectification circuit  13  can use a bridge rectifier circuit, which doesn&#39;t be repeated here. 
         [0025]    The single stage power conversion circuit  14  includes a capacitor C 1 , an inductor or switching transformer L, a diode D 1 , a capacitor C 2 , a master switch S 1 , a drive controlling transistor S 2 , a resistor R 2 , a controlling circuit  16  and an auxiliary power supply circuit  17 . 
         [0026]    A first end of the capacitor C 1  is connected to both of the rectification circuit  13  and a cathode of the DC load  15 , a second end of the capacitor C 1  is grounded, a first end of the inductor or switching transformer L is connected to a cathode of the DC load  15 , the second end of the inductor or switching transformer L is connected to an anode of the diode D 1 , a cathode of the diode D 1  is connected to an anode of the DC load  15 , the capacitor C 2  is connected between the anode and cathode of the DC load  15 , a first end of the master switch S 1  is connected to the cathode of the DC load  15  by the auxiliary power supply circuit  17 , a second end of the master switch S 1  is connected to the anode of the diode D 1 , a first end of the drive controlling transistor S 2  is connected to a first end H of the controlling circuit  16 , a second end of the drive controlling transistor S 2  is connected to a third end of the master switch S 1 , a third end of the drive controlling transistor S 2  is grounded by a resistor R 2  and also connected to a second end U of the controlling circuit  16 , and a third end D of the controlling circuit  16  is connected to a second end of the master switch S 1 . 
         [0027]    Both of the master switch Si and the drive controlling transistor S 2  are N-channel field effect transistors. A node between a drain of the master switch S 1  and the anode of the diode D 1  can be referred as D, a node between a grid of the master switch S 1  and the auxiliary power supply circuit  17  can be referred as E, and a node between a drain of the drive controlling transistor S 2  and a source of the master switch S 1  can be referred as F. 
         [0028]    Referring to  FIG. 2 , the controlling circuit  16  includes a valley detection circuit  161 , a current detection circuit  162 , an error amplifier Err amp, a PWM controller U 1  and a drive controlling circuit  163 , the input end U of the current detection circuit  162  is connected to a third end of the drive controlling transistor S 2 , the input end D of the current detection circuit  162  is connected to a second end of the master switch S 1 , an output end of the current detection circuit  162  is connected to an input end of the error amplifier Err_amp, an output end of the error amplifier is connected to the PWM controller U 1 , the PWM controller U 1  is connected to a first end of the drive controlling circuit  163 , a second end of the drive controlling circuit  163  is connected to an output end of the valley detection circuit  161 , a third end of the drive controlling circuit  163  is connected to a first end of the drive controlling transistor S 2 , and an input end of the valley detection circuit  161  is connected to a second end of the master switch S 1 . 
         [0029]    The auxiliary power supply circuit  17  includes a diode D 2 , a resistor R 1 , a capacitor C 6  and a voltage regulator Z 2 , an anode of the diode D 2  is connected to the a cathode of the DC load  15 , a cathode of the diode D 2  is grounded through the resistor R 1  and the capacitor C 6  in turn, a node between the resistor R 1  and the capacitor C 6  is connected to the first end of the master switch S 1 , an anode of the voltage regulator Z 2  is grounded, and a cathode of the voltage regulator Z 2  is connected to the first end of the master switch S 1 . 
         [0030]    The working process of the inventive power conversion circuit is described as follows. 
         [0031]    The filter circuit  12  is used to filter noise in the AC, the rectification circuit  13  is used for AC-DC conversion, and the single stage power conversion circuit  14  is used to adjust a power factor of the power conversion circuit and detect the output current thereof. The auxiliary power supply circuit  17  in the single stage power conversion circuit  14  is used to provide an auxiliary power supply, the controlling circuit  16  is used to detect current output to the DC load  15  and adjust an average value of the current output to the DC load  15  to be equal to a predefined value defined by the DC load  15 , thereby, the current output to the DC load  15  is kept constant. 
         [0032]    When a node E of an input controlling end of the master switch S 1  is powered on, the node E is clamped at fixing electrical level, the switching on and off of the master switch S 1  is mainly controlled by the drive controlling transistor S 2 . During the switching on of the master switch S 1 , the current of the inductor L rises, when the master switch S 1  is switched off, due to the stray capacitance of the master switch S 1  and the diode D 1 , the voltage of a node D of an upper end of the master switch S 1  rises from zero (zero voltage turn-off), when the electric potential of the node D exceeds the electric potential of a node K of the DC load  15 , the diode D 1  is switched on, the current of the inductor L is output to the DC load  15  through the diode D 1 , the current of the inductor L drops from a peak value, when the current of the inductor L drops to zero, due to the resonance between the stray capacitance of the master switch Si and the diode D 1  and the inductor L, the electric potential of the upper node D of the master switch S 1  begins to drop, the voltage of the upper node D of the master switch S 1  will arrives at a valley value after a period of time. 
         [0033]    The valley detection circuit  161  is used to control switching on time of the single stage power conversion circuit  14 , the voltage of the end D is detected, when a value of the voltage is equal to a valley value, the detected result is sent to the drive controlling circuit  163  and the master switch S 1  is driven to switch on by the drive controlling circuit  163  and the drive controlling transistor S 2 , zero voltage turn-on is realized, therefore, switching loss of the valley detection circuit  161  is low. In the working process of the power conversion circuit, if switching on duration of the master switch S 1  is increased, working current of the inductor L and current of the output load  15  are increased, if switching on duration of the master switch S 1  is decreased, the working current of the inductor L and the current of the output load  15  are decreased. 
         [0034]      FIG. 2  also can be referred at the same time, the controlling circuit  16  and the single stage power conversion circuit  14  are connected by three ends D, U and H. With regard to the controlling circuit  16 , the ends D, U are output ends of the controlling circuit  16 , based on information of the ends D, U, controlling signals are generated at the end H by the controlling circuit  16 , and then the controlling signals are used to control the drive controlling transistor S 2  so as to control working process of the single stage power conversion circuit  14 . The controlling circuit  16  needs to obtain current information of the output load  15  to control a switch circuit, therefore, better power efficiency and power factor can be obtained. 
         [0035]    In the present, the power conversion circuit filters the noise in the AC by the filter circuit  12 , an AC-DC conversion is performed by the rectification circuit  13 , and the single stage power conversion  14  detects the current output to the DC load and adjusts the power factor. 
         [0036]    Furthermore, the power conversion circuit in the present invention also includes a fuse F 1 . The fuse F 1  is connected between the live wire L and the filter circuit  12 , when the current flowing through the fuse F 1  is excessive, the fuse F 1  is blown to protect the power conversion circuit. 
         [0037]    Referring to  FIG. 2  again, furthermore, the current detection circuit  162  includes a sample keeping circuit  1 , a rising edge detection circuit  2 , a falling edge detection circuit  3 , a sequential controlling circuit  4 , a synchronous detection circuit  5  and a lowpass filter  6 . 
         [0038]    A first end S 11  of the sample keeping circuit  1  is connected to the end U, a second end S 12  of the sample keeping circuit  1  is connected to a first end S 41  of the sequential controlling circuit  4 , and a third end S 13  of the sample keeping circuit  1  is connected to a first end S 51  of the synchronous detection circuit  5 . 
         [0039]    A first end S 21  of the rising edge detection circuit  2  is connected to the node D, and a second end S 22  of the rising edge detection circuit  2  is connected to a second S 42  of the sequential controlling circuit  4 . 
         [0040]    A first end S 31  of the falling edge detection circuit  3  is connected to the node D, and a second end S 32  of the falling edge detection circuit  3  is connected to a third end S 43  of the sequential controlling circuit  4 . 
         [0041]    A fourth end S 44  of the sequential controlling circuit  4  is connected to a second end S 52  of the synchronous detection circuit  5 . 
         [0042]    A third end S 53  of the synchronous detection circuit  5  is connected to a first end S 61  of the lowpass filter  6 , a second end S 62  of the lowpass filter  6  is connected to an input end of the error amplifier Err_amp. 
         [0043]    The controlling circuit  16  detects current of the sample resistor R 2  by the current detection circuit  162 , signals of the detected current are processed to obtain an average value of the current output to the DC load  15 , then the average value is input to the drive controlling circuit  163  and used to compare with a predefined value, based on the comparison whether the switching on time of the master switch S 1  is increased or decreased is determined, which can make the output current be equal to the predefined value. Whatever the DC load or an input voltage fluctuates, the drive controlling circuit  163  can dynamically adjust switching on and off durations of the master switch S 1  so as to obtain the output current desired by the DC load  15 . 
         [0044]    Referring to  FIG. 3 , as a preferable embodiment, the sample keeping circuit  1  of the current detection circuit  162  includes a N-channel field effect transistor N 1 , an inverter INV 1 , a capacitor C 3 , an amplifier A 1 , resistors R 3  and R 4 . A drain of the N-channel field effect transistor N 1  is connected to the node U, a grid of the N-channel field effect transistor N 1  is connected to an input end of the inverter INV 1 , a source of the N-channel field effect transistor N 1  is grounded by the capacitor C 3 . The input end of the inverter INV 1  is connected to a controlling end  CTL . A noninverting input end of the amplifier A 1  is connected to the source of the N-channel field effect transistor N 1 , an inverting input end of the amplifier A 1  is grounded by the resistor R 3 , an output end of the amplifier A 1  is connected to the inverting input end thereof by the resistor R 4 . During the switching on time of the master switch S 1 , the current sample keeping circuit  1  keeps on sampling, and outputs a signal proportional to the input current thereof, after the master switch S 1  is switched off, the sample keeping circuit  1  maintains sampling. 
         [0045]    The rising edge detection circuit  2  includes an amplifier A 2 , resistors R 5  and R 6 . One end of the resistor R 5  is connected to the node D, the other end of the resistor R 5  is grounded by the resistor R 6 . A noninverting input of the amplifier A 2  is connected to a node between the resistors R 5  and R 6 , an inverting input of the amplifier A 2  is connected to a reference voltage end VREF 2 . When the rising edge detection circuit  2  detects that the voltage of the upper end of the master switch S 1  rises to a predefined value, the rising edge detection circuit  2  triggers a latch circuit to control the synchronous detection circuit  5  to output signals from the current sample keeping circuit  1  to the lowpass filter  6 . 
         [0046]    The falling edge detection circuit  3  includes an amplifier A 3 , an inverter INV 2 , a N-channel field effect transistor N 2 , a capacitor C 4 , clamping. zeners Z 1 -Z 4 , resistors R 7  and R 8 . One end of the resistor R 7  is connected to the node D, the other end is grounded by the resistor R 8 . One end of the capacitor C 4  is connected to a node between the resistors R 7  and R 8 , the other end is connected to a noninverting input of the amplifier A 3 . An inverting input of the amplifier A 3  is connected to a reference voltage end VREF 1 , an output end of the amplifier A 3  is connected to an input end of the inverter INV 2 . Both of a grid and drain of the N-channel field effect transistor N 2  are connected to the noninverting input of the amplifier A 3 , a source of the N-channel field effect transistor N 2  is grounded. A cathode of the clamping zener Z 1  is connected to a node between resistors R 7  and R 8 , an anode of the clamping zener Z 1  is grounded by the clamping zener Z 2 -Z 4  in turn. When the falling edge detection circuit  3  detects that a falling edge of the voltage of the upper end of the master switch Si, the falling edge detection circuit  3  unlocks a latch and shutdowns the synchronous detection circuit  5 , so that the input signals of the lowpass filter  6  change to zero. 
         [0047]    The sequential controlling circuit  4  includes D-flip flops DF 1  and DF 2 . A clock signal end CK of the D-flip flop DF 1  is connected to an output of the inverter INV 2  in the falling edge detection circuit  3 , a reset end R of the D-flip flop DF 1  is connected to an output of the inverter INV 1  in the sample keeping circuit  1 , a signal input end D of the D-flip flop DF 1  is connected to a power supply VDD, an output end Q of the D-flip flop DF 1  is connected to a reset end R of the D-flip flop DF 2 , a noninvertering output end QB of the D-flip flop DF 1  is not used. A clock signal end CK of the D-flip flop DF 2  is connected to an output end of the amplifier A 2 , a signal input end D of the D-flip flop DF 2  is connected to the power supply VDD, an output end Q of the D-flip flop DF 2  is not used. 
         [0048]    The synchronous detection circuit  5  includes an inverter INV 3 , N-channel field effect transistors N 3  and N 4 . An input end of the inverter INV 3  is connected to an inverting output end QB of the D-flip flop DF 2  in the sequential controlling circuit  4 , an output end of the inverter INV 3  is connected to a grid of the N-channel field effect transistor N 3 . A drain of the N-channel field effect transistor N 3  is connected to an output end of the amplifier A 1  in the sample keeping circuit  1 , a source of the N-channel field effect transistor N 3  is connected to a drain of the N-channel field effect transistor N 4 . A grid of the N-channel field effect transistor N 4  is connected to an input end of the inverter INV 3 , a source of the N-channel field effect transistor N 4  is grounded. 
         [0049]    The lowpass filter  6  includes a resistor R 9  and a capacitor C 5 . One end of the resistor R 9  is connected to a drain of the N-channel field effect transistor N 4  in the synchronous detection circuit  5 , the other end is grounded by the capacitor C 5  and also connected to an input end of the error amplifier, the lowpass filter  6  filters an input signal thereof and outputs a signal directly proportional to an average value of the output current of the DC load  15 . 
         [0050]      FIG. 5  can be referred at the same time, the current waveform of the inductor L is referred as I_L, the current waveform of the diode D 1  is referred as I_D 1 , the voltage waveform of the node D is referred as V_D, the waveform of the output signal of the sample keeping circuit  1  is referred as S_H_out, the waveform of the output signal of the synchronous detection circuit  5  is referred as Syn_out, the signal waveform of the output end Q of the D-flip flop DF 1  is referred as DF 1 _Q, the signal waveform of the inverting output end QB of the D-flip flop DF 2  is referred as DF 2 _QB. 
         [0051]    As shown in  FIG. 5 , the average value I_avr of the current output to the DC load  15  is equal to the average value of the I_D 1 , namely, equal to the value of multiplying a duty cycle by the value of dividing a peak value of the I_D 1  by 2. According to practical application, just a signal proportional to I_avr is needed. Next will describes how the current detection circuit  162  obtains the signal. 
         [0052]    When the master switch S 1  is switched on, the signal of the end U is input to the sample keeping circuit  1 . During the switching on of the master switch S 1 , the sample keeping circuit  1  keeps on sampling, output signals S_H_out are used to track the current I_L of the inductor L, the synchronous detection circuit  5  is switched off, the output signals of the synchronous detection circuit  5  are low level. 
         [0053]    When the switching on duration of the master switch S 1  is ended, the voltage V_F of the node F rises, the master switch S 1  is switched off, the electric potential V_D of the end D rises, when the electric potential of the node D approximates the electric potential of the node C, the current I_L of the inductor L discharge to the DC load  15  through the diode D 1 . The rising edge detection circuit  2  acts and outputs action signals to the sequential controlling circuit  4 , then the sample keeping circuit  1  is controlled to maintain sampling by the sequential controlling circuit  4 , the sample keeping circuit  1  maintains a voltage proportional to a peak current of the inductor L, the peak current of the inductor L is equal to a peak current of the diode D 1 , therefore, the output S_H_out of the sample keeping circuit  1  is proportional to a peak value of the current I_D 1  of the diode D 1 . 
         [0054]    Before the current I_L of the inductor L drops to zero, since the sample keeping circuit  1  maintains sampling, the signal remains the same all the time. The synchronous detection circuit  5  is switched on, the output S_H_out of the sample keeping circuit  1  is output to the lowpass filter  6  through the synchronous detection circuit  5 . As the current I_L of the inductor L discharges to the DC load  15  through the diode D 1 , the current I_L of the inductor L gradually drops. 
         [0055]    When the current I_L of the inductor L drops to zero, the electric potential of the node D begins to drop, when the signal indicating that the electric potential of the node D begins to drop is detected by the falling edge detection circuit  3 , the falling edge detection circuit  3  acts and outputs action signals to the sequential controlling circuit  4 , the sequential controlling circuit  4  switches off the synchronous detection circuit  5  to make the input signal of the lowpass filter  6  being zero. In the switching on duration, the average value of the input signals output to the lowpass filter  6  is directly proportional to the average value of the output current, namely, a signal output by the lowpass filter is directly proportional to the average value of the output current I_avr. 
         [0056]    The current signals output by the lowpass filter  6  and an internal reference value defined by the lowpass filter  6  are sent to the error amplifier Err_amp, if the average value of the output current is greater than the internal reference value, the output of the error amplifier Err_amp controls the switching on duration of the master switch S 1  to gradually decrease by the PWM controller U 1 , if the average value of the output current is smaller than the internal reference value, the output of the error amplifier Err_amp controls the switching on duration of the master switch  51  to gradually increase by the PWM controller U 1 . At last, the average value of the output current is equal to the internal reference value, and the output current is constant. 
         [0057]    After the switching off duration of the master switch S 1  is ended, the master switch S 1  is switched on again, the circuit enters the next circle. 
         [0058]    When the V_F is low level, the master switch S 1  is switched on, the end D 2 _QB of the D-flip flop DF 2  outputs high level. Signals of the current sample resistor R 2  are output to the field effect transistor N 1  of the sample keeping circuit  1 . A timing sequence of the signal applied on the grid of the field effect transistor N 1  is synchronous with the driving signal of the master switch S 1 . When the master switch S 1  is switched on, the controlling end  CTL  of the master switch S 1  is high level (being inverting to the V_F), the sample keeping circuit  1  keeps on sampling, the output of the D 1 _Q of the D-flip flop DF 1  of the sequential controlling circuit  4  is high level, the output of the D 2 _QB of the D-flip flop DF 2  is high level, the field effect transistor N 4  of the synchronous detection circuit  5  is grounded, the field effect transistor N 3  of the synchronous detection circuit  5  is switched off, and the output of the synchronous detection circuit  5  is zero. 
         [0059]    When the switching on duration of the master switch S 1  is ended, the master switch S 1  is switched off, the electrical level of the controlling end  CTL  of the master switch S 1  changes to low level, the sample keeping circuit  1  maintains the sampling, the D-flip flop DF 1  is reset, the output of the D 1 _Q of the D-flip flop DF 1  is low level, and a reset status of the D-flip flop DF 2  is terminated. As the master switch S 1  is switched off, the electric potential V_D of the upper end D rises, when the electric potential V_D approaches the electric potential of the node C, the rising edge detection circuit  2  acts, the output of the A 2  amplifier becomes higher, and then triggers the output of the D 2 _QB of the D-flip flop DF 2  to become lower, thereby switching on the field effect transistor N 3  of the synchronous detection circuit  5  and switching off the field effect transistor N 4  of the synchronous detection circuit  5 , the output signal of the sample keeping circuit  1  is output to the, input end of the low filter circuit  6 . At this moment, the current I_L of the inductor L discharges to the DC load  15 , the current gradually drops. 
         [0060]    Referring to  FIG. 4  again, as an inventive preferable embodiment, the N-channel field effect transistor N 1  in the falling edge detection circuit  3  of the current detection circuit  162  can be replaced by a diode D 3 . An anode of the diode D 3  is connected to the noninverting input end of the amplifier A 1 , a cathode of the diode D 3  is grounded. 
         [0061]    In the present invention, the power conversion circuit filters the nose in the AC by the filter circuit  12 , the rectification circuit  13  is used for AC-DC conversion, the single stage power conversion  14  is used for adjusting the power factor and adjusting the average value of the output current to be equal to the predefined value, therefore, the constant current output is obtained. 
         [0062]    The present invention has been further detailed in the above descriptions with reference to the preferred embodiments; however, it shall not be construed that implementations of the present invention are only limited to these descriptions. Many simple deductions or replacements may further be made by those of ordinary skill in the art without departing from the conception of the present invention, and all of the deductions or replacements shall be considered to be covered within the protection scope of the present invention.