Abstract:
Structures and methods for forming the same. A semiconductor fabrication method comprises a step of providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate and a capacitor electrode on the semiconductor substrate. The capacitor electrode comprises dopants, and is electrically insulated from the semiconductor substrate by a capacitor dielectric layer. The semiconductor structure further includes a semiconductor layer on the semiconductor substrate. The semiconductor layer comprises a trench which partially but not completely overlaps the capacitor electrode. The method further comprises the step of causing some of the dopants of the capacitor electrode to diffuse into the semiconductor layer, resulting in a doped source/drain region. The doped source/drain region overlaps the capacitor electrode and abuts a sidewall of the trench.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Technical Field 
         [0002]    The present invention relates to semiconductor devices, and more specifically, to semiconductor devices with one-sided buried straps. 
         [0003]    2. Related Art 
         [0004]    In a conventional fabrication process of a DRAM cell, the transistor of the DRAM cell can be formed around a trench and electrically coupled to the capacitor through a buried strap region. As the sizes of the devices on the substrate become smaller and smaller, there is a need to form the buried strap region on only one side of the trench. As a result, there is a need for a simpler method for forming the transistor with the one-sided buried strap. 
       SUMMARY OF THE INVENTION 
       [0005]    The present invention provides a semiconductor structure, comprising (a) a semiconductor substrate; (b) a capacitor electrode on the semiconductor substrate, wherein capacitor electrode comprises dopants, and wherein the capacitor electrode is electrically insulated from the semiconductor substrate by a capacitor dielectric layer; (c) a first doped source/drain region on the capacitor electrode, wherein the doped source/drain region is electrically coupled to the capacitor electrode; and (d) a gate electrode on the capacitor electrode, wherein the gate electrode partially but not completely overlaps the capacitor electrode. 
         [0006]    The present invention provides a semiconductor structure fabrication method, comprising providing a semiconductor structure which includes: (a) a semiconductor substrate, (b) a capacitor electrode on the semiconductor substrate, wherein the capacitor electrode is electrically insulated from the semiconductor substrate by a capacitor dielectric layer, and wherein the capacitor electrode comprises dopants, and (c) a semiconductor layer on the semiconductor substrate, wherein the semiconductor layer comprises a trench, and wherein the trench partially but not completely overlaps the capacitor electrode; and causing some of the dopants of the capacitor electrode to diffuse into the semiconductor layer, resulting in a first doped source/drain region, wherein the first doped source/drain region overlaps the capacitor electrode, and wherein the first doped source/drain region abuts a sidewall of the trench. 
         [0007]    The present invention provides a simpler method for forming a semiconductor device with the one-sided buried strap. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIGS. 1A-1M  illustrate a first fabrication method for forming a first semiconductor structure, in accordance with embodiments of the present invention. 
           [0009]      FIGS. 2A-2J  illustrate a second fabrication method for forming a second semiconductor structure, in accordance with embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0010]      FIGS. 1A-1M  illustrate a fabrication method for forming a semiconductor structure  100 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , in one embodiment, the fabrication of the semiconductor structure  100  starts out with a semiconductor substrate  110 . Illustratively, the semiconductor substrate  110  comprises a semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), and those materials consisting essentially of one or more compound semiconductors such as gallium arsenic (GaAs), gallium nitride (GaN), and indium phosphoride (InP), etc. 
         [0011]    Next, in one embodiment, an insulating layer  112  is formed on top of the semiconductor substrate  110 . In one embodiment, the insulating layer  112  comprise silicon oxide formed by thermal oxidation or by CVD (Chemical Vapor Deposition). 
         [0012]    Next, with reference to  FIG. 1B , in one embodiment, trenches  120   a  and  120   b  are formed in the structure  100  of the  FIG. 1A . In one embodiment, the trenches  120   a  and  120   b  are formed using a conventional patterning and etching processes. 
         [0013]    Next, with reference to  FIG. 1C , in one embodiment, node dielectric layers  130   a  and  130   b  are formed on side walls and bottom walls of the trenches  120   a  and  120   b,  respectively. The dielectric layers  130   a  and  130   b  may comprise any dielectric material, including but not limited to, silicon nitride, silicon oxide, silicon oxynitride, high-k (high dielectric) material, or any suitable combination of these materials. The dielectric layers  130   a  and  130   b  can be formed by any suitable process, including but not limited to thermal oxidation, thermal nitridation, CVD, and/or ALD (atomic layer deposition). 
         [0014]    Next, in one embodiment, the trenches  120   a  and  120   b  are filled with a conducting material, resulting in capacitor electrodes  140   a  and  140   b  in  FIG. 1D . Illustratively, the capacitor electrodes  140   a  and  140   b  ( FIG. 1D ) are formed by depositing an N-type doped polysilicon on top of the entire structure  100  in  FIG. 1C  (including in the trenches  120   a  and  120   b ) and then planarizing by a CMP (chemical mechanical polishing) step to remove the excessive polysilicon outside the trenches  120   a  and  120   b.    
         [0015]    FIG.  1 Da illustrates a semiconductor structure  100   a,  in accordance with embodiments of the present invention. More specifically, with reference to FIG.  1 Da, in one embodiment, the fabrication of the semiconductor structure  100   a  starts out with a semiconductor substrate  210 . The semiconductor substrate  210  may comprise a material as same as or different from the substrate  110 . Furthermore, the semiconductor substrate  210  may have a crystallographic orientation as same as or different from the crystallographic orientation of the substrate  110 . 
         [0016]    Next, in one embodiment, optionally, a dielectric layer  212  is formed on top of the semiconductor substrate  210  to facilitate the subsequent bonding process. The dielectric layer  212 , when present, has a thickness thin enough to allow dopants to diffuse through it and allow carriers (electrons and holes) to tunneling through it. More specifically, the dielectric layer  212  may comprises a thin silicon nitride, silicon carbide, or silicon oxide formed by thermal oxidation, thermal nitridation, chemical oxidation, chemical nitridation, CVD, or ALD process. Preferably, the dielectric layer  212  has a thickness ranging from about 5 to 25 angstroms, and more preferably from 5 to 15 angstroms, and most preferably from 7 to 10 angstroms. 
         [0017]    Next, in one embodiment, the structure  100   a  in FIG.  1 Da is turned upside down and then bonded to a top surface  116  of the structure  100  in  FIG. 1D , resulting in the structure  100  of  FIG. 1E . Next, in one embodiment, the substrate  210  can be thinned to the desired thickness by cleaving, grinding, polishing, or combination of some or all of these processes. 
         [0018]    Next, with reference to  FIG. 1F , in one embodiment, a pad layer  220  is formed on top of the structure  100  of  FIG. 1E . In one embodiment, the pad layer  220  comprises silicon nitride on top of the region  210 . In one embodiment, the pad layer  220  is formed by CVD. 
         [0019]    Next, with reference to  FIG. 1G , in one embodiment, offset trenches  230   a  and  230   b  are formed in the pad layer  220  and the semiconductor substrate  210  of the  FIG. 1F , in which the offset trenches  230   a  and  230   b  can be aligned to the trenches  120   a  and  120   b,  respectively, with an offset  232  (as shown in  FIG. 1G ). In one embodiment, the offset trenches  230   a  and  230   b  are formed using conventional patterning and etching processes. In one embodiment, the step of etching to form the offset trenches  230   a  and  230   b  essentially stops at the dielectric layer  212 . 
         [0020]    Next, with reference to  FIG. 1H , in one embodiment, insulating layers  240   a  and  240   b  are formed in the offset trenches  230   a  and  230   b,  respectively. In one embodiment, the insulating layers  240   a  and  240   b  comprise silicon oxide formed by HDP (high density plasma) deposition followed by a timed etchback to remove the deposited material from the trench sidewall, leaving TTO (trench top oxide) at the bottom of the offset trenches  230   a  and  230   b.  The insulating layer material  240   c  may also be formed on top of the pad layer  220 . 
         [0021]    Next, in one embodiment, the structure  100  in  FIG. 1H  is heated up at a temperature to form one-sided buried straps  250   a  and  250   b  (also called doped source/drain regions  250   a  and  250   b ) as shown in  FIG. 1I . During the heating step, the dopants in the doped polysilicon of the capacitor electrodes  140   a  and  140   b  diffuse into the semiconductor substrate  210 , resulting in the one-sided buried straps  250   a  and  250   b  in  FIG. 1I . Preferably, the annealing step is performed at a temperature ranging from 800 to 1150 Celsius degrees for duration from 5 seconds to 120 minutes. Alternatively, the buried straps  250   a  and  250   b  can be formed by driving the dopants in the doped polysilicon of the capacitor electrodes  140   a  and  140   b  into the substrate  210  in the later thermal processes. 
         [0022]    As described above, the dielectric layer  212 , if present, is thin enough to allow dopants to diffuse through it and allow carriers (electrons and holes) to tunnel through it to ensure a good electrical connection between the buried straps ( 250   a  and  250   b ) and the capacitor electrodes  140   a  and  140   b,  respectively. 
         [0023]    Next, with reference to  FIG. 1J , in one embodiment, gate dielectric regions  260   a  and  260   b  are formed on side walls of the offset trenches  230   a  and  230   b,  respectively. In one embodiment, the gate dielectric regions  260   a  and  260   b  can be formed by thermally oxidizing side wall surfaces  232   a  and  232   b  of the offset trenches  230   a  and  230   b,  respectively. 
         [0024]    Next, in one embodiment, the offset trenches  230   a  and  230   b  are filled with a conducting material, resulting in gate electrodes  270   a  and  270   b  in  FIG. 1K . Illustratively, the gate electrodes  270   a  and  270   b  are formed by depositing polysilicon on top of the entire structure  100  in  FIG. 1J  (including in the offset trenches  230   a  and  230   b ) and then polishing by a CMP step to remove the excessive polysilicon outside the offset trenches  230   a  and  230   b.  The TTO material  240   c  on top of the pad layer  220  can be removed by conventional etching process at this step. 
         [0025]    Next, with reference to  FIG. 1L , in one embodiment, well regions  280   a  and  280   b  are formed in the semiconductor substrate  210 . In one embodiment, the well regions  280   a  and  280   b  are formed by ion implantation of P-type dopants such as boron or indium. 
         [0026]    Next, with reference to  FIG. 1M , in one embodiment, source/drain regions  290   a  and  290   b  are formed in the P-well regions  280   a  and  280   b,  respectively. In one embodiment, the source/drain regions  290   a  and  290   b  (also called second doped source/drain regions  290   a  and  290   b ) are formed by ion implantation of N-type dopants such as phosphorous or arsenic. 
         [0027]    It should be noted that there are first and second DRAM (Dynamic Random Access Memory) cells in  FIG. 1M . More specifically, the first DRAM cell comprises a first capacitor  140   a + 130   a + 110  and a first vertical transistor  250   a + 260   a + 270   a + 282   a + 290   a,  which are electrically coupled together. The first capacitor  140   a + 130   a + 110  comprises a capacitor dielectric layer  130   a,  a first capacitor electrode  140   a,  and a second capacitor electrode  110 . The first vertical transistor  250   a + 260   a + 270   a + 282   a + 290   a  comprises a first source/drain region  250   a,  a second source/drain region  290   a,  a channel region  282   a  (a portion of the P-well region  280   a  as shown in  FIG. 1M ), the gate dielectric region  260   a,  and the gate electrode  270   a.  The second DRAM cell comprises a second capacitor  140   b + 130   b + 110  and a second vertical transistor  250   b + 260   b + 270   b + 282   b + 290   b,  which are electrically coupled together. The second capacitor  140   b + 130   b + 110  comprises a capacitor dielectric layer  130   b,  a first capacitor electrode  140   b,  and a second capacitor electrode  110 . The second vertical transistor  250   b + 260   b + 270   b + 282   b + 290   b  comprises a first source/drain region  250   b,  a second source/drain region  290   b,  a channel region  282   b  (a portion of the P-well region  280   b  as shown in  FIG. 1M ), the gate dielectric region  260   b,  and the gate electrode  270   b.    
         [0028]    In one embodiment, with reference to  FIG. 1M , a width  234  of the cross-section of the gate electrode  270   a  is essentially the same as a width  122  of the cross-section of the capacitor electrode  140   a.  In an alternative embodiment, to increase the capacitance of the first capacitor  140   a + 130   a + 110 , the trench  120   a  (in  FIG. 1B ) can be widened, therefore, the width  122  of capacitor electrode  140   a  is greater than the width  234  of the cross-section of the gate electrode  270   a.    
         [0029]    It should be noted that if the buried strap  250   a  was formed on both side (left and right) of the TTO layer  240   a,  there would be a risk of the buried strap  250   a  shorting to the buried strap  250   b.  As a result, by forming the buried strap  250   a  only on one side of the TTO layer  240   a,  the two DRAM cells can be formed closer together, therefore, increasing the density of the final product. 
         [0030]      FIGS. 2A-2J  illustrate a second fabrication method for forming a second semiconductor structure  200 , in accordance with embodiments of the present invention. More specifically, in one embodiment, the second fabrication method starts out with the structure  200  in  FIG. 2A . In one embodiment, the structure  200  in  FIG. 2A  is similar to the structure  100  in  FIG. 1G . In another embodiment, dielectric layer  312  in  FIG. 2A  is substantially thicker than the dielectric layer  212  in  FIG. 1G . In one embodiment, the dielectric layer  312  in  FIG. 2A  has a thickness ranging from 50 to 1000 angstroms. Illustratively, the formation of the structure  200  in  FIG. 2A  is similar to the formation of the structure  100  in  FIG. 1G . It should be noted that similar regions of the bottom part of the structure  200  in  FIG. 2A , and the bottom part of the structure  100  in  FIG. 1G  (which are similar to the structure  100  in  FIG. 1D ) have the same reference numerals. It also should be noted that the similar remaining regions of the structure  200  in  FIG. 2A  and the structure  100  in  FIG. 1G  have the same reference numerals, except for the first digit. For instance, offset trenches  330   a  and  330   b  ( FIG. 2A ) and the offset trenches  230   a  and  230   b  ( FIG. 1G ) are respectively similar. 
         [0031]    Next, in one embodiment, exposed portions of the thin dielectric layer  312 , when present, are removed by an etching step which is essentially selective to the semiconductor substrate  310 , the polysilicon of the capacitor electrodes  140   a  and  140   b,  and the BOX layer  112 , resulting in four undercut spaces  332   a,    332   b,    332   c,  and  332   d  as shown in  FIG. 2B . In one embodiment, the removal of the exposed portions of the thin dielectric layer  312  can be achieved by an isotropic etch such as a wet etch or a plasma etch. 
         [0032]    Next, with reference to  FIG. 2C , in one embodiment, a conducting layer  334  is formed on the entire structure  200  (including in the trenches  330   a  and  330   b,  and the four undercut spaces  332   a,    332   b,    332   c,  and  332   d ). In one embodiment, the conducting layer  334  comprises polysilicon is formed by conventional CVD method. In one embodiment, a thin barrier layer (not shown) is formed on exposed silicon surfaces of the structure  200  in  FIG. 2B  prior to the deposition of the conducting layer  334  to prevent defect formation in the subsequent processes. The thin barrier layer, when present, has a thickness thin enough to allow dopants to diffuse through it and allow carriers (electrons and holes) to tunnel through it. More specifically, the thin barrier layer may comprises a thin silicon nitride, silicon carbide, or silicon oxide formed by thermal oxidation, thermal nitridation, chemical oxidation, chemical nitridation, CVD, or ALD process. Preferably, the thin barrier layer has a thickness ranging from about 5 to 25 angstroms, and more preferably from 5 to 15 angstroms, and most preferably from 7 to 10 angstroms. 
         [0033]    Next, in one embodiment, exposed portions of the conducting layer  334  are removed, resulting in four buried straps  334   a,    334   b,    334   c,  and  334   d,  as shown in  FIG. 2D . In one embodiment, the formation of the  FIG. 2D  is achieved by a timed isotropic etching step. 
         [0034]    Next, with reference to  FIG. 2E , in one embodiment, TTO (Trench Top Oxide) layers  340   a,    340   b,  and  340   c  are formed in the offset trenches  330   a,    330   b,  and the pad layer  320 , respectively. More specifically, the formation of the TTO layers  340   a,    340   b,    340   c  are similar to the formation of the TTO layers  240   a,    240   b,    240   c  in  FIG. 1H . 
         [0035]    Next, with reference to  FIG. 2F , in one embodiment, one-sided buried straps  350   a  and  350   b  are formed in the semiconductor substrate  310 . More specifically, the formation of the one-sided buried straps  350   a  and  350   b  are similar to the formation of the one-sided buried straps  250   a  and  250   b  in  FIG. 1I . Regions  334   b  and  334   d  are isolated from the capacitor electrodes  140   a  and  140   b  by TTO layers  340   a,    340   b,  and the BOX layer  112 . In one embodiment, the structure  200  in  FIG. 2E  is heated up at a temperature to form one-sided buried straps  350   a  and  350   b  (also called doped source/drain regions  350   a  and  350   b ) as shown in  FIG. 2F . During the heating step, the dopants in the doped polysilicon of the capacitor electrodes  140   a  and  140   b  diffuse into the semiconductor substrate  210 , resulting in the one-sided buried straps  350   a  and  350   b  in  FIG. 2F . Preferably, the annealing step is performed at a temperature ranging from 800 to 1150 Celsius degrees for a duration from 5 seconds to 120 minutes. Alternatively, the buried straps  350   a  and  350   b  can be formed by driving the dopants in the doped polysilicon of the capacitor electrodes  140   a  and  140   b  into the substrate  310  in the later thermal processes. 
         [0036]    Next, with reference to  FIG. 2G , in one embodiment, gate dielectric regions  360   a  and  360   b  are formed. More specifically, the formation of the gate dielectric regions  360   a  and  360   b  are similar to the formation of the gate dielectric regions  260   a  and  260   b  in  FIG. 1J . 
         [0037]    Next, with reference to  FIG. 2H , in one embodiment, gate electrodes  370   a  and  370   b  are formed. More specifically, the formation of the gate electrodes  370   a  and  370   b  are similar to the formation of the gate electrodes  270   a  and  270   b  in  FIG. 1K . 
         [0038]    Next, with reference to  FIG. 2I , in one embodiment, P-well regions  380   a  and  380   b  are formed. More specifically, the formation of the P-well regions  380   a  and  380   b  are similar to the formation of the P-well regions  280   a  and  280   b  in  FIG. 1L . 
         [0039]    Next, with reference to  FIG. 2J , in one embodiment, source/drain regions  390   a  and  390   b  are formed. More specifically, the formation of the source/drain regions  390   a  and  390   b  are similar to the formation of the source/drain regions  290   a  and  290   b  in  FIG. 1M . 
         [0040]    It should be noted that there are two DRAM cells in  FIG. 2J  and this two DRAM cells have the features of the two DRAM cells in  FIG. 1M . 
         [0041]    In the embodiments described above, the first and second transistors of the first and second DRAM cells, respectively, are vertical devices. Alternatively, the first and second transistors can be planar devices. 
         [0042]    While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.