Abstract:
In a multitrack motion analyzer in which video information representing a scene is recorded at a fast frame rate and played back at a slower frame rate, digital data timing and synchronization signals relating to each recorded frame is simultaneously recorded on a separate track as bipolar return to zero (BRZ) FM signals. A Non Return to Zero (NRZ) bit serial digital data signal and synchronous data clock signal are encoded as BRZ digital data signals and then frequency modulated so that the &#34;1&#34; bit, the &#34;0&#34; bit, and the &#34;return to zero&#34; signal levels of the BRZ data signal are converted to three frequencies. The three frequencies are integral multiples and synchronous to the data rate of the NRZ digital data signal so as to eliminate uncertainty between bit boundaries and allow packing more bits per unit time for a given carrier bandwidth. Additionally, accurate synchronization information is recorded and recovered by inserting a missing clock in the BRZ data stream. In a preferred embodiment in which the motion analyzer is operable at different frame rates, the FM frequencies representing the BRZ data signal are chosen to be a function of the ratio between the record frame rate and the playback frame rate which results in constant playback frequencies regardless of record rate.

Description:
BACKGROUND OF THE INVENTION 
     In general, this invention relates to the processing of digital data and more particularly, this invention relates to the conversion of NRZ digital data into BRZ digital data which is frequency modulated in a synchronous manner, for recording on magnetic tape. 
     Motion analysis of fast moving phenomena in slow motion entails the recording of a great number of images during an event at high speed, and then playing the images back slowly to analyze the movement which has occurred in step-by-step progression. Applications for motion analysis include malfunctions in high speed machinery, movements of an athlete, failure of safety equipment, shattering of an object and physical reactions to a tire hitting a pothole at high speed. One type of motion analyzer includes a video camera, a variable speed magnetic tape processor and a cathode ray tube (CRT) display monitor. The camera is capable of producing signals corresponding to selected frame rates of from 60 to about 2000 frames per second. The magnetic tape processing system is capable of recording at one tape speed and appropriately slowing down the tape during playback to a certain predetermined speed to down convert the camera signals regardless of the camera frame rate, to a nominal frame rate of 30 or 60 frames per second. The CRT display monitor receives the second frame rate playback signal from the magnetic tape processing system and displays the scene in question at an appropriate slow motion, depending upon the selected camera frame rate. 
     The display monitor of such a motion analyzer may be provided with a data frame border which displays various items of information recorded on the tape with each frame image. Such items of information include the time of day and date on which the frame was recorded, the elapsed time since the beginning of the recording, a user entered identification number for each test, recording rate selected, a frame counter from beginning of recording, and other information relative to the scene being recorded. In such a magnetic tape processing system, the video information is recorded as FM signals on a plurality of parallel linear tracks on magnetic tape. A multigap record head and multigap reproduce head are utilized for recording and reproducing the video signals from the tape. In order to minimize the number of magnetic heads required to record and reproduce signals from the magnetic tape, it is desirable that the information relating to each frame be recorded in the minimum number of tracks on the magnetic tape. Since the data relating to information concerning a given frame is conventionally in the format of a non return to zero (NRZ) digital data signal, if the NRZ digital data signals were recorded directly on tape, a separate data rate timing signal would also have to be recorded on a separate track on the tape in order to accurately reproduce the recorded data. This necessitates the use of two tracks on the tape for the data, and thus increases the number of recording and reproducing heads and the width of tape required for recording the information data signal. It is thus desirable that digital data information be recorded on the magnetic tape in a single track in order to reduce recording space on the tape, and the number of recording and reproducing magnetic heads needed in the magnetic tape processor. Similarly, it is also desirable that efficient data packing densities on the tape is effected and that accurate synchronization information be recorded on the data track so that the data may be recovered in synchronism with the related video information. 
     Since the speed at which the video data is recorded on tape is variable in relation to the frame rate of recording, but the video information is played back at the same tape speed irrespective of the recording speed, it is also desirable that the data recording technique take into account the varying tape speeds at which the video information is recorded so that there will be constant data signal frequencies played back, thus simplifying the playback circuitry. 
     Thus it is desirable that, in recording and reproducing digital data, the reproduced digital data signal duplicate the original digital data signal so that accurate information relating to a frame is displayed on the monitor. 
     SUMMARY OF THE INVENTION 
     According to the present invention, there is provided a technique for processing digital data of an NRZ format so that the digital data may be recorded at varying tape speeds and played back at the same tape speed without loss of bit information and with the accurate recovery of the digital data clock. The digital signal processing system of the present invention also permits the recording of digital data in a single track on magnetic tape, thus simplifying signal processing circuitry, minimizing the number of record and reproduce magnetic heads needed and the amount of magnetic tape space required for digital data recording. 
     According to an aspect of the invention, a bit serial digital data signal having an NRZ format and a data rate of f D  is encoded as a bipolar return to zero (BRZ) digital data signal in which a &#34;1&#34; bit is represented by a first signal level, a &#34;0&#34; bit is represented by a second signal level, and &#34;return to zero&#34; is represented by a third signal level. This format effectively encodes both the bit pattern and data clock in a single encoded signal. The BRZ digital data signal is converted into an FM signal in a synchronous manner for recording in a single track on magnetic tape. The first BRZ signal value representing a &#34;1&#34; bit is converted to an FM signal S 1  having a frequency n 1  f D  ; the second BRZ signal value representing a &#34;0&#34; bit is converted to an FM signal S 2  having a frequency n 2  f D , and the third &#34;BRZ&#34; signal value representing &#34;return to zero&#34; is converted to an FM signal S 3  having a frequency n 3  f D  where n 1 , n 2  and n 3  are different integers of one or greater. Thus, the BRZ FM signal representing a &#34;1&#34; bit has the form S 1  S 3  and the BRZ FM signal representing a &#34;0&#34; bit has the form S 2  S 3 . Because the FM signals S 1 , S 2 , and S 3  have frequencies which are integral multiples of the NRZ digital data rate, the BRZ FM data signal is recorded synchronously on magnetic tape. Upon playback, the transition between one FM signal to another FM signal is at the zero crossing so that ambiguities in the reproduced signal are minimized, accurate timing information and digital data recovery are effected and more packing of bits per unit time for a given carrier bandwidth is allowed. 
     According to another aspect of the invention, the frequencies at which the BRZ FM data signal are recorded on magnetic tape are varied as a function of the frame rate and tape speed during recording. All reproduced FM data signals have the same frequencies thus greatly simplifying the reproduction processing circuit design. Thus, separate processing circuits need not be provided for processing reproduced signals recorded at different tape speeds. 
     According to another aspect of the invention, accurate synchronization information is recorded and recovered by inserting a missing data clock in the BRZ data stream. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     In a detailed description of the preferred embodiments of the invention presented below, reference is made to the accompanying drawings in which like numerals refer to like elements. 
     FIG. 1 is functional block diagram of a motion analyzer in which the digital data signal processing system according to the present invention is used; 
     FIG. 2 is a functional block schematic diagram of a block readable area imager; 
     FIGS. 3a and 3b depict the format and content of a video signal produced by block readout of an area image sensor; 
     FIG. 4 shows the multitrack format of video information and digital data recorded longitudinally on magnetic tape; 
     FIG. 5 shows the relationship between various operational parameters of the motion analyzer shown in FIG. 1; 
     FIGS. 6a and 6b are a block diagram and truth table respectively of an embodiment of the present invention; 
     FIGS. 7a-7i are signal diagrams illustrating the operation of the present invention; 
     FIGS. 8a-8c are signal diagrams illustrating decoding of the BRZ FM data signal according to the present invention; 
     FIG. 9 is a block diagram of another embodiment of the present invention; 
     FIGS. 10a-10c show the relationship between various operational parameters of the embodiment shown in FIG. 9; 
     FIG. 11a is a schematic diagram of a data playback processing circuit according to the present invention; and 
     FIGS. 11b and 11c are a truth table and a signal diagram, respectively, which illustrate the operation of the circuit of FIG. 11a. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following description of the preferred embodiments of the digital data signal processing technique of the present invention, the present invention will be described as included in a motion analyzer. It will be understood, however, that the digital data signal processing technique of the present invention may be used in applications other than data recording on magnetic tape. For example, the technique may be used in recording on optical media, such as optical discs, recording on other magnetic media, such as magnetic discs, and transmission of digital data over a communications channel such as cable, satellite, direct broadcast, or the public telephone system. 
     The application in which the embodiments of the present invention will be described relates to a motion analyzer which records scene information at a high frame rate and plays back such information at a slower frame rate, thereby allowing slow motion analysis of a moving object. The imager frame rate used for recording is variable between 30 and 1,000 frames per second, depending upon the desired speed reduction while the display frame rate is constant at 30 frames per second. Accordingly, the apparent speed at which an object moves when viewed upon playback will be reduced by a factor equal to the ratio of the recording frame rate to the playback frame rate. The maximum speed reduction is therefore about 33 (i.e. 1,000 divided by 30). At this speed reduction, the exposure time for each frame is 1/1000 of a second which is short enough to provide high resolution images, with very little image smear of rapidly moving objects. 
     To accomplish such frame rate conversion, the variable speed magnetic tape processor records and reproduces an imager signal with a recording tape speed to reproduction tape speed ratio that equals the ratio of the imager frame rate to the display frame rate. The magnetic tape processor operates in cooperation with a divide-by-N circuit that selectively alters the frequency content of the video signal to be recorded, and in a manner to be described in detail below, both the value of (N) and the ratio of the recording to playback tape speed are controlled by the selected speed reduction. 
     Referring to FIG. 1, there is shown a functional block, schematic diagram showing a motion analyzer including an embodiment of the present invention. The motion analyzer 10 includes an imager 12 having a lens 14 which images a scene 16 onto a sensor 18. Imager 12 is controlled by timing and control circuit 20 which supplies suitable timing signals to imager 12 as a function of the operator selectable frame rate and speed reduction entered into by selector 22. The timing signals produced by circuit 20 are in accordance with the parameters tabulated in Columns 1 and 5 of FIG. 5. Thus, if a speed reduction of 8 (Col. 5) is selected, the imager will image scene 16 at a frame rate of 250 frames per second (Col. 1). 
     Sensor 18 is a &#34;block&#34; readable area image sensor. The basic concept of a block readout of a solid state area image sensor is disclosed in U.S. Pat. No. 4,322,752 in the name of James A. Bixby which is incorporated herein by reference. Specific types of block readable sensors are disclosed in U.S. Pat. No. 4,322,638, issued Mar. 30, 1982 in the names of T. H. Lee and R. P. Khosla; and U.S. Pat. No. 4,330,796 in the name of C. N. Anagnostopoulos et al, both of which are herein incorporated by reference. 
     Although the referenced patents provide detailed information, the basic concept of block readout is illustrated in FIGS. 2 and 3. FIG. 2 shows a block readable sensor 18 that includes an array of photosites (not shown individually) arranged in 192 rows and 240 columns. For purposes of readout, sensor 18 is formatted into 12 blocks of 16 photosite rows each. Although demarcation between blocks is indicated by dashed lines, it will be understood that no physical demarcation on the sensor itself is necessary. Each photosite is readable upon the application thereto of an enablement signal and an address signal. To begin readout, a driver 21 produces a BLOCK START signal that causes a block select shift register 23 to produce an enablement signal that enables (via block enable line B 1 ) all photosite rows within block 1, i.e. rows 1-16. In response to a COLUMN START signal from the driver 21 column address electronics in the form of a shift register 24 sequentially addresses the 240 photosite columns of the entire area image sensor 18. Because the photosite rows within blocks 2-12 (rows 17-192) are not enabled, only photosite rows 1-16 (block 1) are read out at this time. The remaining photosites in the not-enabled blocks continue to integrate charge in response to incident radiation from scene 16. After all columns have been addressed an END OF COLUMN signal sequences the block select shift register 23 to enable via block enable line B 2 , the block 2 photosite rows i.e. rows 17-32. Column-wise readout then proceeds as described above for the block 1 photosite rows. This process is repeated until all 12 blocks of photosite rows are read out at which time END OF FRAME signal from block select shift register 23 resets driver 21 for readout of the next frame. 
     Output select gates 26 and an interconnect matrix 28 of conductive bus lines perform the function of a block multiplexer that causes only signals from the 16 photosite rows within the block that is being read out to appear as an output signal. Reference is made to U.S. Pat. No. 4,322,752 referenced above for a more detailed discussion of the construction of output select gates 26 and matrix 28. 
     As a result of such read out, block information is produced in series and each block of information contains 16 row signals arranged in parallel. A result of such a readout technique is a reduction of the time required for sensor readout by a factor of 16 (i.e. the number of photosite rows in a block). 
     As shown in FIG. 3a, the video signal resulting from block readout of a single frame is comprised of serial train of block information wherein each block is comprised of 16 lines of video information that correspond to the 16 rows of photosites within each block. Each individual line of video information (see FIG. 3a) is an analog signal varying in level proportionate to the level of scene illuminance, and each line contains 240 picture elements (pixels) that correspond respectively to the 240 photosites in each row of photosites. Although, as shown in FIG. 3b, only 240 pixels represent the active video information of a line of video information, each line is in reality 256 pixel periods in length with 16 pixel periods representing a black level reference signal of six pixel periods and a white level reference signal of 10 pixel periods. 
     As shown in FIG. 3a, each channel of information includes the video information of every 16th line of image sensor 18. Thus, the first signal includes lines 1, 17, 33, 49, 65, 81, 97, 113, 129, 145, 161, and 177, and the last video information channel includes lines 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, and 192. 
     Referring again to FIG. 1, each of the 16 line signals that constitutes the analog video signal from imager 12 is frequency modulated in an FM modulator circuit 30 on a carrier having a black level frequency of 4.166 MHz and a white level frequency of 6.666 MHz. 
     The frequency modulated video signals undergo a divide-by-N process in a divide-by-N circuit 32. A suitable divide-by-N circuit which may be adapted to the apparatus shown in FIG. 1 is illustrated in FIG. 7 of commonly-assigned U.S. Pat. No. 4,496,995 issued Jan. 29, 1985, by J. H. Colles et al. The value of &#34;N&#34; is equal (to the nearest integer) to the maximum selectable speed reduction divided by the selected speed reduction. The relationship between &#34;N&#34; and various values of the speed reduction &#34;R&#34; is given in columns 5 and 6 of FIG. 5. It will be noted that the selected speed reduction has been used to determine both the frame rate at which sensor 18 is read out and the value of &#34;N&#34; in the divide-by-N circuit 32. While it may not be apparent how these two parameters (frame rate and &#34;N&#34;) relate to slow motion replay, the discussion which follows will show that the selection of these two parameters as described above in conjunction with the proper selection of a third parameter (recording tape speed) will produce the desired speed reduction of scene information upon playback. 
     A timing signal from timing and control circuit 20 is also applied to circuit 32 to be divided by the same factor &#34;N&#34; as the FM video signals. 
     The output of the divide-by-N circuit 32 is comprised of seventeen frequency divided frequency modulated signals. These signals are applied to a recording head driver circuit 34 that drives an 18 channel magnetic recording head 36. Channel 18 of the recording head is used for recording digital data according to the present invention. The digital data is produced by a data source 38 which produces digital data signals in non return to zero (NRZ) digital format which is processed by data record processing circuit 40. Source 38 also provides data clock signals which are in synchronism with the digital data signals to data recording processing circuit 40. The processed data signal is supplied to recording head driver 34 and then to the magnetic recording head for track 18 in multihead 36. 
     The 18 signals are recorded along 18 separate channels or tracks on magnetic tape 38. (FIG. 4) Magnetic tape 38 is provided in a cassette having supply reel 40, takeup reel 42, and tape guides 44 and 46. When the cassette is inserted into apparatus 10, tape 38 is pressed against recording head 36 and reproducing head 48 as well as external guides 50, 52, and 54. Tape is advanced from reel 40 to reel 42 by means of capstans 56 and 58 respectively driven by capstan motors 60 and 62, controlled by motor drive 64. 
     The speed at which magnetic tape 38 is advanced during recording is selected to be proportional to the selected speed reduction and frame rate of recording. The relationship of the record frame rate, record tape speed and speed reduction is tabulated in columns 1, 2, and 6, respectively of FIG. 5. For example, if a record frame rate of 250 frames per second (Column 1) is chosen with a speed reduction R of 8 (column 6), then the magnetic tape 38 would be advanced at a speed of 621/2 inches per second (Column 2). 
     Upon recording, the signals retain the block format (as shown in FIG. 4) in which a timing track 17 and a data track 18 are located between video tracks 1-8 and video tracks 9-16. 
     Having recorded information on magnetic tape 38 that corresponds to a scene including an object under study, a slow motion video display of such object is produced by playing back the recorded information at a constant tape speed of say, 71/2 inches per second irrespective of the originally selected recording tape speed. As a result, the ratio of the recording tape speed to the playback tape speed yields a tape speed reduction ratio that equals the selected speed reduction. Further, all reproduced signals have the same black to white level frequency spread, thereby enabling a fixed frequency demodulator to be used irrespective of the selected speed reduction. To understand why the above-described selection of recording frame rate, the factor &#34;N&#34;, recording tape speed and playback tape speed results in the desired speed reduction and signal form upon playback, reference is made to FIG. 5. It is apparent from inspection of FIG. 5 that &#34;N&#34; is equal to the maximum selected camera (record) frame rate divided by the selected camera frame rate. The effect of the divide-by-N circuit 32 is to reduce the black level to white level frequency spread by a factor &#34;N&#34;. But because the ratio of record tape speed to playback tape speed varies in inverse proportion to &#34;N&#34;, all signals produced upon playback have the same black level to white level frequency spread. Further, because the playback tape speed is always 71/2 inches per second, all video information is reproduced at a frame rate of 30 frames per second, thereby resulting in the desired speed reduction. 
     As a specific example, assume that a speed reduction of 8 is selected. Selecting a speed reduction of 8 will cause the imager sensor 18 to be read out a frame rate of 250 frames per second. The FM modulator 30 frequency modulates the video signal onto a 4.166 MHz carrier having a white level of 6.666 MHz. The divide-by-N circuit 32 with N=4 reduces the frequency of the video signal by a factor of 4, pk thereby resulting in a frequency modulated signal having a black level frequency equal to 1.042 MHz and a white level frequency of 1.666 MHz. This signal is recorded at a tape speed of 62.5 inches per second. Playing back this signal at a tape speed of 71/2 inches per second results in a recovered signal that has a black level frequency of 0.125 MHz and a white level frequency of 0.210 MHz. The desired speed reduction of 8 (more precisely 81/3) has thus been achieved. 
     Referring again to FIG. 1, the sixteen video signals produced by playback head 48 undergo signal processing in a preamplification and equalizatiaon circuit 64. The processed signals are then demodulated in an FM demodulator 66. After demodulation, the video signals (which are still in the block format shown in FIG. 3a) are converted to a line sequential video signal by a video processing and sync circuit 68. 
     A timing signal reproduced from timing track 17 is processed by circuit 64 and is applied to timing signal processing circuit 70 which extracts suitable timing and sync signals which are used in video processing and sync circuit 68 to produce a signal to be displayed on monitor 72. The displayed scene information consists of a slow motion replay of the originally recorded scene at the selected speed reduction. 
     Data from data track 18 is reproduced by reproducing head 48 and preamplified and equalized in circuit 64. The BRZ FM data signal is then processed by data playback processing circuit 74 to be shown in window areas such as 76, 78 in a data frame 80 surrounding the main image area 82 of monitor 72. 
     Video processing and sync circuit 68 may take the form of the format conversion circuit shown in FIG. 9 of the aforementioned commonly assigned U.S. Pat. No. 4,496,995. 
     According to the present invention, digital data relating to information pertinent to a frame of video being recorded is recorded on a data track at the same time as the video information. The data source 38 (FIG. 1) produces digital data in the non return to zero (NRZ) format at a bit frequency of f D . The NRZ digital data signal and data clock signal are supplied to data record processing circuit 40. 
     Samples of NRZ data signal and associated data clock signal are shown in FIGS. 7a and 7b. The signal waveform shown in FIG. 7a represents the digital number 101101 for the first six data periods P1-P6. In the NRZ format, the &#34;0&#34; bit is represented by a low signal value and the &#34;1&#34; bit is represented by a high signal value. If the NRZ digital data signal were to be recorded directly on magnetic tape, either special processing would be required or the data clock would also have to be recorded simultaneously in order to recover the digital data upon reproduction from the magnetic tape. This would require two recording heads, two reproducing heads, and two recording tracks on tape 38. Moreover, the recording of NRZ data directly on tape causes a DC signal which is not readily reproducible from the tape. It is thus advantageous to encode the NRZ data into a format which is not only easily recorded and reproduced, but which also encodes both the data and data clock into a single signal so that only one track need be used for recording on the magnetic tape, thus saving tape space and the number of recording and reproducing heads. 
     As shown in FIG. 7c, the NRZ data of FIG. 7a is encoded in bi-polar return to zero format (BRZ). In this format, a &#34;1&#34; bit is represented by a positive signal value, a &#34;0&#34; bit is represented by a negative signal value. In the BRZ format, the signal value representing the binary bit value only occupies one-half of the bit period with the second half of the bit period having a &#34;return to zero&#34; signal value. Thus, there is a &#34;return to zero&#34; signal value for each bit period and the data clock is therefore encoded into the BRZ data signal since there is a detectable signal transition for each bit period. As shown in FIG. 7c, &#34;1&#34; bit is represented by a first signal value V D1  during the first half of the bit period and &#34;return to zero&#34; by a third signal value V DS , during the second half of the bit period. A &#34;0&#34; bit is represented by a second signal value V DO  during the first half of the bit period and a &#34;return to zero&#34; by the third signal value during the second half of the bit period. 
     According to the present invention, the BRZ data signal is modulated as a synchronous frequency modulation (FM) signal to be recorded on data track 18 of tape 38 (see FIG. 4). The &#34;1&#34; bit of the BRZ signal is converted to an FM signal S 1  having a frequency n 1  f D  ; the &#34;0&#34; bit is represented by an FM signal S 2  having a frequency n 2  f D  and the &#34;return to zero&#34; value of the BRZ signal is represented by an FM signal S 3  having a frequency n 3  f D  where n 1 , n 2 , and n 3  are different integers including one. Thus, an NRZ digital data signal representing &#34;1&#34; bit has the form S 1 , S 3  and a NRZ digital data signal representing a &#34;0&#34; bit has the form S 2 , S 3 . Since the FM signals S 1 , S 2 , S 3 , have frequencies which are integral multiples of the data rate frequency f D , the signals can be synchronously recorded on tape 38. As will be described later, synchronous FM encoding of the BRZ data signal permits unambiguous decoding of the NRZ data signal upon reproduction from tape 38 and also permits accurate recovery of the data clock signal. 
     Referring now to FIGS. 6a and 6b, there is shown a data record processing circuit 40 (FIG. 1) illustrating the present invention. The data record processing circuit 40 is shown in a simplified form in which only a single speed is used for recording and playing back from tape 38. Processing circuit 40 includes a multiplexer 84 and an FM modulator 86. Multiplexer 84 has voltage input terminals 0123, data clock input A, NRZ data input B, and output Q. Voltage inputs 0 and 1 are connected together to a voltage source V DS , voltage input 2 is connected to a voltage source V DO  and voltage input 3 is connected to a voltage source V D1 . Data source 38 produces (1) an NRZ digital data signal which is applied to input B and (2) a synchronous data clock signal which is applied to input A. 
     Referring to the table in FIG. 6b, when the data clock signal applied to input A and the NRZ data signal applied to input B are both equal to a &#34;zero&#34;, or when the data clock signal is &#34;zero&#34; and the NRZ data signal is &#34;one&#34;, then the voltage V DS  will be passed to output Q representing &#34;return to zero&#34;. When the data clock signal is &#34;one&#34; and the NRZ data signal is &#34;zero&#34;, then the voltage V D0  will be passed to output Q (representing &#34;0&#34; bit) producing a negative pulse. When both inputs to A and B are &#34;one&#34;, the voltage V D1  (representing a &#34;1&#34; bit) will be passed to the Q output producing a positive pulse. Thus, multiplexer 84 converts the NRZ digital data signal and synchronous data clock signal into a BRZ digital data signal. The BRZ signal is supplied to FM modulator 86 which is a synchronous modulator and converts the BRZ data signal into a synchronous BRZ FM data signal. The V D0  voltage signal is modulated as an FM signal with a frequency f D  equal to an integral multiple of the data rate frequency of the NRZ data signal. The V DS  voltage is modulated as an FM signal having a frequency 2f D  and the V D1  voltage is modulated as an FM signal having a frequency 3f D . The three FM signals have frequencies which are integral multiples of the data frequency and are recorded on data track 18 of tape 38 in a synchronous manner. It will be appreciated that other integral multiples of the data frequency may also be used. 
     Referring to FIGS. 8a-8e, the advantage of synchronous FM modulation is illustrated. FIG. 8a shows a signal which varies from a voltage level V 0  to a voltage level V 1 . If the signal of FIG. 8a were to be modulated as an FM frequency which was asynchronous at the transition points from V 0  to V 1  or from V 1  to V 0 , the change in FM frequencies would take place at different signal levels and there would be an ambiguity in the region surrounding the transition point (e.g., the encircled regions of FIG. 8b). Thus, when the asynchronous FM signal is reproduced from the magnetic tape, there will be an undefined region of transition from one voltage level to another voltage level, thus causing an error in reproducing time between certain transitions (FIG. 8c). This result is undesirable and is obviated by the present invention in which the BRZ data signal is modulated as a synchronous FM signal. As shown in FIG. 8d, the change between FM signals of different frequencies occurs at a zero crossing point so that the recovered BRZ and NRZ signals will have sharply defined transition points (FIG. 8e) and accurate recovery of the original data bits and data clock. 
     Referring now to FIG. 9 and FIGS. 10a, 10b, and 10c, there is shown a preferred embodiment of the present invention. The data record processing circuit of FIG. 9 is adapted to be used with the motion analyzer of FIG. 1 so that variable tape speeds may be chosen by an operator and the frequencies of the BRZ FM signal to be recorded on tape will be changed accordingly. 
     The processing circuit of FIG. 9 includes a PROM 88, a latch 90, and a synchronous divide by M circuit 91 including programmable counters 92 and 94. Circuit 91 divides by a factor M a clock signal having a frequency f c  provided by timing and control circuit 20. When the operator has selected a frame rate/speed reduction by means of selector 22 (FIG. 1), the frame rate is encoded as a three bit word which is applied to inputs A 2 , A 3 , and A 4  of PROM 88. The data clock signal and the NRZ data signal from data source 38 are applied to input A 0  and A 1 , respectively of PROM 88. The BRZ FM signal is produced at the &#34;Q&#34; output of flip-flop 93 which is clocked synchronously with counters 92 and 94 by the clock signal f c  from timing and control circuit 20. 
     Referring to FIG. 10b, there is shown a table relating the frame rate to the three bit word applied to inputs A 2  -A 4  of PROM 88. Thus, if the operator choses a frame rate of 30 frames per second, the digital signal &#34;101&#34; will be applied to inputs A 2  -A 4  of PROM 88. If a frame rate of 250 frames per second is chosen by the operator, the digital signal &#34;010&#34; will be applied to inputs A 2  -A 4  . 
     FIG. 10c is a table of the values of signal levels applied to data clock input A 0  and NRZ data input A 1 , and the encoded BRZ signal level. Thus, when the inputs to A 0  and A 1  are either &#34;00&#34; or &#34;10&#34;, the BRZ encoded signal level is &#34;return to zero&#34; (RTZ). When the A 0  A 1  inputs are &#34;10&#34;, the BRZ encoding is -1 and when the inputs are &#34;11&#34;, the BRZ encoding is +1. PROM 88 combines the tables shown in FIGS. 10a and 10c to produce an eight bit output at output terminals Q 0  -Q 7 . According to the frame rate and BRZ signal encoding indicated, the eight bit output from PROM 88 is latched in latch 90 and loaded into counters 92 and 94 when a load signal is applied at load inputs L of counters 92 and 94, respectively. Divide by M circuit 91 divides a clock signal from timing and control circuit 20 by the indicated divisor M. The appropriate divisors are shown in the table of FIG. 10a. For example, when a frame rate 125 is selected by the operator, the clock signal of 18.432 MHz is divided by a divisor M equal to &#34;16&#34; for a BRZ encoding of &#34;-1&#34; representing a &#34;0&#34; bit, thus producing a BRZ FM signal of 1.152 MHz. Further, the &#34;RTZ&#34; encoded signal produces a divisor M of &#34;24&#34;, which results in a BRZ FM signal of 0.768 MHz, and a BRZ encoded signal &#34;+1&#34; representing a &#34;1&#34; bit produces a divisor M of &#34;48&#34; which results in a BRZ FM signal of 0.384 MHz. Thus, an NRZ bit of &#34;1&#34; is converted to a BRZ FM signal S 1  S 3 , wherein S 1  has a frequency of 0.384 MHz and S 3  has a frequency of 0.768 MHz and an NRZ &#34;0&#34; bit is converted to a BRZ FM signal S 2  S 3 , wherein S 2  has a frequency of 1.152 MHz and S 3  has a frequency of 0.768 MHz. 
     The BRZ FM signal is then recorded by means of recording heads 36 on data track 18 of tape 38. 
     Referring now to FIG. 11, there is shown a preferred embodiment of data playback processing circuit according to the present invention. The playback head 48 reproduces the BRZ FM data signal from tape 38. FM demodulator 66 demodulates the BRZ FM data signal into a BRZ data signal. From this BRZ data signal is recovered the original NRZ digital data signal such as represented in FIG. 7a and the synchronous data clock signal such as represented in FIG. 7b. To this end, the BRZ signal from demodulator 96 is applied to the &#34;-&#34; input of a comparator 98 and to the &#34;+&#34; of comparator 100. A voltage V 1  is applied to the &#34;+&#34; input of comparator 98 and a voltage V 0  is applied to the &#34;-&#34; input of comparator 100. The output of comparator 98 is a signal &#34;TRX ONE&#34; and the output of comparator 100 is a signal &#34;TRX ZERO&#34;. In effect, comparators 98 and 100 convert the three analog levels of the BRZ data signal from FM demodulator 96 into three logic levels encoded on two logic lines. This conversion is shown more clearly with respect to FIGS. 11b and 11c. FIG. 11c shows the relationship between the BRZ signal levels V D1 , V DS , and V D0  and the comparator reference voltages V 1  and V 0 . FIG. 11b is a table showing the relationship between the BRZ signal levels and the logic conditions of the two logic lines &#34;TRX ONE&#34; and &#34;TRX ZERO&#34;. Thus, for a BRZ signal level V D1  which represents a data bit &#34;1&#34;, there will be a logic level &#34;1&#34; on line &#34;TRX ONE&#34; and a logic &#34;1&#34; on line &#34;TRX ZERO&#34;, etc. 
     The &#34;TRX ONE&#34; signal (FIG. 7b) is supplied to one input of NAND gate 102 and to the D input of D flip-flop 104. The &#34;TRX ZERO&#34; signal (FIG. 7f) is applied to a second input of NAND gate 102. The output of NAND gate 102 is the reproduced original data clock signal (FIG. 7h) which is applied to the clock input of D flip-flop 104 and also to a retriggerable one-shot multivibrator 106. The output Q of D flip-flop 104 is the reproduced NRZ data signal. (FIG. 7g) 
     According to another aspect of the present invention, a special encoded synchronization bit is provided as a missing clock on the BRZ data signal. This missing clock is shown as a deleted clock signal during the period P M  of data clock signal FIG. 7b). The deleted clock signal is encoded in the BRZ data signal as a &#34;return to zero&#34; signal level V DS  (FIG. 7c). The &#34;TRX ONE&#34; and &#34;TRX ZERO&#34; signals are also applied to two inputs of AND gate 108, a third input of which is connected to one shot multivibrator 106, which is retriggered continuously by the reproduced data clock signal since multivibrator 106 has a period greater than the data clock period. However, a missed clock will allow the one shot multivibrator to change state and to trigger AND gate 108 to produce a FRAME SYNC pulse (FIG. 7i) which indicates the start of a block or frame of data. It will be noted that at the time of the missing clock pulse, the BRZ data is in the &#34;return to zero&#34; state so that the &#34;TRX ONE&#34; and &#34;TRX ZERO&#34; signals are both zero. 
     Although the invention has been described in detail with particular reference to preferred embodiments thereof, it will be understood that variations and modifications can be effected within the spirit and scope of the invention as described hereinabove and as defined in the appended claims.