Abstract:
Among other things, devices for use in fluorescence or luminescence lifetime imaging are described. The devices include integrated complementary metal-oxide semiconductor (CMOS) chips that include an imaging region and a time-to-digital converter. The imaging region includes a photodetector for receiving optical signals. The time-to-digital converter provides digital phase output based on the received optical signals.

Description:
TECHNICAL FIELD 
       [0001]    This disclosure relates to imaging fluorescence or luminescence lifetime, in particular, using a monolithic chip that integrates an image sensor and provides direct digital phase readout. 
       BACKGROUND 
       [0002]    The lifetime of excited fluorescent or luminescent dyes, or of an intrinsic autofluorescent response to an excitation light, is highly sensitive and selective to chemical and/or biological properties of the surrounding environment of the dyes or autofluorescent material in the sample. Images of the fluorescence/luminescence lifetime can be used for understanding these chemical or biological properties. Time-correlated single-photon counting (TCSPC) or frequency-domain phase measurement can be used for obtaining the images. In particular, TCSPC is a histogram-based method that uses ultra-fast laser pulse with sub-nanosecond resolution for fluorescence/luminescence excitation and obtains the fluorescent lifetime image through image reconstruction. The frequency-domain phase measurement uses a laser diode or a low-power LED as an excitation source. 
       SUMMARY 
       [0003]    This disclosure features fluorescence and/or luminescence lifetime imaging systems fully integrated in a monolithic chip, e.g., a complementary metal-oxide semiconductor (CMOS) chip containing integrated circuits, that provides on-chip digital phase output (or readout), as well as methods of making and using these systems. The imaging systems can be used in time-resolved lifetime imaging applications, such as oxygen sensing for tumor detection or skin cancer scanning. In particular, the imaging systems implement frequency-domain phase-shift measurements and convert the frequency-domain phase shift into a time-domain delay via a zero-crossing detection method. The converted time-delay is quantized directly on the chip using a time-to-digital converter (TDC) configured to have a high temporal precision and a wide dynamic range. The chips are configured to allow for low-frequency signal modulation and low power consumption, and to provide a high resolution for the phase measurement. 
         [0004]    In certain implementations, the phase readout from the chip can have a sensitivity better than 0.01 degrees at a modulation frequency of 1.2 KHz and 0.1 degrees at a modulation frequency of 1 MHz. In certain implementations, the circuits for zero crossing detection and for the TDC can have a temporal resolution of lower than 110 ps with a dynamic range greater than 400 μsec. The power consumption of the entire chips can be less than 1.2 mW. The chips provide fluorescence lifetime imaging with high temporal and spatial resolution, at a low cost, using a low power, and within a large temporal dynamic range. 
         [0005]    In one aspect, the disclosure features devices for use in fluorescence or luminescence lifetime imaging. The devices can include integrated complementary metal-oxide semiconductor (CMOS) chips that include an imaging region and a time-to-digital converter. The imaging region includes a photodetector for receiving optical signals. The time-to-digital converter provides digital phase output based on the received optical signals. 
         [0006]    In another aspect, the disclosure features microscopes that include a lens and an integrated complementary metal-oxide semiconductor (CMOS) chip. The CMOS chip includes an imaging region and a time-to-digital converter. The imaging region includes a photodetector for receiving optical signals that pass the lens. The time-to-digital converter provides digital phase output based on the received optical signals. In some implementations, the microscopes are oxygen sensing microscopes and the optical signals are received from a fluorescent or luminescent marker or autofluorescence in a tissue, e.g., in vivo. 
         [0007]    In another aspect, the disclosure features scanner devices for use in detecting skin cancer. The scanners include an integrated complementary metal-oxide semiconductor (CMOS) chip that includes an imaging region and a time-to-digital converter. The imaging region includes a photodetector for receiving optical signals. The time-to-digital converter provides digital phase output based on the received optical signals. The scanners also include a display for displaying the digital phase output from the integrated CMIS chip. In some implementations, the scanners are designed to be portable, e.g., sized and configured to be hand-held. 
         [0008]    The devices, microscopes, and scanner devices can include one or more of the following features or embodiments. The imaging region can include an array of photodetectors. The photodetectors can be photodiodes. The photodiodes can include a P+ layer buried in an N-well 0.5. The integrated CMOS chip can also include a phase extraction circuit that extracts a phase shift from the received optical signals and delivers the extracted phase shift to the time-to-digital converter. The time-to-digital converter can be configured to provide a localized digital phase output. The time-to-digital converter can include delay cells and an encoder that scans the delay cells to locate the localized digital phase output. The CMOS chips can have a surface area of about 4 mm by 4 mm. 
         [0009]    In another aspect, the disclosure features methods for imaging lifetime of fluorescence or luminescence. The methods include receiving optical signals by an imaging region of an integrated complementary metal-oxide semiconductor (CMOS) chip and processing the received optical signals to provide a digital phase output from the integrated CMOS chip. The imaging region can include a photodetector. The received optical signals are processed by converting a time delay to the digital phase output by a time-to-digital converter on the CMOS chip. 
         [0010]    The methods for imaging lifetime of fluorescence or luminescence can also include one or more of the following features. The digital phase output can be used for sensing oxygen. The digital phase output can be used for detecting skin cancer. The optical signals can include an excitation signal and a fluorescence or luminescence emission signal, and the received optical signals can be processed by extracting a phase difference between the excitation signal and the emission signal. The received optical signal can be processed by converting the extracted phase difference within a phase domain into a time delay. 
         [0011]    Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, suitable methods and materials are described below. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety. In case of conflict, the present specification, including definitions, will control. 
         [0012]    In addition, the materials, methods, and examples are illustrative only and not intended to be limiting. 
         [0013]    Other features and advantages of the invention will be apparent from the following detailed description, and from the claims. 
     
    
     
       DESCRIPTION OF DRAWINGS 
         [0014]      FIG. 1A  is a schematic top view of a chip containing a fluorescence or luminescence lifetime imaging system. 
           [0015]      FIG. 1B  is a block diagram of a fluorescence or luminescence lifetime imaging system. 
           [0016]    FIG. IC is a block diagram of a system using a chip containing a fluorescence or luminescence lifetime imaging system. 
           [0017]      FIG. 2A  is a plot of sinusoidal excitation and resultant sinusoidal emission due to fluorescence/luminescence lifetime. 
           [0018]      FIG. 2B  is a plot of time-domain delay converted from a frequency-domain phase shift. 
           [0019]      FIG. 3A  is a schematic cross-sectional view of a pixel on a chip containing a fluorescence lifetime imaging system. 
           [0020]      FIG. 3B  is a schematic top view of a pixel on a chip containing a fluorescence or luminescence lifetime imaging system. 
           [0021]      FIG. 4  is a schematic diagram of row-level phase extraction circuit. 
           [0022]      FIG. 4A  is a schematic diagram of a comparator circuit. 
           [0023]      FIG. 5A  is a block diagram of a TDC. 
           [0024]      FIG. 5B  is a diagram of time interpolation in a TDC. 
           [0025]      FIG. 5C  is a schematic diagram of voltage-controlled delay-line (VCDL)-based fine resolution TDC circuit. 
           [0026]      FIG. 6  is a schematic diagram of a system setup for using and/or testing a chip containing a fluorescence lifetime imaging system. 
           [0027]      FIGS. 7A and 7B  are plots of measured linearity of digital phase readout. 
           [0028]      FIGS. 8A and 8B  are plots of measured linearity of fine TDC. 
           [0029]    FIGS.  9 (A)-(D) are phase images. 
           [0030]      FIGS. 10 and 11  are schematic diagrams of microscopes including a chip containing a fluorescence or luminescence lifetime imaging system for various uses. 
           [0031]      FIG. 12A  is a schematic top view of a portable skin cancer scanner including a chip containing a fluorescence lifetime imaging system. 
           [0032]      FIG. 12B  is a schematic exploded view of a portable skin cancer scanner including a chip containing a fluorescence lifetime imaging system. 
       
    
    
     DETAILED DESCRIPTION 
     Fluorescence and/or Luminescence Lifetime Imaging Systems 
       [0033]    Referring to  FIGS. 1A and 1B , a fluorescence and/or luminescence lifetime imaging system  100  on a chip  108  includes an imaging region  102  that captures images, e.g., detects photons received from target materials or environments that are marked with fluorescence, and outputs digital phases with a high sensitivity from a TDC  106 . The output digital phases contain information regarding the biological or chemical properties of the target materials or environments. 
         [0034]    As an example, the use of the chip  108  is shown in FIG. IC. The chip  108  is placed in the vicinity of or in contact with a fluorescently marked target material or one exhibiting autofluorescence in an environment, e.g., a sample or a body part. An off-chip light source  116 , e.g., an LED or laser light source, projects light onto the sample  118  and excites fluorescence  120  contained or inherent in the sample  118 . Alternatively, an on-chip light source  116 ′ (in dashed lines) can be used for exciting the fluorescence  120 . The imaging region  102  of the chip  108  receives measurement signals, e.g., photons, from the excited fluorescence  120  and reference signals, e.g., photons or other signals related to the light source  116  (or source  116 ′). By processing a phase shift detected for the two different types of signals, e.g., one signal being the excitation signal and the other signal being the emitted fluorescence, the chip  108  outputs phases for the fluorescence lifetime imaging. In some implementations, the chip  108  is incorporated into a device (see, e.g.,  FIGS. 10 ,  11 , and  12 A- 12 B), e.g., a hand-held device, and the phase is output on a screen of the device. 
         [0035]    Referring again to  FIGS. 1A and 1B , in some implementations the imaging system  100  implements frequency-domain phase measurements. In particular, the phase shift between the reference signal and the excited fluorescence, luminescence or autofluorescence signal is extracted using a phase extraction circuitry, e.g., row-level phase extraction circuit  104 , on the chip  108 . The phase shift measured and extracted in frequency-domain is converted into time-domain delay using a high-gain trans-impedance amplifier (TIA) cascaded by a high-speed comparator. The time delay is digitized for phase image reconstruction using the TDC  106 . The frequency-domain phase measurements use a low-power light-emitting diode (LED) as an excitation source and are cost-effective and power efficient. 
         [0036]    Referring to  FIG. 2A , the frequency-domain phase measurement extracts an excitation signal  200  (in dashed lines) and an excited fluorescence signal  202  (in solid lines). The excitation signal  200  has a modulated intensity that can be expressed as: 
         [0000]        I=I   0 ·{1+ k   M  sin(ω t )}  (1)
 
         [0000]    where I is the optical intensity, k M  is modulation index, and ω is modulation frequency. The excited fluorescence signal  202  exhibits a phase-shift α from I: 
         [0000]        F=F   0 ·{1+ k   F  sin(ω t −α)}  (2)
 
         [0000]    where F is the optical intensity, a is a function of fluorescence lifetime τ: α=tan −1 (ωτ). When a zero-crossing detection on both the excitation signal  200  and the excited fluorescence signal  202  with respect to their common-mode values I 0  and F 0 , the sine waves are converted to digital square pulses  204  as shown in  FIG. 2B . The square pulses  204  have rising edges  206 ,  208  and falling edges  210 ,  211  triggered by the zero-crossing points. Based on the square pulses  204 , the phase-shift α can be represented in the form of a time-domain delay Δt=α/ω, which can be digitally quantized using a TDC, e.g., the TDC  106  on the chip  108  of  FIG. 1A . The chip  108  can provide a phase readout with a high sensitivity and a high dynamic range. 
         [0037]    The phase-shift between intensity-modulated excitation light and the emitted fluorescence contains fluorescence lifetime information, which can be extracted by analog signal processing, e.g., using lock-in amplifiers. The integration of the frequency-domain phase measurements on the chip  108  provides a low-cost, low-power, and compact platform for fluorescence lifetime imaging, e.g., in field experiments or environment monitoring. 
         [0038]    Referring again to  FIGS. 1A and 1B , the fluorescence lifetime imaging system  100  is entirely integrated on the monolithic chip  108  having small dimensions. In some implementations, the size can be, e.g., 4 mm by 4 mm. For example, the chip  108  can be a 65 nm CMOS chip having high speed transistors having a high transit frequency f T  property. The components of the COMS chip are integrated at a large scale system level. The direct phase output from the chip  108  has a high sensitivity and the chip  108  operates within a large dynamic range. Other than the imaging region  102 , the row-level phase extraction circuit  104  (or “row level phase readout”), and the TDC  106  shown in  FIG. 1A , the chip  108  includes other components (discussed below) that enable the chip  108  to provide direct phase readout based on signals received at the imaging region  102 . The chip  108  does not require any off-chip signal converters to further process signals to obtain digital phase outputs. Although a circuit design for each component is described below, other circuit designs can be implemented to provide the functions of the chip  108 . 
         [0039]    In some implementations, the imaging region  102  can include arrays of photodetectors, e.g., photodiodes, phototransistors, or other types of photodetectors, built within the chip  108 . Although the figures show a 32×32 photodiode array, other array configurations can be used. Each photodiode is identifiable by an address within the array and expressed as a vector (x, y). Each photodiode is connected to the xth column decoder of column decoders  112  and the yth row decoder of row decoders  114 . Detected signals from each photodiode can be independently decoded by the corresponding column decoder and row decoder. 
         [0040]    The photon-generated current from each row of photodiodes, I ph1 ˜I ph32 , are processed by the row-level phase extraction circuit  104 . The circuit  104  performs a current-to-voltage conversion and uses zero-crossing detection to convert extracted phase shifts into time-domain delays. The time delay for each row of photodiodes, Δt i  (i=1˜32) is digitally multiplexed into a time interpolator  110  that divides Δt i  into fine intervals T 1  and T 2 , and a coarse interval T 12 . The intervals T 1  and T 2  are multiplexed into the TDC  106  for fine conversion, and T 12  is delivered to an off-chip digital counter (not shown) for coarse conversion. In some implementations, the TDC  106  is a voltage-controlled delay-line (VCDL) based TDC. The digital phase output is obtained by reconstructing combined fine outputs of T 1  and T 2  and a coarse output of T 12 . The configurations of the photodiode array, the row-level phase extraction circuit  104 , the time interpolator, and the RDC  106  allow the lifetime imaging to be performed within an extended dynamic range while maintaining a high temporal resolution. 
       Pixels of the Imaging Region 
       [0041]    The photodiode array, e.g., a  32  by  32  array, in the imaging region  102  is built by repeating a unit that contains one photodiode and other associated components. We call such a unit a “pixel” of the chip  108 . Referring to  FIGS. 3A and 3B , a pixel  300  can have a passive pixel architecture for high fill factor, and can include a photodiode  302  that is constructed by a P+ layer buried in an N-well  306  and a P-substrate  308 . Such a construction can reduce current leakage. In some implementations, a highly resistive BF-Moat layer  310  can be disposed around the photodiode  302  to isolate noise from the photodiode  302 . The BF-Moat layer  302  can also reduce or prevent crosstalk between adjacent pixels (only one pixel shown). In some implementations, the pixel  300  does not include any BF-Moat layers. Other types of pixels, such as those having an active pixel sensor architecture, can be used in the imaging region  102 . The photodiode can have other structures, such as P+/N-well, N+/P-SUB, NWELL/PSUB or can be a phototransistor. In one embodiment, the pixel  300  can have a pitch size of about 50 μm. The pixel size should be designed to be relatively large pixel size, e.g., sufficiently large, to provide a high fill factor, e.g., about 37%. The large pixel size also provides a high optical sensitivity for imaging (photon detection). The dimensions shown in  FIG. 3B  are just examples of one specific embodiment, and can be varied. 
       Row-Level Phase Extraction Circuits 
       [0042]    Referring to  FIG. 4 , a simplified architecture of one implementation of a row-level phase extraction circuit  400  on the chip  108  is shown. The photon-generated current I ph  from each row of photodiodes is amplified and converted to a voltage using a TIA  412 . A threshold for zero-crossing detection for compensating background illumination I ref  is generated using another TIA  414 . A high-speed comparator  416  adjusts the output of TIA  412 , a voltage from the photon-generated current I ph , based on the output from TIA  414 . The phase-shift to be input into the TDC (e.g., the TDC  106  of  FIG. 1A ) is expressed as time-delay between the excitation signal (e.g., from an external function generator associated with the excitation light) and a row-level zero-crossing output. 
         [0043]    The photocurrents I ph  and I ref  have small magnitudes, e.g., of nA. The TIA  412  includes a T-Network feedback configuration  418  amplify the photocurrent I ph . The TIA 414  can have a similar configuration. In the T-Network feedback configuration  418  as shown, there are three resistors R 1 , R 2  and R 3 , where the gain can be set very high with smaller resistors compared to single resistor feedback-based TIA for a similar resistor layout area. In some implementations, a resistive feedback TIA or regulated gate cascade TIA is used instead of the T-network TIA. Other types of TIAs can also be used. 
         [0044]    A comparator  416  can include a sequence of cascaded low-gain and high bandwidth pre-amp stages similar to conventional limiting amplifiers to precisely convert the phase shift to a time delay at a high resolution, e.g., a sub-nanosecond resolution. The zero-crossing output has fast rising and falling edges and the comparator  416  introduces a minimum propagation delay to the output. In this implementation, the TIA  412  has a DC gain of 160 dB and 97 pARMS input referred noise integrated over 1 MHz bandwidth. The equivalent gain of the T-Network is expressed in equation (3). 
         [0000]        V   OUT   /I   ph   =R   1   +R   2 +( R   1   ·R   2 )/ R   3 =100 MΩ  (3)
 
         [0045]    Referring to  FIG. 4A , the comparator  416  as shown includes an input-stage  424 , four gain-stages  426   a - 426   d , and inverter-based output buffer  428 . The gain-stages include sub-circuit blocks  420 ,  422 . An R-C feedback network  430  is implemented to cancel offset and improve stability of the comparator  416 . The comparator  416  has a 25 dB gain when the input frequency is about 1 GHz. With an input signal of 100 mV pp , the comparator  416  in this implementation has a propagation delay of 1 ns and a rise/fall time of 200 ps. Alternatively, other comparator architectures, such as single stage amplifier or latch based design, can be used. 
       Time-to-Digital Converter (TDC) 
       [0046]    The TDC, e.g., the TDC  106  of  FIG. 1A , can be a time interpolated TDC including a VCDL for fine conversion and a digital counter for coarse conversion. Referring to  FIGS. 5A and 5B , a TDC  500  includes a time interpolator  502  that takes in Start and Stop signals and divides input time delay Δt from the phase extraction circuit  400  of  FIG. 4  into T 1 , T 2 , and T 12  based on an input clock counter  signal. Although the Clock counter  signal shown in the figure has a frequency of 40 MHz, the clock counter  signal can have other frequencies. The coarse output T 12  spans over multiple clock counter  cycles and is measured by an off-chip 14-bit digital counter  504 . In one implementation, a coarse output having a dynamic range of about 0.4 ms and a temporal resolution of about 25 ns is generated based on the coarse output T 12 . 
         [0047]    A precise measurement of T 1  and T 2  is carried out using, e.g., an 8-bit VCDL  506  having a sequence of delay cells, e.g.,  256  delay cells. Each delay cell is implemented using voltage-controlled delay buffer with digital flip-flop (DFF). An on-chip Delay-Locked-Loop (DLL)  508  regulates a bias voltage V b  of the VCDL  506  to compensate for process variation and performance drift due to temperature and power supply variation. A fine output from the precise measurement of T 1  and T 2  is produced by a binary encoder  507 . 
         [0048]    Alternatively, a decoding circuit  520  as shown in  FIG. 5C  can be used to produce output from the precise measurement of T 1  and T 2 . One particular embodiment is now described. The decoding circuit  520  provides an area-efficient and high-throughput readout of the fine TDC. A delay line in the decoding circuit  520  is grouped into 8 banks  510   a - 510   h , each containing, e.g.,  32  delay cells  512 . The decoding circuit  520  decodes in a two-step process. First, after a Stop signal latches the location of a Start signal in the delay line, an 8-to-3 encoder  514  outputs three most significant bits OUT 8 ˜OUT 6  corresponding to one of the 8 banks  510   a - 510   h  that holds the Start signal. A 3-to-8 decoder  516  enables a scanning process of the corresponding bank that holds the Start signal to further locate the Start signal within the bank. In particular, a 5-bit counter connected to a 5-to-32 decoder  518  sequentially scans through the delay cells  512  in the bank that holds the Start signal. Then, when the Start signal location is detected, the counter outputs are latched as least significant bits OUT 5 ˜OUT 1 . This localized two-step readout scheme uses at most 32 counter clock cycles for a complete binary encoding of thermometer code generated by the delay line. Thus, the need for complicated routings between individual delay cells  512  in the delay line to a read-only memory (ROM) or counter based decoder circuitry is eliminated. Although 8 banks of 32 delay cells can be used to provide an 8-bit TDC word-length, an arbitrary M-banks of N-delay cells for a word-length of log 2 (M*N) bits, where M and N are integers, can be used. 
       Examples of System Setup 
       [0049]    As previously described, the monolithic chip  108  having features described in  FIGS. 1A-1B ,  2 A- 3 B,  3 A- 3 B,  4 ,  4 A, and  5 A- 5 C can be used in a setup schematically shown in  FIG. 1C  for fluorescence lifetime imaging.  FIG. 6  shows a more detailed device setup  600  for using and/or testing a chip  602  (the same as or similar to the chip  108 ). The chip  602  images and outputs digital phases based on two input signals, one excitation signal from a two-channel arbitrary function generator  603 , and one simulated fluorescence signal from a red LED  604 . In addition to generating the excitation signal having a constant phase α 0 , the function generator also generates a test signal having the same frequency as the excitation signal. The test signal has a modulated phase α(t) and drives a red LED to generate an intensity-modulated optical signal that simulates a fluorescent signal in a sample. In this implementation, the optical signal from the red LED is filtered using 630 nm bandpass filter  606  having a passband of less than 10 nm and is focused using a microscopic objective  607 . A dichroic beam splitter  608  guides the focused, filtered light through a correction lens  610  onto the chip  602 . The fluorescence lifetime imaging is digitally controlled by a field-programmable gate array (FPGA) such as a Cyclone II FPGA chip (Altera, San Jose, Calif.) and TDC outputs from the chip  602  can be acquired using data acquisition and processing systems, such as LabVIEW (National Instruments, Austin, Tx), for post-signal processing and phase image reconstruction. 
         [0050]    In some implementations, the monolithic chip for fluorescence lifetime imaging as described in the previous figures can have the following specification: 
         [0000]    
       
         
               
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 Basic substrate 
                 65 nm CMOS 
               
               
                   
                 Chip surface area 
                 4 mm × 4 mm 
               
               
                   
                 Power supply 
                 1 mA at 1.2 V V DD   
               
               
                   
                 Photodiode array 
                 32 × 32 
               
               
                   
                 Pixel pitch/fill factor 
                 50 μm/67% 
               
               
                   
                 Row phase readout 
                 0.5LSB/0.58LSB, (LSB = 0.01 degrees) 
               
               
                   
                 (DNL/INL) 
               
               
                   
                 Fine TDC (DNL/INL) 
                 0.49LSB/1.65LSB (LSB = 110 ps) 
               
               
                   
                 TDC dynamic range 
                 110 ps~400 μs 
               
               
                   
                   
               
             
          
         
       
     
       Applications and Uses 
       [0051]    The chips for fluorescence and luminescence lifetime imaging have various applications in chemical, biological, and medical fields. Referring to  FIG. 10 , a chip  1010  can be integrated into an inverted microscope  1000  for use as an oxygen sensing microscope. Such a microscope can be used in in vivo imaging of hypoxia in tissues. In addition to the chip  1010 , the microscope  1000  also includes an arbitrary function generator  1080 , optics, such as lenses  1020 ,  1050 , mirror  1030 , filter  1070 , and microscopic object  1040 . These components have the same or similar features as those discussed with respect to  FIG. 6 . Tissues or cells tagged with fluorescent or luminescent markers can be placed within view of the microscope objective  1040 . A frequency-modulated LED or laser source is used as an excitation light. The emitted light from fluorescent markers passes through the optics in the microscope and impinges on the chip  1010 . The chip images the lifetime of the fluorescent marker and generates an intensity profile. When an oxygen sensing fluorophore, such as ruthenium complex, is used, the imaged fluorescence lifetime provides information on possible oxygenation and hypoxia conditions of the tissues or cells. 
         [0052]    Referring to  FIG. 11 , an inverted microscope  1000  of  FIG. 10  can also be used for skin cancer detection, in vitro or in vivo. The target skin tissues and cells are marked with fluorescent markers sensitive to tumor. Changes in fluorescence lifetime caused by the tumor can be imaged by the chip  1010  in the microscope  1000 . The phase images may show demarcation of the tissue having the tumor. By comparing the phase images with images of healthy tissues, tumors can be readily detected. 
         [0053]    In some implementations, the skin cancer scanner can be a portable device, e.g., a hand-held device. An example of a portable device  1200  is shown in  FIG. 12A . The dimensions shown are for one specific example, but can vary. The device  1200  can be in the form of a tablet PC integrated with fluorescence lifetime imaging chip. Referring also to  FIG. 12B , the portable device  1200  includes a high resolution liquid crystal display (LCD)  1210  to display the acquired fluorescence lifetime images, a digital signal processor (DSP) board  1220  for pattern recognition and system level control, a digital phase imager  1230 , e.g., the chip  108 , configured to perform zero-crossing detection algorithm to extract the fluorescence lifetime from biomedical sensors (e.g., fluorescence), an optical filter  1240  to remove the background illumination, and a light emitting diode (LED) array  1250  as an excitation source. 
         [0054]    In use, the LED array  1250  excites the fluorescent biomedical sensor that is applied on a target skin area  1260 . The emitted fluorescence is filtered and imaged by the digital phase imager  1230 . In some implementations, the scanner  1200  has a small size and includes fewer pieces of optics than the microscope  1000  of  FIGS. 10 and 11 . The scanner  1200  can be placed close to the skin area  1260  to conduct contact imaging without using many pieces of optics in the scanner. Alternatively, a micro-lens at the pixel level can be incorporated into the small scanner  1200 . A skin cancer scanner without the present chips for fluorescence and luminescence lifetime imaging is also discussed by R. Cubeddu et al., J. Phys. D: Appl. Phys., vol. 35, pp. R61-R76 (2002), the entire content of which is incorporated herein by reference. 
         [0055]    In some implementations, optical signals can be obtained in vivo using, e.g., a camera delivered by a catheter or other devices. The optical signals can be delivered to a chip, e.g., the chip  108  or the chip  1010  through optical fibers. In this implementation, the optics and/or microscope objects of the microscope  1000  may be unnecessary. 
       EXAMPLES 
       [0056]    The following examples are not to be viewed as limiting the inventions, which are described in the claims. 
       Example 1 
       [0057]    Using the setup  600  of  FIG. 6 , the row-level phase extraction circuit of the imaging system was evaluated via a code density test. To cover the entire temporal dynamic range while maintaining a reasonable phase resolution, the frequency of the excitation signal and the test signal was selected to be 1.2 KHz. A linear phase-shift sweep based on the excitation signal was performed from 0 to 179 degrees at 0.01 degrees per step, producing an equivalent time-domain sweeping range of more than 414 μs with approximately 23 ns per step. 
         [0058]      FIGS. 7A and 7B  show linearity performance of the photodiode, the TIA, the comparator, and the TDC on the chip. The measured differential nonlinearity (DNL) was 0.5 LSB and the measured integral nonlinearity (INL) was 0.58 LSB. The TDC was characterized using off-chip programmable delay line with dynamic range from 10 ps to 50 ns. Results of the code density test were plotted in  FIGS. 8A and 8B , showing a DNL of 0.49 LSB and an INL of 1.65 LSB. 
       Example 2 
       [0059]    A phase image was reconstructed to demonstrate the phase readout scheme of a chip containing a fluorescence imaging system. A time-resolved fluorescence lifetime image from an oxygen sensor was used as an example phase image ( FIG. 9(A) ) and was used for generating a 32×32 array of 8-bit phase shift (0 to 100 degrees) pattern according to the image intensity. A one-to-one mapping between the phase shift pattern generated from the example phase image and output phase from the setup  600  of  FIG. 6  was performed. Using the setup  600 , phase-shift outputs were obtained by scanning the entire 32×32 pixel array. 8-bit gray-scale phase images were reconstructed based on the phase-shift outputs.  FIG. 9(A)  shows the original example phase image representing fluorescence lifetime from 0 to 280 μs. FIGS.  9 (B)-(D) show reconstructed phase images by modulating both the excitation signal and the test signal at frequencies of 1 KHz, 50 KHz, and 1 MHz, respectively. The measurable lifetime covered a wide temporal range, e.g., 0-280 ns in  FIG. 9(B)  and 0-280 μs in  FIG. 9(D) . 
       OTHER EMBODIMENTS 
       [0060]    It is to be understood that while the invention has been described in conjunction with the detailed description thereof, the foregoing description is intended to illustrate and not limit the scope of the invention, which is defined by the scope of the appended claims. Other aspects, advantages, and modifications are within the scope of the following claims.