Abstract:
A circuit that provides the root-mean-square (RMS) value of an input signal and that detects and independently recovers from an output fault condition is provided. The circuit includes reconfigurable circuitry that changes from normal operating mode to fault recovery mode when an output fault is detected. During fault recovery mode, the circuit provides a modified output signal that allows independent recovery from an output fault condition. Once recovery is complete, the circuit returns to normal operating mode and provides a DC output signal proportional to the RMS value of an AC input signal.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 09/736,068, filed Dec. 13, 2000 now U.S. Pat. No. 6,516,291 which is hereby incorporated by reference herein in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to apparatus and methods for providing an output signal proportional to the root-mean-square (RMS) value of an input signal. More particularly, the present invention relates to apparatus and methods for detecting an output fault condition and for recovering from such a condition so that an output signal is provided. The output signal may be a direct current (DC) signal proportional to the RMS value of an input signal (commonly called RMS-to-DC conversion). 
     The RMS value of a waveform is a measure of the heating potential of that waveform. RMS measurements allow the magnitudes of all types of voltage (or current) waveforms to be compared to one another. Thus, for example, applying an alternating current (AC) waveform having a value of 1 volt RMS gain stage  36 . Gain stage  36  has an output V OUT , and provides a broadband gain A. 
     To simplify the description of pulse modulator  32  and demodulator  34 , the following discussion first assumes that A=B=1 (although in practice it is common for A=B&gt;1). As described below, this assumption only affects a scale factor in the resulting analysis. Pulse modulator  32  may be any commonly known pulse modulator, such as a pulse code modulator, pulse width modulator, or other similar modulator. As shown in FIG. 1, pulse modulator  32  is implemented as a single-bit oversampling ΔΣ pulse code modulator, and includes integrator  40 , comparator  41 , switch  42 , non-inverting buffer  44 , and inverting buffer  46 . As described in more detail below, switch  42  and buffers  44  and  46  form a single-bit multiplying digital-to-analog converter (MDAC)  47 . 
     Integrator  40  has a first input coupled to input V IN , a second input coupled to the pole of switch  42 , and an output coupled to an input of comparator  41 . Comparator  41  has a clock input coupled to clock signal CLK, and an output V 1  coupled to control terminals of switches  42  and  52 . Clock CLK is a fixed period clock that has a frequency that is much higher than the frequency of input V IN  (e.g., 100 times greater). Comparator  41  compares the signal at the output of integrator  40  to a reference level (e.g., GROUND), and latches the comparison result as output signal V 1  on an edge of clock CLK. 
     Non-inverting buffer  44  provides unity gain (i.e., +1.0) and has an input coupled to the output of gain stage  38 , and an output coupled to the first terminal of switch  42 . Inverting buffer  46  provides across a resistor produces the same amount of heat as applying 1 volt DC voltage across the resistor. 
     Mathematically, the RMS value of a signal V is defined as:                V   rms     =         V   2     _               (   1   )                                
     which involves squaring the signal V, computing the average value (represented by the overbar in equation (1)), and then determining the square root of the result. 
     Various previously known conversion techniques have been used to measure RMS values. One previously known conversion system uses oversampling analog-to-digital converters to generate precise digital representations of an applied signal. The digital representations are demodulated and filtered to produce a DC output signal that has the same heat potential as the applied signal. This type of system is attractive to circuit designers because it produces highly accurate results and can be efficiently implemented on an integrated circuit. 
     FIG. 1 is a generalized schematic representation of a portion of an RMS-to-DC converter circuit. As shown in FIG. 1, RMS-to-DC converter circuit  30  includes pulse modulator  32 , demodulator  34 , gain stage  36 , gain stage  38 , and lowpass filter  54 . Pulse modulator  32  has a first input coupled to V IN , a second input coupled to the output of gain stage  38  and an output V 1 . Demodulator  34  has an input coupled to V IN , a control input coupled to V 1 , and an output V 2 . Gain stage  38  has an input coupled to V OUT , and provides a broadband gain B. Lowpass filter  54  has an input coupled to V 2  and an output V 3  coupled to the input of inverting gain (i.e., −1.0) and has an input coupled to the output of gain stage  38 , and an output coupled to the second terminal of switch  42 . 
     V 1  is a signal having a binary output level (e.g., −1 or +1). If V 1 =+1, the pole of switch  42  is coupled to the output of non-inverting buffer  44 . That is, (assuming gain B=1)+V OUT  is coupled to the second input of integrator  40 . Alternatively, if V 1 =−1, the pole of switch  42  is coupled to the output of inverting buffer  46 . That is, (assuming gain B=1)−V OUT  is coupled to the second input of integrator  40 . This switching configuration provides negative feedback in pulse modulator  32 . 
     The first and second inputs of integrator  40  therefore can have values equal to: 
     
       
         − V   OUT   ≦V   IN   ≦+V   OUT   (2) 
       
     
     and V IN  thus has a bipolar input signal range. 
     From equation (2), if V 1  has a duty ratio D between 0-100%, D can be expressed as:                D   =       1   2     ×     (         V   IN       V   OUT       +   1     )         ,     0   ≤   D   ≤   1             (   3   )                                
     That is, if V IN −V OUT , D=0, and if V IN =+V OUT , D=1. 
     Demodulator  34  includes non-inverting buffer  48 , inverting buffer  50  and switch  52 , which form a single-bit MDAC. Non-inverting buffer  48  has an input coupled to V IN , and an output coupled to a first terminal of switch  52 . Inverting buffer  50  has an input coupled to V IN , and an output coupled to a second terminal of switch  52 . Switch  52  has a control terminal coupled to V 1  and a pole coupled to the input of lowpass filter  54 . 
     If V 1 =+1, the pole of switch  52  is coupled to the output of non-inverting buffer  48 . That is, +V IN  is coupled to the input of lowpass filter  54 . Alternatively, if V 1 =−1, the pole of switch  52  is coupled to the output of inverting buffer  50 . That is, −V IN  is coupled to the input of lowpass filter  54 . 
     Demodulator  34  provides an output signal V 2  at the pole of switch  52  that may be expressed as:                V   2     =                    +     V   IN       ×   D     -       (     -     V   IN       )     ×     (     D   -   1     )                              (     4      a     )                 =                  V   IN     ×     (       2   ×   D     -   1     )                            (     4      b     )                                  
     Substituting equation (3) into equation (4b), V 2  is given by:                V   2     =       V   IN   2       V   OUT               (   5   )                                
     Lowpass filter  54  may be a continuous-time or a discrete-time filter, and provides an output V 3  equal to the time average of input V 2 . Accordingly, V 3  equals:                V   3     =         V   IN   2     _       V   OUT               (   6   )                                
     Gain stage  36  provides an output V OUT  equal to (assuming gain A=1) V 3 :                V   OUT     =                    V   IN   2     _       V   OUT                            (     7      a     )                 =                      V   IN   2     _       =     V   RMS                            (     7      b     )                                  
     Thus, circuit  30  has a bipolar input range and provides an output V OUT  equal to the RMS value of input V IN . 
     Demodulator  34  and stage  47  each are single-bit MDACs and comparator  41  is a single-bit analog-to-digital converter (ADC) that provides a single-bit output V 1 . The difference between the output of integrator  40  and MDAC  47  equals the quantization error e[i] of pulse modulator  32 . 
     Because the output of comparator  41  controls the polarity of the feedback signal from V OUT  to the input integrator  40 , converter  30  will remain stable for only one polarity of V OUT . If V OUT  has a polarity opposite of that assumed for the connection of switch  42  (e.g., during power up, a brown out, or a load fault), modulator  32  will become unstable, and the output of integrator  40  will quickly approach a rail voltage. 
     With a DC input, this may not be problematic, because the state of V 1  might be such that V IN  propagates through MDAC  34  and results in the V 2  polarity desired for V OUT . In this case, once any external influences on V OUT  are removed, V 2  (and therefore V OUT ), will return to the proper polarity once it propagates through low pass filter  54 . This sequence, however, has a probability of occurring only about 50% of the time, meaning that converter  30  is unlikely to recover in almost half of the possible DC operating cases. Moreover, RMS-to-DC converters are most often used with AC signals, and in those instances output recovery is even less likely to occur. 
     Thus, in view of the foregoing, it would be desirable to provide methods and apparatus for performing RMS-to-DC conversions that have improved recovery characteristics. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of this invention to provide methods and apparatus for performing RMS-to-DC conversions that have fault detection and recovery capabilities. 
     In accordance with this and other objects of the present invention, circuitry and methods that supply the root-mean-square (RMS) value of an input signal and that detect and independently recover from output fault conditions are provided. The circuit of the present invention includes reconfigurable circuitry that changes from normal operating mode to fault recovery mode when an output fault is detected. During fault recovery mode, the circuit of the present invention generates a modified output signal that allows independent recovery from an output fault condition. Once recovery is complete, the circuit returns to the RMS mode of operation. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above-mentioned objects and features of the present invention can be more clearly understood from the following detailed description considered in conjunction with the following drawings, in which the same reference numerals denote the same structural elements throughout, and in which: 
     FIG. 1 is a schematic diagram of a previously known RMS-to-DC converter circuit; 
     FIG. 2A is a schematic diagram of an RMS-to-DC converter circuit of the present invention; 
     FIG. 2B is another schematic diagram of an RMS-to-DC converter circuit of the present invention; 
     FIG. 3A is another schematic diagram of an RMS-to-DC converter circuit of the present invention; 
     FIG. 3B is another schematic diagram of an RMS-to-DC converter circuit of the present invention; 
     FIG. 4A is another schematic diagram of an RMS-to-DC converter circuit of the present invention; 
     FIG. 4B is another schematic diagram of an RMS-to-DC converter circuit of the present invention; 
     FIG. 5 is a schematic diagram of the reconfigurable ΔΣ modulator of FIGS.  2 - 4 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2A illustrates an embodiment of RMS-to-DC converter constructed in accordance with the principles of the present invention. Circuit  130  includes pulse modulator  132 , demodulator  134 , gain stages  36  and  38 , lowpass filter  54 , and optional delay-matching stage  82 . To simplify the description of modulator  132  and demodulator  134 , the following discussion assumes that A=B=1 (although in practice it is common for A=B&gt;1). This assumption only affects a scale factor in the resulting analysis. 
     Pulse modulator  132  includes cascaded AZ pulse code modulators. In particular, pulse modulator  132  includes reconfigurable ΔΣ stage  72 , ΔΣ stage  76 , monitor circuit  73 , delay stage  78 , and subtractor  80 . As described in more detail below, ΔΣ stage  76 , delay stage  78 , and subtractor  80  provide an estimate of the spectrally-shaped quantization error of reconfigurable ΔΣ stage  72 . 
     Reconfigurable ΔΣ stage  72  has a first input coupled to V IN , a second input coupled to the output of gain stage  38  (through switch  75 ), a first output coupled to the input of monitor circuit  73 , and a second output V 4  coupled to a first input of ΔΣ stage  76 . ΔΣ stage  76  has a second input coupled to the output of gain stage  38 , and an output V 5  coupled to a non-inverting input of subtractor  80  and to an input of delay stage  78 . Subtractor  80  has an inverting input coupled to an output of delay stage  78 , and an output V 1b  coupled to a control terminal of switch  96 . Monitor circuit  73  may include a delay stage (not shown) to match the delay through ΔΣ stage  76 , and has an output V 1a  coupled to a control terminal of switch  88 . 
     ΔΣ stages  72  and  76  may be, for example, single-bit modulators that can be of any order. Preferably, reconfigurable ΔΣ stage  72  is a first-order stage. Reconfigurable first-order ΔΣ stage  72  and monitor circuit  73  provide output V 1a  equal to (assuming gain B=1):                  V     1      a            [     i   +   1     ]       =         (       V   IN          [     i   -   1     ]       )       V   OUT       +       (       e        [   i   ]       -     e        [     i   -   1     ]         )       V   OUT                 (   8   )                                
     where index i denotes the sample index and e[i] is the quantization error of reconfigurable ΔΣ stage  72 . V 1a  thus equals the desired ratio of the input divided by V OUT , plus the spectrally-shaped quantization error of reconfigurable ΔΣ stage  72  divided by V OUT . 
     ΔΣ stage  76 , delay stage  78  and subtractor  80  provide an output V 1b  equal to an estimate of the spectrally-shaped quantization error of reconfigurable ΔΣ stage  72  divided by V OUT . In particular, V 4  is the quantization error e[i] of reconfigurable ΔΣ stage  72 , which is a function of the input signal V IN , the state of the integrator, and the local feedback within the MDAC of reconfigurable ΔΣ stage  72 . ΔΣ stage  76  provides an output V 5  equal to (assuming gain B=1):                  V   5          [     i   +   1     ]       =       (     1     V   OUT       )     ×     [       e        [   i   ]       +     (         e   ′          [     i   +   1     ]       -       e   ′          [   i   ]         )       ]               (   9   )                                
     where e′[i] is the quantization error of ΔΣ stage  76 . Delay stage  78  and subtractor  80  form a digital differentiator that provide an output V 1b  equal to (assuming gain B=1):                  V     1      b            [     i   +   1     ]       =       (     1     V   OUT       )     ×     [       e   1     +     e   2       ]               (   10   )                                
     where 
     
       
           e   1   =e[i]−e[i −1]  (11a) 
       
     
     
       
           e   2   =e′[i +1]−2e′[i]+ e′[i −1]  (11b) 
       
     
     Delay stage  82  matches the combined delay through pulse code modulator  132 . Demodulator  134  provides an output proportional to input V IN  times the ratio of V IN  to V OUT . In particular, demodulator  134  includes non-inverting buffer  84 , inverting buffer  86 , switch  88 , subtractor  90 , non-inverting buffer  92 , inverting buffer  94 , three-position switch  96  and multiply-by-two stage  97 . Non-inverting buffer  84  provides unity gain (i.e., +1.0) and has an input coupled through delay stage  82  to input V IN , and an output coupled to the first terminal of switch  88 . Inverting buffer  86  provides inverting gain (i.e., −1.0) and has an input coupled through delay stage  82  to input V IN , and an output coupled to the second terminal of switch  88 . Non-inverting buffer  84 , inverting buffer  86  and switch  88  form a single-bit MDAC. 
     V 1a  is a binary signal having a binary output level (e.g., −1 or +1). If V 1a =+1, the pole of switch  88  is coupled to the output of non-inverting buffer  84 . That is, +V IN  is coupled to first input V 6  of subtractor  90 . Alternatively, if V 1a =−1, the pole of switch  88  is coupled to the output of inverting buffer  86 . That is, V IN  is coupled to first input V 6  of subtractor  90 . V 6  equals (assuming gain B=1):                  V   6          [     i   +   1     ]       =                      V   IN          [     i   -   1     ]         V   OUT       ×       V     1      a            [     i   +   1     ]                              (     12      a     )                 =                      V   IN          [     i   -   1     ]         V   OUT       ×     (         V   IN          [     i   -   1     ]       +     e   1       )                            (     12      b     )                                  
     Non-inverting buffer  92  provides unity gain (i.e., +1.0) and has an input coupled through delay stage  82  to input V IN , and an output coupled to the first terminal of three-position switch  96 . Inverting buffer  86  provides inverting gain (i.e., −1.0) and has an input coupled through delay stage  82  to input V IN , and an output coupled to the third terminal of three-position switch  96 . The second terminal of three-position switch  96  is coupled to GROUND. Non-inverting buffer  92 , inverting buffer  94  and three-position switch  96  form a 1.5-bit MDAC. Multiply-by-two stage  97  provides a gain of +2.0. 
     V 1b  is a tri-level signal having output values of −2, 0 or +2. If V 1b =+2, the pole of three-position switch  96  is coupled to the output of non-inverting buffer  92 . That is, +2V IN  is coupled to second input V 7  of subtractor  90 . If V 1b =0, the pole of switch  96  is coupled to GROUND, and therefore 0 is coupled to second input V 7  of subtractor  90 . If, however, V 1b =−2, the pole of switch  96  is coupled to the output of inverting buffer  94 . That is, −2V IN  is coupled to second input V 7  of subtractor  90 . V 7  equals (assuming gain B=1):                  V   7          [     i   +   1     ]       =           V   IN          [     i   -   1     ]         V   OUT       ×     (       e   1     +     e   2       )               (   13   )                                
     Subtractor  90  provides an output V 8  that equals the difference between V 6  and V 7 :                  V   8          [     i   +   1     ]       =                    V   6          [     i   +   1     ]       -       V   7          [     i   +   1     ]                              (     14      a     )                 =                        V   IN          [     i   -   1     ]       2       V   OUT       -             V   IN          [     i   -   1     ]       2       V   OUT       ×     e   2                              (     14      b     )                                  
     Thus, V 8  is proportional to V IN  squared divided by V OUT , substantially without the quantization noise of reconfigurable ΔΣ stage  72 . The quantization noise e 2  of ΔΣ stage  76  remains, but the low frequency portion of that noise is further reduced by the spectral shaping provided by delay  78  and subtractor  80 . Further, because e 2  is uncorrelated with V IN , the DC average of the product of e 2  and V IN  equals zero. As a result, output V 9  of lowpass filter  54  approximately equals:                V   9     ≈         V   IN   2     _               (   15   )                                
     Output V OUT  of gain stage  36  approximately equals (assuming gain A=1):                V   OUT     ≈         V   IN   2     _               (   16   )                                
     The circuit of FIG. 2A may be implemented using single-ended or differential circuitry. 
     During operation, output signals from reconfigurable ΔΣ stage  72  may pass through monitor circuit  73  to the pole of switch  88 . As mentioned above, when V OUT  changes polarity, ΔΣ stages  72  and  76  become unstable, producing a string of output bits with the same logic level. Monitor circuit  73 , which may include counter circuits and/or latch circuitry (not shown), detects this string and interprets it as a “fault condition.” In response to the detected fault condition, monitor circuit  73  generates a control signal that causes circuit  130  to switch from RMS-to-DC conversion mode to fault recovery mode. 
     The number of consecutive same logic level bits that constitute a fault condition may be varied if desired. For example, with certain modulator topologies, the number of bits may be set to be relatively long (e.g., about 50) to ensure circuit  130  does not enter recovery mode inadvertently. In other applications, however, the number of bits may be somewhat less (e.g., about 15) to reduce recovery time. 
     In fault recovery mode, switch  75  is opened, breaking the feedback path from output V OUT  to ΔΣ stage  72 . In addition, some components within ΔΣ stage  72  are reconfigured so that ΔΣ stage  72  functions as a comparator circuit rather than as a modulator circuit (shown as comparator circuit  77  in FIG.  2 B). 
     With this arrangement, shown in FIG. 2B, circuit  130  operates as a mean-absolute-detect circuit instead of an RMS-to-DC converter. Circuit  130  thus determines the average of the absolute value of input signal V IN . Although this measurement is less meaningful than the RMS value of the input signal, it ensures circuit  130  will produce an output signal V OUT  that has the proper polarity. Once V OUT  returns to the correct polarity, the bit stream produced by ΔΣ stage  76  toggles, indicating that the fault condition has cleared. Monitor circuit  73  detects this change of logic level and returns circuit  130  to RMS-to-DC conversion mode (i.e., closes switch  75  and reconfigures comparator  77  to operate as ΔΣ stage  72 ). In this way, circuit  130  may detect and recover from fault conditions irrespective of the type and amplitude of input signal V IN . 
     As shown in FIG. 2B, to operate as a mean-absolute-detect circuit, the feedback from V OUT  to comparator  77  is disconnected. The output signal produced by comparator  77  is a bit stream that represents the polarity of input signal V IN . Comparator  77  may be configured as a polarity detector using any suitable arrangement known in the art (e.g., by connecting a threshold terminal to ground and a sensing terminal (both not shown) to input signal V IN ). 
     When the output of comparator  77  is provided to demodulator  134  (i.e., the pole of switch  88 ), the input signal V IN  is multiplied by its own polarity, thus performing an absolute value operation. The resulting signal is then fed through lowpass filter  54  which provides an output signal V OUT  of the desired polarity (assuming any external stimuli has been removed from the output node). 
     As long as output signal V OUT  is the incorrect polarity, ΔΣ stage  76  will be unstable, and its output will remain at either a logic low or a logic high (depending on its state when the output fault occurred). When this occurs, subtractor  80  has a substantially zero output and will not affect the value of V OUT . 
     When circuit  130  is operating in mean-absolute-detect mode, error signal V 4  produced by comparator  77  is the input signal V IN  (or a scaled version thereof). Thus, the output of ΔΣ stage  76  can be monitored (by monitor circuit  73 ) to determine when recovery from an output fault has occurred. For example, when the bit stream produced by ΔΣ stage  76  toggles from one logic state to another, circuit  130  has recovered from the fault condition and may be reconfigured back to the RMS-to-DC converter shown in FIG.  2 A. 
     The overall gain of circuit  130  during fault recovery (i.e., mean-absolute-detect mode) does not need to be similar to that of the RMS-to-DC mode (i.e., normal operation). However, increased gain during fault recovery does tend to reduce recovery time. Moreover, it will be understood that with certain input waveforms and filter time constants, circuit  130  may go into fault recovery, back to normal operation, and return to fault recovery several times in succession. As long as the output is free of external influences however, circuit  130  will recover. The successive fault mode periods will become shorter in duration until circuit  130  has fully recovered. 
     FIG. 3A shows another illustrative embodiment of RMS-to-DC converter constructed in accordance with the present invention. Converter  230  includes single-sample delay stages  82  and  104 , modulator  232  and demodulator  234 . Modulator  232  includes single-bit reconfigurable ΔΣ stage  72 , ΔΣ stage  76 , and monitor circuit  73 , and demodulator  234  includes single-bit MDAC stages  98 ,  100  and  102 , and adder/subtractor  106 . MDACS  98 ,  100 , and  102  may be implemented as in demodulator  34  of FIG.  1 . Alternatively, some of MDACS  98 ,  100  and  102  may be implemented as a single time-multiplexed MDAC. 
     Reconfigurable ΔΣ stage  72  provides a quantized output V 1c  equal to (assuming gain B=1):                  V     1      c            [   i   ]       =           V   IN          [     i   -   1     ]       +     e        [   i   ]       -     e        [     i   -   1     ]           V   OUT               (   17   )                                
     In addition, V 4  equals the quantization error e[i] of reconfigurable ΔΣ stage  72 . 
     ΔΣ stage  76  provides a quantized output V 1d  equal to (assuming gain B=1):                  V     1      d            [   i   ]       =         e        [     i   -   1     ]       +       e   ′          [   i   ]       -       e   ′          [     i   -   1     ]           V   OUT               (   18   )                                
     Single-bit DACs  98 ,  100  and  102  provide outputs V 10 , V 11  and V 12 , respectively, equal to (assuming gain B=1): 
     
       
           V   10   [i]=V   IN   [i −1 ]×V   1c   [i]   (19) 
       
     
       V   11   [i]=V   IN   [i −1 ]×V   1d   [i]   (20) 
     
       
           V   12   [i]=V   IN   [i −2 ]×V   1d   [i]   (21) 
       
     
     Adder/subtractor  106  provides an output V 13  equal to: 
     
       
           V   13   [i]=V   10   [i]+V   11   [i]−V   12   [i]   (22) 
       
     
     which equals (assuming gain B=1):                  V   13          [   i   ]       =             V   IN          [     i   -   1     ]         V   OUT       ×     (         V   IN          [     i   -   1     ]       +     e        [   i   ]       +       e   ′          [   i   ]       -       e   ′          [     i   -   1     ]         )       -           V   IN          [     i   -   2     ]         V   OUT       ×     (       e        [     i   -   1     ]       +       e   ′          [   i   ]       -       e   ′          [     i   -   1     ]         )                 (   23   )                                
     Note that:                  V   13          [     i   +   1     ]       =             V   IN          [   i   ]         V   OUT       ×     (         V   IN          [   i   ]       +     e        [     i   +   1     ]       +       e   ′          [     i   +   1     ]       -       e   ′          [   i   ]         )       -           V   IN          [     i   -   1     ]         V   OUT       ×     (       e        [   i   ]       +       e   ′          [     i   +   1     ]       -       e   ′          [   i   ]         )                 (   24   )                                
     If the time constant of lowpass filter  54  is much greater than the sample period of V 13 [i] (e.g., 10,000 times), lowpass filter  54  provides output V 14  that is the average of sequence V 13 . V 13  as a function of V IN [i−1] approximately equals:                V   13     ∣       V   IN          [     i   -   1     ]       ≈             V   IN          [     i   -   1     ]         V   OUT       ×     (         V   IN          [     i   -   1     ]       +     e        [   i   ]       +       e   ′          [   i   ]       -       e   ′          [     i   -   1     ]         )       -           V   IN          [     i   -   1     ]         V   OUT       ×     (       e        [   i   ]       +       e   ′          [     i   +   1     ]       -       e   ′          [   i   ]         )                 (   25   )                                
     which may be written as:                  V   13     ∣       V   IN          [     i   -   1     ]         =         (         V   IN          [     i   -   1     ]         V   OUT       )     2     -           V   IN          [     i   -   1     ]       ×     (         e   ′          [     i   +   1     ]       -     2          e   ′          [   i   ]         +       e   ′          [     i   -   1     ]         )         V   OUT                 (   26   )                                
     The first term on the right side of equation (26) is the desired output, and the second term equals the second-order spectrally-shaped quantization noise of ΔΣ stage  76 , which is substantially reduced by lowpass filter  54 . Further, because e′ is uncorrelated with V IN , the DC average of the product of e′ and V IN  equals zero. As a result, V 14  approximately equals:                V   14     =         V   13     _     ≈         V   IN   2     _       V   OUT                 (   27   )                                
     Output V OUT  of gain stage  36  approximately equals (assuming gain A=1):                V   OUT     ≈         V   IN   2     _               (   28   )                                
     The circuit of FIG. 3A may be implemented using single-ended or differential circuitry. 
     During operation, output signals from reconfigurable ΔΣ stage  72  may pass through monitor circuit  73  to MDAC  98 . As mentioned above, when V OUT  changes polarity, ΔΣ stages  72  and  76  become unstable, producing a string of output signals with a constant logic level. Monitor circuit  73  detects this output string, which it interprets as a “fault condition” and generates a control signal that causes circuit  230  to switch from RMS-to-DC conversion mode to fault recovery mode. 
     In fault recovery mode, switch  75  is opened, breaking the feedback path from output V OUT  to ΔΣ stage  72 . Additionally, some components within ΔΣ stage  72  are reconfigured so that ΔΣ stage  72  functions as a comparator circuit rather than as a modulator circuit (shown as comparator circuit  77  in FIG.  3 B). 
     In this arrangement, shown in FIG. 3B, circuit  230  operates as a mean-absolute-detect circuit instead of an RMS-to-DC converter. Circuit  230  thus determines the average of the absolute value of the input signal. Although this measurement is less meaningful than the RMS value of the input signal, it ensures circuit  230  will produce an output signal V OUT  that has the proper polarity. Once V OUT  returns to the proper polarity, the bit stream produced by comparator  77  toggles, indicating that the fault condition has cleared. Monitor circuit  73  detects this change of logic level and returns circuit  230  back to RMS-to-DC conversion mode (i.e., closes switch  75  and reconfigures comparator  77  to operate as ΔΣ stage  72 ). In this way, circuit  230  may detect and recover from fault conditions irrespective of the type and amplitude of input signal V IN . 
     As shown in FIG. 3B, to operate as a mean-absolute-detect circuit, the feedback from V OUT  to comparator  77  is disconnected. The output signal produced by comparator  77  is a bit stream that represents the polarity of input signal V IN . Comparator  77  may be configured as a polarity detector using any suitable method known in the art (e.g., by connecting a threshold terminal to ground and a sensing terminal (both not shown) to input signal V IN ). When the output of comparator  77  is provided to demodulator  234  (i.e., MDAC  98 ), input signal V IN  is multiplied by its own polarity, thus performing an absolute value operation. The resulting signal is fed through lowpass filter  54  which generates an output signal (V OUT ) of the desired polarity (assuming any external stimuli has been removed from the output node). 
     As long as output signal V OUT  is the incorrect polarity, ΔΣ stage  76  will remain unstable. Its output will therefore remain at either a logic low or a logic high (depending on its state when the output fault occurred). When this occurs, V 11  and V 12  substantially cancel each other out (at summing node  106 ), and thus output V 13  is substantially equal to the value of V 10 . Alternatively, V 11  and V 12  may be disconnected from summer  106  during fault recovery. 
     When circuit  230  is operating as a mean-absolute-detector, error signal V 4  produced by comparator  77  is the input signal V IN  (or a scaled version thereof). Thus, the output of ΔΣ stage  76  can be monitored (by monitor circuit  73 ) to determine when recovery from an output fault has occurred. For example, when the bit stream produced by ΔΣ stage  76  toggles from one logic state to another, indicating a change in output polarity, circuit  230  has recovered from the fault condition and may be reconfigured back to the RMS-to-DC converter shown in FIG.  3 A. 
     The overall gain of circuit  230  during fault recovery (i.e., mean-absolute-detect mode) does not need to be similar to that of the RMS-to-DC mode (normal operation). However, increased gain during fault recovery does tend to reduce recovery time. Moreover, it will be understood that with certain input waveforms and filter time constants, circuit  230  may go into fault recovery, back to normal operation, and back to fault recovery several times in succession. As long as the output is free of external influences however, circuit  230  will recover. The successive fault mode periods will become shorter in duration until circuit  230  has fully recovered. 
     FIG. 4A illustrates another embodiment of RMS-to-DC converters constructed in accordance with the principles of the present invention. Circuit  330  includes delay stages  82  and  104  and pulse modulator  332  and demodulator  334 . Circuit  330  includes features of circuits  130  and  230 , but substantially eliminates the effect of any DC offset that may occur in ΔΣ stage  76  and delay stage  104 . 
     Modulator  332  includes single-bit reconfigurable ΔΣ stage  72  and ΔΣ stage  76 , delay stage  78 , and subtractor  80 . Demodulator  334  includes 1-bit DAC  87 , 1.5-bit DAC  89  (which may be constructed similar to the DAC formed by buffers  92  and  94  and switch  96 ), subtractor  90 , and multiply-by-two stage  97 . Delay stage  82  matches the delay through reconfigurable ΔΣ modulator  72  and delay stage  104  matches the delay through ΔΣ modulator  76 . 
     Reconfigurable ΔΣ stage  72  provides a quantized output V 1e  equal to (assuming gain B=1):                  V     1      e            [   i   ]       =           V   IN          [     i   -   1     ]       +     e        [   i   ]       -     e        [     i   -   1     ]           V   OUT               (   29   )                                
     ΔΣ stage  76 , delay stage  78  and subtractor  80  provide an output V 1f  equal to an estimate of the spectrally-shaped quantization error V 4  of reconfigurable ΔΣ stage  72  divided by V OUT . ΔΣ stage  76  provides an output V 15  equal to (assuming gain B=1):                  V   15          [     i   +   1     ]       =       (     1     V   OUT       )     ×     [       e        [   i   ]       +     (         e   ′          [     i   +   1     ]       -       e   ′          [   i   ]         )       ]               (   30   )                                
     where e′[i] is the quantization error of ΔΣ stage  76 . Delay stage  78  and subtractor  80  form a digital differentiator that provide an output V 1f  equal to (assuming gain B=1):                  V     1      f            [     i   +   1     ]       =       (     1     V   OUT       )     ×     [       e   1     +     e   2       ]               (   31   )                                
     where 
     
       
           e   1   =e[i]−e[i −1]  (32a) 
       
     
     
       
           e   2   =e′[i +1]−2 e′[i]+e′[i −1]  (32b) 
       
     
     V 16  equals (assuming gain B=1):                  V   16          [   i   ]       =                      V   IN          [     i   -   1     ]         V   OUT       ×       V     1      e            [   i   ]                              (     33      a     )                 =                      V   IN          [     i   -   1     ]         V   OUT       ×     (         V   IN          [     i   -   1     ]       +     e   1       )                            (     33      b     )                                  
     V 17  equals (assuming gain B=1):                  V   17          [     i   +   1     ]       =           V   IN          [     i   -   1     ]         V   OUT       ×     (       e   1     +     e   2       )               (   34   )                                
     The digital differentiator formed by delay stage  78  and subtractor  80  has a zero at DC, and therefore sequence V 1f  substantially has no DC component. As a result, sequence V 17  is substantially free of any DC offset introduced by delay stages  82  and  104 , and ΔΣ stage  76 . 
     Subtractor  90  provides an output V 18  that equals the difference between V 16  and V 17 :                  V   18          [     i   +   1     ]       =                    V   16          [   i   ]       -       V   17          [     i   +   1     ]                              (     35      a     )                 =                        V   IN          [     i   -   1     ]       2       V   OUT       -         V   IN       V   OUT       ×     e   2                              (     35      b     )                                  
     Thus, V 18  is proportional to V IN  squared divided by V OUT , substantially without the quantization noise of Δ−Σ stage  72 . Output V 19  of lowpass filter  54  approximately equals:                V   19     ≈         V   IN   2     _               (   36   )                                
     and output V OUT  of gain stage  36  approximately equals (assuming gain A=1):                V   OUT     ≈         V   IN   2     _               (   37   )                                
     The circuit of FIG. 4A may be implemented using single-ended or differential circuitry. 
     During operation, output signals from reconfigurable ΔΣ stage  72  may pass through monitor circuit  73  to MDAC  87 . As mentioned above, when V OUT  changes polarity, ΔΣ stages  72  and  76  become unstable, producing a string of output signals with a constant logic level. Monitor circuit  73  detects this output string, which it interprets as a “fault condition” and generates a control signal that causes circuit  330  to switch from RMS-to-DC conversion mode to fault recovery mode. 
     In fault recovery mode, switch  75  is opened, breaking the feedback path from output V OUT  to ΔΣ stage  72 . Additionally, some components within ΔΣ stage  72  are reconfigured so that ΔΣ stage  72  functions as a comparator circuit rather than as a modulator circuit (shown as comparator circuit  77  in FIG.  4 B). 
     In this arrangement, shown in FIG. 4B, circuit  330  operates as a mean-absolute-detect circuit instead of an RMS-to-DC converter. Circuit  330  thus determines the average of the absolute value of the input signal. Although this measurement is less meaningful than the RMS value of the input signal, it ensures circuit  330  will produce an output signal V OUT  that has the proper polarity. Once V OUT  returns to the proper polarity, the bit stream produced by comparator  77  toggles, indicating that the fault condition has cleared. Monitor circuit  73  detects this change of logic level and returns circuit  330  back to RMS-to-DC conversion mode (i.e., closes switch  75  and reconfigures comparator  77  to operate as ΔΣ stage  72 ). In this way, circuit  330  may detect and recover from fault conditions irrespective of the type and amplitude of input signal V IN . 
     As shown in FIG. 4B, to operate as a mean-absolute-detect circuit, the feedback from V OUT  to comparator  77  is disconnected. The output signal produced by comparator  77  is a bit stream that represents the polarity of input signal V IN . 
     Comparator  77  may be configured as a polarity detector using any suitable method known in the art (e.g., by connecting a threshold terminal to ground and a sensing terminal (both not shown) to input signal V IN ). 
     When the output of comparator  77  is provided to demodulator  334  (i.e., MDAC  87 ), input signal V IN  is multiplied by its own polarity, thus performing an absolute value operation. The resulting signal is fed through lowpass filter  54  which generates an output signal (V OUT ) of the desired polarity (assuming any external stimuli has been removed from the output node). 
     As long as output signal V OUT  is the incorrect polarity, ΔΣ stage  76  will remain unstable. Its output will therefore remain at either a logic low or a logic high (depending on its state when the output fault occurred). In this case, subtractor  80  will have a substantially zero output and will not affect the value of V OUT . 
     When circuit  330  is operating as a mean-absolute-detect circuit, error signal V 4  produced by comparator  77  is the input signal V IN  (or a scaled version thereof). Thus, the output of ΔΣ stage  76  can be monitored (by monitor circuit  73 ) to determine when recovery from an output fault has occurred. For example, when the bit stream produced by ΔΣ stage  76  toggles from one logic state to another, indicating the output has changed polarity, circuit  330  has recovered from the fault condition and may be reconfigured back to the RMS-to-DC converter shown in FIG.  4 A. 
     The overall gain of circuit  330  during fault recovery (i.e., mean-absolute-detect mode) does not need to be similar to that of the RMS-to-DC mode (normal operation). However, increased gain during fault recovery does tend to reduce recovery time. Moreover, it will be understood that with certain input waveforms and filter time constants, circuit  330  may go into fault recovery, back to normal operation, and back to fault recovery several times in succession. As long as the output is free of external influences however, circuit  330  will recover. The successive fault mode periods will become shorter in duration until circuit  330  has fully recovered. 
     As mentioned above, monitoring circuit  73  may detect an output fault by detecting a string of same logic level output bits from reconfigurable ΔΣ stage  72 . This will occur anytime reconfigurable ΔΣ stage  72  is overloaded, either because it is unstable or because the input signal V IN  is excessively large. Thus, under certain circumstances a fault condition may be detected even when the output signal V OUT  is the “correct” polarity. 
     One such case is when the amplitude of the input signal (V IN ) increases suddenly. For example, a step change of about a factor of ten may cause reconfigurable ΔΣ stage  72  to overload and produce an output duty cycle of either 0% or 100% at the peaks of the input waveform. This result is acceptable and even desirable because it tends to decrease the output response time. 
     Another case during which a fault condition may be detected is when input signal V IN  has a large peak value with respect to the DC level of the output signal V OUT  (e.g., this may occur with input signals V IN  having a high crest factor). Such an input signal may, during its peak, cause reconfigurable ΔΣ stage  72  to produce an output having a duty cycle of either 0% or 100%. Depending on the duration of the peak and the length of the output string detected by monitor circuit  73 , this may initiate entry into the fault recovery mode of operation. This will increase the magnitude of the output signal V OUT  during a time when it otherwise would be underestimated. 
     FIG. 5 is a schematic diagram of one possible embodiment of reconfigurable ΔΣ stage  72 . In FIG. 5, reconfigurable ΔΣ stage  72 , shown as system  500 , includes switches  501 - 508 , capacitors  510 - 517 , amplifier  518 , and comparator  519 . As mentioned above, system  500  may be configured to operate as either ΔΣ modulator  72  or as comparator  77 , depending on the state (i.e., open or closed) of switches  501 - 508 . 
     When configured as ΔΣ stage  72 , system  500  progresses through essentially two phases of operation, an auto-zero phase and integration phase. In auto-zero phase, switches  501 ,  506 , and  508  are closed. In addition, either switches  503  or  504  are closed depending on the output of comparator  519 . For example, if the output of comparator  519  is a logic high, switches  504  may be closed and switches  503  may be open. Alternatively, if the output of comparator  519  is a logic low, switches  504  may be open and switches  503  may be closed. 
     Input voltage V IN  is applied to node  520  and node  522  is connected to ground (if desired, node  522  may be used as a differential input). In the arrangement shown, capacitor  510  is charged to the value of input voltage V IN , and capacitor  511  is set to ground. Assuming for the sake of illustration, that switches  503  are closed and switches  504  are open, capacitor  512  is charged to the value of V OUT  and capacitor  513  is set to ground. 
     Closing switches  506  provides a feedback path from outputs  532  and  536  of amplifier  518  to inputs  530  and  534 , respectively. This sets the gain of amplifier  518 , which is preferably a differential transconductance amplifier, to unity. At this point, system  500  has acquired the values of both the input and output voltages and is ready to proceed to the integration phase of operation. 
     In the integration phase, switches  501  and  506  are opened and switches  502  and  505  are closed, configuring amplifier  518  as an integrator. Furthermore, the state of switches  503  or  504  are interchanged. That is, if switches  503  were closed and switches  504  were open during auto-zero, switches  503  open and switches  504  close during integration (and vice versa). This transfers the charge from capacitors  510 - 513  to capacitors  515  and  516 , respectively. Thus, the resulting charge on capacitors  515  and  516  is now equal to the transferred charge plus any charge from the previous integration phase. Amplifier  518  generates a differential output at terminals  532  and  536  which is a function of the result of the previous integration phase, the value of V IN  and V OUT , and the output state of comparator  519 . Comparator  519 , which is preferably a latching comparator, compares these values and generates an output signal based on the comparison. 
     When configured as comparator stage  77 , system  500  also operates in essentially two phases of operation, an auto-zero phase and a sample and hold phase. In auto-zero phase, switches  501 ,  506 , and  508  are closed. In addition, either switches  503  or  504  are closed. 
     Input voltage V IN  is applied to node  520  and node  522  is connected to ground. In this arrangement, capacitor  510  is charged to the value of input voltage V IN , and capacitor  511  is set to ground. Closing switches  506  provides a feedback path from outputs  532  and  536  of amplifier  518  to inputs  530  and  534 , respectively. This sets the gain of amplifier  518  to unity. At this point, system  500  has acquired the values of both the input and output voltages and is ready to proceed to the sample and hold phase of operation. 
     In the sample and hold phase, switches  501  and  506  are opened and switches  502  and  507  are closed, configuring amplifier  518  as a buffer. In this mode the state of switches  503  or  504  are preferably not interchanged. The charge from capacitors  510  and  511  (but not  512  and  513 ) is transferred to capacitors  514  and  517 , respectively. Thus, the resulting charge on capacitors  514  and  517  is now substantially equal to the input voltage V IN . Amplifier  518  generates a differential output at terminals  532  and  536  based on V IN , which is provided to input terminals  540  and  542  of comparator  519 . Comparator  519  compares these values and generates an output signal based on the comparison. 
     Persons skilled in the art will recognize that the apparatus of the present invention may be implemented using circuit configurations other than those shown and discussed above. All such modifications are within the scope of the present invention, which is limited only by the claims that follow.