Abstract:
A circuit for charging a battery may include a switch operable for conducting a current flowing through the switch, and a first amplifier coupled to the switch and operable for adjusting the current according to an amount of power dissipation associated with the switch.

Description:
RELATED APPLICATION 
       [0001]    This application claims priority to U.S. Provisional Application No. 61/195,778, “Battery Charging Systems,” filed on Oct. 9, 2008, which is hereby incorporated by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    Generally, a conventional battery charging system, e.g., a Li-Ion battery charging system, has three charge periods including a precharge period, a constant current (CC) charge period, and a constant voltage (CV) charge period. Referring to  FIG. 1 , a charging profile  100  of a conventional battery charging system during the three periods is illustrated. 
         [0003]    As shown in  FIG. 1 , the charging profile  100  includes a charging current profile  102  of a battery cell and a voltage profile  104  of the battery cell. The charging current profile  102  changes with the voltage profile  104  during the three charge periods described above. During the precharge period, the battery cell is charged with a small precharging current as shown in the charging current profile  102 , and the battery cell voltage can increase slowly as shown in the voltage profile  104 . When the battery cell voltage reaches a voltage threshold of a CC mode marked in the voltage profile  104 , the battery charging system is transferred to the CC charge period. During the CC charge period, the battery cell is charged with a constant current as shown in the charging current profile  102 , and accordingly the battery cell voltage can increase rapidly as shown in the voltage profile  104 . When the battery cell voltage increases to a voltage threshold of a CV mode marked in the voltage profile  104 , the battery charging system is transferred to the CV charge period. During the CV charge period, the battery cell will be charged with a current decreasing gradually as shown in the charging current profile  102  to keep the voltage of the battery cell constant and equal to the voltage threshold of the CV mode. 
         [0004]    Power dissipation of a charging switch in a battery charging system can be expressed as I CC (V IN −V BATT ), where I CC  represents the constant current and (V IN −V BATT ) represents a voltage difference between a power source voltage, e.g., a voltage of an alternating current (AC) adaptor or a Universal Serial Bus (USB) port, and the battery cell voltage. In a battery charging system with a linear charger, a thermal issue may arise during the CC charge period since the value of I CC *(V IN −V BATT ) may be relatively high when the battery cell voltage is relatively low. This thermal issue may trigger the battery charging system&#39;s thermal protection mechanism, causing the battery charging system to stop charging until the temperature cools down enough. Under some circumstances, the battery charging system may stop charging after a relatively short period of time. This in turn may cause the battery charging system to quickly oscillate between charging and not charging, which may decrease the efficiency of the battery charging system. 
       SUMMARY 
       [0005]    In one embodiment, a circuit for charging a battery includes a switch operable for conducting a current flowing through the switch, and a first amplifier coupled to the switch and operable for adjusting the current according to an amount of power dissipation associated with the switch. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    Features and advantages of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds, and upon reference to the drawings, wherein like numerals depict like parts, and in which: 
           [0007]      FIG. 1  illustrates a charging profile for a conventional battery charging system. 
           [0008]      FIG. 2  is a block diagram of an example of a battery charging system in accordance with one embodiment of the present invention. 
           [0009]      FIG. 3  is a block diagram of an example of a battery charging system in accordance with another embodiment of the present invention. 
           [0010]      FIG. 4  illustrates a charging profile for a battery charging system in accordance with one embodiment of the present invention. 
           [0011]      FIG. 5  illustrates a flowchart of operations performed by a battery charging system, in accordance with one embodiment of the present invention. 
           [0012]      FIG. 6  illustrates a flowchart of operations performed by a battery charging system, in accordance with another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    Reference will now be made in detail to embodiments of the present invention. While the invention will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which can be included within the spirit and scope of the invention as defined by the appended claims. 
         [0014]    Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one of ordinary skill in the art that the present invention can be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention. 
         [0015]      FIG. 2  illustrates a block diagram of an example of a battery charging system  200  with power dissipation control, in accordance with one embodiment of the present invention. 
         [0016]    In this embodiment, a first reference voltage V SET  is provided to a non-inverting input terminal of an amplifier  202 , e.g., an operational amplifier (OPA). Moreover, an inverting input terminal and an output terminal of the OPA  202  are coupled to a source terminal and a gate terminal of a transistor  206 , e.g., an N-Metal-Oxide-Semiconductor (NMOS) transistor, respectively. In addition, a resistor  210  is coupled between the source terminal of the NMOS transistor  206  and ground. 
         [0017]    An inverting input voltage of the OPA  202  is equal to a non-inverting input voltage thereof, and therefore a source voltage of the NMOS transistor  206  can be equal to the reference voltage V SET . By ignoring a gate current of the NMOS transistor  206  and an inverting input current of the OPA  202 , a first reference current I REF1  can be generated according to equation (1). 
         [0000]        I   REF1   =V   SET   /R   210   (1) 
         [0000]    R 210  represents a resistance of the resistor  210 . 
         [0018]    Furthermore, a second reference voltage V SET ′ is provided to a non-inverting input terminal of an amplifier  204 , e.g., an operational amplifier (OPA). In one embodiment, the second reference voltage V SET ′ can be equal to the first reference voltage V SET . Moreover, an inverting input terminal and an output terminal of the OPA  204  are respectively coupled to a source terminal and a gate terminal of a transistor  208 , e.g., a NMOS transistor. In addition, a resistor  212  is coupled between the source terminal of the NMOS transistor  208  and ground. 
         [0019]    Similarly, an inverting input voltage of the OPA  204  is equal to a non-inverting input voltage of the OPA  204 , and therefore a source voltage of the NMOS transistor  208  can be equal to the reference voltage V SET . By ignoring a gate current of the NMOS terminal  208  and an inverting input current of the OPA  204 , a second reference current I REF2  can be generated according to equation (2). 
         [0000]        I   REF2   =V   SET   ′/R   212   =V   SET   /R   212   (2) 
         [0000]    R 212  represents a resistance of the resistor  212 . 
         [0020]    In one embodiment, the battery charging system  200  further includes a first current mirror formed by transistors  214  and  216 , e.g., P-Metal-Oxide-Semiconductor (PMOS) transistors. The PMOS transistors  214  and  216  are matched or identical in one embodiment. The first current mirror is coupled between the NMOS transistor  206  and a transistor  218 , e.g., a PNP transistor. A base terminal and a collector terminal of the PNP transistor  218  are connected to ground. The battery charging system  200  also includes a second current mirror formed by transistors  220  and  222 , e.g., PMOS transistors. The PMOS transistors  220  and  222  are matched or identical in one embodiment. The second current mirror is coupled between the NMOS transistor  208  and a transistor  224 , e.g., a PNP transistor. The PNP transistor  224  is cascaded with the PNP transistor  218  since a base terminal of the PNP transistor  224  is connected to an emitter terminal of the PNP transistor  218 . A collector terminal of the PNP transistor  224  is connected to ground. 
         [0021]    By ignoring the base currents of the PNP transistor  218  and  224 , a current I REF1 ′ flowing through the PNP transistor  218  can be equal to the first reference current I REF1 . Thus, an emitter-base voltage V EB1  of the PNP transistor  218  can be given according to equation (3). 
         [0000]        V   EB1   =V   T *ln( I   REF1   ′/I   S )= V   T *ln( I   REF1   /I   S )  (3) 
         [0000]    V T  represents a thermal voltage of each PNP transistor, e.g., the PNP transistors  218  and  224 , at a given temperature. I S  represents a reverse saturation current of a base-emitter diode in each PNP transistor, e.g., the PNP transistors  218  and  224 . 
         [0022]    Similarly, by ignoring the base current of the PNP transistor  224 , a current I REF2 ′ flowing through the PNP transistor  224  can be equal to the second reference current I REF2 . Thus, an emitter-base voltage V EB2  of the PNP transistor  224  can be given according to equation (4). 
         [0000]        V   EB2   =V   T *ln( I   REF2   ′/I   S )= V   T *ln( I   REF2   /I   S )  (4) 
         [0023]    Since the base terminal of the PNP transistor  218  is connected to ground and the base terminal of the PNP transistor  224  is connected to the emitter terminal of the PNP transistor  218 , an emitter voltage V A  of the PNP transistor  224  can be given according to equation (5). 
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         [0024]    In one embodiment, the battery charging system  200  further includes a charging current sensor  230 , e.g., a PMOS transistor, coupled to a charging switch  252 , e.g., a charging field effect transistor (FET). In one embodiment, the charging FET  252  can be a PMOS transistor. A gate terminal and a source terminal of the charging FET  252  are connected with a gate terminal and a source terminal of the PMOS transistor  230 , respectively. Thus, the charging FET  252  and the PMOS transistor  230  have the same gate-source driving voltage. In one embodiment, the PMOS transistor  230  is K times smaller than the charging FET  252 . Thus, a current I SEN  can be K times smaller than a charging current I CHG  if a short-channel modulation effect is ignored. The current I SEN  can be given by equation (6). 
         [0000]        I   SEN   =I   CHG   /K   (6) 
         [0025]    The battery charging system  200  further includes an amplifier  234 , e.g., an operational transconductance amplifier (OTA), with a transconductance gain. In one embodiment, the transconductance gain of the OTA  234  can be set equal to 1/R 212 . An input voltage is provided to a non-inverting input terminal of the OTA  234  and a voltage of the battery cell  258  is provided to an inverting input terminal of the OTA  234 . The voltage difference between the input voltage and the voltage of the battery cell  258  can be converted into a bias current I DC  by the OTA  234 . The bias current I DC  can be given according to equation (7). 
         [0000]        I   DC =( V   IN   −V   BATT )* Gm =( V   IN   −V   BATT )/ R   212   (7) 
         [0000]    V IN  represents the input voltage. V BATT  represents the voltage of the battery cell  258  (in other words, a battery cell voltage). 
         [0026]    In one embodiment, a transistor  232 , e.g., a PNP transistor, is coupled to the PMOS transistor  230  for receiving the sensing current I SEN . Base and collector terminals of the PNP transistor  232  are connected to ground. Furthermore, a transistor  236 , e.g., a PNP transistor, is coupled to the OTA  234  for receiving the bias current I DC . The PNP transistor  236  is cascaded with the PNP transistor  232  since the base terminal of the PNP transistor  236  is coupled to an emitter terminal of the PNP transistor  232  and the base terminal of the PNP transistor  232  is connected to ground. 
         [0027]    By ignoring base currents of the PNP transistors  232  and  236 , a current flowing through the PNP transistor  232  can be equal to the sensing current I SEN . Thus, an emitter-base voltage V EB3  of the PNP transistor  232  can be given according to equation (8). 
         [0000]        V   EB3   =V   T *ln( I   SEN   /I   S )  (8) 
         [0000]    V T  represents a thermal voltage of each PNP transistor, e.g., the PNP transistors  218 ,  224 ,  232  and  236 , at a given temperature. I S  represents a reverse saturation current of a base-emitter diode in each PNP transistor, e.g., the PNP transistors  218 ,  224 ,  232  and  236 . 
         [0028]    Similarly, by ignoring the base current of the PNP transistor  236 , a current flowing through the PNP transistor  236  can be equal to the bias current I DC . Thus, an emitter-base voltage V EB4  of the PNP transistor  236  can be given according to equation (9). 
         [0000]        V   EB4   =V   T *ln( I   DC   /I   S )  (9) 
         [0029]    Since the base terminal of the PNP transistor  232  is connected to ground and the base terminal of the PNP transistor  236  is connected to the emitter terminal of the PNP transistor  232 , an emitter voltage V B  of the PNP transistor  236  can be given according to equation (10). 
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         [0000]    P CHG , which is equal to (V IN −V BATT )*I CHG , represents a power dissipation of the charging FET  252 . 
         [0030]    In one embodiment, the battery charging system  200  includes an error amplifier  240 , e.g., an OPA, for keeping the power dissipation P CHG  of the charging FET  252  at the predetermined power dissipation threshold P SET . A non-inverting input terminal of the OPA  240  is connected to the emitter terminal of the PNP transistor  236 , and an inverting input terminal of the OPA  240  is connected to the emitter terminal of the PNP transistor  224 . A voltage difference V DEF1  between the non-inverting input voltage V B  and the inverting input voltage V A  can be given according to equation (11). 
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         [0000]    P SET , which is equal to K*V SET   2 /R 210 , represents a predetermined power dissipation threshold of the battery charging system  200 . In one embodiment, the predetermined power dissipation threshold P SET  can be programmed by adjusting the resistance of the resistor R 210 . According to the voltage difference V DEF1 , the OPA  240  can generate a first driving current I DRV1  to the charging FET  252  through a diode  242 . 
         [0031]    In one embodiment, the battery charging system  200  also includes an error amplifier  244 , e.g., an OPA, for keeping the battery cell voltage V BATT  at a predetermined voltage threshold. In addition, a resistor  248  and a resistor  250  coupled in series are connected between a positive terminal and a negative terminal of the battery cell  258 . A non-inverting input terminal of the OPA  244  is coupled to a node between the resistor  248  and the resistor  250 . Hence, the non-inverting input voltage V C  of the OPA  244  can be given according to equation (12). 
         [0000]        V   C   =V   BATT   *R   250 /( R   248   +R   250 )  (12) 
         [0000]    R 248  represents a resistance of the resistor  248 . R 250  represents a resistance of the resistor  250 . Additionally, a reference voltage V REF  is provided to an inverting input terminal of the OPA  244 . In one embodiment, the reference voltage V REF  can be set by equation (13). 
         [0000]        V   REF   =V   PRE   *R   250 /( R   248   +R   250 )  (13) 
         [0000]    V PRE  represents the predetermined voltage threshold. 
         [0032]    Accordingly, a voltage difference V DEF2  between the non-inverting input voltage V C  and the inverting input voltage V REF  can be given according to equation (14). 
         [0000]        V   DEF2   =V   C   −V   REF =( V   BATT   −V   PRE )* R   250 /( R   248   +R   250 )  (14) 
         [0000]    According to the voltage difference V DEF2 , the OPA  244  can generate a second driving current I DRV2  to the charging FET  252  through a diode  246 . 
         [0033]    In addition, a resistor  254  is coupled between the gate terminal and the source terminal of the charging FET  252 . A source-gate voltage of the charging FET  252  can be approximately equal to a voltage across the register  254 . A constant current source  256  is coupled with the resistor  254  in series for providing a constant current I CC  to the resistor  254 . 
         [0034]    When a charger (not shown) is plugged into the battery charging system  200 , the voltage difference V DEF2  can be a negative value according to equation (14) if the voltage V BATT  of the battery cell  258  is lower than the predetermined voltage threshold. As such, the second driving current I DRV2  generated by the OPA  244  to the charging FET  252  can be very small. Thus, the second driving current I DRV2  can be ignored. Additionally, the diode  246  can prevent a reverse current from flowing to an output terminal of the OPA  244 . Accordingly, the driving current of the charging FET  252  is not affected by the OPA  244 . The charging FET  252  can be controlled mainly by the first driving current I DRV1  output from the OPA  240 . Hence, the battery cell  258  can be charged with a constant power dissipation control on the charging FET  252 . 
         [0035]    During a constant power dissipation charge period, if the power dissipation P CHG  of the charging FET  252  is greater than the predetermined power dissipation threshold P SET , the voltage difference V DEF1  can be a positive value according to equation (11). Accordingly, the first driving current I DRV1  output from the OPA  240  can be increased. Since the current I CC  is constant, a voltage drop V 254  over the resistor  254  can be decreased according to equation (15). 
         [0000]        V   254 =( I   CC   −I   DRV1 )* R   254   (15) 
         [0000]    R 254  represents a resistance of the resistor  254 . As such, the source-gate voltage of the charging FET  252  can be decreased, and thus the charging current I CHG  and the power dissipation P CHG  can be decreased. 
         [0036]    If the power dissipation P CHG  of the charging FET  252  is lower than the predetermined power dissipation threshold P SET , the voltage difference V DEF1  can be a negative value according to equation (11). Accordingly, the first driving current I DRV1  output from the OPA  240  can be decreased. Since the current I CC  is constant, the voltage drop V 254  over the resistor  254  can be increased according to equation (15). As such, the source-gate voltage of the charging FET  252  can be increased, and thus the charging current I CHG  and the power dissipation P CHG  can be increased. 
         [0037]    Consequently, the power dissipation P CHG  can be maintained at a nearly constant value. As such, a thermal issue will not occur in the battery charging system  200  during the constant power dissipation charge period. 
         [0038]    When the battery cell voltage V BATT  is near the predetermined voltage threshold, the voltage difference V DEF2  can approach zero according to equation (14). Consequently, the second driving current I DRV2  output from the OPA  244  can gradually increase and cannot be ignored. As such, the voltage drop V 254  over the resistor  254  can be given by equation (16). 
         [0000]        V   254 =( I   CC   −I   DRV1   −I   DRV2 )* R   254   (16) 
         [0000]    If the second driving current I DRV2  is still increased, the voltage drop V 254  can be decreased. The charging current I CHG  can also be decreased. The power dissipation P CHG  can be decreased, which results in a decrease of the non-inverting input voltage V B  of the OPA  240 . As such, the first driving current I DRV1  generated by the OPA  240  can be decreased. Since the second driving current I REF2  increases while the first driving current I DRV1  decreases, the voltage drop V 254  cannot be increased with respect to a decrease of the first driving current I DRV1 . As such, the first driving current I DRV1  can be gradually decreased when the battery cell voltage V BATT  approaches the predetermined voltage threshold. 
         [0039]    When the battery cell voltage V BATT  is equal to or greater than the predetermined voltage threshold, the first driving current I DRV1  output from the OPA  240  can be very small. Thus, the first driving current I DRV1  can be ignored. Additionally, the diode  242  can prevent a reverse current from flowing to the OPA  240 . Then the charging FET  252  can be controlled mainly by the second driving current I DRV2  outputted from the OPA  244 . As such, the battery cell  258  can be charged under a constant voltage control. Accordingly, a smooth transition from the constant power dissipation control to the constant voltage control can be achieved. 
         [0040]    During a constant voltage charge period, if the battery cell voltage V BATT  increases above the predetermined voltage threshold, the voltage difference V DEF2  can be a negative value according to equation (14). As such, the second driving current I DRV2  generated by the OPA  244  can be increased. Since the current I CC  is constant, the voltage drop V 254  over the resistor  254  calculated by equation (17) can be decreased. 
         [0000]        V   254 =( I   CC   −I   DRV2 )* R   254   (17) 
         [0000]    As such, the source-gate voltage of the charging FET  252  can be decreased and thus the charging current I CHG  can be decreased. While the charging current I CHG  is decreased, the battery cell voltage V BATT  can be increased more and more slowly. As such, the battery cell voltage V BATT  can be kept nearly equal to the predetermined voltage threshold V PRE . 
         [0041]    In addition, when the first driving current I DRV1  and the second driving current I DRV2 , generated by the OPA  240  and the OPA  244  respectively, are close to zero, the voltage drop V 254  over the resistor  254  is equal to I CC *R 254 . The input voltage of each charger is a constant value within a voltage range, e.g., from 4.5 v to 5.5 v, and the value of I CC *R 254  can be set equal to the maximum value in the range, e.g., 5.5 v. Hence, the charging FET  252  can be regulated within a corresponding range. 
         [0042]    Advantageously, when the battery cell voltage V BATT  is lower than the predetermined voltage threshold, the battery charging system  200  can implement constant power dissipation control on the charging FET  252 . When the battery cell voltage V BATT  is equal to or greater than the predetermined voltage threshold, the battery charging system  200  can implement constant voltage control on the battery cell  258 . As illustrated in  FIG. 1 , during the constant current charge period, a thermal issue may occur in a conventional battery charging system if a voltage difference between an input voltage of a power source, e.g., an AC adapter of a USB port, and a battery cell voltage is relatively large. Compared with a conventional battery charging system, a thermal issue will not occur in the battery charging system  200  during a whole charge period even if the voltage difference between the input voltage of the power source and the battery cell voltage V BATT  is relatively large. Moreover, the battery charging system  200  can be used for charging an over-drained battery cell. When the battery cell voltage V BATT  is relatively low, the charging current can be also relatively low to precharge the battery cell  258 . In addition, when the battery cell voltage V BATT  rises, the charging current can also increase until the power dissipation P CHG  of the charging FET  252  reaches the predetermined power dissipation threshold P SET . Thus, the overall charging speed can be relatively fast. 
         [0043]      FIG. 3  illustrates a block diagram of an example of a battery charging system  300  with power dissipation control, in accordance with one embodiment of the present invention. Elements that are labeled the same as in  FIG. 2  have similar functions and will not be repetitively described herein.  FIG. 3  is described in combination with  FIG. 2 . 
         [0044]    In  FIG. 3 , a transistor  318 , e.g., an NPN transistor, is coupled with the NMOS transistor  206  for receiving the reference current I REF1 . Furthermore, a transistor  324 , e.g., an NPN transistor, is coupled with the NMOS transistor  208  for receiving the reference current I REF2 . A base terminal and a collector terminal of the NPN transistor  318  are connected to the input voltage V IN . A base terminal of the NPN transistor  324  is connected to an emitter terminal of the NPN transistor  318 . Thus, the NPN transistor  324  is cascaded with the NPN transistor  318 . A collector terminal of the NPN transistor  324  is connected to the input voltage V IN . 
         [0045]    The base currents of the NPN transistor  318  and  324  can be ignored, and therefore a current flowing through the NPN transistor  318  can be equal to the first reference current I REF1 . Thus a base-emitter voltage V BE1  of the NPN transistor  318  can be given according to equation (18). 
         [0000]        V   BE1   =V   T *ln( I   REF1   /I   S )  (18) 
         [0000]    V T  represents a thermal voltage of each NPN transistor, e.g., the NPN transistors  318  and  324 , for a given temperature in the battery charging system  300 . I S  represents a reverse saturation current of a base-emitter diode in each NPN transistor, e.g., the NPN transistors  318  and  324 . 
         [0046]    Similarly, the base current of the NPN transistor  324  can be ignored, and therefore a current flowing through the NPN transistor  324  can be equal to the second reference current I REF2 . Thus a base-emitter voltage V BE2  of the NPN transistor  324  can be given according to equation (19). 
         [0000]        V   BE2   =V   T *ln( I   REF2   /I   S )  (19) 
         [0047]    Since the base terminal of the NPN transistor  318  is connected to the input voltage V IN  and the base terminal of the NPN transistor  324  is connected to the emitter terminal of the NPN transistor  318 , an emitter voltage V A  of the NPN transistor  324  can be given according to equation (20). 
         [0000]        V   A   =V   IN −( V   BE1   +V   BE2 )= V   IN −( V   T *ln( P   SET )− V   T *ln( K*R   212   *I   S   2 ))  (20) 
         [0000]    P SET , which is equal to K*V SET   2 /R 210 , represents a predetermined power dissipation threshold of the battery charging system  300 . In one embodiment, the predetermined power dissipation threshold P SET  can be programmable by adjusting the resistance of the resistor R 210 . 
         [0048]    In one embodiment, the battery charging system  300  includes a first current mirror formed by transistors  314  and  316 , e.g., NMOS transistors. The transistors  314  and  316  are matched or identical in one embodiment. The first current mirror is coupled between the PMOS transistor  230  and a transistor  332 , e.g., an NPN transistor. A base terminal and a collector terminal of the NPN transistor  332  are connected to the input voltage V IN . The battery charging system  300  further includes a second current mirror formed by transistors  320  and  322 , e.g., NMOS transistors. The transistors  320  and  322  are matched or identical in one embodiment. The second current mirror is coupled between the output terminal of the OTA  234  and a transistor  336 , e.g., an NPN transistor. The NPN transistor  336  is cascaded with the NPN transistor  332  since a base terminal of the NPN transistor  336  is connected to an emitter terminal of the NPN transistor  332 . A collector terminal of the NPN transistor  336  is connected to the input voltage V IN . 
         [0049]    The base currents of the NPN transistor  332  and the NPN transistor  336  can be ignored, in which case a current I SEN ′ flowing through the NPN transistor  332  can be equal to the sensing current I SEN  flowing through the NMOS transistor  314 . Thus, a base-emitter voltage V BE3  of the NPN transistor  332  can be given according to equation (21). 
         [0000]        V   BE3   =V   T *ln( I   SEN   ′/I   S )= V   T *ln( I   SEN   /I   S )  (21) 
         [0000]    V T  represents a thermal voltage of each transistor, e.g., the NPN transistors  318 ,  324 ,  332  and  336 , for a given temperature in the battery charging system  300 . I S  represents a reverse saturation current of a base-emitter diode in each transistor, e.g., the NPN transistors  318 ,  324 ,  332  and  336 . 
         [0050]    Similarly, the base current of the NPN transistor  336  can be ignored, in which case a current I DC ′ flowing through the NPN transistor  336  can be equal to the bias current I DC  flowing through the NMOS transistor  320 . Thus, a base-emitter voltage V BE4  of the NPN transistor  336  can be given according to equation (22). 
         [0000]        V   BE4   =V   T *ln( I   DC   ′/I   S )= V   T *ln( I   DC   /I   S )  (22) 
         [0051]    Since the base terminal of the NPN transistor  332  is connected to the input voltage V IN  and the base terminal of the NPN transistor  336  is connected to the emitter terminal of the NPN transistor  332 , an emitter voltage V B  of the NPN transistor  326  can be given according to equation (23). 
         [0000]        V   B   =V   IN −( V   BE3   +V   BE4 )= V   IN −( V   T *ln( P   CHG )− V   T *ln( K*R   212   *I   S   2 )  (23) 
         [0000]    P CHG , which is equal to (V IN −V BATT )*I CHG , represents a power dissipation of the charging FET  252 . 
         [0052]    In one embodiment, the non-inverting input terminal of the OPA  240  is coupled to an emitter terminal of the NPN transistor  324 . The inverting input terminal of the OPA  240  is coupled to an emitter terminal of the NPN transistor  336 . Accordingly, a voltage difference V DEF1  between the non-inverting input voltage V B  and the inverting input voltage V A  can be given according to equation (24). 
         [0000]        V   DEF1   =V   B   −V   A   =V   T *ln( P   CHG )− V   T *ln( P   SET )  (24) 
         [0000]    According to the voltage difference V DEF1 , the OPA  240  can generate a first driving current I DRV1  to the charging FET  252  through the diode  242 . 
         [0053]    Accordingly, the battery charging system  300  can utilize the same processes as the battery charging system  200  in  FIG. 2  to implement constant power dissipation control on the charging FET  252  and/or a constant voltage control on the battery cell  258 . 
         [0054]      FIG. 4  illustrates a charging profile  400  of a battery charging system, e.g., the battery charging system  200  in  FIG. 2 , during the whole charging process, in accordance with one embodiment of the present invention.  FIG. 4  is described in combination with  FIG. 2 . The charging profile  400  includes a power dissipation profile  402  of the charging FET  252 , a charging current profile  404  of the battery cell  258 , and a voltage profile  406  of the battery cell  258 . The power dissipation profile  402  can vary with the charging current profile  404  and the voltage profile  406 . 
         [0055]    When a charger is plugged into the battery charging system  200 , the voltage difference V DEF2  can be a negative value according to equation (14) if the voltage V BATT  of the battery cell  258  is lower than a predetermined voltage threshold V PRE . Thus, a second driving current I DRV2  outputted from the OPA  244  to the charging FET  252  can be small and the second driving current I DRV2  can be ignored. Accordingly, the charging FET  252  can be controlled mainly by the first driving current I DRV1  output by the OPA  240 . Hence, the battery cell  258  can be charged with a constant power dissipation control on the charging FET  252 . 
         [0056]    During the constant power dissipation charge period, when the battery cell voltage V BATT  is relatively low, the charging current I CHG  is also small to keep the power dissipation P CHG  of the charging FET  252  approximately equal to the predetermined power dissipation threshold P SET . With the increase of the battery cell voltage V BATT , the charging current can also increase to keep the power dissipation P CHG  approximately equal to the predetermined power dissipation threshold P SET . 
         [0057]    When the battery cell voltage V BATT  is near the predetermined voltage threshold V PRE  marked in  FIG. 4 , the voltage difference V DEF2  can approach zero according to equation (14). As a result, the second driving current I DRV2  is gradually increased and cannot be ignored any more. Concurrently, the first driving current I DRV1  generated by the OPA  240  can be gradually decreased. When the voltage V BATT  of the battery cell  258  reaches the predetermined voltage threshold V PRE , the first driving current I DRV1  can be decreased until it is relatively small and can be ignored. Hence, the charging FET  252  can be controlled mainly by the second driving current I DRV2  output from the OPA  244  and the battery cell  258  can be charged under a constant voltage control. 
         [0058]    During the constant voltage charge period, the charging current I CHG  gradually decreases to zero. Thus, the battery cell voltage V BATT  can be increased more and more slowly. As such, the battery cell voltage V BATT  can be kept approximately equal to the predetermined voltage threshold V PRE . Concurrently, the power dissipation P CHG  also decreases with the charging current I CHG  since the battery cell voltage V BATT  is nearly constant. 
         [0059]      FIG. 5  illustrates a flowchart  500  of operations performed by a battery charging system, e.g., the battery charging system  200  in  FIG. 2 , in accordance with one embodiment of the present invention.  FIG. 5  is described in combination with  FIG. 2 . 
         [0060]    In block  502 , the battery charging system starts to generate a charging current to a battery, e.g., the battery cell  258 , via the charging switch  252 . If a voltage V BATT  of the battery is less than a predetermined voltage threshold V PRE  (block  504 ), the power dissipation P CHG  of the charging switch  252  can be compared with a predetermined power dissipation threshold P SET , in block  506 . In block  508 , a charging current I CHG  flowing through the charging switch  252  can be adjusted according to the comparison result to keep the power dissipation P CHG  of the charging switch  252  constant. 
         [0061]    In one embodiment, a driving current can be generated to the charging switch  252  according to the comparison result. If the power dissipation P CHG  of the charging switch  252  is greater than the predetermined power dissipation threshold P SET , the charging current I CHG  can be decreased by the driving current. If the power dissipation P CHG  of the charging switch  252  is smaller than the predetermined power dissipation threshold, the charging current I CHG  can be increased by the driving current. 
         [0062]    In block  510 , the voltage V BATT  of the battery can be compared with the predetermined voltage threshold V PRE , if the voltage V BATT  of the battery is equal to or greater than the predetermined voltage threshold V PRE  (block  504 ). In block  512 , the charging current I CHG  flowing through the charging switch  252  can be adjusted according to the comparison result to control the voltage V BATT  of the battery (e.g., keep it constant or nearly so). 
         [0063]    In one embodiment, a driving current can be generated to the charging switch  252  according to the comparison result. If the voltage V BATT  of the battery is greater than the predetermined voltage threshold V PRE , the charging current I CHG  can be decreased by the driving current. 
         [0064]      FIG. 6  illustrates a flowchart  600  of a method of comparing power dissipation of a charging switch with a predetermined power dissipation threshold in a battery charging system, e.g., the battery charging system  200  in  FIG. 2 , in accordance with one embodiment of the present invention.  FIG. 6  is described in combination with  FIG. 5  and  FIG. 2 . 
         [0065]    In block  602 , a first current I 1  that varies with the charging current flowing through the charging switch  252  is generated, as given by equation (25). 
         [0000]        I   1   =I   CHG   /K   (25) 
         [0000]    I CHG  represents the charging current flowing through the charging switch  252 . K represents a scaling parameter based on the relative sizes of the charging switch  252  and the current sensor  230 . In one embodiment, the first current I 1  can be generated by the current sensor  230  (e.g., a PMOS transistor) with source and gate terminals respectively connected to the source and gate terminals of the charging switch  252 . Since the size of the PMOS transistor  230  is K times smaller than the size of the charging switch  252 , the first current I 1  can be K times smaller than the charging current I CHG  if the short-channel modulation effect is ignored. 
         [0066]    In block  604 , a voltage across the charging switch  252  can be converted into a second current I 2  by equation (26). 
         [0000]        I   2 =( V   IN   −V   BATT )* Gm =( V   IN   −V   BATT )/ R   212   (26) 
         [0000]    G m  represents a conversion parameter. In one embodiment, the second current I 2  can be generated by an amplifier, e.g., the OTA  234 , coupled between the source terminal and the drain terminal of the charging switch  252 . A transconductance gain of the OTA  234  is set as the value of the conversion parameter Gm. 
         [0067]    In block  606 , a first voltage V EB1  across an emitter and a base of a transistor, e.g., the PNP transistor  232 , is generated according to the first current I 1  by equation (27), 
         [0000]        V   EB1   =V   T1 *ln( I   1   /I   S1 )  (27) 
         [0000]    V T1  represents a thermal voltage of the PNP transistor  232  at a given temperature. I S1  represents a reverse saturation current of a base-emitter diode of the PNP transistor  232 . 
         [0068]    In block  608 , a second voltage V EB2  across an emitter and a base of a transistor, e.g., the PNP transistor  236 , is generated according to the second current I 2  by equation (28). 
         [0000]        V   EB2   =V   T2 *ln( I   2   /I   S2 )  (28) 
         [0000]    V T2  represents a thermal voltage of the PNP transistor  236  at a given temperature. I S2  represents a reverse saturation current of a base-emitter diode of the PNP transistor  236 . The V T2  is equal to the V T1 . The I S2  is equal to the I S1 . 
         [0069]    In block  610 , a third voltage V EB3  across an emitter and a base of a transistor, e.g., the PNP transistor  218 , is generated according to a first reference current I REF1  by equation (29). 
         [0000]        V   BE3   =V   T3 *ln( I   REF1   /I   S3 )  (29) 
         [0000]    V T3  represents a thermal voltage of the PNP transistor  218  at a given temperature. I S3  represents a reverse saturation current of a base-emitter diode of the PNP transistor  218 . The V T3  is equal to the V T1 . The I S3  is equal to the I S1 . 
         [0070]    In block  612 , a fourth voltage V EB4  across an emitter and a base of a transistor, e.g., the PNP transistor  224 , is generated according to a second reference current I REF2  by equation (30). 
         [0000]        V   EB4   =V   T4 *ln( I   REF2   /I   S4 )  (30) 
         [0000]    V T4  represents a thermal voltage of the PNP transistor  224  at a given temperature. I S4  represents a reverse saturation current of a base-emitter diode of the PNP transistor  224 . The V T4  is equal to the V T1 . The I S4  is equal to the I S1 . 
         [0071]    Then in block  614 , a voltage difference V DIF  can be calculated by equation (31). 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
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                             ) 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   31 
                   ) 
                 
               
             
           
         
       
     
         [0000]    P CHG , which is equal to I GHG *(V IN −V BATT ), represents the power dissipation of the charging FET  252 . P SET  that is equal to I REF1 *I REF2  represents the predetermined power dissipation threshold. 
         [0072]    In block  616 , the power dissipation P CHG  of the charging switch  252  can be compared with the predetermined power dissipation threshold P SET  according to the voltage difference V DIF . If the voltage difference V DIF  is a positive value, the power dissipation P CHG  of the charging switch  252  is greater than the predetermined power dissipation threshold P SET . If the voltage difference V DIF  is a negative value, the power dissipation P CHG  of the charging switch  252  is smaller than the predetermined power dissipation threshold P SET . 
         [0073]    Accordingly, battery charging systems, e.g., the battery charging systems  200  and  300  in  FIG. 2  and  FIG. 3 , are disclosed herein. In one embodiment, the battery charging system includes a charging switch  252  to control a charging current flowing through the charging switch  252 , and a first error amplifier  240  coupled to the charging switch  252 . The first error amplifier  240  is used for adjusting the charging current to keep the power dissipation of the charging switch  252  relatively constant if a voltage of the battery is lower than a predetermined voltage threshold. The battery charging system can also include a second error amplifier  244  coupled to the charging switch  252 . The second error amplifier  244  is used for adjusting the charging current to keep the voltage of the battery relatively constant if the voltage of the battery is equal to or greater than the predetermined voltage threshold. Furthermore, the battery charging systems can be used for charging multiple batteries. 
         [0074]    If the voltage of the battery is lower than a predetermined voltage threshold, the battery cell  258  can be charged with constant power dissipation control on the charging switch  252 . The first error amplifier  240  can compare the power dissipation of the charging switch  252  with a predetermined power dissipation threshold and generate a driving current to the charging switch  252  according to the power dissipation comparison result. If the power dissipation P CHG  of the charging switch  252  is greater than the predetermined power dissipation threshold, the charging current I CHG  flowing through the charging switch  252  can be decreased by the driving current. If the power dissipation P CHG  of the charging switch  252  is smaller than the predetermined power dissipation threshold, the charging current I CHG  flowing through the charging switch  252  can be increased by the driving current. 
         [0075]    If the battery cell voltage is equal to or greater than the predetermined voltage threshold, the battery cell  258  can be charged under constant voltage control. The second error amplifier  244  can compare the voltage of battery with the predetermined voltage threshold and generate a driving current to the charging switch  252  according to the voltage comparison result. If the battery cell voltage V BATT  is greater than the predetermined voltage threshold V PRE , the charging current I CHG  can be decreased by the driving current. 
         [0076]    Advantageously, there will not be a thermal issue in the battery charging system  200  or  300  during a whole charge period even if the voltage difference between the voltage of the power source and the battery cell voltage V BATT  is large. Moreover, the battery charging system can be used for charging an over-drained battery cell. When the voltage of the battery is very low, the charging current can be small to precharge the battery. In addition, when the voltage of the battery rises, the charging current can also increase until the power dissipation of the charging switch reaches the predetermined power dissipation threshold. Thus the overall charging speed can be fast. 
         [0077]    The embodiments that have been described herein, however, are but some of the several that utilize this invention and are set forth here by way of illustration but not of limitation. It is obvious that many other embodiments, which will be readily apparent to those skilled in the art, may be made without departing materially from the spirit and scope of the invention as defined in the appended claims. Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.