Abstract:
Receipt of a training signal by a circuit wherein a demodulated data sequence is compared with a corresponding pre-recorded sequence and an impulse produced upon coincidence therebetween, is acknowledged by two consecutive signals occuring at a time interval corresponding to the period of the data sequence.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a method and circuit for detecting a training signal which is transmitted for initial adjustment of the equalizing characteristics of an automatic equalizer provided in a Modem (Modulator-Demodulator). 
     2. Description of the Prior Art 
     In a Modem having therein an automatic equalizer, it is a common practice to transmit a training signal, prior to the transmission of message data, to a receiving Modem for initial adjustment of the automatic equalizer with respect to channel characteristics. The CCITT (International Consultative Committee for Telephone and Telegraph) has proposed such a training signal in &#34;Recommendation V.27 bis&#34;. This signal consists of three segments which precede the message data in a manner schematically shown in FIG. 1. The first segment is composed of continuous 180° phase reversals for 14 symbol intervals, the second segment of 0°-180° 2-phase equalizer conditioning pattern for 58 symbol intervals, and the third segment of continuous scrambled ONEs for 8 symbol intervals. 
     Such a training signal however consumes a large amount of time for initial adjustment of the automatic equalizer and hence the efficiency of a data transmission system is seriously limited especially when the adjusting time approaches or exceeds the actual message time. 
     In order to overcome this problem, another training signal has been proposed in the European Patent Application publication No. A1 0052362. This training signal is composed of at least two periodic data sequences (maximum length sequences) each having a period L and is such that the autocorrelation function of the sequence assumes an impulse. This training signal will be described in more detail hereinlater. 
     SUMMARY OF THE INVENTION 
     The object of this invention is to provide a method and circuit for effectively detecting the training signal as disclosed in the above mentioned application. 
     According to one aspect of this invention, the present invention takes the form of a method of detecting a training signal for use in initial adjustment of an automatic equalizer with respect to channel characteristics, comprising the steps of: (a) receiving and shifting a demodulated training signal in synchronism with data modulating rate, the training signal comprising at least two periodic data sequences each having a period L and the autocorrelation function of the periodic data sequence assumes an impulse; (b) calculating the correlation between the demodulated training signal and a first periodic data sequence with the period L, and obtaining a first square value indicative of the correlation; (c) calculating the correlation between the demodulated training signal and a second periodic data sequence and obtaining a second square value indicative of the correlation, wherein the second periodic data sequence is circulated in synchronism with the data modulating rate and has the same sequence as the first data sequence; (d) dividing the first square value by the second square value; (e) comparing the quotient obtained in the step (d) with a first and second threshold values; (f) setting the order of the second periodic data sequence to the order of the first periodic data sequence shifted by one, if the quotient exceeds the second threshold value; (g) producing a signal if the quotient exceeds the first threshold value; and (h) detecting the presence of the training signal by detecting sequential signals occuring at a time interval equal to the period L. 
     According to another aspect of this invention, the present invention takes the form of a circuit for detecting a training signal for use in initial adjustment of an automatic equalizer with respect to channel characteristics, comprising: a first means for receiving and shifting a demodulated training signal in synchronism with data modulating rate, the training signal comprising at least two periodic data sequences each having a period L and the autocorrelation function of the periodic data sequence assumes an impulse; a second means for calculating the correlation between the demodulated training signal and a first periodic data sequence with the period L, and obtaining a first square value indicative of the correlation; a third means for calculating the correlation between the demodulated training signal and a second periodic data sequence and obtaining a second square value indicative of the correlation, wherein the second periodic data sequence is circulated in synchronism with the data modulating rate and has the same sequence as the first data sequence; a fourth means for dividing the first square value by the second square value; a fifth means for comparing the quotient produced by the fourth means with a first and second threshold values; a sixth means for setting the order of the second periodic data sequence to the order of the first periodic data sequence shifted by one, if the quotient exceeds the second threshold value; a seventh means for producing a signal if the quotient exceeds the first threshold value; and an eighth means for detecting the presence of the training signal by detecting sequential signals occuring at a time interval equal to the period L. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the present invention will become more clearly appreciated from the following description taken in conjunction with the accompanying drawings in which like blocks or circuits are denoted by like reference numerals and in which: 
     FIG. 1 shows in schematic form the known training signal and message data discussed in the opening paragraphs of the present disclosure; 
     FIGS. 2(a) and 2(b) show examples wherein (a) the demodulated signal and prestored data coincide to produce a signal for detection of a training signal being received and (b) the coincidence is not achieved; 
     FIG. 3 shows in block diagram form a circuit according to the present invention; 
     FIG. 4 is a time chart showing schematically (a) two periodic data sequences, (b) the output of a first correlation circuit, (c) the output of a second correlation circuit and (d) the resulting output of a comparator operatively connected with the aforementioned correlation circuits; 
     FIG. 5 is a time chart similar to that shown in FIG. 4 but which illustrates the operation which occurs when a deviation occurs in the demodulated signal; 
     FIGS. 6 and 7 show complex planes which illustrate the real and the imaginary parts of the correlation and the distance which occurs as a result of noncoincidence between the demodulated signal and prestored data; and 
     FIG. 8 is a flow chart illustrating a program which may be employed in a microprocessor forming part of a second embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The principle underlying this invention will first be discussed. 
     The training signal which the present invention utilizes is comprised of at least two periodic data sequences each having a period L and wherein the autocorrelation function of the sequence assumes an impulse. More specifically, the periodic data sequence (maximum length sequence) is represented by way of example: 
     (for L=15) Q Q Q P P P P Q P Q P P Q Q P 
     (for L=23) QQQQPPPPPQPQPPQQPPQQPQP 
     wherein if the data Q and P are respectively assigned to data points on a complex plane (see FIGS. 6 and 7) such that the data Q is ((Real Part: Re), (Imaginary Part: Im))=(q, 0) and the data P is (Re, Im)=(p, 0) where: ##EQU1## then, the autocorrelation function ρ (i) of the sequence becomes ##EQU2## Further, if θ is the phase deviation between the modulated and demodulated carriers, then we have ##EQU3## 
     Under these conditions, from the equations (2) and (3), we obtain the correlation between the demodulated data sequence and the known periodic data sequence with the period L: ##EQU4## Accordingly, the sum of the squares of the real and imaginary parts for each of i=0 and ≠0 of the equation (4) becomes ##EQU5## FIGS. 2(a) and 2(b) are respective illustrations wherein i=0 and i≠0 in equation (5). 
     It is therefore understood from the equation (5) that the sum of the squares of the real and imaginary parts of the correlation assumes: 
     (a) a maximum value L 2  when the demodulated training signal coincides with the predetermined periodic data sequence (i.e. when i=0); and 
     (b) &#34;0&#34; in the other cases (i.e. when i≠0). 
     The preferred embodiment of this invention is hereinafter described with reference to FIGS. 3 through 5. 
     FIG. 3 is a block diagram of the circuit arrangement according to this invention and FIGS. 4 and 5 are waveforms explaining the operation of the FIG. 3 arrangement. 
     The arrangement of FIG. 3 generally comprises a shift register 10 for receiving a demodulated signal via an input terminal 12, first and second correlation circuits 14 and 16, a divider 18, first and second comparators 20 and 22, a detector 24, and an output terminal 26 of the arrangement, all of which are coupled as shown. 
     The shift register 10 is provided with L shift stages (viz., a number corresponding to the length of a periodic data sequence M i  which is further described later) and successively receives and shifts the demodulated data sequence D i  (wherein D i  is a complex number and i=0, 1, . . . , L-1) in synchronism with the data modulation rate. The first correlation circuit 14 comprises L multipliers M P0  through MP L-1 , an adder 28, a square circuit 30 and a memory means 32 (a ROM for example) in which the first periodic data sequence M i  with the period L (wherein M i  is a real number, and i=0, 1, . . . , L-1) is previously stored. The correlation circuit 14 calculates the square of the distance of the correlation between the modulated data sequence D i  and the periodic data sequence M i . More specifically, the correlation circuit 14 calculates the following value: ##EQU6## The second correlation circuit 16 comprises L multipliers MP&#39; 0  through MP&#39; L-1 , an adder 34, a square circuit 36, and a circulating register 38 in which a periodic data sequence M i  &#39; having the period L (wherein M i  &#39; is a real number and i=0, 1, . . . , L-1) is stored. The circulating register 38 shifts and circulates the stored data sequence M i  &#39; in synchronism with the modulating rate. It should be noted that the sequence order of the data sequence M i  &#39; is equal to one of the circulated orders of the data sequence M i . The correlation circuit 16 calculates the square of the distance of the correlation between the modulated data sequence D i  and the periodic data sequence M i  &#39;. More specifically, the correlation circuit 16 calculates the following value: ##EQU7## 
     The divider 18 divides the output of the correlation circuit 14 by that of the second correlation circuit 16 and applies the result to the comparators 20 and 22. The comparator 20 compares the output of the divider 18 with a first threshold value and generates a logic &#34;1&#34; if the output of the divider 18 exceeds the threshold value. While, the comparator 22 compares the output of the divider 18 with a second threshold value. If the output of the divider 18 exceeds the second threshold value, the comparator 22 supplies the circulating register 38 with a control signal. The register 38 is responsive to the applied control signal and is set to a predetermined sequence order which corresponds to the order of the fixed data sequence M i  but which has been shifted by one. 
     The operation of the FIG. 3 arrangement will be described in more detail with reference to FIGS. 4 and 5. 
     Each of the memory elements or shift stages of the shift register 10 is initially set to &#34;0&#34;. A training signal consisting of more than two periodic data sequences M i  each having the period L, is demodulated and applied to the shift register 10 in synchronism with the data modulation rate, i.e. in each modulation time slot. The demodulated training signal is represented as a periodic data sequence D i  (i=L-1, . . . , 1, 0) in FIG. 4(a). The first correlation circuit 14 outputs the maximum values Ymax at each period L (i.e. at time points t 1 , t 2 , . . . ) as shown in FIG. 4(b). When the first correlation circuit 14 outputs the first maximum value Ymax at t 1 , divider 18 generates a signal with a magnitude exceeding the threshold values of both comparators 20 and 22. Thus, the comparator 20 produces a logic &#34;1&#34; denoted by Q1 (FIG. 4(d)), while the comparator 22 applies the aforementioned control signal to the circulating register 38 and induces the circulating register 38 to assume the aforementioned sequence order. Therefore, the second correlation circuit 16 continuously generates the maximum value Ymax because the comparator 22 no longer produces the control signal. When the correlation circuit 14 produces the second Ymax at t2, the comparator 20 generates a logic &#34;1&#34; (Q2) in response to the Ymax. The detector 24 coupled to the comparator 20 detects the presence of the training signal by detecting sequentially logic &#34;1&#34;s which occur with the time interval L therebetween. 
     It will be noted that during the period that the intially 37 0&#34; set memory elements are being one by one filled with demodulated data, the output of the correlation circuits 14 and 16 are not zero and fluctuate within the hatched zones 50, 52 and thus assume what shall be referred to as &#34;low&#34; values. Accordingly, the output of the comparator 20 fluctuates between &#34;1&#34; and &#34;0&#34; (as shown by the hatched zone 54) depending on the magnitude of the outputs of the correlation circuits 14 and 16 within the hatched zones 50, 52. These output fluctuations do not adversely affect the operation according to this invention. 
     Referring now to FIG. 5, there is shown waveforms depicting the operation of the FIG. 3 arrangement in the event that the demodulated training signal suffers from waveform distortion. It is often the case in practice that the demodulated training signal is distorted due to a transient response such as a precursor or start-up of automatic gain control (AGC), as denoted by a reference numeral 56. The waveform distortion leads to unstabilities of the outputs of the correlation circuits 14 and 16. Under these circumstances the correlation circuit 14 may produce a large value Zmax relative to the maximum value Y&#39;max at a time point t x  when the incoming data sequence does not coincide with the data sequence M i . Under these conditions any number of possibilities may occur, however for simplicity of explanation let it be assumed that at time t x  the correlation circuit 14 outputs a high level Zmax and that the correlation circuit 16 maintains the previously mentioned &#34;low&#34; level output, then as shown in FIG. 5(d) a high level signal S1 will be outputted by the comparator 20 in the hatched zone as shown. However, as the memory elements or shift stages are still not completely full and still contain some intial &#34;0&#34; values, until after the high level signal S2, a &#34;0&#34; level output which persist for a period L cannot be expected. 
     Turning now to FIG. 8, there is shown a flowchart describing the operation in the case a microprocessor is utilized as the detecting circuit of this invention. 
     The demodulated training signal (i.e. the incoming data sequence) is successively stored in a RAM (Random Access Memory) per modulation time slot. RAMs denoted &#34;COUNT&#34; and &#34;DETECT&#34; in the flowchart are initialized to &#34;0&#34;s. The program of the FIG. 8 flowchart is executed within one modulating time slot. 
     At step 301, equation (6) is executed using the demodulated data sequence stored in the RAM and the first periodic data sequence M i  stored in the ROM. The result of the operation is stored in a RAM R1. At next step 302, the equation (7) is executed using the demodulated data sequence stored in the RAM and the second periodic data sequence M i  &#39;. The result of the operation is stored in a RAM R2. The content of the &#34;COUNT&#34; RAM (which is used in this instance as a counter RAM) is checked at step 303 to determine if it is equal to (L-1). If the answer is NO the program proceeds to step 307 to determine if (R&#39;1/R&#39;2) is less than the first threshold value &#34;TH1&#34; (for example, 0.5) of the comparator 20 (FIG. 3), wherein R&#39;1 and R&#39;2 indicate the contents of the RAMs R1 and R2 respectively. If the decision at the step 307 is YES, then the content of &#34;COUNT&#34; RAM is incremented by one at step 309 and the program goes to step 311. In the event that the answer to the question posed in step 307 is NO then the content of &#34;DETECT&#34; RAM (which in this embodiment is used as a flag RAM for indicating the presence of the training signal) is set to &#34;0&#34; at step 308 whereafter the program proceeds to step 310. 
     As will be appreciated the presence of &#34;0&#34; and &#34;1&#34; in the &#34;DETECT&#34; RAM respectively indicate the absence and the presence of the training signal. 
     Returning to step 303, if the decision thereat is YES, step 304 is executed to check if (R&#39;1/R&#39;2) is less than the first threshold value &#34;TH1&#34; similar to step 307. In the event that the answer is YES at the step 304 then &#34;0&#34; is set into the &#34;DETECT&#34; RAM at step 305 whereafter the program goes to the step 310. If No is that answer at step 304, &#34;1&#34; is set into the &#34;DETECT&#34; RAM at step 306. That is to say, the training signal is detected when (R&#39;1/R&#39;2) exceeds the first threshold value &#34;TH1&#34; after being less than &#34;TH1&#34; continuously for the program runs up until that which corresponds to (L-1). 
     At the step 310, &#34;0&#34; is set into the &#34;COUNT&#34; RAM to initalize same. 
     Thereafter, step 311 is executed to determine if (R&#39;1/R&#39;2) is less than the second threshold value &#34;TH2&#34; (for example, 1.0) of the comparator 22 (FIG. 3). In the event that the answer is YES the second periodic data sequence M i  &#39; is circulated by one at step 312. On the other hand, if the decision at the step 311 is NO, the order of the data sequence M i  &#39; is set to the sequence order equal to the fixed order of the sequence M i  but shifted by one. 
     The foregoing description shows only preferred embodiment of the present invention. Various modifications are apparent to those skilled in the art without departing from the scope of the present invention which is only limited by the appended claims.