Abstract:
A voltage controlled oscillator generates a signal having a predetermined cycle corresponding to change of an input power at a self-refresh mode of a DRAM. At the self-refresh mode for performing a refresh operation at every predetermined cycle of the DRAM, a start-up circuit unit provides a constant bias current to an oscillator unit regardless of change of the input power, thereby making the stable operation of the DRAM possible.

Description:
BACKGROUND ART  
       [0001]     1. Field of the Invention  
         [0002]     The present invention generally relates to a voltage controlled oscillator, and more specifically, to a technology of generating a signal having a predetermined cycle corresponding to change of an input voltage in a voltage controlled oscillator used at a self-refresh mode of a DRAM.  
         [0003]     2. Description of the Prior Art  
         [0004]     Generally, in a DRAM, if a predetermined time passes after data are stored, the stored data are destroyed. As a result, the stored data can be preserved by activating a bit line sense amplifier BLSA and self-refreshing the stored data at every predetermined cycle.  
         [0005]      FIG. 1  is a circuit diagram illustrating a conventional voltage controlled oscillator.  
         [0006]     The conventional voltage controlled oscillator comprises a biasing circuit unit  10  and an oscillator unit  20 .  
         [0007]     The biasing circuit unit  10 , which comprises a PMOS transistor P 1 , a NMOS transistor N 1 , resistors R 1 ˜R 5  and fuses F 1 ˜F 3 , generates bias voltages BIAS 1  and BIAS 2 .  
         [0008]     The PMOS transistor P 1 , connected between a power voltage terminal and the resistor R 1 , has a diode structure where its gate is connected to its drain. The resistors R 1 ˜R 5  are connected serially between the PMOS transistor P 1  and the NMOS transistor N 1 . The NMOS transistor N 1 , connected between the resistor R 5  and a ground voltage terminal, has a diode structure where its gate is connected to its drain. The fuses F 1 ˜F 3  are connected in parallel to resistors R 2 ˜R 4 , respectively.  
         [0009]     The oscillator unit  20  comprises a first bias unit  21 , a second bias unit  22  and an inverter unit  23 .  
         [0010]     The first bias unit  21  comprises a plurality of PMOS transistors P 2 ˜P 6  for supplying a power voltage to the inverter unit  23  depending on the bias voltage BIAS 1  applied from the biasing circuit unit  10 . The second bias unit  22  comprises a plurality of NMOS transistors N 5 ˜N 9  for supplying a ground voltage to the inverter unit  23  depending on the bias voltage BIAS 2  applied from the biasing circuit unit  10 .  
         [0011]     The inverter unit  23  is comprised of an inverter chain including the odd number of inverters (PMOS transistor P 7 , NMOS transistor N 7 ˜PMOS transistor P 11 , NMOS transistor N 11 ). An output signal from the inverter (PMOS transistor P 11 , NMOS transistor N 11 ) positioned at the final end is feedback inputted to an input terminal of the inverter (PMOS transistor P 7 , NMOS transistor N 11 ) positioned at the initial end.  
         [0012]     In the above-described conventional voltage controlled oscillator, since the PMOS transistors P 2 ˜P 6  and the NMOS transistors N 2 ˜N 6  of the oscillator unit  20  serve as load of the inverter unit  23 , its operation point is determined depending on levels of the bias voltages BIAS 1  and BIAS 2  applied from the bias circuit unit  10 .  
         [0013]     The biasing level of the PMOS transistor P 2  is determined by a drain voltage of the PMOS transistor P 1  connected with the diode type. The biasing level of the NMOS transistor N 2  is determined by a drain voltage of the NMOS transistor N 1  connected with the diode type.  
         [0014]     Current flowing in the PMOS transistors P 2 ˜P 6  and the NMOS transistors N 2 ˜N 6  is changed by regulating ratios of the resistors R 1 ˜R 5  corresponding to the selective connection state of the fuses F 1 ˜F 3 . As a result, the cycle of the oscillator can be trimmed by setting the levels of the bias voltages BIAS 1  and BIAS 2  so that the PMOS transistors P 2 ˜P 6  and the NMOS transistors N 2 ˜N 6  may be operated in a linear region.  
         [0015]     The DRAM performs a repeated self-refresh operation depending on the operation cycle of the above-described voltage controlled oscillator at a self-refresh mode. As a result, the oscillator unit  20  of the voltage controlled oscillator generates a signal having a predetermined cycle to determine the cycle of the self-refresh operation.  
         [0016]     In other words, the oscillator unit  20  determined the cycle of the self-refresh operation by regulating current required in the operation of the inverter unit  23  with the first bias unit  21  and the second bias unit  22 . The biasing circuit unit  10  determines the level of the bias voltage supplied to the oscillator  20  with the resistors R 1 ˜R 5 .  
         [0017]     However, in the conventional voltage controlled oscillator, if the level of the input power is changed by power noise generated in the internal operation of the DRAM, the level of the bias voltage supplied from the biasing circuit unit  10  is changed, so that a cycle of an output signal from the oscillator unit  20  is changed.  
         [0018]     In case of DDRII, when a power voltage is operated at a low power 1.6V, a voltage margin obtained by subtracting operation voltages of the PMOS transistor P 7  and the NMOS transistor N 7  becomes lower than threshold voltages of the PMOS transistor P 2  and the NMOS transistor N 2 . As a result, the PMOS transistor P 2  and the NMOS transistor N 2  are operated in a cut-off region.  
         [0019]     The amount of the bias current flowing in the PMOS transistor P 2  and the NMOS transistor N 2  becomes different from a value of the linear region, so that the cycle of the output signal from the oscillator unit  20  is changed.  
       SUMMARY OF THE INVENTION  
       [0020]     Accordingly, it is an object of the present invention to generate a signal having a predetermined cycle by providing a constant current to an oscillator corresponding to change of an input power.  
         [0021]     In an embodiment, a voltage controlled oscillator comprises a biasing circuit unit, a start-up circuit unit and an oscillator unit. The biasing circuit unit generates a constant bias voltage depending on a constant current value generated by a current mirror. The start-up circuit unit controls a level of the bias voltage corresponding to a voltage level of an input voltage in a self-refresh mode. The oscillator unit generates successive pulse signals each having a constant oscillating cycle depending on the bias voltage. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]     Other aspects and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:  
         [0023]      FIG. 1  is a circuit diagram illustrating a conventional voltage controlled oscillator; and  
         [0024]      FIG. 2  is a circuit diagram illustrating a voltage controlled oscillator according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0025]     The present invention will be described in detail with reference to the accompanying drawings.  
         [0026]      FIG. 2  is a circuit diagram illustrating a voltage controlled oscillator according to an embodiment of the present invention.  
         [0027]     In an embodiment, the voltage controlled oscillator comprises a biasing circuit unit  100 , a start-up circuit unit  200  and an oscillator unit  300 .  
         [0028]     Here, the biasing circuit unit  100  comprises PMOS transistors P 12 ˜P 15 , NMOS transistors N 12 ˜N 13 , resistors R 6 ˜R 9  and fuses F 4 ˜F 6 .  
         [0029]     A current mirror, which comprises the PMOS transistors P 12 ˜P 15  and the NMOS transistors N 12 ˜N 13 , serves as a constant voltage source to generate bias voltages BIAS 3  and BIAS 4 . The PMOS transistors P 12 ˜P 15  that are formed of two stages of paired transistors bias a gate voltage level at a drain voltage level of the PMOS transistor P 14 .  
         [0030]     The PMOS transistors P 12 ˜P 15  have each gate connected in common which is connected to a drain of the PMOS transistor P 14 . The NMOS transistors N 12 ˜N 13  have each gate connected in common which is connected to a drain of the NMOS transistor N 13 .  
         [0031]     The resistor R 6 ˜R 9 , connected serially between the NMOS transistor N 12  and a ground voltage terminal, regulate drain/source voltages (Vds) of the NMOS transistor N 12 . The fuses F 4 ˜F 6 , connected in parallel to both ends of the resistors R 6 ˜R 8 . As a result, a resistance value between the NMOS transistor N 12  and the ground voltage terminal is regulated depending on selective connection states of the fuses F 4 ˜F 6 .  
         [0032]     The start-up circuit unit  200  comprises a PMOS transistor P 16  and NMOS transistors N 14  and N 15  whose gates are connected in common.  
         [0033]     The PMOS transistor P 16 , connected between a power voltage terminal and the NMOS transistor N 15 , has a diode structure where its gate is connected in common to its drain. The NMOS transistor N 14 , connected between the power voltage terminal and a node ND 1 , has a gate connected in common to the PMOS transistor P 16  and the NMOS transistor N 15 .  
         [0034]     Here, a source of the NMOS transistor N 14  is connected to the gate of the NMOS transistors N 12  and N 13  to maintain a predetermined level of a voltage. The NMOS transistor N 15 , connected between the PMOS transistor P 16  and the ground voltage terminal, has a diode structure where its gate is connected in common to its drain.  
         [0035]     The oscillator unit  300  comprises a third bias unit  301 , a fourth bias unit  302  and an inverter unit  303 .  
         [0036]     The third bias unit  301  comprise a plurality of PMOS transistors P 17 ˜P 21  for supplying a power voltage to the inverter unit  303  depending on the bias voltage BIAS 3  applied from the biasing circuit unit  100 . The fourth bias unit  302  comprises a plurality of NMOS transistors N 16 ˜N 20  for supplying a ground voltage to the inverter unit  303  depending on the bias voltage BIAS 4  applied from the biasing circuit unit  100 .  
         [0037]     The inverter unit  303  is comprised of an inverter chain including the odd number of inverters (PMOS transistors P 22 , NMOS transistors N 21 ˜PMOS transistor P 26 , NMOS transistor N 25 ). An output signal from the inverter (PMOS transistor P 26 , NMOS transistor N 25 ) positioned at the final end is feedback inputted to an input terminal of the inverter (PMOS transistor P 22 , NMOS transistor N 21 ) positioned at the initial end, thereby outputting successive pulses. Also, in the inverter unit  303 , an output signal from the previous inverter is inputted to the next inverter.  
         [0038]     Hereinafter, the operation of the voltage controlled oscillator according to an embodiment of the present invention is described.  
         [0039]     The PMOS transistors P 12 ˜P 15  of the biasing circuit unit  100  has a current mirror structure, and perform a gate biasing operation with a drain voltage of the PMOS transistor P 14 . The NMOS transistors N 12  and N 13  perform a gate biasing operation with a drain voltage of the NMOS transistor N 13 .  
         [0040]     The oscillator unit  300  which comprises the odd number of inverters generates successive pulse signals by inverting an input signal. The degree of increase and decrease in a voltage level of the biasing circuit unit  100  is transmitted as input of the oscillator unit  300  to regulate the self-refresh operation of the oscillator unit  300 .  
         [0041]     As a result, the levels of the bias voltages BIAS 3  and BIAS 4  are set so that the biasing circuit unit  100  may be in a saturation region to change of an input power. That is, an operation current of the bias voltage BIAS 3  applied to the PMOS transistor P 17  is identical with current Ids flowing in the PMOS transistor P 15 . An operation current of the bias voltage BIAS 4  applied to the NMOS transistor N 16  is identical with current Ids flowing in the NMOS transistor N 13 .  
         [0042]     Since the inverter comprised of the PMOS transistor  22  and the NMOS transistor  21  is operated depending on the same current Ids value to the change of the input power, the cycle of the oscillator unit  300  becomes fixed.  
         [0043]     The PMOS transistor P 17  and the NMOS transistor N 16  are operated not in the linear region but in the saturation region. Thus, the voltage controlled oscillator according to an embodiment of the present invention is operated at a voltage level of about 1.4V which is more than addition of threshold voltages of the PMOS transistors P 17  and the NMOS transistor N 16 . As a result, the voltage controlled oscillator can generate a pulse signal having a predetermined cycle by providing a constant current to the oscillator unit  300  even in a low power voltage region.  
         [0044]     Here, the start-up circuit unit  200  controls the levels of the bias voltages BIAS 3  and BIAS 4  in the low power voltage region.  
         [0045]     That is, when the bias voltage BIAS 4  is around 0V, a gate voltage level of the NMOS transistor N 14  becomes lower to turn on the PMOS transistor P 16 . Then, the gate voltage level of the NMOS transistor N 14  becomes higher, so that the level of the bias voltage BIAS 4  becomes also higher. In other words, if the gate voltage level of the NMOS transistor N 14  becomes higher, the NMOS transistor N 16  is turned on to increase the level of the bias voltage BIAS 4 .  
         [0046]     When the level of the input power is high, the NMOS transistor N 15  is turned on. Then, the gate voltage level of the NMOS transistor N 14  becomes lower to turn off the NMOS transistor N 14 . As a result, the NMOS transistor N 14  is configured to increase the level of the bias voltage BIAS 4  in the low power voltage region and to be kept at a turn-off state in a high power voltage region.  
         [0047]     Thereafter, the oscillator unit  300  generates a predetermined pulse signal by providing a constant bias current depending on the values of the bias voltages BIAS 3  and BIAS 4  applied from the biasing circuit unit  100  to the inverter unit  303 .  
         [0048]     As discussed earlier, a voltage controlled oscillator according to an embodiment of the present invention generates a self-refresh signal having a predetermined cycle regardless of change of an input power in the voltage controlled oscillator used in a self-refresh operation of a DRAM.  
         [0049]     While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that the invention is not limited to the particular forms disclosed. Rather, the invention covers all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined in the appended claims.