Abstract:
A signal observation system for displaying a plurality of digital signals simultaneously on a CRT screen. The signals may be displayed individually or may be logically combined and displayed as the combination dependent on selected parameters, including the logic state of each signal and the direction of the transition when the logic level changes.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a system for observing signal waveforms, and relates to such a system which is called a logic scope or a logic analyzer. 
     That kind of signal observation system has a memory for storing a signal to be observed, and displays a plurality of waveforms simultaneously on a CRT screen, therefore, that system is useful for the development of an electronic apparatus, and/or the maintenance or repair of such an apparatus. 
     The prior waveform observation system, or a logic analyzer has been shown in the Japanese patent publication No. 34903/80. FIG. 1 is the block diagram of that prior logic analyzer. 
     In FIG. 1, the reference numeral 1 is an input terminal for accepting signals or waveforms to be analyzed. The input terminal 1 has a plurality of terminals (for instance 8 terminals) in order to analyze simultaneously a plurality of waveforms. The reference numeral 2 is a comparator which compares the level of a signal of the input terminal 1 with the threshold level which is supplied by the reference voltage source 3, and said comparator 2 provides a digital output signal according to the result of the comparison. That comparator 2 is installed for each channel of the input waveforms. The reference numeral 4 is a memory for storing a digital output signal of said comparator 2, and said memory 4 is also provided for each channel. The memory 4 writes the signal with the writing clock signal generated by the clock signal generator 6, and reads the content repetitively with the reading clock signal. The reference numeral 5 is a control counter which provides the address information of the memory 4 according to the writing clock signal generated by the clock signal generator 6. That control counter 5 also provides a write-read switching signal after the predetermined delay time determined by the trigger delay circuit 8 when the trigger circuit 7 provides a trigger signal to said control counter 5. Said write-read switching signal is applied to the clock signal generator 6, and then, the writing clock phase is switched to the reading clock phase. The switch SW is provided in order to trigger the control counter 5 by an external trigger signal. 
     The reference numerals 10 and 11 are a condition set switch and a gate circuit (condition detection circuit), respectively, and are shown in FIG. 2 in detail. That condition set switch and gate circuit are provided for each channel. Each condition set switch (10-1, 10-2, . . . , 10-n) has a switch with three contacts, which correspond to (1) the logic value &#34;1&#34;, (2) DONT CARE &#34;X&#34; which does not care whether the input digital value is &#34;1&#34; or &#34;0&#34;, and (3) the digital value &#34;1&#34;. The first and the third contacts &#34;0&#34; and &#34;1&#34; provide the digital value &#34;0&#34; when closed, and provide the digital value &#34;1&#34; when opened. The gate circuits (11-1, 11-2, 11-3, . . . , 11-n) which relate to the corresponding switches (10-1, 10-2, . . . , 10-n) function (1) to invert the output polarity of the memory 4, (2) to pass the output of the memory 4 without inverting the same, or (3) to stop the output of the memory 4 and prevent the same, according to the status of the switches 10. The AND circuit 12 functions to detect the data which satisfies the conditions defined by the switches 10. 
     The numeral 14 is a channel selector, which receives the outputs of the memory 4, and the output of the AND circuit 12 through the switch 13. The numeral 15 is a channel counter, which provides the channel selection signal to have the channel selector 14 select the designated channel and output the content of the memory 4, every time the control counter 5 designates the final address for each memory 4. The Y-axis signal generator 16 provides the Y-axis signal to the CRT 19 (cathode ray tube) according to the outputs of the channel selector 14 and the channel counter 15. The X-axis signal and the Z-axis signal are provided by the X-axis signal generator 17 and the Z-axis signal generator 18, respectively, according to the count content of the control counter 5. 
     It is supposed in FIG. 1 that the number of channels is 8. Each of the input signals at the input terminal 1 is compared with the threshold level in the comparators 2, and is converted to the digital value which takes 1 or 0. The converted value is sampled by each write clock signal, and the sampled values of 8 channels are stored in the memory 4 simultaneously. Upon the completion of the write operation to the memory 4, the trigger circuit 7 generates a trigger signal, which changes the operation mode from the write mode to the read mode, in which the content of the memory 4 is read out. When the switch 13 contacts the contact (a) in the read mode, the 8 channels of the data in the memory 4 are indicated on the screen of the CRT as shown in FIG. 3A. 
     Next, it is assumed that the switch 13 contacts the contact (b) in the indication status of FIG. 3A, and the switches (10-1, 10-2, . . . , 10-n) set the logic conditions of each channel. For instance, if the channels 1 and 3 are set to &#34;1&#34; by the switches 10, and other channels are set to &#34;x&#34; (don&#39;t care), then, the indication of the 8&#39;th channel is replaced by the time sequence of FIG. 3B, which satisfies the logic conditions set by the switches 10. 
     Accordingly, said prior art of Japanese patent publication No. 34903/80 is useful to analyze the logic signals, and to find out the particular combination of the logic conditions. 
     However, said prior art has the disadvantages that the logic statuses to be analyzed are restricted only to &#34;1&#34;, &#34;0&#34;, and &#34;x&#34; (don&#39;t care), and the transition of the logic status (from &#34;0&#34; to &#34;1&#34;, and from &#34;1&#34; to &#34;0&#34;) is not detected. Thus, due to the lack of the detection of the logic changes, said prior apparatus is useless for some purposes. 
     SUMMARY OF THE INVENTION 
     It is an object, therefore, of the present invention to overcome the disadvantages and limitations of a prior logic analyzer by providing a new and improved logic analyzer. 
     It is also an object of the present invention to provide a logic analyzer which can detect the logical change of an input signal. 
     The above and other objects are attained by a logic analyzer comprising a plurality of input terminals for accepting digital input signals of a plurality of channels; a plurality of comparators each provided for each channel, for converting the input signals to the sampled digital signals; a plurality of memories each provided for each channel for storing the sampled digital signals of all the channels; means for reading out the content of said memories and displaying the same on a screen of a CRT display means; a plurality of condition set switches each provided for each channel being provided, and each condition set switch designating one of the &#34;1&#34; status, the &#34;0&#34; status, the &#34;x&#34; (don&#39;t care) status, the &#34;up&#34; status which shows the transition of the input signal from &#34;0&#34; to &#34;1&#34;, and the &#34;down&#34; status which shows the change of the input signal from &#34;1&#34; to &#34;0&#34;; a plurality of condition detection circuits each provided for each channel being provided to detect if the signal status of each channel coinciding with the designated status which is set by the related condition set switch; an AND circuit for providing the logical product of all the outputs of said condition detection circuits; and a switch for selecting one of the output of said memories and the output of said AND circuit to display the output of the switch on the screen. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects, features, and attendant advantages of the present invention will be appreciated as the same become better understood by means of the following description and accompanying drawings wherein: 
     FIG. 1 is a block diagram of a prior logic analyzer, 
     FIG. 2 is a detailed block diagram of the condition set switches 10 and the gate circuit 11 in FIG. 1, 
     FIGS. 3A and 3B are output waveforms of the apparatus of FIG. 1, 
     FIG. 4 is a block diagram of the logic analyzer according to the present invention, 
     FIG. 5 shows an operational time chart showing the operation of the memory and the clock shaper circuit of FIG. 4, 
     FIG. 6 is a detailed block diagram of the logic condition set switches and the condition detector of FIG. 4, 
     FIG. 7 shows the operational time charts of the flip-flop of FIG. 6, 
     FIG. 8 shows the example of the output indication of the apparatus of FIG. 4, 
     FIG. 9 is the block diagram of the other embodiment of the logic analyzer according to the present invention, 
     FIG. 10 is the memory map of the RAM of FIG. 9, and 
     FIG. 11 is the explanatory drawing of the operation of the apparatus of FIG. 9. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 4 is the block diagram of the logic analyzer according to the present invention. The features of the embodiment of FIG. 4 are the presence of the logic condition set switches 20 which provide the logic conditions a n  including (1) the logic &#34;1&#34;, (2) the logic &#34;0&#34;, (3) the logic &#34;x&#34; (don&#39;t care), (4) the logic &#34;up&#34; (↑) which shows the transition of the logic status from &#34;0&#34; to &#34;1&#34;, and (5) the logic &#34;down&#34; (↓) which shows the transition of the logic status from &#34;1&#34; to &#34;0&#34;, and the condition detection switches 21 which find out the position or the timing which satisfies the designated conditions. The logic condition set switches 20 are provided for each of the channels, and each switch may have one of said five logic conditions. The condition detection switches 21 correspond to the logic condition set switches 20, and said condition detection switches 21 also receive the output of the memory 4. Each of the condition detection switches 21 has flip-flops (explained later) which are reset every clock timing by the output of the clock shaping circuit 23. The clock shaping circuit 23 accepts the clock signal of the clock generator 6, and provides the shaped output which has the relations with the output of the memory 4 as shown in FIG. 5. In FIG. 5, the time duration T is the data read out duration for each clock, and said duration T is in the order of a micro second, the duration t 1  is the pulse width of the output of the clock shaping circuit 23, t 2  is the difference between the end of the duration T and the end of the output pulse of the clock shaping circuit 23. The duration t 1  is usually 10-50 ns for reseting said flip-flops, and the duration t 2  is 30-20 ns which is longer than the data setup time of said flip-flops. 
     The AND circuit 22 receives the outputs of the condition detection circuits 21, and detects the data which satisfies the conditions set by the switches 20. 
     FIG. 6 shows the detailed block diagram of the switches 20 and the condition detection circuits 21. Those circuits are provided for each of the channels, and therefore, only the first ones 20-1 and 21-1 are shown in detail. 
     The switch 20-1 has a pair of contacts (201, 202) which relate to the five logic conditions (&#34;1&#34;, &#34;0&#34;, &#34;x&#34;, &#34;up&#34;, and &#34;down&#34;), and a pair of switches (S 1 , S 2 ) for selecting one of said contacts. The contacts &#34;down&#34;, &#34;0&#34; &#34;x&#34;, &#34;1&#34;, and &#34;up&#34; take the value 0 when the switches S 1  and S 2  contact to the related contact, and take the value 1 when said switches do not contact to the related contact. 
     The condition detection circuit 21-1 has the exclusive-OR circuit 211 which receives the output of the memory 4 and the contacts &#34;down&#34; and &#34;0&#34;, the NAND circuit 212 which receives the contacts &#34;down&#34; and &#34;0&#34;, and the contacts &#34;1&#34; and &#34;up&#34;; the D-type flip-flop 213 of a positive edge trigger type which receives the output of the exclusive-OR circuit 211 through the inverter 215 to the clock input terminal CK, and the output of the clock shaping circuit 23 to the negative clear input terminal CL; the gate circuit 214 which receives the contacts 202, the output of the exclusive-OR circuit 211, and the Q output of the flip-flop 213, and passes the output of the exclusive-OR circuit 211 when &#34;0&#34;, &#34;x&#34; or &#34;1&#34; is selected, and passes the Q output of the flip-flop 213 when &#34;up&#34; or &#34;down&#34; is selected; and the NOR circuit 216 which receives the output of the gate circuit 214 and the output of the NAND circuit 212. The outputs of the NOR circuits 216 of each of the detection circuits (21-1, 21-2, . . . , 21-n) are applied to the AND circuit 22, the output of which is applied to the channel selector 14 through the selection switch 13. 
     In the above configuration, when the logic condition set switch 20-1 contacts to the contact &#34;0&#34;, &#34;x&#34; or &#34;1&#34;, the gate circuit 214 passes the output of the exclusive-OR circuit 211, and the operation of the circuit is the same as that of FIG. 1, and in this case, the data satisfying the conditions are applied to the AND circuit 22. 
     On the other hand, when the switch 20-1 contacts to the contact &#34;up&#34; or &#34;down&#34;, the gate circuit passes the Q output of the flip-flop 213. When the &#34;down&#34; from the level &#34;1&#34; to the level &#34;0&#34; is selected, the contact &#34;down&#34; takes the level 0, and then, the output of the memory 4 passes the exclusive-OR circuit 211, the sign of the same is inverted by the inverter 215, and then, the inverted signal is applied to the clock input terminal CK of the flip-flop 213. Thus, the Q output of the flip-flop is inverted, that is to say, when the level of the data of the memory 4 changes from &#34;1&#34; to &#34;0&#34;, the Q output of the flip-flop 213 changes from 1 to 0. 
     FIG. 7 shows the operational time chart of the D-type flip-flop, and the curve (a) is the output of the memory, (b) is the input of the clock terminal CK of the flip-flop, (c) is the Q output, (d) is the Q output, (e) is the output of the clock shaping circuit 23 applied to the clear input terminal CL of the flip-flop, (f) is the output of the NOR circuit 216. As apparent from FIG. 7, the Q output of the flip-flop changes according to the transient of the output of the memory 4, and said Q output is applied to the NOR circuit 216 through the gate circuit 214. The NOR circuit 216 receives also the output of the NAND circuit 212, and invertes the signal Q as shown in FIG. 7(f), and applied the condition detection signal to the AND circuit 22. In the above operation, the output (FIG. 7(e)) of the clock shaping circuit 23 is applied to the clear terminal CL of the flip-flop, and therefore, the status of the flip-flop returns to the original status (&#34;1&#34;) after one clock duration. In another word, the Q output of the flip-flop is inverted only in one clock interval when the output of the memory 4 satisfies the designated conditions. 
     The operation when the &#34;down&#34; is designated is described above. The operation when the &#34;up&#34; is designated is similar except that the output of the memory is inverted by the exclusive-OR circuit 211. In the &#34;up&#34; condition, the Q output of the flip-flop 213 changes when the output of the memory changes from 0 to 1. 
     Although the above explanation is carried out for the switch 20-1 and the condition detection circuit 21-1, other switches (20-2, . . . , 20-n), and the condition detection circuits (21-2, . . . , 21-n) operate similarly. Accordingly, by providing the logic statuses by the switches (20-1, 20-2, . . . , 20-n), the timing position which satisfies all the logic conditions designated by the switches is detected. 
     FIG. 8 shows the example of the operation of the multi-channels, in which 8 channels of signals are indicated on the screen. In this case, the 8&#39;th channel is not indicated on the screen since the switch 13 in FIG. 4 is connected to the contact (b). In FIG. 8, it is assumed that the logic conditions a n  for the channels are a 1  =&#34;1&#34;, a 2  =&#34;0&#34;, a 3  =&#34;x&#34;, a 4  =&#34;up&#34;, a 5  =&#34;down&#34;, a 6  =&#34;x&#34;, a 7  =&#34;0&#34;, and a 8  =&#34;x&#34;, the bit position which satisfies all the above conditions is indicated on the 8&#39;th track as the result of the combination. It should be appreciated in FIG. 8 that the signals in each of the channels in the interval T which provides the combination result, satisfying the above conditions. The clock signals in FIG. 8 are not indicated on the screen, but those clock signals are shown in the drawing for the sake of the easy understanding of the explanation. 
     FIG. 9 shows the block diagram of the other embodiment of the logic analyzer according to the present invention. The embodiment of FIG. 9 performs the same function as that of FIG. 4, by using a micro-computer system. The same numeral in FIG. 9 as that in FIG. 4 shows the same member as that of FIG. 4. 
     In FIG. 9, the numeral 30 is a control, which includes a micro-processor 301, a ROM (read only memory) 302 for storing the program for the operation of the processor 301, a RAM (random access memory) 303, and some other components consisting of a microcomputer system like a decoder. The numeral 31 is a keyboard for inputing logic conditions a n , 32 is a keyboard interface for coupling the keyboard 31 with the computer system, 33 is an I/O port for coupling memories 4 with the computer bus 40, 34 is a CRT control, 35 is a CRT monitor screen, 36 is an I/O port for applying a write-read switching signal to the clock generator 6. It is supposed that the computer BUS 40 includes the data bus for the data transfer among the sections, the address bus, the read control line, the write control line, and the chip-select line. 
     In the above configuration, when the signals to be analyzed are applied to the input terminals 1, those signals are stored in the memory 4 through the comparator 2, as similar to the previous embodiment. When the data of all the channels are stored in the memory 4, the I/O port 36 provides a switching signal from the write mode to the read mode, and then, the content of the memory 4 is read out, and the data thus read out is transferred to the RAM 303. 
     The RAM 303 has a plurality of sections for storing the data of the memory 4, the section Me for storing the search result, the area A for storing the effective train of bytes A n  of the combined logic condition a n , the sections B and C for storing the result of the comparison, and other miscellaneous work area and/or stack area, as shown in FIG. 10. The section Me stores as shown in FIG. 11 the logical product of the designated condition a n , and the input data b ij  (i=1-n, n is the number of channels, j=1=m, m is the memory length) for every clock interval. In the embodiment of FIG. 11, the j&#39;th bit of the section Me is 1, and other bits are zero. The section A stores the combined logic conditions a n  in the form of the byte train A n  defining the said combined logic conditions. 
     When the logic conditions a n  are provided by the keyboard 31 to each of the channels, the conditions are encoded to the byte train A n , which is stored in the section A. Next, the control 30 derives the input data b ij  to be searched in the RAM 303, then, the input data b ij  is compared with the logic conditions. When the comparison result is &#34;no&#34;, the data &#34;0&#34; is stored in the related bit of the section Me, and when the comparison result is &#34;yes&#34;, the data &#34;1&#34; is stored in the related bit of the section Me. The search result or the comparison result is indicated on the screen of the CRT monitor 35 through the CRT control 34, together with the input data of each of the channels. 
     The comparison of the input data b ij  to be searched with the logic conditions a n  is accomplished as follows. 
     It is assumed in FIG. 11 that there are five channels (1) through (5), and the logic conditions a n  of the channels are &#34;1&#34;, &#34;0&#34;, &#34;x&#34;, &#34;up&#34;, and &#34;down&#34;, respectively. 
     First, the temporary logic condition d n  is defined by replacing &#34;up&#34; to &#34;1&#34;, and &#34;down&#34; to &#34;0&#34;. Then, d n  is shown below. 
     
         d.sub.n =10×10 
    
     (note: a n  =10×up down) 
     Then, the second temporaty condition a n   x  (in the original condition a n ) is defined by replacing the don&#39;t care (x) to &#34;0&#34; as follows. 
     
         a.sub.n.sup.x =11011 
    
     The input data b ij  at the j&#39;th bit position of FIG. 11 to be transferred to the RAM 303 is shown below. 
     
         b.sub.ij =10010 
    
     Then, the d n  and b ij  are masked by a n   x  since &#34;don&#39;t care&#34; needs not to be considered. 
     
         d.sub.n &#39;=d.sub.n AND a.sub.n.sup.x =10010 
    
     
         b.sub.ij &#39;=b.sub.ij AND a.sub.n.sup.x =10010 
    
     Then, d n  &#39; is compared with b ij  &#39; as follows. 
     
         d.sub.n &#39; ExOR b.sub.ij &#39;=00000 
    
     Therefore, when all the bits of said comparison are zero&#39;s, the input data b ij  satisfies the condition a n . When the input data satisfies the condition a n , the data `1` is stored in the section B, and when the input data does not satisfy the conditions, the data `0` is stored in the section B. Thus, the section B stores the result whether or not the input data satisifes the conditions. 
     However, it should be noted that the above procedure does not indicate the transition (&#34;up&#34; and/or &#34;down&#34;). Therefore, the search for the indication of that transfer is performed. 
     In this procedure, the temporary condition f n  is provided by replacing &#34;up&#34; and &#34;down&#34; to &#34;1&#34; in the original condition a n . 
     
         f.sub.n =00011 
    
     In order to find the transition &#34;up&#34; or &#34;down&#34;, the input data b i (j-1) of the previous clock interval is tested. 
     
         b.sub.ij =10010 
    
     
         b.sub.i(j-1) =10001 
    
     It should be noted that when the data of the previous clock interval is different from the data of the present clock interval, there exists a transition or a data change in the related channel. In order to search only the channels in which &#34;up&#34; or &#34;down&#34; is designated, the data b ij  and b i (j-1) are masked by f n  as follows. 
     
         b.sub.ij &#39;=b.sub.ij AND f.sub.n =00010 
    
     
         b.sub.i &#39;.sub.(j-1) =b.sub.i(j-1) AND f.sub.n =00001 
    
     Then, those two values are compared through the exclusive-OR procedure as follows. 
     
         g.sub.n =b.sub.ij &#39; ExOR b.sub.i(j-1) &#39;=00011 
    
     The pulse train g n  clarifies the transition of data between the previous clock interval and the present clock interval. In the above embodiment of g n , the pulse train g n  shows that there exists the transition which satisfies the conditions of a n  in the channels (4) and (5). 
     Next, the exclusive-OR logic is accomplished between f n  and g n  in order to test if all the bit conditions are satisfied. The result is 0 (in all bits) when all the conditions are satisfied. When all the bits is 0 which shows the existence of the transition, the data &#34;1&#34; is stored in the section C, and if there is no transition (when all the bits of g n  is zero), the data `0` is stored in the section C. 
     Finally, the logical product of the content of the section B and the content of the section C is accomplished. When the result of the logical product is `1`, the data `1` is stored in the bit position of the section Me related to the bit position of the input data b ij . In the present embodiment of FIG. 11, the content of the section B is &#34;1&#34;, and the content of the section C is &#34;1&#34;, thus, the logical product is `1`, and then, the data `1` is stored in the j&#39;th bit of the section Me. 
     The above procedure is accomplished to all the bit positions of the input data b ij , and the result is stored in the section Me. The content of Me is indicated on the screen on a time-axis (combination result), and therefore, the bit position that the input data satisfies the designated conditions is indicated on the screen. 
     Some modifications of the above embodiments are possible of course. For instance, the result of the combination result may be indicated by a low level, intensity modulation, a specified mark, et al, instead of a high level of FIG. 11. Further, the indication by binary value or hexadecimal value, instead of a timing indication may be possible. 
     As described above in detail, the additional logic conditions &#34;up&#34; and &#34;down&#34; which indicate the transition or the change from `0` to `1`, or from `1` to `0` may be detected together with the logic conditions `1`, `0`, `don&#39;t care`. Therefore, the present analyzer is useful for analyzing a digital signal for the research laboratory work, and/or field maintenance work. 
     From the foregoing it will now be apparent that a new and improved logic analyzer has been found. It should be appreciated of course that the embodiments disclosed are merely illustrative and are not intended to limit the scope of the invention. Reference should be made to the appended claims, therefore, rather than the specification as indicating the scope of the invention.