Abstract:
There are TDM communication systems in which synchronization is accomplished by means of code words which are transmitted at regular time intervals and coded in a particular code. In systems where the signals are transmitted in packets of uniform length, each of the code words contains the information of the so-called header of a packet. The checking device according to the invention successively checks all n-bit bit groups (X j  to X j+n- ) beginning with any one (X j ) of the successive bits of the received bit sequence as to whether they are coded in a particular code. This is done by calculating the syndrome (S 1  to S n-k ) in several networks (N 1  to N n-k ) which operate in parallel and each of which calculates one syndrome component. The received bit sequence is delayed until the networks have calculated the syndromes for a given n-bit bit group and until a syndrome evaluation circuit (LS) indicates whether the bit group is a code word.

Description:
This is a continuation of copending application Ser. No. 07/547,494 filed on Jul. 2, 1990, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a time-division multiplex communication system comprising a transmitting device which regularly inserts an n-bit word coded in a linear block code into the bit sequence to be transmitted, and a checking device at the receiving end which looks for the n-bit word in the received bit sequence by checking groups of n successive bits as to whether they are coded in the block code. 
     2. Description of the Prior Art 
     Such a system is disclosed in DE-A1-37 35 377, wherein a so-called code word is derived from information referred to there as &#34;header&#34;, which contains a logic channel number, and transmitted subsequent to the information. In common technical terms, the information (K) is coded in a linear block code to form a code word whose number of bits is equal to the number of bits of the information (K) augmented by the number of added bits (called &#34;code word CW&#34; there) . The number of bits in the code word consisting of the k-bit information (K) and the added bits will hereinafter be denoted by n. In the prior art system, such code words are inserted at the transmitting end into the bit sequence at regular time intervals, namely at the beginning of each so-called packet. At the receiving end, the prior art system includes a checking device which looks for the n-bit code words in the received bit sequence. It does so by selecting a sequence of k-bits from the received bit sequence and checking whether this k-bit sequence and the subsequently received n-k bits (n-k is the number of bits added to the information K at the transmitting end) together represent a code word which is coded in the block code. If the checking device determines that the checked bit sequence is not coded in the block code, it will stop the search for the code word in the current packet and resume it in the next packet, in which it then selects a bit sequence which, referred to the beginning of the packet, begins one bit later than the bit sequence selected in the previously checked packet. 
     This means that considerable time may elapse until the n-bit word looked for is found in any packet. This, in turn, has the disadvantage that the synchronization of the receiver with the transmitter takes a long time, thus causing considerable information losses. 
     SUMMARY OF THE INVENTION 
     It is therefore the object of the invention to provide a time-division multiplex communication system of the above kind in which the synchronizing device at the receiving end finds the n-bit words faster, thus ensuring faster synchronization. 
     This object is attained by using a checking device that successively checks all n-bit bit groups which begin with any one of the successive bits of the received bit sequence. 
     Aside from making it possible to quickly find the n-bit words coded in the block code, the invention has the advantage that none of the parts of the check circuit requires a processing clock frequency which is higher than the bit rate of the received bit sequence. Therefore, the checking device can be implemented in CMOS technology and, thus, at low cost even at a high bit rate of 150 Mb/s. Any circuit operating at higher clock frequencies could only be implemented in a more expensive technology, e.g., ECL. 
     Before the invention is described with reference to the accompanying drawings, it will be briefly explained what kind of mathematical check is used to determine whether the bit group is coded in the linear block code. Such a block code is commonly referred to as an (n, k)-block code, where n is the total number of bits per block, and k is the number of information bits per block. 
     According to the invention, the checking of an n-bit bit group as to whether it is coded in the linear block code is done by calculating the syndrome on the basis of the parity check matrix of the linear block code used. That is not the case with the above-mentioned prior art checking device. As is well known, the syndrome, hereinafter denoted S, is a vector of dimension n-k and is calculated by multiplying the transpose of the parity check matrix H of the block code by the received block, hereinafter denoted X. Further details are described in a book by W. W. Peterson, &#34;Error-Correcting Codes&#34;, Massachusetts Institute of Technology and John Wiley &amp; Sons, Inc., New York, London, 1961, pp. 30-36. 
     The ith component of the syndrome must be calculated from an n-bit block and the transpose of the parity check matrix as the scalar product of the ith row h i  and the received block X, i.e., 
     
         S.sub.i =h.sub.i X=h.sub.i1 X.sub.1 +h.sub.i2 X.sub.2 +hi.sub.3 X.sub.3 +. . . h.sub.in X.sub.n. 
    
     These components of the vector S are calculated by the check circuit according to the invention for each n-bit bit group which begins with any one of the successively received bits, i.e., for the first bit of the bit sequence and the next n-1 bits, one bit period later for the second bit of the received bit sequence and the next n-1 bits, etc. 
     The syndrome calculation is commonly used for error detection. A given data word is examined as to whether it contains a code error, as in DE-A1 37 07 143, for example. There, the syndrome calculation is not used to find out at what point a bit sequence transmitted at a high bit rate contains a word coded in the block code. The implementation of the circuit disclosed in that publication also would be unsuitable for the present application, since it uses memories in which partial syndromes are stored, and since such a circuit, because of the memory access times and the EXCLUSIVE-OR gates following the memories, would require too long a processing time for the present application. 
     In the following, it will be explained with the aid of the accompanying drawings how the calculation and checking of the syndrome S are performed for each n-bit bit group beginning with a bit of the received bit sequence. 
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     The invention will now be explained in greater detail, by way of example, with reference to the accompanying drawings, in which: 
     FIG. 1 is a block diagram of the checking device at the receiving end of the system according to the invention; 
     FIG. 2 shows an embodiment of one of the networks N 1  to N n-k  of FIG. 1; 
     FIG. 3 shows the logic diagram of one of the elements E 1  of FIG. 2, and 
     FIG. 4 shows the logic diagram of one of the elements E 2  of FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the checking device shown in FIG. 1, the received bit sequence is applied to the serial input of a shift register R1 having a length of n-1, i.e., n-1 series-connected flip-flops, if the code word to be found contains n-bits. Such a shift register has n-2 parallel outputs, so that n successively received bits of the bit sequence are made available in parallel for further processing. If the bit appearing at the output of the shift register SR1 at any defined point of time is denoted X j , the subsequent bits of the n-bit bit group beginning with the bit X j  will appear simultaneously at the parallel outputs of the shift register SR1, where they are denoted x j+1  to X j+n-2 , and at the input of the shift register SR1, with the bit appearing at the input of the shift register denoted x j+n-1 . Since the shift register is controlled by a clock signal C whose frequency is equal to the received bit frequency, the n-bit word beginning with the bit x j+1  is made available for further processing in the next bit period. 
     The n-bit bit group made available for further processing in any bit period of the received bit sequence is applied in parallel to a bus designated n, of which selected conductors are connected to the inputs of networks N 1  to N n-k  which are arranged and operated in parallel. For each syndrome component S i  to be calculated as described above, there is one network, i.e., n-k networks, because the syndrome has n-k components, as mentioned above. 
     Of the n bits of the n-bit bit group to be checked, only those bits are entered into a network N i  for which the associated value h il  is nonzero (above equation for S i ). In the above equation for S i , this means, for example, that in the network N i , which calculates the component S i  of the syndrome if the values h i2  and h i3  are zero, only the first, fourth, and subsequent bits of the n-bit bit group are entered, while the bits appearing in the second and third positions of an n-bit bit group, no matter what binary value they represent, are omitted. Thus, based on the parity check matrix, a particular selection of the n bits of an n-bit bit group to be checked is entered into each of the n-k networks N 1  to N n-k  for each component of the syndrome. The networks calculate their component of the syndrome by the above equation or S i  in several stages and, as will be explained with the aid of FIG. 2, deliver their components S i  of the syndrome simultaneously at their outputs, which are designated S 1  to S n-k . 
     Since the h il  of the parity check matrix can only have the value 0 or 1, and the additions given in the above equation are modulo-2 additions, the calculation to be performed consists of EXCLUSIVE-ORing the input bits several times, which, as is well known, yields a 1 as a syndrome component in the presence of an odd number of ones and a 0 in the presence of an even number of ones. 
     The EXCLUSIVE-ORing of the input bits of one of the networks, which is performed in several stages, takes place at the bit rate C of the received bit sequence. After a given number of bit periods, the syndrome for the n-bit bit group being checked is present at the outputs of the networks. Its bits pass through a logic circuit LS, which produces an output signal if the syndrome is zero (all components), thus indicating the detection of an n-bit code word. 
     From the output of the shift register SR1, the bit sequence is applied to the serial input of a shift register SR2, which, too, is operated at the bit rate of the bit sequence and delays the bit sequence until the networks N i  have calculated the syndrome for an n-bit bit group beginning with the bit X j . Thus, the first bit of a bit group will appear at the output of SR2 when the logic circuit LS indicates at its output whether this bit group is a code word or not. The logic circuit LS introduces no appreciable delay. If its delay should be too long, it may be compensated by lengthening the shift register SR2 correspondingly. 
     The advantage of the checking device described so far lies in the fact that it checks the received bit sequence bit by bit without any delay and does not require a processing clock frequency which is higher than the bit frequency. 
     An embodiment of one of the networks N i  of FIG. 1 will now be explained with the aid of FIG. 2. FIG. 2 shows a network N i  for calculating a component S i  (j) from a bit group beginning with a bit X j . The example assumes that nine of the n bits of the n-bit bit group to be checked, which begins with the bit X j , have to be used for calculating the component S i  (j) of the syndrome. (For the other bits, the associated h il  are nonzero). The bits to be used for the calculation are denoted at the parallel inputs of N i  by X(j-i 0 ) to X(j-i 8 ). 
     In a stage ST 1  of N i , the input bits to be summed by modulo-2 additions are combined into arbitrary pairs, with each bit permitted to occur in only one pair. In the example shown, therefore, there are four pairs and one remaining bit, because the number of bias is odd. Each pair of bits is added modulo 2 in one of network elements of a first type E 1  in a first clock period and stored until the next clock period. The remaining bit is stored in a network element of a second type E 2  until the next clock period. 
     The functions of the elements of the type E 1  and type E 2  are shown in FIGS. 3 and 4, respectively. An element E 1  contains an EXCLUSIVE-OR gate A 1 , which forms the EXCLUSIVE-OR of two input bits applied at the inputs x and y, i.e., adds them modulo 2, and a succeeding D flip-flop D 1  which stores the result until receipt of the next clock pulse. The D flip-flop is controlled by the bit-rate clock C indicated in FIGS. 1 and 2. An element E 2  serves to store a single bit applied at its input X in a D flip-flop D 2  until receipt of the next clock pulse. It is also controlled by the clock C. 
     After the input bits of N i  have been combined in pairs and the results and the remaining input bits have been temporarily stored in the first stage ST 1  of N i  in a first clock period, the temporarily stored results and the temporarily stored remaining bit of the stage ST 1  are processed in a corresponding manner in a stage ST 2  upon receipt of the next clock pulse. The input bits are again combined in pairs by elements E 1 , and the remaining bit is stored in an element E 2 . Upon receipt of the next clock pulse, the results of stage ST 2  are processed in a corresponding manner in a stage ST 3 , and upon receipt of a further clock pulse, a last stage ST 4   calculates, in an element E 1 , the result bit, i.e., the component S i  (j) of the syndrome, from the results of stage ST 3 . In the example shown, i.e., with nine inputs, four stages are needed, so that four bit periods after the first bit X j  of an n-bit bit group beginning with this bit appeared at the output of the shift registers SR1 of FIG. 1, the network N i  has calculated the component S i  (j) of the syndrome of this bit group. 
     Each of the networks N i  to N n-k  has an individual number of input bits to be combined and a corresponding number M i  of stages necessary for this purpose. In order for the entire syndrome S(j) of an n-bit bit group beginning with the bit group X j  to appear at the outputs of the network N i  simultaneously, those networks whose necessary number of stages M i  is less than the greatest M i  occurring in any one of the networks have additional stages including elements of type E 2 , so that all networks will make available their components S i  (j) of the syndrome S(j) at their outputs at the same instant. 
     This instant is M bit periods later than the instant at which X j  appears at the output of the shift register SR1 of FIG. 1, where M is the maximum number of stages required in any of the networks N i . The delay of the shift register SR2, mentioned above in connection with FIG. 1, is thus M bit periods. Thus, the shift register SR2 delays the bit sequence until it has been decided whether a particular bit group is a code word or not. 
     It should be added that instead of a shift register SR1, any other memory circuit can be used to make available the n-bit bit groups to be checked. This may also be a memory in which the bits of a received bit sequence are stored other than serially provided that it is possible to output successively received bits simultaneously as one n-bit bit group. 
     To optimize the circuit, the networks N i  may be interconnected to permit the transfer of intermediate results from one network to another, thus reducing the amount of circuit elements required.