Abstract:
A system for interpolatively displaying the values of a one-dimensional array of data sources is disclosed. The output signals are multiplexed and successively made available to the input of a tandem of samples and hold circuits. Stored data from the tandem of sample and hold circuits is applied in parallel format to a computation unit which produces a continuous signal interpolatively representing the values of each spatially adjacent pair of data sources. Control circuitry provides appropriately timed sample and hold signals to the tandem of sample and hold circuits as well as initialization signals to the computation unit. The computation unit is initialized on every sample period in synchronism with the multiplexer and sample and hold tandem. 
     The basic one-dimensional recursive interpolation scheme disclosed may also be utilized in a dual re-iterative manner to display the interpolated status of a two-dimensional data source array such as a two-dimensional array of thermocouples situated in proximity to the face of a continuous casting mold.

Description:
BACKGROUND OF THE INVENTION 
     The apparatus of the present invention relates generally to the production of graphical displays representative of the interpolated status of data source arrays. More specifically, the present invention relates to methods and apparatus for producing a continuously interpolated graphical display representing the status of a transducer array in spatial equivalence thereto. 
     Arrays of discrete date sources, i.e., transducers, are often used to monitor the spatial variations of a critical parameter. For example, it is often desirable to continuously monitor the temperature distribution of a face of a continuous casting mold. In order to monitor this temperature distribution, an array of thermocouples are strategically positioned along the mold face and their outputs monitored. This approach, of course, requires equipment and personnel to monitor the output of each individual thermocouple. Furthermore, the output of the individual thermocouples provide no information reflecting temperature conditions intermediate the individual thermocouples. 
     By the method and apparatus of the present invention a single graphical display representing the temperature distribution of a mold face is realized. In addition, the graphical display includes information reflecting the temperature distribution for locations intermediate the discretely located thermocouples. 
     The prior art teaches various devices whose general purpose is that of obtaining a graphic display from a plurality of intermittently sampled data signals. However, the graphic displays formulated by prior art methods have generally been limited to a series of discrete dots representing the values of the data sensors only. That is, for the most part, prior art teachings do not include means for obtaining information regarding positions intermediate the discrete sensor locations. And, although some prior art apparatus teaches the general concept of interconnecting the discrete data points with straight lines, this has generally been accomplished without attempting to derive any meaningful information respecting the positions intermediate the discrete data sensors. 
     The relatively few prior art devices which attempt to provide a meaningfully interpolated graphical output representing a data sensor array have involved the use of extremely complex equipment, generally including rather sophisticated computer programs. Complex devices of this type have proven unsatisfactory from both a cost and logistical standpoint. 
     Furthermore, the prior art methods have generally been limited to presenting graphical displays for a one-dimensional data sensor array only. As such, prior art methods of graphically displaying the condition of a two-dimensional data sensor array consists of simply repeating the one-dimensional process a sufficient number of times. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide an improved method and apparatus for producing a graphic display from intermittently sampled data sources, which method and apparatus yield a continuous and clearly readable display spatially equivalent to the status of the data source array. 
     A further object of the present invention is to provide a graphic display from intermittently sampled data which includes meaningfully interpolated results respecting locations intermediate data sensors. It is still a further object of the present invention to provide a graphic display from a plurality of intermittently sampled data signals arranged in a two-dimensional array wherein meaningful interpolations are accomplished with respect to both axes of the array. 
     More specifically, it is an object of the present invention to provide an improved method and apparatus for producing a graphic display of the temperature distribution on a continuous casting mold face from temperature data acquired by intermittently sampling a two-dimensional array of thermocouples located in proximity to the mold face. Another object of the present invention is to provide a meaningful and continuously interpolated display which presents, in spatial equivalence, an output representative of the temperature distribution of the mold face. 
     In accordance with the present invention data signals from a one-dimensional transducer array are multiplexed and successively made available to the input of a tandem of sample and hold circuits. The tandem of sample and hold circuits is configured so as to form an analog shift register such that the input for each sample and hold circuit succeeding the input sample and hold circuit is taken from the output of the immediately preceding sample and hold circuit. A control circuit establishes the sampling rate of the sample and hold tandem in a repetitive fashion such that, during each sample period, the last sample and hold circuit in the tandem is updated firstly, consecutively followed by the remaining sample and hold circuits in turn. The updating procedure of the sample and hold tandem occurs once for every sample period as determined by the sample rate. 
     Data from the sample and hold tandem is applied, in parallel format, to a computation unit. The computation unit, utilizing the applied data and time, after a predetermined time delay and, during each subsequent sample period, recursively provides a continuous output signal interpolatively representing the values of each spatially adjacent pair of data sources. Due to the continual updating of the sample and hold tandem, a continuous signal representing the interpolated values of the one dimensional transducer array is produced. 
     The particular interpolation scheme utilized is implemented by the computation unit. In some situations a linear interpolation may be considered appropriate, in which case the computation unit would be configured so as to implement a linear scheme. Furthermore, in the case of a linear scheme, two individual sample and hold circuits would comprise the sample and hold tandem. Should the computation unit be rearranged so as to implement a non-linear scheme the number of sample and hold circuits in the tandem would be accordingly increased. For example, in the case of implementation by a computation unit representing a third degree equation, four sample and hold circuits would be utilized. 
     The basic one-dimensional recursive interpolation scheme may also be utilized in a dual re-iterative manner so as to provide a graphical display of the status of a two-dimensional transducer array. That is, by causing a single one-dimensional interpolator to scan, at a relatively rapid rate, the interpolated outputs of a series of slower one-dimensional interpolators, a graphical output can be obtained of the two-dimensional transducer array which includes interpolative information in the direction of both axes of the array. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a general block diagram of one embodiment of the one-dimensional recursive interpolator of the present invention. 
     FIG. 2 is a diagrammatic representation of a one-dimensional transducer array showing the output signal levels of the individual transducers. 
     FIG. 3 is a detailed block diagram showing a linear embodiment of the one-dimensional recursive interpolator of the present invention. 
     FIG. 4 is a timing diagram for the interpolator embodiment of FIG. 3. 
     FIG. 5 is a graphical representation of various signals associated with the interpolator embodiment of FIG. 3. 
     FIG. 6 is a block diagram including a modification to the interpolator embodiment of FIG. 3. 
     FIG. 7 is a graphical representation of the output of the modified interpolator embodiment of FIG. 6. 
     FIG. 8 is a block diagram showing another linear embodiment of the one-dimensional recursive interpolator of the present invention. 
     FIG. 9 is a block diagram showing the interpolator embodiment of FIG. 3 being utilized in association with a single time varying transducer. 
     FIG. 10 is a diagrammatic representation of another one-dimensional transducer array showing the output signal levels of the individual transducers. 
     FIG. 11 is a block diagram showing a non-linear third degree embodiment of the one-dimensional recursive interpolator of the present invention. 
     FIG. 12 is a schematic diagram of the computation unit of the interpolator embodiment of FIG. 11. 
     FIG. 13 is a table illustrating various signal levels associated with the computation unit of FIG. 12. 
     FIG. 14 is a table illustrating various periodic states of the sample and hold circuits associated with the interpolator embodiment of FIG. 11. 
     FIG. 15 is a graphical representation of the output of the interpolator embodiment of FIG. 11. 
     FIG. 16 is a diagrammatical representation of a two-dimensional N × M transducer array. 
     FIG. 17 is a block diagram showing an embodiment of the two-dimensional recursive interpolator of the present invention. 
     FIG. 18 are four graphical representations associated with the interpolator embodiment of FIG. 17. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to the drawings and, particularly to FIG. 1, there is shown a general block diagram of the one-dimensional recursive interpolator of the present invention. A plurality of sample and hold circuits, indicated generally as at 2, 4, 6, 8 and 10, are arranged in tandem so as to form an analog shift register. As indicated by interconnections 3, 5, 7 and 9, the output of each sample and hold circuit is applied to the input of its immediately succeeding sample and hold circuit. Data from the sample and hold tandem 2, 4, 6, 8 and 10 is applied to a computation unit 11 in a parallel manner by respectively, data lines 12, 13, 14, 15 and 16. A control assembly comprising a system clock 17, such as clock oscillator model XO-14 manufactured by Electronics Division of Bulova Watch Company, Inc., and a timing control circuit 18 establishes the sampling rates of sample and hold circuits 2, 4, 6, 8 and 10 by repetitively pulsing, respectively, update lines 19, 20, 21, 22 and 23 communicating therewith. In addition, timing control circuit 18 causes the computation unit 11 to repetitively reset by commands transmitted thereto along reset line 24. The discrete input data is applied to the recursive interpolator along input line 25 communicating with sample and hold circuit 2 and the interpolated output is applied to a display means 26, such as a conventional oscilloscope, by the output line 27. The timing control circuit 18 drives the horizontal deflection input 28 of the display 26 by means of a deflection signal over line 29 such that the display 26 is caused to horizontally sweep at a rate proportional to the sampling rates of the sample and hold circuits 2, 4, 6, 8 and 10. Of course, the interpolated output from the computation unit 11 is applied by output line 27 to the vertical deflection input 30 of the display 26. 
     As indicated above, FIG. 1 is a general block diagram representing the basic one-dimensional interpolator of the present invention. Accordingly, a specific embodiment of the interpolator of the present invention may include a definite number of sample and hold circuits along with an appropriately configured computation unit. For example, a linear computation unit 11 can be utilized in conjunction with two sample and hold circuits to provide linear interpolation. Similarly, a non-linear computation unit 11 can be utilized in conjunction with four sample and hold circuits to provide third degree non-linear interpolation. 
     It has been found that adapting the recursive interpolator of FIG. 1 to perform linear interpolation is especially useful. Accordingly, FIG. 2 shows a one-dimensional transducer array 31 comprising five spatially oriented transducers 32, 33, 34, 35 and 36 occuring in a consecutive progression. E 0 , E 1 , E 2 , E 3  and E 4  respectively represent the successive magnitudes of the output voltages of the transducers. The linear interpolator shown in FIG. 3 can be utilized to provide an interpolated continuous output reflecting the data distribution monitored by the transducers 32, 33, 34, 35 and 36. 
     As noted in FIG. 3, wherein like parts have been identified by corresponding numerals, the linear recursive interpolator comprises a computation unit 11a, two sample and hold circuits 8a and 10a, a system clock 17a, a timing control circuit 18a, input line 25a, output line 27a, reset line 24a and update lines 22a and 23a. The display 26a has a vertical deflection input 28a coupled to the computation until 11a by output line 27a and a horizontal deflection input 30a connected to the timing control circuit 18a by line 29a. The computation unit 11a comprises a difference amplifier 37, a summing amplifier 38 and an integrator 39. 
     Operation of the one-dimensional linear recursive interpolator shown in FIG. 3 is conveniently illustrated with reference to the timing diagram shown in FIG. 4 and the various graphical outputs shown in the diagram of FIG. 5. To initiate the interpolation process, the system clock 17a applies a clock pulse 40 along line 41 to the timing control circuit 18a. In turn, the timing control circuit 18a applies a gate address signal along line 42 to the multiplexer 43 gating the output of the first transducer 32 of the transducer array 31 to input line 25a. Multiplexer 43 as well as the various other multiplexers discussed herein may be of the type identified by Datel Systems, Inc., Model MM16. Substantially simultaneously with the occurrence of clock pulse 40 the timing control circuit 18a develops and applies pulse 44 along update line 23a to sample and hold circuit 10a causing it to sample and store the current output of sample and hold circuit 8a by means of interconnection 45 communicating therebetween. Thereafter, the timing control circuit 18a applies a pulse 46 to sample and hold circuit 8a along update line 22a causing the latter to sample and store the current data value available along input line 25a from multiplexer 43. Therefor, since sample and hold circuit 10a accomplishes its sample slightly before sample and hold circuit 8a and, if the initial value stored in sample and hold circuit 8a is zero (0), sample and hold circuit 10a will store a value of zero during the first sample period which is defined as the time between occurrences of clock pulses 40 and identified in FIG. 4 by T. Also, since sample and hold circuit 8a samples the output of multiplexer 43 after the sampling by sample and hold circuit 10a, its stored value during the first sample period will consist of the gated output of transducer 32, which is represented by the data value E 0 . 
     It can thusly be seen that during the first sample period, i.e. T 0  as shown in FIG. 5, a data value having a magnitude of E 0  is being applied to the positive input terminal 46 of the difference amplifier 37 while a data value having zero magnitude is being applied to the negative input terminal 47 thereof. The output of the difference amplifier 37, during the first sample period T 0 , is constant at the value of E 0  as shown by curve 48 in FIG. 5. The constant difference data value E 0  is then applied over line 49 to integrator 39, which has been set to zero by the timing control circuit 18a via pulse 50 (See FIG. 4) along reset line 24a. If the gain of the integrator 39 is adjusted so that it equals the reciprocal of the sample period (i.e. 1/T) the output 51 of integrator 39 during the first sample period T 0 , will be a ramp function extending from zero to E 0  as shown by curve 52 of FIG. 5. The summing amplifier 38 adds the values applied to it by lines 51 and 53, respectively, the outputs of the integrator 39 and the sample and hold circuit 10a, to provide the interpolated output 54 during the first sample period to as shown in FIG. 5. 
     During the second sample period T 1  a similar process occurs. The system clock initiates clock pulse 40a whereupon the timing control circuit 18a causes multiplexer 43 to gate the output of the next consecutive transducer 33 of the transducer array 31 to input line 25a. Sample and hold circuit 10a is caused to update by pulse 44a transmitted thereto along update line 23a to the current value of sample and hold circuit 8a (E 0 ) and sample and hold circuit 8a is then caused to update by pulse 46a transmitted thereto along update line 22a to the current value available along input line 25a (E 1 ). Also, at the initiation of sample period T 1 , the integrator 39 is reset to zero by means of pulse 50a along reset line 24a. The output 49 of the difference amplifier 37 is now the value of E 1  minus E 0 , see curve 48a of FIG. 5, the output 51 of the integrator 39 is a ramp function, initialized at zero, reflecting this difference, see curve 52a of FIG. 5, and the output 27a of summing amplifier 38, see curve 54a of FIG. 5, adds the value of E 0  to the ramp. Note that during each sample period the integrator 39 is reset to zero so that each ramp function initiates at a zero level. A similar process is repeated during each subsequent sample period resulting in a repetitive interpolated output as depicted by the curve 54 through 54d in FIG. 5. It will be understood, of course, that the various sample periods may be of different duration. 
     As clearly shown in FIG. 5, the output 27a, which is represented by the curve 54 through 54d, is a linear interpolation, delayed by one sample period, of the transducer array 31 consisting of transducers 32, 33, 34, 35, and 36. The output 27a therefor, graphically represents, in spatial equivalency, the interpolated data distribution of the repetitively and successively sampled transducer array 31. Furthermore, since each repetitive interpolation (i.e. the inter-connection of each spatially adjacent pair of transducer data values) is an independent operation, due to repetitively initializing the integrator 39 to a zero level, and not dependent upon any prior or subsequent interpolations, the output 27a is a recursively interpolated output. 
     Finally, since the timing control circuit 18a drives the horizontal deflection input 30a of the display 26a synchronously with its gating of the multiplexer 43 and, since the repetitively interpolated output 27a of the computation unit 11a drives the vertical deflecton input 28a of the display 26a, the display 26a will exhibit a graphical continuous output accurately reflecting, in spatial equivalency, the data values (E 0 , E 1 , E 2 , E 3  and E 4 ) of the transducer array 31 and will include linearly interpolated data values intermediate each adjacent pair of individual transducers. 
     It can be see that since each repetitive integration is initialized at zero and, since the integrator output is scaled by the reciprocal of the sample period (1/T) the one-dimensional linear recursive interpolator described above repetitively implements the following function: ##EQU1## where, time (t) repetitively varies between 0 and T, and, b(t) = the interpolated output between and including the data values of any two adjacent transducers. 
     Accordingly, the interpolated output reflecting the data values of transducers 32 and 33 of FIG. 2 can be written as follows: ##EQU2## where, 0 ≦ t ≦ T. In order to insure that the output 27a (see curves 54 through 54d in FIG. 5) of the one-dimensional linear interpolator of FIG. 3 consists of a series of connected straight line segments, the total update time of the sample and hold circuits 8a and 10a, as determined by the pulse width of pulses 44 and 46, must be small compared to the sample period T. Furthermore, in order to remove switching transients from the output signal line 27a caused by the switching of sample and hold circuits 8a and 10a in response to respectively pulses 46 and 44, circuitry to remove switching transients can be provided as shown in FIG. 6. This circuitry consists of a track and hold circuit 55 controlled by signals along line 56 from the timing control circuit 18a. Removal of transients is accomplished by holding the output 57 of the computation unit 11a at its previous value during the updating time for sample and hold circuits 8a and 10a, respectively the pulse widths of pulses 46 and 44, by means of degliching pulse 58. As will be readily understood, while the level of the degliching pulse 58 is high, the output 59 of the track and hold circuit 55 follows its input 57; when the level of the degliching pulse 58 is low, the output 59 of the track and hold circuit 55 is held at the current value of its input 57. Datel Systems, Inc. Model SHM-2, which is operationally consistent with the foregoing switchology, may conveniently be used for track and hold circuit 55. Although switching transients are thereby removed from the output signal line 59, small distortions are produced in the interpolated output 59 as noted by the flat line segments 60 through 60d in the output curve 61 of FIG. 7 which graphically represents the interpolated output 59. 
     In order to eliminate the one sample period time delay in the interpolated output 27a of the circuit configuration of FIG. 3 a further modification as shown in FIG. 8 may be utilized. The reason for the time delay of one sample period in the circuit of FIG. 3 is that it takes one sample period before sample and hold circuit 10a is updated to the initial transducer 32 value of E 0 . To eliminate this delay, the FIG. 8 circuit configuration utilizes multiplexers 62 and 63 in place of multiplexer 43 and sample and hold circuits 8a and 10a of FIG. 3. The gating of multiplexers 62 and 63 by gate address signals from the timing control circuit 18a along, respectively lines 64 and 65, is synchronized such that multiplexers 62 and 63 will repetitively gate successive transducer values to their respective outputs 66 and 67 at an equivalent rate and with the gating of multiplexer 63 being unitarily shifted with respect to that of multiplexer 64. That is, when multiplexer 62 is gating the data value of transducer 32 to its output 66, multiplexer 63 will simultaneously be gating the data value of transducer 33 to its output 67; during the next sample period multiplexer 62 will be gating the data value of transducer 33 to its output 66 while multiplexer 63 will be simultaneously gating the data value of transducer 34 to its output 67; and so on. As thus seen, data is supplied to the computation unit 11 in a manner similar to that in the FIG. 3 circuit configuration but without the attendant time delay. The interpolated output 27a of the FIG. 8 circuit configuration consequently does not exhibit the one sample period time delay characteristic of the circuitry shown in FIG. 3. 
     Although operation of the recursive interpolator of the present invention has been described with respect to a spatial array of a transducers 31, it is readily apparent that it is likewise applicable to a single time varying transducer. Accordingly, FIG. 9 shows a linear interpolator corresponding to the interpolator of FIG. 3 except that the spatial transducer array 31 and the multiplexer 43 have been replaced by a single time varying transducer 68. Sample and hold circuit 8a will intermittently sample the output of time varying transducer 68 in a manner similar to its sampling of the output of multiplexer 43 and thereby provide an output 27a representing the time interpolated condition of transducer 68. 
     The one-dimensional interpolation scheme described above should be utilized where it is anticipated that a linear relationship exists between the values of adjacent discrete transducer data values. However, since situations may arise wherein a non-linear relationship is expected, the general interpolation system as shown in FIG. 1 may be modified to accomodate a non-linear interpolation scheme. For example, it has been found that in many situations it is desirable to provide an interpolated output which represents a thrid degree equation. Accordingly, an adaptation of the general interpolator of FIG. 1 capable of accomplishing third degree non-linear interpolation is discussed in detail below. 
     There are various well known mathematical schemes which can be implemented to accomplish third degree non-linear interpolation. Two common methods are Legrange&#39;s scheme and Newton&#39;s scheme. However, both of these schemes, as well as any other known scheme, present considerable deficiencies with respect to hardware implementation. For example, the use of Legrange&#39;s scheme introduces poor accuracy into the output because of the hardware inaccuracy of the numerous multipliers required and Newton&#39;s scheme presents timing difficulties since the integrators are reset to a value other than zero. In order to overcome these difficulties and deficiencies in hardware implementation a novel third degree interpolation scheme has been developed. 
     Consider the four discrete transducer values E 0  through E 3  shown in FIG. 10 which represent the first four transducer values of a one-dimensional transducer array such as shown at 69 in FIG. 11. As previously discussed, a linear interpolation between values E 1  and E 2  can be accomplished by hardware implementing the following equation: ##EQU3## where, 0 ≦ t ≦ T. Since the interpolated values immediately preceding E 1  and immediately subsequent to E 3  may effect the interpolation between E 1  and E 2 , the slopes E 10  = E 1  - E 0  and E 32  = E 3  - E 2  would similarly effect the interpolation between E 1  and E 2 . clearly E 10  should effect the interpolation between E 1  and E 2  for values of t close to zero (i.e., the time occurrence of E 1 ) more than should E 32 . Conversely, E 32  should have the greater effect for t close to T (i.e., the time occurrence of E 2 ). And, the two slopes should have the same weight for t = T/2. Finally, any terms added to the basic linear scheme [i.e., equation (3)] must vanish at t = 0 and t = T since the output curve must pass through the values E 1  and E 2 . A novel equation which satisfies these constraints is: ##EQU4## where; E 10  = E 1  - E 0  ; 
     E 32  = e 3  - e 2  ; 
     a 0  is a constant; and 
     0 ≦ t ≦ T. 
     As will be noted, the first two terms of the novel equation (4) constitute the linear term of equation (3) and the remaining term represents a correction term accounting for the effects of slopes E 10  and E 32 . Rearranging the terms of equation (4) yields the hardware form of the equation as follows: ##EQU5## where, E 21  = E 2  - E 1 . 
     It is readily apparent that equation (5) will interpolate between E 1  and E 2  by means of a curve of the third degree. By repetitively reaccomplishing equation (5) for all adjacent transducer pairs in the transducer array, a third degree interpolated output representing the transducer array, in spatial equivalency, results. 
     Since each independent interpolation in the novel third degree scheme utilizes data values from four successive transducers, the hardward implementation of the scheme may incorporate four sample and hold circuits. Accordingly, FIG. 11, which shows an interpolator circuit for implementing the novel third degree interpolation scheme, includes four sample and hold circuits 4b, 6b, 8b and 10b. Except for the computation unit 11b, the remaining circuitry is similar to that shown in FIG. 3. Of course, additional interconnections are required to accomodate the two additional sample and hold circuits 4b and 6b. These additional interconnections include lines 13b, 14b, 20b and 21b. 
     The hardware of the computation unit 11b necessary to implement the third degree scheme of equation (5) is shown in FIG. 12. As shown, the computation unit 11b consists of difference amplifiers 70, 71, 72, 73, 74 and 75 and integrators 76, 77 and 78. Also included are associated scaling resistors for each difference amplifier and for each integrator. Since the operation of the various difference amplifiers are substantially identical, the operating characteristics of difference amplifier 70 will be explained as representative thereof. Initially, after the sample and hold circuits 4b, 6b, 8b and 10b have been updated, respectively, to the values E 3 , E 2 , E 1  and E 0 , it will be noted that voltage E 1  is applied over data line 15b to the positive input terminal 79 of difference amplifier 70 through the voltage divider consisting of resistors R n  and R g . Therefore, the voltage at the positive input terminal 79 of difference amplifier 70 is E 1  R g  / (R n  + R g ). And, the non-inverted output voltage at node 80 of difference amplifier 70, taking into account the scaling effect of feedback resistor R f  and the input resistor R p , is as follows: ##EQU6## Since the values of R g , R n , R p  and R f  are all equal to R 0 , the output at node 80 would reduce to E 1  - E 0 . The output of the integrators 76, 77, and 78 are summated integrations of the inputs thereto scaled by the reciprocal of the constant multiplier of the input resistors R 1 . The voltages at nodes 81 through 88 are shown in the Table of FIG. 13 wherein it is apparent that the voltage at output node 88 implements the novel non-linear third degree equation (5). 
     The operation of the non-linear third degree recursive interpolator of FIG. 11 can be conveniently explained with reference to Table 2 of FIG. 14 and the graph of FIG. 15. It will be noted that during the first sample period T 1  the stored value of sample and hold circuit 4b is E 0  while the remaining sample and hold circuits are at a zero level. Therefore, the only input to the computation unit 11b form the sample and hold tandem during the first sample period T 1  will be along the line 13b from sample and hold circuit 4b. Similarly, during the second sample period T 2  sample and hold circuits 4b and 6b will apply respectively, data values E 1  and E 2  along respectively, lines 13b and 14b to the computation unit 11b; during the third sample period T 3  sample and hold circuits 4b, 6b and 8b will apply respectively, data values E 2 , E 1  and E 0  along respectively lines 13b, 14b and 15b to the computation unit 11b; and, during the fourth sample period T 4  sample and hold circuits 4b, 6b, 8b and 10b will apply respectively, data values E 3 , E 2 , E 1  and E 0  along respectively, lines 13b, 14b, 15b and 16b to the computation unit 11b. 
     Since the computation unit 11b repetitively interpolates between the middle two data values of the four data values repetitively applied thereto (e.g., during sample period T 4  the computation unit 11b will interpolate between data values E 1  and E 2 ), a distorted output, not reflecting an accurate interpolation, will result during the first three sample periods T 1 , T 2  and T 3 . However, beginning with sample period T 4 , four appropriate values are applied to the computation unit 11b by the sample and hold tandem resulting in a true interpolated output. Therefore, in the third degree non-linear scheme shown in FIG. 11, a time delay of three sample periods is introduced before the interpolated output is achieved. Curve 89 of FIG. 15 accordingly shows the third degree recursively interpolated output resulting from the implementation by the computation unit 11b of the novel third degree equation (5). 
     The value of a 0  introduced into equation (4) and (5) and into the scaling resistors of integrator 76 may be chosen to obtain an output third degree curve 89 with the desired degree of inflection. It has been found that an a 0  of 1/2 results in an interpolation scheme closely corresponding to the Newton scheme and therefor has been used in the computation unit 11b and in calculating the voltages in Table 1 of FIG. 13. 
     The timing sequence of the non-linear interpolator of FIG. 11 is substantially equivalent to the timing of the linear interpolator of FIG. 3. Accordingly, the timing control circuit 18b causes sample and hold circuit 10b to sample and be updated first closely followed by sample and hold circuits 8b, 6b and 4b in turn. This updating procedure occurs once for every sample period T. Furthermore, as in the case of the linear interpolator of FIG. 3, the timing control circuit 18b will reset the integrators 76, 77 and 78 to a zero level at the initiation of each sample period. Also, it will be apparent that a transient removal track and hold circuit similar to the track and hold circuit 55 discussed with reference to the linear interpolator can likewise be utilized in the output line 27b of the non-linear interpolator. 
     It will be obvious to one skilled in the art that the general recursive interpolation scheme discussed above can be easily adapted to provide interpolated outputs reflecting curves of various degrees. Such can be accomplished by utilizing an appropriate number of sample and hold circuits or, alternatively, an appropriate multiple multiplexer shifting configuration as described herein, in conjunction with a corresponding computation unit. Therefore, depending upon the specific application, curves of a higher order than 3 may be obtained although, a correspondingly larger time delay will be introduced into the output signal. The time delay could, however, be eliminated by using a multiple multiplexer configuration as previously described herein. 
     In numerous applications transducers are found to exist in two-dimensional arrays rather than one-dimensional arrays. The general one-dimensional interpolator described above can be conveniently adapted to drive an output display corresponding to the spatially interpolated data value distribution of a two-dimensional array of discrete transducers. 
     Consider, for example, the two-dimensional array of M rows of N corresponding transducers each shown in FIG. 16. The two dimensional N × M array of transducers 90, such as thermocouples from which information is to be gathered and displayed in a realtime manner, will comprise the input to the two-dimentional interpolator. One rather obvious method for providing an interpolated output reflecting a two-dimensional array such as 90 is to utilize a series of M independent one-dimensional interpolators, as described above, each of which would independently provide a one-dimensionally interpolated output corresponding to one row of transducers of the transducer array 90. Although the utilization of a series of independent one-dimensional interpolators to provide an output for a two-dimensional transducer array is certainly feasible, it possesses one serious deficiency; namely, although interpolated information is extracted reflecting data values between the columns of each individual transducer rows, no interpolated information reflecting data values between transducer rows is provided. 
     Accordingly, shown in FIG. 17 is a novel combination of the one-dimensional recursive interpolators previously described herein which is adapted to provide interpolated information reflecting data values in the direction of both axes of a two-dimensional transducer array such as generally shown at 90 in FIG. 16. 
     As will be noted from FIG. 17, the outputs of each individual row of N transducers each is applied to the input of a plurality of multiplexers A 1  through A M . The multiplexers A 1  through A M  are simultaneously provided with identical X address gate signals from the frequency divider 91 of the control unit 100 so that they all scan their corresponding transducer row synchronously. The outputs a 1  through a M  of the multiplexers A 1  through A M , which can be considered to comprise a plurality of data sets each of which is identical to the input to the one-dimensional interpolators previously described, are then applied to a series of one-dimensional interpolators B 1  through B M  respectively which, in turn, generate a series of M independent one-dimensional interpolations b 1  through b M  as shown in FIG. 17 and in the graph 18B of FIG. 18. Since the one-dimensional interpolators B 1  through B M  can be substantially identical to the interpolators previously described herein, the M outputs of the B 1  through B M  one-dimensional interpolators are continuous analog functions corresponding to the one-dimensional spatial interpolations of the M one-dimentional arrays of N transducers each (i.e. of the M rows of N transducers each). A clock signal (clock 1) from the frequency divider 92 of the control unit 100 causes the one-dimensional interpolators B 1  through B M  to operate synchrouously (i.e., to update and reset integrators simultaneously) and at a rate equivalent to the gating of multiplexers A 1  through A M . 
     It will next be noted that the b 1  through b M  outputs from the B 1  through B M  one-dimensional interpolators are applied to an M channel multiplexer C. The multiplexer C is caused to scan the b 1  through b M  analog signals by Y address gate signals from frequency divider 93 such that a plurality of scans are accomplished before frequency divider 91 causes the X address to multiplexers A 1  through A M  to be incremented. In other words, during any one sample period, such as T o  in graphs 18B and 18C of FIG. 18, multiplexer C will accomplish a plurality of Y vertical scans during each X horizontal increment. The plurality of Y scans per X increment are applied by the multiplexer C to a one-dimensional interpolator D via the connection line c 0 . The one-dimensional interpolator D can again be substantially identical to the one-dimensional interpolators previously described herein. The operating rate of the one-dimensional interpolator D is sychronized with the scan rate of the multiplexer C by means of the clock 2 input from the frequency divider 94 of the control unit 100. The output Z 0  of the one-dimensional interpolator D is consequently a vertical interpolation of the horizontal interpolations of the one-dimensional interpolators B 1  through B M  as shown in graph 18C of FIG. 18. The series of vertical amplitude interpolations shown in graph 18C can subsequently be utilized to intensity modulate a CRT display 97 as is generally shown by graph 18D of FIG. 18. The X and Y deflection means of the CRT 97 are controlled synchronously with transducer scanning by means of X and Y deflection signals 98 and 99 from respectively digital to analog convertors 95 and 96 thereby assuring that the display corresponds spacially to the discrete transducer array 90. The intensity modulated CRT thereby provides a real-time two-dimensional display of a spatial interpolation of the parameter data values monitored by the discrete transducer array 90. 
     The control unit 100 of the two-dimensional interpolator of FIG. 17 includes four frequency dividers 91, 92, 93 and 94 having, respectively, frequency division factors of N, K, M and R where N equals the number of transducers per row and M equals the number of transducers per column of the transducer array 90. Also included in the control unit 100 is a system clock 101 having a frequency represented by F. As previously mentioned, the multiplexer C scanning rate, controlled by Y address gate signals from frequency divider 93, is synchronized with the sample rate of the one-dimensional interpolator D, the latter being controlled by the clock 2 signal from the frequency divider 94. In a similar manner, the scanning rates of multiplexers A 1  through A M  (all of which are identical) are synchronized with the sample rates of the one-dimensional interpolators B 1  through B M  by means of the X address gate signals from the frequency divider 91 and the clock 1 signal from the frequency divider 92. Furthermore, the scanning rate of multiplexer C is necessarily faster than the operating rate of the one-dimensional interpolators B 1  through B M  by a factor of M X K whereby K scans per X address increment will be applied to the one-dimensional interpolater D. Furthermore, due to the presence of the frequency divider 93, clock 2 will have a frequency of M × K times the frequency of clock 1. Accordingly, the one dimensional interpolator D will have a relatively fast operational rate as compared to the one-dimensional interpolators B 1  through B M . 
     The X and Y deflection signals 98 and 99 for the CRT are derived from the digital to analog converters 95 and 96. Digital to analog converter 95 is driven by the X digital address signal from frequency divider 91 and a digital address signal from frequency divider 92 whereas the digital to analog converter 96 is driven by the Y digital address signal from frequency divider 93 and a digital address signal from frequency divider 94. The digital address inputs to the digital to analog converters 95 and 96 from frequency divider 91 and 93 determine the actual range and rate of the X and Y deflection signals respectively. Digital address inputs from frequency divider 92 and 94 are applied to the converters 95 and 96 since more bits are needed to derive the deflection signals 98 and 99 than are needed for the multiplexer gate address signals in order to provide smooth deflection ramps for the CRT 97. In other words, frequency divider 94 will enable the inclusion of 2 R  steps in each of the 2 M  steps of the Y deflection signal 99 while the frequency divider 92 will enable the inclusion of 2 K  steps in each of the 2 N  steps of the X deflection signal 98. 
     As thus seen, the frequency divider 92 has two functions: (1) to provide extra bits for smoothing the X deflection ramp 98 and (2) to determine the number of scan lines between actual transducer columns. The frequency divider 94 is solely to furnish additional resolution for the Y deflection ramp 99. Accordingly, the system scans and interpolates the entire transducer field at the rate of F/RMKN frames per second. As will be noted, this two-dimensional interpolation scheme provides an output Z 0  reflecting interpolated values between both transducer rows and transducer columns. 
     It is, of course, understood that the one-dimensional interpolators (D and B 1  through B m ) utilized in connection with the two-dimensional interpolation scheme as shown in FIG. 17 may be the one-dimensional interpolators discussed previously herein. Accordingly, the one-dimensional interpolators utilized in the two-dimensional interpolation scheme of FIG. 17 may be either linear or non-linear interpolators. Furthermore, the one-dimensional interpolators may include transient removal track and hold circuits and means may be provided to eliminate any time delay associated therewith. For example, any time delay in the output Z 0  of the two-dimensional interpolator could be partially eliminated by doubling the number of input multiplexers A 1  through A M  and applying a second input directly to each of the one-dimensional interpolators B 1  through B M  as previously taught with reference to the one-dimentional linear interpolator. 
     It will, of course, be understood that the description herein of the preferred embodiments of the invention are intended as exemplary only and not to impose any limitations on the invention.