Abstract:
A semiconductor integrated circuit includes a plurality of stacked slices each configured to have a plurality of vias formed therein so that signals are transferred between the slices arranged in a vertical direction, wherein each of the plurality of slices is configured to transfer a pulse signal, generated during a test section, to a lowest slice of the plurality of slices through the vias connected thereto.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2011-0136547, filed on Dec. 16, 2011, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates to a semiconductor circuit, and more particularly, to a semiconductor integrated circuit. 
         [0004]    2. Related Art 
         [0005]    As shown in  FIG. 1 , a known semiconductor integrated circuit  1  is configured in package form by stacking a plurality of slices and coupling the plurality of stacked slices through vias, for example, through silicon vias (TSVs) so that signals may be transferred between the slices. 
         [0006]    The lowest slice of the plurality of slices may become a master. 
         [0007]    The TSV is a very important element that performs the transfer of a signal between the slices. Accordingly, a via test, which is a test for determining whether the TSV couples different slices electrically, must be performed. 
         [0008]    In the known art, the via test is performed on each of the slices Slice 1  and Slice 2  by using a method comprising of electric current flowing in the TSV through a transistor and measuring the electric current of the master using the monitor pad  11 . 
         [0009]    The method of measuring an electric current, however, has low reliability in a test because the electric current may change due to several internal and external environmental factors. 
         [0010]    If a circuit block  21  (for example, a circuit related to the processing of information for distinguishing slices from one another) is placed between the TSVs as in  FIG. 2 , the via test itself may be undesirable since an electric current may be blocked or greatly changed by the circuit block  21 . 
       SUMMARY 
       [0011]    A semiconductor integrated circuit that enables an efficient and reliable via test to be performed is described herein. 
         [0012]    In an embodiment of the present invention, a semiconductor integrated circuit includes a plurality of stacked slices each configured to have a plurality of vias formed therein so that signals are transferred between the slices arranged in a vertical direction, wherein each of the plurality of slices is configured to transfer a pulse signal, generated during a test section, to a lowest slice of the plurality of slices through the vias connected thereto. 
         [0013]    In an embodiment of the present invention, a semiconductor integrated circuit includes a plurality of stacked slices each configured to have a plurality of vias formed therein so that signals are transferred between the slices arranged in a vertical direction, wherein each of the plurality of slices is configured to transfer an electric current or a pulse signal to a lowest slice of the plurality of slices through the vias connected thereto during a test section. 
         [0014]    In an embodiment of the present invention, a semiconductor integrated circuit includes a plurality of stacked slices each configured to have a plurality of vias formed therein so that signals are transferred between the slices arranged in a vertical direction and a circuit block disposed between two neighboring vias of the plurality of vias, wherein a signal path connected to the two vias is formed within the circuit block, and each of the plurality of slices is configured to generate a pulse signal during each test section, open the signal path, and transfer the pulse signal to a lowest slice of the plurality of slices through the vias connected thereto along the signal path. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0016]      FIG. 1  is a block diagram of a known semiconductor integrated circuit  1 ; 
           [0017]      FIG. 2  is a diagram illustrating the addition of a circuit block that prevents an accurate reading of a via test of the known semiconductor integrated circuit  1 ; 
           [0018]      FIG. 3  is a block diagram of a semiconductor integrated circuit  100  according to an embodiment of the present invention; 
           [0019]      FIG. 4  is a block diagram showing the construction of a test block  600  shown in  FIG. 3 ; 
           [0020]      FIG. 5  is a circuit diagram showing the construction of a pulse generator  610  shown in  FIG. 4 ; 
           [0021]      FIG. 6  is an operation timing diagram of the semiconductor integrated circuit  100  according to an embodiment of the present invention; 
           [0022]      FIG. 7  is a block diagram of a semiconductor integrated circuit  101  according to an embodiment of the present invention; and 
           [0023]      FIG. 8  is an operation timing diagram of the semiconductor integrated circuit  101  according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0024]    Hereinafter, a semiconductor integrated circuit according to the present invention will be described below with reference to the accompanying drawings through various embodiments. 
         [0025]      FIG. 3  is a block diagram of a semiconductor integrated circuit  100  according to an embodiment of the present invention. 
         [0026]    As shown in  FIG. 3 , the semiconductor integrated circuit  100  according to an embodiment of the present invention includes a plurality of slices Slice 0 ˜Slice 2  electrically coupled through vias, for example, TSVs, so that signals can be transferred between the slices. 
         [0027]    In  FIG. 3 , although it may seem that the vias are placed outside the slices, the figure is exaggerated to show the state of connection between the slices. Practically, the vias are formed to penetrate the slices. Furthermore, the lowest slice, a master, may not need a via because it is placed at the bottom. 
         [0028]    From among the plurality of slices Slice 0 ˜Slice 2 , the lowest slice, Slice 0 , may become a master and the remaining slices, Slice 1  and Slice 2 , may become slaves. 
         [0029]    The slice Slice 1  is configured to supply an electric current or pulse to vias connected thereto in response to first test control signals supplied from the master, such as a test mode signal TM and a slice selection signal SSEL. 
         [0030]    The slice Slice 1  includes a control signal generator  500  and a plurality of test blocks  600 . 
         [0031]    The control signal generator  500  is configured to generate second test control signals, such as a test current enable signal TCEN, a test pulse enable signal TPEN, and a test selection signal TMUX in response to the test mode signal TM and the slice selection signal SSEL. 
         [0032]    The slice selection signal SSEL functions to select one of the slices, Slice 1  and Slice 2 . 
         [0033]    The test mode signal TM functions to define the activation of a current test mode or the activation of a pulse test mode. 
         [0034]    Each of the test blocks  600  is configured to supply an electric current or pulse to vias connected thereto in response to the test current enable signal TCEN, the test pulse enable signal TPEN, and the test selection signal TMUX. 
         [0035]    The slice Slice 1  includes a control signal generator  501  and a plurality of test blocks  601 . 
         [0036]    The control signal generator  501  may have the same construction as the control signal generator  500  of the slice Slice 1 , and the test block  601  may have the same construction as the test block  600  of the slice Slice 1 . 
         [0037]    The master is configured to supply control signals that enable the slices to perform via tests in response to external control and to externally provide a process in which the via tests of the slices are being performed in the form of an electrical signal. 
         [0038]    The master includes a control signal generator  200 , a test block  300 , a monitor pad  400 , and a plurality of switches M 1 ˜Mn+1. 
         [0039]    The control signal generator  200  is configured to generate the test mode signal TM, the slice selection signal SSEL, test count signals TEST&lt;1:n+1&gt;, the test current enable signal TCEN, the test pulse enable signal TPEN, and the test selection signal TMUX in response to an address signal ADD. 
         [0040]    The control signal generator  200  may include a shift register for generating the test count signals TEST&lt;1:n+1&gt; and a decoder for generating the test mode signal TM and the slice selection signal SSEL in response to the address signal ADD. 
         [0041]    The control signal generator  200  may further include a logic circuit block for generating the test current enable signal TCEN, the test pulse enable signal TPEN, and the test selection signal TMUX. 
         [0042]    The test block  300  is configured to model the test blocks  600  and  601  of the slices Slice 1  and Slice 2  and is connected to the monitor pad  400  without passing through the vias. 
         [0043]    The test block  300  is added to monitor a difference between a signal transmission characteristic of the test block  600  connected to the monitor pad  400  through the vias and a signal transmission characteristic of the test block  600  connected to the monitor pad  400  without passing through the vias. 
         [0044]    The difference in the signal transmission characteristic includes a electrical load of the via and a difference in the characteristics between the transistor of the slice Slice 1  or Slice 2  and the transistor of the master. 
         [0045]    The monitor pad  400  is used as a terminal for monitoring the via test externally. 
         [0046]      FIG. 4  is a block diagram showing the construction of the test block  600  shown in  FIG. 3 . 
         [0047]    As shown in  FIG. 4 , the test block  600  includes a transistor M 11 , a pulse generator  610 , and a multiplexer  620 . 
         [0048]    When the test current enable signal TCEN is activated at a logic low, the transistor M 11  connects a power supply terminal VDD with the input terminal  0  of the multiplexer  620 . 
         [0049]    When the test pulse enable signal TPEN is activated in a logic high, the pulse generator  610  generates a pulse signal TP and provides the pulse signal TP to the input terminal  1  of the multiplexer  620 . 
         [0050]    The multiplexer  620  connects one of the two input terminals  0  and  1  with the via in response to the test selection signal TMUX. 
         [0051]      FIG. 5  is a circuit diagram showing the construction of the pulse generator  610  shown in  FIG. 4 . 
         [0052]    As shown in  FIG. 5 , the pulse generator  610  includes a NAND gate ND 1  and a plurality of inverters IV 1 ˜IV 4 . 
         [0053]    When the pulse enable signal TPEN shifts to a logic high, the pulse generator  610  generates the pulse signal TP. 
         [0054]      FIG. 6  is an operation timing diagram of the semiconductor integrated circuit  100  according to an embodiment of the present invention. 
         [0055]    A via test method according to an embodiment of the present invention is described below with reference to  FIGS. 3 to 6 . 
         [0056]    In an embodiment of the present invention, a via test may be performed by selecting a pulse method or a current method. 
         [0057]    First, the via test may be sequentially performed on the vias connected to the plurality of switches M 1 ˜Mn, respectively, on the same line. 
         [0058]    Furthermore, the via test may be performed starting from the highest slice, such as slice Slice 2  in the embodiment of the present invention, and then performed on the slice Slice 1 . 
         [0059]    For example, a pulse is generated on the slice Slice 2 . If a logic level of the waveform of the pulse that passes through the vias appears normal on the monitor pad  400 , it means that all the vias on the same line are normal. Accordingly, the via test is sequentially performed from the highest slice to a lower slice. 
         [0060]    The via test using the current method is first described below. 
         [0061]    The control signal generator  200  of the master generates the test mode signal TM to define the current test and the slice selection signal SSEL to define the selection of the slice Slice 2 , in response to the address signal ADD. 
         [0062]    The control signal generator  501  of the slice Slice 2  generates the test selection signal TMUX with a logic low, the test current enable signal TCEN with a logic low, and the test pulse enable signal TPEN with a logic low, in response to the test mode signal TM and the slice selection signal SSEL. 
         [0063]    All the test blocks  601  supply an electric current to the vias connected therewith. 
         [0064]    The control signal generator  200  of the master sequentially activates the test count signals TEST&lt;1:n+1&gt;. 
         [0065]    When the test count signal TEST&lt;1&gt; is activated, or in other words, during a logic high section, an electric current passing through all the vias electrically connected to the switch M 1  flows through the monitor pad  400 . 
         [0066]    Likewise, when the test count signals TEST&lt;1: n+1&gt; are activated, tests in all the vias electrically connected to the switches M 2 ˜Mn+1 are sequentially performed. 
         [0067]    Whether a via is normal or not may be externally determined based on an electric current flowing through the monitor pad  400 . 
         [0068]    If, as a result of the via test, a via is determined to be abnormal, lower slices may be sequentially selected and a test using the same method as that described above may be performed on the selected lower slices in order to detect the abnormal via. 
         [0069]    A via test using the pulse method is described below. 
         [0070]    The control signal generator  200  of the master generates the test mode signal TM to define the pulse test and the slice selection signal SSEL to define the selection of the slice Slice 2 , in response to the address signal ADD. 
         [0071]    The control signal generator  501  of the slice Slice 2  generates the test selection signal TMUX with a logic high, the test current enable signal TCEN with a logic high, and the test pulse enable signal TPEN with a logic high, in response to the test mode signal TM and the slice selection signal SSEL. 
         [0072]    All the test blocks  601  supply repetitive pulse signals to the vias connected therewith. 
         [0073]    The control signal generator  200  of the master sequentially activates the test count signals TEST&lt;1:n+1&gt;. 
         [0074]    When the test count signal TEST&lt;1&gt; is activated, or in other words, during a logic high section, a pulse signal passing through all the vias electrically connected to the switch M 1  is outputted through the monitor pad  400 . 
         [0075]    Likewise, when the test count signals TEST&lt;1: n+1&gt; are activated, tests in all the vias electrically connected to the switches M 2 ˜Mn+1 are sequentially performed. 
         [0076]    Whether a via is functioning as expected or not may be externally determined based on the logic level of the pulse signal outputted through the monitor pad  400 . 
         [0077]    If, as a result of the via test, a via is determined to be abnormal, lower slices may be sequentially selected and a test using the same method as that described above may be performed on the selected lower slices in order to detect the abnormal via. 
         [0078]    The control signal generator  500  of an unselected slice Slice 1  maintains the test current enable signal TCEN with a logic high and the test pulse enable signal TPEN with a logic low. All the test blocks  600  of the unselected slice Slice 1  block an electric current and, at the same time, block the generation of a pulse. 
         [0079]    Here, the master is operated so that the test block  300  is operated according to the same method as the known via test method and an output according to the operation is outputted through the monitor pad  400  via the switch Mn+1 when the test count signal TEST&lt;n+1&gt; is activated. 
         [0080]    In other words, when the via test using the current method is performed, the test block  300  outputs an electric current. When the via test using the pulse method is performed, the test block  300  outputs pulses. 
         [0081]    A change in the electric current of the monitor pad  400  or of a waveform of the pulse signal of the monitor pad  400  when the test count signal TEST&lt;1:n&gt; is activated may be compared with a change in the electric current of the monitor pad  400  or a waveform of the pulse signal of the monitor pad  400  when the test count signal TEST&lt;n+1&gt; is activated externally. A difference between a signal transmission characteristic outputted through the vias and a signal transmission characteristic outputted without passing through the vias may be monitored according to a result of the comparison. 
         [0082]    The difference in the signal transmission characteristic includes a a electrical load of the via and a difference in the characteristics of the transistor of the slice Slice 1  or Slice 1  and the transistor of the master. 
         [0083]      FIG. 7  is a block diagram of a semiconductor integrated circuit  101  according to an embodiment of the present invention. 
         [0084]    As shown in  FIG. 7 , the semiconductor integrated circuit  101  according to an embodiment of the present invention shows an example in which a circuit block  700  is connected between vias. 
         [0085]      FIG. 7  shows an example in which the circuit block  700  is included in a slice Slice 1 , but one or more circuit blocks  700  may be included between other vias. 
         [0086]    The semiconductor integrated circuit  101  according to an embodiment of the present invention may have the same construction as the semiconductor integrated circuit  100  of  FIG. 3  other than the circuit block  700  and the control signal generator  502  of a slice including the circuit block  700 , for example, the slice Slice 1 , and thus a description thereof is omitted. 
         [0087]    The circuit block  700  includes a circuit (not shown) for performing an inherent function and additional tri-state inverters TI 1  and TI 2  for forming a signal path through which an electric current or a pulse signal provided from a slice Slice 2  passes. 
         [0088]    The control signal generator  502  further includes a logic circuit for generating signal path enable signals EN and ENB to control the tri-state inverters TI 1  and TI 2 , as compared with the control signal generator  500  of  FIG. 3 . 
         [0089]      FIG. 8  is an operation timing diagram of the semiconductor integrated circuit  101  according to an embodiment of the present invention. 
         [0090]    The via test method of the semiconductor integrated circuit  101  according to an embodiment of the present invention is similar to the via test method of the semiconductor integrated circuit  100  according to the embodiment of the present invention. 
         [0091]    Unlike in  FIG. 6 , in  FIG. 8 , the signal path enable signals EN and ENB are activated during each via test section for each of the current and pulse methods. 
         [0092]    A signal path ranging from the slice Slice 2  to the circuit block  700  of the slice Slice 1  is formed. An electric current or pulse signal outputted from the slice Slice 2  passes through the vias along the signal path before reaching the monitor pad  400 . 
         [0093]    In accordance with the embodiments of the present invention, reliability of a via test may be improved due to a logic leveling method being used. 
         [0094]    Furthermore, a via test may be performed even if a circuit block is placed between vias. 
         [0095]    While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the semiconductor integrated circuit described herein should not be limited based on the described embodiments. Rather, the semiconductor integrated circuit described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.