Abstract:
A method and a system for controlling a state machine are described. In the method, a script is used via which each arbitrary path in the state machine. The script is created using a language which includes the “data” command, the “data” command allowing reading and writing of data.

Description:
RELATED APPLICATION INFORMATION 
       [0001]    The present application claims priority to and the benefit of German patent application no. 10 2012 210 408.9, which was filed in Germany on Jun. 20, 2012, the disclosure of which is incorporated herein by reference. 
       FIELD OF THE INVENTION 
       [0002]    The present invention relates to a method for controlling a state machine, and a system for carrying out the method. 
       BACKGROUND INFORMATION 
       [0003]    A state machine, also referred to as a finite automaton, represents a model of a system composed of states, state transitions, and actions. The automaton is referred to as “finite” when the quantity of states which the automaton is able to accept is finite. 
         [0004]    A state stores the information concerning the past; i.e., the state reflects the changes in the input since the start of the system up to the present point in time. A state transition indicates a change in the state of the automaton, and is described by a logical condition that must be met in order to allow the state transition. An action is the output of the automaton which occurs in a certain situation. 
         [0005]    A state machine may be represented as a state transition diagram. In addition, different types of transition tables may be utilized. 
         [0006]    State machines are primarily used in the development of digital circuits and in the modeling of the application characteristics of control systems, for hardware and software as well as for mixed systems. 
         [0007]    A number of methods are known for testing electronic units or electronic hardware. The aim of these methods is to recognize faults in the hardware and to eliminate then, which is also referred to as “debugging.” 
         [0008]    The so-called Joint Test Action Group (JTAG) refers to a standard which describes a collection of methods for testing and debugging electronic hardware directly in the circuit. The so-called boundary scan test is one method that is presently widely used. 
         [0009]    The method is used to test the functionality of integrated circuits while they are in their working environment. For this purpose, these integrated circuits may be soldered to a printed circuit board, for example. A JTAG-capable IC may have components which are completely separate during normal operation and which thus do not impair the function of the component. Only by activating the JTAG function by a sequence is the control of certain functions transferred to JTAG. The JTAG interface to the outside environment is generally implemented as a shift register. 
         [0010]    A JTAG component is composed essentially of the following parts: 
         [0011]    the test access port (TAP) together with control lines, which is also referred to as a JTAG port or a JTAG interface; 
         [0012]    the TAP controller, which controls a state machine which controls the test logic; and 
         [0013]    two shift registers, the instruction register (IR) and the data register (DR). 
         [0014]    The test access port (TAP) includes five control lines: 
         [0015]    1. test data input (TDI): serial input of the shift register; 
         [0016]    2. test data out (TDO): serial output of the shift register; 
         [0017]    3. test clock (TCK): the clock signal for the entire test logic system; 
         [0018]    4. test mode select input (TMS): this line determines into which subsequent state the state machine of the test access port skips upon the next positive signal edge of the TCK signal; and 
         [0019]    5. test reset (reset of the test logic system): this signal is optional. 
         [0020]    Multiple integrated circuits may be connected to a JTAG interface. This results in a series connection of the shift registers of the affected ICs. 
         [0021]    The TAP controller is a state automaton which is clocked by the TCK and controlled by the TMS line. The TMS line determines into which subsequent state a skip is made during the next clock pulse. The TAP controller has six stable states, i.e., states in which the system may remain for multiple clock pulses. 
         [0022]    JTAG thus provides an at least partially standardized interface. A microcontroller may be accessed via this interface without assistance from the microcontroller. 
         [0023]    Various methods and languages are known for accessing the microcontroller via the standardized interface, the TAP with the aid of the TAP controller, which may be described as a state machine. Such a language or file format is the so-called Serial Vector Format (SVF), for example. 
         [0024]    SVF is a file format for exchanging boundary scan test vectors. SVF was developed with the aim of describing JTAG operations regardless of the manufacture. 
         [0025]    SVF files contain a sequence of SVF instructions which describe how the JTAG state machine is to be run through. The two essential commands are the scan instruction register (SIR) and the scan data register (SDR) shift instructions. SIR carries out a shift operation into the instruction register, and SDR carries out a shift operation into the data register that is active at that moment, in each case with an indicated number of bits. 
         [0026]    SVF is an ASCII format that is easily read and modified. 
         [0027]    A disadvantage of SVF is that the states of the state machine of the TAP controller may run through only in a predetermined manner. If this is not sufficient, it is not possible to use SVF. 
       SUMMARY OF THE INVENTION 
       [0028]    Against this background, a method for controlling an electronic unit according to Patent Claim  1  and a system for carrying out the method having the features of Claim  7  are presented. Further embodiments of the present invention result from the dependent patent claims and the description. 
         [0029]    The presented method allows a state machine to be controlled, and not just executing or describing predefined paths in the process. This is particularly important for controlling a TAP controller as a JTAG interface. 
         [0030]    A microcontroller is accessed via the JTAG interface without the need for assistance from the microcontroller. SVF, which represents a known script that is standardized, cannot be used in this case. Any given path within the state machine may be taken using the presented method. This is particularly important for microcontrollers, which require a path through the TAP controller that is not covered by SVF. 
         [0031]    In the method, a script is used which is created using a language, i.e., a programming language. Such a language is also referred to as script language. Script languages are programming languages that are primarily used for small, manageable programming tasks. Programs that are written in a script language are referred to as scripts. 
         [0032]    The language used allows scripts to be generated which allow access to the JTAG interface via a system configured for this purpose, i.e., hardware, regardless of the process manufacturer and the chip. 
         [0033]    One advantage of the presented method is the complete flexibility due to generating arbitrary hardware-related sequences for the JTAG TAP controller of the microcontroller; i.e., firmware does not have to be modified in order to, for example, assist new derivatives of the microcontroller or other manufacturers of the microcontroller with new or different JTAG commands. A tool-assisted generation of the corresponding scripts (ASCII file) is made possible. 
         [0034]    However, exact knowledge of the hardware (JTAG TAP controller) is necessary for generating the correct sequences. 
         [0035]    In principle, two commands may be used, namely, “step,” which takes a path without exchanging data, and “data transfer” or “data,” in which a path is taken and data are exchanged. In addition, a loop mechanism may be carried out. 
         [0036]    Command: 
         [0037]    step 
         [0038]    Parameter: 
         [0039]    TDI value 
         [0040]    number of steps 
         [0041]    TMS sequence or bit sequence 
         [0042]    Properties: 
         [0043]    generates a number of rising TCK edges and the specified TMS sequence 
         [0044]    TDI remains constant as specified 
         [0045]    Command: 
         [0046]    data transfer 
         [0047]    Parameter: 
         [0048]    number of bits 
         [0049]    TMS sequence 
         [0050]    TDI sequence 
         [0051]    expected TDO sequence 
         [0052]    TDO bit mask 
         [0053]    Retry count (x) 
         [0054]    definition of a step sequence in order to move the TAP controller back to the start of the data transmission, so that the number of repetitions of this step sequence is displayed 
         [0055]    Properties: 
         [0056]    generates a number of TCK clock pulse edges using the specified TMS and TDI signals 
         [0057]    data transmission is repeatedly carried out until TDO agrees with the expected value, or a number of repetitions are exceeded 
         [0058]    Further commands may be as follows: 
         [0059]    Command: 
         [0060]    request JTAG 
         [0061]    Parameter: 
         [0062]    initial values for TMS, TDI 
         [0063]    Properties: 
         [0064]    JTAG signals are not modified during execution of the command (i.e., no generation of a TCK edge, TCK is high) bus ownership remains until the explicit release via the “release JTAG” command 
         [0065]    Command: 
         [0066]    Release JTAG 
         [0067]    Parameter: 
         [0068]    None 
         [0069]    Properties: 
         [0070]    JTAG signals are not modified during execution of the command (i.e., no generation of a TCK edge, TCK is high) bus ownership is released 
         [0071]    The “request” and “release” commands are necessary only when multiple competing interface devices are connected to a JTAG interface. 
         [0072]    Further advantages and embodiments of the present invention result from the description and the appended drawings. 
         [0073]    It is understood that the features mentioned above and to be explained below are usable not only in the particular stated combination, but also in other combinations or alone without departing from the scope of the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0074]      FIG. 1  shows a TAP controller in a state diagram. 
           [0075]      FIG. 2  shows one system for carrying out the presented method, in a schematic illustration. 
           [0076]      FIG. 3  shows one interface controller. 
           [0077]      FIG. 4  shows signal curves for the “request/release JTAG bus” command. 
           [0078]      FIG. 5  shows signal curves for the “step” command. 
           [0079]      FIG. 6  shows the command structure of the “data” command. 
           [0080]      FIG. 7  shows signal curves of the “data” command. 
           [0081]      FIG. 8  shows signal curves of the “data” command. 
       
    
    
     DETAILED DESCRIPTION 
       [0082]    The exemplary embodiments and/or exemplary methods of the present invention are schematically illustrated in the drawings with reference to specific embodiments, and is described in greater detail below with reference to the drawings. 
         [0083]      FIG. 1  illustrates in a state diagram  10  a TAP controller  11  which is used to control a test logic system. This TAP controller  11  represents a state machine  13  whose behavior is described by state diagram  10 . The illustration shows a number of states and state transitions. The following states are shown: TEST-LOGIC-RESET  12 , RUN-TEST/IDLE  14 , SELECT-DR-SCAN  16 , CAPTURE-DR  18 , SHIFT-DR  20 , EXIT1-DR  22 , PAUSE-DR  24 , EXIT2-DR  26 , UPDATE-DR  28 , SELECT-IR-SCAN  30 , CAPTURE-IR  32 , SHIFT-IR  34 , EXIT1-IR  36 , PAUSE-IR  38 , EXIT2-IR  40 , UPDATE-IR  42 . 
         [0084]    Data input and data output are carried out in the states denoted by reference numerals  20  and  34 , respectively. Illustrated state diagram  10  corresponds to the JTAG standard. 
         [0085]    One sequence, i.e., a succession of state transitions, which cannot be demonstrated using SVF is as follows: 
         [0086]    state  14 —state  16 —state  18 —state  20 —state  22 —state  24 —state  26 —state  28 —state  14   
         [0087]      FIG. 2  shows one of a system for carrying out the presented method, and is denoted overall by reference numeral  50 . The illustration shows a tool  52  on which a script is stored. In addition, access hardware  54  having an arithmetic unit  56  and an interface  58  is depicted. This interface  58 , a JTAG interface, for example, represents the connection to a device  60 . 
         [0088]    The script in tool  52  defines, on a relatively abstract level, which data are transmitted via interface  58  to device  60 . Arithmetic unit  56  executes the script, and for this purpose uses interface  58  which is present in access hardware  54 . 
         [0089]      FIG. 3  shows device  60  from  FIG. 2 , and in particular shows interface  58  in a detailed view. This interface is configured as a multi-core controller, and includes a JTAG HW IF (IF: interface)  72 , a JTAG TAP master  74 , a JTAG core (TAP core 1)  76 , a JTAG core (TAP core  2 )  78 , and a JTAG core (TAP core 3)  80 . Control lines TCK, TMS, TDI, TDO, and optionally TRST are applied at JTAG interface  72 , and registers are associated with each of JTAG cores  76 ,  78 , and  80 . 
         [0090]    It should be noted that each JTAG IF in the controller (TAP) implements the JTAG state automaton. JTAG HW IF  72  terminates in a JTAG master  74 . There are frequently special commands for directing the access from JTAG master  74  to another JTAG TAP. To direct the access from a JTAG TAP back to master  74  or to another TAP, the JTAG state automaton must generally be run through in a special sequence. 
         [0091]      FIG. 3  illustrates one option of a JTAG implementation in which a special sequence must be run through which cannot be demonstrated using SVF. 
         [0092]      FIG. 4  illustrates a time diagram for the “request JTAG” command. The illustration shows, in addition to the curve of the signals at the control lines, the structure of the command, namely, the general command structure in a first row  100  and the specific command structure in a second row  102 . In the first row, a first block  104  contains the command identifier (7 bits), a next block  106  contains the assignment rule 1=request, 0=release (1 bit), and a third block  108  contains an assignment for initial values for TMS, TDI (8 bits). In second row  102 , a first block  110  includes the command identifier (7 bits), a second block  112  includes the assignment “1”=“request,” and a third block  114  includes the assignments TMS=“0,” TDI=“0.” 
         [0093]    The corresponding curves of the signals at the control lines are illustrated therebeneath, namely, TCK  120 , TMS  122 , TDI  124 , BREQ  126 , and BGRANT  128 . 
         [0094]      FIG. 5  illustrates a time diagram for one example of the “step” command. The basic command structure is illustrated in a first row  150 . A second row  152  includes a specific command structure. 
         [0095]    First row  150  includes a first block  154  for the command identifier (8 bits), a second block  156  for the TDI value (8 bits), a third block  158  for field width m in bytes (8 bits), a fourth block  160  for number of steps n (8 bits), and a fifth block  162  for an assignment “N TMS bits” (N≦m * 8). 
         [0096]    Second row  152  includes a first block  180  having a command identifier (8 bits), a second block  182  having an assignment TDI=“0,” a third block  184  having an assignment “field width=0x2,” a fourth block  186  having an assignment “number of steps=0xE,” and a fifth block  188  having an assignment “TMS=0x1803.” 
         [0097]    The corresponding curves of the signals at the control lines are illustrated therebeneath, namely, TCK  190 , TMS  192 , and TDI  194 . 
         [0098]      FIG. 6  illustrates in a first row  200  the general command structure of the data command, and in a second row  202 , a specific structure of the data command. 
         [0099]    First row  200  includes a first block  204  having a command identifier (8 bits), a second block  206  having an assignment for field width m in bytes (8 bits), a third block  208  containing information concerning data bits n (8 bits), a fourth block  210  having an assignment “n TMS bits” (m * 8 bits), a fifth block  212  having an assignment “n TDI bits” (m * 8 bits), a sixth block  214  having an assignment “n expected TDO bits” (m * 8 bits), a seventh block  216  having an assignment “n TDO mask bits” (m * 8 bits), an eighth block  218  having the assignment “TDI repeat value” (8 bits), a ninth block  220  having a repeat count x (8 bits), a tenth block  222  for indicating field width p in bytes (8 bits), an eleventh block  224  for indicating number of steps q for repeat sequence (8 bits), and a twelfth block  226  having an assignment “q TMS bits for repeat sequence” (p * 8 bits). 
         [0100]    Second row  202  includes a first block  234  having a command identifier (8 bits), a second block  236  having an assignment for field width =0x1, a third block  238  containing information concerning the data bits=0x8, a fourth block  240  having an assignment “TMS=0x80,” a fifth block  242  having an assignment “TDI=0x48,” a sixth block  244  having an assignment “expected TDO=0x2A,” a seventh block  246  having an assignment “TDO mask=0x0F,” an eighth block  248  having the assignment “repeat count x=0xA,” a ninth block  250  having the assignment “TDI repeat value =0,” a tenth block  252  for indicating the field width=0x1, an eleventh block  254  for indicating the number of steps=0x4, and a twelfth block  256  having an assignment “TMS=0x03.” 
         [0101]    The corresponding curves at the signal inputs are illustrated in  FIG. 7 , namely, TCK  260 , TMS  262 , TDI  264 , and TDO  266 . This means that the illustrated signal curves are to be applied to the signals in order to execute the mentioned command. 
         [0102]      FIG. 7  consequently illustrates a time diagram for one example of the data transfer command which has successfully concluded; i.e., the TDO value corresponds to the expected TDO value, taking the mask into account. This is ascertained at a point in time  270 . 
         [0103]      FIG. 8  corresponds to  FIG. 7 , except without a successful conclusion; i.e., the access is repeated if the maximum number has not been reached. The curves at the signal inputs are depicted, namely, TCK  280 , TMS  282 , TDI  284 , and TDO  286 . The sequence is repeated up to ten times, for example (arrow  290 ). The TDO value is checked at a point in time  294 . 
         [0104]    The presented method allows a path from one state to a next state to be explicitly specified. In contrast to SVF, no implicit transitions are determined. 
         [0105]    The device to be tested, which may include software and/or hardware, may be externally influenced in a targeted manner. This may be used for testing the device, although possible applications are not limited thereto. Thus, the behavior of a control unit may be modified without the control unit having to actively assist the process.