Abstract:
Described are apparatus and methods for control of multi-channel load switches with synchronized power up/down timing sequences. The slew rate control methods of the PMOS load switches contained in the N Multi-channel configuration is also described. A preferred slew rate control circuit includes a power PMOS transistor that is capable of handling load currents of several amperes along with an integrated controller. The integrated controller allows the user to program the power on/off sequences of each of the load switch channels by simply using a single or multiple input enable input pins.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
       [0001]    Described herein are apparatus and methods for synchronized control of N Multi-channel load switches. These techniques allow for multiple channels that are connected to different power rails to be sequenced in the correct order such that the application subsystems utilizing those power rails would be brought up in the proper sequence and can be powered down with a different sequence. 
       2. Description of the Related Art 
       [0002]    This application is a continuation-in-part (CIP) application of prior application Ser. No. 14/469,270 filed on 2014 Aug. 26, a continuation-in-part (CIP) application of prior application Ser. No. 14/586,586 filed on 2014 Dec. 30, and a continuation-in-part (CIP) application of prior application Ser. No. 14/638,989 filed on 2015 Mar. 4. Present application seeks the same priority as that of these applications. And this application is a non-provisional application of the provisional application with Application No. 62/478,607 filed on 2017 Mar. 30. The entire contents of each of which are incorporated herein by reference. 
       BRIEF SUMMARY OF THE PRESENT INVENTION 
       [0003]    Over the last decade the proliferation of mobile devices has mushroomed. From the creation of the portable digital assistant (PDA) to the development of smart phones, the need for consumers to have more computing power on the go has risen dramatically. The recent development of smart watches has extended that development into even smaller form factors requiring the equivalent computing power of a smart phone but with extended battery life. These new smart watches can be used to connect to a variety of external systems with Bluetooth, text message, or GPS tracking. All of these subsystems need to be managed properly and turned on and off appropriately with the application processor. 
         [0004]    Into this environment has emerged the load switch; a smart version of the Power MOSFET. These load switched can be used to completely remove the power from various subsystems with extremely low leakage currents extending the life of the small watch batteries. However, using multiple independent load switches that are connected to the various subsystems uses valuable board real estate in a smart watch, not to mention the control circuitry needed to synchronize the systems for the proper power up/down sequencing. Furthermore, these different subsystems have different current requirements as well as different turn on/off times. This can cause the smart watch manufacturer to have to have large inventories of several different load switch types possibly from different vendors. 
         [0005]    Entering into this design challenge comes the N Multi-channel load switch with individual power up/down sequencing. Depending upon the requirements, these unique monolithic integrated circuits can contain two, three, or even four uniquely controllable load switch devices which can be controlled individually or synchronously with a single enable pin. In the simplest configuration, the N Multi-channel load switch could have two control pins and an on board decoder that would allow up to 4 load switches to be controlled. This architecture would require the application processor to keep track of the timing sequence of each load switch and issue the appropriate combination of enable signals to the multi-channel load switch at the appropriate time, similar to how one would control a group of individual load switch ICs. This architecture allows for the most flexible design options, however, it burdens the application processor timing circuits to produce the appropriate power up/down timing for each load switch channel. An alternative approach unburdens the processor with the timing requirements and allows the multi-channel load switch to take control of the individual load switch channel timing. In this architecture the timing circuits are off loaded to the load switch IC allowing it autonomous control of the various channels. All the processor has to do is issue a single enable or disable command and the load switch IC will perform the power up/down functions with the appropriate timing for each channel. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1  shows the overall block diagram of general switching circuit (SC)  100  with a synchronization control circuit (SCC)  140 . 
           [0007]      FIG. 2  is a simplified schematic of a single channel of the multi-channel load switches. 
           [0008]      FIG. 3  shows an alternative embodiment of a single channel that can be used as one of the channels on a Multi-channel load switches. 
           [0009]      FIG. 4  illustrates an alternative embodiment of a single channel within the N Multi-channel load switches architecture. 
           [0010]      FIG. 5  shows how a typical N Multi-channel load switch timing synchronization might work. 
           [0011]      FIG. 6  illustrates an embodiment of the N Multi-channel load switch consisting of 4 independent load switches (LS_i)  10   i  with the synchronization control circuit (SCC)  140 . 
           [0012]      FIG. 7  shows an embodiment of the 4 channel load switches with two enable input pins allowing for an independent selection version of 1 out of 4 input voltages. 
           [0013]      FIG. 8  illustrates the configuration of ON/OFF-timing circuits (OTC_i)  81   i  within a synchronization control circuit. 
           [0014]      FIG. 9  shows a block diagram of the synchronization and control block for a single channel of the N Multi-channel load switches. 
           [0015]      FIG. 10  shows the architecture of ON/OFF delay circuit that is used in both the ON and OFF delay functions in the synchronization control circuit (SCC)  140 . 
           [0016]      FIG. 11  illustrates an embodiment of the ON/OFF-timing circuits (OTC_i)  81   i  using a voltage control oscillator (VCO)  111   i / 112   i.    
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0017]    The following description with reference to exemplary and illustration drawings of the present invention will be further described in detail, but the present illustration is not intended to limit the embodiment of the present invention, any similar structure of the present invention and similar changes should be included in the scope of the present invention. 
         [0018]    Below in conjunction with illustration with the  FIGS. 1-11 , the present invention will be described in detail as follows. 
         [0019]    As shown in the  FIG. 1 , the present invention is about a switching circuit (SC)  100  and method of making it that can be connected between external input voltage sources  11   i  and external output loads  12   i,  including at least two or more load switches (LS_i)  10   i  in combination with a synchronization control circuit (SCC)  140  for providing power up/down sequencing for the load switches (LS_i)  10   i,  wherein i represents any integer larger than 0. There are multiple load switches (LS_i)  10   i,  the object of the load switches (LS_i)  10   i  is to protect the load devices  12   i  from any possible overvoltage condition due to a possible inrush current that can be present when connecting the load devices  12   i  to the input voltage sources  11   i.    
         [0020]    Each load switch (LS_i)  10   i  is connected between an input voltage source  11   i  on the V IN   _   LS   _   i  pin to the output load devices on the V OUT   _   LS   _   i  pin. As shown in the  FIG. 2 , each load switch (LS_i)  10   i  has:
       a. a PMOS transistor (PMOS_i)  21   i  with its source and drain respectively connected to the power input V IN   _   LS   _   i  and the power output V OUT   _   LS   _   i ; and   b. a slew rate control circuit (SRCC_i)  22   i  with its input connected to the output V EN   _   SCC   _   OUT   _   i  of the synchronization control circuit (SCC)  140  and having its output connected the gate of the PMOS transistor (PMOS_i)  21   i.          
 
         [0023]    Each PMOS transistor (PMOS_i)  21   i  is connected input voltage sources  11   i  such as a battery or voltage source created by a voltage regulator circuit and an output load device  12   i.  Also included is the slew rate control circuit (SRCC_i)  22   i  that is connected to the gate of the PMOS transistor (PMOS_i)  21   i,  which when turned on will cause the turn on of the power PMOS transistor (PMOS_i)  21   i  and the transition of the voltage at the output of the switch from zero volts to the V IN   _   LS   _   i  voltage, minus a small voltage drop due to the R DSON  of the PMOS transistor (PMOS_i)  21   i.  And when turned off, the slew rate control circuit (SRCC_i)  22   i  will become disabled, thereby saving power during the time that the PMOS transistor (PMOS_i)  21   i  are in the OFF position. 
         [0024]    The slew rate control circuit (SRCC_i)  22   i  can take on many forms to produce the overall result. In the embodiment shown in the  FIG. 2 , the load switch (LS_i)  10   i  consists of an input buffer  23   i  that is connected to the V EN   _   LS   _   i  input. The output of the buffer  23   i  is then connected to an inverter stage that consists of a PMOS pull up transistor labeled M 2  and a NMOS pull down transistor labeled M 1 . In order to control the slew rate of the gate voltage of the PMOS load switch transistor, a resistor is placed in the source of the NMOS pull down transistor. Thus the current generated to pull down the gate voltage of the PMOS load switch will be: 
         [0000]        I   DSCG =( V   GATE   −V   DS(M1) )/ R    (1)
 
         [0000]    The rate at which the gate of the PMOS load switch is discharged can be calculated by using the equation: 
         [0000]      Discharge Time= C   GATE   *V IN/ I   DSCG    (2)
 
         [0025]    Another embodiment of the slew rate control circuit (SRCC_i)  22   i  is illustrate in the  FIG. 3 . The resistor is replaced by a current mirror which obtains a reference current from a stable voltage source such as a band gap reference circuit. The current mirror is then use to divide the reference current by a dividing ratio N in order to obtain the desired I DSCG  current. This technique is used when the turn on time of the power PMOS transistor (PMOS_i)  201  needs to be extended beyond 1-2 ms, which is the practical limit for a resistor based solution. 
         [0026]    Another embodiment of the slew rate control circuit (SRCC_i)  22   i  is illustrated in the  FIG. 4 , which uses a chopped reference current where the chopping is delivered by an oscillator with a prescribed duty cycle in order to extend the turn on time of the power PMOS transistor (PMOS_i)  201  in excess of 30 ms. 
         [0027]    It is noted that in adjusting the slew rate, that there can be adjustments as to both the amount of time that the voltage takes to rise, as well as the extent of the voltage rise. As such, the term “slew rate” is used in the art to refer to both the actual slew rate, as well as to the rise time, and is similarly used herein to mean both; with reference to the rise time being made when that is specifically being discussed. 
         [0028]    The synchronization control circuit (SCC)  140  has: 
         [0029]    a. one or more input(s) V EN   _   SCC   _   IN   _   j , wherein j is an integer lager than 0, and 
         [0030]    b. multiple outputs V EN   _   SCC   _   OUT   _   i , wherein i an integer larger than 1 but smaller than or equal to  2   j  so that the input(s) V EN   _   SCC   _   IN   _   j  can be programmed with their various combinations for individually selecting an LS_i. The V EN   _   SCC   _   OUT   _   i  is/are connected to the V EN   _   LS   _   i . The  FIG. 5  illustrates how the synchronization control circuit (SCC)  140  works. When the EN input signal V EN   _   SCC   _   IN   _   j  is brought to a HIGH level, the sequencing of each of the load switches (LS_i)  10   i  begins. Each of the load switches (LS_i) is enabled after the prescribed delay and the rise time is then executed until the V OUT   _   LS   _   i  level is equal to the V IN   _   LS   _   i  level. When the EN input signal V EN   _   SCC   _   IN   _   j  is brought to a low level, the OFF timing sequence is engaged. Thus the outputs are disabled in the prescribed sequence after executing the appropriate delay sequences. 
         [0031]    As shown in the  FIG. 8 , the synchronization control circuit (SCC)  140  has multiple independent ON/OFF-timing circuits (OTC_i)  81   i.  And as shown in the  FIG. 9 , each ON/OFF-timing circuit (OTC_i)  81   i  has an independent pair of ON Delay sequencing block/circuit (ON-DC_i)  91   i  and an OFF delay sequencing block/circuit (OFF-DC_i)  92   i  connected to a providing desired independently sequenced PMOS transistor (PMOS_i)  201  ON/OFF delay timing(s) relative to the input(s) V EN   _   SCC   _   IN   _   j , wherein j is an integer lager than 0. 
         [0032]    The  FIG. 9  is the basic block diagram of the switching circuit (SC)  100  for one of the load switches (LS_i)  10   i.  There is a load switch (LS_i)  10   i  and an ON/OFF timing circuit (OTC_i)  81   i.  There is an inverter  93   i  connected between EN and the OFF delay sequencing block/circuit (OFF-DC_i)  92   i.  The output of the ON Delay sequencing block/circuit (ON-DC_i)  91   i  is connected to the set of a latch  93   i,  and the output of the OFF delay sequencing block/circuit (OFF-DC_i)  92   i  is connected to the reset of the latch  93   i.  The slew rate control circuit (SRCC_i)  22   i  is enabled by the latch  93   i  after the prescribed ON delay sequencing block/circuit (ON-DC_i)  91   i  time out. Once the slew rate control is engaged, the latch  93   i  is set, and the load switch (LS_i)  10   i  is allowed to turn on and connect the V IN   _   LS   _   i  pin to the V OUT   _   LS   _   i  pin. Once the V EN   _   LS   _   i  pin is brought to a logic LOW level, then the OFF delay is engaged. The OFF delay sequencing block/circuit (OFF-DC_i)  92   i  will time out and then reset the latch  93   i  causing the PMOS transistor (PMOS_i)  201  to be turned off, disconnecting the V OUT   _   LS   _   i  pin from the V IN   _   LS   _   i  pin. 
         [0033]    The  FIG. 10  illustrates the details of the ON delay sequencing block/circuit (ON-DC_i)  91   i  or the OFF delay sequencing block/circuit (OFF-DC_i)  92   i,  and they are identically designed. Each delay counter ON-DC_i  91   i /OFF-DC_i  92   i  consists of an oscillator  101   i / 102   i  and a 2 N  counter  103   i / 104   i  along with some logic. When the V EN   _   LS   _   i  pin is brought to a HIGH level, the oscillator  101   i / 102   i  is enabled and the 2 N  counter  103   i / 104   i  begins to count clock cycles. Once the Nth count has been achieved, the 2 N  output is brought HIGH and the latch  105   i / 106   i  is energized to clock its output HIGH. The COUNT output is then used to enable the slew rate control circuit (SRCC_i)  22   i  to turn on the load switches (LS_i). When the V EN   _   LS   _   i  pin is brought LOW, then the oscillator  101   i / 102   i  is disabled and the 2 N  counter  103   i/   104   i  and the latch  105   i / 106   i  are reset. 
         [0034]    The  FIG. 11  illustrates an embodiment of the ON delay sequencing block/circuit (ON-DC_i)  91   i  or the OFF delay sequencing block/circuit (OFF-DC_i)  92   i.  Each delay counter ON-DC_i/OFF-DC_i  90   i / 91   i  consists of the voltage controlled oscillator (VCO)  111   i / 112   i  and a 2 N  counter  103   i/   104   i  along with some logic. When the EN pin is brought to a HIGH level, the voltage controlled oscillator (VCO)  111   i / 112   i  is enabled and the 2 N  counter  103   i/   104   i  begins to count clock cycles. Once the Nth count has been achieved, the 2 N  output is brought HIGH and the latch  105   i/   106   i  is energized to clock its output HIGH. The COUNT output is then used to enable the slew rate control system to turn on the load switch. When the EN pin is brought LOW, then the voltage controlled oscillator (VCO)  111   i / 112   i  is disabled and the 2 N  counter  103   i/   104   i  and the latch  105   i / 106   i  are reset. For achieving an additional degree of flexibility for a user in adjusting ON delays, an extra input connected to an adjustable off-chip resistor for adjusting an input voltage of the voltage controlled oscillator (VCO)  111   i / 112   i.    
         [0035]    The  FIG. 6  illustrates a specific embodiment of the invention with four load switches (LS_i)  10   i.  In this embodiment, each of the load switches (LS_i)  10   i  can be independently sequenced into the ON state by the synchronization control circuit (SSC)  140  similar to the sequencing shown in the  FIG. 5 . 
         [0036]    The  FIG. 7  illustrates an embodiment of the invention with four load switches (LS_i)  10   i.  In this embodiment, the synchronizing controller (SSC)  140  is allowed to only enable one of the four channels at any one given time according to the input HIGH/LOW levels of the two enable input pins, EN 1  and EN 2 .