Abstract:
A low power timekeeping system utilizes a state machine to first read seconds stored in a RAM and update seconds and then determine if the minutes requires updating. If the minutes do not require updating then the sequencer stops operation until the next update cycle. Similarly, the minutes, hours, days of the week, date of the month, month, and year are updated only as needed in each update cycle thereby lowering the power requirement needed by the timekeeping system.

Description:
REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of application Ser. No. 08/571,677, filed Dec. 13, 1995; which is a continuation of application Ser. No. 08/142,755, filed Oct. 25, 1993; which is a division of application Ser. No. 07/717,215, filed Jun. 18, 1991 (U.S. Pat. No. 5,267,222); which is a continuation of application Ser. No. 07/208,889, filed Jun. 17, 1988 (U.S. Pat. 5,050,113). 
     Reference is made to a first related application entitled DUAL STORAGE CELL MEMORY INCLUDING DATA TRANSFER CIRCUITS, U.S. Pat. No. 4,873,665, issued Oct. 10, 1989, to Jiang et al.; to a second related application entitled DYNAMIC CMOS BUFFER FOR LOW CURRENT SWITCHING, U.S. Pat. No. 4,876,465, issued Oct. 24, 1989 to Podkowa et al.; to a third related application entitled DELAY CIRCUIT PROVIDING SEPARATE POSITIVE AND NEGATIVE GOING EDGE DELAYS, application Ser. No. 07/208,288, filed Jun. 17, 1988, now abandoned; to a fourth related application entitled ARBITRATION OF DATA WRITTEN INTO A SHARED MEMORY, application Ser. No. 07/208,890, filed Jun. 17, 1988, now abandoned; to a fifth related application entitled DYNAMIC PLA TIMING CIRCUIT, U.S. Pat. No. 4,959,646, issued Sep. 25, 1990, to Podkowa et al. These applications and patents disclose and claim a dual memory cell, a dynamic buffer circuit, a one shot circuit, arbitration circuitry, and timing circuitry for use with a PLA ROM respectively which are used in the preferred embodiment of the present invention. 
    
    
     TECHNICAL FIELD 
     The present application pertains to timekeeping circuits and, more particularly, to low power timekeeping circuits. 
     BACKGROUND OF THE INVENTION 
     Most computers include a timekeeping module or system which keeps track of the present time of day and date using its own oscillator. These timekeeping systems receive their primary power from the computer system but have backup batteries in order to preserve the time data when the primary power source fails. Since the useful life of the backup battery depends generally on the amount current drawn by the timekeeping system, the power supply current used by the timekeeping system generally determines how often battery replacement is required. Therefore it can be appreciated that a timekeeping system which operates with a relatively small amount of power supply current is highly desirable. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of this invention to provide a timekeeping system which requires a relatively small amount of power supply current. 
     Shown in an illustrated embodiment of the invention is a method for keeping time which includes reading seconds data from a memory, incrementing the seconds data, and storing the incremented seconds data back into the memory. If the seconds data, before being incremented, was 59 seconds, then the minutes data is read, incremented, and the incremented minutes data is stored in the memory. If the minutes data, prior to being incremented, was at  59  minutes, then the hours data is read from the memory, incremented, and the incremented hours data is stored back into the memory. 
     Also shown in an illustrated embodiment of the invention is a method for keeping time in a timekeeping system which includes a sequencer, a memory, and an accumulator connected together by a data bus which includes placing the seconds data onto the data bus by the memory and reading the seconds data in the accumulator. The accumulator increments the seconds data and writes the incremented seconds data onto the data bus. The incremented seconds data is stored in the memory and the memory holds the incremented seconds data on the data bus until at least a next read operation by the memory or a next write operation by the accumulator. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The aforementioned and other features, characteristics, advantages, and the invention in general, will be better understood from the following, more detailed description taken in conjunction with the accompanying drawings in which: 
     FIG. 1 is a block diagram of a timekeeping system according to the present invention; 
     FIGS. 2A-2E are logic diagrams of the data bus interface circuitry for the sequencer, accumulator, and common memory of FIG. 1; 
     FIG. 3 is a schematic diagram of a dual memory cell used in the common memory of FIG. 1; 
     FIG. 4 is a block diagram of the PLA portion of the sequencer of FIG. 1; 
     FIGS. 5A-5E are flow diagrams of the timekeeping system according to the present invention; and 
     FIG. 6 is a timing diagram of certain signals in the timekeeping system of FIG.  1 . 
    
    
     It will be appreciated that for purposes of clarity and where deemed appropriate, reference numerals have been repeated in the figures to indicate corresponding features, and that the timing signals shown in FIG. 6 have not necessarily been drawn to scale in order to more clearly show timing relationships in the preferred embodiment of the present invention. 
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A timekeeping system according to the preferred embodiment of the present invention consists primarily of an oscillator, a sequencer, a memory, and an accumulator. Various signal lines connect the major blocks of circuitry listed above, and the sequencer, memory, and accumulator are also connected by two data buses, an A data bus and a B data bus. 
     In operation a clock line from the oscillator to the sequencer is usually at a logic 1 level, but becomes a pulse train for a period of time at one second intervals. The sequencer is a state machine which performs an update cycle each second. The update cycle consists of two segments, an update sequence for updating the time stored in the memory, and an alarm sequence for comparing the present time to alarm data stored in the memory. When the clock signal into the sequencer transitions to a logic 0 level to begin the pulse train, the sequencer begins the update cycle by performing first the update sequence. The update sequence consists of reading the seconds data from the memory, testing the seconds data to see if it reads 59 seconds, incrementing the seconds data and writing the incremented seconds data back to the memory. If the seconds data was not 59 seconds, then the sequencer enters into the alarm sequence. If the seconds data was 59 seconds, then the minutes data is read, incremented, and written back into the memory. If the minutes data was not 59 minutes, then the sequencer enters into the alarm sequence, and if the minutes data was 59 minutes, then the sequencer reads hours. In a similar manner the sequencer, as required, updates the hours, days of the week, date of the month, month, and year data stored in the memory. 
     When the sequencer enters the alarm sequence, the present seconds data is compared to the alarm seconds data and if a match is not found the sequencer sends a signal to the oscillator to hold the clock line at a logic 1 level. If a match is found, then the minutes alarm data is compared to the minutes present time data, if a match is found then the hours alarm data is compared to the hours present time data. If an hour match is found then a signal is sent from the sequencer indicating that the alarm match has been made. At this point the sequencer again sends a signal to the oscillator to hold the clock line at a logic 1 level. 
     The A data bus is used to transfer the present time data between the sequencer in the memory and the accumulator. The B data bus is used either to provide a second number to the accumulator from the sequencer or to transfer the alarm data from the memory to the accumulator. Since in the majority of the times the sequencer will read the seconds data and increment the seconds data and then enter into the alarm sequence in which the seconds data is reread to be compared to the alarm seconds data, the data on the A bus usually changes state only once per update cycle thereby saving the power supply current which would be required to charge and discharge the lines of the A data bus several times during each update. 
     The timekeeping system of the present invention advantageously saves power by sequencing only as far in the update cycle and the alarm cycle as is needed during each update cycle and being inactive during the rest of the one second interval, therefore requiring only a small amount of power supply current. Thus, the electrical energy required for each update cycle varies with the amount of time data required to be updated. Also, the sequencer in the preferred embodiment uses a PLA array of ratioless logic which provides a low power state machine. Moreover, since the A data bus usually only changes once and the B data bus usually stays at the same logic state during each update cycle, the amount of current required to charge and discharge these data buses is minimal for each update cycle on the average. 
     Turning now to the drawings, FIG. 1 is a block diagram of a timekeeping system  10  according to the present invention. The timekeeping system  10  includes an oscillator  12  which is connected by several lines  13  to a sequencer  14 . The sequencer  14  is connected to a system bus  16  which is also connected to an accumulator  18  and a common memory  20 . The common memory  20  is connected to a computer interface  22  which in turn is connected to a computer bus  24 . 
     The common memory  20  includes an array of dual memory cells as described in the aforementioned related Patent entitled DUAL STORAGE CELL MEMORY including data transfer circuits and incorporated herein by reference. The common memory  20  allows a user to write the present time into the common memory through the computer bus interface  22 . As will be described later, other data is also loaded and stored in the common memory  20  through the computer bus interface  22 . In order to avoid collisions between the present time entered by the user on the computer bus  24  and the time being written into the common memory by the sequencer  14 , arbitration logic is contained within the timekeeping system  10  as described in the aforementioned related application entitled ARBITRATION OF DATA WRITTEN INTO A SHARED MEMORY and incorporated herein by reference. 
     FIG. 2A is a block diagram of the system bus  16  which includes an A data bus  26  and a B data bus  28 . Both the A data bus  26  and the B data bus  28  each have eight data lines and are connected to the sequencer  14 , the accumulator  18 , and the common memory  20 . Each of the eight lines of the A data bus  26  is connected in an interface circuit  30 , inside the common memory  20 . The eight data lines of the A data bus  26  are also connected to an interface circuit  32  in the accumulator  18  and to the address lines of a PLA array in the sequencer  14 . Each of the eight data lines of the B data bus  28  are connected to an interface circuit  34  in the common memory  20  and to an interface circuit  36  in the accumulator  18 . Each of the eight data lines of the B data bus  28  is connected to eight data lines in the PLA array inside the sequencer  14 . The accumulator  18  includes an ALU circuit  38 , the output of which on lines  39  is fed back into the interface circuits  32 . 
     FIG. 2B is a logic diagram of the interface circuit  30  wherein one of the lines  40  of the A data bus  26  is connected to the input of an input buffer  42  and also to one of the data terminals of a transmission gate  44 . The control terminals of the transmission gate  44  are connected to complementary control signals which enable or disable the transmission gate  44 . The other signal terminal of the transmission gate  44  is connected to the Q output of a D latch  46 . The D latch  46  receives a clock signal from inside the common memory  20 . The D input of the D latch  46  is connected to the output of an OR gate  48 , one input of which is connected to a data line  50  in the common memory  20 . The second input of the OR gate  48  is connected to the output of an AND gate  52 . One input of the AND gate  52  is connected to the output of the buffer circuit  42 . The output of the buffer circuit  42  provides one data input line to the common memory  20 . The second input of the AND gate  52  is connected to a control signal inside the common memory  20 . 
     The interface circuit  30  operates during a memory read operation by latching the data on a data line  50  into the D latch  46  while the output of the AND gate  52  is held at a logic  0  level. The Q output of the D latch  46  is passed through the transmission gate  44  onto the A bus  26 . During a memory write operation the transmission gate  44  is made nonconductive and the data on line  40  is passed through the buffer  42  to write circuitry inside the common memory  20 . Also during a memory write operation, the data at the output of the buffer  42  is passed through the AND gate  52  and the OR gate  48  and latched into the D latch  46 . After the memory write operation, the transmission gate  44  is made conductive so that the common memory  20  is holding the data on the A bus  26  which was just previously written into the common memory  20 . 
     The interface circuit  32  in FIG. 2C includes a buffer  54 , a transmission gate  56 , and a D latch  58  which are configured like the buffer  42 , the transmission gate  44 , and the D latch  46  of FIG.  2 B. However, the interface circuit  32  does not include the OR gate  48  or the NAND gate  52  of FIG.  2 B. 
     Similarly, the interface circuit  34  shown in FIG. 2D includes a transmission gate  60 , one signal input of which is connected to one line  62  of the B data bus  28 . The other signal input of the transmission gate  60  is connected to the Q output of a D latch  64  which receives data from the common memory  20  at the D input of the D latch  64  and also receives a clock signal at the clock input of the D latch  64 . Thus, the interface circuit  34  is able to provide data onto the B data bus  28 , but not to read data from the B data bus. 
     The interface circuit  36  as shown in FIG. 2E includes only a buffer circuit  66  for receiving data from the B data bus  28 . 
     FIG. 3 is a schematic diagram for the dual memory cell  68  used in a portion of the common memory  20  and described in detail in the aforementioned related application entitled DUAL STORAGE CELL MEMORY. The memory cell  68  shown in FIG. 3 includes an upper timekeeping portion  70  which includes two additional lines  72  and  74  not shown in the aforementioned related application entitled DUAL STORAGE CELL MEMORY. Each of the lines  72  and  74  are connected to the data nodes inside the six-transistor memory cells of the timekeeping section  70  of the dual memory cell  68 . These additional lines  72  and  74  are connected to buffer circuitry (not shown) and allows data to be read directly out of these cells without requiring a normal read operation in the common memory  20 . Thus, the data taken from these memory cells Is continuously available. These logic cells shown in FIG. 3 are used in the common memory  20  for those cells storing the day of the week, date of the month, month, and year and are provided to the sequencer  14  on the system bus  16  and used by the sequencer  14  in a manner described below. 
     Turning now to FIG. 4, a block diagram of the PLA  70  including a PLA array  72  as shown. The PLA  70  and the PLA array  72  are described in the aforementioned related Patent entitled DYNAMIC PLA TIMING CIRCUIT which is hereby incorporated by reference. The PLA circuit receives a plurality of address lines  74  which are connected as inputs into an address decoder circuit  76 . The address decoder circuit  76  provides true and complementary address lines into the PLA array  72  for each of the address lines  74 . The PLA circuit  70  also includes a plurality of data lines  78  which are connected to precharge and latch circuits  80  as described in the aforementioned related Patent entitled DYNAMIC PLA TIMING CIRCUIT. Two additional data lines  82  and  84  are connected as inputs to dynamic buffer circuits  85  and  86  which are described in the aforementioned related Patent entitled DYNAMIC CMOS BUFFER FOR LOW CURRENT SWITCHING which is hereby incorporated by reference. The outputs of the buffer circuits  85  and  86  form timing signals T 1  and  72  respectively which are also connected as inputs to two one-shot circuits  88  and  90 , the outputs of which form signals T 1 P and T 2 P respectively. The one shot circuits  88  and  90  are described in the aforementioned related application entitled DELAY CIRCUIT PROVIDING SEPARATE POSITIVE AND NEGATIVE GOING EDGE DELAYS and incorporated herein by reference. 
     Seven of the data lines  78  form signals NS 0 -NS 6  which are the next state data lines which are used as inputs into the address decoder circuit  76 . The outputs of the address decoder circuit  76  corresponding to the next state input lines forms the present state address lines into the PLA array  72 . 
     The address lines  74  consist of 23 addresses, 7 of which are the next state data lines out of the PLA array, and 8 of which come from the A data bus  26 . The remaining consist of a FEB address line which is high (logic 1 level) when the present month is February; an LEAP address line which is high when the present year is a leap year; a THRT address line which is high when the present month has 30 days; an HRM address line which is high when the stored data is for a 24 hour clock and low (logic 0 level) when the data is for a 12 hour a.m., p.m. clock; a DM address line which is high when the data is stored in binary format and low when the data is stored in BCD format; an S line which is high on the first Sunday of April, the day when the switch is made from standard time to daylight savings time; an F address line which is switched high at the start of the last Sunday in October when the switch is made from daylight savings time to standard time; and an EQLZ address line which is one when the accumulator compares the data on the A bus  26  and the B bus  28  and finds the two buses have the same data. The FEB, LEAP, THRT, S, and F address lines are formed by combinational logic in the sequencer  14  from data taken from the signal lines  72  and  74  of the timekeeping cells  68  storing the present day of the week, date of the month, month, and year data. 
     There are 29 data lines  78  out of the PLA array  72  not including the two timing lines  82  and  84 . The 29 data lines include eight data lines providing data to the B data bus  28  and the seven data lines for the next state into the address lines  74  of the PLA  70 . The other data lines are as follows: a UDC data line which when ANDed together with the T 2 P timing signal forms a signal back to the oscillator to tell the oscillator to hold the clock signal on lines  13  from the oscillator to the sequencer at a logic 1 level until time for the next update cycle; an ALMF data line which provides a signal to an interrupt mask circuit in the common memory  20  which, if enabled by the user, will cause an interrupt to be presented on the computer bus  24  and is used to signal that an alarm match has been found; four data lines TAD 0 -TAD 3  which are address lines into the common memory  20 ; an ALPHA data line which is used to reset a latch circuit when the timekeeper switches from daylight savings time to standard time to 1:00 a.m. on the last Sunday in October. This ALPHA signal changes the state of the F address line so that the sequencer won&#39;t set its time back one hour more than once each year. An RWB data line signal the memory whether to read or write data; an RAMEN data line which, when at a logic 1, enables the common memory  20  to read or write data and when at a logic 0 causes the common memory  20  to precharge the timekeeping bit lines in the memory; an ALMM line to signal that the sequencer is in an alarm sequence rather than a time update sequence; three signal lines S 0 -S 2  to the accumulator  18  to control whether the accumulator is to transfer data from the B bus onto the A bus, to increment the data on the A bus or to add the A bus to the B bus and place the resultant on the A bus; and a CI data line as a carry input into the accumulator  18 . 
     These address lines and data lines are combined in the PLA array  72  to provide the operational sequence shown in the flow chart of FIG.  5 . As shown in FIG. 5 the sequencer  14  begins an update cycle in block  100  by first reading seconds data which corresponds to a present state address of  7 A. Following the  7 A state the sequencer  14  enters into the  7 E state in which it evaluates the seconds data and then performs one of three operations: either to add seven to the seconds data (state  3 F) if the seconds data is in BCD format and the time is X 9  (e.g. 09,19,29, etc.) but not 59; load  00  into the accumulator if the seconds data is at 59 either in BCD or binary format and go to state  3 E; or, if neither of the previous conditions are satisfied, to add one to the seconds data (state  79 ). 
     If the sequencer  14  enters state  7 F or  3 F, then the next operation is a write into the memory of the data on the A bus shown as state  7 D. After this write in state  7 D the sequencer enters into the alarm sequence shown in FIG.  5 E. Thus, in 59 cases out of 60 the sequencer will have progressed from reading the seconds data, updating the seconds data, writing the seconds data back into the common memory, and then entering into the alarm sequence. 
     If the sequencer enters into state  3 E, it then writes 00 seconds data back into the memory and then enters into a precharge cycle  7 C in which the timekeeping bit lines in the common memory are precharged prior to a read operation and also the minutes address into the memory is selected. The next cycle is a read minutes operation, state  75 . The state  75  is followed by a state  77  which is similar to the state  7 E for the seconds operation. If the minutes data is at 59 minutes, then 00 is written into the minutes portion of the memory and the memory is again precharged in step  6 C and the address is selected in order to read the hours in step  6 E. If the minutes data is not 59 minutes, the minutes data is incremented (state  7 F or  3 F), written into the memory (state  7 D), and the sequencer begins the alarm sequence. 
     After the hours are read, the sequencer enters step  6 A which has many options depending on whether the data is binary or BCD, whether the time is for a 12 hour clock or a 24 hour clock, whether the hours are switching from 11 a.m. to 12 p.m., from 11 p.m. to 12 a.m., from 12 p.m. to 1 p.m. or from 12 a.m. to 1 a.m., and whether it is time to switch between standard time and daylight savings time. If the hour data rear is not 12:00 a.m., then the hour data is incremented (state  7 F or  3 F), written into memory (state  7 D), and the sequencer begins the alarm sequence. 
     If the hour is changing to 12:00 a.m., then the sequencer reads the day of the week, updates the day of the week, and reads the date of the month, and, if the date is the last day of the month, updates the date of the month in state  65  to  01  and reads the month data. If the date is not the last day of the month, the date is incremented (state  7 F or  3 F), written into memory (state  7 D), and the sequencer begins the alarm sequence. The date of the month change is determined by the number of days in the particular month and whether the year is a leap year or not. 
     If the month is changing to January, then the year data is read and updated. If the month read is not December, then the month data is incremented (state  7 F or  3 F), written into memory (state  7 D), and the sequencer begins the alarm sequence. After the year data is updated, the sequencer begins the alarm sequence. 
     As shown in FIG. 5E the alarm sequence consists of first precharging the timekeeping bit lines in the common memory  20  (step  6 D) and then reading the seconds data and the seconds alarm data (step  6 F) and then enabling the ALU to compare the data on the A data bus  26  and the B data bus  28 . If there is a match in step  6 B, then the minutes data and minutes alarm data is read in step  79  and another comparison is made in step  78 . If the minutes match, then the hours and the hours alarm data is read and compared and if there is a match at this point, then the alarm flag is set in step  76 . Any time a match is not made the sequencer branches to state  7 B which precharges the timekeeping bit lines of the common memory, sets the address lines to read the seconds data, and issues a command on data line UDC to cause the oscillator to hold the clock line to the sequencer at a logic 1 level until the next update cycle. 
     FIG. 6 is a timing diagram showing the clock signal from the oscillator  12  to the sequencer  14  for the first two states of the sequencer  14 . At time  110 , the signal from the oscillator  12  goes from a logic 1 to a logic 0 after being held high after the last update cycle. This transition at time  110  initiates another update cycle. Prior to time  110 , the sequencer  14  is in a precharge operation. At the time  110  the sequencer  14  enters an evaluate cycle and timing signals T 1 , T 2 , T 1 P, and T 2 P shown in FIG. 6 are generated. The falling edge of the T 1  signal generates the T 1 P signal which latches the data out of the PLA array  72  and the T 2 P timing pulse is used to control the transmission gates connected to the lines on the A data bus  26  and the B data bus  28 . Following the initial evaluate cycle the sequencer  14  enters into another precharge cycle and this process is repeated until the sequencer enters into state  7 B at which time it sends a signal to the oscillator to hold the clock line at a logic 1 level until the next update cycle is to begin. In the preferred embodiment the pulse train out of the oscillator  12  into the sequencer  14  shown in FIG. 6 has a frequency of 4096 HZ, the T 1  and T 2  delay times are on the order of 0.5 microseconds, and the T 1 P and T 2 P pulses have a width of about 50 nanoseconds. 
     Significantly, the data on the A data bus  26  changes only once in 58 out of every 60 update cycles since the sequencer only reads seconds unless the seconds data is at 59 or if the seconds data matches the seconds alarm data. Also after each write operation, the incremented seconds data is written into the memory and immediately written back onto the A data bus by the interface circuit  30  of the common memory  20 . 
     Thus, there has been described a timekeeping system which operates with a minimum number of sequential states and which minimizes the number of logic level changes on the primary data bus to thereby provide a low power timekeeping system in comparison to systems which read all time data on each update cycle or which use approximately the same electrical energy for each update cycle. 
     Although the invention has been described in part by making detailed reference to a certain specific embodiment, such detail is intended to be, and will be understood to be, instructional rather than restrictive. It will be appreciated by those skilled in the art that many variations may be made in the structure and mode of operation without departing from the spirit and scope of the invention as disclosed in the teachings contained herein.