Abstract:
Integrated circuits are designed having optimal signal timing between and among cells. A set of identities are generated corresponding to logic operations and to library cells in technology basis. A resynthesis window is created for the identities having less than a predetermined depth of critical variables. Logic equations of the resynthesis window are transformed using the identities, and the resynthesized window area is optimized.

Description:
FIELD OF THE INVENTION 
   This invention relates to design of integrated circuits, and particularly to designing integrated circuits having optimal signal timing. 
   BACKGROUND OF THE INVENTION 
   Integrated circuits (ICs) comprise plural cells each consisting of one or more circuit elements, such as transistors, capacitors and other devices, grouped to perform a specific logic function. Each cell has one or more pins which are connected by wires to one or more pins of other cells of the IC. A net is the set of pins connected by the wire; a netlist is a list of nets of the IC. The IC may also include plural functional circuit blocks, such as central processing units, memories and input/output interface units. The cells and circuit blocks are represented as standard designs in technology-specific circuit libraries. The IC is constructed using selected circuit blocks and millions of cells. 
   Computer aided design (CAD) tools are used in most phases of the circuit design and layout processes. The layout is typically partitioned by grouping the components into blocks defining subcircuits and modules and interconnecting the blocks with wires according to the netlist. Routing channels are defined between the blocks of a layout, and wires connect the blocks along the shortest possible paths within the channels. 
   One measure of the performance of an IC is expressed by the time delays, including propagation delays and setup/hold delays, within the circuit. Propagation delays include the time required for a signal to travel from the input to the output of a cell. A setup delay is the time required by the cell that a signal must be available at an input prior to a clock signal transition. A hold delay is the time duration that a signal is required to be stable after a clock signal transition. 
   An important consideration in the design and layout of ICs is the optimization of signal timing through the IC so that signals are available at the correct pin just in time for an event to be performed by the cell. In the past, signal timing optimization was addressed after initial layout of the blocks and during the routing of wires between the blocks. Timing considerations often led to repositioning blocks and re-routing the wires during this design phase. The present invention is directed to a technique of optimization that is applied to the logical equations in operations of the technology basis to maximize signal timing optimization. 
   SUMMARY OF THE INVENTION 
   In one embodiment of the invention, a plurality of identities are generated representing a union of the axioms of plural logic operations and the functional definitions of the cells in a given technology basis. A resynthesis window is created, and the resulting logic equations are transformed through the identities. The resynthesis window area is then optimized. 
   In other embodiments of the invention, the process is carried out by a computer operating under the control of a computer readable program that contains computer readable code that, when read and processed by the computer, causes the computer to perform the process. In preferred embodiments, the computer readable program is embedded on a computer readable medium, such as a recordable disk of a computer disk drive. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a flow chart of the process of the present invention. 
       FIGS. 2-5  are flow charts of portions of the process illustrated in FIG.  1 . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The present invention is based on a preliminary generation of identities in the technology basis. The identities minimize the depth of variables with critical timing. The generation of identities is automatic, so the timing optimization procedure is independent from the choice of a specific technology basis. 
     FIG. 1  is a flowchart illustrating the general procedure of the present invention. At step  100 , a preliminary set of identities for the given technology basis are generated. A resynthesis window is created at step  200 , and its logical equations are transformed for better applicability of identities. The logical equations are transformed through the identities at step  300 . At step  400  final resynthesis window area optimization is performed without degrading timing. 
   Step  100 . Identities Generation. 
   An identities generation algorithm is used to generate identities in the technological basis. Each identity diminishes the depth of a variable (e.g., x 1 ). In the process of timing optimization, this variable is identified by a subexpression of critical timing. While generation of identities of only one variable is considered critical, we have discovered numerous situations where an identity diminishes timing for critical and quasi-critical variables. 
   The process  100  of generating preliminary identities for the technology basis is illustrated in the flow chart of  FIG. 2. A  subset M of most frequently used current design logic operations of the technology basis (for example, NOT, OR, AND, NOR, NAND, XOR, MUX, etc.) is selected at step  110 . The number of inputs m of each operation is not more than some predetermined number, such as  4 . To obtain a practical number of identities, it is desirable to select not more than about 30 to 40 logic operations in subset M. 
   At step  112 , a list of initial identities is created. Each identity is a union of (1) the axioms of the logic operations in M and (2) the definitions of functions of the logic cells of the technology basis in terms of logic operations. The left parts of these identities are enumerated. There are two types of left parts, expressions with a depth 2 and expressions with depth 3. At step  114  an enumeration is made of all expressions of depth 2, having a form f 1 (y 1  . . . y i−1 f 2 (x 1  . . . . x n )y i+1  . . . y m ), where f 1 ,f 2  are from subset M. Here, y 1 , . . . y m ,x 1 , . . . ,x n , are different variables. Expressions are considered identical if they can be transformed to another by reordering operands of “symmetrical” operations f 1  and by renaming all of the variables except x 1  (x 1  is considered as critical by timing). During enumeration of the left parts of the identities, some of these left parts would be created as identities themselves, as described below. 
   After completing enumeration of the left parts of depth 2, enumeration of left parts that have depth 3 is performed at step  116 . Here, the expressions take on the form f 1 (z 1  . . . z i-1 f 2 (y 1  . . . y j−1 f 3 (x 1  . . . x n )y j+1  . . . y m )z i+1  . . . z k ). All expressions that have a subexpression A from depth 2 are excluded from this enumeration because an identity A=B has already been generated. 
   For every left part T of the identity that appears during enumeration process, an attempt is made to generate a corresponding right part pursuant to steps  118 - 130 . 
   At step  118 , constants 0,1 are substituted for variable x 1  in the left part expression T of the identity, creating results R 0 ,R 1 . Simple identities are applied for logical constants (i.e., 1νx=1; 0νx=x, etc.). An expression R=x 1 ·R 1 ν−x 1 ·R 0  is created, where disjunction, conjunction and negation are elements of the basic set of operations M. 
   At step  120 , expression R is optimized by a timing optimization procedure using identities that have double occurrences of the same variable in right part. Application of this identity is equivalent to modification of factoring (that is, regrouping of implicants, oriented to diminishing the critical variable depth). The process of timing optimization for R assumes that timing of variable x 1  is greater than sum of delays of all operations in R, and that timings of other variables in R are equal to 0. The simplest model of timing is used here so that each operation in M has a fixed delay. The result of transformations of the expression R is designated by H. 
   Maximal subexpressions P 1 , . . . ,P n  are selected at step  122  from expression H that do not have variable x 1 . Arbitrary new variables y 1 , . . . ,y n  (that is, variables not used in H) are selected at step  124  and an auxiliary system of logical equations y 1 =P 1 , . . . ,y n =P n  in technology basis is created. More particularly, the logical equations are transformed to basis OR, AND and NOT. The right parts of equations are transformed to disjunctive normal form and minimized (by an ordinary flattening procedure). A factoring procedure is applied to system of equations. Finally, a procedure of mapping-to-gates is applied to system of equations. It may be necessary to add additional new variables z 1 , . . . ,z m  during the factoring procedure. These new variables are designations for some subexpressions, B 1 , . . . B m , that have more than one occurrence in equations. The transformation of the auxiliary equations results in a new system of equations y 1 =Q 1 , . . . ,y n =Q n ,z 1 +B 1 , . . . ,z m =B m . 
   At step  126 , expression D is created by replacing subexpressions P 1 , . . . ,P n  in expression H with Q 1 , . . . , Q n . The result is an identity T=D. However, if m&gt;0, the identity is supplemented, as indicated at step  128 , with a system of equations z 1 =B 1 , . . . ,z m =B m , which are definitions of auxiliary variables z 1 , . . . ,z in D. These identities (where m&gt;0) can be considered “identities with definitions”. 
   Increments of timing and area for replacement of T to D are calculated at step  130 . For example, for the simplest timing model, every operation from M has fixed delay and area, variable x 1  has fixed “large” timing, and other variables have timing 0. If the decrease of timing is not less than given parameter Δ, and the increase of area is not more than given percent S, then the identity with definitions T=D is registered in list of resulting identities. Otherwise the identity is missing. Parameters Δ, S are determined experimentally. In experiments, we chose Δ as one-half of the mean delay of operations from M, and S as 40%. 
   For two examples of identities generated by this procedure, assume
         AO1(x 1 x 2 x 3 x 4 )=NOT(AND(OR(x 1 x 2 )x 3 x 4 )) and   AO2(x 1 x 2 x 3 x 4 )=NOT(OR(AND(x 1 x 2 )AND(x 3 x 4 ))).
 
The first of these identities is
   AO1(x 2 x 3 x 4 AND(x 1 x 5 ))=NAND(x 1 NOT(AO1(x 2 x 3 x 4 x 5 ))),
 
which is the usual identity for replacement of left part to right part. The second identity is
   AO2(OR(x 1 x 2 )x 3 x 4 x 5 ) AO1(x 1 OR(x 3 x 6 ));x 6 =AND(x 4 x 5 ),
 
which is an identity with a definition of auxiliary variable x 6 .
       

   Step  200 . Generation of resynthesis window and transformation of equations. 
     FIG. 3  is a flow chart of the process of step  200  in  FIG. 1. A  list C of all critical timing cells of the netlist is created by standard procedures. At step  210  binary trees are formed having levels of vertices. The vertices represent logical cells, and are arranged such that each vertex representing a cell inside the tree (i.e., at levels other than a bottom level of the tree) has its output connected to another vertex representing another cell of the same tree. The bottom level vertices represent output cells. The tree is “maximal”, in the sense that no cell can be added to it. The tree is used to generate a window for resynthesis. At step  212 , a tree is selected containing an output cell v in list C. The tree containing output cell v gives a logical equation of the resynthesis window as y=F. If the maximal depth of variables with critical timing in F is not less than some parameter d, then the window is expanded. 
   Window expansion is performed at step  214  by identifying all trees that have inputs connected to output of cell v. The resynthesis window is expanded to include all identified trees. Hence, all trees containing a cell connected to an output of cell v are included in the expanded tree. The resulting tree adds new logical equations z 1 =G 1 , . . . ,z n =G n  for resynthesis. 
   Variable y appears in all expressions G 1 , . . . ,G n  for the output of cell v. Variable y is eliminated from the resynthesis window by substituting F for y in all expressions G 1 , . . . ,G n  and by deleting equation y=F. This transformation often increases the depth of variables with critical timing, and therefore creates more possibilities for application of identities generated above, although application of any such identity requires a depth of at least 2, and preferably 3. 
   The process of window expansion and transformation continues until the depth of critical variables in all equations is less than d, and total complexity of the equations is less than some critical value. 
   Step  300 . Logical Equation Transformation. 
   Let y 1 =F 1 , . . . ,y n =F n  be the system of logical equations, in terms of technology basis operations, for the current resynthesis window. Elaboration of these equations is performed as described in the flow chart of FIG.  4 . 
   All subexpressions G of expressions F i  having critical timing and a depth not less than 2, are selected. If a subexpression G has a depth of 2 or less, it is ignored. Each subexpression G is presented in form
 
f 1 ( . . . f 2  ( . . . f m (A 1  . . . A p ) . . . ) . . . ), 
 
where f i+1  are operands of operation f i  with maximal timing, and m&lt;4. An identity T with left part of the same form f 1 ( . . . f m ( . . . ) . . . 0 . . . ) is selected from the base of identities. Variable x 1  of the selected identity T is identified with operand A j  having a maximal timing.
 
   The total number of identities may appear to be very large. Since the left parts of the identities have “linear” structure of operations, the identities can be organized into tree-like databases for a quick search. Since the time required to perform the search is logarithmic of the number of identities, the quick search is possible for millions of such identities. When the identity T is found, the result G′ of application of T to subexpression G is considered, and the decrement δ of timing for F i  is computed. After all subexpressions G are considered, a variant of transformation G→G′ is selected, which gives maximal diminishing of timing (i.e., minimal decrement δ, δ&lt;0). This transformation G→G′ is realized, and the cycle is repeated. Transformations are continued until δ is less than 0. If an identify T defined some auxiliary variables, then the definitions of these variables are included in the list of equations. 
   Step  400 . Final Resynthesis Window Area Optimization. 
     FIG. 5  is a flow chart illustrating the process of step  400  in FIG.  1 . At step  410  subexpressions T are found in equations y 1 =F 1 , . . . y n =F n  of the resynthesis window that have more than one occurrence. New variables z are selected, and at step  412  all occurrences of T in equations are replaced with z. An equation z=T is added to system of equations. These transformations are necessary to remove duplications that appeared in the equations as a result of elimination of variables in step  200 . Alternatively (or supplementally), duplication can be removed by selecting non-critical (by timing) subexpressions P 1 , . . . , P m  of the equations and minimizing their complexity by standard area optimization cycles of flattening, factoring and mapping-to-gates. Replacement of subexpressions P i  by result R i  of such cycle is permissible if it does not negatively impact the results of timing optimization. 
   While the invention has been described as a process, in preferred embodiments the invention is carried out by a computer under the control of a computer readable program comprising computer readable code embedded in a computer readable medium. The code of the computer readable program causes the computer to carry out the processes herein described. The computer readable program may be part of a computer aided design program for carrying out the process to design integrated circuits having millions of cells. 
   Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.