Abstract:
A process for fabricating an interconnect structure, featuring contact of the interconnect structure, to an exposed side of an underlying conductive plug structure, where the conductive plug structure is used to communicate with an active device region in a semiconductor substrate, has been developed. The process features the use of simple photolithographic patterns, such as a stripe opening, exposing a group of gate structures, and a group of spaces, located between the gate structures, to be used for subsequent contact plug formation. This is in contrast to conventional processing, in which a more difficult photolithographic procedure is used to create smaller, individual openings, to individual spaces between gate structures. In addition this invention features a self-aligned opening, exposing only a side of a contact plug structure. An overlying interconnect structure then contacts only the exposed side of the underlying contact plug structure, again reducing photolithographic difficulties, encountered with conventional methods of creating a non-self aligned opening to an underlying contact plug.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form an interconnection between an overlying bit line and an underlying contact plug. 
     2. Description of the Prior Art 
     The objective of the semiconductor industry, to continually decrease the size of dynamic random access memory, (DRAM), or static random access memory, (SRAM), devices, used for advanced integrated circuits, (IC), is dependent on the ability of specific semiconductor disciplines, to improve processes and tools, that will enable device features of less than 0.25 um, to be realized. Advances in photolithographic exposure tools, have allowed short wavelengths, using KrF, (248 nm), or ArF, (193 nm), to be achieved, however to achieve features of 0.1 um, or less, specific semiconductor elements, such as conductive interconnect structures, and the fabrication processes needed to create these elements at reduced dimensions, are needed, in addition to the advances in photolithographic disciplines. 
     This invention will describe a novel process resulting in structural innovations that will allow sub-quarter micron features, to be achieved without taxing the photolithographic discipline, by increasing exposure resolution, or by demanding more sensitive photolithographic alignment and critical image control. One features of this invention is the use of merging three contact plug openings, created self-aligned to adjacent gate structures, via use of a single stripe type contact opening, therefore easing patterning difficulties encountered with conventional processes, in which individual openings are formed to individual plug structures. In addition this invention also features the use of a bit line structure, self-aligned to, and contacting the sidewall of, an underlying contact plug structure, in a non-active device region, thus easing the patterning procedure, used with conventional bit line contacts in which an opening to a plug structure is formed in an active device region. Prior art, such as Witek et al, in U.S. Pat. No. 5,393,681, as well as Woo et al, in U.S. Pat. No. 5,451,543, describe methods of forming sidewall contacts, however these prior arts do not describe the merged contact plug approach, or the sidewall contact of a bit line structure to a contact plug, in a non-active device region. 
     SUMMARY OF THE INVENTION 
     It is an object of this invention to create ultrasmall interconnect structures, for semiconductor devices, using simplified patterns. 
     It is another object of this invention to create an merged contact pattern, in a silicon oxide layer, simultaneously exposing a series of regions, located between gate structures, to be used for contact plug structures, thus reducing the complexity of conventional patterning procedures, in which individual openings are made to individual regions, located between gate structures. 
     It is still another object of this invention, to create a bit line opening, in a silicon oxide layer, self-aligned to adjacent gate structures, and to an adjacent contact plug structure, allowing a subsequent bit line structure, to contact the sidewall of a contact plug structure. 
     In accordance with the present invention a method is described for forming a self-aligned interconnect structure, contacting the sidewall of an underlying contact plug, using simplified photolithographic patterns. After formation of a series of silicon nitride capped, polycide gate structures, with source/drain regions located between the polycide gate structures, silicon nitride sidewall spacers are formed, leaving a thin layer of silicon nitride remaining on the top surface of the source/drain regions. A simple stripe opening, is created in an overlying first silicon oxide layer, exposing a series of openings, between polycide gate structures, still covered by the thin layer of silicon nitride. After removal of the thin layer of silicon nitride, located between polycide gate structures, individual contact plug structures, are formed on the source/drain regions, located between polycide gate structures, via a deposition of a conductive layer, followed by a chemical mechanical polishing procedure. A bit line opening is created in a second silicon oxide layer, self-aligned to adjacent, silicon nitride encapsulated, polycide gate structures, and exposing the side of a contact plug structure, located between silicon nitride encapsulated, polycide gate structures. Deposition and patterning of a conductive layer, results in the creation of a bit line structure, located overlying the second silicon oxide layer, and located in the bit line opening, contacting the side of the contact plug structure. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The object and other advantages of this invention are best described in the preferred embodiments with reference to the attached drawings that include: 
     FIGS. 1B, 2, 3B, 4, 5B, 6B, 6C, which schematically, in cross-sectional style, show key stages of fabrication used to create an interconnect structure, self-aligned to, and contacting, the side of a contact plug structure. 
     FIGS. 1A, 3A, 5A, 6A, which schematically show the top view, at key stages of fabrication of an interconnect structure, self-aligned to, and contacting the side of, an underlying contact plug structure. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The method of fabricating an interconnect structure, self-aligned to, and contacting the side of, an underlying contact plug structure, will now be described in detail. This invention will be described using NFET devices, however it should be noted that this invention can be also be applied to PFET devices. A P type semiconductor substrate 1, comprised of single crystalline silicon, with a &lt;100&gt; crystallographic orientation, is used and schematically shown, in cross-sectional style, in FIG. 1B. Shallow trench isolation, (STI), regions 2, are used for isolation purposes, defining active device region 21, schematically shown, in the top view of FIG. 1A. STI regions 2, are formed via creating shallow trenches, between about 2000 to 4000 Angstroms, in depth, in semiconductor substrate 1, via conventional photolithographic and anisotropic RIE procedures, using Cl 2  as an etchant. After removal of the photoresist shape, used for definition of the shallow trenches, via plasma oxygen ashing and careful wet cleans, a silicon oxide layer, obtained via low pressure chemical vapor deposition, (LPCVD), via plasma enhanced chemical vapor deposition, (PECVD), or via high density plasma chemical vapor deposition, (HDPCVD), procedures, is deposited completely filling the shallow trenches. Unwanted regions of the silicon oxide layer are next removed using either a chemical mechanical polishing, (CMP), procedure, or using a selective, reactive ion etching, (RIE), procedure, using CHF 3  as an etchant, resulting in the insulator filled, STI regions 2, schematically shown in FIG. 1B. 
     A silicon dioxide, gate insulator layer 3, is next thermally grown, in an oxygen-steam ambient, to a thickness between about 30 to 80 Angstroms. A series of depositions are next performed, the first being polysilicon layer 4, obtained via LPCVD procedures, at a thickness between about 500 to 1500 Angstroms. Polysilicon layer 4, can be in situ doped, during deposition, via the addition of arsine, or phosphine, to a silane ambient, or polysilicon layer 4, can be deposited intrinsically, then doped via ion implantation of arsenic or phosphorous ions. A metal silicide layer 5, such as tungsten silicide, is next deposited, using LPCVD procedures, at a thickness between about 500 to 1500 Angstroms, followed by the deposition of silicon nitride layer 6, obtained via LPCVD or PECVD procedures, at a thickness between about 1500 to 3000 Angstroms. Conventional photolithographic and RIE procedures, using CF 4  as an etchant for silicon nitride layer 6, and using Cl 2  for both metal silicide layer 5, and for polysilicon layer 4, are employed to create silicon nitride capped, polycide, (metal silicide-polysilicon), gate structures 7-10, schematically shown, in cross-sectional style, FIG. 1B, and with a top view, shown schematically in FIG. 1A. The photoresist shape, used for definition of the polycide gate structures, is removed via plasma oxygen ashing and careful wet cleans, which also removes regions of gate insulator layer, not covered by the polycide gate structures. 
     Lightly doped, N type, source/drain regions, (not shown in the drawings), are formed in regions of the semiconductor substrate, not covered by the silicon nitride capped, polycide gate structures, via an ion implantation procedure, using arsenic or phosphorous ions, at an energy between about 20 to 40 KeV, and at an implant does resulting in a surface concentration of between about 1E17 to 1E19 atoms/cm 3 . A silicon nitride layer lla, shown schematically in FIG. 1B, is next deposited via LPCVD or PECVD procedures, to a thickness between about 300 to 600 Angstroms. 
     A blanket, anisotropic RIE procedure, using CF 4  /CHF 3  as an etchant, is next used to thin silicon nitride layer 11a, creating thin silicon nitride layer 11b, now between about 100 to 300 Angstroms in thickness, in regions overlying silicon nitride layer 6, and on the surface of semiconductor substrate 1, in regions between the silicon nitride capped, polycide gate structures, while forming silicon nitride spacers 11c, on the sides of the silicon nitride capped, polycide gate structures. This is schematically shown in FIG. 2. Heavily doped, N type source/drain regions, (not shown in the drawings), are next created in regions of semiconductor substrate 1, not covered by the silicon nitride capped, polycide gate structures, or by silicon nitride spacers 11c, via ion implantation of arsenic or phosphorous ions, at an energy between about 50 to 150 KeV, at an implant dose resulting in a surface concentrattion between about 1E19 to 1E21 atoms/cm 3 . Silicon oxide layer 12, is next deposited, via LPCVD or PECVD procedures, at a thickness between about 5000 to 10000 Angstroms, using tetraethylorthosilicate, (TEOS), as a source, followed by a CMP procedure, used to create a smooth top surface topography for silicon oxide layer 12. This is schematically shown in FIG. 2. 
     FIGS. 3A, (top view), and 3B, (cross-sectional), schematically show the result of exposing a group of regions, to be used to subsequently accommodate contact plug structures, self-aligned to the silicon nitride capped, polycide gate structures. First a photoresist shape 22, with a stripe opening, identical in dimensions and location to a previous photoresist shape, used for definition of the active device region 21, (FIG. 1A), is used as a mask, to allow a selective RIE procedure, using C 4  F 8  as an etchant, to remove exposed regions of silicon oxide layer 12. The selectivity, or etch rate ratio of silicon oxide to silicon nitride, is about 10 to 1, allowing this cycle of the RIE procedure, to slow at the appearance of thin silicon nitride layer 11b. Next an in situ removal of thin silicon nitride layer 11b, is performed, using CH 3  F/O 2  as an etchant, creating self-aligned contact, (SAC), openings 13, 14, and 15, schematically shown in cross-sectional style, in FIG. 3B, and schematically shown for the top view, in FIG. 3A. The etch rate ratio of silicon nitride to silicon oxide, using CH 3  F/O 2  as an etchant, is between about 5 to 1. The main purpose of the stripe opening, using photoresist shape 22, is to avoid the photolithographic patterning procedures, in terms of alignment, and critical image, that is encountered in conventional openings of individual SAC openings. The trend to narrow polycide widths, can present difficulties even when an narrower photoresist shape is used to form the SAC opening, where the SAC opening has to overlap the polycide gate structure. The use of the stripe opening, merging a group of SAC openings, relieves the difficult photolithographic procedures, encountered with conventional, individual SAC openings. 
     After removal of photoresist shape 22, via plasma oxygen ashing and careful wet cleans, contact plug structures 24, are formed, in SAC openings 13-15, self-aligned to the silicon nitride capped, polycide gate structures. Contact plug structures 24, can be comprised of polysilicon or tungsten. The contact plug structures, are initially formed via LPCVD procedures, at a thickness between about 3000 to 6000 Angstroms, completely filling SAC openings 13-15. If polysilicon is used, doping is accomplished in situ, during deposition, via the addition of arsine, or phosphine, to a silane ambient. A CMP procedure is next employed to remove unwanted regions of polysilicon, (or tungsten), followed by the removal of regions of silicon oxide layer 12, with the CMP procedure stopping at the appearance of silicon nitride, resulting in conductive plug structures 24, in SAC openings 13-15. This is schematically shown in FIG. 4. 
     Silicon oxide layer 16, is next deposited, using LPCVD or PECVD procedures, at a thickness between about 1000 to 2000 Angstroms, again using TEOS as a source. A photoresist shape, is then used as an etch mask, to allow bit line contact opening 17, to be created in silicon oxide layer 16, and in silicon oxide layer 12, via a selective RIE procedure, using C 4  F 8  /CO as an etchant, stopping at the appearance of thin silicon nitride layer 11b, located at the bottom of bit line contact opening 17. The etch rate ratio, between silicon oxide, and either silicon nitride or polysilicon, is between about 10 to 1, using C 4  F 8  /CO as an etchant. The result of this procedure exposes a side of contact plug structure 24. In order to insure that the side of contact plug structure 24, will be exposed, bit line contact opening 17, is designed to slightly overlap contact plug structure 24, resulting in the exposure of portion of the top surface of contact plug structure 24, in bit line contact opening 17. FIG. 5A, shows bit line contact opening 17, self-aligned to silicon nitride capped, polycide gate structure 8, In addition, to selectively forming opening 17, using C 4  F 8  /CO, and stopping on silicon nitride layer 11b, opening 17, can be formed only to a depth of between about 1500 to 3500 Angstroms, in silicon oxide layer 12, still resulting in exposure of a portion of contact plug structure 24. This is schematically shown in FIG. 5B. 
     After removal of the photoresist shape, used to define bit line contact opening 17, via plasma oxygen ashing and careful wet cleans, bit line interconnect structures 19, and 20, are formed. Bit line contact interconnect structures can be a polycide structure, comprised of an underlying, N type, in situ doped polysilicon layer, and an overlying tungsten silicide layer, or bit line contact interconnect structure can be comprised tungsten, on an underlying adhesive-barrier layer, of titanium-titanium nitride. The polycide version is obtained via LPCVD procedures, at a thickness between about 1500 to 2500 Angstroms, completely filling bit line contact opening 17, while the tungsten bit line interconnect layer can be obtained using either LPCVD or R.F. sputtering procedures, at a thickness between about 1000 to 2000 Angstroms, again completely filling bit line contact opening 17. Conventional photolithographic and anisotropic, and selective RIE procedures, using Cl 2  for polysilicon, or using SF 6  /Cl 2 , for tungsten, as an etchant, are used to create bit line interconnect structures 19, and 20, shown schematically in a top view, in FIG. 6A, and shown in cross-sectional style in FIGS. 6B and 6C. FIG. 6B, schematically shows the desired contact between bit line interconnect structure 20, and contact plug structure 24, occurring mainly at the side of contact plug structure 24. The use of the bit line interconnect structure, contacting the side of the contact plug structure, in an area overlying the non-active device region, allows a reduced active device region to be used. Counterpart designs, employing a bit line contact opening, directly on the top surface of an underlying contact plug structure, would have needed a larger active device region, to accommodate possible misalignment problems. FIG. 6C, schematically, in cross-sectional style, shows the active device region, without the bit line contact opening, and bit line interconnect structure. The photoresist shape, used for definition of the bit line interconnect structures, is once again removed via plasma oxygen ashing and careful wet cleans. 
     While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of this invention.