Abstract:
An integrated circuit test apparatus includes a testing board having at least two divided test sites thereon and at least two devices under test (DUT) disposed on their corresponding test site respectively with at least one associated independent ground.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a DUT (device under test) testing board, and more particularly, to a DUT testing board having separated test sites with at least one independent associated grounds for reducing interference during testing.  
           [0003]    2. Description of the Prior Art  
           [0004]    Semiconductor testing of ICs or chips is required at various stages during the fabrication process. Each IC must be individually tested in the wafer and in a packaged form manner to ensure that it functions as intended. As chips become more and more powerful and complicated, the needs of high-speed and accurate tests become more and more important accordingly.  
           [0005]    A testing board is used to interface the DUTs (device-under-test). Typically, a number of DUTs are disposed on the testing board at the same time. FIG. 1 is a schematic diagram exemplarily showing configuration of two devices, DUT 1  and DUT 2 . As shown in FIG. 1, the DUT 1  and DUT  2  share the same signal ground DG and the power supply ground  2 . The signal ground DG is for grounding signals, and the power supply ground  2  is for grounding the power supply.  
           [0006]    [0006]FIG. 2 is a cross-sectional, schematic view illustrating a prior art testing board structure. The DUT 1  and DUT 2 , for example, are mounted on the top plate (TOP) as known by those skilled in the art. Four interplates (IN 1 , IN 2 , IN 3 , and IN 4 ) are mounted between the top plate (Top) and the bottom plate (BOT). Each of the four inter plates is disposed a data ground (DG). Furthermore, a first device power supply (DPS 1 ) and a third device power supply (DPS 3 ) are disposed on the inter plate IN 2 , and, a second power supply (DPS 2 ) and a fourth power supply (DPS 4 ) are disposed on the inter plate IN 3 . As shown in FIG. 2, these data grounds on the inter plates are electrically connected.  
           [0007]    However, one drawback of such configuration is that if one device such as DUT 1  is interfered due to the noises, the other device like DUT 2  will be affected also because with the same data (signal) ground. Consequently, the need to provide an interference-reduced IC testing system for devices under tests is necessary.  
         SUMMARY OF THE INVENTION  
         [0008]    It is a primary object of the present invention to provide an IC test apparatus for accurately and simultaneously testing at least two devices.  
           [0009]    According to the claimed invention, the test apparatus includes a testing board having divided test sites and electrically disconnected data grounds on these test sites. At least two devices under test (DUTS) are disposed at different divided test sites on the testing board.  
           [0010]    It is to be understood that both the forgoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. Other advantages and features of the invention will be apparent from the following description, drawings and claims. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    [0011]FIG. 1 is a schematic diagram showing configuration of two devices: DUT 1  and DUT 2 .  
         [0012]    [0012]FIG. 2 is a cross-sectional, schematic view illustrating a prior art testing board structure.  
         [0013]    [0013]FIG. 3 is a diagram depicting arrangement of a testing board according to one preferred embodiment of this invention.  
         [0014]    [0014]FIG. 4 is across-sectional, schematic diagram conceptually showing the testing board structure as depicted in FIG. 3 according to the present invention.  
         [0015]    [0015]FIG. 5 is a schematic diagram conceptually illustrating connection between the devices under test and the power supply. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0016]    [0016]FIG. 3 is a diagram depicting arrangement of a testing board according to one preferred embodiment of this invention. As shown in FIG. 3, two devices, for example, DUT 1  and DUT 2 , are mounted on different test sites of the testing board  1 . Different test sites are distinguished by at least one distinguishing line  13 , and each of the DUT 1  and the DUT 2  has its own grounds. In this embodiment, these grounds can be power grounds (SG) for grounding the power supply, signal grounds SG 1  And SG 2  for grounding the signals, reference grounds DG 1  and DG 2  for the purpose of grounding other devices.  
         [0017]    [0017]FIG. 4 is a cross-sectional, schematic diagram conceptually showing the testing board structure as depicted in FIG. 3 according to the present invention. In this embodiment, an exemplary six-layer testing board is demonstrated in FIG. 4. Note that this invention is not limited to six-layer testing boards. As shown in FIG. 4, reference grounds DG 1  and DG 2  are disposed on the TOP plate. On the second plate (IN 1 ), a power ground SG for grounding the power supply (+5V and +15V) of the testing system is mounted between the reference grounds DG 1  and DG 2 . On the third plate (IN 2 ), signal grounds SG 1  and SG 2  for DUT 1  and DUT 2  respectively and device power supply DPS 1  and DPS 3  are disposed. Another power ground SG is located between the DPS 1  and DPS 2  on the third plate IN 2 . On the fourth plate (IN 3 ), DUT signal grounds SG 1  and SG 2  for DUT 1  and DUT 2 , respectively, and device power supply DPS 2  and DPS 4  are disposed on the fourth plate IN 3  too. Another power ground SG is located between the DPS 2  and DPS 4  on the fourth plate IN 3 . On the fifth plate (IN 4 ), reference grounds DG 1  and DG 2  are disposed. Another power ground SG is located between the reference grounds DG 1  and DG 2  on the fifth plate IN 4 . DUT signal grounds SG 1  and SG 2  on the fourth plate IN 3  and the reference groundsDG 1  and DG 2  are electrically connected with magnetic devices like L 1  and L 2  respectively to form new reference grounds. Finally, on the bottom plate (BOT), reference grounds DG 1  and DG 2  for DUT 1  and DUT 2 , respectively, are disposed. In this embodiment, the test site for DUT 1  and the test site for DUT 2  are both independent and devices DUT 1  and DUT 2  are with different and independent power grounds, signal grounds, and reference grounds. That is, noises affect DUT 1  will not interfere DUT 2  during testing.  
         [0018]    [0018]FIG. 5 is a schematic diagram conceptually illustrating connection between the devices under test and the power supply. In FIG. 5, DUT signal ground SG 1  for DUT 1  and DUT signal ground SG 2  for DUT 2  are coupled with the power supply ground  2 . Since SG 1  and SG 2  are not connected, when one of the devices DUT 1  or DUT 2  is affected by the surrounding noises, noises will be attenuated by the power supply ground  2  and then feed back to the DUT 1  or DUT 2 , lowering down the noise interferences and improving the test accuracy for the semiconductor devices.  
         [0019]    In summary, it is advantageous to use the invention since 1) devices under test are mounted on different and independent test sites during testing on the testing board, and 2) testing accuracy is improved since aforementioned test sites respectively have at least one ground, which is independent with its counterpart on other divided testing sites. Note that this invention is not limited to testing board described in FIG. 3. Other testing board such as burn-inboard is also suitable for the claimed invention.  
         [0020]    Those skilled in the art will readily observe that numerous modification and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.