Abstract:
A row line selection circuit comprises first and second decoding sections and NMOS transistors. The first decoding section receives a first address signal and generates first selection signals. The second decoding section receives a second address signal and generates second selection signals. The NMOS transistors each of which has a gate for receiving one of the first selection signals, one end of a current path of each of the NMOS transistors being connected to receive the one of the second selection signals. The NMOS transistors classified into groups, each group including a predetermined number of the transistors which are prepared in correspondence with row lines lying adjacent to each other. One of the first selection signals is supplied to the predetermined number of NMOS transistors in one of the groups, and one of the second selection signals is supplied to one of the predetermined number of NMOS transistors in each group.

Description:
This is a continuation of application Ser. No. 09/699,632, filed Oct. 31, 2000, which is a divisional of application Ser. No. 09/550,791, filed Apr. 17, 2000, now U.S. Pat. No. 6,178,116, which is a divisional of application Ser. No. 09/305,479, filed May 6, 1999, now U.S. Pat. No. 6,072,748, which is a continuation of application Ser. No. 08/901,660, filed Jul. 28, 1997, now U.S. Pat. No. 6,058,051, which is a division of application Ser. No. 08/731,914, filed Oct. 22, 1996, now U.S. Pat. No. 5,745,413, which is a division of application Ser. No. 08/433,071, filed May 3, 1995, now U.S. Pat. No. 5,596,525, which is a division of application Ser. No. 08/288,219, filed Aug. 9, 1994, now U.S. Pat. No. 5,448,517, which is a continuation of application Ser. No. 08/115,100, filed Sept. 2, 1993, now abandoned, which is a continuation of application Ser. No. 07/913,451, filed Jul. 15, 1992, now U.S. Pat. No. 5,270,969, which is a continuation of application Ser. No. 07/685,650, filed Apr. 16, 1991, now U.S. Pat. No. 5,148,394, which is a continuation of application Ser. No. 07/212,649, filed Jun. 28, 1988, now U.S. Pat. No. 5,008,856, all of which are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a nonvolatile semiconductor memory device having floating gate type MOSFETs as memory cells. 
     2. Description of the Related Art 
     Conventionally, EEPROM and UVEPROM are known as the nonvolatile semiconductor memory device with a floating gate structure, for example. In the EEPROM, data is electrically written in or programmed and electrically erased. With a memory cell in the EEPROM, data can be programmed by injecting or emitting electrons into or from the floating gate via an oxide film with a thickness of approx. 100 Å which is extremely thinner than a gate oxide film by use of the tunnel effect. The EEPROM is explained in detail in U.S. Pat. No. 4,203,158 (Frohman-Bentchkowsky et al. “ELECTRICALLY PROGRAMMABLE AND ERASABLE MOS FLOATING GATE MEMORY DEVICE EMPLOYING TUNNELING AND METHOD OF FABRICATING SAME”). 
     However, since, in the above EEPROM, two transistors are,used to constitute a single memory cell, the memory cell size becomes large and the chip cost will increase. 
     For the above reason, ultraviolet erasable non-volatile semiconductor memory devices or UVEPROM has an advantage in attaining high integration density, in which each memory cell is formed of a single transistor. 
     In the UVEPROM, data can be electrically programmed and erased by applying ultraviolet rays thereto. As described above, in the UVEPROM, each memory cell is formed of a single transistor so that the chip size can be reduced for the same memory scale or capacity as that of the EEPROM. 
     However, in the UVEPROM, a high power source voltage is required to program data. That is, in order to inject electrons into the floating gate of a selected memory cell, a high voltage is applied between the control gate and drain to cause impact ionization in an area near the drain region, injecting the electrons thus generated into the floating gate. For this purpose, it becomes necessary to provide a power source of high voltage for data programming outside the memory device. In contrast, since electrons are injected into or emitted from the floating gate by the tunnel effect in the EEPROH, it is not necessary to use such a programming power source as is used in the UVEPROM and data can be programmed by an output voltage of a booster circuit provided in the same chip as that of the memory device. Therefore, the EEPROM can be operated on a single power source voltage of 5 V. 
     As described above, the UVEPROM can be formed at a higher integration density in comparison with the EEPROM. However, in general, since a single contact portion is formed for each common drain of two memory cell transistors, the number of contact portions increases. Increase in the number of contact portions is an obstruction to the attainment of high integration and large memory capacity. For this reason, the UVEPROM can be formed at a higher integration density than the EEPROM, but can be further improved in its integration density. 
     SUMMARY OF THE INVENTION 
     One aspect of the present invention provides a row line selection circuit. The row line selection circuit comprises a first decoding section which receives a first address signal and generates a plurality of first selection signals in response to the first address signal; a second decoding section which receives a second address signal and generates a plurality of second selection signals in response to the second address signal; and a plurality of N-channel type MOS transistors each of which has a gate, one end of a current path of each of the plurality of N-channel type MOS transistors being connected in such a manner as to receive one of the plurality of second selection signals, and each of the plurality of N-channel type MOS transistors transferring one of the plurality of second selection signals to a row line for selecting the row line in response to one of the plurality of first selection signals, wherein the plurality of N-channel type transistors are classified into groups, each group including a predetermined number of the N-channel type transistors which are prepared in correspondence with row lines lying adjacent to each other; one of the plurality of first selection signals is supplied to the gate of the predetermined number of N-channel type MOS transistors in one of the groups; one of the plurality of second selection signals is supplied to a corresponding one of the predetermined number of N-channel type MOS transistors in each group; and the row line is selected in response to one of the plurality of first selection signals generated in the first decoding section and one of the plurality of second selection signals generated in the second decoding section. 
     Another aspect of the present invention provides a row line selection circuit. The row line selection circuit comprises a first decoding section which receives a first address signal and generates a plurality of first selection signals in response to the first address signal; a second decoding section which receives a second address signal and generates a plurality of second selection signals in response to the second address signal; and a plurality of switching means for transferring one of the plurality second selection signals to a row line in response to one of the plurality of first selection signals in order to select the row line, wherein the plurality of switching means are classified into groups, each group including a predetermined number of the switching means which are prepared in correspondence with row lines lying adjacent to each other; one of the plurality of first selection signals is supplied to the predetermined number of switching means in one of the groups; one of the plurality of second selection signals is supplied to a corresponding one of the predetermined number of switching means in each group; and the plurality of second selection signals do not affect the row lines when the plurality of switching means are turned off; and the row line is selected in response to one of the plurality of first selection signals generated in the first decoding section and one of the plurality of second selection signals generated in the second decoding section. 
     Still another aspect of the present invention provides a row line selection circuit. The row line selection circuit comprises a first decoding section which receives a first address signal and generates a plurality of first selection signals in response to the first address signal; a second decoding section which receives a second address signal and generates a plurality of second selection signals in response to the second address signal; and a plurality of transfer circuits for selecting a row line, each of the plurality of circuits transfer one of the plurality of second selection signals to the row line and a low level component of one of the plurality of second selection signals while maintaining a voltage level of the low level component in response to one of the plurality of first selection signals, the plurality of transfer circuits are classified into groups, each group including a predetermined number of the transfer circuits which are prepared in correspondence with row lines lying adjacent to each other; one of the plurality of first selection signals is supplied to the predetermined number of transfer circuits in one of the groups; one of the plurality of second selection signals is supplied to a corresponding one of the predetermined number of transfer circuits in each group; and the row line is selected in response to one of the plurality of first selection signals generated in the first decoding section and one of the plurality of second selection signals generated in the second decoding section. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a nonvolatile semiconductor memory device according to a first embodiment of this invention; 
     FIGS. 2 and 3 are timing charts for illustrating the operation of the circuit shown in FIG. 1; 
     FIG. 4A is a pattern plan view showing the construction of a cell transistor in the circuit of FIG. 1; 
     FIG. 4B is a cross sectional view taken along line  4 B— 4 B of the pattern plan view of FIG. 4A; 
     FIG. 4C is a cross sectional view taken along line  4 C— 4 C of the pattern plan view of FIG. 4A; 
     FIG. 5A is a pattern plan view showing another construction of a cell transistor in the circuit of FIG. 1; 
     FIG. 5B is a cross sectional view taken along line  5 B— 5 B of the pattern plan view of FIG. 5A; 
     FIG. 6A is a pattern plan view showing still another construction of a cell transistor in the circuit of FIG. 1; 
     FIG. 6B is a cross sectional view taken along line  6 B— 6 B of the pattern plan view of FIG. 6A; 
     FIG. 7 is a circuit diagram showing another construction of a data programming circuit constituted by two MOSFETs and a data input circuit in the circuit of FIG. 1; 
     FIG. 8 is a circuit diagram showing still another construction of a data programming circuit constituted by two MOSFETs and a data input circuit in the circuit of FIG.  1 . 
     FIG. 9 is a circuit diagram showing still another construction of a data programming circuit constituted by two MOSFETs and a data input circuit in the circuit of FIG.  1 . 
     FIG. 10 is a circuit diagram showing the construction of a memory device formed by arranging cell transistors shown in FIG. 1 in a matrix form; 
     FIGS. 11 and 12 are timing charts for illustrating operation of the circuit of FIG. 10; 
     FIGS. 13 and 14 are diagrams showing the levels of various signals in the circuit of FIG. 10; 
     FIG. 15 is a circuit diagram showing the construction of a circuit for applying a power source voltage of two different voltage levels to the row decoder in the circuit of FIG. 10; 
     FIG. 16 is a circuit diagram showing a modified construction of a memory cell section in the circuit of FIG. 1; 
     FIG. 17 is a circuit diagram showing a modified construction of a peripheral portion of the memory cell section in the circuit of FIG. 10; 
     FIG. 18A is a circuit diagram for illustration of another construction of the circuit of FIG. 10; 
     FIG. 18B is a circuit diagram showing a construction of a booster circuit in the circuit of FIG. 18A; 
     FIG. 19 is a circuit diagram for illustration of the principle of a nonvolatile semiconductor memory device according to a second embodiment of this invention; 
     FIG. 20 is a pattern plan view of the circuit of FIG. 19; 
     FIG. 21A is another pattern plan view of the circuit of FIG. 19; 
     FIG. 21B is a cross sectional view taken along line  21 B— 21 B of the pattern plan view of FIG. 20A; 
     FIG. 22 is a pattern plan view indicating that the pattern structure of FIGS. 21A and 21B can be advantageously used in the manufacturing process; 
     FIGS. 23 to  25  and  26 A are still other pattern plan views of the circuit of FIG. 19; 
     FIG. 26B is a pattern plan view illustrating an ion-implantation mask used for forming the pattern of FIG. 26A; 
     FIG. 27 is a diagram showing the circuit model formed to illustrate the operation of the circuit of FIG. 17; 
     FIG. 28 is a diagram showing a voltage-current characteristic of a floating gate type MOSFET; 
     FIG. 29 and 30 are timing charts for illustrating the operation of the circuit of FIG. 17; 
     FIG. 31 is a circuit diagram showing the construction of a nonvolatile semiconductor memory device formed of memory cells of the same construction as the memory cell shown in FIG.  19  and formed to have a plural-bit output construction; 
     FIGS. 32 to  34  are timing charts for illustrating the operation of the memory device of FIG. 31; 
     FIGS. 35 and 36 are circuit diagrams showing the detail construction of a row decoder in the memory device of FIG. 31; 
     FIG. 37 is a circuit diagram showing a modification of the circuit of FIG. 36; 
     FIGS. 38 and 49 are the truth tables obtained in the row decoder of the memory device of FIG. 31; and 
     FIG. 40 is a circuit diagram showing a modification of the circuit of FIG.  19 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a memory cell section and a peripheral circuit section (programming circuit and readout circuit) thereof in an EEPROM according to a first embodiment of this invention. The FIG. 1 circuit is schematically shown for briefly explaining the first embodiment of this invention. Data programming circuit  10  is constituted by input circuit  11  and N-channel MOSFETs  12  and  13 . output signal D 1  from data input circuit  11  is supplied to the gate of MOSFET  12  which is connected at one end to high voltage power source Vpp. Output signal D 2  of data input circuit  11  is supplied to the gate of HOSFET  13  connected between node N 1  on the other end of MOSFET  12  and a ground terminal (reference potential terminal). MOSFET  12  is used to charge node N 1  in the programming mode and MOSFET  13  is used to discharge node N 1 . The current paths of selection transistor ST and cell transistors CT 1  to CT 4  are serially connected between node N 1  and the ground terminal. The gate of selection transistor ST is applied a signal X 1  for selecting a group of cell transistors CT 1  to CT 4 . Further, the gates of cell transistors CT 1  to CT 4  are respectively applied signals W 1  to W 4  for respectively selecting cell transistors CT 1  to CT 4 . Node N 1  is further connected to one end of N-channel MOSFET  14  whose conduction state is controlled by signal RE set at “1” level in the readout mode and at “0” level in the programming mode. The other end of MOSFET  14  is connected to an input terminal of data detection circuit  15 . P-channel MOSFET  16  is connected between power source terminal vcc and node N 2  which is present on the input side of data detection circuit  15  and the gate thereof is connected to node N 2 . MOSFET  16  functions as a load in the readout mode. 
     For brief explanation, a combination of selection transistor ST and cell transistors CT 1  to CT 4  is referred to as a single memory cell in the first embodiment. However, it should be understood that the memory cell is different from an ordinary memory cell and can store data of four bits (the number of bits corresponds to that of cell transistors having current paths connected in series). That is, the memory cell in this example is equivalent to four conventional memory cells. 
     There will now be described an operation of the memory device with the above construction with reference to FIGS. 2 and 3. FIG. 2 is a timing chart of various signals in the programming mode in the circuit of FIG.  1 . First, signal RE is set to “0” level to turn off transistor  14 . At time to, signals X 1  and W 1  to W 4  are set to a high voltage level to inject electrons into the floating gates of cell transistors CT 1  to CT 4 . Then, at successive times t 1  to t 4 , signals W 4  to W 1  are sequentially set to 0 V in this order. If output signals D 1  and D 2  of data input circuit  11  are respectively set at “1” and “0” levels when signals W 1  to W 4  are set to 0 V, transistors  12  and  13  are respectively turned on and off, causing a high voltage from high voltage power source Vpp to be applied to the drain of a corresponding transistor via transistor  12  and selection transistor ST so that electrons can be emitted from the floating gate of the respective cell transistors. In FIG. 2, since signal D 1  is set at “1” when signals W 3  and W 1  are set to 0 V electrons are emitted from the floating gates of cell transistors CT 3  and CT 1 . Thus, data can be programmed. In a case where output signals D 1  and D 2  of data input circuit  11  are set at “0” and “1” levels, respectively, node N 1  is discharged. 
     In the data readout mode, output signals D 1  and D 2  of data input circuit  11  are set to “0” level to turn off transistors  12  and  13 . Further, signals RE and X 1  are set to “1” level and the control gate voltage of a cell transistor to be selected for data readout is set to 0 V. At this time, the control gate voltages of other cell transistors are set to “1” level. FIG. 3 is a timing chart showing the case where data is sequentially read out from cell transistors CT 4  to CT 1 . More specifically, data is read out from cell transistor CT 4  in a period of time t 0  to t 1 , from cell transistor CT 3  in a period of time t 1  to t 2 , from cell transistor CT 2  in a period of time t 2  to t 3 , and from cell transistor CT 1  in a period of time t 3  to t 4 . Assume now that signal W 1  is set at 0 V and signals W 2  to W 4  are set at “1” level. Then, data is read out from cell transistor CT 1 . If data has been programmed as described before, the threshold voltage thereof is set negative since electrons have been emitted from the floating gate of cell transistor CT 1 , and therefore cell transistor CT 1  is turned on by signal W 1  of 0 V. The control gate voltages of other cell transistors CT 2  to CT 4  are set at “1” level and the cell transistors are turned on. Thus, all the cell transistors are set in the conductive state, lowering the potential of node N 2 . The potential fall is detected by means of data detection circuit  15  and thus data can be read out from cell transistor CT 1 . Assume now that signal W 2  is set to 0 V to select cell transistor CT 2  and electrons are kept held in the floating gate of cell transistor CT 2 . Since, in this case, the control gate voltage is set at 0 V, cell transistor CT 2  is turned off. Therefore, node N 2  is charged via transistor  16 , and the potential rise of node N 2  is detected by means of data detection circuit  15 . It should be noted here that the threshold voltages of cell transistors CT 1  to CT 4  having electrons kept held in the floating gates are so determined that the cell transistors can be turned on when the control gate voltages thereof are set to “1” level. 
     FIGS. 4A to  4 C show an example of a transistor which is suitable for cell transistors CT 1  to CT 4  and in which part of the insulation film on the channel region is formed of a thin oxide film with the thickness of approx. 100 Å. FIG. 4A is a pattern plan view, FIG. 4B is a cross sectional view taken along line  4 B— 4 B of FIG. 4A, and FIG. 4C is a cross sectional view taken along line  4 C— 4 C of FIG. 4A. N + -type source and drain regions ( 18  and  19 ) are formed with a predetermined distance therebetween in the main surface area of P-type silicon substrate  17 . First oxide film  20  having thin portion  20 A is formed on that part of semiconductor substrate  17  which lies on the channel region between source and drain regions ( 18  and  19 ). Floating gate  21  is formed on oxide film  20 , and control gate  23  is formed on second oxide film  22  formed on floating gate  21 . 
     FIGS. 5A and 5B show another example of a transistor suitable for cell transistors CT 1  to CT 4  in the circuit of FIG.  1 . In this case, an insulation layer disposed on the entire portion of the channel region is formed of an oxide film with a thickness of approx. 100 A. Portions in FIGS. 5A and 5B which are similar to those in FIGS. 4A to  4 C are denoted by the same reference numerals. FIG. 5A is a pattern plan view and FIG. 5B is a cross sectional view taken along line of  5 B— 5 B of FIG.  5 A. 
     FIGS. 6A and 6B show still another example of a transistor suitable for cell transistors CT 1  to CT 4  in the circuit of FIG.  1 . In the cell transistor shown in FIGS. 6A and 6B, N − -type impurity region  24  with low impurity concentration is formed in part of the channel region. That is, the cell transistor is a depletion type transistor. FIG. 6A is a pattern plan view and FIG. 6B is a cross sectional view taken along line of  6 B— 6 B of FIG.  6 A. With this construction, even if electrons are injected into the floating gate to such an extent that the cell transistor may be kept off when a “1” level signal is supplied to the control gate, current will flow since source and drain regions  18  and  19  are connected to each other via N − -type impurity region  24 . The operation of reading out data from the cell transistor with above construction is effected by detecting the amount of current varying according to whether or not electrons are injected into the floating gate when a “0” level voltage is applied to the control gate. 
     FIG. 7 shows another construction of data programming circuit  10  constituted by MOSFETs  12  and  13  and data input circuit  11  in the circuit of FIG.  1 . Programming data Din is supplied to CMOS inverter  27  formed of P-channel MOSFET  25  and N-channel MOSFET  26 . The output terminal of CMOS inverter  27  is connected to one end of N-channel HOSFET  28  whose gate is connected to power source Vcc. P-channel MOSFET  29  is connected between the other end of MOSFET  28  and power source Vpp of high voltage, for example, 12.5 V. Further, the other end of MOSFET  2 B is connected to the gates of P-channel MOSFET  30  and N-channel MOSFET  31 . One end of MOSFET  30  is connected to power source Vpp, and the other end thereof is connected to one end of MOSFET  31 . N-channel MOSFET  32  is connected between the other end of MOSFET  31  and the ground terminal. The gate of MOSFET  32  is connected to the other end of MOSFET  31 . A connection node between MOSFETs  30  and  31  is connected to the gate of MOSFET  29  and one end of N-channel MOSFET  33 . The gate of HOSFET  33  is supplied with signal PR which is set at an “1” level in the program mode and an “0” level in the readout mode. In this case, “1” level indicates a high voltage level approximately equal to Vpp level. If signal PR is set higher than Vpp by the threshold voltage of MOSFET  33 , voltage of Vpp is transmitted as it is to mode N 1 . The other end of MOSFET  33  is connected to node N 1  or one end of selection transistor ST and one end of transistor  14  in the circuit of FIG.  1 . 
     With the above construction, signal PR is set at “1” level in the data programming mode to turn on MOSFET  33 . In this case, high voltage Vpp is generated from data programming circuit  10  when input data Din is at “1” level, and a signal of a level equal to threshold voltage V TH  of MOSFET  32  is generated as programming data when input data Din is at “0” level. In this example, a signal of V TH  level is generated when input data Din is at “0” level. The reason why a V TH  level signal is output when input data Din is at “0” level is as follows: 
     As will be described later, a plurality of memory cells as shown in FIG. 1 are arranged in a matrix form in order to from an integrated circuit. Therefore, adjacent transistors ST are controlled by the same signal X 1 , and the gates of transistors ST are formed of the same polysilicon layer, for example. Signal X 1  is set at a high voltage level in the programming mode, and at this time, potentials of the drains of transistors ST are set at different levels according to the programming data. For example, in a case where electrons are emitted from the floating gate of a cell transistor connected to a first one of transistors ST and electrons are injected into the floating gate of a cell transistor connected to the other or second transistor ST, the drain of the first transistor ST is set at a high potential and the drain of the second transistor ST is set at a low potential. In this case, a parasitic MOS transistor is formed between the first and second transistors ST connected to the same polysilicon layer. If the parasitic MOS transistor has a threshold voltage lower than the potential level of signal X 1 , unwanted current will flow from the first transistor ST whose drain is set at a high potential to the second transistor ST through the parasitic MOS transistor. The drain potential of the first transistor ST is lowered by the unwanted current flow, deteriorating the programming characteristics. In order to prevent the deterioration of the programming characteristics, the amount of impurity implanted into the field area for channel-cut may be increased to get a high threshold voltage of the parasitic MOS transistor. However, if the impurity concentration of the field area is increased, the breakdown voltage in the drain region to which a high voltage is applied will be lowered. As shown in FIG. 7, if the drain of transistor ST which is set at a low potential to inject electrons into the floating gate is is connected to the ground terminal through MOSFET  32 , the above-described problem will not occur. When current flows through the parasitic MOS transistor, the drain of the second transistor ST is charged and the drain voltage is increased, thus increasing the source potential of the parasitic MOS transistor. The source potential increase of the parasitic MOS transistor being on the increase of the threshold voltage without increasing the amount of impurity implanted into the field area for channel-cut. Therefore, no current will flow from the first transistor ST to the second transistor ST through the parasitic MOS transistor and the drain voltage of the first transistor ST can be enhanced to a sufficiently high voltage level, effectively preventing the deterioration of the programming characteristics. In the data readout mode, since signal PR is set at “0” level to turn off MOSFET  33 , data programming circuit  10  has no influence on the potential at node N 1 . 
     FIG. 8 shows still another construction of data programming circuit  10  in the circuit of FIG.  1 . In the circuit, depletion type MOSFET  34  is used as a load instead of P-channel MOSFET  30  in FIG.  7 . Further, in the circuit, a plurality of diode connected MOSFETs  32 - 1  to  32 -n are provided. The number of MOSFETs  32 - 1  to  32 -n is determined by a designed output level. With this construction, substantially the same operation as that of the FIG. 7 can be attained. 
     As described above, in order to prevent current from flowing through the parasitic MOS transistor, it is preferable to set higher the potential of an area acting as the source of the parasitic MOS transistor into which the current flows. When the source potential is set higher, we get a higher threshold voltage of the parasitic MOS transistor. For this reason, as shown in FIG. 8, a plurality of MOSFETs  32 - 1  to  32 -n are used. However, in this case, if the source potential is set to be extremely high, electrons may happen to be emitted from the drain to the floating gate of the cell transistor. Therefore, it is necessary to set the source potential in such a potential level that electrons will not emitted from the drain of the cell transistor and current will not flow out from the parasitic MOS transistor. 
     FIG. 9 shows still another construction of data programming circuit  10  in the circuit of FIG.  1 . Inverted signal {overscore (Din)} of data Din is supplied to the gates of P-channel MOSFET  35  and N-channel MOSFET  36 . P-channel HOSFET  37  is connected between one end of MOSFET  35  and power source Vcc. The gate of MOSFET  37  is supplied with signal {overscore (PR)} which is set at “L” level in the program mode. The other end of MOSFET  35  is connected to one end of MOSFET  36  which is connected at the other end to the ground terminal. N-channel MOSFET  38  having a gate supplied with signal {overscore (PR)} is connected between the ground terminal and a connection node between MOSFETs  35  and  36 . Further, one end of N-channel MOSFET  39  whose gate is connected to power source Vcc is connected to a connection node between MOSFETs  35  and  36 . P-channel MOSFET  40  is connected between the other end of MOSFET  39  and power source Vpp. The other end of MOSFET  39  is connected to the gates of P-channel MOSFET  41  and N-channel MOSFET  42 . One end of MOSFET  41  is connected to power source Vpp and the other end thereof is connected to one end of MOSFET  42  which is connected at the other end to the ground terminal. The gates of MOSFET  40  and P-channel MOSFET  43  are connected to a connection node between MOSFETs  41  and  42 . One end of MOSFET  43  is connected to power source Vpp and the other end thereof is connected to one end of N-channel MOSFET  44 . Diode connected N-channel MOSFET  45  is connected between the other end of MOSFET  44  and the ground terminal. 
     Data {overscore (Din)} is supplied to an input terminal of CMOS inverter  48  including P-channel MOSFET  46  and N-channel MOSFET  47 . An output signal of CMOS inverter  48  is supplied to the gates of P-channel MOSFET  49  and N-channel MOSFET  50 . P-channel MOSFET  51  is connected between one end of MOSFET  49  and power source vcc, and the gate of MOSFET  51  is supplied with signal {overscore (PR)}. The other end of MOSFET  49  is connected to one end of MOSFET  50  which is connected at the other end to the ground terminal. N-channel MOSFET  52  having a gate supplied with signal {overscore (PR)} which is set at “L” level in the programming mode is connected between the ground terminal and a connection node between MOSFETs  49  and  50 . The gate of MOSFET  44  is connected to a connection node between MOSFETS  49  and  50 , and the connection node between MOSFETs  43  and  44  is connected to node N 1 . 
     With this construction, the same operation as that of the circuit shown in FIGS. 7 and 8 can be attained. That is, since signal {overscore (PR)} is set at “H” level at a time other than the programming mode, for example, in the readout mode, MOSFETs  38  and  52  are turned on and MOSFETs  37  and  51  are turned off. Therefore, MOSFETs  43  and  44  are turned off, electrically isolating data programming circuit  10  from node N 1 . In contrast, signal PR is set at “0” level in the data programming mode so that MOSFETs  37  and  51  will be turned on and MOSFETs  38  and  52  will be turned off. Therefore, high voltage Vpp is generated from data programming circuit when input data Din is at “0” level, and a signal at a level equal to the threshold voltage V TH  Of MOSFET  45  when input data Din is at “1” level. 
     FIG. 10 shows a nonvolatile semiconductor memory device formed by arranging memory cells with the above construction in a matrix form. In FIG. 10, data programming and reading circuits  200  surrounded by one-dot-dash lines in the circuit of FIG. 1 are connected to data input/output lines IO 1  to IO 8 . In FIG. 10, a plurality of data programming and reading circuits  200  are formed by a single block. Row decoder  53  generates signals X 1 , X 2 , . . . , signals W 11 , W 12 , . . . , Wln, and signals W 21 , W 22 , . . . , W 2 n to select a row line or lines in the memory cell array. Column decoder  54  generates signals Yl to Ym to selectively activate column selection MOSFETs Ql to Qm so that data to be programmed can be supplied to one of memory cell blocks Bl to Bm through data input/output lines IO 1  to IO 8  or data can be read out from one of the memory cell blocks through the input/output lines. Further, column decoder  55  generates signals Z 2  to Zm to selectively activate depletion type MOSFETs QD 2  to QDm for array division so as to sequentially specify memory cell blocks Bl to Bm in the program mode. 
     With the above construction, the data programming operation is effected starting from the memory cell which is positioned far away from row decoder  53 . Now, the data programming operation in the memory device of FIG. 10 is explained. FIG. 11 is a timing chart of various signals in the program mode. That is, the data programming operation is effected with respect to the memory cells connected to data line Xl of memory cell block Bm. At the time of programming, signals Xl, Ym, Z 2  to Zm are set at a high voltage level. In this condition, signals wll to Wln are set to a high voltage level to inject electrons into the floating gates of the cell transistors. Then, signals Wln to Wll are sequentially set to “0” level in this order. In this case, electrons are emitted only when the control gate voltage is at “0” level and programming data is supplied as a high voltage to the drain through any one of data input/output lines IO 1  to IO 8 , column selection transistor Qm and selection transistor STm, and thus data can be programmed in the respective cell transisters. 
     FIG. 12 is a timing chart for the readout mode, and signals X and Y associated with a selected memory cell are set at “1” level. Further, one of signals Wll to Win associated with cell transistors of the selected memory cell is set to “0” level, and all the gate voltages of nonselected cell transistors are set at “1” level. As a result, data can be read out in the same manner as in the case of the circuit of FIG.  1 . 
     FIG. 13 shows the truth table indicating the levels of signals Wll to Wln. For simplifying the explanation, assume that n is set to 4, and the cell transistor is selected by row address signals A 0  and A 1 . In this case, signal RE is used to identify the programming mode and readout mode. That is, signal RE indicates the programming mode when set at “0”, and the readout mode when set at “1”. 
     Signal I is a signal used for initialization. If signal I is set at “1” when signal RE is set at “0” indicating the programming mode, W 11  to W 14  are set at “1” level or a high voltage level irrespective of signals A 0  and A 1 , causing electrons to be injected into the floating gates of the cell transistors connected to W 11  to W 14 . When signals I and RE are at “0” level, the potential levels of W 11  to W 14  are determined according to address signals A 0  and A 1  as shown in the truth table. 
     When signal RE is at “1” level indicating the readout mode, the potential levels of W 11  to W 14  are determined according to address signals A 0  and A 1  irrespective of signal I. That is, in the readout mode, only one of Wll to W 14  selected by a combination of address signals A 0  and A 1  is set to “0” level. 
     “1” level at which W 11  to W 14  are set in the programming mode is set at a high voltage of, for example, approx. 20 V, and “1” level at which W 11  to W 14  are set in the readout mode is set to a low voltage of, for example, 5 V. 
     FIG. 14 shows the truth table of signals X 1 , X 2 , W 11  to W 14 , and W 21  to W 24  in the readout mode in combination with three addresses A 0  to A 2 . In this example, if Xl=“0”, signals wll to W 14  are set at “0” level in the readout mode, but it is also possible to set one of signals W 11  to W 14  to “0” in the same manner as in the case of Xl=“1”. 
     FIG. 15 shows a circuit for selectively producing power source voltage vcc which set a potential used in the reading mode and high level voltage Vpp of 20 V, for example, which is used for programming mode to row decoder  53  in the circuit of FIG.  10 . In the circuit of FIG. 15, capacitor  59  is connected between the ground terminal and an output terminal of COOS inverter  58  including P-channel MOSFET  56  and N-channel MOSFET  57 . The output terminal of CMOS inverter  58  is connected to an input terminal of CMOS inverter  62  including P-channel MOSFET  60  and N-channel MOSFET  61 . Capacitor  63  is connected between the ground terminal and the output terminal of CMOS inverter  62 . The output terminal of CMOS inverter  62  is connected to an input terminal of CMOS inverter  66  including P-channel MOSFET  64  and N-channel MOSFET  65 . The output terminal of CMOS inverter  66  is connected to the input terminal of CMOS inverter  58  and one electrode of capacitor  67 . N-channel MOSFET  66  having a gate connected to power source vcc is connected between the other electrode of capacitor  67  and the power source vcc. Further, the other electrode of capacitor  67  is connected to one end and the gate of N-channel MOSFET  69 . The current paths of depletion type (D-type) MOSFET  70  and N-channel MOSFET  71  are serially connected between the other end of MOSFET  69  and power source vcc. The gate of MOSFET  70  is connected to receive signal {overscore (PR)} and the gate of MOSFET  71  is connected to the other end of MOSFET  69 . D-type MOSFET  72  having a gate connected to receive signal PR is connected between the other end of MOSFET  69  and high level voltage source Vpp. Node N 3  used as an output terminal of the circuit of FIG. 15 is connected to a power source terminal of row decoder  53  in the circuit of FIG.  10 . 
     With the construction described above, when signal PR is set at “0” level and signal {overscore (PR)} is set at “1” level, or when data is read out from a cell transistor, MOSFETs  70  and  72  are turned on and off, respectively, CMOS inverters  58 ,  62  and  66  are connected to constitute a ring oscillator whose oscillation output is supplied to one electrode of capacitor  67 . Power source voltage vcc is stepped up by means of MOSFETs  68 ,  69  and  71 , and is transmitted to node N 3 . The other end of MOSFET  69  is set at a potential higher than power source voltage vcc by the threshold voltage of MOSFET  71 . In contrast, when signal PR is set at “1” level and signal {overscore (PR)} is set at “0” level, that is, when data is programmed in a cell transistor, MOSFETs  72  and  70  are turned on and off, respectively. Therefore, in this case, power source voltage Vpp is supplied to node N 3  through MOSFET  72 . 
     Thus, in the circuit of FIG. 15, a first readout voltage higher than power source voltage Vcc is supplied when data is read out from a cell transistor, and power source Vpp higher than the first readout voltage is supplied in the programming mode. In this way, row decoder  53  is operated on power source voltages of different voltage levels in the data programming mode and readout mode. 
     It is of source possible to supply power source voltage vcc itself as the power source voltage for row decoder  53  in the data readout mode. In the readout mode, the gate of the selected cell transistor is set to “0” and the gate of the nonselected cell transistor is set to “1”. Data is determined depending on whether or not current flows in the selected cell transistor whose gate is set at “0”. As the current flowing in the selected cell transistor becomes larger, data input/output line IO may be charged or discharged at a higher speed, thus enhancing the data readout speed. 
     Since the memory cell is constituted by connecting cell transistors in series, the same amount of current as that which flows in the selected cell transistor flows in the nonselected cell transistor. Therefore, current flowing in the memory cell is determined by a series circuit of the resistive component of the selected cell transistor and the resistive component of the nonselected cell transistor. For this reason, the current flowing in the memory cell becomes larger as the resistive component of the nonselected cell transistor is reduced. Therefore, in the circuit of FIG. 15, a voltage which is higher than power source voltage vcc by the threshold voltage of MOSFET  71  is used as the power source voltage for row decoder  53  so as to set the gate voltage of the nonselected cell transistor higher, thus reducing the resistance of the nonselected cell transistor. In a case where row decoder  53  is constituted by CMOS circuits, current which may constantly flow in the circuit can be suppressed to 0. Therefore, the circuit of FIG. 15 can be satisfactorily used as a power source. Further, power source voltage Vpp can be supplied from the exterior. However, if the peripheral circuit is formed of CHOS circuits, constantly flowing current can be prevented, and therefore Vpp can be internally obtained by stepping up power source voltage vcc by use of a charge pump circuit in the well known manner. 
     FIG. 16 shows another construction of the memory cell section in FIG.  1 . In the circuit of FIG. 16, N-channel MOSFET  80  whose conduction state is controlled by signal {overscore (PR)} set at “0” or “1” level respectively in the programming mode or readout mode is connected between cell transistor CT 4  of FIG.  1  and the ground terminal. Portions in FIG. 16 which are similar to those in FIG. 1 are denoted by the same reference numerals and the detail explanation thereof is omitted. 
     With this construction, even if a leakage current flows from cell transistors CT 1  to CT 4  when a high voltage is applied to the drain thereof in the program mode, the leakage current can be cut off by means of transistor  80 . Thus, the drain potential can be prevented from being lowered and the programming characteristic can be prevented from being deteriorated. In the circuit of FIG. 10, transistor  80  can be used commonly for a plurality of cell blocks. 
     FIG. 17 shows a circuit which can be used to form the FIG. 1 circuit in a matrix form. The circuit of FIG. 17 corresponds to one of memory cell blocks Bl to Bm, and includes MOSFETs QT 1 , QT 2 , . . . which are connected to the control gates of the cell transistors and whose conduction states are controlled by signals X 1 , X 2 , . . . . Since signals are input through MOSFETs QT 1 , QT 2 , . . . a desired one of the memory cell blocks can be programmed by selectively satisfying a logical condition determined by a combination of signals wll, W 12 , . . . and signals Z 2  to Zm supplied to corresponding memory cell blocks to selectively set signals Wlnl, . . . , W 121 , W 111  to a high voltage level. In this case, two-layered aluminum wiring layer is used and signals W 111 , W 121 , . . . , Wlnl are transmitted via the second wiring aluminum layer. Therefore, the chip size will be increased because the wiring layer for signals W 111 , W 121 , . . . , Wlnl is additionally provided, but increase in the chip size can be suppressed to a minimum. 
     Further, it is possible to connect a latch circuit shown in FIG. 18 to each column line (the drain of selection transistor ST). In this case, one end of MOSFET  81  and input and output terminals of booster circuit  82  are connected to each column line. The gate of MOSFET  81  is connected to receive signal LA/PR which is set at “1” level in the latching operation and programming mode, and set at “0” level in the read mode. The other end of MOSFET  81  is connected to an output terminal of CMOS inverter  85  constituted by P-channel MOSFET  83  and N-channel MOSFET  84  and an input terminal of CMOS inverter  88  constituted by P-channel MOSFET  86  and N-channel MOSFET  87 . The input terminal of CMOS inverter  85  is connected to the output terminal of CMOS inverter  88 . 
     Thus, CMOS inverters  85  and  88  are connected to constitute latch circuit  89 . Data to be programmed can be latched in latch circuit  89 , and the column lines can be selectively set at high voltage or 0 V according to the latched data for one row of memory cells so that the all memory cells connected to one line of row lines can be programmed. Therefore, MOSFETs QD 2  to QDm for array division shown in FIG. 10 can be omitted. 
     FIG. 18B shows the construction of booster circuit  82  in the circuit of FIG.  18 A. Clock generating circuit  90  generates clock signal φC. The output terminal of clock generating circuit  90  is connected to one electrode of MOS capacitor  92  which is connected at the other electrode to one end of MOSFET  93  having a threshold of approx. 0 V and one end and the gate of MOSFET  94 . The other end of HOSFET  93  is connected to receive an output voltage Vpp′ of another booster circuit (not shown) and the gate thereof is connected to the column line. The other output terminal of MOSFET  94  is connected to the column line. 
     In booster circuit  82 , when the latch data is “1”, the potential of the column line is stepped up and supplied to the cell transistor. 
     According to the first embodiment described above, a nonvolatile semiconductor memory device is provided in which data can be electrically programmed, the memory cell size can be made smaller than a UVEPROM, and the low cost can be attained. 
     FIG. 19 is a circuit diagram for illustrating the principle of a nonvolatile semiconductor memory device according to a second embodiment of this invention. That is, the nonvolatile semiconductor memory device is constructed by applying this invention to a UVEPROM. Each of cell transistors MC 1  to MC 4  is constituted by a floating gate type MOSFET having floating and control gates. The current paths of four cell transistors MC are serially connected to constitute series circuit  100 . One end of series circuit  100 , or the drain of cell transistor MC 1  is connected to programming voltage source Vpp of high voltage, for example, 20 V through enhancement type (E-type) MOSFET  101  for application of programming voltage. The other end of series circuit  100  or the source of cell transistor MC 4  is connected to the reference voltage terminal (ground terminal) of 0 V. The gate of MOSFET  101  is connected to receive voltage Vin corresponding to programming data Din, and the control gates of four cell transistors MC 1  to MC 4  are connected to receive selection voltages VG 1  to VG 4 , respectively. 
     FIG. 20 is a pattern plan view of the circuit of FIG. 19 which is integrated on a semiconductor wafer. The pattern is formed in and on semiconductor substrate  102 . Diffusion regions  103 - 1  to  103 - 6  are formed in the main surface area of semiconductor substrate  102  to constitute the source and drain regions of MOSFET  101  and four cell transistors MC 1  to MC 4 . MOSFET  101  has gate  104  formed on a first insulation layer (not shown) formed on that part of semiconductor substrate  102  which lies between diffusion regions  103 - 1  and  103 - 2 . Further, floating gates  105 - 1  to  105 - 4  of cell transistors MC 1  to MC 4  are formed on the first insulation layer and over those portions of semiconductor substrate  102  which lie between diffusion regions  103 - 2  and  103 - 3 ;  103 - 3  and  103 - 4 ;  103 - 4  and  103 - 5 ; and  103 - 5  and  103 - 6 . Control gates  106 - 1  to  106 - 4  of cell transistors MC 1  to MC 4  are formed on a second insulation layer (not shown) and over floating gates  105 - 1  to  105 - 4 . 
     With the memory cell of this construction, one end of series circuit  100  or a connection node between cell transistor MC 1  and programming voltage applying MOSFET  101  is connected to column line (not shown) via a contact portion. Therefore, in the FIG. 19 circuit, it is only necessary to form a single contact portion for four cell transistors. For this reason, the number of contact portions can be reduced in comparison with the conventional memory device, and the area of the contact portions can be reduced in the case of forming a memory device of large capacity. When these memory cells are arranged in a matrix form, a selection transistor which is similar to the selection transistor ST in FIG. 10 is necessary. In this case, five transistors are used to form a memory cell which is include four cell transistors MC 1  to MC 4  and one selection transistor. That is, the number of transistors used increases by one in comparison with the prior art case, but if the number of series-connected cell transistors MC is increased, then increase in the pattern area due to the use of the selection transistor can be made smaller than that of the pattern area due to formation of the contact portions. 
     In the memory device according to the second embodiment of this invention, a plurality of cell transistors are serially connected to reduce the number of contact portions. Therefore, unlike the conventional UVEPROM having a plurality of cell transistors connected is in parallel, it is impossible to use a method of programming data by injecting into the floating gate, electrons which are generated by impact ionization occurring near the drain when a high voltage is applied to the gate and drain of the cell transistor to cause a channel current. That is, in the memory device of this invention, a different method is used in which data is programmed by removing electrons from the floating gate or Injecting holes into the floating gaze to thereby set the threshold voltage negative. 
     FIG. 27 shows a circuit model in which the drain of MOSFET  120  is connected to voltage source VD through load circuit  121 , and the source thereof is connected to the ground terminal. If control gate voltage VG of MOSFET  120  is set to 0 V and voltage VD is set at a high voltage level to cause breakdown near the drain of MOSFET  120 , electrons are emitted from the floating gate to set the threshold voltage of MOSFET  120  negative. 
     FIG. 28 is a characteristic diagram showing the voltage-current characteristic of floating gate type MOSFET. Characteristic curve  122  in the drawing shows the characteristic prior to occurrence of the breakdown, and in this case, drain current ID does not flow until the control gate voltage becomes higher than a preset positive voltage. In contrast, characteristic curve  123  shows the characteristic after occurrence of the break-down, and in this case, drain current ID flows even when control gate voltage VG is negative. That is, after the breakdown has occurred in the circuit of FIG. 27, MOSFET  120  comes to have characteristic curve  123  and the threshold voltage is changed from a positive value to a negative value. Further, even in a case where the breakdown does not occur, and if punchthrough current flows, for example, when control gate voltage VG is low, the threshold voltage of MOSFET  120  may be changed to a negative value. An electric field between the drain and the floating gate of MOSFET  120  has an important function, and part of holes generated by the breakdown or punchthrough occurring near the drain is attracted by an electric field between the drain and the floating gate and is injected into the floating gate. Thus, the floating gate may be charged to be positive, making the threshold voltage negative. In the second embodiment, it is important to lower control gate voltage VG, and holes can be injected into the floating gate because of use of low control gate voltage VG. With the use of patterns shown in FIGS. 21A,  21 B,  22  to  25 ,  26 A and  26 B, breakdown will occur prior to punchthrough because of formation of high impurity concentration region  112 - 1 ,  112 - 2  or  112 . 
     There will now be described an operation of the circuit of FIG. 19 with reference to FIGS. 29 and 30. 
     FIG. 29 shows a timing chart of the data programming, and in this example, data is programmed in cell transistor MC 3  in period T 1  and data is programmed in cell transistor MC 2  in period T 2 . In period T 1 , selection voltages VG 1 , VG 2  and VG 4  are set to a high voltage level and selection voltage VG 3  is set to a low voltage level of, for example, 0 V. Then, gate voltage Vin of MOSFET  101  is set to a high voltage to turn on MOSFET  101 , permitting a high voltage of Vpp to be applied to one end of series circuit  100 . Further, in series circuit  100 , cell transistors MC 1 , MC 2  and MC 4  are turned on and cell transistor MC 3  is turned off, and therefore a high voltage is applied to the drain of cell transistor MC 3  which is in the off state. At this time, if Vpp and Vin are set to such values that breakdown or punchthrough may occur near the drain of cell transistor MC 3 , then breakdown or punchthrough occurs in cell transistor MC 3 . Since control gate voltage VG 3  of cell transistor MC 3  is set at 0 V, holes generated by the breakdown or punchthrough are injected into the floating gate. As a result, the threshold voltage of cell transistor MC 3  is changed to a negative value, thus programming data in cell transistor MC 3 . 
     In period T 2 , selection Voltages VG 1 , VG 3  and VG 4  are set to a high voltage level and only selection voltage VG 2  is set to a low voltage level of 0 V. At this time, gate voltage Vin of MOSFET  101  is kept at a high voltage. In this condition, breakdown or punchthrough will occur near the drain of cell transistor MC 3 , and then holes generated by the breakdown or punchthrough are injected into the floating gate, thus programming data in cell transistor MC 3 . 
     In general, it is well known that avalanche breakdown occurring near the drain is caused at a lower drain voltage when the gate voltage is set at a lower voltage. Therefore, the breakdown will occur when the control gate voltage is set at 0 V and will not occur when it is set at a high voltage level. 
     FIG. 30 shows a timing chart at the time of data readout, and in this example, data is sequentially read out from cell transistor MC 1  to cell transistor MC 4 . In the data readout mode, a readout voltage lower than 5 V is applied to one end of series circuit  100  by a load circuit (not shown). Then, control gate voltage VG of a nonselected cell transistor is set to a high voltage of, for example, 5 V, and control gate voltage VG of a selected cell transistor is set to a low voltage of, for example, 0 V. First, control gate voltage VG 1  of cell transistor MC 1  is set to 0 V and thus cell transistor MC 1  is selected. If, for example, data is not programmed in cell transistor MC 1  and the threshold voltage thereof is positive, then cell transistor MC 1  is kept off. Therefore, no current flows in series circuit  100 . 
     Next, control gate voltage VG 2  of cell transistor MC 2  is set to 0 V, and thus cell transistor MC 2  is selected. If, for example, data is programmed in cell transistor MC 2  and the threshold voltage thereof is negative, then cell transistor MC 2  is turned on. Since, at this time, control gate voltages VG 1 , VG 3  and VG 4  of cell transistors MC 1 , MC 3  and MC 4  are set at a high voltage level, cell transistors MC 1 , MC 3  and MC 4  are all set in the conductive state. Therefore, current flows through series circuit  100 . After this, control gate voltages VG 3  and VG 4  of cell transistors MC 3  and MC 4  are sequentially set to 0 V. 
     In the data readout operation, potential at one end of series circuit  100  varies according to the ON and OFF states of selected cell transistor MC, and data can be determined by detecting the potential variation by a sense amplifier or the like. 
     FIG. 31 is a circuit diagram showing a UVEPROM of plural-bit output construction according to another embodiment of this invention. The UVEPROM includes row decoder  131 , column decoder  132  and m memory blocks  133 - 1  to  133 -m. Each memory block  133  is formed with the same construction as memory block  133 - 1 . That is, in each memory block  133 , a plurality of series circuits  100  constructed by serially connecting n floating gate type cell transistors MC 1  to MCn each having a control gate and a floating gate are arranged on rows and columns. Each of series circuits  100  is connected at one end to a corresponding one of column lines Cl to Cp through E-type MOSFET  134 . The gates of MOSFETs  134  connected to series circuits  100  are respectively connected to row lines X 1 , X 2 , . . . to which decoded outputs of row decoder  131  commonly used for all memory blocks  133  are supplied, and the control gates of cell transistors MC 1  to MCn in each series circuit  100  are connected to row lines Wll, W 12 , . . . , Wln, W 21 , W 22 , . . . , w 2 n, . . . to which decoded outputs of row decoder  131  are supplied. Column lines Cl to Cp are connected commonly to data programming/readout node  136  through respective column selection E-type MOSFETs  32  whose gates are connected to column selection lines CS 1  to CSp supplied with respective decoded outputs from column decoder  132  which is commonly used for all memory blocks  133 . 
     Node  136  is connected programming voltage source Vpp through programming voltage applying E-type N-channel MOSFET  137  corresponding to MOSFET  101  in FIG.  19 . Data input circuit  138  generates voltage Vin according to the programming data. Node  136  is also connected to date detection node  140  through potential isolation E-type MOSFET  139  whose gate is connected to receive preset bias voltage Vb. Data detection node  140  is connected to the drain and gate of E-type P-channel load HOSFET  141  whose source is connected to readout voltage source vcc. Further, detection node  140  is connected to the input terminal of sense amplifier  142  which determines is  15  readout data and supplies this readout data to output buffer  143 . 
     With the memory device of the above construction, it is only necessary to connect MOSFET  134  to column line for every n cell transistors, and therefore it is possible to considerably reduce the number of contact portions required for connecting the memory cells to the column lines. As a result, the area occupied by the contact portions can be reduced, and the chip size for large memory capacity can be considerably reduced, thus lowering the manufacturing cost. 
     Now, the operation of the above memory device is explained. 
     FIG. 32 is a timing chart showing one example of data programming operation in the memory device. In this example, series circuit  100  connected to row lines X 1 , Wll to Wln and column line Cl is selected and data is programmed in the cell transistors of selected series circuit  100 . In this case, only column selection line CSl is set to a high voltage level by decoded outputs from column decoder  132  to turn on column selection MOSFET  135 - 1  connected to column line Cl. At this time, 10 other column selection lines CS 2  to CSp are all set to a low voltage level, and the remaining column selection MOSFETs  135 - 2  to  135 -p connected to column lines C 2  to Cp are turned off. Further, only row line X 1  among row lines X 1 , X 2 , . . . is set to a high voltage level by is decoded outputs of row decoder  131 , and series circuit selection MOSFETs  134  which are connected to series circuits  100  arranged on the same row are turned on. Then, only row line Wll is set to a low voltage level by decoded outputs of row decoder  131 . At this time, if output voltage Vin of data input circuit  138  is set at a high voltage level, MOSFET  137  is turned on to permit high programming voltage Vpp to be applied to node  136 . The high voltage applied to node  136  is applied to column line C 1  through column selection MOSFET  135 - 1  which is set in the conductive state. As a result, the breakdown will occur near the drain of cell transistor MCl of selected series circuit  100  and holes are injected into the floating gate thereof, thus programming data in the cell transistor. 
     After this, only row line W 12  is set to a low voltage level by decoded outputs of row decoder  131 . At this time, if output voltage Vin of data input circuit  138  is set at a low voltage level, no hole is injected into the floating gate of memory cell MC 2  connected to row line W 12 . The control gate voltage of the cell transistor in which no hole is injected is set at a low voltage level. This is because row lines X and W are commonly used for all memory blocks  133  and it may become necessary to inject holes into the floating gate of a corresponding cell transistor in each of other memory blocks. 
     Then, the remaining row lines are sequentially set to a low voltage and voltage Vin is set to a voltage level corresponding to the programming data in the same manner as described above. Thus, data can be programmed in n cell transistors of selected series circuit  100 . 
     At this time, in order to prevent the breakdown from occurring in the series circuits on the nonselected rows, it is necessary to decide the impurity concentration of the drain region in each MOSFET  134  so as to set the starting voltage of the avalanche breakdown caused by an electric field between the gate and drain higher than that of the memory cell. 
     FIG. 33 is a timing chart of different voltage waveforms of signals on row lines Wll to Wln in the data programming operation. In the timing chart of FIG. 32, the row line is normally set at a high voltage level and set at a low voltage level for a preset period of time s when data is programmed in the selected cell transistor. However, in this example, row lines Wln to Wll are sequentially set to a low voltage level in this order, thus causing holes to be injected in the order from cell transistor MCn to cell transistor MCl. 
     Further, in the operation shown by the timing chart of FIG. 32, the row line is normally set at a high voltage level, for example, 20 V, and is set at a low voltage level, for example, 0 V for a preset period of time in the data programming mode. However, it is possible to set the row lines at a voltage, for example, 5 V which is lower than 20 V when no cell transistor is selected as shown by the timing chart of FIG. 34, thus reducing the voltage stress on the cell transistors. 
     In the readout operation in the memory device of FIG. 31, one of row lines X 1 , X 2 , . . . connected to the selected cell transistor is set to a high voltage level of, for example, 5 V, and one of row lines Wll, W 12 , W 13 , . . . , Wln, W 21 , W 22 , W 23 , . . . , W 2 n, . . . connected to the selected cell transistor is set to a low voltage level. The remaining row lines are all set to the high voltage level, and cell transistors connected to the remaining row lines are all turned on. At this time, the selection cell transistors connected to the row lines set at the low voltage level are turned on or off according to the threshold voltages thereof. Then, node  140  is kept charged by means of MOSFET  141  or is discharged according to the conduction state of the selection cell transistor. The potential variation on the node  140  is detected by means of sense amplifier  142  which in turn supplies an output as readout data to the external through output buffer  143 . 
     FIG. 35 is a circuit diagram showing the detail construction of a decoding section used in row decoder  131  of the memory device of FIG. 31 to set the voltage of row line X 1 . In this example, six bit-signals A 0  to A 5  are supplied as address signals, four series circuits  100  are provided for each column line C, and each series circuit  100  is constituted by 16 cell transistors. 
     The decoding section for setting the voltage of row line X 1  is connected to receive address signals A 4  and A 5 . When both address signals are set at “1”, N-channel MOSFETs  151  and  152  are turned on so that node  154  connected to voltage source Vcc through P-channel MOSFET  153  which is normally set in the ON state may be set to “0”. As a result, a signal on output node  158  of inverter  157  formed of P-channel MOSFET  155  and N-channel MOSFET  156  and connected to receive a signal from node  154  is set to “1”. 
     In the data programming mode, signal {overscore (PR)} is set at 0 V and signal H is set at a high voltage level. Therefore, row line X 1  is charged by high voltage Vpp through N-channel MOSFET  159  and depletion type (D-type) N-channel MOSFET  160 . Since, at this time, the gate of D-type N-channel MOSFET  161  connected between node  158  and row line X 1  is set at 0 V, no current will flow from row line X 1  which is coupled to voltage source Vpp towards node  158 . 
     In the data readout mode, signal PR is set at 5 V, for example. Since, at this time, high voltage Vpp is not supplied, signal “1” on output node  158  of inverter  157  is transmitted as it is to row line X 1 . 
     In other decoding sections (not shown) for setting voltages of other row lines X 2 , X 3  and X 4 , combination signals of address signals A 4  and A 5 , address signals A 4  and A 5  and address signals A 4  and As are supplied to N-channel MOSFETs  151  and  152 . When input address signals are both set at “1”, a signal of high voltage level or “1” level is supplied from a corresponding row line. 
     FIG. 36 is a circuit diagram showing the detail construction of a decoding section used in row decoder  131  of FIG. 31 to set a voltage of row line wll. The decoder section is connected to receive address signals {overscore (A 0 )}, {overscore (A 1 )}, {overscore (A 2 )} and {overscore (A 3 )}. When all the input addresses are set at “1”, N-channel MOSFETs  162 ,  163 ,  164  and  165  are turned on and node  167  connected to voltage source Vcc through P-channel MOSFET  166  which is normally set in the ON state is set to “0”. As a result, a signal on output node  171  of inverter  170  formed of P-channel MOSFET  168  and N-channel MOSFET  169  and connected to receive the signal on node  167  is set to “1”, and a signal on output node  175  of inverter  174  formed of P-channel MOSFET  172  and N-channel MOSFET  173  and connected to receive the signal on output node  171  of inverter  170  is set to “0” level. 
     In the data programming mode, signal PR is set at 0 V and signal H is set at a high voltage level. As a result, row line Wll is charged through N-channel MOSFET  176  and D-type N-channel MOSFET  177  by high voltage Vpp. Since, at this time, the signal on output node  175  of is inverter  174  is set at “0”, current flows from row line Wll towards node  175  through D-type N-channel MOSFET  178 , setting row line Wll to a low voltage level or 0 V. In contrast, when any one of address signals {overscore (A 0 )}, {overscore (A 1 )}, {overscore (A 2 )} and {overscore (A 3 )} is set at “0”, output node  175  of inverter  174  is set to “1”, thereby charging row line Wll by high voltage Vpp. That is, in the data programming mode, row line Wll is set at 0 V at the time of selection and at high voltage Vpp at the time of nonselection. 
     In the data readout mode, signal {overscore (PR)} is set at 5 V. Since, at this time, high voltage Vpp is not supplied, a signal on output node  175  of inverter  174  is supplied as it is to row line Wll. 
     In other decoding sections (not shown) for setting voltage of row lines W 12 , . . . and W 110  to W 116  (n=16), address signals A 0  to A 3  and {overscore (A 0 )} to {overscore (A 3 )} of a different combination are supplied to the gates of N-channel MOSFETs  162 ,  163 ,  164  and  165 . In the data programming mode, when all the address signals are set at “1”, an output voltage of 0 V is supplied from a corresponding row line. 
     The FIG. 36 circuit can be constituted to contain N-channel MOSFETs  179  and  180  and P-channel MOSFETs  181  and  182  which are surrounded by broken lines in the drawing. Addition of the MOSFETs causes an output signal of “1” or “0” to be supplied through row line Wll according to the logic levels of address signals A 0  to is A 3  only when address signals A 4  and A 5  are set to “1” to set row line X 1  at “1” level. When row line X 1  is not selected, that is, when row line X 1  is set at “0”, row line Wll is always set at “0” so that a row line connected to a group of series-connected cell transistors which are not selected can be set at “0”, enhancing the reliability. However, if it is required to reduce the number of MOSFETS used, it is possible to omit these MOSFETS. 
     In the FIG. 36 circuit, when row line W 11  is selected in the data programming mode, the voltage thereof is set at 0 V. In a case where data is programmed by causing breakdown, no problem will occur, but it is preferable to set the voltage to approx. 1 V when data programming is effected by causing punch-through. In this case, as shown in FIG. 37, bias circuit  183  is connected between MOSFET  173  of inverter  174  in FIG.  36  and the ground terminal, and the source voltage of N-channel MOSFET  173  may be set to the threshold voltage of a cell transistor which is not programmed, for example, 1 V. Bias circuit  183  can be constituted by an N-channel MOSFET whose gate and drain are connected together as shown in FIG.  37 . 
     Further, use of the circuit of FIG. 37 increases current flowing in a cell transistor which is turned on in the data readout mode, enlarging the readout margin. 
     FIG. 38 is a diagram showing the truth values corresponding to the output states of row decoder  131  which generates output signals of the waveforms shown in FIG.  32 . Programming signal PR is set at “0” in the data readout mode. One of  16  row lines Wll to W 116  is set to “0” according to variation in address signals A 0  to A 3 . Row decoder  131  can be formed only to satisfy the output condition set up by the truth values. 
     FIG. 39 is a diagram showing the truth table corresponding to the output states of row decoder  131  which generates output signals of the waveforms shown in FIG. 33 in the data programming mode. 16 row lines Wll to W 116  are sequentially set to 0 V in the order from W 116  to wll according to variation in address signals A 0  to A 3 . Row decoder  131  can be formed only to satisfy the condition determined by the truth table. At this time, the readout or data programming mode is determined based on signal PR, and when signal PR is at “0” indicating the readout mode, row decoder  131  is constituted to satisfy the truth table condition shown in FIG.  38 . 
     FIG. 40 is a circuit diagram showing the modified construction of the circuit shown in FIG.  19 . In the memory device of the FIG. 19 embodiment, the other end of each series circuit  100  or the source of cell transistor MCn is connected to the ground terminal. In contrast, in the memory device of the FIG. 40 embodiment, the other end of each series circuit  100  is connected to the ground terminal through MOSFET  190  having a gate connected to signal line {overscore (PR)} which is set at a low voltage level in the data programming mode. With this construction, substantially no current flows through series circuit  100  in the data programming mode, and thus the drain voltage of the cell transistor can be prevented from being lowered. Therefore, holes can be efficiently injected into the floating gate thereof. MOSFET  190  can be provided for each series circuit  100 , but it is also possible to provide a single MOSFET  190  commonly for a plurality of series circuits  100 . 
     According to the second embodiment described above, a nonvolatile semiconductor memory device can be obtained in which the chip size can be reduced by reducing the number of contact holes and the manufacturing cost can be lowered. 
     However, since cell transistors are connected in series in the UVEPROM shown in FIG. 19, current flowing in each cell transistor becomes small in comparison with the conventional UVEPROM. 
     The operation speed of reading out data from the cell transistor depends on current flowing in the cell transistor, and data readout speed increases as the cell current increases. Since data is read out form the cell transistor by detecting a potential at one end of the series circuit  100  of cell transistors by use of a sense amplifier circuit, it becomes important to charge or discharge one end of the series circuit  100  as quickly as possible in order to enhance the data readout speed. For example, if the channel width and channel length are set to W and L, respectively, current flowing in one cell transistor varies in proportion to W/L. In a case where series circuit  100  is formed of four cell transistors as shown in FIG. 19, current which can flow in series circuit  100  is equal to or less than one-fourth the current flowing in each cell transistor. 
     For this reason, it is preferable to lower the threshold voltage of each cell transistor in the UVEPROM of FIG. 19 in order to enhance the readout speed. That is, the memory cell current becomes larger as the threshold voltage becomes lower, and the data readout speed becomes higher. In general, in order to lower the threshold voltage, the impurity concentration of the channel region will be lowered. However, in order to lower the breakdown voltage and improve the programming characteristics, it is necessary to increase the impurity concentration of the channel region. That is, when the impurity concentration of the channel region is high, the breakdown will occur at a lower voltage. Therefore, if the impurity concentration of the channel region is lowered to enhance the data readout speed, the breakdown voltage becomes high and the programming characteristics will be deteriorated. 
     As described above, the impurity concentration of the channel region in the cell transistor is an important factor for both characteristics, the data readout speed and programming characteristics. That is, the two characteristics may be improved and deteriorated, or vice versa when the impurity concentration is set low or high, respectively. Therefore, it is necessary to make a compromise between the two characteristics. 
     For the reasons described above, in the patterns of FIGS. 21A,  23  to  25 , and  26 A, part of the channel region which is formed in contact with the drain region has a higher impurity concentration than the other regions. 
     Since part of the channel region is formed to have a higher impurity concentration than the other regions, a breakdown may easily occur between the high impurity concentration region and the drain region, thus lowering the breakdown voltage. Since, in this case, the other part of the channel region can be formed to have a sufficiently low impurity concentration, the threshold voltage can be set at a low voltage, permitting a sufficiently large memory cell current. Further, impurity concentration of the portion other than the high impurity concentration region is set to such a low value that each cell transistor can have a low threshold voltage and may permit a sufficiently large channel current flow. 
     The same portions in FIG. 21A as those in FIG. 20 are denoted by the same reference numerals. High impurity concentration regions  112 - 1  and  112 - 2  are formed in those portions of channel region  111  which lie in contact with field portions  110 - 1  and  110 - 2 . FIG. 21B is a cross sectional view of a semiconductor device taken along line  21 B— 21 B of the pattern of FIG.  21 A. The semiconductor device has P-type substrate  102  and floating gate  105 - 4  formed on insulation layer  108  which in turn is formed on substrate  102 . Further, control gate  106 - 4  is formed on insulation layer  109  which in turn is formed on floating gate  105 - 4 . For example, floating gate  105 - 4  is formed of polycrystalline silicon, and control gate  106 - 4  is formed of polycrystalline silicon or metal. High impurity concentration regions  112 - 1  and  112 - 2  containing, at a high impurity concentration, P-type impurity which is the same as that of the substrate are formed in channel region  111  which is divided by means of the field portions  110 - 1  and  110 - 2  of insulation films  108  and  109 . 
     With the above construction, a breakdown may easily occur between the drain region and high impurity concentration  112 - 1  and  112 - 2  of each channel region  111 , and thus the breakdown voltage can be lowered. Further, since portion of channel region  111  other than high impurity concentration regions  112 - 1  and  112 - 2  is formed to have a low impurity concentration and the threshold voltage is set to a low voltage, a channel current flowing each cell transistor can be increased. As a result, both of the data readout speed and programming characteristics in the memory device of this embodiment can be enhanced at the same time. 
     In the memory device described above, high impurity concentration regions  112 - 1  and  112 - 2  are formed in two portions of channel region  111  in contact with the opposite field portions  110 - 1  and  110 - 2  of insulation layer  108 . This is because misalignment will occur when an ion-implantation mask is formed. That is, when the mask is formed, patterns surrounded by broken lines are first formed on an ion shielding member (not shown) so as to expose ion-implanted regions as shown in the pattern plan view of FIG.  22 . Then, portion of the shielding member except those on which the patterns are formed is removed. That is, portions  113  and  114  of the shielding member surrounded by broken lines as shown in FIG. 22 are removed to form the ion-implantation mask. In this case, even if the pattern is deviated on the s shield member rightwards or leftwards in the drawing, the total contact area between the drain region and high impurity concentration region  125  formed in the following step can be kept constant. As a result, variation in channel current can be suppressed in this embodiment. 
     The breakdown between the drain region and high impurity concentration regions  112 - 1  and  112 - 2  occurs in the form of junction breakdown when the impurity concentration of high impurity concentration regions  112 - 1  and  112 - 2  are set extremely high, the operation thereof cannot be controlled by the gate potential. Therefore, it is necessary to set the impurity concentration of high impurity concentration regions  112 - 1  and  112 - 2  in such a range that the gate control can be made effective. That is, it is sufficient to ion-implant impurity at an impurity concentration slightly higher than that of the channel region into which impurity is ion-implanted to control the threshold voltage. As is well known in the art, a breakdown is caused by an electric field between the gate and drain of an ordinary MOSFET in a portion directly under the drain region thereof at a voltage lower than that at which the breakdown occurs in an ordinary PN junction. The breakdown voltage becomes high as the gate voltage becomes high, and the same breakdown as the junction breakdown occurs when the gate voltage has reached a certain high voltage level. Therefore, it is preferable to set the impurity concentration of high impurity concentration regions  112 - 1  and  112 - 2  in such a range that the breakdown voltage can be controlled by the gate voltage. 
     FIGS. 23 to  25 , and  26 A and  26 B show other pattern plan views of series circuit  100  shown in FIG.  19 . 
     In the pattern of FIG. 23, a high impurity concentration region corresponding to high impurity concentration regions  112 - 1  and  112 - 2  shown in FIGS. 21A and 21B is formed on the entire portion of channel region  111  which is positioned in contact with the drain regions  103 - 2  to  103 - 5 . That is, high impurity concentration region  112 A is formed in contact with drain region  103 - 2 . Likewise, high impurity concentration regions  112 B to  112 D are formed in contact with drain regions  103 - 3  to  103 - 5 . 
     In the pattern of FIG. 24, high impurity concentration regions  112 - 1  and  112 - 2  are formed in two portions of channel region  111  which are positioned in contact with the drain region and the field insulation layer. 
     In the pattern of FIG. 25, high impurity concentration region  112  is formed only at the center of that portion of channel region  111  which is positioned in contact with the drain region. 
     In the pattern of FIG. 26A, high impurity concentration region  112  is formed only at the center of that portion of channel region  111  which is positioned in contact with the drain region, and it is formed in a triangle form. In a case where high impurity concentration region  112  is formed in a triangle form, part of a pattern shown by broken lines in FIG. 26B can be used as a pattern for forming the ion-implantation mask, making it easy to form the mask. 
     A process of ion-implanting impurity into the channel region to control the threshold voltage can be omitted by suitably setting the impurity concentration is of the semiconductor wafer on which the above memory cell is formed. Therefore, it is only necessary to ion-implanting impurity into channel region  111  to form high impurity concentration regions  112 - 1 ,  112 - 2 , and  112 . 
     For example, in a case where the memory device is formed on the semiconductor wafer having the substrate resistivity of 10 Ω·cm, a threshold voltage of approx. 0 V can be obtained without ion-implanting impurity into the channel region. It is preferable that a cell transistor in which data is not programmed is turned off when it is selected and permits a larger current to flow when it is not selected. For this reason, it is preferable to set the threshold voltage to approx. 0 V. 
     In a UVEPROM having series-connected memory cells and formed with the above pattern structure, the data readout speed and programming characteristic can be enhanced to a satisfactory degree.