Abstract:
An internal step-down power supply circuit is capable of improving response performance (transition from a standby state to an active state in particular) of a system without increasing current consumption. The internal step-down power supply circuit includes an internal step-down power-supply output node (N 15 ) for outputting an internal step-down power-supply potential and a driver ( 120 ) for adjusting an external power-supply potential VDD and supplying it to the internal step-down power-supply output node (N 15 ). The internal step-down power supply circuit further includes a divider circuit ( 160 ) for diving a voltage developed at the internal step-down power-supply output node (N 15 ) and outputting a divided voltage and a differential amplifier ( 100 ) for comparing the voltage outputted from the divider circuit and a reference voltage (Vf). The differential amplifier ( 100 ) outputs a voltage equivalent to twice predetermined gain. The operational amplifier sets the conductance of each of transistors (P 10  and N 10 ) for feeding a current in response to the reference voltage (Vf) to twice or more the conductance of each of transistors (P 11  and N 11 ) for feeding a current in response to the voltage outputted from the divider circuit.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The present invention relates to an internal step-down power supply circuit suitable for use in a semiconductor device.  
           [0002]    An internal step-down or deboost power supply circuit for generating an internal source or power-supply voltage by using an external power-supply voltage comprises a driver for supplying a source or power supply voltage, a divider circuit for dividing the internal power-supply voltage, an amplifier for comparing the voltage generated from the divider circuit and a reference voltage and supplying a drive voltage to the driver based on the result of comparison, etc.  
           [0003]    Now, the more a circuit connected to a terminal for outputting an internal power-supply potential in the internal step-down power supply circuit increases in size, the more source impedance must be reduced. Thus, the size of a transistor for the driver becomes very large in a VLSI in which a stepped-down or deboosted power supply produced in the internal step-down power supply circuit is used in the whole semiconductor chip, thereby increasing load capacity of the amplifier. However, a change in instantaneous current of the circuit connected to the terminal for outputting the internal power-supply potential results in such very large values as to rise in one stroke from a value near zero to a few 10 mA even in the case of a small current and a few 100 mA in the case of a large current. On the other hand, since the current that the amplifier can feed, is limited in terms of specs, various methods used up to now could not achieve compatibility with a follow-up to a change in internal step-down power-supply potential.  
         SUMMARY OF THE INVENTION  
         [0004]    An object of the present invention is to provide an internal step-down power supply circuit which is capable of improving response performance (transition from a standby state to an active state in particular) of a system without increasing current consumption.  
           [0005]    An internal step-down power supply circuit of the present invention includes an internal step-down power supply output node for outputting an internal step-down power-supply potential, a driver for adjusting an external power-supply potential and outputting the same to the internal step-down power-supply output node, a divider circuit for diving a voltage developed at the internal step-down power-supply output node and outputting a divided voltage, and a differential amplifier for comparing the voltage outputted from the divider circuit and a reference voltage and outputting a voltage equivalent to twice the predetermined gain, the operational amplifier setting the conductance of each of transistors for feeding a current in response to the reference voltage to twice or more the conductance of each of transistors for feeding a current in response to the voltage outputted from the divider circuit. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]    While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which:  
         [0007]    [0007]FIG. 1 is a circuit diagram showing a first embodiment of an internal step-down power supply circuit of the present invention;  
         [0008]    [0008]FIG. 2 is a circuit diagram illustrating a second embodiment of an internal step-down power supply circuit of the present invention;  
         [0009]    [0009]FIG. 3 is a circuit diagram depicting a third embodiment of an internal step-down power-supply circuit of the present invention;  
         [0010]    [0010]FIG. 4 is a circuit diagram showing a fourth embodiment of an internal step-down power supply circuit of the present invention;  
         [0011]    [0011]FIG. 5 is a circuit diagram depicting a fifth embodiment of an internal step-down power supply circuit of the present invention;  
         [0012]    [0012]FIG. 6 is a circuit diagram illustrating a sixth embodiment of an internal step-down power supply circuit of the present invention;  
         [0013]    [0013]FIG. 7 is a circuit diagram showing a seventh embodiment of an internal step-down power supply circuit of the present invention;  
         [0014]    [0014]FIG. 8 is a circuit diagram depicting an eighth embodiment of an internal step-down power supply circuit of the present invention; and  
         [0015]    [0015]FIG. 9 is a circuit diagram illustrating a ninth embodiment of an internal step-down power supply circuit of the present invention; 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0016]    Preferred embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings.  
         [0017]    [0017]FIG. 1 is a circuit diagram showing a first embodiment of an internal step-down power supply circuit of the present invention. In the present specification unless otherwise stated below, VDD indicates an external source or power supply voltage, IVC indicates an internal source or power-supply voltage indicative of a potential level lower than the level of the external power supply voltage VDD, “H” indicates an external source or power supply voltage level, “L” indicates a ground level, “VF” indicates a reference potential, and “VB” indicates a current control voltage for a differential amplifier, respectively. Further, NMOSs are signs indicative of N channel MOS transistors, PMOSs are signs indicative of P channel MOS transistors, CAPs are signs indicative of capacitors, INVs are signs indicative of inverters, respectively.  
         [0018]    The internal step-down power supply circuit shown in FIG. 1, according to the first embodiment of the present invention comprises a differential amplifier  100 , a driver  120 , a speed-up capacitor  140  (CO 1 ) and a divider circuit  160 . The differential amplifier  100  is an amplifier circuit which amplifies the difference between right-and-left input-potentials and outputs it therefrom. The speed-up capacitor  14  is a capacitor for instantaneously transferring a change in internal power-supply voltage to an input part of the differential amplifier  100 . The driver  120  comprises a transistor P 04  for supplying a current from the external power supply VDD to the internal step-down power supply IVC. The divider circuit  160  is a circuit for generating a voltage divided from a constant voltage.  
         [0019]    In FIG. 1, P 00  through P 06  indicate PMOSs respectively. Further, N 00  through N 03  indicate NMOSs respectively. A signal VBA 00  is a signal brought to “H” in an active state and brought to “L” upon standby. A terminal VBS 00  is used to supply a low voltage “VB”. A node N 05  corresponds to an output terminal used to output the internal step-down power supply IVC.  
         [0020]    A gage electrode of the NMOS N 01  is electrically connected to a node N 01  corresponding to one signal input terminal of the differential amplifier  100 . One electrodes of PMbSs P 10  and P 11  are electrically connected to the external power supply potential VDD. A gate electrode of the PMOS P 10 , a gate electrode and the other electrode of the PMOS P 11 , and the other electrode of an NMOS N 11  are electrically connected to a node N 03 . The other electrode of the PMOS P 11  and the other electrode of an NMOS N 10  are electrically connected to a node N 02 . One electrode of the NMOS N 10 , one electrode of the NMOS N 11 , one electrode of the NMOS N 02 , and one electrode of the NMOS N 03  are electrically connected to a node N 06 . A gate electrode of the NMOS N 02  is electrically connected to the terminal VBS 00 , whereas the other electrode thereof is electrically connected to a ground potential GND. A gate electrode of the NMOS N 03  is supplied with the signal VBA 00 , and the other electrode thereof is electrically connected to the ground potential GND.  
         [0021]    Now, the NMOS N 11  and the PMOS P 11  of the differential amplifier  100  make use of transistors low in conductance. The ratio between the conductance of the PMOS P 10  and that of the NMOS N 10 , and the ratio between the conductance of the PMOS P 11  and that of the NMOS N 11  are equally set. The ratios determines the gain of the differential amplifier  100 . The NMOS N 10  and the PMOS P 10  are respectively set to conductances equivalent to n times those of the NMOS N 11  and PMOS P 11 . Although the more n increases, the more the effect is brought about, the intended or objective one can be achieved if more than or equal to twice. If preferably four times or more are given, then the effect becomes pronounced as will be described below.  
         [0022]    The driver  140  comprises the PMOS P 04 . One electrode of the PMOS P 04  is electrically connected to the external power supply potential VDD, the other electrode thereof is electrically connected to the node N 05  (output terminal of internal power-supply voltage IVC), and a gate electrode thereof is electrically connected to the output node N 02  of the differential amplifier  100 .  
         [0023]    The speed-up capacitor  140  (C 01 ) is electrically connected between a node N 04  electrically connected to the gate electrode of the NMOS N 01 , which corresponds to the other input of the differential amplifier  100 , and the node N 05 .  
         [0024]    The divider circuit  160  comprises the two PMOSs P 05  and P 06 . One electrode of the PMOS P 05  is electrically connected to the node N 05 , whereas the other electrode thereof is electrically connected to the node N 04  and one electrode of the PMOS P 06 . A gate electrode of PMOS P 05  is electrically tied to the ground potential GND in common with the gate electrode and other electrode of the PMOS P 06 .  
         [0025]    The operation of the internal step-down power supply circuit according to the first embodiment of the present invention will next be described.  
         [0026]    The differential amplifier  100  is a circuit which outputs the difference between the right and left input signals as its amplified potential difference. In the present circuit, a voltage Vf at one input node N 01  is set as a reference voltage. The difference between the voltage Vf and a potential or voltage at the other input node N 04  is amplified to a potential difference equivalent to twice the gain with respect to the node N 03  and then outputted to the output node N 02 . Let&#39;s now assume that the ratio between the conductances of the PMOSs P 10  and P 11  (i.e., NMOSs N 10  and N 11 ) is defined as 4:1 and a current that flows through the whole differential amplifier  100 , is defined as 5 mA. A current that flows through the PMOS P 11  and the NMOS N 11 , is 1 mA, and a current that flows through the PMOS P 10  and the NMOS N 10 , is 4 mA. Accordingly, the output node N 02  is driven by the current of 4 mA.  
         [0027]    If the ratio between the conductance of the PMOS P 10  (i.e., NMOS N 10 ) and that of the PMOS P 11  (i.e., NMOS N 11 ) is assumed to be 1:1, then the current that flows through the PMOS P 11  and the NMOS N 11 , is 2.5 mA, and the current that flows through the PMOS P 10  and the NMOS N 10 , is 2.5 mA. Thus, the output node N 02  is driven by the current of 2.5 mA. Namely, the driver  120  can be early driven by a change in conductance ratio.  
         [0028]    The PMOS P 04  of the driver  120  supplies a current corresponding to the voltage at the node N 02  to the node N 05 . The divider circuit  160  divides the potential at the node N 05  to a predetermined division ratio and outputs it to the other input node N 04  of the differential amplifier  100 . Since the potential at the node N 04  reaches “internal power-supply voltage IVC×(⅔)=Vf” when the ratio between ON resistances of the PMOSs P 05  and P 06  corresponding to a pair of division ratio setting element groups, for example, is given as 1:2, the internal power-supply voltage IVC=1.5×Vf. The PMOS P 04  and the differential amplifier  100  are respectively set to drive capabilities commensurate with an instantaneous current and a stationary current consumed by a circuit (hereinafter called an “internal power-supply voltage slave circuit”) connected to the output node N 05 . Thus, the differential amplifier  100 , the driver  120  and the divider circuit  160  constitute a negative feedback circuit, which is capable of obtaining a step-down voltage corresponding to the reference voltage Vf and the division ratio of the divider circuit  160 . Incidentally, the speed-up capacitor performs the action of instantaneously transferring a change in the potential at the node N 05  to the node N 04  and increasing a response speed of a feedback system.  
         [0029]    Incidentally, since power consumption is low in a standby state, the signal VBA 00  is rendered “L” and the NMOS N 03  is held OFF. The low voltage VB is always applied to the terminal VBS 00  and the NMOS N 02  feeds a small current alone. Since only the small current allowed to flow by the NMOS N 02  flows through the differential amplifier  100 , a response speed is extremely reduced. Since, however, the instantaneous current of the internal power-supply voltage slave circuit is not developed in the standby state, the potential of the internal power-supply voltage can be maintained.  
         [0030]    On the other hand, the signal VBA 00  results in “H” in an active state. A current enough to allow the PMOS P 04  to instantaneously respond to the instantaneous current that flows out from the node N 05  and maintain the internal power-supply voltage, flows through the NMOS N 03  that constitutes the differential amplifier  100 . Therefore, even if the instantaneous current of the internal power-supply voltage slave circuit varies in a steady state, the system is capable of suppressing a variation in the potential of the internal power-supply voltage.  
         [0031]    According to the first embodiment of the present invention as described above, since the drive capability of the driver can be enhanced under the same current consumption and exclusively-possessed or occupied area, it is possible to lighten a reduction in the potential of the internal power-supply voltage due to the instantaneous current of the internal power-supply voltage slave circuit.  
         [0032]    With a decrease in the size of the NMOS N 11  as compared with the NMOS N 01 , the node N 04  is reduced in parasitic capacitance too. Therefore, an advantageous effect is also brought about in that the speed-up capacitor C 01  can be made smaller than ever and the efficiency of-transfer of the change in voltage from the node N 05  increases.  
         [0033]    [0033]FIG. 3 is a circuit diagram showing an internal step-down power supply circuit according to a second embodiment of the present invention. Incidentally, the same elements of structure as those in FIG. 2 are respectively identified by the same reference numerals in FIG. 3 and the description thereof will therefore be omitted.  
         [0034]    Since the second embodiment is different from FIG. 2 in terms of a configuration of a differential amplifier  101 , a description will be made of that portion alone.  
         [0035]    The differential amplifier  101  comprises PMOSs P 10  and P 11 , NMOSs N 10 , N 11  and N 23  through N 25 , and a stabilizing capacitor C 20 . In the differential amplifier  101 , one electrode of the NMOS N 10  is electrically connected to a node N 02 , the other electrode thereof is electrically connected to a node N 26 , and a gate electrode thereof is electrically connected to a node N 01 , respectively. One electrode of the NMOS N 11  is electrically connected to a node N 03 , the other electrode thereof is electrically connected to a node N 27 , a gate electrode thereof is electrically connected to a node N 14 , respectively. One electrode of the NMOS N 23  is electrically connected to a node N 26 , the other electrode thereof is electrically connected to a ground potential GND, and a gate electrode thereof is supplied with a signal VBA 00 , respectively. One electrode of an NMOS N 22  is electrically connected to the node N 26 , the other electrode thereof is electrically connected to the ground potential GND, and a gate electrode thereof is electrically connected to a terminal VBS 00 , respectively. One electrode of the NMOS N 24  is electrically connected to the node N 27 , the other electrode thereof is electrically connected to the ground potential GND, and a gate electrode thereof is supplied with the signal VBA 00 , respectively. One electrode of the NMOS N 25  is electrically connected to the node N 27 , the other electrode thereof is electrically connected to the ground potential GND, and a gate electrode thereof is electrically connected to the terminal VBS 00 , respectively. The stabilizing capacitor C 20  is electrically connected between the node N 27  and GND.  
         [0036]    The ratio of the conductance of the NMOS N 23  to that of the NMOS N 24  is set equal to the ratio between the conductance of the PMOS P 10  and that of the PMOS P 11  employed in the first embodiment. Further, the ratio between the conductance of the NMOS N 22  and that of the NMOS N 25  is also set to become similar to the ratio between the conductance of the NMOS N 23  and that of the NMOS N 24 .  
         [0037]    The operation of the internal step-down power supply circuit according to the second embodiment of the present invention will next be described with reference to FIG. 2.  
         [0038]    A current that flows through an internal power-supply voltage slave circuit, is 0 in a standby state. The NMOSs N 22  and N 25  connected to the terminal VBS 00  simply feed a small current. The PMOSs P 11 , P 10  and the NMOSs N 10  and N 11  that constitute the differential amplifier  101 , are respectively in a state of being slightly ON. Similarly, a PMOS P 04  of a driver  120  is also in a state of being slightly ON, which is indicative of only the supply of a current used up or consumed by a divider circuit. The differential amplifier  101  serves as a current mirror similar to the differential amplifier  100 . Tn a manner similar to the first embodiment upon standby, the other input voltage converges on a predetermined step-down or deboost voltage with one input voltage Vf as a reference voltage.  
         [0039]    On the other hand, the signal VBA 00  is brought to “H” in an active state and hence the NMOSs N 23  and N 24  each of which receives the signal therein as an input, are turned ON. Therefore, although there is a difference in that current consumption increases as compared with the standby state, the step-down voltage in the steady state is basically identical to that in the first embodiment.  
         [0040]    A change from the standby state to the active state will next be described.  
         [0041]    Voltages applied to the gates of the NMOSs N 10  and N 11  in a state of equilibrium remain unchanged upon both the standby and active states. Thus, each of the nodes N 26  and N 27  is brought to a slightly high voltage by current suppression upon standby as compared with upon the active state. Since the individual internal power-supply voltage slave circuits are operated in unison and starts to feed a large instantaneous current upon transition from this state to the active state, the output is temporarily reduced. While the node N 26  is reduced in one stroke in potential by the turning ON of the NMOSs N 23  and N 24  in the differential amplifier  101 , the node N 27  is slowly lowered in potential since time is required to discharge the stabilizing capacitor C 120 . Accordingly, a reduction in the potential at the node N 03  is low by a gradual amount of reduction in the potential at the node N 27 , and the supply of the current to the PMOSs P 10  and P 11  still remains small. Thus, the NMOS N 10  at the time that the node N 26  is lowered in one stroke in potential, is sharply turned ON and only the node N 10  is quickly reduced in potential. Since the PMOS P 04  of the driver is brought to a state of being capable of supplying a large current instantaneously, the internal power-supply voltage is capable of lightening a potential reduction and providing quick restoration.  
         [0042]    According to the second embodiment of the present invention as described above, since the driver is immediately brought to the ON state upon transition from the standby state to the active state, the reduction in the potential of the internal step-down power supply due to the instantaneous current that flows out from the output, can be lightened and the restoration can be speeded up.  
         [0043]    [0043]FIG. 4 is a circuit diagram showing an internal step-down power supply circuit according to a third embodiment of the present invention. Incidentally, the same components as those shown in FIG. 3 are respectively identified by the same reference numerals in FIG. 4, and the description thereof will therefore be omitted.  
         [0044]    The third embodiment is different in timing provided to input the signal VBA 000  shown in FIG. 3. Namely, the third embodiment is provided with a delay circuit  180  for delaying the differential amplifier  10  employed in the second embodiment from a standby state. Hence only portions associated with it will be described.  
         [0045]    In a differential amplifier  102 , gate electrodes of NMOSs N 23  and N 24  are respectively electrically connected to a node VBA 30 . The node VBA 30  receives a signal VBA 00  through the delay circuit  180  in such a manner that the signal VBA 00  is delayed by a time required to completely bring an internal step-down power-supply slave circuit to the standby state upon only the falling edge of the signal VBA 00 . Incidentally, when the signal VBA 00  rises, its timing is the same.  
         [0046]    The operation of the internal step-down power supply circuit according to the third embodiment of the present invention will next be described with reference to FIG. 4.  
         [0047]    Operations in the standby state, the active state and at the transition from the standby state to the active state are identical to the second embodiment and the description thereof will therefore be omitted.  
         [0048]    Even upon the transition from the active state to the standby state in a manner similar to the transition from the standby state to the active state, the internal step-down power-supply slave circuit is rendered inactive and hence a large change in instantaneous current takes place. Thus, a problem arises in that when the step-down power-supply circuit is immediately brought to the standby state while the internal step-down power-supply slave circuit is not rendered inactive, a step-down power-supply voltage cannot maintain a predetermined voltage with respect to a subsequent change in instantaneous current. Therefore, the third embodiment is provided with the delay circuit  180  having a delay equivalent to the time required to completely bring the internal step-down power-supply slave circuit into inactivity according to the signal VBA 00  upon transition from the active state to the standby state. Thus, the step-down circuit is also brought to the active state while the internal step-down power-supply slave circuit is in operation, whereas the step-down circuit is brought to the standby state in a state in which the internal step-down power-supply slave circuit stops operating and no instantaneous current flows.  
         [0049]    According to the third embodiment of the present invention as described above, since there is provided the delay circuit  180  for providing the delay equivalent to the time required to completely bring the internal step-down power-supply slave circuit to the non-activity according to the signal VBA 00 , the step-down power-supply voltage can be maintained at a predetermined voltage even upon the transition from the active state to the standby state.  
         [0050]    [0050]FIG. 5 is a circuit diagram showing an internal step-down power supply circuit according to a fourth embodiment of the present invention. Incidentally, the same components as those in FIG. 4 are respectively identified by the same reference numerals in FIG. 5 and the description thereof will therefore be omitted.  
         [0051]    In the fourth embodiment, a differential amplifier  103  is provided as a modification wherein an NMOS N 46  for equalizing voltages at nodes N 26  and N 27  upon standby is added to the differential amplifier  102  employed in the third embodiment. Further, there is provided a circuit (inverter INV 4 ) for generating a signal VBA 0 B for controlling the NMOS N 46 . These portions different in configuration from the third embodiment will be described below.  
         [0052]    Since the control signal VBA 0 B is of a phase-inverted signal of a signal VBA 00 , the inverter INV 4  uses a signal VBA as an input signal. In the differential amplifier  103 , one electrode of the NMOS N 46  is electrically connected to a node N 26 , the other electrode thereof is electrically connected to a node N 27 , and a gate electrode thereof is electrically connected to the output of the inverter TNV 4  respectively. The NMOS N 46  has an ON resistance equivalent to the extent negligible for ON resistances of the NMOSs N 23  and N 24 .  
         [0053]    The operation of the fourth embodiment of the present invention will next be described using FIG. 5 in terms of only the added circuit portion.  
         [0054]    Since the signal VBA 0 B is “L” and the NMOS N 46  is held OFF in an active state, the operation thereof is identical to the third embodiment.  
         [0055]    Since the signal VBA 0 B takes “L” of a signal VBA 00  and is then brought to “H” in a standby state, the NMOS N 46  is turned ON. Namely, the potentials at the node N 26  and the node N 27  are equalized.  
         [0056]    According to the fourth embodiment of the present invention as described above, the equalization of the potentials at the nodes N 26  and N 27  makes it possible to bring the step-down power-supply voltage at standby to a set value without being so affected by transistor manufacturing variations.  
         [0057]    Since it is necessary to reduce current consumption at standby as less as possible, currents consumed at the NMOSs N 23  and N 24  are extremely low. When these currents are reduced to a sub-threshold current, there is a danger that the step-down power-supply voltage at standby deviates from the set voltage due to variations in the manufacture of the NMOSs N 23  and N 24  that constitute the differential amplifier. According to the fourth embodiment, since the nodes N 26  and N 27  are equalized in potential, low current consumption can be achieved without being subjected to the variations in the manufacture of the NMOSs N 23  and N 24 .  
         [0058]    [0058]FIG. 6 is a circuit diagram showing an internal step-down power supply circuit according to a fifth embodiment of the present invention. Incidentally, the same components as those in FIG. 5 are respectively identified by the same reference numerals in FIG. 6 and the description thereof will therefore be omitted.  
         [0059]    The fifth embodiment makes use of a differential amplifier  107  from which the NMOS N 23  provided for the differential amplifier  106  employed in the fourth embodiment is deleted.  
         [0060]    The operation of the fifth embodiment of the present invention will next be described using FIG. 6 in terms of only the portion different from the fourth embodiment.  
         [0061]    A signal VBA 0 B is “L” and an NMOS N 46  is held OFF in an active state. While the NMOS N 23  has been deleted, a current that flows through an NMOS N 23 , can be neglected because the current is less reduced by double to triple digits as compared with a current that flows through an NMOS N 22 . Therefore, the operation of the fifth embodiment at the active state is considered to be identical to the third and fourth embodiments.  
         [0062]    Since the signal VBA 0 B takes “L” of a signal VBA 00  and is brought to “H” in a standby state, the NMOS N 46  is turned ON. Accordingly, an ON resistance of the NMOS N 46  is negligibly smaller than that of the NMOS N 23 , potentials at nodes N 26  and N 27  are equalized in a manner similar to the fourth embodiment.  
         [0063]    According to the fifth embodiment of the present invention as described above, a step-down power-supply voltage at standby can be brought to a set voltage owing to the equalization of the potentials at the nodes N 26  and N 27  in the same manner as the fourth embodiment.  
         [0064]    In the fifth embodiment, a chip area equivalent to the deleted area of NMOS N 23  can be reduced as compared with the fourth embodiment. Further, current consumption can also be reduced.  
         [0065]    Incidentally, while the NMOS N 23  has been deleted and the NMOS N 24  has been left behind in the fifth embodiment, the inverse thereof is also made possible.  
         [0066]    [0066]FIG. 7 is a circuit diagram showing an internal step-down power supply circuit according to a sixth embodiment of the present invention. Incidentally, the same components as those in FIG. 6 are respectively identified by the same reference numerals in FIG. 7 and the description thereof will therefore be omitted.  
         [0067]    The sixth embodiment makes use of a differential amplifier  105  wherein in the differential amplifier  104  employed in the fifth embodiment, the NMOS N 46  for equalizing the voltages at the nodes N 26  and N 27  at standby is changed to,two series-connected NMOSs N 66  and N 67 , and an NMOS N 64  for bringing an intermediate node N 68  between the two NMOSs N 67  and N 68  down to a ground potential is provided as an alternative to the NMOS N 24 . Only these portions different in configuration from the fifth embodiment will be explained below.  
         [0068]    One electrode of the NMOS N 66  is electrically connected to the node N 26 , the other electrode thereof is electrically connected to the node N 68 , and a gate electrode thereof is supplied with a signal VBA 0 B, respectively. One electrode of the NMOS N 67  is electrically connected to the node N 27 , the other electrode thereof is electrically connected to the node N 68 , and a gate electrode thereof is supplied with the signal VBA 0 B, respectively. One electrode of the NMOS N 64  is electrically connected to the node N 68 , the other electrode thereof is electrically connected to the ground potential GND, and a gate electrode thereof is electrically connected to a node VBA 30  (output of an inverter  180 ), respectively.  
         [0069]    Incidentally, ON resistances,of the NMOSs N 66  and N 67  are negligibly smaller than an ON resistance of the NMOS N 64 . When it is desired to follow up the extreme strictness about the voltage, the ratio between the conductance of the NMOS N 66  and that of the NMOS N 67  is matched with the ratio between the conductance of the PMOS P 10  and that of the PMOS P 11 .  
         [0070]    The operation of the sixth embodiment of the present invention will be described using FIG. 7 in terms of the portions different from the fifth embodiment.  
         [0071]    The signal VBA 0 B is “L” and the NMOSs N 66  and N 67  are held OFF in an active state. Since the NMOS N 24  is omitted, an active current for the differential amplifier  105  flows through the NMOSs N 22  and N 25  alone. The current that flows through the NMOS N 23  deleted from the fifth embodiment, is negligible because it is reduced by double or triple digits as compared with the current that flows through each of the NMOSs N 22  and N 25 . Therefore the operation of the sixth embodiment in the active state may be considered to be identical to the third through fifth embodiments.  
         [0072]    Since the voltage applied to the gate of the NMOS N 64  is low, the NMOS N 64  is always held ON. Since the signal VBA 0 B takes L” of a signal VBA 00  and is brought to “H” in a standby state, the NMOSs N 66  and N 67  are held ON. Since ON resistances of the NMOSs N 66  and N 67  are negligibly smaller than the ON resistance of the NMOS N 64  (or it is matched with a conductance ratio between the right and left transistors that constitute the differential amplifier  105 ), potentials at the nodes N 26  and N 27  are completely equalized.  
         [0073]    According to the sixth embodiment of the present invention as described above, economizing current consumption is achieved and a step-down power-supply voltage at standby is provided as a set voltage owing to the complete equalization of the potentials at the nodes N 26  and N 27 . Thus, they can be compatible with each other within a wide power-supply potential range.  
         [0074]    [0074]FIG. 8 is a circuit diagram showing an internal step-down power supply circuit according to a seventh embodiment of the present invention. Incidentally, the same components as those in FIG. 7 are respectively identified by the same reference numerals in FIG. 8 and the description thereof will therefore be omitted.  
         [0075]    The seventh embodiment is an example wherein the divider circuit  160  employed in the fifth embodiment is modified to provide a divider circuit  161 . Since others are identical to FIG. 7 except for the divider circuit  161 , the configuration of the divider circuit  161  will be explained.  
         [0076]    A signal AVM 70  is a control signal for performing switching to a step-down power-supply voltage according to device&#39;s operation modes. An inverter INV 7  receives the signal AVM 70  therein and outputs a phase-inverted signal AVM 7 B thereof therefrom.  
         [0077]    In the divider circuit  161 , one electrode of a PMOS P 05  is electrically connected to a node N 15 , the other electrode thereof is electrically connected to a node N 14 , and a gate electrode thereof is supplied with the control signal AVM 70 , respectively. One electrode of a PMOS P 06  is electrically connected to a node N 14 , the other electrode thereof is electrically connected to a ground potential GND, and a gate electrode thereof is supplied with the control signal AVM 70 , respectively. One electrode of a PMOS P 75  is electrically connected to the node N 15 , the other electrode thereof is electrically connected to the node N 14 , and a gate electrode thereof is supplied with the control signal AVM 7 B, respectively. One electrode of a PMOS P 76  is electrically connected to the node N 14 , the other electrode thereof is electrically connected to the ground potential GND, and a gate electrode thereof is supplied with the control signal AVM 7 B, respectively. The ratio between ON resistances of the PMOSs P 75  and P 76  is set to a ratio different from the ratio between ON resistances of the PMOSs P 05  and P 06 .  
         [0078]    The operation of the seventh embodiment of the present invention will be described using FIG. 8 from only a phase at operation mode switching different from the fifth embodiment.  
         [0079]    When the signal AVM 70  is “L”, the PMOSs P 05  and P 06  in the divider circuit  161  are operated and the PMOSs P 75  and P 76  are not operated. Thus, the operation of the seventh embodiment is completely the same as the operations described up to now, which is defined as a normal operation. Upon the normal operation, the step-down power-supply voltage is given as 1.5×Vf as described above.  
         [0080]    On the other hand, when the signal AVM 70  reaches “H”, the signal AVM 7 B results in “L”. Thus, the PMOSs P 05  and P 06  in the divider circuit  161  are turned OFF, and the PMSOs P 75  and P 76  thereof are turned ON. Accordingly, a division ratio determined by a division ratio setting element group of the PMOSs P 75  and P 76  is outputted to the node N 14 . When the ratio-between the ON resistances of the PMOSs P 75  and P 76  is set as 1:1, for example, the step-down power-supply voltage results in 2×Vf.  
         [0081]    According to the seventh embodiment of the present invention as described above, the step-down power-supply voltage can be selected according to the operation modes. According to the present embodiment, the step-down power-supply voltage is lowered in a low frequency operation mode, for example, and hence lower current consumption can also be realized.  
         [0082]    [0082]FIG. 9 is a circuit diagram showing an internal step-down power supply circuit according to an eighth embodiment of the present invention. Incidentally, the same components as those in FIG. 8 are respectively identified by the same reference numerals and the description thereof will therefore be omitted.  
         [0083]    The eighth embodiment is configured under the assumption that when it is desired to change a step-down power-supply voltage to an external power-supply voltage VDD upon testing, on-burn in voltage switching for screening an initial failure or defect, for example, is performed. The eighth embodiment is an example in which the divider circuit  161  according to the seventh embodiment is modified to provide a divider circuit  162 . Since others are identical to FIG. 8 except for the divider circuit  162 , the configuration of the divider circuit  162  will be explained.  
         [0084]    A signal TST 80  is a control signal for switching the step-down power-supply voltage to an external power-supply voltage VD. The signal TST 80  is “L” upon a normal operation and “H” upon testing.  
         [0085]    In the divider circuit  162 , one electrode of an NMOS N 88  is electrically connected to a node N 14 , the other electrode thereof is electrically connected to a ground potential GND, and a gate electrode thereof is supplied with the control signal TST 80 , respectively.  
         [0086]    The operation of the eighth embodiment of the present invention will be explained using FIG. 9 from only a viewpoint at test mode switching different from the seventh embodiment.  
         [0087]    When the signal TST 80  is “L”, the operation of the eighth embodiment is identical to the operations described up to the seventh embodiment. Upon the normal operation as described above, the step-down power-supply voltage is a voltage such as 1.5×Vf or 2×Vf, which is determined by a selected division ratio setting element group.  
         [0088]    When the operation enters a test mode, the signal TST 80  is rendered “H”. Thus, the NMOS N 88  of the divider circuit  162  is turned ON. If an ON resistance of the NMOS N 88  is set to a magnitude negligible with respect to an ON resistance of the division ratio setting element group, then the node N 14  is brought to the ground potential GND. Since an NMOS N 11  and PMOSs P 10  and P 11  are held OFF and NMOSs N 10  and N 22  are held ON in this case, the gate of a PMOS P 04  is also supplied with the ground potential GND, and the step-down power-supply voltage is electrically connected to the external power-supply voltage VDD by the PMOS P 04  at low impedance.  
         [0089]    According to the eighth embodiment of the present invention as described above, since the step-down power-supply voltage can easily be switched to the external power-supply voltage VDD by using the test mode, the external power-supply voltage VDD can easily be supplied as the step-down power-supply voltage by only the addition of one signal and the addition of one transistor to the divider circuit. Further, since the external power-supply voltage VDD and a step-down power-supply voltage output node are connected at low impedance, the external power-supply voltage VDD can reliably be supplied.  
         [0090]    [0090]FIG. 10 is a circuit diagram showing an internal step-down power supply circuit according to a ninth embodiment of the present invention. The present embodiment is provided as an embodiment which takes into consideration where it is desired to obtain a relatively high voltage as a step-down power-supply voltage and wherein the reference voltage Vf is taken as the gate voltage of the PMOS with the fourth embodiment as the base. Thus, only a configuration of a different amplifier  107  modified from FIG. 9 and a divider circuit  163  will be described. As to a control signal, another signal name is given to each of signals identical in purpose but different in state from the relationship in which gate control of NMOS is changed to gate control of PMOS. An inverter INV 9  is “H” upon standby, and receives therein a signal VBA 0 B indicative of “L” upon activation and outputs a phase-inverted signal VBA 00  thereof. A signal VBA 9 B is a signal which is responsive to the transition of the signal VBA 0 B from “L” to “H” upon transition from an active state to a standby state and which is brought to “H” with a delay equivalent to a time at which a circuit connected to the step-down power-supply voltage is completely brought into non-activation. When this is taken in reverse, no delay occurs. The signal VBS 90  has a constant voltage in the neighborhood of VDD−Vtp (threshold value of PMOS) at all times.  
         [0091]    In the differential amplifier  107 , one electrode of a PMOS P 93  is electrically connected to an external source or power supply VDD, the other electrode thereof is electrically connected to a node N 96 , and a gate electrode thereof is supplied with the signal VBA 9 B, respectively. One electrode of a PMOS P 92  is electrically connected to the external power supply VDD, the other electrode thereof is electrically connected to the node N 96 , and a gate electrode thereof is supplied with a signal VBS 90 , respectively. One electrode of a PMOS P 94  is electrically connected to the external power supply VDD, the other electrode thereof is electrically connected to a node N 97 , and a gate electrode thereof is supplied with the signal VBA 9 B, respectively. One electrode of a PMOS P 95  is electrically connected to the external power supply VDD, the other electrode thereof is electrically connected to the node N 97 , and a gate electrode thereof is supplied with the signal VBS 90 , respectively. One electrode of a PMOS P 96  is electrically connected to the external power supply VDD, the other electrode thereof is electrically connected to the node N 97 , and a gate electrode thereof is supplied with the signal VBA 00 , respectively. One electrode of a PMOS P 90  is electrically connected to the node N 96 , the other electrode thereof is electrically connected to a node N 92 , and a gate electrode thereof is electrically connected to a node N 01  (reference voltage Vf), respectively. One electrode of a PMOS P 91  is electrically connected to the node N 97 , the other electrode thereof is electrically connected to a node N 93 , and a gate electrode thereof is electrically connected to a node N 14  (internal step-down power-supply output node), respectively. One electrode of an NMOS N 90  is electrically connected to the node,N 92 , the other electrode thereof is electrically connected to a ground potential GND, and a gate electrode thereof is electrically connected to the node N 93 , respectively. One electrode of an NMOS N 91  is electrically connected to the node N 93 , the other electrode thereof is electrically connected to the ground potential GND, and a gate electrode thereof is electrically connected to the node N 93 , respectively. A stabilizing capacitor C 90  is electrically connected between the external power supply VDD and the node N 97 .  
         [0092]    In the divider circuit  163 , one electrode of the PMOS P 95  is electrically connected to a node N 15 , and the other electrode thereof and a gate electrode thereof are electrically connected to the node N 14 . One electrode of a PMOS P 06  is electrically connected to the node N 14 , and the other electrode thereof and a gate electrode thereof are electrically connected to the ground potential GND.  
         [0093]    Since the embodiment shown in FIG. 10 is perfectly identical in operation to the fourth embodiment, the description thereof will be omitted.  
         [0094]    The diode-connection of the PMOS P 95  in the divider circuit  163  means that the potential at the node N 14  is reliably set to VDD−Vtp or less, an the differential amplifier  107  is guaranteed in operation within a wide VDD voltage range.  
         [0095]    According to the ninth embodiment of the present invention as described above, since the voltages inputted to both the nodes N 01  and N 14  are received at the PMOS gates, a relatively high voltage can be supplied as the step-down power-supply voltage.  
         [0096]    The capacitors used through the first through ninth embodiments may be implemented using any of MOS capacitors for NMOS, PMOS, etc., a Poly-Poly capacitor, etc. While the transistors have been described with MOS as an example, a circuit may comprise bipolar transistors.  
         [0097]    Except for the description in the embodiments, no particular restriction is imposed on a delay time of a delay circuit.  
         [0098]    The method of generating the control signal for the differential amplifier, and producing the divider circuit is not limited to one described in the embodiments either. While PMOSs have been used as the resistive elements in the embodiments, resistive elements each formed of a diffused layer or Poly, for example, may be used. While the load MOS for the differential amplifier makes use of PMOS, any one may be used if means for implementing a constant current, for example, is utilized.  
         [0099]    While the equalize transistor makes use of NMOS or PMOS, PMOS or NMOS may be used singly or PMOS and NMOS may be utilized in combination.  
         [0100]    Finally, while the signal VBS 00  has the predetermined low voltage, the external power-supply voltage VDD may be used.  
         [0101]    According to the invention of the present application as described above in details, the drive capability of a driver can be enhanced with the same current consumption and exclusively-possessed area, it is possible to lighten a reduction in the potential of an internal power-supply voltage due to an instantaneous current of a internal power-supply voltage slave circuit.  
         [0102]    While the present invention has been described with reference to the illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art on reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.