Abstract:
A circuit exhibiting rectification and amplification characteristics. In particular, a full-wave rectifier, wherein the rectifier has the ability to simultaneously amplify and rectify an input voltage. The circuit comprises transconductor circuit, rectifying circuit and amplifying circuit. The transconductor circuit is adapted for receiving an input voltage from at least one voltage source. The input voltage is then converted into intermediate currents by the transconductor circuit. Thereafter, the rectifying circuit rectifies the intermediate currents current to produce a rectified current. Lastly, the amplification circuit amplifies the input voltage to produce the amplified voltage.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims priority from the U.S. provisional application No. 61/452,049 titled: “RECTIFICATION AND AMPLIFICATION CIRCUITRY” filed Mar. 11, 2011 the disclosure of which is hereby incorporated by reference. 
     TECHNICAL FIELD 
     The present disclosure relates, in general, to electronic circuits or components. More specifically, the present disclosure relates to a rectification and amplification circuit. 
     BACKGROUND 
     Electronic components/circuits are very important as the functioning of consumer electronics, industrial and household appliances depend on them. Various examples of electronic components are rectifiers, battery chargers, inverters, uni-directional or bi-directional converters, diodes, transistors, clippers, dampers, etc. Of these, rectifiers are widely used in the electronics industry and find a huge number of applications in our day-to-day life. The applications include deriving Direct Current (DC) power from an Alternating Current (AC) supply, power supplies, and detecting amplitude modulated radio signals. 
     Rectifiers are electronic components used for converting an Alternating Current (AC) into a Direct Current (DC). Rectifiers take the current that flows alternately in both directions and modifies it so that the output current flows only in one direction. The process of conversion of AC to DC is termed as rectification. Rectifiers are broadly classified as half-wave rectifier and full-wave rectifier. 
     In a half-wave rectifier, only one half of an AC wave, i.e. either the positive or the negative half is allowed to pass, while the other half is eliminated. The output of a half-wave rectifier can be achieved with a single diode connected in between a power supply and a load resistance or load reactance. 
       FIG. 1  shows a conventional half-wave rectifier circuit  100 .  FIG. 1  is shown to include an AC power supply  102 , a diode  104 , and a load  106 . AC power supply  102  is connected to diode  104 . Diode  104  is further connected to load  106 , generating an output waveform. Load  106  can be a resistive load or a reactive load. Diode  104  is forward-biased and reverse-biased alternatively during every cycle of the AC wave. Further, diode  104  only passes one half of the AC wave during the forward-biased condition and blocks the other half of the AC wave during the reverse-biased condition. The output waveform at load  106  thus has a DC component. 
     Similar to the half-wave rectifier, a full-wave rectifier also produces DC output; however, it consists of two or more diodes connected to a single load resistance or reactance. Each diode supplies current to the load, in isolation from the other diode. Also, at least one of the diodes is always active during either the positive or negative cycle of an input AC wave. Therefore, the full-wave rectifier converts both polarities of the input AC wave to DC. Full-wave rectifiers are more efficient as compared to the half-wave rectifiers and have some fundamental advantages over the half-wave rectifiers. The output of a full-wave rectifier has much less ripple than the output of a half-wave rectifier and thus, produces a smoother output waveform. 
     Rectifiers are also commonly used as received signal strength indicators (RSSI). As the name suggests, RSSIs are used to measure the strength of an incoming signal. In general, a signal strength indicator circuit receives an input RF signal and produces an output, which is equivalent to the strength of the input signal. If the output voltage is high, then the signal strength is also high and vice-versa. An RSSI is commonly used in Automatic Gain Control (AGC) loops. Depending on the received signal power, the signal is amplified using an amplifier to boost the signal if it is too low or attenuated using an attenuator if it is too high. There are a number of consumer devices with inbuilt RSSI circuits, such as cell phones, wireless network adapters, and remote controls. Moreover, antennas contain RSSI circuits that help in aligning the antenna for maximum signal reception. 
     A number of Complementary metal-oxide-semiconductor (CMOS) solutions are available in the market that utilizes rectification techniques employed in RSSI implementations. However, such solutions require a lot of additions and subtractions to the current during the rectification process, which in turn requires very precise mathematics to be implemented. High precision further requires use of a long/large gate length to be utilized in such solutions. Typically, the gate length means the channel/region length representing the movement of the electrons and/or holes between two terminals formed inside the devices, for example, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Typically, a MOSFET is employed in electronic circuits for the purpose of amplifying or switching electronic signals. Large gate length leads to large gate area, resulting in large capacitance, which in turn leads to poor frequency response. If the existing circuit designs have a small gate length; it becomes very difficult to achieve such precision, due to large variations in device characteristics in the process for minimal gate length devices. There are RSSI implementations for devices having a large gate length, thereby providing good matching of characteristics of various components in the circuit. However, such designs fail to work at very high frequencies. These designs perform badly as they can operate only at a limited frequency range. 
     In view of the aforesaid challenges, there exists a need for a circuit design that operates in a broad frequency spectrum and achieves a large dynamic range with the circuit exhibiting rectification as well as amplification characteristics. Moreover, the circuit design should be simple and the circuit should employ minimum gate length. 
     SUMMARY 
     An objective of the present disclosure is to provide a rectification and amplification circuit that achieves broadband frequency response by utilizing the minimum gate length available in given process. 
     Yet another objective of the present disclosure is to convert a differential voltage into a rectified current. 
     Further, another objective of the present disclosure is to provide a rectification and amplification circuit performing both rectification and amplification. 
     Another objective of the present disclosure is to amplify a differential voltage. 
     An additional objective of the present disclosure is to cascade a plurality of rectifier circuits to achieve a large dynamic rectification range. 
     Embodiments of the present disclosure provide a rectification and amplification circuit for generating a rectified current and an amplified voltage. The circuit comprises a first transconductor and a second transconductor. Further, the first transconductor and the second transconductor receive a first input voltage V in     —     a  and a second input voltage V in     —     b  respectively and convert a differential voltage between the first input voltage and the second input voltage to intermediate currents. The sum of intermediate currents has a magnitude of a tail current being provided by a first current source and a second current source connected to the first transconductor and the second transconductor respectively. A rectifying circuit converts the differential voltage (V in     —a   −V in     —     b ) into the intermediate currents and selectively sums the intermediate currents to obtain the rectified current. Further, an amplifying circuit amplifies the differential voltage (V in     —     a −V in     —     b ) to an amplified voltage, wherein the amplified voltage corresponds to the difference between a first output voltage and a second output voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various embodiments of the disclosure will, hereinafter, be described in conjunction with the appended drawings provided to illustrate and not to limit the disclosure, wherein like designations denote like elements, and in which: 
         FIG. 1  is a schematic circuit representation of a conventional half-wave rectifier; 
         FIG. 2  is an exemplary circuit diagram of a rectification and amplification circuit performing simultaneous rectification and amplification, in accordance with an embodiment of the disclosure; 
         FIG. 3  is an exemplary circuit diagram of a rectification and amplification circuit performing rectification, in accordance with an embodiment of the disclosure; 
         FIG. 4  is an exemplary circuit diagram of a rectification and amplification circuit performing amplification, in accordance with an embodiment of the disclosure; 
         FIG. 5  is an exemplary circuit illustrating cascaded multiple stages of a rectification and amplification circuit, in accordance with an embodiment of the disclosure; 
         FIG. 6  shows an exemplary graphical representation of the performance of a rectification and amplification circuit, in accordance with an embodiment of the disclosure; and 
         FIG. 7  is another exemplary graphical representation of the performance of a rectification and amplification circuit, in accordance with an embodiment of the disclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     This application describes a circuit operating as a full-wave rectifier as well as an amplifier. In particular, the present application is directed to a novel full-wave rectifier implementation, including the ability to simultaneously amplify and rectify the input voltage/current. The full-wave rectifier operates on broad frequency spectrum. 
     For the sake of simplicity and better understanding of the disclosure, the terminologies/devices, which will be used later to describe the figures, are explained herein with their corresponding meanings/definitions. 
     A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is generally employed in electronic circuits for the purpose of amplifying or switching electronic signals. The basic MOSFET include three terminals such as a gate, a source and a drain. The metal oxide-insulated gate electrode forms a conducting medium between the source and the drain. Further, the MOSFET may be of two types i.e. nMOSFET or pMOSFET depending on the type of medium i.e. n-type or p-type respectively. Typically, nMOSFETs are used for implementing N-type metal-oxide-semiconductor (NMOS) logic in various known logic gates and other digital circuits. Also, nMOSFETs have four modes of operation: cut-off (or sub-threshold), triode, saturation (sometimes called active), and velocity saturation. Similarly, pMOSFETs are used for implementing P-type metal-oxide-semiconductor (PMOS) logic in various known logic gates and other digital circuits. Similar to the NMOS, pMOSFETs have four modes of operation: cut-off (or sub-threshold), triode, saturation (sometimes called active), and velocity saturation. As described above, nMOSFETs and pMOSFETs may be termed as NMOS transistors and PMOS transistors respectively. 
     Electrical resistance is the characteristic of an electrical element, which relates to the opposition of electric current flowing through the electrical element. The electrical elements made specifically for the purpose of providing opposition to the electric current in an electrical circuit are known as resistors. The resistors are made by keeping in mind various factors such as desired resistance, amount of energy that it needs to dissipate, precision, cost and the like. 
     Transconductance is a property of the transconductors, which can be defined as the ratio of current change at an output port to voltage change at an input port. It is usually represented as g m . In case of MOSFET&#39;s, transconductance is defined as the ratio of change in drain/source current to change in gate/source voltage, provided the drain/source voltage is constant. 
     A current mirror represents a circuit that utilizes current of one of the active devices of a circuit, to control the current in another active device of the circuit. 
     Current sources refer to any type of appropriate sources which inputs the current to a circuit. 
       FIG. 2  illustrates an exemplary circuit diagram of a rectification and amplification circuit  200  performing simultaneous rectification and amplification, in accordance with an embodiment of the disclosure. It will be apparent to those skilled in the art that the system components described herein can be applied to any other embodiment of the present disclosure. 
       FIG. 2  includes an input portion  202  and an output portion  204 . Input portion  202  includes a seventh transistor  206 , an eighth transistor  208 , a first input voltage source  210 , a second input voltage source  212 , a first current source  214 , a second current source  216  and a source resistance  218 . Output portion  204  includes a first transistor  224 , a second transistor  220 , a third transistor  226 , a fourth transistor  222 , a fifth transistor  228 , a sixth transistor  230 , a load resistance  232 , a first output voltage terminal  234 , a second output voltage terminal  236  and an output current terminal  238 . 
     First current source  214  and second current source  216  may be implemented in multiple ways to produce a tail current referred to as I TAIL . First current source  214  and second current source  216  may have a large gate length and are further implemented to provide current of a pre-defined value to rectification and amplification circuit  200 . Further, first current source  214  and second current source  216  with a large gate length do not have a significant effect on the frequency response of rectification and amplification circuit  200 . 
     In accordance with an embodiment of the present disclosure, seventh transistor  206  and eighth transistor  208  are transconductors which are converting an incoming differential voltage to a current as an output. 
     In accordance with another embodiment of the present disclosure, first transistor  224 , second transistor  220 , third transistor  226 , fourth transistor  222 , fifth transistor  228 , sixth transistor  230 , seventh transistor  206 , and eighth transistor  208  are one or more of a Bipolar Junction Transistor (BJT), Heterojunction bipolar transistor (HBT), a Metal Semiconductor Field Effect Transistor (MESFET), a Junction gate Field Effect Transistor (JFET), a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and a Pseudomorphic High Electron Mobility Transistor (pHEMT). 
     In accordance with an embodiment of the present disclosure, first transistor  224 , second transistor  220 , third transistor  226 , fourth transistor  222 , fifth transistor  228  and sixth transistor  230  are complimentary to seventh transistor  206  and eighth transistor  208 . For example, if seventh transistor  206  and eighth transistor  208  are N-Channel Metal Oxide Semiconductor (NMOS) transistors, then first transistor  224 , second transistor  220 , third transistor  226 , fourth transistor  222 , fifth transistor  228  and sixth transistor  230  are P-Channel Metal Oxide Semiconductor (PMOS) transistors. 
     In accordance with an embodiment of the present disclosure, rectification and amplification circuit  200  may include CMOS components. The CMOS components may be of various CMOS technologies such as, but not limited to, 0.35 μm CMOS and 0.18 μm CMOS. Additionally, the circuit may be implemented using other advanced technologies to achieve better performance over frequency. First transistor  224 , second transistor  220 , third transistor  226 , fourth transistor  222 , fifth transistor  228 , and sixth transistor  230  are hereinafter referred to as PMOS 1   224 , PMOS 2   220 , PMOS 3   226 , PMOS 4   222 , PMOS 5   228 , and PMOS 6   230  respectively. Further, seventh transistor  206  and eighth transistor  208  are hereinafter referred to as NMOS 1   206  and NMOS 2   208  respectively. 
     In the rectification and amplification circuit  200  as shown in  FIG. 2 , source terminals of NMOS 1   206  and NMOS 2   208  are connected to first terminals of first current source  214  and second current source  216  respectively. Second terminals of first current source  214  and second current source  216  are connected to a ground. A gate terminal of NMOS 1   206  is connected to first input voltage source  210  and a gate terminal of NMOS 2   208  is connected to second input voltage source  212 . Bulk terminals of NMOS 1   206  and NMOS 2   208  are connected to the ground. Source resistance  218  is connected between the source terminals of NMOS 1   206  and NMOS 2   208 . Drain terminals of NMOS 1   206  and NMOS 2   208  are connected to drain terminals of PMOS 2   220  and PMOS 4   222  respectively. Bulk terminals and source terminals of PMOS 2   220  and PMOS 4   222  are connected to a supply voltage V DD . A gate terminal of PMOS 1   224  is connected to the drain terminal of PMOS 2   220 . The drain terminal of PMOS 2   220  is connected to the drain terminal of NMOS 1   206 . 
     Further, a drain terminal of PMOS 3   226  is connected to the drain terminal of PMOS 4   222 . The drain terminal of PMOS 4   222  is connected to the drain terminal of NMOS 2   208 . Bulk terminals and source terminals of PMOS 1   224  and PMOS 3   226  are connected to the supply voltage V DD . A gate terminal of PMOS 3   226  is connected to the drain terminal of PMOS 4   222 . PMOS 4   222  and PMOS 2   220  are cross coupled to each other. The gate terminal of PMOS 4   222  and the gate terminal of PMOS 2   220  are cross coupled with the drain terminal of PMOS 2   220  and the drain terminal of PMOS 4   222  respectively. Load resistance  232  is connected between the drain terminals of PMOS 2   220  and PMOS 4   222 . 
     Furthermore, gate terminals of PMOS 5   228  and PMOS 6   230  are connected to the gate terminals of PMOS 1   224  and PMOS 3   226  respectively. Bulk terminals and source terminals of PMOS 5   228  and PMOS 6   230  are connected to the supply voltage V DD . Drain terminals of PMOS 5   228  and PMOS 6   230  are connected to output current terminal  238 . 
     First output voltage terminal  234  is connected to the drain terminal of PMOS 2   220  and the drain terminal of NMOS 1   206 . Second output voltage terminal  236  is connected to the drain terminal of PMOS 4   222  and the drain terminal of NMOS 2   208 . 
     In an embodiment of the present disclosure, PMOS 1   224  and PMOS 3   226  are diode connected. In an embodiment of the present disclosure, PMOS 5   228  and PMOS 6   230  are implemented as current mirror for PMOS 1   224  and PMOS 3   226  respectively. Therefore, PMOS 5   228  and PMOS 6   230  copy the current flowing in PMOS 1   224  and PMOS 3   226  respectively. 
     In accordance with an embodiment, PMOS 1   224 , PMOS 2   220 , PMOS 3   226 , and PMOS 4   222  may be of equal size. In accordance with another embodiment of the present disclosure, the size of PMOS 1   224 , PMOS 2   220 , PMOS 3   226 , and PMOS 4   222  may vary, as per the design requirements. 
       FIG. 3  illustrates an exemplary circuit diagram of a rectification and amplification circuit  300  performing rectification, in accordance with an embodiment of the disclosure. Rectification and amplification circuit  300  includes the elements illustrated to be a part of rectification and amplification circuit  200  (refer to  FIG. 2 ) except for first output voltage terminal  234  and second output voltage terminal  236  which have been removed. Further, rectification and amplification circuit  300  has a component connection configuration identical to rectification and amplification circuit  200 . 
     In  FIG. 3 , the gate terminal of NMOS 1   206  receives a first input voltage V in     —     a  from first input voltage source  210  and the gate terminal of NMOS 2   208  receives a second input voltage V in     —     b  from second input voltage source  212 . A differential voltage V DIFF  is defined as a difference between the first input voltage V in     —     a  and the second input voltage V in     —     b , i.e., V DIFF =(V in     —     a −V in     —     b ). NMOS 1   206  and NMOS 2   208  convert the differential voltage into intermediate currents. The sum of the intermediate currents has a magnitude of the tail current I TAIL  provided by first current source  214  and second current source  216 . 
     Further, source resistance  218  is implemented to adjust the effective transconductance of a differential pair comprising of NMOS 1   206  and NMOS 2   208 . The value of source resistance  218  may be varied to control an output gain. Source resistance  218  controls a rectified current I OUT  and eventually the gain of rectification and amplification circuit  200 . 
     In accordance with an embodiment of the present disclosure when the differential voltage V DIFF =0, only the tail current I TAIL  flows in rectification and amplification circuit  300 . Further, equal voltage at NMOS 1   206  and NMOS 2   208  provides equal value of input gate to source voltage (i.e. V gs ) in each of PMOS 1   224 , PMOS 2   220 , PMOS 3   226 , and PMOS 4   222 . Consequently, the intermediate current flowing through each of PMOS 1   224 , PMOS 2   220 , PMOS 3   226 , and PMOS 4   222  is of similar value. Accordingly, the tail current I TAIL  coming from input portion  202  is equally divided between PMOS 1   224 , PMOS 2   220 , PMOS 3   226  and PMOS 4   222  and the same is represented by equation (1), as shown below. The equation depicts the mathematical representation of the said scenario. 
     
       
         
           
             
               
                 
                   
                     I 
                     
                       DSP 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   = 
                   
                     
                       I 
                       
                         DSP 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                     = 
                     
                       
                         I 
                         
                           DSP 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           3 
                         
                       
                       = 
                       
                         
                           I 
                           
                             DSP 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             4 
                           
                         
                         = 
                         
                           
                             I 
                             TAIL 
                           
                           4 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     where, I DSP1 , I DSP2 , I DSP3  and I DSP4  correspond to the intermediate currents flowing through PMOS 1   224 , PMOS 2   220 , PMOS 3   226 , and PMOS 4   222  respectively. 
     According to the equation (1) above, the intermediate currents flowing through PMOS 1   224  and PMOS 3   226  is of the value of I TAIL /4. Thereafter, the intermediate currents flowing through PMOS 1   224  and PMOS 3   226  are copied by PMOS 5   228  and PMOS 6   230 , respectively. As described above, PMOS 5   228  and PMOS 6   230  are implemented as a current mirror for PMOS 1   224  and PMOS 3   226  respectively. The intermediate currents flowing through PMOS 1   224  and PMOS 3   226  are mirrored by PMOS 5   228  and PMOS 6   230 , respectively. Further, the drain terminals of PMOS 5   228  and PMOS 6   230  are connected to output current terminal  238  and hence provide the rectified current I OUT . The rectified current I OUT  is the sum of intermediate currents flowing in PMOS 5   228  and PMOS 6   230  and the same is shown by following equation (2): 
     
       
         
           
             
               
                 
                   
                     I 
                     out 
                   
                   = 
                   
                     
                       
                         I 
                         
                           DSP 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           5 
                         
                       
                       + 
                       
                         I 
                         
                           DSP 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           6 
                         
                       
                     
                     = 
                     
                       
                         
                           
                             I 
                             TAIL 
                           
                           4 
                         
                         + 
                         
                           
                             I 
                             TAIL 
                           
                           4 
                         
                       
                       = 
                       
                         
                           
                             I 
                             TAIL 
                           
                           2 
                         
                         ⁢ 
                         
                           | 
                           
                             
                               V 
                               DIFF 
                             
                             = 
                             0 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     where, I DSP5  and I DSP6  correspond to the intermediate currents flowing through PMOS 5   228  and PMOS 6   230 , respectively. 
     In the above equation 2, the value of I OUT  is half of the tail current I TAIL . Therefore, when the differential voltage V DIFF  of value zero, i.e. V DIFF =0, is applied to the input terminal of output portion  204 , the rectified current I OUT  will be half of the value of the tail current I TAIL , as calculated by the equation (2). 
     In accordance with another embodiment of the present disclosure when the differential voltage V DIFF &gt;&gt;0, the entire tail current I TAIL  flows through NMOS 1   206  and no tail current I TAIL  flows through NMOS 2   208 . No tail current I TAIL  flows through PMOS 4   222  or PMOS 3   226  since they are connected to NMOS 2   208 , leading to drain voltage of PMOS 4   222  to be high. Since the gate terminal of PMOS 2   220  is connected to the drain terminal of PMOS 4   222 , PMOS 2   220  is turned off. Subsequently, the entire tail current I TAIL  flows through PMOS 1   224  since it is connected to NMOS 1   206 . 
     In the above scenario, the entire tail current I TAIL , supplied by the drain terminal of NMOS 1   206  flows through PMOS 1   224 , whose drain terminal is connected to the drain terminal of NMOS 1   206 . Therefore, the entire tail current I TAIL  flows through PMOS 1   224 , which is copied by PMOS 5   228  (while acting as a current mirror) and PMOS 5   228  provides the entire tail current I TAIL  as the rectified current I OUT  at output current terminal  238 . Hence, the rectified current I OUT  is equal to the current that flows through PMOS 1   224 , i.e. I TAIL =I OUT . This is represented by an equation (3) shown below: (3)
 
 I   OUT   =I   DSN1   =I   DSP1   =I   TAIL   (3)
 
     where, I DSP1  corresponds to the intermediate current flowing through PMOS 1   224  and I DSN1  corresponds to current flowing through NMOS 1   206 . 
     In accordance with another embodiment of the present disclosure when the differential voltage V DIFF &lt;&lt;0, the entire tail current I TAIL  flows through NMOS 2   208  and no tail current I TAIL  flows through NMOS 1   206 . Therefore, no tail current I TAIL  flows through PMOS 1   224  or PMOS 2   220  since their drain terminals are connected to NMOS 1   206 , leading to drain voltage of PMOS 2   220  to be high. Since the gate terminal of PMOS 4   222  is connected to the drain terminal of PMOS 2   220 , PMOS 4   222  is turned off. Subsequently, the entire tail current I TAIL  flows through PMOS 3   226  since it is connected to NMOS 2   208 . 
     In the above scenario, the entire tail current I TAIL , supplied by the drain terminal of NMOS 2   208  flows through PMOS 3   226 , whose drain terminal is connected to the drain terminal of NMOS 2   208 . Therefore, the entire tail current I TAIL  flows through PMOS 3   226 , which is copied by PMOS 6   230  (acting as a current mirror) and which provides the entire tail current I TAIL  as the rectified current I OUT  at output current terminal  238 . Hence, the rectified current I OUT  is equal to the current that flows through PMOS 3   226 , i.e. I TAIL =I OUT . This scenario is represented by an equation (4) below
 
 I   OUT   =I   DSN2   =I   DSP3   =I   TAIL   (4)
 
     where, I DSP3  corresponds to the intermediate current flowing through PMOS 3   226  and I DSN2  corresponds to current flowing through NMOS 2   208 . 
     In view of the above illustration of various working scenarios of the circuit shown in  FIG. 3 , it is apparent that the rectified current I OUT  is increasing monotonically with the value of differential voltage V DIFF , for example, I OUT  is minimum at V DIFF =0 and maximum at |V DIFF |&gt;&gt;0. Such, monotonically increasing characteristic of the rectified current I OUT  with respect to the magnitude of differential voltage V DIFF  establishes the rectification nature of rectification and amplification circuit  300 , hence the circuit shown in  FIG. 3  can be said to perform rectification. 
       FIG. 4  illustrates an exemplary circuit diagram of a rectification and amplification circuit  400  performing amplification, in accordance with an embodiment of the disclosure. Rectification and amplification circuit  400  includes the elements illustrated to be a part of rectification and amplification circuit  200  (refer to  FIG. 2 ) except for PMOS 5   228 , PMOS 6   230 , and output current terminal  238  which have been removed. Further, rectification and amplification circuit  400  has a component connection configuration identical to rectification and amplification circuit  200 . It will be apparent to those skilled in the art that the system components described herein can be applied to any other embodiment of the present disclosure. 
     The working of the circuit shown in  FIG. 4  is explained in conjunction with  FIG. 3 . Since rectification and amplification circuit  400  performs amplification, the output of the circuit is measured from first output voltage terminal  234  and second output voltage terminal  236 . First output voltage terminal  234  provides a first output voltage V out     —     a  and second output voltage terminal  236  provides a second output voltage V out     —     b . Further, an amplified voltage V out  will be a differential output voltage, which is the difference between the first output voltage V out     —     a  and the second output voltage V out     —     b , i.e. V out =V out     —     a −V out     —     b . 
     In accordance with an embodiment of the present disclosure, the circuit shown in  FIG. 4  is a fully balanced circuit. The term balanced circuit is well known to a person of ordinary skill in the art and is therefore not explained in detail for sake of brevity. 
     In accordance with an embodiment of the present disclosure, amplification of a differential voltage is performed by the circuit shown in  FIG. 4  and it has a gain of value higher than unity. Such amplification process performed by rectification and amplification circuit  400  may be described by using half-circuit analogy, since the circuit is fully balanced. 
     The NMOS transistors (i.e. NMOS 1   206  and NMOS 2   208 ) have reasonably high impedance looking into the drain in common source configuration. On the other hand, the impedance of diode-connected PMOS transistors, i.e. PMOS 1   224  and PMOS 3   226 , is low and equal to 1/gm in parallel with ro. Also, since PMOS 2   220  and PMOS 4   222  are cross-coupled, PMOS 2   220  has input impedance equal to −1/gm in parallel with ro. This −1/gm output impedance of PMOS 2   220  cancels the 1/gm output impedance of PMOS 1   224 . Therefore, the impedance at first output voltage terminal  234  is of reasonably high value and equal to ro/2. Further, load resistance  232  may be used to control the gain in conjunction with effective transconductance formed by NMOS 1   206 , NMOS 2   208  and source resistance  218 . 
     Output impedance, R out , at first output voltage terminal  234  may be calculated by the following equation (5): 
     
       
         
           
             
               
                 
                   Rout 
                   = 
                   
                     
                       1 
                       
                         
                           1 
                           
                             ro 
                             
                               p 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                           
                         
                         + 
                         
                           gm 
                           
                             p 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                         + 
                         
                           1 
                           
                             ro 
                             
                               p 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                           
                         
                         - 
                         
                           gm 
                           
                             p 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                       
                     
                     ⁢ 
                     
                        
                       
                         ro 
                         
                           n 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                        
                     
                     ⁢ 
                     
                       
                         R 
                         L 
                       
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     Assuming that gm p1 =gm p2 =gm p , ro p1 =ro p2 =ro p    
     Where, 
     gm is defined as Device Transconductance 
     
       
         
           
             gm 
             = 
             
               
                 
                   ⅆ 
                   
                     I 
                     ds 
                   
                 
                 
                   ⅆ 
                   
                     V 
                     gs 
                   
                 
               
               ⁡ 
               
                 [ 
                 
                   Ω 
                   
                     - 
                     1 
                   
                 
                 ] 
               
             
           
         
       
     
     r o  is defined as Device Output Impedance 
     
       
         
           
             ro 
             = 
             
               
                 
                   ⅆ 
                   
                     I 
                     ds 
                   
                 
                 
                   ⅆ 
                   
                     V 
                     ds 
                   
                 
               
               ⁡ 
               
                 [ 
                 Ω 
                 ] 
               
             
           
         
       
     
     
       
         
           
             
               
                 
                   Rout 
                   = 
                   
                     
                       
                         ro 
                         p 
                       
                       2 
                     
                     ⁢ 
                     
                        
                       
                         ro 
                         
                           n 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                        
                     
                     ⁢ 
                     
                       
                         R 
                         L 
                       
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     If R L  is chosen such that 
                     ro   p     2          ⁢     ro     n   ⁢           ⁢   1         &gt;&gt;       R   L     2           
then
 
 R out= R   L /2  (6)
 
     Then the total gain is: 
     
       
         
           
             
               
                 
                   Av 
                   = 
                   
                     
                       Gm 
                       · 
                       Rout 
                     
                     = 
                     
                       
                         
                           gm 
                           n 
                         
                         
                           1 
                           + 
                           
                             
                               gm 
                               n 
                             
                             · 
                             
                               
                                 R 
                                 s 
                               
                               2 
                             
                           
                         
                       
                       · 
                       
                         
                           R 
                           L 
                         
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
     The equation (7) could be further simplified assuming that 
     
       
         
           
             1 
             ⁢ 
             
               
                 &lt;&lt; 
                 
                   gm 
                   n 
                 
               
               · 
               
                 
                   R 
                   S 
                 
                 2 
               
             
           
         
       
     
     
       
         
           
             
               
                 
                   Av 
                   = 
                   
                     
                       Gm 
                       · 
                       Rout 
                     
                     = 
                     
                       
                         R 
                         L 
                       
                       
                         R 
                         S 
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
     A more general equation is given below (8a) 
     
       
         
           
             
               
                 
                   Av 
                   = 
                   
                     
                       Gm 
                       · 
                       Rout 
                     
                     = 
                     
                       
                         
                           gm 
                           n 
                         
                         
                           1 
                           + 
                           
                             
                               gm 
                               n 
                             
                             · 
                             
                               
                                 R 
                                 S 
                               
                               2 
                             
                           
                         
                       
                       · 
                       
                         [ 
                         
                           
                             1 
                             
                               
                                 1 
                                 
                                   ro 
                                   
                                     p 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     1 
                                   
                                 
                               
                               + 
                               
                                 gm 
                                 
                                   p 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                 
                               
                               + 
                               
                                 1 
                                 
                                   ro 
                                   
                                     p 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     2 
                                   
                                 
                               
                               - 
                               
                                 gm 
                                 
                                   p 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   2 
                                 
                               
                             
                           
                           ⁢ 
                           
                              
                             
                               ro 
                               
                                 n 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                             
                              
                           
                           ⁢ 
                           
                             
                               R 
                               L 
                             
                             2 
                           
                         
                         ] 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     8 
                     ⁢ 
                     a 
                   
                   ) 
                 
               
             
           
         
       
     
     Since the voltage gain of rectification and amplification circuit  400  is reasonably high, i.e. greater than unity, it means that rectification and amplification circuit  400  shown in  FIG. 4  performs amplification. 
     In accordance with an embodiment of the present disclosure, a detection range of rectification and amplification circuit  200  as shown in  FIG. 2  may be calculated in the following manner:
 
 I   OUT   =I   DSP5   +I   DSP6  
 
     Assuming perfect mirroring of current by PMOS 5   228  and PMOS 6   230 , we can rewrite the above equation as follows:
 
 I   OUT   =I   DSP1   +I   DSP3  
 
     For V DIFF &gt;0 and assuming that gm p1 =gm p3 =gm p    
     
       
         
           
             
               
                 
                   
                     I 
                     
                       DSP 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   = 
                   
                     
                       
                         I 
                         TAIL 
                       
                       4 
                     
                     - 
                     
                       
                         
                           V 
                           DIFF 
                         
                         2 
                       
                       · 
                       Av 
                       · 
                       
                         gm 
                         p 
                       
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
     
       
         
           
             
               
                 
                   
                     I 
                     
                       DSP 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                   
                   = 
                   
                     
                       
                         I 
                         TAIL 
                       
                       4 
                     
                     + 
                     
                       
                         
                           V 
                           DIFF 
                         
                         2 
                       
                       · 
                       Av 
                       · 
                       
                         gm 
                         p 
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
     As long as 
                 V   DIFF     &lt;       I   TAIL       2   ·   Av   ·     gm   p           ,         
the rectified current I OUT  remains the same. Since the minimum value for each branch, I DSP1  and I DSP2 , is zero, we can obtain a minimum value for the differential input voltage, using the following equation (11), beyond which rectification and amplification circuit  400  begins to rectify:
 
     
       
         
           
             
               
                 
                   
                     V 
                     MIN 
                   
                   = 
                   
                     
                       I 
                       TAIL 
                     
                     
                       2 
                       · 
                       Av 
                       · 
                       
                         gm 
                         p 
                       
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
     Furthermore, rectification and amplification circuit  400  will run out of range when 
                   3   ·     I   TAIL       4     =         V   DIFF     2     ·   Av   ·     gm   p         ,         
leads to
 
     
       
         
           
             
               
                 
                   
                     V 
                     MAX 
                   
                   = 
                   
                     
                       
                         3 
                         · 
                         
                           I 
                           TAIL 
                         
                       
                       
                         2 
                         · 
                         Av 
                         · 
                         
                           gm 
                           p 
                         
                       
                     
                     = 
                     
                       
                         V 
                         MIN 
                       
                       + 
                       
                         
                           I 
                           TAIL 
                         
                         
                           Av 
                           · 
                           
                             gm 
                             p 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
     Moreover, the minimum and maximum value of the first input voltage V in     —     a  and the second input voltage V in     —     b  for the circuit shown in  FIG. 2  is given by equations (11) and (12). 
     In accordance with an embodiment of the present disclosure, rectification and amplification circuit  200  shown in  FIG. 2  performs the operation of a rectifier as shown in  FIG. 3 , and also performs the operation of an amplifier as shown in  FIG. 4 . This unique feature of the circuit may be utilized to produce a large dynamic range rectifier, if we replicate rectification and amplification circuit  200  several times. 
       FIG. 5  represents an exemplary circuit illustrating a multi-stage rectification and amplification circuit  500 , in accordance with an embodiment of the present disclosure. The  FIG. 5  is explained in conjunction with  FIG. 2 ,  FIG. 3  and  FIG. 4 . It will be apparent to those skilled in the art that the system components described herein can be applied to any other embodiment of the present disclosure. 
     The circuit shown in  FIG. 5  includes a plurality of stages of rectification and amplification circuits. Each stage respectively includes rectification and amplification circuits  502   a ,  502   b  and  502   n  and respective current sources  506   a ,  506   b , and  506   n.    
     Each of rectification and amplification circuits  502   a ,  502   b  and  502   n  corresponds to rectification and amplification circuit  200 . The rectification and amplification circuit of a first stage is connected to a common differential voltage source  504 , providing differential input voltage V DIFF . The first output voltage terminal and the second output voltage terminal of the rectification and amplification circuit of the each stage are connected to a subsequent stage and respectively provide the first input voltage V in     —     a  and the second input voltage V in     —     b  to the rectification and amplification circuit of the subsequent stage. The rectified currents I OUT     —     a , I OUT     —     b  and I OUT     —     n  of each stage of cascaded multiple stage rectification and amplification circuit  500  is aggregated to provide a total rectified current I OUT     —     Total . Further, tail currents I TAIL     —     1 , I TAIL     —     2 , and I TAIL     —     n  of current sources  506   a ,  506   b , and  506   n  respectively are connected to the ground. In accordance with an embodiment of the present disclosure, the functioning of each of the plurality of circuits  300  has been described earlier in the document, in detail, in conjunction with  FIG. 3  (i.e. for performing rectification) and  FIG. 4  (i.e. for performing amplification) 
     Further, in the circuit shown in  FIG. 5 , the gain and rectification range of each stage of rectification and amplification circuit  500  should be set in such a way that if one of the stages goes out of range, then the other stages perform the operation of rectification. 
     In accordance with an exemplary embodiment of the present disclosure, the implementation of the circuit in  FIG. 5  may be realized by utilizing, but not limited to, 0.35 μm CMOS technology. In such an implementation, three circuits are cascaded, wherein each circuit (stage) has been provided with a similar gain and rectification range. The value of other variables is as follows: 
     gm n =13.5 mA/V 
     ro n =3.3 kΩ 
     ro p =6.7 kΩ 
     Rs=100Ω 
     RL=2.5 kΩ 
     Now, the total gain of the above mentioned circuit may be computed by the following equation (13): 
     
       
         
           
             
               
                 
                   Av 
                   = 
                   
                     
                       Gm 
                       · 
                       Rout 
                     
                     = 
                     
                       
                         
                           gm 
                           n 
                         
                         
                           1 
                           + 
                           
                             
                               gm 
                               n 
                             
                             · 
                             
                               
                                 R 
                                 S 
                               
                               2 
                             
                           
                         
                       
                       · 
                       
                         [ 
                         
                           
                             1 
                             
                               
                                 1 
                                 
                                   ro 
                                   
                                     p 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     1 
                                   
                                 
                               
                               + 
                               
                                 gm 
                                 
                                   p 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                 
                               
                               + 
                               
                                 1 
                                 
                                   ro 
                                   
                                     p 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     2 
                                   
                                 
                               
                               - 
                               
                                 gm 
                                 
                                   p 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   2 
                                 
                               
                             
                           
                           ⁢ 
                           
                              
                             
                               ro 
                               
                                 n 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                             
                              
                           
                           ⁢ 
                           
                             
                               R 
                               L 
                             
                             2 
                           
                         
                         ] 
                       
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
     If we incorporate the above mentioned values in equation (13), the value of total gain is obtained, as shown below 
     A v =6.5 [V/V]. 
     In order to obtain a higher dynamic frequency range, more stages may be combined. 
       FIG. 6  shows an exemplary graphical representation of the performance of a rectification and amplification circuit  200 , in accordance with an embodiment of the present disclosure.  FIG. 6  depicts a graph  600  showing the relationship between amplitude and rectified current I OUT  of each stage used (three stages totals) in the cascade of amplification rectification circuits as depicted in  FIG. 5 . The graph is shown in terms of linear curves representing the performance of rectification and amplification circuit  200 . As shown in the  FIG. 6 , each of the linear curves are separated by a gain of 6.5 [v/v], hence a similar value of gain for each of rectification and amplification circuit  200  is obtained when calculated by the equation (13) discussed above. 
       FIG. 7  is another exemplary graphical representation of the performance of a rectification and amplification circuit  200 , in accordance with an embodiment of the present disclosure. The performance of rectification and amplification circuit  200 , as demonstrated in  FIG. 5 , is shown in terms of graphical analysis  700 . Graphical analysis  700  demonstrates a relation between the amplitude and rectified current I OUT  current that is shown using a linear curve. 
     Most high-precision current mode rectifiers implemented in CMOS technology primarily depend on the mathematics of the circuit, i.e., addition and subtraction of currents. As a result, these designs need to be implemented with great precision. Precise current mirrors require large gate length components which, in turn, degrade the frequency response of the circuit. 
     However, the design described above in the present disclosure does not rely very much on a precision current mirror implementation. If we refer to equations (2) and (4), shown below for convenience, the rectified current depends mostly on I TAIL , which does not have much of an effect on the bandwidth. 
     
       
         
           
             
               I 
               OUT 
             
             = 
             
               
                 
                   I 
                   
                     DSP 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     5 
                   
                 
                 + 
                 
                   I 
                   
                     DSP 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     6 
                   
                 
               
               = 
               
                 
                   
                     
                       I 
                       TAIL 
                     
                     4 
                   
                   + 
                   
                     
                       I 
                       TAIL 
                     
                     4 
                   
                 
                 = 
                 
                   
                     
                       
                         I 
                         TAIL 
                       
                       2 
                     
                     ⁢ 
                     
                       | 
                       
                         
                           V 
                           DIFF 
                         
                         = 
                         0 
                       
                     
                     ⁢ 
                     
                       
 
                     
                     ⁢ 
                     
                       I 
                       OUT 
                     
                   
                   = 
                   
                     
                       I 
                       
                         DSN 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                     = 
                     
                       
                         I 
                         
                           DSP 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           4 
                         
                       
                       = 
                       
                         
                           I 
                           TAIL 
                         
                         ⁢ 
                         
                           | 
                           
                             
                               V 
                               DIFF 
                             
                             &gt;&gt; 
                             0 
                           
                         
                       
                     
                   
                 
               
             
           
         
       
     
     The above description is made assuming that first transistor  224 , second transistor  220 , third transistor  226 , fourth transistor  222 , fifth transistor  228 , and sixth transistor  230  are PMOS transistors, and seventh transistor  206 , and eighth transistor  208  are NMOS transistors. However, those of ordinary skill in the art will appreciate that the same circuit can work without change of any scope when first transistor  224 , PMOS 2   220 , third transistor  226 , fourth transistor  222 , PMOS 5   228  and PMOS 6   230  are transistors other than the PMOS transistor. Similarly, NMOS 1   206  and NMOS 2   208  can be any other transistor, different from the NMOS transistor but still complementary to first transistor  224 , PMOS 2   220 , third transistor  226 , fourth transistor  222 , PMOS 5   228  and PMOS 6   230 . 
     A circuit exhibiting rectification and amplification characteristics, or any of its components, as described in the present disclosure, may be embodied in the form of devices like, but not limited to, power control loop devices. For another embodiment, the components of the present disclosure may be embodied in the form of an embedded controller. Typical examples of embedded controllers include a general-purpose computer, a programmable microprocessor, a micro controller, a peripheral integrated circuit element, ASIC&#39;s (Application Specific Integrated Circuit), PLC&#39;s (Programmable Logic Controller), devices and other devices or arrangements of devices that are capable of implementing the steps that constitute the method for the present disclosure. In addition to this, the amplification and rectification circuit can also be implemented using any three terminal device, but are not limited to, a Bipolar Junction Transistor (BJT), a Metal Semiconductor Field Effect Transistor (MESFET), a Junction gate field-effect transistor (JFET) and a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). 
     While various embodiments of the disclosure have been illustrated and described, it will be clear that the disclosure is not limited only to these embodiments. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the disclosure.