Abstract:
Methods and apparatuses are provided for protecting an interconnect line in a microelectromechanical system. The interconnect line is disposed over a substrate for conducting electrical signals, such as from a bonding pad to a mechanical component to effect movement as desired of the mechanical component. A first protective covering is disposed over a first portion of the interconnect line and a second protective covering is disposed over a second portion of the interconnect line. The first protective covering is provided in electrical communication with the substrate and the second protective covering is electrically isolated from the substrate.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
   This application is related to commonly assigned U.S. patent application Ser. No. 10/216,600, entitled “METHOD AND APPARATUS FOR PROTECTING WIRING AND INTEGRATED CIRCUIT DEVICE,” filed Aug. 9, 2002 by Robert L. Anderson and David Reyes, the entire disclosure of which is incorporated herein by reference for all purposes. 
   BACKGROUND OF THE INVENTION 
   This application relates generally to microelectromechanical systems (“MEMS”). More specifically, this application relates to methods and systems for protecting interconnect structures in MEMS. 
   There are various known techniques for providing protective structures in the field of integrated circuits. For example, it is common to form an integrated-circuit structure through the deposition of various layers of materials and to complete the process by depositing a passivation layer over the resulting layered structure. Furthermore, the integrated circuits may also be capped with a plastic material to prevent their destruction. In the case of MEMS, protection of components is complicated by the existence of active mechanical components, which in some instances need to be exposed to the atmosphere for the device to operate as desired. In these applications, a passivation layer cannot be applied to the entire structure because it would interfere with the movement of the active mechanical components. 
   Thus, in MEMS packaging, conductors may sometimes be exposed to the atmosphere, permitting contamination by particulate matter that may interfere with the operation of the device. For example, a typical MEMS device includes a plurality of interconnect traces, with each trace being designed to connect to a single element of the device. The presence of contaminant debris between two (or more) traces may tie those traces together electrically so that they no longer connect to a single element. Even worse, the location of contaminant debris may electrically tie the trace to ground, resulting in a true electrical short circuit than renders the entire MEMS device nonfunctional. In some instances, the electrical short circuit may result in arcing, melting, or welding, causing destruction of the device. 
   Contaminant particles may arise from different sources. For example, they may occur as dirt particles that exist in the atmosphere in which the device is manufactured. Filtering techniques are used to limit the presence of dirt particles, but these techniques are imperfect. More typically, the manufacturing process itself results in fragments of silicon that are not completely removed during fabrication steps. This may occur, for example, during the removal of sacrificial material, resulting in contaminant “stringers.” Also, handling of the devices may induce chipping or fracturing at the edges of the material. 
   There is, therefore, a general need in the art for methods and systems to mitigate the damage caused to MEMS devices resulting from electrical interference by contaminant particles. 
   BRIEF SUMMARY OF THE INVENTION 
   Embodiments of the invention provide methods and apparatuses for protecting an interconnect line in a microelectromechanical system. The interconnect line is disposed over a substrate for conducting electrical signals, such as from a bonding pad to a mechanical component to effect movement as desired of the mechanical component. A first protective covering is disposed over a first portion of the interconnect line and a second protective covering is disposed over a second portion of the interconnect line. The first protective covering is provided in electrical communication with the substrate and the second protective covering is electrically isolated from the substrate. Suitable materials for the protective coverings include polysilicon. The electrical communication between the first protective covering and the substrate permits establishing an equipotential ring around the interconnect line. Since the second protective covering is not in electrical communication with the substrate, it has a floating electric potential and acts as an entrance guard for the interconnect shield. In some instances, the substrate may be in electrical communication with the bonding pad such that the equipotential ring comprises a ground ring. 
   In some embodiments, an electrically insulative barrier may also be included between the interconnect line and the substrate. Electrical communication between the first protective covering and the substrate may thus be achieved by including one or more openings in the barrier layer. 
   In other embodiments, a third protective covering may be disposed over a third portion of the interconnect line, with the third protective covering being electrically isolated from the substrate. Where the first protective covering is disposed between the second and third protective coverings, the second and third protective coverings function as floating entrance guards on either end of the equipotential portion of the interconnect shield. The effectiveness of these floating entrance guards may be improved by configuring them so that longitudinal end regions have smaller heights above the interconnect line than a central region. Gaps that exist between the first and second protective coverings or between the first and third protective coverings may be covered by a protective jacket. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings wherein like reference numerals are used throughout the several drawings to refer to similar components. In some instances, a sublabel is associated with a reference numeral and is enclosed in parentheses to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sublabel, it is intended to refer to all such multiple similar components. 
       FIG. 1A  is a cross-sectional view of a portion of an interconnect shield made in accordance with an embodiment of the invention; 
       FIG. 1B  is a cross-sectional view illustrating the effect of a contaminant particle present at a longitudinal end of the interconnect shield; 
       FIG. 2  is a top view of a portion of a MEMS device illustrating the use of an interconnect shield having an equipotential portion and a floating portion; 
       FIG. 3A  is a cross-sectional view of an equipotential portion of an interconnect shield in one embodiment; 
       FIG. 3B  is a cross-sectional view of a floating portion of an interconnect shield in one embodiment; 
       FIG. 4A  is a flow diagram illustrating a method for forming an equipotential portion of an interconnect shield in an embodiment; 
       FIG. 4B  is a flow diagram illustrating a method for forming a floating portion of an interconnect shield in an embodiment; 
       FIG. 5A  is a scanning electron micrograph of a floating portion of an interconnect shield in one embodiment; and 
       FIG. 5B  is a scanning electron micrograph of a jacket formed over a gap between equipotential and floating portions of an interconnect shield. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Embodiments of the invention use an interconnect shield to prevent contaminant particles from interfering with the electrical operation of the interconnect structure that it shields. The protection of the interconnect shield is enhanced in some embodiments by having the interconnect shield include a first portion maintained at a specific electric potential through the formation of an equipotential ring and a second portion whose electric potential is permitted to float. In some instances, the equipotential portion is also electrically coupled with a circuit ground, such as to a bonding pad that is coupled to the circuit ground, so that the equipotential ring corresponds to a ground ring. Grounding the equipotential portion has the advantage of generally reducing electrical attraction of contaminant particles to the interconnect shield. Reference to an “equipotential” ring is intended to mean that the electric potential is substantially constant throughout the ring. It is recognized that because of the resistive properties of some materials, the electric potential may have some negligible variation throughout the ring; such negligible variations introduced by the materials used are not considered to take such structures out of the definition of an equipotential ring, as would be understood by those of skill in the art. 
   In the following description of the structures used for the interconnect shield and for methods of forming the interconnect shield, reference is sometimes made to the relative positions of material layers, with one layer being identified as “over” another layer. Such references are not intended to require that the layers be adjacent, although they may be in some embodiments. In other embodiments, there may be additional intermediate layers separating the referenced layers. 
   The basic use of an interconnect shield is illustrated in  FIG. 1A , which shows an intermediate MEMS structure  100  prior to performing release. The MEMS structure is formed over a substrate  120 , which is typically made of silicon although the principles of the invention are effective for any electrically conductive material. Over the substrate is a barrier layer  104  that is formed of an electrically insulative material, such as an oxide and/or a nitride; in specific embodiments, the barrier layer  104  comprises SiN. The barrier layer  104  includes openings that permit the completion of an equipotential ring as described below. 
   The interconnect line  116  is provided over the barrier layer  104  and is formed with an electrically conductive material. A suitable material for the interconnect line  116  comprises polysilicon, although any electrically conductive material may alternatively be used, including metals. The general function of the interconnect line  116 , which runs perpendicularly to the page, is to conduct electrical signals within the MEMS device from a bonding pad on a chip to the input of an active mechanical component. At each of the openings within the barrier layer  104 , support stacks  128  are included to provide structural support for a protective covering  124  erected around the interconnect line  116 . Both the support stacks  128  and the protective covering  124  are formed of an electrically conductive material, such as polysilicon, and the material of the support stacks  128  fills the openings in the barrier layer  104  to contact the substrate  120 .  FIG. 1A  also shows the presence of insulating material  108  between the interconnect line  116  and protective covering  124 . Such insulating material  108  typically comprises sacrificial material used as part of a manufacturing process, described in greater detail below, and is usually removed during a subsequent release step; in other embodiments, however, it may by used to provide an insulative sheath around the interconnect line  116  that also provides additional structural support to the protective covering  124 . 
   The configuration of the structure shown in  FIG. 1A  results in the establishment of an equipotential ring  112 , shown as a ground ring. An equipotential circuit  112  around the interconnect line  116  is produced because there is contact between the conductive substrate  120 , the conductive support stacks  128 , and the conductive protective covering  124 . In addition to the structural protections provided by the interconnect shield, the equipotential ring  112  ensures that any contaminant particles that fall onto the protective covering  124  are exposed only to the reference equipotential. In addition, surrounding the interconnect line  116  with the equipotential ring  112  helps mitigate the effects that external electrical noise could otherwise have on the signal carried by the interconnect line  116 . 
   In those instances where the insulating material  108  is removed, there is a possibility at the longitudinal ends of the interconnect shield that a contaminant particle may become situated between the protective covering  124  and the interconnect line  116 , as shown in cross-section view in  FIG. 1B . In  FIG. 1B , the interconnect shield is denoted  100 ′ and differs from the interconnect shield  100  shown in  FIG. 1A  in that the insulting material  108  is not present, such as by having been removed with a release procedure. The presence of the contaminant particle  132  between the protective covering  124  and the interconnect line  116  may cause an electrical short if the contaminant particle is electrically conductive, as would be the case for a stringer resulting from a MEMS fabrication process. 
   According to embodiments of the invention, such electrical shorts at a longitudinal end of the interconnect shield are avoided by providing an entrance-guard portion to the interconnect shield that is electrically floating. Such an entrance-guard portion is provided at either or both longitudinal ends of the interconnect shield and is not restricted to a particular electrical potential, thereby avoiding a short circuit even when debris accumulates at the entrance guard region. The remainder of the interconnect line remains protected by the equipotential portion the interconnect shield. It is generally preferred that the longitudinal extent of the floating entrance-guard portions be small in comparison with the longitudinal extent of the equipotential portion to prevent the accumulation of a large capacitive charge. In addition to the specific embodiments described herein, a number of the structural and/or functional features described in Anderson may be adapted for use with the equipotential and/or floating portions of the interconnect shield. 
   A plan view is provided in  FIG. 2  of one configuration of an interconnect shield that includes both a floating entrance-guard portion  212  and an equipotential portion  208 . The term “interconnect shield” is used to refer to the floating and equipotential portions collectively, although these portions may be separated by a gap  218  as shown in  FIG. 2 . The floating and equipotential portions of the interconnect shield protect the interconnect line  216 , which is shown extending from a bond pad  204 . While  FIG. 2  shows only a single floating portion  212  at an end of the interconnect shield proximal to the bond pad  204 , there may be another floating portion at an end of the interconnect shield distal from the bond pad  204 , i.e. towards an active mechanical component of a MEMS device. Such a second floating portion may also be separated from the equipotential portion  208  by a gap. As illustrated by  FIG. 2 , it is not necessary that the interconnect shield extend along the entire length of the interconnect line  216  to achieve the benefits discussed herein. Rather, the interconnect shield may be configured to extend along a substantial portion of the of the interconnect line  216 , cover 50% or more, or even 70%, 90%, or 95% of the length of the interconnect line  216 . 
     FIGS. 3A and 3B  respectively show cross-sectional views of the equipotential portion  208  and floating portion  212  of the interconnect shield in one embodiment. Common to the two cross-sectional views are the substrate  320  over which the interconnect shield is formed and the interconnect line  216  that is protected. Each portion of the interconnect shield in the embodiment illustrated with  FIGS. 3A and 3B  comprises similar components that are distinguished with the labels “first” and “second” in describing their respective arrangements. 
   Thus, the equipotential portion  208  shown in  FIG. 3A  has a structure similar to that described with respect to  FIG. 1A  with no insulating material between the interconnect line  216  and the first protective covering  324 . The first support stacks  328 , which support the first protective covering  324 , are in electrical communication with the underlying substrate  320  through openings in the electrically insulative first barrier layer  304 . The interconnect line  316  is positioned between the first support stacks  328  over the first barrier layer  304  so that it is encapsulated by the first protective covering  324 . The substrate  320 , first support stacks  328 , and first protective covering  324  each comprise electrically conductive material, such as polysilicon, so that an equipotential ring  312  is defined to surround the interconnect line  216 . 
   The floating portion  212  shown in  FIG. 3B  differs from the equipotential portion  208  primarily in the use of the electrically insulative second barrier layer  306  to prevent electrical communication between the second protective covering  326  and the substrate  320 . This is achieved by providing a second barrier layer  306  that is free of openings, at least where it contacts the second support stacks  330 . The second barrier layer  306  is provided between the substrate  320  and the second support stacks  330 , which are used to support the second protective covering  326 . The second protective covering  326  is thus electrically isolated from the substrate  320  by the presence of the gap  218  between the two portions of the interconnect shield and the second barrier layer  306 . The gap  218  ensures at least that the first and second protective coverings  324  and  326 , and the first and second support stacks  328  and  330 , are noncontiguous. The first and second barrier layers  304  and  306  may either be contiguous or noncontiguous, provided that only the first barrier layer  304  includes openings that permit electrical communication between the first support stacks  328  and the substrate  320 . 
   There are a variety of methods that may be used to form the interconnect shield.  FIGS. 4A and 4B  respectively set forth exemplary methods for forming the equipotential and floating portions. Each of the methods begins with a substrate, usually a common substrate for the two portions. The methods include subsequent steps of deposition and etching. In one embodiment, layers of polysilicon may be built up in successive steps; these layers are conventionally identified as poly-0, poly-1, poly-2, . . . layers, with the poly-0 layer corresponding to the lowest polysilicon layer, poly-1 to the next higher polysilicon layer, etc. The depositions and etching may be performed using any suitable technique known to those of skill in the art. For example, the depositions may be performed using epitaxy, chemical-vapor deposition (including atmospheric-pressure chemical-vapor deposition, low-pressure chemical vapor deposition, plasma-enhanced chemical-vapor deposition, high-density-plasma chemical vapor deposition, and electron-cyclotron-resonance chemical vapor deposition, among others), spin-on methods, sol-gel methods, bonding methods, or any other suitable deposition method. The etchings may be performed using wet isotropic etching, plasma etching, reactive-ion etching, deep reactive-ion etching, or any other suitable etching method. The etchings may be done selectively by using a known patterning technique, such as optical lithography. 
   As shown in  FIG. 4A , formation of the equipotential portion  208  begins at block  404  by depositing a dielectric layer on the substrate that will function as the first barrier layer  306 . This dielectric layer may comprise any suitable electrically insulative material. In one embodiment, the dielectric layer comprises an oxide or a nitride, such as SiN. At block  408 , the dielectric layer is etched to produce the openings in the first barrier layer  306  through which the equipotential ring  312  is produced. At block  412 , a first conductive layer of material is deposited that will correspond functionally to the interconnect line  216  and support stacks  328 . In one embodiment, this first conductive layer comprises a poly-0 layer. At block  416 , the first conductive layer is etched to distinguish the support stacks  328  and interconnect line  216 . Sacrificial material is deposited at block  420  as an intermediate stage in preparation for forming the protective covering  324 . The sacrificial material may comprise any material that may be removed without also removing the structural layers; in one embodiment, the sacrificial material comprises SiO 2 . At block  424 , the sacrificial material is etched to define the desired shape for the protective covering  324 . At block  428 , a second conductive layer of material is deposited that corresponds to the protective covering  324 . In one embodiment, this second conductive layer comprises a poly-1 layer. It will, however, be apparent to those of skill in the art that the second conductive layer may alternative comprise a layer successive to a poly-1 layer. 
   Application of this sequence of blocks  404 – 428  results in the formation of a structure like that shown in  FIG. 1A . It will be appreciated that in the fabrication of a MEMS device, this sequence will also be accompanied by additional steps used in fabricating mechanical components and additional interconnect lines to be used in the MEMS device. Once the sequence of deposition and etching steps is completed, including both those to form the functional components of the MEMS device and those shown in  FIG. 4A  to produce the equipotential portion of the interconnect shield, the MEMS device is released at block  432 . The release may be effected by exposure to a substance that removes the sacrificial material, such as by exposure to HF where the sacrificial material comprises SiO 2 . 
     FIG. 4B  is similar to  FIG. 4A , reflecting the similarity in structures of the equipotential portion  208  and the floating portion  212  of the interconnect shield. In most instances, fabrication of the floating portion  212  may take place in parallel with fabrication of the equipotential portion  208 , even to the extent of sharing some of the steps in  FIGS. 4A and 4B . For example, at block  440  of  FIG. 4B , a dielectric layer is deposited on the substrate  320 , which will function as the second barrier layer  306 . As for fabrication of the equipotential portion  208 , this dielectric barrier layer may comprise an oxide or a nitride, such as SiN. Accordingly, block  440  may be performed simultaneously with block  404  of  FIG. 4A  to deposit a single dielectric barrier layer that extends longitudinally through the regions of both the equipotential and floating portions  208  and  212 . In embodiments where the gap  218  between the equipotential and floating portions  208  and  212  includes a separation between the first and second barrier layers  304  and  306 , the etching at block  408  of  FIG. 4A  may include etching such a separation. Generally, the dielectric barrier layer is not etched when forming the floating portion  212  (as contrasted with the formation of the equipotential portion  208 ) since the second protective covering  326  is to be electrically isolated from the substrate  320 . 
   Similarly, when a first conductive layer (such as a poly-0 layer) is deposited at block  444  of  FIG. 4B  in fabricating the floating portion  212 , this deposition may be performed simultaneously with the deposition of the first conductive layer at block  412  of  FIG. 4A . At block  448 , the first conductive layer is etched to separate it into distinct support stacks  330  and interconnect line  316 . If depositions are performed simultaneously at blocks  412  of  FIGS. 4A and 444  of  FIG. 4B , the etching at block  448  may additionally separate the first support stacks  328  from the second support stacks  332  as part of forming the gap  218  between the equipotential and floating portions  208  and  212 . As discussed above, this separation contributes to the electrical isolation of the first and second protective coverings  324  and  326 . Generally, the interconnect line  316  will not be etched along the longitudinal direction since a continuous interconnect line  316  is desirable for operating mechanical components of the completed MEMS device. 
   The second protective structure is formed with the sequence of blocks  452 ,  456 , and  460  of depositing sacrificial material, such as SiO 2 , etching the sacrificial material and depositing a second conductive layer, which may be a poly-1 layer. This sequence is similar to the sequence of blocks  420 ,  424 , and  428  in  FIG. 4A  and may, in some embodiments, be performed simultaneously with those blocks. In instances where they are performed simultaneously, an additional etching may be performed to separate the first and second protective covers  324  and  326  so that they are electrically isolated. In addition to being performed simultaneously with portions of  FIG. 4A , blocks  440 – 460  of  FIG. 4B  are also generally performed simultaneously with steps to produce the mechanical components of the MEMS device. Accordingly, at block  464 , the MEMS device is released, such as by exposure to HF to dissolve sacrificial material deposited as part of the process. 
   In the embodiments described above, the floating entrance-guard portion  212  of the interconnect shield provides protection against contaminant particles that are larger than any of its openings. Expressed differently, for a contaminant particle to pass by the floating entrance-guard portion  212  and interfere in the manner described with respect to  FIG. 1B , it must be smaller than any openings around the floating portion  212 . These openings exist at both longitudinal ends of the floating portion  212  and may be reduced in size with a number of different techniques, thereby improving the effectiveness of the interconnect shield. 
   Practical fabrication limitations limit how low an approximately uniform height of the second protective covering  326  may be above the interconnect line. Accordingly, in one embodiment, a longitudinal end region of the second protective covering  326  has a smaller height above the interconnect line  216  than an approximately uniform height of a longitudinally central region of the second protective covering  326 . One technique that may be used to achieve such a smaller height at a longitudinal end region is a dimple-cut technique, in which the profile of the second protective covering  326  is provided with a downwards protrusion at the longitudinal end region. In a fabrication process, this may be achieved by performing a partial etch of an insulating layer between the interconnect-line layer and the protective covering layer at the end region and subsequently etching to this additional polysilicon layer at the end region. In different embodiments, the dimple cut may be included at one or both longitudinal end regions of the second protective covering  326 ; it is expected that the dimple cut will more usually be included at least at the end region opposite from the equipotential portion  208 . 
   An example of such a dimple cut  504  is provided in  FIG. 5A , which is a scanning electron micrograph of a floating portion  212  of an interconnect shield that has been manufactured according to the methods described herein. The micrograph shows the interconnect line  216  being shielded and the bond pad  204  from which it originates, in addition to the dimple cut  504  in the end region of the second protective covering. In the example shown in  FIG. 5A , the height of the central region of the floating portion  212  above the interconnect line  216  is approximately 1.8 μm and the height of the end portion where the dimple cut  504  is located is approximately 0.65 μm. Since the dimple cut provides a smaller separation between the interconnect line  216  and the protective covering, only very small contaminant particles can pass through the end region. 
   For similar reasons, it is also desirable to keep the gap  218  between the equipotential portion  208  and the floating portion  212  of the interconnect shield small to prevent the longitudinal travel of contaminant particles. In some embodiments, this gap  218  is itself protected with a protective jacket structure formed over the gap. Such a protective jacket may be formed in manner similar to that for the protective coverings, but will have generally larger dimensions. An example of such a protective jacket  508  is provided in  FIG. 5B , which is a scanning electron micrograph of a part of a MEMS device that includes an interconnect shield and a protective jacket  508 . As in the micrograph of  FIG. 5A , both the interconnect line  216  being shielded and the bond pad  204  from which it originates are visible. A first end region of the second protective covering  212  is visible near the bond pad  204 ; the other end region of the second protective covering  212  and the first protective covering  208  are hidden by the protective jacket. 
   Having described several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the invention. For example, while embodiments have been illustrated in which a single interconnect line is covered with a single interconnect shield, it is alternatively possible for a single interconnect shield to be used to cover multiple interconnect lines. In addition, in some embodiments, a MEMS device may be provided in which some of the interconnect lines are protected with interconnect shields while other interconnect lines are not. Accordingly, the above description should not be taken as limiting the scope of the invention, which is defined in the following claims.