Abstract:
An image synthesizer according to an embodiment of the present invention includes: a plurality of computing units synthesizing first and second image information based on first and second factors corresponding to the first and second image information to output a third factor as a composition factor of the first and second factors and intermediate output information obtained by multiplying the third factor by third image information as composite image information of the first and second image information; a divider dividing the intermediate output information output from one of the plurality of computing units by the third factor to output the third image information, at least one of the plurality of computing units serving as a first computing unit receiving intermediate input information obtained by multiplying the first image information by the first factor as input information corresponding to the first image information.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to an image synthesizer and an image synthesizing method for the same. In particular, the invention relates to an image synthesizer and an image synthesizing method for the same that adopt an alpha blending technique of synthesizing plural images by using different weighting factors α for the plural images.  
         [0003]     2. Description of Related Art  
         [0004]     Hitherto, an alpha blending technique has been well known as a technique of synthesizing plural images. The alpha blending technique assigns weights to plural images by using a weighting factor α and combines the weighted images to thereby synthesize the images. An example of the alpha blending technique is described by T. Poter and T. Duff in “Compositing Digital Images”, SIGGRAPH, 1984, pp. 253-259. This technique is called “Poter-Duff compositing operation”.  
         [0005]     A weighting factor α used in the Poter-Duff compositing operation is called α value or alpha value, which represents image opacity. In the present invention, this factor is referred to as an “alpha value”. The Poter-Duff compositing operation is described next. In the Poter-Duff compositing operation, an alpha value α out  and a pixel value C out  of a composite image are derived from Expressions (1) and (2), respectively. 
 
α out =α SRC +(1−α SRC )*α DST   (1) 
 
α out   *C   out =α SRC   *C   1 +(1−α SRC )*α DST   *C   0   (2) 
 
 In the above Expressions, C 0  represents a pixel value of a background image, C 1  represents a pixel value of a foreground image, α DST  represents an alpha value of the background image, and α SRC  represents an alpha value of the foreground image. Here, provided that the alpha value α DST  of the background image C 0  is 1, and the background image is opaque, Expressions (1) and (2) are rearranged to Expressions (3) and (4). 
 
α out =α SRC +(1−α SRC )=1  (3) 
 
 C   out =α SRC   *C   1 +(1−α SRC )* C   0   (4) 
 
 If α SRC =0.3, the pixel value C out  of the composite image includes 30% of the pixel value of the foreground image and 70% of the pixel value of the background image. That is, regarding the pixel value C out  of the composite image calculated with the Poter-Duff compositing operation, the pixel value C 1  of the foreground image accounts for 30% of opacity, and the pixel value C 0  of the background image accounts for 70% of opacity. The composite image is obtained by combining the two images. 
 
         [0006]     As understood from the above description, the alpha blending technique makes it possible to adjust opacity of each image based on an alpha value and synthesize the images each having the adjusted opacity. The alpha blending technique can be applied to a color image. For example, as for RGB color images, the alpha blending technique may be applied to each of R (red), G (green), and B (blue) components. As for YCbCr color images, the alpha blending technique may be applied to each of Y (luminance), Cb (chroma blue), and Cr (chroma red) components. An image synthesizing technique adopting such alpha blending technique is disclosed in Japanese Unexamined Patent Publication Nos. 2001-285749 and 2005-77522.  
         [0007]     Further, in the case of synthesizing three or more images, two of the plural images are first combined with Expressions (3) and (4), and the resulting image and the third image are input and combined with Expressions (3) and (4). This operation is repeated to thereby synthesize the three or more images.  
         [0008]     A conventional the image synthesizer  100  that realizes the aforementioned alpha blending technique is described next.  FIG. 13  is a block diagram of the conventional the image synthesizer  100 . As shown in  FIG. 13 , the image synthesizer  100  includes image generators  110 ,  120 , and  140 , a divider  130 , and a display device  150 . The image generator  110  outputs, for example, an alpha-multiplied pixel value α 1 C 1  obtained by multiplying a pixel value obtained by synthesizing four images by an alpha value, and an alpha value α 1 . The image generator  120  outputs a background image pixel value C 0 . The divider  130  divides the input alpha-multiplied pixel value α 1 C 1  by the alpha value α 1  to output a foreground image pixel value C 1 . The image generator  140  outputs a pixel value C out  of a composite image by use of the input background image pixel value C 0 , foreground image pixel value C 1 , and alpha value α 1  based on Expression (4). The display device  150  displays the pixel value C out  of the composite image.  
         [0009]     The image generator  110  is described in more detail below.  FIG. 14  is a block diagram of internal units of the image generator  110 . As shown in  FIG. 14 , the image generator  110  includes alpha blending computing units  111 ,  112 , and  113 , and dividers  114 ,  115 , and  116 . The alpha blending computing units  111 ,  112 , and  113  each synthesize two input images based on an alpha value α and a pixel value C of each image to generate new alpha value and alpha-multiplied pixel value. The dividers  114 ,  115 , and  116  each divide the input alpha-multiplied pixel value by the input alpha value to generate a pixel value; the pixel value is input to the next stage. Here, the image generator  140  of  FIG. 13  includes one alpha blending computing unit and one divider as shown in  FIG. 14  or includes one alpha blending computing unit of  FIG. 14 . A fixed value “1” is set to the alpha value of the background image.  
         [0010]     That is, in the conventional alpha blending computing unit, the alpha-multiplied pixel value is divided by the output alpha value that outputs together with the alpha-multiplied pixel value, and normalizes the pixel value to be input to the next stage with the alpha value to thereby obtain a pixel value of a composite image.  
         [0011]     However, the conventional alpha blending computing unit can output nothing but the alpha-multiplied pixel value. Hence, if a pixel value is sent to the next stage, it is necessary to generate a pixel value not multiplied with an alpha value. As a result, the alpha blending computing units each require a divider, leading to a problem of increasing the circuit size. In the case of synthesizing more images, a number of dividers are necessary, so this problem becomes more serious.  
         [0012]     Further, even if pixel value of a composite image is successively calculated with a CPU (central processing unit), the calculated values are alpha-multiplied pixel values. Thus, the alpha-multiplied pixel values should be divided and normalized for subsequent composition. In general, the division takes more time to execute than the multiplication or addition. This causes a problem in that the processing time increases if computation is executed with a computation method used in the conventional alpha blending computing unit.  
       SUMMARY OF THE INVENTION  
       [0013]     An image synthesizer according to an aspect of the present invention includes: a plurality of computing units synthesizing first and second image information based on first and second factors corresponding to the first and second image information to output a third factor as a composition factor of the first and second factors and intermediate output information obtained by multiplying the third factor by third image information as composite image information of the first and second image information; a divider dividing the intermediate output information output from one of the plurality of computing units by the third factor to output the third image information, at least one of the plurality of computing units serving as a first computing unit receiving intermediate input information obtained by multiplying the first image information by the first factor as input information corresponding to the first image information.  
         [0014]     According to the image synthesizer of the present invention, the computing unit outputs the third factor as the composition factor of the first and second factors, and the intermediate output information obtained by multiplying the third factor by the third image information as the composite image information of the first and second image information. However, at least one of the plurality of computing units is a first computing unit receiving intermediate input information obtained by multiplying the first image information by the first factor as input information corresponding to the first image information. Thus, since the first computing unit is used as the tandem-connected computing units, intermediate output information output from a computing unit at a previous stage can be used as intermediate input information of a computing unit at a subsequent stage as it is. Hence, the image synthesizer of the present invention can omit a divider that is provided between the tandem-connected computing units. Therefore, a divider that occupies a larger circuit area can be omitted, so a chip area or layout area of the image synthesizer can be reduced. In contrast, conventional image synthesizers should be provided with a divider between tandem-connected computing units.  
         [0015]     An image synthesizing method according to another aspect of the invention includes: executing a plurality of synthesizing processes of synthesizing first and second image information based on first and second factors corresponding to the first and second image information to output a third factor as a composition factor of the first and second factors and intermediate output information obtained by multiplying the third factor by third image information as composite image information of the first and second image information; and dividing the intermediate output information output in one of the plurality of synthesizing processes by the third factor to output the third image information, at least one of the plurality of synthesizing processes being a first synthesizing process receiving intermediate input information obtained by multiplying the first image information by the first factor as input information corresponding to the first image information.  
         [0016]     According to the image synthesizing method of the present invention, the synthesizing processes output a third factor as a composition factor of the first and second factors and intermediate output information obtained by multiplying the third factor by third image information as composite image information of the first and second image information. However, at least one of the plurality of synthesizing processes is a first synthesizing process receiving intermediate input information obtained by multiplying the first image information by the first factor as input information corresponding to the first image information. Thus, the first synthesizing process is executed as the second and subsequent processes, so intermediate output information output in a previous synthesizing process can be used as intermediate input information to be output in a subsequent synthesizing process as it is. Hence, the image synthesizing method of the present invention can omit the division executed between consecutive synthesizing processes. Hence, the time-consuming division can be omitted, so a period necessary for the image synthesizing processing can be shortened. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:  
         [0018]      FIG. 1  is a block diagram of an image synthesizer according to a first embodiment of the present invention;  
         [0019]      FIG. 2  is a block diagram of an image synthesizer according to a second embodiment of the present invention;  
         [0020]      FIG. 3  is a block diagram of another example of the image synthesizer of the second embodiment;  
         [0021]      FIG. 4  is a block diagram of an image synthesizer according to a third embodiment of the present invention;  
         [0022]      FIG. 5  is a block diagram of an image synthesizer according to a fourth embodiment of the present invention;  
         [0023]      FIG. 6  is a block diagram of another example of the image synthesizer of the fourth embodiment;  
         [0024]      FIG. 7  is a block diagram of an image synthesizer according to a fifth embodiment of the present invention;  
         [0025]      FIG. 8  is a block diagram of an image synthesizer according to a sixth embodiment of the present invention;  
         [0026]      FIG. 9  is a block diagram of another example of the image synthesizer of the sixth embodiment;  
         [0027]      FIG. 10  is a block diagram of an image synthesizer according to a seventh embodiment of the present invention;  
         [0028]      FIG. 11  is a block diagram of an image synthesizer according to an eighth embodiment of the present invention;  
         [0029]      FIG. 12  is a flowchart of processings executed with a CPU of the image synthesizer of the eighth embodiment;  
         [0030]      FIG. 13  is a block diagram of a conventional image synthesizer; and  
         [0031]      FIG. 14  is a detailed block diagram of a conventional image generator.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0032]     The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed.  
       First Embodiment  
       [0033]     An image synthesizer  1  according to a first embodiment of the present invention synthesizes four images, images A, B, C, and D, for example and outputs the composite image. The respective images include information about an alpha value α representing image opacity and a pixel value C. An alpha blending computing unit used in the present invention combines, for example, first image information (for example, pixel value C 0  of a background image) and second image information (for example, pixel value C 1  of a foreground image) based on a first factor (for example, alpha value α 0  of the background image) and a second factor (for example, alpha value α 1  of the foreground image) to synthesize two images. Then, a third factor (for example, alpha value α mix  of the composite image) obtained by synthesizing the alpha values α of the background image and the foreground image, and intermediate output information (for example, alpha-multiplied pixel value α mix C mix ) obtained by multiplying the alpha value α mix  of the composite image by third image information (for example, pixel value C mix  of the composite image) obtained by synthesizing the pixel values of the background image and the foreground image.  
         [0034]     Further, in this embodiment, plural pixels are synthesized using first and second computing units that execute computation in different ways. The second computing unit outputs the alpha value α mix  of the composite image, and the alpha-multiplied pixel value α mix C mix  based on the alpha value α 0  and pixel value C 0  of the background image, and the alpha value α 1  and pixel value C 1  of the foreground image. The first computing unit outputs alpha value α mix  of the composite image and the alpha-multiplied pixel value α mix C mix  based on the intermediate input information (for example, alpha-multiplied pixel value α 0 C 0  of the background image), the alpha value α 0  of the background image, and the alpha value α 1  and pixel value C 1  of the foreground image.  
         [0035]      FIG. 1  is a block diagram of the image synthesizer  1 . As shown in  FIG. 1 , the image synthesizer  1  includes a second computing unit (for example, alpha blending computing unit  10 ), a first computing unit (for example, alpha blending computing units  20   1  and  20   2 ), and a divider  31 . The alpha blending computing units  10 ,  20   1 , and  20   2  are arranged such that the alpha blending computing units  20   1  and  20   2  are connected in tandem with the alpha blending computing unit  10  at the first stage. An output of the alpha blending computing unit  20   2  at the last stage is connected with the divider  31 .  
         [0036]     The alpha blending computing unit  10  receives, as an alpha value α 0  and pixel value C 0  of the background image, an alpha value α a  and pixel value C a  of the image A, and receives, as an alpha value α 1  and pixel value C 1  of the foreground image, an alpha value α b  and pixel value C b  of the image B. Further, as an alpha value α mix  and alpha-multiplied pixel value α mix C mix  of the composite image, an alpha value cab and alpha-multiplied pixel value α ab C ab  are output. The alpha blending computing unit  10  includes multipliers  11  to  13 , a subtractor  14 , and adders  15  and  16 .  
         [0037]     The multiplier  11  receives the alpha value α a  of the image A and an output value of the subtractor  14  to output a result of multiplying the two values. The multiplier  12  receives the pixel value C a  of the image A and an output value of the multiplier  11  to output a result of multiplying the two values. The multiplier  13  receives the alpha value α b  and pixel value C b  of the image B to output a result of multiplying the two values. The subtractor  14  receives a value “1” and the alpha value α b  of the image B to output a value obtained by subtracting the alpha value α b  from the value “1”. The adder  15  receives an output value of the multiplier  11  and the alpha value α b  of the image B to output a result of adding the two values. The adder  16  receives an output value of the multiplier  12  and an output value of the multiplier  13  to output a result of adding the two values. Here, an output value of the adder  15  is the alpha value α ab  output from the alpha blending computing unit  10 , and an output value of the adder  16  is the alpha-multiplied pixel value α ab C ab  output from the alpha blending computing unit  10 .  
         [0038]     The alpha blending computing unit  20   1  receives, as an alpha value α 0  and alpha-multiplied pixel value α 0 C 0  of the background image, an alpha value α ab  and alpha-multiplied pixel value α ab C ab  of the alpha blending computing unit  10  at a previous stage, and receives an alpha value α 1  and pixel value C 1  of the foreground image, an alpha value α c  and pixel value C c  of the image C. Further, as an alpha value α mix  and alpha-multiplied pixel value α mix C mix  of the composite image, an alpha value α abc  and alpha-multiplied pixel value α abc C abc  are output. The alpha blending computing unit  20   1  includes multipliers  21   1  to  23   1 , a subtractor  24   1 , and adders  25   1  and  26   1 .  
         [0039]     The multiplier  21   1  receives the alpha value α ab  output from the alpha blending computing unit  10  and an output value of the subtractor  24   1  to output a result of multiplying the two values. The multiplier  22   1  receives the alpha-multiplied pixel value α abc C abc  output from the alpha blending computing unit  10  and an output value of the subtractor  24   1  to output a result of multiplying the two values. The multiplier  23   1  receives the alpha value α c  and pixel value C c  of the image C to output a result of multiplying the two values. The subtractor  24   1  receives the value “1” and the alpha value α c  of the image C to output a result of subtracting the alpha value α c  from the value “1”. The adder  25   1  receives an output value of the multiplier  21   1  and the alpha value α c  of the image C to output a result of adding the two values. The adder  26   1  receives an output value of the multiplier  22   1  and an output value of the multiplier  23   1  to output a result of adding the two values. Here, an output value of the adder  25   1  is the alpha value α abc  output from the alpha blending computing unit  20   1 , and an output value of the adder  26   1  is the alpha-multiplied pixel value α abc C abc  output from the alpha blending computing unit  20   1 .  
         [0040]     The alpha blending computing unit  20   2  receives, as an alpha value α 0  and alpha-multiplied pixel value α 0 C 0  of the background image, the alpha value α abc  and alpha-multiplied pixel value α abc C abc  of the alpha blending computing unit  20   2  at the previous stage, and receives, as alpha value α 1  and pixel value C 1  of the foreground image, the alpha value α d  and pixel value C d  of the image D. Further, as the alpha value α mix  and alpha-multiplied pixel value α mix C mix  of the composite image, the alpha value α abcd  and alpha-multiplied pixel value α abcd C abcd  are output. The alpha blending computing unit  20   2  includes multipliers  21   2  to  23   2 , a subtractor  24   2 , and adders  25   2  and  26   2 .  
         [0041]     The multiplier  21   2  receives the alpha value α abc  output from the alpha blending computing unit  20   1  and an output value of the subtractor  24   2  to output a result of multiplying the two values. The multiplier  22   2  receives the alpha-multiplied pixel value α abc C abc  output from the alpha blending computing unit  20   1  and an output value of the subtractor  24   2  to output a result of multiplying the two values. The multiplier  23   2  receives an alpha value α d  and pixel value C d  of the image D to output a result of multiplying the two values. The subtractor  24   2  receives the value “1” and the alpha value α d  of the image D to output a result of subtracting the alpha value α d  from the value “1”. The adder  25   2  receives an output value of the multiplier  21   2  and the alpha value α d  of the image D to output a result of adding the two values. The adder  26   2  receives an output value of the multiplier  22   2  and an output value of the multiplier  23   2  to output a result of adding the two values. Here, an output value of the adder  25   2  is the alpha value α abcd  output from the alpha blending computing unit  20   2 , and an output value of the adder  26   2  is the alpha-multiplied pixel value α abcd C abcd  output from the alpha blending computing unit  20   2 . Further, the alpha value α abcd  output from the alpha blending computing unit  20   2  is output as an output alpha value of the image synthesizer  1  to another device.  
         [0042]     The divider  31  receives the alpha-multiplied pixel value α abcd C abcd  output from the alpha blending computing unit  20   2  and the alpha value α abcd  to output a result of dividing the alpha-multiplied pixel value α abcd C abcd  by the alpha value α abcd  (pixel value C abcd ). The pixel value C abcd  is output as an output pixel value of the image synthesizer  1  to another device.  
         [0043]     In the thus-connected units, the result of calculating output values of the alpha blending computing units and operations of the image synthesizer  1  are described next. Here, as for the images A, B, C, and D, the image A is assumed as the bottom image, and the images B, C, and D are superimposed on the image A in this order. First, the alpha blending computing unit  10  at the first stage receives the alpha value α a , pixel value C a  of the image A as one input image and receives the alpha value α b  and pixel value C b  of the image B as the other input image. Based on the input values, the subtractor  14  subtracts the alpha value α b  of the image B from the value “1” to output (1−α b ). The multiplier  11  multiplies an output value of the subtractor  14  by the alpha value α a  of the image A to output ((1−α b )*α a ). The adder  15  adds an output value of the multiplier  11  and the alpha value α b  of the image B to output (α b +(1−α b )*α a ). Accordingly, the alpha value α ab  output from the alpha blending computing unit  10  is expressed by Expression (5). 
 
α ab =α b +(1−α b )*α a   (5) 
 
         [0044]     On the other hand, the multiplier  13  multiplies the alpha value α b  and pixel value C b  of the image B to output (α b *C b ). The multiplier  12  multiplies an output value of the multiplier  11  by the pixel value C a  of the image A to output ((1−α b )*α a *C a ). The adder  16  adds an output value of the multiplier  12  and an output value of the multiplier  13  to output (α b *C b +(1−α b )*α a *C a ). Accordingly, the alpha-multiplied pixel value α ab C ab  output from the alpha blending computing unit  10  is expressed by Expression (6). 
 
α ab   C   ab =α b   *C   b +(1−α b )*α a   *C   a   (6) 
 
         [0045]     Next, the alpha blending computing unit  20   1  at the second stage receives the alpha value α ab  output from the alpha blending computing unit  10 , the alpha-multiplied pixel value α ab C ab , and the alpha value α c  and pixel value C c  of the image C. Based on the input values, the subtractor  24   1  subtracts the alpha value α c  of the image C from the value “1” to output (1−α c ). The multiplier  21   1  multiplies an output value of the subtractor  24   1  by the alpha value α ab  of the alpha blending computing unit  10  to output ((1−α c )*α ab ). The adder  25   1  adds an output value of the multiplier  21   1  and the alpha value α c  of the image C to output (α c +(1−α c )*α ab ). Accordingly, the alpha value α abc  output from the alpha blending computing unit  20   1  is derived from Expression (7).  
                     α   abc     =       α   c     +       (     1   -     α   c       )     *     α   ab                     =       α   c     +       (     1   -     α   c       )     *     α   b       +       (     1   -     α   c       )     *     (     1   -     α   b       )     *     α   a                       (   7   )             
 
         [0046]     On the other hand, the multiplier  23   1  multiplies the alpha value α c  and pixel value C c  of the image C to output (α c *C c ). The multiplier  22   1  multiplies the alpha-multiplied pixel value α ab C ab  output from the output from the alpha blending computing unit  10  by an output value of the subtractor  24   1  to output ((1−α c )*α ab C ab ). The adder  26   1  adds an output value of the multiplier  22   1  and an output value of the multiplier  23   1  to output (α c *C c +(1−α c )*α ab C ab ) Accordingly, the alpha-multiplied pixel value α abc C abc  output from the alpha blending computing unit  20   1  is derived from Expression (8).  
                       α   abc     ⁢     C   abc       =       ⁢         α   c     *     C   c       +       (     1   -     α   c       )     *     α   ab     ⁢     C   ab                     =       ⁢         α   c     *     C   c       +       (     1   -     α   c       )     *     α   b     *     C   b       +                     ⁢       (     1   -     α   c       )     *     (     1   -     α   b       )     *     α   a     *     C   a                     (   8   )             
 
         [0047]     Next, the alpha blending computing unit  20   2  at the third stage receives the alpha value α abc  output from the alpha blending computing unit  20   1 , the alpha-multiplied pixel value α abc C abc , and the alpha value α d  and pixel value C d  of the image D. Based on the input values, the subtractor  24   2  subtracts the alpha value α d  of the image D from the value “1” to output (1−α d ). The multiplier  21   2  multiplies an output value of the subtractor  24   2  by the alpha value α abc  of the alpha blending computing unit  20   1  to output ((1−α d )*α abc ). The adder  25   2  adds an output value of the multiplier  21   2  and the alpha value α d  of the image D to output (α d +(1−α d )*α abc ). Accordingly, the alpha value α abcd  output from the alpha blending computing unit  20   2  is expressed by Expression (9).  
                     α   abcd     =       ⁢       α   d     +       (     1   -     α   d       )     *     α   abc                     =       ⁢       α   d     +       (     1   -     α   d       )     *     α   c       +       (     1   -     α   d       )     *     (     1   -     α   c       )     *     α   ab                     =       ⁢       α   d     +       (     1   -     α   d       )     *     α   c       +       (     1   -     α   d       )     *     (     1   -     α   c       )     *     α   b       +                     ⁢       (     1   -     α   d       )     *     (     1   -     α   c       )     *     (     1   -     α   b       )     *     α   a                     (   9   )             
 
         [0048]     On the other hand, the multiplier  23   2  multiplies the alpha value α d  and pixel value C d  of the image D to output (α d *C d ). The multiplier  22   2  multiplies the alpha-multiplied pixel value α abc C abc  output from the alpha blending computing unit  20   1  by an output value of the subtractor  24   2  to output ((1−α d )*α abc C abc ). The adder  26   2  adds an output value of the multiplier  22   2  and an output value of the multiplier  23   2  to output (α d *C d +(1−α d )*α abc C abc ). Accordingly, the alpha-multiplied pixel value α abcd C abcd  output from the alpha blending computing unit  20   1  is derived from Expression (10).  
                       α   abcd     ⁢     C   abcd       =       ⁢         α   d     *     C   d       +       (     1   -     α   d       )     *     α   abc     ⁢     C   abc                     =       ⁢         α   d     *     C   d       +       (     1   -     α   d       )     *     α   c     *     C   c       +                     ⁢       (     1   -     α   d       )     *     (     1   -     α   c       )     *     α   ab     ⁢     C   ab                   =       ⁢         α   d     *     C   d       +       (     1   -     α   d       )     *     α   c     *     C   c       +                     ⁢         (     1   -     α   d       )     *     (     1   -     α   c       ⁢           )     *     α   b     *     C   b       +                     ⁢       (     1   -     α   d       )     *     (     1   -     α   c       )     *     (     1   -     α   b       )     *     α   c     *     C   a                     (   10   )             
 
         [0049]     The divider  31  divides the thus-calculated alpha-multiplied pixel value α abcd C abcd  by the alpha value c. Thus, a pixel value C abcd  as the final output value of the image synthesizer  1  is obtained.  
         [0050]     As described above, according to the image synthesizer  1  of this embodiment, the second computing unit at the first stage (for example, alpha blending computing unit  10 ) synthesizes the image A and the image B to output the alpha value α ab  and alpha-multiplied pixel value α ab C ab  of the composite image of the images A and B.  
         [0051]     Further, the first computing unit (for example, alpha blending computing unit  20   1 ) is connected in tandem with the alpha blending computing unit  10 . The alpha blending computing unit  20   1  receives the alpha value α ab  and alpha-multiplied pixel value α ab C ab  of the composite image output from the alpha blending computing unit  10  as one input image information. Further, as the other input image information, the alpha value α c  and pixel value C c  of the image C are input.  
         [0052]     As apparent from the above Expression (7), the alpha blending computing unit  20   1  outputs the alpha value α abc  of the composite image obtained by synthesizing the images A, B, and C based on the alpha value α ab  of the composite image output from the alpha blending computing unit  10  and the alpha value α c  of the image C. Further, as apparent from the above Expression (8), the alpha blending computing unit  20   1  outputs the alpha-multiplied pixel value α abc C abc  of the composite image of the images A, B, and C based on the alpha-multiplied pixel value α ab C ab  of the composite image output from the alpha blending computing unit  10  and the alpha value α c  and pixel value C c  of the image C.  
         [0053]     That is, in the case of generating an alpha-multiplied pixel value αC to be output, the alpha blending computing unit  20   1  uses an alpha-multiplied pixel value out of input image information and does not take an alpha value corresponding to the alpha-multiplied pixel value into consideration. Thus, the alpha-multiplied pixel value αC output from the alpha blending computing unit at the previous stage can be directly received. This makes it possible to dispense with a divider that needs to be provided between tandem-connected alpha blending computing units in the conventional technique. The alpha blending computing unit of the present invention includes no divider. Accordingly, the number of dividers the circuit size of which is larger than that of the computing unit can be reduced in the entire image synthesizer, and a layout area or chip area of the image synthesizer can be reduced.  
         [0054]     Further, the alpha blending computing unit  20   2  connected with the alpha blending computing unit  20   1  receives, similar to the alpha blending computing unit  20   1 , the alpha value α abc  and alpha-multiplied pixel value α abc C abc  of the composite image as one input information and receives the alpha value α d  and pixel value C d  of the image D as the other input information. Based on the input values, the alpha blending computing unit  20   2  outputs the alpha value α abcd  and alpha-multiplied pixel value α abcd C abcd  of the composite image of the images A, B, C, and D as expressed by above Expressions (9) and (10). In this embodiment, the alpha blending computing unit  20   2  is at the last stage, so its output is connected with the divider  31 . The divider  31  generates and outputs the pixel value C abcd  to be output from the image synthesizer  1  based on an output value of the alpha blending computing unit  20   2 . Here, the alpha value α abcd  output from the alpha blending computing unit  20   2  is output as an alpha value of an image synthesized with the image synthesizer  1  as it is.  
         [0055]     Accordingly, the image synthesizer  1  of this embodiment has only to provide a divider at the last stage and can reduce the number of dividers as compared with the conventional image synthesizer. This beneficial effect is enhanced if many images are synthesized and the number of alpha blending computing units connected in tandem is increased.  
       Second Embodiment  
       [0056]      FIG. 2  shows an image synthesizer  2  according to a second embodiment of the present invention. Although the image synthesizer  1  of the first embodiment provides the second computing unit at the first stage, the image synthesizer  2  of the second embodiment provides the first computing unit at the first stage. In the second embodiment, the same components as those of the first embodiment are denoted by like reference numerals, and description thereof is omitted here.  
         [0057]     As shown in  FIG. 2 , the image synthesizer  2  of the second embodiment includes the first computing unit at the first stage (for example, alpha blending computing unit  20   3 ). Further, the image A is input to the alpha blending computing unit  20   3  through the multiplier  32 . The multiplier  32  multiplies the alpha value α a  and pixel value C a  of the image A to generate an alpha-multiplied pixel value α a C a  of the image A. The alpha-multiplied pixel value α a C a  and alpha value αa are input as one input information and the alpha value α b  and pixel value C b  of the image B as the other input information, and the alpha blending computing unit  20   3  outputs the alpha value α ab  and alpha-multiplied pixel value α ab C ab  of the composite image of the images A and B. The alpha value α ab  and alpha-multiplied pixel value α ab C ab  output from the alpha blending computing unit  20   3  are expressed by Expressions (11) and (12). 
 
α ab =α b +(1−α b )*α a   (11) 
 
α ab   C   ab =α b   *C   b +(1−α b )*α a   *C   a   (12) 
 
         [0058]     As apparent from Expressions (11) and (12), an output of the alpha blending computing unit  20   3  at the first stage of the image synthesizer  2  of the second embodiment is the same as that of the alpha blending computing unit  10  at the first stage of the image synthesizer  1  of the first embodiment. The alpha blending computing unit  20   1  and  20   2 , and the divider  31  are connected with the alpha blending computing unit  20   3  in the same manner as the first embodiment. Hence, an output value of the image synthesizer  2  of the second embodiment is similar to that of the first embodiment.  
         [0059]     As understood from the above description, according to the image synthesizer  2  of the second embodiment, the first computing units are connected in tandem to realize an output value similar to that of the image synthesizer  1  of the first embodiment. Further, the tandem-connected computing units are the first computing units, and the same circuits can be used at the stage of the circuit design or chip layout, making it possible to simplify the circuit design and chip layout.  
         [0060]     Further, also in the image synthesizer  2  of the second embodiment, it is unnecessary to provide a divider between the alpha blending computing units and inside the alpha blending computing unit. Hence, it is possible to save a layout area or chip area for the divider similar to the first embodiment.  
         [0061]      FIG. 3  shows another example of the image synthesizer  2  of the second embodiment. An image synthesizer  2 ′ of  FIG. 3  uses the first computing unit (for example, alpha blending computing unit  20   4 ) in place of the multiplier  32  of the image synthesizer  2 . The alpha blending computing unit  20   4  does not receive the alpha value α and the image value C as one input information (as expressed by value “0” in  FIG. 3 ) and receives the alpha value α a  and pixel value C a  of the image A as the other input information. Thus, the alpha value α 204  and alpha-multiplied pixel value α 204 C 204  output from the alpha blending computing unit  20   4  are expressed by Expressions (13) and (14).  
                     α   204     =       α   a     +       (     1   -     α   a       )     *   0                   =     α   a                   (   13   )                         α   204     ⁢     C   204       =         α   a     *     C   α       +       (     1   -     α   a       )     *   0   *   0                   =       α   a     *     C   a                     (   14   )               
         [0062]     That is, the alpha value α 204  and alpha-multiplied pixel value α 204 C 204  output from the alpha blending computing unit  20   4  become the alpha value α a  and alpha-multiplied pixel value α a C a  of the image A. Accordingly, the alpha blending computing unit  20   3 ,  20   1  and  20   2 , and the divider  31  are connected in tandem with the alpha blending computing unit  20   4  similar to the image synthesizer  2  to realize an output value similar to that of the image synthesizer  1  of the first embodiment.  
         [0063]     Further, in the image synthesizer  2 , the multiplier  32  is necessary in addition to the alpha blending computing unit, but in the image synthesizer  2 ′, the alpha blending computing unit of the same configuration as those of the units is used in place of the multiplier  32 . Thus, the design of the image synthesizer  2 ′ can be simpler than that of the image synthesizer  2 .  
       Third Embodiment  
       [0064]      FIG. 4  is a block diagram of an image synthesizer  3  according to a third embodiment of the present invention. As shown in  FIG. 4 , the image synthesizer  3  of the third embodiment differs from the image synthesizer  1  of the first embodiment in terms of tandem-connected alpha blending computing units at second and subsequent stages. In this embodiment, as the tandem-connected first computing units at the second and subsequent stages, the alpha blending computing units  40   1  and  40   2  are used. The first computing unit of this embodiment receives, as one input information, a result of subtracting the alpha value α from the value “1” (1−α) and the alpha-multiplied pixel value αC and receives, as the other input information, the alpha value α and pixel value C. Further, the first computing unit of this embodiment outputs, based on the input values, a result of subtracting the alpha value α mix  from the value “1” (1−α mix ) and the alpha-multiplied pixel value α mix C mix  of the composite image.  
         [0065]     Here, in the image synthesizer  3  of this embodiment, the alpha value α ab  output from the output from the alpha blending computing unit  10  at the first stage is input as an alpha value corresponding to one input image to the alpha blending computing unit  40   1  at the second stage through the subtractor  33 . The subtractor  33  outputs a result of subtracting the alpha value α ab  from the value “1”.  
         [0066]     The first computing unit of this embodiment is described in detail next. As the first computing unit, the alpha blending computing unit  40   1  is described by way of example. The alpha blending computing unit  40   1  includes multipliers  41   1 ,  42   1 , and  43   1 , a subtractor  44   1 , and an adder  45   1 . The alpha blending computing unit  40   1  receives, as an alpha value α and alpha-multiplied pixel value αC corresponding to one input image, the value (1−α ab ) and alpha-multiplied pixel value α ab C ab . Further, the alpha blending computing unit  40   1  receives, as an alpha value α and pixel value C corresponding to the other input image, the alpha value α c  and pixel value C c  of the image C.  
         [0067]     The alpha blending computing unit  40   1  outputs a result of subtracting the alpha value α c  of the image C from the value “1” (1−α c ) with the subtractor  44   1 . The multiplier  41   1  multiplies an output value of the subtractor  44   1  by the value (1−α ab ) input as one input image value to output the multiplied value. The output value is an alpha value to be output from the alpha blending computing unit  40   1  as the value (1−α abc ). The value (1−α abc ) is expressed by Expression (15) below.  
                     1   -     α   abc       =       (     1   -     α   c       )     *     (     1   -     α   ab       )                   =     1   -     {       α   c     +       (     1   -     α   c       )     *     α   ab         }                   =     1   -     {       α   c     +       (     1   -     α   c       )     *     α   b       +       (     1   -     α   c       )     *     (     1   -     α   b       )     *     α   a         }                     (   15   )             
 
         [0068]     Further, the multiplier  42   1  multiplies an output value of the subtractor  44   1  by the alpha-multiplied pixel value α ab C ab  input as one input image to output the multiplied value. The multiplier  43   1  multiplies the alpha value α c  and pixel value C c  of the image C to output the multiplied value. The adder  45   1  adds an output value of the multiplier  42   1  and an output value of the multiplier  43   1  to output the added value. The an output value of the adder  45   1  becomes an alpha-multiplied pixel value α abc C abc  to be output from the alpha blending computing unit  40   1 . The alpha-multiplied pixel value α abc C abc  is expressed by Expression (16) below.  
                       α   abc     ⁢     C   abc       =       ⁢         α   c     *     C   c       +       (     1   -     α   c       )     *     α   ab     ⁢     C   ab                     =       ⁢         α   c     *     C   c       +       (     1   -     α   c       )     *     α   b     *     C   b       +                     ⁢       (     1   -     α   c       )     *     (     1   -     α   b       )     *     α   a     *     C   a                     (   16   )             
 
         [0069]     Next, the alpha blending computing unit  40   2  connected in tandem with the alpha blending computing unit  40   1  has the same configuration as that of the alpha blending computing unit  40   1 . Further, the alpha blending computing unit  40   2  receives, as the alpha value α and alpha-multiplied pixel value αC corresponding to one input image, the value (1−α abc ) and alpha-multiplied pixel value α abc C abc . Further, the alpha blending computing unit  40   2  receives, as alpha value α and pixel value C corresponding to the other input image, the alpha value α d  and pixel value C d  of the image D. The alpha blending computing unit  40   2  outputs, based on the input values, the alpha value (1−α abcd ) and alpha-multiplied pixel value α abcd C abcd . The alpha value (1−α abcd ) and alpha-multiplied pixel value α abcd C abcd  are expressed by Expressions (17) and (18) below.  
                     1   -     α   abcd       =       ⁢       (     1   -     α   d       )     *     (     1   -     α   abc       )                   =       ⁢     1   -     {       α   d     +       (     1   -     α   d       )     *     α   abc         }                   =       ⁢     1   -     {       α   d     +       (     1   -     α   d       )     *     α   c       +       (     1   -     α   d       )     *     (     1   -     α   c       )     *     α   ab         }                   =       ⁢     1   -     {             α   d     +       (     1   -     α   d       )     *     α   c       +       (     1   -     α   d       )     *                   α   b     +       (     1   -     α   d       )     *     (     1   -     α   c       )     *     (     1   -     α             ⁢   b         )     *     α             ⁢   a                 }                     (   17   )                         α   abcd     ⁢     C   abcd       =       ⁢         α   d     *     C   d       +       (     1   -     α   d       )     *     α             ⁢   abc       ⁢     C   abc                     =       ⁢         α   d     *     C   d       +       (     1   -     α   d       )     *     α   c     *     C   c       +                     ⁢       (     1   -     α   d       )     *     (     1   -     α   c       )     *     α   ab     ⁢     C   ab                   =       ⁢         α   d     *     C   d       +       (     1   -     α   d       )     *     α   c     *     C   c       +       (     1   -     α   d       )     *                       ⁢         (     1   -     α   c       )     *     α   b     *     C   b       +       (     1   -     α   d       )     *     (     1   -     α   c       )     *                       ⁢       (     1   -     α   b       )     *     α   a     *     C   a                     (   18   )             
 
         [0070]     The alpha value (1−α abcd ) output from the alpha blending computing unit  40   2  is input to the subtractor  34 , and the alpha value (1−α abcd ) is subtracted from the value “1”. That is, an output value of the subtractor  34  is an alpha value α abcd . The alpha value α abcd  is input to the divider  31  and then output as an alpha value of the image synthesizer  3 .  
         [0071]     As understood from the above description, in the image synthesizer  3  of the third embodiment, an alpha value corresponding to an input alpha-multiplied pixel value among the alpha values input to a computing unit at the first stage out of the tandem-connected first computing units is set to (1−α) by use of the subtractor, and an alpha value output from a computing unit at the last stage out of the tandem-connected first computing units is set to (1−α) by use of the subtractor. Thus, the image synthesizer  3  of the third embodiment can obtain an alpha value of a composite image similar to the image synthesizer of the first and second embodiments.  
         [0072]     Accordingly, the image synthesizer  3  of the third embodiment can reduce the circuit size of the first computing unit (for example, alpha blending computing units  40   1  and  40   2 ) by an adder size as compared with the first computing unit of the first and second embodiments. That is, each alpha blending computing unit can be downsized, so the effect of reducing the circuit size is very large in the case of synthesizing a number of images.  
       Fourth Embodiment  
       [0073]      FIG. 5  is a block diagram of an image synthesizer  4  according to a fourth embodiment of the present invention. In the first to third embodiments, the image A is the bottom image, and the images B, C, and D are superimposed on the image A in this order. In contrast, in the fourth embodiment, the images C, B, and A are superimposed in the order on the image D as the bottom image. That is, the image synthesizer  4  of the fourth embodiment synthesizes, based on the top image, images as the background images.  
         [0074]     As shown in  FIG. 5 , in the image synthesizer  4 , the first computing unit (for example, alpha blending computing units  50   1  and  50   2 ) is connected in tandem with the second computing unit (for example, alpha blending computing unit  10 ). The alpha blending computing unit  10  outputs the alpha value α cd  and alpha-multiplied pixel value α cd C cd  of the composite image of the image C and image D. The alpha blending computing unit  50   1  uses the alpha value α cd  and alpha-multiplied pixel value α cd C cd  output from the alpha blending computing unit  10  as a first factor and first image information and uses the alpha value α b  and pixel value C b  of the image B as a second factor and second image information. Based on the above, the alpha blending computing unit  50   1  outputs the alpha value α bcd  and alpha-multiplied pixel value α bcd C bcd  of the composite image of the images B, C, and D. The alpha blending computing unit  50   2  uses an output value of the alpha blending computing unit  50   1  to output the alpha value α abcd  and alpha-multiplied pixel value α abcd C abcd  of the composite image of the images A, B, C, and D. An output of the alpha blending computing unit  50   2  is connected with the divider  31 , and the alpha-multiplied pixel value α abcd C abcd  is divided by the alpha value α abcd  to output the pixel value C abcd  of the composite image.  
         [0075]     Here, the alpha blending computing unit  10  differs from that of the first embodiment only in terms of an input image, and an output alpha value α cd  and alpha-multiplied pixel value α cd C cd  are expressed by Expressions (19) and (20). 
 
α cd =α d +(1−α d )*α c   
 
α cd   C   cd =α d   *C   d +(1−α d )*α c   *C   c   (20) 
 
         [0076]     The alpha blending computing unit  10  is the same as that of the first embodiment, so its detailed description is omitted here. The alpha blending computing units  50   1  and  50   2  are detailed below. The alpha blending computing units  50   1  and  50   2  are the same, so the alpha blending computing unit  50   1  is explained by way of example.  
         [0077]     The alpha blending computing unit  50   1  receives, as the alpha value α and pixel value C corresponding to one input image, the alpha value α b  and pixel value C b  of the image B. Further, the alpha blending computing unit  50   1  receives, as the alpha value α and alpha-multiplied pixel value αC corresponding to the other input image, the alpha value α cd  and alpha-multiplied pixel value α cd C cd  output from the alpha blending computing units  10  at the previous and subsequent stages. The alpha blending computing unit  50   1  outputs, based on the input values, the alpha value α bcd  and alpha-multiplied pixel value α bcd C bcd .  
         [0078]     The alpha blending computing unit  50   1  includes multipliers  51   1  and  52   1 , a subtractor  53   1 , and adders  54   1  and  55   1 . The subtractor  53   1  subtracts the alpha value α cd  corresponding to the other input image from the value “1” to output the resultant. The multiplier  51   1  multiplies an output value of the subtractor  53   1  by the alpha value α b  of the image B to output the multiplied value. The adder  54   1  adds an output value of the multiplier  51   1  and the alpha value α cd  corresponding to the other input image to output the added value. An output value of the adder  54   1  becomes an alpha value α bcd  to be output from the alpha blending computing unit  50   1 . The alpha value α bcd  is expressed by Expression (21) below.  
                     α   bcd     =       α     c   ⁢           ⁢   d       +       (     1   -     α     c   ⁢           ⁢   d         )     *     α   b                     =       α   d     +       (     1   -     α   d       )     *     α   c       +       (     1   -     α   d       )     *     (     1   -     α   c       )     *     α   b                       (   21   )             
 
         [0079]     Further, the multiplier  52   1  multiplies an output value of the multiplier  51   1  by the pixel value C b  of the image B to output the multiplied value. The adder  55   1  adds an output value of the multiplier  52   1  and the alpha-multiplied pixel value α cd C cd  output from the alpha blending computing unit  10  to output the added value. An output value of the adder  55   1  becomes an alpha-multiplied pixel value α bcd C bcd  to be output from the alpha blending computing unit  50   1 . The alpha-multiplied pixel value α bcd C bcd  is expressed by Expression (22) below.  
                       α   bcd     ⁢     C   bcd       =       ⁢         α     c   ⁢           ⁢   d       *     C     c   ⁢           ⁢   d         +       (     1   -     α     c   ⁢           ⁢   d         )     *     α   b     ⁢     C   b                     =       ⁢         α   d     *     C   d       +       (     1   -     α   d       )     *     α   c     *     C   c       +       (     1   -     α   d       )     *                       ⁢       (     1   -     α   c       )     *     α   b     *     C   b                     (   22   )             
 
         [0080]     On the other hand, the alpha blending computing unit  50   2  connected in tandem with the alpha blending computing unit  50   1  has the same configuration as that of the alpha blending computing unit  50   1 . Further, the alpha blending computing unit  50   2  receives, as the alpha value α and pixel value C corresponding to one input image, the alpha value α a  and pixel value C a  of the image A. Further, the alpha blending computing unit  50   2  receives, as the alpha value α and alpha-multiplied pixel value αC corresponding to the other input image, the alpha value α bcd  and alpha-multiplied pixel value α bcd C bcd  output from the alpha blending computing unit  50   1 . The alpha blending computing unit  50   2  outputs, based on the input values, the alpha value α abcd  and alpha-multiplied pixel value α abcd C abcd . The alpha value α abcd  and alpha-multiplied pixel value α abcd C abcd  are expressed by Expressions (23) and (24) below.  
                     α   abcd     =       ⁢       α   bcd     +       (     1   -     α   bcd       )     *     α   a                     =       ⁢       α   d     +       (     1   -     α   d       )     *     α   c       +       (     1   -     α   d       )     *     (     1   -     α   c       )     *     α   b       +                     ⁢       (     1   -     α   d       )     *     (     1   -     α   c       )     *     (     1   -     α   b       )     *     α   a                     (   23   )                         α   abcd     ⁢     C   abcd       =       ⁢         α   bcd     *     C   bcd       +       (     1   -     α   bcd       )     *     α   a     ⁢     C   a                     =       ⁢         α   d     *     C   d       +       (     1   -     α   d       )     *     α   c     *     C   c       +       (     1   -     α   d       )     *                       ⁢         (     1   -     α   c       )     *     C   b       +       (     1   -     α   d       )     *     (     1   -     α   c       )     *     (     1   -     α   b       )     *                       ⁢       α   a     *     C   a                     (   24   )             
 
         [0081]     As apparent from the Expressions (23) and (24), in this embodiment as well, the alpha value α abcd  and alpha-multiplied pixel value α abcd C abcd  output from the alpha blending computing unit  50   2  at the last stage are similar to those of the first embodiment. That is, according to this embodiment, even if images are rearranged and then synthesized, the images can be synthesized in the same way as the first embodiment.  
         [0082]     Further,  FIG. 6  shows another example of this embodiment. An image synthesizer  4 ′ of  FIG. 6  changes the image synthesizer  4  like the change of the image synthesizer  1  to the image synthesizer  3 .  
       Fifth Embodiment  
       [0083]      FIG. 7  is a block diagram of an image synthesizer  5  according to a fifth embodiment of the present invention. The image synthesizer  5  of the fifth embodiment includes first and second selectors (for example, selector  37   1  and  37   2 ) in addition to the components of the image synthesizer  1  of the first embodiment. The selector  37   1  receives alpha values α output from the alpha blending computing units, selects any one of the alpha values, and outputs the selected one as an alpha value α out . Further, the selector  37   2  receives alpha-multiplied pixel values α C  from the alpha blending computing units, selects any one of the alpha-multiplied pixel values, and outputs the selected one as an alpha-multiplied pixel value α out C out . Here, there is a correspondence between the alpha value output from the selector  37   1  and the alpha-multiplied pixel value selected with the selector  37   2 .  
         [0084]     An output value of the selectors  37   1  and  37   2  is input to the divider  31 . The divider  31  divides the alpha-multiplied pixel value α out C out  output from the selector  37   2  by the value α out  output from the selector  37   1 . Thus, the divider  31  generates a pixel value C out  of the composite image to be output from the image synthesizer  5 . Further, the alpha value α out  output from the selector  37   1  becomes an alpha value α out  to be output from the image synthesizer  5  as it is.  
         [0085]     As understood from the above description, the image synthesizer  5  of the fifth embodiment can select a desired output value of the alpha blending computing units in accordance with the number of images to synthesize even if the number of images to synthesize is changed. Thus, even if the number of images to synthesize is changed, one image synthesizer  5  can output an appropriate value.  
       Sixth Embodiment  
       [0086]      FIG. 8  is a block diagram of an image synthesizer  6  according to a sixth embodiment of the present invention. The image synthesizer  6  of the sixth embodiment includes a third selector (for example, selector  38 ) at the output of the image synthesizer  1  of the first embodiment. The selector  38  receives the pixel value C abcd  of the composite image output from the divider  31  and the alpha-multiplied pixel value α abcd C abcd  output from the alpha blending computing unit  20   2 . The selector  38  selects one of the received output values to output the selected one.  
         [0087]     As a result, the image synthesizer  6  of the sixth embodiment can select one of the pixel value C abcd  and alpha-multiplied pixel value α abcd C abcd  as an output value. Hence, the image synthesizer  6  can select and output a desired value in accordance with a function of a block connected to its output. That is, the image synthesizer  6  can enhance the flexibility of a system including the image synthesizer  6 .  
         [0088]     Further,  FIG. 9  shows another example of the sixth embodiment. The image synthesizer  6 ′ of  FIG. 9  includes a third selector (for example, selector  39 ) selecting an alpha value to be input to the divider  31 . The selector  39  receives the value “1” and the alpha value α abcd  output from the alpha blending computing unit  20   2 . The selector  39  selects and outputs one of the input values.  
         [0089]     Here, if the selector  39  selects the alpha value α abcd , the alpha value α abcd  is input to the divider  31 , so the divider  31  outputs the pixel value C abcd  of the composite image. Further, if the selector  39  selects the value “1”, the divider  31  receives the value “1”, so the divider  31  outputs the alpha-multiplied pixel value α abcd C abcd  of the composite image. That is, the image synthesizer  6 ′ can also select and output a desired value similar to the image synthesizer  6 .  
       Seventh Embodiment  
       [0090]      FIG. 10  is a block diagram of an image synthesizer  7  according to a seventh embodiment of the present invention. As shown in  FIG. 10 , the image synthesizer  7  of the seventh embodiment additionally includes a fourth selector inside the alpha blending computing unit of the image synthesizer  1  of the first embodiment. The alpha blending computing unit of this embodiment can thereby deal with the case where the pixel value or alpha-multiplied pixel value is input as image information.  
         [0091]     The second computing unit of the image synthesizer  7  (for example, alpha blending computing unit  70 ) includes two fourth selectors (for example, selectors  71  and  72 ) in addition to the components of the second computing unit (for example, alpha blending computing unit  10 ) of the image synthesizer  1 . Further, the first computing unit of the image synthesizer  7  (for example, alpha blending computing units  80   1  and  80   2 ) includes the fourth selectors (for example, selectors  81   1  and  81   2 ) in addition to the components of the first computing unit of the image synthesizer  1  (for example, alpha blending computing units  20   1  and  20   2 ).  
         [0092]     How to connect the selectors  71  and  72  additionally provided in the alpha blending computing unit  70  is described next. The selector  71  includes input terminals i 1  and i 2 , and selects and outputs one of values input to the input terminals i 1  and i 2 . The input terminal i 1  of the selector  71  is connected with an output of the multiplier  13 , and the input terminal i 2  receives the pixel value C or alpha-multiplied pixel value αC corresponding to the other input image. The selector  72  includes input terminals i 1  and i 2 , and selects and outputs one of values input to the input terminals i 1  and i 2 . The input terminal i 1  of the selector  72  is connected with an output of the multiplier  11 , and the input terminal i 2  is connected with an output of the subtractor  14 . If the selectors  71  and  72  select the value input to the input terminal i 1 , the connection form of the alpha blending computing unit  70  is the same as that of the alpha blending computing unit  10  of the first embodiment, and similar computation is carried out. On the other hand, if the selectors  71  and  72  select the value input to the input terminal i 2 , the connection form similar to the alpha blending computing units  80   1  and  80   2  as described below is adopted, and computation is carried out similarly thereto. That is, the alpha blending computing unit  70  can select a function of the first computing unit or the second computing unit.  
         [0093]     How to connect the selector  81   1  added to the alpha blending computing unit  80   1  is described next. The selector  81   1  includes input terminals i 1  and i 2 , and selects and outputs one of values input to the input terminals i 1  and i 2 . The input terminal i 1  of the selector  81   1  is connected with an output of the multiplier  23   1 , and the input terminal i 2  receives the pixel value C or alpha-multiplied pixel value αC corresponding to the other input image. If the selector  81   1  selects the value input to the input terminal i 1 , the connection form of the alpha blending computing unit  80   1  is the same as that of the alpha blending computing unit  20   1  of the first embodiment, and similar computation is carried out. On the other hand, if the selector  81   1  selects the value input to the input terminal i 2 , the input alpha-multiplied pixel value αC and the alpha value α corresponding to the alpha-multiplied pixel value αC are not multiplied. Here, the connection form of the selector  81   2  added to the alpha blending computing unit  80   2  is the same as that of the selector  81   1  added to the alpha blending computing unit  80   1 , so its description is omitted here.  
         [0094]     Operations of the image synthesizer  7  of the seventh embodiment are described next. First, similar to the image synthesizer  1  of the first embodiment, the case where the alpha value α and pixel value C are input as input image information is described. In this case, the selectors  71  and  72 , and selectors  81   1  and  81   2  select the input terminal i 1 . Thus, the internal connection form of each alpha blending computing unit becomes the same as that of the alpha blending computing unit of the image synthesizer  1 . Accordingly, an output value of the image synthesizer  7  is similar to that of the image synthesizer  1 .  
         [0095]     Meanwhile, the case where alpha value α and alpha-multiplied pixel value αC are input as the input image information is described. In this case, the selectors  71  and  72 , and selectors  81   1  and  81   2  select the input terminal i 2 . Thus, the alpha blending computing units are connected not to multiply the input alpha-multiplied pixel value αC by the alpha value α corresponding to the alpha-multiplied pixel value αC. Accordingly, an output value of the alpha blending computing unit  70  is expressed by Expressions (25) and (26), an output value of the alpha blending computing unit  80   1  is expressed by Expressions (27) and (28), and an output value of the alpha blending computing unit  80   2  is expressed by Expressions (29) and (30).  
               α   ab     =       α   b     +       (     1   -     α   b       )     *     α   a                 (   25   )                   α   ab     ⁢     C   ab       =         α   b     ⁢     C   b       +       (     1   -     α   b       )     *     α   a     ⁢     C   a                 (   26   )                       α   abc     =       ⁢       α   c     +       (     1   -     α   c       )     *     α   ab                     =       ⁢       α   c     +       (     1   -     α   c       )     *     α   c       +       (     1   -     α   c       )     *     (     1   -     α   b       )     *     α   a                       (   27   )                         α   abc     ⁢     C   abc       =       ⁢         α   c     ⁢     C   c       +       (     1   -     α   c       )     *     α   ab     ⁢     C   ab                     =       ⁢         α   c     ⁢     C   c       +       (     1   -     α   c       )     *     α   b     ⁢     C   b       +       (     1   -     α   c       )     *     (     1   -     α   b       )     *     α   a     ⁢     C   a                       (   28   )                       α   abcd     =       ⁢       α   d     +       (     1   -     α   d       )     *     α   abc                     =       ⁢       α   d     +       (     1   -     α   d       )     *     α   c       +       (     1   -     α   d       )     *     (     1   -     α   c       )     *     α   ab                     =       ⁢       α   d     +       (     1   -     α   d       )     *     α   c       +       (     1   -     α   d       )     *     (     1   -     α   c       )     *     α   b       +                     ⁢       (     1   -     α   d       )     *     (     1   -     α   c       )     *     (     1   -     α   b       )     *     α   a                     (   29   )                         α   abcd     ⁢     C   abcd       =       ⁢         α   d     ⁢     C   d       +       (     1   -     α   d       )     *     α   abc     ⁢     C   abc                     =       ⁢         α   d     ⁢     C   d       +       (     1   -     α   d       )     *     α   c     ⁢     C   c       +       (     1   -     α   d       )     *     (     1   -     α   c       )     *                       ⁢       α   ab     ⁢     C   ab                   =       ⁢         α   d     ⁢     C   d       +       (     1   -     α   d       )     *     α   c     ⁢     C   c       +       (     1   -     α   d       )     *     (     1   -     α   c       )     *                       ⁢         α   b     ⁢     C   b       +       (     1   -     α   d       )     *     (     1   -     α   c       )     *     (     1   -     α   b       )     *     α   a     ⁢     C   a                       (   30   )             
 
         [0096]     The values derived from the Expressions (29) and (30) become the same as the alpha value α abcd  and alpha-multiplied pixel value α abcd C abcd  output from the alpha blending computing unit  20   2  of the first embodiment. Accordingly, the image synthesizer  7  of the seventh embodiment can obtain a value similar to the image synthesizer  1  of the first embodiment even if the alpha value α and alpha-multiplied pixel value αC are input as input image information.  
         [0097]     As understood from the above description, according to the image synthesizer  7  of the seventh embodiment, even if the alpha-multiplied pixel value is input as an input image pixel value, the computational result similar to that of the first embodiment can be obtained. Further, even if the input image pixel value C is input like the first embodiment, the selector changes the internal connection form of the alpha blending computing unit to thereby obtain the output value similar to the first embodiment. That is, the image synthesizer  7  of the seventh embodiment selects a desired internal connection form of the alpha blending computing unit with the selector additionally provided inside the alpha blending computing unit to obtain the output value similar to the first embodiment regardless of input information.  
       Eighth Embodiment  
       [0098]     An image synthesizer  8  according to an eighth embodiment of the present invention executes computation of the image synthesizer  1  of the first embodiment by use of a general-purpose computer such as a CPU (Central Processing Unit).  FIG. 11  is a block diagram of the image synthesizer  8 . As shown in  FIG. 11 , the image synthesizer  8  includes an image input unit  91 , a CPU unit  92 , an image output unit  93 , and a memory  94 . Further, the image input unit  91 , the CPU unit  92 , the image output unit  93 , and the memory  94  transmit/receive data through a data bus  95 .  
         [0099]     The image input unit  91  receives input image information and transmits the information to the memory  94  through the data bus  95 . The CPU unit  92  synthesizes images based on the computation of the image synthesizer  1 . The image output unit  93  outputs the image synthesized with the CPU unit  92  to, for example, a display device (not shown). The memory  94  stores information about the input images or composite image.  
         [0100]      FIG. 12  is a flowchart of the computation executed with the CPU unit  92 . Referring to  FIG. 12 , the computation of the CPU unit  92  is described next. Here, the pixel number of each of the images to synthesize is represented by i, and the image number is represented by j.  
         [0101]     When image synthesis is started, the CPU unit  92  first initializes the pixel number i to 1 (step S 1 ). Further, the image number j is initialized to 1 (step S 2 ). Subsequently, an i-th pixel of a j-th image and an i-th pixel of a (j+1)th image are synthesized. Then, a second synthesizing step of calculating the alpha value α out [i] and the alpha-multiplied pixel value α out C out [i] of the i-th pixel obtained by synthesizing the j-th image and the (j+1)th image is executed (step S 3 ). Here, the calculation in step S 3  corresponds to the computation of the alpha blending computing unit  10  of the first embodiment. The calculation in step S 3  is expressed by Expressions (31) and (32). 
 
α out   [i]=α   j+1   [i ]+(1−α j+1   [i ])*α j   [i]   (31) 
 
α out   C   out   [i]=α   j+1   [i]*C   j+1   [i ]+(1−α j+1   [i ])*α j   [i]*C   j   [i]   (32) 
 
         [0102]     Subsequently, information on a (j+2)th image is read (step S 4 ). At this time, the alpha value α out [i] and alpha-multiplied pixel value α out C out [i] obtained in step S 3  are stored as an alpha value α DST  and a pixel value C DST . Further, the alpha value α j [i] and pixel value C j [i] of the (j+2)th image obtained in step S 4  are stored as an alpha value α SRC  and a pixel value C SRC  (step S 5 ). Next, based on the alpha value α DST  and pixel value C DST , and the alpha value α SRC  and pixel value C SRC , a first synthesizing step of calculating an alpha value α out [i] and alpha-multiplied pixel value α out C out [i] is carried out (step S 6 ). Here, the calculation of alpha value α out [i] and alpha-multiplied pixel value α out C out [i] in step S 6  corresponds to the computation of the alpha blending computing unit  20   1  of the first embodiment. The calculation in step S 6  is expressed by Expressions (33) and (34). 
 
α out   [i]=α   SRC +(1−α SRC )*α DST   (33) 
 
α out   C   out   [i]—α   SRC   *C   SRC +(1−α SRC )*α DST   *C   DST   (34) 
 
         [0103]     After the completion of the calculation in step S 6 , it is determine whether or not images remain to be synthesized (step S 7 ). If it is determined that images remain to be synthesized in step S 7 , the next image is read under the condition that j=j+1 (step S 8 ), and the processings of steps S 5  and S 6  are repeated The alpha value α out [i] and alpha-multiplied pixel value α out C out [i] calculated in these steps correspond to the values computed with the alpha blending computing unit  20   2  of the first embodiment. On the other hand, if there is no unsynthesized image, a dividing step of calculating a pixel value C out  of a composite image to be output based on the calculation result in step S 6  is executed (step S 9 ). The calculation in step S 9  corresponds to the computation of the divider  31  of the first embodiment. The computation is expressed by Expression (35). 
 
 C   out   [i]=α   out   C   out   [i]/α   out[i]   (35) 
 
         [0104]     Subsequently, it is determine whether or not pixels remain to be synthesized (step S 10 ). If it is determined that pixels remain to be synthesized in step S 10 , the next pixel is read under the condition that i=i+1, and the processings of steps S 2  to S 9  are repeated (step S 11 ). On the other hand, if there is no unsynthesized pixel, the synthesizing processing is completed.  
         [0105]     As understood from the above description, according to the image synthesizer  8  of the eighth embodiment, the processing executed with the alpha blending computing unit in the above embodiments can be carried out with a general-purpose computing unit such as a CPU.  
         [0106]     Here, image synthesizing processing of a conventional alpha blending computing unit can be carried out with a general-purpose computing unit such as a CPU. However, the conventional alpha blending computing unit requires one divider for an output value of one alpha blending computing unit, so if the above processing is carried out with a general-purpose computing unit, the division takes more time to execute than the other computation, leading to a problem that images cannot be synthesized at high speeds.  
         [0107]     In contrast, the image synthesizing processing of the eighth embodiment only needs to execute the division once after all images are synthesized. That is, the number of times the time-consuming division is executed is much smaller than the conventional one, so the image synthesizing processing can be performed at high speeds.  
         [0108]     Here, even if a general-purpose computing unit carries out the processings executed in the embodiments other than the first embodiment, the computation flow is appropriately changed under the condition that the multiplier  32  of the second embodiment executes a multiplying step, the first and second selectors of the fifth embodiment execute first and second selecting steps, the third selector of the sixth embodiment executes a third selecting step, and the fourth selector of the seventh embodiment executes a fourth selecting step to thereby perform the processings with the general-purpose computing unit.  
         [0109]     The above embodiments describe the example of synthesizing the four images. However, as another embodiment, for example, four or more images can be synthesized by changing the number of tandem-connected alpha blending computing units in accordance with the number of images to synthesize. Further, the above embodiments may be combined as appropriate.  
         [0110]     It is apparent that the present invention is not limited to the above embodiment that may be modified and changed without departing from the scope and spirit of the invention.