Abstract:
A packet output device for formatting serial data into packets and for transmitting resulting data packets includes a data packet generator for generating each data packet and for generating time data corresponding to the data packet, the time data defining an output time of the data packet, and a packet transmitting circuit for receiving the data packet and the corresponding time data and transmitting the data packet based on the corresponding time data.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a data transmitting device for formatting data into packets and transmitting the data packets. In particular, the present invention relates to a packet output device for reducing the load of a packet generator of the data transmitting device by adding transmission time data to the data packets. 
     2. Description of the Related Art 
     In digital data communication, data transmission is generally performed using a packet as a unit of data. An IEEE 1394 interface is one of such interfaces performing data communication using packets. The IEEE 1394 is a serial interface having a high data transmission rate for the next generation multimedia standardized by the IEEE (for example, refer to High Performance Serial Bus P1394/Draft 8.0 v2). At present, an IEEE 1394 interface has been developed for use in digital audio visual (AV) equipment. 
     The IEEE 1394 can transmit two types of packets, i.e., isochronous packets for transmitting data which requires real-time transfer and asynchronous packets for transmitting data which does not require the real-time transfer. For example, digital audio visual (AV) data is communicated in the isochronous transfer mode using common isochronous packets. 
     In order to determine a buffer size for transmitting and receiving data requiring real-time transfer, it is necessary to determine a packet transmission timing, i.e., a maximum delay time permitted for the transmission. In the case of transmitting AV data using the IEEE 1394 interface as well, such transmission timing is determined by a range of the permitting time period in which each packet can be transmitted. 
     In general, in a packet output device, one packet per predetermined unit time which is referred to as a cycle is output to a transmitting path in an isochronous transfer mode based on the IEEE 1394 standard. For example, when a data rate is 28.8 Mbps, 250 data packets and 16 to 17 vacant packets are output for 1/30 second. Each data packet contains 480 bytes of data, and each vacant packet contains no data. The generated packets (data packets and vacant packets) are output from the packet output device. 
     A conventional packet output device 300 and operations thereof will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram showing a basic structure of the conventional packet output device 300. The packet output device 300 includes a packet generator 31, a packet transmitting circuit 32 and a clock signal generator 33. 
     The clock signal generator 33 outputs, for example, a clock signal having a predetermined cycle, which defines clock time for the system of the packet output device 300. The packet generator 31 generates, for example, one data packet or vacant packet per 125 μs (8 kHz) based on the clock time which is defined by the clock signal output from the clock signal generator 33. The packet generator 31 outputs the generated packets to the packet transmitting circuit 32. The packet transmitting circuit 32 receives the packets and then outputs the packets to the transmitting path 34 in accordance with a predetermined transmission cycle C. 
     FIG. 2 is a timing chart showing an exemplary packet arrangement on the transmitting path 34. As shown in FIG. 2, a time period of each transmission cycle C is 10 t, where t is a predetermined unit of time (e.g., one cycle of a clock signal). In FIG. 2, each cycle C is shown as cycle C j  (j=1, 2, 3, . . . .), and each cycle C j  starts from a time (10×j)t. The transmitting path 34 is typically shared with another device such as a terminal, and it is assumed that the transmitting path 34 is busy from cycles C 3  to C 5  because of the transmission of data from the other device, as shown in FIG. 2. 
     The packet generator 31 generates one data packet P i  (i=1, 2, 3, . . . ) every time period of 16 t, i.e., time width 16 t. Each generated packet P i  can be transmitted within a time width 13 t to the transmitting path 34 via the packet transmitting circuit 32. For example, the first data packet P 1  is required to be output from the packet transmitting circuit 32 to the transmitting path 34 during a time period from the time 16 t to the time 29 t. Accordingly, the data packet P 1  is output in the cycle C 2  which is available in this time period. Accordingly the output of the data packet P 1  starts at time 20 t. 
     Similarly, the second data packet P 2  (indicated by a broken line in FIG. 2) is required to be output to the transmitting path 34 during a time period from time 23 t to time 45 t. At this time , a cycle C 4  starts at time 40 t, and therefore the data packet P 2  is output in cycle C 4 . However, the transmitting path 34 is busy for transmitting data from the other device during cycle C 4 . Thus, the packet P 2  cannot be transferred and thus is abandoned. Since there is no data packet to be transmitted in the previous cycle C 3 , a vacant packet V 2  is generated in the packet generator 31 and it output to the transmitting path 34. 
     The third data packet P 3  is to be output to the transmitting path 34 during a time period from time 48 t to time 61 t. Accordingly, the data packet P 3  can be output in cycles C 5  and C 6  which start at time 50 t and 60 t, respectively. However, as shown in FIG. 2, since the transmitting path 34 is busy during cycle C 5 , the data packet P 3  is output in the available cycle C 6 . 
     The fourth data packet P 4  is to be output to the transmitting path 34 during a time period from time 64 t to time 77 t. During this time, an available cycle C 7  starts at time 70 t, and therefore the data packet P 4  is output in cycle C 7 . In a cycle C 8 , since there is no data packet to be transmitted, a vacant packet V 3  is generated and output to the transmitting path 34. 
     The fifth data packet P 5  is to be output to the transmitting path 34 during a time period from time 80 t to time 93 t. Accordingly, the data packet P 5  can be output in cycles C 8  and C 9  which start at times 80 t and 90 t, respectively. Since cycle C 8  is occupied by the vacant packet V 3 , the data packet P 5  is output in cycle C 9 . 
     In the conventional packet device 300, as described above, the packet generator 31 generates the data packets P i  (i=1, 2, 3, . . . . ), or vacant packets V k  (k=1, 2, 3,, . . . . ) in the case there is no data to be transmitted, for output to the packet transmitting circuit 32 at a time (10×j)t at which each cycle C j  starts. Accordingly, the packet generator 31 is required to generate and transmit the packets in accordance with the transmission cycle C j . The packet generator must generate and transmit the packets to the transmitting path 34, based on the clock time defined by the clock signal generated from the clock signal generator 33. For this reason, the packet generator 31 is required to constantly monitor the clock time and perform predetermined operations for each transmission cycle C j , i.e., the packet generator 31 should perform a timing control on the order of μsec. This increases the load on the packet generator 31. For example, when the packet generator 31 is implemented using a microcomputer, it is necessary for the microcomputer to constantly monitor the clock time, thus reducing the time available for executing other tasks for operation processes. 
     SUMMARY OF THE INVENTION 
     A packet output device according to the present invention for formatting serial data into packets and for transmitting resulting data packets includes a data packet generator for generating each data packet and for generating time data corresponding to the data packet, the time data defining an output time of the data packet; and a packet transmitting circuit for receiving the data packet and the corresponding time data and transmitting the data packet based on the corresponding time data. 
     According to another aspect of the invention, a packet output device for formatting serial data into packets and for transmitting resulting data packets includes a clock signal generator for generating a clock signal defining clock time; a data packet generator for generating each data packet and for generating time data corresponding to the data packet, the time data defining an output time of the data packet based on the clock time; and a packet transmitting circuit for receiving the data packet and the corresponding time data and for transmitting the data packet based on the corresponding time data in accordance with the clock time. 
     In one embodiment of the invention, the time data generated by the data packet generator includes a transmission start time before which the corresponding data packet is prevented from being transmitted, and a transmission end time after which the corresponding data packet is prevented from being transmitted. The packet transmitting circuit compares the clock time with the transmission start time and the transmission end time of the time data, in a case where the clock time is before the transmission start time, a vacant packet for indicating absence of data to be transmitted is output, and in a case where the clock time is between the transmission start time and the transmission end time, the data packet is output. 
     In another embodiment of the invention, the time data generated by the data packet generator includes a transmission start time before which the corresponding data packet is prevented from being transmitted, and a transmission time width starting from the transmission start time during which the corresponding data packet can be transmitted. The packet transmitting circuit compares the clock time with the transmission start time and the transmission time width of the time data, in a case where the clock time is before the transmission start time, a vacant packet for indicating absence of data to be transmitted is output, and in a case where the clock time is between the transmission start time and a time which is obtained by adding the transmission time width to the transmission start time, the data packet is output. 
     In still another embodiment of the invention, the packet transmitting circuit includes a vacant packet generator for generating a vacant packet for indicating absence of data to be transmitted; a packet selector for receiving a data packet generated in the data packet generator and a vacant packet generated in the vacant packet generator, and selecting either one of the data packet or the vacant packet in accordance with the time data of the corresponding data packet and the clock time; and a transmitting circuit for transmitting a packet selected by the packet selecting means. 
     In yet another embodiment of the invention, the time data generated by the data packet generator includes a transmission start time before which the corresponding data packet is prevented from being transmitted, and a transmission end time after which the corresponding data packet is prevented from being transmitted. The packet selecting means compares the clock time with the transmission start time and the transmission end time of the time date, in a case where the clock time is before the transmission start time, a vacant packet for showing absence of data to be transmitted is output, and in a case where the clock time is between the transmission start time and the transmission end time ,the data packet is output to the transmitting circuit. 
     In another embodiment of the invention, the time data generated by the data packet generator includes a transmission start time before which the corresponding data packet is prevented from being transmitted, and a transmission time width starting from the transmission start time during which the corresponding data packet can be transmitted. The packet transmitting circuit compares the clock time with the transmission start time and the transmission time width of the time data, in a case where the clock time is before the transmission start time, a vacant packet for indicating absence of data to be transmitted is output, and in a case where the clock time is between the transmission start time and a time which is obtained by adding the transmission time width to the transmission start time, the data packet is output to the transmitting circuit. 
     In still another embodiment of the invention, the packet transmitting circuit includes a packet storage circuit for temporarily storing the data packet and the corresponding time data output from the data packet generator; a vacant packet generator for generating a vacant packet for showing absence of data to be transmitted; a packet selector for receiving a data packet stored in the packet storage circuit and a vacant packet generated in the vacant packet generator, and selecting either one of the data packet and the vacant packet in accordance with the time data of the data packet stored in the packet storage circuit and the clock time; and a transmitting circuit for transmitting a packet selected by the packet selector. 
     In yet another embodiment of the invention, the time data generated by the data packet generator includes a transmission start time before which the corresponding data packet is prevented from being transmitted, and a transmission end time after which the corresponding data packet is prevented from being transmitted; and the packet selecting means compares the clock time with the transmission start time and the transmission end time of the corresponding time data of the data packet stored in the storage means. In a case where the clock time is before the transmission start time, the vacant packet is output. In a case where the clock time is between the transmission start time and the transmission end time, the data packet is output to the transmitting circuit and further the data packet and the corresponding time data are deleted from the storage circuit. In a case where the clock time is past the transmission end time, the data packet and the corresponding time data are deleted from the storage means and the vacant packet is output. 
     In another embodiment of the invention, the time data generated by the data packet generator includes a transmission start time before which the corresponding data packet is not permitted to be transmitted, and a transmission time width starting from the transmission start time during which the corresponding data packet can be transmitted; and the packet transmitting circuit compares the clock time with the transmission start time and the transmission time width of the time data of the data packet stored in the storage means. In a case where the clock time is before the transmission start time, the vacant packet is output. In a case where the clock time is between the transmission start time and a time which is obtained by adding the transmission time width to the transmission start time, the data packet is output to the transmitting circuit, and further the data packet and the corresponding time data are deleted from the storage means. In a case where the clock time is past a time which is obtained by adding the transmission time width to the transmission start time, the data packet and the corresponding time data are deleted from the storage circuit and the vacant packet is output. 
     According to another aspect of the invention, a packet output method for formatting serial data into packets and transmitting resulting data packets includes the steps of: generating each data packet and time data corresponding to the data packet for defining output time of the data packet; and receiving the data packet and the corresponding time data and transmitting the data packet based on the time data. 
     According to another aspect of the invention, a packet output method for formatting serial data into packets and transmitting resulting data packets includes the steps of: generating a clock signal defining clock time; generating a data packet and time data corresponding to the data packet for defining an output time of the data packet based on the clock time; and transmitting the data packet based on the time data and the clock time. 
     In one embodiment of the invention, the time data includes a transmission start time before which the corresponding data packet is not permitted to be transmitted, and a transmission end time after which the corresponding data packet is not permitted to be transmitted. The packet transmitting step includes the steps of: comparing the clock time with the transmission start time and the transmission end time of the time data; outputting a vacant packet for showing absence of data to be transmitted in a case where the clock time is before the transmission start time; and outputting the data packet in a case where the clock time is past the transmission start time and before the transmission end time. 
     In another embodiment of the invention, the time data includes a transmission start time before which the corresponding data packet is prevented from being transmitted, and a transmission time width starting from the transmission start time during which the corresponding data packet can be transmitted. The packet transmitting step includes the steps of: comparing the clock time with the transmission start time and the transmission time width of the time data; outputting a vacant packet for indicating absence of data to be transmitted in a case where the clock time is before the transmission start time; and outputting the data packet in a case where the clock time is past the transmission start time and before a time obtained by adding the transmission time width to the transmission start time. 
     In still another embodiment of the invention, the packet transmitting step includes the steps of: generating a vacant packet for indicating absence of data to be transmitted; selecting either one of the data packet and the vacant packet in accordance with the time data of the data packet and the clock time; and transmitting the selected packet. 
     In yet another embodiment of the invention, the time data includes a transmission start time before which the corresponding data packet is prevented from being transmitted, and a transmission end time after which the corresponding data packet is not permitted to be transmitted. The step of selecting includes the steps of: comparing the clock time with the transmission start time and the transmission end time of the time data; outputting a vacant packet for indicating absence of data to be transmitted in a case where the clock time is before the transmission start time; and outputting the data packet in a case where the clock time is past the transmission start time and before the transmission end time. 
     In another embodiment of the invention, the time data includes a transmission start time before which the corresponding data packet is not permitted to be transmitted, and a transmission time width starting from the transmission start time during which the corresponding data packet can be transmitted. The step of selecting includes the steps of: comparing the clock time with the transmission start time and the transmission time width of the time data; outputting a vacant packet for showing absence of data to be transmitted in a case where the clock time is before the transmission start time; and outputting the data packet in a case where the clock time is between the transmission start time and a time which is obtained by adding the transmission time width to the transmission start time. 
     In still another embodiment of the invention, the packet transmitting step includes the steps of: temporarily holding the data packet generated in the data packet generating step and the corresponding time data; generating a vacant packet for indicating absence of data to be transmitted; selecting either one of the stored data packet and the vacant packet in accordance with the time data of the stored data packet and the clock time; and transmitting the selected packet. 
     In yet another embodiment of the invention, the time data generated includes a transmission start time before which the corresponding data packet is prevented from being transmitted, and a transmission end time after which the corresponding data packet is prevented from being transmitted. The packet selecting step includes the steps of: comparing the clock time with the transmission start time and the transmission end time of the time data of the stored data packet; outputting the vacant packet in a case where the clock time is before the transmission start time; outputting the data packet to the transmitting circuit, and further deleting the data packet and the corresponding time data from the storage circuit in a case where the clock time is past the transmission start time and before the transmission end time; and deleting the data packet and the corresponding time data which have been held in the holding step in a case where the clock time is past the transmission end time. 
     In another embodiment of the invention, the time data includes a transmission start time before which the corresponding data packet is not permitted to be transmitted, and a transmission time width starting from the transmission start time during which the corresponding data packet can be transmitted. The packet selecting step comprising the steps of: comparing the clock time with the transmission start time and the transmission time width of the time data of the stored data packet; outputting the vacant packet in a case where the clock time is before the transmission start time; outputting the data packet, and deleting the data packet and the corresponding time data which have been held in the holding step in a case where the clock time is between the transmission start time and a time which is obtained by adding the transmission time width to the transmission start time; and deleting the data packet and the corresponding time data which have been held in the holding step in a case where the clock time is past a time which is obtained by adding the transmission time width to the transmission start time. 
     Thus, the invention described herein makes possible the advantages of (1) providing a packet output device and a packet output method allowing a data packet generator to have a simple structure by making it unnecessary for the data packet generator to monitor the conditions of the transmitting path and the clock time, and (2) providing a packet output device and a packet output method for transmitting packets in accordance with the corresponding time data which is generated in the data packet generator and is added to the respective packets. 
     These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram illustrating an exemplary structure of a conventional packet output device. 
     FIG. 2 is a timing chart illustrating the operation of the conventional packet output device. 
     FIG. 3 is a block diagram illustrating a basic structure of a packet output device in Example 1 according to the present invention. 
     FIG. 4 is a timing chart illustrating the operations of a packet output device according to the present invention. 
     FIG. 5 is a table of exemplary transmission cycles in which packets are output to the transmitting path including a start time for each transmission cycle. 
     FIG. 6 is a table of an example of the time data (transmission start time and transmission end time) and the transmission cycles in which the corresponding data packets can be transmitted. 
     FIG. 7 is a table of another example of the time data (transmission start time and transmission time width) and the transmission cycles in which the corresponding data packets can be transmitted. 
     FIG. 8 is a block diagram illustrating a basic structure of a packet output device in Example 2 according to the present invention. 
     FIG. 9 is a block diagram illustrating a basic structure of a packet output device in Example 3 according to the present invention. 
     FIG. 10 is a block diagram illustrating a basic structure of a packet output device in Example 4 according to the present invention. 
     FIG. 11 is a block diagram illustrating a basic structure of a packet output device in Example 5 according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     EXAMPLE 1 
     A structure and an operation of a packet output device 100 according to Example 1 of the present invention will be described with reference to FIGS. 3 and 4. FIG. 3 schematically shows the basic structure of the packet output device 100 of Example 1. As shown in FIG. 3, the packet output device 100 includes a data packet generator 11, a packet transmitting circuit 12 and a clock signal generator 13. In the same manner as in the conventional clock signal generator 33, the clock signal generator 13 outputs, for example, a clock signal in a predetermined cycle. The clock time ST of the system of the packet output device 100 is defined by the clock signal. The clock signal (clock time ST) is supplied to both the data packet generator 11 and the packet transmitting circuit 12. 
     The data packet generator 11 generates data packets P i  (i=1, 2, 3, . . . . ) and time data TD i  for specifying the time at which the corresponding data packet P i  is output. The time data TD i  is generated based on the clock time ST which is defined by the clock signal generated by the clock signal generator 13. In addition, the data packet generator 11 outputs the generated data packet P i  and time data TD i  to the packet transmitting circuit 12. 
     The packet transmitting circuit 12 compares the time data TD i  with the clock time ST. When the clock time ST is within the time specified by the time data TD i , the data packet P i  corresponding to the time data TD i  is output to a transmitting path 14 in accordance with a cycle C j . When the clock time ST is not within the time specified by the time data TD i , a vacant packet V i  is generated and output to the transmitting path 14. 
     The time data TD i  includes; for example, a transmission start time t s  before which transmission of the corresponding packet is prevented from starting and a transmission end time t E  after which transmission of a packet is prevented from being performed. The packet transmitting circuit 12 compares the transmission start time t s  of the time data TD i  with the clock time ST for each transmission cycle C j . In the case where the clock time ST is later than the transmission start time t s , the data packet P i  corresponding to the time data TD i  is output to the transmitting path 14. In the case where the clock time ST goes by the transmission end time t E  without the data packet P i  being transmitted, such as in the case where the transmitting path is busy, the transmission of the data packet P i  is cancelled. When there is no data packet P i  to be transmitted in a transmission cycle C j , the vacant packet V k  is generated and output to the transmitting path 14. 
     FIG. 4 shows an exemplary arrangement of the packets output from the packet output device 100 to the transmitting path 14. FIG. 5 shows an example of cycles C j  (j=1, 2, 3, . . . ) in which the packets P i  (i=1, 2, 3, . . . . ) are output to the transmitting path 14 and includes a start time for each cycle C j . In this case, a time period of one cycle is 10 t as in the case of the conventional packet output device 300. 
     The data packet generator 11 generates the data packet P i  and the corresponding time data TD i  and outputs them to the packet transmitting circuit 12. As shown in FIG. 4, the time at which the data packet P i  is generated is not limited to a fixed cycle. Instead a data packet P i  may be generated at random time interval. FIG. 6 shows an example of the time data TD i  (transmission start time t s  and transmission end time t E ) and cycles C j  in which the corresponding data packet can be transmitted. 
     Next, the operations of the packet output circuit 100 will be more specifically described below. The data packet generator 11 generates the data packet P i  (the length of the data packet generation cycle may be arbitrary) and outputs the corresponding time data TD i  in addition to the generated data packet P i . In this example, the transmission start time t s  and the transmission end time t E  are specified for each data packet P i . 
     As shown in FIGS. 3 and 4, the data packet generator 11 generates a first data packet P 1  and the time data TD I  and outputs them to the packet transmitting circuit 12. The packet transmitting circuit 12 compares the time data TD 1  supplied from the data packet generator 11 with the clock time ST. Then, the packet transmitting circuit 12 outputs the data packet P 1  in a cycle C 2  which is a first cycle starting after the time t s  (=16 t) and ending before t E  (=29 t) among the transmission cycles C j . Next, the packet transmitting circuit 12 attempts to output the data packet P 2  in a cycle C 4  which is the first cycle starting after t s  )=32 t) and ending before t E  (=45 t) among the cycles C j , in accordance with the corresponding time data TD 2 . However, as shown in FIG. 4, since the transmitting path 14 is busy in cycle C 4 , the data packet P 2  is abandoned and not output to the transmitting path 14. 
     Similarly, the packet transmitting circuit 12 attempts to output the data packet P 3  during a cycle C 5  which starts after 48 t and ends before 61 t. However, since the transmitting path 14 is busy in a cycle C 5  as well as in cycle C 4 , the data packet P 3  is output in a next available cycle C 6  which starts before the time period specified by time data TD 3  ends. Similarly, the packet transmitting circuit 12 outputs the data packet P 4  in a cycle first starting after the time 64 t and ending before the time 77 t, cycle C 7 , and outputs the data packet P 5  in a cycle first starting after the time 80 t and ending before the time 93 t, cycle C 8 . In cycles C 1 , C 3  and C 9  where no data packet P i  is supplied to the packet transmitting circuit 12, and the transmitting path 14 is available, vacant packets V 1 , V 2  and V 3  are generated by the packet transmitting circuit 12 and are output to the transmitting path 14 (shown in FIG. 4). 
     As described above, the data packet generator 11 outputs the time data TD i  in addition to the data packet P i  so that it is possible to output the data packet P i  to the packet transmitting circuit 12 regardless of the transmission cycle C j  for outputting the generated packet P i  to the transmitting path 14. Thus, the load on the data packet generator 11 can be reduced. 
     In the packet output device 100 described above, the data packet generator 11 generates the transmission start time t s  and the transmission end time t E  as shown in FIG. 6 as the time data TD i  to output to the packet transmitting circuit 12. The time data TD i  is not limited to this example. Alternatively, for example, as shown in FIG. 7, the time data TD i  may include transmission start time t s  and a transmission time width t w  (=13 t) which represents the time period during which the transmission is allowed. In this case, the same effects can be obtained. For example, the packet transmitting circuit 12 receives the transmission start time t s  and the transmission time width t w  as the time data TD i  of the packet P i . The packet transmitting circuit 12 outputs the data packet P i  to the transmitting path 14 at a time after the transmission start time t s  of 16 t and before the time of 29 t which is a time width T w  of 13 t later than the transmission start time. Other packets P i  are output in the similar manner. 
     Thus, the data packet generator 11 outputs the time data TD i  in addition to the data packet P i  to the packet transmitting circuit 12, so that it is unnecessary for the data packet generator 1 to constantly monitor the clock time. As a result, the data packet generator 11 can be simplified and the load thereon can be reduced. 
     In this example, the data packet generator 11 generates the transmission start time t s  as one of the time data TD i . However, the cycle C j  in which the data packet P i  can be output may be determined by setting the transmission start time t s  as the time at which the data packet P i  is output from the data packet generator 11 (i.e., the permitted time period for outputting the data packet is set to be a predetermined time interval following the time at which the data packet is generated), and by identifying the transmission end time t E  or transmission time width t w . 
     EXAMPLE 2 
     A packet output device 110 according to Example 2 of the present invention will be described with reference to FIG. 8. FIG. 8 shows the basic structure of the packet output device 110 of Example 2. As shown in FIG. 8, the packet output device 110 includes a data packet generator 11a, a packet transmitting circuit 12a and a clock signal generator 13. The packet transmitting circuit 12a includes a vacant packet generator 113, a selector 114, a transmitting circuit 115 and a comparator 116. The clock signal generator 13 is the same as the conventional clock signal generator 33, as in the case of the packet output device 100 according to Example 1. The clock signal generator 13 outputs, for example, a clock signal for defining a clock time ST for the system of the packet output device 110. The clock time ST is supplied to the data packet generator 11a and the comparator 116 of the packet transmitting circuit 12a. 
     As shown in FIG. 8, the data packet generator 11a generates data packets P i  (i=1, 2, 3, . . . . ) and the corresponding time data TD i  (transmission start time t s  and transmission end time t E ) for identifying the time at which the data packet P i  will be output. As in Example 1, the time at which the data packet P i  is output depends on the clock time ST. The data packet P i  is supplied to the selector 114, and the transmission start time t s  data and the transmission end time t E  data are supplied to the comparator 116. 
     In the packet transmitting circuit 12a, the vacant packet generator 113 generates vacant packets V k  (k=1, 2, 3, . . . . ) each of which indicates the absence of data to be output to the selector 114. The selector 114 selectively outputs either one of the data packet P i  and the vacant packet V k  to the transmitting circuit 115, based on a control signal CS (described in detail later) supplied from the comparator 116. The transmitting circuit 115 outputs the data packet P i  or the vacant packet V k  input from the selector 114, to the transmitting path 14. In this example, the timing chart showing the packet arrangement on the transmitting path 14 is the same as that in FIG. 4. 
     The transmitting circuit 115 informs the comparator 116 of whether or not the packet can be output to the transmitting path 14 (i.e., whether of not the transmitting path 14 is busy) for each transmission cycle C j  by a signal BS. Signal BS may be, for example, a signal which is output only when the transmitting path 14 is available. 
     The comparator 116 generates a control signal CS based on the time data TD i  (the transmission start time t s  and the transmission end time t E ) input from the data packet generator 11a and the clock time ST defined by the clock signal input from the clock signal generator 13. The comparator 116 compares the transmission start time t s  and the transmission end time t E  with the clock time ST for each cycle C j . The control signal CS is supplied to the selector 114. 
     In the case where the clock time ST is later than the transmission start time t s  and earlier than the transmission end time t E , the comparator 116 determines that the data packet P i  should be selected. In the case where the result of the comparison is other than the above, the comparator 116 determines that the vacant packet V should be selected. When the signal BS supplied from the transmitting circuit 115 indicates that the transmitting path 14 is available (or not busy), the comparator 116 outputs a control signal CS to the selector 114 so that the data packet P i  or vacant packet V k  are selected in accordance with the decision, and the selected packet is output. When the signal BS supplied from the transmitting circuit 115 indicates that the transmitting path 14 is busy, the comparator 116 outputs the control signal CS to the selector 114 so as not to output either one of the packet from the selector 114. 
     More simply, for example, the signal BS may be supplied from the transmitting circuit 115 to the comparator 116 only when the transmitting path 14 is available, and the comparator 116 outputs control signal CS only when the comparator 116 receives the signal BS so as to specify either one of the data packet P i  or the vacant packet V k  to be output. In this case, the data packet P i  or the vacant packet V k  is output to the transmitting circuit 115 only when the selector 114 receives control signal CS. 
     As described above, the data packet generator 11a outputs the time data TD i  (transmission start time t s  the transmission end time t E ) in addition to the data packet P i  to the packet transmitting circuit 12a, so that it is unnecessary for the data packet generator 11a to constantly monitor the clock time. As a result, the data packet generator 11a can be simplified and the load thereon can be reduced. 
     In this example, the data packet generator 11a generates the transmission start time t s  as one of the time data TD i . However, the cycle C j  in which the data packet P i  can be output may be determined by setting the transmission start time t s  as the time at which the data packet P i  is output from the data packet generator 11a (i.e., the permitted time period for outputting the data packet is set as a predetermined time interval after the time at which the data packet is generated), and by identifying the transmission end time t E  or transmission time width t w . 
     EXAMPLE 3 
     A packet output device 120 according to Example 3 of the present invention will be described with reference to FIG. 9. FIG. 9 is a block diagram showing the basic structure of the packet output device 120 of Example 3. The same components bear the same reference numerals as in Example 2. As shown in FIG. 9, the packet output device 120 includes a data packet generator 11b, a packet transmitting circuit 12b and a clock signal generator 13. The packet transmitting circuit 12b includes a vacant packet generator 113, a selector 114, a transmitting circuit 115, a comparator 116 and an adder 119. The clock signal generator 13 is the same as the conventional clock signal generator 33, as in the case of the packet output devices according to Examples 1 and 2. The clock signal generator 13 outputs, for example, a clock signal for defining a clock time ST for the system of the packet output device 120. The clock time ST is supplied to the data packet generator 11b and the comparator 116 of the packet transmitting circuit 12b. 
     As shown in FIG. 9, the data packet generator 11b generates a data packet P i  (i=1, 2, 3, . . . . ) and corresponding time data TD i  (transmission start time t s  and transmission time width t w ) for specifying the time at which the data packet P i  will be output, based on the clock time ST. The data packet P i  is supplied to the selector 114 of the packet transmitting circuit 12b, and the transmission start time t s  is supplied to the comparator 116 and the adder 119. The transmission time width t w  is also supplied to the adder 119. 
     In the packet transmitting circuit 12b, the vacant packet generator 113 generates a vacant packet V k  (k=1, 2, 3, . . . . ), each of which indicates the absence of data to output to the selector 114. The adder 119 generates the transmission end time t k  by adding the transmission start time t s  and the transmission time width t w  supplied from the data packet generator 11b. The adder 119 outputs the generated transmission end time t E  to the comparator 116. 
     The selector 114 selectively outputs either one of the data packet P i  or the vacant packet V k  to the transmitting circuit 115, based on a control signal CS (described in detail later) supplied from the comparator 116. The transmitting circuit 115 outputs the data packet P i  or the vacant packet V k  input from the selector 114, to the transmitting path 14. In this example, the timing chart showing the packet arrangement on the transmitting path 14 is the same as that in FIG. 4. 
     The transmitting circuit 115 informs the comparator 116 whether or not the packet can be output to the transmitting path 14 (i.e., whether or not the transmitting path 14 is busy) for each transmission cycle C j  (by a signal BS). Signal BS can be, for example, a signal which is output only when the transmitting path 14 is not busy. 
     The comparator 116 generates the control signal CS based on the signal BS supplied from the transmitting circuit 115, the transmission start time t s  input from the data packet generator 11b, the transmission end time t E  input from adder 119 and the clock time ST input from the clock signal generator 13. 
     The comparator 116 compares the transmission start time t s  and the transmission end time t E  with the clock time ST for each cycle C j . In the case where the clock time ST is past the transmission start time t s , and the clock time ST is not past the transmission end time t E , the comparator 116 determines that the data packet P i  should be selected. In the case where the result of the comparison is other than the above, the comparator 116 determines that the vacant packet V k  should be selected. In the case where the signal BS supplied from the transmitting circuit 115 indicates that the transmitting path 14 is not busy, the comparator 116 outputs the control signal CS to the selector 114 so that the determined packet, the data packet P i  or the vacant packet V k , is selected and output. In the case where the signal BS supplied from the transmitting circuit 115 indicates that the transmitting path 14 is busy, the comparator 116 outputs the control signal CS to the selector 114 so that neither of the packets is output. 
     More simply, for example, only when the transmitting path 14 is not busy, is the signal BS input from the transmitting circuit 115 to the comparator 116, and only when the comparator 116 receives the signal BS, can the comparator 116 output the control signal CS for specifying either one of the data packet P i  or the vacant packet V k . In this case, only when the selector 114 receives the control signal CS, is the data packet P i  or the vacant packet V k  output to the transmitting circuit 115 in accordance with the control signal CS. 
     As described above, the data packet generator 11b outputs the time data TD i  (the transmission start time t s  and the transmission time width t w ) in addition to the data packet P i  to the packet transmitting circuit 12b, so that it is unnecessary for the data packet generator 11b to constantly monitor the clock time. As a result, the structure of the data packet generator 11b can be simplified, thus reducing the burden thereon. 
     In this example, the data packet generator 11b generates the transmission start time t s  as one of the time data TD i . However, by setting the time at which the data packet generator 11b outputs the data packet P i  as the transmission start time t s  (i.e., setting a predetermined time interval after the time at which the data packet is generated as a period of time during which a data packet can be output), and by specifying the transmission time width t w , the cycle C j  in which the data packet P i  can be output can be determined. Furthermore, in the case where the transmission time width t w  is a fixed value, it is unnecessary to calculate the transmission end time t E  for each cycle, once a value of the transmission time width t w  is set in the adder 119. 
     EXAMPLE 4 
     A packet output device 130 according to Example 4 of the present invention will be described with reference to FIG. 10. FIG. 10 is a block diagram showing the basic structure of the packet output device 130 of Example 4. The same components as in Example 2 bear the same reference numerals. As shown in FIG. 10, the packet output device 130 includes a data packet generator 11c, a packet transmitting circuit 12c and a clock signal generator 13. The packet transmitting circuit 12c includes a vacant packet generator 113, a selector 114, a transmitting circuit 115, a storage circuit 121 and a comparator 122. The clock signal generator 13 is the same as the conventional clock signal generator 33, as in the case of the packet output devices according to Examples 1 and 2. The clock signal generator 13 outputs, for example, a clock signal for defining a clock time ST for the system of the packet output device 130. The clock time ST is supplied to the data packet generator 11c and the comparator 122 of the packet transmitting circuit 12c. 
     As shown in FIG. 10, the data packet generator 11c generates a data packet P i  (i=1, 2, 3, . . . ) and time data TD i  (transmission start time t S  and transmission end time t E ) for specifying a time at which the data packet P i  will be output based on the clock time ST. The data packet P i , the transmission start time t S  and the transmission end time t E  are supplied to the storage circuit 121 of the packet transmitting circuit 12c. The storage circuit 121 stores the data packet P i , the transmission start time t S  and the transmission end time t E  input thereto. 
     The comparator 122 retrieves the transmission start time t S  and the transmission end time t E  of the oldest data packet P i  stored in the storage circuit 121, and determines which to output , the data packet P i  or a vacant packet V k  (k=1, 2, 3, . . . ), by comparing the transmission start time t S  and the transmission end time t E  with the clock time ST input from the clock signal generator 13. Based on this determination, the comparator 122 outputs a control signal CS 1  to control the selector 114 so that the selector 114 outputs the determined packet, the data packet P i  or the vacant packet V k , to the transmission circuit 115. 
     Furthermore, when the comparator 122 determines that the data packet P i  should be output, the comparator 122 simultaneously outputs a control signal CS 2  to the storage circuit 121 so that the storage circuit 121 outputs the corresponding data packet P i  to the selector 114. Furthermore, the vacant packet generator 113 generates a vacant packet V k  indicating the absence of data to output to the selector 114. 
     The selector 114 outputs either one of the data packet P i  or the vacant packet V k  to the transmitting circuit 115, in accordance with the determination of the comparator 122, based on control signal CS 1  supplied from the comparator 122. The transmitting circuit 115 outputs the data packet P i  or the vacant packet V k  input from the selector 114 to the transmitting path 14. Moreover, the transmitting circuit 115 informs the comparator 122 whether or not the packet can be output to the transmitting path 14 (i.e., whether or not the transmitting path 14 is busy) for each cycle C j  (by a signal BS). Signal BS can be, for example, a signal which is output only when the transmitting path 14 is not busy. 
     Next, the operation of the comparator 122 will be more specifically described. 
     The comparator 122 generates control signal CS 1  based on the signal BS supplied from the transmitting circuit 115, the transmission start time t S  and the transmission end time t E  input from the storage circuit 121, and the clock time ST input from the clock signal generator 13. The comparator 122 supplies the signal CS 1  to the selector 114. 
     When being informed that the transmitting path 14 is not busy by signal BS from the transmitting circuit 115, the comparator 122 compares the transmission start time t S  and the transmission end time t E  of the oldest data packet P i  stored in the storage circuit 121 with the clock time ST. In the case where the clock time ST is past the transmission start time t S , and the clock time ST is not past the transmission end time t E , the comparator 122 determines that the data packet P i  should be selected. Then, the comparator 122 outputs control signal CS 1  to the selector 114 so that the data packet P i  is selected. 
     At the same time, the comparator 122 outputs control signal CS 2  to the storage circuit 121 so that the storage circuit 121 outputs the data packet P i  to the selector 114, and relinquishes the previously output data packet P i  and the transmission start time t S  and the transmission end time t E  thereof. Accordingly, after the data packet P i  is output, the oldest packet in the storage circuit 121 is a data packet P i+1 . 
     In the case where the clock time ST is past the transmission end time t E  of the data packet P i , the comparator 122 outputs the control signal CS 1  to the selector 114 so that the vacant packet V k  is selected. In addition, the comparator 122 outputs the control signal CS 2  to the storage circuit 121 so that the storage circuit 121 relinquishes the data packet P i  and the time data (the transmission start time t S  and the transmission end time t E ) of the data packet P i . In the case where the clock time ST is before the transmission start time t S  of the data packet P i  (i.e., ST&lt;t S ), the comparator 122 only outputs the control signal CS 1  to the selector 114 so that the vacant packet V k  is selected. 
     As described above, when the transmitting path 14 is not busy, the selector 114 outputs the data packet P i  or the vacant packet V k  to the transmitting circuit 115 in accordance with the control signal CS 1  supplied from the comparator 122. 
     On the other hand, when the transmitting path 14 is busy (e.g., when signal BS is not output from the transmitting circuit 115), the comparator 122 signals the selector 114 such that neither the data packet P i  nor the vacant packet V k  is output from the selector 114. Therefore, in this example as well, the timing chart showing the packet arrangement on the transmitting path 14 is the same as that in FIG. 4. 
     As described above, the data packet generator 11c outputs the time data TD i  (transmission start time t S  and transmission end time t E ) in addition to the data packet P i  to the storage circuit 121 of the packet transmitting circuit 12c, to that it is possible for the data packet generator 11c to generate the data packet P i  regardless of the state of the transmitting path 14. Thus, the structure of the data packet generator 11c can be simplified, and the burden thereon can be reduced. Furthermore, for example, in the case where the packet generator 11c includes a computer or the like, it is unnecessary for the computer to monitor the state of the transmitting path 14 or the clock time ST, thus making it possible for the computer to perform other operations. 
     In this example, although the transmission start time t S  and the transmission end time t E  are generated as the time data TD i , even when either one of the transmission start time t S  or the transmission end time t E  is used, it is unnecessary for the data packet generator 11c to monitor the clock time ST, thus obtaining the same effect as in this example. 
     In this example, in the case where the clock time ST is past the transmission end time t E , the comparator 122 outputs control signal CS 1  to the selector 114 so that the vacant packet V k  is selected. Alternatively, in the case where the clock time ST is past the transmission end time t E , the following processing with respect to the data packet P i  can be performed. 
     With respect to the oldest data packet P i  in the storage circuit 121, when the clock time ST is past the transmission end time t E , the comparator 122 compares the transmission start time t S  and the transmission end time t E  of the second oldest data packet P i+1  with the clock time ST. In the case where the clock time ST is past the transmission start time t S  of the data packet P i+1 , and the clock time ST is not past the transmission end time t E  of the data packet P i+1 , the comparator 122 determines that the data packet P i+1  should be selected. Then, the comparator 122 outputs control signal CS 2  to the storage circuit 121 so that the storage circuit 121 outputs the data packet P i+1  to the selector 114, and the comparator 122 simultaneously outputs the control signal CS 1  to the selector 114 so that the selector 114 selects the data packet P i+1 . Thus, it is possible to enhance transmission efficiency of the data packet P i . 
     Furthermore, in this example, by comparing the time data TD i  of the oldest data packet P i  stored in the storage circuit 121 with the clock time ST, the comparator 122 determines the packet (P i  or V k ) to be output. This implies that the data packet P i  which has been input earliest is accessed in accordance with the input order (time) of the data packet P i  input to the storage circuit 121, and that the corresponding time data TD i  thereof is used. Alternatively, it is possible that, by accessing the transmission start time t S  stored in the storage circuit 121, and comparing the time data TD i  of the packet data P i  having the earliest transmission start time t S  with the clock time ST, the packet (P i  or V k ) to be output can be determined. 
     In this example, the data packet generator 11c generates the transmission start time t S  as one of the time data TD i . However, by setting the time at which the data packet generator 11c outputs the data packet P i  as the transmission start time t S  (i.e., setting a predetermined time interval after the time at which the data packet is generated as a period of time during which a data packet can be output), and specifying the transmission end time t E , the cycle C j  in which the data packet P i  can be output can be determined. 
     EXAMPLE 5 
     A packet output device 140 according to Example 5 of the present invention will be described with reference to FIG. 11. FIG. 11 is a block diagram showing the basic structure of the packet output device 140 of Example 5. The same components as in Examples 2 and 3 bear the same reference numerals. As shown in FIG. 11, the packet output device 140 includes a data packet generator 11d, a packet transmitting circuit 12d and a clock signal generator 13. The packet transmitting circuit 12d includes a vacant packet generator 113, a selector 114, a transmitting circuit 115, an adder 119, a comparator 122 and a storage circuit 124. The clock signal generator 13 is the same as the conventional clock signal generator 33, as in the case of the packet output devices according to Examples 1 to 4. The clock signal generator 13 outputs, for example, a clock signal for defining a clock time ST for the system of the packet output device 140. The clock time ST is supplied to the data packet generator 11d and the comparator 122 of the packet transmission circuit 12d. 
     As shown in FIG. 11, the data packet generator 11d generates a data packet P i  (i=1, 2, 3, . . . ) and time data TD i  (transmission start time t S  and transmission time width t W ) for specifying a time at which the data packet P i  will be output based on the clock time ST. The data packet P i , the transmission start time t S  and the transmission time width t W  are supplied to the storage circuit 124 of the packet transmitting circuit 12d. The storage circuit 124 stores the data supply P i , the transmission start time t S  and the transmission time width t W  input thereto. 
     The comparator 122 outputs a control signal CS 2  to the storage circuit 124 so that the transmission start time t S  and the transmission width t W  of the oldest data packet P i  stored in the storage circuit 124 are retrieved. The transmission start time t S  is output to the comparator 122 and the adder 119, and the transmission time width t W  is output to the adder 119. The adder 119 adds the transmission start time t S  and the transmission time width t W  supplied from the storage circuit 124 to generate the transmission end time t E  and outputs the generated transmission end time t E  to the comparator 122. 
     The comparator 122 compares the transmission start time t S  and the input transmission end time t E  input thereto with the clock time ST input from the clock signal generator 13 to determine which to output, the data packet P i  or a vacant packet V k . Based on this determination, the comparator 122 outputs the control signal CS 1  to control the selector 114 so that the selector 114 outputs the determined packet, the data packet P i  or the vacant packet V k , to the transmitting circuit 115. 
     Furthermore, when the comparator 122 determines that the data packet P i  should be selected, the comparator 122 simultaneously outputs the control signal CS 2  to the storage circuit 124 so that the storage circuit 124 outputs the corresponding data packet P i  to the selector 114. Furthermore, the vacant packet generator 113 generates the vacant packet V k  showing the absence of data and outputs it to the selector 114. 
     The selector 114 outputs either one of the data packet P i  or the vacant packet V k  to the transmitting circuit 115, in accordance with the determination of the comparator 122, based on a control signal CS 1  supplied from the comparator 122. The transmitting circuit 115 outputs the data packet P i  or the vacant packet V k  input from the selector 114 to the transmitting path 14. Moreover, the transmitting circuit 115 informs the comparator 122 whether or not the packet can be output to the transmitting path 14 (i.e., whether or not the transmitting path 14 is busy) for each transmission cycle C j  (by a signal BS). Signal BS can be, for example, a signal which is output only when the transmitting path 14 is not busy. 
     Next, the operation of the comparator 122 will be more specifically described. 
     The comparator 122 generates the control signal CS 1  based on the signal BS supplied from the transmitting circuit 115, the transmission start time t S  input from the storage circuit 124, the transmission end time t E  input from the adder 119 and the clock time ST input from the clock signal generator 13 so as to output the signal CS 1  to the selector 114. 
     When being informed that the transmitting path 14 is not busy by the signal BS from the transmitting circuit 115, the comparator 122 retrieves the transmission start time t S  and the transmission time width t W  of the oldest data packet P i  stored in the storage circuit 124 to output to the adder 119. Then, the comparator 122 compares the retrieved transmission start time t S  and the transmission end time t E  output from the adder 119 with the clock time S. In the case where the clock time ST is past the transmission start time t S , and the clock time ST is not past the transmission end time t E , the comparator 122 determines that the data packet P i  should be selected. Then, the comparator 122 outputs the control signal CS 1  to the selector 114 so that the data packet P i  is selected. 
     At the same time, the comparator 122 outputs the control signal CS 2  to the storage circuit 124 so that the storage circuit 124 outputs the data packet P i  to the selector 114, and relinquishes the previously output data packet P i , the transmission start time t S  and the transmission time width t W  thereof. Accordingly, after the data packet P i  is output, the oldest data packet in the storage circuit 124 is a data packet P i+1 . 
     In the case where the clock time ST is past the transmission end time t E  of the data packet P i , the comparator 122 outputs the control signal CS 1  to the selector 114 so that the vacant packet V k  is selected. In addition, the comparator 122 outputs the control signal CS 2  to the storage circuit 124 so that the data packet P i  and the time data (the transmission start time t S  and the transmission time width t W ) of the data packet P i  are relinquished. In the case where the clock time ST is before the transmission start time t S , the comparator 122 outputs the control signal CS 1  to the selector 114 so that the vacant packet V k  is selected. 
     As described above, when the transmitting path 14 is not busy, the selector 114 outputs the data packet P i  or the vacant packet V k  to the transmitting circuit 115 in accordance with the control signal CS 1  supplied from the comparator 122. 
     On the other hand, when the transmitting path 14 is busy (e.g., when the signal BS is not output from the transmitting circuit 115), the comparator 122 sends a signal CS 1  to the selector 114 controls such that neither the data packet P i  nor the vacant packet V k  will be output from the selector 114. Therefore, in this example as well, the timing chart showing the packet arrangement on the transmitting path 14 is the same as that in FIG. 4. 
     As described above, the data packet generator 11d outputs the time data TD i  (transmission start time t S  and transmission time width t W ) in addition to the data packet P i  to the storage circuit 124 of the packet transmitting circuit 12d, so that it possible for the data packet generator 11d to generate the data packet P i  regardless of the state of the transmitting path 14. Thus, the structure of the data packet generator 11d can be simplified, and the burden thereon can be reduced. Furthermore, for example, in the case where the packet generator 11c includes a computer or the like, it is unnecessary for the computer to monitor the state of the transmitting path 14 or the clock time ST, thus making it possible for the computer to perform other operations. 
     In this example, although the transmission start time t S  and the transmission time width t W  are generated as the time data TD i , and the transmission end time t E  is obtained by the adder 119, even when either one of the transmission start time t S  and the transmission end time t E  is used, it is unnecessary for the data packet generator 11d to monitor the clock time ST, thus obtaining the same effect as in this example. 
     In this example, in the case where the clock time ST is past the transmission end time t E , the comparator 122 outputs the control signal CS 1  to the selector 114 so that the vacant packet V k  is selected. Alternatively, in the case where the clock time ST is past the transmission end time t E , the following processing with respect to the data packet P i  can be performed. 
     With respect to the oldest data packet P i  in the storage circuit 124, when the clock time ST is past the transmission end time t E , the comparator 122 compares the transmission start time t S  and the transmission end time t E  of the second oldest data packet P i+1  with the clock time ST. In the case where the clock time ST is between the transmission start time t S  of the data packet P i+1  and the transmission end time t E  of the data packet P i+1 , the comparator 122 determines that the data packet P i+1  should be selected. Then, the comparator 122 outputs the control signal CS 2  to the storage circuit 124 so that the storage circuit 124 outputs the data packet P i+1  to the selector 114, and simultaneously outputs the control signal CS 1  to the selector 114 so that the selector 114 selects the data packet P i+1 . Thus, it is possible to enhance transmission efficiency of the data packet P i . 
     Furthermore, in this example, by comparing the time data TD i  of the oldest data packet P i  stored in the storage circuit 124 with the clock time ST, the comparator 122 can determines the packet (P i  or V k ) to be output. This implies that the data packet P i  which has been input earliest to the storage circuit 124, and that the time data TD i  thereof are used first. Alternatively, it is possible that, by accessing the transmission start time t S  stored in the storage circuit 124 and comparing the time data TD i  (transmission start time t S  and transmission end time t E ) of the packet data P i  having the earliest transmission start time t S , with the clock time ST, the comparator 122 can determine the packet (P i  or V k ) to be output. 
     In this example, the data packet generator 11d generates the transmission start time t S  as one of the time data TD i . However, by setting the time at which the data packet generator 11d outputs the data packet P i  as the transmission start time t S  (i.e., setting a predetermined time interval after the time at which the data packet is generated as a period of time during which a data packet can be output), and by specifying the transmission end time t E , the cycle C j  in which the data packet P i  can be output can be determined. 
     In the case where transmission of the packet having a predetermined transmission time is performed by a computer or the like, it is possible to obtain the transmission start time and the transmission end time by calculation of a CPU. However, it is difficult for the CPU to monitor the time for transmitting packets to the transmitting path because it requires constant processing in a predetermined cycle (typically, on the order of μs ec). Actually, in the case where the computer performs transmission of the packet while monitoring the transmitting path and the clock time, a large burden is imposed on the computer. By using the circuitry for transmitting packets according to Examples 1 to 5, it is possible to reduce the burden on the CPU and for the computer to easily perform transmission of a packet having a predetermined transmission time. In particular, the computer can transmit of the packets while performing other processing operations, thus improving the processing efficiency of the computer. 
     Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be broadly construed.