Abstract:
A test system includes at least one computer and a control circuit for testing the computer. The computer includes an input interface and an output interface. The control circuit is configured for sending test signals to the input interface and receiving feedback signals from the output interface for facilitating locating and recording errors during testing of the computer. A testing method for testing the computer is also disclosed.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present invention relates to a system and method for testing computers. 
         [0003]    2. Description of Related Art 
         [0004]    After a computer is produced, stability tests are required. A conventional test fashion is manually operating the computer repeatedly to check whether the computer can pass stability test. However, because a great number of computers need to be tested in the manufacturing process, manually testing the computer is inefficient and a waste of manpower. 
         [0005]    An improved method for automatically testing the computer is also adopted. The method includes steps of utilizing a microcontroller (MCU) with test procedure burnt therein to send test signals to the computer and detecting whether the computer can pass POST (Power On Self Test), whether the computer can be awaked normally etc. However, there is no feedback signal from the computer to the MCU. The test signals cannot be adjusted automatically according to actual running conditions of the computer. Error test information is not available to be recorded. 
         [0006]    What is needed, therefore, is a system and method for testing computers capable of bi-directionally communicating with a control chip of the system. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is a block diagram of an embodiment of a test system, the test system including a control circuit and a computer; 
           [0008]      FIG. 2  illustrates a detailed block diagram of the test system of  FIG. 1 ; and 
           [0009]      FIG. 3  is a flow chart of an embodiment of a test method for testing a computer. 
       
    
    
     DETAILED DESCRIPTION 
       [0010]    Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
         [0011]    Referring to  FIG. 1 , an embodiment of a test system includes a computer  20  and a control circuit  10  configured for testing the computer  20 . The computer  20  includes a switch  22  and an input/output (I/O) port  24 . The switch  22  is connected to the control circuit  10  and configured for receiving test signals from the control circuit  10 . The I/O port  24  is connected to the control circuit  10  and configured for sending out feedback information to the control circuit  10 . 
         [0012]    Referring to  FIG. 2 , the control circuit  10  includes a microcontroller (MCU)  12 , a power supply  14  configured for powering the MCU  12 , a crystal oscillator circuit  16  connected to the MCU  12  and configured for applying clock signals to the MCU  12 , and a reset circuit  18  connected to the MCU  12  and configured for applying reset signals to the MCU  12 . In one embodiment, a test procedure may be burnt into the MCU  12  for testing the computer  20 . An output of the MCU  12  is connected to the switch  22  to send test signals to the computer  20  according to the test procedure. An input of the MCU  12  is connected to the I/O port  24  to receive feedback signals from the computer  20 . In one embodiment, an address of the I/O port  24  may be a port number to which test codes are written during testing of the computer  20 , for example, port  80 H. 
         [0013]    Referring to  FIG. 3 , is a flowchart utilizing the above described test system for testing the computer  20 . Depending on the embodiment, certain of the steps described below may be removed, others may be added, and the sequence of steps may be altered. 
         [0014]    In a block S 01 , the test procedure may be started in the MCU  12 . Continuing to a block S 02 , the MCU  12  sends a power-on signal to the computer  20 . Moving to a block S 03 , the computer  20  starts power on self test (POST) codes and sends the POST codes to the I/O port. Continuing to a step S 04 , the MCU  12  reads the codes sent from the I/O port. 
         [0015]    In a decision step S 05 , the MCU  12  determines if there are any error codes. If there are error codes, for example, a code  26 H indicating that the super I/O failed during POST, the method continues to a decision step S 06 . If there is no error code read by the MCU  12 , the method continues to a step S 07 . 
         [0016]    In the decision step S 06 , the MCU  12  determines if a restart signal is to be sent to the computer  20 . If a restart signal needs to be sent, then the method continues back to the step S 03  and executes a loop of S 03 →S 04 →S 05 →S 06  for locating the error and gathering more detailed information regarding the error. The error information is recorded in a step S 11 . If a number of iterations of the loop equals a predetermined number according to the test procedure, the MCU  12  stops sending the restart signal to the computer  20 , the loop ends, and the method is continues to a step S 12 . 
         [0017]    Moving to the step S 07 , the computer  20  goes into an operation system (OS) after POST. Continuing to a step S 08 , the computer  20  goes into a sleep state from the OS after a predetermined period of time. 
         [0018]    In a decision step S 09 , the MCU  12  determines if an awake signal is sent to the switch  22  to test an awake function of the computer  20 . If the awake signal is sent to the computer, the method continues to a decision step S 10 . If the awake signal is not sent to the computer, the method continues to the step S 12 . 
         [0019]    Moving to the decision step S 10 , the MCU  12  reads codes from the I/O port  24  and determines if the computer  20  can be awaked In one particular embodiment, if the MCU  12  reads a code of  30   h  , which indicates that the computer  20  has been awaked, the method continues back to the step S 08  and executes a loop of S 08 →S 09 →S 10  for repeating a testing stability of the awake function. If the number of iterations equals a predetermined number according to the test procedure, the MCU  12  stops sending the awake signal to the computer  20  and the method continues to the step S 12 . In another particular embodiment, if the MCU  12  reads a code of D3H, which indicates that the computer  20  cannot be awaked normally, the method continues to the step S 11  to record the error. 
         [0020]    Moving to the step S 11 , the MCU  12  records the error. 
         [0021]    In the step S 12 , the test ends and a further check for the computer  20  may be made. 
         [0022]    It may be appreciated that more than one computer  20  may be tested by the control circuit  10 . It may also be appreciated that the control circuit  10  may include another type of programmable chip instead of the MCU  12 . 
         [0023]    It is to be understood, however, that even though numerous characteristics and advantages have been set forth in the foregoing description of preferred embodiments, together with details of the structures and functions of the preferred embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.