Abstract:
Methods and system for achieving improved copyright protection for programmable logic devices are disclosed. One preferred embodiment comprises a programmable logic device comprising a programmable element programmed by a mutated programming pattern, said mutated programming pattern causing the PLD to generate a mutated output; and a circuit element that translates the mutated output into a normal output.

Description:
FIELD OF INVENTION 
   This invention is related in general to intellectual property protection technologies and in particular to methods and systems for achieving improved intellectual property protection for programmable logic devices. 
   BACKGROUND OF INVENTION 
   Programmable logic devices (PLD) such as field programmable gate arrays (FPGA) and complex programmable logic devices (CPLD) are digital logic circuits that can be programmed by certain “programming patterns” such as programmable object files (POFs) to perform logical functions. These devices have grown significantly in capability and complecity. Yet intellectual property (IP) protection embedded in such devices, such as the programming patterns, has not enjoyed similar development. 
   Currently, most IP protection schemes rely on encrypting/decrypting the programming patterns on chip.  FIG. 1  shows a typical encryption/decryption IP protection scheme that includes a decrypter  120  that receives an encrypted POF  110  and a decryption key  160 . The encrypted POF  110  is decrypted by the decrypter  120  using decryption key  160 . The decrypted POF  130  is then used to program a programmable logic circuit  140 . An output  170  of the programmable logic circuit  140  is coupled to a utility circuit  150 . The drawback of this IP protection scheme is that it relies on a decryption key  160 , which must be stored somewhere on the chip. As a result, this IP protection scheme is vulnerable to attack because it is not difficult for an attacker to reverse engineer the chip to obtain the decryption key. 
   In addition to being vulnerable to reverse engineering, storing a key on the chip may add production cost and complexity to chip manufacturers. For example, a battery must be used to store the encryption key in a SRAM FPGA. For an antifuse FPGA, extra fuses have to be blown to store the encryption key. 
   There is therefore a need to develop an IP protection scheme that achieves improved protection without using any decryption key. 
   SUMMARY OF INVENTION 
   In one aspect, the present invention comprises: a programmable element programmed by a mutated programming pattern, said mutated programming pattern causing the PLD to generate a mutated output; and a circuit element that translates the mutated output into a normal output. 
   In another aspect, the present invention comprises a method of copy-protecting the programming pattern of a PLD. The method comprises the steps of: fabricating a circuit element of the PLD, said circuit element capable of translating a mutated signal into a normal output signal of the PLD; and producing a programming pattern for programming the PLD, said programming pattern causing the PLD to generate the mutated signal. 
   In yet another aspect, the present invention comprises a method of producing a mutatable PLD. The method comprises the steps of: producing a plurality of programming patterns for programming the PLD, each programming pattern causing the PLD to generate one of a plurality of mutated signals; fabricating a plurality of circuit elements, each circuit element translating one of a plurality of mutated signals into a normal output of the PLD; and fabricating a switching element for selecting one of said circuit elements. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
       FIG. 1  shows a prior art encryption/decryption scheme. 
       FIG. 2  shows one embodiment of the invention. 
       FIG. 3  shows another embodiment of the invention. 
       FIG. 4  describes another exemplary embodiment of the invention. 
       FIG. 5  describes one method of fabricating one embodiment of the invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 2  shows one embodiment of the present invention. The system of  FIG. 2  comprises a mutated PLD  220  programmed by a mutated programming pattern, or mutated POF  120 . An output  240  of PLD  220  is applied to a utility circuit  250 , which is intended to represent any circuit that might be connected to the output of a PLD. The mutated POF  210  is a POF that causes the mutated PLD  220  to generate a “mutated” output signal that causes the utility circuit  250  to function abnormally. The mutated POF  210  may be produced, for example, by altering a portion of the source code of a normal POF. The mutated PLD  220  also contains an additional circuit element  260 . The additional circuit element  260  is capable of translating the mutated output signal to a normal output signal. Optionally, the system of  FIG. 2  also contains a switch  230  for enabling or disabling the circuit element  260 . 
   The system of  FIG. 2  may be part of a system on a programmable chip (SOPC) using a PLD, such as a FPGA or a CPLD. The PLD  220  may be part of the core logic of the SOPC and the programming pattern used in the PLD  220  is often the target of attackers. The embodiment of  FIG. 2  requires both the mutated programming pattern  210  and the mutated PLD  220  to generate a normal output signal  240 . Thus, if the mutated programming pattern  210  were stolen by the attacker and used on a normal PLD, the normal PLD will generate a mutated output signal that will disrupt the operation of the utility circuit. Furthermore, even if the attacker were able to detect how the programming pattern  210  was mutated, it would not be easy job for him to reverse the mutation. This is because an attacker must either redesign the hardware of his PLD to add an additional circuit  260  to reverse the mutation, or reverse-engineer the mutated programming pattern  210  to remove the portion of the code that has been altered. Neither alternative is likely to be practical. FIG.  2 &#39;s system, therefore, discourages piracy and ensures stronger protection of the programming pattern embedded in the PLD. 
     FIG. 3  shows another embodiment of the present invention. The system of  FIG. 3  comprises a mutated PLD  320  that could be programmed by a plurality of mutated programming patterns, or mutated POFs  310 . An output  340  of PLD  320  is applied to a utility circuit  350 . Each mutated POF causes the PLD  320  to generate a mutated output signal. The mutated PLD  320  contains an circuit element  330  that is capable of selectively reversing the signal mutation caused by each one of the plurality of mutated POFs  310 . Specifically, the circuit element  330  contains a plurality of circuit elements  370 – 380 . Each one of these circuit elements performs a mutated function that translates a different one of the mutated output signals into a normal output signal. 
   In  FIG. 3 , all of the circuit elements  370 – 380  are connected to a selection MUX  360  controlled by a switch logic circuit  390 . The switch logic circuit  390  may be coupled to a number of fuses and the user of the PLD  320  can select a circuit element by blowing one or more fuses. After detecting which fuses are blown, the switch logic circuit determines which corresponding circuit element should be selected and generates a control signal to MUX  360  informing it to switch to the selected circuit element. The selected switch element is then available to translate one of the mutated output signals into a normal output signal. 
   A specific embodiment of the system of  FIG. 3  is shown in  FIG. 4 . The system of  FIG. 4  comprises a mutated PLD  420  that can be programmed by a plurality of different mutated programming patterns, or mutated POFs  410 . An output  440  of PLD  420  is applied to a utility circuit  350 . Each mutated POF  410  performs an up-sampling function that causes the PLD  420  to output “n” pulses per single pulse in a normal output signal, where “n” is an integer number greater than 1. To recover the normal output signal, the mutated PLD  420  contains an circuit element  430  that contains a plurality of down-sampler circuits  470 – 480 . Each one of these down-sampler circuits selects the first pulse of every 2, 3, . . . , or n pulses, thereby restoring the output signal  340  to its normal form. 
   Similar to  FIG. 3 , all of the down-sampler circuits  470 – 480  are connected to a MUX  460  for selection. The MUX  460  is controlled by a switch logic circuit  490 . The user of the PLD  420  can select a down-sampler circuit corresponding to the up-sampling rate of the mutated POF  410 . For example, if the POF  410  causes the PLD  420  to output 2 pulses per single pulse in the normal output signal, then the ½ down-sampler circuit  470  is selected by the switch logic circuit  490  to offset this. 
     FIG. 5  describes the steps for fabricating the system of  FIG. 3  according to one embodiment of the present invention. In step  510 , a plurality of programming patterns, such as the POFs  310  are produced for programming the PLD  320 . Each programming pattern  310  causes the PLD  320  to generate one of a plurality of mutated signals. In step  520 , a plurality of circuit elements  370 – 380  are fabricated. Each circuit element translates one of the plurality of mutated signals generated by the programming pattern  310  into a normal output signal. Finally, in step  530 , the switching element  360  is fabricated for selecting one of the circuit elements  370 – 380 . The designs of the programming pattern  310 , the circuit elements  370 – 380  logic circuit  180 , and the switching element  360  may be produced using commercially available design software such as the Quartus® II design software provided by Altera Corporation, San Jose, Calif. 
   While the above invention has been described with reference to certain preferred embodiments, the scope of the present invention is not limited to these embodiments. One skilled in the art may find variations of these embodiments which, nevertheless, fall within the spirit of the present invention, whose scope is defined by the claims set forth below.