Abstract:
The present invention provides methods and apparatus for controlling power utilization in a wireless communication receiver. A representative system comprises a signal properties evaluation module, an analog to digital converter (ADC), and an analog to digital converter control module. The signal properties evaluation module evaluates the stability of a received signal, and provides an indication of the stability. The ADC control module responds to the signal properties evaluation module to select the precision of the ADC based upon the indication of the stability. The ADC has at least two modes of operation, comprising a first precision and a second precision, and is responsive to the signal properties evaluation module to operate in at least one of two modes based upon the stability. The ADC responds to the signal properties evaluation module so as to limit the amount of power consumed by the wireless communications device.

Description:
FIELD OF INVENTION 
     The present invention relates to the field of wireless communication and in particular to an adaptive receiver. 
     BACKGROUND OF THE INVENTION 
     The field of wireless communications is rapidly expanding. In particular, cellular communication systems are experiencing phenomenal growth. Likewise, cordless telephones are in widespread use. 
     Each mobile station, whether a cordless or cellular telephone, operates using power supplied by an associated battery. Each mobile station continually draws power from the battery while in standby mode or during an active communication link. The mobile unit draws the most power during periods of an active communication link. In particular, the receiver, which is responsible for obtaining, filtering, decoding and synthesizing the incoming signal, comprises a large percentage of total mobile unit power usage during an active communication link. This is especially true when the communication system comprises a modem cellular system, such as Global System for Mobile Communication (GSM) or a system adopting Code Division Multiple Access (CDMA) techniques. Modem communication systems adopt these complex coding schemes to increase both system capacity and voice quality. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to unique methods and apparatus for controlling power utilization in a wireless communication receiver. A representative system, among others, comprises a signal properties evaluation module, an analog to digital converter, and an analog to digital converter control module. The signal properties evaluation module evaluates the stability of a received signal, and provides an indication of the stability. The analog to digital converter control module responds to the signal properties evaluation module to select the precision of the analog to digital converter based upon the indication of the stability. The analog to digital converter has at least two modes of operation, and is responsive to the signal properties evaluation module to operate in at least one of two modes based upon based upon the stability. The first mode comprises operation at a first precision and said second mode comprises operation at a second precision. The analog to digital converter responds to the signal properties evaluation module so as to limit the amount of power consumed by the wireless communications device. 
     A representative method, amoung others, comprises the steps of: receiving a signal; monitoring the characteristics of the incoming signal; evaluating the stability of the incoming signal; and altering the precision of an analog to digital converter based on the evaluated stability of the incoming signal so as to limit the amount of power consumed by said wireless communications receiver. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of wireless communication system receiver. 
     FIG. 2 illustrates the front end of a digital communication receiver with analog to digital converters incorporating signal quality feedback. 
     FIG. 3 illustrates a timing estimator incorporating signal quality feedback. 
     FIG. 4 illustrates equalizer incorporating signal properties feedback. 
     FIG. 5 illustrates a basic block diagram of a combiner having adaptive performance. 
     FIG. 6 illustrates a block diagram of a wireless communication receiver in a Global System for Mobile Communications. 
     FIG. 7 illustrates a frequency estimation block diagram for an adaptive frequency estimator. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 illustrates the basic components of a wireless communication system receiver as embodied in a cellular telephone communication receiver adopting code division multiple access (CDMA). Modern cellular communication systems generally comprise a plurality of base stations and mobile stations. Both of the base station and a mobile station incorporate a communication receiver. The present invention focuses on a system and method of reducing power consumption of a battery powered mobile station communication receiver and also, improving performance when necessary. The base stations are typically wired to a land based power source. For purposes of explanation, a general overview of a receiver in one preferred embodiment is provided below. In general, the receiver comprises an antenna  110  coupled to a radio frequency (RF) subsystems module  112 . This module  112 , provides two outputs (I,Q) to analog-to-digital (A/D) converters  114 ,  116 . Each of the A/D converters  114 ,  116  connects to signal estimator  120 , a timing estimator  122 , a data demodulator  124 , and a phase and frequency estimator  126 . In turn, the output of the timing estimator  122  and the phase and frequency estimator  126  couple to inputs of the data demodulator  124 . The output of the data demodulator  124  couples to a vocoder  132  and a signal properties evaluation module  130 . The vocoder&#39;s output couples to a codec  134  and the signal properties evaluation module  130 . The output of the codec  134  couples to an amplified speaker  136  for audio reproduction. 
     In operation the antenna  110  converts arriving radio frequency signals to electrical signals for the radio frequency (RF) subsystems module  112 . The RF subsystems module  112  amplifies the incoming signal before performing frequency translation and band pass filtering on the signal. The RF subsystem provides the in-phase (I) and quadrature-phase (Q) portions of the incoming signal to A/D converters  114 ,  116 . The A/D converters  114 , 116  convert the incoming analog signal to a digital format. Conventionally, the A/D converters  114 , 116  are configured with a predetermined precision for the conversion process. 
     The signals exiting the A/D converters  114 , 116  enter the signal estimator  120 , a timing estimator  122 , a phase and frequency estimator  126 , and a data demodulator  124 . The output of the timing estimator  122 , and phase and frequency estimator  126  connect to the data demodulator  124  to provide data necessary for the demodulation and decoding of the voice signal. 
     The timing estimator  122  determines the timing of the signal in relation to a synchronization signal to obtain signal alignment during decoding and demodulation. In one preferred embodiment, the timing estimator  122  comprises a delay lock loop (DLL), which is described in more detail below in conjunction with FIG.  3 . 
     The phase and frequency estimator  126  determines the phase and frequency of the incoming signal which, as known by those familiar with receiver operation, aids in the demodulation process. 
     The signal estimator  120  determines the signal to noise ratio, signal dynamics, and the signal strength level and provides these values to the signal properties evaluation module  130 . As discussed in more detail below, the signal properties evaluation module  130  uses these values for dynamic receiver control. 
     The data demodulator and decoder  124  demodulates the signal from radio frequency and performs reverse coding on the signal. In one embodiment the coding comprises code division multiple access (CDMA). 
     The output of the data demodulator and decoder  124  is coupled to the signal properties evaluation module  130  and the vocoder  132 . The signal properties evaluation module  130  uses the demodulated and decoded data to estimate the bit error rate (BER) and the frame error rate (FER) which in turn are used to further evaluate the incoming signal. The vocoder  132  generally comprises an electronic speech analyzer as known in the art. 
     The output of the vocoder  132  is coupled to a codec  134  input. As known in the art, the codec  134  converts the digital signal to an analog signal. The corresponding signal exits the codec  134  for receipt by a speaker  136  which audibly reproduces the signal. An optional amplifier, not shown, may exist between the codec  134  and the speaker  136 . 
     Optionally, the signal may comprise data information which would not require conversion of the signal to an analog format. Hence, a receiver configured to process non-voice data would lack componentry for processing voice, such as the vocoder  132  and codec  134 . 
     The signal properties evaluation module  130  provide feedback to the A/D converters  114 ,  116 , the signal estimator  120 , the timing estimator  122 , the data demodulator and decoder  124 , and the phase and frequency estimator  126  in accordance with various aspects of the present invention in order to facilitate dynamic control of the various blocks of the receiver for changing signal quality and/or power reduction purposes. 
     Analog to Digital Converters Incorporating Signal Quality Feedback 
     FIG. 2 illustrates one embodiment of the present invention. At the front end of a receiver adopting CDMA principles, the signal is divided into its in-phase (I) and quadrature-phase (Q) components. Each of these respective signals enters one of the analog to digital converters  114 , 116 . The analog to digital converters  114 , 116  converts the incoming analog signal to a digital representation of the signals. 
     In conventional systems, the precision of each A/D converter  114 , 116  is held constant, typically at 5 bits. The output of the A/D converters  114 , 116  couple to the other receiver subsystems  200 . The receiver subsystems  200  comprises componentry such as the signal estimator  120 , timing estimator  122 , data demodulator  124 , and the phase and frequency estimator  126 , shown in greater detail in FIG.  1 . Accordingly, the precision of the A/D converters impacts the processing of the majority of the remaining receiver subsystems, as depicted in FIG.  1 . As explained previously in conjunction with FIG. 1, the output of the signal estimator  120  connects to the signal properties evaluation module  130 . The signal properties evaluation module  130  is in communication with the A/D converters via an A/D converter control module  220 . The control decision module connects to each of the A/D converters  114 , 116 . Of course, the A/D converter control module  220  can be considered part of what could be combined with the signal properties evaluation module  130 . In other words, the control for the A/D converters  114 ,  116  can be generated directly from the signal properties evaluation module whereby the separate A/D converter control module  220 , which receives input from the signal properties evaluation module  130 , is made up of one module or multiple modules or combined with the signal properties evaluation module  130 . The independent depiction in the figures of the present application is provided to facilitate the description of the system. 
     In operation, real-time feedback from the signal properties evaluation module  130  controls the operating precision of the A/D converters  114 , 116 . In particular, the in-phase and quadrature phase components of the incoming signal enter the A/D converters  114 , 116 . At the inception of the communication link, the precision of the A/D converters  114 , 116  is set to a first precision level, in one embodiment, the highest precision level provided by the A/D converters  114 ,  116 . The A/D converters  114 ,  116  modify the incoming signal to a digital format and forward the signal to the other components of the receiver. One component of the receiver which obtains the output of the A/D converters  114 , 116  is the signal estimator  120 , which is incorporated in FIG. 2 in the receiver subsystem  200 . The signal estimator  120  evaluates the digitized signal to determine dynamics, noise and interferences level and the signal strength. These values are forwarded to signal properties evaluation module  130 . 
     The evaluation module  130  processes the information from the signal estimator  120  (and other inputs as depicted in FIG. 1) and arrives at a determination of the signal quality and stability, referred to herein as the signal properties or characteristics. The signal properties are forwarded to the A/D converter control module  220  which evaluates the signal properties. Based on the evaluation of the incoming signal, the control module  220 , which is in communication with the A/D converters  114 , 116 , adjusts the precision level of the A/D converters. Advantageously, the A/D converters can be adjusted separately. An evaluation by the signal properties evaluation module  130  and the control module  220  indicating a generally stable signal prompts the control module to reduce the precision of each of the A/D converters  114 , 116 . If signal quality is high enough on I or Q, one or the other signals may be entirely shut off. In one embodiment, when the signal is of high quality the control module  220  reduces the precision of each or one of A/D converter  114 , 116  to four, three, or even two bits. Reducing the precision of the A/D converters  114 , 116  reduces the power consumption of the receiver. Because the control module  220  only reduces the precision of the A/D converters  114 , 116  when the incoming signal is of high quality, the power consumption of the mobile station decreases without a compromise in audio quality. Because the precision of the A/D converters can drastically increase or decrease the total amount of data which must be processed by the remaining receiver components such as the signal estimator  120 , the timing estimator  122 , the data demodulator and decoder  124 , and the phase and frequency estimator  126 , the power savings resulting from the reduction of precision in the A/D converters  114 ,  116  can significantly impact the power consumption of the receiver. As further shown in FIG. 2, the control module  220  also connects to the receiver subsystems  200  to appropriately adjust the operating precision of the other aspects of the receiver. In particular, when the control module  220  reduces the precision (number of bits) of the A/D converters  114 , 116 , the components which receive the output of the A/D converters will also operate in a reduced precision mode. If one of the I or Q signals is completely discontinued due to very high signal quality on the other signal, receiver subsystems which respond to the particular signal which has been discontinued would be completely deactivated in one embodiment, further reducing power. 
     Conversely, if the evaluation module  130  and control module  220  ascertains that the signal quality is poor, the control module increases the precision of either or both of the A/D converters  114 , 116 . In this fashion the precision of the A/D converters  114 ,  116  dynamically adjust depending on the quality of the incoming signal. 
     The degree or percentage of power consumption achieved using these principles varies depending on the receiver subsystems  200  components. In one embodiment, the reduction in operating precision in the front end A/D converters  114 , 116  can result in an overall reduction in receiver power consumption of about 20 percent, while degrading signal quality by less than about 0.8 dB. This correlates to an overall reduction in chip power usage of approximately 5% to 10% in the present embodiment. Furthermore, with the reduction in power consumption during periods of high signal quality, for the same power usage over time, the precision of the A/D converters  114 ,  116  can be increased during periods of poor signal quality to enhance communication performance without increasing the overall power usage over time. 
     Timing Estimator Incorporating Signal Quality Feedback 
     Modem communication receivers utilize some form of signal synchronization to properly track, demodulate and decode the incoming signal. One example of such a synchronization mechanism is a delay lock loop which serves to synchronize the incoming signal with an internal or known clock or timing signal. FIG. 3 illustrates a synchronization mechanism known as a timing estimator incorporating signal quality feedback. 
     A receiver includes a number of despreaders  300 , each coupled to a timing estimator and filter module  122  (e.g., a delay—lock-loop or DLL) . The output of the timing estimator and filter module  122  connects to the data demodulator, as shown in FIG.  1 . Also shown in FIG. 3 is the signal properties evaluation module  130  which obtains information regarding the incoming signal and, upon processing the information, determines the quality and/or dynamics of the incoming signal. The output of the signal properties evaluation module  130  connects to a timing control decision unit  320 . The output of the signal properties evaluation module couples to each of the despreaders  300  and the timing estimator and filter module  122  via the timing control decision unit  320 . 
     In conventional systems, the timing estimator and filter module  122 , (e.g., the DLL), operates constantly, and at a fixed rate of sampling. However, in accordance with the principles of the present invention, the timing estimator and filter module  122  can operate all the time, intermittently, or at a reduced rate. 
     In the present embodiment, each of the despreaders  300  outputs a signal recovered from the spread spectrum data transmission to the timing estimator and filter module  122 . The timing estimator and filter module  122  receives and processes the despread signals to synchronize the signals. A timing signal is provided to the demodulation unit  124  (FIG. 1) for use in demodulation. 
     The signal properties evaluation module  130  simultaneously provides information regarding the quality and/or dynamics of the incoming signal to the timing control decision unit  320 . The timing control decision unit  320  evaluates the information describing the incoming signal properties and provides control information to the timing estimator and filter module  122  and each of the despreaders  300 . 
     The timing estimator and filter module  122  and each of the despreaders  300  may alter its operation based on the input from the timing control decision module  320 . For example, the timing control decision module  320  provides data to the timing estimator and filter  122  to thereby control the type, operation duty cycle, and filter properties, such as complexity and bandwidth. The information provided from the timing control decision unit  320  to the timing estimator  122  changes depending on the quality of the signal. The timing estimator and filter module  122  uses this information to adjust its operation to save power when the incoming signal is of high quality and/or increase performance during periods of low signal quality and/or high dynamics. 
     More specifically, based on the timing error, the DLL  122  can modify its operation. For instance, if the timing error becomes very small on repetitive samples, the duty cycle, or percentage of time that the DLL  122  operates, can be adapted to save power. In other words, in periods of small error in timing, the duty cycle of the DLL  122  can be decreased for less frequent operation. In times of higher timing error, the duty cycle of the DLL  122  can be advanced for more frequent sampling. Similarly, the DLL type can be adjusted for better or poorer timing error. Furthermore, the DLL type can be altered during periods such as pull-in or reacquisition to provide necessary performance during these periods. For example, during pull-in, the DLL may utilize four taps and then adjust the tap spacing to two when the delay is estimated. Accordingly, only the processing complexity necessary to maintain signal timing is required. 
     As known in the art, timing estimators and associated filters, such as a DLL, begin operation after the initial signal search process occurs to achieve precise synchronization and tracking. The DLL generally comprises a first correlator beginning operation early and a second correlator beginning operation later in relation to the optimum sampling time. An error signal is formed by taking the difference between the two absolute values of the two correlator outputs. A non-zero error signal indicates that the timing of the synchronizing signal is incorrect relative to the optimum sampling time. Accordingly, the synchronization signal is either retarded or advanced, depending on the sign of the error. Operating this loop adjusts the synchronization signal. 
     During periods of general stability with regard to the incoming signal, the error signal is generally zero and hence the timing of the synchronization signal remains generally unchanged. Alternatively, when the incoming signal is generally unstable and possesses high dynamics or interference, the error signal is generally non-zero and the timing estimator  122  continually evaluates and adjusts the synchronization signal. 
     Based on the above described operation of an embodiment of the present invention using a DLL, the timing control decision unit  320  evaluates the incoming signal based on input from the signal properties evaluation unit  130  and adjusts the behavior of the DLL to use power efficiently and/or provide increased reliability in times of low signal quality. For example, during periods of general stability, the timing control decision unit  320  adjusts operation of the DLL by reducing the duty cycle, the complexity and/or bandwidth of the filters, all of which reduce power consumption of the receiver. 
     The timing control decision unit  320  also provides data to the despreaders  300  to control the tap spacing of the despreaders. The information provided from the timing control decision unit  320  to the despreaders  300  alters the operation of the despreaders to use power efficiently by reducing power usage during periods when the incoming signal is of superior quality. For example, the control information provided to the despreaders  300  may alter the despreaders tap spacing to save power during periods when the incoming signal is of high quality. 
     In this fashion the receiver monitors the quality of the incoming signal and adjusts the operation of the timing estimator and filter module  122  and the despreaders  300  to reduce the power consumption when the signal is of high quality and generally stable. Alternatively, during periods of poor signal quality, the operation is made more robust, at the cost of additional power consumption. 
     Equalizer Incorporating Signal Properties Feedback 
     Many modem communication systems, such as systems employing time division multiple access (TDMA) and code division multiple access (CDMA), often employ a type of receiver known as a RAKE receiver. A RAKE receiver has a number of receivers, or “fingers,” each of which are configured to obtain a portion of a radio signal. Receivers employ such a configuration because, in most communication systems, the channel characteristics are unknown or time-variant. One example is when a transmitted signal encounters obstacles in the path between the transmitter and receiver. Because of the obstacles, the resulting signal includes energy peaks which are spread over time. In particular, the incoming signal is often separated into a number of peaks or time-varied portions each of which contain important signal information. Each of the fingers of a RAKE receiver obtains the information at each of the peaks of the incoming signal. However, the energy at each of the peaks may become misaligned or smeared, thereby preventing the fingers of the rake receiver from properly obtaining the signal. 
     To overcome the misalignment of the peaks in the incoming multipath signal, modem communication systems often employ equalizers. The equalizer removes certain time delayed waves or signal portions. In particular, equalizers detect the delayed portions of the signal and lock onto the strongest portions. Equalizers may operate by using a training sequence that is sent at the start of the data communications burst. The equalizer then adjusts itself to provide the maximum response on the channel, thereby negating the deteriorating effects of the radio channel itself. 
     Undesirably, the one or more equalizers in a receiver of a modern communication system operate continuously during an active communication link. The continuous operation of the equalizer is desirable when the peaks of a multipath signal are misaligned. However, continuous operation of the equalizers in a mobile station when the incoming signal is generally stable and not in need of equalization consumes valuable battery power. One embodiment of the present invention comprises adjusting the complexity and/or duty cycle of the equalizer based on the characteristics of the incoming signal to reduce power consumption and/or increase performance as needed. 
     FIG. 4 illustrates one embodiment of an equalizer configured for adaptive operation in accordance with the principles of the present invention. In particular, with regard to signal equalization, the relevant portion of a wireless communication receiver comprises an equalizer  400  having a first input configured to receive a signal, a second input coupled to an output of an equalizer controller  410 , and an output coupled to the demodulator  124 . The input of the equalizer controller  410  couples to the output of the signal properties evaluation module  130 , which is described above in greater detail. 
     In operation, the components illustrated in FIG. 4 cooperate to receive a signal at the first input of the equalizer  400 . In one embodiment, at start-up, the equalizer  400  enters a full operation mode wherein the signal improving capabilities of the equalizer are fully operational. After fully equalizing the incoming signal, the equalizer passes the signal to the demodulator  124  for additional signal processing. The output of the demodulator  124  passes to other receiver subsystems (see FIG.  1 ). 
     Other subsystems of the receiver (FIG. 1) provide information regarding the signal to the signal properties evaluation module  130 . The signal properties evaluation module  130  processes and feeds the processed information to the equalizer controller  410 . The equalizer controller  410  further evaluates the signal characteristics based on the information from the signal properties evaluation module  130  and, based on this evaluation, outputs control information to the equalizer  400 . The control information dictates the duty cycle and complexity of operation of the equalizer  400 . 
     The amount of power used by the equalizer  400  depends upon the duty cycle of the equalizer  400  and the complexity of the equalizing algorithms used in the equalizer  400 . In one embodiment, the equalizer  400  can be completely disabled when the peaks in an incoming signal are readily discernible and the equalizer can be re-activated when the peaks become “smeared.” For example, the equalizer  400  enters a power saving mode when the signal properties evaluation module  130  and the equalizer controller  410  determine that the incoming signal no longer requires extensive equalization. Conversely, the equalizer returns to full equalization when instructed that the incoming signal requires equalization to maintain communication quality and prevent dropped calls. In this manner the equalizer&#39;s overall power consumption is minimized without sacrificing signal quality and communication link integrity. 
     RAKE Finger Duty Cycle Adjustment and Combiner Algorithms Adjustment 
     FIG. 5 illustrates a combiner in a RAKE receiver. A CDMA receiver employs multiple correlators also known as fingers. The multiple correlators reduce a receivers susceptibility to multipath components because the receiver can simultaneously receive several multipath signals and coherently combine them, resulting in a stronger signal. The RAKE receiver also enables a mobile station to communicate with two base stations simultaneously, making soft hand-offs possible and greatly reducing the probability of dropped calls. 
     Present systems operate every finger of the RAKE receiver at full precision during the entirety of each active communication link. Operating each finger of the RAKE receiver at full precision maintains audio quality during signal fading and when the signal contains multipath components. However, operating every finger of the RAKE receiver and the combiner at full precision when the incoming signal is of high quality needlessly consumes battery power. The embodiment described herein dynamically adjusts the duty cycle of the fingers of the RAKE receiver and varies the complexity of the combiner algorithms to save power when the signal is of high quality. 
     As shown in FIG. 5, one preferred embodiment comprises several correlators  510 , each of which couple to a combiner  516 . The output of a combiner control module  550  couples to the combiner  516  and each of the correlators  510 . The combiner control module has an input connected to the signal properties evaluation module  130 , discussed in conjunction with FIG.  1 . 
     The combiner  516 , which receives the signals from each of the fingers of the RAKE receiver, adds each of the multipath signals and provides an output to the other subsystems of the receiver. 
     In particular, each of the correlators  510  provides a portion of the incoming signal to the combiner  516 . In turn, the combiner  516  uses an algorithm to calculate parameter values that aid in the combination of each of the incoming multipath signals from the correlators  510 . These parameter values represent the required time shift, phase shift and amplitude adjustment necessary to properly combine each of the multipath signals. The combiner  516  processes the incoming signals using the parameter calculations and provides a combined signal at the output. 
     Advantageously, a receiver adopting the principles of the present invention includes the combiner control module  550 . The combiner control module  550  provides input to the combiner  516  and each correlator  510  to dynamically adjust the duty cycle of the correlators and the manner of operation of the combiner to reduce power consumption. The combiner control module  550  evaluates various characteristics of the incoming signal and, based on the evaluation, provides appropriate input to the combiner  516  and the correlators  510 . The combiner control module  550  obtains information regarding the incoming signal from the signal properties evaluation module  130 . In particular, the signal properties evaluation module  130  provides information regarding the signal dynamics, the signal to noise ratio, the signal interference level and the signal power level to the combiner control module  550 . Using this information, the combiner control module  550  adjusts the duty cycle of the correlators  510  and the manner of operation of the combiner  516  to reduce power consumption. 
     With regard to the correlators  510 , the combiner control module  550  alters the duty cycle of each correlator based on the incoming signal. For example, if the incoming signal is generally weak and contains a number of multipath components, then the combiner control module  550  enables the maximum number of correlators  510 , thereby capturing the weak signal. Alternatively, if the signal properties evaluation module  130  indicates that the signal is generally strong and comprises relatively few (one or two) multipath components, then the control module  550  instructs a number of the correlators  510  to suspend operation. Suspending operation of a number of the correlators  510  reduces the power consumption of the receiver, which extends battery life. Suspending operation of a number of correlators  510  reduces the input to the combiner  516 , which consequently reduces the processing burden on the combiner  516 . This further reduces the power consumption of the receiver. 
     The combiner control module  550  also instructs the combiner  516  to dynamically change the algorithms used for parameter estimation. In particular, mobile stations (i.e., a cellular telephone) may operate while stationary or while moving, such as during automobile travel. For a receiver, and in particular the combiner  516 , a significant amount of processing (and therefore power) is required to estimate the parameters used to calculate time shift  512 , phase shift  520  and amplitude adjustment  530  of each component of the incoming signal before summing with the summer  540  each adjusted signal component. Precise calculation of these parameters is vital during periods when the incoming signal includes significant multipath components, such as for example when the mobile station is moving or when reflecting objects such as building, are intermediate the mobile station and the base station. However, such complex calculations needlessly consume power during periods when the incoming signal does not include a plurality of significant multipath components, such as for example when the mobile station is generally stationary or when it possesses an obstruction free signal path to the base station. Instead of performing complex calculations, the parameters used to determine time shift, phase shift and amplitude adjustment are arrived at using calculations which consume less power or by fixing the parameter values for certain signal conditions. Thus, the power consumption may be reduced without compromising audio quality or communication link stability. 
     FIG. 7 illustrates an enhanced frequency estimator to provide adaptive frequency estimation (phase reconstruction) such as in the phase/frequency estimator  126  of FIG.  1 . As seen in FIG. 7, there is demodulator  710  provided for a pilot signal and demodulator  712  provided for a desired signal. A phase reconstruction block  714  provides phase estimation for the desired signal. Accordingly, an output of the phase reconstruction block  714  provides an input to the desired signal demodulator  712 . The incoming signal (after digital conversion in the present embodiment), provides an input to both the pilot demodulator  710  and the desired signal demodulator  712 . The phase reconstruction module  714  receives input from the pilot demodulator  710  and from the signal properties module  130  (see FIG.  1 ). More specifically, the signal properties module  130  provides signals to a dynamic phase reconstruction control module  716  which forms part of the phase reconstruction module  714 . The dynamic phase reconstruction control module  716  reacts to information from the signal properties module  130  and from the pilot demodulator  710  to dynamically control the phase reconstruction module  714  to accommodate changing signal conditions. More specifically, the phase reconstruction module operations can be adaptively controlled to change operations based on the particular signal properties at the time. 
     As known in the art, a phase reconstruction scheme can be very important because a small error in the estimated phase can result in a large loss for the desired signal. Typically, existing systems utilize the pilot signal which is transmitted at a higher power without full spreading codes so that it is much easier to demodulate. Accordingly, the demodulation allows determination of the phase of the incoming signal. Because the pilot signal and the desired signal are transmitted together, they experience similar or identical paths and interference to the receiver. During periods of high signal dynamics and multi-path components, frequency estimation becomes an important function of the system in order to avoid significant signal losses. 
     In the present invention, the frequency estimation algorithm, precision, or active periods may be controlled. More specifically, any one or more of the following parameters could be included in selecting two or more algorithms which can be selected based upon the pilot demodulation information or the pilot demodulation together with the signal properties module information. The processing rate may be increased or decreased. Such increase or decrease may be based on power level rather than tracking performance. The phase reconstruction filter  714  may actually be deactivated and activated only a few to several times a second during periods of high signal strength and low signal dynamics and fading. However, during high signal dynamics, where the signal may have multi-path components and the phase is changing rapidly, the filter may run constantly. In addition or alternatively, the precision of the phase reconstruction filter  714  can be modified. For instance, the precision can be changed from 16-bit to 8-bit in one embodiment. In addition or in combination with the other elements, the actual filter type could be changed. For instance, a FIR filter, IIR filter, sliding window filter, or other type of filter could be selected based upon the signal characteristics. 
     Finally, as shown in FIG. 7, the signal properties module  130  could play a significant role in the phase reconstruction decisions. Conventional designs typically involve using the pilot signal to determine frequency estimation. The pilot is easy to demodulate because of its high power and lack of full spreading codes. In spread spectrum systems, each base station may have many desired signals, each with its own spreading code transmitted in a particular direction from the base station. Typical base stations in spread spectrum systems may have three different directional sections, each which can have 10 to 20 signals with spreading codes (such as Walsh codes) for each signal. Accordingly, the signal from the base station includes a pilot plus several desired signals using several corresponding spreading codes. Typically, each mobile site demodulates the data resulting only from its own spreading code. However, because there are many other coded signals in the same collective signal, the present embodiment also involves utilizing the other spread spectrum signals not intended for the particular receiver in determining the phase reconstruction. In other words, the demodulated desired signal for other users can be used for tracking the phase, and, the tracking can be improved. Of course, the additional demodulation requires additional power; however, in periods of high signal dynamics, such increase in processing may be required in order to maintain a signal for the particular user in question. 
     In summary, in accordance with this embodiment of the present invention, several different features can come into play in impacting the phase reconstruction (frequency estimation) operations of the receiver. 
     GSM Demodulator having Reduced Power Consumption Design 
     In yet another embodiment, power saving features are integrated with a receiver operating in accordance with Global System for Mobile Communications (GSM). 
     FIG. 6 illustrates a typical Global System for Mobile Communication (GSM) demodulator. Input lines carrying baseband I (in-phase) and Q (quadrature-phase) data connect to an automatic gain control module  610  and a signal level estimator  612 . The output of the signal level estimator  612  connects to the AGC module  610 . 
     The output of the AGC module  610  connects to a cross-correlator  614 . The cross-correlator&#39;s output connects to each of a matched filter  617 , a matched filter extractor  618 , and a timing recovery unit  620 . The output of the matched filter extractor  618  feeds directly into the matched filter  617 . The output of the matched filter  617  and the timing recovery unit  620  both connect to a Maximum Likelihood Sequence Estimation (MLSE) detector  622 . 
     The MLSE detector  622  couples to the input of a decryption unit  624  and the output of the decryption unit feeds into a deleaver  626 . The deleaver  626  outputs data to a convolutional decoder  630 . The convolutional decoder  630  in turn connects to a block decoder  632 . The block decoder  632  provides output on a data out line. 
     In operation, the automatic gain control module  610  adjusts the input signal level of the baseband I and Q data (hereinafter signal) for optimal performance during the subsequent demodulation operations as well understood in the art. The incoming signal also enters a signal level estimator  612  that estimates the power level of the incoming signal. Estimating the signal power level serves two purposes; first, a GSM communication system adapts its performance based on the strength of the received signal at each of the mobile stations; and second, the receiver adjusts the gain of the input signal for subsequent demodulation processes. Accordingly, the modulator provides the output of the signal level estimator  612  to the AGC module  610  so that the gain of signal may be adjusted appropriately. 
     The cross-correlator  614  compares the received data to a known training sequence or a training sequence included mid-sample in the received data burst. The cross-correlator locates the beginning of each burst of data using the known 26 symbols located at the center of each burst. As known in the art, bursts are sent in a generally 0.5 millisecond time frame followed by 4.5 millisecond pause. The cross-correlator, having located or correlated the known 26 symbols is able to locate the beginning of the data transmission. 
     Next, the signal undergoes filtering and timing recovery. The matched filter extractor  618  models an ideal matched filter to reverse the effects of the transmission channel and any inter-symbol interference introduced by the pulse shape. The timing recovery unit  620  determines the proper timing of the incoming signal to locate the center of the burst which in-turn allows the receiver to correctly separate and demodulate the individual symbols. 
     The next phase of the demodulation process comprises MLSE detection. The MLSE detector  622  performs a sophisticated detection algorithm that declares each received symbol to be a 1 or 0 and provides a measure of the certainty of each binary decision. As known in the art, the algorithms of the MLSE detector  622  employ a dynamic programming model to simultaneously demodulate an entire half-burst (typically 58 bits) of data. While certain advantages exist in performing demodulation over the half-burst instead on a symbol-by-symbol bases, half-burst demodulation consumes a significant amount of power during operation. 
     After MLSE detection, the signal enters a decryption unit  624  to reverse the anti-eavesdropping measures undertaken by the transmitter. Next, the signal enters the deleaver  626 , wherein the transmitted bits are dispersed over several time division multiple access (TDMA) bursts to provide robustness in the presence of fading. The deleaver  626  rearranges the received bits into message blocks i.e. into the original order existing prior to transmission. 
     The output of the deleaver  626  progresses to the input of the convolutional decoder  630 . The convolutional decoder  630  performs convolutional decoding on the received data. Convolutional coding and decoding provides means to detect and correct data errors introduced during transmission. In particular, convolutional coding adds coding to the data so that the convolutional decoder may accurately reconstruct the transmitted data, even if some of the data bits become corrupted during transmission. 
     After convolutional decoding, the signal enters the block decoder  632  to undergo reverse block coding. Block coding provides redundancy, typically parity bits. These parity bits are typically often transmitted at the end of a sequence of data bits so that upon receipt by the receiver, the block decoder  632  may perform reverse block coding to determine if errors exist in the data stream. After undergoing block decoding, the signal exits the block decoder  632  for further processing in other parts of the receiver, such as a vocoder (not shown). 
     In one embodiment of the present invention, the receiver comprises a digital signal processor (DSP) coded implementation of a GSM receiver. The inventors recognize that the most complex and power consuming operation is typically the MLSE detection algorithm of the MLSE detector  622 . For example, in some DSP based implementations, the MLSE detection may comprise up to 50% of the complexity in relation to total DSP operations. While the advantages of the MLSE detector are worthy of its power needs during periods of poor signal quality, the MLSE detector needlessly consumes power when the signal is robust. 
     Another very complex and power consuming component is the cross-correlator  614  because it operates over a broad range of delays to correctly locate the center of the data burst. Cross-correlation in DSP based implementations may comprise up to 30% of the total DSP operations. 
     In one embodiment, a GSM receiver is configured to eliminate a substantial portion of the computational requirements of the receiver by monitoring the timing recovery unit  620  for rapid movement from center on a burst-by-burst basis. In such an embodiment, the receiver would also include a cross-correlator controller  616 . The cross-correlator controller  616  connects to the cross-correlator and the timing recovery unit. The cross-correlator controller  616  obtains data from the timing recovery unit  620  and depending on the timing of the incoming signal, changes the operation of the cross-correlator accordingly. In particular, if the incoming signal does not demonstrate rapid movement from burst center then the cross-correlator controller  616  instructs the cross-correlator  614  to operate over a more narrow range of delays. For example, in normal operation the cross-correlator  614  may operate over ±5 data symbols. Under ideal situations, such as when the burst center is generally stable, performing cross-correlation over ±2 symbols may be adequate. In short, when assuming the data transmission to be generally stable, the cross-correlator can anticipate little change in burst center and reduce computational complexity such as, for example, evaluating fewer symbols. Reducing the computational complexity and duration of the cross-correlator  614  reduces the power consumption of the receiver which, in turn, extends battery life. If the timing recovery unit  620  detects rapid movement from burst center, then the cross-correlator controller  616  instructs the cross-correlator  614  to resume operation over a broader range of delays. In this fashion, the cross-correlator controller  616  adjusts the operation of the cross-correlator  614  to save power during periods when the signal is stable without degrading signal quality. 
     In another embodiment, the receiver includes a MLSE controller  621  connected to the MLSE detector  622 , the matched filter  617 , and the output of the signal level estimator  612 . The MLSE controller receives input from the matched filter  616  and the signal level estimator  612 . The MLSE controller  621  monitors both the signal level of an incoming transmission and the response to the matched filter  617 . If the incoming signal level is high and the response to the match filter  617  indicates that the signal is arriving over a generally clear channel, then the receiver suspends operation of the complicated MLSE detector  622 , and instead implements a simple bit-by-bit Minimum Shift Keying (MSK) demodulator. MSK demodulators are known by those of skill in the art, and require a trivial amount of computational resources, and thus battery power, in relation to the MLSE algorithms of the MLSE detector  622  due to their operation on a bit-by-bit basis instead of the typical 58 bit delay of the MLSE detector  622 . 
     A receiver adopting MSK demodulation over MLSE algorithms consumes less power than a receiver utilizing only MLSE detection algorithms. Thus, if the signal is robust, the power intensive MLSE detector operation may be suspended and replaced with bit-by-bit MSK demodulation. Alternatively, if the signal changes causing the response to the matched filter  617  to not resemble a impulse and if the signal level decreases, then the MLSE controller  621  suspends operation of the bit-by-bit MSK demodulator and resumes operation of the MLSE algorithms. In this fashion, the MLSE controller  621  reduces power consumption of the receiver without sacrificing audio quality. As explained in the embodiment above, the signal level estimator and the match filter are used to determine the signal quality. Other quality measurements such as automatic gain control could be used to indicate the receiver algorithm which will be implemented for the remainder of the receiver. 
     Although the foregoing description of the preferred embodiment of the present invention has shown, described and pointed out the fundamental novel features of the invention, it will be understood that various omissions, substitutions and changes in form of the detail of the apparatus as illustrated as well as the uses thereof, may be made by those skilled in the art without departing from the spirit from the present invention. Consequently, the scope of the invention should not be limited to the foregoing discussion, but should be defined by the appended claims.