Abstract:
Each row of a row based shader engine comprises a shader pipe array, a texture filter, and a level one texture cache system. The shader pipe array accepts texture requests for a specified pixel from a resource and performs associated rendering calculations, outputting texel data. The texture mapping unit receives texel data from a level one cache system and through formatting and bilinear filtering interpolations, generates a formatted bilinear result based on a specific pixel&#39;s corresponding four texels. Utilizing multiple rows of a row based shader engine within the shader engine allows for the parallel processing of multiple simultaneous resource requests. A method for texture filtering utilizing a row based shader engine is also presented.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 61/057,504 filed May 30, 2008; U.S. Provisional Patent Application No. 61/057,492 filed May 30, 2008; U.S. Provisional Patent Application No. 61/057,499 filed May 30, 2008; U.S. Provisional Patent Application No. 61/057,513 filed May 30, 2008, and U.S. Provisional Patent Application No. 61/057,483 filed May 30, 2008; which are incorporated by reference herein in their entireties. 
     
    
     BACKGROUND 
       [0002]    1. Field of the Invention 
         [0003]    The present invention is generally directed to computing operations performed in computing systems, and more particularly directed to graphics processing tasks performed in computing systems. 
         [0004]    2. Related Art 
         [0005]    A graphics processing unit (GPU) is a complex integrated circuit that is specially designed to perform graphics processing tasks. A GPU can, for example, execute graphics processing tasks required by an end-user application, such as a video game application. In such an example, there are several layers of software between the end-user application and the GPU. 
         [0006]    The end-user application communicates with an application programming interface (API). An API allows the end-user application to output graphics data and commands in a standardized format, rather than in a format that is dependent on the GPU. Several types of APIs are commercially available, including DirectX® developed by Microsoft Corp. and OpenGL® developed by Silicon Graphics, Inc. The API communicates with a driver. The driver translates standard code received from the API into a native format of instructions understood by the GPU. The driver is typically written by the manufacturer of the GPU. The GPU then executes the instructions from the driver. 
         [0007]    A GPU produces the pixels that make up an image from a higher level description of its components in a process known as rendering. GPU&#39;s typically utilize a concept of continuous rendering by the use of pipelines to processes pixel, texture, and geometric data. These pipelines are often referred to as a collection of fixed function special purpose pipelines such as rasterizers, setup engines, color blenders, hieratical depth, texture mapping and programmable stages that can be accomplished in shader pipes or shader pipelines, “shader” being a term in computer graphics referring to a set of software instructions used by a graphic resource primarily to perform rendering effects. In addition, GPU&#39;s can also employ multiple programmable pipelines in a parallel processing design to obtain higher throughput. A multiple of shader pipelines can also be referred to as a shader pipe array. 
         [0008]    Manufacturing defects and subsequent failures can occur somewhere within a pipeline and can become apparent as a shader pipe array performs its ongoing rendering process. A small defect or failure in a system without any logic repair can be fatal and render the device defective. In addition, GPU&#39;s also support a concept known as texture mapping. Texture mapping is a method used to determine the texture color for a texture mapped pixel through the use of the colors of nearby pixels of the texture, or texels. The process is also referred to as texture smoothing or texture interpolation. However, high image quality texture mapping requires a high degree of computational complexity. 
         [0009]    Given the ever increasing complexity of new software applications and API shader language advancements, the demands on GPU&#39;s to provide high quality rendering, texture mapping and generalized compute, computation complexities are further increasing. 
         [0010]    In addition, GPUs equipped with a Unified Shader also simultaneously support many types of shader processing, from pixel, vertex, primitive, surface and generalized compute are raising the demand for higher performance generalized memory access capabilities. 
         [0011]    What are needed, therefore, are systems and/or methods to overcome the aforementioned deficiencies. Particularly, what is needed is a scalable unified parallel processing based design capable of executing shader instructions, texture mapping operations and generalized load/store operations with the additional ability to overcome the effects of a defective internal sub-circuit with minimal impact on overall system performance. 
       SUMMARY OF THE INVENTION 
       [0012]    This section is for the purpose of summarizing some aspects of the present invention and to briefly introduce some preferred embodiments. Simplifications or omissions may be made to avoid obscuring the purpose of the section. Such simplifications or omissions are not intended to limit the scope of the present invention. Consistent with the principles of the present invention as embodied and broadly described herein, the present invention includes method and apparatus for a multiple row, parallel processing based unified shader engine filtering system with the ability to overcome the effects of a defective shader pipe. Each row of the unified shader engine filtering system comprises a shader pipe array, texture mapping unit, and a level one texture cache system. Each row based unified shader module is configured to accept instructions from a executing shader program, including input, output, ALU, and texture or general memory load/store requests with address data from register files in the shader pipes and program constants to generate the return texel or memory data based on state data controlling the pipelined address and filtering operations for a specific pixel, vertex, primitive, surface or general compute thread. Each texture mapping operation is configured based on the shader program instruction and constants to generate a formatted interpolation based on texel data stored in the level one texture cache system. 
         [0013]    In an embodiment of the invention, each row of the unified shader engine filter system further comprises a redundant shader pipe system. The redundant shader pipe system is configured to process shader pipe data originally destined to a defective shader pipe in the shader pipe array of the same row. In this embodiment a redundant shader switch transfers shader pipe data originally destined to a defective shader pipe to the redundant shader pipe system for processing. In addition, the redundant shader switch places the processed shader pipe data at the correct column of output data at the appropriate time. An error within the shader pipe array can be static or intermittent, and could be caused, for example, because of a manufacturing or post-manufacturing defect, component degradation, external interference, and/or inadvertent static discharge, or other electrical or environmental condition or occurrence. The redundant shader pipe enables the recovery of devices with a defective sub-circuit. 
         [0014]    In embodiments of this invention with configurations containing two or more rows of Unified Shader Module, the Unified Shader Module itself can be configured to be a repairable unit. In such an embodiment workloads destined to a defective Unified Shader Module will instead be sent to a redundant Unified Shader Module to process all ALU, texture, and memory operations. This increases the portion of the device that is covered by repair significantly due to the inclusion of texture mapping unit and L1 cache system and thus significantly improves on the yield of such device. 
         [0015]    In another embodiment each texture mapping unit in the unified shader module of the unified shader engine filter system further comprises a pre-formatter module, an interpolator module, an accumulator module, and a format module. The pre-formatter module is configured to receive texel data and convert it to a normalized fixed point format. The interpolator module is configured to perform an interpolation on the normalized fixed point texel data from the pre-formatter module and generate re-normalized floating point texel data. The accumulator module is configured to accumulate floating point texel data from the interpolator module to achieve the desired level of bilinear, trilinear, and anisoptropic filtering. The format module is configured to convert texel data from the accumulator module into a standard floating point representation. 
         [0016]    Further features and advantages of the invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings. It is noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0017]    The accompanying drawings, which are incorporated in and constitute part of the specification, illustrate embodiments of the invention and, together with the general description given above and the detailed description of the embodiment given below, serve to explain the principles of the present invention. In the drawings: 
           [0018]      FIG. 1  is a system diagram depicting an implementation of a single Unified Shader Module. 
           [0019]      FIG. 2  is a system diagram depicting an implementation of a single Unified Shader Module illustrating the details of the shader pipe array. 
           [0020]      FIG. 3  is a system diagram depicting an implementation of a single Unified Shader Module illustrating the details of the texture mapping unit. 
           [0021]      FIG. 4  is a system diagram depicting an implementation of a multi-row Unified Shader Module based unified shader engine. 
           [0022]      FIG. 5  is a system diagram depicting a detailed implementation of a multi-row Unified Shader Module based unified shader engine filtering system. 
           [0023]      FIG. 6  is a flowchart depicting an implementation of a method for a unified shader engine filtering system. 
       
    
    
       [0024]    Features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number. 
       DETAILED DESCRIPTION  
       [0025]    The invention will be better understood from the following descriptions of various “embodiments” of the invention. Thus, specific “embodiments” are views of the invention, but each is not the whole invention. In one respect, the present invention relates to a multiple row, parallel processing based unified shader engine filtering system whereby each row of the unified shader engine filtering system processes a shader program instruction on input pixel, vertex, primitive, surface or compute work items to create output data for each item using generated texel data or memory load/store operations In embodiments of this invention, bilinear texture filtering, trilinear texture filtering, and anisotropic texture filtering are applied to texel data stored in a multi-level cache system. In another embodiment, a redundant shader system can be added and configured to each row to process shader pipe data destined to a defective shader pipe within that row&#39;s unified shader module. Additionally, a unified shader module can be reserved as a redundant subsystem and a data destined for a defective unified shader model can be sent to the redundant unified shader module. This increases the portion of the device that is covered by repair significantly due to the inclusion of texture mapping unit and L1 cache system and thus significantly improves on the yield of such device. 
         [0026]    While specific configurations, arrangements, and steps are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art(s) will recognize that other configurations, arrangements, and steps can be used without departing from the spirit and scope of the present invention. It will be apparent to a person skilled in the pertinent art(s) that this invention can also be employed in a variety of other applications. 
         [0027]    References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to incorporate such a feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. 
         [0028]    While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those skilled in the art with access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the invention would be of significant utility. 
         [0029]      FIG. 1  is an illustration of a single row of a shader engine filter system  100  according to an embodiment of the present invention. System  100  comprises a sequencer  110  and a unified shader module  120 . Row based unified shader module  120  comprises a shader pipe array  122 , an optional redundant shader pipe array  124 , a texture mapping unit  126 , and a level one texture cache system  128 . 
         [0030]    Shader pipe array  122  performs ALU operations on input data. Sequencer  110  controls the shader program instruction issue for workloads contained in the shader pipe array  122  and the flow of data through shader pipe array  122 . In addition, in an embodiment where the redundant shader pipe array  124  is present, sequencer  110  reacts to a defective shader pipe within shader pipe array  122  by scheduling instructions to the appropriate redundant units. 
         [0031]    Sequencer  110  can issue a texture or load/store operation that will initiate the shader pipe array to send addresses with request to texture mapping unit  126 . In this instance texture mapping unit  126  generates appropriate addresses to the level one cache system  128  that contains texel data associated with source addresses. The level one cache system  128 , after receiving the addresses, will return the associated texel or memory data to texture mapping unit  126 . 
         [0032]      FIG. 2  is an illustration of a single row of a unified shader module  120  that includes a more detail view of the shader pipe array  122  according to an embodiment of the present invention. In this embodiment, shader pipe array  122  comprises one or more shader pipe blocks, here represented as SP_ 0  through SP_M, labeled  210 - 1  through  210 -M, where “M” represents a positive integer greater than one. 
         [0033]    In an embodiment where redundant shader pipe array  124  is present, if sequencer  110  identifies, as an example, that the shader pipe located in shader pipe block SP — 1 is defective, then the shader pipe data destined to the defective pipe would be sent to the redundant shader pipe array  124  via the input stream by the input module and processed by the redundant shader pipe. All texture mapping unit requests would be intercepted by the redundant unit when instructed via horizontal control path  211 , from sequencer  110 . Once redundant shader pipe array  124  processes the shader pipe data initially destined to the defective shader pipe, the processed redundant data would be transferred from redundant shader pipe array  124  back to the output stream of unified shader module  122  for merging at the output model. 
         [0034]    In an embodiment, the redundant shader pipe array  124  consists of a single block, and therefore can only process shader pipe data destined to a single defective shader pipe at a time. In another embodiment wherein redundant shader pipe array  124  comprises multiple redundant shader blocks, then redundant shader pipe array  124  could process shader pipe data destined to more than one defective shader pipe simultaneously. 
         [0035]      FIG. 3  is an illustration of a single row of a unified shader module  120  that includes a more detail view of texture mapping unit  126  according to an embodiment of the present invention. In this embodiment, shader pipe array  122  generates a texture or memory load/store request to texture mapping unit  126  that comprises an address generator  318 , a pre-formatter module  310 , an interpolator module  312 , an accumulator module  314 , and a format module  316 . The texture mapping unit  126  receives a request from shader arrays  122  and  124  and sequencer  110  respectively, and processes the instruction in the address generator  318  to determine the actual addresses to service. Resulting texel data received from the level one cache system  128  and, after the data is processed in pre-formatter module  310 , interpolator module  312 , accumulator module  314 , and format module  316 , is sent back to the requesting resource in shader pipe array  122  and/or redundant shader pipe array  124 . Pre-formatter module  310  is configured to receive texel data and performs a block normalization thereby generating normalized fixed point texel data. Interpolator module  312  receives the normalized fixed point texel data from pre-formatter module  310  and performs one or more interpolations, each of which are accumulated in accumulator module  314 , to achieve the desired level of bilinear, trilinear, and anisotropic texture filtering. Format module  316  converts the accumulated texel data in accumulator module  314  to a standard floating point representation for the requesting resource, shader pipe array  122  and/or redundant shader pipe array  124 . 
         [0036]      FIG. 4  illustrates a unified shader engine filter system with multiple rows according to an embodiment of the present invention. In this embodiment, unified shader engine system  400  comprises up to “N” rows of row based shader engines as shown by  120 - 1  through  120 -N, where N is a positive integer greater than one. The unified shader module  120  has been previously described and illustrated in  FIGS. 1 ,  2 , and  3 . 
         [0037]      FIG. 5  is an illustration of a multi-row unified shader module  120  that includes a more detail view of the shader pipe array  122  in each row according to an embodiment of the present invention. System  500  comprises a plurality of row based unified shader modules labeled  120 - 1  through  120 -N, where N is a positive integer greater than one. In addition, system  500  comprises a sequencer  110  and a redundant shader switch (RSS) represented as RSS-In  510  and RSS-Out  512 . 
         [0038]    RSS-In  510  controls the flow of input data to the unified shader modules  120 - 1 . Sequencer  110  controls data processing with shader program instructions for each unified shader module  120 - 1  through  120 -N as well as instructing a redundant shader pipe to process data destined to the defective shader pipe that occurs within unified shader module  120 - 1  through  120 -N. In the event that there is no defective shader pipe, the processed data continues to RSS-Out  512 . 
         [0039]    However, in the event that the unified shader engine filtering system is notified of a defect state, the data provided by sequencer  110  replaces a defective shader pipe in a respective unified shader module  120 - 1  through  120 -N, by notifying the RSS-In  510  of the location of the defective shader pipe. RSS-In  510  then transfers the shader pipe data destined to the defective shader pipe via a direct horizontal data path in the RSS-In  510  module from the defective shader pipe data array column to redundant shader pipe array  124  of the same row. Redundant shader pipe array  124  is responsible for processing the shader pipe data that was destined to the defective shader pipe. Once the shader pipe data is processed it is sent to the RSS-Out  512  via sequencer  110  issued export instruction that realigns the processed shader pipe data at the correct location and at the proper time as it would have been if the shader pipe had not been found to be defective. 
         [0040]    In  FIG. 5 , as an example, if sequencer  110  identifies the shader pipe located in shader pipe block SP_ 12  as being defective, then RSS-In  510  would transfer the shader pipe data destined to the defective pipe via an internal horizontal data path from SP_ 12  to redundant shader pipe  2 ,  124 - 2 , for processing. Once redundant shader pipe  2 ,  124 - 2 , processes the shader pipe data that was destined to the defective shader pipe, the processed shader pipe data would be transferred from redundant shader pipe  2 ,  124 - 2 , to RSS-Out  512  where it is realigned with the other shader pipe output data. 
         [0041]      FIG. 6  is a flowchart depicting a method  600  for texture mapping operating using a unified shader engine filtering system with a plurality of row based shader modules. Method  600  begins at step  602 . In step  604 , multiple texture fetch instructions can be received by multiple unified shader engine modules in parallel. In step  606 , each participating unified shader module in parallel generates a source set of addresses based on the shader program instructions for the specified set of pixels, vertices, primitives, surfaces, or compute work items. In step  608  each texture mapping unit  126 , in parallel, can retrieve texel data from a level one cache system of a respective unified shader module. In step  610  each texture mapping unit calculates a formatted accumulated interpolation for each set of output texels based on the originating shader instructions. Method  600  concludes at step  612 . 
         [0042]    The functions, processes, systems, and methods outlined in  FIGS. 1 ,  2 ,  3 ,  4 ,  5 , and  6  can be implemented in software, firmware, or hardware, or using any combination thereof. If programmable logic is used, such logic can execute on a commercially available processing platform or a special purpose device. 
         [0043]    As would be apparent to one skilled in the relevant art, based on the description herein, embodiments of the present invention can be designed in software using a hardware description language (HDL) such as, for example, Verilog or VHDL. The HDL-design can model the behavior of an electronic system, where the design can be synthesized and ultimately fabricated into a hardware device. In addition, the HDL-design can be stored in a computer product and loaded into a computer system prior to hardware manufacture. 
         [0044]    It is to be appreciated that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims. The Summary and Abstract sections can set forth one or more but not all exemplary embodiments of the present invention as contemplated by the inventor(s), and thus, are not intended to limit the present invention and the appended claims in any way. 
         [0045]    The present invention has been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. 
         [0046]    The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance. 
         [0047]    While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.