Abstract:
An improved current switch circuit having an active load. The active load comprises a current source at the collectors of the switch transistors which generates a current which is less than the current generated by the current source at the emitters of the switch transistors. The active load also includes both means for supplying the current difference between said source currents as supplementary current to the emitter current source when the associated switch transistors are conductive as well as means for diverting the source current at the collectors of the switch transistors when they are non-conductive. 
     Depending on the current generated by the current sources, the performance of the circuit can be selected to optimize power dissipation versus switching speed. The circuit utilizes a minimum number resistors, thereby using a minimum amount of semiconductor area and insuring lower power dissipation than is available with prior art circuits.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to transistor switching circuits. In particular it relates to an improved switching circuit of the current switch type. 
     2. Description of the Prior Art 
     The performance of digital computers and other systems employing switching circuits are dependent upon the switching speed of the individual circuits. In general, the higher the switching speed of a circuit, the higher may be the speed of the system. 
     The current switch disclosed by H. S. Yourke in U.S. Pat. No. 2,964,652 is superior to all other comparable commercially-available switching circuits with respect to switching speed. It is well known, for example, that the current switch circuit is around five to ten times faster than comparable bipolar resistor-transistor-logic (RTL), diode-transistor-logic (DTL) and the transistor-transistor logic (TTL) circuit families. Moreover, it is far superior to any circuit family using field effect transistors. 
     In addition to high speed operation, the current switch offers excellent DC stability and good noise immunity. 
     For these reasons, the current switch logic family is used quite extensively in high speed digital circuitry and high performance systems requiring digital components. However, the current switch suffers from certain disadvantages as compared, say, to TTL and DTL. In particular, the power dissipated by the individual logic circuit is greater for the current switch than for the other named circuit families, primarily because one portion of the circuit or the other is always conductive. Current relates to power which must be dissipated as heat. 
     At the present time, in fact, the number of current switch circuits which can be &#34;packed&#34; on a semiconductor chip of a given size is limited only by the power dissipated within the chip. Above a certain level, around 5 watts, it is virtually impossible to dissipate sufficient heat to avoid destroying the circuits on the chip completely. At the present time the art is limited to accommodating around 600 current switch circuits on a chip around 200 mils square. It is physically possible to place more circuits on the chip from the standpoint of semiconductor area, surface wiring and input/output pads and pins. However, the circuit quantity is power-limited. 
     Thus, in general, it is possible to place more TTL or DTL logic circuits on a semiconductor chip than current switch circuits. For well-known reasons of reducing manufacturing costs and increasing reliability, the art is continually attempting to accommodate a maximum number of circuit components on a single semiconductor chip. 
     The interaction between circuit speed and power dissipation has directed the attention of circuit designers in recent years to the concept of &#34;speed-power product&#34;, which is simply the multiplication of average circuit switching speed and the power dissipated by the circuit. For example, a circuit switching at 10 nanoseconds and dissipating 5 milliwatts of power (heat) has a speed-power product of 50 picojoules. At the present time, the speed-power product of advanced TTL circuits is practically equal to that of standard current switch circuits. 
     One reason for the relatively high power required by present current switching circuits is the need for load resistors through which all current flows. As a result, the resistors dissipate a good deal of heat (as well as requiring a great amount of area as compared to transistors or diodes). 
     SUMMARY OF THE INVENTION 
     It is, therefore, one object of our invention to decrease the speed-power product of current switch circuits. 
     It is a further object of our invention to reduce to a practical minimum the number or resistors required in a current switch circuit which is suitable for modern digital applications. 
     These and other objects of our invention are achieved by providing a standard current switch circuit with an active load comprising current sources at the collectors of the switch transistors which generate a current which is less than the current generated by the current sink at the emitters of the switch transistors. The active load also includes means for supplying the current difference between source and sink currents as supplementary current to the sink when the associated switch transistors are conductive and means for diverting the source current to a reference potential when the switch transistors are non-conductive. 
     In the preferred embodiment, each current source is a transistor having a conductivity type opposite that of the switch transistors. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a circuit diagram of one embodiment of our invention. 
     FIG. 2 illustrates a simpler version of the circuit of FIG. 1. 
     FIG. 3 is a circuit diagram of an alternate embodiment of our invention. 
     FIG. 4 illustrates a preferred connection of a plurality of circuits of the type shown in FIG. 3. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Turning to FIG. 1, the current switch logic circuit comprises basically a plurality of NPN switch transistors T1, T2, T3 and TR, connected between a first reference potential, VCC, and a constant current sink denoted ICS. As is well known, the current sink may comprise an NPN transistor having its collector connected to the emitters of the switch transistors, its base connected to a reference bias and its emitter connected to VEE through a resistor. Alternatively, the current sink may be a high value resistor. 
     The base of reference switch transistor TR is connected to an input reference potential, denoted VREF, which preferably has a value mid-way between the voltage values corresponding to the binary 1 and binary 0 bits of information of the logic circuit. The out-of-phase output of the circuit, v out , is taken from the collector of T1, T2 and T3; and the in-phase output v out , is taken from the collector of TR. 
     In the preferred embodiment, VREF equals -1.25 volts and the logic input levels at input switch transistors T1, T2 and T3 are approximately -1.0V up level and -1.5 V down level. 
     The active load for input switch transistors T1, T2 and T3 comprises transistors TEO and TPO, resistor RCC, diode DO and potential VT. Transistor TPO, which is a complementary conductivity type (PNP) with respect to the switch transistors T1, T2, and T3, is connected to the collectors thereof. The emitter of TPO is connected to a source of potential VCC through resistor RCC. Resistor RCC, diode DO and potential VT set the current ICPO available through TPO to the collectors of T1, T2 and T3. Thus, TPO functions as a constant current source for its associated switch transistors. Current ICPO is always less than current ICS. Depending on the particular design characteristics desired, RCC is generally around 0.7 kilohms. 
     Diode DO is connected between the collector and base of TPO. The cathode of DO is connected to a reference potential VT. Diode DO and potential VT function as a path for diverting current ICPO when switch transistors T1, T2 and T3 are non-conductive. Diode DO and VT also serve to define the most positive level, i.e., the up level, at output terminal v out . Diode DO is advantageously a Schottky Barrier diode to assure fast switching and because it can be easily integrated with the transistors in a semiconductor chip. 
     In the preferred embodiment, VT equals -1.5V and the forward voltage drop of DO equals 0.5 V. This sets the logic output levels at v out  at approximately -1.5V down level and -1.0V up level. 
     Transistor TEO is connected between VCC and the collectors of transistors T1, T2 and T3. TEO functions as a means for supplying supplementary current IENO, which is the difference between ICS and ICPO, when any one of transistors T1, T2 or T3 are conductive. Thus: 
     (1). ICS = ICPO + IENO 
     Teo also serves to define the most negative level, i.e., the down level at terminal v out . 
     The active load for switch transistor TR comprises transistors TEI and TPI, diode, DI, resistor RCC and VT. 
     Switch transistor TR is connected to these elements in the same fashion as diode DO, transistors TPO and TEO are connected to transistors T1, T2 and T3. 
     Because the active loads for each side of the circuit in FIG. 1 are relatively isolated from each other, the ICPO currents from TPO and TPI need not be identical. In fact, it may be desirable to set the ICPO current through TPO greater than the ICPO current through TPI because of the greater capacitance at the collectors of T1, T2 and T3 as compared to that at the collector of TR. 
     In that case, resistor RCC would be removed and displaced by a pair of resistor RO and RI, between VCC and the emitters of TPO and TPI, respectively. In addition, electrical connections 1 and 2 would be deleted. Such a configuration is illustrated by means of phantom lines in FIG. 1. Typically, resistor RO would have a value somewhat less than the value of RI, e.g., RO=1.3 kilohms and RI = 1.5 kilohms. 
     For convenience and ease of description in the specification, we have designated ICS as a current sink and TPO as a current source in terms of positive circuit flow between the reference potentials VCC and VEE. Generally speaking, however, each is broadly denoted a current source in the art, with the significant consideration being that ICS, ICPO and IENO tend to flow in the same direction between VCC and VEE. 
     OPERATION ON THE CIRCUIT IN FIG. 1 
     Transistors TPO and TPI are always conducting current; and it is critical for the operation of our circuit that current ICPO generated from either of the transistors TPO or TPI is always less than the current ICS. 
     Assume that the inputs at IN1, IN2 and IN3 are all at a down level below the potential VREF at the base of TR. In this condition transistors T1, T2 and T3 are off and TR is on, conducting current ICS. Because ICS is greater than ICPO, transistor TEI starts to conduct supplementary current IENO. The output signal at inphase terminal v out  is then equal to the output reference potential VT, i.e., -1.5 V down level. 
     The reason for this is as follows: vI equals the potential VT plus the base-emitter voltage drop (V BE ) of transistor TPI. Similarly, v out  is equal to potential vI at the base of TEI minus the V BE  of transistor TEI when it is conducting. Because the V BE  &#39;s of the transistors are substantially the same, the effects of the V BE  &#39;s of TPI and TEI offset each other; and v out  equals VT when transistor TR is conducting. V, 
     Simultaneously with the above operation and considering the output at terminal v out , transistor TR is conducting current ICPO. However, since transistors T1, T2 and T3 are off, all of the current ICPO from TPO flows through diode DO to terminal VT. This causes terminal v out  to rise to a potential above VT which is equal to the forward voltage drop (V f ) of diode DO. As previously noted, diode DO is advantageously a Schottky Barrier diode having a potential drop of around 0.5 V. Therefore the potential at terminal v out  is -1.5V + 0.5V = -1.0V up level. 
     The operation of the circuit when either T1, T2 or T3 are turned on, as by a -1.0V signal at any combination of the inputs, is similar. When either T1, T2 or T3, or any combination thereof turn on, the reference switch transistor TR turns off. Current ICPO from transistor TPO is thereby transmitted through whichever one of transistors T1, T2 or T3 is conductive. Since ICS is greater than ICPO, transistor TEO turns on. (With TR off, TEI turns off). The output potential at v out  then falls to VT, -1.5 V, and the potential at v out  rises to -1.0 V. 
     The advantages of our circuit in FIG. 1 reside in the fact that its AC performance is proportional to the current level ICS and the Beta of the complementary transistors TPO and TPI. For example, with a Beta of 3 for the complementary transistors, ICS set to 0.75 mA and ICPO set to 0.5 mA, an average circuit delay of 0.5 nanosecond is achieveable. The power dissipation is approximately 3.0 mW, for a speed-power product of 1.5 picojoules. With higher speed, the power dissipation is greater, and is selectable over a wide range depending on the circuit designer&#39;s selection of current levels. To a first approximation the down-going transition is a function of the difference between the current levels ICS and ICPO, i.e., supplementary current IENO. 
     Another advantage of the circuit is that the up and down levels at the outputs are quite independent of resistor tolerance or tracking. The output level swings are a function solely of the V BE  &#39;s of transistors TEO, TPO, TEI and TPI and the forward voltage drops of the schottky barrier diodes, DO and DI. 
     Moreover, the circuit requires only one or two resistors, which may be integrated within the semiconductor chip containing the circuits. 
     The circuit in FIG. 2 may be used in the event that only the out-of-phase output, v out , is desired. In this event, no active load is required at the collector of transistor TR. Hence, transistors TEI, TPI and diode DO are omitted from the circuit. In addition, because current requirements are roughly halved, resistor RCC is replaced by RCC&#39; which has a value about double that of RCC, i.e., RCC&#39; = 1.4 kilohms. In all other significant respects, the circuit in FIG. 2 is identical to that in FIG. 1. 
     Similarly, if only the in-phase output, v out , were desired, no active load would be required at the collectors of transistors T1, T2 and T3. In this event, transistors TEO, TPO and diode DO would be omitted from the circuit in FIG. 1 and resistor RCC replaced by RCC- 
     Although the preferred embodiments in FIGS. 1 and 2 use NPN transistors as the switch transistors and PNP transistors as the constant current sources, it will be understood that the conductivity types could be reversed, with appropriate changes in potential and signal polarity. Moreover, for the sake of clarity we have identified ICS, in the sense of positive current flow, as a current sink and transistors TPO and TPI as current sources. Obviously, we could interchange these terms. The important point, from the standpoint of clear description, is that the currents ICPO and ICS both tend to flow in the same direction between the first and second reference potential VCC and VEE. 
     FIG. 3 is an embodiment of our invention which is quite similar to that of FIG. 1 except that it requires only a single resistor RB for a plurality of current switch circuits. Typically, resistor RB and diode TPB may serve four current switch circuits. 
     Because the circuit in FIG. 3 is quite similar to that in FIG. 1 in its basic components, the components in FIG. 3 which are similar to those in FIG. 1 are denoted by the prime of the same alpha-numerical designation. Thus, for example, transistor TEO in FIG. 1 is similar to transistor TEO&#39; in FIG. 3, and so on. For this reason, the description which follows does not repeat in great detail the identification or the function of all of the elements in FIG. 3. 
     Transistors TEO&#39; and TPO&#39; are connected in parallel between VCC and the collectors of the input switch transistors. Similarly transistors TP1&#39; and TE1&#39; are connected in parallel between the VCC and the collector of transistor TR&#39;. 
     As with the circuit in FIG. 1, the current generated from transistors TPO&#39; and TPI&#39;, denoted ICPO&#39;, must be less than current ICS&#39;. ICPO&#39; is determined by output reference voltage V T  &#39;, the V BE  of transistor TPB and resistor RB by the following equation: 
     (2). ICPO&#39; = [VCC&#39;-V BE  (of TPB)-VT&#39;]/RB. 
     Transistor TPB, which is connected as a diode in the forward direction between VCC&#39; and VT&#39;, thus provides a bias and constant current control for the transistors TPO&#39; and TPI&#39; as well as base drive for transistors TEI&#39; and TEO&#39;. 
     Operation of the Circuit in FIG. 3 
     With transistors T1&#39;, T2&#39; and T3&#39; off, TR&#39; is rendered conductive. Because ICS&#39; is greater than ICPO&#39;, transistor TEI&#39; conducts to supply the current difference, IENO&#39;. With TEI&#39; conducting, the in-phase output v out  &#39; is then one V BE  drop below vBX, typically -1.6 V. Simultaneously, the current ICPO&#39; from transistor TPO&#39; flows through schottky diode DO&#39; which causes the out-of-phase output v out  &#39; to rise one V f  of diode DO&#39; above the external VT&#39;, i.e., approximately -1.0 V up level. 
     When either T1&#39;, t2&#39; or T3&#39; or any combination thereof turn on, transistor TR turns off, resulting in the reverse output levels. v out  &#39; falls to -1.6 V and v out  &#39; rises to -1.0 V. 
     As with the circuit in FIG. 1, the AC performance is dependent upon the Beta of the PNP transistor and the ICS&#39; current level. For a Beta of 3, an ICS of 0.6 mA and an ICPO&#39; of 0.4 mA, an average delay of 600 picoseconds is obtainable with a power dissipation of less than 3.0mW. This equates to a speed-power product of 1.8 picojoules. 
     As previously mentioned, because resistor RB and transistor TPB are required only to set the level of current ICPO&#39;, they may also be used in other circuits. A block diagram configuration of such a circuit is shown in FIG. 4 where four current switch circuits are used in common with the same resistor RB and transistor TPB. 
     Reference potentials VCC&#39;, VEE&#39; and VT&#39; are supplied to each of the current switch circuits 10 via lines 16, 17 and 14 - 15, respectively. The same applies to VREF&#39;. 
     Typically, each of the reference potentials is generated external to the semiconductor chip containing the current switch circuits and serve all such circuits on the chip. 
     The specific embodiments shown in the drawing above are merely illustrative of several of the forms which the invention may take in practice. Numerous modifications will readily occur to those skilled in the art without departing from the scope of the invention as delineated in the appended claims which are to be construed as broadly as permitted by the prior art.