Abstract:
According to the present invention, there is provided a nonvolatile semiconductor memory capable of electrically writing and erasing information, comprising: a semiconductor substrate; source and drain regions formed at a predetermined spacing in a surface portion of said semiconductor substrate; a channel region positioned between said source and drain regions; a floating gate electrode formed on said cannel region via a first insulating film; a control gate electrode including a semiconductor layer formed on said floating gate electrode via a second insulating film, and a metal layer formed on said semiconductor layer; and an oxidation-resistant third insulating film formed on said control gate electrode, wherein the nonvolatile semiconductor memory further comprises an oxidation-resistant fourth insulating film so formed as to cover at least sidewalls of said metal layer, and said fourth insulating film is formed from the sidewalls of said metal layer to at least portions of sidewalls of said semiconductor layer of said control gate electrode.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application is based upon and claims benefit of priority under 35 USC § 119 from the Japanese Patent Application No. 2003-200343, filed on Jul. 23, 2003, the entire contents of which are incorporated herein by reference.  
       RELATED ART  
       [0002]     The present invention relates to a nonvolatile semiconductor memory and a method of fabricating the same.  
         [0003]     A nonvolatile semiconductor memory is developed in which electric charge injected from a channel region into a charge storage layer via a tunnel insulating film by a tunnel current is used as a digital bit information storage, and information is read out by measuring that conductance change of a MOSFET, which corresponds to the charge amount.  
         [0004]     This nonvolatile semiconductor memory uses a stacked structure of a metal and polysilicon. The metal is tungsten silicide (Wsi) having an Si/W composition ratio of 2.4 or more.  
         [0005]     The cell reliability worsens if this Wsi is changed to a material having a lower resistance, i.e., Wsi having an Si/W composition ratio of 2.4 or less or W, in order to shorten the gate delay and reduce the write time by lowering the resistance of the control gate electrode.  
         [0006]     In connection with this phenomenon, the problem of the conventional nonvolatile semiconductor memory will be explained below with reference to  FIG. 29 .  
         [0007]     First, a silicon oxide film, for example, is formed as a tunnel oxide film  21  on a P-type semiconductor substrate  10 , and a phosphorus-doped polysilicon film, for example, is formed as a floating gate electrode  22  on the tunnel oxide film  21 .  
         [0008]     An interpoly insulating film  23  is stacked on top of the structure, and a polysilicon film is formed as a control gate electrode  24  on the interpoly insulating film  23 . On this polysilicon film, a control gate resistance decreasing metal film  25  made of Wsi or W is formed.  
         [0009]     Assume that a metal made of Wsi having an Si/W composition ratio of 2.4 or less or W is used as the control gate resistance decreasing metal film  25  to further decrease the resistance.  
         [0010]     On the control gate resistance decreasing metal film  25 , a silicon nitride film, for example, is formed as a mask insulating film  26  which functions as an etching mask material during gate electrode formation.  
         [0011]     The stacked structure thus formed is patterned from the polysilicon film as the floating gate electrode  22  to the silicon nitride film as the mask insulating film  26  by lithography and anisotropic etching.  
         [0012]     Subsequently, damage recovery is performed by anisotropic etching, and, in order to prevent a leakage current from the polysilicon film as the floating gate electrode  22  via the gate sidewalls, the sidewalls of the floating gate electrode  22  are oxidized within the range of, e.g., 5 to 20 nm.  
         [0013]     If the control gate resistance decreasing metal film  25  is made of Wsi or W, the control gate resistance decreasing metal film  25  oxidizes more than the polysilicon film as the floating gate electrode  22  under the normal wet oxidation, dry oxidation, or ISSG oxidation conditions. As shown in  FIG. 29 , therefore, a silicon oxide film  43  formed on the sidewalls of the control gate resistance decreasing metal film  25  and containing the metal elements expands more than sidewall oxide films  41  and  42  formed on the side surfaces of the polysilicon film as the floating gate electrode  22  and on the side surfaces of the polysilicon film as the control gate electrode  24 .  
         [0014]     Especially when the control gate resistance decreasing metal film  25  is made of Wsi having an Si/W composition ratio of 2.4 or less, a conductive tungsten oxide  61  abnormally grows in the sidewall oxidation step.  
         [0015]     On the other hand, when the control gate resistance decreasing metal film  25  is made of W, the control gate resistance decreasing metal film  25  readily oxidizes in a heating step at 700° C. or higher, and a conductive tungsten oxide  61  abnormally grows.  
         [0016]     In either case, the spacing between the control gate resistance decreasing metal film  25  (WL 1 ) and control gate resistance decreasing metal film  25  (WL 2 ) of the adjacent control gates is narrowed by the conductive tungsten oxide film  61 . This produces a defective breakdown voltage between data selecting lines WL 1  and WL 2 .  
         [0017]     In addition, after gate sidewall oxidation, an N-type impurity such as phosphorus or arsenic is usually ion-implanted to form source/drain regions  28 . If the tungsten oxide film  61  is formed, however, shadowing occurs when ion implantation is performed, so the N-type impurity cannot be well supplied to the underlying semiconductor substrate  10  any longer.  
         [0018]     Accordingly, as shown in  FIG. 29 , a portion having no impurity diffusion layer  51  serving as a source or drain region is formed, and this makes the device unable to operate as a transistor.  
         [0019]     When an interlayer dielectric film such as a silicon oxide film or silicon nitride film is buried between the gate electrodes after that, the expanding tungsten oxide  61  worsens the burying properties, and an air gap called a seam forms. Also, shadowing is caused by the presence of the tungsten oxide  61 , and an air gap in which no interlayer dielectric film is formed forms on the sidewall of the floating gate.  
         [0020]     When an air gap forms very close to the charge storage layer as described above, the etching depth of the interlayer dielectric film largely changes from that when no such air gap is present. This extremely worsens the controllability of the etching depth when a contact is formed in this portion later.  
         [0021]     Furthermore, when memory cells are formed adjacent to each other in the direction perpendicular to the paper of  FIG. 29 , a conductor for forming a contact electrode enters along the air gap. This may cause a shortcircuit between the adjacent cells.  
         [0022]     Note that non-patent reference 1 (to be described later) is disclosed in connection with selective oxidation of polysilicon and W.  
         [0023]     This reference discloses a method by which polysilicon sidewalls oxidize more than W by selective oxidation at 800° C. to 850° C.  
         [0024]     In this method, however, low-temperature oxidation normally performed at 850° C. is used, so the viscosity of the oxide film is high. Consequently, as shown in  FIG. 29 , after the oxidation an end portion  200  of the floating gate electrode  22  positioned in the contact point between the sidewall oxide film  41  and tunnel oxide film  21  is sharply pointed.  
         [0025]     This shape becomes significant especially when the phosphorus concentration in the polysilicon of the floating gate electrode  22  is high, and so the oxidation rate is high.  
         [0026]     When this device is used as a nonvolatile semiconductor memory, therefore, field concentration occurs in the sharp-pointed portion  200  when data is erased by extracting electrons from the floating gate electrode  22 . This allows electrons to be discharged from the sharp-pointed portion more easily than from a flat portion into the semiconductor substrate  10  or impurity diffusion layer  51 .  
         [0027]     As a consequence, the flow of electrons concentrates to the sharp-pointed portion, so this portion rapidly deteriorates when write and erase are repeated by using the device as a flash memory. This degrades the reliability.  
         [0028]     Also, patent reference 1 (to be described later) discloses a technique related to the present invention.  
         [0029]     This reference discloses a technique which, in a nonvolatile semiconductor memory using tungsten as a control gate, prevents abnormal oxidation of tungsten by covering the control gate with a nitride film.  
         [0030]     Unfortunately, this technique has the following problem. As shown in  FIG. 9  of this reference, a nitride film  49   a  covers the sidewalls of a control gate polysilicon layer  39 , but does not cover any sidewalls of an ONO film  37  and floating gate polysilicon film  35  at all.  
         [0031]     This reference does not disclose the shape of a post-oxide film which is formed on the floating gate polysilicon film  35  by post-oxidation. However, when the post-oxidation step is performed, the sidewalls of the floating gate polysilicon layer  35  positioned below the ONO film  37  oxidize to form bird&#39;s beaks. Consequently, the sidewalls of the control gate polysilicon layer  39  positioned above the ONO film  37  do not oxidize at all.  
         [0032]     This makes etching damage recovery in the upper portion of the ONO film  37  unsatisfactory, and causes an insufficient breakdown voltage and unsatisfactory reliability.  
         [0033]     In a nonvolatile semiconductor memory, the increase in thickness of the ONO film  37  can be prevented by decreasing the post-oxidation amount and thereby decreasing the size of the bird&#39;s beaks formed at the upper and lower edges of the sidewalls of the ONO film  37 . Since this increases the coupling ratio defined by C ONO /(C ONO +C ox ), the data write characteristics (program characteristics) improve. C ONO  is the capacitance of the ONO film  37 , and C ox  is the capacitance of a tunnel oxide film  33   a.    
         [0034]     Unfortunately, bird&#39;s beaks form on the sidewalls of the floating gate polysilicon layer  35  positioned below the ONO film  37  disclosed in  FIG. 9  of this reference. Accordingly, the write characteristics are also unsatisfactory.  
         [0035]     That is, the reliability pertaining to the breakdown voltage and the program characteristics have a tradeoff relationship in accordance with whether to form bird&#39;s beaks at the upper and lower edges of the sidewalls of the ONO film  37 . The technique disclosed in this reference cannot satisfy either.  
         [0036]     Non-Patent Reference 1:  
         [0037]     S. choi, “High Manufacturable Sub-100 nm DRAM Integrated with Full Functionality”, IEDM2002  
         [0038]     Patent Reference 1:  
         [0039]     Japanese Patent Laid-Open No. 2003-31708  
         [0040]     As described above, when the control gate resistance decreasing metal film  25  is formed by using a metal made of Wsi having an Si/W composition ratio of 2.4 or less or by using W, a conductive tungsten oxide  61  abnormally grows in the gate sidewall oxidation step. This deteriorates the breakdown voltage between the control gates.  
         [0041]     Also, the floating gate electrode  22  positioned in the contact point between the sidewall oxide film  41  and tunnel oxide film is sharply pointed. This accelerates deterioration by field concentration, and lowers the reliability.  
         [0042]     Furthermore, the prior art which, in a device using tungsten as a control gate, prevents abnormal oxidation of tungsten by covering the control gate with a nitride film is proposed. However, this prior art has the problems of poor reliability and program characteristics.  
       SUMMARY OF THE INVENTION  
       [0043]     According to one aspect of the present invention, there is provide a nonvolatile semiconductor memory capable of electrically writing and erasing information, comprising: 
        a semiconductor substrate;     source and drain regions formed at a predetermined spacing in a surface portion of said semiconductor substrate;     a channel region positioned between said source and drain regions;     a floating gate electrode formed on said cannel region via a first insulating film;     a control gate electrode including a semiconductor layer formed on said floating gate electrode via a second insulating film, and a metal layer formed on said semiconductor layer; and     an oxidation-resistant third insulating film formed on said control gate electrode,     wherein the nonvolatile semiconductor memory further comprises an oxidation-resistant fourth insulating film so formed as to cover at least sidewalls of said metal layer, and     said fourth insulating film is formed from the sidewalls of said metal layer to at least portions of sidewalls of said semiconductor layer of said control gate electrode.        
 
         [0052]     According to one aspect of the present invention, there is provide a nonvolatile semiconductor memory, comprising: 
        a semiconductor substrate;     source and drain regions formed at a predetermined spacing in a surface portion of said semiconductor substrate;     a channel region positioned between said source and drain regions;     a floating gate electrode formed on said cannel region via a first insulating film;     a control gate electrode including a semiconductor layer formed on said floating gate electrode via a second insulating film, and a metal layer formed on said semiconductor layer;     an oxidation-resistant third insulating film formed on said control gate electrode; and     an oxidation-resistant fourth insulating film formed as to cover sidewalls of said metal layer, and to cover regions from sidewalls of said semiconductor layer of said control gate electrode to portions of sidewalls of said floating gate electrode.        
 
         [0060]     According to one aspect of the present invention, there is provide a nonvolatile semiconductor memory fabrication method, comprising: 
        forming, on a semiconductor substrate, a first insulating film, a conductive film serving as a floating gate electrode, a second insulating film, a semiconductor layer and metal layer serving as a control gate electrode, and a third insulating film in the order named;     patterning the third insulating film, the metal layer, and an upper portion of the semiconductor layer into a shape of a gate electrode;     forming a fourth insulating film on surfaces of the third insulating film, metal layer, and semiconductor layer;     etching the fourth insulating film such that the fourth insulating film remains on sidewalls of the third insulating film, metal layer, and semiconductor layer, and does not remain on an upper surface of the semiconductor layer;     etching and patterning the semiconductor layer, metal layer, second insulating film, and conductive film into a shape of an electrode by using the third insulating film as a mask, thereby forming the floating gate electrode and control gate electrode;     performing a post-oxidation process to form a sidewall oxide film on portions of sidewalls of the semiconductor layer, which are not covered with the fourth insulating film, and on sidewalls of the conductive film; and     ion-implanting an impurity in a surface portion of the semiconductor substrate by using the floating gate electrode and control gate electrode as masks, thereby forming source and drain regions.       
 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0068]      FIG. 1  is a longitudinal sectional view showing the sectional structure of a nonvolatile semiconductor memory according to the first embodiment of the present invention;  
         [0069]      FIG. 2  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the first embodiment;  
         [0070]      FIG. 3  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the first embodiment;  
         [0071]      FIG. 4  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the first embodiment;  
         [0072]      FIG. 5  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the first embodiment;  
         [0073]      FIG. 6  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the first embodiment;  
         [0074]      FIG. 7  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the first embodiment;  
         [0075]      FIG. 8  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the first embodiment;  
         [0076]      FIG. 9  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the second embodiment;  
         [0077]      FIG. 10  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the second embodiment;  
         [0078]      FIG. 11  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the second embodiment;  
         [0079]      FIG. 12  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the second embodiment;  
         [0080]      FIG. 13  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the second embodiment;  
         [0081]      FIG. 14  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the second embodiment;  
         [0082]      FIG. 15  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the second embodiment;  
         [0083]      FIG. 16  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the third embodiment;  
         [0084]      FIG. 17  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the third embodiment;  
         [0085]      FIG. 18  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the third embodiment;  
         [0086]      FIG. 19  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the third embodiment;  
         [0087]      FIG. 20  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the third embodiment;  
         [0088]      FIG. 21  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the third embodiment;  
         [0089]      FIG. 22  is a longitudinal sectional view showing the section in a certain step of the nonvolatile semiconductor memory according to the third embodiment;  
         [0090]      FIG. 23  is a circuit diagram showing the circuit configuration of the nonvolatile semiconductor memory according to the fourth, fifth or sixth embodiment;  
         [0091]      FIG. 24  is a planar view showing a planar arrangement of the nonvolatile semiconductor memory according to the fourth, fifth or sixth embodiment;  
         [0092]      FIG. 25  is a longitudinal sectional view showing the sectional structure taken along a line B-B in  FIG. 24  of a nonvolatile semiconductor memory according to the fourth embodiment;  
         [0093]      FIG. 26  is a longitudinal sectional view showing the sectional structure taken along a line A-A in  FIG. 24  of a nonvolatile semiconductor memory according to the fourth embodiment;  
         [0094]      FIG. 27  is a longitudinal sectional view showing the sectional structure taken along the line A-A in  FIG. 24  of a nonvolatile semiconductor memory according to the fifth embodiment;  
         [0095]      FIG. 28  is a longitudinal sectional view showing the sectional structure taken along the line A-A in  FIG. 24  of a nonvolatile semiconductor memory according to the sixth embodiment; and  
         [0096]      FIG. 29  is a longitudinal sectional view showing the section in a certain step of the conventional nonvolatile semiconductor memory. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0097]     Embodiments of the present invention will be described below with reference to the accompanying drawings.  
         [heading-0098]     (A) First Embodiment  
         [0099]      FIG. 1  shows the sectional structure of a nonvolatile semiconductor memory according to the first embodiment of the present invention.  
         [0100]     This embodiment has the features that all the sidewalls of a control gate resistance decreasing metal film  25  and portions of the sidewalls of a polysilicon film serving as a control electrode  24  are covered with a sidewall insulating film made of an oxidation-resistant film, e.g., a silicon nitride film or silicon oxide film.  
         [0101]     Referring to  FIG. 1 , on a P-type silicon semiconductor substrate  10  having a boron or indium impurity concentration of 10 14  to 10 19  cm −3 , 10- to 50-nm thick floating gate electrodes  22  made of polysilicon or the like are formed via a tunnel gate insulating film  21  made of, e.g., a 4- to 20-nm thick silicon oxide film, oxynitride film, or silicon nitride film.  
         [0102]     On the floating gate electrodes  22 , an ONO film (a multilayered film made up of a silicon oxide film, silicon nitride film, and silicon oxide film) serving as an interpoly insulating film  23  is stacked such that the thicknesses of the silicon oxide film, silicon nitride film, and silicon oxide film are, e.g., 2 to 10 nm, 5 to 15 nm, and 2 to 10 nm, respectively.  
         [0103]     The interpoly insulating film  23  can be, e.g., an Al 2 O 3  film or a single-layered silicon oxide film, and the thickness of the film is 5 to 30 nm.  
         [0104]     On the interpoly insulating film  23 , polysilicon serving as control gate electrodes  24  (a select gate electrode  24  (SG) for a select transistor, and a data selecting line  24  (WL 1 ) and data selecting line  24  (WL 2 ) for semiconductor memory transistors) are formed to have a thickness of 10 to 500 nm.  
         [0105]     On this polysilicon, a 10- to 500-nm thick Wsi or W layer is formed as a control gate resistance decreasing metal film  25 .  
         [0106]     When Wsi is to be used, a metal made of Wsi having an Si/W composition ratio of 2.4 or less is preferred to a metal made of conventionally used Wsi having an Si/W composition ratio of 2.4 or more, because the resistance can be decreased.  
         [0107]     More specifically, when the Si/W composition ratio is 2 to 2.15, the resistance can be decreased to be smaller than 70% of the resistance of Wsi having an Si/W composition ratio of 2.4 or more. Accordingly, the resistance can be maintained at a predetermined value or less even when the design rule is reduced by one generation (70 to 80%), i.e., even when the control line width is reduced by one generation while the length of a data control line is held.  
         [0108]     Since, therefore, the cell array scale can be increased while the length in the data control line direction is held constant, this is particularly desirable in designing a NAND nonvolatile semiconductor memory having limitations on the package size in the data control line direction.  
         [0109]     On the control gate resistance decreasing metal film  25 , a 10- to 500-nm thick mask insulating film  26 , such as a silicon nitride film or silicon oxynitride film (SiON), which serves as an etching mask material for gate electrode formation is stacked. The control gate resistance decreasing metal film  25  may also be a stacked insulating film of, e.g., a silicon oxide film and silicon nitride film.  
         [0110]     The mask insulating film  26  must be oxidation-resistant in order to prevent an oxidizer from oxidizing the control gate resistance decreasing metal film  25  from the upper surface during sidewall oxidation.  
         [0111]     In addition, on the side surfaces of the control gate resistance decreasing metal film  25  and the two sides of the upper portions of the side surfaces of the polysilicon film serving as the control gate electrodes  24 , a sidewall insulating film  31  made of, e.g., a 2- to 20-nm thick silicon nitride film or silicon oxynitride film is formed.  
         [0112]     The sidewall insulating film  31  must be oxidation-resistant in order to prevent an oxidizer from oxidizing the control gate resistance decreasing metal film  25  from the upper surface during sidewall oxidation.  
         [0113]     In particular, the sidewall insulating film  31  must be formed before a gate post-oxidation step. To prevent an oxidizer for gate post-oxidation from entering between the sidewall insulating film  31  and control gate resistance decreasing metal film  25 , the sidewall insulating film  31  is desirably formed in direct contact with the control gate resistance decreasing metal film  25 .  
         [0114]     Furthermore, on the sidewalls of the lower portions of the control gate electrodes  24 , a sidewall oxide film  42  made of, e.g., a 3- to 20-nm thick silicon oxide film is formed.  
         [0115]     Also, on the sidewalls of the floating gate electrodes  22 , a sidewall oxide film  41  made of, e.g., a 3- to 20-nm thick silicon oxide film is formed.  
         [0116]     The sidewall oxide film  41  is formed by oxidation of the floating gate electrodes  22 , and may also be a silicon oxynitride film (SiON) having an oxygen composition larger than that of the sidewall insulating film  31 . Note that the sidewall oxide film  42  is separated from the control gate resistance decreasing metal film  25 .  
         [0117]     An N-type impurity is ion-implanted into the surface portion of the semiconductor substrate  10  by using the gate electrodes as masks, thereby forming N-type impurity diffusion layers  51  serving as source and drain regions. A channel region is positioned between the two N-type impurity diffusion layers  51 .  
         [0118]     The N-type impurity diffusion layers  51 , floating gate electrodes  22 , and control gate electrodes  24  form floating gate type nonvolatile EEPROM cells. The gate length of the floating gate electrode  22  is 0.01 to 0.5 μm.  
         [0119]     The N-type impurity diffusion layers  51  as source and drain regions are formed at a depth of 10 to 500 nm from the surface of the semiconductor substrate  10 , so that the surface concentration of phosphorus, arsenic, or antimony is 10 17  to 10 21  cm −3 .  
         [0120]     The N-type impurity diffusion layers  51  are shared by adjacent semiconductor memories to realize, e.g., a NAND connection or NOR connection.  
         [0121]     Furthermore, an interlayer dielectric film  71  made of, e.g., a silicon oxide film, silicon nitride film, or silicon oxynitride film is buried between the floating gate electrodes  22 .  
         [0122]     A channel region is formed between the N-type impurity diffusion layers  51  as source and drain regions. In this channel region, the number of conduction carriers can be changed via the gate insulating film  21 .  
         [0123]     The fabrication steps of this embodiment will be explained below with reference to FIGS.  2  to  8 .  
         [0124]     On a P-type silicon semiconductor substrate  10  having a boron or indium impurity concentration of 10 14  to 10 19  cm −3 , a tunnel gate insulating film  21  made of, e.g., a 4- to 20-nm thick silicon oxide film, oxynitride film, or nitride film is formed.  
         [0125]     Then, a 10- to 500-nm thick floating gate electrode  22  made of, e.g., polysilicon is formed by LPCVD.  
         [0126]     On the floating gate electrode  22 , an ONO film (a multilayered film made up of a silicon oxide film, silicon nitride film, and silicon oxide film) serving as an interpoly insulating film  23  is stacked such that the thicknesses of the silicon oxide film, silicon nitride film, and silicon oxide film are, e.g., 2 to 10 nm, 5 to 15 nm, and 2 to 10 nm, respectively. For example, the interpoly insulating film  23  can be an Al 2 O 3  film or a single-layered silicon oxide film.  
         [0127]     On the interpoly insulating film  23 , polysilicon serving as control gate electrodes  24  (a select gate electrode  24  (SG), data selecting line  24  (WL 1 ), and data selecting line  24  (WL 2 )) are formed to have a thickness of 10 to 500 nm.  
         [0128]     On this polysilicon, a 10- to 500-nm thick Wsi or W layer is stacked as a control gate resistance decreasing metal film  25 .  
         [0129]     On these electrodes, a 50- to 800-nm thick mask insulating film  26 , such as a silicon nitride film or silicon oxynitride film, which functions as an etching mask material for gate formation is stacked. As described above, the mask insulating film  26  may also be a stacked insulating film of, e.g., a silicon oxide film and silicon nitride film. In this manner, a stacked structure shown in  FIG. 2  is obtained.  
         [0130]     Subsequently, as shown in  FIG. 3 , a resist film patterned by lithography is used as a mask to partially etch away the mask insulating film  26 , the control gate resistance decreasing metal film  25 , and the control gate electrode  24  made of a polysilicon film or the like, by using an etching technique such as reactive ion etching (to be referred to as RIE hereinafter).  
         [0131]     Letting tox2 be the thickness of the sidewall oxide film  42  shown in  FIG. 1 , the etching depth of the control gate electrode  24  is desirably 4×tox2 or more, in order to prevent bird&#39;s beaks of the sidewall oxide film  42  from reaching the control gate resistance decreasing metal film  25 .  
         [0132]     As shown in  FIG. 4 , a sidewall insulating film  31  made of a 2- to 20-nm thick silicon nitride film or silicon oxynitride film is deposited on the entire surface.  
         [0133]     When a silicon nitride film is to be formed, this film is preferably formed in a heating step at 800° C. or less because the temperature is lower than that of a heating step of forming a gate sidewall oxide film later. This silicon nitride film can be any of dichlorosilane-based, tetrachlorosilane-based, and hexachlorodisilane-based silicon nitride films.  
         [0134]     Anisotropic etching is then performed such that the sidewall insulating film  31  remains on sheer gate sidewalls and does not remain on the polysilicon upper surfaces of the control gate electrodes  24 , thereby obtaining a shape shown in  FIG. 5 .  
         [0135]     Furthermore, the mask insulating film  26  is used as an etching mask to anisotropically etch the control gate electrodes  24 , interpoly insulating film  23 , and floating gate electrode  22 , thereby obtaining a shape shown in  FIG. 6 .  
         [0136]     After that, to recover etching damage to the tunnel oxide film  21 , a post-oxidation process is performed by annealing in an oxidizing ambient.  
         [0137]     As shown in  FIG. 7 , when a gate sidewall post-oxidation process is performed, thin sidewall oxide films  41  and  42  are formed on the side walls of the floating gate electrodes  22  and control gate electrodes  24 .  
         [0138]     In this oxidation, it is unnecessary to use the W selective oxidation conditions by which the viscosity of the oxide films rises in the conventional device as described previously. That is, it is possible to select oxidation conditions, such as ISSG oxidation or high-temperature oxidation at 1,000° C. or higher, by which the floating gate electrode  22  is not sharply pointed at the contact point between the sidewall oxide film  41  and tunnel oxide film  21  while the viscosity of the oxide films is kept low.  
         [0139]     After that, as shown in  FIG. 8 , N-type impurity diffusion layers  51  serving as source and drain regions are formed by ion implantation or the like of, e.g., phosphorus, arsenic, or antimony, so that the surface concentration is 10 17  to 10 21  cm −3 .  
         [0140]     Since the metal of the control gate electrodes  24  does not abnormally oxidize, the breakdown voltage between the control gates does not decrease. Also, the impurity diffusion layers  51  can be evenly formed without any influence of shadowing.  
         [0141]     Finally, a 50- to 400-nm thick silicon oxide film made of, e.g., TEOS, HTO, BSG, PSG, BPSG, or HDP is deposited as an interlayer dielectric film  71  on the entire surface and buried by anisotropic etching until portions between cells are filled, thereby obtaining the sectional structure shown in  FIG. 1 .  
         [0142]     The following functions and effects are obtained by this embodiment.  
         [0143]     (1) In the gate sidewall oxidation step, the oxidizer does not reach the control gate resistance decreasing metal film  25 . Accordingly, no oxide film thicker than the control gate electrode  24  positioned below the control gate resistance decreasing metal film  25 , such as the oxide  61  formed on the sidewalls of the control gate resistance decreasing metal film  25  shown in  FIG. 29 , is formed. Consequently, the normal shape and dimensions as a gate electrode can be maintained.  
         [0144]     This reduces the possibility that the metal contained in the control gate resistance decreasing metal film  25  diffuses in an oxidation furnace and causes metal contamination in the gate sidewall oxidation step. Accordingly, the junction leak characteristics on the same wafer can be improved more than the conventional methods.  
         [0145]     Also, no seam is formed in the interlayer dielectric film unlike in the conventional devices, so good burying characteristics can be obtained. Therefore, the controllability of the etching depth can be improved when contacts are formed later in the dielectric film  71  shown in  FIG. 1 .  
         [0146]     Furthermore, when a plurality of semiconductor memories are to be formed adjacent to each other in the direction perpendicular to the paper of  FIG. 1 , no conductor for contact electrode formation enters between the adjacent semiconductor memories, so the insulation properties between these memories can be well maintained.  
         [0147]     In particular, those side surfaces of the sidewall oxide film  41 , which are not in contact with the floating gate electrode  22  extend more than those side surfaces of the sidewall insulating film  31 , which are not in contact with the side surfaces of the control gate resistance decreasing metal film  25 . Consequently, as shown in  FIG. 1 , a forward tapered shape is formed when the interlayer dielectric film  71  is buried, unlike in the conventional devices. Since this eliminates seams formed in the conventional devices, the reliability can be further improved.  
         [0148]     (2) In the gate sidewall oxidation step, both the control gate electrode  24  in contact with the upper portions of the sidewalls of the interpoly insulating film  23  and the floating gate electrode  22  in contact with the lower portions of the sidewalls of the interpoly insulating film  23  oxidize to form bird&#39;s beaks at the upper and lower edges of the sidewalls of the interpoly insulating film  23 , thereby increasing the film thickness.  
         [0149]     Accordingly, even if defects are formed in the interpoly insulating film  23  in the etching step for gate electrode formation, the electric field can be reduced by the increase in film thickness. As a consequence, a semiconductor memory having higher reliability can be realized.  
         [0150]     In particular, those lower portions of the sidewalls of the floating gate electrode  22 , which are in contact with the interpoly insulating film  23  oxidize to form bird&#39;s beaks on the interpoly insulating film  23 , and the thickness of the edges of these portions increase. Therefore, unlike in the technique disclosed in patent reference 1 mentioned earlier, damage is recovered even if defects are formed in the interpoly insulating film  23  in the etching step of patterning the gate electrode shape. In addition, field concentration is reduced by increasing the thickness of the interpoly insulating film  23 , so the reliability can be improved.  
         [0151]     (3) Unlike in the conventional devices, the control gate resistance decreasing metal film  25  does not abnormally oxidize, and the thickness of the sidewall oxide film  41  can be increased. This makes it possible to prevent electrons from being discharged from the floating gate electrode  22  through the sidewall oxide film  41 .  
         [0152]     Consequently, the holding characteristics of electrons stored in the floating gate electrode  22  can be improved.  
         [0153]     (4) As described above, the phenomenon in which the floating gate electrode  22  is sharply pointed after the oxidation step can be prevented. This prevents field concentration to a sharp-pointed portion during erase in which electrons are extracted from the floating gate electrode  22 . Accordingly, electrons can be discharged more evenly from the floating gate electrode  22  to the semiconductor substrate  10  or impurity diffusion layers  51 .  
         [0154]     As a consequence, electrons are more evenly discharged to the edges and channel region of the floating gate electrode  22 . Therefore, no deterioration occurs even when write and erase are repeated by using the device as a flash semiconductor memory, so the reliability can be improved.  
         [0155]     (5) The conventional gate sidewall post-oxidation step has the problem that the oxidizer comes in direct contact with the control gate resistance decreasing metal film  25 , and the control gate resistance decreasing metal film  25  abnormally oxidizes. In this embodiment, however, the side surfaces of the control gate resistance decreasing metal film  25  are covered with the oxidation-resistant sidewall insulating film  31 , and the upper surface of the control gate resistance decreasing metal film  25  is covered with the mask insulating film  26 . Therefore, the problem of abnormal oxidation can be avoided because there is no contact with the oxidizer.  
         [0156]     Also, the gate length of the floating gate electrode  22  and tunnel insulating film  21  increases by an amount twice the thickness of the sidewall insulating film  31 . This suppresses the short channel effect.  
         [0157]     (6) In this embodiment, the lower portion of the control gate electrode  24 , and the interpoly insulating film  23  and floating gate electrode  22  are simultaneously processed. This decreases the dimensional differences in the gate length direction.  
         [0158]     Accordingly, the ratio of the capacitance of the interpoly insulating film  23  to the capacitance of the tunnel insulating film  21  can be held high.  
         [0159]     (7) It is possible to select oxidation conditions by which the shape of the floating gate electrode  22  at the contact point between the sidewall oxide film  41  and tunnel oxide film  21  is not sharply pointed.  
         [0160]     Also, since the thickness of the sidewall oxide film  41  can be made larger than in the conventional devices without any abnormal oxidation, no electrons are easily discharged from the floating gate electrode  22  through the sidewall oxide film  41 . As a consequence, the holding characteristics of electrons stored in the floating gate electrode  22  can be improved.  
         [0161]     Furthermore, the floating gate electrode  22  can be prevented from being sharply pointed. Therefore, during erase in which electrons are extracted from the floating gate electrode  22 , field concentration to a sharp-pointed portion can be prevented. This makes it possible to more evenly discharge electrons from the floating gate electrode  22  to the semiconductor substrate  10  or impurity diffusion layers  51 .  
         [0162]     Consequently, electrons are more evenly discharged to the edges and channel region of the floating gate electrode  22 . Accordingly, no deterioration occurs even when write and erase are repeated by using the device as a flash semiconductor memory, so the reliability can be improved.  
         [heading-0163]     (B) Second Embodiment  
         [0164]      FIG. 9  shows the structure of a nonvolatile semiconductor memory according to the second embodiment of the present invention.  
         [0165]     This embodiment differs from the first embodiment in that a sidewall insulating film  31  is so formed as to reach an interpoly insulating film  23 . The same reference numerals as in the first embodiment denote the same parts, and an explanation thereof will be omitted.  
         [0166]     FIGS.  10  to  15  illustrate device sections in different fabrication steps of this embodiment.  
         [0167]     First, in the same manner as in the first embodiment, a tunnel gate insulating film  21 , floating gate electrode  22 , interpoly insulating film  23 , control gate electrode  24  (a selecting gate electrode  24  (SG), data selecting line  24  (WL 1 ), and data selecting line  24  (WL 2 )), control gate resistance decreasing metal film  25 , and mask insulating film  26  are stacked on a P-type semiconductor substrate  10 , thereby obtaining the structure shown in  FIG. 2 .  
         [0168]     Subsequently, as shown in  FIG. 10 , a resist patterned by lithography is used as a mask to pattern the mask insulating film  26 , control gate resistance decreasing metal film  25 , and control gate electrode  24  until the interpoly insulating film  23  is reached, by using an etching technique such as RIE.  
         [0169]     As shown in  FIG. 11 , a sidewall insulating film  31  made of a 2- to 20-nm thick silicon nitride film or silicon oxynitride film is deposited on the entire surface.  
         [0170]     Note that the silicon nitride film to be deposited is desirably formed in a heating step at 800° C. or less because the temperature is lower than that of a maximum heating step of forming a gate sidewall oxide film later. This silicon nitride film can be a dichlorosilane-based silicon nitride film, or a tetrachlorosilane-based or hexachlorodisilane-based silicon nitride film.  
         [0171]     Anisotropic etching is then performed such that the sidewall insulating film  31  remains on sheer gate sidewalls and does not remain on the upper surface of the floating gate electrode  22 , thereby obtaining a shape shown in  FIG. 12 .  
         [0172]     In this step, the interpoly insulating film  23  and sidewall insulating film  31  can be patterned with high controllability, as shown in  FIG. 12 , by using insulating film etching conditions having a selective ratio to polysilicon.  
         [0173]     Furthermore, the mask insulating film  26  and sidewall insulating film  31  are used as etching masks to pattern the floating gate electrode  22  by anisotropic etching, thereby obtaining a shape shown in  FIG. 13 .  
         [0174]     After that, to recover etching damage to the tunnel oxide film  21 , a post-oxidation process is performed by annealing in an oxidizing ambient.  
         [0175]     Also, as shown in  FIG. 14 , on the side walls of the floating gate electrodes  22  having undergone the gate sidewall post-oxidation process, the oxidizer and polysilicon react with each other to form a thin sidewall oxide film  41 .  
         [0176]     In this oxidation, as in the first embodiment described above, it is possible to select oxidation conditions, such as ISSG oxidation or high-temperature oxidation at 1,000° C. or higher, by which the floating gate electrode  22  is not sharply pointed at the contact point between the sidewall oxide film  41  and tunnel oxide film  21  while the viscosity of the oxide films is kept low.  
         [0177]     The sidewall oxide film  41  may also be a silicon oxynitride film formed by oxidation of the floating gate electrode  22  and having an oxygen composition larger than that of the sidewall insulating film  31 .  
         [0178]     After that, N-type impurity diffusion layers  51  serving as source and drain regions are formed by ion implantation of, e.g., phosphorus, arsenic, or antimony, so that the surface concentration is 10 17  to 10 21  cm  −3 , thereby obtaining a structure shown in  FIG. 15 .  
         [0179]     Since the control gate resistance decreasing metal film  25  does not abnormally oxidize, the breakdown voltage between the control gates does not decrease, and the impurity diffusion layers  51  can be evenly formed without any influence of shadowing.  
         [0180]     Finally, a 50- to 400-nm thick silicon oxide film made of, e.g., TEOS, HTO, BSG, PSG, BPSG, or HDP is deposited on the entire surface and anisotropically etched until portions between cells are filled, thereby obtaining the sectional structure shown in  FIG. 9 .  
         [0181]     This embodiment has the following characteristic features in addition to characteristic features (1), (3) to (5), and (7) described in the first embodiment.  
         [0182]     (8) In the etching step shown in  FIG. 10 , the polysilicon etching conditions having a selective ratio to the interpoly insulating film  23  are used. So, etching can be controlled to stop at the interpoly insulating film  23 .  
         [0183]     Accordingly, in the etching step shown in  FIG. 13  performed after that, the etching amount can be controlled independently of variations in film thickness of the control gate electrodes  24 . This prevents an over etching phenomenon.  
         [0184]     This makes it possible to make the depth of the impurity diffusion layers  51  more constant, and realize a more uniform semiconductor memory.  
         [0185]     (9) Sine the thickness of the sidewalls of the control gate electrodes  24  does not increase by oxidation, it is possible to obtain a shape by which the burying properties of the interlayer dielectric film  71  are superior even in the interpoly insulating film  23 .  
         [0186]     This embodiment also has the following characteristic feature compared to (2) described in the first embodiment.  
         [0187]     (2′) In the gate sidewall oxidation step, the floating gate electrode  22  in contact with the sidewalls of the interpoly insulating film  23  oxidizes to form bird&#39;s beaks on the lower side (near the floating gate electrode  22 ) of the sidewalls of the interpoly insulating film  23 , thereby increasing the film thickness.  
         [0188]     Accordingly, although the structure is different from the first embodiment in which bird&#39;s beaks are formed at both the upper and lower edges of the interpoly insulating film  23 , the electric field can be reduced by the increase in film thickness on the lower side. As a consequence, a semiconductor memory having higher reliability can be realized.  
         [0189]     Furthermore, although the thickness of the interpoly insulating film  23  is smaller than that in the first embodiment, the smaller this film thickness, the better the write characteristics. In this embodiment, therefore, it is possible to improve the reliability and ensure the write characteristics at the same time by increasing the film thickness of only the lower portions of the sidewalls of the interpoly insulating film  23 .  
         [heading-0190]     (C) Third Embodiment  
         [0191]     A nonvolatile semiconductor memory according to the third embodiment of the present invention will be described below.  
         [0192]     As shown in  FIG. 16 , the structure of this embodiment differs from the first and second embodiments in that a sidewall insulating film  31  is so formed as to reach middle portions of floating gate electrodes  22 . The same reference numerals as in the first and second embodiments denote the same parts, and an explanation thereof will be omitted.  
         [0193]     A method of fabricating the nonvolatile semiconductor memory according to this embodiment will be described below with reference to FIGS.  17  to  22 .  
         [0194]     First, in the same manner as in the first and second embodiments, a tunnel gate insulating film  21 , floating gate electrode  22 , interpoly insulating film  23 , control gate electrode  24  (a selecting gate electrode  24  (SG), data selecting line  24  (WL 1 ), and data selecting line  24  (WL 2 )), control gate resistance decreasing metal film  25 , and mask insulating film  26  are stacked on a P-type semiconductor substrate  10 , thereby obtaining the structure shown in  FIG. 2 .  
         [0195]     As shown in  FIG. 17 , a resist patterned by lithography is used as a mask to partially etch away the mask insulating film  26 , control gate resistance decreasing metal film  25 , control gate electrode  24 , the interpoly insulating film  23 , and floating gate electrode  22  by using an etching technique such as RIE.  
         [0196]     The etching depth of the floating gate electrode  22  can be set with high controllability by stopping the etching on an element isolation film (not shown) having a surface within the range of the film thickness of the floating gate electrode  22 , or on the upper surface of a gate oxide film (not shown) of a peripheral transistor whose film thickness is increased so as to be able to apply a high voltage.  
         [0197]     As shown in  FIG. 18 , a sidewall insulating film  31  made of a 2- to 20-nm thick silicon nitride film or silicon oxynitride film is deposited on the entire surface.  
         [0198]     As in the first and second embodiments, the silicon nitride film to be deposited is desirably formed in a heating step at 800° C. or less. This silicon nitride film can be a dichlorosilane-based silicon nitride film, or a tetrachlorosilane-based or hexachlorodisilane-based silicon nitride film.  
         [0199]     Anisotropic etching is then performed such that the sidewall insulating film  31  remains on sheer gate sidewalls and does not remain on the polysilicon upper surface of the floating gate electrode  22 , thereby obtaining a shape shown in  FIG. 19 .  
         [0200]     Furthermore, the mask insulating film  26  is used as an etching mask to process the floating gate electrode  22  by anisotropic etching, thereby obtaining a shape shown in  FIG. 20 . To recover etching damage to the tunnel oxide film  21 , a post-oxidation process is performed by annealing in an oxidizing ambient.  
         [0201]     Also, as shown in  FIG. 21 , a post-oxidation process is performed to allow the oxidizer and polysilicon to react with each other, thereby forming a thin sidewall oxide film  41  made of a silicon oxide film on the side walls of the floating gate electrodes  22 .  
         [0202]     In this oxidation, as in the first and second embodiments described above, it is possible to select oxidation conditions, such as ISSG oxidation or high-temperature oxidation at 1,000° C. or higher, by which the floating gate electrode  22  is not sharply pointed at the contact point between the sidewall oxide film  41  and tunnel oxide film  21  while the viscosity of the oxide films is kept low.  
         [0203]     The sidewall oxide film  41  may also be a silicon oxynitride film formed by oxidation of the floating gate electrodes  22  and having an oxygen composition larger than that of the sidewall insulating film  31 .  
         [0204]     After that, N-type impurity diffusion layers  51  serving as source and drain regions are formed by ion-implanting an impurity such as phosphorus, arsenic, or antimony so that the surface concentration is 10 17  to 10 21  cm −3 , thereby obtaining a structure shown in  FIG. 22 .  
         [0205]     Since the metal of the control gate electrodes  24  does not abnormally oxidize, the breakdown voltage between the control gates does not decrease, and the impurity diffusion layers  51  can be evenly formed without any influence of shadowing.  
         [0206]     Finally, a 50- to 400-nm thick silicon oxide film made of, e.g., TEOS, HTO, BSG, PSG, BPSG, or HDP is deposited on the entire surface and anisotropically etched until portions between cells are filled, thereby obtaining the sectional structure shown in  FIG. 16 .  
         [0207]     This embodiment has the following characteristic features in addition to characteristic features (1), (3) to (5), and (7) described in the first embodiment, and characteristic feature (9) described in the second embodiment.  
         [0208]     (10) The sidewalls of the interpoly insulating film  23  are covered with the sidewall insulating film  31 , and hence can prevent permeation of hydronium ion or hydrogen because these sidewalls are not exposed to the gate post-oxidation ambient. Therefore, unlike in the technique disclosed in patent reference 1, an increase in leakage current can be prevented even when, e.g., an Si film is contained in the interpoly insulating film  23 . Also, even when a high-dielectric film such as an Al 2 O 3  film is used, a good insulating film can be formed without increasing the leakage current.  
         [0209]     This embodiment also has the following characteristic feature compared to (2) described in the first embodiment and (2′) in the second embodiment.  
         [0210]     In the gate sidewall oxidation step, those portions of the control gate electrodes  24  and floating gate electrodes  22 , which are in contact with the sidewalls of the interpoly insulating film  23  do not oxidize because they are covered with the sidewall insulating film  31 .  
         [0211]     Accordingly, no bird&#39;s beaks are formed at the upper and lower edges of the sidewalls of the interpoly insulating film  23 , so the film thickness does not increase. Unlike in the first and second embodiments, therefore, field concentration cannot be reduced because the thickness of the interpoly insulating film  23  does not increase.  
         [0212]     Since, however, the thickness of the interpoly insulating film  23  does not increase, this embodiment is superior in write characteristics.  
         [0213]     (11) The sidewalls of the interpoly insulating film  23  are not exposed to the oxidizing ambient in the gate electrode post-oxidation step, so no bird&#39;s beaks are formed on the sidewalls of the interpoly insulating film  23 . Accordingly, the capacitance ratio represented by C2/(C1+C2) increases, and the program characteristics improve. C1 indicates the capacitance of the tunnel oxide film  21 , and C2 indicates the capacitance of the interpoly insulating film  23 .  
         [heading-0214]     (D) Fourth Embodiment  
         [0215]      FIG. 23  shows the circuit configuration of a nonvolatile semiconductor memory according to the fourth embodiment of the present invention. In this embodiment, the semiconductor memory structure according to the first embodiment is applied to a NAND cell array.  
         [0216]     The same reference numerals as in the first embodiment denote the same parts, and an explanation thereof will be omitted.  
         [0217]      FIG. 23  shows an equivalent circuit of a NAND cell block NA 101 .  FIG. 24  shows the planar arrangement of elements.  FIG. 24  shows a structure in which three NAND cell blocks NA 101  shown in  FIG. 23  are juxtaposed. To clearly show the cell structure in particular, a planar arrangement below control gat electrodes  24  is shown in  FIG. 24 .  
         [0218]     In the NAND cell block NA 101 , nonvolatile semiconductor memories M 0  to M 15  each of which is a MOS transistor having a floating gate electrode  22  are connected in series. One end of the series circuit is connected to a data transfer line BL via a select transistor S 1 . The other end of the series circuit is connected to a common source line SL via a select transistor S 2 .  
         [0219]     The transistors M 0  to M 15 , S 1 , and S 2  are formed on a P-type semiconductor substrate  10  (P-type well).  
         [0220]     The control electrodes of the semiconductor memories M 0  to M 15  are connected to data selecting lines WL 0  to WL 15 , respectively.  
         [0221]     Also, to select one of the plurality of NAND semiconductor memory blocks NA 101  arranged along the data transfer line BL and to connect the selected semiconductor memory block to the data transfer line BL, the control electrode of the select transistor S 1  is connected to a block selecting line SSL. The control electrode of the select transistor S 2  is connected to a block selecting line GSL.  
         [0222]     In this embodiment, the block selecting lines SSL and GSL are connected between other cells (not shown) adjacent in the horizontal direction of the paper by the same conductor layer as the floating gate electrodes  22  of the data selecting lines WL 0  to WL 15  of the semiconductor memories M 0  to M 15 .  
         [0223]     The semiconductor memory block NA 101  need only have at least one block selecting line SSL and at least one block selecting line GSL. The block selecting lines SSL and GSL are desirably formed in the same direction as the data selecting lines WL 0  to WL 15  in order to increase the density.  
         [0224]     In this embodiment, 16=2 4  semiconductor memories are connected to the semiconductor memory block NA 101 . However, the number of semiconductor memories connected to the data transfer line BL and data selecting lines WL 0  to WL 15  need only be a plural number. This number is desirably 2 n  (n is a positive integer) in order to perform address decoding.  
         [0225]      FIG. 25  shows a longitudinal sectional structure taken along a line B-B in  FIG. 24 .  FIG. 26  shows a longitudinal sectional structure taken along a line A-A in  FIG. 24 .  FIG. 25  shows the longitudinal sectional structure of the semiconductor memory.  
         [0226]     Referring to  FIGS. 24, 25 , and  26 , on a P-type semiconductor substrate  13  having, e.g., a boron impurity concentration of 10 14  to 10 19  cm −3 , 10- to 500-nm thick floating gate electrodes  22 ,  22  (SSL), and  22  (GSL) made of polysilicon doped with 10 18  to 10 21  cm −3  of, e.g., phosphorus or arsenic are formed via tunnel gate insulating films  21 ,  21  (SSL), and  21  (GSL) made of, e.g., a 4- to 20-nm thick silicon oxide film or oxynitride film.  
         [0227]     The floating gate electrodes  22  are formed in self-alignment with the P-type semiconductor region  13  on a region where an element isolation insulating film  110  made of, e.g., a silicon oxide film is not formed.  
         [0228]     For example, the element isolation insulating film  110  can be formed by depositing the tunnel gate insulating film  21  and floating gate electrode  22  on the entire surface of the semiconductor region  13 , and patterning them until they reach the semiconductor region  13 , e.g., to a depth of 0.05 to 0.5 μm by etching, thereby burying the insulating film.  
         [0229]     Since the tunnel gate insulating film  21  and floating gate electrode  22  can be formed on the entire plane surface having no steps as described above, the uniformity further improves, and film formation can be performed with good characteristics.  
         [0230]     On top of the resulting structure, 10- to 500-nm thick control gate electrodes  24  made of polysilicon doped with 10 17  to 10 21  cm −3  of an impurity such as phosphorous, arsenic, or boron, a stacked structure of Wsi and polysilicon, or a stacked structure of W and polysilicon are formed via an interpoly insulating film  23  made of a 5- to 35-nm thick silicon oxide film, oxynitride film, or silicon oxide film/silicon nitride film/silicon oxide film.  
         [0231]     As shown in  FIG. 24 , the control gate electrodes  24  are formed to the block boundaries in the horizontal direction of the paper so as to be interconnected between the adjacent semiconductor memory blocks, thereby forming the data selecting lines WL 0  to WL 15 .  
         [0232]     Note that it is desirable to apply a voltage to the P-type semiconductor region  13  by an N-type semiconductor region  12  independently of a P-type semiconductor substrate  11 , in order to reduce the boosting circuit load during erase and suppress the power consumption.  
         [0233]     In the gate shape of this embodiment, the sidewalls of the P-type semiconductor region  13  are covered with the element isolation insulating film  110 . Therefore, these sidewalls are not exposed by etching before the floating gate electrodes  22  are formed. This prevents the floating gate electrodes  22  from being positioned below the semiconductor region  13 .  
         [0234]     Accordingly, in the boundary between the semiconductor region  13  and element isolation insulating film  110 , it is possible to prevent the concentration of a gate electric field or the formation of a parasitic transistor having a decreased threshold value.  
         [0235]     Furthermore, a phenomenon in which a write threshold value is decreased by field concentration, i.e., a so-called sidewalk phenomenon hardly occurs, so transistors having higher reliability can be formed.  
         [0236]     Also, as in the first embodiment, as shown in  FIG. 26 , the side walls of a mask insulating film  26  and control gate resistance decreasing metal film  25  and the side walls of the upper portion of the control gate electrode  24  are covered with a sidewall insulating film  31  made of, e.g., a 2- to 20-nm thick silicon nitride film or silicon oxynitride film.  
         [0237]     Additionally, a sidewall insulating film  42  made of a silicon oxide film is formed on the sidewalls of the lower portion of the control gate electrode  24 , a sidewall insulating film  41  made of a silicon oxide film is formed on the sidewalls of the floating gate electrode  22 , and N-type impurity diffusion layers  51  serving as source and drain regions are formed.  
         [0238]     The impurity diffusion layers  51 , floating gate electrode  22 , and control gate electrode  24  form a floating gate type EEPROM cell in which a charge amount stored in the floating gate electrode  22  is used as an information amount. The gate length is 0.01 to 0.5 μm.  
         [0239]     Note that this semiconductor memory structure is the same as the first embodiment describe earlier, so an explanation thereof will be omitted.  
         [0240]     The N-type impurity diffusion layers  51  are formed at a depth of 10 to 500 nm so that the surface concentration of, e.g., phosphorus, arsenic, or antimony is 10 17 to  10 21  to cm −3 . The N-type impurity diffusion layers  51  are shared by adjacent semiconductor memories to realize a NAND connection.  
         [0241]     The floating gate electrodes  22  (SSL) and  22  (GSL) are gate electrodes connected to the block selecting lines SSL and GSL, respectively, and formed by the same layer as the floating gate electrode of the floating gate type EEPROM.  
         [0242]     The gate length of the floating gate electrodes  22  (SSL) and  22  (GSL) is longer than that of the semiconductor memory gate electrode, e.g., 0.02 to 1 μm. This makes it possible to increase the on/off ratio of the state in which a block is selected to the state in which no block is selected, and to prevent write errors and read errors.  
         [0243]     Also, N-type impurity diffusion layers  51   d  formed on one side of the control gate electrode  24  (SSL) is connected to data transfer lines  104  (BL) made of, e.g., W, Wsi, Ti, TiN, or Al via contacts  102   d  formed in contact holes  101   d.    
         [0244]     Although not shown in  FIG. 24 , data transfer lines  104  (BL) are formed to the block boundaries along the vertical direction of the paper of  FIG. 24 , so as to be connected to the adjacent semiconductor memory blocks.  
         [0245]     On the other hand, N-type impurity diffusion layers  51 S formed on one side of the control gate electrode  24  (GSL) are connected to the source line SL (not shown) via contacts  102 S formed in contact holes  101 S.  
         [0246]     Although not shown in  FIG. 24 , the source line SL is formed to the block boundaries along the horizontal direction of the paper of  FIG. 24 , so as to be connected between the adjacent semiconductor memory blocks. The source line SL may also be obtained by forming the N-type impurity diffusion layers  51 S to the block boundaries in the horizontal direction of the paper.  
         [0247]     The contacts  102   d  for the data transfer lines BL and the contacts  102 S for the source line SL are conductor regions obtained by filling the contact holes  101   d  and  101 S with N- or P-doped polysilicon, W, Wsi, Al, TiN, or Ti. Portions between the source line SL, data transfer lines BL, and transistors are filled with an interlayer insulating film  105  made of, e.g., a silicon oxide film or silicon nitride film.  
         [0248]     On the data transfer lines BL, an insulating film protective layer  106  made of, e.g., a silicon oxide film, silicon nitride film, or polyimide is formed. Although not shown, upper interconnections made of, e.g., W, Al, or Cu are also formed.  
         [0249]     This embodiment has the following characteristic features in addition to the characteristic features of the first embodiment.  
         [0250]     (12) In this embodiment, data of a plurality of cells can be simultaneously erased by tunnel injection from the common P-type semiconductor region  13 . Therefore, multiple bits can be simultaneously erased at high speed while the power consumption during erase is suppressed.  
         [0251]     Also, this embodiment has the effect of increasing the width of the floating gate electrode  22  by the formation of the sidewall insulating film  31 . This achieves the following effects.  
         [0252]     (13) As shown in  FIGS. 6, 14 , and  20 , the width of the floating gate electrode  22  can be increased by an amount twice the thickness of the sidewall insulating film  31  with respect to the processing dimensions of the mask insulating film  26  which are determined by the lithography accuracy.  
         [0253]     Especially in a NAND EEPROM, the impurity diffusion layers of the memory cell transistors M 0  to M 15  are connected in series as they are shared between one impurity diffusion layer of the select transistor S 1  having the other impurity diffusion layer connected to the bit line BL and one impurity diffusion layer of the select transistor S 2  having the other impurity diffusion layer connected to the source line SL. Therefore, the diffusion layer resistance functions as a parasitic resistance. This reduces the electric current on the bit line BL during read, and thereby prolongs the read time.  
         [0254]     In this embodiment, the length of the impurity diffusion layer decreases by the increase in width of the gate electrode, and the parasitic resistance in the impurity diffusion layer reduces. As a consequence, the read electric current increases, and this increases the speed of the read operation.  
         [0255]     Also, in a NAND EEPROM, a leakage current from a NAND block or memory cell transistor which is not selected during read or from a memory cell transistor in a written state causes read errors. This leakage current increases as the gate length of a select transistor and memory cell transistor decreases. This is so because the off-leakage current of a transistor increases by the short channel effect. In particular, the cutoff characteristic of a select transistor is an important parameter.  
         [0256]     In this embodiment, the short channel effect improves by the increase in gate electrode width, and this reduces the leakage current, so the margin to read errors improves. In particular, the gate lengths of not only the memory cell transistors M 0  to M 15  but also the select transistors S 1  and S 2  can be increased without changing the NAND length, i.e., the distance between the contact of the source line SL and the contact of the bit line BL. This makes it possible to increase the density and improve the read characteristics of the semiconductor memory at the same time.  
         [heading-0257]     (E) Fifth Embodiment  
         [0258]     A nonvolatile semiconductor memory according to the fifth embodiment of the present invention will be described below.  
         [0259]     In this embodiment, the semiconductor memory structure of the second embodiment is used in a NAND cell array. Note that the same reference numerals as in the second embodiment denote the same elements, and an explanation thereof will be omitted. Note also that an equivalent circuit configuration and a planar arrangement are similar to those shown in  FIGS. 23 and 24 , so an explanation thereof will be omitted.  
         [0260]      FIG. 27  shows a longitudinal section taken along the line A-A in  FIG. 24 .  
         [0261]     As in the second embodiment, the sidewalls of a mask insulating film  26 , control gate resistance decreasing metal film  25 , and control gate electrode  24  are covered with a sidewall insulating film  31  made of, e.g., a 2- to 20-nm thick silicon nitride film or silicon oxynitride film.  
         [0262]     A sidewall insulating film  41  made of a silicon oxide film is formed on the sidewalls of a floating gate electrode  22 . N-type impurity diffusion layers  51  serving as source and drain regions are also formed.  
         [0263]     The impurity diffusion layers  51 , floating gate electrode  22 , and control gate electrode  24  form a floating gate type EEPROM cell in which a charge amount stored in the floating gate electrode  22  is used as an information amount.  
         [0264]     This embodiment has characteristic features (12) and (13) explained in the fourth embodiment in addition to the characteristic features of the second embodiment.  
         [heading-0265]     (F) Sixth Embodiment  
         [0266]     A nonvolatile semiconductor memory according to the sixth embodiment of the present invention will be described below.  
         [0267]     In this embodiment, the semiconductor memory structure of the third embodiment is used in a NAND cell array. Note that the same reference numerals as in the second embodiment denote the same elements, and an explanation thereof will be omitted. Note also that an equivalent circuit configuration and a planar arrangement are similar to those shown in  FIGS. 23 and 24 , so an explanation thereof will be omitted.  
         [0268]      FIG. 28  shows a longitudinal section taken along the line A-A in  FIG. 24 .  
         [0269]     As in the third embodiment, the sidewalls of a mask insulating film  26 , control gate resistance decreasing metal film  25 , control gate electrode  24 , and interpoly insulating film  23  and the sidewalls of the upper portion of a floating gate electrode  22  are covered with a sidewall insulating film  31  made of, e.g., a 2- to 20-nm thick silicon nitride film or silicon oxynitride film.  
         [0270]     A sidewall insulating film  41  made of a silicon oxide film is formed on the sidewalls of the lower portion of the floating gate electrode  22 . N-type impurity diffusion layers  51  serving as source and drain regions are also formed.  
         [0271]     The impurity diffusion layers  51 , floating gate electrode  22 , and control gate electrode  24  form a floating gate type EEPROM cell in which a charge amount stored in the floating gate electrode  22  is used as an information amount.  
         [0272]     This embodiment has characteristic features (12) and (13) explained in the fourth and fifth embodiments in addition to the characteristic features of the third embodiment.  
         [0273]     As described above, in the nonvolatile semiconductor memory according to each embodiment, the sidewalls of the metal layer forming the control gate electrode are covered with the sidewall insulating film. In the gate sidewall oxidation step, therefore, this metal layer does not abnormally oxidize, so the normal shape and dimensions as a gate electrode can be maintained. Accordingly, impurity diffusion layers can be normally formed by ion-implanting an impurity by using the gate electrode as a mask after that, and this improves the yield.  
         [0274]     The above embodiments are merely examples and hence do not limit the present invention. For example, the method of forming the element isolation films and insulating films is not limited to the method of the above embodiments in which silicon is converted into a silicon oxide film or silicon nitride film, and it is also possible to use, e.g., a method of injecting oxygen ion into deposited silicon or a method of oxidizing deposited silicon.  
         [0275]     In addition, the interpoly insulating film  23  may also be a TiO 2  film, Al 2 O 3  film, tantalum oxide film, strontium titanate film, barium titanate film, zirconium lead titanate film, ZrSiO film, HFSiO film, ZrSiON film, or HFSiON film, or a stacked film having at least two layers of any of these films.  
         [0276]     The sidewall insulating film  31  and mask insulating film  26  need only be oxidation-resistant insulating films. Examples are an Al 2 O 3  film, ZrSiO film, HFSiO film, ZrSiON film, HFSiON film, Si film, or SiON film, or a stacked film having at least two layers of any of these films.  
         [0277]     In each of the above embodiments, a P-type substrate is used as a semiconductor substrate. However, this semiconductor substrate can be any silicon-containing single-crystal semiconductor substrate. Examples are an N-type semiconductor substrate, an SOI silicon layer of an SOI substrate, an SiGe mixed crystal layer, and an SiGeC mixed crystal layer.  
         [0278]     Furthermore, although an N-type MOSFET is formed on a P-type semiconductor substrate in each of the above embodiments, a P-type MOSFET may also be formed on an N-type semiconductor substrate. In this case, N-type and P-type in the above embodiments are replaced with P-type and N-type, respectively, and a doping impurity As, P, or Sb in the above embodiments is replaced with IN or B.  
         [0279]     Also, as the control gate electrode, it is possible to use an Si semiconductor, SiGe mixed crystal, or SiGeC mixed crystal, or a stacked structure of these materials.  
         [0280]     As the control gate resistance decreasing metal film, it is possible to use silicide or polycide such as TiSi, NiSi, CoSi, TaSi, Wsi, or MOSi, or a metal such as Ti, Al, Cu, TiN, or W.  
         [0281]     Each of the above embodiments is explained by taking a NAND semiconductor memory as an example. However, the first to third embodiments are also applicable to a NOR semiconductor memory or a stand-alone semiconductor memory.  
         [0282]     When W is used as the control gate resistance decreasing metal film, a 0.5- to 10-nm thick barrier metal made of, e.g., WN or Wsi is desirably formed between this control gate resistance decreasing metal film and the control gate electrode, in order to prevent unevenness of the interface in a heating step performed after the gate structure is stacked.  
         [0283]     Moreover, the above embodiments can be variously modified without departing from the technical scope of the present invention.