Abstract:
Different circuit-based implementations of stochastic anti-windup PI controllers are provided for a motor drive controller system. The designs can be implemented in a Field Programmable Gate Arrays (FPGA) device. The anti-windup PI controllers are implemented stochastically so as to enhance the computational capability of FPGA.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the priority of U.S. Provisional Application 60/969,506,which was filed on Aug. 31, 2007 with the U.S. Patent and Trademark Office and which is incorporated herein in its entirety. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention is related to the field of motor drive controllers for induction motor systems, and more particularly, to proportional-integral (PI) controllers. 
       BACKGROUND OF THE INVENTION 
       [0003]    A command signal intended to induce a large step change in the speed of a variable-speed motor drive typically causes the generated current command from a PI speed controller to exceed the prescribed maximum value, which is limited by the converter protection, the magnetic saturation, and the motor overheating. Thus, a saturator is usually applied, which introduces non-linearity into the system. This phenomenon is referred to as integrator windup. The phenomenon can result in a reduction in performance owing to the fact that the parameters of the PI speed controller are normally designed to operate in a linear region without regard to the nonlinearity that typically results from saturation. 
         [0004]    A number of anti-windup techniques have been proposed in an attempt to overcome the windup phenomenon. One drawback of these conventional methods, however, is the complexity of the hardware implementation. Solutions for motor driver controllers implemented in circuits such as Field Programmable Gate Arrays (FPGAs) offer advantages in terms of price, execution speed, and flexibility. FPGAs, moreover, can perform rapid close-loop tasks without interfering with other tasks. Nonetheless, FPGAs are encumbered by relatively poor calculation capabilities and the relatively low number of available logic gates. Accordingly, there is a need for devices and techniques that more efficiently and effectively implement PI controllers, especially those utilizing FPGAs. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0005]    There are shown in the drawings, embodiments which are presently preferred. It is expressly noted, however, that the invention is not limited to the precise arrangements and instrumentalities shown. 
           [0006]      FIG. 1  is a schematic view of an exemplary circuit in which a PI controller, according to one embodiment of the invention, is utilized. 
           [0007]      FIG. 2  is a schematic view of a stochastic PI controller, according one embodiment of the invention. 
           [0008]      FIG. 3  is a schematic view of a stochastic PI controller, according to another embodiment of the invention. 
           [0009]      FIG. 4  is a schematic view of a stochastic PI controller, according to still another embodiment of the invention. 
           [0010]      FIG. 5  is a schematic view of a digital integrator, according to another embodiment of the invention. 
           [0011]      FIGS. 6A and 6B  are schematic views, respectively, of a conventional digital integrator and a stochastic-based digital integrator according to an embodiment of the invention. 
           [0012]      FIG. 7  is a schematic representation of a randomization process, according to another embodiment of the invention. 
           [0013]      FIG. 8  is a schematic view of a digital design scheme of a proposed stochastic anti-windup PI controller, according to yet another embodiment of the invention. 
           [0014]      FIG. 9  is a schematic view of another digital design scheme of a proposed stochastic anti-windup PI controller, according to still another embodiment of the invention. 
           [0015]      FIG. 10  is a schematic view of another digital design scheme of a proposed stochastic anti-windup PI controller, according to yet another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    The invention is directed to various devices and methods for implementing stochastic anti-windup PI controllers. The invention encompasses different circuit arrangements that, according to different embodiments of the invention, implement distinct anti-windup algorithms for a digital PI speed controller. As described herein, the anti-windup algorithms implemented by the circuit arrangements can significantly improve the control performance of variable-speed motor drives. 
         [0017]    In particular embodiments described herein, the different implementations utilize a FPGA device and are configured on the basis of stochastic theory. The combination of a FPGA device with the application of certain principles drawn from stochastic theory in accordance with the invention enhance the computational capability of FPGA. 
         [0018]      FIG. 1  is a schematic view of an exemplary circuit  100  in which a stochastic anti-windup PI controller  102 , according to one embodiment, implemented in an FPGA  103  is utilized. Illustratively, the PI controller  102  is connected to an exemplary variable-speed motor drive  105  and provides control signaling to the second device. The stochastic anti-windup PI controller  102  can alternately be any one of the different stochastic anti-windup PI controller implementations described more particularly below. As described, each alternate embodiment is based on a particular stochastic anti-windup digital PI control algorithm. 
         [0019]      FIG. 2  is a schematic view of a circuit-based implementation  200  of a first stochastic anti-windup digital PI control algorithm, according to one embodiment of the invention. Illustratively, the algorithm is implemented utilizing a randomization block  202  connected to a signal input  204  connected to a first dual-input AND gate  206 A and a second dual-input AND gate  206 B, which in turn are each connected to an up/down counter  208 . One input of the first AND gate  206 A is connected to a first inverter  207 A and one input of the second AND gate  206 B is connected to a second inverter  207 B. Illustratively, a sampler  210  samples an analog signal that is then converted to an analog signal by an analog-to-digital (A/D) converter  212 . 
         [0020]    As illustrated, a saturation signal  214  is connected to the up/down counter  208  through the two AND gates  206 A,  206 B. When the saturation signal  202  is ‘1’, the output of the two AND gates  206 A,  206 B both become ‘0’, which disables the accumulation of the up/down counter  208 . The integration process operates normally when the saturation signal  202  is ‘0’ for the linear region. Accordingly, the illustrated scheme performs the same anti-windup function as the conventional anti-windup strategy, as the integration action switches off when saturation occurs. 
         [0021]      FIG. 3  is a schematic view of a circuit-based implementation  300  of a second stochastic anti-windup digital PI control algorithm, according to another embodiment of the invention. Again, a randomization block  302  is connected through a first dual-input AND gate  304 A and a second dual-input AND gate  304 B to an up/down counter  306 . 
         [0022]    According this implementation, when the output of the PI controller exceeds the upper limit of a saturator, the first AND gate  304 A transmits a ‘0’ to an up port of the up/down counter  306 , and the down port continues to receive transmitted pulses. Thus, the integral term will decrease, which, as a result, tends to bring the PI controller back to the linear region. The saturation happens at the lower limit. That causes the increase of the integral term and avoids an accumulation of errors. 
         [0023]      FIG. 4  is a schematic view of a circuit-based implementation  400  of a third stochastic anti-windup digital PI control algorithm, according to another embodiment of the invention. The exemplary circuit comprises a first randomization block  402 A a second randomization block  402 B, and a third randomization block  402 C. The exemplary circuit further includes a first dual-input AND gate  404 A, a second dual-input AND gate  404 B, a third dual-input AND gate  404 C, and a fourth AND gate  404 D. Additionally, the exemplary circuit for implementing this third anti-windup digital PI control algorithm includes an up/down counter  406 . 
         [0024]    As shown, the first randomization block  402 A is connected to one input of the first dual-input AND gate  404 A and, through an inverter  405 A, to an input of the second dual-input AND gate  404 B. The second randomization block  402 B is connected to an input of the fourth randomization block  404 D, the other input of which receives a saturation signal. The third randomization block  402 C is connected to an input of the third dual-input AND gate  404 C, the other input of which also receives the saturation signal. As further illustrated, the output of the fourth dual-input AND gate  404 D is inverted and supplied to an input of the first dual-input AND gate  404 A. The output of the third dual-input AND gate  404 C is inverted and supplied to an input of the second dual-input AND gate  404 B. The output of the first AND gate  404 A is supplied to the up port of the up/down counter  406 , and the output of the second AND gate  404  B is supplied to the down port of the up/down counter. 
         [0025]    This scheme provides a tuning parameter to adjust the anti-windup performance. The output of the PI controller is randomized to a bit-stream and connected with the saturation signals as well as with AND gates. In this way, when saturation occurs, the up and down ports all are receiving incoming pulses, but the randomization process determines the rate of the increase or decrease for the integral term when saturation occurs. The constant C in the randomization process becomes a free tuning parameter, that can be adjusted to achieve an optimized performance. 
         [0026]    The digital integrator can be expressed as in equation (1), following: 
         [0000]        y ( n )= x ( n )+ y ( n− 1)  (1) 
         [0027]      FIG. 5  is a schematic view of the structure of the digital integrator  500 . 
         [0028]      FIG. 6A  is a schematic view of a digital integrator  600 A according to a traditional Accumulator design. As shown, a register  602 , preferably a large-size register, holds the previous output of the integrator  600 A and transmits a one-step, time-delayed output signal back to an n-bit adder  604  to perform the integration function. 
         [0029]      FIG. 6B  is a schematic view of an alternative, stochastic digital integrator  600 B, the design of which is based upon stochastic arithmetic according to an embodiment of the invention. The stochastic digital integrator  600 B illustratively comprises the following elements: a signal-value-to-frequency converter (randomization block)  602  and an up-down (pulse) counter  606 , the output of which is summed with the output of a counter. 
         [0030]      FIG. 7  is a schematic view of a randomization block  700 . The randomiation block  700  illustratively includes a comparator  602 , a first input of which receives the output of an op amp  604  and a second input of which receives the output of a pseudo-random engine. With the randomization process effected by the exemplary circuit shown in  FIG. 7 , the value of the input signal x is represented by the frequency of ‘1’, which appears in the output bit stream. If p is the probability of having a bit value of ‘1’ in any position in the bit stream, then the value of the input signal is given by equation (2), following: 
         [0000]        x =(2 p− 1)· c,   (2) 
         [0000]    where c is a constant, and the input x lies in the range of −c and c. For example, if the input x equals c, then the output bit stream will be all ‘1’s. If x equals −c, the output bit stream will be all ‘0’s. After this process concludes, the up/down counter  606  accumulates the incoming pulses and performs the integration function. 
         [0031]    Compared with the conventional approach of implementing a digital integrator, the stochastic method has a larger dynamic range and can obviate the need for an n-bit adder that typically contains tens of logic gates. Although the randomization process requires extra digital resources for the pseudo random engine and the comparator, these resources can be shared if many digital integrators are employed in the same digital integrated circuits (ICs), thereby saving the digital resources occupied by single digital integrator for large systems. 
         [0032]      FIG. 8  schematically illustrates a digital design scheme of the proposed stochastic anti-windup PI controller  800 , according to a particular embodiment. The PI controller  800 , according to this embodiment, comprises a signal input  802  connected to an A/D converter  804 . The signal output of the A/D converter is supplied to processing circuitry comprising arithmetic-logic units (ALUs)  806 , the output of which supplied to one port of a comparator  808 . The PI controller  800  illustratively includes a pseudo random generator  810  that supplies a signal to the other port of the comparator  808 . The comparator  808  is connected to inputs of a pair of AND gates  812 A,  812 B. (As shown the signal inputs of one gate  812 B are inverted.) The signal outputs of the pair of AND gates  812 A,  812 B are supplied to a an up/down counter  813 , the output of which is supplied to additional processing circuitry  814  and an input of an XOR gate  815 , which in turn supplies a signal to another comparator  816 . The PI controller  800  further includes a digital-to-analog (D/A) converter  817  connected through an ALU  818  to the comparator  816 . 
         [0033]      FIG. 9  schematically illustrates another digital design scheme of the proposed stochastic anti-windup PI controller  900 , according to another embodiment. The PI controller  900 , according to this embodiment, also comprises a signal input  902  connected to ah A/D converter  904 . The signal output of the A/D converter is supplied to processing circuitry comprising arithmetic-logic units (ALUs)  906 , the output of which supplied to one port of a comparator  908 . The PI controller  900  illustratively includes a pseudo random generator  910  that supplies a signal to the other port of the comparator  908 . Signal inputs, as shown, to one port of each of the AND gates  912 A,  912 B are inverted. The signal outputs of the pair of AND gates  912 A,  912 B arc supplied to an up/down converter  913 , the output of which is supplied to additional processing circuitry  914  and two additional AND gates  916 A,  916 B as well as an input to an XOR gate  917 . The output of the up/down converter  913  is supplied to another comparator  918  through the additional processing circuitry  914 . A signal is supplied to a D/A  922  connected through an ALU  920 . 
         [0034]      FIG. 10  schematically illustrates a digital design scheme of the proposed stochastic anti-windup PI controller  1000 . The PI controller  1002 , according to this embodiment, also comprises a signal input  1002  connected to ah A/D converter  1004 . The signal output of the A/D converter is supplied to processing circuitry comprising arithmetic-logic units (ALUs)  1006 , the output of which supplied to one port of a comparator  1008 . The PI controller  900  illustratively includes a pseudo random generator  1010  that supplies a signal to the. other port of the comparator  1008 . The comparator provides a signal to inputs of a pair of AND gates  1012 A,  1012 B. (The signal input to one AND gate  1012 B is inverted.) The other respective inputs of the pair of AND gates  1012 A,  1012 B are signals (inverted) supplied by the output of two additional AND gates  1014 A,  1014 B. The signal outputs of the pair of AND gates  1012 A,  912 B are supplied to an up/down converter  1016 , the output of which is supplied to additional processing circuitry  1018  as well as an input to an XOR gate  1020 . The output of the up/down converter  1016  is supplied to another comparator  1020  through the additional processing circuitry  1018 . A signal is supplied to a D/A converter  1022  connected through an ALU  1024 . 
         [0035]    The stochastic arithmetic performed by the circuitry provides a better way to enhance the computation capability of an FPGA with the same logic gate density of conventional circuits. The stochastic PI controller provides an efficient implementation approach that uses straightforward digital logic circuits but has the advantage of significantly reducing the circuit complexity compared with the traditional digital implementation approach. Therefore, the present invention notably improves the performance of the stochastic PI controller and saves digital resources in a motor drive control system. 
         [0036]    The invention can be realized in hardware or a combination of hardware and software. The invention can be realized in a centralized fashion in one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software can be a general purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein. 
         [0037]    The invention, as also already noted, can be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form. 
         [0038]    The foregoing description of preferred embodiments of the invention have been presented for the purposes of illustration. The description is not intended to limit the invention to the precise forms disclosed. Indeed, modifications and variations will be readily apparent from the foregoing description. Accordingly, it is intended that the scope of the invention not be limited by the detailed description provided herein.