Abstract:
A method for manufacturing an embedded package comprises the steps of: coupling at least one first embedded body including at least one connection port with a first circuit substrate and packaging the first embedded body and the first circuit substrate to form a package; and exposing the connection port of the package on an outer side of the package for other electronic carriers to couple with. The invention can overcome the disadvantage of the conventional System in Package manufacturing process which integrally packages multiple ICs in a same package to result in discard of the entire package because of failure of a single IC. The method of the invention makes assembly simpler, expansion, test and replacement of IC components easier, and also can reduce manufacturing time and accumulated heat, lower the cost and improve yield rate.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a method for manufacturing a package and structure thereof, particularly an integrated package comprising an embedded body and the structure thereof. 
       BACKGROUND OF THE INVENTION 
       [0002]    In recent years semiconductor package technology includes two-dimensional System on Chip (SoC) which aims to cluster electronic systems into integrated circuits formed on a single chip. It has many advantages such as lower power consumption, higher performance and smaller package area. But design of SoC takes a great deal of time, and packaging different elements on one IC still takes significant area on the produced IC, hence its range of application is limited. 
         [0003]    System in Package (SiP) is a newly developed package technique which deploys all or most electronic functions of a system or sub-system in an integrated substrate. Compared with SoC it has many benefits such as smaller size, higher performance, shorter development cycle and lower cost. System in Package (SiP) includes many types of techniques, for example, three dimensional integration system-in-package, 3D IC and through silicon via (TSV). 
         [0004]    However, through silicon via (TSV) technique has a much higher technical threshold and manufacturing cost, thus it is not widely adopted yet. At present other techniques such as Multi-chip Package (MCP), Stack Die, Package on Package (PoP), Package in Package (PiP) and Embedded Substrate are the main stream in the package industry. 
         [0005]    The manufacturing methods of SiP adopted the technique of MCP and the like generally integrate a plurality of ICs into a package. However, the ICs before integration are usually not all known good dies. Hence before and after integration of ICs the problems of complex tests and heat dissipation are encountered. Moreover, in the event that any IC is damaged, the entire 3D IC has to be discarded. 
         [0006]    Hence how to provide a solution to improve the SiP technology is a critical issue yet to be resolved. 
       SUMMARY OF THE INVENTION 
       [0007]    The primary object of the present invention is to provide a package manufacturing method to facilitate assembly, expansion, test and replacement. 
         [0008]    To achieve the foregoing object, the present invention provides a method for manufacturing an embedded package that comprises the steps of: coupling at least one first embedded body which includes at least one connection port with a first circuit substrate and packaging the first embedded body and the first circuit substrate to form a package; and cutting the package to expose the connection port of the first embedded body at an outer side of the package. 
         [0009]    The invention also provides an embedded package structure which includes at least one package includes a first circuit substrate and at least one first embedded body to couple with the first circuit substrate. The first embedded body includes at least one connection port open at an outside of the package. 
         [0010]    By means of the techniques set forth above, the invention improves the shortcoming of conventional techniques that packages the entire IC in one package to result in discard of the entire IC chip when a single IC is failure. Moreover, the package can be made with high pin count to serve as a carrier and the peripheral IC can be inserted into the connection port, thus the peripheral IC, module and controller can be inserted and coupled according to different requirements, or other systems or equipments also can be connected with the package through flat cables. 
         [0011]    In short, the method for manufacturing an embedded package and structure thereof according to the invention provides many advantages, notably: 
         [0012]    1. Easier in assembly, expansion, test and replacement of IC components; 
         [0013]    2. Shorter manufacturing time; 
         [0014]    3. Reduce heat accumulation; 
         [0015]    4. Reduce cost; and 
         [0016]    5. Improve production yield. 
         [0017]    The foregoing features and advantages of the invention will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]      FIG. 1A  is a first schematic view for assembling a first embodiment of the manufacturing method of the invention. 
           [0019]      FIG. 1B  is a second schematic view for assembling the first embodiment of the manufacturing method of the invention. 
           [0020]      FIG. 2  is a first schematic view for assembling the first embodiment of the invention with another type of embedded body. 
           [0021]      FIG. 3  is a second schematic view for assembling the first embodiment of the invention with yet another type of embedded body. 
           [0022]      FIG. 4  is a third schematic view for assembling the first embodiment of the manufacturing method of the invention. 
           [0023]      FIG. 5  is a first schematic view for assembling the first embodiment of the invention with another type of package. 
           [0024]      FIG. 6  is a second schematic view of the first embodiment of the invention with yet another type of package. 
           [0025]      FIG. 7  is a first schematic view of a second embodiment of the manufacturing method of the invention. 
           [0026]      FIG. 8  is a second schematic view of the second embodiment of the manufacturing method of the invention showing the assembly process. 
           [0027]      FIG. 9  is a third schematic view of the second embodiment of the manufacturing method of the invention after assembly. 
           [0028]      FIG. 10  is a schematic view of a third embodiment of the manufacturing method of the invention. 
           [0029]      FIG. 11  is a schematic view of the third embodiment of the manufacturing method of the invention in an expanding condition. 
           [0030]      FIG. 12  is a schematic view of the structure of the invention. 
           [0031]      FIG. 13  is a first schematic view of the manufacturing method of the invention in a cutting process. 
           [0032]      FIG. 14  is a second schematic view of the manufacturing method of the invention in the cutting process. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0033]    Please refer to  FIGS. 1A through 6  for a first embodiment of the method for manufacturing an embedded package according to the invention. To facilitate discussion, a manufacturing process of a USB 3.0/Micro-USB dual connector flash drive is used as an example below. The manufacturing process comprises: 
         [0034]    Step 1: Referring to  FIG. 1A , coupling an first embedded body  1  including a plurality of connection ports  11  with a first circuit substrate  2  which has flash memory chips (not shown in the drawings), a control circuit (also not shown in the drawings) and metal contacts  21  and  22  for USB 2.0 and USB 3.0. The first embedded body  1  can be male or female formed by an epoxy molding compound (EMC) or through injection molding. A female seat is employed as an embodiment for discussion below. After the first embedded body  1  (or the first embedded body  1   a  shown in  FIG. 2 ) is coupled with the first circuit substrate  2 , they are packaged into a package  3 , and the connection ports  11  are not yet exposed at an outer side of the package  3 . 
         [0035]    Step 2: Cutting one side (indicated by arrows) of the package  3  where the first embedded body  1  is located to expose the connection ports  11  as shown in  FIG. 1B , so that the connection ports  11  are exposed at the outer side the package  3 . The first embedded body  1  can be implemented in another type as shown in  FIG. 2  which differs from  FIG. 1A  by having a plurality of first embedded bodies  1   a  each includes a connection port  11   a  to couple with the first circuit substrate  2 , then are packaged to form the package  3   a  as shown in  FIG. 3 . The package  3   a  also is cut to expose the individual connection ports  11   a  of the first embedded body  1   a  at the outer side of the packaged element  3   a.    
         [0036]    It should be noted that at step 2, the connection ports  11  and  11   a  can also be exposed and open at the outer side of the package  3  through positioning of the first embedded body  1  (or the first embedded body  1   a ) at selected positions to save the cutting process. 
         [0037]    Thus, please refer to  FIG. 1B  or  3 , a micro-USB connector a can be easily inserted and connected with the connection ports  11  or  11   a ; then as shown in  FIG. 4 , through a SMT (Surface Mount Technology) or other coupling techniques such as latching or bonding (also can be selectively injecting adhesive) a USB 3.0 connection member b can be coupled with the package  3  (such a coupling technique has been disclosed in R.O.C. patent M439795 which mainly provides a feature to upgrade a memory drive of USB 2.0 interface to support a memory drive of USB 3.0 interface), thereby form an embedded package structure of a USB 3.0/Micro-USB dual connector flash memory drive through the method for manufacturing an embedded package of the invention. 
         [0038]    The package  3  at step 1 as previously discussed can further be implemented in another embodiment that a package  3   z  including a plurality of terminals p, as shown in  FIGS. 5 and 6 . Prior to step 1, the plurality of terminals p can be positioned in the connection ports  11   z  and coupled with the first embedded body  1   z  through injection encasing molding, latching or surface mount technology. The surface mount technology (SMT) discussed here is glue filling. After the coupling is formed, the terminals p have one end extended and exposed at one side of the first embedded body  1   z  so that the terminals p can connect to metal contacts  21   z  and form electric connections with the first circuit substrate  2   z . Finally, the package  3   z  is formed through a packaging process; then the package  3   z  can continue the step 2 previously discussed and install a Micro-USB connector a for power supply or data transmission, thus finish an embedded package structure. 
         [0039]    At present the general multi-chip package (MCP) technology integrates and packages two or more memory chips in a same Ball Grid Array (BGA) package through horizontal positioning and/or vertical stacking manner. A second embodiment of the invention also provides a novel application for the MCP technology. Please referring to  FIGS. 7 through 9 , the method includes: 
         [0040]    Step 1: coupling a plurality of first embedded bodies  1   b  each includes a plurality of connection ports  11   b  with a first circuit substrate  2   b  including multiple chips c or electronic elements d, and packaging them to form a package  3   b  which can be a BGA or Land Grid Array (LGA) with high pin count. In this embodiment a BGA package  3   b  is used. The first circuit substrate  2   b  has pins extended to each side thereof so that the first embedded bodies  1   b  can be positioned at four sides of the first circuit substrate  2   b.    
         [0041]    Step 2: cutting the four sides of the package  3   b  to expose the connection ports  11   b  and make them open at four sides of the package  3   b.    
         [0042]    Step 3: stacking a bonding intermediate layer  4  and an first electronic carrier  5  on one side of the package  3   b  formed at the step 2. The intermediate layer  4  can be thermal grease, a silicon substrate, a washer, a metal layer, a dielectric layer or a thin film. The first electronic carrier  5  can be a circuit substrate, a chip, an electronic element or any package elements. In this embodiment the intermediate layer  4  and the first electronic carrier  5  are respectively thermal grease and a LGA package as shown in  FIG. 8 . To prevent generation of electromagnetic interference (EMI) after stacking, a sputter process can be executed on the first circuit substrate  2   b  of the package  3   b  or the first electronic carrier  5 , or a metal material can be interposed between the package  3   b  and the first electronic carrier  5 . Through the steps  1 ,  2  and  3  previously discussed a package manufacturing method which is simpler, faster and lower cost with improved heat dissipation can be realized. 
         [0043]    Furthermore, the package  3   b  at the step 3 mentioned above can be connected with at least one second electronic carrier  7  with a pin thereon. The second electronic carrier  7  can be another circuit board, a chip, an electronic element, a package element or a line connector for transmission, such as a peripheral IC, a controller, a LGA or BGA package, a flat cable, a signal line, or a transmission line (not shown in the drawings). Therefore the second electronic carrier  7  can be inserted into the connection ports  11   b  of the package  3   b  formed at the step 2 to form a SiP product which includes a stacked embedded package inserted by the peripheral IC. 
         [0044]    Please refer to  FIG. 10  for a third embodiment of the invention. It is different from the second embodiment that the first electronic carrier  5  in the second embodiment is replaced by another LGA-packaged first electronic carrier  5   a  (i.e. coupling at least one second embedded body  1   c  with a second circuit substrate  2   c , and the second embedded body  1   c  includes a plurality of connection ports  11   c ) processed through the steps  1  and  2  as previously discussed. Furthermore, in this embodiment the connection ports  11   c  of the stacked first electronic carrier  5   a  can be electrically connected to the connection ports  11   b  via at least one connecting member  6 . The connecting member  6  can be a wire, conductive adhesive or a plated wire formed by a redistribution layer (RDL) technique. 
         [0045]    Thus, in this embodiment after stacking of the package  3   b  and the first electronic carrier  5   a , at least one second electronic carrier  7  with the pin thereon or the transmission line (such as flat cable) can be inserted into the connection port  11   b  of the package  3   b  (like in the second embodiment). Or, the second electronic carrier  7  with the pin thereon or the transmission line can also be inserted into the connection port  11   c  of the electronic carrier  5   a  stacked above the package  3   b.    
         [0046]    In addition, in the event that the second electronic carrier  7  horizontally inserted into the first electronic carrier  5   a  also includes the connection ports  11   y , the second electronic carrier  7  also can be horizontally inserted by a third electronic carrier  8  with a pin thereon to enhance expandability, as shown in  FIG. 11 . The third electronic carrier  8  is a circuit board, a chip, an electronic element or a package element. Moreover, each second electronic carrier  7  or the third electronic carrier  8  can also be vertically stacked via the intermediate layer  4 . As the manufacturing method of the invention can be flexibly applied in a mixed fashion (i.e. expanded both in horizontal positioning and vertical stacking manner), it gets excellent applicability and expandability. 
         [0047]    Moreover, the structure made via the embedded package manufacturing method of the invention can be illustrated by referring to  FIG. 12 . It includes a plurality of packages  3   d ,  3   e  and  3   f  (package  3   d  is a BGA package, and packages  3   e  and  3   f  are LGA packages). The packages  3   d ,  3   e  and  3   f  are coupled with each other through a plurality of intermediate layers  4 , and include respectively first circuit substrates  2   d ,  2   e  and  2   f . The first circuit substrates  2   d ,  2   e  and  2   f  respectively include embedded bodies  1   d ,  1   e  and  1   f  that have respectively a plurality of connection ports  11   d ,  11   e  and  11   f  which are exposed at the outer side of the packages  3   d ,  3   e  and  3   f . In addition, the embedded package structure of the invention further includes at least one second electronic carrier  7   a  to form electric connection with the connection port  11   d  of the package  3   d , and the second electronic carrier  7   a  is the same as the electronic carrier  7  previously discussed, hence can be implemented in an circuit board with the pin, a package element with the pin or a transmission line. 
         [0048]    Furthermore, when the embodiments previously discussed are cut at the step 2, the multiple first embedded bodies including the connection ports that are coupled on the same circuit substrate can be arranged and packaged according to a predetermined layout to form a package. While packaging is finished, each package is cut in an array fashion according to a predetermined path to form a plurality of separated package elements to save manufacturing time. 
         [0049]    For instance, please referring to  FIG. 13 , to produce the package  3  depicted in  FIG. 1A  an first embedded body  1   g  including connection ports  11   g  is disposed on a first circuit substrate  2   g , then a packaging process is performed to form a package  3   g . Next, performing one cutting process with a cutter according to a predetermined path (indicated by arrows in the drawing) to slit the package  3   g  and embedded body  1   g  into two separated package elements and also expose the connection ports  11   g.    
         [0050]    Similarly, as shown in  FIG. 14 , to produce the MCP or SiP as mentioned in the embodiment 2, a plurality of first embedded bodies  1   h  including multiple connection ports (not shown in the drawing) can be arranged in a preset layout on a first circuit substrate or a substrate  9  made of a wafer and packaged. Then the substrate  9  is cut according to preset paths corresponding to the arranged layout (indicated by solid lines in the drawing) to form multiple independent package elements and expose the connection ports. 
         [0051]    The method of positioning the first embedded bodies and performing cutting after packaging them (not limited to the drawings or description depicted above) as discussed above can further reduce manufacturing time and improve production efficiency. 
         [0052]    It is to be noted that the first circuit substrates  2 ,  2   b ,  2   d ,  2   e  and  2   f  discussed in the previous embodiments can also be implemented like a package loading board with a separable metal layer disclosed in R.O.C. patent 1421958 (illustrated in  FIG. 1I  of the said reference); i.e., forming a patterned metal layer which includes a plurality of conductive connection pads on the separable metal layer, and using a packaging material to cover the chip, the conductive connection pads and the separable metal layer, then removing the package loading board to expose the separable metal layer. Thereby the packages  3 ,  3   b ,  3   d ,  3   e ,  3   f  and  3   g  without features of the circuit substrate can be obtained, and they also provide same effect depicted in the invention. 
         [0053]    In short, when the invention is implemented according to the manufacturing process of the first embodiment, it is applicable for production of an embedded package structure like a USB flash drive. Details are omitted herein. When the invention is implemented through the manufacturing process of the second embodiment, a stacked structure can be formed by coupling individual packages through intermediate layers, and the corresponding connection ports of the packages can be connected electrically through a connection element to finish the embedded package structure used in SiP. 
         [0054]    When the invention is practically adopted on products, the same type of products can be coupled together, such as stacking of flash memories. In addition, products with thousands of high pin count or high complexity or high frequency application (such as products of 3D packaging, MCP, or eMCP) can be used as carriers (such as a wireless communication module), then be coupled in series with other peripheral IC package bodies (such as coupled in series with a GPS module and a multimedia module). 
         [0055]    As a conclusion, the invention can be applied on SiP, such as 3D IC, through vertical stacking, horizontal insertion, mixed coupling through stacking and insertion, stacking and insertion after horizontal insertion or the like to get improved applicability. The method of the invention not only can overcome the drawbacks of the conventional techniques that integrate all ICs on the same stack, also can improve yield rate, save time and make assembly and test easier. 
         [0056]    While the preferred embodiments of the invention have been set forth for the purpose of disclosure, they are not the limitation of the invention, modifications of the disclosed embodiments of the invention as well as other embodiments thereof may occur to those skilled in the art. Accordingly, the appended claims are intended to cover all embodiments which do not depart from the spirit and scope of the invention.