Abstract:
A switch mode power converter circuit ( 20, 50 ) adapted to receive a driver voltage V diver  includes a boot capacitor C boot  and a recharger for restoring the charge to the boot capacitor C boot  to a voltage substantially equal to the driver voltage V driver , where the recharger is internal to the circuit ( 20, 50 ). The recharger includes a synchronous rectifier S 5  which restores the boot capacitor C boot  to a voltage equal to the driver voltage V driver  less the voltage V S5  across the synchronous rectifier S 5 . Alternatively, the recharger may include a synchronous rectifier S 5  and a first switch S 4  of a charge pump circuit ( 22 ) that restore the charge to the boot capacitor C boot  in parallel to a voltage equal to the driver voltage V driver  less the voltage V S5  across the synchronous rectifier S 5  plus the voltage V S4  across the first switch S 4 . The circuit ( 20, 50 ) is particularly useful for applications such as DSPs and mixed signal or analog circuits.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     Cross reference is made to the following patent applications, each assigned to the same assignee, the teachings of which are incorporated herein by reference: 
     
       
         
               
               
               
               
               
             
           
               
                   
               
               
                 U.S. Pat. No. 
                 Serial No. 
                 Filing Date 
                 Inventor 
                 Title 
               
               
                   
               
             
             
               
                 TBD 
                 09/389,691 
                 09/04/99 
                 Grant 
                 Charge-Pump Closely 
               
               
                   
                   
                   
                   
                 Coupled to Switching 
               
               
                   
                   
                   
                   
                 Converter to Improve 
               
               
                   
                   
                   
                   
                 Area Efficiency 
               
               
                 TBD 
                 09/389,810 
                 09/04/99 
                 Martinez, et al. 
                 Controlled Linear Start- 
               
               
                   
                   
                   
                   
                 up in Linear 
               
               
                   
                   
                   
                   
                 Regulator 
               
               
                 TBD 
                 09/389,809 
                 09/04/99 
                 Grant et al. 
                 Charge Pump Device 
               
               
                   
                   
                   
                   
                 and Method of 
               
               
                   
                   
                   
                   
                 Sequencing Charge 
               
               
                   
               
             
          
         
       
     
     TECHNICAL FIELD OF THE INVENTION 
     This invention relates generally to integrated circuits, more specifically to a switch mode power converter. 
     BACKGROUND OF THE INVENTION 
     As logic integrated circuits (ICs) have migrated to lower working voltages in the search for lower power consumption and higher operating frequencies, and as overall system sizes have continued to decrease, IC power supply designs with smaller size and higher efficiency are in demand. Switch mode power supplies, or DC to DC converters, as they are sometimes called, are frequently used in IC circuits such as digital signal processors (DSPs) and mixed signal analog circuits, etc., to efficiently convert an input supply voltage to voltage levels appropriate for internal circuitry as well as external circuitry that the IC is coupled to. For instance, a 2.8 volt supply voltage provided to a BiCMOS IC may need to be increased internally to 5.0 volts to operate internal CMOS circuitry. As appliances and circuit designs have continued to decrease in size, the need for smaller and more efficient IC switch mode power converters has increased. 
     FIG. 1 illustrates a block diagram of a buck topology switch mode power converter  10  of the prior art. Control circuit X 3  alternately turns on gate drivers X 1  and X 2 . When driver X 2  is off, the gate of Field Effect Transistor (FET) MN 2  is connected to ground  12 . FETs MN 1  and MN 2  are typically N-channel MOSFETs, for example. When X 2  is on, the gate of FET MN 2  is tied to V driver , turning on FET MN 2 . When driver X 1  is off, FET MN 1  is connected to ground  12 , turning off FET MN 1 . In some prior art buck topology converters, when driver X 1  is off, FET MN 1  is connected to the source of FET MN 1 , which has the same effect as the circuit topology shown. 
     When driver X 1  is on, the gate of FET MN 1  is connected to the upper plate  14  of C boot . Capacitor C boot  is adapted to have some positive voltage stored on it, V boot . The lower plate  16  of capacitor C boot  is coupled to the source of FET MN 1 , and by this means, the gate of FET MN 1  is pulled up to voltage V boot  above the source of FET MN 1 . Therefore, FET MN 1  is turned on, even as the source of FET MN 1  rises. Before FET MN 1  is turned on, the source of FET MN 1  is pulled to ground by FET MN 2 : FET MN 2  is then turned off and FET MN 1  is turned on. As a result, the source of FET MN 1  rises to the voltage V in  and the gate of FET MN 1  rises to (V in +V boot ). The use of the “bootstrap capacitor” or boot capacitor C boot  is a feedback technique which tends to improve linearity and input impedance of circuits operating over a wide range of input signals. Specifically, the boot capacitor C boot  allows FET MN 1  to be turned on without there being a permanent supply available which is high enough to hold FET MN 1  on even when the source of FET MN 1  is at V in . 
     When FET MN 1  is turned off and FET MN 2  is turned on again, the source of FET MN 1  returns to ground; however, some charge has been taken off boot capacitor C boot , so its voltage V boot  is lower than before. The voltage V boot  on boot capacitor C boot  needs to be restored to its previous value. In the prior art circuit  10  shown, the restoration of boot capacitor C boot  is accomplished by diode D 1  that is connected between voltage V driver  and the upper plate  14  of boot capacitor C boot . 
     FIG. 2 is a block diagram of a charge pump of the prior art typically used to generate the voltage V driver  for the circuit  10  shown in FIG. 1 from supply voltage V in . The capacitor C pump  is first charged to voltage V in  by closing switches S 1  and S 3 , with switches S 2  and S 4  open. Next, switch S 1  and S 3  are opened, and switches S 2  and S 4  are closed. Some of the charge stored in capacitor C pump  is pumped into capacitor C driver . When switches S 2  and S 4  are closed, the voltage at node A is slightly higher than the voltage at V driver , which is caused by the voltage drop across switch S 4 , created by the current flowing from capacitor C pump  to capacitor C driver . 
     SUMMARY OF THE INVENTION 
     The present invention achieves technical advantages as a circuit and method of restoring a charge to a boot capacitor of a switch mode power converter to an amount substantially equal to the amount of the driver voltage, V driver . 
     In a first embodiment, a switch mode power converter circuit is adapted to receive a driver voltage, including a boot capacitor and means for restoring the charge to a boot capacitor to a voltage substantially equal to the driver voltage, where the restoring means is internal to the circuit. The restoring means may include synchronous rectifier which restores the boot capacitor to a voltage equal to the driver voltage less the voltage V S5  across the synchronous rectifier S 5 . Alternatively, the restoring means may include a synchronous rectifier and a first switch of a charge pump circuit that restore the charge to the boot capacitor in parallel to a voltage equal to the driver voltage less the voltage across the synchronous rectifier plus the voltage across the first switch. 
     In a second embodiment, a switch mode power converter circuit is adapted to receive an input voltage and generate a driver voltage. The circuit includes a charge pump circuit providing a driver voltage, and the charge pump includes at least a first switch and a first transistor. The circuit also includes a buck converter having a boot capacitor coupled at least to the first switch and the first transistor of the charge pump circuit. The first switch and the first transistor are adapted to recharge the boot capacitor in parallel to a boot voltage in an amount substantially equal to the driver voltage. The boot voltage is equal to the driver voltage less the voltage across the first transistor plus the voltage across the first switch. 
     Also disclosed is a method of restoring a charge to a boot capacitor of a switch mode power converter circuit, where the circuit is adapted to receive an input voltage and generate a driver voltage. The method includes the step of restoring the charge to the boot capacitor. The restored charge of the boot capacitor is substantially equal to the driver voltage, and the restoring means is internal to the circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings, which form an integral part of the specification and are to be read in conjunction therewith: 
     FIG. 1 is a prior art block diagram of a typical buck topology switch mode power converter; 
     FIG. 2 illustrates a schematic of a prior art charge pump circuit used to generate a V driver , supply; 
     FIG. 3 shows the charge pump circuit of FIG. 2 integrated with a buck converter, with switch S 5  adapted to restore the voltage V boot  of boot capacitor C boot  in accordance with a first embodiment of the present invention; 
     FIG. 4 is a timing diagram for the circuit shown in FIG. 3 showing how voltages V driver  and V boot  are restored; 
     FIG. 5 illustrates a block diagram of a second embodiment of the present invention, with switch S 5  adapted to restore the charge V boot  to boot capacitor C boot  without the use of a charge pump; and 
     FIG. 6 is a timing diagram for the circuit shown in FIG. 5 showing how voltage V boot  is restored. 
     Like numerals and symbols are employed in different figures to designate similar components in various views unless otherwise indicated. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     A problem with the prior art switching converter circuit of FIG. 1 is that boot capacitor C boot  may only be restored to a diode voltage drop below signal V driver : voltage V boot  may be restored to a maximum of (V driver −V D1 ). If diode D 1  is a diode internal to an integrated circuit (IC), the voltage drop V D1  is large, perhaps a volt or more. If the diode D 1  is external to the IC, an additional component is required in the system design and the voltage drop is also large, typically about 400 mV or more. For example, if V driver  is 5 V, the maximum recharge voltage V boot  for boot capacitor C boot  in the prior art is 4 V−4.6 V. In the case where the V driver  supply is the same as V in , the presence of the diode voltage drop V D1  that reduces the recharge voltage available on the C boot  capacitor may require one or more of the following four disadvantageous corrective design-arounds, for example: 1) the use of a lower voltage threshold (V t ) FET for transistor MN 1 , which is expensive; 2) reducing the amount of drive voltage to FET MN 1 , resulting in reduced efficiency; 3) reducing the amount of drive voltage to FET MN 1  while using more devices in parallel to maintain efficiency, which increases costs; or 4) increased supply voltage V in  requirement. In the case where the V driver  supply is provided by a charge pump, a solution to the reduced amount of recharge voltage available on the C boot  capacitor may require one or more of the following, for example: 1) the use of a lower V t  FET for transistor MN 1 , which is expensive; 2) more stages in the charge pump which adds components and pin count, increasing costs and semiconductor real estate; 3) increased supply voltage for the charge pump, which is undesirable, because a low supply voltage is usually required; 4) reducing the amount of drive voltage to FET MN 1 , resulting in reduced efficiency; or 5) reducing the amount of drive voltage to FET MN 1  while using more devices in parallel to maintain efficiency, which increases costs. Another solution in the prior art is to use a separate supply and abandon the boot capacitor technique, which requires a separate supply and is not feasible for many applications. 
     The present invention achieves technical advantages as a circuit and method of efficiently restoring the voltage charge to a boot capacitor of a switch mode converter to a voltage very close to V driver , for example, within 0-200 mV of V driver , solving the above problems in the prior art. Referring to FIG. 3, a first embodiment of the present invention, circuit  20 , is shown, with a charge pump circuit  22  integrated with a buck (switch mode power) converter  26 . In accordance with the present invention, switch S 5  is coupled between node A and the V boot  voltage node, which switch S 5  is adapted to restore the voltage V boot  on capacitor C boot  in conjunction with switch S4. Preferably, switch S 5  is a PMOS transistor or synchronous rectifier having a voltage drop V S5  of 200 mV or less, and more preferably, a voltage drop V S5  of between 0-300 mV. Switch S 5  is adapted to recharge the boot capacitor C boot  by the synchronization of the charge pump circuit  22  operation to the buck converter  26  such that switches S 2  and S 4  are closed with FET MN 1  is off and FET MN 2  is on. Refer to U.S. patent application filed herewith, entitled, “Charge Pump Device and Method of Sequencing Charge Pump Switches” by Grant. Because switch S 5  is connected to node A rather than at V driver , as typical in the prior art, capacitor C boot  is charged to the same voltage as capacitor C driver . If switch S 5  were connected directly to V driver , boot capacitor C boot  would only be recharged to a voltage below that of C driver  (below voltage V driver ) and switch S 4  would need to be larger with a larger voltage drop, to carry both the current out of V driver  and the current out of V boot . Thus, the present invention permits the use of smaller switches for S 4  and S 5 , resulting in a semiconductor real estate savings of up to 50% for the aggregate physical surface area for S 4  and S 5 . Preferably, switch S 5  is a PMOS device with a resistance sufficiently low to drop less than 300 mV across the device. Switch S 4  may be an NMOS device, further reducing the physical surface area by approximately 50% for switch S 4 . Capacitor C boot  may be {fraction (1/10)} the size of capacitor C driver : capacitor C boot  may be 1 μF and capacitor C driver  may be 10 μF, for example. Capacitor C pump  may be smaller than capacitor C driver  and may be 1 μF, for example. 
     FIG. 4 is a timing diagram of the circuit in FIG. 3 showing how V driver  and V boot  of circuit  20  are recharged in accordance with the first embodiment of the present invention, with the x-axis representing time. Switches S 1  (signal  30 ) and S 3  (signal  34 ) are closed. Capacitor C pump  has been charged up to approximately V in , so that node A (signal  40 ) begins at voltage V in . At time “a,” switches S 1  and S 3  are opened (signals  30  and  34 , respectively). The voltage at node A is now indeterminate because all switches S 1 , S 4 , and S 5  tied to it are open, as are the switches S 1 , S 2 , S 3 , S 4 , and S 5  connected to capacitor C pump . The voltage at node A is indeterminate between times “a” to “c” and between times “f” and “h.” 
     At time “b,” the phase node  24  drops, bringing down voltage V boot  with it (signal  44 ), via capacitor C boot  to a voltage less than V driver . At time “c,” switches S 4  and S 5  close (signals  36  and  38 , respectively), connecting capacitor C pump , and the nodes at voltages V driver  and V boot  together. There may be some current flow between nodes V driver  and V boot , which is undesired, so the system quickly progresses to time “d.” At time “d,” switch S 2  is closed (signal  32 ) which raises the voltage on the lower and also upper plates of capacitor C pump . at nodes B and D, respectively. Charge flows from capacitor C pump  through switches S 4  and S 5  in parallel, recharging both V driver  and V boot  (signals  42  and  44 , respectively). Voltage V boot  asymptotically approaches voltage V driver  (signal  44 ). At time “e,” switches S 4  and S 5  are opened (signals  36  and  38 , respectively), and at time “f,” switch S 2  is opened (signal  32 ). At time “g,” the phase node  24  rises, bringing up voltage V boot  with it (signal  44 ). At time “h,” switches S 1  and S 3  are closed (signals  30  and  34 , respectively), recharging capacitor C boot  from V in . 
     Preferably, V boot  is charged to an amount equal to V driver . However, it is possible for V boot  to be charged to an amount higher or lower than V driver , for example V driver +/−200 mV in accordance with the present invention. The voltage of the boot capacitor C boot  is approximately equal to: 
     
       
           V   boot   =V   driver   −V   S5   +V   S4 .  Equation 1  
       
     
     when V S5 =V S4 , V boot =V driver . If there is a difference between the switch voltages V S5  and V S4 , then V boot  will be slightly higher or lower than V driver . For example, if V driver  is 5.2 V, voltage V S4  is 100 mV, and voltage V S5  is 300 mV, V boot  equals approximately 5.0 V. Similarly, if V driver  is 5 V, voltage V S5  is 100 mV and voltage V S4  is 300 mV, V boot  equals approximately 5.2 V. Preferably, voltages V driver  and V boot  are 5 V+/−200 mV. 
     A second embodiment of the present invention is shown in the circuit of FIG.  5 . Diode D 1  of the prior art is replaced with a switch S 5 , which switch is a synchronous rectifier or MOS transistor. The gate drive for S 5  is arranged such that switch S 5  is turned on when the source of S 5  is low. Preferably, a relatively small PMOS transistor is used for switch S 5 , for example, having a voltage drop of 200 mV or less. Switch S 5  has a lower voltage drop than the diode D 1  of the prior art having a voltage drop of 400 mV or higher, and therefore the boot capacitor C boot  can be recharged to a higher voltage closer to the voltage of V driver . For example, the PMOS transistor S 5  may have a voltage drop of 100 mV and the driver voltage V driver  may be approximately 5 volts, enabling the boot capacitor C boot  to be restored to a voltage of approximately 4.9 volts. 
     A timing diagram for the second embodiment is shown in FIG. 6, with the x-axis representing time. In normal operation, voltage V phase  displays a rectangular voltage waveform, switching between zero volts and V in  (signal  52 ). At time “a,” the gate of transistor S 5  is high; therefore, transistor S 5  is off. Voltage V phase  drops from V in  to 0 V. Voltage V boot , which is connected to V phase  by C boot , also drops by the same amount, approximately equal to (V in  less 0 V). The voltage on V boot  (signal  56 ) is now lower than the level of V driver , but the gate of S 5  remains tied to V boot , so transistor S 5  remains off. Note that whenever transistor S 5  is to be held in the “off” state, the gate of S 5  is tied to the V boot  node, and when S 5  is to be turned on, the gate of S 5  is tied to zero volts. 
     At time “b,” the gate of transistor S  5  is now pulled to 0 V (signal  54 ), turning S 5  on. The C boot  capacitor charges up, with its lower plate at V phase  at ground. The upper plate of capacitor C boot , at V boot , is connected to V driver  via transistor S 5 . Capacitor C boot  charges up, asymptotically approaching V driver  (signal  56 ). At time “c,” the gate of transistor S 5  is pulled high again (signal  54 ), turning off S 5  and stopping the charging of capacitor C boot . At time “d,” the voltage at V phase  rises again from 0 V to Vin (signal  52 ). V boot  (signal  56 ) rises from just below V driver  to just below (V driver +V in ). V boot  does not rise by an amount equal to V in  due to charge lost from V boot  to power the gate driver X 1 . Consequently, when the cycle repeats at time “a” again, V boot  ends up lower than V driver . 
     There are many advantages of the solution provided by the present invention, where the charge of capacitor C boot  is either restored by switch S 5  alone or by S 5  and S 4  in parallel. First, excellent semiconductor area efficiency for a given voltage drop is achieved. The present invention allows lower supply voltages to be used than in the prior art. External high side FETs driven by the circuit (not shown, at V out ) are driven harder, resulting in a more efficient switch mode power converter. The voltage at V boot  can be charged to a voltage very close to V driver  in accordance with the present invention. This is desired because FETs MN 1  and MN 2  are typically of similar types, requiring similar gate drives to turn on. If V boot  is charged to the same voltage as V driver , both MN 1  and MN 2  will see identical amounts of gate drive when turned on. Furthermore, fewer external components are required than when using the external diode D 1  of the prior art. Using a transistor S 5  in place of diode D 1  as in the second embodiment is possible to implement with or without a charge pump. 
     While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. The charge pump circuit of the present invention may be utilized with a power converter in a wide variety of applications, such as digital signal processors, microprocessors, mixed signal analog circuits, telecommunications applications, mobile devices and systems, laptops and personal computers, and any lower power electrical application, in general.