Abstract:
In a receiver for synchronously demodulating real bandpass signals and including circuit elements connected for removing noise, equalizing the signals, converting the resulting signals to analytical signals, shifting the signals in phase, sampling the signals at the signal element timing rhythm, and interrogating the sampled signals, there is provided a single pair of filters serving to perform both the equalizing and converting functions.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a receiver for the synchronous demodulation of real bandpass signals which have been freed from interference or distortion, respectively, by means of filters. After such filtering, the signals are converted by means of a pair of Hilbert filters into analytical signals which are shifted in phase by means of a phase shifting member, are scanned at the rate of the signal element timing rhythm, and are interrogated in a decider. 
     Such receivers are disclosed, for example, in the article entitled, &#34;A High Performance Digital QAM 9600 bit/sec Modem&#34; by Akashi et al., published in NEC Research &amp; Development No. 45, April 1977, at pages 38, et seq.; the article entitled, &#34;Microprocessor Implementation of High-Speed Data Modems&#34; by Gerwen et al., published in IEEE Trans. on Communications, Vol. COM-25, No. 2, February, 1977, pages 238 et seq.; and the article entitled &#34;Ein flexibles Experimentiersystem fur die Datenubertragung im Fernsprechbereich&#34; [A Flexible Experimental System for Data Transmission in the Telephone Art] by Kammeyer and Schenk, published in Frequenz (Frequency] 33, 1979, No. 5, pages 141-145 and No. 6, pages 165-172. 
     Data receivers, such as those mentioned above, usually employ quadrature amplitude modulation and mainly employ time sampling or digital signal processing. 
     In all data receivers of this type, the individual functions are realized in separate filter arrangements, for example, the synchronous demodulation with phase separation is performed in a digital pair of Hilbert filters, the optimum noise suppression in a matched filter, and the signal equalization in a special equalizer filter. With fast operating data transmission instruments, the above-mentioned other filters are necessary in addition to the pair of Hilbert filters to achieve a low bit error rate, so that the circuitry becomes relatively complicated. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to significantly reduce the circuitry required in a receiver of the above-mentioned type. 
     The above and other objects are achieved, according to the invention, in a receiver for synchronously demodulating real bandpass signals and including means connected for removing noise, means connected for equalizing the signals, means connected for converting the resulting signals to analytical signals, phase shifting means connected for shifting the signals in phase, sampling means connected for sampling the signals at the signal element timing rhythm, and a decider connected for interrogating the sampled signals, by the provision of a single pair of filters constituting both the equalizing means and the converting means. 
     The receiver according to the invention makes it possible to reduce the total circuitry required to perform the filter functions. With time-discrete or digital implementation of the filter functions, there exists the particular advantage that all filter component groups are able to operate at the low signal element timing rhythm and do not require the high scanning timing rhythm for multiplication. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a block circuit diagram of a prior art receiver. 
     FIG. 2 is a similar diagram of a preferred embodiment of a receiver according to the present invention. 
     FIG. 3a shows a general transversal filter as a tapped delay line. 
     FIG. 3b is a diagram of a transversal filter exploiting the fact that the sampling frequency required at the output is reduced with respect to its input, thus leading to a reduction of the multiplication rate. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a block circuit diagram for a prior art QAM receiver wherein the input signal received from an associated channel, and generally containing noise and being linearly distorted, is sampled at a sampling frequency which satisfies the scanning theorem, by operation of an element represented schematically as a switch. The sampled signal is fed to a matched filter MF for limiting the noise or for optimum noise suppression, respectively. Thereafter, the signal is equalized in an equalizing filter EZ and is fed to a pair of Hilbert filters F 1  and F 2 , where a complex signal is derived from the common real input signal. This complex signal has spectral components only at positive frequencies, i.e., is an analytical signal. 
     The desired complex data signal is obtained precisely when the phase curves of the two filters F 1  and F 2  in the frequency range of interest differ by π/2 and the attenuation curve exhibits an allpass characteristic. Thereafter, a phase shift takes place in a phase shifting member Ph by the value 2·k·(T/1)·f, where (T/1) is the sampling time with 1≠0 being an integer number, f is the carrier frequency, T the length of the signal element timing period and k the number of sampling values, or steps. 
     After the phase shift, sampling takes place at the signal element timing rhythm i·T and interrogation in a decider Es whose output provides the demodulated data pairs. T is the time between the arrival of any two subsequent signal elements to be received. The integer number l indicates--for time discrete or digital signal processing--the factor by which the sampling time interval at the receiver front end is reduced relative to the signal element sampling time interval. The integer figure k is related to the sampling instants at the receiver front end; the integer figure i relates to the sampling instants of the signal elements. 
     FIG. 2 shows an embodiment of the invention in which the filter functions of MF, EZ, F 1  and F 2  of FIG. 1 are combined in a single pair of filters F 1  &#39; and F 2  &#39;. The sampling in the signal element timing rhythm here occurs before the phase shift in shifter Ph and has been included in the filter block. The advantage of this arrangement is that the entire quadrature filter block can operate at the signal element timing rhythm T, resulting in a low multiplication rate while the two filters MF and EZ according to FIG. 1 must operate at the higher scanning and multiplication rate (l/T). 
     The arrangement according to the invention results in a further advantage that with different distortions which depend, for example, on the selected connection, the transfer function of the filter pair can simply be switched so that optimum data reception is made possible. 
     For the embodiment of the filters F 1  and F 2  there are various possibilities. First, in contrast to the example of FIG. 1, an analog implementation is given by S. D. Bedrosian, IRE Trans. Circ. theory, vol. 7, pp. 128-136, 1960 entitled &#34;Normalized Design of 90° Phase Difference Networks.&#34; There, a pair of allpass filters, implemented with coils and capactors, is used to perform a 90° phase difference at the output ports of the two filters. This approach does not require any timing and control circuitry. 
     With time-discrete or digital implementations, transversal filters may, for instance, be applied (FIG. 3a). Such a filter consists of a tapped delay line, where the frequency response of such a filter is determined by the weighting (tap) coefficients a o , a 1 , a 2 , . . . a L . A time-discrete embodiment of a transversal filter F 1  or F 2 , respectively, using charge couled devices (CCD) is for instance, given by Puckette et al. IEEE Trans Comm., vol. COM-22, pp. 926-934, July 1974 and by Ibrahim et al, IEEE J Solid State Circ., vol. SC-14, pp. 80-84, February 1979. Corresponding digital embodiments including timing and control circuitry can, for example, be found in U.S. Pat. No. 4,062,060 (December 1977) or in L. Schirm &#34;Multiplier-Accumulator Application Notes&#34;  TRW LSI Products, El Segundo, CA. 90245, January 1980. 
     The filters F 1  &#39; and F 2  &#39;, respectively, according to the invention can be embodied in the same way as the filters F 1  and F 2 . However, the values of the coefficients are different. If, for example, transversal filters according to FIG. 3a are used in the receiver according to FIG. 2, the multiplication rate can substantially be reduced, if the subsampling switch at the filter output is drawn into the filter according to FIG. 3b. Thus, this switch is replaced by a bank o synchronously driven switches in front of the multipliers so that fewer multiplications per second must be carried out. Detailed description of all other blocks of FIGS. 1 and 2, particularly of the phase rotating circuit Ph and the decision device Es, can be found in &#34;Data Transmission&#34; by W. R. Bennett and J. R. Davey, McGraw Hill Book Co., New York, 1965. Especially, a great variety of signals which can be processed with the receiver according to the invention are dealt with in this book. 
     It is to be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations, and the same are intended to be comprehended within the meaing and range of equivalents of the appended claims.