Abstract:
A differential two-or-more stage oscillator with precision phase tuning is presented. The phase difference between the stages can be varied by differentially adjusting the propagation delays of each stage. In addition, an injection-locked differential two-or-more stage oscillator with precision phase tuning is presented. The phase relationship between the stages can be altered without altering the frequency of the oscillator by differentially altering input bias voltages coupled to each stage. Additionally, a mechanism for the realization of a self-calibrating image-reject mixer architecture within a radio transceiver utilizing the new oscillator circuits is introduced. The mechanism provides a practical means for allowing a portable wireless device, for example, a cellular telephone, to calibrate its internal receive and transmit image-reject-mixer&#39;s phase and amplitude errors without the use of an externally applied test signal.

Description:
DESCRIPTION OF THE FIGURES  
         [0001]    [0001]FIG. 1 is a block diagram of a differential 2 stage ring oscillator with variable quadrature output phases according to the present invention.  
           [0002]    [0002]FIG. 2 is a schematic of the circuit of FIG. 1.  
           [0003]    [0003]FIG. 3 is a schematic of a differential regenerative frequency divider according to the present invention.  
           [0004]    [0004]FIG. 4 is a block diagram of an image reject mixer.  
           [0005]    [0005]FIG. 5 is a block diagram of an improved image reject mixer according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0006]    [0006]FIG. 1 shows a differential 2 stage ring oscillator  20  with quadrature output phases. Oscillator  20  includes a ring oscillator  21  and two current sources  28 ,  30 . Ring oscillator  21  includes a pair of differential amplifiers  22  and  24  which are connected together as a ring oscillator. The propagation delay τ A  of amplifier  22  is controlled by varying the current of controllable current source  28  and the propagation delay τ B  of amplifier  24  is controlled by varying the current of controllable current source  30 . The oscillation frequency of ring oscillator  21  is inversely related to the total propagation delay (τ A +τ B ) of amplifiers  22  and  24 . Signal V 1  is measured across nodes V 1+  and V 1− . Signal V 2  is measured across nodes V 2+  and V 2− . If the propagation delays, τ A  and τ B , of amplifiers  22  and  24  are equal, then signal V 2  will lag 90° behind signal V 1  (i.e. signals V 1  and V 2  will be quadrature signals). Propagation delay τ A  of amplifier  22  can be changed by adjusting the current of current source  28 . Similarly, propagation delay τ B  of amplifier  24  can be changed by adjusting the current of current source  30 .  
         [0007]    The frequency of ring oscillator  21  may be varied, without affecting the phase difference between signals V 1  and V 2 , by adjusting the currents of current sources  28  and  30  proportionally.  
         [0008]    The phase difference between signals V 1  and V 2  may be varied by differentially adjusting the propagation delays, τ A  and τ B , of amplifiers  22  and  24 . This is done by differentially adjusting the currents of current sources  28  and  30 .  
         [0009]    [0009]FIG. 2 is a schematic diagram of circuit  10 . Amplifier  22  comprises a pair of emitter coupled amplifiers Q 1  and Q 2 . Amplifier  24  comprises a pair of emitter coupled transistors Q 3  and Q 4 . The collectors and bases of transistors Q 1 - Q 4  are connected to form differential ring  21 . The collectors of Q 1  and Q 2  are coupled to a voltage source V cc1  through resistors R 1  and R 2 . The collectors of Q 3  and Q 4  are coupled to voltage source V cc2  through resistors R 3  and R 4 .  
         [0010]    Current source  28  comprises a transistor Q 5 . The base of transistor Q 5  is coupled to at input voltage V bias1 , which controls the current of current source  28 . Similarly, current source  30  comprises a transistor Q 6 . The current of current source  30  is controlled by voltage signal V bias2 . Voltage signals V bias1  and V bias2  must have a  
         [0011]    As the level of voltage signal V bias1  is increased, the current of current source  28  will increase. This will increase the switching speed and decrease the propagation delay of differential amplifier  22 . Similarly, the switching speed and propagation delay of differential amplifier  24  are controlled by varying the level of voltage signal V bias2 .  
         [0012]    Although the propagation delays of amplifiers  22  and  24  are described here as being controlled by varying the bias currents of the amplifiers (i.e. the currents of current sources  28  and  30 ), the same results may be attained by creating any imbalance in the electrical symmetry between amplifiers  22  and  24 . For example: a bias voltage or current may be altered at any node of ring oscillator  21 . Alternatively, a controllable capacitor, inductor or resistor may be coupled to any node to differentially alter the internal impedances in amplifiers  22  and  24 .  
         [0013]    Ring oscillator  21  may also be implemented as a pair of quadrature coupled differential oscillators.  
         [0014]    [0014]FIG. 3 shows a differential regenerative (i.e. dynamic) divider  50  with quadrature output. This circuit is identical to circuit  20 , except that the bases of transistors Q 5  and Q 6  are additionally coupled to an input signal V in  at nodes  52  and  54  through coupling capacitors C c1  and C c2 .  
         [0015]    Signal V in  is received at nodes  52 ,  54  and has a frequency f in . Transistors Q 5  and Q 6  convert input signal V in  into an alternating current signal i in  which is injected into emitter coupled nodes  56  and  58  of amplifiers  22  and  24 . The frequency of current signal i in  is the same as the frequency f in  of input signal V in . This injection locks ring oscillator  21  such that the oscillation frequency f osc  of the ring oscillator is half the input frequency f in  of input signal V in .  
         [0016]    If the propagation delays τ A  and τ B  of amplifiers  22  and  24  are configured to be the same, then signals V 1  and V 2  will be quadrature phased signals (i.e. they will be separated in phase by 90°).  
         [0017]    The phase relationship between V 1  and V 2  can be altered, without altering the frequency of ring oscillator  21  by differentially altering input voltages V bias1  and V bias2 . Since ring oscillator  21  is injection locked to frequency f in /2, it is only necessary to vary one of the input voltages V bias1  or V bias2 , with respect to the other, to vary the phase relationship between V 1  and V 2 .  
         [0018]    In radio system architectures, image reject mixing requires accurate quadrature local oscillator signal generators to attain high image rejection performance. This is required for both up (transmitter) and down (receiver) conversions. Known designs attempt to design the quadrature signal generator (frequency divider) to produce as accurately as possible a pair of signals (generally referred to as the inphase (I) and quadrature (Q) signals) which are separated by precisely 90°. It is impossible to account for all process tolerances which can impair the image rejection performance of an image reject architecture. Approximately 1° of phase error is common. This translates to a maximum image rejection of about 46 dB. Including other sources of phase and amplitude error in the quadrature down conversion path a typical specification for image rejection is approximately 35 dB. In order to improve image rejection beyond this level, a system is required for controlling the phase relation between the I and Q local oscillator signals with a high degree of precision. This system may be used to provide I and Q signals which have a phase relation which compensates for the other sources of phase error. In a particular case, the phase relation between the I and Q signals may be greater or less than 90°.  
         [0019]    [0019]FIG. 4 is a block diagram of an image reject mixer  100  using the Hartley topology. Signal RF in  comprises a RF signal having a frequency f RF  and an image signal having a frequency f IM . Signal generator  101  provides a pair of local oscillator signals V 1  (which takes the place of the I signal) and V 2  (which takes the place of the Q signal), both having the same frequency f LO . Signals V 1  and V 2  have phase angles φ V1  and φ V2 . φ V1  is arbitrarily chosen as a reference for 0° phase. Signals V 1  and V 2  are mixed with the received signal RF in  in mixers  102  and  104  to provide a pair of signals IF 1  and IF 2 . When high side injection is used (f LO  is greater than f RF ), the IF 1  signal comprises the RF signal converted to frequency (f LO −f RF ) and the image signal (sideband) converted to frequency (f IM −f LO ). Signal IF 2  comprises the RF signal converted to frequency (f LO −f RF ) and shifted in phase by φ V2 ° and the image signal converted to frequency (f IM −f LO ) and shifted in phase by −φ V2 °.  
         [0020]    The amplified signals IF 1  and IF 2  are combined by a quadrature combiner  110 . Quadrature combiner  110  is designed to complete the image rejection by providing a phase shift φ QC1  to signal IF 1  and a phase shift φ QC2  to signal IF 2 . Ideally, to maximize suppression of the image signal, φ QC1 −φ V1 =0° and φ QC2 +φ V2 =−180° (assuming high side injection). Ideally, φ V2 −φ V1 =90°, φ QC2 −φ QC1 =90°. In known quadrature combiners, φ QC2 −φ QC1  is generally not 90°. Typically a phase error exists, and the image is not maximally suppressed. In addition, known quadrature combiners also introduce amplitude errors in the IF 1  and/or IF 2  signal paths. For example, both signal IF 1  may be reduced in amplitude by N dB.  
         [0021]    Current state of the art systems attempt to maintain the 90° phase separations between φ V1  and φ v2  and between φ QC1  and φ QC2 . It has been found that image rejection performance can be substantially increased by adjusting the phase difference to compensate for the phase error in the quadrature combiner  110 . In addition, amplitude errors in the IF 1  and IF 2  signal paths can be compensated for.  
         [0022]    [0022]FIG. 5 shows an improved image reject mixer  200 . Components of image reject mixer  200  which correspond to components of image reject  100  are identified by the same reference numerals. Signal generator  101  of image reject mixer has been replaced with circuit  50  (FIG. 3). Nodes  52  and  54  of circuit  50  are coupled to a signal generator  202 .  
         [0023]    Output signal IF out  is received by a carrier level detector  203 . Carrier level detector provides a signal to feedback controller  204 . Feedback controller provides control signals to switches SW 1  and SW 2 , calibration signal transmitter  206 , signal generator  202 , amplifiers  210 ,  212  and provides voltage signal V bias1  and V bias2 . Image reject mixer has a calibration mode and operation mode.  
         [0024]    Initially, in the calibration mode the following configuration is set by controller  204 :  
         [0025]    (a) switches SW 1  and SW 2  are configured to connect calibration signal transmitter  206  to input node RF in ;  
         [0026]    (b) signal generator  202  is configured to produce a signal with a frequency twice that required for the local oscillator signals V 1  and V 2 ; and  
         [0027]    (c) voltage signals V bias1  and V bias2  are configured to initiate the operation of circuit  50  with the phase delays of amplifiers  22  and  24  being approximately equal; and  
         [0028]    (d) calibration signal transmitter  206  is configured to generate a signal at the frequency of the image;  
         [0029]    (e) the gains of amplifiers  210  and  212  are set equal.  
         [0030]    Controller  204  then runs a calibration algorithm. Signal IF out  is generated as in image reject mixer  100 . Signal IF out  will contain the image signal generated by calibration signal generator  206 . The level of signal IF out  will correspond to phase and amplitude errors introduced in quadrature combiner  110  and other components of image reject mixer  200 . Carrier level detector provides a signal corresponding to the level of signal IF out  to controller  204 .  
         [0031]    Controller  204  then adjusts the relative propagation delays of amplifier  22  and  24  (within circuit  50 ) to control the relative phase difference between V 1  and V 2  to reduce the signal level of IF out  as much as possible. Controller  204  than adjusts the relative gains of amplifiers  210  and  212  to reduce the signal level of IF out  as much as possible. Controller  204  then alternately attempts to reduce the signal level of IF out  by adjusting the phase difference between V 1  and V 2  and by adjusting the relative gains of amplifiers  210  and  212 . When no further reduction of IF out  is attained for several iterations, the calibration mode is terminated by configuring switches SW 1  and SW 2  to disconnect the calibration signal transmitter  206  from node RF in  and to connect the antenna to node RF in .  
         [0032]    Image reject mixer  200  then enters the operation mode. The setting for the phase difference between V 1  and V 2  and the relative gains of amplifiers  210  and  212  determined during the calibration mode are retained during the operation mode to maintain the improved image reject performance of image reject mixer  200  attained during calibration mode.  
         [0033]    Image reject mixer  200  may be integrated. The functionality of the elements of image reject mixer  200  contained within dashed boundary  216  may wholly or partially implemented using analog or digital technology.  
         [0034]    In addition, image reject mixer  200  may be used with a transmitter. 
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
 
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