Abstract:
An exemplary packet processing apparatus where a large number of comparisons can be made concurrently in bit-parallel fashion by partitioning the comparison functionality to two optoelectronic integrated circuits, and interconnecting the two circuits using free space optics. Illustratively, different embodiments are used to perform one-to-many or many-to-one comparisons by developing multiple copies of one value for concurrent comparison with many possible values. The invention is more generally applicable to other comparison applications where one-to-many or many-to-one comparisons are made.

Description:
TECHNICAL FIELD 
     This invention relates to communication and computing technology, specifically including packet processing apparatus. 
     BACKGROUND AND PROBLEM 
     The term broadband covers a host of new products, technologies, services, and networks. One way to define broadband networks is to categorize them as those networks that support services requiring bit rates well above one megabits per second. Business and residential subscribers will be connected to broadband networks via a common access, operating at 150 megabits per second or above, that can handle a range of different broadband service types. ATM (asynchronous transfer mode) has been chosen as the communication principle on which broadband networks will be based. A future broadband ISDN (integrated services digital network) will offer the flexibility needed to handle diverse services ranging from basic telephone service to high speed data transfer, videotelephony, and high quality television distribution. The key to this flexibility is ATM which carries digital information in special cells. This allows the network to be used efficiently by applications and services with widely differing bandwidth requirements and call characteristics. 
     ATM cells have a five-byte header and a 48-byte payload. The header includes the routing information for the packet. It is important to compare this routing information to many possible values very rapidly. For example, if the bit rate is 155 megabits per second, an eight-byte header corresponds to approximately 0.25 microseconds. It is desirable to make the routing decision in this very short time period. What is needed is an apparatus capable of making very fast comparisons. 
     SOLUTION 
     This need is met and a technical advance is achieved in accordance with the principles of the invention in an exemplary packet processing apparatus where a large number of comparisons can be made concurrently in bit-parallel fashion by partitioning the comparison functionality to two optoelectronic integrated circuits, and interconnecting the two circuits using free space optics. Illustratively, different embodiments are used to perform one-to-many or many-to-one comparisons by developing multiple copies of one value for concurrent comparison with many possible values. The invention is more generally applicable to other comparison applications where one-to-many or many-to-one comparison are made 
     The packet processing apparatus in accordance with the invention includes first and second optoelectronic integrated circuits. The first circuit includes first storing means for storing information and transmits an array of optical beams representing the information stored by the first storing means. Free space optical apparatus is used for imaging the beam array onto the second circuit. The second circuit includes second storing means for storing information and comparison circuitry for comparing the information represented by the beam array, with the information stored by the second storing means. A header of an input packet is transmitted to one of the first and second storing means. The other storing means stores at least one possible value. The second circuit generates a signal in response to a predefined comparison by the comparison circuitry. 
     In a first embodiment, the one storing means is the first storing means and the transmitted array represents multiple copies of the stored header. The second storing means stores many possible values. The comparison circuitry concurrently compares each of the multiple copies with a different one of the many possible values. 
     In a second embodiment, the other storing means is the first storing means and it stores many possible values. The transmitted array represents the many possible values. The second storing means stores multiple copies of the stored header. The comparison circuit concurrently compares each of the multiple copies with a different one of the many possible values. 
     In a third embodiment, a plurality of input packets are received by the first circuit, the one storing means is the first storing means and the transmitted array represents headers from the plurality of input packets. The second storing means stores multiple copies of only one possible value. The comparison circuit concurrently compares each of the multiple copies with a header from a different one of the plurality of input packets. 
     In a fourth embodiment, only one possible value is received by the first circuit, the other storing means is the first storing means and the transmitted array represents multiple copies of the one possible value. A plurality of input packets are received by the second circuit. The comparison circuit concurrently compares each of the multiple copies with a header from a different one of the plurality of input packets. 
     The first and second embodiments may be used to process packets prior to their transmission into a self-routing packet network. Information associated with each possible value is stored which defines a specific path through the self-routing packet network. This information becomes the comparison signal upon a positive comparison and is combined with other information from the input packet for transmission as an output packet into the packet network. The third and fourth embodiments may be used in a packet node, to separate packets destined for the node from packets destined for other nodes. 
     Multiple quantum well devices, specifically FET-SEED devices, are used in the first optoelectronic integrated circuit to transmit the array of optical beams. The beams are received by FET-SEED devices in the second optoelectronic integrated circuit. 
     Packets may be received either as serial, electrical signals or as optical signals, in either serial or parallel format. 
     The apparatus of the invention may be applied more generally for one-to-many and many-to-one comparisons of bit strings where multiple copies of one value are developed to reduce the time to make the comparisons. In addition to equality, the predefined comparison may be &lt;, &gt;, &lt;=, &gt;=, not equal, or any other comparison of some or all of the bits. 
    
    
     DRAWING 
     FIG. 1 is a functional diagram of a first embodiment in accordance with the invention; 
     FIG. 2 is a circuit diagram of a first optoelectronic circuit in the embodiment of FIG. 1; 
     FIG. 3 is a circuit diagram of a second optoelectric circuit in the embodiment of FIG. 1; 
     FIG. 4 is a functional diagram of a second embodiment in accordance with the invention; 
     FIG. 5 is a circuit diagram of a first optoelectronic circuit in the embodiment of FIG. 4; 
     FIG. 6 is a circuit diagram of a second optoelectronic circuit in the embodiment of FIG. 4; 
     FIG. 7 is a functional diagram of a third embodiment in accordance with the invention; 
     FIG. 8 is a circuit diagram of a first optoelectronic circuit in the embodiment of FIG. 7; 
     FIG. 9 is a circuit diagram of a second optoelectronic circuit in the embodiment of FIG. 7; 
     FIG. 10 is a functional diagram of a fourth embodiment in accordance with the invention; 
     FIG. 11 is a circuit diagram of a first optoelectronic circuit in the embodiment of FIG. 10; 
     FIG. 12 is a circuit diagram of a second optoelectronic circuit in the embodiment of FIG. 10; 
     FIG. 13 is an alternative embodiment of the first optoelectronic integrated circuit of FIG. 2; and 
     FIG. 14 is an alternative embodiment of the first optoelectronic integrated circuit of FIG. 11. 
    
    
     DETAILED DESCRIPTION 
     First Embodiment 
     FIG. 1 is a diagram of a first embodiment comprising packet processing apparatus 10. An input packet including an N-bit header is received by a first optoelectronic integrated circuit 20 (FIG. 2) as a serial, electrical signal on line 11. Circuit 20 includes a fanout 21 which distributes the input packet to M, N-bit serial/parallel shift registers 23-1 through 23-M. When the N bits of the M copies of the packet header have been stored, they are transmitted as an array of optical beams by an array of modulators 24-11, 24-1N, 24-M1, 24-MN and are imaged via the free-space optical apparatus of FIG. 1 in a 1:1 fashion onto a second optoelectronic integrated circuit 40. The input packet from register 23-1 is delayed by N or more bits by a delay element 28 and transmitted as a serial, electrical signal via line 12 to an output packet transmitter 50. 
     A controller 90 writes M unique, possible N-bit header values into M, N-bit serial/parallel shift registers 43-1 through 43-M (FIG. 3.) Controller 90 also writes information associated with each of the M possible values into M, P-bit serial/parallel shift registers 47-1 through 47-M, each having tri-state outputs. The associated information is, for example, a self-routing header, used to route a packet through a self-routing packet network (not shown). Controller 90 writes an N-bit possible value and a corresponding P-bit self-routing header into circuit 40 as part of the process of establishing a virtual circuit. The M copies of the input packet header, represented by the array of optical beams from circuit 20, are received by an array of demodulators 44-11, 44-1N, 44-M1, 44-MN. The demodulators transmit corresponding electrical signals to an array of exclusive NOR-gates 45-11, 45-1N, 45-M1, 45-MN, which also receive each bit stored in registers 43-1 through 43-M. The bit comparison results of one input packet header copy with one of the M possible values are combined by an associated one of M, AND-gates 46-1 through 46-M. When, for example, the possible value stored by register 43-1 is equal to the corresponding input packet header copy, AND-gate 46-1 enables the transmission of the associated self-routing header, referred to as a comparison signal, from register 47-1 to transmitter 50 (FIG. 1). Transmitter 50 combines the input packet received on line 12 with the self-routing header and transmits the resulting output packet as a serial, electrical signal on line 16 to the packet network. There would typically be a plurality of packet processors such as apparatus 10 on the input side of the packet network. 
     FIG. 13 is a diagram of an alternative first optoelectronic integrated circuit 1020 which would replace circuit 20 in apparatus 10 (FIG. 1). In circuit 1020 (FIG. 13), the input packet is received by a single N-bit serial/parallel shift register 1023. Each bit in register 1023 is transmitted to a corresponding column of modulators, e.g., 1024-11 through 1024-M1 or 1024-1N through 1024-MN. The MN modulators collectively transmit the array of optical beams representing M copies of the input packet header. The packet from register 1023 is delayed by at least N bits by a delay element 1028 and transmitted as a serial, electrical signal on line 12. 
     Second Embodiment 
     FIG. 4 is a diagram of a second embodiment comprising packet processing apparatus 110. A controller 190 writes M unique, possible N-bit header values into M, N-bit serial/parallel shift registers 123-1 through 123-M (FIG. 5). When the M header values have been stored, they are transmitted as an array of optical beams by an array of modulators 124-11, 124-1N, 124-M1, 124-MN and are imaged via the free-space optical apparatus of FIG. 4 in a 1:1 fashion onto a second optoelectronic integrated circuit 140. 
     An input packet including an N-bit header is received by circuit 140 (FIG. 6) as a serial, electrical signal on line 111. Circuit 140 includes a fanout 189 which distributes the input packet to M, N-bit serial/parallel shift registers 143-1 through 143-M. The input packet from register 143-1 is delayed by N or more bits by a delay element 190 and transmitted as a serial, electrical signal via line 192 to an output packet transmitter 150 (FIG. 4). Controller 190 writes information associated each of the M possible values into M, P-bit serial/parallel shift register 147-1 through 147-M (FIG. 6), each having tri-state outputs. The associated information is, for example, a self-routing header, used to route a packet through a self-routing packet network (not shown). Controller 190 writes an N-bit possible value into circuit 120 and a corresponding P-bit self-routing header into circuit 140 as part of the process of establishing a virtual circuit. The M possible values represented by the array of optical beams from circuit 120, are received by an array of demodulators 144-11, 144-1N, 144-M1, 144-MN. The demodulators transmit corresponding electrical signals to an array of exclusive NOR-gates 145-11, 145-1N, 145-M1, 145-MN, which also receive each bit stored in registers 143-1 through 143-M. The bit comparison results of each input packet header copy with one of the M possible values are combined by an associated one of M, AND-gates 146-1 through 146-M. When, for example, the input packet header copy stored by register 143-1 is equal to the corresponding possible value, AND-gate 146-1 enables the transmission of the associated self-routing header, referred to as a comparison signal, from register 147-1 to transmitter 150 (FIG. 4). Transmitter 150 combines the input packet received on line 192 with the self-routing header and transmits the resulting output packet as a serial, electrical signal on line 116 to the packet network. There would typically be a plurality of packet processors such as apparatus 110 on the input side of the packet network. 
     Third Embodiment 
     FIG. 7 is a diagram of a third embodiment comprising packet processing node 210. A plurality, M, of input packets including N-bit headers are received by a first optoelectronic integrated circuit 220 (FIG. 8) as a plurality of serial, electrical signals on lines 211-1 through 211-M. The M packets are received by M, N-bit serial/parallel shift registers 223-1 through 223-M. When the N bits of the M input packet headers have been stored, they are transmitted as an array of optical beams by an array of modulators 224-11, 224-1N, 224-M1, 224-MN and are imaged via the free-space optical apparatus of FIG. 7 in a 1:1 fashion onto a second optoelectronic integrated circuit 240. 
     A controller 290 transmits a single, possible N-bit header value via line to a fanout 279 (FIG. 9), which distributes M copies of the single possible value to M, N-bit serial/parallel shift registers 243-1 through 243-M. The M input packet headers, represented by the array of optical beams from circuit 220, are received by an array of demodulators 244-11, 244-1N, 244-M1, 244-MN. The demodulators transmit corresponding electrical signals to an array of exclusive NOR-gates 245-11, 245-1N, 245-M1, 245-MN, which also receive each bit stored in registers 243-1 through 243-M. The bit comparison results of one input packet header with one of the M possible value copies are combined by an associated one of M, AND-gates 246-1 through 246-M. When, for example, the possible value copy stored by register 243-1 is equal to the corresponding input packet header, AND-gate 246-1 transmits a logic one comparison signal on line 215-1. Similarly, when the possible value copy stored by register 243-M is equal to the corresponding input packet header, AND-gate 246-M transmits a logic one comparison signal on line 215-M. 
     The M input packets from registers 223-1 through 223-M (FIG. 8), are delayed, for a time sufficient for comparison signals to be returned from circuit 240, by a plurality of delay elements 280-1 through 280-M, and are transmitted as serial, electrical signals to a plurality of AND-gates 225-1 through 225-M, and to a plurality of AND-gates 226-1 through 226-M, each of the latter gates having one inverting input. When a logic one comparison is received on one of the lines 215-1 through 215-M, the associated one of the AND-gates 225-1 through 225-M transmits the input packet to a node circuit 260 which performs further packet processing for node 210. When a logic zero comparison signal is received on one of the lines 215-1 through 215-M, the associated one of the AND-gates 226-1 through 226-M transmits the input packet to one of a plurality of other packet processing nodes (not shown). 
     FIG. 14 is a diagram of an alternative first optoelectronic integrated circuit 1320 which would replace circuit 320 in apparatus 310 (FIG. 10). In circuit 1320 (FIG. 14), the single possible value is received by an N-bit serial/parallel shift register 1323. Each bit in register 1323 is transmitted to a corresponding column of modulators, e.g., 1324-11 through 1324-M1 or 1324-1N through 1324-MN. The MN modulators collectively transmit the array of optical beams representing M copies of the single possible value. 
     Fourth Embodiment 
     FIG. 10 is a diagram of a fourth embodiment comprising packet processing node 310. A controller 390 transmits a single, possible N-bit header value via line 313 to a fanout 321 (FIG. 11) of a first optoelectronic integrated circuit 320. Fanout 321 distributes M copies of the single possible value to M, N-bit serial/parallel shift registers 323-1 through 323-M. When the N bits of the M copies have been stored, they are transmitted as an array of optical beams by an array of modulators 324-11, 324-1N, 324-M1, 324-MN and are imaged via the free-space optical apparatus of FIG. 10 in a 1:1 fashion onto a second optoelectronic integrated circuit 340. 
     A plurality, M, of input packets including N-bit headers are received by circuit 340 (FIG. 12) as a plurality of serial, electrical signals on lines 311-1 through 311-M. The M packets are received by M, N-bit serial/parallel shift registers 343-1 through 343-M. The M copies of the single possible value, represented by the array of optical beams from circuit 320, are received by an array of demodulators 344-11, 344-1N, 344-M1, 344-MN. The demodulators transmit corresponding electrical signals to an array of exclusive NOR-gates 345-11, 345-1N, 345-M1, 345-MN, which also receive each bit stored in registers 343-1 through 343-M. The bit comparison results of one input packet header with one of the M possible value copies are combined by an associated one of M, AND-gates 346-1 through 346-M. When, for example, the input packet header stored by register 343-1 is equal to the corresponding possible value copy, AND-gate 346-1 transmits a logic one, internal comparison signal on line 347-1. Similarly, when the input packet header stored by register 343-M is equal to the corresponding possible value copy, AND-gate 346-M transmits a logic one, internal comparison signal on line 347-M. The M input packets from registers 343-1 through 343-M are delayed, for a time sufficient for internal comparison signals to be transmitted on lines 347-1 through 347-M, by a plurality of delay elements 370-1 through 370-M, and are transmitted as serial, electrical signals to a plurality of AND-gates 371-1 through 371-M, and to a plurality of AND-gates 372-1 through 372-M, each of the latter gates having one inverting input. When a logic one comparison is received on one of the lines 347-1 through 347-M, the associated one of the AND-gates 371-1 through 371-M transmits the input packet to a node circuit 360 which performs further packet processing for node 310. When a logic zero comparison signal is received on one of the lines 347-1 through 347-M, the associated one of the AND-gates 372-1 through 372-M transmits the input packet to one of a plurality of other packet processing nodes (not shown). 
     The invention is particularly advantageous for use in rapidly processing ATM cells which comprise five header bytes and 48 information bytes. 
     The free space optical configuration used in each of the embodiments is now described. In apparatus 10 (FIG. 1), for example, a collimated beam having a single linear polarization (s-polarization) is directed via lens 65 from a laser source 26 at a transmissive, two-dimensional spatially varying binary phase grating 64. Grating 24 divides the single beam into an array of individual, equal intensity beams as described in U.S. Pat. No. 5,113,286 issued to R. L. Morrison on May 12, 1992. Because the beams (not shown) transmitted from grating 64 have s-polarization, they are reflected from a diagonal surface of a polarization beam splitter 63 to a quarter-wave plate 62 which changes them to circular polarization. Because of the spatially varying phase delays introduced by grating 54, the beams are Fourier transformed by a compound lens 61 into individual spots on the surface of circuit 20. 
     Because circuit 20 is arranged to be placed at the focus of lens 61, the spots created are centered on individual modulators. The modulators have their reflectance state changed by the electric field applied from the associated electronic circuitry. The reflected beams (shown in FIG. 1) are transmitted via lens 61 to quarter-wave plate 62, where they are changed from circular polarization to p-polarization. The beams are transmitted through beam splitter 63 and are Fourier transformed by a compound lens 67 into an array of spots on circuit 40. The free-space optical apparatus of FIG. 1 performs 1:1 imaging. To perform 1:n imaging (n&gt;1), a binary phase grating (not shown) is added between beam splitter 63 and lens 67. Using 1:n imaging would reduce the number of modulators required in the first optoelectronic circuit. The mounting of the elements of apparatus 10 (FIG. 1) is effected in the manner described in &#34;A Six-Stage Digital Free-Space Optical Switching Network Using S-SEEDs&#34;, by F. B. McCormick, et al., Applied Optics: Information Processing, 1992and &#34;Optomechanics of a Free Space Photonic Switch: the Components&#34;, by J. L. Brubaker et al., Optomechanics and Dimensional Stability, Jul. 25-26, 1992, the details of which are unimportant to the present invention. Any suitable mounting arrangement, including an arrangement where the two optoelectronic circuits are mounted flat on a printed circuit board, may be used. The free-space optical apparatus shown in FIGS. 4, 7, and 10 is substantially the same as that shown in FIG. 1. 
     The modulators herein are multiple quantum well devices, specifically FET-SEED devices as described in &#34;Operation of a Fully Integrated GaAs-Al x  Gal x  As FET-SEED: A Basic Optically Addressed Integrated Circuit&#34;, T. K. Woodward et al., IEEE Photonics Technology Letters, Vol. 4, No. 6, June 1992, pp. 614-617. The demodulators are also FET-SEED devices. 
     The fanout devices shown in FIGS. 2, 6, 9 and 11 could alternatively be external to the optoelectronic integrated circuits. 
     The input packets could alternatively be received as optical signals, in either serial or parallel format. 
     The invention is also usable more generally in rapidly comparing input bit strings and reference bit strings in a one-to-many or many-to-one fashion. One example is detection of the presence of a particular word or phrase in some input text. The comparisons performed in the four embodiments described herein require equality of all bits. Other predefined comparisons could be &lt;, &gt;, ←, →, not equal, or any other comparison of all or any subset of bits. 
     It is to be understood that the above-described embodiments are merely illustrative of the principles of the invention and that many variations may be devised by those skilled in the art without departing from the spirit and scope of the invention. It is therefore intended that such variations be included within the scope of the claims.