Abstract:
A system and method for translating a non-logic-family signal level into a logic-family signal level, the system comprising: a source of a non-logic-family signal that can assume a first and a second non-logic-family state; and a translator for determining whether the signal is in the first non-logic-family state, and if so, providing a translated signal having a first-logic family level. The translator can take the form of a comparator controlling an output transistor tied to a pull-up resistor, or a programmed processor. Examples of the logic-families include transistor-transistor logic (TTL) and complimentary metal oxide semiconductor (CMOS) logic. Examples of sources of non-logic-family signals includes a light emitting diode, a buzzer and a beeping device.

Description:
FIELD OF THE INVENTION 
     The invention is directed toward an interface method and apparatus for digital logic, and more particularly a method and apparatus for interfacing a source of non-logic-family signal levels to a circuit that requires signals to conform to the specifications of a logic-family. 
     BACKGROUND OF THE INVENTION 
     In many technologies, e.g., telecommunications, diagnostic circuitry is employed. Often, such diagnostic circuitry only takes the form of a warning light, such as a light emitting diode (LED), and/or an auditory indicator, e.g., a buzzer or beeping device. In the event that a predetermined condition arises, the LED and/or buzzer is energized to provide a warning. 
     As the demands upon such technology and the environments in which they are used change, such diagnostic technology sometimes becomes insufficient. For example, a device might have originally been placed in a quiet and/or rather dimly lit environment. However, changing demands might place this device in a brightly lit and/or noisy environment where a blinking LED and/or faint buzzer might go unnoticed. 
     Alternatively, it might be desired to remotely gather data based upon the state of such an LED or buzzer for improved monitoring purposes. 
     SUMMARY OF THE INVENTION 
     It is an advantage of the invention to be able to translate a non-logic-family signal level into a logic-family-signal level, e.g., in order to augment the output of an indicator such as an LED or buzzer or to remotely collect data based upon the state of such an indicator. 
     These and other advantages of the invention are achieved by providing a system for translating a non-logic-family signal level into a logic-family signal level, the system comprising: a source of a non-logic-family signal that can assume a first and a second non-logic-family state; and a translator for determining whether said non-logic-family signal is in said first non-logic-family state, and if so, providing a translated signal having a first logic-family level. 
     These and other advantages of the invention are also achieved by providing a converter for converting a non-logic-family signal level to a logic-family signal level comprising: a comparator for comparing a level of a non-logic family signal with a reference value to determine whether said signal is in said first or said second non-logic-family state; an output transistor controlled by said comparator; and a pull-up resistor connected between an output terminal of said output transistor and a supply voltage set according to a logic-family high signal level. 
     These and other advantages of the invention are also achieved by providing a method of translating from a non-logic-family signal level into a logic-family signal level, the method comprising: comparing a level of a non-logic-family signal with a reference value to determine whether said signal is in a first or second non-logic-family state; and causing, when said first non-logic-family signal level is detected, an input to a logic-family device to take a first logic-family state. 
     The foregoing and other objectives of the present invention will become more apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein: 
     FIG. 1 is a block diagram of a first embodiment of the invention; and 
     FIG. 2 is a block diagram of a second embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a block diagram of a first, and preferred, embodiment of the invention. In FIG. 1, a source  10  of a non-logic-family signal W is connected to a translator  100  which translates the non-logic-family signal, W, into a logic-family signal, e.g., transistor-transistor-logic (TTL) such that the output of the translator  100  is W TTL . 
     The non-logic-family signal source  10  includes an alarm generator circuit  12  connected to an indicator  14 . The indicator  14  is connected to the translator  100  at a node  20 . Also, a resistor R 5  is connected between the node  20  and a source of voltage, V DD . The indicator  14  is depicted as a light emitting diode, LED  16 . Alternatively, the indicator can be a buzzer or beeping device (such as a piezo element). The signal on the node  20  is a warning signal, W. 
     The translator  100  includes an undervoltage sensing integrating circuit  102  that receives the warning signal W and outputs a translated signal, e.g., W TTL , at an output terminal  112 . The output terminal  112  is also connected to the source of voltage, V DD , via a resistor R 4 . The magnitude of the voltage V DD  is selected to be sufficient to establish a logical high signal level for the desired family of logic, e.g., five volts for TTL. 
     An example of the undervoltage sensing integrated circuit (IC)  102  is the MC33064 model of undervoltage sensing integrated circuit marketed by either Motorola Incorporated or Linfinity. The undervoltage sensing integrated circuit  102  includes a comparator  104 , the non-inverting input of which is connected to a voltage reference source  106  providing a reference voltage V ref . The voltage source  106  is connected to the relative system ground  18 . The inverting input of the comparator  104  is connected to the node  20  via resistor R 1  and to the relative system ground  18  via a resistor R 2 . The output of the comparator  104  is connected to the node  20  via a resistor R 3 . The node  20  is also connected to the cathode of a diode  110 , the anode of which is connected to the output terminal  112  of the IC  102 . The output terminal  112  also is connected to the collector of a bipolar junction transistor (BJT)  108 , the emitter of which is connected to the relative system ground  18 , and the base of which is connected to the output of the comparator  104 . 
     FIG. 2 is a block diagram depicting a second embodiment of the invention. FIG. 2 differs from FIG. 1 in that the translator  100  has been replaced by an alternative translator  200 . The translator  200  includes an analog to digital (A/D) converter  202  that is connected to the node  20  and so receives the indicator signal W. The digitized signal is provided to a processor  204 , which is bidirectionally connected to a memory  206 . The processor provides a digital representation of a logic-family signal level to a digital to analog (D/A) converter  208 . The D/A converter  208  provides the analog translated signal, e.g., W TTL . 
     The operation of the invention will now be explained in terms of the embodiments described above. 
     When the indicator  14  is implemented by the LED  16 , rather than a buzzer or beeping device, and when the LED  16  is not emitting (not activated) then a voltage on the node  20  is typically 5 volts. However, when the LED  16  is emitting light (activated), then the voltage on the node  20  can typically take a voltage in the range of 2 and 4 volts, but nominally is about 3 volts. Thus, an emitting (activated) LED has a logical low state characterized by a voltage between 2 and 4 volts while a non-emitting (inactive) logical high state of the LED is characterized by a voltage of 5 volts. These voltage levels are incompatible with the voltage levels for the standard logic families, which include TTL, emitter-couple logic (ECL), N-type oxide semiconductor (N-MOS) logic and complementary metal oxide semiconductor (C-MOS) logic. If one desires to interface the LED  16  with, e.g., TTL logic in order to drive a supplemental indicator or gather data from a remote location, then it is necessary to translate the non-logic-family signal levels of the LED  16  into the TTL family-logic levels. The translator  100  does this as follows. 
     The translator  100  is an implementation of the recognition that an LED  16  is inactive if the voltage on node  20 , i.e., the signal W, is approximately 5 volts. Thus, a voltage of 5 volts on the node  20  is treated as a logical high state. While it is true that the that the logical low state of the LED  16  can be determined by assessing whether the signal W is between 2 and 4 volts, this is a more complicated determination and so the determination of the logical high state is preferred. 
     The IC  102  determines whether the signal W is greater than 4.6 volts. The resistance values of the resistors R 1  and R 2  are selected such that the voltage on the inverting comparator  104  corresponds to the reference voltage  106  in such a way that the threshold of the undervoltage sensing IC  102  is set at 4.6 volts. 
     If the signal W is greater than 4.6 volts, then the comparator  104  outputs a low signal, which turns off the BJT  108 . When the BJT  108  is turned off, then the terminal element  112  of the IC  102  takes the voltage V DD  corresponding to the logical high state of the logic family, which is 5 volts for TTL logic. Thus, W TTL =5 volts when W is greater than 4.6 volts. However, when the LED  16  is emitting, W is between 2 and 4 volts, i.e., W is less than 4.6 volts. When W is less than 4.6 volts, the comparator  104  outputs a high signal, which turns on the BJT  108 . When turned on, the BJT  108  provides a path to relative system ground  18  so that the voltage on the terminal element  112  drops to the level of the relative system ground, which for TTL is approximately 0 volts such that W TTL =0. 
     The translator  200  of FIG. 2 digitally implements the algorithm inherent to the translator  100  of FIG.  1 . The analog signal W on node  20  is digitized by the A/D converter  202 . The digital representation of W is compared by the processor  204  to a reference value, e.g., 4.6 volts, stored in the memory  206 . The bi-directional connection between the memory  206  and the processor  204  permits the reference value to be changed. Alternatively, the memory  206  could be formed in some type of read-only memory. 
     If the processor  204  determines that the digital version of the signal W is greater than 4.6 volts, then the processor outputs a digital representation of the TTL high signal, i.e., 5 volts to the D/A converter  208 . The D/A converter  208  converts the digital representation from the processor  200  into the analog signal W TTL =5 volts. Similarly, if the level of signal W on node  20  is less than 4.6 volts, then the processor outputs a digital representation of the low signal for TTL, i.e., 0 which is converted to analog by the D/A converter  208  such that W TTL =0. 
     The embodiments have been discussed in terms of translating the non-logic-family signal into TTL signals. However, the non-logic-family signal could be converted into signal levels appropriate for CMOS, N MOS, ECL or any other logical signal definition. 
     The embodiment of FIG. 1 is preferred because it is simple and economical to implement especially in view of the commercial availability of the undervoltage sensing circuit  102 . However, the individual components of the IC  102  could be implemented discreetly, or as noted the translator  100  of FIG. 1 could be implemented as the processor-based translator  200  of FIG.  2 . 
     The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.