Abstract:
A regulator and related method for providing a regulated voltage. The regulator includes a bipolar junction transistor (BJT) as a charging circuit, a capacitive circuit formed for regulating the regulated voltage by bypass and regulation capacitors, an operational amplifier (OP-AMP), a bandgap circuit, and a pre-charging circuit. The capacitive circuit receives current to establish the regulated voltage. According to the regulated voltage, the OP-AMP biases the base of the BJT to obtain the accurate regulated voltage to control a current conducted to the capacitive circuit by the BJT. When the regulator starts to work, the OP-AMP is disabled to prevent the BJT from providing current. Instead the pre-charging circuit first provides a pre-charging current to charge the capacitive circuit, then the OP-AMP is enabled to turn on the BJT to charge the capacitive circuit and establish the steady-state regulated voltage.

Description:
BACKGROUND OF INVENTION 
   1. Field of the Invention 
   The present invention relates to a regulator for chip biasing and related control methods, and more particularly, to a regulator capable of charging a regulator capacitor with a pre-charging circuit so as to prevent a current-capture transistor of the regulator from generating initial currents that are too high, and related control methods. 
   2. Description of the Prior Art 
   In modern information society, a variety of electronic information apparatuses, such as cell-phones, personal computers and network servers, are all fabricated based on a microprocessor control system. How to enable a microprocessor to function normally is therefore becoming one of the most important R&amp;D topics of modern information industry. 
   In general, a microprocessor control system is realized by one or more than one chips installed on a circuit board, like a printed circuit board. In order to achieve high integration, low power consumption and fast operation speed, a core circuit, which is installed in the chip for data calculation and information manipulation, is always biased by a low voltage and generates electrical signals of low levels correspondingly. However, low-leveled signals do not have the capability to drive data in the core circuit to circuits outside of the chip and vice versa, so the chip usually further comprises an I/O circuit as an I/O buffer. Since both data and signals that the core circuit manipulates are of low levels, these data and signals cannot be transmitted to a region outside of the chip unless they have been pumped by the I/O circuit to become data and signals of high levels. On the contrary, data transmitted from the region outside of the chip to the chip are to be transformed by the I/O circuit to become data of low levels. 
   A regulator, capable of generating a regulated voltage of a low level by referring a direct voltage of a high level, is usually for biasing the core circuit with the regulated voltage to bias the I/O circuit with the direct voltage. According to the prior art, the regulator is realized by a Zener diode. One end of the Zener diode is reversed biased by the direct voltage and the other end of the Zener diode outputs the regulated voltage, which is equal to a voltage difference between the direct voltage and a voltage across the two ends of the Zener diode. 
   However, the regulated voltage that the prior art regulator generates is neither precise nor stable. 
   SUMMARY OF INVENTION 
   It is therefore a primary objective of the claimed invention to provide a regulator capable of generating a precise and stable regulated voltage to overcome drawbacks of the prior art. 
   In a prototype regulator of the present invention, an operational amplifier is used to detect a regulated voltage established by a power module and controls a BJT transistor in a pre-charging circuit to charge the power module and to establish and stabilize the regulated voltage. However, in the beginning of operation, the operational amplifier probably feeds back too great a current to drive the pre-charging circuit and therefore burns the BJT transistor. 
   Therefore, an amended regulator, capable of pre-charging a power module with a pre-charging circuit before a charging circuit charges the power module, first generates a voltage whose level is slightly lower than that of the regulated voltage. In the meantime, the operational amplifier and the charging module are still disabled. When the regulated voltage rises and is equal to a predetermined voltage, the regulator then enables the operational amplifier and the charging module, enabling the operational amplifier to feedback control the charging circuit to establish and to keep the regulated voltage. Since the regulated voltage has risen and is equal to the predetermined voltage after the operational amplifier functions, the operational amplifier can therefore keep the current actuated by the BJT transistor to have a level between a predetermined range, overcoming the problem of the prototype regulator and providing the chip with a correct and stable bias voltage. 
   These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
       FIG. 1  is a function block diagram of a chip and a circuit board according to the present invention. 
       FIG. 2  is a function block diagram of a regulator fabricated between the chip and the circuit board shown in  FIG. 1  according to the present invention. 
       FIG. 3  is a circuit diagram of a practical embodiment of an operational amplifier according to the present invention. 
       FIG. 4  is a circuit of a practical embodiment of a control circuit according to the present invention. 
       FIG. 5  is a timing diagram of voltages at corresponding nodes of a regulator in operation according to the present invention. 
   

   DETAILED DESCRIPTION 
   Please refer to  FIG. 1 , which is a function block diagram of a chip  10  and a circuit board  12 , both of which are installed in a micro-controller system, according to the present invention. The circuit board  12 , for example, is a motherboard and the chip  10  is a chip installed on the motherboard. The circuit board  12  can also be a printed circuit board with an add-on card installed and the chip  10  is for controlling the add-on card. The chip  10  comprises an I/O circuit  16  and a core circuit  14  for data calculation and information manipulation. The I/O circuit  16  buffers and transforms both data manipulated by the core circuit  14  and data ready to be transmitted to the circuit board  12  and raw data ready to be transmitted to the core circuit through the circuit board  12 . As described previously, the core circuit  14  is biased by a low-leveled voltage and generates low-leveled data and signals of low levels, which are to be pumped by the I/O circuit  16  and then to be transmitted to the circuit board  12 . On the contrary, the I/O circuit  16  reduces the voltage of both raw data and signals ready to be transmitted from the circuit board  12  to the core circuit. 
   Since the I/O circuit  16  is designed to exchange data with the circuit board  12  and vice versa, bias voltages to bias the I/O circuit  16  and the circuit board  12  are of equal levels. The circuit board  12  and the I/O circuit  16  of the chip  10  are biased by two distinct direct voltages Vcc and Vss (can be referred as ground) respectively. Since the core circuit  14  needs a low-leveled voltage as a bias voltage, the chip  10  has to combine with the circuit board  12  to form a regulator  18  to generate a regulated voltage Vp 25  to bias the core circuit  14 . Typically, the circuit board  12  provides the chip  10  with a direct voltage of 3.3 volts, while the bias voltage to bias the core circuit  14  is of 2.5 volts. For such a configuration, the regulator  18  generates the regulated voltage Vp 25 , capable of providing power for the core circuit  14  to operate, with the direct voltage Vcc of 3.3 volts. 
   In the regulator  18 , a bipolar junction transistor Qp 1 , which is installed on the circuit board  12 , functions as a charging circuit to provide currents. A capacitor Cp 1  functions as a power module  24 . In accordance with the transistor Qp 1  and the power module  24 , the chip  10  comprises an operational amplifier  20 , a bandgap circuit  22  for generating a bandgap voltage Vbg 0 , and two voltage-dividing resistors Rp 0  and Rp 1 . A bias voltage, whose level is between the direct voltages Vcc and Vss, biases the regulator  18 . The operational amplifier  20  has two differential input ends, labeled by “+” and “−” and connected to node Np 1  and to a bandgap voltage output end of the bandgap circuit  22  respectively. An output end Op 0  of the operational amplifier  20  is electrically connected to a base of the transistor QP 1  for biasing the base of the transistor Qp 1  with a driving voltage as a driving signal. In operation, the chip  10  can connect the output end Op 0  to the transistor Qp 1  of the circuit board  12  with a pin. The direct voltage Vcc biases an emitter of the transistor Qp 1 . A collector of the transistor Qp 1  is electrically connected to the power module  24  at node Np 0 . The power module  24  comprises a capacitor of high capacitance for voltage regulation and bypassing the interference of alternative fluctuation as well. The capacitor can be charged to a stable state and generates the regulated voltage Vp 25  at node Np 0 . The regulated voltage Vp 25  of the power module  24  at node Np 0  can be transmitted back to the chip  10  through another corresponding pin. The regulated voltage Vp 25  not only provides the core circuit  14  with the biased voltage, it also generates a divided voltage Vs 0  at node Np 1  through the use of the resistors Rp 0  and Rp 1 . After comparing the bandgap voltage Vbg 0  with the direct voltage Vs 0 , the operational amplifier  20  generates a driving voltage Vd 0  to control the transistor Qp 1 . 
   Operations of the regulator  18  are described as follows: when the circuit board  12  enables the chip  10  to start to function, the circuit board  12  provides the regulator  18  with the direct voltage Vcc to enable the regulator  18  to function. In the meantime, the operational amplifier  20  also starts to compare a voltage Vs 0  at node Np 1  with the bandgap voltage Vbg 0  generated by the bandgap circuit  22 . Since node Np 0  and the voltage Vs 0  both are kept at low level before the regulator  18  functions, as the operational amplifier  20  starts to function, the operational amplifier  20  outputs the driving voltage Vd 0  of a low level at the output end Op 0  due to a comparison result that the voltage Vs 0  is far smaller than the bandgap voltage Vbg 0 . In the mean time, a voltage across the emitter and base of the transistor Qp 1  is almost equal to a voltage difference between the direct voltages Vcc and Vss, enabling the transistor Qp 1  to generate a high-leveled current Ic 0  as a charging current to charge the high-capacitanced capacitors Cp 1  of the power module  24 . As the charging process keeps functioning, the voltages at node Np 0  as well as at node Np 1  are increasing and the operational amplifier  20  keeps increasing the driving voltage Vd 0  at the output end Op 0 . The degree to which the driving voltage Vd 0  is increased corresponds to the degree to which a voltage across the emitter and base of the transistor Qp 1  is decreased, enabling the transistor Qp 1  to conduct lesser currents. The operational amplifier  20  is capable of controlling the driving voltage Vd 0  by detecting the voltage Vs 0  and stabling the voltage Vp 25  at node Np 0 . After reaching to the stable state, the operational amplifier  20  keeps the voltage Vs 0  to be equal to the bandgap voltage Vbg 0 . That is, the voltage Vp 25  is equal to (1+Rp 0 /Rp 1 )Vbg 0 . Such the stable voltage Vp 25  can function as the direct biased voltage for the core circuit  14 . The current for the core circuit  14  to operate is therefore supplied by the transistor Qp 1 . Occasionally, when the voltage Vp 25  is changed, the operational amplifier  20  accordingly controls the driving voltage Vd 0  to be dynamically compensated. For example, if the core circuit  14  needs more current due to an increment of calculation, the capacitor Cp 2  is capable of preventing the voltage Vp 25  at node Np 0  from dropping abruptly. The voltage Vp 25  of a slightly reduced level enables the voltage Vs 0  to drop accordingly and a voltage across the emitter and base of the transistor Qp 1  to rise, thus increasing currents Ic 0  flowing through the transistor Qp 1  to meet the demand of increasing currents for the core circuit  14 . 
   However, although the regulator  18  shown in  FIG. 1  can generate the stable voltage Vp 25  to bias the core circuit  14 , the regulator  18  has a problem that the regulator  18  actuates too great currents to flow through the transistor Qp 1  in the beginning, the too great currents probably burning the transistor Qp 1 . As described previously, when the regulator  18  starts to operate, voltage at node Np 0  has a low level and the driving voltage Vd 0  output by the operational amplifier  20  at the output end Op 0  also has a low level. Therefore, a voltage across the emitter and base of the transistor Q 1  is almost equal to a voltage difference, 3.3 volts for example, between the direct voltages Vcc and Vss. However, the level of the voltage across the emitter and base of the transistor Q 1  for the transistor Q 1  to actuate a significant current is generally equal to 0.7 to 0.8 volts. Theefore, the current actuated by the regulator in the beginning of operation is in fact greater than a current for the transistor Qp 1  to operate normally dramatically. Such a high-leveled current probably burns the transistor Qp 1  while the regulator  18  is in the beginning of operation. 
   Accordingly, the present invention also presents an amended regulator. Please refer to  FIG. 2 , which is a function block diagram of a regulator  38  fabricated between a chip  30  and a circuit board  32  according to the present invention. In accordance with allocation of modern microprocessor, the chip  30  also comprises a core circuit  34  and an I/O circuit  36 , the core circuit  34  operating at the voltage V 25  of a lower level, and the I/O circuit  36  as well as the circuit board  32  biased by the direct voltage Vcc of a higher level. The direct bias Vss can be ground of zero volts. In order to generate the regulated voltage V 25  for the core circuit  34 , a regulator  38  is fabricated between the chip  30  and the circuit board  32  for generating the regulated voltage V 25  according to the direct bias Vcc provided by the circuit board  32 . The regulator  38  is biased by a voltage between the direct bias Vcc and Vss. The regulator  38  comprises a bandgap voltage generator  42  fabricated in the chip  30  for generating a bandgap voltage Vbg, an operational amplifier  40 , a control circuit  48 , a MOS transistor Q 3  functioning as a charge circuit, and two voltage-dividing resistors R 0  and R 1 . In accordance with the above circuit, the circuit board  32  also comprises a BJT Q 1  and a power module  46  for providing currents and appropriate reduced voltage. The operational amplifier  40  comprises a positive input end Inp electrically connected to node N 1 , a negative input end Inn for receiving the bandgap voltage Vbg, and an output end Op. In operation, the operational amplifier  40  generates a corresponding driving voltage Vd as a driving signal at the output end Op by referring by referring a voltage difference between the positive and negative input ends Inp and Inn. The driving voltage Vd is for controlling a base of the transistor Q 1 . In practice, the chip  30  can comprises a pin to electrically connect the output end Op to the base of the transistor Q 1 , whose emitter is biased by the direct voltage Vcc and a collector is electrically connected to node N 0 . Based on the control of the driving voltage Vd, the transistor Q 1  is capable of providing a charging current Ic to flow to node N 0 . The power module  46  comprises a capacitor C 1  of high capacitance for voltage regulation and bypassing unnecessary interference, enabling a voltage at node N 0  to be stable. With the power module  46  as a load, the regulator  38  is capable of generating the regulated voltage V 25  at node N 0 . The regulated voltage V 25  at node N 0  can be transmitted back to the core circuit  34  for biasing the core circuit  34  by connecting node N 0  through another pin in the chip  30  to a node N 3  of the chip  30 . The resistors R 0  and R 1  are capable of generating a dividing voltage Vs, equal to (R 1 /(R 0 +R 1 ))V 25 , at node N 1  and transmitting the dividing voltage Vs to the positive input end Inp of the operational amplifier  40 . 
   In the present invention, the control circuit  48  generates voltage signals Vpc, Vop and Vopb as control signals. The transistor Q 3 , as a pre-charging circuit, comprises a drain biased by the direct voltage Vcc, a body biased by the direct voltage Vss, a gate controlled by the voltage Vpc, and a source electrically connected to node N 3 . With the above connection, the transistor Q 3  is capable of generating a pre-charging current to flow to node N 3  based on the control of the control circuit  48 . The operational amplifier  40 , controlled by the voltage Vop as well as Vopb, selectably either disables the operational amplifier  40  to stop functioning or enables the operational amplifier  40  to start to function. In the preferred embodiment of the present invention, when the operational amplifier  40  is disabled, the operational amplifier  40  continuously outputs a high-leveled voltage (that is the direct voltage Vcc) at the output end Op to turn off the transistor Q 1 . When the operational amplifier  40  is enabled, the operational amplifier  40  generates the corresponding driving voltage Vd at the output end Op by referring a voltage difference between the positive and negative input ends Inp and Inn. 
   In accordance with the above allocation, the regulator  38  functions as following descriptions. In the beginning, the circuit board  32  provides the chip  30  and the regulator  38  with the direct voltage Vcc. In the meantime, the control circuit  48  disables the operational amplifier  40  with the voltages Vop and Vopb. As described previously, the disabled operational amplifier  40  outputs the driving voltage of a high level at the output end OP and disables the transistor Q 1  to actuate currents because of a voltage of substantial zero volts between the emitter and base of the transistor Q 1 . While the operational amplifier  40  is disabling, the control circuit  48  controls the transistor Q 3  with the voltage Vpc of a high level to provide the pre-charging charge Ipc to flow through nodes N 3  and N 0  and charge the power module  46 . In other words, at this moment the pre-charge current Ipc for charging the power module  46  is not generated by the transistor Q 1 , but by the transistor Q 3  instead. As the transistor Q 3  keeps charging the power module  46 , the regulated voltage V 25  at node N 0  rises from a voltage of a low-level (equal to the level of the direct voltage Vss), and the control circuit  48  keeps estimating how high the regulated voltage V 25  has risen until the control circuit  48  estimates that the regulated voltage V 25  has risen to a voltage equal to a predetermined voltage. In the preferred embodiment of the present invention, the predetermined voltage is a voltage whose level is slightly lower than that of the regulated voltage V 25 . As soon as the control circuit  48  has estimated that the regulated voltage V 25  has risen to the predetermined voltage, the control circuit  48  changes levels of the voltage signals Vop, Vopb and Vpc, enables the operational amplifier  40 , and turns off the transistor Q 3  not to provide the pre-charging current Ipc. After starting to function, the operational amplifier  40  generates the corresponding driving voltage Vd by referring a voltage difference between the voltage Vs and the bandgap voltage Vbg and controls the transistor Q 1  to actuate the charging current Ic to charge the power module  46 . Eventually, the operational amplifier  40  keeps the regulated voltage V 25  to have a stable level equal to (1+R 0 /R 1 )Vbg. 
   From the above descriptions, when the regulator  38  begins to function and the regulated voltage V 25  is equal to zero volts, the regulator  38  disables the feedback control between the operational amplifier  40  and the transistor Q 1 , preventing the operational amplifier  40  from excessively driving the transistor Q 1  because of too high a voltage difference between the voltage Vs and the bandgap voltage Vbg. When disabling the operational amplifier  40 , the regulator  38  provides the pre-charging current Ipc with the transistor Q 3 , served as a pre-charging circuit, to flow to the power module  46  and to charge the capacitors C 1  and C 2 , raising the regulated voltage V 25  at node N 0 . As soon as the regulated voltage V 25  is raised to the predetermined voltage, the control circuit  48  controls the transistor Q 3  with the signal Vpc not to actuate and to stop providing the pre-charging current Ipc. The control circuit  48 , in the meantime, enables the operational amplifier  40  with the signals Vop and Vopb, enabling the feedback control between the operational amplifier  40  and the transistor Q 1  and stabilizing the regulated voltage V 25 . That is, while the operational amplifier  40  is functioning, the regulated voltage V 25  is not a low-leveled voltage any more and the voltage Vs is becoming closer and closer to the bandgap voltage Vgp, enabling the operational amplifier  40  to output the driving voltage Vd of a level higher than that of the low-leveled voltage. Therefore, as the driving voltage Vd actuates the transistor Q 1 , a problem of too low a voltage between the emitter and base can be approved and the transistor Q 1  will not be exceedingly driven to actuate too great a current. 
     FIG. 3  is a circuit diagram of a practical embodiment of the operational amplifier  40  according to the present invention.  FIG. 4  is a circuit of a practical embodiment of the control circuit  48  according to the present invention. As shown in  FIG. 3 , the operational amplifier  40  is biased by voltages ranging between the direct voltages Vcc and Vss and is composed of NMOS transistors T 1 , T 2 , T 5  to T 8 , T 12  and T 14  and PMOS transistors T 3 , T 4 , T 9  to T 11  and T 13 . NMOS transistors S 1  to S 3  and S 7  and PMOS transistors S 4  and S 5  are functioned as switch transistors for the need to enabling or disabling the operational amplifier  40 . Each of the NMOS transistors comprises a body biased by the direct voltage Vss. Each of the PMOS transistors also comprises a body biased by the direct voltage Vcc. The transistors T 1  and T 2  form a differential pair. The transistors T 1  and T 2  comprise respective gates, serving as the positive and negative input ends of the operational amplifier  40 . The transistor T 5 , connected to the differential pair at node N 5  and serving as a current source for bias, comprises a gate electrically connected to gates of the transistors T 6 , T 7  and T 14  to form a current mirror. A support circuit  50 , capable of generating a current Ir to serve as a reference current, adjusts a level of a bias voltage at node T 5  through the use of the current mirror. The transistors T 3  and T 4  function as active loads of the differential pair. The transistors T 3  and T 4  comprise respective gates connected to gates of the transistors T 9  and T 11  and form another current mirror. In summary, the transistors T 1  and T 5  form a differential input stage of the operational amplifier  40 . Signals amplified by the differential input stage are further amplified by a second stage, including the transistors T 6  to T 11 , of the operational amplifier  40 . The operational amplifier  40  has the transistors T 12  and T 13  as a class AB output stage and node N 8  as the output end Op. 
   In contrast to the transistors T 1  to T 14 , which form a basic structure of the operational amplifier  40 , the switch transistors S 1  to S 7  control biases applied to the gates of the transistors T 1  to T 14  and enables or disables the operational amplifier  40 . The transistors S 1 , S 2  and S 7  have gates controlled by the signal Vop generated by the control circuit  48 , please further refer to  FIG. 2 , while the transistors S 3  to S 5  have gates controlled by the signal Vopb. Operations for the operational amplifier  40  to disable or enable by referring by referring the signals Vop and Vopb are described as follows: When disabling the operational amplifier  40 , the control circuit sets the signals Vop and Vopb to have a high and low level respectively, conducting the switch transistors S 1  to S 7 . Conducted transistors S 1  and S 3  reduce a voltage at node N 6  to a voltage equal to the direct voltage Vss, turning off the transistors T 5  to T 7  and T 14  and enabling the current Ir generated by the support circuit  50  to flow into the conducted transistor Q 3  instead of the transistor Q 14 . Likewise, conducted transistors S 2  and S 7  pull voltages at the gates of the transistors TB and T 12  down to a voltage equal to the direct voltage Vss and turn off the transistors T 8  and T 12  accordingly. The transistor T 10  is actuated. Conducted transistors S 4  and S 5  pull voltages at the gates of the transistors T 3 , T 4 , T 9  and T 11  up to a voltage equal to the direct voltage Vcc and turn off these four transistors. The actuated transistor T 10  combined with the turned off transistor T 11  are capable of pulling a voltage at the gate of the transistor T 13  down to a voltage of a low level, turning on the transistor T 13 , and pulling a voltage (the driving voltage shown in Fi. 2 ) at the output end Op up to a voltage equal to the direct voltage Vcc. When the regulator  38  just starts operating, the operational amplifier  40  is disabled and the high-leveled driving voltage Vd at the output end makes a voltage difference between the emitter and the base of the transistor Q 1  neglected and turns off the transistor Q 1 . 
   In contrast, when enabling the operational amplifier  40 , the control circuit  48  pulls the voltage Vop up to a voltage of a high level and the voltage Vopb down to a voltage of a low level. The transistors S 1  to S 7  are then turned off from affecting biases applied to the gates of the transistors T 1  to T 14 , the transistors T 1  to T 14  then capable of executing normal functions that the operational amplifier  40  has, generating the corresponding driving voltage Vd at the output end Op by referring by referring a voltage difference between the positive and negative input ends Inp and Inn. 
   As shown in  FIG. 4 , the control circuit  48  of the present invention comprises NMOS transistors M 1  to M 3 , M 5 , M 6 , M 9  to M 11 , PMOS transistors M 4 , M 7  and M 8 , and an inverter  52  and a NOR gate  54 , both of which are biased by voltages ranging between the direct voltage Vcc and Vss. Each of the PMOS transistors has a body biased by the direct voltage Vcc, while each of the NMOS has a body biased by the direct voltage Vss. The transistors M 1  to M 3  have respective gates all electrically connected to the direct voltage Vcc for forming an internal pre-charging circuit  56 , which is electrically connected to a gate of the transistor M 6  at node N 9 . The transistor M 6  further comprises a drain and a source, both of which are biased by the direct voltage Vss and form a capacitor as a second power module. The internal pre-charging circuit  56  is capable of charging the capacitor formed by the transistor M 6  and generating a voltage V 2  at node N 9 . The transistors M 7 , M 9  and M 10  are connected to form a circuit of an inverter, receiving the voltage V 2  as an input voltage with the gate and outputting the voltage Vpc for the control circuit  48  to control the transistor Q 3  at node  10 , please further refer to FIG.  5 . Through the use of the NOR gate  54  and the inverter  52 , the control circuit  48  is capable of generating another two control signals Vop and Vopb with the voltage Vpc to enable or disable the operational amplifier  40 . 
   Please refer to  FIG. 5 , which is a timing diagram of voltages at corresponding nodes of the regulator  38  in operation according to the present invention, an abscissa representing time and an ordinate representing levels of the voltages. In  FIG. 5 , solid lines from top to bottom represent the regulated voltage V 25 , a voltage Vreg, the voltage V 2  in the control circuit  48 , as shown in  FIG. 4 , and the signals Vpc, Vop and Vopb for the control circuit  48  to control the transistor Q 3  and the operational amplifier  40 . In following paragraph  FIG. 5  will be used to illustrate operations of the control circuit  48  and the regulator  38  as well. As shown in  FIG. 5 , it is assumed that the circuit board  32  enables the chip  30  to start to operate at time t0. As described previously, at this moment the circuit board  32  begins to provide the regulator  38  with the direct voltage Vcc. At time t0 the voltage Vreg of a low level enables the transistors M 4  and MB (referring to  FIG. 4 ) to be turned on and the transistors M 5  and M 11  to be turned off. In the meantime, the internal pre-charging circuit  56  begins to actuate a current Ipc 2  as a second pre-charging current to flow to the gate of the transistor Q 6  through node N 9  due to the bias the direct voltage Vcc, like charging the capacitor formed by the transistor Q 6  and raising the voltage V 2  at node N 9  for a voltage of a low level. However, a voltage at node N 9  at time t0 is still a low-leveled voltage, which turns on the transistor M 7  and turns off the transistors M 9  and M 10 , pulling the voltage Vpc at node N 10  as well as the voltage Vop up to voltages of high levels. The inverter  52  of the control circuit  48  pulls the signal Vopb down to a voltage of a low level. As described previously, the high-leveled voltage Vpx turns on the transistor Q 3  and enables the transistor Q 3  to actuate the pre-charging current Ipc to charge the power module  46  and to raise the voltage V 25 . In the meantime, the signal Vop has a high level and the signal Vopb has a low level, enabling the operational amplifier  40  to be disabled and to output the driving voltage Vd of a high level at the output end Op to turn off the transistor Q 1  (referring to  FIG. 2 ,  FIG. 3 , and corresponding descriptions). 
   As shown in  FIG. 5 , as the internal pre-charging circuit  56  charges the transistor M 6  at time t0, the voltage V 2  at node N 9  starts to rise from a voltage of a low level and eventually reaches to a voltage great enough to turn off the transistor M 7  and to turn on the transistors M 9  and M 10 , thus reducing the high-leveled voltage Vpc at time t0 to the voltage Vpc of a low level at time t1, reducing the high-leveled voltage Vop to the voltage Vop of a low level, and raising the low-leveled voltage Vopb at time t1 to the voltage Vopb of a high level. Moreover, from the time t0 to t1, not only does the internal pre-charging circuit  56  of the control circuit  48  charge the capacitor formed by the transistor Q 6 , the transistor Q 3 , as a pre-charging circuit, of the regulator  38  also charges the capacitors C 1  and C 2  of the power module  46 , raising the regulated voltage V 25  at node N 0  from the time to on. Up to time t1, the regulated voltage V 25  has been raised to a voltage of a level equal to a voltage level V 25   m . Since the voltages Vpc, Vop and Vopb at time t1 have changed, the transistor Q 3  is then turned off and stops actuating the pre-charging current Ipc. The operational amplifier  40  begins to operate after time t1 and adjusts the driving voltage Vd to drive the transistor Q 1  to charge the power module  46 , raising the driving voltage Vd after time t1 until that the driving voltage Vd is stable. The stable driving voltage Vs is equal to (1+R 0 /R 1 )Vbg. For example, the stable driving voltage Vs is 2.5 volts. The stable driving voltage Vs can then used for the operations of the core circuit  34 . 
   It is apparent from the previous descriptions that when the operational amplifier  40  and the transistor Q 1  begin to operate, the regulated voltage V 25  is generated by the transistor Q 3  in the pre-charging circuit from time t0 to t1, from a voltage of a low level at time t0 to a voltage equal to the voltage V 25   m  at time t1. The operational amplifier  40  drives the transistor Q 1  at time t1 with the regulated voltage V 25  instead of the driving voltage Vd of a low level and prevents the transistor Q 1  from burning out due to too great a current. Additionally, it can be seen in  FIG. 5  that the sooner the voltage Vc 2  of the control circuit  48  is changed, the earlier the operational amplifier  40  as well as the transistor Q 1  begin to operate. For example, if the voltage Vc 2  changes in accordance with a dotted curve Vc 2   p , at time tp the voltage Vc 2  rises to a voltage to enable the voltages Vpc and Vop to be reduced and the voltage Vopb to be increased. Therefore, as the regulated voltage V 25  is raised to be equal the stable regulated voltage V 25   mp , the regulated voltage V 25  is then made stable by the operational amplifier  40  and the transistor Q 1 . In other words, in order to control the transistors Q 3  and Q 1  capable of operating sequentially when the regulated voltage V 25  is raised to be equal to a predetermined voltage, the internal pre-charging circuit  56  of the control circuit  48  can be controlled to adjust the speed to charge the transistor M 6 , the transistor Q 3  charging the power module  46  to a voltage equal to the predetermined voltage when the voltage Vc 2  is raised to a voltage whose level is high enough to trigger the voltages Vpc, Vop and Vopb to change. Moreover, the transistor M 6  and currents actuated by the internal pre-charging circuit  56  can be adjusted to adjust the speed for the internal charging circuit  56  to charge the transistor M 6 . For example, if the current Ipc 2  actuated by the pre-charging circuit  56  is equal to one-tenth of the pre-charging current Ipc flowing through the transistor Q 3 , and the equivalent capacitance of the transistor M 6  is also equal to one-tenth of the equivalent capacitance of the power module  46 , the voltage Vpc 2  will rise as fast as the regulated voltage V 25  when the transistor Q 3  is in operation. Therefore, the rising speed for the voltage Vpc 2  can be used to estimate the rising speed for the voltage V 25  and the timing for the transistors Q 3  and Q 1  to operate sequentially. 
   In contrast to the prior art, the present invention can provide a regulator capable of providing a stable and concise regulated voltage in a feedback control manner. In the prototype regulator, since the operational amplifier controls the BJT transistor Qp 1  to operate according to a low-leveled regulated voltage in the beginning and drives the transistor Qp 1  exceedingly, the transistor Qp 1  is easily burned-out, disabling the regulator to generate the regulated voltage and preventing the core circuit of the chip from getting the bias voltage and operating. In the present invention, the transistor Q 3  functions as a pre-charging circuit and raises the regulated voltage to a voltage equal to a predetermined voltage prior to the operations of the operational amplifier and the BJT transistor Q 1 , preventing the transistor Q 1  from burning out due to too great driving currents to drive the transistor Q 1  after the operational amplifier starts to function, allowing the regulator to function normally thereafter, and ensuring that the core circuit can obtain the concise and stable bias voltage. 
   Following the detailed description of the present invention above, those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.