Abstract:
A semiconductor device is provided which includes a semiconductor substrate, a gate insulating film which is provided on the semiconductor substrate and contains a first metallic element and oxygen, and a gate electrode which is provided on the gate insulating film and includes a metal silicide film containing a second metallic element, and an impurity layer interposed between the gate insulating film and the metal silicide film and containing a p type impurity element, wherein a Gibbs free energy of a first system including an insulator containing the first metallic element and oxygen, the p type impurity element and silicon is smaller than a Gibbs free energy of a second system including a compound containing the first metallic element and the p type impurity element, and a silicon oxide.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2004-172745, filed Jun. 10, 2004, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a semiconductor device and a method of manufacturing the same.  
         [0004]     2. Description of the Related Art  
         [0005]     To enhance the performance of MIS transistors, scale down of MIS transistors is indispensable. However, with scale down of MIS transistors, a leakage current (tunnel current) of a gate insulating film and depletion of a polysilicon gate electrode become great problems.  
         [0006]     To solve such problems, it has been considered adopting a gate insulating film having a high dielectric constant, such as an Hf oxide film, and adopting a metal gate electrode. By using a gate insulating film of a high dielectric constant, the thickness of the gate insulating film can be set thick, and thus it is possible to suppress a tunnel current. Further, by adopting a metal gate electrode, it is possible to prevent depletion of the gate electrode.  
         [0007]     However, in a gate structure using a metal electrode, there arises a new problem which is different from that in the conventional gate structure using polysilicon. In the conventional gate structure using polysilicon, a threshold voltage of a transistor depends on the impurity concentration in a channel region and the impurity concentration in the polysilicon film. In comparison with this, in the gate structure using a metal electrode, a threshold voltage of a transistor depends on the impurity concentration in a channel region and a work function of the metal gate electrode.  
         [0008]     Therefore, it is necessary to adopt a so-called dual metal gate structure, in which two types of gate electrode materials having different work functions are used for an n type MIS transistor and a p type MIS transistor. For example, a conductive material having a work function φm lower than 4.6 eV is used for a gate electrode of the n type MIS transistor, and a conductive material having a work function φm higher than 4.6 eV is used for a gate electrode of the p type MIS transistor.  
         [0009]     As a method of obtaining a dual metal gate structure, for example, “Dual Work Function Metal Gates Using Full Nickel Silicidation of Doped Poly-Si” J. H. Sim et al., IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 10, OCTOBER 2003, pp 631-633 discloses a method of performing ion implantation of impurity elements into metal silicide. Specifically, As is implanted as an n type impurity into a metal silicide film in an n type MIS transistor region by ion implantation, and B is implanted as a p type impurity into a metal silicide film of a p type MIS transistor region by ion implantation. By using this method, it is possible to set the work functions of the n type MIS transistor and the p type MIS transistor to be different from each other.  
         [0010]     However, in the method disclosed in the above document, a silicon oxide film is used as gate insulating film. If a metal oxide film, such as an Hf oxide film, is used as gate insulating film, it may cause the new problem. Therefore, the method disclosed in the above document cannot always form a MIS transistor having excellent property and reliability.  
         [0011]     As described above, in prior art, it is difficult to obtain a semiconductor device which can optimize the work function of the gate electrode, without causing an adverse influence on the property and reliability of the transistor.  
       BRIEF SUMMARY OF THE INVENTION  
       [0012]     A semiconductor device according to a first aspect of the present invention comprises: a semiconductor substrate; a gate insulating film which is provided on the semiconductor substrate and contains a first metallic element and oxygen; and a gate electrode which is provided on the gate insulating film and includes a metal silicide film containing a second metallic element, and an impurity layer interposed between the gate insulating film and the metal silicide film and containing a p type impurity element, wherein a Gibbs free energy of a first system including an insulator containing the first metallic element and oxygen, the p type impurity element and silicon is smaller than a Gibbs free energy of a second system including a compound containing the first metallic element and the p type impurity element, and a silicon oxide.  
         [0013]     A semiconductor device according to a second aspect of the present invention comprises: a semiconductor substrate; a gate insulating film which is provided on the semiconductor substrate and contains a first metallic element, oxygen and nitrogen; and a gate electrode which is provided on the gate insulating film and includes a metal silicide film containing a second metallic element, and an impurity layer interposed between the gate insulating film and the metal silicide film and containing a p type impurity element, wherein a Gibbs free energy of a first system including an insulator containing the first metallic element, oxygen and nitrogen, the p type impurity element and silicon is smaller than a Gibbs free energy of a second system including a compound containing the first metallic element and the p type impurity element, a compound containing the p type impurity element and nitrogen, and a silicon oxide.  
         [0014]     A method of manufacturing a semiconductor device according to a third aspect of the present invention comprises: forming a gate insulating film containing a first metallic element and oxygen on a semiconductor substrate; forming a silicon film on the gate insulating film; introducing a p type impurity element into the silicon film; forming a metal film containing a second metallic element on the silicon film; and forming a metal silicide film containing the second metallic element by reaction between the silicon film and the metal film, and an impurity layer containing the p type impurity element between the gate insulating film and the metal silicide film, wherein a Gibbs free energy of a first system including an insulator containing the first metallic element and oxygen, the p type impurity element and silicon is smaller than a Gibbs free energy of a second system including a compound containing the first metallic element and the p type impurity element, and a silicon oxide.  
         [0015]     A method of manufacturing a semiconductor device according to a fourth aspect of the present invention comprises: forming a gate insulating film containing a first metallic element, oxygen and nitrogen on a semiconductor substrate; forming a silicon film on the gate insulating film; introducing a p type impurity element into the silicon film; forming a metal film containing a second metallic element on the silicon film; and forming a metal silicide film containing the second metallic element by reaction between the silicon film and the metal film, and an impurity layer containing the p type impurity element between the gate insulating film and the metal silicide film, wherein a Gibbs free energy of a first system including an insulator containing the first metallic element, oxygen and nitrogen, the p type impurity element and silicon is smaller than a Gibbs free energy of a second system including a compound containing the first metallic element and the p type impurity element, a compound containing the p type impurity element and nitrogen, and a silicon oxide. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING  
       [0016]     FIGS.  1  to  8  are cross-sectional views which schematically illustrate steps of manufacturing a semiconductor device according to an embodiment of the present invention.  
         [0017]      FIG. 9  is a diagram illustrating a relationship between concentrations of impurity elements and amount of change of work functions. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]     An embodiment of the present invention will now be described with reference to drawings.  
         [0019]     FIGS.  1  to  8  are cross-sectional views which schematically illustrate steps of manufacturing a semiconductor device (MIS transistor) according to the embodiment of the present invention.  
         [0020]     First, as shown in  FIG. 1 , a hafnium oxide film (HfO 2  film) containing hafnium (a first metallic element) is formed as a gate insulating film  102  on a single-crystal silicon substrate (semiconductor substrate)  100  having isolation regions  101 . A zirconium oxide film (ZrO 2  film) may be used instead of the hafnium oxide film. Thereafter, a polysilicon film  103  and a silicon nitride film  104  are deposited on the gate insulating film  102 .  
         [0021]     Next, as shown in  FIG. 2 , the polysilicon film  103  and the silicon nitride film  104  are subjected to anisotropic etching to form a gate electrode pattern. Thereafter, arsenic ions (As +  ions) are implanted into an n type MIS transistor region, and boron ions (B +  ions) are implanted into a p type MIS transistor region. Further, the structure is subjected to heat treatment at 800° C. for 5 seconds, and thereby source/drain low-concentration diffusion layers  105  are formed.  
         [0022]     Next, as shown in  FIG. 3 , a silicon oxide film  106  and a silicon nitride film  107  are deposited on the whole surface of the structure. Then, anisotropic etching is performed to leave the silicon oxide film  106  and the silicon nitride film  107  on side surfaces of the gate electrode pattern. Thereafter, phosphorus ions (P +  ions) are implanted into the n type MIS transistor region, and boron ions (B +  ions) are implanted into the p type MIS transistor region. Further, the structure is subjected to heat treatment at 1000° C. for 5 seconds, and thereby source/drain high-concentration diffusion layers  108  are formed. Thereafter, an Ni film is formed by PVD (physical vapor deposition). Then, heat treatment is performed at 400° C. for 30 seconds to react the Ni film with the surface of the silicon substrate  100 , forming an Ni silicide film  109 .  
         [0023]     Next, as shown in  FIG. 4 , an interlayer insulating film  110  is deposited on the whole surface of the structure. Then, the interlayer insulating film  110  is planarized by CMP (chemical mechanical polishing). Thereby, a surface of the polysilicon film  103  is exposed.  
         [0024]     Next, as shown in  FIG. 5 , a photoresist pattern  111  is formed by using photolithography. The photoresist pattern  111  covers the p type MIS transistor region, and does not cover the n type MIS transistor region. Then, with the photoresist pattern  111  used as mask, P +  ions or As +  ions are implanted into the polysilicon film  103 .  
         [0025]     Next, as shown in  FIG. 6 , a photoresist pattern  112  is formed by using photolithography. The photoresist pattern  112  covers the n type MIS transistor region, and does not cover the p type MIS transistor region. Thereafter, with the photoresist pattern  112  used as mask, indium ions (In +  ions) are implanted as p type impurity element ions into the polysilicon film  103 . Gallium ions (Ga +  ions) may be used instead of the indium ions. Then, heat treatment is performed at 900° C. for 10 seconds. By this heat treatment, the impurity element introduced into the polysilicon film  103  uniformly diffuses in the thickness direction of the polysilicon film  103 .  
         [0026]     Next. As shown in  FIG. 7 , a nickel (a second metallic element) film (Ni film) is formed as a metal film  113  by PVD.  
         [0027]     Next, as shown in  FIG. 8 , heat treatment is performed at 400° C. for 30 seconds. By this heat treatment, the Ni film  113  reacts with the polysilicon film  103 , and thereby an Ni silicide film is formed as a metal silicide film  114 . Further, by this heat treatment, in the n type MIS transistor region, the implanted phosphorus (P) is precipitated in an interface between the gate insulating film  102  and the metal silicide film  114 , and thereby an impurity layer  115  containing phosphorus is formed. In the p type MIS transistor region, the implanted indium (In) is precipitated in an interface between the gate insulating film  102  and the metal silicide film  114 , and thereby an impurity layer  116  containing indium is formed. Thereafter, unreacted Ni is removed by a mixed solution of sulfuric acid and hydrogen peroxide.  
         [0028]     As described above, in the n type MIS transistor region, a gate electrode having the impurity layer  115  formed of phosphorus (P) or arsenic (As) and the Ni silicide film  114  is formed. In the p type MIS transistor region, a gate electrode having the impurity layer  116  formed of indium (In) and the Ni silicide film  114  is formed. The work function of the impurity layer  115  formed of phosphorus (P) or arsenic (As) is lower than the work function of the Ni silicide film  114  by about 0.2 eV. The work function of the impurity layer  116  formed of indium (In) is higher than the work function of the Ni silicide film  114  by about 0.2 eV. The work function of the gate electrode depends on the work function in its portion contacting the gate insulating film. Therefore, it is possible to set the work function of the gate electrode of the p type MIS transistor to be higher than the work function of the gate electrode of the n type MIS transistor.  
         [0029]     As described above, according to the embodiment of the present invention, In is introduced as impurity element into the polysilicon film  103  in the p type MIS transistor region. Using In like this enables formation of a MIS transistor having excellent property and reliability. This point is explained as follows.  
         [0030]     In the step shown in  FIG. 6 , if boron (B) is implanted instead of indium (In), it was found that in the heat treatment in  FIG. 8 , Ni in the Ni silicide film  114  is diffused into the silicon substrate  100 . The reason why such diffusion occurs is considered below.  
         [0031]     Suppose that a silicon oxide film, polysilicon film and Ni film are stacked on the silicon substrate, and thereafter an Ni silicide film is formed by heat treatment. In such a case, impurity elements which exceed the solubility limit are discharged from the Ni silicide film, and precipitated in the interface between the Ni silicide film and the polysilicon film. Then, when the polysilicon film is entirely transformed into the Ni silicide film, the impurity elements are precipitated in the interface between the Ni silicide film and the silicon oxide film. As a result, in the n type MIS transistor region, P or As is precipitated in the interface between the silicide film and the silicon oxide film, and in the p type MIS transistor region, B is precipitated in the interface between the silicide film and the silicon oxide film. As described above, if a silicon oxide film is used as gate insulating film, B does not diffuse into the silicon substrate, and it is possible to precipitate impurity elements in the interface between the silicide film and the silicon oxide film.  
         [0032]     However, if an Hf oxide film or a Zr oxide film is used as gate insulating film, the following problem arises.  
         [0033]     Generally, Zr oxides and Hf oxides are thermally stable in comparison with Ti oxides and easy to use as gate insulating film. This is because Zr oxides and Hf oxides do not easily react with Si, while Ti oxides easily react with Si. This can be thermodynamically expressed as follows: 
 
TiO 2 +2Si→SiO 2 +TiSi ΔG&lt;0  (1) 
 
ZrO 2 +2Si→SiO 2 +ZrSi ΔG&gt;0  (2) 
 
HfO 2 +2Si→SiO 2 +HfSi ΔG&gt;0  (3) 
 
         [0034]     As shown in formula (1), the amount of change ΔG of Gibbs free energy when TiO 2  is reduced by Si has a negative value. In comparison with this, as shown in formulae (2) and (3), the amount of change of Gibbs free energy when ZrO 2  or HfO 2  is reduced by Si has a positive value. Therefore, in the reaction of formula (1), the state of the right side of the formula is thermodynamically more stable than the state of the left side. In the reactions of formulas (2) and (3), the state of the left side of the formula is thermodynamically more stable than the state of the right side.  
         [0035]     However, the circumstances change in the system containing B. It is known that Ti, Zr and Hf react with B to generate a thermally stable compound. Therefore, if Si and B exist together, Ti oxides, Zr oxides and Hf oxides are reduced. This can be thermodynamically expressed as follows: 
 
TiO 2 +Si+2B→SiO 2 +TiB 2  ΔG&lt;0  (4) 
 
ZrO 2 +Si+2B→SiO 2 +ZrB 2  ΔG&lt;0  (5) 
 
HfO 2 +Si+2B→SiO 2 +HfB 2  ΔG&lt;0  (6) 
 
         [0036]     As is clear from formulas (4)-(6), in all of TiO 2 , ZrO 2  and HfO 2 , the amount of change of Gibbs free energy has a negative value. Specifically, TiB 2 , ZrB 2  and HfB 2  are thermodynamically more stable than TiO 2 , ZrO 2  and HfO 2 .  
         [0037]     Therefore, if a Zr oxide or an Hf oxide is used as gate insulating film and B is used as impurity element, the Zr oxide or Hf oxide is undesirably reduced. Since Zr oxides and Hf oxides have a high barrier property, they can suppress diffusion of Ni into the silicon substrate. However, if the Zr oxide and the Hf oxide are reduced, they cannot suppress diffusion of Ni into the silicon substrate. As a result, as described above, if B ions are implanted instead of In ions in the step shown in  FIG. 6 , Ni in the Ni silicide film  114  in the heat treatment of  FIG. 8  diffuses into the silicon substrate  100 .  
         [0038]     If Ga (gallium) or In (indium) is used as p type impurity instead of B, it is possible to prevent the above diffusion. If Ga or In is used, the following formulae are established: 
 
MeO 2 +Si+2Ga→SiO 2 +MeGa 2  ΔG&gt;0  (7) 
 
MeO 2 +Si+2In→SiO 2 +MeIn 2  ΔG&gt;0  (8) 
        Me is Zr or Hf.        
 
         [0040]     As is clear from formulae (7) and (8), The Gibbs free energy of the system including a metal oxide (MeO 2 ) containing a metallic element (Me) and an impurity element (Ga or In) and silicon (Si) is smaller than the Gibbs free energy of the system including a compound containing the metallic element (Me) and the impurity element (Ga or In) and a silicon oxide (SiO 2 ). Specifically, in the reactions indicated by formulae (7) and (8), the amount of change of the Gibbs free energy has a positive value, and MeO 2  (ZrO 2  or HfO 2 ) can stably exist. Therefore, If a Ze oxide film or an Hf oxide film is used as gate insulating film, the Zr oxide film or the Hf oxide film can prevent diffusion of Ni in the Ni silicide film into the silicon substrate.  
         [0041]     Also in the case where a metal silicate is used as gate insulating film, using Ga or In instead of B enables prevention of the above diffusion.  
         [0042]     If a metal silicate is used as gate insulating film, the following formulae are established: 
 
MeSiO 4 +Si+2B→2SiO 2 +MeB 2  ΔG&lt;0  (9) 
 
MeSiO 4 +Si+2Ga→2SiO 2 +MeGa 2  ΔG&gt;0  (10) 
 
MeSiO 4 +Si+2In→2SiO 2 +MeIn 2  ΔG&gt;0  (11) 
        Me is Zr or Hf.        
 
         [0044]     As is clear from formulae (10) and (11), the Gibbs free energy of the system including a metal silicate (MeSiO 4 ) containing a metallic element (Me) and an impurity element (Ga or In) and silicon (Si) is smaller than the Gibbs free energy of the system including a compound containing the metallic element (Me) and the impurity element (Ga or In) and a silicon oxide (SiO 2 ). Specifically, in the reactions expressed by the formulae (10) and (11), the amount of change of the Gibbs free energy has a positive value, and MeSiO 4  (ZrSiO 4  or HfSiO 4 ) can stably exist.  
         [0045]     Further, also in the case where a metal silicate containing nitrogen (hereinafter referred to as “MeSiON” for convenience), using Ga or In instead of B enables prevention of the above diffusion.  
         [0046]     Since nitrogen introduced into a metal silicate is in the state of being bonded to silicon, the MeSiON is considered as having a state where MeSiO 4  and Si 3 N 4  coexist. Therefore, if a metal silicate containing nitrogen is used as gate insulating film, the following formulae are established: 
 
4MeSiO 4 +Si 3 N 4 +Si+12B→8SiO 2 +4MeB 2 +4BN ΔG&lt;0  (12) 
 
4MeSiO 4 +Si 3 N 4 +Si+12Ga→8SiO 2 +4MeGa 2 +4GaN ΔG&gt;0  (13) 
 
4MeSiO 4 +Si 3 N 4 +Si+12In→8SiO 2 +4MeIn 2 +4InN ΔG&gt;0  (14) 
        Me is Zr or Hf.        
 
         [0048]     As is clear from the formulae (13) and (14), the Gibbs free energy of the system including a metal silicate (MeSiON (MeSiO 4 +Si 3 N 4 )) containing a metallic element (Me) and nitrogen and an impurity element (Ga or In) and silicon (Si) is smaller than the Gibbs free energy of the system including a compound containing the metallic element (Me) and the impurity element (Ga or In), a compound containing the impurity element (Ga or In) and nitrogen, and a silicon oxide (SiO 2 ). Specifically, in the reactions expressed by the formulae (13) and (14), the amount of change of the Gibbs free energy has a positive value, and MeSiON (ZrSiON or HfSiON) can stably exist.  
         [0049]      FIG. 9  is a diagram illustrating a relationship between concentrations of the impurity elements (In or Ga) existing in the interface between the Ni silicide film and the Hf oxide film and the amounts of change (AW) of the work functions. As shown in  FIG. 9 , with respect to both In and Ga, the work function increases when the impurity concentration exceeds about 1×10 19  cm −3 .  
         [0050]     Although In and Ga are p type impurities, their solubility limit concentrations in Si are about 7×10 18  cm −3 , which is much lower than the solubility limit concentration of B, 1×10 20  cm −3 . Therefore, In and Ga are not suitable for a high-concentration p type diffusion layer (such as a source/drain p type diffusion layer) and a high-concentration p type polysilicon film (such as a p type polysilicon film for a gate electrode). Therefore, B is generally used as p type impurity (acceptor) in silicon, and In and Ga are not used. In this embodiment, In or Ga is used as metal layer for defining the work function of the gate electrode, not as acceptor, and thus their low solubility limit does not cause any problem. In other words, using In or Ga which are hardly used as p type impurity in silicon as metal layer can avoid the abovementioned problems due to use of B.  
         [0051]     As described above, according to this embodiment, In or Ga is introduced into the polysilicon film in the p type MIS transistor region, and the work function of the gate electrode is defined by the impurity layer containing In or Ga. Using In or Ga as described above can prevent reduction of the metal oxide film or metal silicate film used as gate insulating film. Therefore, the barrier function of the metal oxide film and the metal silicate film is maintained, and thus it is possible to prevent diffusion of the metal element in the metal silicide film into the silicon substrate. Thus, according to the embodiment, it is possible to optimize the work function of the gate electrode, without producing an adverse effect on the property and reliability of the transistor.  
         [0052]     In the above embodiment, although one of In and Ga is introduced as impurity element into the polysilicon film, both In and Ga may be introduced into the polysilicon film.  
         [0053]     Further, in the above embodiment, although Hf and Zr are mentioned as examples of the metallic element contained in the gate insulating film, the gate insulating film may contain other metallic elements. Generally, an insulating film (such as a metal oxide film and metal silicate film) containing a metallic element selected from Hf, Zr, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er and Lu can be used as gate insulating film.  
         [0054]     Further, in the above embodiment, although an Ni silicide film (NiSi film, Ni 2 Si film) is used as metal silicide film, other films may be used, such as a Pt 2 Si film, PtSi film, Pd 2 Si film, PdSi film, CO 2 Si film, CoSi film, and CoSi 2  film. Generally, it is possible to use a metal silicide film containing a metal element selected from Ni, Pd, Pt, Co, Ti, Zr and Hf.  
         [0055]     Further, in the above embodiment, although impurity elements are introduced into a polysilicon film after patterning the polysilicon film as shown in  FIGS. 5 and 6 , impurity elements may be introduced into the polysilicon film before patterning the polysilicon film.  
         [0056]     Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.