Abstract:
Systems for displaying images. The system comprises a display panel comprising a plurality of data lines DL(x), a plurality of gate lines SL(y) perpendicular to the data lines DL(x), and a pixel array coupled to the data lines and the gate lines. The pixel array comprises a first pixel P(x+1, y) coupled to the gate line SL(y+1) and the data line DL(x+1), a second pixel P(x+1, y+1) coupled to the gate line SL(y+1) and the data line DL(x+2), a third pixel P(x, y+1) coupled to the gate line SL(y+2) and the data line DL(x+1), and a fourth pixel P(x, y+2) coupled to the gate line SL(y+2) and the data line DL(x).

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1.Field of the Invention 
         [0002]    The invention relates to the display of images. 
         [0003]    2.Description of the Related Art 
         [0004]    Liquid crystal displays (LCDs) are used in a variety of applications including calculators, watches, color televisions, computer monitors, and many other electronic devices. Active matrix LCDs are a well known type of LCD. In a conventional active matrix LCD, each picture element (or pixel) is addressed using a matrix of thin film transistors (TFT) and one or more capacitors. The pixels are arranged and wired in an array having a plurality of rows and columns. For example, a SVGA display is a matrix of 2400×600 pixels. 
         [0005]    To address a particular pixel, the proper row is switched “on” (i.e., charged with a voltage), and a voltage is sent down the correct column. Since other intersecting rows are turned off, only the TFT and capacitor at the particular pixel receive a charge. In response to the applied voltage, the liquid crystal cell of the pixel changes its polarization, and thus, the amount of light reflected therefrom or passing therethrough. This process is then repeated row by row. 
         [0006]    In liquid crystal cells of a pixel, the magnitude of applied voltage determines the amount of light reflected therefrom or passing therethorugh. Due to the nature of liquid crystal material, the polarity of the voltage applied across the liquid crystal cell must alternate. Therefore, for an LCD displaying video, the voltage polarity of the liquid crystal cells is inverted (or reversed) for alternate frames of the video. This process is known as inversion. 
         [0007]    Unfortunately, if the polarity of the entire LCD is inverted with the same polarity for alternate frames, the LCD flickers at an unacceptable level. Hence, many conventional LCDs use other forms of inversion, such as line inversion or dot inversion. In line inversion, alternate columns or rows of an LCD are inverted on alternate frames (e.g., in a “striped” pattern). Dot inversion inverts alternate pixels of each row and column alternate frames (e.g., in a “checkerboard” pattern). Of the two inversion techniques, dot inversion is generally considered to produce higher display quality. 
         [0008]    However, inversion, especially dot inversion, increases power consumption of the LCD, since the data lines behave as a capacitive load (and may also include a storage capacitor), and thus, consume power as their voltages change polarity. Since LCDs are often used in battery powered or low power devices, many LCDs use driving methods optimized for power consumption. For example, many LCDs use line inversion rather than dot inversion. 
       BRIEF SUMMARY OF THE INVENTION 
       [0009]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
         [0010]    Embodiments of a system displaying images are provided, comprising a display panel. The display panel comprises a plurality of data lines DL(x), a plurality of gate lines SL(y) perpendicular to the data lines DL(x), and a pixel array coupled to the data lines and the gate lines. The pixel array comprises a first pixel P(x+1, y) coupled to the gate line SL(y+1) and the data line DL(x+1), a second pixel P(x+1, y+1) coupled to the gate line SL(y+1) and the data line DL(x+2), a third pixel P(x, y+1) coupled to the gate line SL(y+2) and the data line DL(x+1), and a fourth pixel P(x, y+2) coupled to the gate line SL(y+2) and the data line DL(x). For example, x, y can be positive integers. 
         [0011]    The invention provides another embodiment of a system displaying images, comprising a display panel. The display panel comprises first and second data lines, a first gate line perpendicular to the first and second data lines, and first and second pixels disposed in the same column to display the same color. The first and second pixels are both coupled to the first gate line and receive display data on the first and second data lines respectively. 
         [0012]    The invention provides an embodiment of a driving method of a system displaying images, in which gate lines are scanned in sequence and display data is provided to data lines in an effective display period in a frame period based on column inversion. The data lines are electrically coupled to a common voltage in a blanking period of the frame period, wherein the ratio of the blanking period to the frame period exceeds 5%. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0014]      FIG. 1  is a diagram illustrating a display panel known to the inventors. 
           [0015]      FIG. 2  shows an embodiment of a system displaying images incorporating a display panel; 
           [0016]      FIG. 3  shows a driving method of the system for displaying images; and 
           [0017]      FIG. 4  shows another embodiment of a system for displaying images. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0018]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0019]      FIG. 1  demonstrates a display panel known to the inventors for displaying images. This is not prior art for purposes of determining the patentability of the invention and merely shows a problem found by the inventors. 
         [0020]    As shown in  FIG. 1 , the display panel  100  is driven by a column inversion, but can obtain display quality as driven by a dot inversion due to pixel layout thereof. For example, the odd-numbered data lines and even-numbered data lines are provided by display data with two different polarities in each frame, and the polarities are switched frame by frame. The display panel  100  can be driven by column inversion to obtain display quality as driven by dot inversion, because the pixels in the second row, coupled to the gate line GL 2 , are each coupled to the data line disposed on the right side thereof and those coupled to the gate lines GL 1  and GL 3  are coupled to the data lines disposed on the left side thereof. 
         [0021]    As each gate line, such as GL 1 , is activated, display data of different polarities on data lines DL 1 , DL 2 , DL 3 , . . . , DL 6  is input to the pixels R 11 , G 11 , B 11 , R 21 , G 21 , B 21 . However, due to coupling effect, each pixel is affected by display data on adjacent data lines. For example, the pixel R 11  is driven by the display data with a positive polarity on the data line DL 1  and affected by the display data with a negative polarity on the adjacent data line DL 2 . The pixel G 11  is driven by the display data with a negative polarity on the data line DL 2  and affected by the display data with a positive polarity on the adjacent data line DL 3 , and so on. Thus, the pixels cannot remain at the desired voltage level due to the display data on the adjacent data line, referred to coupling noise. Low coupling noise induces effects upon each pixel because different color pixels have different driving voltage. For example, coupled noise caused by the display data with a negative polarity on the adjacent data line DL 2  has a great effect on the pixel R 11 , and so on. Because of this, brightness of pixels occurs with the lower area of the panel more serious for bright/dark line defect than the upper portion. 
         [0022]      FIG. 2  shows an embodiment of a system for displaying images that includes a display panel. As shown, the display panel  200  comprises a pixel array  210 , a scan driver  220  and a data driver  230 . The pixel array  210  comprises a plurality of data lines DL 1 , DL 2 , DL 3 , . . . , coupled to the data driver  220 , a plurality of gate lines GL 1 , GL 2 , GL 3 , . . . , coupled to the scan driver  230 , and a plurality of pixels. 
         [0023]    The data line DL 1  is coupled to the pixels R 11 , B 0 , and R 13 , the data line DL 2  is coupled to the pixels G 11 , R 12 , and G 13 , and the data line DL 3  is coupled to the pixels B 11 , G 12 , and B 13 . The data line DL 4  is coupled to the pixels R 21 , B 12 , and R 23 , the data line DL 5  is coupled to the pixels G 21 , R 22 , and G 23 , and the data line DL 6  is coupled to the pixels B 21 , G 22 , and B 23 . The data line DL 7  is coupled to the pixels R 31 , B 22 , and R 33 , and so on. 
         [0024]    The gate line GLI is coupled to the pixels R 11 , B 11 , G 21 , B 31  and so on. The gate line GL 2  is coupled to the pixels B 0 , G 11 , G 12 , R 21 , R 22 , B 21 , B 22  and so on. The gate line GL 3  is coupled to the pixels R 12 , R 13 , B 12 , B 13 , G 22 , G 23 , B 33  and so on. The gate line GL 4  is coupled to the pixels G 13 , R 23 , B 23  and so on. 
         [0025]    Namely, the gate line GL 2  is coupled to a pair of pixels G 11  and G 12  displaying green color, a pair of pixels R 21  and R 22  displaying red color, and a pair of pixels B 21  and B 22  displaying blue color. The gate line GL 3  is coupled to a pair of pixels R 12  and R 13  displaying red color, a pair of pixels B 12  and B 13  displaying blue color and a pair of pixels G 22  and G 23  displaying green color, and so on. 
         [0026]    To obtain display quality as driven by dot inversion, the display panel  200  is driven by column inversion. 
         [0027]    For example, in a current frame (as shown in  FIG. 2 ), the scan driver scans the gate lines, GL 1 , GL 2 , GL 3  and GL 4  in sequence, while the data driver provides positive polarity display data on the odd-numbered data lines DL 1 , DL 3 , DL 5  and GL 7  and negative polarity display data on the even-numbered data lines DL 2 , DL 4  and DL 6 . In the following frame (not shown), the scan driver scans the gate lines GL 1 , GL 2 , GL 3  and GL 4  in sequence, while the data driver provide negative polarity display data on the odd-numbered data lines DL 1 , DL 3 , DL 5  and GL 7  and positive polarity display data on the even-numbered data lines DL 2 , DL 4  and DL 6 . 
         [0028]    In the embodiment, when one gate line is scanned, pixels disposed on two sides of each driven gate line are not driven. For example, if gate line GL 1  is scanned by the scan driver  220 , the pixels R 11 , B 11 , G 21  and R 31  are driven and the pixels G 11 , R 21 , B 21  are not. As the gate line GL 2  is scanned by the scan driver  220 , the pixels B 0 , G 11 , G 12 , R 21 , R 22 , B 21  and B 22  are driven and the pixels R 12 , B 12 , G 22  are not. As the gate line GL 3  is scanned by the scan driver  220 , the pixels R 12 , R 13 , B 12 , B 13 , G 22 , G 23  and B 33  are driven, and pixels B 0 , G 12 , G 13 , R 22 , R 23 , B 22  and B 23  are not driven, and so on. 
         [0029]    Because each driven pixel and pixels disposed on two sides thereof are not driven at the same time, display data for the other color from adjacent data lines does not affect the driven pixel, and thus coupled noise and bright/dart line defect can be reduced. 
         [0030]      FIG. 3  shows a driving method of the system for displaying images. As shown, the wave  3 A illustrates the display panel  200  is driven by column inversion. In an effective display period EDP of the frame period FD 1 , the scan driver  220  scans all gate lines, such as GL 1 , GL 2 , GL 3  and GL 4 , in sequence, while the data driver  230  provides positive polarity display data on the odd-numbered data lines DL 1 , DL 3 , DL 5  and GL 7  and negative polarity display data on the even-numbered data lines DL 2 , DL 4  and DL 6 . Next, in a blanking period BP 1 , all data lines, DL 1 , DL 2 , DL 3  and . . . , are coupled to a common voltage (not shown), wherein the frame rate of the display panel  200  is 60 Hz. 
         [0031]    In the effective display period of the frame period FD 2 , the scan driver  220  scans the all gate lines, such as GL 1 , GL 2 , GL 3  and . . . , in sequence, while the data driver  230  provides negative polarity display data on the odd-numbered data lines DL 1 , DL 3 , DL 5  and GL 7  and positive polarity display data on the even-numbered data lines DL 2 , DL 4  and DL 6 . Next, in the blanking period BP 1 , all data lines, DL 1 , DL 2 , DL 3  and . . . , are coupled to the common voltage (not shown), wherein the ratio of the blanking period BP 1  to the frame period FD 1  or FD 2  exceeds 5%. 
         [0032]    As shown, the wave  3 B illustrates the display panel  200  driven by column inversion, in which the blanking period BP 1  is extended to half frame period FD 3  such that the frame rate is lower to 30 Hz. In an effective display period EDP of the frame period FD 1 , the scan driver  220  scans all gate lines, such as GL 1 , GL 2 , GL 3  and GL 4 , in sequence, while the data driver  230  provides positive polarity display data on the odd-numbered data lines DL 1 , DL 3 , DL 5  and GL 7  and negative polarity display data on the even-numbered data lines DL 2 , DL 4  and DL 6 . Next, in a blanking period BP 2 , all data lines, DL 1 , DL 2 , DL 3  and . . . , are coupled to a common voltage (not shown). 
         [0033]    In the effective display period of the frame period FD 2 , the scan driver  220  scans the all gate lines, such as GL 1 , GL 2 , GL 3  and . . . , in sequence, while the data driver  230  provides negative polarity display data on the odd-numbered data lines DL 1 , DL 3 , DL 5  and GL 7  and positive polarity display data on the even-numbered data lines DL 2 , DL 4  and DL 6 . Next, in the blanking period BP 1 , all data lines, DL 1 , DL 2 , DL 3  and . . . , are coupled to the common voltage (not shown). 
         [0000]    
       
         
               
             
               
               
               
             
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 shows 
               
             
          
           
               
                   
                   
                 Frame rate at 30 Hz 
               
               
                   
                   
                 with blanking period 
               
               
                   
                 Frame rate at 60 Hz 
                 half frame period 
               
             
          
           
               
                   
                   
                 New 
                   
                 New 
               
               
                   
                 Old structure 
                 structure 
                 Old structure 
                 structure 
               
               
                   
               
               
                 Upper area on 
                  ~4 mV 
                 ~44 mV 
                 ~26 mV 
                 ~22 mV 
               
               
                 panel 
               
               
                 Center area on 
                 ~48 mV 
                  ~0 mV 
                 ~48 mV 
                  ~0 
               
               
                 panel 
               
               
                 Lower area on 
                 ~91 mV 
                 ~44 mV 
                 ~69 mV 
                 ~22 mV 
               
               
                 panel 
               
               
                   
               
             
          
         
       
     
         [0034]    Table 1 shows simulated results of the voltage difference between adjacent pixels in display panels under different frame rates. In this case, the voltage difference between pixels in the same column can be regarded as coupling noise disclosed above, the display panel  100  shown in  FIG. 1  represents an old structure and the display panel  200  shown in  FIG. 2  represents a new structure. As shown, in the display panel  100 , the voltage difference between adjacent pixels in the lower area is about 91 mV. In the display panel  200 , the voltage difference between adjacent pixels in the lower area is lowered to about 44 mV. As the frame rate is lowered to 30 Hz with blanking period is half frame period, the voltage difference between adjacent pixels in the lower area of the display panel  100  is lower to about 69 mV and the voltage difference between adjacent pixels in the lower area of the display panel  200  is lower to about 22 mV. 
         [0035]    In view of this, the new pixel structure in the display panel  200  can lower coupling noise (the voltage difference between pixels in the same column) to 44 mV, and further lower it to 22 mV when cooperating with blanking period which is half frame period. 
         [0036]      FIG. 4  schematically shows another embodiment of a system for displaying images, implemented here as an electronic device  400 , comprising a display panel, such as display panel  200 . The electronic device  400  may be a digital camera, a portable DVD, a television, a car display, a PDA, notebook computer, tablet computer, cellular phone, or a display device, etc. Generally, the electronic device  400  includes a housing  410 , the display panel  200  and a DC/DC converter  420 . The DC/DC converter  420  is operatively coupled to the display panel  400  and provides an output voltage powering the display panel  400  to display images. 
         [0037]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.