Abstract:
An aqueous solution composition may include an organic base hydroxide, potassium hydroxide, a compound selected from the group of compounds consisting of 2-mercaptobenzimidazole, 1-Phenyl-1H-tetrazole-5-thiol and 2-MerCaptoBenzoThiazole, hydrogen peroxide and deionized water. A method for removing photoresist and anti-reflective coating from a wafer using such a solution is also disclosed.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to the manufacture of semiconductors. More specifically it relates to removal of etched photoresist and silicon-based and/or an organic anti-reflective coating with alkaline solutions, typically in backend of the production line of semiconductors. 
       BACKGROUND OF THE INVENTION 
       [0002]    In a typical photolithography process, a photosensitive material is spun-on to cover a wafer, and light is irradiated through a photomask onto the photosensitive layer covering the wafer and the wafer undergoes development to produce a predetermined pattern on the photoresist. The presence of an additional light absorbing material is necessitated based on the substrate or wafer that is being used and the pattern being defined. 
         [0003]    In the subsequent patterning process, a chemically reactive plasma etch is performed, wherein the pre-defined pattern on the photoresist is transferred to the substrate. This process leaves the patterned wafer with the etched photoresist, etch polymer and an anti-reflective coating (ARC) when it is used. A plasma-ash step may be included to aid in the removal of the etched photoresist during the subsequent cleans step(s). 
         [0004]    Finally, the remaining of the photoresist layer, etch polymer and the ARC layer (if used) is removed. Chemical solutions, generically called strippers may be used for removing the aforementioned materials to result in a clean patterned wafer for further processing to add the copper interconnects. 
         [0005]    Current backend of the production line of 65 nm and 90 nm process nodes utilize expensive wet chemical mixtures with high solvent composition (ranging from 40-60%) to remove resist and sacrificial antireflective (light absorbing) coating (ARC) at via and trench layers of the inter-layer dielectric (ILD) during the dual-damascene structure formation. Some of the cleans solutions include two-step processes that compound the costs and processing time for each dielectric layer in a manufacturing environment. Generally the cleans process is required to remove the desired material without significant damage to the ILD and with high degree of compatibility with exposed metals (like copper and tungsten). It is desired to minimize the solvent usage and reduce impact on waste stream from the backend fabrication cleans processes. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    In order to better understand the present invention, and appreciate its practical applications, the following Figures are provided and referenced hereafter. It should be noted that the Figures are given as examples only and in no way limit the scope of the invention. Like components are denoted by like reference numerals. 
           [0007]      FIG. 1A  is a scanning electron microscopy (XSEM) image of etched vias before being subjected to an aqueous solution according to embodiments of the present invention. 
           [0008]      FIG. 1B  is a XSEM image of etched vias after being subjected to an aqueous solution according to embodiments of the present invention. 
           [0009]      FIG. 2A  is a XSEM image of trenches in dual damascene patterning scheme before being subjected to an aqueous solution according to embodiments of the present invention. 
           [0010]      FIG. 2B  is a XSEM image of trenches in dual damascene patterning scheme after being subjected to an aqueous solution according to embodiments of the present invention (possibly without an ash process). 
           [0011]      FIG. 3A  and  FIG. 3B  are a XSEM images of dual damascene structures after etch-stop cleans (with aqueous solution according to embodiments of the present invention) showing Cu compatibility. 
           [0012]      FIG. 4  showing W compatibility of the solvent-free photoresist cleans aqueous solution according to embodiments of the present invention. 
           [0013]      FIG. 5  is a table of normalized critical dimension (CD) comparing vias and trenches that underwent a solvent-free treatment according to embodiments of the present invention with a wafer that underwent common treatment that involves solvents, in a dual damascene structure. 
           [0014]      FIG. 6  is a table of normalized defect count at the end of the patterning process, comparing a wafer that underwent a solvent-free treatment according to embodiments of the present invention with a wafer that underwent common treatment that involves solvents, in a dual damascene structure. 
           [0015]      FIG. 7  is a table comparing the ratio of various CD of the solventless cleans (according to embodiments of the present invention) to that of solvent-based cleans. 
           [0016]      FIG. 8  is a flow chart of a method for removal of photoresist and/or ARC, according to embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0017]    In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However it will be understood by those of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention. 
         [0018]    According to embodiments of the present invention a cleans process for jointly removing etched photoresist, etch polymer and antireflective coating selective to the dielectric material off an etched wafer is made possible at via and trench layers of patterning, while being copper compatible. 
         [0019]    A photoresist stripper according to embodiments of the present invention may have no solvent content. 
         [0020]    Wafer fabrication facilities (also known as FABs) which may have preferred infrastructure or equipment to support multi-step clean process can utilize much simpler and less complex chemicals involving shorter recipe times at lower temperatures, according to embodiments of the present invention. 
         [0021]    Main elements of the photoresist stripper according to embodiments of the present invention may include aqueous clean formulations which allow single step cleans substantially bringing down chemical costs and environmental foot-print. 
         [0022]    Photoresist stripper formulations according to embodiments of the present invention can offer drop-in replacement to existing integration schemes and may be compatible with inter layer dielectrics (ILDs) such as, for example, non-porous or low-porosity (7-14%) carbon doped oxide (CDO) or silicon oxide (SiO2). 
         [0023]    Photoresist stripper formulations according to the present invention may offer single step cleans with shorter process time (relatively to processes used to-date), thereby improving module output. Formulations are aqueous, which are more environmentally benign. Lower temperature processes also significantly reduce module/equipment downtime due to shorter temp-up duration. 
         [0024]    It may be desirable to avoid plasma ash cleans for removing photoresist and ARC (e.g. sacrificial light absorbing material) in the back-end of line (for, for example, copper interconnects) in the via first integration scheme to minimize both mechanical and electrical damage in the dielectric (to avoid increase in capacitance). Embodiments of the present invention may provide simplification of the chemical mixture for removing etched photoresist, etch polymer and ARC from patterned dielectrics. A photoresist removal process according to embodiments of the present invention may be subjected to constraints, which include: 
         [0025]    A) CD (critical dimensions) of via and trench structures achieved on the patterned dielectric after a solvent-free cleans process according to embodiments of the present invention, relative to current solvent-containing solutions. 
         [0026]    B) Defects (unremoved residues) achieved on the patterned dielectric after a solvent-free cleans process according to embodiments of the present invention relative to current solvent-containing solutions. 
         [0027]    C) Photoresist removal according to embodiments of the present invention may be a “Plug and play” process which may need no changes in the existing or previously developed lithography or plasma etch process. 
         [0028]    Details of experimental findings are detailed in this section: 
         [0029]    According to embodiments of the present invention, a composition of a photoresist removal solution formulation (by weight percent) is given below: 
         [0030]    1-12% TMAH (tetramethylammonium hydroxide) or other organic bases like tetraethylammonium hydroxide or tetrapropylammonium hydroxide or tetrabutylammonium hydroxide or methyltripropylammonium hydroxide or benzyltrimethylammonium hydroxide or choline hydroxide; 
         [0031]    0.05-2.5% KOH (potassium hydroxide); 
         [0032]    0-0.5% 2-Mercaptobenzimidazole CAS# 583-39-1 (MBI) or 1-Phenyl-1H-tetrazole-5-thiol or 2-MerCaptoBenzoThiazole; 
         [0033]    0-12% Hydrogen peroxide; and 
         [0034]    Rest—deionized water. 
         [0035]    Higher KOH and TMAH concentrations may give lower defects but at the cost of increasing CD&#39;s. Further, the cleaning of vias may be aided by using megasonic power at a frequency of about 900 KHz and around 800 W power and operating temperatures were in the range of 40 to 80 degrees Celsius. The mechanical power associated with the wafer spinning and/or spraying of the chemical onto the wafer may enable the via and trench cleans processes to be more efficient (e.g. lower defects with minimal damage to the dielectric). 
         [0036]      FIG. 1A  is a XSEM image of etched vias before being subjected to cleans aqueous solution according to embodiments of the present invention. 
         [0037]      FIG. 1B  is a XSEM image of etched vias after being subjected to an aqueous solution according to embodiments of the present invention. 
         [0038]      FIG. 2A  is a XSEM image of trenches in dual damascene patterning scheme before being subjected to an aqueous solution according to embodiments of the present invention. 
         [0039]      FIG. 2B  is a XSEM image of trenches in dual damascene patterning scheme after being subjected to an aqueous solution according to embodiments of the present invention (possibly without ash process in between). 
         [0040]      FIG. 3A  and  FIG. 3B  are a XSEM images of dual damascene structures after etch-stop cleans (with aqueous solution according to embodiments of the present invention) showing Cu compatibility. 
         [0041]      FIG. 4  showing W compatibility of the solvent-free photoresist cleans aqueous solution according to embodiments of the present invention. 
         [0042]    It is evident that photoresist, ARC and etch polymer removal using a solution according to embodiments of the present invention was successful in all cases. 
         [0043]      FIG. 5  is a table of normalized critical dimension (CD) comparing vias and trenches that underwent a solvent-free treatment according to embodiments of the present invention with a wafer that underwent common treatment that involves solvents, in a dual damascene structure. 
         [0044]      FIG. 6  is a table of normalized defect count at the end of the patterning process, comparing a wafer that underwent a solvent-free treatment according to embodiments of the present invention with a wafer that underwent common treatment that involves solvents, in a dual damascene structure. 
         [0045]    The tables relates to post-patterning final check critical dimensions (FCCD,  FIG. 5 ) and defects ( FIG. 6 ) on the wafer with a photoresist stripper removal solution according to an embodiment of the present invention (used for all the three cleans types, namely: post via etch, trench etch and etch stop (ES) etch (to expose the underlying Copper), compared with commonly used solution results. 
         [0046]      FIG. 7  is a table comparing the ratio of various CD (critical dimensions) of the solventless cleans (presented in this invention) to that of solvent-based cleans. Note the matching trench CD&#39;s before barrier deposition and 8% reduction of the trench CD and a concomitant increase in the resistance of the solvent-free process in the copper line, according to embodiments of the preset invention. 
         [0047]      FIG. 8  is a flow chart of a method for removal of photoresist and/or ARC, according to embodiments of the present invention. Referring to  FIG. 8 , a wafer with photoresist and ARC may be provided (operation  10 ). The wafer may be subjected to a solution according to embodiments of the present invention (operation  12 ) and the solution with the wafer inside may be agitated (operation  14 ). This may result in, for example, removing the photoresist and anti-reflective layer. 
         [0048]    Very good performance results for photoresist removal solution according to embodiments of the present invention that may yield desirable photoresist removal results can fall under the following range: 
         [0049]    1-12% TMAH (tetramethylammonium hydroxide) or other organic bases like tetraethylammonium hydroxide or tetrapropylammonium hydroxide or tetrabutylammonium hydroxide or methyltripropylammonium hydroxide or benzyltrimethylammonium hydroxide or choline hydroxide; 
         [0050]    0.05-2.5% KOH (potassium hydroxide); 
         [0051]    0-0.5% 2-Mercaptobenzimidazole CAS# 583-39-1 (MBI) or 1-Phenyl-1H-tetrazole-5-thiol or 2-MerCaptoBenzoThiazole; 
         [0052]    0-12% Hydrogen peroxide; 
         [0053]    Rest—deionized water. 
         [0054]    One embodiment of the present invention includes the following: 
         [0055]    Via treatment at a temperature range of 40 to 70 degrees Celsius, treatment duration of 10 to 50 minutes, megasonic energy/agitation at about 900 kHz and 800 W power and/or mechanical agitation associated with wafer spinning and chemical spray. 
         [0056]    Trench treatment at a temperature range of 40 to 80 degrees Celsius, duration of 10 to 50 minutes, with above-mentioned agitation conditions. 
         [0057]    Etch stop treatment at a temperature range of 40 to 60 degrees Celsius, duration of 3 to 8 minutes. 
         [0058]    The above parameter information is given for explanatory purposes relating to the examples discussed hereinabove and in no way limit the scope of the present invention. 
         [0059]    Another aspect of solventless (e.g. aqueous) cleans discovered here is that the patterned dielectric is more immune towards the damages caused by the physical vapor deposition-based tantalum barrier deposition process. This is noted by the smaller increase in the CD of the features before and after the deposition of the barrier in the aqueous cleans when compared against that of a solvent-based cleans. 
         [0060]    Although it may be desirable to avoid plasma ash cleans for removing photoresist and ARC, a process for the removal of photoresist and ARC involving the use of a solution according to embodiments of the present invention can be also involve a plasma-ash step as well. 
         [0061]    While the invention has been described with respect to a limited number of embodiments, it will be appreciated that many variations, modifications and other applications of the invention may be made. Embodiments of the present invention may include other apparatuses for performing the operations herein. The appended claims are intended to cover all such modifications and changes.