Abstract:
A novel transistor structure and method for fabrication the same. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. The method for fabricating the transistor structure starts out with a planar semiconductor layer and a gate stack on top of the semiconductor layer. Then, top regions of the semiconductor layer on opposing sides of the gate stack are removed. Then, regions beneath the removed regions are doped to form lowered S/D regions of the transistor structure

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Technical Field  
         [0002]     The present invention relates to semiconductor transistors, and more particularly, to lowered source/drain semiconductor transistors.  
         [0003]     2. Related Art  
         [0004]     A typical semiconductor transistor comprises a channel region and first and second source/drain (S/D) regions formed in a semiconductor layer, wherein the channel region is disposed between the first and second S/D regions. The typical semiconductor transistor further comprises a gate stack (that includes a gate dielectric region directly on top the channel region and a gate region on top of the gate dielectric region) directly above the channel region. In addition, first and second gate spacers are formed on sidewalls of the gate stack so as to define the first and second S/D regions, respectively. The capacitance between the gate region and the first S/D region has several components one of which is defined by a path from the gate region to the first S/D region through the first gate spacer. This capacitance component is usually referred to as the out-fringing capacitance. For example, the out-fringing capacitance between the gate region and the second S/D region is defined by a path from the gate region to the second S/D region through the second gate spacer.  
         [0005]     It is desirable to minimize the out-fringing capacitances between the gate region and the first and second S/D regions in order to increase transistor performance or to reduce transistor switching time. Therefore, there is a need for a novel transistor structure in which the out-fringing capacitances between the gate region and the first and second S/D regions are relatively less than those of the prior art. There is also a need for a method for fabricating the novel transistor structure.  
       SUMMARY OF THE INVENTION  
       [0006]     The present invention provides a semiconductor structure, comprising (a) a semiconductor layer including a channel region and first and second source/drain regions, wherein the channel region is disposed between the first and second source/drain regions, and wherein top surfaces of the first and second source/drain regions are below a top surface of the channel region; (b) a gate dielectric region on the channel region; and (c) a gate region on the gate dielectric region, wherein the gate region is electrically isolated from the channel region by the gate dielectric region.  
         [0007]     The present invention also provides a method for fabricating a semiconductor structure, the method comprising the steps of (a) providing a semiconductor layer and a gate stack on the semiconductor layer, wherein the semiconductor layer comprises (i) a channel region directly beneath the gate stack and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions; (b) removing the first and second semiconductor regions; and (c) doping regions directly beneath the removed first and second semiconductor regions so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region.  
         [0008]     The present invention also provides a method for fabricating a semiconductor structure, the method comprising the steps of (a) providing (i) an underlying dielectric layer, (ii) a semiconductor layer on the underlying dielectric layer, and (iii) a gate stack on the semiconductor layer; (b) implanting first dopants in a top layer of the underlying dielectric layer except in a separating dielectric region of the top layer directly beneath the gate stack; (c) removing the top layer of the underlying dielectric layer except the separating dielectric region; (d) epitaxially growing semiconductor regions to fill the removed top layer of the underlying dielectric layer; and (e) implanting second dopants in semiconductor regions of the semiconductor layer and the epitaxially grown semiconductor regions on opposing sides of the gate stack so as to form first and second source/drain regions such that the separating dielectric region is disposed between the first and second source/drain regions.  
         [0009]     The present invention provides a novel transistor structure in which the out-fringing capacitances between the gate region and the first and second S/D regions are relatively less than those of the prior art. The present invention also provides a method for fabricating the novel transistor structure. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]      FIGS. 1A-1K  show cross-section views of a semiconductor structure used to illustrate a method of fabricating semiconductor structures, in accordance with embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0011]      FIGS. 1A-1K  show cross-section views of a semiconductor structure  100  used to illustrate a method of fabricating semiconductor structures, in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , in one embodiment, the method starts out with an SOI (silicon on insulator) substrate  110  comprising, illustratively, a silicon layer  110   a , an underlying dielectric layer  110   b  (usually referred to as BOX, i.e., buried oxide layer) on top of the silicon layer  110   a , and another silicon layer  110   c  on top of the underlying dielectric layer  110   b . Starting from  FIG. 1B , the silicon layer  110   a  is omitted for simplicity.  
         [0012]     Next, in one embodiment, the method comprises the step of forming a gate dielectric layer  120  on top of the silicon layer  110   c . In one embodiment, the gate dielectric layer  120  can comprise silicon dioxide and can be formed by thermally oxidizing a top surface  112  of the silicon layer  110   c.    
         [0013]     Next, in one embodiment, a gate layer  130  is formed on top of the gate dielectric layer  120 . In one embodiment, the gate layer  130  can comprise poly-silicon. Next, in one embodiment, a hard mask dielectric layer  140  is formed on top of the poly-silicon layer  130 . In one embodiment, hard mask dielectric layer  140  can comprise silicon dioxide and can be formed by, illustratively, chemical vapor deposition (i.e., CVD). Then, in one embodiment, a photoresist layer  150  is formed on top of the hard mask dielectric layer  140 .  
         [0014]     Next, in one embodiment, the photoresist layer  150  is patterned to become the patterned photoresist layer  150 ′ by, illustratively, photolithography (i.e., the regions of the photoresist layer  150  represented by the dashed lines are removed).  
         [0015]     Next, in one embodiment, the patterned photoresist layer  150 ′ can be used as a mask to etch the hard mask dielectric layer  140  and then the gate layer  130  so as to form the hard mask dielectric region  140 ′ and the gate region  130 ′, respectively. In other words, the regions of the hard mask dielectric layer  140  and the gate layer  130  represented by the dashed lines are removed.  
         [0016]     Next, with reference to  FIG. 1B , in one embodiment, the method proceeds with an implantation step of using the regions  130 ′,  140 ′, and  150 ′ as a mask to implant nitrogen in a top layer  114  of the underlying dielectric layer  110   b . As a result, regions  114   a  and  114   b  of the top layer  114  are doped with nitrogen except for a separating dielectric region  114   c  directly beneath the regions  130 ′,  140 ′, and  150 ′. In general, any dopants can be used here instead of nitrogen provided that the doped regions  114   a  and  114   b  doped with the dopants can be later etched away (i.e., removed) essentially without affecting the other regions of the underlying dielectric layer  110   b.    
         [0017]     Next, with reference to  FIG. 1C , in one embodiment, the patterned photoresist layer  150 ′ ( FIG. 1B ) can be removed, and a nitride layer  150  can be blanket-deposited on top of the structure  100 .  
         [0018]     Next, with reference to  FIG. 1D , in one embodiment, the method can proceed with an anisotropic etching step that removes most of the nitride layer  150  and leaves nitride spacers  150   a  and  150   b  on sidewalls of the gate stack  130 ′, 140 ′ (that comprises the gate region  130 ′ and the hard mask dielectric region  140 ′). In one embodiment, the anisotropic etching step can be RIE (Reactive Ion Etching). Next, in one embodiment, an oxide (e.g., SiO 2 ) layer  160  can be blanket-deposited on the structure  100  by, illustratively, CVD.  
         [0019]     Next, in one embodiment, the gate stack  130 ′, 140 ′ can be used as a mask to implant germanium in a top layer  116  of the silicon layer  110   c . As a result, doped regions  116   a  and  116   b  of the top layer  116  are doped with germanium except for a region  116   c  directly beneath the gate stack  130 ′, 140 ′. In general, any dopants can be used here instead of germanium provided that the resulting silicon regions  116   a  and  116   b  doped with the dopants can be later etched away essentially without affecting the other regions of the silicon layer  110   c.    
         [0020]     Next, with reference to  FIG. 1E , in one embodiment, nitride spacers  170   a  and  170   b  can be formed on sidewalls of the gate stack  130 ′, 140 ′ (that now includes a portion of the oxide layer  160  that covers the gate stack  130 ′, 140 ′). In one embodiment, the nitride spacers  170   a  and  170   b  can be formed by blanket-depositing a nitride layer (not shown) on top of the structure  100  and then etching back.  
         [0021]     Next, in one embodiment, the method proceeds with an implantation step (represented by arrow  117   a ′) of implanting germanium in the silicon layer  110   c  at an angle such that the resulting doped region  117   a  is deeper than the doped region  116   a  and extends under the nitride spacer  170   a . Then, in one embodiment, the method proceeds with an implantation step (represented by arrow  117   b ′) of implanting germanium in the silicon layer  110   c  at an angle such that the resulting doped region  117   b  is deeper than the doped region  116   b  and extends under the nitride spacer  170   b . The arrows  117   a ′ and  117   b ′ also indicate the respective directions of germanium bombardments.  
         [0022]     Next, in one embodiment, the method proceeds with an implantation step (represented by arrow  118 ) of implanting germanium vertically in the silicon layer  110   c  such that the resulting doped regions  118   a  and  118   b  are deeper than the doped regions  117   a  and  117   b , respectively. The arrow  118  also indicates the direction of germanium bombardment. Starting from  FIG. 1F , the doped regions  116   a ,  117   a , and  118   a  are collectively referred to as the doped region  119   a . Similarly, the doped regions  116   b ,  117   b , and  118   b  are collectively referred to as the doped region  119   b.    
         [0023]     Next, with reference to  FIG. 1F , in one embodiment, oxide spacers  180   a  and  180   b  are formed on sidewalls of the nitride spacers  170   a  and  170   b , respectively. In one embodiment, the oxide spacers  180   a  and  180   b  can be formed by blanket-depositing an oxide layer (not shown) on top of the structure  100  and then etching back. As a result, a top region of the oxide layer  160  is etched away, and the nitride spacers  160   a  and  160   b  are exposed to the atmosphere. Also as a result, the doped regions  119   a  and  119   b  are exposed to the atmosphere. The oxide layer  160  is reduced to the oxide regions  160   a  and  160   b . The gate dielectric layer  120  is reduced to gate dielectric region  120 ′.  
         [0024]     Next, with reference to  FIG. 1G , in one embodiment, the method proceeds with an etching step of anisotropically etching away (illustratively, using RIE) silicon regions exposed to the atmosphere while leaving essentially intact other regions comprising other materials such as oxide and nitride. As a result, regions  119   a  and  119   b  of the silicon layer  110   c  are removed.  
         [0025]     Next, in one embodiment, the nitrogen-doped regions  114   a  and  114   b  can be removed by a wet-etching process which essentially affects only nitrogen-doped oxide material and essentially does not affect other materials such as nitride, silicon, and undoped oxide.  
         [0026]     Next, with reference to  FIG. 1H , in one embodiment, silicon is epitaxially grown from the silicon layer  110   c  (including the doped regions  119   a  and  119   b ) to top surfaces  192   a  and  192   b.    
         [0027]     Next, in one embodiment, the resulting silicon layer  110   c  is anisotropically etched back (illustratively, using RIE) to top surfaces  194   a  and  194   b , respectively. In one embodiment, the top surfaces  194   a  and  194   b  of the resulting silicon layer  110   c  after etching back are below the bottom surfaces  195   a  and  195   b  ( FIG. 1G ) of the germanium-doped regions  119   a  and  119   b , respectively.  
         [0028]     Next, in one embodiment, an anneal process can be performed to diffuse germanium in the germanium-doped regions  119   a  and  119   b  into the silicon layer  110   c.    
         [0029]     Next, with reference to  FIG. 1I , in one embodiment, the germanium-doped regions  119   a  and  119   b  ( FIG. 1H ) of the silicon layer  110   c  can be removed (illustratively, by wet etching) while leaving essentially intact other regions of the silicon layer  110   c  that are not doped with germanium.  
         [0030]     Next, in one embodiment, an S/D implantation step can be performed to form S/D regions  210   a  and  210   b  in the silicon layer  110   c . In one embodiment, an S/D anneal step can be performed after the S/D implantation step.  
         [0031]     Next, with reference to  FIG. 1J , in one embodiment, the method proceeds with a step of anisotropically etching (illustratively, using RIE) the exposed nitride regions  150   a ,  150   b ,  170   a , and  170   b  ( FIG. 1I ). As a result, the nitride spacers  170   a  and  170   b  are removed. The nitride regions  150   a  and  150   b  are thin and protected by surrounding oxide regions  160   a ,  160   b , and  140 ′ ( FIG. 1I ). As a result, the etch rate for the nitride regions  150   a  and  150   b  is much slower than that for the nitride spacers  170   a  and  170   b . Therefore, when the nitride spacers  170   a  and  170   b  are completely removed, the nitride regions  150   a  and  150   b  can be almost intact.  
         [0032]     Next, in one embodiment, the method proceeds with a step of anisotropically etching (illustratively, using RIE) the exposed oxide regions  160   a ,  160   b , and  140 ′ ( FIG. 1I ). As a result, the hard mask dielectric region  140 ′ is removed, while the oxide regions  160   a  and  160   b  are reduced to the oxide spacers  160   a ′ and  160   b ′, respectively.  
         [0033]     Next, in one embodiment, a halo implantation step (represented by an arrow  220   a ′) can be performed to form a halo region  220   a . Next, in one embodiment, another halo implantation step (represented by an arrow  220   b ′) can be performed to form a halo region  220   b . The arrows  220   a ′ and  220   b ′ also indicate the respective directions of halo ion bombardments.  
         [0034]     Next, in one embodiment, an extension implantation step (represented by arrows  230 ) can be performed to form extension regions  230   a  and  230   b . The arrow  230  also indicates the direction of extension ion bombardments.  
         [0035]     Next, in one embodiment, a halo and extension anneal step can be performed to anneal the resulting halo regions  220   a  and  220   b  and the resulting extension regions  230   a  and  230   b.    
         [0036]     Next, with reference to  FIG. 1K , in one embodiment, oxide spacers  240   a  and  240   b  are formed on sidewalls of the oxide spacers  160   a ′ and  160   b ′, respectively. In one embodiment, the oxide spacers  240   a  and  240   b  can be formed by blanket-depositing an oxide layer (not shown) on top of the structure  100  and then etching back. Now, the gate region  130 ′ and the gate dielectric region  120 ′ can be collectively referred to as the gate stack  120 ′, 130 ′ of the structure  100 .  
         [0037]     In summary, the method for forming lowered S/D transistor  100  starts out with a planar silicon layer  110   c  ( FIG. 1A ). Then, the silicon regions  119   a  and  119   b  ( FIG. 1H ) are doped with germanium so that they can be removed later ( FIG. 1I ) without affecting other silicon regions of the silicon layer  110   c . As a result, the transistor  100  ( FIG. 1K ) has lowered S/D regions  210   a  and  210   b  (i.e., top surfaces  212   a  and  212   b  of the S/D regions  210   a  and  210   b , respectively, are lower than a top surface  242  of the channel region  240 ). Considering a path from the gate region  130 ′ to the S/D region  210   a  through the nitride spacer  150   a , the oxide spacers  160   a ′ and  240   a , because of the lowered S/D region  210   a , the path is extended when it goes through the oxide spacer  240   a . As a result, the out-fringing capacitance between the gate region  130 ′ to the S/D region  210   a  is reduced. For a similar reason, the out-fringing capacitance between the gate region  130 ′ and the S/D region  210   b  is also reduced.  
         [0038]     To form the separating dielectric region  114   c  ( FIG. 1C ), the oxide regions  114   a  and  114   b  of the underlying dielectric layer  110   b  are doped with nitrogen so that the oxide regions  114   a  and  114   b  can be later removed ( FIG. 1G ) and replaced by epi-silicon (epi=epitaxially grown) as shown in  FIG. 1H . As a result, the separating dielectric region  114   c  is disposed between the S/D regions  210   a  and  210   b  ( FIG. 1K ). Because of the separating dielectric region  114   c , the channel region  240  (immediately beneath the gate dielectric region  120 ′) is thinner. As a result, short channel effects are improved.  
         [0039]     While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.