Abstract:
Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is continuation application that is based on and derives the benefit of the filing date of U.S. patent application Ser. No. 14/453,352 that claims the benefit of the filing dates of U.S. Provisional Patent Application No. 61/864,151, filed Aug. 9, 2013 and U.S. Provisional Patent Application No. 61/864,212, filed Aug. 9, 2013, the contents of all three patent application are incorporated herein by reference in their entirety. 
     
    
     BACKGROUND 
       [0002]    In order to expose a semiconductor substrate during manufacture of an integrated circuit (IC), the substrate may be chucked on an imaging scanner or camera. During chucking, the wafer can be thought of as a “pancake” that is able to “wrinkle”, resulting in significant distortion of images projected onto the wafer. This impacts overall performance when aligning multiple lithographic layers in integrated circuit manufacturing. 
       SUMMARY 
       [0003]    Embodiments described herein relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0004]    A detailed description of several embodiments will now be provided, taken in conjunction with the accompanying drawings, of which: 
           [0005]      FIG. 1  is a simplified diagram of chuck pins and a semiconductor substrate; 
           [0006]      FIG. 2  is a schematic illustration of a process according to an embodiment; 
           [0007]      FIG. 3  is a schematic diagram of apparatus according to an embodiment; 
           [0008]      FIG. 4  is a chart illustrating semiconductor substrate materials and corresponding etchants; 
           [0009]      FIG. 5  is a schematic illustration of apparatus according to an embodiment; 
           [0010]      FIG. 6  is a schematic illustration of a process according to an embodiment; and 
           [0011]      FIG. 7  is a schematic illustration of roughness associated with a backside of a semiconductor substrate. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    Typically in IC manufacturing, the backside of semiconductor substrates may be contaminated during processing. The contamination may include residual films and organic and inorganic particles. Such contamination may result from many steps in the manufacturing process such as thermal material growth, e.g., growing SiN or SiO 2  films, photoresist processing, rapid thermal annealing and/or chemical vapor deposition (CVD). In addition, the backside substrate surface may also become scratched due to wafer handling such as by robotic arms during wafer transfers from tool to tool. 
         [0013]    The condition of the wafer backside may play a significant role in the final wafer distortion signature that results during chucking on an imaging scanner or camera.  FIG. 1  shows contact areas, such as chuck pins  100 , and wafer stage  102  receiving semiconductor substrate  104 . Particles  106  are attached to the back surface of semiconductor substrate  104 . The interaction between the backside surface of substrate  104  and chuck pins  100  determines how substrate  104  will slip across pins  100 . When the backside of substrate  104  is not uniform, such as when particles  106  are present or surface unevenness exists, substrate  104  slips differently at each pin  100 , resulting in non-uniform substrate distortions. Non-uniform substrate distortions are undesirable because such distortions may result in poor overlay performance. 
         [0014]    To improve distortion uniformity and, perhaps, improve overlay performance, the backside surface of semiconductor substrate  104  which contacts chuck pins  100  may be texturized to produce a more uniform wafer distortion due to wafer slippage on the chuck. The backside of semiconductor substrate  104  is texturized to produce a smaller coefficient of friction which improves the slippage uniformity across the backside of the semiconductor substrate  104  during scanner chucking. 
         [0015]      FIG. 2  illustrates a process for improving distortion uniformity according to an embodiment. A lot of substrates  200  are texturized at  202  and then undergo photoresist processing at  204 . Photoresist processing  204  may include photoresist coating and baking a top surface of each substrate  200 . Texturizing  202  and photoresist processing  204  may be performed with a wafer track system  206 . 
         [0016]    Subsequent to photoresist processing  204 , each semiconductor substrate  200  may be exposed  208  in a scanner for which each substrate  200  may be chucked on chuck pins  100 . Then each semiconductor substrate  200  undergoes further photoresist processing  210  to develop the photoresist. Next, at  212 , overlay metrology is performed, such as, for example, using an Archer tool. Subsequent processing may then be performed at  214  such as, for example, etching. 
         [0017]    Prior to texturizing  202 , the contact areas, e.g., chuck pins  100 , of the photolithographic tool employed at exposing  208 , may be determined. The texture of the backside of one or more substrates in lot  200  may be determined. As explained in more detail below, the determining may be based at least in part on the frequency of backside features at one or more portions of the semiconductor substrate, the amplitude of the backside features at one or more portions of the semiconductor substrate, and/or a size of the one or more contact areas. The determining may employ a microscopy tool including a computer having a processor and a computer readable, non-transitory medium, such as a memory. The memory may store program instructions for causing the processor to control the microscopy tool to determine backside surface texturing. 
         [0018]    Texturizing  202  of the substrate backside may be accomplished chemically, mechanically or with a plasma process. Optionally, as a preliminary process, the backside of the substrate may be cleaned to remove contamination, such as particles or residual films. Texturizing  202  modifies the surface of the substrate to achieve a smaller and uniform coefficient of friction as compared to a substrate where the backside has not been texturized. A smaller and more uniform coefficient of friction may yield more uniform wafer distortion signatures during chucking and thus improves overlay performance during subsequent lithography level stacking. 
         [0019]      FIG. 3  illustrates apparatus to improve distortion uniformity according to an embodiment. Semiconductor substrates in lot  300  are provided to etcher  302  which texturizes the backside of the substrate. As noted above, the substrates may first be provided to a cleaning station to clean the substrate backsides or cleaning may occur in etcher  302  or cleaning may occur in etcher  302 . Subsequent to etcher  302 , the substrates  300  may be provided to photoresist coater/oven  304 . In coater/oven  304 , photoresist material is applied to the top side of the substrate and baked thereon. Etcher  302  and coater/oven  304  may be parts of wafer track system  306 . 
         [0020]    Substrates with the photoresist layer may then be exposed in scanner  308  for which each substrate  300  may be chucked on chuck pins  100 . Then, substrates are passed to photoresist developer  310 . After the photoresist has been developed, the substrate may be passed to an overlay metrology tool  312 , such as an Archer tool, for measurements to be made. Subsequently, each substrate is passed for subsequent processing  314 . 
         [0021]    As noted above, texturizing  202  may be accomplished chemically. Thus, etcher  302  may be a chemical etcher. The chemical etchant employed depends upon the material to be removed. Texturizing  202  may include treatment with an etchant to remove unwanted residual films, such as silicon nitride, oxide, etc.; an etchant to remove silicon in a manner that texturizes the substrate backside; or a combination of both. Etchants that can be used to etch silicon substrate and/or materials on the substrate backside are listed in  FIG. 4 .  FIG. 4  provides examples of materials to be etched and corresponding etchants, but a list of possible substrate materials and corresponding etchants is not limited to those identified in  FIG. 4 . Those of ordinary skill in the art know of other substrate materials and etchants that may be employed. For example, other substrate materials may include GaAs, sapphire, gadolinium gallium garnet (GGG) and lithium niobate. A combination of two or more chemicals may be used to control the etch rate for a substrate which, in turn, determines the resulting geometry for the surface, such as whether the surface is pitted or smooth. 
         [0022]    In addition to etching, another way to change the coefficient of friction of the substrate backside is to chemically change the material characteristics or properties at an atomic level. The use of vapor treatment such as HMDS (Hexamethyldisilazane) or other vapor treatments, well known to those skilled in the art, that react with the substrate backside surface may be employed. For example, the etchants listed in  FIG. 4 , in more dilute form, may also chemically alter the substrate backside. By chemically changing the surface, different surface energy and friction properties may be achieved, changing the interaction of the substrate with the chuck pins  100  on the scanner stage  102 . 
         [0023]    Texturizing  202  may alternatively include a plasma or dry etcher  302 . As with chemical etching, the purpose is to remove unwanted residual films; etch silicon in a manner that texturizes the wafer surface; or a combination of both. 
         [0024]    Alternatively, texturizing  202  may be accomplished by polishing.  FIG. 5  illustrates apparatus to improve distortion uniformity employing a polisher. Semiconductor substrates in lot  500  are provided to polisher  502  which texturizes the backside of the substrate. As noted above, the substrates may first be provided to a cleaning station to clean the substrate backsides. Subsequent to polisher  502 , the substrates may be provided to photoresist coater/oven  504 . In coater/oven  504 , photoresist material is applied to the top side of the substrate and baked thereon. Polisher  502  and coater/oven  504  may be parts of wafer track system  506 . 
         [0025]    Substrates with the photoresist layer may then be exposed in scanner  508  for which each substrate  500  may be chucked on chuck pins  100 . Then, substrates are passed to photoresist developer  510 . After the photoresist has been developed, the substrate may be passed to an overlay metrology tool  512 , such as an Archer tool, for measurements to be made. Subsequently, each substrate is passed for subsequent processing  514 . 
         [0026]    Polisher  502  may include a rotating polishing brush that scrubs/scratches the substrate backside to remove contamination and create a desired texture. The head of rotating polishing brush may include a surface which contacts the substrate with diamond particles embedded therein. Those of ordinary skill in the art will understand that any appropriate hard material may be employed to contact the substrate backside. As an alternative to diamond particles, silicon carbide may also be employed. 
         [0027]    The polishing brush may contact the wafer in a dry state. Alternatively, a slurry material may be added during the polishing process. The slurry may include an abrasive. Alternatively, chemical agents, such as HDMS, TMAH or any of the etchants listed in  FIG. 4  may be employed during the polishing process. 
         [0028]      FIG. 6  illustrates a process alternative to  FIG. 2  for improving distortion uniformity. Elements  600 - 614  may be similar to elements  200 - 214  in  FIG. 2  and therefore a description will not be repeated. Once overlay metrology measurements have been taken at  612 , the measurements may be employed to create an overlay model  616  that corrects for overlay signatures. The overlay model  616  is employed to modify the exposure at  608  to compensate for the overlay signatures. This feedback process may be repeated, for example, every 10 to 12 lots of substrates. 
         [0029]      FIG. 7  represents a schematic illustration of texturing on a substrate backside. Texturing provides a controlled degree of roughness. The roughness may be described as a series of valleys and ridges in the substrate. The roughness may be characterized by amplitude A, representing the vertical distance from a valley to a peak, and a period λ, which indicates a peak-to-peak distance. The roughness may also be characterized by the uniformity of the amplitude and/or period over the area of the substrate backside. Atomic Force Microscopy (AFM) may be employed to measure or quantify these metrics. The microscopy tool may be controlled by a computer including a processor and a computer readable, non-transitory medium, such as a memory. The memory may store program instructions for causing the processor to control the microscopy tool to determine backside surface texture based on more or more of the parameters discussed above and/or the size of the contact areas of the photolithography tool. 
         [0030]    Optimum texturing characteristics is dictated by the interaction of the semiconductor substrate  104  and chuck pins  100  on scanner  102 . The interaction between the substrate  104  backside and chuck pins  100  as a vacuum is applied during chucking is primarily determined by the coefficient of friction that exists between the two surfaces. In general, the coefficient of friction becomes higher as the backside of the substrate  104  becomes both smoother and less smooth from an optimal range. A higher coefficient of friction results in larger distortion levels. Furthermore, the uniformity of the coefficient of friction across the wafer may impact the uniformity of substrate slippage which also affects distortion. Larger non-uniformity may result in substrate distortion which has greater variability across the substrate, which leads to worsened overlay performance. 
         [0031]    In general, the backside of the semiconductor is textured to impact the effective contact surface area between chuck pins  100  and substrate  104 . In general, an optimal range may exist for the period λ of the texturing. If the period λ of the texturing is too small, the substrate  104  backside may touch the chuck pins  100  at too many locations to minimize the coefficient of friction. If the period λ becomes too large, the number of touch points between the substrate  104  and the chuck pins  100  may become so small that the substrate  104  catches on the chuck pins  100 , increasing the coefficient of friction. The amplitude A of the texture on the wafer backside may also play a role in determining the coefficient of friction, particularly when taking into consideration the surface roughness of the chuck pins  100  themselves. Therefore, an embodiment can also involve characterization of the texture amplitude A to minimize the coefficient of friction. 
         [0032]    In one embodiment, the backside texture may have an amplitude A that is within 50 nm across at least a portion of the backside of the substrate. 
         [0033]    Typically, chuck pins  100  may have a diameter on the order of 150 microns. The coefficient of friction may be minimized if the period λ of the texturizing is smaller than the width of each contact pin  100 . The coefficient of friction may be minimized if 5-20 touch points exist between the backside surface and each chuck pin  100 . The period λ of the texturing may be ⅕ to 1/10 of the width of each chuck pin  100 . The backside features may contact each chuck pin at a frequency of no more than 70 contacts per millimeter. Alternatively, the backside features may contact each chuck pin at a frequency of 5-10 contacts per micron. 
         [0034]    In one embodiment, the amplitudes A of the backside features may be within 10 nm distribution of each other. 
         [0035]    In other embodiments, the amplitude, period and/or uniformity requirements listed above may be combined together, used individually, or used collectively while omitting one or more of the requirements. 
         [0036]    Although several embodiments have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the described embodiments without materially departing from the novel teachings of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined by the following claims.