Abstract:
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a first detected data signal in response to (i) one or more first voltages, (ii) one or more second voltages, and (iii) a first reference voltage having a first common mode offset. The second circuit may be configured to present a second detected data signal in response to (i) said one or more first voltages, (ii) said one or more second voltages, and (iii) a second reference voltage having a second common mode offset.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a detection circuit generally and, more particularly, to a differential signal detection circuit. 
     BACKGROUND OF THE INVENTION 
     Referring to FIG. 1, a circuit  10  illustrates such a conventional approach for implementing a detection circuit. The circuit  10  generally comprises a number of comparators  12   a - 12   n , a number of resistors  14   a - 14   n , a number of capacitors  16   a - 16   n  and an inductor  18 . 
     The circuit  10  detects signals primarily through signal peak detection. Input signals are not detected differentially, but compared the positive input transitions with an externally set common mode offset voltage. The capacitor  16   n  is charged when valid signals are present and discharge through a bleed resistor. 
     Referring to FIG. 2, a circuit  40  is shown illustrating another conventional detection circuit. The circuit  40  generally comprises a detector logic block  42 , a comparator  44 , a comparator  46  and a voltage offset current stealing circuit  48 . The circuit  40  takes advantage of current stealing to set a trip threshold level. An offset voltage is created between the gates of a differential pair in the stealing circuit. The stealing circuit differential pair is matched to the comparator differential pair, and their drains are connected together. When the voltages at the comparator inputs are equal, the currents through them are unequal by the amount taken by the stealing circuit. A trip point threshold is reached when comparator inputs are unequal by the offset voltage at the stealing circuit. The currents into the comparator differential pair will become equal. As the comparator voltage increases beyond the offset voltage, the output state of the comparator will change. 
     The circuit  10  uses discrete components which can false trigger with common mode noise. The circuit  40  requires separate differential pairs to create the threshold and comparison circuits. The differential pairs are required to match (or track) each other over process and temperature variations. The currents setting the threshold could be small and difficult to control. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a first detected data signal in response to (i) one or more first voltages, (ii) one or more second voltages, and (iii) a first reference voltage having a first common mode offset. The second circuit may be configured to present a second detected data signal in response to (i) said one or more first voltages, (ii) said one or more second voltages, and (iii) a second reference voltage having a second common mode offset. 
     The objects, features and advantages of the present invention include providing a differential signal detection circuit that may (i) use a plurality of independent comparators to detect valid serial differential data amplitudes, (ii) dynamically adjust threshold trip points based on input common mode voltage and/or (iii) implement post detection OR functions to detect any phase combination of valid data. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
     FIG. 1 is a circuit diagram of a conventional detection circuit; 
     FIG. 2 is a circuit diagram of a conventional detection circuit; 
     FIG. 3 is a block diagram of a preferred embodiment of the present invention; 
     FIG. 4 is a block diagram of an example of the differential pair of FIG. 3; 
     FIG. 5 is a circuit diagram of an example of the differential pair of FIG. 3; and 
     FIG. 6 is a timing diagram showing the various waveforms of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention may (i) detect high speed differential data transitions and (ii) indicate signal activity after a period of time. The present invention may also indicate signal loss after a predetermined period of time. The present invention may implement, in one example, two sets of differential pairs. Each set may have either a positive or negative common mode offset produced by forcing current through resistors connected between the differential pair bases. Input signals which exceed these offset common mode voltages may be considered valid data. Valid differential data may be essentially peak detected with the differential values summed. A signal detect indication is produced once the sum exceeds a CML voltage level threshold. 
     In one example, four separate comparators with separate threshold trip points may be dynamically adjusted for common mode variation. A post detection OR may detect valid opposite phase signals. The output may be re-compared against valid CML level voltage thresholds by filtering the inputs of a CML-CMOS level translator producing the detected signal. The threshold trip levels may be user adjustable through an input pin (e.g., to three different levels). The present invention may be implemented to allow factory adjustments to the three levels. 
     Referring to FIG. 3, a block diagram of a circuit  100  is shown in accordance with a preferred embodiment of the present invention. The circuit  100  generally comprises an input section (or circuit)  102  and an output section (or circuit)  104 . The input section  102  generally comprises a differential pair set  106  and a differential pair set  108 . In one example, the differential pair sets  106  and  108  may each comprise two differential pairs. However, other numbers of differential pairs may be implemented accordingly to meet the design criteria of a particular implementation. 
     The differential pair set  106  may have an input  110  that may receive a signal (e.g., LCM_HI), an input  112  that may receive a signal (e.g., INN) and an input  114  that may receive a signal (e.g., INP). The differential pair set  108  may have an input  116  that may receive a signal (e.g., LCM_LO), an input  118  that may receive the signal INN and an input  120  that may receive the signal INP. The differential pair set  106  may have an output  122  and an output  124 . The differential pair set  108  may have an output  126  and an output  128 . The differential pair sets  106  and  108  may present signals to a logic gate  130 . The logic gate  130  may present a single ended output  132  and a single ended output  134 . 
     The output section  104  may have an input  136  that may receive the signal from the output  132  and an input  138  that may receive the signal from the output  134 . The output section  104  generally comprises a peak detection circuit  140  and a level conversion (or shifter) circuit  142 . In one example, the level conversion circuit  142  may be a CML-to-CMOS level shifter. The shifter circuit  142  generally presents a signal (e.g., OUT) and an output  144 . 
     Referring to FIG. 4, a diagram of the input section  102  is shown. The differential pair set  106  and the differential pair set  108  are shown generically presenting a multi-bit signal at an output  125  and an output  127 , respectively. The output  125 , may represent the complimentary outputs  122  and  124  illustrated in FIG. 3 or another similar multi-bit output. Similarly, the output  127  may represent the complimentary outputs  126  and  128  illustrated in FIG. 3, or another similar multi-bit output. The logic gate  130  is also shown generically. While FIG. 3 illustrates the logic gate  130  as an OR-gate, other appropriate logic gates may be implemented accordingly to meet the design criteria of a particular implementation. For example, a NOR gate with appropriate inverter circuits may be implemented. 
     Referring to FIG. 5, a more detailed diagram of the differential pair circuit  102  is shown. The differential pair set circuit  106  generally comprises a transistor Q 1 , a transistor Q 2 , a transistor Q 3 , a transistor Q 4 , a resistor R 1 , a resistor R 2 , a resistor R 3 , a resistor R 4 , a resistor R 5 , a resistor R 6 , a current source I 1 , a current source I 2  and a current source I 3 . The transistors Q 1  and Q 2  generally implement a first differential pair. The transistors Q 3  and Q 4  generally implement a second differential pair. The gates of the transistors Q 1  and Q 2  generally create a signal (e.g., VOFF_POS). The gates of the transistors Q 3  and Q 4  may also receive the signal VOFF_POS. The drains of the transistors Q 1 , Q 2 , Q 3  and Q 4  may be connected to a supply voltage through the resistors R 1 , R 2 , R 3  and R 4 . A signal VCM_HI may be connected between the gates of the transistors Q 2  and Q 3 . 
     The differential pair set  108  may be implemented as a transistor Q 5 , a transistor QG, a transistor Q 7 , a transistor Q 8 , a resistor R 7 , a resistor R 8 , a resistor R 9 , a resistor R 10 , a resistor R 11 , a resistor R 12 , a current source I 4 , a current source I 5  and a current source I 6 . The transistors Q 5  and Q 6  generally implement a differential pair. Similarly, the transistors Q 7  and Q 8  also implement a differential pair. The gates of the transistors Q 5  and Q 6  generally form a signal VOFF_NEG. The transistors Q 7  and Q 8  may also receive the signal VOFF_NEG at their gates. A signal VCM_LO may be connected between the gates of the transistors Q 6  and Q 7 . The shifter circuit  142  is shown presenting a differential output signal OUT. 
     The circuit  100  may provide a robust design that may survive common mode noise. The circuit may employ fully differential signal detection, with four or more independent threshold comparisons. Valid signals are generally detected for any input phase combination. The threshold levels may be adjustable to compensate for a noisy environment. The circuit  100  may create trip threshold offset voltages and input voltage comparisons within the same differential block. 
     The resistor R 5 , R 6 , R 11  and R 12  may set up threshold levels VCM_LO/VCM_HI at the common mode points. Forcing current into the common mode node generally raises the effective common mode voltage by I*R. Removing current reduces the other effective common mode node voltage by I*R. The transistors Q 2  and Q 3  are nominally on until either input rises above the common mode voltage. The transistors Q 6  and Q 7  are nominally off until one of the inputs drops below the common mode voltage VCM_LO. 
     The outputs, in one example, are “wired-or&#39;d” together to from two sets of CML differential voltage level signals. These levels are then used in standard CML logic blocks to create the detected signal OUT. Four separate comparators with separate threshold trip points that dynamically adjust for common mode variation. Post detection ORing may be implemented to detect valid opposite phase signals. Re-comparison against valid CML level voltage thresholds may provide filtering of the inputs of a CML-CMOS level translator to generate the signal OUT. 
     Referring to FIG. 6, a timing diagram of the various outputs of the present invention is shown. One waveform illustrates the signals INP and INN compared to the signals VCM_HI and VCM_LO. Another waveform illustrates the signals Z_N and Z_P when compared to a CML threshold voltage. Another waveform illustrates the signals Y_N and Y_P compared to a CML threshold voltage. Another waveform illustrates the signal OUT. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.