Abstract:
A loading device for use in a tester for testing a semiconductor integrated circuit device (DUT) includes a programmable voltage source for providing a selected voltage at an output terminal thereof and multiple resistive elements each having at least a first state, in which the resistive element is conductive, and a second state, in which the resistive element is substantially non-conductive. The resistive elements are connected as a two-terminal network between the output terminal of the programmable voltage source and a tester pin for connection to a pin of the DUT. A selection device selects the state of each resistive element, whereby the resistance between the output terminal of the programmable voltage source and the tester pin can be selectively varied.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a switchable load for testing a semiconductor integrated circuit device. 
     Frequently the specifications for a semiconductor integrated circuit device define performance of the device by reference to a pin, when operating as an output, being connected through a specified resistive load to a specified voltage. It would be desirable in testing of an integrated circuit device to be able to load an output pin of the device under test (DUT) in this manner, but the value of the specified load resistance can vary widely from device to device, and it may be specified with a high degree of precision. A suitable resistive load could be realized by arranging fixed resistors in a relay-switched resistor network, allowing a single resistor to be selected for a given test, but since the value of the resistance can vary widely, a large number of resistors would be required. It has not been economical to provide a load of this nature because of the considerable space occupied by the resistors and the power consumed in controlling the switches. In addition, the load resistor must be out of circuit in a test cycle in which the pin operates as an input to the DUT, which requires that a low resistance switch be inserted in series between the relay-switched resistor network and the DUT pin and that the switch be operated very rapidly, typically in less than 100 ns. 
     One compromise solution to the problem of providing the proper resistive load has employed a diode bridge connected to a programmable current source, in which the DUT output provides the commutating voltage for the diode switches. This approach is subject to disadvantage because it does not provide a resistive termination for the interconnect cable to the DUT and only meets the specified load conditions at two voltage-current points. Other solutions have been to provide a third voltage level to which the test system driver could be switched. This typically would provide a fixed 50 ohm value of load resistance, and the switching time could be controlled by the driver I/O timing. This solution offers only one value of load resistance and typically does not test the DUT at its specified load conditions. 
     SUMMARY OF THE INVENTION 
     In accordance with a first aspect of the invention there is provided a loading device for use in a tester for testing a semiconductor integrated circuit device (DUT), the loading device including a programmable voltage source for providing a selected voltage at an output terminal thereof, a plurality of resistive elements each having at least a first state, in which the resistive element is conductive, and a second state, in which the resistive element is substantially non-conductive, and wherein the resistive elements are connected as a two-terminal network between the output terminal of the programmable voltage source and a tester pin for connection to a pin of the DUT, and a selection means for selecting the state of each resistive element, whereby the resistance between the output terminal of the programmable voltage source and the tester pin can be selectively varied. 
     In accordance with a second aspect of the invention there is provided a loading device for use in a tester for testing a semiconductor integrated circuit device (DUT), the loading device including a programmable voltage source for providing a selected voltage at an output terminal thereof, a plurality of CMOS transmission gates each having an enabled state, in which it is conductive, and a disabled state, in which it is substantially non-conductive, and wherein the transmission gates are connected as a two-terminal network between the output terminal of the programmable voltage source and a tester pin for connection to a pin of the DUT, and a selection means for selecting the state of each transmission gate, whereby the resistance between the output terminal of the programmable voltage source and the tester pin can be selectively varied. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which 
     FIG. 1 is a schematic diagram of a first loading device in accordance with the present invention, and 
     FIG. 2 is a schematic diagram of a second loading device in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION 
     The loading device shown in FIG. 1 is designed for testing a memory device. 
     Referring to FIG. 1, a data word DATA, is supplied to a programmable voltage source 12, such as an operational amplifier driven by a digital-to-analog converter, for setting the output voltage V TH  of the voltage source. A pin 10 of the DUT is connected to the voltage source 12 through a load resistor constituted by an arrangement of sixteen paralleled switches SW 1  -SW 16  fabricated in an integrated circuit die using CMOS technology. Each switch SW has an enabled, or closed, state in which it is conductive and a disabled, or open, state in which it is non-conductive and may be implemented by a CMOS transmission gate (T-gate). Each switch has two control gate terminals and is enabled when one terminal is high and the other terminal is low, and is disabled when the terminals are in the opposite respective states. The sixteen switches are of binary weighted conductance, such that the conductance of the switch SW 1 , when enabled, is twice that of the switch SW 2 , which in turn is twice that of the switch SW 3 , and so on. This provides 2 16  selectable resistance values. The combination in which the switches SW are enabled determines the value of the resistance R load  between the DUT pin 10 and the voltage V TH  supplied by the voltage source 12. 
     Sixteen AND gates A 1  -A 16  and a register 20 storing a data word DATA R  composed of sixteen binary values R 1  -R 16  are integrated in the same die as the sixteen switches SW 1  -SW 16 . Each AND gate A i  (i=1 . . . 16) has one input connected to an output of the register 20 and a second input connected to receive a timing signal T G , which is distributed to all the AND gates. The timing signal T G  is in the logic one state when the DUT pin 10 is to be connected to the programmed voltage V TH  through the programmed resistance R load  and is otherwise in the logic zero state. Each AND gate A i  has one (non-inverted) output connected to one terminal of the switch SW i  and a second (inverted) output connected to the other terminal of the switch. In this manner, the AND gate A i  controls the state of the switch SW i  depending on the value R i . 
     A data word DATA R  is loaded into the register 20. The resistance value R load  of the switches SW 1  -SW 16  is established by the value of the word DATA R . If, for example, the switches SW 1  and SW 2  only are to be enabled and the other switches SW 3  -SW 16  are to be disabled, the register 20 is loaded with the data word (1, 1, 0, 0, . . . , 0). In this case, the outputs R 1  and R 2  of the register are in the logic one state and the other outputs R 3  -R 16  are in the logic zero state. When the timing signal T G  is high, the switches SW 1  and SW 2  are closed (conductive) and the switches SW 3  -SW 16  are open (non-conductive) 
     The typical range of the resistance R load  is 50-5000 ohms and a typical range of V TH  is 1-2 volts. The typical output voltage levels of the pin 10 are between 0.4 and 2.4 volts. In the event that R load  is 100 ohms, the maximum power dissipation is about 50 mW, which is less than one-tenth of the dissipation in the conventional load circuit. 
     In the event that the output signal at the DUT pin 10 has high frequency components, such that it is desirable to employ a transmission line 22 for connecting between the load device and the DUT pin and the desire to avoid degradation of the signal by reflections outweighs the need for the resistance R load  to match accurately the specified value, the value DATA R  may be selected to set the switches SW to provide the proper resistance value to terminate the transmission line. In this case, the value DATA V  may be selected to set the voltage VT H  at a fixed level, which is typically between the specified output high and output low voltage levels at the DUT pin 10. 
     The data values DATA R  are calibrated by connecting an external parametric measurement unit (PMU) to the DUT pin 10 and forcing a current while measuring the voltage at the DUT pin. A table relating voltage and current points to values of DATA R  is created and the value that fits most closely to the specified point is selected and loaded into the register 20. 
     The pin 10 may also be connected through a switch 24 to a driver 28. In the event the pin 10 is to operate as an input, the switches SW are disabled and the switch 24 is closed to connect the driver 28 to the pin 10 for driving the pin to a high or low voltage. 
     In some cases, the specifications of the DUT might define two states of the pin 10 when operating as an output, requiring an output high current I OH  at an output high voltage V OH  and an output low current I OL  at an output low voltage V OL . A single combination of values of V TH  and R load  can provide both the output low current I OL  when the pin 10 is at the output low voltage V OL  and the output high current I OH  when the pin is at the output voltage V OH . 
     The resistance of the CMOS switches SW 1-SW   16  will vary as a function of temperature, typically increasing 1% per degree C. over a fairly wide range of temperatures. Accordingly, a change in temperature of the integrated circuit die in which the switches are fabricated will have a significant effect on the load resistance of a given combination of switches SW. Referring to FIG. 2, a diode D1 is formed in the same integrated circuit die as the switches SW and can be used to generate a voltage signal which is proportional to temperature. If the data value to be stored in the register 20 to achieve a desired resistance value is calibrated at a temperature T 0 , at which the voltage signal provided by the diode has a value V 0 , then the data value required to program the register during operation at a temperature T, at which the voltage signal provided by the diode has a value V T  can be expressed as 
     
         DATA.sub.R =a(T-T.sub.0)+DATA.sub.0 
    
     where a is a constant. 
     In order to compensate for the effect of temperature on load resistance, the voltage signal provided by the diode D1 is converted to digital form and is used as one input to a mathematical function 40, such as a look-up table, which receives the value DATA 0  as another input and returns the value DATA R . In this manner, the resistance value of the switches SW 1  -SW 16  is rendered independent of temperature. 
     In another modification shown in FIG. 2, an additional control register 34 containing a preset value is formed in the same integrated circuit die as the register 20 and a 2×1 multiplexer 36 is connected between the outputs of the registers 20 and 34 and the inputs of the AND gates A1-A16. The multiplexer 36 is controlled by a control signal so that either the program register 20 or the control register 34 is selected for providing the data word that selects the pattern in which the switches SW 1  -SW 16  are to be enabled. By using the multiplexer to switch from the program register 20 to the control register 34, the preset value in the control register can be selected without it being necessary to halt the test sequence and reload the program register 20, which is advantageous because reloading time is much longer than a cycle time. 
     The value to be stored in the control register 34 is calibrated by connecting an external parametric measurement unit to the DUT pin 10 and forcing a selected current while measuring the voltage at the DUT pin. The value stored in the program register 20 is adjusted to achieve the closest fit to a desired current-voltage point, and this register value is then stored in the control register 34. The value to be stored in the control register 34 may be adjusted to compensate for temperature effects in response to the voltage signal provided by the diode D1, in similar fashion to the manner in which the value stored in the register 20 is adjusted. 
     Subject matter disclosed in this application is related to subject matter disclosed and claimed in patent application Ser. No. 08/962,050 which is U.S. Pat. No. 5,959,890, the entire disclosure of each of which is hereby incorporated by reference herein. 
     It will be appreciated that the invention is not restricted to the particular embodiments that have been described, and that variations may be made therein without departing from the scope of the invention as defined in the appended claims and equivalents thereof. For example, although the invention has been described with reference to implementation in CMOS technology, it would be equally applicable in other technologies allowing fabrication of transfer gate switches, such as GaAs. Use of GaAs would provide the advantage of faster switching times at lower values of V TH .