Abstract:
A phase-change memory device, wherein memory cells form a memory array arranged in rows and columns. The memory cells are formed by a MOS selection device and a phase-change region connected to the selection device. The selection device is formed by first and second conductive regions which extend in a semiconductor substrate and are spaced from one another via a channel region, and by an isolated control region connected to a respective row and overlying the channel region. The first conductive region is connected to a connection line extending parallel to the rows, the second conductive region is connected to the phase-change region, and the phase-change region is connected to a respective column. The first connection line is a metal interconnection line and is connected to the first conductive region via a source-contact region made as point contact and distinct from the first connection line.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a phase-change memory (PCM) device and the manufacturing process thereof.  
         [0003]     2. Description of the Related Art  
         [0004]     As is known, phase-change memory devices are based upon storage elements which use a class of materials that have the property of switching between two phases having distinct electrical characteristics, associated to two different crystallographic structures of the material forming the storage element, namely a disorderly amorphous phase and an orderly crystalline or polycrystalline phase.  
         [0005]     Currently, the alloys of the elements of group VI of the periodic table, such as Te or Se, referred to as calcogenides or calcogenic materials, may be advantageously used in phase-change memory cells. The currently most promising calcogenide is formed by an alloy of Ge, Sb, and Te (Ge 2 Sb 2 Te 5 ), which is now widely used for storing information in over-writable disks.  
         [0006]     In the calcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous phase (which is more resistive) to the crystalline one (which is more conductive), and vice versa.  
         [0007]     The phase change can be obtained by increasing the temperature locally. Below 150° C., both the phases are stable. Above 200° C., starting from the amorphous phase, there is a rapid nucleation of the crystallites and, if the material is kept at the crystallization temperature for a sufficient time, it changes phase and becomes crystalline. To bring the calcogenide back into the amorphous state, it is necessary to raise the temperature above the melting point (approximately 600° C.) and then cool the calcogenide rapidly.  
         [0008]     From the electrical standpoint, it is possible to reach the crystallization and melting temperatures by causing a current to flow through a resistive element (also referred to as a heater), which heats the calcogenic material by the Joule effect.  
         [0009]     The structure of a phase-change memory array, which uses a calcogenic element as the storage element, is illustrated in  FIG. 1 . The memory array  1  of  FIG. 1  comprises a plurality of memory cells  2 , each including a storage element  3  of a phase-change type and a selection element  4  formed here by an NMOS transistor. Alternatively, the selection element  4  can be formed by a bipolar-junction transistor, by a PN diode or by a calcogenic switch (“ovonic threshold switch”).  
         [0010]     The invention relates to a memory array wherein the selection element  4  is made as an MOS transistor, to which reference will then be made hereinafter.  
         [0011]     The memory cells  2  are arranged in rows and columns. In each memory cell  2 , the storage element  3  has a first terminal connected to an own bitline  6  (address bitlines BLn−1, BLn, . . . ), and a second terminal connected to a first conduction terminal of an own selection element  4 . The selection element  4  has a control terminal connected to an own control line, also referred to as a wordline  7  (address wordlines WLn−1, WLn, . . . ) and a grounded second conduction terminal.  
         [0012]     The storage element  3  is formed by a portion of a region of calcogenic material (which forms the proper memory portion) and by a heating element that enables the phase change.  
         [0013]      FIG. 2  shows the cross-section through a wafer of conductive material wherein a memory cell  2  has been formed.  
         [0014]     In detail, a wafer  10  comprises a substrate  11  of a P type accommodating a source region  12  and a drain region  13  of an N+ type. The source and drain regions  12 ,  13  are reciprocally spaced by a portion  14  of the substrate, which forms a channel region. A gate region  15  (formed by a wordline  7  of  FIG. 1 ) extends on top of the substrate  11 , vertically aligned to the channel region  14 , but isolated with respect to the substrate  11 . The source region  12 , the drain region  13  and the gate region  15  form an MOS device forming the selection element  4  of  FIG. 1 .  
         [0015]     A dielectric region  18  extends on top of the substrate  11  and accommodates within it, in addition to the gate region  15 , a source line  19 , a drain contact  20 , a heating element  21 , and a bitline  22 .  
         [0016]     The source line  19  is formed by a local interconnection line (LIL), which extends transversely with respect to the drawing plane (parallel to the wordline  7 ) and connects the source regions  12  of the memory cells  2  arranged on a same row of the memory array  1  of  FIG. 1 . The different source lines  19  of memory cells  2  belonging to a same sector are moreover connected to one another and to ground (as represented in the equivalent electrical circuit of  FIG. 1 ). In currently proposed devices, the source line  19  is obtained using a contact technique, forming a via in the bottom portion of the dielectric layer  18  and filling the via with conductive material, for example tungsten, possibly coated with a barrier material, such as Ti/TiN.  
         [0017]     Generally, the drain contact  20  is made simultaneously and using the same technique as the source line  19 , albeit having a different area, of a square or circular shape, and thus it has the same cross-section as the source line  19  in the cross-sectional view of  FIG. 2  (in particular, it has the same height) but differs in a section perpendicular thereto.  
         [0018]     The heating element  21  is made of a resistive material having thermal stability and good compatibility with CMOS processes and with calcogenic materials. For example, TiSiN, TiAlN or TiSiC can be used, formed as a thin layer that coats the walls of a cavity formed in an intermediate portion of the dielectric layer  18 . The cavity is then filled with dielectric material.  
         [0019]     The bitline  22  preferably comprises a multilayer including at least one calcogenic layer  22   a  (for example, of Ge 2 Sb 2 Te 5 ) and a metal electrode layer  22   b  (for example, of AlCu); an adhesive layer may moreover be provided (for example, of Ti or Si) underneath the calcogenic layer  22   a  and/or a barrier layer may be provided on top of the calcogenic layer  22   a.    
         [0020]     The heating element  21 , the drain contact  20  (and thus the source line  19 ), and the bitline  22  can be obtained as described in detail, for example, in EP-A-1 318 552 or in EP-A-1 339 110, which refer, however, to the construction of memory cells having a selection element of a bipolar type.  
         [0021]     The structure of  FIG. 2  has the disadvantage that it cannot be implemented with all the currently available processes, in particular when the basic CMOS technology does not enable local interconnections of an LIL type to be made.  
       BRIEF SUMMARY OF THE INVENTION  
       [0022]     One embodiment of the invention provides a device and a manufacturing process that can be implemented with any currently used or future, CMOS-compatible technique.  
         [0023]     One embodiment of the present invention is directed to a phase-change memory device. The memory device includes:  
         [0024]     an array of memory cells arranged in rows and columns and each including a MOS selection device and a phase-change region connected to the selection device, the selection device having a first conductive region and a second conductive region, formed in a substrate of semiconductor material and spaced from one another by a channel region, and an isolated control region connected to a respective one of the rows of the array and overlying the channel region;  
         [0025]     a connection line extending parallel to the rows and connected to the first conduction region, the second conductive region being connected to the phase-change region, and the phase-change region being connected to a respective one of the columns of the array; wherein the connection line is a metal interconnection line; and  
         [0026]     a source-contact region, distinct from the first connection line and connecting the first conductive region to the connection line. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0027]     For an understanding of the present invention a preferred embodiment thereof is now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:  
         [0028]      FIG. 1  shows the equivalent electrical circuit of a phase-change memory array;  
         [0029]      FIG. 2  shows the implementation of a cell of the memory of  FIG. 1 ;  
         [0030]      FIGS. 3-5  show two cross-sectional views and a top view of a first embodiment of a memory cell;  
         [0031]      FIGS. 6 and 7  show a cross-sectional view and a top view of a second embodiment of a memory cell;  
         [0032]      FIGS. 8 and 9  show two cross-sectional views of a third embodiment of a memory cell;  
         [0033]      FIG. 10  shows a cross-sectional view of a fourth embodiment of a memory cell; and  
         [0034]      FIG. 11  is a block diagram of a system that uses the present storage device.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0035]      FIGS. 3-5  refer to an embodiment wherein the source line is made in a metal layer, and precisely in the first metal level (meta11). Furthermore, the bitline is formed on top of the first metal level, and precisely between the first and second metal levels (not illustrated). Furthermore, the memory cells are split-gate cells, i.e., the selection element  4  is formed by two MOS transistors connected in parallel and thus equivalent to an individual MOS transistor having a width W twice the width of the defined active area.  
         [0036]     In detail, a wafer  30  comprises a substrate  31  of a P type accommodating source regions  32  (two of which are visible in  FIG. 3 ) and drain regions  33  (just one of which is visible in  FIG. 3 ). Between each source region  32  and the adjacent drain region  33 , the substrate  31  forms a channel region  34 ; a dielectric layer  35  coats all the surface of the substrate  31  and accommodates gate regions  36  that extend on the channel regions  34  and are formed by polysilicon lines WL forming the wordlines  7  of  FIG. 1 .  
         [0037]     Source-contact regions  40  extend through the dielectric layer  35  between the source regions  32  and the source lines  42 ; likewise, drain-contact regions or memory-contact regions  41  extend between the drain regions  33  and the metal pad regions  43 .  
         [0038]     The source-contact regions  40  and drain-contact regions  41  are made in vias opened in the bottom portion of the dielectric layer  35  and are obtained using the contact technique, for example, with tungsten coated with a Ti/TiN barrier layer.  
         [0039]     In practice, each source-contact region  40  defines a local contact with a respective source region  32 , and the connection between the various source regions  32  is ensured by the source lines  42 , which extend at a certain height on top of the substrate and are distinct from the source-contact regions  40  themselves.  
         [0040]     The source lines  42  and the metal pad regions  43  are formed in the first metal level (metal1), which is for example of AlCu or Cu, and have the shape shown in the top view of  FIG. 5 ; in particular, the source lines  42  extend parallel to the wordlines WL, while the metal pad regions  43  have a rectangular or square shape.  
         [0041]     Heater elements  44 , of resistive material, extend on top of the metal pad regions  43 . Finally, bitlines  45  are formed on top of the heater elements  44 , locally in contact with the heater elements  44 .  
         [0042]     The bitlines  45  are formed by a bottom layer  45   a , of calcogenic material, and by a top layer  45   b , of metal material, for example AlCu or Cu.  
         [0043]     In practice,  FIGS. 3 and 5  show in a complete way just one memory cell  2 , comprising a column  41 ,  43 ,  44 , a drain region  33 , two gate regions  36  (wordlines WL n ), and two source regions  32 ; the source regions  32  are moreover shared with the adjacent memory cells  2 , connected to the wordlines WL n−1  and WL n+1 .  
         [0044]     It is emphasized that  FIGS. 3-5  are only schematic as regards the heater elements  44  and the bitlines  45 , and these could be modified as described in the European patents cited above so as to obtain sublithographic contact regions. For example, each heating element  44  could be formed by a wall of material deposited in an appropriate cavity, and the bitlines  45  could comprise further layers, such as an adhesion layer and/or a barrier layer and could be shaped so as to have a thinner bottom portion. For example, the bottom layer  45   a  could be formed by a thin line that crosses the walls forming the heater elements. Alternatively, should considerations of a thermal type not require the presence of submicrometric contact regions between the heating material and the calcogenic material, the structure of the heater elements  44  and of the bitlines  45  could correspond to the one illustrated in the drawings.  
         [0045]     In any case, the portions of the bottom layer  45   a  of the bitlines  45  in contact with the heater elements  44  form storage regions, designated as a whole by  46 , the phase whereof (whether crystalline or amorphous) represents the information stored.  
         [0046]     For completeness, it is pointed out that, in the top view of  FIG. 5 , the line  48  represents the active-area mask which, in this embodiment, is strip-shaped and extends through the entire column. Furthermore, field-isolation regions  49  are visible in the cross-section of  FIG. 4  (preferably formed through shallow-trench isolation—STI), and separate cells  2  that are adjacent in the direction of the wordlines WL (and thus of the source lines  42 ).  
         [0047]      FIGS. 6 and 7  refer to a different embodiment of the invention, referred to as split-active, wherein the active areas  48 ′ are formed by rectangles of width W, corresponding to two adjacent memory cells  2 . In practice, here, each active area accommodates two drain regions  33  and a single source region  32 , which is intermediate and is shared by the two memory cells  2 . In this case, the cross-section perpendicular to that of  FIG. 6  coincides with that of  FIG. 4 .  
         [0048]     The embodiments of  FIGS. 3-5  and  6 - 7  are both characterized in that the definition of the storage element  46  occurs after definition of the metal1 level, and the heater elements  44  are defined between the metal1 level and the bitlines  45 . This approach has the main advantage of reducing the thermal budget seen by the bottom layer  45   a , of calcogenic material, of the bitlines  45 , maintaining the same basic architecture of traditional memory cells  2 , and thus without having to modify excessively the existing design criteria.  
         [0049]     Furthermore, with the presented solutions it is possible to save a mask (LIL or pre-contact mask), if this is not required by the basic CMOS process.  
         [0050]     In these two cases, the second metal level (metal2, not illustrated) can be advantageously used for strapping of the wordlines WL, in a per se known manner. The use of the first solution or of the second solution depends upon the technology adopted (layout rules) and upon the sizing of the MOS transistor (width W and length L of the gate); in practice, the two solutions provide different shape factors (i.e., the ratio between global width and length of each cell), and during the design phase it is possible to use the optimal solution for the required specifications.  
         [0051]      FIGS. 8-10  show a third embodiment, wherein the storage region  46  is not formed by the bitline  45  but by an appropriate region (rectangular dot or pad) set underneath the metal1 level. Furthermore, the third embodiment implements a solution of the split-gate type, like the first embodiment. The third embodiment has a similar top view as the embodiment of  FIG. 5 , except, as mentioned, for the shape of the regions of calcogenic material, consequently the top view is not illustrated.  
         [0052]     In detail, in  FIGS. 8 and 9 , the source-contact regions  40  are formed by different parts and comprise a bottom portion  40   a , equivalent to the contact region  40  of  FIGS. 3-7 , and a top portion  40   b , formed using the same technique and aligned to the bottom portion  40   a , thereby, globally, the source-contact regions  40  of  FIGS. 8 and 9  have a height greater than the height of those of  FIGS. 3-7 .  
         [0053]     Furthermore, the heater elements  44  are formed immediately on top of the drain-contact or memory regions  41 ; the storage regions  46  (of calcogenic material) are arranged immediately on top of the heater elements  44 ; and first contact portions  50  are formed on top of the storage regions  46  and extend up to the level of the metal1 level. Metal pad regions  43  are here formed on top of the first contact portions  50 , at the same height as the source lines  42 , since both the source lines  42  and the metal pad regions  43  are formed in the first metal level (metal1).  
         [0054]     On top of the metal pad regions  43 , second contact portions  51  are present, which connect the metal pad regions  43  and thus the storage regions  46  to the bitlines  45 , which are here formed by the second metal level (metal2) and are obtained with the techniques normally used for metal interconnections (for example, AlCu or Cu interconnections).  
         [0055]     In practice, since the storage regions  46  are here made separately from the bitlines  45 , underneath the metal1 level, the source-contact regions  40  are made by two different portions  40   a ,  40   b , arranged on top of one another and made at two different times, the first portions  40   a  using the contact technique, before the formation of the heater elements  44 , and the second portions  40   b  using the same contact technique, after the formation of the storage regions  46 , and the deposition and planarization of an intermediate portion of the dielectric layer  35 , together with the first contact portions  50 . After formation of the source lines  42 , of the metal pad regions  43 , and possibly of other regions in the first metal level (metal1), deposition and planarization of a further portion of the dielectric layer  35 , and formation of the second contact portions  51  (also these formed using the contact technique), the bitlines  45  are formed.  
         [0056]      FIG. 10  shows an embodiment differing from the third embodiment of  FIGS. 8-9 , of the split-active type wherein, similarly to the embodiment of  FIGS. 6 and 7 , the active-area mask has separate windows for each memory cell  2 . In this fourth embodiment, the cross-section perpendicular to  FIG. 10  is the same as in  FIG. 9  and the top view is similar to  FIG. 7  (apart from the shape of the region of calcogenic material), and consequently said views are not shown.  
         [0057]     The third and fourth embodiments illustrated in  FIGS. 8-10  have the advantage that the storage regions  46  are separated from the bitlines  45  and can be located only where necessary. In this way, it is possible to avoid some process steps (such as deposition and definition of the top metal layer  45   b , on top of the calcogenic material  45   a ), which are, instead, used for the first and second embodiments for reducing the resistivity of the bitlines  45 .  
         [0058]      FIG. 11  shows a portion of a system  500  according to an embodiment of the present invention. The system  500  can be used in wireless devices such as, for example, a personal digital assistant (PDA), a laptop or portable computer with wireless capacity, a “web tablet”, a wireless telephone, a pager, a device for sending instantaneous messages, a digital music player, a digital camcorder, or other devices that can be suitable for transmitting and/or receiving information in wireless mode. The system  500  can be used in any one of the following systems: a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, or a cellphone network, even though the extent of the present invention is not limited in this connection.  
         [0059]     The system  500  comprises a controller  510 , an I/O device  520  (for example, a keyboard or a display), a memory  530 , a wireless interface  540 , and a static random-access memory (SRAM)  560 , connected to one another through a bus  550 . A battery  580  supplies the system  500 .  
         [0060]     The controller  510  comprises, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. The memory  530  can be used for storing messages transmitted to or received by a system  500 . The memory  530  can optionally be used also for storing instructions that are executed by the controller  510  during operation of the system  500 , and can be used for storing user data. The instructions can be stored as digital information, and the user data, as described herein, can be stored in one section of the memory as digital data and, in another section, as analog memory. In another example, one data section at a time can be labeled as such and can store digital information, and can then be re-labeled and reconfigured for storing analog information. The memory  530  can be provided with one or more types of memory. For example, the memory  530  can comprise a volatile memory (any type of RAM), a nonvolatile memory, such as a flash memory, and/or a memory that includes the memory array  1  of  FIG. 1 , as implemented in one of the embodiments of  FIGS. 3-10 .  
         [0061]     The I/O device  520  can be used for generating a message. The system  500  can use the wireless interface  540  for transmitting and receiving messages to and from a wireless communication network with a radio-frequency (RF) signal. Examples of wireless interfaces  540  comprise an antenna or a wireless transceiver, such as a dipole antenna, even though the scope of the present invention is not limited in this respect. Furthermore, the I/O device  520  can provide a voltage reflecting what is stored as either a digital output (if digital information was stored), or as analog information (if analog information was stored).  
         [0062]     Finally, it is clear that numerous modifications and variations can be made to the storage device and to the manufacturing process described and illustrated herein, all of which fall within the scope of the invention, as defined in the attached claims.  
         [0063]     All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety.