Abstract:
A system for converting a continuous-time analog signal having a signal bandwidth to a discrete-time digital signal, the system includes a plurality of proportional filters configured to receive the continuous-time analog signal, each proportional filter having a different center frequency from all other proportional filters and each proportional filter having an operational bandwidth directly proportional to its center frequency, and a plurality of sample and hold circuits, each sample and hold circuit coupled to a respective one of the proportional filters.

Description:
TECHNICAL FIELD 
   This disclosure relates to analog to digital converters, and in particular to analog to digital converters that use a filter bank. 
   BACKGROUND 
   Analog to digital converters with sufficient dynamic range and linearity become increasingly difficult to implement as the sampling rates increase. Improving the performance of wideband analog to digital converters is a long standing problem and a number of approaches have been developed to address this issue. One approach in the prior art is to use time interleaved analog to digital converters, which are exemplified by U.S. Pat. No. 5,294,926 to Corcoran, issued Mar. 15, 1994. In that approach the signal is fed to a bank of analog to digital converters and the sampling of the signal is time interleaved between the analog to digital converters (ADC) so that the first sample is taken by the first ADC, the second sample by the second ADC and so on until the last ADC takes a sample and then the sampling order repeats starting with the first ADC. The samples from the ADCs are then recombined. The sample rate of any one of the analog to digital converters is reduced; however, mismatches between the analog to digital converters can cause amplitude and phase errors. 
   Another approach is use a filter bank to filter the wideband input signal into a set of lower bandwidth input signals. The lower bandwidth input signals can then be converted to digital form with ADCs operating at lower sample rates and then the outputs from the ADCs are recombined. The filter bank approach for reducing ADC sample rates is exemplified by U.S. Pat. No. 5,568,142 to Velazquez et al. issued Oct. 22, 1996 and by U.S. Pat. No. 6,476,749 to Yeap et al. issued Nov. 5, 2002. 
   Such a system for analog to digital conversion  10  is shown in  FIG. 1 . The wideband input signal  12  is fed into filters  14 , which subdivide the wideband input signal  12  into a set of lower bandwidth signals that are each then fed into sample and hold circuits  16  and then to analog to digital converters  18 . The outputs of the analog to digital converters  18  are digitally recombined in digital recombiner  20  to form a digital output  22 , which is the digital representation of input signal  12 . 
   In the prior art the filters  14  have different center frequencies to cover the bandwidth of the wideband input signal; however, each filter  14  has the same operational bandwidth. This has the advantage that the hardware downstream of each filter  14  is identical including the sample and hold circuit  16  and the ADC  18 . Because all of the operational bandwidths of the filters  14  are identical, each sample and hold circuit  16 , as shown in  FIG. 1 , is clocked at the same rate. 
   A disadvantage of the prior art system is that capacitors in the sample and hold circuits  16  may see large signal swings and if, as a result, the sample and hold circuits  16  cannot react fast enough to the large signal swings the sample and hold circuit  16  will introduce errors that effectively limit the performance of the analog to digital conversion system. Because the performance of the sample and hold circuits  16  is a major limiter to the performance of the filter bank approach for wideband analog to digital conversion, any improvement to the performance of the sample and hold circuits  16  can help improve the signal to noise ratio and the signal to noise plus distortion ratio of the analog to digital conversion system. 
   What is needed is a system that improves the performance of the sample and hold circuits or limits large signal swings at the input of the sample and hold circuits. If the stress on the sample and hold circuits can be limited then the performance of the analog the digital conversion system can be improved. The embodiments of the present disclosure answer these and other needs. 
   SUMMARY 
   In a first embodiment disclosed herein, a system for converting a continuous-time analog signal having a signal bandwidth to a discrete-time digital signal includes a plurality of proportional filters configured to receive the continuous-time analog signal, each respective one of the proportional filters having a different center frequency from all other proportional filters and each respective one of the proportional filters having an operational bandwidth directly proportional to its center frequency, and a plurality of sample and hold circuits, each respective one of the sample and hold circuits coupled to a respective one of the proportional filters. 
   In another embodiment disclosed herein, a method for converting a continuous-time analog signal having a signal bandwidth to a discrete-time digital signal includes filtering the continuous-time analog signal with a plurality of proportional filters configured to receive the continuous-time analog signal, each respective one of the proportional filters having a different center frequency from all other proportional filters and each respective proportional filter having an operational bandwidth directly proportional to its center frequency, and sampling and holding an output of each respective one of the proportional filters with a respective one of a plurality of sample and hold circuits, each respective one of the sample and hold circuits coupled to a respective one of the proportional filters. 
   These and other features and advantages will become further apparent from the detailed description and accompanying figures that follow. In the figures and description, numerals indicate the various features, like numerals referring to like features throughout both the drawings and the description. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic depiction of a system for analog to digital conversion in accordance with the prior art; 
       FIG. 2  is a schematic depiction of a system for analog to digital conversion in accordance with the present disclosure; 
       FIG. 3  is diagram showing the sampling of input sine waves in accordance with the present disclosure; and 
       FIG. 4  is portion of a filter bank in accordance with the present disclosure. 
   

   DETAILED DESCRIPTION 
   Referring to  FIG. 2 , a system  30  for analog to digital conversion is shown. A wideband input signal  32  is fed into a filter bank  40  with a set of proportional filters  34 ,  35 ,  36 ,  37  . . . and  46 , the number of which depend on the application. In  FIG. 2  the individual proportional filters are shown as filters  34 ,  35 ,  36 ,  37  . . . and  46 . Each of these filters has a different center frequency; however, in contrast to the prior art, the operational bandwidth of each of the filters is directly proportional to the center frequency of the filter, and thus the filters are proportional filters  34 ,  35 ,  36 ,  37  . . . and  46 . The operational bandwidth of a proportional filter is wider for a high center frequency and lower for a low center frequency of the proportional filter, thus the filters are proportional filters  34 ,  35 ,  36 ,  37  . . . and  46 . The center frequencies and the operational bandwidth of the proportional filters  34 ,  35 ,  36 ,  37  . . . and  46  are such that the sum of the operational bandwidths of the proportional filters  34 ,  35 ,  36 ,  37  . . . and  46  is at least equal or greater than the bandwidth of the wideband signal input  32 . 
   Because the operational bandwidths of the each of the proportional filters  34 ,  35 ,  36 ,  37  . . . and  46  in the filter bank  40  vary, the clock rates (CLK 1 , CLK 2 , CLK  3 , CLK  4  . . . and CLK N) of the sample and hold circuits  50 ,  51 ,  52 ,  53  . . . and  56  also vary, and depend on the operational bandwidth of the proportional filter to which the sample and hold circuit is connected. In one embodiment, as discussed further below, the clock rate of each sample and hold circuit is substantially the same as the center frequency of the proportional filter to which the sample and hold circuit is connected. 
   The analog to digital converters  60 ,  61 ,  62 ,  63  . . . and  66  that follow the sample and hold circuits  50 ,  51 ,  52 ,  53  . . . and  56  may be clocked at the same rate as the sample and hold circuit to which they are connected. However, the analog to digital converters  60 ,  61 ,  62 ,  63  . . . and  66  may also oversample or under sample the sample and hold circuit outputs. The outputs of the analog to digital converters  60 ,  61 ,  62 ,  63  . . . and  66  are digitally recombined by the digital recombiner  70  to form the digital output  72 . 
   The clock signals may be chosen to be submultiples of a master clock so they can be easily generated on chip and retimed to reduce jitter. 
   To improve the sample and hold circuit performance in this system, the signal swings at the input to the sample and hold circuits  50 ,  51 ,  52 ,  53  . . . and  56  are preferably limited. Referring to  FIG. 3 , a sine wave  80  having a frequency f is sampled by a sample and hold circuit at a periodic interval of T or a rate of 1/T. If the sample time  86  is chosen to be T=N/f, where N=0, 1, 2, . . . , then the sine wave  80  having a frequency of f will be continually sampled at the same point on the sine wave. However, sine waves with different frequencies will not. By limiting the operational bandwidth of the proportional filter coupled to and preceding the sample and hold circuit, the signal swings at the input to the sample and hold circuit can be limited to +/−δ as shown by reference  84  in  FIG. 3 . For example, sine wave  81  has a frequency of f−Δf and sine wave  82  has a frequency of f+Δf. If a sampling of sine wave  81  is followed by a sampling of sine wave  82 , then the two succeeding samples will have at most a 2δ amplitude signal swing. So by setting the bandwidth of the proportional filter feeding this sample and hold circuit to be 2Δf or in radians per second 2Δω, the signal swing at the input to the sample and hold circuit can be limited to a 2δ signal swing. 
   Assuming an amplitude of 1,
 
2δ=sin [( w+Δw ) T ]−sin [(ω−Δ w ) T].   (1)
 
   Letting 
                     T   ≅       2   ⁢   N   ⁢           ⁢   π     ω       ,     N   =   0     ,   1   ,   2   ,     3   ⁢           ⁢   …       ⁢                   (   2   )               
and using trigonometric identities sin(a+b)=sin(a)cos(b)+cos(a)sin(b), we can solve (1) to obtain
 
   
     
       
         
           
             
               
                 δ 
                 = 
                 
                   
                     sin 
                     ⁡ 
                     
                       ( 
                       
                         2 
                         ⁢ 
                         N 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         π 
                         ⁢ 
                         
                           Δω 
                           ω 
                         
                       
                       ) 
                     
                   
                   . 
                 
               
             
             
               
                 ( 
                 3 
                 ) 
               
             
           
         
       
     
   
   If δ is restricted to be small, then by using sin(x)=˜x, the following equation is obtained 
   
     
       
         
           
             
               
                 Δω 
                 ≅ 
                 
                   
                     δω 
                     
                       2 
                       ⁢ 
                       N 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       π 
                     
                   
                   . 
                 
               
             
             
               
                 ( 
                 4 
                 ) 
               
             
           
         
       
     
   
   Equation (4) indicates that the filter bank  40  is a bank of proportional filters  34 ,  35 ,  36 ,  37  . . . and  46 , because Δω, which is the bandwidth of the proportional filter, is directly proportional to ω, which is the center frequency of the proportional filter. Equation (2) indicates that the sample rates for the sample and hold circuits  50 ,  51 ,  52 ,  53  . . . and  56  depend on the center frequencies of each proportional filter and are higher for sample and hold circuits  50 ,  51 ,  52 ,  53  . . . and  56  connected to proportional filters  34 ,  35 ,  36 ,  37  . . . and  46  with a high center frequency and lower for sample and hold circuits  50 ,  51 ,  52 ,  53  . . . and  56  connected to proportional filters  34 ,  35 ,  36 ,  37  . . . and  46  with lower center frequencies. 
     FIG. 4  shows a portion of the filter bank  40  of proportional filters  34 ,  35 ,  36 ,  37  . . . and  46  connected to sample and hold circuits  50 ,  51 ,  52 ,  53  . . . and  56  and analog to digital converters  60 ,  61 ,  62 ,  63  . . . and  66 . Each proportional filter is shown with its center frequency and its operational bandwidth. For example, proportional filter  35  has a center frequency  35   a  of ω i+1  and an operational bandwidth of  35   a  plus  35   b  for a total operational bandwidth for proportional filter  35  of 2Δω i+1 . From  FIG. 4 ,
 ω i+1 =ω i −Δω i −Δω i−1   (5) 
   Using (4), 
   
     
       
         
           
             
               
                 
                   ω 
                   
                     i 
                     - 
                     1 
                   
                 
                 = 
                 
                   
                     ω 
                     i 
                   
                   - 
                   
                     
                       δω 
                       i 
                     
                     
                       2 
                       ⁢ 
                       N 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       π 
                     
                   
                   - 
                   
                     
                       δω 
                       
                         i 
                         - 
                         1 
                       
                     
                     
                       2 
                       ⁢ 
                       N 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       π 
                     
                   
                 
               
             
             
               
                 ( 
                 6 
                 ) 
               
             
           
         
       
     
   
   which can be solved as: 
   
     
       
         
           
             
               
                 
                   ω 
                   
                     i 
                     - 
                     1 
                   
                 
                 = 
                 
                   
                     ω 
                     i 
                   
                   ⁢ 
                   
                     
                       
                         1 
                         - 
                         
                           δ 
                           
                             2 
                             ⁢ 
                             N 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             π 
                           
                         
                       
                       
                         1 
                         + 
                         
                           δ 
                           
                             2 
                             ⁢ 
                             N 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             π 
                           
                         
                       
                     
                     . 
                   
                 
               
             
             
               
                 ( 
                 7 
                 ) 
               
             
           
         
       
     
   
   The center frequency for the proportional filter with the highest center frequency for a wideband input signal with bandwidth of Fs/2 above DC, can be expressed as
 
ω N =2 πF   s /2−Δω N .  (8)
 
   Then from (4), 
   
     
       
         
           
             
               
                 
                   ω 
                   N 
                 
                 = 
                 
                   
                     π 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       F 
                       s 
                     
                   
                   
                     1 
                     + 
                     
                       δ 
                       
                         2 
                         ⁢ 
                         N 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         π 
                       
                     
                   
                 
               
             
             
               
                 ( 
                 9 
                 ) 
               
             
           
         
       
     
   
   Equation (2) can be used to solve for the sample time T i . 
   
     
       
         
           
             
               
                 
                   T 
                   
                     i 
                     - 
                     1 
                   
                 
                 = 
                 
                   
                     T 
                     i 
                   
                   ⁢ 
                   
                     
                       1 
                       + 
                       
                         δ 
                         
                           2 
                           ⁢ 
                           N 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           π 
                         
                       
                     
                     
                       1 
                       - 
                       
                         δ 
                         
                           2 
                           ⁢ 
                           N 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           π 
                         
                       
                     
                   
                 
               
             
             
               
                 ( 
                 10 
                 ) 
               
             
           
         
       
     
   
   Equations (2) through (10) describe how to set the filter bandwidths and sample times based on a desired value of δ. In practice, it is not always straightforward to obtain ideal ratios of sample times. For this reason, a desired fraction f=T i /T i+1  can be used to solve for δ in equation (10) to obtain 
   
     
       
         
           
             
               
                 δ 
                 = 
                 
                   2 
                   ⁢ 
                   N 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   π 
                   ⁢ 
                   
                     
                       
                         1 
                         - 
                         f 
                       
                       
                         1 
                         + 
                         f 
                       
                     
                     . 
                   
                 
               
             
             
               
                 ( 
                 11 
                 ) 
               
             
           
         
       
     
   
   This system of analog to digital conversion improves the performance of the sample and hold circuits  50 ,  51 ,  52 ,  53  . . . and  56 , which leads to improved overall performance of the analog to digital conversion system  10 . 
   Having now described the invention in accordance with the requirements of the patent statutes, those skilled in this art will understand how to make changes and modifications to the present invention to meet their specific requirements or conditions. Such changes and modifications may be made without departing from the scope and spirit of the invention as disclosed herein. 
   The foregoing Detailed Description of exemplary and preferred embodiments is presented for purposes of illustration and disclosure in accordance with the requirements of the law. It is not intended to be exhaustive nor to limit the invention to the precise form(s) described, but only to enable others skilled in the art to understand how the invention may be suited for a particular use or implementation. The possibility of modifications and variations will be apparent to practitioners skilled in the art. No limitation is intended by the description of exemplary embodiments which may have included tolerances, feature dimensions, specific operating conditions, engineering specifications, or the like, and which may vary between implementations or with changes to the state of the art, and no limitation should be implied therefrom. Applicant has made this disclosure with respect to the current state of the art, but also contemplates advancements and that adaptations in the future may take into consideration of those advancements, namely in accordance with the then current state of the art. It is intended that the scope of the invention be defined by the Claims as written and equivalents as applicable. Reference to a claim element in the singular is not intended to mean “one and only one” unless explicitly so stated. Moreover, no element, component, nor method or process step in this disclosure is intended to be dedicated to the public regardless of whether the element, component, or step is explicitly recited in the Claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for . . . ” and no method or process step herein is to be construed under those provisions unless the step, or steps, are expressly recited using the phrase “comprising the step(s) of . . . . ”