Abstract:
A power supply voltage switch circuit for selecting a power supply voltage of an integrated circuit according to a first control signal. The power supply voltage switch circuit contains a high voltage selecting module for generating an output voltage according to the higher of a first and a second voltages; a level shifting module electrically connected to the high voltage selecting module to receive the output voltage as power supply, for performing level shifting to a first control signal according to the output voltage; and a selecting switch module electrically connected to the level shifting module for selectively outputting the first or the second voltage as the power supply voltage of the integrated circuit according to the level-shifted first control signal.

Description:
BACKGROUND OF INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The invention generally relates to a power supply voltage switching circuit, and more particularly, to a power supply voltage switching circuit having a high voltage selecting module.  
         [0003]     2. Description of the Prior Art  
         [0004]     In certain application of IC technology, situations might come across where a different power supply voltage is required for operating in different modes, such as non-volatile flash memory. In prior art, a power supply voltage switch circuit is often used to accomplish the switching of different power supply voltage in different operating modes.  
         [0005]     Please refer to  FIG. 1 , which shows a schematic diagram of a conventional power supply voltage switching circuit  10  according to prior art. The power supply voltage switching circuit  10  comprises a level shifting module  12  for shifting the level of the input signal to a comparatively high level before outputting the signal. In  FIG. 1 , the level shifting module  12  comprises two level-shifters  14  and  16  for respectively shifting levels of the two input signals, wherein the voltage level of the comparatively high level signal after level shifting is determined by the power supply voltage of the level-shifters  14  and  16 . The power supply voltage switching circuit  10  further comprises a selecting switch module  18 , where the selecting switch module  18  in  FIG. 1  is made up of a first p-type MOS transistor  20  and a second p-type MOS transistor  22 . The selecting switch module  18  selects from either a first voltage V PP  or a second voltage V DD  to generate a power supply voltage V PS  for an integrated circuit according to the comparatively high level signals generated by the level shifting module  12 .  
         [0006]     In the actual application, the level of the first voltage V PP  is usually the level after charge pumping such as 7V˜0V and the second voltage V DD  is usually the standard voltage used in common integrated circuits such as 3V˜0V. Therefore, generally speaking, if the integrated circuit wishes to operate at a different voltage mode, a control circuit (not shown in  FIG. 1 ) generates a first control signal ENVPP to control the power supply voltage switching circuit  10  in generating the desired power supply voltage V PS . In  FIG. 1 , besides the first control signal ENVPP, the control circuit can also generate a second control signal ENVDD which is a complementary signal of the first control signal ENVPP, for controlling the power supply voltage switching circuit  10 . The power supply voltage of the control circuit is the standard voltage so the level of both the first control signal ENVPP and the second control signal ENVDD is within the standard range (3V˜0V).  
         [0007]     As previously mentioned, the level of the shifted comparatively high level signal from the level shifting module  12  corresponds to the power supply voltage of the level-shifters  14  and  16 . In  FIG. 1 , the power supply voltage of the level-shifters  14  and  16  is the first voltage V PP , therefore the level of the first control signal ENVPPHV and the second control signal ENVDDHV after level shifting is comparatively high (7V˜0V) which is used to control the operation of the third and fourth p-type MOS transistors  20 ,  22  in the selecting switch module  18 .  
         [0008]     In the above-mentioned configuration, the power supply voltage switching circuit  10  can generate a power supply voltage V PS  from the first voltage V PP  and the second voltage V DD  according to the control of the first control signal ENVPP and the second control signal ENVDD. If the first voltage V PP  is chosen to be the power supply voltage V PS  the control circuit sets the first control signal ENVPP to a logic value of 0 (i.e. 0V) and the second control signal ENVDD to a logic value of 1 (i.e. 3V). After the level shift by the level shifting module  12 , the first control signal ENVPP remains 0V but the second control signal ENVDD becomes 7V and are inputted to the selecting switch module  18 . At the same time, the first voltage V PP  is 7V and the second voltage V DD  is 3V so the third p-type MOS transistor  20  is in conduct and the fourth p-type MOS transistor  22  is switched off. As a result the power supply voltage V PS  will output the value of the first voltage V PP  (i.e. 7V). Oppositely if the second voltage V DD  is chosen to be the power supply voltage V PS , the control circuit sets the first control signal ENVPP to a logic value of 1 (i.e. 3V) and the second control signal ENVDD to a logic value of 0 (i.e. 0V). After the level shift by the level shifting module  12 , the first control signal ENVPP becomes 7V but the second control signal ENVDD remains 0V and are inputted to the selecting switch module  18 . At the same time, the first voltage V PP  is 7V and the second voltage V DD  is 3V so the third p-type MOS transistor  20  is switched off and the fourth p-type MOS transistor  22  is in conduct. As a result the power supply voltage V PS  will output the value of the second voltage V DD  (i.e. 3V).  
         [0009]     Furthermore, the above operation takes into the assumption that the value of the first voltage V PP  does not change. However in certain design of circuits, it is possible that the value of the first voltage V PP  cannot always be maintained at a charge-pumped level, an example is the sharing of a pad between a charge-pumped voltage (such as V PP ) and other signals. In this condition, the value of the first voltage V PP  can be at a comparatively low level or even become 0V or floating in some situation. The level-shifters  14  and  16  of the level shifting module  12  use the first voltage V PP  as the power supply voltage which renders the selecting switch module  18  unable to operate properly, or renders the third and fourth p-type MOS transistors  20  and  22  to be in conduct at the same time causing the first voltage V PP  the second voltage V DD  to short circuit which wastes energy.  
       SUMMARY OF INVENTION  
       [0010]     It is therefore an objective of the claimed invention to provide a power supply voltage switching circuit having a high voltage selecting module to solve the above-mentioned problem.  
         [0011]     The claimed invention discloses a power supply voltage switching circuit for selecting a power supply voltage for an integrated circuit according to a first control signal, the circuit comprising: a high voltage selecting module for generating an output voltage according to a higher one of a first voltage and a second voltage; a level shifting module, being electrically coupled to the high voltage selecting module for inputting the output voltage as the power supply voltage, for shifting a level of the first control signal according to the output voltage; and a selecting switch module, being electrically coupled to the level shifting module, for selectively outputting the first voltage or the second voltage as the power supply voltage of the integrated circuit according to the level-shifted first control signal.  
         [0012]     The claimed invention discloses a high voltage selecting circuit comprising: a first transistor where a first terminal of the first transistor being electrically coupled to a first voltage, a second terminal of the first transistor being electrically coupled to an output junction, and a gate of the first transistor being electrically coupled to a second voltage; and a second transistor where a first terminal of the second transistor being electrically coupled to the second voltage, a second terminal of the second transistor being electrically coupled to the output junction, and a gate of the second transistor being electrically coupled to the first voltage; wherein the high voltage selecting circuit selectively generates an output voltage according to a higher one of the first voltage and the second voltage.  
         [0013]     The claimed invention discloses a high voltage selecting circuit to supply power to the level-shifters according to an output voltage generated from either a first voltage or a second voltage. Therefore no matter how the level of the first voltage changes, the control signals after level-shifting can ensure the level is enough to allow the power supply voltage switching circuit to operate properly.  
         [0014]     These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.  
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0015]      FIG. 1  is a schematic diagram of a conventional power supply voltage switching circuit according to prior art.  
         [0016]      FIG. 2  is a schematic diagram of the power supply voltage switching circuit according to a preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0017]     Please refer to  FIG. 2 , which is a schematic diagram of the power supply voltage switching circuit  30  of the present invention. In  FIG. 2 , the power supply voltage switching circuit  30  comprises a level shifting module  32  and a selecting switch module  38  wherein the level shifting module  32  shifts the level of the input signal to a higher level. In this preferred embodiment, the level shifting module  32  comprises level-shifters  34  and  36  which are used to respectively shift levels of the two input signals (i.e. the first control signal ENVPP and the second control signal ENVDD). The level of the comparatively high level signal after the level shift is dependent on the power supply voltage of the level shifter  34  and  36 . The selecting switch module  38  electrically coupled to the level shifting module  32  is for selectively choosing the first voltage V PP  or the second voltage V DD  to be the power supply voltage V PS  of the integrated circuit according to the level-shifted first control signal ENVPPHV and second control signal ENVDDHV.  
         [0018]     In this embodiment, the selecting switch module  38  comprises a third p-type MOS transistor  40  where the source is electrically coupled to the first voltage V PP , the drain is electrically coupled to a supply node, and the gate is electrically coupled to the level-shifted first control signal ENVPPHV; a fourth p-type MOS transistor  42  where the source is electrically coupled to the second voltage V DD , the drain is electrically coupled to the supply node, and the gate is electrically coupled to the level-shifted second control signal ENVDDHV (i.e. the complementary signal of the level-shifted first control signal ENVPPHV). The selecting switch module  38  generates the power supply voltage V PS  for the integrated circuit at the supply node according to the level-shifted first control signal ENVPPHV and second control signal ENVDDHV.  
         [0019]     The power supply voltage switching circuit  30  of the present invention further comprises a high voltage selecting module  44 . In this embodiment, the high voltage selecting module  44  comprises a first p-type MOS transistor  46  where the source is electrically coupled to a first voltage V PP , the drain is electrically coupled to an output node, and the gate is electrically coupled to a second voltage V DD ; and a second p-type MOS transistor  48  where the source is electrically coupled to the second voltage V DD , the drain is electrically coupled to the output node, and the gate is electrically coupled to the first voltage V PP . The high voltage selecting module  44  generates an output voltage VV according to the higher of the first voltage V PP  and the second voltage V DD  and sends the output voltage VV to the level shifting module  32  to be the power supply voltage for the level-shifters  34  &amp;  36 .  
         [0020]     It is to be noted that in this embodiment, the first p-type MOS transistor  46  further comprises a well which is electrically coupled to the drain of the first p-type MOS transistor  46 . The second p-type MOS transistor  48  also further comprises a well which is electrically coupled to the drain of the second p-type MOS transistor  48 . Furthermore for simplification in explanation, it is assumed that the sizes of the first p-type MOS transistor  46  and the second p-type MOS transistor  48  are identical but not limited to what is disclosed. Moreover the well being electrically coupled to the drain is only one design choice of this embodiment which also comprises the situation where the connection is not available.  
         [0021]     Under the configuration of the high voltage selecting module  44  in this embodiment, if the absolute value of the difference between the first voltage V PP  and the second voltage V DD  is greater than the threshold voltage V TH  of the transistors  46 ,  48 , the voltage difference between the source and the gate will be greater than the threshold voltage so the channel is in conduct, therefore the output voltage VV is substantially the greater one of the first voltage V PP  and the second voltage V DD  If the absolute value of the difference between the first voltage V PP  and the second voltage V DD  is smaller than or equal to the threshold voltage V TH  of the transistors  46 ,  48 , in view of the fact that the wells of the transistors  46 ,  48  are respectively electrically coupled to the drain of the transistors  46 ,  48 , although the channel is not in conduct due to the difference between the source and the gate being smaller than or equal to the threshold voltage, because of the existence of a PN junction between the source and the well (i.e. the drain), the output voltage VV is substantially the higher one of the first voltage V PP  and the second voltage V DD  minus the junction voltage V D  that is between the source and the well (i.e. the diode voltage of an equivalent diode formed by the source and the well).  
         [0022]     As mentioned above, the output voltage VV generated by the high voltage selecting module  44  supplies the power supply voltage for the level shifting module  32 . Therefore, even when the problem mentioned in the related prior art happens, i.e. when the first voltage V PP  is at a lower level or even at 0V, the control signals ENVPPHV and ENVDDHV generated by the level shifting module  32  will not be overly low causing the power supply voltage switching circuit  30  to malfunction. The following is an actual example describing the operation of the power supply voltage switching circuit  30 . It is to be noted that in the following example, it is assumed that the threshold voltage V TH =0.7V for the first and second p-type MOS transistor  46  and  48  and the junction voltage V D =0.65V between the source and the well. Generally speaking, to take body effect into account, the threshold voltage of a MOS transistor is slightly larger than the junction voltage between the source and the well.  
         [0023]     First assume the first voltage V PP  is 1V and the second voltage V DD  is 3V. In this situation, the first p-type MOS transistor  46  is switched off and the second p-type MOS transistor  48  is switched on so the output voltage VV equals the second voltage V DD  which is 3V.  
         [0024]     The power supply voltage of the level-shifters  34  and  36  is 3V so when the first voltage V PP  is to be chosen as the power supply voltage V PS  the control circuit will set the logic value of the first control signal ENVPP to 0 (i.e. 0V) and the logic value of the second control signal ENVDD to 1 (i.e. 3V). After the level-shifting by the level shifting module  32 , the first control signal ENVPPHV will be 0V and the second control signal ENVDDHV will be 3V and they are inputted to the selecting switch module  38 . At this time, the first voltage V PP  is 1V and the second voltage V DD  is 3V so the third p-type MOS transistor  40  is switched on and the fourth p-type MOS transistor  42  is switched off. As a result, the power supply voltage V PS  is the first voltage V PP  (being 1V). Oppositely when the power supply voltage V PS  is to be chosen as the second voltage V DD  the control circuit will set the logic value of the first control signal ENVPP to 1 (i.e. 3V) and the logic value of the second control signal ENVDD to 0 (i.e. 0V). After the level-shifting by the level shifting module  32 , the first control signal ENVPPHV will be 3V and the second control signal ENVDDHV will be 0V and they are inputted to the selecting switch module  38 . At this time, the first voltage V PP  is 1V and the second voltage V DD  is 3V so the third p-type MOS transistor  40  is switched off and the fourth p-type MOS transistor  42  is switched on. As a result, the power supply voltage V PS  is the second voltage V DD  (being 3V).  
         [0025]     Following assume the first voltage is 3.5V and the second voltage is 3V. In this situation, the first p-type MOS transistor  46  is switched off and the second p-type MOS transistor  48  is switched off. Thus, the output voltage VV equals the second voltage V DD  minus V D,  that is 3.5V−0.65V=2.85V because the first voltage V PP  is in conduct with the output node through the PN junction that is formed between the source and the well.  
         [0026]     The power supply voltage of the level-shifters  34  and  36  is 2.85V so when the first voltage V PP  is to be chosen as the power supply voltage V VS  the control circuit will set the logic value of the first control signal ENVPP to 0 (i.e. 0V) and the logic value of the second control signal ENVDD to 1 (i.e. 3V). After the level-shifting by the level shifting module  32 , the first control signal ENVPPHV will be 0V and the second control signal ENVDDHV will be 2.85V and they are inputted to the selecting switch module  38 . At this time, the first voltage V PP  is 3.5V and the second voltage V DD  is 3V so the third p-type MOS transistor  40  is switched on and the fourth p-type MOS transistor  42  is switched off. As a result, the power supply voltage V PS  is the first voltage V PP  (being 3.5V). Oppositely when the power supply voltage V PS  is to be chosen as the second voltage V DD,  the control circuit will set the logic value of the first control signal ENVPP to 1 (i.e. 3V) and the logic value of the second control signal ENVDD to 0 (i.e. 0V). After the level-shifting by the level shifting module  32 , the first control signal ENVPPHV will be 3V and the second control signal ENVDDHV will be 0V and they are inputted to the selecting switch module  38 . At this time, the first voltage V PP  is 3.5V and the second voltage V DD  is 3V so the third p-type MOS transistor  40  is switched off and the fourth p-type MOS transistor  42  is switched on. As a result, the power supply voltage V PS  is the second voltage V DD  (being 3V).  
         [0027]     The power supply voltage selecting circuit of the present invention uses a high voltage switching circuit to supply power to the level-shifters according to an output voltage generated from either a first voltage or a second voltage. Therefore no matter how the level of the first voltage changes, the control signal after level-shifting can ensure the level is enough to allow the power supply voltage switching circuit to operate properly to alleviate the problem in the prior art.  
         [0028]     Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, that above disclosure should be construed as limited only by the metes and bounds of the appended claims.