Abstract:
A differential amplifier having two complementary differential pairs connected for rail-to-rail common mode input voltage range operation including a constant transconductance maintaining bias circuit is disclosed. The bias circuit provides a fixed rail current bias to a master differential pair and adjusts the bias to the second pair in response to variations in the bias level of the master pair. A unique biasing method and method of operating a differential amplifier are also disclosed.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to the field of differential amplifiers and more specifically to CMOS differential amplifiers intended to provide a rail-to-rail common mode input voltage range. 
     BACKGROUND OF THE INVENTION 
     CMOS amplifiers having the ability to accept common mode input voltages varying between the supply voltage rails are required in many applications, including input buffers and output drivers involving large signal swings. 
     An input circuit arrangement for providing a large common mode voltage input range employing a pair of complementary differential pairs is discussed in several articles: J. A. Fisher and R. Koch, &#34;A highly linear CMOS buffer amplifier,&#34; IEEE Journal of Solid State Circuits, Vol. 22, pp. 330-334, June 1987; M. Pardoen and M. Degrauwe, &#34;A rail-to-rail input/output CMOS power amplifier,&#34; Proc. Custom Integrated Circuits Conference, pp. 25.5.1-4, May 1989; J. F. Duque-Carillo, J. M. Valverde and R. Perez-Aloe, Constant G m  rail-to-rail common mode input stage with minimum CMRR degradation, IEEE journal of Solid State Circuits, Vol. 28, pp. 661-666, June 1993; and W-C. Wu, W. J. Helms, J. A. Kuhn and B. E. Byrkett, &#34;Digital-compatible high-performance operational amplifier with rail-to-rail input and output stages,&#34; IEEE Journal of Solid State Circuits, Vol. 29, pp. 63-66, January 1994. The output currents from the two pairs are summed together using current mirrors or can be directly injected into a folded cascode stage as discussed in J. A. Fisher and R. Koch, &#34;A highly linear CMOS buffer amplifier,&#34; IEEE Journal of Solid State Circuits, Vol. 22, pp. 330-334, June 1987; and M. Pardoen and M. Degrauwe, &#34;A rail-to-rail input/output CMOS power amplifier,&#34; Proc. Custom Integrated Circuits Conference, pp. 25.5.1-4, May 1989. 
     In the simplest form of this circuit, the tail current for each pair is held constant. Unfortunately, that arrangement leads to large variations in the net transconductance of the input stage as the common mode input voltage is varied. This large variation in net transconductance is undesirable because it leads to large variations in the unity gain frequency of the amplifier which makes optimal frequency compensation difficult to achieve especially in high frequency designs. 
     If the differential pairs are operated in the weak inversion region, i.e. , barely turned on, the transconductance is approximately proportional to the tail current. Then the large variation in net transconductance can be avoided by fixing the sum of the tail currents. The drawback of the weak inversion approach, however, is that the drain current will be relatively low for a given transistor size which in turn adversely impacts other factors such as slew rate. 
     Even for transistors operated in moderate to strong inversion regions, fixing the sum of the tail currents to a constant value reduces the large variation in net transconductance by a factor of √2, Although a substantial improvement in reducing the variation of net transconductance results, a substantial variation is still present over the common mode input voltage range. 
     As a result there is a need for a differential amplifier having a constant net transconductance over the entire common mode input voltage range. 
     SUMMARY OF THE INVENTION 
     An amplifier in accordance with one aspect of the present invention includes a differential amplifier arrangement allowing a rail-to-rail common mode input voltage range and a bias circuit connected to bias the amplifier at the desired operating point. The bias circuit manipulates the bias point of one amplifier section in response to variations in the bias level of a second amplifier section thereby maintaining a substantially constant net transconductance in the amplifier. 
     A method of operating an amplifier in accordance with another aspect of the present invention includes the steps of setting a first bias level for one amplifier section, setting a reference bias level representative of a predetermined amplifier operating point, setting the bias level for a second amplifier section according to a predetermined relationship between the reference bias level and the first bias level, and adjusting the second bias level in response to variations in the first bias level thereby maintaining a constant net transconductance for the amplifier. 
     A bias circuit for maintaining constant net transconductance in an amplifier in accordance with yet another aspect of the present invention includes a first fixed source for providing a first bias, a second source having a control input connected to monitor the level of the first bias, the second source providing a second bias dependent on the first bias level according to a predetermined relationship and responsive to variation in the first bias level to adjust the second bias level to maintain a substantially constant net transconductance in the amplifier. 
     Other features and advantages of the present invention will become readily apparent to those of ordinary skill in the art by reference to the following detailed description and accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
    
    
     A better understanding of the invention may be had from a consideration of the following Detailed Description, taken in conjunction with the accompanying drawings in which: 
     FIG. 1 is a schematic diagram of an amplifier input stage having a rail-to-rail common mode input voltage range using a pair of complementary differential pairs. 
     FIG. 2 is a plot of a simulation of the net transconductance versus common mode input voltage for an amplifier input stage shown in FIG. 1 and for a modified input stage. 
     FIG. 3 is a schematic diagram of a constant transconductance amplifier input stage having a rail-to-rail common mode input voltage range. 
     FIG. 4 is a plot of a simulation of the net transconductance versus common mode input voltage for the amplifier input stage of FIG. 3. 
    
    
     DETAILED DESCRIPTION 
     The present invention is best understood by comparison with the prior art. As a result, this detailed description begins with a discussion of a prior art amplifier input stage shown in FIG. 1. As discussed above, that circuit arrangement leads to large variations in net transconductance over the common mode input voltage range. Referring to FIG. 1, the net transconductance of the input stage for common mode input voltages between but not close to either of the positive and negative supply rails is given by the following equation: ##EQU1## Transistors M 1 , M 2  are scaled (approximately 2.5 to 1) versions of transistors M 7 , M 8  to make K 1  and K 2  equal. Equation [1] then simplifies to: ##EQU2## 
     Tail currents I 1 , I 2  are typically set equal to each other and remain so for values of common mode input voltage between and not too close to either of the supply rails, V DD  and ground. However, as the common mode input voltage (V i .sbsb.cm) approaches the positive supply rail V DD , the tail current I 2  in the p-channel complementary differential pair M 1 , M 2  approaches zero. Similarly, as the common mode input voltage approaches the negative supply rail (ground), tail current I 1  in the n-channel complementary differential pair M 7 , M 8  approaches zero. An inspection of equation [2] above reveals that the first or second term drops out as the common mode input voltage approaches V DD  or ground, respectively. The net transconductance in each case is then given by equations [3] and [4] respectively: ##EQU3## 
     Comparing equation [2] with either equation [3] or [4] reveals that the net transconductance of the input stage varies by a factor of two for large variations in the common mode input voltage. Referring to FIG. 2, a plot of the simulated variation of net transconductance of the input stage as a function of common mode input voltage is shown. The simulation was based on 0.9 micron CMOS technology and the device sizes have been chosen to match the transconductance of the pairs for a given tail current. The solid curve 1, shows the net transconductance variation for the input circuit of FIG. 1 which maintains each tail current I 1 , I 2  constant. The dashed curve 2, shows the net transconductance variation for an input stage having a pair of complementary differential pairs with the sum of the tail currents held constant. A comparison of curve 2 with curve 1 of FIG. 2 shows that some improvement in reducing the variations in net transconductance is achieved by fixing the sum of the tail currents. 
     Referring now to FIG. 3, one embodiment of the present invention is shown schematically and will be described. The components of the amplifier of FIG. 3 may suitably be comprised of components fabricated on a single integrated circuit substrate. The bias circuit 20 provides tail currents I 1 , I 2  to the amplifier 10 instead of the independent constant current sources shown in FIG. 1. Bias circuit 20 is designed to maintain a constant net transconductance in amplifier 10 by manipulating the magnitude of amplifier tail currents I 1 , I 2 . 
     The operation of bias circuit 20 will now be described in greater detail with reference to FIG. 3. It should be noted at the outset that transistors M 12 , M 13 , M 14 , M 15 , M 16 , and M 17  are assumed to be identical with a conductance constant K and threshold voltage V TP . This condition however is not necessary to the proper operation of the bias circuit which would work when these devices are properly scaled versions of each other. 
     The bias circuit 20 was designed to make the n-channel differential pair M 7 , M 8  of amplifier 10 the &#34;master&#34;. That is, the p-channel pair M 1 , M 2  is activated only when the tail current I 1  of the n-channel pair M 7 , M 8  starts to drop off. This occurs only at very low values of common mode input voltage. As a result, the p-channel current source M 17  is guaranteed to be in saturation whenever the p-channel pair M 1 , M 2  is contributing significantly to the net transconductance of the amplifier thereby maintaining a high power supply rejection ration (&#34;PSRR&#34;) over the entire common mode input voltage range. 
     A fixed voltage applied to V BIAS  is used to set the value of tail current I 1  which will be constant for all but very small values of common mode input voltage. Transistors M 9 , M 10 , M 11  provide a reference current 16 in bias circuit 20 which will track variations in tail current I 1 . Transistor M 9  is matched to transistor M 18  providing a current mirror. As long as transistors M 9  and M 18  are in saturation, transistor M 9  ensures that current I 6  will be equal to tail current I 1 . For low values of common mode input voltage, however, transistor M 18  will be forced out of saturation thus reducing tail current I 1 . Transistors M 10  and M 11 , which are matched to transistors M 7  and M 8 , force transistor M 9  to follow transistor M 18  out of saturation for low common mode input voltages. Current I 6  therefore will be equal to tail current I 1  over the entire common mode input voltage range. 
     The large signal transfer characteristics for enhancement mode MOSFETs in saturation are approximately given by equation [5] below which relates the transistor gate to source voltage (V gs ) to the square root of the drain current (I D ). ##EQU4## 
     Using equation [5] the following equations describing the operating points of the transistors of bias circuit 20 are obtained by inspection of FIG. 3. The drain current (I D ) of transistor M 12  is equal to the sum of currents I 6  and I 3 . Substitution into equation [5], thus provides the following equation for transistor M 12 . ##EQU5## 
     Similarly, the drain current (I D ) of transistor M 13  is equal to current I 4 . The operating point of transistor M 13  is, therefore, given by: ##EQU6## 
     Noting that the drain current of transistor M 14  is the sum of currents I 5  and I 4  and substitution into equation [5] provides: ##EQU7## 
     The drain current (I D ) of transistor M 17  is equal to tail current I 2 . Substituting I 2  into equation [5] thus yields the operating point of transistor M 17  as follows: ##EQU8## 
     The gate-to-source voltage (V gs ) of transistor M 16  is equal to the V gs  of transistor M 12  because their respective gates and sources are connected. 
     
         V.sub.gs (M.sub.16)=V.sub.gs (M.sub.12)                    [10] 
    
     Since the drain current (I D ) of transistor M 15  is equal to the drain current of transistor M 16 , the operating point of transistor M 15  is defined by combining equations [6] and [10] yielding: ##EQU9## 
     Further inspection of bias circuit 20 reveals that the sum of the gate-to-source voltages of transistors M 17  and M 15  is equal to the sum of the gate-to-source voltages of transistors M 13  and M 14 . The relationship of those gate-to-source voltages may be rewritten as follows: 
     
         V.sub.gs (M.sub.17)=V.sub.gs (M.sub.13)+V.sub.gs (M.sub.14)-V.sub.gs (M.sub.15)                                                [12] 
    
     Substituting equations [7], [8], [9], and [11] into equation [12] yields the following equation which defines the relationship of currents in bias circuit 20: ##EQU10## Substituting I 1  for I 6  in equation [13] and simplifying yields: ##EQU11## The currents I 3 , I 4  are used only to ensure that transistors M 13  and M 15  are biased with at least the minimum amount of current needed to keep them out of weak inversion. The values for currents I 3 , I 4  are thus chosen to be very small (less than 5% ) in comparison with I 5  and I 1 . As a result equation [14] is approximated by equation [15], below. ##EQU12## Equation [15] may be rewritten as follows: ##EQU13## Referring to FIG. 3, independent current source S 5  maintains current I 5  constant. Substituting equation [16] into equation [2] reveals that this is the required condition for constant net transconductance operation of amplifier 10. By maintaining the sum of the square roots of the tail currents I 1 , I 2  constant, bias circuit 20 substantially eliminates variations in net transconductance of amplifier 10 despite rail-to-rail variations in the common mode input voltage. 
     A simulation of the net transconductance of amplifier 10 using the bias circuit 20 is plotted in FIG. 4. The nominal tail currents I 1 , I 2  and input transistor M 1 , M 2 , M 7 , M 8  sizes are the same as those used for the simulations shown in FIG. 2. Referring to FIG. 4 reveals that the variation in net transconductance for rail-to-rail variations in common mode input voltage is substantially eliminated. The residual deviations from a perfectly flat line are partly due to the non-zero values of I 3  and I 4  and partly due to the second order factors in the transistor characteristics not included in equations [5] through [9] and [11]. 
     It is clear from FIG. 4 that the net transconductance of the amplifier of FIG. 3 is substantially constant over the entire common mode input voltage range. That represents a substantial improvement over the large variations in net transconductance present in prior art amplifiers plotted in FIG. 2. 
     From the foregoing description, it will be apparent that improvements in the biasing of amplifiers have been provided to maintain the net transconductance substantially constant despite rail-to-rail variations in common mode input voltage. While a preferred embodiment of the amplifier and bias circuit have been described, it should be appreciated that variations and modifications in the herein described amplifier and bias circuit, within the scope of the invention will be apparent to those skilled in the art. Accordingly, the foregoing description should be taken as illustrative and not in a limiting sense.