Abstract:
A resistive random access memory device, a method for manufacturing the resistive random access memory device, and a method for operating the resistive random access memory device are disclosed. The resistive random access memory device includes a resistive switching memory element including two electrodes and a layer of variable-resistance material between the two electrodes, wherein the layer of variable-resistance material exhibits bipolar resistive switching behavior; and a Schottky diode including a metal layer and a p-doped semiconductor layer which contact each other, wherein the metal layer of the Schottky diode is coupled to one of the two electrodes of the resistive switching memory element. The present disclosure provides the resistive random access memory device operating in bipolar resistive switching scheme.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates to a memory device, and in particular, to a resistive random access memory device (RRAM). 
         [0002]    The present disclosure also relates to a method for manufacturing the resistive random access memory device and a method for operating the resistive random access memory device. 
       BACKGROUND 
       [0003]    Today, advance of microelectronic industry also promotes memory technology to achieve an increased integration level and a reduced manufacture cost. Non-volatile memory devices maintain information data stored therein after power off and play an important role in information storage. 
         [0004]    One of novel non-volatile memory devices uses a variable-resistance material and has the advantages of high operation speed (&lt;5 ns), low power dissipation (&lt;1V) and easily being integrated with other semiconductor devices. Such non-volatile memory devices are a prospective candidate for next-generation memory devices. The resistive switching memory device typically has an metal-insulator-metal (MIM) configuration in which a layer of variable-resistance material is sandwiched between two metal electrodes. 
         [0005]    The variable-resistance material is typically a transition metal oxide, such as NiO, TiO 2 , HfO 2 , ZrO 2 , ZnO, or the like. The variable-resistance material can have two stable states, i.e. a high-resistance state and a low-resistance sate, which correspond to digital “0” and digital “1” respectively. A change from the high-resistance state to the low-resistance state is referred to as programming or SET operation, and a change from the low-resistance state to the high-resistance state is referred to as erasing or RESET operation. 
         [0006]    The resistive switching memory devices can be classified as unipolar or bipolar devices according to its operation scheme. According to the former, a voltage is applied across a resistive switching memory device in one direction, and changes a resistance state of a variable-resistance material between a high-resistance state and a low-resistance with different amplitudes of the voltage to write data into the resistive switching memory device or erase data therefrom. According to the latter, a voltage is applied across the resistive switching memory device in two opposite directions for changing the resistance state of the variable-resistance material respectively. The bipolar resistive switching memory devices are superior to the unipolar resistive switching memory devices in memory performances such as switching speed, uniformity, reliability (data retention and endurance), controllability, or the like. 
         [0007]    The resistive switching memory devices can be classified as 1T-1R configuration or 1D-1R configuration according to its basic configuration. Each memory cell in the 1T-1R configuration includes one select transistor and a resistive switching memory cell. By controlling the select transistor, data can be written into a selected memory cell or erased therefrom. Because the select transistor is used, it occupies a major portion of a footprint of the memory cell, which hinders an increase of the integration level. Each memory cell in 1D-1R configuration includes one diode and a resistive switching memory cell. By controlling the diode, data can be written into a selected memory cell or erased therefrom. Because the diode typically occupies an area less than a transistor, the memory cell in 1D-1R configuration is advantageous in an increase of the integration level. 
         [0008]    However, conventional resistive switching memory devices in 1D-1R configuration can only operate in unipolar resistive switching scheme due to limited material properties of the diode, which in turn limits memory performances. 
       SUMMARY OF THE DISCLOSURE 
       [0009]    One object of the present disclosure is to provide a resistive random access memory device in 1D-1R configuration and operating in bipolar resistive switching scheme. 
         [0010]    Another object of the present disclosure is to provide a method for manufacturing the resistive random access memory device and a method for operating the resistive random access memory device. 
         [0011]    A Schottky diode including contacted metal and semiconductor exhibits a relatively large reverse current which dependents on a metal material under an external bias. The inventor proposes a series configuration of the Schottky diode and a bipolar resistive switching memory element to provide a resistive random access memory device in 1D-1R configuration and operating in bipolar resistive switching scheme. The Schottky diode has suitable property parameters under a positive voltage and a negative voltage. 
         [0012]    Moreover, the disclosure proposes a feasible operation scheme for the above resistive random access memory device in 1D-1R configuration. 
         [0013]    According to one aspect of the present disclosure, there is provided a resistive random access memory device, comprising: a resistive switching memory element including two electrodes and a layer of variable-resistance material between the two electrodes, wherein the layer of variable-resistance material exhibits bipolar resistive switching behavior; and a Schottky diode including a metal layer and a semiconductor layer which contact each other, wherein the metal layer of the Schottky diode is coupled to one of the two electrodes of the resistive switching memory element. 
         [0014]    According to another aspect of the present disclosure, there is provided a method for manufacturing the above resistive random access memory device, comprising: a) forming a polysilicon layer on a substrate; b) doping the polysilicon layer with dopants to form a p-doped polysilicon layer; c) annealing the p-doped polysilicon layer to activate the dopants; d) forming a first metal layer on the p-doped polysilicon layer; e) forming a layer of variable-resistance material on the first metal layer; f) forming a second metal layer on the layer of variable-resistance material; g) patterning a stack of the p-doped polysilicon layer, the first metal layer, the layer of variable-resistance material and the second metal layer to separate a plurality of resistive random access memory devices. 
         [0015]    According to another aspect of the present disclosure, there is provided a method for operating the above resistive random access memory device, wherein the semiconductor layer of the Schottky diode is coupled to a bit line, and the other of the two electrodes of the resistive switching memory element is coupled to a word line, 
         [0016]    during read operation, a negative voltage V read  is applied to the resistive switching memory element between the word line and the bit line; 
         [0017]    during programming operation, a positive voltage V +  is applied to the resistive switching memory element between the word line and the bit line; 
         [0018]    during erasing operation, another negative voltage V −  is applied to the resistive switching memory element between the word line and the bit line, 
         [0019]    wherein V read , V +  and V −  satisfy, 
         [0000]        V   SET   +V   s   &lt;V   +   &lt;V   SET +2 V   s   +V   t    
         [0000]        V   RESET   +V   t   &lt;V−&lt;V   SET +2 V   t   +V   s    
         [0000]    
       
      
       V 
       t 
       &lt;V 
       read 
       &lt;V 
       RESET 
       +V 
       t  
      
     
         [0020]    where V SET , I SET  and V RESET  are parameters which depend on the variable-resistance material of the resistive switching memory element, and represent a minimum voltage and a minimum current required for changing the resistive switching memory element from a high-resistance state to a low-resistance state and a minimum voltage required for changing the resistive switching memory element from the low-resistive state to the high-resistance state respectively, V s  and V t  represent a reverse saturation voltage and a threshold voltage of the Schottky diode respectively, and I s  represents a reverse saturation current of the Schottky diode, wherein the doping concentration of the semiconductor layer of the Schottky diode is tuned so that I s  satisfies I SET &lt;I s &lt;2 I SET . 
         [0021]    The resistive random access memory device according to the present disclosure has 1D-1R configuration and operates in bipolar resistive switching scheme. It occupies a relatively small footprint of a wafer, such as 4F 2 , where F represents a feature size. Moreover, it has improved memory performances when compared with unipolar resistive random access memory devices, such as high switching speed, small erasing current, small resistance, small voltage variations, long data retention time and high reliability. 
         [0022]    The Schottky diode in the resistive random access memory device is faster than other types of diodes, which can further increase operation speed and reliability. Moreover, the Schottky diode has current density larger than other types of diodes and can limit a current during programming operation, which can further increase endurance and reduce resistance variation. 
         [0023]    The Schottky diode has desired value of reverse saturation current by precisely tuning doping of the semiconductor layer. Furthermore, a process for forming a Pt—Si based Schottky diode is simple and compatible to conventional semiconductor processes. Thus, the resistive random access memory device according to the present disclosure can be mass-produced. 
         [0024]    By limiting voltages for read operation, programming operation and erasing operation in specific ranges, an unintended read operation on an adjacent resistive random access memory can be avoided when operating a selected resistive random access memory. A plurality of resistive random access memory devices according to the present disclosure can be arranged an array with a high density. Each of the plurality of resistive random access memory devices is located at a cross point of a bit line and a word line as a memory cell. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0025]      FIG. 1  schematically shows an array of resistive random access memory devices according to the present disclosure; 
           [0026]      FIG. 2  schematically shows a cross section of a memory cell of the array of resistive random access memory devices shown in  FIG. 1 , where the memory cell is a resistive random access memory device comprising a variable-resistance memory element and a Schottky diode; 
           [0027]      FIG. 3  schematically shows bit lines and word lines for programming/erasing the resistive random access memory devices shown in  FIG. 1 ; 
           [0028]      FIG. 4  is a typical I-V curve of one resistive random access memory device shown in  FIG. 1 ; and 
           [0029]      FIG. 5  is an equivalent circuit diagram of four resistive random access memory devices shown in  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0030]    Exemplary embodiments of the present disclosure will be described in more details below with reference to the accompanying drawings. In the drawings, like reference numerals denote like members. The figures are not drawn to scale, for the sake of clarity. 
         [0031]    It should be understood that when one layer or region is referred to as being “above” or “on” another layer or region in the description of device structure, it can be directly above or on the other layer or region, or other layers or regions may be intervened therebetween. Moreover, if the device in the figures is turned over, the layer or region will be “under” or “below” the other layer or region. 
         [0032]    In contrast, when one layer is referred to as being “directly on” or “on and adjacent to” or “adjoin” another layer or region, there are not intervening layers or regions present. 
         [0033]    In the present application, the term “semiconductor structure” means generally the whole semiconductor structure formed at each step of the method for manufacturing the semiconductor device, including all of the layers and regions having been formed. 
         [0034]    Some particular details of the present disclosure will be described below, such as exemplary semiconductor structures, materials, dimensions, process steps and technologies of the semiconductor device, for better understanding of the present disclosure. However, it can be understood by one skilled person in the art that these details are not always essential for but can be varied in a specific implementation of the disclosure. 
         [0035]    Unless the context clearly indicates otherwise, each part of the semiconductor device can be made of material (s) well known to one skilled person in the art. 
         [0036]      FIG. 1  schematically shows an array of resistive random access memory devices according to the present disclosure, including 3×3 memory cells. 
         [0037]    The array of resistive random access memory devices comprises word lines  10  and bit lines  11 , and p-doped polysilicon layer  14 , a metal layer  13  (for example, Pt) and a layer  12  of variable-resistance material from bottom to top between the word lines  10  and the bit lines  11 . The word lines  10  and the bit lines  11  are typically arranged to be perpendicular to each other. Each of the plurality of resistive random access memory devices is located at a cross point of a word line  10  and a bit line  11  as a memory cell. 
         [0038]    Each memory cell has 1D-1R configuration, including a resistive switching memory element and a Schottky diode which are connected with each other in series (see  FIG. 2 ). The Schottky diode  130  comprises a p-doped polysilicon layer  14  and a metal layer  13 . The resistive switching memory element  120  is located above the Schottky diode  130 , and comprises a word line  10  which is also a top electrode, a layer  12  of variable-resistance material, and a metal layer  13  which is a bottom electrode. 
         [0039]    The Schottky diode  130  and the resistive switching memory element  120  share the metal layer  13  and are connected directly with each other by the metal layer  13 , which facilitates decreasing connection resistance and further decreasing a driving current. 
         [0040]    Alternatively, the resistive switching memory element  120  may have a separate top electrode which is formed from a metal layer the same as that of the word line  10  in the same or different steps and in the same or different apparatus, or different from that of the word line  10  in different steps and/or in different apparatus. 
         [0041]    Although not shown in  FIGS. 1 and 2 , it can be understood that an insulating material (for example, an oxide) can be formed between memory cells (i.e. around the semiconductor structure shown in  FIG. 2 ) to isolate various resistive random access memory devices. 
         [0042]      FIG. 3  schematically shows bit lines and word lines for programming/erasing the resistive random access memory devices shown in  FIG. 1 . When operating a memory cell, a voltage V is applied to, for example, a word line WL 2 , a zero voltage 0 V is applied to, for example, a bit line BL 2 , other word lines WL 0 -WL 1 , WL 3 -WL 4  and other bit lines BL 0 -BL 1 , BL 3 -BL 4  are floating. The memory cell at a cross point of the word line WL 2  and the bit line BL 2  is selected. Due to the diode, the memory cells at cross points of other word lines and other bit lines are disconnected from the external voltage, and are not selected. 
         [0043]      FIG. 4  is a typical I-V curve of one resistive random access memory device shown in  FIG. 1 . The magnitude and the polarity of the applied voltage V determines read operation or write operating of the memory device. In the resistive random access memory device shown in  FIG. 2 , the Schottky diode is turned on by a negative voltage and turned off by a positive voltage. 
         [0044]    During programming operation, the selected memory cell is changed to a low-resistance state when a voltage across the layer of variable-resistance material goes beyond V SET . However, due to the fact that the diode is reversely biased, the external voltage actually applied to the word line is a little larger, for example, about 1.5˜2 times of V SET . Moreover, a reverse current of the Schottky diode near the external voltage V SET  needs to be larger than a current through the resistive switching memory element when the resistive switching memory element is in a high-resistance state so as to ensure that the layer of variable-resistance material is changed from the high-resistance state to a low-resistance state. This requires that the Schottky diode provides a sufficiently reverse current. 
         [0045]    During erasing operation, the selected memory cell is changed to a high-resistance state when a voltage across the layer of variable-resistance material goes beyond −V RESET . Due to a small value of forward resistance of the diode, only a negative voltage slightly larger than V RESET  is needed to be applied to the word line. 
         [0046]    During read operation, a relatively small negative voltage, between a threshold voltage V t  of the diode and V RESET , is needed to be applied to the word line so as to ensure that original data is not destroys while the diode is turned on. 
         [0047]      FIG. 5  is an equivalent circuit diagram of four resistive random access memory devices shown in  FIG. 1 . When a memory cell is selected, other word lines and other bit lines are floating. However, there is actually other conductive path for the selected memory cell in the array. As shown in  FIG. 5 , when a word line WL 1  and a bit line BL 1  are selected, a current flows through one conductive path WL 1 -R 1 -D 1 -BL 1  (referred to as “selected path” hereinafter) and another conductive path WL 1 -R 2 -D 2 -BL 2 -D 3 -R 3 -WL 2 -R 4 -D 4 -BL 1  (referred to as “additional conductive path” hereinafter). In most cases, due to D 2 , D 3  and D 4 , the current through the additional conductive path has a small value and can be omitted. 
         [0048]    However, in certain cases, the current through the additional conductive paths interfere with operations on the selected memory cell. To avoid interference, the current flowing through the resistive switching memory element and the Schottky diode should be limited. 
         [0049]    During read operation, the interference occurs only in a case that R 1  is in a high-resistance state and all of R 2 , R 3  and R 4  are in a low-resistance state. It requires that a reverse current of the Schottky diode near V read  has a value much smaller than a current through the resistive switching memory element when the resistive switching memory element is in a low-resistance state, as normally achieved by a conventional Schottky diode. 
         [0050]    During programming operation, R 2  (R 4 ) may be changed to a low-resistance state by SET operation in a case that R 2  (R 4 ) is in a high-resistance state and R 3  and R 4  (R 2 ) are in a low-resistance state, while R 2  (R 4 ) is connected in series with two reversely-biased diodes D 2  and D 4 . It requires that a reverse current of the Schottky diode have a value of the same order of the current through the resistive switching memory element when the resistive switching memory element is in a high-resistance state, and a voltage for programming operation slightly larger than a critical of the 1D1R configuration, so as to ensure that adjacent 2D1 R configuration is not unintendedly programmed. 
         [0051]    During erasing operation, R 3  may be changed to a low-resistance state by SET operation in a case that R 2  and R 4  are in a low-resistance state and R 3  is in a high-resistance state, while R 3  is connected in series with a reversely-biased diode D 3 . It requires that a voltage for erasing operation either has a value smaller than a voltage for programming operation, or has a value larger than the voltage for programming operation but smaller than a sum of the voltage for programming operation and threshold voltages of the two diodes. 
         [0052]    In view of the above, the reverse current of the Schottky diode should be carefully designed to have a value sufficiently large for programming operation but not for turning on unselected memory cells. All suitable values of voltages and currents for operating a selected memory cell are summarized in table 1. Relevant parameters are defined in table 2. 
         [0000]    
       
         
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 Parameters 
                 Requirements 
               
               
                   
                   
               
             
             
               
                   
                 V +   
                 V SET  + V s  &lt; V +  &lt; V SET  + 2V s  + V t   
               
               
                   
                 V −   
                 V RESET  + V t  &lt; V −  &lt; V SET  + 2V t  + V s   
               
               
                   
                 V read   
                 V t  &lt; V read  &lt; V RESET  + V t   
               
               
                   
                 I s   
                 I SET  &lt; I s  &lt; 2 I SET   
               
               
                   
                   
               
             
          
         
       
     
         [0000]    
       
         
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 Parameters 
                 Meaning 
               
               
                   
               
             
             
               
                 V +   
                 external positive voltage applied between a word line 
               
               
                   
                 and a bit line for changing a resistance state of a 
               
               
                   
                 memory cell from a high-resistance state to a low- 
               
               
                   
                 resistance state (programming operation) 
               
               
                 V −   
                 external negative voltage applied between a word line 
               
               
                   
                 and a bit line for changing a resistance state of a 
               
               
                   
                 memory cell from a low-resistance state to a high- 
               
               
                   
                 resistance state (erasing operation) 
               
               
                 V read   
                 external negative applied between a word line and a bit 
               
               
                   
                 line for determining a resistance state of the memory 
               
               
                   
                 cell (read operation) 
               
               
                 V SET   
                 a minimum voltage for changing a resistance state of 
               
               
                   
                 the memory cell from a high-resistance state to a low- 
               
               
                   
                 resistance state 
               
               
                 V RESET   
                 a minimum voltage for changing a resistance state of 
               
               
                   
                 the memory cell from a low-resistance state to a high- 
               
               
                   
                 resistance state 
               
               
                 I SET   
                 a minimum current for changing a resistance state of the 
               
               
                   
                 memory cell from a high-resistance state to a low- 
               
               
                   
                 resistance state, I SET  is slightly larger than V SET /R H   
               
               
                 R L   
                 a resistance value of the memory cell when it is in a 
               
               
                   
                 low-resistance state 
               
               
                 R H   
                 a resistance value of the memory cell when it is in a 
               
               
                   
                 high-resistance state 
               
               
                 I s   
                 a revere saturation current of the diode 
               
               
                 V s   
                 a voltage across the diode near saturation 
               
               
                 V t   
                 a threshold voltage of the diode 
               
               
                   
               
             
          
         
       
     
         [0053]    An exemplary embodiment of a method for operating a resistive random access memory device according to the present disclosure includes: 
         [0054]    during read operation, a negative voltage of about −0.5V-−1V is applied between a word line and a bit line, at which a Schottky diode has a reverse current of less than 5 uA; 
         [0055]    during programming operation, a positive voltage of about 2V-5V is applied between the word line and the bit line, at which the Schottky diode has a reverse current of about 10-100 uA; 
         [0056]    during read operation, a negative voltage of about −2V-−5V is applied between the word line and the bit line. 
         [0057]    An exemplary embodiment of a method for manufacturing resistive random access memory devices arranged in an array of a plurality of memory cells according to the present disclosure includes the follow steps. 
         [0058]    A metal layer (for example, aluminium) for bit lines is formed on a silicon substrate, for example, by physical vapor deposition (PVD). The metal layer has a thickness of about 10-100 nm. The metal layer is then formed as a plurality of bit lines  11  by pattering the metal layer into stripes. The bit lines  11  have a width and a pitch between adjacent ones, both of which depend on resolution of lithography. 
         [0059]    The patterning process may involve following steps: a photoresist mask having a pattern therein is formed on the metal layer, by a conventional lithographical process including exposure and development steps; the exposed portions of the metal layer are removed by dry etching such as ion beam milling, plasma etching, reactive ion etching, laser ablation and the like, or wet etching using a solution of etchant, stopping on the top of the silicon substrate  1 ; and the photoresist mask is then removed by ashing or dissolution with a solvent. 
         [0060]    An insulating layer (for example, silicon dioxide) is then formed on the surface of the entire semiconductor structure, for example, by chemical vapor deposition (CVD). The insulating layer has a thickness of about 20-200 nm. The semiconductor structure is then planarized by chemical mechanical polishing (CMP) with the metal layer of the bit lines  11  as a stop layer, until the top surface of the bit lines  11  is exposed. 
         [0061]    A polysilicon layer is then formed on the entire semiconductor structure, for example, by CVD. The polysilicon layer has a thickness of about 30-500 nm. The polysilicon layer is doped with boron or boron fluoride at a certain doping concentration by ion implantation, followed by an anneal at about 600-800° C. A p-doped polysilicon layer  14  is thus formed. 
         [0062]    As mentioned above, external voltages will be applied to the resistive random access memory device according to the present disclosure during operation in accordance with requirements listed in table 1. Thus, a voltage for changing a resistance state of a resistive switching memory element and a reverse current of a Schottky diode should be carefully limited to a range. 
         [0063]    By tuning a doping concentration of the p-doped polysilicon layer  14  of the Schottky diode  130  in the above ion implantation, a forward current and a reverse current of the Schottky diode  130  can have suitable values. 
         [0064]    Preferably, the doping concentration of boron in the p-doped polysilicon layer  14  may be in the range of about 10 13 ˜10 18 /cm 3 . 
         [0065]    A metal layer  13  (for example, Pt) is then formed on the entire semiconductor structure, for example, by PVD. The metal layer  13  has a thickness of about 10-100 nm. The Schottky diode  130  comprises the p-doped polysilicon layer  14  and the metal layer  13 . The metal layer  13  is also used as a bottom electrode of a resistive switching memory element to be formed. A layer  12  of variable-resistance material (for example, HfO 2 ) is then formed on the surface of the entire semiconductor structure by the above conventional deposition process. The layer  12  of variable-resistance material has a thickness of about 5-50 nm. 
         [0066]    The p-doped polysilicon layer  14 , the metal layer  13  and the layer  12  of variable-resistance material are then patterned to a plurality of separate stacks of square or circle shape. Each stack (for example, of square shape) will be a memory cell. The stacks of square shape are aligned to the bit lines, and typically have a width and a pitch between adjacent ones the same as those of the bit lines. 
         [0067]    An insulating layer (for example, silicon dioxide) is then formed on the entire semiconductor structure, for example, by CVD. The insulating layer has a thickness of about 50-800 nm. The semiconductor structure is then planarized by CMP until the top surface of the layer  12  of variable-resistance material is exposed. 
         [0068]    A metal layer (for example, Pt or TiN) is then formed for word lines on the entire semiconductor structure, for example, by PVD. The metal layer has a thickness of about 10-100 nm. The metal layer is then formed as a plurality of word lines  10  by pattering the metal layer into stripes. The word lines are perpendicular to the bit lines and have a width and a pitch between adjacent ones the same as those of the bit lines. 
         [0069]    The word lines  10  are also used as a top electrode of the resistive switching memory element  120 . 
         [0070]    Alternatively, the resistive switching memory element  120  may have a separate top electrode which is formed from a metal layer the same as that of the word line  10  in the same or different steps and in the same or different apparatus, or different from that of the word line  10  in different steps and/or in different apparatus. 
         [0071]    An insulating layer (for example, silicon dioxide) is then formed on the entire semiconductor structure, for example, by CVD. The insulating layer has a thickness of at least about 150 nm and is used as isolation between a memory cell and other memory cells or other components of the memory. 
         [0072]    Subsequent steps for forming wirings, for passivation, or for other purposes may be continued to complete the structure of the resistive random access memory device according to the present disclosure. These subsequent steps are well known by one skilled person. 
         [0073]    While the disclosure has been described with reference to specific embodiments, the description is illustrative of the disclosure. The description is not to be considered as limiting the disclosure. Various modifications and applications may occur for those skilled in the art without departing from the true spirit and scope of the disclosure as defined by the appended claims.