Abstract:
An electronic image sensor with a pixel array of a plurality of active pixels is provided. Each of the active pixels includes: a photo detector, providing a sensing node for producing a signal based on an amount of light incident thereon; a storing node for storing a plurality of photo-generated charges according to the signal; a first controllable potential barrier between the sensing node and the storing node; an outputting node; and a second controllable potential barrier between the storing node and the outputting node, wherein each of the sensing node, the storing node and the sampling node is not overlapped.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to CMOS sensors, and more particularly, to a method and apparatus for providing simultaneous electronic shutter action (SESA) frame storage and correlated double sampling (CDS) simultaneously in the CMOS sensors. 
         [0003]    2. Description of the Prior Art 
         [0004]    Digital cameras are commonly used today. Typically, a digital camera contains image sensors for converting light into electrical charges. Generally, image sensors can be divided into two broad categories according to the applied manufacturing process: CCD (charge-coupled device) sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors, where the CMOS image sensors (CIS) are based on the CMOS technologies. 
         [0005]    For CMOS image sensors, a pixel is an element of an image sensor implemented for generating a differentiable strength output signal; the differentiable strength output signal is proportional to the strength of incident light. Each pixel within the image sensor is also implemented for detecting, storing, and outputting a signal. Typically, CMOS sensors use an “active pixel” for image sensing rather than use a “passive pixel” within. In brief, a pixel with an amplifier or signal buffer is called an “active pixel”, while a pixel with only a photo detector and a switch is defined as a “passive pixel”. With regards to a typical “active pixel” CMOS image sensor, each active pixel contains a photodiode for sensing light and a parasitic capacitor for holding the received signal. 
         [0006]    Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a conventional structure of an active pixel. As shown in  FIG. 1 , an active pixel  100  contains three nodes  101 ,  103  and  105 . The node  101  is a detecting node for detecting a signal; the node  103  is a storing node for storing the signal; and the node  105  is a sampling node for outputting the signal. In different cases, the detecting node (i.e., node  101 ), storing node (i.e., node  103 ) and sampling node (i.e., node  105 ) can be overlapped (e.g., using only one node for executing the three functions) or separated, depending on different design requirements of image sensors. 
         [0007]    In  FIG. 1 , the active pixel  100  further contains an amplifier (AMP)  106 , where the amplifier  106  (e.g., an in-pixel amplifier) amplifies the sampled signal from the sampling node (i.e., the node  105 ) to thereby generate an output  107 . The output  107  is then sent to other circuitry in a digital camera (not shown) for follow-up processes. In addition, the active pixel  100  shown in  FIG. 1  can further contain two gateways  102  and  104 , coupled between the nodes  101  and  104  and coupled between the nodes  103  and  105  respectively. As active pixel gateways are known to those skilled in this art, further description is omitted here for brevity. 
         [0008]    For CMOS image sensors with active pixels, correlated double sampling (CDS) is often adopted to eliminate a low-frequency noise within the CMOS image sensors. The operating scheme of the CDS operation is described as follows. 
         [0009]    For the CDS operation, at time t=t 1 , a first voltage signal readout v out1 =v n1  is obtained, where V n1  illustrates noise at the sampling node (i.e., the node  105 ). At time t=t 2 =t 1 +Δt, a signal is added to the sampling node (i.e., the node  105 ), and then a second signal readout, i.e., v out2 =v n2 +v sig  is obtained immediately. That is, in the CDS operation, the first readout is for capturing noise, and the second readout is for capturing both the undesired noise (V n2 ) and the demanded signal (V sig ). 
         [0010]    Thereafter, the CDS operation extracts the demanded signal by subtracting the first sampled value derived from the first signal readout from the second sampled value derived from the second signal readout. The extracted signal ΔVout hence can be represented as below: 
         [0000]      Δ v   out =v out2   −v   out1 =( v   n2   +v   sig )−(v n1 )=( v   n2   −v   n1 )+ v   sig  
 
         [0011]    In a case where the low-frequency noise dominates and Δt is small enough, a value (v n2 −v n1 ) at this time will be close to zero, thus achieving a desired output: Δv out ≅v sig . 
         [0012]    That is, the CDS operation acts as a high-pass filter for filtering out undesired low-frequency noise. The smaller the value of Δt; the higher the cutoff frequency, which further suppresses noise. The Δt between two readouts should be as small as possible. Typically, for an effective CDS in an image sensor with active pixels, Δt should be in the order of a few microseconds or smaller. However, for an active pixel to perform the CDS function, two separated storing nodes for signal storage are necessary, although one of the storing nodes may simultaneously have other functions, e.g., signal detecting or sampling. In addition, a complete CDS readout also requires CDS operation in the readout circuitry, which adds its own noise to the data. 
         [0013]    Please refer to  FIG. 2 ;  FIG. 2  is a diagram illustrating a typical electronic image sensor  200 . As shown in  FIG. 2 , the electronic image sensor  200  contains a pixel array  210  (i.e., the pixel array  210  has M*N pixels  215  arranged in a matrix format with N rows  214  and M columns  216 ) and M column processors  220  coupled to M columns  216  respectively. Due to the column processors  220  are only capable of processing one row  214  at a time, a scheme for only executing a reset operation or a readout operation at a time is adopted in such an electronic image sensor (e.g., the electronic image sensor  200  shown in  FIG. 2 ), where the scheme is usually called “rolling” reset and readout scheme. In general, each readout operation of one individual row  214  usually takes more than a few microseconds. As a result, an image sensor with 1000 rows takes more than a few milliseconds for successfully getting readout data of a full frame. However, the very long required time creates artifacts on moving object images and further results in image blurring. These effects are not desirable for modern digital cameras (i.e., electronic image sensors) and other imaging equipment. 
         [0014]    In face, it is preferable in most cases to perform a snapshot operation and a simultaneous electronic shutter action (SESA) operation. The “snapshot” function synchronizes all pixels in an image sensor to simultaneously start and stop exposure. The process to achieve higher shutter speed in an electronic image sensor by controlling the start and stop of integration (exposure) is called “Simultaneous Electronic Shutter Action (SESA)”. The SESA operation ensures that all pixels capture the image of a scene at the very same moment. Unfortunately, the designs of the existing CMOS image sensors can not provide both a complete CDS function and the SESA functionality simultaneously. As mentioned above, there are a plurality of different structures of APS pixel, such as 3T APS pixel, 4T APS pixel (e.g., a photogate APS), 5T APS pixel, etc. depending on design requirements. Descriptions for these different APS pixels are as follows. 
         [0015]    Please refer to  FIG. 3 ;  FIG. 3  is a diagram illustrating a conventional structure of a 3T APS (active pixel structure) pixel  300 . In  FIG. 3 , the 3T active pixel  300  contains three transistors  306 ,  309  and  310  and the 3T active pixel  300  possesses a non correlated double sampling functionality. Here the node  308  is implemented for executing all the detecting, storing and outputting operations. Please note that, the 3T APS pixel  300  has more elements; however, since the structure of the 3T APS pixel is known to those skilled in this art, further description is omitted here. 
         [0016]    Please refer to  FIG. 4  in conjunction with  FIG. 3 .  FIG. 4  is a timing diagram illustrating a plurality of signals of a CMOS image sensor containing N rows of the 3T APS pixels  300  in a pixel array. As shown in  FIG. 4 , the pixel array of the CMOS image sensor in this case operates in a “rolling row” manner, where the rolling manner has been explained in the above descriptions of rolling reset and readout operation. The timing signals for a row therefore resemble the predecessor row, but are delayed by one row at a given time. As shown in  FIG. 4 , for each row of the pixel array to execute a non-correlated double sampling functionality, there are two timing signals, including a reset signal and a row select signal. For instance, in  FIG. 4 , an operation of a row  1  within the pixel array is described as follows, where the CMOS image sensor here employs 3T active pixels  300 . The operation flow for one row includes the following steps: 
         [0017]    Step 1: For the row  1  as shown in  FIG. 4 , firstly a reset operation is executed. The node  308  (as shown in  FIG. 3 ) is reset via turning on the reset transistor  310  (a pulse  1  of a reset signal  310 A occurs in  FIG. 4 ), then turns off the Reset transistor  310  in  FIG. 3  to start a charge integration during the integration time such that: v 1 ( 1 )=v reset1 +v n1 , where the voltage V 1 ( 1 ) is an extracted voltage expressed a noise level signal ( FIG. 4 ), and the reset signal  310 A expressed the voltage signal applied to the gate terminal of the reset transistor  310 . 
         [0018]    Step 2: The CMOS image sensor executes a first readout operation for the row  1  to sample (signal+noise) level, thereby extracting a rudimentary output voltage V out1 : v out1 =v 1 ( 2 )=v reset1 +v n1 +v sig . The voltage V out1  (i.e., V 1 ( 2 )) represents an extracted voltage when turning on the row select transistor  306  (a pulse  2  of the row select signal  306 A in  FIG. 4 ). 
         [0019]    Step 3: A second reset operation is executed for the node  308  via turning on the reset transistor  310  (i.e., a pulse  3  of the reset signal  310 A occurs) to thereby extracts a voltage: v 1 ( 3 )=v reset2 +v n2 , where the voltage V 1 ( 3 ) represents the extracted voltage at this time. 
         [0020]    Step 4: A second readout operation is executed for completing an operation cycle of one particular row (e.g., the row  1  in this case). The second reset level is sampled in the second readout operation, hence: v out2 =v reset2 +v n2 , where the voltage V out2  represents an extracted voltage via turning on the row select transistor  306  (i.e., a pulse  4  of the row select signal  306 A occurs in  FIG. 4 ). 
         [0021]    The above four steps complete an operation cycle for one certain row in one frame. With the execution of aforementioned steps 1-4, an output of a pixel can be extracted as: 
         [0000]        v   out   =v   out1   −v   out2   =v   sig +( v   reset1   −v   reset2 )+( v   n1   −v   n2 ). 
         [0022]    In general, v reset1 −v reset2 ≈0, but (v n1 −v n2 )=√{square root over (2)}·{tilde over (v)} n  ({tilde over (v)} n  is the root-mean-square noise value), due to the fact that two samples (readouts) are not correlated to each other. Therefore, a final output of non correlated double sampling functionality in  FIG. 4  becomes: v out =v sig +√{square root over (2)}·{tilde over (v)} n . 
         [0023]    The 3T APS pixel  300  has some unwelcome drawbacks due to no true CDS (correlated double sampling) operation. This is because there being only one node  308  for signal detection, storage and sampling; once a charge integration of pixels in a row ends at the first readout, the subsequent second reset then destroys the signal. 
         [0024]    Please refer to  FIG. 5 ;  FIG. 5  illustrates one conventional structure of 4T APS pixel  500 . Compared with  FIG. 3 , the 4T APS Pixel  500  has one node for both signal detecting and storing, and another node  504  for signal sampling. The pixel array, however, still has to operate in a “rolling row” manner. 
         [0025]    Please refer to  FIG. 6  in conjunction with  FIG. 5 .  FIG. 6  is a timing diagram for the photogate APS pixel  500  in  FIG. 5 . Here the 4T APS pixel  500  has a true CDS functionality, and operates according to a reset signal  310 A of a reset transistor  310  ( FIG. 5 ), a row select signal  306 A for a row select transistor  306  ( FIG. 5 ), a photodiode signal  502 A for a photodiode  502  ( FIG. 5 ), and a transmit signal  503 A for a transfer gate ( FIG. 5 ), whenever with appropriate adjustments the photodiode  502  can be replace by a photogate. In this case, a voltage of the photodiode signal  502 A increases to start a charge integration after a reset operation for the sampling node  504  finishes. Before charge integration stops, the reset transistor  310  turns on for resetting the sampling node  504 . The induced noise is left at the sampling node  504 . 
         [0026]    During the first read out operation, a noise is sampled accordingly as: v out1 =v reset +v n1 . Then, a voltage of the transmit signal  503 A rises to turn on the transfer transistor  503  and a voltage of the photodiode signal  502 A falls, and the charges stored underneath the photodiode  502  are transferred to the sampling node  504 . The second readout (i.e., signal+noise) is sampled as: v out2 =v sig +v reset +v n1 . In this way, the output can be extracted from the two corrected samples (readouts) as: v out =v out2 −v out1 =v sig . 
         [0027]    By applying the 4T APS pixels  500  with the CDS operation to the CMOS image sensor, the low-frequency noise hence is removed. However, the CMOS image sensor with a pixel array of a plurality of 4T APS pixels  500  still lack SESA operation since the same node is used for both signal detecting and storing. 
         [0028]    Please refer to  FIG. 7 .  FIG. 7  is a diagram illustrating a structure of an APS pixel  800  with a SESA function according to the prior art. The structure of the APS pixel  800  has been disclosed in “A Snapshot CMOS Active Pixel Imager for Low Noise, High Speed Imaging”, IEEE Meeting in 1998, by Guang Yang et al., which has two transfer transistor(i.e., TX 1  and TX 2 ) and a charge sink  802  to achieve the SESA operation. In  FIG. 7 , the APS pixel  800  has a reset transistor  310 , a row select transistor  306 , a source follower  501 , a first transfer transistor TX 1  and a photodiode  502 . In the APS pixel  800 , the storing node and the sampling nodes overlap at a single node (i.e., the node  806 ). Hence, the collected charges are immediately transferred to a floating diffusion node (i.e., node  806 ) serving as the storing node and sampling node concurrently after charge integration stops. However, the APS pixel  800  has no CDS functionality and the quantum efficiency of the APS pixel  800  is still low, especially in blue light. 
         [0029]    Generally, for achieving the aforementioned SESA operation, an APS pixel has to hold “exposure data” until it is read out. Nevertheless, a required data holding time could be as long as tens of milliseconds. Because electronic imaging systems do not have a mechanical shutter, the incoming light continues to generate charges during this period. A simple charge sink commonly seen in a pixel consists of a high-voltage source as a drain for electrons (or low-voltage source for holes), and a switch that connects this voltage source to a sensing node. 
         [0030]    Yet another prior art structure of an APS pixel with the SESA operation is disclosed in U.S. Pat. No. 6,369,853 (Merrill et al.). In Merrill&#39;s disclosure, a reset switch and a reset voltage reset the photodiode before integration, and serve as a charge sink while holding signal. However, the structure taught by Merrill again lacks CDS capability. 
         [0031]    As discussed above, the conventional systems have drawbacks. Therefore, there is a demand for providing a process and a system that allows both efficient CDS and SESA operation in the CMOS environment for digital cameras for better performances. 
       SUMMARY OF THE INVENTION 
       [0032]    In one exemplary embodiment of the present invention, an electronic image sensor with a pixel array of a plurality of active pixels is provided. Each of the active pixels includes: a photo detector, providing a sensing node for producing a signal based on an amount of light incident thereon; a storing node for storing a plurality of photo-generated charges according to the signal; a first controllable potential barrier between the sensing node and the storing node; a outputting node; and a second controllable potential barrier between the storing node and the outputting node, wherein each of the sensing node, the storing node and the outputting node is not overlapped. 
         [0033]    In another exemplary embodiment of the present invention, a method for correlated double sampling (CDS) in an electronic image sensor with a pixel array of a plurality of active pixels where each active pixel has a photo detector for producing a signal based on an amount of light incident on the pixel array is provided. The method includes: integrating a plurality of photo-generated charges according to the signal; resetting a signal sampling node; sampling noise at a first readout; transferring the photo-generated charges to the signal sampling node; and obtaining a second read out with charge sampling to extract a signal accordingly. 
         [0034]    In yet another exemplary embodiment of the present invention, a method is provided for correlated double sampling and “snapshot and simultaneous electronic shutter action (SESA)” in an electronic image sensor with a pixel array of a plurality of active pixels where each active pixel has a photo detector for producing a signal based on an amount of light incident on the pixel array. The method includes: integrating a plurality of photo-generated charges according to the signal; holding the photo-generated charges until a readout; turning on a charge sink for draining a plurality of incoming photo-generated charges; resetting a signal sampling node; sampling noise at a first readout; transferring the photo-generated charges to the signal sampling node; and turning off a charge sink for pre-resetting a plurality of nodes. 
         [0035]    In yet another exemplary embodiment of the present invention, an 
         [0000]    imaging system with an electronic image sensor having a pixel array of a plurality of active pixels is provided. Each of the active pixels includes: a photo detector, providing a sensing node for producing a signal based on an amount of light incident thereon; a storing node for storing a plurality of photo-generated charges according to the signal; a first controllable potential barrier between the sensing node and the storing node; an outputting node; and a second controllable potential barrier between the storing node and the outputting node, wherein each of the sensing node, the storing node and the outputting node is not overlapped. 
         [0036]    According to one aspect of the present invention, a pixel with a plurality of separated nodes for signal detecting, storing and sampling, and further with a charge sink is provided. The pixel is capable of efficiently performing SESA in the CMOS sensor. 
         [0037]    According to another aspect of the present invention, a pixel capable of performing Correlated Double Sampling (CDS) by using a “spill well” structure is provided. The photo detector of the present invention has higher quantum efficiency than those employing CCD and photogate types of pixels. 
         [0038]    According to yet another aspect of the present invention, a pixel and an area-array of such a pixel as an image sensor capable of performing both SESA and CDS at the same time are provided. Also, the spill well structure that uses a photodiode as the photo detector helps to achieve higher quantum efficiency than those employing CCD and photogate pixels. Furthermore, the present invention is compatible with a standard CMOS process. 
         [0039]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0040]    The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit, the invention. The drawings include the following figures: 
           [0041]      FIG. 1  is a diagram illustrating a conventional structure of an active pixel. 
           [0042]      FIG. 2  is a diagram illustrating a typical electronic image sensor. 
           [0043]      FIG. 3  is a diagram illustrating a conventional structure of a 3T APS (active pixel structure) pixel. 
           [0044]      FIG. 4  is diagram illustrating a timing diagram for a plurality of signals of a CMOS image sensor containing N rows of the 3T APS pixels in  FIG. 3 . 
           [0045]      FIG. 5  is a diagram illustrating a conventional structure of a 4T APS (active pixel structure) pixel. 
           [0046]      FIG. 6  is a timing diagram for the 4T APS pixel for a plurality of signals of a CMOS image sensor containing N rows of the 4T APS pixels in  FIG. 5 . 
           [0047]      FIG. 7  is a diagram illustrating a conventional structure of an APS pixel with a SESA functionality. 
           [0048]      FIG. 8  is a block diagram illustrating a structure of an active pixel according to one exemplary embodiment of the present invention. 
           [0049]      FIG. 9  is a diagram illustrating various steps of the active pixel shown in  FIG. 8  to operate without SESA. 
           [0050]      FIG. 10  is a timing diagram illustrating a plurality of signals according to an embodiment of the active pixel shown in  FIG. 8  with respect to the process steps shown in  FIG. 9 . 
           [0051]      FIG. 11  is a diagram illustrating various steps that may be used for the active pixel shown in  FIG. 8  to operate with both the CDS function and the SESA function according to one exemplary embodiment of the present invention. 
           [0052]      FIG. 12  is a timing diagram illustrating a plurality of signals according to an embodiment of the active pixel shown in  FIG. 8  with respect to the process steps shown in  FIG. 11 . 
           [0053]      FIG. 13  is a diagram illustrating various steps for simultaneously performing SESA and CDS functions according to one exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0054]    Please refer to  FIG. 8 .  FIG. 8  is a diagram illustrating a structure of an active pixel  900  according to one exemplary embodiment of the present invention. In  FIG. 8 , the active pixel  900  includes a plurality of transistors acting as switches, a light shield  909  and a fully depleted photodiode  914 , as described below. By the transistors, the active pixel  900  with separated sensing node, storing node, and outputting node for achieving the simultaneously electronic shutter action (SESA) and the correlated double sampling (CDS) functions. Please note the configuration of  FIG. 8  is for illustrative purposes only and not meant to be a limitation. For instance, the row select transistor  904  is optional, and so as the light shield  909 , the optional elements can be omitted depending on different design requirements. Furthermore, for the efficiency consideration, a fully depleted photodiode is used rather than the conventional photogate, however, with appropriate adjustments; the active pixel  900  can use the conventional photogate and/or photodiode to replace the fully depleted photodiode  914  to achieve the novel active pixel with both SESA and CDS functionalities simultaneously; the aforementioned design variances obey and fall in the scope of the present invention. 
         [0055]    In this embodiment, the active pixel  900  includes a charge sink  910 , wherein the charge sink  910  contains a transistor  911  (TX 3 ) that creates a potential barrier between a photo detecting node  914 A and a charge drain  915 . The active pixel  900  further includes a spill well structure  906  that contains a transistor  912  (TX 2 ) implemented for creating a potential barrier between the photo detecting node  914 A and a storing node  917 . A transistor  918  (TX 1 ) forms a potential barrier between the storing node  917  and a outputting node  922 ; and a transistor  919 , serving as a reset transistor, switches between the outputting node  922  and a reset voltage V a . In addition, a transistor  905  is implemented to act as a source-follower amplifier for signal buffering. In  FIG. 9 , a row select transistor  904  is coupled to an output bus of the pixel array, and operates as a switch for row selection in a pixel array. 
         [0056]    In  FIG. 9 , the voltage V a  can be a constant voltage or vary under different operations according to different design requirements. For instance, a plurality of the active pixels  900  can share a single transistor  911  (TX 3 ), a single source follower  905 , a single voltage node V a , and a single voltage node V sink  to diminish the required cost and the circuit area. When the voltage V a  is allowed to vary under different steps, different APS pixels  900  can further share a single row select transistor  904  in a pixel array. However, please note, the row select transistor  904  is an optional element, and can be omitted in other embodiment. The alternative designs obey and fall into the scope of the present invention. 
         [0057]    In this embodiment, the voltage Va is set to be less than or identical to a voltage V DD , and a voltage V sink  is preferably greater than a voltage applied to the transistor  911  (TX 3 ). In one aspect, the voltage V sink  is at least one transistor threshold voltage greater than the voltage applied to the transistor  911  (TX 3 ). That is, the voltage V sink  can be set as a high voltage V DD  since it is used as a charge sink. 
         [0058]    In different embodiments, the active pixel  900  may be constructed using n-type or p-type semiconductor transistors with appropriate adjustments according to the design requirements. It is noteworthy that the polarity described above ( FIG. 9 ) will be reversed in the case of a p-type transistor. The light shield  909  in  FIG. 9  is formed by one or more opaque layers on the transistor  913  to prevent stored pixel charges from being discharged. In addition, when the SESA function is not required in some operation cases, the active pixel  900  can achieve the CDS function while keeping the transistor  911  (TX 3 ) off. 
         [0059]    Please refer to  FIG. 9  in conjunction with  FIG. 8 .  FIG. 9  is a diagram illustrating various steps of the active pixel  900  in  FIG. 8  to operate without SESA operation. For clear understanding of the process flow shown in  FIG. 9 , a brief structure of the active pixel  900  is illustrated at the top of the diagram. 
         [0060]    Please refer to  FIG. 10  in conjunction with  FIG. 8  and  FIG. 9 .  FIG. 10  is a timing diagram illustrating a plurality of signals according to an embodiment of the active pixel  900  with respect to the process steps shown in  FIG. 8 , including a reset signal  919 A applied to the gate of the reset transistor  919 , a signal  918 A applied to the gate of the transfer transistor  918 , a signal  913 A applied to the gate of the transistor  913 , a signal  912 A applied to the gate of the transfer transistor  912 , a signal  904 A applied to the gate of the row select transistor  904 , and a voltage Va. Where a signal  911 A illustrates the signal applied on the gate of the transistor  911 A. 
         [0061]    Please refer to  FIG. 8 ,  FIG. 9  in view of  FIG. 10 . As shown in  FIG. 9 , in the following steps the photodiode  914  is fully depleted with a pinning voltage Vpin. In step S 1001 , the reset transistor  919  turns on since the voltage signal  919 A is set to be high. After the first reset operation, the active pixel  900  starts integration (Step  1002 ). 
         [0062]    In step S 1002 , a plurality of photo-generated charges are integrated. The reset transistor  919  is turned off and the voltage V STO  (i.e., the voltage at the gate of the storing transistor  913 ) pulls up. In this step, a potential well is formed to store the charges collected by the fully depleted photodiode  914 . As shown in  FIG. 9 , some noise n 1  is left at the outputting node  922  after resetting, but a first readout of the pixel  900  is not affected by the noise n 1  since the transfer transistor  918 (TX 1 ) is acted as a barrier of the storing node  917 . 
         [0063]    In  FIG. 9 , in step S 1003 , the integration is ended and the outputting node  922  is reset again by turning on the reset transistor  919 . In step S 1004 , the reset transistor  919  turns off and then the first readout occurs. The sampled noise n 2  left at the outputting node  922  during step S 1003 , and the sampled value of the noise signal n 2  is stored in the readout circuit (not shown) for the CDS operation. 
         [0064]    In step S 1005  in  FIG. 9 , the charges are transferred and a second readout takes place. The storing transistor  913  turns off for transferring the stored charges from the storing node  917  to the outputting node  922 . The charges at the outputting node  922  are induced by the signal and the second reset noise n 2 . In the end, a readout follows charge transfer and samples that value. Using the sampled value in step S 1004 , the signal value can be extracted. 
         [0065]    The gate of the transfer transistor  918 (TX 1 ) may be held at a specified constant voltage V 1 , and the gate of the second transfer transistor  912  may be held at another specified constant voltage V 2 , for minimizing any switching noise. However, in another embodiment shown in  FIG. 11 , the applied voltage on the gate of the transfer transistor  912 (TX 2 ) pulls down in step S 1203  to ensure an effective barrier between the sensing node  914 A and the storing node  917 . The alternative designs obey and fall into the scope of the present invention. 
         [0066]    In the descriptions above, the active pixel  900  operates with CDS when no SESA required is disclosed, In other words, the foregoing operation may be conducted in a “row-rolling” manner, since there is no SESA function. 
         [0067]    Please refer to  FIG. 11  in conjunction with  FIG. 8 ;  FIG. 11  a diagram illustrating various steps that may be used for the active pixel  900  to operate with both the CDS function and the SESA function according to one aspect of the present invention. For clear understanding of the process flow shown in  FIG. 11 , a brief structure of the active pixel  900  is shown at the top of the diagram.  FIG. 12  is a timing diagram illustrating a plurality of signals according to an embodiment of the active pixel  900  with respect to the process steps shown in  FIG. 11 , including a reset signal  919 A applied to the gate of the reset transistor  919 , a signal  918 A applied to the gate of the transfer transistor  918 (TX 1 ), a signal  913 A applied to the gate of the storing transistor  913 , a signal  912 A applied to the gate of the transfer transistor  912 (TX 2 ), a signal  904 A applied to the gate of the row select transistor  904  and a voltage Va. 
         [0068]    Steps S 1201 , S 1202 , S 1204 , S 1205 , and S 1206  in  FIG. 11  are similar to steps S 1001 ,  1002 , S 1003 , S 1004 , and S 1005  respectively, as described above with respect to  FIG. 9 . 
         [0069]    In brief, at step S 1201 , the reset transistor  919  turns on for a first resetting, and before the step S 1202  the reset transistor  919  turns off. In step S 1202  the storing transistor  913  turns on and the photodiode  914  in this embodiment is fully depleted photodiode so that the generated charges will successfully store in the storing node  913 . In a preferred embodiment, at the end of the integration, the voltage applied on the transfer transistor  912  (TX 2 ) is slightly heaved to further enhance the barrier between the sensing node  914 A and the storing node  917 . in step  1203 , since the pixel  900  is operated with both SESA and CDS, the voltage signal  911 A of the transfer transistor  911  (TX 3 ) is down during the data holding for drain out the remnant charges at the sensing node  914 A. Since the voltage signal  912 A of the second transfer transistor is heaved at step S 1203  and the photodiode  914  is shorted to a voltage V sink  since the third transfer transistor  911  is on, any additional photo-generated charges are drained by the voltage V sink . Data associated with any captured exposure is stored under the gate of the storing transistor  913 . The potential barrier created by the transfer  912 (TX 2 ) and the light shield  909  prevents the stored data from being interfered with by any incoming signal, and the charge sink  910  formed by the third transfer transistor  911  (TX 3 ) and the voltage V sink . This combination allows all pixels in an area array to stop integration simultaneously, and hold the data until readout and hence efficiently facilitates SESA operation. 
         [0070]    In step S 1204 , the reset transistor  919  turns on again for reset. In step S 1205 , after the reset transistor  919  turns off, the row select transistor  904  turns on for achieve first read out. At step S 1206 , the transfer transistor  918  turns on and the storing transistor  913  turns off for transferring the charges from the storing node  917  to the outputting node  922 ; after the charge transfer the transfer transistor  918 (TX 1 ) turns off and then the row select transistor  904  turns on for the second readout. It is noteworthy that steps S 1204 -S 1206  (also steps S 1003 -S 1005 ) are performed in a “rolling” manner, i.e., sequentially row after row, until the last row is reached. 
         [0071]    Operations for one row of the pixel array are finished from the aforementioned steps. After the readout operations of all the rows within the pixel array end (a readout operation of a frame), the transfer transistor  911  (TX 3 ) is turned off and the reset transistor  919  is turned on for the follow-up frames. Since the photodiode  914  is a fully depleted photodiode in this embodiment; this ensures that all incoming charges are transferred to the storage node  917 , instead of staying in the photodiode  914 . 
         [0072]    It should be noted that the present invention is not limited to the foregoing implementations. Various modifications may be used to implement the foregoing techniques. For example, the potential barrier formed by the transfer transistors  918 (TX 1 ), the transfer transistor  912 (TX 2 ), and the transfer transistor  911  (TX 3 ) may be operated differently than as described above. An example of such a variation is provided with respect to the diagram shown in  FIG. 13 . 
         [0073]    The steps S 1401 -S 1407  of  FIG. 13  correspond to steps S 1201 -S 1207  of  FIG. 11 , respectively. Referring to  FIG. 13 , step S 1401  is similar to step S 1201  of  FIG. 11 . 
         [0074]    In step S 1402 , the voltage applied on the gate of the first transfer transistor  918 (TX!) is biased at a voltage V 13     —     tx1  lower than a voltage V 11     —     tx1 , as shown in  FIG. 13  and  FIG. 11 . The lower voltage of the first transfer transistor  918 (TX 1 ) can fully turn off the first transistor  918 (TX 1 ). The applied voltage on the gate of the first transfer transistor  918 (TX 1 ) therefore stays at this voltage V 13     —     tx1  until step S 1406  is executed, where step S 1406  is similar to step S 1206  mentioned above. 
         [0075]    As for the applied voltage on the transfer transistor  912 (TX 2 ), the gate of the transfer transistor  912 (TX 2 ) is biased at a voltage V 13-tx2  lower than a voltage V 11     —     tx2 ( FIG. 11  and  FIG. 13 ) as the process enters the data holding step S 1403  which is similar to step S 1203  mentioned above. The voltage applied on the gate of the transfer transistor  912 (TX 2 ) stays at this voltage V 13-tx2  after step S 1406  is finished. 
         [0076]    According to one aspect of the present invention, an active pixel with a plurality of separate nodes for signal detecting, storing and outputting, a charge sink, and an area-array is provided. The active pixel is capable of efficiently performing SESA in the CMOS area. 
         [0077]    According to another aspect of the present invention, an active pixel can perform Correlated Double Sampling (CDS) by using a “spill well” structure. The photo detector of the present invention has higher quantum efficiency than those using CCD and photogate types of pixels. 
         [0078]    According to yet another aspect of the present invention, an active pixel and an area-array of such a pixel can perform both SESA and CDS simultaneously. The spill well structure which uses a photodiode as the photo detector helps to achieve higher quantum efficiency than those using CCD and photogate types of pixels. In a preferred embodiment, the photodiode is a fully depleted photodiode. Furthermore, the present invention is compatible with standard CMOS process. 
         [0079]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.