Abstract:
A method and apparatus of interleaving memory banks in a multi-layer bus system. The apparatus includes a plurality of slave interface units receiving signals requesting a bus access and generating control signals, and a controller receiving the control signals generated from the plurality of slave interface units and generating signals required to access the memory banks. Accordingly, it is possible to greatly reduce a delay time caused when accessing a synchronous dynamic random access memory (SDRAM), for example, in a multi-layer bus system.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the benefit of Korean Patent Application No. 2004-9755, filed on Feb. 13, 2004 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to interleaving of a memory bank, and more particularly, to a method and apparatus of interleaving a memory bank in a multi-layer bus system.  
         [0004]     2. Description of the Related Art  
         [0005]     A structure of a bus in an embedded System-on-Chip (SoC) depends on the type of a processor installed in the SoC. For instance, an AMBA High-performance Bus (AHB) is used when an ARM processor is included in a SoC. In general, the performance of the SoC varies according to factors, such as the type of a processor, the performance of software and the performance of a bus provided. When a piece of hardware is manufactured using the SoC, connection with a memory or memories is required. The hardware performance is largely affected by that of the memory. Generally, a Synchronous Dynamic Random Access Memory (SDRAM) or a Double Date Rate (DDR) memory is used as the memory. Accordingly, a delay in data transmission may occur based on the performance of the memory.  
         [0006]     When a slave device, such as an SDRAM, is shared and simultaneously accessed by a plurality of master devices, such as a processor or a Direct Memory Access (DMA) unit, the performance of a system is not remarkably influenced by the type of bus used. In this case, the performance of the system is affected only by a response delay of the bus. Generally, the AHB bus, for example, is a bus with good performance, which has a clock response delay of 0.  
         [0007]     Moreover, when the SDRAM is used as a slave device and reading and/or writing data is performed by accessing the SDRAM, it is possible to reduce a response delay caused when the SDRAM is continuously accessed by using bank interleaving. Bank interleaving is a function of improving speed of data processing by dividing a storage space of a memory into several banks, for example, dividing the storage space of the memory into rooms for storing and/or processing data, and allowing the several banks to process data in response to a processing command.  
         [0008]     However, it is impossible to use bank interleaving for an SDRAM connected with an AHB system bus, where sequence of commands and responses to commands are predetermined and, thus, a large delay in data transmission becomes unavoidable.  
       SUMMARY OF THE INVENTION  
       [0009]     An aspect of the present invention provides a method and apparatus of interleaving memory banks of a Synchronous Dynamic Random Access Memory (SDRAM) using bank interleaving, where the SDRAM is shared and accessed by a plurality of master and/or slave devices, thereby minimizing a delay when the SDRAM is accessed.  
         [0010]     According to an aspect of the present invention, a method of interleaving memory banks of a memory connected with a multi-layer bus system is provided. The method includes: receiving signals requesting access to a bus, generating control signals, and receiving a plurality of sets of the control signals and generating signals required to access the memory banks.  
         [0011]     When receiving the plurality of sets of the control signals and generating the signals required to access the memory bank, a signal requesting access to a memory bank, which is not accessed by the plurality of master devices and/or the plurality of slave devices may be processed for a first time.  
         [0012]     Additional aspects and/or advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.  
         [0013]     According to another aspect of the present invention, an apparatus to interleave memory banks of a memory connected with a multi-layer bus system is provided. The apparatus includes: a plurality of slave interface units receiving signals requesting access to a bus and generating control signals, and a controller receiving the generated control signals from the plurality of slave interface units and generating signals required to access the memory banks.  
         [0014]     According to an aspect of the present invention, a plurality of layers of the multi-layer bus system are connected with a plurality of master devices and/or a plurality of slave devices, and different banks are respectively allocated to the plurality of layers.  
         [0015]     According to an aspect of the present invention, the apparatus includes an arbiter receiving the signals requesting the bus access from the plurality of master devices and/or the plurality of slave devices, and arbitrating the signals so that a right for the bus access is given to one of the plurality of master devices and/or the plurality of slave devices.  
         [0016]     According to an aspect of the present invention, the controller processes a signal requesting access to a memory bank, which is not accessed by the plurality of master devices and/or the plurality of slave devices, for the first time, where the signal is input from a slave interface unit.  
         [0017]     According to an aspect of the present invention, a storage space of the memory is divided into a plurality of banks and the plurality of banks are allocated to the slave interface units. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     The above and/or other aspects and advantages of the present invention will become apparent and more readily appreciated from the following description of the embodiments taken in conjunction with the accompanying drawings of which:  
         [0019]      FIG. 1A  illustrates an order in which signals to control a Synchronous Dynamic Random Access Memory (SDRAM) are generally generated when N pieces of data are transmitted in a burst mode;  
         [0020]      FIG. 1B  illustrates an order in which SDRAM control signals are generally generated when data is continuously transmitted as bursts;  
         [0021]      FIG. 1C  illustrates an order in which SDRAM control signals are generally generated when data is transmitted as a second burst at a row of a bank where data is transmitted as a first burst;  
         [0022]      FIG. 1D  illustrates an order in which SDRAM control signals are generally generated during bank interleaving;  
         [0023]      FIG. 2A  illustrates a single-layer bus system to which a plurality of master and/or slave devices are connected to access an SDRAM;  
         [0024]      FIG. 2B  illustrates a double-layer bus system to which a plurality of master and/or slave devices are connected to access two SDRAMs;  
         [0025]      FIG. 3  illustrates timing diagrams of signals according to an AHB protocol when two bursts are continuously transmitted;  
         [0026]      FIG. 4  is a timing diagram of signals in a Finite State Machine (FSM) to show possible states of an SDRAM;  
         [0027]      FIG. 5  is a block diagram of a bus according to an aspect of the present invention;  
         [0028]      FIG. 6  is a block diagram an N-layer bus system according to an aspect of the present invention;  
         [0029]      FIG. 7  is a timing diagram of signals for bus access in the bus system of  FIG. 5  when two bursts are continuously transmitted, according to an aspect of the present invention;  
         [0030]      FIG. 8  is a timing diagram of signals in a Finite State Machine (FSM) to show possible states of an SDRAM according to an aspect of the present invention; and  
         [0031]      FIG. 9  is a detailed block diagram of an SDRAM controller according to an aspect of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0032]     Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below to explain the present invention by referring to the figures.  
         [0033]      FIG. 1A  illustrates an order in which SDRAM control signals are generated when N pieces of data are transmitted as a burst. In an SDRAM, a position of a storage space is determined with the use of rows and columns, and thus, the row and column of a particular address of the SDRAM are selected to write data to and/or read data from the particular address.  
         [0034]     Referring to  FIG. 1A , when an address of the SDRAM for data access is determined, a Row Address Strobe (RAS) signal to enable selection of a row of the address is generated from a first clock, a No OPeration (NOP) signal allowing no operation is generated from a second clock, and a Column Address Strobe (CAS) signal to enable selection of the column of the address is generated from a third clock. A signal that indicates a bank for the row of the address is output together with the output of the RAS signal. Further, no signal is generated during an N-1 clock, where N indicates a number of pieces of data that must be transmitted. Further, a Burst Stop (BS) signal or a Precharge (PR) signal is generated. After the PR signal is generated, other control signals are generated during a period of 2 clocks. A new RAS signal is not required after generation of the BS signal, but a new RAS signal must be generated after generation of the PR signal since an address with a previous row is closed. That is, the BS signal is generated when a new RAS signal is required, otherwise, the PR signal is generated.  
         [0035]      FIG. 1B  illustrates an order in which SDRAM control signals are generated when data is continuously transmitted as bursts. Referring to  FIG. 1B , when data is continuously generated as bursts at different rows of the same bank and/or the content of data transmitted as a second burst is unknown beforehand, a first RAS signal, an NOP signal, a first CAS signal, the NOP signal, a first PR signal, and the NOP signal are transmitted as a first burst, and a second RAS signal, the NOP signal, a second CAS signal, the NOP signal, a second PR signal, and the NOP signal are transmitted as the second burst. Accordingly, a relatively significant amount of time is required to continuously transmit signals as first and second bursts.  
         [0036]      FIG. 1C  illustrates an order in which SDRAM control signals are generated when data is transmitted as a second burst at a row of a bank where data is transmitted as a first burst. When data is transmitted as the second burst at the row of the bank where data is transmitted as the first burst, a first BS signal rather than a first PR signal is generated and a second CAS signal rather than an NOP signal is generated in comparison to the first burst.  
         [0037]      FIG. 1D  illustrates an order in which SDRAM control signals are generated during bank interleaving. Referring to  FIG. 1D , data is transmitted as a second burst at a different bank than a bank where data is transmitted as a first burst. Thus, a second RAS signal and a second CAS signal can be generated in place of an NOP signal as the first burst, thereby reducing a number of clocks required during generation of the NOP signal NOP, and reducing a time required to access an SDRAM.  
         [0038]      FIG. 2A  illustrates a single-layer bus system with which a plurality of master and/or slave devices are connected to access an SDRAM. Referring to  FIG. 2A , to access an SDRAM, several master devices transmit signals requesting use of a bus of the SDRAM to an AMBA High-performance Bus (AHB) arbiter and decoder. Then, the AHB arbiter and decoder receives the signals and arbitrates use of the bus. Specifically, the AHB arbiter and decoder gives a master device a right to access the bus according to a predetermined order of priority, detects a slave device using an address of the slave device that the master device having the right desires to access, and selects the slave device.  
         [0039]     The single-layer bus system has a simple structure and can arbitrate use of a bus with reduced power consumption, but it does not allow the remaining master devices to access an SDRAM while the SDRAM is accessed by another master device.  
         [0040]      FIG. 2B  illustrates a double-layer bus system with which a plurality of master devices and/or slave devices are connected to access two SDRAMs # 1  and # 2 . Here, the layer of the double-layer bus system is used as a term to represent a number of buses, and several devices may be connected with a layer. A matrix receives a command that instructs access to an SDRAM from the respective layers, and switches between SDRAMs # 1  and # 2 . The double-layer bus system provides improved performance because of use of the two SDRAMs # 1  and # 2  and data can be simultaneously transmitted to both the SDRAMs # 1  and # 2 . However, such a system is expensive to manufacture and requires large power consumption.  
         [0041]      FIG. 3  illustrates timing diagrams of signals in accordance with an AHB protocol when two bursts are continuously transmitted. Since simultaneous access of a plurality of master devices to an SDRAM is not permitted, a signal HGRANT # 1  output from a first master device (not shown) and a signal HGRANT # 3  output from a third master device (not shown) cannot be activated at the same time. Thus, only subsequent to transmission of one burst in response to signals HBUSREQ # 1 , HGRANT # 1 , HTRANS # 1 , and HREADY # 1 , another burst can be transmitted in response to signals HBUSREQ # 3 , HGRANT# 3 , HTRANS # 3 , and HREADY# 3 . Therefore, a large delay in transmission of the two bursts is unavoidable.  
         [0042]      FIG. 4  illustrates timing diagrams of signals in a Finite State Machine (FSM) to indicate possible states of an SDRAM. Referring to  FIG. 4 , a state of the SDRAM may be changed from an IDLE state  410  to a RAS state  420  and then, to a NOP state  440 . After the NOP state  440 , the SDRAM may enter a CAS state  430 , a BS state  450 , or a PR state  460 . After the BS state  450 , the SDRAM may enter a PR state  460 . Each piece of data is transmitted in each of the above states of the SDRAM, and transmission of each data requires a new RAS signal.  
         [0043]      FIG. 5  is a block diagram of a bus system according to an aspect of the present invention. A bus system according to an aspect of the present invention may be configured with a plurality of layers, however, the bus system shown in  FIG. 5  illustrates first and second layers. The respective first and second layers are connected with a plurality of master devices and/or a plurality of slave devices. Accordingly, the first layer is connected with first and second mater devices  502  and  504  and a slave device  506 , and the second layer is connected with third and fourth mater devices  508  and  510 . The first and second layers are connected with an SDRAM controller  550  and are connected with first and second slave interface units  540  and  542 , respectively. An arbiter and decoder  520  arbitrates commands that instruct access to the bus system, where the commands are input from the first and second master devices  502  and  504  and the slave device  506  connected with the first layer. Further, the arbiter and decoder  520  decodes an address of the slave device  506 . An arbiter  530  arbitrates commands that instruct access to the bus system which are input from the third and fourth master devices  508  and  510  connected with the second layer.  
         [0044]     According to an aspect of the present invention, the bus system is an AHB system bus. In this case, the first through fourth mater devices  502 ,  504 ,  508 , and  510  are AHB master devices, and the slave device  506  is an AHB slave device. Further, the arbiter and decoder  520  is an AHB arbiter and decoder, and the first and second slave interface units  540  and  542  are AHB slave interface units.  
         [0045]     The SDRAM controller  550  controls an SDRAM  560  that includes first and second banks  562  and  564 . The first bank  562  is mainly accessed by the first and second master devices  502  and  504 , respectively, and the slave device  506  that are connected with the first layer. The second bank  564  is mainly accessed by the third and fourth master devices  508  and  510  that are connected with the second layer.  
         [0046]      FIG. 6  is a block diagram to illustrate an N-layer bus system according to an aspect of the present invention. Similar to a dual-layer bus system, a plurality of devices are connected with layers of the N-layer bus system, and N slave interface units are included in the N-layer bus system to provide slave interface for the respective layers. Further, an SDRAM includes N banks.  
         [0047]      FIG. 7  illustrates timing diagrams of signals for bus access in the bus system of  FIG. 5  when two bursts are continuously transmitted, according to an aspect of the present invention. Since simultaneous access of a plurality of master devices to the SDRAM  560  is not permitted, a signal HGRANT # 1  output from the first master device  502  and a signal HGRANT # 3  from the third master device  508  cannot be simultaneously activated. Referring to  FIG. 7 , in this bus system, access to the SDRAM  560  is efficiently performed since a second RAS signal is generated even before transmission of a burst is completed, thus reducing a number of clocks for generation of a NOP signal. In other words, a command from the first master device  502  is sent to the first slave interface unit  540  and arbitrated by the arbiter &amp; decoder  520 . In this case, the SDRAM controller  550  begins transmission of data to the SDRAM  560  in response to a RAS signal output from the SDRAM  560 . Thereafter, a time delay corresponding to five clocks is caused until a response signal HREADY 1  is generated after an output of a CAS signal from the SDRAM  560 . When the third master device  508  connected with the second layer generates a command requesting access to the SDRAM  560  during transmission of data to the first master device  502  connected with the first layer, the command is sent to the second slave interface unit  542  by the arbiter  530  connected with the second layer so that transmission of data is executed during a delay in responding to the command, thereby remarkably reducing the response delay.  
         [0048]      FIG. 8  illustrates timing diagrams of signals in a Finite State Machine (FSM) to show states of an SDRAM according to an aspect of the present invention. In  FIG. 8, 810  shows a state diagram of a first layer, and  820  shows a state diagram of a second layer. As shown in  FIG. 8 , an IDLE state and a PR state of an SDRAM are shared by the first and second layers. As the states of the SDRAM change as shown in  FIG. 8 , a plurality of master devices and/or a plurality of slave devices access the SDRAM.  
         [0049]      FIG. 9  is a detailed block diagram of an SDRAM controller according to an aspect of the present invention. Referring to  FIG. 9 , N interface units  910 - 1 , . . . , to  910 -N that process a plurality of slave interface signals, respectively, are connected with a controller  920  that switches and controls these interface signals. The controller  920  receives a plurality of control signals (not shown) and generates a plurality of control signals, such as signals RAS, CAS, ADDR, and DATA, that allow a plurality of master devices and/or a plurality of slave devices to be connected with an SDRAM.  
         [0050]     A method of interleaving a memory bank according an aspect of the present invention has been described with respect to an SDRAM, but the present invention is applicable to various types of memories with a multi-layer bus system. For instance, the present invention may be applied to a Double Data Rate (DDR) memory.  
         [0051]     An aspect of the present invention is implemented as a computer program. In this case, the members of the present invention are code segments that execute necessary operations and they can be easily derived by computer programmers in the art to which the present invention belongs. Further, the program may be stored in a computer readable medium, read and implemented in a computer to realize the method of interleaving a memory bank. The computer readable medium may be any medium, such as a magnetic recording medium, an optical recording medium, and a carrier wave.  
         [0052]     As described above, according to an aspect of the present invention, since the next data is read before transmission of data is completed, it is possible to interleave memory banks of an SDRAM in a multi-layer bus system, and further, largely reduce a time delay caused when accessing the SDRAM.  
         [0053]     While this invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.