Abstract:
A readout circuit with a self-detection circuit and a control method therefor. The circuit comprises a pre-charging circuit and a control circuit, the pre-charging circuit and the control circuit being connected to a first node and used for charging a memory unit. The readout circuit also comprises a detection circuit, the detection circuit and the pre-charging circuit being connected to the first node. The detection circuit comprises a third NOT gate, a fourth NOT gate, a first NAND gate, a sixth NOT gate, a first trigger and an eighth NOT gate. In such a manner of detecting the reversal of the first NOT gate through the reversal of the third NOT gate, the charging duration of the first node (A) can be greatly reduced, thereby reducing the reading duration of the whole circuit. At the same time, the re-occurrence of a state of charging the circuit can be avoided after pre-charging has ended.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to the semiconductor field, and particularly relates to a readout circuit with a self-detection circuit and a control method thereof. 
       BACKGROUND OF THE INVENTION 
       [0002]    As a storage chip without loss of data after power-off, An electrically erasable programmable read-only memory (EEPROM) has advantages of non-volatility, byte erasability, fast programming speed and the like. EEPROM is programmed without removing the EEPROM from the system, so that it is convenient, efficient and feasible to storage and update (or program) data. EEPROM makes it possible to perform the remotely programming process over radio or wires, which eliminates the light-transmission window for ultraviolet light of EEPROM. The package cost of EEPROM is low, and the test of EEPROM is simple, resulting in its widespread application. 
         [0003]    The readout circuit is an essential part in the memory design and to a large extent decides the important parameter of a reading time of the memory. However, the current of the memory unit will drift as the manufacturing process drifts. Meanwhile, the number of the readout circuits will increase correspondingly as digits of the memory increases, resulting in a more widespread distribution of the readout circuits in the whole chip. Therefore, the readout circuits are more easily subject to some negative influences during the manufacturing process. 
         [0004]    In the conventional solution, as shown in  FIG. 1 , M 0  is a charge transistor and controlled by the signal Pre_charge. When the readout circuit begins to work, the Pre_charge signal is a low pulse, and right now the power source potential VDD charge the first node A by M 0  to increase the potential of the first node A. As the potential of the first node A increases, the potential of the node B will reduce gradually, and the transistor M 3  is turned on. Right now the first node A is pulled-up by a pull-up current, and the magnitude of this current is determined by the transistors M 1  and M 2 . If the decoded EEPROM cell is an erased cell, i.e. the starting voltage threshold of this cell is very low, and then there will be a current flowing through EEPROM cell. The voltage of the first node A is pulled-down, and right now the corresponding Out is “0”. The corresponding timing diagram is shown in  FIG. 2 . 
         [0005]    Although the readout circuit can well control charging of the first node A, it easily results in false charge because there is no detection circuit in the readout circuit. Moreover, the charging speed of the readout circuit is slower, resulting in a slow reading speed of the readout circuit, which can not satisfy the great reading requirement. Therefore, it is necessary to improve the conventional readout circuit to overcome the above disadvantages. 
       SUMMARY OF THE INVENTION 
       [0006]    A readout circuit with a self-detection circuit includes: a precharge circuit and a control circuit, the precharge circuit and the control circuit being connected at a first node A and being configured to charge a memory unit; the readout circuit further includes a detection circuit, the detection circuit and the precharge circuit are connected at the first node A; the detection circuit includes a third NOT gate X 3 , a fourth NOT gate X 4 , a first NAND gate X 5 , a sixth NOT gate X 6 , a first trigger X 7  and an eighth NOT gate X 8 ; wherein an input of the third NOT gate X 3  is connected to the first node A, an output of the third NOT gate X 3  and an input of the fourth NOT gate X 4  are connected at a third node C, an output of the fourth NOT gate X 4  and an input for a clock signal of the first trigger X 7  are connected at a fourth node D, an inverse reset terminal of the first trigger X 7  is connected to an output of the eighth NOT gate X 8 , an input of the eighth NOT gate X 8  is connected to a first signal terminal, an output QN of the first trigger X 7  is connected to an input of the first NAND gate X 5 , another input of the first NAND gate X 5  is connected to a first read terminal, an output of the first NAND gate X 5  is connected to an input of the sixth NOT gate X 6 , the first NAND gate X 5  is further connected to the third node C. 
         [0007]    In one of embodiments, the output of the fourth NOT gate X 4  is connected to a clock signal terminal CP of the first trigger X 7 . 
         [0008]    In one of embodiments, the readout circuit further includes a reset circuit; the reset circuit is connected to the precharge circuit at the first node A. 
         [0009]    In one of embodiments, the reset circuit comprises a fourth transistor M 4 , a source of the fourth transistor M 4  is connected to the first node A, a gate of the fourth transistor M 4  is connected to the first signal terminal, a drain of the fourth transistor M 4  is grounded. 
         [0010]    In one of embodiments, the control circuit includes a first NOT gate X 1  and a second NAND gate X 2 , wherein an input of the first NOT gate X 1  is connected to the first node A, an output of the first NOT gate X 1  is connected to an input of the second NAND gate X 2 , another input of the second NAND gate X 2  is connected to the first read terminal, an output of the second NAND gate X 2  is connected to an output signal terminal. 
         [0011]    In one of embodiments, the precharge circuit includes a charge transistor (M 0 ), a source of the charge transistor M 0  is connected to a power source potential (VDD), a drain of the charge transistor M 0  is connected to the first node A, and a gate of the charge transistor M 0  is connected to a precharge signal. 
         [0012]    In one of embodiments, an output of the sixth NOT gate X 6  is connected to the precharge signal. 
         [0013]    In one of embodiments, the charge transistor M 0  is a P-type or N-type charge transistor. 
         [0014]    In one of embodiments, the precharge circuit further includes a first transistor M 1 , a second transistor M 2  and a third transistor M 3 ; wherein the first transistor M 1  and the second transistor M 2  forms a mirror circuit, both sources of the first transistor M 1  and the second transistor M 2  are connected to the power source potential VDD, a gate of the first transistor M 1  is connected to a gate of the second transistor M 2 , a drain of the first transistor M 1  is connected to a source of the third transistor M 3 , a drain of the second transistor M 2  is connected to a reference current, a drain of the third transistor M 3  is connected to the first node A, a gate of the third transistor M 3  and an output of the first NOT gate X 1  are connected to a second node B. 
         [0015]    A control method of a readout circuit includes: 
         [0016]    step (1), configuring the first signal terminal as a high level, configuring the precharge signal as a low level, and turning the charge transistor (M 0 ) off; 
         [0017]    step (2), changing the first signal terminal from the high level to the low level, changing the signal of the first read terminal from the low level to the high level, so that the precharge circuit performs a charging process to charge the memory unit; 
         [0018]    step (3), controlling a potential of the first node A to be higher than a reversal voltage of the third NOT gate X 3 , changing the precharge signal to the low level, so as to turn the charge transistor M 0  off, and then completing a precharging process; meanwhile, reducing a potential of the second node B to turn the third transistor M 3  on, controlling the reversal voltage of the third NOT gate X 3  to be higher a reversal voltage of the first NOT gate X 1  to ensure the charge transistor M 0  is turned off after the third transistor M 3  is turned on. 
         [0019]    In one of embodiments, the step (1) includes: 
         [0020]    changing a signal of the first signal terminal to the high level, changing a signal of the first node A to the low level, changing a signal of the output QN of the first trigger X 7  to the high level, changing the first read signal to the low level, and changing the precharge signal to the low level, so as to turn the charge transistor M 0  off. 
         [0021]    In one of embodiments, the step (2) includes: changing a signal of the first signal terminal from the high level to the low level, changing signals of three inputs of the first NAND gate X 5  to the high level, changing the precharge signal to the high level, so as to turn the charge transistor (M 0 ) on and charge the first node A by the power source potential VDD. 
         [0022]    In one of embodiments, during the charging process, the method includes: changing a signal of the fourth node D from the low level to the high level, changing a potential of the output QN of the first trigger X 7  from the high level to the low level, locking the precharge signal to the low level, thereby preventing the memory unit from being charged again after the precharging process is completed. 
         [0023]    In one of embodiments, the step (2) includes: increasing the potential of the first node A to reach the reversal voltage of the third NOT gate X 3 , so as to change the precharge signal to the low level and turn the charge transistor (M 0 ) off to complete the precharging process. 
         [0024]    In one of embodiments, the step (3) includes: increasing the potential of the first node A to reach the reversal voltage, reducing the potential of the second node B, so as to turn the third transistor M 3  on, so that the potential of the first node A is clamped by the third NOT gate X 3  and the third transistor M 3 . 
         [0025]    In the readout circuit with a self-detection circuit described above, detection of the precharging process is implemented by arranging a detection circuit in the readout circuit. The charging time of the first node A can be saved greatly by using a manner that reversal of the first NOT gate X 1  is detected by reversal of the third NOT gate X 3 , and then the reading time of the whole circuit can be reduced correspondingly. During the whole charging process, the potential of the fourth node D is changed from 0 to 1, the potential of the output QN of the first trigger X 7  is changed from 0 to 1, so that the Pre_charge signal is locked as a 0 state, preventing the memory unit from being charged again after the precharging process is completed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0026]    To illustrate the technical solutions in the embodiments of the present invention or the prior art more clearly, the accompanying drawings for describing the embodiments or the prior art are introduced briefly in the following. Apparently, the accompanying drawings in the following description are only some embodiments of the present invention, and persons of ordinary skill in the art can derive other drawings from the accompanying drawings without creative efforts. 
           [0027]      FIG. 1  is a circuit diagram of a readout circuit in a prior art; 
           [0028]      FIG. 2  is a timing diagram in the reading process of the readout circuit in the prior art; 
           [0029]      FIG. 3  is circuit diagram of a readout circuit according to an embodiment of the invention; 
           [0030]      FIGS. 4  is a time diagram of the high level in the reading process according to an embodiment of the invention; 
           [0031]      FIG. 5  is a time diagram of the low level in the reading process according to an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0032]    The following description provides a large number of specific details for a thorough understanding of the present invention. However, one skilled in the art will understand that the invention may be practiced without one or more of such details. In other instances, some well-known technique features have not been described to avoid unnecessarily obscuring the present invention. 
         [0033]    It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0034]    The exemplary embodiments according to the present invention are now described with reference to the drawings. However, there exemplary embodiments can be embodied in many different forms, and should not be explained to be limited the described embodiments. It should be understood that these embodiments are provided to make disclosure of the invention thorough and complete, and the idea of these exemplary embodiments are fully presented to those skilled in the art. For clarity, the same elements have been designated with the same reference numerals in the different drawings, and then their descriptions are omitted. 
         [0035]    As shown in  FIG. 3 , in an embodiment, in order to solve the problems presented in the prior art, a readout circuit with a self-detection circuit is provided. The readout circuit includes a precharge circuit and a control circuit. The precharge circuit and the control circuit are connected at a first node A, and configured to charge a memory unit. The readout circuit further includes a detection circuit; the detection circuit and the precharge circuit are connected at the first node A. 
         [0036]    The detection circuit includes a third NOT gate X 3 , a fourth NOT gate X 4 , a first NAND gate X 5 , a sixth NOT gate X 6 , a first trigger X 7  and an eighth NOT gate X 8 . 
         [0037]    An input of the third NOT gate X 3  is connected to the first node A, an output of the third NOT gate X 3  and an input of the fourth NOT gate X 4  are connected at a third node C, an output of the fourth NOT gate X 4  and an input for a clock signal of the first trigger X 7  are connected at a fourth node D, an inverse reset terminal of the first trigger X 7  is connected to an output of the eighth NOT gate X 8 , an input of the eighth NOT gate X 8  is connected to a first signal terminal, an output QN of the first trigger X 7  is connected to an input of the first NAND gate X 5 , another input of the first NAND gate X 5  is connected to a first read terminal, an output of the first NAND gate X 5  is connected to an input of the sixth NOT gate X 6 , the first NAND gate X 5  is further connected to the third node C. 
         [0038]    Preferably, the output of the fourth NOT gate X 4  is connected to a clock signal terminal CP of the first trigger X 7 . 
         [0039]    Preferably, the readout circuit further includes a reset circuit; the reset circuit is connected to the precharge circuit at the first node A. 
         [0040]    The reset circuit includes a fourth transistor M 4 , a source of the fourth transistor M 4  is connected to the first node A, a gate of the fourth transistor M 4  is connected to the first signal terminal, a drain of the fourth transistor M 4  is grounded. 
         [0041]    Preferably, the control circuit includes a first NOT gate X 1  and a second NAND gate X 2 , wherein an input of the first NOT gate X 1  is connected to the first node A, an output of the first NOT gate X 1  is connected to an input of the second NAND gate X 2 , another input of the second NAND gate X 2  is connected to the first read terminal, an output of the second NAND gate X 2  is connected to an output signal terminal. 
         [0042]    Preferably, the precharge circuit includes a charge transistor M 0 , a source of the charge transistor M 0  is connected to a power source potential VDD, a drain of the charge transistor M 0  is connected to the first node A, and a gate of the charge transistor M 0  is connected to a precharge signal. 
         [0043]    Preferably, the charge transistor M 0  can be selected as a P-type or N-type charge transistor. For the P-type charge transistor, the charging speed is slower, and the highest charging potential can be the power source potential VDD. For the N-type charge transistor, the charging speed is faster, and the highest charging potential can be VDD-VthM 0 . Preferably, the N-type charge transistor is used in the present invention for obtaining a faster reading speed. 
         [0044]    Further, the precharge circuit further includes a first transistor M 1 , a second transistor M 2  and a third transistor M 3 ; wherein the first transistor M 1  and the second transistor M 2  forms a mirror circuit, both sources of the first transistor M 1  and the second transistor M 2  are connected to the power source potential VDD, a gate of the first transistor M 1  is connected to a gate of the second transistor M 2 , a drain of the first transistor M 1  is connected to a source of the third transistor M 3 , a drain of the second transistor M 2  is connected to a reference current, a drain of the third transistor M 3  is connected to the first node A, a gate of the third transistor M 3  and an output of the first NOT gate X 1  are connected at a second node B. 
         [0045]    For selection of the reference current (Iref), two factors should be considered: the reading time and the anti-interference capacity. When Iref is selected to be higher, the anti-interference capacity is stronger but the speed of reading Programmed Cell will be reduced. When Iref is selected to be lower, the anti-interference capacity of the circuit will be reduced but the speed of reading Programmed Cell will be increased. In the present invention, Iref is designed to be adjustable, and the most proper value of Iref can be selected according to the actual test result. 
         [0046]    A control method of the readout circuit includes: 
         [0047]    step (1): the first signal terminal is configured as a high level, the precharge signal is configured as a low level, and the charge transistor M 0  is turned off. 
         [0048]    step (2): the first signal is changed from the high level to the low level, the signal of the first read terminal is changed from the low level to the high level, so that the precharge circuit performs a charging process to charge the memory unit. 
         [0049]    step (3): a potential of the first node A is controlled to be higher than a reversal voltage V 3  of the third NOT gate X 3 , the precharge signal is changed as the low level, so as to turn the charge transistor M 0  off, and then a precharging process is completed. Meanwhile, a potential of the second node B is reduced to turn the third transistor M 3  on. A reversal voltage of the first NOT gate X 1  is V 1 , and V 3  is controlled to be higher than V 1  to ensure the charge transistor M 0  is turned off after the third transistor M 3  is turned on. 
         [0050]    The working principle of the control method is as follows. 
         [0051]    When the first signal terminal PD_EN is the high level, the circuit is on standby. At this time the first node A is pulled-down to 0 by the fourth transistor M 4 , the first trigger X 7  is in a reset state, and the output QN of the first trigger X 7  outputs 1. Because both the first reading signal and the Pre_charge signal are now 0, the charge transistor M 0  is turned off. 
         [0052]    When the first signal terminal is changed from 1 to 0, the first reading signal is correspondingly changed from 0 to 1. All signals of three inputs of the first NAND gate X 5  are 1, the Pre_charge signal is 1, the charge transistor M 0  is turned on, and the power source potential VDD charges the first node A by the charge transistor M 0 . 
         [0053]    After the voltage of the first node A increases gradually to reach the reversal voltage V 3  of the third NOT gate (the third inverter) X 3 , the electrical level of the third node C begins to reduce. When the electrical level of the third node C is reduced to 0, the Pre_charge signal is also changed to 0. At this time the charge transistor M 0  is turned off, and then the precharging process is completed. 
         [0054]    Because the potential of the first node A increases, and after the potential of the first node A increases to reach the reversal voltage V 1  of the first NOT gate X 1 , the potential of the second node B reduces correspondingly, which causes the third transistor M 3  to be turned on. The magnitude of the pull-up current is determined by the current of the second transistor M 2  mirrored by the first transistor M 1 . 
         [0055]    The reversal voltage V 3  of the third NOT gate X 3  and the reversal voltage V 1  of the first NOT X 1  are designed precisely, so that upon the potential of the first node A is larger than the reversal voltage V 1  of the first NOT X 1 , the charging process is completed, the third transistor M 3  is turned on, and the potential of the first node A is clamped by the first NOT gate X 1  and the third transistor M 3 . In order to ensure the third transistor M 3  is turned on when the charge transistor is turned off, V 3  can be selected to be larger than V 1 . 
         [0056]    Because the distance between the first NOT gate X 1  and the third NOT X 3  in the layout can be very close and their circuit structures are also very similar, values of V 1  and V 3  can be set much precisely by simulation, and it is not easy to generate errors in the manufacturing process. 
         [0057]    In the present invention, the charging time of the first node A can be saved greatly by using a manner that reversal of the first NOT gate X 1  is detected by reversal of the third NOT gate X 3 , and then the reading time of the whole circuit can be reduced correspondingly. During the whole charging process, the potential of the fourth node D is changed from 0 to 1, the potential of the output QN of the first trigger X 7  is changed from 0 to 1, so that the Pre_charge signal is locked as a 0 state, preventing the memory unit from being charged again after the precharging process is completed. 
         [0058]    After the precharging process is completed, the potential of the first node A is the high level. At this time if the decoded EEPROM is the erased cell, and because the starting voltage of the erased cell is very high, it may be now considered no current flowing through the cell, the first node A is maintained in the original state, and output thereof outputs 1. The timing diagram of the reading “1” is shown in  FIG. 4 . 
         [0059]    If the decoded EEPROM is the programmed cell and because the starting voltage of the programmed cell is lower, a certain current (about 8 uA) flows through the cell, so that the potential of the first node A is pulled-down, and the output thereof outputs 0. The timing diagram of the reading “0” is shown in  FIG. 5 . 
         [0060]    Because the potential of the first node A is clamped nearby the reversal voltage of the first NOT gate X 1  after the precharging process is completed, when EEPROM cell is read there is a current flowing through EEPROM cell, then the potential of the first node A will reduce. Meanwhile, voltage of the gate of the third transistor M 3  will increase, and the pull-up current will reduce, which is equivalent to a positive feedback, and can speed up the reading action. Moreover, the reading process has little relationship to the reference current and the current of EEPROM cell, which avoid negative influence of current due drifting of the manufacturing process. When the reading period is ended, the signal of the first signal terminal is recovered as 1, the signal of the first reading terminal is recovered as 0, and then the whole circuit is reset to prepare for performing a next reading operation. 
         [0061]    In the conventional art, the first node A is charged by using the signal Pre_charge with a fixed pulse width. When there are many number of the readout circuits, because these readout circuits will widespreadly distribute across the layout, it cannot avoid some negative influences of the manufacturing process. In the present invention, the Pre_charge signal is not a signal with a fixed pulse width, and generated by a circuit formed by the third NOT gate X 3 , the fourth NOT gate X 4 , the sixth NOT gate X 6 , the eighth NOT gate X 8 , the first NAND gate X 5  with three inputs and the first trigger X 7 . 
         [0062]    When the signal of the first signal terminal is changed from “1” to “0” and the signal of the first reading terminal is changed from “0” to “1”, the circuit performs the charging process. When the potential of the first node A is higher than the reversal voltage V 3  of the third NOT gate X 3 , the signal of the third node C is reduced to “0”. The Pre_charge signal is now “0”, the charge transistor M 0  is turned off, and then the circuit completes the precharging process. Meanwhile, as the potential of the first node A increases gradually, the potential of the second node B reduces gradually, and the third transistor M 3  (as the pull-up transistor) begins to be turned on. If the reversal voltage of the first NOT gate X 1  is V 1 , then when V 3 &gt;V 1 , it will ensure the charge transistor M 0  is turned off after the third transistor M 3  (as the pull-up transistor) is turned on. Because the distance between the first NOT gate X 1  and the third NOT gate X 3  in the layout can be very close, this arrangement minimizes the negative influence of the manufacturing process. 
         [0063]    The function of the circuit formed by the fourth NOT gate X 4 , the first trigger X 7  and the eighth X 8  is that after the first node A is precharged, D terminal of the first trigger generates a rising edge signal, so that the output QN of the first trigger X 7  is set as “0”. At this time it can ensure the Pre_charge signal is always “ 0 ” during the reading period after the precharging process is completed, for preventing a false charging action due to change of the first node A. After end of one reading period, the first trigger X 7  is reset to prepare for a next reading period. 
         [0064]    In the circuit design, as long as it ensure the reversal voltage V 3  of the third NOT gate X 3  is larger than the reversal voltage V 1  of the first NOT gate X 1 , the circuit can successfully perform the precharging process, for avoiding design of a circuit generating a charging signal with a fixed pulse width. Meanwhile, the charging time is dependent on the reversal voltage of the third NOT gate X 3 . As long as the first node A is charged and its voltage is up to the reversal voltage of the third NOT gate X 3 , the charge transistor M 0  is turned off (at this time the pull-up transistor M 3  must be turned on), so that the charging time is saved and then the reading speed for data is increased. 
         [0065]    In order to solve various problems present in the prior art, the invention improves the readout circuit by arranging a detection circuit in the readout circuit to implement detection of the precharging process. The charging time of the first node A can be saved greatly by using a manner that reversal of the first NOT gate X 1  is detected by reversal of the third NOT gate X 3 , and then the reading time of the whole circuit can be reduced correspondingly. During the whole charging process, the potential of the fourth node D is changed from 0 to 1, the potential of the output QN of the first trigger X 7  is changed from 0 to 1, so that the Pre_charge signal is locked as a 0 state, preventing the memory unit from being charged again after the precharging process is completed. 
         [0066]    Although the invention is illustrated and described herein with reference to specific embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the invention.