Abstract:
A driver to provide low voltage swings on a bus with fast switching times, the driver comprising two pairs of pullup and pulldown nMOSFETs, each pair operated in complementary fashion to each other, each pair with a high voltage rail at a smaller voltage than the data input logic HIGH voltage, and where each substrate of the nMOSFETs are biased so as to reduce their threshold voltages.

Description:
FIELD OF INVENTION 
     The present invention relates to drivers for buses, and more particularly to low swing, high performance and low power differential CMOS trisate drivers. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a prior art low swing CMOS driver. 
     FIG. 2 illustrates an embodiment of a low swing, high performance and low power differential CMOS driver with tristate capabilities. 
     FIG. 3 illustrates another embodiment of a low swing, high performance and low power differential CMOS driver with tristate capabilities. 
    
    
     BACKGROUND 
     Rapidly increasing circuit integration density, coupled with accompanying on-die heat dissipation problems, has motivated strong interest in exploring low power and low voltage circuit methodologies, while retaining high performance. In particular, long point-to-point interconnects between and within microprocessor datapath functional unit blocks have become, with increased integration, major on-chip performance and power bottlenecks. This is primarily because interconnect capacitance per unit length, dominated by sidewall fringing and cross-coupling, increases hyperbolically with lateral dimensional scaling of interconnects. 
     Mixed (multiple) voltage swing based CMOS circuit techniques have been studied previously for high performance and low power on-chip datapath interconnects. See &#34;Sub 1V Swing Internal Bus Architecture for Future Low Power ULSI&#39;s&#34;, Y. Nakagome, et al., IEEE Journal of Solid State Circuits, April 1993, pp. 414-419; and &#34;Exploring the Design Space of Mixed Swing QuadRail for Low Power Digital Circuits&#34;, R. K. Krishnamurthy and L. R. Carley, to appear in IEEE Trans. on VLSI Systems, September 1997. FIG. 1 illustrates the general principle behind these approaches. Essentially, the voltage swings across long interconnects, such as bus line 110, are suppressed by employing an additional pair of power supply rails (V dd2  and V SS2 ). For a given V dd2  and V SS2 , reducing the low voltage swing V dd2  -V SS2  offers a nearly linear to quadratic reduction in interconnect power depending upon how the additional pair of power rails are generated. 
     Dynamic drivers, which cause voltage swings even if their input data remains constant, have generally much larger switching activity than static drivers and thus consume more power. It is therefore advantageous to provide static drivers with low voltage swings, but which have faster switching times than prior art static drivers and which provide less unwanted power dissipation than prior art dynamic drivers. It is also advantageous to provide drivers that require only three power rails (one rail to provide a LOW voltage and the other two rails to provide first and second HIGH voltages). 
     DETAILED DESCRIPTION OF EMBODIMENTS 
     FIG. 2 illustrates driver 200 providing complementary output signals on interconnect or bus lines 205 to receiver 210 in response to a digital input voltage signal at terminal 215. Receiver 210 is modeled as a low-to-high differential sense amplifier. Driving bus lines 205 with complementary output signals, along with differencing the output signals by receiver 210, allows for large common mode noise rejection, and consequently improved noise immunity. An enable signal is applied to terminal 220 so that driver 200 can be tristated (i.e., provides a high impedance to bus lines 205) when the enable signal is LOW (V ss1 ). 
     Consider the case in which terminal 220 is held HIGH. Pullup nMOSFET 225 drives bus line 205a to a voltage min{V dd2  -V DS , V dd1  -V th  } when ON, where V dd1  is the full swing supply voltage applied to the gate of nMOSFET 225 when NOR gate 240a is providing a HIGH logic level, V th  is the threshold voltage of nMOSFET 225, and V DS  is the drain-to-source voltage drop of nMOSFET 225 when ON. For most practical cases, V DS  can be ignored. However, when nMOSFET 225 is being driven ON, because of inverter 235, pulldown nMOSFET 250 is driven ON, which drives bus line 205b to voltage V SS1 . 
     Because of NOR gates 240a and 240b, nMOSFETs 225 and 245 are switched in complementary fashion respect to each other and nMOSFETs 230 and 250 are in switched in complementary fashion with respect to each other. Because of inverter 235, nMOSFETs 225 and 230 are switched in complementary fashion with respect to each other and nMOSFETs 245 and 250 are switched in complementary fashion with respect to each other. Consequently, when nMOSFET 225 is ON, nMOSFET 245 is OFF, nMOSFET 230 is OFF, nMOSFET 250 is ON, bus line 205a is driven to min{V dd2  -V DS , V dd1  -V th  }, and bus line 205b is driven to V ss1 . Also, when nMOSFET 225 is OFF, nMOSFET 245 is ON, nMOSFET 230 is ON, nMOSFET 250 is OFF, bus line 205a is driven to V ss1 , and bus line 205b is driven to min{V dd2  -V DS , V dd1  -V th  }. (For simplicity of discussion only, we assume that all shown nMOSFETs have the same threshold voltages and the same drain-to-source voltage drops when ON.) 
     For the case in which terminal 220 is held LOW, pullup nMOSFETs 225 and 230 are OFF, and pulldown nMOSFETs 255 and 260 are OFF, so that driver 200 provides a high impedance to bus lines 205a and 205b from the rails providing V ss1  and V dd2 . 
     The digital input voltage signal will have a data-high voltage when in its HIGH state and a data-low voltage when in its LOW state. The voltage V dd2  is chosen to be less than the data-high voltage. In a preferred embodiment, V ss1  will be equal to the data-low voltage so that driver 200 requires only three power rails. Note that other embodiments may be realized in which the drain voltages of nMOSFETs 225 and 230 may be different from each other. Similarly for the source voltages of nMOSFETs 255 and 260. 
     In the particular embodiment shown in FIG. 2, solid lines 265 indicate that the substrates of the shown nMOSFETs may be biased to voltage V ss1 . However, provided V dd2  is not much greater than 500 mV+V ss1 , the substrates may be biased to voltage V dd2 , as indicated by dashed lines 270. By biasing the substrates at a voltage above V ss1 , the p-n junctions within the shown nMOSFETs are slightly forward biased. This decreases the threshold voltages of the shown nMOSFETs. With decreased threshold voltages, the shown nMOSFETs source or sink larger currents for the same gate-source voltages, which allows driver 200 to drive bus lines 205 faster. 
     In other embodiments, the substrates of the shown nMOSFETs may be biased to voltages other than V dd2  and V ss1  by a bias circuit. Also, other means may be employed to reduce the threshold voltages, such as channel ion-implantation. 
     Another embodiment driver 300 is shown in FIG. 3. The operation of driver 300 is similar to that of driver 200, except that only four nMOSFETs rather than six nMOSFETs need be sized for driving bus lines 205a and 205b. 
     Other embodiments may be realized without departing from the scope of the invention as claimed below.