Abstract:
A semiconductor device that has a passing gate with a single gate electrode and a main gate with lower and upper gate electrodes mitigates gate induced drain leakage (GIDL). Additional elements that help mitigate GIDL include the upper gate electrode having a lower work function than the lower gate electrode, and the lower gate electrode being disposed below a storage node junction region while the upper gate electrode is disposed at a same level as the storage node junction region.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The priority of Korean patent application No. 10-2014-0109102 filed on 21 Aug. 2014, the disclosure of which is hereby incorporated in its entirety by reference, is claimed. 
       BACKGROUND OF THE INVENTION 
       [0002]    Embodiments of the present disclosure relate to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device having passing gates that prevents characteristics of a cell transistor from being deteriorated by the passing gate effect, and a method for fabricating the same. 
         [0003]    In order to increase the degree of integration of a semiconductor device, the size of cell transistors are reduced. More specifically, as semiconductor devices are being developed to implement higher levels of integration, a preferred cell layout is changing from an 8F 2  structure to a 6F 2  structure. 
         [0004]    As the degree of integration of semiconductor devices increases, the distance between a gate (word line) coupled to a cell transistor and a bit line coupled to the cell transistor is reduced. As a result, parasitic capacitance between the bit line and the gate may increase such that the operational reliability of the semiconductor device deteriorates. In order to improve the operational reliability of highly integrated semiconductor devices, a buried gate structure has been proposed in which a gate is buried within a semiconductor substrate. A conventional buried gate structure can be incorporated within a semiconductor device having a 6F 2  layout, and can include a metal film as a gate electrode. 
         [0005]    However, in a conventional buried gate structure, a portion of the buried gate electrode is disposed on the same level as a junction region that is adjacent to the buried gate. This causes Gate Induced Drain Leakage (GIDL) to occur where the buried gate electrode is on the same level as the junction region. More specifically, when a gate of a cell array of the semiconductor device is a line type gate, a portion of the buried gate disposed in a device isolation film and adjacent to an active region, which is referred to as a passing gate, is present in a conventional device. The passing gate may exacerbate the occurrence of GIDL. The GIDL discharges charges stored in the cell array, thereby deteriorating retention characteristics of the semiconductor device. 
       BRIEF SUMMARY OF THE INVENTION 
       [0006]    Various embodiments of the present disclosure are directed to providing a semiconductor device having passing gates and a method for fabricating the same that substantially obviate one or more problems due to limitations and disadvantages of the related art. 
         [0007]    An embodiment of the present disclosure relates to a semiconductor device configured to prevent deterioration of a cell transistor by reducing Gate Induced Drain Leakage (GIDL) caused by a passing gate. 
         [0008]    In accordance with an aspect of the present invention, a semiconductor device includes: a device isolation film defining an active region; a main gate having first and second gate electrodes buried in the active region; and a passing gate having a single gate electrode buried in the device isolation film. 
         [0009]    In accordance with an aspect of the present invention, a semiconductor device includes: a device isolation film defining an active region; a first gate electrode buried in the active region and the device isolation film; and a second gate electrode located over portions of the first gate electrode that are buried in the active region, and not disposed over portions of the first gate electrode that are buried in the device isolation film between adjacent active regions. 
         [0010]    In accordance with an aspect of the present invention, a semiconductor device includes: a device isolation film defining an active region; a main gate having first and second gate electrodes provided in a first trench, the second gate electrode provided over the first gate electrode and having an upper surface provided within the first trench; a passing gate having a third gate electrode provided in a second trench, the third gate electrode having an upper surface provided within the second trench; and a dielectric film having first and second portions, the first portion extending into the first trench and having a lower end proximate to the upper surface of the second gate electrode, the second portion extending into the second trench an and having a lower end proximate to the upper surface of the third gate electrode, wherein the lower end of the second portion is at a lower level than the lower end of the first portion. 
         [0011]    In accordance with an aspect of the present invention, a method for forming a semiconductor device includes: forming a device isolation film defining an active region; forming a gate trench by etching the active region and the device isolation film; forming a first gate electrode in the gate trench; forming a second gate electrode over the first gate electrode; selectively etching a portion of the second gate electrode in a passing gate region; and forming a capping film over the second gate electrode and the first gate electrode to cover portions of the first gate exposed by the selective etching. 
         [0012]    The second gate electrode is formed by implanting one or more of nitrogen (N), oxygen (O), arsenic (As), aluminum (Al), and hydrogen (H) ions into an upper portion of the first gate electrode. 
         [0013]    The selectively etching the second gate electrode includes etching a portion of the second gate electrode interposed between storage node junction regions of adjacent active regions. 
         [0014]    The first gate electrode is disposed below the storage node junction regions, and the second gate electrode is disposed at a substantially same level as the storage node junction regions. 
         [0015]    A work function of the first gate electrode is higher than a work function of the second gate electrode. 
         [0016]    It is to be understood that both the foregoing general description and the following detailed description of embodiments are exemplary and explanatory. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIG. 1A  is a plan view illustrating a semiconductor device according to an embodiment. 
           [0018]      FIG. 1B  is a cross-sectional view illustrating the semiconductor device taken along the line A-A′ of  FIG. 1A . 
           [0019]      FIGS. 2A to 8A  are plan views illustrating a method for forming the semiconductor device shown in  FIG. 1A . 
           [0020]      FIGS. 2B to 8B  are cross-sectional views taken along line A-A′ of  FIGS. 2A to 8A , respectively. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0021]    Reference will now be made in detail to certain embodiments, examples which are illustrated in the accompanying drawings. The embodiments described in the specification and shown in the drawings are purely illustrative and are not intended to represent the full scope of this disclosure, such that various equivalents and modifications may be made within the scope of this disclosure. 
         [0022]      FIG. 1A  is a plan view illustrating a semiconductor device according to an embodiment.  FIG. 1B  is a cross-sectional view illustrating the semiconductor device taken along the line A-A′ of  FIG. 1A . 
         [0023]    Referring to  FIGS. 1A and 1B , active regions  120  defined by a device isolation film  110  may be formed over a semiconductor substrate  100 . Each active region  120  may cross two gates  130 , and may be divided into three regions by the two gates  130 . That is, each active region  120  is divided into a bit-line contact region disposed between two gates  130  and two storage node contact regions located at sides of the bit-line contact region. In other words, for each active region, a central portion of the active region may be a bit line contact region, and end portions of the active region may be storage node contact regions according to an implementation. In the active region  120 , a bit-line junction region  140   b  is formed in the bit-line contact region, and storage node junction regions  140   s  are formed in the storage node contact regions. 
         [0024]    The gate  130  may be a buried gate buried in a trench that runs through the active region  120  and the device isolation film  110 . In such an embodiment, a portion of the buried gate  130  buried in the active region  120  is a main gate  130 M, and a portion of the buried gate  130  that is buried in the isolation film  110  between adjacent storage node junction regions  140   s  is a passing gate  130 P. In the embodiment shown in  FIG. 1A , passing gates  130 P are disposed at regions denoted by dotted circles. As seen in  FIG. 1A , the passing gate  130 P is located between opposing ends of adjacent active regions  120 . The adjacent active regions  120  are arranged in a line that crosses gates  130 . 
         [0025]    Although the main gate  130 M and the passing gate  130 P are both described above as being portions of gate  130 , the main gate  130 M and the passing gate  130 P have different structures. While the main gate  130 M and the passing gate  130 P may share a contiguous first gate electrode  130   a , the main gate  130 P may also include a second gate electrode  130   b  that is not disposed over the first electrode  130   a  of the passing gate. In other words, while the main gate  130 M has two gate electrodes, the passing gate  130 P only has a single gate electrode. The first gate electrode  130   a  may be referred to as a lower gate electrode  130   a , while the second gate electrode  130   b  may be referred to as an upper gate electrode  130   b . In an embodiment, the first gate electrode  130   a  material has a different work function than the second gate electrode  130   b . In addition, the depth of the portion of the first gate electrode  130   a  disposed at the passing gate  130 P may have a greater depth than the portion of the first gate electrode  130   a  disposed at the main gate  130 M. In an embodiment, the main gate  130 M includes a first gate electrode  130   a  having a high work function and a second gate electrode  130   b  having a lower work function than the first gate electrode  130   a . In such an embodiment, the first gate electrode  130   a  may be disposed in a region that does not contact a junction region  140   s , and the second gate electrode  130   b  may be formed in a region contacting the junction region  140   s . More specifically, the first gate electrode  130   a  may be disposed at a lower level than storage node junction region  140   s  (e.g., the upper surface of the first gate electrode  130   a  is at a lower level than the lower surface of the storage node junction region  140   s ), while at least a portion of the second gate electrode  130   b  may be disposed at a same level as the storage node junction region  140   s . In other words, a portion of second gate electrode  130   b  may overlap with storage node junction region  140   s , while no portion of first gate electrode  130   a  overlaps the storage node junction region  140   s . Each of these features—the passing gate  130 P not having an upper second gate electrode  130   b , and the first gate electrode  130   a  having a higher work function than second gate electrode  130   b -helps to mitigate GIDL while maintaining good device performance. 
         [0026]    In an embodiment, the first gate electrode  130   a  includes a metal material, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), etc. The second gate  130   b  may include a conductive layer with a lower work function than the first gate electrode  130   a , such as N +  polysilicon. Alternatively, the second gate electrode  130   b  may be formed by implanting at least one of nitrogen (N), oxygen (O), arsenic (As), aluminum (Al), and hydrogen (H) ions into the conductive film used to form first gate electrode  130   a.    
         [0027]    In addition, according to an embodiment, a gate trench in which the gate  130  is buried may have a fin structure in which the active region  120  protrudes more than the device isolation film  110 . In other words, a depth of the passing gate  130 P, which runs across device isolation film  110 , is greater than a depth of the main gate  130 M which runs across active region  120 . Accordingly, the trench for gate  130  has different depths for a main gate region and a passing gate region. 
         [0028]    A capping film  160  for isolating the gate  130  is formed over the buried gate  130 . A pad insulation film pattern  150  that defines the trench for gate  130  and a capping film  160  are formed over the active region  120  and the device isolation film  110 . 
         [0029]      FIGS. 2A to 8A  are plan views illustrating a method for forming the semiconductor device shown in  FIG. 1A .  FIGS. 2B to 8B  are cross-sectional views taken along line A-A′ of  FIGS. 2A to 8A , respectively. 
         [0030]    Referring to  FIGS. 2A and 2B , a pad oxide film (not shown) and a pad nitride film (not shown) are formed over a semiconductor substrate  200 , and a hard mask pattern (not shown) defining an active region  202  is formed over the pad nitride film. In order to form the hard mask pattern, after a line-type pattern is formed using a Spacer Pattern Technology (SPT) process, the line pattern is etched in units of a predetermined length corresponding to a length of an active region using a cut mask. The active region  202  may be formed to obliquely cross a gate formed in a subsequent process. In an embodiment, the gate is a word line. 
         [0031]    Subsequently, the pad nitride film, the pad oxide film, and the semiconductor substrate  200  are sequentially etched using the hard mask pattern as an etch mask, resulting in a device-isolation trench that defines the active region  202 . In this case, the etching process may be a dry etching process. 
         [0032]    Subsequently, a sidewall insulation film (not shown) is formed at a sidewall of the device isolation trench. The sidewall insulation film may include a wall oxide film, and may be formed over a sidewall either by depositing an oxide film at a trench sidewall, or by a dry or wet etching method. 
         [0033]    Subsequently, after a device isolation trench is filled with a device-isolation insulation film, the device-isolation insulation film is etched until the active region  202  is exposed, thereby forming a device isolation film  204  that defines the active region  202 . In various embodiments, the device isolation film  204  may include a Spin On Dielectric (SOD) material or High Density Plasma (HDP) oxide film having superior gapfill characteristics. Alternatively, the device isolation film  204  may be a nitride film or a stacked structure of oxide film and nitride film. 
         [0034]    Subsequently, impurities are implanted into the active region  202 , thereby forming a junction region  206 . 
         [0035]    Referring to  FIGS. 3A and 3B , a pad insulation film (not shown) is formed over the active region  202  and the device isolation film  204 , and a photoresist pattern (not shown) defining a gate region is formed over a pad insulation film. Subsequently, the pad insulation film is etched using the photoresist pattern as an etch mask, thereby forming a pad insulation film pattern  208 . The active region  202  and the device isolation film  204  are etched using the pad insulation film pattern  208  as an etch mask, thereby forming a gate trench for a buried gate. 
         [0036]    The gate trench may be a substantially linear, or line type trench. The active region  202  and the device isolation film  204  are simultaneously etched to form the line-shaped trench. In an embodiment, the device isolation film  204  is more deeply etched than the active region  202  due to an etch selectivity between the active region  202  and the device isolation film  204 . Therefore, the gate trench may have a fin structure in which the active region  202  is more protruded than the device isolation film  204  in the gate trench. 
         [0037]    Subsequently, the bottom surface and a sidewall of the gate trench may be oxidized through an oxidation process, or an oxide film may be deposited through a deposition process, thereby forming a gate insulation film (not shown). 
         [0038]    A conductive film is deposited in the gate trench until the gate trench is filled. The conductive film is planarized until the pad insulation film pattern  208  is exposed. In an embodiment, the planarization may be accomplished by a chemical mechanical planarization (CMP) process. Subsequently, the conductive film is etched back and cleaned, thereby forming first buried gate electrodes  210   a  and  210   b . In various embodiments, the conductive film may include a metal material such as titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), etc. 
         [0039]    For example, a thin titanium nitride (TiN) film or tantalum nitride (TaN) film may be conformally deposited in a gate trench, and a tungsten (W) film may then be deposited over the metal nitride film until the trench is filled. In other embodiments, a metal film is formed by stacking a titanium nitride (TiN) film and a tantalum nitride (TaN) film, or the titanium nitride (TiN) film, the tantalum nitride (TaN) film, and the tungsten (W) film are sequentially deposited, resulting in the first buried gate electrode. 
         [0040]    Referring to  FIGS. 4A and 4B , a second gate conductive film is deposited over the first buried gate electrodes  210   a  and  210   b  until the gate trench is filled, and is then planarized. Subsequently, the planarized second-gate conductive film is etched back, so that the second buried gate electrodes  212   a  and  212   b  are formed over the first buried gate electrodes  210   a  and  210   b.    
         [0041]    The second gate conductive film may be formed of a conductive material having a lower work function than the first gate conductive film. In an embodiment, the second gate conductive film includes N +  polysilicon. 
         [0042]    Alternatively, the second buried gate electrodes  212   a  and  212   b  may be formed by implanting at least one of nitrogen (N), oxygen (O), arsenic (As), aluminum (Al), and hydrogen (H) ions into an upper portion of the first buried gate electrodes  210   a  and  210   b . For example, a first gate conductive film may be deposited in the gate trench, planarized, and etched back to the height of second buried gate electrodes  212   a  and  212   b  as shown in  FIG. 4B . Subsequently, nitrogen (N) ions may be implanted into an upper portion of the buried gate electrodes, thereby forming second gate electrodes  212   a  and  212   b  which are doped with nitrogen ions over first gate electrodes  210   a  and  210   b  which are not doped with nitrogen ions. 
         [0043]    In another embodiment, a barrier film is formed at an upper portion of the first buried gate electrodes  210   a  and  210   b . In such an embodiment, nitrogen ions are implanted into an upper portion of the first buried gate electrodes  210   a  and  210   b , thereby forming a barrier film. Such a barrier film reduces contact resistance between the first buried gate electrodes  210   a  and  210   b  and second buried gate electrodes  212   a  and  212   b  that are subsequently formed over the first buried gate electrodes  210   a  and  210   b.    
         [0044]    Referring to  FIGS. 5A and 5B , an insulation film  214  is deposited over the second buried gate electrodes  212   a  and  212   b  and the pad insulation film pattern  208  until the gate trench is filled, and the insulation film  214  is then planarized. The insulation film  214  may include an oxide film deposited by a spin-on dielectric (SOD) or high density plasma (HDP) process. 
         [0045]    Referring to  FIGS. 6A and 6B , a passing-gate open mask pattern  216  with openings over the passing gate regions is formed over the insulation film  214 . The passing gate open mask pattern  216  may be a hole-type mask pattern. In an embodiment, the cut mask that has been used to form a hard mask pattern defining the active region  202  as explained with respect to  FIG. 2A  may be used as a mask to form the passing gate open mask pattern  216 . 
         [0046]    Referring to  FIGS. 7A and 7B , the insulation film  214  of the passing gate region and the second buried gate electrode  212   b  are removed by an etching process using the passing gate open mask pattern  216  as an etch mask. 
         [0047]    Referring to  FIGS. 8A and 8B , the remaining portions of insulation film  214  and the passing gate open mask pattern  216  are removed, and the capping film  218  is formed over the first buried gate electrode  210   b  and the second buried gate electrode  212   a  to fill the gate trench. The capping film  218  may be formed to insulate and protect the buried gates, and may include a nitride film or an oxide film. In an embodiment, the buried gates include a stacked structure of a nitride film and an oxide film. 
         [0048]    As is apparent from the above description, embodiments of the present disclosure can reduce GIDL caused by a passing gate to prevent characteristics of the cell transistor from being deteriorated, so that a data retention time can be improved and the reliability achieved after packaging completion can also be improved. 
         [0049]    Those skilled in the art will appreciate that embodiments of the present disclosure may be carried out in other ways than those set forth herein without departing from the spirit and characteristics of these embodiments. The above embodiments are therefore to be construed in all aspects as illustrative and not restrictive. For example, the embodiments may be implemented in a layout configuration other than 6F 2  structure, e.g., 4F 2  structure. 
         [0050]    Various alternatives and equivalents to the specifically described embodiments are possible. Embodiments are not limited by the type of deposition, etching polishing, and patterning steps described herein. Nor is the disclosure limited to any specific type of semiconductor device. For example, embodiments may be implemented in a dynamic random access memory (DRAM) device or nonvolatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.