Abstract:
A circuit for spike-free clock switching which offers asynchronous switching between two clock signals of the same frequency and of any desired phase angle, which is purely digital, which can be fully implemented in an integrated module, and which avoids spikes/glitches during switching.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a circuit for spike-free clock switching between clock signals which, as a digital circuit, can be fully implemented in an integrated circuit and which allows any desired phase angle of the clock signals. 
     In switching systems in which clock signals are duplicated for reasons of redundancy, the intention is to switch between the two clock signals of the same frequency and of any desired different phase angle without spikes/glitches occurring in the process. 
     This problem is conventionally solved by circuits which have a combination of monostable multivibrators with discrete components, such as resistors and capacitors for example. In these circuits, it becomes disadvantageously apparent that they cannot be fully implemented in an integrated circuit. The abovementioned objective also can be achieved via purely digital, fully integrable circuits, but they do not allow any desired phase angle of the clock signals. 
     The present invention is, therefore, directed to a circuit arrangement for switching between clock signals which, as a digital circuit, can be fully implemented in an integrated circuit and which allows any desired phase angle of the clock signals. 
     SUMMARY OF THE INVENTION 
     Accordingly, the inventive circuit for switching from a first clock signal to a second clock signal according to a clock select signal includes: a first circuit branch for a first clock signal, the first circuit branch having a first flip-flop, a second flip-flop, a third flip-flop, a first AND gate and a second AND gate, an output of the first flip-flop being connected to a data input of the second flip-flop, an output of the second flip-flop being connected to a second input of the first AND gate, an output of the first AND gate being connected to a data input of the third flip-flop, and an output of the third flip-flop being connected to a second input of the second AND gate, wherein an inversion of the clock select signal is fed as a select signal for the first clock signal to a data input of the fist flip-flop and to a first input of the first AND gate, wherein the first clock signal is fed to a clock input of the first flip-flop, a clock input of the second flip-flop, an inverting clock input of the third flip-flop and a first input of a second AND gate, and wherein an alarm signal associated with the first clock signal is applied to a reset input of the third flip-flop: a second circuit branch for a second clock signal, the second circuit branch having a fourth flip-flop, a fifth flip-flop, a sixth flip-flop, a third AND gate and a fourth AND gate, an output of the fourth flip-flop being connected to a data input of the fifth flip-flop, an output of the fifth flip-flop being connected to a second input of the third AND gate, an output of the third AND gate being connected to a data input of the sixth flip-flop, and an output of the sixth flip-flop being connected to a second input of the fourth AND gate, wherein the clock select signal is fed as a select signal for the second clock signal to a data input of the fourth flip-flop and to a first input of the third AND gate, wherein the second clock signal is fed to a clock input of the fourth flip-flop, a clock input of the fifth flip-flop, an inverting clock input of the sixth flip-flop, and a first input of the fourth AND gate, and wherein an alarm signal associated with a second clock signal is applied to a reset input of the sixth flip-flop; and a combination element having a first input connected to an output of the second AND gate, a second input connected to an output of the fourth AND gate, and an output connected to an output clock signal. 
     Accordingly, the circuit of the present invention is purely digital and requires no discrete components at all. Thus, it can be implemented in an integrated circuit such as, for example, an ASIC (Application Specific Integrated Circuit) or an FPGA (Flash Programmable Gate Array). An asynchronous signal for switching between the clock signals can be applied to the circuit arrangement. The clock signals have any desired phase angle. 
     Additional features and advantages of the present invention are described in, and will be apparent from, the following Detailed Description of the Invention and the Figures. 
    
    
     DESCRIPTION OF THE FIGURES 
     FIG. 1 shows a block diagram of a circuit for switching between clock signals. 
     FIG. 2 shows a circuit diagram of a circuit of the present invention for switching between clock signals at the gate level. 
     FIG. 3 shows a signal state diagram of possible states of individual signals in the case of switching from one clock signal to another clock signal. 
     FIG. 4 shows a state diagram of other possible states of individual signals in the case of switching from one clock signal to another clock signal. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The clock selection circuit CS, to which are fed, on the input side, a clock select signal CLKSEL, a first clock signal B 0 CLK, a second clock signal B 1 CLK, a first clock alarm signal B 0 CLKALA and a second clock alarm signal B 1 CLKALA, outputs the output clock signal BS_BCMCLK on the output side. 
     The clock selection circuit in FIG. 2 has two identical circuit sections, the first circuit section illustrated at the top being assigned to the first clock signal and the second circuit section illustrated at the bottom being assigned to the second clock signal. The clock select signal CLKSEL is fed to the second circuit section as second clock select signal B 1 CLKSEL and, having been inverted via an inverter INV, is fed to the first circuit section as first clock select signal B 0 CLKSEL. The first clock select signal B 0 CLKSEL is fed to the data input D of a flip-flop FF  01  in the first circuit section, and the first clock signal B 0 CLK is fed to the clock input of the flip-flop. The signal output from the first flip-flop at the output Q is fed to the data input D of a second flip-flop FF 02  in the first circuit section, and the clock signal B 0 CLK is fed to the clock input CLK of the flip-flop. The first clock select signal B 0 CLKSEL and the signal output at the output Q of the flip-flop FF 02  are fed to inputs of a logic AND gate AND 01 . The signal output by the AND gate AND 01  is applied to that input of a flip-flop FF 03  which is designed by D, the first clock signal B 0 CLK is applied to the inverting clock input CLK of the flip-flop, and the first alarm signal B 0 CLKALA of the first clock signal B 0 CLK is applied to the reset input RES of the flip-flop. The signal output by the flip-flop FF 3  at its output Q forms an enable signal BOEN for the first clock signal B 0 CLK. The, enable signal B 0 EN for the first clock signal B 0 CLK and the first clock signal B 0 CLK are fed to inputs of a logic AND gate AND 02 . 
     In principle, the second circuit section for the second clock signal is constructed identically to the first circuit section for the first clock signal. 
     A combination element VKG, to which are fead, on the input side, the signals output by the AND gate AND 02  and the AND gate AND 12 , outputs the selected clock signal BS_BCMCLK at its output. As emerges from FIGS. 3 and 4, the clock switching is effected in two phases. If the clock signals are switched, which is represented in FIGS. 3 and 4 in row B 0 CLKSEL by a state change in the clock select signal from the logic high level (H) to the logic low level (L), the clock signal (the, first clock signal B 0 CLK in FIG.  3  and FIG. 4) that has heretofore been activated as the output clock signal is switched off with the first falling edge of this clock signal. In the switching process, the clock signal (the clock signal B 1 CLK in FIG.  3  and FIG. 4) that has heretofore not been activated as the output clock signal is switched on during its logic low level. The switch-on is effected with a delay which results in a clock gap of, as illustrated in FIG. 3, not less than one clock period and, as illustrated in FIG. 4, not more than three clock periods. 
     As emerges from FIGS. 3 and 4, the first clock signal and the second clock signal may be provided by mutually complementary clock signals. The circuit arrangement ensures that in the case of an active clock alarm signal, switching to the associated clock signal cannot be effected. 
     Although the present invention has been described with reference to specific embodiments, those of skill in the art will recognize that changes may be made thereto without departing from the spirit and scope of the invention as set forth in the hereafter appended claims.