Abstract:
A current limit circuit is provided, with a DMOS output transistor DM2. A second DMOS transistor DM1 is provided in parallel with DM2. A pair of matched resistors R12 and R13 are connected to a reference current source and to DM1. If the voltage across R13 exceeds the voltage across R12, a control circuit sinks current away from DM1.

Description:
This application is a continuation of application Ser. No. 07/726,473 abandoned, filed Jul. 8, 1991. 
    
    
     BACKGROUND OF THE INVENTION 
     There is an increasing diversity of requirements for intelligent power ICs, which have to provide protection for thermal limit, transients, overvoltage and short circuit loads. Since the requirements are in addition to the normal requirements for proper functioning of an integrated circuit, there is a need for circuitry which accomplishes the above requirements without being overly complex and which requires a minimum of area on an integrated circuit chip. 
     A recent requirement has arisen specifically for a short circuit current limit on an intelligent power IC which has an intentional and controlled reduction in current limit as the device temperature increases. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic of the present invention; and 
     FIG. 2 is a waveform diagram showing the output of the invention of FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     There is a need for a current limited circuit with a short circuit operation having a negative temperature coefficient, allowing more current to pass at low temperatures before a short circuit condition occurs, than is allowed to pass at high temperatures. 
     Referring to FIG. 1, the circuit of the present invention is shown and is referred to generally with a reference numeral 10. The limit circuit 10 has a DMOS supply voltage shown as VTRIP in FIG. 1. An internal logic voltage supply is also supplied at VINT, as well as references voltages P20IM and N20IM. The DMOS supply voltage VTRIP is provided to the gates of DMOS output device DM2, as well as to the gate of a sensefet structure DM1 embedded within DM2. The DMOS supply voltage is supplied through device R14, which may be either a resistor or an inductor. The drains of DM1 and DM2 are connected to the output node as well as to ground. The emitter of DM2 is connected to capacitor 2, the drain of DM2 and to ground. The source of DM1 is coupled to ground through a resistor R13. A pair of NPN transistors Q15 and Q16 are connected in a Darlington configuration, with their collectors coupled to the gates of DMOS transistors DM1 and DM2 as well as to gate voltage terminal N15. The emitter of transistor Q 15 is connected to the base of transistor Q16, while the emitter of transistor Q16 is connected to ground. 
     A comparator circuit consisting of matched NPN transistors Q13 and Q14 is also provided. The emitters of transistor Q13 and Q14 are connected to ground through resistors R12 and R13, respectively. The bases of transistors Q13 and Q14 are connected together, as well as to the collector of transistor Q13. The collectors of transistors Q13 and Q14 are connected to the outputs of current sources consisting of P-channel transistors MP11 and MP12. The drains of MOS transistors MP11 and MP12 are connected to VINT while their gates are coupled together and connected to P20IM, a reference voltage. A PNP bipolar transistor Q12 has its emitter connected to VINT, and its collector coupled to the drain of an N-channel field effect transistor MN11. The source of transistor MN11 is connected to ground, while its gate is connected to N20IM, a reference voltage source. The base of transistor Q 12 is coupled to VINT through resistor R11 and to the emitter of PNP transistor Q11. The collector of transistor Q11 is coupled to the emitter of transistor Q13, while the base of transistor Q11 is coupled to the collector of transistor Q12. 
     Transistors Q13 and Q14 are a matched comparator, monitoring the voltage difference at the heads of matched resistors R12 and R13. Q11 and Q12, with resistor R11 are the temperature-dependent current source, which create a voltage at resistor R12. At the point where the current through DM1 (which is proportional to the current through DM2) reaches a critical value the comparator switches, and the Darlington configuration of transistors Q15 and Q16 pull the gate voltage of DM1 and DM2 down, limiting the current. In the preferred embodiment the critical value of current through DM1 is approximately 4 milliamps. The current limit variation over temperature depends upon the base emitter voltage variation of Q12 over temperature, and the resistance variation of resistor R11 over temperature. Since base emitter voltage coefficient is normally negative and resistance coefficient is normally positive a net reduction in current is accomplished using the configuration of the preferred embodiment. 
     Transistors Q11, Q12 with resistor R11 and N-channel FET MN11 create a variable reference current, which flows out of the collector of Q11. The current is generated when MN11 sinks current from the base of Q11 and the collector of Q12. This enables Q11 to turn on, sinking current through resistor R11 and the base of Q12. As Q12 turns on more current for the current sink MN11 is sourced from Q12, until an equilibrium point is reached. With high gain transistors, this equilibrium is the point where the current through R11 defines the Q11 collector current. This current is highly temperature dependent. As temperature increases the base emitter voltage across Q12 is reduced, typically by about 2 millivolts per degree centigrade of temperature increase. In addition the resistance of the diffused resistor R11 increases with temperature, in the preferred embodiment by about 0.2% per centigrade degree. The resulting effect is a temperature dependent reference current. 
     The section of the circuit comprising the current source consisting of P-channel field effect transistors MP11 and MP12, bipolar transistors Q13 and Q14, and resistors R12 and R13 create a comparator. The comparator is capable of detecting voltage differences very close to the ground rail of the integrated circuit, and provides a gained up output at node N14. P-channel field effect transistors MP11 and MP12 provide equal currents into transistors Q13 and Q14 respectively at the balance point. Resistor values R12 and R13 are chosen such that the current from transistors MP11 and MP12 do not significantly effect the voltages at the emitters of transistors Q13 and Q14. Variation of the voltages at the emitters of Q13 and Q14 are created by the reference current from transistor Q11, feeding into resistor R12 and current from the sensefet DM1 feeding into resistor R13. Resistors R12 and R13 have matched temperature coefficients and are laid out in the IC to be closely matched. The ratio of resistors R12 to R13 gives the ratio of the sensefet current to that of the reference current for comparator balance. The output structure of the limit circuit 10 consists of a passive device (a resistor or inductor) R14 and DMOS devices DM1 and DM2. The voltage supplied through VTRIP is at a high level (approximately 10 volts in the preferred embodiment) when the DMOS output at DM2 is on, and low at other times. Resistor R14 is provided so current can be sunk through the Darlington configuration of transistors Q15 and Q16 during short circuit operation. The sensefet DM1 is a part of the DMOS output, and produces a current proportional to DM2 approximately in the ratio of the number of cells in the sensefet to the number of cells in the DMOS. 
     The output at node N14 drives the Darlington combination Q15 and Q16, which in the event of the sensefet (DM1) current exceeding the value which causes the voltage at resistor R13 to exceed that across resistor R12 will cause the voltage at node N14 to rise, turning transistors Q15 and Q16 on. This pulls the gate voltage at DM1 and DM2 down, reducing the current capability of DM2 and thus limiting the current. The feedback loop maintains the current limit until the short circuit is removed or the voltage at VTRIP is removed. 
     This circuit is especially beneficial when combined with loads which are expected to reduce in the current at higher temperatures, when the circuit described can switch into short circuit limit operation at a reduced current level. 
     The current limit variation over temperature is shown in FIG. 2. In FIG. 2, the output voltage is held at ten volts, with VINT at 7 volts. The output shown in FIG. 2 represents the current levels at the drain of DM2 for various temperatures. As shown in FIG. 2, the current level during the current limit at 180 degrees is 1.27 amps, while the current limit at -50 degrees is approximately 4.38 amps. 
     While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.