Abstract:
An imaging device includes a focal plane array of demodulation pixel cells. Each of the demodulation pixel cells includes a pinned photodiode, demodulation gates operable to demodulate optical signals sensed by the pinned photodiode and to transfer accumulated photo-charges to a respective one of a multitude of sense nodes, a readout circuit operable selectively to read out signals from the sense nodes, and a background light suppression circuit including cross-coupled current mirrors.

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
       [0001]    This application claims the benefit of priority of U.S. Provisional Patent Application No. 62/338,664, filed on May 19, 2016. The contents of the earlier application are incorporated herein by reference in their entirety. 
     
    
     FIELD OF THE DISCLOSURE 
       [0002]    The present disclosure relates to pinned photodiode (PPD) pixels including current mirror-based background light suppression, and imaging devices including such pixels. 
       BACKGROUND 
       [0003]    Many applications, such as robotics, biometrics, automobile security and navigation, medical imaging, surveillance, and others, require a three-dimensional (“3D”) representation of the environment to avoid time-consuming processing steps required to ensure high quality of the specific task. Thus, real-time 3D-imaging has become an important challenge in the design of modern electronic image sensors. Optical systems can provide various advantages such as very fast 3D-data acquisition. 
         [0004]    One type of device that has been used for photo-detection in the charge domain is a PPD. A pinned photodiode generally has two implants in the substrate, the doping concentrations of which are chosen in such a way that a fully depleted area is created beneath a very shallow non-depleted layer at the substrate surface. As shown, for example, in  FIG. 1 , the two implant steps include a deep n− implant  14  and a shallow p+ implant  16  (assuming a p-type substrate  12 ), where the p+ extends laterally beyond the n− layer in order to create an electrical connection to the substrate  12 . At one side of the structure, a poly-silicon gate  18  is provided to enable the transfer of charges out of the PPD region  14  to a sense node diffusion  20 . The pinned region  14  defines the photo-sensitive area  24  where photons are converted into electric charges. As long as the transfer gate  18  is set to low potential, the photo-generated charges are stored within the PPD region  14 . 
         [0005]    Electronic imaging sensors sometimes have an array of (m×n) photo-sensitive pixels, with x&gt;1 rows and y&gt;1 columns. Each pixel of the array can individually be addressed by dedicated readout circuitry for column-wise and row-wise selection. A block for signal post-processing may be integrated on the sensor. Demodulation pixels are a particular class of pixels that are useful for 3D imaging and other applications. 
         [0006]    Background light (e.g., infrared radiation), however, can have a significant, adverse impact on imaging devices based on PPDs. For example, many 3D-camera systems operate in the non-visible, near-infrared region of the spectrum (e.g., 780 nm-900 nm). In this range of optical wavelengths, the maximal solar irradiance can amount, for example, to 1000 W/m 2 /μm, which can result, in some cases, in millions of electrons being generated in addition to the signal-generated electrons. Thus, sensor-level background suppression techniques are generally needed. 
       SUMMARY 
       [0007]    The present disclosure describes pinned photodiode pixels including current mirror-based background light suppression, and imaging devices including the such pixels. 
         [0008]    For example, in one aspect, a demodulation pixel cell includes a pinned photodiode, demodulation gates operable to demodulate optical signals sensed by the pinned photodiode and to transfer accumulated photo-charges to a respective one of a multitude of sense nodes, a readout circuit operable to read out signals from the sense nodes, and a background light suppression circuit including cross-coupled current mirrors. 
         [0009]    In another aspect, the disclosure describes an imaging device including a focal plane array of demodulation pixel cells. Each of the demodulation pixel cells includes a pinned photodiode, demodulation gates operable to demodulate optical signals sensed by the pinned photodiode and to transfer accumulated photo-charges to a respective one of a multitude of sense nodes, a readout circuit operable selectively to read out signals from the sense nodes, and a background light suppression circuit including cross-coupled current mirrors. 
         [0010]    Some implementations include one or more of the following features. For example, in some instances, the current mirrors are operable to compensate for common mode current resulting from background light. Preferably, the photocurrent generated as a result of background light is split substantially evenly between the current mirrors. In some cases, the demodulation pixel cell includes circuitry operable to apply time domain current mirror chopping. In some instances, the circuitry operable to apply time domain current mirror chopping includes a cross-coupled chopping current mirror circuit. In some implementations, the cross-coupled chopping current mirror circuit is operable to apply time domain chopping to drains of transistors in the cross-coupled current mirrors. In some implementations, the cross-coupled chopping current mirror circuit is operable to apply time domain chopping to gates of transistors in the cross-coupled current mirrors. 
         [0011]    Each one of the demodulation pixel cells further can include, in some instances, a charge exchange switch coupled to gates of transistors in the cross-coupled current mirrors. The charge exchange switch can be operable to be controlled by a clock signal different from clock signals that control switches of the circuitry operable to apply the time domain current mirror chopping. 
         [0012]    In some cases, the cross-coupled chopping current mirror circuit includes a multitude of switches each of which is operable to respond, respectively, either to first or second clock signals that are phase-inverted with respect to one another. If a charge exchange switch is present, it can be controlled by a third clock signal different from the first and second clock signals. 
         [0013]    In some instances, the readout circuit includes an output circuit coupled to the sense nodes and having a capacitance, each one of the demodulation pixel cells further being operable to alternate, from one integration period to the next, a phase of signals applied to the demodulation gates, and operable to change a polarity of connections for the capacitance. 
         [0014]    Other aspects, features and advantages will be readily apparent from the following detailed description, the accompanying drawings, and the claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    FIG. illustrates an example of a pinned photodiode pixel. 
           [0016]      FIGS. 2A and 2B  illustrate a simplified schematic of a PPD pixel including background light suppression. 
           [0017]      FIG. 3  illustrates further details of a pixel background light suppression and readout circuit. 
           [0018]      FIG. 4  is an example of a timing diagram for the circuit of  FIG. 3 . 
           [0019]      FIG. 5  illustrates a cross-coupled chopping current mirror configuration. 
           [0020]      FIG. 6  illustrates another cross-coupled chopping current mirror configuration. 
           [0021]      FIG. 7  is a timing diagram for the circuits of  FIGS. 5 and 6 . 
           [0022]      FIG. 8  illustrates a cross-coupled chopping current mirror configuration with charge exchange. 
           [0023]      FIG. 9  is a timing diagram for the circuit of  FIG. 8 . 
           [0024]      FIG. 10  illustrates another cross-coupled chopping current mirror configuration. 
           [0025]      FIG. 11  illustrates the cross-coupled chopping current mirror configuration of  FIG. 10  with charge exchange. 
           [0026]      FIG. 12  is a timing diagram for the circuit of  FIG. 11 . 
           [0027]      FIG. 13  illustrates another current mirror configuration. 
           [0028]      FIG. 14  is a timing diagram for the circuit of  FIG. 13 . 
           [0029]      FIG. 15  is a block diagram of a three-dimensional camera system based on a sensor that includes an array of demodulation pixels. 
       
    
    
     DETAILED DESCRIPTION 
       [0030]    The present disclosure describes various techniques and circuits for providing background light suppression for a PPD pixel. The background light may include, for example, ambient light, sunlight and/or other unmodulated light. 
         [0031]      FIGS. 2A and 2B  illustrate a simplified schematic of a PPD demodulation pixel  20  of a focal plane array of many such cells formed in an integrated circuit. As illustrated in the example PPD pixel of  FIGS. 2A and 2B , toggle gates (i.e., switches)  26 ,  28  are provided to demodulate signals from the PPD. Control signals TG 0 , TG 18  are applied to the demodulation gates  26 ,  28  such that the charge from the PPD is stored, respectively, in a first sense node diode FD 0  during a first (e.g., 0°) demodulation phase, and in a second sense node diode FD 18  during a second (e.g., 180°) demodulation phase. A single input clock signal, for example, can be used to generate the complementary toggle gate driving signals. Each of the sense node diodes FD 0  and FD 18  can be implemented, for example, as a floating diffusion region in a semiconductor substrate and serves as a sense node for the PPD pixel. The sense nodes can be coupled to output circuitry implemented, for example, as NMOS source follower field-effect transistors (FETs) having a capacitance shown in  FIGS. 2A and 2B  as Cbg (e.g., implemented as a metal stack capacitor). The source follower FETs, in turn, can be is connected to readout circuitry. 
         [0032]    As further shown in  FIGS. 2A and 2B , a pair of cross-coupled current mirrors  30 ,  32  provides background light suppression based on direct common mode compensation in the current domain. In the illustrated example, each of the current mirrors  30 ,  32  is composed of two PMOS transistors respectively (i.e., M 1  and M 2  for current mirror  30 , and M 3  and M 4  for current mirror  32 ). The cross-coupled current mirrors  30 ,  32  are coupled to the capacitance Cgbs of the output circuit and to the sense node diodes FD 0 , FD 18 . Current that is generated as a result of background light is split substantially evenly between the current mirrors  30 ,  32 , which compensate for the background current such that only the differential signal current appears across the output capacitance Cbgs. Thus, as indicated by  FIG. 2A , if the signal-generated currents of the 0° and 180° phases are identical, the circuit remains in a balanced condition with the differential current equal to zero. On the other hand, as indicated by  FIG. 2B , if the currents of the 0° and 180° phases differ, the circuit is in an unbalanced state, and the current difference is integrated across the capacitance Cbgs. In either case, the current mirrors  30 ,  32  compensate for the common mode current resulting from the background light. 
         [0033]      FIG. 3  illustrates further details of a pixel background light suppression and readout circuit, including readout circuitry and reset circuitry. For ease of illustration, the demodulation gates  26 ,  28 , as well as dump gates, are not shown in  FIG. 3 . Output and readout circuitry  36  coupled to the sense node FD 0  (or FD 18 ) includes, for example, an output circuit implemented as a source follower field-effect transistor (FET) M 5  (or M 7 ). Each sense node FD 0  (or FD 18 ) is connected to the gate of the source follower FET M 5  (or M 7 ), whose drain is connected to a main supply voltage (VD_SF). The source follower FET M 5  (or M 7 ) is connected to a row-select switch M 6  (or M 8 ) controlled by a signal (SEL) applied to its gate. The row-select switches M 6  and M 8  form part of the pixel&#39;s readout circuit. Although not shown in  FIG. 3 , each row-select switch M 6  (or M 8 ), in turn, can be coupled, for example, to a column-select switch and a correlated double sampling (CDS) amplifier operable to provide a correlated double sampling of the potential of the sense nodes FD 0 , FD 18 . The outputs in  FIG. 3  are indicated, respectively, by TAP 0 _OUT and TAP 18 _OUT. During readout, signals are applied to CCD gates (TG_DUMP) associated with dump diffusion diodes D 1 , D 2 . The CCD gates transfer charge from the PPD region  14  to the main power supply (VD_SF) net during readout (i.e., while the TG 0  and TG 18  gates are off). 
         [0034]    As further shown in  FIG. 3 , a reset circuit  38  includes reset switches M 9 , M 10  and a current sink transistor M 11 . In operation, the background current suppression circuit should be balanced prior to a subsequent integration cycle. The reset switches M 9 , M 10  and current sink transistor M 11  serve this purpose. The reset switches M 9 , M 10  equalize the potential across the capacitance Cbgs and pass some initial bias current, which provides some initial common mode voltage across the current mirror transistors M 2  and M 4  and places them into forward conduction. The reset switches M 9 , M 10  are controlled by a signal (RST) applied to their gates. Likewise, the current sink transistor M 11  has a bias voltage signal (VBIASN) applied to its gate. This bias voltage defines the reset current. The various switches in  FIG. 3  can be implemented, for example, as FETs. 
         [0035]    In the illustrated example, the power supply (VD_NWELL) of the n-well for the current mirror transistors M 1 , M 2 , M 3 , M 4  is separate from the main power supply (VD_SF). This feature allows the swing in the differential voltage to increase by applying a higher N-well potential so as to modulate the PMOS device threshold voltage. An alternative technique for increasing the differential is to provide an additional PMOS diode in series with the current mirrors  30 ,  32 . Such an approach, however, tends to increases the overall layout size of the circuit and has less in swing adjustment. 
         [0036]      FIG. 4  is a timing diagram showing examples of the input signals RST, TG 0 , TG 18 , TG_DUMP and SEL, as well as signals at the sense nodes FD 0 , FD 18  and the output signals TAP 0 _OUT, TAP 18 _OUT, during pixel reset, pixel integration and pixel readout. 
         [0037]    In some cases, as a result of an imperfect integrated circuit manufacturing process, a deviation between the real output current at the output nodes and the originally desired current may occur. Nevertheless, background light suppression can be improved even in the presence of such imperfect mirror current matching by applying time domain current mirror chopping. 
         [0038]    For example, as shown in  FIG. 5 , a cross-coupled chopping current mirror configuration can be provided by the addition of switches M 20  through M 23 . By using a first clock signal Clka and a second clock signal Clkb, the transmission-gates of the circuit are controlled to be turned on or off. In particular, the first clock signal Clka and the second clock signal Clkb are phase-inverted with respect to one another. Thus, when the first clock signal Clka takes a logic-high level, the second clock signal Clkb takes a logic-low level. Likewise, when the first clock signal Clka takes a logic-low level, the second clock signal Clkb takes a logic-high level. The cross-coupled chopping current mirror thus is operable to average the currents of the channels. 
         [0039]    Instead of applying the time domain chopping to the drains of the current mirror switches M 1 -M 4  as in  FIG. 5 , time domain chopping can be applied to their respective gates by the using switches M 24 -M 27 , as shown in the configuration of  FIG. 6 . Here too, the first clock signal Clka and the second clock signal Clkb are phase-inverted with respect to one another such that when the first clock signal Clka takes a logic-high level, the second clock signal Clkb takes a logic-low level, and vice-versa. In this case, however, DC current does not flow through the switches M 24 -M 27 . 
         [0040]      FIG. 7  is a timing diagram for the chopping circuit clock signals Clka, Clkb of  FIGS. 5 and 6 , as well as the signals applied to the demodulation gates  26 ,  28 , during pixel integration and chopping. 
         [0041]    The foregoing approaches may cause charge loss as the gates of the mirror transistors M 1 -M 4  are switched from one floating diffusion (i.e., sensing) node to another. Such charge loss can cause undesirable signal saturation at low currents. To alleviate such situations, a charge exchange switch M 28 , implemented for example as a FET transistor, can be coupled to the gates of the current mirror switches M 1 -M 4  as show in  FIG. 8 . A third clock signal Clkc is applied to the gate of the charge exchange switch M 28  such that the charge exchange switch M 28  is open during chopping.  FIG. 9  is a timing diagram showing an example of the clock signals Clka, Clkb, Clkc, as well as the signals TG 0 , TG 18  applied to the demodulation gates  26 ,  28 , during pixel integration and chopping for the configuration of  FIG. 8 . 
         [0042]    In some instances, it may be desirable to combine the configurations of  FIGS. 5 and 6  so as to fully preserve the gate charges during chopping. Such a configuration is illustrated in  FIG. 10 , and allows time domain chopping to be applied to both the drains and gates of the current mirror switches M 1 -M 4 . In this case, the same two clock signal (Clka or Clkb) is applied to the drain and gate of each respective switch M 1 -M 4 . The timing diagram of  FIG. 7  is applicable to this scenario as well. 
         [0043]    In the foregoing examples, time domain chopping is applied to the drains and/or gates of the current mirror switches M 1 -M 4 . As shown in  FIG. 11 , in some implementations, however, a different approach includes alternating the phase of the signals TG 0 , TG 18  applied to the demodulation gates  26 ,  28  (e.g., switching the phase between 0° and 180°) from one pixel integration to the next and providing switches M 30 -M 33  to change the polarity of the pins of the capacitance Cbgs. Thus, during a first pixel integration period, the capacitor pins have a first polarity and the phase of the signals applied to the demodulation gates is 0°. During the next, subsequent pixel integration period, the capacitor pins have a second, opposite polarity and the phase of the signals applied to the demodulation gates is 180°. This alternating sequence continues for subsequent pixel integration periods.  FIG. 12  illustrates a timing diagram for such an implementation. 
         [0044]    The configuration of  FIGS. 11 and 12  can compensate for mismatch in the current mirrors  30 ,  32  as well as for asymmetries in the pixel sensitive area. Unfortunately, the charge placed on the gates of the current mirror switches M 1 -M 4  and on the floating diffusion regions FD 0 , FD 18  will be lost, which can result in high signal attenuation and saturation for low signals levels. To alleviate these issues, a charge exchange switch M 35  can be added as shown in  FIG. 13 . A third clock signal Clkc is applied to the gate of the charge exchange switch M 35 .  FIG. 14  is a timing diagram for such a configuration. 
         [0045]    The electronic noise level can be limited, in some instances, by shortening the pixel integration time. 
         [0046]    A pixel including any of the foregoing background light suppression and readout circuits can be included in a focal plane array of many such pixels formed in an integrated circuit.  FIG. 15  illustrates the basic principle of a 3D-measurement camera system based on a sensor  200  comprising an array of demodulation pixels  202  each of which can be similar to one of demodulation pixels described above. The camera system can be used advantageously, for example, in time-of-flight (TOF) and other applications. 
         [0047]    Modulated illumination light ML 1  from an illumination module or light source IM is sent to the object OB of a scene. In some instances, the light source generates modulated infra-red (IR) radiation. A fraction of the total optical power sent out is reflected to the camera  10  and detected by the 3D imaging sensor  200 . The sensor  200  comprises a two dimensional pixel matrix of the demodulation pixels  202 . Each pixel  202  is capable of demodulating the impinging light signal ML 2  using known techniques. A control board CB is operable to regulate the timing of the camera  204 . The phase values of all pixels correspond to the particular distance information of the corresponding point in the scene. The two-dimension gray scale image with the distance information is converted into a three-dimensional (e.g., depth) image by image processor IP. The image can be displayed to a user, for example, via display D or used as a machine vision input. 
         [0048]    The distance R for each pixel can be calculated by R=(c·TOF)/2, with ‘c’ as light velocity and TOF corresponding to the time-of-flight. Either pulse intensity-modulated or continuously intensity-modulated light is sent out by the illumination module or light source IM, reflected by the object and detected by the sensor. With each pixel  202  of the sensor  200  being capable of demodulating the optical signal at the same time, the sensor is able to deliver 3D images in real-time, i.e., frame rates of up to 30 Hertz (Hz), or even more, are possible. In pulse operation, the demodulation would deliver the time-of-flight directly. However, continuous sine modulation delivers the phase delay (P) between the emitted signal and the received signal, also corresponding directly to the distance R=(P·c)/(4·pi·fmod), where fmod is the modulation frequency of the optical signal. Typical state-of-the-art modulation frequencies range from a few MHz up to a few hundreds of MHz or even GHz. 
         [0049]    Various modifications can be made within the spirit of the foregoing disclosure. Accordingly, other implementations are within the scope of the claims.