Abstract:
The present invention provides a semiconductor structure and a method of fabricating the same. The semiconductor structure includes a carrier, a semiconductor chip and an encapsulant. The semiconductor chip is disposed on the carrier, and has opposing non-active and active surfaces. The non-active surface is coupled to the carrier, and the active surface has a plurality of metallic pillars formed thereon. A under bump metallogy layer is formed between the metallic pillars and the active surface and on side surfaces of the metal pillars. The surface of the encapsulant is flush with end surfaces of the metallic pillars. Therefore, the product yield is increased significantly.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to semiconductor structures and methods of fabricating the same, and, more particularly, to a semiconductor structure including a semiconductor chip having metallic pillars formed thereon, and a method of fabricating the semiconductor structure. 
         [0003]    2. Description of Related Art 
         [0004]    With the rapid growth in electronic industry, there is an increasing need in developing electronic products with multi-functionality and high performance and miniaturization, thereby facilitating the development of several different types of packaging technologies. 
         [0005]      FIGS. 1A-1G  are cross-sectional views illustrating a method of fabricating a conventional package structure. 
         [0006]    As shown in  FIG. 1A , a semiconductor chip  10  is provided. The semiconductor chip  10  has opposing active and non-active surfaces  10   a  and  10   b . A plurality of electrode pads  101  are formed on the active surface  10   a . A passivation layer  11  having a plurality of passivation layer holes  110  is formed on the active surface  10   a  and the electrode pads  101 , with the electrode pads  101  exposed from the corresponding passivation layer holes  110 . A titanium layer  121  and a copper layer  122  of the under bump metallogy layer (UBM)  12  are sequentially formed on the passivation layer  11  and the electrode pads  101 . A resist layer  13  having a plurality of resist layer holes  130  is formed on the copper layer  122 , with the resist layer holes  130  corresponding in position to the passivation layer holes  110  and the periphery thereof. 
         [0007]    As shown in  FIG. 1B , copper bumps  14  are formed in the resist layer holes  130  by an electroplating method. 
         [0008]    As shown in  FIG. 1C , the resist layer  13  and the titanium layer  121  and the copper layer  122  covered by the resist layer  13  are removed. 
         [0009]    As shown in  FIG. 1D , through an adhesive layer  15 , the non-active surface  10   b  of the semiconductor chip  10  is mounted to a bottom surface of a groove  160  of the carrier  16 . 
         [0010]    As shown in  FIG. 1E , an encapsulant  17  is formed on the carrier  16  and encapsulates the semiconductor chip  10  and the copper bumps  14 . 
         [0011]    As shown in  FIG. 1F , a plurality of encapsulant holes  170  are formed, with the copper bumps  14  exposed from the corresponding encapsulant holes  170 . 
         [0012]    As shown in  FIG. 1G , conductive vias  18  are formed on the copper bumps  14  in the encapsulant holes  170 . A redistribution layer (not shown) is formed on the encapsulant  17  and the conductive vias  18  and electrically connected with the semiconductor chip  10 . 
         [0013]    However, the copper bumps, since formed in the resist layer holes  130  by an electroplating process, are not at the same level, and the copper bumps formed in the resist layer holes subsequently suffer from poor contact problem. Besides, an alignment problem occurs when the encapsulant holes that correspond to the copper bumps are formed. As a result, the copper bumps have poor electrical connection quality, and the product yield is thus reduced. 
         [0014]    Accordingly, there is an urgent need to solve the above-mentioned problems of the prior art. 
       SUMMARY OF THE INVENTION 
       [0015]    In view of the foregoing objectives, the present invention provides a semiconductor package, comprising: a semiconductor chip having a non-active surface and an active surface opposing the non-active surface; a plurality of metallic pillars formed on the active surface; and an under bump metallogy layer formed between the metallic pillars and the active surface and on side surfaces of the metallic pillars. 
         [0016]    The present invention further provides a method of fabricating a semiconductor structure, comprising: disposing on a carrier a semiconductor chip having opposing active and non-active surfaces, with the non-active surface being coupled to the carrier, wherein a plurality of metallic pillars are formed on the active surface, and an under bump metallogy layer is formed between the metallic pillars and the active surface and on side surfaces of the metallic pillars; and forming on the carrier an encapsulant that encapsulates the semiconductor chip and has a surface flush with end surfaces of the metallic pillars. 
         [0017]    The present invention further provides a method of fabricating a semiconductor structure, comprising: forming a dielectric layer having a plurality of holes on an active surface of a semiconductor chip, with a portion of the active surface exposed from the holes; forming an under bump metallogy layer on the dielectric layer, the walls of the holes, and the portion of the active surface exposed from the holes; forming a metal layer on the under bump metallogy layer; and removing a portion of the metal layer and the under bump metallogy layer that is higher than the dielectric layer, and forming a plurality of metallic pillars on the portion of the active surface exposed from the holes. 
         [0018]    In summary, the present invention is characterized by forming a dielectric layer exposing the electrode pads, followed by forming an under bump metallogy layer and a metal layer, and then removing parts of the thickness of the under bump metallogy layer and metal layer, so as to solve the unevenness of conventional metallic pillars; Moreover, an encapsulant is formed to encapsulate the semiconductor chip and the metallic pillars after the semiconductor chip is coupled to the carrier, of which the encapsulant and metallic pillars are subsequently grinded to expose the metallic pillars. As a result, the conventional method of forming encapsulant holes is not required to expose the metallic pillars, thereby solving the conventional problems in the prior art such as alignment deviation, and uneven thickness of the semiconductor chip and the adhesive layer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]      FIGS. 1A-1G  are cross-sectional views illustrating a method of fabricating a conventional package structure; 
           [0020]      FIGS. 2A-2I  are cross-sectional views illustrating a method of fabricating a semiconductor structure of a first embodiment according to the present invention; and 
           [0021]      FIGS. 3A-3D  are cross-sectional views illustrating a method of fabricating a semiconductor structure of a second embodiment according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0022]    The present invention is described in the following with specific embodiments, so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention from the disclosure of the present invention. 
         [0023]    It should be noted that all the drawings are not intended to limit the present invention. Various modification and variations can be made without departing from the spirit of the present invention. Further, terms used in the present invention are merely for illustrative purpose and should not be construed to limit the scope of the present invention. 
         [0024]      FIGS. 2A-2I  are cross-sectional views illustrating a method of fabricating a semiconductor structure of a first embodiment according to the present invention. 
         [0025]    As shown in  FIG. 2A , a semiconductor chip  20  having opposing active and non-active surfaces  20   a  and  20   b  is provided. A plurality of electrode pads  201  are formed on the active surface  20   a  of the semiconductor chip  20 . A passivation layer  21  having a plurality of passivation layer holes  210  is formed on the electrode pads  201  and on the active surface  20   a . The passivation layer holes  210  correspond in position to the exposed electrode pads  201 . A dielectric layer  22  having a plurality of holes  220  is formed on the passivation layer  21 , with the electrode pads  201  exposed from the corresponding holes  220 . The dielectric layer  22  can be formed by a photosensitive insulating material or a resist material. 
         [0026]    As shown in  FIG. 2B , a titanium sub-layer  231  and a copper sub-layer  232  that serve as a under bump metallogy layer  23  are sequentially formed on the dielectric layer  22 , the walls of the holes  220 , and the electrode pads  201  exposed from the holes  220 . 
         [0027]    As shown in  FIG. 2C , a metal layer  24  is formed on the copper layer  232 . In an embodiment, the metal layer  24  is made of copper. 
         [0028]    As shown in  FIG. 2D , a portion of the metal layer  24  that is higher than the dielectric layer  22  and the under bump metallogy layer  23  is grinded and removed, while the metallic pillars  24 ′ on the electrode pads  201  are retained. A under bump metallogy layer  23  is formed between the metallic pillars  24 ′ and the active surface  20   a  and on the side surfaces of the metallic pillars  24 ′. The dielectric layer  22  encapsulates the metallic pillars  24 ′ and the under bump metallogy layer  23 , and is flush with the end surfaces of the metallic pillars  24 ′. The dielectric layer  22  can be removed according to practical needs (not shown). As shown in  FIG. 2E , an adhesive layer  25  is used to adhere the semiconductor chip  20  to the bottom surface of the groove  260  of the carrier  26  via the non-active surface  20   b  of the semiconductor chip  20 . In an embodiment, the carrier  26  does not have the groove  260 . The carrier  26  can be a wafer, a glass board or a metal board. 
         [0029]    In an embodiment, a wafer having a plurality of semiconductor chips is provided. The wafer is singulated by a singulation process after the fabrication processes described in  2 A- 2 D, to form a plurality of semiconductor chips  20 , as shown in  FIG. 2E . The semiconductor chips  20  are attached to the carrier  26 , for the subsequent processes to be performed. 
         [0030]    As shown in  FIG. 2F , an encapsulant  27  is formed on the carrier  26  and encapsulates the semiconductor chip  20  and the metallic pillars  24 ′. In an embodiment, the encapsulant  27  is further formed in the groove  260 . 
         [0031]    As shown in  FIG. 2G , a grinding process is performed to remove a portion of the thickness of the encapsulant  27  and the metallic pillars  24 ′, as well as a portion of the thickness of the carrier  26  and the dielectric layer  22  according to practical needs, allowing the surface of the encapsulant  27  to be flush with the end surfaces of the metallic pillars  24 ′. 
         [0032]    As shown in  FIG. 2H , a redistribution layer  28  is formed on the encapsulant  27  and the metallic pillars  24 ′ and electrically connected with the semiconductor chip  20 . An insulative protecting layer  29  is formed on the redistribution layer  28 , and a portion of the redistribution layer  28  is exposed from the insulative protecting layer  29 . 
         [0033]    As shown in  FIG. 2I , a plurality of solder balls  30  are formed on the redistribution layer  28 . 
         [0034]      FIGS. 3A-3D  are cross-sectional views illustrating a method of fabricating a semiconductor structure of a second embodiment according to the present invention. The second embodiment differs from the first embodiment in that in the second embodiment the thickness of the semiconductor chips  20  or the thickness of the adhesive layer  25  on the non-active surface  20   b  are different from those in the first embodiment. In the second embodiment, the semiconductor chip  20  and the metallic pillars  24 ′ are positioned at different heights. However, the implementation is not influenced by this difference. 
         [0035]    The present invention provides a semiconductor structure comprising a carrier  26 , a semiconductor chip  20 , and an encapsulant  27 . The semiconductor chip  20  is formed on the carrier  26 , and has a non-active surface  20   b  coupled with the carrier  26  and an active surface  20   a  opposing the non-active surface  20   b . A plurality of metallic pillars  24 ′ are formed on the active surface  20   a . An under bump metallogy layer  23  is formed between the metallic pillars  24 ′ and the active surface  20   a  and on the side surfaces of the metallic pillars  24 ′. The encapsulant  27  is formed on the carrier  26  and encapsulates the semiconductor chip  20 . The surface of the encapsulant  27  is flush with the end surfaces of the metallic pillars  24 ′. 
         [0036]    In an embodiment, a dielectric layer  22  is formed on the active surface  20   a  of the semiconductor chip  20 , encapsulates the metallic pillars  24 ′ and the under bump metallogy layer  23 , and is flush with the end surfaces of the metallic pillars  24 ′. The dielectric layer  22  is made of a photosensitive insulating material or a resist material. 
         [0037]    In an embodiment, the carrier  26  further comprises a groove  260 , the semiconductor chip  20  is mounted on the bottom surface of the groove  260  and received in the groove  260 , and the encapsulant  27  is formed in the grooves  260 . 
         [0038]    In an embodiment, the under bump metallogy layer  23  comprises a titanium sub-layer  231  and a copper sub-layer  232  formed between the metallic pillars  24 ′ and the titanium sub-layer  231 . The packaging structure further comprises a redistribution layer  28  formed on the encapsulant  27  and the metallic pillars  24 ′ and electrically connected with the semiconductor chip  20 . 
         [0039]    Compared to the prior art, the present invention is characterized by forming a dielectric layer exposing the electrode pads, forming an under bump metallogy layer and a metal layer, and removing a portion of the under bump metallogy layer and the metal layer, so as to solve the unevenness of conventional metallic pillars. Moreover, an encapsulant is formed to encapsulate the semiconductor chip and the metallic pillars after the semiconductor chip is coupled to the carrier, and the encapsulant and the metallic pillars are subsequently grinded to expose the metallic pillars. As a result, the conventional method of forming encapsulant holes are not required, thereby solving the conventional problems in the prior art such as alignment deviation, and uneven thickness of the semiconductor chip and the adhesive layer. 
         [0040]    The present invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.