Abstract:
Multiplying digital-to-analog converters (MDACs), which are generally employed in pipelined analog-to-digital converters (ADCs), can have a settling error associated with the MDAC amplifier. Here, a circuit is provided that includes additional amplifiers and a capacitor network that compensates for this settling error. Thus, a more accurate pipelined ADC can now be produced.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority from Indian Application No. 2639/CHE/2009, filed Oct. 30, 2009, which is hereby incorporated by reference for all purposes 
       TECHNICAL FIELD 
       [0002]    The invention relates generally to an amplifier and, more particularly, to correcting for settling error in an amplifier employed in a multiplying digital-to-analog converter (MDAC) of a pipelined analog-to-digital converter (ADC). 
       BACKGROUND 
       [0003]    Multiplying digital-to-analog converters (MDACs) are commonly used in pipelined analog-to-digital converters (ADCs). MDACs in this application generally employ switched capacitive networks and an MDAC amplifier. Turning to  FIG. 1  of the drawings, a simplified, conventional MDAC amplifier with its associated capacitors can be seen. Here, an input signal VIN is applied to sampling capacitor CS (which is coupled to the inverting terminal of MDAC amplifier  102 ). Additionally, feedback capacitor CF is coupled between the output terminal of amplifier  102  and the inverting terminal of amplifier  102 . Assuming that amplifier  102  has a good phase margin, its output would settle like a single pole system as follows: 
         [0000]    
       
         
           
             
               
                 
                   VOUT 
                   = 
                   
                     VIN 
                     * 
                     
                       CS 
                       CF 
                     
                     * 
                     
                       ( 
                       
                         1 
                         - 
                         
                            
                           
                             
                               - 
                               t 
                             
                             τ 
                           
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Of interest, however, is the output voltage VOUT at setting time of the amplifier  102   
         [0000]    
       
         
           
             
               ( 
               
                 t 
                 ≈ 
                 
                   
                     T 
                     s 
                   
                   3 
                 
               
               ) 
             
             , 
           
         
       
     
         [0000]    where T S  is the clock or sample period of the ADC, so that equation (1) becomes: 
         [0000]    
       
         
           
             
               
                 
                   VOUT 
                   = 
                   
                     VIN 
                     * 
                     
                       CS 
                       CF 
                     
                     * 
                     
                       
                         ( 
                         
                           1 
                           - 
                           
                              
                             
                               
                                 - 
                                 
                                   T 
                                   s 
                                 
                               
                               
                                 3 
                                  
                                 τ 
                               
                             
                           
                         
                         ) 
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0000]    This results in an error of: 
         [0000]    
       
         
           
             
               
                 
                   e 
                   = 
                   
                     VIN 
                     * 
                     
                       CS 
                       CF 
                     
                     * 
                     
                       
                          
                         
                           
                             - 
                             
                               T 
                               s 
                             
                           
                           
                             3 
                              
                             τ 
                           
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Thus, it can clearly be seen that this error shown in equation (3) increase exponentially with the decrease in the period of the ADC clock T S . Therefore, there is a need to address this error. 
         [0004]    Some other conventional circuits are: U.S. Pat. No. 6,323,800; U.S. Pat. No. 6,573,791; U.S. Pat. No. 7,230,483; U.S. Pat. No. 7,397,409; U.S. Patent Pre-Grant Publ. No. 2006/0197593; and U.S. Patent Pre-Grant Publ. No. 2009/0146854. 
       SUMMARY 
       [0005]    A preferred embodiment of the present invention, accordingly, provides an apparatus. The apparatus comprises a sampling capacitor that receives an input signal; a multiplying digital-to-analog converter (MDAC) amplifier having an input terminal and an output terminal, wherein the sampling capacitor is coupled to the input terminal of the MDAC amplifier; a feedback capacitor that is coupled between the input terminal of MDAC amplifier and the output terminal of the MDAC amplifier; a correction amplifier having an input terminal and an output terminal, wherein the input terminal is coupled to correction amplifier is coupled to the output terminal of the MDAC amplifier, wherein the correction amplifier at least applies a settling gain to an output signal from the MDAC amplifier; and a correction capacitor that is coupled between the output terminal of the correction amplifier and the input terminal of the MDAC amplifier, wherein the capacitance of the correction amplifier is a fraction of the capacitance of the feedback capacitor. 
         [0006]    In accordance with a preferred embodiment of the present invention, the correction amplifier further comprises an attenuating amplifier that attenuates the output signal from the MDAC amplifier; and a settling amplifier that applied the settling gain to the output signal from the MDAC. 
         [0007]    In accordance with a preferred embodiment of the present invention, the setting gain is negative. 
         [0008]    In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a first set of stage coupled in series with one another that receives an analog input signal, wherein the stage from the first set of stages includes: a first analog-to-digital converter (ADC); and an MDAC having: a sampling capacitor that is coupled to the first ADC; a MDAC amplifier having an input terminal and an output terminal, wherein the sampling capacitor is coupled to the input terminal of the MDAC amplifier; a feedback capacitor that is coupled between the input terminal of MDAC amplifier and the output terminal of the MDAC amplifier; a correction amplifier having an input terminal and an output terminal, wherein the input terminal is coupled to correction amplifier is coupled to the output terminal of the MDAC amplifier, wherein the correction amplifier at least applies a settling gain to an output signal from the MDAC amplifier; and a correction capacitor that is coupled between the output terminal of the correction amplifier and the input terminal of the MDAC amplifier, wherein the capacitance of the correction amplifier is a fraction of the capacitance of the feedback capacitor; a final stage that is coupled to at least one of the stages from the first set of stages, wherein the final stage includes a second ADC; and output circuitry is coupled to each of the first ADCs and to the second ADC, wherein the output circuitry outputs a digital signal. 
         [0009]    In accordance with a preferred embodiment of the present invention, each stage from the first set of stages further comprises: a track-and-hold (T/H) amplifier that is coupled to the first ADC; an adder that is coupled to the T/H amplifier and to the MDAC; and a residue amplifier that is coupled to the adder. 
         [0010]    The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
           [0012]      FIG. 1  is an example of a conventional multiplying digital-to-analog converter (MDAC) amplifier and its associated capacitors; 
           [0013]      FIG. 2  is an example of a pipeline analog-to-digital converter (ADC) in accordance with a preferred embodiment of the present invention; and 
           [0014]      FIGS. 3 and 4  are examples of at least a portion of the MDACs of  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. 
         [0016]    Referring to  FIG. 2  of the drawings, the reference numeral  200  generally designates a pipelined analog-to-digital converter (ADC) in accordance with a preferred embodiment of the present invention. ADC  200  generally comprises a first set of stage  202 - 1  to  202 -(M−1), a final or second stage  202 -M, and output circuitry  204 . Each of the stages  202 - 1  to  202 -(M−1) is (respectively) generally comprised of a track-and-hold (T/H) amplifier  206 - 1  to  206 -(M−1), a flash ADC  208 - 1  to  208 -(M−1), an MDAC  210 - 1  to  210 -(M−1), an adder  212 - 1  to  212 -(M−1), and a residue amplifier  214 - 1  to  214 -(M−1). The final or second stage  202 -M is generally comprised of T/H amplifier  206 -M and flash ADC  208 -M. Additionally, output circuitry  204  is coupled to each of the ADCs  208 - 1  to  208 -M to generate a digital output signal DOUT. 
         [0017]    In operation, the ADC  200  uses the stages  202 - 1  to  202 -M and output circuit  204  to convert the analog input signal AIN to the digital output signal DOUT. Preferably, the first stage  202 - 1  receives the analog input signal AIN at its T/H amplifier  206 - 1 , where the signal AIN is sampled or tracked during a track phase and held for conversion during a hold phase. During conversion, flash ADC  208 - 1  performs a conversion on the sampled signal from T/H amplifier  206 - 1  and provides a digital signal to the output circuitry  204  and MDAC  210 - 1 . MDAC  210 - 1  converts converted signal from ADC  208 - 1  back to an analog signal so that it can be subtracted from the sampled signal from T/H amplifier  206 - 1  to generate a residue signal. The residue signal is amplified by residue amplifier  214 - 1 , so that it can be provided to the next stage  202 - 2 . This process is repeated over the stages  202 - 2  to  202 -(M−1), and in stage  202 -M, the output from residue amplifier  214 -(M−1) is sampled by T/H amplifier  206 -M, which is converted to a digital signal by ADC  208 -M and provided to output circuit  204 . 
         [0018]    Of interest, however, are the MDACs  210 - 1  to  210 -(M−1), an example of a portion which can be seen in  FIG. 3 . Here, a portion of MDAC  210  (which is generally the same as MDACs  210 - 1  to  210 -(M−1)) is shown including sampling capacitor CS, feedback capacitor CF, MDAC amplifier  102 , a correction amplifier, and correction capacitor CC. The correction amplifier is generally comprised of an attenuating amplifier  302  (which can be a capacitive divider) with a gain K and a setting amplifier  304  with a gain of −GS. Additionally, correction capacitor CC has a capacitance that is a fraction of the capacitance of the feedback capacitor CF (CC=a*CF, where a&lt;&lt;1). As a result of this configuration, the output voltage VOUT from MDAC amplifier  102  is: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         VOUT 
                         = 
                           
                          
                         
                           VIN 
                           * 
                           
                             CS 
                             
                               CF 
                               * 
                               
                                 ( 
                                 
                                   1 
                                   - 
                                   
                                     a 
                                     * 
                                     k 
                                     * 
                                     GS 
                                   
                                 
                                 ) 
                               
                             
                           
                           * 
                           
                             ( 
                             
                               1 
                               - 
                               
                                  
                                 
                                   
                                     - 
                                     
                                       T 
                                       S 
                                     
                                   
                                   
                                     3 
                                      
                                     τ 
                                   
                                 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           VIN 
                           * 
                           
                             
                               CS 
                               * 
                               
                                 ( 
                                 
                                   1 
                                   + 
                                   
                                     a 
                                     * 
                                     k 
                                     * 
                                     GS 
                                   
                                 
                                 ) 
                               
                             
                             
                               CF 
                               * 
                               
                                 ( 
                                 
                                   1 
                                   - 
                                   
                                     
                                       ( 
                                       
                                         a 
                                         * 
                                         k 
                                         * 
                                         GS 
                                       
                                       ) 
                                     
                                     2 
                                   
                                 
                                 ) 
                               
                             
                           
                           * 
                           
                             ( 
                             
                               1 
                               - 
                               
                                  
                                 
                                   
                                     - 
                                     
                                       T 
                                       S 
                                     
                                   
                                   
                                     3 
                                      
                                     τ 
                                   
                                 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                   
                     
                       
                         ≈ 
                           
                          
                         
                           VIN 
                           * 
                           
                             CS 
                             CF 
                           
                           * 
                           
                             ( 
                             
                               1 
                               - 
                               
                                  
                                 
                                   
                                     - 
                                     
                                       T 
                                       S 
                                     
                                   
                                   
                                     3 
                                      
                                     τ 
                                   
                                 
                               
                             
                             ) 
                           
                           * 
                           
                             ( 
                             
                               1 
                               + 
                               
                                 a 
                                 * 
                                 k 
                                 * 
                                 GS 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                   
                     
                       
                         ≈ 
                           
                          
                         
                           VIN 
                           * 
                           
                             CS 
                             CF 
                           
                           * 
                           
                             ( 
                             
                               1 
                               - 
                               
                                  
                                 
                                   
                                     - 
                                     
                                       T 
                                       S 
                                     
                                   
                                   
                                     3 
                                      
                                     τ 
                                   
                                 
                               
                               + 
                               
                                 a 
                                 * 
                                 k 
                                 * 
                                 GS 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
       Thus, if: 
       [0019]    
       
         
           
             
               
                 
                   
                     
                        
                       
                         
                           - 
                           
                             T 
                             S 
                           
                         
                         
                           3 
                            
                           τ 
                         
                       
                     
                     = 
                     
                       a 
                       * 
                       k 
                       * 
                       GS 
                     
                   
                    
                   
                       
                   
                    
                   
                     
 
                   
                    
                   
                     then 
                     , 
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
             
               
                 
                   
                     VOUT 
                     ≈ 
                     
                       VIN 
                       * 
                       
                         CS 
                         CF 
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0000]    so that the error of equation (3) can be compensated for. 
         [0020]    Typically, with ADCs (such as ADC  200 ), a speed dependent current I TS  is available, which increases generally linearly with a decreasing sampling period T S . Preferably, the speed dependent current is: 
         [0000]        I   TS   =I   c *(1− n*T   S ),
 
         [0000]    where I C  is a generally constant current. Realizing that when the same types of transistors are used for both the input and load, then the gain −GS of the settling amplifier  304  is: 
         [0000]    
       
         
           
             
               
                 
                   
                     - 
                     GS 
                   
                   = 
                   
                     
                       
                         - 
                         
                           gm 
                           IN 
                         
                       
                       
                         gm 
                         LOAD 
                       
                     
                     = 
                     
                       
                         - 
                         
                           
                             I 
                             IN 
                           
                         
                       
                       
                         
                           I 
                           LOAD 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0000]    So, if the input current I IN  and load current I LOAD  are: 
         [0000]        I   IN   =I   0   +m*I   TS   (9)
 
         [0000]        I   LOAD   =I   0   −m*I   TS ,  (10)
 
         [0000]    (where I 0  is a generally constant current and m is a multiplying factor), then equation (8) becomes: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         GS 
                         = 
                         
                           
                             
                               
                                 I 
                                 0 
                               
                               + 
                               
                                 m 
                                 * 
                                 
                                   I 
                                   TS 
                                 
                               
                             
                           
                           
                             
                               
                                 I 
                                 0 
                               
                               - 
                               
                                 m 
                                 * 
                                 
                                   I 
                                   TS 
                                 
                               
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             
                               1 
                               + 
                               
                                 
                                   m 
                                   * 
                                   
                                     I 
                                     TS 
                                   
                                 
                                 
                                   I 
                                   0 
                                 
                               
                             
                           
                           
                             
                               1 
                               - 
                               
                                 
                                   m 
                                   * 
                                   
                                     I 
                                     TS 
                                   
                                 
                                 
                                   I 
                                   0 
                                 
                               
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             
                               1 
                               + 
                               
                                 
                                   m 
                                   * 
                                   
                                     I 
                                     C 
                                   
                                   * 
                                   
                                     ( 
                                     
                                       1 
                                       - 
                                       
                                         n 
                                         * 
                                         
                                           T 
                                           S 
                                         
                                       
                                     
                                     ) 
                                   
                                 
                                 
                                   I 
                                   0 
                                 
                               
                             
                           
                           
                             
                               1 
                               - 
                               
                                 
                                   m 
                                   * 
                                   
                                     I 
                                     C 
                                   
                                   * 
                                   
                                     ( 
                                     
                                       1 
                                       - 
                                       
                                         n 
                                         * 
                                         
                                           T 
                                           S 
                                         
                                       
                                     
                                     ) 
                                   
                                 
                                 
                                   I 
                                   0 
                                 
                               
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Thus, over the range of speeds of interest for ADC  200 , it is possible to find a value of m such that the gain GS is exponential in nature, satisfying equation (5) and having the following form: 
         [0000]    
       
         
           
             
               
                 
                   GS 
                   = 
                   
                     
                        
                       
                         m 
                         * 
                         
                           
                             I 
                             TS 
                           
                           
                             I 
                             0 
                           
                         
                       
                     
                     = 
                     
                       
                          
                         
                           m 
                           * 
                           
                             
                               
                                 I 
                                 C 
                               
                               * 
                               
                                 ( 
                                 
                                   1 
                                   - 
                                   
                                     n 
                                     * 
                                     
                                       T 
                                       S 
                                     
                                   
                                 
                                 ) 
                               
                             
                             
                               I 
                               0 
                             
                           
                         
                       
                       = 
                       
                         
                           G 
                           0 
                         
                          
                         
                            
                           
                             
                               - 
                               m 
                             
                             * 
                             
                               
                                 n 
                                 * 
                                 
                                   I 
                                   C 
                                 
                                 * 
                                 
                                   T 
                                   S 
                                 
                               
                               
                                 I 
                                 0 
                               
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Now, substituting equation (12) into equation (4), the output voltage VOUT is: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         VOUT 
                         ≈ 
                           
                          
                         
                           VIN 
                           * 
                           
                             CS 
                             CF 
                           
                           * 
                           
                             ( 
                             
                               1 
                               - 
                               
                                  
                                 
                                   
                                     - 
                                     
                                       T 
                                       S 
                                     
                                   
                                   
                                     3 
                                      
                                     τ 
                                   
                                 
                               
                               + 
                               
                                 a 
                                 * 
                                 k 
                                 * 
                                 GS 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           VIN 
                           * 
                           
                             CS 
                             CF 
                           
                           * 
                           
                             ( 
                             
                               1 
                               - 
                               
                                  
                                 
                                   
                                     - 
                                     
                                       T 
                                       S 
                                     
                                   
                                   
                                     3 
                                      
                                     τ 
                                   
                                 
                               
                               + 
                               
                                 a 
                                 * 
                                 k 
                                 * 
                                 
                                   G 
                                   0 
                                 
                                 * 
                                 
                                    
                                   
                                     
                                       - 
                                       m 
                                     
                                     * 
                                     
                                       
                                         n 
                                         * 
                                         
                                           I 
                                           C 
                                         
                                         * 
                                         
                                           T 
                                           S 
                                         
                                       
                                       
                                         I 
                                         0 
                                       
                                     
                                   
                                 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Therefore, the portion of the MDAC shown in  FIG. 3  can accurately compensate for the settling error of equation (3) by the choice of the appropriate gain k and multiplying factor m. 
         [0021]    From equation (13), however, it can be easily seen that gain GS exponentially increases with speed of ADC  200  (decrease in sampling period T S ). The output impedance of amplifier  304  should, therefore, continue to increase with speed of ADC  200 , causing the bandwidth to decrease. Additionally, the time available for amplifier  304  to settle continues decreasing with speed of ADC  200 . If amplifier  304  fails to settle to its expected output in the hold time of amplifier  304 , the correction will be incorrect. As a result, another example of MDAC  210  (which is generally the same as MDACs  210 - 1  to  210 -(M−1)) is shown in  FIG. 4 . 
         [0022]    In  FIG. 4 , an adjustment is made to the feedback capacitor CF and the correction capacitor CC of  FIG. 3 , yielding feedback capacitor CF′, correction capacitor CC′, and settling amplifier  402 . This adjustment results in the closed loop gain of amplifier  102  of  FIG. 4  being: 
         [0000]    
       
         
           
             
               
                 
                   ClosedLoopGain 
                   = 
                   
                     
                       
                         C 
                         S 
                       
                       
                         C 
                         f 
                         ′ 
                       
                     
                     ≈ 
                     
                       
                         
                           C 
                           S 
                         
                         
                           C 
                           f 
                         
                       
                       * 
                       
                         
                           ( 
                           
                             1 
                             + 
                             δ 
                           
                           ) 
                         
                         . 
                       
                     
                   
                 
               
               
                 
                   ( 
                   14 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Additionally, if the input current I IN  and load current I LOAD  are: 
         [0000]        I   IN   =I   0   −m*I   TS   (15)
 
         [0000]        I   LOAD   =I   0   +m*I   TS ,  (16)
 
         [0000]    then the gain GS of amplifier  402  is: 
         [0000]    
       
         
           
             
               
                 
                   GS 
                   = 
                   
                     
                       G 
                       0 
                     
                      
                     
                       
                          
                         
                           m 
                           * 
                           
                             
                               n 
                               * 
                               
                                 I 
                                 C 
                               
                               * 
                               
                                 T 
                                 S 
                               
                             
                             
                               I 
                               0 
                             
                           
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   17 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The resulting output voltage VOUT would then be: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         VOUT 
                         ≈ 
                           
                          
                         
                           VIN 
                           * 
                           
                             CS 
                             CF 
                           
                           * 
                           
                             ( 
                             
                               1 
                               + 
                               δ 
                               - 
                               
                                  
                                 
                                   
                                     - 
                                     
                                       T 
                                       S 
                                     
                                   
                                   
                                     3 
                                      
                                     τ 
                                   
                                 
                               
                               - 
                               
                                 a 
                                 * 
                                 k 
                                 * 
                                 GS 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           VIN 
                           * 
                           
                             CS 
                             CF 
                           
                           * 
                           
                             ( 
                             
                               1 
                               + 
                               δ 
                               - 
                               
                                  
                                 
                                   
                                     - 
                                     
                                       T 
                                       S 
                                     
                                   
                                   
                                     3 
                                      
                                     τ 
                                   
                                 
                               
                               - 
                               
                                 a 
                                 * 
                                 k 
                                 * 
                                 
                                   G 
                                   0 
                                 
                                 * 
                                 
                                    
                                   
                                     m 
                                     * 
                                     
                                       
                                         n 
                                         * 
                                         
                                           I 
                                           C 
                                         
                                         * 
                                         
                                           T 
                                           S 
                                         
                                       
                                       
                                         I 
                                         0 
                                       
                                     
                                   
                                 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   18 
                   ) 
                 
               
             
           
         
       
     
         [0000]    While this configuration of  FIG. 4  is less accurate than the configuration of  FIG. 3 , it is much simpler to implement because the gain of amplifier  402  is lower than the gain of amplifier  304  at higher speeds. 
         [0023]    Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.