Abstract:
Zero adjustment of second information in an electronic timepiece is carried out upon receiving a command from the operator. &#34;Increment one&#34; is performed upon minute information when the second information is between 24 and 59 seconds when the zero adjustment command is generated. Minute information is not changed when the second information is between 0 and 23 seconds when the zero adjustment command is generated.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to zero adjustment in an electronic timepiece such as an electronic digital wristwatch. 
     The conventional zero adjustment in a mechanical timepiece was performed in the following manner. When the operator depressed a zero adjustment switch at a time when the second-hand was in a region between 0 and 30, the second-hand was forced to rotate fast in a counterclockwise direction to reach the zero second position. When the operator depressed the zero adjustment switch at a time when the second-hand was in a region between 30 and 60, the second-hand was forced to rotate fast in a clockwise direction to reach the zero second position. 
     Recently, the above-mentioned zero adjustment technique has been applied to an electronic timepiece. An electronic timepiece employing a quartz oscillator has, generally, high accuracy, and the error in a month can be controlled within 15 seconds. Therefore, when the operator performs the zero adjustment once a week with reference to the time tone, the error of the electronic timepiece can be always maintained below several seconds. 
     The conventional zero adjustment in an electronic timepiece was achieved in a same manner as for the mechanical one. When the second information was in a region between 0 and 30 at a time when a zero adjustment command was generated, a zero adjust control circuit determined that the timepiece was fast and the second information was forced to become zero without changing the minute information. On the contrary, when the second information was in a region between 30 and 60 at a time when the zero adjustment command was generated, the zero adjust control circuit determined that the timepiece was slow and the second information was forced to become zero with an incremental one step of minute calculation. 
     By the way, in the electronic timepiece which comprises a quartz oscillator of 32,768 KHz and C-MOS circuits, a ratio of tendencies to fast and to slow is not 1:1. Therefore, when the boundary area to increase the minute information is chosen at 30 seconds, there is a considerably great possibility that erroneous time adjustment is achieved. More particularly, increment one is not effected on the minute information at a time when the zero adjustment operation is performed even when the increment is necessary, or the increment operation is performed at a time when it is not required. 
     OBJECTS AND SUMMARY OF THE INVENTION 
     Accordingly, an object of the present invention is to provide a zero adjust control circuit for use in conjunction with an electronic timepiece. 
     Another object of the present invention is to provide a zero adjust control circuit which can perform accurate time adjustment in an electronic timepiece. 
     Other objects and further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications wtihin the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. 
     To achieve the above objectives, the present inventors have measured the ratio of tendencies to fast and to slow in an electronic timepiece employing the quartz oscillator. The boundary area to increase the minute information at the zero adjustment operation is determined in accordance with the said measurement. 
     The electronic timepiece has generally a great tendency to slow that to fast. The error is a month of the electronic timepiece mostly belongs within a region which is to fast 20 seconds and to slow 40 seconds. Therefore, the boundary area to add one to the minute information at the zero adjustment operation is selected below 30 seconds, for example, at 24 seconds. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein, 
     FIG. 1 is a graph showing error versus operation temperature characteristics of a quartz oscillator used in an electronic timepiece; 
     FIG. 2 is a circuit diagram of an embodiment of a zero adjust control circuit of the present invention; and 
     FIG. 3 is a time chart showing wave forms of various signals occurring within the circuit of FIG. 2. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now in detail to the drawings, and to facilitate a more complete understanding of the present invention, characteristics of a quartz oscillator used in an electronic timepiece of the present invention will be first described with reference to FIG. 1. 
     FIG. 1 shows the relationship between the operation temperature (along the abscissa axis) and the error in a day (along the ordinate axis) of an electronic timepiece employing the quartz oscillator of 32,768 KHz and the C-MOS calculation circuit. 
     In general, the electronic timepiece such as an electronic wristwatch is used at a temperature between 10° C. and 35° C. The chronometer standard requires that the error becomes zero near 25° C. Therefore, the quartz oscillator used in the electronic timepiece is so controlled that the error becomes zero when used at 25° C. It will be clear from FIG. 1 that the electronic timepiece has a tendency to slow at every temperature except 25° C. 
     As discussed above the electronic timepiece employing the quartz oscillator has a tendency to slow. But the characteristics of the quartz oscillator may be shifted to fast upon reception of an outer shock. Therefore, there is provided a trimmer condenser to regulate the quartz-crystal oscillation, but it is almost impossible to accurately control the oscillator to make the error zero. 
     FIG. 2 shows a circuit construction of a zero adjust control circuit of the present invention and FIG. 3 shows wave forms of various signals occurring within the circuit of FIG. 2. In this embodiment, the boundary area to add one to the minute information at a time when the zero adjustment is performed is selected at 24 seconds. 
     A typical circuit construction of an entire electronic digital wristwatch is shown in Tsutomu Nakamura and Mitsuo Morihisa U.S. Pat. No. 818,484 &#34;POWER SUPPLY CIRCUIT FOR ELECTRONIC DIGITAL SYSTEM&#34; patented on June 18, 1974 and assigned to the same assignee as the present application. Therefore, FIG. 2 only shows an essential part of the circuit of the present invention and the remaining portions have been omitted for the purpose of simplicity. 
     A second information counter C 1  comprises six T-type flip-flops F 1 , F 2 , F 3 , F 4 , F 5  and F 6 , which are connected in series to form a 1/60 frequency divider. A minute information counter C 2  is formed in the same manner as the second information counter C 1 . The respective output signals of the T-type flip-flops F 1  -F 6  are applied to a display system (not shown) via a decoder (not shown) in a parallel fashion to display the second information or the minute information as is well known in the art. S 1  is a zero adjustment command switch, and A is an &#34;increment one&#34; circuit to add one to the minute information at a time when the zero adjustment is performed. 
     The zero adjustment command switch S 1 , a NAND gate A 1  and another NAND gate A 2 , from which an output signal is applied to the reset terminals R of the respective T-type flip-flops F 1 , F 2 , F 3 , F 4 , F 5  and F 6  of the second information counter C 1 , form in combination a &#34;forced zero clear&#34; circuit of the second information. A NAND gate A 3 , of which input terminals are connected to receive output signals Q from the third, fourth, fifth and sixth flip-flops F 3 , F 4 , F 5  and F 6  of the second information counter C 1 , a flip-flop FF and the NAND gate A 2  form in combination an &#34;automatic zero clear&#34; circuit of the second information. When the respective output signals Q of the flip-flops F 3 , F 4 , F 5  and F 6  become the high levels, namely, when the second information counter C 1  counts 59 seconds, the &#34;automatic zero clear&#34; circuit functions to reset the flip-flops F 1 , F 2 , F 3 , F 4 , F 5  and F 6  and clear the content of the counter C 1  to become zero upon receiving the following timing clock. 
     One input terminal of the NAND gate A 1  (a reset terminal RS) is connected to +V volts level via the zero adjustment command switch S 1 . Another input terminal of the NAND gate A 1  is connected to receive a timing signal CON&#39; of which a wave form is shown in FIG. 3(a). 
     When the zero adjustment command switch S 1  is depressed, the reset terminal RS of the NAND gate A 1  bears the high level and, therefore, the NAND gate A 1  provides a signal 1 as shown in FIG. 3(c). The signal 1 is applied to the NAND gate A 2 , at which a reset pulse is provided in synchronization with the timing signal COM&#39;, whereby the flip-flops F 1 , F 2 , F 3 , F 4 , F 5  and F 6  are forced to become zero to clear the second information in the counter C 1 . A signal SR at the reset terminal RS of the NAND gate A 1  is shown in FIG. 3(b). 
     When the zero adjustment command switch S 1  is depressed at a time when the second information is between 24 and 59, &#34;increment one&#34; is performed upon the minute information by the &#34;increment one&#34; circuit A in the following manner. 
     An ND gate A 4 , a NOR gate A 5  and an inverter A 6  in combination determine whether the second information in the counter C 1  is between 24 and 59. The AND gate A 4  connected to receive the output signals Q of the fourth and fifth flip-flops F 4  and F 5  in the second counter C 1  determines whether the second information is between 24 and 31. The inverter A 6  provides an output signal CM of the high level when the second information in the counter C 1  is greater than or equal to 24, since the NOR gate A 5  is connected to receive the output signal of the AND gate A 4  and the output signal Q of the sixth flip-flop F 6  in the counter C 1 . FIG. 3(d) shows an output wave form CM of the inverter A 6 . When the zero adjustment command switch S 1  is depressed, the output signal CM is forced to become the low level as shown in FIG. 3(d) since the respective flip-flops F 1  -F 6  are forced to become zero by the output signal of the NAND gate A 2 . 
     NAND gates A 7 , A 8 , an inverter A 9  and NAND gates A 10 , A 11  in combination function to provide an increment signal to be applied to the minute counter C 2 . The NAND gate A 7  is connected to receive the output signal CM of the inverter A 6  and the reset signal SR associated with the depression of the zero adjustment command switch S 1 . Therefore, when the zero adjustment command switch S 1  is depressed at a time when the second information in the counter C 1  is above 24, the NAND gate A 7  provides an increment signal 2 as shown in FIG. 3(e). The minute information in the minute counter C 2  is &#34;incremented one&#34; by the increment signal 2. 
     The output signal of the sixth flip-flop F 6  of the second information counter C 1  is applied to one input terminal of the NAND gate A 8 . The NAND gate A 8 , the inverter A 9  and the NAND gates A 10 , A 11  in combination provides increment signals 5 as shown in FIGS. 3(n) and 3(o) to &#34;add one&#34; to the minute information. An input signal MS for the NAND gate A 11  is a timing signal for synchronizing the minute counter C 2 . 
     FIGS. 3(f) and 3(g) show wave forms of the Q output signal SC 32  of the sixth flip-flop F 6  included within the second information counter C 1 . FIG. 3(f) shows the wave form when the zero adjustment command switch S 1  is depressed at a time when the second information is between 24 and 31. FIG. 3(g) shows the wave form when the zero adjustment command switch S 1  is depressed at a time when the second information is greater than 32. 
     FIGS. 3(h), 3(i) and 3(j) show the output signal 3 of the NAND gate A 8  when the zero adjustment command switch S 1  is depressed at the time when the second information in the counter C 1  is between 24 and 31, over 32, and below 23, respectively. 
     FIGS. 3(k), 3(l), 3(m), 3(o) and 3(p) show output signals 4 and 5 of the inverter A 9  and the NAND gate A 10  when the zero adjustment command switch S 1  is depressed at the time when the second information in the counter C 1  is between 24 and 31, above 32, and under 23 respectively. 
     As described above, in accordance with the embodiment of the present invention, the minute information is &#34;added one&#34; by the trailing edge of the output signal of the NAND gate A 10  when the zero adjustment command switch S 1  is depressed at a time when the second information in the counter C 1  is between 24 and 59. 
     The invention being thus described, it will be obvious that the same way be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following claims.