Abstract:
A voltage converter circuit includes a first transistor (M 1 ) having a drain connected to receive an unregulated input voltage (Vin), a gate connected to receive a feedback control signal ( 4 ), and a source connected to a first conductor ( 5 ). An inductor ( 6 ) having a first terminal coupled to the first conductor ( 5 ) and a second terminal use connected to produce a regulated output voltage (Vout) on an output conductor ( 7 ). A feedback control circuit ( 190 ) coupled between the gate of the first transistor (M 1 ) and the output conductor for regulating switching of the first transistor in response to the regulated output voltage (Vout). A synchronous rectifier circuit includes a comparator ( 120 ) having an inverting input coupled to the first conductor ( 5 ) and a non-inverting input coupled to the reference voltage conductor ( 3 ), a logic circuit ( 140 ) having an input coupled to an output ( 13 ) of the comparator, a first output ( 15 ), and a second output ( 9 ), a second transistor (M 2 - 1 ) having a gate coupled to the first output ( 15 ), a source coupled to the reference voltage conductor ( 3 ), and a drain coupled to the first conductor ( 5 ), and a third transistor (M 2 - 2 ) having a gate coupled to the second output ( 9 ), a source coupled to the reference voltage conductor ( 3 ), and a drain coupled to the first conductor ( 5 ).

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates generally to synchronous rectifier circuits, and more particularly to “buck”, “boost” and other switching voltage converter circuits (i.e., voltage regulator circuits) that include synchronous rectifier circuits, and still more particularly to such voltage converter circuits which operate with reduced power dissipation and improved efficiency. 
     FIG. 1 shows a conventional buck switching voltage converter  1  that includes a synchronous rectifier. The synchronous rectifier includes a large, low-resistance MOS N-channel transistor M 2  having its source connected to a ground conductor  3 , its gate being coupled by logic circuitry  14  to the output of a comparator  12  having its (+) input connected to a ground conductor  3  and its (−) input connected by conductor  5  to the drain of transistor M 2 . Logic circuitry  14  typically includes a latch circuit that prevents comparator  12  from turning transistor M 2  on more than once during each switching cycle. This can occur if the offset of comparator  12  is negative and causes transistor M 2  to be turned off “early”, in which case the magnitude of the V DS  voltage between the drain and source of transistor M 2  rapidly increases to equal the forward bias voltage of a “body diode” D and then decreases back down to the threshold voltage of comparator  12 . Transistor M 2  inherently includes the drain-to-substrate body diode D, with its N-type cathode region common with the drain and its P-type anode connected to the source of transistor M 2 . 
     Voltage converter circuit  1  also includes an input conductor  2  receiving an unregulated voltage Vin and applying it to the drain of an N-channel switching transistor M 1 . The source of transistor M 1  is connected by conductor  5  to the drain of transistor M 2  and to a first terminal of an inductor  6  having an inductance L. A second terminal of inductor  6  is connected by an output conductor  7  to a first terminal of a load or output capacitor  8  having a capacitance C. As is well known to those skilled in the art, an inductor current I INDUCTOR  flows back and forth between inductor  6  and capacitor  8  during operation of voltage converter circuit  1 . The second terminal of load capacitor  8  is connected to ground conductor  3 . A regulated output voltage Vout is produced on output conductor  7 . The regulated output voltage Vout is applied to an input of a feedback control circuit  19  that compares Vout with a reference voltage and accordingly produces a signal on conductor  4  to control the switching of transistor M 1  so as to cause voltage regulator circuit  1  to maintain the desired regulated value of Vout. 
     In any integrated circuit manufacturing process, the comparator (such as comparator  12 FIG. 1) has an inherent offset voltage, which may be positive or negative. The value of the comparator offset voltage produced by any particular integrated circuit manufacturing process has a statistical distribution. 
     In operation, switching transistor M 1  is turned on during the initial part of each switching cycle. This causes current to flow from the source of the unregulated voltage Vin through transistor M 1  and inductor  6  such that conductor  7  supplies current to maintain the desired value of output voltage Vout across a load capacitor  8  that may be connected to conductor  7  and/or across any additional external load that may be connected to conductor  7 . During this portion of the switching cycle, the voltage of conductor  5  is high, so the output of comparator  12  is at a logical “0” level. The low “ 0 ” output voltage produced by comparator  12  causes logic circuit  14  to keep transistor M 2  turned off. The flow of I INDUCTOR  into load capacitor  8  increases the value of Vout to the desired regulated value determined by a reference voltage within feedback control circuit  19 , which then produces a signal on conductor  4  that abruptly turns switching transistor M 1  off. 
     The current I INDUCTOR  cannot change abruptly, and therefore continues to flow from conductor  5  through inductor  6  and conductor  7 . This causes the voltage on conductor  5  to rapidly decrease to a level approximately 600 millivolts below ground, at which point body diode D becomes forward biased enough to supply the current I INDUCTOR . The low voltage on conductor  5  causes comparator  12  to switch, causing it to produce a high logical “1” output level. That causes logic circuit  14  to produce a high voltage level on the gate of transistor M 2  after a short delay, turning transistor M 2  on. 
     The size of transistor M 2  is selected so that when it is turned on, its channel resistance (Ron) is low enough that its drain-to-source voltage V DS  is reduced from the approximately 600 millivolt forward bias voltage of body diode D to only approximately 100 millivolts (which reverse biases body diode D). Therefore, the power dissipation due to the flow of I INDUCTOR  through transistor M 2  after it is turned on is much lower than the power dissipation due to the flow of I INDUCTOR  through body diode D before transistor M 2  is turned on. After transistor M 1  is turned off, the magnitude of I INDUCTOR  gradually decreases at the rated (I INDUCTOR )/dt=Vout/L. Therefore, the drain-source voltage V DS  voltage of transistor M 2  decreases at roughly the same rate as I INDUCTOR  until the V DS  of transistor M 2  is equal to the offset voltage of comparator  12 , which typically can be as large as approximately 10 millivolts above or below ground. 
     Typically, the size of transistor M 2  is chosen so that when the maximum value of I INDUCTOR  is flowing through the channel resistance of transistor M 2 , its V DS  voltage is approximately equal to the above mentioned 100 millivolts. The 10 millivolt offset voltage of comparator  12  typically corresponds to roughly 10 percent of the maximum value of I INDUCTOR . If, for example, the magnitude of the offset voltage of comparator  12  is 10 millivolts, the decreasing V DS  voltage causes comparator  12  to turn off transistor M 2  either too soon or too late, depending on whether the offset voltage is positive or negative. In either case, the power dissipation is substantially increased. If the offset voltage is negative, transistor M 2  is turned off too late, and then it draws current from load capacitor  8  and any additional load that is connected to output conductor  7 . Even if the net current flow out of conductor  7  to an external load (not shown) is zero, I INDUCTOR  at that time has a value equal to approximately 10 percent of the maximum current through inductor  6  and oscillates between inductor  6  and load capacitor  8 , and also flows through the channel resistance of transistor M 2  and dissipates power therein. 
     If the comparator offset voltage is positive, then transistor M 2  will be turned off too soon. In that case, there is still up to approximately 10 percent of the maximum inductor current still flowing in inductor  6 , and it flows through the large 600 millivolt forward bias voltage of body diode D, and consequently dissipates a large amount of power. 
     Thus, the prior art buck voltage converter  1  of FIG. 1 is characterized by decreased conversion efficiency for either positive or negative offset voltages of comparator  12 . 
     Synchronous rectifier circuits of the kind described above also can be used in motor control circuits, class D audio amplifiers, and other circuitry. 
     Thus, there is an unmet need for an improved synchronous rectifier that accomplishes improved conversion efficiency when used in a utilization circuit such as an integrated circuit voltage converter, a motor control circuit, a class D audio amplifier, or the like. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide an improved synchronous rectifier circuit having reduced power dissipation when used in conjunction with a utilization circuit. 
     It is another object of the present invention to provide an improved synchronous rectifier circuit having reduced power dissipation when used in conjunction with a signal conversion circuit. 
     It is another object of the present invention to provide an improved synchronous rectifier circuit having reduced power dissipation when used in conjunction with a voltage converter circuit. 
     It is another object of the present invention to provide an improved synchronous rectifier circuit having reduced power dissipation when used in conjunction with a buck voltage converter circuit. 
     It is another object of the present invention to provide an improved synchronous rectifier circuit having reduced power dissipation when used in conjunction with a boost voltage converter circuit. 
     It is another object of the present invention to provide an improved synchronous rectifier circuit which avoids the above described problems of the prior art. 
     It is another object of the invention to provide an improved voltage converter circuit including a synchronous rectifier. 
     It is another object of the invention to avoid undesirable effects of delay through a comparator in a synchronous rectifier of a voltage converter or other utilization device such as a motor control circuit or a class D audio amplifier to decrease power dissipation. 
     Briefly described, and in accordance with one embodiment, the present invention provides a synchronous rectifier circuit suitable for use in conjunction with a utilization circuit such as a signal conversion circuit. In its broadest aspects, the synchronous rectifier circuit includes a comparator ( 120 ) having first input coupled to a first conductor ( 5 ) and a second input coupled to a reference voltage conductor ( 3 ). Typically, the first conductor conducts a current that also flows through an inductor. The synchronous rectifier circuit includes a logic circuit ( 140 ) having an input coupled to an output ( 13 ) of the comparator, a first output ( 15 ), and a second output ( 9 ), a first transistor (M 2 - 1 ) having a gate coupled to the first output ( 15 ), a source coupled to the reference voltage conductor ( 3 ), and a drain coupled to the first conductor ( 5 ), and a second transistor (M 2 - 2 ) having a gate coupled to the second output ( 9 ), a source coupled to the reference voltage conductor ( 3 ), and a drain coupled to the first conductor ( 5 ). 
     In the described embodiments, the synchronous rectifier circuit is included in a voltage converter circuit. In one embodiment the synchronous rectifier circuit includes a comparator ( 12 ) having an inverting input coupled to a first conductor ( 5 ) and a non-inverting input coupled to a reference voltage conductor ( 3 ), a logic circuit ( 140 ) having an input coupled to an output ( 13 ) of the comparator, a first output ( 15 ), and a second output ( 9 ), and transistor circuitry including first and second transistor sections. The first transistor section (M 2 - 1 ) has a gate coupled to the first output ( 15 ), a source coupled to the reference voltage conductor ( 3 ), and a drain coupled to the first conductor ( 5 ). The second transistor section (M 2 - 2 ) has a gate coupled to the second output ( 9 ), a source coupled to the reference voltage conductor ( 3 ), and a drain coupled to the first conductor ( 5 ). The logic circuit ( 140 ) is operative to turn on both the second transistor section (M 2 - 1 ) and the third transistor section (M 2 - 2 ) in response to a first switching of the comparator ( 12 ) to a “1” level, and to turn off only the first transistor section (M 2 - 1 ) in response to a second switching of the comparator to the “1” level, and to turn the off second transistor section (M 2 - 2 ) in response to a third switching of the comparator to the “1” level. The logic circuit ( 140 ) also is operative to turn on both the second transistor section (M 2 - 1 ) and the second transistor section (M 2 - 2 ) in response to a first switching of the comparator from a “0” level to a “1” level and to turn off the first transistor section (M 2 - 1 ) if the comparator does not then switch from the “1” level to the “0” level within a predetermined delay. 
     The voltage converter circuit includes a first transistor (M 1 ) having a drain connected to receive an unregulated input voltage (Vin), a gate connected to receive a feedback control signal ( 4 ), and a source connected to a first conductor ( 5 ). An inductor ( 6 ) includes a first terminal coupled to the first conductor ( 5 ) and a second terminal connected to produce a regulated output voltage (Vout) on an output conductor ( 7 ). A load or output capacitor ( 8 ) is coupled between the output conductor and a reference voltage conductor ( 3 ). A feedback control circuit ( 19 ) is coupled between the gate of the first transistor (M 1 ) and the output conductor for regulating switching of the first transistor in response to the regulated output voltage (Vout) so as to maintain it at a desired value. 
     In another embodiment the synchronous rectifier is included in a boost voltage regulator. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a prior art synchronous rectifier connected in a buck voltage converter circuit. 
     FIG. 2 is a schematic diagram of a synchronous rectifier of the present invention, connected in a buck voltage converter circuit. 
     FIG. 3 is a timing diagram useful in describing the operation of the synchronous rectifier included in FIG. 2 for large values of the inductor current. 
     FIG. 4 is a schematic diagram useful in describing the operation of the synchronous rectifier circuit included in FIG. 2 for low values of the inductor current. 
     FIG. 5 is a schematic diagram useful in describing a practical implementation of logic circuit  140  of FIG.  2 . 
     FIG. 6 is a schematic diagram of a synchronous rectifier of the present invention, connected in a boost voltage converter circuit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 2, the illustrated buck voltage converter circuit  10  is similar to the one in prior art FIG. 1, except that in FIG. 2 an improved synchronous rectifier circuit is provided that includes comparator  12 , logic circuit  140 , and at least two N-channel transistors or transistor sections M 2 - 1  and M 2 - 2 . An output of feedback control circuit  190  is connected to a conductor  47  that is connected to an input of a driver/level shift circuit  56  that produces a suitably high drive voltage on conductor  4  to fully turn on transistor M 1 . The signal on a conductor  47  therefore is essentially coincident with the gate drive signal on conductor  4  which turns transistor M 1  on. 
     Logic circuit  140  includes circuitry (subsequently described) responsive to the signal on conductor  47  to control the turn-on of a composite transistor M 2  so as to prevent “shoot-through” currents which otherwise would occur if transistors M 1  and M 2  are both simultaneously in an on condition. The circuitry referred to also bypasses and thereby avoids delay associated with comparator  120  so as to substantially reduce power dissipation across the large forward bias voltage of body diode D when the inductor current is large, and is subsequently described with reference to FIG.  5 . 
     In FIG. 2, transistor M 2  of prior art FIG. 1 is replaced by a “composite” transistor M 2  including a transistor section M 2 - 1  and a transistor section M 2 - 2  which have a common source electrode, a common drain electrode, and two separate gate electrodes connected to conductors  9  and  15 , respectively. (Alternatively, composite transistor M 2  could be replaced by two separate transistors M 2 - 1  and M 2 - 2  connected as shown.) The gate electrode of transistor section M 2 - 1  is connected by conductor  15  to a first output of logic circuit  140 , and the gate electrode of transistor section M 2 - 2  is connected by conductor  9  to a second output of logic circuit  140 . The common source of transistor sections M 2 - 1  and M 2 - 2  is connected to ground conductor  3 , and the common drain thereof is connected to conductor  5 . The channel-width-to-channel-length ratio of transistor section M 2 - 1  is N times greater than that of transistor section M 2 - 2 , so the channel resistance (Ron) of transistor section M 2 - 2  is N times that of transistor section M 2 - 1 . 
     Comparator  120  of FIG. 2 is different than comparator  12  of prior art FIG. 1, in that comparator  120  includes a built-in negative offset voltage the magnitude of which is slightly larger than the statistical offset voltage variation that would be present in any large sample of comparators  120  manufactured by the CMOS manufacturing process to be utilized to make buck voltage converter circuit  10 . The built-in negative offset voltage V offset  (see horizontal dashed line  22  of FIG. 3) of comparator  120  causes it to switch so as to produce a “1” level on conductor  13  when the voltage on conductor  5  decreases to a voltage that is equal to a negative offset of V offset  volts less than the voltage on the (+) input of comparator  120 , i.e., ground or zero volts. 
     When a logic “1” level is first produced by comparator  120  on conductor  13 , logic circuit  140  produces high voltages on both conductors  9  and  15  so as to turn on both transistor section M 2 - 1  and transistor section M 2 - 2 , provided the magnitude of I INDUCTOR  flowing out of the drain of composite transistor M 2  is sufficiently large to cause its V DS  voltage V DS(M2)  to be large enough to cause comparator  120  to switch its output back to a “0” level as soon as transistor sections M 2 - 1  and M 2 - 2  are turned on. 
     After transistor sections M 2 - 1  and M 2 - 1  have been switched on by comparator  120  and logic circuit  140  in response to the rapid decrease of V DS(M2)  caused by transistor M 1  being turned off, the composite transistor M 2  including transistor sections M 2 - 1  and M 2 - 2 , operating in combination with logic circuit  14 , permits the lower resistance transistor section M 2 - 1  to be switched off first, at the time when the slowly decreasing V DS(M2)  voltage (caused by the slowly decreasing flow of I INDUCTOR  through the channel resistance of composite transistor M 2 ) reaches the threshold voltage of comparator  120 . This causes comparator  120  to switch its output from a “0” level to a “1” level, causing logic circuit  140  to turn off transistor section M 2 - 1 . As a result of the lower resistance transistor section M 2 - 1  being turned off and the higher resistance section (M 2 - 2  remaining on, the magnitude of the V DS(M2)  voltage rapidly increases to a level well above the magnitude of the threshold voltage of comparator  120 . 
     The magnitude of the V DS(M2)  voltage then gradually decreases from that level proportionally to the decrease in the magnitude of I INDUCTOR . When the magnitude of the V DS(M2)  voltage again reaches the magnitude of the threshold of comparator  120 , it again switches its output V 13  from a “0” level to a “1” level, and this time causes logic circuit  140  to turn off the second transistor section M 2 - 2 . From that point until the end of the present switching cycle, any remaining inductor current flows through the relatively large 600 millivolt voltage drop of body diode D. 
     It is undesirable for the offset voltage of comparator  120  to be positive, because that causes transistor section M 2 - 1  to be switched off later. Therefore, comparator  120  preferably is designed so that it has a built-in negative offset voltage the magnitude of which is slightly greater than the statistical range of offset voltages that otherwise would be expected for the integrated circuit manufacturing process to be used. Consequently, the lower resistance transistor section M 2 - 1  always will be turned off a bit early. (A built-in negative offset voltage of either positive or negative polarity is easily accomplished in any comparator or differential amplifier input stage by simply providing different size input transistors that are ratioed so as to provide the desired polarity and magnitude of the offset voltage.) 
     If transistor section M 2 - 1  is turned off early, there is additional power loss because I INDUCTOR  is larger at the time comparator  120  switches than is the case if transistor section M 2 - 1  is turned off later. That larger amount of I INDUCTOR  flows first through the relatively large 600 millivolt forward bias voltage drop of body diode D and dissipates therein a substantial amount of power, and later flows across the approximately 100 millivolt V DS(M2)  voltage of composite transistor M 2 , then dissipating substantially less power. 
     In accordance with present invention, above mentioned power loss is reduced by ensuring that only a relatively low resistance section (a relatively large channel-width-to-channel-length section) of composite transistor M 2  is turned off early, and the remaining high resistance section of composite tranisistor M 2  is left on. This prevents the present amount of I INDUCTOR  at the time transistor section M 2 - 1  is turned off from flowing across the large 600 millivolt drop of body diode D and causes it to instead flow through the channel resistance of the high resistance section of transistor M 2 - 2  that has been left on, so as to produce a V DS(M2)  voltage of only approximately 100 millivolts instead of the 600 millivolt forward bias voltage drop across body diode D. This substantially reduces the power dissipation during the immediately following portion of the switching cycle, and therefore substantially increases the conversion efficiency of the voltage converter  10  shown in FIG.  2 . 
     When the V DS(M2)  voltage on conductor  5  has decreased enough due to the decreasing of I INDUCTOR  to again reach the built-in negative offset threshold of comparator  120 , it again switches its output so as to cause logic circuit  140  to also turn off transistor section M 2 - 2 . 
     The operation of voltage converter  10  of FIG. 2, for a relatively large initial value of I INDUCTOR  at the beginning of the switching cycle, can be understood by referring to FIG. 3, which is a timing diagram including the waveform of the drain-to-source voltage V DS(M2)  across composite transistor M 2  (which is equal to the voltage on conductor  5 ), the waveform of the comparator output voltage V 13  on conductor  13 , and the waveform of the inductor current I INDUCTOR . 
     Referring to FIG. 3, the steep downward segment  23 - 1  of the V DS(M2)if  waveform occurs as a result of transistor M 1  being abruptly turned off. (As those skilled art will realize, the current-carrying electrode of an N-channel MOS transistor presently having the highest voltage functions as a drain electrode, and the other current-carrying electrode functions as a source electrode. Therefore, the roles of the two current-carrying electrodes of an MOS transistor are reversed as the voltage of one of them increases above the voltage of the other during circuit operation. Therefore, in both the description and claims herein, it is to be understood that when an electrode of an MOS transistor is referred to as a “source”, this indicates the electrode having an arrow thereon in the drawings, but does not necessarily indicate whether that electrode functions as a source, or a drain, or both, of the MOS transistor.) 
     At the time indicated by vertical dashed line  25 , segment  23 - 1  of the V DS(M2)  waveform (also referred to as the V DS(M2)  waveform) has decreased to the level of the negative comparator offset voltage V offset  represented by dashed line  22 , and continues going more negative until body diode D becomes forward biased at approximately 600 millivolts below ground. Comparator  120  switches when V DS(M2)  falls below the level of the V offset  voltage indicated by horizontal dashed line  22 , causing the comparator output on conductor  13  to rise as indicated by segment  31 - 1  of the V 13  waveform. 
     When transistor M 1  is turned off, I INDUCTOR  stops increasing, as indicated by segment  32 - 1  of the I INDUCTOR  waveform and begins decreasing as indicated by segment  32 - 2 . Comparator  120  switches its output from a “0” to a “1” when V DS(M2)  reaches the threshold voltage of comparator  120 . This causes logic circuit  140  to turn on both transistor sections M 2 - 1  and M 2 - 2 . When composite transistor M 2  is thus turned on, it rapidly pulls V DS(M2)  upward from the approximately 600 millivolt level below ground caused by body diode D to the voltage defined by the “on” channel resistance of composite transistor M 2  and I INDUCTOR  (usually designed to be approximately 100 millivolts below ground at the maximum value of I INDUCTOR ), as indicated by segment  23 - 2 . As the inductor current decreases, V DS(M2)  goes higher from an initial value below ground to the offset voltage of comparator  120 . The typical offset voltage of a CMOS comparator can be as high as 10 millivolts, so the predetermined value of V offset  should exceed this value. At that point, comparator  120  switches again, at the time indicated by vertical dashed line  26 , and V 13  undergoes a transition indicated by segment  31 - 3  in FIG.  3 . This causes logic circuit  140  to turn off the low-resistance transistor section M 2 - 1 , thereby abruptly increasing the channel resistance of the composite transistor M 2  to the high resistance value of transistor section M 2 - 2 . The flow of I INDUCTOR  through the increased channel resistance therefore causes the value of V DS(M2)  to rapidly decrease, as indicated by segment  23 - 3  of the V DS(M2)  waveform. This operation causes comparator  120  to switch back to a “1” level, as indicated by segment  31 - 4  in FIG.  3 . 
     As I INDUCTOR  continues decreasing along segment  32 - 2 , V DS(M2)  increases as indicated by segment  23 - 4  until V DS(M2)  again reaches the threshold of comparator  120 , causing its output voltage V 13  to switch again, as indicated by segment  31 - 6 . That causes logic circuit  140  to turn off transistor segment M 2 - 2 , so the present value of I INDUCTOR  causes V DS(M2)  to sharply decrease to the −600 millivolt level established by the forward bias voltage of body diode D. The decreasing of V DS(M2)  along segment  23 - 5  causes comparator  120  to switch again, as indicated by segment  31 - 7 . When I INDUCTOR  becomes equal to 0, V DS(M2)  becomes somewhat undefined, as indicated by the dashed line segment  23 - 6 . After transition  31 - 6  of V 13 , a latch circuit (not shown) in logic circuit  140  operates to keep composite transistor M 2  in its off condition. 
     In the case in which the initial value of I INDUCTOR  is very low, the waveform shown in FIG. 4 is useful in explaining the operation of voltage conversion circuit  10 . If the initial value of I INDUCTOR  is very low, then comparator  120  first switches as indicated by segment  44 - 1 , causing V 13  to go to a “1” level in response to I INDUCTOR  being supplied through the 600 millivolt forward bias voltage of body diode D. Comparator  120  then causes V 13  to immediately go to a “0” level, as indicated by segment  44 - 2 . (Note that this is unlike the previously described high current case illustrated in FIG. 3, wherein V 13  remains at the “1” level as indicated by segment  31 - 2  of the V 13  waveform.) The “1” level at the top of the segment  44 - 1  of the V 13  waveform in FIG. 4 causes logic circuit  140  to initially turn on both transistor sections M 2 - 1  and M 2 - 2  of composite transistor M 2 , which causes the value of V DS(M2)  to rise toward V offset  as indicated by segment  36 - 2  of the V DS(M2)  waveform. When V DS(M2)  reaches V offset  comparator  120  immediately causes V 13  to undergo a transition  44 - 2  back to a “0” level, as indicated by segment  44 - 2  of the V 13  waveform, and logic circuit  140  turns off the low resistance transistor section M 2 - 1 . Since I INDUCTOR  is very small, it causes the value of V DS(M2)  to stay above the threshold value V offset  of comparator  120  as indicated by segment  36 - 3 , and comparator  120  continues to hold V 13  at a “0” level. 
     If logic circuit  140  determines that V 13  does not increase to a “1” level after transistor section M 2 - 1  has been turned off, then logic circuit  140  also turns off transistor section M 2 - 2 . That causes the comparator output voltage V 13  to increase to a “1” level as indicated by segment  44 - 4 . But even after both transistor sections M 2 - 1  and M 2 - 2  are turned off, I INDUCTOR  is still greater than zero. That means the voltage V DS(M2)  will rapidly fall to the −600 millivolt level established by body diode D. That large magnitude of V DS(M2)  causes comparator  120  to be turned on so as to produce a “1” level at its output. (The above mentioned latch circuit in logic circuit  140  prevents this from affecting the state of voltage converter circuit  10 .) Eventually, I INDUCTOR  decreases to zero, and when it reaches zero, with composite transistor M 2  completely off, the voltage V DS(M2)  is determined by parasitic capacitance on conductor  5  and parasitic leakage currents and therefore is indeterminate, as indicated by dashed line segment  36 - 5  of the V DS(M2)  waveform. 
     Those skilled in the art will recognize that logic circuit  140  can be readily implemented in a variety of ways so as to perform the above described functions. For example, FIG. 5 shows a partial implementation wherein logic circuitry  140 A is the portion of logic circuit  140  that prevents shoot-through currents. Logic circuitry  140 A includes a NAND gate  49  having a first input connected to conductor  47  and a second input connected to conductor  48 . 
     Conductor  47  is connected to the input of the above-mentioned driver circuit  56  and to the output of feedback control circuit  190 , so the logic signal on conductor  47  is nearly coincident with the boosted drive signal on conductor  4  that turns on transistor M 1 . Conductor  48  is connected to the enable input of comparator  120  and to a comparator enable output of feedback control circuit  190 . The comparator enable signal produced on conductor  48  by feedback control circuit  190  disables comparator  120  immediately before producing a “1” signal on conductor  47  to causes driver  56  to produce a large positive signal on conductor  4  and thereby turn on transistor M 1 , to ensure that both transistor sections M 21 - 1  and M 2 - 2  are completely off before transistor M 1  is turned on. Similarly, the comparator enable signal on conductor  48  enables comparator  120  immediately after transistor M 1  is turned off. The logic signal on conductor  47  is delayed relative to the logic signal on conductor  48  such that comparator  120  is disabled before transistor M 1  is turned on. Similarly, the logic signals on conductor  47  and  48  are timed so that comparator  120  is enabled as soon as transistor M 1  is turned completely off. 
     However, the delay through comparator  120  is relatively long, so the purpose of the logic signal on conductor  47 , NAND gate  49 , single-pulse generator  50 , and OR gate  52  is to provide a much faster turn on signal to transistor M 2 - 1  on conductor  15  than can be applied to comparator  120 . This reduces the amount of time that the conductor current I INDUCTOR  needs to be flowing through the 600 millivolt forward bias voltage of body diode D, and if I INDUCTOR  is large, the reduction in power dissipation in body diode D can be very substantial. 
     The output of NAND gate  49  is connected to the input of a single-pulse generator circuit  50 , the output of which is connected by conductor  51  to a first input of an OR gate  52 . Single-pulse generator circuit  51  operates to, in effect, override comparator  120  so as to rapidly produce a fixed-duration output pulse on conductor  51  in response to each negative transition of the output of NAND gate  49 . The second input of OR gate  52  is connected to conductor  13  to receive output signals produced by comparator  120 . The output of OR gate  52  is connected by conductor  53  to the input of a driver circuit  54 , the output of which is connected by conductor  15  to the gate of transistor section M 2 - 1 . (Single-pulse generator circuit  50  can be a one-cycle oscillator circuit. Or alternatively, a latch circuit can be utilized in conjunction with additional logic circuitry to provide the same function.) 
     To summarize, feedback control circuit  190  produces a “1” level on conductor  47  when the voltage on conductor  4  in FIG. 2 falls below the threshold voltage at which transistor M 1  is turned off. This causes NAND gate  49  to trigger single-pulse generator circuit  50  to produce a fixed-duration “1” level on conductor  51 , which in turn causes OR gate  52  to produce a “1” pulse of the same duration on conductor  53  and thereby rapidly cause driver  54  to turn on transistor section M 2 - 1  for that fixed duration, and simultaneously ensuring that there is no shoot-through current from Vin. 
     Logic circuitry similar to logic circuit  140 A can be provided to generate the signal applied by conductor  9  to the gate of transistor section M 2 - 2  to turn it on simultaneously with transistor section M 2 - 1 . 
     FIG. 6 shows an alternative embodiment of the invention in which a boost voltage regulator  10 A includes a synchronous rectifier circuit that includes the composite transistor M 2  as the “high side” transistor and transistor M 1  as the “low side” transistor. In this case, Vin is applied by conductor  50  to a first terminal of inductor  6 , a second terminal of which is connected to conductor  51 . Conductor  51  is connected to the source electrodes of transistor sections M 2 - 1  and M 2 - 2  and also to the (+) input of comparator  120 . The (−) input of comparator  120  is connected by conductor  53  to the output Vout and to the drain electrodes of transistor sections M 2 - 1  and M 2 - 2 . Conductor  53  also is connected to the input of feedback control circuit  190 , which produces a signal on conductor  54  that is applied to the gate of transistor M 1 . The source of transistor M 1  is connected to ground conductor  3  and its drain is connected to conductor  51 . The feedback control circuit  190  produces several control signals on two-conductor bus  52 , which are applied to input of logic circuit  140 . Logic circuit  140  in FIG. 6 includes two level shifting driver circuits similar to driver circuit in FIG. 2 to produce adequate gate drive signals to the sections of composite transistor M 2 . The operation of boost regulator  10 A in FIG. 6 is quite similar to the operation of buck regulator  10  of FIG. 2, except that Vin is greater than Vout for buck regulator  10  of FIG. 2, whereas Vin is less than Vout for boost regulator  10 A of FIG.  6 . Preferably, comparator  120  in FIG. 6 has a built-in positive offset voltage in order to cause comparator  120  to accomplish its initial switching early rather than late, as previously explained. 
     While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make the various modifications to the described embodiments of the invention without departing from the true spirit and scope of the invention. It is intended that all elements or steps which are insubstantially different or perform substantially the same function in substantially the same way to achieve the same result as what is claimed are within the scope of the invention. 
     For example, composite transistor M 2  including the single common source electrode and the single common drain electrode and separate gate electrodes as shown in FIG. 2 could be replaced by two separate transistors M 2 - 1  and M 2 - 2  with their separate drains connected together and separate sources connected together as illustrated. Also, more than  2  segments of composite transistor M 2  could be provided, with their separate electrodes separately controlled by logic circuit  140 .