Abstract:
An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes: (1) at least two interfaces, (2) a programmable gate array (PGA) coupled to the at least two interfaces for communicating data therebetween and, optionally (3) a field-programmable gate array (FPGA) coupled to and configured to cooperate with the PGA to adapt the IC to a particular surrounding environment.

Description:
TECHNICAL FIELD OF THE INVENTION 
   The present invention is directed, in general, to programmable gate arrays (PGAs) and, more specifically, to an integrated circuit (IC) having an integrated PGA and optionally a field-programmable gate array (FPGA) and a method of manufacturing an IC that is suited for a particular application. 
   BACKGROUND OF THE INVENTION 
   Today&#39;s demand for ever-increasing bandwidth continues to push the limits of broadband packet network processors. Such processors interconnect optical fiber segments that make up the backbone of packet networks (such as the Internet) and are employed to switch data among the segments to route them rapidly through the network. As the data traverse the processors, they must be tracked and made to conform to various protocols. Accordingly, the processors themselves include hardware for tracking the data and translating them among the various protocols. This hardware includes serializer/deserializer crossconverters, forward error correctors, framers, mappers, traffic classification and management co-processors, network processors, control plane processors and backplane physical layer interfaces, and switch fabrics. 
   In practice, this hardware is implemented in application-specific integrated circuits (ASICs), application-specific standard product integrated circuits (ASSPs) or other integrated circuits (ICs). These ASICs, ASSPs and ICs must be coupled to one another to form the processor. 
   Unfortunately, coupling these circuits together has proven problematic. Interface mismatches occur when the signals that the circuits transmit or expect to receive are not identical. Interface mismatches also occur when transmit and receive speeds differ. 
   The conventional approach to addressing this problem has been to place a “bridge” between the circuits that are to be coupled to one another. Often, bridges are made from field-programmable gate arrays (FPGAs). Logic within the FPGA modifies or buffers data as necessary to provide the proper interface. Though they are flexible, FPGAs are expensive. Today&#39;s data rates are also becoming too great for FPGAs to handle. 
   ASICs can be used instead of FPGAs. The logic within the FPGAs can be effected within an ASIC, but time and money are required. Further hampering the adoption of ASICs is the fact that they are not readily modifiable should interface requirements change. 
   Accordingly, what is needed in the art is a new architecture that has at least some of the speed, size and cost advantages of ASICs, but the flexibility of FPGAs. 
   SUMMARY OF THE INVENTION 
   To address the above-discussed deficiencies of the prior art, the present invention provides an IC and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes: (1) at least two interfaces, (2) a PGA associated therewith and coupled to the at least two interfaces for communicating data therebetween and (3) an optional FPGA having a configuration memory and coupled to and configured to cooperate with the PGA to adapt the IC to a particular surrounding environment. 
   The present invention therefore introduces the broad concept of a hybrid IC containing a PGA, an FPGA or both, that effects communication of data with at least two interfaces on the IC. In an embodiment to be illustrated and described, the PGA is configured during IC fabrication with at least a portion of a design (perhaps including portions that require the PGA&#39;s superior speed of operation). The resulting IC offers to a designer both the pre-fabrication advantages of a PGA (speed, size, cost and initial configuration flexibility) and the post-fabrication advantages of an FPGA (continuing configuration flexibility). 
   In various embodiments of the present invention that will hereinafter be illustrated and described, the IC further includes a standard input-output interface, a second standard input-output interface, a block of embedded memory, a double data rate interface for access to external memory, a co-processor coupled to the embedded memory and a bus expander. 
   In one embodiment of the present invention, the at least two interfaces are selected from the group consisting of: (1) a system physical interface (SPI) and (2) a 10-Gigabit Attachment Unit Interface (XAUI). Those skilled in the pertinent art will understand, however, that other conventional or later-discovered interfaces are within the broad scope of the present invention. 
   The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  illustrates a block diagram of a line card containing a broadband packet network processor that forms an environment within which a PGA constructed according to the principles of the present invention can operate; 
       FIG. 2  illustrates a block diagram of an IC constructed according to the principles of the present invention; and 
       FIG. 3  illustrates a flow diagram of a method of manufacturing an IC suited for a particular application and carried out according to the principles of the present invention. 
   

   DETAILED DESCRIPTION 
   Referring initially to  FIG. 1 , illustrated is a block diagram of a line card containing a broadband packet network processor, generally designated  100 , that forms an environment within which the integrated circuit constructed according to the principles of the present invention can operate. 
   The processor  100  is illustrated as including serializer/deserializer (serdes)  110  coupled to a high-speed optical fiber interface  111  and/or low-speed communication lines  112 . The serdes  110  is coupled to a forward error corrector (FEC)  120  which is, in turn, coupled to a framer/mapper  130 . The framer/mapper  130  splits packets or cells into a payload stream and a control stream. The payload stream undergoes network processing in a processor  150 , while the control stream undergoes control processing in a processor  160 . 
   A traffic classification co-processor  170  and traffic management co-processor  180  cooperate to manage traffic within the processor  100 . A backplane physical layer (PHY) interface  190  communicates with a switch fabric  191  via a backplane connector  192 . 
   The IC of the present invention finds advantageous use in several exemplary locations within the processor  100 . The IC may be used to intermediate between the FEC  120  and the framer/mapper  130 , between the framer/mapper  130  and the traffic classification co-processor  170 , between the traffic classification co-processor  170  and the traffic management co-processor  180 , between the traffic management co-processor  180  and the backplane PHY interface  190  and between the traffic classification co-processor  170  and the processor  150 . Each of these locations within the processor  100  is subject to interface mismatches and represents a different environment within which an IC constructed according to the principles of the present invention must operate. 
   Turning now to  FIG. 2 , illustrated is a block diagram of an IC constructed according to the principles of the present invention. The IC, generally designated  200 , is formed on a single substrate (which, in the illustrated embodiment, includes silicon) and contains several functional blocks (or “macrocells”) which cooperate together to perform a desired function, which is bridging external circuits such as those called out with reference to FIG. 
   The IC  200  includes at least two interfaces  210 ,  220  which are illustrated as being SPI-4 interfaces, but which may be any suitable conventional type (such as an XAUI interface) or later-discovered type. A PGA  250  is coupled to the at least two interfaces  210 ,  220  to effect the communication of data between the at least two interfaces  210 ,  220 . 
   A PGA  250  is illustrated as being coupled to the FPGA  230 . The PGA  250  is configured to cooperate with the FPGA  230  to adapt the IC  200  to a particular surrounding environment (including the external circuits that the IC  200  is called upon to bridge). The manner in which this cooperation comes about will be set forth in greater detail with respect to  FIG. 3  herein. 
   Other functional blocks are also illustrated as being in the IC  200  of  FIG. 2 . A standard input-output interface  260  is coupled to the PGA  250 . The interface  260  may provide, for example, a 10 gigabit path to and from the IC  200 , perhaps for control purposes. A memory interface  270  is coupled to the configuration memory  240 . The memory interface  270  is illustrated as being a double data rate (DDR) interface, but may be any suitable type. The memory interface  270  provides access to memory (such as synchronous dynamic random access memory, or SDRAM,  271  or flash memory  272 ) that is external to the IC  200  and supplements the embedded memory  240 . 
   A co-processor  280  is illustrated as being coupled to the embedded memory  240 . The co-processor  280  may be employed to assist the PGA  250  in certain tasks, as those skilled in the pertinent art will understand. The co-processor  280  may be an advanced reduced instruction set computer (RISC) machine (ARM), but may be of any other suitable type. The co-processor  280  may be of a Harvard architecture and therefore may have a separate instruction cache memory  281  and data cache memory  282  to increase its performance. 
   A bus expander  290  is illustrated as being coupled to the PGA  250 . The bus expander  290  advantageously allows the IC  200  to be coupled to other ICs, perhaps of the same type. The coupling together of multiple ICs can yield a bridge having substantial processing power. 
   Those skilled in the art should understand that the FPGA  230 , the standard input-output interface  260 , the memory interface  270 , the SDRAM  271 , the co-processor  280 , the instruction cache memory  281 , the data cache memory  282  and the bus expander  290  are optional and may be eliminated or substituted for in whole or in part by other functional blocks as a particular application may find advantageous. 
   In the illustrated embodiment, the PGA  250  is transparent to the person who is configuring the FPGA. As far as the person is concerned, he is configuring a conventional FPGA. Portions of the configuration he designs may call upon functions embedded in the PGA. Those portions should be carried out substantially faster in the PGA than in the FPGA, but otherwise the person need not change his design methodology to accommodate the PGA. Of course, this need not be the case, and the person may be given programmatical access to the PGA&#39;s functions. 
   Though the IC  200  is illustrated in general terms, one embodiment may employ a 250K gate FPGA operating at 156 MHz, a 2 Mb, 16 block memory and a 250K gate PGA operating at 166 MHZ. 
   In understanding the principles and advantages of the present invention, it is helpful to describe the process by which an IC is manufactured. Accordingly, turning now to  FIG. 3 , illustrated is an exemplary method, generally designated  300 , of manufacturing an IC suited for a particular application and carried out according to the principles of the present invention. 
   The method begins in a start step  305 , wherein a customer wants to create a PGA/FPGA-based IC that is adapted to bridge two external circuits between which an interface mismatch exists. It is further assumed that a pure FPGA IC would not be adequate to bridge the external circuits due to its speed limitations. 
   In a step  310 , a circuit designer (not shown) designs a circuit that bridges the two external circuits. The circuit designer may use a high-level hardware description language (HDL) or any other conventional or later-discovered methodology in designing such IC. 
   Part of the process of designing the PGA/FPGA IC is generating (in a step  315 ) a specification describing the configuration that the PGA is to assume. This specification may take the form of a well-known netlist or any other conventional or later-discovered methodology. Even programming languages, such as C, may be employed to generate specifications. Once the netlist or other specification is developed, it is provided, in a step  320 , to an IC fabricator. 
   Having received the PGA configuration from the customer, the IC fabricator employs a standard set of reticles it has on hand to fabricate an IC having at least two interfaces, an FPGA (optional) with associated memory and PGA cells in a step  330 . Then, employing an interconnect reticle made specifically for the customer to effect the PGA configuration specified in the specification, the PGA cells are interconnected in a step  335 . 
   The customer then places the IC in an actual operating environment or a test apparatus that simulates the actual operating environment in a step  345 . The IC is tested and its efficacy determined in a decisional step  350 . If the IC tests are positive (YES branch of the decisional step  350 ), the IC may be placed in full production in a step  355 . 
   If the IC tests are negative (NO branch of the decisional step  350 ), certain changes may be required in a step  360 . The PGA configuration can be redesigned and updated ICs fabricated (represented by the broken line coupling the step  360  to the step  315 ). 
   Given the efficiency of this design process, a fully functional IC suitable for full production should result with few, if any, design iterations. Further, from the IC fabricator&#39;s standpoint, the standard set of reticles it has on hand to fabricate the interfaces, PGA cells and FPGA can be used repeatedly to form ICs having a wide variety of functions, including bridging. 
   Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form. In particular, the IC  200  of  FIG. 2  need not include the FPGA  230  or the co-processor  280 , which are optional.