Abstract:
A data packet switching node that temporarily stores data packets received from at least one source network adapter and transmits them to at least one destination network adapter comprises a data packet flow control system to control the data packet flow. The data packet flow control system comprises identifier to determine the at least one destination adapter of each received data packet. Then, means coupled to the storage allow computing a data packet flow value representing the traffic for the at least one destination adapter. The data packet flow value is transmitted simultaneously to the at least one source network adapter and to the at least one destination network adapter each time a data packet for the at least one destination network adapter is stored into the storage.

Description:
TECHNICAL FIELD  
         [0001]    The present invention relates to the flow control of data packets transmitted between Local Area Networks (LAN) interconnected by a switch engine.  
         BACKGROUND ART  
         [0002]    Local Area Networks (LAN) such as Ethernet or token-ring networks, are generally interconnected through hubs. The hub is a system made of LAN adapters that communicate together through a switch card. The switch card is mainly composed of input ports, output ports and a shared memory switch engine.  
           [0003]    The data packets received by the input ports are stored into the shared memory at address locations determined by queues containing the packet destination addresses. The packets are de-queued to be transmitted to the destination output ports.  
           [0004]    The shared memory having a limited size, a flow control mechanism is generally implemented to control the data packet transfer between each adapter card and the switch engine. Flow control mechanisms are often based on thresholds. The shared memory has a maximum threshold and a minimum threshold. When the number of data packets stored into the shared memory reaches the max. threshold, the switch engine asks the adapter card to stop sending data packets. When the number of data packets stored into the shared memory reaches the min threshold, the switch engine asks the adapter card to resume the transmission of data packets. Drawback of such mechanism is that it is a binary control which operates as ‘do transmit’ or ‘do not transmit’, thereby leading to interrupt and resume the data flow.  
           [0005]    Therefore, there is a need to have a flow control system wherein the transmission from the adapter cards is never stopped. The present invention offers such solution.  
         SUMMARY OF THE INVENTION  
         [0006]    Accordingly, it is an object of the invention to provide a smooth flow control mechanism between adapter cards and a switch engine.  
           [0007]    It is another object to provide a flow control system having less latency between the adapter cards and the switch engine.  
           [0008]    It is yet another object of the invention to offer an optimal use of the shared memory of the switch engine.  
           [0009]    In a preferred embodiment, the invention relates to a data transmission system comprising a plurality of Local Area Networks (LANs) interconnected by several hubs. Each hub contains a Control Point card, a plurality of adapter cards connected to the Local Area Networks and a switching system made of two switch cards, one being active and the other being backup.  
           [0010]    Each data packet transmitted by any adapter card to the switch engine includes a header containing at least the address of the adapter card to which the data packet is forwarded.  
           [0011]    The system of the invention operates both in the switch engine and the adapter cards. It comprises a flow control circuitry associated to the shared memory where the data packets are stored. The flow control circuitry operates between each adapter card and the active switch card.  
           [0012]    In a preferred embodiment, a data packet switching node that temporarily stores data packets received from at least one source network adapter and transmits them to at least one destination network adapter comprises a data packet flow control system to control the data packet flow. The data packet flow control system is characterized in that it comprises:  
           [0013]    identifier means to determine the at least one destination adapter of each received data packet;  
           [0014]    means coupled to the storing means for computing a data packet flow value representing the traffic for the at least one destination adapter; and  
           [0015]    means coupled to the identifier means and to the computing means for transmitting the computed data packet flow value simultaneously to the at least one source network adapter and to the at least one destination network adapter each time a data packet for the at least one destination network adapter is stored into the storing means. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    The above and other objects, features and advantages of the invention will be better understood by reading the following more particular description of the invention in conjunction with the accompanying drawings wherein:  
         [0017]    [0017]FIG. 1 is a schematic diagram of a data transmission system including four LANs interconnected by a hub according to the principles of the invention;  
         [0018]    [0018]FIG. 2 is a schematic diagram of the switch card of FIG. 1;  
         [0019]    [0019]FIG. 3 details the Lease Address Selector block of FIG. 2;  
         [0020]    [0020]FIG. 4 details the Release Address Selector block of FIG. 2;  
         [0021]    [0021]FIG. 5 details the Flow Control Logic of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0022]    The invention is preferably implemented in a data transmission environment as illustrated on FIG. 1. For sake of simplicity, the environment is made of four Local Area Networks (LAN)  10 _ 1 ,  10 _ 2 ,  10 _ 3 , and  10 _ 4  but it could be extended to a plurality of LANs and as such a LAN is also denoted  10 _i in the description. LANs  10 -i are interconnected together by a hub  12 , and may be of the type ATM, Ethernet, or token-ring. Each LAN is connected to a switching system  14  within the hub  12  by means of a respective adapter card  16 _ 1  for LAN  10 _ 1 , adapter card  16 _ 2  for LAN  10 _ 2 , adapter card  16 _ 3  for LAN  10 _ 3  and adapter card  16 _ 4  for LAN  10 _ 4 . Each adapter card (also denoted  16 _i) sends data packets by means of a data bus-in (bus-in  13 _ 1  to bus-in  13 _ 4 ) connected to input ports of the switching system  14 . Each adapter card receives data packets by means of a data bus-out (bus-out  15 _ 1  to bus-out  15 _ 4 ) connected to output ports of the switching system  14 . Then, a data bus-in  13 _i carries data packets from the respective adapter card  16 _i to switching system  14  and data bus-out ( 15 _i) carries data packets from switching system  14  to the adapter card  16 _i. Each adapter card also receives flow control information from the switching system  14  by means of a serial interface  17 . Then, a serial signal  17  carries flow control information from the switching system  14  to the respective adapter card  16 _i. The switching system  14  is made of two distinct switch cards, an active switch card  14 _ 1  and a backup switch card  14 _ 2 . The invention is located within each switch card but for the ease of description, let&#39;s only describe the active switch card  14 _ 1 .  
         [0023]    Referring now to FIG. 2, the invention is described as part of the switch card  14 _ 1 . For the ease of comprehension, let&#39;s describe the transmission of a data packet from adapter card  16 _ 1  on data bus-in  13 _ 1  to adapter card  16 _ 2  on data bus-out  15 _ 2 . It is to be easily understood that adapter cards  16 _ 1  and  16 _ 2  are only taken as example. In the preferred embodiment, the switch card is mainly composed of:  
         [0024]    a Shared Memory  250 ;  
         [0025]    a Header Detection and Packet Validation block  100 _ 1 ;  
         [0026]    a Memory Write entity made of:  
         [0027]    an En-queue Register block  380 _ 1 ,  
         [0028]    a Lease Address Selector block  350 ,  
         [0029]    a Memory Write Controller block  150 ;  
         [0030]    a Memory Read entity made of:  
         [0031]    a De-queue Destination FIFO block  310 _ 2 ,  
         [0032]    a Release Address Selector block  300 ,  
         [0033]    a Memory Read Controller block  200 ,  
         [0034]    a Destination Output Buffer block  280 _ 2 ;  
         [0035]    a Free Buffer Queue block  400 ;  
         [0036]    a Flow Control block  450 .  
         [0037]    The structure and operation of the different blocks are now described.  
         [0038]    Shared Memory ( 250 )  
         [0039]    The Shared Memory receives data packets from adapter card  16 _ 1  on data bus-in  13 _ 1  and transmits them to adapter card  16 _ 2  on data bus-out  15 _ 2  through the Destination Output Buffer block  280 _ 2 . The write operation is controlled by bus  160  and the read operation by bus  210 .  
         [0040]    Header Detection and Packet Validation ( 100 _ 1 ):  
         [0041]    Generally, a data packet is made of a header and a payload. The header contains information such as a destination address, a priority level, and the payload contains the data.  
         [0042]    The Header Detection and Packet Validation block  100 _ 1  receives data packets from adapter card  16 _ 1  through data bus-in  13 _ 1 . When a valid data packet is detected the destination address is extracted and generated on bus  140 _ 1 . In addition, a write enable signal  130 _ 1  is activated.  
         [0043]    Memory Write Entity:  
         [0044]    The Memory Write Entity is made of an En-queue Register block  380 _ 1 , a Lease Address Selector block  350  and a Memory Write Controller block  150 .  
         [0045]    To detail more each task:  
         [0046]    The En-queue Priority Register block  380 _ 1  contains the address where to store an incoming data packet. The address comes from the Free Buffer Queue block  400  through bus  410 . The output bus  370 _ 1  is connected to the Lease Address Selector block  350 .  
         [0047]    The Lease Address Selector block  350  for destination adapter  16 _ 2  is illustrated in FIG. 3. Its function is to transfer the address stored into En-queue Register block  380 _ 1  onto bus  360  through the buffer block  351 . The destination address of the incoming data packet is received on bus  140  by the Destination Decoder block  330  which decodes and activates the corresponding destination chip select signal  360 _ 2 . This chip select signal is carried out to Flow Control block  450  and to the De-queue Destination write FIFO input.  
         [0048]    The Memory Write Controller block  150  controls the Shared Memory block  250  through bus  160 . The write address comes from bus  360  and the write command comes from signal  130 _ 1 .  
         [0049]    Memory Read Entity:  
         [0050]    The Memory Read Entity is made of a De-queue FIFO block  310 _ 2 , a Release Address Selector block  300  and a Memory Read Controller block  200 .  
         [0051]    To detail more each task:  
         [0052]    The De-queue Destination FIFO block  310 _ 2  contains the addresses of incoming data packets that have been stored for a transmission to adapter  16 _ 2 . The input interface is made of an input FIFO data bus connected to the address bus  360  and an input FIFO write signal connected to the destination chip select signal  360 _ 2 . The output interface is made of an output FIFO data bus  320  and an input FIFO read signal  320 _ 2 , both being connected to the Release Address Selector block  300 .  
         [0053]    The Release Address Selector block  300  for destination adapter  16 _ 2  is illustrated in FIG. 4. Its function is to de-queue and release memory read addresses. A State Machine  301  controls the address de-queue in a round-robin fashion from adapter  16 _ 1  to adapter  16 _ 4 . For sake of simplicity, only destination adapter  16 _ 2  is described. A Comparator block  330 _ 2  and a Buffer block  340 _ 2  are connected to the output FIFO data bus  320 . The output bus of the buffer is connected to the Memory Read Controller block  200  through bus  220 . The State Machine  301  receives the output control signal of Comparator block  330 _ 2  on signal  301 _ 2  and generates a De-queue Destination read FIFO signal  320 _ 2  and a memory read signal  270 _ 2 . The read signal is connected to the Memory Read Controller block  200 , the Destination Output Buffer block  280 _ 2  and the Flow Control block  450 . The State Machine  301  is clocked by the outgoing data packet clock received on signal  301 _ 5 . The Release Address Selector block  300  performs the following tasks:  
         [0054]    reads the De-queue Destination FIFO of adapter  16 _ 2  by activating signal  320 _ 2 ,  
         [0055]    compares its content to zero which is the default value when the FIFO is empty,  
         [0056]    if the control signal  301 _ 2  is activated, performs a memory read operation and release the address into the Free Buffer Queue block  400 ; if the control signal  301 _ 2  is not activated reads the De-queue Destination FIFO of next adapter.  
         [0057]    The Memory Read Controller block  200  controls the Shared Memory block  250  through bus  210 . The read address comes from bus  220  and the read command comes from signal  270 _ 2 . The data packet is transmitted from the memory to adapter  16 _ 2  through the Destination Output Buffer block  280 _ 2  on bus  15 _ 2 .  
         [0058]    Free Buffer Oueue block ( 400 ):  
         [0059]    The Free Buffer Queue block  400  contains memory addresses ready to be used. Its output bus  410  provides addresses to the En-queue Register for memory write operations. Its input bus  220  receives addresses from the Release Address Selector block  300  when a memory read operation has been completed.  
         [0060]    Referring now to FIG. 5, the Flow Control block  450  for destination adapter  16 _ 2  is mainly composed of:  
         [0061]    a Microprocessor Interface block  25 ;  
         [0062]    a flow control logic per adapter made of:  
         [0063]    a Threshold Register block  31 _ 2 ,  
         [0064]    a Counter/De counter block  41 _ 2 ,  
         [0065]    a Substract Logic block  51 _ 2   
         [0066]    an ID register block  61 _ 2 ;  
         [0067]    a Serializer block  70 .  
         [0068]    The structure and operating of the different blocks are now described.  
         [0069]    Microprocessor Interface ( 25 ):  
         [0070]    The microprocessor interface block  25  is connected to the Control Point card  21  through bus  20 . The interface allows the user to access the Threshold register block  31 _ 2  in order to predefined a threshold value.  
         [0071]    Flow Control Logic:  
         [0072]    It is made of a Threshold register block  31 _ 2 , a Counter/De counter block  41 _ 2 , a Substract logic block  51 _ 2  and an ID register block  61 _ 2 .  
         [0073]    To detail more each task:  
         [0074]    a. The Threshold register is programmed through the microprocessor interface by the user which access the Control Point card. Its output bus  32 _ 2  is connected to a first port ‘A’ of the Substract logic block  51 _ 2 .  
         [0075]    b. The Counter block is incremented each time a data packet is stored into the shared memory  250  and is decremented each time a data packet is read from the shared memory. An increment input signal is connected to the Lease Address Selector block  350  through signal  360 _ 2 . A decrement input signal is connected to the Release Address Selector block  300  through signal  270 _ 2 . The Counter/De counter data bus  42 _ 2  is connected to a second port ‘B’ of the Substract logic block  51 _ 2 .  
         [0076]    c. The Substract combinatorial logic block  51 _ 2  always computes on the fly the difference between the two input ports ‘A-B’. The result is only transmitted to serializer  70  onto bus  71  when signal  270 _ 2  is activated which means each time a data packet for adapter  16 _ 2  is stored into shared memory  250 . The result represents the flow control information to be transmitted to the adapter cards. When the result is close to the predefined threshold value, this means that the traffic to the respective adapter is very low; when the result is close to zero, this means that the traffic to the respective adapter is heavy. The result is sent to all the adapters connected to the switch and when the flow control information is received by each adapter, each one may take appropriate action to adapt its traffic. As an example let&#39;s assume that there is no traffic at all in the switch and therefore the shared memory block  250  stores and transmits the data packets only to adapter  16 _ 2 . In this case the counter/de counter is equal to zero and each adapter receives the threshold value as the flow control information for adapter  16 _ 2 . This means that adapter  16 _ 2  is receiving data packets without any congestion. Now, let&#39;s assume that there is a high priority traffic going on in the switch with adapter  16 _ 3 . The counter block  41 _ 2  is incremented each time a data packet is stored for adapter  16 _ 2  but will not be decremented until the traffic for adapter  16 _ 3  reduces. Therefore each adapter receives from the Substract logic a flow control information going to zero. This means that adapter  16 _ 2  is not receiving data packets already sent. Therefore all adapters that want to transmit data packets to adapter  16 _ 2  should reduce their traffic until the flow control information reaches again the threshold value. To recall, the present system allows a dynamic picture of the use of the shared memory of the switch engine and provides a real time information to the whole adapter cards communicating with the switch engine.  
         [0077]    ID Register ( 61 _ 2 ):  
         [0078]    The ID Register block  61 _ 2  provides the address of the destination adapter. In a preferred embodiment, this address is hardwired on the board on 2 bits. As an alternative, the address should be programmed from the Control Point through the microprocessor interface.  
         [0079]    Serializer ( 70 ):  
         [0080]    The serializer block  70  receives a parallel bus  71  made of 10 bits,  8  flow control bits which come from the substract logic block  51 _ 2  and  2  ID bits which come from the ID Register block  61 _ 2 . Each read access to the shared memory block  250  for adapter  16 _ 2  activates the control signal  270 _ 2  which then starts the serializer. The transmission begins with the ID bits followed by the flow control bits. This information is received by each adapter card in the hub through the serial link  17 .  
         [0081]    The principle of operation of the system is now detailed as previously explained with adapter  16 _ 1  transmitting a data packet to adapter  16 _ 2 . Adapter  16 _ 1  first builds in a conventional manner a data packet and sends it to the switch card  14  onto data bus-in  13 _ 1 . Next, the data packet is routed by the switch card using the routing index information contained in its header. Then the data packet is transmitted to the destination adapter  16 _ 2  on data bus-out  15 _ 2 . In parallel with the transmission of the data packet, the flow control information is sent to all the adapters  16 _i through corresponding serial links  17 .  
         [0082]    The incoming data packet is analyzed by the Header Detection and Packet Validation block  100 _ 1  which performs the following tasks:  
         [0083]    sending the data packet destination address (port #2 in the description) to the Lease Address Selector block  350  through bus  140 ;  
         [0084]    informing the Write Memory Controller block  150  through signal  130 _ 1  to perform a write operation.  
         [0085]    Next the Lease Address Selector block  350  performs the following tasks:  
         [0086]    decoding the data packet destination address and activating the corresponding chip select signal  360 _ 2 ;  
         [0087]    enabling the buffer block  351  to transmit the address stored into the En-queue Register block  380 _ 1  to the Write Memory Controller block  150 . This address was previously taken from the Free Buffer Queue block  400 ;  
         [0088]    storing this address into De-queue Destination FIFO block  310 _ 2 ;  
         [0089]    transferring the active chip select signal  360 _ 2  to the Flow Control block  450  to increment counter block  41 _ 2 .  
         [0090]    Finally the Write Memory Controller block  150  stores the data packet into the Shared Memory block  250 .  
         [0091]    As a background task, the Release Address Selector block  300  performs the following operations:  
         [0092]    reading the De-queue Destination FIFO of adapter  16 _ 2  by activating signal  320 _ 2 ;  
         [0093]    comparing its content to zero which is the default value when the FIFO is empty;  
         [0094]    if the control signal  301 _ 2  is not activated, reading the De-queue Destination FIFO of next adapter;  
         [0095]    if the control signal  301 _ 2  is activated, performing a memory read operation and releasing the address into the Free Buffer Queue block  400  for further use.  
         [0096]    The Read Memory Controller block  200  controls the Shared Memory block  250  through bus  210 . The read address comes from bus  220  and the read command comes from signal  270 _ 2 . The data packet is transmitted from the memory to adapter  16 _ 2  through the Destination Output Buffer block  280 _ 2  on bus  15 _ 2 .  
         [0097]    While the data packet is transmitted to adapter  16 _ 2  the Flow Control block  450  transmits the flow control information to all adapters on serial link  17 .  
         [0098]    The counter is incremented when a data packet is stored into the shared memory  250  and decremented when a data packet is read. The content of the counter/de counter is subtracted to the threshold value defined by the user at the initialization time. The result represents the flow control information: when the value is close to the threshold value the traffic to the adapter  16 _ 2  is very low, when the value is close to zero the traffic to the adapter  16 _ 2  is heavy. This value along with the destination adapter address are serialized by Serializer block  70  and send to each adapter card in the hub.