Abstract:
A method for synchronizing operation of a heart assist pump device to a patient&#39;s cardiac cycle includes obtaining a signal from a motor of a heart assist pump device and filtering the signal to remove noise. The method also includes determining a speed synchronization start point at which time the motor of the heart assist pump device will begin a change in speed of operation based on the filtered signal. The method further includes modulating a speed of the motor of the heart assist pump device to a target speed at the speed synchronization start point, thereby synchronizing the change in speed of operation with a patient&#39;s cardiac cycle.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority to U.S. Provisional Application No. 62/114,886, filed Feb. 11, 2015 and entitled “HEART BEAT IDENTIFICATION AND PUMP SPEED SYNCHRONIZATION.” This application is also related to co-pending and commonly assigned U.S. patent application Ser. No. 13/873,551, filed Apr. 30, 2013, and entitled “CARDIAC PUMP WITH SPEED ADAPTED FOR VENTRICLE UNLOADING.” These Applications are incorporated by reference herein in their entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    A left ventricular assist device (LVAD) and/or other devices may be used to provide long-term support for heart failure patients or patients suffering from other heart related conditions. Traditionally, many such devices assist heart functioning by generating a continuous blood flow using a constant pumping speed set by clinician based on the patient&#39;s physiologic conditions at that time when the particular device is implanted. 
         [0003]    However, the natural cardiac cycle of a human being (or other animals) does not usually generate a continuous and constant blood flow. Instead, flow is highest during the systole of a cardiac cycle, and then decreased during the diastole of the cardiac cycle. Thus the heart and the implanted device operate in different fashions (i.e., non-constant versus constant flow) which may be detrimental to the patient. 
         [0004]    Embodiments of the present invention provide systems and methods for determining characteristics of a cardiac cycle, so that operation of LVAD and/or other devices may be altered in a dynamic manner when used in a human or other animal experiencing heart related conditions. 
       BRIEF SUMMARY OF THE INVENTION 
       [0005]    In one aspect, a method for synchronizing operation of a heart assist pump device to a patient&#39;s cardiac cycle is provided. The method may include obtaining a signal from a motor of a heart assist pump device and filtering the signal to remove noise. The method may also include determining a speed synchronization start point at which time the motor of the heart assist pump device will begin a change in speed of operation based on the filtered signal. The method may further include modulating a speed of the motor of the heart assist pump device to a target speed at the speed synchronization start point, thereby synchronizing the change in speed of operation with a patient&#39;s cardiac cycle. 
         [0006]    In another aspect, a heart assist pump device is provided. The device may include a motor and a controller. The controller may be configured to obtain frequency range data from the motor and to determine a speed synchronization start point at which time the motor of the heart assist pump device will begin a change in speed of operation based on the frequency range data. The controller may also be configured to modulate a speed of the motor to a target speed at the speed synchronization start point, thereby synchronizing the change in speed of operation with a patient&#39;s cardiac cycle. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The present invention is described in conjunction with the appended figures: 
           [0008]      FIG. 1  shows a top level block diagram of a LVAD pump control system of one embodiment of the invention; 
           [0009]      FIG. 2  shows one speed modulation architecture of one embodiment of the invention; 
           [0010]      FIG. 3  shows one method of identifying a pulse period of a heart beat of one embodiment of the invention; 
           [0011]      FIG. 4  motor data converted to heart beat information and various characteristics thereof pertinent to methods and system of the invention; and 
           [0012]      FIG. 5  is a block diagram of an exemplary computer system capable of being used in at least some portion of the apparatuses or systems of the present invention, or implementing at least some portion of the methods of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0013]    The ensuing description provides exemplary embodiments only, and is not intended to limit the scope, applicability or configuration of the disclosure. Rather, the ensuing description of the exemplary embodiments will provide those skilled in the art with an enabling description for implementing one or more exemplary embodiments. It being understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the invention as set forth herein. 
         [0014]    Specific details are given in the following description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, with regard to any specific embodiment discussed herein, any one or more details may or may not be present in all versions of that embodiment. Likewise, any detail from one embodiment may or may not be present in any particular version of another embodiment discussed herein. Additionally, well-known circuits, systems, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments. The absence of discussion of any particular element with regard to any embodiment herein shall be construed to be an implicit contemplation by the disclosure of the absence of that element in any particular version of that or any other embodiment discussed herein. 
         [0015]    Also, it is noted that individual embodiments may be described as a process which is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process may be terminated when its operations are completed, but could have additional steps not discussed or included in a figure. Furthermore, not all operations in any particularly described process may occur in all embodiments. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination corresponds to a return of the function to the calling function or the main function. 
         [0016]    The term “machine-readable medium” includes, but is not limited to portable or fixed storage devices, optical storage devices, wireless channels and various other mediums capable of storing, containing or carrying instructions and/or data. A code segment or machine-executable instructions may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and/or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc. 
         [0017]    Furthermore, embodiments of the invention may be implemented, at least in part, either manually or automatically. Manual or automatic implementations may be executed, or at least assisted, through the use of machines, hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine readable medium. One or more processors may perform the necessary tasks. 
         [0018]    In some embodiments, a left ventricular assist device (LVAD) or other device may be intended to provide the long-term support for a heart failure patient or a patient suffering from another condition. Many such devices generate a continuous blood flow using a constant pumping speed set by clinician or other process based on the patient&#39;s physiologic conditions at that time when such device is implanted. However, there is the potential to vary the speed of the device to be synchronized to the natural cardiac cycle by modulating the speed based on the natural cardiac cycle. Using this approach, the pump speed is increased during systole of a cardiac cycle (the time of highest flow) and decreased during diastole (the time of lowest flow), so that a maximum unloading of a weakened ventricle may be obtained. This may establish stable hemodynamic conditions and enables a variation of the aortic pulse pressure, while keeping the organ perfusion at an even level to benefit the patient&#39;s recovery. Although the heart is weakened, it is still beating. The LVAD may support the beating heart such that when the heart pumps the resistance met by the pump goes down and vice versa. This would be seen as a change in the back emf and current. In some embodiments, the change in current may depend on the control scheme. For example, the LVAD may be designed to maintain a set motor speed (rpm). The current needed to maintain the speed goes down during pumping (systole). In other embodiments, the LVAD may be designed to maintain a set flow rate, causing the current to go down during systole. It will be appreciated that the LVAD could be designed to just apply a set current, in which case it doesn&#39;t matter what the heart is doing. The flow rate will then go up when the pump and heart are pushing fluid at the same time. 
         [0019]    In some embodiments the pump speed of a LVAD or other device may be precisely synchronized to the systolic phases of the cardiac cycle in a reliable real-time mode regardless of the irregular heart beats. This may prevent a lack of synchrony which may cause ventricular load fluctuation or even overloading of the heart which can increase the occurrence of adverse events and affect the recovery of the patient. Unsynchronized increases in pump speed could also increase the risk of ventricular suction, particularly at the end of systole when the ventricle could be nearly empty. Embodiments of the invention reduce such risks by properly identifying regular heart beats and the proper time to increase pump speed relative thereto. 
         [0020]    Embodiments of the invention implement real-time speed modulation to at least more precisely synchronize LVAD pumps or other devices with the heart beat cycle that allow for increasing the pump speed before the systolic phase and reducing the speed before the end of systole.  FIG. 1  shows a top level block diagram of a LVAD pump control system (or control system for other device) with speed modulation. In this control system, motor drive current or power signal is used as the input of the speed modulation since it reflects the heart beat cycle pattern. By extracting the motor drive current or power signal features, speed synchronization time points within the heart beat cycles can be determined. Based on the speed synchronization time points, the speed set-point configured by clinician or other method can be modulated to the targeted speed reference automatically at the right time for a motor drive of a pump or other device to achieve the required synchronicity. 
         [0021]    The architecture of speed modulation is shown in  FIG. 2  which consists of three main stages: 
         [0022]    Stage  1 —Data Processing—A filter is employed to obtain reasonable frequency range data from the raw motor current or power signal data which is concurrent with, and representative of, the heart beat cycle. 
         [0023]    Stage  2 —Heart Beat Pulse Identification—The heart beat cycle features are identified from the filtered motor current or power data from Stage  1  to determines the speed synchronization start time point (i.e., the point in time in which the pump speed should increase). 
         [0024]    Stage  3 —Speed Synchronization and Ramp Control—Based on the speed synchronization start point identified in Stage  2 , a pump motor is controlled to synchronize speed increases thereof with heart beats. A targeted speed reference for the motor drive, with ramp up and down control, is specified by a clinician or other method. 
         [0025]    At Stage  1 , high frequency noise data which is out of the general heart beat range (i.e. less than 5 Hz (300 beats/min)) is filtered out of the motor current or power data. Any kind of digital filter, for example, an infinite impulse response filter (IIR) or finite impulse response filter (FIR), may be employed, but the phase delay and computational load may need to be considered when implemented it into an embedded LVAD controller. In one embodiment, a second order IIR is employed. 
         [0026]    At Stage  2 , the pulse period of heart beat is identified from the filtered motor current or power data from Stage  1 . In some embodiments, at least two consecutive and complete prior-occurring heart beats may be analyzed to anticipate the current heart beat cycle features. In other embodiments, the two complete prior-occurring heart beats may not be consecutive, or more than two complete prior-occurring heart beats may be analyzed, either consecutive or non-consecutive. In some embodiments, more than two complete prior-occurring heart beats may be analyzed. For example, three, four, five, or any specific number of heart beats greater than five may be analyzed depending on the embodiment. However, using more than the last two consecutive and complete prior-occurring heart beats may involve older heart beat history data which may include irregular heart beats or inconsistent data, thereby reducing the accuracy of the predicted current heart beats cycle features. 
         [0027]    Stage  2  involves three separate steps as shown in  FIG. 3 : 
         [0028]    Step  1 —Determine if each pulse is complete—To determine if a pulse is complete, characteristics of the pulse may first be determined from the data provided from Stage  1 . Those characteristics may include the following (see  FIG. 4  for reference):
       The mean amplitude value from the previous three or more pulses   The maximum amplitude value from the pulse to be analyzed   The minimum amplitude value from the pulse to be analyzed   The first falling-crossing time (t f ) which is the point at which the pulse first crosses the mean value on the downslope   The first rising-crossing time (t r ) which is the point at which the pulse crosses the mean value on the upslope   The second falling-crossing time (t f ) which is the point at which the pulse crosses the mean value on the downslope for a second time   The minimum peak time point (t min ) for the minimum amplitude value   The maximum peak time point (t max ) for the maximum amplitude value       
 
         [0037]    The following rules are then used to determine if two consecutive prior pulses are complete pulses. Both rules must be satisfied to allow the two pulses to be used as a reference for Step  2  of the process which determines the heart beat cycle period. 
         [0038]    Rule 1: The amplitude difference between the maximum amplitude and the mean amplitude must satisfy the following: 
         [0000]      c 1 Diff max2Min [i]&lt;Diff max2Mean [i]&lt;c 2 Diff max2Min [i] 
         [0039]    Where,
       Diff max2Mean [i]=the difference between maximum amplitude and mean data at pulse[i];   Diff max2Min [i]=the difference between maximum and minimum amplitude at pulse[i]; and   c 1 , c 2  are two constant coefficients.       
 
         [0043]    In one embodiment c 1 =0.375 and c 2 =0.75, though in other embodiments other values of c 1  and c 2  may be possible. 
         [0044]    Rule 2: The four pulse periods from different time points must satisfy the following: 
         [0000]      T cyc   _   min &lt;{T f2f [i], T r2r [i], T min2min [i]. T max2max [i]}&lt;T cyc   _   max    
         [0045]    Where,
       T f2f [i]=A pulse period from the last falling-crossing time point to current falling-crossing time point;   T r2r [i]=A pulse period from the last rising-crossing time point to current rising-crossing time point;   T min2min [i]=A pulse period from the last minimum time point to current minimum time point;   T max2max [i]=A pulse period from the last maximum time point to current maximum time point; and   T cyc   _   min , T cyc   _   max  are the limitations of a pulse period of heart beat.       
 
         [0051]    In one embodiment T cyc   _   min =0.3 seconds (200 beats/min), T cyc   _   max =1.25 seconds (48 beats/min), though in other embodiments other values of T cyc   _   min  and T cyc   _   max  may be possible. 
         [0052]    If these rules are not satisfied for two prior consecutive pulses, then such pulses are not adjudged to be complete pulses and pulses prior to the non-complete pulses are then analyzed until two prior consecutive complete pulse are located. Step  2  is then commenced based on such pulses. 
         [0053]    Step  2 —Determine the pulse period—To determine the pulse period the median value of the previously discussed four pulse periods is determined per the below: 
         [0000]      T cyc [i]=Median{T f2f [i], T r2r [i], T min2min [i], T max2max [i]} 
         [0054]    Step  3 —Calculate initial speed synchronization start point—There are at least four possible ways to determine an initial speed synchronization start point t sync [0]) as shown in the below table. In the case where two conditions of different cases in the table are indicated as being equally applicable (for example, under Case 1 and Case 2, the difference between T max2max [i] and T cyc [i] is equal to the difference between T min2min [i] and T cyc [i]), the lower number Case has priority and is employed (in the example, Case 1, instead of Case 2). 

 
         [0055]    After completion of Step  2  and Step  3 , the process continues to Stage  3 , where based on the speed synchronization start point identified in Stage  2 , a pump motor is controlled to synchronize speed increases thereof with heart beats. Considering all the timing offsets such as the data filter timing delay, the phase shift between left ventricle pressure and pumping flow and motor drive current or power, pump speed ramp up and down time, all the next series of speed synchronization time points can be finalized as: 
         [0056]      t   sync   [j]=t   sync [0]− T   offset +( j− 1)* T   cyc   [i]   
         [0000]    Where T offset &lt;T min2max  and in one possible embodiment T offset ≈T offset ≈40˜80 ms, and J is equal to the sequential heart beat to be synchronized (i.e., J=1 at the first heart beat, J=2 at the second heart beat, etc.). 
         [0057]    This synchronized heart beat count (J) should not be too large, since the speed synchronization at one round may rely on the results of Stages  1  and  2 , which may not be matched with the current heart beat features at after some while probably due to the patient&#39;s physiology or other factors, and thus possibly cause asynchrony between the pump and heartbeat. Therefore, to get the precise real-time synchronization, it may be necessary to identify the latest heart beat cycle features and start the synchronization again after several synchronized heart beat counts. Thus J max  may equal 10, 9, 8, 7, or fewer beats in some embodiments, though in other embodiments may exceed 10, prior to Stages  1 - 3  being re-initiated to ensure asynchrony between the pump and heartbeat does not occur. 
         [0058]      FIG. 5  is a block diagram illustrating an exemplary processing or computer system  500  in which embodiments of the present invention may be implemented. This example illustrates a processing or computer system  500  such as may be used, in whole, in part, or with various modifications, to provide the functions of a processor controlling and receiving data back from an LVAD or other device, and/or other components of the invention such as those discussed above. For example, various functions of such processor may be controlled by the computer system  500 , including, merely by way of example, receiving current or power data back from the pump motor, data processing with regard to previous heart pulses, and speed synchronization of the pump based on such data, etc. 
         [0059]    The computer system  500  is shown comprising hardware elements that may be electrically coupled via a bus  590 . The hardware elements may include one or more central processing units  510 , one or more input devices  520  (e.g., data acquisition subsystems), and one or more output devices  530  (e.g., control subsystems). The computer system  500  may also include one or more storage device  540 . By way of example, storage device(s)  540  may be solid-state storage device such as a random access memory (“RAM”) and/or a read-only memory (“ROM”), which can be programmable, flash-updateable and/or the like. 
         [0060]    The computer system  500  may additionally include a computer-readable storage media reader  550 , a communications system  560  (e.g., a network device (wireless or wired), a Bluetooth™ device, cellular communication device, etc.), and working memory  580 , which may include RAM and ROM devices as described above. In some embodiments, the computer system  500  may also include a processing acceleration unit  570 , which can include a digital signal processor, a special-purpose processor and/or the like. 
         [0061]    The computer-readable storage media reader  550  can further be connected to a computer-readable storage medium, together (and, optionally, in combination with storage device(s)  540 ) comprehensively representing remote, local, fixed, and/or removable storage devices plus storage media for temporarily and/or more permanently containing computer-readable information. The communications system  560  may permit data to be exchanged with a network, system, computer and/or other component described above. 
         [0062]    The computer system  500  may also comprise software elements, shown as being currently located within a working memory  580 , including an operating system  584  and/or other code  588 . It should be appreciated that alternate embodiments of a computer system  500  may have numerous variations from that described above. For example, customized hardware might also be used and/or particular elements might be implemented in hardware, software (including portable software, such as applets), or both. Furthermore, connection to other computing devices such as network input/output and data acquisition devices may also occur. 
         [0063]    Software of computer system  500  may include code  588  for implementing any or all of the function of the various elements of the architecture as described herein. Methods implementable by software on some of these components have been discussed above in more detail. 
         [0064]    The invention has now been described in detail for the purposes of clarity and understanding. However, it will be appreciated that certain changes and modifications may be practiced within the scope of the disclosure.