Abstract:
A clock recovery circuit includes a sampler for sampling a data signal. Logic determines whether a data edge lags or precedes a clock edge which drives the sampler, and provides early and late indications. A filter filters the early and late indications, and a phase controller adjusts the phase of the clock based on the filtered indications. Based on the filtered indications, a frequency estimator estimates the frequency difference between the data and clock, providing an input to the phase controller to further adjust the phase so as to continually correct for the frequency difference.

Description:
RELATED APPLICATION  
       [0001]    This application claims the benefit of U.S. Provisional Application No. 60/304,251, filed on Jul. 10, 2001. The entire teachings of the above application are incorporated herein by reference. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    [0002]FIG. 1 is a timing chart  2  illustrating a typical high-speed data signal in which the clock signal is intrinsic to the data signal. Here, five data bits are shown, representing the sequential binary sequence {10010}.  
           [0003]    In at least one currently employed clock recovery circuit, a data signal is oversampled by a factor of two to recover the “edge” between two data bits and adjust the phase of the recovered clock based on this edge measurement.  
           [0004]    For example, FIG. 2 shows the same timing chart  2  as FIG. 1, and further illustrates the ideal data sample points  4  and edge sample points  5  used by a factor-of-two oversampling clock recovery circuit.  
           [0005]    [0005]FIGS. 3A and 3B illustrate how an edge between two data bits is recovered. In FIG. 3A, the two data samples  8 , 10  have different values, so it is clear that an edge occurred between them. Here, because the edge sample  9  has the same value as the first data sample  8 , it is deduced that the sample  9  was early, i.e. the sample occurred prior to the actual edge between the two bits. With the knowledge that the edge was sampled early, the sampling clock can be adjusted by adding a small delay.  
           [0006]    In FIG. 3B, again the two data samples  8 ,  10  have different values, so again it is clear that an edge occurred between them. Now, because the edge sample  9  has the same value as the second data sample  10 , it is deduced that the sample  9  was late, i.e. the sample occurred after the actual edge between the two bits. With the knowledge that the edge was sampled late, the sampling clock can be advanced.  
           [0007]    Of course, where the value does not change between two consecutive data bits, as with the two consecutive 0s in FIG. 1, no edge exists to aid in clock recovery.  
           [0008]    [0008]FIG. 4 is a block diagram of a clock recovery loop  20 . This loop  20  is basically a two stage counter that accumulates the net difference between early and late edges detected by a set of samplers  22 , four for example. For each bclk cycle, the samplers  22  acquire four equally spaced values from the line, i.e. two data bit samples and the edges immediately following these bits, clocked by a four-phase clock from a phase interpolator  24 .  
           [0009]    The early/late logic  26  examines these four samples, along with the previous (historical) data bit, and determines whether one or more edges occurred and whether the sample points are unambiguously early or late with respect to the data signal edges. (Early and late here refers to early and late samples. This is exactly the opposite of an early or late edge. That is, an early sample corresponds to a late edge.)  
           [0010]    The early/late logic  26  provides early and late indications accordingly. These indications become inputs to the two-stage counter  28 ,  29 . The first stage  28  of the counter divides by N, four for example, to filter the number of noisy edge samples, i.e., the number of early/late indications. The second stage  29  of the counter has 2P counts, corresponding to P phase steps per bit cell over the two bit cells spanned by the half-bit-rate bclk. In this figure, there are P=32 phase steps per bit cell and thus the counter has 2P=64 states encoded as a 6-bit phase setting.  
           [0011]    Thus, overall, the two-stage counter  28 ,  29  forms a divide by 2×P×N counter that accumulates the net difference between the number of early and late samples. The divide-by-N counter  28  acts to filter the early and late signals, reducing the variance due to jitter on the input signal. The divide-by-2P phase counter  29  accumulates the net early and late signals out of the divide-by-N counter to generate a log 2 (2P)=6 bit phase setting signal.  
           [0012]    The phase interpolator  24  accepts a reference clock, bclk, and the phase setting output  25  from the divide by 2P counter  29 . The phase interpolator  24  generates a sample clock  27  for each of the four samplers  22 . The sample clock for the first sampler is displaced from the reference clock by an amount determined by the phase setting from the divide by 2P counter. The relative phase from the reference clock to the first sampler clock is 360×p/64 degrees, where p is the phase setting output  25  from the counter  29 . For example, if p=0, the two clocks are exactly aligned; and if p=16, the first sample clock is displaced by 90 degrees from the reference clock. The four sample clocks are spaced evenly around the unit circle—each following the previous clock by 90 degrees.  
           [0013]    [0013]FIG. 5 is a timing chart illustrating operation of the phase interpolator  24  of FIG. 4. The reference clock (blck) pulse is shown at  60 , while  61  and  62  each illustrates the four outputs of the phase interpolator  24  where p=0 and p=8, respectively.  
         SUMMARY OF THE INVENTION  
         [0014]    When the input data signal has considerable jitter, this edge sample is very noisy. The edge may be seen as early (late) even if the sample point is correctly placed or late (early), and corrections to the sample clock can result in “phase wander”. This phase wander of the sample clock can be minimized by filtering pulses, using, for example, a divide-by-N counter where N is a reasonably large number.  
           [0015]    On the other hand, when the data clock frequency and the sample clock frequency are not exactly the same, “phase lag” can occur. Filtering as above for phase wander can increase the effect of phase lag.  
           [0016]    Thus, there is a tension between phase wander and phase lag. Choosing a large N makes phase wander small but phase lag large. Similarly a small N reduces phase lag at the expense of wander. With large amounts of input jitter and a large Δf, it is not possible to get the recovery clock circuit of FIG. 6 to meet both constraints.  
           [0017]    The present invention is a second-order, dual-loop clock-data recovery (CDR) circuit that overcomes this problem by adding a digital frequency estimator loop to estimate the difference between input and reference clock frequencies, and then removing this difference. The divider then must only deal with deviations from the estimated frequency. This permits a very large divider to be used without compromising the ability to track over a wide input frequency range.  
           [0018]    According to an embodiment of the present invention, a clock recovery circuit includes a sampler for sampling a data signal. Logic determines whether a data edge lags or precedes a clock edge which drives the sampler, and provides early and late indications. A filter filters the early and late indications, and a phase controller adjusts the phase of the clock based on the filtered indications. Based on the filtered indications, a frequency estimator estimates the frequency difference between the data and clock, providing an input to the phase controller to further adjust the phase so as to continually correct for the frequency difference.  
           [0019]    A phase interpolator adjusts the phase of the clock responsive to the phase controller.  
           [0020]    The frequency estimator may include a second filter, a frequency counter, and a frequency synthesizer. The second filter further filters the filtered indications. The frequency counter, responsive to the further filtered indications, produces an output that represents an estimated difference in frequency between the clock and the data. The frequency synthesizer produces signals responsive to the estimated frequency difference. The signals control the phase controller to further adjust the phase.  
           [0021]    The frequency synthesizer may include a divide-by-X counter which divides the clock by a number X, which is based on the estimated frequency difference. The divided clock then provides the input to the phase controller to further adjust the phase.  
           [0022]    A converter may convert the estimated frequency difference to a corresponding period, where the number X is responsive to the period. The divide-by-X counter may include both a divide-by-K counter, where K is a fixed number, as well as a divide-by-V counter, where V is responsive to the period. A single divide-by-K counter may be used by plural clock recovery circuits.  
           [0023]    In one embodiment, the converter uses a conversion table that may be stored, for example, in a read-only-memory (ROM). Alternatively, the converter may perform a 1&#39;s complement of a magnitude portion of the estimated frequency difference. The converter may also be implemented with a microprocessor, which may also implement at least a portion of the divide-by-X counter.  
           [0024]    In one embodiment, the frequency counter may be a saturating counter. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]    The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.  
         [0026]    [0026]FIG. 1 is a timing chart illustrating a typical high-speed data signal in which the clock signal is intrinsic to the data signal.  
         [0027]    [0027]FIG. 2 is the timing chart of FIG. 1, further illustrating the ideal data and edge sample points used by a factor-of-two oversampling clock recovery circuit.  
         [0028]    [0028]FIGS. 3A and 3B are timing charts that illustrate how an edge between two data bits is recovered.  
         [0029]    [0029]FIG. 4 is a schematic diagram of a clock recovery circuit.  
         [0030]    [0030]FIG. 5 is a timing chart illustrating operation of the phase interpolator of the clock recovery circuit of FIG. 4.  
         [0031]    [0031]FIG. 6 is the timing chart of FIG. 2, in which jitter has been added to the signal.  
         [0032]    [0032]FIG. 7 is a timing chart illustrating, in a greatly exaggerated manner, the respective cases of a sample clock running faster and slower than a data clock.  
         [0033]    [0033]FIG. 8A is a graph a illustrating a probability density function for the position of an edge between two bit cells when the input data signal has considerable jitter.  
         [0034]    [0034]FIG. 8B is a the same graph of FIG. 8A, additionally showing the case where a sample is taken at phase step +3.  
         [0035]    [0035]FIG. 9 is an illustration of a Markov chain which is used to perform analysis of phase wander.  
         [0036]    [0036]FIG. 10 is a chart showing state probabilities of the two stage counter of FIG. 4 for an arbitrary jitter probability density function.  
         [0037]    [0037]FIG. 11 is a probability density function used to illustrate phase lag.  
         [0038]    [0038]FIG. 12 is a schematic diagram of an embodiment of a dual-loop clock/data recovery (CDR) circuit of the present invention.  
         [0039]    [0039]FIG. 13 is a schematic diagram of an embodiment of the frequency estimator of FIG. 12.  
         [0040]    [0040]FIG. 14 is a schematic diagram of an embodiment of the frequency synthesizer of FIG. 13.  
         [0041]    [0041]FIG. 15 is a schematic diagram of an alternate embodiment of the frequency synthesizer of FIG. 13.  
         [0042]    [0042]FIG. 16 is a schematic diagram of another alternate embodiment of the frequency synthesizer of FIG. 13. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0043]    A description of preferred embodiments of the invention follows.  
         [0044]    Phase Wander  
         [0045]    [0045]FIG. 6 is the timing chart  2  of FIG. 1, but with jitter  12  added to the signal. That is, the edges do not occur exactly at equal intervals but rather each edge is displaced according to some probability distribution.  
         [0046]    For example, the edges  14  in FIG. 6 occur early (but by different amounts), while the edge  16  occurs late. The dashed lines represent how the signal should appear with no jitter.  
         [0047]    Because the recovery circuit&#39;s clock phase is adjusted based on this noisy measurement, the clock phase will wander about the correct setting. That is, it takes a somewhat random walk about its center point. Each time an early edge, such as  14 , is sampled, the clock is advanced. Each time a late edge, such as  16 , is sampled, the clock is retarded. Thus the random distribution of edge times—due to jitter on the input signal—leads to random movement of the clock sampling point.  
         [0048]    This movement is not completely random. If the clock is displaced from its correct position (for example if it is early) it will be adjusted in the correct direction (being retarded) more often that it will be adjusted in the incorrect direction (being advanced). However, the clock position may take many steps in the wrong direction, leading to a broad probability distribution in the position of the clock sample point.  
         [0049]    Reducing this “phase wander” to acceptable levels requires considerable filtering of the raw edge samples. By integrating over many samples before adjusting the clock, the variance of the clock adjustments is reduced and the probability distribution of the clock sample position is narrowed.  
         [0050]    A Markov analysis of a system with N=4 having jitter uniformly distributed over 0.5 unit interval (UI) shows that such a system may have over 0.44 UI of phase wander.  
         [0051]    When the input data signal has considerable jitter, the position of the edge between two bit cells is a random variable. FIG. 8A shows the probability density function for this variable when the input jitter is uniformly distributed over a range of 0.5 UI. The x-axis is shown in phase steps for a system where 32 (i.e., P) phase steps are spaced uniformly over a single UI. The distribution of jitter ranges from −8 steps (-0.25 UI) to +8 steps (+0.25 UI).  
         [0052]    With the data edge position being a random variable, whether an edge sample is early or late (as indicated by the early/late indication) is also a random variable. For example, the probability that a sample taken at phase step +i is early is (8−i)/16 and the probability of the sample being late is (8+i)/16. FIG. 8B shows the case where a sample is taken at phase step +3, as denoted by arrow  65 . At this point, {fraction (5/16)}of the area of the density function falls to the right of the sample point and {fraction (11/16)}falls to the left. Hence the probability that the sample is late is {fraction (11/16)}, while the probability that the sample is early is {fraction (5/16)}.  
         [0053]    To model phase wander, assume that there is no net difference between the input data frequency and twice the reference clock (bclk) frequency and calculate the probability P(x) of the counter wandering x phase steps from the center position.  
         [0054]    [0054]FIG. 9 is an illustration of a Markov chain  71  which can be used to perform the analysis of phase wander. Each node  73  in the chain  71  represents a state of the two-stage counter  28 ,  29 . The label A.B represents the state where the phase counter  29  has a count of A (within a range of 0 to 2P−1, or alternatively −P to +P) and the divide by N counter  28  has a count of B. The probability of an early or late sample edge gives the transition probability between two states. Thus, the transition probabilities out of the state A.B are determined entirely by the label A, with the down probability d A  given by the integral of the probability density function up to phase step A and the up probability u A  given by the remaining area under the curve:  
         u   A     =       ∫     x   =     P   2       A            P        (   x   )               x                               
 
           d   A =1 −u   A    
         [0055]    Since the Markov chain  71  of FIG. 9 is a linear chain (also called a birth-death system), we can analyze it in closed form since in steady state we know:  
         P        (     A   .   B     )       =       P        (       A   .   B     -   1     )              u       A   .   B     -   1         d     A   .   B                                 
 
         [0056]    where A.B−1 denotes decrementing the two-stage counter state. Since the up and down probabilities for the N states at each phase setting are the same, one can write:  
         P        (     A   .   N     )       =       P        (     A      .1     )              (       u   A       d   A       )       N   -   1                   P        (       (     A   +   1     )        .1     )       =       P        (     A   .   N     )            (       u   A       d     A   +   1         )                             
 
         [0057]    Using these equations, we can solve for the state probabilities of the two stage counter for an arbitrary jitter probability density function. FIG. 10 is a chart  77  which shows these probabilities for a 32-step-per-UI phase counter, i.e. P=32, and filter counters ranging from N=4 to N=64. The chart  77  shows that with 0.5 UI uniform jitter, the phase wander range that has a probability of at least 10 −15  of occurring is from −0.23 UI to +0.23 UI, i.e., an eye opening of almost 0.5 UI for N=4. For N=64, this is reduced to a range of −0.075 UI to +0.075 UI, an eye opening of only 0.15 UI.  
         [0058]    Thus, to maintain a bit error rate (BER) better than 10 −15 , a sufficient eye opening, e.g., 0.5 UI for N=4, 0.15 UI for N=64, etc., must be allowed to account for phase wander. That is, the smaller N is, the larger the eye opening must be to achieve the same BER.  
         [0059]    Phase Lag  
         [0060]    Another phenomenon is “phase lag”. As FIG. 7 illustrates, in a greatly exaggerated manner, when the sample clock  52  is faster than the data clock  50 , it leads the data clock  50 , on average, over time. Eventually, the sample clock is adjusted (at  55 ) so that the two clocks are almost exactly synchronized. However, due to the difference in frequency, the sample clock  52  soon leads the data clock  50  more than it lags. A similar effect occurs when the sample clock is slower than the data clock  54 , as illustrated at  54 .  
         [0061]    Thus, when the input data frequency (illustrated as  50 ) is slightly faster (slower) than the reference clock frequency (plesiochronous) and the input signal has significant jitter, the sample point will lag (lead) the correct value so that the early/late probabilities are unbalanced by an amount large enough to generate sufficient net early (late) edges to adjust the clock position often enough to keep up with the constant phase drift between the two clocks. However, when a large filter is employed, for example to reduce phase wander, phase lag is increased as the number of early (late) edges required for each clock adjustment is increased.  
         [0062]    Referring back to the clock recovery loop of FIG. 4, the fraction of edges that drive the two-stage phase counter  28 ,  29  in the proper direction is directly proportional to the offset of the data sample point from the center of the eye—and hence the offset of the edge sample point from the edge of the eye.  
         [0063]    To see this, consider the situation illustrated in FIG. 11. Here we have 0.5 UI of uniform jitter and 32 phase steps per UI. The sample clock phase is currently early relative to the input data signal, leading the input signal by two phase steps (0.0625 UI). This offset of two steps, along with a complementary offset of two steps in the opposite direction together consume four phase steps (0.125) of the eye, as illustrated by the shaded area  85  in the center of FIG. 11. That is, when the data sample point is at this phase step  89 , ⅜ of the possible input edges, those falling in area  83  in FIG. 11, will retard the sample point while ⅝ of the possible input edges, those falling in areas  85  and  87  of FIG. 11, will advance the sample point. The edges that fall in area  83  exactly cancel the effect of the edges that fall in area  87  since ⅜ of all data edges fall in each area. Thus the net result is that only the ¼ of the edges that fall in area  85  act to adjust the clock sample point in the right direction.  
         [0064]    Given a maximum allowable Δf between the input signal and the reference clock (bclk) of the clock recovery circuit, the maximum phase lag can be calculated. Alternatively, we can work from a budgeted phase lag and calculate the maximum Δf consistent with this amount of lag.  
         [0065]    The formulae are:  
       φ   =       JNP                 Δ                 f     d                            Δ                 f     =       d                 φ     JNP                             
 
         [0066]    where φ is phase lag in UI, J is the amount of uniform jitter in UI (peak-to-peak), N and P are the counter moduli, d is the minimum edge density (edges per UI) of the input signal, and Δf is the frequency difference (actually, given as a ratio in ppm). For example, if the input data is random, the edge density will average d=½. However to be conservative it is better to assume a lower edge density such as d=¼.  
         [0067]    For example, with N=4, a phase lag of 0.1 UI yields a maximum Δf of 391 ppm. Increasing N to 64 while holding φ at 0.1 UI gives a maximum Δf of 24 ppm ({fraction (1/16)} the amount).  
         [0068]    Second-Order Digital Clock Recovery Circuit  
         [0069]    [0069]FIG. 12 is a schematic diagram of a dual-loop CDR circuit  31  embodiment of the present invention. The circuit  31  is similar to that shown in FIG. 4 except for the addition of a frequency estimator block  32  and the corresponding second set of up/down inputs to the phase counter  30 A. The differential input line  19  is over-sampled by a factor of two by a set of four samplers  22  clocked by a four-phase clock from a phase interpolator  24 .  
         [0070]    As with the system of FIG. 12, for each bclk cycle, the samplers acquire four equally spaced values from the line, i.e. two data samples and two edge samples. The data and edge samples are used by the early/late block  26  to generate early and late indications. An “early” indication is generated if the edge is sampled early (differs from the next data bit) while a “late” indication is generated if the edge is sampled late (differs from the previous data bit).  
         [0071]    The early and late indications are filtered by a divide-by-N counter  28 . An “early” indication causes the counter to count up, retarding the sample point. A “late” indication causes the counter to count down, advancing the sample point. Ideally, to prevent excessive phase wander, N should be at least 64. When the counter  28  overflows upward it generates a pulse on its ‘up’ output. When it overflows downward, it generates a pulse on its ‘down’ output.  
         [0072]    These up and down pulses drive the phase counter  30 A which adjusts the position of the sampling clock via the phase interpolator  24 . In addition, these up and down pulses are input into a frequency estimator  32  which estimates the frequency difference Δf between the input signal and the system clock bclk. The frequency estimator  32  generates its own up and down pulses (f up  and f dn ) to rotate the phase counter at a steady rate corresponding to the estimated frequency difference. The phase counter rotates in the sense that each complete cycle of the counter from count 0 to count 2P−1 and back to 0 corresponds to a phase shift of 360 degrees in the phase interpolator.  
         [0073]    Frequency Estimator  
         [0074]    [0074]FIG. 13 is a schematic diagram of an embodiment of the frequency estimator  32  of FIG. 12. The up and down pulses from the divide by N counter  28  (FIG. 12) are further filtered by a divide by M counter  34  that acts to stabilize the frequency loop, the output of which is then input to a saturating frequency counter  36 . The output of the frequency counter  36  represents the estimated difference in frequency, Δf, between the data signal input clock and the recovery circuit reference clock.  
         [0075]    In one embodiment, the output of the frequency estimator  32  is in sign-magnitude format. For example, a six-bit Δf contains a sign bit, s, and a five-bit magnitude, m, which together represent the number −1 s ×m, covering the range from −31 to 31. One skilled in the art of timing circuit design will understand that the frequency estimator can be realized with more or fewer bits and with a different encoding (e.g., one&#39;s complement, two&#39;s complement, or one-hot) than sign magnitude.  
         [0076]    Each increment of the frequency counter  36  output represents a uniform difference in frequency, e.g. 10 ppm, which exactly corresponds to the frequency of the correction signal that is generated by the frequency synthesizer  37 , e.g. 10 ppm of 1.25 GHz is 125 KHz.  
         [0077]    The frequency synthesizer  37  generates a pulse stream with the appropriate rate on the appropriate output. For example, if the output of the frequency counter indicates that the input signal is 20 ppm faster than the 1.25 GHz reference clock, then the frequency synthesizer generates a 250 KHz*2P=16 MHz pulse stream on the f up  output to increase the frequency of the sample clock by 250 KHz. Similarly, if the frequency counter indicates that the input signal is 30 ppm slower than the 1.25 GHz reference clock, then the frequency synthesizer generates a 375 KHz*2P=24 MHz pulse stream on the f dn  output to decrease the frequency of the sample clock by 375 KHz.  
         [0078]    [0078]FIG. 14 is a schematic diagram of an embodiment of the frequency synthesizer  37  that uses a ROM  40  and a divide-by-V counter  38 . To control the divide-by-V counter  38 , Δf is converted from a frequency to a period, taking advantage of the relation that T=1/f. This reciprocal operation may be approximated by a small ROM  40 . The ROM  40  outputs a value V that sets the number of kclks (K bclks) between up or down pulses.  
         [0079]    Every V kclks, i.e. every V×K bclks, the divide-by-V counter  38  outputs a pulse. The sign bit of Δf, together with gates  44  and  46 , determines whether this is an up (f up ) or a down (f dn ) pulse. When Δf is zero, the ROM  40  asserts an inhibit signal  48  that disables both the f up  and f dn , outputs.  
         [0080]    The divide-by-K counter  42  may be shared among multiple receivers and can be located elsewhere, perhaps at a receive master. It divides down the bit clock, bclk, to reduce the operating frequency and required length for the divide-by-V counter  38 .  
         [0081]    The first step in calculating the required values for K and V[Δf] (the ROM contents) is to determine the maximum Δf that can be tracked by the original loop. As described in the discussion of phase wander in the background section, the maximum Δf that can be tracked is given by:  
         Δ                 f     =       d                 φ     JNP                           
 
         [0082]    where d is the edge density (minimum edges per bit), φ is the maximum allowable phase lag (in UI), J is the jitter (in UI), and N and P are the divider constants of the divide-by-N counter  28  and the phase counter  30 .  
         [0083]    Assuming J=0.5 UI, d=0.25, and φ=0.1, and P=32, the maximum Δf that can be tracked is provided below in Table 1 for several values of N.  
                           TABLE 1                                   N   max Δf                            32   4.88 × 10 −5              64   2.44 × 10 −5             128   1.22 × 10 −5                        
 
         [0084]    For example, if N=64 and the other parameters are as above, then the maximum Δf that can be left after frequency estimation is 24 ppm.  
         [0085]    The smallest ROM that can be used to estimate frequency to within 24 ppm while covering a range of actual frequency differences from −200 ppm to +200 ppm requires eight entries, as illustrated in the Table 2 below. For each of the eight non-zero states of the frequency counter the table shows the target difference in frequency for this count (Δf), the interval or period in bclks that is required to achieve this frequency difference (interval), the number of kclks that most closely approximates this interval (V), and the actual frequency difference corresponding to an interval of 8×V (actual Δf), and the size of the frequency step between the previous count and the present count (step). Note that while choosing a value of K greater than unity simplifies the implementation by reducing counter lengths, such a value prevents generation of the optimal interval to achieve a given frequency difference, resulting in a small difference between the desired Δf and the actual Δf. This difference sets a limit on how large K can be made.  
                                   TABLE 2                       Count   Δf   interval   kclks (V)   actual Δf   step                   1   2.40 × 10 −5     1302    163    2.40 × 10 −5     2.40 × 10 −5         2   4.80 × 10 −5     651   81   4.82 × 10 −5     2.43 × 10 −5         3   7.20 × 10 −5     434   54   7.23 × 10 −5     2.41 × 10 −5         4   9.60 × 10 −5     326   41   9.53 × 10 −5     2.29 × 10 −5         5   1.20 × 10 −4     260   33   1.18 × 10 −4     2.31 × 10 −5         6   1.44 × 10 −4     217   28   1.40 × 10 −4     2.11 × 10 −5         7   1.68 × 10 −4     186   24   1.63 × 10 −4     2.33 × 10 −5         8   1.92 × 10 −4     163   21   1.86 × 10 −4     2.33 × 10 −5                    
 
         [0086]    Table 2 shows the value of V (kclks) for each frequency counter output value (step), when K=8. With the lowest divide ratio (V=163) the divide-by-V counter  38  generates a 24 ppm pulse stream. At the highest divide ration (V=21), the counter generates a 186 ppm pulse stream (which is within 24 ppm of 200 ppm). Realizing Table 2 requires a frequency counter  36  with a saturating range of−8 to +8 and an 8-bit divide-by-V counter to realize the divide by 163.  
         [0087]    A more conservative design uses a 15-entry ROM, as shown in Table 3 below. The nominal frequency step here is 13 ppm and the worst-case step size is 16 ppm. This design, while requiring one more bit of both the frequency counter and the divide-by-V counter and requiring seven additional ROM entries, gives considerably more margin.  
                                   TABLE 3                       Count   delta F   interval   kclks   actual df   step                   1   1.33 × 10 −5     2344    293    1.33 × 10 −5     1.33 × 10 −5         2   2.67 × 10 −5     1172    146    2.68 × 10 −5     1.34 × 10 −5         3   4.00 × 10 −5     781   98   3.99 × 10 −5     1.31 × 10 −5         4   5.33 × 10 −5     586   73   5.35 × 10 −5     1.37 × 10 −5         5   6.67 × 10 −5     469   59   6.62 × 10 −5     1.27 × 10 −5         6   8.00 × 10 −5     391   49   7.97 × 10 −5     1.35 × 10 −5         7   9.33 × 10 −5     335   42   9.30 × 10 −5     1.33 × 10 −5         8   1.07 × 10 −4     293   37   1.06 × 10 −4     1.26 × 10 −5         9   1.20 × 10 −4     260   33   1.18 × 10 −4     1.28 × 10 −5         10    1.33 × 10 −4     234   30   1.30 × 10 −4     1.18 × 10 −5         11    1.47 × 10 −4     213   27   1.45 × 10 −4     1.45 × 10 −5         12    1.60 × 10 −4     195   25   1.56 × 10 −4     1.16 × 10 −5         13    1.73 × 10 −4     180   23   1.70 × 10 −4     1.36 × 10 −4         14    1.87 × 10 −4     167   21   1.86 × 10 −4     1.62 × 10 −5         15    2.00 × 10 −4     156   20   1.95 × 10 −4     9.30 × 10 −6                    
 
         [0088]    In yet another embodiment, both for simplification and to provide very fine-grain frequency control, the ROM can be eliminated entirely and the 1s complement of the magnitude portion of Δf used directly as the value of V. This requires that the magnitude portion of the frequency counter  36  have eight bits. A consequence of this approach is that it takes longer for the frequency loop to acquire, as it has to step from a divider of 255 kclks to a divider of 20 kclks one step at a time. Note that in this embodiment the output of the frequency counter is not a frequency but rather a period.  
         [0089]    In yet another embodiment of the present invention, the ROM can be replaced with a combinational logic circuit that realizes the same function.  
         [0090]    Values of M  
         [0091]    The value of M determines the gain of the second-order loop. Stability is assured due to the zero provided by the direct phase update provided by the up and down pulses of the divide-by-N counter  28  directly controlling the phase counter  30 . However, M should be sufficiently large that the divide-by-V counter  38  has cycled at least a few times before M is updated again. At lock, where the frequency of pulses out of the divide-by-N counter  28  is at most 24 ppm (one pulse every 40,000 bclks), no divide-by-M counter is needed since the maximum interval for cycling the divide-by-V counter is 2300 bclks. In practice however, a divide-by-8 counter here would smooth the frequency adjustment process.  
         [0092]    A value of 4 or 8 appears to be adequate for M.  
         [0093]    [0093]FIG. 15 illustrates another embodiment of a frequency synthesizer  37 A in which the output of the frequency counter is used to gate kclk pulses whenever a combinational logic circuit  91 , which examines the output of a free-running counter  93  driven by kclk and the frequency counter gives a true output. Gates  97  and  99  pass the pulses to either the f up  or the f dn  output, depending on the value of the sign of the frequency counter output.  
         [0094]    For example, such a circuit can generate a pulse whenever the output of the free running counter is greater than the ones complement of the frequency counter. Note that this embodiment generates the correct number of kclk pulses averaged over a long period of time. However, these pulses are not evenly spaced, leading to increased sample clock jitter.  
         [0095]    Microcomputer Control  
         [0096]    In one embodiment of the present invention, to facilitate debugging, both control loops should be observable and controllable from a microprocessor. Specifically, various embodiments the invention may operate in one or more of the following modes:  
         [0097]    Fully automatic: In this mode, the phase adjust loop and frequency adjust loop both operate without any intervention from a processor.  
         [0098]    Automatic phase, manual frequency: In this mode, illustrated in FIG. 16, the phase adjust loop, where the divide-by-N counter  28  (FIG. 12) directly increments and decrements the phase counter  30 , operates automatically. However, the frequency adjust loop is broken by a microprocessor  101 . The microprocessor  101  completes the loop by reading the output of the frequency counter (Δf) and generating the divide value (V) for the divide-by-V counter  38 . In essence, the microprocessor  101  replaces the ROM  40  (FIG. 14) in this mode.  
         [0099]    To conserve logic, in another embodiment, the saturating frequency counter may be made very small (two or three bits), while the microprocessor accumulates additional Δf bits internally. For such a loop, the only per-receiver logic required over a first-order loop is the divide-by V counter  38  and the 2 or 3 bit saturating frequency counter  36 .  
         [0100]    Completely manual: In this mode, the microprocessor reads the saturating frequency counter and directly updates the phase setting. That is, the microprocessor also performs the function of the phase counter  6 .  
         [0101]    In any of these modes, the microprocessor should have complete observability of all counter states.  
         [0102]    While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.