Abstract:
A voltage controlled oscillator may include a plurality of inverting units connected in serial and connected between a first and a second voltage sources to produce an oscillating frequency. Each of the inverting units may have a first current source for producing a constant current that may determine an oscillating frequency, a switching inverter connected between the first voltage source and the first current source that may produce a current having a phase opposite to an output current from a preceding inverting unit, and a frequency adjuster that may control the oscillating frequency by charging and/or discharging the current from the inverting unit.

Description:
[0001]    The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2007-0112978 (filed on Nov. 7, 2007), which is hereby incorporated by reference in its entirety. 
       BACKGROUND 
       [0002]    A voltage controlled oscillator (VCO) may provide a desired frequency using a voltage supplied from an outside source. A VCO may be used in an analog sound mixing device, a mobile communication terminal, and other devices. A VCO may generate pitches and waveforms in an audio system, and may generate primary sounds by creating a sine wave, a saw-tooth wave, a pulse wave, and a triangular wave. A VCO may be used in a phase locked loop (PLL) module of a mobile communication terminal and may allocate channels and may function as a local oscillator to convert a frequency into a radio frequency (RF) or an intermediate frequency (IF). 
         [0003]    Example  FIG. 1  illustrates a circuit diagram of a voltage controlled oscillator (VCO). Referring to example  FIG. 1 , a VCO may include an odd-number of depletion-mode inverting units S_INV and inverter INV. Inverter INV may invert an output signal from a last inverting unit S_INV and may produce an inverted output signal. Each inverting unit S_INV may include first, second, third, and fourth transistors M 1 , M 2 , M 3 , and M 4 . Second transistor M 2  and third transistor M 3  may function as an inverter and first transistor M 1  and fourth transistor M 4  may function as current sources. First transistor M 1  and fourth transistor M 4  may restrict a current to be supplied to second transistor M 2  and third transistor M 3 . First transistor M 1  and fourth transistor M 4  may be supplied with current from first input terminal IN 1  and second input terminal IN 2 , respectively. This may generate current flowing through inverting unit S_INV. 
         [0004]    The following equation 1 may expresses a frequency of a voltage output from VCO as shown in  FIG. 1 . 
         [0000]    
       
         
           
             
               
                 
                   
                     F 
                      
                     
                       ( 
                       
                         V 
                         S_out 
                       
                       ) 
                     
                   
                   = 
                   
                     
                       I 
                       D 
                     
                     
                       N 
                       × 
                       C 
                       × 
                       
                         V 
                         DD 
                       
                     
                   
                 
               
               
                 
                   Equation 
                    
                   
                       
                   
                    
                   1 
                 
               
             
           
         
       
     
         [0005]    In equation 1, I D  may be current flowing through inverting unit S_INV, N may be a number of inverting unit(s) S_INV provided in VCO, C may be a sum of parasitic capacitances at input terminals of transistors of inverting unit(s) S_INV, and V DD  may be a first voltage supplied to an oscillating unit. F(V S     —     out ) may be a frequency of an output voltage from VCO. A frequency may linearly vary in proportion to current I D  that may flow through inverting units S_INV, and may vary in inverse proportion to first voltage V DD . However, a level of first voltage V DD  may easily be changed due to various factors. This change may bring a variation to frequency F (V S     —     out ) of an output voltage from VCO. Thus, VCO may be restricted to be used in a circuit requiring a constant output frequency due to the voltage change. 
         [0006]    Example  FIG. 2  illustrates a simulated waveform of an output frequency from VCO depending on a first voltage applied to VCO illustrated in example  FIG. 1 . The waveform of  FIG. 2  may express frequencies of an output voltage from VCO when first voltage V DD  varies in a range between approximately 1.6 V to 2.0 V. Referring to example  FIG. 2 , when a level of an output voltage from VCO varies, a frequency of an output voltage from VCO may decrease from 60 MHz to 40 MHz. In other words, a frequency may vary by 10 MHz as a first voltage varies by 0.2 V. As a result, a variation range of the frequency may be very wide when first voltage V DD  varies. Due to a variation of the frequency, problems, such as jitter, may occur. 
       SUMMARY 
       [0007]    Embodiments relate to a voltage controlled oscillator (VCO). Embodiments relate to a VCO that may be capable of maintaining a constant frequency of an output voltage even when an applied voltage varies. 
         [0008]    According to embodiments, a voltage controlled oscillator may maintain a substantially constant frequency of an output voltage from the voltage controlled oscillator even when a voltage supplied to the voltage controlled oscillator varies. 
         [0009]    According to embodiments, a voltage controlled oscillator may include a plurality of inverting units connected in series and connected between first and second voltage sources to produce an oscillating frequency. According to embodiments, each of the inverting units may include at least one of the following. A first current source to produce a constant current determining the oscillating frequency. A switching inverter connected between the first voltage source and the first current source to produce a current having an opposite phase to the output current from a preceding inverting unit. A frequency adjuster to control the oscillating frequency by charging and/or discharging the current from the inverting unit. 
         [0010]    According to embodiments, a voltage controlled oscillator may include a plurality of inverting units connected in series, which may produce an oscillating frequency. According to embodiments, each inverting unit may include at least one of the following. A first PMOS transistor electrically coupled between a first voltage source and a second voltage source. A first NMOS transistor electrically coupled between the first PMOS transistor and the second voltage source. A second NMOS transistor electrically coupled between the first NMOS transistor and the second voltage source. A second PMOS transistor electrically coupled between the first voltage source and an output terminal of a preceding inverting unit. A third NMOS transistor electrically coupled to the second NMOS transistor, and having a control electrode electrically coupled between the first PMOS transistor and the second PMOS transistor. 
         [0011]    According to embodiments, even when a voltage supplied to the voltage controlled oscillator varies, a frequency of an output voltage may be maintained substantially constant. 
     
    
     
       DRAWINGS 
         [0012]    Example  FIGS. 1 and 2  illustrate a circuit diagram of a voltage controlled oscillator (VCO) and a simulated waveform of frequency of a VCO depending on a voltage applied to the VCO shown in example  FIG. 1 . 
           [0013]    Example  FIG. 3  illustrates a block diagram of a voltage controlled oscillator, according to embodiments. 
           [0014]    Example  FIG. 4  illustrates a circuit diagram of an oscillating unit of example  FIG. 3 , according to embodiments. 
           [0015]    Example  FIG. 5  illustrates a simulated waveform of an output frequency from a VCO depending on a first voltage applied to a VCO in example  FIG. 4 , according to embodiments. 
       
    
    
     DESCRIPTION 
       [0016]    Example  FIG. 3  illustrates a block diagram of a voltage controlled oscillator (VCO) according to embodiments. Referring to example  FIG. 3 , voltage controlled oscillator (VCO)  100  may include reference voltage generator  110 , voltage-current converter  120 , and oscillating unit  130 . Reference voltage generator  110  may be electrically coupled with voltage-current converter  120 , and may be supplied with an external signal through input terminal IN to generate a reference voltage. The reference voltage may be supplied to voltage-current converter  120 . Voltage-current converter  120  may be electrically coupled between reference voltage generator  110  and oscillating unit  130 , and may be supplied with a reference voltage from reference voltage generator  110 . Voltage-current converter  120  may convert the reference voltage into a first current signal and a second current signal, which may be supplied to first input terminal IN 1  and second input terminal IN 2  of oscillating unit  130 . Oscillating unit  130  may be electrically coupled to voltage-current converter  120 , and may be supplied with first current at first input terminal IN 1  and second current at second input terminal IN 2  from voltage-current converter  120 . Oscillating unit  130  may output a voltage having a frequency in proportion to first current IN 1  and second current IN 2  through output terminal OUT. 
         [0017]    Example  FIG. 4 , illustrates a circuit diagram of oscillating unit  130  described in example  FIG. 3 . Referring to example  FIG. 4 , oscillating unit  130  may include an odd-number of inverting units. According to embodiments, oscillating unit  130  may include first inverting unit INV 1  through n-th inverting unit INVn arranged and coupled in sequence, all of which may have substantially the same configuration. Oscillating unit  130  may include a single inverter INV. Each of inverting units INV 1 , INV 2 , . . . , and INVn may be electrically coupled between first voltage source V DD  and second voltage source V SS , and may be supplied with a first voltage and a second voltage from first and second voltage sources V DD  and V SS . Inverter INV may invert an output signal from n-th inverting unit INVn. The inverted output signal may be outputted through output terminal OUT. Each inverting unit INV 1 , INV 2 , . . . , and INVn, may include first through fifth transistors. According to embodiments, each inverting unit INV 1 , INV 2 , . . . , and INVn, may include first PMOS transistor P 1 , second PMOS transistor P 2 , first NMOS transistor N 1 , second NMOS transistor N 2 , and third NMOS transistor N 3 . First PMOS transistor P 1  may include a first electrode (a drain electrode or a source electrode) that may be electrically coupled to first voltage source V DD . 
         [0018]    First PMOS transistor P 1  may include a second electrode (a source electrode or a drain electrode) that may be electrically coupled between a first electrode of first NMOS transistor N 1  and output terminal INV_OUT, and a control electrode (a gate electrode) that may be electrically coupled between third input terminal IN 3  and a control electrode of first NMOS transistor N 1 . First NMOS transistor N 1  may include a first electrode that may be electrically coupled between output terminal INV_OUT of inverting unit INVn and the second electrode of first PMOS transistor P 1 . First NMOS transistor N 1  may include a second electrode that may be electrically coupled to a first electrode of second NMOS transistor N 2 , and a control electrode that may be electrically coupled between third input terminal IN 3  and the control electrode of first PMOS transistor P 1 . First PMOS transistor P 1  and first NMOS transistor N 1  may be coupled to each other and may function as a switching inverter. Accordingly, first PMOS transistor P 1  and first NMOS transistor N 1  may provide a current signal having an opposite phase to a current signal from third input terminal IN 3  of a preceding converting unit and may output a signal at terminal INV_OUT. 
         [0019]    Second PMOS transistor P 2  may be connected between first voltage source V DD  and output terminal INV_OUT of the switching inverter and may alleviate a ditch induced from a switching operation of the switching inverter. According to embodiments, second PMOS transistor P 2  may have a first electrode electrically coupled to first voltage source V DD  , a second electrode electrically coupled between output terminal INV_OUT and a control electrode of third NMOS transistor N 3 , and a control electrode electrically coupled to first input terminal IN 1 . 
         [0020]    According to embodiments, if first NMOS transistor N 1  and first PMOS transistor P 1  function as an inverter, second PMOS transistor P 2  may allow a small current to flow through inverting units INV 1 , INV 2 , . . . , and INVn with a voltage supplied from first voltage source V DD  even when first PMOS transistor P 1  is turned off. According to embodiments, inverting units INV 1 , INV 2 , . . . , and INVn may steadily operate with respect to a change of first voltage V DD . Second NMOS transistor N 2  may include a first electrode electrically coupled to the second electrode of first NMOS transistor N 1 , and a second electrode electrically coupled to second voltage source V SS . Second NMOS transistor N 2  may include a control electrode electrically coupled to a second input terminal IN 2 . According to embodiments, second NMOS transistor N 2  may function as a current source and may restrict a current to be supplied to first NMOS transistor N 1 . According to embodiments, if second NMOS transistor N 2 , which may function as a current source, is installed only between first NMOS transistor N 1  and second voltage source V SS , current variation caused by the first voltage supplied from first voltage source V DD  may be minimized. 
         [0021]    Third NMOS transistor N 3  may adjust an oscillating frequency. According to embodiments, third NMOS transistor N 3  may include a first electrode electrically coupled to second voltage source V SS , and a second electrode electrically coupled to second voltage source V SS . Third NMOS transistor N 3  may include a control electrode electrically coupled to output terminal INV_OUT. According to embodiments, in third NMOS transistor N 3 , a first electrode and a second electrode may be electrically coupled to second voltage source V SS  and may control an oscillating frequency by performing charging and discharging, as if a capacitor, of the current outputted to output terminal INV_OUT of the inverting unit. According to embodiments, third transistor N 3  may have a capacitance greater than capacitance of other transistors N 1 , N 2 , P 1 , and P 2  of each inverting unit INV 1 , INV 2 , . . . , and INVn. Capacitance may be a factor having a large effect on a signal outputted to output terminals INV_OUT of inverting units INV 1 , INV 2 , . . . , and INVn. 
         [0022]    First input terminal IN 1  may be a terminal to which the first current signal supplied from voltage-current converter  120  to oscillating unit  130  is received. Second input terminal IN 2  may be a terminal to which the second current signal supplied from voltage-current converter  120  to oscillating unit  130  is received. According to embodiments, first input terminal IN 1  and second input terminal IN 2  of first inverter INV 1  to n-th inverter INVn may be supplied with substantially the same first current signal and substantially the same second current signal. Third input terminal IN 3  may be electrically coupled to output terminal INV_OUT of a preceding inverting unit, and may be supplied with an output signal from the preceding inverting unit. According to embodiments, a preceding inverting unit of n-th inverter INVn may be (n-1)-th inverting unit INVn- 1 . N-th inverter INVn may be coupled such that third input terminal IN 3  thereof may be electrically coupled to output terminal INV_OUT of (n-1)-th inverting unit INVn- 1 . According to embodiments, third input terminal IN 3  of first inverting unit INV 1  may be electrically coupled to output terminal INV_OUT of n-th inverting unit INVn and may receive an output signal from output terminal INV_OUT of n-th inverting unit INVn. 
         [0023]    Example  FIG. 5  illustrates a simulated waveform of a frequency of a first voltage from oscillating unit  130  of VCO  100 , depicted in example  FIG. 4 . Referring to example  FIG. 5 , a simulated waveform of a frequency of a first voltage from oscillating unit  130  of VCO  100  shows a frequency of an output voltage from oscillating unit  130  when a first voltage supplied from first voltage source V DD  is changed from 1.6 V to 2.0 V. According to embodiments, when a first voltage supplied from first voltage source V DD  is varied, a frequency of an output voltage from oscillating unit  130  may decrease from approximately 52 MHz to approximately 48 MHz. According to embodiments, an output frequency of oscillating unit  130  may vary by approximately 2 MHz as a first voltage supplied from first voltage source V DD  varies by approximately 0.2 V. According to embodiments, a variation range of an output frequency of oscillating unit  130  may be less than that of a VCO when a first voltage varies by approximately 0.2 V. Since VCO  100  including oscillating unit  130  may have a frequency variation within approximately 5% of a reference frequency with respect to the variation of the first voltage, a relatively steady output frequency may be output with respect to a variation of the first voltage. 
         [0024]    Although embodiments have been described herein, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.