Abstract:
A signal relay device for accessing an external memory is provided. The signal relay device includes a bus arbiter and a burst access engine. The bus arbiter performs bus arbitration among main masters on a bus. The burst access engine exchanges signals with the bus arbiter and an external memory controller. The signal relay device facilitates data transfer of large groups of read/write commands between the main masters and the external memory controller.

Description:
BACKGROUND 
     1. Technical Field 
     Embodiments of the present disclosure are related to signal transmission, and more particularly to a signal relay device and a method for accessing an external memory via the signal relay device. 
     2. Description of Related Art 
     External memory systems, such as hard disks, floppy disks, optical disks, and others, allow permanent storage of large quantities of data. However, a central processing unit (CPU) can only directly access data that is in main memory. To process data in an external memory, the CPU must first transfer the data to the main memory. An external memory controller is often used for completing the data transfer between the external memory and the main memory. However, the external memory controller can only send one command, that is, one read or write command, to the external memory at one time, with the subsequent command waiting for completion of the current command. As a result, considerable time is spent on the data transfer when numerous commands are required, and bandwidth of the external memory is not fully utilized. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of one embodiment of an application environment of a signal relay device. 
         FIG. 2  is a block diagram of one embodiment of the signal relay device in  FIG. 1 . 
         FIG. 3A  and  FIG. 3B  are flowcharts of one embodiment of an external memory access method. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a block diagram of one embodiment of an application environment of a signal relay device  20 . The signal relay device  20  connects one or more main devices, such as an integrated circuit (IC)  10 , to one or more secondary devices, such as an external memory controller  30 , via a bus  23 . The external memory controller  30  is further connected to an external memory  40  via a data bus  34 . In one embodiment, the IC  10  may be a processor, an audio device, a video device, or any other CPU-driven device. The external memory  40  may be a hard disk, a floppy disk, or an optical disk, such as a compact disk (CD). 
     In one embodiment, the IC  10  includes one or more function modules  100 , which read data from or write data to the external memory  40 , for performing particular tasks. The IC  10  further includes a plurality of memory blocks  110  for storing data. Depending on the embodiment, as shown in  FIG. 1 , the memory blocks  110  may be internal components of the function modules  100 , or be external components corresponding to the function modules  100 . 
     The signal relay device  20  includes a bus arbiter  210  and a burst access engine  220  connected to the bus arbiter  210  via the bus  23 . The bus arbiter  210  performs bus arbitration among the function modules  110  on the bus  23 . Depending on the embodiment, any one function module  110  hosting the bus  23  may issue consecutive read/write commands to the external memory  40  via the burst access engine  220 , to fully utilize the bandwidth of the external memory  40 . 
       FIG. 2  is a block diagram of one embodiment of the bus arbiter  210  and the burst access engine  220 . As mentioned above, the function module  110  sends read/write commands to the bus arbiter  210  along the bus  23 . The burst access engine  220  analyzes and processes the read/write commands, sends the read/write commands to the external memory controller  30 , receives feedback information from the external memory controller  30 , and sends the feedback information to the function module  110 . 
     In one embodiment, the bus arbiter  210  includes a plurality of pins for executing one or more operations of the bus arbiter  210 , i.e., a strobe pin  211 , a command pin  212 , an internal memory address out pin  213 , an internal memory write enable pin  214 , a backward data pin  215 , an internal memory address in pin  216 , a forward data pin  217 , and an acknowledgement pin  218 . The burst access engine  220  includes a burst access finite state machine (FSM)  221 , a command data first in first out (FIFO) queue  222 , an internal memory address FIFO queue  223 , a backward data FIFO  224 , and a forward data FIFO  225 . 
     The strobe pin  211  is configured for sending a preparation signal to the burst access FSM  221 , to inform the external memory controller  30  of an operation requested by the function module  110 . The operation may be read data from or write data to the external memory  40 . 
     The command pin  212  is configured for sending a command signal about the operation to the burst access FSM  221 . In one embodiment, the command signal includes an operation type, one or more commands, and a communication address of the external memory  40 . The command signal may include only one command, or include a plurality of commands. For example, the command signal “‘set length=100’ &amp; ‘read’” may indicate the presence of one hundred consecutive read commands. The burst access FSM  221  stores the commands into the command data FIFO queue  222 . 
     The internal memory address out pin  213  is configured for sending an internal memory address signal corresponding to the command signal to the burst access FSM  221 . In one embodiment, the internal memory address signal includes internal memory address information of the IC  10 , such as a memory block  110  to which the read data is stored or from which the writing data is read. Depending on the amount of commands included in the command signal, the internal memory address signal may target a specific address in the memory block  110 , or a begin address in the memory block  110 . For example, if the command signal only includes one read command, a corresponding internal memory address signal of “addr_[a]” targets a specific address in the memory block  110  for storing data obtained according to the read command. In another example, if the command signal includes a plurality of consecutive read commands, such as “‘set length=100’ &amp; ‘read’,” the internal memory address signal of “addr_[a]” targets a begin address in the memory block  110  for storing data obtained according to the plurality of consecutive read commands. The burst access FSM  221  stores the internal memory address information into the internal memory address FIFO queue  223 . 
     The burst access FSM  221  directs the external memory controller  30  to read first data from the external memory  40  according to the commands in the command data FIFO queue  222 , and stores the first data into the backward data FIFO queue  224 . The external memory controller  30  sends a control signal to direct the burst access FSM  221  to prepare writing of the first data to the memory block  110  in the IC  10 . After receiving the control signal, the burst access FSM  221  transmits an inform signal to the internal memory write enable pin  214 . It is noted that, if the operation type included in the command signal is “writing data,” no inform signal will be sent by the burst access FSM  221 . Upon the condition of receiving the inform signal by the internal memory write enable pin  214 , the backward data pin  215  receives the first data from the backward data FIFO queue  224 , and the internal memory address in pin  216  writes the first data to a corresponding address in the memory block  110 . 
     The internal memory address in pin  216  is configured for reading second data from a corresponding address in the memory block  110 , according to the internal memory address information into the internal memory address FIFO queue  223 . The forward data pin  217  is configured for storing the second data into the forward data FIFO queue  225 . The burst access FSM  221  writes the second data stored in the data FIFO queue  225  to the external memory  40 , according to the commands stored in the command data FIFO queue  222  via the external memory controller  30 . The acknowledgement pin  218  is configured for receiving a reply signal sent by the burst access FSM  221  after the burst access FSM  221  has completed reading or writing operations to the external memory  40 . 
       FIG. 3A  and  FIG. 3B  are flowcharts of one embodiment of an external memory access method. Depending on the embodiment, additional blocks may be added, others removed, and the ordering of the blocks may be changed. 
     In block S 30 , the bus arbiter  210  receives a request to read data from or write data to the external memory  40  from the one or more function modules  100 . 
     In block S 32 , the strobe pin  211  informs the external memory controller  30  of the request by sending a preparation signal to the burst access FSM  221 . 
     In block S 34 , the command pin  212  sends a command signal about the request to the burst access FSM  221 . As mentioned above, the command signal includes an operation type, one or more commands, and a communication address of the external memory  40 . Depending on the embodiment, the operation type may be read data or write data to the external memory  40 . The command signal may include only one command, or include a plurality of commands, such as “‘set length=100’ &amp; ‘read’,” which indicate the presence of one hundred consecutive read commands. 
     In block S 36 , the burst access FSM  221  stores the commands into the command data FIFO queue  222 . 
     In block S 38 , the internal memory address out pin  213  sends an internal memory address signal corresponding to the command signal to the burst access FSM  221 . As mentioned above, the internal memory address signal includes internal memory address information of the IC  10 , such as a memory block  110  to which the read data is stored or from which the writing data is read. For example, if the command signal includes a plurality of consecutive read commands, such as “‘set length=100’ &amp; ‘read’,” the internal memory address signal of “addr_[a]” targets a begin address in the memory block  110  for storing data obtained according to the plurality of consecutive read commands. 
     In block S 40 , the burst access FSM  221  stores the internal memory address information into the internal memory address FIFO queue  223 . 
     In block S 42 , the burst access FSM  221  detects the operation type of the command signal is read data or write data. If the operation type is read data, the procedure goes to block S 44 . Otherwise, if the operation type is write data, the procedure goes to block S 54 . 
     In block S 44 , the burst access FSM  221  directs the external memory controller  30  to read first data from the external memory  40  according to the commands in the command data FIFO queue  222 , and stores the first data into the backward data FIFO queue  224 . 
     In block S 46 , the external memory controller  30  sends a control signal to direct the burst access FSM  221  to prepare writing of the first data to the memory block  110 . 
     In block S 48 , after receiving the control signal, the burst access FSM  221  transmits an inform signal to the internal memory write enable pin  214 . 
     In block  50 , the backward data pin  215  receives the first data from the backward data FIFO queue  224 , and the internal memory address in pin  216  writes the first data to a corresponding address in the memory block  110  according to information stored in the internal memory address FIFO queue  223 . 
     In block  52 , the acknowledgement pin  218  receives a reply signal sent by the burst access FSM  221  after the burst access FSM  221  has completed operations to the external memory  40 . 
     In block  54 , the internal memory address in pin  216  reads second data from a corresponding address in the memory block  110 , according to the internal memory address information into the internal memory address FIFO queue  223 . 
     In block  56 , the forward data pin  217  stores the second data into the forward data FIFO queue  225 . 
     In block  58 , the burst access FSM  221  writes the second data stored in the data FIFO queue  225  to the external memory  40 , according to the commands stored in the command data FIFO queue  222  via the external memory controller  30 . The procedures then goes to block  52  as described above. 
     For full utilization of bandwidth of the external memory  40 , the signal relay device  20  described above uses the bus arbiter  210  to grant ownership of the bus  23  based on an arbitration mechanism. The hosting function memory  110  may transmit a large group of read/write commands to the burst access engine  220  via the set of pins. The burst access engine  220  uses the burst access FSM  221  to exchange signals with the bus arbiter  210  and the external memory controller  30 , and uses four FIFO queues to store different information related to the large group of write/read commands. 
     It should be emphasized that the above-described inventive embodiments are merely possible examples of implementations, and set forth for a clear understanding of the principles of the present disclosure. Many variations and modifications may be made to the above-described inventive embodiments without departing substantially from the spirit and principles of the present disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and the above-described inventive embodiments, and the present disclosure is protected by the following claims.