Abstract:
A vertical bipolar transistor comprises P-type semiconductor substrate, N-type first well provided in the semiconductor substrate and operating as a collector, P-type second well provided on the first well and operating as a base, N-type third well provided on the first well and acting as a lead-out region of the collector, N-type emitter provided in the second well, an isolation structure provided on the second well to define the emitter, P-type base lead-out region provided in the second well to surround the isolation structure, a first insulating isolation layer provided in the second and third wells to define, along with the isolation structure, the base lead-out region, N-type collector lead-out region provided in the third well and adjoining the first insulating isolation layer, and a second insulating isolation layer provided in the third well to define the collector lead-out region.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2004-044209, filed Feb. 20, 2004, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates generally to a semiconductor device and a method of manufacturing the same, and more particularly to a vertical bipolar transistor and a method of manufacturing the same.  
         [0004]     2. Description of the Related Art  
         [0005]     In a conventional circuit that requires no high-performance bipolar transistor, a bipolar transistor, which can be manufactured without adding a fabrication step in a CMOS process, is employed in order to reduce the manufacturing cost.  
         [0006]     In this technique, a source/drain region of a first conductivity type is used as an emitter region. A well region of a second conductivity type, where the sour/drain region is formed, is used as a base region, and a well region of the first conductivity type is used as a collector region.  
         [0007]     FIGS.  13  to  17  illustrate fabrication steps of such a prior-art bipolar transistor.  
         [0008]     As is shown in  FIG. 13 , isolation regions (STI)  51  are selectively formed in, e.g. a P-type silicon substrate  50 . Then, a deep N-type well region  52 , which functions as a collector region of the bipolar transistor, a P-type well region  53 , which functions as a base region, and an N-type well region  54 , which becomes a lead-out region for the collector region, are formed in succession.  
         [0009]     Although a CMOS section is simply described without depiction on drawings, the P-type well region  53  corresponds to an N-channel MOSFET formation region in the CMOS section, and the N-type well region  54  corresponds to a P-channel MOSFET formation region in the CMOS section.  
         [0010]     As is shown in  FIG. 14 , an N +  emitter region  55  and an N +  collector lead-out region  56  are selectively formed. These are formed at the same time as N +  source/drain regions of the N-channel MOSFET in the CMOS section.  
         [0011]     As illustrated in  FIG. 15 , a P +  base lead-out region  57  is selectively formed. This is formed at the same time as P +  source/drain regions of the P-channel MOSFET in the CMOS section. Thereafter, a silicide film  58  is formed on the surface of each diffusion region by a saliciding process.  
         [0012]     In a step shown in  FIG. 16 , after an insulation film  59  is deposited over the surface of the substrate, conductor layers  60 , which are connected to the N+region  55 ,  56  and P +  region  57 , are formed in the insulation film  59  by an ordinary electrode forming process. Thus, the bipolar transistor is completed.  
         [0013]     In the bipolar section, as shown in  FIG. 17 , the N +  emitter region  55 , N +  collector lead-out region  56  and P +  base lead-out region  57  are formed in the silicon regions lying among the isolation regions  51 . Hence, their positional relationship and sizes are determined.  
         [0014]     In any case, in the above-described bipolar transistor, with the fine device structure of isolation regions, it becomes necessary to increase the impurity concentrations in the well regions, or to suppress occurrence of latch-up. This inevitably leads to a decrease in current amplification factor (current gain).  
         [0015]     If the fine device structure is further advanced, the well concentration tends to further increase and the current amplification factor further decreases.  
         [0016]     Jpn. Pat. Appln. KOKAI Publication No. 2002-110811 discloses that a parasitic bipolar transistor is obtained by forming a well of a second conductivity type in a semiconductor substrate of a first conductivity type, and providing, in this well, diffusion regions of the first and second conductivity types, which are isolated from each other by STI.  
       BRIEF SUMMARY OF THE INVENTION  
       [0017]     According to a first aspect of the present invention, there is provided a vertical bipolar transistor which comprises: a semiconductor substrate having a first conductivity type; a first well region having a second conductivity type, the first well region being formed in the semiconductor substrate and operating as a collector region; a second well region having the first conductivity type, the second well region being provided on the first well region and operating as a base region; a third well region having the second conductivity type, the third well region being provided on the first well region and acting as a lead-out region of the collector region; an emitter region having the second conductivity type, the emitter region being provided in the second well region; an isolation structure provided on the second well region so as to define the emitter region; a base lead-out region having the first conductivity type, the base lead-out region being provided in the second well region so as to adjoin and surround the isolation structure; a first insulating isolation layer provided in the second and third wells so as to define, along with the isolation structure, the base lead-out region; a collector lead-out region having the second conductivity type, the collector lead-out region being provided in the third well region and adjoining the first insulating isolation layer; and a second insulating isolation layer provided in the third well region so as to define, along with the first insulating isolation layer, the collector lead-out region.  
         [0018]     According to a second aspect of the invention, there is provided a vertical bipolar transistor which comprises a semiconductor substrate having a first conductivity type, the semiconductor substrate acting as a collector region; a well region having a second conductivity type, the well region being provided in the semiconductor substrate and acting as a base region; an emitter region having the first conductivity type; the emitter region being provided in the well region; an isolation structure provided on the well region so as to define the emitter region; a base lead-out region having the second conductivity type, the base lead-out region being provided in the well region so as to adjoin and surround the isolation structure; a first insulating isolation layer provided in the well region so as to define, along with the isolation structure, the base lead-out region; a collector lead-out region having the first conductivity type, the collector lead-out region being provided in the semiconductor substrate and adjoining the first insulating isolation layer; and a second insulating isolation layer provided in the semiconductor substrate so as to define, along with the first insulating isolation layer, the collector lead-out region.  
         [0019]     According to a third aspect of the invention, there is provided a semiconductor device including a vertical bipolar transistor in which a source/drain region of a first conductivity type in a CMOS section is formed as an emitter region in a bipolar section, a first well region of a second conductivity type in the CMOS section is formed as a base region in the bipolar section, and one of a second well region of the first conductivity type and a semiconductor substrate of the first conductivity type in the CMOS section is formed as a collector region in the bipolar section, wherein the vertical bipolar transistor includes an isolation structure provided on the first well region so as to define the emitter region. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING  
       [0020]      FIG. 1  is a cross-sectional view that schematically shows a fabrication step of a manufacturing process of a vertical bipolar transistor, which is formed at the same time as a CMOSFET, according to an embodiment of the present invention;  
         [0021]      FIG. 2  is a cross-sectional view that schematically shows a fabrication step of the manufacturing process of the vertical bipolar transistor, which is formed at the same time as the CMOSFET, according to the embodiment of the present invention;  
         [0022]      FIG. 3  is a cross-sectional view that schematically shows a fabrication step of the manufacturing process of the vertical bipolar transistor, which is formed at the same time as the CMOSFET, according to the embodiment of the present invention;  
         [0023]      FIG. 4  is a cross-sectional view that schematically shows a fabrication step of the manufacturing process of the vertical bipolar transistor, which is formed at the same time as the CMOSFET, according to the embodiment of the present invention;  
         [0024]      FIG. 5  is a cross-sectional view that schematically shows a fabrication step of the manufacturing process of the vertical bipolar transistor, which is formed at the same time as the CMOSFET, according to the embodiment of the present invention;  
         [0025]      FIG. 6  is a cross-sectional view that schematically shows the vertical bipolar transistor, which is formed at the same time as the CMOSFET, according to the embodiment of the present invention;  
         [0026]      FIG. 7  is a plan view that schematically shows the vertical bipolar transistor according to the embodiment of the invention;  
         [0027]      FIG. 8  shows an example of measurement results of current amplification factors (hFE) of the vertical bipolar transistor of the present invention and the prior art;  
         [0028]      FIG. 9  shows device simulation results of the vertical bipolar transistor of the present invention and the prior art;  
         [0029]      FIG. 10  shows a result of evaluation by actual measurement with respect to the relationship between the width of a polysilicon film and hFE;  
         [0030]      FIG. 11  shows an actual measurement result of an emitter-base breakdown voltage in relation to the width of the polysilicon film;  
         [0031]      FIG. 12  is a cross-sectional view that schematically shows a vertical bipolar transistor that is formed at the same as a CMOSFET, according to an embodiment of the present invention;  
         [0032]      FIG. 13 a  cross-sectional view that schematically shows a fabrication step of a manufacturing process of a prior-art vertical bipolar transistor;  
         [0033]      FIG. 14  is a cross-sectional view that schematically shows a fabrication step of the manufacturing process of the prior-art vertical bipolar transistor;  
         [0034]      FIG. 15  is a cross-sectional view that schematically shows a fabrication step of the manufacturing process of the prior-art vertical bipolar transistor;  
         [0035]      FIG. 16  is a cross-sectional view that schematically shows the prior-art vertical bipolar transistor; and  
         [0036]      FIG. 17  is a plan view that schematically shows the prior-art vertical bipolar transistor. 
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0037]     Referring now to FIGS.  1  to  7 , a description is given of the structure of a vertical NPN bipolar transistor, as well as a method of manufacturing a MOS transistor in a CMOS section.  
         [0038]     As is shown in  FIG. 1 , isolation regions  11  are selectively formed by STI so as to define a first region for a CMOS section and a second region for a bipolar section in a P-type silicon substrate  10 . Then, using ion implantation, a deep N-type well region  12 , which functions as a collector region of the bipolar transistor, a P-type well region  13 , which functions as a base region, and an N-type well region  14 , which becomes a lead-out region for the collector region, are formed. As will be described below, an N-channel MOSFET is formed in the P-type well region  13  of the CMOS section, and a P-channel MOSFET is formed in the N-type well region  14  of the CMOS section.  
         [0039]     As illustrated in  FIG. 2 , a gate structure Gs is formed by a gate electrode forming process in the CMOS section. At the same time as the gate electrode forming process, a gate structure is formed as an isolation structure Is, which defines an emitter region of the bipolar transistor and isolates the emitter region from a base region. The gate structure comprises a gate insulation film  15 , a polysilicon film  16  and a side wall insulation film  17 .  
         [0040]     In the CMOS section, N-type and P-type impurities are successively implanted for relaxation of electric field and characteristic control in the vicinity of the drain, thereby forming n −  extension portions  18   a  and  p   −  extension portions  19   a . The extension ion implantation may be performed in the bipolar section, too, if the characteristics of the bipolar transistor are not greatly affected. In this embodiment, such ion implantation is not performed. The n −  extension portions  18   a  and  p   −  extension portions  19   a  are formed prior to the formation of the side wall insulation film  17 , as in ordinary fabrication processes.  
         [0041]     As shown in  FIG. 3 , at the same time as source/drain N +  regions  18   b  of the N-channel MOSFET in the CMOS section are formed, an N +  emitter region  18   c  and an N +  collector lead-out region  18   d  are selectively formed in the same step.  
         [0042]     As is depicted in  FIG. 4 , at the same time as source/drain P +  regions  19   b  of the P-channel MOSFET in the CMOS section are formed and, a P +  base lead-out  19   c  is selectively formed in the same step.  
         [0043]     The aforementioned N + /P +  regions are formed through a series of steps such as lithography, ion implantation and activation. In this case, resist boundaries for lithography are offset so as to prevent overlapping of N +  ion implantation and P +  ion implantation, relative to a reference pattern center in the polysilicon film  16 . This aims at avoiding abnormal formation of silicide on the polysilicon film  16  in which N + /P +  impurities are implanted.  
         [0044]     As shown in  FIG. 5 , silicide films  20  are formed by a saliciding process on the diffusion regions  18   b  to  18   d ,  19   b  and  19   c  as well as on the polysilicon film  16 .  
         [0045]     As is shown in  FIG. 6 , after an insulation film  21  is deposited over the substrate surface, conductor layers  22 , which are connected to the N +  regions  18   b  to  18   d  and P +  regions  19   b  and  19   c , are formed in the insulation film  21 . Thus, the bipolar transistor including the CMOS section is completed.  
         [0046]     In the bipolar section, as shown in  FIG. 7 , the isolation structure Is, which is present within an inner isolation region  11   a  and comprises the gate insulation film  15 , polysilicon film  16  and side wall insulation film  17 , defines the distance between the emitter region  18   c  and the P +  base lead-out region  19   c  and the size of the emitter region  18   c.    
         [0047]     In the saliciding step, the side wall insulation film  17  effects isolation between silicide films. In the outer isolation region  11   b , the P +  base lead-out region  19   c  and the N +  collector lead-out region  18   d  are isolated and their positional relationship is determined.  
         [0048]     In this case, if further processing is not performed, the gate electrode  16  would be set in the floating state. To avoid this, a contact is formed on the isolation region  11   a , and the gate electrode  16  is electrically connected to the emitter electrode or the base electrode by wiring. The position of the contact is not limited on the isolation region  11   a . The contact may be directly formed on the gate electrode  16 .  
         [0049]     Next, the characteristic improvement effect of the device structure will be explained in comparison with the prior art.  FIG. 8  shows an example of measurement results of current amplification factors (hFE) of the present invention (hereinafter referred to as “GC (Gate Conductor) type”) and the prior art (hereinafter “STI type”). As is clear from  FIG. 8 , the GC type can achieve an increased hFE that is about double that of the STI type.  
         [0050]      FIG. 9  shows device simulation results of these structures. In  FIG. 9 , (a) indicates the GC type, and (b) the STI type. The hFE is expressed by hFE=Ic/Ib. In actual measurement, a difference in base current is small. Improvement is attained by the increase in collector current. The simulation indicates that the current path (electrons) increases at the lower part and edge part of the polysilicon in the gate structure, as shown by circles in  FIG. 9 .  
         [0051]     It is expected that since the silicon region at the lower part of the polysilicon contributes as the current path, the degree of improvement in hFE varies depending on the width of the polysilicon.  FIG. 10  shows a result of evaluation by actual measurement with respect to the relationship between the width of the polysilicon film and hFE.  
         [0052]     In the actual measurement, the width of the polysilicon film is varied in a range between 0.4 μm and 4.0 μm. Compared to the STI type, the hFE is improved over the entire range. With the width of 0.4 μm, the hFE increases 1.3 times. With the width of 1.0 μm, the hFE increases 2.1 times. With the width of 4.0 μm, the hFE increases about 3.2 times. The width of the polysilicon film defines the distance between the base lead-out region  19   c  and emitter region  18   c . If this width increases, degradation in characteristics occurs due to an increase in emitter crowding phenomenon, which results from a voltage effect in the base region under the polysilicon layer. Moreover, the increase in width leads to an increase in area. It is not possible, therefore, to increase the width excessively. The width of the polysilicon film is determined in consideration of an increase in area of the circuit that is used, and the improvement in characteristics. In usual cases, it is difficult to think of the use of many bipolar transistors. No problem arises if the width is set up to about 2.0 μm. This value leads to double the area of the STI type that has been studied. The hFE that depends on the emitter size was constant, regardless of the value of the size.  
         [0053]     If the emitter-base distance is too small, deterioration occurs in the emitter-base breakdown voltage. The polarity of the gate electrode changes depending on whether the potential of the gate electrode is made equal to that of the emitter or made equal to that of the base. It can be thought that the breakdown voltage may vary due to induction of an undesirable channel or gate leak.  
         [0054]      FIG. 11  shows an actual measurement result of an emitter-base breakdown voltage in relation to the width of the polysilicon film. In the measurement, the width of the polysilicon film was varied in a range between 0.4 μm and 0.8 μm. At the width of 0.6 μm, comparison was made with the fixed potential of the polysilicon. The comparison result shows that there is no particular degradation in breakdown voltage at the width of 0.4 μm. Further, it turned out that the emitter-base breakdown voltage is higher when the potential of the polysilicon film is made equal to that of the emitter than when the potential of the polysilicon film is made equal to that of the base.  
         [0055]     As has been described above, in the prior art, when a bipolar device is formed in the CMOS process, STI isolation has been used to isolate the emitter, base and collector. By contrast, in the present invention, emitter-base isolation is effected by the gate electrode, thereby enhancing the current amplification factor. Since the gate electrode is indispensable in the CMOS process, this displacement can easily be performed and an increase in the range of applications is expectable. Although a further decrease in hFE is likely in future fine device structure, double or more hFE can be obtained without the need to add special fabrication steps.  
         [0056]     In the meantime, since it is necessary to isolate the emitter or the base by the gate oxide film and the side wall insulation film formed at the gate electrode side walls, the bipolar device of this embodiment should preferably use a gate oxide film that permits only a low gate leak, with use of a power supply voltage of up to about 1.5 V. In recent years, a plurality of gate oxide films are used in usual cases. This does not narrow the range of applications of the present embodiment.  
         [0057]     The present embodiment has been described with respect to the NPN bipolar transistor. If impurities of opposite conductivity type are introduced into a P-type semiconductor substrate at the time of manufacture, a PNP bipolar transistor can be obtained.  
         [0058]     Specifically, as shown in  FIG. 12 , isolation regions  32  are selectively formed by STI so as to form a first region for a CMOS section and a second region for a bipolar section in a P-type silicon substrate  31 . Then, using ion implantation, an N-type well region  33 , which functions as a base region of the bipolar transistor, and an N-type well region  34  of the CMOS section are selectively formed. An N-channel MOSFET is formed in the P-type silicon substrate  31  of the CMOS section, and a P-channel MOSFET is formed in the N-type well region  34  of the CMOS section.  
         [0059]     Like the above-described NPN bipolar transistor, a gate structure Gs is formed by a gate electrode forming process in the CMOS section. At the same time as the gate electrode forming process, a gate structure is formed as an isolation structure Is, which defines an emitter region of the bipolar transistor and isolates the emitter region from the base region. The gate structure comprises a gate insulation film  35 , a polysilicon film  36  and a side wall insulation film  37 .  
         [0060]     In the CMOS section, P-type impurity is ion-implanted for relaxation of electric field and characteristic control in the vicinity of the drain, thereby forming p −  extension portions  38   a . At the same time as formation of source/drain P +  regions  38   b  of the P-channel MOSFET, a P +  emitter region  38   c  and a P +  collector lead-out region  38   d  are selectively formed.  
         [0061]     Following formation of n −  extension portions  39   a  in the CMOS section, source/drain N +  regions  39   b  of the N-channel MOSFET and an N +  base lead-out region  39   c  are selectively formed at the same time. Then, silicide films  40  are formed by a saliciding process on the diffusion regions  38   b  to  38   d ,  39   b  and  39   c  and the polysilicon films  36 . Although illustration of formation of electrodes is omitted, the PNP bipolar transistor including the CMOS section is thus obtained.  
         [0062]     In this PNP bipolar transistor, like the NPN bipolar transistor, the emitter-base isolation is effected by the gate structure of the CMOS section. Therefore, the same advantageous effects can be obtained.  
         [0063]     Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.