Abstract:
Compliant wafer level packages  10  and methods for monolithically fabricating the same. A monolithically fabricated compliant wafer level package  10  having a compliant layer  14  and a compliant interconnect  30  passing therein. The compliant interconnects  30  being provided so that electrical and mechanical connections may be supported across the compliant layer  14 , and constructed so that stresses related to relative motion between electrical components is accommodated. A method of providing a substrate  10  having a compliant layer  14 , the compliant layer  14  having a via  20  that exposes a die pad  12  on the substrate  10 . Fabricating a compliant interconnect  30  so that the compliant interconnect  30  contacts the die pad  12 . The compliant interconnect  30  constructed so that electrical and mechanical connections may be supported through the compliant layer  14.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to copending U.S. provisional patent application entitled, “Monolithically Fabricated Compliant Wafer Level Package with Wafer Level Reliability and Functionality Testability,” having ser. No. 60/161,437, filed Oct. 26, 1999, which is entirely incorporated-herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention is generally related to integrated circuit packaging, and more particularly, relates to methods and devices for providing compliant packaging for integrated circuits. 
     BACKGROUND OF THE INVENTION 
     The manufacturing process of an integrated circuit (IC) part can be summarized by the following three steps: I) IC fabrication, II) IC packaging, and III) IC testing. The IC fabrication, further classified into front-end and back-end processing, refers to the fabrication of the transistors and metal levels on the ICs in wafer form at the semiconductor foundry. The IC packaging involves packaging the IC to protect, power, and cool the IC and also provide electrical and mechanical connections between the IC and the outside world. The IC packaging is typically accomplished at a packaging foundry separate from the semiconductor foundry. Multiple testing protocols are used from the bare wafer state to fully fabricated and packaged IC state. Therefore, the IC testing involves both the semiconductor and the package foundries. In conventional electronic assembly, the wafer is subjected to simple testing procedures to identify functioning and non-functioning ICs at the end of the IC fabrication process. The wafer is then diced into individual ICs. The functional ICs are shipped to the package foundry to complete the package assembly process. The package assembly process begins at the package foundry where each IC goes through series of steps. The IC is first placed in a temporary package for electrical and reliability test and burn-in. Good ICs are disassembled from the temporary package and placed into a permanent package. Each package is tested once more for functionality before it is approved for system assembly. The package assembly and testing procedures beyond wafer scribing involve one IC at-a-time, significantly increasing the cost of producing the packaged IC. 
     As well, these packaged ICs are generally incorporated into electronic devices by mounting the ICs on substrates, such as printed wiring boards (PWBs). These PWBs physically support and electrically connect the ICs to other elements in the circuit. The structures utilized to connect the IC to the substrate accommodate the electrical and mechanical interconnections to the chip and are commonly referred to as input/output connections (I/O). Normally, these I/O connections are subject to substantial stresses due to the thermal cycling as the temperatures within the electrical device cycle during operation. For example, electrical power dissipated during operation tends to heat up both the substrate and the associated IC, then both the IC and substrate cool as power is secured to the electrical device. In that the substrate and the IC are generally constructed of different materials having different coefficients of thermal expansion, the IC and substrate will expand and contract by different amounts and at different rates. This motion of the IC relative to the substrate can cause movement of the I/O connections and place them under mechanical stress. Repeated occurrence of these stresses may cause breakage of the I/O connections and ultimate failure of the IC. 
     Thus, heretofore unaddressed needs exist in the industry to address the aforementioned deficiencies and inadequacies. 
     SUMMARY OF THE INVENTION 
     The present invention provides an apparatus and method for producing compliant wafer level packages. 
     Briefly described, one aspect the present apparatus can be described as a monolithically fabricated compliant wafer level package (CWLP) for packaging electronic devices, having a compliant layer with a first surface parallel to a second surface, and a compliant interconnect passing between the first surface and the second surface of the compliant layer. The compliant interconnects being provided so that electrical and mechanical connections may be supported across the compliant layer. Preferably, the compliant interconnect further comprises a substantially vertical portion and a portion that is substantially horizontal to the first surface and the second surface of the compliant level, thereby accommodating relative motion between elements disposed on opposing sides of the compliant layer, yet electrically and mechanically connected by the compliant interconnect. 
     The present invention can also be viewed as providing a method for monolithically fabricating compliant wafer level packages. In this regard, the method can be broadly summarized by providing a substrate having a compliant layer on a first side, the compliant layer having a via that exposes a die pad along the first side of the substrate, and fabricating a compliant interconnect so that a first end of the compliant interconnect contacts the die pad. In fabricating the compliant interconnect, further optional but preferred steps include providing a substantially vertical portion of the compliant interconnect contacting the die pad and providing a substantially horizontal portion of the compliant interconnect that contacts the upper surface of the compliant layer. 
     Other systems, methods, features, and advantages of the present invention will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present invention, and be protected by the accompanying claims. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings incorporated in and forming a part of the specification, illustrate several aspects of the present invention, and together with the description serve to explain the principles of the invention. In the drawings: 
     FIG. 1 shows a side view of one embodiment according to the present invention. 
     FIGS. 2A-2I show side views of the various stages in the process of fabricating a compliant wafer level package in accordance with the embodiment of FIG.  1 . 
     FIGS. 3A and 3B depict a side view of the horizontal compliance provided by a compliant wafer level package shown in FIG. 1, when incorporated within an electronic structure. 
     FIGS. 4A and 4B depict a side view of the vertical compliance provided by a compliant wafer level package as revealed in FIG. 1, when wafer level testability is conducted using test probe cards. 
     FIG. 5 shows a side view of the embodiment of the present invention of FIG. 1, where components have been incorporated in the compliant wafer level package. 
     FIG. 6 shows a top perspective view of various possible forms that may be utilized for the compliant interconnects of the embodiments of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Turning now to the drawings, FIG. 1 presents a side view of one of many possible embodiments of the present invention. This embodiment of a compliant wafer level package (CWLP), which is denoted by reference numeral  10 , comprises a substrate  11  on which one or more (typically numerous) die pads  12  are disposed on a first surface  13 . A compliant layer  14 , preferably a polymeric material with desirable dielectric properties, is disposed on the first surface  13  of the substrate  11  as well. One or more compliant interconnects  30 , each of which is connected at one end to a respective die pad  12 , traverse the compliant layer  14  so that the associated die pad  12  is electrically connected to a solder bump  16  disposed on an upper surface  17  of the compliant layer  14 . Preferably, the compliant interconnect  30  further comprises a substantially vertical portion  31  and a substantially horizontal portion  32  that is generally parallel to the first surface  13  of the substrate  11  and the upper surface  17  of the compliant layer  14 . The compliant layer  14  and compliant interconnects  30  accommodate relative motion between the CWLP  10  and a related supporting substrate, i.e., a system board  40  (FIGS. 3A-3B) or test probe card  50  (FIGS.  4 A- 4 B), during testing of the CWLP  10  or system operation wherein a portion of the CWLP  10  has been incorporated. 
     Referring now to FIGS. 2A through 2I. the CWLP monolithic fabrication process begins with the completion of the fabrication process of the integrated circuits (ICs) (not shown, disposed between substrate  11  and die pads  12 ). Monolithic fabrication means that all of the steps required to produce the final CWLP  10  will be performed on the initial substrate  11  that supports the ICs and associated die pads  12 . At this stage of the process, a substrate  11 , such as silicone, exists with a number of die pads  12  disposed thereon, the die pads  12  serving to support electrical connections between external structures, i.e., test cards and PWBs, and the IC associated with the given die pad  12 . The substrate  11  and die pads  12 , and any other layers or materials added thereto during the compliant wafer level packaging process, are referred to herein as a wafer  18 , with the finished product being referred to as a CWLP  10 . 
     The first step in the process involves applying a compliant layer  14  of material to the first surface  13  of the substrate  11  containing the die pads  12 , as seen in FIG.  2 B. The compliant layer  14  serves a number of important functions, such as: encapsulating the IC to protect it from environmentally induced reliability failures caused by moisture, contaminants, mobile ions, ultraviolet, visible, and alpha-particle radiations, heat, humidity, severe cold, etc.; providing mechanical support and a low stress medium to the embedded compliant interconnects  30 ; supporting vertical compliance for wafer level testability; providing a low dielectric medium for compliant interconnects  30 ; and providing the ability to incorporate various components  25  (FIG. 5) like integrated passives (such as resistors, capacitors, inductors), decoupling capacitors, and Radio Frequency (RF) components in the compliant layer  14 . As well, a material chosen for the compliant layer  14  should have a high glass transition temperature, and be compatible with silicon and metal surfaces, such as copper (Cu), gold (Au), titanium (Ti), nickel (Ni), aluminum (Al), and any other metal used in the IC, compliant package, and PWB manufacturing process. 
     In the instant case, the compliant layer  14  is formed from a low modulus polymeric material of approximately 25 μm in height. The compliant material is spin coated onto the wafer  18 , the spin speed and time being adjusted to achieve the desired thickness of the compliant layer  14 . In addition to spin coating, any of a number of acceptable techniques, or combinations thereof, including but not limited to lamination, meniscus coating, extrusion coating, spray coating, or doctor blading, may be used to apply the compliant layer  14  to the wafer  18 . 
     Next, the die pads  12  on the surface of the substrate  11  are exposed, as depicted in FIG.  2 C. This is accomplished by producing vias  20  in the compliant layer  14 . Once again, various techniques are available to accomplish this, and which one is used may depend on what compliant material has been selected for the compliant layer  14 . If the compliant material is photodefinable, the photolithographic process may be utilized. First, using photolithographic equipment, the compliant layer  14  is exposed through a via mask with ultraviolet radiation at the prescribed exposure dose. If the compliant material is negative photosensitive, then the exposed area is strengthened by UV radiation and the unexposed area can be etched away by dissolving the polymer in a solvent. If the compliant material is positive photosensitive, then the exposed area is weakened by UV radiation and it can be etched by dissolving the polymer in a solvent. If, however, the compliant material is not photodefinable, it can be etched into vias  20  by using techniques such as wet etching, dry etching (to include plasma or reactive ion etching), or laser ablation. Note that the angle  22  of the via  20  sidewall  21  that will ultimately support the substantially vertical portion  31  (FIG. 1) of the compliant interconnect  30  may be controlled to obtain the desired vertical and horizontal compliance. In the present embodiment, an angle  22  of 75 degrees to 80 degrees as defined by the via sidewall  21  and the substrate  11  was preferred, but this angle can vary depending upon the embodiment. After the completion of via etching process, the material should be cured if required. Here, standard polymer curing in a nitrogen purged convective curing oven was used. 
     Referring now to FIG. 2D, the next step in the process is fabricating the compliant interconnects  30 . In the preferred embodiment, the wafer  18  is next sputter coated with Titanium/Copper (Ti/Cu) or Titanium/Gold (Ti/Au) to form a first metal seed layer  23  to be used for electroplating copper or gold compliant interconnects  30 , respectively. The titanium is used to improve the adhesion of the compliant interconnects  30  to the underlying compliant material, forming the compliant layer  14 , and also as a barrier metal. The first metal seed layer  23  is disposed on the upper surface  17  of the compliant layer  14 . As an alternative to a first metal seed layer  23 , any other material that can provide these functions can be used. As alternatives to sputtering, the first metal seed layers  23  can also be deposited on the wafer  18  by evaporation, electroplating, or electroless plating. 
     A photoresist is spin coated on the first metal seed layer  23  and using a photolithographic mask, “serpentine,” “zigzag,” or “step” shapes (FIGS. 6A-6G) are patterned into the photoresist. To form the compliant interconnects  30 , copper is deposited in these patterns by using electroplating. Any other electrically and thermally conductive material can be used as an alternative to copper. As an alternative to electroplating, the electrically and thermally conductive material forming the compliant interconnects  30  can be screen printed, electroless plated, evaporated, or sputtered to form compliant interconnects  30 . In this one step, all of the compliant interconnects  30  on the wafer  18  were created simultaneously. The compliant interconnects  30  of the present embodiment are about 50 μm in width and about 10 μm thick. Note, however, that the dimensions of the compliant interconnects  30  may vary depending on the embodiment. After fabrication of the compliant interconnects  30  is complete, the photoresist and first metal seed layer  23  used in the process are removed, leaving the wafer  18  as it appears in FIG.  2 E. 
     After fabricating the compliant interconnects  30 , a selection whether to embed the leads in compliant material or to leave the compliant interconnects  30  exposed is made. In case of non-embedded compliant interconnects  30 , FIG. 2F, the wafer  18  is sputter coated with a Titanium/Copper (Ti/Cu) second metal seed layer  26  to be used for electroplating Tin/Lead (Sn/Pb) solder bumps  16  as electrical connectors. As an alternative to second metal seed layer  26 , any other material that can provide these functions can be used. As well, as an alternative to sputtering, the second metal seed layer  26  can be deposited on the wafer  18  by evaporation, electroplating, or electroless plating. A photoresist layer is then spin coated on the second metal seed layer  26  and using a photolithographic masking step, solder bump vias  27  are etched into the photoresist and solder bumps  16  are electroplated, preferably to a thickness of about 35 μm. The solder bumps  16  can also be screen printed, electroless plated, evaporated, sputtered, or applied through other techniques. Different types of conductive adhesives or any other thermally and electrically conductive material can be used as an electrical connector rather than solder bumps  16 . Once the photoresist and second metal seed layer  26  used for fabrication of the solder bumps  16  are removed, the embedded CWLP process is complete, and a CWLP  10  exists as it appears in FIG.  2 G. 
     Referring now to FIG. 2H, embedded compliant interconnects  30  will now be addressed. After the compliant interconnects  30  have been fabricated, the photoresist and first metal seed layer  23  (FIG. 2D) used for compliant interconnects  30  is removed. The compliant interconnects  30  are then embedded in the compliant material used to construct the compliant layer  14 . In the preferred embodiment, the layer of compliant material deposited will be about 15 μm thick. The same methods that were previously discussed for use with producing the compliant layer  14  may be generally used to produce this layer of compliant material for embedding the compliant interconnects  30 . Further, generally the same methods that were used to create the vias  20  (now filled with compliant material) in the compliant layer  14  may now be used to expose the distal ends  33  of the compliant interconnects  30  in relation to the ends connected to the die pads  12 . 
     Lastly, the wafer  18  is sputter coated with a Titanium/Copper (Ti/Cu) second metal seed layer  26  to be used for electroplating Tin/Lead (Sn/Pb) solder bumps  16  as electrical connectors. As an alternative to second metal seed layer  26 , any other material that can provide these functions can be used. As well, as an alternative to sputtering, the second metal seed layer  26  can be deposited on the wafer  18  by evaporation, electroplating, or electroless plating. A photoresist layer is then spin coated on the second metal seed layer  26  and using a photolithographic masking step, solder bump vias  27  are etched into the photoresist and solder bumps  16  are electroplated, preferably to a thickness of about 35 μm. The solder bumps  16  can also be screen printed, electroless plated, evaporated, sputtered, or applied through other techniques. Different types of conductive adhesives or any other thermally and electrically conductive material can be used as an electrical connector rather than solder bumps  16 . Once the photoresist and second metal seed layer  26  used for fabrication of the solder bumps  16  are removed, the embedded CWLP process is complete, and a CWLP  10  exists as it appears in FIG.  2 I. 
     The compliant interconnects  30  and compliant layer  14  of the CWLP  10  allow for accommodation of relative motion both vertically and in a horizontal plane that is substantially parallel to the surface of the compliant layer  14 . Compliance is desired for assembly of electronic components without the use of underfill and for wafer level testability. Generally, underfill is used to absorb the thermo-mechanical stress resulting from the coefficient of thermal expansion mismatch between a system board and an associated IC chip. Underfill materials require long processing time and when applied, it is difficult to rework the assembled part. These two factors make underfill a costly solution. Referring now to FIG. 3A, electrical contact is made between a CWLP  10  and a system board  40 , such as a PWB, through the solder bumps  16  of the CWLP  10 . FIG. 3B, shows the result of varying coefficients of thermal expansion between the system board  40  and the CWLP  10 . In the case of the CWLP  10 , the compliant interconnects  30  and compliant layer  14  are designed to physically expand and contract during temperature cycling, thereby accommodating relative motion between the system board  40  and the CWLP  10  and absorbing any thermo-mechanical stresses. In this way, compliant interconnects  30  not only provide electromechanical connection from the CWLP  10  to the system board  40 , but they also replace the costly underfill process. 
     As well, the compliant layer  14  and compliant interconnects  30  are designed to be compliant in the vertical direction. As seen in FIGS. 4A and 4B, vertical compliance is necessary to be able to burn-in and perform reliability and AC/DC functional testing at wafer level. Because of non-planarity of test probe cards  50 , some vertical force against the CWLP  10  would be used to make contact with all of the compliant interconnects  30  on the CWLP  10 . If there were no vertical compliance in the package, the test probe  51  could jeopardize the functionality of the sensitive ICs. In case of the CWLP  10 , the test probe  51  contacts the solder bumps  16 , which are approximately 50 μm above the surface of substrate  11 . The compliant interconnects  30  and compliant layer  14  physically deflect in the vertical direction as needed to make a firm contact to all of the probes  51  of the test probe card  50 . 
     As noted earlier, FIGS. 6A-6G depict a number of shapes, as viewed from a top perspective, that may be used for the compliant interconnects  30 . Each of FIGS. 6A-6G comprise a die pad  12 , a via boundary etch  19 , a compliant interconnect  30 , and a solder bump  16  or other electrical connector. The shapes in FIGS. 6A-6B are only representative in that numerous shapes may be used for the compliant interconnect  30 . 
     It should be emphasized that the above-described embodiments of the present invention, particularly, any “preferred” embodiments, are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the invention. Many variations and modifications may be made to the above-described embodiment(s) of the invention without departing substantially from the spirit and principles of the invention. All such modifications and variations are intended to be included herein within the scope of this disclosure and the present invention and protected by the following claims.