Abstract:
A circuit for calibrating a sync-on-green (SOG) signal includes a switching device for controlling whether to output an image signal; a reference voltage generator for providing a clamp reference voltage and a comparison reference voltage; a clamp circuit for receiving the clamp reference voltage to generate a clamp output; and a comparing device for comparing the reference voltage with the clamp output to generate the SOG signal.

Description:
CROSS REFERENCE TO RELATED PATENT APPLICATION 
       [0001]    This patent application claims priority from Taiwan Patent Application No. 098145124 filed in the Taiwan Patent Office on Dec. 25, 2009, entitled “Circuit for Calibrating Sync-on-Green Signal and Associated Method”, and incorporates the Taiwan patent application in its entirety by reference. 
       TECHNICAL FIELD 
       [0002]    The present disclosure relates to synchronization of an image signal, and more particularly, to a circuit for calibrating a sync-on-green (SOG) signal and associated method. 
       BACKGROUND OF THE PRESENT DISCLOSURE 
       [0003]    Transmission and reception of an image data is achieved via good synchronous mechanism, and especially for high-resolution image. Accurate synchronous receiving control is needed for good image display quality. An SOG technique carries a synchronous signal sync on an SOG signal. 
         [0004]    When the SOG signal is retrieved from an image signal by a conventional circuit, deformation of the retrieved SOG signal occurs due to unmatched circuit components, and thereby deteriorating the image display quality. In particular, since an offset voltage exists at an input end of an operational amplifier (op-amp), errors occur at an output end of the op-amp. In addition, the offset voltage of each chip circuit is different from the errors generated due to the offset voltage, but the conventional technique cannot calibrate the errors. 
         [0005]    Since the conventional circuit cannot effectively calibrate the errors of the retrieved SOG signal, an SOG signal calibrating mechanism not undesirably affected by unmatched circuit components is needed. 
       SUMMARY OF THE PRESENT DISCLOSURE 
       [0006]    An object of the present disclosure is to provide a circuit and a method capable of calibrating errors due to unmatched circuit components or different wafers. 
         [0007]    The present disclosure describes a circuit for calibrating an SOG signal comprises a switching device, a reference voltage generator, a comparing device and a clamp circuit. The switching device controls whether to output an image signal. The reference voltage generator provides a clamp reference voltage and a comparison reference voltage. The clamp circuit receives the clamp reference voltage to generate a clamp output. The comparing device compares the reference voltage with the clamp output to generate an output SOG signal. The clamp reference voltage and the comparison reference voltage are updated to find the transition of the output SOG signal. 
         [0008]    The present disclosure further describes a method for calibrating an SOG signal comprises performing closed-loop clamping according to a predetermined reference voltage to generate a clamp output; comparing the clamp output with a comparison reference voltage to generate a comparison output; and recording a clamp parameter according to the comparison output. The clamp reference voltage and the comparison reference voltage are updated by sweeping a plurality of voltages according to the comparison output. Thus, a first intrinsic offset voltage and a second intrinsic offset voltage can be cancelled according to the clamp parameter. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is a block diagram of a circuit for calibrating an SOG signal in accordance with an embodiment of the present disclosure. 
           [0010]      FIG. 2  shows waveforms of an input SOG signal and an output SOG signal. 
           [0011]      FIG. 3A  is a detailed circuit for calibrating an SOG signal in accordance with an embodiment of the present disclosure. 
           [0012]      FIG. 3B  is a detailed circuit for calibrating an SOG signal in accordance with another embodiment of the present disclosure. 
           [0013]      FIG. 4  is a flow chart of a method for calibrating an SOG signal in accordance with an embodiment of the present disclosure. 
           [0014]      FIG. 5A  and  FIG. 5B  show partial circuits of a reference voltage generator for configurations of switches during two periods. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0015]      FIG. 1  shows a block diagram of a circuit  1  for calibrating an SOG signal in accordance with an embodiment of the present disclosure. The circuit  1  comprises a switching device  10 , a clamp circuit  12 , a low-pass filter  14 , a comparing device  16 , and a reference voltage generator  18 . The switching device  10  controls whether to output an image signal. The clamp circuit  12  receives a predetermined reference voltage, e.g., a clamp reference voltage V CLP , from the reference voltage generator  18 , and generates a clamped output to the comparing device  16 . The low-pass filter  14 , coupled between the clamp circuit  12  and the comparing device  16 , removes high-frequency (HF) noises from the clamped output of the clamp circuit  13 . The low-pass filter  14  is optional. The comparing device  16  receives a comparison reference voltage V COMP  from the reference voltage generator  18  that is compared with the clamped output to generate an output SOG signal V SOGOUT .  FIG. 2  shows waveforms of an input SOG signal V SOGIN  and an output SOG signal V SOGOUT . 
         [0016]      FIG. 3A  is a detailed circuit  1  for calibrating an SOG signal in accordance with an embodiment of the present disclosure. The switching device  10  comprises one multiplexer  100 A. Alternatively, for better effect, two multiplexers  100 A and  100 B coupled in parallel can be applied. For brevity, only one input end of each multiplexer is shown in  FIG. 3A , and other input ends receive input SOG signals from other image sources. Upon selecting a desired image signal, the multiplexer  100 A/ 100 B outputs and feeds it to the clamp circuit  12 . Once being disabled, the multiplexer  100 A/ 100 B stops all of the image signals, and presents high-impedance at its output end. 
         [0017]    The clamp circuit  12  comprises a clamp op-amp  120 , which is equivalent to an ideal op-amp  1201  and an intrinsic offset voltage source V OSI  coupled to a positive input end of the ideal op-amp  1201 , and the clamp reference voltage V CLP  is received at another end of the offset voltage source V OSI  from the reference voltage generator  18 . A negative input end of the clamp op-amp  120  is coupled to an output end of the multiplexer  100 A, and is coupled to an output end of the clamp op-amp  120  via a switch  122  and a transistor  124 , which is coupled between a voltage source V DD  and a current source I SS . 
         [0018]    The comparing device  16  comprises a comparison op-amp  160 , which is equivalent to an ideal op-amp  1601  and an intrinsic offset voltage source V OS2  coupled to a positive input end of the ideal op-amp  1601 , and a comparison reference voltage V COMP  is received at another end of the intrinsic offset voltage source V OS2  from the reference voltage generator  18 . An output end of the op-amp  160  is coupled in series to an inverter  162 , of which an output provides the output SOG signal V SOGOUT . However, when connection configurations of the positive input end and the negative input end of the op-amp  160  are exchanged with each other, the inverter  162  can be omitted. 
         [0019]    The reference voltage generator  18  comprises two voltage dividers  181  and  183 . In  FIG. 3A , a first voltage divider  181  comprises a plurality of first resistors R 1  serially-connected between the voltage source V DD  and ground. A partial resistor R B  provides a plurality of partial voltages from a first voltage V A  to a fourth voltage V D , which are exemplified in  FIG. 3A . The second voltage V B  and the third voltage V C  are selected by the first multiplexer  180  to generate the clamp reference voltage V CLP  to the clamp circuit  12 . The second voltage divider  183  of the reference voltage generator  18  comprises a plurality of second resistors R 2  serially-connected, and the plurality of voltages are selected by the second multiplexer  182  to generate a comparison reference voltage V COMP  to the comparing device  16 . Preferably, the resistance of the resistor R 2  is larger than that of the resistor R 1 . In addition, a plurality of switches  184  coupled between the first voltage divider  181  and the second voltage divider  183  select a partial voltage of the first voltage divider  181 , so that the partial voltage enters two ends of the second voltage divider and serves as a voltage source for the second voltage divider  183 . In one embodiment, the first voltage V A , the second voltage V B , the third voltage V C  and the fourth voltage V D  are respectively 1.08V, 1.11V, 1.20V and 1.32V. The first voltage divider  181  applies a bandgap reference voltage of silicon. For example, when a constant reference voltage V REF  is 1.35V, the fourth voltage is 1.32V. 
         [0020]      FIG. 3B  shows a detailed circuit  1  for calibrating the SOG signal in accordance with another embodiment of the present disclosure. This embodiment is similar to the previous embodiment. In this embodiment, the comparing device  16 ′ applies a hysteresis comparator  160 ′, the reference voltage generator  18 ′ comprises a third voltage divider  185 , and a hysteresis voltage V HYS  is provided to the hysteresis comparator  160 ′ via a third multiplexer  186 ′. The hysteresis comparator  160 ′ prevents the comparison result from being undesirably affected by noises to stabilize SOG signal V SOGOUT . 
         [0021]      FIG. 4  shows a flow chart of a method for calibrating an SOG signal in accordance with an embodiment of the present disclosure. Please refer to  FIG. 4  together with  FIG. 3A  or  FIG. 3B . In Step  41 , the image signal is blocked by disabling the multiplexer  100 A/ 100 B, and nodes X and Y are conducted by closing a switch  122 . After the switch  122  is closed, the clamp op-amp  120  of the clamp circuit  12  forms a feedback configuration and enters a calibration mode. 
         [0022]    In Step  42 , the first multiplexer  180  of the reference voltage generator  18  selects the third voltage V C  (e.g., 1.20V) to the clamp circuit  12  that serves as the clamp reference voltage V CLP . Preferably, the third voltage V C  is selected as a predetermined value or a target value of the comparison reference voltage V COMP . The clamp circuit  12  feeds a clamp output generated at the node X to the comparing device  16 . 
         [0023]    In Step  43 , the second multiplexer  182  of the reference voltage generator  18  selects different voltages between the first voltage V A  and the fourth voltage V D  (e.g., between 1.08V and 1.32V) to the comparing device  16  as the comparison reference voltage V COMP . For example, voltages between the first voltage V A  and the fourth voltage V D  are swept. According to configurations of the switches  184  of the reference voltage generator  18 , different comparison reference voltages V COMP  can be provided accurately.  FIG. 5A  and  FIG. 5B  show a partial circuit of the reference voltage generator  18  to illustrate different configurations of the switches  184  during two periods. In  FIG. 5A , the second multiplexer  182  sweeps voltages between the first voltage V A  and the second voltage V B , e.g. between 1.08V and 1.11V, to the comparing device  16 . In  FIG. 5B , the second multiplexer  182  sweeps voltages, e.g. between 1.11V and 1.14V, to the comparing device  16 . 
         [0024]    The comparing device  16  compares the clamp output with the swept comparison reference voltages to generate a comparison output. The voltages are continuously swept till polarity of the output end (i.e., the output SOG signal V SOGOUT ) of the inverter  162  of the comparing device  16  is changed, e.g. the output SOG signal V SOGOUT  in  FIG. 2  is changed from a positive level to a negative level. Supposing that a sweep value is V E  when the polarity is changed, at this point, a voltage at the positive input end of the op-amp  160  equals that at the negative input end, i.e., V OS2 +V E =V OS1 +V C . Accordingly, it is determined that: 
         [0000]        V   COMP   =V   E   =V   C   +V   OS1   −V   OS2 . 
         [0025]    In Step  44 , a clamp parameter is recorded according to the comparison output, i.e., a code value of V E  is recorded for normal operation. In Step  45 , the first multiplexer  180  of the reference voltage generator  18  selects the second voltage V B , e.g., 1.11V, to the clamp circuit  12 , such that the clamp reference voltage V CLP  is changed from the original third voltage V C , e.g., 1.20V, to the second voltage V B , e.g., 1.11V. After that, the switch  122  is closed to form a short circuit between the node X and the node Y. Accordingly, the calibration procedure of a clamp level of the SOG signal is completed, and a detection procedure of the SOG signal begins. According to the foregoing calibration procedure, when the comparison reference voltage V COMP =V E  and V COMP =V B , a voltage difference between the positive input end and the negative input end is determined that: 
         [0000]    
       
         
           
             
               
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         [0026]    Accordingly, the voltage difference, i.e., V C −V B , between the positive input end and the negative input end of the comparison op-amp  160  is not affected by the intrinsic offset voltage source V OS1  or V OS2 . In other words, the offset voltage sources V OS1  and V OS2  are cancelled so that no undesirable influences occur in the detection procedure of the SOG signal. 
         [0027]    In Step  46 , the multiplexer  100 A/ 100 B is enabled to output the image signal to the clamp circuit  12  and the detection procedure of the SOG signal begins. 
         [0028]    To sum up, the present disclosure describes a circuit for calibrating an SOG signal comprises a switching device, a reference voltage generator, a comparing device and a clamp circuit. The switching device controls whether to output an image signal. The reference voltage generator provides a clamp reference voltage and a comparison reference voltage. The clamp circuit receives the clamp reference voltage to generate a clamp output. The comparing device compares the reference voltage with the clamp output to generate an output SOG signal. The clamp reference voltage and the comparison reference voltage are updated to find the transition of the output SOG signal. 
         [0029]    The present disclosure further describes a method for calibrating an SOG signal comprises performing closed-loop clamping according to a predetermined reference voltage to generate a clamp output; comparing the clamp output with a comparison reference voltage to generate a comparison output; and recording a clamp parameter according to the comparison output. The clamp reference voltage and the comparison reference voltage are updated by sweeping a plurality of voltages according to the comparison output. Thus, a first intrinsic offset voltage and a second intrinsic offset voltage can be cancelled according to the clamp parameter. 
         [0030]    While the present disclosure has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the present disclosure needs not to be limited to the above embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.