Abstract:
A transmitter including a continuous phase FSK modulator is disclosed for use primarily in optical transmission. The output frequencies are achieved by switching a capacitor into and out of an oscillator circuit by means of a PIN diode switch network which is responsive to a binary data input. The resulting sinusoidal waveforms are squared up by means of an inverte with feedback control for adjusting the duty cycle.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to transmitters which include frequency shift key modulation. 
     FSK (Frequency Shift Key) modulators are employed in optical data transmission to produce different frequencies corresponding to a binary data input stream. Most existing modulators employ a varactor diode to vary the capacitance of an oscillator circuit and, therefore, the output frequency. The problem with such a technique is that the capacitance vs. voltage characteristic of the varactor tends to vary from part to part and over temperature. Alternatively, a modulator may employ switching between two crystal oscillators, but this tends to produce discontinuous phase transitions in the output. 
     Recently, it has been proposed in an article identification system to utilize an FSK modulator which switches a capacitor or inductor into and out of an oscillator circuit in order to vary the frequency output (see U.S. Pat. No. 4,918,296 issued to Fujisaka et al). The switches employed were bipolar transistors. Use of such transistors would not be advantageous at the high frequencies required for the present application due to the relatively high and non-linear rf resistance the transistor would exhibit in the saturated state. Also, the oscillator signal amplitude would need to be small to avoid conduction of the collector-base junction of the transistor in the off-state. 
     A further problem with present modulators used in optical transmission involves producing a square wave output signal with a fixed duty cycle (usually higher than 50 percent) suitable for driving an optical device. High speed comparators could be used, but would tend to draw excessive power. Recent proposals have included the use of an inverter to produce the square wave, but generally without any means for fixing the duty cycle in spite of changes in the inverter threshold (see, e.g., U.S. Pat. No. 4,716,383 issued to Lofgren et al, U.S. Pat. No. 4,174,534 issued to Kotlarewsky, and U.S. Pat. No. 4,603,301 issued to Dukes, et al). 
     SUMMARY OF THE INVENTION 
     The invention, in one aspect, is a transmitter including a Frequency Shift Key modulator comprising an oscillator circuit adapted to produce a specific output level frequency. A capacitor is coupled in parallel with the oscillator circuit, and means are provided for switching the capacitor into and out of the parallel connection with the oscillator circuit in order to change the output frequency. The switching means is responsive to a binary data input and comprises a PIN diode. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     These and other features are delineated in detail in the following description. In the drawing: 
     FIG. 1 is a block diagram illustrating portions of an optical transmitter in accordance with an embodiment of the invention; 
     FIG. 2 is a block diagram illustrating portions of an FSK modulator in accordance with the same embodiment. 
     FIG. 3 is a circuit diagram of a portion of the modulator in accordance with the same embodiment, and 
     FIG. 4 is a circuit diagram of a further portion of the modulator in accordance with the same embodiment. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 illustrates portions of a typical optical transmitter which utilizes an FSK modulator. Binary data is received by the modulator illustrated as block 10. The modulator converts the binary data into a duty cycle controlled square wave output signal having two frequencies. The high frequency typically corresponds to a &#34;1&#34; and the low frequency to a &#34;0&#34; of the binary data input. This output is coupled to a laser driver indicated by block 11 which creates the drive signal needed for the laser. The output of the laser driver is applied to a standard laser illustrated by block 12 to produce the optical signal which also comprises two frequencies correpsonding to the original data input. Typically, the optical frequencies are at 11.85 MHz and 13.09 MHz. 
     FIG. 2 illustrates in a block diagram further details of the modulator 10. The data input is coupled to a PIN switch network, 13, to be described, which operates on a tuned circuit oscillator 14. In a manner to be described, the oscillator is adapted to produce two sinusoidal output frequencies depending upon the state of the switch network 13. The resulting signal is coupled to a buffer circuit 15 which prevents loading of the tuned oscillator circuit by other circuitry coupled thereto. The buffer also provides a feedback signal to an automatic gain control circuit, 17, applied to the oscillator 14. The output of the buffer is applied to a duty cycle control circuit, 16, to be described, which squares up the sinusoidal signal and adjusts the duty cycle to be compatible with the laser to be driven. 
     FIG. 3 illustrates in more detail the portions of the modulator including the PIN switch network and oscillator circuit. The binary data input stream is coupled to the base of a bipolar transistor Q 1  through a pair of inverters, 30 and 31, and a voltage divider formed by resistors R 1  and R 20 . A dc voltage of approximately +5 volts, in this example, is applied at terminal 32 to bias the emitter of transistor Q 1  through resistor R 2 . The collector Q 1  is coupled to the anode of PIN diode, D 1 , whose cathode is coupled to ground potential. A dc voltage of approximately -5 volts, in this example, is applied at terminal 33 and is also coupled to the anode of diode D 1  through inductor L 1  and resistor R 3 . 
     One plate of capacitor C 1  is also coupled to the anode of PIN diode D 1 , and the other plate of capacitor C 1  is coupled to the drain of field effect transistor (FET) T 1 . Also coupled to the drain of T 1  is one plate of capacitor C 2 , while its other plate is coupled to ground potential. Feedback for oscillation is provided from the drain of T 1  to the gate of T 2  through capacitor C 6 . 
     Transistor T 1  has its drain biased by a constant dc potential at terminal 34, which in this example is +5 volts. The bias is supplied through inductor L 2 . The source of the transistor is grounded. The gate of the transistor T 1  is coupled to the drain of field effect transistor T 2  through a capacitor C 3 , and also to the automatic gain control circuit (17 of FIG. 2) through a resistor R 4 . A diode, D 4 , is coupled between the gate of T 1  and ground. 
     Transistor T 2  has its drain biased by a constant dc voltage applied at terminal 35, which in this example is approximately +5 volts. The bias is supplied through a resistor R 5 . The source of transistor T 2  is grounded. The gate of T 2  is coupled through a capacitor C 6  to the feedback from the drain of T 1 . Diode D 5  and resistor R 21  are couple between the gate of T 2  and ground. 
     In operation, it will be recognized that the combination, including T 1 , T 2 , L 2 , C 2 , comprises a tuned oscillator circuit producing a specified frequency at the output to the buffer, which in this particular example was 13.09 MHz and constitutes the high frequency for the modulator. That is, T 2  will invert and amplify the signal from the drain of T 1 , and re-apply it to the gate of T 1 , which also inverts and amplifies the signal, and the circuit will oscillate at a frequency according to the value of L 2  and C 2 . When C 1  is coupled into the circuit parallel to C 2 , the increased capacitance lowers the output frequency to a value, which in this example was 11.85 MHz, constituting the low frequency of the modulator. 
     The switching of capacitor C 1  is controlled by the network comprising PIN diode D 1 , transistor Q 1 , inductor L 1  and resistor R 3 . It will be recognized that Q 1 , along with R 1 , R 20 , R 2 , D 2  and D 3 , constitute a switchable current source. Thus, when the data input is low (i.e., a &#34;0&#34;), the base of Q 1  is biased at a potential, such that a fixed current will flow from the collector through the diode D 1  so that the diode D 1  will exhibit a low rf resistance. This will bring C 1  into active connection in parallel with the capacitor C 2 , thus increasing the capacitance and lowering the output frequency of the oscillator. When the data input is high (a &#34;1&#34;), however, Q 1   will shut off. The bias at terminal 33 through the inductor L 1  and resistor R 3  will reverse bias diode D 1  so that D 1  will now exhibit a high rf resistance (i.e., low capacitance) thereby effectively disconnecting C 1  from the oscillator circuit. This reduces the total capacitance and raises the output frequency to its higher level. The data rate in this example was 1.544 Mbit/sec. 
     For this application, the PIN diode D 1  can be a standard switching diode with a low rf resistance (typically 1 ohm) at forward bias and a low capacitance (typically 0.7 pF) at reverse bias. A proper carrier lifetime for the output frequencies in this example would be 150 ns, and an appropriate reverse recovery time for the data rate in this example would be 50 ns. 
     The output of the circuit of FIG. 3, after passing through a buffer circuit (15 of FIG. 2) is then coupled to the circuit of FIG. 4. The signal is first coupled to an inverter 40 through capacitor C 11 . Coupled between the output of the inverter and ground is a series connection of a resistor R 7  and capacitor C 8 . The node between R 7  and C 8  is coupled to the noninverting (+) input of an operational amplifier (op amp), 41, A constant dc voltage at terminal, 42, in this example approximately +5V, is divided down and filtered to form a reference voltage by R 8 , R 10 , and C 9 . This reference voltage is applied to the inverting (-) input of the op amp through resistor R 9 . The output of the op amp is coupled to the input of inverter 40 through resistor R 11 . The output of inverter 40 is also coupled to a second inverter 43, which is used for buffering the output of inverter 40. 
     In operation, the sinusoidal signal at the input of inverter 40 will be transformed into a square wave signal of reversed polarity at the output, and then returned to the original polarity after being sent through inverter 43. Since the threshold of the inverter will vary, op amp 41 is utilized to adjust the dc level of the sinusoidal input signal so that it will always produce a fixed duty cycle for the output square wave, which, in this example is a duty cycle of 50 percent. This is achieved by coupling the output signal through a low pass filter formed by the combination of resistor R 7  and capacitor C 8 , and applying it to the &#34;+&#34; input of the op amp. The values of the resistor R 7  and capacitor C 8  are chosen so that the resulting signal applied to the op amp input is a dc signal equal to the duty cycle of the square wave signal output of the inverter, 40, multiplied by the supply voltage. In this example, the resistance of R 7  was 10K ohms, the capacitance of C 8  was 0.1 microfarads and the supply voltage was +5 volts. 
     Meanwhile, resistors R 8  and R 10  are chosen so that the reference voltage applied to the inverting (-) input of the op amp is equal to the voltage which will give the desired duty cycle, in this example 0.5 times the supply voltage, or 2.5 volts. In this example, the resistance of the resistors R 8  and R 10  was 10K ohms each. The output of op amp 41 applied back to the input of inverter 40 will, therefore, adjust the dc level of the input sinusoidal signal until the noninverting (+) input of the op amp is also at 2.5 volts. At that time, the output of inverter 40 will be at the desired 50 percent duty cycle, and op amp 41 will go into a quiescent state until such time as the threshold of inverter 40 should change and alter the duty cycle. 
     Due to the inherent turn-on delay of laser diodes, it is known that the electrical drive duty cycle should be greater than 50 percent to achieve a 50 percent optical waveform duty cycle. In this example, the required duty cycle is approximately 60 percent. Consequently, the output of inverter 43 is coupled, through resistors R 12 , R 18 , and capacitor C 10 , to inverters 44 and 45 where the operation of duty cycle adjustment is repeated by op amp 46. The purpose of R 12 , R 18  and C 10  is to convert the square wave output of inverter 43 into a triangular wave so that duty cycle adjustment can be repeated. This time, however, resistors R 14  and R 15  are chosen to produce a reference voltage of approximately 0.4 times the supply voltage, or 1 volt, at the inverting (-) input to achieve a 40 percent duty cycle signal at the output of inverter 44 so that the output of inverter 45 produces the desired 60 percent duty cycle. The signal is then sent to the laser driver to produce the optical output signal. 
     It will be understood that the 60 percent duty cycle is not produced in one stage due to amplitude variations in the sine wave input to inverter 40 which occur in the oscillator circuit during the data transitions. Such amplitude variations would cause duty cycle jitter for any value other than 50 percent. 
     It will be appreciated from the above that any desired duty cycle can be achieved in accordance with this aspect of the invention by an appropriate choice of reference voltage. 
     Various additional modifications will become apparent to those skilled in the art. All such variations which basically rely on the teachings through which the invention has advanced the art are properly considered within the scope of the invention.