Abstract:
A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction which divides the numerator value by the denominator value to generate a quotient value and a remainder value, and a sign assignment instruction which adjusts the sign of at least one of the quotient and remainder values. The conditional subtraction instruction is configured to cause the core to perform multiple iterations of a conditional subtraction in one execution of the conditional subtraction instruction and in one clock cycle. Others methods and apparatus are described as well.

Description:
BACKGROUND 
       [0001]    Unsigned division on a computer involves an iterative process. Each iteration includes the execution of one conditional subtraction instruction and that instruction generally executes in one clock cycle. For an M-bit/N-bit integer division in a computer, the division process requires the execution of M conditional subtraction instructions which execute over M cycles. For example, a 32-bit integer division operation in a computer may require a conditional subtraction instruction to be executed 32 times and thus take 32 clock cycles to complete. Integer division thus is a relatively time-consuming operation. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0002]    For a detailed description of various examples, reference will now be made to the accompanying drawings in which: 
           [0003]      FIG. 1  shows a block diagram of a processor which can execute an instruction including sign extraction instructions, conditional subtraction instructions, and sign assignment instructions in accordance with various examples; 
           [0004]      FIG. 2  illustrates the use of registers that include numerator and denominator values in a division operation that results in a remainder in a register and a quotient in the register originally including the numerator value in accordance with various examples; 
           [0005]      FIG. 3  illustrates a time sequence of events for computing four bits of a numerator during execution of a single conditional subtraction instruction in accordance with various examples; 
           [0006]      FIG. 4  shows a block diagram of a processor configured to execute the instruction set described herein in accordance with various examples; and 
           [0007]      FIG. 5  shows a method for computing a signed division operation in accordance with various examples. 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, different companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the term “couple” or “couples” is intended to mean either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. 
         [0009]    Many conventional integer processes involve the iterative execution of a conditional subtraction instruction—one such execution per cycle. In accordance with the disclosed embodiments, however, a conditional subtraction instruction is provided as part of an instruction set that performs multiple conditional subtraction operations in one execution of the instruction and thus in one cycle. The disclosed integer division process includes the use of an instruction set that includes sign extraction instructions, conditional subtraction instructions, and sign assignment instructions. 
         [0010]    Various embodiments of the sign extraction instructions save the sign of the numerator for a signed numerator value as well as save the sign of the denominator value if the denominator is a signed value or otherwise computes the exclusive OR of the most significant bits of the numerator and denominator values. The sign extraction instructions also compute the absolute value of the numerator and denominator when such values are signed negative values. 
         [0011]    After extracting the signs of the numerator and denominator and conversion of the numerator and denominator to unsigned integers as appropriate, one or more conditional subtraction instructions can be executed to perform an unsigned division. This instruction includes the performance of multiple conditional subtraction operations. For example, the conditional subtraction instruction may perform four conditional subtraction operations. As such, to divide a 32-bit numerator by a 32-bit denominator, eight executions of the conditional subtraction instruction are performed. Each execution of the instruction computes 4 bits of the quotient and thus the entire 32-bit quotient is computed after only eight executions of the instruction. Thus, the entire division process is much faster than if only a single conditional subtraction instruction was executed in each clock cycle. 
         [0012]    The completion of the appropriate number of executions of the disclosed conditional subtraction instruction to fully consume all of the bits of the numerator results in the computation of the quotient and the remainder values. Following completion of the conditional subtraction process, the quotient and remainder may be adjusted as necessary depending on the signs of the numerator and denominator (as determined and extracted when executing the sign extraction instructions) and depending on the type of division desired. The disclosed instruction set supports truncated (also called traditional) division, modulo division, and Euclidean division. In some cases, the signs of the quotient and/or remainder are adjusted. 
         [0013]      FIG. 1  shows a block diagram of a processor  100  in accordance with an embodiment. The processor  100  as shown includes a core  102 , which contains multiple registers  104 . The core  102  may contain other hardware components as well such as subtractors, comparators, fetch logic, decode logic, arithmetic logic units (ALUs), etc. The core  102  may execute various machine instructions  106 , which may be stored in memory within, or otherwise accessible to, the core  102 . The machine instructions  106  comprise an instruction set that includes instructions that may perform a variety of operations. One function that can be implemented through a series of instructions from the instruction set is integer division. In at least some embodiments, the integer division operation performed by processor  102  is implemented through the execution of a sign extraction instruction  108 , one or more instances of a conditional subtraction instruction  110 , and a sign assignment instruction  112 . The machine instructions  106  may include one or more different types of sign extraction instructions  108 , one or more different types of conditional subtraction instructions, and one or more different types of sign assignment instructions. 
         [0014]    The integer division process that can be performed by the processor  100  includes the processor dividing a numerator (NUM) value by a denominator value (DEN). The result of the division is a quotient (QUO) and a remainder (REM). The division may include a signed NUM divided by a signed DEN, a signed NUM divided by an unsigned DEN, or an unsigned NUM divided by an unsigned DEN. Before executing a conditional subtraction instruction using the NUM and DEN, the state of the signs of the NUM and DEN are determined and saved through execution of a sign extraction instruction  108 . Depending on the whether the NUM and DEN are signed or unsigned, the processor is programmed to execute a corresponding sign extraction instruction  108  and, if either of the NUM and DEN are negative values, the sign extraction instruction  108  also determines their absolute value. A conditional subtraction instruction can then be executed one or more times as needed based on the size of the NUM and DEN. Following the computation of the QUO and REM, an appropriate sign assignment instruction  112  is executed to restore the signs to the QUO and REM as may be necessary. While restoring the appropriate sign to the QUO and REM, the sign assignment instruction also may adjust the QUO and REM based on a specified type of division such as traditional, modulo, or Euclidean. 
         [0015]      FIG. 2  depicts the use of registers  104  to perform the integer division, which may be a signed or unsigned division process  120 . NUM is stored in a register  104  designated in this example as R 1  and DEN is stored in register R 3 . The completion of the division operation results in the quotient QUO and remainder REM being in registers R 1  and R 2 , respectively. In this embodiment, the same register (R 1 ) is used for both the NUM and the QUO. The register initially contains the NUM. The registers  104  may be implemented as shift registers. The NUM is consumed during the iterative division process one bit at a time starting with the most significant bit (MSB). Each iteration also results in the computation of a QUO bit. As the MSB of the NUM value is consumed, the bits of R 1  are left-shifted one bit and the newly computed QUO bit is shifted into R 1  at the least significant bit (LSB) location. The REM value is iteratively computed as well during the division process. Therefore, both the QUO and REM are computed and available when the last bit of the QUO is computed. 
         [0016]    The integer division operation is an iterative process that consumes one NUM bit in each iteration to compute one QUO bit. Each iteration includes a conditional subtraction operation, which computes the difference between the left-shifted remainder appended with NUM MSB bit and the denominator if the number obtained as above is equal to or greater than the denominator in which case the quotient bit is determined to be a 1. If the number obtained as above is less than the denominator, no subtraction is performed and, instead, the quotient bit is determined to be a 0. In accordance with the disclosed embodiments, the conditional subtraction instruction  110  performs multiple (e.g., 4) conditional subtraction operations with one execution of the instruction and in one cycle. 
         [0017]      FIG. 3  illustrates a time sequence of events to illustrate an execution of the disclosed conditional subtraction instruction, which performs four conditional subtraction operations. In other embodiments, the number of conditional subtraction operations may be other than four. In the example of  FIG. 3 , a numerator is to be divided by a denominator. The denominator in this example is decimal  3  (0011b in binary). The registers may be 32-bit registers (or other than 32 bits in other implementations). In the example of a 32-bit register, R 3  contains the denominator [00 . . . 0011] as shown. The numerator also is a 32-bit value and, as explained above, is consumed four bits at time with each execution of the conditional subtraction instructions  110 . The four numerator bits consumed during the execution of the conditional subtraction instruction are the four most significant bits. In the example of  FIG. 3 , the four most significant NUM bits are 1011b as shown in register R 1 . The remaining 28 least significant bits of NUM are depicted by the line  202  and will be consumed four bits at a time in subsequent executions of the conditional subtraction instruction  110 . 
         [0018]    At  200 , the DEN value of 0011 is stored in register R 3  and the NUM value containing 1011b as the MSBs is stored in register R 1 . A move instruction may be executed by the core  102  to place the NUM and DEN values in the corresponding registers R 1  and R 3 . The remainder register R 2  is initialized to a value of 0 as shown. 
         [0019]    At  202 , register R 1  is left-shifted with the MSB bit (currently a “1”) shifted into the LSB of the remainder register R 2 . At this point, the remainder register R 2  is compared to the denominator register R 3 . If the denominator register R 3  contains a value that is greater than the value in the remainder register R 2 , then the next QUO bit is determined to be 0. If the denominator register R 3  contains a value that is less than or equal to the value in the remainder register R 2 , the QUO bit is determined to be a 1 and the difference between the values in remainder and denominator registers R 2  and R 3  is computed and the result written back to the remainder register R 2 . The process then repeats, three more times in this example. 
         [0020]    In the example of  FIG. 3 , the remainder register R 2  currently contains a value of 1b (after the MSB from R 1  is shifted into the R 2  at  202 ) and the denominator register R 3  contains 0011b. R 2  is compared to R 3  at  204 . The denominator register R 3  (0011b) is greater than remainder register R 2  (1b). As such, the next QUO bit is determined at  206  to be a 0 and is written into the LSB of register R 1  as shown. 
         [0021]    The process repeats and thus at  208 , register R 1  is again left-shifted with the MSB bit (currently a “0”) of R 1  is shifted into the LSB of the remainder register R 2 . The remainder register R 2  now becomes 0010b. At  210 , R 2  is compared to R 3 . R 2  contains 0010b and R 3  contains the denominator 0011b. Thus, R 2  is less than R 3  and the next QUO bit is again determined to be a 0 and shifted into the LSB of R 1  as illustrated at  212 . As can be seen, the remaining MSBs of the numerator are shifted into the remainder register and consumed to compute QUO bits, which are shifted into the LSB positions of register R 1 . Thus, the NUM is iteratively shifted out of register R 1  and the QUO is shifted into R 1 . 
         [0022]    In the next iteration at  214 , the register R 1  is again left-shifted with the MSB (a 1) shifted into the LSB of the remainder register R 2 . R 2  now contains the value 0101b. The remainder register R 2  is compared to the denominator register R 3  at  216 . R 2 &#39;s value of 0101b is greater than R 3 &#39;s value of 0011b. Consequently, the next QUO bit is determined to be a 1 and is shifted into the LSB of register R 1  at  218 . In addition, the difference between R 2  and R 3  is determined as 0101b-0011b=0010b and the resulting difference 0010b is written into register R 2  as shown at  220 . At this point, the first three MSBs of the quotient have been determined to be 001b. 
         [0023]    In the last iteration, register R 1  is again left-shifted and the MSB (a 1) is shifted into the LSB of the remainder register R 2  at  222 . The remainder register R 2  now contains the value 0101b and is compared to denominator register R 3  (0011b). R 2  is greater than R 3  and thus the next QUO bit is determined to be a 1 as shown at  226 . Further, the value contained in R 3  (0011b) is subtracted from the value contained in R 2  (0101b). The resulting difference 010b is written to the remainder register R 2  as shown at  228 . 
         [0024]    At this point, the conditional subtraction instruction has performed four conditional subtraction operations. The four QUO bits were computed as 0011b and the REM is computed as 010b. The conditional subtraction instruction again may be executed with the current states of registers R 1 , R 2  and R 3  (from the previous iteration of the conditional subtraction instruction) used as the initial state of the registers for the new execution of the conditional subtraction instruction. The conditional subtraction instruction may be repeatedly executed until all 32 bits of register R 1  have been consumed. At that point, register R 1  will contain the entire quotient and register R 2  will contain the remainder. 
         [0025]      FIG. 4  shows an example of an architecture for processor  100  to execute the conditional subtraction instruction  110 . The illustrative architecture of  FIG. 4  includes the R 1 , R 2 , and R 3  registers (although additional registers may included), a subtractor  300 , a selection circuit  302 , a comparator  304 , and a 0/1 bit generator  306 . The components of the processor  100  may be comprised of transistors and other types of electrical circuit components. The subtractor  300  compares the values in the R 2  remainder register and the R 3  denominator register and generates an output as shown as R 2 -R 3 . The R 2 -R 3  value is provided to the selection circuit  302 . 
         [0026]    The comparator  304  compares the values in the R 2  and R 3  registers and generates control signals  305  and  307  to the selection circuit  302  and the 0/1 bit generator  306 , respectively. Although separate control signals  305 ,  307  are shown in  FIG. 4 , one control signal could be generated by the comparator  304  and provided to both the selection circuit  302  and the 0/1 bit generator  306 . The comparator  304  determines whether the value in R 2  is greater than or equal to the value in R 3 , or whether the value in R 2  is less than the value in R 3 , and generates the control signals accordingly. 
         [0027]    If R 2  is greater than or equal to R 3 , then a control signal  305  is asserted to a first state that causes the selection circuit  302  to provide the R 2 -R 3  value back to the register R 2  for overwriting the value currently in R 2 . Thus, R 2  will contain the value R 2 -R 3 . Further, when R 2  is greater than or equal to R 3 , the comparator asserts control signal  307  to a first state to cause the 0/1 bit generator  306  to generate a 1 bit to be written into the least significant bit of register R 1 . 
         [0028]    However, if the comparator determines that the value in R 2  is less than the value in R 3 , the comparator asserts the control signal  305  to a second state to preclude the selection circuit  302  from outputting its R 2 -R 3  computed value to the remainder register R 2 . As such, R 2  remains unchanged. Further, when R 2  is less than R 3 , the comparator asserts control signal  307  to a second state to cause the 0/1 bit generator  306  to generate a 0 bit to be written into the least significant bit of register R 1 . 
         [0029]      FIG. 5  is a flow chart depicting a method in accordance with various embodiments. The operations shown may be performed in the order presented in  FIG. 5 , or may be performed in a different order as desired. The method is performed by the processor  100  and specifically may be performed by the core  102  executing a sign extraction  108 , one or more conditional subtraction instructions  110 , and a sign assignment instruction  112 . Generally, operations  400 - 410  are performed during the execution of a sign extraction instruction  108 . Operation  412  is performed during the execution of one or more conditional subtraction instructions  110 , and operation  414  is performed during execution of a sign assignment instruction  112 . Through execution of different types of sign extraction instructions, conditional subtraction instruction, and sign assignment instructions, the disclosed embodiments can perform an integer division based on whether the numerator is a signed or unsigned value and whether the denominator is a signed or unsigned value. The illustrative method depicted in  FIG. 5  covers multiple variations of dividing a numerator by a denominator (e.g., signed/signed, signed/unsigned). If the division is for a signed numerator and signed denominator, specific instructions are used for the sign extraction and assignment processes based on apriori knowledge of the numerator and denominator. Similarly, if the division involves a signed numerator and an unsigned denominator, different types of instructions are used for the sign extraction and assignment processes. If it is desired to divide an unsigned numerator by an unsigned denominator, the execution of a sign extraction instruction  108  and a sign assignment instruction  112  are not necessary. 
         [0030]    At  400 , the method includes initializing an “NI” flag to the MSB of the numerator. In some embodiments, the MSB of the numerator is the sign bit for numerators that are signed values. Setting the NI flag to the value of the numerator&#39;s MSB causes the sign (positive or negative) of the numerator to be saved. 
         [0031]    If the denominator is a signed value ( 402 ), then control moves to operation  406 . The sign extraction instruction itself does not make a determination as to whether the denominator is signed or unsigned. Whether the denominator is signed or unsigned is known apriori and a corresponding sign extraction is selected, for example, by a software programmer, compiler, etc. If the denominator is a signed number, then at  406  a “TF” flag is set to be the exclusive-OR between the MSBs of the numerator and denominator. Otherwise if the denominator is not a signed value, then at  408 , the TF flag is set to be the MSB of the numerator. At this point, the state of the signed bits of the numerator and denominator have been saved and/or used to set the NI and TF flags. 
         [0032]    If either NUM or DEN are signed and negative values ( 408 ), then the absolute value of each NUM and/or DEN is computed at  410 . Any suitable technique for negating a negative NUM or DEN to a positive value can be used. 
         [0033]    At  412 , the method includes iteratively executing a conditional subtraction instruction that includes multiple conditional subtractions operations as described herein. In some embodiments, the conditional subtraction instruction performs four conditional subtractions in a single execution of the instruction and thus in one cycle, although other than four conditional subtractions can be implemented in other embodiments. The denominator is subtracted from the remainder and the difference replaces the value in the remainder register based on the remainder register currently containing a value that is greater than or equal to the denominator. Otherwise, the remainder register remains unchanged in that iteration. Further, in each such iteration, the QUO bit is determined to be a 1 if the remainder is greater than or equal to the denominator, or a 0 if the remainder is less than the denominator. 
         [0034]    Following the completion of the unsigned division process of the numerator divided by the denominator, which may include multiple executions of the conditional subtraction instruction, at  414  the method includes (e.g., by the processor  100  executing a sign assignment instruction) conditionally adjusting the quotient and remainder based on the NI flag, the TF flag, and the type of division. The type of division may include traditional, modulo, and Euclidean. A separate sign assignment instructions can be executed for each division type. There is a sign assignment instruction for traditional division, a separate sign assignment instruction for modulo division, and a separate sign assignment instruction for Euclidean division. Such instructions are known and selected by a software programmer, compiler, etc. The various types of sign assignment instructions adjust the value of the QUO and REM such as by negating each such value, or by other forms of adjustment. The examples below illustrate various types of sign extraction and sign assignment instructions. 
         [0035]    As explained above, multiple different sign extraction instructions  108  can be executed by the processor. Some examples of sign extraction instructions are provided below in Table I. 
         [0000]    
       
         
               
             
               
               
               
             
           
               
                 TABLE I 
               
             
             
               
                   
               
               
                 Sign Extraction Instructions 
               
             
          
           
               
                 Instruction 
                 Microcode 
                 Explanation 
               
               
                   
               
               
                 ABSI32DIV32 R2H, R1H, R3H 
                 NI = R1H(31) 
                 For a signed 
               
               
                   
                 TF = (R1H(31)) {circumflex over ( )}(R3H(31)) 
                 numerator and signed 
               
               
                   
                 if ((R1H = 0x8000_0000) | 
                 denominator. 
               
               
                   
                   (R3H = 0x8000_0000)) { LVF = 1} 
                 32 bit division. 
               
               
                   
                  R2H = 0 
                 MSB of R1 saved as 
               
               
                   
                 if (R1H(31) = 1) {R1H = −R1H} 
                 NI 
               
               
                   
                 if (R3H(31) = 1) {R3H = −R3H} 
                 Ex-OR of MSBs of R1 
               
               
                   
                   
                 and R3 saved as TF. 
               
               
                   
                   
                 Overflow flag (LVF) is 
               
               
                   
                   
                 set if NUM or DEN is 
               
               
                   
                   
                 largest negative 
               
               
                   
                   
                 integer value. 
               
               
                   
                   
                 R2 initialized to 0. 
               
               
                   
                   
                 R1 and R3 negated if 
               
               
                   
                   
                 either is negative. R1 
               
               
                   
                   
                 is negated if R1 is 
               
               
                   
                   
                 negative and same is 
               
               
                   
                   
                 the case with R3. 
               
               
                 ABSI32DIV32U R2H, R1H, R3H 
                 NI = R1H(31) 
                 For a signed 
               
               
                   
                 TF = R1H(31) 
                 numerator and 
               
               
                   
                 if (R1H = 0x8000_0000) { LVF = 1} 
                 unsigned 
               
               
                   
                  R2H = 0 
                 denominator. 32 bit 
               
               
                   
                 if (R1H(31) = 1) {R1H = −R1H} 
                 division. 
               
               
                   
                   
                 MSB of NUM is saved 
               
               
                   
                   
                 as NI and TF, 
               
               
                   
                   
                 respectively. 
               
               
                   
                   
                 Overflow flag (LVF) is 
               
               
                   
                   
                 set if NUM is largest 
               
               
                   
                   
                 negative integer value. 
               
               
                   
                   
                 R2 initialized to 0. 
               
               
                   
                   
                 R1 negated if 
               
               
                   
                   
                 negative. 
               
               
                   
               
             
          
         
       
     
         [0036]    Table II below provides several examples of conditional subtraction instructions in accordance with the disclosed embodiments. 
         [0000]    
       
         
               
             
               
               
               
             
           
               
                 TABLE II 
               
             
             
               
                   
               
               
                 Conditional Subtraction Instructions 
               
             
          
           
               
                 Instruction 
                 Microcode 
                 Explanation 
               
               
                   
               
               
                 SUBC4UI32 R2H, R1H, R3H 
                 ZI =0 
                 32 bit unsigned div. 
               
               
                   
                 If (R3H = 0x0) {LVF = 1} 
                 Set LVF to 0 if 
               
               
                   
                 for(i=1;i&lt;=4;i++) { 
                 DEN = 0. 
               
               
                   
                  temp(32:0) = (R2H &lt;&lt; 1) + R1H(31) − 
                 Perform 4 iterations 
               
               
                   
                 R3H 
                 in a loop. Each loop 
               
               
                   
                  if(temp(32:0) &gt;= 0) 
                 left shifts R2, R1&#39;s 
               
               
                   
                   R2H = temp(31:0); 
                 MSB is shifted into 
               
               
                   
                   R1H = (R1H &lt;&lt; 1) + 1 
                 R2 and R2-R3 is 
               
               
                   
                  else 
                 computed as temp. If 
               
               
                   
                   R2H:R1H = (R2H:R1H) &lt;&lt; 1 
                 temp is &gt;= 0, R1-R3 
               
               
                   
                 } 
                 is stored in R2 and 
               
               
                   
                 If (R2H = 0x0) {ZI = 1} 
                 R1 is left shifted with 
               
               
                   
                   
                 1 inserted into Rts 
               
               
                   
                   
                 LSB. Otherwise, 
               
               
                   
                   
                 R2/R1 is left shifted. 
               
               
                   
                   
                 ZI flag is set and 
               
               
                   
                   
                 used in Euclidean 
               
               
                   
                   
                 and modulo division. 
               
               
                 SUBC2UI64 R2H:R4H, 
                 ZI = 0 
                 Similar to 
               
               
                 R1H:R0H, R3H:R5H 
                 If ((R3H:R5H) = 0x0) {LVF = 1} 
                 SUBC4UI32, but 64 
               
               
                   
                 for(i=1;i&lt;=2;i++) { 
                 bit division. 
               
               
                   
                  temp(64:0) = ((R2H:R4H) &lt;&lt; 1) + 
                   
               
               
                   
                 R1H(31) − (R3H:R5H) 
                   
               
               
                   
                  if(temp(64:0) &gt;= 0) 
                   
               
               
                   
                   (R2H:R4H) = temp(63:0); 
                   
               
               
                   
                   (R1H:R0H) = ((R1H:R0H) &lt;&lt; 1) + 
                   
               
               
                   
                 1 
                   
               
               
                   
                  else 
                   
               
               
                   
                 (R2H:R4H:R1H:R0H)=(R2H:R4H:R1H: 
                   
               
               
                   
                 R0H)&lt;&lt;1 
                   
               
               
                   
                 } 
                   
               
               
                   
                 If (R2H:R4H = 0x0) {ZI = 1} 
               
               
                   
               
             
          
         
       
     
         [0037]    Table III below provides several examples of sign assignment instructions in accordance with the disclosed embodiments. 
         [0000]    
       
         
               
             
               
               
               
             
           
               
                 TABLE III 
               
               
                   
               
               
                 Sign Assignment Instructions 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 NEGI32DIV32 R1H, R2H 
                 if(TF = TRUE) 
                 For traditional division. QUO 
               
               
                   
                  R1H = −R1H 
                 and REM are converted positive 
               
               
                   
                 if(NI = TRUE) 
                 to negative conversion as 
               
               
                   
                  (R2H) = −(R2H) 
                 needed as determined by states 
               
               
                   
                   
                 of TF and NI flags. 
               
               
                 ENEGI32DIV32 R1H, R2H 
                 IF (NI = 1 &amp;&amp; ZI = 0) { 
                 For Euclidean division. 
               
               
                   
                  R1H = R1H + 1 
                 NUM = DEN*QUO + REM, 0 ≦ 
               
               
                   
                  R2H = R3H-R2H 
                 REM &lt; |DEN| 
               
               
                   
                 } 
                 Remainder will always be 
               
               
                   
                 if(TF = TRUE) 
                 positive. 
               
               
                   
                  R1H = −R1H 
                 The case of (R1H = 
               
               
                   
                   
                 0x7FFF_FFFF) will be caught by 
               
               
                   
                   
                 the overflow flag setting during 
               
               
                   
                   
                 ABS operation itself and hence 
               
               
                   
                   
                 not required. 
               
               
                 MNEGI32DIV32 R1H, R2H 
                 if (TF = 1 &amp; ZI = 0) { 
                 Sign manipulation for Modulo 
               
               
                   
                  R1H = R1H + 1 
                 division. 
               
               
                   
                  R2H = R3H − R2H 
                 REM = NUM − 
               
               
                   
                 } 
                 DEN*floor(NUM/DEN). 
               
               
                   
                 if(TF = TRUE) 
                 Remainder will follow sign of 
               
               
                   
                  R1H = −R1H 
                 denominator 
               
               
                   
                 if(NI XOR TF = TRUE) 
                   
               
               
                   
                  (R2H) = −(R2H) 
               
               
                   
               
             
          
         
       
     
         [0038]    The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.