Abstract:
A method and system for storing data in a non-volatile memory having a plurality of memory regions each assigned with a serial address to permit serial accessing of the plurality of memory regions. Each memory region has a writing count number storing region and a data storing region. In accessing the non-volatile memory, contents of the writing count number storing regions are checked serially to locate an effective memory region having the last serial address among memory regions having the same writing count number. In writing data into the non-volatile memory, a memory region having an address following that of the located effective memory region will be accessed, and in reading data from the non-volatile memory, the located effective memory region will be accessed. The final address of the non-volatile memory is followed by the first address thereof, thus permitting circular or access to the serially addressed memory regions of the non-volatile memory.

Description:
This is a continuation of application Ser. No. 07/661,164 filed Feb. 27, 1991 which is now abandoned. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to a method and a system for storing data in a memory, and more particularly to, a method and a system for storing data in a memory in which data should be re-written a considerable number of times and should be maintained for a long time even in a state where the power supply is cut off. 
     BACKGROUND OF THE INVENTION 
     In a first conventional method for storing data which should be re-written a considerable number of times and should be maintained even in a state where the power supply is cut off, the data are stored in a volatile type memory such as a random access memory (RAM) which is backed up by a battery to maintain the data. The data can be re-written an unlimited number of times. 
     In a second conventional method for storing data which should be re-written a considerable number of times and should be maintained even in a state where the power supply is cut off, the data are stored in a non-volatile type memory such as an erasable programmable read only memory (EPROM) which maintains the data without backing up even in a state where the power supply is cut off. 
     According to the first and second conventional methods for storing data, however, there are disadvantages as described below. 
     In the first conventional method for storing data, the data can not be maintained for a long time in the state where the power supply is cut off, because the data may be volatilized if the battery is exhausted. 
     In the second conventional method for storing data, the number of times of re-writing is limited because of the property of the non-volatile type memory, so that there occurs a practical problem if the number of necessary times of re-writing is larger than that of possible times of re-writing of the non-volatile type memory. 
     SUMMARY OF THE INVENTION 
     Accordingly , it is an object of the invention to provide a method and a system for storing data in a memory in which data can be stored for a predetermined time in the state where the power supply is cut off even if the number of necessary times of re-writing data is larger than that of possible times of re-writing data of the non-volatile memory. 
     According to a first feature of the invention, a method for storing data in a memory includes the steps of 
     providing a memory having a plurality of memory regions for storing data and count numbers of writing the data thereinto, the plurality of memory regions being accessed by serial addresses assigned thereto, a last address of the serial address being followed by a first address of the serial addresses to convert the plurality of memory regions into circularly accessible memory regions, 
     locating an effective memory region from the circularly accessible memory regions by reference to the count numbers and the serial addresses, the effective memory region having a count number indicative of writing data thereinto at a latest time, and 
     accessing a memory region selected from the effective memory region and a memory region having an address next to that of the effective memory region, the effective region being selected for reading data therefrom, and the next address memory region being selected for wet tiny data thereinto. 
     According to a second feature of the invention, a system for storing data in a memory comprises: 
     a memory having a plurality of memory regions for storing data and count numbers of writing the data thereinto, the plurality of memory regions being provided with serial addresses, a last address of the serial addresses being followed by a first address of the serial addresses to convert the plurality of memory regions to circularly accessible memory regions, 
     a counter for counting a number of times of writing the data into each of the plurality of memory regions so as to provide count members, 
     A device for locating an effective region from the circularly accessible memory regions by reference to the count numbers and the serial address, the effective memory region having a count number indicative of writing data thereinto at a latest time, 
     a device for writing data into a memory region having an address next to that of the effective memory region, and 
     a device for reading data from the effective memory region. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be explained in more detail in conjunction with the appended drawings, wherein: 
     FIG. 1 is a block diagram showing a system for storing data in a preferred embodiment according to the invention; 
     FIG. 2 is a memory map of the EEPROM of the system for storing data in the preferred embodiment according to the invention; 
     FIG. 3 is an explanatory view showing a content of one memory region of the EFPROM of the system for storing data in the preferred embodiment according to the invention; 
     FIG. 4 is a flow chart showing operation of locating an address of an effective memory region in the memory regions of the EEPROM in the system for storing data in the preferred embodiment according to the invention; 
     FIG. 5 is a flow chart showing operation of reading out data from a memory region of the EEPROM in the system for storing data in the preferred embodiment according to the invention; and 
     FIG. 6 is a flow chart showing operation of writing data into a memory region of the EEPROM in the system for storing data in the preferred embodiment according to the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a block diagram showing a system for storing data in a preferred embodiment according to the invention. The system for storing data comprises a central processor unit (CPU) 10, a read only memory (ROM) 20, a random access memory (RAM) 30, and an electrically erasable programmable ROM (EEPROM) 40. These components are connected to each other by a bus line 50. 
     The CPU 10 comprises an address counter 11, a writing number counter 12, an arithmetic and logic unit (ALU) 13, and a control unit 14. The address counter 11 counts an address of a memory region in the EEPROM 40. The writing number counter 12 counts the number of times of writing data The ALU 13 carries out various arithmetic processes The control unit 14 controls reading and writing operations, and locates an effective address of a memory region in the EEPROM. 
     The ROM 20 stores programs by which the control of the CPU 10 is carried out. The RAM 30 stares data temporarily. The EEPROM 40, into which data can be written a limited number of times, stores data which should be re-written a considerable number of times and should be maintained even in a state where the power supply is cut off. 
     The EEPROM 40 has a plural number N of memory regions M(0), MR(1), MR(N-1) which have serial addresses 0, 1, . . . , N-1. FIG. 2 is a memory map of the EEPROM of the system for storing data in FIG. 1. The number N of the memory regions MR(0), MR(1), . . . , MR(N-1) has a value as following. 
     N≧N 1  /N z   
     Here, N.sub. is defined as the number of necessary times of writing data, and N z  is defined as the number of maximum possible times of writing data to the EEPROM 40. 
     FIG. 3 is an explanatory view showing a content of one memory region MR(i) of the EEPROM 40, where i is an integer between 0 to N-1. The memory region MR(i) has a writing count number storing region CR(i) having a predetermined number of bits for storing a writing count number C i  of the writing number counter 12 and a data storing region DR(i) for storing data D i . 
     In operation, all contents of the writing count number storing regions of the memory regions are checked to locate an effective memory region which has the last address in a group of the memory regions each of which stores a writing count number equal to that stored in a first memory region which has the first address in the group of the memory regions. 
     In the writing operation, a count number and data are written into the writing count number storing region and the data storing region of a memory region which has an address next to that of the effective memory region. The writing count number has a value which is the result of adding one to the writing count number stored in the writing count number storing region of the first memory region if the effective memory region is a last memory region which has the last address in the memory regions, and a value which is the same as that stored in the writing count number storing region of the first memory region if the effective memory region is not the last memory region. 
     In the reading operation, the writing count number and the data are read out from the effective memory region if the effective memory region exists. 
     FIG. 4 is a flow chart showing operation of searching the memory regions MR(0), MR(1) . . . , MR(N-1) for locating an address of an effective memory region. This searching operation is carried out as a subroutine. 
     In operation, a content of a number j is set to &#34;0&#34; in a step 101, and a content of a writing count number counter C X  is set to be equal to the writing count number C O  of the first memory region MR(0) in a step 102. Then, j is added by one in a step 103, and it is judged whether j is equal to N in a step 104. If it is, then j is set to be N-1 which is the final address in the memory regions in a step 105, and then the operation is returned to the main operation. If it is not, then it is judged if C x  is equal to C j  in so step 106. If it is so, then the operation is re-started from step 103. If it is not, then j is subtracted by one to get an address of the effective memory region in step 107. As a result, the address of the effective memory region is found out as the number j. 
     FIG. 5 a is a flow chart showing operation of reading out data from the effective memory region in the EEPROM. 
     In operation, first, the searching subroutine 100 shown in FIG. 4 is carried out to locate an address of the effective memory region. Then, i is set to be the address of the effective memory region located in the subroutine 100 in step 110. After that, the data D i  is read out from a data storing region DR(i) of the effective memory region MR(i) in step 111. 
     FIG. 6 is a flow chart showing the operation of writing data into a memory region having an address next to that of the effective memory region in the EEPROM. 
     In operation, first, the searching subroutine 100 is carried out to find an address of the effective memory region. Then, i is set to be the address of the effective memory region located in the subroutine 100 in step 120. Then, C x  is set to be equal to C i  in step 121, and then i is added by one in step 122. Then, it is judged whether i is equal to N in step 123. If it is, then i is set to be &#34;0&#34; and C x  is added by one in step 124, and then data D i  which is D 0  is written into a data storing region DR(i) which is DR(0) of the memory region MR(i) which is MR(0) in step 125. If it is not, then the step 125 is carried out directly without changing i and C x . In this case, data D i  is written into a data storing region DR(i) of the memory region MR(i) which has the next address to that of the effective memory region. After step 125, the writing count number counter C x  is written into a writing count number storing region CR(i). The memory region MR(i) to which the writing count number C i  and the data D i  are newly written is defined as a new effective memory region. 
     Next, a practical example of selecting a memory region from a group of memory regions will be described. Here, it is supposed that the contents of the writing count number storing regions are defined as C k  (k=0, 1, . . . , N-1), and the writing count number C k  consists of 8-bits, however, a 2-bit number or 3-bit number is generally sufficient as the writing count number. The following table shows examples of contents of C 0 , C 1 , . . . , C N-1  by describing in hexadecinormal digits. 
     
         __________________________________________________________________________STATE-1   STATE-2           STATE-3                 STATE-4                       STATE-5                             STATE-6                                   STATE-7__________________________________________________________________________C.sub.N-1    FF    FF    02    02    02    03    03C.sub.N.sub.-2    FF    FF    02    02    02    03    03.   .     .     .     .     .     .     ..   .     .     .     .     .     .     ..   .     .     .     .     .     .     .C.sub.k+3    FF    FF    02    02    02    03    03C.sub.k+2    FF    FF    02    02     03   03    03C.sub.k+1    FF    FF    02     03   03    03    03C.sub.k    FF    FF     03   03    03    03    03C.sub.k-1    FF    FF    03    03    03    03    03.   .     .     .     .     .     .     ..   .     .     .     .     .     .     ..   .     .     .     .     .     .     .C.sub.1    FF    FF    03    03    03    03    03C.sub.0    FF     00   03    03    03    03     04__________________________________________________________________________ 
    
     Generally, eight bits of writing count number storing regions in the EEPROM 40 are &#34;11111111&#34; in an initial state. Therefore, (C o , C 1 , . . . , C N-1  are all described as &#34;FF&#34; in hexadecinormal digits shown as the STATE 1 in the Table. When the first writing operation is carried out, the memory region MR(0) is selected. For this purpose, the content of the writing count number C 0  is changed to &#34;00&#34; (&#34;00000000&#34;) as shown in the STATE 2 in the Table. At the same time, the data D 0  is written into the data storing region DR (0) of the memory region MR (0) . 
     In the STATE 3, contents of C O  to C k  are &#34;03&#34; (&#34;00000011&#34;) and contents of C k+1 , to C N-1 , are &#34;02&#34; (&#34;00000010&#34;), so that an effective memory region is MR(k), because the content of the writing count number C K  is the same as that of the writing count number C 0  and has the last address in the writing count numbers which have the same contents as that of the Writing count number C 0 . If the writing operation is carried out, the contents of the writing count numbers changes to the STATE 4, and then the STATE 5. If the writing count number &#34;03&#34; is written into the writing count number storing region of the memory region MR(N-1) as shown in the STATE 6, then the writing count number C 0  is added to be &#34;04&#34; by one as shown in the STATE 7. 
     As shown in the Table, the memory region MR(0), MR(k), MR(k+1) MR(k+2) and MR(0) are effective, memory regions, respectively, in the STATES 2, 3, 4, 5 and 7 as indicated by underlined writing count numbers. Thus, data are read from the effective memory regions, while data are written into memory regions having addresses next to those of the effective memory regions. In the above table, data can be re-written into each memory region a predetermined number of times equal to or less than 126 (FF) times depending on a re writing property of EEPROM. 
     Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not limited to this embodiment and alternative constructions may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.