Abstract:
In some examples, a semiconductor device includes a substrate, a first doped region formed in the substrate, a second doped region around and spaced apart from the first doped region, and a channel between the first and second doped regions and formed using a gate ring on the substrate as a mask. A gate is formed over only a portion of the channel, the gate being a portion of the gate ring.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This is a division of U.S. application Ser. No. 14/913,980, having a national entry date of Feb. 23, 2016, which is a national stage application under 35 U.S.C. §371 of PCT/US2013/057482, filed Aug. 30, 2013, which are both hereby incorporated by reference in their entirety. 
     
    
     BACKGROUND 
       [0002]    Inkjet technology is widely used for precisely and rapidly dispensing small quantities of fluid. Inkjets eject droplets of fluid out of a nozzle by creating a short pulse of high pressure within a firing chamber. During printing, this ejection process can repeat thousands of times per second. Inkjet printing devices are implemented using semiconductor devices, such as thermal inkjet (TIJ) devices or piezoelectric inkjet (PIJ) devices. For example, a TIJ device is a semiconductor device including a heating element (e.g., resistor) in the firing chamber along with other integrated circuitry. To eject a droplet, an electrical current is passed through the heating element. As the heating element generates heat, a small portion of the fluid within the firing chamber is vaporized. The vapor rapidly expands, forcing a small droplet out of the firing chamber and nozzle. The electrical current is then turned off and the heating element cools. The vapor bubble rapidly collapses, drawing more fluid into the firing chamber. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    Some embodiments of the invention are described with respect to the following figures: 
           [0004]      FIG. 1  is a block diagram of an ink jet printer according to an example implementation. 
           [0005]      FIGS. 2A through 2C  illustrate cross-sections of a semiconductor device according to an example implementation. 
           [0006]      FIGS. 3A and 3B  show a top view and cross-section view respectively of a semiconductor device according to an example implementation prior to partial gate etching. 
           [0007]      FIGS. 4A and 4B  show a top view and cross-section view respectively of a semiconductor device according to an example implementation after partial gate etching. 
           [0008]      FIG. 5A  is a schematic showing a circuit of transistors according to an example implementation. 
           [0009]      FIG. 5B  is a top view of the circuit of  FIG. 5  as formed on a substrate prior to partial gate etching according to an example implementation. 
           [0010]      FIG. 6  is a flow diagram of a method of forming a semiconductor device according to an example implementation. 
           [0011]      FIG. 7  is a flow diagram of a method of forming transistors in a substrate according to an example implementation. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]      FIG. 1  is a block diagram of an ink jet printer  102  according to an example implementation. The ink jet printer  102  includes a print controller  106  and a printhead  108 . The print controller  106  is coupled to the printhead  108 . The print controller  106  receives printing data representing an image to be printed to media (media not shown for clarity). The print controller  106  generates signals for activating drop ejectors on the printhead  108  to eject ink onto the media and produce the image. The print controller  106  provides the signals to the printhead  108  based on the printing data. 
         [0013]    The print controller  106  includes a processor  120 , a memory  122 , input/output (IO) circuits  116 , and various support circuits  118 . The processor  120  can include any type of microprocessor known in the art. The support circuits  118  can include cache, power supplies, clock circuits, data registers, and the like. The memory  122  can include random access memory, read only memory, cache memory, magnetic read/write memory, or the like or any combination of such memory devices. The  10  circuits  116  can by coupled to the printhead  108 . The  10  circuits  116  can also be coupled to external devices, such as a computer  104 . For example, the  10  circuits  116  can receive printing data from an external device (e.g., the computer  104 ), and provide signals to the printhead  108  using the  10  circuits  116 . 
         [0014]    The printhead  108  includes a plurality of drop ejectors  110  and associated integrated circuitry  111 . The drop ejectors  110  are in fluidic communication with an ink supply (not shown) for receiving ink. For example, ink can be provided from a container. In an example, the printhead  108  is a thermal ink jet (TIJ) device. The drop ejectors  110  generally include a heating element, a firing chamber, and a nozzle. Ink from the ink supply fills the firing chambers. To eject a droplet, an electrical current generated by the circuits  111  is passed through the heater element placed adjacent to the firing chamber. The heating element generated heat, which vaporizes a small portion of the fluid within the firing chamber. The vapor rapidly expands, forcing a small droplet out of the firing chamber and nozzle. The electrical current is then turned off and the resistor cools. The vapor bubble rapidly collapses, drawing more fluid into the firing chamber from the ink supply. 
         [0015]    The circuits  111  include various circuit elements and conductors formed as part of an integrated circuitry on the printhead  108 . In particular, the circuits  111  include transistors  112  used for various purposes, such as providing signals to the drop ejectors or implementing higher-level circuits, such as logic gates, shift registers, address generators, multiplexers/demultiplexers, on-chip memory, and the like. In some circuits, multiple transistors are laid out in proximity to one another (e.g., a cascade arrangement of transistors). In a standard complementary metal oxide semiconductor (CMOS) process, transistors are isolated from one another using a field oxide (FOX), shallow trench isolation (STI), deep trench isolation (DTI), or the like. Some printheads, however, are manufactured using a no-field oxide process for cost reduction. Since there is no field oxide (or similar feature) isolating individual transistors, the transistors must be laid out with an enclosed gate structure. 
         [0016]    For example, in an N-type metal oxide semiconductor (NMOS) no-field oxide process, a gate is formed as a ring on a semiconductor substrate. An inner doped region is formed in the substrate inside the ring and an outer doped region is formed outside the ring separated from the inner doped region by a channel. The inner and outer doped regions act as drain and source of the transistor. If two or more transistors are cascaded and share a common source/drain, additional gate ring(s) must be concentrically arranged on the substrate. This transistor layout is not efficient in terms of area as compared to industry CMOS design having FOX or the like. Further, layout becomes more complicated, requires more semiconductor area, and increases cost. Examples discussed below improve the efficiency of transistor layout in a no-field oxide process by forming transistors using a partially etched gate NMOS transistor process, which requires less semiconductor area for higher packing density and for reduces manufacturing cost. Also, due to the smaller size capacitance, the resulting device exhibits increase electrical speed. 
         [0017]      FIGS. 2A through 2C  illustrate cross-sections of a semiconductor device according to an example implementation. The cross-sections show the device after different steps of a NMOS transistor process. As shown in  FIG. 2A , the device includes a substrate  202  having a gate oxide (GOX)  204  deposited thereon. A polysilicon layer  206  is deposited on the GOX layer  204 . The polysilicon layer  206  acts as a hard mask to produce N+ doped regions  210  and  212  in the substrate  202  and the polysilicon layer  206  will be in-situ doped for lower resistance. A dielectric layer  208  is deposited over the polysilicon layer  206 . The dielectric layer  208  can be any type of insulator material, such as phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). 
         [0018]    As shown in step  FIG. 2B , the dielectric layer  208  is masked using a photolithographic technique, such as use of a contact mask, and etched to produce an exposed portion  214  of the polysilicon layer  206 . The etch can be designed to stop at the polysilicon layer  206  using etch control and selectivity techniques. 
         [0019]    As shown in  FIG. 2C , a metal layer  216  is deposited on the dielectric layer using a mask that covers at least the exposed portion  214  of the polysilicon layer  206 . Thus, no metal is deposited on the exposed portion  214  of the polysilicon layer  206 . The metal layer  216  is etched to form a conductor pattern. The etching process of the metal layer  216  will also remove the exposed portion  214  of the polysilicon layer  206  and some of the dielectric layer  208  to produce a break  218  in the polysilicon layer  206 . This general process, referred to as a partially etched gate NMOS transistor process, can be used to remove unwanted gate portions after doping, as discussed below. 
         [0020]      FIGS. 3A and 3B  show a top view and cross-section view respectively of a semiconductor device according to an example implementation. The semiconductor device includes a substrate  308  having a GOX layer  310  deposited thereon. A polysilicon layer is formed on the GOX layer  310  having a polysilicon ring  302 . The polysilicon ring  302  has a section  302 A and a section  302 B. Doped regions  304  and  306  are formed in the substrate  308  to provide drain and source for a transistor. In particular, the doped region  306  includes a section  306 A and  306 B. After the doped regions  304  and  306  are formed, the section  302 B can be removed using the process partial-etch process described above in  FIG. 2 . The resulting transistor structure is shown in  FIGS. 4A and 4B . 
         [0021]    As shown in  FIG. 4 , the section  302 B is removed. A transistor is formed from the doped region  306 A, the section  302 A of polysilicon, and the doped region  304  (e.g., source, gate, and drain, respectively). The doped region  304  is isolated from the doped region  306 B because the section  302 B of polysilicon has been removed (i.e., there is no gate spanning the channel between doped region  304  and doped region  306 B). Thus, the gate ring  302  is used to form the doped regions for the transistor (source and drain) and the unwanted portion (e.g., the section  302 B) of the polysilicon ring is removed thereafter using the partial-etch process described above. Thus, transistor layouts can be provided to conserve silicon area and cost. When two or more transistors are cascaded, there is no need to build a ring in ring design, as shown below. 
         [0022]      FIG. 5A  is a schematic showing a circuit  500  of transistors according to an example implementation. The circuit  500  includes three transistors Q 1 , Q 2 , and Q 3  in a cascade arrangement.  FIG. 5B  is a top view of the circuit  500  as formed on a substrate prior to partial gate etching according to an example implementation. The layout includes polysilicon gate segments  502  and doped regions  506 . A polysilicon ring  504 , used when forming the doped regions  506 , is removed using the partial etching process described above. In this manner, a ring-in-ring structure is not required to produce a layout of cascaded transistors, saving silicon area and cost. 
         [0023]      FIG. 6  is a flow diagram of a method  600  of forming a semiconductor device according to an example implementation. The method  600  begins at step  602 , where a polysilicon layer is deposited on a substrate having at least one polysilicon ring. At  604 , the substrate is doped using the polysilicon layer as a mask to form doped regions in the substrate. At step  606 , a dielectric layer is deposited over the polysilicon layer and the substrate. At step  608 , the dielectric layer is etched to expose portions of the polysilicon layer. At step  610 , a metal layer is deposited over the dielectric layer. In examples, the metal layer is not deposited over at least the exposed portions of the polysilicon layer. At step  612 , the metal layer, dielectric layer, and the exposed portions of the polysilicon layer such that at least a portion of the polysilicon ring is removed. 
         [0024]      FIG. 7  is a flow diagram of a method  700  of forming transistors in a substrate according to an example implementation. The method  700  begins at step  702 , where a gate layer is formed on the substrate having at least one gate ring. At step  704 , the substrate is doped to form source and drain regions. At step  706 , a dielectric layer is formed over the gate layer and the substrate. At step  708 , the dielectric layer is etched to expose portions of the gate layer. At step  710 , a metal layer is deposited on the dielectric layer. In examples, the metal layer is not deposited over at least the exposed gate portions. At step  712 , the metal layer, dielectric layer, and the exposed gate portions are etched such that at least a portion of the gate ring is removed. 
         [0025]    In the foregoing description, numerous details are set forth to provide an understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these details. While the invention has been disclosed with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover such modifications and variations as fall within the true spirit and scope of the invention.