Abstract:
A multilayer printed circuit board comprising: i) a plurality of circuit board layers disposed in parallel planes to one another; ii) an outer via forming an electrical connection between a conductor contact on a first circuit board layer and a conductor contact on a second circuit board layer, wherein the outer via has a hollow central core; and iii) an inner via formed within the hollow central core of the outer via. The inner via forms an electrical connection between a conductor contact on a third circuit board layer and a conductor contact on a fourth circuit board layer. The inner via and the outer via are substantially concentric cylinders.

Description:
TECHNICAL FIELD 
       [0001]    The present application relates generally to printed circuit boards and, more specifically, to a via-within-via structure for connecting different layers of a printed circuit board. 
       BACKGROUND 
       [0002]    Many computer systems and communication applications operate at multi-gigabit speeds. Such high speeds pose unique challenges to hardware designers, particularly with respect to multi-layer printed circuit boards. A printed circuit board (PCB) provides a compact means for routing signals between circuit components mounted on the PCB. However, printed circuit boards that support multi-gigabit/second digital signals require significant signal integrity. Signal integrity is a major issue not only in high-speed digital electronics, but also in high frequency RF systems. While a printed circuit board is efficient at creating a two-dimensional (planar) structure, a PCB is less efficient for three-dimensional structures. 
         [0003]    A via is typically used to provide a connection between signal traces on different layers of the printed circuit board. For example, a via is needed to route signal traces between components mounted on opposite sides of the PCB. But, as signal frequencies increase, the wavelength of the signal decreases. Physical dimensions greater than, for example, 1/10 th  of a wavelength may degrade the signal as the signal propagates through a printed circuit board. Signal degradation results in unwanted signal loss, ripple, and distortion. Moreover, multiple traces on a densely routed PCB are often adjacent to each other, which causes unwanted signal coupling. Good shielding of the traces is required to prevent coupling. 
         [0004]    Therefore, there is a need for printed circuit boards that reduce signal degradation and improve signal integrity at high frequencies. In particular, there is a need for improved via structures for use in multi-layer printed circuit boards. 
       SUMMARY 
       [0005]    To address the above-discussed deficiencies of the prior art, it is a primary object to provide a multilayer printed circuit board comprising: i) a plurality of circuit board layers disposed in parallel planes to one another; ii) an outer via forming an electrical connection between a conductor contact on a first circuit board layer and a conductor contact on a second circuit board layer, wherein the outer via has a hollow central core; and iii) an inner via formed within the hollow central core of the outer via, wherein the inner via forms an electrical connection between a conductor contact on a third circuit board layer and a conductor contact on a fourth circuit board layer. 
         [0006]    In one embodiment, the outer via has a circular cross-section. 
         [0007]    In another embodiment, the inner via has a circular cross-section. 
         [0008]    In still another embodiment, the outer via has a substantially cylindrical shape. 
         [0009]    In yet another embodiment, the inner via has a substantially cylindrical shape. 
         [0010]    In a further embodiment, the inner via and the outer via are substantially concentric cylinders. 
         [0011]    In a still further embodiment, the inner via is connected to a signal trace on the third circuit board layer and the signal trace is associated with an impedance matching network. 
         [0012]    Before undertaking the DETAILED DESCRIPTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts: 
           [0014]      FIG. 1  illustrates a perspective view of a via-in-via structure for use in a printed circuit board (PCB) according to the principles of the present disclosure. 
           [0015]      FIG. 2  illustrates a perspective view of a via-in-via structure and two exemplary layers of a printed circuit board (PCB) according to an embodiment of the disclosure. 
           [0016]      FIG. 3  illustrates a cross-sectional view of a via-in-via structure in a multi-layer printed circuit board (PCB) according to an embodiment of the disclosure. 
           [0017]      FIG. 4  illustrates a side view of a via-in-via structure in a multi-layer printed circuit board (PCB) according to an embodiment of the disclosure. 
           [0018]      FIG. 5  illustrates a top view of a via-in-via structure in a multi-layer printed circuit board (PCB) according to an embodiment of the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]      FIGS. 1 through 5 , discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged printed circuit board (PCB). 
         [0020]    The present disclosure describes a via-in-via structure that provides a well-shielded, low-loss transition of high frequency signals through multiple layers of a printed circuit board. A via-in-via structure is created by drilling an inner via having a smaller diameter inside an outer via having a larger diameter. For example, a coaxial transmission line may be created by drilling a larger diameter via in a PCB as the outer wall of the coaxial transmission line. A smaller diameter via drilled inside the larger via creates the inner conductor of the coaxial transmission line. Other structures are possible with this technique include twin-axial transmission lines. 
         [0021]    The larger diameter via is formed by drilling a hole in the printed circuit board and conductively plated to a known thickness, which defines the outer diameter of the coaxial transmission line. The larger via is then filled with a non-conductive filler, such as an epoxy with a known dielectric constant. The inner via diameter is selected to provide the desired signal impedance, which is a function of the outer diameter, the inner diameter, and the dielectric constant of the filler. 
         [0022]    To further reduce the physical size of the coaxial via-in-via structure, a low-valued characteristic impedance may be selected for the dimensions. Signal traces of a fixed impedance transition into and out of the via-in-via structure by way of a via in capture pad  150 . The capture pad  150  may capacitively couple to an adjacent ground plane layer. The PCB stack-up implementation determines the length of the via and the size of capture pad  150 . These features transitioning from the signal layer into the coaxial transmission line mode may create a substantial reflection. In addition, the signal trace impedance may differ from that of the via-in-via structure, also contributing to reflection of the signal. . Matching networks may be used to phase-match the reflections caused by the transition between the via-and-via structure and the signal trace. For example, an open stub may be placed on the signal trace on the layer where the signal trace transitions into the center via of the coaxial via-in-via structure. Additionally, a hole inserted into the adjacent ground plane layer immediately above the capture pad may improve the match as well. 
         [0023]      FIG. 1  illustrates a perspective view of via-in-via structure  100  for use in a printed circuit board (PCB) according to the principles of the present disclosure. In  FIG. 1 , the layers of a multi-layer PCB are not shown for clarity of explanation. Via-in-via structure  100  comprises outer via  110  and inner via  120 , which is disposed inside of outer via  110 . One end of inner via  120  is connected to signal trace  130  by capture pad  150 . The other end of inner via  120  is connected to signal trace  140  by another capture pad (not shown). Alternatively, either end or both ends of inner via  120  may be connected to a metallization layer, such as a ground plane or power supply plane. 
         [0024]    In an advantageous embodiment, inner via  120  and outer via  110  may be aligned in a manner similar to concentric cylinders. However, in alternate embodiments, inner via  120  may be positioned off-center within outer via  110 . Moreover, in alternate embodiments, inner via  120  and/or outer via  110  may not have a circular cross-sectional area. If different cutting or etching tools are used, inner via  120  or outer via  110  may have a cross-sectional area that is a square, a rectangle, or another shape. 
         [0025]      FIG. 2  illustrates a perspective view of via-in-via structure  100  and exemplary layers  210  and  220  of printed circuit board (PCB)  200  according to an embodiment of the disclosure. In  FIG. 2 , upper layer  210  and lower layer  220  represent the circuit conductor contacts (e.g., metallization layers, signal traces) that are intended to make contact with outer via  110 . The substrate portion (e.g., epoxy) of each layer is omitted for clarity. 
         [0026]    Upper layer  210  is aligned with the top end of outer via  110  and lower layer  220  is aligned with the bottom end of outer via  110 . It is intended for both layers  210  and  220  to be metalized up to and including the outer circumference of via  110 . Layer  210  provides a ground reference for signal trace  130  and layer  220  provides a ground reference for signal trace  140 . The ohmic contact between layer  210  and via  110  and the ohmic contact between layer  220  and via  110  provide a low-impedance ground path for both signal traces on signal traces  130  and  140 . If the impedance of signal trace  130  is different than the impedance of coaxial via-in-via structure  100 , then matching network  230  may be added to signal trace  130  to match impedances. Signal trace  130  is separated from upper layer  210  by the substrate portion (not shown) of the layer on which signal trace  130  is disposed. 
         [0027]      FIG. 3  illustrates a cross-sectional view of via-in-via structure  100  and multi-layer printed circuit board (PCB)  200  according to an embodiment of the disclosure. In  FIG. 3 , additional layers  351 - 356  are shown between upper layer  210  and lower layer  220 . As in  FIG. 2 , layers  351 - 356  represent the circuit conductor contacts (e.g., metallization layers, signal traces) that are intended to make contact with outer via  110 . The substrate portion (e.g., epoxy) of each layer is omitted for clarity. 
         [0028]    Also shown in  FIG. 3  are top layer  310 , bottom layer  320 , and ground planes  390  and  395 . To reduce coupling, hole  340  is cut in ground plane  390  above capture pad  150 . At the opposite end of inner via  110 , hole  341  is similarly cut in ground plane  395  below capture pad  350  for trace  140 . 
         [0029]      FIG. 4  illustrates a side view of via-in-via structure  100  in multi-layer printed circuit board  200  according to an embodiment of the disclosure. In  FIG. 4 , a plurality of smaller vias connects different layers. For example, via  411  connects top layer  310  and upper layer  210 , and vias  412  and  413  connect ground plane  390  and upper layer  210 . Similarly, vias  421  and  422  connect bottom layer  310  and lower layer  220 , and via  423  connects ground plane  395  and bottom layer  220 . The plurality of vias establishes continuity between ground layers and signal containment within individual signal layers. 
         [0030]      FIG. 5  illustrates a top view of via-in-via structure  100  in multi-layer printed circuit board (PCB)  100  according to an embodiment of the disclosure. In  FIG. 5 , signal trace  130  is coupled to capture pad  150  through matching network  230 . The tops of a plurality of vias are visible on upper layer  210 , including vias  411 ,  412  and  412 . Capture pad  150  is connected to one end of inner via  120  (not visible). 
         [0031]    Although the present disclosure has been described with an exemplary embodiment, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.