Abstract:
A selector switch may be controlled by a single-ended control signal for steering a current through a load or through an auxiliary line. The selector switch may include a first terminal to be coupled to the load, and a second terminal to be connected to the auxiliary line, and two analog switches coupled to respective ones of the first and second terminals and configured to implement a single pole double throw switch so that a conduction or non-conduction state is determined by the single-ended control signal for steering the current through the load or the auxiliary line. The selector switch may also include a circuit defining a positive feedback loop controlling the two analog switches.

Description:
FIELD OF THE INVENTION 
   This invention relates to selector switches for radar systems, and, more particularly, to a selector switch controlled by a single-ended control signal for steering a current from a load to an auxiliary path and vice versa. 
   BACKGROUND OF THE INVENTION 
   The demand of pulse radars and short-range sensors capable of detecting obstacles or levels of liquid with a resolution smaller than 0.1 m is increasing and manufacturers offer integrated radio frequency transceivers that operate in the microwave range. In a pulse radar system, short radio frequency pulses are transmitted to the antenna, are reflected by the obstacle and are then detected by the receiver. From the delay of the received echo, the distance of the target may be calculated by multiplying the speed of the light by half of the delay time. 
   The minimum detectable delay time equals the duration of the radio frequency pulse. As a consequence, the duration of the radio frequency pulse determines the minimum distance that the sensor may detect. Targets closer than this minimum distance would cause a superposition between the transmitted signal and the received echo signal. 
   Many techniques for generating very fast radio frequency pulses are available in literature. For instance, there are pulse radar systems that generate radio frequency bursts by switching on/off a high frequency oscillator that is generally realized with GaAs devices or Gunn oscillators as disclosed in U.S. Pat. Nos. 6,414,627 and 4,470,049. The oscillator is enabled for detecting the echo signal at the receiver side by controlling the input of the local oscillator either of the sampler or of the mixer. 
   The minimum detectable distance is determined by the switching time of the oscillator that is proportional to the attenuation time constant of the oscillator, and to the quality factor of the resonant circuit used for tuning the oscillator. 
   Generally, integrated radio frequency transceivers include a single reference low frequency oscillator and a PLL (Phase Locked Loop) for generating the high frequency pulse signal. In practice, the high frequency oscillator works in a continuous functioning mode and not in a discontinuous functioning mode, and the radio frequency bursts may be generated by introducing switches along the transmission path. This method has been disclosed in U.S. Pat. No. 5,239,309 by combining different spectral components of the pulse signal coming from different PLLs. 
   In transmissions with TDMA protocols that are largely used in wireless systems, switches are required. The so-called single-pole double-throw switches (SPDT) are largely used at the end of the transmission path. They are realized with diodes or with GaAs active devices or with CMOS devices. CMOS devices are preferred because they may not require input bias currents and have smaller costs and power consumption than the former ones. 
   A typical SPDT switch is shown in  FIG. 1 . It is controlled by the signal VCTRL that alternately connects the antenna to the TX transmission line or to the reception line RX. This switch has a low insertion loss of the signal to be transmitted when the respective switch is in a conduction state, and isolates the switch from the transmission line when the transistor is turned off. In the latter situation, the transmission line is connected to a reference potential and a strong impedance mismatch may be present. 
   Typically, a VCO coupled with a tuned reactive load generates an oscillating signal at a certain frequency on the transmission line. By switching the transmission line from the antenna and the reference potential, the line connected to ground functions as a reactive load in parallel to the tuned load that modifies the oscillation frequency of the VCO. Moreover, this load variation starts a transient that must be left to decay. Therefore, the pulses sent to the antenna should last at least a certain or minimum time. In addition, the selector switch of  FIG. 1  needs a differential control signal and balancing this signal at high switching frequencies is not easy and typically requires a complex circuit. 
   A selector switch SPST with shorter switching times, disclosed in P. R. Gray and R. G. Meyer, Analysis and Design of Integrated Circuits, 2nd ed. New York: Wiley 1984, is depicted in  FIG. 2 . It is inserted at the beginning of the transmission line to the antenna, symbolically represented with a differential load LOAD. The depicted selector switch transfers the differential signal VIN+, VIN− to be transmitted to the load LOAD or to a dummy line, depending on the level of the differential control signal VCTRL+, VCTRL−. 
   This selector switch is burdened by drawbacks due to the Miller effect that limits the speed of the response of the transistors M 2  and M 3  and, as a consequence, the speed of the response to the variations of the input impedance between the on state and the off state. A remedy may include installing on the auxiliary line DUMMY LOAD an impedance (not depicted in the figure) equal to the load LOAD. 
   A generally known architecture of a selector switch that prevents variations of the input impedance seen by the local oscillator that generates the signal VIN is depicted in  FIG. 3 . It substantially exploits a so-called current steering technique for switching the single-ended input signal VIN on the load LOAD. 
   The performance of this type of selector switch is not limited by the Miller effect, because the transistors controlled by the differential control signal always see the same load whichever is the single-ended input voltage VIN. 
   Even in this case, a high frequency differential control signal VCTRL+, VCTRL− is necessary that is difficult to generate in a perfectly balanced manner. Moreover, switching times are determined exclusively by the pass band of the transistors of the differential pair. 
   SUMMARY OF THE INVENTION 
   The present invention provides an architecture of a very fast selector switch suitable for transferring an input signal to a load in an on/off mode. The selector switch is very simple to be realized, may be controlled by a single ended signal, and allows generating pulses at frequencies of the order of tenths of GHz. 
   This extraordinary result may be substantially due to the selector switch comprising a positive feedback switching stage that steers a current from a load to an auxiliary line and vice versa. Therefore, switching times are significantly reduced. 
   Moreover, it may not be necessary to use balanced differential control signals for driving the switches, but it is sufficient to make the single-ended control signal of the switch modify the working point as much as needed to make the feedback loop enter an unstable state. With this technique, a self-excited phenomenon begins and very rapidly increases thereby causing the switch that was off to turn on and the switch that was on to turn off. 
   Preferably, the positive feedback stage is realized with a differential amplifier that controls the switches and realizes with them a positive feedback loop. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be described referring to the attached drawings, wherein: 
       FIG. 1  shows a known SPDT switch as in the prior art; 
       FIG. 2  shows a known SPST switch as in the prior art; 
       FIG. 3  show a known selector switch that uses the so-called current steering technique as in the prior art; 
       FIG. 4  shows an embodiment of the selector switch of the invention for steering the current generated by a cascode stage; 
       FIG. 5  shows a second embodiment of the selector switch of the invention for steering the current generated by a cascode stage; 
       FIG. 6  shows a third embodiment of the selector switch of the invention for steering the current generated by a cascode stage; 
       FIG. 7  is a graph of the output voltage of the selector switch of  FIG. 5  as a function of the control voltage VCTRL; 
       FIG. 8  is a possible time graph of the output voltage of the selector switch of  FIG. 5  following a step variation of the control voltage VCTRL; 
       FIG. 9  shows a differential switching device of this invention including two selector switches of  FIG. 6 ; and 
       FIG. 10  shows a mixer of this invention that employs two selector switches of  FIG. 6 . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   An embodiment of the selector switch of this invention is depicted in  FIG. 4 . It substantially comprises a pair of switches SW 1  and SW 2  connected to circuit means or a circuit such as to be controlled through a positive feedback loop. In the example shown in  FIG. 4 , this circuit comprises a differential output amplifier OA that controls both switches SW 1  and SW 2 . 
   The differential amplifier OA generates on its two outputs an amplified replica of the difference between the single-ended control signal VCTRL of the selector switch and the voltage present on the terminal B of the selector switch. The output voltages of the operational amplifier OA control the switches SW 1  and SW 2 , such that the current Io, that in the depicted example is generated by a cascode stage V/I CONVERTER controlled by a signal Vin, is steered from the terminal A to the terminal B of the selector switch and vice versa. 
   The selector switch works with a common single-ended control signal VCTRL, therefore it is not burdened by the stringent balance requirements of the known selector switches of  FIGS. 1 to 3 . In fact, the voltages on the control nodes of the switches need not be balanced, as in the prior art selector switches of  FIGS. 2 and 3 . As a matter of fact, it is sufficient that one of control voltages of the two switches exceeds the other for starting a positive feedback evolution. Such a self-excited evolution amplifies itself and leads to the closing of a switch and to the opening of the other switch, thus switching the current Io from the load LOAD to the auxiliary line DUMMY LOAD and vice versa. 
   More particularly, let us suppose that when the control voltage VCTRL exceeds the voltage on the node B to which the auxiliary line is connected, the switch SW 1  is on and the switch SW 2  is off. As soon as the control signal VCTRL drops below the voltage on the node B, the switch SW 2  results in being controlled with a voltage larger than that of the switch SW 1 , thus the current flowing through SW 2  is larger than the current flowing through SW 1 . As a consequence, the voltage on the node B increases and the switch SW 2  is controlled by an even larger voltage than the voltage that controls the switch SW 1 . This process will reach a stable state when the voltage on the node B reaches the supply voltage of the circuit and the whole current Io circulates in the switch SW 2 . 
   A second embodiment of the selector switch is depicted in  FIG. 5 . A cascode stage M 0  generates the current Io to be steered as a function of a single-ended input signal VIN. The operational amplifier OA includes the MOSFETs M 5  and M 6 , the switches are the MOSFETs M 1  and M 2  and the auxiliary line DUMMY LOAD is realized with a diode-connected MOSFET M 3  coupled between the output node B of the selector switch and the power supply line VDD. 
   When the signal VCTRL is high (e.g. equal to the supply voltage), the whole current Io flows through the switch M 1 . The signal applied to the buffer M 5  is low because of the gate-source voltage of the active load M 3 . The switch M 2  is open (non-conducting) and its gate voltage V gM2  is approximately:
 
 V   gM2   =Vdd−V   gsM3   −V   gsM5  
 
with Vdd being the supply voltage of the switch, V gsM3  and V gsM5  the gate-source voltages of the MOSFETs M 3  and M 5 .
 
   The voltage V gsM5  will be close to the threshold voltage of the MOSFET M 5 . When the control signal VCTRL decreases, the gain of the positive feedback loop increases and, when the signal VCTRL becomes closer than the voltage V gM2 , the loop gain becomes larger than 1. In this situation, the selector switch evolves rapidly to a stable state in which the switch M 2  is on and the whole current Io flows through the load LOAD. 
   As a matter of fact, as soon as the control signal VCTRL drops below the threshold of the MOSFET M 1 , the transistor M 1  turns off and the transistor M 5  turns on, thus also the switch M 2  is turned on. Optionally, as shown, the auxiliary line DUMMY LOAD may be implemented with an active load including a diode-connected MOSFET M 3  coupled between the second output terminal of the switch and the supply line. 
   An even simpler embodiment is shown in  FIG. 6 . This architecture may be derived from that of  FIG. 4  by using an operational amplifier OA, the output of which tracks the input voltages on its input terminals. 
   By carrying out an analysis of the small-signal equivalent circuit of the circuit of  FIG. 5 , the gains Av ON  and Av OFF  for small signals of the switch are calculated respectively when the current Io flows through the load LOAD and when the current flows in the auxiliary line, that is through the active load M 3 . 
   Being gm the transconductance, Cgs the intrinsic gate-source capacitance and ω T     —     M3 , the angular transition frequency of the MOSFET M 3 , the following equations hold: 
   
     
       
         
           
             
               
                 
                   Av 
                   ON 
                 
                 = 
                 
                   
                     gm 
                     
                       M 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       0 
                     
                   
                   
                     gm 
                     LOAD 
                   
                 
               
             
             
               
                 ( 
                 1 
                 ) 
               
             
           
           
             
               
                 
                   Av 
                   OFF 
                 
                 = 
                 
                   
                     
                       Av 
                       ON 
                     
                     · 
                     
                        
                       
                         
                           jω 
                           · 
                           
                             Cgs 
                             
                               M 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               5 
                             
                           
                         
                         
                           
                             gm 
                             
                               M 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               3 
                             
                           
                           + 
                           
                             jω 
                             · 
                             
                               Cgs 
                               
                                 M 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 5 
                               
                             
                           
                         
                       
                        
                     
                   
                   ≅ 
                   
                     
                       Av 
                       ON 
                     
                     · 
                     
                       
                         ω 
                         · 
                         
                           Cgs 
                           
                             M 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             5 
                           
                         
                       
                       
                         gm 
                         
                           M 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           3 
                         
                       
                     
                   
                   ≤ 
                   
                     
                       Av 
                       ON 
                     
                     · 
                     
                       ω 
                       
                         ω 
                         T_M3 
                       
                     
                   
                 
               
             
             
               
                 ( 
                 2 
                 ) 
               
             
           
         
       
     
   
   Equation (2) has been calculated supposing that the gate-source capacitance of the MOSFET M 6  be negligible, and the MOSFET M 5  has a channel length equal to that of the switch M 2  and channel width smaller than 1/10 of the channel width of M 2 . The maximum gain Av OFF  (the case of worse isolation, that allows simplifying equation 2) has been determined by supposing that the load has a high impedance. 
   Supposing that
 
Cgs M5 &lt;&lt;CgS M3   (3)
 
the ratio between the two gains Av ON  and Av OFF  defines the isolation of the switch, given by
 
   
     
       
         
           
             
               
                 
                   
                     Av 
                     ON 
                   
                   
                     Av 
                     OFF 
                   
                 
                 ≥ 
                 
                   
                     ω 
                     T_M3 
                   
                   ω 
                 
               
             
             
               
                 ( 
                 4 
                 ) 
               
             
           
         
       
     
   
   Equations similar to the above may be obtained also for the switch of  FIG. 6 , by simply substituting the transconductances gm of the MOSFET M 3  and of the load LOAD with the inverse of the resistances R LOAD  and R DUMMY . 
   The values of the thresholds beyond which the control signal VCTRL switches M 1  and M 2  may be calculated by equating to 1 the open loop gains of the loop that generates the positive feedback (M 1 , M 3 , M 5  and M 2 ) as disclosed in P. R. Gray and R. G. Meyer, Analysis and Design of Integrated Circuits, 2nd ed. New York: Wiley 1984. 
   The results of the simulations of the functioning of the selector switch of  FIG. 6  are shown in  FIGS. 7 and 8 , by supposing that the switches M 1  and M 2  are realized in a 90 nm CMOS technology with an aspect ratio of 50 μm/0.09 μm, with a transition frequency of about 90 GHz, a gain Av ON  of 0 dB and isolation of about 30 dB at a working frequency of about 8 GHz. 
     FIG. 7  shows that the voltage VOUT on the load LOAD describes a hysteresis loop as a function of the signal VCTRL, while  FIG. 8  shows that the selector switch of this invention of  FIG. 6  responds to a step variation of the signal VCTRL in times of the order of a tenth of picoseconds. 
   Two identical selector switches may be used for realizing a device for switching a differential input signal VIN+, VIN− on a load LOAD shown in  FIG. 9  and a mixer that generates a differential output signal by frequency modulating and amplifying a differential input signal RF+, RF− shown in  FIG. 10 . 
   The functioning of these two devices is not described in detail because it would be readily appreciated by those skilled in the art in view of what has been stated referring to the selector switches of  FIGS. 5 and 6 . 
   Though embodiments in MOS technology have been described, embodiments in bipolar technology may be immediately obtained by substituting the MOSFETs in  FIGS. 5 ,  6 ,  9  and  10  with BJTs. Similarly, loads on the auxiliary path may be diode-connected transistors and/or impedances.