Abstract:
The present invention relates to a method of manufacturing a cloverleaf microgyroscope containing an integrated post comprising: attaching a post wafer to a resonator wafer, forming a bottom post from the post wafer being attached to the resonator wafer, attaching the resonator wafer to a base wafer, wherein the bottom post fits into a post hole in the base wafer, forming a top post from the resonator wafer, wherein the bottom and top post are formed symmetrically around the same axis, and attaching a cap wafer on top of the base wafer. The present invention relates further to a gyroscope containing an integrated post with on or off-chip electronics.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention refers to a cloverleaf microgyroscop and a method of manufacturing a cloverleaf microgyroscop that contains a single crystal silicon cloverleaf-shaped resonator and integrated post attached to the leaves. 
   2. Description of Related Art 
   U.S. Pat. No. 5,894,090 to Tang et al., which is incorporated herein as reference, discloses a micromachined symmetric leaf structure having a plurality of symmetrically disposed leaves about a defined center. At least one micromachined spring symmetrically is disposed with respect to the symmetric leaf structure and supporting the symmetrical leaf structure, a rim/base structure to which the spring is coupled. The rim/base structure includes a plurality of sensing and drive electrodes and a circuit electrically coupled to the electrodes included within the rim/base structure. The circuit provides drive signals to the drive electrodes to oscillate the symmetric leaf structure and to receive a sensing signal from the sensing electrodes to detect response of the oscillating symmetric leaf structure to physical phenomena exterior to the micromachined resonator. The micromachined resonator has a manually inserted post. It shows a lack of a silicon based vacuum encapsulation. A low yield is obtained during the separation. The manufacturing of the resonator involves high fabrication costs. It shows large vibration sensitivity and no clear path to electronic integration. 
   The known manufacture processes make it very difficult to manufacture a micro gyroscope. The central post is inserted by hand, the device has to be vacuum packaged in a custom package and there is no ability to integrate control electronics with the silicon structure. 
   What is needed is a cloverleaf microgyroscope and a process for manufacturing a cloverleaf microgyroscope with an integrated central post and electronics with the resonator and vacuum package at wafer-level with a single crystal silicon construction. 
   BRIEF SUMMARY OF THE INVENTION 
   This invention addresses the above needs. 
   One aspect of the present invention is a method of manufacturing a cloverleaf microgyroscope containing an integrated post comprising:
         a) attaching a post wafer to a resonator wafer,   b) forming a bottom post from the post wafer being attached to the resonator wafer,   c) attaching the resonator wafer to a base wafer, wherein the bottom post fits into a post hole in the base wafer,   d) forming a top post from the resonator wafer, wherein the bottom and top post are formed symmetrically around the same axis, and   e) attaching a cap wafer on top of the base wafer.       

   Another aspect of the present invention is a cloverleaf microgyroscope with off-chip electronics manufactured by this method. 
   In one embodiment, the construction of a microgyroscope has a single crystal silicon cloverleaf-shaped resonator and integrated post attached to the leaves. The microgyroscope device array is fabricated by bonding two separate substrates together using a gold/gold thermo compression technique; one contains the cloverleaf resonator structures fabricated from SOI and bulk silicon substrates, and the other contains the support pillars and electrode metal. A fourth wafer containing an array of etched cavities and openings which allow the bonding of electrical wires from metal pads to off-chip circuitry is solder-bonded to the device wafer in a vacuum, thus hermetically sealing each individual microgyroscope. 
   Another aspect of the present invention is a method of manufacturing a cloverleaf microgyroscope containing an integrated post comprising:
         a) attaching a post wafer to a resonator wafer,   b) forming a bottom post from the post wafer being attached to the resonator wafer,   c) application specific integrated circuits (ASIC) electronics on a base wafer   d) attaching the resonator wafer to the base wafer, wherein the bottom post fits into a post hole in the base wafer,   e) forming a top post from the resonator wafer, wherein the bottom and top post are formed symmetrically around the same axis,   f) and attaching a cap wafer on top of the base wafer.       

   Another aspect of the present invention is a cloverleaf microgyroscope with on-chip electronics manufactured by this method. 
   In another embodiment, the construction of a microgyroscope with on-chip electronics has a single crystal silicon cloverleaf-shaped resonator and integrated post attached to leaves. The microgyroscope with on-chip electronics device array is fabricated by bonding two separate substrates together using a gold/gold thermo compression technique; one includes the cloverleaf resonator structures fabricated from SOI and bulk silicon substrates. 
   In another embodiment, the present invention relates to a fabrication method that incorporates an integrated post, which eliminates a manual post insertion process. In addition, a wafer-scale packaging can be used to facilitate die separation and to enhance the quality factor of the mechanical resonator. The method of the present invention increases the yield and decreases the manufacturing costs of the cloverleaf gyroscope. The on-chip integration according to an aspect of the present invention of the control electronics with the gyroscope will further decrease the cost and size of the device. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     These and other features, aspects and advantages of the present invention will become better understood with reference to the following description, appended claims, and accompanying drawings where 
     Cloverleaf Microgyroscope 
       FIG. 1   a  is a top plan view of the preferred starting material of a resonator SOI wafer A and  FIG. 1   b  is a cross-sectional view through wafer A of  FIG. 1   a  at line  1   b — 1   b  of the resonator SOI wafer A; 
       FIG. 2   a  is a top plan view of the preferred starting material of a resonator SOI wafer A and  FIG. 2   b  is a cross-sectional view through wafer A of  FIG. 2   a  at line  2   b — 2   b  of the resonator SOI wafer A; 
       FIG. 3   a  is a top plan view of the preferred starting material of a resonator SOI wafer B and  FIG. 3   b  is a cross-sectional view through wafer B of  FIG. 3   a  at line  3   b — 3   b  of the bottom-portion wafer B; 
       FIG. 4   a  is a cross-sectional view at line  3   b — 3   b  of the bond wafer B; 
       FIG. 4   b  is a cross-sectional view at line  2   b — 2   b  of bonded to wafer A; 
       FIG. 5   a  is a top plan view of the resonator SOI wafer A and a bottom post B′ and  FIG. 5   b  is a cross-sectional view through wafer A and bottom post B′ of  FIG. 5   a  at line  5   b — 5   b  of the resonator SOI wafer A and bottom post B′; 
       FIG. 6   a  is a top plan view of the resonator SOI wafer A and a bottom post B′ and  FIG. 6   b  is a cross-sectional view through wafer A and bottom post B′ of  FIG. 6   a  at line  6   b — 6   b  of the resonator SOI wafer A and bottom post B′ after several contacts are attached to it; 
       FIG. 7   a  is a top plan view of the preferred starting material of a base wafer C and  FIG. 7   b  is a cross-sectional view through wafer C of  FIG. 7   a  at line  7   b — 7   b of the base wafer C;    
       FIG. 8   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 8   b  is a cross-sectional view through wafer C  FIG. 8   a  at line  8   b — 8   b  of the base wafer C, after on both surfaces of base wafer C an silicon dioxide layer is grown; 
       FIG. 9   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 9   b  is a cross-sectional view through wafer C of  FIG. 9   a  at line  9   b — 9   b  of the base wafer C, after pillar fabrication; 
       FIG. 10   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 10   b  is a cross-sectional view through wafer C of  FIG. 10   a  at line  10   b — 10   b  of the base wafer C, after on both surfaces of base wafer C an silicon dioxide layer is grown; 
       FIG. 11   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 11   b  is a cross-sectional view through wafer C of  FIG. 11   a  at line  11   b — 11   b  of the base wafer C after an ohmic contact and interconnect metal patterning; 
       FIG. 12   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 12   b  is a cross-sectional view through wafer C of  FIG. 12   a  at line  12   b — 12   b  of the base wafer C after electrode, bond pad, and wire bond metal were provided on the base wafer C; 
       FIG. 13   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 13   b  is a cross-sectional view through wafer C of  FIG. 13   a  at line  13   b — 13   b  of the base wafer C after silicon nitride is provided on the base wafer C; 
       FIG. 14   a  is a top plan view of the preferred starting material of the base wafer C and  FIG. 14   b  is a cross-sectional view of through wafer C of  FIG. 14   a  at line  14   b — 14   b  of the base wafer C after a seal ring deposition; 
       FIG. 15   a  is a top plan view of the preferred starting material of the base  15   b — 15   b  of the base wafer C after a post hole etch is carried out in the base wafer C; 
       FIG. 16   a  is a top plan view of the preferred starting material of the bottom surface of wafer A and  FIG. 16   b  is a cross-sectional view through the base wafer A, post B′, and base wafer C of  FIG. 16   a  at line  16   b — 16   b  of the base wafer A, post B′, and base wafer C; 
       FIG. 17   a  is a top plan view depicting post A′ and base wafer C and  FIG. 17   b  is a cross-sectional view through the base wafer A, post B′, and base wafer C of  FIG. 17   a  at line  17   b - 17  depicting post A′, post B′, and base wafer C after post formation; 
       FIG. 18   a  is a top plan view of the preferred starting material of a cap wafer D and  FIG. 18   b  is a cross-sectional view through the cap wafer D of  FIG. 18   a  at line  18   b — 18   b  of the cap wafer D; 
       FIG. 19   a  is a top plan view of the preferred starting material of a cap wafer D and  FIG. 19   b  is a cross-sectional view through the cap wafer D of  FIG. 19   a  at line  19   b — 19   b  of the cap wafer D after preparing of holes in the top layer; 
       FIG. 20   a  is a bottom plan view of the preferred starting material of a cap wafer D and  FIG. 20   b  is a cross-sectional view through the cap wafer D of  FIG. 20   a  at line  20   b — 20   b  of the cap wafer D after backside metallization; 
       FIG. 21   a  is a bottom plan view of the preferred starting material of a cap wafer D and  FIG. 21   b  is a cross-sectional view through the cap wafer D of  FIG. 21   a  at line  21 — 21  of the cap wafer D after formation of backside cavities; 
       FIG. 22   a  is a top plan view of the preferred starting material of a cap wafer D and  FIG. 22   b  is a cross-sectional view through the cap wafer D and the base wafer C of  FIG. 22   a  at line  22   b — 22   b  of the cap wafer D bonded to the base wafer C; 
       FIG. 23   a  is a top plan view of the preferred starting material of a cap wafer D and  FIG. 23   b  is a cross-sectional view through the cap wafer D and the base wafer C of  FIG. 23   a  at line  23   b — 23   b  of the cap wafer D bonded to the base wafer C after etching remaining silicon in the cap wafer D, to produce a channel for a wire dicing; 
       FIG. 24   a  is a top plan view of the preferred starting material of a cap wafer D and  FIG. 24   b  is a cross-sectional view through the cap wafer D and the base wafer C of  FIG. 24   a  at line  24   b — 24   b  of the cap wafer D bonded to the base wafer C after dicing and ball-bonding of wires. 
     Cloverleaf Microgyroscope with On-Chip Electronics 
       FIG. 25   a  is a top plan view of the preferred starting material of a base wafer C and  FIG. 25   b  is a cross-sectional view through base wafer C of  FIG. 25   a  at line  25   b — 25   b  of the base wafer C after a cavity formation; 
       FIG. 26   a  is a top plan view of the preferred starting material of a base wafer C and  FIG. 26   b  is a cross-sectional view through base wafer C of  FIG. 26   a  at line  26   b — 26   b  of the base wafer C after ion implantation and thermal oxidation; 
       FIG. 27   a  is a top plan view of the preferred starting material of a base wafer C and  FIG. 27   b  is a cross-sectional view through base wafer C of  FIG. 27   a  at line  27   b — 27   b  of the base wafer C after a cavity planarization; 
       FIG. 28   a  is a top plan view of the preferred starting material of a base wafer C and  FIG. 28   b  is a cross-sectional view through base wafer C of  FIG. 28   a  at line  28   b — 28   b  of the base wafer C after ASIC electronic fabrication; 
       FIG. 29   a  is a top plan view of the preferred starting material of a base wafer C and  FIG. 29   b  is a cross-sectional view through base wafer C of  FIG. 29   a  at line  29   b — 29   b  of the base wafer C after the ohmic contact metal patterning and deposition; 
       FIG. 30   a  is a top plan view of the preferred starting material of a base wafer C and  FIG. 30   b  is a cross-sectional view through base wafer C of  FIG. 30   a  at line  30   b — 30   b  of the base wafer C after interconnect metal patterning and deposition; 
       FIG. 31   a  is a top plan view of the preferred starting material of a base wafer C and  FIG. 31   b  is a cross-sectional view through base wafer C of  FIG. 31   a  at line  31   b — 31   b  of the base wafer C after electrode metal deposition and patterning; 
       FIG. 32   a  is a top plan view of the preferred starting material of a base wafer C and  FIG. 32   b  is a cross-sectional view through base wafer C of  FIG. 32   a  at line  32   b — 32   b  of the base wafer C after a dielectric layer deposition and patterning; 
       FIG. 33   a  is a top plan view of the preferred starting material of a base wafer C and  FIG. 33   b  is a cross-sectional view through base wafer C of  FIG. 33   a  at line  33   b — 33   b  of the base wafer C after providing a seal ring metal; 
       FIG. 34   a  is a top plan view of the preferred starting material of a base wafer C and  FIG. 34   b  is a cross-sectional view through base wafer C of  FIG. 34   a  at line  34   b — 34   b  of the base wafer C after a post hole etch is carried out in the base wafer C; 
       FIG. 35   a  is a top plan view of the preferred starting material of the bottom surface of wafer A and  FIG. 35   b  is a cross-sectional view through the wafer A, post B′, and base wafer C of  FIG. 16   a  at line  16   b — 16   b  of the wafer A, post B′, and base wafer C; 
       FIG. 36   a  is a top plan view depicting post A′ and base wafer C and  FIG. 36   b  is a cross-sectional view through of post A′, post B′, and base wafer C  FIG. 36   a  at line  36   b — 36   b  depicting post A′, post B′, and base wafer C after post formation; 
       FIG. 37   a  is a top plan view of the preferred starting material of a cap wafer D and  FIG. 37   b  is a cross-sectional view through the cap wafer D bonded to the base wafer C of  FIG. 37   a  at line  37   b — 37   b  of the cap wafer D bonded to the base wafer C; 
       FIG. 38   a  is a top plan view of the preferred starting material of a cap wafer D and  FIG. 38   b  is a cross-sectional view through the cap wafer D bonded to the base wafer C of  FIG. 38   a  at line  38   b — 38   b  of the cap wafer D bonded to the base wafer C after etching remaining silicon in the cap wafer D; 
       FIG. 39   a  is a top plan view of the preferred starting material of a cap wafer D and  FIG. 39   b  is a cross-sectional view through the cap wafer D bonded to the base wafer C of  FIG. 39   a  at line  39   b — 39   b  of the cap wafer D bonded to the base wafer C after dicing and ball-bonding of wires. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Cloverleaf Microgyroscope 
   The resonator wafer A, preferably a silicon-on-insulator (SOI) wafer, is preferably prepared first. On a bulk silicon base  1  having a preferable thickness of ≦500 μm, which is optionally lightly-doped bulk silicon about 1e15 cm −3 , a silicon dioxide layer  2  having a preferable thickness of ≦2 μm is formed preferably by thermal oxidation at a temperature between 800° C. and 1000° C. On top of the silicon dioxide layer  2  a heavily doped silicon epi-layer, p-type, 1e19-1e20 cm −3    3  is provided having a preferable thickness of 10 μm to 20 μm, as shown in  FIGS. 1   a  and  1   b.    
   Then the cloverleaf petal and spring of the resonator wafer A is prepared. Parts of the heavily-doped silicon epi-layer  3  are removed by photo resist lithography, deep reactive ion etching (DRIE) and photo resist removal, as shown in  FIG. 2   a . Photo resist lithography and DRIE are described in inter alia Veljko Milanovic et al. “Deep Reactive Ion Etching for Lateral Field Emission Devices”, IEEE Electron Device Letters, Vol. 21, No. 6, June, which is incorporated herein as reference. 
   The process preferably comprises:
         1. The top silicon layer of the wafer is coated with a layer of photoresist.   2. Light from an illuminator is projected through a mask that contains the pattern to be created on the wafer. That light patterns that pass through the mask are projected onto the photoresist-coated layer.   3. The photoresist that is exposed to the light becomes soluble and is rinsed away, leaving miniature images of the mask pattern. It remains an etch mask on the silicon surface of the wafer.   4. Regions unprotected by photoresist are etched by gases utilizing Deep Reactive Ion Etching (DRIE). DRIE involves repeated exposure of a photoresist-masked silicon wafer to an etchant (usually SF 6 ) plasma in alternation with a passivant (usually C 4 F 8 ) plasma. So the etching process preferably cycles between etching and deposition steps several times to achieve a deep etching with a quite vertical profile. The etch rate, profile and selectivity to the mask are controlled by adjusting etch and passivation steps efficiency or the time ratio of the two steps. Average etch rate is around 2.7 μm/min, and etching is terminated when the SiO 2  layer  2  is reached. The SiO 2  layer  2  serves as a stop layer.   5. After the DRIE process the photoresist is removed. Photoresist removal with solvents is a preferred process in the semiconductor manufacturing and is used extensively after any metal processing. Organic strippers may have any number of different components such as NMP, glycol ether, amine, and DMSO.       

   The process parameters for the photoresist lithography are preferably as follows:
         a) Resist Application.
           2.07 μm   AZI 1350J, 3500 RPM   100° C. Hotplate bake for 45 sec.   
           b) Resist Exposure
           Photomask # C 1     Time=7 sec.   Mask Offset=0.2 μm   
           c) Develop &amp; Bake:
           MF351:H 2 O, 1:5 for 60 sec   100C Hotplate Bake for 45 sec.   
               

   The bottom post wafer B is prepared next. On a bulk silicon base  1  having a preferable thickness a of ≦500 μm, which is optionally lightly-doped bulk silicon layer (about 1e15 cm −3 )  2  a silicon dioxide layer, having a preferable thickness of ≦2 μm, is formed preferably by thermal oxidation between 800° C. and 1000° C. as shown in  FIGS. 3   a  and  3   b.    
   Wafer B is bonded to resonator wafer A. The bondage between heavily-doped silicon epi-layer  3  of the bottom portion of wafer A and the silicon dioxide layer  2  of the wafer B is achieved by heating at a temperature from 800° C. to 1000° C., as shown in  FIGS. 4   a  and  4   b . In this process the SiO 2  layer  2  of wafer B is preferably bonded to the heavily doped silicon epi-layer,  3  of the SOI wafer A. The epi-layer  3  is preferably p-type, 1e19-1e20 −3 . 
   Then the bottom post B′ and rib pattern are prepared. The bulk silicon layer  1  and silicon dioxide  2  of the wafer B have been partially removed to yield a post B′ as shown in  FIGS. 5   a  and  5   b.    
   The process preferably comprises:
         1. Coating the top silicon layer  1  of the wafer B with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern to be created on the wafer B,   3. Washing of the exposed regions of the photoresist layer and leaving an etch mask on the silicon surface of the wafer B.   4. Etching silicon layer  1  unprotected by photoresist by gases utilizing the deep reactive ion etch (DRIE).   5. Removing SiO 2  layer  2  of wafer B by CF 4 /O 2  plasma etch, and   6. Removing of photoresist on the surface of the post B′.       

   Then ohmic contacts are formed. On the heavily doped silicon epi-layer  3  several contacts  4 , are preferably formed by sputtering metal. The contacts  4  are placed symmetrically around the post B′. The contacts  4  contain preferably Ti/Pd/Au, Ti/Pt/Au or mixtures thereof. The contacts  4  are prepared by photo resist lithography, wet etching the metal and removing the photo resist (photoresist spray lithography, metallization Ti/Pt/Au and metal lift-off), as shown in  FIGS. 6   a  and  6   b . Metal liftoff is a common means of creating narrow metal lines for metals. The metal liftoff process is preferably done in a spray system. The process of resist photoresist, spray lithography, metallization and metal lift-off is described for example, in inter alia, in Andrea Via et al. “Metal Lift-off on InP HBTs Using Carbon Dioxide Snow Spray” (see: www1.boc.com/eco-snow/pdf/CS-MAX %202002.pdf.) 
   The process preferably comprises:
         1. Coating the heavily doped silicon epi-layer, p-type, 1e19-1e20 cm −3    3  of the wafer A by metallization with sputter metal (Ti/Pd/Au).   2. Coating metal (Ti/Pd/Au) on the layer  3  with a layer of photoresist,   3. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the ohmic contacts  4  to be created, on the layer  3  of wafer A,   4. Washing of the exposed regions of the photoresist layer and leaving an etch mask on the silicon surface of the wafer A, Removing the metal which is not covered by photoresist by wet etch,   5. Removing of photoresist on the surface of the ohmic contacts  4 .       

   The process for photoresist spray lithography, metallization Ti/Pt/Au and metal lift-off preferably comprises:
         1. Coating layer  3  with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the ohmic contacts Ti/Pt/Au  4  to be created, on the layer on the layer  3  of wafer A,   3. Washing of the exposed regions of the photoresist layer and leaving an etch mask on the silicon surface of the wafer A, Removing the metal which is not covered by photoresist by wet etch,   4. Depositing Ti/Pt/Au  4  by spray lithography,   5. Removing of Ti/Pt/Au  4  covering the photoresist by a metal lift-off process,   6. Stripping of the remaining photoresist yielding an Ti/Pt/Au  4  pattern on the to surface of wafer C.       

   Then a base wafer C is prepared. The preferred starting material  5  of the base wafer C has a preferable thickness of about ≦800 μm and contains moderately doped silicon substrate p-type, 1e19 cm −3 , as shown in  FIGS. 7   a  and  7   b.    
   On both surfaces of the preferred starting material  5  of the base wafer C a silicon dioxide layer  2  of ≦0.3 μm-thick is grown by thermal oxidation at a temperature preferably of about 950° C., as shown in  FIGS. 8   a  and  8   b.    
   Then a pillar fabrication is carried out. From the preferred starting material  5  a thickness of preferably about 5 μm to 8 μm is removed by photo resist lithography, wet etch SiO 2  and photo resist removal, wet KOH etch of silicon and SiO 2  removal in order to obtain pillars PI, as shown in  FIGS. 9   a  and  9   b.    
   The process preferably comprises:
         1. Coating the top and bottom SiO 2  layer  2  of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the pillars PI to be created, on the top layer  2  of wafer C,   3. Washing of the exposed regions of the photoresist layer and leaving an etch mask on the SiO 2  layer  2  of the wafer C,   4. Removing the SiO 2  layer  2 , which is not covered by photoresist, by CF 4 /O 2  plasma etch,   5. Removing 5–8 μm of moderate doped Si preferred starting material  5  by wet KOH etch to produce a cavity CA,   6. Removing of remaining photoresist, and   7. Removing SiO 2  layer  2  on the pillars and on the bottom layer by CF 4 /O 2  plasma etch.       

   On both surfaces of the preferred starting material  5  of the base wafer C an SiO 2  layer of ≦2 μm thick is grown by thermal oxidation at a preferable temperature of about 1050° C., as shown in  FIGS. 10   a  and  10   b.    
   An ohmic contact metal Al  6  and interconnect metal Ti/Al  7  were attached to the preferred starting material  5  of the base wafer C by photo resist spray lithography and metal deposition and liftoff, as shown in  FIGS. 11   a  and  11  b. 
   The process preferably comprises:
         1. Coating SiO 2  layer  2  with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern namely the places for the ohmic contact Al  6  to be created on the layer  2  of wafer C,   3. Washing of the exposed regions of the photoresist layer and leaving an etch mask on the SiO 2  layer  2  of the wafer C,   4. Removing the SiO 2  layer  2  by wet etch which is not covered by photoresist,   5. Depositing Al  6  by spray lithography,   6. Removing of Al  6  covering the photoresist by a metal lift-off process,   7. Stripping of the remaining photoresist yielding an Al  6  pattern on the to surface of wafer C,   8. Coating the top layer  2  of wafer C again with a layer of photoresist,   9. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the interconnect metal Ti/Al  7  to be created, on the SiO 2  layer  2  of wafer C,   10. Depositing Ti/Al  7  by spray lithography,   11. Removing of Ti/Al  7  covering the photoresist by a metal lift-off process,   12. Stripping of remaining photoresist and yielding a Ti/Al  7  pattern on the wafer C.       

   Electrode metal (drive/sense electrodes) Ti/Pt/Au  8   b , wire bond metal Ti/Pt/Au  8   c , and wafer bonding metal Ti/Pt/Au  8   d  were provided by photoresist lithography and metal deposition and liftoff, as shown in  FIGS. 12   a  and  12   b.    
   The process preferably comprises:
         1. Coating the top surface of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the wire bond metal Ti/Pt/Au  8  to be created, on the top surface of wafer C,   3. Washing of the exposed regions of the photoresist layer and leaving an mask on the top surface of the wafer C,   4. Depositing Ti/PT/Au  8  on the surface of wafer C spray lithography,   5. Removing of excess Ti/PT/Au  8  covering the photoresist by a metal lift-off process,   6. Stripping of remaining photoresist yielding a wire bond Ti/PT/Au  8 .       

   Silicon nitride  9  layer is provided on the top of base wafer C by the dielectric layer deposition and patterning. A Si 3 N 4  film ≦0.5 μm thick is provided by deposition and photo resist lithography and removed by CF 4 /O 2  plasma etch of Si 3 N 4  in device and wire bond regions and by photo resist removal, as shown in  FIGS. 13   a  and  13   b.    
   The process preferably comprises:
         1. Coating the surface of wafer C with Si 3 N 4    9 , with a thickness of about 0.5 μm,   2. Coating Si 3 N 4    9  with a layer of photoresist,   3. Projecting light from an illuminator through a mask that contains the pattern, namely covering the places for the interconnect metal dielectric layer Si 3 N 4    9  to be created, on the surface of wafer C,   4. Washing of the exposed regions of the photoresist layer and leaving an mask on Si 3 N 4    9 ,   5. Removing the Si 3 N 4    9  which is not covered by CF 4 /O 2  plasma etch, and   6. Stripping of remaining photoresist.       

   A seal ring  8   a  containing Ti/Pt/Au is provided on the silicon nitride  9  by metal patterning and deposition, particularly by photo resist lithography spray on thick resist and metal deposition and liftoff, as shown in  FIGS. 14   a  and  14   b.    
   The process preferably comprises:
         1. Coating the top surface of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for seal ring metal  8   a  containing Ti/Pt/Au provided on the silicon nitride  9  to be created, on the top surface of wafer C,   3. Washing of the exposed regions of the photoresist layer and leaving an mask on the top surface of the wafer C,   4. Depositing Ti/PT/Au on the surface of wafer C,   5. Removing of excess Ti/PT/Au  8   a  covering the photoresist by a metal lift-off process,   6. Stripping of remaining photoresist yielding removing of excess Ti/PT/Au  8   a  covering the photoresist by a metal lift-off process,   7. Stripping of remaining photoresist yielding a seal ring  8   a  containing Ti/Pt/Au on the silicon nitride  9 .       

   As a next step a post hole etch  5 ′ is carried out by photo resist lithography (spray on thick resist), CF 4 /O 2  plasma etch of silicon dioxide in hole region, DRIE of silicon hole and photo resist removal as shown in  FIGS. 15   a  and  15   b.    
   The process preferably comprises:
         1. Coating the top surface of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern namely the place for the hole region on the top surface of wafer C,   3. Washing of the exposed regions of the photoresist layer and leaving an mask on the top surface of the wafer C,   4. CF 4 /O 2  plasma etch of silicon dioxide in hole region,   5. DRIE remove to create a silicon hole, and   6. Stripping of the remaining photo resist layer.       

   As a next step a bonding of resonator wafer A according to  FIG. 6   b  and to base wafer C according to  FIG. 15   b  is carried out preferably by a Au to Au thermo compression bonding at temperature of 300° C. to 400° C., as shown in  FIGS. 16   a  and  16   b . The bonding is carried between the contacts  4  of resonator wafer A–B and the seal ring metal  8   a  of the base wafer C. Post B′ of resonator wafer A–B fits into the post hole  5 ′ of base wafer C. 
   The post fabrication on wafer A is carried out by photo resist lithography (spray on thick resist), CF 4 /O 2  plasma etching of silicon dioxide, photo resist removal by dry etch. Thereby a post A′ and optional frame formation in the top layer A″ is obtained, as shown in  FIGS. 17   a  and  17   b.    
   The process preferably comprises:
         1. Coating the top surface of wafer A with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the place for the hole region on the top surface of wafer A,   3. Washing of the exposed regions of the photoresist layer and leaving an mask on the top surface of the wafer A,   4. DRIE remove of silicon from wafer A,   5. CF 4 /O 2  plasma etch of silicon dioxide from wafer A, whereby a post A′ and optional frame formation in the top layer A″ is obtained, and   6. Stripping of the remaining photo resist layer.       

   A cap wafer D is prepared with a preferred starting material of lightly doped bulk silicon  1  having a thickness of ≦800 μm and having on top and bottom a thin silicon dioxide layer  2 , as shown in  FIGS. 18   a  and  18   b.    
   An opening  1   b  into the top silicon dioxide layer  2  to form silicon dioxide holes for front side silicon etching of wire bonding pad  8   c  is carried out by photo resist lithography, dry etch of silicon dioxide and photo resist removal, as shown in  FIGS. 19   a  and  19   b.    
   The process preferably comprises:
         1. Coating the top surface SiO 2  of the cap wafer D with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the place for the hole region on the top surface of cap wafer E,   3. Washing of the exposed regions of the photoresist layer and leaving an mask on the top surface of the wafer E,   4. CF 4 /O 2  plasma etch of silicon dioxide until the Silicon starts yielding a hole  1   b  into the top silicon dioxide layer  2 ,   5. Stripping of the remaining photo resist layer.       

   Then a backside metallization is carried out by photo resist lithography and metal deposition and liftoff. Thereby Ti/Pt/Au  8  and solder metal  12  are attached, as shown in  FIGS. 20   a  and  20   b.    
   The process preferably comprises:
         1. Coating the bottom surface of cap wafer D with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for seal ring Ti/Pt/Au  8  and solder metal  12  to be attached, on the bottom surface of wafer cap wafer E,   3. Washing of the exposed regions of the photoresist layer and leaving an mask on the top surface of the wafer E,   4. Depositing Ti/PT/Au on the bottom surface of cap wafer E,   5. Depositing solder metal  12  on the bottom surface of cap wafer E,   6. Removing of excess Ti/PT/Au  8  and solder metal  12  covering the photoresist by a metal lift-off process,   7. Stripping of remaining photoresist yielding a seal ring Ti/Pt/Au  8  and solder metal  12 .       

   Then backside cavities  13   a  and  13   b  are formed on the cap wafer D by spray thick photo resist on the backside, DRIE etch SiO 2 , DRIE cavities and remove photo resist, as shown in  FIGS. 21   a  and  21   b.    
   The process preferably comprises:
         1. Coating the bottom silicon dioxide layer  2  of the cap wafer D with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern to be created on bottom layer  2  of the cap wafer D,   3. Washing of the exposed regions of the photoresist layer and leaving an etch mask on the bottom silicon dioxide layer  2  of the cap wafer E,   4. Removing SiO 2  layer  2  of wafer B by CF 4 /O 2  plasma etch,   5. Etching silicon layer  1  unprotected by photoresist by gases utilizing the deep reactive ion etch (DRIE) on the bottom of the cap wafer D, and   6. Removing of photoresist from the bottom silicon dioxide layer  2  of the cap wafer D yielding two cavities  13 .       

   The cap wafer D is bonded to the base wafer C. The cap wafer D is positioned on top of base wafer C. A solder bond is carried out at low temperature at about 200° C. between the solder metal  12  of the cap wafer D and the seal ring metal  8   a  of the base wafer C, as shown in  FIGS. 22   a  and  22   b.    
   A channel  14  is formed by wet etch (KOH) of silicon from the top of cap wafer D. The channel  14  combines with the cavity  13   b  to form a channel for wire bonding as shown in  FIGS. 23   a  and  23   b.    
   The process preferably comprises: 
   Wet etching (KOH) of silicon from the top of the cap wafer D in the position of the hole  1   b  and generating a hole. The hole from the top of the cap wafer D forms with the cavity  13   b  from the bottom of the cap wafer D a channel  14 . 
   A ball bonding of wires  15  by vacuum oven bake is carried out as shown in  FIGS. 23   a  and  23   b . The process preferably comprises leading a wire  15  from the top of the cap wafer D through channel  14  and attaching the wire to the wire bonding pad Ti/Pt/Au  8   c  on the bottom wafer C. 
   Cloverleaf Microgyroscope with On-Chip Electronics 
   The bonded resonator wafer containing wafer resonator A and bottom post B′ is prepared according to the same process as described above in regard to  FIGS. 1–6 . Therefore the same resonator wafer according to  FIG. 6  is used to produce the cloverleaf microgyroscope with on-chip electronics. 
   Then a base wafer C is prepared. The preferred starting material  5  of the base wafer C has a thickness about ≦800 μm and includes moderately doped silicon substrate p-type, 1e19 cm −3 , as shown in  FIGS. 7   a  and  7   b.    
   On both surfaces of the preferred starting material  5  of the base wafer C a silicon dioxide layer of ≦0.3 μm-thick is grown by thermal oxidation at a temperature of about 950° C., as shown in  FIGS. 8   a  and  8   b.    
   Then a cavity CA formation is carried out. From the preferred starting material  5  a thickness of 5 μm to 8 μm is removed by photo resist lithography, co-pattern cavities, dry etch SiO 2  on front side and photo resist removal, wet KOH etch of Silicon and SiO 2  removal in order to obtain cavities, as shown in  FIGS. 25   a  and  25   b.    
   The process preferably comprises:
         1. Coating the top and bottom SiO 2  layer  2  of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the cavities CA to be created, on the top layer  2  of wafer C,   3. Washing of the exposed regions of the photoresist layer and leaving an etch mask on the SiO 2  layer  2  of the wafer C patterning the cavities CA,   4. Removing the SiO 2  layer  2  by dry etch which is not covered by photoresist,   5. Removing 5–8 μm of moderate doped Si preferred starting material  5  by wet KOH etch to yield the cavities CA,   6. Removing of remaining photoresist, and   7. Removing SiO 2  layer  2  on the top and bottom layer by dry etch.       

   Then an ion implantation II and thermal oxidation is carried out by a 300 keV boron ion implantation (10 19  cm −3 ) on the top surface of the preferred starting material silicon  5  of the base wafer C. After a photoresist removal a SiO 2  layer  2  of ≦0.2 μm thick is grown by thermal oxidation at a temperature of about 950° C., on the top surface of material silicon  5  of the base wafer C as shown in  FIGS. 26   a  and  26   b.    
   The process preferably comprises:
         1. Coating the top surface of silicon  5  of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the cavity ion implantation II shall be carried out, on the top surface  5  of wafer C,   3. Washing of the exposed regions of the photoresist layer and leaving an etch mask on the silicon surface  5  of the wafer C showing the location of the cavity ion implantation II,   4. 300 keV boron ion implantation (10 19  cm 3 ) is formed preferably to yield ion implantation II,   5. Removing of remaining photoresist.       

   Then a cavity planarization is carried out. The cavity planarization is preferably done by chemo mechanical polishing and applying a spin on dielectric DE on the cavity CA in the preferred starting material  5  of the base wafer as shown in  FIGS. 27   a  and  27   b.    
   Then an application specific integrated circuits (ASIC) electronic AS fabrication is carried out. A thermal oxidation of the surface of silicon  5  was carried out and a SiO 2  layer around the dielectric DE was developed. After that the dielectric DE was removed from preferred starting material  5  of the base wafer C as shown in  FIGS. 28   a  and  28   b.    
   Then an ohmic contact Al  6  was attached to the preferred starting material  5  of the base wafer C by photo resist spray lithography and metal deposition and liftoff, as shown in  FIGS. 29   a  and  29   b.    
   The process preferably comprises:
         1. Coating SiO 2  layer  2  with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the ohmic contact Al  6  to be created, on the layer  2  of wafer C,   3. Washing of the exposed regions of the photoresist layer and leaving an etch mask on the SiO 2  layer  2  of the wafer C,   4. Removing the SiO 2  layer  2  by wet etch which is not covered by photoresist,   5. Depositing Al  6  by spray lithography,   6. Removing of Al  6  covering the photoresist by a metal lift-off process,   7. Stripping of the remaining photoresist yielding an Al  6  pattern on the surface of wafer C.
 
Then an ohmic contact and interconnect metals Ti/Al  7  were attached to the preferred starting material  5  of the base wafer C by photo resist spray lithography and metal deposition and liftoff, as shown in  FIGS. 30   a  and  30   b.  
       

   The process preferably comprises:
         1. Coating the top layer  2  of wafer C again with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the interconnect metal Ti/Al  7  to be created, on the SiO 2  layer  2  of wafer C,   3. Depositing Ti/Al  7  by spray lithography,   4. Removing of Ti/Al  7  covering the photoresist by a metal lift-off process,   5. Stripping of remaining photoresist and yielding a Ti/Al  7  pattern on the wafer C.       

   Then electrode metal (drive/sense electrodes) Ti/Pt/Au  8   b , wire bond metal Ti/Pt/Au  8   c , and wafer bonding metal Ti/Pt/Au  8   d  were provided by photoresist lithography and metal deposition and liftoff, as shown in  FIGS. 31   a  and  31   b.    
   The process preferably comprises:
         1. Coating the top surface of wafer C with a layer of photoresist   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for the wire bond metal Ti/Pt/Au  8  to be created, on the top surface of wafer C,   3. Washing of the exposed regions of the photoresist layer and leaving an mask on the top surface of the wafer C,   4. Depositing Ti/PT/Au  8  on the surface of wafer C by spray lithography,   5. Removing of excess Ti/PT/Au  8  covering the photoresist by a metal lift-off process,   6. Stripping of remaining photoresist yielding a wire bond Ti/PT/Au  8 .       

   Silicon nitride  9  layer is provided on the top of base wafer C by the dielectric layer deposition and patterning. A Si 3 N 4  film ≦0.5 μm thick is provided by deposition and photo resist lithography and removed by CF 4 /O 2  plasma etch of Si 3 N 4  in device and wire bond regions and by photo resist removal, as shown in  FIGS. 32   a  and  32   b.    
   The process preferably comprises: 
   1. Coating the surface of wafer C with Si 3 N 4    9 , with a thickness of about 0.5 μm,
         2. Coating Si 3 N 4    9  with a layer of photoresist,   3. Projecting light from an illuminator through a mask that contains the pattern, namely covering the places for the interconnect metal dielectric layer Si 3 N 4    9  to be created, on the surface of wafer C,   4. Washing of the exposed regions of the photoresist layer and leaving an mask on Si 3 N 4    9 ,   5. Removing the Si 3 N 4    9  which is not covered by CF 4 /O 2  plasma etch, and   6. Stripping of remaining photoresist.       

   A seal ring metal  8   a  containing Ti/Pt/Au is provided on the silicon nitride  9  by metal patterning and deposition, particularly by photo resist lithography spray on thick resist and metal deposition and liftoff, as shown in  FIGS. 33   a  and  33   b.    
   The process preferably comprises:
         1. Coating the top surface of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the places for seal ring metal  8   a  containing Ti/Pt/Au provided on the silicon nitride  9  to be created, on the top surface of wafer C,   3. Washing of the exposed regions of the photoresist layer and leaving an mask on the top surface of the wafer C,   4. Depositing Ti/PT/Au on the surface of wafer C,   5. Removing of excess Ti/PT/Au  8   a  covering the photoresist by a metal lift-off process,   6. Stripping of remaining photoresist yielding removing of excess Ti/PT/Au  8   a  covering the photoresist by a metal lift-off process,   7. Stripping of remaining photoresist yielding a seal ring  8   a  containing Ti/Pt/Au on the silicon nitride  9 .       

   As a next step a post hole etch  5 ′ is carried out by photo resist lithography (spray on thick resist), CF 4 /O 2  plasma etch of silicon dioxide in hole region, DRIE of silicon hole and photo resist removal as shown in  FIGS. 34   a  and  34   b.    
   The process comprises:
         1. Coating the top surface of wafer C with a layer of photoresist,   2. Projecting light from an illuminator through a mask that contains the pattern, namely the place for the hole region on the top surface of wafer C,   3. Washing of the exposed regions of the photoresist layer and leaving an mask on the top surface of the wafer C,   4. CF 4 /O 2  plasma etch of silicon dioxide in hole region,   5. DRIE remove to create a silicon hole, and   6. Stripping of the remaining photo resist layer.       

   As a next step, a bonding of resonator wafer A–B according to  FIG. 6  and to base wafer C according to  FIG. 34  is carried out preferably by an Au to Au thermo compression bonding at temperature of 300° C. to 400° C. The bonding is carried between the contacts  4  of resonator wafer A–B and the seal ring  8   a  of the base wafer C. Post B′ of resonator wafer A–B fits into the post hole  5 ′ of base wafer C as shown in  FIG. 35   b.    
   The post fabrication on wafer A is carried out by photo resist lithography (spray on thick resist), CF 4 /O 2  plasma etch of silicon dioxide, photo resist removal by dry etch. Thereby a post A′ and optional frame formation in the top layer A″ is obtained, as shown in  FIGS. 36   a  and  36   b.    
   The process preferably comprises:
         1. Coating the top surface of wafer A with a layer of photoresist,   2 Projecting light from an illuminator through a mask that contains the pattern, namely the place for the hole region on the top surface of wafer A,   3 Washing of the exposed regions of the photoresist layer and leaving an mask on the top surface of the wafer A,   4 DRIE removes silicon from wafer A,   5 CF 4 /O 2  plasma etch of silicon dioxide from wafer A, whereby a post A′ and optional frame formation in the top layer A″ is obtained, and   6 Stripping of the remaining photo resist layer.       

   A cap wafer D is prepared with a starting material of lightly doped bulk silicon  1  having a thickness of ≦800 μm and having on top and bottom a thin silicon dioxide layer, as shown in  FIGS. 18   a  and  18   b.    
   An opening  1   b  of silicon dioxide holes for front side silicon etching of wire bonding pad is carried out by photo resist lithography, dry etch of silicon dioxide and photo resist removal, as shown in  FIGS. 19   a  and  19   b.    
   Then, a backside metallization is carried out by photo resist lithography and metal deposition and liftoff. Thereby Ti/Pt/Au  8  and solder metal  12  are attached, as shown in  FIGS. 20   a  and  20   b.    
   Then backside cavities  13   a  and  13   b  are formed on the cap wafer D by spray thick photo resist on the backside, DRIE etch SiO 2 , DRIE cavities and remove photo resist, as shown in  FIGS. 21   a  and  21   b.    
   The cap wafer D is bonded to the base wafer C. The cap wafer D is positioned on top of base wafer C. A solder bond is carried out at low temperature at about 200° C. between the solder metal  12  of the cap wafer D and the seal ring metal  8   a  of the base wafer C, as shown in  FIGS. 37   a  and  37   b . This preferred process step is carried out as described above in regards to  FIGS. 22   a  and  22   b.    
   A channel  14  is formed by wet etching (KOH) of silicon, as shown in  FIGS. 38   a  and  38   b . This preferred process step is carried out as described above in regard to  FIGS. 23   a  and  23   b.    
   The process preferably comprises the following steps. Wet etching (KOH) of silicon from the top of the cap wafer D in the position of the hole  1   b  and generating a hole. The hole from the top of the cap wafer D combines with the cavity  13  from the bottom of the cap wafer D generating a channel  14 . 
   A ball bonding of wires  15  by vacuum oven bake is carried out as shown in  FIGS. 39   a  and  39   b . The process preferably comprises leading a wire  15  from the top of the cap wafer D and attaching the wire to the wire bonding pad Ti/Pt/Au  8   c  on the bottom wafer C. This process step is preferably carried out as described above in regards to  FIGS. 24   a  and  24   b.    
   Although certain preferred embodiments of the present invention have been described above, these should not be construed as limiting the scope of the invention but as merely providing illustrations of some of the presently preferred embodiments of this invention.