Abstract:
A lower-cost and more precise control methodology of regulating the output current of a Flyback converter from the primary side is provided. The methodology regulates the output current accurately in both continuous current mode (CCM) and discontinuous mode (DCM) and can be applied to most small, medium, and high power applications such as cell phone chargers, power management in desktop computers and networking equipment, and, generally, to a wide spectrum of power management applications. Two highly integrated semiconductor chips based on this control methodology are also described that require very few components to build a constant current Flyback converter.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   The present utility patent application claims priority benefit of the U.S. provisional application for patent having Ser. No. 60/691,980, filed on Jun. 16, 2005, under 35 U.S.C. 119(e). The contents of this related provisional application are incorporated herein by reference. 

   COPYRIGHT NOTICE 
   A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or patent disclosure as it appears in the Patent and Trademark Office, patent file or records, but otherwise reserves all copyright rights whatsoever. 
   FIELD OF THE INVENTION 
   The present invention relates generally to the field of power conversion. More particularly, the invention relates to switching mode power supplies with regulated output current. 
   BACKGROUND OF THE INVENTION 
   With the aggressive growth of battery powered portable electronics, e.g., cell phones, the demand for lower cost, lighter weight and better efficiency battery chargers is very high. Historically, linear power supplies have been employed. However, despite being low in cost, they cannot generally outperform switching mode power supplies, which have lower weight and much higher efficiency. For many applications, the Flyback converter is often chosen from among different switching mode topologies to meet this demand due to its simplicity and good efficiency. 
   Over the years, various integrated circuit (IC) chips have been developed and used to build constant current Flyback power supplies. For example,  FIG. 1  is an illustration of a prior art secondary side controlled constant output current Flyback converter. Such a converter comprises a transformer  201  (which has three windings), a secondary side resistor  301  (which represents the copper loss of transformer  201 ), a primary switch  105 , a current sense resistor  106 , a secondary rectifier  302 , an output capacitor  303 , an optical coupler  202 , a second current sense resistor  305 , a bias resistor  304 , a current limit transistor  306 , and a conventional Pulse Width Modulation (PWM) control IC  104 . Resistor  101  and capacitor  102  provide the initial start-up energy for IC  104 . A general characterization of basic concepts of operation will be described next. Once the Flyback converter is stable, IC  104  is powered by the auxiliary winding (with Na number of turns) of transformer  201  via rectifier  103 . The output current is controlled by resistor  305  and transistor  306 . Transistor  306  regulates the voltage across resistor  305  to a preset voltage VBE (e.g., 0.65V). The output current, therefore, is equal to VBE divided by the resistance of resistor  305 . This circuit, however, is generally undesirable at least both because VBE and the output current vary with temperature and the voltage VBE causes significant power loss. 
   Some known approaches for primary feedback control of constant output current switching regulators teach the use of a reflected auxiliary winding voltage or current to control the primary inductor peak current. One known deficiency of such known methods is that the output current constant control is applicable only in discontinuous conduction mode (DCM) operation, thereby limiting the power capability of the power converter. For operation in continuous conduction mode (CCM), current industry solutions almost entirely rely exclusively on the use of an optocoupler as shown in  FIG. 1 . Typically, they will use the auxiliary current/voltage (e.g., via diode and RC filters) to control the peak primary current. When auxiliary current (i.e., the control current) decreases, the primary current is reduced. Some known techniques use auxiliary voltage to control primary current by essentially scaling the peak current (IPEAK) as proportional to a square root of the output voltage; i.e., SQRT(VOUT). 
   In view of the foregoing, what is needed is a relatively low-cost and effective control methodology of regulating the primary side output current of a Flyback converter. It would be desirable if at least some of the foregoing limitations of the prior art are overcome for operation in both continuous current mode (CCM) and discontinuous mode (DCM), preferably with a minimal number of IC chips (e.g., two IC chips). It is further desirable that the need for a secondary circuit and optical coupler are eliminated, and that the output current of a Flyback converter be largely insensitive to temperature variations. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: 
       FIG. 1  is an illustration of a prior art secondary side controlled constant output current Flyback converter; 
       FIG. 2  is an example of a primary side controlled constant output current Flyback converter according to a first embodiment of the present invention; 
       FIG. 3  illustrates an exemplary block diagram of IC chip shown in  FIG. 2  in accordance with an embodiment of the present invention; 
       FIG. 4  illustrates exemplary ideal waveforms of the auxiliary winding voltage, primary switch current, and secondary rectifier current operating in continuous current mode (CCM) according to an embodiment of the present invention; 
       FIG. 5  illustrates exemplary ideal waveforms of the auxiliary winding voltage, primary switch current and secondary rectifier current operating in discontinuous current mode (DCM) according to an embodiment of the present invention; 
       FIG. 6  illustrates an exemplary schematic of a primary side controlled constant output current Flyback converter in an Emitter Switching configuration using the first IC chip embodiment, in accordance with an embodiment of the present invention; 
       FIG. 7  illustrates an exemplary block diagram of a PWM controller IC chip  704 , in accordance with a second embodiment of the present invention; 
       FIG. 8  is an exemplary schematic of a primary side controlled constant output current Flyback converter using the second embodiment with an external MOSFET and current sensing resistor; 
       FIG. 9  illustrates a schematic diagram of an exemplary digital frequency jittering circuit that is suitable to implement the foregoing jitter functional block, in accordance with an embodiment of the present invention; and 
       FIG. 10  illustrates an exemplary jitter frequency control logic diagram for the exemplary digital frequency jittering circuit of  FIG. 9 , in accordance with an embodiment of the present invention 
   

   Unless otherwise indicated illustrations in the figures are not necessarily drawn to scale. 
   SUMMARY OF THE INVENTION 
   To achieve the foregoing and other objects and in accordance with the purpose of the invention, a variety of techniques to regulate the output current of a switching regulator are described. 
   Some embodiments of the present invention provide a primary side, constant output current PWM controller system and/or IC for a switching regulator with a transformer having at least a primary, a secondary, and an auxiliary winding, where the system or regulator includes: a reference signal for setting the output current level of the switching regulator; a transformer reset time detector that has a feedback input for the auxiliary winding of the transformer used in a switching regulator and computes a transformer reset time signal based on the auxiliary winding feedback input; a multiplier, which outputs a calculation (e.g., multiplication) on signals that is derived from a feedback signal corresponding to the output current of the switching regulator and the transformer reset time signal, the output of the multiplier being operable as a calculated output current; an error amplifier, which outputs a signal based on the difference between the reference signal and the calculated output current; a comparator that is configured to compare one or more ramp signals such as, without limitation, the output of the calculator unit, the error amplifier output and/or the output current feedback signal; a PWM controller module that outputs a PWM switching regulator control signal based on an oscillator output and the comparator output; and a gate drive module that receives the PWM control signal and generates a corresponding gate drive signal operable for properly turning on and off a switched power output device of the switching regulator. 
   A multiplicity of other embodiments may further provide variations of the prior embodiments in which the reference signal is a programmable current mirror circuit operable to output a programmed current; and/or in which the switched power output device is a power MOSFET that is configured as the main power switch of the switching regulator; and/or embodiments further include a current sensing circuit for generating the output current feedback signal where the current sensing circuit optionally comprises a MOSFET connected in parallel with the switched power output device; and/or in which the comparator is a peak current mode PWM comparator with a slope-compensation input. 
   Another embodiment of the present invention provides means for achieving the functions described in the foregoing system embodiments. 
   In yet other embodiments of the present invention, a constant output current PWM controller printed circuit board (PCB) module is described that includes a PCB and an embodiment of the foregoing integrated circuit device joined onto the PCB, where the PCB can be optionally populated with the necessary electronic components such that, in functional combination with the integrated circuit (IC) device, the PCB module is operable to perform as a constant current switching regulator. 
   A method, according to another embodiment of the present invention, is provided for regulating the output current of a Flyback converter from the primary side, and such method includes steps for: computing a calculated output current based on the average current of a primary power switch and a transformer reset time, regulating the output current of the Flyback converter to a desired value, and reducing the temperature sensitivity of the output current. 
   Other features, advantages, and object of the present invention will become more apparent and be more readily understood from the following detailed description, which should be read in conjunction with the accompanying drawings. 
   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The present invention is best understood by reference to the detailed figures and description set forth herein. 
   Embodiments of the invention are discussed below with reference to the figures. However, those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanatory purposes as the invention extends beyond these limited embodiments. For example, it should be appreciated that those skilled in the art will, in light of the teachings of the present invention, recognized a multiplicity of alternate and suitable approaches, depending upon the needs of the particular application, to implement the functionality of any given detail described herein, beyond the particular implementation choices in the following embodiments described and shown. That is, there are numerous modifications and variations of the invention that are too numerous to be listed but that all fit within the scope of the invention. Also, singular words should be read as plural and vice versa and masculine as feminine and vice versa, where appropriate, and alternatives embodiments do not necessarily imply that the two are mutually exclusive. 
   The present invention will now be described in detail with reference to embodiments thereof as illustrated in the accompanying drawings. 
     FIG. 2  illustrates an exemplary circuit implementing a PWM controller IC chip  204 , in accordance with a first embodiment of the present invention. The circuit shown is a primary side controlled constant output current Flyback converter. The converter shown comprises a transformer  201  (which has three separate coil windings: primary with N p  turns, secondary with N s  turns, and auxiliary with N a  turns), a secondary side resistor  301  (which represents the copper loss of transformer  201 ), a secondary rectifier  302 , an output capacitor  303 , and a peak current mode PWM control IC  204 . Resistor  101  and capacitor  102  provide the initial start-up energy for IC  204 . Once the Flyback converter is stable, IC  204  is powered by the auxiliary winding of transformer  201  via rectifier  103 . Resistor  109  programs the output current. Resistor dividers  105  and  106  then provide an input signal for computing the transformer reset time (T r ) via the T r  Detection circuit inside IC  204 . 
     FIG. 3  illustrates an exemplary block diagram of IC chip  204  shown in  FIG. 2  in accordance with an embodiment of the present invention. As illustrated, V CC  supply  401  provides an internal power supply and reference voltage. Current mirror  402  duplicates current I set  to resistor  403 . T r  Detection  405  computes T r  based on the V a  voltage waveform coming from FB input pin. Those skilled in the art, in light of the teachings of the present invention, will readily recognize that the feedback for the FB input pin may come from any other suitable source beyond the auxiliary winding of the transformer such as, by way of example, and not limitation, from the primary winding. In alternate embodiments of the present invention (not shown), the transformer does not have any auxiliary windings, and only has a primary and a secondary winding. Those skilled in the art, will recognize a multiplicity of alternate and suitable transformer types and interface circuit configurations to be operable with connection to the FB input pin. 
   In the embodiment shown, calculation unit  406  performs multiplication between I P     —     AVG  and T r , however, in other embodiments of the present invention, depending on the needs of the particular application, any suitable math function may be implemented instead of multiplication, as will be readily determined by those skilled in the art, in light of the present teachings. 
   Error amplifier  404  then compares the calculated output current with a programmed value across resistor  403 . Resistor  407  and capacitor  408  are coupled to form an averaging circuit for the primary current. Resistor  409  and capacitor  410  form a compensation network for amplifier  404 . Comparator  412  serves as a peak current mode PWM comparator with an optional slope compensation input. In other embodiments of the present invention (not shown), the comparator may be configured by those skilled in the art to compare any suitable ramp signals depending upon the needs of the particular application. System oscillator  411  provides an optional frequency jittering function that widens the frequency spectrum and achieves a lower conducting EMI emission. An example of a preferred frequency jittering circuit is described in connection with  FIG. 9 . 
   Alternate embodiments of the present invention may not include the frequency jittering function in system oscillator  411  and/or slope compensation. In many applications, slope compensation and the system oscillator jitter function can improve converter operation in certain input/output operating conditions; however, these functions are completely optional, whereby alternate embodiments of the present invention may not include either one or both. 
   PWM control unit  417  then generates the correct PWM waveform by utilizing a cycle-by-cycle current limiting function. MOSFET  413  is a relatively high speed MOSFET gate driver. Power internal MOSFET  415  serves as the main switch, while a small die size allocated internal MOSFET  414  and resistor  416  form a current sense circuit. As will be readily apparent to the system designer, some applications may not require resistor  416  to generate the current sensing voltage feedback or it may be located in other circuit configurations, or embedded into other system components. As will be readily recognized by those skilled in the art, depending upon the needs of the particular application and current technology, the power MOSFET may be formed in any suitable manner. By way of example, and not limitation, the power MOSFET may be comprised of a multiplicity of smaller MOSFET device to form a single power MOSFET. In contrast with conventional approaches that only work in DCM, the present embodiment implements a method for using “sampled Auxiliary Flyback Voltage” to control the primary current. Sampling the Auxiliary Flyback Voltage at a known time point provides a more accurate representation of the actual output voltage in most applications. The present embodiment is largely independent of auxiliary voltage and/or current by, for example, basing output current control only on primary current sensing and the ratio of T_R/T_ON, which works in both DCM and CCM. Hence, embodiments of the present invention preferably do not use auxiliary voltage to control primary current by essentially scaling the peak current (IPEAK) as proportional to a square root of the output voltage, as is done in conventional approaches. 
     FIG. 4  illustrates exemplary ideal waveforms of the auxiliary winding voltage, primary switch current, and secondary rectifier current operating in continuous current mode (CCM) according to an embodiment of the present invention. Main switch  415  turns on at t 1 , turns off at t 2  and turns on again at t 3 . The switching period is T, the turn-on time is T on  and the turn-off time is T r . Using known theory, the output current I out  can be expressed as:
   I   out =(½)·( I   S1   +I   S2 )·( T   r   /T ).  (1) Because   I   S1 =( N   P   /N   S )· I   P1   (2) and   I   S2 =( N   P   /N   S )· I   P2 ,  (3) 
I out  may be expressed by combining (1), (2) and (3) as shown in (4) below.
   I   out =(½)·( N   P   /N   S )·( I   P1   +I   P2 )·( T   r   /T ).  (4) Furthermore, because   I   P     —     AVG =(½)·( I   P1   +I   P2 )·( T   ON   /T )  (5) 
equations (4) and (5) may be combined to express I out  as shown in (6) below
   I   out =( N   P   /N   S )·( T   r   /T   ON )· I   P     —     AVG   (6) 
     FIG. 5  illustrates ideal waveforms of the auxiliary winding voltage, primary switch current, and secondary rectifier current operating in discontinuous current mode (DCM) according to an embodiment of the present invention. Main switch  415  turns on at t 1 , turns off at t 2 , and turns on again at t 4 . The switching period is T, the turn-on time is T on  and the turn-off time is equal to (t 4 -t 2 ). As shown in  FIG. 5 , the current at the secondary winding of transformer  201  discharges to zero at t 3 . Because Tr is equal to (t 3 -t 2 ), the output current can be expressed as:
   I   out =(½)· I   S2 ·( T   r   /T ).  (7) 
Because  I   S2 =( N   P   /N   S )· I   P2 ,(8)
 
I out  may be expressed by combining (7) and (8) as shown in (9) below:
   I   out =(½)·( N   P   /N   S )· I   P2 ·( T   r   /T ).  (9) Furthermore, because   I   P     —     AVG =(½)· I   P2 ·( T   ON   /T ),  (10) 
   I out  may be expressed by combining (9) and (10) as shown in (11) below
 
 I   out =( N   P   /N   S )·( T   r   /T   ON )·I P     —     AVG   (11)
 
   The output power of the converter generally depends only on the stored energy of the inductor in DCM operating mode, in accordance with the following formula (12), which neglects efficiency losses:
 
 Vo*Io =(½)* Lp*Ip   2   *F.   (12)
 
In the CCM operating mode, at the output of the converter output, the voltage is dropping from V norm  to zero. To keep Io constant, F is preferably reduced proportionally to Vo while maintaining a fixed Ip.
 
     FIG. 6  illustrates an exemplary schematic of a primary side controlled constant output current Flyback converter in an emitter switching configuration using the first IC chip embodiment, in accordance with an embodiment of the present invention. For many low power applications, using current on-chip MOSFET technology, no external power MOSFET or current sense circuit is needed. For higher output power and/or higher switching frequency than the internal on-chip MOSFET can properly handle, however, external power handling components may be required. For example, the approach of the present embodiment is to introduce NPN bipolar transistor  105  that cooperates with IC chip  204 , of the present invention, in an emitter switching configuration as shown in the figure. In such a configuration, internal MOSFET  415  drives the emitter of external NPN transistor  105  which serves as the main switch. To further increase the power handling capability and switching frequency, an external MOSFET is typically used as the main switch. 
     FIG. 7  illustrates an exemplary block diagram of a PWM controller IC chip  704 , in accordance with a second embodiment of the present invention. IC chip  704  does not include internal power MOSFET  415 , current sensing MOSFET  414 , and current sensing resistor  416  from the first IC chip embodiment of  FIG. 3 . In this second embodiment, the current driving capability of gate drive  413  results in improved control for larger MOSFETs.  FIG. 8  illustrates an exemplary schematic for implementing IC chip  704  with an external MOSFET and a current sense resistor. 
   The functional blocks shown in the prior embodiments may be implemented in accordance with known techniques as will be readily apparent to those skilled in the art. However, some embodiments of the present invention include implementation approaches that are not conventional. For example, without limitation, the foregoing jitter functional block may be implemented as follows.  FIG. 9  illustrates a schematic diagram of an exemplary system oscillator  411  having a digital frequency jittering circuit that is suitable to implement the foregoing jitter functional block, in accordance with an embodiment of the present invention. The frequency jittering in the present embodiment is implemented by a digital control scheme, which departs from known approaches. An oscillator  817  is preferably a current controlled oscillator. There is preferably an uncontrolled, base-line, current source  801 , which, in one aspect, is present to set a minimum oscillator frequency, Fmin, that the switched current sources will jitter from. In the embodiment shown, the current to oscillator  817  is controlled by a multiplicity of switched current sources  802 - 804  that carry out the jittering of the oscillator&#39;s minimum frequency. The frequency of the system oscillator output signal is generally proportional to the total current entering into oscillator  817 . In alternate embodiments, any number of current sources may be implemented depending upon the needs of the particular application. The jitter behavior is generated by feeding back the output signal of oscillator  817  to a multiplicity of series connected flip-flops (e.g.,  818  to  823 ). Current sources  801 ,  802 ,  803  and  804  are presently preferred to be currents of magnitudes 100 μA, 2.5 μA, 5 μA and 10 μA, respectively. Each switched current source is presently configured with four current control switches (e.g., control switches  805 ,  806 ,  811  and  812  for switched current source  802 ) that are arranged in two parallel legs with each leg having two switches in series. In this way, for current to flow into oscillator  817  at least one leg must have both of its switches turned on. In similar fashion, four switches ( 807 ,  808 ,  813  and  814 ) are connected to switched current source  803  and another four switches ( 809 ,  810 ,  815  and  816 ) are connected to switched current source  804 . All of these switches are closed or open by a control input from an output from the series connected flip-flop chain. In the example shown, the switch  805  is open when Q 5  is at logic level “1” and is closed when Q 5  is at logic level “0”. Similarly, the  806  switch is open when Q 5  is at logic level “0” and is closed when Q 5  is at logic level “1”, and so on. When all the switched current sources are enabled, a maximum frequency, Fmax, of the system oscillator output signal is achieved. As will be readily apparent to those skilled in the art, in light of the present teachings, the choice of which flip-flop outputs connect to which current control switch will determine a certain jittering pattern. An aspect of this digital frequency jittering scheme is that the period &amp; the step of frequency variation may be relatively precisely controlled, and is largely insensitive to temperature variations. It should be appreciated that in contrast to conventional analog techniques for jittering the oscillator frequency, the digital jittering approach of the present embodiment always provide digitally calculated frequency step irrespective of the known shortcomings that analog based techniques suffer from; such as, without limitation, temperature, input, output age dependences, etc. Those skilled in the art, in light of the present teachings, will readily recognize a multiplicity of alternate and suitable implementations that implement the spirit of the present embodiment. By way of example, and not limitation, current based operation may be replaced with a voltage based approach, and the number and topology of the switches and/or current sources and/or flip-flop chain may be altered as needed for the particular application, and other suitable means to selectively control the pattern of current flowing into the current controlled oscillator. 
     FIG. 10  illustrates an exemplary jitter frequency control logic diagram for the exemplary digital frequency jittering circuit of  FIG. 9 , in accordance with an embodiment of the present invention. In the example shown, frequency variation from its maximum (Fmax) to minimum (Fmin) corresponding to the logic states “0” or “1” of Q 2 , Q 3 , Q 4  and Q 5 . 
   Having fully described at least one embodiment of the present invention, other equivalent or alternative methods of implementing a primary side constant output current controller according to the present invention will be apparent to those skilled in the art. The invention has been described above by way of illustration, and the specific embodiments disclosed are not intended to limit the invention to the particular forms disclosed. The invention is thus to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the following claims.