Abstract:
The invention discloses a new architecture of multiphase delay-locked loop (DLL) with innovative 3-edge phase detector (3-edge PD), which compares the VCDL&#39;s first delay interval and the last delay interval to send an Up pulse or a Dn pulse to adjust the interval among those delay clock phases. The DLL may achieve both wide-range operation and multiple clock phase generation, and is also immune to multi-selection problem.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a multiphase Delay-Lock Loop (DLL), and more particularly, to a multiphase DLL for Wide-Range Operation. 
         [0003]    2. Description of the Prior Art 
         [0004]    Along with the continuous innovative development of the Complementary metal-oxide-semiconductor (CMOS), the processing speed and the circuit density of the integrated circuit (IC) increase continuously. Therefore, the synchronous processing between modules become an important issue, and so as to form a bottleneck for the development of IC. 
         [0005]    Presently, the high-level circuit has a strong demand for the system clock signal source with high speed and quality. Nevertheless, the propagation delay of the clock driver or the phase difference will easily cause problems when the system clock signal source is operated in high speed, and so as to affect the chip reliability and the system performance. Accordingly, the design of the high-level circuit, such as a microprocessor, a real-time system or a data communication device, often needs to add a Phase-Locked Loop (PLL) with low voltage, high frequency and low jitter to serve as an auxiliary to correct the characteristic of the input clock signal source. 
         [0006]    The CMOS PLL and the Delay-Lock Loop (DLL) are designed to solve the synchronous problem of the circuit clock, and the DLL is more stable than the PLL because of the structural difference. Further, the DLL seldom uses capacitors. Accordingly, there are more and more applications, such as the circuits of the clock recovery and the local oscillator, utilize the DLL to replace the PLL because the DLL is easy to design and stable recently. Additionally, the signal jitter of the DLL is not obvious. Because the noise in the Voltage-Controlled Delay Line (VCDL) will not accumulate after several clock cycles, such that the DLL is an ideal circuit unit for the clock synchronization processing and is suitable for applying for the radio frequency synthetic circuit and the high-speed serial connection. 
         [0007]      FIG. 1  is a schematic diagram of a conventional DLL structure. The VCDL  11  receives a reference clock (Ref-Clk) signal, and then output several signals with phase delay. The output signals feedback to the phase detector (PD)  12 , the charge pump (CP)  13  and the Loop Filter (LF)  14 . The operation theory of the DLL is utilizing a delay element to automatically generate plural delay clock (DLL-Clk) signals with fixed phase difference according to the external input reference clock (Ref-Clk) signals, then orderly passing these DLL-Clk signals through functional circuit and then comparing with the original Ref-Clk signals to check if they are synchronous. Thus, there will be a DLL-Clk signal, which phase difference is small enough to be accepted as a locked DLL-Clk signal to accomplish the DLL process, to be selected through the selection of the control circuit. 
         [0008]      FIG. 2A  is a schematic diagram to show the condition that a DLL-Clk signal leads a Ref-Clk signal in a clock range AA′, these two signals can be synchronous as shown in  FIG. 2B  after the DLL operation.  FIG. 3A  is a schematic diagram to show the condition that a DLL-Clk signal lags a Ref-Clk signal in a clock range BB′, these two signals can be synchronous as shown in  FIG. 3B  after the DLL operation. However, the calibration range of the DLL for the signal deviation is AA′ to BB′, the vague multi-locking problem will be produced if the rising edge of the signal is not within this range. 
         [0009]    The inequalities to be immune to multi-selection are shown in (1.1) and (1.2). 
         [0000]      0.5 ×T   CLK   &lt;T   VCDL (min)&lt; T   CLK   (1.1) 
         [0000]        T   CLK   &lt;T   VCDL (max)&lt;1.5 ×T   CLK   (1.2) 
         [0010]    For example, 20 ns&lt;T CLK &lt;40 ns is obtained from (1.1) and 26.7 ns&lt;T CLK &lt;40 ns is obtained from (1.2) if T VCDL (max)=40 ns. Accordingly, it can be understood from the aforementioned inequalities that the operational delay range of the T CLK  for the conventional DLL structure is limited. 
       SUMMARY OF THE INVENTION 
       [0011]    In order to solve the aforementioned problem, one object of the present invention is to provide a multiphase DLL for wide-range operation, which has a 3-edge Phase Detector (PD) to receive the reference, small delay and large delay clock signals, and then obtains a phase difference between the up signal (Up) and the down signal (Dn) by comparing three clock signals to adjust a control voltage for dynamically adjusting the delay time through the voltage control of the Voltage Control Delay Line (VCDL). The phase of the delay clock signal is changed, and the clock cycle time equally distributed to all delay clock signals, such that the operation range of the delay time is wider. 
         [0012]    Another object of the present invention is to provide a 3-edge PD that uses two comparison circuits to respectively compare the reference clock signal, the final output Dn of the small delay clock signal and the final output Up of the large delay clock signal. Finally, the Dn and Up are transmitted to a CP. 
         [0013]    Another object of the present invention is to provide a method to lock clock for a multiphase DLL with wide-range operation, which adjusts the delay signals in the VCDL to make the starting time of each delay signal averagely fall into a reference clock cycle and so as to avoid the vague multi-locking problem. 
         [0014]    To achieve the purposes mentioned above, one embodiment of the present invention is to provide a multiphase DLL for wide-range operation, which includes: a VCDL to receive a reference clock signal to generate several delay clock signals, wherein the delay clock signals include a first delay clock signal and a second delay clock signal; a 3-edge PD to generate a set of pulse signals according to the reference clock signal, the first delay clock signal and the second delay clock signal; a CP to receive the pulse signals and output a current control signal; and an Loop Filter (LF) to receive the current control signal and output a control voltage, wherein a delay time is adjusted by the VCDL according to the control voltage. 
         [0015]    Additionally, a 3-edge PD that is used to increase the operation range of the clock width according to one embodiment of the present invention, wherein the 3-edge PD receives a reference clock signal, a first delay clock signal and a second delay clock signal, and finally output a set of pulse signals. 
         [0016]    Furthermore, a method to lock clock for a multiphase DLL with wide-range operation, which includes: setting a minimum delay time among a plurality of delay signals existed in the VCDL and arranged according to the time order to make the delay signals have the same delay time between each other, wherein a time interval between a first delay signal and a starting edge of a clock cycle is T 1 , and a time interval between a second delay signal and a starting edge of a clock cycle is Tn; comparing T 1  and Tn to adjust the delay time and so as to make the delay signals fall into a reference clock cycle; increasing the delay time to make the delay signals have the same delay time between each other and so as to make the delay signals fall into a reference clock cycle if T 1 &lt;Tn; and decreasing the delay time to make the delay signals have the same delay time between each other and so as to make the delay signals fall into a reference clock cycle if T 1 &gt;Tn. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    The foregoing aspects and many of the accompanying advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description when taken in conjunction with the accompanying drawings, wherein: 
           [0018]      FIG. 1  is a schematic diagram of a conventional DLL structure; 
           [0019]      FIG. 2A  and  FIG. 2B  are schematic diagrams to show the condition that a DLL-Clk signal leads a Ref-Clk signal in a clock range AA′ for a conventional DLL; 
           [0020]      FIG. 3A  and  FIG. 3B  are schematic diagrams to show the condition that a DLL-Clk signal lags a Ref-Clk signal in a clock range BB′ for a conventional DLL; 
           [0021]      FIG. 4  is a structural schematic diagram to demonstrate a multiphase DLL for wide-range operation according to one embodiment of the present invention; 
           [0022]      FIG. 5A  is a waveform schematic diagram to demonstrate a starting clock signal according to one embodiment of the present invention; 
           [0023]      FIG. 5B  is a waveform schematic diagram to demonstrate a clock signal after adjusting according to one embodiment of the present invention; 
           [0024]      FIG. 6A  and  FIG. 6B  are structural schematic diagrams to demonstrate a 3-edge PD according to one embodiment of the present invention; 
           [0025]      FIG. 7A  and  FIG. 7B  are schematic diagrams to relatively demonstrate the operational schematic diagrams to demonstrate the clock signals corresponding to  6 A and  FIG. 6B ; 
           [0026]      FIG. 8  is a schematic diagram to demonstrate a method to lock clock for a multiphase DLL according to one embodiment of the present invention; and 
           [0027]      FIG. 9   a  to  FIG. 9   f  are schematic diagrams to demonstrate the mechanism for avoiding multi-locking according to one embodiment of the present invention. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0028]      FIG. 4  is a structural schematic diagram to demonstrate a multiphase DLL for wide-range operation according to one embodiment of the present invention. In this embodiment, a VCDL  21  includes several sequentially connected delay elements to receive a reference signal Ref-Clk and output one to N delay clock signals DLL-Ck 1 , DLL-Ck 2 , . . . DLL-Ckn. Wherein the first delay clock signal is outputted from the first delay element and the second delay clock signal is outputted from the Nth delay element, and the first delay clock signal DLL-Ck 1  and the Nth delay clock signal DLL-Ckn feedback to a 3-edge PD  22 . Further, the Ref-Clk is also input to the 3-edge PD  22 , thus the 3-edge PD  22  receives 3 input signals and then output a set of pulse signals which includes a down signal Dn and an up signal Up after processing. 
         [0029]    In one embodiment, the processing way of the 3-edge PD  22  is comparing the first DLL-Ck 1  and the last DLL-Ckn to decide a lead or lag phase difference, and finally generate an Up or Dn signal having the same width with the phase difference. 
         [0030]    Next, the information of the frequency difference between the Up and Dn signals is transmitted to a CP  23  succeeded after the 3-edge PD  22  to serve as a reference and control the CP  23  and so as to generate a current Ip for charging or discharging a capacitor (not shown in the figure) in the succeeding LF  24 , which means increasing or decreasing the voltage value of the capacitor in the LF  24 . The LF  24  will filter out the high-frequency noise produced in the 3-edge PD  22  and the CP  23  and generate a control voltage Vcntl. The Vcntl can adjust the delay time (T VCDL ) of the VCDL  21  through the VCDL  21  and change the phase of the internal clock, and then feedback to the 3-edge PD  22  to start a comparison action of next cycle. In one embodiment, the LF  24  is a capacitor. 
         [0031]    In the above mentioned structure, the first output delay clock signal DLL-Ck 1  has a phase difference T 1  to the reference clock signal Ref-Clk, and the last output delay clock signal DLL-Ckn has a phase difference Tn to the reference clock signal Ref-Clk. When the DLL starts or restarts, the delay time T VCDL  of the VCDL  21  is set in minimum value (T 1 &lt;Tn) as shown in  FIG. 5A . After the difference value between the phase difference T 1  and the phase difference Tn, using a voltage regulation way to make T 1 =Tn as shown in  FIG. 5B . The locking range of the DLL is described in equation (2): 
         [0000]      T VCDL(min) &lt;T CLK &lt;T VCDL(max)   (2) 
         [0032]    The operation range of the VCDL  21  can totally operate within the locking range of the DLL. 
         [0033]      FIG. 6A  and  FIG. 6B  are structural schematic diagrams to demonstrate a 3-edge PD according to one embodiment of the present invention. In  FIG. 6A , the D-type flip-flop  221  receives the Ref-Clk and a data signal, and then output a Dn. The D-type flip-flop  222  receives the DLL-Ck 1  and the Dn, and then output a signal to the AND logic-gate  223 . The AND logic-gate  223  receives the Dn and the digital sampling signal outputted from the D-type flip-flop  222  to decide if it needs to transmit a restart signal rst 1  for restarting the D-type flip-flops  221  and  222  or not, wherein the schematic diagram of the signal action is shown in  FIG. 7A . 
         [0034]    In  FIG. 6B , the D-type flip-flop  226  receives the DLL-Ckn and a data signal, and then output an Up. The D-type flip-flop  227  receives the Ref-Clk and the Up, and then output a signal to a AND logic-gate  228 . The AND logic-gate  228  receives the Up and the digital sampling signal outputted from the D-type flip-flop  227  to decide if it needs to transmit a restart signal rst 2  for restarting the D-type flip-flops  226  and  227  or not, wherein the schematic diagram of the signal action is shown in  FIG. 7B . 
         [0035]    Please refer to  FIG. 8 , which is a schematic diagram to demonstrate a method to lock clock for a multiphase DLL according to one embodiment of the present invention. Step  10  sets a minimum delay time among a plurality of delay signals existed in the VCDL and arranged according to the time order to make the delay signals have the same delay time between each other, wherein a time interval between a first delay signal and a starting edge of a clock cycle is T 1 , and a time interval between a last delay signal and a starting edge of the next clock cycle is Tn, and all the delay signals are distributed within a clock cycle. When the circuit starts to operate, T 1  is smaller than Tn. Step  20  judges if it is a multi-locking or not, which will go back to Step  10  if it is a multi-locking or go to the next step if it is not a multi-locking. Step  30  compares T 1  and Tn to adjust the delay time and so as to make the delay signals fall into a reference clock cycle, and finally lock T 1  to equal to Tn. Then, step S 41  is executed, it means increasing the delay time to make the delay signals have the same delay time between each other and so as to make the delay signals fall into a reference clock cycle if T 1 &lt;Tn, or decreasing the delay time to make the delay signals have the same delay time between each other and so as to make the delay signals fall into a reference clock cycle if T 1 &gt;Tn. 
         [0036]    Please refer to  FIG. 9   a  to  FIG. 9   f , which are schematic diagrams to demonstrate the mechanism for avoiding multi-locking according to one embodiment of the present invention. When the circuit operates, several delay clock signals Dll_ck 1 , Dll_ck 2 , Dll_ck 3 , Dll_ck 4 , Dll_ck 5  and Dll_ck 6  are generated after a reference clock signal Ref_Clk is received by the VCDL. When the frequency of the clock signal changes into B from A to make the circuit work normally and lock in a clock cycle, three adjacent clock signals are utilized to do the judgments which are described in the following. 
         [0037]    Among the three adjacent clock signals Ref_Clk, Dll_ck 1  and Dll_ck 2 , if the value for the rising edge of the Dll_ck 2  sampling Ref_Clk equals to 0, it represents the 2nd or the 3rd cycle is locked as shown in  FIG. 9   b  to  FIG. 9   c . Otherwise, if the value for the rising edge of the Dll_ck 2  sampling Dll_ck 1  equals to 0, it represents the 4th, 5th or 6th cycle is locked as shown in  FIG. 9   d ,  FIG. 9   e  and FIG.  9   f , which needs to reset the circuit. If the value for the rising edge of the Dll_ck 2  sampling Ref_Clk equals to 1, it represents the 1st, 4th or the 5th cycle is locked. Otherwise, if the value for the rising edge of the Dll_ck 2  sampling Dll_ck 1  equals to 1, it represents the 1st, 2nd or 3rd cycle is locked, and the circuit is normal if the 1st cycle is locked that the delay clock signals fall into a reference clock cycle as shown in  FIG. 9   a.    
         [0038]    According to the aforementioned description, the judgment can be made by inputting the values of the rising edge of the Dll_ck 2  sampling Ref_Clk and Dll_ck 1  into a logic circuit (not shown in the figure). 
         [0039]    To sum up, the multiphase DLL with a 3-edge PD having phase difference and frequency difference of the present invention is advantageous to the whole PLL, which can maximize the wide-clock width of the operation range. 
         [0040]    The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustrations and description. They are not intended to be exclusive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.