Abstract:
An LCD device having dual source drivers and related driving method are disclosed for performing data signal driving operation by making use of a data writing synchronous control mechanism. The operation of the data writing synchronous control mechanism includes furnishing all image data signals to both the first and second source drivers, latching odd and even image data signals by the first and second source drivers respectively, performing a signal processing process on the odd image data signals for generating a first set of analog data signals by the first source driver, performing a signal processing process on the even image data signals for generating a second set of analog data signals by the second source driver, writing the first set of analog data signals into a plurality of first pixel units, and writing the second set of analog data signals into a plurality of second pixel units.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a liquid crystal display device and related driving method, and more particularly, to a liquid crystal display device based on dual source drivers with data writing synchronous control mechanism and related driving method. 
         [0003]    2. Description of the Prior Art 
         [0004]    Because liquid crystal display (LCD) devices are characterized by thin appearance, low power consumption, and low radiation, LCD devices have been widely applied in various electronic products for panel displaying. In general, the LCD device comprises liquid crystal cells encapsulated by two substrates and a backlight module for providing a light source. The operation of an LCD device is featured by varying voltage drops between opposite sides of the liquid crystal cells for twisting the angles of the liquid crystal molecules of the liquid crystal cells so that the transparency of the liquid crystal cells can be controlled for illustrating images with the aid of the backlight module. 
         [0005]    It is well known that LCD devices perform data writing operations for writing data signals into a plurality of pixel units via a plurality of data lines under the control of a plurality of gate signals. Concerning an LCD device having low resolution, the width of each pixel unit is enough for wiring a corresponding data line so that all the data lines can be coupled to single source driver. However, concerning an LCD device having high resolution, the width of each pixel unit is not enough for wiring a corresponding data line, and therefore two source drivers are required to be disposed on opposite sides of the LCD panel of the LCD device for coupling odd data lines and even data lines respectively. 
         [0006]      FIG. 1  is a schematic diagram showing a prior-art LCD device. As shown in  FIG. 1 , the LCD device  100  comprises a gate driver  110 , a first source driver  120 , a second source driver  150 , an LCD panel  190 , a data processing interface circuit  199 , a plurality of gate lines GL 1 -GLm, and a plurality of data lines DL 1 -DLn. The gate driver  110  is coupled to the plurality of gate lines GL 1 -GLm for providing each gate line with a corresponding gate signal. The first source driver  120  is coupled to a plurality of odd data lines DL 1 , DL 3 -DLn−1 for providing each odd data line with a corresponding data signal. The second source driver  150  is coupled to a plurality of even data lines DL 2 , DL 4 -DLn for providing each even data line with a corresponding data signal. 
         [0007]    The data processing interface circuit  199  performs the signal extracting and frequency down-converting processes on the image data signal Sdata received by the LCD device  100  for generating an odd data signal Sdata_odd and an even data signal Sdata_even. The odd data signal Sdata_odd and the even data signal Sdata_even are then forwarded to the first source driver  120  and the second source driver  150  respectively. That is, the first source driver  120  receives only the odd data signal Sdata_odd, and the second source driver  150  receives only the even data signal Sdata_even. 
         [0008]    Consequently, the first source driver  120  performs signal processing operations only on the odd data signal Sdata_odd for generating corresponding data signals furnished to the plurality of odd data lines DL 1 , DL 3 -DLn−1, and the second source driver  150  performs signal processing operations only on the even data signal Sdata_even for generating corresponding data signals furnished to the plurality of even data lines DL 2 , DL 4 -DLn. Based on the above description, it is obvious that the data processing interface circuit is required to be installed in the prior-art LCD device for performing the signal extracting and frequency down-converting processes on the received image data signal prior to the signal processing operations of dual source drivers. However, as the resolution of the LCD panel is enhanced or the number of gray-scale levels of the image data signal is increased, the circuit design and layout of the data processing interface circuit will become more complicated in that more circuit units are required for performing the signal extracting and frequency down-converting processes in a desirable speed. In summary, the prior-art LCD device is required to provide more peripheral device area for installing the costly data processing interface circuit, and the power consumption in the operation of the prior-art LCD device is increased significantly due to the signal extracting and frequency down-converting processes. 
       SUMMARY OF THE INVENTION 
       [0009]    In accordance with an embodiment of the present invention, a liquid crystal display device based on dual source drivers with data writing synchronous control mechanism is provided. The liquid crystal display device comprises a first set of data lines, a second set of data lines, a plurality of gate lines, a gate driver, a first source driver, a second source driver, and a plurality of pixel units. 
         [0010]    The first set of data lines is utilized for receiving a first set of data signals. The second set of data lines is utilized for receiving a second set of data signals. The plurality of gate lines is utilized for receiving a plurality of gate signals. The gate driver is coupled to the plurality of gate lines for providing the plurality of gate signals. The first source driver is coupled to the first set of data lines. The first source driver transfers the first set of data signals to the first set of data lines after receiving the first set of data signals and the second set of data signals. The second source driver is coupled to the second set of data lines. The second source driver transfers the second set of data signals to the second set of data lines after receiving the first set of data signals and the second set of data signals. Each pixel unit is coupled to a corresponding data line and a corresponding gate line. 
         [0011]    In accordance with another embodiment of the present invention, a liquid crystal display device based on dual source drivers with data writing synchronous control mechanism is provided. The liquid crystal display device comprises a first set of data lines, a second set of data lines, a plurality of gate lines, a gate driver, a clock controller, a first source driver, a second source driver, and a plurality of pixel units. 
         [0012]    The first set of data lines is utilized for receiving a first set of data signals. The second set of data lines is utilized for receiving a second set of data signals. The plurality of gate lines is utilized for receiving a plurality of gate signals. The gate driver is coupled to the plurality of gate lines for providing the plurality of gate signals. The clock controller is utilized for generating a first horizontal start signal, a first horizontal clock signal, a second horizontal start signal and a second horizontal clock signal based on a master clock signal, a horizontal synchronous signal or a vertical synchronous signal. The clock controller comprising a first output end for outputting the first horizontal start signal, a second output end for outputting the first horizontal clock signal, a third output end for outputting the second horizontal start signal, and a fourth output end for outputting the second horizontal clock signal. The first source driver is coupled to the first and second ends of the clock controller for receiving the first horizontal start signal and the first horizontal clock signal. Also, the first source driver is coupled to the first set of data lines for transferring the first set of data signals to the first set of data lines based on the first horizontal start signal and the first horizontal clock signal after receiving the first set of data signals and the second set of data signals. The second source driver is coupled to the third and fourth ends of the clock controller for receiving the second horizontal start signal and the second horizontal clock signal. Also, the second source driver is coupled to the second set of data lines for transferring the second set of data signals to the second set of data lines based on the second horizontal start signal and the second horizontal clock signal after receiving the first set of data signals and the second set of data signals. Each pixel unit is coupled to a corresponding data line and a corresponding gate line. 
         [0013]    The present invention further provides a driving method for driving a liquid crystal display device having a first source driver and a second source driver. The driving method comprises: furnishing a plurality of data signals to the first source driver and the second source driver, wherein the plurality of data signals comprises a first set of data signals and a second set of data signals; transferring the first set of data signals to a plurality of first pixel units via the first source driver; and transferring the second set of data signals to a plurality of second pixel units via the second source driver. 
         [0014]    Furthermore, the present invention provides a driving method for driving a liquid crystal display device having a first source driver and a second source driver. The driving method comprises: furnishing a plurality of data signals to the first source driver and the second source driver; generating a plurality of first control signals by the first source driver, and generating a plurality of second control signals by the second source driver; performing a data-overwrite latching process on a plurality of odd-order data signals of the data signals based on the plurality of first control signals by the first source driver; performing a data-overwrite latching process on a plurality of even-order data signals of the data signals based on the plurality of second control signals by the second source driver; performing a signal processing process on the plurality of odd-order data signals by the first source driver for generating a plurality of first analog data signals; performing a signal processing process on the plurality of even-order data signals by the second source driver for generating a plurality of second analog data signals; outputting the plurality of first analog signals to a plurality of first pixel units by the first source driver; and outputting the plurality of second analog signals to a plurality of second pixel units by the second source driver. 
         [0015]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  is a schematic diagram showing a prior-art LCD device. 
           [0017]      FIG. 2  is a schematic diagram showing an LCD device based on dual source drivers with data writing synchronous control mechanism in accordance with a first embodiment of the present invention. 
           [0018]      FIG. 3  is a diagram schematically showing the structure of the first source driver in  FIG. 2  in accordance with an embodiment of the present invention. 
           [0019]      FIG. 4  is a diagram schematically showing the structure of the second source driver in  FIG. 2  in accordance with an embodiment of the present invention. 
           [0020]      FIG. 5  is a timing diagram schematically showing the related signal waveforms concerning the operation of the LCD device in  FIG. 2 , having time along the abscissa. 
           [0021]      FIG. 6  is a schematic diagram showing an LCD device based on dual source drivers with data writing synchronous control mechanism in accordance with a second embodiment of the present invention. 
           [0022]      FIG. 7  is a diagram schematically showing the structure of the first source driver in  FIG. 6  in accordance with an embodiment of the present invention. 
           [0023]      FIG. 8  is a diagram schematically showing the structure of the second source driver in  FIG. 6  in accordance with an embodiment of the present invention. 
           [0024]      FIG. 9  is a timing diagram schematically showing the related signal waveforms concerning the operation of the LCD device in  FIG. 6 , having time along the abscissa. 
       
    
    
     DETAILED DESCRIPTION 
       [0025]    Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, it is to be noted that the present invention is not limited thereto. 
         [0026]      FIG. 2  is a schematic diagram showing an LCD device based on dual source drivers with data writing synchronous control mechanism in accordance with a first embodiment of the present invention. As shown in  FIG. 2 , the LCD device  200  comprises a gate driver  210 , a first source driver  220 , a second source driver  250 , a clock controller  280 , an LCD panel  290 , a plurality of gate lines GL 1 -GLm, and a plurality of data lines DL 1 -DLn. The clock controller  280  is utilized for generating a horizontal start signal HST and a horizontal clock signal HCK based on a master clock signal MCK, a horizontal synchronization signal HS, or a vertical synchronization signal VS. The first source driver  220  and the second source driver  250  are coupled to the clock controller  280  for receiving the horizontal start signal HST and the horizontal clock signal HCK. The LCD panel  290  comprises a plurality of pixel units  291 . Each pixel unit  291  is coupled to a corresponding gate line and a corresponding data line. 
         [0027]    The first source driver  220  comprises a first shift register module  225 , a first sampling latch module  230 , a first level shifter module  235 , a first digital-to-analog converter (DAC) module  240 , and a first data output buffer module  245 . The first shift register module  225  is utilized for generating a plurality of first control signals based on the horizontal start signal HST and the horizontal clock signal HCK. The first sampling latch module  230  is utilized for receiving the image data signal Sdata and latching the odd-order data signals of the image data signal Sdata based on the first control signals. 
         [0028]    Referring to  FIG. 3 , there is shown a schematic diagram of the first source driver in  FIG. 2  in accordance with an embodiment of the present invention. As shown in  FIG. 3 , the first shift register module  225  comprises a plurality of first shift registers SR_U 1 , SR_U 2 -SR_Un. The first sampling latch module  230  comprises a plurality of first latches SL_U 1 , SL_U 3 -SL_Un−1. The first level shifter module  235  comprises a plurality of first level shifters LS_U 1 , LS_U 3 -LS_Un−1. The first digital-to-analog converter module  240  comprises a plurality of first digital-to-analog converters DAC_UL, DAC_U 3 -DAC_Un−1. The first data output buffer module  245  comprises a plurality of first buffers Buf_U 1 , Buf_U 3 -Buf_Un−1. 
         [0029]    Each first shift register is utilized for generating a corresponding first control signal. Each first shift register having odd-order is coupled directly to a corresponding first latch for providing a corresponding first control signal to the corresponding first latch. For instance, the first shift register SR_U 1  having first-order is coupled directly to the first latch SL_U 1  for providing the first control signal Sen_U 1  to the first latch SL_U 1 , and the first shift register SR_U 3  having third-order is coupled directly to the first latch SL_U 3  for providing the first control signal Sen_U 3  to the first latch SL_U 3 . The first shift registers having even-order are not coupled directly to any first latch. That is, the plurality of first control signals Sen_U 2 , Sen_U 4 -Sen_Un generated by the first shift registers having even-order are not forwarded to any first latch. Therefore, the first sampling latch module  230  fetches only odd-order data signals of the received image data signal Sdata. It is noted that the number of the first latches is substantially only a half of the number of the first shift registers in the embodiment shown in  FIG. 3 . 
         [0030]    Each first level shifter is coupled to one corresponding first latch for performing a level shifting process on the corresponding odd-order data signal of the image data signal Sdata. Each first digital-to-analog converter is coupled to one corresponding first level shifter for performing a digital-to-analog converting process on the corresponding odd-order data signal of the image data signal Sdata. Each first buffer is coupled to one corresponding first digital-to-analog converter for performing a data output buffering process on the corresponding odd-order data signal of the image data signal Sdata. Also, each first buffer is coupled to one corresponding odd data line. For instance, the first buffer Buf_U 1  is coupled between the first digital-to-analog converter DAC_U 1  and the odd data line DL 1 , and the first buffer Buf_U 3  is coupled between the first digital-to-analog converter DAC_U 3  and the odd data line DL 3 . 
         [0031]    The second source driver  250  comprises a second shift register module  255 , a second sampling latch module  260 , a second level shifter module  265 , a second digital-to-analog converter module  270 , and a second data output buffer module  275 . The second shift register module  255  is utilized for generating a plurality of second control signals based on the horizontal start signal HST and the horizontal clock signal HCK. The second sampling latch module  260  is utilized for receiving the image data signal Sdata and latching the even-order data signals of the image data signal Sdata based on the second control signals. 
         [0032]    Referring to  FIG. 4 , there is shown a schematic diagram of the second source driver in  FIG. 2  in accordance with an embodiment of the present invention. As shown in  FIG. 4 , the second shift register module  255  comprises a plurality of second shift registers SR_D 1 , SR_D 2 -SR_Dn. The second sampling latch module  260  comprises a plurality of second latches SL_D 2 , SL_D 4 -SL_Dn. The second level shifter module  265  comprises a plurality of second level shifters LS_D 2 , LS_D 4 -LS_Dn. The second digital-to-analog converter module  270  comprises a plurality of second digital-to-analog converters DAC_D 2 , DAC_D 4 -DAC_Dn. The second data output buffer module  275  comprises a plurality of second buffers Buf_D 2 , Buf_D 4 -Buf_Dn. 
         [0033]    Each second shift register is utilized for generating a corresponding second control signal. Each second shift register having even-order is coupled directly to a corresponding second latch for providing a corresponding second control signal to the corresponding second latch. For instance, the second shift register SR_D 2  having second-order is coupled directly to the second latch SL_D 2  for providing the second control signal Sen_D 2  to the second latch SL_D 2 , and the second shift register SR_D 4  having fourth-order is coupled directly to the second latch SL_D 4  for providing the second control signal Sen_D 4  to the second latch SL_D 4 . The second shift registers having odd-order are not coupled directly to any second latch. That is, the plurality of second control signals Sen_D 1 , Sen_D 3 -Sen_Un−1 generated by the second shift registers having odd-order are not forwarded to any second latch. Therefore, the second sampling latch module  260  fetches only even-order data signals of the received image data signal Sdata. It is noted that the number of the second latches is substantially only a half of the number of the second shift registers in the embodiment shown in  FIG. 4 . 
         [0034]    Each second level shifter is coupled to one corresponding second latch for performing a level shifting process on the corresponding even-order data signal of the image data signal Sdata. Each second digital-to-analog converter is coupled to one corresponding second level shifter for performing a digital-to-analog converting process on the corresponding even-order data signal of the image data signal Sdata. Each second buffer is coupled to one corresponding second digital-to-analog converter for performing a data output buffering process on the corresponding even-order data signal of the image data signal Sdata. Also, each second buffer is coupled to one corresponding even data line. For instance, the second buffer Buf_D 2  is coupled between the second digital-to-analog converter DAC_D 2  and the even data line DL 2 , and the second buffer Buf_D 4  is coupled between the second digital-to-analog converter DAC_D 4  and the even data line DL 4 . 
         [0035]      FIG. 5  is a timing diagram schematically showing the related signal waveforms concerning the operation of the LCD device in  FIG. 2 , having time along the abscissa. The signal waveforms in  FIG. 5 , from top to bottom, are the master clock signal MCK, the image data signal Sdata, the horizontal start signal HST, the horizontal clock signal HCK, the plurality of first control signals, and the plurality of second control signals. The image data signal Sdata comprises a plurality of data signals D 1 , D 2 , D 3 , etc. After a start pulse of the horizontal start signal HST is furnished to both the first shift register module  225  and the second shift register module  255  during the time T 0 , the first control signals and the second control signals are sequentially enabled based on the horizontal clock signal HCK. Each enable period of the first and second control signals is corresponding to a half period of the horizontal clock signal HCK. 
         [0036]    For instance, the first shift register SR_U 1  and the second shift register SR_D 1  forward the enabled first control signal Sen_U 1  and the enabled second control signal Sen_D 1  respectively during the time T 1 , the first shift register SR_U 2  and the second shift register SR_D 2  forward the enabled first control signal Sen_U 2  and the enabled second control signal Sen_D 2  respectively during the time T 2 , the first shift register SR_U 3  and the second shift register SR_D 3  forward the enabled first control signal Sen_U 3  and the enabled second control signal Sen_D 3  respectively during the time T 3 , the first shift register SR_U 4  and the second shift register SR_D 4  forward the enabled first control signal Sen_U 4  and the enabled second control signal Sen_D 4  respectively during the time T 4 , and similar operations during other times can be inferred accordingly. 
         [0037]    Based on the aforementioned structure of the LCD device  200 , only the first shift registers having odd-order are coupled directly to the corresponding first latches, and therefore only the first control signals Sen_U 1 , Sen_U 3 -Sen_Un−1 generated by the first shift registers having odd-order can be forwarded to the corresponding first latches for performing data latching operations on the image data signal Sdata. That is, only odd-order data signals of the image data signal Sdata can be latched in the plurality of first latches SL_U 1 , SL_U 3 -SL_Un−1. Accordingly, as shown in  FIG. 5 , when the first control signals Sen_U 1  and Sen_U 3  are enabled during the times T 1  and T 3  respectively, the first latches SL_U 1  and SL_U 3  are able to latch the odd-order data signals D 1  and D 3  respectively. When the first control signals Sen_U 2  and Sen_U 4  are enabled during the times T 2  and T 4  respectively, the enabled first control signals Sen_U 2  and Sen_U 4  are not forwarded to any first latch for performing data latching operations. In other words, the enabled first control signals Sen_U 2  and Sen_U 4  are non-functional. 
         [0038]    After the odd-order data signals are latched, the plurality of first level shifters LS_U 1 , LS_U 3 -LS_Un−1 perform level shifting operations on the odd-order data signals, and the plurality of first digital-to-analog converters DAC_UL, DAC_U 3 -DAC_Un−1 perform digital-to-analog converting operations on the odd-order data signals for generating a plurality of first analog data signals. The first analog data signals are then forwarded to the odd data lines DL 1 , DL 3 -DLn−1 respectively via the first buffers Buf_U 1 , Buf_U 3 -Buf_Un−1 so that the first analog data signals can be written into corresponding pixel units  291 . 
         [0039]    Besides, only the second shift registers having even-order are coupled directly to the corresponding second latches, and therefore only the second control signals Sen_D 2 , Sen_D 4 -Sen_Dn generated by the second shift registers having even-order can be forwarded to the corresponding second latches for performing data latching operations on the image data signal Sdata. That is, only even-order data signals of the image data signal Sdata can be latched in the plurality of second latches SL_D 2 , SL_D 4 -SL_Dn. Accordingly, as shown in  FIG. 5 , when the second control signals Sen_D 2  and Sen_D 4  are enabled during the times T 2  and T 4  respectively, the second latches SL_D 2  and SL_D 4  are able to latch the even-order data signals D 2  and D 4  respectively. When the second control signals Sen_D 1  and Sen_D 3  are enabled during the times T 1  and T 3  respectively, the enabled second control signals Sen_D 1  and Sen_D 3  are not forwarded to any first latch for performing data latching operations. In other words, the enabled second control signals Sen_D 1  and Sen_D 3  are non-functional. 
         [0040]    After the even-order data signals are latched, the plurality of second level shifters LS_D 2 , LS_D 4 -LS_Dn perform level shifting operations on the even-order data signals, and the plurality of second digital-to-analog converters DAC_D 2 , DAC_D 4 -DAC_Dn perform digital-to-analog converting operations on the even-order data signals for generating a plurality of second analog data signals. The second analog data signals are then forwarded to the even data lines DL 2 , DL 4 -DLn respectively via the second buffers Buf_D 2 , Buf_D 4 -Buf_Dn so that the second analog data signals can be written into corresponding pixel units  291 . 
         [0041]    In summary, the costly data processing interface circuit is not required to be installed in the peripheral device area of the LCD device  200  of the present invention. That is, the input image data signal can be forwarded directly to both the first source driver  220  and the second source driver  250  for performing data writing operations without the aid of the data processing interface circuit. Accordingly, the LCD device  200  can be scaled down by reducing the peripheral device area, and furthermore the power consumption concerning the signal extracting and frequency down-converting processes can be put away in the operation of the LCD device  200 . 
         [0042]      FIG. 6  is a schematic diagram showing an LCD device based on dual source drivers with data writing synchronous control mechanism in accordance with a second embodiment of the present invention. As shown in  FIG. 6 , the LCD device  600  comprises a gate driver  610 , a first source driver  620 , a second source driver  650 , a clock controller  680 , an LCD panel  690 , a plurality of gate lines GL 1 -GLm, and a plurality of data lines DL 1 -DLn. The clock controller  680  is utilized for generating a first horizontal start signal HST 1 , a first horizontal clock signal HCK 1 , a second horizontal start signal HST 2 , and a second horizontal clock signal HCK 2  based on a master clock signal MCK, a horizontal synchronization signal HS, or a vertical synchronization signal VS. The first source driver  620  is coupled to the first and second output ends of the clock controller  680  for receiving the first horizontal start signal HST 1  and the first horizontal clock signal HCK 1  respectively. The second source driver  650  is coupled to the third and fourth output ends of the clock controller  680  for receiving the second horizontal start signal HST 2  and the second horizontal clock signal HCK 2  respectively. The LCD panel  690  comprises a plurality of pixel units  691 . Each pixel unit  691  is coupled to a corresponding gate line and a corresponding data line. 
         [0043]    The clock controller  680  comprises a first horizontal start signal generator  681  for generating the first horizontal start signal HST 1 , a first horizontal clock signal generator  683  for generating the first horizontal clock signal HCK 1 , a second horizontal start signal generator  685  for generating the second horizontal start signal HST 2 , and a second horizontal clock signal generator  687  for generating the second horizontal clock signal HCK 2 . The circuits of the first horizontal start signal generator  681 , the first horizontal clock signal generator  683 , the second horizontal start signal generator  685 , and the second horizontal clock signal generator  687  may be partly overlapped. 
         [0044]    The first source driver  620  comprises a first shift register module  625 , a first sampling latch module  630 , a first level shifter module  635 , a first digital-to-analog converter module  640 , and a first data output buffer module  645 . The first shift register module  625  is utilized for generating a plurality of first control signals based on the first horizontal start signal HST 1  and the first horizontal clock signal HCK 1 . The first sampling latch module  630  is utilized for receiving the image data signal Sdata and performing a data-overwrite latching process for latching the odd-order data signals of the image data signal Sdata based on the first control signals. 
         [0045]    Referring to  FIG. 7 , there is shown a schematic diagram of the first source driver in  FIG. 6  in accordance with an embodiment of the present invention. As shown in  FIG. 7 , the first shift register module  625  comprises a plurality of first shift registers SR_U 1 , SR_U 3 -SR_Un−1. The first sampling latch module  630  comprises a plurality of first latches SL_UL, SL_U 3 -SL_Un−1. The first level shifter module  635  comprises a plurality of first level shifters LS_UL, LS_U 3 -LS_Un−1. The first digital-to-analog converter  640  comprises a plurality of first digital-to-analog converters DAC_UL, DAC_U 3 -DAC_Un−1. The first data output buffer module  645  comprises a plurality of first buffers Buf_U 1 , Buf_U 3 -Buf_Un−1. 
         [0046]    Each first shift register is utilized for generating a corresponding first control signal. Each first shift register is coupled directly to a corresponding first latch for providing a corresponding first control signal to the corresponding first latch. For instance, the first shift register SR_U 1  is coupled directly to the first latch SL_U 1  for providing the first control signal Sen_U 1  to the first latch SL_U 1 , and the first shift register SR_U 3  is coupled directly to the first latch SL_U 3  for providing the first control signal Sen_U 3  to the first latch SL_U 3 . It is noted that the number of the first latches is substantially equal to the number of the first shift registers in the embodiment shown in  FIG. 7 . In the latching operation corresponding to each first latch of the first sampling latch module  630 , two consecutive data signals are sequentially latched during an enable period of the first control signal, and the firstly-latched data signal is overwritten by the secondly-latched data signal so that only the odd-order data signals of the image data signal Sdata are latched and the even-order data signals of the image data signal Sdata are overwritten. 
         [0047]    Each first level shifter is coupled to one corresponding first latch for performing a level shifting process on the corresponding odd-order data signal of the image data signal Sdata. Each first digital-to-analog converter is coupled to one corresponding first level shifter for performing a digital-to-analog converting process on the corresponding odd-order data signal of the image data signal Sdata. Each first buffer is coupled to one corresponding first digital-to-analog converter for performing a data output buffering process on the corresponding odd-order data signal of the image data signal Sdata. Also, each first buffer is coupled to one corresponding odd data line. For instance, the first buffer Buf_U 1  is coupled between the first digital-to-analog converter DAC_U 1  and the odd data line DL 1 , and the first buffer Buf_U 3  is coupled between the first digital-to-analog converter DAC_U 3  and the odd data line DL 3 . 
         [0048]    The second source driver  650  comprises a second shift register module  655 , a second sampling latch module  660 , a second level shifter module  665 , a second digital-to-analog converter module  670 , and a second data output buffer module  675 . The second shift register module  655  is utilized for generating a plurality of second control signals based on the second horizontal start signal HST 2  and the second horizontal clock signal HCK 2 . The second sampling latch module  660  is utilized for receiving the image data signal Sdata and performing a data-overwrite latching process for latching the even-order data signals of the image data signal Sdata based on the second control signals. 
         [0049]    Referring to  FIG. 8 , there is shown a schematic diagram of the second source driver in  FIG. 6  in accordance with an embodiment of the present invention. As shown in  FIG. 8 , the second shift register module  655  comprises a plurality of second shift registers SR_D 2 , SR_D 4 -SR_Dn. The second sampling latch module  660  comprises a plurality of second latches SL_D 2 , SL_D 4 -SL_Dn. The second level shifter module  665  comprises a plurality of second level shifters LS_D 2 , LS_D 4 -LS_Dn. The second digital-to-analog converter  670  comprises a plurality of second digital-to-analog converters DAC_D 2 , DAC_D 4 -DAC_Dn. The second data output buffer module  675  comprises a plurality of second buffers Buf_D 2 , Buf_D 4 -Buf_Dn. 
         [0050]    Each second shift register is utilized for generating a corresponding second control signal. Each second shift register is coupled directly to a corresponding second latch for providing a corresponding second control signal to the corresponding second latch. For instance, the second shift register SR_D 2  is coupled directly to the second latch SL_D 2  for providing the second control signal Sen_D 2  to the second latch SL_D 2 , and the second shift register SR_D 4  is coupled directly to the second latch SL_D 4  for providing the second control signal Sen_D 4  to the second latch SL_D 4 . It is noted that the number of the second latches is substantially equal to the number of the second shift registers in the embodiment shown in  FIG. 8 . In the latching operation corresponding to each second latch of the second sampling latch module  660 , two consecutive data signals are sequentially latched during an enable period of the second control signal, and the firstly-latched data signal is overwritten by the secondly-latched data signal so that only the even-order data signals of the image data signal Sdata are latched and the odd-order data signals of the image data signal Sdata are overwritten. 
         [0051]    Each second level shifter is coupled to one corresponding second latch for performing a level shifting process on the corresponding even-order data signal of the image data signal Sdata. Each second digital-to-analog converter is coupled to one corresponding second level shifter for performing a digital-to-analog converting process on the corresponding even-order data signal of the image data signal Sdata. Each second buffer is coupled to one corresponding second digital-to-analog converter for performing a data output buffering process on the corresponding even-order data signal of the image data signal Sdata. Also, each second buffer is coupled to one corresponding even data line. For instance, the second buffer Buf_D 2  is coupled between the second digital-to-analog converter DAC_D 2  and the even data line DL 2 , and the second buffer Buf_D 4  is coupled between the second digital-to-analog converter DAC_D 4  and the even data line DL 4 . 
         [0052]      FIG. 9  is a timing diagram schematically showing the related signal waveforms concerning the operation of the LCD device in  FIG. 6 , having time along the abscissa. The signal waveforms in  FIG. 9 , from top to bottom, are the master clock signal MCK, the image data signal Sdata, the first horizontal start signal HST 1 , the first horizontal clock signal HCK 1 , the plurality of first control signals, the second horizontal start signal HST 2 , the second horizontal clock signal HCK 2 , and the plurality of second control signals. The image data signal Sdata comprises a plurality of data signals D 1 , D 2 , D 3 , etc. After a start pulse of the first horizontal start signal HST 1  is furnished to the first shift register module  625  during the time T 10 , the first control signals are sequentially enabled based on the first horizontal clock signal HCK 1 . Each enable period of the first control signals is corresponding to a half period of the first horizontal clock signal HCK 1 . During each enable period of the first control signals, two consecutive data signals are sequentially latched, and the firstly-latched data signal is overwritten by the secondly-latched data signal so that only the odd-order data signals of the image data signal Sdata are latched and the even-order data signals of the image data signal Sdata are overwritten. 
         [0053]    For instance, when the first shift register SR_U 1  forwards the enabled first control signal Sen_U 1  to the first latch SL_U 1  during the time T 11 , the first latch SL_U 1  will sequentially latch the virtual data signal Dx and the odd-order data signal D 1 . Accordingly, the odd-order data signal D 1  is latched in the first latch SL_UL after the time T 11  in that the virtual data signal Dx is overwritten by the odd-order data signal D 1 . 
         [0054]    When the first shift register SR_U 3  forwards the enabled first control signal Sen_U 3  to the first latch SL_U 3  during the time T 12 , the first latch SL_U 3  will sequentially latch the even-order data signal D 2  and the odd-order data signal D 3 . Accordingly, the odd-order data signal D 3  is latched in the first latch SL_U 3  after the time T 12  in that the even-order data signal D 2  is overwritten by the odd-order data signal D 3 . 
         [0055]    When the first shift register SR_U 5  forwards the enabled first control signal Sen_U 5  to the first latch SL_U 5  during the time T 13 , the first latch SL_U 5  will sequentially latch the even-order data signal D 4  and the odd-order data signal D 5 . Accordingly, the odd-order data signal D 5  is latched in the first latch SL_U 5  after the time T 13  in that the even-order data signal D 4  is overwritten by the odd-order data signal D 5 . Other similar operations concerning other first latches during other times can be inferred accordingly. That is, only the odd-order data signals are latched in the plurality of first latches SL_U 1 , SL_U 3 -SL_Un−1. 
         [0056]    After the odd-order data signals are latched, the plurality of first level shifters LS_U 1 , LS_U 3 -LS_Un−1 perform level shifting operations on the odd-order data signals, and the plurality of first digital-to-analog converters DAC_UL, DAC_U 3 -DAC_Un−1 perform digital-to-analog converting operations on the odd-order data signals for generating a plurality of first analog data signals. The plurality of first analog data signals are then forwarded to the odd data lines DL 1 , DL 3 -DLn−1 respectively via the plurality of first buffers Buf_U 1 , Buf_U 3 -Buf_Un−1 so that the plurality of first analog data signals can be written into corresponding pixel units  691 . 
         [0057]    After a start pulse of the second horizontal start signal HST 2  is furnished to the second shift register module  655  during the time T 20 , the plurality of second control signals are sequentially enabled based on the second horizontal clock signal HCK 2 . Each enable period of the second control signals is corresponding to a half period of the second horizontal clock signal HCK 2 . During each enable period of the second control signals, two consecutive data signals are sequentially latched, and the firstly-latched data signal is overwritten by the secondly-latched data signal so that only the even-order data signals of the image data signal Sdata are latched and the odd-order data signals of the image data signal Sdata are overwritten. 
         [0058]    For instance, when the second shift register SR_D 2  forwards the enabled second control signal Sen_D 2  to the second latch SL_D 2  during the time T 21 , the second latch SL_D 2  will sequentially latch the odd-order data signal D 1  and the even-order data signal D 2 . Accordingly, the even-order data signal D 2  is latched in the second latch SL_D 2  after the time T 21  in that the odd-order data signal D 1  is overwritten by the even-order data signal D 2 . 
         [0059]    When the second shift register SR_D 4  forwards the enabled second control signal Sen_D 4  to the second latch SL_D 4  during the time T 22 , the second latch SL_D 4  will sequentially latch the odd-order data signal D 3  and the even-order data signal D 4 . Accordingly, the even-order data signal D 4  is latched in the second latch SL_D 4  after the time T 22  in that the odd-order data signal D 3  is overwritten by the even-order data signal D 4 . 
         [0060]    When the second shift register SR_D 6  forwards the enabled second control signal Sen_D 6  to the second latch SL_D 6  during the time T 23 , the second latch SL_D 6  will sequentially latch the odd-order data signal D 5  and the even-order data signal D 6 . Accordingly, the even-order data signal D 6  is latched in the second latch SL_D 6  after the time T 23  in that the odd-order data signal D 5  is overwritten by the even-order data signal D 6 . Other similar operations concerning other second latches during other times can be inferred accordingly. That is, only the even-order data signals are latched in the plurality of second latches SL_D 2 , SL_D 4 -SL_Dn. 
         [0061]    After the even-order data signals are latched, the plurality of second level shifters LS_D 2 , LS_D 4 -LS_Dn perform level shifting operations on the even-order data signals, and the plurality of second digital-to-analog converters DAC_D 2 , DAC_D 4 -DAC_Dn perform digital-to-analog converting operations on the even-order data signals for generating a plurality of second analog data signals. The plurality of second analog data signals are then forwarded to the even data lines DL 2 , DL 4 -DLn respectively via the plurality of second buffers Buf_D 2 , Buf_D 4 -Buf_Dn so that the plurality of second analog data signals can be written into corresponding pixel units  691 . 
         [0062]    In summary, the costly data processing interface circuit is not required to be installed in the peripheral device area of the LCD device  600  of the present invention. That is, the input image data signal can be forwarded directly to both the first source driver  620  and the second source driver  650  for performing data writing operations without the aid of the data processing interface circuit. Accordingly, the LCD device  600  can be scaled down by reducing the peripheral device area, and furthermore the power consumption concerning the signal extracting and frequency down-converting processes can be put away in the operation of the LCD device  600 . 
         [0063]    The present invention is by no means limited to the embodiments as described above by referring to the accompanying drawings, which may be modified and altered in a variety of different ways without departing from the scope of the present invention. Thus, it should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alternations might occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.