Abstract:
A voltage-controlled oscillator (VCO) circuit includes first, second, third, and fourth transistors, wherein said third and fourth transistors bias the second and first transistors, respectively. First and second capacitances communicate with the first, second, third, and fourth transistors. A first input receives a first capacitance adjustment signal. At least one second input receives a second capacitance adjustment signal. The first capacitance has a first end connected to he first input and the third transistor. The second capacitance has a first end connected to the second input and the fourth transistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. Ser. No. 10/747,521, filed Dec. 29, 2003, now U.S. Pat. No. 7,190,232, issued Mar. 13, 2007, which application claims the benefit of U.S. Provisional Application No. 60/470,689, filed on May 14, 2003. The disclosures of the above applications are incorporated herein by reference. 

   FIELD OF THE INVENTION 
   The present invention relates to oscillator circuits, and more particularly to voltage-controlled oscillator circuits. 
   BACKGROUND OF THE INVENTION 
   Oscillator circuits produce an output that varies periodically at a predetermined frequency. Oscillator circuits typically operate based on positive feedback. In a voltage-controlled oscillator (VCO), the principle tuning element is a varactor diode. The VCO is tuned across a frequency band by applying a DC voltage to the varactor diode, which varies the net capacitance of a tuned circuit. 
   VCOs may be implemented in frequency synthesizers such as phase-locked loops (PLLs). The PLLs, in turn, may be implemented in a device such as a wireless communications device. In wireless communications devices, the VCO provides a clock signal that is used by a transceiver during a frequency up-conversion and a down-conversion process. The clock signal ideally has no phase noise, which creates frequency fluctuations in the output signal. When the PLL is locked, the VCO may contribute noise at higher frequencies. 
   Referring to  FIG. 1 , an exemplary PLL  10  includes a phase detector  12 , a charge pump  14 , a filter  16 , a VCO  18 , and a divider  20 . The phase detector  12  receives a reference frequency signal  22 . For example, a crystal oscillator may be used to provide the reference frequency signal  22 . The phase detector  12  also receives an output signal  24  from the divider  20 . The phase detector  12  compares the reference frequency signal  22  and the divider output signal  24  and generates a phase error signal  26 . The phase error signal  26  is a measure of the phase difference between the reference frequency signal  22  and the divider output signal  24 . Typically, the phase error signal  26  is a DC voltage that is output to the charge pump  14 , which converts the value of the phase error signal  26  into an absolute DC voltage or a VCO voltage signal  28 . 
   Because the VCO  18  is sensitive to fluctuations in the VCO voltage signal  28 , the filter  16  filters the VCO voltage signal  28  from the charge pump  14 . The VCO  18  generates an output signal  32  at a desired frequency based on the value of the filtered VCO voltage signal  30 . 
   The divider  20  receives the output of the VCO  32 . Since the desired value for the output frequency of the VCO  18  is generally different than the reference frequency, the divider  20  is used to adjust the value of the output signal  32  based on the ratio of the desired output frequency to the reference frequency. Based on the feedback from the VCO  18 , the PLL  10  locks the output signal  32  onto the reference frequency signal  22  and maintains a fixed relationship. 
   Referring now to  FIG. 2 , a first VCO circuit  40  includes first and second transistors  42  and  44 , respectively. For example, the first and second transistors  42  and  44 , respectively, may be bi-polar junction transistors (BJTs) that have bases, collectors, and emitters. However, other types of transistors may be used. An emitter (or terminal) of the first transistor  42  communicates with an emitter of the second transistor  44 . The first VCO circuit  40  also includes first and second capacitors  46  and  48 , respectively, that AC couple positive feedback of the first and second transistors  42  and  44 , respectively. A first end of the first capacitor  46  communicates with a collector (or terminal) of the first transistor  42  and a second end of the first capacitor  46  communicates with a base (or control terminal) of the second transistor  44 . A first end of the second capacitor  48  communicates with a collector of the second transistor  44  and a second end of the second capacitor  48  communicates with a base of the first transistor  42 . The emitters of the first and second transistors  42  and  44 , respectively, communicate with a first current source  50 . 
   A net capacitance of the first VCO circuit  40  determines a frequency of an output signal. A control voltage signal  52  is applied to cathodes of first and second varactor diodes  54  and  56 , respectively, to adjust the net capacitance of the first VCO circuit  40 . For example, a charge pump may generate the control voltage signal  52  in a PLL. An anode of the first varactor diode  54  communicates with the collector of the first transistor  42 , and an anode of the second varactor diode  56  communicates with the collector of the second transistor  44 . A cathode of the first varactor diode  54  communicates with a cathode of the second varactor diode  56 . 
   The first VCO circuit  40  that is illustrated in  FIG. 2  is an LC-tank VCO that includes first and second inductors  58  and  60 , respectively, at an output  62 . A first end of the first inductor  58  communicates with the collector of the second transistor  44 . A first end of the second inductor  60  communicates with the collector of the second transistor  44 . The output signal  32  is referenced from second ends of the first and second inductors  58  and  60 , respectively. 
   A DC signal may degrade when the VCO circuit includes coupling capacitors. Also, if the signal is directly coupled, the collector and base of the first and second transistors  42  and  44 , respectively, will be at the same voltage. If the voltage is very low, this may drive the first and second transistors  42  and  44 , respectively, into saturation. It is desirable to maintain the voltage at the collectors of the first and second transistors  42  and  44 , respectively, relatively high with respect to the voltage at the bases of the first and second transistors  42  and  44 , respectively. Therefore, a separate bias voltage signal  64  biases the bases of the first and second transistors  42  and  44 , respectively through first and second resistors  66  and  68 , respectively. 
   Beta values of the first and second transistors  42  and  44 , respectively, may vary. This causes a difference in current through the first and second resistors  66  and  68 , respectively, which leads to a difference in transconductance between the first and second transistors  42  and  44 , respectively. Additionally, the bias voltage signal  64  is separately generated. The bias voltage signal  64  as well as the first and second resistors  66  and  68 , respectively, contribute noise to the first VCO circuit  40 . 
   Referring now to  FIG. 3 , a second VCO circuit  70  includes third and fourth transistors  72  and  74 , respectively, that couple the positive feedback of the first and second transistors  42  and  44 , respectively. For example, the third and fourth transistors  72  and  74 , respectively, may be BJTs that operate as emitter followers, although other types of transistors may be used. An emitter of the third transistor  72  communicates with the base of the second transistor  44 . A base of the third transistor  72  communicates with the collector of the first transistor  42 . An emitter of the fourth transistor  74  communicates with the base of the first transistor  42 . A base of the fourth transistor  74  communicates with the collector of the second transistor  44 . A supply potential  76  is applied to collectors of the third and fourth transistors  72  and  74 , respectively. 
   Current that flows through the third and fourth transistors  72  and  74 , respectively, is sufficient to drive the bases of the first and second transistors  42  and  44 , respectively. Therefore, the base of the third transistor  72  communicates with a second current source  78 . The emitter of the third transistor  72  communicates with a third current source  80 . The second VCO circuit  70  generates less noise than the first VCO circuit  40 . The positive feedback of the second VCO circuit  70  does not have to be AC coupled. However, at high frequencies, the amount of current that the second VCO circuit  70  requires to reduce second harmonic distortion is very high. 
   SUMMARY OF THE INVENTION 
   A voltage-controlled oscillator (VCO) circuit includes first, second, third, and fourth transistors, each with a first terminal, a second terminal, and a control terminal. The first terminal of the first transistor communicates with the first terminal of the second transistor. The control terminals of the third and fourth transistors communicate with the second terminals of the first and second transistors, respectively. The first terminals of the third and fourth transistors communicate with the control terminals of the first and second transistors, respectively. First ends of first and second capacitances communicate with the second terminals of the first and second transistors, respectively. Second ends of the first and second capacitances communicate with the control terminals of the first and second transistors, respectively. 
   In other features, anodes of first and second varactor diodes communicate with the control terminals of the third and fourth transistors, respectively. A cathode of the first varactor diode communicates with a cathode of the second varactor diode. A control voltage that is applied to the cathode of the first varactor diode adjusts a net capacitance of the VCO circuit. The net capacitance determines an output frequency of the VCO circuit. 
   In other features, a phase lock loop circuit comprises the VCO circuit and further comprises a charge pump that generates the control voltage. 
   In other features, first ends of the first and second inductances communicate with the control terminals of the third and fourth transistors. An output signal of the VCO circuit is referenced from second ends of the first and second inductances. 
   In other features, the second terminals of the third and fourth transistors communicate with a supply potential. The first terminals of the first and second transistors communicate with a first current source. The control terminal of the first transistor communicates with a second current source. The control terminal of the second transistor communicates with a third current source. The first, second, and third current sources communicate with a ground potential. 
   In other features, a capacitance adjustment circuit communicates with the VCO circuit and generates a capacitance adjustment control signal. The capacitance adjustment control signal adjusts a net capacitance of the VCO circuit. First and second output terminals of the capacitance adjustment circuit communicate with the second terminals of the first and second transistors, respectively. 
   An output buffer buffers the output signal and adjusts an output impedance of the system. The first, second, third, and fourth transistors are bi-polar junction transistors. The VCO circuit is implemented in a wireless network device that is compliant with at least one of IEEE sections 802.11, 802.11a, 802.11b, 802.11g, 802.11n, and 802.16. 
   Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
       FIG. 1  is a functional block diagram of an exemplary phase-locked loop that includes a voltage-controlled oscillator (VCO) according to the prior art; 
       FIG. 2  is a schematic of a first VCO circuit that includes AC coupling capacitors and a bias voltage according to the prior art; 
       FIG. 3  is a schematic of a second VCO circuit that includes emitter follower transistors to couple positive feedback according to the prior art; 
       FIG. 4  is a functional block diagram of a VCO system that includes a capacitance adjustment circuit and an output buffer according to the present invention; 
       FIG. 5  is a schematic of a VCO circuit that includes coupling capacitors and emitter follower transistors according to the present invention; and 
       FIG. 6  is a functional block diagram of the VCO implemented in a wireless network device. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. 
   Referring now to  FIG. 4 , a voltage-controlled oscillator (VCO) system  88  according to the present invention includes a VCO circuit  90 , a capacitance adjustment circuit  92 , and an output buffer  94 . The VCO system  88  of  FIG. 4  provides two ways to adjust a net capacitance of the VCO circuit  90 , which determines a frequency of an output signal of the VCO circuit  90 . A control voltage signal  96  that is applied to the VCO circuit  90  adjusts the net capacitance. For example, a charge pump of a phase-locked loop may generate the control voltage signal  96 . 
   The capacitance adjustment circuit  92  also adjusts the net capacitance of the VCO circuit  90 . The control voltage signal  96  finely tunes the net capacitance and the capacitance adjustment circuit  92  coarsely tunes the net capacitance. The capacitance adjustment circuit  92  may be implemented by a plurality of capacitances and/or capacitors that can be added in series and/or parallel using one or more switches such as transistors. The output buffer  94  buffers the output signal of the VCO circuit  90  and adjusts an output impedance of the VCO system  88  to prevent loading effects. The VCO system  88  also includes an amplitude correction circuit  98  that maintains a fixed range of current that is delivered to the VCO circuit  90 . 
   Referring now to  FIG. 5 , the VCO circuit  90  includes first and second transistors  104  and  106 , respectively. For example, the first and second transistors  104  and  106 , respectively, may be bi-polar junction transistors (BJTs) that have collectors, emitters, and bases, and that have a negative transconductance. An emitter of the first transistor  104  communicates with an emitter of the second transistor  106 . First and second capacitors  108  and  110 , respectively, AC couple the positive feedback. A first end of the first capacitor  108  communicates with a collector of the first transistor  104 . A second end of the first capacitor  108  communicates with a base of the second transistor  106 . A first end of the second capacitor  110  communicates with a collector of the second transistor  106 . A second end of the second capacitor  110  communicates with a base of the first transistor  104 . 
   Third and fourth transistors  112  and  114 , respectively, provide biasing for the first and second transistors  104  and  106 , respectively. For example, the third and fourth transistors  112  and  114 , respectively, may be BJTs that operate as emitter followers. An emitter of the third transistor  112  communicates with the base of the second transistor  106 . A base of the third transistor  112  communicates with a collector of the first transistor  104 . An emitter of the fourth transistor  114  communicates with a base of the first transistor  104 . A base of the fourth transistor  114  communicates with the collector of the second transistor  106 . 
   The second terminals of the third and fourth transistors  112  and  114 , respectively, communicate with a supply potential  116 . The control voltage signal  96  is applied to first and second varactor diodes  118  and  120 , respectively. An anode of the first varactor diode  118  communicates with the base of the third transistor  112 . An anode of the second varactor diode  120  communicates with the base of the fourth transistor  114 . A cathode of the first varactor diode  118  communicates with a cathode of the second varactor diode  120 . The control voltage signal  96  is applied to the cathodes of the first and second varactor diodes  118  and  120 , respectively. 
   First and second inductors  122  and  124 , respectively, form an output  126  of the VCO circuit  90 . A first end of the first inductor  122  communicates with the base of the third transistor  112 . A first end of the second inductor  124  communicates with the base of the fourth transistor  114 . An output signal of the VCO circuit  90  is referenced from second ends of the first and second inductors  122  and  124 , respectively. The emitters of the first and second transistors  104  and  106 , respectively, communicate with a first current source  128 . The base of the first transistor  104  communicates with a second current source  130 , and the base of the second transistor  106  communicates with a third current source  132 . The first, second, and third current sources  128 ,  130 , and  132 , respectively, communicate with a ground potential  136 . 
   The second and third current sources  130  and  132 , respectively, bias the third and fourth transistors  112  and  114 , respectively, with a relatively low current. Since the amount of current is small, the bandwidth of the third and fourth transistors  112  and  114 , respectively, is typically too low. Therefore, the first and second capacitors  108  and  110 , respectively, communicate in parallel with the third and fourth transistors  112  and  114 , respectively, and AC couple the signals of the third and fourth transistors  112  and  114 , respectively, to the remainder of the VCO circuit  90 . This allows the signals of the third and fourth transistors  112  and  114 , respectively, to be coupled without requiring a large current through the third and fourth transistors  112  and  114 , respectively. The capacitance adjustment circuit  92  communicates with the VCO circuit  90  at the bases of the third and fourth transistors  112  and  114 , respectively, through a capacitance adjustment control signal  134 . Both the control voltage signal  96  and the capacitance adjustment control signal  134  adjust a net capacitance of the VCO circuit  90 . The net capacitance varies a frequency of the output signal. 
   The VCO circuit  90  may be categorized into three sections: an inductance section, a capacitance section, and a negative transconductance section. The inductance section includes the first and second inductors  122  and  124 , respectively. The capacitance section includes the capacitance adjustment control signal  134  and the control voltage signal  96 . The negative transconductance section includes the first and second transistors  104  and  106 , respectively, which are preferably cross-coupled BJTs. 
   It is desirable for the VCO circuit  90  to function with as little phase noise as possible. Phase noise may cause frequency fluctuations in the output signal. Therefore, a phase noise requirement of a transceiver and/or a PLL may determine a maximum allowable phase noise for satisfactory operation. For example, a maximum phase noise requirement may be set to −93 dBc/Hz at 100 kHz offset from the frequency of oscillation. 
   Specific parameters of components in the VCO circuit  90  have a significant effect on phase noise. These parameters include shot noise of the first and second transistors  104  and  106 , respectively, base resistance of the first and second transistors  104  and  106 , respectively, and series resistance of the first and second inductors  122  and  124 , respectively. The shot noise of the first and second transistors  104  and  106 , respectively, is a function of input current and temperature. Otherwise, the VCO circuit  90  is biased in an appropriate region of operation to reduce phase noise contribution from the other components. 
   The VCO circuit  90  of the present invention is an improvement over conventional VCO circuit designs. The third and fourth transistors  112  and  114 , when operating as emitter followers, allow the biasing point to be set with very little current. Also, high frequency signals are coupled by the first and second capacitors  108  and  110 , respectively. A separate bias voltage signal that is required by conventional VCO circuits with coupling capacitors is no longer needed. Additionally, second harmonic distortion that is associated with conventional VCO circuits that include emitter followers is eliminated. While  FIG. 1  illustrates a VCO circuit as part of a PLL device, those skilled in the art can appreciate that the VCO circuit  90  of the present invention is applicable to other devices. 
   Referring now to  FIG. 6 , the VCO  90  according to the present invention is implemented in a PLL circuit  148  of a wireless network device  150 . The wireless network device  150  is compliant with IEEE sections 802.11, 802.11a, 802.11b, 802.11g, 802.11n, 802.16, and/or other existing or future wireless standards. IEEE sections 802.11, 802.11a, 802.11b, 802.11g, 802.11n, 802.16 are hereby incorporated by reference in their entirety. 
   Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and the following claims.