Abstract:
A method for improving the mobility of holes and electrons within a structure comprising the following steps. A structure having at least an adjacent NMOS device and PMOS device is provided. A first stress layer is formed over the PMOS device and a second stress layer is formed over the NMOS device whereby the mobility of holes and electrons within the structure is improved. A semiconductor device comprising: at least one NMOS device; at least one PMOS device adjacent the at least one NMOS device; a first stress layer overlying the at least one PMOS device with the first stress layer having a first stress characteristic; and a second stress layer overlying the at least one NMOS device with the second stress layer having a second stress characteristic.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates generally to semiconductor fabrication and more specifically to metal-oxide semiconductor (MOS) devices/complimentary MOS (CMOS) devices and methods of forming the same.  
         BACKGROUND OF THE INVENTION  
         [0002]    Mechanical stress control in the channel regions of metal-oxide semiconductor field-effect transistors (MOSFETs) enables overcoming the limitations incurred in the scaling down of devices.  
           [0003]    U.S. Pat. No. 6,284,610 B1 to Cha et al. describes a poly layer to reduce stress.  
           [0004]    U.S. Pat. No. 6,281,532 B1 to Doyle et al. describes processes to change the localized stress.  
           [0005]    U.S. Pat. No. 5,562,770 to Chen et al. describes a process for global stress modification by forming layers or removing layers from over a substrate.  
           [0006]    U.S. Pat. No. 5,834,363 to Masanori describes a method for global stress modification by forming layers from over a substrate.  
           [0007]    The J. Welser et al.  Strain Dependence of the Performance Enhancement in Strained - Si n - MOSFETs , IEDM Tech. Dig., pp. 373- 376, 1994 article discloses measurements of the strain dependence of the electron mobility enhancements in n-MOSFETs employing tensilely-strained Si channels.  
           [0008]    The K. Rim et al.  Strained Si NMOSFET&#39;s for High Performance CMOS Technology , VLSI Tech., pp. 59 and 60, 2001 article describes performance enhancements in strained Si NMOSFET&#39;s at L eff &lt;70 nm.  
           [0009]    The F. Ootsuka et al.  A Highly Dense, High - Performance  130  nm node CMOS Technology for Large Scale System - on - a - Chip Applications , IEDM Tech. Dig., pp. 575-578, 2000 article describes a 130 nm node CMOS technology with a self-aligned contact system.  
           [0010]    The Shinya Ito et al.  Mechanical Stress Effect of Etch - Stop Nitride and its Impact on Deep Submicron Transistor Design , IEDM Tech, Dig.; pp. 247-250, 2000 article describes process-induced mechanical stress affecting the performance of short-channel CMOSFET&#39;s.  
           [0011]    The A. Shimizu et al.  Local Mechanical - Stress Control  (LMC) : A New Technique for CMOS - Performance Enhancement , IEDM Tech. Dig., pp. 433-436, 2001 article describes a “local mechanical-stress control” (LMC) technique used to enhance the CMOS current drivability.  
         SUMMARY OF THE INVENTION  
         [0012]    Accordingly, it is an object of one or more embodiments of the present invention to provide a MOS/CMOS device having different stresses on at least two different areas, and methods of fabricating the same.  
           [0013]    Other objects will appear hereinafter.  
           [0014]    It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having at least an adjacent NMOS device and PMOS device is provided. A first stress layer is formed over the PMOS device and a second stress layer is formed over the NMOS device whereby the mobility of holes and electrons within the structure is improved. A semiconductor device comprising: at least one NMOS device; at least one PMOS device adjacent the at least one NMOS device; a first stress layer overlying the at least one PMOS device with the first stress layer having a first stress characteristic; and a second stress layer overlying the at least one NMOS device with the second stress layer having a second stress characteristic.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:  
         [0016]    FIGS.  1  to  5  schematically illustrate a preferred embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0017]    Information Known to the Inventors—Not to be Considered Prior Art  
         [0018]    The following information is known to the inventors and is not to be necessarily considered prior art for the purposes of this invention.  
         [0019]    Changing the Si lattice spacing to a value other than the equilibrium value by using mechanical stress can increase the mobility of holes and electrons. This has been demonstrated in a strained-silicon (Si) MOSFET which applied high biaxial tensile stress to the channel of MOSFETs. However, the fabrication of strained-Si MOSFETs involves complicated processes such as forming a relaxed SiGe buffer layer. A recent study has shown that mechanical stress from a contact etch stop silicon nitride (SiN) layer affects the drive current.  
         [0020]    Initial Structure—FIG. 1 As shown in FIG. 1, the preferred structure of the present embodiment includes a structure  10  that preferably includes (1) at least one NMOS region  12  having at least one NMOS (N-type MOS) device  16  formed therein and (2) at least one PMOS region  14  having at least one PMOS (P-type MOS) device  18  formed therein.  
         [0021]    An isolation device  11  may be formed within structure  10  between adjacent NMOS/PMOS devices  16 ,  18 . Structure  10  may be a silicon substrate or a silicon-germanium substrate, for example, and isolation device  11  may be, for example, a shallow trench isolation (STI) device.  
         [0022]    The NMOS devices(s)  16  comprise a respective electrode  20  and sidewall spacers  22 , source/drain (S/D) implants (not shown) and a gate oxide layer  21 . The PMOS devices(s)  18  comprise a respective electrode  30  and sidewall spacers  32 , source/drain (S/D) implants (not shown) and a gate oxide layer  31 . The respective gate oxide layers  21 ,  31  each have a thickness of preferably from about 6 to 100 Å and more preferably less than about 17 Å.  
         [0023]    An NMOS device channel and a PMOS device channel may be formed (not shown). The respective device channels each have a design width of preferably from about 0.05 to 10.0 μm, more preferably less than about 10.0 μm and most preferably less than about 0.5 μm.  
         [0024]    The operation voltage design is preferably from about 0.6 to 3.3 volts (V) and is more preferably less than about 1.2 V.  
         [0025]    Structure  10  is preferably a silicon substrate or a germanium substrate, is more preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate.  
         [0026]    A first stress layer  40  is formed over structure  10 , NMOS devices(s)  16  and PMOS device(s)  18  to a thickness of preferably from about 200 to 700 Å. First stress layer  40  may be either a tensile-stress layer or a compression-stress layer as described below.  
         [0027]    An etch stop layer  42  is formed over the first stress layer  40  to a thickness of preferably from about 200 to 700 Å and more preferably from about 250 to 500 Å. Etch stop layer  42  is preferably comprised of oxide, silicon oxide (SiO 2 ) or SiON and is more preferably comprised of oxide or silicon oxide.  
         [0028]    A first patterning layer  46  is formed at least over either the NMOS device  16  and adjacent thereto or, as shown in FIG. 1, the PMOS device  18  and adjacent thereto, to permit patterning of the etch stop layer 42  and the first stress layer  40 . First patterning layer  46  is preferably comprised of photoresist, or a hardmask and more preferably photoresist as shown in FIGS. 1 and 2. Etch stop layer  42  may also be patterned by selective etching without using a first patterning layer  46 .  
         [0029]    Patterning of the Etch Stop Layer  42  and the First Stress layer  40 —FIG. 2  
         [0030]    As shown in FIG. 2, preferably using first patterning layer  46  as a mask, the etch stop layer  42  and the first stress layer  40  are patterned to leave a patterned etch stop layer  42 ′ and a patterned first stress layer  40 ′ each at least overlying the PMOS device  18  and adjacent thereto within PMOS area  14 , leaving the NMOS device  16  within NMOS area  12  exposed.  
         [0031]    As one skilled in the art would understand now or hereafter, the first patterning layer  46  may not necessarily be needed to pattern the etch stop layer  42  and the first stress layer  40  as long as the etch stop layer  42  and the first stress layer  40  are patterned/etched as shown in FIG. 2.  
         [0032]    Formation of Second Stress layer  50 —FIG. 3  
         [0033]    As shown in FIG. 3, the first patterning layer  46  (if used) is removed and the structure is cleaned as necessary.  
         [0034]    A second stress layer  50  is formed over structure  10 , NMOS device  16  and over patterned etch stop layer  42 ′ that overlies at least PMOS device  18  and adjacent thereto to a thickness of preferably from about 200 to 700 Å. Second stress layer  50  is (1) a tensile-stress layer if the patterned first stress layer  40 ′ is comprised of a tensile-stress layer and is a (2) a tensile-stress layer is the patterned first stress layer  40 ′ is comprised of a compression-stress layer.  
         [0035]    As shown in FIG. 3, a second patterning layer  48  is formed at least over the NMOS device  16  (if the first patterning layer  46  was formed over the PMOS device  18 ) and adjacent thereto to permit patterning of the second stress layer  50 . Second patterning layer  48  is preferably comprised of photoresist or a hardmask and more preferably photoresist as shown in FIGS. 3 and 4. Second stress layer  50  may also be patterned by selective etching without using a first patterning layer  48 .  
         [0036]    Patterning of the Second Stress Layer  50 —FIG. 4  
         [0037]    As shown in FIG. 4, preferably using second patterning layer  48  as a mask: (1) the second stress layer  50  is patterned to leave a patterned second stress layer  50 ′ at least overlying the NMOS device  16  and adjacent thereto within NMOS area  12 ; and (2) the patterned etch stop layer  42 ′ is etched and removed leaving the patterned first stress layer  40 ′ overlying at least the PMOS device  18  and adjacent thereto within PMOS area  14  exposed.  
         [0038]    As one skilled in the art would understand now or hereafter, the second patterning layer  48  may not necessarily be needed to pattern the second stress layer  50  et al. as long as the second stress layer  50  et al. are patterned/etched as shown in FIG. 4.  
         [0039]    Removal of the Second Patterning Layer  48 —FIG. 5  
         [0040]    As shown in FIG. 5, the second patterning layer  48  (if used) is removed and the structure is cleaned as necessary.  
         [0041]    Formation of Tensile-Stress Layers and Compression-Stress Layers  
         [0042]    As noted above, the first stress layer  40  may be either a tensile-stress layer or a compression-stress layer while the second stress layer  50  is a tensile-stress layer. That is, if the first stress layer  40  is a tensile-stress layer then the second stress layer  50  is a tensile-stress layer, and if the first stress layer  40  is a compression-stress layer then the second stress layer  50  is a tensile-stress layer as illustrated by the following table:  
                                                                     Case 1   Case 2                                        First Stress layer 40′   tensile-stress   compression-stress           Second Stress layer 50′   tensile-stress   tensile-stress                      
 
         [0043]    The tensile-stress layer, be it first stress layer  40  or second stress layer  50 , is preferably comprised of silicon nitride (Si 3 N 4  or just SiN), silicon oxynitride (SiON), oxide or Si-rich nitride, is more preferably SiN or SiON and is most preferably SiON and has a thickness of preferably from about 200 to 1000 Å and more preferably from about 250 to 500 Å. The tensile-stress layer is preferably deposited by rapid thermal chemical vapor deposition (RTCVD) under the following conditions:  
         [0044]    temperature: preferably from about 350 to 800° C. and more preferably from about 400 to 700° C.;  
         [0045]    time: preferably from about 10 to 2000 seconds and more preferably from about 20 to 120 seconds;  
         [0046]    NH 3 :SiH 4  gas ratio: preferably from about 50:1 to 400:1 and more preferably less than about 700:1; or di-saline:NH 3  gas ratio: preferably from about 1:40 to 1:500 and more preferably less than about 1:1; and  
         [0047]    deposition pressure: preferably from about 10 to 400 Torr and more preferably less than about 300 Torr.  
         [0048]    The compression-stress layer, which may be first stress layer  40 , is preferably comprised of silicon nitride (Si 3 N 4  or just SiN), silicon oxynitride (SiON), oxide or Si-rich nitride, is more preferably SiN or SiON and is most preferably SiON and has a thickness of preferably from about 200 to 1000 Å and more preferably from about 250 to 500 Å. The compression-stress layer is preferably deposited by plasma enhanced chemical vapor deposition (PECVD) under the following conditions:  
         [0049]    temperature: preferably from about 300 to 600° C. and more preferably less than about 600° C.;  
         [0050]    time: preferably from about 10 to 500 seconds and more preferably from about 20 to 120 seconds;  
         [0051]    NH 3 :SiH 4  gas ratio: preferably from about 4:1 to 10:1 and more preferably less than about 8:1; or di-saline:NH 3  gas ratio: preferably from about 1 :4 to 1:10 and more preferably less than about 1:1;  
         [0052]    deposition pressure: preferably from about 1.0 to 1.5 Torr and more preferably less than about 1.5 Torr; and  
         [0053]    total power: preferably from about 1000 to 2000 watts (W) and more preferably greater than about 1000 W.  
         [0054]    The different stresses achieved by using either a first tensile-stress layer  40 ′/second compression-stress layer  50 ′ combination or a first compression-stress layer  40 ′/second tensile-stress layer  50 ′ combination in accordance with the teachings of the present invention increases the mobility of holes and electrons.  
         [0055]    Advantages of the Present Invention  
         [0056]    The advantages of one or more embodiments of the present invention include:  
         [0057]    1. using a specific tensile film to improve N, PMOS; and  
         [0058]    3. provide a method to attain PMOS on compressive stress and NMOD on tensile stress to improve N, PMOS device performance.  
         [0059]    While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.