Abstract:
The present invention relates to a processor including at least one memory access unit for presenting a read or write address over an address bus of a memory in response to the execution of a read or write instruction; and an arithmetic and logic unit operating in parallel with the memory access unit and arranged at least to present data on the data bus of the memory while the memory access unit presents a write address. The processor includes a write address queue in which is stored each write address provided by the memory access unit waiting for the availability of the data to be written.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a digital signal processor (DSP), and more specifically to an architecture that avoids problems resulting from memory latency. 
     2. Discussion of the Related Art 
     FIG. 1 schematically and partially shows a conventional DSP architecture. The DSP includes four processing units operating in parallel. Two of these units are memory access units (MEMU)  10 . An arithmetic and logic unit (ALU)  12  and a branch unit (BRU)  14  are further provided. Each of the MEMU units is associated with a memory  16  via an independent bus. 
     Branch unit BRU receives from an instruction memory, not shown, a compound instruction INST which can include four elementary instructions to be provided to each of the units in parallel. Unit BRU retrieves the instruction meant for it and distributes in parallel the three remaining instructions I 1 , I 2 , and I 3  to the ALU and MEMU units. 
     Each of the ALU and MEMU units generally includes an instruction queue  18 , in the form of a FIFO, in which the instructions wait before they are processed by the corresponding unit. 
     A DSP of the type of FIG. 1 is optimized to perform vectorial operations of the type X[i] OP Y[j], where i and j vary, generally in a loop, and where OP designates any operation to be performed by arithmetic unit  12 . Indeed, operands X[i] and Y[j] can be fetched together via the two buses of memory  16  and processed, in theory, in the same cycle by ALU  12 . 
     In practice, difficulties arise due to the structure of currently used memories, generally SRAMs. Although a memory access can be performed at each cycle, the reading of data from a conventional SRAM generally has a latency of two cycles. Indeed, upon execution of a read instruction, the address is presented to the memory. An additional cycle is required to provide the memory with a read access signal, and a last cycle is required for the memory to present the data over its data bus. 
     To illustrate the resulting difficulties, a common loop, the function of which is to increment by a constant successive values stored in the memory will be considered hereafter as an example. This loop may directly be written as: 
       LD: R   1 =[ i]   
     
       
           OP: R   1 = R   1 + R   2   
       
     
     
       
         
           ST: [i]=R 
           1 
         
       
     
     
       
           BR:  test  i, i++,  loop  (1) 
       
     
     This loop, for clarity, uses a single MEMU unit. It consists of loading (LD) in a register R 1  the value stored in the memory at address i, incrementing (OP) the content of register R 1  by the value contained in a register R 2 , storing (ST) at address i the new content of register R 1 , and finally incrementing and testing address i to resume the loop (BR). The loop will be left when branch unit BRU detects that address i has reached a predetermined value. In a DSP, there are generally no BR-type instructions. The loops are programmed in advance by setting registers provided for this purpose in unit BRU which performs the tests, incrementations and branchings independently. 
     Register R 1  is a work register of the ALU, while address i is stored in a register of branch unit BRU. Operations LD and ST are operations to be performed by one of units MEMU, operation OP is to be performed by unit ALU, and operation BR is to be performed by unit BRU. Operations LD and OP will be provided in parallel to units MEMU and ALU in a same compound instruction, while operations ST and BR will be provided in parallel to units MEMU and BRU in a second compound instruction. 
     In fact, some compound instructions include fields which are provided to several units at a time. For example, a load instruction LD, meant for a unit MEMU, also includes a field meant for unit ALU to prepare one of its registers (R 1 ) to receive the data which will be presented by the memory. Similarly, a store instruction ST includes a field meant for unit ALU to select a register, the content of which is presented over the memory bus. Thus, as shown in FIG. 1, a field f of each of instructions I 2  and I 3  provided to units MEMU is provided to the instruction queue  18  of unit ALU in parallel with a normal instruction I 1 , and unit ALU is able to perform in one cycle a normal instruction and an operation indicated by a field f. 
     The following table illustrates, for several iterations of the loop, the operations performed by one memory access unit MEMU and by arithmetic unit ALU. The branching instructions BR do not raise any problem and the table does not illustrate them, for clarity. 
     Each row in the table corresponds to an instruction cycle and each operation marked in the table is assigned with a number corresponding to the loop iteration. 
     
       
         
               
               
               
             
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Instruction queues 
                 Units 
               
             
          
           
               
                 Cycle 
                 MEMU 
                 ALU 
                 MEMU 
                 ALU 
               
               
                   
               
             
          
           
               
                 1 
                 LD1 
                 OP1 
                 LD1 
                 — 
               
               
                 2 
                 ST1 
                   
                 — 
                 — 
               
               
                   
                   
                 OP1 
               
               
                 3 
                 LD2 
                 OP2 
                 — 
                 OP1 
               
               
                   
                 ST1 
               
               
                   
                   
                 OP1 
               
               
                 4 
                 ST2 
                   
                 ST1 
                 — 
               
               
                   
                 LD2 
                 OP2 
               
               
                   
                 ST1 
               
               
                 5 
                 LD3 
                 OP3 
                 LD2 
                 — 
               
               
                   
                 ST2 
               
               
                   
                 LD2 
                 OP2 
               
               
                 6 
                 ST3 
                   
                 — 
                 — 
               
               
                   
                 LD3 
                 OP3 
               
               
                   
                 ST2 
               
               
                   
                   
                 OP2 
               
               
                 7 
                 LD4 
                 OP4 
                 — 
                 OP2 
               
               
                   
                 ST3 
               
               
                   
                 LD3 
                 OP3 
               
               
                   
                 ST2 
               
               
                   
                   
                 OP2 
               
               
                 8 
                 ST4 
                   
                 ST2 
                 — 
               
               
                   
                 LD4 
                 OP4 
               
               
                   
                 ST3 
               
               
                   
                 LD3 
                 OP3 
               
               
                   
                 ST2 
               
               
                 9 
                 LD5 
                 OP5 
                 LD3 
                 — 
               
               
                   
                 ST4 
               
               
                   
                 LD4 
                 OP4 
               
               
                   
                 ST3 
               
               
                   
                 LD3 
                 OP3 
               
               
                 10 
                 ST5 
                   
                 — 
                 — 
               
               
                   
                 LD5 
                 OP5 
               
               
                   
                 ST4 
               
               
                   
                 LD4 
                 OP4 
               
               
                   
                 ST3 
               
               
                   
                   
                 OP3 
               
               
                 11 
                 LD6 
                 OP6 
                 — 
                 OP3 
               
               
                   
                 ST5 
               
               
                   
                 LD5 
                 OP5 
               
               
                   
                 ST4 
               
               
                   
                 LD4 
                 OP4 
               
               
                   
                 ST3 
               
               
                   
                   
                 OP3 
               
               
                 12 
                 ST6 
                   
                 ST3 
                 — 
               
               
                   
                 LD6 
                 OP6 
               
               
                   
                 ST5 
               
               
                   
                 LD5 
                 OP5 
               
               
                   
                 ST4 
               
               
                   
                 LD4 
                 OP4 
               
               
                   
                 ST3 
               
               
                   
               
             
          
         
       
     
     At the first cycle, units MEMU and ALU receive the first instructions LD and OP (LD 1 , OP 1 ). Unit MEMU immediately executes instruction LD 1 , which starts the read cycle of the value stored at address i in the memory. Instruction LD 1  is deleted from the instruction queue of unit MEMU. Instruction OP 1 , which needs the value fetched by instruction LD 1 , cannot be executed yet. This instruction OP 1  waits in the instruction queue of unit ALU. 
     At the second cycle, unit MEMU receives the first instruction ST (ST 1 ). Instruction ST 1 , which needs the result of operation OP 1 , cannot be executed yet and waits in the instruction queue of unit MEMU. Instruction OP 1  still waits in the queue of unit ALU, since the memory still does not send back the operand that it requires. 
     At the third cycle, units MEMU and ALU receive instructions LD 2  and OP 2 . These instructions are put in the queues after the still unexecuted instructions ST 1  and OP 1 . The memory finally sends back the operand required by instruction OP 1 . This instruction OP 1  is then executed and deleted from the instruction queue. 
     At cycle 4, unit MEMU receives instruction ST 2 . Instruction ST 2  is put to wait in the queue of unit MEMU after instruction LD 2 . Since instruction OP 1  was executed at the previous cycle, its result is available. Instruction ST 1  can thus be executed and deleted from the queue. Although instruction OP 2  is alone in the queue of unit ALU, this instruction cannot be executed yet since it requires an operand which will be fetched by the execution of instruction LD 2 . 
     At cycle 5, units MEMU and ALU receive instructions LD 3  and OP 3 . Instruction LD 2  is executed and deleted from the queue. 
     Instruction OP 2  must still wait in the queue, since it requires an operand which will be sent back two cycles later by the memory in response to instruction LD 2 . 
     From the fifth cycle on, the execution of the instructions of the second iteration of the loop proceeds as for the first iteration starting at cycle 1. 
     As shown by the table, although the processor is capable of performing one memory access at each cycle, it only performs memory access two cycles out of four, that is, the loop execution efficiency is only 50%. 
     Further, upon each new iteration of the loop, the instruction queue of unit MEMU fills with additional instructions and ends up overflowing. To avoid the overflow, the provision of instructions must be regularly stopped to enable the queues to empty. This considerably decreases the efficiency. 
     In fact, the loop programming in its straightforward form is not at all optimal due to the memory latency. 
     To improve the efficiency, taking account of the memory latency, a so-called loop unrolling technique is often used. This technique consists of programming a macroloop, each iteration of which corresponds to several iterations of the normal loop. Thus, the preceding loop (1) is written, for example, as: 
     
       
           Lda: R   1 =[ i]   
       
     
     
       
           Opa: R   1 = R   1 + R   2   
       
     
     
       
           Ldb: R   3 =[ i+ 1] 
       
     
     
       
           Opb: R   3 = R   3 + R   2   
       
     
     
       
         
           Sta: [i]=R 
           1 
         
       
     
     
       
           Stb: [i+ 1]= R   3   
       
     
     
       
           BR:  test  i, i=+ 2, loop  (2) 
       
     
     In this loop, the value contained at address i is loaded (LDa) in register R 1 , the content of register R 2  is incremented (OPa) by the content of a register R 1 , the value contained at address i+1 is loaded (LDb) in a register R 3 , the content of register R 3  is incremented (OPb) by the value contained in register R 2 , the content of register R 1  is stored (STa) at address i, the content of register R 3  is stored (STb) at address i+1, and variable i is incremented by 2 to restart the loop. 
     This loop is programmed in four compound instructions. The first one is formed of operations LDa and OPa, the second one of instructions LDb and OPb, the third one of instruction STa, and the fourth one of instructions STb and BR. The following table illustrates the sequence of operations for several loop iterations. 
     
       
         
               
               
               
             
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Instruction queues 
                 Units 
               
             
          
           
               
                 Cycle 
                 MEMU 
                 ALU 
                 MEMU 
                 ALU 
               
               
                   
               
             
          
           
               
                 1 
                 LDa1 
                 OPa1 
                 LDa1 
                 — 
               
               
                 2 
                 LDb1 
                 OPb1 
                 LDb1 
                 — 
               
               
                   
                   
                 OPa1 
               
               
                 3 
                 STa1 
                   
                 — 
                 OPa1 
               
               
                   
                   
                 OPb1 
               
               
                   
                   
                 OPa1 
               
               
                 4 
                 STb1 
                   
                 — 
                 OPb1 
               
               
                   
                 STa1 
               
               
                   
                   
                 OPb1 
               
               
                 5 
                 LDa2 
                 OPa2 
                 STa1 
                 — 
               
               
                   
                 STb1 
               
               
                   
                 STa1 
               
               
                 6 
                 LDb2 
                 OPb2 
                 STb1 
                 — 
               
               
                   
                 LDa2 
                 OPa2 
               
               
                   
                 STb1 
               
               
                 7 
                 STa2 
                   
                 LDa2 
                 — 
               
               
                   
                 LDb2 
                 OPb2 
               
               
                   
                 Lda2 
                 OPa2 
               
               
                 8 
                 STb2 
                   
                 LDb2 
                 — 
               
               
                   
                 STa2 
               
               
                   
                 LDb2 
                 OPb2 
               
               
                   
                   
                 OPa2 
               
               
                 9 
                 LDa3 
                 OPa3 
                 — 
                 OPa2 
               
               
                   
                 STb2 
               
               
                   
                 STa2 
               
               
                   
                   
                 OPb2 
               
               
                   
                   
                 OPa2 
               
               
                 10 
                 LDb3 
                 OPb3 
                 — 
                 OPb2 
               
               
                   
                 LDa3 
                 OPa3 
               
               
                   
                 STb2 
               
               
                   
                 STa2 
               
               
                   
                   
                 OPb2 
               
               
                 11 
                 STa3 
                   
                 STa2 
                 — 
               
               
                   
                 LDb3 
                 OPb3 
               
               
                   
                 LDa3 
                 OPa3 
               
               
                   
                 STb2 
               
               
                   
                 STa2 
               
               
                 12 
                 STb3 
                   
                 STb2 
                 — 
               
               
                   
                 STa3 
               
               
                   
                 LDb3 
                 OPb3 
               
               
                   
                 LDa3 
                 OPa3 
               
               
                   
                 STb2 
               
               
                   
               
             
          
         
       
     
     At the first cycle, units MEMU and ALU receive the first instructions LDa and OPa (LDa 1 , OPa 1 ). Instruction LDa 1  is immediately executed and deleted from the queue. 
     At the second cycle, units MEMU and ALU receive instructions LDb 1  and OPb 1 . Instruction LDb 1  is immediately executed and deleted from the queue. Instructions OPa 1  and OPb 1  remain in the queue of unit ALU waiting for the corresponding operands that the memory has to send back in response to instructions LDa 1  and LDb 1 . 
     At the third cycle, unit MEMU receives instruction STa 1 . The memory sends back the operand asked for by instruction LDa 1  and required by instruction OPa 1 . Instruction OPa 1  can thus be executed and deleted from the queue. 
     At the fourth cycle, unit MEMU receives instruction STb 1 . The memory sends back the operand asked for by instruction LDb 1  and required by instruction OPb 1 . Instruction OPb 1  can thus be executed. 
     At the fifth cycle, units MEMU and ALU receive instructions LDa 2  and OPa 2 . Instruction STa 1  can be executed since the value that it requires has been calculated by instruction OPa 1  two cycles before. 
     At the sixth cycle, units MEMU and ALU receive instructions LDb 2  and OPb 2 . Instruction STb 1  is executed since the value that it requires has been calculated by instruction OPb 1  two cycles before. 
     At the seventh cycle, unit MEMU receives instruction STa 2 . A new iteration of the loop is started by the execution of instruction LDa 2 . 
     The processor appears in this table to perform four memory accesses every six cycles, which amounts to a 66% efficiency and a 33% gain with respect to the preceding solution. 
     The queue of unit MEMU however appears to progressively fill up, requiring to regularly stop the instruction provision. It fills with two instructions every six cycles instead of with two instructions every four cycles as was the case for the previous solution. 
     The loop unrolling technique, although substantially improving the efficiency, is not an optimal solution for superscalar processors. In fact, it works much better on scalar processors. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a superscalar processor architecture having a maximum efficiency for the execution of loops including memory access instructions. 
     This object as well as others is achieved by means of a processor including at least one memory access unit for presenting a read or write address over an address bus of a memory in response to the execution of a read or write instruction; and an arithmetic and logic unit operating in parallel with the memory access unit and arranged at least to present data on the data bus of the memory while the memory access unit presents a write address. The processor includes a write address queue in which is stored each write address provided by the memory access unit waiting for the availability of the data to be written. 
     According to an embodiment of the present invention, the arithmetic and logic unit includes two independent instruction queues intended for receiving instructions waiting for execution, a first of the instruction queues being intended for receiving logic and arithmetic instructions, and the second instruction queue being intended for receiving instruction fields provided to the memory access unit to identify registers of the arithmetic and logic unit which are involved in read or write operations. 
     According to an embodiment of the present invention, the arithmetic and logic unit includes a store data queue in which each datum to be written in the memory waits for the presence of a write address in the write address queue. 
     According to an embodiment of the present invention, the arithmetic and logic unit includes a load data queue in which is written each datum from the memory for the arithmetic and logic unit, waiting for the arithmetic and logic unit to be available. 
     According to an embodiment of the present invention, the processor includes a branch unit for receiving instructions and distributing them in parallel between itself, the memory access unit and the arithmetic and logic unit. 
     According to an embodiment of the present invention, each of the units includes a store data queue in which each datum to be written in the memory waits for the presence of a write address in the write address queue. 
     According to an embodiment of the present invention, each of the units includes a load data queue in which is written each datum from the memory for the unit, waiting for the unit to be available. 
     The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1, previously described, shows a conventional DSP architecture; and 
     FIG. 2 shows a DSP architecture according to the present invention. 
    
    
     DETAILED DESCRIPTION 
     In FIG. 2, a processor according to the present invention includes, as in FIG. 1, two memory access units  10  (MEMU) and one logic and arithmetic unit  12  (ALU), all coupled with a branch unit  14 . Units  10  and  12  include instruction queues  18  in which branch unit BRU stacks instructions awaiting execution. 
     According to the present invention, each memory access unit MEMU includes a store address queue STAQ from which are provided the addresses used for the write accesses to memory  16 . The read addresses are conventionally provided to memory  16 , as shown by dotted lines across queues STAQ. 
     Further, unit ALU is provided with a store data queue STDQ and with a load data queue LDDQ through which the data exchanged with the memory transit. In practice, all units in a processor are conventionally likely to exchange data with the memory and thus include, as shown, queues STDQ and LDDQ. Queues STAQ, STDQ, and LDDQ all are of FIFO type. 
     Each time a unit MEMU executes a store instruction, the write address is stacked in the corresponding queue STAQ. The data to be written by this instruction are stacked in a corresponding store data queue STDQ, generally of unit ALU. For example, if the content of register R 1  of unit ALU should be written at address i, the unit MEMU which executes the write instruction stacks address i in its queue STAQ while unit ALU stacks the content of register R 1  in its queue STDQ. It should be noted that the data to be written are not necessarily stacked in queue STDQ at the same time as the address is stacked in queue STAQ. This is an essential aspect of the present invention. 
     At each cycle, the contents of queues STDQ and STAQ are polled. If queue STAQ contains an address and one of queues STDQ contains data, the data is written at the address contained in queue STAQ, then queues STDQ and STAQ are updated. If these conditions are not fulfilled, that is, if queue STAQ is empty, or if queues STDQ are all empty, no writing is performed. The condition where two queues STDQ contain data at the same time never occurs. 
     In the case of a DSP including two memory access units MEMU, each location of queues STDQ may contain two data words, one for each of units MEMU. Then, for a writing to occur, a data word contained in the location of a queue STDQ must besides correspond to the unit MEMU having a non-empty queue STAQ. 
     This mechanism enables executing a write instruction immediately, without taking account of the availability of the memory bus or of the data to be written. The data to be written will be written subsequently, as soon as the data and the memory bus are all available. This mechanism is described in more detail hereafter by means of an example. 
     Consider again the example of loop (1), programmed in its straightforward form: 
     
       
           LD: R   1 =[ i]   
       
     
     
       
           OP: R   1 = R   1 + R   2   
       
     
     
       
         
           ST: [i]=R 
           1 
         
       
     
     
       
           BR:  test  i, i++,  loop  (1) 
       
     
     As previously indicated, a load instruction LD or store instruction ST is formed of two fields, one for unit MEMU to indicate the read or write address, and the other for unit ALU to indicate the register which should receive the data read or the content of which should be written. Thus, an instruction LD hereabove decomposes in an ALU instruction: 
     
       
           LDA: R   1 = LDDQ,   
       
     
     for loading in register R 1  the first element of load queue LDDQ, and a MEMU instruction: 
     
       
           LDM: R ( i ), 
       
     
     for presenting address i in read mode. 
     An above store instruction ST decomposes in an ALU instruction: 
     
       
           STA: STDQ=R   1 , 
       
     
     for stacking the content of register R 1  in store queue STDQ, and a MEMU instruction: 
     
       
         
           STM: STAQ=i, 
         
       
     
     for stacking write address i in address queue STAQ. 
     The fields f of the read/write instructions for unit ALU are, according to the present invention, stacked in an instruction queue  19  independent of queue  18  by which the normal instructions I 1  for unit ALU (such as instruction OP) are received. 
     The following table illustrates, for several iterations of loop (1), the operations performed by one of units MEMU and unit ALU, and the contents of the instruction queues of units MEMU and ALU, the contents of queue STAQ of unit MEMU, and finally the contents of queues STDQ and LDDQ of unit ALU. In the table, the operations are assigned with a number corresponding to the iteration. 
     
       
         
               
               
             
               
               
               
               
               
             
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Memory queues 
               
             
          
           
               
                   
                 Instruction queues 
                 Units 
                 MEMU 
                 ALU 
               
             
          
           
               
                 Cycle 
                 MEMU 
                 ALU 
                 MEMU 
                 ALU 
                 STAQ 
                 STDQ 
                 LDDQ 
               
               
                   
               
             
          
           
               
                 1 
                 LDM1 
                 LDA1 
                 OP1 
                 LDM1 
                 — 
                   
                   
                   
               
               
                 2 
                 STM1 
                 STA1 
                   
                 STM1 
                 — 
                 i 
               
               
                   
                   
                 LDA1 
                 OP1 
                   
                   
               
               
                 3 
                 LDM2 
                 LDA2 
                 OP2 
                 LDM2 
                 LDA1 
                 i 
                   
                 [i] 
               
               
                   
                   
                 STA1 
                   
                   
                 OP1 
               
               
                   
                   
                 LDA1 
                 OP1 
               
               
                 4 
                 STM2 
                 STA2 
                   
                 STM2 
                 STA1 
                 i + 1 
               
               
                   
                   
                 LDA2 
                 OP2 
                   
                   
                 i 
                 R1 1   
               
               
                   
                   
                 STA1 
               
               
                 5 
                 LDM3 
                 LDA3 
                 OP3 
                 LDM3 
                 LDA2 
                 i + 1 
                   
                 [i + 1] 
               
               
                   
                   
                 STA2 
                   
                   
                 OP2 
               
               
                   
                   
                 LDA2 
                 OP2 
               
               
                 6 
                 STM3 
                 STA3 
                   
                 STM3 
                 STA2 
                 i + 2 
               
               
                   
                   
                 LDA3 
                 OP3 
                   
                   
                 i + 1 
                 R1 2   
               
               
                   
                   
                 STA2 
               
               
                 7 
                 LDM4 
                 LDA4 
                 OP4 
                 LDM4 
                 LDA3 
                 i + 2 
                   
                 [i + 2] 
               
               
                   
                   
                 STA3 
                   
                   
                 OP3 
               
               
                   
                   
                 LDA3 
                 OP3 
               
               
                 8 
                 STM4 
                 STA4 
                   
                 STM4 
                 STA3 
                 i + 3 
               
               
                   
                   
                 LDA4 
                 OP4 
                   
                   
                 i + 2 
                 R1 3   
               
               
                   
                   
                 STA3 
               
               
                   
               
             
          
         
       
     
     At the first cycle, units MEMU and ALU receive instructions LD 1  and OP 1 , instruction LD 1  being decomposed in an instruction LDM 1  provided to unit MEMU and an instruction LDA 1  provided to unit ALU. Instruction LDM 1 , directing transmission of a read address, is immediately executed. Instruction LDA 1  is set to wait, since it requires a value from read queue LDDQ, which is empty. Instruction OP 1 , which requires this same value, is also set to wait. 
     At the second cycle, unit MEMU receives instruction ST 1 , decomposed in an instruction STM 1  provided to unit MEMU and an instruction STA 1  provided to unit ALU. Instruction STM 1  is executed and causes the stacking in queue STAQ of address i at which the result of operation OP 1  will be written. Instruction STA 1  is set to wait behind instruction LDA 1 . 
     At the third cycle, units MEMU and ALU receive instructions LD 2  (LDM 2 , LDA 2 ) and OP 2 . The memory provides queue LDDQ with the value [i] required by instruction LDM 1 . Instruction LDA 1  is executed and causes the transfer of value [i] from queue LDDQ to register R 1 . Instruction OP 1  is executed and updates the content of register R 1 . Unit MEMU being free, instruction LDM 2  is also executed. 
     At the fourth cycle, unit MEMU receives instruction ST 2  (STM 2 , STA 2 ). Instructions STM 2  and STA 1  are executed. Instruction STA 1  causes the copying of the content R 1   1  of register R 1  into queue STDQ. Instruction STM 2  causes the stacking in queue STAQ of the address i+1 at which the result of operation OP 2  will be written. In the same cycle, queue STAQ is detected to contain an address i and queue STDQ of unit ALU is detected to contain data R 1   1 . Since the memory bus is available, data R 1   1  are immediately written at address i and queues STAQ and STDQ are updated. 
     At the fifth cycle, the operations of the third cycle are repeated for a new loop iteration. 
     The above table illustrates that memory unit MEMU executes an access instruction for each cycle. The efficiency is thus maximum. Further, the instruction queues do not fill up. It is thus not necessary to regularly stop the provision of instructions to avoid queue overflow. 
     Queues STDQ and LDDQ appear in this example to receive at most one element. These queues could thus be reduced to a mere register, which register is generally provided in a conventional unit to latch the incoming and outgoing data. 
     In other cases, for more complex loops, queues STDQ and LDDQ may appear to receive more than one element. Then, the number of locations of queues STDQ and LDDQ is increased to avoid any risk of overflow. 
     Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.