Abstract:
A repeatable finite anti infinite impulse response integrated circuit structure has a plurality of filter units programmably interconnected, with each filter unit having a pair of repeatable cells. Each cell has a coefficient stage for receiving a filter coefficient, a mixer stage for multiplying a selected one of a plurality of input signals by the filter coefficient, an accumulator stage for selectively delaying an input accumulation signal, and a summation stage for adding the input accumulation signal to the weighted signal to produce an output accumulation signal. With appropriate programming many desired finite/infinite impulse response filter configurations may be achieved.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to digital filters, and more particularly to a repeatable finite and infinite impulse response integrated circuit (IC) structure having a plurality of standard cells repeated on an IC substrate and interconnected, the cells being programmable to provide most desired FIR or IIR filter configurations. 
     Finite impulse response (FIR) and infinite impulse response (IIR) filters generally are individually designed for each application. This requires a specially designed integrated circuit structure for each desired FIR or IIR filter. Various types of FIR and IIR filter designs are shown in the text book &#34;Discrete-Time Signal Processing&#34; by Oppenheim and Schafer, published 1989 by Prentice Hall of Englewood Cliffs, N.J., at sections 6.3-6.6 (pages 300-323), incorporated herein by reference. 
     What is desired is a standard integrated circuit structure that may be programmed to become a desired FIR or IIR filter configuration. 
     SUMMARY OF THE INVENTION 
     Accordingly the present invention provides a repeatable finite and infinite impulse response integrated circuit (IC) structure using a plurality of repeatable cells coupled together, the cells being programmable according to the desired finite impulse response (FIR) or infinite impulse response (IIR) filter configuration desired. Each cell has a coefficient stage for receiving a filter coefficient, a mixer stage for multiplying a selected one of a plurality of input signals by the filter coefficient to produce a weighted signal, an accumulator, delay stage for selectively delaying an input accumulation signal, and a summation stage for adding the input accumulation signal from the accumulator delay stage to the weighted signal to produce an output accumulation signal. Pairs of the cells are interconnected for form filter units, and a plurality of filter units are programmably interconnected to form a programmable finite/infinite impulse response filter structure that may be programmed to be any desired finite/infinite impulse response filter configuration. 
     The objects, advantages and other novel features of the present invention are apparent from the following detailed description when read in light of the appended claims and attached drawing. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a block diagram view of a repeatable cell according to the present invention. 
     FIG. 2 is a block diagram view of a filter unit according to the present invention. 
     FIG. 3 is a block diagram view of a programmable finite/infinite impulse response filter structure according to the present invention. 
     FIG. 4 is a block diagram view of a transposed FIR network structure using the filter units according to the present invention. 
     FIG. 5 is a block diagram view of a transposed cascade FIR structure using the filter units according to the present invention. 
     FIG. 6 is a block diagram view of a transposed IIR structure using the filter units according to the present invention. 
     FIG. 7 is a block diagram view of a transposed second-order cascade structure using the filter units according to the present invention. 
     FIG. 8 is a block diagram view of a FIR lattice structure using the filter units according to the present invention. 
     FIG. 9 is a block diagram view of a lattice form for an all pole IIR structure using the filter units according to the present invention. 
     FIG. 10 is a block diagram view of an expanded programmable finite/infinite impulse response filter structure according to the present invention. 
     FIG. 11 is a block diagram view of a lattice form for a pole and zeros IIR structure using the filter units according to the present invention. 
     FIG. 12 is a block diagram view of a parallel form structure for a sixth-order filter system with transposed real and complex poles grouped in pairs. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to FIG. 1 a repeatable cell 10 for use in a repeatable finite and infinite impulse response integrated circuit (IC) structure is shown. The repeatable cell 10 has a coefficient stage 12, a mixer stage 13, an accumulator delay stage 14 and a summation stage 15. The coefficient stage 12 has an input coefficient register 16 that has a serial input 17 by which a serial coefficient SC may be loaded. The serial coefficient SC may be loaded using boundary scan techniques, as is well known in the art. The input coefficient register 16 has a parallel output 19 that is one input to a coefficient multiplexer 18. The other input to the coefficient multiplexer 18 is a parallel coefficient PC. The output of the coefficient multiplexer 18 is input to a holding register 20, which may be a latch. The output of the holding register is input to an output coefficient register 22. A data register 24 receives data DI from a data bus and provides it as one input to a multiplier multiplexer 26. The multiplier multiplexer 26 has three additional inputs, two for use in a lattice configuration IAT, LATZ and another for use in a feedback FB configuration, as is explained in more detail below. The outputs of the multiplier multiplexer 26 and the output coefficient register 22 are input to a multiplier 28 that provides a weighted data value at its output. 
     A first accumulator input ACCI --  IN is applied to an input accumulator register 30 in the accumulator delay stage 14. The output of the input accumulator register 30 and the first accumulator input ACCI --  IN are input to an input accumulator multiplexer 32. The output of the input accumulator multiplexer 32 is input to an output accumulator register 34. The outputs of the output accumulator register 34 and the first accumulator input ACCI --  IN are input to a summation input multiplexer 36. Also input to the summation input multiplexer 36 is an accumulated feedback signal ACC --  FB used as a lattice accumulator feedback for an all zeros lattice configuration. The output of the summation input multiplexer 36 provides a data output DO for subsequent cells 10 and is input to a summation circuit 38. Also input to the summation circuit 38 is the weighted data value from the multiplier 28. The output of the summation circuit 38 is a first accumulator output ACCI --  OUT, and also is input to an output multiplexer 40. The other input to the output multiplexer 40 is a second accumulator input ACC2 --  IN from a prior cell 10, and the output from the output multiplexer is a second accumulator output ACC2 --  OUT for input to a subsequent cell 10. 
     The registers are clocked by a system clock (not shown), and thus act as delay units of one clock interval. In the coefficient stage 12 a serial digital coefficient value SC is clocked into the input coefficient register 16 on consecutive clock pulses. Alternatively the input coefficient register 16 may be loaded in parallel from the latch 20. The latch 20 holds the current coefficient for the output coefficient register 22, while the input coefficient register 16 holds the next coefficient. A parallel digital coefficient value PC may be loaded via the multiplexer 18 into the latch 20 to change the coefficient in the output register 22 rapidly. This provides versatility in the selection and changing of coefficient values. 
     Likewise the multiplier multiplexer 26, by being able to select one of four inputs for multiplication by the coefficient, provides programmable flexibility. In the accumulator delay stage 14 the arrangement of registers and multiplexers acts as a variable delay device for the first accumulator input ACCI --  IN from zero to two clock cycles. A clear command CLR for the output accumulator register 34 provides a means of providing a zero value output from the accumulator delay stage 14. The final programmability for the cell 10 is provided by the output multiplexer 40 that selects either the second accumulator input ACC2 --  IN or the first accumulator output ACC1 --  OUT as the second accumulator output ACC2 --  OUT. 
     As shown in FIG. 2 two of the repeatable cells 10 form a filter unit 42, with one repeatable cell 10&#39; being inverted relative to the other. Thus the first accumulator output ACC1-OUT from the summation circuit 38 of the first cell 10 is the second accumulator input ACC2 --  IN for the second cell 10&#39;. The data output DO from the summation input multiplexer 36 of each cell 10, 10&#39; is input to the lattice input LAT of the multiplier multiplexer 26 of the other cell. The second accumulator output ACC2 --  OUT of the output multiplexer 40 of the first cell 10 provides the first accumulator input ACCI --  IN to the second cell 10&#39;. The summation circuit 38 output from the second cell 10&#39; provides the accumulated lattice ACC --  FB input to the summation multiplexer 36 in a prior filter unit 42, and the summation input multiplexer 36 of the second cell receives the accumulated lattice input from a subsequent filter unit. The third input to the summation input multiplexer 36 of the first cell 10 is tied to a zero value. Each cell 10, 10&#39; has its own serial and parallel coefficients SC, PC and output accumulator 34 clear lines CLR. 
     FIR and IIR filter structures may be built up using multiples of three filter units 42. A complete repeatable finite and infinite impulse response integrated circuit structure is represented in FIG. 3 using six filter units. A first input coefficient register 44 receives three parallel coefficient values and couples them via an input register 46 to the first cells 10 of the upper three filter units 42A and couples them directly to the first cells of the lower three filter units 42B. Likewise a second input coefficient register 48 receives three other parallel coefficient values and couples them via a third register 50 to the second cells 10&#39; of the upper filter units 42 and directly to the second cells of the lower three filter units. An input data signal X(n) is also provided to the filter units via the input register 46. The serial coefficients SC are loaded into the respective input coefficient registers 16 in series using boundary scan techniques as indicated above. An output multiplexer 52 is provided for each set of three filter units and has as inputs the input signal, which for the second output multiplexer is the output of the first output multiplexer, and the outputs of the summation circuits 38 from the last filter unit 42 in each set of three. The output from the second output multiplexer is a folded data output. An input multiplexer 54 is provided also for each set of three filter units 42, the lower input multiplexer having as inputs a folded data input and the output from the summation circuit 38 from the first cell 10 of the last of the three filter units. The upper input multiplexer 54 has as inputs the output from the lower input multiplexer and the output from the summation circuit 38 from the last of the first cells 10 of the upper three filter units 42A. The outputs of the respective input multiplexers 54 are input to respective intermediate multiplexers 56 and to the respective multiplier multiplexers 26 in the second cells 10&#39;. The other input to the intermediate multiplexers 56 is the input signal X(n), and the outputs of the intermediate multiplexers are coupled to the respective data registers 24 of the second cells. By controlling the selection by the multiplexers, both external and internal to the cells, many filter configurations may be programmed. 
     FIG. 4 shows a transposed FIR structure corresponding to the tapped delay line or transversal filter structure shown as a flow graph in FIG. 6.28 of the aforementioned Oppenheim and Schafer text book. The input signal X(n) is input to the multipliers 28 in each cell 10, 10&#39; via multiplier registers 24. The coefficients are loaded into the output coefficient register 20 either via the serial coefficient registers 16 or directly from a computer as parallel coefficients PC (C0-C5). The initial weighted data in the first cell 10 is added to zero and passed on to the next cell 10&#39; so that after passing through all of the filter units 42 the FIR filtered output signal Y(n) is derived from the ACCI --  OUT of the last filter unit. Each filter unit 42 is identical except that the first unit adds zero, i.e., applies the CLR signal to the output accumulator register 34, to the weighted data value rather than a value accumulated from prior units. 
     FIG. 5 illustrates a transposed form of a cascade FIR structure that has a flow graph as shown in FIG. 6.29 of the Oppenheim and Schafer text book. Again with appropriate commands for the multiplexers the same basic repeatable structure is configured for the transposed cascade FIR structure. FIG. 6 illustrates a transposed IIR filter structure with a flow graph as shown in FIG. 6.26 of the Oppenheim and Schafer text book. FIG. 7 illustrates a transposed second-order cascade filter structure, corresponding to the flow graph of FIG. 6.24 in Oppenheim and Schafer. FIG. 8 illustrates a FIR lattice filter structure, corresponding to the flow graph of FIG. 6.33 of Oppenheim and Schafer. Finally FIG. 9 illustrates a lattice form for an all pole IIR filter structure, as shown in the flow graph at FIGS. 6.36 and 6.37 of Oppenheim and Schafer. 
     If, as shown in FIG. 10, the upper filter units 42A shown in FIG. 3 are stretched apart from the bottom filter units 42B, and a middle row of filter units 42C is placed between them, then two more filter structures may be realized. The middle filter units 42C are connected to the bottom filter units 42B the same way that the top filter units 42A are connected to the bottom filter units so that the middle filter units are the last filter units in the chain. Then the ACC1 --  IN of each cell 10 of the upper and bottom filter units 42A, 42B are connected to the LATZ inputs of each cell of the middle row filter units 42C. These connections allow implementation of the lattice structure shown in FIG. 11 with poles and zeros, as shown in FIG. 6.41 of the Oppenheim and Schafer text book. Also if a multiplexer 58 is added to the output of the middle row of filter units 42C to allow the output of the bottom row of filter units 42B to be multiplexed with the output port, then the output of multiplexer 40 of the last cell 10&#39; of the upper row of filter units 42A is connected to the LATZ input of the last cell of the middle row of filter units. Finally the output of the last cell 10&#39; of the middle row of filter units 42C is connected to the LATZ input of the last cell of the last row of filter units 42B. Coefficients for the multipliers 28 of the last cell 10&#39; of the last row of filter units 42B and the first row of filter units 42A are set to a value of &#34;1&#34; to just add the outputs of the three rows of filter units together. This configuration allows implementation of a transposed representation of a parallel form structure for a sixth-order system with real and complex poles grouped in pairs, as shown in FIG. 12, corresponding to FIG. 6.16 of the Oppenheim and Schafer test book. 
     Thus the present invention provides a repeatable finite and infinite impulse response integrated circuit structure that uses programmable standard cells, pairs of which are formed into filter units. A plurality of filter units are interconnected, using appropriate external registers and multiplexers, and are programmed to form many desired FIR or IIR filter structures.