Abstract:
High speed address decoders may include a predecoder and a main decoder that are both responsive to a control signal. The predecoder switches from an active state to an inactive state in response to a transition of the control signal from a first logic state to a second logic state. Conversely, the main decoder commences switching from an inactive state to an active state simultaneously with the transition of the control signal from the first logic state to the second logic state. The predecoder may generate a predecoded address signal while the control signal is in the first logic state, which may then be decoded by the main decoder to activate a line enable signal when the control signal transitions to the second logic state. As a result, address decoding speed may be improved thereby facilitating higher speed operation of an integrated circuit memory device.

Description:
RELATED APPLICATION 
     This application claims the benefit of Korean Patent Application No. 99-1649, filed Jan. 20, 1999, the disclosure of which is hereby incorporated herein by reference. 
     FIELD OF THE INVENTION 
     The present invention relates generally to the field of integrated circuit memory devices and, more particularly, to high-speed address decoding in integrated circuit memory devices. 
     BACKGROUND OF THE INVENTION 
     Improvements in both speed and functionality of personal computers and multimedia systems have generally resulted in accompanying improvements in memory devices to support the operation of these products. Various methods have been developed to increase the operational speed of integrated circuit memory devices. One approach to increasing the operational speed of integrated circuit memory devices may involve increasing the transmission speed of signals on data paths, such as the write data path and the read data path, which are used to write data to a memory cell and read data stored in a memory cell, respectively. It may also be desirable to decode a memory cell address at high speed to allow high-speed selection of a memory cell. In this regard, it may be particularly advantageous to decode row addresses at high speed to allow high-speed selection of a row or a word line. 
     With reference to FIG. 1, a conventional integrated circuit memory device includes a row predecoder  11  and an internal master signal generator  13 . The internal master signal generator  13  is coupled to both the row predecoder  11  and an enable signal generator  15 . The integrated circuit memory device further includes a row main decoder  17 , which is coupled to a memory cell array  19 . The row predecoder  11  and the enable signal generator  15  are both coupled to the row main decoder  17 . Operations of the integrated circuit memory device of FIG. 1 will be described hereafter with reference to the signal timing diagram of FIG.  2 . 
     A row address RAi and a row address strobe signal {overscore (RAS)} (ie., external master signal) are provided as inputs to the row predecoder  11  and the internal master signal generator  13 , respectively. As shown in FIG. 2, the row address RAi is provided for a predetermined length of time, tAS (ie., row address setup time) before the row address strobe signal {overscore (RAS)} is activated (ie., driven to a logic 0 level). The internal master signal generator  13 , in response to the activation of the row address strobe signal {overscore (RAS)}, activates an internal master signal PR by driving the internal master signal PR to a logic 1 level. In response to the activation of the internal master signal PR, the row predecoder  11  predecodes the row address RAi and generates a predecoded row address DRAij. 
     After the internal master signal PR has been activated, the enable signal generator  15  allows a predetermined time interval tF to elapse before activating an enable signal PNBLS by driving the enable signal PNBLS to a logic 1 level. This delay provides the row predecoder  11  with time to generate the predecoded row address DRAij. The row main decoder  17  decodes the predecoded row address DRAij and activates a word line enable signal NWEi by driving the word line enable signal NWEi to a logic 1 level in response to the activation of the enable signal PNBLS. When the word line enable signal NWEi is activated, a corresponding word line in the memory cell array  19  is activated. Accordingly, a corresponding memory cell is selected from the memory cell array  19 . 
     As illustrated in the foregoing discussion, decoding a row address in a conventional integrated circuit memory device typically involves at least two time delays: First, the row predecoder  11  waits for the internal master signal generator  13  to activate the internal master signal PR before predecoding the row address RAi. Second, the enable signal generator  15  delays a predetermined time tF before activating the enable signal PNBLS to provide the row predecoder  11  with time to generate the predecoded row address DRAij. As a result , conventional integrated circuit memory devices may take a relatively long time from the point in time at which the row address {overscore (RAS)} is activated to the point in time at which the word line enable signal NWEi is activated. 
     Consequently, there exists a need for improved (e.g., higher speed) address decoding in integrated circuit memory devices. 
     SUMMARY OF THE INVENTION 
     High-speed address decoders may include a predecoder and a main decoder that a re both responsive to a control signal. The predecoder switches from an active state to an inactive state in response to a transition of the control signal from a first logic state to a second logic state. Conversely, the main decoder commences switching from an inactive state to an active state simultaneously with the transition of the control signal from the first logic state to the second logic state. The predecoder may generate a predecoded address signal while the control signal is in the first logic state, which may then be decoded by the main decoder to activate a line enable signal when the control signal transitions to the second logic state. As a result, address decoding speed may be improved thereby facilitating higher speed operation of an integrated circuit memory device. 
     In accordance with an aspect of the present invention, integrated circuit memory devices may include a predecoder and a main decoder as discussed in the foregoing. Integrated circuit memory devices may further include an internal signal generator that generates the control signal as an internal master signal in response to an address strobe signal and a memory cell array that is responsive to a line enable signal that is output from the main decoder. Because the predecoded address signal is already available when the control signal (ie., internal master signal) transitions from the first logic state to the second logic state, the main decoder can activate the line enable signal immediately upon the control signal transition. 
     In accordance with yet another aspect of the invention, the predecoder preferably comprises a plurality of logic gates that receive predetermined bits of the address signal at input terminals thereof, a plurality of latches that generate the predecoded address signal at output terminals thereof, and a plurality of transmission gates that are responsive to the control signal and connect the output terminals of the logic gates to the input terminals of the latches during the first logic state of the control signal. 
     In accordance with still another aspect of the invention, the main decoder preferably comprises a latch, a PMOS precharge transistor connected between a first reference potential (i.e., a logic 1 reference potential) and an input terminal of the latch, and a plurality of NMOS transistors electrically connected in series between the input terminal of the latch and a second reference potential (i.e., a logic 0 reference potential). The gate terminals of the NMOS transistors receive predetermined bits of the predecoded address signal from the predecoder. A control signal may be applied to the gate of the PMOS precharge transistor to charge the input terminal of the latch to a logic 1 level. 
     In accordance with still another aspect of the invention, both row and column addresses may be decoded. That is, the address may be either a row address or a column address and the line enable signal may be either a word line enable signal or a bit line enable signal. 
     Related address decoding methods are also disclosed herein. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other features of the present invention will be more readily understood from the following detailed description of specific embodiments thereof when read in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a block diagram that illustrates a conventional integrated circuit memory device; 
     FIG. 2 is a timing diagram that illustrates operations of the integrated circuit memory device of FIG. 1; 
     FIG. 3 is a block diagram that illustrates integrated circuit memory devices and address signal decoding methods in accordance with the present invention; 
     FIG. 4 is a block diagram that illustrates a row predecoder shown in FIG. 3 in greater detail; 
     FIG. 5 is a circuit diagram that illustrates a predecoder shown in FIG. 4 in greater detail; 
     FIG. 6 is a circuit diagram that illustrates a row main decoder shown in FIG. 3 in greater detail; and 
     FIG. 7 is a timing diagram that illustrates operations of integrated circuit memory devices and address signal decoding methods of FIG. 3 in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the invention to the particular forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the claims. Like reference numbers signify like elements throughout the description of the figures. 
     For purposes of clarity and in no way limited thereto, the present invention is described hereafter in the context of decoding a row address for a memory cell array. It should be understood that the principles of the present invention are equally applicable to decoding a column address for a memory cell array. 
     Referring now to FIG. 3, an integrated circuit memory device  30 , in accordance with the present invention, preferably includes a row predecoder  31  that is coupled to a row main decoder  35 . The row main decoder  35  is coupled to a memory cell array  37 . The integrated circuit memory device further includes an internal signal generator  33 , which is coupled to both the row predecoder  31  and the row main decoder  35 . Exemplary operations of the integrated circuit memory device  30  will be described hereafter with reference to the signal timing diagram of FIG.  7 . 
     A row address RAi and a row address strobe signal {overscore (RAS)} (i.e., external master signal) are provided as inputs to the row predecoder  31  and the internal signal generator  33 , respectively. Typically, the row address strobe signal {overscore (RAS)} is generated external to the row predecoder  31 , internal signal generator  33 , row main decoder  35 , and memory cell array  37 . The row address RAi may be externally or internally generated. As shown in FIG. 7, it is customary for the row address RAi to be provided for a predetermined length of time, tAS (i.e., row address setup time) before the row address strobe signal {overscore (RAS)} is activated (ie., driven to a logic 0 level). The internal signal generator  33 , in response to the activation of the row address strobe signal {overscore (RAS)}, activates an internal master signal PR and, optionally, an enable signal PNBLS by driving both the internal master signal PR and the enable signal PNBLS to a logic 1 level. The row predecoder  31 , however, predecodes the row address RAi during the inactive state (ie., logic 1 level) of both the row address strobe signal {overscore (RAS)} and the internal master signal PR to generate the predecoded row address DRAij. 
     The row main decoder  35  decodes the predecoded row address DRAij and activates a word line enable signal NWEi by driving the word line enable signal NWEi to a logic 1 level in response to the activation of the enable signal PNBLS. Note, however, that the enable signal PNBLS can be eliminated and replaced with the internal master signal PR without changing any finctionality of the integrated circuit memory device  30  because the enable signal PNBLS and the internal master signal PR may be identical signals. When the word line enable signal NWEi is activated, a corresponding word line in the memory cell array  37  is activated. Accordingly, a corresponding memory cell is selected from the memory cell array  37 . 
     Advantageously, the integrated circuit memory device  30  in accordance with the present invention may reduce the time between activation of the row address strobe signal {overscore (RAS)} and activation of the word line enable signal NWEi. Specifically, the row predecoder  31  predecodes the row address RAi during the inactive state of both the row address strobe signal {overscore (RAS)} and the internal master signal PR. In contrast with conventional integrated circuit memory devices, the row predecoder  31  need not wait for the internal signal generator  33  to activate the internal master signal PR before predecoding the row address RAi. Moreover, because the predecoded row address DRAij is already available when the row address strobe signal {overscore (RAS)} is activated, the row main decoder  35  can activate the word line enable signal NWEi immediately upon activation of the internal master signal PR and, optionally, the enable signal PNBLS. As discussed hereinabove with respect to FIGS. 1 and 2, conventional integrated circuit memory devices may delay activation of the enable signal PNBLS with respect to activation of the internal master signal PR by a predetermined time tF to provide the row predecoder  11  with time to generate the predecoded row address DRAij. Accordingly, address decoding speed may be improved thereby facilitating higher speed operation of the integrated circuit memory device. 
     As will be appreciated by those skilled in the art, the foregoing principles and concepts may also be applied to decoding a column address. For example, the row address RAi may be a column address, the row predecoder  31  may be a column predecoder, the row main decoder  35  may be a column main decoder, and the word line enable signal NWEi may be a bit line enable signal. 
     Referring now to FIG. 4, the row predecoder  31  is illustrated in greater detail. The row predecoder  31  preferably comprises one or more unit predecoders  41 ,  43 , and  45 , which predecode row address bits RA[ 0 : 1 ], RA[ 2 : 4 ], and RA[ 5 : 6 ], respectively. The unit predecoders  41 ,  43 , and  45  latch the predecoded row address signals DRA 01 &lt; 0 : 3 &gt;, DRA 234 &lt; 0 : 7 &gt;, and DRA 56 &lt; 0 : 3 &gt;, respectively, during the deactivated state of both the row address strobe signal {overscore (RAS)} (logic 1 level) and the internal master signal PR (logic 0 level). Three unit predecoders  41 ,  43 , and  45  are shown in FIG. 4 because seven bits are used for the row address RAi. In this example, the number of unit predecoders may range from one to three. 
     A preferred embodiment of the unit predecoder  41  is shown in FIG.  5 . The remaining unit predecoders  43  and  45  may be embodied in like fashion. Note, however, that the unit predecoder  43  receives three row address bits RA[ 2 : 4 ] instead of two row address bits like the unit predecoders  41  and  45  and generates an eight bit predecoded row address signal DRA 234 &lt; 0 : 7 &gt;. The unit predecoder  41  includes a plurality of NAND gates (ND 1  and ND 2 ), transmission gates (T 1  and T 2 ), and latches (L 1  and L 2 ). NAND gate ND 1  receives supplementary bits RA 0 B and RA 1 D as inputs, where RAiB corresponds to the complement of RAi. The transmission gate T 1  transmits the output of the NAND gate ND 1  during the deactivated state of both the row address strobe signal {overscore (RAS)} (logic 1 level) and the internal master signal PR (logic 0 level). The latch L 1  latches the output of the transmission gate T 1  and outputs the predecoded row address bit DRA 01 &lt; 0 &gt;. 
     NAND gate ND 2  receives row address bits RAO and RAI as inputs. The transmission gate T 2  transmits the output of the NAND gate ND 2  during the deactivated state of both the row address strobe signal {overscore (RAS)} (logic 1 level) and the internal master signal PR (logic 0 level). The latch L 2  latches the output of the transmission gate T 2  and outputs the predecoded row address bit DRA 01 &lt; 3 &gt;. 
     In other words, the unit predecoder  41  predecodes row address bits RA[ 0 : 1 ] during the deactivated state of both the row address strobe signal {overscore (RAS)} (logic 1 level) and the internal master signal PR (logic 0 level) and latches the corresponding predecoded row address bits DRA 01 &lt; 0 : 3 &gt;. 
     As illustrated in FIGS. 3,  4 , and  7 , the row predecoder  31  is active while the internal master signal PR is in a logic 0 state. That is, the transmission gates T 1 , T 2 , . . . Ti allow a predecoded row address DRAij to propagate through to the latches L 1 , L 2 , . . . Li. When the internal master signal PR transitions from the logic 0 state to the logic 1 state, however, the row predecoder  31  switches from an active state to an inactive state. That is, the transmission gates Ti, T 2 , . . . Ti prevent a predecoded row address DRAij from propagating through to the latches L 1 , L 2 , . . . .Li. 
     A preferred embodiment of the row main decoder  35  is shown in FIG.  6 . The row main decoder  35  includes a PMOS precharge transistor P 1  electrically connected between a reference potential VDD and the input terminal of a latch L 3  at node N. The transistor P 1  may precharge node N to the reference potential VDD in response to a control signal PDPX applied to its gate terminal. The row main decoder  35  further includes a plurality of NMOS transistors N 1 , N 2 , N 3 , and N 4  connected in series between the node N and a ground reference potential VSS. The latch L 3  comprises two inverters I 5  and I 6  configured as shown, which latch the inverse of the voltage level at node N for output as the word line enable signal NWEi. 
     The predecoded row address bits DRAij are applied to the gates of the NMOS transistors N 1  through N 4  as follows: DRA 01 &lt;i&gt;, i=0 through 3 are applied to the gate of the NMOS transistor N 1 ; DRA 234 &lt;i&gt;, i=0 through 7 are applied to the gate of the NMOS transistor N 2 ; and DRA 56 &lt;i&gt;, i=0 through 3 are applied to the gate of the NMOS transistor N 3 . The internal master signal PR or, optionally, the enable signal PNBLS is applied to the gate of the NMOS transistor N 4 . 
     Operations of the row main decoder  35  will now be described. When the enable signal PNBLS is activated to a logic 1 level and the predecoded row addresses DRA 01 &lt;i&gt;, DRA 234 &lt;i&gt;, and DRA 56 &lt;i&gt;are activated to a logic 1 level by the row predecoder  31 , the NMOS transistors N 1  through N 4  are turned on and the node N is pulled to the reference potential VSS, which corresponds to a logic 0 level. As a result, the output of the latch L 3 , which is the word line enable signal NWEi, is activated to a logic 1 level. 
     As illustrated in FIGS. 3,  6 , and  7 , the row main decoder  31  is inactive while the internal master signal PR is in a logic 0 state. That is, the NMOS transistor N 4  is turned off and prevents the latch L 3  from activating the word line enable signal NWEi. When the internal master signal PR transitions from the logic 0 state to the logic 1 state, however, the row predecoder  31  switches from an inactive state to an active state. That is, the NMOS transistor N 4  is turned on, which allows the latch L 3  to activate the word line enable signal based on the predecoded row address bits DRAij applied to the NMOS transistors N 1 , N 2 , and N 3 . 
     Thus, opposite states of the internal master signal PR trigger the row predecoder  31  and the row main decoder  35 , which may prevent a new predecoded row address DRAij from being input to the row main decoder  35  before a previous predecoded row address DRAij has been decoded. 
     The principles of the present invention have been described herein in connection with row address decoding in an integrated circuit memory device. From the foregoing it can readily be seen that the present invention may allow predecoding of the row address RAi during the inactive state of both the row address strobe signal {overscore (RAS)} and the internal master signal PR. Because the predecoded row address DRAij is already available when the row address strobe signal {overscore (RAS)} is activated, the row main decoder  35  can activate the word line enable signal NWEi immediately upon activation of the internal master signal PR and, optionally, the enable signal PNBLS. Accordingly, address decoding speed may be improved thereby facilitating higher speed operation of the integrated circuit memory device. 
     In concluding the detailed description, it should be noted that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention. All such variations and modifications are intended to be included herein within the scope of the present invention, as set forth in the following claims.