Abstract:
I claim a device and method for reducing current consumption. The device including a memory cell array having a first region to store normal data and a second region to store both normal data and parity data associated with error correction functionality, and a refresh control unit to perform refresh operations on the memory cell array, the refresh control unit adapted to adjust a cycle associated with the performance of the refresh operations responsive to the storage of normal data in the second region.

Description:
RELATED APPLICATIONS  
       [0001]     This patent application claims priority from Korean Patent Application 10-2005-117842, filed on Dec. 6, 2005, which we incorporate by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates, generally, to memory devices and, more particularly, to a memory device and method for reducing refresh current consumption.  
         [0004]     2. Description of the Related Art  
         [0005]     In memory devices, such as a Dynamic Random Access Memory (DRAM), memory cells may degrade over time, e.g., through the degradation of a dielectric layer, the introduction of foreign particles, etc. This memory cell degradation may cause the memory cells to store data incorrectly, thus contributing to memory device failure. To help overcome memory cell degradation, memory devices may include error correction code (ECC) functionality or circuits to detect and correct errors in stored data. For instance, an ECC circuit may generate parity data according to data to be stored by the memory cells, and then store the parity data in a parity memory portion of the memory device. During data retrieval operations, the memory device may use the parity data to detect and correct errors in data retrieved from the memory cells.  
         [0006]      FIG. 1  shows a conventional memory device including a parity memory region  10  and a normal memory region  20 . The conventional memory device stores normal data NDAT in the normal memory region  20  and parity data PDAT in the parity memory region  10 . That is, the memory device only stores parity data PDAT in the parity memory region  10 , which maintains ECC functionality of the memory device. The parity memory region  10  typically is about half the size of the normal memory region  20 . Since the conventional memory device allocates a significant portion of the memory cells to exclusively store parity data PDAT, the capacity of the memory device to store normal data NDAT is reduced.  
         [0007]     Memory devices, such as a DRAM, also execute refresh operations to effectively preserve data stored in the memory cells. These refresh operations, however, consume a large amount or current due to the switching of transistors embedded in the memory device. Particularly, when a refresh operation is executed during each cycle in standby mode or power down mode of the memory device, the current consumption for the refresh operation accounts for a large portion of the total current consumption by the memory device.  
         [0008]     To decrease current consumption, memory devices may control the refresh operation cycle. Since ECC functionality can correct improperly stored or preserved data, memory devices that include ECC circuits may lengthen their refresh operation cycles and thus decrease the current consumption.  
       SUMMARY OF THE INVENTION  
       [0009]     Embodiments of the present invention provide a memory device and method to reduce current consumption in the refresh operations. The device including a memory cell array having a first region to store normal data and a second region to store both normal data and parity data associated with error correction functionality, and a refresh control unit to perform refresh operations on the memory cell array, the refresh control unit adapted to adjust a cycle associated with the performance of the refresh operations responsive to the storage of normal data in the second region. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]     The features and advantages of the present invention will be more apparent with the detailed description of exemplary embodiments referencing the attached drawings.  
         [0011]      FIG. 1  is a diagram showing a conventional memory device.  
         [0012]      FIG. 2  is a block diagram showing a memory device useful with embodiments of the present invention.  
         [0013]      FIG. 3  is a block diagram showing example embodiments of the memory cell array shown in  FIG. 2 .  
         [0014]      FIGS. 4A-4C  are block diagrams showing other example embodiments of the memory cell array shown in  FIG. 2 .  
         [0015]      FIG. 5  is a flowchart example for the operation of the memory device shown in  FIG. 2 .  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]      FIG. 2  is a block diagram showing a memory device useful with embodiments of the present invention. Referring to  FIG. 2 , the memory device includes a memory cell array  100 , an error correction control unit  200 , a refresh control unit  300 , a DQ pad  400 , a data transfer unit  500 , and a command control unit  600 .  
         [0017]     The memory cell array  100  includes a normal memory region  110  and a parity memory region  120 . The normal memory region  110  and the parity memory region  120  may be allocated according to a command CMD. The command CMD may include or identify region dividing information RGCON used by the memory device to divide the memory cell array  100  into the normal memory region  110  and the parity memory region  120 . The command CMD may be provided to the command control unit  600  from one or more systems internal or external to the memory device.  
         [0018]     The normal memory region  110  may store normal data NDAT that is input/output via the DQ pad  400  and the data transfer unit  500 . The parity data PDAT may have a logic state associated with a bit combination of normal data NDAT.  
         [0019]     The error correction control unit  200  is adapted to generate parity data PDAT according to at least one bit combination of normal data NDAT to be stored to the memory cell array  100 . The error correction control unit  200  may generate the parity data PDAT during normal data storage operations via the data transfer unit  500 . The error correction control unit  200  is adapted to detect and correct the normal data NDAT according to the parity data PDAT. The error correction control unit  200  may also detect and correct the normal data NDAT during normal data retrieval operations via the data transfer unit  500 .  
         [0020]     The refresh control unit  300  is adapted to perform refresh operations for the memory cell array  100 . The refresh control unit  300  includes a refresh address generating means  310  and a refresh operating means  320 . The refresh address generating means  310  generates a refresh address FADD in response to a refresh control signal REF. The refresh control signal REF may be provided by the command control unit  600  or another source internal or external to the memory device.  
         [0021]     The refresh operating means  320  is adapted to refresh the memory cells of the memory array  100  according to the refresh address FADD. The refresh control unit  300  may cyclically perform refresh operations according to a first cycle when the normal data NDAT is stored in the parity memory region  120  of the memory cell array  100 . The refresh control unit may cyclically perform refresh operations according to a second cycle when the normal data NDAT is not stored in the parity memory region  120  of the memory cell array  100 . The second cycle may have a greater period or duration between refresh operations than the first cycle.  
         [0022]     The command control unit  600  is adapted to control the error correction unit  200  and the refresh control unit  300  responsive to one or more external commands CMD. The external commands CMD may include region dividing information RGCON indicating the portions of the memory cell array  100  that correspond to the normal memory region  110  and the parity memory region  120 . The memory device may divide the memory cell array  100  into the normal memory region  110  and the parity memory region  120  responsive to the region dividing information RGCON. The external command CMD may also include the information to identify whether the parity memory region  120  is capable of storing normal data NDAT.  
         [0023]      FIG. 3  is a block diagram showing example embodiments of the memory cell array  100  shown in  FIG. 2 . Referring to  FIG. 3 , the normal memory region  110  may store the normal data NDAT, and the parity memory region  120  may store the parity data PDAT. The parity memory region  120  may also store the normal data NDAT.  
         [0024]     The memory device may refresh the memory cell array  100  according to a refresh cycle that may be dependent on the storage location of the normal data NDAT. For instance, when normal data NDAT is stored in the parity memory region  120 , the memory device may execute refresh operations according to a first cycle, and when normal data NDAT is not stored in the parity memory region  120 , the memory device may execute refresh operations according to a second cycle. Since the first cycle may be shorter than the second cycle, the memory device may reduce data loss associated with the first cycle and decrease current consumption associated with the second cycle. The storage of normal data NDAT in the parity memory region  120  may be monitored internally be the memory device, or by one or more external systems.  
         [0025]     The memory device may prioritize the storage of normal data NDAT to the memory cell array  100 . For instance, the parity memory region  120  may have the lowest priority for storing normal data NDAT. That is, when the normal memory region  110  is full or cannot store any more normal data NDAT, the parity memory region  120  may then be used to store normal data NDAT. This may allow the memory device to enable ECC functionality without decreasing the overall storage capacity of the memory device.  
         [0026]      FIGS. 4A-4C  are block diagrams showing other example embodiments of the memory cell array shown in  FIG. 2 . Referring to  FIGS. 4A-4C , the memory cell array  100  includes a plurality of memory banks BANK A—BANK D. The memory cell array  100  may be divided into one or more normal memory regions  110  and one or more parity memory regions  120 . For instance, in  FIG. 4A , each memory bank BANK A—BANK D is divided into a parity memory region  120 A- 120 D and a normal memory region  110 A- 110 D. In  FIG. 4B , the memory device may allocate one of the memory banks, e.g., BANK D, as the parity memory region  120 D. In  FIG. 4C , the memory device may allocate two or more of the memory banks, e.g., BANK C and BANK D, as the parity memory region  120 C- 120 D.  
         [0027]      FIG. 5  is a flowchart example for the operation of the memory device shown in  FIG. 2 . In block S 10 , the normal memory region  110  and the parity memory region  120  are assigned in the memory cell array  100 . The parity memory region  120  may have the lowest priority for storing normal data NDAT. The memory device may divide the memory cell array  100  into the normal memory region  110  and the parity memory region  120  responsive to one or more external commands CMD.  
         [0028]     In block S 20 , the memory device enters into a self refresh operation mode. In some embodiments, the memory device may enter the self refresh mode from a standby mode or power down mode.  
         [0029]     In block S 30 , the memory device determines whether normal data NDAT is stored in the parity memory region  120 . When normal data NDAT is stored in the parity memory region  120 , in block S 40 , the memory device performs one or more refresh operations on the memory cell array  100  according to a first cycle. When normal data NDAT is not stored in the parity memory region  120 , in block S 50 , the memory device performs one or more refresh operations on the memory cell array  100  according to a second cycle. The first cycle may have a shorter period than the second cycle. In other words, the memory device may perform refresh operations with a greater frequency according to the first cycle than the second cycle.  
         [0030]     In block S 60 , the memory device releases self refresh operation mode. In some embodiments the memory device may also exit from a standby mode or a power down mode. Accordingly the memory device may reduce the refresh current consumption without decreasing the storage capacity of the memory device.  
         [0031]     The scope of the prevent invention can be extended to various data types and operation modes. In some embodiments, the normal and parity memory regions may be called as first and second memory regions, respectively, while the refresh operations associated with a first cycle may be called ‘first mode’ and the refresh operations associated with a second cycle may be called ‘second mode.’ 
         [0032]     Although embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.