Abstract:
A classical differential amplifier provides outputs of unequal magnitude due to its emitter resistance being finite. In order to equalize its output, a voltage follower circuit is associated with each of the inputs of the differential amplifier. The output of each voltage follower circuit is converted to a current and subtracted from one of the outputs of the differential amplifier. Subtracting the outputs results in a differential amplifier with both outputs being substantially equal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates generally to differential amplifiers and, in particular, to amplifiers providing balanced, or equal and opposite outputs when one input is driven. 
     2. Description of the Prior Art 
     Conventional differential amplifiers as illustrated in FIG. 1, do not produce equal amplitude outputs when one input is driven and the other input is AC grounded. Specifically, differential amplifier DA, having gain K, as inputs 13 and 16 and outputs 14 and 15. Input 12 is coupled 15 to a voltage generator providing a voltage V in  and output 13 is grounded through capacitor 16. Inputs 12 and 13 are also properly DC biased. As a result, the voltage available at output 14 is equal to [K/(1+d)]V in  and the voltage available at output 15 is equal to -KV in . Therefore, noninverted ouptput 14 has a magnitude which is less by amount KdV in  /(1+d) than the magnitude of inverted output 15. 
     FIG. 2 illustrates a circuit diagram for a conventional differential amplifier. In general, a voltage V in  is applied to the base of transistor Q11 and the base of the transistor Q12 is grounded through bypass capacitor C BP . In this configuration transistor Q12 functions as a common-base amplifier and transistor Q11 functions as a voltage follower. Considering the emitter of transistor Q12 as AC grounded, the gain G11 of stage 11 including transistor Q11 is related to the collector impedance which is equal to resistor R c1 , and the emitter impedance which is equal to the series combination of emitter resistance R e1  and the parallel combination of resistor R e2  and resistor R cm  where R e1  =R e2  =R e . Therefore, the gain G 11  of stage 11 is given by formula 1 (see FIG. 4) where the parallel combination of emitter resistor R e2  and resistor R cm  is given by formula 2. Substituting formula 2 into formula 1 illustrates that gain G 11  of stage 11 is equal to the ratio of ##EQU1## since transistor Q12 is a common-base stage (see formula 3). As the value of resistor R cm  approaches infinity, gain G 11  approaches -R c  /2R e . Therefore, resistor R cm , due to its parallel relationship with resistor R e2 , causes gain G 11  to be greater than this limit value. 
     This must be compared with the gain of stage 12. Stage 12 includes transistor Q12 in a common base mode with the emitter functioning as a summing junction. Thus, all currents into the emitter will be summed and appear at the collector. When considering transistor Q12, transistor Q11 is regarded as a voltage follower with the emitter resistors converting the emitter voltage of transistor Q11 into a current for application to the emitter of transistor Q12. The emitter current I e  (Q11) of transistor Q11 is as shown in formula 4. However, not all of this current reaches the emitter of transistor Q12 because some of the current is shunted to ground by resistor R cm . As a result, the current I e  (Q12) into the emitter of transistor Q12 is shown by formula 5. As shown in formula 6, this reduces current I e  (Q11) applied to the emitter of Q12 and, therefore, the gain of G 12  is reduced by an amount equal to R e  /(R e  +R cm ). The conclusion is that the magnitude of gain G 11  in stage 11 is always greater than the magnitude of gain G 12  through stage 12 as illustrated in formula 7. 
     Another conventional configuration of a differential amplifier is shown in FIG. 3. Following a similar pattern of analysis as indicated above with regard to FIG. 2, gain G 21  for stage 21 including transistor Q21 is shown by formula 8 and gain G 22  for stage 22 including transistor Q22 is shown by formula 9. Once again, the magnitude of gain G 21  of stage 21 is greater than the magnitude of the gain G 22  of stage 22. 
     In the classical circuits illustrated in FIGS. 2 and 3, the additional gain to the V 0  -output stage is due to an extra emitter current component. The additional emitter current component of the circuit in FIG. 2 is due to the emitter resistor R cm , while the additional emitter current component in the circuit in FIG. 3 is due to resistor R b1 . To eliminate these components, resistor R cm , R b1  and R b2  must become infinitely large. However, this is very difficult to achieve at high frequencies such as frequencies in the range of 300 MHz. 
     SUMMARY OF THE INVENTION 
     It is an object of this invention to provide a differential amplifier having outputs which are substantially equal in magnitude. 
     The invention comprises an apparatus including a differential amplifier having gain K, with first and second inputs and first and second outputs. A first voltage follower circuit is associated with the first input of the differential amplifier, the first circuit having an output. A second voltage follower circuit is associated with the second input of the differential amplifier, the second circuit having an output. First means for summing has inputs associated with the first output of the amplifier and the output of the second circuit, and has an output providing a voltage substantially representing the sum of the outputs associated with the inputs of the first means. Second means for summing has inputs associated with the second output of the amplifier and the output of the first circuit, and has an output providing a voltage substantially representing to the sum of the outputs associated with the inputs of the second means. Grounding the first input of the amplifier and applying a positive voltage V to the second input results in the output of the first means providing a voltage substantially equal to the output of the second means. 
     For a better understanding of the present invention, together with other and further objects, reference is made to the following description, taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a differential amplifier according to the prior art. 
     FIG. 2 is a schematic diagram of a conventional differential amplifier according to the prior art. 
     FIG. 3 is a schematic diagram of another conventional differential amplifier according to the prior art. 
     FIG. 4 is a table of the formula representing the analysis of FIGS. 2 and 3. 
     FIG. 5 is a block diagram of a differential amplifier according to the invention. 
     FIG. 6 is a schematic diagram of a differential amplifier according to the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     As illustrated in FIG. 5, the differential amplifier 50 according to the invention includes a prior art differential current amplifier 100. Amplifier 100 has a first output port 101 which provides a current equal to +V in  /R e  and a second output port 102 providing current (-V in  /Re)(1+R e  /R b ). Therefore, as shown above in the analysis of the classical circuits illustrated in the FIGS. 1-3, the gain at output port 102 is greater than the gain at output port 101. 
     Voltage follower circuit 200 is associated with input 103 of current amplifier 100 and has an output 201 which provides a voltage to current converter 202 which converts the voltage into a current equal to V in  /R ccl . This current is applied to current summer 500 for summing with the output current from output port 102. Similarly, voltage follower circuit 300 is associated with input 104 of current amplifier 100 and has an output 301 which provides a voltage to current converter 302 which converts the voltage into a current which is summed by current summer 400 with the output current from output port 101. 
     When a voltage such as voltage V in  is applied to input 103 and input 104 is grounded through bypass capacitor 105, voltage follower 200 provides a voltage at output 201 equal to V in  to converter 202. Since input 104 is AC grounded, output 301 of voltage follower circuit 300 is zero. Essentially, voltage follower 300 is included so that differential amplifier 50 is a symmetrical network and a voltage can be applied to either input 51 or input 52. Output 401 of current summer 400 provides a current equivalent to the voltage supplied by output 301 of converter 302 (which is zero in the FIG. 5 circuit) added to the current supplied by output 101 of current amplifier 100 (which is +V in  /R e  in the FIG. 5 circuit). Output 401 of summer 400 provides a current to converter 402 which converts the current into a voltage equal to V in  R c  /R e . Similarly, current summer 500 sums the currents provided by output 102 (-V in  /R e )(1+R e  /Rb) and the output of converter 202 (V in  /R b ) so that output 501 provides a current to converter 502 which converts the current into a voltage equal to -V in  R c  /R e . (This implies R b  equals R c . However, FIG. 5 illustrates a first order approximation. Secondary and tertiary terms which modify R c  result in R b  =R c .) As a result, the output voltage at output port 53 of amplifier 50 is substantially equal and opposite to the output voltage at output port 54 of amplifier 50. 
     FIG. 6 illustrates a schematic diagram for the differential amplifier of FIG. 5. Summers 400 and 500 include transistors Q33 and Q34, respectively, which are common-base stages used as current summers. Voltage follower circuits 200 and 300 include transistors Q35 and Q36 with emitters which are DC biased through resistors R a1  and R a2 , respectively, which are voltage followers duplicating the voltage follower role of transistors Q32 and Q31, respectively, of current amplifier 100. The DC quiescent condition of voltage follower circuits 200 and 300, including transistors Q35 and Q36, respectively, is maintained as closely as possible to the quiescent condition for transistors Q32 and Q31, respectively, of current amplifier 100. In this way, these four transistors will have the best matched AC performance. The voltage supplied at output 201 of voltage follower 200 is applied to converter 202 (i.e. compensating resistor R cc1 ) which converts the voltage to an equivalent current for summation by current summer 500 along with the current provided by output 102 of current amplifier 100. The voltage supplied at output 301 of voltage follower 300 is applied to converter 302 (i.e. compensating resistor R c2 ) which converts the voltage to an equivalent current for summation by current summer 500 along with the current provided by output 101 of current amplifier 100. 
     Compensation resistors R cc1  and R cc2  are used to reduce the gain of transistors Q31 and Q32, respectively, of amplifier 100 so that it is equal to the gain of transistors Q32 and Q31, respectively. The extra gain of transistor Q31, as pointed out above, is due to biasing resistor R b2 . When the base of transistor Q31 goes high, a current component equal to V in  /R b2  is created causing the collector current of transistor Q31 to increase. To offset this AC current component, current is supplied from transistor Q35 through R c1  to diminish the AC emitter current of transistor Q34. This effectively lowers the gain of transistor Q31 without affecting the gain of transistor Q32. When the input voltage V in  is applied to input 52 and input 51 is capacitively grounded, the extra gain of transistor Q32 is due to biasing resistor R b1  and compensating resistor R cc2  diminishes the emitter current of transistor Q32. 
     Compensation resistor R cc1  should have a value equal to resistor R b2  and R cc2  should equal R b1 . This would cause total cancellation. However, at high frequencies, the current-transfer ratios of transistors Q31 and Q32 decrease and the simplifying assumptions become less valid. 
     The circuit of FIG. 5 was computer analyzed at 300 MHz with the use of a circuit simulation software package. In an iterative analysis, compensation resistor R c1  was found to be somewhat less than resistor R b2 . This is due to the more comprehensive modeling available in computer simulation which accurately predicts performance better than manual calculations using simplifying assumptions. 
     The results of simulation analysis indicate that a differential amplifier which is more perfect than the conventional differential amplifier can be achieved. Circuit performance will produce complementary outputs with amplitudes within 0.1 db of each other. In addition, frequency response is symmetrical at frequencies less than 450 MHz. 
     One embodiment of the differential amplifier invention may be as part of an unpackaged monolithic large scale integrated microcircuit chip. Such a chip may function to transfer signals from surface acoustic wave delay line taps to either of two summing buses in accordance with coded data input control signals. The chip would also differentially add the two summing bus output signals and provide in-phase and out-of-phase output signals of this addition. For example, such a chip may be used to switch 32 independent RF inputs to one of two summing buses (A or B) in accordance with the data information input to a shift register of the chip. The explicit operation is as follows for any RF input: if Q n  is high, then signal RF n  is switched to bus A; if, however, Q n  is low, then RF n  is switched to bus B. The input data may be serially shifted into a 32 bit static serial in, serial out/parallel out register by the positive edge of clock. All external input/output signals are TTL compatable. The parallel outputs are connected to switch control latches which are loaded on the high level of a transfer pulse. The Q inputs and Q outputs of the switch control latches operate the RF switches. 
     Such an arrangement is possible because (1) the switching transistors of the invention are grounded base stages and the RF operating frequency of the IC transfer chip is in the range of 60 to 300 MHz; and (2) the impedance of the RF source is very high compared to the input impedance of the grounded base stages (which is required to be 125 ohms or less, essentially resistive). The two summing bus signals may be differentially added at the output side of the chip to supply in-phase and out-of-phase output signals of the resultant. 
     While there have been described what are at present considered to be the preferred embodiments of this invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention and it is, therefore, aimed to cover all such changes and modifications as fall within the true spirit and scope of the invention.