Abstract:
A 2&#39;s complementer having a simple circuit arrangement and yet obtaining a high 2&#39;s-complementation rate. The 2&#39;s complementer includes an inverting circuit for inverting binary data with at least two bits to produce an 1&#39;s complement. The 2&#39;s complementer also includes an inverter for inverting inverted data resulted from an inversion of the least-significant bit of the 1&#39;s-complement data of at least two bits, and at least one exclusive OR gate for comparing bit data to be currently processed with lower-order bit data of at least one bit of the 1&#39;s-complement data, and inverting the current bit data when the at least one lower-order bit data has the value of logic-1.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a complementation device employed in an operator part of a digital information processing system, and more particularly to a 2&#39;s complementer having a simple circuit arrangement and yet obtaining a high complementation rate. 
     2. Description of the Prior Art 
     Generally, a digital information processing system includes an operator part for performing four basic arithmetic operations, i.e., addition, substraction, multiplication, and division, according to the rules of the addition. For the substraction and division operation, the operator part derives complement of a subtrahend to be added to a minuend and complement of a divisor to be added to a dividend. 
     As such complements, there are 1&#39;s complements and 2&#39;s complements. The 2&#39;s complements are mainly used because they can simplify the process of the substraction and division, as compared to the 1&#39;s complements. Such 2&#39;s complements are derived by taking the 1&#39;s complements of binary data by bits and then adding &#34;1&#34; to each of the 1&#39;s complements. Otherwise, 2&#39;s complements may be derived by inverting higher-order bits of binary data than the first one of bits having the value of logic-1 on an order-by-order basis starting with the least-significant bit (LSB) and ending with the most-significant bit (MSB). The first method have been hardly used because of its troublesome operation involving the addition of &#34;1&#34; after deriving of 1&#39;s complements. The second method have been mainly used because it enables a simple circuit arrangement to be constructed and a rapid operation rate to be obtained. 
     However, existing 2&#39;s complementers utilizing the second method encounter problems that the circuit arrangement becomes more complex and the complement driving rate is gradually reduced as the number of bits of the data to be complemented is increased. This is because the second method is performed on an order-by-order basis starting with the LSB and ending with the MSB. These problems encountered in the conventional 2&#39;s complementers utilizing the second method will be described in detail, in conjunction with FIG. 1. 
     FIG. 1 is a circuit diagram of a conventional 2&#39; complementer. As shown in FIG. 1, the 2&#39; complementer includes four exclusive OR gates 10, 12, 14 and 16 for receiving binary data of 4 bits respectively applied to four input lines 11, 13, 15 and 17, and four AND gates 18, 20, 22 and 24 for receiving an enable signal EN from a control line 19 in common. The first AND gate 18 performs the AND operation between the enable signal EN and a carry signal received from a fifth input line 21. For a complementation, the enable signal EN has the high logic value. The first exclusive OR gate 10 outputs the value of logic-0 to the first output line 23 when LSB data from the first input line 11 has the same logic value as the output from the first AND gate 18. On the contrary, when LSB data from the first input line 11 has a different logic value from the output from the first AND gate 18, the first exclusive OR gate 10 outputs the value of logic-1 to the first output line 23. As a result, the first exclusive OR gate 10 inverts the LSB data when the carry signal has the value of logic-1. On the contrary, when the carry signal has the value of logic-0, the first exclusive OR gate 10 sends the LSB signal, as it is, to the first output line 23. 
     This 2&#39;s complementer further includes a first OR gate 26 for performing the OR operation between the LSB data from the first input line 11 and the carry signal from the fifth input line 21, a second OR gate 28 for performing the OR operation between the second LSB data from the second input line 13 and the output signal from the first OR gate 26, and a third OR gate 30 for performing the OR operation between the second MSB data from the third input line 15 and the output signal from the second OR gate 28. 
     The second AND gate 20 performs the AND operation between the enable signal EN and the output signal from the first OR gate 26 and supplies the result of the AND operation to the second exclusive OR gate 12. The second exclusive OR gate 12 then compares the output signal from the second AND gate 20 with the second LSB data and supplies the result of the comparison to the second output line 25. When the output signal from the first OR gate 26 has the value of logic-1, the data sent to the second output line 25 has the same logic value as the inverted second LSB data. On the contrary, the data on the second output line 25 has the same logic value as the second LSB data when the output signal from the first OR gate 26 has the value of logic-0. 
     The third AND gate 22 performs the AND operation between the enable signal EN and the output signal from the second OR gate 28 and supplies the result of the AND operation to the third exclusive OR gate 14. In similar, the fourth AND gate 24 performs the AND operation between the enable signal EN and the output signal from the third OR gate 30 and supplies the result of the AND operation to the fourth exclusive OR gate 16. In similar to the second exclusive OR gate 12, the third exclusive OR gate 14 applies to the third output line 27 the inverted second MSB data or the second MSB data, based on the logic value of the output signal from the second OR gate 28. In similar to the third exclusive OR gate 14, the fourth exclusive OR gate 16 applies to the third output line 27 the inverted MSB data or the MSB data, based on the logic value of the output signal from the third OR gate 30. 
     In actual, where the 2&#39;s complementer receives data having logic values of 0, 0, 1 and 0 via the first to fourth input lines 11, 13, 15 and 17, it generates 2&#39;s-complement data having logic values of 1, 1, 1 and 0. 
     However, since the conventional 2&#39;s complementer operates binary data from LSB data to MSB data in a sequential manner, the complementation rate is lowered as the number of bits of the data to be complemented is increased. Furthermore, the conventional 2&#39;s complementer encounters the problem that the circuit thereof becomes more complex as the number of bits of the data to be complemented is increased. 
     SUMMARY OF THE INVENTION 
     Therefore, an object of the invention is to provide a 2&#39;s complementer having a simple circuit arrangement and yet obtaining a high complementation rate. 
     In accordance with the present invention, this object can be accomplished by providing a 2&#39;s complementer comprising an inverting circuit for inverting binary data with at least two bits to produce an 1&#39;s complement, inverting means for inverting inverted data resulted from an inversion of the least-significant bit of said 1&#39;s-complement data of at least two bits; and at least one comparing means for comparing bit data to be currently processed with lower-order bit data of at least one bit of the 1&#39;s-complement data, and inverting said current bit data when said at least one lower-order bit data has a predetermined logic. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the invention will become more apparent upon a reading of the following detailed specification and drawings, in which: 
     FIG. 1 is a circuit diagram of a conventional 2&#39; complementer; 
     FIG. 2 is a block diagram of a 2&#39;s complementer in accordance with the present invention; 
     FIG. 3 is a circuit diagram of an increment signal generator shown in FIG. 2; 
     FIG. 4 is a circuit diagram of one of conditional incrementers shown in FIG. 2 in accordance with a first embodiment of the present invention; 
     FIG. 5 is a circuit diagram of one of conditional incrementers shown in FIG. 2 in accordance with a second embodiment of the present invention; and 
     FIG. 6 is a table illustrating complementary speeds, namely, complementation rates and the number of transistors required per bit for complementation in the conventional 2&#39;s complementer and 2&#39;s complementers respectively including conditional incrementers according to the first and second embodiments of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2 is a block diagram of a 2&#39;s complementer in accordance with the present invention. As shown in FIG. 2, the 2&#39;s complementer of the present invention includes an increment signal generator 32 for receiving an enable signal EN and 12 inverted data bits /a 0  to /a 11  from three input lines 33, 35 and 37. The increment signal generator 32 combines the received enable signal EN and the 12 inverted data bits /a 0  to /a 11  with one another and thereby generates four increment signals inc 1  to inc 4 . 
     In accordance with the present invention, the 2&#39;s complementer further includes four conditional incrementers 34, 36, 38 and 40 respectively receiving the increment signals inc 1  to inc 4  from the increment signal generator 32. When the first increment signal inc 1  from the increment signal generator 32 has the high logic value, the first conditional incrementer 34 adds &#34;1&#34; to each of the 4 inverted data bits /a 0  to /a 3  received from the first input line 33 and thereby outputs the resultant added inverted data of 4 bits via the first output line 41. On the contrary, the first conditional incrementer 34 outputs the 4 inverted data bits /a 0  to /a 3  received from the first input line 33, as they are, to the first output line 41 when the first increment signal inc 1  from the increment signal generator 32 has the low logic value. 
     The second to fourth conditional incrementers 36, 38 and 40 operate in a similar manner as the first conditional incrementer 34. The second conditional incrementer 36 receives the second increment signal inc 2  from the increment signal generator 32 and the four inverted data bits /a 4  to /a 7  from the second input line 35. The third conditional incrementer 38 receives the third increment signal inc 3  from the increment signal generator 32 and the four inverted data bits /a 8  to /a 11  from the third input line 37. On the other hand, the fourth conditional incrementer 36 receives the fourth increment signal inc 4  from the increment signal generator 32 and four inverted data bits /a 12  to /a 15  from the fourth input line 39. The second to fourth conditional incrementers 36, 38 and 40 send, by four bits, the inverted data bits /a 4  to /a 15 , as they are, or inverted data bits each resulted from the addition of &#34;1&#34; to each of the inverted data bits /a 4  to /a 15 , to the second to fourth output lines 43, 45 and 47, respectively. The 16 inverted data bits /a 0  to /a 15  inputted at the first to fourth input lines 33, 35, 37 and 39 are 1&#39;s complements of 16 data bits a 0  to a 15  and generated from an inverting circuit not shown. For simplicity of the illustration, this inverting circuit is not shown in FIG. 2. 
     FIG. 3 is a circuit diagram of the logic of the increment signal generator 32 shown in FIG. 2. As shown in FIG. 3, the increment signal generator 32 includes a buffer 42 adapted to receive an enable signal EN from a control line 31, and three AND gates 44, 46 and 48 respectively coupled to the input lines 33, 35 and 37. The buffer 42 buffers the enable signal EN received from the control line 31 and applies the buffered enable signal EN as the first increment signal inc 1  to the first conditional incrementer 34 shown in FIG. 2. The first AND gate 44 performs the AND operation among the inverted data /a 0  to /a 3  of 4 bits received from the first input line 33. The second AND gate 46 performs the AND operation among the inverted data /a 4  to /a 7  of 4 bits received from the second input line 35. In similar to the first and second AND gates 44 and 46, the third AND gate 48 performs the AND operation among the inverted data /a 8  to /a 11  of 4 bits received from the third input line 37. 
     The increment signal generator 32 further includes fourth to sixth AND gates 50, 52 and 54 all adapted to receive the enable signal EN from the control line 31 in common. The fourth AND gate 50 performs the AND operation between the enable signal EN and the output signal from the first AND gate 44 and sends the result of the AND operation as the second increment signal inc 2  to the second conditional incrementer 36 shown in FIG. 2. In other words, the fourth AND gate 50 ANDs the enable signal EN and the 4 inverted data bits /a 0  to /a 3  and supplies the result of the AND operation to the second conditional incrementer 36. 
     The fifth AND gate 52 performs the AND operation among the enable signal EN and the output signals from the first and second AND gates 44 and 46 and sends the result of the AND operation as the third increment signal inc 3  to the third conditional incrementer 38 shown in FIG. 2. The third increment signal inc 3  outputted from the fifth AND gate 52 has the high logic value only when all the 8 inverted data bits /a 0  to /a 7  have the value of logic-1. 
     The sixth AND gate 54 performs the AND operation among the enable signal EN and the output signals from the first to third AND gates 44, 46 and 48 and sends the result of the AND operation as the fourth increment signal inc 4  to the fourth conditional incrementer 40 shown in FIG. 2. The fourth increment signal inc 4  outputted from the sixth AND gate 54 has the high logic value only when all the 8 inverted data bits /a 0  to /a 11  applied to the first to third input lines 33, 35 and 37 have the value of logic-1. 
     FIG. 4 is a circuit diagram of one of the first to fourth conditional incrementers 34, 36, 38 and 40 shown in FIG. 2 in accordance with a first embodiment of the present invention. As shown in FIG. 4, the conditional incrementer includes seventh to ninth AND gates 56, 58 and 60 for receiving an increment signal inc k  from a first input line 49, and a first exclusive OR gate 62 for receiving i-th inverted data /a i  from a second input line 51. The seventh AND gate 56 ANDs the increment signal inc k  and the i-th inverted data /a i  from the second input line 51. The eighth AND gate 58 performs the AND operation among the increment signal inc k , the i-th inverted data /a i  from the second input line 51 and i+1-th inverted data /a i+1  from a third input line 53. On the other hand, the ninth AND gate 60 performs the AND operation among the increment signal inc k , the i-th inverted data /a i  from the second input line 51, the i+1-th inverted data /a i+1  from the third input line 53 and an i+2-th inverted data /a i+2  from a fourth input line 55. 
     The increment signal inc k  is generated by the AND operation between data /a i-1  i-1-th inverted from the LSB data /a 0  and the enable signal EN. The increment signal inc k  has the high logic value only when both the i-1-th inverted data /a i-1  and the enable signal EN. Here, &#34;i&#34; corresponds to &#34;4k-1&#34; and &#34;k&#34; is a positive integer. 
     The first exclusive OR gate 62 compares the increment signal inc k  from the first input line 49 and the i-th inverted data /a i  from the second input line 51 with each other and sends the result of the comparison to a first output line 59. When the increment signal inc k  has the high logic value, the output signal from the first exclusive OR gate 62 carries i-th data a i  resulted from an inversion of the i-th inverted data /a i . On the contrary, the output signal from the first exclusive OR gate 62 carries the i-th inverted data /a i  when the increment signal inc k  has the low logic value. 
     The conditional incrementer further includes second to fourth exclusive OR gates 64, 66 and 68 for receiving the seventh to ninth AND gates 56, 58 and 60, respectively. The second exclusive OR gate 64 compares the output signal from the seventh AND gate 56 with the i+1-th inverted data /a i+1  from the third input line 53 and sends the result of the comparison to a second output line 61. When both the i-th inverted data /a i  and the increment signal inc k  have the high logic value, that is, the value of logic-1, the output signal from the second exclusive OR gate 64 carries i+1-th data a i+1  resulted from an inversion of the i+1-th inverted data /a i+1 . On the contrary, the output signal from the second exclusive OR gate 64 carries the i+1-th inverted data /a i+1  when both the i-th inverted data /a i  and the increment signal inc k  have not the value of logic-1. 
     The third exclusive OR gate 66 compares the output signal from the eighth AND gate 58 with the i+2-th inverted data /a i+2  from the fourth input line 55 and sends the result of the comparison to a third output line 63. When all the i-th inverted data /a i , the i+1-th inverted data /a i+1  and the increment signal inc k  have the value of logic-1, the output signal from the third exclusive OR gate 66 carries i+2-th data a i+2  resulted from an inversion of the i+2-th inverted data /a i+2 . On the contrary, the output signal from the third exclusive OR gate 66 carries the i+2-th inverted data /a i+2  when all the i-th inverted data /a i , the i+1-th inverted data /a i+1  and the increment signal inc k  have not the value of logic-1. 
     In similar to the third exclusive OR gate 66, the fourth exclusive OR gate 68 compares the output signal from the ninth AND gate 60 with the i+3-th inverted data /a i+3  from the fifth input line 57 and sends the results of the comparison to a fourth output line 65. When all the i-th inverted data /a i , the i+1-th inverted data /a i+1 , the i+2-th inverted data /a i+2  and the increment signal inc k  have the value of logic-1, the output signal from the fourth exclusive OR gate 68 carries i+2-th data a i+2  resulted from an inversion of the i+3-th inverted data /a i+3 . On the contrary, the output signal from the fourth exclusive OR gate 68 carries the i+3-th inverted data /a i+3  when all the i-th inverted data /a i , the i+1-th inverted data /a i+1 , the i+2-th inverted data /a i+2  and the increment signal inc k  have not the value of logic-1. 
     Where the increment signal inc k  has the high logic value, 4 data bits on the first to fourth output lines 59, 61, 63 and 65 have logic values each resulted from the addition of &#34;1&#34; to each logic value of the 4 inverted data bits /a i  to /a i+3  applied to the first to fourth input lines 51, 53, 55 and 57, respectively. On the contrary, when the increment signal inc k  has low high logic value, the 4 data bits on the first to fourth output lines 59, 61, 63 and 65 have logic values identical to those of the 4 inverted data bits /a i  to /a i+3  applied to the first to fourth input lines 51, 53, 55 and 57, respectively. 
     In actual, where four data bits having logic values of 0, 0, 1 and 1 are applied respectively to the first to fourth input lines 51, 53, 55 and 57 and the increment signal inc k  had the high logic value, four 2&#39;s-complement data bits having logic values of 0, 1, 0 and 0 are generated on the first to fourth output lines 59, 61, 63 and 65, respectively. 
     FIG. 5 is a circuit diagram of one of the first to fourth conditional incrementers 34, 36, 38 and 40 shown in FIG. 2 in accordance with a second embodiment of the present invention. The conditional incrementer shown in FIG. 5 has a simple logic circuit including reduced number of transistors, as compared with that of FIG. 4. 
     As shown in FIG. 5, the conditional incrementer includes a first inverter 70 for receiving an increment signal inc k  from a first input stage 67 and a second inverter 72 for receiving i-th inverted data /a i  from a second input stage 69. The first inverter 70 serves to invert the increment signal inc k  received from the first input stage 67 and then send the inverted increment signal /inc k  to the first transmission line 85. The second inverter 70 inverts the i-th inverted data /a i  received from the second input stage 69 and then send the resultant i-th data a i  to the second transmission line 87. 
     A first field effect transistor (FET) Q 1  is coupled between the second input stage 69 and the first output stage 77. A second FET Q 2  is coupled between the second transmission line 87 and the first output stage 77. The first FET Q 1  transmits the i-th inverted data /a i  from the second input stage 69 to the first output stage 77 when it receives at the gate thereof the high logic value of the inverted increment signal /inc k  from the first transmission line 85. On the other hand, the second FET Q 2  transmits the i-th inverted data /a i  from the first input stage 67 to the first output stage 77 when it receives at the gate thereof the high logic value of the increment signal inc k  from the first input stage 67. In other words, the i-th inverted data /a i  or the i-th data a i  is transmitted to the first output stage 77 in accordance with the logic state of the increment signal inc k . 
     The conditional incrementer of FIG. 5 further includes a third inverter 74 for receiving i+1-th inverted data /a i+1  from a third input stage 71 and a third FET Q 3  coupled between the third input stage 71 and a second output stage 79. The third inverter 74 serves to invert the i+1-th inverted data /a i+1  and then send the resultant i+1-th data a i+1  to a third transmission line 89. Between the third transmission line 89 and the second output stage 79, a fifth FET Q 5  and a sixth FET Q 6  are connected in series. A fourth FET Q 4  is coupled between the junction 93 of the fifth and sixth FETs Q 5  and Q 6  and the third input stage 71. 
     The third FET Q 3  transmits the i+1-th inverted data /a i+1  from the third input stage 71 to the second output stage 79 when it receives at the gate thereof the high logic value of the inverted increment signal /inc k  from the first transmission line 85. The fourth FET Q 4  transmits the i+1-th inverted data /a i+1  from the third input stage 71 to the sixth FET Q 6  when it receives at the gate thereof the high logic value of the i-th data a i  from the second transmission line 87. The fifth FET Q 5  transmits the i+1-th data a i+1  received from the third inverter 74 via the third transmission line 89 to the sixth FET Q 6  when it receives at the gate thereof the high logic value of the i-th inverted data /a i  from the second input stage 69. On the other hand, the sixth FET Q 6  transmits the i+1-th inverted data /a i+1  from the fourth FET Q 4  or the i+1-th data a i+1  from the fifth FET Q 5  when it receives at the gate thereof the high logic value of the increment signal inc k  from the first input stage 67. 
     Accordingly, the second output stage 79 receives the i+1-th data a i+1  when both the increment signal inc k  and the i-th inverted data /a i  have the high logic value. On the contrary, the i+1-th inverted data /a i+1  is applied to the second output stage 79 when both the increment signal inc k  and the i-th inverted data /a i  have not the high logic value. 
     Furthermore, the conditional incrementer of FIG. 5 includes a fourth inverter 76 for receiving i+2-th inverted data /a i+2  from a fourth input stage 73 and a seventh FET Q 7  coupled between the fourth input stage 73 and a third output stage 81. The fourth inverter 76 inverts the i+2-th inverted data /a i+2  and then sends the resultant i+2-th data a i+2  to a fourth transmission line 91. Between the fourth transmission line 91 and the third output stage 81, tenth to twelfth FETs Q 10  to Q 12  are connected in series. A ninth FET Q 9  is coupled between the junction 97 of the tenth and eleventh FETs Q 10  and Q 11  and the fourth input stage 73. An eighth FET Q 8  is coupled between the junction 95 of the eleventh and twelfth FETs Q 11  and Q 12  and the fourth input stage 73. 
     The seventh FET Q 7  transmits the i+2-th inverted data /a i+2  from the fourth input stage 73 to the third output stage 81 when it receives at the gate thereof the high logic value of the inverted increment signal /inc k  from the first transmission line 85. The eighth FET Q 8  transmits the i+2-th inverted data /a i+2  from the fourth input stage 73 to the twelfth FET Q 12  when it receives at the gate thereof the high logic value of the i-th data a i  from the second transmission line 87. The ninth FET Q 9  transmits the i+2-th inverted data /a i+2  from the fourth input stage 73 to the eleventh FET Q 11  when it receives at the gate thereof the high logic value of the i+1-th data a i+1  from the third transmission line 89. 
     The tenth FET Q 10  transmits the i+2-th inverted data /a i+2  from the fourth inverter 76 via the fourth transmission line 91 to the eleventh FET Q 11  when it receives at the gate thereof the high logic value of the i+1-th inverted data /a i+1  from the third input stage 71. The eleventh FET Q 11  transmits the i+2-th inverted data /a i+2  from the ninth FET Q 9  or the i+2-th data a i+2  from the tenth FET Q 10  to the twelfth FET Q 12  when it receives at the gate thereof the high logic value of the i-th inverted data /a i  from the second input stage 69. The twelfth FET Q 12  receiving at the gate thereof the increment signal inc k  from the first input stage 67 transmits the i+2-th inverted data /a i+2  from the eight FET Q 8  or the i+2-th data a i+2  and i+2-th inverted data /a i+2  from the eleventh FET Q 11  to the third output stage 81 when the increment signal inc k  has the high logic value. 
     Accordingly, the third output stage 81 receives the i+2-th data a i+2  when all the increment signal inc k , the i-th inverted data have the high logic value. On the contrary, the i+2-th inverted data /a i+2  is applied to the third output stage 81 when all the increment signal inc k , the i-th inverted data /a i  and the i+1-th inverted data /a i+1  have the high logic value. 
     The conditional incrementer of FIG. 5 further includes a fifth inverter 75 for receiving i+3-th inverted data /a i+3  from a fifth input stage 75 and a thirteenth FET Q 13  coupled between the fifth input stage 75 and a fourth output stage 83. The fifth inverter 78 serves to invert the i+3-th inverted data /a i+3  and then send the resultant i+3-th data a i+3  to a seventeenth FET Q 17 . Between the seventeenth FET Q 17  and the fourth output stage 83, eighteenth to twentieth FETs Q 18  to Q 20  are connected in series. A sixteenth FET Q 16  is coupled between the junction 103 of the seventeenth and eighteenth FETs Q 17  and Q 18  and the fifth input stage 75. A fifteenth FET Q 15  is coupled between the junction 101 of the eighteenth and nineteenth FETs Q 18  and Q 19  and the fifth input stage 75. A fourteenth FET Q 14  is coupled between the junction 99 of the nineteenth and twentieth FETs Q 19  and Q 20  and the fifth input stage 75. 
     The thirteenth FET Q 13  transmits the i+3-th inverted data /a i+3  from the fifth input stage 75 to the fourth output stage 83 when it receives at the gate thereof the high logic value of the inverted increment signal /inc k  from the first transmission line 85. The fourteenth FET Q 14  transmits the i+3-th inverted data /a i+3  from the fifth input stage 75 to the twentieth FET Q 20  when it receives at the gate thereof the high logic value of the i-th data a i  from the second transmission line 87. The fifteenth FET Q 15  transmits the i+3-th inverted data /a i+3  from the fifth input stage 75 to the nineteenth FET Q 19  when it receives at the gate thereof the high logic value of the i+1-th data a i+1  from the third transmission line 89. The sixteenth FET Q 16  transmits the i+3-th inverted data /a i+3  from the fifth input stage 75 to the eighteenth FET Q 18  when it receives at the gate thereof the high logic value of the i+2-th data a i+2  from the fourth transmission line 91. 
     The seventh FET Q 17  transmits the i+3-th data a i+3  from the fifth inverter 78 to the eighteenth FET Q 18  when it receives at the gate thereof the high logic value of the i+2-th inverted data /a i+2  from the fourth input stage 73. The eighteenth FET Q 18  transmits the i+3-th inverted data /a i+3  from the sixteenth FET Q 16  or the i+3-th data a i+3  from the seventeenth FET Q 17  to the nineteenth FET Q 19  when it receives at the gate thereof the high logic value of the i+1-th inverted data /a i+1  from the third input stage 71. The nineteenth FET Q 19  transmits the i+3-th inverted data /a i+3  from the fifteenth FET Q 15  or one of the i+3-th data a i+3  and i+3-th inverted data /a i+3  from the eighteenth FET Q 18  to the nineteenth FET Q 19  when it receives at the gate thereof the high logic value of the i-th inverted data /a i  from the second input stage 69. The twentieth FET Q 20  receiving at the gate thereof the increment signal inc k  from the first input stage 67 transmits the i3-th inverted data /a i+3  from the fourteenth FET Q 14  or one of the i+3-th data a i+3  and i+3-th inverted data /a i+3  from the nineteenth FET Q 19  to the fourth output stage 83 when the increment signal inc k  has the high logic value. 
     Accordingly, the fourth output stage 83 receives the i+3-th data a i+3  when all the increment signal inc k  and the i-th to i+2-th inverted data /a i  to /a i+2  have the high logic value. On the contrary, the i+3-th inverted data /a i+3  is applied to the fourth output stage 83 when all the increment signal inc k  and the i-th to i+2-th inverted data /a i  to /a i+2  have the high logic value. 
     FIG. 6 is a table illustrating complementary speeds, namely, complementation rates and the number of transistors required per bit in the conventional 2&#39;s complementer and 2&#39;s complementers respectively including conditional incrementers according to the first and second embodiments of the present invention, where data of 20 bits are to be complemented. As shown in the table of FIG. 6, the 2&#39;s complementer including the conditional incrementers shown in FIG. 4 can perform the complementation for the data of 20 bits at a rate corresponding to 4 times the rate of the conventional 2&#39;s complementer. This means that the 2&#39; complementer of the first embodiment of the present invention can have a circuit arrangement simplified to 1/4 of that of the conventional 2&#39;s complementer. The 2&#39;s complementer including the conditional incrementers shown in FIG. 5 can perform the complementation for the data of 20 bits at a rate corresponding to about 3.8 times the rate of the conventional 2&#39;s complementer. This means that the 2&#39; complementer of the second embodiment of the present invention can have a circuit arrangement simplified to about 1/2 of that of the conventional 2&#39;s complementer. 
     As apparent from the above description, the present invention provides a 2&#39;s complementer capable of simultaneously performing operations for individual bits of 1&#39;s complement data in a parallel manner, thereby achieving an improvement in complementation rate and a simpleness in circuit arrangement. 
     Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.