Abstract:
It is an object of the present invention to provide a method for controlling the vehicle speed during acceleration of a four-wheel drive vehicle, wherein the vehicle speed during acceleration can be determined with precision. According to the above method, even if a wheel is spinning, the vehicle speed can be correctly determined without any influence of the spin, by correcting the vehicle speed during acceleration by comparison of the determined second vehicle speed, based upon the lowest speed of the four wheels, with the first vehicle speed, which is determined based upon the wheel speed.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a method for predicting the vehicle speed during acceleration of a four-wheel drive vehicle. 
     BACKGROUND OF THE INVENTION 
     Anti-lock control of a four-wheel drive vehicle is coventionally based upon the vehicle speed. In a two-wheel drive vehicle, the vehicle speed substantially corresponds with the speed of a driven wheel (the speed of a rear wheel in a front-wheel drive vehicle) and hence, during acceleration, the vehicle speed can be determined based upon this driven-wheel speed. In contrast, in a four-wheel drive vehicle, it is difficult to determine the vehicle speed when the wheel(s) spin due to increasing speed of the wheels on a snowy road, a frozen road or the like, because the four-wheel drive vehicle has no driven wheels. 
     If the vehicle speed during acceleration of the wheels cannot be determined with precision, as described above, the accuracy of the anti-lock control may also be reduced. 
     SUMMARY OF THE INVENTION 
     The present invention has been accomplished with the prior art in view, and it is an object of the present invention to provide a method for controlling the vehicle speed during acceleration of a four-wheel drive vehicle, wherein the vehicle speed during acceleration ca be determined with precision. 
     According to the present invention, a first vehicle speed is determined based upon a wheel speed in such a manner that an acceleration of a determined vehicle speed may be less than a first upper limit acceleration. A second vehicle speed is determined based upon a lowest speed of one of four wheel speeds of the four wheels of the vehicle in such a manner that the acceleration of the determined vehicle speed may be less than a second upper limit acceleration which is lower than the first upper limit acceleration. The vehicle speed during an increase in speed is corrected by comparison of the first vehicle speed with the second vehicle speed. 
     According to the above method, even if a wheel is spinning, the vehicle speed can be correctly determined without any influence of the spin, by correcting the vehicle speed during acceleration by comparison of the determined second vehicle speed, based upon the lowest speed of the four wheels, with the first vehicle speed, which is determined based upon the wheel speed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The drawings illustrate one embodiment of the present invention, wherein 
     FIG. 1 is a block diagram illustrating an arrangement of an anti-lock control circuit; 
     FIG. 2 is a flow chart illustrating the processing of a first vehicle speed determining means; 
     FIG. 3 is a flow chart illustrating the processing of a second vehicle speed determining means; 
     FIG. 4 is a graph illustrating determining a vehicle speed characteristic. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention will now be described by way of one embodiment with reference to the accompanying drawings. FIG. 1 illustrates an anti-lock control circuit for a four-wheel drive vehicle. The speeds detected by front-wheel speed detectors, S FL  and S FR , for independently detecting the wheel speeds of left and right front wheels, are supplied to an arithmetic circuit 1 F . The speeds detected by rear-wheel speed detectors S RL  and S RR , for independently detecting the wheel speeds of left and right rear wheels, are supplied to an arithmetic circuit 1 R . The arithmetic circuits 1 F  and 1 R  average the supplied vehicle speeds to give an average wheel speed of the front wheels and an average wheel speed of the rear wheels. Alternatively, in place of the arithmetic circuits 1 F  and 1 R , a low select circuit or a high select circuit may be used. 
     Detection signals from the front-wheel speed detectors S FL  and S FR  are input to a low select circuit 2 F , while detection signals from the rear-wheel speed detectors S RL  and S RR  are input to a low select circuit 2 R . Signals from the low selection circuit 2 F  and 2 R  are supplied to a low select circuit 3. Thus, the lowest one of the wheel speeds of the four wheels, i.e., the front wheels and the rear wheels is delivered by the low select circuit 3. 
     The wheel speeds obtained in the arithmetic circuits 1 F  and 1 R  are input to a first vehicle-speed determining means 4 F  for the front wheels and a first vehicle-speed determining means 4 R  for the rear wheels, respectively. First vehicle speeds V 1F  and V 1R  are based on the front wheel speed and the rear wheel speed. The wheel speed selected in the low select circuit 3 is input to a second vehicle-speed determining means 5 where a second vehicle speed V 2  is determined based upon the wheel speeds of the four wheels. 
     Each of the vehicle-speed determining means 4 F , 4 R  and 5 comprises a computer. In the first vehicle-speed determining means 4 F  for the front wheels and the first vehicle-speed determining means 4 R  for the rear wheels, the vehicle speeds are determined according to a control procedure as shown in FIG. 2. In the second vehicle-speed determining means 5, the vehicle speed is determined according to a control procedure as shown in FIG. 3. 
     Referring to FIG. 2, the control procedure will be first described for the vehicle-speed determining means 4 F  and 4 R  for the front and rear wheels. The suffix F for the front wheel and the suffix R for the rear wheel are omitted in FIG. 2. V&#39; represents the vehicle speed obtained in the last processing cycle. In an initial cycle, at step S1, V&#39;=0 is established. At a subsequent second step S2, the wheel speeds from the arithmetic circuits 1 F  and 1 R , i.e., the wheel speeds V W2F  and V W2R  of both front wheels or both rear wheels are read as a temporary vehicle speed. 
     At a third step S3, a determination is made whether or not the last vehicle speed V&#39; is equal to or greater than the read wheel speed V W2F  or V W2R  (V&#39;≧V W2F  or V&#39;≧V W2R ), (i.e., the speed is decreasing) by comparison with the wheel speed V W2F  or V W2R  read as the last vehicle speed V&#39;. When V&#39;≧V W2F  or V&#39;≧W W2R , the processing proceeds to a fourth step S4. When V&#39;&lt;V W2F  or V&#39;&lt; V W2R , i.e., when the speed is increasing, the processing proceeds to a seventh step S7. 
     At the fourth step S4, a determination is made whether or not the deceleration is equal to or greater than a value a which corresponds to a lower limit deceleration (V&#39;-V W2F  ≧a or V&#39;-V W2R  ≧a). When (V&#39;-V W2F ) ≧a, or (V&#39;-V W2R )≧a, a new vehicle speed V is corrected to establish V=(V&#39;-a) at a fifth step S5. When (V&#39;-V W2F )&lt;a and (V&#39;-V W2R )&lt;a, V=V W2  is established at a sixth step S6. Processing then continues at a tenth step S10. 
     At the seventh step S7, a determination is made whether or not the acceleration is equal to or greater than a value b which corresponds to a first upper limit acceleration, e.g., 1.0 G (V&#39;-V W2F  ≧b, or V&#39;-V W2R  ≧b). When (V&#39;-V W2F )≧b or (V&#39;-V W2R ) ≧ b, new vehicle speeds V 2F  ; and V 2R  are corrected to establish V 2F  =(V&#39;+b) or V 2R  =(V&#39;+b) at an eight step S8. Alternatively, when (V&#39;-V W2F )&lt;b or (V&#39;-V W2R )&lt;b, V 2F  =V W2F  and V W2F  =V W2R  are established at a ninth step S9. Processing then proceeds to the tenth step S10. It is to be noted that the maximum acceleration of the vehicle is about 0.7 G, but the above-described upper limit of the vehicle is about 0.7 G, but the above-described upper limit acceleration is set at 1.0 G for more accurately determining the vehicle speed during braking. 
     At the tenth step S10, the determined vehicle speeds V 2F  and V 2R  are output as the second vehicle speeds. Then, V&#39;=V 2F  and V&#39;=V 2R  are established at an eleventh step S11. 
     The procedure of determining vehicle speeds in a speed-increasing condition in the first vehicle-speed determining means 4 F  and 4 R  will be summarized as follows: First vehicle speeds V 2F  and V 2R  are determined based upon the wheel speeds of the two subject wheels in such a manner that the accelerations of the determined vehicle speeds may be less than the first upper limit acceleration b. In this case, when the accelerations of the wheel speeds are higher than the first upper limit acceleration b, the first upper limit acceleration b is determined to be the vehicle acceleration. When the accelerations of the wheel speeds are less than the first upper limit acceleration b, the accelerations of the wheel speeds are determined to be the vehicle accelerations. 
     Even in the second vehicle speed determining means 5, a first vehicle speed V 4  is determined according to a procedure basically similar to that in the above-described first vehicle speed determining means 4 F  and 4 R , as shown in FIG. 3, wherein a wheel speed to be read is the lowest speed V WL  of the four wheel speeds of the four wheels, and the standard for the determination during increasing speed is a second upper limit acceleration b&#39; set at 0.7 G. 
     The procedure of determining the vehicle speed in a speed increasing condition in the second vehicle speed determining means 5 will be summarized as follows: A second vehicle speed V 4  is determined based upon the lowestspeed V WL  of the four wheel speeds of the four wheels in such a manner that the acceleration of the determined vehicle speed may be less than the second upper limit acceleration b&#39;. In this case, when the acceleration of the lowest wheel speed V WL  is higher than the second upper limit acceleration b&#39;, the second upper limit acceleration b&#39; is determined to be the vehicle acceleration. When the acceleration of the lowest wheel speed V WL  is lower than the second upper limit acceleration b&#39;, the acceleration of the lowest wheel speed V WL  is determined to be the vehicle acceleration. 
     The first vehicle speed V 2F  and V 2R  obtained in the first vehicle speed determining means 4 F  and 4 R  are input into the arithmetic circuits 6 F  and 6 R , respectively. The second vehicle speed V 4  obtained in the second vehicle speed determining means 4 is also input into the arithmetic circuit 6 F  and 6 R . 
     In the arithmetic circuits 6 F  and 6 R , the second vehicle speed V 4 , obtained in the second vehicle speed determining means 5, is subtracted from the first vehicle speeds V 2F  and V 2R  obtained in the first vehicle speed determining means 4 F  and 4 R . In other words, (V 2F  -V 4 ) and (V 2R  -V 4 ) are obtained in the arithmetic circuits 6 F  and 6 R . The arithmetic results are input into noninverted terminals of comparator circuits 7 F  and 7 R , respectively. On the other hand, a set velocity V B  is input to each of the inverted input terminals of the comparator circuits 7 F  and 7 R . Thus, when the aforesaid arithmetic results (V 2F  -V 4 ) and (V 2R  -V 4 ) are larger than the set velocity V B , each of the comparator circuits 7 F  and 7 R  produces a high level signal. 
     An output terminal of each of the comparator circuits 7 F  and 7 R  is connected to one of input terminals of the corresponding one of AND circuits 8 F  and 8 R . A signal which becomes a high level during acceleration is supplied to the other input terminals of the AND circuit 8 F  and 8 R  from a speed-increase sensor 9 which detects the increasing speed condition of the vehicle. Therefore, during acceleration of the vehicle when both first vehicle speeds V 2F  and V 2R  are larger than the second vehicle speed V 4  by a given value V B  or more, the AND circuits 8 F  and 8 R  each produce a high level signal. 
     Moreover, an output from each of the AND circuits 8 F  and 8 R  is input to the corresponding one of the first vehicle speed determining means 4 F  and 4 R , where now determined vehicle speeds V 2F  and V 2R  are retained, when signals from the AND circuits 8 F  and 8 R  each have become a high level. 
     A signal from the first vehicle speed determining means 4 F  for the front wheels is supplied to the reference vehicle speed setting circuits 10 F1  and 10 F2 . A signal from the first vehicle speed determining means 4 R  for the rear wheels is supplied to the reference vehicle speed setting circuits 10 R1  and 10 R2 . The reference vehicle speed setting circuits 10 F1 , 10 F2 , 10 R1  and 10 R2  each set a reference vehicle speed required for the anti-lock control. For example, by simply multiplying the input vehicle speed V 2F  or V 2R  by a set value, a reference vehicle speed is obtained. 
     A reference vehicle speed for each of the reference vehicle speed setting circuits 10 F1  and 10 F2  associated with the front wheels is supplied to a non-inverted terminal of the corresponding one of comparator circuits 12 FL1  and 12 FL2  for the left front wheel and is also supplied to a non-inverted terminal of the corresponding one of comparator circuits 12 FR1  and 12 FR2  for the right front wheel. A reference vehicle speed from each of the reference vehicle speed setting circuits 10 R1  and 10 R2  associated with the rear wheels is supplied to a non-inverted terminal of the corresponding one of comparator circuits 12 R1  and 12 R2  for the rear wheels. Moreover, a left front wheel speed is supplied from a lefthand front wheel speed detector S FL  to inverted terminals of the comparator circuits 12 FL1  and 12 FL2  for the left front wheel. A left front wheel speed is supplied from a righthand front wheel speed detector S FR  to inverted terminals of the comparator circuits 12 FR1  and 12 FR2  for the right front wheel. The lowest wheel speed obtained by the rear wheel speed detectors S RL  and S RR  is selected in the low select circuit 11 and is supplied to inverted terminals of the comparator circuits 12 R1  and 12 R2  for the rear wheels. 
     A signal λ 1  is delivered from each of the comparators 12 FL1 , 12 FR1  and 12 R1  based upon the wheel speeds and becomes a high level when the slippage of the corresponding wheel has exceeded a certain first reference value. This signal λ 1  is supplied to AND circuits 13 FL1 , 13 FR1  and 13 R1 . A signal λ 2  is also delivered from each of the comparators 12 FL2 , 12 FR2  and 12 R2  based upon the wheel speeds and becomes a high level when the slippage of the corresponding wheel has exceeded a second reference value which is larger than the aforesaid first reference value. This signal λ 2  is supplied to AND circuits 13 FL2 , 13 FR2  and 13 R2 . Further, a signal β, which becomes a high level when the wheel deceleration has exceeded a certain value, is supplied to the AND circuits 13 FL1 , 13 FR1  and 13 R1 . A signal α, which becomes a high level when the wheel acceleration has exceeded a certain value, is input in an inverted manner to the AND circuits 13 FL2 , 13 FR2  and 13 R2 . 
     Accordingly, the AND circuits 13 FL1 , 13 FR1  and 13 R1  each produce a high level signal when it is determined that there is a possibility of the wheel being locked in a speed reducing condition where the vehicle speed exceeds the first reference speed. The AND circuits 13 FL2 , 13 FR2  and 13 R2  each produce a high level signal when it is determined that there is an increased possibility of the wheel being locked in a condition where the vehicle speed exceeds the second reference speed and is not being increased. 
     The AND circuits 13 FL1  and 13 FL2  associated with the left front wheel are connected to an OR circuit 14 FL . The AND circuits 13 FR1  and 13 FR2  associated with the right front wheel are connected to an OR circuit 14 FR . The AND circuits 13 R1  and 13 R2  associated with both rear wheels are connected to an OR circuit 14 R . In turn, the OR circuit 14 FL  is connected to a left front wheel anti-lock control section 15 FL  for reducing the hydraulic braking pressure for a left front wheel brake when a high level signal is input thereto. The OR circuit 14 FR  is connected to a right front wheel anti-lock control section 15 FR  for reducing the hydraulic braking pressure for a right front wheel brake when a high level signal is input thereto. The OR circuit 14 R  is connected to a two-rear wheel anti-lock control section 15 R  for reducing the hydraulic braking pressure for a two-rear wheel brake when a high level signal is input thereto. 
     The operation of this embodiment will be described below. A determination of the vehicle speed is required during an anti-lock control. First vehicle speeds V 2F  and V 2R  obtained in the first vehicle speed determining means 4 F  for the front wheels determines the vehicle speed based upon the front wheel speeds. The first vehicle speed determining means for the rear wheels determines the vehicle speed based upon the rear speeds. The front and rear wheel speeds are compared with a second vehicle speed V 4  obtained in the second vehicle speed determining means 5, which determines the vehicle speed based upon the lowest speed of the four wheels. When the second vehicle speed V is lower than the first vehicle speeds V 2F  and V 2R  by a given value V B  or more, outputs from the first vehicle speed determining means 4 F  and 4 R  are maintained constant during increasing speed. Thus, as shown in FIG. 4, the first vehicle speeds V 2F  and V 2R  are determined as a value substantially corresponding to the second vehicle speed V 4 . 
     As a result, when a spinning wheel occurs, the vehicle speed can be determined as a value which cannot be larger than a vehicle speed based on the lowest of the four wheel speeds of the four wheels. On the basis of the determined vehicle speed, the anti-lock control is performed, leading to an improved accuracy of the anti-lock control. 
     As discussed above, according to the present invention, a first vehicle speed is determined based upon the wheel speed in such a manner that the acceleration of the determined vehicle speed may be less than a first upper limit acceleration. The second vehicle speed is determined based upon the lowest wheel speed of four wheels. The acceleration of the determined vehicle speed may be less than a second upper limit acceleration which is lower than the first upper limit acceleration. The vehicle speed during acceleration is corrected by comparison of the first vehicle speed with the second vehicle speed. Therefore, even if a spinning wheel is produced in the subject wheel, the determined vehicle speed does not become greater than the vehicle speed based on the lowest wheel speed of the four wheels. This leads to an improved accuracy of determining the vehicle speed. 
     From the foregoing description of the preferred embodiment of the invention, it will be apparent that many modifications may be made therein. It should be understood that these embodiments are intended as one example of the invention only, and that the invention is not limited thereto. Therefore, it should be understood that the appended claims are intended to cover all modifications that fall within the true spirit and scope of the invention.