Abstract:
A DC to DC converter circuit which accomplishes both non-pulsating input and output currents using a single simple coupled inductor is revealed. The DC to DC converter accomplishes either buck or boost conversion using a simple circuit requiring only two switches, one of which may be a simple diode rectifier, a capacitor, and two inductors, which may be colocated on a single common magnetic core. These converters are, in some ways, similar to the Cuk converter, but they do not provide inverted outputs. Zero voltage switching versions of these converters are revealed. Also revealed are techniques and methodology for reducing both input and output current ripple to near zero levels. The buck version of the circuit accomplishes DC to DC conversion without inversion and with no right half plane zero in its control to output transfer function. The boost version is also non-inverting.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The subject invention generally pertains to electronic power conversion circuits, and more specifically to high frequency, switched mode power electronic converter circuits. 
     2. Description of Related Art 
     There are some power conversion circuits which accomplish power conversion from one DC voltage level to another DC voltage level using an intermediate energy storage mechanism such as a power inductor. Examples of such power conversion circuits include the buck, boost, and buck boost converters which are well known to those skilled in the art of power conversion. These converters are simple, requiring only one large magnetic storage element, the power inductor, and two switches. Typically input and output capacitors are added to the basic circuit. For isolated power conversion an isolation transformer or a coupled inductor is required in addition to or instead of the power inductor. One problem associated with practical non-isolated power conversion circuits that employ the buck, boost, or buck boost converters is that either the input current, the output current, or both the input and output current are pulsating, that is non-continuous. The pulsating currents result in high ripple currents and high ripple voltages by comparison to inputs or outputs in which the input or output current is continuous or non-pulsating. In order to reduce the effects of the pulsating currents an additional filter stage using an additional inductor and capacitor, or LC combination, or the use of a much larger input or output capacitor is required. The consequence of the additional filtering is higher cost and, in the case of the LC filter, higher losses. For example, the buck converter has a pulsating (discontinuous) input current and a non-pulsating (continuous) output current. Power supplies that use buck converters often employ an LC input filter to reduce the ripple resulting from the pulsating input current. One specific example is the Datel dual output BMP models which use a buck post regulator with an LC input filter, which is illustrated in FIG. 1, to generate a second power supply output. The BMP models employ the main output of the power supply as the input to the buck post regulator. If they did not use an input LC filter with the buck post regulator the pulsating input current of the buck post regulator would compromise the ripple performance of the converter&#39;s main output. One example of prior art that overcomes the problem is the famous Cuk converter, shown in FIG. 2, which is also referred to by its inventor as the optimal topology converter. The Cuk converter circuit is optimal in the sense that both the input current and output current are non-pulsating. One of the likely reasons that the Cuk converter was not chosen in the Datel design is that the non-isolated Cuk converter has an output voltage that is opposite in sign to its input. Another shortcoming of the Cuk converter is that its control to output transfer function has a right half plane zero which, in practical terms, limits the available bandwidth, which in some cases, especially where fast load current transient response is a requirement, renders the Cuk converter unsuitable. Cuk, in a paper included in his book entitled “Advances in Switched-Mode Power Conversion” on page 319 explains how the re-orientation or rotation of the switching cell in the Cuk converter leads to buck and boost converters with continuous input and output currents. The continuous input and output current buck and boost converters that Cuk describes in his book on page 319 are simply the well known buck converter with an LC input filter, shown in FIG. 1, and the well known boost converter with an LC output filter, respectively. The Datel design is then the buck implementation of the Cuk converter as described by Cuk in his own writings. The same process of generating continuous input and output current buck and boost converters from the Cuk switching cell is also described in a recent book by Robert Erickson entitled “Fundamentals of Power Electronics” on pages 141 and 142. In Erickson&#39;s book he describes a process for generating the buck and boost forms of the Cuk converter similar to the process described by Cuk with identical results. There is one important feature of the Cuk converter which is missing in the buck and boost derivations described by Cuk and Erickson. The Cuk described buck and boost derivations both require two separate inductors which cannot be magnetically coupled. This requirement is due to the fact that the AC wave forms of the two inductors are dissimilar, whereas the AC wave forms of the two inductors in the Cuk converter are very similar or identical which enables the combination of the two chokes of the Cuk converter in a single simple magnetically coupled inductor construction. In the non-pulsating buck and boost converters described by Cuk and Erickson one of the chokes has a large AC winding voltage component and the other has a very small AC winding voltage component. In the same book by Cuk on page 337 Cuk describes how his optimal topology converter works when implemented with the two chokes combined in a single simple coupled inductor, as illustrated in FIG.  3 . Several patents have been issued on the basic Cuk converter and the coupled inductor versions of the Cuk converter. What is needed are simple optimal topology converters in which the two inductors can be combined into a single simple magnetically coupled inductor and can accomplish step up or step down DC to DC conversion without inversion or isolating transformer. Such an optimal topology converter in the buck form would reduce the size and cost of converters of the Datel BMP type by combining the two inductors into a simple single coupled magnetic circuit element. Such an optimal topology converter in the boost form would satisfy a need for converters similar to the Datel BMP type, but where the main output voltage is lower than the voltage of the second output. 
     OBJECTS AND ADVANTAGES 
     One object of the subject invention is to provide simple DC to DC power conversion circuits with both continuous input current and continuous output current using a single simple magnetically coupled inductor. 
     Another object of the subject invention is to provide a simple non-inverting optimal topology step down DC to DC power conversion circuit without a right half plane zero in the control to output transfer function. 
     Another object of the subject invention is to provide a simple non-inverting optimal topology step up DC to DC power conversion circuit. 
     Another object of the subject invention is to provide simple zero voltage switching DC to DC power conversion circuits with both continuous input current and continuous output current using a single simple magnetically coupled inductor and a small inductor to drive the soft switching transitions. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by reference to the drawings. 
     FIG. 1 illustrates a buck regulator with an LC input filter which accomplishes non-pulsating input and output currents. 
     FIG. 2 illustrates a Cuk converter with two separate chokes. 
     FIG. 3 illustrates a Cuk converter with the two chokes combined into a single simple magnetically coupled inductor. 
     FIG. 4 illustrates a buck type optimal topology converter according to the subject invention. 
     FIG. 5 a  illustrates the current wave form for the main switch of the FIG. 4 circuit. 
     FIG. 5 b  illustrates the current wave form for the second switch of the FIG. 4 circuit. 
     FIG. 5 c  illustrates the current wave form for the L 1  inductor of the FIG. 4 circuit. The L 1  current is also the input current of the converter. 
     FIG. 5 d  illustrates the current wave form for the L 2  inductor of the FIG. 4 circuit. 
     FIG. 5 e  illustrates the wave form for the output current of the FIG. 4 circuit. The output current is the sum of the two inductor currents. 
     FIG. 6 illustrates the on state of the FIG. 4 circuit. 
     FIG. 7 illustrates the off state of the FIG. 4 circuit. 
     FIG. 8 illustrates an embodiment of the FIG. 4 circuit in which the main switch is implemented with a power mosfet and the second switch is implemented with a diode. 
     FIG. 9 illustrates an embodiment of the FIG. 4 circuit in which the two inductors are combined in a coupled inductor on a common core. 
     FIG. 10 illustrates an embodiment of the FIG. 4 circuit in which the main switch is replaced by a generalized active reset switching cell to achieve a converter with zero voltage switching for all switches for all transitions. 
     FIG. 11 illustrates an embodiment of the FIG. 4 circuit similar to the FIG. 9 embodiment in which both switches are implemented using power mosfets. 
     FIG. 12 illustrates an embodiment of the FIG. 4 circuit in which the two inductors are replaced with two coupled inductors and the capacitor is split into two capacitors. By adjusting the coupling coefficient in a specified manner this circuit can achieve zero ripple at both input and output. 
     FIG. 13 illustrates an embodiment of the FIG. 4 circuit in which both input and output currents can be made to be zero ripple by suitable choice of leakage inductances and open circuit inductances. 
     FIG. 14 illustrates a magnetic structure that can accomplish the coupling coefficients necessary to achieve zero ripple at both input and output. 
     FIG. 15 illustrates an embodiment of the FIG. 4 circuit in which chokes are added that can reduce the input and output ripple currents to near zero. 
     FIG. 16 illustrates a boost type optimal topology converter according to the subject invention. 
     FIG. 17 a  illustrates the current wave form for the main switch of the FIG. 16 circuit. 
     FIG. 17 b  illustrates the current wave form for the second switch of the FIG. 16 circuit. 
     FIG. 17 c  illustrates the current wave form for the L 1  inductor of the FIG. 16 circuit. 
     FIG. 17 d  illustrates the current wave form for the L 2  inductor of the FIG. 16 circuit. The L 2  current is also the output current of the converter. 
     FIG. 17 e  illustrates the wave form for the input current of the FIG. 16 circuit. The input current is the sum of the two inductor currents. 
     FIG. 18 illustrates the on state of the FIG. 16 circuit. 
     FIG. 19 illustrates the off state of the FIG. 16 circuit. 
     FIG. 20 illustrates an embodiment of the FIG. 16 circuit in which the main switch is implemented with a power mosfet and the second switch is implemented with a diode. 
     FIG. 21 illustrates an embodiment of the FIG. 16 circuit in which the two inductors are combined in a coupled inductor on a common core. 
     FIG. 22 illustrates an embodiment of the FIG. 16 circuit in which the main switch is replaced by a generalized active reset switching cell to achieve a converter with zero voltage switching for all switches for all transitions. 
     FIG. 23 illustrates an embodiment of the FIG. 16 circuit similar to the FIG. 21 embodiment in which both switches are implemented using power mosfets. 
     FIG. 24 illustrates an embodiment of the FIG. 16 circuit in which the two inductors are replaced with two coupled inductors and the capacitor is split into two capacitors. By adjusting the coupling coefficient and open circuit inductances in a specified manner this circuit can achieve zero ripple at both input and output. 
     FIG. 25 illustrates an embodiment of the FIG. 16 circuit in which both input and output currents can be made to be zero ripple by suitable choice of coupling coefficient and open circuit inductances. 
     FIG. 26 illustrates an embodiment of the FIG. 16 circuit in which chokes are added that can reduce the input and output ripple currents to near zero. 
     
       
         
               
             
               
               
               
             
           
               
                   
               
               
                 Reference Numerals 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 100 DC input voltage source 
                 101 inductor 
               
               
                   
                 102 node 
                 103 node 
               
               
                   
                 104 switch 
                 105 node 
               
               
                   
                 106 capacitor 
                 107 node 
               
               
                   
                 108 switch 
                 109 inductor 
               
               
                   
                 110 capacitor 
                 111 load 
               
               
                   
                 200 DC input voltage source 
                 201 node 
               
               
                   
                 202 node 
                 203 switch 
               
               
                   
                 204 node 
                 205 inductor 
               
               
                   
                 206 switch 
                 207 node 
               
               
                   
                 208 capacitor 
                 209 inductor 
               
               
                   
                 210 node 
                 211 capacitor 
               
               
                   
                 212 load 
               
               
                   
                   
               
             
          
         
       
     
    
    
     SUMMARY 
     The subject invention uses a pair of inductors arranged so that their AC winding voltages are equal, a pair of switches, and a coupling capacitor to achieve buck and boost converters with non-pulsating input and output currents. The most preferred embodiment couples the two inductors on a common core so that only one large magnetic circuit element is required. Embodiments that provide zero voltage switching and zero ripple currents are also described. 
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Buck Derived Topology 
     FIG. 4 illustrates a buck type converter circuit with two inductors and a coupling capacitor connecting the two inductors. The circuit achieves both non-pulsating input current and non-pulsating output current. This fact is not obvious, but it can be seen that the converter can be arranged as a three terminal network, one terminal connecting the switching network to the load positive, one terminal connecting L 1  to the source positive, and one terminal connecting L 2  to both the source negative and the load negative. Since both of the terminals connected to the inductors must have non-pulsating current then the terminal connected to the load positive must also have non-pulsating current. This result is based on the Law of Conservation of Charge. 
     Referring to FIG. 4 there is shown a DC to DC converter circuit in which an input DC voltage is converted into an output DC voltage. The circuit requires an input source of substantially DC voltage, a pair of inductors, a pair of switches, and a capacitor coupling the two inductors and the switches. For purposes of the operational state analysis, it is assumed that the coupling capacitor is sufficiently large that the voltage developed across the capacitor is approximately constant over a switching interval and equal to the input DC source voltage. We will also assume for purposes of analysis that the inductors are large so that the current in the inductors is invariant over a switching cycle. Also, for purposes of the operational state analysis, it is assumed that the input DC voltage source has sufficiently low source impedance that the voltage developed across the input DC voltage source is approximately constant over a switching interval. It will finally be assumed that the power switches are ideal; that is, lossless and able to carry current in either direction. 
     Structure 
     The structure of the circuit of the subject invention is shown in FIG. 4. A positive terminal of a DC input voltage source  100  is connected to a dotted terminal of an inductor  101 . A negative terminal of source  100  is connected to a node  102 . An undotted terminal of inductor  101  is connected to a node  103 . The node  103  is connected to a first terminal of a capacitor  106  and to a first terminal of a switch  104 . A second terminal of switch  104  is connected to a node  105 . A second terminal of capacitor  106  is connected to a node  107 . A first terminal of a switch  108  is connected to node  107 . A second terminal of switch  108  is connected to node  105 . An undotted terminal of an inductor  109  is connected to node  107 . A dotted terminal of inductor  109  is connected to node  102 . A first terminal of a capacitor  110  is connected to node  105 . A second terminal of capacitor  110  is connected to node  102 . A first terminal of a load  111  is connected to node  105 . A second terminal of load  111  is connected to node  102 . 
     Operation 
     It is assumed in this analysis that the system has reached a settled operating condition. Except for the short, but finite, switching intervals there are two states of the circuit of FIG. 4, an on state and an off state. Consider an initial condition as illustrated in FIG.  7 . The initial condition represents the on state. During the initial condition the switch  104  is on (closed) and the switch  108  is off (open). The current wave forms are illustrated in FIGS. 5 a  and  5   b.  The current in the inductor  101  is flowing from left to right into the dotted terminal and out of the undotted terminal. The current in the inductor  109  is flowing from right to left into the dotted terminal and out of the undotted terminal. The inductor current wave forms are illustrated in FIGS. 5 c  and  5   d.  The current in both inductors will be increasing in value during the on state. Since the switch  108  is off (open) the current in the capacitor  106  will be equal to the current in the inductor  109 . The voltage of the first terminal of capacitor  106  is equal to the load voltage so the voltage at the undotted terminal of the inductor  109  will be negative with respect to the voltage at the dotted terminal of the inductor  109 . The current flowing through the switch  104  is equal to the sum of the currents in the inductors  101  and  109 . The switch  104  current is equal to the current in the load network consisting of capacitor  110  and load  111 . The current in the load network is illustrated in FIG. 5 e.  Notice that the load network current is equal to the sum of the two inductor currents and also equal to the sum of the two switch currents. At a time determined by the control circuit the switches change states so that switch  104  is off (open) and switch  108  is on (closed). The circuit is now in the off state as illustrated in FIG.  7 . The currents in the inductors  101  and  109  are the same as they were at the end of the on state, but now the current in the capacitor  106  reverses direction and becomes equal to the current in the inductor  101 . The current in the switch  108  is equal to the sum of the currents in the inductors  101  and  109 . The load network current will be equal to the switch  108  current. Since the switch transition time is very small and the current in an inductor cannot be rapidly changed the load network current at the beginning of the off state is the same as the load network current at the end of the on state. During the off state the currents in the inductors ramp down since the voltages at their undotted terminals is higher than the voltages at their dotted terminals. When the inductors currents have ramped down to their values at the beginning of the on state the switches change state again and the cycle repeats. 
     During the on state the applied voltage on the inductor  101  is just equal to the input voltage minus the output voltage, just as in the standard buck converter. For the inductor  109  the applied voltage during the on state is equal to the capacitor  106  voltage minus the output voltage. During the off state the voltage applied to the inductor  101  is equal to the output voltage plus the capacitor  106  voltage minus the input voltage and the voltage applied to the inductor  109  is equal to the output voltage. From Faraday&#39;s Law of Induction we know that in the steady state the sum of the volt second products applied to each inductor over a full cycle of operation must equal to zero. For the inductor  101  we can say that 
     
       
         0=( V   IN   −V   OUT )· D·T −( V   OUT   +V   C1   −V   IN )·(1− D )· T,   (1) 
       
     
     and for the inductor  109  we can say that 
     
       
         0=( V   C1   −V   OUT )· D·T−V   OUT ·(1− D )· T,   (2) 
       
     
     where V IN  is the DC source voltage, V OUT  is the load voltage, D is the duty cycle, T is the period, and V C1  is the voltage applied to the capacitor  106 . Solving equations (1) and (2) for V OUT  and V C1  yields 
     
       
           V   OUT   =D·V   IN   (3) 
       
     
     and 
     
       
           V   C1   =V   IN .  (4) 
       
     
     The input power will be 
     
       
           P   IN   =V   IN   ·I   L1   (5) 
       
     
     and the output power will be 
     
       
           P   OUT   =V   OUT   ·I   OUT   (6) 
       
     
     where P OUT  is the output power, P IN  is the input power, I L1  is the input current which is also the inductor  101  current, and I OUT  is the load network current. The load network current is also equal to the switch current which is also equal to the sum of the inductor currents or 
     
       
           I   OUT   =I   L1   +I   L2   (7) 
       
     
     where I L2  is the current in the inductor  109 . 
     Setting P OUT =P IN  and combining equations 3, 5, 6, and 7 and solving for I L1  and I L2 , we get 
     
       
           I   L1   =D·I   OUT   (8) 
       
     
     and 
     
       
           I   L2 =(1− D )· I   OUT .  (9) 
       
     
     The results given by equations 3, 8, and 9 indicate that the inductor current is a function of line and load voltage because of the duty cycle dependence. When the input and output voltages are nearly equal almost all of the load current flows in the L 1  inductor  101  and the current in the L 2  inductor  109  is near zero. When the output voltage is much less than the input voltage almost all of the load current flows in the L 2  inductor  109  and only a small fraction of the load current flows in the L 1  inductor  101 . 
     Related Embodiments 
     FIG. 8 illustrates an embodiment of the FIG. 4 circuit in which the S 1  switch  104  is implemented with a power mosfet and the S 2  switch  108  is implemented with a diode. 
     FIG. 9 illustrates another embodiment of the FIG. 4 circuit in which the two inductors are combined on a single magnetic core. Notice that the dotted terminals of the two inductors are both connected to AC grounds, i.e., points of DC potential where the AC voltage is invariant. Notice also that the two undotted terminals are connected to opposing terminals of a capacitor which is sufficiently large that, in the steady state, the capacitor&#39;s voltage is invariant. Because of the capacitor connection at the undotted terminals the AC wave form at each undotted terminal is identical so that we can conclude that the AC wave form of each inductor is identical which suggests that the two inductors can readily be combined on a common core with a high degree of magnetic coupling. The magnetic coupling suggests another possibility, that of ripple current elimination at one terminal. In this case it would be desirable to eliminate the current ripple in the L 1  inductor. Eliminating the ripple in the L 2  inductor can also be accomplished but the benefits of eliminating the L 2  ripple are not obvious. Consider the on state where the applied voltage to the L 1  inductor is the difference between the input source voltage and the output voltage and the voltage applied to the L 2  inductor is the same as the L 1  inductor from equations 1, 2, and 4. A coupled inductor model as described by J. K. Watson in his book “Applications of Magnetics” on pages 270-273 is used here. We can model the two magnetic elements as a coupled inductor or transformer with mutual inductance, M, open circuit inductance on the L 1  side equal to L 11 , open circuit inductance on the L 2  side equal to L 22 , coupling coefficient equal to k, and leakage inductance on the L 1  side equal to l 1 . Let us further define the time rate of change of the L 1  inductor current to be I d1 , and the time rate of change of the L 2  current to be I d2 . Also let us define the voltage difference between the input and output to be 
     
       
           V   Diff   =V   IN   −V   OUT . 
       
     
     During the on state for the L 1  side of the coupled magnetic we know that 
     
       
           V   Diff   =L   11   ·I   d1   +M·I   d2   (10) 
       
     
     and for the L 2  side 
     
       
           V   Diff   =L   22   ·I   d2   +M·I   d1 .  (11) 
       
     
     Solving equations 10 and 11 for I d1  we get                I   d1     =       V   Diff     ·         (       L   22     -   M     )       (         L   11     ·     L   22       -     M   2       )       .               (   12   )                                
     If we set the numerator equal to zero we have the condition necessary for zero input current ripple, i.e.,                L   22     =     M   =     k   ·           L   11     ·     L   22         .                 (   13   )                                
     If we use the result from Watson&#39;s model that 
     
       
           l   1   =L   11 ·(1− k   2 )  (14) 
       
     
     and equation 13, eliminating k, we get the result for zero input ripple current 
     
       
           l   1   =L   11   −L   22 .  (15) 
       
     
     Equation 15 expresses the zero ripple condition in terms of readily measurable quantities. In order to obtain the result indicated by equation 15 for zero input ripple current it is necessary to use more turns on the L 1  winding than on the L 2  winding. The leakage inductance and mutual coupling can be manipulated by altering the relative physical placement of the windings, and, if the two windings are placed on different core legs, then the open circuit inductances and the mutual coupling can be affected by altering the reluctance of the magnetic path connecting the two legs, which can be done by altering a gap in the magnetic path connecting the two legs on which the L 1  and L 2  windings are placed. 
     FIG. 10 illustrates another embodiment similar to the FIG. 9 embodiment in which the switch S 1  is replaced by a zero voltage switching active reset switching cell consisting of S 1 , S 2 , D 2 , L_RES, and C_RESET. The operation of the switching cell is described in detail in the patent application entitled “Zero Voltage Switching Active Reset Power Converters” filed on Jun. 5, 2000 by this inventor. The subject of this prior patent application is closely related to the FIG. 10 embodiment and that prior application is incorporated herein. 
     FIG. 11 illustrates another embodiment similar to the FIG. 9 embodiment in which the two switches are both implemented using power mosfets. 
     FIG. 12 illustrates an embodiment in which the coupling capacitor is split into two capacitors in series and the L 1  and L 2  inductors each have a second coupled winding attached to the connection point of the two coupling capacitors. With the two coupled inductor arrangement both the L 1  ripple current and the L 2  ripple current can be made to be zero simultaneously using the same procedure used to obtain the zero input ripple result for the FIG. 9 circuit. Since the converter is a three terminal network and two of the three terminals can have zero ripple then the third terminal can be made to have zero ripple. This result is based on the Law of Conservation of Charge. In this case both the input and the output current can be made to have zero current ripple. The AC winding voltage for all four windings is the same. During the on state the applied voltage is V Diff . To obtain zero input ripple we require that l 1 =L 11 −L 33A , where L 33A  is the open circuit inductance of the L 3 A winding which is coupled to the L 1  winding. To also obtain zero output ripple we require that l 2 =L 22 −L 33B , where L 33B  is the open circuit inductance of the L 3 B winding which is coupled to L 2  and l 2  is the leakage inductance of the L 2  winding, which is measured with the L 3 B winding shorted. By obtaining both zero ripple in the L 1  winding and zero ripple in the L 2  winding we obtain zero ripple at the output since we have a three terminal network and two of the terminals of our three terminal network have zero ripple so that the third terminal, the output, must also have zero ripple. 
     FIG. 13 illustrates an embodiment in which zero input ripple and zero output ripple can simultaneously be obtained using a single core structure as illustrated in FIG.  14 . In the FIG. 14 structure the L 1  and L 2  windings, which are wound on the outer legs, are uncoupled. Both the L 1  and L 2  windings are coupled to the center post of the core and the L 3  winding. The criteria for zero ripple is the same as for the FIG. 12 circuit, but in this case the L 3  windings are integrated into a single winding and the two cores are integrated onto a common core with effectively two independent coupled inductors on the same core. Flux generated in the L 1  winding will not pass through the L 2  winding because of the gap in the right outer leg and the fact that the center post has no gap and thus presents a magnetic short circuit to flux generated in the left outer leg. Similarly flux generated in the L 2  winding will pass through the center post but will not pass through the left outer leg because of the gap in the left outer leg. L 1 D refers to the dotted terminal of the L 1  winding, L 1 UD refers to the undotted terminal of the L 1  winding, similarly for the L 2  and L 3  windings. 
     FIG. 15 illustrates another embodiment similar to the FIG. 13 embodiment but in this case all three windings, L 1 , L 2  and L 3 , are tightly coupled to each other and have the same number of turns. In this case all three windings can be colocated on the same core leg. Two small inductors are added, L_ 1 A and L_ 2 A, which reduce both the input ripple and output ripple to near zero levels. 
     Boost Derived Topology 
     FIG. 16 illustrates a boost type converter circuit with two inductors and a coupling capacitor connecting the two inductors. The circuit achieves both non-pulsating input current and non-pulsating output current. This fact is not obvious, but it can be seen that the converter can be arranged as a three terminal network, one terminal connecting the switching network to the input source positive, one terminal connecting L 2  to the output load positive, and one terminal connecting L 1  to both the source negative and the load negative. Since both of the terminals connected to the inductors must have non-pulsating current then the terminal connected to the input source must also have non-pulsating current. This result is based on the Law of Conservation of Charge. 
     Referring to FIG. 16 there is shown a DC to DC converter circuit in which an input DC voltage is converted into an output DC voltage. The circuit requires an input source of substantially DC voltage, a pair of inductors, a pair of switches, and a capacitor coupling the two inductors and the switches. For purposes of the operational state analysis, it is assumed that the coupling capacitor is sufficiently large that the voltage developed across the capacitor is approximately constant over a switching interval and equal to the output DC load voltage. We will also assume for purposes of analysis that the inductors are large so that the current in the inductors are invariant over a switching cycle. Also, for purposes of the operational state analysis, it is assumed that the input DC voltage source has sufficiently low source impedance that the voltage developed across the input DC voltage source is approximately constant over a switching interval. It will finally be assumed that the power switches are ideal; that is, lossless and able to carry current in either direction. 
     Structure 
     The structure of the circuit of the subject invention is shown in FIG. 16. A positive terminal of a DC input voltage source  200  is connected to a node  201 . A negative terminal of source  200  is connected to a node  202 . A first terminal of a switch  203  is connected to node  201 . A second terminal of switch  203  is connected to a node  204 . An undotted terminal of an inductor  205  is connected to node  204 . A dotted terminal of inductor  205  is connected to the node  202 . The node  204  is connected to a first terminal of a capacitor  208 . A second terminal of capacitor  208  is connected to a node  207 . A first terminal of a switch  206  is connected to node  201 . A second terminal of switch  206  is connected to node  207 . An undotted terminal of an inductor  209  is connected to node  207 . A dotted terminal of inductor  209  is connected to a node  210 . A first terminal of a capacitor  211  is connected to node  210 . A second terminal of capacitor  211  is connected to node  202 . A first terminal of a load  212  is connected to node  210 . A second terminal of load  212  is connected to node  202 . 
     Operation 
     It is assumed in this analysis that the system has reached a settled operating condition. Except for the short, but finite, switching intervals there are two states of the circuit of FIG. 16, an on state and an off state. Consider an initial condition as illustrated in FIG.  18 . The initial condition represents the on state. During the initial condition the switch  203  is on (closed) and the switch  206  is off (open). The current wave forms of the switches are illustrated in FIGS. 17 a  and  17   b.  The current in the inductor  205  is flowing from top to bottom into the undotted terminal and out of the dotted terminal. The current in the inductor  209  is flowing from left to right into the undotted terminal and out of the dotted terminal. The inductor current wave forms are illustrated in FIGS. 17 c  and  17   d.  The current in both inductors will be increasing in value during the on state. Since the switch  206  is off (open) the current in the capacitor  208  will be equal to the current in the inductor  209 . It will be shown that the applied voltage to the capacitor  208  is equal to the output voltage. The voltage at the first terminal of capacitor  208  is equal to the input voltage so the voltage at the undotted terminal of the inductor  209  will be positive with respect to the voltage at the dotted terminal of the inductor  209 . The current flowing through the switch  203  is equal to the sum of the currents in the inductors  203  and  209 . The switch  203  current is equal to the input source current. The input current is illustrated in FIG. 17 e.  Notice that the input current is equal to the sum of the two inductor currents and also equal to the sum of the two switch currents. At a time determined by the control circuit the switches change states so that switch  203  is off (open) and switch  206  is on (closed). The circuit is now in the off state as illustrated in FIG.  19 . The currents in the inductors  205  and  209  are the same as they were at the end of the on state, but now the current in the capacitor  208  reverses direction and becomes equal to the current in the inductor  205 . The current in the switch  206  is equal to the sum of the currents in the inductors  205  and  209 . The input current will be equal to the switch  206  current. Since the switch transition time is very small and the current in an inductor cannot be rapidly changed the input current at the beginning of the off state is the same as the input current at the end of the on state. During the off state the currents in the inductors ramp down since the voltages at their dotted terminals is higher than the voltages at their undotted terminals. When the inductors currents have ramped down to their values at the beginning of the on state the switches change state again and the cycle repeats. 
     During the on state the applied voltage on the inductor  205  is just equal to the input voltage, just as in the standard boost converter. For the inductor  209  the applied voltage during the on state is equal to the input voltage plus the capacitor  208  voltage minus the output voltage. During the off state the voltage applied to the inductor  205  is equal to the input voltage minus the capacitor  208  voltage and the voltage applied to the inductor  209  is equal to the output voltage minus the input voltage. From Faraday&#39;s Law of Induction we know that in the steady state the sum of the volt second products applied to each inductor over a full cycle of operation must equal to zero. For the inductor  205  we can say that 
     
       
         0= V   IN   ·D·T −( V   C1   −V   IN )·(1− D )· T,   (16) 
       
     
     and for the inductor  209  we can say that 
     
       
         0=( V   C1   +V   IN   −V   OUT )· D·T −( V   OUT   −V   IN )·(1− D )· T,   (17) 
       
     
     where V IN  is the DC source voltage, V OUT  is the load voltage, D is the duty cycle, T is the period, and V C1  is the voltage applied to the capacitor  208 . Solving equations (16) and (17) for V OUT  and V C1  yields                V   OUT     =       V   IN       (     1   -   D     )               (   18   )                                
     and 
     
       
           V   C1   =V   OUT .  (19) 
       
     
     The input power will be 
     
       
           P   IN   =V   IN   ·I   IN   (20) 
       
     
     and the output power will be 
     
       
           P   OUT   =V   OUT   ·I   OUT   (21) 
       
     
     where P OUT  is the output power, P IN  is the input power, I IN  is the input current, and I OUT  is the load network current, which is also the inductor  209  current, I L2 . The input current is also equal to the switch current which is also equal to the sum of the inductor currents or 
     
       
         I IN   =I   L1   +I   L2   (22) 
       
     
     where I L1  is the current in the inductor  205 . 
     Setting P OUT =P IN  and combining equations 18, 20, 21, and 22 and solving for I L1  and I L2 , we get 
     
       
           I   L1   =D·I   IN   (23) 
       
     
     and 
     
       
           L2 =(1− D )· I   IN .  (24) 
       
     
     The results given by equations 18, 23, and 24 indicate that the inductor current is a function of line and load voltage because of the duty cycle dependence. When the input and output voltages are nearly equal almost all of the input current flows in the L 2  inductor  209  and the current in the L 1  inductor  205  is near zero. When the output voltage is much more than the input voltage almost all of the input current flows in the L 1  inductor  205  and only a small fraction of the input current flows in the L 2  inductor  209 . 
     Related Embodiments 
     FIG. 20 illustrates an embodiment of the FIG. 16 circuit in which the S 1  switch  203  is implemented with a power mosfet and the S 2  switch  206 , labeled D 1  in FIG. 20, is implemented with a diode. 
     FIG. 21 illustrates another embodiment of the FIG. 16 circuit in which the two inductors are combined on a single magnetic core. Notice that the dotted terminals of the two inductors are both connected to AC grounds, i.e., points of DC potential where the AC voltage is invariant. Notice also that the two undotted terminals are connected to opposing terminals of a capacitor which is sufficiently large that, in the steady state, the capacitor&#39;s voltage is invariant. Because of the capacitor connection at the undotted terminals the AC wave form at each undotted terminal is identical so that we can conclude that the AC wave form of each inductor is identical which suggests that the two inductors can readily be combined on a common core with a high degree of magnetic coupling. The magnetic coupling suggests another possibility, that of ripple current elimination at one terminal. In this case it would be desirable to eliminate the current ripple in the L 2  inductor. Eliminating the ripple in the L 1  inductor can also be accomplished but the benefits of eliminating the L 1  ripple are not obvious. Consider the on state where the applied voltage to the L 1  inductor is the input source voltage and the voltage applied to the L 2  inductor is the same as the L 1  inductor from equations 16, 17, and 19. A coupled inductor model as described by J. K. Watson in his book “Applications of Magnetics” on pages 270-273 is used here. We can model the two magnetic elements as a coupled inductor or transformer with mutual inductance, M, open circuit inductance on the L 1  side equal to L 11 , open circuit inductance on the L 2  side equal to L 22 , coupling coefficient equal to k, and leakage inductance on the L 2  side equal to I 2 . Let us further define the time rate of change of the L 1  inductor current to be I d1 , and the time rate of change of the L 2  inductor current to be I d2 . During the on state for the L 1  side of the coupled magnetic we know that 
     
       
           V   IN   =L   11   ·I   d1   +M·I   d2   (25) 
       
     
     and for the L 2  side 
     
       
           V   IN   =L   22   ·I   d2   +M·I   d1 .  (26) 
       
     
     Solving equations 25 and 26 for I d2  we get                I   d2     =       V   IN     ·         (       L   11     -   M     )       (         L   11     ·     L   22       -     M   2       )       .               (   27   )                                
     If we set the numerator equal to zero we have the condition necessary for zero output current ripple, i.e.,                L   11     =     M   =     k   ·           L   11     ·     L   22         .                 (   28   )                                
     If we use the result from Watson&#39;s model that 
       l   2   =L   22 ·(1− k   2 )  (29) 
     and equation 28, eliminating k, we get the result for zero output ripple current 
     
       
           l   2   =L   22   −L   11 .  (30) 
       
     
     Equation 30 expresses the zero ripple condition in terms of readily measurable quantities. In order to obtain the result indicated by equation 30 for zero output ripple current it is necessary to use more turns on the L 2  winding than on the L 1  winding. The leakage inductance and mutual coupling can be manipulated by altering the relative physical placement of the windings, and, if the two windings are placed on different core legs, then the open circuit inductances and mutual coupling can be affected by altering the reluctance of the magnetic path connecting the two legs, which can be done by altering a gap in the magnetic path connecting the two legs on which the L 1  and L 2  windings are placed. 
     FIG. 22 illustrates another embodiment similar to the FIG. 21 embodiment in which the switch S 1  is replaced by a zero voltage switching active reset switching cell consisting of S 1 , S 2 , D 2 , L_RES, and C_RESET. The operation of the switching cell is described in detail in the patent application entitled “Zero Voltage Switching Active Reset Power Converters” filed on Jun. 5, 2000 by this inventor. The subject of this prior patent application is closely related to the FIG. 22 embodiment and that prior application is incorporated herein. 
     FIG. 23 illustrates another embodiment similar to the FIG. 21 embodiment in which the two switches are both implemented using power mosfets. 
     FIG. 24 illustrates an embodiment in which the coupling capacitor is split into two capacitors in series and the L 1  and L 2  inductors each have a second coupled winding attached to the connection point of the two coupling capacitors. With the two coupled inductor arrangement both the L 1  ripple current and the L 2  ripple current can be made to be zero simultaneously using the same procedure used to obtain the zero output ripple result for the FIG. 21 circuit. Since the converter is a three terminal network and two of the three terminals can have zero ripple then the third terminal can be made to have zero ripple when the ripple at the other two terminals is zero. This result is based on the Law of Conservation of Charge. In this case both the input and the output current can be made to have zero current ripple. The AC winding voltage for all four windings is the same. During the on state the applied voltage is V IN . To obtain zero output ripple we require that l 2 =L 22 −L 33B , where L 33B  is the open circuit inductance of the L 3 B winding which is coupled to the L 2  winding. To also obtain zero input ripple we require that l 1 =L 11 −L 33A , where L 33A  is the open circuit inductance of the L 3 A winding which is coupled to L 1  and l 1  is the leakage inductance of the L 1  winding, which is measured with the L 3 A winding shorted. By obtaining both zero ripple in the L 1  winding and zero ripple in the L 2  winding we obtain zero ripple at the input since we have a three terminal network and two of the terminals of our three terminal network have zero ripple so that the third terminal, the input, must also have zero ripple. 
     FIG. 25 illustrates an embodiment in which zero input ripple and zero output ripple can simultaneously be obtained using a single core structure as illustrated in FIG.  14 . In the FIG. 14 structure the L 1  and L 2  windings, which are wound on the outer legs, are uncoupled. Both the L 1  and L 2  windings are coupled to the center post of the core and the L 3  winding. The criteria for zero ripple is the same as for the FIG. 24 circuit, but in this case the L 3  windings are integrated into a single winding and the two cores are integrated onto a common core with effectively two independent coupled inductors on the same core. Flux generated in the L 1  winding will not pass through the L 2  winding because of the gap in the right outer leg and the fact that the center post has no gap and thus presents a magnetic short circuit to flux generated in the left outer leg. Similarly flux generated in the L 2  winding will pass through the center post but will not pass through the left outer leg because of the gap in the left outer leg. L 1 D refers to the dotted terminal of the L 1  winding, L 1 UD refers to the undotted terminal of the L 1  winding, similarly for the L 2  and L 3  windings. 
     FIG. 26 illustrates another embodiment similar to the FIG. 24 embodiment but in this case all three windings, L 1 , L 2  and L 3 , are tightly coupled to each other and have the same number of turns. In this case all three windings can be colocated on the same core leg. Two small inductors are added, L_ 1 A and L_ 2 A, which reduce both the input ripple and output ripple to near zero levels. 
     Conclusions, Ramifications, and Scope of Invention 
     Thus the reader will see that the DC to DC converter circuits of the subject invention provides a relatively simple mechanism for converting a DC voltage at one level to a different DC voltage at a different level with both continuous input and output currents. In addition, these results can be achieved using a single coupled inductor. 
     While my above description contains many specificities, these should not be construed as limitations on the scope of the invention, but rather as exemplifications of preferred embodiments thereof. Many other variations are possible. For example, interleaved, parallel DC to DC converters with two or more parallel DC to DC converter sections using common input and output filter capacitors; DC to DC converters similar to those shown but which have instead high AC ripple voltages on input filter capacitors; DC to DC converters, similar to those shown in the drawings, but where the DC input source is instead a varying rectified AC signal. Accordingly, the scope of the invention should be determined not by the embodiments illustrated, but by the appended claims and their legal equivalents.