Abstract:
A vertical memory device on a silicon semiconductor substrate is formed by the following steps. Form an array of isolation silicon oxide structures on the surface of the silicon semiconductor substrate. Form a floating gate trench in the silicon semiconductor substrate between the silicon oxide structures in the array, the trench having trench sidewall surfaces. Dope the sidewalls of the floating gate trench with a threshold implant through the trench sidewall surfaces. Form a tunnel oxide layer on the trench sidewall surfaces, the tunnel oxide layer having an outer surface. Form a floating gate electrode in the trench on the outer surface of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Form an interelectrode dielectric layer over the top surface of the floating gate electrode. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode. Form a source line by the step of performing a self-aligned etch followed by a source line implant.

Description:
This is a division of patent application Serial No. 08/985,647, filing date Dec. 5, 1997 now U.S. Pat. No. 5,960,284, Method For Forming Vertical Channel Flash Memory Cell And Device Manufactured Thereby, assigned to the same assignee as the present invention. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to semiconductor memory devices and more particularly to vertical channel flash memory devices. 
     2. Description of Related Art 
     1. To maintain enough current through the channel, the memory cell takes more area with traditional ETOX (EPROM with Tunnel Oxide) structure since the channel is parallel to the wafer surface. 
     2. During the programming and the erasing procedures, the tunneling electron always needs to traverse (pass through) part of the channel area resulting in charge trapping and transconductance degradation. 
     SUMMARY OF THE INVENTION 
     In accordance of this invention, a vertical memory device on a silicon semiconductor substrate is provided including the following features. An array of isolation silicon oxide structures are formed on the surface of the silicon semiconductor substrate. There is a floating gate trench in the silicon semiconductor substrate between the silicon oxide structures in the array, the trench having trench sidewall surfaces. The sidewalls of the floating gate trench are doped with a threshold implant through the trench sidewall surfaces. There is a tunnel oxide layer on the trench sidewall surfaces. The tunnel oxide layer has an outer surface. There is a floating gate electrode in the trench on the outer surface of the tunnel oxide layer. Source/drain regions are formed in the substrate self-aligned with the floating gate electrode. An interelectrode dielectric layer overlies the top surface of the floating gate electrode. A control gate electrode overlies the interelectrode dielectric layer above the top surface of the floating gate electrode. There is an ion implanted source line formed in the substrate after a self-aligned etch. 
     Preferably, the trench has a depth from about 2,000 Å to about 8,000 Å. The tunnel oxide layer has a thickness from about 70 Å to about 150 Å. The floating gate electrode comprises doped polysilicon having a thickness of from about 1,000 Å to about 4,000 Å. The threshold implant comprises ion implantation of boron fluoride ions which were ion implanted at an energy from about 20 keV to about 50 keV with a dose from about 1 E 12 ions/cm 2  to about 5 E 13 ions/cm 2 . The source/drain implant comprises arsenic which was ion implanted at an energy from about 30 keV to about 55 keV with a dose from about 1 E 15 ions/cm 2  to about 5.5 E 15 ions/cm 2  with a dopant concentration after annealing from about 1 E 20 atoms/cm 3  to about 5 E 21 atoms/cm 3 . A source line was formed after a self-aligned etch to a depth from about 1,000 Å to about 3,000 Å on the source side of the trench. The source line was formed by an implant provided by ion implantation of dopant selected from the group consisting of arsenic and phosphorus ions implanted at an energy from about 30 keV to about 55 keV with a dose from about 1 E 14 ions/cm 2  to about 5 E 14 ions/cm 2 . 
     Features of this Invention 
     1. A cell structure in accordance with this invention uses a vertical channel rather than a traditional horizontal one. 
     2. Since the channel has a vertical orientation with respect to the wafer surface, the activity area of the cell in accordance with this invention can be larger while requiring less silicon surface area compared to a conventional cell with an ETOX structure. Therefore, the unit cell will requires less silicon surface area compared to a conventional one. 
     3. Only a single mask is required to conduct stacking gate etching of a memory cell and control gate etching of peripheral devices simultaneously instead of two masks employed separately for a conventional ETOX structure. 
     4. During the erasing procedure, the band-to-band hot hole phenomenon can be completely prevented with a memory cell, in accordance with this invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other aspects and advantages are explained and described below with reference to the accompanying drawings, in which: 
     FIG. 1A shows a plan view of a fragment of an EPROM device in accordance with this invention in an early stage of manufacture. FIG. 1B shows the device of FIG. 1A taken along line  1 B- 1 B′ in FIG.  1 A. 
     FIGS. 2A and 2B show the device of FIGS. 1A and 1B after etching of an active area pattern in the silicon nitride layer. FIG. 2B shows a section taken along line  2 B- 2 B′ of FIG.  2 A. 
     FIGS. 3A and 3B show the device of FIGS. 2A and 2B after growth of isolation field oxide (FOX) regions  18  where the pad oxide layer is exposed through windows through silicon nitride layer. 
     FIG. 3B shows a section taken along line  3 B- 3 B′ of FIG.  3 A. 
     FIGS. 4A and 4B show the device of FIGS. 3A and 3B after formation of second photoresist mask which comprises a floating gate mask with a transverse slot therethrough above the sites where the floating gates are to be formed. 
     FIG. 4B shows a section taken along line  4 B- 4 B′ of FIG.  4 A. 
     FIGS. 5A and 5B show the device of FIGS. 4A and 4B after etching of the pad oxide layer and down into the substrate to form a set of floating gate trenches to prepare space for floating gate electrodes formed over gate oxide layers. 
     FIG. 5B shows a section taken along line  5 B- 5 B′ of FIG.  5 A. 
     FIGS. 6A and 6B show the device of FIGS. 5A and 5B after a tilted angle cell threshold implant has been applied at a large tilt angle to make sure the sidewalls of the trenched silicon have the correct dosage in sidewall regions. FIG. 6B shows a section taken along line  6 B- 6 B′ of FIG.  6 A. 
     FIGS. 7A and 7B show the device of FIGS. 6A and 6B after the photoresist mask and the silicon nitride layer have both been stripped from the device. FIG. 7B shows a section taken along line  7 B- 7 B′ of FIG.  7 A. 
     FIGS. 8A and 8B show the device of FIGS. 7A and 7B after being subjected to a process of selectively etching back the polysilicon layer to remove the surplus polysilicon on the tunnel oxide layer above the spaces where the source/drain regions are to be formed as shown in FIG.  9 A. 
     FIGS. 9A and 9B show the device of FIGS. 8A and 8B during self-aligned S/D implantation of dopant ions in FIG. 9B into the exposed portions of substrate forming source/drain regions as shown in FIG.  9 A. 
     FIG. 9B shows a section taken along line  9 B- 9 B′ of FIG.  9 A. 
     FIG. 10B shows the device of FIG. 9B (in an elevational section) after an ONO (silicon oxide/silicon nitride/silicon oxide) interconductor dielectric layer has been grown to separate the floating gate electrodes from the control gate electrode to be formed next. 
     FIG. 10A is a section taken along line  10 A- 10 A′ of the device of FIG. 10B below the level of the ONO dielectric layer. 
     FIG. 11 shows a vertical section of the device of FIG. 10A taken along line  11 - 11 ′ therein through the source regions of the device which are separated by the FOX regions. 
     FIG. 12 shows the vertical section of device shown in FIG. 11 after removal of FOX regions (isolation oxide) located between the N+ source regions of the memory cell to a substantial depth within the substrate. 
     FIG. 13 shows the device of FIGS. 10,  11 , and  12  in plan view with additional parts of the device illustrated. 
     FIGS. 14-16 show the portions of the device of FIG. 13 for programming, erasing and reading operations respectively. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1A shows a plan view of a fragment of an EPROM device  10  in accordance with this invention in an early stage of manufacture. FIG. 1B shows the device  10  of FIG. 1A taken along line  1 B- 1 B′ in FIG.  1 A. The process of this invention, commences with formation of a pad oxide (thermal oxide) layer  14  on a P-doped silicon semiconductor substrate  12 . Then a silicon nitride layer  16  is deposited on pad oxide layer  14 . Then an active area (OD) photoresist mask PR 1  with windows W therethrough is formed over the silicon nitride layer  16  for use in defining an active region in the device  10 . 
     FIGS. 2A and 2B show the device  10  of FIGS. 1A and 1B after etching of an active area (OD) pattern in the silicon nitride layer  16 . FIG. 2B shows a section along line  2 B- 2 B′ of FIG.  2 A. Windows W are etched through layer  16  in the pattern of the windows W in the photoresist mask PR 1 . 
     FIGS. 3A and 3B show the device  10  of FIGS. 2A and 2B after growth of isolation field oxide (FOX) regions  18  where the pad oxide layer  14  is exposed through windows W through silicon nitride layer  16 . 
     FIG. 3B shows a section taken along line  3 B- 3 B′ of FIG.  3 A. 
     FIGS. 4A and 4B show the device  10  of FIGS. 3A and 3B after formation of second photoresist mask PR 2  comprising a floating gate mask with a transverse slot SL therethrough above the sites where the floating gates are to be formed. 
     FIG. 4B shows a section taken along line  4 B- 4 B′ of FIG.  4 A. 
     Where the slot SL reaches through the mask PR 2  (separating mask PR 2  into a pair of parallel strips) the silicon nitride layer  16  is stripped away exposing the pad oxide layer  14  and the FOX regions  18 , as seen in the section shown in FIG. 4B in preparation for forming a set of trenches  20  (FIG. 5A and 5B) in the silicon semiconductor substrate  12  which are to be defined by the field oxide (FOX) regions  18  and the slot SL in the second photoresist mask PR 2 . 
     FIGS. 5A and 5B show the device  10  of FIGS. 4A and 4B after etching of the pad oxide layer  14  and down into the substrate  12  to form a set of floating gate trenches  20  through the slot SL in mask PR 2  to prepare space for floating gate electrodes  24  formed over gate oxide layers  23 . The trenches  20  in the silicon semiconductor substrate  12  are self-aligned with the FOX regions  18 . 
     FIG. 5B shows a section taken along line  5 B- 5 B′ of FIG.  5 A. The trenches  20  have a depth from about 2,000 Å to about 8,000 Å. 
     FIGS. 6A and 6B show the device  10  of FIGS. 5A and 5B after a tilted angle cell threshold implant of boron fluoride BF 2  has been applied into the sidewall surface regions and bottom surface regions  22  of the trenches  20  at a large tilt angle Θ to make sure the sidewall surface regions and bottom surface regions  22  of the trenches  20  in silicon semiconductor substrate  12  have the correct dosage in the sidewall surface regions and the bottom surface regions  22 . 
     FIG. 6B shows a section taken along line  6 B- 6 B′ of FIG.  6 A. 
     The dopant comprises boron fluoride ions which were ion implanted at an energy from about 20 keV to about 50 keV with a dose from about 1 E 12 ions/cm 2  to about 5 E 13 ions/cm 2 . After annealing the concentration of the dopant was from about 5 E 16 atoms/cm 3  to about 5 E 17 atoms/cm 3 . 
     FIGS. 7A and 7B show the device  10  of FIGS. 6A and 6B after the photoresist mask PR 2  and the silicon nitride layer  16  have both been stripped from the device  10 . 
     FIG. 7B shows a section taken along line  7 B- 7 B′ of FIG.  7 A. 
     Thereafter a tunnel oxide (silicon oxide) layer  23  is grown covering the sidewalls and the bottom of the trenches  20  and reaching to the top of the trenches  20 . Next, a blanket floating gate polysilicon is deposited to fill up the trenches  20  covering the tunnel oxide layer  23  and FOX regions  18 . The tunnel oxide layer  23  has a thickness from about 70 Å to about 150 Å, and the floating gate electrode has a thickness of from about 1,000 Å to about 4,000 Å. 
     Subsequently, referring to FIGS. 8A and 8B the device  10  of FIGS. 7A and 7B is subjected to selectively etching back the polysilicon layer  24 , reaching to the tops of the trenches  20  as shown in FIGS. 8B,  9 B and  10 B. Etching is employed to remove the surplus amount of polysilicon layer  24  on the tunnel oxide layer  23  above spaces where the source/drain regions S/D are to be formed as shown in FIG.  9 A. 
     Referring to FIGS. 9A and 9B the device  10  of FIGS. 8A and 8B is shown during self-aligned S/D implantation of N+ dopant ions  25  in FIG. 9B into the exposed portions of substrate  12  forming source regions S and drain regions D as shown in FIG. 9A in the surface of substrate  12  located on opposite sides of the combination of each gate electrode  24  and its associated tunnel oxide layer  23  and juxtaposed with the doped sidewall regions  22 . 
     FIG. 9B shows a section taken along line  9 B- 9 B′ of FIG.  9 A. 
     The dopant  25  comprises arsenic ions which were ion implanted at an energy from about 30 keV to about 55 keV with a dose from about 1 E 15 ions/cm 2  to about 5.5 E 15 ions/cm 2 . The resulting dopant concentration after annealing was from about 1 E 20 atoms/cm 3  to about 5 E 21 atoms/cm 3 . 
     Referring to FIG. 10B the device  10  of FIG. 9B is shown (in an elevational section) after an ONO (silicon oxide/silicon nitride/silicon oxide) interconductor dielectric layer  26  has been grown to separate the floating gate electrodes  24  from the control gate electrode to be formed next. The ONO interconductor dielectric layer  26  covers the tops of the floating gate electrodes  24 , reaching across the tops of the trenches  20 , shown to be on the same plane therewith in FIG.  10 B and the layer  26  reaches over the tops of the FOX regions  18  as shown in FIG.  10 B. 
     FIG. 10A is a section taken along line  10 A- 10 A′ of the device of FIG. 10B below the level of the ONO dielectric layer  26 . 
     Above ONO dielectric layer  26 , a polysilicon layer  28  and tungsten silicide layer  30  were deposited on a step-by-step basis in preparation for forming the control gate electrode  30 ,  28  seen in phantom in FIG.  10 A. The control gate electrode  30 ,  28  is crosses above the tops of the trenches  20  separated therefrom by the ONO layer  26 . 
     The pattern of the control gate polysilicon layer  28 , and tungsten silicide layer  30  were defined by a conventional control gate mask (not shown) to produce the pattern shown in phantom in FIG.  10 A. 
     FIG. 11 shows a vertical section of the device  10  of FIG. 10A taken along line  11 - 11 ′ therein. FIG. 11 shows a section passing through the source regions S of the device  10  which are separated by the FOX regions  18 . 
     FIG. 12 shows the vertical section of device  10  shown in FIG. 11, but after a self-aligned source line mask (not shown) has been employed to form a source line by removing the FOX regions  18  (isolation oxide) located between the N+ source regions S of the memory cell to a depth from about 1,000 Å to about 3,000 Å. Ion implantation with ions  120  for the source line  34  is also aligned by the same mask as was used to remove the FOX regions  18  leaving valleys  118  in FIG. 11 where the FOX regions  18  had been. The source line implant with ions  120  comprises ion implantation of arsenic or phosphorus ions which are ion implanted at an energy from about 30 keV to about 55 keV with a dose from about 1 E 14 ions/cm 2  to about 5 E 14 ions/cm 2 . 
     After tungsten silicide annealing, N+/P+ S/D implants are made for the peripheral devices which are conducted with the appropriate masks (not shown). The dopant comprises arsenic ions which were ion implanted at an energy from about 30 keV to about 55 keV with a dose from about 1 E 15 ions/cm 2  to about 5 E 15 ions/cm 2 . After annealing, the concentration of the dopant was from about 1 E 20 atoms/cm 3  to about 5 E 21 atoms/cm 3 . 
     FIG. 13 shows the device of FIGS. 10,  11 , and  12  (in plan view) illustrating additional parts of the device  10 . 
     As the ILD (Inter Layer Dielectric) is coated, contact holes and contact implants are defined by a contact mask. 
     After a tungsten plug is deposited and etched back, the metal layer is coated and defined by a metal layer mask. Then IMD (Inter Metal Dielectric), VIA and METAL masks are used to conduct the back end process. 
     FIGS. 14-16 show the portions of the device  10  of FIG. 13 for programming, erasing and reading operations respectively. 
     For the operation modes, channel hot electron programming is shown in FIG.  14 . During programming there are hot electron paths  40  on vertical channel surfaces. During programming, the voltages are as follows: 
     V D =V CC , V CG =V high , and V S =V B =0. 
     The Fowler-Nordheim (FN) tunneling erase operation is illustrated in FIG. 15 with electron tunneling paths  42  on source/drain S/D sides of the device. During erasing the voltages are as follows: 
     V D =V S =V hiqh , V CG =0, and V B  is Floating 
     Reading is shown in FIG. 16 where electron paths  44  extend from source to drain sides. During reading the voltages are as follows: 
     V D =V CC , V CG =V CC , V S =V S =0 
     The operation conditions of the memory cell illustrated by FIGS. 14-16 are listed in Table I. 
     
       
         
               
             
               
               
               
               
             
               
               
               
               
               
               
             
           
               
                 TABLE I 
               
             
             
               
                   
               
               
                 Memory Cell Operation Condition 
               
             
          
           
               
                   
                 Prog. 
                 Erase 
                 Read 
               
               
                   
                   
               
             
          
           
               
                   
                 Bit Line 
                 Selected 
                 V cc   
                 V high   
                 V cc   
               
               
                   
                 (Drain) 
                 Unselected 
                 0 
                 0 
                 0 
               
               
                   
                 Word Line 
                 Selected 
                 V high   
                 0 
                 V cc   
               
               
                   
                 (Gate) 
                 Unselected 
                 0 
                 0 
                 0 
               
               
                   
                 Source 
                 Selected 
                 0 
                 V high   
                 0 
               
               
                   
                   
                 Unselected 
                 0 
                 0 
                 0 
               
               
                   
                 Buck 
                 Selected 
                 0 
                 0 
                 Floating 
               
               
                   
                   
                 Unselected 
                 0 
                 0 
                 0 
               
               
                   
                   
               
             
          
         
       
     
     CONCLUSIONS 
     The problems solved by a vertical EPROM device in accordance with this invention are as follows: 
     1. Packing density is increased since the unit cell requires less silicon surface area but with more channel area. 
     2. Because the floating gate is under the wafer surface, the profile of the stacking gate above the silicon surface is the same as that of the peripheral devices. Therefore, the stacking gate etching can be done simultaneously with the control gate etching for peripheral devices. 
     3. The processing of the proposed memory cell is more comparable with that of the peripheral devices. 
     4. The tunnel oxide which is used for erasing, is located between the source/drain and the floating gate and does not overlap with the channel region. Therefore, the band-to-band hot hole phenomenon can be completely prevented during the erasing procedure, since the conventional P-N junction formed from the source/drain regions with the bulk region of the device is not involved in this cell structure. 
     5. Since the part of the tunnel oxide used for erasing is not located at the channel, the problematical window closing behavior, which has been caused during erasing, can be avoided. 
     6. Because the area of the tunnel oxide between the source/drain regions and the floating gate electrode is much larger than that of the traditional structure, the result is that the erasing speed is much faster. 
     7. Drain saturation current (IDsat) of the memory cell is enhanced since the channel area can be increased without requiring more wafer surface area. 
     While this invention has been described in terms of the above specific embodiment(s), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims, i.e. that changes can be made in form and detail, without departing from the spirit and scope of the invention. Accordingly all such changes come within the purview of the present invention and the invention encompasses the subject matter of the claims which follow.