Abstract:
A data compression apparatus and method of displaying graphics in a computer system employs a full frame buffer and compressed frame buffer wherein pixel data is sent to a display device and concurrently compressed and captured in parallel so that subsequent unchanged frames are regenerated directly from the compressed frame buffer.

Description:
Continuation of prior application Ser. No: 08,863,123 filed on May 27, 1998. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates generally to systems and methods of video display, and more particularly to systems and methods of pixel data compression in a computer system. 
     2. Description of Related Art 
     Without limiting the scope of the invention, this background information is provided in the context of a specific problem to which the invention has application. 
     Over the last decade, the quality of computer graphic displays has steadily increased with improvements in pixel resolution, color depth, and screen refresh rate of the display device—typically a cathode ray tube (CRT) or a liquid crystal display (LCD). It is commonplace for graphics in computers to have a frame resolution of up to 1280×1024 pixels and up to 16.7 million simultaneous colors. Display of such high resolution and high color content images, particularly at high refresh rates, places great demands on the memory subsystem which stores the frame buffer. Typically, tradeoffs are made to obtain suitable display rates and resolutions which the memory subsystem can supply while still having enough bandwidth to perform memory accesses required by the graphics engine or host central processing unit (CPU). If the display data rate is too high, the system is paralyzed by constant pixel data reads from memory—leaving no time for other tasks to access the memory. 
     To illustrate this point, a computer system employing an inexpensive graphics subsystem, for example a memory array with 32-bit wide DRAMs having a “fast-page” access of 45 nanoseconds, would have a theoretical peak available bandwidth of 89 megabytes/second. Realistically however, this value must be de-rated to account for, inter alia, page misses—imposing an available bandwidth of about 77 megabytes/second. With a frame resolution of 1024×768 pixels, eight color intensity bits per pixel, and a seventy-five Hz refresh rate, the required display bandwidth is 59 megabytes/second (1024×768×1 Byte×75)−seventy-seven percent of the total available memory bandwidth. If the color intensity resolution were increased to sixteen bits per pixel, the display bandwidth requirement would double to 118 megabytes/second−29 megabytes/second more than the peak available bandwidth. 
     One approach in confronting these limitations is to simply increase the bandwidth of the memory subsystem by using special purpose dual-ported memories or by increasing the width of the DRAM interface. Accordingly, several types of specialty graphics memory integrated circuits have spawned such as dual-ported VRAM or Windows™ RAM. These types of memories however, are not produced in as large of volumes as the ubiquitous DRAM used for main memory, thus command a price premium. 
     By way of further background, power consumption is yet another major concern in the design of graphic display subsystems, especially in portable computers due to their limited battery life. It is known that power consumption increases in proportion with consumed memory bandwidth and thus high resolution and high color content display modes traditionally have not been well suited for portable computer applications. 
     From the foregoing, it can be seen that there is a need for a system and method for high performance graphics display without increased power consumption. 
     SUMMARY OF THE INVENTION 
     To overcome the limitations of the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, a low power, reduced bandwidth, graphics display system and method is disclosed for generating pixel data utilizing full and compressed frame buffers. As pixel data is sent from the full frame buffer to a display device, it is concurrently compressed and captured in the compressed frame buffer so that subsequent unchanged frames are regenerated directly from the compressed frame buffer. Coherency is maintained between the full and compressed frame buffers with a dirty/valid tag RAM so that as the pixel data stream is transferred out and compressed, the compressed data is validated for subsequent frame updates from the compressed frame buffer. 
     Once the pixel data stream has been compressed, stored in the compressed frame buffer, and validated, on subsequent frames, the pixel data is retrieved directly from the compressed frame buffer and decompressed as it is sent to the display device. The pixel data is continuously retrieved as required to refresh the display from the compressed frame buffer until the compressed data elements are invalidated by future frame buffer writes. As new pixel data is rendered to the full frame buffer by a graphics engine or host CPU, the dirty tags for the corresponding compressed data elements are set so that during the next qualified frame scan, the pixel data is retrieved from the full frame buffer rather than the compressed frame buffer. 
     A feature of the present invention is separate dirty and valid bits to validate each compressed data element (preferably although not exclusively a raster line) in a frame and a programmable frame rate control mechanism to quality the dirty bits. The dirty bits are set in response to pixel data being rendered to the full frame buffer. The valid bits are set in response to the data compressor updating a compressed data element in the compressed frame buffer. The programmable frame rate control mechanism provides a programmable sample rate to qualify the dirty bits so that updates to the full frame buffer are ignored for a predetermined period of time and more frame displays occur from the compressed frame buffer, thus lowering memory bandwidth and power consumption. 
     Another feature of the present invention is the ability to employ unified memory in a practical graphics system—providing easy upgradeability for either graphics or main memory with the addition of continuous DRAM. 
     These and various other objects, features, and advantages of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and forming a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to the accompanying descriptive matter, in which there is illustrated and described specific examples of systems and methods practiced in accordance with the present invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a block diagram depicting a video refresh compression system practiced in accordance with the principles of the present invention; and, 
     FIG. 2 is a block diagram depicting the command and color data paths for the exemplary system in FIG.  1 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. The detailed description is organized as follows: 
     1. Exemplary Refresh Compression System 
     2. Compression Conmmand And Color Data Paths 
     3. Decompression Command and Color Data Paths 
     4. Conclusion 
     This organizational outline, and the corresponding headings, are used in this Detailed Description for convenience of reference only. Detailed descriptions of conventional or known aspects of microprocessor and graphic display systems are omitted so as not to obscure the description of the invention with unnecessary detail In particular, certain terminology relating to computer video display standards and operational modes are known to practitioners in the field of graphics display design. 
     1. Exemplary Refresh Compression System 
     Referring now to FIG. 1, a block diagram depicts a video refresh compression system practiced in accordance with the principles of the present invention. A graphics engine  10  or CPU (not shown) updates a data element (preferably although not exclusively a raster line) in a full frame buffer  12  by writing (rendering) pixel data thereto and setting a corresponding dirty bit in a dirty/valid RAM  14  to indicate that the raster line has been updated. In the preferred embodiment, the full frame buffer  12  is variable in size but is preferably large enough to accommodate a frame resolution of 1280×1024 pixels or greater. With the aid of the present disclosure, those skilled in the art will recognize other frame resolutions, frame buffer sizes, number of frames stored in the frame buffer, and data element sizes without departing from the scope of the present invention. 
     The dirty/valid RAM  14  holds a dirty bit and a valid bit for each data element (raster line) stored in the full frame buffer  12 —is which in the preferred embodiment corresponds to 2048 (1024×2) bits. If the dirty bit in the dirty/valid RAM  14  indicates that a raster line has been updated, the full frame buffer  12 , responsive to display control circuitry  22 , updates the display device (except as described in more detail hereinbelow), by transferring a stream of pixel data corresponding to each raster line to an input on a two input multiplexer  16 . The output of the multiplexer  16  is fed to the pixel output formatting stage (not shown) where a palette lookup is performed, if necessary, any overlays are inserted, and a flat panel (LCD) interface or a video palette digital-to-analog converter (DAC) (not shown) is driven which in turn drives a CRT (also not shown). 
     The stream of pixel data from the full frame buffer  12  is also coupled to a data compressor  18  which in the preferred embodiment, concurrently compresses and stores the pixel data in a compressed frame buffer  20  as it is received by the multiplexer  16 . After a complete data element (raster line) is compressed and stored in the compressed frame buffer  20 , the data compressor  18  validates the corresponding valid tag in the dirty/valid RAM  14 . On subsequent frame refreshes by display control circuitry  22 , compressed data elements whose valid bits are set and whose dirty bits are not set or not qualified, are supplied through a data decompressor  24  to the multiplexer  16 . The data decompressor  24  decompresses the data and supplies it through the multiplexer  16  for output to the display device. The full frame buffer  12 , the compressed frame buffer  20 , and the dirty/valid RAM  14 , may be physically located in the same DRAM array as main memory. Preferably however, the dirty/valid RAM  14  is located in a scratch pad RAM separate from main memory since fast rendering by the graphics engine  10  or CPU can quickly dirty large blocks of data. 
     The dirty bits in the dirty/valid RAM  14  need not be sampled at the frame refresh rate. Rather, a slower rate set by display control circuitry  22  can “qualify” changes in dirty bit status so that the decompressor  24  ignores updates made in the full frame buffer  12  for N frames. Since fluid motion is generally regarded as thirty frames per second, there is no need to update the displayed frame any faster. Moreover, in the case where the display device has an even slower response time, such as a passive flat panel (LCD) display, the frame update rate may be even lower. 
     For example, there is no need to update the display any faster than five frames per second for a display panel having a 200 millisecond response time. If the display control circuitry  22  supplies a refresh rate of 60 Hz, the qualifier frequency can be twelve times less so that the dirty bits are qualified once every twelve frames (5 Hz) to assure an image update rate equal to five frames per second. Therefore, assuming the entire image is compressible, with a twelve-to-one qualify ratio, the display is updated from the compressed frame buffer  20  approximately ninety-two percent of the time, regardless of how fast new pixel data are rendered by the graphics engine  10  to the full frame buffer  12 . 
     2. Compression Color and Control Data Paths 
     Reference is now made to FIG. 2 which depicts the preferred color and command data paths for a system practiced in accordance with the principles of the present invention. With the aid of the present disclosure, those skilled in the art will recognize other forms and number of stages for the color and command data paths without departing from the scope of the present invention. A display FIFO  30  is coupled via a memory controller  31 , to a DRAM array  11  which includes the full frame buffer  12 , the compressed frame buffer  20 , and optionally main memory  21 . Decode control circuitry  32  has a first input coupled to the dirty/valid RAM  14  and a first output for controlling the display FIFO  30  to load pixel data from the full frame buffer  12  when dirty bits are qualified and set or valid bits are not set Alternatively, the display FIFO  30  loads pixel data from the compressed frame buffer  20  when the valid bit is set and the dirty bit is not qualified or not set. 
     Decode control circuitry  32  has a second input coupled to the output of the display FIFO  30  for detecting and decoding a control word stored in the compressed frame buffer  20  (described in more detail hereinbelow) and a second output coupled to color unpack circuitry  38 , command unpack circuitry  40 , and multiplexer  16 . The multiplexer  16  routes pixel data from the color unpack circuitry  38  if the pixel data originates from the full frame buffer  12  and from the color cache  42  (or the color unpack circuitry  38  in the case of a load new color instruction LNC), if the pixel data originates from the compressed frame buffer  20 . The output of multiplexer  16  is coupled to the pixel output formatting stage (not shown) and to an input on color pack circuitry  58 . Color data from the multiplexer  16  is concatenated “packed” to 32-bit boundaries by color pack circuitry  58 . 
     Command pack circuitry  60  receives and concatenates variable length “hit opcodes” to 32-bit boundaries from hit opcode pipeline  50 , RLE detector  54 , and RL8 detector  56  (all described in more detail hereinbelow). The outputs of color pack circuitry  58  and command pack circuitry  60  are coupled to inputs on multiplexer  62 . Line buffer control circuitry  34  controls multiplexer  62  to fill a compressed line buffer  36  with compressed color and command data at its opposite ends respectively, progressing towards the middle of the line buffer  36 . If the line buffer  36  does not overflow by the time the end of the raster line is reached, line buffer control circuitry  34  writes the contents of the compressed line buffer  36  to the compressed frame buffer  20 , interleaving the color and command data on 64bit boundaries. A control word for each data element (raster line) is calculated by line buffer control circuitry  34  and is appended to the beginning of each compressed line buffer  36  entry to define the amount and the length of the command and color data After the control word, each entry in the compressed frame buffer  20  contains command and color data alternating on 64-bit boundaries until one of the data streams terminates. 
     Although the temporal relationship between command and color data is lost due to the uneven pipelining between the command and color data paths, the interleaving of color and command data in the compressed frame buffer  20  presents data in the approximate required order when the raster line is loaded from the compressed frame buffer  20  into the display FIFO  30  on future refreshes. When the raster line has been successfully written back from the compressed line buffer  36  to the compressed frame buffer  20 , the line buffer control circuitry  34  validates the corresponding valid bit in the dirty/valid RAM  14  for that raster line. 
     A color cache  42 , which preferably includes a fully associative, three entry primary cache, a single entry, secondary “victim” cache, and a plurality of comparators, receives color data from the output of color unpack circuitry  38 . It should be understood however, that with the aid of the present disclosure, those skilled in the art will recognize other cache configuration associations, and sizes without departing from the scope of the present invention. Cache control circuitry  44 , which is coupled to the color cache  42 , tracks and replaces least- recently-used (LRU) entries in the primary cache when a new color is sent from the color unpack circuitry  38 . If the new color hits in the secondary cache, the secondary cache entry is swapped with the LRU entry in the primary cache. When a new color is updated in the primary cache, the color previously in that position is moved to the secondary cache. 
     The color cache  42  signals a hit to the cache control circuitry  44  whenever color data from the color unpack circuitry  38  matches color data in the color cache  42 . In response, the cache control circuitry  44  encodes and sends a “hit opcode” identifying the cache location of the hit to multiplexer  48 . The output of multiplexer  48  is sent through the hit opcode pipeline  50 . 
     In addition to the opeodes used for hits in the color cache  42 , run-length encoding (RLE) opcodes are used to compress a series of constant colors greater than four. Separate opcode commands are used for short runs (five to nineteen) and long runs (twenty to two-hundred-fifty-five) to maximize compression. Constant color sequences less than five are encoded using a repeat cache opcode command. To efficiently handle raster lines containing a dithered background, a Repeat Last “N” (for example, N=eight) (RL8) opcode is used. As a raster line is sent to the pixel output formatting stage, if the next eight pixels match the previous eight pixels in the same order and provided that the group is not all the same color, the group of eight pixels is encoded with the RLS opcode. 
     To avoid encoding repetitive opcodes, a “hit opcode pipeline”  50  is provided having a plurality of stages for pipelning hit opcodes from the multiplexer  48  so that RLE detector  54  and RLS detector  56  can determine RLE and RL8 strings respectively. Since a stream of pixel data can be encoded as a series of hit opcodes in the color cache  42 , as an RLE opcode, or possibly as an RL8 opcode, the hit opcode pipeline  50  provides a means for detectors  54  and  56  to compare, count, and most efficiently encode multiple adjacent hit opcodes. The number of stages in the hit opcode pipelines  50  is preferably eight However, those skilled in the art will recognize that the pipeline  50  can be contracted or expanded to accommodate other opcode strings. The hit opcode pipeline  50 , RLE detector  54 , and RL8 detector  56 , drive the command pack circuitry  60  which packs the respective codes for the respective cache location or opcode strings, as described hereinabove. 
     If the current pixel color from the color unpack circuitry  38  does not match any of the colors in the color cache  42 , the cache control circuitry  44  encodes a Load New Color (LNC) command opcode into the pixel data stream. The LNC opcode requires four bits in addition to the pixel data bits to describe the color value itself and thus results in data expansion rather than compression. The data expansion is not significant since the majority of the screen is repetitive and rarely requires a new color to be loaded. 
     The encoded opcodes for the exemplary embodiment are summarized below in Table 1. 
     
       
         
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                   
                   
                   
                   
                   
                 COMPRESSION 
                 COMPRESSION 
               
               
                   
                   
                   
                 LENGTH 
                 ENCODED 
                 RATIO 
                 RATIO 
               
               
                 OPCODE 
                 NAME 
                 DESCRIPTION 
                 (Bits) 
                 (Bits/Pixel) 
                 (8 Bits/Pixel) 
                 (16 Bits/Pixel) 
               
               
                   
               
             
             
               
                 00 
                 RC0 
                 Repeat Cache 0 
                 2 
                 2 
                 4:1 
                 8:1 
               
               
                 01 
                 RC1 
                 Repeat Cache 1 
                 2 
                 2 
                 4:1 
                 8:1 
               
               
                 10 
                 RC2 
                 Repeat Cache 2 
                 2 
                 2 
                 4:1 
                 8:1 
               
               
                 1100 
                 RC3 
                 Repeat Cache 3 
                 4 
                 4 
                 2:1 
                 4:1 
               
               
                 1101 
                 RL8 
                 Repeat Last 8 
                 4 
                 0.5 
                 16:1  
                 32:1  
               
               
                 1110 
                 RLE4 
                 RLE - 4-bit count 
                 8 
                 0.42-1.6  
                  5:1 to 19:1 
                 10:1 to 38:1 
               
               
                 1110 1111 
                 RLE8 
                 RLE - 8-bit count 
                 16  
                 0.063-0.8  
                  10:1 to 128:1 
                  20:1 to 256:1 
               
               
                 1111 
                 LNC 
                 Load New Color 
                 12/20 
                 12/20 
                 0.67:1   
                 0.8:1   
               
               
                   
               
             
          
         
       
     
     3. Decompression Color and Command Data Path s 
     With reference still to FIG. 2, on refresh, if the valid bit is set and the dirty bit is not qualified or not set in the dirty/valid RAM  14  for the selected raster line, decode control circuitry  32  detects and decodes the control word stored in the compressed frame buffer  20 . The control word identifies the length of the command and data streams and accordingly instructs the decode control circuitry  32  to control color unpack circuitry  38  and command unpack circuitry  40  to unpack the command and color data from the display FIFO  30 . The color data from the color unpack circuitry  38  is cached in the color cache  42  while the command data is decoded by cache control circuitry  44 . Responsive to the command data, cache control circuitry  44  selects one of three inputs to multiplexer  48 . A first input is coupled to the cache control circuitry  44  which outputs a single opcode identifying a single cache location or a LNC opcode to load a new color. The second and third inputs of multiplexer  48  are coupled to the hit opcode pipeline  50  which feeds back repetitive run-length encoded (RLE) and repeat last eight (RL8) opcodes. The first stage of hit opcode pipeline  50  (which is the output of multiplexer  48  delayed by one clock cycle) is coupled back to cache control circuitry  44 . Responsive to the opcode generated by the first stage in hit opcode pipeline  50 , cache control circuitry  44  instructs the color cache  42  to send color data or to load new color data from the color unpack circuitry  38  into the multiplexer  16 . 
     4. Conclusion 
     Although the Detailed Description of the invention has been directed to certain exemplary embodiments, various modifications of these embodiments, as well as alternative embodiments, will be suggested to those skilled in the art For example, specific register structures, mappings, bit assignments, cache associations and sizes, and other implementation details are set forth solely for purposes of providing a detailed description of the invention. However, the invention has general applicability to any computer system architecture. Various modifications based on trade-offs between hardware and software logic will be apparent to those skilled in the art The invention encompasses any modifications or alternative embodiments that fall within the scope of the claims.