Abstract:
A method for dividing a high frequency clock signal for analysis of all clock edges has been developed. The method includes receiving a high frequency clock signal and dividing it up into multiple phases that represent respective edges of the clock signal. The initial phases are generated by the divider with each subsequent phase lagging its preceding phase by one clock cycle. Additional subsequent phases are generated by inverting corresponding initial phases.

Description:
BACKGROUND OF INVENTION 
     1. Field of the Invention 
     The invention relates generally to a micro-electronic clock system. More specifically, the invention relates to a clock divider that allows for analysis of all of the clock edges. 
     2. Background Art 
     A clock signal is critical to the operation of a microprocessor based computer system. The clock signal initiates and synchronizes the operation of almost all of the components of such a computer system. Consequently, the detection of any errors or problems with the clock signal is vitally important. 
     A phased locked loop (PLL) is an important part of a clock signal distribution system. A PLL is a component that uses feedback to maintain an output signal in a specific phase or frequency relationship with an input signal. In the case of a computer system, a PLL is used to synchronize the microprocessor (“chip”) clock with the external (“system”) clock. Such synchronization is necessary because a chip clock typically operates at a much greater frequency than the system clock. Consequently, the PLL operates at the same higher frequency because it serves the chip clock. 
     FIG. 1 shows a prior art overview of a clock distribution system. The computer system  10  broadly includes an input/output (“IO”) ring  12  that is external to the microprocessor chip or “core”  14  of the system. The system clock signal  16  is fed through the IO ring  12  to the PLL  15  inside the core  14 . The PLL  15 , after synchronizing the system clock signal with the chip clock signal, feeds it 
     to a global clocking grid  18  for the chip. The global clocking grid  18  feeds the signal data/scan paths and various components such as system latches  22 , local clocking grids  20 , and a feed back loop  26  that returns to the PLL  15 . The local clocking grids  20  feed the base components of the core  14  such as flip-flops  24  which as basic data storage devices. 
     The PLL clock signal  28  is also sampled after the PLL  15  in order to analyze the signal performance off chip. Specifically, the PLL signal  28  is checked for the effects of system noise (called “jitter”) and timing errors (called “skew”). However, difficulties arise in trying to observe the PLL signal  28  because it is often operating at frequencies up to 3 GHz. The off-chip drivers that drive the signal  28  generally cannot support this speed because they operate at lower frequencies. While a few clock edges might be observed, the higher frequency energy that causes the problems that are trying to be detected will be filtered out. A solution is needed that allows for observation and analysis of all the clock edges. 
     SUMMARY OF INVENTION 
     In some aspects, the invention relates to a method for dividing a clock signal into multiple phases, comprising: inputting the clock signal to a clock divider segment group, wherein the clock divider segment group comprises at least one clock divider segment; generating a first half of the multiple phases with the clock divider segment group; and generating a second half of the multiple phases with an inverse output from the clock divider segment group. 
     In other aspects, the invention relates to a method for dividing a clock signal, comprising: inputting the clock signal to a divider; generating a first phase of the clock signal with the divider; generating a second phase of the clock signal with the divider, wherein the second phase lags behind the first phase by one clock cycle; generating a third phase of the clock signal by inverting the first phase; and generating a fourth phase of the clock signal by inverting the second phase. 
     In other aspects, the invention relates to an apparatus for dividing a clock signal, comprising: a means for inputting the clock signal to a divider; means for generating multiple initial phases of the clock signal with the divider; and means for generating an multiple additional phases of the clock signal by inverting corresponding initial phases of the clock signal. 
     In other aspects, the invention relates to an apparatus for dividing a clock signal, comprising: a divider input that receives the clock signal; a first phase generator that generates a first phase of the clock signal; a second phase generator that generates a second phase of the clock signal, wherein the second phase lags behind the first phase by one clock cycle; a third phase generator that generates a third phase of the clock signal by inverting the first phase; and a fourth phase generator that generates a fourth phase of the clock signal by inverting the second phase. 
     Other aspects and advantages of the invention will be apparent from the following description and the appended claims. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 shows a prior art overview of a clock distribution system. 
     FIG. 2 shows an overview of a clock distribution system in accordance with one embodiment of the present invention. 
     FIG. 3 shows a schematic of a clock divider circuit in accordance with one embodiment of the present invention. 
     FIG. 4 shows a timing diagram of the clock divider circuit show in FIG. 3 in accordance with one embodiment of the present invention. 
     FIG. 5 shows a schematic of a clock divider circuit in accordance with an alternative embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     Exemplary embodiments of the invention will be described with reference to the accompanying drawings. Like items in the drawings are shown with the same reference numbers. 
     FIG. 2 shows an overview of a clock distribution system in accordance with one embodiment of the present invention. The clock distribution system  10  of FIG. 2 is configured in the same arrangement as the prior art system shown in FIG. 1 with the exception of the addition of a clock signal divider  30  for the PLL clock signal  28 . The clock divider, as shown in this embodiment, divides the PLL signal  28  into four separate phases that are observed off-chip. 
     FIG. 3 shows a schematic of a clock divider circuit in accordance with one embodiment of the present invention. The PLL clock signal  28  (“CLK”) is input into the clock signal divider  30 . CLK  28  is used to initiate the operation of the first and third through seventh flip-flops  32   a ,  32   c-   32   g . The second flip-flop  32   b  is initiated by the output of the first flip-flop  32   a . Both the first and second flip-flops  32   a  and  32   b  have inputs that are fed back from their respective outputs. Both outputs are fed through a single inverter  34   a  and  34   b  before being input into their respective flip-flops  32   a  and  32   b.    
     The output of the second flip-flop  32   b  is the first phase of the division of the clock signal  28 . It is referred to as “N1”. The N 1  output is also input into the third flip-flop  32   c . The output of the third flip-flop  32   c  is effectively delayed one cycle behind N 1  by the flip-flop  32   c . This output is the second phase of the division of the clock signal  28 . It is referred to as “N2”. The N 1  output is also fed through an inverter  34   c . The output of this inverter  34   c  is the third phase of the division of the clock signal  28 . It is referred to as “N3”. The N 2  output is also fed through an inverter  34   d . The output of this inverter  34   d  is the fourth phase of the division of the clock signal. It is referred to as “N4”. The four phases of the signal N 1 , N 2 , N 3 , and N 4  are each input into a separate flip-flop  32   d-   32   g  for each phase. The outputs of this bank of four flip-flops  32   d-   32   g  are collectively output from the divider  30  as respective phase signals CKPH 1 , CKPH 2 , CKPH 3 , and CKPH 4 . These phase signals CKPH 1 , CKPH 2 , CKPH 3 , and CKPH 4  are capable of being analyzed for errors without the problems associated with the high frequency of the original clock signal  28 . 
     In accordance with FIG. 3, flip-flops  32   a  and  32   b  with feedback inverters  34   a  and  34   b  and flip-flop  32   c  together form an example of a means for generating multiple initial phases. Inverters  34   c  and  34   d  together form an example of a means for generating multiple additional phases. In another aspect, flip-flops  32   a  and  32   b  with feedback inverters  34   a  and  34   b  form an example of a first phase generator. Flip-flops  32   a  and  32   b  with feedback inverters  34   a  and  34   b  and flip-flop  32   c  form an example of a second phase generator. Inverter  34   c  forms an example of a third phase generator. Inverter  34   d  forms an example of a fourth phase generator. Flip-flops  32   d-   32   g  form an example of an alignment generator that aligns the phases based on a timing of the clock signal. 
     FIG. 4 shows a timing diagram of the clock divider circuit show in FIG. 3 in accordance with one embodiment of the present invention. The CLK diagram is shown with leading edges  36   a-   36   d  of the first four clock cycles that are to be divided out. N 1  shows the timing diagram of the first clock phase CKPH 1 . The leading edge of N 1   38   a  corresponds to the first leading edge  36   a  of the first clock cycle of CLK. N 2  shows the timing diagram of the second clock phase CKPH 2 . The leading edge of N 2   38   b  corresponds to the leading edge  36   b  of the second clock cycle of CLK. N 3  shows the timing diagram of the third clock phase CKPH 3 . The leading edge of N 3   38   c  corresponds to the leading edge  36   c  of the third clock cycle of CLK. Finally, N 4  shows the timing diagram of the fourth clock phase CKPH 4 . The leading edge of N 4   38   d  corresponds to the leading edge  36   d  of the fourth clock cycle of CLK. 
     Each of the HIGH segments of timing diagrams of the phases N 1 , N 2 , N 3  and N 4  lasts for two cycles of the CLK diagram. This demonstrates that the timing of the phases N 1 , N 2 , N 3  and N 4  has been slowed to one quarter of the frequency of the CLK, in effect dividing the CLK by four. For example, a CLK signal running at a speed of 3 GHz, will be divided into four separate phases running at a speed of 750 MHz each. This allows a sufficient cycle duration of the phases N 1 , N 2 , N 3  and N 4  to allow for off-chip analysis of that cycle for jitter and skew. It is significant to note that the N 3  phase is simply the inverse of the N 1  phase and the N 4  phase is simply the inverse of the N 2  phase. This is due to the respective inverters  34   c  and  34   d  shown in FIG.  3 . The inversion of these signals results in a slight timing delay between the N 2  and N 3  phases. 
     FIG. 5 shows a schematic of a clock divider circuit in accordance with an alternative embodiment of the present invention. In this embodiment, the PLL clock signal  28  (CLK) is input into the clock divider circuit  40 . The CLK signal serves to initiate the operation of a first flip-flop  42   a  and a second flip-flop  42   b . The outputs of each of the flip-flops  42   a  and  42   b  is input into a respective inverter  44   a  and  44   b . The output of the inverters  44   a  and  44   b  is an input into a respective XNOR gate  46   a  and  46   b . The other input to the first XNOR gate  46   a  is the system power supply (V DD ). The other input to the second XNOR gate  46   b  is the output of the first inverter  44   a . The outputs of the XNOR gates  46   a  and  46   b  are fed back to the inputs of their respective flip-flops  42   a  and  42   b.    
     The output of the first XNOR gate  46   a  is the first phase of the division of the clock signal  28 . It is referred to as “N1”. The N 1  phase is input into a third inverter  44   c . The output of this inverter  44   c  is the third phase of the division of the clock signal  28 . It is referred to as “N3”. The output of the second XNOR gate  46   b  is the second phase of the division of the clock signal  28 . It is referred to as “N2”. The N 2  phase is input into a fourth inverter  44   d . The output of this inverter  44   d  is the fourth phase of the division of the clock signal  28 . It is referred to as “N4”. The four phases N 1 , N 2 , N 3 , and N 4  generated by the circuit  40  in FIG. 5 are the same as the four phases N 1 , N 2 , N 3 , and N 4  generated by the circuit  30  in FIG.  3 . As in the previous embodiment shown in FIG. 3, the four phases of the signal N 1 , N 3 , N 2 , and N 4  are each input into a separate flip-flop  44   c-   44   f  for each phase. The outputs of this bank of four flip-flops  44   c-   44   f  are collectively output from the divider  40  as respective phase signals CKPH 1 , CKPH 3 , CKPH 2 , and CKPH 4 . These phase signals CKPH 1 , CKPH 3 , CKPH 2 , and CKPH 4  are capable of being analyzed for errors without the problems associated with the high frequency of the original clock signal  28 . 
     Since the outputs of the embodiments shown in FIGS. 3 and 5 are the same, it follows that FIG. 4 shows the timing diagrams of the phase outputs for the embodiment of FIG. 5 as well. In FIG. 4, the CLK diagram is shown with leading edges  36   a-   36   d  of the first four clock cycles that are to be divided out. N 1  shows the timing diagram of the first clock phase CKPH 1 . The leading edge of N 1   38   a  corresponds to the first leading edge  36   a  of the first clock cycle of CLK. N 2  shows the timing diagram of the second clock phase CKPH 2 . The leading edge of N 2   38   b  corresponds to the leading edge  36   b  of the second clock cycle of CLK. N 3  shows the timing diagram of the third clock phase CKPH 3 . The leading edge of N 3   38   c  corresponds to the leading edge  36   c  of the third clock cycle of CLK. Finally, N 4  shows the timing diagram of the fourth clock phase CKPH 4 . The leading edge of N 4   38   d  corresponds to the leading edge  36   d  of the fourth clock cycle of CLK. 
     Each of the HIGH segments of timing diagrams of the phases N 1 , N 2 , N 3  and N 4  lasts for two cycles of the CLK diagram. This demonstrates that the timing of the phases N 1 , N 2 , N 3  and N 4  has been slowed to one quarter of the frequency of the CLK, in effect dividing the CLK by four. For example, a CLK signal running at a speed of 3 GHz, will be divided into four separate phases running at a speed of 750 MHz each. This allows a sufficient cycle duration of the phases N 1 , N 2 , N 3  and N 4  to allow for off-chip analysis of that cycle for jitter and skew. It is significant to note that the N 3  phase is simply the inverse of the Ni phase and the N 4  phase is simply the inverse of the N 2  phase. This is due to the respective inverters  44   c  and  44   d  shown in FIG.  5 . The inversion of these signals results in a slight timing delay between the N 2  and N 3  phases. 
     In alternative embodiments, the degree of division of the signal is scalable. In the previously described embodiments shown in FIGS. 3 and 5, the signal was divided into four phases. In alternative embodiments, the number of division phases could be increased or decreased by simply adding or deleting any number of circuit dividing segments as needed. 
     For example in FIG. 3, the circuit could be converted to divide the clock signal by eight by simply adding two additional flip-flops and two additional inverters. Specifically, the circuitry arrangement to generate N 1  and N 2  would remain the same as shown in FIG.  3 . The input for the first additional flip-flop would be taken from N 2  and its output would be N 3 . The input for the second additional flip-flop would be taken from N 3  and its output would be N 4 . Thus, the first four phases N 1 , N 2 , N 3 , and N 4  are generated by outputs from respective flip-flops. The last four phases N 5 , N 6 , N 7 , and N 8  are generated by inverting the corresponding signal from the first four phases. Specifically, N 1  is inverted to generate N 5 ; N 2  is inverted to generate N 6 ; N 3  is inverted to generate N 7 ; and N 4  is inverted to generated N 8 . The same technique could be used with the circuit dividing segments of the embodiment shown in FIG.  5 . 
     This principle uses clock divider segments to generate the first half of the total number of output phases. The outputs of the clock divider segments are then inverted to generate the last half of the total number of output phases. In the embodiment shown in FIG. 3, one clock divider segment includes one flip-flop  32   c  whose input is the preceding output phase N 1  of the previous flip-flop  32   b . The output of this clock divider segment N 2  is inverted  34   d  to generate N 4 . In the embodiment shown in FIG. 5, the clock divider segment includes a flip-flop  42   b , an inverter  44   b , and an XNOR gate  46   b  arranged as shown. The output of this clock divider segment N 2  is inverted  44   d  to generate N 4 . 
     While all of the previously described embodiments have monitored the rising edge of the clock cycle for jitter and skew, it is possible to monitor the falling edge of a clock cycle as well. Implementation of the falling edge clock divider simply involves inverting the CLK signal input  28  as shown in FIGS. 3 and 5. The CLK signal input  28  is inverted prior to being input into any flip-flops of the respective circuits  30  and  40 . 
     While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.