Abstract:
An adaptive equalizer includes: an equalizer configured to equalize a digital RF signal based on a plurality of tap coefficients; and a tap coefficient controller configured to correct the plurality of tap coefficients in a time division. The tap coefficient controller includes a tap coefficient register configured to hold the plurality of tap coefficients; and a product-sum calculating circuit configured to correct at least one selected from the plurality of tap coefficients in response to an enable signal, by a predetermined product-sum calculation, and update the selected tap coefficient by the corrected tap coefficient.

Description:
INCORPORATION BY REFERENCE 
       [0001]    This patent application claims a priority on convention based on Japanese Patent Application No. 2009-157562 filed on Jul. 2, 2009. The disclosure thereof is incorporated herein by reference. 
       TECHNICAL FIELD 
       [0002]    The present invention relates to an adaptive equalizer, an information reproducing device, and an adaptive equalization method. 
       BACKGROUND ART 
       [0003]    Through recent development of a multimedia technique, a large amount of data including video data should be processed. Further, a capacity of a storage device for recording such data should be increased, and in particular, in the field of storage for high quality video data, BD (Blu-ray Disc) having a storage capacity far exceeding that of DVD (Digital Versatile Disc) is beginning to be put into the market. In order to increase a storage capacity of an optical disc or HDD device, a record density should be increased, and along with this, a reduction in an error rate and ensuring of reliability have become important issues. 
         [0004]    On the other hand, if the record density of the optical disc is increased, a waveform obtained from the disc at a specific time interferes with that obtained from the disc at another time (this is referred to as intersymbol interference), and therefore reproduction of a short record mark of a certain length or less becomes difficult. On the other hand, if the record mark is long, an output frequency of phase data for extracting a synchronization clock is reduced, which causes step-out of synchronization. Accordingly, a length of the record mark should be limited to a predetermined length or less. For the above reasons, record data on the optical disc is encoded and recorded. In particular, an RLL code (Run Length Limited Code) in which a code inversion length is limited is often used, and a 17PP modulation code, EFM (Eight to Fourteen Modulation), 8/16 modulation core, and the like are used. 
         [0005]    As a method for eliminating the intersymbol interference, a technique called waveform equalization is known. This is a method in which an error rate is reduced with an inverse filter eliminating the intersymbol interference. In the waveform equalization, a high frequency bandwidth component of a reproduction signal is enhanced to suppress the intersymbol interference. However, a high frequency bandwidth component of noise is also enhanced, and therefore an SNR (Signal to Noise Ratio) of the reproduction signal may be degraded. In particular, in a case of increasing the record density, the degradation in SNR due to the waveform equalization becomes a main cause of error in detection data. 
         [0006]    On the other hand, PR (Partial Response) equalization is known that is one of waveform equalization methods, and intentionally gives rise to known intersymbol interference. According to the PR equalization, the degradation in SNR can be suppressed without enhancing the high frequency bandwidth component upon waveform equalization. 
         [0007]    Meanwhile, as an effective detection method, a maximum likelihood detection method is known. In this method, detection performance is increased by selecting one having a minimum square mean error from among all possible time-series patterns for a data stream in which occurrence of a state transition is known. However, it is difficult to perform the above processing in an actual circuit from the viewpoint of a circuit size and an operation speed. For this reason, typically, the maximum likelihood detection method is realized by using algorithm called a Viterbi algorithm to recursively select a path. The maximum likelihood detection method using the Viterbi algorithm is referred to as Viterbi decoding or Viterbi detection. 
         [0008]    A detection method in which the PR equalization and the Viterbi detection are combined is referred to as a PRML (Partial Response Maximum Likelihood) method. In a reproduction waveform after the PR equalization, only a specific state transition appears because of the PR equalization and modulation restriction. By using this to select a state transition path that minimizes the square mean error, the detection data error can be reduced. In particular, it is known that a code having the minimum run length of 1, such as the 17PP modulation code, and the PR equalization are fit with each other, and therefore a large detection margin can be obtained upon reproduction from a high record density of disc. 
         [0009]    In order to increase the detection performance by the Viterbi detection, a frequency characteristic of a reproduction channel should be made to match to a characteristic of specific PR equalization such as PR (3, 4, 4, 3). In such a case, the PR equalization characteristic as close to the frequency characteristic of the reproduction channel as possible are selected. However, in the field of an optical disc, which handles replaceable media, a frequency characteristic of a reproduction signal is not unique. Also, the characteristics are changed due to degradation of an optical pickup, lens stain, or the like. For this reason, as a technique for adaptively correcting the frequency characteristic to increase the detection performance, an automatic equalization or adaptive equalization method is required. As an adaptive equalization algorithm of a sequential type, in particular, a Zero Forcing Method, Mean Square Method, or the like is typically used. 
         [0010]      FIG. 1  illustrates a configuration example of a typical adaptive equalizer  200 . The adaptive equalizer  200  is provided with an equalizer  1 , a maximum likelihood detecting circuit  2 , an equalization error generating circuit  3 , delay circuits  9   a  to  9   e , and correlating circuits  8   a  to  8   e . The equalizer  1  is a typical N-tap FIR (Finite Impulse Response) filter. It is assumed that an input (digitalized RF signal drf) at time Ti is Xi, and each tap coefficient is α j  (j is an integer from 0 to N−1), an output (equalized signal eqo) Yi of the equalizer  1  is expressed by the following equation (1): 
         [0000]    
       
         
           
             
               
                 
                   Yi 
                   = 
                   
                     
                       ∑ 
                       
                         j 
                         = 
                         0 
                       
                       
                         N 
                         - 
                         1 
                       
                     
                      
                     
                       
                         X 
                         
                           i 
                           - 
                           j 
                         
                       
                       * 
                       
                         α 
                         j 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where the number of taps is N. 
         [0011]    The RF signal drf (Xi) that has been quantized in advance by an A/D converter of around 8 bits is equalized to a certain PR characteristic by the equalizer  1 , and outputted to the maximum likelihood detecting circuit  2  and the equalization error generating circuit  3  as the equalized signal eqo. The maximum likelihood detecting circuit  2  detects a binary data sequence Do from the equalized signal eqo. For example, the maximum likelihood detecting circuit  2  outputs, as the binary data sequence Do, data detected from the equalized signal eqo on the basis of the Viterbi detection. The equalization error generating circuit  3  calculates an ideal value Ri of an input to the maximum likelihood detecting circuit  2  on the basis of the binary data sequence Do, and outputs a difference between the actual input (equalized signal eqo (Yi)) and the ideal value Ri as an equalization error err (ei). The equalization error (ei) is expressed by the following equation (2): 
         [0000]        ei=Yi−Ri   (2)
 
         [0012]    Further, a power P of the equalization error ei can be expressed by the following equation (3), which forms a superquadric surface with respect to the N-dimensional tap coefficient α j : 
         [0000]    
       
         
           
             
               
                 
                   P 
                   = 
                   
                     
                       ∑ 
                       
                         i 
                         = 
                         0 
                       
                       M 
                     
                      
                     
                       ei 
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0013]    Accordingly, by correcting the tap coefficient α j  in the direction of −grad P=(−∂P/α 0 , −∂P/α 1 , . . . , −∂P/α N−1 ), a minimum point of P is obtained. That is, given that a j th  tap coefficient value at the time T i  is α j   i , the adaptive equalization can be achieved by the sequential correction: 
         [0000]      α j   i+1 =α j   i   −Δ∂P/α   j =α j   i   −α′X   i−j   *ei   (4)
 
         [0014]    In order to realize the above equation (4) by use of a circuit, equalizer inputs X i−j  respectively having different phases are generated by the delay circuits  9   a  to  9   e . Further, the correlation between X i−j  and the equalization error Ri is calculated by the correlating circuits  8   a  to  8   e , and a result of the calculation is fed back to the equalizer  1  as tap coefficients α 0  to α 4 . Thus, all of the prepared tap coefficients α 0  to α 4  are sequentially corrected, and after a certain time has passed, the tap coefficients α 0  to α 4  are converged. Each of the correlating circuits  8   a  to  8   e  includes a multiplier, an integrator (adder), and a delay circuit. Typically, correlating circuits for the number of the taps N are required in the equalizer  1 . 
         [0015]      FIG. 2  is a timing chart illustrating clock timing at the time of adaptive equalization operation in the conventional technique, and variation timings of the respective tap coefficients. Referring to  FIG. 2 , in the conventional technique, the correlating circuits for the number of the taps N (five in this case) are present, and therefore all of the tap coefficients α 0  to α 4  are sequentially corrected every one clock. For example, at time T 1 , α 0   0  to α 4   0  are corrected to α 0   1  to α 4   1 . 
         [0016]    Meanwhile, a reproduction signal from a disc recorded in a higher density receives larger influence of the intersymbol interference. For example, it may be influenced by data that is present a ten and a few channel clocks away from a sampling point. In order to adaptively equalize such a signal, the order of the FIR filter (the number of the taps in the equalizer) should be increased. That is, in order to reduce the influence of the intersymbol interference, the number of correlating circuits should be increased, each of which includes multipliers and integrators requiring large circuit areas. Further, if, in order to achieve a high speed read in association with high density recording, parallel processing is performed, the number of correlating circuits should be further increased. The increase in the number of circuits causes not only a cost increase in association with an increase in die size of an LSI but many problems such as a reduction in yield, increase in test time, and increase in power consumption. 
         [0017]    In this context, a method for reducing a circuit amount with respect to parallel processing is described in patent literature 1.  FIG. 3  is a diagram illustrating a configuration of an adaptive equalizer described in the patent literature 1. Referring to  FIG. 3 , the adaptive equalization circuit is provided with two transversal filters  10   a  and  10   b , tentative discriminators  11   a  and  11   b , switches  12  and  13 , a correlator group  14 , and a control signal generator  15 . A synchronized reproduction signal is distributed into even-numbered values and odd-numbered values, which are separately inputted to the equalizers  10   a  and  10   b . The tentative discriminators  11   a  and  11   b  respectively output equalization errors corresponding to outputs from the two equalizers  10   a  and  10   b . The transversal filters  10   a  and  10   b  use the common correlator group  14  on the basis of switching operation by the switches  12  and  13 . At this time, the switches  12  and  13  are controlled by the control signal generator  15 . Thus, the number of correlators is a half of the total number of taps in the transversal filters  10   a  and  10   b.    
         [0018]    Also, patent literature 2 proposes a method of performing synchronization at a lower rate than a channel rate to perform equalization, and restores an output of the equalization to channel rate synchronization timing by interpolation to perform maximum likelihood detection. In the patent literature 2, on the basis of this method, an increase in the number of circuits in association with an increase in speed can be suppressed. 
       Citation List 
     Patent Literature 1: JP 2004-79013A 
     Patent Literature 2: JP 2008-181583A 
     SUMMARY OF THE INVENTION 
       [0019]    The method described in the patent literature 1 is effective if there are a plurality of equalization filters. However, the correlator group  14  itself cannot be decreased in size. Also, even by the method described in the patent literature 2, a correlator group itself cannot be decreased in size. In particular, in the case of a reproduction signal from a disc recorded in a high density, the number of taps increases, and in proportion to the increase, the correlator group is also increased in size. 
         [0020]    In an aspect of the present invention, an adaptive equalizer includes: an equalizer configured to equalize a digital RF signal based on a plurality of tap coefficients; and a tap coefficient controller configured to correct the plurality of tap coefficients in a time division. 
         [0021]    In another aspect of the present invention, an information reproducing apparatus includes: an A/D (analog-to-digital) converter configured to convert a reproduction signal read from an information storage medium into a digital RF signal; an adaptive equalizer which includes: an equalizer configured to equalize the digital RF signal based on a plurality of tap coefficients, and a tap coefficient controller configured to corrects the plurality of tap coefficients in a time division; and a detecting circuit configured to detect a binary data sequence from an output of the equalizer. 
         [0022]    In still another aspect of the present invention, an adaptively equalizing method is achieved by equalizing a digital RF signal based on a plurality of tap coefficients; and by correcting each of the plurality of tap coefficients in a time division. 
         [0023]    As described above, in the present invention, a plurality of tap coefficients are corrected in time-division, and therefore it is not necessary to provide product-sum operation circuits respectively corresponding to the plurality of tap coefficients. Therefore, according to the present invention, a circuit scale of an adaptive equalizer can be reduced. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]    The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain embodiments taken in conjunction with the accompanying drawings, in which: 
           [0025]      FIG. 1  is a diagram illustrating the configuration of a conventional adaptive equalizer; 
           [0026]      FIG. 2  shows timing charts in a conventional adaptive equalization operation; 
           [0027]      FIG. 3  is a diagram illustrating the configuration of another conventional adaptive equalizer; 
           [0028]      FIG. 4  is a diagram illustrating the configuration of an adaptive equalizer according to an embodiment of the present invention; 
           [0029]      FIG. 5  is a diagram illustrating the configuration of a tap coefficient register shown in  FIG. 4 ; 
           [0030]      FIG. 6  is a diagram illustrating the configuration of an information reproducing apparatus according to an embodiment of the present invention; 
           [0031]      FIG. 7  shows timing charts in an adaptive equalization operation in the embodiment; 
           [0032]      FIG. 8  shows timing charts in the adaptive equalization operation in another embodiment; and 
           [0033]      FIG. 9  shows timing charts in the adaptive equalization operation in another embodiment. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0034]    Hereinafter, an adaptive equalizer of the present invention will be described with reference to the attached drawings. In the drawings, the same or similar reference numerals denote the same or similar components. 
         [0035]    Referring to  FIG. 4 , a configuration of an adaptive equalizer  100  according to an embodiment of the present invention will be described.  FIG. 4  is a diagram illustrating the configuration of the adaptive equalizer according to the embodiment of the present invention. The adaptive equalizer  100  is provided with an equalizer  1 , a maximum likelihood detecting circuit  2 , an equalization error generating circuit  3 , delay circuits  4   a  to  4   e , a product-sum circuit  5 , a timing controller  6 , and a tap coefficient register  7 . A description will be given, taking as an example an adaptive equalizer in which the number of taps is five. However, the number of taps is not limited to this. In addition, preferably, all of the equalizer  1 , the maximum likelihood detecting circuit  2 , the equalization error generating circuit  3 , the delay circuits  4   a  to  4   e , the product-sum circuit  5 , the timing controller  6 , and the tap coefficient register  7  operate in synchronization with the same clock signal. 
         [0036]    The equalizer  1  is preferably a typical N-tap FIR (Finite Impulse Response) filter. In the present embodiment, as the equalizer  1 , a five-tap FIR filter (tap coefficients α 0  to α 4 ) is used. The equalizer  1  is supplied with a reproduction signal (digitalized RF signal drf) obtained from a storage medium such as an optical disc. The digitalized RF signal drf is generated by an A/D converter that samples an RF signal at timing synchronized with the digitalized RF signal drf. 
         [0037]    An internal characteristic of the equalizer  1  is the same as that of a typical FIR filter. Supposing that the digitalized RF signal drf at time T i  is X i , and each of the tap coefficients is α j  (j is an integer from 0 to N−1), an output (equalized signal eqo) Y i  of the equalizer  1  is expressed by the equation (1), where the number of taps is N. The digitalized RF signal drf is equalized to certain PR characteristics by the equalizer  1 , and outputted to the maximum likelihood detecting circuit  2  and equalization error generating circuit  3  as the equalized signal eqo. For example, the digitalized RF signal drf is equalized to a PR(3, 4, 4, 3) channel, and outputted as the equalized signal eqo. 
         [0038]    The maximum likelihood detecting circuit  2  detects a binary data sequence Do from the equalized signal eqo on the basis of a predetermined algorithm that selects the most likely state transition. In order to extract PR equalization performance as much as possible, the maximum likelihood detecting circuit  2  preferably performs the Viterbi detection using the Viterbi algorithm. For example, when the digitalized RF signal drf is equalized to the PR(3, 4, 4, 3) channel, the maximum likelihood detecting circuit  2  detects the binary data sequence Do on the basis of the Viterbi detection corresponding to the PR(3, 4, 4, 3) channel. 
         [0039]    The equalization error generating circuit  3  calculates an ideal value Ri of an input to the maximum likelihood detecting circuit  2  on the basis of the binary data sequence Do, and outputs a difference between an actual input (equalized signal eqo (Yi)) and the ideal value Ri as an equalization error err (ei). The equalization error err (ei) is expressed by the above equation (2). By convolving a binary data sequence Do of an NRZI (Non Return to Zero Invert) format with impulse response of the PR characteristics, the ideal input (ideal value of the equalized signal eqo) Ri to the maximum likelihood detecting circuit  2  is obtained. The equalization error generating circuit  3  outputs the difference between the ideal input Ri and the actual input to the maximum likelihood detecting circuit  2  (equalized signal eqo (Yi)) as the equalization error err (ei). It should be noted that in consideration of the binary data sequence Do that is largely delayed due to delay inside the maximum likelihood detecting circuit  2 , a tentative determination result having a small internal delay may be used for the generation of the equalization error err. The equalization error (ei) is inverted by a multiplier  52   c  (inverter), and then supplied to the product-sum circuit  5 . 
         [0040]    The input signal to the equalizer  1 , i.e., the digitalized RF signal drf is delayed by the delay circuit  4   a  by an amount corresponding to the summation of internal delays of the maximum likelihood detecting circuit  2  and equalization error generating circuit  3 , and then outputted as a signal W 0  to the product-sum circuit  5 . Also, the signal W 0  is further delayed by the delay circuits  4   b  to  4   e  connected to the delay circuit  4   a  in series, and then outputted to the product-sum circuit  5  from them as signals W 1  to W 4 . Each of the delay circuits  4   b  to  4   e  shifts a phase of a signal inputted thereto every one clock, and then outputs the signal to the product-sum circuit  5  as each of the signals W 1  to W 4 . 
         [0041]    The product-sum circuit  5  is provided with selectors  51   a  and  51   b , multipliers  52   a  and  52   b , and an adder  53 . The selector  51   a  selects any of the signals W 0  to W 4  inputted through the delay circuits  4   a  to  4   e , and outputs it to the multiplier  52   a  as a signal W. At this time, the selector  51   a  determines a signal to be selected as the signal W according to a control signal N tap  from the timing controller  6 . The multiplier  52   a  multiplies the signal W selected by the selector  51   a  by the equalization error err inputted through the multiplier  52   c . A result of the multiplication is multiplied by g by the multiplier  52   b . Here, g is equivalent to a loop gain in adaptive equalization control. If μ is large, a convergence rate increases, but the control is susceptible to noise. On the other hand, if μ is small, the convergence rate decreases, but the control is resistant to noise. It should be noted that the multiplier  52   b  is not necessarily configured by use of a multiplier, but can be realized simply with a bit shift register if g is limited to a multiplier corresponding to a power of two. 
         [0042]    The selector  51   b  selects any of the tap coefficients α 0  to α 4  stored in the tap coefficient register  7  to output it to the adder  53  as a tap coefficient α. At this time, the selector  51   b  selects the tap coefficient α to be outputted to the adder  53  in response to the control signal N tap  from the timing controller  6 . The adder  53  adds the multiplication result by the multiplier  52   b  and the tap coefficient α selected by the selector  51   b , and outputs the resultant to the tap coefficient register  7  as a corrected tap coefficient α a . 
         [0043]    The signal pair (W, α) selected by the selectors  51   a  and  51   b  is controlled by the control signal N tap  from the timing controller  6 , and any of (W 0 , α 0 ) (W 1 , α 1 ) (W 2 , α 2 ) (W 3 , α 3 ) or (W 4 , α 4 ) is selected. Also, the timing controller  6  controls a data writing operation into the tap coefficient register  7  based on an enable signal en[0:4], in which a bit number corresponds to the number of taps (N=5 in this case). 
         [0044]      FIG. 5  is a diagram illustrating an example of a configuration of the tap coefficient register  7 . The tap coefficient register  7  has registers for the number of taps (N). In the present embodiment, the tap coefficient register  7  has registers  71   a  to  71   e  corresponding to the tap coefficients α 0  to α 4 . The registers  71   a  to  71   e  are connected to the output (corrected tap coefficient α a ) from the product-sum circuit  5  in common. The respective registers  71   a  to  71   e  take in the corrected tap coefficient α a  according to the corresponding enable signal bits en[0] to en[4]. Specifically, each of the registers  71   a  to  71   e  operates in synchronization with the clock. However, only if a corresponding one of individual enable signals is true, a value is updated, whereas in the other cases, a previous value is held. By making any of the five enable signal bits en[0] to en[4] true, only a specific tap coefficient value can be updated. 
         [0045]    Also, the enable signal bits en[0] to en[4] may be independently controlled, or a plurality of enable signals may be controlled as a group. For example, by simultaneously setting the enable signal bits en[0] and en[4] and the enable signal bits en[1] and en[3] to be true (high level), the tap coefficients that are symmetrically positioned with respect to the central tap coefficient α 2  can be simultaneously updated to the same value. 
         [0046]    As described above, in the adaptive equalizer  100  according to the present invention, the product-sum circuit  5  that is a main component of the correlating circuit is made common to the plurality of taps, and each of the tap coefficients is corrected through the time division operation according to the control by the timing controller  6 . Thus, a circuit amount of the adaptive equalizer can be largely reduced. In the present invention, the time division operation makes a coefficient conversion rate to be reduced. However, a rate at which frequency characteristics of the equalization input signal (digitalized RF signal drf) change is small, and therefore after the convergence has completed once, it is not necessary to increase the number of corrections. For this reason, the reduction in rate through the time division operation has a fully allowable magnitude. 
         [0047]    It should be noted that the product-sum circuit  5  can be described as a product-sum circuit with an input selection function. Also, the delay circuits  4   a  to  4   e , the product-sum circuit  5 , the timing controller  6 , and the tap coefficient register  7  can also be collectively referred to as a tap coefficient controller  30 . 
         [0048]    In the example illustrated in  FIG. 4 , only one product-sum circuit  5  is provided. However, two or more product-sum circuits may be provided. In such a case, a plurality of tap coefficient registers  7  respectively corresponding to the plurality of product-sum circuits  5  are provided. For example, the total number of taps (N) is halved by two tap coefficient registers  7 , and one is controlled by a first product-sum circuit, whereas the other is controlled by a second product-sum circuit. In this way, the convergence rate can be improved, which is reduced through the time division operation. When an the number of product-sum circuits  5 A increases, circuit size increases as compared with the example illustrated in  FIG. 4 . However, if a plurality of tap coefficients are corrected by a common product-sum circuit, the circuit size can be decreased as compared with the conventional case. 
         [0049]    The adaptive equalizer  100  according to the present invention is preferably used for a data reproducing apparatus that obtains and reproduces data from an optical recording medium, or records data on the optical recording medium.  FIG. 6  is a diagram illustrating an example of a configuration of a data reproducing apparatus mounted with the adaptive equalizer  100  according to the present invention. The data reproducing apparatus that reproduces data from an optical recording medium  20  will be described as an example. 
         [0050]    Referring to  FIG. 6 , the data reproducing apparatus according to the present invention is provided with the adaptive equalizer  100 , an optical pickup device  21 , an actuator servo  22 , a pre-amplifier  23  (RF AMP), an A/D converter, a PLL (Phase Locked Loop) circuit  25 , a formatter  26  (FMT), an ECC demodulator  27  (ECC), and a system controller  28 . 
         [0051]    The optical recording medium  20  is rotated and controlled by a spindle motor (not shown). From the optical pickup device  21 , a focused beam is irradiated toward a record surface of the optical recording medium  20 . The actuator servo  22  detects a part of a reflected beam of the collected beam through a photo-detector (not shown) as a tracking signal and a focusing signal, and controls the collected beam to accurately follow a guide groove of the disc. On the other hand, the remaining part of the reflected beam reads fine marks on the disc, and a reproduction signal is extracted through the RF amplifier  23 . The reproduction signal passes through an analog filter (not shown), and then is digitalized by the A/D converter  24  with the accuracy of about 6 to 8 bits. 
         [0052]    The A/D converter  24  uses a clock generated by the PLL circuit  25  as a sampling clock signal to digitalize the reproduction signal. At this time, the PLL circuit  25  generates the clock signal that is synchronized with the reproduction signal (digitalized RF signal drf). Alternatively, the A/D converter  24  may perform sampling with a system clock signal that is not synchronized with a channel frequency, and then output a synchronized sampling signal to be supplied to the equalizer  1  through digital. PLL and resampling process, as the digitalized RF signal drf. 
         [0053]    The digitalized RF signal drf is supplied to the equalizer  1 , and then tap coefficients are corrected through the time division operation in the adaptive equalizer  100 . A binary data sequence Do that is an output of the maximum likelihood detecting circuit  2  is subjected to frame sync pattern removal and RLL demodulation by the formatter  26 . The demodulated data sequence is subjected to error correction processing by the ECC demodulator  27 , and then processed in the system controller  28  as data such as video data. 
         [0054]    Here, as an apparatus using the adaptive equalizer  100  according to the present invention, the data reproducing apparatus that extracts data from the optical recording medium  20  (optical disc) has been described. The present invention is preferable for an HDD, an optical disc device, and in particular, a data detecting device such as a BD (Blu-ray Disc) player. However, the adaptive equalizer  100  according to the present invention can also be used for reproduction processing in an HDD device or a magnetic tape apparatus, or a receiver for general baseband transmission. 
         [0055]    Referring to  FIG. 7 , an operation of the adaptive equalizer according to the present invention will be described.  FIG. 7  shows timing charts in the adaptive equalization operation. 
         [0056]    The timing controller  6  controls signal levels of the enable signal bits en[0] to en[4] in synchronization with a clock signal CLK. That is, the timing controller  6  switches to set any of bits of the enable signal en to a high level for each trigger edge of the clock signal CLK, and outputs a control signal N tap  corresponding to a tap coefficient to be corrected. In the example illustrated in  FIG. 7 , at each time synchronous with the clock signal CLK, only one enable signal bit is set to the high level, and the other enable signal bits are set to a low level. Thus, only one tap coefficient is corrected at each time. It should be noted that the tap coefficient α to be corrected is switched in the order of α 0 , α 1 , α 2 , α 3 , and α 4  by the selector  51   b . Specifically, at time T 1 , the tap coefficient α 0  (α o ) that is selected as a correction target is corrected to α 0   1  according to the enable signal bit en[0] having a true value. At the next time T 2 , the tap coefficient α 1  (α 1   −3 ) that is selected as a correction target is corrected to α 1   2  according to the enable signal bit en[1] having a true value. Similarly, at respective times T 3  to T 5 , the tap coefficients α 2   −2  to α 4   0  are corrected to α 2   3  to α 4   5 . Thus, according to the present example, all of the tap coefficients α 0  to α 4  are corrected in five clocks. 
         [0057]    In the conventional technique, the tap coefficients are corrected by the correlating circuits for the number of taps (e.g., five). For this reason, all of the tap coefficients can be corrected in one clock. On the other hand, in the present invention, the tap coefficients are corrected through the time division by use of one product-sum circuit. For this reason, a tap coefficient convergence time in the present invention becomes longer than the conventional case. However, the time variation in frequency characteristics of the input signal (digitalized RF signal drf) is minute, and therefore an influence on normal reproduction performance due to a reduction in convergence performance is small. Thus, according to the present invention, without reducing the normal reproduction performance, a circuit size of an adaptive equalizer can be reduced. 
         [0058]    In the example illustrated in  FIG. 7 , a tap coefficient to be corrected is switched through the cyclic time division operation such that the correction is repeated in the predetermined order. At this time, if the input signal (digitalized RF signal drf) is a singular signal having a period equal to an integral multiple of a tap coefficient correction timing period, a correlation is generated due to such a periodic property, and a tap coefficient may not be converged well. In some cases, a coefficient is diverged or converged to zero. In particular, in a medium in which randomization processing on data is not performed as in a CD format, such a problem may occur. 
         [0059]    For this reason, in order to solve the above problem, it is effective to provide a random number generator in the timing controller  6  to break the periodic property of the tap coefficient correction order. That is, the timing controller  6  controls the signal levels of the enable signal bits en and the control signal N tap  to randomly change a tap coefficient to be corrected. For example, as illustrated in  FIG. 8 , the tap coefficients to be corrected are randomly switched at times T 1  to T 7  as α 4 , α 1 , α 2 , α 1 , α 2 , α 3 , α 0 , . . . , and at the respective times, the corrections are performed as α 4   x  to α 4   1  α 1   2  to α 1   4  (time T 4 ), α 2   3  to α 2   5  (time T 5 ), α 3   X  to α 3   6  (time T 6 ), α 0   x  to α 0   7  (time T 7 ), and so on (where x is an randomly selected integer). As described, the tap coefficients α are randomly corrected, and thereby the correlation depending on the periodic property of the input signal (digitalized RF signal drf) can be eliminated to avoid the above problem. The random number generator can be realized with a very small circuit by using an M sequence generator including a feedback shift register, or the like. 
         [0060]    As described above, in the present invention, the tap coefficients are corrected through the time division operation, and therefore the tap coefficient convergence rate is reduced. On the other hand, if value of the multiplication factor μ of the multiplier  52   b  is increased, the tap coefficient convergence rate can be improved. However, in such a case, the tap coefficient is likely to be influenced by noise, and therefore stability of it is lost. On the other hand, if a waveform distortion due to TAN tilt or the like is small, converged tap coefficients are ideally symmetrical with respect to the central tap. For this reason, by simultaneously correcting the tap coefficients α o  to α 4 , i.e., the plurality of taps that are symmetrical with respect to the central tap (tap coefficient α 2 ), stabilities of the tap coefficients can be ensured. For example, when the number of taps is N (N is an odd number in this case), an i th  tap coefficient α i  is corrected simultaneously with an [N−(i−1)] th  tap coefficient α N−(i−1)  that is positioned symmetrically with respect to the central tap. Also, when the number of taps is N (N is an even number in this case), an i th  tap coefficient α i  is corrected simultaneously with an [N−(i−2)] th  tap coefficient α N−(i−2)  that is positioned symmetrically with respect to the central tap. 
         [0061]    Accordingly, by setting the multiplication factor μ of the multiplier  52  to a large value and symmetrically correcting the tap coefficients, the tap coefficient convergence rate can be improved so as to be hardly influenced by noise. An example of tap coefficient correcting operation for this case is illustrated in  FIG. 9 . 
         [0062]    In the example illustrated in  FIG. 9 , the timing controller  6  controls the enable signal bits en[0] and en[4] to the same signal level, and the enable signal bits en[1] and en[3] to the same signal level. The timing controller  6  simultaneously corrects the tap coefficients α 0  and α 4  (time T 1 ), then simultaneously corrects the tap coefficients α 1  and α 3  (time T 2 ), and subsequently corrects the tap coefficient α 2  (time T 3 ). After that, the same procedure is repeated, and the tap coefficients are corrected until the tap coefficients α 0  to α 4  are converged. In the example illustrated in  FIG. 7 , five clocks are required to correct all of the tap coefficients α 0  and α 4 . However, in the example illustrated in  FIG. 9 , the corrections can be made only with three clocks, and therefore the tap coefficient convergence rate can be improved. 
         [0063]    From the view of the tap coefficient stability, the tap coefficient convergence rate may be preferably temporarily improved. For example, in an optical disc device, there is the case where data is desired to be reproduced as quickly as possible immediately after the seek. In this case, there is preferably a function that temporarily increases the convergence rate of the adaptive equalizer  100 . For this reason, the timing controller  6  is switched to symmetrical tap control (mode in which tap coefficients are symmetrically corrected) as illustrated in  FIG. 9  only at the time of fast data acquisition (e.g., immediately after the seek), and in the other periods, performs correction control (normal operation mode in which tap coefficients are sequentially corrected one by one) as illustrated in  FIG. 7  or  8 . For example, during a certain period immediately after the seek, by increasing μ and correcting tap coefficients on the basis of the symmetrical tap control, and then by restoring the control to the normal operation, the convergence rate can be temporarily increased, 
         [0064]    As described above, according to the present invention, the product-sum circuit that is a main component of the correlating circuit is made common to the plurality of taps, and therefore a circuit amount of the adaptive equalizer can be largely reduced as compared with the conventional case. That is, the present invention can reduce a circuit scale of an adaptive equalizer having an equalizer with a large number of taps. Also, a scale of a circuit that operates when tap coefficients are corrected is reduced, and therefore a power consumption amount of an adaptive equalizer, or a data reproducing apparatus using it can be reduced. 
         [0065]    Also, the variation in frequency characteristics of the equalization input signal (digitalized RF signal drf) is gradual, and therefore after the first convergence, even in the case of the coefficient corrections through the time division operation, the tap coefficients can be corrected with following the signal variation. 
         [0066]    Further, by correcting the tap coefficients in a random order, the correlation between the period of the time division operation and the input signal having the periodic property can be eliminated. For this reason, unstable operation such as divergence or zero convergence of a tap coefficient can be avoided. That is, even for any signal, stable adaptive control can be performed. 
         [0067]    As above, the embodiments of the present invention have been described in detail. However, a specific configuration is not limited to the above-described embodiments, but any modification without departing from the scope of the present invention is included in the present invention. The methods for correcting tap coefficients illustrated in  FIGS. 7 to 9  may be combined within a technically feasible range. In such a case, any of the correction timings illustrated in  FIGS. 7 to 9  may be switched at arbitrary timing to correct tap coefficients.