Abstract:
A thin film transistor includes a low resistance metal film covering a drain region and an interconnecting metal line disposed thereon. Covering the drain region with the low resistance metal film reduces oxidation in the drain region, and thus reduces the contact resistance between the drain region and the interconnecting metal line.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method of manufacturing a thin film transistor and more specifically, to a method of manufacturing a thin film transistor where the contact resistance between an impurity-doped silicon layer and an interconnecting metal line is reduced. The interconnecting metal line is in contact with the silicon layer and forms both the drain and pixel electrodes. 
     2. Description of the Background Art 
     Amorphous silicon (a-Si) TFT LCDs (Thin Film Transistor Liquid Crystal Displays) are increasingly being used in more diverse applications such as notebook PCs and desk top monitors. The growth of the TFT-LCD industry along with wider acceptance of TFT-LCD related applications have occurred because of the improvements in screen resolution and screen size of TFT LCDs. Further, the key to sustaining this growing trend is manufacturing TFT LCDs with greater productivity so that the price of TFT LCDs become more affordable to consumers. To realize significant gains in productivity, the manufacturing process must be simplified, and this can only occur if there is cooperation among all those involved in the manufacture of LCDs. 
     FIGS. 1A-1D are cross-sectional views illustrating a process manufacturing a thin film transistor according to the prior art. 
     As shown in FIG. 1A, silicon oxide is deposited on an insulating substrate  100  such as glass to form a buffer oxide layer  102 . Polysilion is then deposited on the insulating substrate  100  and covers the buffer oxide layer  102 . The polysilicon is thereafter patterned via an etching process to form an active layer  104 . 
     Referring to FIG. 1B, a gate insulating layer  106  is formed on the buffer oxide layer  102  and covers the active layer  104 . The gate insulating layer  106  is formed by depositing silicon oxide via chemical vapor deposition (CVD). Next, a gate electrode  108  is formed so as to cover a selected portion of the active layer  104 . The gate electrode  108  is created by sputtering a metal such as aluminum or molybdenum to form a metal film, and then patterning the metal film via an etching process. 
     Thereafter, the entire surface of the insulating substrate  100  is heavily doped with n or p type impurity ions with the gate electrode  108  functioning as a mask. After the doping process, heavily doped impurity regions are formed within the active layer  104  on both sides of the gate electrode  108 . These regions serve as a source region S 1  and a drain region D 1 . 
     Referring to FIG. 1C, an interlevel insulating layer  110  covers the entire surface of the structure. It is then patterned via an etching process to create a first contact hole c 1 , which leaves the source region S 1  exposed. A source electrode  112  electrically connected to the source region S 1  is provided. Next, a protective layer  114  is deposited on the entire surface of the structure. 
     Referring to FIG. 1D, a second contact hole c 2  is created within the protective layer  114  and the interlevel insulating layer  110 , thus exposing the drain region D 1 . Thereafter, ITO (Indium Tin Oxide) is deposited on the protective layer  114  and then patterned via an etching process so as to cover the second contact hole c 2 . This process forms an interconnecting metal line  120 . The interconnecting metal line  120  serves both as a pixel electrode and a drain electrode because it is connected to the drain region D 1  of the active layer  104 . 
     Thus, in the prior art, the ITO is deposited directly on the drain region to form the interconnecting metal line. The direct contact between the drain region and the ITO causes an increase in the contact resistance between the drain region and the ITO because an oxide layer is formed therebetween. Therefore, a contact failure may occur in the interconnecting metal line when it is connected to the drain region. 
     SUMMARY OF THE INVENTION 
     To overcome the problems described above, preferred embodiments of the present invention provide a method for manufacturing a thin film transistor which greatly reduces contact resistance between an impurity-doped silicon layer and an interconnecting metal line without increasing the cost or difficulty of manufacturing the thin film transistor. 
     According to a preferred embodiment of the present invention, a method for manufacturing a thin film transistor includes providing an exposed drain region on an insulating substrate and covering the exposed drain region with a low resistance metal film. 
     According to another preferred embodiment, a method for manufacturing a thin film transistor includes forming an active layer on an insulating substrate, forming a gate insulating layer on the active layer, forming a metal film on the gate insulating layer, patterning the metal film to form a gate electrode, forming a source region and a drain region by heavily implanting a first conductivity type impurity into the active layer using the gate electrode as a mask, forming an interlevel insulating layer and exposing the source region by patterning the interlevel insulating layer, forming a source electrode on the source region, forming a protective layer and patterning the protective layer so as to expose the drain region on the interlevel insulating layer, covering the drain region with a low resistance metal film and forming an interconnecting metal line so as to cover the low resistance metal film. 
     According to another preferred embodiment of the present invention, a method of manufacturing a thin film transistor includes the steps of forming an active layer on an insulating substrate, applying a gate insulating layer on the active layer, sputtering a metal such as aluminum or molybdenum to form a metal film on the gate insulating layer, patterning the metal film to form a gate electrode, forming source and drain regions by heavily implanting impurity ions into the active layer using the gate electrode as a mask, forming an interlevel insulating layer covering the entire surface of the resulting structure and patterning the insulating layer so as to expose the source region, forming a source electrode covering the source region, forming a protective layer and patterning it to expose the drain region on the interlevel insulating layer, depositing a low resistance metal film so as to cover the drain region, and forming an interconnecting metal line that covers the low resistance metal film. 
     Another preferred embodiment provides a thin film transistor including an insulating substrate, a drain region on the insulating substrate and a low resistance metal film that covers the drain region. 
     Various other features, elements, and advantages of the present invention will be readily appreciated as the same becomes better understood with reference to the following detailed description of preferred embodiments when considered in connection with accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE ATTACHED DRAWINGS 
     The present invention will become more fully understood from the detailed description provided below and the accompanying drawings which are given by way of illustration only, and thus do not limit the present invention and wherein: 
     FIGS. 1A-1D are cross-sectional views illustrating a process for manufacturing a thin film transistor according to the prior art; and 
     FIGS. 2A-2E are cross-sectional views illustrating a process for manufacturing a thin film transistor according to preferred embodiments of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIGS. 2A-2E are cross-sectional views illustrating a process for manufacturing a thin film transistor according to preferred embodiments of the present invention. 
     Referring to FIG. 2A, silicon oxide is deposited on an insulating substrate  200  such as glass to form a buffer oxide layer  202 . Next, polysilicon is deposited on the buffer oxide layer  202  and then patterned preferably via an etching step so that the patterned polysilicon forms an active layer  204 . The buffer oxide layer  202  is provided to suspend defective induction. This can be caused by movement of the silicon component of the polysilicon towards the substrate during deposition of the polysilicon. The buffer oxide layer  202  also is arranged to function as a buffer between the insulating substrate  200  and the active layer  204 . 
     Note that the active layer  204  may also be formed from amorphous silicon instead of polysilicon. However, if amorphous silicon is used to form the active layer  204 , the amorphous silicon is instantaneously heated at a high enough temperature to achieve crystallization. This can be achieved with the use of a laser or some other suitable device. 
     Referring to FIG. 2B, a gate insulating layer  206  is formed on the buffer oxide layer  202  and covers the active layer  204 . A metal film is then formed on the gate insulating layer  206  and the active layer  204  preferably by sputtering a metal such as aluminum or molybdenum, or other suitable material. Next, the metal film is patterned preferably via an etching process to cover only a portion of the active layer  204 , and thus, the patterned metal layer forms a gate electrode  208 . 
     The gate electrode  208  is used as a mask while n type impurity ions heavily dope the entire surface of the insulating substrate  200 . The doping process creates heavily doped impurity regions on both sides of the gate electrode  208  within the active layer  204 . These regions serve as source region S 2  and drain region D 2 . 
     Referring to FIG. 2C, an interlevel insulating layer  210  is formed by covering the entire surface of the structure. The interlevel insulating layer  210  is then etched until the source region S 2  of the active layer  204  is exposed. This process forms a first contact hole C 3 . Next, a metal film is formed on the interlevel insulating layer  210  and covers the first contact hole C 3 . The metal film is patterned by an etching process so that it is connected to the source region S 2 , and thus forms the source electrode  212 . Thereafter, a protective layer  214  is formed to cover the entire surface of the structure. 
     Referring to FIG. 2D, the protective layer  214  is patterned preferably via an etching process to create a second contact hole C 4 , thus exposing the drain region D 2 . A metal film  218 , hereinafter referred to as the low resistance metal film, made from an In film, Sn film or In/Sn alloy film or other suitable material is formed on the protective layer  214  and covers the second contact hole C 4 . In this preferred embodiment, the thickness of the low resistance metal film  218  should be in the range of about 100-200 angstroms. 
     Referring now to FIG. 2E, ITO (Indium Tin Oxide) is deposited on the low resistance metal film  218  preferably via sputtering or chemical vapor deposition. Note, when IZO (Indium Zinc Oxide) instead of ITO is deposited on the low resistance metal film  218 , In, Zn or In/Zn alloy may be used for the low resistance metal film. The ITO is then patterned preferably via an etching process to cover the second contact hole C 4 , and thus forms an interconnecting metal film (conductive material)  220 . Finally, the low resistance metal film  218  is now patterned with the conductive material  220  functioning as a mask. 
     Except for certain portions, the low resistance metal film  218  is oxidized by the oxygen in the atmosphere during ITO deposition and other processes so that it becomes transparent. Further, the conductive material  220  serves both as a pixel electrode and a drain electrode because it is connected to the drain region D 2  of the active layer  204 . 
     As described above, the preferred embodiments of the present invention have many advantages over the prior art such as the contact resistance being greatly reduced in the present invention. More specifically, the contact resistance is greatly reduced because the second contact hole C 4  is oxidized much less because of the existence of the low resistance film between the impurity-doped silicon layer and the ITO. Further, there is no need for an additional mask because the low resistance metal film is patterned using a photo-mask when forming the interconnecting metal line. 
     While the invention has been particularly shown and described with reference to preferred embodiments, it will be understood by those skilled in the that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.