Abstract:
An open drain driver circuit generates four switching signals to switch respective sets of current driving transistors on and off. The switching signals have slightly different transition times, and the rate at which the magnitude of each switching signal changes during each transition is controlled throughout each transition to maximize the switching times while slowing the rate of change during certain portions of each transition to prevent excessive changes in the rate at which the current changes. As a result, voltage transients generated in power supply lines coupled to the driver circuit have relatively small peak amplitude.

Description:
TECHNICAL FIELD 
     This invention relates integrated circuits, and, more particularly, to a method and system for controlling the slew rate of a signal applied to a transmission line using open drain technology to minimize inductive voltage transients internal to packaged devices and minimize other voltage asperties coupled to the transmission line. 
     BACKGROUND OF THE INVENTION 
     As the operating speed of electronic systems, such as computer systems and memory devices, continue to increase, the speed at which digital signals must be coupled continues to increase. As a practical matter, the speed at which a digital signal may be coupled through a signal line is reduced if the signal is reflected from various nodes in the signal line, such as connections to the signal line by various electronic circuits. Reflection of digital signals may be avoided by coupling the digital signals through a transmission line having an impedance matched to the impedance of circuitry coupled to the line. Electronic circuits can be designed to be impedance matched to a transmission line in this manner if the number of electronic circuits coupled to the line and the impedance of such circuits remains fixed. However, it is common to vary the number of electronic circuits coupled to a signal lines. For example, in computer systems, the number of memory modules coupled to a memory controller through a data bus, address bus, and control bus may vary. If these buses are impedance matched to the memory modules when the computer system is initially placed in service, the buses may not be impedance matched when additional memory modules are coupled to the buses. 
     One conventional approach to allowing a varying number of electronic devices to be coupled to a transmission line while maintaining impedance matching between the devices and the line is through open drain technology. The principle of open drain technology can be explained with reference to FIG.  1 . As shown in FIG.  1 , a memory controller  10  generating a binary signal is coupled to one end of a transmission line  14 . An opposite end of the transmission line  14  is coupled to a voltage source  16  through a terminating resistor  18 . For purposes of illustration, the voltage of the voltage source  16  is assumed to be 1.5 volts, although it may be any voltage in practice. The resistance of the terminating resistor  18  is substantially the same as the characteristic impedance Z 0  of the transmission line  14 . For purposes of illustration, the characteristic impedance Z 0  of the transmission line  14  and the resistance of the resistor  18  is assumed to be 20 ohms. The signal generated by the memory controller  10  is a switched current signal that switches between two values of current. For example, one binary value may be represented by a current of 0 ma., and the other binary value may be represented by a current of 25 ma. Under these circumstances, a voltage V 0  at a node  20  to which the transmission line  14  is coupled will switch between 1.5 volts when the current is 0, and 1.0 volt when the current is 25 ma. The voltage V 0  at the node  20  thus switches between two levels to represent respective binary values. Also coupled to the transmission line  14  at a plurality of respective nodes  22   a,b . . . n  are memory devices  24   a,b . . . n  , which also output a switched current signal. 
     Although the voltage at the nodes  20  and  22   a,b . . . n  switch between two values, the effect of doing so by varying the current between two values is significantly different from simply using a switched voltage source to drive the voltage applied to the nodes  20  and  22   a,b . . . n  between two values. If, for example, the memory device  24   b  outputs a switched voltage signal on the transmission line  14 , the signal will propagate through the transmission line  14  away from the memory device  24   b  in both directions. When the signal reaches the memory controller  10 , it will be reflected from node  20  because of the impedance mismatch between the 25 ohm characteristic impedance of the transmission line  14  and the high impedance at the input to the inactive memory controller  10 . By the time the reflected signal reaches the memory device  24   a , the memory device  24   a  may be outputting a signal. If the memory device  24   a  was outputting a switched voltage signal, the voltage at the node  22   a  would remain constant despite the reflected signal reaching the node  22   a  because the memory device  24   a  would draw or provide sufficient current to maintain the voltage substantially constant. The magnitude of an impedance from an A.C. or transient point of view is proportional to the ratio of the change in voltage to the change in current. Consequently, the input impedance of the memory device  24   a  resulting from a small change in voltage and a large change in current is relatively small. The low impedance of the memory device  24   a  would cause further reflection of signal from the node  22   a . Furthermore, the impedance at each node  22   a,b . . . n  would change greatly depending upon whether a memory device  24   a,b . . . n  was coupled to the node  22   a,b . . . n.    
     If a signal was reflected from the memory controller  10  and the memory device  24   a  was outputting a current switched signal, the effect would be substantially different. In such case, the voltage at the node  22   a  would change responsive to the reflected signal reaching the node  22   a  because the memory device  24   a  maintains the current substantially constant. Consequently, the input impedance of the memory device  24   a  resulting from a relatively large change in voltage and a very small change in current is relatively large. In fact, the impedance of the memory device  24   a  may be so large that the memory device  24   a  has no effect on the signal reflected from the memory controller  10 . Under these circumstances, the memory device  24   a  does not even electrically appear to be coupled to the transmission line  14 . The memory devices  24   a,b . . . n  can therefore be added or removed to the transmission line  14  without altering the performance of the transmission line  14 . 
     In practice, the memory controller  10  and the memory devices  24  are able to drive the transmission line  14  with a switched current signal through a drain of a MOSFET transistor (not shown) that is “open” or unconnected to any other circuitry. The advantages of using this open drain technology are not entirely without some countervailing disadvantages. One disadvantage is the switching of current supplied or drawn by an open drain device generally results in a corresponding change in the power supply current drawn by the device. This change in current drawn by the device through inductive power supply lines (not shown) can produce voltage transients on the power supply lines that result in power supply noise. Such power supply noise can adversely affect the operation of other circuitry in the open drain device as well as other devices that are coupled to the same power source. 
     The magnitude of a voltage transient is proportional to the inductance of a power supply line through which the current is drawn and the first derivative of the current through the line as a function of time. Thus, reducing the rate of current change, i.e., the first derivative of the current, reduces the magnitude of the voltage transients generated in a power supply line. One approach to reducing the rate of current change in an open drain device will be explained with reference to FIGS. 2 and 3. As shown in FIG. 2, an open drain device outputs a switched current signal I that changes from I 0  to I 1  and then subsequently back to I 0 . The switched current signal I results in a voltage E that changes correspondingly from E 0  to E 1  and then subsequently back to E 0 . As also shown in FIG. 2, the first derivative I′ of the current signal I is a positive pulse coincident with the leading edge of the switched current signal and a negative pulse coincident with the falling edge of the switched current signal. 
     The peak magnitude of the first derivative I′ of the current signal I can be reduced using a conventional technique that will be explained with reference to FIG.  3 . As shown in FIG. 3, instead of using a single open drain transistor or several open drain transistors switched at the same time, several open drain transistors may be switched at two different times. As a result, the switched current signal I is composed of two switched current signals I 1 , I 2  each of which transitions at a different time. Each of these switched current signals I 1 , I 2  generates a respective voltage (not shown) and a respective first derivative I 1 ′, I 2 ′ of the switched current signals I 1 , I 2 . However, since the magnitude of each individual switched voltage signal I 1 , I 2 , is relatively small, so also is the magnitude of each individual first derivative signal I 1 ′, I 2 ′. As a result, the peak value of each of the first derivative signals I 1 ′, I 2 ′ is approximately one-half the magnitude of the first derivative signal I′ shown in FIG.  2 . 
     One conventional circuit for applying a switched current signal to a bus is shown in FIGS. 4 and 5. The circuit will be explained in the context of a memory device, although it will be understood that it may be used with other types of devices. With reference to FIG. 4, a delay circuit  100  receives a clock signal TCLKL and outputs a delayed clock signal TCL after a predetermined delay. Similarly, a delay circuit  102  receives a clock signal TCLKLB and outputs a delayed clock signal TCLB after a predetermined delay. The relative phases of the TCLKL, TCL, TCLKLB and TCLB signals are shown in FIG.  6 . As shown in FIG. 6, TCLKL and TCLKB are compliments of each other, and TCL and TCLB are delayed versions of TCLKL and TCLKLB, respectively. The TCLKL signal is initially low and the TCKLB signal is initially high so pass gate  114  is conductive. As a result the MUXI signal corresponds to the level of the READE (i.e., read even) signal from an even data path. In contrast, the READO signal is from an odd data path. When the TCLKL signal subsequently transitions high and the TCLKLB signal transitions low, the pass gate  104  becomes conductive and the pass gate  114  becomes non-conductive, this making the MUXI signal equal to the level of the READO signal. Thus, the MUXI signal is alternately equal to the READE and READO signals. The READE and READO signals are received at either a half data rate (i.e., on every fourth clock transition) or full data rate (i.e., on every other clock transistor), thus making the MUXI signal valid at the full data rate or a double data rate (i.e., every clock transition). 
     The MUXI signal is applied to the input of an inverter  110 . For purposes of explanation, assume the MUXI signal is initially low. The output of the inverter  110  is thus initially high, and it subsequently transitions low. The high-to-low transition at the output of the inverter  110  causes the output of an inverter  120  to transition from low to high. The low at the output of the inverter  110  also turns ON two PMOS transistors  124 ,  126  that couple the output of the inverter  120  to a supply voltage to assist in the low-to-high transition at the output of the inverter  120 . Parascitic capacitance represented by a capacitor  128  has the effect of slightly smoothing transitions at the output of the inverter  120 . The resulting signal Q is used by the circuitry shown in FIG. 5, as explained below. 
     A second pair of pass gates,  130 ,  132 , inverters  134 ,  136 , PMOS transistors  140 ,  142  and capacitor  146  are interconnected and operate in the same manner as described above with respect to the pass gates,  104 ,  114 , inverters  110 ,  120 , PMOS transistors  124 ,  126  and capacitor  128  except the pass gates  130 ,  132  are controlled by the delayed TCL and TCLB signals. As a result, a QL signal is generated from the READE and READO signals at a slightly later time than the Q signal is generated. The resulting signal QL is also used by the circuitry shown in FIG.  5 . 
     With reference to FIG. 5, a driver circuit  140  includes  11  current branch circuits  144   a-k  coupled in parallel to each other. Each of the branch circuits  144  includes a respective current regulating NMOS transistor  150   a-k  and a respective switching NMOS transistor  152   a-k . The current regulating transistors  150   a-k  preferably have binary weighted channel widths so that the channel width of each transistor  150  is twice as wide as the channel width of the adjacent transistor  150 . Thus, for example, the channel width of the transistor  150   c  is twice as wide as the channel width of the transistor  150   b , and the channel width of the transistor  150   d  is twice as wide as the channel width of the transistor  150   c , etc. The transistors  150   a-k  are selectively controlled by suitable control signals CNTL&lt;0:10&gt; that are generated by conventional means to select the current draw. The magnitudes of these CNTL&lt;0:10&gt; are typically ground potential or a voltage that is sufficiently low to provide a high drain-to-source impedence for the transistors  150   a-K . The switching transistors  152   a-g  are controlled by the Q signal generated by the circuitry shown in FIG. 4, as previously explained. The switching transistors  152   h-k  are controlled by the QL signal generated by the circuitry shown in FIG.  4 . 
     As explained above, the Q and QL signals have slightly different phases, thereby producing a switched current signal of the type shown in FIG. 3 composed of two different switched current components switching at different times. Even though the circuitry shown in FIGS. 4 and 5 reduces power supply noise resulting from the switched current signal, it nevertheless produces a degree of power supply noise that can be excessive in some applications. The peak magnitude of the power supply noise could be reduced by increasing the number of differently phased, switched current components used to produce the switched current signal. However, doing so might make the width of the switched current signal excessive and thereby limit the operating speed of memory devices using such open drain technology. 
     There is therefore a need for an open drain driver circuit and method that can further reduce the magnitude of induced power supply noise without limiting the operating speed of electronic devices using open drain technology. 
     SUMMARY OF THE INVENTION 
     An open drain driver circuit and method applies switched current signals to an output terminal responsive to a digital input signal applied to an input terminal. The open drain driver circuit includes a switch control circuit receiving a digital signal at the input terminal. The switch control circuit generates a plurality of switching signals each of which transitions between first and second voltage levels. Significantly, the rate at which at least one of the transitions occurs in a plurality of the switching signals is controlled in at least two phases. The open drain driver circuit also includes a current control circuit coupled to receive the switching signals. The current control circuit is structured to provide the switched current signals at the output terminal having a first magnitude responsive to the switching signals being at the first voltage level and having a second magnitude responsive to the switching signals being at the second voltage level. By controlling the rate at which at least one of the transitions occurs, the rate of change of the current corresponding to the switched current signals can be limited to minimize power supply noise. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is block diagram of a memory system using open drain technology in accordance with either the prior art or an embodiment of the invention. 
     FIG. 2 is a waveform diagram showing the current and voltage generated using basic open drain technology in accordance with the prior art. 
     FIG. 3 is a waveform diagram showing the current and voltage generated using an improved open drain technology in accordance with the prior art. 
     FIGS. 4 and 5 are block and logic diagrams of an open drain driver circuit using the prior art open drain technology generating current and voltage waveforms of the type shown in FIG.  3 . 
     FIG. 6 is a waveform diagram showing the timing of clock signals used in both the prior art circuit of FIGS. 4 and 5 and the embodiment of a circuit in accordance with the invention that is shown in FIGS. 7 and 8. 
     FIGS. 7 and 8 are block diagrams and logic diagrams of an open drain driver circuit creating a reduced level of power supply noise according to one embodiment of the invention. 
     FIG. 9 is a waveform diagram showing the current and voltage generated using the open drain driver circuit of FIGS. 7 and 8. 
     FIG. 10 is a block diagram of a computer system having a plurality of memory device each of which includes a plurality of the open drain driver circuits of FIGS.  7  and  8 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 7 and 8 show two portions of an open drain driver circuit according to one embodiment of the invention. The circuitry shown in FIG. 7 substantially corresponds in function to the prior art circuitry shown in FIG. 4, and the circuitry shown in FIG. 8 substantially corresponds in function to the prior art circuitry shown in FIG.  5 . In the interest of brevity and clarity, the components of both circuitry that perform and the same function in the same manner will be provided with the same reference numerals and a detailed explanation of such circuitry will not be repeated. As explained in greater detail below, the basic difference between the open drain driver circuit of FIGS. 7 and 8 and the prior art open drain driver circuit of FIGS. 4 and 5 is the open drain driver circuit of FIGS. 7 and 8 controls the rate at which the drive current changes during each transition. Basically, the open drain driver circuit of FIGS. 7 and 8 increases the voltage of the signals Q, Q 2 , QL, Q 2  relatively slowly during a first turn-on phase, and then increases the voltage substantially faster during a second turn-on phase. The voltage of the signals Q, Q 2 , QL, QL 2  in FIGS. 7 and 8 decreases relatively quickly during a first turn-off phase, then decreases substantially slower during a second turn-off phase, and then decreases substantially faster during a final turn-off phase. 
     With reference to FIG. 7, the MUXI and MUXIL signals are generated from the READE, READO, TCKL, and TCKLB signals in the same manner as in the prior art circuit shown in FIG.  4 . The MUXI signal is used to generate the Q signal through a first path formed by the inverters  110 ,  120 , the PMOS transistors  124 ,  126  and the parascitic capacitance  128  in the same manner as these components do so in the prior art circuit of FIG.  4 . When the MUXI signal transitions from low-to-high, this first path increases the magnitude of the Q signal relatively slowly to effect the first turn-on phase. During this first turn-on phase, the Q signal causes the circuit shown in FIG. 8 to increase the current drawn by the driver circuit relatively quickly despite the slow increase in the magnitude of the Q signal. 
     The MUXI signal is also applied to a second path formed by an inverter  160  and a pair of PMOS transistors  166 ,  168 . When the MUXI signal transitions high, the output of the inverter  160  does not immediately transition low. Instead, the output of the inverter  160  does not transition low until after it is enabled by an NMOS transistor  170  turning ON responsive to the Q signal reaching the threshold voltage V T  of the transistor  170 . The low at the output of the inverter  160  then turns ON the two PMOS transistors  166 ,  168 . Turning ON the transistor  166  substantially increases the rate at which the Q signal increases. Turning ON the transistor  168  substantially increases the rate at which the Q 2  signal increases, and also further increases the rate at which the Q signal increases through a resistor  174 . This more rapid increase in the rate at which the Q signal increases constitutes the second turn-on phase mentioned above. During this second turn-on phase, the more rapidly increasing Q signal, as well as the Q 2  signal, insure that both Q and Q 2  make it to a full high level before new data is coupled to the inverters  160 ,  110  the MUXI signal. 
     As previously mentioned, during turn-off, the current decreases in three phases. Prior to the MUXI signal transitioning low, the high MUXI signal turns ON a pair of NMOS transistors  180   a,b  (represented by a single transistor), thereby coupling the gate of a respective NMOS transistor  182   a,b  to ground to turn OFF the transistors  182   a,b . When the MUXI signal transitions low, the low MUXI signal and the resulting high signal at the output of the inverter  110  render respective pass gates  188   a,b  (again represented by a single pass gate) conductive. The pass gates  188   a,b  then couple the gates of the respective transistors  182   a,b  to their drains, which are also coupled to the respective Q and Q 2  signals. The transistors  182   a,b  then act as diodes through which the Q and Q 2  signals are coupled to ground. During this first turn-off phase, the high-to-low transition of the MUXI signal at the input of the inverter  110  is also coupled through the inverter  120  to assist in driving the Q signal low. Similarly, the high-to-low transition of the MUXI signal at the input of the inverter  160  causes the PMOS transistors  166 ,  168  to turn OFF, thereby assisting in driving the Q 2  signal low. As a result, the Q and Q 2  signals quickly decrease during this first turn-off phase. 
     When the magnitudes of the Q and Q 2  signals have decreased during the first turn-off phase to the threshold voltage V T  of the transistors  182   a,b , the transistors  182   a,b  turn OFF, so the Q and Q 2  signals are no longer shunted to ground. However, the Q and Q 2  signal are still being driven low through the inverters  110 ,  120 , and the inverter  160  and the PMOS transistors  166 ,  168 . The magnitudes of the Q and Q 2  signals decrease more slowly near the V T  of the transistors  182   a, b  during this second turn-off phase to cause the circuit shown in FIG. 8 to minimize the peak rate of change of the current. 
     The Q 2  signal is also applied to one input of a NOR gate  190 , which is enabled by the low MUXI signal. When the magnitude of the Q 2  signal has decreased during the second turn-off phase to a level corresponding to logic “0”, the output of a NOR gate  190  transitions high, thereby turning ON an NMOS transistor  194  to shunt the Q 2  signal to ground. The magnitude of the Q 2  signal then decreases at a more rapid rate during this third turn-off phase to insure Q 2  and Q through a resistor achieve ground potential before MUXI receives new data. 
     The portion of the driver circuit shown in FIG. 7 also includes circuitry  198  for generating QL and QL 2  signals. This circuitry is identical in structure and operation to the circuitry  198  for driving Q and Q 2  signals. Therefore, an explanation of the operation of such circuitry will not be repeated. The QL and QL 2  signals are driven high in the same two distinct turn-on phases as the Q and Q 2  signals, and they are driven low in the same three turn-off phases as the Q and Q 2  signals. 
     The Q, Q 2 , QL and QL 2  signals are applied to the portion of the driver circuitry shown in FIG.  8 . With reference to FIG. 8, three current branch circuits  200   a,b,c  are coupled in parallel with each other. Each of the branch circuits  200   a,b,c  includes a respective NMOS current regulating transistor  204   a,b,c  and a respective MOS switching transistor  208   a,b,c . The switching transistors  208   a,b,c  are driven by the Q signals. The current regulating transistors  204   a,b,c  are selectively controlled by suitable control signals CNTL&lt;0:10&gt; that are generated by conventional means to maintain the source-to-drain resistance of the transistors  204  relatively low. 
     The portion of the driver circuitry shown in FIG. 8 also includes five additional current branch circuits  200   d-h  that are also coupled in parallel with each other and with the current branch circuits  200   a,b,c . Each of the branch circuits  200   d-h  includes a respective NMOS current regulating transistor  204   d-h  and a respective pair of NMOS switching transistor  208   d-h  and  210   d-h  . The switching transistors  208   d-h  are driven by the Q signals, while the switching transistors  210   d-h  are driven by the Q 2  signals. As explained below, using a pair of transistors  208 ,  210  in each branch circuit  200  allows the rate of the current drawn by the branch circuits  200  to be better controlled while the current draw is being increased and decreased. 
     Finally, the driver circuitry shown in FIG. 8 also includes five additional current branch circuits  200   i-m  that are also coupled in parallel with each other and with the current branch circuits  200   a-h . Each of the branch circuits  200   i-m  includes a respective NMOS current regulating transistor  204   i-m  and a respective pair of NMOS switching transistor  208   i-m  and  210   i-m . The switching transistors  208   i-m  are driven by the QL signals, while the switching transistors  210   i-m  are driven by the QL 2  signals. Again, using a pair of transistors  208 ,  210  in each branch circuit  200  allows the rate of the current drawn by the branch circuits  200  to be better controlled while the current draw is being increased and decreased. 
     In operation, during the first turn-on phase, the slow increase in the magnitude of the Q signal turns ON the switching transistors  208   a-h  relatively slowly. During this same time, the slow increase in the magnitude of the QL signal turns ON the switching transistors  208   i-m  relatively slowly, but the time at which the switching transistors  208   i-m  are turned on can be different from the time the switching transistors  208   a-h  are turned ON. As a result, during this first phase, the transistors  208  are driven through their saturation region relatively slowly to limit the rate at which the current drawn by the branch circuits  200   a-m  increases. After the transistors  208  have been driven through their saturation region, the Q and QL signals enter the second turn-on phase. During this phase, the Q and QL signals increase at a more rapid rate because of he PMOS transistor  166  turning ON, thereby more rapidly turning ON the transistors  208 . Slightly delayed, the rapid increase of the Q 2  and QL 2  signals quickly turns ON the transistors  210 . 
     When the MUXI signal transitions low, the shunting of the Q, Q 2 , QL and QL 2  signals by the NMOS transistors  182   a,b  quickly drive the transistors  208 ,  210  to near their saturation operating region during the first turn-off phase. The Q, Q 2 , QL and QL 2  signals continue to decrease during the second turn-off phase, as previously explained. It is during this second turn-off phase when the transistors  208 ,  210  are being driven from linear to saturation region that the current can decrease too rapidly if the Q, Q 2 , QL and QL 2  signals driving them decrease too rapidly. However, when the transistors  208 ,  210  reach toward the lower part of their saturation operating region, they may be turned OFF at a more rapid rate without excessively increasing the rate at which the current draw changes. Consequently, during this third turn-off phase the Q 2  and QL 2  signals are shunted to ground by the NMOS transistor  194 , as explained above. The driver circuit embodiment shown in FIGS. 7 and 8 thus alters the rate at which the current draw increases and decreases during each transition to maximize the switching speed of the driver circuit without unduly increasing the rate at which the current draw changes. 
     The switched current signal produced by the open drain driver circuit of FIGS. 7 and 8 is shown in FIG.  9 . As shown therein,  4  switched current signals I 1 , I 2 , I 3 , I 4  are generated responsive to respective transitions of the Q, Q 2 , QL and QL 2  signals. During each transition of the switched current signals I 1 , I 2 , I 3 , I 4 , respective voltages induced by the changes in current are generated, as indicated by the signals I 1 ′, I 2 ′, I 3 ′, I 4 ′. Also shown is a composite signal I c  resulting from a combination of the signals I 1 ′, I 2 ′, I 3 ′, I 4 ′. The amplitude of this signal I C  is relatively low because the rate of change of each of the switched current signals is controlled during their transitions, as explained above. 
     A computer using a plurality of memory devices each containing several of the open drain driver circuits of FIGS. 7 and 8 is shown in FIG.  10 . The computer system  300  includes a processor  302  for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor  302  includes a processor bus  304  that normally includes an address bus, a control bus, and a data bus. The computer system  300  also includes a memory controller  330  or similar device, such as a system controller, coupled to an expansion bus  332 , such a Peripheral Component Interconnect (“PCI”) bus. The expansion bus  332  is coupled to one or more input devices  314 , such as a keyboard or a mouse, to allow an operator to interface with the computer system  300 . Typically, the computer system  300  also includes one or more output devices  316  coupled to the processor  302 , through the expansion bus  332 , memory controller  330  and processor bus  304 . Typical output devices are a printer and a video terminal. One or more data storage devices  318  are also typically coupled to the processor  302  to allow the processor  302  to store data in or retrieve data from internal or external storage media (not shown). Examples of typical storage devices  318  include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). The processor  302  is also typically coupled to cache memory  326 , which is usually static random access memory (“SRAM”) 
     The computer system  300  also includes a plurality of memory devices  340   a,b . . . n  coupled to the memory controller  330  through a bus system  344 . The bus system  344  may include a control bus, an address bus, and a data bus, or some other type of bus system. Regardless of which bus system  344  is used in the computer system  300 , the bus system  344  includes a plurality of signal conductors (not shown in FIG.  10 ), at least some of which are formed by respective transmission lines. Preferably transmission lines are used for at least the bus lines used to couple data between the memory devices  340   a,b . . . n  and the memory controller  330 . Each of the memory devices  340   a,b . . . n  includes an open drain driver circuit, such as the embodiment of FIGS. 7 and 8, coupled to each transmission line. The bus system  344  is thus able to couple data between the memory controller and each of the memory devices  340   a,b . . . n  at optimum speed regardless of whether memory devices  340   a,b . . . n  are added to or removed from the computer system  300 . The use of an open drain driver in accordance with an embodiment of the invention minimizes voltage transients induced in power supply lines  350  applying power to the memory devices  340   a,b . . . n  responsive to transitions in switched current signals generated by the open drain driver circuits in either the memory controller  330  or the memory devices  340   a,b . . . n.    
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.