Abstract:
A pseudo pipeline including a plurality of pseudo pipeline stages and a control circuit. The control circuit may be configured to control the plurality of pseudo pipeline stages to provide pseudo pipelined operation.

Description:
This application claims the benefit of U.S. Provisional Application No. 60/732,684, filed Nov. 1, 2005 and is hereby incorporated by reference in its entirety. 

   FIELD OF THE INVENTION 
   The present invention relates to memory controllers generally and, more particularly, to a pseudo pipeline and pseudo pipelined synchronous dynamic random access memory (SDRAM) controller. 
   BACKGROUND OF THE INVENTION 
   Data and control pipelines are common in digital electronics. Earlier SDRAM controllers using a pipelined approach failed. Variable delays between different stages of SDRAM transactions proved to be extremely difficult to accommodate. The addition of page mode transactions was even worse. Page mode transactions skipped some stages entirely. Static random access memory (SRAM) transactions failed completely. The SRAM transactions used all the stages in parallel, instead of sequentially like the SDRAM transactions. 
   It would be desirable to have a SDRAM controller that accommodates SDRAM and SRAM transactions. 
   SUMMARY OF THE INVENTION 
   The present invention concerns a memory controller including a plurality of pseudo pipeline stages and a control circuit. The control circuit may be configured to control the plurality of pseudo pipeline stages to provide pseudo pipelined operation. 
   The objects, features and advantages of the present invention include providing a pseudo pipeline that may (i) be used to implement a pseudo pipelined synchronous dynamic random access memory (SDRAM) controller, (ii) be used to manage a program counter (PC) of a central processing unit (CPU), (iii) transcend limitations of conventional pipelines, (iv) allow operations to flow through a pseudo pipeline with few restrictions, (v) allow operations to flow with variable delay, (vi) allow operations to skip stages of the pseudo pipeline, (vii) allow operations to use multiple stages of the pseudo pipeline simultaneously and/or (viii) allow operations to flow backwards. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
       FIG. 1  is a block diagram illustrating an application processor architecture including a memory controller in accordance with the present invention; 
       FIG. 2  is a block diagram illustrating a pseudo pipeline in accordance with preferred embodiments of the present invention; 
       FIG. 3  is a block diagram illustrating a crossbar style pseudo pipeline; 
       FIG. 4  is a block diagram illustrating an example implementation of a pseudo pipeline; 
       FIG. 5  is a block diagram illustrating details of an internal register file of the pseudo pipeline of  FIG. 4 ; 
       FIG. 6  is a block diagram illustrating controlling a front end logic using the pseudo pipeline of  FIG. 4 ; and 
       FIG. 7  is a block diagram illustrating another example implementation of a pseudo pipeline. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Referring to  FIG. 1 , a block diagram is shown illustrating an application processor architecture  100 . The architecture  100  may be used by system designers to cost-effectively design System-on-Chips (SoC). The architecture  100  may comprise a memory controller  102 , an interrupt controller  104 , an AHB-to-AHB bridge  106 , a bus matrix block  108 , an AHB bus  110 , an AHB-to-APB bridge  112 , APB bus  114 , a timer block  116 , a watchdog timer (WDT)  118 , a real time clock (RTC)  120 , a power management unit (PMU)  122 , a general purpose input/output (GPIO) block  124 , a UART  126 , an I2C block  128  and a keyboard interface  130 . The memory controller  102  may be implemented, in one example, as a multi-ported synchronous dynamic random access memory (SDRAM) controller. In one example, the memory controller  102  may be implemented with 12 ports. The interrupt controller  104  may be implemented, in one example, as a 32-channel interrupt controller. The timer block  116  may be implemented, in one example, as a number of 16-bit timers. 
   In one example, the memory controller  102  may be implemented as a pseudo pipelined SDRAM controller. The memory controller  102  may comprise, in one example, a pseudo pipeline implemented in accordance with preferred embodiments of the present invention. In one example, a first number of AHB master modules may be coupled directly to the memory controller  102  and a second number of AHB master modules may be coupled to the memory controller  102  through the bus matrix  108 . The memory controller  102  may be coupled to any of a synchronous dynamic random access memory (SDRAM), a static random access memory (SRAM) and/or a programmable read only memory (PROM). The present invention may be applicable also to Double Data Rate (DDR and DDR2) SDRAM. 
   The AHB bus  110  may be coupled directly to the interrupt controller  104  and the AHB-to-AHB bridge  106 . A number of AHB slave modules may be coupled to the AHB bus  110 . The AHB bus  110  may be coupled to the APB bus  114  via the AHB-to-APB bridge  112 . The APB bus  114  may be coupled to each of the blocks  116 - 130 . A number of APB expansion modules may be connected to the APB bus  114 . 
   Referring to  FIG. 2 , a block diagram is shown illustrating a pseudo pipeline  150  implemented in accordance with preferred embodiments of the present invention. The pseudo pipeline  150  may comprise a block (or circuit)  152  and a block (or circuit)  154 . The block  152  may be implemented as a multi-port register file. The block  154  may be implemented as a control block. The register file  152  may comprise a number of pseudo pipeline stages (e.g., STAGE  1 -STAGE N). In contrast to a conventional pipeline, the pseudo pipeline  150  may be implemented with no fixed relationship between pseudo pipeline stages. For example, operation of one pseudo pipeline stage with respect to a previous stage may proceed after 0 to N clock cycles. The variable delay between stages may allow the pseudo pipeline  150  to optimally accommodate SDRAM or SRAM timing. The depth (or number of registers) implemented in the register file  152  is generally determined by the number of transactions that may be active simultaneously. 
   The control circuit  154  may comprise a number of pointers  156   a - 156   n . In one example, the pointer  156   a  may be implemented as a write pointer and the pointers  156   b - 156   n  may be implemented as read pointers. In one example, a signal (e.g., DATA_IN) may be written into a first port of the register file  152  using a first address (e.g., AD_ 0 ) provided by the write pointer  156   a . Read data (e.g., signals RD_ 1 -RD_N) for each of the stages  1 -N may be accessed using addresses (e.g., AD_ 1  to AD_N) provided by the read pointers  156   b - 156   n . However, more complex pseudo pipelines may be implemented with additional write ports and/or read ports. 
   Operation of a conventional 4-stage pipeline is generally illustrated in the following TABLE 1: 
                                                                                                       TABLE 1                           TIME:                t + 1   t + 2   t + 3   t + 4   t + 5   t + 6   t + 7   t + 8                        Stage 1   1   2   3   4   5   5               Stage 2       1   2   3   4   4   5       Stage 3           1   2   3   3   4   5       Stage 4               1   2       3   4                    
Transactions  1  and  2  flow smoothly through the pipeline stages. Transaction  3  stalls at time t+5. The stall of transaction  3  creates a pipeline bubble in stage  4  at time t+6. Transactions  4  and  5  also stall at time t+5 to avoid overrunning.
 
   An operation of a 4-stage pseudo pipeline in accordance with the present invention is generally illustrated in the following TABLE 2: 
                                                                                                       TABLE 2                           TIME:                t + 1   t + 2   t + 3   t + 4   t + 5   t + 6   t + 7   t +8                        Stage 1   T1   T2   T3                           Stage 2   T1           T3   T2   T2   T2       Stage 3   T1       T2       T3       Stage 4   T1                   T3                    
In contrast to the conventional pipeline, a pseudo pipeline implemented in accordance with the present invention allows a transaction, for example, to use all of the stages simultaneously (e.g., transaction T 1 ). A pseudo pipeline implemented in accordance with the present invention also allows a transaction to flow through the pseudo pipeline similarly to the flow of transactions through a conventional pipeline (e.g., transaction T 3 ). In another example, a transaction T 2  generally demonstrates the flexibility of a pseudo pipeline implemented in accordance with the present invention. For example, at time t+2, T 2  skips Stage  2 . At time t+3, T 2  flows backward with a variable delay of 2 cycles. From t+5 to t+7, T 2  uses Stage  2  multiple times, eventually completing after T 3 .
 
   Referring to  FIG. 3 , a block diagram is shown illustrating a cross bar style implementation of the pseudo pipeline of  FIG. 2 . In one example, the register file  152  may comprise a block (or circuit)  160 , a number of blocks (or circuits)  162   a - 162   n  and a number of blocks (or circuits)  164   a - 164   n . The block  160  may be implemented as a write control block. The blocks  162   a - 162   n  may be implemented, in one example, as registers. The blocks  164   a - 164   n  may be implemented, in one example, as multiplexer blocks (or circuits). The block  160  may have an input that may receive the signal AD_ 0  and a number of outputs that may present a respective control signal (e.g., C 1 -Cn) to a corresponding first input of each of the number of blocks  162   a - 162   n . The block  160  may be configured to generate the signals C 1 -Cn in response to the signal AD_ 0 . In one example, each of the signals C 1 -Cn may be asserted (or active) in response to the signal AD_ 0  having values 0 through n−1 respectively. 
   Each of the blocks  162   a - 162   n  may have a second input that may receive the signal DATA_IN and an output that may present a signal to a corresponding data input of each of the blocks  164   a - 164   n . Each of the blocks  164   a - 164   n  may have an address input that may receive a respective one of the signals AD_ 1  to AD_N. Each of the blocks  164   a - 164   n  may have an output that may present a respective one of the signals RD_ 1 -RD_N. The number of data registers  162   a - 162   n  may be determined by the number of transactions that may be active simultaneously. The read data for each stage may be selected by the multiplexer blocks  164   a - 164   n . In one example, the multiplexer blocks  164   a - 164   n  may be arranged as a crossbar switch. Although the example illustrated in  FIG. 3  shows a full crossbar, implementations with partially connected crossbars may be implemented with less circuitry to meet the design criteria of particular applications. 
   Referring to  FIG. 4 , a block diagram is shown illustrating an example implementation of a pseudo pipeline  180  in accordance with the present invention. In one example, the pseudo pipeline  180  may be implemented as part of the memory controller  102 . The pseudo pipeline  180  may be implemented, in the context of a pseudo pipelined memory controller, having a precharge stage, a row access stage, a column access and write data stage, and a read data stage. The precharge stage may be used to start all of the transactions. 
   The pseudo pipeline  180  may comprise a block (or circuit)  182  and a block (or circuit)  184 . The block  182  may be implemented as a control circuit. The block  184  may be implemented as a register file. The control circuit  182  may be configured to generate a number of control signals (e.g., N_PRE, N_ROW, N_COL, and N_RD). The signals N_PRE, N_ROW, N_COL, and N_RD specify the transaction number of the transaction in the precharge, row access, column access and read data stages, respectively. The register file  184  may have (i) a first input that may receive a signal (e.g., MAS_NEW), (ii) a number of second inputs that may receive the signals N_PRE, N_ROW, N_COL and N_RD and (iii) a number of outputs that may present a number of output signals (e.g., MAS_ROW, MAS_COL, and MAS_RD). The block  184  may be configured to generate the signal MAS_ROW, MAS_COL, and MAS_RD in response to the signals MAS_NEW, N_PRE, N_ROW, N_COL and N_RD. 
   At the end of the precharge stage, a value (e.g., MAS_NEW) representing a master module selected by the memory controller  102  may be written into the register file using a pointer AD_ 0 . At the beginning of the other stages, the value representing the master may be read from the register file  184 . 
   In one example, the block  182  may comprise a number (e.g., four) of counters  186   a - 186   n . In one example, the counters  186   a - 186   n  may be implemented as 2-bit counters. However, other size counters may be implemented accordingly to meet the design criteria of a particular implementation. The counters  186   a - 186   n  may be configured to address the data for each of the pseudo pipeline stages. In one example, transactions may be processed in order within each pseudo pipeline stage. When a transaction completes a stage, the counter corresponding to the stage may be incremented. 
   An example operation of the counters  186   a - 186   n  implemented as 2-bit counters is illustrated in the following TABLE 3: 
                                                                                                       TABLE 3                           TIME:                t + 0   t + 1   t + 2   t + 3   t + 4   t + 5   t + 6   t + 7                        COUNTER 1   0   1   2   3   0   0   0   0       COUNTER 2   0   0   1   2   3   0   0   0       COUNTER 3   0   0   0   1   2   3   0   0       COUNTER N   0   0   0   0   1   2   3   0                    
At time t+0, all the counters  186   a - 186   n  are initialized to zero. The counters  186   a - 186   n  are incremented so that transactions  1 ,  2  and  3  (corresponding to count values 1, 2 and 3 respectively) flow through the pseudo pipeline in a manner similar to a conventional pipeline. When transaction  3  completes at time t+6, transaction  4  (corresponding to count value 0) is left active in all stages simultaneously.
 
   Different pseudo pipeline operations may be performed (or implemented) by specifying the increment values for the individual counters  186   a - 186   n . Example increment values and corresponding operations are illustrated in the following TABLE 4: 
                                 TABLE 4               INCREMENT   OPERATION                                −1   Backward flow       0   Repeat stage       1   Conventional forward flow       2   Skip one stage                    
A variable delay operation may occur when two counters are incremented such that a transaction completes in one stage before starting in a second stage. Other increment values may be implemented accordingly to meet the design criteria of a particular implementation.
 
   Referring to  FIG. 5 , a block diagram is shown illustrating internal details of the register file  184  of  FIG. 4 . The register file  184  may comprise, in one example, a block (or circuit)  190 , a number of blocks (or circuits)  192   a - 192   n  and a number of blocks (or circuits)  194   a - 194   n . The block  190  may be implemented, in one example, as a write control block. Each of the blocks  192   a - 192   n  may be implemented, in one example, as a data register. Each of the blocks  194   a - 194   n  may be implemented, in one example, as a multiplexer circuit. The block  190  may have an input that may receive the signal N_PRE and a number of outputs that may present a respective control signal (e.g., C 1 -Cn) to a corresponding first input of each of the blocks  192   a - 192   n . The block  190  may be configured to generate the signals C 1 -Cn in response to the signal N_PRE. In one example, each of the signals C 1 -Cn may be asserted (or active) in response to the signal N_PRE having values 0 through n−1 respectively. 
   Each of the blocks  192   a - 192   n  may have a second input that may receive the signal MAS_NEW and an output that may present a signal to a corresponding data input of each of the blocks  194   a - 194   n . Each of the blocks  194   a - 194   n  may have an address input that may receive a respective one of the signals N_ROW, N_COL and N_RD. Each of the blocks  194   a - 194   n  may have an output that may present a respective one of the signals MAS_ROW, MAS_COL and MAS_RD. The number of data registers  192   a - 192   n  may be determined by the number of transactions that may be active simultaneously. The read data for each stage may be selected by the multiplexer blocks  194   a - 194   n . In one example, the multiplexer blocks  194   a - 194   n  may be arranged as a crossbar switch. Timing and flow examples for transactions using the pseudo pipeline  180  are generally illustrated in TABLES 3 though 7 below. 
   A number of SRAM transactions using a pseudo pipeline in accordance with the present invention are illustrated in the following TABLE 5: 
                                                                                                       TABLE 5                           TIME:                t + 1   t + 2   t + 3   t + 4   t + 5   t + 6   t + 7   t + 8                        Precharge   1       2       3                   Row                   3       Col/Write   1               3       Read           2       3                    
Operation of SRAM transactions is not generally pipelined. All stages/resources are generally used in parallel, rather than sequentially. For example, transaction  1  generally illustrates an SRAM write. Transaction  2  generally illustrates an SRAM read. In practice, all SRAM transactions operate similarly to Transaction  3  with some of the pseudo pipeline stages not used.
 
   A page mode write operation and a page mode read operation using a pseudo pipeline in accordance with the present invention are illustrated in the following TABLES 6 and 7, respectively: 
   
     
       
             
             
           
             
             
             
             
             
             
             
             
             
           
             
             
             
             
             
             
             
             
             
           
         
             
                 
               TABLE 6 
             
           
           
             
                 
                 
             
             
                 
               TIME: 
             
           
        
         
             
                 
               t + 1 
               t + 2 
               t + 3 
               t + 4 
               t + 5 
               t + 6 
               t + 7 
               t + 8 
             
             
                 
                 
             
           
        
         
             
               Precharge 
               1 
                 
                 
                 
                 
                 
                 
                 
             
             
               Row 
             
             
               Col/Write 
               1 
                 
               1 
                 
               1 
                 
               1 
             
             
               Read 
             
             
                 
             
           
        
       
     
   
                                                                                                       TABLE 7                           TIME:                t + 1   t + 2   t + 3   t + 4   t + 5   t + 6   t + 7   t + 8                        Precharge   1                                   Row       Col/Write   1       1       1       1       Read               1   1   1   1   1                    
Page mode transactions generally do not perform a precharge or row access. For burst transactions, the column access may be repeated every 2 cycles. Write data may be transferred on the column access and the immediately following cycle. Read data may be transferred after a 3 cycle CAS (column address strobe) latency and on the immediately following cycle.
 
   In general, all SDRAM transactions may overlap with only a few restrictions. For example, column access for different transactions may not overlap, data for different transactions may not overlap and a turn around cycle is generally inserted between read and write data. 
   Random write and random read transactions using a pseudo pipeline in accordance with the present invention are generally illustrated in the following TABLES 8 and 9, respectively. 
   
     
       
             
             
           
             
             
             
             
             
             
             
             
             
             
             
             
             
             
           
             
             
             
             
             
             
             
             
             
             
             
             
             
             
           
         
             
                 
               TABLE 8 
             
           
           
             
                 
                 
             
             
                 
               TIME: 
             
           
        
         
             
                 
               t + 1 
               t + 2 
               t + 3 
               t + 4 
               t + 5 
               t + 6 
               t + 7 
               t + 8 
               t + 9 
               t + 10 
               t + 11 
               t + 12 
               t + 13 
             
             
                 
                 
             
           
        
         
             
               Pre 
               1 
                 
                 
                 
                 
                 
                 
                 
                 
                 
                 
                 
                 
             
             
               Row 
                 
                 
                 
               1 
             
             
               Col/ 
                 
                 
                 
                 
                 
                 
               1 
                 
               1 
                 
               1 
                 
               1 
             
             
               Write 
             
             
               Read 
             
             
                 
             
           
        
       
     
   
                                                                                                                                               TABLE 9                           TIME:                t +       t +       t +   t +   t +   t +   t +   t +   t +   t +   t +           1   t + 2   3   t + 4   5   6   7   8   9   10   11   12   13                        Pre   1                                                       Row               1       Col/                           1       1       1       1       Write       Read                                       1   1   1   1                    
Random transactions may start by precharging the addressed SDRAM bank. After a 3 cycle precharge to RAS (row address strobe) latency, a row activate may be performed. After a 3 cycle RAS to CAS delay, random access transactions may operate similarly to page mode transactions (described above in connection with TABLES 6 and 7).
 
   Referring to  FIG. 6 , a block diagram is shown illustrating an example of a front end logic  200  of the memory controller  102 . The pseudo pipeline  180  may be configured to control the front end logic  200 . In one example, the front end logic  200  may comprise a block (or circuit)  202 , a block (or circuit)  204 , a block (or circuit)  206  and a block (or circuit)  208 . In one example, the blocks  202 - 208  may be implemented as multiplexers. The multiplexer  202  may have a first input that may receive the signal MAS_NEW, a second input that may receive the signal MAS_ROW, a third input that may receive the signal MAS_COL and a control input that may receive a control signal (e.g., MAS_SEL). The multiplexer  202  may have an output that may present an output signal (e.g., MAS_NUM). The signal MAS_NUM generally represents a number of an active master for a current SDRAM cycle. The signal MAS_SEL generally selects the master that requested the transaction that includes the current SDRAM command. The multiplexer  202  may be configured to select one of the signals MAS_NEW, MAS_ROW and MAS_COL for presentation as the signal MAS_NUM. 
   The signal MAS_NUM may be presented to a control input of the multiplexer  204 . The multiplexer  204  may have a number of inputs that may receive a number of address signals (e.g., ADDR_ 0  . . . ADDR_ 11 ) and control signals (e.g., CONTROL_ 0  . . . CONTROL_ 11 ). The multiplexer  204  may be configured to select the address and control signals from a corresponding input for presentation at an output in response to the signal MAS_NUM. 
   The signal MAS_COL may be presented to a control input of the multiplexer  206 . The multiplexer  206  may be used during write cycles. The multiplexer  206  may be configured to select from a number of write data inputs (e.g., WR_DATA_ 0  . . . WR_DATA_ 11 ) and a number of inputs receiving signals indicating a type for the current transfer (e.g., HTRANS_ 0  . . . HTRANS_ 11 ) for presentation as write transaction signals (e.g. WR_DATA, WR_HTRANS) in response to the signal MAS_COL. In one example, the signals HTRANS_ 0  . . . HTRANS_ 11  may be implemented as unregistered HTRANS bits. In one example, the signals HTRANS_ 0  . . . HTRANS_ 11  may be implemented in compliance with the Advanced Microcontroller Bus Architecture (AMBA) specification (AMBA is a trademark of ARM limited). When the signals HTRANS_ 0  . . . HTRANS_ 11  are implemented in compliance with the AMBA specification, the signals HTRANS_ 0  . . . HTRANS_ 11  may have values indicating whether transfers are nonsequential, sequential, idle or busy. 
   The signal MAS_RD may be presented to a control input of the multiplexer  208 . The multiplexer  208  may be used during read cycles. The multiplexer  208  may be configured to select one of the signals HTRANS_ 0  . . . HTRANS_ 11  for presentation, as a read transaction signal (e.g., RD_TRANS). For example, the multiplexer  208  may select one of the signals HTRANS_ 0  . . . HTRANS_ 11  for presentation as the signal RD_TRANS in response to the signal MAS_RD. 
   The front end logic may include, in one example, an h_ready logic. In one example, the h_ready logic may be configured to indicate a status of a transfer. In one example, the h_ready logic may be implemented as a simple demultiplexing circuit configured to return a signal (e.g., H_READY) to the correct master during read and write cycles. In one example, the signal H_READY may have a first state that may indicate a transfer is complete and a second state that may indicate a transfer is extended. An example of an h_ready logic may be described using Verilog as follows:
         assign H_READY=({12{H_READY_WR}} &amp; (12′b1&lt;&lt;MAS_COL)|({12{H_READY_RD}} &amp; (12′b1&lt;&lt;MAS_RD));       

   Referring to  FIG. 7 , a block diagram is shown illustrating a pseudo pipeline  220  in accordance with the present invention. The pseudo pipeline  220  may be configured to manage a program counter (PC) of a central processing unit (CPU) with a conventional pipeline. The PC value for each instruction may be entered into a first stage of the pseudo pipeline  220 . The PC value may be used in several different stages depending on an instruction being processed. For example, the PC value may be used in an early stage by a PC relative branch instruction, a middle stage by a PC relative load instruction, or saved in a final stage if an instruction encountered an exception. 
   In one example, the pseudo pipeline  220  may be configured to implement an initial stage, a fetch stage, a decode stage, an arithmetic logic unit (ALU) stage, a memory stage, and an exception stage. The pseudo pipeline  220  may comprise a block (or circuit)  222  and a block (or circuit)  224 . The block  222  may be implemented as a control circuit. The block  224  may be implemented as a register file. In one example, the block  224  may be implemented similarly to the block  152  (described above in connection with  FIG. 3 . 
   The block  222  may be configured to generate a number of control signals (e.g., N_PC, N_FETCH, N_DECODE, N_ALU, N_MEMORY, and N_EXCEPTION). The control signals N_PC, N_FETCH, N_DECODE, N_ALU, N_MEMORY, and N_EXCEPTION may specify transaction numbers for various stages of the processor pipeline. The block  224  may have (i) a first input that may receive a signal (e.g., PC), (ii) a number of second inputs that may receive the control signals N_PC, N_FETCH, N_DECODE, N_ALU, N_MEMORY, and N_EXCEPTION and (iii) a number of outputs that may present output signals (e.g., FETCH_PC, DECODE_PC, ALU_PC, MEMORY_PC, EXCEPTION_PC). The signal PC may comprise a value of the program counter of the CPU. The block  224  may be configured to generate the signals FETCH_PC, DECODE_PC, ALU_PC, MEMORY_PC, EXCEPTION_PC in response to the signal PC and the control signals N_PC, N_FETCH, N_DECODE, N_ALU, N_MEMORY, and N_EXCEPTION. 
   In one example, the block  222  may comprise a number of counters  226   a - 226   n . In one example, the counters  226   a - 226   n  may be implemented as n-bit counters, where the number of stages in the pseudo pipeline  220  is less than or equal to 2 n . However, other size counters may be implemented accordingly to meet the design criteria of a particular implementation. The counters  226   a - 226   n  may be configured to address the data for each of the pseudo pipeline stages. 
   The pseudo pipeline  220  in accordance with the present invention generally operates with lower power consumption than a conventional pipeline. In the pseudo pipeline  220  in accordance with the present invention, only a single register is clocked every cycle. In a conventional PC pipeline, all registers are clocked every cycle. 
   The various signals of the present invention are generally “on” (e.g., a digital HIGH, or 1) or “off” (e.g., a digital LOW, or 0). However, the particular polarities of the on (e.g., asserted) and off (e.g., de-asserted) states of the signals may be adjusted (e.g., reversed) to meet the design criteria of a particular implementation. Additionally, inverters may be added to change a particular polarity of the signals. 
   As used herein, the term “simultaneously” is meant to describe events that share some common time period but the term is not meant to be limited to events that begin at the same point in time, end at the same point in time, or have the same duration. 
   While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.