Abstract:
A variable rate correlation circuit for conserving power includes a variable clock source, a local PN source, and a correlator. The local PN source further includes a local generator and a resampler. The variable clock source provides a normal clock rate and a lower clock rate. The local generator supplies the local PN sequence at the normal clock rate. The resampler receives the local PN sequence sampled at the normal clock rate and outputs the local PN sequence sampled at the lower clock rate. The correlator receives the lower sampled local PN sequence, the received PN sequence, and the lower clock rate signal, correlating the received and local PN sequences at the lower clock rate to produce a. correlated result.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 60/092,374, entitled “A Variable Clock Rate Correlation Circuit and Method of Operation,” filed Jul. 10, 1998. 
     Further, the following applications are herein incorporated by reference in their entirety for all purposes: 
     “AN IMPROVED CDMA TRANSCEIVER AND FREQUENCY PLAN,” Ser. No. 09/113,603, filed Jul. 10, 1998; and 
     “AN IMPROVED CDMA RECEIVER AND METHOD OF OPERATION,” Ser. No. 09/113,791, filed Jul. 10, 1998. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to a correlation circuit, and more particularly, to a variable clock rate correlation circuit for use in a portable CDMA receiver. 
     Correlation circuits are commonly used in portable telecommunications receivers for identifying which transmission among many signals is intended for the particular receiver. The correlation circuit generates a locally generated signal and compares that local signal to the received signal. When the received signal and the locally generated signal have a high degree of correlation, the transmission is deemed to be intended for the receiver. When the resulting correlation is low, the transmission is deemed not intended for the receiver and discarded. The received and locally generated signals may be either analog signals, such as those used in FM telecommunications systems, or sequences of binary data in digital systems such as Code Division Multiple Access (CDMA) systems. 
     Correlation circuits are used throughout the receiver, including in the carrier lock loop and delay lock loop circuitry of the receiver. A carrier lock loop (CLL) is used to remove the carrier offset frequency and phase of the received signal. A delay lock loop (DLL) is used to maintain signal lock, i.e., maintain the alignment between the received and locally generated signals once the received signal has been acquired. 
     FIG. 1A illustrates a system block diagram of a carrier lock loop (CLL) for a digital CDMA receiver. The CLL includes a complex multiplier  102 , a correlation circuit  103 , an arc-Tangent look up table (ATAN LUT)  104 , a loop filter  105 , and a numerically controlled oscillator (NCO)  106 . Using a CDMA receiver front end (not shown), a CDMA signal is received and downconverted to baseband I and Q data sequences  101   a  and  101   b.    
     The I and Q data sequences  101   a  and  101   b  are supplied to the complex multiplier  102  with complex multipliers sin(Φ)  106   a  and cos(Φ)  106   b . The complex multipliers  106   a  and  106   b  operate to remove the carrier frequency and phase offset from the carrier signal. The I and Q data sequences  102   a  and  102   b  are correlated with locally generated sequences (not shown), producing complex phase error components cos(Φ)′  101   a  and sin (Φ)′  103   b . The complex phase error components  103   a  and  103   b  are supplied to an Arc-tangent look-up table  104 , which produces a phase error signal  105   a . The phase error signal  104   a  is a measure of how closely aligned the received I and Q data carrier offset phase is to the locally generated phase (Φ). The phase error will be minimum when the received carrier phase and Φ are aligned. A loop filter  105  removes any spurious out-of-band signal components from the phase error signal  103   a . The phase error signal is supplied to a numerically controlled oscillator (NCO)  106 , which in response produces an improved set of complex multipliers  106   a  and  106   b.    
     Once the received sequence is matched to the local PN sequence, the alignment between the two sequences must be closely maintained. FIG. 1B illustrates a block diagram of a delay lock loop for dynamically maintaining alignment between the received and local PN sequences once the two sequences are within a predefined range. The delay lock loop  100  includes correlators  110   a-c , filters  120   a-c , an adder  122 , a loop filter  132 , a voltage controlled oscillator (VCO)  134 , and a local pseudo-normal (P-N) code generator  136 . A received chip sequence  102  is concurrently supplied to correlators  110   a-c . The PN generator  136  generates a three local PN sequences  104   a-c . The first local PN sequence  104   a  is punctual with the received PN sequence  102 . The correlator  110   a  produces the response shown in FIG.  1 C. 
     When the alignment between the received PN sequence and the Local PN sequence are varied from −T to T, the second local PN sequence  104   b  is late with respect to the received PN sequence  102 , thereby generating the output response  125  shown in FIG.  1 D. The third local PN sequence  104 c is early with respect to the received PN sequence  102  generating an output response  125   c  which is shown in FIG.  1 E. The early and late versions of the received and locally generated sequences are typically used in the correlation circuits, as shown below. 
     An adder  122  is used to sum a negated version of the late response with the early response to generate an error signal  130 , shown in FIG.  1 F. As shown in FIG. 1F, the error signal  130  has a linear voltage level versus time response over the correlation period ±T/2. Once the locally generated and received sequences are within this range, the DLL dynamically realigns them until the error signal  130  reaches zero, indicating perfect alignment between the two. 
     A loop filter  132  removes spurious noise from the error signal  130  which may occur during the correlation process. The filtered error signal is supplied to the VCO  134 , which generates a tone corresponding to the error signal  130 . The local PN generator  136  receives the VCO tone, and in response, adjusts the timing of its internally generated local PN sequences  104   a-c , either advancing or delaying the local PN sequences  104   a-c  according to error signal response of FIG.  1 F. The adjusted local PN sequences  104   a-c  are then output to the correlators  110   a-c  to obtain a higher degree of correlation with the received PN sequence. 
     Correlation circuits consume power primarily as a function of its operating speed or correlation rate. A correlation circuit operating at a high clock rate consumes more power than the correlation circuit operating at a lower clock rate. 
     In conventional receiver circuitry such as the aforementioned CLL and DLL, the correlation rate is maintained at a constant clock rate, typically many times higher than the chip rate of the received signal or sequence. The cumulative effect of a large number of correlation circuits operating at a relatively high clock rate results in a significant consumption of power. In light of the limited power supply available to portable cellular telephones, the present method of operating the correlation circuits become very disadvantageous. 
     What is needed is a new correlation circuit and method of operation which allows a reduction in the clock rate and accordingly, a decrease in power consumption. 
     SUMMARY OF THE INVENTION 
     The present invention provides for a variable clock rate correlation circuit which conserves power by operating at two different clock rates. During initial signal acquisition, the variable clock rate correlation circuit operates at a high clock rate, 2 or more times the chip rate to correlate the received and locally generated sequences for a possible match. Once the received and local generated sequences exhibit a high degree of correlation, the relative positioning of the received and locally generated sequences is known to a large degree. The variable clock rate correlation circuit then switches to a lower clock rate, less than twice the chip rate, reducing the amount of power it consumes, while maintaining a high degree of time alignment accuracy. 
     In one embodiment, the correlation circuit includes a variable clock source, a local PN source, and a correlator. The local PN source further includes a local generator and a resampler. The variable clock source provides a normal clock rate and a lower clock rate. The local generator supplies the local PN sequence at the normal clock rate. The resampler receives the local PN sequence sampled at the normal clock rate and outputs the local PN sequence sampled at the lower clock rate. The correlator receives the lower sampled local PN sequence, the received PN sequence, and the lower clock rate signal, correlating the received and local PN sequences at the lower clock rate to produce a correlated result. 
    
    
     A further understanding of the nature and advantage of the invention herein may be realized by reference to the remaining portions of the specification and attached drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A illustrates a known circuit architecture for a carrier lock loop for a digital CDMA receiver. 
     FIG. 1B illustrates known circuit architecture for a CDMA Delay Lock Loop. 
     FIGS. 1C-1F illustrate the response of the CDMA delay lock loop shown in FIG.  1 B. 
     FIG. 2 illustrates a flowchart describing the operation of the variable clock rate correlation circuit in accordance with the present invention. 
     FIG. 3 illustrates an exemplary embodiment of the variable clock rate correlation circuit in accordance with the present invention. 
     FIG. 4 illustrates a timing diagram useful in understanding the operation of the LPN resampler. 
     FIG. 5 illustrates an exemplary embodiment of the LPN resampler in accordance with the present invention 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 2 illustrates a flow chart describing the operation of the variable clock rate correlation circuit in accordance with the present invention. During start-up  205  or any other period when a prior correlation between a received and a locally generated PN sequence has not occurred, the correlation circuit initially operates in an acquisition mode. During acquisition mode operation, a local PN generator generates a local PN sequence which is sampled at a high clock rate compared to the received PN sequence (step  210 ). In the preferred embodiment, the local PN sequence is sampled at 4x the chip rate of the received PN sequence. Once sampled, the local PN sequence and the received PN sequence are supplied to a correlator. The correlator correlates the two sequences at a high clock rate, preferably at the 4 times (“4x”) the chip rate used in sampling the local PN sequence (step  215 ). If the resulting cross-correlation product indicates that the received and local PN sequences are not within the ±T/2 correlation range shown in FIG. 1B, the correlation circuit operates in the acquisition mode again as described above, performing steps  205  and  215 . 
     If the cross-correlation product indicates that the local and received sequences are within the ±T/2 correlation range, the two sequences can be aligned and the correlation circuit switches to a locked signal mode of operation. In the locked signal mode, the positioning of the received sequence is known to a large degree, i.e., within ±1/2 of a chip period. Consequently, the correlation between the received and local sequences can occur at a reduced clock rate with little or no error resulting therefrom. When the correlation circuit operates in the locked signal mode, the correlation clock rate is reduced, preferably from the 4x chip rate during the acquisition mode to (32/31)x chip rate during the locked mode. 
     When the correlation circuit operates at the reduced clock rate, the local PN sequence must be resampled at the reduced clock rate in order for the correlation circuit to produce an accurate cross-correlation product. Accordingly, the local sequence is resampled at the reduced clock rate, preferably (32/31)x the chip rate of the received PN sequence (step  225 ). The resampled local sequence is correlated with the received sequence at the reduced clock rate producing a cross-correlation product (step  230 ). If the resulting cross-correlation product indicates alignment between the two sequences within a predefined range, the correlation circuit continues to operate in the locked signal mode during the subsequent sample period. If the cross-correlation product is outside of the predefined range, the correlation circuit switches to the signal acquisition mode, described above. 
     FIG. 3 illustrates one embodiment of the variable clock rate correlation circuit in accordance with the present invention. The correlation circuit includes a correlator  320 , a clock source  340 , and a local PN source  360 . 
     The correlator  320  includes a bitwise exclusive or (XOR) operator  321  having a first input  321   a  to receive the received PN chip sequence and a second input  321   b  to receive the local PN chip sequence. The received sequence is represented by an offset two&#39;s complement number, preferably of 10-bit length representing a value from −512 to +512. The XOR operator  321  performs a cross correlation upon the two sequences, producing a large cross-correlation product when the two sequences are aligned. The result of each correlation is summed by an adder  322 , and a running sum of previous correlations occurring within the same clock period is stored in register  323 . A counter  324  running at a clock rate CLK  349  counts down from N−1 to 0 at which time the terminal count signal  327  goes high, thereby activating register  326  to output the accumulated result over the N samples. 
     The CLK signal  349  is generated by a clock source  340 . The clock source  340  includes a voltage controlled oscillator (VCO)  342 , a divide-by- 31  circuit  344 , a counter  346 , and a sample mode select switch  348 . The VCO  342  provides a reference signal  343  to the counter  346  and the divide-by- 31  circuit  344 . In the preferred embodiment, the reference signal operates at a frequency of 32x the chip rate (1.2288 MHz), or 39.3216 MHz. The divide-by- 31  circuit  344  generates a beat clock signal  345  equal to (32/31)x chip rate, further discussed below. From the 32x reference frequency  343 , the counter  346  generates 1x, 2x, 4x, 8x, and 16x clock signals  347   a-e.    
     Responsive to a control signal  341 , a clock source switch  348  selects either the beat clock  345  or one of the counter rates  347   a-e  as the clock rate CLK used for the lo correlation rate. In the preferred embodiment, the beat clock rate is (32/31)x the chip rate and the 4x chip rate is used as the second input of the clock source switch  348 , although other clock rates may be used. 
     The local PN (LPN) source  360  includes a LPN is generator  361 , a LPN resampler  364 , a LPN signal delay  366 , and a LPN switch  368 . The LPN generator  361  receives a clock signal  361   a  and produces the local PN chip sequence  362 . The clock signal  361   a  is used to advance or delay the beginning of the local sequence  362  in fractional intervals of the clock rate, which in the preferred embodiment is 8x the chip rate. 
     The local sequence  362  is supplied to the LPN resampler  364  and to the LPN signal delay  366 . The LPN signal delay  366  operates as an N-period delay to compensate for the delay occurring in the LPN resampler  364 . The delayed sequence  367  is supplied to the LPN switch  368  for input into the correlator  320 , if selected by the LPN switch  368 . In the preferred embodiment, the delayed sequence  367  is selected for input into the correlator&#39;s LPN input  321   b  during operation in the signal acquisition mode. 
     The LPN resampler  364  also receives the local PN sequence  362 , a 1x chip rate clock signal  347   e , and the beat clock signal  345 . The 1x chip rate clock signal  347   e  is used to provide a reference clock signal to the resampler. The beat clock signal  345  is the reduced clock rate at which the local PN chip sequence  362  is resampled. In the lock signal mode, the LPN resampler  364  samples the local sequence at the reduced rate, (32/31)x chip rate in the preferred embodiment, producing a resampled local sequence  365 . The resampled local sequence  365  is routed to the correlator&#39;s LPN input  321   b  via the LPN switch  368 . In the signal acquisition mode, the delayed sequence  367  is supplied to the correlator&#39;s LPN input  321   b  via the LPN switch  368 . In an alternative embodiment, the LPN resampler may also include a bypass feature to route the local PN sequence  362  delayed by an appropriate time period to the LPN switch  368  during the signal acquisition mode, thereby obviating the need for the signal delay  366 . 
     FIG. 4 illustrates a timing diagram useful in understanding the operation of the LPN resampler  364 . A first pulse train  402  represents the rising edges of the 1x chip rate clock, the rate at which chips are generated within and output from the LPN generator  361 . For purposes of illustration, the first pulse train is shown as 1x the chip rate, but can be Nx the chip rate in other embodiments. 
     A second pulse train  404  represents the beat clock, which is shown for purposes of illustration as (10/9)x chip rate. This rate is derived from the master clock using a divide-by-9 function and is the reduced sampling rate at which the local PN sequence  362  is sampled and correlated with the received PN sequence once alignment between the received and local sequences is established. In the preferred embodiment, the beat clock is (32/31)x chip rate derived from the master clock (VCO)  342  and the divide-by-31 circuit  344  (FIG.  3 ). 
     The points at which the 1x chip rate pulse and the beat clock pulses simultaneously occur form boundary lines  430  and  440 . These boundary lines  430  and  440  define frames of the LPN chip sequences shown. A mid-frame boundary line  450  occurs at the center of each frame. 
     Correlation circuits operate using early and late versions of the local and received sequences. The early and late versions of each can be generated using a tapped delay line, described below. Chip sequences  406  and  408  are early and late versions of the local PN sequence  365  (FIG.  3 ), advanced or delayed by one half of a chip relative to punctual. 
     The early/late received PN chip sequences are shown as sequences  410  and  412 , respectively. The received sequences  410 / 412  are shown delayed in relation to the local sequences in FIG. 4, as described in greater detail below. 
     When the local and received sequences are perfectly aligned, the LPN resampler will produce a “resampled” local sequence which is identical to the received PN sequence  410 / 412 , but sampled at the beat clock rate  404  instead of the original clock rate  402 . The early/late versions of the resampled local sequence is shown as sequences  422 / 424 . The resampled local sequences  422 / 424  are then supplied to the correlator ( 320 , FIG.  3 ), and are correlated, at the beat clock rate, with early/late versions of the received PN sequence to ascertain the degree of correlation therebetween. By way of Example in FIG. 4, applying the beat clock  404  (F 2 ) to the early/late chip pairs of the received PN sequences  410 / 412  (E 2 ) produces the following chip pairs: ( 1 , 0 ), ( 2 , 1 ), ( 2 , 1 ), ( 3 , 2 ), ( 4 , 3 ), ( 5 , 4 ), ( 6 , 5 ), ( 7 , 6 ), ( 8 , 7 ), ( 0 , 8 ). The chip pair ( 2 , 1 ) would be selected twice since the second beat clock occurs at the transition point and in the preferred embodiment the next occurring chip pair is selected when the beat clock occurs at a transition point. 
     However, the local and received sequences may not be perfectly aligned. This is the case shown in FIG. 4 in which the local sequences  406 / 408  are misaligned (advanced) {fraction (3/10)} of a chip period with respect to the received sequences  410 / 412 . If the two sequences are correlated while misaligned, the resulting correlation cross product would be erroneous. The LPN resampler must therefore produce the aforementioned early/late chip pairs of the perfectly aligned local sequences  422  and  424  when sampled at the beat clock rate  404 . The LPN resampler accomplishes this by initially generating additional local PN sequences. The LPN resampler then selectively chooses chips from among the generated local PN sequences to reconstruct the aforementioned early/late chip pairs corresponding to the perfectly aligned early/late local PN sequences. 
     In the preferred embodiment, the LPN resampler generates two additional PN sequences; an earlier PN sequence  414  and a later PN sequence  420 . The earlier and later PN sequences  414  and  420  are advanced/delayed one chip compared to the early/late sequences  406  and  408 . The earlier, early, late, and later versions of the local PN sequences are preferably generated by means of a delay line tapped at appropriate points to provide the aforementioned chip offset. Additional PN sequences having the same or different chip offset periods may alternatively be used. 
     Once the four PN sequences are generated, the LPN resampler selectively chooses between the four PN sequences  414 ,  406 ,  408 , and  420  to yield the aforementioned early/late PN chip pairs corresponding to the perfectly aligned early/late local PN sequence. A multiplexer receives the earlier, early, late, and later PN sequences  414 ,  406 ,  408 , and  420 . The beat clock  404  activates the multiplexer at the beat clock rate. A mux control signal  426 , further described below, controls the selection of chip pairs from the four PN sequences  414 ,  406 ,  408 , and  420 . 
     During the first beat clock after the frame boundary  430 , the ( 1 , 0 ) chip pair is selected from the early/late PN sequences  406 / 408 . This selection is consistent with the aforementioned early/late chip pair of the perfectly aligned local PN sequences. During the second beat clock period, the ( 2 , 1 ) chip pair is selected again from the early and late PN sequences  406 / 408 . During the third beat period, the ( 2 , 1 ) chip pair from the late and later PN sequences  408 / 420  is selected. The selection is correct since the perfectly aligned local PN sequence also produces the redundant ( 2 , 1 ) early/late chip pair, as shown above. The ( 3 , 2 ) chip pair is selected from the late/later PN sequences  408 / 420  during the fourth beat period. 
     During the mid-frame period, (the 5th chip period in the exemplary embodiment of FIG.  4  and the 16th chip period in the preferred embodiment), two beat clock pulses  404   a  and  404   b  occur. During this period, the mux control signal  426  operates at 2x the chip rate to output two chip pairs ( 4 , 3 ) and ( 5 , 4 ) sampled by the beat clock. The two beat clock pulses  404   a  and  404   b  occur during the mid-frame period due to the beat clock&#39;s slight oversampling. To accurately reconstruct the perfectly aligned early/late PN sequence listed above, the ( 4 , 3 ) chip pair is selected as the first output and the ( 5 , 4 ) chip pair is selected as the second output during this period. The chip selection process continues as previously described. In this manner, the resampled early/late local PN sequences  422 / 424  are constructed having chip pairs which match the chip pairs of the perfectly aligned early/late local PN sequences, described above. 
     FIG. 5 illustrates one embodiment of the LPN resampler  364 . The LPN resampler  364  includes a tapped delay line  510  for providing the four local PN sequences  414 ,  406 ,  408 , and  420 , a multiplexer  530  for outputting the resampled early/late PN sequences  422  and  424 , and control circuitry  550  for controllably selecting the appropriate chip pair from the 4 LPN sequences. 
     Three signals are received into the LPN resampler  364 : the local PN sequence  502 , an error signal  504 , and a dec/advB signal  508 . The local PN sequence  502  is provided by the LPN generator  364 , described above. The error signal  504  and the dec/advB signal  508  are provided by the delay lock loop (DLL) (FIG. 1B) described above, and define the fractional chip misalignment between the received and local sequences, {fraction (3/10)} of a chip period in the exemplary embodiment of FIG.  4 . In the preferred embodiment, the error/dec_thresh signal  504  is a 4-bit number indicating the magnitude of the DLL&#39;s error signal  130  (FIGS. 1B and 1F) and represents N/ 32  of a chip period. The dec/advB signal  508  is a one bit signal representing the sign of the DLL&#39;s error signal  130  (FIGS.  1 B and  1 F), indicating if the frame of the received PN chip sequence is delayed (−T) or advanced (+T) relative to the frame of the local PN sequence  502 . These two signals allow the correlation circuit to operate within ±1/2 of a chip period range as described in FIG.  1 F. An adder  505  is used to generate adv_thresh signal  506  by combining a value  15  to the error/dec_thresh signal  504 . 
     In the preferred embodiment, the tapped delay line  510  includes 3 serially connected registers  510   a-c , each of which process the local sequence with a one chip period delay to generated the local sequences  414 ,  406 ,  408 , and  420  (FIG.  4 ). The output of each register  510   a-c  is tapped and connected to the multiplexer  530 . 
     The multiplexer  530  in the preferred embodiment consists of five, dual input multiplexers  530   a-e , as shown. The multiplexers  530   a-c  each receive two versions of the local sequence, one version delayed one chip period compared to the other. A first mux control signal  550   a  selects between the is outputs of each of the three multiplexers  530   a-c . These three outputs and a second mux control signal  550   b  are input to the multiplexers  530   d-e . Responsive to the second mux signal  550   b , the two multiplexers  530   d-e  output the correct early/late local sequences  422  and  424  (FIG.  4 ). 
     The resampler control circuitry  550  is used to controllably select the correct chip pair from the four local sequences. In the preferred embodiment, the resampler control circuitry  550  includes an alignment circuit  551 , signal delays  552   a-b , multiplexers  553   a-c , logic circuits  554   a-b , a chip counter  555  and comparators  556   a-b.    
     The alignment circuit  551  detects when the pulses of the 1x chip clock and the beat clock are coincident and, in response, generates the first boundary signal  430  (FIG.  4 ), described above. Signal delays  552   a-b  generate the mid- and end-of-frame boundary pulses  450  and  440 . The mid- and end-of-frame pulses  450  and  440  are supplied to a first mux  553   a . The dec/advB signal controls the first mux  553   a  to output an end of frame boundary signal  450  when the dec/advB signal is high and a mid-frame pulse when the dec/advB signal is low. 
     A chip counter  555  is loaded with a count value equal to N, where 1/[2*(N+1)] is the maximum resolution allowed to correctly align the chip pairs. In the exemplary embodiment of FIG. 4 where the local and received PN sequences are misaligned {fraction (3/10)} of a chip, the count value is 4. In the preferred embodiment, the count value is 15. 
     When the dec/advB  508  is a logical high, the chip counter  555  counts down from N to zero starting at the beginning of a frame. The count value is subsequently supplied to first and second comparators  556   a-b . The first comparator  556   a  tests whether the count value is less or equal to than the dec_thresh value and if so, a high signal is output. The second comparator  556   b  tests whether the count value is greater than the adv_thresh, and if so, a high signal is output. In response to the dec/advB signal  508 , a third mux  553   c  selects between the first and second comparator signals. The comparator&#39;s output pulse, the mid-frame pulse and the dec/advB signals are supplied to the mux select logic circuit  554   b , which outputs two mux control signals  550   a  and  550   b . The mux control signal  550   a  is determined by the state of the dec/advB signal  508 . In the preferred embodiment, if dec/advB  508  is high, the mux signal  550   a  selects chip pairs from the sequences  406 / 408  or  408 / 420 . If dec/advB is low, chips pairs from the sequences  414 / 406  and  406 / 408  are selected. The mux signal  550   b  is the aforementioned mux control signal  426  of FIG.  4  and has a duration of [X+0.5] chips, where X represents the fraction chip misalignment (dec_thresh value), 2.5 chips in the exemplary embodiment of FIG.  4 . 
     The above described process continues until the chip counter reaches zero. Once the chip counter  555  counts down to zero, the counter  555  loads the count value and disables itself until it receives the next frame boundary, at which time it repeats the process, assuming dec/advb remains high. 
     While the above is a complete description of the preferred embodiments of the invention, various alternatives modifications and equivalence may be used. For instance, the above-described correlation circuit may be easily modified to operate within analog communication systems. The earlier, early, late, and later versions of the received signal in the analog domain may be realized using phase delays instead of signal delays shown. It should be evident that the present invention is equally applicable by making appropriate modifications to the embodiments described above. Therefore, the above description should not be taken as limiting the scope of the invention which is defined by the metes and bounds of the appended claims.