Abstract:
A Serializer/Deserializer (SerDes) is described with improved transmitter driver architecture. The transmitter driver architecture consumes significantly less power than other transmitter driver architectures as most of the circuits are driven by a low power supply. Furthermore, there is no need for level shifting even though the transmitter driver architecture is capable of supporting over as 1V of differential peak-to-peak voltage across the communication channel.

Description:
FIELD OF THE DISCLOSURE 
     The present disclosure is generally directed toward data communication and, in particular, toward drivers for serializers. 
     BACKGROUND 
     Serializer/Deserializers (Ser/Des) are devices that can take wide bit-width, single-ended signal buses and compress them to a few, and often times one, differential signal that switches at a much higher frequency rate than the wide single-ended data bus. A SerDes is often used in high-speed communication networks and is typically an Integrated Circuit (IC) transceiver. In other words, the SerDes provides the interface between a core of an IC or similar processor core and the communication channel used to carry information to/from the core of the IC or processor. 
     SerDes applications with higher data rates are trying to strive for better power efficiency (mW/Gbps). Meanwhile, some applications and standards require the transmitter output to be as high as 1.2V (differential peak-to-peak). There are some problems with using a conventional voltage mode driver for providing as high as 1.2V differential swings at the output, including: (1) reliability concerns (oxide breakdown in case of thin oxide devices); (2) higher power consumption due to the transmission circuits using a 1.2V supply when not needing it; and (3) level shifters are needed to raise the signal domain from a lower supply that the Serializers and other preceding circuits use. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure is described in conjunction with the appended figures, which are not necessarily drawn to scale: 
         FIG. 1  is a block diagram depicting a communication system in accordance with embodiments of the present disclosure; 
         FIG. 2  is a block diagram depicting details of a transmitter in accordance with embodiments of the present disclosure; 
         FIG. 3  is a block diagram depicting details of transmitter driver segments in accordance with embodiments of the present disclosure; 
         FIG. 4  is a circuit diagram depicting illustrative circuits that can be used to construct transmitter driver segments in accordance with embodiments of the present disclosure; 
         FIG. 5  is a circuit diagram depicting additional details of a transmitter driver segment in accordance with embodiments of the present disclosure; 
         FIG. 6  is a circuit diagram depicting an equivalent circuit for the transmitter driver segment in accordance with embodiments of the present disclosure; 
         FIG. 7  is a block diagram depicting details of a transmitter regulator in accordance with embodiments of the present disclosure; and 
         FIG. 8  is a circuit diagram depicting details of a regulator circuit in accordance with embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The ensuing description provides embodiments only, and is not intended to limit the scope, applicability, or configuration of the claims. Rather, the ensuing description will provide those skilled in the art with an enabling description for implementing the described embodiments. It being understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the appended claims. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure. 
     As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise,” “comprises,” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The term “and/or” includes any and all combinations of one or more of the associated listed items. 
     While embodiments of the present disclosure will be described in connection with a transmitter of a serialized data stream that serializes data that was previously parallelized, it should be appreciated that embodiments of the present disclosure are not so limited. In particular, while the particular type of low-level circuit or circuit components described herein (e.g., a Serializer/Deserializer (SerDes)) is capable of accelerating and serializing data, it should be appreciated that any type of Integrated Circuit (IC), IC chip, IC chip component, audio/video signal processing, telephone system, etc. can utilize circuitry and/or systems described herein. 
     Referring now to  FIG. 1 , a communication system  100  will be described in accordance with at least some embodiments of the present disclosure. The system  100  is shown to include one or more transceivers  104   a ,  104   b , each having a transmitter  108  and a receiver  112 . The transceivers  104   a ,  104   b  are shown to communicate with one another via one or more communication channels  116  that connect a transmitter  108  with a receiver  112 . It should be appreciated that embodiments of the present disclosure may also be implemented in a communication system having dedicated transmitters  108  and receivers  112  instead of a combination of a transmitter  108  and receiver  112  being implemented in a transceiver  104 . 
     In some embodiments, the communication channel  116  may carry an analog signal that is modulated according to any type of known modulation technique, such as Amplitude Modulation, Pulse Amplitude Modulation, Non-Return to Zero Modulation, Double-Sideband Modulation, Vestigal Sideband Modulation, Quadrature Amplitude Modulation, Frequency Modulation, Phase Modulation, combinations thereof, or the like. The communication channel  116  may include a wired communication medium (e.g., a physical wire, coaxial cable, fiber-optics, etc.), a wireless communication medium (e.g., air), or a combination of wired and wireless media. It should be appreciated that the transmitter  108  may be configured to first receive a digital signal as an input (e.g., from a digital circuit or digital circuit components, such as an IC or IC component or processor core) and then convert the digital signal into an analog signal for transmission across the communication channel  116 . The receiver  112  may be configured to receive the analog signal from the communication channel  116  and convert the analog signal back into a digital signal for processing by a digital circuit or processor core that is connected to an output of the receiver  112 . It should be appreciated that the communication channel  116  may traverse long or short distances. For instance, the communication channel  116  may correspond to a short interconnection between components on an IC chip. In some embodiments, the communication channel  116  may correspond to a SerDes channel. As another example, the communication channel  116  may correspond to a long interconnection (e.g., on the order of miles) between a transmitting station and a receiving station. 
     Referring now to  FIG. 2 , additional details of a transmitter system  200  will be described in accordance with at least some embodiments of the present disclosure. The transmitter system  200  may correspond or be similar to transmitter  108 . In some embodiments, the transmitter system  200  includes a processor core  204 , a serializer  208 , and a driver  216 . The driver  216  is show to include a pre-driver  220  as well as one or more driver segments  224 . Although the components  204 ,  208 ,  220 ,  224  are shown as being a part of a common transmitter system  200 , it should be appreciated that the components  204 ,  208 ,  220 ,  224  can be included in different physical components. The output of the driver segments  224  include a first and second data channel that carry serialized data generated by the driver segment(s)  224 . In the depicted embodiment, the two outputs include a txp and txn output. The transmitter system  200  may be capable of supporting up to 1.0V of different peak-to-peak voltage between the first data channel txp and the second data channel txn. 
     Advantageously, the serializer  208  and pre-driver components  220  are driven by low power supplies  212 ,  228 , which may be on the order of 0.85V to 1.0V. Meanwhile the driver segment(s)  124  are capable of being partially driven by low power supplies and minimally driven by high power supplies  232 . Because the serializer  208 , pre-driver  220 , and most of the components in the driver segment(s)  224  are driven by low power  212 ,  228  as opposed to high power supplies, which may be on the order of 1.0V to 1.2V. Most SerDes transmitters of the prior art require that the driver segments and pre-driver entirely be driven by high power supplies. Moreover, conventional SerDes transmitters required the user of a level shifter between the serializer and pre-driver to assist with the signal shift from the low voltage to the high voltage without inducing jitter and other sources of noise. The transmitter system  200  of the present disclosure, on the other hand, does not need the use of a level shifter as the driver segment(s)  224  are at least partially driven by the low voltage supply. 
     As can be seen in  FIG. 3 , additional details of the driver segment(s)  224  are shown. In particular, the driver segment(s)  224  may include a plurality of driver segments  304  where each segment  308  in the plurality of driver segments  304  is weighted and has at least two nodes that are tied individually to one another. This particular construction of the plurality of driver segments  304  enables a flexibility in transmitter design for different transmitter applications. Furthermore, the various weighted transmitter segments  308  may have their resistances weighted from 1 to 68 or more. In some embodiments, the driver segment(s)  224  are composed of differently weighted segments  308 , each of which contributes to transmission of a signal across the output channels txp, txn. 
     Additional details of the plurality of weighted segments  404   a -N are shown in  FIG. 4  where it can be seen that the circuit of each weighted segment  404   a -N is connected to a common high voltage supply line Vhigh. The weighted segments  404   a -N may correspond to specific variants of the segments  308 , but should not be construed as the only mechanism for achieving the segments  308 . 
     In the depicted embodiment, each of the weighted set of segments  404   a -N have a P-channel Metal Oxide Semiconductor Field-Effect Transistor (PMOS) side (e.g., top half of circuit between Vhigh supply line and a line drawn through inputs inp, inn) as well as an N-channel MOSFET (NMOS) side (e.g., bottom half of circuit between the reference node/ground and a line drawn through inputs inp, inn). In the event that the driver segment(s)  224  are desired to only include a single segment, then only the first weighted segment  404   a  may be necessary for the driver segment  224 . On the other hand, if a plurality of driver segments  224  are desired, then a plurality of weighted segments  404   a -N may be connected to one another. One advantage to using the configuration of the weighted segments  404  depicted herein is that each of the inputs to the logic components (e.g., inputs inn and inp) are on the low voltage domain. This alleviates the need for a level shifter in addition to reducing the overall power consumed by the transmitter driver  216 . 
     As can be seen in  FIG. 4 , each weighted segment  404  includes two or more logic components (e.g., PMOS transistors S 1 , S 2 ) on the PMOS side and two or more logic components (e.g., NMOS transistors S 3 , S 4 ) on the NMOS side. The pair of PMOS transistors S 1 , S 2  on the PMOS side each have a source node connected to a first shared node N 1 . The first shared node N 1  is separated from the high voltage source (e.g., Vhigh supply line) by a first resistor R 1 . The first resistor R 1  may be referred to herein as a degeneration resistor or split degeneration resistor as it helps degenerate the high voltage source to a level that is approximately equal to the low voltage (e.g., inputs inp, inn) at which the other logic components of the circuit are driven. 
     The first PMOS transistor S 1  receives the first input inp from the pre-driver  220  at its gate. In some embodiments, the first input inp is a low voltage input and is on the order of 0.85V to 1.0V. The drain of the first PMOS transistor S 1  is connected to a first drive resistor Rx, which may be weighted depending upon which segment  404   a -N it belongs to. For instance, the first drive resistor Rx in the first segment  404   a  may not be weighted at all and may have a nominal resistance of approximately 33 ohms. The first drive resistor R 16   x  in the Nth segment  404 N may be weighted by 16 times the first segment  404   a , in which case the first drive resistor R 16   x  may comprise a resistance that is sixteen times greater than the resistance of the first drive resistor Rx in the first segment  404   a . The first drive resistor Rx carries current from the drain of the first PMOS transistor S 1  to a first output node N 3 , which supplies the first portion of the serialized output txp. 
     The second PMOS transistor S 2  receive the second input inn from the pre-driver  220  at its gate. In some embodiments, the second input inn is complimentary and opposite to the first input inp, meaning that the second input is 180 degrees out of phase with the first input and operating at approximately the same voltage levels as the first input (e.g., between 0.85V and 1.0V). The drain of the second PMOS transistor S 2  is connected to a second drive resistor Rx, which may be weighted depending upon which segment  404   a -N it belongs to. The second drive resistor Rx carries current from the drain of the second PMOS transistor S 2  to a second output node N 4 , which supplies the second portion of the serialized output txn. The outputs txp, txn may then be serialized with one another for transmission across the communication channel  116 . 
     Similar to the PMOS side, the pair of NMOS transistors S 3 , S 4  on the NMOS side may each have a source node connected to a second shared node N 2 . The second shared node N 2  is shown to be separated from a reference voltage or ground by a second resistor R 2 . In some embodiments, the resistance of the first and second resistors R 1 , R 2  are approximately the same and can be on the order of 10 ohms to 20 ohms for the transmitter system  200  operating at 14 GHz or more and having a high supply voltage around 1.2V. 
     The first NMOS transistor S 3  (which may also be referred to as a third logic component) is shown to receive the same input as is provided to the first PMOS transistor S 1 . The second NMOS transistor S 4  (which may also be referred to as a fourth logic component) is shown to receive the same input as is provided to the second PMOS transistor S 2 . The drain of the first NMOS transistor S 3  is connected to the first output node N 3  via a third drive resistor Rx, that is approximately the same size as the other drive resistors in the circuit. Likewise, the second NMOS transistor S 4  is connected to the second output node N 4  via a fourth drive resistor Rx, that is approximately the same size as the other drive resistors in the circuit. 
     By enabling each of the logic components S 1 , S 2 , S 3 , S 4  to receive low voltage inputs at their gates, the power consumption of the overall segment  404   a -N is reduced as compared to a scenario where each of the logic components are receiving high voltage inputs. Accordingly, the first and second resistors R 1 , R 2  enable reduced power consumption for the overall circuit and help to avoid the need for a level shifter in the transmitter system  200 . In other words, the first and second resistors R 1 , R 2  provide a voltage drop from the high voltage supply that approximates a voltage input to the gates of the logic components S 1 , S 2 , S 3 , S 4 . The drive resistors also help to protect the logic components S 1 , S 2 , S 3 , S 4  from electrostatic discharge. 
     Because of the configuration of the driver segments  224  depicted herein, each segment  404  can behave like a different cell. Every segment  404  has its source tied at local levels (e.g., Vhigh supply voltage). This global node connection impacts the amplitude/step size as well as non-linearity/common mode noise. In particular, as can be seen in  FIG. 5 , parasitic capacitance Cp can exist between the first common node N 1  and the drain of a PMOS transistor (e.g., S 1  or S 2 ).  FIG. 5  shows a parasitic capacitance Cp existing between the first common node and the drain of the second logic component S 2 . The transmitter architecture suggested herein helps to limit this parasitic capacitance Cp within controlled levels. 
     The impact of the parasitic capacitance Cp at the first common node N 1  impacts the bandwidth of the node as the voltage needs to settle within 1 UI (e.g., 28.5 ps for a transmitter operating at 28 Gbps). A very high capacitance dictates the voltage settling at the node. For a large number of 1 UI patterns, the voltage trends higher than the DC level of Vreg−IR. This is referred to as the common mode noise impact. However, the impact of the common mode noise is generally minimized due to the fact that the degeneration resistors R 1 , R 2  help to drop the high voltage in front of the sources of the logic components S 1 , S 2 , S 3 , S 4 . 
     With reference now to  FIG. 6 , additional details of an equivalent circuit to the segments  404  shown in  FIG. 4  will be described. In particular, the equivalent circuit shown in  FIG. 6  is showing the split resistors and the features of implementing the same. The resistance between the input voltage and the first output txp may have its total resistance split among the first resistor (e.g., the degradation resistor) R 1  and a third resistor (e.g., a drive resistor and internal resistance of the first logic component S 1 ) R 3 . A communication channel resistance Rcc is also depicted as approximating the resistance of the communication channel  116 . Similar to the first output, the second output txn may have a split resistance between itself and the reference node. 
     In some embodiments, the ratio of the split resistance R 1 :R 3  may be approximately 0.33:0.66. For instance, if the Vhigh is approximately 1.15V or 1.2V and the communication channel resistance Rcc is approximately 100 ohms, then the split resistance for the first output (e.g., R 1  and R 3 ) may be approximately 50 ohms. The first resistor R 1  may have a resistance of approximately 16.66 ohms (e.g., ⅓ of the whereas the third resistor R 3  may have a resistance of approximately 33.33 ohms. Similar values may be applied for R 2  and R 3 , meaning that the size of the second resistor R 2  may be approximately equal to the size of the first resistor R 1 . It should be appreciated that the relatively larger size of the drive resistors helps to protect the logic components S 1 , S 2 , S 3 , S 4  from electrostatic discharge. However, it is also desirable to keep Vsp and Vsn at relatively low levels to maintain low power consumption for the driver. 
     In this illustrative scenario, the current flowing through the equivalent circuit may be approximately 5.75 mA. This will result in a voltage at the first output txp to be approximately 0.86V while the voltage at the second output txn will be approximately 0.288 V. These voltages result in a differential peak-to-peak voltage of 1.15V, consistent with the high supply voltage. It should also be appreciated that the proposed transmitter architecture exhibits approximately the same return loss as conventional drivers; again, without needing a level shifter and with reduced power consumption. 
     It is another aspect of the present disclosure to propose a mechanism for handling hot plug-in events as well as other device reliability concerns. With reference now to  FIG. 7 , details of a transmission regulator  704  will be described in accordance with at least some embodiments of the present disclosure. The transmission regulator  704  is shown to be connected to a regulator capacitance Cr, which can be on the order of 70 pF to 100 pF, or more specifically about 80 pF, when the regulator voltage Vreg is approximately 1.2V. When operating at these levels, the driver current may be approximately 6.0 mA. This voltage and current provided to the driver  216  and specifically to the driver segments  404  can be regulated by the transmission regulator  704  to help avoid damage to the logic components S 1 , S 2 , S 3 , S 4  in each of the driver segments  404 . 
       FIG. 8  shows one specific, but non-limiting, example of a transmission regulator circuit  700  that can be implemented in accordance with at least some embodiments of the present disclosure. The regulator circuit  800  that can be incorporated into the transmission regulator  704  and is shown to include a plurality of logic components. The regulator circuit  800  is shown to include an amplifier section  804  and a hot-plug detection section  808 . The amplifier section  804  includes a plurality of logic components that are used to regulate the voltage and current provided by the transmission regulator to the driver  216 . In particular, the amplifier section  804  is connected to and controlled by the hot-plug detection section  808 . In the event that the hot-plug detection circuit  808  detects normal or regular operating conditions, then the input voltage Vin is approximately 700 mV and the output voltage Vout is set to ‘0’. This causes the amplifier section  804  to produce a regulated voltage Vreg of approximately 1.2V and a regulated current of approximately 6 mA. 
     On the other hand, when the hot-plug detection section  808  detects a hot-plug condition, the input voltage will be approximately 100 mV and the output voltage will be set to ‘1’. This causes the amplifier section  804  to generate a regulated voltage Vreg of approximately 1.0V, thereby protecting the driver  216  and the components thereof from the voltage spikes traditionally encountered with a hot-plug condition. 
     In some embodiments, a hot-plug condition or event occurs when there is no connection to the receiver/Rx. The connection could be pulled out accidentally or sometimes for testing purposes. The problem with such an event is that the Tx port sees and open circuit. There is no current flowing through the transmitter devices. This means that there is zero current flowing through the degeneration resistor. 
     With no current flowing through the degeneration resistor, the PMOS source is at the Vhigh supply instead of the Vsupply−IR drop (Approximately low supply). Such an event causes device overstress and increases chances of Oxide breakdown. 
     To handle a hot-plug condition, embodiments of the present disclosure propose a feedback scheme where a switch mirroring the Regulator output voltage is employed. W/L is the size of the Regulator Amplifier switch whereas W/nL means that the mirrored current is a very small replica current. The idea of the small replica current is to help detect when the transmitter is in operation so that the regulated output can be approximately 1.2V. 
     If the logic built with the replica bias detects that there is no current through the transmitter (e.g., a hot-plug condition), then the logic sends a feedback to the regulator to lower the output voltage to approximately 1V. Vgn is the gate voltage of the regulator amplifier. The Vset is high or the low supply select based on the transmitter operation. 
     Specific details were given in the description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments. 
     While illustrative embodiments of the disclosure have been described in detail herein, it is to be understood that the inventive concepts may be otherwise variously embodied and employed, and that the appended claims are intended to be construed to include such variations, except as limited by the prior art.