Abstract:
In a non-planar based semiconductor process where the structure includes both N and P type raised structures (e.g., fins), and where a different type of epitaxy is to be grown on each of the N and P type raised structures, prior to the growing, a lithographic blocking material over one of the N and P type raised structure portions is selectively etched to expose and planarize a gate cap. After the first type of epitaxy is grown, the process is repeated for the other of the N and P type epitaxy.

Description:
BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention generally relates to fabrication of non-planar semiconductor structures. More particularly, the present invention relates to preventing non-uniform gate height over N and P type raised structures on the substrate, by selective etching of a lithographic blocking material to expose a gate cap and planarizing the gate cap prior to growing epitaxy on the N type raised structures and P type raised structures. 
     2. Background Information 
     In a conventional fin-based semiconductor process with both N and P type fins, when growing epitaxy on top of the fins (one kind for N type fins, and a different kind for P type fins), the protective materials used during lithography for both types of fins overlap in a small area above the gate, resulting in a non-uniform gate height over the different epitaxies. 
     Therefore, a need exists for a way to prevent the non-uniform gate height during the use of lithography. 
     SUMMARY OF THE INVENTION 
     The shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, of a method of preventing non-uniform gate height over N and P type raised structures. The method includes providing a non-planar semiconductor structure, the structure including a semiconductor substrate, at least one first raised semiconductor structure of N or P type coupled to the substrate, at least one second raised semiconductor structure of opposite N or P type coupled to the substrate, and at least one dummy gate structure situated over and encompassing a portion of the at least one first and the at least one second raised structures, the dummy gate structure including a conformal layer of a dummy gate material and a gate cap layer over the dummy gate material. The method further includes masking one of the at least one first and the at least one second raised structure and a portion of the dummy gate structure thereover with a layer of lithographic blocking material, selectively etching the layer of lithographic blocking material to expose the gate cap layer of the masked one of the at least one first and the at least one second raised structure, and planarizing all of a top surface of the gate cap layer. 
     In accordance with another aspect, a non-planar semiconductor structure is provided. The structure includes a semiconductor substrate, at least one first raised semiconductor structure of N or P type coupled to the substrate, at least one second raised semiconductor structure of the other of N or P type coupled to the substrate, and at least one dummy gate structure situated over and encompassing a portion of the at least one first and the at least one second raised semiconductor structures, the dummy gate structure including a conformal layer of a dummy gate material and a gate cap layer over the dummy gate material. The structure further includes a layer of lithographic blocking material over a portion of the dummy gate structure above one of the at least one first raised semiconductor structure and the at least one second raised semiconductor structure, a top surface of the gate cap layer being planarized below a top surface of the layer of lithographic blocking material. 
     These, and other objects, features and advantages of this invention will become apparent from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts a cross-sectional plan view of a non-planar semiconductor structure having both N and P type raised semiconductor structures, a dummy gate structure and a lithographic blocking material over the N type raised structures. 
         FIG. 2  depicts the semiconductor structure of  FIG. 1  after selective etching of the lithographic blocking material to expose the gate cap of the dummy gate structure. 
         FIG. 3  depicts the semiconductor structure of  FIG. 2  after planarizing the gate cap. 
         FIG. 4  depicts the semiconductor structure of  FIG. 3  after removing the lithographic blocking material and growing epitaxy on the P type raised structures. 
         FIG. 5  depicts the semiconductor structure of  FIG. 4  after adding a layer of lithographic blocking material over the P type portion of the semiconductor structure. 
         FIG. 6  depicts the semiconductor structure of  FIG. 5  after selectively etching the lithographic blocking material to expose the gate cap. 
         FIG. 7  depicts the semiconductor structure of  FIG. 6  after planarizing the gate cap and protecting the necks of the N type raised structures. 
         FIG. 8  depicts the semiconductor structure of  FIG. 7  after removal of the lithographic blocking material and growing epitaxy on the N type raised structures above the protected necks. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating aspects of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions, and/or arrangements, within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure. 
     Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” is not limited to the precise value specified. In some instances, the approximating language may correspond to the precision of an instrument for measuring the value. 
     The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include (and any form of include, such as “includes” and “including”), and “contain” (and any form of contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises,” “has,” “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises,” “has,” “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed. 
     As used herein, the term “connected,” when used to refer to two physical elements, means a direct connection between the two physical elements. The term “coupled,” however, can mean a direct connection or a connection through one or more intermediary elements. 
     As used herein, the terms “may” and “may be” indicate a possibility of an occurrence within a set of circumstances; a possession of a specified property, characteristic or function; and/or qualify another verb by expressing one or more of an ability, capability, or possibility associated with the qualified verb. Accordingly, usage of “may” and “may be” indicates that a modified term is apparently appropriate, capable, or suitable for an indicated capacity, function, or usage, while taking into account that in some circumstances the modified term may sometimes not be appropriate, capable or suitable. For example, in some circumstances, an event or capacity can be expected, while in other circumstances the event or capacity cannot occur—this distinction is captured by the terms “may” and “may be.” 
     Reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers are used throughout different figures to designate the same or similar components. 
       FIG. 1  depicts a cross-sectional plan view of a semiconductor structure  100 , including a substrate  102  and raised semiconductor structures  104  (e.g., fins) with respect to the substrate. Between the bodies of the raised structures is one or more dielectric materials  105 . In one example, a shallow trench isolation process is used to deposit the dielectric material(s). The raised structures include both N type  106  and P type  108 . Above and encompassing a portion  110  of the raised structures is a gate structure  112 , in this example, the gate structure including a layer  114  of a dummy gate material (e.g., polysilicon) and a gate cap layer  116  of a protective material (e.g., a nitride, for example, silicon nitride (SiN)). Conformally covering a neck portion (e.g., neck portion  118 ) of the raised structures, as well as the gate structure and dielectric material(s)  105 , is a relatively thin (e.g., about 5 nm to about 10 nm) conformal layer  119  of a protective material, e.g., a nitride. Covering the N type portion  120  of the structure  100  is a layer  122  of a lithographic blocking material, for example, an organic planarizing layer (OPL). As one skilled in the art will know, OPL is highly selective to ashing (a dry etch), which uses a strongly oxidizing ambient, e.g., oxygen plasma ashing. 
       FIG. 2  is a cross-sectional plan view of the structure  100  of  FIG. 1  after the layer of lithographic blocking material  122  has been etched to expose the gate cap  116 . The etch used is preferably selective to the lithographic blocking material, in order to avoid etching the gate cap. Also preferably, the etch used for the lithographic blocking material will also remove the thin, conformal layer of protective material  119  above the gate cap, as well as about the P type raised structure neck(s)  118  and above the dielectric(s)  105 . In one example, where the lithographic blocking material is OPL, ashing may be used for the etch, e.g., oxygen plasma ashing. 
     With the gate cap exposed, it can be planarized across both N and P type sections, as shown in  FIG. 3 . In one example, where the gate cap is silicon nitride (SiN), the planarization can be accomplished by, for example, using a dry etch process. With the neck(s) of the P type raised structures exposed, epitaxy  124  (see  FIG. 4 ) can be grown thereon after recessing the neck(s). 
     In one example, as shown in  FIG. 4 , epitaxial silicon germanium (SiGe) is grown on the P type raised structures. As one skilled in the art will know, SiGe naturally grows into an elongated diamond shape. After removing the lithographic blocking material, a similar process may then be performed for the N type raised structures. In one example, where the lithographic blocking material is OPL, it can be removed by, for example, oxygen or Diazene (N 2 H 2 ) ashing. 
     As shown in  FIG. 5 , the thin, conformal layer of protective material  119  is restored above the gate cap and now covers the epitaxy atop the P type raised structures. A layer of lithographic blocking material  126  (e.g., OPL) now covers the P type portion  128  of structure  100 . In one example, the layer of lithographic blocking material is deposited using a commercially available lithographic track tool. Similar to the process for the N type section, the layer of lithographic blocking material  126  is etched, as shown in  FIG. 6 , to expose the gate cap  116 . As noted above, the etch used is preferably selective to the lithographic blocking material, to avoid etching the gate cap. For example, where the gate cap is SiN, a dry etch may be used. 
     After the gate cap  116  has been exposed, it can be planarized, as shown in  FIG. 7 . As with the N type section, the gate cap etch also preferably removes the thin, conformal layer of protective material  119  above the gate cap (see  FIG. 6 ) and the N type raised structures, except for the neck area thereof (e.g., neck  130 ). A layer  132  of the protective material remains around the N type necks. The epitaxial material used for the N and P type raised structures is different, and different epitaxial materials grow at different rates. In the present example, the N type epitaxy may include, for example, silicon phosphorus (SiP), which grows more slowly than, for example, silicon germanium used for the P type raised structures. In general, the goal is to have the N and P type epitaxy end at about the same height. Thus, as shown in  FIG. 8 , slower growing epitaxy  134  together with a longer raised structure neck  130  on the N type raised structures  106  will be at a similar height as relatively faster growing epitaxy  124  and a shorter neck or none on the P type raised structures  108 . 
     While several aspects of the present invention have been described and depicted herein, alternative aspects may be effected by those skilled in the art to accomplish the same objectives. Accordingly, it is intended by the appended claims to cover all such alternative aspects as fall within the true spirit and scope of the invention.