Abstract:
A voltage regulator circuit has a first amplifier stage with input and output terminals, a feedback terminal, a pole-inducing transistor, and a compensating network coupled to the output terminal. A second amplifier stage has an input coupled to the first amplifier output, first and second current mirrors, and a pass transistor.

Description:
TECHNICAL FIELD  
       [0001]     The present invention is related to integrated circuits. More specifically, the present invention is an apparatus and method for a voltage regulator circuit.  
       BACKGROUND ART  
       [0002]     Low drop-out (LDO) voltage regulators are implemented in a variety of circuit applications to provide regulated power supplies. Increased regulator performance is especially being demanded in mobile battery-operated products such as cellular phones, pagers, camcorders, and laptop computers. For these products, regulators having a high power supply rejection ratio (PSRR) to yield low noise and ripple are needed. Regulators of this type are preferentially fabricated in standard low-cost CMOS processes, making them difficult to realize with the required performance characteristics.  
         [0003]     A journal publication entitled “A Low-Noise High PSRR, Low Quiescent Current, Low Drop-out Regulator” by Hafid Amrani et al. states that regulators with high PSRR require a first stage amplifier with a large gain-bandwidth product. The gain-bandwidth product of an amplifier is the product of the amplifier&#39;s dc gain and its cutoff frequency, which for LDO applications is typically 1 MHz or lower. The required first stage amplifier performance can be achieved by a large dc gain, or by a high cutoff frequency.  
         [0004]     A first journal publication entitled “A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator” by Gabriel A. Rincon-Mora and Phillip E. Allen proposes a circuit structure using a current efficient buffer and a current boosted pass device to realize a low quiescent current LDO regulator for low voltage operation.  
         [0005]     A second journal publication entitled “Optimized Frequency Shaping Circuit Topologies for LDOS” by Gabriel A. Rincon-Mora and Phillip E. Allen proposes a circuit structure using pole-zero doublet generation to increase the bandwidth for dynamic load regulation.  
         [0006]     A third journal publication entitled “Active Capacitor Multiplier in Miller-Compensated Circuits” by Gabriel A. Rincon-Mora and Phillip E. Allen proposes a circuit structure using Miller capacitor multipliers to reduce the silicon area consumed by a voltage regulator.  
         [0007]     The main drawbacks of these proposed methods are:  
         [0008]     1. The current efficient buffer circuit requires NPN bipolar transistors to avoid creation of a parasitic pole at the output of an error amplifier within the circuit.  
         [0009]     2. The structure based on the pole-zero doublet can be stabilized if the dc open-loop gain is relatively small (e.g., 50 dB for a high current load). However, since the dc value of the PSRR is proportional to the inverse of the open-loop gain of the regulator, the dc value of the PSRR for this design cannot exceed 50 dB.  
         [0010]     3. The Miller compensation method creates an internal pole. To make the cutoff frequency of the PSRR as high as possible, the pole of the first stage has to be as high as possible. Thus, the PSRR performance of this circuit structure is compromised. The noise performance of the regulator is also reduced.  
         [0011]     With reference to  FIG. 1 , a low drop-out (LDO) regulator circuit  100  as known in the prior art comprises a first amplifier stage  110  and a second amplifier stage  120 . The first amplifier stage  110  includes PMOS transistors P 112 , P 116 , and P 118 , diode-connected NMOS transistor N 116  and NMOS transistor N 118 . The second amplifier stage  120  includes diode-connected PMOS transistors P 122  and P 126 , PMOS transistor P 124 , diode-connected NMOS transistor N 124  and NMOS transistors N 122  and N 126 . The second amplifier stage  120  further includes PMOS power transistor P 128 . Resistive divider circuit comprising a resistor R 1  and a resistor R 2  is coupled to an output controlled voltage node V OUT . The ratio of the resistor R 1  to the resistor R 2  controls a proportion of the potential on the output controlled voltage node V OUT  which is fed back to the first amplifier stage. By varying the resistor R 1  and the resistor R 2 , the output voltage of the regulator circuit  100  can be programmed. A current load I L  is coupled to the output controlled voltage node V OUT , representing an electrical load being powered by the regulator circuit  100  and requiring a consistent operating voltage. An external decoupling capacitance C L  with an associated equivalent series resistance (ESR) R S  is connected in parallel with the current load I L . Skilled artisans will recognize that a plurality of applications exist, such as the operation of microprocessor circuits, mixed signal circuits, memory circuits, and others, which can replace the generic current load I L  attached to the regulator circuit  100  in practical use.  
         [0012]     An analysis of the regulator circuit  100  operation now follows the assumptions and methods in the cited journal publications. A low-valued equivalent series resistance (ESR) R S  is assumed for the external decoupling capacitance C L , which improves the transient ripple of the regulator. A zero introduced by the external decoupling capacitance C L  and the equivalent series resistance (ESR) R S  into the system transfer function is therefore at a higher frequency than the unity gain frequency (UGF) of the open-loop, and does not alter the stability of the regulator circuit  100 .  
         [0013]     As described in the journal article by Hafid Amrani et al., a dominant pole p 1  of the regulator response is determined by the external decoupling capacitance C L  as:  
               p   1     =         gd     P   ⁢           ⁢   128       +     (     1       R   ⁢           ⁢   1     +     R   ⁢           ⁢   2         )         2   ⁢   Π   ⁢           ⁢     C   L                 (   1   )             
 
         [0014]     In formula (1), gd P128  represents the output admittance of PMOS power transistor P 128 . The output admittance gd P128  can be expressed as a function of the current load I L  and a channel modulation parameter, λ, of PMOS power transistor P 128 : 
 
 gd   P128   =λ*I   L   (2) 
 
         [0015]     For a current load I L  that is much larger than  
         (       1     R   ⁢           ⁢   1   *   R   ⁢           ⁢   2       *     1   λ       )     ,       
 
 the pole frequency can be approximated as:  
               p   1     ≈       λ   *     I   L         2   ⁢   Π   ⁢           ⁢     C   L                 (   3   )             
 
         [0016]     For a typical CMOS process, λ is of the order of 0.1 V −1  and typical low-noise regulator applications employ a resistive divider such that (R 1 +R 2 ) is of the order of 100 kΩ. Under these conditions, formula (3) is valid for load currents which are large in comparison with approximately 100 μA. Thus, for a current load I L  of 1 mA or more, the dominant pole of the open-loop transfer function increases with increasing current.  
         [0017]     The dc gain, G DC , of the open-loop transfer function of the regulator circuit  100  can be expressed as:  
                     G   DC     =         gm     P   ⁢           ⁢   118           gd     P   ⁢           ⁢   118       +     gd     N   ⁢           ⁢   118           *         k   1     *     k   2       a     *       gm     N   ⁢           ⁢   122           gd     P   ⁢           ⁢   128       +     1       R   ⁢           ⁢   1     +     R   ⁢           ⁢   2             *       R   ⁢           ⁢   2         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2                       with   ⁢     :                   (   4   )                 gm     N   ⁢           ⁢   122       =       2   *     K   n     *         I   L     *   a         k   1     *     k   2         *       W     N   ⁢           ⁢   122         L     N   ⁢           ⁢   122                     (   5   )             
 
         [0018]     In formulae (4) and (5), gm represents the transconductance of the associated subscripted transistor name, e.g., gm P118  represents the transconductance of PMOS transistor P 118 . Analogously, gd represents the output admittance of the associated subscripted transistor name, e.g., gd P118  represents the output admittance of PMOS transistor P 118 . The parameters k 1  and k 2  represent width ratios of current mirror transistors, such that k 1 =W P124 /W P122  and k 2 =W N126 /W N124 , where W indicates the channel width of the associated subscripted transistor name.  
         [0019]     The variable L in formula (5) represents the channel length of the associated subscripted transistor name, i.e., L N122  is the channel length of the NMOS transistor N 122 . The parameter K n  in formula (5) is the transconductance parameter for the NMOS transistors, and can be further represented as K n =μ n *C ox , where μ n  is the carrier mobility for electrons and C ox  is the capacitance per unit area of the gate oxide. The parameter α is a fraction of the current load I L  flowing in PMOS transistor P 126 . It is also equal to a width ratio of the diode-connected PMOS transistor P 126  and the PMOS power transistor P 128 . Both the diode-connected PMOS transistor P 126  and the PMOS power transistor P 128  are designed with the same channel length to facilitate current matching, i.e., L P126 =L P128  and α=W P126 /W P128 .  
         [0020]     Using the approximation given by formula (3), and combining formulae (2) and (5) into (4) gives G DC  as a decreasing function of I L :  
               G   DC     =         gm     P   ⁢           ⁢   118           gd     P   ⁢           ⁢   118       +     gd     N   ⁢           ⁢   118           *         2   *   Kn   *         k   1     *     k   2       a       λ       *       R   ⁢           ⁢   2         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2         *     1       I   L                   (   6   )             
 
         [0021]     A second pole p 2  is introduced into the regulator open-loop response as a result of the large output impedance of the first amplifier stage  110  and an input capacitance C N122 , associated with the second amplifier stage  120 . The second pole p 2  value can be expressed as:  
               p   2     =         gd     P   ⁢           ⁢   118       +     gd     N   ⁢           ⁢   118           2   ⁢   Π   ⁢           ⁢     C     N   ⁢           ⁢   122                   (   7   )             
 
         [0022]     The capacitance C N122  is determined by the gate-to-source capacitance and Miller gate-to-drain capacitance of the NMOS transistor N 122  according to:  
               C     N   ⁢           ⁢   122       =             Cgs     N   ⁢           ⁢   122       +       Cgd     N   ⁢           ⁢   122       *                       k   ⁢           ⁢   1   *   k   ⁢           ⁢   2     a     *       K   n       K   p       *       W     N   ⁢           ⁢   122         W     P   ⁢           ⁢   128         *       L   P128       L     N   ⁢           ⁢   122                           (   8   )             
 
         [0023]     In formula (8) K p =μ p *C ox  is the transconductance parameter for PMOS transistors, μ p  is the carrier mobility for holes, and C ox  is the capacitance per unit area of the gate oxide. Cgs N122  is the gate-to-source capacitance for NMOS transistor N 122  and Cgd N122  is the gate-to-drain capacitance for NMOS transistor N 122 .  
         [0024]     Formula (8) shows that C N122 , and thus p 2 , are not a function of current load I L , whereas the dominant pole p 1  and the dc gain G DC  depend upon I L . In standard CMOS processes, pole p 2  is typically at a frequency lower than 100 kHz, and therefore below the unity gain frequency. This makes the system transfer function second order and unstable. As previously mentioned, and discussed in the journal article by Hafid Amrani et al., to maintain adequate power supply rejection ratio (PSRR) performance, the regulator circuit  100  configures the first amplifier stage  110  with high dc gain. For maximum stability, the pole P 2  is preferably as high in frequency as possible. The approach employed in the regulator circuit  100  is to add a zero in the feedback loop to stabilize the system. The zero is implemented by means of zero stabilizing resistor R 115  and zero stabilizing capacitor C 115  at the output of the first amplifier stage  110 . The resistor R 115  and the capacitor C 115  series configuration create a pole-zero doublet (pc, zc) in the open-loop transfer function. The zero zc is placed after the unity gain frequency (UGF) such that the open-loop gain crosses the 0 dB axis with a −20 dB per decade slope. The zero stabilizing capacitor C 115  is chosen to have a low value to reduce the frequency of the pole p 2  of the first amplifier stage  110  according to:  
               p   ⁢           ⁢   2     =       1     2   ⁢   Π       *     1           C     N   ⁢           ⁢   122       +     C   ⁢           ⁢   115           gd     P   ⁢           ⁢   118       +     gd     N   ⁢           ⁢   118           +     R   ⁢           ⁢   115   *   C   ⁢           ⁢   115                   (   9   )             
 
         [0025]     The pole-zero doublet (pc, zc) can be expressed as:  
             zc   =     1     2   ⁢   Π   ⁢           ⁢   C   ⁢           ⁢   115   *   R   ⁢           ⁢   115               (   10   )               pc   =     zc   ⁡     (     1   +         C   ⁢           ⁢   115       C     N   ⁢           ⁢   122         *     [     1   +       (       gd     P   ⁢           ⁢   118       +     gd     N   ⁢           ⁢   118         )     *   R   ⁢           ⁢   115       ]         )               (   11   )             
 
         [0026]     Like pole p 2 , pc and zc are independent of the current load I L . Comparison of formulae (9), (10), and (11) shows that p 2 &lt;zc&lt;pc. Therefore, the regulator is stable regardless of the value of the current load I L . The system transfer function becomes locally a first order transfer function.  
         [0027]     In addition to the discussions supra, the first journal publication by Gabriel A. Rincon-Mora and Phillip E. Allen explains that a third pole p 3  is realized by the gate node of the PMOS output transistor P 128 . By application of a boost technique described in the first publication, pole p 3  can easily be increased in frequency beyond the unity-gain frequency (UGF) of the open-loop system such that pole p 3  does not alter system stability. To apply the boost technique in the regulator circuit  100  a fraction of the current load I L  is sourced into the bulk terminal (not shown) of the diode-connected PMOS transistor P 126 . Typically, the current fraction is between 1/1000 and 1/100. By sourcing current into the bulk terminal of the diode-connected PMOS transistor P 126 , the threshold voltage of the diode-connected PMOS transistor P 126  and the PMOS power transistor P 128  is effectively lowered, producing an increase in the conductance of PMOS power transistor P 128  and an increase in the associated pole p 3  frequency. Additionally, the current mirrors of ratio k 1  and k 2  are implemented to reduce the current in the NMOS transistor N 122 . Reduction of the current in the NMOS transistor N 122  enables the W/L ratio WN 122 /L N122  to be reduced, thereby reducing the CN 122  capacitance. Reference to formula (7), supra, shows that reduction in the C N122  capacitance raises the pole p 2  frequency. The higher pole p 2  frequency enables zc to be increased in frequency, permitting a reduction in zero stabilizing resistor R 115  and zero stabilizing capacitor C 115  values.  
         [0028]     The architecture of the regulator circuit  100  results in the gate node of PMOS power transistor P 128  acting as a low impedance net due to the action of the diode-connected PMOS transistor P 126  according to the relation:  
               gm     P   ⁢           ⁢   126       =     a   *       2   *   Kp   *     I   L     *       W     P   ⁢           ⁢   128         L     P   ⁢           ⁢   128                       (   12   )             
 
         [0029]     The boost technique consists of increasing α, thereby increasing gm P126 . The third pole value can be expressed as a function of current load I L :  
               p   ⁢           ⁢   3     =       1     2   ⁢   Π       *   a   *         2   *   Kp   *       W     P   ⁢           ⁢   128         L     P   ⁢           ⁢   128                       ⁢       Cgs     P   ⁢           ⁢   128       +     Cgd     P   ⁢           ⁢   128             *       I   L                 (   13   )             
 
         [0030]     In formula (13), Cgs P128  is the gate-to-source capacitance of PMOS power transistor P 128  and Cgd P128  is the gate-to-drain capacitance of the PMOS power transistor P 128 .  
         [0031]     The PMOS power transistor P 128  operates in the saturation region, so the following relations apply:  
               Cgs     P   ⁢           ⁢   128       =       2   3     *   Cox   *     W     P   ⁢           ⁢   128       *     L     P   ⁢           ⁢   128                 (     14   ⁢           ⁢   A     )                 Cgd     P   ⁢           ⁢   128       =       1   3     *   Cox   *     W     P   ⁢           ⁢   128       *     L     P   ⁢           ⁢   128                 (     14   ⁢   B     )             
 
         [0032]     Applying formulae (14A) and (14B) to formula (13) gives:  
               p   ⁢           ⁢   3     =       1     2   ⁢   Π       *     a     Cox   *     L     P   ⁢           ⁢   128           *         2   *   Kp         W     P   ⁢           ⁢   128       +     L     P   ⁢           ⁢   128             *       I   L                 (   15   )             
 
         [0033]     Formula (15) shows that the third pole p 3  is an increasing function of the current load I L . The current ratio α is preferentially large enough to ensure p 3  is higher than the unity-gain frequency (UGF) of the open-loop, so that p 3  does not alter the regulator stability. Increasing the current ratio a requires a compromise between the phase margin and the current efficiency performance of the regulator circuit  100 .  
         [0034]     To recapitulate the analysis, supra, transfer function pole p 2 , zero zc, and pole pc have been shown to be independent of I L  by formulae (9), (10) , and (11) respectively. However, the dc gain G DC  is a function of  
       1       I   L           
 
 as shown by formula (6), and the dominant pole p 1  is a function of I L  as shown by formula (3). The unity gain frequency (UGF) of the open-loop varies with a factor of √{square root over (I L )} as:  
             UGF   =       (       G   DC     *   p   ⁢           ⁢   1     )     ⁢     (       p   ⁢           ⁢   2     zc     )               (   16   )             
 
         [0035]     Formula 16 implicitly shows that the unity gain frequency (UGF) and hence the regulator stability, depends on the current load I L . It becomes difficult to maintain stability when large variations in current load I L  are desired.  
         [0036]     What is needed, therefore, is a method of realizing a high performance regulator which takes advantage of CMOS fabrication processes in order to provide low noise, stable operation, and low-ripple voltage regulation without requiring tradeoffs between current efficiency and stability.  
       SUMMARY OF THE INVENTION  
       [0037]     The present invention is an apparatus and method for an improved voltage regulator. A low drop-out (LDO) regulator, fabricated in a standard CMOS process, with new dynamic compensation, low noise, high open-loop gain, and high PSRR is introduced in the present invention. The regulator has a small silicon area requirement because it uses a low value internal compensation capacitor. Moreover, the architecture stabilizes the regulator operation without altering the noise, power supply rejection ratio (PSRR), or quiescent current performance. The circuit architecture of the present invention makes a pole-zero doublet frequency and unity gain frequency (UGF) of the regulator vary at the same rate with respect to a current load I L ; in particular, the pole-zero doublet frequency and the unity gain frequency are made to vary in proportion to the square root of the load current (i.e., √{square root over (I L )}). The variation is accomplished by making a zero stabilizing resistor Rz and first stage amplifier gain a decreasing function of I L . The zero stabilizing resistor Rz is realized by means of an NMOS transistor having a gate terminal connected to a voltage which is dependent upon the current load I L . The control of the first stage amplifier gain is accomplished by means of a PMOS transistor P 214  ( FIG. 2 ) to source an additional bias current. The gate terminal of the PMOS transistor P 214  is connected to a potential which is dependent upon the current load I L . 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0038]      FIG. 1  is a circuit schematic of a low drop-out (LDO) regulator as known in the prior art.  
         [0039]      FIG. 2  is an exemplary circuit schematic of a low drop-out (LDO) regulator according to the present invention.  
         [0040]      FIG. 3  is a conceptual gain vs. frequency plot of a regulator circuit according to the present invention.  
         [0041]      FIG. 4  is a simulated frequency response plot of a regulator circuit in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0042]     With reference to  FIG. 2 , exemplary regulator circuit  200  comprises a first amplifier stage  210  and a second amplifier stage  220 . The first amplifier stage  210  comprises PMOS transistors P 212 , P 214 , P 216 , and P 218 . The first amplifier stage  210  further comprises a zero stabilizing capacitor C 215 , diode-connected NMOS transistor N 216 , resistor-like NMOS transistor N 215  and NMOS transistor N 218 . The second amplifier stage  220  comprises diode-connected PMOS transistors P 222  and P 226 , a PMOS transistor P 224 , a PMOS power transistor P 228 , a diode-connected NMOS transistor N 224 , and NMOS transistors N 222  and N 226 .  
         [0043]     The PMOS transistor P 212  has its source terminal coupled to a first power supply potential VDD, its gate terminal coupled to a constant bias potential, and its drain terminal coupled to a drain terminal of PMOS transistor P 214 . The drain terminal of PMOS transistor P 212  is further coupled to the source terminal of PMOS transistor P 216  and to the source terminal of PMOS transistor P 218 . The PMOS transistor P 214  has its source terminal coupled to the first power supply potential VDD, and its gate terminal coupled to the gate terminal of the PMOS transistor P 222  and to the gate terminal of the PMOS transistor P 224 .  
         [0044]     The PMOS transistor P 216  has its gate terminal coupled to an input control voltage node VIN, and its drain terminal coupled to the drain and to the gate terminal of the diode-connected NMOS transistor N 216 . The gate terminal of the diode-connected NMOS transistor P 216  is further coupled to the gate terminal of the NMOS transistor N 218 . Those skilled in the art will recognize that the diode-connected NMOS transistor N 216  and the NMOS transistor N 218  are configured to form a current mirror, which is characterized by a tendency to maintain a constant ratio of drain currents between the transistors comprising the current mirror. The PMOS transistor P 218  has its drain terminal coupled to the drain terminal of the NMOS transistor N 218 , to the gate terminal of the NMOS transistor N 222 , and to a first terminal of the zero stabilizing capacitor C 215 . The diode-connected NMOS transistor N 216 , the NMOS transistor N 218 , and the resistor-like NMOS transistor N 215  have their source terminals coupled to a second power supply potential GND. The resistor-like NMOS transistor N 215  has its drain terminal coupled to a second terminal of the zero stabilizing capacitor C 215 . The gate terminal of the resistor-like NMOS transistor N 215  is coupled to the gate terminal of the diode-connected NMOS transistor N 224  and to the gate terminal of the NMOS transistor N 226 .  
         [0045]     The source terminals of the diode-connected PMOS transistors P 222  and P 226 , the source terminal of PMOS transistor P 224 , and the source terminal of PMOS power transistor P 228  are coupled to the first power supply potential VDD. The drain terminal and the gate terminal of the diode-connected PMOS transistor P 222  are coupled to each other, to the gate terminal of the PMOS transistor P 224 , and to the drain terminal of the NMOS transistor N 222 . Skilled artisans will recognize that the diode-connected PMOS transistor P 222 , the PMOS transistor P 224 , and the PMOS transistor P 214  are configured in the form of a current mirror. In the analyses to follow infra, it is assumed that the current mirror ratio k 1  applies such that k 1 =W P224 /W P222 . Furthermore, a current mirror ratio k 3 =W P214 /W P222 =k 1 *W P214 /W P224  is assumed to apply.  
         [0046]     The gate terminal and the drain terminal of the diode-connected NMOS transistor N 224  are coupled to each other, to the drain terminal of the PMOS transistor P 224 , to the gate terminal of the NMOS transistor N 226 , and to the gate terminal of the resistor-like NMOS transistor N 215 . The source terminals of the NMOS transistor N 222 , the diode-connected NMOS transistor N 224 , and the NMOS transistor N 226  are coupled to the second power supply otential GND. Skilled artisans will recognize that the diode-connected NMOS transistor N 224 , the NMOS transistor N 226 , and the resistor-like NMOS transistor N 215  are configured in the form of a current mirror. In the analyses to follow infra, it is assumed that the current mirror ratio k 2  applies such that k 2 =W N226 /W N224 .  
         [0047]     The drain terminal and the gate terminal of the diode-connected PMOS transistor P 226  are coupled to each other, to the gate terminal of the PMOS power transistor P 228 , and to the drain terminal of the NMOS transistor N 226 . The drain terminal of the PMOS power transistor P 228  is coupled to the output controlled voltage node V OUT . The PMOS power transistor P 228  the diode-connected PMOS transistor P 226  are configured in the form of a current mirror. In the analyses to follow infra, it is assumed that the current ratio a applies such that α=W P226 /W P228 .  
         [0048]     The output controlled voltage node V OUT  is coupled to a first terminal of the resistor R 1 . A second terminal of the resistor R 1  is coupled to the gate terminal of the PMOS transistor P 218  and to a first terminal of the resistor R 2 . A second terminal of the resistor R 2  is coupled to the second power supply potential GND. The configuration of the resistors R 1  and R 2  creates a voltage divider circuit, with the input voltage terminal being the output controlled voltage node V OUT  and the divided voltage coupled to the gate terminal of the PMOS transistor P 218 . The divided voltage coupled to the gate terminal of the PMOS transistor P 218  provides a feedback signal into the first amplifier stage  210 .  
         [0049]     The decoupling capacitance C L  and an equivalent series resistance (ESR) R S  are coupled between the output controlled voltage node V OUT  and the second power supply potential GND. A first terminal of the equivalent series resistance (ESR) R S  is coupled to the output controlled voltage node V OUT  and a second terminal of the equivalent series resistance (ESR) R S  is coupled to a first terminal of the decoupling capacitance C L . A second terminal of the decoupling capacitance C L  is coupled to the second power supply potential GND. Those skilled in the art will appreciate that the equivalent series resistance (ESR) R S  may not be physically separate from the decoupling capacitance C L , but may represent a parasitic electrical characteristic resulting from physical attributes inherent to the decoupling capacitance C L  itself. The representation of the equivalent series resistance (ESR) R S  as a separate component facilitates design and analysis of the regulator circuit  200 .  
         [0050]     The current load I L  has a first terminal coupled to the controlled output voltage node V OUT  and a second terminal coupled to the second power supply potential VDD.  
         [0051]     Those skilled in the art will recognize that the resistors R 1  and R 2 , as well as the external decoupling capacitance C L  and its associated equivalent series resistance (ESR) R S , may be external to the voltage regulator  200 , or may be optionally integrated onto the same substrate, and even into the regulator circuit itself, by known techniques.  
         [0052]     A discussion and analysis of the architecture of the regulator circuit  200  is now presented for an exemplary embodiment of the present invention. A novel approach is to make the pole-zero doublet (pc, zc) and the unity-gain frequency (UGF) vary at the same rate of the current load I L . More specifically, the pole-zero doublet (pc, zc) and the unity-gain frequency (UGF) are made to vary in proportion to the square root of the current load I L  (i.e., √{square root over (I L )}). In order to provide the variation, the fixed-value zero stabilizing resistor R 115  ( FIG. 1 ) in the prior art, c.f., formulae (10) and (12), is made to vary with load current. The resistance variation with load current is accomplished in the present invention by the resistor-like NMOS transistor N 215  acting as a variable resistor. The gate terminal of the NMOS transistor N 224  exhibits a potential which depends on the value of the current load I L , to be shown infra, and is coupled to the gate terminal of the resistor-like NMOS transistor N 215  to provide control of the variable resistor action. The NMOS transistor N 226  operates in saturation and the following relation applies:  
                 Vgs     P   ⁢           ⁢   228       -   Vtn     =           2   ⁢   a   *     I   L           k   2     *     K   n         *       L     N   ⁢           ⁢   224         W     N   ⁢           ⁢   224                     (   17   )             
 
         [0053]     In formula (17), Vgs P228  represents the gate-to-source voltage of the PMOS power transistor P 228 , Vtn represents the threshold voltage for NMOS transistors, and α, k 2 , and k n  were introduced supra.  
         [0054]     The PMOS power transistor P 228  operates in the linear region, with an output conductance given by the relation:  
               gds     P   ⁢           ⁢   228       =       K   n     *       W     P   ⁢           ⁢   228         L     P   ⁢           ⁢   228         *     (       Vgs     P   ⁢           ⁢   228       -   Vtn     )               (   18   )             
 
         [0055]     Combination of formula (17) and formula (18) gives an expression for the resistance Rz presented by the NMOS transistor N 215 :  
             Rz   =       1     gds     P   ⁢           ⁢   228         =         L     P   ⁢           ⁢   228         W     P   ⁢           ⁢   228         *     1           L     N   ⁢           ⁢   224         W     N   ⁢           ⁢   224         *           ⁢       2   ⁢   a   *     K   n         k   2             *     1       I   L                     (   19   )             
 
         [0056]     Combining formula (19) and an analogous form of formula (10) gives an expression for the zero zc as an increasing function of I L :  
                   zc   =       1     2   ⁢   Π   *   C   ⁢           ⁢   215       *       W     P   ⁢           ⁢   228         L     P   ⁢           ⁢   228         *           L     N   ⁢           ⁢   224         W     N   ⁢           ⁢   224         *       2   ⁢   a   *     K   n         k   2           *       I   L                     =       1     2   ⁢   Π   *   C   ⁢           ⁢   215       ⁢   Tz   *       I   L                       (   20   )             
 
         [0057]     Formula (20) shows that the zero zc varies with the load current I L  at the desired rate in proportion to √{square root over (I L )}. The variable Tz is introduced as a simplification for writing the expression in a more compact form.  
         [0058]     The next attribute to be demonstrated for the present invention is the controlled dependence of the pole p 2  on the current load I L . The p 2  variation is introduced into the open-loop transfer function of the first amplifier stage  210 , by the PMOS transistor P 214 , which sources a fraction of the current load I L  into the first amplifier stage  210 . First, we consider a transconductance gm P218  of a differential pair formed by the PMOS transistors P 216  and P 218 :  
               gm     P   ⁢           ⁢   218       =           a   *     k   3           k   1     *     k   2           *       2   *     K   p     *     I   L     *       W     P   ⁢           ⁢   218         L     P   ⁢           ⁢   218                       (   21   )             
 
         [0059]     The output admittance of the first stage amplifier  210  is determined by addition of the admittances of the PMOS transistor P 218  and the NMOS transistor N 218  according to the relation:  
                 gd     P   ⁢           ⁢   218       +     gd     N   ⁢           ⁢   218         =       (       λ     P   ⁢           ⁢   218       +     λ     N   ⁢           ⁢   218         )     *       α   *   k   ⁢           ⁢   3       k   ⁢           ⁢   1   *   k   ⁢           ⁢   2       *     I   L               (   22   )             
 
         [0060]     In formula (22), λ P218  represents the channel modulation parameter for the PMOS transistor P 218  and λ N218  represents the channel modulation parameter for the NMOS transistor N 218 . Furthermore, as described supra, k 3  is the ratio of the device widths for the PMOS transistors P 222  and P 214  such that k 3 *W P222 =W P214 .  
         [0061]     In an exemplary embodiment of the present invention, the resistance Rz is designed such that: 
 
 Rz *( gd   P218   +gd   N218 )&lt;&lt;1  (23) 
 
         [0062]     In the exemplary embodiment formula (23) is valid for all values of the current load I L . When formula (23) is valid, formulae (9) and (11) can be simplified by application of formula (22) giving:  
               p   ⁢           ⁢   2     =       2     2   Π       *         λ     P   ⁢           ⁢   218       +     λ     N   ⁢           ⁢   218             C   ⁢           ⁢   215     +     C     N   ⁢           ⁢   222           *       α   *     k   3           k   1     *     k   2         *     I   L               (   24   )                 pc   zc     =         C   ⁢           ⁢   215       C     N   ⁢           ⁢   222         +   1             (   25   )             
 
         [0063]     A digression is now made to  FIG. 3 , a conceptual gain vs. frequency plot  300  for the regulator circuit  200  according to an exemplary embodiment of the present invention. Conceptual gain vs. frequency plot  300  includes a gain vs. frequency response line  310 A corresponding to a current load I L1  and a gain vs. frequency response line  310 B corresponding to a current load I L2  such that I L2 &gt;I L1 . The arrow  310 C indicates a relative shift in the dc gain GDC as a function of increasing load current. Initial positions  320 A- 320 E indicate locations of pole p 1 , pole p 2 , zero zc, unity gain frequency (UGF), and pole pc respectively, all corresponding to the current load I L1 . Arrows  330 A- 330 E indicate respective motions of pole p 1 , pole p 2 , zero zc, unity gain frequency (UGF), and pole pc, respectively, as the load current increases from I L1  to I L2 . Final positions  340 A- 340 E indicate locations of pole p 1 , pole p 2 , zero zc, unity gain frequency (UGF), and pole pc respectively, corresponding to the current load I L2 .  
         [0064]     Reference to formulae (24), (25), and to  FIG. 3  shows that the pole p 2  is a function of the current load I L , and that a splitting ratio pc/zc, associated with the pole-zero doublet (pc, zc), is independent of the current load I L , but depends predominantly on the capacitance ratio C 115 /C N222 . As discussed in the first journal publication by Gabriel A. Rincon-Mora and Phillip E. Allen, the gain-bandwidth product of the first amplifier stage  210 ,  
         (         gm     P   ⁢           ⁢   218           gd     P   ⁢           ⁢   218       +     gd     N   ⁢           ⁢   218           *   p   ⁢           ⁢   2     )     ,       
 
 is a function of √{square root over (I L )}. Since the dc gain of the first amplifier stage  210  decreases with increasing load current, the power supply rejection ratio (PSRR) as a function of frequency is improved from the prior art regulator circuit  100 . 
 
         [0065]     Using formulae (21) and (22), the DC gain may be written as a function of the current load:  
               G   DC     =             k   1     *     k   2         α   *     k   3           *       2   *     K   p     *       W     P   ⁢           ⁢   218         L     P   ⁢           ⁢   218             *     1       λ     P   ⁢           ⁢   218       +     λ     N   ⁢           ⁢   218           *         2   *     K   n     *         k   1     *     k   2       α     *       W     N   ⁢           ⁢   222         L   N222           λ     *       R   ⁢           ⁢   1       R   ⁢           ⁢   2       *     1     I   L                 (   26   )             
 
         [0066]     By substitution of formulae (26), (3), (20), and (24) into formula (16), the unity gain frequency (UGF) of the exemplary regulator circuit  200  open-loop transfer function can be written as:  
             UGF   =         C   ⁢           ⁢   215         2   Π     *     C   L         *         α   *     k   3           k   1     *     k   2           *       2   *     K   p     *       W     P   ⁢           ⁢   218         L     P   ⁢           ⁢   218             *       2   *     K   n     *         k   1     *     k   2       α     *       W     N   ⁢           ⁢   222         L     N   ⁢           ⁢   222             *       R   ⁢           ⁢   2         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2         *     1   Tz     *     1       C   ⁢           ⁢   215     +     C     N   ⁢           ⁢   222           *       I   L                 (   27   )             
 
         [0067]     Formula (27) demonstrates that the variation of the unity gain frequency (UGF) with current load I L  is in proportion to the square root of the current, √{square root over (I L )}, matching the variation of the introduced pole-zero doublet (pc, zc).  
         [0068]     The phase margin (PM) for the regulator circuit  200  is independent of the current load I 230  and can be expressed as:  
                   PM   =       arc   ⁢           ⁢   tan   ⁢           ⁢     (     UGF   zc     )       -     arc   ⁢           ⁢   tan   ⁢           ⁢     (     UGF   pc     )                     =     arc   ⁢           ⁢   tan   ⁢           ⁢     (       UGF   *     (     pc   -   zc     )           zc   *   pc     +     UGF   2         )                     (   28   )             
 
         [0069]     An analysis of the phase margin (PM) as a function of the unity gain frequency (UGF) gives an optimal (i.e., maximum) phase margin when:  
             UGF   =         zc   *   pc       =     zc   *           C   ⁢           ⁢   215       C     N   ⁢           ⁢   222         +   1                   (   29   )             
 
         [0070]     The conditions for optimal phase margin can be calculated for the W/L ratio of the PMOS power transistor P 224 , W P224 /L P224 , by equating formulae (27) and (29) and applying formula (20). The ratio W P224 /L P224  is independent of λ P218  and λ N218 , permitting reduction of λ P218 +λ N218  to ensure that the condition required by formula (23) is satisfied, regardless of the current load I L . Substitution of formula (29) into formula (28) gives:  
             PM   =     arc   ⁢           ⁢   tan   ⁢           ⁢     (       1   2     *           C   ⁢           ⁢   215       C     N   ⁢           ⁢   222         *       C   ⁢           ⁢   215         C   ⁢           ⁢   215     +     C     N   ⁢           ⁢   222                 )               (   30   )             
 
         [0071]     The phase margin PM is a monolithic increasing function of zero stabilizing capacitor C 215 . The value of zero stabilizing capacitor C 215  is chosen as large as possible, consistent with meeting the power supply rejection ratio (PSRR) requirement for the regulator circuit. Selection of zero stabilizing capacitor C 215  as large as possible establishes the best compromise between regulator stability and PSRR performance. As an example, if the ratio C 215 /C N222  equals 10, then application of formula (30) predicts a phase margin (PM) of 60 degrees.  
         [0072]     With reference to  FIG. 4 , a simulated frequency response plot of the exemplary regulator circuit  200  according to the present invention comprises a gain versus frequency plot  410  and a phase versus frequency plot  420 . Frequency response predictions of the type in  FIG. 4  are commonly performed using a variety of circuit simulation tools familiar to those skilled in the art. A gain versus frequency curve  412  is the simulation prediction for the regulator circuit  200  response when supplying a current load equal to 1 mA. A gain versus frequency curve  414  is the simulation prediction for the exemplary regulator circuit  200  response when supplying a current load equal to 10 mA. A gain versus frequency curve  416  is the simulation prediction for the regulator circuit  200  response when supplying a current load equal to 100 mA. A phase shift versus frequency curve  422  is the simulation prediction for the exemplary regulator circuit  200  response when supplying a current load equal to 1 mA. A phase shift versus frequency curve  424  is the simulation prediction for the exemplary regulator circuit  200  response when supplying a current load equal to 10 mA. A phase shift versus frequency curve  426  is the simulation prediction for the exemplary regulator circuit  200  response when supplying a current load equal to 100 mA.  
         [0073]     A comparison of simulated and experimentally measured performance for the exemplary regulator circuit  200  is summarized in the following table:  
                                                                             Simulated   Measured           Parameter   Conditions   Results   results   Unit                                Output       2.85   2.85   V       voltage       Quiescent   I L  = 0 mA   32   35   μA       Current   I L  &gt; 10 mA   0.7% of   1% of               Iload   Iload       20 kHz   VDD = 3.6 V   −64   −62   dB       Power   I L  = 100 mA       Supply   VDD = 3.2 V   −58   −55       Rejection   I L  = 100 mA       100 kHz   VDD = 3.6 V   −61   −59   dB       Power   I L  = 100 mA       Supply   VDD = 3.2 V   −55   −52       Rejection   I L  = 100 mA       Output   BW:   25   26   μV rms         Noise   10 Hz to 100 kHz       (filtered       bandgap       included)                  
 
         [0074]     In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident to a skilled artisan that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, the first and second amplifier stages may be integrated onto a single substrate, or they may be optionally fabricated as separately packaged circuit components. Other components, e.g., the resistive divider or decoupling capacitance, may optionally be included with the fabricated regulator circuit, or may be provided separately. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.