Abstract:
A method for sampling data is disclosed. The method includes providing a first data and a second data, detecting a phase of the first data by a first clock, and sampling the second data by an inverted signal of the first clock.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a clock and data recovery circuit, and more particularly, to a clock and data recovery circuit utilizing an input data frequency divider to divide the frequency of the input data for lowering the clock rate and related method thereof.  
         [0003]     2. Description of the Prior Art  
         [0004]     The data stream received by a receiver is asynchronous. For subsequent processing, timing information, such as a clock, must be extracted from the data so as to allow synchronous operations. Furthermore, the data must be retimed such that the jitter accumulated during transmission is removed. The task of clock extraction and data retiming is called “clock and data recovery”. Clock and data recovery circuits must satisfy stringent specifications defined by related receiver standards, presenting difficult challenges to system and circuit designs.  
         [0005]     The clock and data recovery circuit and the method for clock and data recovery can be used for many applications, e.g. for synchronous optical networks (SONET), synchronous digital hierarchic networks (SDH), networks operated in a synchronous transfer mode (ATM), local area networks (LAN), plesiochronous digital hierarchic networks (PDH), or serial-link applications such as SATA interface or PCI-Express interface.  
         [0006]     Please refer to  FIG. 1 .  FIG. 1  is a waveform diagram illustrating operation of prior art clock and data recovery. Please note that the input data D in B shown in  FIG. 1  is an inverted signal of the input data D in , and both data, D in  and D in B, come from a common signal source. As shown in  FIG. 1 , the recovered clocks CK Q  and CK QB  are utilized to sample the input data D in  to obtain the recovered data D out , for example, D[0]−D[3] for input data D in  and D[0]B−D[3]B for the input data D in B. The other recovered clocks CK I  and CK IB  are utilized to detect the phase relationship between the input data D in  and the recovered clocks CK I , and CK IB . Additionally, suppose that the data rate of the input data D in , D in B is 2.5 Gbps. The clock rate of each recovered clock CK I , CK IB , CK Q , CK QB  should be 1.25 Ghz.  
         [0007]     Please refer to  FIG. 2  in conjunction with  FIG. 1 .  FIG. 2  shows a prior art clock and data recovery circuit  100 . The clock and data recovery circuit  100  performs two main tasks. The first task is utilizing this system to recover input data, and the second task is recovering the system clock. As shown in  FIG. 2 , the clock and data recovery circuit  100  includes a decision circuit  110 , a phase detection unit  120 , a loop filter  130 , a phase shifter  140 , and a clock source  150 . The clock and data recovery circuit  100  utilizes the phase detection unit  120  to sample an input data D in  according to recovered clocks CK I , and CK IB  generated from the phase shifter  140 , and then converts the input data D in  into an error signal E r  having phase error values associated with the aforementioned recovered clocks. The operation of phase detection is illustrated in  FIG. 1 . Furthermore, it should be noted that recovered clock CK IB  is an inverted signal of the recovered clock signal CK I , and recovered clock CK QB  is an inverted signal of the recovered clock signal CK Q . Additionally, the recovered clocks CK I , CK Q , CK IB , and CK QB  correspond to four different phases. Next, the loop filter  130  filters the error signal E r  to generate a control signal C. The clock source  150 , which can be a phase-locked loop (PLL) or a delay-locked loop (DLL), is implemented to provide the phase shifter  140  with a reference clock CLK ref . By referring to the control signal C outputted from the loop filter  130 , the phase shifter  140  is able to generate the recovered clocks CK I , CK Q , CK IB , and CK QB . Then, referring to  FIG. 1 , the decision circuit  110  utilizes the recovered clocks CK Q  and CK QB  to sample the input data D in  to obtain the recovered data D out .  
         [0008]     The prior art clock and data recovery circuit  100  has two shortcomings. The architecture shown in  FIG. 2  does not utilize all of the recovered clocks for either of phase detection and data recovery. As described above, the recovered clocks CK Q  and CK QB  are utilized to sample the input data D in , while the recovered clocks CK I  and CK IB  are utilized to detect the phase relationship between the input data D in  and the recovered clocks CK I  and CK IB . The other shortcoming is that the clock frequency has to be maintained at a high operating frequency to match the high data rate of the input data D in . This means the system requires a high operating frequency controllable oscillator (e.g. voltage-controlled oscillator) in the PLL (i.e. the clock source  150 ) to provide the desired high-speed clock rate. In addition, the high-speed data rate will increase the difficulty in designing the clock and data recovery circuit  100 .  
       SUMMARY OF THE INVENTION  
       [0009]     One objective of the claimed invention is therefore to provide a clock and data recovery circuit utilizing an input data frequency divider to divide the frequency of the input data for lowering the clock rate and related method thereof, to solve the above-mentioned problems.  
         [0010]     According to an embodiment of the claimed invention, a method for sampling data is disclosed. The method includes: providing a first data and a second data; detecting a phase of the first data by a first clock while the clock is sampling the second data.  
         [0011]     In addition, the claimed invention further provides a circuit for sampling data. The circuit includes a data provider providing a first data and a second data; a clock provider providing a first clock and a second clock; a phase detection unit coupled to the data provider and the clock provider, the phase detection unit detecting a phase of the first data by the first clock, and detecting a phase of the second data by the second clock; and a decision circuit coupled to the data provider and the clock provider, the decision circuit sampling the first data by the second clock, and sampling the second data by the first clock.  
         [0012]     This invention provides a method and apparatus to lower the clock rate of the clock and data recovery circuit. Compared with the prior art, the clock and data recovery circuit of the present invention can enable the decision circuit and the clock recovery loop circuits to operate at a lower clock rate since the input data frequency is lowered by the input data frequency divider. In this way, the complexity of the clock and data recovery circuit is greatly reduced because the required clock rate of the circuits is reduced.  
         [0013]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIG. 1  is a waveform diagram illustrating operation of prior art clock and data recovery.  
         [0015]      FIG. 2  shows a prior art clock and data recovery circuit.  
         [0016]      FIG. 3  is a waveform diagram illustrating operation of a clock and data recovery according to the present invention.  
         [0017]      FIG. 4  is a diagram of a clock and data recovery circuit according to an embodiment of the present invention.  
         [0018]      FIG. 5  is a diagram of an embodiment of an input data frequency divider shown in  FIG. 4 .  
         [0019]      FIG. 6  is a circuit diagram illustrating an embodiment of a decision circuit shown in  FIG. 4 .  
         [0020]      FIG. 7  is a flowchart illustrating a clock and data recovery method according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0021]     Please refer to  FIG. 3 .  FIG. 3  is a waveform diagram illustrating operation of the clock and data recovery according to the present invention. In this embodiment, all of the recovered clocks CK I ′, CK Q ′, CK IB ′, CK QB ′ are used in a phase detection operation to detect the phase relationship between the recovered clocks CK I ′, CK Q ′, CK IB ′, CK QB ′ and the first and the second adjusted data Data_rising, Data_falling. The recovered clocks CK I ′ and CK IB ′ are used to detect the phase error of the first adjusted data Data_rising. The recovered clocks CK Q ′ and CK QB ′ are used to detect the phase error of the second adjusted data Data_falling. In addition, all of the recovered clocks CK I ′, CK Q ′, CK IB ′, CK QB ′ are used in a data recovery operation to generate the recovered data D out ′. In short, in contrast to the prior art using part of the recovered clocks, the present invention uses the recovered clocks in an efficient way. In addition, in this embodiment the first and the second adjusted data Data_rising, Data_falling are generated by dividing frequency of an input data. Therefore, suppose that the data rate of the input data is 2.5 Gbps. With the help of the input data frequency dividing operation, the date rate of the first adjusted input data Data_rising becomes 1.25 Gbps, and the date rate of the second adjusted input data Data_falling becomes 1.25 Gbps. As a result, the clock rate of each recovered clock CK I ′, CK IB ′, CK Q ′, CK QB ′ is only 625 Mhz. Compared with the prior art clock and data recovery circuit demanding the clock rate of 1.25 Ghz, the clock rate of the present invention is lowered. The detailed operation of the clock and data recovery scheme of the present invention is described as below.  
         [0022]     Please refer to  FIG. 4 .  FIG. 4  is a diagram of a clock and data recovery circuit  200  according to an embodiment of the present invention. The clock and data recovery circuit  200  is used for generating recovered clocks that are locked to the adjusted input data D in ″ and for recovering the input data D in ′. As shown in  FIG. 4 , the clock and data recovery circuit  200  includes a decision circuit  210 , a phase detection unit  220 , a loop filter  230 , a phase shifter  240 , a clock source  250 , and an input data frequency divider  260 . The input data frequency divider  260 , coupled to the input data D in ′, serves as a data provider and is used for dividing the frequency of the input data D in ′ to generate an adjusted input data D in ″, where the operation of the input data frequency divider  260  is detailed later. The phase detection unit  220 , coupled to the input data frequency divider  260 , is used for generating a phase error signal E r ′ representing a phase error between the adjusted input data D in ″ and recovered clocks CK I ′, CK Q ′, CK IB ′, CK QB ′. It should be noted that recovered clock CK IB ′ is an inverted signal of the recovered clock signal CK I ′, and recovered clock CK QB ′ is an inverted signal of the recovered clock signal CK Q ′. Additionally, the recovered clocks CK I ′, CK Q ′, CK IB ′, and CK QB ′ correspond to four different phases. The loop filter  230 , coupled to the phase detection unit  220 , is used for filtering the phase error signal E r ′ and generating a control signal C′. The phase shifter  240 , coupled to the loop filter  230 , the clock source  250 , the decision circuit  210  and the phase detection unit  220 , serves as a clock provider and is used for generating the desired recovered clocks CK I ′, CK Q ′, CK IB ′, and CK QB ′ by phase-shifting a reference clock CLK ref ′ according to the control signal C′. The clock source  250 , coupled to the phase shifter  240 , is used for generating the reference clock CLK ref ′. The decision circuit  210 , coupled to the input data frequency divider  260  and the phase shifter  240 , is used for generating a recovered data D out ′ according to the adjusted input data D in ″ and the recovered clocks CK I ′, CK Q ′, CK IB ′, and CK QB ′. Please note that in this embodiment the clock source  250  can be implemented by a phase-locked loop (PLL) or a delay-locked loop (DLL). However, these implementations are not meant to be limitations of the present invention.  
         [0023]     In the embodiment shown in  FIG. 4 , the key component is the input data frequency divider  260 . Compared with the prior art clock and data recovery circuit  100  shown in  FIG. 2 , this invention utilizes the input data frequency divider  260  to lower the clock rate needed by the clock and data recovery circuit  200 . The main objective of this invention is to implement an input data frequency divider  260  to lower the frequency of the input data D in ′ for the following signal processing, thereby simplifying the circuit design of the next stage.  
         [0024]     Please refer to  FIG. 5 .  FIG. 5  is a diagram of an embodiment of the input data frequency divider  260  shown in  FIG. 4 . In this embodiment, the input data frequency divider  260  includes a first D flip-flop (DFF)  330 , a second D flip-flop  340 , a first AND gate  310 , a second AND gate  320  and a combination logic  350 . The input data D in ′ of the clock and data recovery circuit  200  is usually a differential data including a first data Data and a second data DataB. It should be noted that the second data DataB is an inverted signal of the first data Data, and both the first data Data and the second data DataB come from a common signal source. The first data Data and the second data DataB are separately processed to generate the aforementioned adjusted output data D in ″ including a first adjusted data Data_rising associated with the first data Data, and a second adjusted data Data_falling associated with the second data DataB. The generation of the first adjusted data Data_rising and the second adjusted data Data_falling and the operation of the input data frequency divider  260  is detailed as follows.  
         [0025]     The combination logic  350  can operate as an XOR gate or an XNOR gate. The combination logic  350  has a first input node A coupled to the non-inverted data output node Q of the first DFF  330 ; a second input node B coupled to the non-inverted data output node Q of the second DFF  340 ; a first output node R; and a second output node S. The combination logic  350  generates an output at the first output node R by XNORing inputs at the first and second input nodes A, B and generates an output at the second output node S by XORing inputs at the first and second input nodes A, B.  
         [0026]     The first AND gate  310  performs an AND logic operation upon the first data Data and the output at the first output node R of the combination logic  350 , and then outputs a result to the clock input node CK of the first DFF  330 . In other words, the first DFF  330  is triggered by “riging” edges of the first data Data, thereby generating the desired first adjusted data Data_rising. The second AND gate  320  performs an AND logic operation upon the second data DataB and an output at the second output node S of the combination logic  350 , and then outputs a result to the clock input node CK of the second DFF  340 . In other words, the second DFF  340  is triggered by “rising” edges of the second data DataB, thereby generating the desired second adjusted data Data_falling. Please note that, the first adjusted data Data_rising and the second adjusted data Data_falling are generated according to the first data Data and the second data DataB, respectively. The second adjusted data Data_falling should not regard as an inverted signal of the first adjusted data Data_rising.  
         [0027]     As shown in  FIG. 5 , the inverted data output node QB is connected to the data input node D in both DFFs  330  and  340 . In other words, both DFFs  330 ,  340  act as a frequency divider with a frequency-dividing factor equaling two. Therefore, the frequency of the input data D in ′ is twice that of either of the first adjusted data Data_rising and the second adjusted data Data_falling through the utilization of the first and the second DFFs  330  and  340 . It should be noted that the adjusted input data D in ″ consists of the first adjusted data Data_rising and the second adjusted data Data_falling each having the frequency half that of the input data D in ′. However, the data rate of the adjusted input data D in ″ is equivalent to that of the input data D in ′.  
         [0028]     Please note that the implementation of the first and second AND gates  310 ,  320  and the combination logic  350  is for making the first and the second adjusted data Data_rising, Data_falling correctly represent the input data (i.e., Data and DataB). And these circuits (i.e., AND gates  310 ,  320  and combination logic  350 ) can be implemented in any similar or equivalent logic. But these implementations are not meant to be limitations of the present invention.  
         [0029]     Please refer to  FIG. 6  in conjunction with  FIG. 3 .  FIG. 6  is an embodiment of the decision circuit  210  shown in  FIG. 4 . The decision circuit  210  includes a plurality of DFFs  212   a - 212   h  and a plurality of combination logics  214   a - 214   d . The operation of the DFFs  212   a - 212   h  and combination logics  214   a - 214   d  has been detailed above, and further description is omitted for brevity. As shown in  FIG. 3 , the first adjusted data Data_rising is sampled at rising edges of the recovered clock CK Q ′ to obtain D[0]_pre and D[4]_pre sequentially. In addition, the first adjusted data Data_rising is further sampled at the rising edge of the recovered clock CK QB ′ to obtain D[2]_pre. As to the second adjusted data Data_falling, it is sampled at rising edges of the recovered clocks CK IB ′ and CK I ′ to obtain D[1]_pre and D[3]_pre, respectively. Then, the combination logics  214   a - 214   d  process the outputs of the DFFs  212   a ,  212   b ,  212   d ,  212   f ,  212   f  to successfully get the desired recovered data D[0]-D[3] and D[0]B-D[3]B.  
         [0030]     Please refer to  FIG. 7 .  FIG. 7  is a flowchart illustrating a clock and data recovery method according to an embodiment of the present invention. The clock and data recovery method is performed by the aforementioned clock and data recovery circuit  200 , and is summarized as follows.  
         [0031]     Step  500 : Divide the frequency of input data to generate adjusted input data;  
         [0032]     Step  502 : Generate a phase error signal representing a phase error between the adjusted input data and recovered clocks;  
         [0033]     Step  504 : Filter a phase error signal and generate a control signal;  
         [0034]     Step  506 : Phase-shift a reference clock to generate recovered clocks according to the control signal; and  
         [0035]     Step  508 : Generate a recovered data according to adjusted input data and recovered clocks.  
         [0036]     It should be noted that the clock and data recovery method is performed by the aforementioned clock and data recovery circuit  200  and the detailed operations associated with phase detection and data recovery are clearly illustrated in above paragraphs and corresponding figures. Therefore, further description is omitted for brevity.  
         [0037]     This invention provides a method and apparatus to lower the clock rate required by the clock and data recovery circuit. Compared with the prior art, the clock and data recovery circuit of the present invention can enable the decision circuit and the clock recovery loop circuits to operate at a lower clock rate since the input data is processed by the input data frequency divider to generate adjusted input data of lower frequency. In this way, the complexity of the clock and data recovery circuit is greatly reduced because the required clock rate of the circuits is reduced.  
         [0038]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.