Abstract:
A power supply noise compensation amplifier has an input for connection to a power supply. The amplifier includes a differential amplifier circuit for providing an instantaneous amplified signal in response to power supply noise, and produces an output signal with an instantaneous opposite polarity from the power supply noise so a noise sensitive circuit connected to the noise compensation amplifier has a compensated power supply signal which enables it to produce a reduction in the amplitude of the noise signal at the output thereof. The differential amplifier circuit includes a differential pair of coupled transistor circuits including a leading transistor circuit and a lagging transistor circuit. The leading and lagging transistor circuits have source-drain circuits connected in parallel to the source-drain circuit of a constant current transistor so the leading and lagging transistor circuits must share a common current as a function of voltages on the leading node connected to the gate of the leading transistor and a lagging node connected to the gate of the lagging transistor. The leading transistor circuit includes a first FET transistor having leading node connected to both and the gate electrode thereof and a resistive circuit. The lagging transistor circuit includes a lagging FET transistor having a lagging node connected to both the gate electrode thereof and the resistive and capacitive elements, and the differential amplifier circuit includes a differential pair of coupled transistor circuits including a leading transistor circuit and a lagging transistor circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to electronic circuits connected to power supplies which produce noisy outputs and more particularly to circuits for reducing the noise introduced by the power supply. 
     2. Description of Related Art 
     To some degree, almost all electronic circuits are susceptible to noise on their power supply or ground input lines. 
     FIG. 1 shows a typical prior art system  10  including a supply voltage VDD input connected through a terminal via line  60  and line  63  to the power supply input of a typical VDD Noise Sensitive Circuit (NSC)  11 . The NSC  11  is also connected by lines  66  and  64  to ground (reference potential) connection of the VDD power supply to complete to the power supply circuit connection as will be well understood by those skilled in the art. Unfortunately, the power supply voltage includes a noise signal NS which is an unwanted component included with the direct current voltage VDD. A control circuit  12  is also included in system  10 . The control circuit  12  is connected to receive power from the power supply through the lines  62  and  60 . The ground of the control circuit  62  is connected by lines  65  and  64  to ground (reference potential) to complete the connections to the power supply. The control circuit provides control signals on output line  52  connected to an input of the NSC  11 . 
     The typical VDD noise sensitive circuit  11  is sensitive to an unwanted input noise signal NS which is representative of certain frequencies included with the Direct Current (DC) power supply voltage VDD on line  60  which cause an unacceptable operational problem for the NSC  11 . For example, in FIG. 1, the output signal OS is shown on the output line  9  from NSC  11 . Thus the output signal OS from the NSC  11  is noisy and in many applications, the noise must be substantially reduced in amplitude for the output signal OS to meet specifications. 
     In summary the noise NS received by control circuit  12  and noise sensitive circuit  11  has an unwanted harmful effect on the typical noise sensitive circuit  11  producing an output noise signal OS along with the output signal from circuit  11  on line  9 . 
     FIG. 2 is a modification of the electrical schematic diagram of FIG. 1 which shows a prior art method for combating the noise sensitivity problem by adding a decoupling capacitor  15  across to the power supply to reduce the noise output signal OS′ on output line  9 . The capacitor  15  can filter out the noise by providing an effective short circuit for the Alternating Current (AC) component of the noise. The upper plate of the capacitor  15  is connected by line  61  to line  60  to the power supply. The lower plate of capacitor  15  is connected by line  67  via to line  64  to ground completing the power supply capacitor circuit. However, when the circuit of FIG. 2 is embodied on a small microchip the decoupling capacitor  15  can consume too much area on the surface of the small microchip. 
     FIG. 3 is a modification of the electrical schematic diagram of FIG. 2 which shows a prior art method in which there are dual output lines  52 ′/ 52 ″ in place of the single output line  52  in FIG.  2 . 
     Other prior art approaches to combating the noise sensitivity problem require signal processing or filtering of the output of the affected circuit, which can be very complicated and costly. 
     U.S. Pat. No. 4,630,104 of Nakagaki et al for “Circuit Arrangement for Removing Noise of a Color Video Signal” describes apparatus for color video signal processing to separate noise in a color video signal from the output, then subtract it from the color video signal output. This reference is not directed to solving the problem of power supply noise. A luminance signal and a chroma signal of a color video signal are processed to generate a first signal and a second signal, respectively. The first signal indicates the contour line of images represented by the video signal. The second signal includes noise included in the chroma signal and a signal component having an amplitude substantially equal to the peak to peak value of the noise. The first and second signals are fed to either a switching circuit or a multiplier so that a resultant output signal having only the noise is obtained. The noise components are then subtracted, by way of a subtractor, from the chroma signal so that a chroma signal having no noise will be obtained. 
     U.S. Pat. No. 4,475,215 of Gutleber entitled “Pulse Interference Cancelling System for Spread Spectrum Signals Utilizing Active Coherent Detection” describes a pulse interference canceling system for spread spectrum signals utilized in a digital noise coded communications system. A noise coded signal that is phase shifted by 180° is added to the original to cancel noise and to recover the coded signal. The system includes first and second noise coded signal channels located in a noise coded signal receiver which also includes a demultiplexer for providing a pair of received noise coded signals which were initially generated, multiplexed and transmitted to the receiver. First and second coherent detectors are coupled to both signal channels, the first being directly coupled thereto so that no signal delay exists. The second is coupled to the two signal channels with respective first and second variable time delay circuits having a delay substantially equal to the bit width of each digital code as well as a vernier delay which is adapted to delay the phase of any received pulse interference in the respective channel so that it is exactly 180° out of phase with the same undelayed pulse interference. Signal summing means are coupled to the outputs of the two coherent detectors which operate to completely cancel the interference pulse signal while leaving the desired noise coded signal at its peak amplitude. 
     U.S. Pat. No. 6,052,420 of Yeap et al. entitled “Adaptive Multiple Sub-band Common-mode RFI Suppression” uses a common mode signal to estimate noise in narrow frequency band. The estimate is subtracted from the original signal. A noise suppression circuit for a two wire communications channel comprising a hybrid device, e.g. a hybrid transformer or circuit, which provides a differential mode signal corresponding to a differential signal received from the channel. A summing device extracts from the channel wires a common mode signal that it supplies to a noise estimation unit that derives a common mode signal as an estimate of a noise level in a frequency band having a bandwidth narrower than an operating channel bandwidth. The noise estimation unit adjusts the amplitude of the noise estimate to correspond to the residual noise in the differential mode signal and subtracts it from the differential mode signal to produce a noise-suppressed output signal. A noise detection and control unit scans the operating band, identifies a frequency band having a highest noise level, and sets the noise estimation unit to the detected noisy band. The noise estimation unit suppresses the noise in that band. Preferably, the noise estimation unit comprises several channels, with a tunable filter, a phase shifter and an amplifier, and the noise detection and control unit sets the channels, in succession, to different frequency bands in descending order of noise level. The noise detection and control unit may cross-correlate the common mode signal and the noise-suppressed output signal and adjust the amplification of the noise estimation signal to reduce residual differential mode noise towards zero. 
     U.S. Pat. No. 6,061,456 of Andrea entitled “Noise Cancellation Apparatus” discloses a transducer for an acoustic noise cancellation apparatus for reducing background noise using microphones and amplifiers. The transducer includes a housing with first microphone for receiving a first acoustic sound, composed mainly of speech and background noise, that converts the first acoustic sound to a first signal. A second microphone is arranged at an angle, close to the first microphone to receive a second acoustic sound, composed mainly of the background noise, that converts the second acoustic sound to a second signal. The first and second microphones are connected to a differential amplifier of the noise cancellation apparatus to obtain a signal mainly representing speech. The amplifier is receives acoustic sounds from each microphone and has a first terminal and a second terminal. The second terminal is grounded. The transducer receives and amplifies an AC signal representative of the audio input from each microphone; and filters out the amplified AC signal from the DC signal. The DC signal powers the amplifier. A method for calibrating an active noise reduction apparatus includes use of a housing having a speaker to produce an acoustic anti-noise signal in the housing. A microphone detects an external noise signal, and amplitude adjustment calibrates the acoustic anti-noise signal creating a quiet zone in the housing for operation with an independent electrical assembly. The apparatus is calibrated separately from the electrical assembly. The method includes the steps of: inputting the external noise signal received by the microphone to produce an anti-noise signal. The anti-noise signal is transmitted to the speaker with an equal gain and an opposite phase response from the external noise signal detected by the microphone. The gain and phase response of the anti-noise signal are balanced by the amplitude adjustment located in the noise reduction apparatus to match the gain and phase response of the external noise signal to yield a theoretical zero in the quiet zone. 
     U.S. Pat. No. 5,907,624 of Taxidea entitled “Noise Canceler Capable of Switching Noise Canceling Characteristics” describes an acoustic noise canceler which switches noise canceling characteristic on detecting narrow band noise, and which cancels narrow band noise adequately. The noise canceler selects an output signal with a particular noise canceling characteristic, depending on whether or not a speech signal contained in an input acoustic signal is voiced. Also, the noise canceler adaptively changes, for an acoustic signal containing voiced sound, a window function that regulates the depth of a valley of an attenuation characteristic meant for the acoustic signal. The noise canceler improves an output signal with respect to the auditory sense and sound quality without regard to narrow band noise. 
     SUMMARY OF THE INVENTION 
     It is an object of this invention to diminish the effects of noise within a certain bandwidth by converting the noise to a control current that is fed into the affected circuit with an opposite polarity from the polarity of the noise. 
     In accordance with this invention, apparatus for compensating for power supply noise comprises a noise compensation amplifier with a power supply input for connection to a power supply. The amplifier provides an instantaneous amplified signal in response to power supply noise with an opposite polarity from the power supply noise. The noise compensation amplifier provides the noise sensitive circuit with a compensated power supply signal which enables it to produce a reduction in the amplitude of the noise signal at the output thereof. 
     Preferably, the amplifier includes a differential pair of coupled transistor circuits including a leading transistor circuit and a lagging transistor circuit. 
     Preferably, the leading and lagging transistor circuits have source-drain circuits connected in parallel to the source-drain circuit of a constant current transistor, whereby the leading and lagging transistor circuits share a common current as a function of voltages on the leading node connected to the gate of the leading transistor and a lagging node connected to the gate of the lagging transistor. 
     Preferably, the differential pair of coupled transistor circuits each have the source/drain circuits thereof connected in series with a transistor source/drain circuit connected to the power supply input; or the differential pair of coupled transistor circuits each have the source/drain circuit thereof connected in series with a resistor connected to the power supply input. 
     Preferably the amplifier includes a differential pair of coupled transistor circuits including a leading transistor circuit and a lagging transistor circuit the leading transistor circuit includes a first FET transistor having leading node connected to both and the gate electrode thereof and a resistive circuit, and the lagging transistor circuit includes and a lagging FET transistor having a lagging node connected to both the gate electrode thereof and the resistive and capacitive elements. 
     In accordance with another aspect of this invention, apparatus for compensating for power supply noise comprises a noise compensation amplifier with a power supply input and a reference potential input for connection to a power supply. The amplifier includes a differential amplifier circuit for providing an instantaneous amplified signal in response to power supply noise, and the amplifier produces an output signal with an instantaneous opposite polarity from the power supply noise. Thus, a noise sensitive circuit connected to the noise compensation amplifier has a compensated power supply signal which enables it to produce a reduction in the amplitude of the noise signal at the output thereof. 
     Preferably, the differential pair of coupled transistor circuits each have the source/drain circuits thereof connected in series with a transistor having the source/drain circuit thereof connected to the power supply input or the differential pair of coupled transistor circuits each have the source/drain circuit thereof connected in series with a resistor connected to the power supply input. 
     Preferably, and the differential amplifier circuit includes a differential pair of coupled transistor circuits including a leading transistor circuit and a lagging transistor circuit. 
     In accordance with still another aspect of this invention, apparatus for compensating for power supply noise comprises a noise compensation amplifier with a power supply input and a reference potential input for connection to a power supply. The amplifier includes a differential amplifier circuit for providing an instantaneous amplified signal in response to power supply noise. The amplifier produces an output signal with an instantaneous opposite polarity from the power supply noise. The differential amplifier circuit includes a differential pair of coupled transistor circuits including a leading transistor circuit and a lagging transistor circuit. The leading and lagging transistor circuits have source-drain circuits connected in parallel to the source-drain circuit of a constant current transistor. A current reference constant current source connected to a set of transistors with gate electrodes connected together and source/drain circuits connected to the ground with the gate electrodes connected to the source/drain circuit of one of the set of transistor to provide constant current in the source/drain circuits to the ground circuit. Thus the leading and lagging transistor circuits share a common current as a function of voltages on the leading node connected to the gate of the leading transistor and a lagging node connected to the gate of the lagging transistor and the noise sensitive circuit connected to the noise compensation amplifier has a compensated power supply signal which enables it to produce a reduction in the amplitude of the noise signal at the output thereof. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other aspects and advantages of this invention are explained and described below with reference to the accompanying drawings, in which: 
     FIG. 1 shows a typical prior art system including a supply voltage VDD input connected to the power supply input of a typical VDD noise sensitive circuit. 
     FIG. 2 is a modification of the electrical schematic diagram of FIG. 1 which shows a prior art method for combating the noise sensitivity problem by adding a decoupling capacitor across to the power supply to reduce the noise output signal on the output line. 
     FIG. 3 is a modification of the electrical schematic diagram of FIG. 2 which shows a prior art method in which there are dual output lines in place of the single output line in FIG.  2 . 
     FIG. 4 is a schematic diagram which shows a first preferred embodiment of a Power Supply Noise Compensation (PSNC) amplifier in accordance with the present invention, wherein the system of FIG. 2 has been modified by the addition of the PSNC amplifier which provides a correction output current comprising an Inverted Noise Signal INS on a line which tends to compensate for the effect of the noise signal NS on the NSC. 
     FIG. 5 is a circuit diagram of the single output line, variable current embodiment in accordance with this invention of the PSNC amplifier shown in FIG.  4 . The power supply voltage VDD is used to supply power to the amplifier as seen in FIGS.  4 / 5 . The PSNC amplifier detects the noise and provides a single compensating output current to the NSC. 
     FIG. 6 is a schematic diagram which shows a first preferred embodiment of a Power Supply Noise Compensation (PSNC) amplifier in accordance with the present invention, wherein the system of FIG. 3 has been modified by the addition of the PSNC amplifier which provides a correction output current comprising an Inverted Noise Signal INS on a line which tends to compensate for the effect of the noise signal NS on the NSC. 
     FIG. 7A is a circuit diagram of the single output line variable current embodiment in accordance with this invention of the PSNC amplifier shown in FIG.  6 . The power supply voltage VDD is used to supply power to the amplifier as seen in FIGS.  6 / 7 A. The PSNC amplifier detects the noise and provides a pair of compensating output currents to the NSC. 
     FIG. 7B is a circuit diagram of a single output line variable voltage embodiment in accordance with this invention of the PSNC amplifier shown in FIG. 6 which is an alternative to the embodiment shown in FIG.  7 A. 
     FIG. 8 shows an application of the embodiment of FIGS. 6 and 7A to a VCO circuit which includes a VCO_NSC with a phase locked loop output line in place of the NSC of FIG.  6 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention employs a Power Supply Noise Compensation (PSNC) amplifier  17  seen in FIGS. 4 and 5 in a single output line embodiment of this invention and seen in FIGS. 6,  7 A and  7 B as a modified PSNC amplified  17 ′ in a dual output line embodiment of this invention. In FIG. 8 the PSNC amplifier  17 ′ of FIG. 7A is employed with a VCO loop circuit as the VDD NSC device  110 . The amplifiers  17 ,  17 ′ and  17 ′ all provide output currents which compensate for noise on the power supply VDD as is explained in the descriptions found below. 
     In a particular application, this invention can be implemented where the noise sensitive circuit  11  comprises an I (current) Controlled Oscillator (ICO). Alternatively, it can be a Voltage Controlled Oscillator (VCO). Moreover this invention can be used to reduce the effects of noise in any circuit with variable controls. Use of an embodiment of this invention with an ICO/VCO is just one example of many possible applications therefor. 
     Single Output Line Embodiment 
     FIG. 4 is a schematic diagram which shows a first preferred embodiment of a Power Supply Noise Compensation (PSNC) amplifier  17  in accordance with the present invention, wherein the system of FIG. 2 has been modified by the addition of the PSNC amplifier  17  which provides a correction output current comprising an Inverted Noise Signal INS on line  71  which tends to compensate for the effect of the noise signal NS on NSC  11 . 
     In FIG. 4 like elements to those shown in FIG. 2 have the same description and serve the same function. The power input line  68  of the PSNC amplifier  17  is connected through line  63  and line  60  to the power output terminal of the power supply voltage VDD which includes the noise signal NS. A ground connection to the amplifier  17  is made through amplifier ground line  67 ′ and the capacitor ground line  67  for connection to the power supply ground terminal. 
     The PSNC amplifier  17  provides the VRATE current through an output line  71  which supplies the INS plus/minus (+/−) compensation current (VRATE in FIG.  5 ). That is to say that the inverted noise frequency signal INS on line  71  is one hundred-eighty degrees (180°) out of phase with the noise signal NS on lines  60 / 62 / 63 / 68 . At the node N 0 , the INS current on line  17  (from node N 4  in FIG. 5) is added to the current on line  52  from the circuit control  12 . The result is that a compensated input current is supplied on line  81  to the NSC  11 . In other words, a noise compensated current which is the sum of the currents from line  52  and line  71  is supplied on the input line  81  to the NSC  11 . The adjusted signals on line  81  provide plus/minus (+/−) adjustments to the current signals input to the noise sensitive circuit  11 . 
     In the preferred embodiment of FIG. 4, the noise sensitive circuit  11  (not shown in FIG. 5) or another type of circuit which is in need of noise compensation, receives its control current on line  52  from control circuit  12  and on line  71  from amplifier  17  to compensate for fluctuations of the power supply voltage VDD, as described above. 
     Since the signal INS on line  71  is one hundred-eighty degrees (180°) out of phase with the noise signal NS reducing the effect of the noise signal on line  81  which is supplied to the noise sensitive circuit (NSC)  11 , the result is a reduction of the noise in the compensated output signal COS on the output line  9 . 
     For example, when circuit  17  senses an instantaneous noise induced decrease in the voltage VDD (on line  68  in FIG.  4 ), it responds by providing the correct current signal on line  71  in the case wherein the NSC  11  comprises an ICO/VCO circuit. A differential current produced by a reduced noise signal NS results in an increase in current on line  71 . Likewise, a noise induced increase in the power supply voltage (VDD) or a noise induced decrease in the voltage on the ground (GND) increases the frequency of the NSC  11  and vice versa. 
     This invention reduces this effect of noise signals acting to modulate the frequency of the sensitive (ICO/VCO) circuit  11  by supplying currents INS in such plus/minus polarities as to reduce the ICO/VCO frequency when the source of noise is trying to increase it. 
     FIG. 5 is a circuit diagram of the single output line embodiment in accordance with this invention of the PSNC amplifier  17  shown in FIG.  4 . The power supply voltage VDD is used to supply power to the amplifier  17  on line  68 , as seen in FIGS. 4 and 5. The amplifier  17  detects the noise NS and provides a compensating output current on line  71 . 
     The amplifier circuit of FIG. 5, includes a set of six MOS NFET transistors T 0 , T 1 , T 2 , T 3 , T 4  and T 12  and a set of five MOS PFET transistors T 5 , T 6 , T 7 , T 9  and T 10  plus two identical resistors R 0  and R 1  and a capacitor C 0 . The NFET input transistor T 0  has its drain/source circuit connected between node N 9  and line  67 ′ to ground. Node N 9  is connected through a constant current source IREF to line  74  and node N 9  is also connected to the gate electrodes of transistors T 0 , T 1 , T 2  and T 12 . The sources of PFET transistors T 5 , T 6 , T 7 , T 9  and T 10  and the drain of NFET transistor T 3  are connected to voltage source VDD. The sources of some of the NFET transistors T 0 , T 1 , T 2 , and T 12  are connected by line  67 ′ to ground. 
     The drain of transistor T 5  is connected through node N 6  and through the source/drain of transistor T 1  to ground. Node N 6  connects to the gates of transistors T 5 , T 6  and T 7 . The drain of transistor T 6  is connected via leading node N 1  through resistor R 0  to ground. The leading node N 1  also connects to the gate of transistor T 3 . 
     The drain of PFET transistor T 7  is connected via the lagging node N 2  through the parallel combination of resistor R 1  and capacitor C 0  to ground. The lagging node N 2  also connects to the gate of transistor T 4 . The drain of PFET transistor T 9  connects through node N 8  to the drain of NFET transistor T 4 . Node N 8  also connects to the gates of PFET transistors T 9  and T 10 . The sources of NFET transistors T 3  and T 4  are connected via node N 3  through the drain/source circuit of NFET constant current transistor T 2  to ground. The drain of transistor T 10  is connected via VRATE output node N 4  through the drain/source circuit of transistor T 12  to ground and as the output result of FIG. 5, node N 4  provides the VRATE current output of circuit  17  on line  71  in FIG.  4 . 
     Operation of Single Output Line Embodiment 
     The current from constant current reference IREF flows into node N 9  which is connected to the source and gate of the reference FET transistor T 0  which causes the transistor T 0  to operate with a constant current maintaining a constant voltage at node N 9  and on the gates of transistors T 1 , T 2  and T 12 . The current IREF is mirrored by NFET transistor T 1  and constant current NFET transistor T 2 . Current to NFET transistor T 1  is supplied from PFET transistor T 5  and mirrored to the identical pair of transistors, i.e. PFET transistor T 6  and PFET transistor T 7 , which in turn supply currents to the two identical resistors, i.e. resistor R 0  and resistor R 1 . An identical pair of transistors, i.e. NFET transistors T 3 /T 4 , comprise a source-coupled differential pair of transistors T 3 /T 4  which pair senses and reacts to the difference in voltages between leading node N 1  and lagging node N 2 . Constant current transistor T 2  supplies the tail current for the source-coupled differential pair of transistors T 3 /T 4 . 
     When there is no noise on the VDD connection to sources of transistors T 5 , T 6 , T 7 , T 9 , and T 10  (line  68  in FIG. 4) or GND sources of transistors T 0 , T 1 , T 2  and T 12  (line  67 ′ in FIG.  4 ), the voltages at nodes N 1  and N 2  are identical. However, the presence of noise modulates the source/drain voltages of transistor T 6  and transistor T 7 , changing their drain currents and causing the voltages at nodes N 1  and N 2  to change differentially because of capacitor C 0 . It should be noted that the voltages at leading node N 1  and lagging node N 2  would move identically, were it not for capacitor C 0 , which acts as a high pass filter, bypassing some of the noise current around resistor R 1 . Thus, the voltage on lagging node N 2  changes less in response to noise, than leading node N 1 , and leading transistor T 3  and lagging transistor T 4  amplify a signal proportional to the power supply noise. 
     The current of NFET transistor T 4  is mirrored to the output at node N 4  by PFET transistor T 9  and PFET transistor T 10 . 
     A noise signal that increases VDD will increase the voltage at leading node N 1  relative to lagging node N 2 . In response, the differential pair of transistors T 3 /T 4  will cause less current to flow in VRATE transistors T 9 /T 10  thereby reducing the current flowing through node N 4  to the line  71 . 
     As a result, VRATE is decreased. The opposite effect occurs when the value of VDD decreases, thereby increasing VRATE. VRATE is connected to the noise affected circuit in such a way that the current change on line  71  is the opposite of the noise effect, thereby compensating for some of the noise. 
     The bandwidth over which this invention is effective is primarily determined by the values of resistor R 1  and capacitor C 0 , as well as the bandwidth of the current mirror formed by PFET transistor T 9 /PFET transistor T 10 . 
     Dual Output Line Embodiment 
     In FIG. 6, a second preferred embodiment of the system of FIG. 3 has been modified by the addition of a PSNC amplifier  17 ′ which is generally similar to the PSNC amplified  17  of FIGS. 4 and 5, but which has two output lines  71 ′/ 71 ″ instead of the one line  71  in FIG.  4 . 
     In the preferred embodiment, the NSC  11  of FIG. 6 is an ICO/VCO (such as the one shown in FIG. 8 or other circuit) which is in need of noise compensation, receives its control currents from output lines  71 ′/ 71 ″ (terminals VFAST and VSLOW in FIG. 7A) to compensate for fluctuations of the power supply voltage VDD as described above. In the case of the NSC circuit  11  being an ICO/VCO, a differential current into VFAST and out of VSLOW increases the output frequency of the ICO/VCO circuit  11 . Likewise, an increase in the power supply voltage (VDD) or a decrease in the ground (GND) increases the frequency of the ICO/VCO circuit  11  and vice versa. 
     The PSNC  17 ′ has a power input line  68  connected to line  63  to line  60  to the power output terminal of the power supply voltage VDD. A return path ground connection of the amplifier  17  to the power supply is made via line  67 ′ to line  67 . The amplifier  17  has an output lines  71 ′/ 71 ″ which supply a pair of inverted noise frequency INS signals In/Ip (one hundred-eighty degrees (180°) out of phase) to the output signals of the circuit control  12  on lines  52 ′/ 52 ″ therefrom. The adjusted signals on lines  71 ′/ 71 ″ provide plus/minus (+/−) adjustments to the signals on lines  52 ′/ 52 ″ supplied to the two signal inputs  81 ′/ 81 ″ of the NSC  11 . The signals In/Ip are one hundred-eighty degrees (180°) out of phase with the noise signal NS. The result is a reduction of the noise in the compensated output signal COS on the output line  9 . 
     This invention reduces this effect of noise signals NS acting to modulate the frequency of the ICO/VCO circuit  11  by supplying currents Ip/In on lines  71 ″/ 71 ′ with appropriate polarities as to reduce the ICO/VCO frequency voltage when the power supply noise is trying to increase it and vice versa. 
     For example when circuit  17 ′ senses an instantaneous noise induced decrease in the voltage VDD on power supply input line  68 , it provides at its outputs the In/Ip signals on lines  71 ′/ 71 ″ (VFAST/VSLOW in FIG. 7A) which change with an opposite polarity to the noise NS on line  68  from the power supply VDD. In the case wherein the NSC  11  comprises an ICO/VCO circuit, a differential current produced by a reduced noise signal NS results in a current increase at the VFAST terminal and a current decrease at the VSLOW terminal. Likewise, a noise induced increase in the power supply voltage (VDD) or a noise induced decrease in the voltage on the ground (GND) changes the current in the direction to increase the frequency of the NSC  11  and vice versa. 
     This invention reduces this effect of noise signals acting to modulate the frequency of the sensitive (ICO/VCO) NSC circuit  11  by supplying currents In and Ip with appropriate polarities for reducing the ICO/VCO frequency when the source of noise is trying to increase it. 
     The amplifier circuit of FIG. 7A, includes seven MOS NFET transistors T 0 , T 1 , T 2 , T 3 , T 4 , T 12  and T 13  and seven MOS PFET transistors T 5 , T 6 , T 7 , T 8 , T 9 , T 10  and T 11 , plus two identical resistors R 0  and R 1  and capacitor C 0 . The NFET input transistor T 0  has its drain/source circuit connected between node N 9  and ground line  67 ′. Node N 9  is connected through a constant current source IREF to line  74 . Node N 9  is also connected to the gate electrodes of transistors T 0 , T 1 , T 2 , T 12  and T 13 . The sources of only five of the seven MOS transistors T 0 , T 1 , T 2 , T 12  and T 13  are connected to ground with the sources of NFET transistors T 3  and T 4  being connected to the drain of transistor T 2 . 
     The sources of all seven PFET transistors T 5 , T 6 , T 7 , T 8 , T 9 , T 10  and T 11  are connected to the voltage source VDD which is the source of the noise signal to be compensated by the amplifier  17 ′. The drain of transistor T 5  is connected through node N 6  and through the source/drain of transistor T 1  to ground. Node N 6  connects to the gates of transistors T 5 , T 6  and T 7 . 
     The drain of transistor T 6  is connected via leading node N 1  through resistor R 0  to ground. Leading node N 1  also connects to the gate of transistor T 3 . 
     The drain of PFET transistor T 7  is connected via lagging node N 2  through the parallel combination of resistor R 1  and capacitor C 0  to ground. The lagging node N 2  also connects to the gate of transistor T 4 . 
     The drain of PFET transistor T 8  connects through node N 7  to the drain of NFET transistor T 3 , and node N 7  connects to the gates of PFET transistors T 8 /T 11 . The drain of PFET transistor T 9  connects through node N 8  to the drain of NFET transistor T 4  and node N 8  connects to the gates of PFET transistors T 9 /T 10 . 
     The sources of NFET transistors T 3  and T 4  are connected via node N 3  through the drain/source circuit of NFET constant current transistor T 2  to ground. 
     The drain of transistor T 10  is connected via node N 4  through the drain/source circuit of transistor T 12  to ground. The drain of transistor T 11  connects via node N 5  through the source/drain circuit of transistor T 13  to ground. 
     Node N 4  provides the VFAST (In current) output of circuit  17 . Node N 5  provides the VSLOW (Ip current) output of circuit  17 . 
     Operation of Dual Output Line Embodiment 
     The current from current reference IREF flows into node N 9  which is connected to the source and gate of the reference FET transistor T 0  which causes the transistor T 0  to operate with a constant current maintaining a constant voltage at node N 9  and on the gates of transistors T 1 , T 2  and T 12 . The current IREF is mirrored by NFET transistor T 1  and constant current NFET transistor T 2 . 
     The current IREF is mirrored by NFET transistor T 1  and NFET constant current transistor T 2 . Current to NFET transistor T 1  is supplied from PFET transistor T 5  and mirrored to the identical pair of transistors, i.e. PFET transistor T 6  and PFET transistor T 7 , which in turn supply currents to the two identical resistors, i.e. resistor R 0  and resistor R 1 . An identical pair of transistors, i.e. NFET transistor T 3  and NFET transistor T 4 , comprise a source-coupled differential pair. The source-coupled differential pair of NFET transistors T 3 /T 4  senses the difference in voltage between leading node N 1  and lagging node N 2 . Constant current transistor T 2  supplies the tail current for the differential pair of NFET transistors T 3 /T 4 . Note that the tail current through transistor T 2  is a constant current which must be shared by transistors T 3  and T 4 . When there is no noise on VDD or GND, the voltages at the leading nodes N 1  and the lagging node N 2  connected to the gate electrodes of transistors T 3  are identical. 
     The presence of noise modulates the source/drain voltages of PFET transistor T 6  and PFET transistor T 7 , changing their drain currents and causing changes in the voltages at leading node N 1  and lagging node N 2 . 
     The voltages at leading node N 1  and lagging node N 2  would move identically, were it not for capacitor C 0 , which acts as a high pass filter, bypassing some of the noise current around resistor R 1  causing node N 2  to lag behind leading node N 1 . Therefore, lagging node N 2  voltage changes less than the voltage on the leading node N 1 . As a result, the leading circuit of transistor T 3  and the lagging circuit of transistor T 4  amplify a signal proportional to the noise on the power supply VDD. 
     The current of transistor T 3  is mirrored to the output on VSLOW node N 5  to output line  71 ″ with current Ip by PFET transistor T 8  and PFET transistor T 11 , while the current of transistor T 4  is mirrored to the output on node N 4  to output line  71 ′ with current In by FET transistor T 9  and FET transistor T 10 . 
     PFET transistor T 8  and PFET transistor T 9  are identical, as are PFET transistor T 10  and PFET transistor T 11 . The currents of the identical NFET transistor T 12  and NFET transistor T 13  are mirrored from NFET transistor T 0  in such a way that they balance the currents from transistor T 10  and transistor T 11  when there is no noise. 
     A noise signal that increases VDD will increase the voltage at node N 1  relative to node N 2 . As a result, the source-coupled, differential pair of NFET transistors T 3 /T 4  will cause more current to flow in VSLOW current mirror transistors T 8 /T 11  than the VFAST current mirror transistors T 9 /T 10 . 
     As a result, Ip is increased and In is decreased. 
     VFAST and VSLOW are connected to the noise affected circuit in such a way that the change in Ip is the opposite of the noise effect, thereby compensating for some of the noise. 
     The bandwidth over which this invention is effective is primarily determined by the values of resistor R 1  and capacitor C 0 , as well as the bandwidth of current mirrors transistor T 8 /T 11  and transistor T 9 /T 10 . 
     FIG. 7B is a circuit diagram of a single output line variable voltage embodiment in accordance with this invention of the PSNC amplifier shown in FIG. 6 which is an alternative to the embodiment shown in FIG.  7 A. In FIG. 7B, the difference in the circuit is that the transistor T 8  has been replaced by resistor R 8  and transistor T 9  has been replaced by resistor R 9 . Transistors T 10 , T 11 , T 12  and T 13  have been omitted along with nodes N 4  and N 5  and the interconnection lines to those elements. Node N 7  between the resistor R 8  and the drain of transistor T 3  is the VFAST output on line  71 B″. Node N 8  between the resistor R 9  and the drain of transistor T 4  is the VSLOW output on line  71 B′. The IR current drop through resistors R 8  and R 9  has necessitated a reversal of the connections to node N 7  and N 8  as shown since the voltage drops at node N 7  when the IR drop increases across the resistor R 8  and vice versa for node N 8  and resistor R 9 . 
     FIG. 8 shows an application of the embodiment of FIGS. 6 and 7A to a VCO circuit  100 ″ which includes a VCO_NSC  110  with a phase locked loop output line  90  in place of the NSC  11  of FIG.  6 . The circuit of FIG. 8 is generally similar to FIG.  6 . The differences between FIGS. 6 and 8 will be described below and the since the remainder of features are the same, they will not be discussed further here. A charge pump/filter  120  is substituted for the circuit control  12  of FIG.  6  and lines  152 ′/ 152 ″ replace lines  52 ′/ 52 ″. Node N 0 ′ and line  181 ′ replace of the node N 0  and line  81 ′. Node N 0 ″ and line  181 ″ replace the node N 0  and line  81 ″. The functions are the same. Lines  17 ′ and  152 ′ join at node N 0 ′ which feed into line  181 ′ into the plus (+) terminal of the VCO NSC  110 . Lines  17 ″ and  152 ″ join at node N 0 ″ which feed into line  181 ″ into the minus (−) terminal of the VCO NSC  110 . 
     A feedback loop from line  90  connects to the input of divide by N circuit  180  which provides an input on line  180 ′ to a phase/frequency detector  190 . The other input of detector  190  is frequency reference line FR. The detector  190  feeds an input on line  192  to the charge/pump filter  120 . This completes the Phase-Locked Loop (PLL) of FIG.  8 . The frequency of the VCO_NSC  110  is controlled by the PLL feedback circuit. 
     While this invention has been described in terms of the above specific embodiment(s), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims, i.e. that changes can be made in form and detail, without departing from the spirit and scope of the invention. Accordingly all such changes come within the purview of the present invention and the invention encompasses the subject matter of the claims which follow.