Abstract:
The present invention relates to producing semiconductor integrated circuits, and particularly relates to a method for forming a tungsten plug. The invention protects the dielectric layer from getting damaged and avoids impact from CMP technology on the RC of devices by using an APF as the barrier layer while grinding, to improve the yield of products.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to producing semiconductor integrated circuits, and particularly relates to a method of manufacturing a tungsten plug. 
       BACKGROUND OF THE INVENTION 
       [0002]    As an important part of the semiconductor integrated circuit industry, the contact holes filled by tungsten and then processed by chemical mechanical planarization (CMP), can make a significant effect directly on the resistance-capacitance (RC) of the whole device. 
         [0003]    As the size of devices becomes smaller, and the TiN film and the Ti barrier layer between tungsten and the dielectric layer are thinner, it becomes more difficult to control the CMP technology. In this case over-grinding is common which results in a great difference in the thickness of the dielectric layer, and this reduces the stability of the devices and the yield of products. 
         [0004]    In 65 nanometer technology, as the sizes of the devices become smaller, amorphous carbon is typically used in the contact holes as a hard mask when etching. It is common to remove the amorphous carbon after finishing the etching, and then subsequent processes can be started. Because the hardness of the amorphous carbon is extremely high, it can be a good stop layer in the CMP technology. 
       SUMMARY OF THE INVENTION 
       [0005]    The present invention discloses a method of manufacturing a tungsten plug, wherein the method includes following steps: 
         [0006]    Step S1: Successively preparing an etch stop layer and an inter-layer dielectric on a silicon substrate layer; and then depositing an amorphous carbon layer to cover the upper surface of said inter-layer dielectric; depositing a dielectric anti reflectivity coating to cover the upper surface of said amorphous carbon layer; 
         [0007]    Step S2: Etching said dielectric anti reflectivity coating, said amorphous carbon layer, said inter-layer dielectric and said etch barrier layer to the upper surface of said silicon substrate layer and form a contact hole; wherein said dielectric anti reflectivity coating is removed, and the exposed amorphous carbon layer is partly removed; 
         [0008]    Step S3: Depositing the barrier layer to cover the upper surface of the rest of the amorphous carbon layer as well as the bottom and the side walls of said contact hole; then fully fill tungsten in the contact hole; and 
         [0009]    Step S4: Applying CMP technology to remove a part of the tungsten to the upper surface of the rest of the amorphous carbon layer, and then removing the remaining amorphous carbon layer. 
         [0010]    The above method of manufacturing a tungsten plug, wherein said silicon substrate layer is a silicon wafer which has already formed the structure of bottom devices. 
         [0011]    The above method of manufacturing a tungsten plug, wherein the range of the thickness of the etch stop layer is 200-500 Å. 
         [0012]    The above method of manufacturing a tungsten plug, wherein SiN can be materials of said etch stop layer. 
         [0013]    The above method of manufacturing a tungsten plug, wherein the range of the thickness of said etch barrier layer is 2000-8000 Å. 
         [0014]    The above method of manufacturing a tungsten plug, wherein said inter-layer dielectric includes a silicon oxide layer with high aspect ratio and another silicon oxide layer prepared by tetraethoxysilane; said silicon oxide layer with high aspect ratio covers the upper surface of said etch barrier layer, and said silicon oxide layer prepared by tetraethyl oxidation silicon covers the upper surface of said silicon oxide layer with high aspect ratio. 
         [0015]    The above method of manufacturing a tungsten plug, wherein chemical vapor deposition (CVD) technology is applied to deposit said amorphous carbon layer and said dielectric anti reflectivity coating. 
         [0016]    The above method of manufacturing a tungsten plug, wherein a light resistance is formed in photoetching technology, and then removing the remaining light resistance by mixed gas with hydrogen and nitrogen which is oxygen-free after forming a contact hole which is formed in etching technology by grinding the light resistance. 
         [0017]    The above method for manufacturing a tungsten plug, wherein Ti and TIN can be used as materials of said barrier layer. 
         [0018]    The above method for manufacturing a tungsten plug, wherein removes the rest of said amorphous carbon layer using oxygen-free plasma. 
         [0019]    In conclusion, as a result of the use of said technology solution, the present invention relates to a method of manufacturing a tungsten plug; this invention can well protect the dielectric layer from being damaged and impact can be avoided from CMP technology on the RC of devices by using an amorphous carbon layer as the stop layer while grinding, and this can improve the yield of products. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]      FIG. 1-7  are structural diagrams showing successive stages in the method of manufacturing a tungsten plug in accordance with the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0021]    The present invention will be further elaborated in the following with figures, and include the following steps: 
         [0022]    Firstly, a SiN etch stop layer  2  having a thickness in the range of 200-500 Å is grown on the silicon wafer  1  which has already formed the structure of bottom devices, and then a silicon oxide layer  31  is prepared using a high aspect ratio process (HARP) to cover the upper surface of the silicon nitride etch stop layer  2 , and then another silicon oxide layer  32  is prepared using tetraethoxysilane (TEOS) to cover the upper surface of the silicon oxide layer  31 . The silicon oxide layer  31  and the silicon oxide layer  32  together make up the inter-layer dielectric (ILD) layer  3  which has a thickness in the range of 2000-8000 Å. 
         [0023]    Secondly, successively depositing an amorphous carbon layer (which is also named as an advance pattern film, APF)  4  and a dielectric anti-reflectivity coating (DARC)  5  using chemical vapor deposition (CVD), and then spinning on the photoresist to cover the upper surface of the DARC  5 , removing the photoresist for manufacturing the light resistance of the contact hole  6  after exposure and development; wherein the APF  4  covers the upper surface of the silicon oxide layer  32  using TEOS, and the DARC  5  covers the upper surface of the APF  4 . 
         [0024]    Thirdly, successively etching the DARC  5 , the APF  4 , the inter-layer dielectric  3  and the etch stop layer  2  to the upper surface of the silicon wafer using the above light resistance of the contact hole  6  as a mask, forms the remaining APF  41 , the remaining inter-layer dielectric  33 , the remaining barrier layer  21  and the contact hole  7 . After the above steps, the photoresist is removed; wherein the DARC  5  is completely removed during the etching process, the exposed APF  4  is partly etched for manufacturing a thinner remaining APF  41 , and removing the remaining photoresist  61  using mixed gas made up with oxygen-free hydrogen and nitrogen in a stripping and cleaning process. 
         [0025]    Fourthly, depositing the barrier layer  8  which uses Ti and TiN as materials to cover the upper surface of the remaining APF  41  as well as the bottom and the side walls of the contact hole  7 ; and then fully filling metal tungsten  9  in the remaining contact hole  71  to cover the upper surface of the barrier layer  8 . 
         [0026]    Finally, grinding the metal tungsten  9  to the remaining APF  41  by CMP technology, removing a part of the metal tungsten  9  and the barrier layer  8  covering the remaining APF  41 , for manufacturing the remaining metal tungsten  91  filling in the contact hole and the remaining barrier layer  81 ; then removing the remaining APF  41  using oxygenous plasma. 
         [0027]    In conclusion, applying the above technical solution, a method for manufacturing a tungsten plug that uses a high hardness APF as an etch stop layer of grinding is proposed in this invention; using the Planarization process, the APF can effectively avoid the dielectric layer damage in the grinding process, and avoid impact from CMP technology on the RC of devices, and thus improve the yield of products. 
         [0028]    Although having given a typical embodiment of a particular structure of the specific implementation way above with description and the figures, we can make other changes based on the spirit of this invention. Though preferred embodiments are proposed above, these contents are not the limitation of this invention. 
         [0029]    It is obvious for the skilled in the art to make varieties of changes and modifications after reading the above descriptions. Hence, the Claims attached should be regarded as all the changes and modifications which cover the real intention and the range of this invention. Any and all equivalent contents and ranges in the range of the Claims should be regarded belonging to the intention and the range of this invention.