Abstract:
An instruction fetch control method is generally arranged so as to have a plurality of instruction buffers, issue an instruction read request to a memory when a part of the instruction buffers becomes in an empty state and store a fetched instruction in the instruction buffer in an empty state. A flag is provided for specifying another instruction buffer which becomes in an empty state after the instruction stored in the instruction buffer is transmitted to a decoder. The quantity of instructions to be stored in the instruction buffer is made variable in accordance with output of the flag latch, and the fetched instruction is stored in the instruction buffer in an empty state. This arrangement enables a plurality of instructions fetched upon an instruction read request to be stored in the empty instruction buffers, thereby reducing the number of read requests issued.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to an instruction fetch control method and, more particularly, to an instruction fetch method which involves efficiently fetching instructions from a memory and supplying the instructions to an instruction processor which processes a sequence of instructions in order to execute data processing. 
     Heretofore, instruction processors for data processors have adopted an instruction fetch control in which a plurality of instruction buffers are pre-fetched in order to accomplish instruction processing at a high speed. In the pre-fetch control for pre-fetching instructions, an instruction read request is provided to the memory (hereinafter also referred to as a first instruction fetch) whenever a portion of the instruction buffers is rendered empty as the instruction processing advances, in order to avoid rendering all of the instruction buffers empty. Further, processing performance, when a branch destination instruction read request is given to the plural instruction buffers in processing a branch instruction, when the branch instruction is decoded or when the appearance of a branch instruction is predicted from the processing history (this instruction fetch being hereinafter also referred to as a second instruction fetch; for example, as disclosed in Japanese Patent Unexamined Publication (kokai) No. 59-91,522/1984). 
     As disclosed in Japanese Patent Unexamined Publication (kokai) No. 62-77,648/1987, for example, for the instruction pre-fetch control of this kind, there is proposed a method which involves issuing an instruction read request to the memory regardless of whether the instruction buffer is in an empty state and accepting the instruction read request in fetching the fetched instruction into the instruction buffer when the instruction buffer is empty, while suppressing the acceptance of the instruction read request when the instruction buffer is not empty. 
     It is to be noted that, in order to always ensure an adequate quantity of instructions within the instruction buffers, for example, an instruction read request is required to be given whenever an empty capacity reaches eight bytes if the instruction buffer has the capacity of 32 bytes. Therefore, in this case, the quantity of instructions to be fetched upon one instruction read request becomes relatively small. 
     In the second instruction fetch, as all of the instruction buffers are rendered empty, it is necessary to immediately store the fetched instructions in the instruction buffers. Therefore, in this case, it is desired to fetch as many instructions as possible in one instruction read request. 
     For these reasons, in conventional pre-fetch control, the amount of instructions to be fetched per one instruction read request is controlled so as to adapt the quantity required for the second instruction fetch, with the impact upon the hardware amount and performance taken into consideration. Therefore, in implementing the first instruction fetch, only a fixed length from the top out of the fetched instruction is stored in the instruction buffer and the rest is left unemployed. For instance, suppose that, when the instruction buffer has the capacity of 32 bytes as in the previous case, 16 bytes of the instruction out of the 32 bytes are fetched by one request. In this case, in the second instruction fetch, the instruction read requests are issued twice, thereby filling the instruction buffer of 32 bytes with the instructions fetched, while in the first instruction fetch, the former 8 bytes out of the 16 bytes fetched are stored in the instruction buffer and the latter 8 bytes are left unemployed. 
     If a large number of instruction buffers are provided and a branch destination is fetched, a frequency of instruction read request increases as the number of instruction buffers increases. Further, in instances where a branch destination instruction is fetched by predicting the appearance of a branch instruction from the past history, the fetch timing becomes earlier, as compared with the fetching of the branch destination instructions when the branch instruction is decoded, thereby further increasing a frequency of the instruction read requests. 
     As described hereinabove, in the instruction fetch control in conventional technique, the frequency of the second instruction read request increases when the first instruction is fetched at a constant frequency, thereby causing collision between the instruction read requests. As a result, memory overhead increases, leading to a reduction in overall processing performance. 
     SUMMARY OF THE INVENTION 
     Therefore, it is an object of the present invention to provide an instruction fetch control method which is so adapted as to reduce the number of first instruction read requests and as to prevent a decrease in processing performance due to collision between the instruction read requests, thereby improving processing performance. 
     In order to achieve the above object, the present invention provides an instruction fetch control method to a system having a plurality of instruction buffers. In the system an instruction read request is issued to a memory when a part of the instruction buffers becomes in an empty state and a fetched instruction is stored in the instruction buffer in an empty state. 
     The method comprises a flag latch for specifying another instruction buffer which become in an empty state after the instruction stored in the instruction buffer is transmitted to a decoder, 
     making a quantity of instructions to be stored in the instruction buffer variable in accordance with output of the flag latch, and 
     storing the fetched instruction in the instruction buffer in an empty state. 
     In the instruction fetch control method according to the present invention, the instruction processing proceeds in an instruction processor, followed by fetching the instruction from the instruction buffer. As the instruction is fetched and decoded and the decoded instruction is fed to the instruction processor, a flag latch is so set as to correspond to the instruction buffer fetched and a report is given to indicate that the corresponding instruction buffer is in an empty state. When the flag latch is set and the empty instruction buffer is detected, an instruction read request is transmitted to the memory in order to store the instruction in the empty instruction buffer. During a period of time when a response to the instruction read request is returned from the memory, even if a next instruction is fetched from the instruction buffer and it is detected that the succeeding portion of the instruction buffer became empty, the instruction read request for the empty instruction buffer concerned is suppressed until a signal is returned in response to the previous instruction read request from the memory and the fetched instruction is stored in the preceding instruction buffer in an empty state. The response from the memory is returned immediately even if the instruction to be fetched would exist in the memory. However, if a portion of memory of the instruction to be fetched would be paged out and it would not exist in the memory, no response will be returned until block transfer has finished and the instruction is stored in the memory. Hence, when the next instruction is fetched from the instruction buffer and the succeeding instruction buffer became empty during the period of the time until the response is returned from the memory, the instruction fetched is stored in the preceding empty instruction buffer and the succeeding empty instruction buffer when the response has been returned from the memory. If the next instruction would not be fetched from the instruction buffer and the succeeding instruction buffer would not become empty during the period of time when a response is returned from the memory, the instruction fetched from the memory is stored in the preceding empty instruction buffer, a next instruction for the succeeding instruction buffer would not become empty. 
     Other objects, features and advantages of the present invention will become apparent in the course of the description of the preferred embodiments, which follows, with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing the construction of an essential portion of an instruction fetch control section of data processor according to an embodiment of the present invention. 
     FIG. 2 is a diagrammatic representation of the construction of an instruction fetch controller. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     As shown in FIG. 1, in the construction of the essential portion of the instruction fetch control section of an instruction processor, reference numeral 1 denotes a memory; reference numeral 2, a shifter; 3 to 6, instruction buffer registers; 7, a selector; 8, an instruction decoder; 9, an instruction fetch controller; 10, an instruction fetch pointer; and 11, an instruction fetch address register. The memory 1 stores an instruction sequence (one instruction having a length of 4 bytes) to be processed. The instructions (four instructions) are to be fetched from the memory 1 by one instruction read request. The instructions having a length as long as 16 bytes fetched from the memory 1 are shifted by the shifter 2 in accordance with a fetch address and then fed to each of instruction buffer registers IBR3 to IBR6, inclusive. Each of the instruction buffer registers IBR3 to IBR6 is an instruction buffer register for supplying an instruction of a 4-byte length. One instruction is stored in each of the registers. Hence, the instruction buffer registers IBR3 to IBR6 constitutes an instruction buffer which stores instructions having the capacity of 16 bytes as a whole. It is noted herein that, when one instruction is decoded, one instruction buffer register corresponding to the decoded instruction becomes empty because the instruction length for one instruction is 4 bytes. 
     Description will now be made of an instruction fetch operation. Suppose that the instruction buffer registers IBR3 to IBR6, inclusive, store instructions and the instruction fetch pointer 10 is pointed to the instruction buffer register IBR3. The instruction stored in the instruction buffer register IBR3 is selected by the selector 7 in response to the selection instruction from the instruction fetch pointer 10 and then inputted into the decoder 8. When the input instruction into the decoder 8 is decoded and a decode signal 1d is turned on, the instruction buffer register IBR3 is rendered empty due to decoding, so that the instruction fetch controller 9 transmits an instruction read request 1b to the memory 1 in order to allow the empty instruction buffer register IBR3 to store a next instruction. At this time, the instruction fetch pointer 10 is increment by the decode signal 1d so as to point to the instruction buffer register IBR4 in which a next instruction is stored. On the other hand, the instruction fetch address of the instruction fetch address register 11 indicates an instruction fetch address in which an instruction of a 4-byte length is added and stored in the instruction buffer register IBR4 to be inputted next into the decoder 8. 
     A response signal 1c to the instruction read request 1b is to be returned immediately from the memory 1 when the instruction exists in the memory 1. On the other hand, when no instruction exists in the memory 1, a block transfer is implemented to thereby store necessary data in the memory 1 and thereafter the response is to be returned. Hence, in instances where the instruction does not exist in the memory 1, no response will be returned until the block transfer has been finished. 
     Hence, until the response signal 1c is returned from the memory 1 after the instruction read request 1b has been transmitted, if processing of instructions proceeds and the instruction within the next instruction buffer register IBR4 is decoded and the decode signal 1d is turned on again, the instruction fetch pointer 10 is increased so as to update the content of the instruction fetch address register 11 to an instruction fetch address to be fetched next, in the same manner as in the previous case in which it has been so increased as to point to the instruction buffer register IBR4. At this time, the instruction fetch controller 9 does not transmit the instruction read request for the instruction to be stored in the instruction buffer register IBR4, because the response to the instruction read request for the instruction to be stored in the instruction buffer register IBR3 has not been returned. 
     Thereafter, when the response signal 1c is returned from the memory 1 prior to the decoding of the instruction within the instruction buffer register IBR5 which stores the next instruction, the instruction fetch controller 9 transmits an instruction store signal 1a to thereby store the fetched instruction in the instruction buffer register IBR3 which has previously been made in an empty state. Then, the instruction fetch controller 9 transmits the instruction store signal 1a to the instruction buffer register IBR4, too, which has been made empty subsequent to the instruction buffer register IBR3. 
     As described hereinabove, the instruction fetched from the memory 1 after the response signal 1c was returned from the memory 1 is shifted by the shifter 2 in accordance with the fetch address and inputted into the instruction buffer registers IBR3 to IBR6, inclusive, in accordance with the empty state of each instruction buffer register. More specifically, the instruction is stored in the instruction buffer register IBR3 by the instruction store signal 1a to the instruction buffer register IBR3, and the instruction is stored in the instruction buffer register IBR4 by the instruction store signal 1a to the instruction buffer register IBR4. This is to store the fetched instructions in the instruction buffer register IBR3 and 4 which have been rendered empty. 
     If the instruction in the instruction buffer register IBR4 has not been decoded during a period of time after the transmission of the instruction read request to the instruction buffer register IBR3 up to the return of the response signal from the memory 1, the instruction buffer register which is in an empty state is only the IBR3 and, when the response is returned, the instruction fetched from the memory 1 is stored only in the instruction buffer register IBR3. When the instruction stored in the instruction buffer register IBR4 is decoded and the instruction buffer register IBR4 is rendered empty, a new instruction read request is transmitted in order to store the instruction for buffering in the instruction buffer register IBR4. 
     FIG. 2 is a logic circuit showing the construction of the detail of the instruction fetch controller 9. As shown in FIG. 2, reference numerals 12 to 17, inclusive, denote delay latches; reference numerals 18 to 21, inclusive, AND gates; reference numerals 22 to 25, inclusive, flag latches indicative of the empty state of each of the instruction buffer registers so disposed as to correspond to the respective instruction buffer registers IBR3 to IBR6; reference numeral 26, a NOR gate; and reference numerals 27 to 31, inclusive, AND gates. It is noted herein that the decode signal 1d is so arranged as to vary in timing of a phase from the response signal 1c from the memory 1 and as to fail to be turned on currently with the response signal 1c. 
     When all of the instruction buffer registers IBR3 to IBR6 store instructions, the values of the flag latches 22 to 25 are set to &#34;0&#34;. If the instruction in the instruction buffer register IBR3 would be transmitted to the decoder 8 through the selector 7 by means of the instruction from the instruction fetch pointer 10 and it is decoded, the decode signal 1d is generated, thereby turning output of the delay latch 12 on. At this time, all the flag latches 22 to 25 are set to &#34;0&#34; so that output of the NOR gate 26 becomes in an ON state, followed by turning output of the AND gate 27 and transmitting the instruction read request 1b to the memory 1. The data from the instruction fetch pointer 10 serves as output to the delay latches 13 to 16, inclusive. In this embodiment, it is to be noted that, as the data of the instruction fetch pointer 10 points to the instruction buffer register IBR3, only output of the delay latch 13 is turned on, while the rest is turned off. This allows only the output of the AND gate 18 to be turned on and only the flag latch 22 to be set to &#34;1&#34;, while the other flag latches 23 to 25, inclusive, are left unchanged at &#34;0&#34;. 
     If processing of instructions proceeds during a period of time before the response is returned from the memory 1 and the next instruction stored in the instruction buffer register IBR4 would be decoded, like the previous cases as described hereinabove, the delay latch 12 is turned on by the decode signal 1d is turned on and the output of the delay latch 14 is also turned on by a signal from the instruction fetch pointer 10, so that the output of the AND gate 19 is turned on, thereby setting the flag latch 23 to &#34;1&#34;. It is to be noted herein, however, that no instruction read request 1b is transmitted to the memory 1 at this time because at this time the flag latch 22 has already been set to &#34;1&#34; so that the output of the NOR gate 26 is turned off and the output of the AND gate 27 is turned off, too. 
     Thereafter, when the response signal 1c is returned from the memory 1 prior to the decoding of the instruction in the instruction buffer register IBR5, the output of the delay latch 17 is turned on. In this case, both of the flag latches 22 and 23 are set to &#34;1&#34;, so that the AND gates 28 and 29 are turned on, thereby transmitting the instruction store signal 1a to the instruction buffer registers IBR3 and IBR4, respectively. At this time, after the instruction store signal 1a is transmitted to each of the instruction buffer registers IBR3 and IBR4 through the AND gate 28 and the AND gate 29, respectively, by means of the output of the delay latch 17, the flag latches 22 and 23 are reset to &#34;0&#34; by the respective instruction store signal 1a in correspondence with the transmission of the instruction store signal 1a. Likewise, when processing of instructions proceeds and the instruction stored in the instruction buffer register IBR5 is decoded to thereby generate the decode signal 1d, the delay latch 12 is turned on and the NOR gate 26 is turned on, too, so that the instruction read request 1b is transmitted from the AND gate 27 to the memory 1, in substantially the same manner. When processing of instructions further advances, the instruction read request 1b is transmitted to the memory 1 in substantially the same manner. 
     As have been described hereinabove, the present invention makes the quantity of instructions to be stored in the instruction buffer variable in accordance with the empty state of the instruction buffer, so that it can store a plurality of instructions fetched upon the instruction read request in the empty instruction buffer in accordance with the empty state of the instruction buffer. This reduces the number of instructions read requests issued and also prevents a reduction in processing performance due to collision between the instruction read requests.