Abstract:
In an optical receiver, a photodiode converts an optical digital input signal to an electrical signal which is fed into a differential amplifier to produce a pair of true and complementary output signals. The true output signal is received by a peak detector and the output of this peak detector is summed in a first adder with the complementary output of the differential amplifier. The true output of the amplifier is summed in a second adder with a predetermined constant voltage. Difference between the output signals of the first and second adders is detected and compared with a decision threshold to produce an output signal at one of two logical levels depending on whether the difference is higher or lower than the decision threshold. Preferably, a second peak detector having a substantially similar operating characteristic to that of the first peak detector is connected between the source of the predetermined constant voltage and the second adder.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an adaptive threshold controlled decision circuit suitable for receiving optical digital signals contaminated with ringing components. 
     2. Description of the Related Art 
     In computers and communications equipment, optical interconnection networks are used to transfer optical binary signals between LSI circuits with no format conversion. As constituent elements of the interconnection networks, attention is currently focused on DC-mode optical receivers capable of receiving binary digits of the same value which last for an indefinitely long period of time. Since the required transmission rate is more than several 100 of megabits per second, DC-mode optical receivers with a constant decision threshold and a dynamic range of 10 to 15 dB are not practical because of the difficulty to support a sufficient bandwidth to meet the speed requirement. AC-mode optical receivers are also known in the art. This type of optical receivers is used in combination with a coding circuit as an optical data link to take the benefit of its excellent sensitivity characteristic to low optical input levels. 
     An important factor to be taken into consideration in the design of an optical receiver is the generation of noise-like components, or “ringing”, caused by electrical crosstalk between optical transmitters. The ringing occurs on both high and low level laser outputs when laser diodes are driven at logical-1 (i.e., mark) and logical-0 level (i.e., space), respectively. Although the ringing that occurs at low level laser output can be reduced to a minimum by setting the bias current of laser diodes at a value sufficiently lower than their threshold level, it is impossible to eliminate the ringing that occurs at high level laser output. 
     As shown in FIG. 1, a prior art optical receiver disclosed in Japanese Laid-Open Patent Specification Hei-8-84160 includes a photodiode  1  for converting optical unipolar input pulses (see FIG. 1) to an electrical current signal which is fed to a differential preamplifier  2 . The preamplifier produces a pair of voltage signals of opposite logic levels. The true output of the preamplifier is supplied to a peak detector  3  and an adder  5 , and the complementary output is supplied to a peak detector  4  and an adder  6 . The difference between the outputs of adders  5  and  6  is determined by a subtractor  7 . As a result, the decision levels of a decision circuit  8 , or Schmitt trigger are adaptively controlled by the input signal. When the difference output of subtractor  7  is higher than threshold V H , the output of decision circuit  8  goes high and when it reduces to a level lower than threshold V L , the output of decision circuit  8  goes low. 
     As shown in FIG. 2, when the optical input level is low, there is no ringing component. After two successive cycles of marks and spaces, the optical input is maintained at a high level which is rich in ringing components. If no ringing were present, the output of subtractor  7  would steadily decay and stay at a midpoint of the two threshold values, so that the optical receiver could be used as a DC-mode optical receiver. However, due to the presence of ringing component, the difference signal crosses the high and low threshold levels in rapid succession, producing error pulses. Since the amplitude of the ringing component is proportional to the optical input power, this ringing problem will become serious and the implementation of a DC-mode optical receiver operating on a high optical input level becomes difficult. On the other hand, if the optical input contains no DC components, the prior art optical receiver can still be used as an excellent AC-mode optical receiver. 
     Furthermore, optical receivers are used in both interconnection networks and data links and demand for such applications is enormous, there is therefore a need for dual mode optical receivers. 
     Japanese Laid-Open Patent Specifications Sho-62-206947 and Hei-2-266630 disclose DC-mode optical receivers immune to ringing components. However, it is impossible to modify the prior art DC-mode optical receivers into AC-mode optical receivers to be used in tandem connection while canceling offset components. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide an adaptive threshold controlled decision circuit which is immune to ringing components and is capable of being used in both DC and AC modes. 
     According to one aspect of the present invention, there is provided a circuit arrangement comprising an amplifier for producing a true output signal and a complementary output signal in response to a digital input signal, a peak detector for receiving the true output signal, a first adder for summing the complementary output signal and an output signal of the peak detector, and a second adder for summing the true output signal and a predetermined constant voltage. Difference between the output signals of the first and second adders is detected. A decision circuit makes a decision on the difference signal to produce a digital output signal. Preferably, a second peak detector having a substantially similar operating characteristic to that of the first peak detector is connected between the source of the constant voltage and the second adder. 
     According to a second aspect, the present invention provides a circuit arrangement comprising an amplifier for producing a true output signal and a complementary output signal in response to a digital input signal, a first peak detector for receiving the true output signal, a second peak detector for receiving the complementary output signal, a first adder for summing the complementary output signal with an output signal of the first peak detector, a second adder for receiving the true output signal and switching circuitry, responsive to a first control signal, for causing a predetermined constant voltage to be summed by the second adder with the true output signal, and responsive to a second control signal, for causing an output signal of the second peak detector to be summed by the second adder. Difference between the output signals of the first and second adders is detected. A decision circuit makes a decision on the difference signal to produce a digital output signal. Preferably, each of the first and second peak detectors has a variable time constant value, and wherein the switching circuitry comprises means for setting the time constant values of the first and second peak detectors at a lower value in response to the first control signal, and setting the time constant values of the first and second peak detectors at a higher value in response to the second control signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be described in further detail with reference to the accompanying drawings, in which: 
     FIG. 1 is a block diagram of a prior art optical receiver; 
     FIG. 2 is a timing diagram illustrating various waveforms appearing in the optical receiver of FIG. 1; 
     FIG. 3 is a block diagram of an optical receiver according to one embodiment of the present invention; 
     FIG. 4 is a timing diagram illustrating various waveforms appearing in the optical receiver of the present invention; 
     FIG. 5 is a circuit diagram of a portion of the optical receiver of the present invention; and 
     FIG. 6 is a circuit diagram of a portion of a dual mode optical receiver according to the present invention. 
    
    
     DETAILED DESCRIPTION 
     In FIG. 3, the optical receiver of this invention comprises a photodiode  11  for converting optical unipolar input pulses to an electrical current signal which is fed to a differential preamplifier  12  of an adaptive threshold controlled decision circuit. The preamplifier produces a pair of voltage signals of true and complementary logic levels. The true output of the preamplifier is supplied to a peak detector  13  and an adder  15 . 
     According to this invention, the complementary output of differential preamplifier  12  is supplied only to an adder  16  where it is summed with the output of peak detector  13 , and the differential preamplifier  12  has a constant DC voltage supply circuit  19  which feeds a peak detector  14  which is identical in time-constant characteristic to the peak detector  13 . Adder  15  combines the true output of differential amplifier  12  with the output of peak detector  14 . Peak detectors  13  and  14  are of identical circuit configuration. 
     Difference between the outputs of adders  15  and  16  is determined by a subtractor  17  and then compared by a decision circuit or Schmitt trigger  18  with a decision threshold V th . When the difference output of subtractor  17  is higher than threshold V th , the output of decision circuit  18  is high. Otherwise, the output of decision circuit  18  is low. 
     The voltage produced by the DC voltage supply circuit  19  is a DC voltage of constant level M which is set equal to an average value of the true and complementary output voltages of the differential amplifier  12 . This constant DC voltage M is coupled via the peak detector  14  to the adder  15  and summed with the amplifier&#39;s true output. The purpose of the peak detector  14  is to cancel the internal offset voltage of the peak detector  13 . 
     The operation of the optical receiver of this invention will be described with reference to FIG. 4 by assuming that the same optical input signal is applied to the receiver as that of FIG.  2 . 
     The input signal shown in part (a) of FIG. 4 is converted by the differential amplifier  12  to a pair of true and complementary varying waveforms as shown in part (b) of FIG.  4 . Peak detector  13  detects peak voltages of the true output of amplifier  12  and peak detector  14  produces an output voltage corresponding to the constant level M of the voltage supply circuit  19  as shown in part (c) of FIG.  4 . Adder  15  produces a sum of the true output of amplifier  12  and the constant level output of peak detector  14  and the adder  16  produces a sum of the complementary output of amplifier  12  and the peak level output of peak detector  13  as shown in part (d) of FIG.  4 . Subtractor  17  produces a voltage representing the difference between the summed output voltages of adders  15  and  16  as shown in part (e) of FIG.  4  and compared by the decision circuit  18  with the threshold voltage V th . Since the output of the peak detector  14  is constant, the difference voltage does not approach the threshold level when the input optical level remains at high level. The output of the decision circuit  18  thus contains no error pulses as shown in part (f) of FIG.  4 . The bias current of the laser diode at the optical transmitter, not shown, is so adjusted that no ringing occurs when it is driven to low level. Therefore, the output signal of the decision circuit  18  is an accurate representation of the optical input level. 
     A portion of the optical receiver is enclosed by a broken-line rectangle  10  and details of this portion are shown in the circuit diagram of FIG.  5 . 
     Differential preamplifier  12  is of a trans-impedance amplifier configuration in which the true output is fed back to the complementary input and the complementary output is fed back to the true input. Specifically, the preamplifier comprises transistors T 1  to T 5 , resistors R 1  to R 6  and a capacitor C 1 . Transistor T 1  has its emitter coupled via resistor R 1  to a voltage terminal V EE  and its base coupled via resistor R 2  to DC voltage supply circuit  19 , the collector of transistor T 1  being connected to a circuit node between the emitters of transistors T 2  and T 3 . Transistor T 2  has is base connected via capacitor C 1  to voltage terminal V EE  and via resistors R 3  and R 11  to voltage terminal V EE . Transistor T 3  has its base connected to input terminal IN and further connected via resistors R 4  and R 15  to voltage terminal V EE . Transistors T 4  and T 5  have their collectors connected to voltage terminal V CC  and their emitters coupled to resistors R 3  and R 4 , respectively. The base of transistor T 4  is connected to a circuit node between the collector of transistor T 2  and resistor R 5  and the base of transistor T 5  is connected to a circuit node between the collector of transistor T 3  and resistor R 6 , the resistors R 5  and R 6  being connected to the voltage terminal V CC . 
     Peak detector  13  comprises a transistor T 7  and a capacitor C 2  which is connected across the emitter and collector of transistor T 7 . The base and collector of transistor T 7  are connected to the base and collector of transistor T 4 , respectively. The collector of transistor T 7  is further connected to voltage terminal V CC . The emitter of transistor T 7  is further connected to the base of a transistor T 10 . 
     Peak detector  14  comprises a transistor T 8  and a capacitor C 5  which is connected across the emitter and collector of transistor T 8 . The base of transistor T 8  is connected to the DC voltage supply circuit  19  and the collector of transistor T 8  is connected to the voltage terminal V CC . The emitter of transistor T 8  is further connected to the base of transistor T 11 . 
     DC voltage supply circuit  19  is of a current mirror configuration for setting a current from the preamplifier  12  as a constant current source. Specifically, it comprises resistors R 7  to R 10  and a transistor T 9 . Resistors R 7 , R 8  and R 9  are connected in series between voltage terminal V CC  and the base of transistor T 9  and resistor R 10  is connected between the emitter of transistor T 9  and voltage terminal V CC . A circuit node between resistors R 8  and R 9  is connected via resistor R 2  to the base of transistor T 1  of preamplifier  12  and to this circuit node the collector of transistor T 9  is also connected. Resistors R 7  to R 10  are determined so that a voltage developed across resistor R 7  is substantially equal to an average value of voltages respectively developed across resistors R 6  and R 7  of the preamplifier  12 . The voltage developed across resistor R 7  is the constant DC voltage M, and this voltage is applied to the base of transistor T 8  of peak detector  14 . 
     Transistors T 10  and T 11  have their collectors coupled to voltage terminal V CC  and their emitters respectively coupled via resistors R 12  and R 13  to voltage terminal V EE . The output of peak detector  13  is amplified by transistor T 10  and applied to adder  16 . Adder  16  is formed with resistors R 16 , R 17  and R 18  arranged to combine the amplified peak detector output with a complementary output of amplifier  12  which appears at a circuit node between resistors R 4  and R 15 . The output of peak detector  14  is amplified by transistor T 11  and applied to adder  15 , the adder  15  comprising resistors R 19 , R 20  and R 21  arranged to combine the amplified peak detector output with a true output voltage of amplifier  12  which appears at a circuit node between resistors R 3  and R 11 . 
     A differential post-amplifier  20  is provided for respectively amplifying the outputs of adders  15  and  16  for application to the subtractor  7 . This amplifier is formed with transistors T 13  to T 18  and resistors R 22  to R 31 . Transistor T 13  has its emitter coupled via resistor R 22  to the voltage terminal V EE  and its base coupled via resistor R 23  to the collector of transistor T 18  whose base is coupled via resistor R 29  to its collector. Transistors T 14  and T 15  have their emitters coupled together to the collector of transistor T 13  and their collectors coupled to the bases of transistors T 16  and T 17 , respectively. The base of transistor T 14  is connected to the circuit node of resistors R 19  to R 21  and the base of transistor T 15  is connected to the circuit node of resistors R 16  to R 18 . Resistors R 24  and R 25  are connected in series across the collectors of transistors T 14  and T 15 , the circuit node between R 24  and R 25  being connected via resistor R 26  to voltage terminal V CC . Transistors T 16  and T 17  have their collectors connected to voltage terminal V CC  and their bases connected to resistors R 21  and R 17 , respectively. Transistor T 18  has its collector connected via resistor R 27  to voltage terminal V CC . The emitter of transistor T 18  is connected via resistor R 28  to voltage terminal V EE  to which the emitters of transistors T 16  and T 17  are also connected via resistors R 30  and R 31 . The amplified output of adder  16  is taken from the circuit node between resistors R 17  and R 31  and the amplified output of adder  15  is taken from the circuit node between resistors R 21  and R 30 . 
     In order to establish a balance between the circuit formed by transistors T 7 , T 10 , capacitor C 2  and resistor R 12 , a transistor T 6  is provided having its base and collector coupled to those of transistor T 5  and its emitter coupled to the base of a transistor T 12 , the collector-emitter path of transistor T 12  and a resistor R 14  being connected between voltage terminals V CC  and V EE . 
     The optical receiver of FIG. 5 is modified into a dual mode optical receiver as shown in FIG. 6 by additionally including capacitors C 3 , C 4  and C 7  and metal oxide field-effect transistors as switching elements which are classified as K, L and M groups. MOSFET switches K 1  and K 2  are always biased at a constant voltage for coupling capacitor C 2  to transistor T 17  and the emitter of transistor T 10  to the adder  16 , regardless of operational modes. 
     In a DC mode of operation, MOSFET switches L 1  and L 2  are turned on in response to a DC-mode control signal (e.g., slightly lower than the voltage at terminal V EE ) supplied to a control terminal CTRL for coupling capacitor C 5  to transistor T 18  to form the peak detector  14  and coupling the emitter of transistor T 11  to the adder  15 , while switches M 1  to M 5  are turned off. The DC-mode optical receiver operates in a characteristic identical to that shown in FIG.  4 . 
     In an AC mode, MOSFET switches L 1  and L 2  are turned off and M 1  to M 6  are turned on in response to an AC-mode control signal (e.g., slightly higher than the voltage at terminal V CC ) supplied to the control terminal CTRL. The turn-on of switches M 1  to M 3  causes capacitors C 5 , C 6  and C 7  to be connected in parallel across the emitter and collector of transistor T 6  to form a first peak detector. The turn-on of switch M 4  establishes a connection between the emitter of transistor T 12  to the adder  15 , so that the output of the first peak detector is applied to the adder  15 . The turn-on of switches M 5  and M 6  causes capacitors C 3  and C 4  to be connected in parallel with capacitor C 2  across the emitter and collector of transistor T 7  to form a second peak detector identical in characteristic to the first peak detector. The output of the second peak detector is supplied through transistor T 10  and switch K 2  to the adder  16 . It is seen that, during the AC mode, the transistors T 8  is disconnected from capacitor C 5  and the transistor T 11  is disconnected from the adder  15 . Therefore, the AC-mode optical receiver operates in a characteristic identical to that shown in FIG.  2 . 
     It is seen that, in DC mode, the peak detectors have low capacitance value and in AC mode their capacitance value is increased. The lower capacitance value of the DC mode makes the optical receiver quickly respond to the varying input level, while the higher capacitance value of the AC mode has the effect of reducing the leakage of the peak detectors.