Abstract:
A pipeline type processor, which is capable of determining a process starting address for each processor constituting the pipeline type processor prior to executing the process for increasing the processing capability of each processor even if the processing condition for each processor vary depending upon the type of ATM cell to be processed, is realized. Prior to cell process by a cell processing section, in which a plurality of processors are provided, an address determining section obtains key information such as the type of cell and the contents of the cell from the input ATM cell, and retrieves a process starting address for each processor by referring to a predetermined address storing table with the key information. The retrieved process starting address for each processor is transferred to the cell processing section, and each processor executes its process from the process starting address when the ATM cell has been stored into a buffer corresponding to own processor.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a pipeline type processor for processing asynchronous transfer mode (ATM) cells, and more particularly relates to a pipeline type processor that determines necessary processing condition for each processor constituting the pipeline type processor and provides the determined condition to each processor in advance of its individual processing in order to cope with the ATM cell processing which is different from each other depending upon cell conditions such as the type of cell and the contents of the cell. 
     2. Description of the Related Art 
     A pipeline type processor is used in a technical field in which a large volume of data such as picture image data is to be processed in a high speed. A plurality of processors are provided in the pipeline type processor, and each processor performs a partial processing dedicated to each processor. Data input into the pipeline type processor is partially processed by each of a plurality of processors one by one like a production line, and output from the pipeline type processor as completely processed data. 
     An example of a system in which all processors in a pipeline type processor can partially process input data in the same processing time is disclosed in Japanese published unexamined patent application No. Hei 1-295335, titled A Load Distribution System. 
     As shown in FIG. 8, the load distribution system disclosed in the above patent application is composed of partial processing  81  to  8 n divided so that processing can be processed in the same time and processors  91  to  9 n for processing data. The above load distribution system is composed so that the partial processing  81  in the processor  91  of precedently input data is finished when the processor  91  receives input data and starts the execution of the partial processing  81 . The residual processors  92  to  9 n and partial processing  82  to  8 n are also similarly composed. 
     However, in the above prior art, there is a defect that if the processing of an input cell is different depending upon a condition such as the type and the contents of the cell, processing is redundant. The reason is that if a series of processing of an input cell is divided into partial processing, processing for determining a condition is required in each partial processing. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to avoid the need to determine a condition by each processor during processing, even if the processing of an input cell is different, depending upon a condition such as the type and the contents of the cell and to increase the quantity of processing that each processor can process within a fixed time during pipeline processing composed of n pieces of partial processing in which processing is finished within predetermined time, for example within one cell time. 
     The present invention made to solve the above problem is based upon a Pipeline type processor for asynchronous transfer mode (ATM) cells provided with input buffers for storing n pieces of asynchronous transmission mode (ATM) cells, n pairs of a processor and a buffer for processing the above each cell according to pipeline processing and an address determining section for determining a condition of pipeline processing. The above address determining section determines a processing instruction code starting address of each cell based upon the information of each cell stored in the input buffer, and the processors sequentially execute pipeline processing based upon the each processing instruction code starting address. 
     That is, in the present invention, in pipeline processing y n pieces of processors in which processing is finished within a predetermined time, for example within one cell time of an ATM cell, if the processing of a input cell is different depending upon a condition such as the type and the contents of the cell, a condition is determined before pipeline processing and the contents of processing composed of n pieces of steps by the processor are determined beforehand. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing a Pipeline type processor for asynchronous transfer mode (ATM) cells according to the present invention; 
     FIG. 2 is a block diagram showing a memory storing a processing instruction code starting address; 
     FIG. 3 is a block diagram showing processors  11 ,  12  and  1 n; 
     FIG. 4 is a block diagram showing the Pipeline type processor for asynchronous transfer mode (ATM) cells according to the present invention provided with an address transferring section; 
     FIG. 5 is a block diagram showing the structure of the memory storing the processing instruction code starting address; 
     FIG. 6 shows an example of the contents of each memory storing code information provided to the processors  11 ,  12  and  1 n; 
     FIG. 7 is a table showing an example of the contents of the memory storing information; and 
     FIG. 8 shows a conventional type ATM cell pipeline processing system. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to the drawings, an embodiment of the present invention will be described below. 
     As shown in FIG. 1, this embodiment includes an input port  100  for receiving a cell, a processing instruction code starting address determining section  107  for determining the address of a processing instruction code read by each processor  11  to  1 n, a cell processing section  106  for processing a cell, (n+1) pieces of buffer memories  20  to  2 n for storing an input cell and an output port  104  for sending a processed cell. 
     The processing instruction code starting address determining section  107  is provided with a cell determining section  108 , an information storing memory  101 , a processing instruction code starting address storing memory  103  and a retrieving section  102 . 
     The cell determining section  108  reads its information from an input cell and determines the type of the cell, reads required information from the information storing memory  101  and generates a condition for retrieval, and informs the retrieving section  102  of the condition. The information storing memory  101  stores information related to a cell stored in a buffer memory. The processing instruction code starting address storing memory  103  stores processing instruction code leading addresses  31  to  3 n which are addresses in memories storing a condition such as the type and the contents of an input cell and processing instruction codes which the processors  11  to  1 n execute. The retrieving section  102  retrieves a condition stored in the processing instruction code starting address storing memory  103  using a condition informed by the cell determining section  108  as a key and retrieves a processing instruction code starting address. 
     The cell processing section is provided with the processors  11  to  1 n and a state transition control section  105 . 
     The processors  11  to  1 n reads a processing instruction code based upon an processing instruction code starting address informed by the processing instruction code starting address determining section  107  and execute the processing of each cell stored in buffer memories  21  to  2 n. The state transition control section  105  controls the state of (n+1) pieces of buffer memories  20  to  2 n. 
     A state in which each processor  11  to  1 n shown in FIG. 1 processes the buffer memories  21  to  2 n is respectively called a state 1, a state 2 and a state n. A cell received by the input port  100  is stored in the buffer memory  20 , the data contents of the input cell is read by the cell determining section  108 , required information is read from the information storing memory  101 , the type of the cell and others are discriminated and a condition for retrieval is informed the retrieving section  102 . The retrieving section  102  retrieves the processing instruction code starting address storing memory  103  under the informed condition, determines the processing instruction code starting address of each processor  11  to  1 n and informs the cell processing section  106  of the address. When the above processing is finished, the buffer memory  20  storing a cell proceeds to the state 1. The processor  11  reads a processing instruction code stored at the processing instruction code starting address determined by the retrieving section  102  and applies processing to the cell in the buffer memory  21  for the state 1. When the processing applied to the cell in the buffer memory for the state 1 is finished, the buffer memory  21  proceeds from the state 1 to the state 2 of the buffer memory  22 , the processor  12  reads a processing instruction code stored in the processing instruction code starting address determined by the retrieving section  102  and applies processing to a cell in the buffer memory  22  for the state 2. Similar processing is sequentially applied up to the processor  1 n. 
     When a state proceeds to the state n of the buffer memory  2 n and processing by the processor in is finished, a series of processing to input cells is finished and is output from the output port  104 . Hereby, processing can be executed without each processor determining a condition. 
     As shown in FIG. 1, a cell received by the input port  100  is written to (n+1) buffer memories  20  to  2 n. The cell determining section  108  reads information from the received cell, determines the type of the cell, reads information related to the cell stores in the buffer memory  20  from the information storing memory  101 , generates a condition for retrieval in combination with the above cell type and informs the retrieving section  102  of the condition. 
     As shown in FIG. 2, the retrieving section  102  retrieves conditions  1  to X in a memory for retrieval  200  using the generated condition as a key. If a condition equivalent to a retrieval key is stored in the memory for retrieval  200 , the retrieving section  102  reads the corresponding processing instruction code starting addresses  31  to  3 n in the states 1 to n from the memory for retrieval  200 . The above processing instruction code starting addresses  31  to  3 n are stored in an address storing memory  300  shown in FIG. 3 in each processor  11  to  1 n via the cell processing section  106 . If a condition equivalent to a retrieval key is not stored in the memory for retrieval  200 , a prepared default processing instruction code starting address is used. 
     The buffer memory  20  proceeds to the state 1 when the above processing is finished and when the state transition control section  105  detects the above transition of the state, the processor  11  starts processing. 
     As shown in FIG. 3, a processing instruction code reading control section  301  reads a processing instruction code starting address from a predetermined address of the address storing memory  300  and reads a processing instruction code based upon the read processing instruction code starting address from a processing instruction code storing memory  304 . The read processing instruction code is decoded by an instruction decoding section  302 , is passed to a processor core  303  and an instruction is executed. When processing is finished, the buffer memory  21  in the state 1 proceeds to the state of the buffer memory  22  and processing is executed by the processor  12 . The state transition control section  105  informs the processing instruction code reading control section  301  of the processor  12  when the above transition of the state is detected. Hereafter, the same processing as in the state 1 is executed. 
     When the processing of the state n is finished, a cell stored in the buffer memory  2 n is output from the output port  104  and the buffer memory  2 n becomes a state waiting for an input cell. 
     Next, the operation of this embodiment will be described using a concrete example. 
     In FIG. 5, a case that processing is different depending upon a condition such as a cell type, a terminal point of a virtual path (VP) and an intermediate point is shown. 
     The processing instruction code starting address storing memory  103  stores the information of a cell type, a VP terminal point and an intermediate point, the processing instruction code starting addresses  31  to  3 n corresponding to the information, an OAM cell and processing instruction code starting addresses  51  to  5 n corresponding to the condition of the VP terminal point. 
     As shown in FIG. 6, processing instruction code storing memories  61  to  6 n (similar to  304  in FIG. 3) respectively corresponding to the processors  11  to  1 n store a processing instruction code when a virtual path identifier (VPI) is  2  at a predetermined address. 
     As shown in FIG. 7, the information of a VP terminal point or an intermediate point corresponding to a value of VPI is stored in the information storing memory  101 . 
     When an operation administration and maintenance (OAM) cell when a virtual path identifier VPI is  2  is received, it is stored in the buffer memory  20 . The cell determining section  108  reads required information from the cell, determines the type of the cell and detects that the cell is an OAM cell. The cell determining section also reads a value (=2) of VPI from a predetermined location in the cell. 
     As shown in FIG. 7, the cell determining section  108  generates an address based upon the value of VPI of  2  and reads information  900  showing a VP terminal point from the information storing memory  101 . The information of the above OAM cell and the VP terminal point is informed by the retrieving section  102 . The retrieving section  102  retrieves the memory for retrieval  200  using the OAM cell and the VP terminal point as a retrieval key. 
     As shown in FIG. 5, as the VP terminal point of the OAM cell is stored in a condition storing area  500  of the memory for retrieval  200 , the retrieving section  102  reads the processing instruction code starting addresses  51  to  5 n (respectively  10 ,  30 ,  20 ) corresponding to the above information and writes the addresses to the address storing memory  300  of each processor  11  to  1 n. When predetermined time, for example one cell time elapses, the buffer storing the cell proceeds to the state 1. 
     The processing instruction code reading control section  301  of the processor  11  reads  10  which is a processing instruction code starting address from the address storing memory  300  and sequentially reads processing instruction codes from the leading address of a processing instruction code area  604  starting from the tenth address of the processing instruction code storing memory  61  shown in FIG.  6 . The read processing instruction code is decoded by the instruction decoding section  302 , is passed to the processor core  303  and is executed. 
     When predetermined time, for example one cell time elapses, control proceeds from the buffer memory  21  to the buffer memory  22  for the state 2. When the state transition control section  105  detects the transition of a state, it informs the processing instruction code reading control section  301  in the processor  12  of the transition. The informed processing instruction code reading control section  301  reads  30  which is a processing instruction code starting address from the address storing memory and sequentially reads processing instruction codes from the leading address of a processing instruction code area  605  starting from the thirtieth address of a processing instruction code storing memory  62 . The subsequent processing is the same as in the case of the state 1. When control proceeds to a buffer memory for the state n, processing instruction codes are sequentially read from the leading address of a processing instruction code area  606  starting from the twentieth address of the processing instruction code storing memory  6 n. 
     When pipeline processing composed of n pieces of steps is finished, a cell stored in the buffer memory  2 n is output from the output port  104 . 
     The embodiment of the present invention is described above, however, the present invention is not limited to this and an address transferring section  400  may be also further provided to the cell processing section  401 . 
     As shown in FIG. 4, the address transferring section  400  is means for transferring an address pointing the leading address for reading a processing instruction code from the processing instruction code storing memory  304  in the processor  12  in case processing by the next processor  12  is different from the result of the processing by the processor  11 . 
     That is, as the operation until a cell is received from the input port  100  and the processor  11  executes the processing of the buffer memory  21  for the state 1 and the operation until processing in the state n is finished and is output from the output port  104  are the same as in the embodiment shown in FIG. 1, the description is omitted. If the processing of the next processor  12  is fixed by the result of the processing by the processor  11 , the operation is the same as the operation in the embodiment shown in FIG.  1 . If the processing of the processor  12  is different from the result of the processing by the processor  11 , the processor core  303  informs the address transferring section  400  of a processing instruction code starting address. The address transferring section  400  stores the processing instruction code starting address in an area which the processing instruction code reading control section  301  reads when a state next proceeds in the address storing memory  300  in the processor  12 . The operation of the processor  12  is the same as the operation of the processor  11  in this embodiment. A series of processing to an input cell is finished by executing such processing in n pieces of processors  11  to  1 n. 
     Hereby, as this embodiment is provided with a mechanism for transferring a processing instruction code starting address between the processors, the subsequent processing can be varied according to the result of processing on the way of pipeline processing. 
     According to the present invention described above, in pipeline processing composed of n pieces of steps in which processing is finished within predetermined time, for example within one cell time, if the processing of an input cell is different depending upon a condition such as the type and the contents of the cell, the condition is not required to be determined in processing by each processor by providing a mechanism for determining an address from which a processing instruction code for each processor is read based upon the condition before pipeline processing. As a result, the redundancy of processing is removed, the quantity of processing which each processor can execute within fixed time is increased and efficient processing is enabled. 
     Particularly, as one cell time is reduced in case a cell is input at high speed and processing instructions executed in one processing are reduced, the present invention is more effective. 
     While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is, therefore, contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.