Abstract:
A voltage regulator circuit includes a differential amplifier circuit that includes a first input terminal and a second input terminal, the first input terminal supplied a reference voltage, an output circuit that receives an output voltage from the differential amplifier circuit to generate a first voltage based on the output voltage, and a control circuit that compares the first voltage with a second voltage, and outputs the first voltage or a third voltage to the second input terminal based on a result of comparing, the second and third voltage being different from the first voltage.

Description:
INCORPORATION BY REFERENCE 
       [0001]    The present application is a Continuation Application of U.S. patent application Ser. No. 12/662,371, filed on Apr. 13, 2010, which is based on Japanese patent application No. 2009-102964, filed on Apr. 21, 2009, the entire contents of which is incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a voltage regulator circuit applied to an IC for driving a liquid crystal panel used in a mobile telephone, a digital camera or the like. 
         [0004]    2. Description of Related Art 
         [0005]    A liquid crystal panel driving IC used in a mobile telephone, a digital camera or the like is increasingly made faster in transmission of data (as high-speed serial transmission) and smaller in size. Due to this, the liquid crystal panel driving IC is often designed by a fine and low voltage process (hereinafter, referred to as “the low voltage process”) capable of using higher-speed and smaller-sized elements. In such a low voltage process, a voltage with which an element is broken down (withstand voltage of the element) necessarily falls. It is, therefore, required to pay attention to the range of a voltage to be used. 
         [0006]    Furthermore, a power supply voltage (battery voltage) supplied from a power supply (battery) to the liquid crystal panel driving IC is often higher than the voltage used in such a low voltage process. Due to this, it is required to use the power supply voltage after regulating the voltage to an appropriate voltage using a voltage regulator circuit included in the liquid crystal panel driving IC. 
         [0007]    Moreover, in a normal case, the power supply voltage is stabilized by a device (such as a stabilization circuit) arranged between the power supply and the liquid crystal panel driving IC, and is supplied to the liquid crystal panel driving IC as a supply voltage as a supply voltage. However, not only an average consumption current but also an instantaneous consumption current is desired to be as low as possible for the liquid crystal panel driving IC since the stabilization circuit includes such a function as a function to prevent overcurrent. 
         [0008]      FIG. 1  shows a configuration of a general voltage regulator circuit  110  (hereinafter, referred to as “the voltage regulator circuit  110 ”). The voltage regulator circuit  110  includes a differential amplifier circuit AMP 1 , a first resistor element R 1  (hereinafter, “the resistor element R 1 ”), and a second resistor element R 2  (hereinafter, “the resistor element R 2 ”). 
         [0009]    The differential amplifier circuit AMP 1  is connected to a high-voltage power supply [VDD] supplying a high voltage VDD and a low-voltage power supply [VSS] supplying a low-voltage VSS (ground voltage GND) lower than the high-voltage VDD, and operates with the voltage between the high-voltage VDD and the low-voltage VSS. The differential amplifier circuit AMP 1  includes a positive-side input terminal +IN that is a first input terminal, a negative-side input terminal −IN that is a second input terminal, and an output terminal. A reference voltage Vref is supplied to the positive-input terminal +IN as the supply voltage. 
         [0010]    One end of the resistor element R 1  is connected to the output terminal of the differential amplifier circuit AMP 1 . One end of the resistor element R 2  is connected to the other end of the resistor element R 1 , and the other end of the resistor element R 2  is connected to the low-voltage power supply [VSS]. One end of the resistor element R 2  is also connected to the negative-side input terminal −IN via a signal line. One end of a smoothing capacitor C 1  is connected to the output terminal of the differential amplifier circuit AMP 1  and one end of the resistor element R 1  via an output node, and the other end of the smoothing capacitor C 1  is connected to the low-voltage power supply [VSS]. 
         [0011]    The resistor elements R 1  and R 2  divide an output voltage Vout 100  output from the differential amplifier circuit AMP 1  into voltages to generate a divided voltage Vmon 100  on one end of the resistor element R 2 . The differential amplifier circuit AMP 1  amplifies the difference between the reference voltage Vref supplied to the positive-side input terminal +IN and the divided voltage Vmon 100  supplied to the negative-side input terminal −IN. The smoothing capacitor C 1  smoothes the output voltage Vout 100  output from the differential amplifier circuit AMP 1 . 
         [0012]      FIG. 2  shows a configuration of the differential amplifier circuit AMP 1 . The differential amplifier circuit AMP 1  includes first and second N channel MOS (Metal Oxide Semiconductor) transistors MN 1  and MN 2  (hereinafter, referred to as “the transistors MN 1  and MN 2 ”), first to third P channel MOS transistors MP 1 , MP 2 , and MP 3  (hereinafter, referred to as “the transistors MP 1 , MP 2 , and MP 3 ”), and first and second constant current sources. 
         [0013]    Sources of the transistors MN 1  and MN 2  are connected to one node in common. Gates of the transistors MN 1  and MN 2  are used as the negative-side input terminal −IN and the positive-side input terminal +IN of the differential amplifier circuit AMP, respectively. 
         [0014]    A first constant current source is provided between the sources of the transistors MN 1  and MN 2  and the low-voltage power supply [VSS]. For example, the first constant current source is a third N channel MOS transistor MN 3  (hereinafter, referred to as “the transistor MN 3 ”). The sources of the transistors MN 1  and MN 2  are connected to the drain of the transistor MN 3 , and the low-voltage power supply [VSS] is connected to the source thereof. A bias voltage Vbias is supplied to the gate of the transistor MN 3  for turning on the transistor MN 3 . 
         [0015]    Sources of the transistors MP 1  and MP 2  are connected to the high-voltage power supply [VDD] in common, gates thereof are connected to one node in common, and drains thereof are connected to drains of the transistors MN 1  and MN 2 , respectively. The gate of the transistor MP 1  is connected to the drain of the transistor MN 1 . 
         [0016]    The source of the transistor MP 3  is connected to the high-voltage power supply [VDD], the gate thereof is connected to the drain of the transistor MN 2 , and the drain thereof is connected to one end of the resistor element R 1 . 
         [0017]    A second constant current source is provided between the drain of the transistor MP 3  and the low-voltage power supply [VSS]. For example, the second constant current source is a fourth N channel MOS transistor MN 4  (hereinafter, referred to as “the transistor MN 4 ”). The drain of the transistor MP 3  is connected to the drain of the transistor MN 4  and the low-voltage power supply [VSS] is connected to the source thereof. The bias voltage Vbias is supplied to the gate of the transistor MN 4  for turning on the transistor MN 4 . 
         [0018]    Next, operation performed by the voltage regulator circuit  110  will be described below. 
         [0019]    The reference voltage Vref is supplied to the positive-side input terminal +IN of the differential amplifier circuit AMP 1 , and the divided voltage Vmon 100  is supplied to the negative-side input terminal −IN of the differential amplifier circuit AMP 1 . Due to this, the differential amplifier circuit AMP 1  operates so that the voltage supplied to the negative-side input terminal −IN is equal to that supplied to the positive-side input terminal +IN, that is, equal to the reference voltage Vref. 
         [0020]    If Vref&gt;Vmon  100  (namely, if the output voltage Vout 100  is lower than a voltage-of-interest), then an ON-resistance of the transistor MP 3  and a current  1100  falls in the smoothing capacitor C 1  via the differential amplifier circuit AMP 1  from the high-voltage power supply [VDD]. As a result, the output voltage Vout 100  rises. If Vref&lt;Vmon 100  (if the output voltage Vout 100  is higher than the voltage-of-interest), then the ON-resistance of the transistor MP 3  rises, and a current Isink flows in the transistor MN 4  included in the differential amplifier circuit AMP 1  from the smoothing capacitor C 1 . As a result, the output voltage Vout falls. By repeating this operation, the output voltage Vout 100  is made constant to the voltage-of-interest. In this case, the output voltage Vout 100 =voltage-of-interest is represented by the following Equation. 
         [0000]        V out= V ref×( R 1+ R 2)/ R 2
 
       SUMMARY OF THE INVENTION 
       [0021]    As stated above, the power supply voltage is often higher than the voltage that can be used in a low voltage process. Due to this, the stabilization circuit stabilizes the power supply voltage and supplies the stabilized power supply voltage to the liquid crystal panel driving IC as the supply voltage. This stabilization circuit includes an overcurrent prevention circuit for preventing an overcurrent. The voltage regulator circuit  100  included in the liquid crystal driving IC regulates the supply voltage from the stabilization circuit to an appropriate voltage and supplies the regulated supply voltage to the low voltage logic circuit as the output voltage Vout. Operation performed by the voltage regulator circuit  110  when the liquid crystal panel driving IC is turned on in such a case will be considered. 
         [0022]    Normally, a power supply starting sequence is applied to the liquid crystal panel driving IC. 
         [0023]    When the liquid crystal panel driving IC is not turned on, then the low-voltage power supply [VSS] is connected to an output of the differential amplifier circuit AMP 1 , that is, to the output node, and the low-voltage power supply voltage VSS (the ground voltage GND) is supplied to the differential amplifier circuit AMP 1  from the low-voltage power supply [VSS]. When the liquid crystal panel driving IC is turned on, then the high-voltage power supply voltage VDD and the reference voltage Vref are generated, and the output of the differential amplifier circuit AMP 1  is disconnected from the low-voltage power supply [VSS]. That is, the voltage regulator circuit  110  starts. 
         [0024]    First, the output voltage Vout 100  is 0 [V] and charge of the smoothing capacitor C 1  is zero at the moment the voltage regulator circuit  110  starts. In this case, the reference voltage Vref and the divided voltage Vmon 100  satisfy Vref&gt;Vmon 100 . A gate voltage Vg of the transistor MP 3  is near 0 [V] to turn the transistor MP 3  almost into the ON-state. Due to this, the ON-resistance of the transistor MP 3  is very low. It is to be noted that a transistor having a large gate width is normally used as the transistor MP 3  so as to ensure capability at normal time. Next, to charge the smoothing capacitor C 1 , the current  1100  flows in the smoothing capacitor C 1  via the differential amplifier AMP 1  from the high-voltage power supply [VDD]. However, the current I 100  becomes very high as the inrush current since the ON-resistance of the transistor MP 3  is very low. The current I 100  at this time is referred to as “the inrush current”. If the inrush current is high, such a problem possibly occurs that the overcurrent prevention circuit of the stabilizing circuit operates. 
         [0025]    Furthermore, the output voltage Vout 100  rapidly rises and exceeds the voltage-of-interest. The voltage which excesses the voltage-of-interest in the output voltage Vout 100  causes the current Isink to flow into the transistor MN 4  included in the differential amplifier circuit AMP 1  from the smoothing capacitor C 1 . As a result, the output voltage Vout 100  is to fall down to the voltage-of-interest. However, the current Isink is normally low and it takes time for the output voltage Vout 100  to be equal to the voltage-of-interest, resulting in occurrence of overshoot. If overshoot occurs, then a voltage of the low voltage logic circuit that uses the output of the voltage regulator circuit main body  110  as a power supply exceeds a process withstand voltage of an element, possibly causing such a defect as breakdown of the element. 
         [0026]      FIG. 5  is a timing chart showing this state. The moment the voltage regulator circuit  110  starts (Power ON), the inrush current increases and overshoot occurs. Therefore, it is desired to reduce the inrush current and the overshoot. 
         [0027]    A circuit described in Japanese Patent Publication JP2005-044203A will be described below. 
         [0028]      FIG. 3  shows a configuration of a circuit (hereinafter, referred to as “the voltage regulator circuit  210 ”) described in the JP2005-044203A. The voltage regulator circuit  210  includes a differential amplifier circuit AMP 200  in place of the differential amplifier circuit AMP 1  of the voltage regulator circuit  110 . 
         [0029]      FIG. 4  shows a configuration of the differential amplifier circuit AMR 200 . The differential amplifier circuit AMP 200  further includes a P channel MOS transistor MP 200  and a switch SW 200 . The source of the transistor MP 200  is connected to the high-voltage power supply [VDD], the gate thereof is connected to the drain of the transistor MN 2 , and the drain thereof is connected to one end of the resistor element R 1 . The transistor MP 200  is relatively small in a gate width so as to increase an ON-resistance of the transistor MP 200 . 
         [0030]    One end of the switch SW 200  is connected to the drain of the transistor MN 2 . The gate of the transistor MP 3  is connected to the other end of the switch SW 200  in place of the drain of the transistor MN 2 . A power-ON signal Pon 200  is supplied to the switch SW 200 . A signal level of the signal Pon 200  is High if the liquid crystal panel driving IC is turned on. At normal time, the signal level of the signal Pon 200  is Low. 
         [0031]    The switch SW 200  is turned off according to the power-ON signal Pon 200  (High), and otherwise turned on. That is, if the liquid crystal panel driving IC is turned on, then the switch SW 200  is turned off, the transistor MP 3  is not used but the transistor MP 200  is used. At the normal time, the switch SW 200  is turned on and the transistor MP 3  is used. 
         [0032]    However, in this case, similarly to the previous case, a gate voltage Vg of the transistor MP 200  is almost 0 [V] right and the transistor MP 200  is turned into an almost complete ON-state right after the liquid crystal panel driving IC is turned on. Due to this, it is difficult to sufficiently increase the ON-resistance. 
         [0033]    According to an aspect of the present invention, a voltage regulator circuit includes: a differential amplifier circuit, a reference voltage is supplied to a first input of the differential amplifier circuit, and a smoothing capacitor is connected to an output of the differential amplifier circuit; a first resistor element whose one end is connected to the output of the differential amplifier circuit; a second resistor element whose one end is connected to another end of the first resistor element; a first switch, one end of the first switch is connected to the first input of the differential amplifier circuit, another end of the first switch is connected to a second input of the differential amplifier circuit, and the first switch is configured to be turned on in response to a first control signal; a second switch, an end of the second switch is connected to the second input of the differential amplifier circuit, another end of the second switch is connected to the second resistor element, and the second switch is turned on in response to a second control signal; and a switch control circuit configured to output the first control signal in a predetermined period from a power supply is turned on, and to output the second control signal after the predetermined period. 
         [0034]    In the voltage regulator circuit according to an aspect of the present invention, if the voltage regulator circuit is turned on, then the switch is turned on according to the first control signal, the second switch is turned off, and the reference voltage is supplied, as a same voltage, to the first input and the second input of the differential amplifier circuit. If the voltage supplied to the first input of the differential amplifier circuit is equal to that supplied to the second input terminal thereof, a current value of the current flowing from the high-voltage power supply to the smoothing capacitor via the differential amplifier circuit is limited to low. That is, the inrush current can be reduced. Furthermore, the voltage regulator circuit according to the aspect of the present invention can reduce the overshoot because of gradual rise of the output voltage output from the differential amplifier circuit. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0035]    The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred exemplary embodiments s taken in conjunction with the accompanying drawings, in which: 
           [0036]      FIG. 1  is a schematic diagram showing a configuration of a general voltage regulator circuit  110  (voltage regulator circuit  110 ); 
           [0037]      FIG. 2  is a schematic diagram showing a configuration of a differential amplifier circuit AMP 1 ; 
           [0038]      FIG. 3  is a schematic diagram showing a configuration of a circuit (voltage regulator circuit  210 ) described in Japanese Patent Publication No. 2005-044203A; 
           [0039]      FIG. 4  is a schematic diagram showing a configuration of a differential amplifier circuit AMP 200 ; 
           [0040]      FIG. 5  is a timing chart showing an operation performed by the voltage regulator circuit  110 ; 
           [0041]      FIG. 6  is a schematic diagram showing a configuration of a device using a voltage regulator circuit  30  according to an embodiment of the present invention; 
           [0042]    FIG,  7  is a schematic diagram showing a configuration of the voltage regulator circuit  30  according to an embodiment of the present invention; and 
           [0043]      FIG. 8  is a timing chart showing operation performed by the voltage regulator circuit  30  according to an embodiment of the present invention. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0044]    Hereinafter, some embodiments of the present invention will be described below with reference to the attached drawings. 
         [0045]    [Configuration] 
         [0046]      FIG. 6  shows a configuration of a device using a voltage regulator circuit  30  according to an embodiment of the present invention. The device is used in a mobile telephone, a digital camera or the like, and includes a power supply section  34 , a stabilization circuit  32 , and a liquid crystal panel driving IC. The liquid crystal panel driving IC includes the voltage regulator circuit  30  according to this embodiment of the present invention (also referred to as “voltage regulator circuit  30 ”), a low voltage logic circuit  31 , and a smoothing capacitor C 1 . 
         [0047]    An output of the power supply section  34  is connected to an input of the stabilization circuit  32 . An output of the stabilization circuit  32  is connected to an input of the voltage regulator circuit  30 . One end of the smoothing capacitor C 1  is connected to an output of the voltage regulator circuit  30 , and the other end of the smoothing capacitor C 1  is grounded. The low voltage logic circuit  31  is connected to the output of the voltage regulator circuit  30 . 
         [0048]    The low voltage logic circuit  31  operates with voltage-of-interest VO that is a first voltage. 
         [0049]    When a user performs an instruction to turn on the device, the power supply section  34  (battery) supplies a power supply voltage VB (battery voltage) that is a second voltage to the stabilization circuit  32 . The power supply voltage VB is higher than the voltage-of-interest VO. 
         [0050]    The stabilization circuit  32  stabilizes the power supply voltage VB to a supply voltage VDC and supplies the supply voltage VDC to the liquid crystal display panel driving IC. The stabilization circuit  32  includes an overcurrent prevention circuit  33  for preventing overcurrent. 
         [0051]    The supply voltage VDC from the stabilization circuit  32  is input to the voltage regulator circuit  30  included in the liquid crystal panel driving IC as a reference voltage to be described later. The voltage regulator circuit  30  regulates the reference voltage to an appropriate voltage (voltage-of-interest VO) and supplies the appropriate voltage to the low voltage logic circuit  31  as an output voltage to be described later. 
         [0052]      FIG. 7  shows a configuration of the voltage regulator circuit  30  according to this embodiment of the present invention. It is to be noted that the same constituent elements as those of the voltage regulator circuit  110  (see  FIGS. 1 and 2 ) are denoted by the same reference numerals, respectively. 
         [0053]    The voltage regulator circuit  30  includes a voltage regulator circuit main body  10 . The voltage regulator circuit main body  10  includes a differential amplifier circuit AMP 1  a first resistor element R 1  (hereinafter, referred to as “the resistor element R 1 ”), and a second resistor element R 2  (hereinafter, referred to as “the resistor element R 2 ”). 
         [0054]    The differential amplifier circuit AMP 1  is connected to a high-voltage power supply [VDD] supplying a high-voltage power supply voltage VDD and a low-voltage power supply [VSS] supplying a low-voltage power supply voltage VSS (ground voltage GND) lower than the high-voltage power supply voltage VDD. The differential amplifier circuit AMP 1  operates with a voltage between the high-voltage power supply voltage VDD and the low-voltage power supply voltage VSS. The differential amplifier circuit AMP 1  includes a positive-side input terminal +IN that is a first input terminal, a negative-side input terminal −IN that is a second input terminal, and an output terminal. The reference voltage Vref serving as the supply voltage VDC is supplied to the positive-side input terminal +IN. 
         [0055]    The configuration of the differential amplifier circuit AM 1  is the same as that shown in  FIG. 1 . 
         [0056]    One end of the resistor element R 1  is connected to the output final of the differential amplifier circuit AM 1 . One end of the resistor element R 2  is connected to the other end of the resistor element R 1  and the other end of the resistor element R 2  is connected to the low-voltage power supply [VSS]. One end of the resistor element R 2  is also connected to the negative-side input terminal −IN via a signal line. One end of the smoothing capacitor C 1  is connected to the output terminal of the differential amplifier circuit AMP 1  and to one end of the resistor element R 1  via an output node. The other end of the smoothing capacitor C 1  is connected to the low-voltage power supply [VSS]. 
         [0057]    The resistor elements R 1  and R 2  divide an output voltage Vout output from the differential amplifier circuit AMP 1  into voltages to generate a divided voltage Vmon on one end of the resistor element R 2 . The differential amplifier circuit AMP 1  amplifies a difference between the reference voltage 
         [0058]    Vref supplied to the positive -side input terminal +IN and the divided voltage Vmon supplied to the negative-side input terminal −IN. The smoothing capacitor C 1  smoothes the output voltage Vout output from the differential amplifier circuit AMP 1 . 
         [0059]    A common power supply starting sequence applied to a liquid crystal panel driving IC will now be described. 
         [0060]    When the device is not turned on, the low-voltage power supply [VSS] is connected to the output of the differential amplifier circuit AMP 1 , that is, to an output node and the low-voltage power supply [VSS] supplies the low-voltage power supply voltage VSS (ground voltage). When the device is turned on, then the high-voltage power supply voltage VDD and the reference voltage Vref (ground voltage GND) are generated, and the output of the differential amplifier circuit AMP 1  is then disconnected from the low-voltage power supply [VSS]. That is, the voltage regulator circuit  10  starts. 
         [0061]    First, the output voltage Vout is 0 [V] and the charge of the smoothing capacitor C 1  is zero the moment the voltage regulator circuit main body  10  starts. In this case, as stated above, a gate voltage Vg of a transistor MP 3  (see  FIG. 2 ) included in the differential amplifier circuit AMP 1  is near 0 [V] to turn the transistor MP 3  almost into an ON-state. Due to this, an ON-resistance of the transistor MP 3  is very low. Next, to charge the smoothing capacitor C 1 , a current I flows in the smoothing capacitor C 1  via the differential amplifier AMP 1  from the high-voltage power supply [VDD]. However, the current I is very high as an inrush current since the ON-resistance of the transistor MP 3  is very low. If the inrush current is high, such a problem possibly occurs that the overcurrent prevention circuit  33  of the stabilizing circuit  32  operates. 
         [0062]    Furthermore, the output voltage Vout suddenly rises and exceeds the voltage-of-interest VO. A voltage amount of the output voltage Vout by as much as which the output voltage Vout exceeds the voltage-of-interest VO causes a current Isink (see  FIG. 2 ) to flow into a transistor MN 4  included in the differential amplifier circuit AMP 1  from the smoothing capacitor C 1 . As a result, the output voltage Vout is to fall down to the voltage-of-interest VO. However, the current Isink is normally low and it takes time for the output voltage Vout to be equal to the voltage-of-interest VO, resulting in occurrence of overshoot. If overshoot occurs, then a voltage of the low voltage logic circuit  31  that uses the output of the voltage regulator circuit main body  10  as a power supply exceeds a process withstand voltage of an element, possibly causing such a defect as breakdown of the element. 
         [0063]    Considering these, the voltage regulator circuit  30  further includes a switch control circuit  20  and first and second switches SW 1  and SW 2  (hereinafter, referred to as “the switches SW 1  and SW 2 ”) for reducing the inrush current and the overshoot. 
         [0064]    The switch SW 1  is provided between the positive -side input terminal +IN and the negative-side input terminal −IN. Specifically, one end of the switch SW 1  is connected to the positive-side input terminal IN and the other end of the switch SW 1  is connected to the negative-side input terminal −IN. 
         [0065]    The switch SW 2  is provided on a signal line connecting the negative-side input terminal −IN to one end of the resistor element R 2 . Specifically, one end of the switch SW 2  is connected to the negative-side input terminal −IN and the other end of the switch SW 2  is connected to one end of the resistor element R 2 . 
         [0066]    A first control signal CTR 1  (hereinafter, referred to as “the control signal CTR 1 ”) is supplied to the switch SW 1  from the switch control circuit  20 . If a signal level of the control signal CTR 1  is High, the switch SW 1  is turned on. If the signal level of the control signal CTR 1  is Low, the switch SW 1  is turned off. 
         [0067]    A second control signal CTR 2  (hereinafter, referred to as “the control signal CTR 2 ”) is supplied to the switch SW 2  from the switch control circuit  20 . If a signal level of the control signal CTR 2  is High, the switch SW 2  is turned on. If the signal level of the control signal CTR 2  is Low, the switch SW 2  is turned off. The control signal CTR 2  has a signal level inverted with respect to a signal level of the control signal CTR 1 . 
         [0068]    The switch control circuit  20  sets the signal level of the control signal CTR 1  High and that of the control signal CTR 2  Low in a period before a predetermined period passes since the device is turned on. In this case, the switch SW 1  is turned on and the switch SW 2  is turned off. The control signals CTR 1  and CTR 2  supplied during this period will be described later in detail. 
         [0069]    At normal time (after the predetermined period), the switch control circuit  20  sets the signal level of the control circuit CTR 1  Low and that of the control signal CTR 2  High. In this case, the switch SW 1  is turned off and the switch SW 2  is turned on. 
         [0070]    A configuration of the switch control circuit  20  will be described. The switch control circuit  20  includes a converter COMP 1 , a negative AND arithmetic circuit NAND 1 , and a NOT arithmetic circuit INV 1 . 
         [0071]    The comparator COMP 1  is connected to the high-voltage power supply [VDD] and the low-voltage power supply [VSS], and operates with a voltage between the high-voltage power supply voltage VDD and the low-voltage power supply voltage VSS. The comparator COMP 1  includes a positive-side input terminal that is a first input terminal, a negative-side input terminal that is a second input terminal, and an output terminal. The reference voltage Vref is supplied to the positive-side input terminal of the comparator COMP 1  as a supply voltage. The negative-side input terminal of the comparator COMP 1  is connected to one end of the resistor element R 2 , and the divided voltage Vmon is supplied to the negative-side input terminal of the comparator COMP 1 . The comparator COMP 1  compares the divided voltage Vmon with the reference voltage Vref and outputs a comparison result signal Vcomp representing a comparison result from the output terminal. 
         [0072]    The NAND arithmetic circuit NAND 1  includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the NAND arithmetic circuit NAND 1  is connected to the output terminal of the comparator COMP 1 , and the comparison result signal Vcomp is supplied to the first input terminal of the NAND arithmetic circuit NAND 1 . A power-on signal Pon is supplied to the second input terminal of the NAND arithmetic circuit NAND 1 . A signal level of the power-on signal Pon is High until passage of predetermined time since the device is turned on. At normal time, the signal level of the power-on signal Pon Low. The output terminal of the NAND arithmetic circuit NAND 1  is connected to the switch SW 2 , and an output of the NAND arithmetic circuit NANDI is supplied to the switch SW 2  as the control signal CTR 2 . 
         [0073]    The NOT arithmetic circuit INV 1  includes an input terminal and an output terminal. The input terminal of the NOT arithmetic circuit INV 1  is connected to the output terminal of the NAND arithmetic circuit NAND 1 . The output terminal of the NOT arithmetic circuit INV 1  is connected to the switch SW 1 , and an output of the NOT arithmetic circuit INV 1  is supplied to the switch SW 1  as the control signal CTR 1 . 
         [0074]    [Operation] 
         [0075]      FIG. 8  is a timing chart showing operation performed by the voltage regulator circuit  30 . 
         [0076]    A normal operation will first be described. At the normal time (during a normal control period shown in  FIG. 8 ), the signal level of the power-on signal Pon is Low. In this case, a signal level of the NAND arithmetic circuit NAND is High and that of the output of the NOT arithmetic circuit INV is Low irrespectively of the output of the comparator COMP. That is, signal levels of the control signals CTR 1  and CTR 2  are Low and High, respectively. As a result, the switch SW 1  is turned off, and the switch SW 2  is turned on according to the control signal CTR 2  (High). At this time, the negative-side input terminal −IN of the differential amplifier circuit AMP 1  is connected to one end of the resistor element R 2 . At the normal time, the voltage regulator circuit main body  10  is similar in a state to the voltage regulator circuit  110  and the output voltage Vout output from the differential amplifier circuit AMP 1  is controlled to the constant to the voltage-of-interest VO. 
         [0077]    Operation performed by the voltage regulator  30  when the device is turned on will be described. 
         [0078]    When the device is not turned on, the low-voltage power supply voltage VSS (ground voltage GND) is supplied to the output of the differential amplifier circuit AMP 1 . When the device is turned on (Power ON in  FIG. 8 ), then the high-voltage power supply voltage VDD and the reference voltage Vref are generated, and supply of the low-voltage power supply voltage VSS to the output of the differential amplifier circuit AMP 1  is stopped. In addition, until passage of the predetermined time since the device is turned on (power-ON control period in  FIG. 8 ), the signal level of the power-ON signal Pon is High. 
         [0079]    Right after the device is turned on (Power ON in  FIG. 8 ), the output voltage Vout is 0 [V] and the charge of the smoothing capacitor C 1  is zero. In this case, the divided voltage Vmon obtained by causing the resistor elements R 1  and R 2  divide the output voltage Vout is also 0 [V]. At this time, the reference voltage Vref is higher than the divided voltage Vmon. That is, the reference voltage Vref and the divided voltage satisfy Vmon Vref&gt;Vmon. Due to this, the signal level of the comparison result signal Vcomp output from the comparator COMP 1  is High. 
         [0080]    As stated above, the signal level of the power-ON signal Pon is High. In this case, the signal level of the output of the NAND arithmetic circuit NAND is Low and that of the output of the NOT arithmetic circuit INV is High. That is, the signal levels of the control signals CTR 1  and CTR 2  are High and Low, respectively. As a result, the switch SW 1  is turned on according to the control signal CTR 1  (High), and the switch SW 2  is turned off. At this time, the negative-side input terminal −IN of the differential amplifier circuit AMP 1  is connected to the positive-side input terminal +IN thereof. Accordingly, the reference voltage Vref is supplied, as a same voltage, to the positive side input terminal +IN and the negative-side input terminal −IN of the differential amplifier circuit AMP 1 . 
         [0081]    The operation performed by the switch control circuit  20  for outputting the control signal CTR 1  (High) when the reference voltage Vref is higher than the divided voltage Vmon during the predetermined period will be red to as “the first operation”. 
         [0082]    Next, during the predetermined period, the voltage supplied to the positive-side input terminal +IN of the differential amplifier circuit AMP 1  is equal to that supplied to the negative-side input terminal −IN thereof. At this time, a gate voltage Vg of the transistor MP 3  (see  FIG. 2 ) included in the differential amplifier circuit AMP 1  is near a threshold voltage Vt. Due to this, an ON-resistance of the transistor MP 3  is relatively high. Next, to charge the smoothing capacitor C 1 , the current I flows in the smoothing capacitor C 1  via the differential amplifier circuit AMP 1  from the high-voltage power supply [VDD]. However, a current value of the current I is limited to low because of the high ON-resistance of the transistor MP 3 , so that the output voltage Vout output from the differential amplifier circuit AMP 1  gradually rises. 
         [0083]    Next, during the predetermined period, the output voltage Vout exceeds the voltage-of-interest VO. At this time, the divided voltage Vmon divided by the resistor elements R 1  and R 2  exceeds the reference voltage Vref. In this case, because of Vref&lt;Vmon, the signal level of the comparison result signal Vcomp output from the comparator COMP 1  is inverted to Low. Since the signal level of the power-ON signal Pon is High, the signal level of the NAND arithmetic circuit NAND 1  is High and that of the output of NOT arithmetic circuit INV 1  is Low. That is, the signal levels of the control signals CTR 1  and CTR 2  are Low and High, respectively. As a result, the switch SW 1  is turned off, and the switch SW 2  is turned on according to the control signal CTR 2  (High). At this time, the negative-side input terminal −IN of the differential amplifier circuit AMP 1  is connected to one end of the resistor element R 2 . 
         [0084]    Operation performed by the switch control circuit  20  for outputting the control signal CTR 2  (High) if the divided voltage Vmon is higher than the reference voltage Vref during the predetermined period will be referred to as “the second operation”. 
         [0085]    Next, during the predetermined period, the output voltage Vout is controlled to be constant. If the output voltage Vout falls to be lower than the reference voltage Vref, that is, Vref&gt;Vmon, then the switch SW 1  is turned on according to the control signal CTRL (High), the switch SW 2  is turned off, and the output voltage Vout rises. That is, the switch control circuit  20  re-executes the first operation. The switch control circuit  20  alternately executes the first and second operations until the output voltage Vout is made equal to the voltage-of-interest VO. 
         [0086]    After passage of the predetermined time, the signal level of the power-ON signal Pon is Low and the voltage regulator circuit  30  executes normal operation. That is, at the normal time, the voltage regulator circuit main body  10  is similar in state to the voltage regulator circuit  110  and the output voltage Vout is controlled to be constant to the voltage-of-interest VO. 
         [0087]    In the voltage regulator circuit  30  according to this embodiment of the present invention, if the voltage regulator circuit  30  is turned on, then the switch SW 1  is turned on according to the control signal CTR 1  (High), the switch SW 2  is turned off, and the reference voltage Vref is supplied, as the voltage, to the positive-side input terminal +IN and the negative-side input terminal −IN of the differential amplifier circuit AMP 1 . If the voltage supplied to the positive-side input terminal +IN of the differential amplifier circuit AMP 1  is equal to that supplied to the negative-side input terminal −IN thereof, the current value of the current I flowing from the high-voltage power supply [VDD] to the smoothing capacitor C 1  via the differential amplifier circuit AMP 1  is limited to low. Specifically, if the voltage supplied to the positive-side input terminal +IN of the differential amplifier circuit AMP 1  is equal to that supplied to the negative-side input terminal −IN thereof, the gate voltage Vg of the transistor MP 3  (see  FIG. 2 ) included in the differential amplifier circuit AMP 1  is near the threshold voltage Vt. Due to this, the ON-resistance of the transistor MP 3  is relatively high. To charge the smoothing capacitor C 1 , the current I flows in the smoothing capacitor C 1  via the differential amplifier circuit AMP 1  from the high-voltage power supply [VDD]. However, the current value of the current I is limited to low because of the high ON-resistance of the transistor MP 3 . That is, the inrush current can be reduced. Furthermore, the voltage regulator circuit  30  according to this embodiment of the present invention can reduce the overshoot because of gradual rise of the output voltage Vout output from the differential amplifier circuit AMP 1 . 
         [0088]    Although the present invention has been described above in connection with several exemplary embodiments thereof, it would be apparent to those skilled in the art that those exemplary embodiments are provided solely for illustrating the present invention, and should not be relied upon to construe the appended claims in a limiting sense.