Abstract:
An information processing system and method forms a fast optimal or near optimal association based on satisfying global constraints expressed in an association matrix by simulating the behavior of a network of interconnected processing elements resembling neurons in a brain.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a signal processing system and method, and in particular to a hardware implementation of a neural network-based signal processing system and method. 
     2. Description of Related Art 
     Present approaches to data fusion, unlike the approach of the invention, are purely mathematical in nature. No apparatus currently exists which is specifically designed for data fusion. Instead, the common practice is to run traditional association techniques, such as the sub-optimal nearest neighbor technique or the optimal Munkres algorithm, on a conventional or parallel general purpose computer. 
     Association techniques can be applied to a large class of problems arising from real-world situations, including target tracking and telecommunications. The approach for solving this class of problems usually involves minimizing some quantity referred to as a cost. A cost may, for example, be related to the dissimilarity of objects to be associated, the energy required to perform a specific operation, the distance to be traveled, or money to be spent. 
     A typical association problem involves combining the information from two or more sources referring to the same set of objects. The association from one source of information about a particular object to another source of information about the same object is trivial if the two sources have no ambiguity about the objects. However, in many real-world situations, uncertainties in the information make the associations nontrivial. One such situation, illustrated in FIG. 1, is the situation where information about a given object from more than one sensor is combined. The information combination technique, called sensor fusion, produces information about an object by fusing information from several sources. The sensor fusion technique must unambiguously associate data from each sensor that corresponds to a given object. 
     FIG. 1 illustrates the situation where two sensors A and B are used to measure the position of several objects. Sensor A may, for example, have fine resolution in its range measurement and course resolution in its azimuth measurement while sensor B has poorer range resolution and better azimuth resolution. Assuming that the third report from sensor A indicates that there is an object at location A3 and the fifth report from sensor B indicates an object at location B5. Given the uncertainties in sensor A, the true position of the object described in the third report from sensor A (shown as a diamond) may be anywhere within the error ellipse labelled &#34;A&#34; in FIG. 1, while the location of the object described in the fifth report from sensor B can be anywhere within the error ellipse labeled B in the figure. If it were possible to note that the third report from sensor A refers to the same object as the fifth report from sensor B, then the range from sensor A combined with the azimuth from sensor B would provide more accurate information about that object than either sensor&#39;s data taken individually. If there is only one object in the vicinity and both sensors see only that object, the association of A3 to B5 is trivial, but the association process becomes nontrivial when there are several objects in the error ellipses or one sensor sees objects that the other misses. The solution then requires an association that considers the global effect of making associations which may not necessarily be the best local associations. 
     FIG. 2 illustrates the situation where the field of view includes two objects and it is known that each sensor detected only those two objects. In this case, one could use the distance between reports as the cost function to be minimized. At first glance, it appears that reports A3 and B5 would need to be associated with the same object, as in the first example, simply because they are closest and have the least cost of association. Unfortunately, the consequence of this decision is to require that report A4 be associated to B1, which has a large cost. If this were the decision, the sum of the large cost and the small cost would be greater than the sum of the costs if the associations A4 to B5 and A3 to B1 were chosen. 
     To take into account all of the necessary associations, the complexity of which increases rapidly with increasing numbers of objects, the decisions may be formed into an association matrix, as shown in FIG. 3. This matrix contains a measure of closeness, scaled from -1 to +1, of each report from sensor A relative to each report from sensor B. Sensor A reports are indexed by column and sensor B reports are indexed by row. In this case, row 1, column 3, by way of example, contains a measure of closeness based on some function of the inverse distance between the ports B1 and A3. The closeness measure is 1-(k)(d ij  /d ave ) for close reports and -1 for distant reports, where k is a positive constant, d ij  is the distance between the ith report from sensor A to the jth report from sensor B, and d ave  is the average of all the distances. If the two reports were at the same position, this entry be +1. If they were very far apart, the entry would be -1. In FIG. 3, the matrix entry is 0.2, indicating a possible but not excellent match. 
     To simplify the problem, the selection of a similarity measure may include thresholds so that reports that are too dissimilar (for example, when sensor A sees an object and sensor B does not), have entries of zero or less in the matrix, and the associations can be immediately disregarded. 
     An unequal number of reports from each sensor would result in a matrix that would not be square. If an entry of +1 in the matrix represents a match between reports sharing the same row and column, then the solution would result in a matrix with at most one +1 in each row, at most one +1 in each column, and all other entries equaling -1. As the size of the n×m matrix increases, the number of possible solutions containing at most one +1 in each row and column grows faster than N! where N is the minimum of m and n. It is clear that exhaustive searches are impractical for problems involving large matrices. 
     Several techniques have been devised to provide solutions where the total cost is very low (near optimal) or the lowest cost possible (optimal). For the most part, these traditional association techniques, designed to be run on conventional or parallel general purpose computers, either take too long to be practical, or produce answers that have unacceptable inaccuracies under certain conditions. In addition, the traditional techniques tend to force associations to happen even when it may be better to defer the decision until more information is available, i.e., allow some rows and columns of the association matrix to have all entries equal -1. 
     SUMMARY OF THE INVENTION 
     It is accordingly an objective of the invention to provide apparatus specifically designed to produce near optimal associations for very large problems, very quickly. 
     It is a further objective of the invention to provide a method of producing near optimal associations for very large problems which, unlike conventional optimal association techniques run on a general purpose computer, is optimized for specific apparatus. 
     It is a still further objective of the invention to provide a circuit capable of producing near optimal associations for very large problems, very quickly. 
     These objectives are achieved, according to a preferred embodiment of the invention, by providing a circuit which represents a neural network connected to resolve an association matrix from an initial state containing closeness measures to a final state with at most one +1 in each row and column. The circuit of the preferred embodiment includes a plurality of circuit components arranged to transform and replace electrical signals representative of neuron values stored in a memory device by electrical signals obtained as a result of an iterative procedure carried out by the preferred circuit. 
     The term &#34;neural network&#34; as used herein refers to a system of simple processing elements or neurons connected together in a way that causes their interaction to converge to a stable state. The stable state is the solution to the problem to be solved. The state of each neuron is governed by a differential equation which, as it evolves with time, may be thought of as a trajectory through n×m dimensional space. In that space, special points with coordinates of +1 and -1 can represent association matrices. Typically, a trajectory starts in the space at a point determined by sensor data and subsequently approaches one of the special points that represents an optimal or near optical association. 
     The preferred encoding for the solution space of the neural network is an association matrix of the type shown in FIG. 3. Each entry in the matrix has a corresponding neuron that receives its inputs from neurons belonging to the same row and column, as illustrated in FIG. 4 for the neuron at entry 1, 1. In this type of network, interconnection weights are fixed and are therefore not a function of the problem to be solved. This is a distinct advantage over other neural network models that require new weights for each problem and long set up computations. The present invention uniquely uses the association matrix to set the initial state of the matrix neurons and represents the evolution of neuron states as time advances in terms of a trajectory in state space. The trajectories ultimately converge to a stable state which represents the answer. The stable state has at most one +1 in each row and column of the neuron matrix and the remaining neurons will come to rest at -1. 
     The relationship between stored neuron values from one iteration to the next is conveniently described in terms of a mathematical formula. Those skilled in the art should understand, however, 1.) that the mathematical formula is merely a convenient way of describing the circuit, 2.) that any circuit in which an electrical signal is transformed can be described mathematically and that such a description does not make the circuit any less tangible, 3.) that any physical combination of electrical signals can be described as an addition or multiplication operation, 4.) that digital operations also involve manipulation of electrical signals, and 5.) that a neural network, although conveniently described in terms of matrices, is still a physical apparatus requiring a specific (albeit modifiable) arrangement of memory cells and interconnections. With these points in mind, the mathematical formula which describes how the preferred neural network operates is as follows: 
     
         Δx.sub.i =Δt[-x.sub.i -a+kG(x.sub.i)(b-F(ROW j SUM-H(x.sub.i)-c)-F(COL m SUM-H(x.sub.i)-d))], 
    
     where Δx i  is the change in neuron value x i  from one iteration to the next, ROW j SUM and COL m SUM are variables representing the sums of functions H(x i ) and H(x m ) of all neuron values in the row and column containing neuron i; a, b, c, d, and k are positive constants; and H, G, and F are operators defined by functions, described in more detail below. This mathematical formula describes the evolution of neuron states as time advances as a trajectory in state space. The functions H, G, and F are ramp or ramp-approximation functions for computational simplicity (see equations (1) and (2), infra). 
     The apparatus of the preferred embodiment of the invention includes a state memory in which signals representative of neuron values x i  are stored at locations defined by respective row and column indexes j and m. An active list memory contains addresses of all neurons with x i  greater than -e. As the preferred apparatus iteratively processes neuron values, the active list memory maintains an active list containing all x i  &#39;s that contribute to formation of the new neuron values. After each iteration, the active list is updated. When the neuron values converge, the active list contains the solution to the problem. The operators H, G, and F used to transform the active neuron signals during processing are applied, in this embodiment, by look-up tables, while the subtraction, addition, and multiplication functions are carried out by appropriate signal combining circuits. While some of the functions of the preferred circuit may be carried out by software, those skilled in the art will appreciate that the functions are optimally carried out by hard-wired components. 
     The preferred neural network operates to solve an association problem as follows: 
     Initially, all row and column accumulation variables stored in a row sum memory and a column sum memory are set to zero. Then, for each neuron value x i  in the active list, the row index and column index are found, and H(x i ) is obtained and added to the existing row and column sum variables. Next, for each neuron in the active list, a new x i  is obtained by finding the row index and column index and then transforming the old x i  into a new x i  which varies from the old x i  by an amount equal to Δx i . The new xi is stored in the state memory if the new neuron value is greater than -e, at which time the address of the new x i  is written into the active list for the next iteration. If any Δx i  computed in an iteration is less than zero, another iteration is performed. After the last iteration, all of the neuron values in the active list are interpreted as equal to +1, and the neurons not in the active list are interpreted as equal to -1. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram which illustrates the principles of sensor fusion utilized by the present invention. 
     FIG. 2 is a schematic diagram further illustrating the principles of sensor fusion. 
     FIG. 3 shows an example of an association matrix for use in analyzing problems of type represented by the schematic diagrams of FIGS. 1 and 2. 
     FIG. 4 is an illustration of a neural network representation for an association matrix of the type shown in FIG. 3, according to the present invention. 
     FIG. 5 is a block diagram of a hardware implementation of a neural network according to a preferred embodiment of the invention. 
     FIG. 6 is a continuation of the block diagram of FIG. 5. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The evolution of neuron states as time advances may be represented as a trajectory in state space. These trajectories ultimately converge to a stable state which represents the answer. The stable state will have at most one +1 in each row and column of the neuron matrix and the remaining neurons will come to rest at -1. 
     The output of each neuron is controlled by the following differential equation: 
     
         dx.sub.i /dt=-x.sub.i -a+kG(x.sub.i)(b-F(ΣH(x.sub.j)-c)-F(ΣH(x.sub.j)-d)); jεR.sub.i &#39;; mεC.sub.i &#39;                  (1) 
    
     where a, b, c, d, and k are constants, F, G, and H are functions, R i  &#39; is the set of indexes corresponding to input to neuron i from the same row as neuron i (not including H(x i ) itself), and C i  &#39; is the set of indexes corresponding to inputs to neuron i from the same column as neuron i (not including H(x i ) itself). 
     For computational simplicity, functions F, G and H may be represented as ramp or ramp- approximation functions limited to the closed range between 0 and 1 inclusive. More specifically: 
     
         F(z)=G(z)=H(z)={0 if z≦-e, 1 if z≧+e, and continuous and monotonic if -e&lt;z&lt;+e}                                     (2) 
    
     While this expression is specified only for a two-dimensional association matrix, i.e., a matrix where only two information sources are to be associated, the model may in general be expanded to cases where n sources are to be associated by adding one dimension to the matrix for each source, and by adding sum terms for each dimension. 
     Based on an understanding of the behavior of the dynamical system defined by equations (1) and (2), a number of computational simplifications may be made. For purposes of the invention, the following three observations are important: 
     1.) The trajectory of a neuron reaches a point of no return when G(x i )=0. From the description of dx i  /dt in equation (1), x i  will never become positive once x i  goes below -e. Further, if an x i  goes below -e, it does not contribute to any changes in any other neuron. Therefore, any such neuron may immediately assume an output of -1 (x i  =-1). When this happens, no further computations for neuron i are necessary. 
     2.) If a neuron output x i  goes below -e, it can no longer contribute to any changes in the system, so i may be removed from the sets R i  &#39; and C i  &#39;, thus saving additional computation. 
     3.) The sums ΣH(x i ) and ΣH(x m ) need not be computed for each x i  separately. It is far more efficient to compute the complete sums once for all j in the given dimension (row, column, etc.) and subtract the single value H(x i ) for each x i  evaluation. This saves 2n 3  -5n 2  add operations for an n×n matrix. If n=1000, a savings of 1.995×10 9  add operations results. 
     The preferred embodiments of the invention utilize these observations to provide an efficient method of simulating the dynamical system as difference equations in discrete time. In addition, the circuit of the preferred embodiment takes advantage of the general principle that, where n is large, it is acceptable to find a very good answer rather than the very best as long as the answer can be found quickly. The neural network-based apparatus and method of the present invention provides a signal processing method and hardware implementation that can produce very good answers for problems of this type where n is large (in excess of 10,000) and the time required is short (on the order of seconds). It uses an iterative process applied to a neural network to quickly resolve the abovedescribed matrix, represented by stored neuron values, from an initial state containing the closeness measures, to a final state with at most one +1 in each row and column. 
     As shown in FIG. 5, a neural network constructed in accordance with the above-described principles of the preferred embodiment of the invention includes a state memory 1 in which signals representative of active neurons with values greater than a threshold -e are stored. All other neuron values are set equal to -1. As will be explained below, the row and column addresses for the state memory 1 are supplied by an active list memory 2 in response to the outputs of counters 5 and 7 based on index clock (index clk) and rewrite clock (rewrite clk) signals supplied by controller 11. The active list memory 2 is used to store a list of all active neurons during the initial and subsequent iterations, with the highest active list memory address being saved in an i limit register 6. The illustrated embodiment also includes two additional memories 3 and 4 for storing signals representative of respective variables ROW j SUM and COL m SUM obtained by accumulating successive outputs of a first signal transform circuit, for example a state function look-up table 10, which applies operator H(x i ) to current values of x i  indexed by row and column, in respective adders 8 and 9. In addition to supplying the clock signals noted above, controller 11 also supplies all other necessary read/write strobes, and controls for switches SW1-SW12, whose function will be evident from the description of the operation of the hardware below (those skilled in the art will appreciate, however, that switches SW1-SW12 could easily be eliminated and replaced by duplicate components and appropriate timing, if desired). 
     The operators kG(x i ) and F are preferably applied by respective second and third transform circuits, such as look-up tables 17 and 18, connected to appropriate xi outputs of the state memory 1, to outputs of subtractor circuits 13 and 14 which make up first and second signal combining circuits, and to row and column sum memories 3 and 4, as shown in FIG. 6. Additional signal processing functions, whose purpose will become more evident from the following description of function, include: (1) a fifth signal combining means in the form of an adder circuit 16 which combines a signal representative of the old neuron value with a signal representative of the change Δx i  in the old neuron value to obtain the new neuron value; (2) a third signal combining means in the form of a subtractor circuit 19 which supplies inputs to a fourth signal combining means in the form of a multiplier circuit 20 for generating the Δx i  signal; and (3) another subtractor circuit 21 which forms a sixth signal combining means for supplying an input to multiplier 20, to be explained below. The preferred apparatus also includes two temporary registers 12 and 15 for respectively storing addresses and x i  values during processing, and comparators 22 and 24 which respectively determine whether the Δx value, and the H or G values, are non-zero as described below (see also, observation 3, supra). 
     At the start of each iteration, switches SW1 and SW2 are set by controller 11 to their &#34;1&#34; position so that a data value of 0 is connected to the inputs of row sum memory 3 and column sum memory 4. Next, the index counter 5 starts at zero and increments to equal the contents of the i limit register 6. The output of index counter 5 serves as an address to the active list memory 2, which in turn provides the row and column coordinates of each active neuron to be computed during the iteration. The row and column coordinates form an address which is supplied to state memory 1 and which contains the current values x i  of the neuron at this row and column position in the matrix. The row portion of this address is used as the address for the row sum memory 3 and the column portion of the address is used as the address for column sum memory 4. At each count, a read write strobe issued by controller 11 loads a &#34;0&#34; into each location in the row sum memory 3 and column sum memory 4. This resets all of the respective ROW j SUM and all COL m SUM variables stored in respective memories 3 and 4 to 0. 
     Switches SW1 and SW2 are then changed by controller 11 to their &#34;2&#34; position so that data from adders 8 and 9 may be written back to the respective row and column sum memories 3 and 4, in order to obtain a cumulative signal representative of ΣH(x i ) which is stored in the respective memories as variables ROW j SUM and COL m SUM. The index counter 5 is reset back to zero and increments as it did at the start of the iteration, until the index count equals the contents of the i limit register 6. At each count, the contents of the row sum memory 3 and column sum memory 4 are loaded into adders 8 and 9, respectively. At the same time, the row and column addresses are used by state memory 1 to produce a current x i  or x m , which in turn is used as the argument for the output H(x i ) or H(x m ) of look-up table 10 and added to the contents of each of the sum memories using adders 8 and 9, as described above. After each add operation, the sum is written back to the respective row and column sum memories 3 and 4 by way of switches SW1 and SW2 which are in the ¢2&#34; position. When the index count reaches the value in the i limit register, and the final sums are written back to the sum memories, then each memory address contains the sum of H(x j )&#39;s or H(x m )&#39;s for the corresponding row or column. 
     Switches SW4, SW5, SW6; and SW7 are set to their &#34;1&#34; position after resetting the index counter 5 and the rewrite counter 7 back to zero. For each index count between zero and the i limit contained in i limit register 6, the active row and column are stored in a temporary register 12. Subtractors 13 and 14 (see FIG. 6) reduce the signals stored in memories 3 and 4 by, respectively, a constant signal c and a constant signal d. Switches SW4, SW5, SW6, and SW7 are then changed to their &#34;2&#34; position so that the current H(x i ) can be subtracted from the respective ROW j SUM and COL m SUM variables while again using subtractors 13 and 14. While this is happening, the current neuron value x i  is stored in temporary register 15 and then added to the constant &#34;a&#34; input through switch 12 by adder 16. At the same time kG(x i ) is retrieved from the kG(x i ) look-up table 17. 
     Next, with switches SW8 and SW9 set to position &#34;1&#34;, the F look-up table 18 operates on the output of subtractor 13 to obtain a signal representative of the function F(ROW j SUM-H(x i )-c), which is subtracted from a signal having the value &#34;b&#34; supplied by the &#34;1&#34; position of SW9, using subtractor 19. Then switches SW8 and SW9 are switched by controller 11 to the &#34;2&#34; position and look-up table 18 applies the operator F to the output of subtractor 14 to obtain a signal representative of F(COL m SUM-H(x i )-d). The F(COL m SUM-H(x i )-d) and F(ROW j SUM-H(x i )-c) are then subtracted, again using subtractor 19. With switch SW10 and SW11 in position 1, the contents of subtractor 19 (b-F(ROW j SUM-H(x) i  -c)-F(COL m SUM-H(x i )-d)) are combined with kG(x i ) using the multiplier 20. Finally, the contents of adder 16, a+x i , are subtracted from the product in the multiplier using subtractor 21, switches SW10, SW11 and SW12 are changed to position &#34;2&#34;, and the output of subtractor 21 is multiplied by Δt, again using multiplier 20. Δt can easily be predetermined based on the time it takes for the circuit to complete an iteration. The output of multiplier 20 is a signal corresponding to the difference Δx i  between the old and new neuron values for the current iteration. 
     In order to determine whether the neuron values are converging, Δx i  is tested to determine if it is less than zero using comparator 22. If any Δx i  is less than zero for a given iteration, the system has not yet converged and another iteration is required. Finally, the Δx i  signal is added to the &#34;old&#34; neuron value x i  (previously referred to as the current neuron value) using adder 16, and the resulting new neuron value x i  is input to state memory 1 for use in the next iteration. 
     During each iteration, H(x i ) and kG(x i ) are also tested by comparator 1 using respective positions &#34;1&#34; and &#34;2&#34; of switch SW3. If either H(x i ) or kG(x i ) is greater than zero, a STILL USEFUL signal is sent to the controller 11, after which the row and column for the corresponding neuron which was previously stored in temporary register 15 is rewritten to the active list memory using an address n provided by the rewrite counter 7. Address n will always be equal to or less than the current index i output by the index counter 5. After the last neuron is computed for each iteration, the maximum count n in the rewrite counter becomes the i limit and is stored in the i limit register 6. In this way, the active list continually grows shorter until convergence is detected, at which point, the active list contains only the associated rows and columns. The final answer can be found by reading the active list memory using the index counter from zero to the i limit. Each reading provides a row and its associated column. 
     Those skilled in the art will appreciate that the above-described digital circuit implementation of the invention can be varied according to the principles described above without departing from the scope and spirit of the invention. For example, while memories or signal storage devices are necessary, and some type of signal accumulating and combining components or processors are also required, much of the signal processing could be accomplished by using software to configure programmable components or processors, to retrieve values from, and store values in, the memories, and to combine them in a manner similar to the manner by which the circuit of the preferred embodiment accomplishes its functions. The &#34;signals&#34; processed could be either digital or analog, although the illustrated embodiment is a digital circuit. 
     Accordingly, having described a specific embodiment of the invention in sufficient detail to enable one skilled in the art to make and use the invention, it is to be understood that modifications and adaptations of the invention may be made without departing from the spirit or scope of the invention, and it is consequently intended that the invention not be limited by the above description, but rather that it be defined solely by the appended claims.