Abstract:
A 3D variable resistance memory device and a method of manufacturing the same are provided. A semiconductor substrate includes a peripheral area, having a top surface, wherein a peripheral circuit is formed in the peripheral area. The peripheral circuit includes a driving transistor formed on a surface of the semiconductor substrate, wherein the semiconductor substrate forms the channel of the driving transistor. The semiconductor substrate includes a cell area, having a top surface, wherein a height of the top surface of the cell area is lower than a height of the top surface of the peripheral area, thereby defining a trench in the cell area. A plurality of memory cells, each include a switching transistor formed on the semiconductor substrate in the cell area, a channel extending in a direction substantially perpendicular to a surface of the semiconductor substrate, and a variable resistance layer that selectively stores data in response to the switching transistor.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. 19(a) to Korean application number 10-2013-0038586, filed on Apr. 9,2013, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The inventive concept relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a three-dimensional (3D) variable resistance memory device and a method of manufacturing the same. 
         [0004]    2. Related Art 
         [0005]    Memory devices are generally provided as internal semiconductor integrated circuits of computers or other electronic apparatuses. The memory devices are divided into volatile memory devices and nonvolatile memory devices. In recent years, variable resistance memory devices have been more closely studied. 
         [0006]    Examples of variable resistance memory devices include phase-change random access memory devices (PCRAMs), resistive RAMS (ReRAMs), and magnetic RAMS (MRAMs). Among the variable resistance memory devices, the PCRAMs have characteristics such as high memory density like dynamic random access memories (DRA high reliability, and low power consumption. 
         [0007]    The nonvolatile memory devices, including the variable resistance memory devices, may be used in portable music players such as MP3 players, movie players, or other electronic apparatuses, portable phones, digital cameras, solid states drives (SSDs), portable memory sticks, or personal computers. 
         [0008]    The variable resistance memory devices may include a plurality of memory cells arranged in a matrix form. Each of the plurality of memory cells may include a switching device connected to a word line and a resistance device connected to a bit line. 
         [0009]    The switching device may be accessed by activating a corresponding word line. The selected memory cell may programmed by a current transferred to the resistance device. 
         [0010]    To achieve a high integration density and multi-level cell, the switching device of the variable resistance memory device may have a 3D structure and the resistance device is stacked on the switching device. [Unclear.] 
         [0011]    As is generally known, a channel of the 3D switching device is generally extends perpendicular to a surface of a semiconductor substrate. Therefore, the 3D switching device has a narrower width and a relatively higher height than a 2D switching device. 
         [0012]    However, in the 3D variable resistance memory devices, since a lower electrode is additionally formed on the 3D switching device having the increased height, there is difficulty in forming the lower electrode. Furthermore, a step between a cell area and a peripheral area is increased, 
       SUMMARY 
       [0013]    An exemplary variable resistance memory device may include A variable resistance memory device, comprising a semiconductor substrate including a peripheral area, having a top surface, wherein a peripheral circuit is formed in the peripheral area, the peripheral circuit including a driving transistor formed on a surface of the semiconductor substrate, wherein the semiconductor substrate forms the channel of the driving transistor, and a cell area, having a top surface, wherein a height of the top surface of the cell area is lower than a height of the top surface of the peripheral area, thereby defining a trench in the cell area; and a plurality of memory cells, each of the plurality of memory cells including a switching transistor formed on the semiconductor substrate in the cell area, a channel extending in a direction substantially perpendicular to a surface of the semiconductor substrate, and a variable resistance layer that selectively stores data in response to the switching transistor. 
         [0014]    A method of manufacturing an exemplary variable resistance memory device may include providing a semiconductor substrate in which a cell area and a peripheral area are defined; forming a first trench in the semiconductor substrate in the cell area and a second trench in the semiconductor substrate in a device isolation region of the peripheral area; forming a device isolation layer in the second trench; forming a switching transistor in the first trench; forming a lower electrode on the switching transistor; forming a driving transistor in the peripheral area; and forming a variable resistance layer on the lower electrode. 
         [0015]    A method of manufacturing an exemplary variable resistance memory device may include forming a trench in a cell area of a substrate; forming a vertical channel transistor in the trench; forming a lower electrode and a hard mask layer on the vertical channel transistor; forming a first insulating layer at sides of the vertical channel transistor; forming a second insulating layer at sides of the lower electrode and the hard mask layer; defining, by selectively removing the hard mask layer, a space in the second insulating layer to contain a variable resistance layer; and forming a variable resistance layer in the space to contain a variable resistance layer. 
         [0016]    These and other features, aspects, and implementations are described below in the section entitled “DETAILED DESCRIPTION”. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    The above and other aspects, features and other advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0018]      FIGS. 1 to 9  are cross-sectional views illustrating a method of manufacturing an exemplary variable resistance memory device. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    Hereinafter, an exemplary implementation will be described in greater detail with reference to the accompanying drawings. 
         [0020]    An exemplary implementation is described herein with reference to cross-sectional illustrations that are schematic illustrations of the exemplary implementation (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary implementation should not be construed as limited to the particular shapes of regions illustrated herein but may be to include deviations in shapes that result, for example, from manufacturing. In the drawings, lengths and sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements. It is also understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other or substrate, or intervening layers may also be present. 
         [0021]    Referring to  FIG. 1 , a semiconductor substrate  100 , in which a cell area A and a peripheral area B are defined, is prepared. For example, the semiconductor substrate  100  may be a silicon substrate, but the semiconductor substrate  100  is not limited thereto. The semiconductor substrate  100  may include a wafer formed of any semiconductor material, such as a silicon-on-insulator (SOT) or a gallium arsenide (GaAS). 
         [0022]    A first trench T 1  is formed in the cell area A, and a second trench T 2  is formed in the peripheral area B. The first trench T 1  may be entirely formed in the cell area A, and the second trench T 2  may be formed in a device isolation formation region of the peripheral area B. The first trench T 1  and the second trench T 2  may have different widths, but may have the same depth. 
         [0023]    Referring to  FIG. 2 , a pillar  110  is formed in a predetermined region of the cell area A. The pillar  110  may be formed by depositing a semiconductor layer on the cell area A and patterning the semiconductor layer. For example, the pillar  110  may include a polysilicon layer and have substantially the same height as a depth of the trench T 1 . Before the formation of the pillar  110 , an impurity ion implantation process is performed on a bottom of the first trench T 1  so that the bottom of the first trench T 1  (i.e. the semiconductor substrate  100  of the cell area A) may be used as a common source of a switching transistor to be formed later. A gate insulating layer  115  may be formed on a surface of the semiconductor substrate  100 , expect for a portion of the surface of the semiconductor substrate  100  where the pillar  110  is formed, and a side of the pillar  110 . For example, the gate insulating layer  115  may be formed by performing an oxidation on the semiconductor substrate  100  and the pillar  110 . A gate  120  may be formed on the gate insulating layer  115  to surround the pillar  100 . Hereinafter, the gate  120  will be referred to as a surround gate. For example, the surround gate  120  may include a doped polysilicon layer or a metal layer. The surround gate  120  may be formed to a height lower than that of the pillar  110  to overlap a region of the pillar  100  which is to be used as a channel. A protection layer  125 , which serves as an etch stopper, may be formed on the gate insulating layer  115  and on the surround gate  120 . The protection layer  125  may have a uniform thickness. An insulating layer  130  may be formed over the semiconductor substrate  100  and in the first trench T 1  and the second trench T 2 . The semiconductor substrate  100  is then planarized to expose the semiconductor substrate  100 . Therefore, the surround gate  120 , formed in the cell area A, may be insulated by the insulating layer  130 , and a device isolation layer  130   a  may be formed in the peripheral area B. A sacrificial layer  132  may be formed on the semiconductor substrate  100 , in which the device isolation layer  130   a  may be formed. For example, the sacrificial layer  132  may include an insulating layer. The sacrificial layer  132  may be selectively removed in the cell area A, but may remain on the peripheral area B. A switching transistor CTR may be formed in the cell area A by ion-implanting an impurity to form a drain junction region into a portion of the pillar  110  exposed by the sacrificial layer  132 . A drain junction region D of the switching transistor CTR is formed in an upper portion of the pillar  110 . 
         [0024]    Referring to  FIG. 3 , a lower electrode layer  135  and a hard mask layer  140  may be sequentially formed on the semiconductor substrate  100  and the sacrificial layer  132 . The lower electrode layer  135  may include, for example, an impurity-doped polysilicon layer or a metal layer. The hard mask layer  140  may include, for example, a silicon nitride layer. If the lower electrode layer  135  includes a metal layer, then a metal silicide layer (not shown) may be selectively formed between the pillar  110  and the lower electrode layer  135 . The sacrificial layer  132  may function to protect the semiconductor substrate  100  corresponding to the peripheral area B from the lower electrode layer  135 . 
         [0025]    Referring to  FIG. 4 , a lower electrode  135   a  and a hard mask  140   a  may be formed by patterning the lower electrode layer  135  and the hard mask layer  140 . 
         [0026]    Referring to  FIG. 5 , a first interlayer insulating layer  145  may be formed on the semiconductor substrate  100 , over which the lower electrode  135   a  and the hard mask  140   a  are formed. The first interlayer insulating layer  145  may be formed in a space between adjacent pairs of lower electrodes  135   a  and hard masks  140   a.  The first interlayer insulating layer  145  may have a thickness substantially equal to a combined thickness of the lower electrode  135   a  and the hard mask  140   a.  The first interlayer insulating layer  145  may and then planarized to expose a surface of the hard masks  140   a.    
         [0027]    An etch stopper layer  150  is formed on the planarized first interlayer insulating layer  145 . The etch stopper layer  150  may include, for example, a silicon nitride layer. 
         [0028]    Referring to  FIG. 6 , the etch stopper layer  150 , the first interlayer insulating layer  145 , and the sacrificial layer  132  are etched to expose a surface of the semiconductor substrate  100  in the peripheral area B. A gate insulating layer [Not shown in  FIG. 6 ], a polysilicon layer  160 , a metal layer  162 , and a hard mask layer  164  are sequentially stacked on an exposed active region of the peripheral area B (i.e., a region between the device isolation layers  130   a ). Predetermined portions of the polysilicon layer  160 , the metal layer  162 , and the hard mask layer  164  may be patterned to form a gate structure  165 . Alternatively, the gate structure  165  may be formed of a single polysilicon layer or a single metal layer. A source  167   a  and a drain  167   b  may be formed in the active region of the peripheral area B at sides of the gate structure  165 . Therefore, a driving transistor PTR may be formed in the peripheral area B. The driving transistor PTR may read and Trite data from and to memory cells formed in the cell area A. 
         [0029]    Referring to  FIG. 7 , a second interlayer insulating layer  170  may be formed over the semiconductor substrate  100 , that is, on the entire cell area A and the entire peripheral area B. That is, the second interlayer insulating layer  170  may cover the peripheral area B and, in the cell area A, the second interlayer insulating layer  170  may cover the first interlayer insulating layer  145  and the etch stopper layer  150 . The second interlayer insulating layer  170  may be planarized, Next, a conductive plug  175  may be electrically connected to a conductive region of the peripheral area B, for example, the metal layer  162 , the source  167   a  and the drain  167   b  is formed in the second interlayer insulating layer  170  through a general method. For example, the conductive plug  175  may include a metal layer having a gap fill characteristic such as tungsten. However, the conductive plug  175  is not limited thereto, and various conductive materials may be used as the conductive plug. A capping layer  180  may be formed on the planarized second interlayer insulating layer  170 , In the exemplary implementation, the capping layer  180  may protect device structures formed on the peripheral area B and selectively expose the etch stopper layer  150  of the cell area A (as will be described later). 
         [0030]    Referring to  FIG. 8 , the capping layer  180  on the cell area A is selectively removed and remains on the peripheral area B as capping layer  180 . The second interlayer insulating layer  170  on the cell area A is etched using the remaining capping layer  180  as a mask to expose the etch stopper layer  150  formed on the cell area A. Next, the exposed etch stopper layer  150  is selectively removed. Since the etch stopper layer  150  is formed of a silicon nitride layer, as described above, the etch stopper layer  150  may be selectively removed through a wet etch process. At this time, the hard mask layer  140   a,  which is disposed below the etch stopper layer  150  and formed of the same material as the etch stopper layer  150 , may be also removed. A space H is formed by the removal of the hard mask layer  140   a.  A variable resistance material will be formed in the space H in a subsequent process. 
         [0031]    Referring to  FIG. 9 , a heat-resistant spacer  185  may be formed on a sidewall of the space H. The heat-resistant spacer  185  may include, for example, a silicon nitride layer. A variable resistance layer  190  may be formed in the space H and surrounded by the heat-resistant spacer  185 . Characteristics of the device may be changed based on a type of material used as the variable resistance layer  190 . Various materials may be used for the variable resistance layer  190 . For example, a PCMO (Pr 1-x Ca x MnO 3 ) layer may be used for a ReRAM, a chalcogenide layer may be used for a PCRAM, a magnetic layer may be used for a MRAM, a magnetization reversal device layer may be used for a spin-transfer torque magnetoresistive RAM (STTMRAM), or a polymer layer may be used a polymer RAM (PoRAM). An upper electrode  195  may be formed on the variable resistance layer  190  by a known method. 
         [0032]    As described above, the switching transistor formed in the cell area may be formed in the trench region to reduce a step between the cell area and the peripheral area. 
         [0033]    Further, the lower electrode may be formed before the driving transistor of the peripheral area is formed, and the space H may be formed in a self-aligning manner by removing the hard mask layer after the driving transistor is formed. Therefore, the variable resistance layer may be formed without the effect of increasing of an aspect ratio. 
         [0034]    As described above, the spare H may be defined at the same time as the removal of the etch stopper layer formed in the cell area. Therefore a separate etching process for defining the space H is not necessary. 
         [0035]    The above exemplary implementation is illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the exemplary implementation described herein. Nor is the invention limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.