Abstract:
An improved output circuit for an operational amplifier which is controlled to operate in one of two modes. In the first mode, the output of the operational amplifier tracks a reference signal or ground. In the second mode, the output of the operational amplifier tracks the level of a time varying second voltage signal. The improvement consists of replacing the stabilization capacitor of prior art output circuits with a pair of stabilization capacitors connected in parallel. Each of the pair of capacitors has an associated series connected switch for switching the capacitor into and out of the circuit. The switches are operated by a respective one of a pair of external non-overlapping clock pulse trains so as to not be closed simultaneously. The effect of this improved output circuit is to allow the output voltage of the operational amplifier to slew rapidly (or snap) up to the last previous level of a sampled input voltage (or a predetermined second reference voltage) thereby minimizing the effects imposed by the limiting of the first stage slew rate. Thus, slewing begins at a higher rate, governed primarily by the higher slew rate capability of the output stage, and consumes less time. In addition, the output voltage will snap directly from the level of the sampled time varying second voltage to the reference voltage level at the same high slew rate of the output stage. Because the voltage difference through which the stabilization capacitor must charge is greatly reduced, the output is able to reach and track the time varying voltage more rapidly than can prior art devices. The output of the operational amplifier thus shows greater correlation with the level of the second or time varying signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to the design of operational amplifiers and, in particular, to the design of the output stage of operational amplifiers intended to provide an output voltage which switches (or alternates) between a first output reference voltage and a second output signal voltage level. The signal voltage may be time varying. 
     2. Description of the Prior Art 
     The use of operational amplifiers to switch between output voltage levels is known. Such operational amplifiers require a specific amount of time to make the transition from one output voltage level to another output voltage level. The required time interval is commonly divided into two sub-intervals, the slewing time interval and the settling time interval. 
     The rate at which the output voltage of an operational amplifier changes from a first level to a second level during the slewing time interval is called the slew rate dV/dt. The slew rate is limited to a maximum value determined by the input stage bias current I 1  and the size of the internal stabilization capacitor (Cs). The maximum value of the slew rate is known as the first-stage slew rate limit and may be expressed as dV/dt=I 1  /Cs. In presently known operational amplifiers which are required to switch from a first voltage level to a second voltage level, the first voltage level may be a reference level such as ground or the offset voltage of the differential input stage of the operational amplifier. The second voltage level may be a specific time varying voltage level which the operational amplifier is required to provide at its output. Thus, as the value of the time varying voltage increases, it takes the operational amplifier longer to slew from the ground or reference voltage level to the level of the second or time varying voltage. The longer the time required to slew to the desired voltage level, the less time is available (during a given clock period) for the settling time interval, during which the amplifier output voltage may settle to a value approaching that of the desired output voltage. 
     SUMMARY OF THE INVENTION 
     The invention is an improved output circuit for an operational amplifier which is controlled to operate alternately in each of two modes. In the first mode, the output of the operational amplifier is reset to a reference signal or ground. In the second mode, the output of the operational amplifier samples the level of a time varying second voltage signal. The improvement consists of replacing the stabilization capacitor of prior art output circuits with a pair of stabilization capacitors connected in parallel. A series connected switch is associated with each capacitor for switching the associated capacitor into and out of the circuit. The switches are operated by a respective one of a pair of external non-overlapping clock pulse trains so as to not be closed simultaneously. The effect of this improved output circuit is to allow the output voltage of the operational amplifier to snap up to the last previous level of a sampled input voltage at a rate which is not restricted by the first stage slew rate limit. Thus, slewing begins at a higher rate, limited only by the output stage slew rate capability. The slew interval will therefore consume less time. Because the time interval during which the output slews is greatly reduced, the output has more time to settle and track the time varying voltage than in prior art devices. The output of the operational amplifier thus shows greater correlation with the level of the second or time varying signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates the typical circuit environment in which the present invention is intended to operate. 
     FIG. 2 is a schematic diagram of prior art circuitry used within the operational amplifier contained in FIG. 1. 
     FIG. 3 is a diagram of the output waveform resulting from use of the circuit of FIG. 2. 
     FIG. 4 is a schematic diagram of the circuit of the present invention. 
     FIG. 5 is a representation of the non-overlapping external clock signals used in the circuit of FIG. 4. 
     FIG. 6 is a diagram of the output waveform resulting from use of the circuit of FIG. 4. 
     FIG. 7 is a schematic diagram of an alternate embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The environment in which the circuit of the present invention is intended to operated is typified by the circuit shown in FIG. 1. That circuit is a simplified circuit diagram of an insulated gate field effect transistor (IGFET) circuit formed on a semiconductive substrate for performing a sample and reset function. This circuit is the subject of a copending patent application of Lucas et al, Ser. No. 316,453, filed Oct. 30, 1981, titled &#34;Sample and Hold Circuit with Improved Offset Compensation&#34;. That application is assigned to the same assignee as is the present application. A detailed explanation of the circuit of FIG. 1 may be found in the referenced copending application. Only an abbreviated explanation will be given herein. 
     The switch 50 permits alternate connection of the input capacitor 40 to the input voltage source 18 and ground. The switch 52 permits the alternate connection of the amplifier output 10c to the amplifier inverting input 10b and to plate 42b of the feedback capacitor 42. The switch 54 permits connection of the feedback capacitor plate 42b to ground. When the circuit is operating in the &#34;reset&#34; mode, the switch 50 is connected between ground and the input capacitor 40, and the switch 52 is connected between the output 10c and the inverting input 10b while the switch 54 is closed to connect the feedback capacitor plate 42b to ground. When the circuit is in the &#34;sample&#34; mode, the position of all of the switches 50, 52, 54 is reversed so that the switch 50 connects the input voltage source 18 to capacitor 40, the switch 52 connects the amplifier output 10c to the feedback capacitor plate 42b, while the switch 54 disconnects the feedback capacitor plate 42b from ground. 
     The switch 56 is operated during the &#34;sample&#34;  mode to disconnect the positive amplifier input 10a from ground leaving the positive amplifier input connected to the capacitors 60 and 62. The value of capacitors 60 and 62 are selected to be proportional to the value of capacitors 40 and 42, respectively. The purpose of the capacitors 60, 62 is to provide compensation for the leakage currents I in-  and I in+  which leak through the switches 56 and 52, respectively, during the &#34;sample&#34; mode. Typically, each of the switches 52, 56 is formed as a metal oxide semiconductor field effect transistor (MOSFET). Such a switch typically has junction leakage which is a well-known problem in the art and causes the leakage currents I in-  and I in+ . 
     By omitting switch 54 and operating switches 50, 52 as described above, but in synchronism with a clock signal Φ of frequency f c  derived from a clock signal generator 80, the circuit of FIG. 1 becomes a switched capacitor integrator. By reversing the phase of the clock signal controlling switch 50, the circuit of FIG. 1 becomes a sample and hold circuit. 
     Internal to the operational amplifier 10 is circuitry typified by that shown in FIG. 2. That circuit comprises a first current source 100, a pair of P-type FETs 102, 104 forming the differential input, a pair of N-type FETs 106, 108 forming a current mirror, and an output stage 109 comprising a second current source 110, an N-type FET 112 and a stabilization capacitor 113. The inverting input terminal 114 and the positive input terminal 116 correspond respectively to the input terminals 10b and 10a of op amp 10 of FIG. 1. Output terminal 118 provides the output signal and corresponds to terminal 10c of FIG. 1. 
     If the internal circuitry of the op amp 10 is as shown in FIG. 2, then the circuit of FIG. 1 may be operated in a sample and reset mode to give the output waveform V out  as shown in FIG. 3 when the input waveform is sinusoidal such as V in . When the circuit is not in the sample mode, the output voltage returns to the reset level of V ref  which is typically the offset voltage of the op amp. As shown in FIG. 3, V out  is at V ref  for the time interval t 1  to t 2 . During the sample time interval t 2  to t 3 , the output V out  ideally should track V in . However, V out  can rise only at the maximum slew rate dV/dt set by the input stage bias current I 1  from source 100 and the size of the stabilization capacitor 113 (Cs). The maximum rate dV/dt max is expressed as I 1  /Cs and is commonly referred to as the input stage slew rate limit. V out  will rise at this maximum slew rate until it nears V in  as indicated at A in FIG. 3. Thereafter, V out  will settle toward V in  until the time t 3 . At time t 3 , V out  would ideally switch to V ref  and remain there until t 4 . However, V out  can only slew toward V ref  at a rate of -dV/dt max . V out  thus begins to slew downward toward V ref  and continues to slew at the maximum rate until it reaches point B where it begins to settle into the level V ref . The time period between B and C is referred to as the settling time of the waveform V out . From point C to time t 4 , the output V out  tracks V ref . At time t 4 , the switching circuitry again places the circuit of FIG. 1 in the sample mode. V out  thus begins to rise at the rate dV/dt max. Since V in  has now reached a higher level, V out  must slew for a longer time period, i.e., slews from t 4  to point D. This time span is significantly longer than the time span t 2  to point A. Because it takes so long to approach the level of V in , V out  cannot reach V in  during the period D to E. Similarly, for the sample period t 6  to t 7 , V out  actually tracks V in  only for the time span from point H to point I. For the sample time t 8  to t 9 , the lower level of V in  permits V out  to track for a relatively long period of time between point L and t 9 . In general, the higher the voltage level of V in , the longer is the slew time, and the less time there is available to actually settle to and track the desired voltage V in   or V ref . 
     The present invention is a switching circuit, intended to modify the output stage 109 of the circuit of FIG. 2. On the average, the invention reduces the time required to slew to the level of V in , thereby leaving a greater portion of the sample or reset periods available for actually tracking either the input voltage V in , or the reference voltage V ref , as appropriate. The modification to the circuit is illustrated by the output stage 109&#39; of FIG. 4. 
     The disadvantages of the circuit of FIG. 2 stem from the fact that a single capacitor is required to switch between both the reference level V ref  and the input signal V in . Before the single capacitor 113 can track one signal, it must charge or discharge from the voltage retained when tracking the other signal. In the improved circuit of FIG. 4, one capacitor, e.g., 123, is dedicated to tracking V in  and another capacitor, e.g., 125, is dedicated to tracking the other voltage level V ref . Thus, neither capacitor is required to track both V out  and V ref , each is free to retain the last achieved voltage level of the signal which it tracks. 
     As shown in FIG. 4, the improvement of the invention comprises replacing capacitor 113 of FIG. 2 by a pair of capacitors 123 and 125, each of which may be selectively switched in or out of the tracking mode by a respective switch means such as switches 127 and 129 which may comprise a pair of FET switches. The switches 127 and 129 are operated such that they are never both closed at the same time. This is accomplished by the pair of nonoverlapping clock signals Φ 1  and Φ 2  shown in FIG. 5. As an example, Φ 1  could be used to control switch 127. When Φ 1  is high, switch 127 would be closed thereby placing capacitor 123 in the circuit to track the input signal. When Φ 1  is high, Φ 2  is low and switch 129 is open. Thus capacitor 125 would be out of the circuit and would retain or &#34;hold&#34; the voltage level that it had reached during the last time it was in the circuit (i.e, when switch 129 was closed). Of course, for proper operation, Φ 1  and Φ 2  must be operated in synchronism with the signal Φ of the circuit of FIG. 1. 
     An example may serve to better illustrate the operation of the circuit of FIG. 4. Assume that the signal Φ is in its low state as during the period t 1  to t 2  of FIG. 5, this would connect capacitor 40 of FIG. 1 to ground and connect terminal 10c to the inverting input terminal 10b. Switches 54 and 56 are closed. This is the &#34;reset&#34; mode of the circuit of FIG. 1. During this same time period Φ 1  is low, causing switch 127 to be open, thus removing capacitor 123 from the circuit. However, Φ 2  is high causing switch 129 to be closed, thus putting capacitor 125 into the circuit to &#34;track&#34; the reference voltage. With capacitor 40 switched to ground, the only output voltage will be the offset voltage, i.e., V ref . Therefore, the output voltage V out  shown in FIG. 6 will be held to V ref  and stored on capacitor 125. 
     At time t 2 , Φ goes to its high state for the period t 2  to t 3  of FIG. 5. This connects capacitor 40 to the input voltage V in  and connects output terminal 10c to plate 42b of capacitor 42. Switches 54 and 56 are opened. This is the &#34;sample&#34; mode of the circuit of FIG. 1. During this same time period Φ 1  is high, causing switch 127 to be closed, thus switching capacitor 123 into the circuit, Φ 2  is low causing switch 129 to be open, thus switching capacitor 125 out of the circuit where it will retain the voltage level V ref . When capacitor 123 is switched into the circuit, the voltage stored across it will be nearly the same as reached during the previous sample period which ended at t 1 . Since the input voltage at t 1  was nearly the same as V ref , the voltage stored across capacitor 123 will be nearly the same as the voltage stored across capacitor 125. Consequently, the output voltage will not be driven to a substantially different value as a result of the voltage stored across capacitor 123. Capacitor 123 then begins to charge or discharge toward the current value of V in . However, the capacitor 123 can change voltage only at a maximum rate dV/dt equal to the slew rate I 1  /Cs1 where Cs1 is the value of capacitor 123. Thus the output voltage begins to rise at the input stage limited slew rate and at point A of FIG. 6 nears V in  and thereafter settles into and tracks V in . 
     At time t 3  of FIG. 5, Φ changes to its low state for the time period t 3  to t 4 . This connects capacitor 40 of FIG. 1 to ground and connects the output terminal 10c to the inverting input terminal 10b. Switches 54 and 56 are closed. During this same time period t 3  to t 4 , Φ 1  is low causing switch 127 to be open, thus removing capacitor 123 from the circuit. Capacitor 123, while removed during this period t 3  to t 4 , will retain the last voltage level which it had reached, i.e., the voltage at just prior to time t 3 . When Φ 1  is low, Φ 2  is high, causing switch 129 to close and switch capacitor 125 into the circuit. When capacitor 125 is switched into the circuit, the output voltage V out  slews at a high rate, limited only by the output stage slew rate, not the input stage slew rate. It then settles to the value of the voltage previously stored in capacitor 125, which is V ref . Thus, V out  is not required to slew back to V ref  at a rate determined by the input stage slew rate limit as was the case in FIG. 3 for the time period t 3  to point B. V out  will thus accurately track V ref  for most of the period t 3  to t 4 . 
     At time t 4  in FIG. 5, Φ changes from low to its high state and stays in its high state for the period t 4  to t 5 . This again connects capacitor 40 to the input voltage V in  and connects output terminal 10c to plate 42b of capacitor 42. Switches 54 and 56 are closed. Φ 1  goes to high closing switch 127 and switching capacitor 123 into the circuit. Φ 2  is now low, switching capacitor 125 out of the circuit, where it retains its level V ref . As capacitor 123 is switched into the circuit, it still has stored on it the last voltage level reached during the previous sample period, t 2  to t 3 . As soon as capacitor 123 is switched into the circuit, V out  slews at a high rate, limited only by the output stage slew rate, not the input stage slew rate, from V ref  to the value previously stored on capacitor 123, i.e., the high voltage level shown in FIG. 6 at time t 3 . V out  thus begins to rise at the output stage slew rate limit until at point D it nears the level of, and begins to settle toward, V in . The time duration required to slew to near the level of V in , i.e., the time t 4  to point D, is significantly less than the corresponding slew time required by the circuit of FIG. 2, which time is shown as the period t 4  to D in FIG. 3. Correspondingly, the time that V out  settles to and tracks V in  is much greater in FIG. 6 (i.e., point D to E) than in FIG. 3 (point D to E). Note that in FIG. 3, because of the slew rate limitation, V out  never reaches V in  during the t 4  to t 5  interval. 
     At time t 5 , Φ drops to its low state, Φ 2  goes high, and Φ 1  goes low. V out  thus slews at a high rate from its value at point E to V ref , as explained for time t 3  above. 
     At times t 6  and t 8  as shown in FIG. 5, Φ goes high and Φ 1  goes high switching capacitor 123 into the circuit. In each case, the voltage stored in capacitor 123 is higher than the current level of V in . Thus, V out  begins at V ref  and slews at a rapid rate toward the previously stored value of V in . It may go above the value of V in  and slews back down toward V in  at the rate of -Is1/Cs1 until it gets relatively close to V in  and then gradually settles into and tracks V in  as at points H and L. The output waveform shown in FIG. 6 can readily be compared to the output waveform of FIG. 3. It is apparent that V out  of FIG. 6 tracks the desired voltage levels V ref  and V in  for a greater percentage of the time period t 1  to t 9  than does V out  of FIG. 3. V out  of FIG. 6 is required to slew from one voltage level to another for much less time than required in FIG. 3. Although the input slew rate limit dV/dt is the same for the circuits of FIG. 2 and FIG. 4, the output V out  of FIG. 6 requires less time for slewing. 
     Since the voltage level stored on capacitor 123 is generally going to be closer to the next sampled value of V in  than is the reference voltage V ref , the slewing time of the circuit of FIG. 4 will generally be less than the slewing time of the circuit of FIG. 2. The output V out  will thus show greater correlation with V in  for the circuit of FIG. 4 than was achieved by the circuit of FIG. 2. 
     The improvement in slewing time may be computed as follows: 
     Let the slewing time of the prior art circuit of FIG. 2 be designated Tso. Let Vd equal the voltage difference between the reference voltage level V ref  and the voltage level of the desired output voltage waveform V in . Then: 
     
         Tso=Vd/(dV/dt.sub.max)                                     (1) 
    
     where dV/dt max  has been previously defined as the maximum slewing rate sized by I 1  /Cs. 
     Let the input stage limited slewing time of the new and improved circuit be designated Tsn. Let ΔV out  be the maximum voltage through which the new circuit must slew at the input stage limited slew rate dV/dt max . Assume (see FIG. 6) that the time required to slew, at the output stage limited slew rate, to the previously stored voltage is small in comparison to Tsn. Then: 
     
         Tsn=ΔV.sub.out /(dV/dt.sub.max)                      (2) 
    
     Note that ΔV out  represents the difference between signal output voltage levels occurring over the time interval in which the reference voltage is present at the amplifier output. This time interval is usually T clk  /2 where T clk  is the clock period (i.e., the period of the externally supplied clock pulse train). Where V out  is a sine wave (with frequency ω s  =2πf s ) described by: 
     
         V.sub.out =V.sub.d sin ω.sub.s t, 
    
     it can be shown that ΔV out  has a maximum value given by: 
     
         ΔV.sub.out.sbsb.max =(T.sub.clk /2)·ω.sub.s Vd (3) 
    
     where ω s  Vd is equal to the maximum slope of the output sine wave. 
     In typical switched capacitor filter applications, and in the switched capacitor application of the invention, the clock frequency f c  is usually several times (e.g., usually 10 times) the mid band frequency f s . Thus, if 
     
         f.sub.c /f.sub.s =n                                        (4) 
    
     then n is much greater than 1. (n&gt;&gt;1). 
     Using the above equations, the improvement in slewing time can be written as the old slew time divided by the new slew time, or from (1) and (2) 
     
         (Tso/Tsn)=(Vd/ΔV.sub.out)                            (5) 
    
     But from (3), 
     
         Tso/Tsn=(2/T.sub.clk)(Vd/ω.sub.s Vd)                 (6) 
    
     Substituting 2πf s  for ω s  and  1  /f c  for T clk  yields 
     
         (Tso/Tsn)=(f.sub.c /πf.sub.s)                           (7) 
    
     Substituting (4) into (7) gives the final result 
     
         (Tso/Tsn)=(n/π)                                         (8) 
    
     In the typical case where n is 10, the improvement factor is 10/π or about a factor of 3 reduction in slewing time. This reduction in slewing time can be used to great advantage. For example, the reduced slewing time typically permits the same amplifier to be used at more than double the clock rate. That is, a circuit using the present invention can utilize values for n which are twice that of the old circuit and thereby significantly reduce distortion produced by sampling as in switched capacitor filter circuit applications. Similarly, equivalent results can be obtained by the new circuit even if the current limited slew rate, and therefore the power supplied to the operational amplifier, is reduced by about 50%. Thus, by using the design of the present invention, great flexibility is achieved. The three factors, tracking capability, clock rate and power consumption can be balanced against one another and traded off to achieve the most desired output waveform characteristics. 
     It should be noted that if the external feedback network around the operational amplifier, as shown in FIG. 1 is switched from one configuration to another, an optimum value for capacitors 123 and 125 can be chosen for each configuration of the feedback network. 
     An alternate embodiment of the invention is shown in FIG. 7. The alternate embodiment is a more versatile version of the circuit of FIG. 4. The increased versatility is achieved by adding switching devices such as switches 137 and 139 on the other side of the respective capacitors 123 and 125. This permits complete isolation of capacitors 123 and 125 from the remainder of the circuit. By further adding switch devices 130 and 132 and properly biasing FET 134, capacitor 123 may be precharged to a selected voltage level while capacitor 125 is switched into the circuit. Similarly, by adding switch devices 136 and 138 and properly biasing FET 140, capacitor 125 may be precharged to a selected voltage level while capacitor 123 is switched into the circuit. The added switches 137, 132 and 130, and the biasing FET 134 may be referred to generally as a precharging means for capacitor 123. By precharging the capacitors 123 and 125, the output voltage V out  may be caused to return to any desired voltage level whenever the non-overlapping clock signals change state. Thus, V out  can be caused to slew rapidly toward a reference level other than the last stored value of V ref  (shown in FIG. 6) during the &#34;reset&#34; period such as t 3  to t 4 , and V out  may also be caused to slew rapidly to any predetermined level, independent of the last sampled value of V out , as was the case at times t 4  to t 5  when the sample period begins. The above described operation may be readily understood by noting that when Φ 1  is high and Φ 2  is low, capacitor 123 is switched into the circuit and capacitor 125 is switched out of the circuit and into the precharge configuration. Capacitor 125 precharges through switches 136 and 138 to ground (or another predetermined reference). Conversely, when Φ 1  is low and Φ 2  is high, capacitor 123 is switched out of the circuit and into the precharge mode while capacitor 125 is switched into the circuit. 
     The circuit of FIG. 7 can easily be operated to perform identically to the circuit of FIG. 4. This is accomplished by not applying any clock signal Φ 1  or Φ 2  to switches 130, 132, 136, 138, which thus remain open, and driving switches 137 and 139 with a voltage which will keep the switches constantly closed. The configuration of the circuit of FIG. 7 then becomes electrically equivalent to the circuit of FIG. 4. 
     There has thus been described an improved circuit for the output stage of an operational amplifier intended for use in a sample and reset circuit. The improved circuitry greatly improves the apparent slew rate of the operational amplifier. In an alternate embodiment, additional provision is made to allow precharging the capacitor voltages such that the output voltage V out  can be caused to return to a desired voltage level each time the circuit changes from one state (&#34;sample&#34; or &#34;reset&#34;) to the other. 
     While the invention and an alternate embodiment have been described with particular reference to FIGS. 4 through 7, the figures are for purposes of illustration only and should not be interpreted in a limiting sense. Various modifications to the invention could be made by one skilled in the art without departing from the scope of the invention as defined by the appended claims. For example, the phasing of switch 50 in FIG. 1 could be reversed to obtain a sample and hold circuit. The non-overlapping clock pulse trains could also be a single clock pulse train, the high level of which would serve to close those switches driven by Φ 1  and open those switches driven by Φ 2 . This could be accomplished by appropriate selection of FETs as either P-type or N-type as required. In such a case, the signal Φ used to select the operating mode of the circuit of FIG. 1 could be used to serve the function of the non-overlapping pulse trains Φ 1  and Φ 2 .