Abstract:
The disclosure describes an exemplary method of measuring gate capacitance to determine electrical thickness of a gate dielectric located in a gate structure of a metal oxide semiconductor field effect transistor (MOSFET). This method can include connecting a meter to an integrated circuit gate structure and an active region located proximate the integrated circuit gate structure, applying forward body bias to the transistor to reduce the electrical field of the transistor at a gate inversion measuring point; and measuring capacitance from the meter while the transistor receives the forward body bias.

Description:
FIELD OF THE INVENTION 
     The present specification relates generally to integrated circuits and methods of fabricating integrated circuits. More specifically, the present specification relates to a method of measuring gate capacitance in an integrated circuit to determine the electrical thickness of metal oxide semiconductor (MOS) gate dielectrics. 
     BACKGROUND OF THE INVENTION 
     Integrated circuits (ICs) include a multiple of transistors formed on a semiconductor substrate. Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally built on the top surface of a bulk substrate. The substrate is built to form impurity diffusion layers (i.e., source and drain regions). Between the source and drain regions is a conductive layer which operates as a gate for the transistor. The gate controls current in a channel between the source and drain regions. 
     Typically, an integrated circuit gate includes a gate electrode and a gate dielectric. The electrical thickness of MOS gate dielectrics can be an important parameter in the design and fabrication of the circuit. Such a thickness determination can be made from the gate capacitance in the inversion region. The inversion region refers to the characteristic of a transistor where the channel between active regions and under the gate is “inverted”. That is, the channel changes from a semiconductor P-type to N-type or N-type to P-type. Generally, the inversion region occurs when the gate to source voltage (V gs ) is greater than or equal to the threshold voltage (V th ). 
     However, as the physical thickness of gate dielectrics decreases (with the continuing decrease in integrated circuit size), gate leakage current due to direct tunneling increases. As a result, inversion region capacitance-voltage (C-V) characteristics can be so distorted (from gate leakage current) that the electrical thickness extraction or determination is less accurate. 
     Accordingly, there is a need for an improved technique for gate capacitance-voltage (C-V) measurement. Further, there is a need to use forwarded biased MOSFET structures to measure the inversion region gate capacitance at a reduced gate electrical field, thereby reducing the effects of gate leakage. Even further, there is a need for a method of measuring gate capacitance to more accurately determine the thickness of gate dielectrics. 
     SUMMARY OF THE INVENTION 
     An exemplary embodiment relates to a method of measuring gate capacitance to determine electrical thickness of a gate dielectric located in a gate structure of a metal oxide semiconductor field effect transistor (MOSFET). This method can include connecting a sensor to an integrated circuit gate structure and an active region located proximate the integrated circuit gate structure, applying forward body bias to the transistor to reduce the electrical field of the transistor at a gate inversion measuring point, and measuring capacitance with the sensor while the transistor receives the forward body bias. 
     Another exemplary embodiment relates to a method of measuring gate dielectric thickness in a metal oxide semiconductor field effect transistor (MOSFET). This method can include applying a voltage to a back gate of a transistor to reduce threshold voltage of the transistor, connecting a capacitance-voltage meter to the transistor, using the capacitance-voltage meter to measure the capacitance at a voltage above the threshold voltage of the transistor, and automatically determining thickness of a gate dielectric in the transistor using the measured capacitance. 
     Another exemplary embodiment relates to a method of automatically determining gate capacitance in a transistor having a gate structure including a gate dielectric. This method can include forward biasing a transistor having agate structure and a size greater than 100 square microns to reduce a voltage threshold of the transistor and measuring capacitance of the transistor at a voltage above the voltage threshold of the transistor. 
     Other features and advantages of the exemplary embodiments will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention is illustrated by way of example and not limitation by the figures of the accompanying drawings, in which like references indicates similar elements and in which: 
     FIG. 1 is a schematic representation of a gate capacitance measurement configuration in accordance with an exemplary embodiment; 
     FIG. 2 is a circuit diagram representation of the gate capacitance measurement configuration of FIG. 1; 
     FIG. 3 is a plot of capacitance and voltage under various conditions; and 
     FIG. 4 is a flow diagram depicting an exemplary measurement process in accordance with an exemplary embodiment. 
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     Referring to FIG. 1, a schematic  10  includes a gate  12 , a substrate  14 , a source  16 , a drain  18 , and a meter  20 . Gate  12 , substrate  14 , source  16 , and drain  18  are part of an integrated circuit (IC) device including several transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs). In an exemplary embodiment, a large MOSFET, (e.g., greater than 100 microns 2 ) is used to measure gate capacitance. 
     Gate  12  can include a gate electrode  23  and a gate dielectric  25 . Gate  12  is aligned between source  16  and drain  18 . Source  16  and drain  18  are active regions in substrate  14  impurities or dopants, such as, a P-type dopant (e.g., boron) or an N-type dopant (e.g., phosphorous). 
     Meter  20  is a sensor configured to measure capacitance and voltage. An example of meter  20  is a 4284A LCR meter manufactured by Agilent Technologies of Palo Alto, Calif. Alternatively, meter  20  can be part of a workstation or a computer. The computer executes software that determines capacitance in response to a voltage measurement. 
     In an exemplary embodiment, meter  20  is coupled to gate  12  and source  16 . Gate inversion capacitance can be obtained by connecting meter  20  to gate  12  and source  16  and taking a sweep gate voltage measurement. The sweep gate voltage can be from 0.0 to 1.0 volts. In order to determine device capacitance, and, consequently, the thickness of gate dielectric  25 , gate inversion capacitance is measured at the strong inversion region. The onset of the strong inversion region is marked by the device threshold voltage (V TH ). The thickness of gate dielectric  25  can be determined using measured capacitance utilizing the formula          t   inv     =       EoxEo   C                   A                            
     where Eox is the relative value of the dielectric constant, Eo is the permativity of free space, C is the measured capacitance, and A is the size of the MOSFET. 
     In an exemplary embodiment, the device threshold voltage (V TH ) is lowered by forward biasing the transistor. Forward biasing the transistor can be at a voltage, such as, 0.5 V, which then lowers the gate voltage and, hence, the amount of gate leakage current experienced. The transistor can be biased at a voltage controlled by the contact potential of a p-n junction in the transistor. This contact potential and bias voltage are related by the formula          Vo   =       kt   q                   ln                   NaNd     n   i   2           ,                          
     where k is the Boltzman constant, t is the temperature, q is the charge, Na is the acceptor density, Nd is the donor density, and n 1  is the intrinsic carrier density. Advantageously, with lass gate leakage current present, more accurate capacitance measurements can be obtained as well as more accurate measurements of the gate dielectric. 
     Advantageously, this technique of measuring capacitance and, thereby, determining gate dielectric thickness is compatible with capacitance voltage measurement tools available. Further, this technique can be employed automatically by measuring devices and measuring equipment. Such a measurement can be made in a wafer fabrication process included on an in-line measurement system in an integrated circuit fabrication process. 
     FIG. 2 illustrates a circuit diagram representation where meter  20  is coupled to MOSFET  30 . MOSFET  32  includes a back gate  32  which, in an exemplary embodiment, is forward biased. Forward bias to back gate  32  reduces threshold voltage (VTH). As explained above, reduction of the threshold voltage reduces the gate electrical field and gate leakage current. Reduction of the threshold voltage also reduces the onset of the strong inversion region, where capacitance is measured. Thus, forward biasing the transistor before a capacitance measurement is taken advantageously reduces the measuring point such that less leakage current is experience, resulting in less distortion in the capacitance-voltage measurement. For example, gate leakage can be reduced from 0.1 A/cm 2  to 0.01 A/cm 2 . 
     FIG. 3 illustrates a graph  40  of capacitance and voltage. Line  42  represents the ideal capacitance-voltage relationship. Line  44  represents capacitance-voltage distortion due to gate leakage. Line  46  represents capacitance-voltage with forward bias applied. 
     Advantageously, the technique of capacitance measurement described with reference to FIGS. 1-3, provides for a closer approximation of the ideal C-V in the strong inversion region above the threshold region. Line  46  illustrates that less distortion occurs in the C-V measurement due to leakage when forward bias is used than when not used (line  44 ). This technique can be automatically followed by measuring instruments to provide a more accurate capacitance determination. 
     FIG. 4 illustrates a flow diagram  400  showing steps in an exemplary measurement process. In a step  410 , a sensor probe is coupled to an integrated circuit wafer. In an exemplary embodiment, a sensor probe is coupled to the integrated circuit wafer from a computer workstation in an in-line wafer manufacturing system. In another exemplary embodiment, the sensor probe is coupled to the wafer manually. 
     After step  410 , a step  420  is performed in which the back bias is set. In an exemplary embodiment, a back bias of 0.5 volts is applied. After step  420  is performed, a step  430  is performed in which a sweep voltage is applied. In an exemplary embodiment, sweep voltage can include a range of voltages between 0.0 volts and 1.0 volts. In a step  440 , capacitance is measured at the sweep voltages. In an exemplary embodiment, capacitance is determined automatically using a computer to determine capacitance from measured voltage. After step  440 , a step  450  is performed in which the sensor probe is uncoupled. 
     While the embodiments illustrated in the FIGURES and described above are presently preferred, it should be understood that these embodiments are offered by way of example only. Other embodiments may include a variety of different processes for carrying out the functions described. The invention is not limited to a particular embodiment, but extends to various modifications, combinations, and permutations that nevertheless fall within the scope and spirit of the appended claims.