Abstract:
A method for balancing signals across an IC design having multiple voltage domains. The method uses a voltage tress to balance the signals at the top level above the voltage domains. Then using worst case and best case signal latencies determines the average latency in each voltage domain. Then balancing signals at the other levels of the design by incrementing the latencies in each domain until a target level based on the slowest average latency is reached.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application is related to another U.S. Patent Application, IBM Docket Number BUR920020136US1, entitled “Programmable Delay Method for Hierarchical Signal Balancing,” which is filed concurrently with this application by the same assignee and is incorporatated herein by reference. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    This invention relates generally signal balancing, specifically to a method, system and software for balancing signals spanning multiple voltage domains.  
           [0004]    2. Background of the Invention  
           [0005]    The semiconductor industry is constantly increasing the number of circuits and functionality that can be compressed onto a single die. As process dimensions decrease, this ability has grown at an astronomical rate. The ability to put entire functioning systems on a single die is now the norm rather than the exception. As a consequence of this growth, the die/integrated circuit can be viewed as compilation of functioning islands.  
           [0006]    Some of these islands operate at different voltages from one another, others have the ability to switch to standby or sleep mode, while still others result from the need to isolate noisy circuitry. The ability to combine these different islands onto a single integrated circuit, requires techniques and circuitry for propagating communication (clocks, signals, etc), power, and output results.  
           [0007]    In a design without Voltage Islands, the entire signal operates on identical power rails. Even though the voltage varies between best case (“BC”) and worst case (“WC”) conditions, every buffer on the power rail is assumed to operate at an identical voltage for balancing purposes. However, with the use of Voltage Islands signal buffers are powered by separate power rails. As a result the signal&#39;s buffers operate at various voltage conditions between voltage islands and voltage domains to be balanced.  
         BRIEF SUMMARY OF THE INVENTION  
       SUMMARY OF THE INVENTION  
         [0008]    This invention is a method and media to balance signals operating on multiple power rails and thus multiple voltage conditions. Additionally it provides methods of modeling the resulting signal skew.  
           [0009]    The invention for balancing signals across an voltage island domain in an IC design comprises the steps of balancing signals at heirarchial levels above the voltage domains and balancing signals at the other levels in the design as a function of varying operating conditions across the voltage domains in the IC. 
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0010]    [0010]FIG. 1 is a block diagram that schematically illustrates a structure of a balanced signal spanning multiple Voltage Domains.  
         [0011]    [0011]FIG. 2 is a block diagram that schematically illustrates sources of signal skew.  
         [0012]    [0012]FIG. 3 is a diagram in schematic form that represents a typical computer system hardware environment for practicing this invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0013]    Voltage Islands complicate signal balancing for two primary reasons: 1) The signal is divided among multiple Random Logic Macros (RLMs) while design, layout and balance routing is performed independently within each RLM. During operation the voltage level within each Voltage Island independently floats between Best Case (BC) and Worst Case (WC) conditions resulting in signal latencies within each Voltage Domain which vary independently of each other over a known range. Signal arrival times can vary by over 20% of the total signal&#39;s latency as voltage levels float between BC and WC conditions. The independent floating of voltage levels between separate voltage domains introduces additional skew. As a result, the goal of signal balancing in Voltage Island designs is to balance the signal over all possible combinations of operating conditions, instead of one specific condition.  
         [0014]    [0014]FIG. 1 illustrates an example of a signal extending through two voltage domains  1  and  2  and the top level of the design  3 . The objective is to balance the signal&#39;s arrival time at each sink  8  throughout the heirarchy of the design, regardless of the voltage condition at the top level or any Voltage Island. The signal tree is inserted and balanced separately within each Voltage Island assuming WC voltage in all voltage domains. The result is a balanced signal from point A to points B, D, and F in FIG. 1, regardless of the voltage condition at the top level or at any Voltage Island. The signal&#39;s latency along these three paths from source  6  to sinks  8  are only affected by the voltage condition of the top level. As the top level&#39;s voltage varies between BC and WC conditions, the signal&#39;s arrival time at points B, D, and F are assumed to stay balanced. As a result, these points  6  are referred to as “equivalent” or common starting points for the rest of the tree.  
         [0015]    For the rest of the tree, paths Bá†′C, Dá†′E, and Fá†′G (cell paths  6  to  8 ) are balanced within each voltage domain, but not to each other. In other words, the signal&#39;s arrival time matches for all sinks at point C. However, point C is not balanced to points E or G. If the signal&#39;s latency through each of these three paths is balanced at one specific voltage condition (for example WC voltage), a well-balanced signal tree is produced only if all three voltage domains operate at the specific voltage condition. As the voltage within each Voltage Island floats between BC and WC conditions, the sinks  8  across the global design experience additional skew.  
         [0016]    The objective of signal balancing in Voltage Island designs is to globally balance the signal&#39;s latency over every possible voltage condition. To accomplish this, the balancing tool of this invention examines the signal&#39;s latency at BC and WC conditions in each Voltage Island, and calculates the mid-point of each Voltage Island. This mid-point is considered the “average latency” for each path. (Note: The “average latency” is not the nominal case, the average latency depends solely on the BC and WC conditions.) The delay of the programmable delay element on each path is progressively increased until the “average latency” matches an initial target. Normally the initial target is the slowest average latency.  
         [0017]    During each stage of balancing, the BC and WC voltage conditions are reevaluated to calculate an updated average latency. By balancing to the average latency, signal skew is minimized when individual Voltage Islands operate at the edges of their operational range (i.e. BC or WC voltage). The final result is a signal optimally balanced for any combination of voltage conditions, but not necessarily balanced at a specific voltage condition.  
         [0018]    A major advantage of this method is it is possible to change a voltage island&#39;s operational voltage range after design work is complete. This is possible since the signal latency is still adjustable because of the ease in reprogramming the delay elements. So, preferably the invention employs the method described in copending application “Programmable Delay Method for Hierarchical Signal Balancing” to make it possible to implement automated balancing routines.  
         [0019]    After the chip design is complete but prior to fabrication, the programmable delay elements&#39; functionality is fixed. Doing so turns the programmable delay elements into fixed blocks of delay where the amount of delay added is optimized for each signal branch. However, this invention does not depend upon the programmable delay methods. For example once latency targets between Voltage Islands have been calculated, it is also possible to balance the signal manually without programmable delay elements.  
         [0020]    The following example shows example BC and WC latencies (based on experimentation) for paths Bá†′C, Dá†′E, and Fá†′G shown in FIG. 1. For the given example assume the Voltage Islands operate at a higher voltage than the global design resulting in faster signal propagation. As mentioned previously, because the signal&#39;s arrival times at points B, D, and F are considered equivalent, only the latency of each path from the equivalent starting points are considered. Using the latency from the common starting points removes any dependency between the top-level voltage domain and the voltage islands during balancing.  
                                     TABLE 1                           Initial Average Latency Calculation                Path   BC Latency   WC Latency   Avg. Latency                       B→C   0.85   1.05   0.95           D→E   0.90   1.30   1.10           F→G   0.65   0.85   0.75                      
 
         [0021]    Table 1 displays average signal arrival times within each Voltage Island. In the example shown paths Bá†′C and Fá†′G are faster than the signal&#39;s arrival time at the top level. The slowest average latency, 1.10 ns, is selected as the target for balancing. During balancing the algorithm incrementally increases the delay along each Voltage Island as it attempts to optimally match each voltage domain&#39;s average latency. After each delay increment the algorithm reevaluates the BC and WC latencies to recalculate updated average latency values.  
                                     TABLE 2                           Nth-Pass Average Latency Calculation                Path   BC Latency   WC Latency   Avg. Latency                       B→C   1.00   1.20   1.10           D→E   0.90   1.30   1.10           F→G   0.85   1.05   0.95                      
 
         [0022]    After several more iterations the latency of path Bá†′C matches the 1.10 ns target as close as possible. However, as shown in Table 2 the latency along path Fá†′G, Voltage Island 2, requires further processing. After some additional adjustments the average latency of path Fá†′G matches the original path. This is shown in Table 3. Note: To simplify the current example, no design skew was introduced and an assumption is made that perfect balancing is possible. Design skew is the difference in average latency due to imperfect balancing between domains plus any standard design skew. In an actual design there is slight average latency mismatch yielding additional design skew.  
                                     TABLE 3                           Final-Pass Average Latency Calculation            Path   BC Latency   WC Latency   Avg. Latency   Voltage Jitter               B→C   1.00   1.20   1.10   0.10       D→E   0.90   1.30   1.10   0.20       F→G   1.00   1.20   1.10   0.10                  
 
         [0023]    The concept of “Voltage Jitter” is introduced in Table 3. Voltage Jitter is the maximum amount a signal&#39;s arrival time can deviate from the average latency due to the voltage level floating between BC and WC conditions. For example, the latency of path Dá†′E varies at most Å±0.2 ns from the 1.10 ns target. Voltage Jitter does not effect sinks within a single voltage domain since all signal paths in a voltage domain operate at identical voltage conditions in any given time. However when considering timing between voltage domains, skew increases by the Voltage Jitter of each voltage domain plus any design skew between the domains.  
         [0024]    In the example shown in Table 3, the maximum additional skew is 0.30 ns (0.1 ns Bá†′C voltage jitter+0.2 ns Dá†′E voltage jitter+0.00 ns design skew between Bá†′C and Dá†′E. Note: As stated in the above paragraph for this example, there is no design skew. This an unlikely event in a real design. However, one can see how, in an actual design, design skew is considered. The maximum additional skew is evident when path Dá†′E operates at BC voltage (0.9 ns) and path Bá†′C operates at WC voltage (1.2 ns). Note that the 0.3 ns difference is less than the 0.4 ns range in arrival times for sinks at point E, which vary between 0.9 ns and 1.3 ns. The improvement is possible because balancing considered both BC and WC timing modes, rather than just a single timing mode.  
         [0025]    Table 4 shows two signal balancing examples and the corresponding range of signal arrival times. The last two columns illustrate balancing at a specific operating condition. Here the voltage domains were balanced assuming each voltage domain operates at WC voltage. During operation if every voltage domain operates at WC voltage, total signal skew due to voltage effects is non existent. However, if path D-&gt;E shifts to BC voltage, sink latencies vary from 0.90 ns to 1.30 ns, resulting in 0.40 ns of signal skew due to voltage effects, which is 33% worse than balancing to the average latency.  
                                                           TABLE 4                           Two Signal Balancing Examples: Average       Latency versus Worst Case Latency                Balancing to Average       Balancing to Worse Case               Latency: Skew = 0.30 ns       Latency: Skew = 0.40 ns                Path   Range   Path   Range                       B→C   1.10-1.20   B→C   1.10-1.30           D→E   0.90-1.30   D→E   0.90-1.30           F→G   1.10-1.20   F→G   1.10-1.30                      
 
         [0026]    [0026]FIG. 2 shows an example of how to model separate sources of signal skew across Voltage Islands. Design skew values represent the standard skew found in hierarchical designs without the use of voltage islands and are caused by the combination of unbalanced wiring and RLM signal latency mismatches  5  and  7 . Once voltage islands are introduced, Voltage Jitter  6  must also be considered. Signals traversing a voltage domain experience the effect of both domains&#39; Voltage Jitter components. In this example, the additional skew for a signal traveling between Voltage Island 1 and the top level is: 100 ps+200 ps=300 ps. Signals which do not traverse a voltage domain, are not required to consider Voltage jitter components since all relevant signal paths operate at an identical voltage level.  
         [0027]    However, signals which travers voltage domains  9 ,  10 , and  11  must take into account all sources of design skew, source jitter and voltage jitter. Note, voltage jitter represents over half of the skew on a balanced signal making it the primary source of overall skew. This highlights how dominating the voltage jitter component is, i.e. how much worse signal balancing is because of voltage jitter, and thus why it has to be considered. Since voltage jitter is just how much the latency of a signal&#39;s path can vary from the ‘average latency’ because of voltage effects, voltage jitter is just an easy method to look at and understand the effect voltage drift on power rails have on balancing.  
         [0028]    A representative hardware environment for practicing the present invention is depicted in FIG. 3, which illustrates the typical hardware configuration of a computer system capable of performing the signal balancing in accordance with the present invention. The typical environment has at least one processor or central processing unit (CPU)  510 . CPUs  510  are interconnected via system bus  520  to a random access memory (RAM)  530 , read-only memory (ROM)  540 , an input/output (I/O) adapter  560  for connecting peripheral devices such as disk units  570  and tape drives  580  to bus  520 , user interface adapter  600  for connecting keyboard  610 , mouse  620 , speaker  630 , microphone  640 , and/or other user interface devices such as touch screen device (not shown) to bus  520 , communication adapter  650  for connecting the information handling system to a data processing network, and display adapter  660  for connecting bus  520  to display device  670 . The design system comprising the design information needed for this invention, libraries, simulation and verification software can be loaded on the appropriate disk or tape units or fed either through I/O adapters or the network for processing. A computer program with an appropriate application interface could be created by one of skill in the art and stored on the system to simplify the practicing of this invention.  
         [0029]    It is thus believed that the operation and construction of the present invention will be apparent from the foregoing description. The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.