Abstract:
A sign extension unit has first and second sign extenders to extend a sign bit, i.e., the most significant bit of input data to the higher side of the input data. The input data is divided into n-bit blocks. The first sign extender carries out sign extension based on highest bits of the blocks, and the second sign extender carries out sign extension in each of the blocks based on the highest bits of the respective blocks.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a sign extension unit for extending a sign bit, i.e., the most significant bit of input data to the higher side of the input data. 
     2. Description of Related Art 
     FIG. 1 shows a sign extension circuit  301  according to a related art. The sign extension circuit  301  receives input data of byte length (8 bits), half-word length (16 bits), word length (32 bits), or double-word length (64 bits) and extends a sign bit thereof to form signed 64-bit output data. The circuit  301  has selectors MM 8  to MM 63  to receive input data consisting of bits IN 0  to IN 63  at the maximum. The selectors MM 8  to MM 15  select the bit IN 7  or the bits IN(8+n) (n=0 to 7) and provide the selected bits as output bits OUT 8  to OUT 15 . The selectors MM 16  to MM 31  select the bit IN 7 , the bit IN 15 , or the bits IN(16+n) (n=0 to 15) and provide the selected bits as output bits OUT 16  to OUT 31 . The selectors MM 32  to MM 63  select the bit IN 7 , the bit IN 15 , the bit IN 31 , or the bits (32+n) (n=0 to 31) and provide the selected bits as output bits OUT 32  to OUT 63 . The selection made by the selectors MM 8  to MM 63  is based on the length of input data. 
     Upon receiving input data of byte length consisting of bits IN 0  to IN 7 , the selectors MM 8  to MM 63  select the bit IN 7  serving as a sign bit of the input data for output bits OUT 8  to OUT 63 , and the bits IN 0  to IN 7  are provided as they are as output bits OUT 0  to OUT 7 . Namely, the sign bit of the input data is extended for the output bits OUT 8  to OUT 63 , and the output bits OUT 0  to OUT 63  form sign-extended 64-bit output data. Upon receiving input data of half-word length consisting of bits IN 0  to IN 15 , the selectors MM 16  to MM 63  select the bit IN 15  serving as a sign bit of the input data for output bits OUT 16  to OUT 63 , the bits IN 0  to IN 7  are provided as they are as output bits OUT 0  to OUT 7 , and the selectors MM 8  to MM 15  select the bits IN 8  to IN 15  as output bits OUT 8  to OUT 15 . Namely, the sign bit of the input data is extended for the output bits OUT 16  to OUT 63 , and the output bits OUT 0  to OUT 63  form sign-extended 64-bit output data. Upon receiving input data of word length consisting of bits IN 0  to IN 31 , the selectors MM 32  to MM 63  select the bit IN 31  serving as a sign bit of the input data for output bits OUT 32  to OUT 63 , the bits IN 0  to IN 7  are provided as they are as output bits OUT 0  to OUT 7 , and the selectors MM 8  to MM 31  select the bits IN 8  to IN 31  as output bits OUT 8  to OUT 31 . Namely, the sign bit of the input data is extended for the output bits OUT 32  to OUT 63 , and the output bits OUT 0  to OUT 63  form sign-extended 64-bit output data. Upon receiving input data of double-word length consisting of bits IN 0  to IN 63 , the bits IN 0  to IN 7  are provided as they are as output bits OUT 0  to OUT 7 , and the selectors MM 8  to MM 63  select the bits IN 8  to IN 63  as output bits OUT 8  to OUT 63 . Namely, the input data is provided as it is as 64-bit output data. 
     This related art supplies an input bit IN 7  to the 56 selectors MM 8  to MM 63 . Namely, the input bit IN 7  must drive the gates of the 56 selectors, and long wiring must be laid to transmit the input bit IN 7  to the 56 selectors. In this way, the related art applies large load on the input bit IN 7 , to increase signal delay and decrease operation speed. 
     To solve this problem, there is an idea of inserting buffers in signal paths for transmitting the input bit IN 7 . The buffers, however, cause gate delay and increase the size of the circuit  301 . 
     In addition, input bits IN 15  and IN 31  must drive large load, and therefore, these bits involve the same problem as the bit IN 7 , although the load on the bits IN 15  and IN 31  is relatively small compared with that on the bit IN 7 . 
     In this way, the related art applies large load on some bits of input data, to increase signal delay and decrease operation speed. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a sign extension unit capable of reducing load on paths for transmitting a sign bit. Another object of the present invention is to provide a sign extension unit capable of operating at high speed. 
     In order to accomplish the objects, the present invention provides a sign extension unit having first and second sign extenders. Input data consisting of input bits to the sign extension unit is divided into blocks of equal number of bits. The first sign extender receives highest bits from the blocks, selects a sign bit of the input data or the received bits according to the bit length of the input data, and provides the selected bits. The second sign extender receives the input bits from the blocks except a lowest one of the blocks, selects the highest bits of the blocks or the input bits according to the bit length of the input data, and provides the selected bits. 
     The first sign extender may have selectors for receiving the highest bits from the blocks, selecting the received bits or the sign bit of the input data according to data length information related to the input data, and providing the selected bits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a sign extension unit according to the related art; 
     FIG. 2 shows a sign extension unit according to an embodiment of the present invention; 
     FIG. 3 shows an example of a first sign extender according to the embodiment; 
     FIG. 4 shows another example of the first sign extender according to the embodiment; 
     FIG. 5 shows the details of the example of FIG. 4; and 
     FIG. 6 shows an example of a second sign extender according to the embodiment. 
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified. 
     FIG. 2 shows a sign extension unit  310  according to an embodiment of the present invention. The unit  310  receives input data of byte length (8 bits), half-word length (16 bits), word length (32 bits), or double-word length (64 bits) and extends a sign bit thereof to form signed 64-bit output data. Input data to the unit  310  is divided from the least significant bit thereof into n-bit blocks. The unit  310  has a first sign extender (FSE)  311  and seven second sign extenders (SSEs)  321 . The first sign extender  311  extends a sign bit of the input data for highest bits of the blocks. The second sign extenders  321  extend the sign bit for the respective blocks according to the bits provided by the first sign extender  311 . 
     In this embodiment, 64-bit input data consisting of bits 0 to 63 is divided by eight from the least significant bit thereof into eight 8-bit blocks. The first sign extender  311  receives the highest bits  7 ,  15 ,  23 ,  31 ,  39 ,  47 ,  55 , and  63  from the blocks. In general, input data is divided by “n” into n-bit blocks, and therefore, highest bits of the blocks are expressed as “nL−1” where L is 1, 2, 3, and the like. 
     FIG. 3 shows a first sign extender  312  as an example of the first sign extender  311  of FIG.  2 . The extender  312  has selectors M 1   1  to M 1   7 . A piece of 64-bit input data consists of bits IN 0  to IN 63 , which are divided by eight into eight 8-bit blocks according to the embodiment. The selector M 1   1  receives the highest bit IN 7  from the first block (the bits IN 0  to IN 7 ) and the highest bit IN 15  from the second block (the bits IN 8  to IN 15 ), selects one of them, and provides the selected bit as an output bit OUT 15 . The selector M 1   2  receives the highest bits IN 7  and IN 15  and the highest bit IN 23  from the third block (the bits IN 16  to IN 23 ), selects one of them, and provides the selected bit as an output bit OUT 23 . The selector M 1   3  receives the highest bits IN 7  and IN 15  and the highest bit IN 31  from the fourth block (the bits IN 24  to IN 31 ), selects one of them, and provides the selected bit as an output bit OUT 31 . The selector M 1   4  receives the highest bits IN 7 , IN 15 , and IN 31  and the highest bit IN 39  from the fifth block (the bits IN 32  to IN 39 ), selects one of them, and provides the selected bit as an output bit OUT 39 . The selector M 1   5  receives the highest bits IN 7 , IN 15 , and IN 31  and the highest bit IN 47  from the sixth block (the bits IN 40  to IN 47 ), selects one of them, and provides the selected bit as an output bit OUT 47 . The selector M 1   6  receives the highest bits IN 7 , IN 15 , and IN 31  and the highest bit IN 55  from the seventh block (the bits IN 48  to IN 55 ), selects one of them, and provides the selected bit as an output bit OUT 55 . The selector M 1   7  receives the highest bits IN 7 , IN 15 , and IN 31  and the highest bit IN 63  from the eighth block (the bits IN 56  to IN 63 ), selects one of them, and provides the selected bit as an output bit OUT 63 . 
     These selectors M 1   1  to M 1   7  carry out the selection according to the bit length of input data. If the input data is of byte length consisting of bits IN 0  to IN 7 , the selectors M 1   1  to M 1   7  select each the bit IN 7 . If the input data is of half-word length consisting of bits IN 0  to IN 15 , the selectors M 1   1  to M 1   7  select each the bit IN 15 . If the input data is of word length consisting of bits IN 0  to IN 31 , the selector M 1   1  selects the bit IN 15 , the selector M 1   2  the bit IN 23 , and the selectors M 1   3  to M 1   7  the bit IN 31 . If the input data is of double-word length consisting of bits IN 0  to IN 63 , the selector M 1   1  to M 1   7  select the bits IN 15 , IN 23 , IN 31 , IN 39 , IN 47 , IN 55 , and IN 63 , respectively. 
     In this way, the first sign extender  312  receives every eighth bit of input data. If the input data is of 64 bits ranging from bit  0  to bit  63 , the extender  312  receives the bits  7 ,  15 ,  23 ,  31 ,  39 ,  47 ,  55 , and  63  of the input data. A cache memory of a processor, for example, aligns data eight bits by eight bits so that the data may easily be handled. Accordingly, it is advantageous for the extender  312  to divide input data into 8-bit blocks and manipulate one of the blocks because the data structure of the cache memory can be used as it is by the extender  312 . In FIG. 2, the remaining bits other than those handled by the extender  311  are grouped according to the every-eighth-bit grouping to utilize the data structure of the cache memory. It is not always necessary to arrange input bits in the manner of FIG. 2, except those supplied to the first sign extender  311 . 
     FIG. 4 shows another example of the first sign extender  311  of FIG.  2 . In FIG. 4, a load unit  100  provides a given address, a cache memory  200  provides data according to the address from the load unit  100 , and a sign extension unit  300  extends a sign of the data provided by the cache memory  200 . The address provided by the load unit  100  usually accompanies data length information indicating the bit length of the data stored at the address. Accordingly, the sign extension unit  300  receives the data length information as well. 
     FIG. 5 shows a first sign extender  313  serving as the sign extension unit  300  of FIG.  4 . Similar to the sign extender  312  of FIG. 3, the sign extender  313  has selectors M 1   1  to M 1   7  to select bits of input data according to data length information related to the input data. For example, the data length information is “1” if the input data is of 8 bits, “2” if it is of 16 bits, “3” if it is of 32 bits, and “4” if it is of 64 bits. The data length information is supplied to each of the selectors M 1   1  to M 1   7 . If the data length information is “1”, the selectors M 1   1  to M 1   7  select each a bit IN 7  from among input bits IN 0  to IN 7 . If the data length information is “2”, the selectors M 1   1  to M 1   7  select each a bit IN 15  from among input bits IN 0  to IN 15 . If the data length information is “3”, the selector M 1  selects a bit IN 15 , the selector M 1   2  a bit IN 23 , and the selectors M 1   3  to M 1   7  a bit IN 31  from among input bits IN 0  to IN 31 . If the data length information is “4”, the selector M 1   1  selects a bit IN 15 , the selector M 1   2  a bit IN 23 , the selector M 1   4  a bit IN 39 , the selector M 1   5  a bit IN 47 , the selector M 1   6  a bit IN 55 , and the selector M 1   7  a bit IN 63  from among input bits IN 0  to IN 63 . 
     FIG. 6 shows a second sign extender  322  as an example of any one of the second sign extenders  321  of FIG.  2 . The extender  322  comprises of selectors M 2 (8m−7) to M 2 (8m−1) (m being one of 1 to 7). The selector M 2 (8m−7) receives an input bit IN(8m) and an output bit OUT(8m+7) of the first sign extender  311 , selects one of them, and provides the selected one as an output bit OUT(8m). The selector M 2 (8m−6) receives an input bit IN(8m+1) and the output bit OUT(8m+7), selects one of them, and provides the selected one as an output bit OUT(8m+1). The selector M 2 (8m−5) receives an input bit IN(8m+2) and the output bit OUT(8m+7), selects one of them, and provides the selected one as an output bit OUT(8m+2). The selector M 2 (8m−4) receives an input bit IN(8m+3) and the output bit OUT(8m+7), selects one of them, and provides the selected one as an output bit OUT(8m+3). The selector M 2 (8m−3) receives an input bit IN(8m+4) and the output bit OUT(8m+7), selects one of them, and provides the selected one as an output bit OUT(8m+4). The selector M 2 (8m−2) receives an input bit IN(8m+5) and the output bit OUT(8m+7), selects one of them, and provides the selected one as an output bit OUT(8m+5). The selector M 2 (8m−1) receives an input bit IN(8m+6) and the output bit OUT(8m+7), selects one of them, and provides the selected one as an output bit OUT(8m+6). 
     The selectors M 2 (8m−7) to M 2 (8m−1) of the second sign extenders  322  (the second sign extenders  321  in FIG. 2) select bits of input data according to the bit length of input data. If the input data is of byte length, the selectors M 2 (8m−7) to M 2 (8m−1) select each the output bit OUT(8m+7) of the first sign extender  311 . If the input data is of half-word length, the selectors M 2   1  to M 2   7  select the input bits, and the selectors M 2 (8m−7) to M 2 (8m−1) (m=2 to 7) select the output bits OUT(8m+7) (m=2 to 7) of the first sign extender  311 . If the input data is of word length, the selectors M 2 (8m−7) to M 2 (8m−1) (m=1 to 3) select the input bits, and the selectors M 2 (8m−7) to M 2 (8m−1) (m=4 to 7) select the output bits OUT(8m+7) (m=4 to 7) of the first sign extender  311 . If the input data is of double-word length, all of the selectors M 2 (8m−7) to M 2 (8m−1) (m=1 to 7) select the input bits. 
     The selectors may be structured in various ways according to required functions. For example, they may be structured with logic gates, a combination of logic and transmission gates, or clocked inverters. 
     Upon receiving input data of byte length consisting of bits IN 0  to IN 7 , the selectors M 1   1  to M 1   7  of the first sign extender  312  select the sign bit IN 7  and provide the selected bit as output bits OUT(8m+7) (m=1 to 7). Then, all of the selectors M 2 (8m−7) to M 2 (8m−1) (m=1 to 7) of the second sign extenders  322  select and provide the output bits of the first sign extender  312 . As a result, the sign bit IN 7  of the input data is extended for output bits OUT 8  to OUT 63  to provide signed 64-bit output data. 
     Upon receiving input data of half-word length consisting of bits IN 0  to IN 15 , the selectors M 1 l to M 1   7  of the first sign extender  312  select the sign bit IN 15  and provide the selected bit as output bits OUT(8m+7) (m=1 to 7). Then, the selectors M 2   1  to M 2   7  of the first one of the second sign extenders  322  select the input bits IN 8  to IN 14  and provide the selected bits as output bits OUT 8  to OUT 14 . At the same time, the selectors M 2 (8m−7) to M 2 (8m−1) (m=2 to 7) of the other extenders  322  select the output bits of the first sign extender  311  and provide the selected bits as output bits OUT 16  to OUT 63 . As a result, the sign bit IN 15  of the input data is extended for the output bits OUT 16  to OUT 63  to provide signed 64-bit output data. 
     Upon receiving input data of word length consisting of bits IN 0  to IN 31 , the selectors M 1   3  to M 1   7  of the first sign extender  312  select the sign bit IN 31  and provide the selected bit as output bits OUT(8m+7) (m=3 to 7). At this time, the selector M 1   1  selects the input bit IN 15  and the selector M 1   2  the input bit IN 23 . Then, the selectors M 2 (8m−7) to M 2 (8m−1) (m=1 to 3) of the second sign extenders  322  select the input bits IN 8  to IN 31  and provide the selected bits as output bits OUT 8  to OUT 31 . The selectors M 2 (8m−7) to M 2 (8m−1) (m=4 to 7) of the remaining second sign extenders  322  select the output bits of the first sign extender  312  and provide the selected bits as output bits OUT 32  to OUT 63 . As a result, the sign bit IN 31  of the input data is extended for the output bits OUT 32  to OUT 63  to provide signed 64-bit output data. 
     Upon receiving input data of double-word length consisting of bits IN 0  to IN 63 , all of the selectors of the first and second sign extenders  312  and  322  select the input bits IN 0  to IN 63  to form output bits OUT 0  to OUT 63 . 
     In this way, the present invention limits the number of bits for which a sign bit is extended, to “n−1” or “(output bit length/n)−1” where “n” is the number of bits contained in each block when input data is divided into blocks. This technique greatly reduces load capacitance and wiring capacitance when extending input data to output data of long bit length. Input and output bits handled by the first and second sign extenders  311  and  321  of the present invention are juxtaposed, and load on a sign bit in each of the sign extenders is limited to the gates and wiring of the seven selectors of the extender. As a result, the present invention greatly reduces load on paths for transmitting a sign bit and improves operation speed compared with the related art. 
     In the above explanation, input data consists of 8, 16, 32, or 64 bits, sign-extended output data consists of 64 bits, and input data is divided into 8-bit blocks. These examples do not limit the present invention. For example, the present invention is applicable to handle 2 n -bit data. 
     In summary, the present invention divides input data into n-bit blocks, extends a sign bit of the input data for highest bits of the n-bit blocks, and extends the sign bit in the n-bit blocks according to the highest bits of the blocks. The present invention limits the number of bits for which a sign bit is extended, to “n−1” or “(output bit length n)−1.” As a result, the present invention reduces load on paths for transmitting a sign bit and improves operation speed. 
     The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiment is therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.