Abstract:
A data reproduction apparatus for an optical disc system is provided. Included is an analog-to-digital converter (ADC) for sampling an input RF signal and outputting the sampled result, an adder for adding the sampled signal and an asymmetry correction signal. The added signal is output. A blank/defect detector is provided for generating a blank detection signal if no change in data is detected from the added signal during a predetermined interval of time. A correction signal generator is provided for calculating a digital sum value (DSV) from the received added signal, generating an asymmetry correction signal based on the calculated DSV, and outputting the generated asymmetry correction signal to the adder. A waveform equalizer is provided for waveform-equalizing the added signal. A decoder is provided for decoding the waveform-equalized signal and outputting the result. The correction signal corrector temporarily stops a DSV calculation operation with respect to the interval of the corresponding added signal, if the blank detection signal is output. Thus, an asymmetry of the RF signal is corrected to enhance quality of the reproduced data.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of Korean Application No. 98-49542, filed Nov. 18, 1998, in the Korean Patent Office, the disclosure of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a data reproduction apparatus for an optical disc system. 
     2. Description of the Related Art 
     FIG. 1 is a block diagram showing a data reproduction apparatus for a conventional optical disc system. In the FIG. 1 apparatus, a radio frequency (RF) signal read from an optical disc is input to an analog-to-digital converter (ADC)  11  and a binarization circuit  14 . The binarization circuit  14  binarizes the RF signal and outputs the binarization signal to a phase locked loop (PLL)  15 . The PLL  15  receives the binarization signal and generates a clock signal PLCK synchronized with the RF signal. The clock signal PLCK is supplied to the ADC  11 , a waveform equalizer  12  and a Viterbi decoder  13 . The ADC  11  converts the input analog RF signal into a digital RF signal and outputs the digital RF signal to the waveform equalizer  12 . The waveform equalizer  12  receives the digital RF signal and waveform-equalizes the received digital RF signal into a form which is appropriate for the Viterbi decoder  13 . The Viterbi decoder  13  receives the waveform equalized signal to then be Viterbi decoded and outputs the result as a reproduction signal (VITO). The Viterbi decoding can restore the damaged signal when the RF signal is damaged due to noise interference in a channel, such as that which is widely used in a hard disc drive (HDD). 
     However, if in the input RF signal in the conventional data reproduction apparatus is asymmetrical, the Viterbi decoder does not restore the RF signal, thereby degenerating the quality of the reproduced data. 
     SUMMARY OF THE INVENTION 
     To solve the above problems, it is an object of the present invention to provide a data reproduction apparatus for an optical disc system which corrects asymmetry of an RF signal to improve the quality of the reproduced data. 
     Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention. 
     To accomplish the object of the present invention, a data reproduction apparatus is provided for an optical disc system in which a radio frequency (RF) signal detected from an optical recording medium is decoded to reproduce data, the data reproduction apparatus comprising: an analog-to-digital converter (ADC) for sampling the input RF signal and outputting the sampled result; an adder for adding the sampled signal and an asymmetry correction signal and outputting the added signal; a blank/defect detector for generating a blank detection signal if no change in data is detected from the added signal during a predetermined interval of time; a correction signal generator for calculating a digital sum value (DSV) from the received added signal, generating an asymmetry correction signal based on the calculated DSV, and outputting the generated asymmetry correction signal to the adder; a waveform equalizer for waveform-equalizing the added signal; and a decoder for decoding the waveform-equalized signal and outputting the result. Here, if a blank detection signal is output, the correction signal corrector temporarily stops a DSV calculation operation with respect to the interval of the corresponding added signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and advantages of the present invention will become more apparent by describing the preferred embodiment thereof in more detail with reference to the accompanying drawings in which: 
     FIG. 1 is a block diagram showing a data reproduction apparatus for a conventional optical disc system; 
     FIG. 2 is a block diagram showing a data reproduction apparatus for an optical disc system according to one embodiment of the present invention; 
     FIG. 3 is a graphical view showing a gain variation characteristic of the booster amplifier of FIG. 2; 
     FIG. 4 is a detailed circuit diagram of the blank/defect detector of FIG. 2; 
     FIG. 5 is a detailed circuit diagram of the ASM level generator of FIG. 2; 
     FIG. 6 is a detailed circuit diagram of the ADTGC unit of FIG. 2; 
     FIG. 7 is a detailed circuit diagram of the AGC unit of FIG. 2; and 
     FIG. 8 is a block diagram showing a data reproduction apparatus for an optical disc system according to another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures. 
     In FIG. 2, a booster amplifier  20  receives an RF signal detected from an optical disc, generates an amplification signal RFBSTO and outputs the same to an analog-to-digital converter (ADC)  21 . The ADC  21  generates a digital signal ADO and outputs the same to the first input port of an adder  22 . The adder  22  adds the signal input via the first input port and an asymmetry correction signal ASYVAL input via the second input port, and outputs the added result SYMO to a phase locked loop (PLL)  23 , a blank/defect detector  24 , a waveform equalizer  26  and a multiplexer  31 . The PLL  23  generates a clock signal PLCK and supplies the clock signal PLCK to the ADC  21  and other circuits which are described below. The blank/defect detector  24  receives the SYMO signal and generates the blank/defect detection signal BLANK to be supplied to the ASM level generator  25 . The waveform equalizer  26  receives the SYMO signal and generates the waveform equalized signal PRF to be output to an automatic gain control (AGC) unit  27 , an adaptive Tmin gain control (ADTGC) unit  28 , a Viterbi decoder  29  and a multiplexer  31 . The multiplexer  31  receives the SYMO signal and the PRF signal and outputs one of these received signals to the ASM level generator  25  according to a select signal ASMDS. The ASM level generator  25  receives the output of the multiplexer  31  and generates the ASYVAL signal to be output to the second input port of the adder  22 . The AGC  27  receives the PRF signal and generates a gain control signal RFAGC to be supplied to the booster amplifier  20 . The ADTGC unit  28  receives the PRF signal and generates filter coefficients KC′ and KD′ to be supplied to the waveform equalizer  26 . The Viterbi decoder  29  receives the PRF signal and outputs the reproduction signal VITO. 
     The operation of the FIG. 2 apparatus having the above configuration will be described below with reference to FIGS. 3 and 7. 
     In FIG. 2, the RF signal detected from the optical disc is input to the booster amplifier  20 . The booster amplifier  20  has a gain variation characteristic as shown in FIG. 3, and amplifies the RF signal according to the RFAGC signal supplied from the AGC unit  27 , to be described later. However, at the initial time of operation in the FIG. 2 apparatus, the input signal is amplified at an amplification rate set to an initial value. The ADC  21  receives the amplified RF signal RFBSTO, converts the same into a digital signal ADO, and outputs the digital signal ADO to the first input port of the adder  22 . The adder  22  adds the ADO signal and the asymmetry correction signal ASYVAL, which is input via the second input port. At the initial time of operation in the FIG. 2 apparatus, the ASYVAL value is set to “0” and the ADO signal is output as the added signal SYMO. The blank/defect detector  24  detects an interval where no data is recorded, or data is damaged due to a defect on a disc, from the received SYMO signal in such a manner that an asymmetry level can be accurately detected in the ASM level generator  25 . 
     The detailed configuration and operation of the blank/defect detector  24  will be described below with reference to FIG.  4 . The SYMO signal output from the adder  22  is input to an edge detector  41  and an absolute value calculator  43  in the blank/defect detector  24 . The edge detector  41  detects an edge from the input SYMO signal and applies an edge detection signal to a first check unit  42 . The first check unit  42  checks the length of a sign bit from the point in time when one edge detection signal is output until the following edge detection signal is output. The first check unit  42  generates a first check signal, to be output to an OR gate  46 , indicating that no variation exists in the input signal for an interval nT when an edge is not detected for the interval nT. Here, T denotes a period of clock PLCK and n is an integer. The absolute value calculator  43  calculates an absolute value of the SYMO signal to be output to a shift unit  44 . The shift unit  44  shifts the absolute value of the SYMO signal to the right by a set value supplied from a controller (not shown). A second check unit  45  checks whether a value of zero is sequentially input from the shift unit  44 . If a value of zero is sequentially input for the interval nT, the second check unit  45  generates a second check signal, to be output to the OR gate  46 , indicating that data greater than a predetermined value does not exist for the interval nT. The OR gate  46  logically sums the outputs of the check units  42  and  45  and outputs the result. That is, if any one of the first or second check signals is output, the OR gate  46  generates a blank/defect detection signal BLANK indicating that no data has been recorded or that data has been lost. 
     Referring back to FIG. 2, the waveform equalizer  26  receives the SYMO signal to perform a waveform equalization operation. The waveform equalizer  26  utilizes filter coefficient values set to initial values at the initial time of operation. The multiplexer  31  selects either the SYMO signal or the waveform equalized signal PRF output from the waveform equalizer  26  according to the selection signal ASMDS and outputs the selected result to the ASM level generator  25 . The ASM level generator  25  receives the output of the multiplexer  31  and detects an asymmetry level of the received signal. 
     FIG. 5 is a detailed circuit diagram of the ASM level generator of FIG. 2. A sign detector  52  in the ASM level generator  25  detects a sign of the signal input from the multiplexer  31  and outputs the detected result to an up/down counter  53 . The up/down counter  53  performs an up-counting operation when a sign detected in the sign detector  52  is positive (+) and a down-counting operation when the sign is negative (−). If the BLANK signal is output from the blank/defect detector  24 , the counting operation is stopped since reliability with respect to the input data is lowered. The count value UDCNT of the up/down counter  53  is a digital sum value DSV with respect to the input data. As the DSV increases , the asymmetry of the input signal increases. A comparator  54  obtains an absolute value of the UDCNT and compares the obtained absolute value with a predetermined DSV threshold value DSVTH. The comparator  54  generates a determination resultant signal indicating that the absolute value of the UDCNT is larger than the DSVTH, if it is determined that the former is larger than the latter, and then outputs the determination resultant signal to an accumulator  51  and a reset of the up/down counter  53 . 
     The accumulator  51  generates the ASYVAL value based on the UDCNT value if the determination resultant signal indicating the absolute value of the UDCNT is larger than the DSVTH is output. In more detail, when a sign of the UDCNT is positive, the ASYVAL value having a negative sign and a value proportional to the absolute value of the UDCNT is generated. Meanwhile, when a sign of the UDCNT is negative, the ASYVAL value having a positive sign and a value proportional to the absolute value of the UDCNT is generated. The ASYVAL value is output to the second input port of the adder  22  of FIG.  2 . The adder  22  adds the ASYVAL value to the current input signal input via the first input port, to thereby continuously output the asymmetry corrected signal. 
     Meanwhile, the ADTGC  28  extracts data corresponding to a  3 T level which is an intermediate value of the data used in the Viterbi decoder  29  among the data input to the Viterbi decoder  29  and checks whether the extracted level is appropriate. 
     In FIG. 6, showing a detailed circuit diagram of the ADTGC unit  28  of FIG. 2, delays  611 - 613  and comparators  614 - 617  extract a signal corresponding to 3T from the PRF signal. The delays  611 - 613 , which are connected in series, delay the waveform equalized signal PRF in sequence by one period of the clock signal PLCK, respectively. The comparator  614  obtains the absolute value of the input PRF signal and compares the obtained absolute value with a reference value EQRNG for detecting a 3T signal. The comparator  614  judges that the input signal is a 3T signal if the absolute value of the PRF is smaller than EQRNG, to thus generate a first enable signal E 1 . The first enable signal E 1  is output to operators  618  and  619 . The comparator  615  receives delay signals D 1  and D 2 , output from the delays  611  and  612 , respectively, and obtains an absolute value of the difference between the values of the delay signals D 1  and D 2 . Also, the obtained absolute value is compared with EQRNG. If the former is smaller than the latter, it is judged that the delay signals D 1  and D 2  are signals having similar levels, respectively. This means that the input data is synchronized with the PLL  23 . The second comparator  615  outputs a determination resultant signal to the fourth comparator  617 . The fourth comparator  617  receives the determination resultant signal from the second comparator  615  and the delay signals D 1  and D 2  from the delays  611  and  612  and compares the delay signals D 1  and D 2  with the EQRNG signal, respectively. Due to the result of the comparison, when the delay signals D 1  and D 2  are larger than the EQRNG signal, it is determined that the delay signals D 1  and D 2  are signals having a value larger than an appropriate level which is not close to a zero value, respectively, to thereby output a second enable signal E 2  to the operator  618 . In the mean time, when the delay signals D 1  and D 2  are smaller than the EQRNG signal, it is determined that the delay signals D 1  and D 2  are signals having a value smaller than an appropriate level which is not close to a zero value, respectively, to thereby output a fourth enable signal E 4  to the operator  619 . The comparator  616  obtains the absolute value of the delay signal D 3 , output from the delay  613 , and compares the obtained absolute value with EQRNG. In the comparison result, if the absolute value of the delay signal D 3  is smaller than EQRNG, a third enable signal E 3  is generated to be output to the operators  618  and  619 . The operators  618  and  619  become enabled when all of the enable signals E 1 , E 2  (or E 4 ), and E 3  are output. Here, if the enable signals E 1 , E 2  and E 3  are output, the input data indicates a −3T signal synchronized with the clock. If the enable signals E 1 , E 4  and E 3  are output, the input data indicates a −3T signal synchronized with the clock. If that the operator  618  is enabled, the operator  618  adds the delay signals D 1  and D 2  with respect to the +3T signal, and outputs the result to a comparator  620 . If the operator  619  is enabled, the operator  619  adds the delay signals D 1  and D 2  with respect to the −3T signal, and outputs the result to a comparator  621 . The comparator  620  compares the added result output from the operator  618  with a standard intermediate value (MIDSET) corresponding to the 3T level at an operational initial time of the Viterbi decoder  29 , and outputs the comparison result to an up/down counter  622 . Likewise, the comparator  621  compares the added result output from the operator  619  with the MIDSET, and outputs the comparison result to the up/down counter  622 . When a comparison result indicating that D 1 +D 2  is larger than the MIDSET is output from the comparator  620  or the comparator  621 , the up/down counter  622  performs an up-counting operation. Alternately, when a comparison result indicating that D 1 +D 2  is smaller than the MIDSET is output, the up/down counter  622  performs a down-counting operation. The count value of the up/down counter  622  is output to a comparator  623 . The comparator  623  compares the count value with an externally supplied offset value OFFSET. If the count value exceeds the offset value, a signal indicating same is output to a coefficient adjuster  624 . The coefficient adjuster  624  adjusts the filter coefficient values KC′ and KD′ of the waveform equalizer  26  if a comparison resultant signal indicating that the count value exceeds the OFFSET value is output. The up/down counter  622  in the ADTGC  28  stops a count operation and stabilizes the operation of the circuit, if a clock synchronization signal PLLOCK output from the PLL  23  indicates that data is not synchronized with the clock. 
     Meanwhile, the AGC unit  27  extracts data corresponding to a 4T level, which is a maximum value of data used in the Viterbi decoder  29  among the data input to the Viterbi decoder  29  and checks whether the level of the extracted data is appropriate to maintain the gain of the booster amplifier  20  to an appropriate value. 
     FIG. 7 shows a detailed circuit diagram of the AGC unit  27  of FIG. 2, in which delays  711 - 714  and comparators  715 - 719  extract a signal corresponding to 4T from the input PRF signal. The delays  711 - 714 , which are connected in series, delay the input PRF signal in sequence with one period of the clock signal PLCK, respectively. The comparator  715  detects a 4T level signal by using a reference signal EQRNG for detecting a 4T level. The comparator  715  generates a first enable signal E 1  when a 4T level signal is detected, which is then output to storage units  720  and  721 . Also, the comparator  718  detects a 4T level signal from the delay signal D 4 . The comparator  718  generates a third enable signal E 3  when a 4T level signal is detected, which is then output to the storage units  720  and  721 . The comparator  716  outputs, to the comparator  719 , a comparison resultant signal indicating that D 1  is smaller than D 2 . The comparator  717  outputs, to the comparator  719 , a comparison resultant signal indicating that D 2  is larger than D 3 . The comparator  719  receives the comparison resultant signals of the comparators  716  and  717  and outputs a second enable signal E 2  to the first storage device  720  only when D 1 , D 2  and D 3  are all larger than EQRNG. When D 1 , D 2  and D 3  are all smaller than EQRNG, a fourth enable signal E 4  is output to the storage device  721 . The storage devices  720  and  721  become enabled only when all of the enable signals E 1 , E 2  (or E 4 ) and E 3  are output. The storage device  720  stores a D 2  value with respect to the +4T signal and reads the stored value to output the same to a comparator  722 . If the storage device  721  is enabled, the storage device  721  stores a D 2  value with respect to the −4T signal and reads the stored value to output the read result to a comparator  723 . The comparator  722  compares D 2  of the +4T signal with an externally supplied standard maximum value MAXSET, corresponding to a 4T level at the initial time of operation in the Viterbi decoder  29 , and outputs the comparison result to an up/down counter  724 . The comparator  723  compares D 2  of the −4T signal with the MAXSET and outputs the comparison result to the up/down counter  724 . If D 2  is larger than the MAXSET, the up/down counter  724  performs an up-counting operation, and if D 2  is smaller than the MAXSET, the up/down counter  724  performs a down-counting operation. The count value of the up/down counter  724  is output to a comparator  725 . The comparator  725  compares the count value with an externally supplied offset value OFFSET. When the count value exceeds the OFFSET value, a PWM generator  726  and a gain controller  727  generate a gain control signal RFAGC for controlling a gain of the booster amplifier  20  and supply the generated result to the booster amplifier  20 . The up/down counter  724  of the AGC unit  27  also stops the counting operation and stabilizes the circuitry operation, if a clock synchronization signal PLLOCK output from the PLL  23  indicates that data is not clock-synchronized. 
     Referring back to FIG. 2, the Viterbi decoder  29  Viterbi-decodes the PRF signal and outputs the Viterbi-decoded signal as a reproduced signal VITO. 
     FIG. 8 is a block diagram showing a data reproduction apparatus for an optical disc system according to another embodiment of the present invention. The FIG. 8 apparatus includes a digital-to-analog converter (DAC)  32  for digital-to-analog conversion of the output of the ASM level generator  25  and outputting the result to the ADC  21 , instead of the adder  22  of FIG.  2 . Except for this difference, the FIG. 8 apparatus is same as the FIG. 2 apparatus. In FIG. 8, the blocks performing the same functions as those of FIG. 2 are assigned same reference numerals as those of FIG.  2 . Thus, the detailed description thereof will be omitted. The DAC  32  converts the digital ASYVAL value into an analog value and applies the result to the ADC  21  as a reference voltage. As a result, the signal output from the ADC  21  becomes the asymmetry corrected data. 
     As described above, the present invention corrects asymmetry of the RF signal to thereby improve performance of the Viterbi decoder. As a result, quality of the reproduced data can be improved.