Abstract:
The present invention relates to a tristate gate ( 1000, 2000 ) comprising an output port ( 1400 ) and at least two transistors ( 1200, 1300; 2200, 2300 ), each having at least a first and a second gate, configured such that a high-impedance value (Z) on the output port is set by controlling the threshold voltage of at least one of the transistors.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a national phase entry under 35 U.S.C. §371 of International Patent Application PCT/EP2012/075054, filed Dec. 11, 2012, designating the United States of America and published in English as International Patent Publication WO2013/087612 A1 on Jun. 20, 2013, which claims the benefit under Article 8 of the Patent Cooperation Treaty to the Europe Application Serial No. 11290575.7, filed Dec. 13, 2011, the disclosure of each of which is hereby incorporated herein in its entirety by this reference. 
     
    
     TECHNICAL FIELD 
       [0002]    The present invention relates to the field of electronics, and more in particular to the field of tristate gates. More specifically, it relates to tristate gates comprising an output port and capable of outputting a high-impedance value on the output port by controlling the tristate gate. 
       BACKGROUND 
       [0003]    Tristate gates allow their output port to assume a high impedance state in addition to the zero and one logic levels, effectively removing the effect of the output of the tristate gate from the circuit. This is useful in case when multiple circuits have to share a common medium, such as in the case of a plurality of I/O circuits driving a common bus. 
       BRIEF SUMMARY 
       [0004]    An exemplary realization of a tristate gate  3000  is illustrated in  FIG. 3A . As can be seen in the figure, tristate gate  3000  includes a NAND gate  3001 , an NOR gate  3002 , a P-type transistor  3200  and an N-type transistor  3300 . Moreover, the tristate gate  3000  has the following input and output connections: input port  3100 , output enable terminals  3700  and  3800 , output port  3400 , a power supply terminal  3500  and a ground terminal  3600 . 
         [0005]    The behavior of the tristate gate  3000  of  FIG. 3A  is explained with reference to  FIG. 3B . 
         [0006]    As can be seen in  FIG. 3B , the value of the output signal OUT on output port  3400  of tristate gate  3000  depends on the value of signals Φ and Φ B  inputted into output enable terminals  3700  and  3800 . 
         [0007]    More specifically, when the signal Φ is equal to a logic value of 0 or, more generally a low logic value represented in the table by “L,” and the signal Φ B  is equal to a logic value of 1 or, more generally, a high logic value represented in the table by “H,” the output signal OUT is equal to a high impedance value Z. This is due to the fact that the signal Φ being at a low logic value forces the NAND gate  3001  to output a high logic value independently of what the value of the signal IN is. Similarly, the Φ B  signal having a high logic value forces the output of the NOR gate  3002  to assume a low logic value independently of the value of the input signal IN. Accordingly, the P-type transistor  3200  has a high logic value on its gate while N-type transistor  3300  has a low logic value on its gate. This implies that both transistors  3200  and  3300  are closed, as indicated in the table by the keyword “OFF” in the lines Pchannel and Nchannel, and the output port  3400  is physically disconnected from both the power supply terminal  3500  and the ground terminal  3600 . In such a manner, a high-impedance value on the signal OUT can be realized, independently of the value of the input signal IN on input port  3100 . 
         [0008]    Conversely, when the signal Φ is equal to a high logic value while the signal Φ B  is equal to a low logic value, the output of both the NAND gate  3001  and NOR gate  3002  will depend on the value of the input signal IN. More specifically, if the signal IN has a low logic value, the output of NAND gate  3001  will be at a high logic value. Also, the output of NOR gate  3002  will be at a high logic value. Accordingly, the value of the OUT signal will be at a low logic value. On the other hand, when the IN signal is at a high logic value, the OUT signal will be at a high logic value. Accordingly, the OUT signal assumes the same value of the IN signal and the logic value inputted on input port  3100  is transferred to the output port  3400 . This is indicated by the keyword “switch” for the N and P transistor channels, which indicates that the state of the transistors&#39; channel will be determined according to the IN signal. 
         [0009]    The remaining combinations of values for the signal Φ and Φ B  being respectively at logic values of low and low, and high and high, produce a signal OUT on output port  3400 , which depends on the value of the signal IN on input port  3100 . The details are given in the table of  FIG. 3B , where “OFF” indicates that the respective transistor does not conduct, irrespectively of the value of the IN signal, while “switch” indicates that the transistor conducts, depending on the value of the IN signal. More specifically, for the combination of signals Φ and Φ B  being respectively low and low, the signal OUT assumes a value of low when the input signal IN has a value of low, while the signal OUT assumes a value of high impedance Z when the input signal IN has a logic value of high. Conversely, for the combination of signals Φ and Φ B  being respectively high and high, the output signal OUT assumes a value of high impedance value Z, when the input signal IN has a low logic value, while the output signal OUT assumes a high logic value when the input signal IN has a high logic value. 
         [0010]    In other words, a Pull Down (PD in the figure) can be realized for the combination Φ and Φ B  being low and low. In this condition, the output can be only pulled-down by the buffer and cannot return to the high level by itself. This is useful when multiple outputs are connected to the same signal (only one active at once) and the return to high is realized by a single and common pull-up external to the buffer. This is widely used in practice as all signals are referenced from a common ground. 
         [0011]    Symmetrically, a Pull UP (PU in the figure) can be realized for the combination Φ and Φ B  being high and high. In this condition, the output can be only pulled-up by the buffer and cannot return to the low level by itself. This is useful when multiple outputs are connected to a same signal (only one active at once) and the return to low is realized by a single and common pull-down. 
         [0012]    This is rarely used in practice as signals are referenced from power supply potentials (VDDs) that can be different from one function to the next. 
         [0013]    Such a behavior makes it possible either to transfer the value of the input port  3100  to the output port  3400  or to decouple the input port  3100  from the output port  3400  by outputting a signal OUT corresponding to a high-impedance logic value Z. 
         [0014]    Such a tristate buffer  3000  is widely employed on virtually all I/O driver. In those cases, the transistors required are usually rather large, especially when compared to the remaining “core” transistors normally used in a semi-conductor chip. Sometimes, the area destined to I/O circuitry can in fact account more than 50% of the total area of the chip. Accordingly, any reduction in the number of transistors to be used in order to realize a tristate buffer achieves a significant impact in the size and costs of a semi-conductor chip. 
         [0015]    The present invention has been realized with such an aim. More specifically, the present invention allows the realization of a tristate buffer employing a reduced number of transistors, thereby drastically reducing the area consumption due to the tristate buffer. 
         [0016]    More specifically, an embodiment of the present invention may relate to a tristate gate comprising an output port; and at least two transistors, each having at least a first and a second gate, configured such that a high-impedance value on the output port is set by controlling the threshold voltage of at least one of the transistors. 
         [0017]    Thanks to such approach, it is possible to advantageously realize a tristate buffer using a reduced number of transistors. 
         [0018]    In some embodiments, the transistors can be configured such that the high-impedance value on the output port is set by controlling the threshold voltages of the at least two transistors. 
         [0019]    Thanks to such approach, it is possible to advantageously realize a tristate buffer using a reduced number of transistors. 
         [0020]    In some embodiments, the threshold voltages of the transistors can be controlled independently of each other. 
         [0021]    Thanks to such approach, it is possible to advantageously operate the tristate gate so as to output different values on the output port. 
         [0022]    In some embodiments, the transistors can be SOI transistors. 
         [0023]    Thanks to such approach, it is possible to advantageously realize double gate transistors. 
         [0024]    In some embodiments, the threshold voltage can be controlled by means of the back gate. 
         [0025]    Thanks to such approach, it is possible to advantageously control the threshold voltage when the transistors are SOI transistors. 
         [0026]    In some embodiments, the transistors can be fully depleted SOI transistors. 
         [0027]    Thanks to such approach, it is possible to advantageously control the threshold voltage of the transistors with a higher precision and lower voltages on the back gate. 
         [0028]    In some embodiments, the transistors can be Finfet transistors. 
         [0029]    Thanks to such approach, the tristate gate can be realized without the use of SOI substrates. 
         [0030]    In some embodiments, the transistors can comprise a first transistor and a second transistor; and the first transistor can be connected between a power supply terminal and the output port and the second transistor can be connected between a ground terminal and the output port. 
         [0031]    Thanks to such approach, it is possible to advantageously connect the transistors so as to realize the tristate functionality with only two transistors. 
         [0032]    In some embodiments, the tristate gate can further comprise an input port connected to the first gate of the transistors. 
         [0033]    Thanks to such approach, it is possible to advantageously realize a digital tristate gate. 
         [0034]    In some embodiments, the tristate gate can further comprise an input port connected to the first gate of one of the transistors. 
         [0035]    Thanks to such approach, it is possible to advantageously realize an analog tristate gate. 
         [0036]    In some embodiments, the tristate gate can further comprise a control port connected to the first gate of one of the transistors different from the transistor whose first gate is connected to the input port. 
         [0037]    Thanks to such approach, it is possible to advantageously control the operation of an analog tristate gate. 
         [0038]    In some embodiments, the control port can be configured to enable or disable a signal path from the input port to the output port. 
         [0039]    Thanks to such approach, it is possible to advantageously operate an analog tristate gate so as to transmit or not the analog signal through the gate. 
         [0040]    An embodiment of the present invention may further relate to a circuit comprising a tristate gate according to any of the previous embodiments. 
         [0041]    Thanks to such approach, it is possible to advantageously integrate the tristate gate into electrical circuits. 
         [0042]    An embodiment of the present invention may further relate to a semiconductor structure, in particular, a semiconductor wafer and/or a semiconductor chip and/or a semiconductor component, implementing the circuit according to the previous embodiment. 
         [0043]    Thanks to such approach, it is possible to advantageously realize the circuit implementing a tristate gate according to the present invention. 
         [0044]    An embodiment of the present invention may further relate to a method for driving a tristate gate comprising an output port and at least two transistors, each having at least a first and a second gate, the method comprising setting a high-impedance value on the output port by controlling the threshold voltage of at least one of the transistors. 
         [0045]    Thanks to such approach, it is possible to advantageously control a tristate gate realized with a reduced number of transistors. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0046]    The invention will be described in more detail by way of example hereinafter using advantageous embodiments and with reference to the drawings. The described embodiments are only possible configurations in which the individual features may, however, as described above, be implemented independently of each other or may be omitted. Equal elements illustrated in the drawings are provided with equal reference signs. Parts of the description relating to equal elements illustrated in the different drawings may be omitted. In the drawings: 
           [0047]      FIG. 1A  illustrates a schematic drawing of a tristate buffer  1000  in accordance with an embodiment of the present invention; 
           [0048]      FIG. 1B  illustrates a schematic table resuming the operation of the tristate buffer  1000  of  FIG. 1A ; 
           [0049]      FIG. 2A  illustrates a schematic drawing of a tristate buffer  2000  in accordance with an embodiment of the present invention; 
           [0050]      FIG. 2B  illustrates a schematic table resuming the operation of the tristate buffer  2000  of  FIG. 2A ; 
           [0051]      FIG. 3A  illustrates a schematic drawing of a tristate buffer  3000  in accordance with the state of the art; 
           [0052]      FIG. 3B  illustrates a schematic table resuming the operation of the tristate buffer  3000  of  FIG. 3A ; 
       
    
    
       [0053]    As can be seen in  FIG. 1A , a tristate buffer  1000 , in accordance with an embodiment of the present invention, includes an input port  1100 , n-type transistor  1200  and p-type transistor  1300 , power supply terminal  1500 , ground terminal  1600 , output port  1400 , and output enable terminals  1700  and  1800 . 
         [0054]    More specifically, a connection is realized between the input port  1100  and the gates of both the transistors  1200  and  1300 . Transistor  1200  is a P-type SOI transistor. Transistor  1300  is an N-type SOI transistor. Transistors  1200  and  1300  may be partially depleted SOI transistors (PDSOI), or fully depleted SOI transistors (FDSOI). The drain of both transistors  1200  and  1300  is connected to the output port  1400 . The source of p-type transistor  1200  is connected to the power supply terminal  1500  while the source of n-type transistor  1300  is connected to the ground terminal  1600 . The body voltage of p-type transistor  1200  can be controlled via a back-gate bias by using output enable terminal  1800 . Similarly, the body voltage of n-type transistor  1300  can be controlled by means of output enable terminal  1700 . 
         [0055]    The two transistors  1200  and  1300  are double-gate transistors in which each gate can be controlled independently of the other. 
         [0056]      FIG. 1B  illustrates a schematic table of the behavior of the tristate gate  1000  of  FIG. 1A . 
         [0057]    As can be seen in the table, in each column the values of the signals Φ B , V THp , Pchannel, Φ, V THn  Nchannel and OUT are reported. More specifically, the signal Φ B  corresponds to the signal inputted to the output enable terminal  1800  controlling the body voltage of the p-type transistor  1200 . The signal V THp , corresponds to the absolute value of the threshold voltage of the p-type transistor  1200  and is a function of the back-gate bias voltage Φ B . The signal Pchannel indicates the status of the channel of P transistor  1200  with respect to the switching of the IN signal on port  1100 . The signal Φ corresponds to the signal inputted to the output enable terminal  1700  controlling the body voltage of the n-type transistor  1300 . The signal V THn , corresponds to the absolute value of the threshold voltage of the n-type transistor  1300  and is a function of the back-gate bias voltage Φ. The signal Nchannel indicates the status of the channel of N transistor  1300  with respect to the switching of the IN signal on port  1100 . The signal OUT correspond to the signal on the output port  1400 . 
         [0058]    For each of the input signals among the above-mentioned signals, a value is given among “H,” “L,” “SC,” “Z,” and “I  N ,” “Very L” and “Very H.” More specifically, the signal value “H” corresponds to a high logic value, the signal value “L” corresponds to a low logic value. Similarly, the signal value “Very H” corresponds to a very high logic value, enough for turning the P transistor  1200  in depletion mode, while the signal value “Very L” corresponds to a very low logic value, enough for turning the N transistor  1200  in depletion mode. The signal value “Z” corresponds to a high-impedance signal. The signals value “I  N ” corresponds to the inverted logic signal input on input port  1100 . The signal value “SC” corresponds to a signal resulting from the short circuit between the power supply terminal  1500  and the ground terminal  1600  via transistors  1200  and  1300 . For instance, assuming that the series resistance of the transistors  1200  and  1300  is the same, the voltage value corresponding to the signal “SC” will be half of the difference between the voltage of the power supply terminal  1500  and the voltage of the ground terminal  1600 . 
         [0059]    In this context, the values “H” and “L” are to be interpreted as respectively “high enough” and “low enough” to modify the value of the threshold voltage of the transistors  1200  and  1300  in such a way that the behavior of the transistors  1200  and  1300  is dictated by the application of the back-gate bias to the body. In other words, for instance, if the signal Φ has a high voltage value “H,” then the threshold voltage of the n-type transistor  1300  V THn  will be lowered and the transistor will be conducting or not depending on the value of the signal IN applied to the gate terminal of transistor  1300 , as indicated by the keyword “switch.” Symmetrically, for instance, if the signal Φ has a low voltage value “L,” then the threshold voltage of the n-type transistor  1300  V THn  will be increased and the transistor will be open, i.e., not conducting, independently of the value of the signal IN applied to the gate terminal of transistor  1300 , as indicated by the keyword “OFF.” 
         [0060]    Furthermore, the following signal values are given to the signals V THp  and V THn : “high” and “low.” More specifically, the signal value corresponding to “high” signifies a high-voltage value while the voltage value corresponding to the signal “low” corresponds to a low voltage value. In this context, the terms “high” and “low” are to be interpreted as respectively “high enough” and “low enough” make the transistors  1200  and  1300  behave on the basis of the voltage value on the back gate. For instance, if the signal Φ B  has a low voltage value “L,” then the threshold voltage of the p-type transistor  1200  V THp  will be lowered and the transistor will be conducting or not depending on the value of the signal IN applied to the gate terminal of transistor  1200 , as indicated by the keyword “switch.” Symmetrically, for instance, if the signal Φ B  has a high voltage value “H,” then the threshold voltage of the p-type transistor  1200  V THp  will be increased and the transistor will be open, i.e., not conducting, independently of the value of the signal IN applied to the gate terminal of transistor  1200 , as indicated by the keyword “OFF.” 
         [0061]    It is to be noted that the signals V THp  and V THn  are intended as absolute values. Accordingly, when the threshold voltage is indicated as having a low value for the n-type transistor  1300 , this implies that the transistor  1300  is closed at a lower gate terminal voltage with respect to the case in which the threshold voltage is indicated as having a high value. Similarly, when the threshold voltage V THp  of p-type transistor  1200  is indicated as being low, this implies that the p-type transistor  1200  is closed (i.e., conducting), at a higher gate terminal voltage with respect to the case in which the threshold voltage is indicated as having a high value. 
         [0062]    In general, the above-mentioned behavior can be obtained by opening, i.e., setting in a non-conducting state, any of the transistors by setting its threshold voltage over VDD when the back gate is at an appropriate level. This case is indicated by the keyword “OFF” in the Figures. 
         [0063]    For instance, on Nchannel, setting the voltage Φ at Ov increases the threshold voltage to a value that can be chosen at 0.8 v-1.0 v. With a VDD of 0.6-0.7V, this implies that the transistor cannot be made conducting, independently on what logic value is applied on the gate. On the other hand, applying a high voltage “H” on signal Φ will lower the threshold voltage in the range of 0.3V. With the same VDD at 0.6 v-0.7 v, the transistor that can be turned in a conducting or non-conducting state according to the top gate logic value, as in usual enhancement transistors. The same applies on the P transistor by symmetry. 
         [0064]    The above numerical values are an example only and the present invention is not limited thereto. The voltage amplitude on the back gate that makes the transistor acts, as described above, depends on technological parameters such as, but not limited to, thicknesses of Silicon film, top gate and back gate. In general, the back gate voltage can be in the range of VDD, or a little more on Fully Depleted SOI technology. 
         [0065]    As can be seen from the table of  FIG. 1B , due to the different possible combinations of the various input signals, the output signal OUT can assume different values. 
         [0066]    In particular, columns  1010  and  1011  result, respectively, in a Pull Up “PU” and Pull Down “PD” case. Column  1030  results in the output being the negated version of the Input signal IN. Column  1020  results in the output being at a high impedance value “Z.” Columns  1040 ,  1041  and  1042  may result in a Short Circuit “SC,” in some cases also depending on the input on signal IN. Therefore, depending on the application, these combinations of signals may be forbidden. 
         [0067]    As can be seen in the table, with the configuration of signals given in column  1020 , the output signal OUT assumes a high-impedance value “Z” irrespective of the value of the input signal IN on input port  1100 . More specifically, the combination that provides such an effect consists of having a high voltage level “H” for the signal Φ B  and a low voltage level “L” for the signal Φ. In fact, the high voltage level for the signal Φ B  has the effect of increasing the absolute value of the threshold voltage V THp  of p-type transistor  1200  to a high level “high.” While the low value “L” for the signal Φ has the effect of increasing the absolute value of the threshold voltage V THn  of n-type transistor  1300  to a high level “high.” Accordingly, since both the threshold voltage of transistor  1200  and of transistor  1300  are increased to such a value “high” where the transistors are open, i.e., non-conducting, irrespective of the value of the input signal IN, the output signal OUT on output port  1400  is disconnected from both, the power supply tem - final  1500  and the ground terminal  1600 , irrespective of the value of the input signal IN on input port  1100 . In such a manner, a reliable high-impedance value can be achieved on output port  1400  by using only the back-gate bias of the body terminals of transistors  1200  and  1300 . 
         [0068]    On the other hand, when the values of the signals Φ B  and Φ are respectively set to “L” and “H” such that the transistors operate according to the gate terminal voltage, as indicated by the keyword “switch,” such as in column  1030 , the tristate gate  1000  acts as an inverter and the output signal OUT corresponds to the logic inversion of the input signal IN. 
         [0069]    The Pull Up “PU” of column  1010  can be realized for the combination Φ B  and Φ being respectively at “L” and “L.” In this condition, the output can be only pulled-up by tristate gate  1000  and cannot return to the low level by itself, unless the values of signals Φ B  and Φ are changed. In this case, for instance, the return to a low value on the OUT signal can be realized by a single and common pull-down external to the buffer such as, for instance, a resistor. 
         [0070]    Symmetrically, the Pull Down “PD” of column  1011  can be realized for the combination Φ B  and Φ being respectively at “H” and “H.” In this condition, the output can be only pulled-down by tristate gate  1000  and cannot return to the high level by itself, unless the values of signals Φ B  and Φ are changed. In this case, for instance, the return to a high value on the OUT signal can be realized by a single and common pull-up external to the buffer such as, for instance, a resistor. 
         [0071]    As can be seen in  FIG. 2A , a tristate buffer  2000  in accordance with a further embodiment of the present invention includes an input port  2100 , a control port  2900 , n-type transistor  2200  and p-type transistor  2300 , power supply tell final  1500 , ground terminal  1600 , output port  1400 , and output enable terminals  1700  and  1800 . 
         [0072]    More specifically, a connection is realized between the input port  2100  and the gate of the n-type transistor  2300 . The remaining connections are similar to the corresponding connections in  FIG. 1A . 
         [0073]      FIG. 2B  illustrates a schematic table of the behavior of the tristate gate  2000  of  FIG. 2A . 
       DETAILED DESCRIPTION 
       [0074]    The meaning of the signal values in the table are similar to those of table of  FIG. 1B . In addition, the table of  FIG. 2A  includes a row for the value of the control signal CTRL. For ease of representation, the control signal CTRL has been assigned both low logic value “0” and high logic value “1” in each column. When the behavior of the gate is different, depending on whether the CTRL signal is at “0” or “1,” this is indicated in each column by providing more than one value, respectively, corresponding to CTRL being at “0” or “1.” For instance, in column  2010 , if CTRL is “0,” then P transistor  2200  is made conducting as indicated by “switch on” or non-conducting as indicated by “switch off” in line “Pchannel.” This results in OUT signal having a respective Pull Up value “PU,” when CTRL is set at “0” value, or high impedance “Z,” when CTRL is set at “1.” 
         [0075]    As can be seen, thanks to the configuration of tristate gate  2000 , the gate acts as an analog tristate gate. 
         [0076]    In particular, as indicated in column  2030 , the tristate function can be implemented by setting signals Φ B  and Φ at “H” and “L” values, respectively. In this case, the values of signals Φ B  and Φ force both the P and N transistor to be always “OFF,” i.e., non-conducting, independently on the value of the CTRL signal or the IN signal. 
         [0077]    Columns  2040 ,  2041  and  2042  may result in a Short Circuit “SC,” in some cases also depending on the input on signal IN. Similarly, the signal combination of column  2021 , when CTRL is set at “0” also results in a short circuit. The signal combinations corresponding to these columns can, therefore, be forbidden, depending on the applications. 
         [0078]    Colum  2021  when CTRL is set at “1” can be used in order to implement a Pull Down “PD” on the output. Similarly, column  2020  can be used in order to implement a Pull Down “PD” function. 
         [0079]    Accordingly, the tristate gate  2000  can act as an analog tristate port, with a reduced number of transistors. 
         [0080]    Furthermore, although tristate gates  1000  and  2000  have been described with respect to SOI technology for the transistors  2200  and  2300 , the present invention is not limited to SOI technology. Alternatively, the two transistors could be realized with any technology that provides control of the body voltage of the transistor by more than one independent gate, such as independent double-gate or triple-gate, or multiple-gate transistors. For instance, in the case of double-gate technology, one of the gates could be connected as the front gate of transistors  1200 ,  2200 ,  1300  and  2300 , while the other gate could be connected as the back gate of transistors  1200 ,  2200 ,  1300  and  2300 . 
         [0081]    Alternatively, or in addition, the invention could also be implemented by using finfets, with at least two independent gates, for some or all of the transistors. In this case, one of the two gates could act as a top gate or front gate, as described above, while the other gate could act as a bottom gate or back gate, as described above. 
         [0082]    All previously discussed embodiments are not intended as limitations but serve as examples illustrating features and advantages of the invention. It is to be understood that some or all of the above-described features can also be combined in different ways.