Abstract:
We describe and claim a delay locked loop harmonic detector and associated method. A delay locked loop includes a detection circuit to generate a detection signal responsive to an input clock and a control circuit to synchronize the delay locked loop to a fundamental of the input clock responsive to the detection signal. A method includes detecting harmonic synchronization in a delay locked loop responsive to an input clock and locking the delay locked loop to a fundamental of the input clock responsive to the detecting.

Description:
FIELD 
   This application relates to a Delay Locked Loop (DLL) harmonic detector and associated method. 
   BACKGROUND 
   DLLs are advanced clock management circuits employed in systems supporting high bandwidth transfer rates. DLLs allow for precise synchronization of external and internal clocks. More particularly, DLLs generate internal clocks with a known phase relationship to an external input clock. 
   Low Voltage Differential Signaling (LVDS) receivers and transmitters often employ DLLs to generate multiple internal clocks having phases with a known relationship to the external input clock. A DLL typically consists of a chain of variable delay elements. When properly adjusted, the sum of all the delays in the delay elements equals the external clock&#39;s period. When this occurs, the DLL is said to be locked to the external clock. In some circumstances, however, the DLL locks to a multiple of the clock period (e.g., two or three times the clock period) resulting in erroneous operation. 
   Accordingly, a need remains for an improved DLL harmonic detector and associated method. 

   
     BRIEF DRAWINGS DESCRIPTION 
     We describe embodiments of this application referencing the following drawings. 
       FIG. 1  is a block diagram of display system. 
       FIG. 2  is a block diagram of an embodiment of the LVDS receiver shown in  FIG. 1 . 
       FIG. 3  is a block diagram of an embodiment of the clock channel shown in  FIG. 2 . 
       FIG. 4  is a block diagram of an embodiment of the detection circuit shown in  FIG. 3 . 
     FIGS.  5  and  6 A–E are timing diagrams illustrating exemplary operation of the DLL shown in  FIGS. 2–4 . 
   

   DETAILED DESCRIPTION 
     FIG. 1  is a block diagram of a display system  100 . Referring to  FIG. 1 , the system  100  includes a receiver  120  for receiving an analog image data signal  110 , e.g., RGB or YP B P R  signal, from a source  102 . The source  102  may be a personal computer  107 , a digital video disk player  105 , set top box (STB)  103 , or any other device capable of generating the analog image data signal  110 . The receiver  120  may be an analog-to-digital converter (ADC) or any other device capable of generating digital video signal  109  from the analog image data  110 . The receiver  120  converts the analog image data signal  110  into the digital image data  109  and provides it to a controller  150 . A person of reasonable skill in the art knows well the design and operation of the source  102  and the receiver  120 . 
   Likewise, a video receiver or decoder  122  decodes an analog video signal  112  from a video source  104 . The video source  104  may be a video camcorder, tape player, digital video disk (DVD) player, or any other device capable of generating the analog video signal  112 . The video source  104  may read (or play) external media  101 . In an embodiment, a DVD player  104  plays the DVD  101 . In another embodiment, a VHS tape player  104  plays a VHS tape  101 . The decoder  122  converts the analog video signal  112  into the digital video signal  109  and provides it to the display controller  150 . The decoder is any device capable of generating digital video signal  109 , e.g., in Y/C or CVBS format, from the analog video signal  112 . A person of reasonable skill in the art knows well the design and operation of the video source  104  and the video decoder  112 . 
   A modem or network interface card (NIC)  124  receives data  114  from a global computer network  106  such as the Internet®. The data  114  may be in any format capable of transmission over the network  106 . In an embodiment, the data  114  is packetized digital data. But the data  114  may also be in an analog form. Likewise, the modem  124  may be a digital or analog modem or any device capable of receiving and/or decoding data  114  from a network  106 . The modem  124  provides digital video signal  109  to the display controller  150 . A person of reasonable skill in the art knows well the design and operation of the network  106  and the modem/NIC  124 . 
   A Digital Visual Interface (DVI) or high definition multimedia interface (HDMI) receiver  126  receives digital signals  116  from a digital source  108 . In an embodiment, the source  108  provides digital RGB signals  116  to the receiver  126 . The receiver  126  provides digital video signal  109  to the display controller  150 . A person of reasonable skill in the art knows well the design and operation of the source  108  and the receiver  126 . 
   A tuner  128  receives a wireless signal  118  transmitted by the antenna  119 . The antenna  119  is any device capable of wirelessly transmitting or broadcasting the signal  118  to the tuner  128 . In an embodiment, the antenna  119  transmits a television signal  118  to the television tuner  128 . The tuner  128  may be any device capable of receiving a signal  118  transmitted wirelessly by any other device, e.g., the antenna  119 , and of generating the digital video signal  109  from the wireless signal  118 . The tuner  128  provides the digital video signal  109  to the controller  150 . A person of reasonable skill in the art knows well the design and operation of the antenna  119  and the tuner  128 . 
   The digital video signal  109  may be in a variety of formats, including composite or component video. Composite video describes a signal in which luminance, chrominance, and synchronization information are multiplexed in the frequency, time, and amplitude domain for single wire transmission. Component video, on the other hand, describes a system in which a color picture is represented by a number of video signals, each of which carries a component of the total video information. In a component video device, the component video signals may be processed separately and, ideally, encoding into a composite video signal occurs only once, prior to transmission. The digital video signal  109  may be a stream of digital numbers describing a continuous analog video waveform in either composite or component form.  FIG. 1  describes a variety of devices (and manners) in which the digital video signal  109  may be generated from an analog video signal or other sources. A person of reasonable skill in the art should recognize other devices for generating the digital video signal  109  come within the scope of the application. 
   In  FIG. 1 , the controller  150  is shown as receiving the digital video signal  109 . Alternatively, the controller  150  may receive an analog signal, e.g., analog image data signal  110  from the video  103 , DVD  105 , and/or computer  107 . In the later case, the controller  150  may include means for receiving and converting the analog signal into the digital signal  109 , e.g., ADC receiver  120  or video decoder  122 . 
   The controller  150  may generate image data  132  and control signals  133  by manipulating the digital video signal  109  or any other signal it receives at its input. The display controller  150  provides the image data  132  and control signals  133  to a display  160  in any of a variety of manners. In an embodiment, the display  160  is a television either analog (e.g., Cathode Ray Tube (CRT)), digital (e.g., High Definition Television (HDTV)), or otherwise. The display  160  may be digital with a fixed pixel structure, e.g., active and passive LCD displays, plasma displays (PDP), field emissive displays (FED), electro-luminescent (EL) displays, micro-mirror technology displays, low temperature polysilicon (LTPS) displays, and the like. The display  160  may be other than a digital display, e.g., an analog display such as a CRT as used in monitors, projectors, personal digital assistants, and other like applications. 
   In an embodiment, the controller  150  may scale the digital video signal  109  for display using a variety of techniques including pixel replication, spatial and temporal interpolation, digital signal filtering and processing, and the like. In another embodiment, the controller  150  may additionally change the resolution of the digital video signal  109 , changing the frame rate and/or pixel rate encoded in the digital video signal  109 . We will not discuss scaling, resolution, frame, and/or pixel rate conversion, and/or color manipulation in any further detail. A person of reasonable skill in the art should recognize that the controller  150  may manipulate the video signal  109  and provides the image data  132  and control signals  133  to the display  160  such that it is capable of properly displaying a high quality image regardless of display type. 
   Read-only (ROM) and random access (RAM) memories  140  and  142 , respectively, are coupled to the display system controller  150  and store bitmaps, FIR filter coefficients, and the like. A person of reasonable skill in the art should recognize that the ROM and RAM memories  140  and  142 , respectively, may be of any type or size depending on the application, cost, and other system constraints. A person of reasonable skill in the art should recognize that the ROM and RAM memories  140  and  142 , respectively, are optional in the system  100 . A person of reasonable skill in the art should recognize that the ROM and RAM memories  140  and  142 , respectively, may be external or internal to the controller  150 . RAM memory  142  may be a flash type memory device. Clock  144  controls timing associated with various operations of the controller  150 . 
   The controller  150  may include a transmitter  170  to transmit the data and control signals  132  and  133 , respectively. And the panel  160  may include a receiver  180  to receive the data and control signals  132  and  133 , respectively. In an embodiment, the transmitter  170  and receiver  180  are Low Voltage Differential Signal (LVDS) devices. Low voltage differential signaling uses high-speed analog circuit techniques to provide multi-gigabit data transfers on copper interconnects. LVDS signaling is a well-known interface standard for high speed data transmission described in part in the American National Standards Institute (ANSI)/Telecommunications Industry Association (TIA)/Electronic Industries Alliance (EIA)—644-1995 standard and other like documents. 
     FIG. 2  is a block diagram of an embodiment of the LVDS receiver  180 .  FIG. 3  is a block diagram of an embodiment of the clock channel  214  shown in  FIG. 2 . Referring to  FIGS. 2 and 3 , in an embodiment, the LVDS receiver  180  is adapted to receive high speed, serialized, differential LVDS data  132  and control  133  at its inputs and present de-serialized data and control at its outputs. The LVDS receiver  180  may receive the data  132  from the LVDS transmitter  170 . The LVDS receiver  180  may include a supply circuit  202 . The supply circuit  202  may include a voltage regulator  204  to generate an internal voltage supply, e.g., 1.8V, from the external voltage supply, e.g., 2.5V–3.3V. The voltage regulator  202  may be linear and include bypass capacitors (not shown). And the supply circuit  202  may include a bias generator  206  to generate a bias voltage when necessary. 
   The LVDS receiver  180  may include a plurality of clock and data channels. In an embodiment, the LVDS receiver  180  includes two input channels  210  and  220 , one each for odd and even data. Each input channel  210  may include four data channels  212 A–D and a clock channel  214 . 
   Referring to  FIGS. 2 and 3 , in an embodiment, the clock channel  214  may include a differential receiver  302 , an inversion circuit  304 , a programmable delay  306 , and a DLL  300 . The differential receiver  302  converts the input differential LVDS clock signal to a single-ended clock. The differential receiver  302  may operate off the external voltage supply, e.g., 2.5–3.3V. The differential receiver  302  may include standard analog input pads that protect against an electrostatic discharge event. The inversion circuit  304  inverts the clock output from the differential receiver  302  responsive to an invert clock control signal. The programmable delay  306  delays the clock signal responsive to delay clock control signals. We will not further discuss the design and operation of the differential receiver  302 , inversion circuit  304 , and programmable delay  306  as these circuits are well known. 
   In an embodiment, the DLL  300  includes phase generator  320 , control circuit  310 , and detection circuit  330 . The phase generator  320  generates a multiphase clock from the input clock CLK. In an embodiment, the phase generator generates a fourteen phase clock P 0 –P 13   [ryg1]  although only the odd clock phases may be used to capture data bits on both odd and even channels. This is because the even clock phases typically transition when the data is changing or transitioning. The odd clock phases, on the other hand, transition in the middle of each data bit window, when the data is stable. The data channel, e.g.,  212 A–D, uses the multiphase clock to capture and de-serialize the input data  132 . The control circuit  310  generates the control signals necessary for the DLL  300  to generate the multiphase clock P 0 –P 13  responsive to the input clock CLK. The control circuit  310  may, for example, generate synchronization signals for the DLL  300  to lock to a fundamental of the input clock. And the control circuit  310  may generate a clock present signal LOCK to detect the presence of the input clock CLK. 
     FIG. 4  is a block diagram of an embodiment of the detection circuit  330  shown in  FIG. 3 . Referring to  FIG. 4 , the detection circuit  330  generates a detection signal DLL_gofast responsive to the input clock, i.e., phase P 0 . Note that phase P 0  is coincident with the input clock CLK. The detection circuit  330  includes a first counter circuit  332 . The first counter circuit  332  includes a first counter  333  to generate a first count ctr 1 (8:0) responsive to input clock P 0 . In an embodiment, the first counter circuit  332  counts a predetermined number of input clock periods, e.g., 512 clock periods. In an embodiment, the predetermined number of input clock periods is longer than the DLL lock time to prevent false triggers when a clock is initially connected. A flip flop  335  generates the measurement enable signal, labeled meas_en in  FIG. 4 , by logically manipulating the first count ctr 1 (8:0) with the input clock P 0 . In an embodiment, the flip flop  335  is a D flip flop. The flip flop  335  provides the measurement enable signal meas_en to a state machine  334 . 
   The state machine  334  determines whether the DLL is locked properly to the input clock P 0 . If not, the state machine  334  generates the detection signal DLL_gofast that it provides to the control circuit  310  ( FIG. 3 ). The control circuit  310 , in turn, speeds up the DLL  300  to its minimum delay state and then releases the DLL so that it gradually slows down and locks to an input clock&#39;s fundamental. 
   In an embodiment, the state machine  334  asynchronously determines the presence of a predetermined number of states, e.g., state  1 , state  2 , and state  3 . If these states are present in order and in a single input clock period, the detection circuit  330  determines the DLL is locked properly to a fundamental of the input clock and the state machine  334  generates a no error signal noerrq. The state machine  334  provides the no error signal noerrq to a second counter circuit  336 . 
   If, however, the state machine  334  does not detect the presence of the predetermined number of states, e.g., state  1 , state  2 , and state  3 , in order and in a single input clock period, the detection circuit  330  determines the DLL is locked improperly to a harmonic of the input clock. In this later case, the state machine  334  generates an error signal errq that it provides to the second counter circuit  336 . 
   In an embodiment, the state machine  334  uses any number of predetermined states. And the predetermined states may be selected to simplify the state machine&#39;s timing. In an embodiment, the predetermined states are spaced at least two clock phases apart, e.g., P 2 , P 5 , and P 9 , to relax timing requirements and allow for slower timing paths than would be required if the states were spaced closer together. 
   The second counter circuit  336  includes a second counter  337  to generate a second count ctr 2 (1:0) responsive to the error and no error signals errq and noerrq, respectively, and responsive to the input clock P 0 . The second counter  337  provides the second count signal ctr 2 (1:0) to a logic circuit  339  that logically manipulates the second count signal ctr 2  with the first count signal ctr 1 . The second counter circuit  337  generates the detection signal DLL_gofast when a number of consecutive error signals errq, e.g., 3, occur. 
   FIGS.  5  and  6 A–E are timing diagrams illustrating exemplary operation of the DLL  300  shown in  FIGS. 3–4 .  FIG. 5  illustrates the DLL  300 &#39;s operation when it locks properly to a fundamental of the input clock. After the measurement enable signal meas_en goes high responsive to a low to high transition of the input clock at  1 , state  1  goes high responsive to a low to high transition of input clock phase P 2  at  2 . State  2  goes high responsive to a low to high transition of input clock phase P 5  at  3 . And state  3  goes high responsive to a low to high transition of input clock phase P 9  at  4 . States  1 ,  2 , and  3  are therefore present in sequence and within a single clock period ending at  5 . The DLL  300  is properly locked to a principal of the input clock as indicated by state  3  being high at the next low to high transition of the input clock at  5   [ryg2] . 
   Referring to  FIG. 6A , states  1 ,  2 , and  3  go high at  2 ,  3 , and  4 , respectively, responsive to a low to high transition of the input clock at  1 . Because all three states are present sequentially before the next low to high transition of the input clock at  5 , the DLL  300  is properly locked to a harmonic of the input clock [ryg3] . 
   Referring to  FIG. 6B , only states  1  and  2  go high at  2  and  3 , respectively, responsive to a low to high transition of the input clock at  1 . State  3  (low to high transition of phase P 9 ) goes high after the low to high transition of the input clock at  5 . This indicates that the DLL  300  is improperly locked to a second harmonic of the input clock. The detection circuit may generate the detection signal DLL_gofast in this example. 
   Referring to  FIG. 6C , only state  1  goes high at  2  responsive to a low to high transition of the input clock at  1 . State  2  (low to high transition of phase P 5 ) goes high after the low to high transition of the input clock at  5 . State  3  (low to high transition of phase P 9 ) goes high before the low to high transition of the input clock at  5  but does not follow state  2 . Since all three states are not present sequentially within a single input clock period, the DLL  300  is improperly locked to a third harmonic of the input clock. The detection circuit may generate the detection signal DLL_gofast in this example. 
   Referring to  FIG. 6D , only state  1  goes high at  2  responsive to a low to high transition of the input clock at  1 . States  2  and  3  (low to high transitions of phases P 5  and P 9 ) go high at after the low to high transition of the input clock at  5 . But state  2  is present before state  1 , thus, the DLL  300  is improperly locked to a fourth harmonic of the input clock. The detection circuit may generate the detection signal DLL_gofast in this example. 
   Referring to  FIG. 6E , state  1  goes high at  2  responsive to a low to high transition of the input clock at  1 . State  2  (low to high transition of phase P 5 ) goes high after state  1 . State  3  (low to high transition of phase P 9 ), however, goes high before states  1  and  2  are present. The DLL  300  is improperly locked to a fifth harmonic of the input clock. The detection circuit may generate the detection signal DLL_gofast in this example. 
   I have illustrated and described the principles of this application by way of illustrative and not restrictive examples. Those of skill in the art will recognize certain modifications, permutations, additions, and sub-combinations to the exemplary embodiments I describe above. I intend that the following claims and those claims I introduce later be interpreted to include all such modifications, permutations, additions, sub-combinations as are within the spirit and scope.