Abstract:
The Ge channel device comprises: a Ge channel layer ( 2 ); a Si-containing interface layer ( 4 ) formed on the Ge channel layer ( 2 ); a La 2 O 3  layer ( 6 ) formed on the interface layer ( 4 ); and an electrically conductive layer ( 8 ) formed on the La 2 O 3  layer ( 6 ). In this device, the Si-containing interface layer ( 4 ) functions to suppress the diffusion of Ge atoms into the La 2 O 3  layer ( 6 ) and thereby prevents the formation of Ge oxide in the La 2 O 3  layer ( 6 ); accordingly, a Ge channel device whose C-V characteristic exhibits only a small hysteresis can be achieved.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority of Japanese Patent Application No. 2007-221605, filed on Aug. 28, 2007. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor device using Ge as a channel material and a method for fabricating such a device, and more particularly to a Ge channel device using La 2 O 3  as a gate insulating film material and a method for fabricating such a device. 
         [0004]    2. Prior Art 
         [0005]    The need for higher-speed and lower-power consumption LSIs (large-scale integrated circuits) has been growing more than ever before. To increase the operating speed of LSIs that use Si as a channel material, a lot of effort has been expended to miniaturize MOS devices that form the basic elements of LSIs. As a result of such effort, the gate length of MOS devices has now been reduced to several tens of nanometers, almost reaching the limit of miniaturization. In view of this, to develop LSIs capable of higher speed operation, research is currently directed toward using a Ge semiconductor to replace a Si semiconductor as the channel material. The reason is that, compared with Si, Ge has excellent electronic properties, in particular, high carrier mobility. The higher the carrier mobility, the faster the LSI can function. 
         [0006]    However, Ge has a drawback that its oxides are chemically and thermodynamically unstable, and as a result, it is difficult to stably protect the surface of a Ge substrate. For this reason, not much progress has been made in the development of LSIs using Ge substrates. However in recent years, various kinds of dielectrics that can stably protect the Ge substrate surface have been found, and LSIs using Ge substrates have been drawing attention because of their future potential (for example, refer to Japanese Unexamined Patent Publication No. 2005-191293). 
         [0007]    Noting that La 2 O 3  has high permittivity and its bandgap is larger than other dielectric materials, the present inventors have been working on fabricating Ge channel devices using La 2 O 3  as a gate insulating film material. 
         [0008]      FIG. 1  shows the structure of a Ge-MOS capacitor  100  as one example of such a device. In the figure, reference numeral  102  is a Ge semiconductor substrate for forming a Ge channel,  104  is a La 2 O 3  layer formed, for example, by electron-beam evaporation on the Ge semiconductor substrate  102 , and  106  is an electrode layer formed by depositing a metal such as Pt or W on the La 2 O 3  layer  104 , for example, by electron-beam evaporation. Here, the La 2 O 3  layer forms a gate insulating film. 
         [0009]    After the fabrication, the C-V characteristic of the Ge-MOS capacitor  100  having the structure shown in  FIG. 1  was measured in order to evaluate its electrical characteristic. However, it was found that the C-V characteristic exhibited appreciable hysteresis (refer to  FIG. 4  to be described later), which would present a serious problem when forming a switching device such as a transistor. To identify the cause, the photoelectron spectrum of the capacitor  100  was measured, and the result showed a peak peculiar to Ge oxide (especially, suboxide); it was thus found that Ge oxide was grown in the capacitor  100  of the structure shown in  FIG. 1 . 
         [0010]    In practice, before depositing La 2 O 3  on a Ge substrate, the Ge substrate is cleaned and any Ge oxide formed on the surface of the Ge substrate is removed, for example, by heating; therefore, no peaks associated with Ge oxide should normally appear in the photoelectron spectrum. Accordingly, the peak appearing in the photoelectron spectrum was presumably due to the Ge oxide grown during the fabrication of the capacitor  100 . That is, it is presumed that, during the heating step in the fabrication process of the capacitor  100 , Ge atoms in the Ge substrate were diffused into the La 2 O 3  layer where the Ge atoms combined with oxygen contained in the La 2 O 3  layer, resulting in the formation of the Ge oxide. 
         [0011]    Accordingly, to achieve a Ge channel device whose C-V characteristic exhibits only a small hysteresis, it is essential to develop a novel structure and a novel fabrication method for suppressing the diffusion of Ge into the La 2 O 3  layer during the heating step and thereby preventing the formation of Ge oxide in the La 2 O 3  layer. 
       SUMMARY OF THE INVENTION 
       [0012]    In view of the foregoing, it is an object of the present invention to achieve a Ge channel device having a novel structure that can effectively prevent the Ge atoms contained in the substrate from diffusing into the La 2 O 3  layer during the heating step in the fabrication process of the Ge channel device, and to provide a method for fabricating a device having such a structure. 
         [0013]    A Ge channel device that achieves the above object comprises: a Ge channel layer; a Si-containing interface layer formed on the Ge channel layer; a La 2 O 3  layer formed on the interface layer; and an electrically conductive layer formed on the La 2 O 3  layer. 
         [0014]    In the above Ge channel device, the Si-containing interface layer may be formed to have a layer thickness of 0.5 to 2 nm. 
         [0015]    In the above Ge channel device, the Si-containing interface layer may contain either Si or silicate or La-silicate or may contain all of them. 
         [0016]    In the above Ge channel device, in order to operate the device as a MOS capacitor, a second electrically conductive layer may be formed on a surface of the Ge channel layer opposite to the surface thereof on which the interface layer is formed. 
         [0017]    In the above Ge channel device, the Ge channel layer may contain source and drain regions. 
         [0018]    A method for fabricating a Ge channel device, which achieves the above object, comprises the steps of: forming a Si-containing interface layer on a channel layer of Ge; forming a gate insulating film of La 2 O 3  on the interface layer; and forming an electrically conductive material layer on the gate insulating film. 
         [0019]    In the above method, the step of forming the interface layer may be accomplished by depositing Si on the channel layer by electron-beam evaporation. 
         [0020]    In the above method, the interface layer may be formed to have a layer thickness of 0.5 to 2 nm. 
         [0021]    The above method may further includes the step of heat-treating the channel layer after forming the electrically conductive material layer. 
         [0022]    In the above method, the step of forming the Si-containing interface layer on the channel layer of Ge may be carried out after removing a Ge oxide film grown on a surface of the channel layer on which the interface layer is to be formed. 
       EFFECT OF THE INVENTION 
       [0023]    According to the Ge channel device and its fabrication method of the invention, the interface layer containing Si is interposed between the Ge channel layer and the La 2 O 3  layer. Therefore, the Si interface layer functions to prevent Ge contained in the Ge channel layer from being thermally diffused during the heat treating step, and Ge atoms are thus prevented from moving into the La 2 O 3  layer. In this way, the formation of Ge oxide in the La 2 O 3  layer is suppressed, achieving a Ge channel device having an excellent electrical characteristic by greatly reducing the hysteresis in the C-V characteristic. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]      FIG. 1  is a diagram showing the structure of a prior art Ge channel device having a dielectric layer formed from La 2 O 3 . 
           [0025]      FIG. 2(   a ) is a diagram showing a step in a Ge channel device fabrication process according to one embodiment of the present invention. 
           [0026]      FIG. 2(   b ) is a diagram showing a step that follows the step shown in  FIG. 2(   a ). 
           [0027]      FIG. 2(   c ) is a diagram showing a step that follows the step shown in  FIG. 2(   b ). 
           [0028]      FIG. 2(   d ) is a diagram showing a step that follows the step shown in  FIG. 2(   c ). 
           [0029]      FIG. 3  is a diagram showing the photoelectron spectrum of the Ge channel device fabricated by the process shown in  FIGS. 2(   a ) to  2 ( d ). 
           [0030]      FIG. 4  is a diagram showing the C-V characteristic of the Ge channel device fabricated by the process shown in  FIG. 2 . 
           [0031]      FIG. 5  is a diagram showing the structure of a Ge capacitor device that can be fabricated using the process shown in  FIGS. 2(   a ) to  2 ( d ). 
           [0032]      FIG. 6  is a diagram showing the structure of a Ge-MOS transistor that can be fabricated using the process shown in  FIG. 2 . 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0033]    The present inventors have discovered that diffusion of Ge and the growth of a suboxide can be suppressed by interposing an Si layer between La 2 O 3  and a Ge semiconductor substrate. In the case of a semiconductor substrate formed from Si, the growth of suboxide is reduced compared with the case of the Ge substrate; rather, it tends to form La-silicate, and the hysteresis in the C-V characteristic of the resulting semiconductor substrate is also reduced. In view of this, the present inventors considered suppressing the diffusion of Ge and the growth of suboxide by interposing an Si layer between the Ge semiconductor substrate and the La 2 O 3  layer that forms the gate insulating film, and fabricated the Ge channel device of the present invention as will be described hereinafter. 
         [0034]      FIGS. 2(   a ) to  2 ( d ) are diagrams showing the process steps for fabricating the Ge channel device according to the present invention. In  FIG. 1  and subsequent figures, the thicknesses of the respective layers are exaggerated, and the thickness ratio shown in each figure does not represent the actual thickness ratio. First, as shown in  FIG. 2(   a ), the Ge semiconductor substrate  2  for forming the Ge channel therein is prepared. After cleaning, the Ge semiconductor substrate  2  is placed in an ultra-high vacuum deposition chamber (not shown) where the native Ge oxide film formed on the semiconductor substrate surface is removed by heating. 
         [0035]    Next, Si is deposited by electron-beam evaporation in the ultra-high vacuum deposition chamber to form a Si interface layer  4  as shown in  FIG. 2(   b ). The thickness of the Si interface layer  4  is about 0.5 to 2 nm. Further, by performing electron-beam evaporation in the same ultra-high vacuum deposition chamber, a La 2 O 3  layer  6  that functions as the gate insulating film is formed over the Si interface layer  4 , as shown in  FIG. 2(   c ). During this step, the Ge semiconductor substrate  2  is held at 250° C. In one example, the La 2 O 3  layer  6  was formed to a thickness of 5.0 nm to 6.0 nm. 
         [0036]    After that, an upper electrode layer  8  is formed on top of the layer  6  by electron-beam evaporation, as shown in  FIG. 2(   d ). For the material of the electrode layer  8 , use can be made, for example, of Pt or W. The thickness of the upper electrode layer  8  is several nanometers when measuring the photoelectron spectrum and several tens of nanometers when measuring the electrical characteristic. In the case of the device having the structure of  FIG. 2(   d ), a back electrode (not shown) for measuring the electrical characteristic is formed after performing heat treatment in a nitrogen atmosphere. The heat treatment is performed, for example, for five minutes in a nitrogen atmosphere held at 500° C. 
         [0037]    It is presumed that, as a result of the heat treatment, some of the Si atoms in the Si interface layer  4  combine with the oxygen contained in the La 2 O 3  layer  6  to form various kinds of silicates such as SiO, SiO 2 , etc. or combine with La to form La-silicate. Therefore, the completed Ge channel device contains these silicates in the Si interface layer  4 . 
         [0038]    To investigate the effect of the Si interface layer  4  in suppressing the growth of Ge suboxide, the spectrum was measured by photoelectron spectroscopy, along with the measurement of the C-V characteristic. 
         [0039]      FIG. 3  is a diagram showing the photoelectron spectrum of the Pt/La 2 O 3 /Si/Ge structure; more specifically, the diagram shows how the photoelectron spectrum changes when the thickness of the Si interface layer  4  is varied. In particular,  FIG. 3  shows the spectrum in the vicinity of the peak due to the 2p electron of Ge. The measurement was performed after heat-treating the Pt/La 2 O 3 /Si/Ge structure for five minutes in a 500° C. nitrogen atmosphere. In the figure, the ordinate represents the emission intensity in an arbitrary unit, and the abscissa represents the binding energy in eV. 
         [0040]    Curve A shows the spectrum when the thickness of the Si interface layer was 0, i.e., when the Si interface layer was not provided, and curve B shows the spectrum when the thickness of the Si interface layer was not greater than 0.5 nm, while curve C shows the spectrum when the thickness of the Si interface layer was 1.0 to 1.5 nm. In the energy range shown, two distinct peaks were observed in the spectrum waveform. The peak near 1218 eV was presumably due to the Ge 2p electron, while the peak in the region of 1219 eV to 1222 eV was presumably due to Ge oxide. 
         [0041]    It is presumed that the peak due to Ge oxide contains emission peaks due to Ge suboxides GeOx where x is 0.5, 1, 1.5, etc. The spectrum curve A for the case where no Si interface layer was provided exhibits a relatively large peak in the region of 1219 eV to 1222 eV. Therefore, this structure is considered to contain an appreciable amount of Ge oxide. 
         [0042]    The spectrum curve B for the case where the Si interface layer was formed to a thickness not greater than 0.5 nm exhibits a slight peak in the region of 1219 eV to 1222 eV. Therefore, this structure is considered to contain Ge oxide, though in a trace amount. On the other hand, the spectrum curve C in the case where the Si interface layer was formed to a thickness of 1.0 to 1.5 nm hardly exhibits any observable peak in the region of 1219 eV to 1222 eV. Therefore, this structure is considered to contain very little of the Ge oxide. Since the Ge diffused into the La 2 O 3  layer remains therein in the form of oxide, the results of  FIG. 3  show that when the thickness of the Si interface layer is 1.0 to 1.5 nm or greater, the diffusion of Ge into the La 2 O 3  layer due to the heat treatment and the growth of Ge suboxide can be suppressed. 
         [0043]      FIG. 4  is a diagram showing the C-V characteristic curve S of a W/La 2 O 3 /Si(thickness not greater than 2 nm)/Ge structure for comparison with the C-V characteristic curve P of a W/La 2 O 3 /Ge structure. The C-V characteristics of these structures were measured after heat-treating them for five minutes in a 500° C. nitrogen atmosphere. As can be seen from the figure, the C-V characteristic curve P of the W/La 2 O 3 /Ge structure having no Si interface layer exhibits a marked hysteresis, and, the C/Cmax value also gently rises in the gate voltage region of −1 V to 1 V. Accordingly, with the W/La 2 O 3 /Ge structure having no Si interface layer, it is difficult to achieve a semiconductor device having an excellent switching characteristic. 
         [0044]    On the other hand, the C-V characteristic curve S of the W/La 2 O 3 /Si/Ge structure having a Si interface layer of thickness not greater than 2 nm exhibits only a slight hysteresis. Further, in the case of the curve S, the C/Cmax value steeply rises near the gate voltage 1 V; it can therefore be seen that a semiconductor device having an excellent switching characteristic can be formed using this structure. 
         [0045]    As described above, in the Ge channel device according to the present invention, since the Si interface layer (with thickness of about 0.5 to 2 nm) is interposed between the Ge substrate layer and the La 2 O 3  dielectric layer, the diffusion of Ge into La 2 O 3  can be suppressed while also suppressing the growth of suboxide; as a result, a Ge channel device having an excellent electrical characteristic can be formed. 
         [0046]      FIG. 5  is a diagram showing a capacitor device  10  that can be fabricated using the W(Pt)/La 2 O 3 /Si/Ge structure according to the present invention. In the figure, reference numeral  12  indicates the Ge semiconductor substrate,  14  the Si interface layer,  16  the La 2 O 3  layer, and  18  the electrode layer. The structure of each of these layers is the same as that described with reference to  FIG. 2 . In this device  10 , the Ge semiconductor substrate  12  can be formed on a semiconductor substrate  20 , for example, by epitaxial growth. This facilitates the handling of the device. Alternatively, a SiO 2  layer may be formed on the Si semiconductor substrate  20 , and the Ge semiconductor substrate  12  may be grown on top of that. 
         [0047]      FIG. 6  is a diagram showing the structure of a Ge-MOS transistor  30  that can be fabricated using the Ge channel device according to the present invention. The Ge channel layer  32  is formed on a supporting substrate  44 . The Ge channel layer  32  contains source and drain regions  34  and  36  formed by diffusing impurities. Reference numeral  38  indicates the Si interface layer,  40  the La 2 O 3  layer, and  42  the electrode layer formed from W or Pt or the like. The Si interface layer  38 , the La 2 O 3  layer  40 , and the electrode layer  42  can be formed on the Ge channel layer  32  by using the method of the embodiment shown in  FIG. 2 . 
         [0048]    Though not shown in  FIG. 6 , the source and drain electrodes are respectively formed on the source and drain regions  34  and  36 , thus forming a MOS transistor having a Ge channel  46 . The electrode layer  42  forms the gate electrode, and the La 2 O 3  layer  40  forms the gate insulating film, and by controlling the voltage applied to the gate electrode  42 , the conduction state of the channel  46  between the source and drain regions can be controlled, and the device can thus be operated as a switching device. From the C-V characteristic measured of the capacitor structure, it is expected that this transistor device has an excellent electrical characteristic sufficient for practical use.