Abstract:
A computing device includes a wafer having multiple layers, the wafer including a top layer and sublayers disposed below it, the sublayers including one or more memory devices. The computing device also includes two or more shaped retainer elements shaped to mate with and at least partially surround at least the top of the wafer and in electrical contact with one or more chips disposed on a top of the top layer and a holding device that mates with the retainer elements to provide at least power to the retaining elements. So arranged, the wafer may be cooled.

Description:
BACKGROUND 
       [0001]    This invention generally relates to stacked, multi-wafer structures, and, in particular, to communication of information to and from such structures and providing power to them. 
         [0002]    Huge quantities of data are being generated in the world in unconventional and unstructured formats (texts, video, images, sentiment, etc.). Making useful sense of these data requires new cognitive computing techniques similar to the way the human brain processes information. 
         [0003]    These techniques, which require very high memory and communication bandwidths, reach fundamental limitations in a conventional von Neumann architecture, which suffers from a bottleneck between a separated CPU and memory. 
       SUMMARY 
       [0004]    Disclosed is a computing device that includes a wafer having multiple layers, the wafer including a top layer and sublayers disposed below it, the sublayers including one or more memory devices. The computing device also includes two or more shaped retainer elements shaped to mate with and at least partially surround at least the top of the wafer and in electrical contact with one or more chips disposed on a top of the top layer and a holding device that mates with the retainer elements to provide power to the retaining elements. 
         [0005]    Also disclosed is a computing device that includes a wafer having multiple layers, the wafer including a top layer and sublayers disposed above it, the sublayers including one or more memory devices. The device also includes a holding device that mates with the wafer elements to provide at least power to the retaining elements, the holding device including wire springs that contact either the top layer or a bottom layer of the wafer. 
         [0006]    Please include cooling in the summary 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures: 
           [0008]      FIG. 1  illustrates an SSP according to one embodiment; (SSP is not defined at this point) 
           [0009]      FIG. 2  shows an example of stacked SPP wafers; (same comment as above) 
           [0010]      FIG. 3  shows a top view of a wafer stack held by two holding elements; 
           [0011]      FIG. 4  shows a cross-sectional view of  FIG. 3  taken along lines  4 - 4 ; 
           [0012]      FIG. 5  shows one configuration where the connectors include a groove into which the wafer may be inserted; 
           [0013]      FIG. 6  shows alternative connector embodiment to that shown in  FIG. 5 ; 
           [0014]      FIG. 7  shows a cross-section of a wafer attached to a board according to one embodiment; 
           [0015]      FIG. 8  shows a cross section of a wafer attached to a board according to another embodiment; 
           [0016]      FIG. 9  shows an example of a pin-fin heat sink; 
           [0017]      FIG. 10  shows a side view of a lidded wafer; and 
           [0018]      FIG. 11  shows a cross section of a wafer attached to a board according to another embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    Embodiments of the invention provide a construct that allows for power/data communication with a cortical system. Additionally the embodiments provide cooling schemes to draw power away from the cortical system. 
         [0020]    A cortical system may alleviate the CPU memory bandwidth problem of conventional computer architectures by transferring much of the memory intensive processing to a battalion of Simple Specialized Processors (SSPs) which are embedded in a large sea of computer memory. These SSPs carry out operations on their domains and then transmit very high level results to a number of General Management Processors (GMPs). The burden of the memory and communications bandwidth is therefore transferred largely to the SSPs. Since the SSPs report very high level results to the GMPs, the bandwidth required for the SSP-to-GMP communication is manageable. A more detailed description of how a cortical system may be formed may be found in U.S. patent application Ser. No. 14/713,689, which is incorporated herein by reference. 
         [0021]      FIG. 1  shows an SSP wafer  100 . In this wafer, a battalion of simple specialized processors (SSPs)  102  are embedded in a large sea of computer memory  104 . Memory  104  may comprise any suitable amount and type of memory. For example, the embedded memory, may be in the range of 30-300 GB per wafer, and, in embodiments of the invention, may be embedded DRAM, DRAM, or SRAM. 
         [0022]    Each SSP is associated with a memory domain, one of which is shown at  106 . The SSPs carry out operations on their domains  106  and then transmit very high level results to a small number of General Management Processors (GMPs). The SSPs may number between approximately 100-1000 per wafer. Each SSP is a specialized simple microprocessor to execute certain memory primitives for memory in its vicinity (domain). The SSPs are referred to as specialized because they are used for a limited number of functions. Any suitable processor may be used in embodiments of the invention as an SSP, and suitable processors are known in the art. 
         [0023]    Examples of SSP jobs include: find largest or smallest element in domain; multiply matrix or vector by constant; matrix-matrix, matrix-vector, vector-vector products; fill the domain with random numbers. The SSP also has router/buffer capabilities, discussed below. Each memory domain is a region of neuron/synaptic data which is owned by one SSP—this is the SSP&#39;s domain. 
         [0024]      FIG. 2  shows a stack  202  of wafers in accordance with an embodiment of the invention. This stack comprises four SSP wafers  204   a - 204   d , of the type shown in  FIG. 1  on top of a handle wafer  206  and a top wiring wafer  210 . In this embodiment, the top wafer  210  is mounted on top of the SSP wafer stack and is bonded to that stack, and the GMPs  212  and other high level chips are bonded by flip chip bonding to the wiring-level wafer. The bottom SSP wafer  204   a  is bonded to the handle wafer  206  via a bonding interface. 
         [0025]    Frontside wiring  212  on the final wiring wafer  210  is used, for example, to provide GMP-to-GMP communications. Communications between the GMP chips and the underlying SSPs can be done through a communication channel with only medium bandwidth capabilities such as a layer of micro C4s due to the modest bandwidth requirements, as discussed above. Inter-strata TSVs are used, for instance, for communication from GMP level to SSP level, and for connections to power and ground within the stack. 
         [0026]    As illustrated, interlayer connections  214  may be used to allow data to be transferred between SSP wafers and between the SSP wafers and the top wiring wafer  210 . Also illustrated is a power bus  216  that provides for the transmission of power to all wafers  204  and  210 . The interconnectivity between layers is shown by example only in  FIG. 2 . Of course, other configurations are possible. 
         [0027]    In the stack of  FIG. 2 , adjacent SSP wafers are placed back-to-front—that is, the backside of one of the adjacent wafers faces the front side of the other of the adjacent wafers. Backside wiring on the SSP wafer may be used, for example, to provide power and ground the wafer. Frontside wiring  212  on the final SSP wafer  210  may be used, for instance, for SSP-SSP communication from an external location to the wafers. 
         [0028]    The above-described wiring scheme is general, and many other suitable schemes may be used in embodiments of the invention. Also, for instance, in embodiments of the invention, backside wiring is optional, and power/ground can also be distributed on the front. Below, systems and methods for providing power/data from an external location to the wafer stack  202  are discussed. 
         [0029]    The stack in  FIG. 2  comprises four SSP wafers. It may be noted that the stack can be general to N SSP wafers, and have more or fewer SSP wafers than is shown in  FIG. 2 . 
         [0030]      FIG. 3  shows a top view of a wafer  300  contained in a two-part retaining element  301 . It shall be understood that the wafer  300  can include several layers as described above and, as such, may also be referred to as a wafer stack herein. 
         [0031]    The two part retaining element  301  includes retainer halves  301   a  and  301   b  and allows for power to be provided to the wafer  300 . It may also allow for data to be transferred to or from the wafer  300 . 
         [0032]    In this embodiment, the wafer  300  includes 2 GMPS  302 . This number is purely by way of example and is in no way limited. The GMPs  302  may be bonded on a wiring wafer  304 .  FIG. 3  also shows power supplies  314  and I/O connections  316 . As illustrated, Each GMP  302   a ,  302   b  is independent and includes has own respective power supply  314   a ,  314   b  and I/O connections  316   a ,  316   b . In another embodiment, one of the GMPs may be selected as the lead GMP, and the other GMP(s) are referred to as subordinate GMPs. In embodiments of the invention, memory chips bonded to the wiring wafer are optional and can be dedicate to an individual GMP  302  or shared between two or more GMPs or a combination of both. Any suitable memory chips or devices may be used in embodiments of the invention; and, for example, memory chips  312  may be DRAMs or other suitable memory chips in the range of 4-128 GB. 
         [0033]    The GMPs  302  may be high performance processors. Any suitable processor may be used as a GMP, and suitable processors are known in the art. The GMPs communicate with external I/O connections  316 . The GMP&#39;s may also receive power from a power supply  314 . The power supplies may also provide power directly to the I/O connections  316  (as illustrated) or such power may be provided through the GMP&#39;s  302 . One of ordinary skill will realize that any number of additional of GMP&#39;s, I/O connections, or any other kind of chip may be provided on the wiring wafer  304 . 
         [0034]    As illustrated, the two part retaining element  301  includes retainer halves  301   a  and  301   b . These retainer halves may be forced together to contact and surround outer edges of the wafer  300 . The outer edges are shown as element  320  in  FIG. 3 . 
         [0035]    The retainer halves  301   a  and  301   b  are shaped such that when brought together they will contact the outer edges  320  of the wafer stack  300 . The retainer halves  301   a ,  301   b  include one or more curvilinear connectors  350  shaped to mate with the outer edge  320 . As illustrated the retainer halves  301   a ,  301   b  include 4 separate connectors  350  labelled as  350   a ,  350   b  (contained in retainer half  301   b ) and  350   c ,  350   d  (contained in retainer half  301   a ) Of course the number of connectors may vary and be only one in one embodiment and can include any other number. The connectors allow power or data to be carried from or to an external location. For example, connectors  350   c  and  350   d  may be power connectors that receive power from external power lines  342   a  and  342   b , respectively. The external power lines  342   a ,  342   b  may connect to another source of power off of wafer  300 . 
         [0036]    Similarly, connectors  350   a  and  350   b  may be data connectors that provide data to I/O connections  316   a  and  316   b , respectively. The data may be received from or delivered to external data line  340   a ,  340   b  so that the wafer can transfer data to other wafers. The power lines and data lines can be on the surface of the wafer or between layers and, as such, are shown in dashed form. 
         [0037]    In the above description the connectors  350  where described are part of retainer halves  301   a  and  301   b . It shall be understood that in another embodiment, the connectors  350  could be attached to the wafer  300  first, and then inserted between the retainer halves  301   a ,  301   b . The retainer halves  301   a ,  301   b  could then be brought together to contact and hold the assembly including the connectors and the wafer  300 . The retainer halves  301  may form a holding device in one embodiment. 
         [0038]      FIG. 4  shows a block diagram of a cross-section of the embodiment shown in  FIG. 3  taken along line  4 - 4 . The wafer  300  has connectors  350   c  and  350   a  coupled to opposing sides thereof. The connectors  350   c  and  350   a  could initially be connected and part of retainer halves  301   a ,  301   b  or could be connected directly to the wafer  300  and then held by the retainer halves  301   a ,  301   b . In this embodiment, the connectors  350  are flush or nearly flush with the top  304  and bottom  404  of the wafer  300 . 
         [0039]      FIG. 5  shows an example of another embodiment where the connectors  550   c ,  550   a  (or any other connector) includes a groove  502  into which the wafer  300  may be inserted. In this embodiment, the connectors  550   c ,  550   a  have at least a top extension  560  or a bottom extension  570  (or both) that, respectively, covers at least a portion of the top  304  or the bottom  404  of the wafer stack. Such extensions may allow for the wafer  300  to be retained in the same manner as described above (e.g., by retaining halves  301   a  and  301   b ) or by a bottom mounted system. 
         [0040]      FIG. 6  shows an example of a bottom mounted system  600  that holds a wafer  300 . The wafer  300  (or wafer stack) includes connectors  550   a ,  550   c  that include bottom extensions  570 . Of course, the connectors could also include top extensions or no extension in one embodiment. 
         [0041]    The wafer of  FIG. 6  may be inserted into and held in various manners. For example, with reference now to  FIG. 7 , the wafer  300  including one or more connectors  550  may be inserted into a open-bottomed socket  700 . The socket (holding device) includes a seat  702  and outer edges  704 . The socket  700  receives power or data from a circuit board or laminate  720  via connections  710  (e.g., solder bumps) in one embodiment but other means for providing power/data to the socket  700  could be utilized. The socket also includes one or more springs  712  through which power or data can be communicated with the wafer. The springs  712  may be formed or a deformable metal and may be referred to as wires herein. 
         [0042]    As illustrated, the wafer includes connectors  550  coupled to it outer edges. These connectors could be omitted in one embodiment. For example, if omitted, the wafer could be flipped over and placed face down such that the power/data access locations on the upper surface  304  may contact the springs  712 . Of course, the power/data access locations could be location on an underside of the wafer  300  instead and, in such a case, the wafer  300  need not be flipped over. Such is shown in  FIG. 11 . (why not renumber the figures to have  FIG. 11  as  FIG. 8  instead of a non-sequential order of figures?)—This comment can be removed. 
         [0043]    Most wafer level packaging approaches involve attaching the chips to wafers, and then dicing the larger wafers to create 2-high stack chip-on-chip structures that can then be attached to chip-carrier substrates and then packaged in a similar manner to conventional 2D packages. Power delivery is achieved through the bottom chip with through silicon vias to the top chip. Cooling of such structures is then achieved by a TIM inserted between the top chip and a lid attached to the chip-carrier substrate. The bottom chip in the stack has a thermal penalty compared to a 2D chip since the heat dissipated in the bottom chip has to conduct through the top chip and the chip-chip interconnects. 
         [0044]    To provide for cooling, in one in one embodiment, the board  720  includes a hole  722  that allows for air to flow to an underside of the wafer. In one embodiment, a heat sink  724  may be attached to the wafer on its underside. The heat sink can be attached to the top of the wafer, the bottom of the wafer or both. Further, referring again to  FIG. 3 , such a configuration will also allow for heat sinks to be placed on the top/bottom due to its open nature. The wafer  300  may be inserted into the socket  700  in direction Z. 
         [0045]      FIG. 8  shows an alternative embodiment. In this embodiment, a circuit board  800  includes a full socket  802  coupled thereto. The full (holding device) includes a seat  803  and outer edges  812 . The socket  802  receives power or date from a circuit board or laminate  720  via connections  810  (e.g., solder bumps) in one embodiment but other means for providing power/data to the socket  802  could be utilized. The socket also includes one or more springs  813  through which power or data can be communicated with the wafer. As illustrated, the wafer includes connectors  550  coupled to it outer edges. These connectors could be omitted in one embodiment. For example, if omitted, the wafer could be flipped over and placed face down such that the power/data access locations on the upper surface  304  may contact the springs  813 . Of course, the power/data access locations could be location on an underside of the wafer  300  instead and, in such a case, the wafer  300  need not be flipped over. The wafer  300  may be inserted into the socket  800  in direction Z. 
         [0046]    An example of a heat sink  900  that may be used is shown in  FIG. 9 . It shall also be understood that another heat sink may be placed on a bottom wafer  300 . The heat sink in  FIG. 9  includes a base  901  from which a sidewall  902  extends upwardly to a top layer  904 . The sidewall may be sized and arranged such that it creates a hollow region under the top layer  904  so that chips on the top of the wafer may fit under and be in thermal contact with the heat sink  900 . As illustrated, the heat sink  900  includes a plurality of optional pin fins  906 . Fins of other shapes can also be used. 
         [0047]      FIG. 10  shows an example of a heat sink  1000  disposed on top of a wafer  300  that includes chips  302   a ,  314   a  and  316   a  connected to a top side thereof. An adhesive  1002  may hold the sidewalls  1004  to the wafer  300 . In addition, heat transferring material may be disposed between the chips  302   a ,  314   a  and  316   a  and the tip  1006  of the heat sink. Such a material may include a glue in one embodiment, or polymers, epoxies or solders. 
         [0048]    The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.