Abstract:
A DC-to-DC converter having multiple power delivery channels, and including a current-sharing switching controller implemented as an integrated circuit, multi-channel circuitry (including parallel channels connected to one output node) external to the controller chip, and current sharing circuitry (including circuitry external to the controller chip and circuitry including current mirrors internal to the controller chip), and methods for generating PWM power switch control signals for use in (and performing DC-to-DC conversion using) such a DC-to-DC converter. Preferably, the current sharing circuitry generates individual channel current signals from voltage analogs thereof produced external to the controller chip, and superposes the individual channel current signals to produce an average current signal. Channel current error signals are generated by subtracting the individual channel current signals from the average current signal. The power switch control signal for each channel is generated in response to the channel current error signal for the appropriate channel and a feedback signal (an output voltage error signal) indicative of the output potential of the DC-to-DC converter relative to a reference potential, so that the DC-to-DC converter achieves a desired output potential with increased current sharing among the channels. The invention implements current sharing between channels of a DC-to-DC converter using simple circuitry external to the controller chip (and without an external bus which connects one channel to the other), and with simple, silicon-area efficient circuitry internal to the controller chip. Preferably, current mirror circuitry in the controller chip generates a set of identical average current signals, each of which is proportional to the average of the currents drawn from the individual channels, and additional current mirror circuitry generates a set of identical error current signals, each of which is an error current proportional to the difference between the DC-to-DC converter&#39;s output potential and a reference potential.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to switching DC-to-DC converters having multiple power channels (either simple-paralleled or interleaved-paralleled) and configured to implement current sharing, in the sense that feedback indicative of the output current drawn from each channel is used to reduce the differences between the output currents drawn from the individual channels, thus preventing any of the channels from contributing significantly more to the combined output current than any of the other channels. 
     2. Description of the Related Art 
     For convenience, we will use the expression &#34;switching controller&#34; chip below to denote either a controller (implemented as an integrated circuit) which generates power switch control signals for at least one power switch implemented external to the chip (typically multiple power switches, each implemented external to the chip), or a switching &#34;regulator&#34; (implemented as an integrated circuit) which generates such power switch control signals and which also includes at least one power switch implemented on-board the chip (typically multiple power switches, each implemented on-board the chip). The power switches are typically MOSFET devices. 
     One type of conventional switching power supply circuitry which employs current-sharing control to achieve output voltage regulation is a DC-to-DC converter including a current-share switching controller chip, and circuitry (including a current sense resistor) external to the controller chip. The controller chip includes one or more channels, each channel generating a pulse width modulated power switch control signal in response to a ramped voltage and a feedback signal indicative of the DC-to-DC converter&#39;s output potential. Typically, each pulse width modulated power switch control signal is a binary signal having periodically occurring leading edges, and trailing edges which occur at times determined by the instantaneous value of the feedback signal. Typically, the ramped voltage signals for all the channels increase periodically (with the same period for all channels) at a fixed ramp rate, and their waveforms are identical (to the extent possible and practical), except that each may have a different phase than the others. In interleaved PWM DC-to-DC converters (where &#34;PWM&#34; denotes &#34;pulse width modulated&#34;), the ramped voltage signals and pulse width modulated power switch control signals are out of phase with respect to each other. In non-interleaved PWM DC-to-DC converters, the ramped voltage signals and pulse width modulated power switch control signals are in phase with respect to each other. 
     In power supply circuitry, it is often desired to employ multiple (parallel) channels, each channel generating a pulse width modulated power switch control signal for a different power switch. For example, in PWM DC-to-DC converters, multiple pulse width modulated power switch control signals are generated (in parallel) by providing multiple ramped voltages in parallel to comparator circuitry. The power switch control signals typically all have the same duty cycle. Often, the power switch control signals are generated in a current-share switching controller chip, and asserted to external power switch circuitry (comprising multiple power switches) to cause the latter circuitry to determine the amplitude of the DC output voltage of the DC-to-DC converter. An advantage of providing multiple channels (each channel including a power switch) rather than a single channel is that use of multiple channels allows the DC-to-DC converter to be implemented with smaller power stage inductors, smaller input filter inductors, and smaller output capacitors, thus providing an overall improved step-load transient response and reduced physical size. 
     However, when implementing such multi-channel, a variety of factors including process and temperature variations typically cause undesired variation from channel to channel in the output current drawn from each channel by the load (to which the output node of the DC-to-DC converter is coupled). 
     When implementing a current shared switching controller for a DC-to-DC converter with multiple channels, it is desirable to prevent any of the channels from contributing significantly more to the output current (the output drawn by the load at the output of the DC-to-DC converter) than any of the other channels. Preferably, the converter is implemented so that all the channels contribute equally to the output current. Current sharing between the channels (whether the paralleled power switch control signals are interleaved or non-interleaved) is essential for reliable operation and to achieve a minimum-cost system solution. As load levels increase, active feedback is required for equal distribution of current between the channels. 
     However, until the present invention, it was not known how to implement such current sharing using silicon-area efficient circuitry within a current mode switching controller chip (and simple circuitry external to the controller chip) while achieving a high degree of current sharing among the channels. 
     SUMMARY OF THE INVENTION 
     In a class of embodiments, the invention is a DC-to-DC converter having multiple power delivery channels, and including a current share switching controller (implemented as an integrated circuit), multi-channel circuitry (including parallel channels connected to a single output node) external to the controller chip, and current sharing circuitry (including circuitry external to the controller chip and circuitry including current mirrors internal to the controller chip). In preferred embodiments, the current sharing circuitry generates individual channel current signals (currents proportional to or otherwise indicative of the individual channel currents) from voltage analogs (produced external to the controller chip) thereof, and superposes the individual channel current signals to produce an average current signal (or multiple copies thereof). Channel current error signals are generated by subtracting the individual channel current signals from the average current signal. Optionally, the channel current error signals are amplified with a gain that is controlled by an external gain control signal applied to a pin of the controller chip. The power switch control signal for each channel is generated in response to the channel current error signal (for the appropriate channel) and a feedback signal (an output voltage error signal) indicative of the output potential of the DC-to-DC converter relative to a reference potential, so that the DC-to-DC converter achieves a desired output potential with increased current sharing among the channels (reduced differences between the currents drawn by the converter&#39;s load from the individual channels). 
     In accordance with the invention, current sharing is implemented between channels of a DC-to-DC converter using simple circuitry external to the controller chip (and without an external bus which connects one channel to the other), and with simple, silicon-area efficient circuitry internal to the controller chip. 
     In preferred embodiments, current mirror circuitry internal to the controller chip generates a set of identical average current signals (one for each channel), each of which is a &#34;channel average current&#34; proportional to the average of the currents drawn (by the load at the DC-to-DC converter&#39;s output) from the individual channels. Additional current mirror circuitry generates a set of identical error current signals (one for each channel), each of which is an error current proportional to the difference between the output potential of the DC-to-DC converter and a reference potential. Circuitry is also provided for generating individual channel current signals, each proportional to the current (the &#34;individual channel current&#34;) drawn (by the load at the DC-to-DC converter&#39;s output node) from a different one of the channels. Additional current mirror circuitry generates a set of control signals (one for each channel), each having a current equal (or proportional) to the error current (itself proportional to the output voltage error) plus the difference between the channel average current and a different one of the individual channel currents. Each control signal is used to generate a PWM power switch control signal for a different one of the channels. An unique feature of this architecture is the use of current mirrors and &#34;current-mode signal-processing&#34; within the controller chip. 
     Other aspects of the invention are methods for generating PWM power switch control signals for use in a multi-channel, switching DC-to-DC converter using any embodiment of the inventive controller circuitry, and methods for performing DC-to-DC conversion with multiple power delivery channels using any embodiment of the inventive current mode switching controller chip and the inventive external circuitry coupled to the controller chip. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a preferred embodiment of the inventive DC-to-DC converter. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A preferred embodiment of the invention will be described with reference to FIG. 1. The DC-to-DC converter of FIG. 1 has four power delivery channels (each including a different one of power switches Q1, Q2, Q3, and Q4), and comprises current share switching controller chip 1, buck converter circuitry external to controller chip 1, and current sharing circuitry. The current sharing circuitry comprises circuitry (including resistors R1, R2, R3, and R4, and capacitors C1, C2, C3, and C4) external to controller chip 1, and circuitry (including elements 11, 12, 13, 14, 20, 21, 31, 32, 33, and 34) within controller chip 1. 
     The external buck converter circuitry comprises four identical portions, connected in parallel. The first portion comprises power switch Q1 which is connected between the input node (at input potential V in ) and Node 1, and is controlled by signal DRV1 from controller chip 1 (preferably switch Q1 is implemented as an NMOS transistor whose gate is coupled to receive signal DRV1); inductor L1 connected between Node 1 and the output node (Node 5); Schottky diode SD1 connected between Node 1 and ground, and resistor R1 and capacitor C1 connected in series between Node 1 and ground. The second portion comprises power switch Q2 which is connected between the input node and Node 2 and is controlled by signal DRV2 from controller chip 1 (preferably switch Q2 is implemented as an NMOS transistor whose gate is coupled to receive signal DRV2); inductor L2 connected between Node 2 and the output node; Schottky diode SD2 connected between Node 2 and ground, and resistor R2 and capacitor C2 connected in series between Node 2 and ground. The third portion comprises power switch Q3 which is connected between the input node and Node 3 and is controlled by signal DRV3 from controller chip 1 (preferably switch Q3 is implemented as an NMOS transistor whose gate is coupled to receive signal DRV3); inductor L3 connected between Node 3 and the output node; Schottky diode SD3 connected between Node 3 and ground, and resistor R3 and capacitor C3 connected in series between Node 3 and ground. The fourth portion comprises power switch Q4 which is connected between the input node and Node 4 and is controlled by signal DRV4 from controller chip 1 (preferably switch Q4 is implemented as an NMOS transistor whose gate is coupled to receive signal DRV4); inductor L4 connected between Node 4 and the output node; Schottky diode SD4 connected between Node 4 and ground, and resistor R4 and capacitor C4 connected in series between Node 4 and ground. 
     In embodiments in which switches Q1-Q4 are NMOS transistors, each of Nodes 1, 2, 3, and 4 is coupled to the source of a different one of the NMOS transistors, and the drains of the NMOS transistors are coupled to receive the input potential V in . 
     The buck controller circuitry of FIG. 1 has conventional design, except in that, in accordance with the present invention, it includes resistors R1-R4 and capacitors C1-C4. No external current sharing bus (or other external circuitry) connects the four power distribution channels together. The node between resistor R1 and capacitor C1 is coupled to pin ISNS0 of controller chip 1, and is at potential V1 which is proportional to the current drawn from the first channel (i.e., through inductor L1) by the load coupled to the output node (Node 5). Similarly, the node between resistor R2 and capacitor C2 is coupled to pin ISNS1 of controller chip 1, and is at potential V2 which is proportional to the current drawn from the second channel (i.e., through inductor L2) by the load coupled to the output node, the node between resistor R3 and capacitor C3 is coupled to pin ISNS2 of controller chip 1, and is at potential V3 which is proportional to the current drawn from the third channel (i.e., through inductor L3) by the load coupled to the output node, and the node between resistor R4 and capacitor C4 is coupled to pin ISNS3 of controller chip 1, and is at potential V4 which is proportional to the current drawn from the fourth channel (through inductor L4) by the load coupled to the output node. Resistors R1-R4 and capacitors C1-C4 implement a non-dissipative switching voltage sense scheme, with each of pairs R1 and C1, R2 and C2, R3 and C3, and R4 and C4 implementing a low-pass RC filter which averages the potential between the resistor and capacitor. Alternatively, dissipative circuitry (external to the controller chip and typically including a sense resistor in series with inductors L1-L4 and one terminal connected to Node 5) is coupled between each channel and the corresponding one of pins ISNS0-ISNS3 to assert signals indicative of the current through each inductor L1-L4 to controller chip 1. 
     An output voltage feedback resistor divider, comprising resistors R5 and R6, is connected between the output node and ground, and an output capacitor C o  is connected between the output node and ground. The node between resistors R5 and R6 is coupled to pin FB of controller chip 1, so that the potential at that node (which is indicative of the DC-to-DC converter&#39;s output potential at Node 5) is supplied as feedback to pin FB. 
     Controller chip 1 includes voltage-to current converters 11, 12, 13, and 14, coupled respectively to pins ISNS0, ISNS1, ISNS2, and ISNS3. Converters 11, 12, 13, and 14 are identical, each having two outputs at which it asserts currents proportional to the input potential at the corresponding one of pins ISNS0, ISNS1, ISNS2, and ISNS3. Specifically, currents I 12  and I 13  at the outputs of converter 11 are proportional to potential V1, currents I 22  and I 23  at the outputs of converter 12 are proportional to potential V2, currents I 32  and I 33  at the outputs of converter 13 are proportional to potential V2, and currents I 42  and I 43  at the outputs of converter 14 are proportional to potential V3. 
     Converter 11 includes buffer amplifier 2 (whose noninverting input is coupled to pin ISNS0), current mirror circuitry 4, resistor Rsp, NMOS transistor N2 (having a gate coupled to the output of amplifier 2, a drain coupled to current mirror 4, and a source coupled through resistor Rsp to ground). The source of transistor N2 is coupled to the inverting input of amplifier 2. The current I 11  through the channel of transistor N2 is determined by (and proportional to) the potential V1 at pin ISNS0. Current mirror 4 has two outputs, each of which asserts a current (I 12  or I 13 ) identical to current I 11 . 
     The current mirror within voltage to current converter 12 has two outputs, each of which asserts a current (I 22  or I 23 ) proportional to the potential at pin ISNS1. The current mirror within voltage to current converter 13 has two outputs, each of which asserts a current (I 32  or I 33 ) proportional to the potential at pin ISNS2. The current mirror within voltage to current converter 14 has two outputs, each of which asserts a current (I 42  or I 43 ) proportional to the potential at pin ISNS3. 
     Currents I 12 , I 22 , I 32 , and I 42  flow to Node 6, and thus the current through the channel of transistor N6 (within current mirror 20) is equal to (I 12  +I 22  +I 32  +I 42 ). Current mirror 20 includes NMOS transistors N5 and N6 connected as shown. The channels of transistors N5 and N6 have length to width ratios such that the current through the channel of N5 is I avg  =k 1  (I 12  +I 22  +I 32  +I 42 ), where k 1  is a constant determined by the ratio of the width to length ratio of transistor N5&#39;s channel to the width to length ratio of transistor N6&#39;s channel. Current I avg  is proportional to the average of the currents drawn from the four channels of the DC-to-DC converter. Preferably k 1  =1/4. 
     Current mirror circuitry 21, coupled to current mirror 20 as shown, is configured to assert four identical currents k(I avg ) in parallel, in response to current I avg , where k is a constant determined by the characteristics of the components of current mirror circuitry 21. 
     In alternative embodiments, current mirror circuitry 21 is configured so that the parameter k is variable in response to an external control signal (e.g., a signal applied to a pin labeled &#34;Gain&#34;, indicated in phantom view, and supplied from the pin labeled &#34;Gain&#34; to circuitry 21). Thus, a desired value of parameter k is determined by an external control signal applied (from external circuitry) to a pin of controller chip 1, and from such pin to circuitry 21, and each current signal k(I avg ) is effectively amplified with a gain that is controlled by the external gain control signal. 
     As mentioned, pin FB of controller chip 1 is at a potential indicative of the DC-to-DC converter&#39;s output potential (the potential at Node 5). The inverting input of error amplifier 9 is coupled to pin FB. The noninverting input of error amplifier 9 is coupled to the output of digital-to-analog converter 7 (&#34;DAC&#34; 7). The input of DAC 7 is coupled to pins which receive binary control bits &#34;VID CODE&#34; (supplied from an external unit) which determine a reference potential V ref . In response to the control bits VID CODE, DAC 7 asserts reference potential V ref  to the non-inverting input of error amplifier 9. The output of error amplifier 9 (which is asserted both to pin &#34;EAOUT&#34; and to the noninverting input of error amplifier 10) is a potential indicative of the difference between the potential at Node 5 (the output potential of the DC-to-DC converter) and the reference potential V ref . 
     Reference potential V ref  is normally not varied during use of the circuit. In order to set (or vary) the regulated level of the output potential at Node 5, resistors R5 and R6 with the appropriate resistance ratio R5/R6 are employed. 
     The inverting input of error amplifier 10 is coupled to the source of NMOS transistor N1, the output of error amplifier 10 is coupled to the gate of NMOS transistor N1, and the source of transistor N1 is coupled through resistor R E  to ground. The drain of transistor N1 is coupled to current mirror circuitry 16. The current through transistor N1 (denoted &#34;g m  I&#34;) is determined by the difference between the output potential of amplifier 9 and the voltage across resistor R E , and is thus linearly related to the difference between the reference potential V ref  and the output potential of the DC-to-DC converter (at Node 5). Thus, if the output potential of the DC-to-DC converter is at the reference potential V ref , the current g m  I has a first value, and if the output potential of the DC-to-DC converter then decreases below the reference potential V ref , the current g m  I increases to a level above the first value. 
     Current mirror circuitry 16, coupled to transistor N1 as shown, is configured to assert four parallel, identical currents g m  I, each identical to the current through the channel of transistor N1. Each of these currents is asserted to the input node of a different one of current mirror circuits 31, 32, 33, and 34. Circuits 31, 32, 33, and 34 are identical to each other, and each includes two NMOS transistors identical to transistors N3 and N4 (connected as shown within the block labeled 31). The drain and gate of N3, and the gate of N4 are at the same potential, and current I 13  flows through the channel of N3. Thus, the current through the channel of N4 is equal to current I 13 . The drain of N4 (Node 7) is coupled to an output of circuit 21, and output of circuit 16, and to an input of circuit 41 (to the noninverting input of comparator 8 within circuit 41). Thus, the current flowing from Node 7 to circuit 41 is equal to g m  I+k(I avg )-I 13 . 
     Similarly, the current flowing from circuit 32 to circuit 42 is equal to equal to g m  I+k(I avg )-I 23 , the current flowing from circuit 33 to circuit 43 is equal to equal to current g m  I+k(I avg )-I 33 , and the current flowing from circuit 34 to circuit 44 is equal to equal to current g m  I+k(I avg )-I 43 . 
     Controller chip 1 also includes oscillator 15 which generates ramped voltage signals RA1, RA2, RA3, and RA4. All of signals RA1-14 RA4 have the same frequency (determined by externally supplied control signal FSET), but are out of phase with respect to each other. Typically, RA4 is 90 degrees out of phase with respect to RA3, RA3 is 90 degrees out of phase with respect to RA2, RA2 is 90 degrees out of phase with respect to RA1, and RA1 is 90 degrees out of phase with respect to RA4. Each ramped voltage RA1, RA2, RA3, and RA4 periodically increases at a fixed ramp rate and then decreases, with a waveform as indicated. 
     Circuits 41, 42, 43, and 44 are identical, each comprising a comparator (identical to comparator 8 of circuit 41) whose inverting input is coupled to receive a different one of ramped voltage signals RA1, RA2, RA3, and RA4 (circuit 41 receives RA1, circuit 42 receives RA2, circuit 43 receives RA3, and circuit 44 receives RA4), a resistor R 11  connected between ground and the comparator&#39;s noninverting input, and a capacitor C 11  and resistor R 12  connected between ground and the comparator&#39;s noninverting input (in parallel with resistor R 11 ). These resistor-capacitor circuits connected between the noninverting input and ground convert the current signal to a voltage and also provide frequency dependent gain. 
     Comparator 8 within circuit 41 produces &#34;reset&#34; pulse train D1 in response to a comparison of ramped voltage RA1 with the feedback potential at Node 7 (which is indicative of the current g m  I+k(I avg )-I 13 ). In response to the leading edge of each pulse of pulse train D1, a latch within logic (and gate driver generation) circuit 50 is reset to cause the power switch control signal DRV1 to undergo a transition to a level which turns off switch Q1. 
     Oscillator 15 also asserts four periodic &#34;set&#34; pulse trains (each in phase with one of ramped voltage signals RA1, RA2, RA3, and RA4) to latch circuitry within circuit 50. One latch for each channel is set (in response to each &#34;set&#34; pulse of each such pulse train, and is reset by each &#34;reset&#34; pulse of the corresponding one of &#34;reset&#34; pulse trains D1, D2, D3, and D4. Each time the latch for the first channel is set, the power switch control signal DRV1 undergoes a transition to a level which turns on switch Q1. Thus, although switch Q1 turns on at times in phase with the periodic &#34;set&#34; pulse train, it turns off at times (determined by &#34;reset&#34; pulse train D1) that have arbitrary phase relative to the pulses of the periodic &#34;set&#34; pulse train. 
     In the same way, the comparator within each of circuits 42, 43, and 44 produces one of &#34;reset&#34; pulse trains D2, D3, and D4 in response to a comparison of the corresponding one of ramped voltages RA2, RA3, and RA4 with a feedback potential indicative of the corresponding one of currents g m  I+k(I avg )-I 23 , g m  I+k(I avg )-I 33 , and g m  I+k(I avg )-I 43 . In response to the leading edge of each pulse of pulse train D2, a latch within circuit 50 is reset to cause the power switch control signal DRV2 to undergo a transition to a level which turns off switch Q2. In response to the leading edge of each pulse of pulse train D3, a latch within circuit 50 is reset to cause the power switch control signal DRV3 to undergo a transition to a level which turns off switch Q3. In response to the leading edge of each pulse of pulse train D4, a latch within circuit 50 is reset to cause the power switch control signal DRV4 to undergo a transition to a level which turns off switch Q4. 
     Pulse width modulated power switch control signals DRV1, DRV2, DRV3, and DRV4 (asserted at the output of logic and gate driver generation circuit 50) respectively turn power switches (transistors) Q1, Q2, Q3, and Q4 on and off with a controlled duty cycle. Each of switches Q1, Q2, Q3, and Q4 turns on at times in phase with a periodic &#34;set&#34; pulse train, and turns off at times (determined by the corresponding one of &#34;reset&#34; pulse trains D1, D2, D3, and D4) that have arbitrary phase relative to the pulses of the periodic &#34;set&#34; pulse train. 
     Circuit 50 can include logic circuitry for causing controller 1 to operate in desired ones of multiple operating modes. For example, it can be implemented with soft start circuitry which overrides the previously described circuitry for generating signals DRV1, DRV2, DRV3, and DRV4 in a soft start mode. In another class of examples, it can include circuitry for implementing an operating mode in which only a subset of switches Q1, Q2, Q3, and Q4 is used. As an example of the latter embodiment, the FIG. 1 circuit may operate in a mode in which only switches Q1, Q2, and Q3 are used, with oscillator 15 generating only signals RA1, RA2, and RA3 (each 120 degrees out of phase with respect to each other) and three periodic &#34;set&#34; pulse trains (each in phase with one of signals RA1, RA2, and RA3), and circuits 14, 34, and 44 being disabled. 
     We sometimes use the term &#34;channel&#34; to refer to the circuitry for generating one of the signal pairs D1 and DRV1, D2 and DRV2, D3 and DRV3, and D4 and DRV4, and providing a corresponding contribution to the current drawn from the output node (Node 5), so that the FIG. 1 circuit includes four channels (one channel comprising elements 11, 31, 41, Q1, and L1; another channel comprising 12, 32, 42, Q2, and L2; a third channel comprising 13, 33, 43, Q3, and L3; and a fourth channel comprising 14, 34, 44, Q4, and L4). The portion of each channel of circuitry that is external to the controller (e.g., elements Q1, SD1, L1, R5, R6, and C o  of FIG. 1, but not elements 11, 31, and 41 of FIG. 1) is sometimes also referred to as a &#34;channel&#34; (or a &#34;power delivery channel&#34;). The sets of control signals themselves are sometimes also referred to as &#34;channels&#34; of control signals. 
     The control technique of the invention comprises the steps of: sensing the individual channel currents drawn from the output node of a DC-to-DC converter (e.g., the currents drawn from Node 1, Node 2, Node 3, and Node 4 of FIG. 1), generating a signal indicative of the average of the individual channel currents, generating individual channel error signals indicative of the error in each individual channel current relative to its desired theoretical value (determining the difference between each individual channel current and the average of the channel currents), and modifying a general feedback signal (a feedback signal indicative of the difference between the DC-to-DC converter&#39;s output potential and the desired output potential) with each of the individual channel error signals to determine the duty cycle for the power switch of each channel. 
     Although only a preferred embodiment has been described in detail herein, those having ordinary skill in the art will certainly understand that many modifications and variations thereon are possible without departing from the teachings hereof. For example, a wide variety of DC-to-DC converters which employ circuitry, other than buck converter circuitry, external to a current mode switching controller can be implemented in accordance with the invention (in one class of such DC-to-DC converters, boost converter circuitry external to a current mode switching controller chip is employed, the boost converter circuitry provides voltage signals indicative of the individual channel currents to the controller chip, and the controller chip is implemented in accordance with the invention). All such modifications and variations are intended to be encompassed within the following claims.