Abstract:
A circuit arrangement for brief mute switching of the reproduction of an LF signal in a radio receiver for performing additional control operations is described, in which the mute switching is effected by varying the current flow through the control path of an interrupter by means of a reversing switch, as a consequence of the change in charge of a capacitor acted upon by a blanking signal.

Description:
The subject of the patent is a circuit arrangement for brief mute switching of the reproduction of an LF signal in a radio receiver, is generically defined by the preamble to claim 1. 
     BACKGROUND OF THE INVENTION 
     One such circuit arrangement is known from the earlier German Patent Application P 43 26 097 of the same inventor. This known circuit arrangement attains the object of making extremely brief, hardly perceptible interruptions, free of clicking noises, in the LF signal of the radio receiver in order to carry out additional control operations. 
     SUMMARY OF THE INVENTION 
     The object of the present invention was to further improve the transition to the mute-switched or re-activated state in terms of freedom from clicking noises upon an interruption and in terms of avoiding perceptibility of the interruptions themselves. 
     This object is attained according to the invention by the provisions recited in claim 1. 
     Advantageous features of the invention are defined by the characteristics of the dependent claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Details of the invention will be described in conjunction with the drawing. To that end, 
     FIG. 1 shows the function circuit diagram of the novel circuit arrangement; 
     FIG. 2 shows an exemplary embodiment of the novel circuit arrangement; 
     FIG. 3 shows voltage courses between two reference points of the exemplary embodiment; 
     FIG. 4 shows the voltage course at the output of the exemplary embodiment during a blanking pulse. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The low-frequency useful signal that is to be interrupted briefly is carried in FIG. 1 from an LF input 1 of the circuit arrangement via a coupling capacitor C 2  to a controllable semiconductor system that forms an interrupter 2. The output of the interrupter 2, which is connected to ground, via a resistor R 3 , simultaneously forms the LF output 3 of the circuit arrangement. 
     The resistor R 3  also defines the DC operating point of the interrupter 2. 
     Connected to the output of the interrupter 2, that is, to the high point of the resistor R 3 , is a current branch 4, which is supplied from one output of a reversing switch 6. The current branch 4 is located parallel to the control branch 5 of the interrupter 2, which is connected to the other output of the reversing switch 6. The input of the reversing switch 6 is connected to a constant current source 7, which is connected to the terminal for the supply voltage U B . 
     The position of the reversing switch 6 is determined by the charge state of the capacitor C 1 , which is connected to ground via a resistor R 2  and to the terminal for the supply voltage U B  via a resistor R 1 . At the terminal 8, via the resistor R 10 , the blanking pulse is supplied to the high point of the capacitor C 1  and to the reversing switch 6. The position of the switch arm of the reversing switch 6 determines whether the current from the constant current source 7 flows via the control path 5 of the interrupter 2 and the resistor R 3  or via the current branch 4 and in turn the resistor R 3  to ground. In both cases, the same voltage drop occurs at the resistor R 3 , so that at the LF output 3 no difference can be found, regardless of whether the LF signal itself is precisely equal to zero, or the interrupter 2 is preventing the further conduction of the LF signal. Because the potential at the high point of the resistor R 3  remains constant, there is no charge reversal of the coupling capacitor C 2 , either, upon the mute switching or the cancellation thereof. 
     Thus no voltage changes, which could be the cause of clicking noises in the circuit, not shown in detail, connected to the output 3 of the circuit arrangement occur in the circuit arrangement. 
     In the exemplary embodiment of the circuit arrangement shown in FIG. 2, two antiparallel-connected npn transistors T 1  and T 2  form the aforementioned interrupter 2. The base terminals of the transistors T l  and T 2 , which are located in the control circuit 5 of the interrupter, are connected to the one output of the reversing switch 6 via rectifiers D 1  and D 2  assigned to them. 
     The reversing switch 6 is formed by two parallel pnp transistors T 3  and T 4 , which are connected to a differential circuit by the current branches 4 and 5 connected to their collectors and by the resistor R 3 . The collector of a further pnp transistor T 5  is connected to the emitters of the transistors T 3  and T 4  and acts as a constant current source 7, and its emitter is connected via a resistor R 4  to the terminal for the supply voltage U B  of 8.5 V. 
     A voltage divider formed by the resistors R 5  and R 6  is connected between the terminal U B  and ground and determines the operating point of the transistor T 5 . The base terminal of the transistor T 5  is connected to the connecting line located between the resistors R 5  and R 6 . A second voltage divider comprising the resistors R 7  and R 8 , which is likewise located between the terminal U B  and ground, forms the static operating point of the transistor T 4  in the differential circuit. 
     The base of the transistor T 4  located at the pickup of the second voltage divider R 7 , R 8  is also connected via a resistor R 9  to the high point of the capacitor C 1 . Also located at its potential is the base of the transistor T 3  in the differential circuit. This potential is determined on the one hand, via the resistor R 10 , by the voltage at the blanking pulse input 8, and on the other by the ratio of the resistors R 1 , R 2 , of which the resistor R 1  is connected to the terminal U B  while the resistor R 2  is connected to ground. 
     The design of the reversing switch 6 as a differential circuit brings about a controlled switching speed of the reversing switch and hence a controlled steepness of the edge in the interruption of the LF signal. An interruption with suitably controlled edge steepness in turn shortens the time required for the LF signal to drop or rise again at a minimal interference spectrum. As a result, a control function of predetermined duration can be performed within a shorter interruption of the LF signal, which markedly improves the avoidance of perceptibility of the interruption. 
     For the duration of the blanking pulse, the potential at the blanking pulse input 8 is dropped from approximately 5.0 V to 0 V. The voltage values given in the description below are based on the use of npn transistors of type BC 848 C as T 1  and T 2 , and pnp transistors of type BC 858 C as T 3 , T 4  and T 5 . 
     FIG. 3 on the left shows the voltage course between the base of the transistor T 3  and the base of the transistor T 4 , which acts as a reference, during the descending edges or in other words at the onset of a blanking pulse, and on the right during the reascending edge, that is, at the end of a blanking pulse. During the state of repose of the blanking line (phase I), the transistor T 3  is blocked, and the current from the constant current source T 5  flows entirely via the transistor T 4 , whose base at this time is at approximately 5.5 V. With the onset of the descending edge of the blanking pulse, in switching phase II, the voltage between the control electrodes of the two transistors T 3 , T 4  of the differential amplifier also drops abruptly from approximately +350 mV to approximately +70 mV; this voltage value is determined essentially by the dimensioning of the resistors R 1 , R 2  and R 9 . The capacitor C 1  then begins to charge, and the potential at its high point and hence at the base of the transistor T 3  drops further relative to the operating point of the transistor T 4 , initially approximately linearly to a negative value of approximately 220 mV. With the discharging of the capacitor C 1 , the current conduction in the two transistors of the differential amplifier begins to vary as well. Once the voltage value of -220 mV is reached, then the variation in the current conduction in the differential amplifier is concluded, and the current flows exclusively via the transistor T 3 . 
     The voltage at the high point of capacitor C 1  does continue to drop slowly down to approximately -500 mV in phase III. However, this further drop serves the purpose only of security of the new current flow distribution with regard to possible transistor data deviations. The cross-fading from current conduction by the transistor T 4  to transistor T 3  itself lasts about 0.3 msec. 
     During the cross-fading, the conductivity of the transistors T 1  and T 2  that form the reversing switch 2 drops in cosine fashion, resulting in the course indicated in FIG. 4 for the LF signal amplitudes at the LF output 3, which has only a slight interference spectrum. 
     At the end of the first cross-fading, the current, which has remained unchanged, flows entirely via the transistor T 3  and from its collector to ground via the resistor R 3  ; that is, the resistor R 3  experiences the same current constantly, so that the operating point, determined by this resistor, of the LF output 3 of the circuit arrangement during and after the cross-fading does not change, and hence the cross-fading causes no DC interference in the circuit, not shown, connected by alternating current to the output 3. 
     At the end of a blanking pulse, whose duration in FIG. 3 is assumed to be 0.7 ms (approximately 8 ms in actual practice), the reascending edge of the blanking pulse first, in phase IV, causes a voltage jump to approximately -220 mV, and from there, as a consequence of the recharging of the capacitor C 1 , a nearly linear rise to approximately +70 mV, and after that in phase V to approximately +350 mV, in an exponential course. At the end of the switching pulse as well, the current distribution in the differential amplifier accordingly changes, and this time the cross-fading is effected to current conduction through the transistor T 4 . 
     The fadeout of current conduction by the transistor T 3  at the onset of a blanking pulse and the fade back in at the end of the blanking pulse also averts a charge reversal of the capacitor C 2 , so that once again no disadvantageous interference effects are brought about. The longitudinal interruption of the signal also assures interference-free operation in the event of a charge reversal potential of C 2  imposed from outside. 
     
         ______________________________________1 = LF Input              C.sub.22 = Interruptor           T.sub.1, T.sub.23 = LF Output             R.sub.34 = Current Branch5 = Current Circuit of the Interruptor                     D.sub.1, D.sub.26 = Reversing Switch = Differential Circuit                     T.sub.3, T.sub.47 = Constant Current Source                     T.sub.5, R.sub.48 = Blanking Pulse Input  R.sub.10______________________________________