Abstract:
A plurality of receivers each having: an RF amplifier having an RFAMP input coupled to an antenna and having an RFAMP output; a capacitor having a CAP first side connected to the RFAMP output and a CAP second side; a passive mixer coupled to the RFAMP input, the CAP second side, and the output of a local oscillator phase shifter; an operational transconductor amplifier having an OTA input connected to the CAP second side and having an OTA output; a feedback resistor connected between the OTA input and the OTA output; a baseband transconductor having a BBGM input connected to the OTA input and a BBGM output; a cancelling transconductor having a CANCELLER output connected to the BBGM output and having a CANCELLER input; and an attenuator between the OTA output and the CANCELLER input, wherein the OTA output of each of the plurality of receivers are connected together.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of U.S. Provisional Patent Applications Nos. 62/288,852, filed Jan. 29, 2016, and 62/452,280, filed Jan. 30, 2017, each of which is hereby incorporated by reference herein in its entirety. 
     
    
     STATEMENT REGARDING GOVERNMENT FUNDED RESEARCH 
       [0002]    This invention was made with government support under FA8650-14-1-7414 awarded by DARPA. The government has certain rights in the invention. 
     
    
     BACKGROUND 
       [0003]    Multiple-antenna techniques, often referred to as multiple-input-multiple-output (MIMO) techniques, enable communication with increased spectral efficiency, either through linear beamforming which enhances signal-to-noise ratio (SNR), spatial multiplexing which enhances data rate through multiple parallel streams, or spatial diversity which enhances link reliability. 
         [0004]    MIMO systems that leverage multiplexing or diversity gains typically require space-time array signal processing that can practically only be implemented in the digital domain, and thus require digitization in each antenna signal path. A digital array also enables powerful digital array calibration. However, since the spatial processing is only performed in the digital domain, RF/analog spatial filtering is forsaken, leaving the RF/analog circuits and the data converters exposed to all the spatial content that is present at the antenna aperture, desired or not. In the presence of strong interference signals, such an architecture requires high instantaneous dynamic range from the RF/analog circuits and the data converters, leading to high power consumption and cost. 
         [0005]    Accordingly, new circuits and methods for spatio-spectral interference mitigation are desirable. 
       SUMMARY 
       [0006]    Circuits and methods for spatio-spectral interference mitigation are provided. 
         [0007]    In some embodiments, circuits for mitigating spatio-spectral interference in a multi-input, multi-output receiver are provided, the circuits comprising: a plurality of receivers, each comprising: a local oscillator generator having a plurality of phase outputs, including a first phase output and a second phase output; an antenna having an output; an RF amplifier having an input coupled to the output of the antenna and having an output; a first switch having a control input coupled to the first phase output, having a first side connected to the input of the RF amplifier, and having a second side; a first capacitor having a first side connected to the second side of the first switch and having a second side connected to the output of the RF amplifier; a second switch having a control input coupled to the second phase output, having a first side connected to the input of the RF amplifier, and having a second side; a second capacitor having a first side connected to the second side of the second switch and having a second side connected to the output of the RF amplifier; a first operational transconductance amplifier having an input connected to the second side of the first switch and having an output; a first feedback resistor having a first side connected to the input of the first operational transconductance amplifier and having a second side connected to the output of the first operational transconductance amplifier; a second operational transconductance amplifier having an input connected to the second side of the second switch and having an output; a second feedback resistor having a first side connected to the input of the second operational transconductance amplifier and having a second side connected to the output of the second operational transconductance amplifier; a first transconductor having an input connected to the input of the first operational transconductance amplifier and having an output; a second transconductor having an input connected to the input of the second operational transconductance amplifier and having an output; a first attenuator having an input connected to the output of the first operational transconductance amplifier and having an output; a third transconductor having an input connected to the output of the first attenuator and having an output coupled to the output of the first transconductor; a second attenuator having an input connected to the output of the second operational transconductance amplifier and having an output; and a fourth transconductor having an input connected to the output of the second attenuator and having an output coupled to the output of the second transconductor, wherein the outputs of the first operational transconductance amplifier in each of the plurality of receivers are connected together, and wherein the outputs of the second operational transconductance amplifier in each of the plurality of receivers are connected together. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  is an example of a schematic of a circuit for canceling spatial and spectral blockers in accordance with some embodiments. 
           [0009]      FIG. 2  is an example of a schematic of an integrated circuit having four single-element receivers for canceling spatial and spectral blockers in accordance with some embodiments. 
           [0010]      FIG. 3  is an example of a schematic of an example of a single-element receiver of the circuit of  FIG. 2  in accordance with some embodiments. 
           [0011]      FIG. 4  is an example of a local oscillator path of a single-element receiver of the circuit of  FIG. 3  in accordance with some embodiments. 
           [0012]      FIG. 5  is an example of a schematic of an operational transconductance amplifier that can be used in the circuit of  FIG. 1  in accordance with some embodiments. 
           [0013]      FIG. 6  is an example of a schematic of a transconductor that can be used in the circuit of  FIG. 1  in accordance with some embodiments. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    Circuits and methods for spatio-spectral interference mitigation are provided. 
         [0015]    Turning to  FIG. 1 , an example  100  of a circuit for reducing the impact of spatial blockers and spectral blockers on desired signals in a MIMO receiver in accordance with some embodiments is illustrated. 
         [0016]    As shown, circuit  100  includes N antennas  102 ,  104 , and  106 , N RF amplifiers  108 ,  110 , and  112 , N passive mixers and capacitors  114 ,  116 , and  118 , N phase shifters  120 ,  122 , and  124 , N operational transconductance amplifiers (OTAs)  126 ,  128 , and  130 , N feedback resistors R FB    132 ,  134 , and  136 , N baseband transconductors  138 ,  140 , and  142 , N attenuators  144 ,  146 , and  148 , N cancellation transconductors  150 ,  152 , and  154 , N analog-to-digital converters (ADCs)  164 ,  166 , and  168 , and a digital beamforming mechanism  170 . 
         [0017]    Each path from left to right in  FIG. 1  from an antenna to an ADC forms an element of circuit  100 . As shown, the signals at the outputs of OTAs  126 ,  128 , and  130  are connected together at node V BF . 
         [0018]    N antennas  102 ,  104 , and  106  can be implemented and arranged in any suitable manner, and any suitable number of antennas can be implemented, in some embodiments. For example, in some embodiments, the N antennas can be arranged in a uniform linear array with a λ/2 antenna spacing, where λ is wavelength in free space at the local oscillator (LO) frequency input to the mixer. 
         [0019]    N RF amplifiers  108 ,  110 , and  112  can be implemented in any suitable manner, and any suitable number of RF amplifiers can be implemented, in some embodiments. For example, in some embodiments, each RF amplifier can be implemented using a low noise amplifier (LNA). 
         [0020]    N passive mixers and capacitors  114 ,  116 , and  118  can be implemented in any suitable manner, and any suitable number of passive mixers and capacitors can be implemented, in some embodiments. For example, in some embodiments, the passive mixers can be implemented using switching transistors and capacitors can be implemented using a Metal-Insulator-Metal structure with a capacitance of 10 pF. 
         [0021]    N phase shifters  120 ,  122 , and  124  can be implemented in any suitable manner, and any suitable number of phase shifters can be implemented, in some embodiments. For example, in some embodiments, the phase shifters can be Cartesian phase shifters that are used in each LO path for notch steering. More particular examples of the phase shifters that can be used in some embodiments are shown in, and described in connection with,  FIG. 4 . 
         [0022]    N operational transconductance amplifiers (OTAs)  126 ,  128 , and  130  can be implemented in any suitable manner, and any suitable number of OTAs can be implemented, in some embodiments. 
         [0023]    N feedback resistors R  132 ,  134 , and  136  can be implemented in any suitable manner, and any suitable number of feedback resistors can be implemented, in some embodiments. For example, in some embodiments, feedback resistors can be 3.5 k ohm. 
         [0024]    Together, the pairs of OTAs  126 ,  128 , and  130  and feedback resistors R  132 ,  134 , and  136 , respectively, in each receiver path or element form a gyrator. 
         [0025]    N baseband transconductors g m    138 ,  140 , and  142  can be implemented in any suitable manner, and any suitable number of transconductors can be implemented, in some embodiments. 
         [0026]    N attenuators  144 ,  146 , and  148  can be implemented in any suitable manner, and any suitable number of attenuators can be implemented, in some embodiments. For example, in some embodiments the attenuators can be 7-bit digital attenuators that are controlled digitally by off-chip control signals from a hardware processor (not shown). 
         [0027]    N cancellation transconductors g m    150 ,  152 , and  154  can be implemented in any suitable manner, and any suitable number of transconductors can be implemented, in some embodiments. For example, in some embodiments, these cancellation transconductors can be identical to the baseband transconductors. 
         [0028]    N analog-to-digital converters (ADCs)  164 ,  166 , and  168  can be implemented in any suitable manner, and any suitable number of ADCs can be implemented, in some embodiments. 
         [0029]    Digital beamforming mechanism  170  can be implemented in any suitable manner, and any suitable number of digital beamforming mechanisms can be implemented, in some embodiments. 
         [0030]    During operation, when signals are equal in magnitude and in phase as they arrive from the broadside direction (θ=0°, or perpendicular to a line of MIMO antennas), the impedance seen at each signal input (R BB1,2 . . . N  in  FIG. 1 ) is low due to the high gain of OTAs  126 ,  128 , and  130 . When signals arrive at end-fire incidence (θ=+−/90°, or parallel to a line of MIMO antennas), the impedance seen at each signal input (R BB1,2 . . . N  in  FIG. 1 ) is equal to the resistor R FB  due to the AC ground at VBF. 
         [0031]    This impedance profile can be translated to RF at the antenna so that incidence-angle-dependent input reflection coefficients are provided that are reflective at broadside incidence angles, and matched to 50 Ω at off-broadside incidence angles. Thus, voltages from signals incident from broadside are suppressed at the inputs of antennas  102 ,  104 , and  106 , outputs of RF amplifiers  108 ,  110 , and  112 , and at the inputs of baseband transconductors gm  138 ,  140 , and  142 . 
         [0032]    In some embodiments, the notch formed at broadside incidence angles can be steered in any direction by phase-shifting the LO signals of mixers  114 ,  116 , and  118  relative to each other using phase shifters  120 ,  122 , and  124 . 
         [0033]    In addition, in some embodiments, tunable spectral filtering can be provided by tuning the LO signal frequency in any suitable manner, such as using a separate hardware processor. 
         [0034]    In some embodiments, the attenuators and the cancellation transconductors can be used to perform feedforward cancellation of residual interference and distortion. In order to do so, a beam formed in the notch direction at node V BF  is used as a replica of blockers in that direction. Next, the variable attenuators scale the replica to match the residue. The attenuators can be controlled in any suitable manner, such as using a separate hardware processor. Then, cancellation transconductors generate a residue current. Finally, the residue current is subtracted from the current generated by the baseband transconductors at nodes  156 ,  160 , and  162  to thereby cancel the residual interference and distortion. 
         [0035]    Turning to  FIG. 2 , an example  200  of an integrated circuit (IC) having four single-element receivers based on  FIG. 1  in accordance with some embodiments is shown. In some embodiments, these single-element receivers can operate over 0.1 to 1.7 GHz. In some embodiments, IC  200  can be implemented in any suitable technology, such as 65 nm CMOS. 
         [0036]    As illustrated in  FIG. 2 , IC  200  can include four single-element receivers  202 ,  204 ,  206 , and  208 . These receivers can be implemented in any suitable manner, and although only four receivers are shown in  FIG. 2 , any suitable number of receivers can be used. For example, in some embodiments, each of receivers  202 ,  204 ,  206 , and  208  can be implemented using example a receiver like receiver  300  of  FIG. 3 . 
         [0037]    As shown in  FIG. 2 , the signal V BF  can be connected to V BF  of other ICs  200  so that more that more than four single-element receivers can be connected together. 
         [0038]    As shown in  FIG. 3 , receiver  300  includes an RF amplifier  302 , four passive mixers  304 ,  306 ,  308 , and  310 , four capacitors  312 ,  314 ,  316 , and  318 , two operational transconductance amplifiers (OTAs)  320  and  322 , four feedback resistors  324 ,  326 ,  328 , and  330 , two baseband transconductors  332  and  334 , two attenuators  336  and  338 , two cancellation transconductors  340  and  342 , two variable gain amplifiers  344  and  346 , two buffers  348  and  350 , a divide-by-two local oscillator (LO) divider  352 , a phase shifter  354 , and a  25 % duty cycle generator  356 . 
         [0039]    RF amplifier  302  can be implemented in any suitable manner, and any suitable number of RF amplifiers can be implemented, in some embodiments. For example, in some embodiments, RF amplifier can be implemented using a low noise amplifier (LNA). 
         [0040]    Passive mixers  304 ,  306 ,  308 , and  310  can be implemented in any suitable manner, and any suitable number of passive mixers can be implemented, in some embodiments. For example, in some embodiments, the passive mixers can be implemented using switching transistors. 
         [0041]    Capacitors  312 ,  314 ,  316 , and  318  can be implemented in any suitable manner, and any suitable number of capacitors can be implemented, in some embodiments. For example, in some embodiments, capacitors can be implemented using Metal-Insulator-Metal structures with a capacitance of 10 pF. 
         [0042]    Operational transconductance amplifiers (OTAs)  320  and  322  can be implemented in any suitable manner, and any suitable number of OTAs can be implemented, in some embodiments. For example, in some embodiments, OTAs  320  and  322  can be implemented as OTA  500  as illustrated in  FIG. 5 . 
         [0043]    Feedback resistors  324 ,  326 ,  328 , and  330  can be implemented in any suitable manner, and any suitable number of feedback resistors can be implemented, in some embodiments. For example, in some embodiments, feedback resistors can be 3.5 k ohm. 
         [0044]    Together, the sets of OTAs  320  and  322  and feedback resistors R  324 ,  326 ,  328 , and  330  in each receiver path or element form a gyrator. 
         [0045]    Baseband transconductors  332  and  334  can be implemented in any suitable manner, and any suitable number of baseband transconductors can be implemented, in some embodiments. For example, in some embodiments, transconductors  332  and  334  can be implemented as transconductor  600  as illustrated in  FIG. 6 . 
         [0046]    Attenuators  336  and  338  can be implemented in any suitable manner, and any suitable number of attenuators can be implemented, in some embodiments. For example, in some embodiments, the attenuators can be 7-bit digital attenuators that are controlled digitally with control signals from a hardware processor, and can be implemented in transconductor  600  as illustrated in  FIG. 6 . 
         [0047]    Cancellation transconductors  340  and  342  can be implemented in any suitable manner, and any suitable number of cancellation transconductors can be implemented, in some embodiments. For example, in some embodiments, these cancellation OTAs can be identical to the baseband transconductors. 
         [0048]    Variable gain amplifiers (VGAs)  344  and  346  can be implemented in any suitable manner, and any suitable number of VGAs can be implemented, in some embodiments. For example, in some embodiments, the VGAs can have 30 dB range of gain control. 
         [0049]    Buffers  348  and  350  can be implemented in any suitable manner, and any suitable number of buffers can be implemented, in some embodiments. For example, in some embodiments, the buffers can be 50 ohm buffers. 
         [0050]    Divide-by-two local oscillator (LO) divider  352  can be implemented in any suitable manner, in some embodiments. 
         [0051]    Phase shifter  354  can be implemented in any suitable manner, and any suitable number of phase shifters can be implemented, in some embodiments. For example, in some embodiments, the phase shifter can be implemented as described below in connection with  FIG. 4 . 
         [0052]    25% duty cycle generator  356  can be implemented in any suitable manner, in some embodiments. 
         [0053]    Turning to  FIG. 4 , examples of circuits implementing divide-by-two local oscillator (LO) divider  352 , phase shifter  354 , and 25% duty cycle generator  356  of  FIG. 3  in accordance with some embodiments are shown. 
         [0054]    As illustrated,  FIG. 4  shows a divide-by-two circuit  402  that is driven by a local oscillator (LO) signal (that is twice the desired LO signal) and that drives resistors  404  and variable capacitors  406  to produce signals I-Path+, I-Path−, Q-Path+, and Q-Path−. Together the resistors and variable capacitors provide a local oscillator slew rate control filter that partially removes harmonic component. 
         [0055]    As also illustrated, an I-path phase shifter  408  and a Q-path phase shifter  410  can each be formed from banks of parallel, selectable transconductance cells  412  and  414  and resistors  416  and  418 . The banks can have any suitable number, such as six, bits of control. In some embodiments, the cells  412  can each have the same transconductance value and the cells  414  can each of the same transconductance value. Phase shifter  408  is driven by signals I-Path+ and I-Path− and produces signals IPS+ and IPS−. Phase shifter  410  is driven by signals Q-Path+ and Q-Path− and produces signals QPS+ and QPS−. 
         [0056]    As further illustrated, the signals IPS+, IPS−, QPS+, and QPS− are provided to a 25% duty-cycle generator  420  that generators signals φ 1 , φ 2 , φ 3 , φ 4 , which are 25% duty cycle versions of IPS+, IPS−, QPS+, and QPS−, respectively, so that signals φ 1 , φ 2 , φ 3 , φ 4  do not overlap. Signals φ 1 , φ 2 , φ 3 , φ 4  can then be used to control switches  304 ,  306 ,  308 , and  310  ( FIG. 3 ) of the passive mixers. 
         [0057]    Although the invention has been described and illustrated in the foregoing illustrative embodiments, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of embodiment of the invention can be made without departing from the spirit and scope of the invention, which is limited only by the claims that follow. Features of the disclosed embodiments can be combined and rearranged in various ways.