Abstract:
A bandgap voltage reference circuit is provided with: a feedback circuitry, first and second PN junction elements and first and second resistor elements. The feedback circuitry provides a feedback so as to reduce a voltage between first and second nodes. The first PN junction element is connected between the first node and a ground terminal so as to allow a first current from the first node to the ground terminal to flow in a forward direction of a PN junction. The second PN junction element is connected between the first node and a ground terminal so as to allow a first current from the first node to the ground terminal to flow in a forward direction of a PN junction. The first resistor element is connected between the first node and the first PN junction element, and a second resistor element is connected between the second node and the second PN junction element.

Description:
INCORPORATION BY REFERENCE 
       [0001]    This application claims the benefit of priority based on Japanese Patent Application No. 2010-011113, filed on Jan. 21, 2010, the disclosure of which is incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention is related to a voltage reference circuit, more particularly, to a bandgap voltage reference circuit which is configured to generate a reference voltage stabilized against the temperature, making use of characteristics of a current flowing through a PN junction. 
         [0004]    2. Description of the Related Art 
         [0005]    Due to the increase in the scale of the LSI (large scale integrated circuit), mixed analog-digital LSIs have been recently showing an increasing demand. Conventionally, a power supply for an analog circuit requiring high accuracy, such as a PLL circuits and a bandgap voltage reference circuit, is usually separated from a power supply for a logic circuit in order to avoid power supply noise. In the viewpoint of chip cost reduction, however, it is preferable that the power supply is shared by an analog circuit and a logic circuit. As a result, there has been an increasing demand for an analog circuit which is tolerant against power supply noise. 
         [0006]      FIG. 1  is a circuit diagram showing an exemplary schematic configuration of a commonly-used bandgap voltage reference circuit. The bandgap voltage reference circuit of  FIG. 1  is provided with an operational amplifier AMP, bipolar transistors Q 1  and Q 2,  and resistor elements R 1 , R 2  and R 20 . The bipolar transistors Q 1  and Q 2  each have a commonly-connected collector and base, operating as a diode. The emitter of the bipolar transistor Q 1  is directly connected to a node N 1  and the emitter of the bipolar transistor Q 2  is connected to a node N 2  through the resistor R 20 . The resistor element R 1  is connected between the node N 1  and the output of the operational amplifier AMP and the resistor element R 2 . The nodes N 1  and N 2  are connected to the non-inverting and inverting inputs of the operational amplifier AMP, respectively, and thereby the output voltage of the operational amplifier AMP is controlled to reduce the voltage between the nodes N 1  and N 2  to zero. The output voltage of the operational amplifier AMP is used as a resultant reference voltage V REF  and therefore the bandgap voltage reference circuit of  FIG. 1  is configured to stabilize the reference voltage V REF  to against the temperature. 
         [0007]    The circuit configuration of  FIG. 1 , however, undesirably suffers from deterioration in the accuracy of the reference voltage V REF  due to the power supply noise. The cause of such deterioration is described in the following. 
         [0008]    In a case that the currents through the resistor elements R 1  and R 2  are identical due to the same resistance of the resistor elements R 1  and R 2  and the ratio of the area of the emitter of the bipolar transistor Q 2  to that of the bipolar transistor Q 1  is 1:α, the reference voltage V REF  is expressed by the following expression: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       REF 
                     
                     = 
                     
                       
                         V 
                         EB 
                       
                       + 
                       
                         
                           
                             R 
                             2 
                           
                           
                             R 
                             20 
                           
                         
                          
                         
                           ( 
                           
                             
                               
                                 kT 
                                 q 
                               
                                
                               ln 
                                
                               
                                   
                               
                                
                               α 
                             
                             + 
                             
                               V 
                               OS 
                             
                           
                           ) 
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where V EB  is the emitter-base voltage of the bipolar transistors Q 1  and Q 2  (which are used as diodes); k is the Boltzmann constant; T is the absolute temperature; q is the elementary charge; and V OS  is the offset voltage of the operational amplifier AMP. 
         [0009]    As is understood from Expression (1), the reference voltage V REF  depends on the offset voltage V OS  of the operational amplifier AMP, and the offset voltage V OS  causes a significant influence on the accuracy of the reference voltage V REF  as discussed below: The temperature dependence of the reference voltage V REF  is expressed by the following Expression (2), which is obtained by partial differentiation of Expression (1) with respect to the absolute temperature T: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         ∂ 
                         
                           V 
                           REF 
                         
                       
                       
                         ∂ 
                         T 
                       
                     
                     = 
                     
                       
                         
                           ∂ 
                           
                             V 
                             EB 
                           
                         
                         
                           ∂ 
                           T 
                         
                       
                       + 
                       
                         
                           
                             R 
                             2 
                           
                           
                             R 
                             20 
                           
                         
                          
                         
                           ( 
                           
                             
                               k 
                               q 
                             
                              
                             ln 
                              
                             
                                 
                             
                              
                             α 
                           
                           ) 
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where ∂V OS /∂T is approximated as zero (this approximation is reasonable in actual use). Referring to Expression (2), ∂v OS /∂T is about −2.0 (mV/k), and k/q is about 0.086 (mV/k), when silicon transistors are used as the bipolar transistors Q 1  and Q 2 , that is, PN junctions of silicon are used. For α=8, for example, the ratio R 2 /R 20  required to adjust ∂v OS /∂T in Expression (2) to zero is 11.19. In this case, the reference voltage V REF  experiences a change of ten or more times of a change in the offset voltage V OS , as is understood from Expression (1). Accordingly, the reduction of the offset voltage V OS  of the operational amplifier AMP is important for improvement in the accuracy of the bandgap voltage reference circuit. 
         [0010]    In the circuit configuration shown in  FIG. 1 , however, the power supply noise undesirably increases the effective offset voltage V OS  of the operational amplifier AMP, deteriorating the accuracy of the bandgap voltage reference circuit. In the bandgap voltage reference circuit shown in  FIG. 1 , the output voltage of the operational amplifier AMP (that is, the reference voltage V REF ) is influenced by the power supply noise, because the output voltage is generated on the power supply voltage VDD. When the noises transmitted to the differential inputs of the operational amplifier AMP are different in the noise level between Paths  1  and  2  shown in  FIG. 1 , the difference between the voltages V 1  and V 2  on the non-inverting and inverting inputs is increased and this results in that the effective offset voltage V OS  is increased, causing the deterioration of the accuracy of the reference voltage V REF . 
         [0011]    In detail, a small signal equivalent resistance R Di  of a PN junction in a low frequency region (or the small signal resistance of the emitter-base junctions of the bipolar transistors Q 1  and Q 2 ) is expressed by the following expression: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       R 
                       Di 
                     
                     = 
                     
                       
                         
                           ( 
                           
                             
                               ∂ 
                               
                                 I 
                                 Di 
                               
                             
                             
                               ∂ 
                               
                                 V 
                                 EB 
                               
                             
                           
                           ) 
                         
                         
                           - 
                           1 
                         
                       
                       = 
                       
                         
                           kT 
                           q 
                         
                         · 
                         
                           1 
                           
                             I 
                             Di 
                           
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where I Di  is the current flowing through the PN junction. The ac signal component v 1  transmitted to the non-inverting input of the operational amplifier AMP through Path  1  and the ac signal component v 2  transmitted to the inverting input of the operational amplifier AMP through Path  2  are given with the ac signal component v REF  of the reference voltage V REF  as the following expressions, respectively: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       v 
                       1 
                     
                     = 
                     
                       
                         
                           R 
                           Di 
                         
                         
                           
                             R 
                             Di 
                           
                           + 
                           
                             R 
                             1 
                           
                         
                       
                       · 
                       
                         v 
                         REF 
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
             
               
                 
                   
                     v 
                     2 
                   
                   = 
                   
                     
                       
                         
                           R 
                           Di 
                         
                         + 
                         
                           R 
                           20 
                         
                       
                       
                         
                           R 
                           Di 
                         
                         + 
                         
                           R 
                           20 
                         
                         + 
                         
                           R 
                           2 
                         
                       
                     
                     · 
                     
                       
                         v 
                         REF 
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0012]    The ratio of the ac signal components fed to the differential inputs of the operational amplifier AMP through Paths  1  and  2  are obtained by the divisions of right sides and left sides of Expressions (4) and (5), respectively, as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       v 
                       2 
                     
                     
                       v 
                       1 
                     
                   
                   = 
                   
                     1 
                     + 
                     
                       
                         
                           
                             R 
                             20 
                           
                           · 
                           
                             R 
                             1 
                           
                         
                         
                           
                             R 
                             Di 
                           
                            
                           
                             ( 
                             
                               
                                 R 
                                 Di 
                               
                               + 
                               
                                 R 
                                 20 
                               
                               + 
                               
                                 R 
                                 2 
                               
                             
                             ) 
                           
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0013]    The difference between the ac signal components given as Expression (6) appears on the differential inputs of the operational amplifier AMP through the mechanism described above. The ac signal components are virtually superposed onto the offset voltage V OS  as the dc offset component of the operation amplifier AMP, because of the response characteristics of the operational amplifier AMP and the parasitic capacitances therein. 
         [0014]    Japanese Patent Application Publication No. P2007-305010 A discloses a circuit configuration which cuts off the power supply noise superposed onto the power supply voltage VDD to thereby improve the accuracy of the reference voltage V REF , avoiding the deterioration caused by such mechanism. In the circuit configuration disclosed in this publication, a constant current is fed to a bandgap voltage reference circuit by a constant current supply configured as a current mirror, to thereby reduce the influence of the noise superposed onto the power supply voltage VDD. 
         [0015]    The conventional circuit disclosed in this publication, however, undesirably suffers from an increase in the current consumption, since the conventional circuit is added with an additional current path which does not pass through the bandgap voltage reference circuit. In addition, the conventional circuit suffers from a drawback that the actual operation voltage limit is increased above the intrinsic operation voltage limit of the bandgap voltage reference circuit, due to the voltage drop between the source and drain of a PMOS transistor of the current mirror of the constant current supply. 
         [0016]    The suppression of the influence of the noise may be achieved by a low pass filter including a resistor element and a capacitor element; however, the use of a capacitor element undesirably causes an increase in the circuit size and the use of a resistor element undesirably increases the operation voltage limit due to the voltage drop. 
         [0017]    The person skilled in the art would therefore appreciate that one desirable measure is a circuit design in which the bandgap voltage reference circuit itself is configured to be tolerant against the power supply noise. 
       SUMMARY 
       [0018]    In an aspect of the present invention, a bandgap voltage reference circuit is provided with: a feedback circuitry providing a feedback so as to reduce a voltage between first and second nodes; a first PN junction element connected between said first node and a ground terminal so as to allow a first current from said first node to the ground terminal to flow in a forward direction of a PN junction; a second PN junction element connected between said first node and a ground terminal so as to allow a first current from said first node to the ground terminal to flow in a forward direction of a PN junction; a first resistor element connected between said first node and said first PN junction element; and a second resistor element connected between said second node and said second PN junction element. 
         [0019]    The bandgap voltage reference circuit according to the present invention can generate a reference voltage stabilized against power supply noise. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
           [0021]      FIG. 1  is a circuit diagram showing an exemplary configuration of a commonly-used bandgap voltage reference circuit; 
           [0022]      FIG. 2  is a circuit diagram showing an exemplary configuration of a bandgap voltage reference circuit in one embodiment of the present invention; 
           [0023]      FIG. 3  is a circuit diagram showing an exemplary configuration of a bandgap voltage reference circuit in another embodiment of the present invention; 
           [0024]      FIG. 4  is a circuit diagram showing an exemplary configuration of a bandgap voltage reference circuit in still another embodiment of the present invention; and 
           [0025]      FIG. 5  is a block diagram showing an exemplary configuration of an integrated circuit incorporating a bandgap voltage reference circuit of any of the embodiments of the present invention. 
       
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0026]    The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
         [0027]      FIG. 2  is a circuit diagram showing an exemplary configuration of a bandgap voltage reference circuit in one embodiment of the present invention. The bandgap voltage reference circuit shown in  FIG. 2  is provided with an operational amplifier AMP, bipolar transistors Q 1 , Q 2  and resistor elements R 11 , R 21 , R 12 , R 22  and R 20 . As is the case of the bandgap voltage reference circuit shown in  FIG. 1 , the bipolar transistors Q 1  and Q 2  each have a commonly connected collector and base, operating as a diode. The resistor element R 1  is connected between a node N 1  and the output of the operational amplifier AMP and the resistor element R 2  is connected between a node N 2  and the output of the operational amplifier AMP. The nodes N 1  and N 2  are connected to non-inverting and inverting inputs of the operational amplifier AMP, respectively, and the output voltage of the operational amplifier AMP, that is, the voltage reference V REF  is controlled so as to reduce the voltage between the nodes N 1  and N 2  to zero. In the bandgap voltage reference circuit of  FIG. 2 , the resistor element R 12  is inserted between the emitter of the bipolar transistor Q 1  and the node N 1 , and the resistor elements R 22  and R 20  are inserted between the emitter of the bipolar transistor Q 2  and the node N 2 . It should be noted here that the resistor elements R 12  and R 22  have the same resistance. The bandgap voltage reference circuit configuration of this embodiment generates the same reference voltage V REF  as the bandgap voltage reference circuit shown in  FIG. 1 , when the sum of the resistance values of the resistor elements provided between the output of the operational amplifier AMP in Path  1  is identical to the resistance value of the resistor element R 1  of the bandgap voltage reference circuit of  FIG. 1  and the sum of the resistance values of the resistor elements provided between the output of the operational amplifier AMP in Path  2  is identical to the resistance value of the resistor element R 2 . That is, the same reference voltage V REF  is generated in the circuit configurations shown in  FIGS. 1 and 2 , when R 1 =R 11 +R 12  and R 2 =R 21 +R 22 . In other words, the bandgap voltage reference circuit shown in  FIG. 2  is configured so that the non-inverting and inverting inputs of the operational amplifier AMP are disconnected from the nodes N 10  and N 20 , respectively, and connected to the nodes N 1  and N 2 , respectively. 
         [0028]    As discussed with reference to Expression (6), the influence of the power supply noise on the offset voltage V OS  is suppressed when the ratio of the ac signal components of the voltages inputted to the non-inverting and inverting inputs of the operational amplifier AMP is close to one. In the circuit configuration of  FIG. 2 , the ratio of the ac signal components is expressed by the following Expression (7): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         ( 
                         
                           
                             v 
                             2 
                           
                           
                             v 
                             1 
                           
                         
                         ) 
                       
                       ′ 
                     
                     = 
                     
                       1 
                       + 
                       
                         
                           
                             R 
                             20 
                           
                           · 
                           
                             R 
                             11 
                           
                         
                         
                           
                             ( 
                             
                               
                                 R 
                                 Di 
                               
                               + 
                               
                                 R 
                                 12 
                               
                             
                             ) 
                           
                            
                           
                             ( 
                             
                               
                                 R 
                                 Di 
                               
                               + 
                               
                                 R 
                                 20 
                               
                               + 
                               
                                 R 
                                 21 
                               
                               + 
                               
                                 R 
                                 22 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where R 12 =R 22 . 
         [0029]    In the following, Expressions (6) and (7) are rewritten so that the resistor elements of the same resistance value are denoted by the same notation. Expressions (6) and (7) can be rewritten with R Di , R 2 , R 20  and R 22  as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       ( 
                       
                         
                           v 
                           2 
                         
                         
                           v 
                           1 
                         
                       
                       ) 
                     
                     = 
                     
                       1 
                       + 
                       
                         
                           
                             R 
                             20 
                           
                           
                             
                               R 
                               Di 
                             
                             + 
                             
                               R 
                               20 
                             
                             + 
                             
                               R 
                               2 
                             
                           
                         
                         · 
                         
                           
                             R 
                             2 
                           
                           
                             R 
                             Di 
                           
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   
                     ( 
                     6 
                     ) 
                   
                   ′ 
                 
               
             
             
               
                 
                   
                     
                       
                         ( 
                         
                           
                             v 
                             2 
                           
                           
                             v 
                             1 
                           
                         
                         ) 
                       
                       ′ 
                     
                     = 
                     
                       1 
                       + 
                       
                         
                           
                             R 
                             20 
                           
                           
                             
                               R 
                               Di 
                             
                             + 
                             
                               R 
                               20 
                             
                             + 
                             
                               R 
                               2 
                             
                           
                         
                         · 
                         
                           
                             
                               R 
                               2 
                             
                             - 
                             
                               R 
                               22 
                             
                           
                           
                             
                               R 
                               Di 
                             
                             + 
                             
                               R 
                               22 
                             
                           
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   
                     ( 
                     7 
                     ) 
                   
                   ′ 
                 
               
             
           
         
       
     
         [0000]    since it holds: 
         [0030]    R 1 =R 11 +R 12 , 
         [0031]    R 2 =R 21 +R 22 , 
         [0032]    R 1 =R 2 , 
         [0033]    R 11 =R 21 , and 
         [0034]    R 12 =R 22 , 
         [0000]    as described above. The second term of Expression (7)′ is smaller than that of Expression (6)′, since it holds: 
         [0000]        R   Di   &lt;RDi+R 22, and   (8)
 
         [0000]        R   2   &gt;R   2   −R   22 ,   (9)
 
         [0000]    as is understood from comparisons of the numerators and denominators of the second terms of Expressions (6)′ and (7). Therefore, it holds: 
         [0000]    
       
         
           
             
               
                 
                   
                     ( 
                     
                       
                         v 
                         2 
                       
                       
                         v 
                         1 
                       
                     
                     ) 
                   
                   &gt; 
                   
                     
                       
                         ( 
                         
                           
                             v 
                             2 
                           
                           
                             v 
                             1 
                           
                         
                         ) 
                       
                       ′ 
                     
                      
                     
                         
                     
                      
                     
                       
                         ( 
                         
                           &gt; 
                           1 
                         
                         ) 
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
         [0035]    As thus discussed, the circuit configuration of  FIG. 2  effectively suppresses the influence of the power supply noise on the offset voltage V OS , reducing the ac signal components of the voltages inputted to the non-inverting and inverting inputs of the operational amplifier AMP. 
         [0036]    An increased resistance of the resistor element R 22  effectively enhances the effect of the suppression of the influence of the power supply noise. According to the second term of Expression (7)′, an increase in R 22  results in a decrease in the numerator and an increase in the denominator, making (v 2 /v 1 )′ closer to one. It should be noted here that R 22 &lt;R 2 , because R 2 =R 21 +R 22 . 
         [0037]    Although an increased resistance of the resistor element R 22  effectively enhances the effect of the suppression of the influence of the power supply noise as thus discussed, the increase in R 22  also increases the offset voltage V OS  caused by the feedback operation of the operational amplifier AMP. The increased offset voltage V OS ′ is given by Expression (11) which is expressed only with R 2 , R 20  and R 22  as is the case of Expression (7)′: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     OS 
                     ′ 
                   
                   = 
                   
                     
                       
                         ( 
                         
                           1 
                           + 
                           
                             
                               R 
                               22 
                             
                             
                               R 
                               21 
                             
                           
                         
                         ) 
                       
                       · 
                       
                         V 
                         OS 
                       
                     
                     = 
                     
                       
                         ( 
                         
                           1 
                           + 
                           
                             
                               R 
                               22 
                             
                             
                               
                                 R 
                                 2 
                               
                               - 
                               
                                 R 
                                 22 
                               
                             
                           
                         
                         ) 
                       
                       · 
                       
                         
                           V 
                           OS 
                         
                         . 
                       
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Expression (11) implies that, when the effect of the suppression of the accuracy deterioration caused by the power supply noise is enhanced, this undesirably causes an increase in offset voltage of the operational amplifier AMP. 
         [0038]    As thus discussed, the increase in R 22  effectively reduces the difference of the ac signal components caused by the power supply noise, while undesirably making the influence of the offset voltage of the operational amplifier worse. This implies that an appropriate value of the resistance of the resistor element R 22  should be determined on the basis of the comparison between the effects of the power supply noise and the amplifier offset. 
         [0039]    Although the resistor elements R 22  and R 20  are shown as separate elements in  FIG. 2  for understanding of the circuit operation, the resistor elements R 22  and R 20  may be integrated as a single resistor element in an actual integration. When the single resistor element is denoted by symbol R x , the circuit topology shown in  FIG. 2  can be understood as a circuit topology in which the resistor element R 12  is inserted between the emitter of the bipolar transistor Q 1  and the node N 1 , and the resistor element R x  is inserted between the emitter of the bipolar transistor Q 2  and the node N 2 . 
         [0040]    The circuit configuration in which resistor elements are inserted between the node N 1  and the emitter of the bipolar transistor Q 1  and between the node N 2  and the emitter of the bipolar transistor Q 2  to reduce the variations of the reference voltage V REF  due to the power supply noise as shown in  FIG. 2  is applicable to any bandgap voltage reference circuit which is configured to reduce the voltage between the nodes N 1  and N 2  to zero through feedback control. 
         [0041]      FIGS. 3 and 4  are circuit diagram showing exemplary configurations of bandgap voltage reference circuits in alternative embodiments of the present invention. The bandgap voltage reference circuit of  FIG. 3  is provided with PMOS transistors MP 1  to MP 3 , NMOS transistors MN 1  and MN 2 , resistor elements R 31  to R 33 , R 20  and bipolar transistors Q 1  to Q 3 . It should be noted here that the resistor element R 31  provided between the emitter of the bipolar transistor Q 1  and the node N 1  has the same resistance as the resistor element R 32  provided between the emitter of the bipolar transistor Q 2  and the node N 2 . 
         [0042]    The PMOS transistors MP 1  and MP 2  form a first current mirror connected to a power supply terminal fed with the power supply voltage VDD. More specifically, PMOS transistors MP 1  and MP 2  have sources commonly connected to the power supply terminal fed with the power supply voltage VDD and gates commonly connected to the drain of the PMOS transistor MP 2 . 
         [0043]    The NMOS transistors MN 1  and MN 2  form a second current mirror connected to the first current mirror. More specifically, the NMOS transistors MN 1  and MN 2  have drains connected to the drains of the PMOS transistors MP 1  and MP 2 , respectively, and gates commonly connected to the drain of the NMOS transistor MN 1 . The sources of the NMOS transistors MN 1  and MN 2  are connected to the node N 1  and N 2 , respectively. 
         [0044]    In the circuit configuration shown in  FIG. 3 , the first and second current mirrors provide feedback control so as to reduce the voltage between the node N 1  and N 2  to zero. 
         [0045]    The PMOS transistor MP 3 , the bipolar transistor Q 3  and the resistor element R 33  function as an output stage which outputs the reference voltage V REF  in response to the voltage level on the commonly-connected gates of the PMOS transistors MP 1  and MP 2 . In detail, the PMOS transistor MP 3  has a gate connected to the gate of the PMOS transistor MP 2  and a source connected to the power supply terminal. The bipolar transistor Q 3  has a commonly connected collector and base, operating as a diode. The resistor element R 33  is connected between the drain of the PMOS transistor MP 3  and the emitter of the bipolar transistor Q 3 . The reference voltage V REF  is outputted from the drain of the PMOS transistor MP 3 . 
         [0046]    The circuit configuration shown in  FIG. 3  also reduces ac signal components transmitted to the node N 1  and N 2  resulting from the power supply noise to thereby suppress the deterioration of the accuracy of the reference voltage V REF , since resistor elements are inserted between the node N 1  and the emitter of the bipolar transistor Q 1  and between the node N 2  and the emitter of the bipolar transistor Q 2 . 
         [0047]    An increased resistance of the resistor elements R 31  and R 32  (which have the same resistance) effectively suppresses the influence of the power supply noise, also in the circuit configuration  FIG. 3 . It should be noted that the increase in the resistance of the resistor elements R 31  and R 32  does not cause an increase in the influence of the offset voltage as in the circuit configuration shown in  FIG. 2 ; however, the increase in the resistance of the resistor elements R 31  and R 32  undesirably increases the voltage levels on the nodes N 1  and N 2 , resulting in deterioration of the operation margin of the power supply voltage VDD. The increase in the resistance of the resistor elements R 31  and R 32  also causes an undesired increase in the area thereof. This implies that an appropriate resistance of the resistor elements R 31  and R 32  should be determined on the basis of the comparison between the effect of the power supply noise, the operation margin of the power supply voltage VDD and the area of the resistor elements R 31  and R 32 . 
         [0048]    In the circuit configuration shown in  FIG. 3 , the resistor elements R 32  and R 20  may be integrated as a single resistor element in an actual integration. 
         [0049]    On the other hand, the bandgap reference circuit shown in  FIG. 4  is provided with PMOS transistors MP 1  to MP 3 , resistor elements R 41  to R 43 , R 20 , an operational amplifier AMP, and bipolar transistors Q 1  to Q 3.  The resistor element R 41 , which is connected between the emitter of the bipolar transistor Q 1  and the node N 1 , has the same resistance as the resistor element R 42 , which is connected between the emitter of the bipolar transistor Q 2  and the node N 2 . The PMOS transistors MP 1  and MP 2  have sources commonly connected to a power supply terminal, drains connected to the node N 1  and N 2 , respectively, and gates commonly connected to the operational amplifier AMP. In the circuit configuration shown in  FIG. 4 , the operational amplifier AMP and the PMOS transistors MP 1  and MP 2  provide feedback control to reduce the voltage between the node N 1  and N 2  to zero. The PMOS transistor MP 3 , the bipolar transistor Q 3  and the resistor element R 43  function as an output stage which outputs the reference voltage V REF  in response to the output level of the operational amplifier AMP. 
         [0050]    The circuit configuration shown in  FIG. 4  also reduces ac signal components transmitted to the node N 1  and N 2  resulting from the power supply noise to thereby suppress the deterioration of the accuracy of the reference voltage V REF , since resistor elements are inserted between the node N 1  and the emitter of the bipolar transistor Q 1  and between the node N 2  and the emitter of the bipolar transistor Q 2 . 
         [0051]    An increased resistance of the resistor elements R 41  and R 42  (which have the same resistance) effectively suppresses the influence of the power supply noise, also in the circuit configuration  FIG. 4 . It should be noted that the increase in the resistance of the resistor elements R 41  and R 42  does not cause an increase in the influence of the offset voltage as in the circuit configuration shown in  FIG. 2 ; however, the increase in the resistance of the resistor elements R 41  and R 42  undesirably increases the voltage levels on the nodes N 1  and N 2 , resulting in deterioration of the operation margin of the power supply voltage VDD. The increase in the resistance of the resistor elements R 41  and R 42  also causes an undesired increase in the area thereof. This implies that an appropriate resistance of the resistor elements R 41  and R 42  should be determined on the basis of the comparison between the effect of the power supply noise, the operation margin of the power supply voltage VDD and the area of the resistor elements R 41  and R 42 . 
         [0052]    In the circuit configuration shown in  FIG. 4 , the resistor elements R 42  and R 20  may be integrated as a single resistor element in an actual integration. 
         [0053]    It is especially preferable that a bandgap voltage reference circuit according to the present invention (for example, those shown in  FIGS. 2 to 4 ) is applied to a circuit which receives a boosted power supply voltage generated by a booster circuit. It is difficult to operate a bandgap voltage reference circuit in a low voltage device, such as a device with a single 1.0V power supply. In such device, a boosted power supply voltage (for example, a power supply voltage higher than 1.0V) is generated with a booster circuit and a bandgap voltage reference circuit is operated on the boosted power supply voltage. The use of a bandgap voltage reference circuit according to the present invention is quite advantageous in such case, since the boosted power supply voltage experiences significantly large noise. 
         [0054]      FIG. 5  is a block diagram showing an exemplary configuration of an integrated circuit in which a bandgap voltage reference circuit according to the present invention is used in combination with a boosting power supply. The integrated circuit shown in  FIG. 5  is provided with a booster circuit  11  and a bandgap voltage reference circuit according to the present invention (denoted by numeral  12 ). A charge pump may be used as the booster circuit  11 , for example. A boosted power supply voltage VDD 2  is generated on a boosted power supply line by the booster circuit  11  and fed to the bandgap voltage reference circuit  12 . The bandgap voltage reference circuit  12  may be configured in accordance with any of the circuit configurations shown in  FIGS. 2 to 4 . A power supply capacitor C 1  is provided between the boosted power supply line and a ground line. 
         [0055]    Large power supply noise generated by the booster circuit  11  necessitates a measure, for example, an increase in the capacitance of the power supply capacitor C 1 . When the power supply noise is suppressed by the technique disclosed in the above-mentioned Japanese Patent Application Publication No. P2007-305010 A, for example, the current consumption is increased and this necessitates an enhancement of the drive capacity of the booster circuit  11 , that is, the element areas of the circuit elements thereof to compensate the current consumption. The technique disclosed in this application also causes a higher operation voltage limit, necessitating an increase in the boosted power supply voltage VDD2 and this undesirably increases the element areas of the circuit elements of the booster circuit 11. 
         [0056]    The use of any of the bandgap voltage reference circuits of the above-described embodiments, which are configured to be tolerant against the power supply noise, effectively suppresses the increase in the element areas of the circuit elements of the booster circuit  11  and allows reducing the element area of the power supply capacitor C 1 , if it is used for the suppression of the power supply noise. As thus discussed, the present invention offers a significant advantage in reduction of the element areas, especially when the present invention is implemented in combination with a boosting power supply. 
         [0057]    It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope of the invention.