Abstract:
A metal oxide semiconductor field effect transistor (MOSFET) amplifier with dynamically biased cascode output circuitry in which the biasing of the cascode output circuitry dynamically tracks one or more other internal amplifier bias voltages such that operation of each transistor in the input signal circuitry is maintained in a state of saturation.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to metal oxide semiconductor field effect transistor (MOSFET) amplifiers with cascode outputs, and in particular, MOSFET amplifiers with cascode outputs biased to maintain operation of their driver transistors in states of saturation. 
     2. Description of the Related Art 
     Many amplifier circuits using MOSFETs (P-type or N-type, or both) are increasingly relying upon the use of cascode output devices for maintaining or increasing the amplifier output impedance. This has become increasingly important as transistor sizes, particularly MOSFET channel lengths, become smaller with increased integrated circuit densities. This is true for current mirror circuits (e.g., as discussed in more detail in U.S. Pat. No. 4,550,284, the disclosure of which is incorporated herein by reference) as well as signal amplifiers. 
     One type of signal amplifier relying upon cascode output transistors is that in which the signal to be amplified or buffered is an AC signal centered about a DC baseline, or common mode, voltage. Such an amplifier, whether differential or single-ended, often relies upon the use of a current mirror circuit for providing the amplifier biasing current to the transistor or transistors responsible for amplifying the incoming signal. Following such transistor or transistors, is the cascode output circuitry responsible for maintaining or increasing the output impedance. 
     Two difficulties are often encountered in biasing such circuitry. One difficulty involves the biasing of the current mirror providing the amplifier biasing current. Depending upon the magnitude and stability of the DC power supply voltage, the biasing of the current mirror circuitry can vary, thereby causing the amplifier biasing current to vary as well. A second difficulty concerns the biasing of the cascode output circuitry. Such biasing is usually done by applying a fixed voltage relative to the power supply voltage. However, while such bias voltage may remain constant, the baseline, or common mode, voltage associated with the input signal may vary, thereby preventing the input transistors from operating in true states of saturation, particularly over PVT (i.e., variations in device fabrication Processing, power supply Voltage and operating Temperature). 
     SUMMARY OF THE INVENTION 
     In accordance with the presently claimed invention, a metal oxide semiconductor field effect transistor (MOSFET) amplifier includes dynamically biased cascode output circuitry in which the biasing of the cascode output circuitry dynamically tracks one or more other internal amplifier bias voltages such that operation of each transistor in the input signal circuitry is maintained in a state of saturation. 
     In accordance with one embodiment of the presently claimed invention, a metal oxide semiconductor field effect transistor (MOSFET) amplifier with dynamically biased cascode output circuitry includes power supply terminals, telescopic cascode amplifier circuitry, voltage replication circuitry and voltage translation circuitry. The power supply terminals convey first and second voltages defining a power supply voltage. The telescopic cascode amplifier circuitry, coupled between the power supply terminals, responds to reception of a current source bias voltage intermediate the first and second voltages, an input signal centered about an input baseline voltage intermediate the first and current source bias voltages, and at least one cascode bias voltage intermediate the first and input baseline voltages by providing a first internal bias voltage intermediate the current source bias and input baseline voltages, a second internal bias voltage intermediate the input baseline and at least one cascode bias voltages, and an output signal corresponding to the input signal and centered about an output baseline voltage intermediate the first and cascode bias voltages. The voltage replication circuitry, coupled to the telescopic cascode amplifier circuitry, responds to reception of the input baseline voltage and a first bias current by providing the current source bias voltage and a first replica bias voltage substantially equal to the first internal bias voltage. The voltage translation circuitry, coupled to the voltage replication circuitry and the telescopic cascode amplifier circuitry, responds to reception of the current source bias voltage, the first replica bias voltage and a second bias current related to the first bias current by providing a first one of the at least one cascode bias voltage. 
     In accordance with another embodiment of the presently claimed invention, such MOSFET amplifier with dynamically biased cascode output circuitry further includes additional voltage replication circuitry and additional voltage translation circuitry. The additional voltage replication circuitry, coupled to the first voltage translation circuitry, responds to reception of the first one of the at least one cascode bias voltage and a third bias current related to the first bias current by providing a current mirror bias voltage and a second replica bias voltage substantially equal to the second internal bias voltage. The additional voltage translation circuitry, coupled to the additional voltage replication circuitry and the telescopic cascode amplifier circuitry, responds to reception of the current mirror bias voltage, the second replica bias voltage and a fourth bias current related to the first bias current by providing a second one of the at least one cascode bias voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a schematic diagram of a MOSFET amplifier circuit with dynamically biased cascode output circuitry in accordance with one embodiment of the presently claimed invention. 
     FIG. 2 is a schematic diagram of a MOSFET amplifier with dynamically biased cascode output circuitry in accordance with another embodiment of the presently claimed invention. 
     FIG. 3 is a schematic diagram of a MOSFET amplifier with dynamically biased cascode output circuitry in accordance with still another embodiment of the presently claimed invention. 
     FIG. 4 is schematic diagram of a MOSFET amplifier with dynamically biased cascode output circuitry in accordance with yet another embodiment of the presently claimed invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments arc described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
     Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. 
     Referring to FIG. 1, a MOSFET amplifier with dynamically biased cascode output circuitry in accordance with one embodiment  100  of the presently claimed invention is implemented as a differential amplifier biased with a current mirror circuit and dynamic voltage biasing for the cascode output circuitry. This circuit  100  is biased with a power supply voltage defined by the positive VDD and negative VSS (or ground GND) voltages applied at the power supply terminals. The differential input signal VIN centered about its baseline, or common mode, input voltage VCMI, is applied to the gate terminals of P-MOSFETs M 9  and M 10  which form the differential input pair. (As indicated, each of the MOSFETs has width W and length L dimensions as well as width-to-length W/L ratios associated with them.) These input transistors M 9 , M 10  are provided a biasing current I 14  from P-MOSFET M 14  (discussed in more detail below). Depending upon the input signal VIN, this current I 14  is divided between the two output branch currents I 15 , I 16  conveyed by the cascode output transistors M 5 , M 6 . These output currents I 15 , I 16 , in conjunction with load resistors R 0 , R 1  establish the output voltage VOUT. Current sink N-MOSFETs M 15 , M 16  establish the lower biasing for the differential amplifier circuitry, with their gate terminal biasing voltage E 0  provided by a voltage generator VG which also maintains the node connecting the load resistors R 0 , R 1  at the common mode output voltage VCMO in accordance with well known techniques. 
     It will be appreciated that while the presently claimed invention is discussed in the context of embodiments in which various differential or single-ended output amplifier stages are used, the specific topology of the output amplifier stage (e.g., differential versus single-ended) is not the focus of the subject invention. 
     As discussed in more detail below, transistor M 14  provides an accurate replication, or mirror, current I 14  relative to current I 3  by accounting for the voltage VDIFF appearing at the source terminals of the input transistors M 9 , M 10 , which must be maintained at one gate-to-source voltage potential VGS abovIe the input baseline voltage VCMI. Additionally, the bias voltage VBIAS for the cascode output transistors M 5 , M 6  is maintained (via voltage tracking as discussed in more detail below) at a voltage level relative to voltage VDIFF. 
     A current generator IG provides a reference current I 1  to N-MOSFET M 1  which serves as the input transistor to a current replication, or mirror, circuit formed by N-MOSFETs M 2  and M 3 . Accordingly, currents I 2  and I 3  will mirror the reference current I 1  in proportion to their respective transistor channel ratios in accordance with well known principles. Current I 3  is provided to P-MOSFETs M 12 , and M 7  which together with P-MOSFETs M 8  and M 13  form a voltage replication circuit. Transistor M 7  is driven by the input signal baseline voltage VCMI and conveys current I 3  to transistor M 12  which establishes a current source bias voltage at its gate terminal for biasing current mirror transistor M 14 . Transistors M 8  and M 13  serve as a voltage level shifting buffer and establish a feedback loop for the voltage appearing at the drain terminal of transistor M 7  to maintain the voltage appearing at the gate terminals of transistors M 12 , M 13  and M 14  such that the replica voltage VDIFF_REPLICA appearing at the source terminal of transistor M 7  is equal to voltage VDIFF in the output amplifier. Accordingly, equal drain-to-source voltages VDS are maintained across current mirror transistors M 12  and M 14 . 
     The dynamic biasing voltage VBIAS for the cascode output transistors M 5 , M 6  is provided by voltage translation circuitry formed by P-MOSFETs M 11  and M 4 . Mirror current I 2  from transistor M 2  is provided to transistors M 4  and M 11 , as is the replica bias voltage VDIFF_REPLICA. Transistor M 4  serves as a current source cascode transistor and has transistor channel dimensions such that its width-to-length ratio W2/L2 is smaller by a factor of N than the corresponding dimensions W2/L2 of the cascode output transistors M 5 , M 6  (i.e., 1/N*W2/L2 versus W 2 /L 2 ). In accordance with well known principles (e.g., see U.S. Pat. No. 4,550,284, the disclosure of which is incorporated herein by reference), with such size factor N being greater than or equal to four. This results in a gate-to-source voltage VGS for transistor M 4  being substantially equal to the sum of the gate-to-source voltage VGS of the cascode output transistor M 5 /M 6  and the drain-to-source voltage VDS of the input transistor M 9 /M 10 . Accordingly, this maintains a sufficient drain-to-source voltage VDS for the input transistors M 9  and M 10  to remain operating in their saturation regions. This can be mathematically summarized as follows:                VDIFF        -        VBIAS     =                VDIFF_REPLICA        -        VBIAS                 =                VGS        (   M4   )                   =                  VGS        (     M5        /        M6     )       +     VDS        (     M9        /        M10     )                                      
     As indicated in FIG. 1, the bulk connections of transistors M 4 , M 7 , M 8 , M 9 , M 10 , M 5  and M 6  are all connected to the source terminal. While this is preferable, it is not necessary. For example, if such connections are not made, e.g., the bulk connections are instead tied to one of the power supply terminals, then the channel dimensions of transistor M 4  must be further reduced, i.e., transistor size factor N must be increased. 
     Referring to FIG. 2, another embodiment  200  of the presently claimed invention provides dynamic biasing for cascode output circuitry in a single-ended amplifier configuration. As before, transistor M 14  provides the amplifier current I 14  which is controlled by input transistor M 9  in accordance with the input signal VCMI+VIN. As with the circuit  100  of FIG. 1, the cascode output transistor M 5  is biased by the dynamic biasing voltage VBIAS such that the difference between voltages VBIAS and VDIFF are maintained such that the input transistor M 9  operates consistently in its saturation region. 
     Referring to FIG. 3, another embodiment  300  of the presently claimed invention has cascode output circuitry with multiple cascode transistors M 5 A, M 5 B connected in series. The first cascode output transistor M 5 A receives its dynamic biasing voltage VBIAS which is generated in conformance with the discussion above concerning the circuit  100  of FIG. 1 so as to maintain the saturation operation state of input transistor M 9 . The second cascode output transistor M 5 B also receives a dynamic biasing voltage VBIASI which is generated so as to dynamically maintain the desired voltage difference between VBIAS 1  and the voltage VDIFF 1  appearing at the mutual connection of input transistor M 9  and first cascode output transistor M 5 A. 
     This circuit  300  uses a second voltage replication circuit in the form of transistors M 7 B, M 12 B, M 8 B and M 13 B, as well as a second voltage translation circuit formed by transistors M 4 B and M 11 B. 
     It should be noted that the similarly numbered transistors with “A” and “B” suffixes perform similar functions. Current sources IG 2 B, IG 3 B, IG 2 A and IG 3 A provide the biasing currents I 2 B, I 3 B, I 2 A, I 3 A and can be implemented in accordance with any well known technique, such as current mirror circuitry as discussed above in connection with the circuit  100  of FIG.  1 . 
     In the second voltage replication circuit, the dynamic biasing voltage VBIAS generated by the first voltage translation circuitry provides the gate bias voltage for transistor M 7 B which with transistors M 12 B, M 8 B and M 13 B, in conformance with the discussion above for transistors M 7 , M 12 , M 8  and M 13  in the circuit  100  of FIG. 1, generates a replica voltage VDIFF 1 _REPLICA at its source terminal equal to the output circuit voltage VDIFF 1  appearing at the drain terminal at the input transistor M 9 . 
     In the second voltage translation circuit, current source cascode transistor M 4 B, in conjunction with transistor M 11 B in conformance with the discussion of transistors M 4  and M 11  in the circuit  100  of FIG. 1, generates the second dynamic biasing voltage VBIAS 1  for the second cascode output transistor M 5 B. This current source cascode transistor M 4 B, similar to the first current source cascode transistor M 4 A, has channel dimensions such that its width-to-length ratio is smaller by another size factor of N 1  than its associated output cascode transistor M 5 B. As a result, the dynamic cascode biasing voltages VBIAS, VBIAS 1  are maintained at levels relative to their associated output voltages VDIFF, VDIFF 1  such that the input transistor M 9  and first cascode output transistor M 5 A are maintained in their respective saturation operation states. This can be mathematically summarized as follows:                VDIFF        -        VBIAS     =                VDIFF_REPLICA        -        VBIAS                 =                VGS        (   M4A   )                   =                  VGS        (   M5A   )       +     VDS        (   M9   )                       VDIFF1        -        VBIAS1     =                VDIFF1_REPLICA        -        VBIAS1                 =                VGS        (   M4B   )                   =                  VGS        (   M5B   )       +     VDS        (   M5A   )                                      
     Referring to FIG. 4, another embodiment  400  of the presently claimed invention uses a single output cascode transistor M 5  similar to the circuits  100 ,  200  of FIGS. 1 and 2, and dual voltage replication and translation circuits similar to the circuit  300  of FIG.  3 . However, by using the second, and lower, dynamic biasing voltage VBIAS 1  for the single output cascode transistor M 5 , associated current source cascode transistor M 4 B and output cascode transistor M 5  can have similar channel dimensions. 
     In conformance with the discussion herein, it will be appreciated and understood by one of ordinary skill in the art that a MOSFET amplifier with cascode output circuitry in accordance with the presently claimed invention can be implemented with the complementary MOSFET circuitry as expressly discussed herein, or alternatively with complementary MOSFET circuitry in which the P-MOSFETs are interchanged with the N-MOSFETs and the N-MOSFETs are interchanged with the P-MOSFETs with appropriate reversals in drain and source terminal connections and power supply voltage to provide an output current sink circuit topology rather than an output current source circuit topology. 
     Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.