Abstract:
A voltage comparing circuit has a current pass forming circuit connecting the one main terminals of a first and second field effect transistors which input two input signal voltages on their control terminals, respectively. The current pass forming circuit, respond to the voltage difference between the two input signals, forms an instantaneous current pass between the one main terminals of the first and second transistors to cancel out the charging and discharging current of the associated transistors.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a semiconductor integrated circuit and, in particular, to an improvement of a voltage comparing circuit for comparing two input voltages to output the result corresponding to the voltage difference between the two inputs. 
     BACKGROUND OF THE INVENTION 
     A conventional voltage comparing circuit is shown in FIG. 1. Two input voltages, V i+  and V i- , are applied on a non-inverting input terminal 5 and an inverting input terminal 4, respectively. An output voltage Vo appears on an output terminal 2, the voltage Vo corresponding to the difference between the input voltages, V i+  and V i- . 
     Referring to FIG. 1, the voltage comparing circuit is mainly comprised of a differential amplifier, a level shift circuit, and an output circuit, the differential amplifier comprising p-channel Metal-Oxide-Semiconductor (MOS) transistors M 3  -M 6  and n-channel MOS transistors M 12  -M 14 , the level shift circuit comprising p-channel MOS transistors M 7  and M 8  and n-channel MOS transistors M 15  and M 16 , and the output circuit comprising a p-channel MOS transistor M g  and an n-channel MOS transistor M 17 . 
     The input voltages V i+  and V i-  are input to the differential amplifier which amplifies their voltage difference. The two voltages having the amplified voltage difference are applied to the respective gates of the transistors M 7  and M 8  in the level shift circuit. 
     Given that the input voltage V i-  is a specified reference voltage, when the input voltage V i+  is less than the reference voltage V i- , the drain voltage of the transistor M 7  is the threshold voltage V th  of the transistor M 15  and the drain voltage of the transistor M 8  is the high voltage V cc-h  on the high supply voltage terminal 1. 
     When the input voltage V i+  increases in excess of the reference voltage V i- , the gate voltages of the transistors M 7  and M 8  are inverted, so that the drain voltage of the transistor M 7  becomes the voltage V d  voltage-divided by the on-state resistances of the transistors M 7  and M 15  and the drain voltage of the transistor M 8  becomes the low voltage V cc-l  on the low supply voltage terminal 3. To sum up, the drain voltage of the transistor M 7  increases from V th  to V d , and the drain voltage of the transistor M 8  decreases from V cc-h  to V cc-l . 
     When such a voltage change occurs in the level shift circuit, however, charging or discharging current flows into or out of the gate capacitances and the drain and source diffusion capacitances of the transistors in the level shift circuit. This means that the drain voltage of the transistor M 8 , that is, the output voltage of the level shift circuit does not increase or decrease until such a charge or discharge terminates. In other words, there is a delay time caused by the charge and discharge which passes between the input voltages changing and the corresponding output of the level shift circuit changing, resulting in delayed response time of the entire voltage comparing circuit. 
     This conventional circuit operation is simulated and its characteristics is shown in FIG. 2, where the reference input voltage V i-  is 2.5 V, the waveform 21 indicates the input voltage V i+  increasing from 2.41 V to 2.51 V, and the waveform 22 indicates the output voltage Vo appearing on the output terminal 2 in response to the input voltage V i+ . 
     SUMMARY OF THE INVENTION 
     A voltage comparing circuit according to the present invention has a current pass forming circuit connecting the one main terminals of a first and second field effect transistors which input two input signal voltages on their control terminals, respectively. 
     The current pass forming circuit, respond to the voltage difference between the two input signals, forms a current pass between the one main terminals of the first and second transistors to cancel out the charging and discharging current of the associated transistors. 
     The current pass forming circuit is comprised of a oneshot trigger pulse generator and a gate circuit. The trigger pulse generator outputs a oneshot trigger pulse to the gate circuit in response to a change of the voltage difference between the two input signal voltages. Receiving the trigger pulse, the gate circuit forms an instantaneous current pass. 
     Preferably, the gate circuit comprises a field effect transistor whose gate receives the oneshot trigger pulse. More preferably, the gate circuit comprises a bilateral gate whose control terminal receives the oneshot trigger pulse. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram of a conventional voltage comparing circuit, 
     FIG. 2 is a graph of simulation waveforms illustrating the relationship between an input voltage and the corresponding output voltage in the conventional voltage comparing circuit, 
     FIG. 3 is a schematic circuit diagram of a voltage comparing circuit according to the present invention, 
     FIG. 4 is a circuit diagram of a first embodiment according to the present invention, 
     FIG. 5 is a circuit diagram of a second embodiment according to the present invention, 
     FIG. 6 is a circuit diagram of a third embodiment according to the present invention, 
     FIG. 7 is a graph of simulation waveforms illustrating the relationship between an input voltage and the corresponding output voltage in the first embodiment, 
     FIG. 8 is a graph of simulation waveform illustrating the relationship between an input voltage and the corresponding trigger pulses in the first embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 3, a voltage comparing circuit in accordance with the present invention has a high supply voltage terminal 1, an output terminal 2, a low supply voltage terminal 3, an inverting input terminal 4, and a non-inverting input terminal 5. Two input voltages, V i+  and V i- , are applied on the non-inverting and the inverting input terminals 5 and 4, respectively. An output voltage Vo appears on the output terminal 2, the output voltage Vo corresponding to the difference between the input voltages, V i+  and V i- . 
     The voltage comparing circuit is mainly comprised of a differential amplifier receiving the two input voltages, a level shift circuit including a gate circuit which is capable of providing a current pass according to a oneshot trigger pulse, and an output circuit providing the output of the level shift circuit to the output terminal 2. 
     The differential amplifier is comprised of p-channel MOS transistors M 3  -M 6  and n-channel MOS transistors M 12  -M 14 . The two input voltages, V i+  and V i- , are applied on the gates of the transistors M 12  and M 13  through the non-inverting and the inverting input terminals 5 and 4, respectively. 
     The voltage difference between V i+  and V i-  is amplified by the differential amplifier. Its two output voltages with the amplified voltage difference are output from the drains of the transistors M 3  and M 6  to the gates of the transistors M 7  and M 8  in the level shift circuit, respectively. 
     The level shift circuit is comprised of p-channel MOS transistors M 7  and M 8 , n-channel MOS transistors M 15  and M 16 , the gate circuit, and a trigger pulse generator (not shown in FIG. 3). 
     The transistors M 7  and M 15  are connected in series. The transistor M 7  has its drain connected to the drain of the transistor M 15  and its source connected to the high supply voltage terminal 1. The transistor M 15  has its source connected to the low supply voltage terminal 3 and its gate connected to its drain as well as the gate of the transistor M 16 . 
     Similarly, the transistors M 8  and M 16  are connected in series, the transistor M 8  having its drain connected to the drain of the transistor M 16  and its source connected to the high supply voltage terminal I and the transistor M 16  having its source connected to the low supply voltage terminal 3. The drain of the transistor M 8  serves as the output terminal of the level shift circuit. 
     The drains of the transistor M 7  and M 8  are connected with the gate circuit which is capable of forming a current pass between them according to a oneshot trigger pulse. This current pass forming circuit will be described in detail later. 
     The output circuit is comprised of p-channel MOS transistor M g  and n-channel MOS transistor M 17 . Their gates are connected in common to the drain of the transistor M 8  as the output terminal of the level shift circuit and their drains to the output terminal 2. 
     The operation of the voltage comparing circuit mentioned above will now be described. Assuming that the respective threshold voltages of p-channel and n-channel MOS transistors are -0.8 V and 0.8 V, the high supply voltage V cc-h  is 5 V, the input voltage V i-  is the reference voltage of 2.5 V, and the non-inverting input terminal 5 receives a pulse of 0.1 V p--p  comprising the initial low voltage of 2.41 V and the pulse high voltage of 2.51 V. 
     When the input voltage V i+  =2.41 V is applied on the noninverting input terminal 5, the differential amplifier amplifies the voltage difference of the two input voltages, V i+  =2.41 V and V i-  =2.5 V, and outputs two voltages having the amplified difference from the drains of the transistors M 3  and M 6  to the gates of the transistors M 7  and M 8 , respectively. 
     Thus, the threshold voltage V th  of the transistor M 15  appears on the drain of the transistor M 7  that is in off-state, and the high supply voltage V cc-h  appears on the drain of the transistor M 8  that is in on-state. 
     A 0.1 V p--p  pulse is now applied to the non-inverting input terminal 5 whose voltage V i+  rises from 2.41 V to 2.51 V in excess of the input voltage V i-  of 2.5 V. This causes the relative polarity of the gate voltages of the transistors M 7  and M 8  to be inverted. 
     At this instance, a oneshot trigger pulse is generated and given to the gate circuit. This trigger pulse causes the gate circuit to form an instantaneous current pass between the drains of the transistors M 7  and M 8 . The current pass cancels out the charging and discharging current on the drains of those transistors, resulting in more rapid operation that the drain voltage of the transistor M 7  increases from V th  to V d  and the drain voltage of the transistor M 8  decreases from V cc-h  to V cc-l . 
     CURRENT PASS FORMING CIRCUIT 
     FIG. 4 shows details of a current pass forming circuit of the integrated circuit according to one embodiment of the present invention. 
     The current pass forming circuit is comprised of a oneshot trigger pulse generator and a gate circuit, the trigger pulse generator comprising p-channel MOS transistors M 18  -M 20  and n-channel MOS transistors M 21  -M 24 , and the gate circuit comprising n-channel MOS transistor M 25  by which the drains of the transistors M 7  and M 8  are connected. The oneshot trigger pulse is applied on the gate of the transistor M 25  which forms the instantaneous current pass between the drains of the transistors M 7  and M 8 . 
     The transistors M 19  and M 20  have their respective gates connected to the drains of the transistors M 3  and M 6  in the differential amplifier. The drains D 19  and D 20  of the transistors M 19  and M 20  are connected to the low supply voltage terminal 3 via the transistors M 24  and M 23 , respectively. The drains D 19  and D 20  are also connected in common to the gate of the transistor M 25  via the transistors M 21  and M 22 , respectively. The gate of the transistor M 21  is connected to the drain D 20  of the transistor M 20 , and the gate of the transistor M 22  to the drain D 19  of the transistor M 19 . 
     OPERATION OF THE CURRENT PASS FORMING CIRCUIT 
     Now assuming that the transistor M 19  is in on-state and the transistor M 20  in off-state by two output voltages of the differential amplifier. 
     On the drain D 19  of the transistor M 19  appears the voltage Vhi divided by the on-state resistances of the transistors M 19  and M 24  and on the drain D 20  of the transistor M 20  appears the low voltage V low  equal to the low supply voltage V cc-l . This means that the transistor M 21  is in off-state and the transistor M 22  in on-state, and the low voltage Vlow on the drain D 20  is applied on the gate of the transistor M 25 . Thus, the transistor M 25  is in off-state, forming no current pass. 
     When the two output voltages from the differential amplifier are changed, the transistor M 20  turns out to be in on-state, therefore the transistor M 21  is also turned into on-state. This causes the voltage V hi  on the drain D 19  to be applied on the gate of the transistor M 25  via the transistor M 21 . 
     When the two output voltages from the differential amplifier are further changed, however, the voltage of the drain D 19  drops from V hi  to V low . Therefore, an instantaneous pulse is applied to the gate of the transistor M 25  only when the relative polarity of the two output voltages from the differential amplifier is changed. 
     Receiving the oneshot trigger pulse, the transistor M 25  turns out to be in on-state, forming an instantaneous current pass between the drains of the transistors M 7  and M 8 . The current pass cancels out the charging and discharging current on the drains of those transistors, resulting in reduced response delay of the entire integrated circuit. 
     The present circuit operation is simulated and its characteristics is shown in FIGS. M 7  and 8. Referring to FIG. 7, when a 0.1 V p--p  pulse indicated by the reference numeral 71 is applied on the non-inverting input terminal 5, a trigger pulse rises as represented by a waveform 72 and then the output voltage Vo rises as represented by a waveform 73. Compared with the prior art as shown in FIG. 2, the output voltage Vo of the present embodiment rises promptly and sharply. FIG. 8 shows the generated trigger pulses as a waveform 82 when the 0.1 V p--p  input pulse as a waveform 81 rises and falls. 
     A second embodiment of the present invention is shown in FIG. 5. In this embodiment, the gate circuit for forming a current pass is comprised of a bilateral gate where the n-channel MOS transistor M 25  is connected to a p-channel MOS transistor M 26  in parallel with the gates of those transistors connected by an inverter INV. Employing the bilateral gate causes the on-state resistance of the gate circuit to be further reduced, so that higher speed operation can be achieved. 
     The gate circuit mentioned above may comprise a switching circuit Sl as shown in FIG. 6, which can form the current pass according to a control signal applied on a control signal input terminal 6.