Abstract:
An optimized hardware architecture and method introducing a simple arithmetic processor that allows efficient implementation of an Elliptical Curve Cryptography point doubling algorithm for Jacobian coordinates. The optimized architecture additionally reduces the required storage for intermediate values to one intermediate value.

Description:
BACKGROUND 
       [0001]    Electronic devices are becoming a ubiquitous part of everyday life. The number of smartphones and personal tablet computers in use is rapidly growing. A side effect of the increasing use of smartphones and personal tablets is that increasingly the device are used for storing confidential data such as personal and banking data. Protection of this data against theft is of paramount importance. 
         [0002]    The field of cryptography offers protection tools for keeping this confidential data safe. Based on hard to solve mathematical problems, cryptography typically requires highly computationally intensive calculations that are the main barrier to wider application in cloud and ubiquitous computing (ubicomp). If cryptographic operations cannot be performed quickly enough, cryptography tools are typically not accepted for use on the Internet. In order to be transparent while still providing security and data integrity, cryptographic tools need to follow trends driven by the need for high speed and the low power consumption needed in mobile applications. 
         [0003]    Public key algorithms are typically the most computationally intensive calculations in cryptography. For example, take the case of Elliptic Curve Cryptography (ECC), one of the most computationally efficient public key algorithms. The 256 bit version of ECC provides security that is equivalent to a 128 bit symmetric key. A 256 bit ECC public key should provide comparable security to a 3072 bit RSA public key. The fundamental operation of ECC is a point multiplication which is an operation heavily based on modular multiplication, i.e. approximately 3500 modular multiplications of 256 bit integers are needed for performing one ECC 256 point multiplication. Higher security levels (larger bit integers) require even more computational effort. 
         [0004]    Building an efficient implementation of ECC is typically non-trivial involves multiple stages.  FIG. 1  illustrates stages  101 ,  102  and  103  that are needed to realize the Elliptical Curve Digital Signature Algorithm (ECDSA), which is one of the applications of ECC. Stage  101  deals with finite field arithmetic that comprises modular addition, inversion and multiplication. Stage  102  deals with point addition and point doubling which comprises the Joint Sparse Form (JSF), Non-Adjacent Form (NAF), windowing and projective coordinates. Finally, stage  103  deals with the ECDSA and the acceptance or rejection of the digital signature. 
         [0005]    Any elliptic curve can be written as a plane geometric curve defined by the equation of the form (assuming the characteristic of the coefficient field is not equal to 2 or 3): 
         [0000]        y   2   =x   3   +ax+b   (1)
 
         [0000]    that is non-singular; that is it has no cusps or self-intersections and is known as the short Weierstrass form where a and b are integers. The case where a=−3 is typically used in several standards such as those published by NIST, SEC and ANSI which makes this the case of typical interest. 
         [0006]    Many algorithms have been proposed in the literature for efficient implementation of the Point Addition (PADD) and Point Doubling (PDBL) operations. Many of these algorithms are optimized for software implementation. While these are typically efficient on certain platforms, the algorithms are typically not optimal once the underlying hardware can be tailored to the algorithm. 
         [0007]    A PDBL algorithm for Jacobian coordinates has been described by Cohen, Miyaji and Ono in Proceedings of the International Conference on the Theory and Applications of Cryptography and Information Security; Advances in Cryptology, ASIACRYPT 1998, pages 51-65, Springer-Verlag, 1998. Jacobian coordinates are projective coordinates where each point is represented as three coordinates (X, Y, Z). Note the coordinates are all integers. PDBL algorithm  200  requires 4 modular multiplications, 4 modular squarings, 4 modular subtractions, one modular addition, one modular multiplication by 2 and one modular division by 2 and is shown in  FIG. 2 . In order to perform the PDBL, the algorithm further requires a minimum of 3 temporary registers, which for ECC 256 bit each need to be 256 bits in size. All operations are done in the finite field K over which the elliptic curve E is defined. The finite arithmetic field K is defined over the prime number p so that all arithmetic operations are performed modulo p. The identity element is the point at infinity. 
       SUMMARY 
       [0008]    An optimized hardware architecture and method reduces storage requirements and speeds up the execution of the ECC PDBL algorithm by requiring only two temporary storage registers and by introducing a simple arithmetic unit for performing modular addition, subtraction and multiplication and division by 2. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  shows stages  101 ,  102  and  103  that are needed to realize the Elliptical Curve Digital Signature Algorithm (ECDSA). 
           [0010]      FIG. 2  shows a prior art point doubling algorithm. 
           [0011]      FIG. 3  shows an embodiment in accordance with the invention. 
           [0012]      FIG. 4  shows an embodiment in accordance with the invention. 
           [0013]      FIG. 5  shows an embodiment in accordance with the invention. 
           [0014]      FIG. 6  shows an embodiment in accordance with the invention. 
           [0015]      FIG. 7  shows an embodiment in accordance with the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    PDBL algorithm  300  in accordance with the invention is shown in  FIG. 3 . PDBL algorithm  300  requires fewer steps and reduces the storage requirements compared to PDBL algorithm  200  for the same modular point doubling. PDBL algorithm  300  requires only two temporary storage registers, T 1  and T 2 . PDBL algorithm  300  is implemented over an optimized hardware architecture shown in  FIG. 6  and  FIG. 7  which is specifically designed to take advantage of PDBL algorithm  300 . 
         [0017]    As input in step  301 , PDBL algorithm  300  shown in  FIG. 3  takes point P=(X 1 , Y 1 , Z 1 ) in Jacobian coordinates. α is the temporary storage variable. Note that all mathematical operations shown are in modular arithmetic and the coordinates are Jacobian. In step  302  of PDBL algorithm  300 , if P=∞ (the identity element) the value co is returned. In step  303 , Z 1  is squared (Z 1 *Z 1 ) with the resulting value stored in Z 3 . In step  304 , Y 1  is squared (Y 1 *Y 1 ) and the resulting value stored in Y 3 . In step  305 , X 1 *Y 3  is calculated and the result stored in temporary register α. In step  306 , 3(X 1 −Z 3 )*(X 1 +Z 3 ) is calculated and the result stored in Z 3 . In step  307 , Z 3 *Z 3 −8α is calculated with the result stored in X 3 . In step  308 , Z 3 *(4α−X 3 ) is calculated and the result stored in temporary register α. In step  309 , α−8Y 1 *Y 1  is calculated and the result stored in Y 3 . In step  310 , 2Y 1 *Z 1  is calculated and the result is stored in Z 3 . Finally, in step  311  the result of the point doubling of P is returned in Jacobian coordinates as (X 3 , Y 3 , Z 3 ). 
         [0018]    The most computationally intensive operation in PDBL algorithm  300  in  FIG. 3  is modular multiplication denoted by “*”. Because most of the steps described in PDBL algorithm  300  depend on the previous steps of the algorithm, it is typically most efficient to implement PDBL algorithm  300  in hardware using a single modular multiplier although more than one modular multiplier may be used in accordance with the invention which allows more than one modular multiplication to be performed in a step. Using only one modular multiplier restricts each step in PDBL algorithm  300  to having no more than one modular multiplication. 
         [0019]    It is important to note that besides the modular multiplication steps performed in steps  303 ,  304 ,  305 ,  306 ,  307 ,  308 ,  309  and  310  of PDBL algorithm  300 , additional, comparatively simple operations are performed as well: modular subtraction and addition and modular multiplication by powers of 2. Note that multiplication by a power of 2 in binary is merely a left shift operation. In order to speed up execution of PDBL algorithm  300  and eliminate the need for additional temporary registers, an embodiment in accordance with the invention of simple arithmetic unit (SAU)  400  with the inputs A, B and outputs C and D as shown in  FIG. 4  is used. 
         [0020]      FIG. 5  shows how steps  306 ,  307 ,  308 ,  309  and  310  are broken down for utilization of SAU  400  which has inputs A and B with outputs C and D. Note that the input and output labels of SAU  400  correspond to the respective variable names in  FIG. 5 . Block  501  shows how step  306  of PDBL algorithm  300  is broken down using SAU  400  and involves setting inputs A=X 1  and B=Z 3  with outputs C=A+B and D=3(A−B). Outputs c and D are then multiplied together and the result stored in Z 3 . Block  502  shows how step  307  of PDBL algorithm  300  is broken down using SAU  400  and involves setting inputs A=Z 3   2  and B=α with output D=A−8B. Block  503  shows how step  308  of PDBL algorithm  300  is broken down using SAU  400  and involves setting inputs A=α, B=X 3  with output D=4A−B. Output D is then multiplied by Z 3  and the result stored in temporary storage register α. Block  504  shows how step  309  of PDBL algorithm  300  is broken down using SAU  400  and involves setting inputs A=α and B=Y 3   2  with output D=A−8B. Block  505  shows how step  310  of PDBL algorithm  300  is broken down using SAU  400  and involves setting input A=Y 1  and output D=2A. Output D is then multiplied by Z 1  and the result is stored in Z 3 . 
         [0021]      FIG. 6  shows embodiment 600 in accordance with the invention comprising multi-cycle multiplier  610  with output register (not shown), SAU  400 , multiplexer (MUX)  620  and MUX  630  with input registers X 1 , Y 1 , Z 1 , x 2 , y 2  (not used), output registers X 3 , Y 3 , Z 3  and temporary register α that are all part of register memory  695 . Note the individual register labels correspond to variable names in  FIGS. 3 and 5 . Multiplexer (MUX)  620 , MUX  630  and MUXs  720 .  722  and  725  (part of SAU  400 , see  FIG. 7 ) are controlled by the microprocessor (not shown) which executes PDBL algorithm  300 . As noted above, each step in PDBL algorithm  300  involve at most one modular multiplication (not counting multiplications by a power of 2 which in binary representation is merely a shift operation). 
         [0022]    SAU  400  shown in  FIG. 7  comprises subtractor  710 , adder  722 , logical one bit left shifter  715 , logical two bit left shifter  718  (multiplication by 4), logical three bit left shifter  714  (multiplication by 8), MUX  720 , MUX  723 , MUX  725  and multiplier by three  728  which is constructed using a logical one bit left shifter and an adder (2x+x=3x). 
         [0023]    Input A connects to adder  722  on line  671  and also connects to one bit left shifter  715 , to input “0” of MUX  720  and to logical two bit left shifter  718  on line  671 . Logical one bit shifter  715  outputs 2A on line  776  to input “0” of MUX  725 . Logical two bit left shifter  718  outputs 4A on line  733  to input “1” of MUX  720 . MUX  720  connects to the minuend input of subtractor  710  on line  731 . Input B connects to adder  722  on line  672  and also connects to logical three bit left shifter  714  and input “0” of MUX  723  on line  672 . Logical three bit left shifter  714  outputs 8B to input “1” of MUX  723  on line  744 . MUX  723  connects to the subtrahend input of subtractor  710  on line  732 . Adder  722  outputs C(=A+B) on line  690 . Subtractor  710  connects to input “1” of MUX  725  on line  777  and connects to multiplier by three  728  on line  777 . Multiplier by three  728  connects to input “2” on MUX  725 . MUX  725  outputs D (see  FIG. 4 ) on line  696 . 
         [0024]    Multi-cycle multiplier  610  functions by multiplying the values on lines  635  and  640  together and outputting the result. Steps  301 - 302  are performed using the microprocessor (not shown) without using multi-cycle multiplier  610  and SAU  400 . 
         [0025]    Step  303  utilizes multi-cycle multiplier  610 . Register memory  695  provides Z 1  on both inputs  635  and  640  of multi-cycle multiplier  610  and multi-cycle multiplier  610  computes Z 1   2  which is sent on line to register memory  695  where it is stored in Z 3 . 
         [0026]    Step  304  utilizes multi-cycle multiplier  610 . Register memory  695  provides Y 1  on both line  635  and on line  640  to multi-cycle multiplier  610 . Multi-cycle multiplier  610  computes Y 1 *Y 1  which is sent on line  650  to register memory  695  where it is stored in Y 3 . 
         [0027]    Step  305  utilizes multi-cycle multiplier  610 . Register memory  695  provides X 1  on line  635  and Y 3  on line  640  to multi-cycle multiplier  610 . Multi-cycle multiplier  610  computes X 1 *Y 3  which is sent on line  650  to register memory  695  where it is stored in temporary register α. 
         [0028]    Step  306  utilizes both multi-cycle multiplier  610  and SAU  400 . Register memory  695  provides X 1  on line  665  to input “0” of MUX  620  with MUX  620  set to “0”. MUX  620  sends X 1  to input A of SAU  400  on line  671  directly to adder  722  and to input “0” of MUX  720  with MUX  720  set to “0”. MUX  720  sends A (X 1 ) to the minuend input of subtractor  710  on line  731 . Register memory  695  provides Z 3  on line  650  to input “0” of MUX  630  with MUX  630  set to “0”. MUX  630  sends Z 3  to input B of SAU  400  on line  672  directly to adder  722  and input “0” of MUX  723  with MUX  723  set to “0”. MUX  723  sends B (Z 3 ) to the subtrahend input of subtractor  710 . Subtractor  710  computes A−B (which is X 1 −Z 3 ) which is output online  777  to multiplier by three  728  which computes and outputs 3(A−B) (which is 3(X 1 −Z 3 )) on line  778  to input “2” of MUX  725 . MUX  725  sends D (which is 3(A−B)=3(X 1 −Z 3 )) on line  696  to register memory  695  which passes D on line  635  to multi-cycle multiplier  610 . Adder  722  computes A+B and outputs the result as C (which is (X 1 +Z 3 )) on line  690  to register memory  695  which passes C on line  640  to multi-cycle multiplier  610 . Multi-cycle multiplier computes C*D (which is 3(X 1 −Z 3 )*(X 1 +Z 3 )) which is output on line  650  to register memory  695  where the result is stored in Z 3 . 
         [0029]    Step  307  utilizes both multi-cycle multiplier  610  and SAU  400 . Register memory  695  provides Z 3  on both lines  635  and  640  to multi-cycle multiplier  610 . Multi-cycle multiplier  610  computes and outputs Z 3 *Z 3  on line  650  to input “1” of MUX  620  with MUX  620  set to “1”. MUX  620  sends Z 3   2  to input A of SAU  400  on line  671  which connects to input “0” on MUX  720  with MUX. MUX  720  sends A (Z 3   2 ) on line  731  to the minuend input of subtractor  710 . Register memory  695  provides a on line  660  to input “0” of MUX  630  with MUX  630  set to “0”. MUX  630  sends α to input B of SAU  400  on line  672  which connects to logical three bit left shifter  714  (multiply by 8). Logical three bit left shifter  714  computes and outputs 8B (8α) on line  744  to input “1” of MUX  723  with MUX  723  set to “1”. MUX  723  sends 8B on line  732  to the subtrahend input of subtractor  710 . Subtractor computes and outputs A−8B (which is Z 3 −8α) on line  777  to input “1” of MUX  725  with MUX  725  set to “1”. MUX  725  sends D (which is A−8B=Z 3 −8α) on line  696  to register memory  695  where the result is stored in X 3 . 
         [0030]    Step  308  utilizes both multi-cycle multiplier  610  and SAU  400 . Register memory  695  provides a on line  665  to input “0” of MUX  620  with MUX  620  set to “0”. MUX  620  sends α to input A of SAU  400  on line  671  which connects to logical two bit left shifter  718  (multiply by 4). Logical two bit left shifter  718  computes and outputs 4A (4α) on line  733  to input “1” of MUX  720  with MUX  720  set to “1”. MUX  720  sends 4A on line  731  to the minuend input of subtractor  710 . Register memory  695  provides X 3  on line  660  to input “0” of MUX  630  with MUX  630  set to “0”. MUX  630  sends X 3  to input B of SAU  400  on line  672  which is connected to input “0” of MUX  723  with MUX  723  set to “0”. MUX  723  sends B (X 3 ) on line  732  to the subtrahend input of subtractor  710 . Subtractor  710  computes and outputs 4A−B (which is 4α−X 3 ) on line  777  to input “1” of MUX  725  with MUX  725  set to “1”. MUX  725  outputs D (which is 4A−B=4α−X 3 ) on line  696  to register memory  695  which passes D onto line  635  and provides Z 3  on line  640  to multi-cycle multiplier  610  which computes and outputs Z 3 *D (which is Z 3 *(4α−X 3 )) on line  650  to register memory  695  where the result is stored in temporary register α. 
         [0031]    Step  309  utilizes both multi-cycle multiplier  610  and SAU  400 . Register memory  695  provides a on line  665  to input “0” of MUX  620  with MUX  620  set to “0”. MUX  620  sends α to input A of SAU  400  on line  671  which connects to input “0” of MUX  720  with MUX  720  set to “0”. MUX  720  sends A (α) on line  731  to the minuend input of subtractor  710 . Register memory  695  provides Y 3  on both line  635  and line  640  to multi-cycle multiplier  610  which computes and outputs Y 3 *Y 3  on line  650  which connects to input “1” of MUX  630  with MUX  60  set to “1”. MUX  630  outputs Y 3   2  to input B of SAU  400  on line  672  which connects to logical three bit left shifter  719  (multiply by 8). Logical three bit left shifter  719  computes and outputs 8B (8Y 3   2 ) on line  744  to input “1” of MUX  723  with MUX  723  set to “1”. MUX  723  sends 8B to the subtrahend input of subtractor  710 . Subtractor  710  computes and outputs A−8B (which is α−8Y 3   2 ) on line  777  to input “1” of MUX  725 . MUX  725  sends D (which is A−8B=α−8Y 3   2 ) on line  696  to register memory  695  where the result is stored in Y 3 . 
         [0032]    Step  310  utilizes both multi-cycle multiplier  610  and SAU  400 . Register memory  695  provides Y 1  on line  665  to input “0” of MUX  620  with MUX  620  set to “0”. MUX  620  sends Y 1  to input A of SAU  400  on line  671  which connects to logical one bit left shifter  715  (multiply by 2). Logical one bit left shifter  715  computes and outputs 2A (2Y 1 ) on line  776  to input “0” of MUX  725  with MUX  725  set to “0”. MUX  725  sends D (which is 2A=2Y 1 ) on line  696  to register memory  695  which passes D onto line  635  and provides Z 1  on line  640  to multi-cycle multiplier  610 . Multi-cycle multiplier  610  computes and outputs D*Z 1  (which is 2A*Z 1 =2Y 1 *Z 1 ) on line  650  to register memory  695  where it is stored in Z 3 . 
         [0033]    Step  311  is performed using the microprocessor and returns the result of PDBL algorithm  300  which is (X 3 , Y 3 , Z 3 ) for input (X 1 , Y 1 , Z 1 ).