Abstract:
A static semiconductor memory device comprises memory cells arranged in a matrix having columns and rows, and bit selection circuits provided in the respective columns. Each of the bit selection circuits is adapted to receive a column selection signal, having a high reference potential, when the corresponding column is selected for supplying a current to the selected column. A discharge path is provided in each bit selection circuit so that the potential of the column selection signal is rapidly lowered when the column is switched from a selected state to a nonselected state, whereby the power consumption is lowered and high speed operation is achieved.

Description:
BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     The present invention relates to a static semiconductor memory device having memory cells arranged in a matrix, each memory cell comprising two driving transistors connected in intersection, and more particularly to a semiconductor memory device having a bit line selection circuit in each column for receiving a high potential selection signal when selected and for supplying a current to the selected column; in which a discharge path is provided in each bit line selection circuit for rapidly lowering the potential of the selection signal during the transition from a selected state to a nonselected state, whereby the power consumption is reduced and high speed operation is realized. 
     (2) Description of the Prior Art 
     In recent years, semiconductor memory devices, especially static RAMs (random access memories) have greatly progressed in high integration, high speed operation, and low power consumption. The development of large memory capacities, however, has led to the demand for even higher speed operation and lower power consumption. 
     FIG. 1A is a circuit diagram illustrating a main portion of a conventional static bipolar RAM. In FIG. 1A, MC 11 , MC 1n , MC mn , . . . represent memory cells arranged in a matrix having n columns C 1  through C n  and m rows R 1  through R m . 
     FIG. 1B is a circuit diagram illustrating the memory cell MC 11  in detail. In FIG. 1B, the memory cell MC 11  consists of two driving transistors Q 11  and Q 12  and two memory storage transistors Q 21  and Q 22 . The driving transistor Q 11  and the memory storage transistor Q 21  constitute a multi-emitter transistor. Similarly, the transistors Q 12  and Q 22  constitute another multi-emitter transistor. The collector of the transistor Q 11  is connected to the base of the transistor Q 12 . Similarly, the collector of the transistor Q 12  is connected to the base of the transistor Q 11 . Thus, the collectors of the transistors Q 11  and Q 12  are connected in intersection with each other. The emitters of the memory storage transistors Q 21  and Q 22  are commonly connected to a negative word line WD 1 . Load resistors R 11  and R 12  are respectively connected between the collectors of the transistors Q 11  and Q 12  and a positive word line WD 1   + . Load diodes D 1  and D 2  are respectively connected between the collectors of the transistors Q 11  and Q 12  and the positive word line WD 1   + . When this memory cell MC 11  is selected, only one of the diodes D 1  and D 2  conducts current so as to supply a collector current to one of the memory storage transistors Q 21  and Q 22 . Thus, the load diodes D 1  and D 2   contribute to saving power consumption. 
     The other memory cells have a similar configuration to the memory cell MC 11 . 
     Referring back to FIG. 1A, WD 1   + , . . . , and WD m   +  represent positive word lines connected to the emitters of word driving transistors TW 1 , . . . , and TW m , respectively. The bases of the word driving transistors TW 1 , . . . , and TW m  are adapted to receive word selection signals X 1 , . . . , and X m , respectively. The collectors of the transistors TW 1 , . . . , and TW m  are grounded. WD 1   - , . . . , and WD m   -   represent negative word lines, each of which is commonly connected to the emitters of the memory storage transistors, included in the corresponding row, and also to a holding current source (not shown). 
     (B 11 , B 12 ), . . . , and (B n1 , B n2 ) each represents a pair of bit lines connected to the emitters of the driving transistors Q 11 , Q 12 , . . . in the corresponding column. The bit lines B 11 , B 12 , . . . , B n1 , and B n2  are connected to the emitters of transistors TR 11 , TR 12 , . . . , TR n1 , and TR n2 , respectively. The bases of the transistors TR 11 , TR 12 , . . . , TR n1  and TR n2  are adapted to receive a signal of a reference potential for a reading operation. The signal of the reference potential is supplied from a reference potential setting circuit RC. The collectors of the transistors TR 11 , TR 12 , . . . , TR n1  and TR n2  are grounded. PSA 1 , . . . , and PSA n  are pre-sense amplifiers each consisting of a pair of transistors (T 71 , T 81 ), . . . , or (T 7n , T 8n ), respectively. The bases of the transistors T 71 , T 81 , . . . , T 7n , and T 8n  are connected to the bit lines B 11 , B 12 , . . . , B n1 , and B n2 , respectively. The collectors of the transistors T 7n , and T 8n , . . . , Q 7n , and Q 8n  are commonly connected to a sense amplifier SA. PLP 1 , . . . , and PLP n  represent pull-up circuits for charging up the nonselected bit lines, respectively. Each pull-up circuit comprises a multi-emitter transistor T 61 , . . . or T 6n  with the first emitter being connected to one of the corresponding pair of bit lines and the second emitter being connected to the other of the bit lines. 
     BD 1 , . . . , and BD n  represent bit driver circuits. The bit driver circuit BD 1  comprises a transistor T 11 , a diode DI 1 , and a current source IB 1 . The emitter of the transistor T 11  is connected to the anode of the diode DI 1 . The cathode of the diode DI 1  is connected to the current source IB 1 . The collector of the transistor T 11  is grounded. The base of the transistor T 11  is connected to a terminal Y 1  which is adapted to receive a column selection signal. The other bit driver circuits have a circuit configuration similar to the bit driver circuit BD 1 . 
     BSW 1 , . . . , and BSW n  represent bit selection circuits. The bit selection circuit BSW i  consits of four transistors T 2i , T 3i , T 4i , and T 5i , where i represents the column number. The collector of the transistor T 2i  is connected to the bit line B i1 . The collector of the transistor T 5i  is connected to the bit line B i2 . The collector of the transistor T 3i  is connected to the coupled emitters of the transistors T 7i  and T 8i . The collector of the transistor T 4i  is connected to the base of the pull-up transistor T 6i . The emitters of the transistors T 2i  through T 5i  are connected through signal lines K 2 , K 3 , K 4 , and K 5  to current sources I 2 , I 3 , I 4 , and I 5 , respectively. The bases of the transistors T 2i , T 3i , T 4i , and T 5i  are commonly connected to a node YB i  connected to the cathode of the diode DI i . Thus, the transistors T 21 , T 22 , . . . , and T 2n  constitute a current switch. Similarly, the other sets of transistors T 31  through T 3n , T 41  through T 4n , and T 51  through T 5n  constitute current switches, respectively. When one of the columns C i  is selected, a high potential column selecting signal is applied through the terminal Y i  to the bases of the transistors T 2i  through T 5i  in the corresponding bit selection circuit BSW i  so that these transistors are turned on to supply currents to the column C i . 
     The operation of the conventional static bipolar RAM of FIG. 1 will now be briefly described. Assume that information is stored in the memory cell MC 11  in a state that the transistor Q 21  is in a conductive state and the transistor Q 22  is in a cut-off state. In this state, the potential V c1  at the collector of the transistor Q 11  (see FIG. 1B) is at a low potential (hereinafter referred to as an &#34;L level&#34;), and the potential V c2  at the collector of the transistor Q 12  is at a high potential (hereinafter referred to as a &#34;H level&#34;). When the memory cell MC 11  is selected by applying the H level signals to a terminal X 1  connected to the base of the transistor TW 1  and to the terminal Y 1  connected to the base of the transistor T 11 , respectively, the transistor TW 1  is turned on so that the positive word line WD 1   +   is caused to be the H level, and, simultaneously, the transistor T 11  is turned on so that the node YB 1  is caused to be the H level. The other terminals Y 2 , . . . , and Y n  are all at the L level so that the nodes YB 2 , . . . , and YB n  are at the L level. Accordingly, only the transistors T 21 , T 31 , T 41 , and T 51  is the selected bit selection circuit BSW 1  are turned on to supply currents from the current sources I 2 , I 3 , I 4 , and I 5  to the selected column C 1 . 
     The emitter of the transistor TR 11  for setting the reading reference potential and the emitters of the driving transistors Q 11  in the memory cells MC 11 , . . . , and MC m1  are connected to the bit line B 11  to which the current I 2  is supplied when the transistor T 21  is turned on. Also, the emitter of the transistor TR 12  for setting the reading reference potential and the emitters of the driving transistors Q 12  in the memory cells MC 11 , . . . , and MC m1  are connected to the bit line B 12  to which the current I 5  is supplied when the transistor T 51  is turned on. In the memory cell MC 11 , when the positive word line WD 1   +   is raised to the H level so that the potential difference between the positive word line WD 1   +   and the node V c1  exceeds the threshold voltage of the diode D 1 , the diode D 1  begins to conduct current because the node V c1  was at the L level. In contrast, the diode D 2  is kept in the cut-off state because the node V c2  was at the H level. When the memory cell MC 11  has been selected, the potential at the nodes V c1  and V c2  become higher than those when the memory cell MC 11  is not selected. Also, the potential difference between the nodes V c1  and V c2  is increased. Then, the reading reference potential setting circuit RC provides an intermediate potential between the voltages V c1  and V c2  to the bases of the transistors TR 11 , TR 12 , . . . , TR n1 , and TR n2 . Because the base potential of the transistor Q 11  is V c2 , which is higher than the base potential of the transistor TR 11 , the current switch constituted by the transistors TR 11  and Q 11  is operated to cause the transistor Q 11  to be turned on, while the transistor TR 11  is kept in the cut-off state. Also, because the base potential of the transistor Q 12  is V c1 , which is lower than the base potential of the transistor TR 12 , the current switch constituted by the transistors TR 12  and Q 12  is operated to cause the transistor TR 12  to be turned on, while the transistor Q 12  is kept in the cut-off state. Thus, the transistor Q 11  conducts a current from the positive word line WD 1   +   to the bit line B 11 , and the transistor TR 12  conducts current to the bit line B 12 . The potential difference between the bit lines B 11  and B 12  is amplified by the pre-sense amplifier PSA 1  which consists of the transistors T 71  and T 81  having emitters commonly connected through the transistor T 31  to the current source I 3  to form a current switch. The amplified signal obtained between the collectors of the transistors T 71  and T 81  is further amplified by the sense amplifier SA. 
     In order to avoid unnecessary writing in the half-selected memory cells MC 12 , . . . , and MC 1n , the driving transistors in these half-selected memory cells must be completely turned off. For this purpose, the pull-up circuits PLP 2 , . . . , PLP n  operate so that the transistors T 62 , . . . , and T 6n  included therein are turned on. Thus, the transistors T 42 , . . . , and T 4n  are cut off, and, therefore, the bases of the transistors T 62 , . . . , and T 6n  are at the H level. Thus, the bit lines B 21 , B 22 , . . . , B n1 , and B n2  are charged up to the H level by the power supply line V cc  through respective transistors T 62 , . . . , and T 6n . This ensures the cut-off states of the driving transistors in the memory cells MC 12 , . . . , and MC 1n . 
     The problem in the conventional static bipolar RAM of FIG. 1A will now be described. Referring to the bit selection circuit BSW i  (i=1, 2, . . . , or n), when one column C i  is selected, a column selection signal is applied to the node YB i  commonly connected to the bases of the transistors T 2i , T 3i , T 4i , and T 5i  in the bit selection circuit. When the column changes its state from a nonselected state to a selected state, the column selection signal rises from the L level to the H level. When the column changes its state from a selected state to a nonselected state, the column selection signal falls from the H level to the L level. In the conventional memory, there is a disadvantage in that the falling speed of the potential at the node YB i  is low, so that the switching speed of the columns is low. 
     More specifically, the bit driver circuit BD i  provided in each column comprises an emitter follower transistor T 1i , a level shifting diode DI i , and a level shifting current source IB i . When the potential at the terminal Y i  is at the H level, the transistor T 1i  turns on to cause the node YB i  to be at the H level. When the terminal Y i  is at the L level, the transistor T 1i  turns off so that the node YB i  goes to the L level. The H level at the node YB i  is set by the transistor T 1i  and the diode DI i  to a predetermined level lower than the potential at the collector of the transistor T 2i , T 3i , T 4i , or T 5i , so that the transistors T 2i , T 3i , T 4i , and T 5i  are not saturated. The bases of the transistors T 2i , T 3i , T 4i , and T 5i , the junction portion of the diode DI i , and the wiring line for these bases have a parasitic capacitance CB i . When the column C i  changes its state from a selected state to a nonselected state, the transistor T 1i  is turned off so that the potential at the node YB i  falls. During the fall of the potential at the node YB i , the charges stored in the parasitic capacitance CB i  should be discharged. Recent technology has increased memory capacities more and more with a corresponding increase in the number of the columns. The increase in the number of columns has been accompanied by an increase in the number of the current sources IB i  as well, so that the power consumption tends to be increased. Also, the lengths of the wiring lines tend to become longer, so that the parasitic capacitance tends to increase. In order to suppress the increase in the power consumption, the value of the current source IB i  should be as small as possible. However, the smaller the value of the current source IB i , the longer the time required for discharging the parasitic capacitance CB i . Accordingly, the falling speed of the potential at the node YB i  becomes low. 
     FIG. 2 is a time chart illustrating the changes of the potentials of the bit lines. In FIG. 2,  1  represents a curve of the potential at the node YB i  when the column C i  changes from its selected state to the nonselected state. As can be seen from the curve  1 , the falling time T is too long. A curve  2  is the curve of the potential at the node YB i  when the column changes from its nonselected state to the selected state. As can be seen from the curve  2 , the rising time T 1  is relatively small regardless of the value of the current IB i  because the emitter-follower transistor T 1i  forces the node YB i  to be driven to the H level. In a reading operation, the sense amplifier SA can detect, through the pre-sense amplifier, the potential difference between the bit lines B i1  and B i2  only after the potential difference between the curves  1  and  2  exceeds a predetermined value ΔV. Therefore, the falling speed of the potential at the node YB i  directly affects the access time of the memory. 
     The above-mentioned problem becomes more and more serious with the increase in the memory capacity, because the value of the current source IB i  must be increasingly minimized so as to save on power consumption, along with the increase in the number of columns. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a static semiconductor memory device which overcomes the above-described disadvantages of the conventional memory. 
     An object of the present invention is to provide a static semiconductor memory device in which high speed operation is realized by decreasing the fall time of the potential at the node YB i  and in which low power consumption is realized by decreasing the value of the current source IB i . 
     According to the present invention, there is provided a static semiconductor memory device comprising: a plurality of memory cells arranged in a matrix having columns and rows, each memory cell comprising two driving transistors connected in intersection; a plurality of word lines connected to the memory cells and arranged in the row direction; a plurality of bit lines connected to the memory cells and arranged in the column direction, each bit line being adapted to receive a current for reading information stored in or for writing information to be stored in the memory cells; a plurality of bit selection circuits provided in the columns, respectively, each of the bit selection circuits being adapted to receive a column selection signal having a high (or low) reference potential, when the corresponding column is selected, for supplying a current from a common current source to the selected column; and a plurality of bit driver circuits provided in the columns, respectively. Each of the bit driver circuits is adapted to cause the column selection signal to have the high (or low) reference potential when the corresponding column is selected. The static semiconductor memory device further comprises: a discharge current source; a plurality of discharge paths, each of the discharge paths being connected between one of the bit selection circuits and the discharge current source, whereby, when a column is switched from a selected state to a nonselected state, the potential of the column selection signal is lowered (or highered) through the discharge path. 
     It is preferable that each of the bit selection circuits comprises a transistor having an emitter connected to the common current source, a base being adapted to receive the column selection signal, and a collector connected to the corresponding column, whereby all of the transistors included in the respective bit selection circuits constitutes a current switch. One end of each of the discharge paths is connected to the base of the transistor in the corresponding bit selection circuit. 
     It is also preferable that each of the discharge paths comprises a discharge diode having an anode connected to the base of the transistor in the corresponding bit selection circuit and a cathode connected to the common current source. 
     It is further preferable that each of the discharge paths comprises a delay circuit and a discharge transistor having a collector connected to the base of the transistor in the corresponding bit selection circuit, an emitter connected to the common current source, and a base adapted to receive the column selection signal through the delay circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing objects and other objects as well as characteristic features of the invention will become more apparent and more readily understandable by the following description when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof and wherein: 
     FIG. 1A is a circuit diagram of a main portion of a conventional static bipolar RAM; 
     FIG. 1B is a detailed circuit diagram of a memory cell in the circuit of FIG. 1A; 
     FIG. 2 is a graph of the changes of the potentials of the bit lines, in the conventional example, and according to the present invention; 
     FIG. 3 is a circuit diagram of a static bipolar RAM, according to the present invention; 
     FIG. 4 is a circuit diagram of a part of the static bipolar RAM, according to an embodiment of the present invention; 
     FIG. 5 is a circuit diagram of a part of the static bipolar RAM, according to another embodiment of the present invention; 
     FIG. 6 is a circuit diagram of a part of the static bipolar RAM, according to still another embodiment of the present invention; and 
     FIG. 7 is a circuit diagram of a part of the static bipolar RAM, according to still another embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3 is a circuit diagram of a static bipolar RAM, according to the present invention. The difference between FIGS. 1 and 3 is that, in FIG. 3, a discharge path DIS i  is connected to the bases of the transistors T 2i  through T 5i  in the bit selection circuit BSW i . The other ends of the discharge paths DIS 1 , . . . , and DIS n  are commonly connected through a discharge signal line KDIS to a discharge current source IDIS. 
     FIG. 4 is a circuit diagram of a part of the static bipolar RAM, according to an embodiment of the present invention. In FIG. 4, a diode DD i  is employed as a practical embodiment of each discharge path DIS i . All of the diodes DD 1 , . . . , and DD n  and the discharge current source IDIS constitute a current switch so that only one of the diodes is turned on to conduct a discharge current IDIS. The anode potential of the conducted diode, i.e., the potential at the node YB i  in the selected column, is the highest of all the anode potentials of the other diodes. Therefore, a current IB i  +IDIS is conducted through the node YB i  in the selected column; and only the current IB i  is conducted through each node YB i  in the other nonselected columns. Because of the large current IB i  +IDIS in the selected bit driver circuit BD i , the parasitic capacitance CB i  is very rapidly discharged during the early stage of a switching when the column is switched from its selected state to the nonselected state. This causes a rapid fall of the potential at the node YB i  and accordingly the potential of the bit line B i1  when the column is switched from the selected state to the nonselected state, as illustrated by a dotted curve 2 in FIG. 2. After the dotted curve 2 crosses the rising curve 4, the column is changed to the nonselected state so that only the current IB i  contributes to discharge the parasitic capacitance CB i . Therefore, after that cross point, the dotted curve 2 falls as slowly as the conventional fall curve 1. As a result, the time required for obtaining the predetermined potential difference ΔV between the bit lines B i1  and B i2  is T 2  which is far shorter than the time T 1  in the conventional circuit of FIG. 1. Thus, high speed switching of the columns can be obtained, and, accordingly, the access time of the memory is shortened. Although the discharge current source IDIS is added, the power consumption of the memory is not significantly increased but rather is decreased in comparison with the power consumption in the conventional memory, because, in the circuit of FIG. 3, it is possible to make the current drawing capability of each current source IB i  in each bit drive circuit BD i  smaller than that in the circuit of FIG. 1. 
     FIG. 5 is a circuit diagram of a part of the static bipolar RAM, according to another embodiment of the present invention. In FIG. 5, the cathode of the diode DD i  in each discharge path DIS i  is connected to the signal line K 3  connected to the emitter of the transistor T 3i  so that the discharge signal line KDIS in FIG. 4 is eliminated. In place of the current sources I 3  and IDIS, a current source I 3  &#39; having a value I 3  +IDIS is connected to the signal line K 3 . The ratio between the current I 3  which flows through the transistor T 3i  to the pre-sense amplifier PSA i  and the current IDIS which flows through the discharge diode DD i  is determined by the ratio between the areas of the transistor T 3i  and the diode DD i . Therefore, the ratio of these areas is designed to have a predetermined value. The diode DD i  is formed by a junction portion between the emitter and the base of a conventional transistor. In place of connecting the cathode of the diode DD i  to the signal line K 3  in the circuit of FIG. 5, the cathode may be connected to the signal line K 4  connected through the transistors T 41 , . . . , and T 4n  to the pull-up circuits PLP 1 , . . . , and PLP n , respectively, which serve to charge up the nonselected bit lines. 
     FIG. 6 is a circuit diagram of a part of a static bipolar RAM, according to still another embodiment of the present invention. In FIG. 6, the base of the transistor T 61  in the pull-up circuit PLP 1  is commonly connected to the collectors of transistors T P1  and T P2 . The base and the emitter of the transistor T P1  are connected to the base and the emitter of the transistor T 71 , respectively. Also, the base and the emitter of the transistor T P2  are connected to the base and the emitter of the transistor T 81 , respectively. The emitters of the transistors T 71 , T P1 , T p2 , and T 81  are commonly connected to the collector of a transistor T 31  &#39; which takes the place of the transistors T 31  and T 41  in the circuit of FIG. 5. The emitter of the transistor T 31  &#39; is connected through the signal line K 3  to a current source I 3  &#39; which takes the place of the current sources I 3  and I 4  in the circuit of FIG. 4. The other columns have the same circuit configurations as the first column described above. This circuit configuration decreases the number of the transistors in each bit selection circuit BSW i  to three so that the parasitic capacitance CB i  due to the base capacitances of these transistors is decreased in comparison with the circuit of FIG. 5. Further, the number of signal lines K 2 , K 3 , and K 5 , each of which is commonly connected to all of the bit selection circuits BSW 1 , . . . , and BSW n , is decreased to three. The bit line pull-up circuit PLP i  receives a current from the current source I 3  &#39; through the signal line K 3 , the transistor T 3i  &#39; and the transistor T P1  or T P2 . The pre-sense amplifier PSA i  receives a current from the current source I 3  &#39; through the transistor T 3i  &#39;. The discharge diode DD i  is connected between the base and the emitter of the transistor T 31  &#39; in a manner similar to the circuit of FIG. 5. 
     In the foregoing embodiments, however, the discharge current IDIS is supplied to the node YB i  in the column, which is switched from the selected state to the nonselected state, only in the first half switching period because the discharge current IDIS flows through a discharge path DIS i  connected to the node YB i  which has the highest potential. Therefore, as illustrated in FIG. 2 by the dotted curve 2, after the cross point of the falling curve 2 and the rising curve  2 , the falling speed of the curve 2 is lowered, with the result that a sufficiently high speed operation cannot be realized. 
     In order to obtain a higher speed of operation, an additional embodiment is presented according to the present invention. 
     FIG. 7 is a circuit diagram of a part of a static bipolar RAM, according to the additional embodiment of the present invention. The differences between the circuit of FIG. 4 and FIG. 7 are that, in FIG. 7, each discharge path DIS i  comprises a transistor TDIS i  having a collector connected to the node YB i  and a base connected through a resistor RDL i  to the node YB i . A delay capacitor CDL i  is connected to the base of the transistor TDIS i . The emitter of the transistor TDIS i  is connected through the signal line KDIS to the current source IDIS. In each bit drive circuit BD i , the current source IB i  is eliminated. When a column is switched from the selected state to the nonselected state, the charge on the node YB i  in that column is discharged through the transistor TDIS i  in that column so that the potential at the node YB i  is lowered. However, the fall of the base potential BDL i  of the transistor TDIS i  in that column is delayed in comparison with the fall of the potential at the node YB i  due to a time constant derived from the resistor RDL i  and the capacitor CDL i . Therefore, the transistor TDIS i  in that column continues to discharge after the potential at the node YB i  is sufficiently lowered. On the other hand, when another column is switched from the nonselected state to the selected state, the rise of the base potential BDL i  of the transistor TDIS i  in this column is also delayed in comparison with the rise of the potential at the node YB i  due to the time constant derived from the resistor RDL i  and the capacitor CDL i . Therefore, the transistor TDIS i  in this column is kept cut-off after the potential at the node YB i  in that column sufficiently rises. Thus, as illustrated in FIG. 2 by a dash dot curve 3, the falling curve 3 falls more rapidly than the curve 2 because the discharge current IDIS flows through the discharge path even after the falling curve 3 crosses with the rising curve  2 . As a result, the time required for obtaining the predetermined difference between the bit lines B i1  and B i2  is T 3 , which is the shortest of all the embodiments. 
     From the foregoing description, it will be apparent that, the present invention enables the fabrication of a static semiconductor memory device, having a large memory capacity, in which the power consumption is decreased and high speed column switching is realized. 
     It should be noted that the present invention is not restricted to the foregoing embodiments, but various changes and modifications are possible without departing from the essential spirit of the invention. For example, although the column selection signal changes from the high potential to the low potential when the column is switched from the selected state to the nonselected state, the present invention may also be applied to the case where the column selection signal changes from the low potential to the high potential when the column is switched from the selected state to the nonselected state.