Abstract:
A communications management system uses a single timer to control the transmission of ATM cells along a plurality of virtual paths/virtual channels (VPs/VCs). The system includes first and second memories, a time counter that records when a data packet is received from a specific VP/VC, and a control unit that controls transmission of data in the received packet based on whether another packet from the same VP/VC was received within a predetermined time-out period. By using a single timer, the system and an associated method reduce hardware and operating constraints which limit performance of conventional ATM transmission systems. This translates into improved capacity in terms of the numbers of virtual paths and virtual channels the system is able to manage.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a communication system, and more particularly to an apparatus and a method for operating a timer of an asynchronous transfer mode (ATM) system.  
           [0003]    2. Background of the Related Art  
           [0004]    An ATM system is a packet-mode transfer mode system based on an asynchronous time division multiplexing method, where a band is assigned only when information to be transmitted exists. In such an ATM system, the fundamental unit for transmitting information is a cell which has a fixed length of 53 bytes. The ATM cell is 53 bytes. Five bytes out of the 53 bytes are used for a header field and the remaining 48 bytes are used for a payload field for transmitting information. The header field includes: a virtual path identifier (VPI) and a virtual channel identifier (VCI) for identifying a connection to which the ATM cell belongs; cell loss priority (CLP) information for indicating whether a cell is allowed to be discarded or not during congestion; and header error check (HEC) information to be used for detecting and controlling errors in the header.  
           [0005]    The structure of a service protocol layer of an ATM system is shown in FIG. 1. As shown, the service protocol layer of the ATM system includes an ATM adaptation layer (AAL), an ATM layer, and an ATM physical layer. The AAL segments and reassembles the ATM cell. The ATM layer generates and removes the header of the ATM cell and multiplexes and demultiplexes the ATM cell. The ATM physical layer controls the speed of the ATM cell, generates and verifies an HEC header sequence, and synchronizes a cell. The AAL will now be described in detail.  
           [0006]    When various user application data items are received from an upper layer, the AAL controls the received data to have a fixed length of 48 bytes and assembles and segments the received data. Unlike the ATM layer, the AAL is not dependent on the application of real data but the application of the upper layer.  
           [0007]    The AAL also provides various service classes according to characters of the data received from the upper layer. The ATM system can, for example, transfer a service having a constant bit rate (CBR) such as an audio service and a service having a variable bit rate (VBR) such as data service.  
           [0008]    An AAL type 1, used for a broad band integrated services digital network (B-ISDN) using the CBR, is a design for an application of transmitting a rate equal to the transferred bit rate to a receiving side, while guaranteeing the rate equal to the transferred bit rate and a design for an excellent quality of video or audio data service.  
           [0009]    An AAL2, which transfers video/audio data not in a fixed rate but in a variable rate, is a design for providing functions almost identical to the functions of the AAL1.  
           [0010]    AAL3 and 4 are protocols for transferring a connection-oriented data packet and a non-connection-oriented data packet. A connection method for these methods is formed of a point-to-point or a point-to-multipoint.  
           [0011]    An AAL5 is a protocol that can be applied to connection-oriented data communication and signaling and is a design for a confirmation type data communication service, where an error or a flow must be controlled by re-transmission. The present invention can be applied to at least AAL2 and AAL5 among the various types of the AAL. Examples applied to the AAL2 service will now be described.  
           [0012]    The AAL2 is generally realized as a software program due to its complexity. When the AAL2 is realized as hardware in order to increase speed, it is significantly difficult to support multiple virtual paths/virtual channels (VP/VC). In particular, because the AAL2 supports real time data, a timer is used for each VP/VC in order to prevent the delay of a data transfer.  
           [0013]    [0013]FIG. 2 shows an example of the structure of a timer operating apparatus in a conventional AAL2 protocol service logic. The timer operating apparatus includes an AAL2 service logic  10  for generating the payload of an AAL2 ATM cell using AAL2 data received from an upper layer, a data memory  20  for temporarily storing the AAL2 data by each VP/VC, and a plurality of VP/VC timers  30 A through  30 N which are in one-to-one correspondence with the VP/VCs for checking lapses of time for storing AAL2 data for respective ones of the VP/VCs. Each of the VP/VC timers  30 A through  30 N is formed of a binary counter having a uniform size.  
           [0014]    The operation of the timer operating apparatus in the conventional AAL2 protocol service logic having the above structure will now be described as follows.  
           [0015]    A case, where the AAL2 data is received from the upper layer of the AAL and is transferred to the ATM layer that is a lower layer, will be described. Description of a case, where the AAL2 data is received from the ATM layer and is transferred to the upper layer, will be omitted.  
           [0016]    An AAL2 common part sublayer (CPS) packet input for a service supporting the VBR such as some isochronous video or audio traffic is generated as an AAL2 CPS protocol data unit (PDU) by the AAL2 service logic  10  and is transmitted to the ATM layer through an ATM link. The AAL2 service logic  10  includes a CPS layer for dividing the AAL2 CPS packet into the AAL2 CPS PDUs of 48 bytes and assembling the AAL2 CPS packet to the AAL2 CPS PDU of 48 bytes. The size of the AAL2 CPS packet is variable. The maximum length of the AAL2 CPS packet is 45 through 64 bytes.  
           [0017]    When the AAL2 service logic  10  generates the AAL2 CPS PDU (the payload of the ATM cell) of 48 bytes, in the case where the size of the AAL2 CPS packet does not fill the payload of the ATM cell, the AAL2 service logic  10  waits for a next AAL2 CPS packet and multiplexes the next AAL2 CPS packet with the previous AAL2 CPS packet when the next AAL2 CPS arrives, to thus create the payload of the ATM cell, in order to effectively use the ATM link.  
           [0018]    At this time, because the AAL2 protocol supports a real time service, time spent on waiting for the next AAL2 CPS packet must be restricted. For example, the payload of the ATM cell must be generated and transmitted to the ATM layer within a restricted time (for example, 20 ms). Therefore, when the AAL2 CPS packet does not arrive within 20 ms after one AAL2 CPS packet arrives, the AAL2 service logic  10  generates the AAL2 CPS PDU only by the current AAL2 CPS packet without waiting for the next AAL2 CPS packet.  
           [0019]    The AAL2 service logic  10  checks whether the restricted time for generating the AAL2 CPS PDU of each VP/VC has lapsed using the timer that one-to-one corresponds to the VP/VC. When the restricted time has passed, the AAL2 service logic  10  generates the AAL2 CPS PDU only based on the current AAL2 CPS (i.e., without waiting for the next AAL2 CPS) and transmits the generated AAL2 CPS PDU to the ATM layer through the ATM link. The above processes will now be described in greater detail.  
           [0020]    When the AAL2 CPS packet of VP/VC #1 is received from the upper layer through the user interface, the AAL2 CPS packet of the VP/VC #1 is temporarily stored in the data memory  20  and the VP/VC #1 timer  30 A starts counting at the same time, by the control of the AAL2 service logic  10 . When the AAL2 CPS packet of VP/VC #2 is received from the upper layer, the AAL2 CPS packet of the VP/VC #2 is temporarily stored in the data memory  20  and the VP/VC #2 timer  30 B starts counting at the same time, by the control of the AAL2 service logic  10 .  
           [0021]    When the AAL2 service logic  10  receives the AAL2 CPS packet of the corresponding VP/VC, the AAL2 service logic  10  temporarily stores the AAL2 CPS packet of the corresponding VP/VC in the corresponding region of the data memory  20  and drives the corresponding VP/VC timer, to thus check time, for which the AAL2 CPS packet of the corresponding VP/VC is stored.  
           [0022]    When the VP/VC #1 timer  30 A times out, the AAL2 service logic  10  does not wait for the AAL2 CPS packet of the next VP/VC #1. Instead, logic  10  generates the AAL2 CPS PDU by using the AAL2 CPS packet of the VP/VC #1, which is stored in the data memory  20 , and by filling the remaining bits with a specific value, for example, 0, and transfers the generated AAL2 CPS PDU to the ATM layer through the ATM link.  
           [0023]    In the timer operating apparatus of the conventional AAL2 service logic, the number of timers that can be realized in a hardware logic device is restricted because the timer operating apparatus includes a plurality of timers each of which one-to-one corresponds to each VP/VC. Because the number of timers that correspond to each VP/VC is restricted, the number of supportable VP/VCs is restricted. Accordingly, the capacity of a system is restricted  
         SUMMARY OF THE INVENTION  
         [0024]    An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.  
           [0025]    Accordingly, an object of the present invention is to provide an apparatus and method for operating a timing device of a communication system in a way that increases transmission capacity and reduces operating and/or hardware restrictions compared with timing units of conventional communications systems.  
           [0026]    Another object of the present invention is to provide a method for controlling a timing apparatus of an asynchronous transfer mode (ATM) system, where the number of timers in the apparatus does not restrict the number of virtual paths/virtual channels (VPs/VCs) that can be handled by the system. The aforementioned object is realized, in at least one way, by removing the need to have a one-to-one correspondence between a plurality of timers and a plurality of virtual paths/virtual channels in the apparatus, and more specifically by replacing the multiple timers used in a conventional timing device with a single timer which records receiving times of packets received from multiple virtual paths/virtual channels. The single timer then cooperates with a control unit to transmit the packets within a certain time period. By using a single timer for multiple VPs/VCs, the present invention advantageously removes the operating and hardware limitations which constrain the performance of conventional timing devices.  
           [0027]    To achieve these and other advantages and in accordance with the purposes of the present invention, as embodied and broadly described herein, there is provided an apparatus for operating timer of a communication system, comprising a service logic for receiving data and generating a base address for temporarily storing the data; a data memory for temporarily storing the data by the destination according to the base address; a time counter for outputting a receiving time of the data; a timer input controller for inputting the receiving time and the base address; a timer memory for storing the inputted receiving time and base address; and a timer output controller for periodically detecting the stored receiving time.  
           [0028]    The present invention is also an apparatus for operating timer of an ATM system, comprising an ATM adaptation layer (AAL) 2 service logic for receiving an AAL2 packet by each virtual path/virtual channel (VP/VC), outputting a base address of the AAL2 packet to be stored temporarily, and generating a payload of an AAL2 ATM cell using the AAL2 packet; a data memory for temporarily storing the received AAL2 packet by each VP/VC according to the base address; a time counter for outputting a receiving time of the AAL2 packet; a timer input controller for inputting the base address and the receiving time; a timer memory for storing the inputted base address and receiving time by each VP/VC; and a timer output controller for predetermining a restricted time for periodically generating the packet, and detecting the timer memory periodically based on the restricted time.  
           [0029]    The present invention is also a method for operating timer of an AAL2 service logic in an ATM system, comprising the steps of outputting a receiving information when an AAL2 packet is received; recording a receiving time of the AAL2 packet by each VP/VC, according to the receiving information; checking the recorded receiving time of the AAL2 packet by each VP/VC; reporting that a restricted time of a VP/VC has lapsed, when there exists the VP/VC of which the restricted time for periodically generating a payload of an AAL2 ATM cell has lapsed; and generating the payload of the AAL2 ATM cell by the AAL2 packet of the reported VP/VC without waiting for the arrival of a next AAL2 packet of the VP/VC according to the report.  
           [0030]    The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.  
       
    
    
     DESCRIPTION OF THE DRAWINGS  
       [0031]    The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute part of this specification, illustrate embodiments of the invention and together with the written description serve to explain principles of the invention. In the drawings:  
         [0032]    [0032]FIG. 1 shows a service protocol layer structure of a common asynchronous transfer mode (ATM) system;  
         [0033]    [0033]FIG. 2 shows an example of the structure of a timer operating apparatus in a conventional ATM adaptation layer (AAL)2 protocol service logic;  
         [0034]    [0034]FIG. 3 shows an example of a timer operating apparatus of an AAL2 service logic in an ATM system according to an embodiment of the present invention;  
         [0035]    [0035]FIG. 4 is a flowchart showing the operation of a timer input controller according to the embodiment of the present invention; and  
         [0036]    [0036]FIG. 5 is a flowchart showing the operation of a timer output controller according to the embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0037]    A preferred embodiment of the present invention will now be described with reference to the attached drawings.  
         [0038]    [0038]FIG. 3 shown an example of the structure of a timer operating apparatus of an asynchronous transfer mode (ATM) adaptation layer (AAL)2 service logic in an ATM system according to an embodiment of the present invention. As shown, the timer operating apparatus includes an AAL2 service logic  100  for generating a base address for temporarily storing AAL2 data received from an upper layer for each virtual path/virtual channel (VP/VC), and for periodically generating the payload of an AAL2 ATM cell using the stored AAL2 data. A data memory  200  temporarily stores the AAL2 data for each VP/VC according to the control of the AAL2 service logic  100 . In addition to these features, the timer operating apparatus includes a time counter  300  for outputting a receiving time of the AAL2 data, and a timer input controller  400  for calculating a corresponding address of a timer memory  500  using the base address when the base address in each VP/VC is generated by the AAL2 service logic  100  and for inputting the base address and the receiving time in the corresponding address for each VP/VC. The timer memory  500  stores the inputted base address and receiving time for each VP/VC. Also included is a timer output controller  600  for periodically and sequentially detecting the timer memory  500 , for checking whether restricted time for generating the payload of the AAL2 ATM cell of each VP/VC has lapsed, and for reporting that time is out when the restricted has lapsed.  
         [0039]    The operation of the timer operating apparatus of the AAL2 service logic in the ATM system according to the embodiment of present invention, which has the above structure, will now be described.  
         [0040]    A case where the AAL2 data is received from the upper layer of the AAL and is transferred to the ATM layer that is the lower layer will now be described. Description of a case where the AAL2 data is received from the ATM layer and is transferred to the upper layer will be omitted.  
         [0041]    The timer operating apparatus of the AAL2 service logic according to the embodiment of the present invention includes a time counter  300  for counting time regardless of the number of VP/VCs. The timer input controller  400  manages the time at which an AAL2 common part sublayer (CPS) packet is received by each VP/VC. The timer output controller  600  manages the restricted time.  
         [0042]    When the AAL2 CPS packets are received from the upper layer, the AAL2 service logic  100  temporarily stores the received AAL2 CPS packets in the data memory  200  by each VP/VC and outputs an address of the temporarily stored AAL2 CPS packets to the timer input controller  400  as the base address. The AAL2 service logic  100  needs not store the AAL2 CPS packets in the data memory  200  in the order of VP/VC index. The AAL2 service logic  100  can store the AAL2 CPS packets of the VP/VCs in the order that the AAL2 CPS packets are received.  
         [0043]    The timer input controller  400  calculates the address of the timer memory  500  using the base address by each VP/VC, which is output from the AAL2 service logic  100 , and stores the base address by each VP/VC and the receiving time currently output from the time counter  300  in the calculated address.  
         [0044]    [0044]FIG. 4 is a flowchart showing the operation of the timer input controller  400 . When the base address of the data memory  200  is output from the AAL2 service logic  100  (S 11 ), the timer input controller  400  calculates the corresponding address of the timer memory  500  using the base address (S 12 ) and determines that the AAL2 CPS packet of the corresponding VP/VC is received. The time counting value output from the time counter  300  is considered the receiving time of the AAL2 CPS packet of the VP/VC. The timer input controller  400  records the base address and the receiving time in the corresponding address of the timer memory  500  (S 13 ).  
         [0045]    The timer input controller  400  can obtain the corresponding address of the timer memory  500  by adding a uniform offset value to the base address of the data memory  200 . Therefore, the timer input controller  400  can access the corresponding address of the timer memory  500 , where the base address and the receiving time of each VP/VC are stored, using only the base address of the data memory  200 .  
         [0046]    The timer output controller  600  periodically and sequentially detects the timer memory  500 . Therefore, it is checked whether the restricted time of each VP/VC has lapsed by comparing the receiving time of each VP/VC, which is stored in the data memory  500 , with the current counting value, which is output from the time counter  300 . When the restricted time for generating the payload of the AAL2 ATM cell of a specific VP/VC has lapsed, the timer output controller  600  reports the AAL2 service logic  100  that the time of the VP/VC is out and outputs the base address of the VP/VC.  
         [0047]    The AAL2 service logic  100 , which receives the report that the time of the VP/VC is out, does not wait for a next AAL2 CPS packet of the VP/VC, whose time is out, to be received. Rather, service logic  100  generates an AAL2 CPS protocol data unit (PDU) based only on the AAL2 CPS packet of the corresponding VP/VC which is temporarily stored in the base address received from the timer output controller  600 , and then transfers the generated AAL2 CPS PDU to the ATM layer. The above processes will be now described in more detail.  
         [0048]    When the AAL2 CPS packet of VP/VC #1 is received from the upper layer, the AAL2 service logic  100  temporarily stores the received AAL2 CPS packet of the VP/VC #1 in the data memory  200  and outputs the base address of the temporarily stored data memory  200  to the timer input controller  400 .  
         [0049]    The timer input controller  400  accesses an address of the timer memory  500  using the base address of the VP/VC #1, which is received from the AAL2 service logic  100 , and records the base address of the VP/VC #1 and the receiving time currently output from the time counter  300 .  
         [0050]    In a case where the restricted time for the AAL2 service logic  100  generating the AAL2 CPS PDU is 20 ms for a real-time service, when the next AAL2 CPS packet of the VP/VC #1 arrives within 20 ms, the AAL2 service logic  100  generates the AAL2 CPS PDU using the AAL2 CPS packet of the VP/VC #1, which has just arrived and the AAL2 CPS packet of the VP/VC #1 which is temporarily stored in the data memory  200 . Service logic  100  then informs the timer input controller  400  that the next AAL2 CPS packet of the VP/VC #1 has arrived.  
         [0051]    The timer input controller  400  updates the receiving time of the VP/VC #1, which is stored in the timer memory  500 , to the current counting value output from the time counter  300 . The timer input controller  400  also records the time, at which the AAL2 CPS packet arrives, in each VP/VC according to the control of the AAL2 service logic  100 .  
         [0052]    As shown in FIG. 5, the timer output controller  600  periodically and sequentially detects the timer memory  500 . More specifically, the timer output controller  600  considers the first address of the timer memory  500  as a current address and reads a receiving time of a corresponding VP/VC from the current address (S 21 ). The timer output controller  600  subtracts the read receiving time from the current output value of the time counter  300  and compares whether the subtracted resulting value is larger than the restricted time(S 22 ). When the subtracted resulting value is not larger than the restricted time, the timer output controller  600  identifies the restricted time has not lapsed, increases the current address to a predetermined degree (S 24 ) and reads a receiving time of a corresponding VP/VC from the increased address (S 21 ).  
         [0053]    When the subtracted resulting value is larger than the restricted time, the timer output controller  600  identifies that the restricted time for the corresponding VP/VC has lapsed, fetches a base address of the corresponding VP/VC from the current address, includes the base address in a time-out signal, and outputs the time-out signal to the AAL2 service logic  100  (S 25 ). The timer output controller  600  deletes the base address and the receiving time of the corresponding VP/VC, which are stored in the current address (S 26 ).  
         [0054]    The timer output controller  600  manages the restricted time for generating the AAL2 CPS PDU of each VP/VC by the above-mentioned method. The AAL2 service logic  100  does not wait for the arrival of the next AAL2 CPS packet of the corresponding VP/VC, but rather generates the AAL2 CPS PDU by using the AAL2 CPS packet of the corresponding VP/VC of the data memory  200  and by filling the remaining bits with a specific value, for example, 0, according to a report of the timer output controller  600  indicating that the time of the VP/VC is out. The AAL2 service logic  100  transfers the generated AAL2 CPS PDU to the ATM layer through the ATM link.  
         [0055]    The apparatus and method for operating a timer apparatus of a communication system according to the present invention is advantageous because it is not restricted in the manner of conventional timing systems. Instead of using a separate timer for each of a plurality of virtual paths/virtual channels, the present invention uses a single timer for all VP/VCs in the system. A timer input controller then manages the packet arrival time (receiving time) for each VP/VC and stores this time in a timer memory. A timer output controller then manages the restricted time for each VP/VC by searching the timer memory for time-outs. If a time-out occurs and an additional data packet has not been received on that VP/VC, the data packet is transmitted to avoid the creation of a data transfer delay. Through these features, the present invention is able to achieve greater transmission capacity in terms of the number of VP/VCs it can handle, because there is no restriction of the number of timers which can be employed. Also, it is possible to improve efficiency of the operation of timers of the system by not restricting the number of timers in the communication system that requires a large number of timers.  
         [0056]    The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.