Abstract:
A dynamic random access memory device having an input/output load connected between a pair of input/output lines and a control circuit used to generate an internal /RAS signal having a reset transition delayed with respect to the same transition of the external /RAS signal. The internal /RAS signal controls at least a word signal applied to a transistor of a selected memory cell and an enable signal applied to an enable transistor, whereby the time the transistor of the memory cell and the enable transistor become non-conductive is delayed with respect to the time at which a transfer transistor connected between each pair of bit lines and the input/output lines becomes non-conductive.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a dynamic RAM (Random Access Memory) device. 
     Recent dynamic RAM devices have commonly employed what is termed a &#34;static column&#34; mode to increase the read-out speed and reduce the cycle time of the device. To realize this mode, a columnar arrangement of static circuits is employed, similarly to a static RAM device, which makes it unnecessary to provide a precharge circuit as in the case of other dynamic RAM devices. That is, each input/output line is pulled up to a predetermined potential through an input/output load by a supply potential V cc  so that it cannot be swung within the full range from ground potential to V cc . As a result, it is possible to make the column decoder a static-type decoder. 
     FIG. 1 is a circuit diagram of a typical D-RAM (Dynamic Random Access Memory) device. The D-RAM includes a plurality of memory cells, pairs of bit lines, word lines, sense amplifier circuits, a pair of input/output lines, etc. In FIG. 1, each memory cell includes one N-type MOS (Metal Oxide Semiconductor) translator 4 and one charge storage device 12 such as a capacitor. The transistor 4 is connected between a respective bit line BL or /BL (&#34;/&#34; denoting negation, i.e., the complementary form of the signal, as shown in the drawings by the more conventional bars over the signal designations) and one electrode of the charge storage device 12. The gate electrode of the transistor 4 is connected to a corresponding word line WL. The other electrode of the charge storage device is grounded. 
     Each sense amplifier circuit 16 has two driver N-type MOS transistors 5 and 6 and two load P-type MOS transistors 2 and 3. A first driver transistor 5 is connected between the bit line BL and a first common node 16a, and a gate electrode of the transistor 5 is connected to the other bit line /BL. A second driver transistor 6 is connected between the other bit line /BL and the first common node 16a, and a gate electrode thereof is connected to the one bit line BL. A first load transistor 2 is connected to the bit line BL. A first load transistor 2 is connected between the bit line BL and a second common node 16b, and a gate electrode thereof is connected to the other bit line /BL. A second load transistor 3 is connected between the bit line /BL and the second common node 16b, and the gate electrode thereof is connected to the bit line BL. 
     A first enable N-type MOS transistor 7 is connected between the first common node 16a and ground, and a gate electrode thereof receives a first enable signal S 0 . A second enable P-type MOS transistor 1 is connected between the second common node 16b and a supply potential node, and a gate electrode thereof receives a second enable signal /S 0 . 
     An equalizer circuit 14 is coupled between the two bit lines BL and /BL for equalizing the potential between the two lines prior to information stored in the memory cell being read out when the cell is selected for read out. The equalizer circuit is implemented with an N-type MOS transistor connected between the bit lines BL and /B, a gate electrode thereof receiving an enabling signal. 
     A first transfer N-type MOS transistor 8 is connected between the bit line BL and the uncomplemented input/output line I/O. The gate electrode of the transistor 8 receives a column signal Y i  generated by a column decoder 15. A second transfer N-type MOS transistor 9 is connected to the complemented bit line /BL and the complemented input/output line /I/O. The gate electrode of this transistor is connected to the gate electrode of the first transistor 8 and receives the column signal Y i . 
     An input/output load 13, composed of two N-type MOS transistors 10 and 11, is connected to the two input/output lines I/O and /I/O. The first load transistor 10 is connected between the input/output line I/O and a supply potential node, and the gate electrode thereof is connected to the supply potential node. The second load transistor 11 is connected between the complemented input/output line /I/O and the supply potential node, while the gate electrode of this transistor is connected to the supply potential node. 
     FIG. 2 shows waveforms in the conventional D-RAM device. 
     In the operation of this device, it is assumed that the selected memory cell connected to the bit line BL has stored therein a &#34;1&#34; data bit. The potential of the bit lines BL and /BL will be about half the supply potential. The external signal /RAS goes from an &#34;H&#34; (high) level to a &#34;L&#34; (low) level, as shown in waveform (a), at time t 0 . Then, at time t 1 , the word signal on the selected word line WL goes from &#34;L&#34; to &#34;H&#34;, according to the change in /RAS, as shown in waveform (b). As a result, the transistor 4 of the selected memory cell is rendered conductive, and the potential of the bit line BL goes up, as shown in waveform (c). At time t 2 , the potential of the first enable signal S 0  goes from &#34;L&#34; to &#34;H&#34; and the potential of /S 0  goes to &#34;L&#34; from &#34;H&#34;, as shown in waveforms (d) and (e) in FIG. 2. Thus, the first and second enable transistors 7 and 8 are placed in the conductive state and the sense amplifier is also enabled. 
     The sense amplifier 16 amplifies the potential between the two bit lines BL and /BL. At this time, the potential of the bit line BL is at the &#34;H&#34; level (V cc ), while the potential on the complemented bit line /BL is an &#34;L&#34; level (ground), as shown in waveform (c). At time t 3 , the column signal Y i  from the column decoder 15 goes high, as seen in waveform (f), and the first and second transfer transistors 8 and 9 are rendered conductive. Accordingly, the potential of the bit lines BL and /BL is transferred to the input/output lines I/O and /I/O, respectively. That is, the potential of I/O is the &#34;H&#34; level and the potential of /I/O is an intermediate level, as shown in waveform (g). 
     Because current flows from the supply potential node to ground through the input/output load transistor 11, the input/output line /I/O, and the second transfer transistor 9, the bit line /BL, the second driver transistor 6, the first common node 16a, and the first enable transistor 7, and the drive capacities of the load transistors 10 and 11 and the drive transistors 5 and 6 are substantially the same, the potential of the input/output line /I/O will not swing by the full potential difference between V cc  and ground. That is, the potential of the bit line /BL is limited to the intermediate potential V m , which is less than half the supply potential V cc , as indicated in waveform (c). 
     At time t 4 , the external signal /RAS goes high, as seen in waveform (a). The word signal WL and the column signal Y, go to the &#34;L&#34; level from the &#34;H&#34; level following the /RAS signal, as shown in waveforms (b) and (f). As a result, the transistor 4 of the selected memory cell and the transfer transistors 8 and 9 are rendered nonconductive. The input/output line /I/O goes up to the supply potential, as shown in waveform (g). At time t 5 , the first enable signal S 0  goes down to the &#34;L&#34; level from the &#34;H&#34; level following the change in the external signal /RAS, while the second enable signal S 0  makes the opposite transition, as shown in waveforms (d) and (e), and the first and second enable transistors 7 and 1 are nonconductive. As a result, the sense amplifier 16 is disabled. Subsequently, the equalizer circuit 14 is enabled, and the potentials of the two bit lines BL and /BL are made the same. 
     In the case where the selected memory cell has stored therein a &#34;0&#34; data bit, the operation is the same as described above, except that the potentials of the bit lines BL and /BL will be as shown in waveform (c&#39;). 
     In the D-RAM device constructed and operated as described above, when a &#34;0&#34; data bit is stored in the memory cell, the intermediate potential V m  will remain on the charge storage device at the completion of the read-out operation. As a result, during the following read-out operation, incorrect information can be read out. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a D-RAM device with an input/output load connected to a pair of input/output lines, as in the device described above, but with which the incorrect information cannot be read out. 
     In accordance with this and other objects, the present invention provides a D-RAM device having an input/output load and which has a control circuit which generates an internal /RAS signal in response to the external /RAS signal. The reset timing of the internal /RAS signal is delayed with respect to the external /RAS signal. The internal /RAS signal controls at least the word signal which enables the selected memory cell and the enable signal which enables the sense amplifier, whereby the time the transistor of the memory cell and the enable transistors are rendered nonconductive is delayed from the time at which the transfer transistor is rendered nonconductive. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a typical conventional D-RAM device; 
     FIG. 2 shows a series of waveforms in the D-RAM of FIG. 1; 
     FIG. 3 is a schematic diagram of an internal /RAS signal generating circuit used in the present invention; 
     FIG. 4 is a waveform diagram showing the internal signal /RAS generated in the circuit of FIG. 3; and 
     FIG. 5 is a waveform diagram showing waveforms in a D-RAM constructed in accordance with the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3 is a schematic diagram of a control circuit 100 used to generate an internal /RAS signal, and FIG. 4 is a waveform diagram used to explain the operation of the circuit of FIG. 3. FIG. 5 shows waveforms in the overall D-RAM device according to the present invention. 
     With reference to FIG. 3, inverter 101 receives the external /RAS signal. The number of inverters should be even so as to not invert the external /RAS signal. A delay stage is provided for delaying the output /RAS E  of the inverter 102, and is composed of inverters 103, . . . , 104. A NAND gate 105 receives the output of the delay stage and the output /RAS E  of the inverter 102. An inverter 106 receives as an input, the output of the NAND gate 105. The output of the inverter 106 is an internal /RAS signal, as shown in waveform (c) of FIG. 4. As shown in waveforms (a) and (b) of FIG. 4, the transition from &#34;H&#34; to &#34;L&#34; of the internal /RAS signal occurs at substantially the same time as the same transition in the external /RAS signal. On the other hand, the transition from &#34;L&#34; to &#34;H&#34; of the internal /RAS signal is delayed with respect to the like transition of the external /RAS signal by a time period t d . 
     The internal /RAS signal is used to control the word signal WL and the first and second sense enable signals S 0  and /S 0 , and also to enable the equalizer circuit 14. Hence, the transition from the &#34;H&#34; to the &#34;L&#34; state of the word signal WL, the resetting of the sense amplifier 16, and the setting (activation) of the equalizer circuit 14 are delayed with respect to the &#34;H&#34; to &#34;L&#34; transition of the column signal Y i , but there is no effect on the setting (&#34;L&#34; to &#34;H&#34; transition) of the word signal WL, the setting of the sense amplifier 16, and the resetting (deactivation) of the equalizer circuit 14. 
     The operation of the D-RAM device of the invention will now be explained with reference to FIGS. 1 and 3 to 5. 
     It is assumed that the selected memory cell connected to the bit line BL has stored a &#34;1&#34; data bit. The potential on the bit lines BL and /BL will be about half the supply voltage, as described previously. 
     The external /RAS signal will undergo a transition from &#34;H&#34; to &#34;L&#34;, as shown in waveform (a) in FIG. 5, at time T 0 , and the internal /RAS signal will undergo the same transition at substantially the same time. The word signal on the selected word line WL changes from the &#34;L&#34; level to the &#34;H&#34; level at time T 1  according to the change of the internal /RAS signal, as shown in waveform (b). As a result, the transistor 4 of the selected memory cell will be rendered conductive, and the potential of the bit line BL will rise, as seen in waveform (c). A time T 2 , the first enable signal S 0  transits to the &#34;H&#34; level from the &#34;L&#34; level while the second enable signal /S 0  makes the opposite transition, as shown in waveforms (d) and (e) of FIG. 5. As a result, the first and second enable transistors 7 and 8 are made conductive, whereupon the sense amplifier is enabled. 
     The sense amplifier 16 amplifies the potential of the two bit lines BL and /BL. The potential of the uncomplemented bit line BL is an &#34;H&#34; level (V cc ), while the potential of the complemented bit line /BL is an &#34;L&#34; level (ground), as seen in waveform (c) in FIG. 5. At time T 3 , the column signal Y i  from the column decoder 15 goes to the &#34;H&#34; level from the &#34;L&#34; level, as seen in waveform (f), and the first and second transfer transistors 8 and 9 are rendered conductive. Accordingly, the potentials of the two bit lines BL and /BL are transferred to the input/output lines I/O and /I/O, respectively. The potential of the line I/O is at the &#34;H&#34; level, and the potential of the line /I/O is at the intermediate level, as seen in waveform (g) in FIG. 5. That is, because current flows from the supply potential node to ground through the input/output load transistor 11, the input/output /I/O, the second transfer transistor 9, the bit line /BL, the second driver transistor 6, the first common node 16a, and the first enable transistor 7, and the drive capacities of the input/output load transistors 10 and 11 and the driver transistors 5 and 6 are substantially the same, the potential of the input/output line I/O will not swing between the full difference between the supply potential and ground, and will be limited to the intermediate potential. Hence, the potential of the complemented bit line /BL will be the intermediate potential V m , namely, less than half the value of the difference between the supply potential and ground, as shown in waveform (c) of FIG. 5. 
     At time T 4 , the external signal /RAS goes from &#34;L&#34; to &#34;H&#34; , as shown in waveform (a) in FIG. 5, but the internal /RAS signal is maintained at the &#34;H&#34; level. The column signal Y i  drops from the &#34;H&#34; level to the &#34;L&#34; level, and the first and second transfer transistors 8 and 9 and made nonconductive. Hence, as shown in waveform (c) of FIG. 5, the potential of the bit line /BL is pulled from the intermediate level V m  to ground through the path through the second driver transistor 6, the first common node 16a, and the first enable transistor 7. The input/output line /I/O goes up to the &#34;H&#34; potential, as shown in waveform (g) of FIG. 5. 
     At time T 5 , which is delayed by the period t d  from time T 4 , the internal /RAS signal rises from the &#34;L&#34; level to the &#34;H&#34;  level. The word line signal WL goes from &#34;H&#34; to &#34;L&#34; after a period t d  followed the change of the external /RAS signal, as shown in waveform (b) of FIG. 5, whereupon the transistor 4 of the selected memory cell is made nonconductive. At time T 6 , the first enable signal S 0  goes down from the &#34;H&#34; to the &#34;L&#34; level, and the second enable signal /S 0  makes the opposite transition, as shown in waveforms (d) and (e) in FIG. 5. The first and second enable transistors 7 and 1 are then nonconductive. As a result, the equalizer circuit 14 is enabled following the change of the internal /RAS signal, and the potentials of the bit lines are made the same. 
     If a &#34;0&#34; has been stored in the selected memory cell, the operation is essentially the same as that already described. However, the potentials of the bit lines BL and /BL will be as shown in waveform (c&#39;) of FIG. 5. As shown in waveform (c&#39;) of FIG. 5, the potential of the bit line BL connected to the selected memory cell storing a &#34;0&#34; is at ground level after the time T 4 . Also, after time T 4  the transfer transistors 8 and 9 are nonconductive, and the first and second enable transistors 7 and 1 and the transistor 4 of the selected memory cell are in the conductive state. Hence, the potential stored in the selected memory cell is pulled down to ground level through the path through the transistor 4 of the selected memory cell, the bit line BL, the first driver transistor 5, the first common node 16a, and the first enable transistor 7. Subsequently, the transistor 4 and the first and second enable transistors 7 and 1 are rendered nonconductive. Accordingly, the potential of the charge storage device in the selected memory cell is ground level. As a result, the correct information will always be read out of the cell.