Abstract:
A graphics processor for processing vertices of a polygon includes an input for receiving an instruction for processing a given vertex, memory for storing a first lookup table and a second lookup table, and an interpolation engine that, responsive to receipt of the instruction from the input, selects one of the lookup tables, determines table output from the one of the lookup tables, and produces an output value based upon the table output and data relating to the given vertex. Each of the first and second lookup tables may correspond to a selected function and contains table output as a function of an input value. The input value corresponds to data relating to the given vertex.

Description:
PRIORITY 
     This application claims priority from U.S. provisional patent application serial number 60/093,185, filed Jul. 17, 1998, entitled “GRAPHICS PROCESSING WITH TRANSCENDENTAL FUNCTION GENERATOR” and bearing attorney docket number 1247/A01, the disclosure of which is incorporated herein, in its entirety, by reference. 
    
    
     FIELD OF THE INVENTION 
     The invention generally relates to computer systems and, more particularly, the invention relates to processing graphics request data for display on a computer display device. 
     BACKGROUND OF THE INVENTION 
     Three dimensional graphics request data commonly is processed in a computer system as a plurality of polygons having vertices. Each of the vertices have associated attribute data (e.g., color, transparency, depth, etc . . . ) that is utilized to rasterize pixels on a computer display device. 
     Vertices commonly are subjected to a plurality of different types of geometry calculations prior to being rasterized. Common functions typically include addition and multiplication functions. Specialized geometry accelerators often are utilized to perform such functions. Additionally, some transcendental functions commonly are required in vertex processing. Such calculations, for example, may be to determine an inverse square root of a number, or 2 raised to a power. Many geometry accelerators include a lookup table for each transcendental or elementary used function. Each lookup table typically has accompanying interpolation hardware for enhancing the accuracy of the transcendental functions by interpolating the results of the lookup table. 
     SUMMARY OF THE INVENTION 
     In accordance with one aspect of the invention, a graphics processor for processing vertices of a polygon includes an input for receiving an instruction for a processing step, memory for storing a first lookup table and a second lookup table, and an interpolation engine that, responsive to receipt of the instruction from the input, selects one of the lookup tables, determines table output from the one of the lookup tables, and produces an output value based upon the table output and data relating to the given vertex. In preferred embodiments, each of the first and second lookup tables corresponds to a selected function and contains table output as a function of an input value. The input value corresponds to data relating to the given vertex. 
     In other embodiments, the graphics processor also includes a multiplexer for enabling the interpolation engine to couple to either of the first and second lookup tables. The graphics processor also may have a plurality of additional lookup tables, where the interpolation engine is selectively coupled with any of the first, second or additional lookup tables. 
     In accordance with other aspects of the invention, an apparatus for processing computer graphics requests includes a graphics request input, and a processor coupled to the graphics request input. The processor is responsive to instructions and has an output. Among other things, the processor preferably includes a transcendental function generator with a plurality of lookup tables, and an interpolator engine selectably coupled to one of the plurality of lookup tables. Each table preferably corresponds to a particular transcendental function and contains interpolation coefficients. 
     In preferred embodiments, the apparatus includes a multiplexer for enabling the interpolator engine to selectively couple to any one of the plurality of lookup tables. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects and advantages of the invention will be appreciated more fully from the following further description thereof with reference to the accompanying drawings wherein: 
     FIG. 1 schematically shows a portion of an exemplary computer system on which preferred embodiments of the invention may be implemented. 
     FIG. 2 schematically shows a preferred graphics accelerator that may be utilized in accord with preferred embodiments of the invention. 
     FIG. 3 shows a preferred embodiment of a transcendental function generator within a geometry accelerator shown in FIG.  2 . 
     FIG. 4 shows a preferred method utilized by the transcendental function generator shown in FIG. 3 for producing output data. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 1 shows a portion of an exemplary computer system  100  on which preferred embodiments of the invention may be implemented. More particularly, the computer system  100  includes a host processor  104  (i.e., a central processing unit) for executing application level programs and system functions, volatile host memory  102  for short term data storage (i.e., random access memory), a graphics accelerator  106  for processing graphics request code in accord with preferred embodiments of the invention (see FIG.  4 ), and a bus coupling all of the prior noted elements of the system  100 . The system  100  further includes a display device  108  for displaying the graphics request code processed by the accelerator  106 . The graphics accelerator  106  preferably utilizes any well known graphics processing application program interface such as, for example, the OPENGL™ application program interface (available from Silicon Graphics, Inc. of Mountain View, Calif.) for processing three dimensional (“3D”) and two dimensional (“2D”) graphical request code. In preferred embodiments, the host processor  104  executes a graphical drawing application program such as, for example, the PLANT DESIGN SYSTEM™ drawing program, available from Intergraph Corporation of Huntsville, Ala. 
     FIG. 2 shows several elements of the graphics accelerator  106 . In preferred embodiments, the graphics accelerator  106  includes a double buffered frame buffer  200  (i.e., having a back buffer and a front buffer) for storing the processed graphics request code in accord with the OPENGL™ interface. Among other things, the graphics accelerator  106  also preferably includes a geometry accelerator  202  for performing geometry operations that commonly are executed in graphics processing, a rasterizer  204  for rasterizing pixels on the display device  108 , and a resolver  206  for storing data in the frame buffer  200  and transmitting data from the frame buffer  200  to the display device  108 . As noted above, the graphics accelerator  106  preferably is adapted to process both 2D and 3D graphical data. For more information relating to preferred embodiments of the graphics accelerator  106 , see, for example, copending patent application entitled “WIDE INSTRUCTION WORD GRAPHICS PROCESSOR”, filed on Jul. 15, 1999 and claiming priority from provisional patent application serial number 60/093,165, and copending U.S. patent application entitled “MULTI-PROCESSOR GRAPHICS ACCELERATOR”, filed on Jul. 15, 1999 and claiming priority from provisional U.S. patent application serial number 60/093,247, the disclosures of which are incorporated herein, in there entireties, by reference. 
     FIG. 3 shows a preferred embodiment of a transcendental function generator (“function generator  300 ”) within the geometry accelerator  202  shown in FIG.  2 . As is known to one skilled in the art, a transcendental function may be represented by the combination of elementary functions, such as addition and multiplication, in conjunction with coefficients values specific to the transcendental function. The function generator  300  includes first, second, and third lookup tables  302 A,  302 B, and  302 C for producing output coefficient values based upon an input variable, an interpolation engine  304  for calculating an output value based upon the output coefficient values in selected ones of the lookup tables  302 A- 302 C, and a multiplexer  306  for enabling the interpolation engine  304  to selectively couple with any one of the three lookup tables  302 A- 302 C. The input variable preferably is a vertex data value such as, for example, an input lighting datum. The lookup tables are used to represent the output coeffiecents of the transcendental function. The interpolation engine includes hardware to perform elementary functions on the input variable and the output coefficients to form the output value. The geometry accelerator may use the transcendental function generator to perform lighting calculations, geometry transformations or clipping on the vetex data prior to the rasterization stage. 
     In preferred embodiments, each lookup table  302 A- 302 C is directed to a different function. For example, the following lookup tables  302 A- 302 C may be used to determine the following functions: 
     first lookup table  302 A: 1/T ½  (i.e., the inverse square root of the variable T); 
     second lookup table:  302 B: 2 T  (i.e., 2 raised to the power of the variable T); and 
     third lookup table  302 C: log 2 T (i.e., the log base 2 of the variable T). 
     It should be noted that although three functions are provided, other functions adaptable to graphics processing may be utilized in the lookup tables  302 A- 302 C. In some embodiments, the lookup tables  302 A- 302 C are stored in read only memory (“ROM”) on the graphics accelerator. In a preferred embodiment, the lookup tables  302 A- 302 C are stored in memory created gates. The term “lookup table” is utilized herein to describe any data structure for enabling data to be retrieved based upon input data. Accordingly, input data having a value of “1” should produce output coefficients that yield the value of “2” from the interpolation engine  304  when utilized in the second lookup table  302 B. Each of the values calculated in the lookup tables  302 A- 302 C preferably were calculated for a relatively small range of the input variable, thus controlling the size of the tables  302 A- 302 C. In preferred embodiments of the invention, each table  302 A- 302 C has sixty-four entries that each produce three output table values. 
     As discussed in greater detail below, the interpolation engine  304  receives processing instructions from another portion of the geometry accelerator, and responsively selects the appropriate lookup table  302 A- 302 C via a select input of the multiplexer  306 . Upon receipt of the output table data, the interpolation engine  304  calculates an output value by means of the output table value and the input data. In preferred embodiments, the interpolation engine  304  calculates an output value in accordance with the below quadratic formula: 
     
       
           Y =AX 2 +BX +C  (Equation 1) 
       
     
     where A, B, and C are coefficients produced by either one of the tables  302 A- 302 C; and X is an input variable that is based upon data relating to the vertex being processed. 
     In alternative embodiments, the formula implemented by the interpolation engine  304  is a linear equation. In still other embodiments of the invention, the interpolation formula implemented is a cubic formula. Other embodiments include other formulas. 
     FIG. 4 shows a preferred method utilized by the transcendental function generator  300  shown in FIG. 3 for producing output data. The process begins at step  400  in which an instruction is received by the interpolation engine  304  relating to a given vertex currently being processed. In preferred embodiments, the instruction is five bits of a wide word having at least 128 bits. Specifically, two bits are used to select the appropriate table, and three additional bits select the input argument from one of eight possible sources, ranging from the processor to a crossbar (not shown) or other bus. Among other things, the vertex may have some lighting data that is processed by the geometry accelerator at step  400 . 
     The instruction preferably includes at least two lookup table bits that, when read by the interpolation engine  304 , direct it to select one of the three lookup tables  302 A- 302 C. For example, the bit sequence “00” may direct the engine  304  to the first table  302 A, the bit sequence “01” may direct the engine  304  to the second table  302 B, and the bit sequence “10” may direct the engine  304  to the third table  302 C. Accordingly, the process continues to step  402  in which the interpolation engine  304  reads the two lookup table bits to determine which lookup table  302 A- 302 C to access. 
     The process continues to step  404  in which the coefficients “A”, “B”, and “C” are ascertained from the selected lookup table  302 A- 302 C. Three entries preferably are associated with the input variable entry in each lookup table  302 A- 302 C. Accordingly, in preferred embodiments, the input variable is entered into all of the tables  302 A- 302 C to produce respective sets of output variables “A”, “B”, and “C.” The input variable is associated with the vertex data being processed. The interpolation engine  304  then selects the appropriate lookup table  302 A- 302 C via the select input of the multiplexer  306 , and then retrieves the set of coefficients from the output of such selected lookup table  302 A- 302 C. 
     The process then continues to step  406  in which both the input variable and retrieved coefficients are utilized in equation 1 (above) by the interpolation engine  304  to calculate an output value. 
     In some embodiments, the individual tables  302 A- 302 C may be implemented as different address ranges in a common addressable storage device. This effectively eliminates the need for the multiplexer  306  described above. In such case, the bits from the instruction word that select the table are simply incorporated into the table address. In some embodiments that do not utilize the multiplexer  306 , the table access time undesirably may be slower. 
     Although various exemplary embodiments of the invention have been disclosed, it should be apparent to those skilled in the art that various changes and modifications can be made which will achieve some of the advantages of the invention without departing from the true scope of the invention. These and other obvious modifications are intended to be covered by the appended claims.