Abstract:
The present invention discloses a servo control circuit comprising: a first node for receiving a control voltage; a second node for receiving a feedback voltage; an operational amplifier controlling a current on a path according to the voltages at the first and second nodes, the path including an internal voltage node thereon; an analog to digital converter (ADC) for converting the voltage at the internal voltage node to a digital signal; and a control logic circuit for generating a servo control signal according to the digital signal.

Description:
FIELD OF INVENTION 
       [0001]    The present invention relates to a servo control circuit which can be manufactured by a CMOS manufacturing process. 
       DESCRIPTION OF RELATED ART 
       [0002]    A servo control circuit is a circuit for controlling a servo motor to, e.g., adjust the projection angle of an automobile headlight.  FIG. 1  is a schematic circuit diagram showing a typical structure of a conventional servo control circuit  10 . As shown in the figure, according to an external control input such as an input from the driver of an automobile, the voltage Vref changes and the difference between the voltage Vref and the feedback voltage Vfb drives the motor  20 . In response to the operation of the motor  20 , the voltage across the variable resistor at the right side of the motor changes, and the feedback voltage Vfb corresponding to such change is sent back to the servo control circuit  10  for feedback control, so that the motor  20  is stopped when a desired status is reached, such as when an automobile headlight is adjusted to a desired angle. 
         [0003]      FIG. 2  shows the circuit details of the conventional servo control circuit  10 , in which the relationship between the voltage Vref and the feedback voltage Vfb is reflected at the node B through the setting of the voltage at the node A and the functions of six bipolar transistors B 1 -B 6 . The comparators  101 - 104  determine the voltage level at the node B is, and such information is sent to a control logic circuit  108  to control the motor  20 . In the figure, the right side of the dot-dash line is inside the servo control circuit  10 , and the left side of the dot-dash line is outside the servo control circuit  10 . 
         [0004]    The above prior art has the drawback that it employs bipolar transistors, and thus it can not be manufactured by a CMOS manufacturing process. 
       SUMMARY 
       [0005]    In view of the foregoing, it is desirous, and thus an objective of the present invention, to provide a servo control circuit which can be manufactured by a CMOS manufacturing process. 
         [0006]    In accordance with the foregoing and other objectives, the present invention proposes a servo control circuit which comprises: a first node for receiving a control voltage; a second node for receiving a feedback voltage; an operational amplifier controlling a current on a path according to the voltages at the first and second nodes, the path including an internal voltage node thereon; an analog to digital converter (ADC) for converting the voltage at the internal voltage node to a digital signal; and a control logic circuit for generating a servo control signal according to the digital signal. 
         [0007]    From an aspect of the present invention, the proposed servo control circuit superimposes a first multiple (a) of the difference between the control voltage and the feedback voltage (ΔV) to a second multiple (β) of a supply voltage (VCC), so that the voltage at the internal voltage node becomes β(VCC)−α*ΔV. In a preferred embodiment, β=½. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    These and other features, aspects, and advantages of the present invention will become better understood with reference to the following description, appended claims, and accompanying drawings. 
           [0009]      FIG. 1  is a schematic circuit diagram showing how a conventional servo control circuit operates. 
           [0010]      FIG. 2  shows the circuit details of the servo control circuit of  FIG. 1 . 
           [0011]      FIG. 3  is a schematic circuit diagram showing an embodiment of the present invention. 
           [0012]      FIG. 4  shows, by way of example, an embodiment of the analog to digital converter. 
           [0013]      FIG. 5  explains the effect of changing the voltage Vref. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0014]    Referring to  FIG. 3 , the servo control circuit  11  of the present invention reflects the relationship between the voltage Vref and the feedback voltage Vfb at the node B through the setting of the voltage at the external reference voltage node A, and the functions of an operational amplifier  116  and MOS transistors M 1  and M 2 . The voltage at the node B is converted to a digital signal by an analog to digital converter  117 , and the digital signal is sent to a control logic circuit  118  which generates a servo control signal to control the motor  20  according to the digital signal. In the figure, the right side of the dot-dash line is inside the servo control circuit  11 , and the left side of the dot-dash line is outside the servo control circuit  11 . 
         [0015]    More specifically, when the operational amplifier  116  is at a balanced status, its two inputs should be equal to each other, i.e., V 7  (the voltage at the first node)=V 8  (the voltage at the second node): 
         [0000]        V 7=[( R 3+ R 5)/( R 1+ R 3+ R 5)]*( I 1* R 1)+ V ref[ R 1/( R 1+ R 3+ R 5)] 
         [0000]        V 8 =V 7=[( R 4+ R 6)/( R 2+ R 4+ R 6)]*( IM 2* R 2)+ Vfb[R 2/( R 2+ R 4+ R 6)] 
       Wherein IM 2 =I 2 +IR 9 . 
       [0016]    For simplicity of calculation, the resistances of the resistors and the current amounts of the current sources can be set such that 
         [0000]      R 1 =R 2 ; R 3 =R 4 ; R 5 =R 6 ; I 1 =I 2 ; thus, 
         [0000]        IR 9=( V ref− Vfb )/( R 3+ R 5) 
         [0017]    Furthermore, the external reference voltage node A is a node in a voltage divider circuit in connection with the supply voltage VCC. From the current in and currents out from the node A, the following equation can be obtained: 
         [0000]      [( VCC−VA )/ R 7]− IR 9 =VA/R 8 
         [0000]    wherein VA is the voltage at the node A, and thus 
         [0000]        VA =[( R 7* R 8)/( R 7+ R 8)]*[( VCC/R 7)− IR 9] 
         [0018]    By setting R 7 =R 8 : 
         [0000]        VA =( VCC/ 2)−( R 7/2)* IR 9 
         [0000]    And the voltage VB at the node B is thus: 
         [0000]    
       
         
           
             
               
                 
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         [0019]    In the last equation, {[(R 7 /2)+R 9 ]/(R 3 +R 5 )} can be taken as a constant α, and the equation can be simplified as VB=(VCC/2)−α*(Vref−Vfb); the meaning of the equation is to multiply the difference ΔV between the voltage Vref and the feedback Vfb by (−α), and the product is superimposed on the voltage (VCC/2). 
         [0020]    The voltage VB at the node B is converted to a digital signal by the analog to digital converter  117 , and the digital signal is sent to the control logic circuit  118  to control the motor  20 . The analog to digital converter  117  need not be a converter of complete levels; it only need be able to distinguish between certain critical levels and convert the signals correspondingly. For example, as shown in  FIG. 4 , if five levels are provided, the space between every two levels of VCC−VR 1 −VR 2 −VR 3 −VR 4 −0V does not have to be equal to one another. In one embodiment, the levels may be arranged as thus: 
         [0000]        VR 1=( VCC/ 2)+(2%)* VCC    
         [0000]        VR 2=( VCC/ 2)+(0.4%)* VCC    
         [0000]        VR 3=( VCC/ 2)−(0.4%)* VCC    
         [0000]        VR 4=( VCC/ 2)−(2%)* VCC    
         [0000]    Of course, other arrangements or other number of levels are also workable. 
         [0021]    The meaning of the above arrangement may be better understood with reference to  FIG. 5 . The voltage VB at the node B is equal to (VCC/2)−α*ΔV, so when ΔV=0, the voltage VB is balanced at the position of (VCC/2), within the space between VR 3  and VR 4  in the above arrangement. When, e.g., a driver of an automobile adjusts the voltage Vref, or for some other reason the voltage Vref changes, a difference ΔV is generated. When a constant multiple (−α) of the difference ΔV, i.e., (−α)*ΔV, increases or decreases to a next level, the analog to digital converter  117  generates a corresponding output, by which the control logic circuit  118  generates a servo control signal to control the motor  20  correspondingly. 
         [0022]    The voltage VB need not be balanced at the position of (VCC/2); the balance point can be adjusted by the relationship between R 7  and R 8 . As a more general equation, the voltage VB at the node B is equal to β(VCC)−α*ΔV, and β=½ when R 7 =R 8 . 
         [0023]    The spirit of the present invention has been explained in the foregoing with reference to its preferred embodiments, but it should be noted that the above is only for illustrative purpose, to help those skilled in this art to understand the present invention, and not for limiting the scope of the present invention. Within the same spirit, various modifications and variations can be made by those skilled in this art. For example, the resistances of several resistors are made equal to each other for simplicity of calculation, but they can be arranged otherwise without departing from the spirit of the present invention. The transistors M 1  and M 2  can be replaced by NMOS transistors, with corresponding modifications (such as the inputs of the operational amplifier  116 ) to the circuit. The comparators  111 - 114  may be replaced by a hysteretic comparators. Additional devices may be interposed between any two devices shown in the drawing, without affecting the primary function of the circuit. In view of the foregoing, it is intended that the present invention cover all such modifications and variations, which should interpreted to fall within the scope of the following claims and their equivalents.