Abstract:
An improved semiconductor memory which can achieve high-speed data processing is disclosed. The memory comprises a memory array, a random access port for accessing a desired one of memory cell in accordance with row and column addresses, a serial read circuit for consecutively reading data from the selected row one by one and a serial write circuit for consecutively writing data to the selected row one by one without specific column address information.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor memory device, and more particularly to that suitable for application to video field. 
     Semiconductor memories have been utilized for storing display information for such as information processing system and TV system. Representative semiconductor memories are structured in such that a plurality of memory cells are arranged in a matrix form of rows and columns and one memory cell is selected for read or write for each access cycle. Therefore, an operation speed of such memories and amount of information to be accessed for unit of time have been limited. In order to implement a large amount of data accessing, an interleave technique in which a plurality of memories are alternately accessed and a parallel-serial conversion technique in which a plurality bits of data applied from the outside in series are once held by a register in parallel and data held by the register are stored in a plurality of memories in parallel. According to these technique, effective amount of data accessed for each cycle time is increased remarkably and high speed operation is resultantly achieved. 
     However, the above two techniques require complicated peripheral control circuits for controlling the respective memories. Therefore, the above two memories systems according to the above two techniques have been fabricated by a large amount of elements, and it has been difficult to fabricate such improved memory system on a semiconductor chip. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a semiconductor memory device operable at a high speed. 
     It is another object of the present invention to provide a semiconductor memory device having high speed serial read/write function. 
     The memory semiconductor memory according to the present invention is of the type having a memory array of a plurality of memory cells arranged in rows and columns, a row selection circuit for selecting one of the rows and a random access (RAM) port for selecting a part of the columns for reading and writing data from or to in accordance with column address information, and is featured in that a serial read port for sequentially selecting the columns one by one for reading therefrom and a serial write port for sequentially selecting the columns for writing thereto one by one. 
     According to the present invention, the above three ports, i.e., the RAM port, the serial read port and the serial write port operate in parallel and therefore high speed writing operations through the serial write port and high speed reading operations through the serial read port are simultaneously achieved. Thus, high speed data processing can be achieved without any special peripheral circuit. 
     The memory device according to the present invention is utilized as a video memory for storing video image information. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram showing a memory according to one embodiment of the present invention; 
     FIG. 2 is a timing waveform showing operations of the memory of FIG. 1; 
     FIG. 3 is a diagram showing a serial write operation, a serial read operation and an random access operation in the memory of FIG. 1; 
     FIG. 4 is a schematic block diagram showing a memory device according to another embodiment of the invention; and 
     FIG. 5 is a diagram showing one example of layout of external leads of the memory of FIG. 4. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 shows a schematic block diagram of a memory device according to the present invention. 
     A memory array includes a plurality of memory cells MC each coupled to a word line WL and a digit line DL. A row decoder 11 operatively selects one of word lines WL in accordance with row address information AR when a row address strobe RAS is low in level. A random access (RAM) port 13 has interface with the respective digit lines and a data input terminal D IN  and a data output terminal D OUT . The RAM port 13 operatively outputs data on a selected one of the digit lines to D OUT  in a read mode and applies data at D IN  to a selected digit line in accordance with column address information AC when a column address strobe CAS is at low. The function of the RAM port 13 is the same as that of a conventional random access memory. A serial read port 14 has a read line buffer section 32 having n-bits of storage units 32-1 to 32-n, a read data transfer gate section 31 having n-bits of data transfer gates 31-1 to 31-n, and a serial read addressing section 33 having n-bits of selecting units 33-1 to 33-n, and an output circuit 34. The transfer gate section 31 transfers data on the respective digit lines to the buffer section 32 in parallel when a read data transfer signal RDT is at low. The addressing section 33 is made of a shift register or a counter in a known way. The addressing section 33 takes in column address information AC during a read data transfer period and determines which column location, i.e., bit line is selected at the beginning of a serial read cycle and in the serial read cycle the addressing section 33 selects sequentially the column locations one by one from the initial column location in response to a read control signal SCR. The selected output of the addressing section enables one of the storage units 32-1 to 32-n and data stored in the enabled storage unit is applied to the output circuit 34 and to the serial output terminal S DO . 
     A serial write port 12 includes a data register section 22 having n-bits of register units 22-1 to 22-n, a write transfer gate section 24 composed of n-bits of write transfer gates 22-1 to 22-n for operatively transferring data on the respective units 22-1 to 22-n to the respective digit lines, a serial write addressing circuit 21 having n-bits of selecting units 21-1 to 21-n for sequentially selecting the storage units to be accessed, and an input data buffer 23. 
     The serial write addressing circuit 21 which may be composed of a shift register or counter, takes in column address information during a write data transfer period and determines an initial column location of storage unit to be accessed first in a serial write cycle and sequentially selects the storage units one by one in response to a write control signal SCW. 
     Referring to FIG. 2, representative operations of the memory of FIG. 1 is explained. 
     Since three ports 12, 13 and 14 operate asynchronously from each other, these three ports operate independently. 
     First, serial write operation is explained. 
     During a write data transfer period T W1 , RAS and WDT are changed to low. In response to a low level of WDT, all the transfer gates of the transfer gate section 24 are enabled, and data stored in the register section 22 which have been written into the register section during the previous serial write cycle are written into the respective digit lines and finally to memory cells coupled to the selected word line in parallel. In this instance, RDT is kept high and the read transfer gate section 31 is diesnabled to isolate the read register section 32 from the memory array 10 and therefore contents of the register section 31 are not affected by the new data held by the write register section 22. 
     Also in this write data transfer period T WD1 , the new column address information AC is introduced into the write addressing circuit 21 for determining an initial column location to be accessed first in the subsequent serial write cycle. 
     After the write data transfer cycle T WD1 , a serial write cycle T SW  is introduced and write data is first written via SDI and the circuit 23 to the selected register unit 22-i (1≦i≦n) and thereafter in response to each low level of SCW the register units 22-i+1, 22-i+1, 22-i+2 . . . are sequentially selected by the addressing circuit 21 and write data are written thereto from the circuit 23, one by one. The data written into the register section 22 through this serial write cycle T SW  are written into the respective digit lines of the memory array 10 at the subsequent write data transfer period T WD2  in response to a low level of WDT. 
     Read operation is then explained. 
     During a read data transfer period TRD 1 , and RAS and RDT are changed low in level so that all the transfer gates in the transfer gate section 31 are enabled and data on the respective digit lines are written into the line buffer section 32 in parallel. While also during this period T RD1 , column address information AC is applied to the addressing circuit 33 for determining the initial column address to be accessed first in the subsequent serial read cycle T SR . In the serial read cycle T SR , data stored in the storage unit 32-i corresponding to the above initial column location is first selected by the addressing circuit 33 and outputted to S DO  via the output circuit 34 and thereafter data stored by the storage units 32-i+1, 32-i+2, . . . are sequentially selected by the addressing circuit 33 in synchronism with the respective changes of SCR to a low level and outputted to S DO . 
     In order to avoid interference between read data and write data, the read data transfer period T RD  and the write data transfer period T WD  are introduced different timings from each other, as illustrated. 
     A random access cycle T RAM  in which data of a selected by row address information AR and column address information AC is accessed by the RAM port 13 is introduced at a desired period other than the read data transfer period T RD  and the write data transfer period T WD  because the memory array 10 is isolated from the serial read port 14 and the serial write port 12 during the above desired period and hence the RAM port 13 can access the memory array without limitation. 
     Thus, a serial read operation, a serial write operation and a random access operation can be performed in parallel, as explained in FIG. 3, according to the present invention. 
     FIG. 4 shows a more detailed example of the embodiment shown in FIG. 1. 
     An address buffer 15 receives address signals from address terminals A0 to A8, RAS and a column address strobe CAS. The address buffer 15 samples A0 to A8 as column address information AC at that time when CAS changes high to low in level and holds it thereafter and samples A0 to A8 as row address information AR at the time when RAS changes from high to low in level and holds it thereafter. 
     A gate circuit 25 is provided to apply the column address information AC to the serial addressing circuit 21 composed of a serial input bus and a serial decoder when WDT is at low in level. A gate circuit 35 is provided to apply the column address information to the serial addressing circuit 33 including a serial output bus and a serial decoder. The RAM port 13 includes a column decoder 41 which selectively connects one of the digit lines to a data-in circuit 44 and a data-out circuit 43 in accordance with the column address information AC. The data-in circuit 44 is controlled by a write signal WE. 
     FIG. 5 shows one example of layout of external leads of the memory of FIG. 4.