Abstract:
A semiconductor apparatus may include a master chip, first to n th  slave chips, first to n th  slave chip ID generating units, and a master chip ID generating unit. The first to n th  slave chip ID generating units are disposed respectively in the first to n th  slave chips and connected in series to each other. Each of the first to n th  slave chip ID generating units is configured to add a predetermined code value to an m th  operation code to generate an (m+1) th  operation code. The master chip ID generating unit is disposed in the master chip to generate a variable first operation code in response to a select signal. Here, ‘n’ is an integer that is equal to or greater than 2, and ‘m’ is an integer that is equal to or greater than 1 and equal to or smaller than ‘n’.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. §119(a) to Korean Patent Application No. 10-2010-0131999, filed on Dec. 21, 2010, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as if set forth in full. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    Various embodiments of the present invention relate to a semiconductor apparatus. In particular, certain embodiments relate to a semiconductor memory apparatus including a plurality of chips. 
         [0004]    2. Related Art 
         [0005]    The capacity and speed of semiconductor memories used as memory apparatuses in typical electronic systems have recently increased. Various attempts have been made to install a larger-capacity memory in a smaller area and drive the memory efficiently. 
         [0006]    In order to improve the integration density of semiconductor memory devices, a three-dimensional (3D) arrangement technology may be used to stack a plurality of memory chips, evolving from a conventional two-dimensional (2D) arrangement technology. The trend toward high integration and high capacity of memory apparatuses requires a structure that increases the memory capacity by using a 3D arrangement structure of the memory chips and improves the integration density by reducing the semiconductor chip size. 
         [0007]    A through-silicon via (TSV) technique may be used as such a 3D arrangement technology. The TSV technique is used as an alternative to overcome the degradation of a transmission rate according to the distance from a controller on a module, the weakness of a data bandwidth, and the degradation of a transmission rate generated according to the parameters on a package. The TSV technique creates a path penetrating a plurality of memory chips and forms an electrode in the path to conduct the communication between the controller and the plurality of chips. A TSV-based stack semiconductor memory apparatus directly connects it through a via on a controller without using wires, package subs, and package balls that are used in an SIP technique and in a POP technique. A bump is formed between the paths penetrating a plurality of memory chips, to electrically connect the controller or each memory chip. 
         [0008]    A semiconductor memory apparatus based on a 3D arrangement technique may include a master chip and a plurality of slave chips. A plurality of slave chips may be used as memory devices, and the master chip may control the slave chips. Different chip IDs are allocated to the slave chips to select a desired slave chip. A recording operation such as fuse cutting is performed on one-time recording devices (e.g., fuses) to allocate chip IDs to the slave chips. However, fuses occupy a large area in semiconductor apparatuses, and an operation of recording a chip ID in each slave chip requires high costs (e.g., the amount of money and time). 
       SUMMARY 
       [0009]    Accordingly, there is a need for an improved memory system that can efficiently control a plurality of semiconductor memories. 
         [0010]    To attain the advantages and in accordance with the purposes of the invention, as embodied and broadly described herein, one exemplary aspect of the present invention may provide a semiconductor apparatus which includes: a master chip; first to n th  slave chips; first to n th  slave chip ID generating units disposed respectively in the first to n th  slave chips and connected in series to each other, each of the first to n th  slave chip ID generating units being configured to add a predetermined code value to an m th  operation code to generate an (m+1) th  operation code; and a master chip ID generating unit disposed in the master chip to generate a variable first operation code in response to a select signal. Here, ‘n’ is an integer that is equal to or greater than 2, and ‘m’ is an integer that is equal to or greater than 1 and equal to or smaller than ‘n’. 
         [0011]    In another exemplary aspect of the present invention, a semiconductor apparatus may include: a master chip; a slave chip; a selecting unit disposed in the master chip to select one of an initial code and a variable code according to a select signal and generate a first operation code; and a slave chip ID generating unit disposed in the slave chip to add ‘1’ to the first operation code and generate a second operation code. 
         [0012]    In another exemplary aspect of the present invention, a semiconductor apparatus may include: a master chip; first to n th  slave chips; a plurality of slave chip ID generating units disposed respectively in the first to n th  slave chips and connected in series to each other to subtract ‘1’ from an m th  operation code and generate an (m+1) th  operation code; and a master chip ID generating unit disposed in the master chip to generate a variable first operation code in response to a select signal. Here, ‘n’ is an integer that is equal to or greater than 2, and ‘m’ is an integer that is equal to or greater than 1 and equal to or smaller than ‘n’. 
         [0013]    In another exemplary aspect of the present invention, a semiconductor apparatus may include: a master chip; a slave chip; a selecting unit disposed in the master chip to select one of an initial code and a variable code according to a select signal and generate a first operation code; and a slave chip ID generating unit disposed in the slave chip to subtract ‘1’ from the first operation code and generate a second operation code. 
         [0014]    Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. 
         [0015]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. 
           [0017]      FIG. 1  is a block diagram of a semiconductor apparatus according to an exemplary embodiment of the present invention; 
           [0018]      FIG. 2  is a circuit diagram of an exemplary embodiment of a master chip ID (Identification) generating unit illustrated in  FIG. 1 ; 
           [0019]      FIG. 3  is a circuit diagram of another exemplary embodiment of the master chip ID generating unit illustrated in  FIG. 1 ; 
           [0020]      FIG. 4  is a circuit diagram of an exemplary embodiment of a slave chip ID generating unit illustrated in  FIG. 1 ; 
           [0021]      FIG. 5  is a table illustrating an exemplary embodiment of first to ninth operation codes of eight slave chips according to an operation of the master chip ID generating unit; and 
           [0022]      FIG. 6  is a circuit diagram of another exemplary embodiment of the slave chip ID generating unit illustrated in  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    Reference will now be made in detail to the exemplary embodiments consistent with the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference characters will be used throughout the drawings to refer to the same or like parts. 
         [0024]    A semiconductor apparatus according to an exemplary embodiment of the present invention may include a chip ID (Identification) generating unit in each of a master chip and a plurality of slave chips. Also, in the semiconductor apparatus, the chip ID generating units may be connected in series so that the chip ID generating units of the slave chips may sequentially generate different operation codes when the master chip outputs an operation code of a predetermined number of bits. Also, in the semiconductor apparatus, the chip IDs allocated to the slave chips may be changed by changing the operation code outputted from the master chip. 
         [0025]      FIG. 1  is a block diagram of a semiconductor apparatus according to an exemplary embodiment of the present invention. 
         [0026]    The semiconductor apparatus may include a master chip and a plurality of slave chips. As an exemplary embodiment,  FIG. 1  illustrates that the semiconductor apparatus includes a master chip Master and eight slave chips Slave_ 1  to Slave_ 8 ; however, the present invention is not limited thereto. 
         [0027]    As illustrated in  FIG. 1 , the master chip Master may include a master chip ID generating unit  100 , and each of the eight slave chips Slave_ 1  to Slave_ 8  may include a slave chip ID generating unit  200 . The master chip ID generating unit  100  and the eight slave chip ID generating units  200  are connected in series. 
         [0028]    The master chip ID generating unit  100  generates a first operation code Code_ 1 &lt;0:2&gt;. The master chip ID generating unit  100  adjusts the value of the first operation code Code_ 1 &lt;0:2&gt; in response to a select signal Sel. 
         [0029]    The slave chip ID generating unit  200  of the first slave chip Slave_ 1  may add ‘1’ to the first operation code Code_ 1 &lt;0:2&gt; to generate a second operation code Code_ 2 &lt;0:2&gt;. For example, if the first operation code Code_ 1 &lt;0:2&gt; is &lt;100&gt;, the second operation code Code_ 2 &lt;0:2&gt; may be &lt;101&gt;. 
         [0030]    The slave chip ID generating unit  200  of the second slave chip Slave_ 2  adds ‘1’ to the second operation code Code_ 2 &lt;0:2&gt; and generates a third operation code Code_ 3 &lt;0:2&gt;. 
         [0031]    The third to eighth slave chips Slave_ 3  to Slave_ 8  operate in the same manner as the first and second slave chips Slave_ 1  and Slave_ 2 , and thus a detailed description thereof will be omitted for conciseness. 
         [0032]    According to this configuration, the first to eighth slave chips Slave_ 1  to Slave_ 8  may have their respective chip IDs ChipID_ 1 &lt;0:2&gt; to ChipID_ 8 &lt;0:2&gt; increasing one by one from the first operation code Code_ 1 &lt;0:2&gt;. In an exemplary embodiment, the first to eighth slave chips Slave_ 1  to Slave_ 8  may have their respective chip IDs ChipID_ 1 &lt;0:2&gt; to ChipID_ 8 &lt;0:2&gt; corresponding to the first to eighth operation codes Code_ 1 &lt;0:2&gt; to Code_ 8 &lt;0:2&gt; received by their respective slave chip ID generating units  200 . In another exemplary embodiment, the first to eighth slave chips Slave_ 1  to Slave_ 8  may have their respective chip IDs ChipID_ 1 &lt;0:2&gt; to ChipID_ 8 &lt;0:2&gt; corresponding to the second to ninth operation codes Code_ 2 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt; generated by their respective slave chip ID generating units  200 . This may be set by a designer. 
         [0033]    Also, referring to  FIG. 1 , the first to ninth operation codes Code_ 1 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt; and the first to eighth chip IDs ChipID_ 1 &lt;0:2&gt; to ChipID_ 8 &lt;0:2&gt; comprise 3 bits each. The reason for this is that the semiconductor apparatus is illustrated as including eight slave chips. Although  FIG. 1  illustrates that the first to ninth operation codes Code_ 1 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt; and the first to eighth chip IDs ChipID_ 1 &lt;0:2&gt; to ChipID_ 8 &lt;0:2&gt; are 3-bit signals, it should not be construed as limiting the number of bits of signals for implementing the present invention. 
         [0034]    Also, according to the configurations of the slave chip ID generating units  200 , the first to eighth slave chips Slave_ 1  to Slave_ 8  may have their respective chip IDs ChipID_ 1 &lt;0:2&gt; to ChipID_ 8 &lt;0:2&gt; decreasing one by one from the first operation code Code_ 1 &lt;0:2&gt;. This will be described below in more detail with reference to  FIG. 6 . 
         [0035]      FIG. 2  is a circuit diagram of an exemplary embodiment  100   a  of the master chip ID generating unit  100  illustrated in  FIG. 1 . 
         [0036]    Referring to  FIG. 2 , the master chip ID generating unit  100   a  may include a selecting unit  110 . The selecting unit  110  selects one of an initial code Int&lt;0:2&gt; and a variable code Var&lt;0:2&gt; according to the select signal Sel and generates the first operation code Code_ 1 &lt;0:2&gt;. 
         [0037]    When the select signal Sel is activated, the selecting unit  110  outputs the variable code Var&lt;0:2&gt; as the first operation code Code_ 1 &lt;0:2&gt;. On the other hand, when the select signal Sel is deactivated, the selecting unit  110  outputs the initial code Int&lt;0:2&gt; as the first operation code Code_ 1 &lt;0:2&gt;. The initial code Int&lt;0:2&gt; may include a voltage of a fixed level. For example, if the initial code Int&lt;0:2&gt; is set to &lt;111&gt;, an input terminal of the initial code Int&lt;0:2&gt; may be connected to a power supply voltage (VDD) terminal so that all of the three bits of the initial code Int&lt;0:2&gt; have a logic value ‘1’. The variable code Var&lt;0:2&gt; may include a test mode signal. If the variable code Var&lt;0:2&gt; includes a test mode signal, the semiconductor apparatus according to an exemplary embodiment of the present invention can externally adjust the chip IDs ChipID_ 1 &lt;0:2&gt; to ChipID_ 8 &lt;0:2&gt; of the slave chips Slave_ 1  to Slave_ 8 . The select signal Sel may also include a test mode signal. For example, if the initial code Int&lt;0:2&gt; is set to &lt;111&gt; and the variable code Var&lt;0:2&gt; is set to &lt;100&gt;, the first operation code Code_ 1 &lt;0:2&gt; is &lt;100&gt; when the select signal Sel is activated, and is &lt;111&gt; when the select signal Sel is deactivated. As illustrated in  FIG. 2 , the selecting unit  110  may include a typical multiplexer (MUX) circuit. 
         [0038]      FIG. 3  is a circuit diagram of another exemplary embodiment  100   b  of the master chip ID generating unit  100  illustrated in  FIG. 1 . 
         [0039]    Referring to  FIG. 3 , the master chip ID generating unit  100   b  may include a master code generating unit  120  and an operation code generating unit  130 . 
         [0040]    The master code generating unit  120  selects one of an initial code Int&lt;0:2&gt; and a variable code Var&lt;0:2&gt; according to the select signal Sel and generates a master code Mas&lt;0:2&gt;. 
         [0041]    When the select signal Sel is activated, the master code generating unit  120  outputs the variable code Var&lt;0:2&gt; as the master code Mas&lt;0:2&gt;. On the other hand, when the select signal Sel is deactivated, the master code generating unit  120  outputs the initial code Int&lt;0:2&gt; as the master code Mas&lt;0:2&gt;. The initial code Int&lt;0:2&gt; may include a voltage of a fixed level. For example, if the initial code Int&lt;0:2&gt; is set to &lt;111&gt;, an input terminal of the initial code Int&lt;0:2&gt; may be connected to a power supply voltage (VDD) terminal so that all of the three bits of the initial code Int&lt;0:2&gt; have a logic value ‘1’. The variable code Var&lt;0:2&gt; may include a test mode signal. The select signal Sel may also include a test mode signal. For example, if the initial code Int&lt;0:2&gt; is set to &lt;111&gt; and the variable code Var&lt;0:2&gt; is set to &lt;100&gt;, the master code Mas&lt;0:2&gt; is &lt;100&gt; when the select signal Sel is activated, and is &lt;111&gt; when the select signal Sel is deactivated. As illustrated in  FIG. 3 , the master code generating unit  120  may include a typical multiplexer (MUX) circuit. 
         [0042]    The operation code generating unit  130  adds ‘1’ to the master code Mas&lt;0:2&gt; and generates the first operation code Code_ 1 &lt;0:2&gt;. 
         [0043]    For example, if the master code Mas&lt;0:2&gt; is &lt;010&gt;, the first operation code Code_ 1 &lt;0:2&gt; is &lt;011&gt;. Here, the second to ninth operation codes Code_ 2 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt; including the first operation code Code_ 1 &lt;0:2&gt;, which will be described below, have a cyclic structure in which the minimum value follows the maximum value. Specifically, if the master code Mas&lt;0:2&gt; is &lt;111&gt;, the first operation code Code_ 1 &lt;0:2&gt; is &lt;000&gt;. That is, the first to ninth operation codes Code_ 1 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt; comprise 3 bits each, and adding ‘1’ to the code value &lt;111&gt; results in the code value &lt;000&gt;. 
         [0044]    As illustrated in  FIG. 3 , the operation code generating unit  130  may include an inverter  3001 , XNOR gates  3002  and  3004 , and an OR gate  3003 . 
         [0045]    The inverter  3001  inverts the master code Mas&lt;0&gt; and outputs the first operation code Code_ 1 &lt;0&gt;. 
         [0046]    The XNOR gate  3002  performs an XNOR operation on the output signal of the inverter  3001  and the master code Mas&lt;1&gt; and outputs the first operation code Code_ 1 &lt;1&gt;. 
         [0047]    The OR gate  3003  performs an OR operation on the output signal of the XNOR gate  3002  and the output signal of the inverter  3001 . 
         [0048]    The XNOR gate  3004  performs an XNOR operation on the output signal of the OR gate  3003  and the master code Mas&lt;2&gt; and outputs the first operation code Code_ 1 &lt;2&gt;. 
         [0049]    When the operation code generating unit  130  receives &lt;111&gt; as the master code Mas&lt;0:2&gt;, the inverter  3001  outputs &lt;0&gt; as the first operation code Code_ 1 &lt;0&gt;. Also, the XNOR gate  3002  outputs &lt;0&gt; as the first operation code Code_ 1 &lt;1&gt;. Also, the OR gate  3003  outputs a signal ‘0’, and the XNOR gate  3004  outputs &lt;0&gt; as the first operation code Code_ 1 &lt;2&gt;. That is, in response to the master code Mas&lt;0:2&gt;=&lt;111&gt;, the operation code generating unit  130  outputs &lt;000&gt; as the first operation code Code_ 1 &lt;0:2&gt;. 
         [0050]    Unlike the master chip ID generating unit  100   a  of  FIG. 2 , the master chip ID generating unit  100   b  of  FIG. 3  uses the operation code generating unit  130  to add ‘1’ to the master code Mas&lt;0:2&gt; and generate the first operation code Code_ 1 &lt;0:2&gt;. This is to allow the master chip ID generating unit  100   b  to correspond to the slave chip ID generating unit  200  which will be described below. This configuration may vary according to the loading difference between the master chip Master and the slave chips Slave_ 1  to Slave_ 8 , or according to the code values of the chip IDs ChipID_ 1 &lt;0:2&gt; to ChipID_ 8 &lt;0:2&gt; that are to be allocated to the slave chips Slave_ 1  to Slave_ 8 . 
         [0051]      FIG. 4  is a circuit diagram of an exemplary embodiment  200   a  of the slave chip ID generating unit  200  illustrated in  FIG. 1 .  FIG. 4  illustrates the slave chip ID generating unit  200  of the second slave chip Slave_ 2  by way of example. 
         [0052]    As described above, the slave chip ID generating unit  200   a  may add ‘1’ to the operation code received from the previous chip and outputs the resulting operation code to the next chip. Referring to  FIG. 4 , the slave chip ID generating unit  200   a  of the second slave chip Slave_ 2  may add ‘1’ to the second operation code Code_ 2 &lt;0:2&gt; to generate the third operation code Code_ 3 &lt;0:2&gt;. 
         [0053]    The slave chip ID generating unit  200   a  of the second slave chip Slave_ 2  may be configured in the same manner as the operation code generating unit  130  of  FIG. 3 . The slave chip ID generating unit  200   a  of the second slave chip Slave_ 2  may include an inverter  4001 , XNOR gates  4002  and  4004 , and an OR gate  4003 . The slave chip ID generating unit  200   a  of the second slave chip Slave_ 2  operates in the same manner as the operation code generating unit  130  of  FIG. 3 , and thus a detailed description thereof will be omitted for conciseness. 
         [0054]    As illustrated in  FIG. 4 , the slave chip ID generating unit  200   a  of the second slave chip Slave_ 2  may use the outputted third operation code Code_ 3 &lt;0:2&gt; as the chip ID ChipID 2 &lt;0:2&gt; of the second slave chip Slave_ 2 . Although not illustrated in the drawings, the inputted second operation code Code_ 2 &lt;0:2&gt; may be used as the chip ID ChipID 2 &lt;0:2&gt; of the second slave chip Slave_ 2 . Since the inputted operation codes and the outputted operation codes increase sequentially on a chip-by-chip basis, they may be used as the chip IDs.  FIG. 4  illustrates that the outputted third operation code Code_ 3 &lt;0:2&gt; is used as the chip ID ChipID 2 &lt;0:2&gt; of the second slave chip Slave_ 2 . 
         [0055]      FIG. 5  is a table illustrating an exemplary embodiment of the first to ninth operation codes Code_ 1 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt; of the eight slave chips Slave_ 1  to Slave_ 8  according to an operation of the master chip ID generating unit  100 . 
         [0056]    Referring to  FIG. 5 , the initial code Int&lt;0:2&gt; is set to &lt;111&gt; in the cases of (a), (b) and (c). The variable code Var&lt;0:2&gt; is set to &lt;010&gt; in the cases of (a) and (b), and is set to &lt;100&gt; in the case of (c). 
         [0057]    A case (a) of  FIG. 5  corresponds to the case where the select signal Sel is deactivated to ‘0’. Accordingly, the master code generating unit  120  outputs the initial code Int&lt;0:2&gt; as the master code Mas&lt;0:2&gt;. That is, in the case (a) of  FIG. 5 , the master code Mas&lt;0:2&gt; is &lt;111&gt;. Thereafter, the operation code generating unit  130  and the slave chip ID generating unit  200  cause the first to ninth operation codes Code_ 1 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt; to increase one by one from &lt;000&gt;. 
         [0058]    A case (b) of  FIG. 5  corresponds to the case where the variable code Var&lt;0:2&gt; is set to &lt;010&gt; and the select signal Sel is activated to ‘1’. Accordingly, the master code generating unit  120  outputs the variable code Var&lt;0:2&gt; as the master code Mas&lt;0:2&gt;. That is, in the case (b) of  FIG. 5 , the master code Mas&lt;0:2&gt; is &lt;010&gt;. Thereafter, the operation code generating unit  130  and the slave chip ID generating unit  200  cause the first to ninth operation codes Code_ 1 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt; to increase one by one from &lt;110&gt;. In this manner, because the master chip ID generating unit  100  generates the first operation code Code_ 1 &lt;0:2&gt; differently according to the select signal Sel, the semiconductor apparatus according to an exemplary embodiment of the present invention may vary the values of the first to ninth operation codes Code_ 1 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt;. Because the first to ninth operation codes Code_ 1 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt; are allocated as the chip IDs ChipID_ 1 &lt;0:2&gt; to ChipID_ 9 &lt;0:2&gt; of the first to eighth slave chips Slave_ 1  to Slave_ 8 , the semiconductor apparatus according to an exemplary embodiment of the present invention may set the chip IDs ChipID_ 1 &lt;0:2&gt; to ChipID_ 9 &lt;0:2&gt; of the first to eighth slave chips Slave_ 1  to Slave_ 8  differently through the master chip ID generating unit  100 . 
         [0059]    A case (c) of  FIG. 5  corresponds to the case where the select signal Sel is activated to ‘1’ and the variable code Var&lt;0:2&gt; is set to &lt;100&gt;. Accordingly, the master code generating unit  120  outputs the variable code Var&lt;0:2&gt; as the master code Mas&lt;0:2&gt;. That is, in the case (c) of  FIG. 5 , the master code Mas&lt;0:2&gt; is &lt;100&gt;. Thereafter, the operation code generating unit  130  and the slave chip ID generating unit  200  cause the first to ninth operation codes Code_ 1 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt; to increase one by one from &lt;010&gt;. In this manner, the semiconductor apparatus according to an exemplary embodiment of the present invention may vary the values of the first to ninth operation codes Code_ 1 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt; by adjusting the variable code Var&lt;0:2&gt; inputted to the master chip ID generating unit  100 . Because the first to ninth operation codes Code_ 1 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt; are allocated as the chip IDs ChipID_ 1 &lt;0:2&gt; to ChipID_ 9 &lt;0:2&gt; of the first to eighth slave chips Slave_ 1  to Slave_ 8 , the semiconductor apparatus according to an exemplary embodiment of the present invention may set the chip IDs ChipID_ 1 &lt;0:2&gt; to ChipID_ 9 &lt;0:2&gt; of the first to eighth slave chips Slave_ 1  to Slave_ 8  differently by adjusting the variable code Var&lt;0:2&gt;. 
         [0060]    As described above, the first to ninth operation codes Code_ 1 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt; are 3-bit codes. As illustrated in  FIG. 5 , the first to ninth operation codes Code_ 1 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt; have a sequential structure in which they increase sequentially on a bit-by-bit basis, and has a cyclic structure in which adding ‘1’ to the code value &lt;111&gt; results in the code value &lt;000&gt;. 
         [0061]    In this manner, because the semiconductor apparatus according to an exemplary embodiment of the present invention can allocate the chip IDs ChipID 1 &lt;0:2&gt; to ChipID 8 &lt;0:2&gt; differently, it can flexibly control the slave chips Slave_ 1  to Slave_ 8  instead of using the slave chips Slave_ 1  to Slave_ 8  in a fixed manner. 
         [0062]    As described above, the semiconductor apparatus according to an exemplary embodiment of the present invention is configured such that the slave chips Slave_ 1  to Slave_ 8  have their respective IDs ChipID 1 &lt;0:2&gt; to ChipID 8 &lt;0:2&gt; that increase sequentially. However, the semiconductor apparatus according to another exemplary embodiment of the present invention may be configured such that the slave chips Slave_ 1  to Slave_ 8  have their respective IDs ChipID 1 &lt;0:2&gt; to ChipID 8 &lt;0:2&gt; that decrease sequentially. If the slave chip ID generating unit  200   b  is configured as illustrated in  FIG. 6 , the slave chips Slave_ 1  to Slave_ 8  may have their respective IDs ChipID 1 &lt;0:2&gt; to ChipID 8 &lt;0:2&gt; that decrease sequentially. 
         [0063]      FIG. 6  is a circuit diagram of another exemplary embodiment  200   b  of the slave chip ID generating unit  200  illustrated in  FIG. 1 . 
         [0064]    Referring to  FIG. 6 , the slave chip ID generating unit  200   b  is configured such that the first to eighth slave chips Slave_ 1  to Slave_ 8  have their respective chip IDs ChipID_ 1 &lt;0:2&gt; to ChipID_ 8 &lt;0:2&gt;) decreasing one by one from the first operation code Code_ 1 &lt;0:2&gt;. 
         [0065]    Unlike the slave chip ID generating unit  200   a  of  FIG. 4 , the slave chip ID generating unit  200   b  of  FIG. 6  subtracts ‘1’ from the operation code received from the previous chip and outputs the resulting operation code to the next chip. 
         [0066]    The slave chips Slave_ 1  to Slave_ 8  including the slave chip ID generating unit  200   b  of  FIG. 6  have the first to ninth operation codes Code_ 1 &lt;0:2&gt; to Code_ 9 &lt;0:2&gt; that decrease sequentially. 
         [0067]    Accordingly, the slave chips Slave_ 1  to Slave_ 8  may have their respective chip IDs ChipID 1 &lt;0:2&gt; to ChipID_ 8 &lt;0:2&gt; that decrease sequentially. 
         [0068]      FIG. 6  illustrates the slave chip ID generating unit  200   b  of the second slave chip Slave_ 2  by way of example. 
         [0069]    Referring to  FIG. 6 , the slave chip ID generating unit  200   b  may include inverters  6001  and  6005 , XNOR gates  6002  and  6004 , and an AND gate  6003 . 
         [0070]    The inverter  6001  inverts the second operation code Code_ 2 &lt;0&gt; and outputs the third operation code Code_ 3 &lt;0&gt;. 
         [0071]    The XNOR gate  6002  performs an XNOR operation on the second operation code Code_ 2 &lt;0&gt; and the second operation code Code_ 2 &lt;1&gt; and outputs the third operation code Code_ 3 &lt;1&gt;. 
         [0072]    The AND gate  6003  performs an AND operation on the output signal of the XNOR gate  6002  and the output signal of the inverter  6001 . 
         [0073]    The inverter  6005  inverts the second operation code Code_ 2 &lt;2&gt;. 
         [0074]    The XNOR gate  6004  performs an XNOR operation on the output signal of the AND gate  6003  and the output signal of the inverter  6005  and outputs the third operation code Code_ 3 &lt;2&gt;. 
         [0075]    When the slave chip ID generating unit  200   b  receives &lt;111&gt; as the second operation code Code_ 2 &lt;0:2&gt;, the inverter  6001  outputs &lt;0&gt; as the third operation code Code_ 3 &lt;0&gt;. Also, the XNOR gate  6002  outputs &lt;1&gt; as the third operation code Code_ 3 &lt;1&gt;. Also, the AND gate  6003  outputs a signal ‘0’, and the XNOR gate  6004  outputs &lt;1&gt; as the third operation code Code_ 3 &lt;2&gt;. That is, in response to the second operation code Code_ 2 &lt;0:2&gt;=&lt;111&gt;, the slave chip ID generating unit  200   b  outputs &lt;011&gt; as the third operation code Code_ 3 &lt;0:2&gt;. 
         [0076]    Also, an exemplary embodiment of the present invention may be configured in such a way to add a value of ‘2’ or greater to the operation code of the previous chip according to the number of slave chips and the number of bits of each code. Although  FIGS. 2 and 4  illustrate that the semiconductor apparatus adds ‘1’ to the operation code of the previous chip and transmits the resulting operation code to the next chip, it should not be construed as limiting an operation (e.g., addition or subtraction) or a value (e.g., ‘1’) for implementing the present invention. 
         [0077]    The technical concept of the present invention is more effective for a semiconductor apparatus including a master chip and a plurality of slave chips that are connected through a TSV structure. In the case of a semiconductor apparatus including a plurality of chips connected through a TSV structure, due to the characteristics of its stack structure, an operation of recording chip IDs in one-time recording devices (e.g., fuses) is difficult and requires high cost. The semiconductor apparatus according to an exemplary embodiment of the present invention can be easily used even in a stack structure of a plurality of chips, because it is configured in such a way that the first operation code Code_ 1 &lt;0:2&gt; outputted from the master chip Master is sequentially processed by the slave chips Slave_ 1  to Slave_ 8  to generate a new operation code. Also, the semiconductor apparatus according to an exemplary embodiment of the present invention does not need fuses for recording the chip IDs. Therefore, because a one-time recording device such as a fuse occupies a large area in a semiconductor apparatus, the present invention can increase the integration density of semiconductor apparatuses. 
         [0078]    While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the semiconductor apparatus described herein should not be limited based on the described embodiments. Rather, the semiconductor apparatus described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.