Abstract:
A data processing system having a plurality of FIFO memories and a plurality of ALUs and in which a FIFO memory may be selected to receive a set of data signals from an ALU and at the same time to be selected to provide a set of data signals to another ALU, with the result that the selected FIFO memory performs read and write operations concurrently and intermittently. Also, a set of data signals held by one of the FIFO memories may be transferred to a selected ALU for effecting a logical or arithmetic operation thereon, and the data signals representing the result of the logical or arithmetic operation thereon, and the data signals representing the result of the logical or arithmetic operation by the selected ALU may be transferred to another FIFO memory.

Description:
BACKGROUND OF THE INVENTION 
     This application is a divisional of of U.S. application Ser. No. 303,186, filed Sept. 17, 1981, now U.S. Pat. No. 4,433,394. 
    
    
     The present invention relates to a first-in first-out memory (FIFO memory) capable of reading and writing simultaneously in one memory cycle and a processing unit including the same. 
     A first-in first-out (FIFO) memory is defined as a memory in which information written into the memory is sequentially read out in the order the data is received, i.e., such that the first written information is read first. 
     In the past, memory cells of a high speed FIFO memory were formed, in many cases, of flip-flops (FF&#39;s) or latches including combinations of gates, or conventional memory cells (which allow one read or write operation in each memory cycle). The former is sufficiently fast but a huge number of gates are required to construct a large capacity FIFO memory. The conventional memory cells, on the other hand, need two memory cycles for writing and reading data. The speed of such memory cells is not compatible with the presently available pipelining techniques. On the other hand, it is difficult to obtain memory cells for a large capacity memory which can execute one memory cycle in one half of the pitch time of the pipeline data processor. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a FIFO memory capable of reading and writing in one memory cycle and a processing unit including the same. 
     The present invention is characterized by the provision of a plurality of readable and writable data banks, mode indicating means for indicating a write mode to the respective data banks and read/write control means for writing received data into the data bank to which the write mode is indicated and for reading data from the data bank to which the write mode is not indicated and for outputting the data was from the banks in the same order as the data received. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a block diagram of a pipelined data processor to which the first-in first-out (FIFO) memories according to an embodiment of the present invention are to be applied; 
     FIG. 2 shows a block diagram of the FIFO memory in accordance with one embodiment of the present invention; 
     FIG. 3A shows a circuit diagram of an exemplary mode indicating circuit for indicating an operation mode of a bank; 
     FIG. 3B is a table illustrating modes of the banks indicated by a mode indicating signal SW; 
     FIG. 4 shows a circuit diagram of an exemplary write (W)-control circuit for controlling writing to the bank; 
     FIG. 5 shows a circuit diagram of an exemplary read(R)-control circuit for controlling reading from the bank; 
     FIG. 6 shows a timing chart for explaining the operation of the FIFO memory; and 
     FIG. 7 shows a block diagram of a pipelined data processor embodying the FIFO memory of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     It will be seen that FIFO memories will be effectively applied in a pipelined data processor, as shown in FIG. 1, in which a pipeline execution unit 1 encircled by a dot-and-dash line comprises a pipeline arithmetic and logic unit (ALU) 2 and a pipeline control logic circuit 3, and receives input data (single-bit or multi-bit data) from execution units (E-units) 4 and 5 through data buses 30 and 31 and sends the results of execution to another execution unit (E-unit) 6 through a data bus 32. First-in first-out (FIFO) memories 20, 21 22 are provided between the respective units as buffers for the input data and the execution results. The input data from the execution unit 4 (or the execution result of the execution unit 4) is supplied to the FIFO memory 20 through the data bus 30, thence it is supplied to the pipeline ALU 2 of the execution unit 1 through the data bus 10. The similar operations are performed for the FIFO memories 21 and 22, in which case the data buses 11 and 12 are used. 
     The reasons for using such FIFO memories as buffers are explained below: 
     (1) In the case of the intermittent supply of the input data from the execution units 4 and 5, a buffing of the data is effected. A plurality of input data pairs are successively supplied to the unit 1 from the units 4 and 5. A pair of input data items to be executed by the ALU 2 are usually to be applied simultaneously to the pipeline ALU 2. Let us assume a case where one item of an input data pair has arrived at the ALU 2 from the execution unit 4 but the arrival of the other item of the input data pair from the execution unit 5 is delayed for some reason The FIFO memory 20 is used to delay sending the one of the input data pair sent from the execution unit 4 to the unit 1 until the other of the input data pair from the unit 5 arrives at the FIFO memory 21 while the FIFO memory 20 is receiving successive data sent in each cycle through the data bus 30. During this period, invalid data is supplied to the pipeline ALU 2 from the FIFO memories 20 and 21 and the execution result by the ALU 2 is also invalid. The pipeline control logic circuit 3 controls the ALU 2 so that a forwarding of the invalid output to the unit 6 is prevented. 
     (2) Countermeasures for rejecting the acceptance by the unit 6. The unit 6 sometimes rejects acceptance of the data from the data bus 32. The FIFO memory 22 is used to temporarily buffer the execution result from the pipeline ALU 2 through the data bus 12 and to hold the data until the acceptance by the unit 6 is allowed. 
     Thus, when the intermittence of the data occurs, it is effective to use the FIFO memory between the units having the pipeline ALU&#39;s. The functions required for the FIFO memories are: 
     (A) Ability to simultaneously read and write within a pipeline pitch time; and 
     (B) Ability to read the written data in a short time. 
     Referring now to FIG. 2, a block diagram of a FIFO memory in accordance with one embodiment of the present invention is shown. The present FIFO memory may be applied to any one of the FIFO memories 20, 21 and 22 shown in FIG. 1. 
     In FIG. 2, numerals 47 and 48 denote data banks (hereinafter simply referred to as banks) which can read and write data independently from each other. The data banks 47 and 48 each comprises a random access memory (RAM). At least two banks are needed to satisfy the objects of the present invention; although, the two banks may form part of a single memory. 
     It will be understood as well that a bank may comprise more than one RAM depending on the memory capacity required and the selected word configuration of the received data. 
     Data sent from the outside is designated as odd or even and is written into the respective banks 47 and 48 according to the order of their arrival. For example, the data of arrival number 0 first is written into the bank 47, the data of arrival number 1 next is written into the bank 48, the data of arrival number 2 next is written into the bank 47, the data of arrival number 3 next is written into the bank 48, and so on, so that the data is repetitively and alternately written into the banks 47 and 48. Thus, the data of arrival numbers 0, 2, 4, . . . 2n (where n is an integer), i.e., the even arrival numbered data is sequentially written into the bank 47 and hence the bank 47 is called an even bank. On the other hand, the data of the arrival numbers 1, 3, 5, . . . 2n+1, i.e., the odd arrival numbered data is sequentially written into the bank 48 and hence the bank 48 is called an odd bank. 
     Numeral 41 denotes a mode indicating circuit for repetitively indicating at a constant interval a write mode to the bank 47 or 48. The write mode is called a W mode while the read mode is called an R mode. The mode indicating circuit 41 repetitively produces &#34;0&#34; and &#34;1&#34; at a constant interval such as &#34;0&#34;, &#34;1&#34;, &#34;0&#34;, &#34;1&#34;, . . . . When the output of the mode indicating circuit 41 is &#34;0&#34;, the even bank 47 is controlled to assume the W mode and the odd bank 48 is rendered to assume the R mode. When the output of the circuit 41 is &#34;1&#34;, the even bank 47 assumes the R mode and the odd bank 48 assumes the W mode. Accordingly, the banks 47 and 48 are controlled by the mode indicating circuit 41 to assume the R mode and the W mode repetitively and alternatively at the constant interval with the banks 47 and 48 assuming different modes from each other at a given time. 
     Numeral 100 denotes a read/write control circuit for the banks 47 and 48, which comprises circuits 42 to 46 and 49. 
     The general operation of the FIFO memory is explained first. When the even numbered data is applied from the external and the even bank 47 is in the W mode, the circuit 100 immediately writes the data into the even bank 47. If the even bank 47 is in the R mode, the circuit 100 waits until the even bank 47 assumes the W mode, and then writes the data into the even bank 47 which has now assumed the W mode. The same is true for the write operation of the odd numbered data. 
     When a read request is issued and the data to be read next is stored in the even bank 47 and if the even bank 47 is in the R mode, the circuit 100 immediately reads the data from the even bank 47. If the even bank 47 is in the W mode, the circuit 100 waits until the even bank 47 assumes the R mode, and then reads the data from the even bank 47 which has now assumed the R mode. 
     The FIFO memory shown in FIG. 2 enables the simultaneous read and write. For example, it is possible to write the data into the even bank 47 simultaneously with reading the data from the odd bank 48. In FIG. 2, thick signal lines indicate signal lines each having a plurality of lines for parallel signal transmission. 
     The operation of the FIFO memory is now explained in more detail. 
     Referring to FIG. 2, when a write operation is required, a write request indication signal WREQ on a signal line 33 is set to &#34;1&#34;. A data signal WDATA on a data line 30 represents the data to be written. The signals WREQ and WDATA are supplied from a first external unit, for example, the execution unit 4 (FIG. 1), to a write control circuit (W control circuit) 42. The W control circuit 42 includes means responsive to the signal WREQ to receive the write data signal WDATA, and detect the number (arrival number) of the write request received. Let us assume that the arrival number of the write request is N. Depending on whether N is even or odd (i.e. on the even/odd state of N), the even bank 47 or odd bank 48 is selected as the data bank into which the received data is written. On the other hand the output signal SW of the mode indicating circuit 41 indicates the W mode to the bank. When the data bank determined on the basis of the even/odd state of N and the data bank to which the W mode is indicated by the signal SW are identical, W control circuit 42 sends an address signal WAH determined by higher order bits excluding the least significant bit in the binary expression of N to signal line 93, changes a write enable signal WE on the signal line 93 to &#34;1&#34;, sends the write data WDATA as a signal SDRE to line 82 if the data is to be written into the even bank 47 and sends the write data WDATA as a signal SDRO to line 83 if the data is to be written into the odd bank 48. If the coincidence of the banks determined by N and the signal SW respectively is not met when the write request WREQ arrives, means are necessary for storing the write request WREQ and the write data WDATA until the coincidence of the banks is met. An embodiment of such means will be described later in conjunction with FIG. 4. The W control circuit 42 is initialized in a manner to be described later by an initializing signal START supplied through a signal line 39. 
     A circuit 44 encircled by a dot-and-dash line is a write signal generating circuit which is responsive to the write enable signal WE and the mode indicating signal SW to supply a write enable signal WEE to the even bank 47 through line 59 or a write enable signal WEO to the odd bank 48, through signal line 58. An AND gate 441 of the circuit 44 supplies write enable signal WEE to the even bank 47 only when the signal SW is &#34;0&#34; and the signal WE is &#34;1&#34;. In this manner, when the even bank 47 is in the W mode (the signal SW is &#34;0&#34;) and the data to be written is present (the signal WE is &#34;1&#34;), the write enable signal WEE is supplied to the even bank 47. An AND gate 442 supplies the write indicating signal WEO to the odd bank 48 only when the signal SW is &#34;1&#34; and the signal WE is &#34;1&#34;. Thus, when the odd bank 48 is in the W mode (the signal SW is &#34;1&#34;) and the data to be written next is present (the 10 signal WE is &#34;1&#34;), the write enable signal WEO is supplied to the odd bank 48. A circle at one of the inputs of the AND gate 441 represents an inverting function for the input signal. 
     A selection circuit 45 responds to the mode indicating signal SW to selectively supply the write address signal WAH to the bank 47 or 48. The circuit 45 comprises selectors 451 and 452. When the mode indicating signal SW is &#34;0&#34;, the selector 451 selects the write address signal WAH from the group of the signal WAH on line 93 and a read address signal RAH on line 99 to be described later and supplies the signal as a memory address AE to a signal line 57. Accordingly, when the even bank 47 is in the W mode (the signal SW is &#34;0&#34;), the write address WAH is supplied to the even bank 47. When the signal SW is &#34;1&#34;, the selector 451 selects the read address RAH on line 99 and supplies it as the memory address AE to the even bank 47 by way of line 57. When the signal SW is &#34;0&#34;, the selector 452 selects the read address RAH on line 99 and supplies it as a memory address AO to a signal line 56, and when the signal SW is &#34;1&#34;, the selector 452 selects the write address WAH on line 93 and supplies it as the memory address AO to the signal line 56. Accordingly, when the odd bank 48 is in the W mode (the signal SW is &#34;1&#34;), the write address WAH is supplied to the odd bank 48. The selectors 451 and 452 and selectors 461 and 491 to be described later each function to select an input from a left top part (an input from an address line 93 for the selector 451) when the signal SW from a top part thereof is &#34;0&#34; and select an input from a left bottom part (an input from an address line 99 for the selector 451) when the signal SW is &#34;1&#34; and produce the selected signal at a righthand output line (a signal line 57 for the selector 451). 
     A selection circuit 46 comprises a selector 461 which responds to the signal SW to select the even bank write data signal SDRE or the odd bank write data signal SDRO. The selector 461 selects a signal line 82 when the signal SW is &#34;0&#34; and supplies the data signal SDRE to the signal line 54 as a data signal DIO and to the signal line 55 as a data signal DIE. When the signal SW is &#34;1&#34;, the selector 461 selects a signal line 83 and supplies the data signal SDRO to the signal line as the data signal DIO and the signal line as the data signal DIE. Accordingly, when the even bank 47 is in the W mode (the signal SW is &#34;0&#34;), the even bank write data signal SDRE is supplied to the banks 47 and 48. 
     Accordingly, if an even numbered write request arrives at the FIFO memory and the even bank 47 is in the W mode at that time, the write enable signal WEE is applied to a write terminal WET of the even bank 47, the write address signal WAH is applied to an address terminal AT and the data signal SDRE is applied to a data input terminal DIT so that the even bank write data signal SDRE is written into the even bank 47. When the even bank 47 is in the W mode (the signal SW is &#34;0&#34;), the odd bank 48 is in the R mode and the write enable signal WEO from the output of the AND gate 442 is &#34;0&#34;. Accordingly, writing into the odd bank 48 is inhibited and hence the even bank write data SDRE is not written into the odd bank 48. 
     When the odd bank 48 is in the W mode (the signal SW is &#34;1&#34;), the odd bank write data signal SDRO in supplied to the banks 47 and 48. However, the data signal SDRO is not written into the even bank 47 for the same reason as described above and the data signal SDRO is written into only the odd bank 48. 
     Instead of using the selector 461, the signal line 82 may be connected to the signal line 55 so that the signal SDRE is always supplied to the even bank 47 and the signal line 83 may be connected to the signal line 54 so that the signal SDRO is always supplied to the odd bank 48. When the selector 461 is used, the signal lines 55 and 54 can be shared and the writing of the signal lines between the banks 47 and 48, and the W control circuit 42 can be simplified. 
     In this manner, the data is automatically, repetitively and alternately written into the banks 47 and 48 in the order as received, without necessity of externally specifing the address, such that the data of arrival number 0 is written in the address 0 of the even bank 47, the data of arrival number 1 is written in the address 0 of the odd bank 48, the data of arrival number 2 is written into the address 1 of the even bank 47, the data of arrival number 3 is written into the address 1 of the odd bank 48 and so on. 
     The banks 47 and 48 have the following input/output terminals. The terminal WET is the write enable signal input terminal to which the write enable signal WEE for the even bank 47 or the write enable signal WEO for the odd bank 48 is applied. The terminal AT is the memory address input terminal to which the memory address AE for the even bank 47 or the memory address AO for the odd bank 48 is applied. The terminal DIT is the write data input terminal to which the data signal DIE or DIO is applied. 
     A terminal DOT is a read data output terminal. The read data DOE is supplied from the terminal DOT of the even bank 47 to a data line 471 while the read data DOO is supplied from the terminal DOT of the odd bank 48 to a data line 481. When the input to the terminal WET is &#34;1&#34;, the banks 47 and 48 store the data arriving at the data terminal DIT to the addresses specified by the address signal applied to the address input terminal AT. When the input to the terminal WET is &#34;0&#34;, the banks 47 and 48 read the data stored at the addresses specified by the address signal applied to the address input terminal AT. Other input/output terminals of the banks 47 and 48 which are not shown in FIG. 2 include power supply terminals, chip select terminals and output enable terminals. 
     The write operation has been explained thus far. The read operation is now explained. 
     The read control circuit (R control circuit) 43 is initialized in a manner to be described later by the external initializing signal START The R control circuit 43 internally generates a read address signal RA for the addresses of the banks 47 and 48 to be read, as will be explained later. The read address RA is incremented by one when a read request signal RREQ to be explained later is received. A read address signal RAH which is determined by the higher order bits excluding the least significant bit of the binary expression of the address RA, is supplied from the R control circuit 43 to the signal line 99. The circuit 43 also internally generates a number M which is the total number of written data items which have not been read. The number M is incremented by one whenever the write enable signal WE assumes &#34;1&#34;, that is, each time when one data item is written, and decremented by one whenever the read request signal RREQ assumes &#34;1&#34;, that is, each time when one data item is read. The signal RREQ is supplied through the line 15 from a second external unit, for example, the pipeline execution unit 1 (FIG. 1) which receives the read enable signal ROK through the signal line 13. Only when M is no less than one (that is, unread data is still stored in the banks 47 and 48) and the data is stored in the bank to which the mode indicating signal SW indicates the R mode is the ROK signal supplied to the external unit from the R control circuit 43 through the signal line 13. Whether the data is stored in the bank 47 or the bank 48 is detected by the least significant bit of the binary represented read address RA. 
     The read address signal RAH on the signal line 99 is supplied to the selectors 451 and 452, thence it is applied to the address terminal AT of the bank 47 or 48 depending on whether the mode indicating signal SW is &#34;1&#34; or &#34;0&#34;, respectively. When the signal SW is &#34;0&#34;, the odd bank 48 is in the R mode and the read address signal RAH is supplied to the odd bank 48 through the selector 452. When the signal SW is &#34;1&#34;, the even bank 47 is in the R mode and the read address signal RAH is supplied to the even bank 47 through the selector 451. In this manner the read address signal RAH is supplied to the bank which is in the R mode. 
     As a result, the data to be read is read from the address specified by the read address signal RAH, of the bank which is in the R mode and supplied to the output terminal DOT. 
     A selection circuit 49 which comprises a selector 491 selectively supplies the output of the bank which is in the R mode to the signal line 10. When the mode indicating signal SW is &#34;0&#34;, the odd bank 48 is in the R mode and the selector 491 selects the data signal DOO read from the odd bank 48 and supplies it to the signal line 10. This signal is sent to the external unit as a read data signal RDATA. When the mode indicating signal SW is &#34;1&#34;, the even bank 47 is in the R mode and the selector 491 selects the data signal DOE read from the even bank 47 and supplies it to the second external unit via the signal line 10. It should be understood that where wired OR&#39;s can be used at the output terminals DOT of the banks 47 and 48, the function of the selector 491 can be attained by connecting the data line 471 with the data line 481 and controlling the chip select terminals (not shown) and the output enable terminals (not shown) of the banks 47 and 48. 
     The second external unit, for example, the pipeline execution unit 1 receives the signal RDATA when the signal ROK is &#34;1&#34; and the unit is ready to receive the signal RDATA, and supplies the RREQ signal to the R control circuit 43 to indicate the receipt of the read data. When the signal RREQ is &#34;1&#34;, the R control circuit 43 increments the read address RA by one in the next cycle. 
     In this manner, the data written into the banks 47 and 48 is read in the order as written with the first written data being read first such that the data at the address 0 of the even bank 47 is read first, the data at the address 0 of the odd bank 48 is read next, the data at the address 1 of the even bank 47 is read next, the data at the address 1 of the odd bank 48 is read next and so on. Thus, the memory shown in FIG. 2 has a first-in first-out memory function. As described above, since the mode is indicated to the banks independently, it is possible to write the data to the even bank 47 simultaneously with reading the data from the odd bank 48, and read the data from the even bank 47 simultaneously with writing the data to the odd bank 48. Thus, the simultaneous read and write operations can be carried out. 
     When the circuit of FIG. 1 uses the FIFO memory of FIG. 2 as the memories 20 to 22, it is necessary to synchronize the signals SW of the two FIFO memories 20 and 21. The reason therefor is explained below. In the pipeline ALU 2, it must be ensured that the sequential arrival numbers of the two input data forming the data pair provided thereto are equal if a correct processing result is to be obtained. 
     If the signals SW of the FIFO memories 20 and 21 are received at different times, however, it is not possible to determine that the pair of data items have the same arrival number at the two FIFO memories 20 and 21. To avoid the above problem, the system may be constructed such that the signals SW of all the FIFO memories in the system are always in phase. For example, the signal SW of the FIFO memory 20 may be shared by the FIFO memory 21. In FIG. 2, since the input to the execution unit 6 is only supplied from the FIFO memory 22, the synchronization of the signal SW is not necessary for the FIFO memory 22. 
     Referring to FIGS. 3A, 4 and 5, the mode specifying circuit 41, the W control circuit 42 and the R control circuit 43 will be explained in further detail. 
     The circuits 41, 42 and 43 are clocked by a single phase clock signal T having a clock period which is equal to the pipeline pitch of the ALU as well as to a memory cycle time of the banks 47 and 48. As shown by the encircled numeral at the bottom of FIG. 6, the cycles are numbered 0 to 13. Each cycle starts from a rise of the signal T and ends at the next rise of the signal T. 
     Unless otherwise specified, all flip-flops (FF) and synchronous counters (CNT) are of edge-trigger-type which are triggered by the rise of the clock input signal T. 
     In FIGS. 2 to 5, single circles at terminals of signal lines indicate interface signals terminals within the FIFO memories, and double circles indicate interface signals terminals with the external of the FIFO memories. 
     It is now assumed that the FIFO memories each can store up to eight input data items. Under this assumption, the banks 47 and 48 each may have a memory capacity of four data items. The signal line 93 for the signal WAH, the signal line 99 for the signal RAH, the signal line 57 for the signal AE and the signal line 56 for the signal AO each may have a two-bit width. 
     All of the circuits 41, 42 and 43 shown in FIGS. 3A to 5 are synchronous circuits synchronized to the clock signal T. In the following explanation, the following two assumptions are made: (1) The delay time of the gates and the delay time of the FF&#39;s and the CNT are sufficiently short relative to the cycle time of the clock signal T. (2) When the output of the FF or CNT clocked by the clock signal T is applied to the FF or CNT of the succeeding stage clocked by the same clock signal T, the FF or CNT of the succeeding stage does not mulfunction 
     The assumption (2) means that a content of the FF of the preceding stage in one cycle determines a content of the FF of the succeeding stage in the next cycle, and the content of the FF of the preceding stage does not affect the content of the FF of the succeeding stage in one cycle. When the assumption (1) is not met, the calculation and consideration of the delay times including the delay time of the banks used are necessary, and when the assumption (2) is not met, a two-phase clock signal is necessary. 
     FIG. 3A shows a circuit diagram of the mode indicating circuit 41. An output at a inverting output terminal Q of a FF 50 is applied to an input terminal D thereof. The clock signal T which assumes &#34;1&#34; once in each memory cycle or pipeline pitch is applied to a clock terminal CK of the FF 50. A signal from the non-inverted output terminal Q of the FF 50 is the mode indicating signal SW. Let us assume that the status of the FF 50 is the &#34;1&#34; state. Thus, the &#34;0&#34; output at the terminal Q is applied to the input terminal D. At a first rise of the clock signal T, the FF 50 responds to the &#34;0&#34; output of the terminal Q and the status of the FF 50 changes from the &#34;1&#34; to &#34;0&#34; states. Accordingly, the output at the terminal Q changes from &#34;0&#34; to &#34;1&#34;, and hence the input at the input terminal D also changes to &#34;1&#34;. At a second rise of the clock signal T, the FF 50 responds to the &#34;1&#34; input at the terminal D and the status of the FF 50 returns to the &#34;1&#34; state. In this manner, the status of the FF 50 repetitively flips between &#34;0&#34; and &#34;1&#34; states at the rises of the clock signal T. Accordingly, the signal SW provided from the output terminal Q of the FF 50 also repetitively flips between &#34;0&#34; and &#34;1&#34; in response to the rise of the clock signal T as shown in FIG. 6. The signal SW functions to indicate the operation mode of the banks, as described before. 
     FIG. 3B indicates the modes of the even bank 47 and the odd bank 48 indicated by the mode indicating signal SW. 
     The mode indicating circuit may; 
     (1) be one circuit provided in common for a plurality of FIFO memories so that it is shared by them for synchronism, or 
     (2) further include a circuit for altering the signal SW upon each processing of a read request so that the bank to be read next can always be selected when a possibility of competition between the read operation and the write operation has disappeared after all of the eight write data items have arrived, or 
     (3) further include a circuit for altering the signal SW upon each processing of a write request so that the even/odd state of the arriving data always coincides with the even/odd state of the bank to be indicated in the W mode under a non-competing condition of the read operation and the write operation. 
     FIG. 4 shows a circuit diagram of the W control circuit 42. The functions of CNT&#39;s and a FF of FIG. 4 and the functions of major gates are first explained and then the operation will be explained with reference to the time chart shown in FIG. 6. A CNT 62 is an edge-trigger-type synchronous counter having a one-bit output. A CNT 64 is an edge-trigger-type 3-bit synchronous counter. A terminal UP is a count-up indicating input terminal, a terminal R is a reset terminal for clearing the content, a terminal CK is an input terminal for the clock signal T and a terminal Q is an output terminal for the counter content. The count-up operation is carried out when the input signal at the terminal UP is &#34;1&#34; and the clock signal T applied to the terminal CK rises from &#34;0&#34; to &#34;1&#34;. When the input signal at the terminal UP is &#34;0&#34;, the content of the CNT does not change. A FF 63 is an edge-trigger-type FF and an output at an output terminal Q changes at a rise of the clock signal applied to a terminal CK, as does the counter 62 or 64. 
     The CNT 62 is reset by the external signal START and counts up at the end of the cycle (the rise of the clock signal T) in which the external write request signal WREQ arrives. The output WCNT of the CNT 62 indicates whether the write request (the write request signal WREQ and the write data signal WDATA) arriving in the cycle is to the odd bank 48 or to the even bank 47. When the WCNT output is &#34;0&#34;, it indicates that the write request is present to the even bank 47 and when the WCNT output is &#34;1&#34;, it indicates that the write request is present to the odd bank 48. Another output signal WCNT of the CNT 62 is of opposite polarity to the output signal WCNT. 
     The CNT 64 is reset by the external signal START and counts up at the end of the cycle in which the data is written into either one of the banks (that is, the cycle in which the signal WE is &#34;1&#34;). The output of the CNT 64 is the signal WA and the higher two bits output WAH thereof indicates the write address of the bank and the least significant bit output WAL thereof indicate the even-odd state of the write bank or whether the write bank is an even bank or not. If the output WA of the CNT 64 is &#34;000 2  &#34; (where the subscript 2 indicates a binary notation), the W control circuit 42 indicates the address 00 2  of the even bank 47 as the write address. When the output of the CNT 64 is &#34;001 2  &#34;, the address 00 2  of the odd bank 48 is indicated, and when the output WA is &#34;010 2  &#34;, the address &#34;01 2  &#34; of the even bank 47 is indicated. In order to carry out the write operation to the bank, the write enable signal WE must be &#34;1&#34;. 
     If the signal WREQ is &#34;1&#34; in a certain cycle, the data signal to be written is the signal WDATA in that cycle. The paired signals WREQ and the WDATA must arrive at the W control circuit 42 in the same cycle. 
     As shown in FIG. 3B, one of the even bank 47 and the odd bank 48 is indicated in the W mode depending on the value of the signal SW in the cycle. On the other hand, the write request arriving to the W control circuit 42 from the external unit arrives independently of the value of the signal SW. Accordingly, the W control circuit 42 carries out either one of the following two write procedures to each of the successively arriving write requests WREQ&#39;s: 
     (a) The data is written into the bank in the same cycle as the cycle of the arrival of the request. When a request WREQ has arrived and the even/odd state of the sequential number of the request arrived (that is, whether or not write data is for the even bank) coincides with the even odd state of the bank which is in the W mode in the cycle in which the request has arrived, the write procedure (a) is carried out. Hereinafter, it is called an immediate write procedure. 
     (b) The data is written into the bank in the cycle next to the cycle in which the request has arrived. When a request has arrived and the even odd state of the number of the request arrived does not coincide with even odd state of the bank which is in the W mode in the cycle in which the request has arrived, the write procedure (b) is carried out. Hereinafter it is called a delayed write procedure. 
     An exclusive-OR (EOR) gate 67 shown in FIG. 4 detects the incoincidence of the even/odd states of the arriving request and the W mode bank. The EOR gate 67 is provided with the signals SW and WCNT and provides &#34;1&#34; only when these signals have different values. If the output of the EOR gate 67 on the signal line 88 is &#34;0&#34; in a certain cycle, the even/odd states thereof coincide so that the immediate write procedure is to be carried out when the request WREQ arrives. If the output of the EOR gate 67 is &#34;1&#34;, the even/odd states do not coincide and hence the delayed write procedure is to be carried out when the request WREQ arrives. AND gates 67 and 68 detect the executions of the immediate write procedure and the delayed write procedure, respectively. A circle at one of the input terminals of the AND gate 69 indicates an inverting function of the input signal thereto as is the case of the AND gate 441 shown in FIG. 2. The necessary and sufficient condition for the &#34;1&#34; output of the AND gate 69 is that the signal WREQ on the signal line 33 is &#34;1&#34; and the signal on the signal line 88 is &#34;0&#34;. 
     If the output of the AND gate 69 on the signal line 90 is &#34;1&#34;, the write enable signal WE on the signal line 91 is rendered to be &#34;1&#34; via an OR gate 70 so that the data is written into the bank in the cycle in which the write request has arrived. This is the execution of the immediate write procedure. 
     If the output of the AND gate 68 on the signal line 89 is &#34;1&#34;, the &#34;1&#34; signal is applied to the terminal D of the FF 63, and in the next cycle the output signal WREQDL of the FF 63 on the signal line 86 assumes &#34;1&#34; and the signal WE assumes &#34;1&#34; via the OR gate 70 so that the data is written into the bank in the following cycle in which the write request WREQ has arrived. This is the execution of the delayed write procedure. Thus, the FF 63 stores the arrival of the write request WREQ which should be executed in the delayed write procedure and instructs the write operation to the bank in the next cycle. 
     When the signal WE is &#34;1&#34;, the data is written into the even bank 47 or the odd bank 48. The even/odd state of the write bank can be determined either by the signal SW or by the signal WAL. As described above, in the embodiment of FIG. 2, the signal SW is used as the odd/even selection signal for the write-to bank. 
     The write request signal WREQ is conveyed as the signal WE in the cycle in which the write request WREQ has arrived at the W control circuit 42 in the immediate write procedure and, it is temporarily stored and conveyed as the signal WE in the next cycle in the delayed write procedure. The write data signal WDATA must be also immediately used or stored until the next cycle in the former or latter procedure, respectively. The operations for the both cases for the signal WDATA can be attained by two AND gates (corresponding to the AND gates 68 and 69), a FF (corresponding to the FF 63) and an OR gate (corresponding to the OR gate 70), as is done for the signal WREQ. However, FIG. 4 shows another approach using two latches 60 and 61. 
     Latches 60 and 61 operate differently from the edge-trigger-type FF. When the clock signal at an input terminal CK is &#34;1&#34;, an input signal at an input terminal D is directly produced as an output signal at an output terminal Q, and an input signal at an input terminal D is held (or latched) even when the clock signal falls from &#34;1&#34; to &#34;0&#34;, and the latched signal level is produced at the output terminal Q until the clock signal again rises from &#34;0&#34; to &#34;1&#34;. 
     The latch 60 is used to temporarily hold the even numbered write data (the write data to the even bank 47) while the latch 61 is used to temporarily hold the odd numbered write data (the write data to the odd bank 48). In a cycle in which the even numbered write data arrives, the signal WCNT which is provided to the clock input CK of the latch 60 is &#34;1&#34; and the output signal SDRE of the latch 60 produces the signal WDATA at that time that is, the latch 60 stores an even numbered write data. At the transition to the next cycle, the signal WCNT falls from &#34;1&#34; to &#34;0&#34; and the signal WDATA is held so that the signal SDRE in the next cycle is same as that in the previous cycle. Thus, whether the data is written into the even bank 47 in the cycle in which the even numbered write request arrives or in the cycle next to the arrival cycle, the signal SDRE represents the correct even numbered write data for these writing operations. 
     The latch 61 and the output signal SDRO thereof are similar to the latch 60 and the output signal SDRE except that the clock signal to the latch 61 is the signal WCNT. The signal SDRO represents the correct write data to the odd bank. 
     The write operation of the FIFO memory 20 is now explained with reference to the time chart shown in FIG. 6. The arriving write requests are numbered from 0 to 7 and they are written into the address 0 of the even bank 47, the address 0 of the odd bank 48, the address 1 of the even bank and so on and finally into the address 3 of the odd bank. 
     While not shown in FIG. 6, the CNT 62 and the CNT 64 are reset to &#34;0&#34; by the &#34;1&#34; START signal prior to series of write operations due to these write requests. The FF 63 is also reset by the &#34;1&#34; START signal applied to the reset terminal R, indicating that the first write request is even numbered one. 
     In the example shown in FIG. 6, the immediate write procedure is carried out for the write requests 0 to 2, the delayed write procedure is carried out for the write requests 3 and 4, and the immediate write procedure is carried out for the write requests 5 to 7. 
     First, the write request 0 arrives in a cycle &#34;0&#34; as indicated by encircled numeral 0. The signal WREQ on the signal line 33 and the signal WDATA on the data line 30 are supplied to the W control circuit 42. The signal WREQ is &#34;1&#34; and the signal WDATA represents the write data. In the cycle &#34;0&#34;, the signal WCNT is still &#34;0&#34; and, in the example shown in FIG. 6, the signal SW is &#34;0&#34; indicating that the even bank is in the W mode. Accordingly, the output of the EOR gate 67 is &#34;0&#34;, the output of the AND gate 68 is &#34;0&#34;, the output of the AND gate 90 is &#34;1&#34; and the output signal WE of the OR gate 70 is &#34;1&#34;. In the cycle in which the signal WE is &#34;1&#34;, the data is written into the bank which is specified to the W mode by the signal SW, as shown in FIG. 2. That is, the signal WEE on the signal line 59 is changed to &#34;1&#34; by the AND gate 441 shown in FIG. 2 to indicate the write operation to the even bank 47. 
     The write address is explained below. After the CNT 64 of FIG. 4 has been reset by the signal START, the output of the CNT 64 remains &#34;000 2  &#34; in the cycle &#34;0&#34; as indicated by encircled numeral 0, and the signal WAH which comprises the higher order two bits of the output of the CNT 64, that is, &#34;00 2  &#34;, is supplied to the address line 93. Since the signal SW is &#34;0&#34;, the selector 451 of FIG. 2, which determines the memory address signal AE to the even bank 47, selects the write address signal WAH on the address line 93 and supplies it to the address line 57. In this manner, in the cycle &#34;0&#34;, the correct address &#34;00 2  &#34; is applied to the address terminal AT of the even bank 47. The signal RAH is applied to the address terminal AT of the odd bank 48 by the selector 452, but the write operation is not carried out because the signal WEO is &#34;0&#34; by the function of the AND gate 442. 
     The write data operation is now explained. In FIG. 4, since the signal WCNT is &#34;1&#34; in the cycle &#34;0&#34;, the latch 60 produces the signal WDATA which corresponds to the request 0 on the data line 30, as the signal SDRE on the data line 82. Since the signal SW is &#34;0&#34;, the selector 461 of FIG. 2 supplies the signal SDRE on the data line 82 to the data line 55. Thus, in the cycle &#34;0&#34;, the 0-th write data signal WDATA is correctly applied to the data input terminal DIT of the even bank 47. 
     In a cycle &#34;1&#34;, the write request 1 arrives and the data is written into the odd bank 48 unlike the write operation in the cycle &#34;0&#34;. Since the signal SW is &#34;1&#34;, the signal WEE is &#34;0&#34; and the signal WEO is &#34;1&#34;. The signal WAH is selected by the selector 452 and supplied as the signal AO, and the signal SDRO is selected by the selector 461 and supplied as the signal DIO. The 3-bit output of the CNT 64 of FIG. 4 changes to &#34;001 2  &#34; when the cycle transits from &#34;0&#34; to &#34;1&#34; because the signal WE was &#34;1&#34; in the cycle &#34;0&#34;. The output signals WCNT and WCNT of the CNT 62 are inverted to &#34;1&#34; and &#34;0&#34;, respectively, in the cycle &#34;1&#34; because the signal WREQ was &#34;1&#34; in the cycle &#34;0 &#34;. The output WREQDL of the FF 63 remains &#34;0&#34; in the cycle &#34;1&#34; because the output of the AND gate 68 was &#34;0&#34; in the cycle &#34;0&#34;. The content of the signal WDATA in the cycle &#34;0&#34; has been held in the latch 60 and it is supplied in the cycle &#34;1&#34; as the signal SDRE but it is not used. 
     In a cycle &#34;2&#34;, the request 2 arrives and the data is written into the even bank 47. The output of the CNT 64 changes to &#34;010 2  &#34; in the cycle &#34;2&#34; becuase the signal WE was &#34;1&#34; in the cycle &#34;1&#34;. Accordingly, the second write request data signal WDATA is written into the address 1 of the even bank 47. 
     In the example shown in the time chart of FIG. 6, the write request 3 arrives not in a cycle &#34;3&#34; but in a cycle &#34;4&#34;. In the cycle &#34;4&#34;, since the arriving request is odd numbered and the odd bank 48 is not in the W mode, the write operation to the odd bank 48 for the write request 3 is executed in the next cycle &#34;5&#34;. In FIG. 4, in the cycle &#34;4&#34;, the signal WCNT is &#34;1&#34; and the signal SW is &#34;0&#34;. The signal on the signal line 89 is changed to &#34;1&#34; and the signal on the signal line 88 is changed to &#34;0&#34; by the function of the EOR gate 67 and the AND gate 68. The FF 63 produces the &#34;1&#34; WREQDL signal in the cycle &#34;5&#34; because &#34;1&#34; is applied to the input signal terminal D. The bank write enable signal WE is &#34;0&#34; in the cycle &#34;4&#34; and changes to &#34;1&#34; in the cycle &#34;5&#34; to indicate the third write operation. This is the delayed write procedure described above. 
     The CNT 64 which generates the write address WA holds the same content &#34;011 2  &#34; through the cycles &#34;3&#34; to &#34;5&#34; because the signal WE was &#34;0&#34; in the cycles &#34;3&#34; and &#34;4&#34;. In the cycle &#34;5&#34;, the correct memory address &#34;01 2  &#34; is supplied to the odd bank 48. 
     The write data operation is explained below. In the cycle &#34;4&#34;, the third write data signal WDATA arrives. Since the signal WCNT which clocks the latch 61 is &#34;1&#34; in the cycle &#34;4&#34; and &#34;0&#34; in the cycle &#34;5&#34;, the content of the output signal SDRO of the latch 61 is identical to the content of the signal WDATA in the cycle &#34;4&#34; as well as the cycle &#34;5&#34;. 
     Accordingly, the write data for the request 3 can be correctly supplied to the odd bank 48 in the cycle &#34;5&#34;. 
     The W control circuit 42 of FIG. 4 cannot execute the write operation to the odd bank 48 for the write request 3 in the cycle &#34;4&#34;, but can execute it in the next cycle &#34;5&#34;. From the periodicity of the signal SW, it is predicted that if the signal SW is &#34;0&#34; in the cycle &#34;4&#34;, it will be &#34;1&#34; in the next cycle &#34;5&#34;. 
     The write request 4 also arrives in the cycle &#34;5&#34; in which the even bank 47 is not in the W mode and hence the data is written into the even bank 47 with one cycle delay. 
     The request 5 arrives in the cycle &#34;7&#34; in which the odd bank 48 is in the W mode so that the data is immediately written into the odd bank 48 as is done for the requests 0, 1 and 2. Thus, the immediate write procedure is carried out with the signal WREQ and the signal WE being &#34;1&#34; in the same cycle &#34;7&#34;. 
     Each time when the data for one of the eight write requests is written into the bank, the 3-bit counter CNT 64 is counted up so that the output changes from &#34;000 2  &#34; to &#34;111&#34;. In a cycle &#34;10&#34;, the output may return to &#34;000 2  &#34; but the content at the address &#34;00 2  &#34; of the even bank 47 is not destroyed because the write request 8 does not arrive from the external. 
     FIG. 5 shows a circuit diagram of the R control circuit 43. An edge-trigger-type counter (CNT) 100 is a reversible 4-bit counter. The count-up and count-down modes of the counter 100 are indicated by inputs to a count-up terminal UP and a count-down terminal DOWN. When the write enable signal WE provided to the terminal UP is &#34;1&#34; and the read request signal RREQ provided to the terminal DOWN is &#34;0&#34;, the counter 100 counts up by one at the rise of the clock signal T applied to a clock terminal CK. When the input signal WE to the terminal UP is &#34;0&#34; and the input signal RREQ to the terminal DOWN is &#34;1&#34;, the counter 100 counts down by one. When both inputs are &#34;0&#34; or &#34;1&#34;, the counter 100 does not count up or count down. A 4-bit output REQCNT of the CNT 100 is supplied to a 4-bit data line 101. The content of the CNT 100 indicates the number of data items which were written but have not been read. The CNT 100 is the 4-bit counter so that it can store nine different numbers 0-8 of the input data. The CNT 100 is reset by the initializing signal START applied to a reset terminal R. The 4-bit output of the CNT 100 is supplied to an OR gate 104 which OR&#39;s the respective bits and supplies the result to a signal line 105. If the output of the OR gate 104 is not &#34;0&#34;, it indicates the presence of data which were written into the banks 47 and 48 and have not been read. A CNT 109 is a binary 3-bit counter which is reset by the initializing signal START applied to a reset terminal R and counts up at the rise of the clock signal T applied to a clock terminal CK when the input signal RREQ to a count-up terminal UP is &#34;1&#34;. 
     The content of the binary 3-bit CNT 109 indicates the read address. The CNT 109 supplies the higher two bits of the content to the address line 99 as the bank read address RAH and supplies the low one bit to the signal line 111 as the signal RAL to indicate the odd even state of the bank to be read. 
     Numeral 112 denotes an exclusive OR (EOR) gate which determines if the bank to be read coincides with the bank indicated in the R mode by the mode indicating signal SW. When the low order bit signal RAL of the CNT 109 is &#34;0&#34;, the even bank 47 is to be read therefrom, and when the signal SW is &#34;1&#34; the even bank 47 is in the R mode. When the signal RAL is &#34;1&#34;, the odd bank 48 is to be read therefrom, and when the signal SW is &#34;0&#34;, the odd bank 48 is in the R mode. Accordingly, the EOR gate 112 produces a &#34;1&#34; output when the bank to be read coincides with the bank indicated in the R mode by the mode indicating signal, and produces a &#34;0&#34; output otherwise. An AND gate 106 ANDs the signals on the signal lines 105 and 113. Accordingly, the read enable signal ROK from the output of the AND gate 106 is &#34;1&#34; only when there are data in the banks 47 and 48 which were written but have not yet been read, and the bank to be read is in the R mode. Otherwise, the signal ROK is &#34;0&#34;. The signal ROK indicates that the FIFO memory is ready to be read, as described before. 
     The operation of the R control circuit is explained with reference to the time chart shown in FIG. 6. 
     The external circuit assures that the read request signal RREQ supplied from the signal line 15 assumes &#34;1&#34; only when the signal ROK is &#34;1&#34;. For example, the pipeline control logic circuit 3 of FIG. 1 assures it. The CNT&#39;s 100 and 109 are initialized to &#34;0&#34; by the signal START prior to a series of read operations, as is done in the W control circuit. 
     In the cycle &#34;0&#34;, the write data 0 is written into the even bank 47 and the signal WE is &#34;1&#34; and the CNT 100 counts up at the rise of the clock signal T. In the cycle &#34;1&#34;, the output REQCNT of the CNT 100 changes to &#34;0001 2  &#34; and the OR gate 104 supplies the &#34;1&#34; output to the signal line 105 to indicate the presence of the unread data in the bank. On the other hand, in the cycle &#34;1&#34;, the EOR gate 112 determines that the signal SW is &#34;1&#34; and the even bank 47 is in the R mode and supplies the &#34;1&#34; output to the signal line 113. The AND gate 106 determines that the two conditions are met and supplies the &#34;1&#34; ROK signal to the signal line 13. 
     In the example shown in FIG. 6, the external signal RREQ changes to &#34;1&#34; in response to the signal ROK. When the signal RREQ on the signal line 15 is &#34;1&#34;, the CNT 109 counts up. In the cycle &#34;1&#34;, the CNT 100 does not count because the signal WE indicating the first write is &#34;1&#34;. In the next cycle &#34;2&#34;, the output signal REQCNT remains at &#34;0001 2  &#34; indicating the presence of one unread data item. In the cycle &#34;1&#34;, the output signal RAH which is the higher order two bits of the content of the CNT 109 is &#34;00&#34; and it is supplied to the selection circuit 45 of FIG. 2 via the data line 99. In the cycle &#34;1&#34;, since the signal SW is &#34;1&#34;, the selector 451 in the selection circuit 45 selects the signal RAH and supplies it to the address terminal AT of the even bank 47. On the other hand, since the signal SW is &#34;1&#34;, the AND gate 441 in FIG. 2 produces the &#34;0&#34; WEE signal. Because the signal WEE is &#34;0&#34;, the data is read from the bank 47 at the address &#34;00&#34; specified by the signal AE, and supplies the content of the data O written in the immediately previous cycle, to the data line 471 as the signal DOE. Since the signal SW is &#34;1&#34;, the selector 491 in FIG. 2 selects the signal DOE and supplies it to the data line 10 as the signal RDATA. In this manner, the data 0 is supplied to the signal RDATA in the cycle &#34;1&#34;. 
     The read operations for the data 1 and 2 are similar to that described above except the value of the signal SW and the odd/even state of the banks. 
     The data 3 is written three cycles after the completion of the writing of the data 2. As a result, in the cycle &#34;3&#34; in which the data 2 is read, the signal RREQ is &#34;1&#34; and the signal WE is &#34;0&#34; so that the CNT 100 counts down. In the next cycle &#34;4&#34;, the signal REQCNT changes to &#34;0000 2  &#34;, the signal ROK changes to &#34;0&#34; and the &#34;1&#34; RREQ signal is not applied. Accordingly, the reading operation for the data 3 is not carried out. In the cycle &#34;6&#34; following the cycle in which the signal WE changes to &#34;1&#34; in response to the third write request signal WREQ, the signal REQCNT changes to &#34;0001 2  &#34; and the signal ROK changes to &#34;1&#34;. In the example shown in FIG. 6, the signal RREQ remains &#34;0&#34; by some external cause. In the next cycle &#34;7&#34;, the signal SW changes to &#34;1&#34; and the signal ROK changes to &#34;0&#34; because the odd bank 48 in which the data 3 is stored is not in the R mode. In this cycle, the content of the CNT 100 is &#34;0010 2  &#34; reflecting the fourth writing in the immediately previous cycle. In the next cycle &#34;8&#34;, the signal SW is &#34;0&#34; and the signal ROK is &#34;1&#34; and the signal RREQ is &#34;1&#34;. In the cycle &#34;8&#34; the signal REQCNT has been increased to &#34;0011 2  &#34;. 
     The data items 4 to 7 are read sequentially. In the cycle &#34;12&#34;, the last data item 7 is supplied as the signal RDATA. During thirteen cycles from the cycle &#34;0&#34; to the cycle &#34;12&#34;, the eight write requests and the eight read requests are handled in the FIFO memory. During the four cycles from the cycle &#34;6&#34; to the cycle &#34;9&#34;, the four write requests and the four read requests are handled parallel, one set in each cycle, so that a maximum performance of the FIFO memory is attained. 
     When the present invention is applied to the pipeline execution units, the FIFO memory may be fixedly combined with the execution units as shown in FIG. 1 or the combination may be dynamically altered by a computer program. FIG. 7 shows an example of the latter, in which distribution logic circuits 911 and 912 are arranged between the pipeline execution units 901, 902, 903 and the FIFO memories 921, 922, 923, 924, 925. The distribution logic circuits 911 and 912 function to allocate the FIFO memories to the input ports and the output ports of the units in accordance with external instructions. The distribution logic circuits 911 and 912 each comprises a plurality of multi-input selectors which are known per se. For example, at a certain time point, the distribution logic circuit 912 may select the output of the FIFO memory 921 as the input to the unit 903 and the distribution logic circuit 911 may select the output of the unit 903 as the input to the FIFO memory 922, and at another time point, the FIFO memory 923 may be selected as the input to the unit 903 and the FIFO memory 924 may be selected as the output. The distribution logic circuit 911 and 912 may be constructed of a number of selectors. 
     The FIFO memories 921 to 925 do not include the mode indicating circuit 41 shown in FIG. 2. A mode indicating circuit 910 corresponds to the mode indicating circuit 41, and is shared by the FIFO memories 921 to 925. 
     The execution units shown in FIG. 7 may be ALU units which carry out addition, subtraction, multiplication and division operations or storage control units capable of storing a large volume of data. 
     As described hereinabove, in accordance with the FIFO memory of the present invention, the read and write operations can be simultaneously carried out. When the write request arrives, the write data can be written into the FIFO memory without a waiting time.