Abstract:
A CAM device combines a folded bit line architecture with a standard six transistor DRAM based CAM cell and includes a sensing scheme where the active and reference bit lines being sensed are each from the same memory array of the CAM device. Noise present in one array therefore appears as common mode noise in both the active and reference bit lines, thereby permitting the sensing operation to be performed accurately even in the presence of increased noise.

Description:
FIELD OF INVENTION  
         [0001]    The present invention relates generally to semiconductor memory devices and, more particularly to sensing DRAM based content addressable memory (CAM).  
         BACKGROUND OF THE INVENTION  
         [0002]    An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM allows a memory circuit to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).  
           [0003]    Another form of memory is the content addressable memory (CAM) device. A CAM is a memory device that accelerates any application requiring fast searches of a database, list, or pattern, such as in database machines, image or voice recognition, or computer and communication networks. CAMs provide benefits over other memory search algorithms by simultaneously comparing the desired information (i.e., data in the comparand register) against the entire list of pre-stored entries. As a result of their unique searching algorithm, CAM devices are frequently employed in network equipment, particularly routers and switches, computer systems and other devices that require rapid content searching.  
           [0004]    In order to perform a memory search in the above-identified manner, CAMs are organized differently than other memory devices (e.g., DRAM). For example, data is stored in a RAM in a particular location, called an address. During a memory access, the user supplies an address and writes into or reads the data at the specified address.  
           [0005]    In a CAM, however, data is stored in locations in a somewhat random fashion. The locations can be selected by an address bus, or the data can be written into the first empty memory location. Every memory location includes one or more status bits which maintain state information regarding the memory location. For example, each memory location may include a valid bit whose state indicate whether the memory location stores valid information, or whether the memory location does not contain valid information (and is therefore available for writing).  
           [0006]    Once information is stored in a memory location, it is found by comparing every bit in memory with data in the comparand register. When the content stored in the CAM memory location does not match the data in the comparand register, the local match detection circuit returns a no match indication. When the content stored in the CAM memory location matches the data in the comparand register, the local match detection circuit returns a match indication. If one or more local match detect circuits return a match indication, the CAM device returns a “match” indication. Otherwise, the CAM device returns a “no-match” indication. In addition, the CAM may return the identification of the address location in which the desired data is stored or one of such addresses if more than one address contained matching data. Thus, with a CAM, the user supplies the data and gets back the address if there is a match found in memory.  
           [0007]    [0007]FIG. 1 is a circuit diagram showing a conventional DRAM-based CAM cell  100 , which includes two one-transistor (1T) DRAM cells  110   a  and  110   b,  and a four-transistor comparator circuit  120  made up of transistors Q 2  through Q 6 . DRAM cells  110   a  and  110   b  are used to store values. Generally, the content of cell  110   a  is the logical NOT of the content of cell  110   b.  However, the cells  110   a,    110   b  may also store the same values, i.e., “1”, “1”, or “0”, “0”, so that the CAM cell is respectively set to “always match” or “always mismatch” states. DRAM cell  110   a  includes transistor Q 1  and a capacitor CA, which combine to form a storage node A that receives a data value from bit line BL 1  at node U during write operations, and applies the stored data value to the gate terminal of transistor Q 2  of comparator circuit  120 . Transistor Q 2  is connected in series with transistor Q 3 , which is controlled by a data signal transmitted on data line D 1 , between a match line M and a discharge line D. The second DRAM cell  110   b  includes transistor Q 3  and a capacitor CB, which combine to form a storage node B that receives a data value from bit line BL 2  at node V, and applies the stored data value to the gate terminal of transistor Q 4  of comparator circuit  120 . Transistor Q 4  is connected in series with transistor Q 5 , which is controlled by a data signal transmitted on inverted data line D 1 #, between the match line and the discharge line.  
           [0008]    [0008]FIG. 2 is a block diagram of a portion of a CAM device  200  which includes a plurality of CAM cells, such as the CAM cell  100  of FIG. 1. For purposes of simplicity, only a portion of the CAM device  200  is illustrated. In particular, some well known components, such as the previously discussed comparand register, control logic, and I/O logic are not illustrated. The device  200  includes two arrays  210   a,    210   b  of CAM cells  100 . Each array  210   a,    210   b  includes its own bit lines (e.g., BL 11 -BL 16  for array  210   a,  BL 21 -BL 26  for array  210   b ) and word lines (e.g., WL 11 -WL 13  for array  210   a ). Each word line WL 11 -WL 13 , WL 21 -WL 23  is coupled a respective word line driver  220   a,    220   b.  Similarly, each bit line is also coupled to respective bit line drivers (not illustrated). The CAM device  200  also includes a plurality of sense amplifiers  230 . Each sense amplifier  230  is coupled to the CAM cells  100  of two separate bit lines (e.g., bit lines BL 11 , BL 21 ) from two different arrays. This type of architecture, where a sense amplifier is coupled to bit lines from different arrays, is known as an open bit line architecture.  
           [0009]    Now referring back to FIG. 1, in order perform a write operation upon a CAM cell, the data values (which are complements) to be stored are respectively written to dynamic storage nodes A and B by applying appropriate voltage signals (e.g., Vcc for logical ‘1’ or ground for logical ‘0’) on bit lines BL 11  and BL 21 , and then applying a high voltage signal on word lines WL 1  and WL 2 . The high voltage on word lines WL 1  and WL 2  turn on transistor Q 1  and Q 2 , thereby passing the voltage signals to dynamic storage nodes A and B. Refresh circuitry (not illustrated), periodically refreshes the charges stored in capacitors CA and CB, so the data does not decay over time.  
           [0010]    In order to perform a match operation, the data stored at nodes A and B are respectively applied to the gate terminals of transistors Q 2  and Q 5  of comparator circuit  120 . Comparator circuit  120  is utilized to perform match (comparison) operations by, for example, precharging the match line M, grounding the discharge line D, and transmitting an applied data value and its complement respectively on data lines D 1  and D 1 # to the gate terminals of transistor Q 3  and Q 6 , respectively. A no-match condition is detected when match line M is discharged to ground through the signal path formed by transistors Q 2  and Q 3  and the discharge line D, or through the signal path formed by transistors Q 5  and Q 6  and the discharge line D. For example, when the stored data value at node A and the applied data value transmitted on data line D 1 # are both logic “1”, then both transistors Q 2  and Q 3  are turned on to discharge match line M to the discharge line (e.g., ground). When a match condition occurs, match line M remains in its pre-charged state (i.e., no signal path is formed by transistors Q 2  and Q 3 , or transistors Q 5  and Q 6 ).  
           [0011]    In order to perform a read operation, data stored as a charge level in the capacitors CA, CB of one of the dynamic storage nodes A, B of the CAM cell  100  is sensed using an associated sense amplifier  230  (FIG. 2) which compares the voltage level of a bit line coupled to one of the dynamic storage nodes (known as the active bit line) with the voltage level of a bit line not coupled to any dynamic storage nodes (known as the reference bit line). For example, node A of the CAM cell  100  which appears as the top left CAM cell illustrated in FIG. 2 can be sensed by first precharging two bit lines. The two bit lines to be precharged would include the bit line BL 11  which will couple the CAM cell  100  to the sense amplifier  230  (i.e., the active bit line), as well as the other bit line BL 21  coupled to the same sense amplifier  230  (i.e., the reference bit line). As illustrated in FIG. 2, each sense amplifier has one input coupled to a bit line of array  210   a  and another input coupled to a corresponding bit line of array  210   b.  The word line WL 13  associated with the CAM cell  100  would then be charged, causing the transistor Q 1  in the CAM cell  100  to conduct and thereby share the charge of capacitor CA with bit line BL 1 . The charge sharing alters the voltage level of bit line BL 11 . The sense amplifier  230  is then used to detect the change in potential between BL 11  and BL 21 . The sense amplifier outputs an indication of the state stored at storage node A as a signal indicating the relative potential difference between bit lines BL 11  and BL 21  on line  235 .  
           [0012]    The performance of the above described read operation suffers from many noise issues since the sensing mechanism relies on the reference and active bit lines to be from two separate arrays of the device during a sensing operation. As CAM devices increase in density and therefore power consumption, the level of noise within a CAM cell is likely to increase. There is therefore a need for a CAM device architecture which has better noise immunity.  
         SUMMARY OF THE INVENTION  
         [0013]    The present invention is directed to a CAM device which combines a folded bit line architecture with a standard six transistor DRAM based CAM cell. The CAM device of the present invention has a sensing scheme where the active and reference bit lines being sensed are each from the same memory array of the CAM device. Noise present in one array therefore appears as common mode noise in both the active and reference bit lines, thereby permitting the sensing operation to be performed accurately even in the presence of increased noise. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    The foregoing and other advantages and features of the invention will become more apparent from the detailed description of exemplary embodiments of the invention given below with reference to the accompanying drawings, in which:  
         [0015]    [0015]FIG. 1 is a circuit diagram of a conventional six transistor DRAM based CAM cell;  
         [0016]    [0016]FIG. 2 is a block diagram illustrating a conventional CAM device using an open bit line scheme;  
         [0017]    [0017]FIG. 3A is a block diagram illustrating a CAM device in accordance with a first embodiment of the present invention;  
         [0018]    [0018]FIG. 3B is a block diagram illustrating a CAM device in accordance with a second embodiment of the present invention;  
         [0019]    [0019]FIG. 4 is a circuit diagram of modified sense amplifier circuit used with the CAM device of FIG. 3; and  
         [0020]    [0020]FIG. 5 is a block diagram of a processor based system utilizing the CAM device of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0021]    Now referring to the drawings, where like reference numerals designate like elements, there is shown in FIG. 3A a block diagram illustrating one embodiment of a CAM device  300  in accordance with the principles of the present invention.  
         [0022]    The device  300  is illustrated as having two arrays  210   a,    210   b  of CAM cells  100 . For purposes of simplicity, only a portion of the CAM device  300  is illustrated. In particular, some well known components, such as the comparand register, control logic, and I/O logic are not illustrated. It should be noted that the invention may be practiced even if the number of arrays is varied. Each array  210   a,    210   b  is comprised of a plurality of CAM cells  100 , which preferably are of the six transistor DRAM based embodiment previously discussed in connection with FIG. 1. Each CAM cell  100  is located at an intersection of a word line (e.g., WL 11 ) and a bit line (e.g., BL 11 ). Each word line is also coupled to a word line driver  220   a,    220   b.  Each bit line is also coupled to a bit line driver (not illustrated) and a sense amplifier circuit  231 .  
         [0023]    Now referring also to FIG. 4, it can be seen that the sense amplifier circuit  231  is coupled to four inputs BLA, BLB, BLC, and BLD. The sense amplifier  231  includes a front-end circuit  233  comprising multiplexers  232   a,    232   b,  and select signal input sel. (The sel signal can be controlled by the control circuit, which as noted above, is not illustrated in the drawings.) The two multiplexers  232   a,    232   b  are controlled based on the state of the sel signal so that either signals BLA/BLC or signals BLB/BLD are selected for sensing by the sense amplifier  230 . The result of the sensing is output on line  235 .  
         [0024]    [0024]FIG. 3B is an illustration of the CAM device  300  built in accordance with a second embodiment of the present invention. The CAM device  300  of FIG. 3B differs from that illustrated in FIG. 3A by using pairs of sense amplifiers  230  instead of the single sense amplifier circuit  231 . The embodiment illustrated in FIG. 3B therefore does not require the use of a sel control line for controlling the multiplexers  232   a,    232   b  (FIG. 4) corresponding to the sense amplifier circuit  231  of FIG. 3A. However, the embodiment shown in FIG. 3B requires using twice as many sense amplifiers  230 .  
         [0025]    Thus, one significant difference between device  300  and prior art devices (e.g., device  200 ) is that each sensing operation is performed using an active and a reference bit line from the same array (e.g.,  210   a ). By always sensing two lines from the same array, any noise which appears only in one array is less likely to disrupt the sensing operation because the noise will appears as common mode noise across both the active and reference bit lines, thereby identically affecting the potential of the active and reference bit lines, and having no effect on the potential difference at any point in time between the active and reference bit lines. This property permits the use of ordinary sense amplifiers, even in higher level noise environments. By contrast, if an open bit line architecture were used, noise present in one array may result in an incorrect sensing operation.  
         [0026]    [0026]FIG. 5 is an illustration of a processor based system  500  including a chip  300  in accordance with the present invention. The system  500  includes a central processing unit (CPU)  510 , a main memory  502 , at least one mass storage device  503 , at least peripheral devices  504 - 505  (e.g., keyboard and display), and a CAM subsystem  506 . The CAM subsystem  506  includes a plurality of CAM devices  300  of the present invention.  
         [0027]    An example of a processor based system  500  may be a network router, in which case peripheral devices  504 - 505  may be network cards attached to different computer networks. The main memory  502  may include a random access memory for storing data, and a read only memory for storing a boot loader, and the mass storage device  503  may store an operating system and application software for the router. The CAM subsystem  506  may be used to store network routing table.  
         [0028]    While the invention has been described in detail in connection with the exemplary embodiment, it should be understood that the invention is not limited to the above disclosed embodiment. Rather, the invention can be modified to incorporate any number of variations, alternations, substitutions, or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Accordingly, the invention is not limited by the foregoing description or drawings, but is only limited by the scope of the appended claims.