Abstract:
The invention relates to a leadframe for semiconductor packages and a mold for molding the semiconductor package. The leadframe of the invention reduces occurrences of chip-out and floating of a chip paddle upon singulation after encapsulation. The leadframe inner voids define a chip paddle. At least one end of an inner void extends outwardly beyond a dam bar to provide a flow under pathway for encapsulating material when the leadframe is engaged by a top mold. The top mold has a sill that is continuous, e.g. tetragonal in shape, such that encapsulating material must flow under the sill when the top mold is clamping the leadframe. Encapsulating material is flowed into a mold gate of the leadframe and under a portion of the sill to engulf the semiconductor chip within the cavity formed by the top mold and the leadframe.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a leadframe for semiconductor packages, as well as a combination of a top mold and the leadframe. Further, the present invention relates to a mold for molding the semiconductor package. More particularly, but not by way of limitation, the present invention relates to a leadframe that reduces occurrences of chip-out and floating of a chip paddle upon singulation after encapsulation, and a mold for molding the same. 
     2. History of Related Art 
     It is conventional in the electronic industry to encapsulate one or more semiconductor devices, such as integrated circuit dies, or chips, in a semiconductor package. These plastic packages protect a chip from environmental hazards, and provide a method of and apparatus for electrically and mechanically attaching the chip to an intended device. Recently, such semiconductor packages have included metal leadframes for supporting an integrated circuit chip which is bonded to a chip paddle region formed centrally therein. Bond wires which electrically connect pads on the integrated circuit chip to individual leads of the leadframe are then incorporated. A hard plastic encapsulating material, or encapsulant, which covers the bond wire the integrated circuit chip and other components, forms the exterior of the package. A primary focus in this design is to provide the chip with adequate protection from the external environment in a reliable and effective manner. 
     As set forth above, the semiconductor package therein described incorporates a leadframe as the central supporting structure of such a package. A portion of the leadframe completely surrounded by the plastic encapsulant is internal to the package. Portions of the leadframe extend internally from the package and are then used to connect the package externally. More information relative to leadframe technology may be found in Chapter 8 of the book  Micro Electronics Packaging Handbook , (1989), edited. by R. Tummala and E. Rymaszewski. This book is published by Van Nostrand Reinhold, 115 Fifth Avenue, New York, N.Y., which is hereby incorporated by reference. 
     Once the integrated circuit chips have been produced and encapsulated in semiconductor packages described above, they may be used in a wide variety of electronic appliances. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically include a motherboard on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic appliances are typically manufactured in reduced sizes and at reduced costs, consumer demand increases. Accordingly, not only are semiconductor chips highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density. 
     According to such miniaturization tendencies, semiconductor packages, which transmit electrical signals from semiconductor chips to motherboards and support the semiconductor chips on the motherboards, have been designed to have a small size. By way of example only, such semiconductor packages may have a size on the order of 1×1 mm to 10×10 mm. Examples of such semiconductor packages are referred to as MLF (micro leadframe) type semiconductor packages and MLP (micro leadframe package) type semiconductor packages. Both MLF type semiconductor packages and MLF type semiconductor packages are generally manufactured in the same manner. 
     A typical leadframe used in a semiconductor package is comprised of a plate-type metal frame body that is provided with and a tie bar, which is internally extended from each of the four corners. A chip paddle is in contact with the tie bars. A semiconductor chip is mounted on the chip paddle. A plurality of leads are located along and at a distance away from the perimeter of the chip paddle. From the internal leads external leads are extended with their terminals being connected to the frame body. Dam bars  10  are provided between the internal leads and the external leads to prevent a molding material from flowing over the external leads upon encapsulating. The dam bars, the external leads, and predetermined areas of the tie bars and the frame body are all removed in a subsequent singulation process. 
     After a semiconductor chip is mounted on the chip paddle, the leadframe is positioned between a top mold and a bottom mold and encapsulated by a molding material. 
     The top mold is designed to clamp the dam bar of the leadframe and a part of the internal leads located at the internal side of the dam bar with the aid of a sill and to provide a cavity on the internal side of the sill in which the semiconductor chip, etc. are encapsulated with the encapsulation material. At one side of the cavity, a mold gate is formed as a passage through which the encapsulation material flows. To discharge the air, gas and dregs of the encapsulation material, (hereinafter referred to as flash), to the outside in the molding process, a plurality of air vents are also provided. 
     The mold gate is formed to have a space between the tie bar of the leadframe and the upper surface of the body. Because the four corner areas of the leadframe (in which the tie bars are formed) are not clamped by the sill of the top mold and because the mold gate is connected to the cavity, the molding material flows along the upper surface of the leadframe, the upper surface and opposite end sides of the tie bars and the mold gate into the inside of the cavity. Herein, the upper surface of the tie bar and its opposite end sides in the leadframe, with which the molding material is in contact while flowing into the cavity, is defined as a frame gate. 
     In addition, a mold air vent formed in the top mold is connected to the cavity, so that the molding material flash, gas and air are discharged along the surface of the leadframe, the upper surface and opposite end sides of the tie bar and the mold air vent to the outside in the molding process. Herein, the upper surface of the tie bar and its opposite end sides in the leadframe, with which the flash is in contact while flowing into the cavity, is defined as a mold air vent. 
     After completion of the encapsulation, a molding material flash is usually formed at the side of the package body. That is, a significant amount of the flash is formed at positions corresponding to the mold gate of the top mold and to the mold air vent, respectively. In addition, the flash is connected to the package body formed inside the cavity. Some flash is removed when the leadframe is ejected from the top mold and the bottom mold. 
     The flash is not uniform in thickness owing to various factors such as molding pressure, molding period of time, temperature, etc. and, therefore causes problems in the singulation of the leadframe. 
     The encapsulated semiconductor package is preferably firmly positioned between a bottom clamp and an upper clamp while turning upside down. Thereafter, a boundary area between the internal leads, the dam bars and a predetermined area of the tie bars are cut with the aid of a singulation tool. At this time, any flash present on the tie bars of the leadframe prevents close contact of the semiconductor package with the bottom clamp. 
     After the singulation tool is allowed to descend, different stresses are generated at the square corners of the semiconductor package, which may result in cracking a part of the package body and even causing a chip-out phenomenon. Once a chip-out occurs, the semiconductor package, even though able to function normally, has a reduced commercial value and thus, is less marketable. Where a serious chip-out phenomenon occurs, wires that connect the semiconductor chip and the internal leads may be cut or the semiconductor chip may be exposed to the outside of the package body. 
     Because the sill of the top mold clamps only the internal leads and the dam bars during the encapsulation, the pressure of the molding material causes the chip paddle to lean on one side or float, giving rise to an increase in wire sweeping in addition to leaving a significant amount of flash on the bottom surface of the chip paddle. In an MLF package, typically, the internal leads and the chip paddle are externally exposed at their bottom surfaces. Thus, when a flash is formed on the chip paddle, it must be removed or the semiconductor package is regarded defective. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention relates to leadframes for semiconductor packages. More particularly, one aspect of the present invention comprises a semiconductor package, including a frame body and a chip paddle that is defined by inner voids that are formed in the frame body. The leadframe has at least one tie bar that communicates with an outer portion of the frame body with the chip paddle and at least one dam bar in communication with an outer surface of the inner void. In the embodiment presented, at least one end of an inner void extends outwardly beyond the dam bar to provide a flow under pathway for the encapsulating material when the leadframe is engaged by a top mold. 
     In the above described embodiment of the present invention, the top mold comprises a sill that protrudes from a face of a base plate. The sill defines a cavity and has a contact surface on a distal end of the sill. The sill in continuous such that the cavity is completely enclosed when the contact surface is mated against a flat surface. When the contact surface of the sill engages the leadframe, the sill clamps onto the die bar of the leadframe. In another embodiment, the sill is wider such that the sill engages the dam bar, a plurality of inner leads and a plurality of outer leads of a leadframe when the upper mold engages the leadframe. 
     The semiconductor chip assembled in accordance with the various embodiments of the present invention is also encapsulated to form a semiconductor package by locating a semiconductor chip on a chip paddle of a leadframe. The leadframe is clamped by the sill of a top mold. Encapsulating material is flowed into a mold gate of the leadframe and under a portion of the sill to engulf the semiconductor chip within the cavity formed by the top mold and the leadframe. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above objects and other features and advantages of the present invention will become more apparent after a reading of the following detailed description when taken in conjunction with the drawings, in which: 
     FIG. 1 is a top view of a prior art leadframe; 
     FIG. 1 a  is a cross-sectional view of the prior art leadframe taken along line  1   a — 1   a  of FIG. 1; 
     FIG. 1 b  is a cross-sectional view of the prior art leadframe taken along line  1   b — 1   b  of FIG. 1; 
     FIG. 1 c  is a cross-sectional view of the prior art leadframe taken along line  1   c — 1   c  of FIG. 1; 
     FIG. 2 is a bottom plan view of a prior art top mold in an encapsulation process during the manufacture of a semiconductor package; 
     FIG. 2 a  is a cross-sectional view of the top mold of FIG. 2 taken along line  2   a — 2   a  of FIG. 2; 
     FIG. 2 b  is a cross-sectional view of the top mold of FIG. 2 taken along line  2   b — 2   b  of FIG. 2 a ; 
     FIG. 3 is a bottom view of the prior art top mold of FIG. 3 receiving encapsulating material during an encapsulation phase; 
     FIG. 3 a  is a cross-sectional view of the prior art top mold of FIG. 3 taken along line  3   a — 3   a  of FIG. 3; 
     FIG. 3 b  is a cross-sectional view of the prior art top mold of FIG. 3 taken along line  3   b — 3   b  of FIG. 3; 
     FIG. 3 c  is a cross-sectional view of the prior art top mold of FIG. 3 taken along line  3   c — 3   c  of FIG. 3; 
     FIG. 4 a  is a cross-sectional view of prior art encapsulated semiconductor package encapsulated by the method shown in FIGS.  3 — 3   c;    
     FIG. 4 b  is a cross-sectional view of prior art encapsulated semiconductor package encapsulated by the method shown in FIGS. 3-3 c;    
     FIG. 5 is a top view of a leadframe of the invention; 
     FIG. 5 a  is a cross-sectional view of the leadframe of FIG. 5 taken along line  5   a — 5   a  of FIG. 5; 
     FIG. 5 b  is a cross-sectional view of the leadframe of FIG. 5 taken along line  5   b — 5   b  of FIG. 5; 
     FIG. 6 is a bottom view of a top mold of an embodiment of the present invention used in an encapsulation process during the manufacture of a semiconductor package; 
     FIG. 6 a  is a cross sectional view of the top mold of FIG. 6 taken along line  6   a — 6   a  of FIG. 6; 
     FIG. 6 b  is a cross-sectional view of the top mold of FIG. 6 taken along line  6   b — 6   b  of FIG. 6 a;    
     FIG. 7 is a partial cross-sectional view of the leadframe of FIG. 5 being clamped by the top mold of FIG. 6 during an encapsulation process; 
     FIG. 7 a  is a cross-sectional view of the leadframe and top mold of FIG. 7 taken along line  7   a — 7   a  of FIG.  7  and of a bottom mold; 
     FIG. 7 b  is a cross-sectional view of the leadframe and top mold of FIG. 7 taken along line  7   b — 7   b  of FIG. 7; 
     FIG. 8 is a cross-section view of an encapsulated semiconductor package of the invention undergoing singulation; 
     FIG. 9 is a top view of an alternative embodiment leadframe of the present invention; 
     FIG. 10 is a bottom view of an alternative embodiment top mold of the present invention; 
     FIG. 10 a  is a cross-sectional view of the top mold of FIG. 10; 
     FIG. 11 is a partial cross-sectional view of the leadframe of FIG. 9 being clamped by the top mold of FIG. 10 during an encapsulation process; and 
     FIG. 11 a  is a cross-sectional view of the leadframe and top mold of FIG. 11 taken along line  11   a — 11   a  of FIG.  11  and of a bottom mold. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring first to FIG. 1, there is shown is a prior art leadframe  20  that has a plate type metal frame body  22 . Although only a single leadframe  20  is shown, many leadframes may be formed in a larger frame body in a matrix form, e.g. the frame body described in U.S. patent application Ser. No. 09/176,614 which is commonly owned by assignee and which is hereby incorporated by reference. However, other frame body arrangements may be used. By way of example only, frame body  22  is typically a small wafer of metal used in semiconductor package that may have a size on the order of 1×1 mm to 10×10 mm. However, these dimensions are provided as examples only and other dimensions may be used. Portions of frame body  22  are removed from the frame body  22  to create a plurality of voids therein. For example, the prior art leadframe  20  has a plurality of inner voids  24 , which define internal leads  26 . Leadframe  20  additionally has a plurality of outer voids  28 . Outer voids  28  define a plurality of external leads  30 . Inner voids  24  define a chip paddle  32 , which is typically square. Adjacent inner voids  24  define tie bars  34 ,  36 ,  38  and  40 , which communicate or make contact with chip paddle  32  with the portion of metal frame body  22  that is outside of inner voids  24 . The plurality of internal leads  26  are offset from and surround the perimeter of chip paddle  32 . Dam bars  42  are formed between the outer edge of inner voids  24  the inner edge of outer voids  28 . Dam bars  42  are provided to prevent molding material from flowing over the external leads  30  upon encapsulating. The dam bars  42 , external leads  30 , portions of tie bars  34  through  40  and the frame body  22  are all removed in a singulation process. Leadframe  20  has a groove  44  formed on its underside. Groove  44  can be seen in a cross section of FIG. 1, taken along line  1   a — 1   a , which is shown in FIG. 1 a . Additionally, groove  44  may be seen in FIG. 1 c , which is a cross sectional view taken along line  1   c — 1   c . Line  1   c — 1   c  cuts through tie bars  36  and  40 . Groove  44  can be seen passing beneath tie bars  36  and  40  in FIG. 1 c . FIG. 1 b shows a cross sectional view of prior art leadframe  20  taken along lines  1   b — 1   b  in FIG.  1 . Line  1   b — 1   b  passes through inner void  24  proximate tie bars  36  and  40 . 
     To form a semiconductor package, a semiconductor chip must be adhered to the leadframe  20 . To form the semiconductor package, a semiconductor chip (FIG. 4 a-c ) is mounted onto chip paddle  32 . The leadframe  20  is positioned between a top mold  47  (FIGS. 2 a ,  2   b ,  3   a-c ) and a bottom mold (not shown) where the semiconductor chip  45  is encapsulated by an encapsulating material  46 . Top mold  47  is designed to clamp onto dam bar  42  (FIG. 1) of the leadframe  20  and a portion of internal leads  26  (FIG. 1) with a sill  48  that protrudes down from the top mold plate  50  (FIG.  2 ). Sill  48  forms a mold gate  52  and a plurality of mold vents  54 ,  56  and  58  (FIG.  3 ). Mold gate  52  extends further outwardly than do mold vents  54 ,  56  and  58 . Sill  48  surrounds a cavity  60  (FIGS. 2 and 2 a ) in which the semiconductor chip  45  (FIGS. 3 a - 3   c ) is encapsulated with encapsulation material  46 . A cross sectional view of top mold  47 , is shown in FIG. 2 a , which is taken along lines  2   a — 2   a  of FIG. 2. A further cross sectional view shown in FIG. 2 b  is taken along line  2   b — 2   b  in FIG. 2 a  and shows the sill contact surfaces  62  of sill  48 . 
     Referring now to FIGS. 3 through 3 c , the process of encapsulating the semiconductor chip with encapsulating material  46  is shown. Sill contact surface  62  of top mold  47  is shown clamping leadframe  20 . Sill contact surface  62  is positioned to clamp dam bars  42  and metal frame body  22  (FIG.  1 ). Encapsulating material  46  is shown in FIG. 4, being introduced through mold gate  52 . Encapsulation material  46  can be thermoplastics or thermoset resins, with thermoset resins including silicones, phenolics, and epoxies. Mold vents  54 ,  56  and  58  allow discharge of gas and dregs of the encapsulation material  46 . The semiconductor chip  45  is not shown in FIG. 3, but is visible in FIGS. 3 a ,  3   b  and  3   c . FIGS. 3 a - 3   c  show semiconductor chip  45  being encapsulated by encapsulation material  46 . FIG. 3 a  is a cross sectional view taken along lines  3   a — 3   a  of FIG.  3 . In FIG. 3 a , encapsulation material  46  can be seen surrounding semiconductor chip  45  and flowing through inner voids  24  into groove  44 . FIG. 3 b  is a cross sectional view taken along lines  3   b — 3   b  of FIG.  3 . Line  3   b — 3   b  is a sectional line passing through the ends of internal voids  24 . The four-corner areas of leadframe  20  are not clamped by the sill contact surfaces  62  of the top mold  47 . The encapsulating material  46  flows through mold gate  52 , along the upper surface of the leadframe  20 , across tie bar  36  and into the cavity  60 . Gas and encapsulating material  46  escape through the mold vents  54 ,  56  and  58 . The escape path for gas and encapsulating material may be seen in FIG.  3 . 
     After completion of the encapsulation process, an encapsulated semiconductor package  68  (FIG. 4 a ) is formed. Encapsulated semiconductor package  68  is shown in a cross-sectional view similar to that seen in FIG. 3 b . Encapsulated semiconductor package  68  may also be seen in FIG. 4 b  which is a view similar to the cross-sectional view shown in FIG. 3 c . In FIGS. 4 a  and  4   b , overflow encapsulation material, or flash  70 , is visible. Reference lines S—S are provided to indicate where the singulation process acts upon the encapsulated semiconductor package  68 . The portion of flash  70  that is outside reference lines S—S may be removed when the leadframe  20  is ejected from top mold  47  and the bottom mold. Flash  70  shown in FIGS. 5 a  and  5   b  is not uniform in thickness due to various factors such as molding pressure, molding period of time, temperature, etc. The flash  70  that is present inside of reference lines S—S may cause problems during the singulation of leadframe  20 . The singulation process will be explained in greater detail below. The flash  70  is formed in the cavity  60  between the top mold  47  and the frame body  22  at locations of mold vents  54 ,  56  and  58 . Gaps  71  are visible in FIGS. 3 b  and  3   c.    
     Referring now to FIGS. 5-9, an embodiment of an exemplary an apparatus and process that embodies the present invention will now be discussed. FIG. 6 shows a leadframe  120  that has a plate type metal frame body  122 . Portions of metal frame body  122  are removed from the frame body  122 , which create a plurality of voids therein. Leadframe  120  has a plurality of inner voids  124  having elongated ends  125  as compared to prior art inner voids  24  (FIG.  1 ). Leadframe  120  additionally has a plurality of outer voids  128  formed therein. Outer voids  128  define a plurality of external leads  130 . Inner voids  124  define a chip paddle  132 , which is typically square. Adjacent inner voids  124  define tie bars  134 ,  136 ,  138  and  140 , which communicate chip paddle  132  with the portion of metal frame body  122  that is outside of inner voids  124 . The plurality of internal leads  126  are offset from and surround the perimeter of chip paddle  132 . Dam bars  142  are formed between the outer edge of inner voids  124  the inner edge of outer voids  128 . Dam bars  142  are provided to prevent a molding material from flowing over the external leads  130  upon encapsulating. Elongated ends  125  extend beyond dam bars  142  toward the corners of leadframe  120 . Leadframe  120  has a groove  144  formed on its underside. Groove  144  can be seen in the cross section in FIG. 5 b , which is a cross sectional view of FIG. 5 taken along line  5   b — 5   b . Line  5   b — 5   b  cuts through tie bars  136  and  140 . Groove  144  can be seen passing beneath tie bars  136  and  140  of FIG. 5 b . FIG. 5 a  shows a cross sectional view of leadframe  120  taken along lines  5   a — 5   a  of FIG.  5 . Line  5   a — 5   a  passes through inner void  124  proximate tie bars  136  and  140 . 
     After mounting a semiconductor chip  145  (FIGS. 7 a  and  7   b ) to chip paddle  132 , chip paddle  132  and leadframe  120  are positioned between a top mold  146  (FIG. 6) and a bottom mold  149  (FIGS. 7 a  and  7   b ) and encapsulated by an encapsulating material  147  (FIGS. 7,  7   a  and  7   b ). Encapsulating material  147  can be thermoset plastics or thermoset resins, with thermoset resins including silicones, phenolics, and epoxies. Top mold  146  is designed to clamp the dam bar  142  of the leadframe  120  and part of the internal leads  126  (FIG. 5) with a sill  148 , which protrudes down from the top mold plate  150  (FIGS.  6  and  7 ). Sill  148  forms a mold gate  152  and a plurality of mold vents  154 ,  156  and  158 . Sill  148  forms a cavity  160  (FIGS. 6 and 6 a ) in which the semiconductor chip  145 , wires, etc., are encapsulated with the encapsulation material  147 . A cross sectional view of cavity  160  can be seen in FIG. 6 a , which is taken along lines  6   a — 6   a  of FIG.  6 . 
     FIG. 6 b  is a cross-sectional view of FIG. 6 a  taken along line  6   b — 6   b  in FIG. 6 a . Sill  148  has a tetragonal shape and is chamfered in the area of the bars  134 - 140 . FIG. 6 b  shows sill contact surfaces  162  of sill  148 . 
     Referring now to FIGS. 7 through 7 b , the process of encapsulating the semiconductor chip  145  with encapsulating material  147  is shown. Leadframe  120  is shown being clamped by sill contact surface  162  of top mold  146 . Sill contact surface  162  is positioned to apply clamping pressure to dam bars  142  and metal frame body  122 . Encapsulating material  147  is shown being introduced through mold gate  152 . Mold vents  154 ,  156  and  158  allow discharge of gas and dregs of the encapsulation material  164 . The semiconductor chip  145  is not shown in FIG.  7 . However, semiconductor chip  145  is visible in FIGS. 7 a  and  7   b , where it is shown being encapsulated by encapsulation material  147 . FIG. 7 a  is a cross sectional view taken along lines  7   a — 7   a  of FIG.  7 . In FIG. 8 a , encapsulation material  147  can be seen surrounding semiconductor chip  145 . FIG.  7   b  is a cross sectional view taken along lines  7   b — 7   b  of FIG.  7 . Line  7   b — 7   b  crosses through elongated ends  125  of inner voids  124 . 
     When encapsulation material  147  enters through mold gate  152 , the encapsulation material  147  must pass below sill  148  (see FIG. 7 and 7 b ) before entering cavity  160  Gas that is to be vented is allowed to pass through small openings  163  (FIGS. 7 a  &amp;  7   b ) in mold vents  154 ,  156  and  158 . However, since the openings  163  are small and substantially restrict flow of encapsulation material  147 , the occurrence of flash is reduced. 
     In the cross sectional view of FIG. 7 a , taken along the line  7   b — 7   b  of FIG. 7, all tie bars  134 - 140  are brought into close contact with the sill contact surface  162  of sill  148 , so that the encapsulation material  147  cannot flow along the upper and bottom surfaces of the tie bars  134 - 140 . As a result, after completion of the encapsulation process, no encapsulation material flashes are found on the tie bars  134 - 140 . 
     In the cross sectional view, FIG. 7 b , taken along the line  7   b — 7   b  of FIG. 7, the encapsulating material  147  is shown flowing through elongated ends  125  of inner voids  124  under sill  148  and into cavity  160 . Likewise, molding material gas, air and molding material flash are also discharged through to the outside. Therefore, no molding material flashes remain on the upper surfaces of the tie bars  134 - 140  which are brought into close contact with the sill  148  of the top mold  146 . 
     As can be seen in FIG. 7, not only the dam bars  142 , but also the tie bars  134 ,  136 ,  138  and  140  are clamped by the sill  148  of the top mold  146 , thereby preventing any misalignment of the leadframe  120 , and any floating of the chip paddle  132 . Thus, any molding material flash on the bottom surface of the chip paddle  132  is significantly reduced. 
     After completion of the encapsulation step, an encapsulated semiconductor package  168  (FIG. 8) is formed. Encapsulated semiconductor package  168  is shown in the cross-sectional view similar to that shown in prior art FIG. 3 c . The encapsulated semiconductor package  168  is shown in FIG. 8 undergoing a singulation process. 
     As shown, the encapsulated semiconductor package  168  is undergoing the encapsulation process and is strongly clamped between the top clamp  170  and the bottom clamp  172 . The absence of the molding material flash on the leadframe  120  in the tie bar area enables the leadframe  120  to be accurately brought into close contact with the top clamp  170  and the bottom clamp  172 . Therefore, the dam bars and the tie bars all can be clamped with uniform force. In this state, a singulation tool  174  is allowed to cut the dam bars and the tie bars with uniform force. Without being damaged, the package body  176  is isolated into an individual unit. 
     FIG. 9 shows a leadframe  220  that has a plate type metal frame body  222 . Portions of metal frame body  222  are removed from the metal frame body  222 , which create a plurality of voids therein. Leadframe  220  has two large inner voids  224 . Inner voids  224  define internal leads  226 . Leadframe  220  additionally has a plurality of outer voids  228  formed therein. Outer voids  228  define a plurality of external leads  230 . Inner voids  224  define a chip paddle  232 . The two inner voids  224  define tie bars  234  and  236 , which communicate chip paddle  232  with the portion of metal frame body  222  that is outside of inner voids  224 . The plurality of internal leads  226  are offset from and surround the perimeter of chip paddle  232 . Dam bars  242  are formed between the outer edge of inner voids  224  the inner edge of outer voids  228 . Dam bars  242  are provided to prevent a molding material from flowing over the external leads  230  upon encapsulating. 
     After mounting a semiconductor chip to chip paddle  232 , chip paddle  232  and leadframe  220  are positioned between a top mold  246  (FIGS. 10 and 10 a ) and a bottom mold  249  and encapsulated by an encapsulating material  247  (FIG.  11 ). Encapsulating material  247  can be thermoplastics or thermoset resins, with thermoset resins including silicones, phenolics, and epoxies. Top mold  246  is designed to clamp the dam bar  242  of the leadframe  220  and part of the internal leads  226  with a sill  248 , which protrudes down from the top mold plate  250 . Sill  248  forms a mold gate  252  and a plurality of mold vents  254  and  256 . Sill  248  forms a cavity  260  (FIGS. 10 and 10 a ) in which the semiconductor chip, wires, etc., are encapsulated with the encapsulation material  247 . 
     Referring now to FIG. 11, the process of encapsulating a semiconductor chip  245  with encapsulating material  247  is shown. Leadframe  220  is shown being clamped by sill  248  of top mold  246 . Sill  248  is positioned to apply clamping pressure to dam bars and metal frame body. Encapsulating material  247  is shown being introduced through mold gate  252 . Mold vents  254  and  256  allow for discharge of gas, as well as dregs, of the encapsulation material  264 . The semiconductor chip  245  is not shown in FIG.  11 . However, semiconductor chip  245  is visible in FIG. 11 a , where it is shown being encapsulated by encapsulation material  247 . FIG. 11 a  is a cross sectional view taken along lines  11   a — 11   a  of FIG.  11 . In FIG. 11 a , encapsulation material  247  can be seen surrounding semiconductor chip  245 . 
     When encapsulation material  247  enters through mold gate  252 , the encapsulation material  247  must pass below sill  248  (see FIG. 11 and 11 a ) before entering cavity  260 . Gas is allowed to pass through small openings  263  (FIG. 11 a ) in mold vents  254  and  256 . Small opening  263  in mold vent  254  is visible in FIG. 11 a . However, small opening  263  substantially restricts flow of encapsulation material  247 , thereby reducing flash. 
     In the cross sectional view of FIG. 11 a , taken along the line  11   a — 11   a  of FIG. 11, the encapsulating material  247  is shown flowing through one of inner voids  224  under sill  248  and into cavity  260 . Likewise, molding material gas, air and molding material flash are also discharged through mold vent  254  to the outside. Therefore, no molding material flash remains on the upper surfaces of the tie bars  234  and  236 , which are brought into close contact with the sill  248  of the top mold  246 . 
     As can be seen in FIG. 11, not only the dam bars  242 , but also the tie bars  234  and  236  are clamped by the sill  248  of the top mold  246 , thereby preventing any misalignment of the leadframe  220 , and any floating of the chip paddle  232 . Thus, any molding material flash on the bottom surface of the chip paddle  232  is significantly reduced. 
     The various embodiments of the present invention have been described in an illustrative manner, and it is to be understood that the terminology used is intended to be in the nature of description rather than of limitation. Many modifications and variations of the present invention are possible in light of the above teachings. 
     According to the various embodiments of the present invention, as described herein, when the leadframe is subjected to singulation after the encapsulation, no flash is found in the leadframe area of the singulation, i.e. in the areas of the dam bars and tie bars. Thus, the entire leadframe can be clamped with uniform force, resulting in a smooth singulation operation and preventing the chip-out phenomenon. The sill of the top mold clamps the dam bars as well as the tie bars, so that the chip paddle is prevented from being tilted or floated by pressure of the molding material and thus, no flashes remain on the bottom surface of the chip paddle. 
     The following applications are all being filed on the same date as the present application and all are incorporated by reference as if wholly rewritten entirely herein, including any additional matter incorporated by reference therein: 
     
       
         
               
               
               
             
           
               
                   
               
               
                 Application 
                   
                 First Named 
               
               
                 Number 
                 Title of Application 
                 Inventor 
               
               
                   
               
             
             
               
                 09/687,787 
                 Thin and Heat Radiant Semi- 
                 Jae Hun Ku 
               
               
                   
                 conductor Package and Method for 
               
               
                   
                 Manufacturing 
               
               
                 09/687,532 
                 Method for Making a Semi- 
                 Tae Heon Lee 
               
               
                   
                 conductor Package Having 
               
               
                   
                 Improved Defect Testing and 
               
               
                   
                 Increased Production Yield 
               
               
                 09/687,876 
                 Near Chip Size Semiconductor 
                 Sean Timothy Crowley 
               
               
                   
                 Package 
               
               
                 09/687,536 
                 End Grid Array Semiconductor 
                 Jae Hun Ku 
               
               
                   
                 Package 
               
               
                 09/687,048 
                 Leadframe and Semiconductor 
                 Tae Heon Lee 
               
               
                   
                 Package with Improved Solder 
               
               
                   
                 Joint Strength 
               
               
                 09/687,585 
                 Semiconductor Package Having 
                 Tae Heon Lee 
               
               
                   
                 Reduced Thickness 
               
               
                 09/687,541 
                 Semiconductor Package Leadframe 
                 Young Suk Chung 
               
               
                   
                 Assembly and Method of 
               
               
                   
                 Manufacture 
               
               
                 09/687,049 
                 Improved Method for Making 
                 Young Suk Chung 
               
               
                   
                 Semiconductor Packages 
               
               
                   
               
             
          
         
       
     
     It is thus believed that the operation and construction of the present invention will be apparent from the foregoing description of the preferred embodiments. While the leadframe and semiconductor package shown are described as being preferred, it will be obvious to a person of ordinary skill in the art that various changes and modifications may be made therein without departing from the spirit and the scope of the invention, as defined in the following claims. Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred embodiments contained herein.