Abstract:
A stably operating Schmitt trigger circuit is formed by connecting in parallel a series circuit comprising a first inverter having high threshold voltage and a first switch to another series circuit comprising a second inverter having low threshold voltage and a second switch, making one ends of the series circuits an input terminal, and connecting the other ends to an output terminal through a third inverter, wherein the first switch is allowed to conduct when the electric potential at the output terminal is low and the second switch is allowed to conduct when the potential at the output terminal is high.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a Schmitt trigger circuit comprising inverters employing MOS field effect transistors (hereinafter referred to as MOS FET&#39;s). 
     2. Description of the Prior Art 
     When an input signal having slow rise and fall times is applied to a logic circuit, chattering may occur at the input stage. In order to prevent the chattering, the input signal is given to the logic circuit through the so-called Schmitt trigger circuit having hysteresis characteristics. 
     As the Schmitt trigger circuit, use has been made of the circuit shown in FIG. 1 wherein inverters 10 and 11 are connected in series between input and output terminals 13 and 14 and the output of the inverter 11 is fed back to the input of the inverter 11 through another inverter 12. The electric potential at the output point of the inverter 10 is determined by that at the output point of the inverter 12. The turn-off level V IL  at the input terminal 13 is the value at which the voltage of the output terminal 14 changes from high to low levels; it is the value which can force the output of the inverter 12 to change from low to high levels with the output of the inverter 10. Similarly, the turn-on level V IH  at the input terminal 13 is what can force the output of the inverter 12 to change from high to low levels with the output of the inverter 10. Since these values of the turn-off level V IL  and the turn-on level V IH  are different, the circuit in FIG. 1 operates as a Schmitt trigger circuit. 
     The turn-off and turn-on levels V IL  and V IH  are determined by the output impedances of the inverters 10, 12. In more detail, when the output impedance of the inverter 10 becomes smaller than that of the inverter 12, the output at the output terminal 14 turns to high or low level. Those output impedances depend on the characteristics of transistors constituting the inverters 10, 12 which have an inevitable manufacturing error. This makes it hard to control the turn-off and turn-on levels V IL  and V IH . 
     Since each of the inverters 10, 11 and 12 is of the so-called CMOS type with a circuit formed of P-channel and N-channel type MOS FETs connected in series between power supply terminals, the power consumed in the Schmitt trigger circuit is very small. If, however, the output impedance of the N-channel type MOS FET (or P-channel type MOS FET) of the inverter 10 is not small sufficient to force the output of the inverter 12 to change, the circuit in FIG. 1 will no longer operate as a Schmitt trigger circuit. If the output impedance of the inverter 12 is not large compared to that of the inverter 10, the same maloperation will occur. These phenomena may be derived from manufacturing errors during the process of manufacturing transistors or otherwise caused when the circuit is exposed to gamma (γ) rays as in the case of its use in an earth satellite. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a Schmitt trigger circuit which operates stably despite variations in characteristics of transistors. 
     The Schmitt trigger circuit in accordance with the present invention comprises an input terminal; a first inverter with its input point connected to the input terminal and having high threshold voltage; a second inverter with its input point connected to the input terminal and having low threshold voltage; and output terminal; a third inverter with its output point connected to the output terminal, a first switch connected between the output point of the first inverter and the input point of the third inverter and its control electrode connected to the output terminal, the first switch turning on in response to a low level of the output at the output terminal; and a second switch connected between the output point of the second inverter and the input point of the third inverter and its control electrode connected to the output terminal, the second switch turning on in response to a high level of the output at the output terminal. 
     In the Schmitt trigger circuit thus arranged, the turn-on level V IH  is determined by the threshold voltage of the first inverter, whereas the turn-off level V IL  is determined by the threshold voltage of the second inverter. For this reason, the turn-off and turn-on levels V IL  and V IH  do not depend on the output impedances and are readily controlled. Moreover, even if the threshold voltage of each inverter changes, the circuit will not cease to operate as a Schmitt trigger circuit. The Schmitt trigger circuit in accordance with the present invention is favorably composed of CMOS type inverters with a small power consumption, because the turn-off and turn-on levels V IL  anf V IH  may be controlled by adjusting the threshold levels of the first and second inverters. This may be possible by various methods, for example by adding a voltage attenuator in front of the first and/or second inverter, by changing the ratio of channel lengths of the P and N channel type MOS FET&#39;s or by changing the thickness of the gate insulator in the P and/or N channel type MOS FET. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     The above and further objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with accompanying drawings, wherein: 
     FIG. 1 is a block diagram of a conventional Schmitt trigger circuit; 
     FIG. 2 illustrates a Schmitt trigger circuit of a preferred embodiment according to the present invention; and 
     FIG. 3 is the circuit diagram of the inverter adoped into the embodiment of FIG. 2. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to FIG. 2 the Schmitt trigger circuit according to a preferred embodiment of the present invention comprises an inverter 1 having a high threshold voltage and an inverter 2 with a low threshold voltage. Input points of those inverters 1 and 2 are connected to an input terminal 6. The output of the inverter 1 is applied to the input point of an inverter 5 through a P channel type MOS FET 3, whereas the output point of the inverter 2 is connected to the input point of the inverter 5 through an N channel type MOS FET 4. The output of the inverter 5 is connected to an output terminal 7 and the gates of the P channel MOS FET 3 and the N channel MOS FET 4 are also connected to the output terminal 7. Each of the inverters 1, 2 and 5 is of the CMOS type as shown in FIG. 3; that is, a P channel type MOS FET 22 and an N channel type MOS FET 23 are connected in series between power source terminals V DD  and V SS , and their gates and drains being connected to a common input point 21 and a common output 24, respectively. 
     The operation of the circuit will be described hereinafter. 
     Assuming that V I  is an input signal; Vth H , the threshold voltage of the inverter 1 which has a high threshold voltage; V 1 , the output voltage of the inverter 1; Vth L , the threshold voltage of the inverter 2 which has a low threshold voltage; V 2 , the output voltage of the inverter 2; V 3 , input voltage to the output inverter 5; V 0 , the output voltage of the output inverter 5 and V DD  power supply voltage, 
     when the input signal V I  rises, 
     (1) in the range of 0&lt;V I  &lt;Vth L , the output voltage V 0  is at low level (0V) because the input voltage V 3  is allowed to have a high level due to the fact that the output voltages V 1  and V 2  are at high levels (V DD ) and the P channel type MOS FET 3 is conducting; 
     (2) in the range of Vth L  &lt;V I  &lt;Vth H , the output voltage V 0  remains at low level while the input voltage V 3  is at high level due to the fact that the output voltage V 1  is at high level and the output voltage V 2  is at low level and the P channel type MOS FET 3 is conducting while the N channel type MOS FET 4 is non-conducting; and 
     (3) in the range of Vth H  &lt;V I  &lt;V DD , the input voltage V 3  changes to have a low level due to the fact that both the output voltages V 1  and V 2  are at low levels and the N channel type MOS FET 4 is conducting while the P channel type MOS FET 3 is non-conducting, and accordingly the output voltage V 0  is inverted to the high level contrary to the cases (2) and (3). 
     When the input signal V I  falls from the value higher than Vth H  ; 
     (4) in the range of V DD  &lt;V I  &lt;Vth H , the output voltage V 0  keeps at high levels because the input voltage V 3  keeps at low levels due to the fact that the output voltages V 1  and V 2  are at low levels and the N channel type MOS FET 4 is conducting; 
     (5) in the range of Vth H  &lt;V I  &lt;Vth L , the input voltage V 3  remains at low levels due to the fact that the output voltage V 1  is at high level and the output voltage V 2  is at low level and the N channel type MOS FET 4 is conducting while the P channel type MOS FET 3 is non-conducting, and accordingly the output voltage V 0  remains at high level; and 
     (6) in the range of Vth L  &lt;V I  &lt;0, the input voltage V 3  changes to high level due to the fact that output voltages V 1  and V 2  are at high levels and the P channel type MOS FET 3 is conducting while the N channel type MOS FET 4 is non-conducting, and accordingly the output voltage V 0  changes to have a low level. 
     As explained, the circuit shown in FIG. 2 operates as a Schmitt trigger circuit having a hysteresis range Vth H  -Vth L  with the threshold voltage Vth H  of the inverter 1 as a turn-on level V IH  and the threshold voltage Vth L  ofthe inverter 2 as a turn-off level V IL . The threshold voltages Vth H  and Vth L  of the inverters 1 and 2 can freely be set, for example, by changing a ratio of the dynamic resistance between the source and the drain of the P channel type MOS FET 22 to that of the N channel type MOS FET 23 constituting the CMOS type inverter. In other words, the ratio of the channel length of the FET 22 to that of the FET 23 may be used to control the threshold voltage of the inverter. This control can be simply achieved in the manufacturing process by merely adjusting the dimensions of the source, drain and channel regions in the diffusion mask. It is very easy if compared with the prior art in which the turn-on and turn-off levels are adjusted by controlling the output impedances of the inverters 10 and 12. The threshold voltages Vth H  and Vth L  may be changed by adjusting the thicknesses of the gate insulators of the P and N channel type MOS FET&#39;s 22 and 23. The later measure, however, is not suitable where the Schmitt trigger circuit is formed in an integrated circuit. Another measure for adjusting the threshold voltages is to add an attenuator and an amplifier, respectively, in front of the inverters 1 and 2. The threshold voltages Vth L  and Vth H  may vary when the electrical characteristics of the MOS FET&#39;s constituting the inverters 1, 2 and 5 change due to an exposure to gamma rays, manufacturing errors and so on, but the Schmitt trigger circuit will never fail to function as it should do. The Schmitt trigger circuit changes its turn-on and turn-off levels only. 
     Obviously, the circuit in the above-mentioned preferred embodiment of the invention will operate in the same manner if the P channel type MOS FETs and the N channel type MOS FETs are replaced with PNP type bipolar transistors and NPN type bipolar transistors, respectively, or if the P channel type MOS FETs and the N channel type MOS FETs are mutually rearranged with a change of the power supply voltage V DD  to have negative polarity.