Abstract:
A process for forming high-precision analog transistors with a low threshold voltage roll-up and digital transistors with a high threshold voltage roll-up is disclosed. The process selectively implants the polysilicon layer that forms the gates of the analog transistors so that the doping concentration of the analog gates is greater than the doping concentration of the digital gates.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method for forming transistors and, more particularly, to a method for forming a high-precision analog transistor with a low threshold voltage roll-up and a digital transistor with a high threshold voltage roll-up. 
     2. Description of the Related Art 
     The threshold voltage of a MOS transistor is the gate voltage that defines the boundary between the conducting and non-conducting states of the transistor. Gate voltages greater than the threshold voltage cause n-channel transistors to conduct (when an appropriate drain-to-source voltage is present), while p-channel transistors become non-conductive. 
     On the other hand, gate voltages less than the threshold voltage cause n-channel transistors to stop conducting, while p-channel transistors become conductive (when an appropriate source-to-drain voltage is present). 
     For long-channel transistors (transistors having a channel length greater than 2 um), the threshold voltage of a transistor can be accurately determined. The same models that are used to predict the threshold voltages of long-channel transistors, however, overstate the threshold voltages for short-channel transistors (the long-channel models typically ignore the effect of the source and drain depletion regions). 
     Specifically, the threshold voltages of short-channel n-channel transistors are less positive than predicted, while the threshold voltages of short-channel p-channel transistors are less negative than predicted. Thus, one of the effects of a short-channel device is a reduced threshold voltage. 
     The opposite effect, an increase or roll-up in the threshold voltages, occurs with sub-micron short-channel transistors which are fabricated with current-generation CMOS processes. For digital transistors, this roll-up effect causes few, if any, problems since the precise threshold voltage of digital transistors is typically not an issue. In some cases the roll-up can even increase manufacturing yields by raising the threshold voltages of devices that would otherwise have unacceptably low threshold voltages. 
     This is not the case, however, for high-precision analog transistors. High-precision analog circuits often rely on matched pairs of analog transistors for proper operation. Although two transistors can be formed to have nearly identical dimensions, most matched pairs of analog transistors have slight differences in length which, in turn, lead to slight degradations in the performances of the matched pairs. The threshold voltage roll-up accentuates these differences which further degrades the performances of the matched pairs. 
     In the paper by Alexander Kalnitsky et al., Suppression of the Vt Roll-Up Effect in Sub-Micron NMOST, 24th European Solid State Device Research Conference, Edinbougrh, 1994, the authors report that the threshold voltage roll-up effect is strongly related to the doping concentration of the polysilicon gates of the transistors. 
     SUMMARY OF THE INVENTION 
     The present invention provides a method that reduces the threshold voltage roll-up of a high-precision analog transistor, while also allowing the threshold voltage of a digital transistor to roll up. The method, which forms a device in a semiconductor material of a first conductivity type, begins by forming a layer of gate oxide on the semiconductor material. A layer of polysilicon is then formed on the layer of gate oxide. 
     Following this, the layer of polysilicon is selectively implanted with a dopant to dope the area where the gate of the analog transistor is to be formed. Next, the layer of polysilicon is etched to form a digital gate, an analog gate, and a plurality of exposed areas on the surface of the semiconductor material. 
     After the etch, the digital gate, the analog gate, and the exposed surface areas are implanted with a dopant to dope the digital gate, further dope the analog gate, and form source and drain regions adjacent to the digital gate and the analog gate. 
     A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principals of the invention are utilized. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1-4 are a series of cross-sectional views illustrating a process flow for forming a device which has n-channel analog transistors with a low threshold voltage roll-up and digital transistors with a high threshold voltage roll-up in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIGS. 1-4 show a series of cross-sectional views that illustrate a process flow for forming a device which has n-channel analog transistors with a low threshold voltage roll-up and digital transistors with a high threshold voltage roll-up in accordance with the present invention. 
     As shown in FIG. 1, the process of the present invention begins with a conventionally formed wafer which has a p-type semiconductor material  110 . Material  110  can be implemented as a well formed in a substrate, or as a substrate. 
     In addition, the wafer also has a number of spaced-apart field oxide regions FOX which are formed in material  110 . The field oxide regions FOX can be implemented with LOCOS, trench, or other well known isolation structures. 
     From this point, a layer of sacrificial oxide  112  is formed on material  110 . After this, an analog threshold adjust mask  114  is formed and patterned on oxide layer  112  to expose the surface of oxide layer  112  where the analog n-channel transistors are to be formed. 
     Next, the exposed surface of oxide layer  112  is implanted with a dopant to adjust the threshold voltages of the to-be-formed analog n-channel transistors. Once the implant has been completed, mask  114  is removed. 
     Once mask  114  has been removed, a digital threshold mask (not shown) is formed and patterned on oxide layer  112  to expose the surface of oxide layer  112  where the digital n-channel transistors are to be formed. Next, the exposed surface of oxide layer  112  is implanted with a dopant to adjust the threshold voltages of the to-be-formed digital n-channel transistors. 
     Following the implant, the digital threshold mask and the layer of sacrificial oxide  112  are removed. Alternately, a single mask can be used to adjust the threshold voltages of both the analog and digital n-channel transistors when equivalent dopant concentrations are acceptable. Once oxide layer  112  has been removed, the surface of material  110  is cleaned. 
     Next, as shown in FIG. 2, a layer of gate oxide  116  is formed on material  110 . After this, a layer of polysilicon (poly)  118  is formed on gate oxide layer  116 . In accordance with the present invention, a poly doping mask  120  is then formed over poly layer  118  to expose the surface of poly layer  118  where the n-channel analog transistors are to be formed. 
     Following this, a n-type dopant, such as phosphorous or arsenic, is implanted into poly layer  118 . A relatively high dose of up to 4×10 16  atoms/cm 2  is utilized. Once poly layer  118  has been doped, mask  120  is removed. 
     Next, as shown in FIG. 3, a gate definition mask  122  is formed and patterned on poly layer  118 . After this, poly layer  118  is etched to form an analog gate  124 , a digital gate  126 , and exposed areas  128  on the surface of material  110 . Once the etch has been completed, gate definition mask  122  is removed. 
     After this, as shown in FIG. 4, gates  124  and  126  and the exposed areas  128  are implanted with an n-type dopant to further dope analog gate  124 , dope digital gate  126  for the first time, and form lightly-doped n- source and drain regions  130  and  132 . 
     Next, a layer of isolation material (not shown) is formed over gates  124  and  126  and the exposed areas  128 . The layer of isolation material is then anisotropically etched back to form spacers  134  and smaller exposed areas  136  on the surface of semiconductor material  110 . 
     Following this, gates  124  and  126  and the exposed areas  136  are implanted with an n-type dopant to further dope analog gate  124  and digital gate  126 , and to form heavily-doped n+source and drain regions  138  and  140 . Following this, the process continues with conventional steps. 
     One of the advantages of the present invention is that by separately implanting the gates of the analog transistors, only the roll-up in the threshold voltage of the analog transistor is suppressed. The digital transistor continues to experience a threshold voltage roll-up. 
     It should be understood that various alternatives to the embodiment of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.