Abstract:
A cascade A/D converter that has shorter settling time and enables high-speed operation is provided. A cascade A/D converter comprises fundamental constituent elements cascaded in plural stages, each fundamental constituent element comprising a first comparator for inputting an analog input signal, a D/A converter for converting an output of the first comparator to an analog signal again, and a subtractor for subtracting an output of the D/A converter from the analog input signal, the fundamental constituent elements comprising: a second comparator for inputting the analog input signal every least significant bit near a transition point of the first comparator; and an arithmetic operating unit for generating upper bits based on an output of the first comparator and interpolating lower bits based on an output of the second comparator.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     This invention relates to a cascade A/D converter used for a digital measuring device such as a digital oscilloscope.  
         [0003]     2. Description of the Related Art  
         [0004]     In a conventional cascade A/D converter, fundamental constituent elements ADA are cascaded in plural stages, the fundamental constituent elements ADA having comparators ( 10   a  to  10   f ), which are first comparators for converting an analog input signal AIN to digital signals (D 7  to D 0 ), D/A converters ( 20   a  to  20   f ) for converting outputs (B 7  to B 2 ) of the comparators ( 10   a  to  10   f ) to analog signals again, and subtractors ( 30   a  to  30   f ) for subtracting outputs of the D/A converters ( 20   a  to  20   f ) from the analog input signal AIN (see, for example, Patent Document 1).  
         [0005]      FIG. 1  is a structural view showing the conventional cascade A/D converter.  
         [0006]     In  FIG. 1 , a non-inverting input of the comparator  10   a  is connected to the analog input signal AIN, and an inverting input of the comparator  10   a  is connected to a comparative voltage  0 . The output B 7  of the comparator  10   a  is connected to an error correcting circuit  110 .  
         [0007]     An input of the D/A converter  20   a  is connected to the output B 7  of the comparator  10   a.    
         [0008]     Moreover, an addition input of the subtractor  30   a  is connected to the analog input signal AIN, and a subtraction input of the subtractor  30   a  is connected to the output of the D/A converter  20   a.    
         [0009]     At a comparator  9   a , its non-inverting input is connected to the analog input signal AIN, and its inverting input is connected to a voltage −1LSB having polarity opposite to the polarity of a voltage corresponding to the least significant bit LSB.  
         [0010]     Moreover, at a comparator  11   a , its non-inverting input is connected to a voltage +1LSB corresponding to the least significant bit LSB, and its inverting input is connected to the analog input signal AIN.  
         [0011]     At an AND circuit  60   a , its input is connected to the output of the comparator  9   a  and the output of the comparator  11   a , and its output W 7  is connected to the error correcting circuit  110 . The comparator  9   a , the comparator  11   a  and the AND circuit  60   a  form a window comparator  70   a.    
         [0012]     The comparator  10   a , the D/A converter  20   a , the subtractor  30   a  and the window comparator  70   a  form the first fundamental constituent element ADA.  
         [0013]     Similarly, a non-inverting input of the comparator  10   b  is connected to an output A 1  of the subtractor  30   a , and an inverting input of the comparator  10   b  is connected to a comparative voltage  0 . The output B 6  of the comparator  10   b  is connected to the error correcting circuit  110 .  
         [0014]     An input of the D/A converter  20   b  is connected to the output B 6  of the comparator  10   b.    
         [0015]     Moreover, an addition input of the subtractor  30   b  is connected to the output A 1  of the subtractor  30   a , and a subtraction input of the subtractor  30   b  is connected to the output of the D/A converter  20   b.    
         [0016]     At a comparator  9   b , its non-inverting input is connected to the output A 1  of the subtractor  30   a , and its inverting input is connected to the voltage −1LSB.  
         [0017]     Moreover, at comparator  11   b , its non-inverting input is connected to the voltage +1LSB, and its inverting input is connected to the output A 1  of the subtractor  30   a.    
         [0018]     At an AND circuit  60   b , its input is connected to the output of the comparator  9   b , the output of the comparator  11   b  and an inverted version of the output W 7 , and its output W 6  is connected to the error correcting circuit  110 . The comparator  9   b , the comparator  11   b  and the AND circuit  60   b  form a window comparator  70   b.    
         [0019]     The comparator  10   b , the D/A converter  20   b , the subtractor  30   b  and the window comparator  70   b  form the second fundamental constituent elements ADA.  
         [0020]     The first fundamental constituent element ADA and the second fundamental constituent element ADA are cascaded with each other.  
         [0021]     Similarly, the first fundamental constituent element ADA, the second fundamental constituent element ADA, the third fundamental constituent element ADA formed by the comparator  10   c , the D/A converter  20   c , the subtractor  30   c  and a window comparator  70   c , the fourth fundamental constituent element ADA formed by the comparator  10   d , the D/A converter  20   d , the subtractor  30   d  and a window comparator  70   d , the fifth fundamental constituent element ADA formed by the comparator  10   e , the D/A converter  20   e , the subtractor  30   e  and a window comparator  70   e , and the sixth fundamental constituent element ADA formed by the comparator  10   f , the D/A converter  20   f , the subtractor  30   f  and a window comparator  70   f , are cascaded.  
         [0022]     That is, in the conventional example of  FIG. 1 , the fundamental constituent elements are cascaded in six stages.  
         [0023]     A non-inverting input of the comparator  10   g  is connected to an output A 6  of the subtractor  30   f , and an inverting input of the comparator  10   g  is connected to the comparative voltage  0 . An output B 1  of the comparator  10   g  is connected to the error correcting circuit  110 .  
         [0024]     At a comparator  9   g , its non-inverting input is connected to the output A 6  of the subtractor  30   f , and its inverting input is connected of the voltage −1LSB.  
         [0025]     Moreover, at a comparator  11   g , its non-inverting input is connected to the voltage +1LSB, and its inverting input is connected to the output A 6  of the subtractor  30   f.    
         [0026]     At an AND circuit  60   g , its input is connected to the output of the comparator  9   g , the output of the comparator  11   g , an inverted version of the output W 7 , an inverted version of the output W 6 , an inverted version of the output W 5 , an inverted version of the output W 4 , an inverted version of the output W 3  and an inverted version of the output W 2 . Its output W 1  is connected to the error correcting circuit  110 .  
         [0027]     The comparator  9   g , the comparator  11   g  and the AND circuit  60   g  form a window comparator  70   g.    
         [0028]     The error correcting circuit  110  performs calculations based on the following logical expressions (1) to (8) and outputs digital signals D 7  (most significant bit MSB) to D 0  (least significant bit LSB). That is, in the conventional example of  FIG. 1 , digital signals (D 7  to D 0 ) of an 8-bit gray code are outputted. 
 
D 7 =B 7   (1) 
 
 D   6 =( B   7  xor  B   6 ) or  W   7   (2) 
 
 D   5 ={( B   6  xor  B   5 ) or  W   6 } and not ( W   7 )  (3) 
 
 D   4 ={( B   5  xor  B   4 ) or  W   5 } and not ( W   7 ) and not ( W   6 )  (4) 
 
 D   3 ={( B   4  xor  B   3 ) or  W   4 } and not ( W   7 ) and not ( W   6 ) and not ( W   5 )  (5) 
 
 D   2 ={( B   3  xor  B   2 ) or  W   3 } and not ( W   7 ) and not ( W   6 ) and not ( W   5 ) and not ( W   4 )  (6) 
 
 D   1 ={( B   2  xor  B   1 ) or  W   2 } and not ( W   7 ) and not ( W   6 ) and not ( W   5 ) and not ( W   4 ) and not ( W   3 )  (7) 
 
D 0 =W 1   (8) 
 
         [0029]     The operation in the conventional example of  FIG. 1  having the above-described structure will now be described.  
         [0030]     The comparator  10   a  compares the analog input signal AIN with the comparative voltage  0  and converts (A/D conversion) the analog input signal AIN to a digital signal with respect to the digital signal D 7  (most significant bit MSB).  
         [0031]     The D/A converter  20   a  converts the 1-bit output of the comparator  10   a  to an analog signal again. The subtractor  30   a  subtracts the output of the D/A converter  20   a  from the analog input signal AIN.  
         [0032]     Similarly, the comparator  10   b  compares the output A 1  of the subtractor  30   a  with the comparative voltage  0  and converts (A/D conversion) the analog output A 1  to a digital signal. Since the output A 1  is the result of subtracting the output of D/A converter  20   a  from the analog input signal AIN, the comparator  10   b  performs A/D conversion of the second bit from the most significant bit MSB with respect to the digital signal D 6 .  
         [0033]     Similarly, in the conventional example of  FIG. 1 , A/D conversion of each bit is performed sequentially.  
         [0034]     In this manner, in the conventional example of  FIG. 1 , digital signals (D 7  to D 0 ) of 8-bit gray codes are outputted.  
         [0035]     The window comparators ( 70   a  to  70   g ) generate mask signals to restrain occurrence of an error at a transition point from 0 to 1 and a transition point from 1 to 0 in the comparators ( 10   a  to  10   g ).  
         [0036]     Patent Document 1: JP-A-9-238077  
         [0037]     However, the conventional example of  FIG. 1  has a problem that settling takes a long time because of the many stages of fundamental constituent elements ADA. Therefore, the conventional example of  FIG. 1  has a difficulty in achievement of high-speed operation.  
       SUMMARY OF THE INVENTION  
       [0038]     It is an object of this invention to provide a cascade A/D converter that requires a shorter settling time and enables high-speed operation. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0039]      FIG. 1  is a structural view showing a conventional cascade A/D converter.  
         [0040]      FIG. 2  is a structural view showing an embodiment of this invention.  
         [0041]      FIGS. 3A  to  3 E show operating waveforms in the embodiment of  FIG. 2 .  
         [0042]      FIGS. 4A  to  4 J show operating waveforms in the embodiment of  FIG. 2 .  
         [0043]      FIGS. 5A  to  5 H show operating waveforms in the embodiment of  FIG. 2 .  
         [0044]      FIGS. 6A  to  6 H show operating waveforms in the embodiment of  FIG. 2 .  
         [0045]      FIG. 7  is a structural view showing another embodiment of this invention.  
         [0046]      FIGS. 8A  to  8 D show operating waveforms in the embodiment of  FIG. 7 .  
         [0047]      FIGS. 9A  to  9 L show operating waveforms in the embodiment of  FIG. 7 .  
         [0048]      FIGS. 10A  to  10 L show operating waveforms in the embodiment of  FIG. 7 .  
         [0049]      FIG. 11  is a structural view showing still another embodiment of this invention.  
         [0050]      FIG. 12  is an equivalent circuit diagram of a sub-A/D converter  200   a  in the embodiment of  FIG. 11  in the case where an input range is 1.375 times.  
         [0051]      FIGS. 13A  to  13 E show operating waveforms in the embodiment of  FIG. 12 .  
         [0052]      FIGS. 14A  to  14 G show operating waveforms in the case where an input range is 1.375 times in the embodiment of  FIG. 11 .  
         [0053]      FIGS. 15A  to  15 I show operating waveforms in the case where an input range is 1.375 times in the embodiment of  FIG. 11 .  
         [0054]      FIG. 16  shows differential non-linear error (DNL) based on the operating waveforms of  FIGS. 15A  to  15 I in the case where an input range is 1.375 times in the embodiment of  FIG. 11 .  
         [0055]      FIG. 17  is an equivalent circuit diagram of the sub-A/D converter  200   a  in the embodiment of  FIG. 11  in the case where an input range is 0.625 times.  
         [0056]      FIGS. 18A  to  18 E show operating waveforms in the embodiment of  FIG. 17 .  
         [0057]      FIGS. 19A  to  19 G show operating waveforms in the case where an input range is 0.625 times in the embodiment of  FIG. 11 .  
         [0058]      FIGS. 20A  to  20 I show operating waveforms in the case where an input range is 0.625 times in the embodiment of  FIG. 11 .  
         [0059]      FIG. 21  shows differential non-linear error (DNL) based on the operating waveforms of  FIGS. 20A  to  20 I in the case where an input range is 0.625 times in the embodiment of  FIG. 11 . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0060]     This invention will now be described in detail with reference to  FIG. 2 .  FIG. 2  is a structural view showing an embodiment of this invention. The same elements as those in the conventional example of  FIG. 1  are denoted by the same numerals and will not be described further in detail. An arithmetic operating unit  100  in the embodiment of  FIG. 2  is equivalent to the error correcting circuit  110  in the conventional example of  FIG. 1 .  
         [0061]     The embodiment of  FIG. 2  is characterized by the structure of comparators ( 6   a  to  9   a ,  11   a  to  14   a ,  6   b  to  9   b ,  11   b  to  14   b ,  6   c  to  9   c ,  11   c  to  14   c ,  6   d  to  9   d , and  11   d  to  14   d ), which are second comparators, and the arithmetic operating unit  100 .  
         [0062]     In  FIG. 2 , a voltage +1LSB is a voltage corresponding to the least significant bit LSB. A voltage +2LSB is a voltage twice as large as the voltage +1LSB. A voltage +3LSB is a voltage three times as large as the voltage +1LSB. A voltage +4LSB is a voltage four times as large as the voltage +1LSB. A voltage −1LSB, a voltage −2LSB, a voltage −3LSB and a voltage −4LSB are voltages having polarity opposite to the polarity of the voltage +1LSB, the voltage +2LSB, the voltage +3LSB and the voltage +4LSB, respectively.  
         [0063]     The comparator  6   a  is a comparator for multiplication by −4 of the least significant bit LSB. Its non-inverting input is connected to an analog input signal AIN, and its inverting input is connected to the voltage −4LSB. Its output is connected to an AND circuit  54   a  via a latch circuit  36   a.    
         [0064]     The comparator  7   a  is a comparator for multiplication by −3 of the least significant bit LSB. Its non-inverting input is connected to the analog input signal AIN, and its inverting input is connected to the voltage −3LSB. Its output is connected to an AND circuit  53   a  via a latch circuit  37   a.    
         [0065]     The comparator  8   a  is a comparator for multiplication by of the least significant bit LSB. Its non-inverting input is connected to the analog input signal AIN, and its inverting input is connected to the voltage −2LSB. Its output is connected to an AND circuit  52   a  via a latch circuit  38   a.    
         [0066]     The comparator  9   a  is a comparator for multiplication by −1 of the least significant bit LSB. Its non-inverting input is connected to the analog input signal AIN, and its inverting input is connected to the voltage −1LSB. Its output is connected to an AND circuit  51   a  via a latch circuit  39   a.    
         [0067]     The comparator  11   a  is a comparator for multiplication by +1 of the least significant bit LSB. Its non-inverting input is connected to the analog input signal AIN, and its inverting input is connected to the voltage +1LSB. Its output is connected to the AND circuit  51   a  via a latch circuit  41   a  and an inverting unit.  
         [0068]     The comparator  12   a  is a comparator for multiplication by +2 of the least significant bit LSB. Its non-inverting input is connected to the analog input signal AIN, and its inverting input is connected to the voltage +2LSB. Its output is connected to the AND circuit  52   a  via a latch circuit  42   a  and an inverting unit.  
         [0069]     The comparator  13   a  is a comparator for multiplication by +3 of the least significant bit LSB. Its non-inverting input is connected to the analog input signal AIN, and its inverting input is connected to the voltage +3LSB. Its output is connected to the AND circuit  53   a  via a latch circuit  43   a  and an inverting unit.  
         [0070]     The comparator  14   a  is a comparator for multiplication by +4 of the least significant bit LSB. Its non-inverting input is connected to the analog input signal AIN, and its inverting input is connected to the voltage +4LSB. Its output is connected to the AND circuit  54   a  via a latch circuit  44   a  and an inverting unit.  
         [0071]     An output W 71  of the AND circuit  51   a , an output W 72  of the AND circuit  52   a , an output W 73  of the AND circuit  53   a  and an output W 74  of the AND circuit  54   a  are connected to the arithmetic operating unit  100 .  
         [0072]     The comparators ( 6   a  to  14   a ), a D/A converter  20   a , a subtractor  30   a , the latch circuits ( 36   a  to  44   a ), the AND circuits ( 51   a  to  54   a ) and the inverting units form a first fundamental constituent element ADA.  
         [0073]     Similarly, the comparator  6   b  is a comparator for multiplication by −4 of the least significant bit LSB. Its non-inverting input is connected to an output A 1  of the subtractor  30   a , and its inverting input is connected to the voltage −4LSB. Its output is connected to an AND circuit  54   b  via a latch circuit  36   b.    
         [0074]     The comparator  7   b  is a comparator for multiplication by −3 of the least significant bit LSB. Its non-inverting input is connected to the output A 1  of the subtractor  30   a , and its inverting input is connected to the voltage −3LSB. Its output is connected to an AND circuit  53   b  via a latch circuit  37   b.    
         [0075]     The comparator  8   b  is a comparator for multiplication by −2 of the least significant bit LSB. Its non-inverting input is connected to the output A 1  of the subtractor  30   a , and its inverting input is connected to the voltage −2LSB. Its output is connected to an AND circuit  52   b  via a latch circuit  38   b.    
         [0076]     The comparator  9   b  is a comparator for multiplication by −1 of the least significant bit LSB. Its non-inverting input is connected to the output A 1  of the subtractor  30   a , and its inverting input is connected to the voltage −1LSB. Its output is connected to an AND circuit  51   b  via a latch circuit  39   b.    
         [0077]     The comparator  11   b  is a comparator for multiplication by +1 of the least significant bit LSB. Its non-inverting input is connected to the output A 1  of the subtractor  30   a , and its inverting input is connected to the voltage +1LSB. Its output is connected to the AND circuit  51   b  via a latch circuit  41   b  and an inverting unit.  
         [0078]     The comparator  12   b  is a comparator for multiplication by +2 of the least significant bit LSB. Its non-inverting input is connected to the output A 1  of the subtractor  30   a , and its inverting input is connected to the voltage +2LSB. Its output is connected to the AND circuit  52   b  via a latch circuit  42   b  and an inverting unit.  
         [0079]     The comparator  13   b  is a comparator for multiplication by +3 of the least significant bit LSB. Its non-inverting input is connected to the output A 1  of the subtractor  30   a , and its inverting input is connected to the voltage +3LSB. Its output is connected to the AND circuit  53   b  via a latch circuit  43   b  and an inverting unit.  
         [0080]     The comparator  14   b  is a comparator for multiplication by +4 of the least significant bit LSB. Its non-inverting input is connected to the output A 1  of the subtractor  30   a , and its inverting input is connected to the voltage +4LSB. Its output is connected to the AND circuit  54   b  via a latch circuit  44   b  and an inverting unit.  
         [0081]     An output W 61  of the AND circuit  51   b , an output W 62  of the AND circuit  52   b , an output W 63  of the AND circuit  53   b  and an output W 64  of the AND circuit  54   b  are connected to the arithmetic operating unit  100 .  
         [0082]     The comparators ( 6   b  to  14   b ), a D/A converter  20   b , a subtractor  30   b , the latch circuits ( 36   b  to  44   b ), the AND circuits ( 51   b  to  54   b ) and the inverting units form a second fundamental constituent element ADA.  
         [0083]     The first fundamental constituent element ADA and the second fundamental constituent element ADA are cascaded with each other.  
         [0084]     Similarly, the first fundamental constituent element ADA, the second fundamental constituent element ADA, a third fundamental constituent element ADA formed by comparators ( 6   c  to  14   c ), a D/A converter  20   c , a subtractor  30   c , latch circuits ( 36   c  to  44   c ), AND circuits ( 51   c  to  54   c ) and inverting units, and a fourth fundamental constituent element ADA formed by comparators ( 6   d  to  14   d ), a D/A converter  20   d , a subtractor  30   d , latch circuits ( 36   d  to  44   d ), AND circuits ( 51   d  to  54   d ) and inverting units, are cascaded.  
         [0085]     That is, in the embodiment of  FIG. 2 , the fundamental constituent elements are connected in four stages. On the stage subsequent to the fundamental constituent elements, the following structure is provided.  
         [0086]     A comparator  7   e  is a comparator for multiplication by −3 of the least significant bit LSB. Its non-inverting input is connected to an output A 4  of the subtractor  30   d , and its inverting input is connected to the voltage −3LSB. Its output is connected to an AND circuit  53   e  via a latch circuit  37   e.    
         [0087]     A comparator  8   e  is a comparator for multiplication by −2 of the least significant bit LSB. Its non-inverting input is connected to the output A 4  of the subtractor  30   d , and its inverting input is connected to the voltage −2LSB. Its output is connected to an AND circuit  52   e  via a latch circuit  38   e.    
         [0088]     A comparator  9   e  is a comparator for multiplication by −1 of the least significant bit LSB. Its non-inverting input is connected to the output A 4  of the subtractor  30   d , and its inverting input is connected to the voltage −1LSB. Its output is connected to an AND circuit  51   e  via a latch circuit  39   e.    
         [0089]     A comparator  11   e  is a comparator for multiplication by +1 of the least significant bit LSB. Its non-inverting input is connected to the output A 4  of the subtractor  30   d , and its inverting input is connected to the voltage +1LSB. Its output is connected to the AND circuit  51   e  via a latch circuit  41   e  and an inverting unit.  
         [0090]     A comparator  12   e  is a comparator for multiplication by +2 of the least significant bit LSB. Its non-inverting input is connected to the output A 4  of the subtractor  30   d , and its inverting input is connected to the voltage +2LSB. Its output is connected to the AND circuit  52   e  via a latch circuit  42   e  and an inverting unit.  
         [0091]     A comparator  13   e  is a comparator for multiplication by +3 of the least significant bit LSB. Its non-inverting input is connected to the output A 4  of the subtractor  30   d , and its inverting input is connected to the voltage +3LSB. Its output is connected to the AND circuit  53   e  via a latch circuit  43   e  and an inverting unit.  
         [0092]     An output W 31  of the AND circuit  51   e , an output W 32  of the AND circuit  52   e  and an output W 33  of the AND circuit  53   e  are connected to the arithmetic operating unit  100 .  
         [0093]     Moreover, the arithmetic operating unit  100  executes calculations for error correction and encoding based on the following logical expressions (9) to (16) and outputs digital signals D 7  (most significant bit MSB) to D 0  (least significant bit LSB). That is, in the embodiment of  FIG. 2 , digital signals (D 7  to D 0 ) of 8-bit gray codes are outputted. 
 
D 7 =B 7   (9) 
 
 D   6 =( B   7  xor  B   6 ) or  W   74   (10) 
 
 D   5 ={( B   6  xor  B   5 ) or  W   64 } and not ( W   74 )  (11) 
 
 D   4 ={( B   5  xor  B   4 ) or  W   54 } and not ( W   74 ) and not ( W   64 )  (12) 
 
 D   3 ={( B   4  xor  B   3 ) or  W   44 } and not ( W   74 ) and not ( W   64 ) and not ( W   54 )  (13) 
 
 D   2 =not ( W   74  or  W   64  or  W   54  or  W   44 )  (14) 
 
 D   1 =not ( W   72  or  W   62  or  W   52  or  W   42  or  W   32 )  (15) 
 
 D   0 =( W   73  or  W   63  or  W   53  or  W   43  or  W   33 ) and not ( W   71  or  W   61  or  W   51  or  W   41  or  W   31 )  (16) 
 
         [0094]     The operation in the embodiment of  FIG. 2  having the above-described structure will be described with reference to  FIGS. 3A  to  5 H.  FIGS. 3A  to  5 H show operating waveforms in the embodiment of  FIG. 2 . The horizontal axes represent the analog input signal AIN within a range from −¼ of a full scale FS (i.e., −FS/4) to +¼ of the full scale (i.e., FS/4). That is, each of the operating waveforms shown in  FIGS. 3A  to  5 H represents a half of the full scale FS of the analog input signal AIN.  
         [0095]      FIG. 3A  shows the waveform of the output B 7  of the latch circuit  40   a .  FIG. 3B  shows the waveform of the output B 6  of the latch circuit  40   b .  FIG. 3C  shows the waveform of the output B 5  of the latch circuit  40   c .  FIG. 3D  shows the waveform of the output B 4  of the latch circuit  40   d .  FIG. 3E  shows the waveform of the output B 3  of the latch circuit  40   e.    
         [0096]      FIG. 4A  shows the waveform of the outputs of the comparators ( 6   a  to  9   a  and  11   a  to  14   a ).  FIG. 4B  shows the waveform of the outputs (W 71  to W 74 ) of the AND circuits ( 51   a  to  54   a ).  FIG. 4C  shows the waveform of the outputs of the comparators ( 6   b  to  9   b  and  11   b  to  14   b ).  FIG. 4D  shows the waveform of the outputs (W 61  to W 64 ) of the AND circuits ( 51   b  to  54   b ).  
         [0097]      FIG. 4E  shows the waveform of the outputs of the comparators ( 6   c  to  9   c  and  11   c  to  14   c ).  FIG. 4F  shows the waveform of the outputs (W 51  to W 54 ) of the AND circuits ( 51   c  to  54   c ).  
         [0098]      FIG. 4G  shows the waveform of the outputs of the comparators ( 6   d  to  9   d  and  11   d  to  14   d ).  FIG. 4H  shows the waveform of the outputs (W 41  to W 44 ) of the AND circuits ( 51   d  to  54   d ).  
         [0099]      FIG. 4I  shows the waveform of the outputs of the comparators ( 7   e  to  9   e  and  11   e  to  13   e ).  FIG. 4J  shows the waveform of the outputs (W 31  to W 33 ) of the AND circuits ( 51   e  to  53   e ).  
         [0100]      FIG. 5A  shows the waveform of the digital signal D 7 .  FIG. 5B  shows the waveform of the digital signal D 6 .  FIG. 5C  shows the waveform of the digital signal D 5 .  FIG. 5D  shows the waveform of the digital signal D 4 .  FIG. 5E  shows the waveform of the digital signal D 3 .  FIG. 5F  shows the waveform of the digital signal D 2 .  FIG. 5G  shows the waveform of the digital signal D 1 .  FIG. 5H  shows the waveform of the digital signal D 0 .  
         [0101]     The waveforms shown in  FIGS. 3A  to  3 E show that the arithmetic operating unit  100  acquires the signals of the upper five bits from the outputs (B 6  to B 3 ) of the fundamental constituent elements ADA cascaded in four stages.  
         [0102]     The outputs (B 6  to B 3 ) have regions P 1  where the outputs are undefined, at transition points from 0 to 1 and transition points from 1 to 0.  
         [0103]     The waveforms shown in  FIGS. 4A and 4B  show that A/D conversion is performed every least significant bit LSB in the region from −4LSB to +4LSB near the transition point from 0 to 1 and near the transition point from 1 to 0 of the digital signal D 7 .  
         [0104]     Similarly, the waveforms shown in  FIGS. 4C and 4D  show that A/D conversion is performed every least significant bit LSB in the region from −4LSB to +4LSB near the transition point from 0 to 1 and near the transition point from 1 to 0 of the digital signal D 6 .  
         [0105]     Similarly, the waveforms shown in  FIGS. 4E and 4F  show that A/D conversion is performed every least significant bit LSB in the region from −4LSB to +4LSB near the transition point from 0 to 1 and near the transition point from 1 to 0 of the digital signal D 5 .  
         [0106]     Similarly, the waveforms shown in  FIGS. 4G and 4H  show that A/D conversion is performed every least significant bit LSB in the region from −4LSB to +4LSB near the transition point from 0 to 1 and near the transition point from 1 to 0 of the digital signal D 4 .  
         [0107]     Similarly, the waveforms shown in  FIGS. 4I and 4J  show that A/D conversion is performed every least significant bit LSB in the region from −3LSB to +3LSB near the transition point from 0 to 1 and near the transition point from 1 to 0 of the digital signal D 3 .  
         [0108]     Therefore, the comparators ( 6   a  to  9   a ,  11   a  to  14   a ,  6   b  to  9   b ,  11   b  to  14   b ,  6   c  to  9   c ,  11   c  to  14   c ,  6   d  to  9   d ,  11   d  to  14   d ,  7   e  to  9   e , and  11   e  to  13   e ) in the embodiment of  FIG. 2  perform A/D conversion of the lower three bits in such a manner as to interpolate the transition point from 0 to 1 and the transition point from 1 to 0 of the upper five bits.  
         [0109]     The arithmetic operating unit  100  interpolates the lower three bits on the basis of the outputs (W 61  to W 64 , W 51  to W 54 , W 41  to W 44 , and W 31  to W 33 ) based on the outputs of the comparators ( 6   b  to  9   b ,  11   b  to  14   b ,  6   c  to  9   c ,  11   c  to  14   c ,  6   d  to  9   d ,  11   d  to  14   d ,  7   e  to  9   e , and  11   e  to  13   e ).  
         [0110]     The outputs of the comparators ( 6   b  to  9   b ,  11   b  to  14   b ,  6   c  to  9   c ,  11   c  to  14   c ,  6   d  to  9   d ,  11   d  to  14   d ,  7   e  to  9   e , and  11   e  to  13   e ) and the outputs (W 61  to W 64 , W 51  to W 54 , W 41  to W 44 , and W 31  to W 33 ) have regions P 2  where the outputs are undefined, respectively.  
         [0111]     As described above, in the embodiment of  FIG. 2 , an 8-bit cascade A/D converter is formed in which the fundamental constituent elements ADA are cascaded in four stages. In the embodiment of  FIG. 2 , the fundamental constituent elements ADA are cascaded in four stages, whereas in the conventional example of  FIG. 1 , the fundamental constituent elements ADA are cascaded in six stages.  
         [0112]     Therefore, in the embodiment of  FIG. 2 , the settling time is reduced because of the fewer stages of the fundamental constituent elements ADA.  
         [0113]      FIGS. 6A  to  6 H show operating waveforms in the embodiment of  FIG. 2 . The horizontal axes in  FIGS. 6A  to  6 H represent the analog input signal AIN within a range from −½ of the full scale FS (i.e., −FS/2) to −⅜ of the full scale FS (i.e., −3FS/8).  
         [0114]      FIG. 6A  shows the waveform of the outputs (W 71  to W 74 ) of the AND circuits ( 51   a  to  54   a ), corresponding to  FIG. 4B .  
         [0115]      FIG. 6B  shows the waveform of the outputs (W 61  to W 64 ) of the AND circuits ( 51   b  to  54   b ), corresponding to  FIG. 4D .  
         [0116]      FIG. 6C  shows the waveform of the outputs (W 51  to W 54 ) of the AND circuits ( 51   c  to  54   c ), corresponding to  FIG. 4F .  
         [0117]      FIG. 6D  shows the waveform of the outputs (W 41  to W 44 ) of the AND circuits ( 51   d  to  54   d ), corresponding to  FIG. 4H .  
         [0118]      FIG. 6E  shows the waveform of the outputs (W 31  to W 33 ) of the AND circuits ( 51   e  to  53   e ), corresponding to  FIG. 4J .  
         [0119]      FIG. 6F  shows the waveform of the digital signal D 2 , corresponding to  FIG. 5F .  
         [0120]      FIG. 6G  shows the waveform of the digital signal D 1 , corresponding to  FIG. 5G .  
         [0121]      FIG. 6H  shows the waveform of the digital signal D 0 , corresponding to  FIG. 5H .  
         [0122]     In  FIGS. 6F  to  6 H, broken lines R represent characteristics proper to the gray codes. That is,  FIGS. 6F  to  6 H show that codes  0  to  3  cannot be acquired in the embodiment of  FIG. 2 .  
         [0123]     Specifically, in the embodiment of  FIG. 2 , there are codes that cannot be acquired at the lower end of the full scale FS and the upper end of the full scale FS. More specifically, in the embodiment of  FIG. 2 , codes  0  to  3  and codes  252  to  255  cannot be acquired.  
         [0124]     Such an embodiment as shown in  FIG. 2  has a defect that a part of the codes are missing. However, since the missing codes are limited to the very small regions at both ends, it can operate without any trouble in most applications.  
         [0125]     Therefore, in the embodiment of  FIG. 2 , the minimum number of comparators ( 6   a  to  9   a ,  11   a  to  14   a ,  6   b  to  9   b ,  11   b  to  14   b ,  6   c  to  9   c ,  11   c  to  14   c ,  6   d  to  9   d ,  11   d  to  14   d ,  7   e  to  9   e , and  11   e  to  13   e ) necessary for practical applications are arranged, thus realizing lower cost and smaller size.  
         [0126]      FIG. 7  is a structural view showing another embodiment of this invention. The same elements as those in the embodiment of  FIG. 2  are denoted by the same numerals and will not be described further in detail. An arithmetic operating unit  101  in the embodiment of  FIG. 7  is equivalent to the arithmetic operating unit  100  in the embodiment of  FIG. 2 .  
         [0127]     The embodiment of  FIG. 7  is characterized by having an auxiliary A/D converter  105 .  
         [0128]     In  FIG. 7 , the input of a non-inverting amplifier  103  and the input of an inverting amplifier  104  are connected to an analog input signal AIN.  
         [0129]     At an analog multiplexer  102 , its input A is connected to an output of the non-inverting amplifier  103 , and its input B is connected to an output of the inverting amplifier  104 . Its input SEL_A is connected to the output of a comparator  10   a.    
         [0130]     At a subtractor  30   e , its addition input is connected to an output OUT of the analog multiplexer  102 , and its subtraction input is connected to a voltage FS/2 corresponding to ½ of the full scale FS.  
         [0131]     A comparator  6   f  is a comparator for multiplication by four of the least significant bit LSB. Its non-inverting input is connected to an output of the subtractor  30   e , and its inverting input is connected to a voltage −4LSB. Its output is connected to an AND circuit  51   f  via a latch circuit  36   f.    
         [0132]     A comparator  7   f  is a comparator for multiplication by three of the least significant bit LSB. Its non-inverting input is connected to the output of the subtractor  30   e , and its inverting input is connected to a voltage −3LSB. Its output is connected to an AND circuit  53   f  via a latch circuit  37   f.    
         [0133]     A comparator  8   f  is a comparator for multiplication by two of the least significant bit LSB. Its non-inverting input is connected to the output of the subtractor  30   e , and its inverting input is connected to a voltage −2LSB. Its output is connected to an AND circuit  52   f  via a latch circuit  38   f.    
         [0134]     A comparator  9   f  is a comparator for multiplication by one of the least significant bit LSB. Its non-inverting input is connected to the output of the subtractor  30   e , and its inverting input is connected to a voltage −1LSB. Its output is connected to the AND circuit  53   f  via a latch circuit  39   f  and an inverting unit.  
         [0135]     An output W 74  is connected to the AND circuit  51   f  via an inverting unit. The output W 74  is also connected to the AND circuit  52   f  via an inverting unit. The output W 74  is also connected to the AND circuit  53   f  via an inverting unit.  
         [0136]     An output B 2  of the AND circuit  51   f , an output B 1  of the AND circuit  52   f  and an output W 11  of the AND circuit  53   f  are connected to the arithmetic operating unit  101 .  
         [0137]     The non-inverting amplifier  103 , the inverting amplifier  104 , the analog multiplexer  102 , the subtractor  30   e , the comparators ( 6   f  to  9   f ), the latch circuits ( 36   f  to  39   f ) and the AND circuits ( 51   f  to  53   f ) form the auxiliary A/D converter  105 .  
         [0138]     The auxiliary A/D converter  105  operates in parallel with a structure having fundamental constituent elements ADA cascaded in plural stages. It operates at a higher speed than the structure having fundamental constituent elements ADA cascaded in plural stages (i.e., structure equivalent to the embodiment of  FIG. 2 ).  
         [0139]     Specifically, the delay at the auxiliary A/D converter  105  is of a small value based on the non-inverting amplifier  103 , the inverting amplifier  104 , the analog multiplexer  102 , the subtractor  30   e , the comparators ( 6   f  to  9   f ), the latch circuits ( 36   f  to  39   f ) and the AND circuits ( 51   f  to  53   f ), whereas the delay in the structure having fundamental constituent elements ADA cascaded in plural stages is of a large value based on the comparators ( 10   a  to  10   e ), the D/A converters ( 20   a  to  20   d ), the subtractors ( 30   a  to  30   d ), the latch circuits ( 37   e  to  43   e ) and the AND circuits ( 51   e  to  53   e ).  
         [0140]     The arithmetic operating unit  101  executes calculation for error correction and encoding based on the following logical expressions (17) to (24) and outputs digital signals D 7  (most significant bit MSB) to D 0  (least significant bit LSB) That is, in the embodiment of  FIG. 7 , digital signals (D 7  to D 0 ) of 8-bit gray codes are outputted. 
 
D 7 =B 7   (17) 
 
 D   6 =( B   7  xor  B   6 ) or  W   74   (18) 
 
 D   5 ={( B   6  xor  B   5 ) or  W   64 } and not ( W   74 )  (19) 
 
 D   4 ={( B   5  xor  B   4 ) or  W   54 } and not ( W   74 ) and not ( W   64 )  (20) 
 
 D   3 ={( B   4  xor  B   3 ) or  W   44 } and not ( W   74 ) and not ( W   64 ) and not ( W   54 )  (21) 
 
 D   2 =not ( W   74  or  W   64  or  W   54  or  W   44 ) and not ( B   2 )  (22) 
 
 D   1 =not ( W   72  or  W   62  or  W   52  or  W   42  or  W   32 ) and not ( B   2 )  (23) 
 
 D   0 =( W   73  or  W   63  or  W   53  or  W   43  or  W   33 ) and not ( W   71  or  W   61  or  W   51  or  W   41  or  W   31 ) or  W   11   (24) 
 
         [0141]     Here, the operations of the analog multiplexer  102  and the subtractor  30   e  with reference to  FIGS. 8A  to  8 D.  FIGS. 8A  to  8 D show operating waveforms in the embodiment of  FIG. 7 . In  FIGS. 8A  to  8 D, the horizontal axes represent the analog input signal AIN within a range from −½of the full scale FS (i.e., −FS/2) to +½ of the full scale FS (i.e., FS/2).  
         [0142]      FIG. 8A  shows the waveforms of the input A of the analog multiplexer  102  and the input B of the analog multiplexer  102 .  FIG. 8B  shows the waveform of the input SEL_A of the analog multiplexer  102 .  FIG. 8C  shows the waveform of the output OUT of the analog multiplexer  102 .  FIG. 8D  shows the waveform of the output of the subtractor  30   e.    
         [0143]     As shown in  FIGS. 8A  to  8 C, when the input SEL_A is at high level, the analog multiplexer  102  outputs the value of the input A as the output OUT, and when the input SEL_A is at low level, the analog multiplexer  102  outputs the value of the input B as the output OUT.  
         [0144]     The subtractor  30   e  subtracts the voltage FS/2 from the output OUT and shifts the level of the output OUT. The output of the subtractor  30   e  is 0 when the analog input signal AIN is −FS/2, and the output of the subtractor  30   e  is 0 when the input analog signal AIN is FS/2, as shown in  FIG. 8D .  
         [0145]     Therefore, the analog multiplexer  102  switches the vicinity of the lower end of the range and the vicinity of the upper end of the range. In the embodiment of  FIG. 7 , with this structure, the number of constituent elements is reduced, and simplification, lower cost and smaller size are realized.  
         [0146]     The operation in the embodiment of  FIG. 7 , constructed as described above, will now be described with reference to  FIGS. 9A  to  9 L and  FIGS. 10A  to  10 L.  FIGS. 9A  to  9 L and  FIGS. 10A  to  10 L show operating waveforms in the embodiment of  FIG. 7 . In  FIGS. 9A  to  9 L, the horizontal axes represent the vicinity of the lower end of the analog input signal AIN within a range from −½ of the full scale FS (i.e., −FS/2) to −⅜ of the full scale FS (i.e., −3FS/8). In  FIGS. 10A  to  10 L, the horizontal axes represent the vicinity of the upper end of the analog input signal AIN within a range from +⅜ of the full scale FS (i.e., 3FS/8) to +½ of the full scale FS (i.e., FS/2).  
         [0147]      FIGS. 9A and 10A  show the waveform of the output of the subtractor  30   e , corresponding to  FIG. 8D .  FIGS. 9B and 10B  show the waveform of the output B 2  of the AND circuit  51   f .  FIGS. 9C and 10C  show the waveform of the output B 1  of the AND circuit  52   f .  FIGS. 9D and 10D  show the waveform of the output W 11  of the AND circuit  53   f.    
         [0148]      FIGS. 9E and 10E  show the waveform of the outputs (W 71  to W 74 ), corresponding to  FIG. 6A .  FIGS. 9F and 10F  show the waveform of the outputs (W 61  to W 64 ), corresponding to  FIG. 6B .  FIGS. 9G and 10G  show the waveform of the outputs (W 51  to W 54 ), corresponding to  FIG. 6C .  FIGS. 9H and 10H  show the waveform of the outputs (W 41  to W 44 ), corresponding to  FIG. 6D .  FIGS. 9I and 10I  show the waveform of the outputs (W 31  to W 33 ), corresponding to  FIG. 6E .  
         [0149]      FIGS. 9J and 10J  show the waveform of the digital signal D 2 , corresponding to  FIG. 6F .  FIGS. 9K and 10K  show the waveform of the digital signal D 1 , corresponding to  FIG. 6G .  FIGS. 9L and 10L  show the waveform of the digital signal D 0 , corresponding to  FIG. 6H .  
         [0150]     First, the operation in the vicinity of the lower end of the range in the embodiment of  FIG. 7  will be described with reference to  FIGS. 9A  to  9 L. As shown in  FIG. 9A , the output of the subtractor  30   e  is 0 when the analog input signal AIN is at a voltage −FS/2, and it decreases with the increase of the analog input signal AIN.  
         [0151]     When the analog input signal AIN increases from the voltage −FS/2 by a voltage +1LSB, the output of the subtractor  30   e  increases from 0 by a voltage −1LSB. The output of the comparator  9   f  changes from high level to low level, and the output W 11  changes from low level to high level.  
         [0152]     When the analog input signal AIN increases from the voltage −FS/2 by a voltage +2LSB, the output of the subtractor  30   e  increases from 0 by a voltage −2LSB. The output of the comparator  8   f  changes from high level to low level, and the output B 1  changes from high level to low level.  
         [0153]     When the analog input signal AIN increases from the voltage −FS/2 by a voltage +3LSB, the output of the subtractor  30   e  increases from 0 by a voltage −3LSB. The output of the comparator  7   f  changes from high level to low level, and the output W 11  changes from high level to low level.  
         [0154]     When the analog input signal AIN increase from the voltage −FS/2 by a voltage +4LSB, the output of the subtractor  30   e  increases from 0 by a voltage −4LSB. The output of the comparator  6   f  changes from high level to low level, and the output B 2  changes from high level to low level.  
         [0155]     That is, in the vicinity of the lower end of the range in the embodiment of  FIG. 7 , the comparators ( 6   f  to  9   f ) perform A/D conversion every least significant bit LSB. The arithmetic operating unit  101  in the embodiment of  FIG. 7  interpolates the lower three bits.  
         [0156]     Therefore, in the embodiment of  FIG. 7 , correct codes  252  to  255  can be acquired, as shown in  FIGS. 9J  to  9 L.  
         [0157]     Next, the operation in the vicinity of the upper end of the range in the embodiment of  FIG. 7  will be described with reference to  FIGS. 10A  to  10 L. As shown in  FIG. 10A , the output of the subtractor  30   e  is 0 when the analog input signal AIN is at a voltage FS/2, and it increases with the decrease of the analog input signal AIN.  
         [0158]     When the analog input signal AIN increases from the voltage FS/2 by a voltage −1LSB, the output of the subtractor  30   e  increases from 0 by a voltage −1LSB. The output of the comparator  9   f  changes from high level to low level, and the output W 11  changes from low level to high level.  
         [0159]     When the analog input signal AIN increases from the voltage FS/2 by a voltage −2LSB, the output of the subtractor  30   e  increases from 0 by a voltage −2LSB. The output of the comparator  8   f  changes from high level to low level, and the output B 1  changes from high level to low level.  
         [0160]     When the analog input signal AIN increases from the voltage FS/2 by a voltage −3LSB, the output of the subtractor  30   e  increases from 0 by a voltage −3LSB. The output of the comparator  7   f  changes from high level to low level, and the output W 11  changes from high level to low level.  
         [0161]     When the analog input signal AIN increase from the voltage FS/2 by a voltage −4LSB, the output of the subtractor  30   e  increases from 0 by a voltage −4LSB. The output of the comparator  6   f  changes from high level to low level, and the output B 2  changes from high level to low level.  
         [0162]     That is, in the vicinity of the upper end of the range in the embodiment of  FIG. 7 , the comparators ( 6   f  to  9   f ) perform A/D conversion every least significant bit LSB. The arithmetic operating unit  101  in the embodiment of  FIG. 7  interpolates the lower three bits.  
         [0163]     Therefore, in the embodiment of  FIG. 7 , correct codes  0  to  3  can be acquired, as shown in  FIGS. 10J  to  10 L.  
         [0164]     By the above-described operation, in the embodiment of  FIG. 7 , all the codes can be correctly acquired on the full scale FS.  
         [0165]     Meanwhile, the waveform of the output OUT and the waveform of the output of the subtractor  30   e  have a region P 4  where the outputs are undefined, respectively, near the transition point of the input SEL_A, as shown in  FIGS. 8C and 8D . The region P 4  is in the vicinity of the point where the analog input signal AIN becomes 0 and therefore in the vicinity of the switching point of the analog multiplexer  102 .  
         [0166]     In such vicinity of the region P 4 , the output W 74  of the AND circuit  54   a  is at high level, and the output B 2  of the AND circuit  51   f , the output B 1  of the AND circuit  52   f  and the output W 11  of the AND circuit  53   f  are at low level and therefore masked.  
         [0167]     That is, the auxiliary A/D converter  105  masks the outputs (B 2 , B 1  and W 11 ) in the vicinity of the switching point of the analog multiplexer  102 .  
         [0168]     The embodiment of  FIG. 7  operates normally and no malfunction occurs in the embodiment of  FIG. 7 . The AND circuit  51   f , the AND circuit  52   f  and the AND circuit  53   f  restrains malfunction based on the region P 4  where the output is undefined.  
         [0169]     While the input SEL_A of the analog multiplexer  102  is connected to the output of the comparator  10   a  in the above-described embodiment, similar effects and advantages can be achieved, for example, by connecting the input SEL_A to other signals than the output of the comparator  10   a.    
         [0170]     Specifically, in association with the embodiments of  FIG. 2  and  FIG. 7 , similar effects and advantages can be achieved by connecting the input SEL_A of the analog multiplexer  102  to the signal that switches between the vicinity of the lower end of the range and the vicinity of the upper end of the range.  
         [0171]     Moreover, while the output W 74  is connected to the AND circuits ( 51   f  to  53   f ) in the above-described embodiment, similar effects and advantages can be achieved, for example, by connecting the output W 73  to the AND circuits ( 51   f  to  53   f ).  
         [0172]     Specifically, in association with the embodiment of  FIG. 7 , similar effects and advantages can be achieved as long as the auxiliary A/D converter  105  masks the output in the vicinity of the switching point (region P 4 ) of the analog multiplexer  102 .  
         [0173]      FIG. 11  is a structural view showing still another embodiment of this invention. The same elements as those in the embodiment of  FIG. 2  are denoted by the same numerals and will not be described further in detail.  
         [0174]     The embodiment of  FIG. 11  is characterized by having a structure related to a differential non-linear error correcting circuit  300  (differential non-linear error correcting unit).  
         [0175]     In the embodiment of  FIG. 11 , comparators ( 6   a  to  14   a ) latch circuits ( 36   a  to  44   a ) and AND circuits ( 51   a  to  54   a ) are formed with structures similar to those in the embodiment of  FIG. 2 , and they form a first sub-A/D converter  200   a.    
         [0176]     Similarly, comparators ( 6   b  to  14   b ), latch circuits ( 36   b  to  44   b ) and AND circuits ( 51   b  to  54   b ) form a second sub-A/D converter  200   b . Comparators ( 6   c  to  14   c ), latch circuits ( 36   c  to  44   c ) and AND circuits ( 51   c  to  54   c ) form a third sub-A/D converter  200   c . Comparators ( 6   d  to  14   d ), latch circuits ( 36   d  to  44   d ) and AND circuits ( 51   d  to  54   d ) form a fourth sub-A/D converter  200   d.    
         [0177]     A comparator  6   e  is a comparator for multiplication by −4 of the least significant bit LSB. Its non-inverting input is connected to an output A 4  of a subtractor  30   d , and its inverting input is connected to a voltage −4LSB. Its output is connected to an AND circuit  54   e  via a latch circuit  36   e.    
         [0178]     A comparator  14   e  is a comparator for multiplication by +4 of the least significant bit LSB. Its non-inverting input is connected to the output A 4  of the subtractor  30   d , and its inverting input is connected to a voltage +4LSB. Its output is connected to the AND circuit  54   e  via a latch circuit  44   e  and an inverting unit.  
         [0179]     Comparators ( 6   a  to  14   a ), latch circuits ( 36   e  to  44   e ) and AND circuits ( 51   e  to  54   e ) form a fifth sub-A/D converter  201   e.    
         [0180]     Digital signals (D 7  to D 3 ) of upper five bits outputted from an arithmetic operating unit  100  become digital signals (G 7  to G 3 ) via flip-flops ( 70  to  74 ). The digital signal G 7  is the most significant bit MSB.  
         [0181]     A digital signal D 2  of a lower bit becomes a digital signal G 2  via a flip-flop  75  and an exclusive OR circuit  64 . A digital signal D 1  of a lower bit becomes a digital signal G 1  via a flip-flop  76 . Moreover, a digital signal D 0  of a lower bit becomes a digital signal G 0  via a flip-flop  77  and an AND circuit  65 . The digital signal G 0  is the least significant bit LSB.  
         [0182]     The differential non-linear error correcting circuit  300  inputs the digital signal D 2 , the digital signal D 1 , and an output W 34  of the AND circuit  54   e , and outputs an output EC 2  and an output EC 0 . The output EC 2  is connected to an input of the exclusive OR circuit  64 , and the output EC 0  is connected to an input of the AND circuit  65  via an inverting unit.  
         [0183]     The internal structure of the differential non-linear error correcting circuit  300  will now be described in detail.  
         [0184]     To an input of an AND circuit  60 , an inverted version of the digital signal D 2 , the digital signal D 1 , the output W 34 , and an inverted version of the output EC 2  are connected.  
         [0185]     To an input of an AND circuit  61 , the digital signal D 2 , an inverted version of the output W 34 , and an inverted version of the output EC 2  are connected.  
         [0186]     To an input of an AND circuit  63 , an output EC 21  of the AND circuit  60  and an output EC 22  of the AND circuit  61  are connected. An output EC 23  of the AND circuit  63  becomes the output EC 2  via a flip-flop  78 .  
         [0187]     Moreover, to an input of an AND circuit  62 , an inverted version of the digital signal D 2 , the digital signal D 1 , and the output W 34  are connected. An output EC 20  of the AND circuit  62  becomes the output EC 0  via a flip-flop  79 .  
         [0188]     That is, the AND circuits  60  to  62  calculate the logical products of the outputs of the comparators  6   e  and  14   e , which are second comparators, and the digital signals D 2  and D 1  of lower bits.  
         [0189]     Therefore, the outputs (EC 21 , EC 22 , EC 23 , EC 20 ) in the differential non-linear error correcting circuit  300  satisfy the following logical expressions (25) to (28). 
 
 EC   21 =not ( D   2 ) and  D   1  and  W   34  and not ( EC   2 )  (25) 
 
 EC   22 = D   2  and not ( W   34 ) and not ( EC   2 )  (26) 
 
EC 23 =EC 21  or EC 22   (27) 
 
 EC   20 =not ( D   2 ) and  D   1  and  W   34   (28) 
 
         [0190]     The digital signals (G 7  to G 0 ) satisfy the following logical expressions (29) to (36) and form 8-bit gray codes. 
 
G 7 =D 7   (29) 
 
G 6 =D 6   (30) 
 
G 5 =D 5   (31) 
 
G 4 =D 4   (32) 
 
G 3 =D 3   (33) 
 
G 2 =D 2  or EC 2 =D 2  xor EC 23   (34) 
 
G 1 =D 1   (35) 
 
 G   0 = D   0  and not ( EC   0 )= D   0  and not ( EC   20 )  (36) 
 
         [0191]     First, the operation in the case where the embodiment of  FIG. 11  is in the normal state (ideal state), that is, in the case where the A/D conversion range of the sub-A/D converter  200   a  is stable, will be described.  
         [0192]     In this case, the output EC 21  is zero (EC 21 =0), the output EC 22  is zero (EC 22 =0), the output EC 23  is zero (EC 23 =0), and the output EC 2  is zero (EC 2 =0). The output EC 20  is zero (EC 20 =0) and the output EC 0  is zero (EC 0 =0).  
         [0193]     Thus, in the case, the digital signal G 2  is the digital signal D 2  (G 2 =D 2 ) and the digital signal G 0  is the digital signal D 0  (G 0 =D 0 ).  
         [0194]     Therefore, the operation in the case where the embodiment of  FIG. 11  is in the normal state is equivalent to the operation in the case where the embodiment of  FIG. 2  is in the normal state. It is equivalent to the above-described operation in the embodiment of  FIG. 2 .  
         [0195]     Next, the operation in the case where the embodiment of  FIG. 11  is in an abnormal state (state deviated from the ideal state), that is, in the case where the A/D conversion range of the sub-A/D converter  200   a  varies, will be described.  
         [0196]     First, the operation in the embodiment of  FIG. 11 , for example, in the case where the input range of the sub-A/D converter  200   a  is 1.375 times, will be described.  FIG. 12  is an equivalent circuit diagram of the sub-A/D converter  200   a  in the embodiment of  FIG. 11  in the case where the input range is 1.375 times. The description of the other parts than the sub-A/D converter  200   a  is not given here.  
         [0197]     In this case, the sub-A/D converter  200   a  in the embodiment of  FIG. 11  is equivalently constructed as shown in the equivalent circuit diagram of  FIG. 12 . Specifically, the inverting input of the comparator  6   a  is a voltage (−4LSB×1.375) the inverting input of the comparator  7   a  is a voltage (−3LSB×1.375), the inverting input of the comparator  8   a  is a voltage (−2LSB×1.375), the inverting input of the comparator  9   a  is a voltage (−1LSB×1.375), the inverting input of the comparator  11   a  is a voltage (+1LSB×1.375), the inverting input of the comparator  12   a  is a voltage (+2LSB×1.375), the inverting input of the comparator  13   a  is a voltage (+3LSB×1.375), and the inverting input of the comparator  14   a  is a voltage (+4LSB×1.375).  
         [0198]      FIGS. 13A  to  15 I show operating waveforms in the embodiment of  FIG. 12  and operating waveforms in the case where the input range is 1.375 times in the embodiment of  FIG. 11 . In  FIGS. 13A  to  15 I, the horizontal axes represent the analog input signal AIN within a range from −{fraction (1/16)} of the full scale FS (i.e., −FS/16) to +{fraction (1/16)} of the full scale FS (i.e., FS/16).  
         [0199]      FIG. 13A  shows the waveform of the output B 7 .  FIG. 13B  shows the waveform of the output W 74 .  FIG. 13C  shows the waveform of the output W 73 .  FIG. 13D  shows the waveform of the output W 72 .  FIG. 13E  shows the waveform of the output W 71 .  
         [0200]     In  FIGS. 13B  to  13 E, broken lines R 2  represent characteristics in the case where the embodiment of  FIG. 11  is in the ideal state (ideal characteristics). The characteristics of the outputs W 74  to W 71  change because the input range in the embodiment of  FIG. 11  is enlarged.  
         [0201]      FIG. 14A  shows the waveform of the digital signal D 2 .  FIG. 14B  shows the waveform of the digital signal D 1 .  FIG. 14C  shows the waveform of the output W 34 .  FIG. 14D  shows the waveform of the output EC 21 .  FIG. 14E  shows the waveform of the output EC 22 .  FIG. 14F  shows the waveform of the output EC 2 .  FIG. 14G  shows the waveform of the output EC 0 .  
         [0202]     In  FIGS. 14A and 14B , broken lines R 3  represent characteristics in the case where the embodiment of  FIG. 11  is in the ideal state (ideal characteristics). In  FIGS. 14D and 14F , slant line parts E 1  represent characteristics that zero (0) and 1 occur alternately and evenly.  
         [0203]     The regions where the broken lines R 3  appear and the regions where the slant line parts E 1  appear correspond to each other. That is, the AND circuit  60  and the AND circuit  62  detect a shift when the sub-A/D converter  200   a  enlarges the input range.  
         [0204]     In the circuit formed by the AND circuit  60 , the AND circuit  61 , the AND circuit  63  and the flip-flop  78 , zero (0) and 1 occur alternately and evenly. When the output EC 2  becomes 1, the input of the AND circuit  60  becomes zero. Therefore, the output EC 21  and the output EC 2  have characteristics that zero (0) and 1 occur alternately and evenly.  
         [0205]      FIG. 15A  shows the waveform of the digital signal G 7 .  FIG. 15B  shows the waveform of the digital signal G 6 .  FIG. 15C  shows the waveform of the digital signal G 5 .  FIG. 15D  shows the waveform of the digital signal G 4 .  FIG. 15E  shows the waveform of the digital signal G 3 .  FIG. 15F  shows the waveform of the digital signal G 2 .  FIG. 15G  shows the waveform of the digital signal G 1 .  FIG. 15H  shows the waveform of the digital signal G 0 .  FIG. 15I  shows digital output codes C corresponding to the digital signals (G 7  to G 0 ).  
         [0206]     In  FIGS. 15G and 15H , broken lines R 4  represent characteristics in the case where the embodiment of  FIG. 11  is in the ideal state (ideal characteristics). Moreover, in  FIG. 15F , slant line parts E 2  represent characteristics that zero (0) and 1 occur alternately and evenly.  
         [0207]     In  FIG. 15I , all the digital output codes Care outputted. That is, no code is missing. The codes are arranged in order.  
         [0208]     With the above-described structure, in the embodiment of  FIG. 11 , a shift in the case where the sub-A/D converter  200   a  enlarges the input range is detected and properly corrected.  
         [0209]      FIG. 16  shows differential non-linear error (DNL) based on the operating waveforms of  FIGS. 15A  to  15 I in the case where the input range of the sub-A/D converter  200   a  is 1.375 times in the embodiment of  FIG. 11 . As shown in  FIG. 16 , the differential non-linear error is between −0.5LSB and +0.375LSB.  
         [0210]     Therefore, in the embodiment of  FIG. 11 , the differential non-linear error can be reduced. Meanwhile, in the embodiment of  FIG. 2 , the differential non-linear error (DNL) in the case where the input range of the sub-A/D converter  200   a  is 1.375 times is between −1LSB and +0.875LSB (not shown).  
         [0211]     Second, the operation in the embodiment of  FIG. 11  in the case where the input range of the sub-A/D converter  200   a  is 0.625 times will be described.  FIG. 17  is an equivalent circuit diagram of the sub-A/D converter  200   a  in the embodiment of  FIG. 11  in the case where the input range is 0.625 times. The equivalent circuit diagram of  FIG. 17  corresponds to the equivalent circuit diagram of  FIG. 12 .  
         [0212]     In this case, the sub-A/D converter  200   a  in the embodiment of  FIG. 11  is equivalently structured as shown in the equivalent circuit diagram of  FIG. 17 . Specifically, the inverting input of the comparator  6   a  is a voltage (−4LSB×0.625) the inverting input of the comparator  7   a  is a voltage (−3LSB×0.625), the inverting input of the comparator  8   a  is a voltage (−2LSB×0.625), the inverting input of the comparator  9   a  is a voltage (−1LSB×1.375), the inverting input of the comparator  11   a  is a voltage (+1LSB×0.625), the inverting input of the comparator  12   a  is a voltage (+2LSB×0.625), the inverting input of the comparator  13   a  is a voltage (+3LSB×0.625), and the inverting input of the comparator  14   a  is a voltage (+4LSB×0.625).  
         [0213]      FIGS. 18A  to  20 I show operating waveforms in the embodiment of  FIG. 17  and operating waveforms in the case where the input range is 0.625 times in the embodiment of  FIG. 11 .  FIGS. 18A  to  20 I correspond to  FIGS. 13A  to  15 I. Therefore, similar parts will not be described further in detail.  
         [0214]     In  FIGS. 18B  to  18 E, broken lines R 5  represent characteristics in the case where the embodiment of  FIG. 11  is in the ideal state (ideal characteristics). The characteristics of the outputs W 74  to W 71  change because the input range in the embodiment of  FIG. 11  is narrowed.  
         [0215]     In  FIGS. 19A and 19B , broken lines R 6  represent characteristics in the case where the embodiment of  FIG. 11  is in the ideal state (ideal characteristics). In  FIGS. 19E  and  19 F, slant line parts E 3  represent characteristics that zero (0) and 1 occur alternately and evenly.  
         [0216]     The regions where the broken lines R 6  appear and the regions where the slant line parts E 3  appear correspond to each other. That is, the AND circuit  61  detects a shift when the sub-A/D converter  200   a  narrows the input range.  
         [0217]     In the circuit formed by the AND circuit  60 , the AND circuit  61 , the AND circuit  63  and the flip-flop  78 , zero (0) and 1 occur alternately and evenly. When the output EC 2  becomes 1, the input of the AND circuit  61  becomes zero. Therefore, the output EC 22  and the output EC 2  have characteristics that zero (0) and 1 occur alternately and evenly.  
         [0218]     In  FIGS. 20G and 20H , broken lines R 7  represent characteristics in the case where the embodiment of  FIG. 11  is in the ideal state (ideal characteristics). Moreover, in  FIG. 20F , slant line parts E 4  represent characteristics that zero (0) and 1 occur alternately and evenly.  
         [0219]     In  FIG. 20I , all the digital output codes Care outputted. That is, no code is missing. The codes are arranged in order.  
         [0220]     With the above-described structure, in the embodiment of  FIG. 11 , a shift in the case where the sub-A/D converter  200   a  narrows the input range is detected and properly corrected.  
         [0221]      FIG. 21  shows differential non-linear error (DNL) based on the operating waveforms of  FIGS. 20A  to  20 I in the case where the input range of the sub-A/D converter  200   a  is 0.625 times in the embodiment of  FIG. 11 . As shown in  FIG. 21 , the differential non-linear error is between −0.375LSB and +0.75LSB.  
         [0222]     Therefore, in the embodiment of  FIG. 11 , the differential non-linear error can be reduced. Meanwhile, in the embodiment of  FIG. 2 , the differential non-linear error (DNL) in the case where the input range of the sub-A/D converter  200   a  is 0.625 times is between −0.375LSB and +1.5LSB (not shown).  
         [0223]     In the above-described embodiment, the case where the input range of the sub-A/D converter  200   a  is deviated from the ideal state is described. However, similar effects and advantages can be achieved, for example, when the sub-A/D converter  200   b  to the sub-A/D converter  200   d  and the sub-A/D converter  200   e  are deviated from the ideal state.  
         [0224]     While the 8-bit cascade A/D converter is used in the above-described embodiment, similarly preferable effects can be achieved by a cascade A/D converter other than the 8-bit cascade A/D converter.  
         [0225]     As can be understood from the above description, this invention is not limited to the above-described embodiment and includes various changes and modifications without departing from the scope of the invention.  
         [0226]     This invention has the following effects.  
         [0227]     According to this invention, since fewer stages of fundamental constituent elements ADA may be used, the settling time is reduced and a high-speed cascade A/D converter can be provided.  
         [0228]     Particularly, according to this invention, an 8-bit cascade A/D converter having fundamental constituent elements ADA cascaded in four stages can be formed.  
         [0229]     Moreover, according to this invention, a high-speed cascade A/D converter that can correctly acquire all the codes on the full scale FS can be provided.  
         [0230]     Also, according to this invention, a cascade A/D converter of lower cost and smaller size can be provided.  
         [0231]     Moreover, according to this invention, it is possible to provide a cascade A/D converter that detects and properly corrects a shift when the input range of a sub-A/D converter varies.