Abstract:
A circuit configuration for triggering a field effect transistor with a source-side load has a capacitor which is connected on one hand through a load path of the field effect transistor to a supply voltage and on the other hand both to a first charging device and to a first controllable switching device. The first switching device is connected between the capacitor and a gate terminal of the field effect transistor. A second charging device acts through a second controllable switching device to charge a gate-to-source capacitor of the field effect transistor. A comparator monitors a voltage at the gate terminal of the field effect transistor and makes the first switching device conducting when a predetermined value is reached.

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates to a circuit configuration for triggering a field effect transistor having a load path through which a load on the source side is acted upon with a supply voltage, including a capacitor connected to both a charging device and a controllable switching device, the switching device connecting one terminal of the capacitor to a gate terminal of the field effect transistor. 
     One such circuit configuration is known, for instance, from Published European Patent Application 0 405 407 A2. In such a field effect transistor constructed as a switch, the drain terminal is applied to the positive operating voltage. Since only n-channel field effect transistors can be used as driver transistors, upon turn-on an artificial elevation of the gate voltage through the drain voltage is necessary, so that the transistor will enter the low-loss R on  range. The applicable formula is U DS  &lt;U GS  -U T . In such configurations, relatively high switching speeds and the simplest possible circuit with low surface-area expense are also demanded. 
     In order to achieve an increased voltage, so-called charge pumps are known, in which the elevated operating voltage is in principle attained through the use of a switchover of a plurality of capacitors from parallel (charging phase) to serial (charge reversal or discharging phase). However, that kind of charge pump circuit is complicated and expensive and requires a relatively large surface area in integration. For that reason, the so-called bootstrap principle is often used for such applications, but it only functions dynamically. 
     Published European Patent Application 0 405 407 A1 shows that kind of bootstrap circuit. A capacitor is initially charged to the operating voltage through a supply voltage terminal and a diode, and at the instant of turn-on it is applied through a switch to the gate of a field effect transistor. The drain current then begins to flow, and the gate is &#34;pumped up&#34; by the voltage drop at the load resistor. The power transistor thus reaches the linear operating range. 
     In order to enable a calculation of the charge compensation and the gate voltage that comes to be established as stationary, it is assumed that the voltage at the capacitor is equal to the supply voltage. The following equation then applies: ##EQU1## 
     If one assumes that in the OFF state the voltage at the gate-to-source capacitor is equal to zero, then for the gate-to-source voltage U GS  in the steady-state, that is when the switch is closed, the resultant equation as a function of the gate-to-source capacitance C GS  and the capacitance C is as follows: ##EQU2## 
     This voltage is sufficient if large auxiliary capacitors can be used in discrete circuits, or if C&gt;C GS . Since the gate-to-source capacitance of integrated power transistors is generally very high, that principle can hardly be realized at reasonable surface-area expenditure. 
     SUMMARY OF THE INVENTION 
     It is accordingly an object of the invention to provide a circuit configuration for triggering a field effect transistor with a source-side load, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type. 
     With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for triggering a field effect transistor having a gate terminal, a gate-to-source capacitor, a source side load and a load path through which the load is acted upon by a supply voltage, the circuit configuration comprising a first charging device; a capacitor connected to the first charging device, the capacitor having terminals; a first controllable switching device connected between a first terminal of the capacitor and the gate terminal of the field effect transistor; a second charging device; a second controllable switching device through which the second charging device charges the gate-to-source capacitor of the field effect transistor; and a comparator monitoring a voltage at the gate terminal of the field effect transistor and conductively triggering the first switching device when a predetermined value is attained. 
     It can be seen from equation (1) that in order to minimize the surface-area expenditure, the term U GS0  C GS  C H  should be utilized. That is, prior to the actual charge compensation, the gate-to-source capacitor should have the highest possible initial charge Q GS0  &gt;0. That demand is met according to the invention by the additional charging device. If the voltage at the gate of the field effect transistor has attained a predetermined value, the switch can be activated, and the charge compensation can be effected between the bootstrap capacitor and the gate-to-source capacitor. 
     In accordance with another feature of the invention, the additional charging device is constructed as a controllable current source and a series-connected diode. 
     In accordance with a further feature of the invention, in order for the gate-to-source capacitor to be fully discharged prior to the turn-on operation, a second controllable current source is provided in addition and is triggered with the inverted trigger signal, so that in the OFF state the gate-to-source capacitor is discharged. 
     In accordance with an added feature of the invention, the comparator is particularly advantageously and simply realized through the use of a voltage-current converter with a current mirror coupled thereto. 
     In accordance with an additional feature of the invention, in order to attain a higher switching speed, a third switching device is used to impose the supply voltage on the second terminal of the bootstrap capacitor. A further advantage of such an embodiment is that the voltage jump occurs at a defined time. The third switching device is preferably triggered by the output signal of the current mirror of the comparator. 
     In accordance with yet another feature of the invention, there is provided a third controllable current source connected to the second terminal of the bootstrap capacitor for applying the capacitor to a defined reference level before the field effect transistor is turned on. 
     In accordance with a concomitant feature of the invention, there is provided a small charge pump that is not turned on until later for preventing the gates of the power transistors from discharging through residual diode currents. Static operation can also be assured through the use of this simple feature of the circuit of the invention. 
     Other features which are considered as characteristic for the invention are set forth in the appended claims. 
     Although the invention is illustrated and described herein as embodied in a circuit configuration for triggering a field effect transistor with a source-side load, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. 
     The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a basic schematic diagram of a charge regulation circuit; 
     FIG. 2 is a schematic circuit diagram of an exemplary embodiment of a circuit configuration of the invention shown in FIG. 1; and 
     FIG. 3 is a graph showing a signal course of certain voltages and currents of the circuit configuration of FIG. 2. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to the figures of the drawings in detail and first, particularly, to FIG. 1 thereof, there is seen a field effect transistor indicated by reference symbol M 1 , having a drain terminal on which a supply voltage U DD  is imposed and a source terminal that is connectedthrough a resistor R L  to ground. Reference symbol C GS  designates a gate-to-source capacitor of the power MOSFET M 1 . A series circuit including a second controllable switch S 1 , a diode D 2  and a current source I 2  is connected between the transistor M 1  and thesupply voltage terminal U DD . A second charging device is formed by thecurrent source I 2  and the diode D 2 . The controllable switch S 1  is triggered by a control signal S t . A gate terminal of the transistor M 1  is also connected through a first controllable switch S2 to a first terminal of a capacitor C H . A second terminal of the capacitor C H  is connected to the source terminal of the transistor M 1 . A further series circuit including a current source I 1  and adiode D 1  is connected between the supply voltage terminal U DD  andthe first terminal of the capacitor C H . A first charging device is formed by the current source I 1  and the diode D 1 . The controllable switch S 2  is triggered by an output signal of an operational amplifier OP connected as a comparator. An inverting input of the operational amplifier OP is connected through an auxiliary voltage source U offset  to the supply voltage terminal U DD . A noninverting input of the operational amplifier OP is connected to the gate terminal of the transistor M 1 . 
     If the switch S 1  is closed by a suitable control signal, the current source I 2  is activated, and the gate-to-source capacitor C GS  charges through the load resistor R L . Since the transistor M 1  isnot operating in the saturation range and its drain current causes a voltage drop at the load resistor R L , a maximum initial gate-to-source voltage U GS0  is lower in amount than the operating voltage U DD . In the case of the stable state after the addition of the current source I 2 , where I(C GS )=0 and where the applicable transistor characteristic curve is in the saturation range, ##EQU3##the solution being ##EQU4##Since for a finite drain current, necessarily U GS0  ≧U tn , this equation is reduced to ##EQU5##In that equation, R L  is the load resistor, β is a gain factor, and U Tn  is the threshold voltage of the MOS transistor M 1 . 
     It is not until the above-described precharging can be considered to be concluded and the gate potential is approximately equal to the operating voltage U DD , that the charge compensation is initiated, by the operational amplifier OP acting as a comparator. To that end, it is necessary to furnish a defined comparator switching point. For that purpose, a reference voltage is generated through the auxiliary voltage source U offset , and the reference voltage is somewhat smaller than the supply voltage by subtraction from the supply voltage U DD . Thus, after closure of the switch S 2 , the gate-to-source voltage is established as ##EQU6##FIG. 2 shows one exemplary embodiment of such a configuration according to the invention in further detail. Identical elements have the same reference numerals. A controllable current source I 9  is used in this case instead of the switch S 1 . The controllable current source I 9  is triggered by an output signal of an inverter INV having an input on which the control signal S t  is imposed. The switch S 2  in this case is constructed as a MOSFET transistor M 4 . In this case the second terminal of the capacitor C H  is connected on one hand through the load path of a further MOSFET M 3  to the supply voltage terminal U DD , and on the other hand through a further controllable current source I 3  to ground. The MOSFET M 3  is a third switching device. The controllable current source I 3  is triggered by the control signal S t . A further controllable current source I 4  which is connected between the gate terminal of the MOSFET M 1  and ground, is also triggered by the control signal S t . The comparator isformed by bipolar transistors T 1  -T 4 , current sources I 5  -I 8  and an output MOSFET M 2 . A voltage-current converter includes the current source I 7  and the transistor T 3 . A base terminal of the pnp transistor T 3  is connected to a gate terminal of the transistor M 1 . A collector of the transistor T 3  is connectedto ground, and an emitter thereof is connected both to a base of the pnp transistor T4 and through the current source I 7  to the supply voltageterminal U DD . An emitter of the transistor T 4  is connected through the current source I 4  to the supply voltage terminal U DD . A collector of the transistor T 4  is connected to a base anda collector of the npn transistor T 1 . An emitter of the npn transistorT 1  is connected to ground. A base of the transistor T 1  is connected to a base of the npn transistor T 2 . An emitter of the transistor T 2  is likewise connected to ground. A collector of the transistor T 2  is connected to both a gate terminal of the transistor M 2  and through the current source I6 to the supply voltage terminal U DD . A source terminal of the transistor M 2  is connected to ground, and a drain terminal thereof forms an output of the comparator. The drain terminal of the transistor M 2  is likewise connected throughthe current source I 5  to the supply voltage terminal U DD . The drain terminal of the transistor M 2  is also connected to the gate terminals of transistors M 3  and M 4 . 
     If the control signal S t  is logical &#34;1&#34;, then the gate of the transistor M 1  is discharged by the current source I 4 , and the driver is switched off. At the same time, charging of the capacitor C H  is effected through the use of the current source I 3  through the diode D 1 . In this state, both the transistor M 3  and the transistor M 4  are blocked. 
     The activation of this trigger circuit is then effected through the use of a logical &#34;0&#34; of the control signal S t . As a result, the current sources I 3  and I 4  are turned off, and the gate-to-source capacitor (which is not shown in FIG. 2) of the output transistor M 1  is charged through the load resistor R L , the current source I 9  and the diode D 2 , and the gate potential U G  rises. The output transistor M 1  is in the saturation range, and its drain current increases. 
     If the gate potential U G  is approximately two base-to-emitter voltagesunder the positive operating voltage U DD , the collector currents of the transistors T 3  and T 4  break down, and therefore the gate of the transistor M 2  can no longer be drawn downward by the current mirror that is formed by the transistors T 1 , T 2 . The transistor M 2  thereupon opens and discharges the gates of the transistors M 3  and M 4 . With the transistor M 3 , the capacitor C H , which is precharged to approximately the operating voltage, is applied with the correct sign to the operating voltage U DD . The resultant overelevation of voltage effects a charge compensation through the transistor M4 to the gate-to-source capacitor of the transistor M 1 . The gate-to-source potential U GS  (M 1 ) rises, and the power transistor enters the linear operating range. 
     Conversely to the basic illustration of FIG. 1, in which the voltage rise at the load resistor is utilized, in this circuit the voltage jump is generated by turning on the transistor M 3 . Besides the higher switching speed, this has the advantage of occurring at a defined time andthus not being able to cause premature opening of the transistor M 4  through the source control. 
     FIG. 3 shows the compensation current, that is the drain current of the transistor M 4 , the gate voltage of the power transistor M 1  and the load current, that is the drain current of the transistor M 1 , over time during the turn-on process. The transistor M 1  includes 600 parallel-connected cells, for instance. At the operating voltage, for instance of U DD  =12 V, C H  =20 pF and a load resistance, for instance, of R L  =100 Ω, the driver circuit is turned on at a time t 0 . At a time t 1 , that is about 3 μs later, the transistor M 4  is activated, and the charge pulse which is released causes an increase in the gate voltage by ΔU G , that is equal toapproximately 4 V. 
     In principle, the circuit of the invention only functions dynamically. If astatic turn-on is needed, then a small charge pump that is only turned on later can prevent the gates of the power transistors from discharging through residual diode currents.