Abstract:
The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs, and DFTs. The architecture uses a coupled dual-MAC architecture (MAC 1 ), (MAC 2 ) and attaches a dual-MAC coprocessor (MAC 3 ), (MAC 4 ) onto it in a unique way to achieve a significant increase in processing capability.

Description:
BACKGROUND OF THE INVENTION 
     1. Technical Field 
     This invention relates to digital signal processors, and has particular relation to multiply-accumulate (MAC) units. 
     2. Background Art 
     Digital Signal Processors (DSPs) are specialized types of microprocessors that are specifically tailored to execute mathematical computations very rapidly. DSPs can be found in a variety of applications including compact disk players, PC disk drives, telecommunication modem banks, and cellular telephones. 
     In the cellular telephone context, the demand for DSP computation capability continues to grow, driven by the increasing needs of applications such as GPS position location, voice recognition, low-bit rate speech and audio coding, image and video processing, and 3G cellular modem processing. To meet these processing demands, there is a need for improved digital signal processor architectures that can process computations more efficiently. 
     Considerable work has been done in these areas. Applicant Sih is also an applicant in the following applications for United States patents: 
     “Multiple Bus Architecture in a Digital Signal Processor”, Ser. No. 09/044,087, filed Mar. 18, 1998 now abandoned; 
     “Digital Signal Processor Having Multiple Access Register”, Ser. No. 09/044,088, filed Mar. 18, 1998 U.S. Pat. No. 6,496,920; 
     “Memory Efficient Instruction Storage”, Ser. No. 09/044,089, filed Mar. 18, 1998 now abandoned; 
     “Highly Parallel Variable Length Instructions for Controlling a Digital Signal Processor”, Ser. No. 09/044,104, filed Mar. 18,1998 now abandoned ; 
     “Variable Length Instruction Decoder”, Ser. No. 09/044,086, filed Mar. 18,1998 now U.S. Pat. No. 6,425,070; 
     “Digital Signal Processor with Shiftable Multiply Accumulate Unit”, Ser. No. 09/044,108, filed Mar. 18,1998 now abandoned. 
     The disclosure of these applications is incorporated herein by reference. 
     BRIEF DISCLOSURE OF THE INVENTION 
     The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs, and DFTs. The architecture uses a coupled dual-MAC architecture and attaches a dual-MAC coprocessor onto it in a unique way to achieve a significant increase in processing capability. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of the new architecture. 
     FIG. 2 shows the first configuration of the invention, in FIR Filter and Correlation Mode. 
     FIG. 3 is a logical diagram of the FIR Filter and Correlation Acceleration Mode. 
     FIG. 4 shows another configuration, the Single-Cycle Complex Multiply Mode. 
     FIG. 5 shows yet another configuration, the Single-Cycle Complex Multiply-Accumulate Mode. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a block diagram of the new architecture. In a narrow embodiment of the invention, an electronic circuit includes a register file ( 100 ) having first through third inputs (PI 1 -PI 3 ) and first through sixth outputs (PO 1 -PO 6 ). A first shifter ( 102 ) receives the first output (PO 1 ) of the register file, a first multiplier ( 104 ) receives the second (PO 2 ) and third (PO 3 ) outputs of the register file, and a second multiplier ( 106 ) receives the fourth (PO 4 ) and fifth (PO 5 ) outputs of the register file. A second shifter ( 108 ) receives the output of the first multiplier ( 104 ), and a third shifter ( 110 ) receives the output of the second multiplier ( 106 ). A rounding multiplexer ( 112 ) receives the output of the first shifter ( 102 ), and a first adder ( 114 ) receives, at a first input, the output of the second shifter ( 108 ). A first multiplexer ( 116 ) receives either a zero or the output of the third shifter ( 110 ), and applies an output to a second input of the first adder ( 114 ). A second adder ( 118 ) receives the outputs of the rounding multiplexer ( 112 ) and the first adder ( 114 ), and the output of the second adder ( 118 ) is fed back to the first input (PI 1 ) of the register file. A third adder ( 120 ) receives the outputs of the third shifter ( 110 ) and the sixth register output (PO 6 ), and the output of the third adder ( 120 ) is fed back to the second input (PI 2 ) of the register file. 
     A first input storage element ( 122 ) receives the third output (PO 3 ) of the register file. A second multiplexer ( 124 ) receives the output of the first input storage element ( 122 ) and the third output (PO 3 ) of the register file, and a third multiplexer ( 126 ) receives the second (PO 2 ) and fifth (PO 5 ) outputs of the register file. A third multiplier ( 128 ) receives the outputs of the second ( 124 ) and third ( 126 ) multiplexers, and a fourth shifter ( 130 ) receives the output of the third multiplier ( 128 ). A fourth adder ( 132 ) receives, at a first input, the output of the fourth shifter ( 130 ), and a first output storage element ( 134 ) receives the output of the fourth adder ( 132 ). The output of the first output storage element ( 134 ) is applied to a second input of the fourth adder ( 132 ). 
     A fourth multiplexer ( 136 ) receives the outputs of the first input storage element ( 122 ) and the fourth output (PO 4 ) of the register file, and a second input storage element ( 138 ) receives the output of the fourth multiplexer ( 136 ). A fifth multiplexer ( 140 ) receives the output of the second input storage element ( 138 ) and the fourth output (PO 4 ) of the register file, and a fourth multiplier ( 142 ) receives the output of the fifth multiplexer ( 140 ) and the second output (PO 2 ) of the register file. A fifth shifter ( 144 ) receives the output of the fourth multiplier ( 142 ), and a fifth adder ( 146 ) receives, at a first input, the output of the fifth shifter ( 144 ). A second output storage element ( 148 ) receives the output of the fifth adder ( 146 ). The output of the second output storage element ( 148 ) is applied to a first input of a sixth multiplexer ( 150 ). The sixth multiplexer ( 150 ) receives the output of the fourth shifter ( 130 ) at a second input, and the output of the sixth multiplexer ( 150 ) is applied to a second input of the fifth adder ( 146 ). The output of the fifth adder ( 146 ) is also fed back to the third input (PI 3 ) of the register file. The multiplexers are externally controlled. 
     The present invention, in its broadest embodiment, does not require all of the above components. Indeed, it is sufficient that the electronic circuit merely include a register file ( 100 ) including at least one input and at least four outputs (PO 2 -PO 5 ); that the electronic circuit further include first ( 104 ), second ( 106 ), third ( 128 ), and fourth ( 142 ) multipliers, each having at least two inputs; that it also include first ( 118 ), second ( 120 ), third ( 132 ), and fourth ( 146 ) adders, each adder having, as a first input, an output of the corresponding multiplier (note that these first through fourth adders are the second through fifth adders of the more detailed device); and that the electronic circuit also include means ( 124 ), ( 126 ), ( 136 ), ( 140 ) for associating the outputs of the register file with the inputs of at least some of the multipliers, and means ( 112 ), ( 116 ), ( 150 ) for associating another input of at least some of the adders with an output of another multiplier, or with an output of the register file. It is this feature which causes the multipliers, adders, and register file to operate, together, in a single clock cycle. 
     Preferably, the number of register file outputs to the multipliers is four. 
     It is also preferred that the electronic circuit further include at least one input storage element ( 128 ), ( 138 ). The input of the input storage element is connected to an output (PO 3 ) of the register file or to an output of another input storage element ( 122 ). The output of the input storage element is connected to an input of at least one of the multipliers ( 128 ), ( 142 ) or to an input of another input storage element ( 138 ). The multipliers, adders, input storage elements, and register file operate, together, in a single clock cycle. 
     While the invention will work with only a single input storage element, it is preferred that there be a plurality of input storage elements ( 122 ), ( 138 ). 
     The electronic circuit further preferably includes at least one output storage element ( 134 ), ( 148 ), connected to an output of at least one of the adders ( 132 ), ( 146 ). The multipliers, adders, output storage elements, and register file operate, together, in a single clock cycle. 
     It is preferred that the output storage element or elements ( 134 ), ( 148 ) be external to the register file ( 100 ). 
     FIG. 1 is, as noted above, a block diagram of the new architecture. The core architecture contains a coupled dual-MAC structure composed of MAC units MAC 1  and MAC 2 . MAC 1  fetches its multiplier operands from output ports PO 2  and PO 3  of the register file. The output of the multiplier ( 104 ) is passed to a shifter ( 108 ) that can shift the result left by 0, 1, 2, or 3 bits. The output of the shifter ( 108 ) is passed to an adder ( 114 ) that takes its other input from a multiplexer, MUX 1  ( 116 ), that has zero and the result of the shifted product from MAC 2  as its inputs. The output of the adder ( 114 ) is passed into a 40-bit adder ( 118 ) than can add another 40-bit operand fetched from output port PO 1  of the register file. The output of the 40-bit adder is stored into the register file via input port PI 1 . MAC 2  fetches multiplier operands from register file output ports PO 4  and PO 5 , multiplies them ( 106 ), and shifts ( 110 ) the result left by 0, 1, 2, or 3 bits. The shifter output is passed to a 40-bit adder ( 120 ) that can add an additional register file operand fetched from output port PO 6 . The shifter output is also sent to the multiplexer, MUX 1  ( 116 ) that feeds the first adder ( 114 ) in MAC 1 . The output of the 40-bit adder ( 120 ) is stored into the register file via register file input port PI 2 . 
     The coprocessor consists of multiply accumulate units MAC 3  and MAC 4  that have been connected to the core dual-MAC structure and the register file in a unique way. The inputs to MAC 3  and MAC 4  can be configured (via multiplexers MUX 2  ( 124 ), MUX 3  ( 126 ), and MUX 5  ( 140 )) to be taken from register file output ports PO 2 , PO 3 , PO 4 , PO 5 , or the delay line composed of 16-bit registers IS 1  ( 122 ) and IS 2  ( 138 ). The output of the shifted product in MAC 3  can be fed into MAC 4  via MUX 6  ( 150 ). Alternatively, the 40-bit adders in MAC 3  and MAC 4  can take an input from their local 40-bit accumulator registers OS 1  ( 134 ) and OS 2  ( 148 ), respectively. The output of MAC 4  can be written to the register file via input port PI 3 . The programmer can set up the multiplexers in the diagram to any desired configuration by executing certain program instructions, which allows the 4 MAC units to be flexibly configured to speed up several different types of computations. Several of these configurable modes are described below. 
     FIG. 2 shows the first configuration of the invention, in FIR Filter and Correlation Mode. It can be used to speed up FIR filters and correlation operations. To see why this configuration speeds up FIR filtering, we examine the equation for implementing an FIR filter:          y        (   n   )       =         ∑     N   -   1         k   =   0              h        (   k   )            x        (     n   -   k     )                                  
     If we write out the equations for four consecutive outputs, we have 
     
       
           y ( n )= h (0)×( n )+ h (1)×( n −1)+ h (2)×( n −2)+ . . . + h ( N −1)×( n−N +1) 
       
     
     
       
           y ( n +1)= h (0)×( n +1)+ h (1)×( n )+ h (2)×( n −1)+ . . . + h ( N −1)×( n−N+ 2) 
       
     
     
       
           y ( n +2)= h (0)×( n +2)+ h (1)×( n +1)+ h (2)×( n )+ . . . + h ( N −1)×( n−N+ 3) 
       
     
     
       
           y ( n +3)= h (0)×( n +3)+ h (1)×( n +2)+ h (2)×( n +1)+ . . . + h ( N −1)×( n−N+ 4) 
       
     
     To compute these four quantities simultaneously, the same coefficient h(k) is fed to all four multipliers simultaneously, while the other input is fed through a delay line to each of the multipliers. This is shown in the logical implementation diagram shown in FIG.  3 . 
     FIG. 3 is a logical diagram of the FIR Filter and Correlation Acceleration Mode. To achieve this configuration using the hardware setup shown in FIG. 2, the programmer must execute the proper instructions for the 2 core MACs to insure correct operation. The same register fetched from register file output port PO 2 , and used as an input to each of the coprocessor MAC units, must also be fetched from output port PO 4 . The programmer must also insure that the register fetched out of PO 5  is delayed by one cycle ( 152 ) using a parallel register move before being sent out on PO 3  and propagated through the hardware delay line composed of registers IS 1  ( 122 ) and IS 2  ( 138 ). The two core MACs perform accumulation by fetching and storing results to the register file ( 100 ), while the coprocessor MACs perform accumulation using their local OS 1  ( 134 ) and OS 2  ( 148 ) accumulators. This configuration can also be used to speed up correlation operations in a similar manner. 
     FIG. 4 shows another configuration, the Single-Cycle Complex Multiply Mode. To speed up FFTs and CDMA symbol demodulation, the coprocessor can also be configured to perform single-cycle complex multiplies. As the inputs to each of the core MAC units are sent to the coprocessor to perform the cross-term multiplies, the outputs of the core MAC units are added together and sent to the register file ( 100 ) via input port PI 1 , while the outputs of the coprocessor MAC units are added together and stored into the register file ( 100 ) via input port PI 3 . 
     FIG. 5 shows yet another configuration, the Single-Cycle Complex Multiply-Accumulate Mode. The complex multiply-accumulate configuration is useful for speeding up DFTs and accumulations of 32×32 multiplies. As shown in FIG. 5, the multiplier input connections are set up like the single-cycle complex multiply, but the accumulations are set up like the FIR filter acceleration mode. In the 32×32 MAC case, the core MACs are performing signed-signed and unsigned-unsigned multiplies, while the coprocessor MACs are performing signed-unsigned multiplies. 
     The use of 40-bit adders and 17×17 bit multipliers is shown. This is conventional, but any convenient number of bits may be used. 
     Industrial Application 
     This invention is capable of exploitation in industry, and can be made and used, whenever is it desired to sped up signal processing computations. The individual components of the apparatus and method shown herein, taken separate and apart from one another, may be entirely conventional, it being their combination that is claimed as the invention. 
     While various modes of apparatus and method have been described, the true spirit and scope of the invention are not limited thereto, but are limited only by the following claims and their equivalents, and such are claimed as the invention.