Abstract:
An edge-triggered, self-resetting pulse generator where a pulse is initiated by a voltage transition and is reset using feedback from the output. A voltage transition is presented at one input of a two-input NOR gate and at the input of a circuit with three inverters in series. The output from the circuit with three inverters in series connects to the second input of the two-input NOR gate. This combination creates a voltage pulse that drives a transfer FET. The transfer FET creates a voltage on a latch. The latch stores the voltage presented on the input and then drives a delay-chain with an odd number of inverters. The output of the delay-chain drives a second transfer FET that resets the latch.

Description:
FIELD OF THE INVENTION 
     This invention relates generally to electronic circuits. More particularly, this invention relates to integrated electronic circuits and pulse generators. 
     BACKGROUND OF THE INVENTION 
     One aspect of designing an integrated circuit (IC) is timing. Timing is the relationship between two or more signals with respect to time. A particular signal may need to be established at the input of a latch, before the latch is opened. This example is often called “setup time”. Another example of a timing issue is a “race” condition. A race condition may occur when a signal propagates into a memory element (e.g. a latch) before it should. The memory element in this case may close too slowly while data from another circuit transitions fast enough to be stored in the memory. The data from the other circuit should have been stored on the next clock cycle. In some cases where timing is an important issue, a voltage pulse is created that may activate a circuit for a time corresponding to the width of the pulse. The width of the pulse in time may be critical. The width of the pulse should be well defined over process variations as well as variations in temperature and voltage. An example of a circuit where a pulse may be used to control timing is a RAM (Random Access Memory) device. 
     RAM cells store digital bit values and allow those values to be read at a later time. A RAM cell also allows previous stored values to be written over by new digital bit values. A DRAM (Dynamic Random Access Memory) cell, and an SRAM (Static Random Access Memory) cell are examples of RAM cells that are used in integrated circuit designs. A SRAM cell maintains data without a refresh cycle while a DRAM cells must be refreshed periodically. SRAM cells are used in many electronic applications requiring data storage such as in an internal cache memory of a microprocessor. DRAM cells and SRAM cells may be used to create stand-alone DRAM and SRAM integrated circuits. RAM cells generally comprise one or more storage elements, and additional circuitry to allow charge to transfer from the storage elements to bitlines. Bitlines are electrically connected to a group of RAM cells and to circuitry at the ends of the bitlines for reading writing, and prechanging the bitlines. The value of the digital bit stored in the storage element is developed on the bitlines by transfering charge from a storage element to the bitlines. Transferring charge from a storage element to the bitlines causes the voltage on the bitlines to change. The rate of change in voltage between the bitlines may be relatively slow due to the number of RAM cells electrically connected to the bitlines and the current sinking capability of an individual RAM cell. In order to avoid unacceptably long delays created by waiting for a RAM cell to cause a nearly full rail-to-rail (power supply to power supply) voltage swing on the bitlines, a sense-amp may be connected to the bitlines to amplify a smaller voltage swing generated by the RAM cell. A sense-amp is capable of amplifying the signal developed on the bitlines after a relatively small signal has been developed on the bitlines by a RAM cell. The sense-amp compares the two bitlines and determines which has a larger voltage when there is only a small voltage differential between them. The sense-amp compares the voltage differential on the two bitlines after the sense amp is triggered by a delayed clock signal. The delay in the clock signal may be timed by several methods. One method is to use a signal from a selected wordline. A wordline is a signal that activates transfer gates on a row of RAM cells. After these transfer gates are activated, differential signal is developed on each bitline. Another method used to create a delay is to use an appropriate number of inverters connected in series. If the delayed clock signal goes active too early, the sense-amp may not be able to “sense” the correct digital signal. If the delay of the delayed clock signal is delayed too long, the access time of the RAM may not be optimal 
     In addition to optimally timing the start of a delayed signal to a sense-amp, it is important to limit the time that the sense-amp is activated. If a sense-amp is active for a relatively long period of time, it may cause higher peak power for circuitry with one or more sense-amps. It may also cause an increase in the offset voltage of sense-amps that are designed in SOI (Silicon on Insulator). Sense-amps designed in SOI may have transistors with different V t &#39;s (threshold voltages) due to charge accumulating on the body of these transistors. Since these transistors may have different bias conditions while the sense-amp is enabled, an offset voltage may be developed. In order to overcome an offset voltage developed by this mechanism, precharge circuitry must be active for a longer period of time or must have larger transistors. Either case is not desired in the design of RAMs. There is a need in the art for a well-timed, edge-triggered, self-resetting pulse generator. The apparatus described in this invention, an edge-triggered, self-resetting pulse generator, meets this need. 
     SUMMARY OF THE INVENTION 
     An embodiment of the invention provides an edge-triggered, self-resetting pulse generator. A negative-edge signal (a transition from a high voltage to a lower voltage) is presented to one input of a two-input NOR gate and to the input of a circuit with three inverters in series. The output of the circuit with three inverters in series is connected to the second input to the NOR gate. The combination of the circuit with three inverters and the NOR gate creates a positive pulse that drives the gate of an NFET (N-type field effect transistor). The pulse on the gate of the NFET pulls the input of a latch to ground. The latch drives, through a buffer, the output of the pulse generator to a high value. The high value is maintained until feedback from the output of the pulse generator drives the input of the latch high. The output of the pulse generator is then driven low and is held low until another negative edge signal is presented at the input of the pulse generator. The feedback path includes several delay elements in series that drive the gate of a PFET (P-type Field Effect Transistor). The PFET drives the input of the latch high when the gate of the PFET is driven low. The feedback enables the pulse generator to be self-resetting. The invention may be easily adapted to other technologies used to fabricate integrated circuits. 
     Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawing, illustrating by way of example the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic drawing of an edge-triggered, self-resetting pulse generator. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 is a schematic diagram of an edge-triggered, self-resetting pulse generator. The gates of PFET, PFT 2  and NFET, NFT 1  are connected to the input of the pulse generator, INPUT and the input of inverter, INV 1  at node  102 . The output of inverter INV 1  is connected to the input of inverter, INV 2  at node  104 . The output of inverter INV 2  is connected to the input of inverter, INV 3  at node  106 . The output of inverter INV 3  is connected to the gates of PFET, PFT 1  and NFET, NFT 2  at node  108 . The drain of NFET, NFT 1 , the drain of PFET, PFT 2 , the drain of NFET, NFT 2 , and the gate of NFET, NFT 3  are connected to node  112 . The drain of NFET, NFT 3 , the drain of PFET, PFT 3 , the drain of PFET, PFT 4 , the drain of NFET, NFT 4 , the gate of PFET PFT 5 , and the gate of NFET, NFT 5  are connected to node  114 . The drain of PFET, PFT 5 , the drain of NFET, NFT 5 , the gate of PFET, PFT 4 , the gate of NFET, NFT 4 , and in the input to inverter INV 4  are connected to node  116 . The output of inverter, INV 4  is connected to the input of inverter, INV 5  at node  118 . The output of inverter INV 5  is connected to the input of inverter INV 6  at node  120 , OUTPUT. The output of inverter INV 6  is connected to the input of inverter INV 7  at node  122 . The output of inverter INV 7  is connected to the input of inverter INV 8  at node  124 . The output of inverter INV 8  is connected to the input of inverter INV 9  at node  126 . The output of inverter INV 9  is connected to the input of inverter INV 10  at node  128 . The output of inverter INV 1 O is connected to the gate of PFET, PFT 3  at node  130 . The source of PFET, PFT 3 , the source of PFET, PFT 4 , the source of PFET, PFT 5 , and the source of PFET, PFT 1  are connected to the power supply, VDD. The sources of NFETs, NFT 1 , NFT 2 , NFT 3 , NFT 4 , and NFT 5  are connected to the power supply, GND. 
     To illustrate the operation of the pulse generator shown in FIG. 1, assume that node  102  is charged to a “high” voltage (representing a logical “1”). Node  102  should be charged to a high voltage when the circuit containing the pulse generator is powered up. This assures the pulse generator will not miss the first rising edge on node  102 . In a steady-state condition with node  102  charged high, node  104  is charged to a “low” voltage (representing a logical “0”), node  106  is high, and node  108  is low. Since node  108  is low and node  102  is high, node  110  is charged high. Since node  102  is high, NFET (N-type Field Effect Transistor), NFT 1  pulls node  112  to a low voltage. Because node  112  is low, NFET NFT 3  is “off” and does not actively drive node  114 , the input to a latch,  132 . The latch,  132 , contains NFETs NFT 4  and NFT 5  and PFETs (P-type Field Effect Transistor) PFT 4  and PFT 5 . 
     Node  114  will be charged to a high voltage at steady-state after power-up. To understand why this is so, assume that node  114  is charged low. If node  114  is low, node  116  must be high, node  118  must be low, node  120  must be high, node  122  must be low, node  124  must be high, node  126  must be low, node  128  must be high, and node  130  must be low. Because node  130  is low, it activates PFET, PFT 3  and PFT 3  charges node  114  high. When node  114  changes from a low to high voltage, node  116  must now be low, node  118  must be high, node  120  must be low, node  122  must be high, node  124  must be low, node  126  must be high, node  128  must be low, and node  130  must be high. Because node  130  is high, PFET, PFT 3  is “off” and node  114  remains at a high voltage. The steady-state voltage of node  114  is latched at a high value and remains high until the gate of NFET, NFT 3 , node  112  is driven to high voltage and discharges node  114  to a low voltage. 
     After reaching a steady-state condition, where node  114  and node  102  are high, the pulse generator is ready to create an edge-triggered, self-resetting pulse. A negative-going voltage transition (i.e. a transition from a high voltage to a low voltage) from another circuit drives node  102  low. Driving node  102  to a low voltage, turns PFET, PFT 2  “on”. Since PFETs PFT 1  and PFT 2  are “on” node  112  is charged to a high value. Driving node  112  a high value, turns NFET, NFT 3  “on”. NFET, NFT 3 , then pulls node  114  low. A low voltage is then latched into latch  132 . 
     The signal presented on node  102  propagates through three inverters, INV 1 , INV 2 , and INV 3 , and presents a high voltage on node  108 . Because node  108  is a high voltage, NFET, NFT 2  discharges node  112  to a low voltage. A low voltage on node  112  disables NFET, NFT 3 . NFET, NFT 3  is no longer on and doesn&#39;t change the value of node  114 . Node  114  remains latched at a low voltage. The signal on node  114  drives through latch  132 , inverter INV 4 , and inverter INV 5  presenting a high voltage on node  120 , OUTPUT. In addition to driving the OUTPUT, node  120  feeds back to the latch,  132 , through inverters INV 6 , INV 7 , INV 8 , INV 9 , INV 10 , and PFET, PFT 3 . The positive-going voltage transition (i.e. a low voltage going to a high voltage) on node  120  marks the start of the pulse created by the pulse generator. 
     A high voltage on the OUTPUT, node  120 , results in a low voltage on the gate of PFET, PFT 3 . A low voltage on the gate of PFET, PFT 3  turns on PFET, PFT 3  which then “flips” the latch,  132  connected to node  114  from a low voltage to a high voltage. The latch,  132  then drives inverters INV 4  and INV 5 , resetting node  120  low. Resetting the pulse-generator is independent of the input voltage on node  102 . The time between node  120  going high to node  120  going low is approximately the pulse width of the pulse created by the pulse generator. The width of the pulse is determined by the delay-time a signal takes to propagate through the feedback path that includes inverters, INV 6 , INV 7 , INV 8 , INV 9 , INV 1 O, PFET, PFT 3 , latch  132 , inverter INV 4 , and inverter, INV 5 . The width of the pulse may be adjusted by adding or deleting inverters, or changing the drive strength of the inverters. The pulse-width is adjusted to meet the timing needs of a particular situation and may be determined by using an available FET-level simulator. 
     When node  102  is driven from a low voltage to a high voltage, node  114  and the feedback path described above are unaffected electrically. When another circuit drives the input, node  102 , of the pulse generator high, FFET, PFT 2  is turned “off”. The signal on node  102  propagates through inverters, INV 1 , INV 2 , and INV 3 , and drives node  108  low. A low voltage on the gate of PFET, PFT 1 , turns PFET, PFT 1  on and charges node  110  high. After node  110  is charged high, the pulse-generator is ready to create another pulse. Another pulse may be created by driving the input of the pulse generator, node  102 , to a low voltage. 
     The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.