Abstract:
A circuit for maintaining proper sampling timing in a data modem wherein main channel equalizer error is correlated with a derivative channel signal to drive a clock correction signal. The derivative channel signal is derived from an equalizer using fewer coefficients than required to derive the main channel equalized signal, and calculation of the equalized derivative and clock correction signal is performed only once every other Baud.

Description:
BACKGROUND OF THE INVENTION 
     The subject invention relates to data communication apparatus and, more particularly, to an improved circuit for adjusting the timing of a sampling clock typically used to recover data in the receiver of a data modem. Precise adjustment of the sampling clock is essential to optimum recovery of data. 
     In the prior art, it has been suggested to derive a clock correction signal by correlating so-called main channel error signals and derivative channel signals. The derivative channel signal is derived by differentiating the main channel (received) signal. According to this suggestion, the derivative channel signals must be determined every baud interval and must be equalized by a second equalizer identical to the equalizer employed to equalize the main channel signal. Furthermore, the technique assumes that the sampling clock has already been set to near the correct sampling point. While theoretically interesting, this prior art technique has not appeared practically implementable because of the complexity involved, such as in providing a second equalizer identical to that utilized to equalize the received signal. The prior art technique proves particularly undesirable in modems employing microprocessor techniques because of the excessive number of operations required, which waste valuable microprocessor computation power. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the invention to provide an improved technique for properly adjusting the sampling point of a sampling clock employed in a data modem. 
     It is a further object of the invention to provide a practically implementable sampling clock correction circuit which employs correlation of a main channel error signal and a second channel signal. 
     It is yet another object of the invention to provide such a sampling clock correction circuit implementable in a microprocessor modem design. 
     According to the subject invention, the number of operations necessary to perform sampling clock correcting functions is dramatically reduced by the discovery that it is not necessary to completely equalize the second channel signal, and that the equalized second signal need not be determined every baud interval. Furthermore, the subject invention employs an initial phase estimate based on the signal envelope to initially estimate the positioning of the sampling clock and establishes that such an estimate is sufficient to enable employment of the precise adjustment technique employed. This initial estimate proves very important in that otherwise very poor system performance may result. Employment of a second order phase lock loop to compensate for frequency offset provides a further improvement according to the invention. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a portion of a main channel distortion removing apparatus including a main channel equalizer according to the preferred embodiment of the invention. 
     FIG. 2 is a schematic diagram of the remainder of the apparatus of FIG. 1. 
     FIG. 3 is a schematic diagram of a second channel distortion removing apparatus including a second channel equalizer according to the preferred embodiment. 
     FIG. 4 is a schematic diagram of correlation and phase lock structure for producing a timing correction signal according to the preferred embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the preferred embodiment of the invention, a main channel equalizer illustrated in FIG. 1 and FIG. 2 is employed to generate main channel error signals EX n  and EY n . The main channel equalizer structure of FIG. 1 and FIG. 2 is well known in the art, and is illustrated in brief schematic form. 
     Input samples X n+K  and Y n+K  of the main channel received signal, having a phase quadrature relationship, are employed. Initially it is necessary to set the sampling point near the appropriate point in order to enable proper operation of the preferred embodiment. Such initial setting of the sampling clock may be achieved by known envelope recovery methods or by the preferred technique disclosed in the copending application of the inventors U.S. Ser. No. 900,265, entitled Fast Learn Digital Adaptive Equalizer, filed Apr. 26, 1978 and assigned to Racal-Milgo, Inc., herein incorporated by reference. Once the timing of the sampling clock has been initially set, the preferred embodiment will proceed to precisely locate the sampling time in order to optimize data recovery. 
     The equalizer of FIG. 1 includes an in-phase channel for the X n+K  samples, and a quadrature phase channel for the Y n+K  samples. The samples X n+K  are stored in delay elements 11 and the samples Y n+K  are stored in delay elements 13. The inphase channel samples X n+K  are multiplied by respective constants CP -K  . . . CP m  and summed in a summer 15. The samples Y n+K  are also multiplied by respective constants CS -K  . . . CS m  and summed in a summer 17. The outputs of the two summers 15 and 17 are summed by a summer 19 to provide the signal X EQ .sbsb.n. The output of the summer 19 X EQ .sbsb.n is fed to a phase correction circuit 21. Similarly, the samples X n+K  are multiplied by respective constants CS -K  . . . CS m  and the resulting products are summed in a summer 23. The samples Y n+K  are multiplied by respective constants CP -K  . . . CP m  and the resulting products are summed in a summer 25. The respective outputs of the two summers 23, 25 are summed by a summer 27 to produce the signal Y EQ .sbsb.n. This signal Y EQ .sbsb.n is then fed to the phase correcting circuit 21. The output X EQ .sbsb.n, Y EQ .sbsb.n of the phase correcting circuits are the equalized main channel signal components: 
     
         X.sub.EQ.sbsb.n =X.sub.EQ.sbsb.n COS θ.sub.n +Y.sub.EQ.sbsb.n SIN θ.sub.n 
    
     
         Y.sub.EQ.sbsb.n =Y.sub.EQ.sbsb.n COS θ.sub.n -X.sub.EQ.sbsb.n SIN θ.sub.n 
    
     where θ n  represents the necessary phase angle correction. 
     The phase corrected equalized main channel signals X EQ .sbsb.n and Y EQ .sbsb.n are then fed to respective decision circuits 29, 31 (FIG. 2). Each decision element 29, 31 decides the correct value of the output data signal DX n , DY n  from the respective raw outputs X EQ .sbsb.n, Y EQ .sbsb.n of the equalizer. The data signal values DX n , DY n  are then fed to the respective summers 33, 35 from which the main channel in-phase error component EX n  and the main channel quadrature phase error component EY n  are derived. 
     As known in the prior art, the equalizer constants CP -K  and CS -K , etc., are adjusted according to some algorithm in order to produce equalized output signals to remedy the effects of intersymbol interference. Such algorithms are well known in the art and will not be discussed further herein. 
     FIG. 3 discloses the second channel equalizer of the preferred embodiment which in the preferred embodiment is a derivative channel equalizer. Generation of the input signal X&#39; n+v , Y&#39; n+v  to the derivative channel equalizer is very well known. For example, if X n  and Y n  are the sampled in-phase and quadrature phase baseband signals, then X&#39; n  and Y&#39; n  are the corresponding sampled derivatives of these baseband signals. These samples are then fed to the respective delay elements 15, 17 of the equalizer, shown in FIG. 3, which differs in structure from the equalizer of FIG. 1 in the sole but significant respect that, according to the invention, the number of taps and tap constants CP -V  . . . CP W  and CS -V  . . . CS W  in FIG. 3 is less than the number of taps required by the equalizer of FIG. 1 to equalize the main channel received signal. The values of the tap constants CP, CS for corresponding taps of FIG. 1 and FIG. 3 are the same. By using fewer taps, i.e., V≦K, W&lt;M or V&lt;K, W≦M, the derivative signals X EQ .sbsb.n and Y EQ .sbsb.n, are not as precisely calculated and are typically in error to an extent not tolerable in the main channel received signal. However, according to the invention, it has been found that high accuracy is not required in these signals, whereas high accuracy is required in the output data DX n  and DY n . As a particular example, in a modem constructed according to the preferred embodiment, main tap to derivative tap numbers of 23 to 17, 30 to 19 and 39 to 26 were found to provide accurate operation. 
     Moreover, according to the invention, it has also been found unnecessary to determine the signal X EQ .sbsb.n and Y EQ .sbsb.n every baud. In the preferred embodiment these values and hence the values of X EQ .sbsb.n and Y EQ .sbsb.n are calculated once every other baud only, using a subset of the tap constants determined for the main channel equalizer of FIG. 1. 
     The correlation and phase lock structure employed to utilize these approximately-calculated derivative signals X EQ .sbsb.n and Y EQ .sbsb.n is illustrated in FIG. 4. The derivative signals X EQ .sbsb.n and Y EQ .sbsb.n are multiplied together with the respective error components of the main channel EX n  and EY n  in the respective multipliers 51, 53. The respective products EX n  X EQ .sbsb.n and EY n  Y EQ .sbsb.n are then summed in a summer 55 to produce a signal φ n  representative of the clock error. 
     The output φ n  of the correlator is then applied to a second order loop filter. The second order loop filter includes summers 57, 65 a delay element 59, and constant multipliers 61, 63. The output of summer 57 is denoted φ n  and is delayed by the delay element 59 whose output is fed back as one input to the summer 57. The summer 57 sums φ n  with the delayed value φ n-1  provided by the delay element 59 to provide φ n . The multiplier 61 multiplies φ n  by a loop constant B. A multiplier 63 also multiplies φ n  by a loop constant A to produce Aφ n . The loop constants A and B are chosen according to well-known phase lock loop design considerations. A summer 65 then sums Aφ n  and Bφ n  and produces an output ψ n . The elements 57, 59 and 61 cooperate to provide a second order loop characteristic and eliminate frequency offset between transmitter and receiver clocks. 
     Another summer 67 forms an output P n  =ψ n  +ψ n-1  by summing one input ψ n  with the output ψ n-1  of a delay element 69. The output P n  is fed to a decision block 71 where [P n  /α]·α is determined. The constant α is the smallest adjustment increment or decrement that can be made to the sample clock phase with the given hardware comprising a clock generator 73, and [P n  /α] represents the integer portion of P n  divided by α. Thus, [P n  /α]·α provides an integer number of increments or decrements for sample timing correction. 
     The remainder or non integer portion is determined by the quantity ψ n  =P n  -[P n  /α]·α. This remainder portion ψ n  is stored in the delay element 69 and combined with the next input to the summer 67 in order to provide more accurate sampletime adjustments. 
     As may be appreciated, since equalized derivative values X EQ .sbsb.n and Y EQ .sbsb.n are provided only once every other baud, the circuitry of FIG. 4 need only operate on a once per every other baud timing basis. Thus, the subscripts &#34;n&#34; as used in FIG. 4 indicate the value of the corresponding variable during one particular alternate baud period. 
     The preferred embodiment just described is admirably suited for a microprocessor modem environment where computation power is at a premium. By utilizing fewer taps, the number of multiplications and summations necessary to calculate X EQ .sbsb.n and Y EQ .sbsb.n are significantly reduced. By further limiting the calculations to once every other baud, the number of calculations is effectively cut in half. As a consequence of the preferred embodiment, the number of calculations required to implement FIG. 4 is also cut in half. All of these savings are made at no significant sacrifice to the ultimate accuracy of the timing correction provided. 
     As will be apparent to those skilled in the art, many modifications and adaptations of the just described preferred embodiment may be made without departing from the scope and spirit of the invention. Therefore, it is to be understood that, with the scope of the appended claims, the invention may be practiced other than as specifically described herein.