Abstract:
The invention relates to an electronic component with an integrated semiconductor circuit that comprises a core with functional flip-flops. A part of the functional flip-flops is linked as input flip-flops with input pins of the component and a part of the functional flip-flops is linked as output flip-flops with output pins of the component. In order to allow for efficient and cost-effective ASIC qualification methods that can be carried out rapidly and that take into consideration the growing complexity of integrated circuits and the rapid development of technology, the invention provides a method and a device wherein the input flip-flops and the output flip-flops are interconnected to a shift register during a qualification measurement of the component.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is the U.S. National Stage of International Application No. PCT/EP02/09689, filed Aug. 30, 2002 and claims the benefit thereof. The International Application claims the benefits of European application No. 01122773.3 filed Sep. 21, 2001, both applications are incorporated by reference herein in their entirety. 
     
    
     FIELD OF INVENTION  
       [0002]     The invention relates to an electronic component with integrated semiconductor circuit that comprises a core containing functional flip-flops, some of the functional flip-flops being connected as input FFs to input pins of the component, and some of the functional flip-flops being connected as output FFs to output pins of the component, as well as a method for its qualification testing.  
       BACKGROUND OF INVENTION  
       [0003]     Electrical components of this type are often designed as Application Specific Integrated Circuits (ASICs), which undergo extensive qualification procedures after fabrication. ASICs are a collection of circuits having simple functions, such as flip-flops, inverters, NANDs and NORs, and of more complex structures such as memory arrays, adders, counters and phase locked loops. The various circuits are combined in an ASIC in order to implement a specific application. ASICs are used in numerous products, for instance consumer products such as video games, digital cameras, in vehicles and PCs and also in high-end technology products such as workstations and supercomputers.  
         [0004]     Known ASIC architectures comprise an ASIC are containing the various circuit elements making up the function of the ASIC. The ASIC core receives the inputs to be processed from input drivers. After processing by the ASIC core, the output data is output via output drivers.  
         [0005]     Various “Design for Test” (DFT) techniques are known for testing the functionality of the ASIC. The advantage of DFT techniques is that circuit elements can be inserted back at the chip design stage, which enables later scanbased testing and reduces the number of test points required on the ASIC board while also getting around the problem of unavailable access points.  
         [0006]     Large numbers of test vectors are created in known qualification methods or test methods. These test vectors are then input into an ASIC, the aim being to drive certain outputs of the ASIC in order to change the logical state. When the output state changes, the “clock-to-output delay” can be measured, giving the delay between the supplied clocking pulse and the output appearing at the output. For the input areas of an ASIC, qualification methods are used to determine any timing violation that may exist, e.g. violation of the SETUP and HOLD time (see below), and to signal it at the output of the ASIC.  
         [0007]     For the output of a flip-flop to be determinate, i.e. not metastable, the inputs to the flip-flop must lie within the SETUP and HOLD time specification for the flip-flop. The SETUP time is the time period prior to the rising edge of the synchronization clock. The HOLD time refers to the time period after the rising edge of the synchronization clock. If the SETUP and HOLD timing criteria of the flip-flop are not met, the output of the flip-flop is not definitely guaranteed. Thus it is extremely important to find the SETUP and HOLD time accurately.  
         [0008]     Considerable amounts of time are involved in creating test vectors for qualification methods described above, because some of the test vectors are generated by hand. In addition, it is necessary to know the function of the ASIC core.  
         [0009]     Furthermore, the requirements of the test setup must be met, i.e. it might be necessary to stop the test run in order to reload the test vectors because of limited memory depth.  
         [0010]     Factors such as high pin count, complexity or logic depth, internal phase locked loops (PLLS) and logic power-up sequences of the ASIC also present problems for the test methods used for qualification of the ASIC. These factors will present even greater difficulties for ASIC qualification in the future.  
       SUMMARY OF INVENTION  
       [0011]     It is thus the object of the invention stated in claim  1  to create an electronic component and demonstrate a qualification method that in each case provide an efficient, cost-effective and quick to perform ASIC qualification method, while at the same time taking into account the ever increasing complexity of integrated circuits and the accelerating development pace of technology.  
         [0012]     This object is achieved by an electronic component as claimed in claim  1 , in which the input FFs and the output FFs can be connected together into a shift register during a qualification test of the component.  
         [0013]     This results in the following advantages: 
        Only relatively short test vectors need to be used for the timing measurement.     Short test times are obtained irrespective of the logic depth of the ASIC under test.     The test vectors can be generated automatically from a database similar to the Boundary Scan Description Language file (BDSL File).     Test teams need to get far less involved than before in the function of the ASIC.        
 
         [0018]     According to another advantageous embodiment of the present invention, the input FFs and the output FFs each have a switching element at their inputs, and are connected together by means of these under control from a controller central to all the switching elements. This reduces considerably the time involved in preparing timing measurements on the ASIC.  
         [0019]     In a particularly advantageous embodiment, the qualification test is a setup and/or a hold measurement at the input FFs, by means of which the timing measurements can be made without needing to put the central core into operation, and specific inputs and outputs of the integrated circuit are measured using test vectors irrespective of the logic depth in order to be able to make a setup and hold time measurement at the inputs.  
         [0020]     In a further advantageous embodiment, the qualification test is a clock-to-output time measurement at the output FFs and/or the outputs of the component, by means of which the timing measurements can be made without needing to put the central core into operation, and specific outputs of the integrated circuit are measured using test vectors irrespective of the logic depth in order to be able to find the clock-to-output delay at the outputs.  
         [0021]     In another preferred exemplary embodiment of the invention, the qualification test is an enable-to-output time measurement at the output FFs ( 8 ) and/or the outputs of the component ( 1 ), by means of which the switching speed of the tristate buffers can be measured.  
         [0022]     In another advantageous embodiment, the switching elements are multiplexers, which means that only a small amount of overhead is required in the hardware.  
         [0023]     In another advantageous exemplary embodiment, during the qualification test, the respective switching elements connect the output of one input FF or output FF to the input of an adjacent input FF or output FF respectively, in order to produce the shift register in a particularly simple way.  
         [0024]     In another advantageous exemplary embodiment, all input and output FFs receive the same clock via a clock tree during the qualification test. Thus a real clock is present during the timing measurements, and the clock tree relevant to the test and the PLLs are included in the timing measurements.  
         [0025]     In another advantageous exemplary embodiment, the input and/or output FFs receive a different clock via a clock tree in order to provide qualification tests for an ASIC having different clock domains.  
         [0026]     In a particularly advantageous exemplary embodiment, the controller has a first pin for controlling the switching elements, a second pin for controlling the unidirectional output buffers and a third pin for controlling the bidirectional output buffers, in order to provide the shift register and the control of the output buffers during the qualification test separately or in addition to the control from other test methods such as the production test, or a control from the core itself.  
         [0027]     In an alternative advantageous exemplary embodiment, the controller has a multiplicity of gates in order to provide, during the qualification method according to the invention, masking of controls from other test procedures, such as the production test, or of a control from the core itself.  
         [0028]     In achieving the object according to the invention by providing a method for qualification testing of an electrical component as claimed in claim  13 , in which the input FFs and output FFS are connected together into a shift register during a qualification test of the component, the same advantages result as for the device described above.  
         [0029]     An exemplary embodiment of the method according to the invention, in which the test data is input in parallel to the input FFS via inputs of the component, and then the controller connects together the input FFs and the output FFs into the shift register, whereby the test data passes serially through the shift register and is read out via one output, results in the additional advantage that timing measurements in the input area can be performed without needing to put the central core into operation.  
         [0030]     In another exemplary embodiment of the method according to the invention, the setup and hold time is found by varying the timing of the data input to the input FFs relative to the clock and by verifying the test data read out, enabling a precise definition of the setup and hold criteria to be found.  
         [0031]     In another additional exemplary embodiment of the method according to the invention, the controller connects the input FFs and the output FFS into a shift register, the test data is input serially into an input FF via an input of the component, the test data reaches the output FFS by passing serially through the shift register, and the clock-to-output times are measured at the relevant outputs of the component during the shifting sequence of the data into the output FFS. This results in the additional advantage that timing measurements can be made in the output area without needing to put the central core into operation.  
         [0032]     In a particularly advantageous exemplary embodiment of the method according to the invention, the test data is input in parallel into the input FFs via the inputs of the component, the controller then connects the input FFs and the output FFs into a shift register, the test data reaches the output FFs by passing serially through the shift register, and the clock-to-output times is measured at the relevant outputs of the component during the shifting sequence of the data into the output FFs. This allows a timing measurement to be made particularly quickly in the output area of the ASIC without needing to put the central core into operation.  
         [0033]     In another advantageous exemplary embodiment of the method according to the invention, a tristate buffer is controlled by a flip-flop ( 8   d ) of the shift register during the enable-to-output time measurement in the output area, the test vector data input serially into the shift register being used for the control. This enables an enable-to-output time measurement that is particularly simple to implement. 
     
    
     BRIEF DESCRIPTION OF THE DRAWING  
       [0034]     An exemplary embodiment of the invention is shown in the drawing and is described in more detail below. The single figure of the application shows a schematic diagram of an electronic component according to the present invention. 
     
    
     DETAILED DESCRIPTION OF INVENTION  
       [0035]      FIG. 1  shows an electronic component, more precisely an Application Specific Integrated Circuit (ASIC)  1  containing an integrated circuit (IC). The IC comprises an ASIC core  2  containing circuit elements such as flip-flops, inverters, NANDs and NORs etc. The arrangement of the circuit elements in the ASIC core  2  provides the specific function of the ASIC  1 .  
         [0036]     The data to be processed by the ASIC core  2  is input to the ASIC core  2  in parallel via input pins  3   a,    3   b,    3   c  and respective series-connected input buffers  4   a,    4   b,    4   c,  4     d.    
         [0037]     After processing by the ASIC core  2 , the processed data is output in parallel via unidirectional tristate buffers  5   a,    5   b,    5   c  and respective output pins  6   a,    6   b  and  6   c.  The tristate output buffers  5   a,    5   b,    5   c  can assume the logic states 1 and 0 and a high impedance state Z. In the preferred exemplary embodiment of the present invention, at least one pin  6   a  is bidirectional, i.e. the pin  6   a  can be used as an input pin via the input buffer  4   d  by switching of the tristate buffer  5   a  into the Z state.  
         [0038]     In the ASIC core  2  there are corresponding input flip-flops (input FFs)  7   a,    7   b,    7   d  and corresponding output flip-flops (output FFs)  8   a,    8   b,    8   c,    8   d  for the respective input and output pins  3 ,  6 . The input FFs  7   a,    7   b,    7   d  are arranged in at least one input block  9 , and the output FFs  8   a,    8   b,    8   d  are arranged in at least one output block  10 . The ASIC core  2  is thus divided into at least three blocks: the input block  9 , the output block  10  and a central core  11 . The input block  9  and the output block  10  together form the part of the core  2  referred to as the core boundary.  
         [0039]     The circuit elements of the input block  9 , the output block  10  and the central core  11  together provide the function of the IC of the ASIC  1 . The circuit elements are functional flip-flops (FF) and other functional elements such as inverters, NANDs and NORs etc. The term “functional” is used below to refer to flip-flops or other circuit elements that are only needed for operating the ASIC  1  and for implementing its application-specific function. Such flip-flops or circuit elements that are additionally provided e.g. solely and exclusively for performing test procedures are not covered by this term.  
         [0040]     In normal operation of the ASIC  1 , the data is input via the input pins  3 , and clocked in parallel into the input FFs  7   a,    7   b,    7   d  of the input block  9 . The data is then transferred in parallel into the central core  11  and processed further. After processing in the central core  11 , the data is passed in parallel into the output block  10  where the data is clocked into the output FFs  8   a,    8   b,    8   d  and transferred to the output pins  6   a,    6   b  and  6   c.    
         [0041]     The ASIC  1  has a clock input  12  that clocks the ASIC core  2  via a clock tree  13 . The central core  11  and the blocks  9 , 10  are clocked by using suitable phase locked loops (PLLs) or delay elements (clock input for central core not shown). Each input FF  7   a,    7   b,    7   d  and each output FF  8   a,    8   b,    8   d  is clocked via clock pins  14  and clock lines  15 .  
         [0042]     To perform a timing measurement in the input areas and the output areas of the ASIC  1 , the input FFs  7   a,    7   b,    7   d  are configured with the output FFs  8   a,    8   b,    8   d  into a shift register. This is made possible by the series connection of multiplexers  16  to the respective input of an input FF or output FF  7 , 8 . In normal operation of the ASIC  1 , the multiplexer  16  switches the inputs from the input pins  3   a,    3   b,    3   c  and the outputs from the central core  11  into the input and output FFs  7 , 8  respectively.  
         [0043]     During the ASIC timing measurement, the multiplexers  16  connect the input FFs and output FFs together via lines  17  into a shift register, or more precisely a scan chain (Core Boundary Scan). The chain starts at the input pin  3   c,  which becomes the input pin TESTER_IN for the test procedure, and ends at the last output FF  8   c  of an output  6   c  that doubles as TESTER_OUT.  
         [0044]     The multiplexers  16  may already be present for performing the production test along a scan path. In the production test, the functionality of circuit elements in the ASIC core  2  is tested along scan paths or test paths.  
         [0045]     The ASIC  1  is switched into the shift mode in the same way as for the production test via a SCAN_ENABLE pin  18  that forms part of a test controller  28 . The controller  28 , also referred to as a combinatorial device, controls switching elements of the ASIC core  2  and the unidirectional and bidirectional buffers  5   a,    5   b  and  5   c  when qualification procedures are being performed on the ASIC.  
         [0046]     When the shift register is meant to be formed, the multiplexers  16  are controlled by a signal applied to the SCAN_ENABLE pin  18  via scan lines  19 . Since the SCAN_ENABLE pin is also used for the production test, signals applied to the pin  18  are also fed to other sections (not shown) of the ASIC core  2  via a multiplexer  20  of the controller  28 , said multiplexer being controlled by a scan-mode pin  21  assigned to the controller  28 . This is done in order to connect “scan paths”, or test paths, for the production test in the core  2 . It would also be possible, however, to input control data from a built-in self-test controller (BIST controller)  21  into the core  2  via the multiplexer  20 .  
         [0047]     The controller  28  has a TESTER_ENABLE pin  23   a  for controlling the unidirectional tristate output buffers  5   a,    5   b,    5   c.  The signal from the TESTER_ENABLE pin  23   a  is input with any control signals present from the core into a first gate  25  of the controller  28 . In the preferred exemplary embodiment, the first gate  25  is an AND gate, with the signal from the TESTER_ENABLE pin  23   a  inverted at the input to the AND gate  25 . The output of the first gate  25  is taken via a control line  24  to the tristate output buffers  5  and controls their state. At the same time, the signal from the TESTER_ENABLE pin  23   a  is fed via an additional, second gate  26  of the controller  28  with the signal from the SCAN_ENABLE pin  18  into the multiplexer  20 , and hence into the ASIC core  2 . The second gate  26  is again an AND gate in the preferred exemplary embodiment. This enables masking, that is blocking, of the signal from the SCAN_ENABLE pin  18  to the ASIC core  2  by means of the TESTER_ENABLE pin  23 .  
         [0048]     During the qualification test of the present invention, the unidirectional ASIC outputs are enabled. In order to prevent the SCAN_ENABLE signal from the pin  18  to the ASIC core  2  having any effect during the qualification test, whether from PLLs or delay elements, the SCAN_ENABLE signal to the ASIC core  2  is blocked during the qualification test of the present invention, as explained above.  
         [0049]     A pin TESTER_BIDIR  23   b  is used as part of the controller  28  to control the at least one bidirectional pin  6   a.  A signal at this pin  23   b  is used to control whether the bidirectional pin  6   a  is used as input or output pin. In a similar way to the TESTER_ENABLE pin  23   a,  the signal from the TESTER_BIDIR pin  23   b  is taken to a third gate  27  with any control signals from the core  2  that may be present. In the preferred exemplary embodiment, the third gate  27  is an AND gate, and in a similar way to the first gate  25 , the signal from the TESTER_BIDIR pin  23   b  is inverted at the input to the gate. The output of the third gate  27  controls the state of the bidirectional tristate output buffer  5   a  via the control line  29 .  
         [0050]     An explanation is given below as to how timing measurements, or what is known as a core boundary scan, are made on the input areas and output areas of the ASIC  1  by using the ASIC  1  described above.  
         [heading-0051]     A) Measuring the Clock-To-Output Time at the Output:  
         [0052]     In order to measure the clock-to-output time, which is also known as the clock-to-output delay, the chain of input FFs  7   a,    7   b,    7   d  with the output FFs  8   a,    8   b,    8   d,    8   c  are brought into the shift mode by means of the SCAN_ENABLE pin  18 . The test vector, or the test pattern, for the outputs is input serially via the TESTER_IN pin  3   c.  The at least one bidirectional pin  6   a  has been switched into the output mode via the TESTER_BIDIR pin  23   b.  The clock-to-output time can be measured at the outputs during the serial input sequence of the test vector, e.g. a  0101  pattern. The measured times correspond to those when the ASIC  1  is in normal operation.  
         [0053]     Thus, the test vector data is input serially at the input pin  3   c  to the scan chain, or more precisely the shift register, and is analyzed in parallel at the output. It should be mentioned that a dedicated pin  3   c  is not essential for the input, because certain inputs can be used in more than one way.  
         [heading-0054]     B) Measurement of the Switching Speed:  
         [0055]     The measurement of the switching speed of the tristate buffer  5   b  of the at least one unidirectional pin  6   b  from Z to 1, from Z to 0, from 0 to Z and from 1 to Z is provided by an additionally implemented flip-flop (FF)  8   d  in the shift register. Control is effected via the test vector data input serially at the input pin  3   c.  Control signals from the flit flop  8   d  or control signals from the gate  25  of the controller  28  are fed to the tristate buffer  5   b  via a gate  30 , which in the preferred exemplary embodiment is an OR gate.  
         [0056]     The same effect can also be achieved for bidirectional pins by the measure described.  
         [heading-0057]     C) Measurement of SETUP and HOLD Times at the Inputs:  
         [0058]     When finding the SETUP and HOLD times, the at least one bidirectional pin  6   a  is switched to input via the TESTER_BIDIR pin  23   b.  The input FFs  7   a,    7   b,    7   d  are in normal operation, i.e. operating in parallel. At the ASIC  1 , the test vector pattern is applied to all input pins  3   a,    3   b,    3   c  for one clock pulse, and once the data has been transferred into the input FFs  7   a,    7   b,    7   d,  the shift mode is established via the SCAN_ENABLE pin  18  using the multiplexer  16  and the data is output serially from the ASIC  1  so that the data can be analyzed.  
         [0059]     This process is then repeated, but the step of applying the test input pattern to all input pins  3  is varied in time relative to the clock. When the analyzed data contains errors, this is an indicator that the SETUP and HOLD timing criterion for the input FF or input FFs has been violated. Thus the SETUP and HOLD time can be found indirectly, because violation of the timing at the inputs is signaled by erroneous output at the outputs of the ASIC  1 .  
         [0060]     To sum up, it can be said that the present invention provides an electronic component and a method for an improved timing measurement in integrated circuits. The new component and the new method are based on a small amount of advance hardware design work in the ASIC, generally also referred to as Design for Test (DFT). The method and device described above provide the following advantages: 
        Only relatively short test vectors need to be used for the timing measurement.     Short test times are obtained irrespective of the logic depth of the ASIC  1  under test.     The test vectors can be generated automatically from a database similar to the Boundary Scan Description Language file (BDSL File).     The timing measurements can be performed without needing to put the central core  11  into operation.     The clock tree  13  relevant to the test and the PLLs are included in the timing measurements, i.e. a real clock is present during the timing measurements.     Test teams need to get far less involved than before in the function of the ASIC  1 , thus reducing considerably the preparation time involved in timing measurements.     The hardware overhead is low.        
 
         [0068]     The present invention can also be used in particular in connection with the International Application No. PCT/EP02/09690, filed Aug. 30, 2002, titled “Electronic component”, which is incorporated by reference herein in its entirety.