Abstract:
A digital divider with both integral and fractional division capabilities is provided by utilization of a counter and one decoder to trigger phase reversal and a second decoder to trigger short-cycling of the counter. The first decoder provides phase reversal to cause extra half pulses during the period established by the second decoder to thus create the fractional count needed for fractional division. A control input is included to select either whole number division or fractional division.

Description:
The Government has rights in this invention pursuant to a Contract No. N00039-84-C-0403 with the Department of the Navy. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to digital division of electrical signals by both integer and fractional division ratios. Fractional division is particularly important in digital data transmission and in the transmission of digitized voice, both of which are clocked from a common timing source and which require a plurality of lower frequency rates, some of which may be fractional rates. 
     2. Description of the Prior Art 
     Digital divider circuits of the prior art typically are capable of whole integer binary or decade division of an electrical signal into a plurality of divided down signals at lower frequency rates. An example of a conventional whole number digital divider is a standard synchronous presettable binary counter such as the Fairchild Semiconductor 54F/74F161A or 54F/74F163A high-speed synchronous modulo-16 binary counters. This standard component has the capability of receiving an input clock and generating lower frequency clocks at 1/2, 1/4, 1/8, and 1/16 the input clock frequency. This prior art synchronous presettable counter also enables the presetting of selectable states out of the normal order to obtain various combinations of whole integer division of an input timing signal. 
     It is also known in the prior art that by changing the phase of the incoming timing signal that the clock rate will be affected. Various circuits utilizing a plurality of digital components have been devised in the known prior art to accomplish digital division by a fractional number. All of the known prior art techniques involve complex logic circuitry having a large number of components and tend to result in assymetric signals after the fractional division is accomplished; that is, instead of a well defined squarewave or near squarewave, the fractionally divided down signal may consist of logic pulses of approximately 20% up (high) and 80% down (low) or vice versa. 
     In the prior art, separate circuits are used, for example, for a divide-by-4 and divide-by-4.5 operation. The divide-by-4 circuit can be a standard 2-bit counter available off-the-shelf while the divide by 4.5 circuit may typically consist of a 5-bit Johnson counter whose fifth bit is used to control the counter through other logic circuitry such that the count is shortened by a 1/2 clock period each 5 counts, causing the Johnson counter to divide by 9 instead of the normal 10. 
     It is, therefore, an object of the present invention to provide a simple digital circuit for effecting fractional digital division of an incoming timing or clock signal with a selectable division ratio, low power dissipation, and a substantially reduced number of electrical components. 
     It is an additional object of the present invention to obtain a fractional divided down output signal as close to symmetric as possible. Such symmetry is important in data transmission; particularly for a timing signal, since the sampling edge of a clock should be approximately in the center of the data pulse to be sampled, otherwise noise rather than data could be sampled. 
     SUMMARY OF THE INVENTION 
     The present invention describes a digital division circuit for fractionally dividing an incoming timing or clock signal by a fractional value by means of manipulating the division operation of a counter by both presetting certain of the counter states out of their normal order and by selectively changing the phase of the incoming digital signal to be divided, prior to the midpoint of the timing signal cycle. It has been discovered that by using the combination of both presetting selection of the counter states out of their normal order and by selectively changing the input signal phase that not only is fractional division accomplished, but that the fractionally divided signals are generally symmetrical in nature so that they are useful as clock or timing signals in data processing and/or data transmission applications. 
     Other objects and advantages of the invention will become apparent with reference to the accompanying figures and detailed description thereof, wherein: 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a divide by 4.5 circuit in accordance with the present invention. 
     FIGS. 2(a), 2(b), 2(c), 2(d), 2(e), 2(f), 2(g), and 2(h) are waveform diagrams useful in explaining the operation of the circuit described with reference to FIG. 1. 
     FIG. 3 is a circuit diagram of a divide by 5.5 circuit in accordance with the present invention. 
     FIGS. 4(a), 4(b), 4(c), 4(d), 4(e), 4(f), 4(g), and 4(h) are waveform diagrams useful in explaining the operation of the circuit described with reference to FIG. 3. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to FIG. 1, a circuit in accordance with the present invention for dividing an input timing signal by a fractional divisor, in this example by 4.5, is illustrated. A binary counter such as synchronous presettable binary counter 10 which may be, for example, either a 54F163A or 74F163A, Fairchild Semiconductor MSI modulo-16 binary counter may be utilized. Any particular digital timing signal on line 12 is coupled to one input of an exclusive-OR gate 14. The input timing signal is illustrated by waveform 2(a), and may be, for example, an 18.432 megahertz squarewave. In normal operation the modulo-16 binary counter 10 is capable of selectively generating a plurality of divided down outputs at Q 0 , Q 1 , Q 2 , and Q 3  of 1/2 the frequency of the input timing signal at Q 0 , 1/4 of the input timing signal at Q 1 , 1/8 of the timing signal at Q 2 , and 1/16 of the timing signal at Q 3 . As will become evident, the parallel data inputs P 0 , P 1 , P 2 , P 3  and the phase of the input timing signal can be selectively manipulated so as to vary the result of the input timing signal division. In essence, the specific division integer depends upon the output state selected out of its normal order and the fractional portion of the division depends upon the state at which a phase change of the input timing signal is initiated. The rate of the input timing signal is a fixed rate higher than the rate desired by the final divided down output rate. Exclusive-OR gate 14 either couples the input timing signal to its output or inverts the input timing signal in accordance with a control signal applied via line 16. The control signal is used to select either conventional divide-by-4 operation or the divide-by-4.5 operation of the invention. The timing signal from exclusive-OR gate 14 is applied to the counter 10 at its clock input at line 20 and is illustrated at FIG. 2(b) as the clock signal. The programmable divider integrated circuit 10 may be programmed to divide by integers 2-16 based on the use of its parallel data inputs P 0 , P 3  and the PE (parallel enable) input. The present embodiment manipulates the signals applied to these inputs to selectively divide-by-4 or to divide-by-4.5 based upon the control signal applied at line 16 to the inputs of NAND gate 22 and NAND gate 24. 
     In the conventional divide by 4 operational mode, a selected signal at the logic &#34;zero&#34; level is applied to the input of NAND gates 22 and 24 via line 16. This condition forces the output of NAND gate 24 on line 26 and the output from NAND gate 22 on line 28 to the logic &#34;one&#34; state. The logic &#34;one&#34; state from line 26 to the input of exclusive-OR gate 14 via line 18 selects &#34;phase one&#34; from the timing source (the input to line 12, which may be any conventional clock generator and which in this instance supplies the 18.432 megahertz timing signal). This &#34;phase one&#34; has no affect at the parallel data input P 3  due to the fact that the logic &#34;one&#34; level from line 28 to the parallel enable input PE of counter 10 disables parallel entry of data on the parallel data inputs P 0 , P 1 , P 2 , and P 3 . The output signal in this mode from Q 1  is a squarewave which completes one cycle for each 4 cycles of every clock frequency at the clock input on line 20 to counter 10. The counter 10 enters the logic states 0-15 as described by the outputs Q 3 , Q 2  , Q 1 , and Q 0 . In binary representation, these states are: 
     
         ______________________________________   State        Binary______________________________________   0    0000   1    0001   2    0010   3    0011   4    0100   5    0101   6    0110   7    0111   8    1000   9    1001   10   1010   11   1011   12   1100   13   1101   14   1110   15   1111______________________________________ 
    
     Fractional division is enabled by impressing a logic &#34;1&#34; level to NAND gates 22 and 24 via line 16 by the control signal thereon to enable the NAND gates 22 and 24. The Q 2  output signal from divider 10 is controlled by NAND gate 22 via line 28 to the parallel enable PE input of counter 10. The Q 3  signals from counter 10 are controlled by NAND gate 24 to select the phase of the clock signal through the exclusive-OR gate 14 to the clock input at line 20 of counter 10. Assume the following initial conditions as an example of the circuit operation: 
     (1) The counter 10 is in the binary state 3 (0011). 
     (2) The exclusive-OR gate output is clock phase &#34;1&#34;. 
     Operation continues with the counter 10 entering state 4 (0100) at the rising of the next clock phase &#34;1&#34; signal on the clock input 20 to counter 10. Once in the state 4, the output Q 2  is inverted through NAND gate 22 and enables the present enable function at the PE input of counter 10. Additionally, the Q 3  (logic zero) output of counter 10 appears inverted through NAND gate 24 at the preset P 3  input of counter 10. Upon arrival of the next rising phase &#34;1&#34; clock edge at the clock input 20 of counter 10, the present load forces the divider to state 8 (1000). 
     Two new actions now occur: the parallel load signal is terminated and the phase &#34;two&#34; of the clock signal is generated by the inversion of the timing signal through the exclusive-OR gate 14. Changing the phase of the clock signal at the clock input from line 20 causes another rising clock edge to terminate state 8 at approximately one-half period earlier than if the phase &#34;1&#34; timing were continued. This can be seen at FIG. 2(b) by the direction of the phase &#34;2&#34; arrows at the divider states indicated at FIG. 2(h). Additional phase &#34;2&#34; clock signals drive the divider through states 9, 10, 11, and 12. In state 12 (1100) the preset enable (PE) is again active and on the next clock edge the preset load forces the divider to the zero state (0000). The Q D  signal inverted through NAND gate 24 causes the selection of the phase &#34;1&#34; clock signal. Changing the phase of the clock signal at the clock input on line 20 to the divider causes another rising clock edge to terminate state zero approximately one-half period earlier than if phase &#34;two&#34; timing were continued. 
     Additional clock pulses drive the divider to stated initial conditions and the process repeats. The input at pulse enable (PE) is shown at FIG. 2(c), and the divided down outputs of Q 3 , Q 2 , Q 1 , Q 0  are shown at FIGS. 2(d), 2(e), 2(f), and 2(g) respectively. The desired output signal at Q 1 , shown by FIG. 2(f), is available as a timing source with a period 41/2 times the original reference signal. Also as can be seen the signal has approximately 55/45% symmetry and thus functions ideally as a data clocking signal. Additionally, the Q 3  output of the divider is available as a 50% duty cycle squarewave at nine times the period of the original reference signal. 
     Referring now to FIG. 3 and to the waveforms of FIG. 4(a) through 4(b), an additional embodiment of applicant&#39;s invention, illustrative of fractional division by 5.5 is illustrated. 
     A counter 100, which may be a binary counter, a decade counter, or a synchronous presettable counter of the same type as described with reference to the circuit of FIG. 1, may be used to divide down an input squarewave f on line 101 and which is illustrated at FIG. 4(a). In like manner as described with reference to FIG. 1, the counter 100 divides its input by 1/2, 1/4, 1/8, and 1/16 to derive a plurality of whole integer division frequencies at Q A , Q B , Q C , and Q D , respectively. In accordance with applicant&#39;s invention, a circuit comprised of exclusive-OR gate 102 and NAND gate 104 is configured so as to both preset desired states of the counter 100 and to change the phase of the input timing signal at selected states, thereby changing the division of frequency f to a desired fractional division--in this example to f divided by 5.5 at the Q B  output. An inverter 111 is provides the correct polarity for the signal going to input P 3 . As can be seen on the state diagram associated with FIG. 3, states zero and eight are controlled at parallel data input P 3 , and which is provided as an input to exclusive-OR gate 102 together with the input squarewave f. The preset is enabled when Q A  and Q C  are at a logic high via the NAND gate 104 output to the preset enable input PE. The clock phase approximately midway through states zero and eight is reversed as can be seen at FIG. 4(b), which causes the time duration of states zero and eight to be 1/2 of their normal interval and results in the waveform outputs of FIGS. 4(d), 4(e), 4(f), and 4(g) at flip-flop outputs Q 3 , Q 2 , Q 1 , and Q 0  respectively of the counter during the divider states indicated at FIG. 4(h). Effectively the Q A  and Q C  outputs are decoded by NAND gate 104 to enable the preset enable as can been seen at FIG. 4(c). The result is an output at Q B  of f divided by 5.5 and an output at Q D  of an f divided by eleven squarewave. In this case the symmetry is approximately 60/40% which is an acceptable data clock signal. As can be seen, this fractional division operation is achieved by the simple means of effectively manipulating the states and phase of the signals which are already available and without the use of complex logic circuitry. 
     While the present invention has been described in connection with a preferred embodiment thereof, it is to be understood that the invention is not limited to the specific implementations, and that additional embodiments, modifications and application which will become obvious to those skilled in the art are included within the spirit and scope of the invention as set forth by the claims appended hereto.