Abstract:
A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltage at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    Aspects of the present disclosure relate in general to electronic circuitry. In particular, aspects of the disclosure include an input voltage tolerant circuitry and device able to receive a voltage input three times (3×) larger than the device operating voltage. 
         [0003]    2. Description of the Related Art 
         [0004]    Advanced Integrated Circuits (IC) fabrication processes have been constantly evolving. As the electronics market demands higher performance and lower power consumption, IC fabrication processes increase their integration density, which also results in more reliable circuits. As circuit integration density rises, designers lower the voltage of the power supply needed to run the IC chips. Lowering power supply voltage allows the fabrication process to have smaller geometries and better performance without compromising the reliability or the quality of the integrated circuits. 
         [0005]    One consequence of using the lower power supply voltage is the susceptibility of input and output pads to damage from external voltages higher than the power supply of the integrated circuit. This situation occurs when an external device, which operates at a higher power supply voltage and is electrically coupled to the input/output pad, drives the pad to a greater voltage than the power supply of the integrated circuit. The situation may also occur from transient spikes on the power supply of the IC. Damage results if excessive voltages occur across any two of the three terminals of the transistor (Gate, Source, Drain). 
         [0006]    Damage also results to the transistor gate oxide due to hot carrier injection, if the transistor draws large amounts of current from its drain to its source. Excessive voltages introduced across the transistor source and drain when the transistor is on allows excessive current to flow. The excessive current results in permanent damage to the transistor. 
         [0007]    A contextual example of the above situation may be seen in the migration of integrated circuits from 5 volts to 3.3 volts, or 3.3 volts to 1.8 volts. As the 5 volt to 3.3 volt migration took place, applications were being built that have both 5 volts and 3.3 volts driving the same bus. This was possible since the logic levels driving and received by 5 volt and 3.3 volt chips are usually the same. For example, both 5 volt and 3.3 volt chips consider a logic “1” to be any voltage above 2.5 volts, while a logic “0” is any voltage below 0.4 volts. As a result of mixed IC applications, however, ICs powered by 3.3 volt sources need to be tolerant to the 5 volt signals. Since these signals can also be very high speed signals, the 3.3 volt chips must also be tolerant of the increased transmission line spikes and reflections caused by the increased speed. 
         [0008]    A 3.3V input/output interface is built with 3.3V (or can be overdriven to 3.3V, such as 2.5V overdriven to 3.3V) process. If a 1.8V system has to migrate to another system with 3.3V interface there are a plethora of problems. In some cases, the current circuit solution is overdriving 1.8V to 3.3V (0-2×), as shown in  FIG. 1  (PRIOR ART). Similarly, a 0-3× overdrive circuit is shown in  FIG. 2  (PRIOR ART). However with these circuits reliability is a major issue, as hot carrier injection (HCI) may take place. Moreover these circuits consume a high amount of direct current (DC) power if specific middle bias is needed. 
       SUMMARY 
       [0009]    A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltage at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages. 
     
    
     
       DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1  depicts a conventional input voltage tolerant structure of the PRIOR ART. 
           [0011]      FIG. 2  shows another conventional input voltage tolerant structure of the PRIOR ART. 
           [0012]      FIG. 3  is an embodiment of an input voltage tolerant device capable of supporting a 2× voltage overdrive operation with a 3× voltage tolerate input feature. 
           [0013]      FIG. 4  is an alternate embodiment of an input voltage tolerant device with an electro static discharge (ESD) device. 
           [0014]      FIGS. 5A-5E  are usage examples of an embodiment of an input voltage tolerant device. 
           [0015]      FIG. 6  is an depicting an implementation of an N-shield, a cross-control circuit and a pull-down driver circuit. 
           [0016]      FIG. 7  illustrates an implementation of a cross-control circuit, P-shield and a pull-up driver circuit. 
           [0017]      FIG. 8  is an embodiment of a portion of the cross-control circuit, which provides signal to a portion of the cross-control circuit in  FIG. 7 . 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    One aspect of the present disclosure includes a voltage tolerant input/output circuit configured to three times the internal device voltage. 
         [0019]    The following embodiments are described in a plurality of sections. Further, circuit elements making up each of functional blocks of the following embodiments are formed on a semiconductor substrate made of a single crystal silicon by use of the known integrated circuit (IC) technology for Complementary Metal Oxide Semiconductors (CMOS) transistors. With the present embodiments, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (abbreviated to MOS transistor) is used as an example of a Metal Insulator Semiconductor Field Effect Transistor (MISFET). However, a non-oxide film is not precluded as a gate insulating film. In the drawings, a symbol  0  is affixed to a p-channel MOS transistor (PMOS transistor or “p-type” transistor) to be thereby differentiated from an n-channel MOS transistor (NMOS transistor or “n-type” transistor). Further, in the drawings, connection of a substrate potential of a MOS transistor is not specifically shown, however, there is no particular limitation to a connection method thereof if the MOS transistor is present in a normally operable range. 
         [0020]    Embodiments of the invention will be described hereinafter with reference to the drawings. In all the drawings for use describing the embodiments, identical members are in principle denoted by like reference numerals, thereby omitting detailed description thereof. 
         [0021]    For the sake of convenience, we will refer to the device operating voltage as “1×” voltage. Similarly, twice operating voltage is “2×” voltage, and three-times the operating voltage is “3×.” It is understood by those familiar with the art that the voltages are approximates. For example, a typical “1×” voltage might be around 1.8 volts, while a “2×” voltage would be approximately 3.3 volts, and a “3×” voltage would be about 5 volts. It is understood that embodiments may use different voltages, and the input tolerant circuitry would be design to facilitate the range of voltage inputs/outputs. 
         [0022]    Embodiments will now be disclosed using a power supply (PWR) that is twice (2×) the operating voltage. 
         [0023]    Let us now turn to an embodiment of a voltage tolerant input/output circuit  3000 , shown in  FIG. 3 .  FIG. 3  is an embodiment of an input voltage tolerant device capable of supporting a 2× voltage overdrive operation with a 3× voltage tolerate input feature, designed in accordance with an embodiment of the present disclosure. As shown in  FIG. 3 , voltage tolerant input/output circuit  3000  is coupled to an input/output pad, and includes a pull-up driver  3002 , a pull-down driver  3004 , a P-shield  3006 , an N-shield  3008 , and a cross control circuit  3010 . Details of these elements are elaborated on below. 
         [0024]    P-shield  3006  may have an N-well, as is known in the art. 
         [0025]    Cross control circuit  3010  receives and detects the voltage at three node points: node A, node C, and the input/output pad. Cross control circuit  3010  uses these monitors these voltages and outputs control signals to the P-shield  3006  and N-shield  3008  to ensure reliability of the circuit. The operation of cross control circuit  3010  is described in greater detail below in  FIG. 5 . Embodiments of pull-up driver  3002 , a pull-down driver  3004 , a P-shield  3006 , an N-shield  3008 , and a cross control circuit  3010  are discussed with respect to  FIG. 6-8  below. 
         [0026]      FIG. 4  depicts an alternate embodiment of an input voltage tolerant device  4000  coupled with an electro static discharge device, designed in accordance with an embodiment of the present disclosure. Essentially, input voltage device  4000  is similar to input voltage device  3000  with the addition of an ESD device to shield components from direct contact with the input/output pad. As shown in  FIG. 4 , voltage tolerant input/output circuit  4000  again includes a pull-up driver  3002 , a pull-down driver  3004 , a P-shield  3006 , an N-shield  3008 , and a cross control circuit  3010 . The elements are shielded from direct contact with the input/output pad via an electro static discharge device  4012 . For convenience sake,  FIG. 4  depicts the electro static discharge device  4012  as a number of discrete devices  4012 A-D. It is understood by those well-rehearsed in the art that any electro static discharge device  4012  may be a resistor or any other electro static discharge device known in the art. 
         [0027]      FIGS. 5A-5E  are usage examples of an embodiment of an input voltage tolerant device  3000 , designed in accordance with an embodiment of the present disclosure. 
         [0028]      FIG. 5A  depicts input voltage tolerant device  3000  in use in a low output mode, where the output voltage at the pad is zero volts. In such an embodiment, pull down driver  3004  pullset the voltage at node A to zero (low voltage). Cross control circuit  3010  detects the low voltage at node A, and outputs 0 voltage to node B (controlling the gate of the N-shield  3008 , turning it on). Cross control circuit  3010  outputs 1× voltage to node W (an N-well within the P-shield  3006 ). Furthermore, cross control circuit  3010  may also output 0-1× voltage to node C and node D (controlling the gate of the P-shield  3006 , turning it off). This sequence of cross control circuit  3010  outputs would result in the input/output pad being pulled low (zero volts). 
         [0029]    The input voltage tolerant device  3000  in  FIG. 5B  is being used to output 2× voltage. In such an use, the cross control circuit  3010  detects a high voltage at node C. Cross control circuit  3010  then outputs 1×-2× voltage to node A and node B (controlling the gate of the N-shield  3008 , turning it off). At node D, cross control circuit  3010  outputs 1× voltage to node D (controlling the gate of the P-shield  3006 , turning it on), and 2× voltage at node W (the N-well within the P-shield  3006 ). This results in output pad voltage being pulled to 2×. 
         [0030]      FIG. 5C  shows operation of input voltage tolerant device  3000  in a low input mode, where the input voltage received at the pad is zero volts. Initially, cross control circuit  3010  detects input voltage at the pad being zero volts. The pull-up driver  3002  and pull-down driver  3004  are turned off. Low input at the pad triggers cross control circuit  3010  to control nodes A, B, C, and D, between 0-1× voltage, and control node W as 1× voltage. 
         [0031]    In another use of voltage tolerant device  3000 , the input voltage at the pad is 2×.  FIG. 5D  depicts this scenario. Cross control circuit  3010  detects the 2× input voltage. The pull-up driver  3002  and pull-down driver  3004  are turned off. The high (2×) input at the pad triggers cross control circuit  3010  to control nodes A, B, C, and D, between 1-2× voltage, and control node W as 2× voltage. 
         [0032]      FIG. 5E  depicts input voltage tolerant device  3000  in use in a very high input mode, where the voltage at the pad is three times the operating voltage. Cross control circuit  3010  detects Cross control circuit  3010  detects the 3× input voltage. The pull-up driver  3002  and pull-down driver  3004  are turned off. The very high (3×) input voltage at the pad triggers cross control circuit  3010  to output 2× voltage at nodes A, B, and C, and 3× voltage at nodes D and W. 
         [0033]      FIG. 6  is an embodiment of a portion of an input voltage tolerant device  3000  depicting an implementation of a cross-control circuit  3010 , N-shield  3008  and a pull-down driver circuit  3004 , designed in accordance with an embodiment of the present disclosure. Other circuit elements are disclosed in the remaining figures. 
         [0034]    As shown, N-shield  3008  may be a single n-type transistor controlled by the cross-control circuit  3010  and coupled to the pull-down driver  3004  and the input/output pad. 
         [0035]    Pull down-driver  3004  may be implemented as two additional n-type transistors in series, connected source-to-drain, with one of the n-type transitors being controlled via a pull-down driver control NGATE. It is understood by those familiar with the art that other pull down drivers in the art may be substituted. 
         [0036]      FIG. 6  further depicts a section of cross-control circuit  3010 , which receives input/output voltages from nodes B, C and D, and pull-up driver control PGATE. 
         [0037]      FIG. 7  is an embodiment of a portion of an input voltage tolerant device  3000  depicting an implementation of a cross-control circuit  3010 , P-shield  3006  and a pull-up driver circuit  3002 , designed in accordance with an embodiment of the present disclosure. 
         [0038]    As shown, P-shield  3006  may be two p-type transistor controlled by the cross-control circuit  3010  (at node D) and coupled to the pull-up driver  3002  and the input/output pad. 
         [0039]    In this embodiment, pull up driver  3002  may be implemented as a p-type transistors being controlled via a pull-up driver control PGATE. 
         [0040]      FIG. 7  further depicts another section of cross-control circuit  3010 , which receives input/output voltages from nodes B, C and D, and pull-up driver control PGATE. Cross-control circuit  3010  also receives input/output voltages from pad and “node F”, as depicted in  FIG. 8 . 
         [0041]      FIG. 8  is a portion of an embodiment of a cross-control circuit for use in an input voltage tolerant device, designed in accordance with an embodiment of the present disclosure. Nodes F and nodes E in  FIG. 8  are connected the nodes of the same name of  FIG. 7 . 
         [0042]    The PGATE_BAR indicates the reverse phase (180 degree shift) signal of PGATE. For example, if PGATE=0 then PGATE_BAR=1. 
         [0043]    The previous description of the embodiments is provided to enable any person skilled in the art to practice the invention. The various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of inventive faculty. Thus, the current disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.