Abstract:
A method of testing a circuit having a plurality of one-time programmable cells. The method generally comprises the steps of (A) transmitting a plurality of addresses to the circuit and (B) receiving a plurality of values from the circuit each representing at least one of the one-time programmable cells in response to one of the addresses.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a method and/or architecture for testing one-time programmable cells generally and, more particularly, to testing laser-activated fuses independent of a test scan chain. 
   BACKGROUND OF THE INVENTION 
   Referring to  FIG. 1 , a block diagram of a conventional arrangement  10  for testing fusible cells is shown. Each fuse cell  12   a–c  is associated with a scan flip-flop  14   a–c  within a test scan chain  16 . Multiplexers  18   a–c  are provided to present values of the respective fuse cells  12   a–c  into the respective flip-flops  14   a–c . The fuse cell values are then read in serial fashion through the test scan chain  16  by clocking the flip-flops  14   a–c  with a clock signal (i.e., CLOCK). 
   In the past there have been problems with using laser-activated fuses using the conventional arrangement  10 . One problem is that the fuse cells  12   a–c  alter a scan test methodology. Programming different values into the fuse cells  12   a–c  for different parts cause different captured outputs. Therefore, a custom set of scan test vectors must be created and maintained for each programming pattern of the fuse cells  12   a–c . The multiple sets of test vectors reduce an efficiency of a test engineer as well as a tester itself. Furthermore, generation of the multiple vector sets adds complexity as compared to a single set. Alternatively, if the flip-flops  14   a–c  are not inserted onto the test scan chain  16 , there has been no way to read or test the programmed fuse cells  12   a–c.    
   Another conventional technology is to use a read-only memory (ROM) cell to replace the functionality of the fuse cells  12   a–c . However, the ROM cell approach does not allow for customization among parts based on a common design. Each unique ROM cell program requires a unique fabrication mask. The idea with the laser-activated fuses is that within one mask set, there could be different values in the fuse cells  12   a–c.    
   SUMMARY OF THE INVENTION 
   The present invention concerns a method of testing a circuit having a plurality of one-time programmable cells. The method generally comprises the steps of (A) transmitting a plurality of addresses to the circuit and (B) receiving a plurality of values from the circuit each representing at least one of the one-time programmable cells in response to one of the addresses. 
   The objects, features and advantages of the present invention include providing a method and/or architecture for testing one-time programmable cells that may provide for (i) a simple way for one-time programmable cells to be used as customizable static data storage cells, (ii) testing programs written into one-time programmable cells independent of a test scan, (iii) testing one-time programmable cells without hindering scan test methodology, (iv) increasing an efficiency of a tester, (v) increasing an efficiency for a test engineer, (vi) reducing a cost of developing parts from a common design, (vii) reducing a complexity of developing parts from a common design, and/or (viii) reading fuse values in a test or a manufacturing mode. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
       FIG. 1  a block diagram of a conventional arrangement for testing fusible cells; 
       FIG. 2  is a block diagram of an example circuit in accordance with a preferred embodiment of the present invention; 
       FIG. 3  is a block diagram of a second example embodiment of the circuit; 
       FIG. 4  is a block diagram of a third example embodiment of the circuit; 
       FIG. 5  is a partial block diagram of a fourth embodiment of the circuit; 
       FIG. 6  is a flow diagram of a method of producing the circuit; and 
       FIG. 7  is a flow diagram of a method for testing a programmed identification value through a test scan chain. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The present invention generally isolates one-time programmable cells from a test scan chain, while still maintaining testability and visibility of the one-time programmable cells. The testability and visibility may be maintained through a memory-mapped interface to a block of the one-time programmable cells. The memory-mapped interface generally allows the one-time programmable cells to be tested by “reading” the one-time programmable cells. Reading generally involves presenting a correct address on an address bus. Data that may be programmed or stored in the one-time programmable cells at the address may then be presented on a data bus. A tester may then compare the read data values with the programmed values that should be contained in the one-time programmable cells. The approach generally maintains testability and visibility of the one-time programmable cells and may eliminate a need for conventional fuse cell flip-flops to be on a conventional scan chain. 
   Referring to  FIG. 2 , a block diagram of an example device or circuit  100  is shown in accordance with a preferred embodiment of the present invention. The circuit  100  generally comprises multiple one-time programmable cells  102   a–x , a circuit  104  and a multiplexer circuit  106 . The one-time programmable cells  102   a–x  may be considered as an M column by N row array  107 . The circuit  100  may be implemented on an integrated circuit or chip  108 . 
   An input  109  of the circuit  100  may receive a signal (e.g., EXT — ADD). Another input  110  of the circuit  100  may receive another signal (e.g., READ — ENABLE). The circuit  100  may include an output  112  to present a signal (e.g., DATA). The interfaces  109 ,  110 , and  112  may be configured as a memory-like interface to allow for testability and visibility into the circuit  100 . 
   The circuit  104  may receive the signal EXT — ADD. The circuit  104  may also receive the signal READ — ENABLE. A signal (e.g., MUX — ADD) may be generated and presented by the circuit  104  to the multiplexer circuit  106 . Multiple signals (e.g., A–N) may be generated and presented by the one-time programmable cells  102   a–x  to the multiplexer circuit  106 . The multiplexer circuit  106  may generate and present the signal DATA at the output  112 . 
   Each one-time programmable cell  102   a–x  may be fabricated having a first state and may be programmable into a second state. The one-time programmable cells  102   a–x  may be implemented as, but are not limited to fuse cells, antifuse cells, laser-activated cells (e.g., ablated or annealed), thermally programmable cells, or the like. Programming of the one-time programmable cells  102   a–x  generally involves changing an impedance of the cells  102   a–x . Some types of one-time programmable cells  102   a–x  may change from a low impedance to a high impedance while other types of one-time programmable cells  102   a–x  may change from the high impedance to the low impedance. Each one-time programmable cell  102   a–x  may include additional circuitry (not shown) that may allow the cell  102   a–x  to present a programmed value as a voltage or a current. The fuse block array  107  may be collared or isolated from the scan chain ( FIG. 5 ). Therefore, values read from the scan chain may be independent of the fuse values stored in the fuse block array  107 . 
   The circuit  104  may be implemented as an address decoder circuit. The address decoder circuit  104  generally translates the signal EXT — ADD into the signal MUX — ADD. The translation may compress, shift and/or expand an address range received through the signal EXT — ADD into the signal MUX — ADD. Translation of the signal EXT — ADD may be dependent upon the signal READ — ENABLE. While the signal READ — ENABLE may be in an asserted state, the address decoder circuit  104  may generate the signal MUX — ADD based upon the signal EXT — ADD. While the signal READ — ENABLE may be in a de-asserted state, the address decoder circuit  104  may generate the signal MUX — ADD with a default address. 
   The multiplexer circuit  106  may be implemented as an M-bit wide/input by N or N+1 input multiplexer. The M-bit width may match the M columns of the array  107 . The N inputs may match the N rows of the array  107 . The extra input may be for a default value. The multiplexer circuit  106  may multiplex the signals A–N to generate the signal DATA as controlled by the signal MUX — ADD. The multiplexer circuit  106  may also generate the signal DATA with a predetermined null value while receiving the signal MUX — ADD with the default address. 
   The signal EXT — ADD may be implemented as an address signal generated external to the chip  108 . The signal EXT — ADD may have an address range greater than or equal to the N rows of the array  107 . The signal EXT — ADD may include an offset such that a lowest address carried by the signal EXT — ADD may not have a zero value. 
   The signal READ — ENABLE may be implemented as a read enable signal generated external to the chip  108 . The signal READ — ENABLE may have an asserted state to enable reading from the array  107  via the signal EXT — ADD. The signal READ — ENABLE may have a de-asserted state to disable reading from the array  107  via the signal EXT — ADD. 
   The signal DATA may be implemented as a data signal transferring information regarding the one-time programmable cells  102   a–x . The signal DATA may be available external to the chip  108 . The signal DATA may have a width of M-bits that correspond to the M columns of the array  107 . Each bit of the signal DATA may represent a single value or state programmed into a one-time programmable cell  102   a–x  within a row of the array  107  determined by the signal EXT — ADD. 
   The signal MUX — ADD may be implemented as an address signal that controls the multiplexer circuit  106 . The signal MUX — ADD may have an address range equal to or slightly larger than a number of inputs to the multiplexer circuit  106 . Each address conveyed by the signal MUX — ADD may be uniquely associated with one of the N-rows of the array  107 . 
   Each signal A–N may be implemented as a data signal. Each signal A–N may have a width of M-bits that correspond to the M columns of the array  107 . The signal A may be generated and presented by the Ath row of the array  107 . The signal N may be generated and presented by the Nth row of the array  107 . Each of the M bits may transfer a value from one of the one-time programmable cells  102   a–x  in the respective row. 
   Operationally, the circuit  100  may respond to the signals READ — ENABLE and EXT — ADD by generating the signal MUX — ADD. The multiplexer circuit  106  generally multiplexes one of the signals A–N as determined by the signal MUX — ADD to the signal DATA. The signal DATA may then be read external to the circuit  100  to determine the values programmed into the one-time programmable cells  102   a–x  in the requested row of the array  107 . The read values conveyed by the signal DATA may then be used to verify the states of the one-time programmable cells  102   a–x.    
   Referring to  FIG. 3 , a block diagram of a second example embodiment of the circuit  100  is shown. A circuit  100   a  generally comprises an address decoder circuit  104   a , the multiplexer circuit  106 , and the array  107  on the chip  108  connected by the signals EXT — ADD and MUX — ADD as shown in  FIG. 2 . Furthermore, the circuit  100   a  may also comprise an optional driver or buffer  114 , an optional logic gate  116   a , and another driver or buffer  118 . 
   The signal DATA may be provided to an input of the buffer  114 . In turn, the buffer  114  may generate and present a signal (e.g., EXT — DATA) external to the chip  108 . The signal READ — ENABLE may also be received by the buffer  114  to control generation of the signal EXT — DATA. While the signal READ — ENABLE may be in the asserted state, the buffer  114  may present the signal EXT — DATA equal to the signal DATA. While the signal READ — ENABLE may be in the de-asserted state, the buffer  114  may present a high impedance. The buffer  114  may be eliminated from the circuit  100   a  such that the signal DATA may be always available outside the chip  108 . 
   The address decoder circuit  104   a  may receive a signal (e.g., INT — ADD). A signal (e.g., OE 1 ) may be generated and presented by the address decoder circuit  104   a . The signal OE 1  may have the asserted state while the signal INT — ADD conveys an address within an address range allocated to the array  107 . The signal OE 1  may have the de-asserted state while the signal INT — ADD conveys an address outside the address range allocated to the array  107 . 
   The signal OE 1  may be received at a non-inverting input of the logic gate  116   a . An inverting input of the logic gate  116   a  may receive the signal READ — ENABLE. The logic gate  116   a  may generate and present a signal (e.g., OE 2 ) in the asserted state while the signal READ — ENABLE may be de-asserted and the signal OE 1  may be asserted. Otherwise, the signal OE 2  may be in the de-asserted state. The logic gate  116   a  may be eliminated where the signals EXT — ADD and INT — ADD may be guaranteed to be mutually exclusive in accessing the array  107 . 
   The buffer  118  may receive the signal DATA from the multiplexer circuit  106 . The buffer  118  may generate and present a signal (e.g., BUS — DATA). The buffer  118  may receive the signal OE 2  to control generation of the signal BUS — DATA. While the signal OE 2  may be asserted, the buffer  118  may present the signal BUS — DATA equal to the signal DATA to an internal bus  120   a . While the signal OE 2  may be de-asserted, the buffer  118  may present a high impedance to the internal bus  120   a.    
   The address decoder circuit  104   a  generally comprises a first decoder circuit  122 , a second decoder circuit  124  and a multiplexer circuit  126 . The first decoder circuit  122  may decode the signal EXT — ADD to generate an address signal (e.g., ADD 1 ). The second decoder circuit  124  may decode the signal INT — ADD to generate another address signal (e.g., ADD 2 ). The multiplexer circuit  126  may multiplex the signals ADD 1  and ADD 2  to the signal MUX — ADD as controlled by the signal READ — ENABLE. 
   While the signal READ — ENABLE may be asserted, the multiplexer circuit  126  may route the decoded address signal ADD 1  to the signal MUX — ADD. The multiplexer circuit  106  may route the data from the addressed row of the array  107  to the signal DATA. The buffer  114  may then present the values external to the circuit  100   a.    
   While the signal READ — ENABLE may be de-asserted, the multiplexer circuit  126  may route the signal ADD 2  to the signal MUX — ADD. If the signal INT — ADD is generally within an addressable range for the array  107 , the address decoder circuit  104   a  may assert the signal OE 1  and generate an appropriate address in the signal MUX — ADD. The multiplexer  106  may present the requested values from the one-time programmable cells  102   a–x  in the signal DATA. Concurrently, the logic gate  116   a  may assert the signal OE 2  to the buffer  118 . The buffer  118  may thus present the values in the signal DATA to the internal bus  120   a  within the signal BUS — DATA. Therefore, the array  107  may be configured to behave as a one-time programmable ROM. 
   Referring to  FIG. 4 , a block diagram of a third example embodiment of the circuit  100  is shown. A circuit  100   b  generally comprises the address decoder  104   a , the multiplexer circuit  106 , the array  107 , and the buffer  118  on the chip  108  connected by the signals EXT — ADD, INT — ADD, MUX — ADD, DATA, OE 1 , and OE 2  as shown in  FIG. 3 . In addition, the circuit  100   a  may include a logic gate  116   b . The logic circuit  116   b  may be implemented as a logical OR gate that receives the signals READ — ENABLE and OE 1  to generate the signal OE 2 . The buffer  118  may present signal BUS — DATA to a bus  120   b . The bus  120   b  may be implemented as an output bus or a bi-directional input/output bus. The bus  120   b  may be routed external to the chip  108  to make the signal BUS — DATA available for operational and testing purposes. 
   While the signal READ — ENABLE may be in the asserted state, the logic gate  116   b  may assert the signal OE 2 . The asserted signal OE 2  may cause the buffer  118  to present the signal DATA from the multiplexer circuit  106  on the bus  120   b  as the signal BUS — DATA. The signal BUS — DATA may then be available external to the chip  108 . 
   While the signal READ — ENABLE may be in the de-asserted state, the logic gate  116   b  may assert or de-assert the signal OE 2  in response to the signal OE 1 . While the signal OE 1  may be in the de-asserted state, the buffer  118  may present a high impedance to the bus  120   b . While the signal OE 1  may be asserted, the signal OE 2  may be asserted and the buffer  118  may drive the signal DATA onto the bus  120   b.    
   The circuit  100   b  may be used in situations where the chip  108  is generally input/output limited. By sharing the bus  120   b  between operational and testing purposes, the chip  108  may not require dedicated outputs to present the values in the signal DATA during testing. Control of the bus  120   b  for operational or testing use may be determined by the signal READ — ENABLE. Likewise, the signal EXT — ADD may be shared on another input or input/output bus (not shown) to further reduce the I/O pin count for the chip  108 . Other designs may be implemented for getting the signals EXT — ADD and DATA on and off the chip  108  to meet the design criteria of a particular application. 
   Referring to  FIG. 5 , a partial block diagram of a fourth embodiment of the circuit  100  is shown. A circuit  100   c  may include a connection  128  between one or more of the one-time programmable cells  102   a–x  and an identification register  130  of a test scan chain  132 . Generally, the circuits  100 ,  100   a , and  100   b  are isolated and independent of any test scan chain, such as test scan chain  132 . However, in some designs such as the circuit  100   c , some of the one-time programmable cells  102   a–x  may be used to program information that may be accessible through the test scan chain. 
   The test scan chain  132  and the identification register  130  may be defined by the Joint Test Action Group (JTAG) architecture for scan chains. The architecture may be defined by The Institute of Electrical and Electronics Engineering (IEEE) Standard 1149.1-1990, titled “IEEE Standard Test Access Port and Boundary-Scan Architecture”, published by the IEEE, New York, N.Y., hereby incorporated by reference in its entirety. The IEEE 1149.1-2001 standard may specify the identification register  130  as storing a version number, a part number and a manufacturer identification. Other test scan chain architectures and specifications may be implemented to meet the design criteria of a particular application. 
   A predetermined number (e.g., V) of predetermined one-time programmable cells  102   k–p  may be programmed to store some or all of a vendor identification value, part identification value, version identification value, serial number, and/or the like. The connection  128  may transfer the programmed identification information as a signal (e.g., ID) to the identification register  130 . From the identification register  130 , the programmed information in the signal ID may be transferred across the test scan chain  132  to a test access port  134  and then external to the chip  108 . The test access port  134  may interface external to the chip  108  by a test data input signal (e.g., TDI), a test data output signal (e.g., TDO), a test clock signal (e.g., TCK), and a test mode signal (e.g., TMS). As such, the values programmed into the signal ID may be readable from the chip  108  via the test scan chain  132  and the through the circuit  10   c  in the signal DATA. 
   Referring to  FIG. 6 , a flow diagram of a method of producing the circuit  100  is shown. The method may follow conventional fabrication techniques up to and including a step of fabricating a fuse layer for the one-time programmable cells  102   a–x  (e.g., block  136 ). For designs using laser-ablated fuses in the one-time programmable cells  102   a–x , the fuse layer may default all of the one-time programmable or fuse cells  102   a–x  to a closed state. Laser light may then be used to program one or more of the fuse cells  102   a–x  to an open state (e.g., block  138 ). 
   Once the chip  108  has been connected to power, ground and I/O signals have been connected to a tester, a read from the array  107  may be enabled (e.g., block  140 ) by asserting the signal READ — ENABLE and providing an appropriate value in the signal EXT — ADD. The address decoder  104  may then convert the signal EXT — ADD into the signal MUX — ADD (e.g., block  142 ). The multiplexer circuit  106  may respond to the signal MUX — ADD by presenting the signal DATA (e.g., block  144 ). The tester and/or a human may then check the values in the signal DATA to verify programming of the fuse cells  102   a–x  (e.g., block  146 ). 
   If a result of the verification indicates a failure (e.g., the FAIL branch of decision block  148 ), the failed fuse cell or fuse cells  102   a–x  may be reprogrammed with the laser light (e.g., block  150 ). The process may then repeat from enabling reading from the array  107  (e.g., block  140 ) through verification (e.g., block  146 ). Reprogramming and re-verification may be repeated multiple times if necessary or desired. 
   If the result of the verification indicates a success (e.g., the PASS branch of decision block  148 ), the tester may check to see if the last address for the particular test sequence has been reached in signal EXT — ADD (e.g., decision block  152 ). If the last address has not been reached (e.g., the NO branch of decision block  152 ), the address within the signal EXT — ADD may be incremented or changed (e.g., block  154 ). Testing may then continue with the address decoder circuit  104  translating the new signal EXT — ADD (e.g., block  142 ). The address values in the signal EXT — ADD may be repeatedly changed in block  154  until the last tested address has been reached (e.g., the YES branch of decision block  152 ). Thereafter the test sequence may end. 
   Referring to  FIG. 7 , a flow diagram of a method for testing a programmed identification value through the test scan chain  132  is shown. After the appropriate one-time programmable cells  102   k–p  have been written, the test may begin by asserting an identification code command to the test access port  134  (e.g., block  154 ). The test access port  134  may respond to the command by instructing the identification register  130  to load the signal ID in parallel (e.g., block  156 ). The value from the signal ID may then be serially clocked out of the test scan chain  132  and the test access port  134  (e.g., block  158 ). Finally, the tester and/or human may check the identification value to verify proper programming of the appropriate one-time programmable cells  102   k–p  (e.g., block  160 ). 
   The various signals of the present invention are generally “on” (e.g., a digital HIGH, or 1) or “off” (e.g., a digital LOW, or 0). However, the particular polarities of the on (e.g., asserted) and off (e.g., de-asserted) states of the signals may be adjusted (e.g., reversed) accordingly to meet the design criteria of a particular implementation. Additionally, inverters may be added to change a particular polarity of the signals. As used herein, the term “simultaneously” is meant to describe events that share some common time period but the term is not meant to be limited to events that begin at the same point in time, end at the same point in time, or have the same duration. 
   While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.