Abstract:
A high speed latch and compare function providing rapid cache comparison through the use of a dual rail comparison circuit having transmission gate exclusive or (XOR) circuits.

Description:
FIELD OF THE INVENTION 
     The invention described herein relates to microprocessor cache apparatus. 
     BACKGROUND OF THE INVENTION 
     Directory macro&#39;s are microprocessor cache components that are used to determine if a particular address is currently held in the main cache RAM. FIG. 1 (denominated “Prior Art”) shows a typical cache directory RAM scheme. The directory RAM holds a portion of the addresses stored in the main cache RAM. A portion of the full address is used to retrieve and latch an entry from the RAM. Another portion of the address (tag) is then compared against the latched entry from the RAM. If the tag matches the entry retrieved from the RAM, the cache is said to have found a “hit”. 
     FIG. 2 (denominated “Prior Art”) shows the typical logic flow from the RAM output to the generation of the hit signal. A set of bits from the RAM arc compared bit by bit with the corresponding tag bits using an XOR gate. The output of any XOR would be a “1” if the corresponding RAM bit and tag bit mismatched. If none of the XOR gates generate a mismatch, the output of the second stage nor gate will be a “1”, meaning the cache found a hit. The speed at which the cache can operate is directly affected by how long it takes for this compare structure to evaluate. 
     OBJECTS OF THE INVENTION 
     It is a primary object of the invention to provide a minimum delay cache RAM match/mismatch detection circuit. 
     It is a further object of the invention to eliminate the delay associated with complementing of the latched data. 
     It is still a further object of the invention to provide reduced delay XOR logic in the compare function. 
     SUMMARY OF THE INVENTION 
     These objects are attained by the apparatus of our invention. The apparatus of the invention provides a low delay circuit for generating a RAM cache “match/mismatch” signal. 
     Specifically, our invention provides a dual rail output from the RAM and associated latches, typically two latches, one latch to indicate if a “0” was read from the RAM and the other to indicate if a “1” was read from the RAM. In addition to removing the delay associated with generating the complement of the latch data as in the prior art, the use of a transmission gate XOR (instead of the gate input XOR of the prior art) further reduces circuit delay. This combination of eliminating generation of the complement of the latch data and using a transmission gate XOR in place of a gate input XOR provides a low delay compare function. 
     In a preferred exemplification the apparatus has tag and data inputs. The data inputs are dual-rail inputs sourcing latch pairs, where one of the latch pairs latches true-data and one of said latch pairs latches complement-data. The latch and compare apparatus further includes two sets of transistor pairs, one set of the gates receiving data from the true and complement outputs of the true-data latch, and another set of the gates receiving data from the complement and true outputs of the complement-data latch. The transistor pairs hold and drive signals from the latch pairs. The apparatus has a pair XOR transmission gates with one XOR transmission gate transistor pair receiving as gate inputs tag and inverted tag signals, and the other XOR transmission gate pair receiving as gate inputs inverted tag and tag inputs. One of the XOR transmission gate transistor pairs receives a true-data signal, and the other of the XOR transmission gate transistor pairs receives a complement-data signal. The XOR transmission gate pair outputs a match-mismatch signal. 
     In the apparatus the data input may be pairs of true-complement bit column inputs comprising an input for each data bit column, and the tag input may be an input signal comprising an input for each tag bit. 
     The transmission gates are in series with said data inputs, and the latch pairs are in series with the data inputs, with one of the latch pairs latching true-data inputs and one of the latch pairs latching complement-data inputs. 
    
    
     THE FIGURES 
     Various embodiments and exemplifications of our invention are illustrated in the FIGURES appended hereto. 
     FIG. 1 is a high level illustration of a typical cache directory scheme of the prior art, including an address buss with a RAM, a latch, and a compare functionality. 
     FIG. 2 illustrates a typical cache directory scheme of the prior art with data, data latches, tag data, exclusive or (XOR) gates gating the tag data and the latched data, and an NOR gate to generate a “hit.” 
     FIG. 3 illustrates a dual rail comparison circuit of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The invention implements a high speed latch and compare function. The invention, shown in FIG. 3, eliminates significant delay from prior art implementations by using a dual rail/dual latch approach in combination with a transmission gate implementation the XOR function. The invention does not suffer from the charge sharing hazard found in some compare circuits of the prior art and does not include any delay penalty that would be imposed by other prior art implementations. This invention also has the added benefit of removing the delay associated with overpowering the latch feedback inverter in the path from the RAM output to the mismatch node. 
     In the circuit shown in FIG. 3, PMOS transistors PC(n),  301 , and PT(n),  303 , have been replicated as PC(n)_x, also  301 , and PT(n)_x, also  303 . These replicated devices are connected directly the inputs of transmission gates T 1 ,  321 , and T 2 ,  323 . When one of the bit_col_c or bit_col_t signals is pulsed low (following the reset pulse), these replicated transistors drive signals d_t_x and d_c_x directly into transmission gates T 1 ,  321 , and T 2 ,  323 , while transistors PC(n),  301 , and PT(n),  303 , write the data into the latch pair,  331  and  333 . Since the bit_col signals are negative pulses, once they return to a “I”, the d_t_x and d_c_x signals will no longer be driven by the replicated transistors, instead they will be driven (held) by transistor pairs P 4 ,  341 , N 4 ,  343 , and P 5 ,  345 , N 5 ,  347 . The connection of these transistors is such that when the latch pair is in the pre-read state, transistors P 4 -P 5  ( 341 ,  345 ) and N 4 -N 5  ( 343 ,  347 )arc non-conducting. Once the latch pair has been set, they serve to replicate the latch values d_t and d_c on nodes d_t_x and d_c_x. 
     While the invention has been described with respect to certain preferred embodiments and exemplifications, it is not intended to limit the scope of the invention thereby, but solely by the claims appended hereto.