Abstract:
Provided is a computer including a physical computer that includes CPU&#39;s ( 1   a  and  1   b ), a memory ( 5 ), a PCI bus ( 7 ) for interconnecting I/O devices (# 0  to # 3 ), and a south bridge ( 6 ) for controlling the PCI bus ( 7 ), a hypervisor that divides the physical computer into a plurality of LPAR&#39;s and controls resource allocation of the physical computer, an I/O device allocation unit that sets a correlation between the I/O device and the plurality of LPAR&#39;s based on a command from the hypervisor, and a parallel process issuing unit that issues a processing request (for DMA transfer or interruption processing) received from the I/O device in parallel to the plurality of LPAR&#39;s set by the I/O device allocation unit. Thus, complexity of an on-board circuitry is prevented while dynamic changing of an I/O device of a virtual computer is enabled.

Description:
CLAIM OF PRIORITY  
       [0001]     The present application claims priority from Japanese application P2004-122455 filed on Apr. 19, 2004, the content of which is hereby incorporated by reference into this application.  
       BACKGROUND  
       [0002]     This invention relates to a virtual computer system, and more particularly to a technology of dynamically changing allocation of a plurality of logical partitions and I/O devices.  
         [0003]     An increase in the number of servers has been accompanied by an increase in operational complexity, causing a problem of operational costs. Accordingly, server integration that integrates a plurality of servers into one has attracted attention as a technology of reducing operational costs. As a technology of realizing server integration, there has been known a virtual computer that logically divides one computer at an optional ratio. A physical computer is divided into a plurality of logical partitions (LPAR&#39;s) by firmware (or middleware) such as a hypervisor, computer resources (CPU, main memory, and I/O) are allocated to each LPAR, and an OS is operated on each LPAR. The CPU is used in a time-division manner, and thus flexible server integration can be realized.  
         [0004]     As the virtual computer, there has been known a computer that transfers data between an I/O device and an OS on each logical partition by direct memory access (DMA) (e.g., JP 2002-318701 A).  
       SUMMARY  
       [0005]     In the case of realizing the virtual computer on an open server (e.g., blade server or PC server), an I/O device must be shared by a plurality of logical partitions (OS&#39;s on logical partitions) because the open server includes only a small number of I/O devices to be mounted. The sharing of the I/O device necessitates DMA transfer between the I/O device and the OS on each logical partition, or transmission of an I/O interruption from the I/O device to the sharing OS&#39;s.  
         [0006]     However, in the conventional example, DMA transfer to a logical partition other than that allocated to the I/O device is inhibited. Thus, as the I/O device can always notify only one logical partition, a plurality of OS&#39;s cannot share one I/O device, causing a problem of a shortage of I/O devices allocated to the OS&#39;s.  
         [0007]     This invention has been made in view of the aforementioned problem, and it is therefore an object of this invention to realize a virtual computer on an open server by allowing OS&#39;s on a plurality of logical partitions to share one I/O device.  
         [0008]     According to an embodiment of this invention, there is provided a computer including: a physical computer that includes a CPU, a main memory, an I/O bus connecting an I/O device, and an I/O control unit controlling the I/O bus; firmware (a hypervisor) that divides the physical computer into a plurality of logical partitions, operates an OS on each logical partition, and controls resource allocation of the physical computer to each logical partition; an I/O device allocation unit that sets a correlation between the I/O device and the plurality of logical partitions based on a command from the firmware; a processing request reception unit that receives a processing request (for DMA transfer or interruption processing) from the I/O device; and a parallel process issuing unit that issues the received processing request in parallel to the plurality of logical partitions set by the I/O device allocation unit.  
         [0009]     Thus, according to this invention, by setting the correlation between each I/O device and the plurality of logical partitions, it is possible to issue the processing request from the I/O device in parallel to the plurality of logical partitions. Accordingly, when one I/O device is shared by the plurality of logical partitions, the processing request of the I/O device can be issued only to the logical partition which needs the request. As a result, it is possible to realize a virtual computer even on the open server which includes only a small number of I/O devices. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]      FIG. 1  is a system diagram showing a configuration of a physical computer according to a first embodiment of this invention.  
         [0011]      FIG. 2  is a system diagram showing a software configuration of a virtual computer operated on the physical computer.  
         [0012]      FIG. 3  is a system diagram showing a south bridge in which a DMA control unit is a center.  
         [0013]      FIG. 4  is an explanatory diagram showing an example of a device register.  
         [0014]      FIG. 5  is an explanatory diagram showing an example of a parallel transfer register.  
         [0015]      FIG. 6  is a system diagram showing an example of an I/O device.  
         [0016]      FIG. 7  is a diagram showing an example of DMA transaction.  
         [0017]      FIG. 8  is a diagram showing a relation among a physical address space, a logical address space of each LPAR, and a DMA buffer.  
         [0018]      FIG. 9  is a system diagram showing a south bridge in which an interruption control unit is a center according to a second embodiment of this invention.  
         [0019]      FIG. 10  is a system diagram showing an example of an I/O device according to the second embodiment.  
         [0020]      FIG. 11  is an explanatory diagram showing an example of a parallel interruption register according to the second embodiment.  
         [0021]      FIG. 12  is a flowchart showing an example of a share setting process carried out by a hypervisor according to the second embodiment.  
         [0022]      FIG. 13  is a time chart showing a flow of an interruption process from the I/O device according to the second embodiment.  
         [0023]      FIG. 14  is a system diagram showing an example of a hardware configuration of interruption process completion notification according to the second embodiment.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0024]     Hereinafter, the preferred embodiments of this invention will be described with reference to the accompanying drawings.  
         [0025]     &lt;First Embodiment&gt; 
         [0026]      FIG. 1  shows a configuration of a physical computer (open server)  100  for operating a virtual computer system according to a first embodiment of this invention. CPU&#39;s  1   a  and  1   b  are connected through a front side bus  2  to a north bridge  3 .  
         [0027]     The north bridge  3  is connected through a memory bus  4  to a memory (main memory)  5 , and connected through a bus  8  to a south bridge  6 . A PCI bus  7 , a legacy device (not shown), and a disk interface (not shown) are connected to the south bridge  6 , which can be accessed from the CPU&#39;s  1   a  and  1   b.  It should be noted that the south bridge  6  only needs to be a controller for controlling an I/O bus of a PCI bus  9  or the like, and the north bridge  3  only needs to be a controller for controlling the memory  5 .  
         [0028]     The PCI bus (I/O bus)  7  includes a data bus, an address bus, and a signal line of an interruption signal or the like (not shown), and is shared by PCI slots # 0  to # 3  ( 10  to  13  in the drawing).  
         [0029]     I/O devices # 0  to # 2  ( 20  to  22  in the drawing) are connected to the PCI slots # 0  to # 3 , respectively.  
         [0030]     The number of CPU&#39;s constituting the physical computer  100  may be one, or two or more. When the number of CPU&#39;s is two or more, the CPU&#39;s  1   a  and  1   b  are tightly coupled multiprocessors which share the memory  5 .  
         [0031]     Now, referring to  FIG. 2 , software for realizing a virtual computer on the physical computer  100  will be described in detail.  
         [0032]     A hypervisor  200  (firmware or middleware) is operated on the physical computer  100 . The hypervisor  200  divides the physical computer  100  into two or more logical partitions (LPAR&#39;s) LPAR  0  ( 210 ) to LPAR m ( 21   m ), and manages allocation of computer resources.  
         [0033]     OS  0  ( 220 ) to OS m ( 22   m ) are operated on the LPAR  0  to LPAR m, and applications  0  ( 230 ) to m (   23   m) are operated on the OS&#39;s.  
         [0034]     The hypervisor  200  allocates resources (computer resources) of the CPU&#39;s  1   a  and  1   b,  the memory  5 , and the I/O devices # 0  to # 2  of the PCI slots # 0  to # 3  (computer resources) of the physical computer  100  to the LPAR&#39;s ( 210  to  21   m ). The hypervisor  200  can allocate a plurality of OS&#39;s ( 220  to  22   m ) to one I/O device. In other words, the I/O devices # 0  to # 3  are constituted so that they can be shared by the plurality of LPAR&#39;s  0  to m.  
         [0035]     Further, when executing DMA transfer between each of the I/O devices # 0  to # 3  and each of the OS&#39;s  0  to m ( 220  to  22   m ), the hypervisor  200  sets DMA transfer on the south bridge  6  at the time of booting each of the OS&#39;s  0  to m (described later).  
         [0036]     The DMA transfer is realized in a manner that the south bridge  6  executes writing in a predetermined area of the memory  5  through the north bridge  3  in response to DMA transfer requests from the I/O devices # 0  to # 3 .  
         [0037]     Hereinafter, this embodiment will be described by way of case in which the plurality of OS&#39;s share one I/O device and the south bridge  6  controls DMA transfer. The description below refers to a case in which two LPAR&#39;s  0  and  1  share one I/O device # 0 . However, this invention can be similarly applied to a case in which two or more OS&#39;s share the other I/O device.  
         [0038]      FIG. 3  is a system diagram of the south bridge  6  in which a DMA control unit  62  is a center. The south bridge  6  includes an interface  61  for connecting the south bridge  6  to the north bridge  3  on the CPU side, a PCI bus interface  60  connected to the PCI bus  7 , and the DMA control unit  62  for writing data in the memory  5  in response to DMA transfer requests from the I/O devices # 0  to # 3  shown in  FIG. 1 .  
         [0039]     Here, provided in the DMA control unit  62  is a parallel control unit  63  for distributing (parallelizing) DMA transfer to a plurality of OS&#39;s (LPAR&#39;s) from one I/O device in response to a command from the hypervisor  200 .  
         [0040]     The parallel control unit  63  includes a device register  610  for setting sharing of the I/O devices # 0  to # 3 , and a parallel transfer register  620  provided to each I/O device for indicating a share LPAR and a DMA buffer address of each LPAR. When a DMA transfer request comes from the shared I/O device, DMA transfer is carried out to a plurality of addresses of the memory  5  indicated by the parallel transfer register  620 .  
         [0041]     Referring to  FIG. 4 , device registers  610  are set by a number equal to the number of I/O devices # 0  to # 3 , and include a parallelization flag  612  indicating whether or not to execute DMA transfer in parallel to the plurality of LPAR&#39;s corresponding to a device number  611 , and an issuer ID of an I/O device. “1” of the parallelization flag Fp indicates that parallel DMA transfer is executed, while “0” thereof indicates that parallel DMA transfer is not executed. The issuer ID indicates an ID on the PCI bus  7  of the I/O device, and it is information containing a bus number, a device number, and a function number defined by PCI Local Bus Specification Rev. 2.2 or the like.  
         [0042]     Next referring to  FIG. 5 , the parallel transfer register  620  includes registers independent for the I/O devices # 0  to # 3 . Corresponding to an LPAR number  621  set by the hypervisor  200 , a share flag  622  indicating presence/absence of sharing and an address offset value  623  of a transfer destination are set for each LPAR number  624 .  
         [0043]     In  FIG. 5 , reference numeral  620  indicates an example of the parallel transfer register  620  of the I/O device # 0 , and share flags of the LPAR&#39;s  0  and  1  set to 1, thereby indicating that the I/O device # 0  is shared by the two LPAR&#39;s  0  and  1 . The address offset value  623  of the transfer destination indicates that a DMA buffer address of the I/O device # 0  of the LPAR  0  is C-A′, and a DMA buffer address of the I/O device # 0  of the LPAR  1  is C-B′-L 1st. The L 1st represents a start physical address of the LPAR  1 . A start physical address of the LPAR  0  is 0h, and a logical address space and a physical address space coincide with each other.  
         [0044]     Next, referring to  FIG. 6 , the I/O device # 0  includes a PCI bus interface  201 , a device interface  202 , an I/O device main body  203 , and a DMA controller  204 . For example, when the I/O device # 0  is a network interface card (NIC), upon occurrence of reception, the DMA controller  204  issues to the south bridge  6  a DMA transaction for transferring reception data.  
         [0045]     For example, the DMA transaction  300  is structured as shown in  FIG. 7 . A header  301  includes request contents (TYPE in the drawing)  302 , a transfer destination address  303 , and an issuer ID  304 . Data  305  is added to the end of the header  301 .  
         [0046]     For the transfer destination address  303 , a hypervisor DMA buffer address (C in the drawing) set by the hypervisor  200  is set at the time of booting the physical computer  100 . The transfer destination address  303  is set in a DMA register (not shown) of the DMA controller  204 . The issuer ID  304  is the same as an issuer ID  613  of the device register  610 .  
         [0047]     Now, referring to  FIG. 8 , a relation among a memory space of the OS  0  of the LPAR  9  set in the memory  5 , a memory space of the OS  1  of the LPAR  1 , and the hypervisor DMA buffer will be described.  
         [0048]     The memory  5  includes physical addresses 0 to 10 GB. Among those, an address space (area) of 0 to 4 GB is allocated to the OS  0 , an address space of 4 GB to 8 GB is allocated to the OS  1 , and an address space of 2 MB from a physical address C of 8 GB or more is allocated to a hypervisor DMA buffer  50 .  
         [0049]     The physical address space allocated to the OS  0  of the LPAR  0  is used as a logical address space  5 A of 0 to 4 GB by the OS  0 , and a DMA buffer  51  for the OS  0  is secured in an address space of 2 MB from a logical address A at the time of booting the OS  0 . The DMA buffer  51  corresponds to the I/O device # 0 .  
         [0050]     On the other hand, the physical address space of 4 to 8 GB allocated to the OS  1  of the LPAR  1  is used as a logical address space  5 B of 0 to 4 GB by the OS  1 , and a DMA buffer  52  for the OS  1  is secured in an address space of 2 MB from a logical address B at the time of booting the OS  1 . The DMA buffer  52  corresponds to the I/O device # 0 .  
         [0051]     Here, the hypervisor  200  that manages physical addresses manages physical addresses A′ and B′ of the OS DMA buffers  51  and  52  from the DMA buffers  51  and  52  secured by the OS&#39;s  0  and  1 , respectively.  
         [0052]     Next, an example of sharing the I/O device # 0  by the OS&#39;s  0  and  1  of the LPAR&#39;s  0  and  1  and executing DMA transfer will be described.  
         [0053]     Upon bootup of the OS&#39;s  0  and  1 , the DMA buffers  51  and  52  are secured as described above, respectively, and the OS&#39;s  0  and  1  request the hypervisor  200  to allocate the I/O device # 0  and to execute DMA transfer.  
         [0054]     Since the plurality of OS&#39;s have requested the DMA transfer of the I/O device # 0 , the hypervisor  200  sets 1 as the parallelization flag of a device number  0  (I/O device # 0 ) of the device register  610  of  FIG. 4 , reads an issuer ID from the PCI bus interface  201  of the I/O device # 0 , and sets the ID to the issuer ID of the device register  610 . At the time of booting the physical computer  100 , as described above, the address C of the hypervisor DMA buffer  50  is set as a DMA transfer address of the I/O device # 0  in the DMA controller  204 .  
         [0055]     Next, to execute parallel DMA transfer between the I/O device # 0  and the OS&#39;s  0  and  1 , the hypervisor  200  sets  1  as the share flags of the LPAR&#39;s  0  and  1  of the parallel transfer register  620  of the I/O device # 0 . Then, the hypervisor  200  sets offset of a hypervisor DMA buffer address C and a physical address A′ of the DMA buffer  51  for the OS  0  (C−A′=C−A) in the transfer destination address offset value  623  of the parallel transfer register  620 .  
         [0056]     Similarly, the hypervisor  200  sets offset of the hypervisor DMA buffer address C and a physical address B′ of the DMA buffer  52  for the OS  1  (C−B′=C−B−L 1st) as the transfer destination address offset value  623  of the parallel transfer register  620  of the I/O device # 0 .  
         [0057]     When DMA transaction  300  occurs from the I/O device # 0  upon completion of the bootup, a header  301  and data  305  of TYPE (=MWr=memory write request) similar to that shown in  FIG. 7  are sent from the I/O device # 0  to the south bridge  6 .  
         [0058]     The DMA control unit  62  extracts an issuer ID  304  from the header  301 , and compares the ID with the issuer ID of the device register  610  to determine that a DMA transfer source is the I/O device # 0 . Determination is simultaneously made as to whether the parallelization flag is 1 or not. Parallel transfer is executed as described below when the flag is 1. When the flat is 0, parallel transfer is not executed, while data is transferred to the transfer destination address (i.e., hypervisor DMA buffer address)  303  described in the header  301  of the DMA transaction  300 .  
         [0059]     When the parallelization flag is 1, the DMA control unit  62  refers to the I/O device # 0  of the parallel transfer register  620  to retrieve an LPAR in which a share flag is set to 1. Then, in  FIG. 5 , since the share flag is set in the LPAR  0 , the transfer address offset value (C−A′) is read, and this offset value is subtracted from the transfer address  303  (=C) extracted from the DMA transaction  300 . The transfer destination address of the DMA transaction  300  is the hypervisor DMA buffer address C as described above. Accordingly, referring to  FIG. 8 , an obtained address is C−(C−A′)=A′, whereby an address A′ of a DMA buffer  51 ′ corresponding to the physical address space of the LPAR  0  is obtained.  
         [0060]     The DMA control unit  62  transfers the data  305  of the DMA transaction  300  to the physical address A′ of the memory  5 , and writes data in the DMA buffer  51  for the OS  0 .  
         [0061]     The DMA control unit  62  further searches in the parallel transfer register  620 , reads a transfer destination address offset value (C−B′) since the share flag has been set in the LPAR  1 , and subtracts this offset value from the transfer destination address  303  (=C) extracted from the DMA transaction  300 . Similarly to the above, since the transfer destination address of the DMA transaction  300  is the hypervisor DMA buffer address C as described above, an obtained address is C−(C−B′)=B′, whereby an address B′ of a DMA buffer  52 ′ corresponding to the physical address space of the LPAR  1  is obtained.  
         [0062]     The DMA control unit  62  transfers the data  305  of the DMA transaction  300  to the physical address B′ of the memory  5 , and writes data in the DMA buffer  52  for the OS  1 .  
         [0063]     Accordingly, the DMA control unit  62  sequentially transfers data to the physical address defined by subtracting the offset value from the address indicated by the DMA transaction  300  in the LPAR in which the share flag of the parallel transfer register  620  has been set, whereby the DMA transfer request can be written in parallel in the plurality of LPAR&#39;s from one I/O device.  
         [0064]     Thus, even on the open server having a small number of I/ 0  devices, it is possible to realize a virtual computer which includes a plurality of LPAR&#39;s by sharing an I/O device. As a result, the number of servers can be reduced.  
         [0065]     Furthermore, the DMA transaction  300  of the I/O devices # 0  to # 3  of the PCI bus  7  is parallelized in the south bridge  6 . Thus, the I/O device can be shared by the plurality of OS&#39;s by parallelizing DMA transfer while preventing an increase in data traffic of the PCI bus  7 .  
         [0066]     This embodiment has been described by way of example in which the parallel control unit  63  is disposed in the south bridge  6 . However, the parallel control unit  63  may be disposed in the north bridge  3  (not shown).  
         [0067]     &lt;Modified Example 1&gt; 
         [0068]     According to a first modified example, the parallel control unit  63  is disposed in the south bridge  6 . However, a parallel transfer register  620  may be disposed in the DMA controller  204  of the I/O devices # 0  to # 3  shown in  FIG. 6 , and the DMA transaction  300  from the I/O devices # 0  to # 3  may be parallelized.  
         [0069]     In this case, the parallel transfer register  620  may be disposed for each of the I/O devices # 0  to # 3 , and the south bridge  6  only needs to include the DMA control unit  62  similar to that of the conventional case. Then, a hypervisor  200  accesses the parallel transfer register  620  of each of the I/O devices # 0  to # 3  to set a share flag  622  and the offset value  623 .  
         [0070]     When DMA transfer occurs at the I/O devices # 0  to # 3 , the DMA transfer is executed with respect to a plurality of OS&#39;s (CPU&#39;s) in accordance with the offset value  620  of the parallel transfer registers  620  of the I/O devices # 0  to # 3 .  
         [0071]     Thus, as in the case of the first embodiment, sharing of the I/O devices # 0  to # 3  by the plurality of OS&#39;s (LPAR&#39;s) can be realized. In this case, since the parallel transfer register  620  is disposed on the I/O device side, the device register  610  is made unnecessary, thereby simplifying a configuration.  
         [0072]     &lt;Second Embodiment&gt; 
         [0073]     FIGS.  9  to  14  show a second embodiment, showing an example in which the south bridge  6  of the first embodiment includes an interruption control unit  64  for notifying OS&#39;s on a plurality of LPAR&#39;s sharing an I/O device of I/O interruption (external interruption) from I/O devices # 0  to # 3 .  
         [0074]      FIG. 9  is a system diagram showing the south bridge  6  of the first embodiment in which the interruption control unit  64  for notifying the plurality of OS&#39;s (CPU&#39;s  1   a  and  1   b ) of interruption requests (interruption signals) from the I/O devices # 0  to # 3 .  
         [0075]     The south bridge  6  includes an interface  61  for connecting the south bridge  6  to the north bridge  3  of the CPU side, the PCI bus interface  60  connected to the PCI bus  7 , and the interruption control unit  64  for notifying the CPU&#39;s  1   a  and  1   b  of interruption in accordance with I/O interruption from the I/O devices # 0  to # 3  shown in  FIG. 1 .  
         [0076]     Referring to  FIG. 10 , each of the I/ 0  devices # 0  to # 3  includes a PCI bus interface  201 , a device interface  202 , an I/O device main body  203 , a DMA controller  204 , and an interruption controller  205 . For example, when the I/O device # 0  is a network interface card (NIC), upon occurrence of reception, the interruption controller  205  issues to the south bridge  6  an interruption signal for notifying I/O interruption.  
         [0077]     Other components are similar to those of the first embodiment, and thus description thereof will be omitted to avoid repetition.  
         [0078]     Here, provided in the interruption control unit  64  of the south bridge  6  is a parallel interruption register  640  for distributing (parallelizing) I/O interruption from one I/O device to a plurality of OS&#39;s (CPU&#39;s) in response to a command from a hypervisor  200 .  
         [0079]     Next, referring to  FIG. 11 , the parallel interruption register  640  includes registers independent for the I/O devices # 0  to # 3 . Corresponding to an LPAR number  641  set by the hypervisor  200 , a share flag  642  indicating presence/absence of sharing, a CPU identifier  643  indicating an address of interruption notification, and an area for storing an end-of-interrupt (EOI) flag  644  indicating interruption processing completion notification from the CPU are set for each LPAR number  641 .  
         [0080]     In  FIG. 11 , reference numeral  640  indicates an example of a parallel interruption register  640  of the I/O device # 0 , and the share flags  642  of the LPAR  0  and the LPAR  1  are set to “1”, indicating that the I/O device # 0  is shared by the two LPAR&#39;s  0  and  1 .  
         [0081]     When the CPU  1   a  (CPU # 0  of  FIG. 1 ) is allocated to the LPAR  0  and the CPU  1   b  (CPU # 1  of  FIG. 1 ) is allocated to the LPAR  1 , in the parallel interruption register  640 , # 0  shown in  FIG. 1  is set in a CPU identifier  643  of the LPAR  0 , and # 1  shown in  FIG. 1  is set in a CPU identifier  643  of the LPAR  1 .  
         [0082]     Further, since there is no interruption processing completion notification at present, “0” is set in EOI flags  644  of the LPAR&#39;s  0  and  1 . When the CPU allocated to the LPAR notifies completion of interruption processing, the EOI flags  644  are changed to  1 . The EOI flag  644  is reset to “0” by the interruption control unit  64  each time I/O interruption occurs.  
         [0083]     Next, an example of sharing the I/O device # 0  by the LPAR&#39;s  0  and  1  and parallelizing and notifying I/O interruption by the south bridge  6  will be described.  
         [0084]     First, a flowchart of  FIG. 12  will be used to describe a setting process of parallel interruption executed by the hypervisor  200  executed by the physical computer  100  each time the OS is booted on the LPAR.  
         [0085]     The hypervisor  200  decides an LPAR and a CPU for booting an OS (S 1 ), and selects I/O devices to be allocated to this OS (LPAR) (S 2 ). Next, the parallel interruption register  640  corresponding to the selected I/O devices # 0  to # 3  is read from the south bridge  6  (S 3 ), and determination is made as to whether or not to share with other LPAR by referring to a share flag (S 4 ). This determination may be made by referring to a parallelization flag  612  of a device register  610  disposed in the south bridge  6  as in the case of the first embodiment.  
         [0086]     In the case of no sharing, the process proceeds to a step S 6  to boot an OS (guest OS). In the case of sharing, the share flag  642  corresponding to the LPAR for booting the OS is set to “1”, and share flags of sharing LPAR&#39;s are set to “1”. Then, an identifier  643  of a CPU allocated to each LPAR is set (S 5 ).  
         [0087]     After the parallel interruption register  640  of the south bridge  6  has been set, the guest OS is booted (S 6 ).  
         [0088]     An interruption controller  205  of the I/O devices # 0  to # 3  is initialized at the time of booting the physical computer  100 , and an interruption number is set in the interruption controller  205 .  
         [0089]     Next, referring to a time chart of  FIG. 13 , a process from I/O interruption to completion notification will be described.  
         [0090]     When I/O interruption occurs, the I/O device sends an interruption signal corresponding to an interruption number to the interruption control unit  64  of the south bridge  6  (t 1 ).  
         [0091]     Upon reception of the interruption signal from the I/O device, the interruption control unit  64  of the south bridge  6  specifies an I/O device from an interruption identifier. Then, determination is made as to sharing by referring to a share flag  642  of the parallel interruption register  640  corresponding to the specified I/O device. When sharing is not determined, a predetermined CPU (e.g., CPU  1   a ) is notified of I/O interruption.  
         [0092]     On the other hand, when sharing is determined, I/O interruption notification is executed for all CPU identifiers  643  of destinations set in the parallel interruption register  640  (t 2 ). In the example of  FIG. 11 , the CPU&#39;s  1   a  and  1   b  of the LPAR&#39;s  0  and  1  is notified of the I/O interruption. At this time, the interruption control unit  64  sets the EOI flags  644  of the LPAR&#39;s  0  and  1  to “0”.  
         [0093]     Each of the CPU&#39;s # 0  and # 1  that have received the notification starts interruption processing (t 3 ). For example, when the CPU # 0  first completes interruption processing, the CPU # 0  notifies the interruption control unit  64  of the south bridge  6  of the interruption processing completion (EOI # 0 ) (t 4 ). The interruption control unit  64  that has received the notification sets “1” as an EOI flag having the notified CPU identifier from among the EOI flags  644  of the parallel interruption register  640  (t 5 ).  
         [0094]     At this time, the CPU # 1  is executing interruption processing. Since the EOI flag  644  corresponding to the CPU # 1  is “0”, the interruption control unit  64  withholds notification of I/O interruption processing completion to the I/O device.  
         [0095]     Upon completion of the interruption processing, the CPU # 1  notifies the interruption control unit  64  of the south bridge  6  of the interruption processing completion (EOI # 1 ) (t 6 ). The interruption control unit  64  that has received the notification sets “1” as an EOI flag of the CPU # 1  that has received the notification from among the EOI flags  644  of the parallel interruption register  640  (t 5 ).  
         [0096]     At this time, all EOI flags become “1” for the LPAR whose share flag  642  is set in the parallel interruption register  640  shown in  FIG. 11 . Thus, after determining completion of interruption processing at all the CPU&#39;s (or OS&#39;s), the interruption control unit  64  transmits an interruption processing completion notification EOI to the I/O device of the issuer.  
         [0097]     The determination of the interruption processing completion notification for each CPU at the interruption control unit  64  can be made by hardware similar to that shown in  FIG. 14 .  
         [0098]     Referring to  FIG. 14 , an adder  651  outputs a result of adding together values of the EOI flags  644  of the parallel interruption register  640 , and an adder  652  outputs a result of adding together values of the share flags  642  of the parallel interruption register  640 . ON is output through a gate  653  when values of the adders  651  and  652  coincide with each other.  
         [0099]     On the other hand, ON is output through a gate  654  when any one of the share flags  642  is “1”. When signals of the gates  654  and  653  are both ON, the interruption processing completion notification EOI is transmitted through a gate  655  to the I/O device.  
         [0100]     Accordingly, in the case of LPAR in which the share flag  642  has been set, EOI flags  644  of all the LPAR&#39;s become “1”, and the interruption control unit  64  sends the interruption processing completion notification EOI to the I/O device for the first time. It should be noted that the gate  654  prevents transmission of EOI by the interruption control unit  64  when the share flags  642  and the EOI flags  644  are all 0.  
         [0101]     Thus, the interruption control unit  64  can notify the CPU&#39;s (OS&#39;s) of the LPAR&#39;s, in which the share flags  642  of the parallel interruption register  640  have been set, of I/O interruption in parallel, and one I/O device can be shared by the plurality of LPAR&#39;s.  
         [0102]     As a result, even on the open server (blade or PC server) having a small number of I/O devices, by sharing the I/O device, a virtual computer equipped with a plurality of LPAR&#39;s can be realized, thereby reducing the number of servers.  
         [0103]     The second embodiment has been described by way of example in which the interruption control unit  64  is disposed in the south bridge  6 . However, the interruption control unit  64  may be disposed in the north bridge  3  (not shown).  
         [0104]     &lt;Modified Example 2&gt; 
         [0105]     According to a second modified example, the interruption control unit  64  is disposed in the south bridge  6 . However, a parallel interruption register  640  may be disposed in the interruption controller  205  of the I/O devices # 0  to # 3  shown in  FIG. 10 , and interruption signals from the I/O devices # 0  to # 3  may be parallelized.  
         [0106]     In this case, the parallel interruption register  640  may be disposed for each of the I/O devices # 0  to # 3 , and the south bridge  6  only needs to include an interruption control unit  64  similar to that of the conventional case. Then, a hypervisor  200  accesses the parallel interruption register of each of the I/O devices # 0  to # 3  to set a share flag  642 , a destination CPU identifier  643 , and an EOI flag  644 .  
         [0107]     When I/O interruption occurs at the I/O devices # 0  to # 3 , to a plurality of OS&#39;s (CPU&#39;s) are notified of the I/O interruption in accordance with destination CPU&#39;s of the parallel interruption registers  640  of the I/O devices # 0  to # 3 .  
         [0108]     Each time interruption processing is completed at the CPU&#39;s, the EOI flags  644  sequentially become “1”. When EOI flags  644  of all LPAR&#39;s in which the share flags  642  of the parallel interruption register  640  have been set become 1, an interruption controller  205  notifies the I/O device of interruption processing completion.  
         [0109]     Thus, as in the case of the second embodiment, sharing of the I/O devices # 0  to # 3  by the plurality of OS&#39;s (LPAR&#39;s) can be realized.  
         [0110]     According to each of the embodiments, the front side bus  2  is the share bus. However, the front side bus may be a point-to-point crossbar type bus, and the north and south bridges  3  and  6  can be similarly interconnected through the crossbar type bus. Moreover, the memory bus  4  is connected to the north bridge  3 . However, a configuration may be employed in which the memory bus is connected to the CPU&#39;s  1   a  and  1   b.    
         [0111]     Furthermore, each of the embodiments is directed to the example of the physical computer  100  equipped with one PCI bus. However, this invention can be applied to a physical computer equipped with a plurality of I/O buses (not shown), and to a physical computer equipped with a plurality of different I/O buses.  
         [0112]     As described above, according to this invention, DMA transfer or I/O interruption from the I/O device can be executed in parallel to the plurality of LPAR&#39;s. Thus, it is possible to provide a physical computer (server or personal computer) optimal for realizing virtual computers which share an I/O device.  
         [0113]     While the present invention has been described in detail and pictorially in the accompanying drawings, the present invention is not limited to such detail but covers various obvious modifications and equivalent arrangements, which fall within the purview of the appended claims.