Abstract:
Provided is a semiconductor device capable of suppressing latch-up generation and formed within a small area. In a minority carrier capture region, a P-type diffusion region ( 22 ), an N-type well ( 24 ), and a P-type diffusion region ( 25 ) are formed on a surface of a P-type semiconductor substrate ( 27 ). An N-type diffusion region ( 23 ) is formed on a surface of the N-type well ( 24 ). And the N-type well ( 24 ) is located between the P-type diffusion region ( 22 ) and the P-type diffusion region ( 25 ). The P-type diffusion region ( 22 ) and the P-type diffusion region ( 25 ) are each connected to a ground pad ( 12 ) not by the shortest distance but respectively through metal film wirings arranged in a diverted way.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a semiconductor device, and more specifically, to a semiconductor device capable of suppressing latch-up generation. 
         [0003]    2. Description of the Related Art 
         [0004]    First, a related art semiconductor device is described.  FIG. 5  is a sectional view illustrating the related art semiconductor device. 
         [0005]    When a negative voltage surge is applied to an input pad  71 , electrons serving as minority carriers in a P-type semiconductor substrate  87  may leak from an N-type diffusion region  81  in an ESD protection circuit region to the P-type semiconductor substrate  87 . From the semiconductor substrate  87  into a P-type diffusion region  82  connected to a ground pad  72  the minority carriers flow and are absorbed. A horizontal length of the P-type diffusion region  82  in a direction from the ESD protection circuit to an internal circuit is sufficiently large, and hence the minority carriers are sufficiently absorbed into the P-type diffusion region  82 . The minority carriers that are not absorbed into the P-type diffusion region  82  are forcibly drawn out from the semiconductor substrate  87  into an N-type diffusion region  83  connected to a power supply pad  73 . The minority carriers caused by the surge to the input pad  71  are a main cause of occurrence of latch-up in the internal circuit. As described above, the minority carriers are released from the semiconductor substrate  87 , with the result that the latch-up in the internal circuit is not liable to be caused (see, for example, Japanese Published Patent Application No. 2007-019345). 
         [0006]    However, in the technology disclosed in Japanese Published Patent Application No. 2007-019345, the horizontal length of the P-type diffusion region  82  in the direction from the ESD protection circuit to the internal circuit is large, and along therewith, the area of the semiconductor device becomes larger. 
       SUMMARY OF THE INVENTION 
       [0007]    The present invention has been made in view of the above-mentioned problem, and provides a semiconductor device capable of suppressing occurrence of latch-up with a small area. 
         [0008]    In order to solve the above-mentioned problem, according to one embodiment of the present invention, there is provided a semiconductor device including: a drain as a diffusion region that is connected to a pad; a region of an internal circuit; and a minority carrier capture region formed between the drain and the region of the internal circuit, for capturing minority carriers caused by a surge to the pad, the minority carrier capture region including a triple guard ring including: a first P-type diffusion region; a second P-type diffusion region; and an N-type diffusion region that is located between the first P-type diffusion region and the second P-type diffusion region. The first P-type diffusion region and the second P-type diffusion region are each connected to aground pad not by the shortest distance but detoured respectively through metal film wirings. The N-type diffusion region is connected to a power supply pad. 
         [0009]    According to the present invention, in the triple guard ring, the N-type diffusion region having a positive power supply potential is located between the P-type diffusion regions having a ground potential, and hence the occurrence of latch-up in the internal circuit is suppressed even when the length of the P-type diffusion region is small in a direction from an ESD protection circuit to the internal circuit. Accordingly, it is possible to reduce the area of the semiconductor device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    In the accompanying drawings: 
           [0011]      FIG. 1  is a sectional view illustrating a semiconductor device; 
           [0012]      FIG. 2  is a plan view illustrating the semiconductor device; 
           [0013]      FIG. 3  is a sectional view illustrating a semiconductor device; 
           [0014]      FIG. 4  is a sectional view illustrating a semiconductor device; and 
           [0015]      FIG. 5  is a sectional view illustrating a related art semiconductor device. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0016]    Now, embodiments of the present invention are described with reference to the accompanying drawings. First, a structure of a semiconductor device is described.  FIG. 1  is a sectional view illustrating the semiconductor device, and  FIG. 2  is a plan view illustrating the semiconductor device. 
         [0017]    As illustrated in  FIG. 1 , a semiconductor substrate  27  includes three regions, specifically, a region of an ESD protection circuit for protecting the semiconductor device from ESD, a region of an internal circuit, and a minority carrier capture region for capturing minority carriers in the semiconductor substrate  27  caused by a negative voltage surge to a pad  11  for input or output. The minority carrier capture region surrounds the region of the internal circuit to generally form a guard ring. The pad  11  for input or output, a ground pad  12 , a power supply pad  13 , and the protection circuit are basically formed outside the guard ring. 
         [0018]    In the region of the ESD protection circuit, an N-type diffusion region  21  is formed on a surface of the P-type semiconductor substrate  27 . In general, the N-type diffusion region  21  serves as a drain of an NMOS transistor that functions as the ESD protection circuit for protecting the semiconductor device from the ESD. The drain (N-type diffusion region  21 ) is connected to the pad  11 . Although not illustrated, a source and a gate of the NMOS transistor are connected to the ground pad  12 , and the drain is connected to the pad  11 . Consequently, the NMOS transistor functions as the ESD protection circuit. Further, as another structure, the N-type diffusion region  21  may serve as a cathode of a protective diode. 
         [0019]    In the region of the internal circuit, an N-type well  26  is formed on the surface of the P-type semiconductor substrate  27 . Although not illustrated, a P-type diffusion region is formed on a surface of the N-type well  26 . The P-type diffusion region serves as a source and a drain of a PMOS transistor. Although not illustrated, an N-type diffusion region is formed on the surface of the P-type semiconductor substrate  27 . The N-type diffusion region serves as a source and a drain of an NMOS transistor. 
         [0020]    In the minority carrier capture region, a P-type diffusion region  22 , an N-type well  24 , and a P-type diffusion region  25  are formed on the surface of the P-type semiconductor substrate  27 . An N-type diffusion region  23  is formed on a surface of the N-type well  24 . In this case, the N-type well  24  is located between the P-type diffusion region  22  and the P-type diffusion region  25 . The P-type diffusion region  22 , the P-type diffusion region  25 , and the N-type diffusion region  23  inside the N-type well  24  form a triple guard ring between the drain (N-type diffusion region  21 ) and the region of the internal circuit. The P-type diffusion region  22  and the P-type diffusion region  25  are each connected to the ground pad  12 , and the N-type diffusion region  23  is connected to the power supply pad  13 . 
         [0021]      FIG. 2  illustrates an example of a method of arranging the P-type diffusion region  22 , the P-type diffusion region  25 , and the ground pad  12 . As illustrated in  FIG. 2 , the P-type diffusion region  22  is electrically connected to a metal film wiring  22 B through a contact  22 A, and the P-type diffusion region  25  is electrically connected to a metal film wiring  25 B through a contact  25 A. The metal film wiring  22 B is electrically connected to the ground pad  12  serving as an external connection pad. Similarly, the metal film wiring  25 B is electrically connected to the ground pad  12  serving as the external connection pad. In this case, the layout is designed so that the metal film wiring  22 B is independently wired in a separate manner as another wiring from the metal film wiring  25 B so as not to be wired together to the closest possible to the ground pad  12 . Similarly, the layout is designed so that the metal film wiring  25 B is independently wired in a separate manner as another wiring from the metal film wiring  22 B so as not to be wired together to the closest possible to the ground pad  12 . That is, the P-type diffusion region  22  and the P-type diffusion region  25  are each connected to the ground pad  12  not by the shortest distance but respectively through the detour metal film wirings  22 B and  25 B arranged separately to each other while avoiding the mutual contact. 
         [0022]    Next, a description is given of an operation of the semiconductor device. 
         [0023]    The minority carriers (electrons) caused by the surge to the pad  11  may sometimes leak from the N-type diffusion region  21  (the drain of the protective transistor or the cathode of the protective diode) in the region of the ESD protection circuit to the P-type semiconductor substrate  27 . The minority carriers are caused to flow from the semiconductor substrate  27  into the P-type diffusion region  22  connected to the ground pad  12 , and to be absorbed. The minority carriers that are not absorbed into the P-type diffusion region  22  are forcibly drawn out from the semiconductor substrate  27  into the N-type diffusion region  23  connected to the power supply pad  13 . The minority carriers that are not drawn into the N-type diffusion region  23  are caused to flow from the semiconductor substrate  27  into the P-type diffusion region  25  connected to the ground pad  12 , and to be absorbed. That is, the minority carriers caused by the surge to the pad  11  are released from the semiconductor substrate  27  by the triple guard ring including the P-type diffusion region  22 , the P-type diffusion region  25 , and the N-type diffusion region  23  inside the N-type well  24 . 
         [0024]    In this case, the P-type diffusion region  22  and the P-type diffusion region  25  in the triple guard ring are each connected to the ground pad  12  not by the shortest distance but detoured respectively through the metal film wirings  22 B and  25 B. Therefore, a parasitic resistance of the metal film wiring  22 B and the metal film wiring  25 B occurs between the P-type diffusion region  22  and the P-type diffusion region  25 . The minority carriers absorbed into the P-type diffusion region  22  are not caused to flow into the P-type diffusion region  25  due to the parasitic resistance but flow into the ground pad  12 . That is, a minority carrier absorbing function of the P-type diffusion region  22  is exerted reliably. The minority carriers caused by the surge to the pad  11  are a main cause of occurrence of latch-up in the internal circuit. As described above, the minority carriers are released from the semiconductor substrate  27 , with the result that the latch-up in the internal circuit is not liable to occur. 
         [0025]    Note that, in  FIG. 1 , the N-type diffusion region  21  serves as the drain of the NMOS transistor or the cathode of the protective diode that functions as the ESD protection circuit for protecting the semiconductor device from the ESD. In the case of the NMOS transistor, the source and the gate of the NMOS transistor are connected to the ground pad  12 , and the drain is connected to the pad  11 . 
         [0026]    As another embodiment, as illustrated in  FIG. 3 , the N-type diffusion region  21  may serve as a drain of an open-drain output NMOS transistor. A source of the NMOS transistor is connected to the ground pad  12 , and a drain thereof is connected to an output pad  31 . 
         [0027]    Further, as illustrated in  FIG. 4 , the drain may be a drain of an open-drain output PMOS transistor. A source of the PMOS transistor is connected to the power supply pad  13 , and the drain (P-type diffusion region  28  inside an N-type well  29 ) is connected to the output pad  31 .