Abstract:
A FIFO unit for buffering serial communications includes a register and a unit for maintaining a single pointer. The single pointer functions as an IN pointer during writes and an OUT pointer during reads. The same circuitry maintains the pointer for both reads and writes to the FIFO. This circuitry preferably includes a single counter. If an error occurs during reading, the single pointer can be reinitialized and reading restarted, without loss of data. The register is not erased until reading is complete.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to FIFO units used for buffering serial data. 
     2. Related Art 
     Usually in a serial communication application, a FIFO is used to buffer output data in case access to a data bus is lost. If access to the bus is lost in the middle of a transmission, the output data has to be re-sent from the FIFO when access to the data bus is regained. Normally, the FIFO therefore requires two pointers, an IN pointer and an OUT pointer. Each of these pointers requires circuitry to maintain it. 
     There has been a long-felt need for simplification of FIFO units. For instance, U.S. Pat. No. 5,732,011 illustrates a FIFO unit where the pointer unit is simplified. The patent speaks of creating a single pointer means, but the pointer means still needs to specify three pointers to operate the FIFO. 
     SUMMARY OF THE INVENTION 
     The object of the invention is to simplify a FIFO unit. 
     The simplified FIFO unit has only a single pointer. During reading from the FIFO, the pointer can be reset in response to an interrupt without erasing of the contents of the FIFO unit, so that reading can begin again after the interrupt is over. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be described by way of non-limiting example with reference to the following figures: 
     FIG. 1 shows a FIFO unit in accordance with the invention. 
     FIG. 2 shows a flowchart indicating the order of operations of the elements of the FIFO unit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a FIFO unit in accordance with the invention. This unit includes 32 flip-flops 101 for storing a word in the FIFO unit. The flip-flops 101 together constitute a register. 
     The FIFO is loaded from the Transmit --  data --  in line 102 and unloaded from the data --  out line 103. Data bits from Transmit --  data --  in are accepted by the flip-flops 101 in accordance with enable signals EN from DMUX 104. Data bits from the flip-flops 101 are multiplexed by MUX 105 one by one from the Q outputs of the flip-flops 101 to data --  out. 
     Control logic for the FIFO unit includes five-bit counter 106; OR gates 107, 108, 109; and control bit lines: start --  transmit 110, fifo --  empty 111, tx --  transmit 112, reset --  n 113, and interrupt 114. 
     The five-bit counter 106 holds the single pointer which is used both for reading from and for writing to the register 101. 
     Start --  transmit will be held high for the first part of a data transmission. Let us take the example of a 96 bit communication. Not all 96 bits can fit in register 101. They must be taken in three 32-bit pieces. For the first thirty-two bit piece, start --  transmit will be held high. After the first thirty-two bits, start --  transmit will be forced low again. 
     As start --  transmit goes low, tx --  transmit will be forced high and held high until a signal from the receiving device indicates that the current thirty-two bit piece is received. Since writing new data to the register must a) await completion of reading old data from the register and b) occur before tx --  transmit goes high again, the register must able to be reloaded between a) and b). 
     Typically, the ability to reload the register within the allotted time will depend on the register being small. The designer must determine a time tl between the completion of a previous transmission and the start of a next transmission. The designer must further determine a time t2 necessary to load one bit into the FIFO. The maximum number of bits in the register must then be t1/t2. In the preferred embodiment, the register is 32 bits long. Those of ordinary skill in the art can readily adapt the invention to other numbers of bits, as well, e.g. 64 bits. 
     As the tx --  transmit is forced low again, the fifo --  empty line will be forced high to allow the next thirty-two bit piece to be loaded into the register 101. 
     Reset --  n is normally forced low for a single clock cycle when either a thirty-two bit piece has been loaded or when it has been successfully transmitted. 
     Interrupt is only forced high when there is an error reading from the register 101. 
     The output of gate 109 is coupled both to an enable input of DMUX 104 and to an input of gate 108. The output of gate 108 is coupled to an increase input to the counter 106. Gate 107 has an inverting input coupled to receive reset --  n 113, and a non-inverting input coupled to receive interrupt 114. Either start --  transmit 110 or fifo --  empty 111 must be high to enable the demultiplexer 104, via the output of gate 109. This output of gate 109 is also an input to gate 108. Either tx --  transmit 112 or the output of gate 109 must be high to cause the counter to increment. Reset --  n 113 must be low or interrupt 114 must be high to reset the counter 106. 
     The output of the counter 106 is coupled both to DMUX 104 and to MUX 105. 
     FIG. 2 is a flowchart showing the order of operation of the elements of FIG. 1. At 201 the single FIFO pointer, stored in counter 106, is reset to `00000`. Box 202 corresponds to gate 109, if either start --  transmit or fifo --  empty is high, data is to be loaded per 203 into the register 101. During loading, gate 108 causes incrementation of the counter 106 to insure updating of the register 101 at the proper bit location. If reset --  n goes low during loading, per box 204 control returns to 201. Upon completion of loading after box 210, reset --  n will go low at 205, resetting the counter 106. 
     If tx --  transmit is high, per box 206, reading should occur from the register 101. Gate 108 insures that counter 106 is incremented during reading from the register 101 just as it was during writing to the register 101, per box 207. Once the FIFO is empty, fifo --  empty will go high at box 208. Then operation should return to box 201. On the other hand, if the interrupt line is high, at 209, then operation should return to box 205, where the pointer is reset and reading of the data in the register 101 will begin again. If the interrupt line is low and the fifo --  empty line is low at 209 then operation returns to box 206, to continue reading bits from register 101. 
     The linear nature of the flow chart of FIG. 2 necessarily fails to reflect all the possibilities of the circuit of FIG. 1, which is actually somewhat parallel in its testing of conditions. For instance, if tx --  transmit is low at 206 and if start --  transmit or fifo --  empty were high, operations would in fact be back at box 203. However, the flow chart gives an intuitive understanding of how the FIFO unit of FIG. 1 is intended to be used. 
     Those of ordinary skill in the art may devise many other embodiments of the single pointer FIFO of the invention, for instance the write enable demultiplexer 104 might be designed to demultiplex the input data rather than the enable signals.