Abstract:
One embodiment features an electrical circuit comprising: a high-voltage input configured to receive a high voltage into the electrical circuit; a low-voltage input configured to receive a low voltage into the electrical circuit; a thin-oxide circuit comprising a thin-oxide metal-oxide-semiconductor field-effect transistor (MOSFET); and a protection circuit configured to protect the thin-oxide circuit from the high voltage, wherein the protection circuit comprises a thick-oxide MOSFET clamp circuit, and an adaptive voltage reference circuit configured to provide an adaptive reference voltage, wherein the thick-oxide MOSFET clamp circuit is biased by the adaptive reference voltage.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims benefit of U.S. Provisional Patent Application Ser. No. 61/108,702 filed Oct. 27, 2008, the disclosure thereof incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     The present disclosure relates generally to electrical circuits. More particularly, the present disclosure relates to over-voltage protection of thin-oxide metal-oxide-semiconductor field-effect transistors (MOSFET) in circuits such as data converters. 
     Using different voltages to power different circuit segments is common in VLSI designs for data converters, including analog-to-digital converters (ADC) and digital-to-analog converters (DAC). The main purpose for this approach is to reduce power consumption. However, this approach provides over-voltage protection challenges for thin-oxide devices within the interfaces between the power domains. Theoretically the power up sequence could be controlled by an external power management unit, for example in portable devices. For instance, the system power could be sequenced from the highest power (for example, 3.3V) to the lowest power (for example, 1.2V). However for some applications, the power sequence is difficult to control due to other constraints. Therefore, internal circuits must have the capability to accommodate the different power sequences. 
     In modern submicron CMOS processes, reliability requirements for the power domain interfaces specify certain over-voltage device tolerance limits. Several failure mechanisms can occur when a voltage higher than the maximum voltage limit is applied upon either the gate or drain of the transistor devices. 
     A common solution to the problem is to put diode clamps in the power domain interfaces. However, in some applications such as data converters, high linearity is required within the signal paths. Accordingly, there is a need for a circuit-level solution. 
     SUMMARY 
     In general, in one aspect, an embodiment features an electrical circuit comprising: a high-voltage input configured to receive a high voltage into the electrical circuit; a low-voltage input configured to receive a low voltage into the electrical circuit; a thin-oxide circuit comprising a thin-oxide metal-oxide-semiconductor field-effect transistor (MOSFET); and a protection circuit configured to protect the thin-oxide circuit from the high voltage, wherein the protection circuit comprises a thick-oxide MOSFET clamp circuit, and an adaptive voltage reference circuit configured to provide an adaptive reference voltage, wherein the thick-oxide MOSFET clamp circuit is biased by the adaptive reference voltage. 
     Embodiments of the electrical circuit can include one or more of the following features. Some embodiments comprise a first amplifier powered by the high voltage, wherein the first amplifier comprises an output electrically coupled to the thin-oxide circuit; wherein the thick-oxide MOSFET clamp circuit comprises a first thick-oxide MOSFET, wherein a source of the first thick-oxide MOSFET is electrically coupled to the output of the first amplifier, and wherein the adaptive voltage reference circuit provides the adaptive reference voltage to a gate of the first thick-oxide MOSFET. In some embodiments, the output of the first amplifier comprises a differential output; wherein the differential output comprises a first output and a second output; wherein the source of the first thick-oxide MOSFET is electrically coupled to the first output of the first amplifier; wherein the thick-oxide MOSFET clamp circuit further comprises a second thick-oxide MOSFET, wherein a source of the second thick-oxide MOSFET is electrically coupled to the second output of the first amplifier; and wherein the adaptive voltage reference circuit is further configured to provide the adaptive reference voltage to a gate of the second thick-oxide MOSFET. In some embodiments, the adaptive voltage reference circuit further comprises: a second amplifier powered by the high voltage, wherein a common-mode output of the first amplifier is electrically coupled to a positive input of the second amplifier. In some embodiments, the adaptive voltage reference circuit further comprises: a third thick-oxide MOSFET; wherein a source of the third thick-oxide MOSFET is electrically coupled to the high voltage; and wherein an output of the second amplifier is electrically coupled to a gate of the third thick-oxide MOSFET. Some embodiments comprise a data converter comprising the electrical circuit. Some embodiments comprise an integrated circuit comprising the data converter. 
     The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims. 
    
    
     
       DESCRIPTION OF DRAWINGS 
         FIG. 1  shows elements of a data converter with a bandgap reference in the low-voltage domain according to some embodiments. 
         FIG. 2  shows elements of a data converter with over-voltage protection for blocks driven by an amplifier powered by a relatively high voltage. 
         FIG. 3  shows elements of a data converter with over-voltage protection for blocks driven by an amplifier with differential outputs powered by a relatively high voltage. 
         FIG. 4  shows elements of a data converter with over-voltage protection and common mode tracking for blocks driven by an amplifier with differential outputs powered by a relatively high voltage. 
         FIG. 5  is a timing diagram showing the relationships of the signal waveforms of the electrical circuit in  FIG. 4  according to some embodiments when VDD 2  ramps up faster than VDD 1 . 
     
    
    
     The leading digit(s) of each reference numeral used in this specification indicates the number of the drawing in which the reference numeral first appears. 
     DETAILED DESCRIPTION 
     Embodiments of the present disclosure provide electrical circuits, and elements thereof, having multiple power domains and protection circuits to protect thin-oxide devices in the low-voltage domains from over-voltage conditions. In some embodiments, an amplifier with differential outputs in the high-voltage domain drives a thin-oxide circuit in the low-voltage domain. A clamp circuit protects the thin-oxide circuit. The clamp circuit is biased with an adaptive voltage reference based on a common-mode output of the amplifier. Although in the described embodiments, the elements of the circuits are presented in one arrangement, other embodiments may feature other arrangements, as will be apparent to one skilled in the relevant arts based on the disclosure and teachings provided herein. In addition, the techniques disclosed herein are not limited to data converters, but can be applied to a wide range of circuits. 
     From the system point of view, it is better to place more functional blocks in the low-voltage power domain to reduce overall power consumption, especially for deep sub-micron system-on-a-chip (SOC) designs and the like. For data converter designs, it is preferable to place the bandgap reference in the low-voltage domain if the noise budget can meet requirements.  FIG. 1  shows elements of a data converter  100  with a bandgap reference in the low-voltage domain according to some embodiments. 
     Referring to  FIG. 1 , data converter  100  includes a thin-oxide circuit  102  that includes a plurality of thin-oxide devices Mn powered by a relatively low voltage VDD 1 , a thick-oxide circuit  104  that includes a plurality of thick-oxide devices Mk powered by a relatively high voltage VDD 2 , and a protection circuit  106  configured to protect thin-oxide circuit  102  from high voltage VDD 2 . 
     Thin-oxide circuit  102  includes a bandgap circuit  108  that provides reference voltages vbnc and vbn to a current mirror constructed from four thin-oxide NMOS MOSFETs Mn 0 , Mn 1 , Mn 2 , and Mn 3 . In particular, bandgap circuit  108  provides reference voltage vbnc to the gates of devices Mn 0  and Mn 2 , and provides reference voltage vbn to the gates of devices Mn 1  and Mn 3 . The sources of devices Mn 0  and Mn 2  are electrically coupled to the drains of devices Mn 1  and Mn 3 . The sources of devices Mn 1  and Mn 3  are electrically coupled to voltage VSS. 
     Thick-oxide circuit  104  includes a current mirror constructed from eight thick-oxide PMOS MOSFETs Mk 2 , Mk 3 , Mk 4 , Mk 5 , Mk 6 , Mk 7 , Mk 8 , and Mk 9 . The sources of devices Mk 3 , Mk 5 , Mk 7 , and Mk 9  are electrically coupled to high voltage VDD 2 . The sources of devices Mk 2 , Mk 4 , Mk 6 , and Mk 8  are electrically coupled to the drains of devices Mk 3 , Mk 5 , Mk 7 , and Mk 9 . The drains of devices Mk 6  and Mk 8  provide currents I 1  and I 2 , respectively. The gates of devices Mk 5 , Mk 7 , and Mk 9  are electrically coupled to the drain of device Mk 4 . The gates of devices Mk 2 , Mk 3 , Mk 4 , Mk 6 , and Mk 8  are electrically coupled to the drain of device Mk 2 . 
     Protection circuit  106  includes two thick-oxide NMOS MOSFETs Mk 0  and Mk 1 . The gates of devices Mk 0  and Mk 1  are electrically coupled to low voltage VDD 1 . The drains of devices Mk 0  and Mk 1  are electrically coupled to the drains of devices Mk 2  and Mk 4 , respectively, of thick-oxide circuit  104 . The sources of devices Mk 0  and Mk 1  are electrically coupled to the drains of devices Mn 0  and Mn 2 , respectively, of thin-oxide circuit  102 . 
     In normal operation, the drain voltages of devices Mn 0  and Mn 1  are kept one threshold plus overdrive below voltage VDD 1 , which is within the safe operation zone. In the initial power-up sequence, the drain voltages of devices Mn 0  and Mn 1  are kept below voltage VDD 1  no matter which power supply (VDD 1  or VDD 2 ) is up first, thereby providing over-voltage protection to thin-oxide circuit  102  in all cases. 
     If a larger voltage swing signal is needed for inter-chip communication, a higher power supply VDD 2  is needed to drive the interface domain. One protection challenge in this case is the interface between the VDD 2  domain and the VDD 1  domain.  FIG. 2  shows elements of a data converter  200  with over-voltage protection for blocks driven by an amplifier powered by a relatively high voltage VDD 2 . 
     Referring to  FIG. 2 , data converter  200  includes a thin-oxide circuit  202  powered by a relatively low voltage VDD 1 , an amplifier  204  powered by relatively high voltage VDD 2  and providing an output voltage V_out to thin-oxide circuit  202 , and a protection circuit  206  to protect thin-oxide circuit  202  from over-voltage conditions caused by amplifier  204 . 
     Protection circuit  206  includes a thick-oxide PMOS MOSFET Mk 10  and a voltage reference circuit that includes an adjustable current source I 0  electrically coupled to voltage VDD 1  and an adjustable resistor R 0  electrically coupled between adjustable current source I 0  and voltage VSS. The voltage vref_adj across adjustable resistor R 0  is provided to the gate of device Mk 10 . The source of device Mk 10  is electrically coupled to the output of amplifier  204 . The drain of device Mk 10  is electrically coupled to voltage VSS. The substrate of device Mk 10  is biased with voltage VDD 2 . 
     Device Mk 10  is used as a clamp circuit in this approach. In order to keep amplifier output V_out within a safe operation range to meet the linearity requirements of data converter  200  for different operation modes, the gate of device Mk 10  should be properly biased by voltage vref_adj. In these applications, adjustable current source I 0  and adjustable resistor R 0  provide multiple selections for different application modes. Because the substrate of device Mk 10  is biased with the highest voltage in the system, the Nwell associated with device Mk 10  is not reverse-biased in normal operation. During power-up with voltage VDD 2  rising faster than voltage VDD 1 , voltage vref_adj is pulled down to ground by adjustable resistor R 0 , keeping voltage V_out below one threshold plus overdrive. In the case where voltage VDD 1  rises faster than voltage VDD 2 , the Nwell associated with device Mk 10  is charged by voltage VDD 1  by forward biasing. Thus protection circuit  206  is ready before voltage VDD 2  is up. 
     For differential operation, the amplifier  204  of  FIG. 2  is replaced with an amplifier having differential outputs. In these cases, a similar approach is employed. 
       FIG. 3  shows elements of a data converter  300  with over-voltage protection for blocks driven by an amplifier with differential outputs powered by a relatively high voltage VDD 2 . 
     Referring to  FIG. 3 , data converter  300  includes a thin-oxide circuit  302  powered by a relatively low voltage VDD 1 , an amplifier  304  powered by relatively high voltage VDD 2  and providing output voltages V_outn and V_outp to thin-oxide circuit  302 , and a protection circuit  306  to protect thin-oxide circuit  302  from over-voltage conditions caused by amplifier  304 . 
     Protection circuit  306  includes two thick-oxide PMOS MOSFETs Mk 11  and Mk 12  and a voltage reference circuit that includes an adjustable current source I 1  electrically coupled to voltage VDD 1  and an adjustable resistor R 1  electrically coupled between adjustable current source I 1  and voltage VSS. The voltage vref_adj across adjustable resistor R 1  is provided to the gates of devices Mk 11  and Mk 12 . The sources of devices Mk 11  and Mk 12  are electrically coupled to the negative and positive outputs of amplifier  304 , respectively. The drains of devices Mk 11  and Mk 12  are electrically coupled to voltage VSS. The substrates of devices Mk 11  and Mk 12  are biased with voltage VDD 2 . 
     Devices Mk 11  and Mk 12  are used as a clamp circuit that operates in a manner similar to the clamp circuit of  FIG. 2 . For high linearity requirements, the gate voltages of devices Mk 11  and Mk 12  should be well defined to avoid any linearity degradation. 
     If the common mode output of the differential amplifier will change in different situations, automatic tracking of this common mode is used for the protection circuit.  FIG. 4  shows elements of a data converter  400  with over-voltage protection and common mode tracking for blocks driven by an amplifier with differential outputs powered by a relatively high voltage VDD 2 . 
     Referring to  FIG. 4 , data converter  400  includes a thin-oxide circuit  402  powered by a relatively low voltage VDD 1 , an amplifier  404  powered by relatively high voltage VDD 2  and providing output voltages V_outn and V_outp to thin-oxide circuit  402 , and a protection circuit  406  to protect thin-oxide circuit  402  from over-voltage conditions caused by amplifier  404 . 
     As with data converter  300  of  FIG. 3 , protection circuit  406  includes a clamp circuit including one of thick-oxide PMOS MOSFETs Mk 13  and Mk 14 . In contrast to data converter  300  of  FIG. 3 , the voltage reference circuit is adaptive, and includes a buffer amplifier  408 , a resistor divider R 2 , R 3 , R 4  and by-pass capacitor C 0 , and a thick-oxide PMOS MOSFET Mk 15 . 
     Buffer amplifier  408  is powered by voltage VDD 2 , and drives the gate of device Mk 15 . The source of device Mk 15  is electrically coupled to voltage VDD 2 . The drain of device Mk 15  is electrically coupled to the resistor divider. The common node of resistors R 4  and R 2  provides adaptive reference voltage vref_adj to the clamp circuit, and is electrically coupled to voltage VSS by capacitor C 0 . The positive input of buffer amplifier  408  is electrically coupled to the common node of resistors R 2  and R 3 . The negative input of buffer amplifier  408  is driven by the common mode output VCM of differential amplifier  404 . 
     The common mode output of differential amplifier  404  is controlled by a common-mode feedback amplifier which takes a fixed DC voltage. A low-offset singe-ended buffer amplifier  408  is used here to generate voltage vref_adj with a fixed ratio determined by resistors R 2  and R 3 . By-pass capacitor C 0  is used to stabilize reference voltage vref_adj. 
       FIG. 5  is a timing diagram showing the relationships of the signal waveforms of the circuit in  FIG. 4  according to some embodiments when VDD 2  ramps up faster than VDD 1 . Referring to  FIG. 5 , VDD 2  begins to rise at time t 0 , while VDD 1  does not begin to rise until time t 3 . In response to the rise of VDD 2 , common mode voltage VCM begins to rise at time t 1 , and is ready at time t 2 , after VDD 2  ramps up to its settled value. 
     During power-up with voltage VDD 2  rising faster than voltage VDD 1 , voltage vref_adj is pulled down to ground by resistors R 2  and R 3  with the help of capacitor C 0 . The differential output V_outp-V_outn of amplifier  404  has full swing when the output common voltage VCM settles. However without proper biasing of the clamp circuit, the linearity of the differential output won&#39;t meet requirements because the differential output is distorted by the clamp circuit. This problem is addressed by biasing the gates of devices Mk 13  and Mk 14  to the proper voltage so that the differential output of amplifier  404  has sufficient voltage swing range for good linearity. 
     Reference voltage Vref adj is ready after some delay, and then the protection scheme starts to function before VDD 1  begins to rise. Because the protection PMOS diodes are off during the normal operation, there is no straight bandwidth requirement for the buffer amplifier loop. The additional power overhead from buffer amplifier  408  is small relative to the entire system. 
     A number of implementations of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. Accordingly, other implementations are within the scope of the following claims.