Abstract:
In an integrated circuit process for SOI including trench device isolation, the problem of voids in the trench fill is addressed by a triple fill process, in which a thermal oxide sidewall having recesses at the bottom corners is covered with a LPCVD deposition that fills in the recesses, followed by a void-free HDP deposition. Densification results in substantially the same etch rate for the three types of oxide.

Description:
TECHNICAL FIELD  
         [0001]    The field of the invention is that of integrated circuit processing with a process that includes a trench device isolation.  
         BACKGROUND OF THE INVENTION  
         [0002]    In modern silicon integrated circuit processing, space requirements have resulted in great popularity for device isolation by etching trenches and filling them with oxide, rather than the LOCOS isolation popular in the past.  
           [0003]    The technology for etching and filling such isolation trenches is well advanced, though improvements are continuously being developed.  
           [0004]    A popular method of trench fill includes a step of growing a thin layer of thermal oxide to passivate the trench sidewalls, before the main filling step. A drawback of such an approach on SOI (Silicon On Insulator) wafers is that the thermal oxide does not grow on the trench bottom and also grows nonuniformily along the trench sidewalls. The thermal oxide liner is thicker toward the center and top, leaving a negative angle or recess near the bottom corner of the trench, denoted by numeral  114  in FIG. 2. Such a recess leaves a void in the bottom corners when the main fill is done with HDP (high density plasma) oxide deposition.  
           [0005]    Filling the entire trench with LPCVD oxide fills the negative angle at the bottom corners preventing corner void formation. However, the drawback of this approach is the formation of a seam or center void. Thus, voids remain a problem that is present in contemporary approaches to trench isolation. Any void present in the trench fill can become a receptacle during subsequent processing for conductive material such as polysilicon and may degrade product yield.  
         SUMMARY OF THE INVENTION  
         [0006]    The invention relates to a trench fill process for trench isolation that produces void-free trench filling.  
           [0007]    A feature of the invention is the filling of sidewall recesses left by the initial thermal oxide step.  
           [0008]    Another feature of the invention is a thin filling layer of low density oxide fill having intermediate conformality: i.e. is thicker where it fills the bottom corners.  
           [0009]    Another feature of the invention is filling the remaining aperture with HDP oxide.  
           [0010]    Yet another feature of the invention is densifying the filling layer so that the final composite oxide fill has substantially the same etch rate for all three components. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    [0011]FIGS. 1 and 2 show, in cross section, preliminary steps in the formation of trench isolation.  
         [0012]    [0012]FIGS. 3A and 3B show problems with prior art approaches.  
         [0013]    [0013]FIGS. 4 and 5 show steps in the inventive process. 
     
    
     DETAILED DESCRIPTION  
       [0014]    A section of an SOI (silicon on insulator) wafer  10  is shown in FIG. 1 and following figures. This example is that of a silicon substrate  10  with a silicon device layer  30 , separated by an implanted SIMOX (Separation by IMplantation of OXygen) layer  20 , but bonded oxide insulating layers and Silicon-germanium device layers may also benefit from the invention.  
         [0015]    An aperture  50  has been etched through pad oxide  110  (illustratively 8 nm of thermal oxide) and pad nitride  120  (illustratively 120 nm of LPCVD Si 3 N 4 ) and silicon device layer  30  (illustratively 120 nm). Illustratively, the etch for the pad oxide and nitride is an NF 3 /Ar RIE (reactive ion etch) and the etch for device layer  30  is HBr and Cl 2 . This latter etch is very selective to oxide, so that, for the parameters specified, only about 10 nm of insulating layer (buried oxide, BOX)  20  is removed.  
         [0016]    [0016]FIG. 2 shows the result of a rapid thermal oxidation of the vertical walls of device layer  30 , producing 10-30 nm of oxide  112  at the thickest point. This provides sufficient corner rounding to prevent the occurrence of corner leakage during device operation.  
         [0017]    A problem with this technique is that the thickest portion of the oxide  112  is toward the center and top of the trench, leaving a recessed portion or negative trench angle  114  at the bottom near the corners.  
         [0018]    As can be seen in FIG. 3A, a fill with HDP oxide  130  leaves voids  115  at the bottom corners, since the fill tends to deposit directionally. In operation, these voids present the problem. During subsequent processing, planarization and wet chemical etching will recess the HDP oxide height or thickness. Eventual exposure of the void and expansion due to wet etching leaves a receptacle for polysilicon conductor material to deposit. Such an occurrence will electrically short neighboring devices, leading to product failure.  
         [0019]    A fill with LPCVD oxide  130 ′ (in FIG. 3B) fills in the bottom corners, but leaves a void or seam  115 ′ at the center. This center void has the same drawback previously discussed. It, too, can fill with polysilicon conductive material and cause failure due to device shorting. Failure due to a center void is likely to occur more readily than failure due to a bottom corner since the center void is in closer proximity to the device surface and therefore more easily exposed during processing.  
         [0020]    The inventors have found that both types of voids can be avoided if a preliminary low density oxide liner  152  is deposited, having a thickness in this example of between 25 nm to 45 nm. The actual thickness required is dependent upon the deposition technique used, the resulting liner density, and the degree of recess at the bottom corner of the starting trench. A thickness of about 15 nm greater than the thickness of liner  112  gives sufficient filling margin in the case of LPCVD. When the second liner is deposited by RTCVD, a thickness of about 30 nm greater than the thickness of liner  112  is preferred. Those skilled in the art will readily be able to determine a suitable thickness to fill in their non-planarity. Examples of preliminary liner deposition techniques include LPCVD TEOS (TetraEthyl OrthoSilicate) and RTCVD oxide. Unexpectedly, for these techniques the thin preliminary liner is only moderately conformal and fills in the recesses or negative trench angles  114 , leaving a face that is substantially planar compared with the face left by liner  112  of FIG. 2. In the case of LPCVD TEOS, liner  152  is deposited at a temperature in the range of 620-700 degrees C., with 620 degrees preferred, a chemistry of tetraethyl orthosilicate and pressure range of 200 to 1000 mTorr, with 1000 mTorr preferred. In the case of RTCVD, the deposition is preferably done at a temperature in the range of 700 to 775 degrees C., with 775 degrees C. preferred, a chemistry of N 2   0  and SiH 4  and pressure range of 15 to 75 Torr, with 15 Torr preferred.  
         [0021]    As was described above, the desired result is to apply an intermediate layer of only moderate conformality in a manner to reduce the thickness difference of the thermal oxide passivation layer: i.e. thicker where the passivation layer is thin and vice versa. The examples have been given as an illustration of possible approaches. Those skilled in the art will readily be able, in the light of this disclosure, to modify the processes illustrated to suit their conditions and to apply the teachings to other processes: e.g. PECVD.  
         [0022]    A HDP oxide layer  155  is deposited to a nominal thickness which is dependent upon on the technology node and the corresponding trench depth for that node.  
         [0023]    A densification step, illustratively comprising a rapid thermal anneal at 1100 degrees C. in Argon/O 2  densifies preliminary liner  112 , so that the wet etching rate (in a conventional BHF or DHF mixture) is similar for HDP oxide  155  and the low density preliminary liner oxide (such as TEOS)  112 . The densification can be done at any convenient time.  
         [0024]    The trench fill (HDP and liner) is then planarized, using nitride  120  as a polish stop.  
         [0025]    While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced in various versions within the spirit and scope of the following claims.