Abstract:
An overvoltage/overcurrent electrostatic discharge protection single circuit structure for Integrated Circuits protects on all paths and polarities between In/Out, Supply, and Ground pins. The structure is built on the chip substrate with an N well with three P Diffusions therein each containing N+ and P+ diffusions therein to form 6 transistors and 8 parasitic resistors to yield 5 thyristors. The structure provides very fast, symmetrical, full protection while using minimal chip area.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to protection for semiconductor integrated circuits from over-voltage and over-current conditions caused by electrostatic discharge (ESD). The present invention relates more specifically to a single structure ESD protection circuit using active devices integrated therein. 
     2. Description of Prior Art 
     ESD events, which are inevitable in integrated circuit (IC) manufacturing, assembly, and application, generate huge over-current and over-voltage pulses that can fatally damage electronic components. ESD failure emerges as the major reliability concern to the IC industry, accounting for up to thirty percent of field failures. Therefore, industrial standards generally require on-chip ESD protection circuits for all IC chips. 
     In general principle, an ESD protection circuit is off, or open in normal operation and is triggered on, or closed, during an ESD event to form a low impedance path to shunt the current surge and to clamp the pin voltage to a sufficient level, thereby protecting an IC part from being damaged. To form a complete ESD protection scheme, shown in FIG. 1, protection against ESD pulses of two opposite polarities, or pulse modes, i.e., positive and negative, along a path from each input/output (I/O) pin to both power supply, or V DD , and ground, or GND, as well as the path between V DD  to GND are required to achieve all direction protection. 
     Various on-chip ESD protection designs are known. Traditional solutions generally offer low impedance discharging paths in one direction only while relying on a passive current path with much higher impedance for protection in the opposite direction. This means four circuits may be needed for each I/O pin and an additional circuit between supply and ground, if a high level of ESD protection is desired. This solution consumes significant chip area, e.g., up to thirty percent of the whole chip. 
     Other proposed solutions, such as U.S. Pat. No. 5,739,998 to Wada, may use various combinations of parasitic diodes and SCRs with transistor areas to provide protection for the various paths and pulse modes. Parasitic resistance and capacitance may negatively affect IC performance, as well as offer reduced protection performance because of higher impedance and slower reaction times which may not be adequate for very high speed chips such as RF IC&#39;s. In short, there is great need for a single structure circuit covering all ESD paths and pulse modes utilizing only active devices while utilizing minimal chip area. 
     In  Proceedings of IEEE  7 th International Symposium on the Physical and Failure Analysis of IC &#39;s, pp. 151-155, 1999, an ESD protection scheme is disclosed offering improved performance in a compact area providing low impedance active discharge paths in both directions to shunt ESD pulses in two opposite polarities. It therefore requires only two circuits for each I/O pin and a separate ESD circuit for V DD  to GND for full ESD protection as seen in FIG.  2 . This scheme represents a further size reduction in silicon area consumption over previously known schemes. 
     SUMMARY OF THE INVENTION 
     An ESD protection structure according to the present invention forms a single circuit which has a N-well, or N-substrate, having three separate P diffusions (hereinafter “tubs”) with the first and third P-tubs having N+ and P+ diffusions for ohmic contact therein. A second P-tub interposed between the first and third tub has two N+ diffusions and one P+ diffusion therein. The I/O pin, or anode, is connected across each of the two N+ diffusions and the P+ diffusion of the second P-tub. The V DD , or supply, pin, cathode one, is connected across the N+ and P+ diffusions of the third tub. The ground pin, cathode two, is connected across the P+ and N+ diffusions of the first P-tub. The structure thereby forms six bipolar transistors and eight parasitic resistors and thereby forming a circuit of five thyristors for control of the ESD over-current/over-voltage conditions. The structure set forth herein preferably forms symmetrical upper and lower protection subcircuits. The upper and lower subcircuit have one PNP transistor and two NPN transistors and four resistors creating two thyristors in each protection subcircuit, or structure half, and one thyristor formed between the subcircuits. One protection subcircuit provides positive and negative pulse protection between the I/O pin and the V DD  pin. The other protection subcircuit provides positive and negative pulse protection between the I/O pin and the ground pin. The shared thyristor provides both positive and negative pulse protection between the ground pin and the V DD  pin. By being built on a single substrate and providing protection against both polarities of surge along all paths, the present invention provides maximum protection with minimal use of IC surface area. The present structure operates symmetrically and responds in the sub-nanosecond range, providing low holding voltage, low discharge impedance adjustable trigger voltage and high failure threshold voltages. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic illustration of the traditional scheme for ESD protection. 
     FIG. 2 is a schematic illustration of a known improved scheme for ESD protection. 
     FIG. 3 is a schematic illustration of the single circuit substrate, all active device, all path, all pulse mode, present invention. 
     FIG. 4 is a detailed cross-section of the semiconductor structure of the present invention with connections and equivalent circuitry indications therein. 
     FIG. 5 shows the equivalent circuitry of the present invention. 
     FIG. 6 is a plot of current/voltage behavior for operation of the present invention in various pulse paths and polarities by simulation. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     The ESD protection structure  21  seen in cross-section in FIG. 4, has three terminals, namely I/O, V DD , and GND. The structure has eight layers: N 1 , P 2 , N 3 , P 4 , N 5 , N 6 , P 7 , N 8 . The intrinsic electronic circuitry structure is added for clarity to FIG.  4 . 
     There are three P-type tubs: P 2 , P 4  and P 7 ; with each having a P+ contact  23 ,  25 ,  27 , respectively, and at least one N+ contact N 1  in P 2 ; N 5  and N 6  in P 4 ; and N 8  in P 7 . The three P-type tubs P 2 , P 4  and P 7  are formed in the N-type well, or N Boundary Layer NBL, N 3 . Six bipolar transistors Q 1 -Q 6  and eight parasitic resistors R 1 -R 8  are formed as electrically connected entities and may be grouped into two functional protection subcircuits: upper, or right, unit one and lower, or left, unit two. 
     The upper protection subcircuit  22  consists of Q 1 -Q 3  and R 1 -R 4 . Q 1  is formed by P 2 N 3 P 4 . Q 2  is formed by N 1 P 2 N 3 . Q 3  is formed by N 3 P 4 N 5 . R 1  is formed by the P+ diffusion  23  in the P 2  tub and its boundary with P 2 . R 2  is formed by half of the boundary of the P+ diffusion  25  in the P 4  tub. R 4  is formed at the P 4 N 3  boundary. R 3  is formed at the P 2 N 3  boundary. 
     The lower protection subcircuit  29  comprises Q 4 -Q 6  and R 5 -R 8 . Q 4  is formed by P 4 N 3 P 7 . Q 5  is formed by N 6 P 4 N 3 . Q 6  is formed by N 3 P 7 N 8 . R 5  is formed by the second half of the parasitic resistor of the P 4 /P+  23  junction. R 6  is formed by the boundary of the P+ diffusion  27  in the P 7  tub. R 7  is formed by the boundary of P-tub P 4  with N-well N 3 . R 8  is formed by the boundary of P-tub P 7  with N-well N 3 . 
     Q 3  and Q 5  share the base P 4  and collector N 3  layers. R 2  and R 5  split the resistor layer of P 4 . Each tub P 2 , P 4 , P 7  has formed across its P+ and N+ diffusions a terminal for a connection to the lead frame pins of V DD    31 , I/O  33 , and GND (ground)  35 , respectively, by known means. 
     The ESD protection structure  21  is in the “off” state in normal operation so that it does not interfere with the IC chip function. Referring to FIG. 5, the operation principle is first described for case  1  where a negative ESD pulse occurs at the I/O pin  33  with respect to the supply voltage at the V DD  pin  31  and the upper subcircuit  22  serves as the protection subcircuit. With this positive ESD surge appearing from terminal V DD    31  to I/O  33 , i.e., negatively from I/O to V DD , the base-collector junction (N 3 P 4 ) of Q 1  is reverse biased to its breakdown where excess electron-hole pairs are generated. It will be noted that changing the P and N compositions at the junctions labeled “breakdown” in FIG. 4 enables the manufacturer to adjust the trigger voltages of the device. The holes will be collected by the negative terminal I/O  33  via the P+ contact of P 4 . Since both the P+ layer P 4  and N+ layer N 5  are connected to the I/O terminal  33 , the base-emitter junction voltage (P 4 N 5 ) of Q 3  increases and turns on Q 3  This effectively triggers off the corresponding thyristor, P 2 N 3 P 4 N 5 , and drives it into deep snapback region with low holding voltage V h  less than or equal to two volts. A first active discharge path  37  with negligible impedance is thereby formed to shunt the huge current surge and clamp the I/O pad voltage at a sufficiently low level to protect the core IC from being damaged by the negative I/O-to-V DD  ESD pulse. After the ESD pulse is over, the thyristor is quickly discharged and turned off when the current decreases to below its holding current level. 
     The same mechanism applies to the other four polarity and path cases. In case  2  where a positive I/O-to-V DD  ESD pulse occurs at I/O pin, the thyristor P 4 N 3 P 2 N 1  of the upper subcircuit works to form a second active discharge path  39 . In case  3  where a positive I/O-to-GND ESD pulse occurs at I/O pin, the thyristor P 4 N 3 P 7 N 8  of the lower subcircuit works to form a third active discharge path  41 . In case  4  where a negative I/O-to-GND ESD pulse occurs at I/O pin, the thyristor P 7 N 3 P 4 N 6  of the upper subcircuit works to form a fourth active discharge path  43 . In case  5  where a positive or negative V DD -to-GND ESD pulse occurs, the thyristor P 2 N 3 P 7 N 8  works in the same way to form a fifth active discharge path  45 . 
     In summary, as seen in FIG. 3, only one single device is needed for each I/O pin to protect it against ESD pulses in all four directions as well as to protect ESD surges between V DD  and GND, thereby providing the desired all-direction ESD protections for IC chips. 
     The design of the present embodiment was guided by an unique mixed-mode ESD simulation-design approach that involves both Electra-thermal coupling and device-circuit coupling in simulation, a critical feature in ESD CAD design. Transient ESD simulation was used to simulate the real-world ESD pulsing situation accurately. This transient ESD simulation approach may be the only way to simulate the ultra-fast ESD events and provides such critical information as ESD response time. 
     Referencing FIG. 6 there is shown the terminal I-V characteristics of the new ESD structure from both steady-state and transient simulations. The complete simulation work includes all the five ESD pulsing modes as described previously, i.e., I/O-to-V DD  (PD &amp; ND), I/O-to-GND (PS &amp; NS), and V DD -to-GND (DS). The primary I-V curve  47  in FIG. 6 is from the steady-state I/O-to-V DD  (A˜K 1 ) simulation for both PD and ND modes. The desired symmetric operation was observed that ensures active discharging paths in both directions. The deep snap-back I-V characteristic indicates very low impedance (R&lt;1Ω) in the current shunting channels and excellent voltage-clamping capability (V h ≦2V). 
     The same symmetric operations for I/O-to-GND (A˜K 2 ) and V DD -to-GND (K 1 ˜K 2 ) were observed with example I-V curves for K 2 -to-A and K 1 -to-K 2  stressing shown in the insets  49  and  51 , respectively. Transient simulation results shows the similar properties with example I-V curves for I/O-to-V DD  (A˜K 1 ) ESD pulsing (PD &amp; ND) shown in the insets  53  and  55  respectively for HBM 2 KV stress. 
     The transient ESD pulsing simulation indicates that the ESD structure passes a 16 KV HBM test for a 200 μm wide structure, which represents a very high ESDV-to-Si ratio. The simulated ESD response time is at sub-nano-second level (t 1 ˜0.16 nS), indicating that it can satisfy the tough IEC European model and the CDM (charged device model) ESD standards. This transient response time can not currently be examined by any existing testers and the transient simulation approach may be the only way to investigate transient response time. 
     The relative higher triggering voltage (V t1 ) obtained from transient simulation compared to steady-state simulation may be attributed to the charge accumulation time in transient events. Typical simulation data are summarized in Table I, which are well in line with the measurements as discussed below. 
     
       
         
               
             
               
               
               
               
               
             
               
               
               
               
               
               
               
             
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Data summary from computer simulation 
               
             
          
           
               
                   
                 ESD Device Sample 
                 V t1  (V) 
                 V h  (V) 
                 R (Ω) 
               
               
                   
                   
               
             
          
           
               
                   
                 A &gt; K 1   
                 Simulation 
                 Steady 
                 20.82 
                 1.31 
                 ˜0.5 
               
               
                   
                 stress 
                   
                 Trans. 
                 24.69 
                 — 
                 — 
               
               
                   
                 A &gt; K 2   
                 Simulation 
                 Steady 
                 20.49 
                 1.31 
                 ˜0.4 
               
               
                   
                 stress 
                   
                 Trans. 
                 24.69 
                 — 
                 — 
               
             
          
           
               
                   
                 Device Triggering Time, t 1   
                 0.16 nS 
               
               
                   
                   
               
             
          
         
       
     
     Upon study and simulation of the present invention the artisan will realize that the main benefits of this invention include: all-direction full ESD protection, high protection level, small size, low cost and full integration with IC technology. 
     While in the foregoing specification this invention has been described in relation to certain preferred embodiments thereof, and many details have been set forth for purpose of illustration, it will be apparent to those skilled in the art that the invention is susceptible to additional embodiments and that certain of the details described herein can be varied considerably without departing from the basic principles of the invention. 
     The disclosed embodiment is intended to be illustrative and not limiting to the present invention which is to be limited only with regard to the appended claims.