Abstract:
An electronic calculator with a dot matrix display panel capable of displaying characters, symbols or other patterns is implemented with a central processor unit (CPU). More particularly, when the length of characters is in excess of the capacity of the display panel, those characters are shifted dot by dot on the display panel in the running fashion. Numbers are displayed digit by digit, preferably.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a display device for use in electronic calculators or the like, and more particularly to a display device which achieves a unique display operation. 
     In the past, when it was desired to display data of a length more than the capacity of a display panel in an electronic calculator, the data to be displayed needed to be split into two or more groups in advance. In this case data expressing the same thought had to be split into groups which were inevitably separate and the connections between two adjacent ones of the data groups were indefinite and vague, leading to operator errors in recognizing the overall or combined contents being displayed. To overcome this problem, the same applicants of this application have proposed a unique device which shifts the contents of a display panel digit by digit at a given interval of time, as disclosed and illustrated in U.S. application Ser. No. 058,666, filed July 18, 1979, and entitled DISPLAY DEVICE FOR ELECTRONIC CALCULATORS OR THE LIKE. 
     It is therefore an object of the present invention to provide a display device which uses a dot matrix type display panel for displaying numbers, characters, symbols and similar patterns and shifts successively the overall contents on the display panel when the length of data to be displayed exceeds the capacity of the display panel, wherein the shifting movement of the display takes place dot by dot in a lateral direction. 
     It is another object of the present invention to provide a display device wherein either a conventional display mode (in other words, a static display mode) or a dot shift display mode is selectable with the former displaying keyed information or the results of arithmetic operations, for example, and the latter displaying instructions indicating the sequence of arithmetic operations in a dot matrix form mainly for use in function calculators. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and for further objects and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a plan view of an example of a programmable calculator embodying a display device according to the present invention; 
     FIG. 2 is a schematic block diagram of a circuit arrangement of the illustrated calculator; 
     FIG. 3 is a schematic block diagram of display control circuitry DSC in the illustrated calculator; 
     FIGS. 4A through 4D are logic diagrams of an example of a central processor unit (CPU) in the illustrated calculator; 
     FIG. 5 is a composite diagram of the CPU in the illustrated calculator; 
     FIG. 6 is a schematic representation of a dot matrix display panel in the illustrated calculator; 
     FIG. 7(a) is an explanation diagram of a display pattern on the dot matrix display panel and FIG. 7(b) is a table for numerical binary codes; 
     FIG. 8 is a block diagram of a displaying data storage area; 
     FIG. 9 is a block diagram of part of a random access memory (RAM) of the CPU architecture; 
     FIG. 10 is a flow chart for explanation of the display operation in the illustrated calculator; 
     FIGS. 11(a) through 11(c) are details of the operation shown in FIG. 10; 
     FIG. 12(a) shows the relationship between respective steps and a process list and FIG. 12(b) is the relationship between the respective steps and applied routines; 
     FIG. 13 is a table showing the relationship between characters and their encoded signals; 
     FIG. 14 shows a program for storing encoded signals for displaying a character &#34;I&#34;; 
     FIG. 15(a) is a program for shifting the contents of the displaying data storage area and FIG. 15(b) shows events for achieving the shift operation; and 
     FIG. 16 is a flow chart of a display operation for keyed information. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to FIG. 1, there is illustrated a plan view of a programmable calculator having a display device constructed in accordance with one preferred form of the present invention, wherein a display device is generally designated DSP and a keyboard unit is generally designated K. 
     FIG. 2 shows in a block diagram the programmable calculator which includes a central processor unit CPU (hereinafter referred to as &#34;CPU&#34;), the display device DSP, for example, in the form of a liquid crystal display panel of the dot matrix type, display control circuitry DSC for enabling the display device, a random access memory RAM contained within the CPU and a displaying data storage area DRM comprised of a random access memory (RAM) contained within the display control circuitry. It further includes key strobe output terminals W 1  -W 8 , key input terminals k 1  -k 4 , opposing electrodes signal output terminals H 1  -H 7 , a memory digit address output terminal B L  T, a memory file address output terminal B M  T, a read/write signal terminal R/W, a display (disable) control signal output terminal DIS and data input output terminals DI/O. 
     Details of the display control circuitry in FIG. 2 are illustrated in a block diagram of FIG. 3. Within the display control circuitry illustrated herein, an address decoder DC 6  is connected to the displaying data storage area DRM, which decoder decodes signals from the memory digit address output terminal B L  and the memory file address output terminal B M  via an address buffer AB. A read/write control circuit RWC receives a read/write signal from the R/W terminal and achieves read and write operations on the information in the displaying data storage area via the data input output terminals DI/O. There are also provided a displaying buffer DM and a segment driver SED for decoding the area DM. When the display disable signal terminal is at &#34;1&#34; or &#34;0&#34;, SED provides an ON or OFF waveform output, respectively. Segment signal output terminals are labeled S 1  -S 40 . FIG. 4, a composite diagram of FIGS. 4A through 4D, shows a logic wiring diagram of the CPU scheme in the calculator whereby the display operation of the present invention is effected. FIG. 5 shows how to combine FIGS. 4A-4D concerning the CPU. The following will set forth a logic structure of the CPU. 
     [CPU ARCHITECTURE] 
     RAM (random access memory): this is of a 4 bit input and output capacity and accessible to a specific digit position thereof as identified by a digit address and a file address. 
     BL: a digit address counter associated with the memory RAM, with an output terminal B L  T. 
     DC 1  : a digit address decoder associated with the memory RAM. 
     BM: a file address counter associated with the memory RAM, will an output terminal B M  T. 
     DC 2  : a file address decoder for the memory RAM 
     AD 1  : this serves as an adder and a subtractor respectively in the absence and presence of a control instruction  14  . 
     AD 2  : an adder 
     G 1  : a gate for providing either a digit &#34;1&#34; or an operand I A  to an input to the adder/subtractor AD 1  and delivering I or I A  when a control instruction  15  or  16  is developed, respectively. 
     SB: a count down circuit for the memory digit address counter BL. 
     G 2  : an input gate provided for the memory digit address counter BL, which enables the output of the adder/subtractor AD 1 , the operand I A , another operand I B  and the output of the count down circuit SB to pass therethrough respectively when control instructions  10  ,  11 ,  12   and  74  are developed. 
     G 3  : a gate provides a digit &#34;1&#34; or the operand I A  to an input to the adder/subtractor, the former being provided upon the developed of an instruction  5  and the latter upon the development of an instruction  6 . 
     ED: an exclusive OR gate receiving the contents of the memory file address counter BM and the accumulator ACC and providing its output for a gate G 4 . 
     G 4  : an input gate to the memory file address BM which enables the output of the adder AD 2 , the operand I A  the contents of an accumulator ACC, and the output of EO to pass upon the development of instructions  7  ,  8  ,  9  and  85  . 
     G 5  : a file selection gate for the memory RAM 
     DC 3  : a decoder which translates the operand I A  and supplies a gate G 6  with a desired bit specifying signal. 
     G 6  : an input gate to the memory RAM, which contains a circuit arrangement for introducing a binary code &#34;1&#34; into a specific bit position of the memory identified by the operand decoder DC 3  and a binary code &#34;D&#34; into a specific bit position identified by DC 3 , respectively, when a control instruction  2  or  3  is developed. Upon the development of an instruction 11 4  the contents of the accumulator ACC are read out. 
     ROM: a read only memory 
     N 1 , N 2  : display controlling flags 
     G 46  : an input gate to N 1  and N 2 , which is turned ON upon 69. 
     RW: a read/write signal generator with its output terminal R/W, whcich executes read or write operation upon  70  or  71  , respectively. 
     PL: a program counter PL which specifies a desired step in the read only memory ROM. 
     DC 4  : a step access decoder for the read only memory ROM. 
     G 7  : an output gate which shuts off transmission of the output of the ROM to an instruction decoder DC 5  when a judge flip flop F/F J is set. 
     DC 5  : an instruction decoder adapted to decode instruction codes derived from the ROM and divide them into an operation code area I O  and operand areas I A  and I B , the operation code being decoded into any control instruction  1  - 75  . The decoder DC 5  is further adapted to output the operand I A  or I B  as it is when sensing an operation doce accompanied by an operand. 
     AD 3  : an adder increments one the contents of the program counter PL. 
     G 8  : an input gate associated with the program counter PL provides the operand I A  and transmits the contents of a program stack register SP when the instructions  20  and  61  are developed, respectively. When the instructions  20  ,  61  and  60  are being processed, any output of the adder AD 3  is not transmitted. Otherwise the AD 3  output is transmitted to automatically load &#34;1&#34; into the contents of the program counter PL. 
     FC: a flag F/F 
     G 9  : an input gate for the flag F/F FC, which introduces binary codes &#34;1&#34; and &#34;0&#34; into the flag flip flop FC when the instructions  17  and  18 are developed, respectively. 
     G 10  : a key signal generating gate provides the output of the memory digit address decoder DC 1  without any change when the flag F/F FC is in the reset state (0), and renders all outputs I 1  -I n  &#34;1&#34; whatever output DC 1  provides when FC is in the set state (1). 
     CG: a clock generator 
     BP: an opposing electrode signal generator for the liquid crystal display panel 
     H 1  -H 7  : The opposing electrode signal output terminals 
     ACC: an accumulator of 4 bits long 
     X: a temporary register of 4 bits long 
     G 11  : an input gate for the temporary register X transmits the contents of the accumulator ACC and the stack register SX respectively upon the development of the instructions  29  and  59 . 
     AD 4  : an adder executes a binary addition on the contents of the accumulator ACC and other data. The output C 4  of the adder AD 4  assumes &#34;1&#34; when the fourth bit binary addition yields a carry. 
     C: a carry F/F 
     G 12  : an input gate for the carry F/F, which sets &#34;1&#34; into the carry F/F C in the presence of &#34;1&#34; of the fourth bit carry C 4  and &#34;0&#34; into the same in the absence of C 4  (0) upon the development of  1 . &#34;1&#34; and &#34;0&#34; are set into C upon the development of  21  and  22 , respectively. 
     G 13  : a carry (C) input gate enables the adder AD 4  to perform binary additions with a carry and thus transmits the output of the carry F/F C into the adder AD 4  in response to the instruction  25 . 
     G 14  : an input gate provided for the adder AD 4  and transfers the output of the memory RAM and the operand I A  upon the development of 23  and  24 , respectively. 
     F: an output buffer register having a 4-bit capacity. 
     G 15  : an input gate which enables the contents of the accumulator ACC to enter into F upon the development of  31 . 
     SD: an output decoder decodes the contents of the output buffer F into display segment signals SS 1  -SS n . 
     W: an output buffer register 
     SHC: a shift circuit for the output buffer register, which shifts the overall bit contents of the output buffer register W one bit to the right at a time in response to  32  or  33 . 
     G 16  : an input gate for the output buffer register W leads &#34;1&#34; and &#34;0&#34; into the first bit position of W upon  32  and  33 , respectively. Immediately before &#34;1&#34; or &#34;0&#34; enters into the first bit position of W the output buffer shift circuit SHC becomes operative. 
     NP: an output control flag F/F. 
     G 17  : an input gate to the output control flag F/F for receiving &#34;1&#34; and &#34;0&#34; upon the development of  34  and  35 , respectively. 
     G 18  : an output control gate provided for the buffer register W for providing the respective bit outputs thereof at one time only when the flag F/F NP is in the set state (1). The output signals of the W register are used as the key strobe signals. 
     J: a judge F/F 
     IV 1  -IV 4  : inverter circuits 
     G 19  : an input gate for the judge F/F J for transferring the state of an input KN 1  into J upon the development of  36 . In the case where KN 1  =0, J=1 because of intervention of the inverter IV 1 . 
     G 20  : an input gate for the judge F/F J adapted to transfer the state of an input KN 2  into J upon  37 . When KN 2  =0, J=1 because of intervention of the inverter IV 2 . 
     G 21  : an input gate for the judge F/F J adapted to transfer the state of an input KF 1  into J upon  38 . When KF 1  =0, J=1 because of the inverter IV 3 . 
     G 22  : an input gate for the judge F/F J adapted to transfer the state of the input KF 2  into J upon  39 . When KF 2  =0, J=1 because of the intervening inverter IV 4 . 
     G 23  : an input gate provided for the judge flip flop J for transmission of the state of an input AK into J upon the development of 40 . When AK=1, J=1. 
     G 24  : an input gate G 24  is provided for the judge flip flop J to transmit the state of an input TAB into J pursuant to  41 . When TAB=1, J=1. 
     G 25  : a gate provided for setting the judge F/F J upon the development of  46 . 
     V 1  : a comparator compares the contents of the memory digit address counter BL with preselected data and provides an output &#34;1&#34; if there is agreement. The comparator V 1  becomes operative when  43  or  44  is developed. 
     G 26  : an input gate to the comparator V 1 . The data n 1  to be compared is a specific higher address value which is often available in controlling the RAM. n 1  and n 2  are provided for comparison purposes upon the development of  43  and  44 , respectively. 
     G 27  : an input gate provided for the decision F/F J to enter &#34;1&#34; into J when the carry F/F C assumes &#34;1&#34; upon the development of  45 . 
     DC 6  : a decoder decodes the operand I A  and helps decisions as to whether or not the contents of a desired bit position of the RAM are &#34;1&#34;. 
     G 28  : a gate transfers the contents of the RAM as specified by the operand decoder DC 6  into the judge F/F when  46  is derived. When the specified bit position of the RAM assumes &#34;1&#34;, J=1. 
     V 2  : a comparator decides whether or not the contents of the accumulator ACC are equal to the operand I A  and provides an output &#34;1&#34; when the affirmative answer is provided. The comparator V 2  becomes operative according to  47 . 
     V 3  : a comparator decides under  48  whether the contents of the memory digit address counter BL are equal to the operand I A  and provides an output &#34;1&#34; when the affirmative answer is obtained. 
     V 4  : a comparator decides whether the contents of the accumulator ACC agree with the contents of the RAM and provides an output &#34;1&#34; in the presence of the agreement. 
     G 29  : a gate which transfers the fourth bit carry C 4  occurring during addition into the judge F/F J. Upon the development of 50 C 4  is sent to F/F J. J=1 in the presence of C 4 . 
     F A  : a flag F/F 
     G 31  : an input gate to the flag F/F FA which provides outputs &#34;1&#34; and &#34;0&#34; upon the development of  52  and  53 , respectively. 
     G 32  : an input gate provided for setting the judge F/F J when the flag flip flop FA assumes &#34;1&#34;. 
     F B  : a flag F/F 
     G 33  : an input gate for the flag F/F, which provides outputs &#34;1&#34; and &#34;0&#34; upon  55  and  56 , respectively. 
     G 34  : an input gate for the judge flip flop J is adapted to transfer the contents of the flag flip flop F B  into the F/F J upon the development of  52 . 
     G 44  : an input gate to the judge F/F J to transfer the contents of the input under control of  68 . J=1 when α=1. 
     G 35  : an input gate associated with the judge F/F J is provided for transmission of the contents of an input β upon  19 . When β=1, J=1. 
     G 45  : a gate to transfer the contents of the accumulator ACC into the input output terminal D 1/O  of the displaying data storage area DRM upon receipt of  73 . 
     G 36  : an input gate associated with the accumulator ACC is provided for transferring the output of the adder AD 4  upon  26  and transferring the contents of the accumulator ACC after being inverted by an inverter IV 5  upon  27 . The contents of the memory RAM are transferred upon  28 , the operand I A  upon  13 , the 4 bit input contents k 1  -k 4  upon  57 , and the contents of the stack register SA upon  59 . The data from the storage area DRM are fed via D I/O  upon  72 . 
     IV 5  : an inverter circuit 
     SA: a stack register provides the output outside the present system. 
     SX: a stack register which also provides the output outside the system. 
     G 37  : an input gate associated with the stack register SA transfers the accumulator ACC upon  58 . 
     G 38  : an input gate associated with the stack register SX transfers the contents of the temporary register X upon  58 . 
     SP: a program stack register 
     G 39  : an input gate associated with the program stack register for loading the contents of the program counter PL incremented by &#34;1&#34; through the adder into the program stack register upon  60 . 
     An illustrative example of the instruction codes contained within the ROM of the CPU structure, the name and function of the instruction codes and the control instructions developed pursuant to the instruction codes will now be tabulated in Table 1 wherein the following correspondences exist A: the instruction codes, B: the instruction name, C: the instruction description and D: the CPU control instructions. 
     
                                           TABLE 1__________________________________________________________________________A         B      D__________________________________________________________________________1 I.sub.O SKIP ○422 I.sub.O AD   ○23 ,○263 I.sub.O ADC  ○23 ,○26 ,○25 ,○14 I.sub.O ADCSK          ○23 ,○26 ,○25 ,○50 ,○1          15 I.sub.O I.sub.A     ADI  ○24 ,○26 ,○506 I.sub.O I.sub.A     DC   ○24 ,○26 ,○507 I.sub.O SC   ○218 I.sub.O RC   ○229 I.sub.O I.sub.A     SM   ○210  I.sub.O I.sub.A     RM   ○311  I.sub.O COMA ○2712  I.sub.O I.sub.A     LDI  ○1313  I.sub.O I.sub.A     L    ○28 ,○814  I.sub.O I.sub.A     LI   ○28 ,○8 ,○15 ,○10 ,○43          415  I.sub.O I.sub.A     XD   ○28 ,○8 ,○14 ,○15 ,○10          ,○ 4416  I.sub.O I.sub.A     X    ○28 ,○4 ,○817  I.sub.O I.sub.A     XI   ○28 ,○4 ,○8 ,○15 ,○10          ,○4318  I.sub.O I.sub.A     XD   ○28 ,○4 ,○8 ,○14 ,○15          ,○10 ,○4419  I.sub.O I.sub.A     LBLI ○1120  I.sub.OI.sub.A  I.sub.B     LB   ○8 ,○1221  I.sub.O I.sub.A     ABLI ○16 ,○10 ,○4322  I.sub.O I.sub.A     ABMI ○6 ,○723  I.sub.O I.sub.A     T    ○2024  I.sub.O SKC  ○4525  I.sub.O I.sub.A     SKM  ○4626  I.sub.O I.sub.A     SKBI ○4827  I.sub.O I.sub.A     SKAI ○4728  I.sub.O SKAM ○4929  I.sub.O SKN.sub.1          ○3630  I.sub.O SKN.sub.2          ○3731  I.sub.O SKF.sub.1          ○3832  I.sub.O SKF.sub.2          ○3933  I.sub.O SKAK ○4034  I.sub.O SKTAB          ○4135  I.sub.O SKFA ○5136  I.sub.O SKEB ○5437  I.sub.O WIS  ○3238  I.sub.O WIR  ○3339  I.sub.O NPS  ○3440  I.sub.O NPR  ○3541  I.sub.O ATF  ○3142  I.sub.O LXA  ○2943  I.sub.O XAX  ○29 ,○3044  I.sub.O SFA  ○5245  I.sub.O RFA  ○5346  I.sub.O SFB  ○5547  I.sub.O RFB  ○5648  I.sub.O SFC  ○1749  I.sub.O RFC  ○1850  I.sub.O SFD  ○6251  I.sub.O RFD  ○6352  I.sub.O SFE  ○6553  I.sub.O RFE  ○6654  I.sub.O SKA  ○6855  I.sub.O SKB  ○1956  I.sub.O KTA  ○5757  I.sub.O STPO ○5858  I.sub.O EXPO ○58 ,○5959  I.sub.O I.sub. A     TML  ○62 ,○2060  I.sub.O RIT  ○6161  I.sub.OI.sub.A  I.sub.B     LNI  ○6962  I.sub.O READ ○70 ,○7263  I.sub.O STOR ○71 ,○7364  I.sub.O I.sub.A     EX   ○28 ,○4 ,○75 ,○1665  I.sub.O DECB ○74 ,__________________________________________________________________________ 
    
     Instruction Description (C) 
     (1) SKIP 
     Only the program counter PL is incremented without executing a next program step instruction, thus skipping a program step. 
     (2) AD 
     A binary addition is effected on the contents of the accumulator ACC and the contents of the RAM, the addition results being loaded back into the accumulator ACC. 
     (3) ADC 
     A binary addition is effected on the contents of the accumulator ACC, the memory RAM and the carry F/F C, the results being loaded back to the accumulator ACC. 
     (4) ADCSK 
     A binary addition is effected on the contents of the accumulator ACC, the memory RAM and the carry flip flop C, the results being loaded into the accumulator ACC. If the fourth bit carry C 4  occurs in the results, then a next program step is skipped. 
     (5) ADI 
     A binary addition is effected upon the contents of the accumulator ACC and the operand I A  and the results are loaded into the accumulator ACC. If the fourth bit carry C 4  is developed in the addition results, then a next program step is skipped. 
     (6) DC 
     The operand I A  is fixed as &#34;1010&#34; (a decimal number &#34;10&#34;) and a binary addition is effected on the contents of the accumulator ACC and the operand I A  in the same way as in the ADI instruction. The decimal number 10 is added to the contents of the accumulator ACC, the results of the addition being loaded into ACC. 
     (7) SC 
     The carry F/F C is set (&#34;1&#34; enters into C). 
     (8) RC 
     The carry F/F C is reset (&#34;0&#34; enters into C). 
     (9) SM 
     The contents of the operand I A  are decoded to give access to a desired bit position of the memroy specified by the operand (&#34;1&#34; enters). 
     (10) RM 
     The contents of the operand I A  are interpreted to reset a desired bit position of the memory specified by the operand (&#34;0&#34; enters). 
     (11) COMA 
     The respective bits of the accumulator ACC are inverted and the resulting complement to &#34;15&#34; is introduced into ACC. 
     (12) LDI 
     The operand I A  enters into the accumulator ACC. 
     (13) L 
     The contents of the memory RAM are sent to the accumulator ACC and the operand I A  to the file address counter BM. 
     (14) LI 
     The contents of the memory RAM are sent to the accumulator ACC and the operand I A  to the memory file address counter BM. At this time the memory digit address counter BL is incremented. If the contents of BL agree with the preselected value n 1 , then a next program step is skipped. 
     (15) XD 
     The contents of the memory RAM are exchanged with the contents of ACC and the operand I A  is sent to the memory file address counter BM. The memory digit address counter BL is decremented. In the event that the contents of BL agree with the preselected value n 2 , then a next program step is skipped. 
     (16) X 
     The contents of the memory RAM are exchanged with the contents of the accumulator ACC and the operand I A  is loaded into the memory file address counter BM. 
     (17) XI 
     The contents of the memory RAM are exchanged with the contents of the accumulator ACC and the operand I A  is sent to the memory file address counter BM. The memory digit address counter BL is incremented. In the event that BL is equal to the preselected value n 1 , a next program step is skipped. 
     (18) XD 
     The contents of the memory RAM replaces the contents of the accumulator ACC, the operand I A  being sent to the memory file address counter BM. The memory digit address counter BL at this time is incremented. If the contents of BL are equal to n 2 , then a next program step is skipped. 
     (19) LBLI 
     The operand I A  is loaded into the memory digit address counter BL. 
     (20) LB 
     The operand I A  is loaded into the memory file address counter BM and the operand B to the memory digit address counter BL. 
     (21) ABLI 
     The operand I A  is added to the contents of the memory digit address counter BL in a binary addition fashion, the results being loaded back to BL. If the contents of BL are equal to n 1 , then no next program step is carried out. 
     (22) ABMI 
     The operand I A  is added to the contents of the memory file address counter BM in a binary fashion, the results being loaded into BM. 
     (23) T 
     The operand I A  is loaded into the program step counter PL. 
     (24) SKC 
     If the carry flip flop C is &#34;1&#34;, then no next program step is taken. 
     (25) SKM 
     The contents of the operand I A  are decoded and a next program step is skipped as long as a specific bit position of the memory specified by the operand I A  assumes &#34;1&#34;. 
     (26) SKBI 
     The contents of the memory digit address counter BL are compared with the operand I A  and a next succeeding program step is skipped when there is agreement. 
     (27) SKAI 
     The contents of the accumulator ACC are compared with the operand I A  and if both are equal to each other a next program step is skipped. 
     (28) SKAM 
     The contents of the accumulator ACC are compared with the contents of the RAM and if both are equal a next program step is skipped. 
     (29) SKN 1   
     When the input KN 1  is &#34;0&#34;, a next program step is skipped. 
     (30) SKN 2   
     When the input KN 2  is &#34;0&#34;, a next program step is skipped. 
     (31) SKF 1   
     When the input KF 1  is &#34;0&#34;, a next program step is skipped. 
     (32) SKF 2   
     When the input KF 2  is &#34;0&#34;, a next program step is skipped. 
     (33) SKAK 
     When the input AK is &#34;1&#34;, a next program step is skipped. 
     (34) SKTAB 
     When the input TAB is &#34;1&#34;, a next program step is skipped. 
     (35) SKFA 
     When the flag flip flop F/A assumes &#34;1&#34; a next program step is skipped. 
     (36) SKFB 
     When the flag flip flop F B  assumes &#34;1&#34;, a next program step is skipped. 
     (37) WIS 
     The contents of the output buffer register W are one bit right shifted, the first bit position (the most significant bit position) receiving &#34;1&#34;. 
     (38) WIR 
     The contents of the output buffer register W are one bit right shifted, the first bit position (the most significant bit position being loaded with &#34;0&#34;. 
     (39) NPS 
     The output control F/F N p  for the buffer register W is set (&#34;1&#34; enters). 
     (40) NPR 
     The buffer register output control flip flop N p  is reset (&#34;0&#34; enters therein). 
     (41) ATF 
     The contents of the accumulator ACC are transferred into the output buffer register F. 
     (42) LXA 
     The contents of the accumulator ACC are unloaded into the temporary register X. 
     (43) XAX 
     The contents of the accumulator ACC are exchanged with the contents of the temporary register X. 
     (44) SFA 
     The flag F/F FA is set (an input of &#34;1&#34;). 
     (45) RFA 
     The flag F/F FA is reset (an input of &#34;0&#34;). 
     (46) SFB 
     The flag flip flop F B  is set (an input of &#34;1&#34;). 
     (47) RFB 
     The flag flip flop F B  is reset (an input of &#34;0&#34;). 
     (48) SFC 
     An input testing flag F/F F C  is set (an input of &#34;1&#34;). 
     (49) RFC 
     The input testing flag F/F F C  is reset (an input of &#34;0&#34;). 
     (50) SFC 
     The input testing flag F/F F D  is set (an input of &#34;1&#34;). 
     (51) RFD 
     The input testing flag F/F F D  is reset (an input of &#34;0&#34;). 
     (52) SFE 
     The input testing flag F/F F E  is set (an input of &#34;1&#34;). 
     (53) RFE 
     The input testing flag F/F F E  is set (an input of &#34;1&#34;). 
     (54) SKA 
     When an input α is &#34;1&#34;, a next program step is skipped. 
     (55) SKB 
     When an input β is &#34;1&#34;, a next program step is skipped. 
     (56) KTA 
     The inputs k 1  -k 4  are introduced into the accumulator ACC. 
     (57) STPO 
     The contents of the accumulator ACC are sent to the stack register SA and the contents of the temporary register X to the stack register SX. 
     (58) EXPO 
     The contents of the accumulator ACC are exchanged with the stack register SA and the contents of the temporary register X with the stack register SX. 
     (59) TML 
     The contents of the program counter P L  incremented by one are transferred into the program stack register SP and the operand I A  into the program counter P L . 
     (60) RIT 
     The contents of the program stack register SP are transmitted into the program counter P L . 
     Table 2 sets forth the relationship between the operation codes contained within the ROM of the CPU structure and the operand. 
     
                       TABLE 4______________________________________ ##STR1## ##STR2## ##STR3## ##STR4## ##STR5##______________________________________ wherein I.sub.O : the operation codes and I.sub.A, I.sub.B : the operands 
    
     Taking an example wherein the output of the read only memory ROM is 10 bit long, the instructoin decoder DC 5  decides whether the instruction AD or COMA (see TAble 1) assumes &#34;0001011000&#34; or &#34;0001011111&#34; and develops the control instructions  23 , 26 , or  27 . SKBI is identified by the fact that the upper six bits assume &#34;000110&#34;, the lower 4 bits &#34;0010&#34; being treated as the operand I A  and the remaining ninth and tenth bits &#34;11&#34; as the operand I B . The operand forms part of instruction words and specifies data and addresses for next succeeding instructions and can be called an address area of an instruction. 
     Major processing operaitons (a processing list) of the CPU structure will now be described in sufficient detail. 
     [PROCESSING LIST] 
     (I) A same numeral N is loaded into a specific region of the memory RAM (NNN→X) 
     (II) A predetermined number of different numerals are loaded into a specific region of the memory (N 1 , N 2 , N 3 , . . . →X) 
     (III) The contents of a specific region of the memory are transferred into a different region of the memory (X→Y) 
     (IV) The contents of a specific region of the memory are exchanged with that of a different region (X←→Y) 
     (V) A given numeral N is added or subtracted in a binary fashion from the contents of a specific region of the memory (X±N) 
     (VI) The contents of a specific region of the memory are added in a decimal fashion to the contents of a different region (X±Y) 
     (VII) The contents of a specific region of the memory are one digit shifted (X right, X left). 
     (VIII) A one bit conditional F/F associated with a specific region of the memory is set or reset (F set, F reset) 
     (IX) The state of the one bit conditional F/F associated with a specific region of the memory is sensed and a next succeeding program address is changed according to the results of the state detection. 
     (X) It is decided whether the digit contents of a specific region of the memory reach a preselected numeral and a next succeeding program step is altered according to the results of such decision. 
     (XI) It is decided whether the plural digit contents of a specific region of the memory are equal to a preselected numeral and a program step is altered according to the results of the decision. 
     (XII) It is decided whether the digit contents of a specific region of the memory are smaller than a given value and a program step to be next executed is changed according to the decision. 
     (XIII) It is decided whether the contents of a specific region of the memory are greater than a given value and the results of such decision alter a program step to be next executed. 
     (XIV) The contents of a specific region of the memory are displayed. 
     (XV) What kind of a key switch is actuated is decided. 
     The above processing events in (1)-(15) above are executed according to the instruction codes step by step in the following manner. 
     (I) PROCEDURE OF LOADING A SAME VALUE N INTO A SPECIFIC REGION OF THE MEMORY (NNN→X) 
     
         ______________________________________(Type 1)______________________________________ ##STR6##______________________________________ 
    
     P 1  . . . The first digit position of the memory to be processed is specified by a file address m A  and a digit address n E . 
     P 2  . . . The value N is loaded into ACC. 
     P 3  . . . The value N is loaded into the specified region of the memory by exchange between the memory and ACC. With no change in the file address of the memory, m A  is specified and the digit address is decremented to determine a digit to be next introduced. By determing n 2  as the final digit value n A  to be introduced, the next step P 4  is skipped to complete the processing of the Type 1 since BL=n 2  under the condition that the value N has been completely loaded into the specific region. 
     P 4  . . . LDI and XD are carried out repeatedly from the program address P 2  up to BL=V. 
     
         ______________________________________(Type 2)______________________________________ ##STR7##______________________________________ 
    
     P 1  . . . The digit of the memory to be processed is determined by the file address m B  and the digit address n C . 
     P 2  . . . The ACC is loaded with the value N. 
     P 3  . . . By exchange between the memory and ACC the value N is loaded into the above specified region of the memory. This completes the processing of Type 2. An operand area of X D  is necessary to the next succeeding proce-s and not to this step. 
     
         ______________________________________(Type 3)______________________________________ ##STR8##______________________________________ 
    
     P 1  . . . The first digit of the memory to be processed is specified by the file address m C  and the digit address n O . 
     P 2  . . . The ACC is loaded with the value N. 
     P 3  . . . By exchange between the memory and ACC the value N is loaded into that specified region of the memory. With no change in the file address of the memory m C  is specified and the digit address is decremented in order to determine the digit to be next loaded therein. 
     P 4  . . . It is decided whether the digit processed during the step P 3  is the final digit n B . If it is n B , then the digit address is decremented to n A . An operand area of the SKI instruction is occupied by n A , thus loading the final digit with the value N. In reaching P 4 , conditions are fulfilled and the next step P 5  is skipped, thereby terminating the type 3. If the conditions are not fulfilled, P 5  is then reached. 
     P 5  . . . The program address P 2  is specified and P 2  -P 4  are repeated until BL=n A . 
     (II) PROCEDURE OF LOADING A PREDETERMINED NUMBER OF DIFFERENT VALUES INTO A SPECIFIC REGION OF THE MEMORY (N 1 , N 2 , N 3 , . . . →X) 
     
         ______________________________________(Type 1) For example, for digit values N.sub.4 N.sub.3 N.sub.2 N.sub.1areloaded an arbitraray digit position in the same manner -as______________________________________above. ##STR9##______________________________________ 
    
     P 1  . . . The first processed digit position of the memory is specified by the file address m A  and the digit address n E . 
     P 2  . . . A constant N 1  is loaded into ACC. 
     P 3  . . . Through exchange between the memory and the ACC the value N 1  is loaded into the above specified region of the memory. The file address of the memory remains unchanged as m A , whereas the digit address is up for introduction of the next digit. 
     P 4  . . . A second constnat N 2  is loaded into ACC. 
     P 5  . . . Since the second digit of the memory has been specified during P 3 , the second constant N 2  is loaded into the second digit position of the memory through exchange between the memory and ACC. 
     P 6  -P 9  . . . The same as in the above paragraph. 
     
         ______________________________________(Type 2)Any value of 0-15 is loaded into a predetermined register.______________________________________ ##STR10##______________________________________ 
    
     P 1  . . . The value N is loaded into ACC. 
     P 2  . . . The value N is transmitted from ACC into the register X. 
     (III) PROCEDURE OF TRANSFERRING THE CONTENTS OF A SPECIFIC REGION OF THE MEMORY TO A DIFFERENT REGION OF THE MEMORY (X→Y) 
     
         ______________________________________(Type 1)______________________________________ ##STR11##______________________________________ 
    
     P 1  . . . The first memory file address is specified as m A  and the first digit address as n E . 
     P 2  . . . The contents of the first digit position of the memory are loaded into ACC and its designation, the second memory file address is specified as m B  prior to the transmission step P 3 . 
     P 3  . . . The first digit memory contents loaded into the ACC are replaced by the same second memory digit contents so that the first memory contents are transmitted into the second memory. In order to repeat the above process, the first memory file address m A  is again set. The value of the final digit n A  to be transmitted is previously selected to be n 1 . Since BL→n 1  after the overall first memory contents have been sent to the second memory, the next step P 4  is skipped to complete the processing of Type 1. The digit address is progressively incremented until BL=V (the final digit). Through the step P 4  the file address is set up at m A  to lead back to P 2 , thereby specifying the first memory. 
     P 4  . . . The program address is set at the step P 2  and the instructions P 2  and P 3  are repeatedly executed until BL=n 1 . The transmission step is advanced digit by digit. 
     
         ______________________________________(Type 2)______________________________________ ##STR12##______________________________________ 
    
     P 1  . . . The region of the memory to be processed is determined by the file address m A  and the digit address n C . 
     P 2  . . . The contents of the memory as specified above are unloaded into ACC and the memory file address is set at m C  prior to the next transmission step P 4 . 
     P 3  . . . The digit address of the memory, the destination for the transmission process, is specified as m C . The destinated region of the memory is specified via the steps P 2  and P 3 . 
     P 4  . . . The contents of ACC are exchanged with the contents of the regions of the memory specified bu P 2  and P 3 . The operand of X has no connection with the present process. 
     
         ______________________________________(Type 3)______________________________________ ##STR13##______________________________________ 
    
     P 1  . . . The region of the memory to be processed is identified by the file address m A  and the digit address n C . 
     P 2  . . . The contents of the memory region specified during P 1  are unloaded into ACC. 
     P 3  . . . The contents of the memory transmitted from ACC are sent to the register X, completing the type 3 processing. 
     (IV) PROCEDURE OF EXCHANGING CONTENTS BETWEEN A SPECIFIC REGION OF THE MEMORY AND A DIFFERENT REGION (X→Y) 
     
         ______________________________________(Type 1)______________________________________ ##STR14##______________________________________ 
    
     P 1  . . . The first memory file address to be processed is specified as m A  and the first digit address as n E . 
     P 2  . . . The specific digit contents of the first memory are loaded into ACC and the second memory file address is specified as m B  for preparation of the next step. 
     P 3  . . . The specific digit contents of the first memory contained within ACC are exchanged with the same digit contents of the second memory specified by P 2 . The file address of the first memory is specified as m A  in order to load the contents of the memory now in ACC into the first memory. 
     P 4  . . . The contents of the second memory now in ACC are exchanged with the contents of the first memory at the corresponding digit positions so that the contents of the second memory are transferred to the first memory. Exchanges are carried out during the steps P 2  -P 4 . The first memory is specified on by the file address m A , while the digit address is incremented to select a next address. Exchange is carried out progressively digit by digit. The final digit value n A  is previously set at n 1  such that B L  =n 1  after the exchange operation between the first memory and the second has been effected throughout the all digit positions, thus skipping the next step P 5  and completing the processing of Type 1. 
     P 5  . . . The program address P 2  is selected and the instructions for P 2  to P 4  are executed repeatedly until B L  =n 1 . The exchange operation is advanced digit by digit. 
     
         ______________________________________(Type 2)______________________________________ ##STR15##______________________________________ 
    
     P 1  . . . The file address of the first memory to be processed is specified as m A  and the digit address as n C . 
     P 2  . . . The contents of the specific digit position of the first memory are unloaded into ACC and the file address of the second memory is specified as m C  and ready to exchange. 
     P 3  . . . The digit address of the second memory, the destination for the exchange process, is specified as n O  to determine the destinated memory address. 
     P 4  . . . The contents of the first memory now within ACC are exchanged with that of the second memory. At the same time the file address m B  of the first memory is again specified to transfer the contents of the first memory to the first memory. 
     P 5  . . . The digit address n C  of the first memory is specified to determine the destination address of the first memory. 
     P 6  . . . The contents of the second memory now within ACC are exchanged with the contents of the first memory. 
     
         ______________________________________(Type 3)______________________________________ ##STR16##______________________________________ 
    
     P 1  . . . The file address m A  of the first memory to be processed is specified and the digit address n C  is specified. 
     P 2  . . . The contents of the first memory are loaded into ACC and the file address m C  of the second memory is selected. 
     P 3  . . . The exchange is carried out between the first and second memory so that the contents of the first memory are loaded into the second memory. Prior to the step P 4  the file address m B  of the first memory is selected again. 
     P 4  . . . The exchange is effected between the contents of the second memory and the first memory. 
     
         ______________________________________(Type 4)______________________________________ ##STR17##______________________________________ 
    
     P 1  . . . The region of the memory to be processed is specified by the file address m A  and the digit address n C . 
     P 2  . . . The contents of the memory region specified in P 1  above are loaded into ACC. The file address m B  is kept being selected prior to the exchange with the contents of the register X. 
     P 3  . . . The exchange is effected between ACC and the register X so that the contents of the memory are shifted to the register X. 
     P 4  . . . Through the exchange between ACC containing the contents of the register X and the memory, the contents of the register X are substantially transferred into the memory, thus accomplishing the Type 4 processing. 
     (V) PROCEDURE OF EFFECTING A BINARY ADDITION OR SUBTRACTION OF A GIVEN VALUE N ONTO A SPECIFIC REGION OF THE MEMORY 
     
         ______________________________________ ##STR18## 
    
     
         ______________________________________ ##STR19##______________________________________ 
    
     P 1  . . . The region of the memory to be processed is specified by the file address m B  and the digit address n C . 
     P 2  . . . The contents of the memory specified by the step P 1  are unloaded into ACC. The memory file address is set again at m B  to specify the same memory. 
     P 3  . . . The operand specifies the value N to be added and the contents of the memory contained within ACC are added with the value N, the results being loaded back to ACC. 
     P 4  . . . The sum contained with ACC is exchanged with the contents of the memory specified by the step P 2 , thus completing the Type 1 processing. 
     
         ______________________________________ ##STR20## 
    
     
         ______________________________________ ##STR21##______________________________________ 
    
     P 1  . . . The exchange is effected between the register X and ACC. 
     P 2  . . . The operand specifies the value N to be added and an addition is carried out on the contents of the register X now within ACC and the value N, with the results back to ACC. 
     P 3  . . . Through the exchange between the resulting sum within ACC and the contents of the register X, the processing of Type 2 (X+N→X) is performed. 
     
         ______________________________________ ##STR22## 
    
     
         ______________________________________ ##STR23##______________________________________ 
    
     P 1  . . . The region of the first memory to be processed is decided by the file address m B  and the digit address n C . 
     P 2  . . . The contents of the memory specified by P 1  are loaded into ACC. The file address m C  of the second memory is specified to return addition results to the second memory. 
     P 3  . . . The operand specifies the value N to be added and the value N is added to the contents of the memory now within ACC, with the results being loaded into ACC. 
     P 4  . . . The resulting sum within ACC is exchanged with the contents of the second memory as specified by P 2 , thus completing the processing of Type 3. 
     
         ______________________________________ ##STR24## 
    
     
         ______________________________________ ##STR25##______________________________________ 
    
     P 1  . . . There are specified the file address m B  and the digit address n C  of the memory to be processed. 
     P 2  . . . Subtraction is carried out in such a way that the complement of a subtrahend is added to a minuend and the F/F C remains set because of the absence of a borrow from a lower digit position. 
     P 3  . . . ACC is loaded with the subtrahend N. 
     P 4  . . . The complement of the subtrahend to &#34;15&#34; is evaluated and loaded into ACC. 
     P 5  . . . In the event that any borrow occurs during the subtraction, the complement of the subtrahend to &#34;16&#34; is added to the minuend. If a borrow free state is denoted as C=1, then a straight binary subtraction of ACC+C+M→ACC is effected. 
     P 6  . . . The resulting difference during P 5  is returned to the same memory through the exchange between ACC and that memory. 
     
         ______________________________________ ##STR26## 
    
     
         ______________________________________ ##STR27##______________________________________ 
    
     P 6  . . . To load the resulting difference during P 5  into the second memory, the file address m C  and the digit address n C  of the second memory are selected. 
     P 7  . . . Through exchange the resulting difference is transferred from ACC into the second memory as specified by the step P 6 . 
     
         ______________________________________(Type 6)______________________________________ ##STR28##______________________________________ 
    
     P 1  . . . The file address m B  and the digit address n C  of the memory ready for the step P 5  are selected. 
     P 2  . . . Subtraction is carried out in the manner of adding the complement of a subtrahend to a minuend and the F/F C remains set because of the absence of a borrow from a lower digit position. 
     P 3  . . . ACC is loaded with the subtrahend N. 
     P 4  . . . The complement of the subtrahend to &#34;15&#34; is evaluated and loaded into ACC. 
     P 5  . . . To accomplish calculations with the contents of the register X, the memory as specified by P 1  is loaded with the contents of ACC. 
     P 6  . . . The contents of the register X are transmitted into ACC through the exchange process. After this step the memory contains the complement of the subtrahend to &#34;15&#34; and ACC contains the contents of X. 
     P 7  . . . ACC+M+C corresponds to X-N and the results of a binary subtraction are loaded into ACC. 
     P 8  . . . The contents of ACC are exchanged with the contents of X and the value of X-N is transmitted into X, thereby completing the processing of Type 6. 
     
         ______________________________________ ##STR29## 
    
     
         ______________________________________ ##STR30##______________________________________ 
    
     P 1  . . . The file address m B  and the digit address n C  of the memory to be processed are selected. 
     P 2  . . . One-digit subtraction is effected in the manner of adding the complement of a subtrahend to a minuend, in which case F/F C remains set. 
     P 3  . . . ACC is loaded with a minuend. 
     P 4  . . . The exchange is effected between the memory (the subtrahend) and ACC and the memory file address remains as m B  for preparation of P 7 . 
     P 5  . . . The complement of a subtrahend in ACC to &#34;15&#34; is evaluated and loaded into ACC. 
     P 6  . . . In the event that there is no borrow from a lower digit position, the complement of a subtrahend to &#34;16&#34; is added to a minuend. If a borrowless state is denoted as C=1, then N-M is substantially executed by ACC+C+M, the resulting difference being loaded into ACC. 
     P 7  . . . Since the memory file address remains unchanged during P 4 , the difference is unloaded from ACC back to the memory, thus completing the processing of Type 7. 
     
         ______________________________________ ##STR31## 
    
     
         ______________________________________ ##STR32##______________________________________ 
    
     P 1  . . . The file address m B  and the digit address n C  of the memory to be processed are selected. 
     P 2  . . . The contents specified by the step P 1  and corresponding to a subtrahend are loaded into ACC. The file address m C  of the second memory is specified for preparation of a step P 5 . 
     P 3  . . . The complement of the subtrahend to &#34;15&#34; is evaluated and loaded into ACC. 
     P 4  . . . The operand is made a minuend plug &#34;1&#34;. This subtraction is one digit long and accomplished by adding the complement of the subtrahend to the minuend. A conventional complementary addition is defined as ACC+C+M as in the Type 7 processing in the absence of a borrow as defined by C=1. Since the ADI instruction carries C, ACC+1 is processed in advance. This completes the processing of Type 8 of N-M, the results being stored within ACC. 
     P 5  . . . The difference obtained from the step P 4  is transmitted into the second memory specified by P 2 . 
     
         ______________________________________ ##STR33## 
    
     
         ______________________________________ ##STR34##______________________________________ 
    
     P 1  . . . (When M+1) ACC is loaded with a binary number &#34;0001&#34; (=1). 
     P 1&#39;   . . . (When M-1) ACC is loaded with a binary number &#34;1111&#34; (=15). 
     P 2  . . . The file address m B  and the digit address n C  of the memory to be processed are selected. 
     P 3  . . . The contents of the memory specified by P 2  are added to the contents contained within ACC during P 1  or P 1  &#39;, the sum thereof being loaded into ACC. In the case of P 1  ACC+1 and in the case of P 1  &#39; ACC-1. 
     P 4  . . . The results are unloaded from ACC to the original memory position, thus completing the processing fashion of Type 9. 
     (VI) PROCEDURE OF EFFECTING A DECIMAL ADDITION OR SUBTRACTION BETWEEN A SPECIFIC REGION OF THE MEMORY AND A DIFFERENT REGION 
     
         ______________________________________ ##STR35## 
    
     
         ______________________________________ ##STR36##______________________________________ 
    
     P 1  . . . The first digit position of the first memory to be processed is identified by the file address m A  and the digit address n E . 
     P 2  . . . The carry F/F C is reset because of a carry from a lower digit position in effecting a first digit addition. 
     P 3  . . . The contents of the specific digit position of the first memory are loaded into ACC and the file address m B  of the second memory is selected in advance of additions with the contents of the second memory during P 4 . 
     P 4  . . . &#34;6&#34; is added to the contents of the specific digit position of the first memory now loaded into ACC for the next succeeding step P 5  wherein a decimal carry is sensed during addition. 
     P 5  . . . ACC already receives the contents of the first memory compensated with &#34;6&#34; and a straight binary addition is effected upon the contents of ACC and the contents of the second memory at the corresponding digit positions, the results being loaded back to ACC. In the event a carry is developed during the binary addition at the fourth bit position, P 7  is reached without passing P 6 . The presence of the carry during the fourth bit addition implies the development of a decimal carry. 
     P 6  . . . In the event the decimal carry failed to develop during the addition P 5 , &#34;6&#34; for the process P 4  is overruded. An addition of &#34;10&#34; is same as a subtraction of &#34;6&#34;. 
     P 7  . . . The one-digit decimal sum is unloaded from ACC into the second memory and the digit address is incremented for a next digit addition and the file address m A  of the first memory is selected. The final digit to be added is previously set at n 1 . Since BL=n 1  after the overall digit addition is effected upon the first and second memory, the next succeeding step P 8  is skipped to thereby complete the processing of Type 1. 
     P 8  . . . The program address P 3  is selected and the instructions P 3  -P 7  are repeatedly executed until BL=n 1 . A decimal addition is effected digit by digit. 
     
         ______________________________________ ##STR37## 
    
     
         ______________________________________ ##STR38##______________________________________ 
    
     P 1  . . . The first digit position of the first memory to be processed is specified by the file address m A  and the digit address n E . 
     P 2  . . . Subtraction is performed in the manner of adding the complement of a subtrahend to a minuend and F/F C is set because of the absence of a borrow from a lower digit position during the first digit subtraction. 
     P 3  . . . The contents of the specific digits in the first memory, the subtrahend, are loaded into ACC and the file address m B  of the second memory is specified in advance of the step P 7  with the second memory. 
     P 4  . . . The complement of the subtrahend to &#34;15&#34; is evaluated and loaded into ACC. 
     P 5  . . . In the event that there is no borrow from a lower digit place, the complement of the subtrahend is added to the minuend to perform a subtraction. On the contrary, in the presence of a borrow, the complement of the subtrahend is added to the minuend. If a borrowless state is denoted as C=1, then a binary addition of ACC+C+M→ACC is effected. The development of a carry, as a consequence of the execution of the ADSCK instruction, implies failure to give rise to a borrow and leads to the step P 7  without the intervention of the step P 6 . Under these circumstances the addition is executed with the second memory, thus executing substantially subtraction between the first and second memories. 
     P 6  . . . In the case where no carry is developed during the execution of the ADCSK instruction by the step P 5 , the calculation results are of the sexadecimal notation and thus converted into a decimal code by subtraction of &#34;6&#34; (equal to addition of &#34;10&#34;). 
     P 7  . . . The resulting difference between the first and second memories is transmitted from ACC into the second memory. The digit address is incremented and the file address m A  of the first memory is specified in advance of a next succeeding digit subtraction. The final digit to be subtracted is previously determined as n 1 . Since BL=n 1  after the overall-digit subtraction has been completed, the next step P 8  is skipped to thereby conclude the processing of Type 2. 
     P 8  . . . After selection of the program address P 3  the instructions P 3  -P 7  are repeatedly executed until BL=n 1 . The decimal subtraction is advanced digit by digit. 
     (VII) PROCEDURE OF SHIFTING ONE DIGIT THE CONTENTS OF A SPECIFIC REGION OF THE MEMORY 
     
         ______________________________________(Type 1) Right Shift______________________________________ ##STR39##______________________________________ 
    
     P 1  . . . The file address m A  and the digit address n A  of the memory to be processed are determined. 
     P 2  . . . ACC is loaded with &#34;0&#34; and ready to introduce &#34;0&#34; into the most significant digit position when the right shift operation is effected. 
     P 3  . . . The exchange is carried out between XCC and the memory and the digit address is decremented to specific a one digit lower position. The memory address is still at m A . XD is repeated executed through P 4  and P 3 . By the step ACC←→M &#34;0&#34; is transmitted from ACC to the most significant digit position of the memory which in turn provides its original contents for ACC. When the digit address is down via B and XD is about to be executed at P 3  via P 4 , the second most significant digit is selected to contain the original content of the most significant digit position which has previously been contained within ACC. At this time ACC is allowed to contain the contents of the second most significant digit position. The least significant digit is previously selected as n 2 . If the transmission step reaches the least significant digit position BL=n 2  is satisfied and P 4  is skipped. In other words, the digit contents are shifted down to thereby conclude the processing of Type 1. 
     P 4  . . . XD is repeated at P 3  until BL=V. 
     
         ______________________________________(Type 2) Left Shift______________________________________ ##STR40##______________________________________ 
    
     P 1  . . . The file address m A  and the least significant digit n E  of the memory to be processed are determined. 
     P 2  . . . ACC is loaded with &#34;0&#34; and ready to introduce &#34;0&#34; into the least significant digit position when the left shift operation is started. 
     P 3  . . . The exchange is carried out between ACC and the memory and the digit address is incremented to specify a one digit upper position. The memory address is still at m A . XD is repeated executed through P 4  and P 3 . By the step ACC→M, &#34;0&#34; is transmitted from ACC to the least significant digit position of the memory which in turn provides its original contents for ACC. When the digit address is up via P 3  and XD is about to be executed at P 3  via P 4 , the second least significant digit is selected to contain the original content of the least significant digit position which has previously been contained within ACC. At this time ACC is allowed to contain the contents of the second least significant digit position. The most significant digit is previously selected as n 1 . If the transmission step reaches the most significant digit position, BL=n 1  is satisfied and P 4  is skipped. In other words, the digit contents are shifted up to thereby conclude the processing of Type 2. 
     P 4  . . . XI is repeated at P 3  until BL=V. 
     (VIII) PROCEDURE OF SETTING OR RESETTING A ONE-BIT CONDITION F/F ASSOCIATED WITH A SPECIFIC REGION OF THE MEMORY 
     
         ______________________________________(Type 1)______________________________________ ##STR41##______________________________________ 
    
     P 1  . . . The file address m B  and the digit address n C  of a region of the memory to be processed are determined. 
     P 2  . . . &#34;1&#34; is loaded into a desired bit N within the digit position of the memory specified by P 1 , thus concluding the processing of Type 1. 
     
         ______________________________________(Type 2)______________________________________ ##STR42##______________________________________ 
    
     P 1  . . . The file address m B  and the digit address n C  of a region of the memory to be processed are determined. 
     P 2  . . . &#34;0&#34; is loaded into a desired bit N within the digit position of the memory specified by P 1 , thus concluding the processing of Type 2. 
     (IX) PROCEDURE OF SENSING THE STATE OF THE ONE-BIT CONDITIONAL F/F ASSOCIATED WITH A SPECIFIC REGION OF THE MEMORY AND CHANGING A NEXT PROGRAM ADDRESS (STEP) AS A RESULT OF THE SENSING OPERATION 
     
         ______________________________________ ##STR43## 
    
     
         ______________________________________ 
    
     P 1  . . . There are specified the file address m B  and the digit address n C  where a desired one-bit conditional F/F is present. 
     P 2  . . . In the case where the contents of the bit position (corresponding to the conditional F/F) specified by N within the memory region as selected during P 1  assume &#34;1&#34;, the step proceeds to P 4  with skipping P 3 , thus executing the operation OP 1 . In the event that the desired bit position bears &#34;0&#34;, the next step P 3  is skipped. 
     P 3  . . . When the foregoing P 2  has been concluded as the conditional F/F in the &#34;0&#34; state, the program step P n  is selected in order to execute the operation OP 2 . 
     (X) PROCEDURE OF DECIDING WHETHER THE DIGIT CONTENTS OF A SPECIFIC REGION OF THEMEMORY REACH A PRESELECTED NUMERAL AND ALTERING A NEXT PROGRAM ADDRESS (STEP) ACCORDING TO THE RESULTS OF THE DECISION 
     
         ______________________________________ ##STR44## 
    
     
         ______________________________________ 
    
     P 1  . . . The region of the memory which contains contents to be decided is identified by the file address m B  and the digit address n C . 
     P 2  . . . The contents of the memory as identified during P 1  are unloaded into ACC. 
     P 3  . . . The contents of ACC are compared with the preselected value N and if there is agreement the step advances toward P 5  without executing P 4  to perform the operation OP 1 . P 4  is however reached if the contents of ACC are not equal to N. 
     P 4  . . . The program address (step) P n  is then selected to perform the operation OP 2 . 
     (XI) PROCEDURE OF DECIDING WHETHER THE PLURAL DIGIT CONTENTS OF A SPECIFIC REGION OF THE MEMORY ARE EQUAL TO A PRESELECTED NUMERAL AND ALTERING A PROGRAM STEP ACCORDING TO THE RESULTS OF THE DECISION 
     
         ______________________________________ ##STR45## 
    
     
         ______________________________________ 
    
     P 1  . . . The region of the memory to be judged is identified by the file address m B  and the first digit address n E . 
     P 2  . . . The value N is loaded into ACC for comparison. 
     P 3  . . . The value V within ACC is compared with the digit contents of the specific region of the memory and if there is agreement P 5  is reached without passing P 4  to advance the comparison operation toward the next succeeding digit. P 4  is selected in a non-agreement. 
     P 4  . . . In the case of a non-agreement during P 3  the program address (step) P n  is specified to execute the operation forthwith. 
     P 5  . . . The digit address is incremented by adding &#34;1&#34; thereto. This step is aimed at evaluating in sequence a plurality of digits within the memory. The ultimate digit to be evaluated is previously determined as (V). The comparison is repeated throughout the desired digit positions. If a non-agreement state occurs on the way, the operation OP 2  is accomplished through P 4 . In the case where the agreement state goes on till BL=V, there is selected P 7  rather than P 6  to perform the operation OP 1 . 
     P 6  . . . When the agreement state goes on during P 5 , P 3  is reverted for evaluation. 
     (XII) PROCEDURE OF DECIDING WHETHER THE CONTENTS OF A SPECIFIC REGION OF THE MEMORY ARE SMALLER THAN A GIVEN VALUE AND DECIDING WHICH ADDRESS (STEP) IS TO BE EXECUTED 
     
         ______________________________________ ##STR46## 
    
     
         ______________________________________ 
    
     P 1  . . . The file address m B  and the digit address n C  of the memory are decided. 
     P 2  . . . The contents of the memory as specified during P 1  are unloaded into ACC. 
     P 3  . . . N is the value to be compared with the contents of the memory and the operand area specifies 16-N which in turn is added to the contents of ACC, the sum thereof being loaded back to ACC. The occurrence of a fourth bit carry during the addition suggests that the result of the binary addition exceeds 16, that is, M+(16-N)≧16 and hence M≧N. The step is progressed toward P 4 . 
     P 4  . . . When M≧N is denied, the program step P n  is selected to carry out the operation OP 2 . 
     (XIII) PROCEDURE OF DECIDING WHETHER THE CONTENTS OF A SPECIFIC REGION OF THE MEMORY ARE GREATER THAN A GIVEN VALUE AND DECIDING WHICH ADDRESS (STEP) IS TO BE EXECUTED 
     
         ______________________________________ ##STR47## 
    
     
         ______________________________________ 
    
     P 1  . . . The file address m B  and the digit address n C  of the memory are decided. 
     P 2  . . . The contents of the memory as specified during P 1  are unloaded into ACC. 
     P 3  . . . N is the value to be compared with the contents of thememory and the operand area specifies 15-N which in turn is added to the contents of ACC, the sum thereof being loaded back to ACC. The occurrence of a fourth bit carry during the addition suggests that the results of binary addition exceeds 16, that is, M+(15-N)≧16 and hence M≧N+1 and M&gt;N. The step is progressed toward P 5  with skipping P 4 , thus performing the operation OP 1 . In the absence of a carry (namely, M&gt;N) the step P 4  is reached. 
     P 4  . . . When M≧N is denied, the program address (Step) P n  is selected to carry out the operation OP 2 . 
     (XIV) PROCEDURE OF DISPLAYING THE CONTENTS OF A SPECIFIC REGION OF THE MEMORY 
     
         ______________________________________(Type 1)______________________________________ ##STR48##______________________________________ 
    
     P 1  . . . The bit number n 1  of the buffer register W is loaded into ACC to reset the overall contents of the buffer register W for generating digit selection signals effective to drive a display panel on a time sharing basis. 
     P 2  . . . After the overall contents of the register W are one bit shifted to the right, its first bit is loaded with &#34;0&#34;. This procedure is repeated via P 4  until C 4  =1  during P 3 , thus resetting the overall contents of W. 
     P 3  . . . The operand I A  is decided as &#34;1111&#34; and AC+1111 is effected (this substantially corresponds to ACC-1). Since ACC is loaded with n 1  during P 1 , this process is repeated n 1  times. When the addition of &#34;1111&#34; is effected following ACC=0, the fourth bit carry C 4  assumes &#34;0&#34;. When this occurs, the step is advanced to P 4 . Otherwise the step is skipped up to P 5 . 
     P 4  . . . When the fourth bit carry C 4  =0 during ACC+1111, the overall contents of W are reduced to &#34;0&#34; to thereby complete all the pre-display processes. The first address P 6  is set for the memory display steps. 
     P 5  . . . In the event that the fourth bit carry C 4  =1 during ACC+1111, the overall contents of W have not yet reduced to &#34;0&#34;. Under these circumstances P 2  is reverted to repeat the introduction of &#34;0&#34; into W. 
     P 6  . . . The first digit position of the memory region which contains data to be displayed is identified by the file address m A  and the digit address n A . 
     P 7  . . . After the contents of the register W for generating the digit selection signals are one bit shifted to the right, its first bit position is loaded with &#34;1&#34; and thus ready to supply the digit selection signal to the first digit position of the display. 
     P 8  . . . The contents of the specific region of the memory are unloaded into ACC. The file address of the memory still remains at m A , whereas the digit address is decremented for the next succeeding digit processing. 
     P 9  . . . The contents of the memory is shifted from ACC to the buffer register F. The contents of the register F are supplied to the segment decoder SD to generate segment display signals. 
     P 10  . . . To lead out the contents of the register W as display signals, the conditional F/F N p  is supplied with &#34;1&#34; and placed into the set state. As a result of this, the contents of the memory processed during P 9  are displayed on the first digit position of the display. 
     P 11  . . . A count initial value n 2  is loaded into ACC to determine a one digit long display period of time. 
     P 12  . . . ACC-1 is carried out like P 3 . When ACC does not assume &#34;0&#34; (when C 4  =1) the step is skipped up to P 14 . 
     P 13  . . . A desired period of display is determined by counting the contents of ACC during P 12 . After the completion of the counting P 15  is reached from P 13 . The counting period is equal in length to a one-digit display period of time. 
     P 14  . . . Before the passage of the desired period of display the step is progressed from P 12   to P 14  with skipping P 13  and jumped back to P 12 . This procedure is repeated. 
     P 15  . . . N p  is reset to stop supplying the digit selection signals to the display. Until N p  is set again during P 10 , overlapping display problems are avoided by using the adjacent digit signals. 
     P 16  . . . The register W is one bit shifted to the right and its first bit position is loaded with &#34;0&#34;. &#34;1&#34; introduced during P 7  is one bit shifted down for preparation of the next succeeding digit selection. 
     P 17  . . . It is decided whether the ultimate digit of the memory to be displayed has been processed and actually whether the value n E  of the last second digit has been reached because the step P 8  of B L  -1 is in effect. 
     P 18  . . . In the event that ultimate digit has not yet been reached, P 8  is reverted for the next succeeding digit display processing. 
     P 19  . . . For example, provided that the completion of the display operation is conditional by the flag F/F FA, FA=1 allows P 20  to be skipped, thereby concluding all the displaying steps. 
     P 20  . . . If FA=1 at P 19 , the display steps are reopened from the first display and the step is jumped up to P 6 . 
     
         ______________________________________(Type 2)______________________________________ ##STR49##______________________________________ 
    
     P 1  . . . The bit number n 1  of the buffer register W is loaded into ACC to reset the overall contents of the buffer register W for generating digit selection signals effective to drive a display panel on a time sharing basis. 
     P 2  . . . After the overall contents of the register W are one bit shifted to the right, its first bit is loaded with &#34;0&#34;. This procedure is repeated via P 4  until C 4  =1 during P 3 , thus resetting the overall contents of W. 
     P 3  . . . The operand I A  is decided as &#34;1111&#34; and AC+1111 is effected (this substantially corresponds to ACC-1). Since ACC is loaded with n 1  during P 1 , this process is repeated n 1  times. When the addition of &#34;1111&#34; is effected following ACC=0, the fourth bit carry C 4  assumes &#34;0&#34;. When this occurs, the step is advanced to P 4 . Otherwise the step is skipped up to P 5 . 
     P 4  . . . When the fourth bit carry C 4  =0 during ACC+1111, the overall contents of W are reduced to &#34;0&#34; to thereby complete all the pre-display processes. The first address P 6  is set for the memory display steps. 
     P 5  . . . In the event that the fourth bit carry C 4  =1 during ACC+1111, the overall contents of W have not yet reduced to &#34;0&#34;. Under these circumstances P 2  is reverted to repeat the introduction of &#34;0&#34; into W. 
     P 6  . . . The upper four bits of the first digit position of the memory region which contains data to be displayed are identified by the file address m A  and the digit address m A . 
     P 7  . . . The contents of the specific region of the memory are unloaded into ACC. The file address of the memory still remains at m A , whereas the digit address is decremented to specify the lower four bits. 
     P 8  . . . The contents of ACC, the upper four bits, are transmitted into the temporary register X. 
     P 9  . . . The contents of the specific region of the memory are unloaded into ACC. The file address of the memory still remains at m A , whereas the digit address is decremented to specify the upper four bits of the next succeeding digit. 
     P 10  . . . The contents of ACC are unloaded into the stack register SA and the contents of the temporary register X into the stack register SX. 
     P 11  . . . After the contents of the register W for generating the digit selection signals are one bit shifted to the right, its first bit position is loaded with &#34;1&#34; and thus ready to supply the digit selection signal to the first digit position of the display. 
     P 12  . . . To lead out the contents of the register W as display signals, the conditional F/F N p  is supplied with &#34;1&#34; and placed into the set state. As a result of this, the contents of the memory processed during P 10  are displayed on the first digit position of the display. 
     P 13  . . . A count initial value n 2  is loaded into ACC to determine a one digit long display period of time. 
     P 14  . . . ACC-1 is carried out like P 3 . When ACC assumes &#34;0&#34; P 15  is reached and when ACC≠0 (when C 4  =1) the step is skipped up to P 16 . This procedure is repeated. 
     P 15  . . . A desired period of display is determined by counting the contents of ACC during P 14 . After the completion of the counting P 17  is reached from P 15 . The counting period is equal in length to a one-digit display period of time. 
     P 16  . . . Before the passage of the desired period of display the step is progressed from P 14  to P 16  with skipping P 15  and jumped back to P 14 . This procedure is repeated. 
     P 17  . . . N p  is reset to stop supplying the digit selection signals to the display. Until N p  is set again during P 10 , overlapping display problems are avoided by using the adjacent digit signals. 
     P 18  . . . The register W is one bit shifted to the right and its first bit position is loaded with &#34;0&#34;. &#34;1&#34; introduced during P 7  is one bit shifted down for preparation of the next succeeding digit selection. 
     P 19  . . . It is decided whether the ultimate digit of the memory to be displayed has been processed and actually whether the value n E  of the last second digit has been reached because the step p 9  of B L  -1 is in effect. 
     P 20  . . . In the event that ultimate digit has not yet been reached, P 7  is reverted for the next succeeding digit display processing. 
     
         ______________________________________(XV) PROCEDURE OF DECIDING WHICH KEY SWITCHIS ACTUATED (SENSING ACTUATION OF ANY KEYDURING DISPLAY______________________________________ ##STR50##           ##STR51##______________________________________ 
    
     P 1  -P 18  . . . The display processes as discussed in (XIV) above. 
     P 19  . . . After the overall digit contents of the register W are displayed, the flag F/F FC is set to hold all the key signals I l  -I n  at a &#34;1&#34; level. 
     P 20  . . . The step is jumped to P 30  as long as any one of the keys connected to the key input KN 1  is actuated. 
     P 22  -P 27  . . . It is decided whether any one of the keys each connected to the respective key inputs KN 2  -KF 2  and in the absence of any actuation the step is advanced toward the next succeeding step. To the contrary, the presence of the key actuation leads to P 30 . 
     P 28  . . . When any key is not actuated, F/F FC is reset to thereby complete the decision as to the key actuations. 
     P 29  . . . The step is jumped up to P 6  to reopen the display routine. 
     P 30  . . . When any key is actually actuated, the memory digit address is set at n 1  to generate the first key strobe signal I 1 . 
     P 31  . . . It is decided if the first key strobe signal I 1  is applied to the key input KN 1  and if not the step is advanced toward P 33 . 
     P 32  . . . When the first key strobe signal I 1  is applied to the key input KN 1 , which kind of the keys is actuated is decided. Thereafter, the step is jumped to P A  to provide proper controls according to the key decision. After the completion of the key decision the step is returned directly to P 1  to commence the displaying operation again (P Z  is to jump the step to P 1 ) 
     P 33  -P 38  . . . It is sequentially decided whether the keys coupled with the first key strobe signal I 1  are actuated. If a specific key is actuated, the step jumps to P B  -P D  for providing appropriate controls for that keys. 
     P 39  . . . This step is executed when no key coupled with the first key strobe signal I 1 . This step is to increment the digit address of the memory for the developments of the key strobe signals. 
     P 41  and up . . . The appropriate key strobe signals are developed and KN 1  -KF 2  are sequentially monitored to decide what kind of the keys are actuated. Desired steps are then selected to effects control steps for those actuated keys. 
     P A  and up . . . Control steps for the first actuated keys. 
     P X  . . . P 1  is returned to reopen the display operation after the control steps for the first key. 
     The foregoing is the description of the respective major processing events in the CPU architecture. 
     By reference to FIGS. 6 and 7 an example of the display operation of a calculator implementing the display device according to the present invention will now be described in detail. 
     FIG. 7 exemplifies a manner by which a pattern &#34;I&#34; is displayed on upper and lower rows of the 7×5 dot matrix display panel by use of the segment signals S 1  -S 40  and the opposing electrode output signals H 1  -H 7  after the storage contains &#34;11F1144744&#34; (see FIG. 7(b)). The displaying data storage area DRM stores temporarily those displaying data as depicted in FIG. 8. The encoded information is stored within the areas (1)-(16), with the area (1) storing the encoded information &#34;11F1144744.&#34; Also, the same encoded information is stored in part of the RAM of the CPU as shown in FIG. 9 as do the areas (1)-(16). 
     The displaying data storage area DRM of FIG. 8 is able to store the character data (1)-(16) but actually the encoded information within the area covering from B B  B L  (0, 0) to B M  B L  (5, 7) may be displayed and all of the character data are not displayed at a time. The characters on the display panel shifts dot by dot at a given period of time by shifting the selected address B M  B L  (0, 0)-B M  B L  (B, F) of the displaying data storage area DRM in the display control circuitry DSC digit by digit at the given period of time through the action of the CPU. 
     FIG. 10 is a flow chart of the running display operation which achieves dot by dot movement of the display contents. By the step N 1  the display is disabled and the DRM is loaded with the data to be running displayed. The step N 2  loads the count indicative of the speed of the running display operation into the display counter. The step N 3  loads the next address of the DRM into the accumulator to shift the address digit by digit. The step N 4  enables the display operation and the step N 5  decrements the display counter. The display operation goes on until the counter reaches &#34;zero&#34; as sensed by the counter which determines the speed of the running display operation. The step N 7  disables the display operation, followed by the SHIFT routine. The running display mode is completed in this manner. 
     FIG. 11 is a flow chart for explanation of the operation shown in FIG. 10 through the utilization of the circuit arrangement of FIGS. 2 through 4. Assume now that the displaying data have already stored within the RAM of the CPU. It is noted that the respective steps n 1 , n 2  . . . n 111  are listed in FIG. 12. Each of the characters 0, 1, 2, . . . 8, 9, a, b, c, . . . x, y, z is stored within the RAM of the CPU in the form of the encoded signals of FIG. 13. As is clear from FIG. 13, if the lower 4 bits are &#34;0000&#34;, then the numerical information is present. If the lower 4 bits are &#34;0001&#34;, the alphabetic characters a-p are evaluated and if the lower 4 bits are &#34;0010&#34; the remaining alphabetic characters q-z are evaluated. 
     The steps and their contents in FIG. 11 will now be discussed. 
     n 1  : the address EO of the RAM of the CPU is selected. 
     n 2  : it is decided as to whether the address EO is &#34;0000&#34; 
     n 3  : it is decided as to whether the address EO is &#34;0001&#34; 
     n 4  : it is decided as to whether the address EO is &#34;0010&#34; 
     n 5  : the selected bit C 1  of the RAM is set and C 2  and C 3  are reset. 
     n 6  : the selected bit C 2  of the RAM is set and C 1  and C 3  are reset. 
     n 7  : the selected bit C 3  of the RAM is set and C 1  and C 2  are reset. 
     n 8  : the address E 1  of the RAM of the CPU is selected. 
     n 9  : whether the address E 1  is &#34;0000&#34; is decided. 
     n 10  : whether the address E 1  is &#34;0001&#34; is decided. 
     n 11  : whether the address E 1  is &#34;1111&#34; is decided. 
     n 12  : whether C 1  is set or reset is decided. 
     n 13  : whether C 2  is set or reset is decided. 
     n 14  : the character pattern corresponding to the data &#34;0&#34; is loaded into the displaying data storage area DRM (the program effective in displaying the character &#34;I&#34; is illustrated in FIG. 14). 
     n 15  : the character pattern indicative of the data &#34;A&#34; is loaded into the displaying data storage area DRM. 
     n 16  : the character pattern indicative of the data &#34;Q&#34; is loaded into the storage area. 
     n 17  -n 26  : the steps n 12  -n 16  are repeated. 
     n 27  : the address E 2  of the RAM of the CPU is selected. 
     n 28  -n 33  : same as the above mentioned steps n 2  -n 7 . 
     n 34  : the address E 3  of the RAM of the CPU is selected. 
     n 35  up to n 52  : same as the above steps n 12  -n 26 . 
     n 53  : the address FF of the RAM of the CPU is selected. 
     n 54  up to n 71  : same as the steps n 12  -n 26 . 
     n 72  : the value m is loaded into the counter CO which may be part of the RAM. 
     n 73  : the address BF of the DRM is selected. 
     n 74  : the file address B is shifted by one digit via the subroutine SR. This step is shown in FIG. 15. 
      S 1    TML: upon the completion of the subroutine the address of the ROM is stored to return to the main routine. 
      S 2    EXO: exchange takes place between the memory storing the selected address of the RAM of the CPU and the accumulator ACC. The address of the memory file remains unchanged. 
      S 3    READ: the selected address of the DRM is read into the accumulator. 
      S 4    EXO: exchange takes place between the contents of the accumulator and the contents of the memory stored at the selected address of the RAM of the CPU. 
      S 5    STOR: the contents of the accumulator ACC are unloaded into the DRM at the selected address. 
      S 6    EXO: exchange occurs between the contents of the accumulator ACC and the contents of the RAM. 
      S 7    DECB: the digit address counter B L  is decremented. By the following steps the contents of the DRM are shifted via repeated execution of the program with varying the digit address. Eventually, 
      S 16    RIT: the address of the ROM is regained for the main routine. 
     Thereafter, the respective file addresses 9, 7, 5, 3, 1 are shifted by one digit through the steps n 75  -n 84 . The steps n 85  -n 90  makes up a routine for transferring the contents of the address B M , B L  (1, 0) into the addresses B, F. In this manner, the lower 3 dots of FIG. 6 are shifted left by one dot. The steps n 91  -n 101  are a routine for shifting left the respective file addresses A, 8, 6, 4, 2, 0 by one dot in the same manner as the steps n 73  -n 84 . 
     The steps n 102  -n 107  shift the contents of the address B M  B L  : 0, 0 to AF. Accordingly, the steps n 91  -n 107  shift left the upper 4 dots of the character by one dot. The step n 108  sets the display controlling flag N 1  so that the segment driver SED provides the segment signals S 1  -S 40 , thus displaying the data out of the displaying storage area DM. By the action of the step n 109  the counter keeps decrementing until CO=&#34;0.&#34; When CO=&#34;0&#34; the instruction n 111  places the displaying controlling flag N 1  into the reset state. Consequently, SED turns OFF S 1  -S 40 , thus disabling the display operation. Then, the step n 72  is returned to shift the contents of the displaying data storage area during the disable period. 
     FIG. 16 is a flow chart associated with the display operation on keyed inputs, wherein a display of the actuated key is shifted each time the keys are actuated as is obvious in the calculator art other than shifting that dot by dot. 
     In FIG. 16, the step m 1  should be inserted into an appropriate position in the routine shown FIG. 11, followed by the step m 2  when any keyed input is sensed. The step m 2  is executed to check if a display key is actuated and, if NO, regards that a character key not the display key has been actuated, thus leading to the step m 3  by which the character code corresponding to that character key is introduced into the first character position of the register within the memory. The step m 4  places that character pattern into the displaying data storage area DRM. The step m 5  sets the displaying flag N 1  and enables the contents of the DRM to be displayed. When the second character is inputted, a sequence of the steps m 6  m 7  m 8  is executed to transfer that character code into the second character position of the register within the memory. The step m 9  discontinues the display operation. The step m 10  shifts the 6 dots within the data storage area DRM. After the second character pattern is loaded into DRM, the instruction m 12  starts the display operation. In this manner, keyed information is loaded and displayed simultaneously. If the display key DK is actuated subsequently to the introduction of the character, then the routine 4 as shown in FIG. 11 is selected to attain the dot by dot movement on the display panel. 
     Whereas the present invention has been described with respect to specific embodiments thereof, it will be understood that various changes and modifications will be suggested to one skilled in the art, and it is intended to encompass such changes and modifications as fall within the scope of the appended claims.