Abstract:
Subject matter disclosed herein relates to memory operations regarding encoding program bits to be programmed into a memory array.

Description:
BACKGROUND 
       [0001]    1. Field 
         [0002]    Subject matter disclosed herein relates to memory operations regarding encoding program bits to be programmed into a memory array. 
         [0003]    2. Information 
         [0004]    Memory devices may be employed in various electronic devices, such as computers, cell phones, PDA&#39;s, data loggers, or navigational equipment, just to name a few examples. For example, various types of nonvolatile memory devices may be employed, such as solid state drives (SSD), NAND or NOR flash memory, or phase change memory, among others. In general, writing or programming operations may be used to store information, while read operations may be used to retrieve stored information. 
         [0005]    Phase change memory (PCM) may operate based, at least in part, on behavior or properties of one or more particular phase change materials, such as chalcogenide glass or germanium antimony telluride (GST), just to name a few examples. Electrical resistivities of crystalline or amorphous states of such materials may be different from one another, thus presenting a basis by which information may be represented or expressed. The amorphous, high resistance state may represent a stored first binary state and the crystalline, low resistance state may represent a stored second binary state. Of course, such a binary representation of stored information is merely an example. PCM may also be used to store multiple memory states, represented by varying degrees of phase change material resistivity, for example. 
         [0006]    Nonvolatile memory devices, such as PCM, may comprise wordlines and bitlines to program an array of memory cells. As density of memory cells in an array increase, distances between adjacent wordlines or bitlines may decrease. Decreased spacing among wordlines or bitlines may lead to undesirable effects, such as capacitive coupling, crosstalk, or memory disturb, just to name a few examples. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0007]    Non-limiting and non-exhaustive embodiments will be described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified. 
           [0008]      FIG. 1  is a schematic diagram of a portion of a memory array, according to an embodiment. 
           [0009]      FIG. 2  is a schematic diagram of an arrangement of program bits on adjacent wordlines, according to an embodiment. 
           [0010]      FIG. 3  is a flow diagram of an embodiment of a process to encode program bits to be programmed in a memory array. 
           [0011]      FIG. 4  is another flow diagram of an embodiment of a process to encode program bits to be programmed in a memory array. 
           [0012]      FIG. 5  is a schematic diagram illustrating an embodiment of a computing system. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of claimed subject matter. Thus, appearances of phrases such as “in one embodiment” or “an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in one or more embodiments. 
         [0014]    A phase change memory (PCM) cell, if used to store a binary logic value, may be set or reset to one of two states. For example, an amorphous, high resistance state may represent a stored first binary state (e.g., a zero-bit) and a crystalline, low resistance state may represent a stored second binary state (e.g., a one-bit). A PCM cell may be programmed to a zero-bit by resetting the PCM cell to an amorphous state by applying a relatively high amplitude, relatively short duration electrical programming pulse or signal so as to melt and then cool phase change material of the PCM cell. A PCM cell may be programmed to a one-bit by setting the PCM cell to a crystalline state by crystallizing phase change material. 
         [0015]    A memory array comprising PCM cells may be programmed using wordlines or bitlines that provide electrical programming pulses or signals representing one-bits or zero-bits in individual PCM cells. While one wordline may be used to program one row of PCM cells, an adjacent wordline may be used to program an adjacent row of PCM cells. Adjacent rows of PCM cells may be spaced apart to provide structural, electrical, or thermal insulation between the adjacent rows. However, as the density of PCM cells in an array increase, spacing between adjacent rows of PCM cells may decrease, thus reducing the amount of available semiconductor material providing thermal insulation between the adjacent rows. Among other things, thermal contact among PCM cells may undesirably lead to an increased probability that a state of one PCM cell may be disturbed by the state of a neighboring PCM cell. A PCM cell thermally affecting another PCM cell may be called a “proximity-disturb” event, which may include a “program disturb” event or a “read disturb” event, depending on whether a program process or a read process is involved. For example, a zero-bit of a PCM cell may be cyclically re-programmed with a particular frequency in a process of refreshing the state of the PCM cell. Such re-programming a zero-bit may comprise applying a relatively high amplitude electrical programming pulse or signal so as to melt and then cool phase change material of the PCM cell, as mentioned above. A process of melting phase change material of the PCM cell, however, may inadvertently add heat to one or more neighboring PCM cells. A neighboring PCM cell nearest the re-programmed PCM cell may be affected more than other neighboring PCM cells. In one implementation, a neighboring PCM cell nearest the re-programmed PCM cell may be located in a wordline adjacent to a wordline of the re-programmed PCM cell. Thus, a neighboring PCM cell located in a wordline adjacent to a wordline of the re-programmed PCM cell may be program-disturbed by the re-programming process of the neighboring PCM cell. As the frequency of refreshing the state of a PCM cell increases, so does the probability of occurrence of a program-disturb event, induced by increasing ambient temperatures of a memory array, for example. 
         [0016]    PCM cells in a zero-bit, amorphous state may be more susceptible to effects of a program-disturb event compared to PCM cells in a one-bit, crystalline state. Such effects may change a PCM memory cell in a zero-bit state to a one-bit state or vise versa. For example, a program-disturb event may erroneously change a state of a PCM cell from a zero-bit state to a one-bit state. This may be true, at least in part, because an amorphous state may comprise a meta-stable state with respect to a relatively stable crystalline state. Additional energy applied to such an amorphous state (via thermal or electrical energy, for example) may accelerate a crystallization process. Such additional energy may comprise ambient thermal energy from neighboring PCM cells being repeatedly programmed, as mentioned above. In this case, heat generated during programming operation of neighboring PCM cells may diffuse from the neighboring PCM cells to accelerate crystallization of another PCM cell in a zero-bit, amorphous state. In another implementation, a read-disturb event may occur if a PCM cell is read many times during a relatively short period of time to create excess heat. 
         [0017]    Two or more PCM cells in adjacent wordlines on particular bit lines of a memory array may lead to undesirable effects of a program-disturb event, as explained above. For example, a PCM cell in a zero-bit state may program-disturb another PCM cell in a zero-bit state. Embodiments described herein include processes or electronic architecture to reduce probability of occurrence of a program-disturb event. For example, one embodiment may involve a process of encoding program bits to be programmed in a memory array to reduce the number of occurrences of two or more adjacent zero bits on particular bit lines of the memory array, as explained in detail below. 
         [0018]    In an embodiment, a method to reduce a probability of occurrence of a program-disturb event may comprise partitioning program bits to be written into a memory cell array into two or more portions, and encoding the two or more portions of the program bits so as to reduce occurrences of two or more adjacent memory cells on particular bit lines of said memory cell array having zero-bit states. In one implementation, the two or more portions of program bits may be respectively written on two or more adjacent wordlines of the memory cell array. Though claimed subject matter is not so limited, encoding particular program bits to be written into a memory cell array may comprise using a table that includes bit-codes corresponding to portions of the particular program bits. For example, bit-codes may comprise bit sequences used to encode portions of program bits leading to a reduction of the number of occurrences of two or more adjacent memory cells on particular bitlines having zero-bit states. As mentioned above, a memory cell array may comprise a PCM cell array, wherein a one-bit state corresponds to a crystalline set state of a PCM cell and a zero-bit state corresponds to an amorphous reset state of the PCM cell. 
         [0019]    In an embodiment, a non-volatile memory device may include an ability to reduce a probability of occurrence of a program-disturb event. For example, such a memory device may comprise a controller to encode program bits to be written into a memory cell array, and to place the encoded program bits onto two adjacent wordlines of the memory cell array. Encoded program bits may be encoded to reduce the number of occurrences of adjacent zero bits on two adjacent wordlines of memory cells. As described below, a non-volatile memory device may comprise a plurality of wordlines configured in pairs. Wordlines of individual pairs may be separated by a first distance, while pairs of wordlines may be separated by a second distance greater than the first distance. A program-disturb event may occur among wordlines that are paired with one another, whereas a program-disturb event need not occur among wordlines from different pairs, though claimed subject matter is not so limited. 
         [0020]    In one implementation, a controller of a non-volatile memory device may comprise circuitry to encode program bits to be written to a memory cell array, wherein such encoding may be based, at least in part, on an ordering of bit values (e.g., zero-bit or one-bit) of the program bits. In another implementation, a controller may encode program bits based, at least in part, on an ordering of bit values of the program bits and a table comprising codes corresponding to the ordering of bit values of the program bits. For example, such codes may comprise bit sequences to encode the program bits so as to lead to a reduction of the number of occurrences of two or more adjacent zero bits on adjacent wordlines of memory cells. Though memory cells may comprise PCM cells, claimed subject matter is not so limited. For example, encoding program bits to be written to a memory array may be performed as described herein for other types of memory for any number of reasons. 
         [0021]      FIG. 1  is a schematic diagram of a portion of a memory array  100 , according to an embodiment. For example, a memory device may comprise memory array  100  and address decoding circuitry (not shown) to read from or write to selected memory cells via bitlines or wordlines. Memory cells  150  may be connected at intersections of wordlines and bitlines and may be selectively addressed by the wordlines or bitlines. For example, memory cell  155  may be programmed to be in a zero-bit state by placing a zero-bit on wordline WL 1  in a bitline BL 1  position. Similarly, memory cell  157  may be programmed to be in a one-bit state by placing a one-bit on wordline WL 2  in a bitline BL 1  position. In another example,  FIG. 1  shows wordline WL 3  with bits  0 - 1 - 0 - 1  in bitline positions BL 1 , BL 2 , BL 3 , and BL 4 , respectively. Memory cells  150  may comprise PCM cells, though claimed subject matter is not so limited. 
         [0022]    In an embodiment, adjacent wordlines in memory array  100  may be physically spaced apart by two different distances. For example, adjacent wordlines WL 9  and WL 10  may be spaced apart by a distance D 1 , while adjacent wordlines WL 8  and WL 9  may be spaced apart by a distance D 2 . The different spacing distances may be determined, at least in part, from fabrication architecture of a semiconductor memory device that includes memory array  100 , for example. Thus, adjacent wordlines may be physically grouped in pairs with an inter-pair spacing of distance D 1 , whereas such pairs of wordlines may be spaced apart a distance D 2 . Referring to  FIG. 1 , for example, adjacent wordlines WL 1  and WL 2  comprise a wordline pair separated by a distance D 1 , adjacent wordlines WL 3  and WL 4  comprise a wordline pair separated by a distance D 1 , adjacent wordlines WL 5  and WL 6  comprise a wordline pair separated by a distance D 1 , adjacent wordlines WL 7  and WL 8  comprise a wordline pair separated by a distance D 1 , and adjacent wordlines WL 9  and WL 10  comprise a wordline pair separated by a distance D 1 . In contrast, wordline WL 2  and wordline WL 3 , though they are adjacent to one another, may be separated by a distance D 2 , which may be greater than inter-pair spacing distance D 1 . To continue the example, wordline WL 4  and wordline WL 5  may be separated by a distance D 2 , wordline WL 6  and wordline WL 7  may be separated by a distance D 2 , and wordline WL 8  and wordline WL 9  may be separated by a distance D 2 . 
         [0023]    As mentioned above, thermal contact among PCM cells may lead to a program-disturb event, wherein a state of one PCM cell may be disturbed by the state of a neighboring PCM cell. A neighboring PCM cell nearest the re-programmed PCM cell may be affected more than other neighboring PCM cells. In one implementation, a neighboring PCM cell nearest the re-programmed PCM cell may be located in a wordline adjacent to a wordline of the re-programmed PCM cell. Thus, a neighboring PCM cell located in a wordline adjacent to a wordline of the re-programmed PCM cell may be program-disturbed by the re-programming process of the neighboring PCM cell. In memory array  100 , for example, memory cells included in wordlines of a wordline pair may be physically near one another so as to be affected by a program-disturb event. More specifically, memory cells included in wordlines of a wordline pair along a same bitline may be physically near enough to one another so as to be affected by a program-disturb event. On the other hand, memory cells included in wordlines of different wordline pairs, even if on a same bitline, may be physically separated enough so as to not be substantially affected by a program-disturb event. Returning to  FIG. 1 , for example, memory cells in memory cell pair  110  may program-disturb one another, whereas memory cells in memory cell pair  120  need not program-disturb one another. 
         [0024]    As discussed above, PCM cells in a zero-bit, amorphous state may be more susceptible to effects of a program-disturb event compared to PCM cells in a one-bit, crystalline state. For example, memory cells in zero-bit states in memory cell pair  110  may program-disturb one another, whereas memory cells  155  and  157  in zero-bit and one-bit states, respectively, need not program-disturb one another. 
         [0025]    In one implementation, PCM cells in adjacent wordlines of wordline pairs may be more susceptible to effects of a program-disturb event compared to PCM cells in a same wordline and adjacent bitlines. Such effects may change a PCM memory cell in a zero-bit state to a one-bit state or vise versa. For example, memory cells in memory cell pair  130  need not program-disturb one another, even though the adjacent memory cells may both be in zero-bit states. 
         [0026]    Accordingly, as discussed above, it may be desirable to avoid or reduce the number of occurrences of memory cells in adjacent wordlines of a wordline pair along a single bitline to be in a zero-bit state. For example, the occurrence of zero-bit states in memory cells in memory cell pair  110  may be undesirable. 
         [0027]      FIG. 2  is a schematic diagram of an arrangement program bits on adjacent wordlines, according to an embodiment.  FIG. 2  may depict a memory array similar to that of  FIG. 1 , but without explicitly showing memory cells, wordlines, and bitlines. For example, in  FIG. 2 , a wordline WL(i) may have bits  0 - 1 - 0 - 0 - 1 - 0 - 1 - 0  on consecutive bitlines, such as BL 1 , BL 2 , BL 3 , and so on, shown in  FIG. 1 . An adjacent wordline WL(i+1) may have bits  0 - 1 - 1 - 1 - 1 - 0 - 1 - 1  on the same consecutive bitlines as for WL(i). As discussed above, PCM cells in a zero-bit, amorphous state may be more susceptible to effects of a program-disturb event compared to PCM cells in a one-bit, crystalline state. Also, PCM cells in adjacent wordlines may be more susceptible to effects of a program-disturb event compared to PCM cells in a same wordline and adjacent bitlines. Thus, zero-bit pair  210 , comprising zero bits on a same bitline and adjacent wordlines WL(i) and WL(i+1), may lead to an undesirable program-disturb event. As another example, zero-bit pair  220 , comprising zero bits on a same bitline and adjacent wordlines WL(i) and WL(i+1), may also lead to an undesirable program-disturb event. However, in another example, zero-bit pair  230 , comprising zero bits on a same wordline WL(i) but adjacent bitlines, need not lead to a program-disturb event. Accordingly, as discussed above, it may be desirable to avoid or reduce the number of occurrences of zero bits on a same bitline and adjacent wordlines. 
         [0028]      FIG. 3  is a flow diagram of an embodiment of a process  300  to encode a group  310  of data bits representing binary states to be programmed in a memory array, such as memory array  100  shown in  FIG. 1 , for example. Process  300  may comprise a technique to avoid or reduce a number of occurrences of zero bits on a same bitline and adjacent wordlines in the memory array to be programmed. A desirable outcome, for example, is that, during a process of programming a memory array, adjacent wordlines along same bitlines will not both include zero-bits at the same time, regardless of the combination of bits in group  310 . Accordingly, a program-disturb event may be avoided. 
         [0029]    Group  310  data bits may comprise a byte, a word, or several to several hundred data bits, just to name a few examples. In one implementation, group  310  may comprise an upper-significant-bits portion  312  and a lower-significant-bits portion  314 . Each portion may comprise a same number of bits, though claimed subject matter is not so limited. In process portion  315 , group  310  may be partitioned into portions  312  and  314 , providing bit group  322  and bit group  324 . In process portion  325  a combination of bits  330  and  333  may be created from a particular combination of bits of bit group  322  and bit group  324 . Though any of a number of possible combinations may be used, in one particular implementation, the most-significant bits from each of bit group  322  and bit group  324  may be combined to create bit combination  330 , as shown by arrows in  FIG. 3 . Also, the next most-significant bits from each of bit group  322  and bit group  324  may be combined to create bit combination  333 , also shown by arrows in  FIG. 3 . In process portion  335 , a look-up table, for example, may be used arrive at a wordline bit groups  340  and  350 . Wordline bit groups  340  and  350  may respectively comprise bits to be placed on adjacent wordlines, as shown in detail below. In one implementation, a look-up table may be used by looking up the bit values of bit group  322  and bit group  324  and finding a corresponding table value to give wordline bit groups  340  and  350 . An example of such a table is shown in Table 1. 
         [0000]    
       
         
               
               
               
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                   
                 Combined Bit 
                   
                   
               
               
                   
                 combination 330 and 
               
               
                 Line number 
                 bit combination 333 
                 First wordline 
                 Second wordline 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 1 
                 0000 
                 010 
                 101 
               
               
                 2 
                 0001 
                 110 
                 111 
               
               
                 3 
                 0010 
                 011 
                 111 
               
               
                 4 
                 0011 
                 101 
                 111 
               
               
                 5 
                 0100 
                 011 
                 111 
               
               
                 6 
                 0101 
                 011 
                 110 
               
               
                 7 
                 0110 
                 011 
                 101 
               
               
                 8 
                 0111 
                 110 
                 111 
               
               
                 9 
                 1000 
                 101 
                 010 
               
               
                 10 
                 1001 
                 111 
                 110 
               
               
                 11 
                 1010 
                 111 
                 011 
               
               
                 12 
                 1011 
                 111 
                 101 
               
               
                 13 
                 1100 
                 111 
                 011 
               
               
                 14 
                 1101 
                 110 
                 011 
               
               
                 15 
                 1110 
                 101 
                 011 
               
               
                 16 
                 1111 
                 111 
                 110 
               
               
                   
               
             
          
         
       
     
         [0030]    Table 1 may comprise values so that adjacent wordlines along same bitlines do not both include zero-bits at the same time. Of course, tables comprising values different than those in Table 1 may be used, and Table 1 is merely an example. Thus, in the example shown in  FIG. 3 , combined bit combinations  330  and  333  comprise bit values  0110 , located in line 7 of Table 1. 0110 corresponds to a wordline bit group  340  comprising bits  011  and a wordline bit group  350  comprising bits  101 . Bits of wordline bit group  340  may be placed on wordline WL(i) and bits of wordline bit group  350  may be placed on adjacent wordline WL(i+1). Accordingly, adjacent wordlines along same bitlines do not both include zero-bits at the same time. In fact, use of any other components of lines 1 through 16 of Table 1 may lead to there being no zero bits adjacent to one another on adjacent wordlines. 
         [0031]    In another embodiment, a look-up table, such as Table 1 described above, need not be used to arrive at wordline bit groups  340  and  350 . Instead, circuitry comprising logic components, for example, may be used. Such circuitry may be included in a memory controller or peripheral circuitry of a memory array, though claimed subject matter is not so limited. For example, instead of using a look-up table with a combination of bits  330  and  333 , as described above, the combination of bits  330  and  333  may be provided to a combination of logic components interconnected so as to produce bit values  340  and  350 . 
         [0032]    As described so far, process  300  may encode a portion of a group of bits  310  into wordline bit groups  340  and  350 . Adjacent wordlines along same bitlines may not both include zero-bits at the same time if wordline bit groups  340  and  350  are respectively placed on the adjacent wordlines, as mentioned above. Repeating at least some portions of process  300 , additional bits from bit group  322  and bit group  324  may be used to create another combination of bits  330  and  333  during process portion  325 . In one particular implementation, the most-significant bits from each of bit group  322  and bit group  324  that have yet to be used in process portion  325  (such as that described above, for example) may be combined to create bit combination  330 . Also, the next most-significant bits from each of bit group  322  and bit group  324  may be combined to create bit combination  333 . In process portion  335 , a look-up table, for example, may be used to arrive at wordline bit groups  340  and  350 , as described above. Bit line groups  340  and  350  may be appended to previously determined bit line groups  340  and  350 . Such an iterative process may continue until all bits of bit group  322  and bit group  324  have been encoded by process portions  325  and  335 , for example. 
         [0033]      FIG. 4  is a flow diagram of an embodiment of a process  400  to encode program bits to be programmed in a memory array. Process  400  may comprise one of an unlimited number of techniques to encode program data to reduce effects of a program-disturb event by avoiding neighboring zero-bits on a bitline. Process  400  merely describes an example of an encoding embodiment, but other encoding techniques may be used. Also, various portions or details of process  400  may be changed. Accordingly, details of process  400  are merely examples, and claimed subject matter is not so limited. 
         [0034]    At block  410 , a memory controller, or other device to perform process  400 , may receive a group of bits to program a memory array, for example. A group of bits may be similar to  310 , shown in  FIG. 3 , though claimed subject matter is not so limited. As explained above, such a group of bits may comprise a byte, a word, or several to several hundred data bits, just to name a few examples. In block  420 , the group of bits may be partitioned into two portions, though a partitioning process may partition a group of bits into any number of portions, as in the case of other implementations, for example. The group of bits may be partitioned so that half the number of bits are in one portion and the other half are in another portion. For example, returning to  FIG. 3 , group  310  may comprise an upper-significant bits portion  312  and a lower-significant bits portion  314  that are partitioned into bit group  322  and bit group  324 . 
         [0035]    In block  430 , two portions of bits determined, at least in part, by the partitioning process of block  420  may be encoded to reduce effects of a program-disturb event by avoiding neighboring zero-bits on a bitline. As mentioned above, such encoding may be performed by any of an unlimited number of encoding techniques. In one technique, described in the example embodiment shown in  FIG. 3 , most-significant bits from each of two portions of bits (e.g., bit group  322  and bit group  324 ) may be combined to create a new combination of bits (e.g., bits  330  and  333 ). The new combination of bits may be applied to a look-up table, such as Table 1, described above, to obtain a pair of encoded program bits that, by design, do not include adjacent zero-bits in a bitline direction. Accordingly, as at block  440 , the pair of encoded program bits may be placed onto adjacent wordlines in the memory array without (or with a reduced) occurrence of adjacent zero-bits in the adjacent wordlines. 
         [0036]      FIG. 5  is a schematic diagram illustrating an embodiment of a computing system  500  including a memory device  510 . Such a computing device may comprise one or more processors, for example, to execute an application or other code. For example, memory device  510  may comprise memory array  100 , shown in  FIG. 1 . A computing device  504  may be representative of any device, appliance, or machine that may be configurable to manage memory device  510 . Memory device  510  may include a memory controller  515  and a memory  522 , which may comprise PCM, for example. By way of example but not limitation, computing device  504  may include: one or more computing devices or platforms, such as, e.g., a desktop computer, a laptop computer, a workstation, a server device, or the like; one or more personal computing or communication devices or appliances, such as, e.g., a personal digital assistant, mobile communication device, or the like; a computing system or associated service provider capability, such as, e.g., a database or information storage service provider/system; or any combination thereof. It is recognized that all or part of the various devices shown in system  500 , and the processes and methods as further described herein, may be implemented using or otherwise including hardware, firmware, software, or any combination thereof. Thus, by way of example but not limitation, computing device  504  may include at least one processing unit  520  that is operatively coupled to memory  522  through a bus  540  and a host or memory controller  515 . 
         [0037]    Processing unit  520  is representative of one or more circuits configurable to perform at least a portion of an information computing procedure or process. By way of example but not limitation, processing unit  520  may include one or more processors, controllers, microprocessors, microcontrollers, application specific integrated circuits, digital signal processors, programmable logic devices, field programmable gate arrays, and the like, or any combination thereof. Processing unit  520  may include an operating system configured to communicate with memory controller  515 . Such an operating system may, for example, generate commands to be sent to memory controller  515  over bus  540 . Such commands may comprise read or write commands. In response to a write command, for example, memory controller  515  may encode program bits to be written into memory  522 , and place the encoded program bits onto two or more adjacent wordlines of the memory, wherein the encoded program bits are encoded to reduce the number of occurrences of adjacent zero bits on the adjacent wordlines of memory cells. In one implementation, controller  515  may comprise circuitry (e.g., logic components) to encode program bits based, at least in part, on an ordering of bit values of the program bits. Of course, such details of a portion of memory are merely examples, and claimed subject matter is not so limited. 
         [0038]    In a particular implementation, computing system  500  may comprise memory  522  comprising a first number of memory sectors to store information provided by one or more applications and a second number of memory sectors to store ECC associated with the information. Memory  522  may further comprise memory controller  515  to adjust from a first level of error correctability to a second level of error correctability applied to the memory in response to determining that at least a portion of the memory is non-functional. 
         [0039]    Memory  522  is representative of any information storage mechanism. Memory  522  may include, for example, a primary memory  524  or a secondary memory  526 . Primary memory  524  may include, for example, a random access memory, read only memory, etc. While illustrated in this example as being separate from processing unit  520 , it should be understood that all or part of primary memory  524  may be provided within or otherwise co-located/coupled with processing unit  520 . 
         [0040]    Secondary memory  526  may include, for example, the same or similar type of memory as primary memory or one or more information storage devices or systems, such as, for example, a disk drive, an optical disc drive, a tape drive, a solid state memory drive, etc. In certain implementations, secondary memory  526  may be operatively receptive of, or otherwise configurable to couple to, a computer-readable medium  528 . Computer-readable medium  528  may include, for example, any medium that can carry or make accessible information, code, or instructions for one or more of the devices in system  500 . Computing device  504  may include, for example, an input/output  532 . Input/output  532  is representative of one or more devices or features that may be configurable to accept or otherwise introduce human or machine inputs, or one or more devices or features that may be configurable to deliver or otherwise provide for human or machine outputs. By way of example but not limitation, input/output device  532  may include an operatively configured display, speaker, keyboard, mouse, trackball, touch screen, data port, etc. 
         [0041]    It will, of course, be understood that, although particular embodiments have just been described, claimed subject matter is not limited in scope to a particular embodiment or implementation. For example, one embodiment may be in hardware, such as implemented on a device or combination of devices, for example. Likewise, although claimed subject matter is not limited in scope in this respect, one embodiment may comprise one or more articles, such as a storage medium or storage media that may have stored thereon instructions capable of being executed by a specific or special purpose system or apparatus, for example, to lead to performance of an embodiment of a method in accordance with claimed subject matter, such as one of the embodiments previously described, for example. However, claimed subject matter is, of course, not limited to one of the embodiments described necessarily. Furthermore, a specific or special purpose computing platform may include one or more processing units or processors, one or more input/output devices, such as a display, a keyboard or a mouse, or one or more memories, such as static random access memory, dynamic random access memory, flash memory, or a hard drive, although, again, claimed subject matter is not limited in scope to this example. 
         [0042]    The terms, “and” and “or” as used herein may include a variety of meanings that will depend at least in part upon the context in which it is used. Typically, “or” if used to associate a list, such as A, B or C, is intended to mean A, B, and C, here used in the inclusive sense, as well as A, B or C, here used in the exclusive sense. Embodiments described herein may include machines, devices, engines, or apparatuses that operate using digital signals. Such signals may comprise electronic signals, optical signals, electromagnetic signals, or any form of energy that provides information between locations. 
         [0043]    In the preceding description, various aspects of claimed subject matter have been described. For purposes of explanation, specific numbers, systems, or configurations may have been set forth to provide a thorough understanding of claimed subject matter. However, it should be apparent to one skilled in the art having the benefit of this disclosure that claimed subject matter may be practiced without those specific details. In other instances, features that would be understood by one of ordinary skill were omitted or simplified so as not to obscure claimed subject matter. While certain features have been illustrated or described herein, many modifications, substitutions, changes, or equivalents may now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications or changes as fall within the true spirit of claimed subject matter.