Abstract:
A thermostat circuit (FIG.  4 ) is provided which (i) works properly with very low supply voltages, (ii) does not need a separate constant value as a reference, and (iii) has improved temperature sensitivity over prior art thermostat circuits. The thermostat circuit compares two reference currents—I PTAT  and I VBE . When I VBE &gt;I PTAT , the output of the thermostat circuit is one logic state (either high or low). When I PTAT &gt;I VBE , the output of the thermostat circuit is a different logic state (either low or high). Current I PTAT  comes from a PTAT current generator (FIGS.  5 - 7 ), and current I VBE  comes from a V BE  current generator (FIGS.  8 - 10 ). The PTAT current generator and the V BE  current generator may be implemented with cascode amplifiers. In an embodiment, the currents I PTAT  and I VBE  can be compared at a current comparator circuit (FIG.  11 ) with a summing node and an output node. The total current at the current comparator&#39;s output node is independent of temperature, and the output node exhibits a hysteresis behavior. The thermostat circuit can include a testing/tuning circuit (FIG.  12 ) which is capable of injecting a test current into or subtracting a test current out of the summing node.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to electrical circuits, and in particular to a thermostat circuit with an output that indicates when the circuit&#39;s temperature is above or below a certain predetermined value.  
           [0003]    2. Description of the Related Art  
           [0004]    [0004]FIG. 1—Prior Art  
           [0005]    [0005]FIG. 1 shows a block diagram of a prior art thermostat circuit  100 . Thermostat circuit  100  comprises a constant voltage generator  105 , a proportional to absolute temperature (“PTAT”) voltage generator  110 , and a current comparator  115 . The constant voltage generator  105  generates a reference voltage V REF  which is fed into the comparator  115 . Similarly, the PTAT voltage generator  110  generates a PTAT voltage V PTAT  which is fed into the comparator  115 . When V PTAT &gt;V REF , the output  120  is one logic state. When V REF &gt;V PTAT , the output  120  is a different logic state.  
           [0006]    Because V PTAT  is proportional to temperature, this prior art thermostat circuit indicates when the circuit&#39;s temperature is above or below a certain temperature. V REF  is set to equal V PTAT  at this temperature.  
           [0007]    There are at least two disadvantages associated with the circuit of FIG. 1: (i) it will not function properly for very low supply voltages, and (ii) it requires a separate constant value as a reference. In addition, it is always desirable to have a thermostat circuit with better temperature sensitivity.  
           [0008]    [0008]FIG. 2—Prior Art  
           [0009]    [0009]FIG. 2 shows a prior art PTAT current generator. This circuit is built with current sources I 1 -I 2 , npn bipolar junction transistors Q 1 -Q 2 , resistor R 1 , and operational amplifier (“opamp”) A 1 . Opamp A 1  has a noninverting input terminal (node n 1 ), an inverting input terminal (node n 2 ), and an output terminal (node n 3 ).  
           [0010]    Current sources I 1 -I 2  are implemented so that each current source produces a substantially equal current I PTAT . This can be done, for example, by utilizing PMOS transistors. In such an implementation, the sources of the PMOS transistors are connected to V CC , and the gates of the PMOS transistors are connected together in a current mirror configuration to node n 3 .  
           [0011]    Transistor Q 2  is N times larger in size than transistor Q 1 . Initially, with Q 2  larger than Q 1 , and equal current from I 1 -I 2 , the voltage across Q 1  will be N times larger than the voltage across Q 2 . Thus, node n 2  will be driven higher than node n 1 . This will cause the voltage at node n 3  to decrease. Decreasing the voltage at node n 3  causes current I PTAT  from current sources I 1 -I 2  to increase. Current I PTAT  will increase until the voltage across resistor R 1  balances the voltage difference between transistors Q 1  and Q 2 .  
           [0012]    The voltage difference between transistors Q 1  and Q 2  is proportional to absolute temperature, and can be expressed as:  
               Δ                   V   BE       =       kT   q     ·     ln        (   N   )                 (   1   )                               
 
           [0013]    The current I PTAT  is determined by a PTAT voltage drop on the resistor R 1 :  
               I   PTAT     =         Δ                   V   BE         R   1       ·     kT     q   ·     R   1         ·     ln        (   N   )                 (   2   )                               
 
           [0014]    [0014]FIG. 3—Prior Art  
           [0015]    [0015]FIG. 3 shows a prior art V BE  current generator. This circuit is built with current sources I 3 -I 4 , npn bipolar junction transistor Q 3 , resistor R 2 , and opamp A 2 . Opamp A 2  has a noninverting input terminal (node n 11 ), an inverting input terminal (node n 12 ), and an output terminal (node n 13 ).  
           [0016]    Current sources I 3 -I 4  are implemented so that each current source produces a substantially equal current I VBE . This can be done, for example, by utilizing PMOS transistors, as described above with respect to current sources I 1 -I 2 .  
           [0017]    Because current sources I 3 -I 4  produce a substantially equal current I VBE , the voltage across transistor Q 3  appears across resistor R 2 . Therefore, the current I VBE  is given by:  
               I   VBE     =       V     BE   1         R   2               (   3   )                               
 
         SUMMARY OF THE INVENTION  
         [0018]    In accordance with the present invention, a thermostat circuit is provided which (i) works properly with very low supply voltages, (ii) does not need a separate constant value as a reference, and (iii) has improved temperature sensitivity.  
           [0019]    In accordance with the present invention, as illustrated in FIG. 4, current I PTAT  from the prior art PTAT current generator and current I VBE  from the prior art V BE  current generator are fed into a current comparator. When I VBE &gt;I PTAT , the output is one logic state (either high or low). When I PTAT &gt;I VBE , the output is a different logic state (either low or high).  
           [0020]    Another aspect of the present invention is the implementation of the I PTAT  and I VBE  current generators. One implementation shown in FIGS. 5 and 8 uses only substrate pnp bipolar devices, which are the bipolar devices usually available in CMOS technology. Using only substrate pnp bipolar devices has the additional advantage of an operating supply voltage that could be below 1 V.  
           [0021]    Another implementation is shown in FIGS. 6 and 9 which has improved power supply rejection. Improved power supply rejection is obtained by cascoding current source transistors M 1  and M 2  using cascode transistors M 5  and M 6 . And yet another implementation shown in FIGS. 7 and 8 includes a secondary loop for biasing cascode transistors M 1  and M 2  properly when the voltage between nodes n 11  and n 12  is not I VBE .  
           [0022]    Another aspect in accordance with the present invention is the implementation of a current comparator. In one embodiment shown in FIG. 11, the current comparator is implemented so as to enable a hysteresis behavior.  
           [0023]    Another aspect in accordance with the present invention is a circuit shown in FIG. 12 which can be used in order to test or tune a low-voltage thermostat circuit in accordance with the present invention at room temperature. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]    Further details of the present invention are explained with the help of the attached drawings in which:  
         [0025]    [0025]FIG. 1 shows a block diagram of a prior art thermostat circuit;  
         [0026]    [0026]FIG. 2 shows a prior art PTAT current generator;  
         [0027]    [0027]FIG. 3 shows a prior art V BE  current generator;  
         [0028]    [0028]FIG. 4 shows a block diagram illustrating a thermostat circuit in accordance with the present invention;  
         [0029]    [0029]FIG. 5 shows a more detailed embodiment of the I PTAT  current generator in accordance with the present invention;  
         [0030]    [0030]FIG. 6 shows another embodiment of the I PTAT  current generator in accordance with the present invention;  
         [0031]    [0031]FIG. 7 shows another embodiment of the I PTAT  current generator in accordance with the present invention;  
         [0032]    [0032]FIG. 8 shows an embodiment of the I VBE  current generator in accordance with the present invention;  
         [0033]    [0033]FIG. 9 shows another implementation of the I VBE  current generator in accordance with the present invention;  
         [0034]    [0034]FIG. 10 shows another implementation of the I VBE  current generator in accordance with the present invention;  
         [0035]    [0035]FIG. 11 shows an embodiment of the current comparator in accordance with the present invention; and  
         [0036]    [0036]FIG. 12 shows a circuit which can be used in order to test or tune a low-voltage thermostat circuit in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0037]    [0037]FIG. 4 
         [0038]    [0038]FIG. 4 shows a block diagram illustrating a thermostat circuit in accordance with the present invention. This embodiment comprises a PTAT current generator  405 , a V BE  current generator  410 , and a current comparator  415 . The prior art PTAT current generator shown in FIG. 2 could be used to implement the PTAT current generator  405 . Similarly, the prior art V BE  current generator shown in FIG. 3 could be used to implement the V BE  current generator  410 .  
         [0039]    Current I PTAT  from the PTAT current generator  405  and current I VBE  from the V BE  current generator  410  are fed into the current comparator  415 . When I VBE &gt;I PTAT , the output  420  is one logic state (either high or low). When I PTAT &gt;I VBE , the output  420  is a different logic state (either low or high).  
         [0040]    The circuit shown in FIG. 4 possesses at least two advantages over the thermostat circuit described above. First, there is no need for a separate constant value as a reference. Second, the point where I VBE =I PTAT  (the “crossing point”) has better temperature sensitivity than the prior art thermostat circuit in FIG. 1, because it involves two variables with temperature coefficients of opposite signs.  
         [0041]    [0041]FIG. 5 
         [0042]    [0042]FIG. 5 shows a more detailed embodiment of the I PTAT  current generator  405  in accordance with the present invention. As in FIG. 2, this implementation comprises pnp bipolar transistors Q 1  and Q 2  and resistor R 1 . Current sources I 1  and I 2  in FIG. 2 are implemented with transistors M 1  and M 2  in FIG. 5. Opamp A 1  in FIG. 2 is implemented with transistors M 9 -M 16  and M 25 -M 29  in FIG. 5.  
         [0043]    Because the gate and the source terminals of transistors M 1 -M 2  are connected to node n 3  and V CC  respectively, transistors M 1 -M 2  have substantially identical gate-to-source voltages. Consequently, the magnitude of the current I PTAT  generated by transistors M 1 -M 2  is substantially equal.  
         [0044]    The implementation of opamp A 1  comprises two sections: the amplifier section, and the biasing section. The amplifier section consists of transistors M 9 -M 16 . The biasing section consists of transistors M 25 -M 29 .  
         [0045]    The amplifier section is implemented as a cascode amplifier with transistors M 9 -M 16 . The cascode amplifier has the advantage of a large gain in a single stage, which simplifies frequency compensation. Transistors M 9 -M 16  work together with current sources M 1 -M 2  to drive the voltage on nodes n 1  and n 2  to equal values. Transistor pairs M 13 -M 14  and M 15 -M 16  are each connected in a current mirror configuration, so the same current drives the drains of transistors M 11  and M 12 . With n 2  above n 1 , transistors M 9  and M 11  will turn on to a greater degree than transistors M 10  and M 12 . Thus, the voltage on node n 3  will decrease. With the voltage on node n 3  decreasing, I PTAT  current sources M 1 -M 2  will turn on more strongly. Current I PTAT  will increase from M 1 -M 2  until the voltage drop across resistor R 1  equals a voltage difference ÎV BE  across transistors Q 1  and Q 2 .  
         [0046]    The biasing section is implemented with transistors M 25 -M 29 . Transistor M 26  provides a replica of the I PTAT  current. Transistor pairs M 25 -M 27  and M 25 -M 28  are connected in a current mirror configuration, so that transistors M 27  and M 28  each sink a current roughly equal to the I PTAT  current. This ensures that transistors M 13 -M 14  and M 9 -M 10  are properly biased. The bias for transistors M 11 -M 12  can be the V CC  rail or a separate bias point.  
         [0047]    A separate circuit is needed to avoid a stable state with zero currents in all branches. Although such a circuit is not shown, the implementation of such a circuit would be readily apparent to one of ordinary skill in the art.  
         [0048]    One advantage of the implementation in FIG. 5 is that it uses only substrate pnp bipolar devices, which are the only bipolar devices usually available in plain CMOS technologies. Another advantage is the low operating supply voltage. Because the minimum operating supply voltage is basically one V BE  plus one V DSAT  for an MOS device, the operating supply voltage could be below 1 V.  
         [0049]    [0049]FIG. 6 
         [0050]    [0050]FIG. 6 shows another embodiment of the I PTAT  current generator  405 . The only difference between the circuit of FIG. 5 and the circuit of FIG. 6 is that current sources M 1  and M 2  are cascoded with transistors M 5  and M 6 , respectively. This improves the power supply rejection, or in other words, it reduces the effect of power supply variations on the I PTAT  current. However, this improvement is obtained at the expense of a slightly large minimum operating voltage, since V CC  must be greater than two V DSAT  voltages in order to keep current sources M 1 -M 5  and M 2 -M 6  from saturating.  
         [0051]    The bias current source M 26  could also be implemented with a cascode device in accordance with the present invention. However, such an implementation would require a more complicated start-up circuit to avoid a stable state with zero currents in all branches.  
         [0052]    [0052]FIG. 7 
         [0053]    One of the implicit assumptions in the above description of FIGS.  5 - 6  is that transistors M 9  and M 10  are properly biased. In FIGS. 5 and 6 the input voltage at nodes n 1  and n 2  is one V BE . So this assumption is correct if the threshold voltage of transistors M 9  and M 10  is less than one V BE . Unfortunately, this cannot be guaranteed for all CMOS processes, or even for the same process over all corners.  
         [0054]    One solution to this issue is shown in FIG. 7 which shows another embodiment of the I PTAT  current generator  405 . In this embodiment, the base of Q 1  and resistor R 2  are disconnected from ground and driven by a secondary biasing loop, implemented with transistors M 35 -M 42 .  
         [0055]    The secondary biasing loop ensures that the voltage at nodes n 1  and n 2  is sufficiently high so that transistors M 9  and M 10  are properly biased. First, the secondary biasing loop makes the voltage at node n 2  equal to the voltage at node n 5 . To see this, assume the voltage at node n 5  is higher than the voltage at node n 2 . Transistors M 39  and M 40  are connected in a current mirror configuration to sink the same current to drive the drains of transistors M 37  and M 38 . With node n 5  above node n 2 , transistor M 37  turns on more than transistor M 38 , which causes the voltage at node n 6  to drop. When the voltage at node n 6  drops, transistor M 35  turns off to a greater degree. This increases the voltage at the base of transistor Q 1  which causes transistor Q 1  to turn off more and the voltage at node n 2  to increase. As described above, transistors M 9 -M 16  work together with current sources M 1 -M 5  and M 2 -M 6  to drive the voltage on nodes n 1  and n 2  to equal values. So when node n 2  increases, node n 1  also increases.  
         [0056]    Transistor M 42  provides a replica I PTAT  current. Transistor M 41  is connected as a two-terminal resistor, and is chosen such that the voltage at node n 5  is sufficiently high to bias transistor M 37 . Transistor M 36  sinks a current equal to I PTAT , thereby supplying the differential pair M 37 -M 38  with a constant bias current.  
         [0057]    [0057]FIG. 8 
         [0058]    [0058]FIG. 8 shows an embodiment of the I VBE  current generator  410  in accordance with the present invention. As in FIG. 3, this implementation comprises pnp bipolar transistor Q 3  and resistor R 2 . Current sources I 3  and I 4  in FIG. 3 are implemented with transistors M 3  and M 4  in FIG. 8. Opamp A 2  in FIG. 3 is implemented with transistors M 17 -M 24  and M 30 -M 34  in FIG. 8.  
         [0059]    The operation of transistors M 3 -M 4  is similar to the operation of transistors M 1 -M 2 , as described above with respect to FIG. 5. The magnitude of the current I VBE  generated by transistors M 3 -M 4  is substantially equal.  
         [0060]    The implementation of opamp A 2  with transistors M 17 -M 24  and M 30 -M 34  in FIG. 8 is similar to the implementation of opamp A 1  with transistors M 9 -M 16  and M 25 -M 29 , as described above. Nodes n 11 -n 14  in FIG. 8 correspond to nodes n 1 -n 4  in FIG. 5.  
         [0061]    As with the circuit of FIG. 5, the circuit of FIG. 8 uses only substrate pnp bipolar devices, the operating supply voltage could be below 1 V, and one of ordinary skill in the art would understand that a separate circuit is needed to avoid a stable state with zero currents in all branches.  
         [0062]    [0062]FIG. 9 
         [0063]    [0063]FIG. 9 shows another embodiment of the I VBE  current generator  410 . The only difference between the circuit of FIG. 9 and the circuit of FIG. 8 is that current sources M 3  and M 4  are cascoded with transistors M 7  and M 8 , respectively. As explained above, cascoding the current sources improves the power supply rejection, at the expense of a slightly larger minimum operating voltage. The bias current source M 31  could also be implemented with a cascode device in accordance with the present invention, at the expense of a more complicated start-up circuit.  
         [0064]    [0064]FIG. 10 
         [0065]    [0065]FIG. 10 shows another embodiment of the I VBE  current generator  405 . This embodiment includes a secondary biasing loop to ensure that the voltage at nodes n 11  and n 12  is sufficiently high so that transistors M 17  and M 18  are properly biased.  
         [0066]    The secondary biasing loop is implemented with transistors M 43 -M 50 . Transistors M 43 -M 50  function in a manner similar to M 35 -M 42 , which were described above with respect to FIG. 7. Nodes n 11 -n 16  in FIG. 10 correspond to nodes n 1 -n 6  in FIG. 7.  
         [0067]    [0067]FIG. 11 
         [0068]    [0068]FIG. 11 shows an embodiment of the current comparator  415  in FIG. 4. Nodes n 3  and n 4  are the corresponding bias nodes from the PTAT current generator, while nodes n 13  and n 14  are the corresponding bias nodes from the V BE  current generator.  
         [0069]    Transistor pairs M 51 -M 52  and M 53 -M 54  match transistor pairs M 1 -M 5  and M 3 -M 7  (from FIGS.  6 - 7  and  9 - 10 ). When the gates of transistor pairs M 51 -M 52  are biased with nodes n 3  and n 4  respectively, a replica I PTAT  current is generated that enters node n 20 . When the gates of transistors M 53 -M 54  are biased with nodes n 13  and n 14 , respectively, a replica I VBE  current is generated that enters the drain of transistor M 55 . Transistors M 55 -M 58  form a current mirror, so that transistors M 57 -M 58  sink a replica I VBE  current that exits node n 20 .  
         [0070]    Transistor pair M 60 -M 61  also matches transistor pair M 3 -M 7 . Transistor M 62  is connected as a two-terminal resistor, and is chosen such that the voltage at node n 22  is sufficiently high to bias transistor M 55 .  
         [0071]    The replica PTAT and V BE  currents are compared at the summing node n 20 . If I VBE  is larger than I PTAT , the voltage at node n 20  decreases until transistors M 57 -M 58  begin operating in the linear region to sink the I PTAT  current value. At this point, the equilibrium voltage at node n 20  is much less than the threshold voltage of M 70 , so the current comparator output at node n 21  is high. Conversely, if I PTAT  is larger than I VBE , the voltage at node n 20  increases until transistors M 51 -M 52  enter the linear region to source a current value equal to I VBE  In this case, the equilibrium voltage at node n 20  is much larger than the threshold value of transistor M 70 , so the current comparator output at node n 21  is low.  
         [0072]    The total current at the output node n 21  can be made roughly temperature independent by rationing the V BE  and PTAT currents through transistor pairs M 63 -M 64  and M 65 -M 66 .  
         [0073]    Transistors M 67 -M 68  are smaller than transistors M 51 -M 52 . This creates a reduced version of the PTAT current that is gated into the summing node n 20  by the transistor M 69 , driven by the output node n 21 . This configuration enables a hysteresis behavior with the width of the hysteresis determined by the relative ratios of the currents through M 51  and M 67 , which can be easily designed by the geometry of the two devices.  
         [0074]    Cascode devices M 52 , M 54 , M 61 , and M 68  improve the power-supply rejection.  
         [0075]    [0075]FIG. 12 
         [0076]    One way to test a low-voltage thermostat circuit is to heat or cool the circuit to the desired temperature and do the testing or tuning at that temperature. This method would also enable one to tune the exact crossing point. The problem with this method is that it is very expensive.  
         [0077]    [0077]FIG. 12 shows a circuit which can be used in order to test or tune a low-voltage thermostat circuit in accordance with the present invention at room temperature. This circuit comprises transistors M 71 -M 76 , current sources I 5  and I 6 , resistor R 3 , and capacitor C 1 .  
         [0078]    When transistor M 76  is turned on, current I 6  is added into or subtracted from the summing node n 20 . This alters the ratio of I PTAT  and I VBE , which is equivalent to shifting the temperature of the device. Because I 6  can be a well-defined fraction of I VBE  or I PTAT , the temperature shift can be known.  
         [0079]    The functionality of the circuit in FIG. 12 is based on forcing node n 30  below ground potential. Transistors M 71 -M 75  form a differential amplifier which has a built-in offset of 200-300 mV. This offset is created by unbalancing the geometry of input transistors M 71 -M 72 . If the voltage at node n 30  is below ground by more than this built-in offset, the output of this amplifier becomes active and the test circuit can inject or subtract current I 6  into the summing node n 20  of the current comparator.  
         [0080]    The R 3 -C 1 , filter rejects narrow spikes, to prevent noise that would otherwise put the circuit in test mode. Current source I 5  is used to properly bias the differential amplifier.  
         [0081]    Because one embodiment of the thermostat circuit in accordance with the present invention has only three terminals (power, ground, and output), it fits very well into very small packages. It is preferable for the testing/tuning circuit not to add additional output pads.  
       CONCLUSION  
       [0082]    Although the present invention has been described above with particularity, this was merely to teach one of ordinary skill in the art how to make and use the invention. The present invention is not limited to the above embodiments. Many additional modifications will also fall within the scope of the invention, as that scope is defined by the claims which follow.