Abstract:
A double-diffused insulated-gate field effect transistor is disclosed having impurity regions each acting as a channel base region and depletion layer preventing regions having a high concentration impurity and being of a conductivity type opposite to that of the base region. With the transistor in the ON state a depletion layer is confined within the depletion layer preventing region, preventing an increase in ON resistance in a narrow region between the channel base regions. The concentration and diffusion depth of the depletion layer preventing region are such that, due to the presence of the depletion layer preventing region, the reverse bias voltage between the channel base region and a drain region causes no avalanche breakdown between the channel base region and the drain region.

Description:
This application is a continuation of application Ser. No. 808,252, filed Dec. 12, 1985 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a double-diffused, insulated-gate, field effect transistor. 
     2. Description of the Prior Art 
     FIGS. 1(A) and 1(B) show a known double-diffused, insulated-gate, field effect transistor. As shown in these figures, the transistor comprises a semiconductor substrate consisting of N +  semiconductor layer 1a and N -  semiconductor layer 1b formed on the layer 1a. Layer 1b acts as a drain region. Channel base regions 2 of the P conductivity type are formed in layer 1b, spaced apart from each other. Narrow region 3, generally called a neck area, is provided between regions 2. Source electrode 5 is buried in insulating layer 4 overlying channel base regions 2. Gate electrode 6 is formed in insulating layer 4 and overlies region 3. 
     Let us assume that a power MOSFET having a high reverse bias voltage of hundreds of volts (e.g., 400 V) of the structure described above is manufactured. The conduction path 100 of this power MOSFET is prominently narrowed due to the broadening of a depletion layer formed in narrow region 3. This increases the ON resistance of the power MOSFET. Hence, the magnitude of the ON current of the MOSFET is about ten times lower than that of a power MOSFET having a lower reverse bias voltage of, for example, 60 V, provided the narrow regions of the power MOSFET are of equal size. One solution of this problem is to broaden region 3. This solution results in a decrease of effective channel width per unit area. This decrease does not occur in the MOSFET shown in FIG. 2, wherein N +  impurity area 8 having the same diffusion depth as channel base regions 2 is formed in narrow region 9 present between regions 2. 
     The MOSFET of FIG. 2 has a drawback, however. Since entire region 8 is an N +  type region, the source-to-drain reverse bias voltage, V DSS , is determined by channel base regions 2 and N +  impurity area 8. Hence, the MOSFET cannot have a high reverse bias voltage. To raise the reverse bias voltage, depletion layer 7 must be formed below narrow region 3, thus floating the potential of impurity area 8. This method improves the ON characteristic of the MOSFET, as experimentally proved, but narrow area 9 is left between depletion layer 7, immediately below N +  region 8. 
     Hitherto it has been possible to solve the above-noted problem completely. 
     SUMMARY OF THE INVENTION 
     Accordingly, the object of this invention is to provide a double-diffused, insulated-gate, field effect transistor which has an improved ON-resistance characteristic and a high reverse bias voltage. 
     According to this invention, there is provided a double-diffused, insulated-gate, field effect transistor comprising a semiconductor substrate of a first conductivity type, two impurity regions of a second conductivity type formed, at a predetermined interval, in the semiconductor substrate, high concentration impurity regions of the first conductivity type formed in predetermined region of each impurity region of the second conductivity type, and depletion layer preventing regions each formed along an interface between each impurity region of the second conductivity type and the semiconductor substrate and having a high impurity concentration. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1(A) and 1(B) are a cross-sectional view and a plan view of a conventional MOSFET respectively; 
     FIG. 2 is a cross-sectional view of another conventional MOSFET structure; 
     FIG. 3 is a cross-sectional view showing a MOSFET structure according to an embodiment of this invention; 
     FIG. 4 explains the operation of a transistor of FIG. 3; 
     FIG. 5(A) shows the impurity concentration profile on a junction of the transistor of FIG. 3. 
     FIG. 5(B) shows the relationship between a critical electric field and the broadening of a depletion layer for the transistor of FIG. 3; 
     FIG. 6 shows the relationship between a critical electric field and the broadening of a depletion layer for the transistor of FIG. 3; and 
     FIG. 7 explains the relationship between a critical electric field and an impurity concentration level for the transistor of FIG. 3. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A transistor according to one embodiment of this invention will be explained by referring to FIG. 3. 
     As shown in FIG. 3, a semiconductor substrate 10 is comprised of N +  semiconductor layer 10a, and N -  semiconductor layer 10b formed on the semiconductor layer 10a and serving as a drain region. Impurity regions 11 of the P conductivity type are formed, at a predetermined interval, in N -  semiconductor layer 10b and serve as channel base regions. Depletion layer preventing regions 12 are formed at an interface between impurity regions 11, on the one hand, and N -  semiconductor layer 10b, on the other. These regions are comprised of an N +  conductivity type impurity layer of a high impurity concentration. N +  conductivity type impurity regions 13 of a high impurity concentration, serving as source regions, are formed, at predetermined intervals, in each impurity region 11, respectively. Insulating layer 14 is formed on the N -  semiconductor layer. Source electrode 15 is formed, extending through contact hole 14a cut in the insulating layer 14, and connected to impurity region 13. Gate electrode 16 is buried in the insulating layer 14 overlying the impurity regions 11. Drain electrode 17 is formed on the N +  semiconductor layer 10a. Impurity region 13, impurity region 11, depletion layer preventing region 12 and N -  semiconductor layer 10b have different impurity concentrations decreasing in that order. 
     The source-to-drain current of a transistor 20 so formed will be explained in connection with the broadening of the depletion layer at the gate ON time (V DS (ON)) and gate OFF time (V DSS ), while referring to an enlarged view of the major transistor portions as shown in FIG. 4. For ease in explanation, assume that the impurity concentration profile of N -  semiconductor layer 10b, depletion layer preventing region 12 and impurity region 13 are stepped, and that the layers have the concentration levels and resistivities shown in the following table. T1 -impurity? ? -concentration? resistivity? - N -   semiconductor layer 10b 2 × 10 14  cm -3   24 Ω · cm - depletion layer 1 × 10 16  cm -3  0.5 Ω · cm -preventing area - 
     With transistor 20 put in the ON state at the source-to-drain voltage V DS (ON) =10 V, the extending of the depletion layer toward the depletion layer preventing region 12 is evaluated. If the impurity concentration of impurity region 11 provides an adequately high step junction to depletion layer preventing region 12, most of the depletion layer extends toward depletion layer preventing region 12 only, as given by: ##EQU1## where KS: a constant 
     q: an electric charge 
     ε o  : a dielectric constant of a vacuum 
     V DS  : the source-to-drain voltage 
     N D  : the impurity concentration level of region 12. 
     Substituting the respective values into Equation (1) gives: ##EQU2## 
     From this it will be understood that the depletion layer extends about 1.14μ toward depletion layer preventing region 12. In this case, the junction concentration distribution (sheet resistivity) is as shown in FIG. 5(A) and the distribution of the electric field is as shown in FIG. 5(B). Hence the width of region 12 is set to the order of 1.4μ. 
     In the absence of any depletion layer preventing region around impurity layer 13, the broadening of the depletion layer will be given by: ##EQU3## where N D  (N + ) is replaced by N D  (N - ). 
     Obviously, in the absence of the depletion layer preventing region, the depletion layer is broadened to an extent about 7 times as much as in the presence of a depletion layer preventing region. In FIG. 4, the broken line shows the broadening of depletion layer 19 achieved in the absence of region 12. In this case, a conduction path 200 of a narrow region 18, which is formed between impurity regions 11 and 11, is narrowed, resulting in an increase of ON resistance. 
     The determination of a breakdown voltage (V DSS ) at the OFF time of transistor 20 will now be explained. FIG. 6 shows an electric field distribution at the breakdown time. FIG. 7 shows the relationship between the intensity of the critical electric field and the impurity concentration which is important for evaluation. The breakdown voltage (BV) of the step junction will be expressed as follows: ##EQU4## 
     Using Equation (4) with respect to the impurity region 11 and region 12, we obtain: ##EQU5## 
     This indicates the breakdown voltage (BV) when the depletion layer was broadened a necessary amount toward depletion layer preventing region 12. At this time, the distance, over which the depletion layer was broadened, is given below, using Equation (1): ##EQU6## 
     According to this invention, the width of the depletion layer preventing region 12 is set to exactly 1.14μ. This value is a minimal dimension, whereby with the transistor in the ON state at V DS (ON) =10 V, the depletion layer is suppressed. Since, however, it is insufficient in this case to completely set this value to a theoretical one, explanation will be given below with the width of region 12 (W 1  &#39;=1.3×10 -4  cm) being set to 1.3μ with an allowance of about 10%. 
     In the transistor 20 of this invention, N -  semiconductor layer 10b contacts depletion layer preventing region 12. In actual practice, the distribution of an electric field over the junction between region 12 and layer 10b varies as indicated by the solid line in FIG. 6. It is found that, unless the field strength at the point of change exceeds a critical electric field (ε crit (N.spsb.-.sub.)), determined by the impurity concentration level of N -  semiconductor layer 10b, the avalanche breakdown is suppressed by the critical electric field (ε crit (N.spsb.+.sub.)) determined by the impurity concentration level of the region 12. 
     In calculating the breakdown voltage (V DSS ) of the transistor in the OFF state, it is important to find the strength of the electric field (ε crit (N.spsb.-.sub.)) at the changeover point of the inclination of the electric field distribution. 
     As evident from FIG. 6, the electric field strength on the changeover point is found from the following relation: ##EQU7## 
     Substituting the respective associated values into Equation (7), we get: ##EQU8## 
     Upon the calculation of the reverse bias voltage borne by the N -  semiconductor layer 10b by the use of E crit (N.spsb.-.sub.), the following equation is obtained: ##EQU9## 
     On the other hand, the reverse bias voltage borne by depletion layer preventing region 12 can be expressed as follows: ##EQU10## 
     Substituting the respective values into Equation 10 gives: ##EQU11## 
     The total breakdown voltage, being a sum of BV.sub.(N.spsb.+.sub.) and .sub.(N.spsb.-.sub.), can be expressed as follows: ##EQU12## 
     This value is determined to be the source-to-drain reverse bias voltage V DSS . As appreciated from FIG. 7, E crit (N.spsb.-.sub.) of the N -  semiconductor layer 10b is 2.3×10 5  (V/cm). 
     However, the peak electric field E crit (N.spsb.-.sub.) of the N -  semiconductor layer merely attains 2.2×10 5  (V/cm) and, therefore, the depletion layer preventing region 12 first attains a critical electric field: 
     
         E.sub.crit(N.spsb.+.sub.) =4.2×10.sup.5 [V/cm], 
    
     which value governs the breakdown phenomenon. It may not be said that an adequate theoretical breakdown value is attained from the impurity concentration of N -  semiconductor layer 10b. Accordingly, any deviation from the theoretical breakdown value thus evaluated can be recognized from the above considerations. In the absence of the depletion layer preventing region 12, the breakdown voltage is given by: ##EQU13## 
     Thus, the deviation can be expressed by the following equation (14), noting that the reverse bias voltage is lowered by about 3.6%. 
     
         BV.sub.(N.spsb.-.sub.) -BV.sub.(N.spsb.+.sub.,N.spsb.-.sub.) =857-826=31[V](14) 
    
     A higher reverse bias voltage is attained according to this invention by making E crit (N.spsb.-.sub.) as close to ε crit (N.spsb.-.sub.) as possible, making the concentration of depletion layer preventing region 12 as high as possible and making region 12 thinner. According to this invention, the impurity region 11 is formed by inverting region 12 by diffusing the P type impurity and, therefore, it is not possible to unduly increase the impurity concentration of region 12 with respect to the impurity concentration level of impurity region 11. Now suppose that region 12 is made extremely high in its concentration level and thinner in its width. In this case, the critical electric field E crit , which governs the breakdown, is merely shifted from E crit (N.spsb.-.sub.) to E crit (N.spsb.-.sub.). This does not mean that the reverse bias voltage will be lowered. 
     The advantage of this invention will be explained with reference to the dimensions of the layer and region shown in FIG. 4. 
     The resistance per unit width of narrow region 18 provided between the impurity regions 11 of the transistor put in the ON state at V DS  (drain voltage) of 10 V is given below: ##EQU14## 
     In the absence of depletion layer preventing region 12, the following equation is obtained: ##EQU15## 
     Thus, a simple effect ratio α is: 
     
         α=110/5.3≈20 
    
     Obviously, the current path resistance of narrow area 18 between the impurity regions 11 is improved by about 20-fold. Hence, the area of a power MOSFET to achieve a high reverse bias voltage (V DSS  &gt;400 V), which area has had to be greatly increased in the prior art, can now be extensively decreased. 
     Although in the above-mentioned embodiment explanation is given of a double-diffused insulated-gate FET of an N channel type, this invention can be applied to the P channel type.