Abstract:
Apparatus for baseline restoration in an AC-coupled signal is comprised of a differentiation circuit followed by an integration circuit to receive the signal and continually restore its DC reference. Both circuits are initially set to the DC reference, and reset after a lapse of some predetermined period based upon the worst case signal-to-noise ratio anticipated for the system. Transmission is terminated, or interrupted, before resetting. A header may be used to signal resumption of transmission to the apparatus in an asynchronous receiving mode. In a synchronous receiving mode, the transmission is simply interrupted at each time the apparatus is reset.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a method and apparatus for baseline restoration in AC-coupled signals, and more particularly to a circuit for restoring the DC reference of random signals. 
     Whenever random codes are serially transmitted through an AC-coupled system, such as an FM radio link, there will exist at the receiving terminal a continually varying DC offset with respect to the originally transmitted signal. This random modulation of the DC reference is commonly referred to as a &#34;galloping baseline&#34; which, at any one instant, may be viewed as a fixed baseline offset of the signal relative to a reference. 
     In all practical systems, it must be assumed that the transmission link is limited in bandwidth and is fully capable of modulating the signal with some form of noise. The interpretation of a signal distorted by noise in such a transmission link is greatly aided if the true baseline of the modulated signal is known. An object of this invention is to provide an improved circuit for restoring the baseline of an AC-coupled signal. 
     SUMMARY OF THE INVENTION 
     In accordance with an important aspect of an exemplary embodiment, a differentiation circuit or network is followed by an integration circuit or network in cascade to receive an AC-coupled signal and continually restore its DC reference. Both circuits are initially set to the DC reference, and both are reset after a lapse of some predetermined period based upon the worst case signal-to-noise ratio anticipated for the information link. If used in an asynchronous receiving mode, transmission is limited to this period, after which another transmission may be initiated with a header which, upon being detected, initiates a reset. In a synchronous receiving mode, the reset is triggered periodically, and transmission is interrupted during the reset. 
     The novel features that are considered characteristic of this invention are set forth with particularity in the appended claims. The invention will best be understood from the following description when read in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a functional block diagram of the present invention. 
     FIG. 2 is a timing diagram useful in understanding the problem which the present invention solves. 
     FIG. 3 illustrates an asymmetrical digital signal to be coupled by an AC coupling circuit. 
     FIG. 4 illustrates a basic AC coupling circuit. 
     FIG. 5 illustrates the signal of FIG. 3 coupled by an AC coupling circuit. 
     FIGS. 6 through 9 illustrate frequency response diagrams useful in understanding design criteria of the differentiator and integrator of FIG. 1. 
     FIG. 10 illustrates an exemplary circuit design for the differentiator, integrator and initializing circuit of FIG. 1. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     As will be more fully described hereinafter, the invention is based upon the realization that, for a &#34;slowly galloping&#34; baseline, i.e., for a baseline that varies slowly as compared to the rate of change of the information in the signal, the slope of the AC-coupled signal is approximately equal to the slope of the signal if DC coupled. Therefore, to restore the DC reference lost in the AC coupling, what is necessary is to first detect the slope of the AC coupled signal, beginning at a known reference, and to then reconstruct the AC-coupled signal with its DC reference, also beginning at the known reference. If this is done, the AC-coupled signal will have been restored with its original DC properties. Error in this process is limited to the accuracy with which the slope of the baseline in the AC-coupled signal is assumed to be negligible, but measurable, when compared with the slope of the information signal. 
     FIG. 1 shows a block diagram of a baseline restorer according to this method. Basically, there are only three essential parts to the circuit: a differentiator 10, an integrator 11, and an initializing circuit 12. Although the need for each of these parts has been outlined above, verification of the process can only be by mathematical analysis. Before presenting such an analysis, some characteristics of digital signals will first be discussed (as an exemplary aid in the understanding of baseline shifting). Refer to FIG. 2 in which waveform A shows a symmetrical bipolar digital signal centered about its true baseline. The properties of this ideal signal are such that the magnitude of the slope at the discontinuities is infinite and the slope is zero everywhere else. If accurate interpretation of this signal were desired, it would be sufficient to merely determine the polarity of the signal with respect to either its AC or DC reference (where these are identical for a symmetric signal). A very simple diode clamp circuit could be used to accomplish that, provided sufficient signal amplitude exists at the input port to fully saturate the diodes. 
     Useful logic signals are, however, most generally random or pseudorandom sequences of &#34;1&#39;s&#34; and &#34;0&#39;s&#34; which, as a result of AC coupling, require that their electrical baseline be shifted from the true DC reference. An example of this phenomenon is shown in waveform B (where it has been assumed that this waveform is periodic). The electrical baseline for any AC coupled signal will be that level which equalizes the areas of the waveform both above and below it. For the specific example of waveform B, the electrical baseline (0 V) lies above the true baseline indicated by a dotted line. Again, assuming that sufficient input signal amplitude exists, the diode clamp could be used to accurately interpret this logic signal. 
     The two previously examined logic signals would occupy an infinite amount of bandwidth. Let us now consider the same periodic signal of waveform B restricted in bandwidth to half the fundamental frequency of the clock signal (the optimal bandwidth of a transmission link for maximum signal-to-noise ratio). This signal is shown in waveform C. In this example, if the diode clamp circuit were used to reconstruct the digital signal from the bandlimited signal, a signal similar to that shown in waveform D would be produced at its output. Careful comparison of this signal with the infinite bandwidth signal of waveform B shows that the positive duty cycle has been shortened while the negative duty cycle has been increased. This phenomenon also occurs exhibiting a more severe zero crossing distortion for the case of a bandlimited signal with additive noise as shown in waveforms E and F. (The clock waveform has been repeated before and after waveforms E and F to facilitate noting the change in timing in the resulting data waveform F with respect to the original waveform B.) In an effort to preserve timing, it would be desirable to integrate the interpreted waveform over an entire bit period (one clock cycle) and then determine the bit type by comparing the positive and negative duty cycles for that period. With this form of bit determination, the zero crossing distortion must be limited to less than fifty percent of the bit period. When noise is mixed with the signal, the probability of exceeding this limit increases rapidly as the ratio of &#34;1&#39;s&#34; to &#34;0&#39;s&#34; is raised. For example, a signal which has a &#34;1&#39;s&#34; to &#34;0&#39;s&#34; ratio of 1:25 will shift its baseline by 12/13 of its peak amplitude or by about 46.2% of its peak-to-peak amplitude. If the signal is bandlimited, a shift as drastic as 46% will, even without the effects of noise, produce interbit interference during integration. Therefore, it is seen that the diode clamping type of interpreter cannot be used when large &#34;1&#39;s&#34; to &#34;0&#39;s&#34; ratios are present in a bandlimited system. 
     The solution to this problem might seem to be a circuit that would force a baseline to be restored precisely between the peaks of the incoming signal. This, however, is not always useful and can, in fact, produce even worse distortion than the diode clamp circuit. This method has two major sources of error. The first of these sources of error is the error between the detected peak voltages and the actual peak voltages. The second source of error is the susceptibility of this circuit to noise spikes. Spikes can often occur in a transmission link where nonlinear distortion is unavoidable. One example is an FM transmission link where the effects of FM-multipath can produce spike distortions. The peak detecting baseline restorer is actually capable of introducing a greater baseline distortion than would occur from AC coupling the same signal. Thus there exists a need for a baseline restorer which can accommodate additive noise, spikes and a large &#34;1&#39;s&#34; to &#34;0&#39;s&#34; ratio. 
     A mathematical analysis of the system of FIG. 1 will now be presented. Consider the asymmetric signal of FIG. 3. Writing the time equation: 
     
         f.sub.i (t) = A[U.sub.1 (t-T.sub.0) - 2U.sub.1 (t-T.sub.1) + U.sub.1 (t-T.sub.2)]                                              (1) 
    
     where f i  (0)  =   0.0. Performing the La Place transform: 
     
         f.sub.i (t) ⃡ F.sub.i (s) 
    
     
         F.sub.i (s) = (A/s)(e.sup.-T.sbsp.0.sup.s - 2e.sup.-T.sbsp.1.sup.s + e.sup.-T.sbsp.2.sup.s)                                    (2) 
    
     Now consider the voltage transfer function for the basic AC coupling circuit shown in FIG. 4: 
     
         v.sub.o (s) = [s V.sub.i (s) - q.sub.o /C]/[s + 1/(RC)]    (3) 
    
     where q o  .tbd. the total charge on the capacitor at time t = 0, which is the expression for the output as a function of the input in the frequency domain with initial conditions. 
     Next determine the output from the AC coupling circuit when the input is the asymmetric signal. Performing the inverse La Place transform: 
     
         V.sub.o (s) ⃡ v.sub.o (t) 
    
     
         v.sub.o (t) = {A[U.sub.1 (t-T.sub.0)e.sup.-(t-T.sbsp.0.sup.)/(RC) - 2U.sub.1 (t-T.sub.1)e.sup.-(t-T.sbsp.1.sup.)/(RC) + U.sub.1 (t-T.sub.2)e.sup.-(t-T.sbsp.2.sup.)/(RC) ] - (q.sub.o /C)e.sup.-t/(RC) }(4) 
    
     a sketch of this waveform (using highly exaggerated and straight-lined exponential notation) is shown in FIG. 5. If it is assumed that q o  /C is not zero, then examination of this waveform shows the &#34;galloping baseline&#34; effect brought about by the asymmetry of the waveform. The physical process which has occurred here is the repositioning of charge on the plates of the capacitor in an attempt to equalize the concentration of positive and negative charges. The time constant at which this is accomplished is RC (where the diagram of FIG. 5 represents a small value of RC). 
     When a transmission link increases in complexity (by, for example, the inclusion of a radio link), the information signal will be subjected to the effects of many AC coupling circuits, all of which will have a different time constant. The smallest time constant among all of the couplings will, however, determine the degree of distortion caused by the &#34;galloping baseline.&#34; Theoretically, one can argue that if the slowest rate of change of the information signal is very much faster than the rate of change of the AC coupled baseline, then the baseline&#39;s rate of change can be viewed as nearly a constant with respect to the information signal&#39;s rate of change. If an information signal possesses these properties, then it is possible to differentiate the signal to obtain its slope without the introduction of a significant error from the slowly varying baseline term. 
     It can be shown mathematically that the baseline term containing q o  /C is effectively removed from the signal by the differentiating circuit. However, the signal now is the derivative of the desired signal, and it is necessary to integrate to obtain the actual signal desired, as follows: Let v r  (t) .tbd. the asymmetric information signal after having been AC coupled, differentiated and integrated. 
     
         v.sub.r (t) = A[U.sub.1 (t-T.sub.0) - 2U.sub.1 (t-T.sub.1) + U.sub.1 (t-T.sub.2)] + k                                          (5) 
    
     where k is a constant of integration. Comparison of v r  (t) with the asymmetric signal f i  (t) of equation (1) shows that they are dissimilar only by a constant of integration. 
     Thus it has been shown that any signal that has been AC coupled and suffers from a slowly varying electrical baseline reference can be restored to a known baseline within an error that is in direct relationship to the difference between the maximun rate of change of the baseline and the minimum rate of change of the information signal. The known baseline is the resulting constant of integration. 
     The specific designs of the transfer functions for the differentiator 10 and integrator 11 of FIG. 1 will depend largely upon the bandwidth of the information signal (waveform C of FIG. 2, for example). Th magnitude transfer function of a true differentiator is represented by a straight line with a slope of +6db per octave (+20 db/decade), as shown in FIG. 6. Similarly, the magnitude transfer function of a true integrator is represented by a straight line having a slope of -6db per octave (-20 db/decade), as shown in FIG. 7. In practice, each transfer function is magnitude-limited at some frequency as indicated by dotted lines. If a practical differentiator is combined in cascade with a practical integrator, and a gain factor is included in each, the combined transfer function will be the sum of the separate transfer functions as shown in FIG. 8 where the sum is represented by a solid line, and the respective differentiator and integrator transfer functions are represented by dotted lines. If in addition to gain, the differentiator circuit is provided with upper frequency attenuation above the bandwidth of the information signal, a composite transfer function will result as shown in FIG. 9, where the composite transfer function is shown in a solid line, and the differentiator and integrator transfer functions are shown in dotted lines. The design and implementation of an actual circuit can approximate such a composite transfer function. 
     An exemplary circuit of the present invention is shown in FIG. 10. The differentiator circuit has the following voltage transfer function (in the frequency domain): 
     
         V.sub.o /V.sub.i (s)=-C.sub.1 /[R.sub.1 C.sub.2 (C.sub.1 +C.sub.3)]s/([s+1/(R.sub.2 C.sub.2)][s+1/(R.sub.1 [C.sub.1 +C.sub.3 ])](6) 
    
     from this equation it is easy to see that the circuit has a zero at the origin of the complex s-plane and two poles: one at s = -1(R 2  C 2 ) and a second at s = -1/[R 1  (C 1  +C 3 )]. Because it is highly desirable to maintain a large signal-to-noise ratio, both poles should be chosen to occur coincident with the highest frequency of the information signal. With these zero and pole locations, all signals within the frequency band of the information signal will be differentiated and all signals above this band will be attenuated. For applications requiring a moderate bandwidth and gain, this circuit can be constructed using realistic component values. 
     The integrator circuit has the following voltage transfer function (in the frequency domain): 
     
         V.sub.o /V.sub.i (s) = -[1/R.sub.4 C.sub.4)]/[s+1/(R.sub.5 C.sub.4)](7) 
    
     note that this circuit approximates an integrator for frequencies at least one order of magnitude greater than the frequency location of the pole determined by C 4  and R 5 . When this circuit is placed in series with the differentiator circuit as shown, all frequency components greater than those contained in the information signal are attenuated at the rate of -12 db/octave. 
     The differentiating and integrating circuits shown in FIG. 10 will approximate to a first order the processes of voltage differentiation and integration respectively. For applications involving narrow information bandwidths, it may be necessary to design circuitry which will give a more accurate approximation of these processes. When designing the circuitry, it is important to maximally attenuate all frequencies both above and below the information bandwidth. Attenuation of the lower frequencies will aid in limiting the galloping baseline effects, and the combined level of all frequency components outside the information band is directly related to the frequency at which the zeroing process must be repeated. The main disadvantage of using any first order approximation circuitry is seen when the differentiator is placed in series with the integrator. Ideally, the transfer response for this topology across the information bandwidth should be a maximally flat amplitude response and a linear phase response. 
     Referring now to the initializing circuit 12, it is assumed that the baseline restoration circuit is to be operated in a system where a significant amount of noise exists in the absence of the information signal. One example of this type of signal source is the output of an FM receiver that employs a limiter in its demodulation circuitry. Noise of this form can contain frequency components outside the band of interest and its presence can cause an error voltage to accumulate across the integrating capacitor C 4 . This change in the integrator&#39;s reference voltage would force the superposition of a constant voltage level (random in both sign and magnitude) onto the processed information signal. The initializing circuit, however, is designed to reset the integrator&#39;s reference. 
     Initialization is accomplished by first ensuring that the voltages across C 1 , C 3  and C 4  are all simultaneously set to zero (thereby establishing the integrator&#39;s reference as zero) and secondly by limiting the rate of change of the voltage across C 3 , immediately after zeroing, to remain within the bandwidth of the differentiator and integrator. This rate of change of voltage is dependent upon all three components R 1 , C 1  and C 3  and has the time constant R 1  (C 1  +C 3 ) which, of course, is directly related to the bandwidth of the differentiator. To zero C 1 , C 3  and C 4 , a pulse must be passed through the diodes CR1A to CR1D and CR2A to CR2D of sufficient amplitude to cause them to saturate and of sufficient duration to allow the discharge of the capacitors through the effective impedance of the diodes. To maintain a reverse biased condition on the diodes at all other times, the zeroing pulse is AC coupled through the pulse transformer T 1  and capacitors C.sub. 11 and C 12 . 
     The zeroing of the restoration circuit must occur whenever the integrating capacitor accumulates a charge level sufficiently large to degrade the reliability of the bit interpreting process discussed earlier. This type of shift in the baseline is a function of the amplitude of the noise frequency components which lie outside the information bandwidth. The periodicity of the zeroing processing must be determined analytically to satisfy a given error probability. Furthermore, this calculation is strongly dependent upon the degree of filtering prior to the restoration circuitry and the noise figure of the entire transmission link. It is also extremely important that the zeroing process occurs when the value of the transmitted signal is fixed, for the duration of the entire zeroing process, at the reference voltage of the restoration circuitry. Because the reference voltage must be adjusted by the gain of the system, this reference is most logically chosen to be zero. From these restrictions it is now seen that once a point in common is established simultaneously by the transmitter and receiver, it is only necessary to track the deviation from this reference to reconstruct the original signal. 
     In operation, an AC-coupled signal V i  is differentiated as a function of time, starting from a predetermined initial voltage of zero, by an RC network comprised primarily of resistor R 1  and capacitor C 1 . This process limits the galloping baseline effects. The output V od  of amplifier A 1  is then integrated as a function of time, starting from a predetermined initial voltage V REF , by the feedback network R 5  and C 4  of the operational amplifier A 2  to obtain an output voltage, V o , that is the desired AC-coupled signal with its baseline restored. The baseline will be restored relative to the baseline reference voltage, V REF , applied to the operational amplifier A 2  through a resistor R 6 . In the usual case, that reference voltage is conveniently set to zero by connecting the resistor R 6  to circuit ground. To initialize the differentiator and integrator, a positive pulse applied to the base of transistor Q 1  is coupled by the pulse transformer T 1  to the switch comprised of diodes CR1A to CR1D and to the switch comprised of diodes CR2A to CR1D to discharge the capacitor C 3  to zero (circuit ground) and the capacitor C 4  also to zero (virtual ground). 
     The advantages of the baseline restoration circuit presented here are its immunity to noise spiking, narrow bandwidths and large &#34;1&#39;s&#34; to &#34;0&#39;s&#34; ratios. To obtain these features it was necessary to require a well defined zeroing process which must be repeated periodically. For many applications this restriction is easily accommodated by the addition of a suitable preamble to the transmitted message. This method of implementation is recommended for communication links with relatively low transmission duty cycles. As the duty cycle increases, synchronous methods of determining zero periods become more attractive, allowing the initializing process to occur within a few bit periods. Thus, in some applications, the receiver may be conveniently synchronized with the transmitter. In such a synchronous system, a transmission may be commenced with a header, that is detected by a detector circuit 13, which includes a circuit to synchronize periodic pulsing of the initializing circuit in synchronism with interruptions in the transmission. In other applications, where the receiver is not synchronized with the transmitter, the functional block 13 would include only a header detector to pulse the initializing circuit at the beginning of a transmission. Each transmission must then be limited at the transmitter to the maximum period that the baseline restoration circuit may be permitted to operate without being reset. If there is additional information to be transmitted, it is divided into blocks and transmitted with a header for each block. 
     Although particular embodiments of the invention have been described and illustrated herein, it is recognized that modifications and equivalents may readily occur to those skilled in the art and consequently it is intended that the claims be interpreted to cover such modifications and equivalents.