Abstract:
A semiconductor structure and methods for forming the same. A semiconductor fabrication method includes steps of providing a structure. A structure includes (a) a dielectric layer, (b) a first electrically conductive region buried in the dielectric layer, wherein the first electrically conductive region comprises a first electrically conductive material, and (c) a second electrically conductive region buried in the dielectric layer, wherein the second electrically conductive region comprises a second electrically conductive material being different from the first electrically conductive material. The method further includes the steps of creating a first hole and a second hole in the dielectric layer resulting in the first and second electrically conductive regions being exposed to a surrounding ambient through the first and second holes, respectively. Then, the method further includes the steps of introducing a basic solvent to bottom walls and side walls of the first and second holes.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates generally to semiconductor fabrication, and more specifically, to removal of etching process residual in semiconductor fabrication. 
       BACKGROUND OF THE INVENTION 
       [0002]    In a conventional semiconductor fabrication process, vias are formed to provide electrical access to the underlying metal lines. The vias are created by a plasma etching process which leaves residual on side walls and bottom walls of the via holes. Therefore, there is a need for a process to remove the residual before the via holes are filled with an electrically conductive material to form the vias. 
       SUMMARY OF THE INVENTION 
       [0003]    The present invention provides a structure formation method, comprising providing a structure which includes (a) a dielectric layer, (b) a first electrically conductive region buried in the dielectric layer, wherein the first electrically conductive region comprises a first electrically conductive material, and (c) a second electrically conductive region buried in the dielectric layer, wherein the second electrically conductive region comprises a second electrically conductive material being different from the first electrically conductive material; creating a first hole and a second hole in the dielectric layer resulting in the first and second electrically conductive regions being exposed to a surrounding ambient through the first and second holes, respectively; and introducing a basic solvent to bottom walls and side walls of the first and second holes resulting in a removal of polymer residues on the bottom walls and side walls of the first and second holes. 
         [0004]    The present invention provides a process to remove the residual before the via holes are filled with an electrically conductive material to form the vias. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIGS. 1A-1M  illustrate (cross-section views) a fabrication method for forming a semiconductor structure, in accordance with embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0006]      FIGS. 1A-1M  illustrate (cross-section views) a fabrication method for forming a semiconductor structure  100 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , in one embodiment, the fabrication of the semiconductor structure  100  starts out with an ILD (Interlevel Dielectric Layer) layer  110 . Illustratively, the ILD layer  110  can comprise silicon dioxide or a low-K (i.e., K&lt;3) material, wherein K is the dielectric constant. In one embodiment, the ILD layer  110  is formed on top of a device layer of a semiconductor integrated circuit (not shown) which is omitted from this and later figures for simplicity. The device layer is a layer on top of a silicon wafer (not shown) where devices such as transistors are formed. 
         [0007]    Next, in one embodiment, a metal line  112  is formed in the ILD layer  110  by using a conventional damascene method. In one embodiment, the metal line  112  comprises copper (Cu). In one embodiment, the metal line  112  is electrically coupled to devices (not shown) of the underlying device layer. 
         [0008]    Next, with reference to  FIG. 1B , in one embodiment, a first cap layer  120  is formed on top of the entire structure  100  of  FIG. 1A . In one embodiment, the first cap layer  120  is formed by CVD (Chemical Vapor Deposition) of a dielectric material on top of the ILD layer  110  and the metal line  112 . In one embodiment, the first cap layer  120  comprises silicon carbide (SiC), silicon nitride (SiN), or silicon carbon nitride (SiCN). 
         [0009]    Next, with reference to  FIG. 1C , in one embodiment, a dielectric layer  130  is formed on top of the entire structure  100  of  FIG. 1B . In one embodiment, the dielectric layer  130  comprises silicon dioxide. In one embodiment, the dielectric layer  130  is formed by CVD of silicon dioxide on top of the first cap layer  120 . 
         [0010]    Next, with reference to  FIG. 1D , in one embodiment, a bottom electrically conductive layer  140  is formed on top of the entire structure  100  of  FIG. 1C . In one embodiment, the bottom electrically conductive layer  140  is formed by CVD or PVD of an electrically conductive material on top of the dielectric layer  130 . In one embodiment, the bottom electrically conductive layer  140  comprises aluminum (Al), tungsten (W), tantalum nitride (TaN), or any refractory metal/alloy, or any other electrically conductive material. 
         [0011]    Next, with reference to  FIG. 1E , in one embodiment, a dielectric layer  150  is formed on top of the entire structure  100  of  FIG. 1D . In one embodiment, the dielectric layer  150  is formed by CVD of a dielectric material on top of the bottom electrically conductive layer  140 . In one embodiment, the dielectric layer  150  comprises silicon dioxide or a high K dielectric material. 
         [0012]    Next, with reference to  FIG. 1F , in one embodiment, a top electrically conductive layer  160  is formed on top of the entire structure  100  of  FIG. 1E . In one embodiment, the top electrically conductive layer  160  is formed by CVD or PVD of an electrically conductive material on top of the dielectric layer  150 . In one embodiment, the top electrically conductive layer  160  comprises aluminum (Al), tungsten (W), tantalum nitride (TaN), or any refractory metal/alloy, or any other electrically conductive material. It should be noted that the dielectric layer  150  electrically insulates the top electrically conductive layer  160  from the bottom electrically conductive layer  140 . 
         [0013]    Next, in one embodiment, the top electrically conductive layer  160  is patterned resulting in a top plate  162  as shown in  FIG. 1G . More specifically, the patterning process to form the top plate  162  can involve photo-lithography and then RIE (Reactive Ion Etching) etching. In one embodiment, the etching process to form the top plate  162  essentially stops at the dielectric layer  150 . 
         [0014]    Next, with reference to  FIG. 1H , in one embodiment, a second cap layer  170  is formed on top of the entire structure  100  of  FIG. 1G . In one embodiment, the second cap layer  170  is formed by CVD of a dielectric material on top of the entire structure  100  of  FIG. 1G . In one embodiment, the second cap layer  170  comprises silicon carbide (SiC), silicon nitride (SiN), or silicon carbon nitride (SiCN). 
         [0015]    Next, with reference to  FIG. 1I , in one embodiment, a MIM (Metal-Insulator-Metal) cap layer  172 , a MIM dielectric layer  152 , and a MIM bottom plate  142  are created from the second cap layer  170 , the dielectric layer  150 , and the bottom electrically conductive layer  140 , respectively, of  FIG. 1H . Illustratively, the step of forming the MIM cap layer  172 , the MIM dielectric layer  152 , and the MIM bottom plate  142  can involve photo-lithography and then RIE etching. In one embodiment, the etching process to form the MIM cap layer  172 , the MIM dielectric layer  152 , and the MIM bottom plate  142  is performed through the second cap layer  170 , the dielectric layer  150 , and the bottom electrically conductive layer  140 , respectively, of  FIG. 1H , and essentially stops at the dielectric layer  130 . It should be noted that the MIM bottom plate  142 , the MIM dielectric layer  152 , and the top plate  162  (also called a MIM top plate  162 ) can be collectively referred to as a MIM capacitor  142 + 152 + 162 . 
         [0016]    Next, with reference to  FIG. 1J , in one embodiment, a dielectric layer  180  is formed on top of the entire structure  100  of  FIG. 1I . In one embodiment, the dielectric layer  180  is formed by CVD of a dielectric material on top of the entire structure  100  of  FIG. 1I , and then a top surface  180 ′ of the dielectric layer  180  is planarized by, illustratively, a CMP (Chemical Mechanical Polishing) step. In one embodiment, the dielectric layer  180  comprises silicon dioxide. 
         [0017]    Next, with reference to  FIG. 1K , in one embodiment, holes  182   a ,  182   b , and  182   c  are formed in the dielectric layer  180 , the MIM cap layer  172 , and the MIM dielectric layer  152 . Illustratively, the holes  182   a ,  182   b , and  182   c  are formed by using a conventional lithography and etching process. In one embodiment, the etching process to form the hole  182   a  essentially stops at the MIM top plate  162 , and exposes a top surface  162 ′ of the MIM top plate  162  to the surrounding ambient through the hole  182   a . In one embodiment, the etching process to form the hole  182   b  essentially stops at the MIM bottom plate  142 , and exposes a top surface  142 ′ of the MIM bottom plate  142  to the surrounding ambient through the hole  182   b . In one embodiment, the etching process to form the hole  182   c  essentially stops at the metal line  112 , and exposes a top surface  112 ′ of the metal line  112  to the surrounding ambient through the hole  182   c . It should be noted that the holes  182   a  and  182   c  are formed simultaneously because the process to form the holes  182   a  and  182   c  is performed etching through the two materials silicon dioxide and silicon nitride as shown in  FIG. 1K . It should be noted that the etching process to form the holes  182   a ,  182   b , and  182   c  creates residual organic polymers (not shown for simplicity) on side walls and bottom walls of the holes  182   a ,  182   b , and  182   c  and these residual organic polymers are harmful to the final product (not shown). 
         [0018]    Next, with reference to  FIG. 1L , in one embodiment, the residual organic polymers in the holes  182   a ,  182   b , and  182   c  are removed by AZ400T. This removal step is represented by arrows  184  and hereafter is referred to as a removal step  184 . 
         [0019]    AZ400T was originally produced by Clariant. AZ400T is now known under another name “0.175 N Stripper” and can be purchased from Ultra Pure Solutions. In one embodiment, AZ400T is a mixture of (i) 0.175 N tetramethyl ammonium hydroxide (TMAH), (ii) N-Methyl Pyrrolidone (NMP) at about 74% in volume, and (iii) propylene glycol at about 24% in volume. 
         [0020]    In one embodiment, AZ400T being in fluid state is heated to 80° C. and then applied to the side walls and bottom walls of the holes  182   a ,  182   b , and  182   c  at atmospheric pressure so as to remove organic residues there. 
         [0021]    In one embodiment, the MIM bottom plate  142  and the MIM top plate  162  comprise aluminum (Al), tungsten (W), tantalum nitride (TaN), or any refractory metal/alloy, or any other electrically conductive material, whereas the metal line  112  comprises copper (Cu). In this case, AZ400T can be applied to the side walls and bottom walls of the holes  182   a ,  182   b , and  182   c  so as to remove organic residues there without chemically reacting with any of the materials of the metal line  112 , the MIM bottom plate  142 , and the MIM top plate  162 . 
         [0022]    In one embodiment, the metal line  112  comprises copper whereas either the MIM bottom plate  142  or the MIM top plate  162  comprise aluminum. In this case, AZ400T can be applied to the side walls and bottom walls of the holes  182   a ,  182   b , and  182   c  so as to remove organic residues there without chemically reacting with any of the exposed copper and aluminum. 
         [0023]    Next, in one embodiment, the holes  182   a ,  182   b , and  182   c  are filled with an electrically conductive material so as to form vias  186   a ,  186   b , and  186   c , respectively, resulting in the structure  100  of  FIG. 1M . In one embodiment, with reference to  FIGS. 1L and 1M , the vias  186   a ,  186   b , and  186   c  are formed by depositing the electrically conductive material on top of the entire structure  100  of  FIG. 1L  (including in the holes  182   a ,  182   b , and  182   c ), and then polishing by a CMP step to remove excessive material outside the holes  182   a ,  182   b , and  182   c . As a result, the vias  186   a ,  186   b , and  186   c  are electrically coupled to the MIM top plate  162 , the MIM bottom plate  142 , and the metal line  112 , respectively. In one embodiment, the electrically conductive material used to form the vias  186   a ,  186   b , and  186   c  is copper. In one embodiment, before the formation of the vias  186   a ,  186   b , and  186   c , thin diffusion barrier liner layers (not shown) is formed on side walls and bottom walls of the holes  182   a ,  182   b , and  182   c  of  FIG. 1L . In one embodiment, the thin diffusion barrier liner layers comprise tantalum nitride. As a result, the thin diffusion barrier liner layers prevent copper atoms of the vias  186   a ,  186   b , and  186   c  from diffusing into the surrounding dielectric environment (not shown). In an alternative embodiment, the electrically conductive material used to form the vias  186   a ,  186   b , and  186   c  is tungsten (W). In this alternative embodiment, the diffusion barrier liner layers should be made of Ti/TiN. 
         [0024]    Next, additional conventional fabrication steps are performed on the structure  100  of  FIG. 1M  so as to form the final product (not shown). 
         [0025]    In one embodiment, in general, after a plasma etch process, AZ400T is used to remove any resulting residual organic polymers on a wafer (not shown). Moreover, in one embodiment, after a plasma resist strip process, AZ400T is used to remove any resulting residual organic polymers on a wafer (not shown). 
         [0026]    In the embodiments described above, AZ400T is used to remove the residual organic polymers (not shown) on side walls and bottom walls of the holes  182   a ,  182   b , and  182   c  of  FIG. 1L . In general, a basic (non-acidic) photoresist stripping solvent or a solvent containing TMAH can be used to remove the residual organic polymers (not shown) on side walls and bottom walls of the holes  182   a ,  182   b , and  182   c  of  FIG. 1L . 
         [0027]    While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.