Abstract:
Embodiments of the instant invention relate to a system for maintaining the integrity of data transfers in shared memory configuration by different processes to a data buffer located in the contiguous memory locations. The accesses by the different processes can be at the same time. One embodiment employs a CISC CPU, a peripheral using Direct Memory Access (DMA) controller both of which has a 8-bit data bus. The Memory Interface is provided with a sequencer and registers coupled to a Random Access Memory (RAM). The sequencer controls read and write operations of the RAM and ensures atomic transfer of multiple bytes to the RAM by one process invoking a special mode. This ensures that the other processes either read the old set of data or the new set of data with a minimum delay.

Description:
PRIORITY CLAIM  
       [0001]     This application claims priority from Indian patent application No. 1458/Del/2005, filed Jun. 7, 2005, which is incorporated herein by reference.  
       TECHNICAL FIELD  
       [0002]     The present invention relates in general to a system for maintaining the integrity of data transfers in shared memory configurations.  
       BACKGROUND  
       [0003]     Data sharing is an important phenomenon in the day-to-day systems having a number of peripherals connected to a processor. In order to facilitate transfer of data from one peripheral to another the data is routed via the processor or a memory element.  FIG. 1  is a block diagram depicting a system having at least two devices  10  and  11  that share data through a Random Access Memory (RAM)  13 . The device  10  can be a slow communication link that uses a Dynamic Memory Access (DMA) Controller  12  while the device  11  can be a typical Complex Instruction Set Computing (CISC) architecture. The device  10  uses the RAM  13  as a means to share data with the device  11 , as it has no dedicated First-In First-Out (FIFO) for sharing data.  
         [0004]     The first device  10 ,  11  accessing the RAM  13  may release control of the RAM  13  in between while writing bytes into it. In such a situation, if the second device  11 ,  10  reads the shared buffer in the RAM  13 , it will read the buffer which is partially updated. Hence there is a need for a method to protect the atomicity of such shared data, where the term “atomicity” in this context relates to an operation, which in the present example is the writing of bytes in to a shared buffer in the RAM  13 , that must be performed entirely before these bytes are read from the shared buffer. Those skilled in the art will understand the use of the term atomicity in the context of the present invention.  
         [0005]     Conventional FIFO memory interfaces are often used to temporarily store data sequentially that is shared between two or more processes, for e.g. a slow communication link and the CPU as shown in  FIG. 2 . FIFO interfaces are typically employed to accommodate processes that operate asynchronously as described in U.S. Pat. No. 4,151,609.  
         [0006]     The communication link  20  transfers data to the CPU  22  using a FIFO buffer  21 . To quote an example, a sending process in the communications link  20  writes to the buffer  21 , filling the buffer to a particular threshold, and then signals the receiving CPU  22  to read the filled buffer. This significantly increases the waiting time for the processes to read/write if both processes work at different rates. Further, if a process releases the buffer  21  for it to be accessed by any other process before completing the transfer of a set of data, then atomicity of the data is lost as the second process gets access to data that is not updated completely.  
         [0007]     Suppose the CPU  22  is processing data, which consists of multiple bytes, it will take approximately 3 to 6 CPU clock cycles per byte (CISC architecture). Hence to write N bytes it requires N*x (x ranging from 3 to 6 depending on the architecture of the CPU) clock cycles. If in the course of this processing, same data is read by an I2C communications link, a peripheral, using a DMA controller then the atomicity of data read will be lost (i.e. it will read some old bytes and some processed bytes). One method of protecting corruption of shared data would be to disable the DMA during the writing of N bytes, which would result in a waiting time of N*x clock cycles for any DMA requests.  
         [0008]     Based on the foregoing, a need exists for a capability that provides efficient utilization of a shared buffer with atomicity of data maintained between read/write accesses.  
         [0009]     The requirement for an improved architecture is due to the limitations of prior art approaches and the waiting time constraint for processes to access shared memory.  
       SUMMARY  
       [0010]     To obviate the aforesaid drawbacks, an aspect of the instant invention preserves the integrity of data shared between two devices through a memory.  
         [0011]     Another aspect of the instant invention is reducing the waiting time for a device to access data. In one aspect of the invention, the waiting time is reduced to (N−1) CPU cycles while atomicity is maintained.  
         [0012]     According to one aspect of the instant invention, a system for maintaining the integrity of data transfers in shared memory configuration includes a plurality of devices for reading or writing data, a memory interface connected to the plurality of devices, and a shared memory connected to the memory interface for storing the data.  
         [0013]     The memory interface includes arbitration logic for prioritizing the access of the devices to the memory. A control block is connected to the arbitration logic for facilitating the buffering of data while the access of the shared memory is restricted. A plurality of buffers is connected to the control block for temporarily storing data.  
         [0014]     According to one aspect of the present invention, the shared memory is a random access memory.  
         [0015]     The priority of the plurality of devices is decided by the arbitration logic according to another aspect of the present invention.  
         [0016]     A method according to one aspect of the present invention maintains data integrity in memory data transfers in shared memory configurations. The method includes arbitrating the access requests for the data transfers, restricting the access to the shared memory while one device is accessing it, and buffering the data from the restricted device during the restriction period to reduce the waiting time.  
         [0017]     A method according to a further aspect of the present invention maintains data integrity in memory data transfers wherein the buffering further includes configuring a byte count register with the number of bytes to be written in the memory atomically, setting a control bit to enter multi byte control mode writing the data sequentially into an intermediate buffer, and writing the last byte of the data directly to the memory and simultaneously transferring the data from the intermediate buffer to the memory. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     Embodiments of the invention will now be described with reference to the accompanying drawings as follows:  
         [0019]      FIG. 1  shows the block diagram of the prior art.  
         [0020]      FIG. 2  shows the diagram analogous to that of U.S. Pat. No. 4,151,609.  
         [0021]      FIG. 3  shows an architecture in accordance with one embodiment of the invention.  
         [0022]      FIG. 4  shows is a signal timing diagram illustrating the operation of the DMA Controller of  FIG. 3  according to one embodiment of the present invention.  
         [0023]      FIG. 5  shows a state machine used in multiple byte mode of the architecture of  FIG. 3  according to one embodiment of the present invention.  
         [0024]      FIG. 6  is a signal timing diagram illustrating operation of the architecture of  FIG. 3  according to one embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0025]     The following discussion is presented to enable a person skilled in the art to make and use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.  
         [0026]     Embodiments of the present invention relate to a mode by which a set of data can be transferred atomically to a RAM. Since many processes can access this set of data, the mode ensures minimum waiting time for other processes, such that a second process will either receive old data or new data depending on the priorities between the processes.  
         [0027]     The proposed architecture has been designed for an 8-bit CISC micro controller (ST7 family of micro controllers), which shares the same RAM as an I2C communication link. The I2C communications link or peripheral uses a DMA controller for memory transfer between its shift register and the RAM. However, the scope of the invention is not limited to the same. Embodiments of the invention can be extended to all the devices where data sharing is required between two processes while maintaining data atomicity.  
         [0028]      FIG. 3  shows the architecture employed in one embodiment of the invention. It comprises of a peripheral device  30 , a processor  31 , a Memory Interface  33  and a RAM  34 . The Memory Interface  33  consists of a DMA Controller  331  for accessing the Random Access Memory  34 . The CPU  31  accesses the RAM  34  through multiple byte control logic  334  which utilizes buffers  333  when the multiple byte mode is set. The arbitration between DMA Controller  331  and CPU  31  access is done in the arbitration logic  332 . Arbitration logic  332  is utilized to ensure that the DMA Controller  331  is given highest priority over the CPU  31  access except when the CPU  31  enters the “multiple byte mode” and the buffered data is being transferred to RAM  34 . When transferring the data in multi-byte mode, DMA  331  directly writes RAM  34  while the control logic  334  updates RAM  34  with the data from buffers  333 .  
         [0029]     In order to avoid the peripheral  30  from receiving corrupted data, a special mode is created for the CPU  31 . Before entering this mode, the CPU  31  needs to program a byte count register with the number of bytes that need to be written to the RAM  34  atomically. To enter this mode, the CPU  31  sets a control bit in the memory interface  33 . Once this mode is entered, all the bytes are sequentially written to intermediate buffers  333  before writing into the RAM  34 . First N−1 bytes are written in the intermediate buffers, then the last byte is written directly to RAM  34 . Simultaneously N−1 bytes are transferred from the intermediate buffers  333  to RAM  34 . If N bytes are transferred to RAM  34 , then the DMA controller  331  will have a waiting time of (N−1) clock cycles, after which the CPU  31  has finished its access of the RAM  34 .  
         [0030]     The DMA controller  331  in turn should also read such data atomically, that is in a burst mode. Thus a set of data will become atomic when written by one process and also when read by another process.  
         [0031]     The theory underlying this embodiment of the invention is as follows.  
         [0032]     When the CPU  31  writes bytes in the multiple byte mode, the bytes are not written to the RAM  34  but to buffers  333  in the memory interface  33 . The start address is also stored which is the address of the first byte on the address bus.  
         [0033]     After the desired byte count (N−1) is reached, the memory interface  33  transfers all the buffered bytes to the RAM  34  in continuous clock cycles, the first byte at the buffered address and the subsequent bytes sequentially.  
         [0034]     The above may be achieved with the help of a state machine, which gets activated as soon as the multiple bytes control bit is set.  
         [0035]      FIG. 4  is a signal timing diagram showing the operation of the Direct Memory Access DMA Controller  331  according to one embodiment of the present invention. Whenever the DMA Controller  331  needs to access the RAM  34  it checks whether the CPU  31  is accessing the RAM  34 . If the CPU  31  is accessing the RAM  34 , then it stalls the CPU  31  (freezes the CPU state) using a stall signal  44  (specific to ST 7  microcontroller). A signal  40  is the clock at which the CPU  31  and the DMA controller  331  work. A signal  41  is the DMA request for a memory transfer and a signal  42  is a memory write enable signal from the CPU  31 . When a DMA request  41  is made, the stall signal  44  is asserted which freezes the CPU  31  and the DMA controller  331  accesses the RAM  34 . Therefore, the CPU  31  write operation takes place in the next cycle as by signals  45  in  FIG. 4 . A write enable signal ‘ 43 ’ of the RAM  34  is manipulated by the controller  331  accordingly.  
         [0036]     The “multiple byte mode” logic of  FIG. 3  may be realized using a simple state machine as shown in  FIG. 5 . When the state machine is not active, it is in default state ‘IDLE’  50 . It gets activated on setting a control bit “multiple byte mode” in the memory interface  33 . Once this bit is set, the memory interface  33  collects bytes from the process that has set this bit e.g. CPU  31 ; in ‘Wr_buf’  51  state. The number of bytes to be written in the buffers  333  is configured in a configurable byte count register, which can be written only when the multiple byte mode bit is not set. These bytes are written and stored in buffers  333  along with the address of the first byte. In the case of another process having higher priority making a request, the current operation is aborted and control goes to state  50 .  
         [0037]     When a byte counter reaches the value N−1, the nth byte is written directly to the RAM  34  in the ‘Wr_last_RAM’  52  state. Once the last byte is written to the RAM  34 , the remaining (N−1) bytes are written sequentially into the RAM in the ‘Wr_RAM’  53  state, during which any other access to the RAM is not allowed i.e. any DMA is not entertained.  
         [0038]     Once all the buffer  333  contents are transferred to the RAM  34 , the multiple byte mode control bit is reset by hardware and all DMA controller  331  operations are enabled; the state machine returns to IDLE state  50 .  
         [0039]     This embodiment of invention is explained with the help of an example. Suppose in an application the I2C peripheral  30  receives data, which is logical 2 bytes. First byte is received at a time while other byte is transferred to the RAM  34  using DMA Controller  331 . The CPU  31  also processes this 16 bit data, 8 bits at a time. There could be a situation where the I2C peripheral  30  reads the processed bytes in between the two writes of the CPU (spread over 3 to 6 CPU cycles) which would result in the I2C peripheral getting a partially processed data. Referring to  FIG. 6 , using the current invention, for data, which consists of more than one byte, the CPU  31 , working on clock ck  60 , can enter the multiple byte mode after configuring the byte count register to 02H.  
         [0040]     Once the multiple mode bit  66  is set, every write  67  into the buffer  333  decrements the byte count  68 . In the example (N−1) th  byte, i.e. first byte will be written in the data buffer  333  and its address into the address buffer in the memory interface  33 . The second byte will be written directly to the RAM  34  as seen in signal  65 . If the CPU  31  tries to access the RAM  34  during this cycle as shown by the dotted part of  62  then it is stalled as indicated by signal  64 . In the next immediate cycle the interface  33  will transfer the buffered byte to the buffered address. During this cycle all DMA controller  331  accesses  61  will be disabled, hence I2C peripheral  30  will either read old data or completely processed data. The memory interface  33  manipulates the RAM  34  chip select signal  63  accordingly. Thus atomicity of multiple bytes is maintained.  
         [0041]     Embodiments of this invention thus describe a method with the system for an optimal access time while maintaining the atomicity of access for the processes. To achieve the optimal access time, the data to be written is first written in an intermediate buffer (typically by the slow process) before it is updated in the memory.  
         [0042]     Embodiments of the present invention may be used in any type of electronic systems where a multiple devices share or transfer data among one another through a shared memory, such as in computer systems, cellular phones, personal digital assistances, and so on.  
         [0043]     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.