Abstract:
A signal modulation method used for a digital channel of digital recording media and digital communication. The method includes the steps of (a) receiving data in a first data unit of a first bit length and RLL encoding the received data into a (d,k) code word; and (b) receiving data in a second data unit of a second bit length and RLL encoding the received data if a number of consecutive zeroes is less than d when two codes words encoded in said step (a) are concatenated. Therefore, a higher resolution than that of other modulation codes is achieved, for a minimum time interval, 4T (diffraction limit). The DC component of a modulated code can be suppressed by controlling merging bits.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a signal modulation method, and more particularly, to a run length limit (RLL) coding method for enhancing the recording density of digital recording media. 
     2. Description of the Related Art 
     There are various methods for modulating a signal, during the recording and reproduction of the signal used for digital optical recording media and magnetic recording media. Modified frequency modulation (FM) is a representative modulation method. 
     Such modulation methods are used for compact disks, first-generation magneto-optical disks, and second-generation re-recordable optical disks. The optical disk modulation method is either a peak detecting method, for detecting the position of a peak, or an edge detecting method for detecting the edge of a mark. Minimum and maximum time intervals between such peaks or edges are critical characteristic values. They determine the resolution which is related to the recording density of a reproduced signal and a jitter margin, and are expressed as the restriction RLL of the number of continuous `0`s. Other critical variables which determine the recording density are error propagation, whether the number of input bits is variable, and the ratio of the number of input bits to the number of output bits, namely, the conversion ratio. 
     RLL (2,7) is a conventional modulation method used for first-generation magneto-optical disks. It has a relatively small jitter margin to be used for the edge detecting method. RLL (1,7) is a method obtained by improving the conventional modulation method. With this method, a large jitter margin can be secured by reducing the size of the minimum mark, and by improving a capacity and the size of a window by 33%. However, the RLL (1,7) modulation method has a problem in that the recording density is relatively low for a given resolution, in the case of optical recording, in which the minimum time interval is 2T and 3T (the diffraction limit). 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a signal modulation method for enhancing the recording density of digital recording media. 
     To achieve the above object, there is provided a signal modulation method comprising the steps of (a) receiving data in a first data unit of a first bit length and RLL encoding the received data into a (d,k) code word; and (b) receiving data in a second data unit of a second bit length and RLL encoding the received data if a number of consecutive zeroes is less than d when two codes words encoded in the step (a) are concatenated. The variable d denotes the minimum number of `0`s between two `1`s in a sequence and k denotes the maximum number of `0`s between two `1`s in a sequence. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The above and other objects and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawing in which: 
     FIGURE is a flow chart for explaining a signal modulation method according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention employs an RLL (3,15) coding method in which the number of consecutive `0`s is limited from 3 to 15. 
     Also, the signal modulation method of the present embodiment includes two coding schemes: a main conversion coding and a sub-conversion coding. 
     In the main coding scheme, input data bits are received in 3-bit units to yield 7-bit coded sequences (code words). On the other hand, in the sub-coding scheme, input data bits are received in 6-bit units to yield 14-bit coded sequences. 
     The code book used in the main coding scheme and the sub-coding scheme of the present embodiment is given in table 1. 
     
                       TABLE 1______________________________________code book for main codinginput bits     output bits______________________________________000       1000000001       0100000010       0010000011       0001000100       0000100101       0000010110       1000100111       1000010______________________________________                merging bit(s)code book for sub-coding                determination______________________________________100 000   0000000 1000XXX100 110   0000001 0000XXX                    X = 0 or 1100 111   0000001 0001000                    XX = 00, 01 or 10101 000   0000000 01000XX                    XXX = 000, 001, 010101 001   0000000 001000X                    or 100101 110   0010001 0001000101 111   0010001 0000XXX                    * X is110 000   0100001 0001000                    merging bit(s)110 110   0100001 0000XXX110 111   0100010 0001000111 000   0100010 0000XXX111 001   0100010 001000X111 110   1000001 0001000111 111   1000001 0000XXX______________________________________ 
    
     In the table 1, `X` denotes a merging bit. 
     Referring to the FIGURE, data is input to an encoder in a 3-bit unit in the present embodiment (step 100). Thus, the input data bits are one of `000`, `001`, `010`, `011`, `100`, `101`, `110` and `111`. 
     The input data is RLL encoded into (3,15) code of length 7 according to the main coding scheme (step 110). 
     That is, when the input bits are `000`, the output bits are `1000000`. When the input bits are `001`, the output bits are `0100000`. When the input bits are `010`, the output bits are `0010000`. When the input bits are `011`, the output bits are `0001000`. When the input bits are `100`, the output bits are `0000100`. When the input bits are `101`, the output bits are `0000010`. When the input bits are `110`, the output bits are `1000100`. When the input bits are `111`, the output bits are `11000010`. 
     After the 3-bit units (code words) are encoded in such a manner, the next input data bits are received and RLL encoded. Subsequently, the two encoded code words are concatenated. 
     Afterwards, it is determined whether the number of consecutive &#34;0&#34;s in the concatenated bit sequence is less than the lower limit 3 (step 120). 
     If it is determined in the step 120 that the number of consecutive &#34;0&#34;s in the concatenated bit sequence is equal to or greater than the lower limit 3, the encoding process for the first input data bits is completed. 
     On the other hand, if it is determined in the step 120 that the number of consecutive &#34;0&#34;s in the concatenated bit sequence is less than the lower limit 3, the code words for the two 3-bit input data words are invalidated. Also, the two 3-bit input data words are concatenated to be encoded in a 6-bit unit (step 130). 
     In this embodiment, there are fourteen cases in which the number of consecutive &#34;0&#34;s in the concatenated coded word, which is the result after performance of the main coding scheme and subsequent concatenation of the two resultant 7-bit code words, is less than the lower limit 3. That is, 6-bit data to be encoded as one unit may be `100000`, `100110`, `100111`, `101000`, `101001`, `101110`, `101111`, `110000`, `110110`, `110111`, `111000`, `111001`, `111110`, or `111111`. 
     The 6-bit data is RLL encoded into a (3,15) code of length 14 according to the sub-coding scheme (step 140). 
     That is, when the input bits are `100000`, the output bits are `0000000 1000XXX`. When the input bits are `100110`, the output bits are `0000001 0000XXX`. When the input bits are `100111`, the output bits are `0000001 0001000`. When the input bits are `101000`, the output bits are `0000000 01000XX`. When the input bits are `101001`, the output bits are `0000000 001000X`. When the input bits are `101110`, the output bits are `0010001 0001000`. When the input bits are `101111`, the output bits are `0010001 0000XXX`. When the input bits are `110000`, the output bits are `0100001 0001000`. When the input bits are `110110`, the output bits are `0100001 0000XXX`. When the input bits are `110111`, the output bits are `0100010 0001000`. When the input bits are `111000`, the output bits are `0100010 0000XXX`. When the input bits are `111001`, the output bits are `0100010 0010000X`. When the input bits are `111110`, the output bits are `1000001 0001000`. When the input bits are `111111`, the output bits are `1000001 0000XXX`. 
     When the encoding of the step 140 is done, the encoding of the next 3- or 6-bit input data bits are carried out, and then the merging bit(s) X are determined. 
     Next, the methods for determining the merging bit(s)(X) in the sub-coding scheme are described. 
     The simplest method is to set all the merging bits to zeroes. That is, X, XX and XXX are &#34;0&#34;,&#34;00&#34; and &#34;000&#34;, respectively. However, according to such a method, the requirements on the number of consecutive &#34;0&#34;s may not be satisfied. 
     One of the methods which is simple while satisfying the requirements on the number of consecutive &#34;0&#34;s is as follows: 
     
         ______________________________________X = 0        if a next code word starts with 100, 010        or 0011            OtherwiseXX = 00      if a next code word starts with 10 or 0110           OtherwiseXXX = 000    if a next code word starts with 1100          Otherwise______________________________________ 
    
     In other words, the merging bit X is &#34;0&#34; when a next code word starts with `100`, `010` or `001` and &#34;1&#34; when the next code word does not start with `100`, `010` or `001`. The merging bits XX are &#34;00&#34; when the next code word starts with `10` or `01` and &#34;0&#34; when the next code word does not start with `10` or `01`. Also, the merging bits XXX are &#34;000&#34; when the next code word starts with `1` and &#34;100&#34; when the next code word does not start with `1`. 
     However, according to this second method, a DC content in the modulated signal may be large, which is not desirable considering the frequency response characteristics of the readback system. 
     A third merging bit determination method which can reduce the DC content in the modulated signal is as follows. The merging bit is determined as &#34;0&#34; or &#34;1&#34;, the merging bits XX as &#34;00&#34;, &#34;01&#34; or &#34;10&#34;, and the merging bits XXX as &#34;000&#34;, &#34;001&#34;, &#34;010&#34; or &#34;100&#34;, when the number of consecutive `0`s in the concatenated code word sequence does not exceed 15. 
     Now, an example of signal modulation according to the embodiment of the present invention is described, in which the third merging bit determining method is employed. It is assumed that the input data bits are `100 111 010 101 111 000 111 111 011 111 111 010 101 000 001 100`. Then, the input data bits are encoded as follows: 
     
         __________________________________________________________________________INPUT100 111  010      101 111OUTPUT00000010001000         0010000  00100010000XXXINPUT000      111 111  011      111 111OUTPUT1000000  10000010000XXX                  0001000  10000010000XXXINPUT010      101 000  001 100OUTPUT0010000  000000001000XX                  0100000 0000100__________________________________________________________________________ 
    
     First, two 3-bit input data words `100` and `111` are encoded into &#34;0000100,&#34; respectively, according to the main coding scheme. Subsequently, the two code words are concatenated to become &#34;0000100 1000010.&#34; Since there are only two &#34;0&#34;s between two &#34;1&#34;s in the fifth and the eighth digit, the code words for the two 3-bit input data words are invalidated. Then, a 6-bit input word `100 111` which results from the concatenation of `100` and `111` is encoded into &#34;00000010001000&#34; according to the sub-coding scheme. The code word is accepted because the restriction on the number of &#34;0&#34;s is not violated and there is no possibility that the restriction is violated when the code word is concatenated with a following code word. 
     Afterwards, the following 3-bit input data words `010` and `101` are encoded into &#34;0010000&#34; and &#34;0000010&#34; according to the main coding scheme. The code word for the input data word `010` is accepted because the restriction on the number of &#34;0&#34;s is not violated when the two code words are concatenated. 
     Again, the following 3-bit input data words `101` and `111` are encoded into &#34;0000010&#34; and &#34;1000010,&#34; respectively, according to the main coding scheme. The code words for the two 3-bit input words are discarded because the restriction on the number of &#34;0&#34;s is violated when the two code words are concatenated. Then, a 6-bit input word `101 111` which results from the concatenation of `101` and `111` is encoded into &#34;00100010000XXX&#34; according to the sub-coding scheme. The code word is accepted because the restriction on the number of &#34;0&#34;s is not violated. However, since there is a possibility that the restriction is violated when the code word is concatenated with a following code word, the code word shall be in a state of pending to fix the merging bits later. 
     Once again, the following 3-bit input data words `000` and `111` are encoded into &#34;1000000&#34; and &#34;1000010,&#34; respectively, according to the main coding scheme. The code word for the input data word `000` is accepted because the restriction on the number of &#34;0&#34;s is not violated when the two code words are concatenated. At this time, the merging bits which are pending are fixed such that restriction on the number of &#34;0&#34;s is not violated. In such a manner, all the input data words are encoded. 
     Next, how the coded bit sequence is decoded will now be described. In this example, the coded bit sequence which resulted from the encoding example is used in order to verify the logical coincidence of the present invention. 
     Thus, it is assumed that the input bit sequence at a decoder is &#34;00000010001000 0010000 00100010000XXX 1000000 10000010000XXX 0001000 10000010000XXX 0010000 000000001000XX 0100000 0000100.&#34; Then, the input bit sequence is decoded as follows: 
     
         __________________________________________________________________________INPUT00000010001000         0010000  00100010000XXXOUTPUT100 111  010      101 111INPUT1000000  10000010000XXX                  0001000  10000010000XXXOUTPUT000      111 111  011      111 111INPUT0010000  000000001000XX                  0100000  0000100OUTPUT010      101 000  011      100__________________________________________________________________________ 
    
     First, the decoding of a first seven bits of the encoded bit sequence &#34;0000001&#34; is attempted. However, since the code book for the main coding scheme does not include the code word, an attempt is made to decode a first fourteen bits of the encoded bit sequence &#34;00000010001000.&#34; Thus, the code word is decoded into `100 111` according to the sub-coding scheme. 
     Afterwards, an attempt is made to decode another seven bits of the encoded bit sequence &#34;0010000.&#34; Since the code book for the main coding scheme includes the code word &#34;0010000,&#34; the code word is decoded into &#34;010.&#34; 
     In such a manner, all the encoded bit sequences are decoded into original data. 
     Table 2 shows the result of an encoding simulation which was carried out by the inventor, in which arbitrary input data bits numbering about 12,360 bits were modulated. In the table, the time interval (TI) distribution of the modulation codes is shown. 
     
                       TABLE 2______________________________________                  totalrunlength (RL)    time interval (TI)                  occurrences                            probability______________________________________3         4            8923      0.25324         5            6611      0.18765         6            5040      0.14306         7            4472      0.12697         8            2980      0.08468         9            2350      0.06679        10            1660      0.047110       11            1448      0.041111       12             812      0.023012       13             389      0.011013       14             241      0.006814       15             162      0.004615       16             146      0.0041total              35234     1.0000______________________________________ 
    
     It is noted that the distribution probability is low, from the fact that the distribution of the minimum time interval is about 25%. 
     In the above-mentioned signal modulation method, a resolution which is higher than that of other modulation codes is provided, for optical recording in which the minimum time interval is 4T (the diffraction limit.) Accordingly, information density is high and demodulation is easy.