Abstract:
A squaring cell comprises a first circuit responsive to an input voltage to produce a corresponding current, and a second circuit, preferably in the form of an absolute modulator circuit, responsive to the current produced by the first circuit and to the input voltage to produce an output current that corresponds to the square of the input voltage. In one embodiment, the first circuit comprises an absolute value voltage-to-current converter; in another, the first circuit comprises a linear voltage-to-current converter. Techniques to improve accurate square law performance of the cell, independent of temperature, and of broad input voltage range and frequency, are presented.

Description:
TECHNICAL FIELD  
       [0001]     The disclosure is directed to a novel circuit architecture for producing an output signal corresponding accurately to the square of an input signal.  
       BACKGROUND INFORMATION  
       [0002]     Circuitry for squaring an input signal has a number of practical applications, among which are included logarithmic amplifiers and RMS-DC converters implementing them. Such amplifiers often are applied to systems for measuring the power of an RF signal. Doing so capably requires an amplifier exhibiting true square law conformability over a broad dynamic range and being relatively independent of temperature. The subject matter presented herein presents novel circuitry for achieving these characteristics.  
       SUMMARY OF DISCLOSURE  
       [0003]     Presented herein is a squaring cell which comprises a first circuit responsive to an input voltage to produce a corresponding current, and a second circuit responsive to the current produced by the first circuit and to the input voltage to produce an output current that corresponds to the square of the input voltage. The second circuit may comprise an absolute value modulator circuit, and the first circuit may comprise an absolute value, or alternatively, linear, voltage-to-current converter. The circuitry advantageously is composed of bipolar transistors in differential pair configuration, in which tail current is proportional to the square of absolute temperature. Resistors may be implemented to achieve a high effective transistor area ratio while maintaining reasonable transistor size for high frequency operation, and to precisely achieve an accurate square law characteristic.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]      FIG. 1  is a simplified diagram showing squaring cell implementation, in accord with one embodiment of the disclosure.  
         [0005]      FIG. 2  shows a more detailed circuit diagram corresponding to  FIG. 1 .  
         [0006]      FIG. 3  is a simplified diagram showing square cell implementation, in accord with one embodiment of the disclosure.  
         [0007]      FIG. 4  shows a more detailed circuit diagram corresponding to  FIG. 3 .  
         [0008]     FIGS.  5 ( a ) and  5 ( b ) are charts representing characteristics of output signals from the squaring cell, obtained by simulation. 
     
    
     DETAILED DESCRIPTION  
       [0009]     In accord with the principles presented herein, a novel squaring circuit or cell is implemented by a circuit  100 , one embodiment of which is presented functionally in  FIG. 1 , in which the voltage input signal to be squared is applied to voltage inputs of an absolute value voltage and current modulator  102  and of an absolute value voltage-to-current converter  104 . The converter  104  applies a current proportional to the input voltage to a current input of the modulator  102 . In response to the applied voltage and current inputs, the modulator produces an output current that is proportional to the square of the input voltage.  
         [0010]     As will be described, modulator  102  and converter  104  are implemented using bipolar transistors, which inherently present an exponential transconductance characteristic in response to small magnitude input signals of a prescribed polarity depending on the gender of the transistor. In the examples to be described, the transistors are npn type, base driven to an active region in response to an applied positive voltage greater than the transistor&#39;s thermal voltage (about 23 mv.). The circuitry described herein, of course, may be implemented with transistors of either gender. Modulator  102  is configured to be responsive to bipolar input voltage and current signals in such a manner as to generate an output current that is a function of the absolute value of the input voltage to produce the desired squaring signal.  
         [0011]     Referring now to  FIG. 1  in more detail, input voltage Vin is applied commonly to voltage input nodes of modulator  102  and converter  104 . Converter  104  supplies its output current Ix, which is proportional to |Vin|, to an input current node of modulator  102  as depicted. Modulator  102  is responsive to both the absolute value of input voltage and input current applied to it to produce an output current Iout that corresponds to the square of the input voltage.  
         [0012]     This operation can be quantified by the following equations: 
 
 Ix=a*|V in|  (1) 
 
 where a is the coefficient of V-to-I converter  104 , and 
 
 I out= b*|V in|* Ix   (2) 
 
 where b is the coefficient of voltage and current modulator  102 . Combining Equation 1 and Equation 2, Iout can be rewritten as follows: 
 
 I out= a*b*|V in|* Ix=c*V in 2   (3) 
 
         [0013]     Hence, the output current produced by modulator  102  is proportional to the square of the input voltage.  
         [0014]     The principles of this disclosure may be better understood upon consideration of an exemplary circuit implementation of the  FIG. 1  architecture, presented in  FIG. 2 . Referring to  FIG. 2 , converter  104  comprises bipolar transistors Q 1 -Q 4 , interconnected as shown, with the base electrodes of transistors Q 1  and Q 2  commonly receiving the positive-going component Vxp buffered from input voltage signal Vinp through an emitter follower Q 9 . Transistor Q 9 , which is connected between the positive and negative rails, has an emitter constant current source Ie. The emitters of transistors Q 1  and Q 3  are connected commonly through a constant current source Is to the ground rail. The collector of transistor Q 1  is connected to supply output current component Ixp to modulator  102 .  
         [0015]     Similarly, the base electrodes of transistors Q 3  and Q 4  commonly receive the negative-going component Vxn buffered from input voltage signal Vinn through emitter-follower transistor Q 10 . Transistor Q 10  is connected between the rails and another emitter constant current source Ie. The voltages Vxn and Vxp, applied to converter  104  are equal in magnitude to those of the input voltages Vinn and Vinp, reduced by the DC level shifter by transistors Q 9  and Q 10 .  
         [0016]     The emitters of transistors Q 2  and Q 4  are connected commonly to the negative rail through constant current source Is. The collectors of transistors Q 2  and Q 3  are connected commonly to the positive rail. The collectors of transistor Q 1  and Q 4  are connected to supply output current components Ixp and Ixn respectively to modulator  102 . These current components are proportional to the magnitudes of input voltages Vinp and Vinn together with quiescent DC current supplied by transistors Q 2  and Q 3 . Current through the two sources Is is shared by transistors Q 1 , Q 2  and Q 3 , Q 4 , respectively.  
         [0017]     Modulator  102  comprises transistors Q 5 -Q 8 , interconnected as shown. Transistors Q 5  and Q 6  have emitters connected commonly to node Ixp, and collectors connected to the Iout node and positive rail, respectively. Transistors Q 7  and Q 8  correspondingly have emitters connected commonly to node Ixn and collectors connected to the positive rail and Iout node, respectively. The modulator  102  receives the positive and negative components Vinp, Vinn of the input voltage at the bases of transistors Q 5 , Q 7  and Q 6 , A 8 . Current Ixp conducted by transistor Q 1  is shared through transistors Q 5  and Q 6  in proportion to the size ratio of those transistors. Correspondingly, current Ixn, conducted by transistor Q 4  of converter  104  is shared through transistors Q 7  and Q 8  proportionally according to transistor ratio. The collectors of Q 5  and Q 8  are interconnected at output node Iout. The significance of this 1:A size ratio among transistors Q 1 -Q 8  in  FIG. 2  will now be explained.  
         [0018]     By the “size” of a transistor is meant the effective emitter area of that transistor. The significance of transistor size can be appreciated by a recognition that each transistor of a like pair of transistors receiving the same bias conditions will conduct a current proportional to its size. That is, one transistor of a pair whose size (emitter area) is twice that of the other transistor of the pair will conduct twice the current, assuming the same biasing.  
         [0019]     Considering the circuit of  FIG. 2 , transistors Q 1 , Q 4 , Q 5  and Q 8  are shown to be normalized arithmetically to have a size of unity; transistors Q 2 , Q 3 , Q 6  and Q 7  are sized to be of ratio A (where A is a ratio greater than unity). Transistors Q 2 , Q 3 , Q 6  and Q 7  will conduct more current than transistors Q 1 , Q 4 , Q 5  and Q 8  by ratio A, when commonly biased.  
         [0020]     The following equations describing the circuit of  FIG. 2  can now be written, where Is is transistor saturation current, Vt is transistor thermal voltage, A is transistor ratio as explained, and Vxp, Vxn, Vinp and Vinn are as presented in the circuit diagram:  
                 Ixp   -     Iss   *     1     1   +     A   *     ⅇ       (     Vxp   -   Vxn     )     /   Vt                 =     Iss   *     1     1   +     A   *     ⅇ       (     Vinp   -   Vinn     )     /   Vt                 ;           (   4   )                 Ixn   =       Iss   *     1     1   +     A   *     ⅇ       -     (     Vxp   -   Vxn     )       /   Vt               =     Iss   *     1     1   +     A   *     ⅇ       -     (     Vinp   -   Vinn     )       /   Vt                   ;           (   5   )             
 
 Ix in  FIG. 1  can be considered to be the sum of Ixp and Ixn in  FIG. 2 , so that:  
             Ix   =       Ixp   +   Ixn     ==     Iss   (                   ⁢       1             ⁢     1   +     A   *     ⅇ       (     Vinp   -   Vinn     )     /   Vt               +                 1             ⁢     1   +     A   *     ⅇ       -     (     Vinp   -   Vinn     )       /   Vt                     )               (   6   )             
 
 which can be transformed to show that Ix≈small dc quiescent current+a*|Vin|
 
         [0021]     When Vin&gt;0 (Vin=Vinp−Vinn=Vxp−Vxn), transistor Q 5  starts to conduct current. The modulator  102  generates an output current through transistor Q 5 , proportional to the input voltage Vin, and very little current through transistor Q 8 . When Vin&lt;0 (Vin=Vinp−Vinn=Vxp−Vxn), transistor Q 8  starts to conduct current. The modulator  102  now generates output current through transistor Q 8 , proportional to the input voltage Vin and very little through transistor Q 5 . This sharing of output current varies continuously in dependence upon the polarity and magnitude of the input voltage.  
         [0022]     Transistors Q 5  and Q 7  are operative in a manner complimentary to Q 5  and Q 8  so as to supply Ixp and Ixn, respectively. Transistors Q 6  and Q 7 , being of ratio A, conduct more current than transistors Q 5  and Q 8 . The sum of the controlled collector currents of transistors Q 5  and Q 8 , supplied by the output of voltage-to-current converter  104 , forms the output current of the modulator  102 . This output corresponds to the square of the input voltage Vin. Similarly, with respect to converter  104 , transistors Q 2  and Q 3 , which are connected to be complimentary to transistors Q 1 , Q 4 , and being of transistor ratio A, supply the quiescent current. The foregoing can be quantified as follows:  
                     Ic   ⁢           ⁢   5     =     Ixp   *     1             ⁢     1   +     A   *     ⅇ       (     Vinp   -   Vinn     )     /   Vt                             =     Iss   *     1     1   +     A   *     ⅇ       (     Vxp   -   Vxn     )     /   Vt             *     1             ⁢     1   +     A   *     ⅇ       (     Vinp   -   Vinn     )     /   Vt                               =     Iss   *       {     1             ⁢     1   +     A   *     ⅇ       (     Vinp   -   Vinn     )     /   Vt               }     2         ;                 (   7   )                       Ic   ⁢           ⁢   8     =     Ixn   *     1             ⁢     1   +     A   *     ⅇ       -     (     Vinp   -   Vinn     )       /   Vt                               =     Iss   *       {           ⁢     1             ⁢     1   +     A   *     ⅇ       -     (     Vinp   ⁢           -           ⁢   Vinn     )       /   Vt               }     2         ;                 (   8   )                     Iout   =       Ic   ⁢           ⁢   5     +     Ic   ⁢           ⁢   8                   =       Iss   *       {     1             ⁢     1   +     A   *     ⅇ       (     Vinp   -   Vinn     )     /   Vt               }     2       +                 =     Iss   *       {     1             ⁢     1   +     A   *     ⅇ       -     (     Vinp   -   Vinn     )       /   Vt               }     2                     (   9   )             
 
 By way of example, let A=10, x=(Vinp−Vinn)/Vt, then the power series expansion can be written as follows: 
 
 I out= Iss *(2/121+380/14641 *x   2   +O ( x   4 )  (10) 
 
 where O(x 4 ) represents small magnitude higher order terms, that can be ignored. 
 
         [0023]     In the circuit implementation of  FIG. 2  both voltage-to-current converter  104  and voltage and current modulator  102  as described are absolute value circuits. The output current Iout is seen to conform precisely to the square law relationship described in equation (3), that is, Iout fits x well when x&lt;1. In other words, Iout is linearly proportional to the square of the input voltage up to Vt.  
         [0024]     A second embodiment in which absolute value V-to-I converter  104  is replaced by a linear V-to-I converter  106  is depicted in  FIG. 3 , and a circuit implementation shown in  FIG. 4 . Transistors Q 5 -Q 8  of absolute voltage and current modulator  102  are configured to operate similarly to the configuration shown in  FIG. 2 , and description will not be repeated. Linear voltage-to-current converter  106  comprises transistors Q 1 -Q 4 , interconnected as shown. The bases of transistors Q 1  and Q 2  are connected commonly to receive Vinp through emitter followers Q 9  and Q 11 . The bases of transistors Q 3  and Q 4  are connected commonly to receive Vinn through emitter followers Q 10  and Q 12 . The emitters of transistors Q 1  and Q 3  are connected commonly to a current source proportional to the square of absolute temperature Iptat**2 which passes current proportional to square of absolute temperature. The emitters of transistors Q 2  and Q 4  are connected commonly to a like current source Iptat**2. Emitter followers Q 11  and Q 12  are connected between the positive and negative rails, the emitter circuit of each having a constant current source Ie 2 . Emitter followers Q 9  and Q 10  are configured similarly, the emitter circuit of each having a resistor Rs and a constant current source Ie 1 . Current sources Ie 1  and Ie 2  in the emitter circuits of followers Q 11  and Q 12 , respectively, are zero temperature coefficient current sources. Tail currents I 1  and I 2  are proportional to the square of absolute temperature. Tail currents produced as described are necessary to cause the output current of the multiplier to be independent of temperature. Resistors Re are in the emitter circuits of transistors Q 1 , Q 4 , Q 5  and Q 7 . The functions of resistors Re and Rs will be explained hereinafter.  
         [0025]     The collectors of transistors Q 2  and Q 3  may be joined to Ixp and Ixn, respectively. As a result, the output current will be doubled for a given Vin. However, this would result in a quiescent current Iq as a component of Ixp and Ixn.  
         [0026]     The foregoing can better understood from the following mathematical description 
 
 Ixp= 2 a*V in+ Iq; and   (11) 
 
 Ixn=− 2 a*V in+ Iq;   (12) 
 
 where a is the coefficient of the V-to-I converter. 
 
 Ic 5 =b*V in *Ixp  if Vin&gt;0  (13) 
 
 Ic 8 =−b*V in *Ixn  if Vin&lt;0  (14) 
 
 By combination of (11) and (12): 
 
 I out= Ic 5 +Ic 8=4 *a*b*V   in   2= 4 *c*V   in   2   (15) 
 
         [0027]     To conform to the square law relationship over a wide range of input signal magnitudes in  FIG. 4 , the collectors of transistors Q 2  and Q 3  are connected to the emitters of transistor pairs Q 5 , Q 6  and Q 8 , Q 3 , respectively. A resistor Re is applied to each of the emitter circuits of transistors Q 1 , Q 4 , Q 5  and Q 7 , sized to fit square law operation of the circuit more precisely  
         [0028]     To minimize DC quiescent current and conform to the square law relationship, a high transistor ratio A is desirable. However, this may result in degraded high frequency performance. Accordingly, resistor Rs is added in the emitter circuits of Q 9  and Q 10  to achieve a desirable transistor effective area ratio while maintaining reasonable size A for high frequency operation. This may be better understood from the following.  
         [0029]     In general, for a transistor of size A: 
 
 Vbe=Vt *ln( Ic/A*Is ),  (16) 
 
 where Is is saturation current. This expression can be rewritten as: 
 
 Vt *ln( Ic/Is )− Vt *ln( A ).  (17) 
 
         [0030]     The second term is an offset voltage proportional to Vt. Thus, a transistor having an emitter resistor Rs, implemented as shown, is equivalent to a transistor of unity size (normalized) plus an offset voltage which can be introduced by the product of offset current and Rs. The constant current sources Ie 1  and Ie 2  in the emitter circuits of transistors Q 9  and Q 10  are zero temperature coefficient current sources to cause the DC offset to be independent of temperature. This will partially compensate the output conformance to square law verses temperature for a relatively large input voltage.  
         [0031]     FIGS.  5 ( a ) and  5 ( b ) show how the current output of the multiplier described herein conforms to ideal squaring law performance. In  FIG. 5 ( a ), shows deviation of the output current from what is an ideal squaring function, demonstrating a nearly perfect square within a particular range of input voltages (100 mv. in this example).  FIG. 5 ( b ) shows the actual output current as a function of input voltage, in relation to the same example. In this disclosure there are shown and described only preferred embodiments of the invention and but a few examples of its versatility. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.