Abstract:
Method and system for checking frame-length in a Fiber Channel frames is provided. The method includes extracting a R_CTL value from a Fiber Channel frame; comparing the extracted R_CTL value of the Fiber Channel frame with R_CTL values stored in a Content Addressable Memory Table; determining a maximum frame-length and a minimum frame-length of the Fiber Channel frame for the extracted R_CTL value from the Content Addressable Memory Table; and marking the Fiber Channel frame so that it can be discarded if the frame-length is less than the minimum frame-length of the Fiber Channel frame or greater than the maximum frame-length of the Fiber Channel frame. The system includes a processor that accesses a CAM stored in memory; and a receive port that extracts and compares a R_CTL value of the Fiber Channel frame.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This patent application is related to the following US Patent Applications: 
   Ser. No. 10/894,627 filed on Jul. 20, 2004, entitled “Method and System for Programmable Data Dependent Network Routing”; and 
   Ser. No. 10/894,547, filed on Jul. 20, 2004, entitled “Method and System for Using Extended Fabric Features with Fibre Channel Switch Elements”; the disclosure of the foregoing applications is incorporated herein by reference in their entirety. 
   BACKGROUND 
   1. Field of the Invention 
   The present invention relates to Fibre Channel network systems, and more particularly, to checking frame-length in Fibre Channel frames. 
   2. Background of the Invention 
   Fibre Channel is a set of American National Standard Institute (ANSI) standards, which provide a serial transmission protocol for storage and network protocols such as HIPPI, SCSI, IP, ATM and others. Fibre Channel provides an input/output interface to meet the requirements of both channel and network users. 
   Fibre Channel supports three different topologies: point-to-point, arbitrated loop and Fibre Channel fabric. The point-to-point topology attaches two devices directly. The arbitrated loop topology attaches devices in a loop. The Fibre Channel fabric topology attaches host systems directly to a fabric, which are then connected to multiple devices. The Fibre Channel fabric topology allows several media types to be interconnected. 
   Fibre Channel fabric devices include a node port or “N_Port” that manages fabric connections. The N_port establishes a connection to a fabric element (e.g., a switch) having a fabric port or “F_port”. 
   A Fibre Channel switch is a multi-port device where each port manages a point-to-point connection between itself and its attached system. Each port can be attached to a server, peripheral, I/O subsystem, bridge, hub, router, or even another switch. A switch receives messages from one port and routes it to another port. 
   Fibre Channel frames carry information between Fibre Channel Devices which include Host Bus Adapters, Switches and Disk Drives. The components of a Fibre Channel Frame include SOF, Frame Header, Payload, CRC and EOF. Typically, the minimum frame-length of a Fibre frame is 36 bytes and the maximum frame-length of a Fibre Channel frame is 2148 bytes. 
   Typically, a Fibre Channel device receives an incoming Fibre Channel frame when it detects a Start-Of-Frame (SOF) delimiter. The receive port detects an end of the Fibre Channel frame when it detects an End-Of-Frame (EOF) delimiter or if the maximum frame-length is reached. The receive port of the Fibre Channel device keeps a count of the frame-length of the Fibre Channel frame. The frame-length includes the summation of the length of SOF (4 bytes), Frame Header (24 bytes), Payload (0-2112 bytes), CRC (4 bytes) and EOF (4 bytes). The receive port then determines if the frame-length of the received Fibre Channel frame is within the minimum and maximum frame-length as specified in the Fibre Channel specification. If a violation of the frame-length occurs, then the frame is discarded and an error is reported to a processor. 
   With the addition of new routing features for example, Virtual Fabric and Inter-Fabric routing, the length of the Frame Header has changed. This addition caused the total frame-length of the Fibre Channel frame to be different than the current maximum and minimum frame-length. When a switch that was designed before these features were introduced receives a Fibre Channel frame, data is corrupted if the EOF is not detected due to the varying lengths of the frame. Furthermore, the current frame-length checking mechanism causes erroneous errors. Therefore, there is a need for a method and system for efficiently checking the frame-length of a Fibre Channel frame with varying frame lengths. 
   SUMMARY OF THE INVENTION 
   In one aspect of the present invention, a method for checking frame-length in a Fibre Channel frames is provided. The method includes extracting a R_CTL value from a Fibre Channel frame; comparing the extracted R_CTL value of the Fibre Channel frame with R_CTL values stored in a Content Addressable Memory Table; determining a maximum frame-length and minimum frame-length of the Fibre Channel frame for the extracted R_CTL value from the Content Addressable Memory Table; and marking the Fibre Channel frame so that it can be discarded, if the frame-length is less than the minimum frame-length of the Fibre Channel frame or greater than the maximum frame-length of the Fibre Channel frame. 
   This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof concerning the attached drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures: 
       FIG. 1A  shows an example of a network system used according to one aspect of the present invention; 
       FIG. 1B  shows an example of a Fibre Channel switch element, according to one aspect of the present invention; 
       FIG. 1C  shows a block diagram of a 20-channel switch chassis, according to one aspect of the present invention; 
       FIG. 1D  shows a block diagram of a Fibre Channel switch element with sixteen GL_Ports and four 10 G ports, according to one aspect of the present invention; 
     FIG.  1 E- 1 / 1 E- 2  shows a top-level block diagram of a switch element used according to one aspect of the present invention; 
       FIG. 1F  shows a block diagram of a receive port using a Frame Control Module and a CAM Table, according to one aspect of the present invention; 
       FIG. 1G  shows a block diagram illustrating Virtual SANs, used according to one aspect of the present invention; 
       FIG. 1H  shows the Inter-Fabric structure that uses an extended frame header, processed according to one aspect of the present invention; 
       FIG. 2A  shows a standard Fibre Channel Frame, used according to one aspect of the present invention; 
       FIG. 2B  shows an extended Fibre Channel frame processed according to one aspect of the present invention; 
       FIG. 2C  shows a top-level flow chart for processing Fibre Channel frames, according to one aspect of the present invention; 
       FIG. 3A  shows an example of a Content Addressable Memory Table that maintains R_CTL, maximum frame-length and minimum frame-length information, according to one aspect of the present invention; and 
       FIG. 3B  shows a logic diagram for a port level CAM Table, according to one aspect of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Definitions: 
   The following definitions are provided for convenience as they are typically (but not exclusively) used in the Fibre Channel environment, implementing the various adaptive aspects of the present invention. 
   “CRC” (cyclic redundancy code): A 4 byte value used for checking the data integrity of a Fibre Channel frame. 
   “D_ID”: A 24-bit Fibre Channel header field that contains the destination address for a frame. 
   “Dword: A 4 byte Fibre Channel Data Word. 
   “EOF”: End-Of-Frame (EOF) delimiter that is the last Data Word of a Fibre Channel frame. 
   “EOFa”: A frame whose EOF is marked so that the frame is discarded by a destination port, N_Port or NL_Port. 
   “E_Port”: An expansion port that is used to connect Fibre Channel Switch elements in a Fabric. 
   “Fabric”: The structure or organization of a group of switches, target and host devices (NL_Port, N_ports etc.). 
   “F_Port”: A port to which non-loop N_Ports are attached to a fabric and does not include FL_ports. 
   “Fibre Channel ANSI Standard” (“FC-FS-2”): The standard (incorporated herein by reference in its entirety) describes the physical interface, transmission and signaling protocol of a high performance serial link for support of other high level protocols associated with IPI, SCSI, IP, ATM and others. 
   “Inter Fabric Header”: The Inter Fabric Routing Extended Header (IFR_Header) is used for routing Fibre Channel frames from one fabric to another. It provides the fabric identifier of the destination fabric, the fabric identifier of the source fabric and information to determine hop count. 
   “N_Port”: A direct fabric attached port, for example, a disk drive or a HBA. 
   “NL_Port”: A L_Port that can perform the function of a N_Port. 
   “R_CTL”: A 8 bit value containing routing information used to route Fibre Channel Frames. 
   “Switch”: A fabric element conforming to the Fibre Channel Switch standards. 
   “SOF”: Start_of_Frame (SOF) delimiter that is the first Data Word of a Fibre Channel frame. 
   “Virtual Fabric” (“VSAN”): As defined by FC-FS-2, Fibre Channel standard, incorporated herein by reference in its entirety, is a Fabric composed of partitions and N_ports having the properties of a single Fabric management domain and Generic Services; and independent from other Virtual Fabrics (e.g. an independent address space). 
   “Virtual Fabric Header” (VFT_Header): This is a header used for tagging Fibre Channel frames with a Virtual Fabric Identifier (VF_ID) of Virtual Fabric to which the frame belongs. 
   “Virtual Fabric Identifier” (“VF_ID”): A value that uniquely identifies a Virtual Fabric among plural Virtual Fabrics that shares a set of Switches and N_ports. 
   To facilitate an understanding of the preferred embodiment, the general architecture and operation of a Fibre channel System and a Fibre Channel switch element will be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture. 
   Fibre Channel System 
     FIG. 1A  is a block diagram of a fibre channel system  100  implementing the methods and systems in accordance with the adaptive aspects of the present invention. System  100  includes plural devices that are interconnected. Each device includes one or more ports, classified as node ports (N_Ports), fabric ports (F_Ports), and expansion ports (E_Ports). Node ports may be located in a node device, e.g. server  103 , disk array  105  and storage device  104 . Fabric ports are located in fabric devices such as switch  101  and  102 . Arbitrated loop  106  may be operationally coupled to switch  101  using arbitrated loop ports (FL_Ports). 
   The devices of  FIG. 1A  are operationally coupled via “links” or “paths”. A path may be established between two N_ports, e.g. between server  103  and storage  104 . A packet-switched path may be established using multiple links, e.g. an N-Port in server  103  may establish a path with disk array  105  through switch  102 . 
   Fibre Channel Switch Element 
   FIB.  1 B is a block diagram of a 20-port ASIC fabric element according to one aspect of the present invention.  FIG. 1B  provides the general architecture of a 20-channel switch chassis using the 20port fabric element. Fabric element includes ASIC  20  with non-blocking Fibre Channel class  2  (connectionless, acknowledged) service and class  3  (connectionless, unacknowledged) service between any ports. It is noteworthy that ASIC  20  may also be designed for class  1  (connection-oriented) service, within the scope and operation of the present invention as described herein. 
   The fabric element of the present invention is presently implemented as a single CMOS ASIC, and for this reason the term “fabric element” and ASIC are used interchangeably to refer to the preferred embodiments in this specification. Although  FIG. 1B  shows 20 ports, the present invention is not limited to any particular number of ports. 
   ASIC  20  has 20 ports numbered in  FIG. 1B  as GL 0  through GL 19 . These ports are generic to common Fibre Channel port types, for example, F_Port, FL_Port and E-Port. In other words, depending upon what it is attached to, each GL port can function as any type of port. Also, the GL port may function as a special port useful in fabric element linking, as described below. 
   For illustration purposes only, all GL ports are drawn on the same side of ASIC  20  in  FIG. 1B . However, the ports may be located on both sides of ASIC  20  as shown in other figures. This does not imply any difference in port or ASIC design. Actual physical layout of the ports will depend on the physical layout of the ASIC. 
   Each port GL 0 -GL 19  is comprised of transmit and receive connections to switch crossbar  50 . Within each port, one connection is through receive buffer  52 , which functions to receive and temporarily hold a frame during a routing operation. The other connection is through a transmit buffer  54 . 
   Switch crossbar  50  includes a number of switch crossbars for handling specific types of data and data flow control information. For illustration purposes only, switch crossbar  50  is shown as a single crossbar. Switch crossbar  50  is a connectionless crossbar (packet switch) of known conventional design, sized to connect 21×21 paths. This is to accommodate 20 GL ports plus a port for connection to a fabric controller, which may be external to ASIC  20 . 
   In the preferred embodiments of switch chassis described herein, the fabric controller is a firmware-programmed microprocessor, also referred to as the input/output processor (“IOP”). As seen in  FIG. 1B , bi-directional connection to IOP  66  is routed through port  67 , which connects internally to a control bus  60 . Transmit buffer  56 , receives buffer  58 , control register  62  and Status register  64  connect to bus  60 . Transmit buffer  56  and receive buffer  58  connect the internal connectionless switch crossbar  50  to IOP  66  so that it can source or sink frames. 
   Control register  62  receives and holds control information from IOP  66 , so that IOP  66  can change characteristics or operating configuration of ASIC  20  by placing certain control words in register  62 . IOP  66  can read status of ASIC  20  by monitoring various codes that are placed in status register  64  by monitoring circuits (not shown). 
     FIG. 1C  shows a 20-channel switch chassis S 2  using ASIC  20  and IOP  66 . IOP  66  in  FIG. 1C  is shown as a part of a switch chassis utilizing one or more of ASIC  20 . S 2  will also include other elements, for example, a power suplpy (not shown). The 20 GL_Ports correspond to channels C 0 -C 19 . Each GL_Port has a serial/deserializer (SERDES) designated as S 0 -S 19 . Ideally, the SERDES functions are implemented on ASIC  20  for efficiency, but may alternatively be external to each GL_Port. The SERDES converts parallel data into a serial data stream for transmission and converts received serial data into parallel data. The 8 bit to 10 bit encoding enables the SERDES to generate a clock signal from the received data stream. 
   Each GL_Port may have an optical-electric converter, designated as OE 0 -OE 19  connected with its SERDES through serial lines, for providing fibre optic input/output connections, as is well known in the high performance switch design. The converters connect to switch channels C 0 -C 19 . It is noteworthy that the ports can connect through copper paths or other means instead of optical-electric converters. 
     FIG. 1D  shows a block diagram of ASIC  20  with sixteen GL ports and four 10 G (Gigabyte) port control modules designated as XG 0 -XG 3  for four 10 G ports designated as XGP 0 -XGP 3 . ASIC  20  include a control port  62 A that is coupled to IOP  66  through a PCI connection  66 A. ASIC  20 Q also includes a Content Addressable Memory (CAM) Table  80  that maintains information regarding R_CTL, minimum Fibre Channel frame-length and maximum Fibre Channel frame-length. 
   CAM table  80  is stored in memory  80 A that is accessible to IOP  66  and other logic. CAM table  80  is a master copy for the switch element. As described below, each port can have its own CAM table with values that pertain to that particular port. Furthermore, plural ports can share a CAM Table that is located at one of the ports. 
   FIGS.  1 E- 1 / 1 E- 2  (jointly referred to as  FIG. 1E ) show yet another block diagram of ASIC  20  with sixteen GL and four XG port control modules. Each GL port control module has a Receive port (RPORT)  69  (similar to  58 ,  FIG. 1B ) with a receive buffer (RBUF)  69 A (similar to  58 ,  FIG. 1B ) and a transmit port  70  with a transmit buffer (TBUF)  70 A (similar to  56 ,  FIG. 1B ). GL and XG port control modules are coupled to physical media devices (“PMD”)  76  and  75  respectively. 
   Control port module  62 A includes control buffers  62 B and  62 D for transmit and receive sides, respectively. Module  62 A also includes a PCI interface module  62 C that allows interface with IOP  66  via a PCI bus  66 A. 
   XG_Port (for example  74 B) includes RPORT  72  with RBUF  71  similar to RPORT  69  and RBUF  69 A and a TBUF  74 B and TPORT  74 A similar to TBUF  70 A and TPORT  70 . Protocol module  73  interfaces with SERDES to handle protocol based functionality. 
   Incoming frames are received by RPORT  69  via SERDES  68  and then transmitted using TPORT  70 . Buffers  69 A and  70 A are used to stage frames in the receive and the transmit path. 
     FIG. 1F  shows a top-level block diagram of a receive port  69  that includes a frame length control module  80 B (or Control module  80 B) and a port level CAM table  80 C. CAM Table  80 C is described below with respect to  FIG. 3B . 
   CAM Table  80 C can be loaded with different values for each port. It is noteworthy that each port may have its own table  80 C or table  80 C can be shared between plural ports. In contrast, CAM table  80  is the master copy and includes information regarding all the ports. 
   It is also noteworthy that receive port  69  includes various other components that are described in co-pending patent application Ser. No. 10/894,627, filed on Jul. 20, 200, the disclosure of which is incorporated herein by reference. 
     FIG. 1G  shows a top-level block diagram for Virtual Fabrics (VSANs), which use the extended headers, according to one aspect of the present invention.  FIG. 1G  shows three Fabric switches,  1 ,  2  and  3 . Each switch has 8-ports labeled  0 - 7 . It is noteworthy that the present invention is not limited to any particular number/type of ports. 
   VSAN # 1  is the first Virtual Fabric that includes ports  0 - 3  for Switch # 1 . VSAN # 2  includes Switch # 1 , ports  4 - 7 ; Switch # 2 , ports  0 - 3 ; and Switch # 3 , ports  0 - 3 . VSAN # 3  includes Switch # 1 , ports  4 - 7  and Switch # 3 , ports  0 - 3 . VSAN # 4  includes Switch # 2 , ports  4 - 7 . 
     FIG. 1H  shows an example of Inter-Fabric connections where an extended frame header is used and processed, according to one aspect of the present invention. Eight Fabric switch are shown (numbered  1  through  8 ) to illustrate Inter-Fabric routing. Switch # 1  is coupled to Switch # 2 , while Switch # 3  is coupled to Switch # 1  and  2 . Fabric  1  includes Switch # 1 ,  2 , and  3 . 
   Fabric  2  includes Switch  4 ,  5  and  6 . Fabric  3  includes Switch  5  and Switch  7 , while Fabric  4  includes Switch  6  and Switch  8 . The extended headers are used to route frames between the plural Fabrics, for example, between Fabric  1  and Fabric  4 . It is noteworthy that the present invention is not limited to any particular number of Fabrics or switches. 
   Fibre Channel Frame 
     FIG. 2A  shows the components of a typical Fibre Channel Frame, according to one aspect of the present invention; and  FIG. 2B  shows an example of a Fibre Channel frame with additional headers ( 228 ). 
   Receive port  69  detects a frame when a SOF  220  is received. SOF  220  is 4 bytes long and indicates the start of a frame. Receive port  69  starts counting frame-length when it detects a SOF  220 . 
   Frame header  221 , which contains routing and control information follow SOF  220 . Frame header  221  comprises 6 header Dwords or 24 bytes. In a standard frame, these include R_CTL field  222 , D_ID (3 bytes), CS_CTL (3 bytes), S_ID (3 bytes) and reserved bytes. R_CTL field  222  identifies the type of frame. 
   New routing features have added additional header words  226  to the frame header  221 . The additional frame header (32 bytes) is shown in  FIG. 2B  as  228 . Examples of the new routing features include Virtual Fabric header and Inter-Fabric routing headers (shown as  226 ). 
   Frame header  228  uses two R_CTL values. R_CTL value of 50 h  or 51 h  (shown as  227 ,  FIG. 2B ) is used to identify a frame with an extended header, while R_CTL  222  is used to identify the type of frame. The total frame-length of a Fibre Channel frame depends on the frame header  221  or  228 , which in turn depends on R_CTL  222  or  227  values. 
   Payload or data field  223  follows the frame header  221  (or  228 ,  FIG. 2B ). The length of the payload varies between a minimum of 0 bytes and a maximum of 2112 bytes. The maximum length of the payload has not changed for the new routing features. It is noteworthy that the adaptive aspects of the present invention are not limited to any particular payload size or R_CTL value. 
   CRC  224 , which is 4 bytes long, follows the payload  223 . This field is used to check the data integrity of the frame. 
   EOF  225 , which is 4 bytes long, follows the CRC  224 . EOF indicates the end of a frame. When an EOF  225  is detected, receive port  69  stops counting frame-length and stores the value for future comparison and/or frame processing. 
   Process Flow for Checking Frame-Length 
     FIG. 2C  shows a top-level flow chart for checking frame-length in a Fibre Channel frame, according to one aspect of the present invention. It is noteworthy that this process flow chart is applicable to any Fibre Channel device that needs to route frames and faces the same issues as a switch element. Although the examples herein are based on a switch element, the present invention is not limited to a switch element and other devices, for example, a host bus adapter, can also use these inventive features. 
   Turning in detail to  FIG. 2C , in step S 201 , receive port  69  starts receiving a Fibre Channel frame when it detects a SOF. The receive port  69  starts counting frame-length of the received frame. The frame-length counter (not shown) is incremented by 4 bytes when the receive port  69  receives a data word. It is noteworthy that Fibre Channel data could be received in chunks of 4 bytes (Dword) on every clock. The frame length counter can count bits, bytes, Dwords or other values, and the adaptive aspects of the present invention are not limited to any particular type of counter. 
   In step S 202 , receive port  69  parses the frame and R_CTL value  222  (or  227 ) is extracted from the frame header  221 . 
   In step S 203 , R_CTL value  222  (or  227 ) is compared with the R_CTL values stored in a CAM Table  80  (or  80 C). CAM Table  80 , which maintains information regarding R_CTL and frame-length values, is described below with respect to  FIG. 3A . 
   In step S 204 , a maximum frame-length and a minimum frame-length is determined from the fields corresponding to the matched R_CTL value. If none of the values match the R_CTL value then the default (or programmed) maximum frame-length (for example, 2148 bytes) and minimum frame-length (for example, 36 bytes) are used. The maximum frame-length and minimum frame-length values from the Frame length CAM are stored for future comparison. 
   In step S 205 , receive port  69  stops incrementing the received frame-length value when it detects an EOF or error condition. 
   In step S 206 , the received frame-length is compared with the stored maximum and minimum frame-length values to determine if the received Fibre Channel frame is a long or short frame. A Fibre Channel frame is a long frame if the received frame-length is greater than the maximum frame-length and a Fibre Channel frame is a short frame if the frame-length is less than the minimum frame-length. 
   It is noteworthy that the present invention is not limited to any particular format for the maximum and/or minimum frame length comparison. For example, frame length value when compared could be the actual frame length value or as an offset value. 
   If the Fibre Channel frame is determined to be a long or short frame in step S 206 , then in step S 207 , the Fibre Channel frame is marked for discarding. For example, the EOF value may be set to EOFa, which denotes that the frame should be discarded. When the frame is marked then it is discarded by a destination, for example, a host bus adapter or a storage device. 
   In another aspect of the present invention, the frame that is too long or short is discarded in step S 207 . In the alternative, a long frame is truncated to a maximum length and a short frame is padded to the minimum length and the EOF value is replaced by an EOFa (as stated above, this denotes EOF abort). Thereafter, the receive port  69  optionally notifies IOP  66  of the error and records the error statistics for the port. 
   In step S 208 , receive port  69  processes the received Fibre Channel frame if the frame is not a long or short frame in step S 206 . 
   Content Addressable Memory (CAM) Table 
     FIG. 3A  shows CAM Table  80 , which maintains information regarding R_CTL values. CAM Table  80  is maintained in Random Access Memory (RAM)  80 A, which is accessible by IOP  66  and receive port  69 . As stated above, CAM table  80  is a master table for the switch, while each port can have its own CAM Table ( 80 C). 
   Each entry in CAM Table has a R_CTL value and the associated maximum frame-length and minimum frame-length. CAM Table  80  is comprised of a column  300  that includes the R_CTL value, a column  301  that has the corresponding maximum frame-length information and a column  302  that has the minimum frame-length information. 
   Firmware adds the entries in the CAM table  80  (and also for CAM  80 C,  FIG. 1F ) during the initialization of the switch. For example, for a typical Fibre Channel frame, entry corresponding to R_CTL values of 0×00 to 0×4F and 0X60 through 0XFF has a maximum frame-length value equal to 2148 bytes and a minimum frame-length value equal to 36 bytes. Similarly, for a Virtual Fabric frame, entry corresponding to R_CTL value equal to 0×50 has a maximum frame-length value equal to 2156 bytes and a minimum frame-length value equal to 44 bytes. Similarly, R_CTL values equal to 0×51 and 0×52 represent inter-fabric and encapsulated inter-fabric frames, respectively (i.e. frames with extended headers (see  FIG. 2B )). 
   It is noteworthy that R_CTL values can be stored in any format in Random Access Memory and the term “table” is not to be construed as a limitation. 
   In one aspect of the present invention, R_CTL values are used to determine the maximum and minimum frame-length values of the received Fibre Channel frame. These values allows a receive port to check for frame length without causing data corruption. 
   It is noteworthy that different values for the minimum frame-length and/or maximum frame-length are used for different R_CTL values. Also CAM Table  80 C provides default values for minimum frame-length and/or maximum frame-length if the extracted R_CTL values do not match stored R_CTL values. 
   It is also noteworthy that the present invention is not limited to any particular R_CTL, maximum/minimum frame length values. Switch element firmware operating under IOP  66  can program these values. 
   Frame Length Control Module 
     FIG. 3B  shows a detailed logic diagram for implementing port level CAM Table  80 C with entries 00 to entry N. CAM Table  80 C is located in each receive port  69  and is used by one port or shared between plural ports. The term “Table” as used herein is not limit to a table that simply stores values, but denotes a system/logic for achieving the adaptive aspects of the present invention. 
   It is noteworthy that although various bit values are shown in  FIG. 3B , the adaptive aspects of the present invention are not limited to any particular bit value. 
   Incoming frames information (or fields) (R_CTL  222 / 227 ) is compared by logic  30 E with entry  30 B. A valid/control bit  30 A is set for a valid control word entry. Logic  30 E generates a command/signal (output  30 E 1 ) based on the comparison. Output  30 E 1  is sent to logic  30 F that generates a hit signal  30 F 1 . 
   Output  30 F 1  is sent to an encoder module  30 G, whose output  30 H is sent to MUX  30 K. Maximum frame-length  30 C and minimum frame-length  30 D are also sent to MUX  30 K. MUX  30 K selects maximum frame-length  30 J and a minimum frame-length  30 I depending on the input signal  30 H. The selected maximum frame-length  30 J and a minimum frame-length  30 I values are shown as the entries in column  301  and  302  respectively in  FIG. 3A . 
   The present invention is not limited to CAM table  80 C as described above. A hashing table could also be used to implement the adaptive aspects of the present invention. 
   In one aspect of the present invention, frame length is checked efficiently and in real time. The foregoing process/system can accommodate the new standard Virtual Fabric and Inter-Fabric headers in previous Fibre Channel switch elements, without expensive upgrades. 
   Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.