Abstract:
A method for controlling voltage crossing a power switch of a switched-mode power converter is disclosed. The method comprises the steps of: controlling a switch frequency of a power switch of a switched-mode power converter to a first frequency as activating the switched-mode power converter; and changing the switch frequency of the power switch to a second frequency after a specific amount of time; wherein the first frequency is lower than the second frequency.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a control circuit and a method thereof, and particularly to a control circuit and a method thereof that can control voltage crossing a power switch of a switched-mode power converter. 
         [0003]    2. Description of the Prior Art 
         [0004]    A switched-mode power converter, also called a “switched-mode power supply” (SMPS), is an electronic power converter. The switched-mode power converter is used for converting and providing input power to a load. Generally speaking, a voltage level of the input power of the switched-mode power converter is different from a voltage level of output power of the switched-mode power converter. Compared to a linear power converter, the switched-mode power converter not only can provide higher power conversion efficiency, but can also have smaller area. In a transformer-coupled switched-mode power converter, the transformer-coupled switched-mode power converter utilizes a transformer to isolate a power input terminal from a power output terminal, where a side of the transformer near the power input terminal is called a primary side, and another side near the power output terminal is called a secondary side. The primary side of the transformer includes a switch for being controlled by pulse width modulation (PWM). The transformer-coupled switched-mode power converter is further divided into a forward switched-mode power converter and a flyback switched-mode power converter. 
         [0005]    Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a flyback switched-mode power converter  100  according to the prior art. As shown in  FIG. 1 , the switched-mode power converter  100  mainly includes a rectifier  104 , a transformer  106 , a regulator  108 , a photo coupler  110 , a control circuit  112 , and a power switch SW 1 . The switched-mode power converter  100  is coupled to an alternating current voltage source  102 , and provides an approximate direct current voltage to the transformer  106  and the control circuit  112  by the rectifier  104 . The control circuit  112  is used for providing a pulse width modulation signal V OUT  to control the power switch SW 1 . The transformer  106  provides input power from a primary side to a secondary side by turning-on and turning-off of the power switch SW 1 . The regulator  108  and the photo coupler  110  are used for providing a feedback compensation signal V COMP  of an output voltage of the switched-mode power converter  100  to the control circuit  112 . The control circuit  112  can execute pulse width modulation operations by comparing the feedback compensation signal V COMP  and current I P  flowing through the power switch SW 1 . 
         [0006]    However, the switched-mode power converter  100  in  FIG. 1  has disadvantages as follows: when the switched-mode power converter  100  is activated, the output voltage of the secondary side starts to increase from a ground voltage level. A characteristic of the control circuit  112  can quickly increase speed of power conversion of the transformer  106 . Therefore, the feedback compensation signal V COMP  is a high voltage which causes the power switch SW 1  to have a higher switch frequency. 
         [0007]    Please refer to  FIG. 2 .  FIG. 2  is a diagram illustrating a relationship between the feedback compensation signal V COMP  and the current I p  flowing through the power switch SW 1  when the switched-mode power converter  100  is activated. As shown in  FIG. 2 , during a first switch period of the power switch SW 1 , a switch frequency of the power switch SW 1  is higher, and time for turning-off of the power switch SW 1  is shorter, resulting in the power switch SW 1  entering a continuous mode during a second switch period of the power switch SW 1 . That is to say, the primary side of the transformer  106  can not discharge completely when the power switch SW 1  enters a next switch period, so current I p  flowing through the power switch SW 1  gradually becomes larger. Because a voltage crossing the power switch SW 1  is almost proportional to the current I P , the higher current I P  may result in the voltage crossing the power switch SW 1  being so high as to damage itself. 
         [0008]    Therefore, those skilled in the art need a method for controlling voltage crossing a power switch of a switched-mode power converter and a circuit thereof, and the method should effectively control the voltage crossing the power switch of the switched-mode power converter to prevent the power switch from being damaged when the switched-mode power converter is activated. 
       SUMMARY OF THE INVENTION 
       [0009]    An embodiment provides a method for controlling voltage crossing a power switch of a switched-mode power converter. The method includes Steps as follows: controlling a switch frequency of a power switch of the switched-mode power converter to a first frequency when the switched-mode power converter is activated; and changing the switch frequency of the power switch to a second frequency after a predetermined time. The first frequency first frequency is lower than the second frequency. 
         [0010]    Another embodiment provides a method for controlling voltage crossing a power switch of a switched-mode power converter. The method includes Steps as follows: controlling a switch frequency of a power switch of the switched-mode power converter according to a first voltage signal when the switched-mode power converter is activated; and controlling the switch frequency of the power switch according to a second voltage signal after the first voltage signal becomes greater than a threshold value. 
         [0011]    Another embodiment provides a control circuit of a switched-mode power converter. The control circuit includes a multiplexer, a clock generator, and a pulse width modulation controller. The multiplexer is used for providing an output signal with a low voltage level when activated, and providing the output signal with a high voltage level after being activated for a period of time. The clock generator is used for providing a clock signal according to the output signal of the multiplexer. The pulse width modulation controller is used for providing a pulse width modulation signal according to the clock signal. 
         [0012]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  is a diagram illustrating a flyback switched-mode power converter according to the prior art. 
           [0014]      FIG. 2  is a diagram illustrating a relationship between the feedback compensation signal and the current flowing through the power switch SW 1  when the switched-mode power converter is activated. 
           [0015]      FIG. 3  is a flowchart illustrating the method for controlling voltage crossing the power switch of the switched-mode power converter according to an embodiment. 
           [0016]      FIG. 4  is a diagram illustrating a relationship between a feedback compensation signal and current flowing through the power switch when the switched-mode power converter is activated according to the method in  FIG. 3 . 
           [0017]      FIG. 5  is a diagram illustrating a controller of the switched-mode power converter according to an embodiment. 
           [0018]      FIG. 6  is a diagram illustrating the jitter unit according to an embodiment. 
           [0019]      FIG. 7  is a diagram illustrating the clock generator according to an embodiment. 
           [0020]      FIG. 8  is a diagram illustrating a waveform of the switched-mode power converter in  FIG. 5  and  FIG. 7  and waveforms of the jitter unit and the clock generator thereof. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    The present invention provides a control circuit of a switched-mode power converter and a method for controlling voltage crossing a power switch of a switched-mode power converter that can utilize pulse width modulation and pulse frequency modulation to solve a problem of the voltage crossing the power switch of the switched-mode power converter being too high when the switched-mode power converter is activated. 
         [0022]    Please refer to  FIG. 3 .  FIG. 3  is a flowchart illustrating the method for controlling voltage crossing the power switch of the switched-mode power converter according to an embodiment. In Step  301 , a switch frequency of the power switch of the switched-mode power converter is controlled to a first frequency when the switched-mode power converter is activated, then go to Step  302 . In Step  302 , it is determined whether the switched-mode power converter is activated for a predetermined time. If yes, go to Step  303 ; if no, go to Step  301 . In Step  303 , the switch frequency of the power switch is changed to a second frequency, where the first frequency is lower than the second frequency. 
         [0023]    Please refer to  FIG. 4 .  FIG. 4  is a diagram illustrating a relationship between a feedback compensation signal V COMP  and current I P  flowing through the power switch when the switched-mode power converter is activated according to the method in  FIG. 3 . As shown in  FIG. 4 , compared to the relationship in  FIG. 2 , the switch frequency (that is, the first frequency) when the power switch is activated is slower, and time for turning-off of the power switch is longer. Therefore, a transformer of the switched-mode power converter can discharge completely during turning-off of the power switch, and not enter a continuous mode. After the predetermined time, the power switch is free from damage risk. Then, the switch frequency of the power switch is switched to the second frequency higher than the first frequency to increase speed of power conversion of the transformer. 
         [0024]    Please refer to  FIG. 5 .  FIG. 5  is a diagram illustrating a controller  500  of the switched-mode power converter according to an embodiment, where the controller  500  can be used for implementing the method in  FIG. 3 , and for substituting for the control circuit  112  in  FIG. 1 . As shown in  FIG. 5 , the control circuit  500  includes a jitter unit  502 , a clock generator  504 , a pulse width modulation controller  506 , a comparator  508 , and a multiplexer  510 . The jitter unit  502  is used for providing a jitter signal S JITTER . The clock generator  504  is used for providing a clock S CLK  required by the pulse width modulation controller  506 , that is, the clock S CLK  is the switch frequency of the power switch SW 1 . The pulse width modulation controller  506  is used for providing a pulse width modulation signal V OUT  required by the power switch SW 1 . The comparator  508  is used for comparing the jitter signal S JITTER  with a reference signal V READY . The multiplexer  510  is used for providing the jitter signal S JITTER  or the feedback compensation signal V COMP  to the clock generator  504  according to an output signal S OK  (of the comparator  508 . 
         [0025]    The clock generator  504  can obtain a frequency of the clock S ILK  according to an input signal S FRQ , and slowly execute frequency oscillation of the clock S CLK  by the jitter signal S JITTER . In a normal mode, the jitter signal S JITTER  is greater than the reference signal V READY , so the output signal S OK  (of the comparator  508  is logic “1”. Then, the clock generator  504  can obtain the frequency of the clock S ILK  according to the feedback compensation signal V COMP . However, the jitter signal S JITTER  is gradually increased from a ground voltage level to the reference signal V READY  when the switched-mode power converter is activated. During the jitter signal S JITTER  being gradually increased from the ground voltage level to the reference signal V READY , the output signal S OK  (of the comparator  508  is logic “0”, and the clock generator  504  can obtain the frequency of the clock S CLK  according to the jitter signal S JITTER . After the jitter signal S JITTER  exceeds the reference signal V READY , the clock generator  504  is controlled by the feedback compensation signal V COMP  again. Preferably, a time (that is, the predetermined time in Step  302 ) for the jitter signal S JITTER  exceeding the reference signal V READY  can be controlled by adjusting the reference signal V READY . For example, through setting the reference signal V READY , the jitter signal S JITTER  can exceed the reference signal V READY  after the current of the power switch SW 1  reaches a threshold value. 
         [0026]    Please refer to  FIG. 6 .  FIG. 6  is a diagram illustrating the jitter unit  502  according to an embodiment. As shown in  FIG. 6 , the jitter unit  502  includes inverters  602 ,  614 , current sources  604 ,  606 , and  608 , an AND gate  610 , a hysteresis comparator  612 , switches SW 2 , SW 3 , and SW 4 , and a capacitor C 4 . As shown above, when the jitter unit  502  is activated, the switch SW 2  is turned on, and the switches SW 3 , SW 4  are turned off because the input signal S OK  is the logic “0”. Therefore, the current source  604  charges the capacitor C 4 , and the jitter signal S JITTER  of the jitter unit  502  is gradually increased from the ground voltage level. When the jitter signal S JITTER  becomes greater than the reference signal V READY , the switch SW 2  is turned off and the hysteresis comparator  612  can alternately turn on the switches SW 3  and SW 4  according to the jitter signal S JITTER  and saturation voltages V JITTERH  and V JITTERL . Therefore, the jitter signal S JITTER  can be a waveform which moves slowly up and down between the saturation voltage V JITTERH  and the saturation voltage V JITTERL . 
         [0027]    Please refer to  FIG. 7 .  FIG. 7  is a diagram illustrating the clock generator  504  according to an embodiment. As shown in  FIG. 7 , the clock generator  504  includes a comparator  702 , current sources  704 ,  706 , a hysteresis comparator  708 , an inverter  710 , capacitors C 5 , C 6 , and switches SW 5 , SW 6 . The input signal S FRQ  of the clock generator  504  mainly controls driving capability of the current sources  704  and  706 , so the greater the input signal S FRQ , the stronger the driving capability of the current sources  704  and  706 . The comparator  702  turns on the switch SW 5  to redistribute charges stored in the capacitors C 5  and C 6  according to the jitter signal S JITTER . The hysteresis comparator  708  can alternately turn on the switches SW 5  and SW 6  according to a voltage of the capacitor C 6  and reference voltages V OSCH  and V OSCL . As shown above, when the clock generator  504  is activated, the input signal S FRQ  is the jitter signal S JITTER . Due to a voltage level of the jitter signal S JITTER  being lower, the driving capability of the current sources  704  and  706  is weaker, resulting in the frequency of the clock S CLK  of the clock generator  504  (that is, the first frequency) being lower. After the jitter signal S JITTER  exceeds the reference signal V READY , the input signal S FRQ  is changed to the feedback compensation signal V COMP , so the driving capability of the current sources  704  and  706  becomes stronger, resulting in the frequency of the clock S CLK  of the clock generator  504  (that is, the second frequency) being higher. 
         [0028]    Please refer to  FIG. 8 .  FIG. 8  is a diagram illustrating a waveform of the switched-mode power converter in  FIG. 5  and  FIG. 7 , and waveforms of the jitter unit and the clock generator thereof. As shown in  FIG. 8 , the feedback compensation signal V COMP  is quickly increased to the saturation voltage V JITTERH  and the jitter signal S JITTER  is gradually increased from the ground voltage level after the switched-mode power converter is activated. Meanwhile, the input signal S FRQ  of the clock generator  504  is the jitter signal S JITTER . Because the jitter signal S JITTER  is below a variation range of the clock generator  504 , the clock generator  504  outputs a lowest predetermined clock, resulting in the switch frequency of the power switch SW 1  being a lowest switch frequency (20 KHz). After the jitter signal S JITTER  becomes greater than reference signal V READY , the feedback compensation signal V COMP  is still at the saturation voltage V JITTERH . Meanwhile, the input signal S FRQ , of the clock generator  504  is changed to the feedback compensation signal V COMP , and the clock generator  504  outputs a highest predetermined clock, because the input signal S FRQ  is higher than the variation range of the clock generator  504 , resulting in the switch frequency of the power switch SW 1  being a highest switch frequency (60 KHz). After the power switch SW 1  stays at the highest switch frequency for a period of time, the feedback compensation signal V COMP  is gradually decreased to a range between the highest switch frequency (the second frequency) and the lowest switch frequency (the first frequency), so that the control circuit  500  can operate normally. In addition, as shown by an arrow in FIG.  8 , the jitter signal S JITTER  can make the frequency of the clock S ILK  of the clock generator  504  slowly oscillate upward and downward. 
         [0029]    To sum up, the control circuit of the switched-mode power converter and the method for controlling voltage crossing the power switch of the switched-mode power converter utilize the pulse width modulation and the pulse frequency modulation to solve a problem of the voltage crossing the power switch of the switched-mode power converter being too high when the switched-mode power converter is activated. 
         [0030]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.