Abstract:
In a semiconductor device including a high power supply line, a low power supply line, and a CMIS gate circuit having a high voltage side terminal, a low voltage side terminal and an output terminal, a first switching element is connected between the high voltage side terminal and the high power supply line, a second switching element is connected to the output terminal and the high power supply line, a third switching element is connected between the low voltage side terminal and the low power supply line, and a fourth switching element is connected to the output terminal and the low power supply line.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a complementary metal oxide semiconductor (CMOS) device (broadly, complementary metal insulator semiconductor (CMIS) device), and more particularly, to the improvement of a “stuck-at-1” or “stuck-at-0” fault test function thereof. 
     2. Description of the Related Art 
     In a prior art system for testing a CMOS device, the device is driven by using a functional test pattern, and as a result, an output pattern is obtained at the outputs of the device. Then, the output pattern is compared with an expected pattern. Thus, a determination of whether or not the device is normal or abnormal is made based on whether or not the output pattern coincides with the expected pattern. 
     In the above-mentioned prior art system, a fault point such as a “stuck-at-1” fault point or a “stuck-at-0” fault point is estimated. Note that a “stuck-at-1” fault and a “stuck-at-0” fault will be explained later. For this purpose, special test patterns are supplied to external input terminals, thus activating a fault. Then, a plurality of test patterns are further supplied to the external input terminals, so that the activated fault propagates through the CMOS device to reach external output terminals. This will be explained later in detail. 
     In the above mentioned prior art system, however, when the fault is deactivated within the CMOS device before the activated fault reaches the external output terminals, a plurality of test pattern signals for activating the fault and a plurality of test pattern signals for propagating the activated fault are again supplied to the external input terminals. In addition, as the CMOS device is highly-integrated, the number of test pattern signals for activating and propagating a fault is increased. As a result, it is substantially impossible to effectively detect a fault in a highly integrated CMOS device. 
     On the other hand, in order to detect a fault in a CMOS device, an I d d q  test has been adopted (see JP-A-6-118131). That is, a fault is detected by detecting an abnormal quiescent V D D  supply current I d d q , i.e., a penetration current flowing within the CMOS device. In the I d d q  test, it is unnecessary to propagate the activated fault to the external output terminals. 
     In the I d d q  test, however, since it takes a long time to measure a stable I d d q  current, it is impossible to measure all I d d q  currents for all possible test pattern signals. Therefore, in order to decrease the I d d q  test time, test patterns are limited to measure I d d q  currents, or special test patterns for the I d d q  test are used. Also, if the test pattern includes a pattern for initializing the CMOS device, it is impossible to detect a new fault. Therefore, the I d d q  test cannot increase the rate of detection of faults. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a CMOS device capable of carrying out a complete fault detecting test at a high speed. 
     According to the present invention, in a semiconductor device including a high power supply line, a low power supply line, and a CMOS gate circuit having a high voltage side terminal, a low voltage side terminal and an output terminal, a first switching element is connected between the high voltage side terminal and the high power supply line, a second switching element is connected to the output terminal and the high power supply line, a third switching element is connected between the low voltage side terminal and the low power supply line, and a fourth switching element is connected to the output terminal and the low power supply line. 
     In a normal operation mode, the first and third switching elements are turned ON, and the second and fourth switching elements are turned OFF. 
     In a “stuck-at-1” fault test mode, the fourth switching element is turned ON, and the first and second switching elements are turned OFF. The third switching element can be turned ON or OFF. 
     In a “stuck-at-0” fault test mode, the second switching element is turned ON, and the third and fourth switching elements are turned OFF. The first switching element can be turned ON or OFF. 
     Also, a plurality of CMOS gate circuits are individually subjected to a “fault-at-1” fault test mode or a “fault-at-0” fault test mode, and thus, a “bridge” fault between two of the CMOS gate circuits can be detected. Note that a “bridge” fault is explained later. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description as set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein: 
     FIG. 1A is a circuit diagram illustrating a prior art two-input CMOS NAND circuit; 
     FIG. 1B is a circuit diagram illustrating a prior art two-input CMOS NOR circuit; 
     FIG. 2A is a circuit diagram illustrating a first prior art CMOS device including the NAND circuit of FIG. 1A; 
     FIG. 2B is a circuit diagram illustrating a second prior art CMOS device including the NAND circuit of FIG. 1B; 
     FIG. 3A is a circuit diagram showing a “stuck-at-1” fault in the device of FIG. 2A; 
     FIG. 3B is a circuit diagram showing a “stuck-at-1” fault in the device of FIG. 2B; 
     FIG. 4A is a circuit diagram showing a “stuck-at-0” fault in the device of FIG. 2A; 
     FIG. 4B is a circuit diagram showing a “stuck-at-0” fault in the device of FIG. 2B; 
     FIG. 5A is a circuit diagram illustrating a two-input CMOS NAND circuit according to the present invention; 
     FIG. 5B is a circuit diagram illustrating a two-input CMOS NOR circuit according to the present invention; 
     FIG. 6A is a circuit diagram illustrating a first embodiment of the CMOS device including the NAND circuit of FIG. 5A according to the present invention; 
     FIG. 6B is a circuit diagram illustrating a second embodiment of the CMOS device including the NAND circuit of FIG. 5B according to the present invention; 
     FIG. 7A is a circuit diagram showing a “stuck-at-1” fault in the device of FIG. 6A; 
     FIG. 7B is a circuit diagram showing a “stuck-at-1” fault in the device of FIG. 6B; 
     FIG. 8A is a circuit diagram showing a “stuck-at-0” fault in the device of FIG. 7A; 
     FIG. 8B is a circuit diagram showing a “stuck-at-0” fault in the device of FIG. 7B; 
     FIG. 9 is a circuit diagram of a generalized CMOS device of the devices of FIGS. 6A and 6B; 
     FIG. 10 is a circuit diagram illustrating a third embodiment of the CMOS device according to the present invention; 
     FIG. 11 is a circuit diagram showing a “bridge” fault in the device of FIG. 10; and 
     FIG. 12 is a circuit diagram illustrating a fourth embodiment of the CMOS device according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before the description of the preferred embodiments, prior art CMOS devices will be explained with reference to FIGS. 1A,  1 B,  2 A,  2 B,  3 A,  3 B,  4 A and  4 B. 
     In FIG. 1A, which illustrates a prior art two-input input CMOS NAND circuit, P-channel MOS transistors Q p 1 1  and Q p 1 2  are connected in parallel between a power supply line V D D  and an output line OUT 1 , and N-channel MOS transistors Q n 1 1  and Q n 1 2  are connected in series between the output line OUT 1  and a ground line GND. An input signal IN 1 1  is applied to gates of the transistors Q p 1 1  and Q n 1 1 , and an input signal IN 1 2  is applied to gates of the transistors Q p 1 2  and Q n 1 2 . 
     If at least one of the input signals IN 1 1  and IN 1 2  is low, the voltage at the output line OUT 1  is high. On the other hand, if both of the input signals IN 1 1  and IN 1 2  are high, the voltage at the output OUT 1  is low. 
     In FIG. 1B, which illustrates a prior art two-input CMOS NOR circuit, P-channel MOS transistors Q p 2 1  and Q p 2 2  are connected in series between the power supply line V D D  and an output line OUT 2 , and N-channel MOS transistors Q n 2 1  and Q n 2 2  are connected in parallel between the output line OUT 2  and the ground line GND. An input signal IN 2 1  is applied to gates of the transistors Q p 2 1  and Q n 2 1 , and an input signal IN 2 2  is applied to gates of the transistors Q p 2 2  and Q n 2 2 . 
     If at least one of the input signals IN 2 1  and IN 2 2  is high, the voltage at the output line OUT 2  is low. On the other hand, if both of the input signals IN 1 1  and IN 1 2  are low, the voltage at the output line OUT 2  is high. 
     In FIG. 2A, which illustrates a first prior art CMOS device, the NAND circuit of FIG. 1A is included as indicated by reference G 1 . That is, reference numeral  101  designates a sequential circuit/combination circuit connected between external input terminals  102  and external output terminals  103 . 
     As illustrated in FIG. 3A, if the output of the NAND circuit G 1  is short-circuited to the power supply line V D D , this is called a “stuck-at-1” fault. Note that such a “stuck-at-1” fault can be represented by a resistor F 1  having a small resistance connected between the output of the NAND circuit G 1  and the power supply line V D D . 
     In FIG. 3A, in order to detect a “stuck-at-1” fault, special test pattern signals are supplied to the external input terminals  102 , so that the input signals of the NAND circuit G 1  are both high. Therefore, a current flows from the power supply line V D D  via the “stuck-at-1” fault (the resistor F 1 ) to the ground level GND. As a result, the output of the NAND circuit G 1  is reversed, thus activating the “stuck-at-1” fault. 
     As illustrated in FIG. 4A, if the output of the NAND circuit G 1  is short-circuited to the ground line GND, this is called a “stuck-at-0” fault. Note that such a “stuck-at-0” fault can be represented by a resistor F 1 ′ connected between the output of the NAND circuit G 1  and the ground line GND. 
     In FIG. 4A, in order to detect a “stuck-at-0” fault, special test pattern signals are supplied to the external input terminals  102 , so that at least one of the input signals of the NAND circuit G 1  is low. Therefore, a current flows from the output of the NAND circuit G 1  via the “stuck-at-0” fault (the resistor F 1 ′) to the ground level GND. As a result, the output of the NAND circuit G 1  is reversed, thus activating the “stuck-at-0” fault. 
     In FIG. 2B, which illustrates a second prior art CMOS device, the NOR circuit of FIG. 1B is included as indicated by reference G 2 . That is, reference numeral  201  designates a sequential circuit/combination circuit connected between external input terminals  202  and external output terminals  203 . 
     As illustrated in FIG. 3B, if the output of the NOR circuit G 2  is short-circuited to the power supply line V D D , this is also called a “stuck-at-1” fault. Note that such a “stuck-at-1” fault can be represented by a resistor F 2  having a small resistance connected between the output of the NOR circuit G 2  and the power supply line V D D . 
     In FIG. 3B, in order to detect a “stuck-at-1” fault, special test pattern signals are supplied to the external input terminals  202 , so that at least one of the input signals of the NOR circuit G 2  is high. Therefore, a current flows from the power supply line V D D  via the “stuck-at-1” fault (the resistor F 2 ) to the ground level GND. As a result, the output of the NOR circuit G 2  is reversed, thus activating the “stuck-at-1” fault. 
     As illustrated in FIG. 4B, if the output of the NOR circuit G 2  is short-circuited to the ground line GND, this is also called a “stuck-at-0” fault. Note that such a “stuck-at-0” fault can be represented by a resistor F 2 ′ connected between the output of the NOR circuit G 2  and the ground line GND. 
     In FIG. 4B, in order to detect a “stuck-at-0” fault, special test pattern signals are supplied to the external input terminals  202 , so that the input signals of the NOR circuit G 1  are both low. Therefore, a current flows from the output of the NOR circuit G 2  via the “stuck-at-0” fault (the resistor F 2 ′) to the ground level GND. As a result, the output of the NOR circuit G 2  is reversed, thus activating the “stuck-at-0” fault. 
     In FIGS. 3A,  3 B,  4 A and  4 B, in order to detect the “stuck-at-1” or “stuck-at-0” fault, a plurality of test pattern signals are further supplied to the external input terminals  102  or  202 , so that the “stuck-at-1” or “stuck-at-0” fault propagates through the sequential circuit/combination circuit  101  or  201  to reach the external output terminals  103  or  203 . 
     In FIGS. 3A,  3 B,  4 A and  4 B, however, when the “stuck-at-1” or “stuck-at-0” fault is deactivated within the sequential circuit/combination circuit  101  or  201  before the “stuck-at-1” or “stuck-at-0” fault reaches the external output terminals  103  or  203 , a plurality of test pattern signals for activating the “stuck-at-1” or “stuck-at-0” fault and a plurality of test pattern signals for propagating the activated “stuck-at-1” or “stuck-at-0” fault are again supplied to the external input terminals  102  or  202 . In addition, as the CMOS device is highly-integrated, the number of test pattern signals for activating and propagating a “stuck-at-1” or “stuck-at-0” fault is increased. As a result, it is substantially impossible to effectively detect a “stuck-at-1” or “stuck-at-0” fault in a highly integrated CMOS device. 
     On the other hand, in order to detect a fault in a CMOS device, an I d d q  test has been adopted. That is, a fault is detected by detecting an abnormal quiescent V D D  supply current I d d q , i.e., a penetration current flowing within the CMOS device. For example, in the device of FIGS. 3A and 3B, if a “stuck-at-1” fault is activated, an abnormal I d d q  current from the power supply line V D D  to the ground line GND. Such an abnormal I d d q  current can be detected by a current detector connected to the power supply line V D D  or the ground line GND. Also, in the device of FIGS. 4A and 4B, if a “stuck-at-0” fault is activated, an abnormal I d d q  current flow from the power supply line V D D  to the ground line GND. Such an abnormal I d d q  current can be detected by a current detector connected to the power supply line V D D  or the ground line V D D . In the I d d q  test, it is unnecessary to propagate the activated fault to the external output terminals  103  or  203 . 
     In the I d d q  test, however, since it takes a long time to measure a stable I d d q  current, it is impossible to measure all I d d q  currents for all possible test pattern signals. Therefore, in order to decrease the I d d q  test time, test pattern signals are limited to limit measure I d d q  currents, or special test pattern signals for the I d d q  test are used. This cannot increase the rate of detection of fault points. 
     In FIG. 5A, which illustrates a two-input CMOS NAND circuit according to the present invention, a P-channel MOS transistor Q p 1 3  connected between the sources of the P-channel MOS transistors Q p 1 1  and Q p 1 2  and the power supply line V D D , a P-channel MOS transistor Q p 1 4  connected between the output line OUT 1  and the power supply line V D D , an N-channel MOS transistor Q n 1 3  connected between the source of the N-channel MOS transistor Q n 1 2  and the ground line GND, and an N-channel MOS transistor Q n 1 4  connected between the output line OUT 1  and the ground line GND are added to the elements of the NAND circuit of FIG.  1 A. The gate of the transistor Q p 1 3  is controlled by the voltage at a control line POFF, the gate of the transistor Q p 1 4  is controlled by the voltage at a control line PON, the gate of the transistor Q n 1 3  is controlled by the voltage at a control line NOFF, and the gate of the transistor Q n 1 4  is controlled by the voltage at a control line NON. 
     In a normal operation mode, the voltage at the control line POFF is low (=GND) and the voltage at the control NOFF is high (=V D D ), so that the transistors Q p 1 3  and Q n 1 3  are turned ON. On the other hand, the voltage at the control line PON is high (=V D D ) and the voltage at the control line NON is low (=GND), so that the transistors Q p 1 4  and Q n 1 4  are turned OFF. 
     In a “stuck-at-1” fault test mode, the voltage at the control line NON is high (=V D D ), so that the transistor Q n 1 4  is turned ON. On the other hand, the voltages at the control lines POFF and PON are high (=V D D ), so that the transistors Q p 1 3  and Q p 1 4  are turned OFF. In this case, the voltage at the control line NOFF may be high or low, so that the transistor Q n 1 3  is turned ON or OFF, which does not affect the “stuck-at-1” fault test mode. 
     In a “stuck-at-0” fault test mode, the voltage at the control line PON is low (=GND), so that the transistor Q p 1 4  is turned ON. On the other hand, the voltages at the control lines NOFF and NON are low (=GND), so that the transistors Q n 1 3  and Q n 1 4  are turned OFF. In this case, the voltage at the control line POFF may be low or high, so that the transistor Q p 1 3  is turned ON or OFF, which does not affect the “stuck-at-0” fault test mode. 
     In FIG. 5B, which illustrates a two-input CMOS NOR circuit according to the present invention, a P-channel MOS transistor Q p 2 3  connected between the source of the P-channel MOS transistor Q p 2 2  and the power supply line V D D , a P-channel MOS transistor Q p 2 4  connected between the output line OUT 2  and the power supply line V D D , an N-channel MOS transistor Q n 2 3  connected between the sources of the N-channel MOS transistors Q n 1 1  and Q n 1 2  and the ground line GND, and an N-channel MOS transistor Q n 2 4  connected between the output line OUT 2  and the ground line GND are added to the elements of the NOR circuit of FIG.  1 B. The gate of the transistor Q p 2 3  is controlled by the voltage at the control line POFF, the gate of the transistor Q p 2 4  is controlled by the voltage at the control line PON, the gate of the transistor Q n 2 3  is controlled by the voltage at the control line NOFF, and the gate of the transistor Q n 2 4  is controlled by the voltage at the control line NON. 
     In a normal operation mode, the voltage at the control line POFF is low (=GND) and the voltage at the control NOFF is high (=V D D ), so that the transistors Q p 2 3  and Q n 2 3  are turned ON. On the other hand, the voltage at the control line PON is high (=V D D ) and the voltage at the control line NON is low (=GND), so that the transistors Q p 2 4  and Q n 2 4  are turned OFF. 
     In a “stuck-at-1” fault test mode, the voltage at the control line NON is high (=V D D ), so that the transistor Q n 2 4  is turned ON. On the other hand, the voltages at the control lines POFF and PON are high (=V D D ), so that the transistors Q p 2 3  and Q p 2 4  are turned OFF. In this case, the voltage at the control line NOFF may be high or low, so that the transistor Q n 2 3  is turned ON or OFF, which does not affect the “stuck-at-1” fault test mode. 
     In a “stuck-at-0” fault test mode, the voltage at the control line PON is low (=GND), so that the transistor Q p 2 4  is turned ON. On the other hand, the voltages at the control lines NOFF and NON are low (=GND), so that the transistors Q n 2 3  and Q n 2 4  are turned OFF. In this case, the voltage at the control line POFF may be low or high, so that the transistor Q p 2 3  is turned ON or OFF, which does not affect the “stuck-at-0” fault test mode. 
     In FIG. 6A, which illustrates a first embodiment of the CMOS device according to the present invention, the NAND circuit of FIG. 5A is included as indicated by reference G 1 1 . That is, reference numeral  111  designates a sequential circuit/combination circuit connected between external input terminals  112  and external output terminals  113 . 
     In a normal operation mode, the voltages at the control lines POFF and PON are low (=GND) and high (=V D D ), respectively, and the voltages at the control lines NOFF and NON are high (=V D D ) and low (=GND), respectively. 
     As illustrated in FIG. 7A, if the output of the NAND circuit G 1 1  is short-circuited to the power supply line V D D , this is called a “stuck-at-1” fault. Note that such a “stuck-at-1” fault can be represented by a resistor F 1  having a small resistance connected between the output of the NAND circuit G 1 1  and the power supply line V D D . 
     In FIG. 7A, in order to detect a “stuck-at-1” fault, the voltage at the control line NON is high (=V D D ), and the voltage at the control lines POFF and PON are high (=V D D ). As a result a current flows from the power supply line V D D  via the “stuck-at-1” fault (the resistor F 1 )to the ground level GND. Such a current flowing through a “stuck-at-1” fault can be detected by a current detector (not shown) connected to the power supply line V D D  or the ground line GND. 
     As illustrated in FIG. 8A, if the output of the NAND circuit G 1 1  is short-circuited to the ground line GND, this is called a “stuck-at-0” fault. Note that such a “stuck-at-0” fault can be represented by a resistor F 1 ′ having a small resistance connected between the output of the NAND circuit G 1 1  and the ground line GND. 
     In FIG. 8A, in order to detect a “stuck-at-0” fault, the voltage at the control line PON is low (=GND), and the voltage at the control lines NOFF and NON are low (=GND). As a result, a current flows from the output of the NAND circuit G 1  via the “stuck-at-0” fault (the resistor F′ 1 ) to the ground level GND. Such a current flowing through a “stuck-at-0” fault can be detected by a current detector (not shown) connected to the power supply line V D D  or the ground line GND. 
     In FIG. 6B, which illustrates a second embodiment of the CMOS device according to the present invention, the NOR circuit of FIG. 5B is included as indicated by reference G 1 2 . That is, reference numeral  211  designates a sequential circuit/combination circuit connected between external input terminals  212  and external output terminals  213 . 
     In a normal operation mode, the voltages at the control lines POFF and PON are low (=GND) and high (=V D D ), respectively, and the voltages at the control lines NOFF and NON are high (=V D D ) and low =GND), respectively. 
     As illustrated in FIG. 7B, if the output of the NOR circuit G 1 2  is short-circuited to the power supply line V D D , this is called a “stuck-at-1” fault. Note that such a “stuck-at-1” fault can be represented by a resistor F 2  having a small resistance connected between the output of the NOR circuit G 1 2  and the power supply line V D D . 
     In FIG. 7B, in order to detect a “stuck-at-1” fault, the voltage at the control line NON is high (=V D D ), and the voltages at the control lines POFF and PON are high (=V D D ). As a result, a current flows from the power supply line V D D  via the “stuck-at-1” fault (the resistor F 2 ) to the ground level GND. Such a current flowing through a “stuck-at-1” fault can be detected by a current detector (not shown) connected to the power supply line V D D  or the ground line GND. 
     As illustrated in FIG. 8B, if the output of the NOR circuit G 1 2  is short-circuited to the ground line GND, this is called a “stuck-at-0” fault. Note that such a “stuck-at-0” fault can be represented by a resistor F 2 ′ having a small resistance connected between the output of the NOR circuit G 1 2  and the ground line GND. 
     In FIG. 8B, in order to detect a “stuck-at-0” fault, the voltage at the control line PON is low (=GND), and the voltages at the control lines NOFF and NON are low (=GND). As a result, a current flows from the output of the NAND circuit G 1  via the “stuck-at-0” fault (the resistor F 1 ′) to the ground level GND. Such a current flowing through a “stuck-at-0” fault can be detected by a current detector (not shown) connected to the power supply line V D D  or the ground line GND. 
     In FIG. 9, which illustrates a circuit diagram of a generalized CMOS device of the CMOS devices of FIGS. 6A and 6B, reference numeral  301  designates a sequential circuit/combination circuit connected between external input terminals  302  and external output terminals  303 . Also, a CMOS logic gate circuit G 3 1  is formed by the NAND circuit G 1 1  of FIG. 5A or the NOR circuit G 1 2  of FIG.  5 B. In this case, the CMOS logic gate circuit G 3 1  is formed by an n-bit input NAND circuit or an n-bit input NOR circuit (n=3, 4, . . . ) having the control lines PON, POFF, NON and NOFF. Generally, a “stuck-at-1” fault of the CMOS logic gate circuit G 3 1  can be detected by causing the voltage at the control lines NON, PON and POFF to be high (=V D D ), and a “stuck-at-0” fault of the CMOS logic gate circuit G 3 1  can be detected by causing the voltages at the control lines PON, NON and NOFF to be low (=GND). 
     In FIG. 10, which illustrates a third embodiment of the CMOS device according to the present invention, two kinds of CMOS logic gate circuits G 3 1  and G 3 2  are provided. In FIG. 10, reference numeral  301  designates a sequential circuit/combination circuit connected between external input terminals  302  and external output terminals  303 . 
     The CMOS logic gate circuit G 3 1  is controlled by the voltages at control lines PON 1 , POFF 1 , NON 1  and NOFF 1 , and the CMOS logic gate circuit G 3 2  is controlled by the voltages at control lines PON 2 , POFF 2 , NON 2  and NOFF 2 . Therefore, a “stuck-at-1” fault of the CMOS logic gate circuit G 3 1  can be detected by causing the voltage at the control lines NON 1 , PON 1 , and POFF 1  to be high (=V D D ), and a “stuck-at-0” fault of the CMOS logic gate circuit G 3 1  can be detected by causing the voltages at the control lines PON 1 , NON 1  and NOFF 1  to be low (=GND). On the other hand, a “stuck-at-1” fault of the CMOS logic gate circuit G 3 2  can be detected by causing the voltage at the control line NON 2 , PON 2  and POFF 2  to be high (=V D D ), and a “stuck-at-0” fault of the CMOS logic gate circuit G 3 2  can be detected by causing the voltages at the control lines PON 2 , NON 2  and NOFF 2  to be low (=GND). 
     In FIG. 10, a “bridge” fault between the CMOS logic gate circuits G 3 1  and G 3 2  can be detected. That is, as illustrated in FIG. 11, if the output of the CMOS logic circuit G 3 1  is short-circuited to the output of the CMOS logic gate circuit G 3 2 , this is called a “bridge” fault. Note that such a “bridge” fault can be represented by a resistor F 3  having a small resistance connected between the outputs of the CMOS logic circuits G 3 1  and G 3 2 . 
     In FIG. 11, in order to detect a “bridge” fault, the voltages at the control lines NON 1 , PON 1  and POFF 1  to be high (=V D D ) and the voltage at the control lines PON 2 , NON 2 , and NOFF 2  to be low (=GND). Therefore, the voltage at the output of the CMOS logic gate circuit G 3 1  is low (=GND) and the voltage at the output of the CMOS logic gate circuit G 3 2  is high (=V D D ). As a result, a current flows from the power supply line V D D  via the “bridge” fault (the resistor F 3 ) to the ground line GND. Such a current as a “bridge” fault can be detected by a current detector (not shown) connected to the power supply line V D D  or the ground line GND. Similarly, the voltages at the control lines NON 1 , PON 1  and POFF 1  to be low (=GND) and the voltages at the control lines PON 2 , NON 2  and NOFF 2  to be high (=V D D ). Therefore, the voltage at the output of the CMOS logic gate circuit G 3 1  is high (=V D D ) and the voltage at the output of the CMOS logic gate circuit G 3 2  is low (=GND). As a result, a current flows from the power supply line V D D  via the “bridge” fault (the resistor F 3 ) to the ground line GND. Such a current as a “bridge” fault can be detected by a current detector (not shown) connected to the power supply line V D D  or the ground line GND. 
     In FIG. 12, which illustrates a fourth embodiment of the CMOS device according to the present invention, n kinds (n=3, 4, . . . ) of CMOS logic gate circuits G 4 1 , G 4 2 , . . . G 4      n    are provided. In FIG. 12, reference numeral  401  designates a sequential circuit/combination circuit connected between external input terminals  402  and external output terminals  403 . 
     The CMOS logic gate circuit G 4      i    (i=1, 2, . . . , n) is controlled by a control signal C i  (the voltages at control lines PONi, POFFi, NONi and NOFFi). The control signal C i  is generated from a test signal control circuit  404  which is connected to external test terminals  405 . 
     In each of the CMOS logic gate circuit G 4 1 , G 4 2 , . . . , G 4      n   , a “stuck-at-1” or “stuck-at-0” fault can be detected in the same way as in the fifth embodiment. Also, in two of the CMOS logic gate circuits G 4 1 , G 4 2 , . . . G 4      n   , a “bridge” fault can be detected in the same way as in the third embodiment. 
     Note that the test signal control circuit  404  can be of a decoder type, to thereby reduce the number of the external test terminals  405 . 
     In the above-mentioned embodiments, although a definite number of CMOS logic gate circuits are excluded from the sequence circuit/combination circuit, all the CMOS logic gate circuits included therein are subjected to detection of a “stuck-at-1” fault, a “stuck-at-0” fault or a “bridge” fault according to the present invention. 
     As explained hereinabove, according to the present invention, a “stuck-at-1” or “stuck-at-0” fault can be detected without activating and propagating such a “stuck-at-1” or “stuck-at-0” fault by supplying special test pattern signals to the external input terminals, thus decreasing the test time. In addition, a “bridge” fault can be detected without supplying special test pattern signals to the external input terminals, which also can decrease the test time.