Abstract:
A winner-take-all (WTA) circuit apparatus for comparing two current inputs from a WTA circuit to a threshold current to create a reject signal, to assist in the decision criteria of a winner-take-all network. The circuit compares the two input currents from the WTA circuit by using NMOS transistors which perform electrical mathematical functions by manipulating the currents. The end result is that the difference of the two currents is compared with a reference current and a voltage level is outputted. The reference current is adjustable, and the invention also provides a WTA circuit with weighted inputs, and the ability to select between a 1-WTA, and a 2-WTA configuration. The invention therefore solves the problems of prior art by being capable of properly selecting current levels or rejecting current levels which are too close in value, with a voltage reject signal.

Description:
BACKGROUND OF INVENTION 
     Field of the Invention 
     The present invention relates to a winner-take-all (WTA) analog circuit, and more particularly, to a reject signal for a WTA circuit. 
     Artificial neural networks and fuzzy logic are very effective in processing complex scientific, and engineering problems such as pattern classification since both of them are non-parametric, and need no mathematical model. Their massive parallelism, learning ability, adaptivity and fault tolerance make them more attractive in the field of pattern information processing. Although software simulations based on theory of artificial neural network, and fuzzy logic paradigms can be performed in conventional Von Neumann machines, the simulations usually take too much time for practical applications. Recently many significant advances in electronic implementation of neural networks and fuzzy logic have been achieved. Winner-take-all networks for selecting the most prominent one from N elements are central processing components in most model of neural networks such as Hamming neural network, ART (Adaptive Resonance Theory) model, SOFM (Self-organized Feature Mapping) model and fuzzy processors. It can be regarded as 1-WTA if only one prominent element is selected in one time, we call it k-WTA networks if it can select k maximum from N elements. 
     The WTA circuit operates by having a plurality of inputs with corresponding outputs. Using an example of a 1-WTA configuration, the circuit will select the current input that has a maximum magnitude (hence winner-take-all), and switch its corresponding output to a high voltage state. The other voltage outputs will be at a low voltage state. 
     In a normal k-WTA network the system will choose the most prominent element(s) of N inputs. If one of the elements is in a rising condition however it can be very difficult for the system to determine which element(s) are the most prominent. In the previous art if a WTA network is presented with two inputs that are both at similar current levels the circuit could possibly choose the wrong input as being the most prominent element or could simply reject both signals even though a definable difference exists. This limitation becomes especially important on circuits with highly varying inputs or noise. 
     Therefore a need exists for a k-WTA network that has the ability to correctly choose or reject two similar inputs by sending out a reject signal. 
     SUMMARY OF THE INVENTION 
     The invention as described herein provides a circuit apparatus for comparing two current inputs from a WTA circuit to a threshold current to create a reject signal if needed to assist in the decision criteria of a winner-take-all network. The threshold current is adjustable. The circuit then sends out a voltage output depending on the a comparison which can act as a reject signal. The invention also provides a WTA circuit with weighted inputs and the ability to select between a 1-WTA, and a 2-WTA configuration. 
     The circuit compares the two input currents from the WTA circuit by using NMOS transistors which perform electrical mathematical functions by manipulating the currents. The end result is that the difference of the two currents is compared with a reference current. The output voltage level which has two logical states is then set either high or low to indicate if the two inputs are definable or if their values are too close according to the threshold current to determine which current input is the most prominent. 
     The invention therefore solves the problems of prior art by being capable of properly selecting current levels or rejecting current levels which are too close in value, with a voltage reject signal. This allows for the proper decision criteria for the determination of a most prominent input. 
     These and other features, which characterize the invention, are set forth in the claims annexed hereto and forming a further part hereof. However, for a better understanding of the invention, and of the advantages and objectives attained through its use, reference should be made to the drawings, and to the accompanying descriptive matter, in which there is described exemplary embodiments of the invention. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 is a circuit diagram of one preferred embodiment of the invention. 
     FIG. 2 is a timing diagram showing the WTA inputs and the corresponding reject voltage signal output. 
    
    
     DETAILED DESCRIPTION 
     In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. The preferred embodiments are described in sufficient detail to enable those killed in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims. 
     FIG. 1 shows an apparatus according to a preferred embodiment of the invention. For ease of description FIG. 1 has been broken into three blocks. Block  1  shows a WTA circuit with weighted inputs. Block  2  shows the current comparison circuit which is the main thrust of the invention. Block  2  shows a circuit for selecting a 1-WTA or 2-WTA configuration. 
     Referring to Block 1 the WTA circuit is composed of four current inputs (I 1 -I 4 ) and four outputs (O 1 -O 4 ). However one skilled in the art will recognize that the configuration can be used for any number of inputs and outputs. In the first stage corresponding to input I 1  and output O 1 , the input is connected to node A 1 . Node A 1  is connected to the gates of PMOS P 1 , P 2 , and P 3 . The drain of P 1  is connected to node A 1 . The drain of P 2  is connected to the drain of M 1  and the gates of M 1  and M 2 . The drain of P 3  is connected to the drain of S 1 . The sources of P 1 , P 2 , P 3 , P 4 , and P 5  are connected to the source voltage V DD . The drain and gate of PMOS P 4  is connected to node A 2 . The gate of P 5  is connected to node A 2 . The drain of P 5  is connected to B 1  and the drain of NMOS M 2 . B 1  is a current comparator for converting a current into a logical voltage level whose design is well known in the art and not disclosed in the drawing. The source of M 1  is connected to the drain of M 3 . The source of M 3  is connected to ground. The gate of M 3  and the source of M 2  are connected to node A 3 . The source of S 1  is connected to node A 5 . 
     Reference will now be made to the other stages of FIG. 1 which are very similar in design, and connect I 2 , I 3 , and I 4  to their respective outputs. The input is connected to node A 4 . Node A 4  is connected to the gates of PMOS P 6 , P 7 , and P 8 . The drain of P 6  is connected to node A 4 . The drain of P 7  is connected to the drain of M 4  and the gates of M 4  and M 5 . The drain of P 8  is connected to the drain of S 2 , or S 3  or S 4 . The sources of P 6 , P 7 , P 8 , and P 9  are connected to the source voltage V DD . The gate of P 9  is connected to node A 2 . The drain of P 9  is connected to B 2  or B 3  or B 4 , and the drain of NMOS M 5 . B 2 , B 3 , or B 4  is a current comparator for converting a current into a logical voltage level whose design is well known in the art and not disclosed in the drawing. The source of M 4  is connected to the drain of M 6 . The source of M 6  is connected to ground. The gate of M 6  and the source of M 5  are connected to node A 3 . The source of S 2  or S 3  or S 4  are connected to node A 5 . NMOS Transistors S 1 -S 4  allow each input to be weighted. Typically in most applications the inputs will be weighted evenly so S 1 =S 2 =, . . . , SN=1/N. 
     Referring to block  2  the circuit is capable of selecting the most prominent element or elements in a 1-WTA, or 2-WTA network. The circuit is capable of selecting a 1-WTA network, or a 2-WTA network configuration through the use of a CTL input. NMOS M 10 , M 11 , M 12 , and M 13  make up a circuit that allows the device to be configured as either a 1-WTA device, or a 2-WTA device under the control of current positive feedback loop composed of transistors M 11 , M 2 , M 5  and the cascaded PMOS current mirrors. The network has the advantage of avoiding dc matching errors due to asymmetrical biasings. It is also a self bias circuit and needs no applied bias current and so the range of input currents has no limitations, therefore making it a self-adaptive WTA network. In the circuit when the CTL signal is a logical 1 (or high) the circuit is configured as 2-WTA. When the CTL signal is a logical 0 (or low) the circuit is configured as a 1-WTA. The sources of NMOS M 10  M 11 , and M 12  are connected to ground. The gates of M 10  and M 1 , and the drains of M 12  and M 13  are connected to node A 3 . The drain of M 10  is connected to node A 2 . The gate of NMOS M 13  is connected to the CTL signal. 
     Referring to block  3  this circuit allows the device to consider two inputs to determine if the higher magnitude input is more prominent or if they are too close to make that determination. The most prominent element is taken from the inputs (I MAX ) and is added to the most second prominent element (I SEC ) to give a result of I SUM . Using a current mirror a value of the value of I MAX  is doubled to give  2 I max . Then the circuit determines a value I DIFF  which is obtained by subtracting the value of I SUM  from  2 I MAX . The process can also be performed by subtracting a second (I SEC ) current level from a first current level (I MAX ) to give a third current level (I DIFF ) which is then compared with the threshold current. The threshold current is defined by the equation:          I   TH     =         ∑     i   =   1     N                       S   I          I   I         +     I   0                              
     If the threshold current is greater than I DIFF  (I TH &gt;I DIFF ) then the circuit outputs a low voltage level. If the threshold current is less than I DIFF (I TH &lt;I DIFF ) then the circuit outputs a high voltage level although someone skilled in the art will realize that there are many ways to output the result of the comparison. 
     Referring again to block  2  as stated previously a CTL input is used to configure the system as a 2-WTA with a high CTL input, and 1-WTA with a low CTL input. The CTL input is connected to the gates of NMOS M 20  and M 21 , and after being inverted is connected to the gates of M 25  and M 26 . The drain of M 20  is connected to the source of S 1 . The source of M 20 , M 26  and the drains of M 21 , M 22  are connected to node A 20 . NMOS M 20  can act as a storage device to store the current level of I SUM . Connected to node A 21  is the source of M 22 , the drain of M 23  and the gate of M 24 . The source of M 21  connects to the gate of M 23 . The gate of M 22 , the drain of M 24 , and the sources of P 20 , P 21 , P 22 , and P 23  connect to V DD . The drain of M 25  connects to node A 5 . The source of M 25  connects to node A 22 . Node A 22  connects to the drain of M 27 , and the gates of M 27 , M 28 . An input threshold current I TH  connects to the drain and gate of M 29  and the gate of M 30 . The sources of M 23 , M 24 , M 27 , M 28 , M 29 , and M 30  all connect to ground. The drain of M 26  connects to the drain of P 20  and the gates of P 20 , P 21 . The drain of P 21  connects to node A 23 . The drains of P 21  and P 22  connect to node A 23  as well as the gates of P 22 , P 23 . The drain of P 23  connects to the drain of M 30  and to an inverter for the output V OUT . 
     FIG. 2 shows a timing diagram. Section  110  shows a set of 4 inputs where the horizontal axis represents time, and the longitudinal axis represents current. The inputs are from the WTA circuit, which has a low CTL value and is therefore configured as 1-WTA. As seen in  110  current I 3  is rising. Sections  120  and  130  show the output as relates to one preferred embodiment of the invention. The horizontal axis represents time, while the longitudinal axis represents voltage. Section  120  shows a voltage output when the threshold current level is set at 10 uA. Section  130  shows a voltage output when the threshold current level is set at 20 uA. 
     Various additional modifications may be made to the illustrated embodiments without departing from the spirit and scope of the invention. Therefore, the invention lies in the claims hereinafter appended.