Abstract:
A display system uses a weighted PWM scheme to deliver control during a frame time for developing a plurality of grayscale levels in each of a plurality of pixels. Of all the weighted subframes, a predetermined number of the shortest subframes utilize a like subframe duration. However, to provide additional levels of grayscale, differing durations of `on` time are utilized in these like subframes. Thus, all but one of these like-time subframes has a dead zone time during which the pixels are never activated. A clear circuit turns `off` the illuminated pixels during the dead zone time.

Description:
FIELD OF THE INVENTION 
     This invention relates to the field of pulse-width modulation for providing grayscale differentiation for displays. More particularly, the present invention is for a modified pulse-width modulation technique which provides very short `on` times without requiring a commensurate increase in electrical bandwidth. 
     BACKGROUND OF THE INVENTION 
     When displaying an image on a digital display, a pixel is either `on` or `off`. To formulate a more variable image it is desirable to provide selectable grayscale. Such increased variability can be used to provide more information or more realism in an image. For example, consider a display where an `on` pixel is white and an `off` pixel is black. To achieve an in-between state, eg., gray, the pixel can be toggled equally between `on` and `off`. The eye of the average viewer automatically integrates this toggled pixel to perceive a gray image rather than black or white. To achieve a lighter or darker gray, the duty cycle for toggling the pixel can be adjusted to be on more or less of the time, respectively. It is well understood that such grayscale techniques can also apply to color systems to formulate varying intensities of color. Nevertheless, to avoid unnecessarily obscuring the invention in extraneous detail, the remainder of this disclosure will only discuss whites, blacks and varying levels of grays. It will be understood that colors are also contemplated within the teachings of the present invention. 
     The technique described immediately above is known conventionally as pulse-width modulation (PWM). It is well known to implement a PWM scheme as either unweighted or weighted. FIG. 1 illustrates a conventional 3-bit unweighted scheme. According to the unweighted scheme a pixel cycle, commonly known as a frame, is divided into seven equal duration time slots, or subframes. The pixel can be activated during any number of the subframes from zero through seven. For typical frames, the intensity of the pixel is completely dependent upon the duration the pixel is `on`. The same intensity will be achieved when activating only a single subframe regardless of which of the subframes is used. Similarly, the same intensity will be achieved where four subframes are activated whether the first four, last four or alternating subframes are activated. Thus, in the system of FIG. 1, there are eight intensity levels ranging from having the pixel `off` in all the subframes to having the pixel `on` in all the time slots. 
     FIG. 2 illustrates a conventional weighted 8-bit PWM scheme. In a weighted scheme, each subframe has a distinct duration. In a conventional weighted scheme such as shown in FIG. 2, each subframe has twice the duration of the successive subframe. In this way, the intensity of the pixel can be selected using conventional binary counting. Thus, the scheme illustrated in FIG. 2 can select among 256 (0 to 255) levels of grayscale from black to white. In the general weighted case, the frame-time is divided into N subframes, with the duration of each subframe selected by the weight of the bit. In an N-bit system, the frame-time is weighted by 1/2 n  where n={0,N} and the sum of all intervals is 1/2+1/4+ . . . +1/2 N  =(2 N  -1)/2 N . The shortest duration subframe, corresponding to the least significant bit, is frame-time/(2 N  -1). 
     A digital display system includes a plurality of pixels arranged in an array of rows and columns. One conventional system includes 1024 rows of pixels, each having 1280 pixels arranged in columns. A row of 1280 registers is loaded with the display data. For a PWM system, shift registers are used to sequentially store the data for a row of pixels. Data can be fed into the shift registers serially or in parallel; for convenience, the serial case is considered. The time available for loading a row of data into the shift registers is Λ/(# of rows)/(# of columns). Therefore, the required data bus bandwidth for the electronics supplying data to the shift registers is (# of rows)(# of columns)/Λ. This means that the bandwidth of the data bus doubles for every bit of grayscale that is added to a system. It is well understood that the cost of a system can increase significantly with increased bandwidth. 
     If the duration of the shortest subframe is Λ, then the duration available for turning on the pixel is Λ/(# of rows of pixels), since rows are addressed sequentially. In addition, the operating frequency of a system that provides the control signals to such pixels must be (# of rows of pixels)/Λ (assuming the control timing for turning on the pixel is the same as for turning off the pixel). As the duration of the shortest subframe becomes smaller, the design of control circuitry with sufficient bandwidth becomes increasingly difficult. 
     It is well understood that the bandwidth cannot be reduced by simply lengthening the duration of all the subframes. Consider for example where a grayscale of 1/2 is desired. If the duration of the frame and appropriate subframe are sufficiently long, the displayed pixel(s) will appear to flicker rather than appear as an intermediate gray level. Thus, it is important that the display time for any of the subframes not be too long. 
     What is needed is a display system that provides grayscale using a weighted PWM scheme which does not flicker and without significantly increasing the bandwidth requirements of the associated control circuitry and data bus. 
     SUMMARY OF THE INVENTION 
     A display system uses a weighted PWM scheme to deliver control during a frame time for developing a plurality of grayscale levels in each of a plurality of pixels. Of all the weighted subframes, a predetermined number of the shortest subframes utilize a like subframe duration. However, to provide additional levels of grayscale, differing durations of `on` time are utilized in these like subframes. Thus, all but one of these like-time subframes has a dead zone time during which the pixels are not activated. A separate control signal recognized as a clear circuit turns `off` the illuminated pixels during the dead zone time. 
     In the preferred embodiment, the frame includes eight subframes. Each of the subframes is conditioned to activate the display for a unique duration. The first subframe turns its respective pixel `on` for a predetermined length of time and each subsequent subframe for one-half the duration of its immediate predecessor. However, each of the last four subframes, subframes 5, 6, 7 and 8, have a same duration, one to the other. To maintain the condition that each successive subframe has one-half the duration of its immediate predecessor, the subframes 6, 7 and 8, each have a dead zone in which the pixels are never turned on. The dead zone in subframe 6 is 1/2 the subframe duration. The dead zone in subframe 7 is 3/4 the subframe duration and the dead zone in subframe 8 is 7/8 the subframe duration. A clear circuit is provided which provides the necessary counting capability to turn off the illuminated pixels at the appropriate times during the subframes 6, 7 and 8. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a timing diagram for an unweighted PWM scheme in the prior art. 
     FIG. 2 shows a timing diagram for a weighted PWM scheme in the prior art. 
     FIG. 3 shows a timing diagram for a weighted PWM scheme according to the present invention. 
     FIG. 4 shows a block diagram of system architecture for implementing the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 3 shows a timing diagram for the weighted PWM scheme according to the present invention. The invention is directed toward developing a grayscale display capability in a digital display. A single frame time is illustrated in FIG. 3. In this preferred embodiment, there are eight subframes and thus eight bits of selectability for grayscale. This provides 256 unique gray levels from fully off to nearly fully on. As will be appreciated from the discussion below, because of certain features of this invention, a small portion of available light (about 6% in the preferred embodiment) will be lost. This is true even when all of the bits are `on`. 
     The most significant bit is provided first according to the preferred embodiment. The subframe for the first bit, Bit 0, has a duration for a predetermined amount of time. A similar weighted PWM scheme according to the prior art would have a duration for controlling the pixel for 50% of the frame time for Bit 0. In the present invention, Bit 0 controls the pixel for slightly more than 47% of the frame time. Bit 1 controls the pixel for 1/2 the duration of Bit 0. Similarly, Bit 2 controls the pixel for 1/2 the duration of Bit 1, Bit 3 controls for 1/2 of Bit 2, Bit 4 controls for 1/2 of Bit 3, Bit 5 controls for 1/2 of Bit 4, Bit 6 controls for 1/2 of Bit 5, and Bit 7 controls for 1/2 of Bit 6. 
     According to the preferred embodiment, each of the bits falls within one of eight subframes. Bit 0 through Bit 4 each entirely fill their respective subframes. If two of these bits are utilized to achieve a particular grayscale, the `off` signal at the end of the first such subframe is deactivated so that the pixel remains `on`. 
     As shown in FIG. 3, Bit 5 through Bit 7 each have the same subframe duration time as Bit 4. For Bit 5, the pixel receives a control signal to turn the pixel `off` 1/2 the way through the subframe. For Bit 6, the pixel receives a control signal to turn the pixel `off` 1/4 the way through the subframe. For Bit 7, the pixel receives a control signal to turn the pixel `off` 1/8 the way through the subframe. The portion of each of the subframes for Bit 5 though Bit 7 is a dead zone during which time no pixel is `on`. These dead zones do decrease the total amount of illumination available from each pixel by approximately 6%. However, because the time duration of bit 7 is maintained at the time duration of bit 4, the bandwidth of the control system need not operate at as high a frequency as would otherwise be necessary and does not need to be fed into the shift register as fast as would otherwise be necessary. 
     The following illustrates one example for achieving 8-bit grayscale with 5-bit timing. The technique can be generalized to N-bit grayscale timing with M-bit timing, where M&lt;N. It is assumed that the display is digital and has 1024 rows with 1280 columns operating at a 75 Hz frame rate. 
     To achieve 8-bit grayscale, 8 subframes are required corresponding to bits 0 through 7. The timing corresponds to 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128 and 1/256 of a total frame-time as described in the prior art. In actuality according to the teachings of the present invention, the frame is divided into eight subframes which correspond to 1/2, 1/4, 1/8, 1/16, 1/32, 1/32, 1/32 and 1/32. 
     The three least significant bits, Bit 5 through Bit 7, are generated by subdividing the last three subframes into 1/2, 1/4 and 1/8 of the 1/32 subframes to yield 1/64, 1/128 and 1/256, respectively. This occurs by turning off a row of pixels after it has been on 1/2, 1/4 and 1/8 of the 1/32 subframes. It will be apparent that some of the intensity is lost even when all bits are on: approximately 6%. 
     The 1/32 subframes (Bit 4 through Bit 7) defines the speed required for addressing, the time it takes to write 1024 rows, since it corresponds to the shortest subframe. The time required in this example for the 1/32 subframe is 
     
         t(1/32 bit)=(1/f)(32/34)(1/32) 
    
     For f=75 Hz, t=392 μs. The time allowed to write each row is then 
     
         t.sub.ROW =t/ρ; where ρ=number of pixels per row. 
    
     For this example with 1024 pixels per row, the timing is 383 ns per pixel. 
     For all grayscale bits, the time to address 1024 rows is 392 μs 
     FIG. 4 shows a block diagram of a display system according to the present invention. An array 100 of a plurality of discreet pixels is arranged in a plurality of rows 104 and columns 106. Each row contains a predetermined number of pixels. One commercially available display includes 1024 rows, each having 1280 pixels per row. Other sizes of displays are also available. 
     A control circuit 108 is coupled to load display data into a plurality of registers 110. There are the same number of registers 110 as pixels 102 in a row 104. In the preferred embodiment, the data is entered into a first register and shifted through the row of registers like a standard shift register. It is well known that other means for loading the registers can be used. The control circuit 108 is also coupled to a row select circuit 112. One function of the row select circuit is to condition the array 100 to transfer the display data from the registers 1 10 into a predetermined row 104 of pixels 102. 
     To display a particular grayscale image in a row, the data for Bit 0 for each pixel 102 in the selected row 104 is loaded into the registers 110. Once the data is loaded, the control circuit 108 generates a control signal to initiate the transfer of the data to the row 104 of pixels 102 that is selected by the row select circuit 112. The control circuit 108 also provides the row select circuit 112 information regarding which bit of the grayscale is being transmitted to the pixels 102 for display. 
     The row select circuit 112 incorporates a timer circuit 114 which counts down the desired duration of bit being displayed. Once the full duration has been displayed, the timer circuit 114 generates an off signal which is coupled to the appropriate row 104. Control logic 116 is incorporated in the timer circuit 114 which inhibits the off signal in the event two consecutive bits are required for the generation of a grayscale. Of course, the inhibit function does not operate for those bits that include a dead zone because the control logic of the timer circuit 114 has been programmed using digital circuitry to reserve bits 5,6, and 7 as bits that include a dead zone or are of partial duration. 
     The present invention has been described relative to a preferred embodiment. Improvements or modifications that become apparent to persons of ordinary skill in the art only after reading this disclosure are deemed within the spirit and scope of the application.