Abstract:
A parallel carry and carry propagation generator for use with a modulo-2 N-bit operand adder generates the required carry bits to complete the N-bit pair modulo-2 sums as a parallel operation. The logic structure has log 2  2N operation levels that allow for constant fan-in and fan-out design as well as static, rather than fixed-rate precharge/discharge, operation. A simplified version of the network is also suitable for use as a conditional sum selection controller for a conditional sum adder.

Description:
This is a continuation of application Ser. No. 07/820,304, filed Jan. 6, 1992, now abandoned. 
    
    
     FIELD OF INVENTION 
     The invention pertains to the field of arithmetic adder circuits and more specifically to binary adder networks. 
     BACKGROUND TO THE INVENTION 
     Binary adder networks are basic to digital computer arithmetic operation. Because of the large number of adder operations involved, the history of computer development shows a constant search for faster adder networks either through faster component technology or by improved network organization using various auxiliary logic or computing networks to augment the basic adder unit. 
     Early digital computers used ripple-carry adders in which the i th  adder output bit may be represented by the modulo-2 bit sum 
     
         S.sub.i =A.sub.i ⊕B.sub.i ⊕C.sub.i-1 
    
     where A i  and B i  are the i th  bit of the input operands, and C i-1  is the carry-in from the next lowest bit sum. The carry-in may be represented in terms of the prior stage operands (A i-1 , B i-1 ) and the prior stage carry-in, C i-2 , as C i-1  =A i-1  *B i-1  +C i-2  (A i-1  +B i-1 ) where (*,+) are Boolean (AND, OR) operators respectively. The time for the carry-bits to ripple through became the limiting factor in the speed of adders. Subsequent fixed-time adders were introduced to overcome these deficiencies. These fixed-time adders may be classified into two categories: conditional sum and carry-look-ahead (CLA) adders. 
     Conditional adders compute each bit sum, S i , twice: one sum, S Ni , based on the assumption that the carry-in bit, C i , is zero; a second sum, S Ei , on the assumption that C i  =1. FIG. 1 is the logic diagram of a 4-bit-slice conditional sum adder. (Ref. &#34;Introduction to Arithmetic&#34;, Waser and Flynn, Holt, Rinehart and Winston, 1982, p. 77ff). The two input operands are represented by input bits A 0 , A 1 , A 2 , A 3  and B 0 , B 1 , B 2 , B 3 , respectively. Each pair of operand bits (A i , B i ) are applied to input terminals 110. A 0 , B 0  correspond to the input operand least significant bit while A 3 , B 3  correspond to the most significant bits. The conditional sum adder consists of two basic sections: the conditional sum generator unit 130 that forms at its output the two sets of conditional sums and conditional carry, S N0 , S N1 , S N2 , S N3 , C N4  and S E0 , S E1 , S E2 , S E3 , C E4 , the latter group being based on the assumption of a non-zero carry-in to its corresponding individual conditional sum generator 141, 143, 145, 147, 149, respectively. These conditional signals are applied to conditional sum selector unit 150 consisting of the individual output selectors 161, 163, 165, 167, 169 corresponding to output sum bits S 0 , S 1 , S 2 , S 3  and output carry bit C4. The selection is controlled by the carry-in bit, C 0 , and its complement, C 0 , operating on the conditional sums by means of AND-gates 113 and OR-gates 115. 
     The logic equations governing the behavior of the conditional 4-bit slice adder of FIG. 1 are as follows: 
     
         S.sub.N0 =A.sub.0 ⊕B.sub.0 
    
     
         S.sub.E0 =S.sub.N0 
    
     
         S.sub.N1 =A.sub.1 ⊕B.sub.1 ⊕G.sub.0 
    
     
         S.sub.E1 =A.sub.1 ⊕B.sub.1 ⊕P.sub.0 
    
     
         S.sub.N2 =A.sub.2 ⊕B.sub.2 ⊕(G.sub.1 +T.sub.1 G.sub.0) 
    
     
         S.sub.E2 =A.sub.2 ⊕B.sub.2 ⊕(G.sub.1 +T.sub.1 P.sub.0) 
    
     
         S.sub.N3 =A.sub.3 ⊕B.sub.3 ⊕(G.sub.2 +T.sub.2 G.sub.1 +T.sub.2 T.sub.1 G.sub.0) 
    
     
         S.sub.E3 =A.sub.3 ⊕B.sub.3 ⊕(G.sub.2 +T.sub.2 G.sub.1 +T.sub.2 T.sub.1 P.sub.0) 
    
     
         C.sub.N4 =G.sub.3 +T.sub.3 G.sub.2 +T.sub.3 T.sub.2 G.sub.1 +T.sub.3 T.sub.2 T.sub.1 G.sub.0 
    
     
         C.sub.E4 =G.sub.3 +T.sub.3 G.sub.2 +T.sub.3 T.sub.2 G.sub.1 +T.sub.3 T.sub.2 T.sub.1 P.sub.0 
    
     where 
     G i  =A i  B i , 
     P i  =A i  B i , 
     T i  =A i  ⊕B i . 
     The true 4-bit sum and carry-out is selected by selector unit 150 in accordance in accordance with the following boolean equations: 
     
         S.sub.0 =S.sub.E0 C.sub.0 +S.sub.N0 C.sub.0 
    
     
         S.sub.1 =S.sub.E1 C.sub.0 +S.sub.N1 C.sub.0 
    
     
         S.sub.2 =S.sub.E2 C.sub.0 +S.sub.N2 C.sub.0 
    
     
         S.sub.3 =S.sub.E3 C.sub.0 +S.sub.N3 C.sub.0 
    
     
         C.sub.4 =C.sub.E4 C.sub.0 +C.sub.N4 
    
     The above concept could be extended to additional bits with the attendant increase in complexity implied by the above equations and by FIG. 1. 
     Carry-looks ahead (CLA) adders have been the most popular integrated circuit implementation in the recent past because of their simplicity and modularity. Modularity implies relative ease in extending the number of bits in each operand by the use of identical parallel units. 
     Consider, for example, the 4-bit slice CLA of FIG. 2. Comparison with FIG. 1, a 4-bit slice conditional adder, clearly shows the relative simplicity of the CLA. 
     The CLA sum may be expressed in the following logic expression as 
     
         S.sub.i =A.sub.i ⊕B.sub.i ⊕C.sub.i-1,  i=0, 1, 2, 3 
    
     and the CLA carry as 
     
         C.sub.i +A.sub.i B.sub.i +C.sub.i (A.sub.i +B.sub.i) 
    
     or 
     
         C.sub.i =G.sub.i +P.sub.i C.sub.i 
    
     where 
     
         G.sub.i =A.sub.i B.sub.i 
    
     and 
     
         P.sub.i =A.sub.i +B.sub.i 
    
     The above CLA sum expression can be immediately evaluated, absent the carry term (C i-1 ), by forming the EOR of the two operands (A i , B i ). The carry term, C i-1 , is a function of lower order indexed operands, (A i-1 , B i-1 ), and lower order carries, C i-2 . As a result, the time to complete an addition is generally governed by availability of the carry-in bit to each sum-bit. 
     The above expression for C i  is a recursive equation, i.e., one in which the current value, C i+1 , is a function of its own past values. It may be explicitly stated as follows: 
     
         C.sub.i+1 =G.sub.i +P.sub.i G.sub.i-1 +P.sub.i P.sub.i-1 G.sub.i-2 + . . . +P.sub.i P.sub.i-1 . . . P.sub.0 C.sub.0 
    
     Hence, for the four-bit case of FIG. 2, the major output carry, C4, may be expressed as 
     
         C.sub.4 =G.sub.3 +P.sub.3 G.sub.2 +P.sub.3 P.sub.2 G.sub.1 +P.sub.3 P.sub.2 P.sub.1 G.sub.0 +P.sub.3 P.sub.2 P.sub.1 P.sub.0 C.sub.0 
    
     By substituting the following into the above expression 
     
         G.sub.0 &#39;=G.sub.3 +P.sub.3 G.sub.2 +P.sub.3 P.sub.2 G.sub.1 +P.sub.3 P.sub.2 P.sub.1 G.sub.0 
    
     and P 0  &#39;=P 3  P 2  P 1  P 0  C 0  obtains C 4  =G 0  &#39;+P 0  &#39;C 0  which represents the logical expression for the G 0  &#39;,P 0  &#39; output terminals of FIG. 2. 
     If two networks of the type shown in FIG. 2 were to be used as a modular units for generating an 8-bit sum, the carry-in bit to the higher order 4-bit network, C4, would have to be formed in accordance with the above expression. The output carry of the higher order unit, C8, would then be expressible as 
     
         C.sub.8 =G.sub.1 &#39;+P.sub.1 &#39;G.sub.0 &#39;+P.sub.1 &#39;P.sub.0 &#39;C.sub.0 
    
     where G&#39; 1  and P&#39; 1  are the CLA output pair of the next higher order CLA modular unit. 
     Modularity was extended by means of a four group CLA generator that accommodated four CLA 4-bit slice adders and produced at output the necessary carry information, i.e., C 4 , C 8 , C 12  and P&#34;, G&#34;, to form a 16-bit CLA adder using four modular adder units of the type shown in FIG. 2. FIG. 3 shows a four group CLA generator with four input pairs, (G&#39; 0 ,P&#39; 0 ), (G&#39; 1 ,P&#39; 1 ), (G&#39; 2 ,P&#39; 2 ) and (G&#39; 3 ,P&#39; 3 ) and carry outputs corresponding to C 4 , C 8 , C 12  and (P&#34;, G&#34;), where 
     
         G.sub.12 =G&#39;.sub.2 +P&#39;.sub.2 G&#39;.sub.1 +P&#39;.sub.2 P&#39;.sub.1 G&#39;.sub.0 +P&#39;.sub.2 P&#39;.sub.1 P&#39;.sub.0 C.sub.0 
    
     and 
     
         G&#34;=G&#39;.sub.3 +P&#39;.sub.3 G&#39;.sub.2 +P&#39;.sub.3 P&#39;.sub.2 P&#39;.sub.1 C.sub.0 
    
     
         P&#34;=P&#39;.sub.3 P&#39;.sub.2 P&#39;.sub.1 P&#39;.sub.0 
    
     Thus, the most significant carry-out bit, C16, could be logically formed as 
     
         C.sub.16 =G&#34;+P&#34;C.sub.0 
    
     and passed on, as needed, to higher order modular CLA adder units. 
     FIG. 4 shows the logical extension of modular CLA concept to 64-bit addition. A total of sixteen modular 4-bit slice SLA adders 200 are arrayed in parallel to accept input operand pairs, (A 0 , B 0 ) . . . (A 3 , B 3 ), (A 4 , B 4 ) . . . (A 7 , B 7 ), . . . , (A 60 , B 60 ) . . . (A 63 , B 63 ) and carry-in bits, (C 0 , C 16 , C 32 , C 48 ), each producing 4-bit output sums, (S 0 , S 1 , S 3 ) . . . (S 60 , S 61 , S 62 , S 63 ) and carry-generate/carry-propagate pairs (P&#39; 0 ,G&#39; 0 ), . . . (P&#39; 15 ,G&#39; 15 ). 
     A second logical level of four modular four group CLA generators 250, each accepting the carry output information of a corresponding group of four CLA adders 200, generates the necessary carry information for its associated adders 200 from the four pairs of carry-generate/carry-propagate pairs and the necessary carry-generate/carry-propagate pairs, [(P&#34; 0 ,G&#34; 0 ), (P&#34; 1 ,G&#34; 1 ), and (P&#34; 2 ,G&#34; 2 )], from which the third logic level consisting of a single CLA generator 250 generates the three additional carry-in bits, (C 16 , C 32 , C 48 ) supplied to the first and second levels. In this manner, modular 4-bit slice CLA adders have been used to accommodate higher precision operation. 
     Also, the basic conditional adder unit of FIG. 1 may be used as a modular adder and extended to higher precision addition by using the CLA generator concept because the logic equations defining the higher order carries are similar. For example, it may be shown (op cit Waser and Flynn) that the second level conditional same carries may be expressed as 
     
         C.sub.4 =C.sub.N4 +C.sub.E4 C.sub.0 
    
     
         C.sub.8 =C.sub.N8 +C.sub.E8 C.sub.N4 +C.sub.E8 C.sub.E4 C.sub.0 
    
     
         C.sub.12 =C.sub.N12 +C.sub.E12 C.sub.N8 +C.sub.E12 C.sub.E8 C.sub.N8 +C.sub.E12 C.sub.E8 C.sub.E4 C.sub.0 
    
     Because the logic required to implement the above expressions is identical to that of the CLA generator 250 of FIG. 3 and 4, a 16-bit adder may be implemented as shown in FIG. 5. The adder has four conditional adders 100 connected in parallel, each accepting 4-bit pairs of operands. Each adder 100 consists of a conditional sum generator 130 and a multiplexor 150. The modular group carry-out pairs, [(C N4 , C E4 ), (C N8 , C E8 ), (C N12 , C E12 )], are supplied to CLA generator 250 which produces the modular carry-in bits (C4, C8, C12) required to form the sixteen bit addition. The extension required to accommodate more bits clearly indicated by the CLA method previously discussed. 
     Because of the need for cost effective parallel fast adders, it is highly desirable that the number of processing steps required to generate the carry-bits (and hence the sum) be proportional to the logarithm of the number of bits in each operand, and at a relatively low-cost. Also, a logic structure that allows constant fan-in and fan-out and permits static versus fixed rate pre-charge/discharge operation is desirable. The present invention is designed to achieve these goals. 
     SUMMARY OF THE INVENTION 
     A parallel N-bit binary adder network is described comprising a multiplicity of parallel modulo-2 adders, each accepting and summing corresponding operand bit pairs and a final sum carry input. The final sum carry bits are generated in parallel by a carry generating network that comprises a parallel carry propagation logic array for generating carry propagation terms based on the logical OR-ing of pairs of input operand bits, a carry generation logic network based on AND-ing of pairs of input operand bits, and a logic array for operating on the carry generating and propagation terms, in parallel for producing a set of final sum carry terms that are fed in parallel to the modulo-2 parallel adders, or by using the most significant carry bit for selecting one of two sums in a conditional sum adder. The number of gate delays for generating the final set of N sum carry inputs to the modulo-2 adder is [log 2  2N], providing a substantial increase in adder throughput. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a logic diagram of a prior art 4-bit slice conditional sum adder. 
     FIG. 2 is a logic diagram of a prior art 4-bit slice carry-look-ahead (CLA) adder. 
     FIG. 3 is a logic diagram of a prior art four group CLA generator. 
     FIG. 4 is a block diagram of a prior art 64-bit adder using full CLA. 
     FIG. 5 is a block diagram of a prior art 16-bit conditional sum adder using a four group CLA generator. 
     FIG. 6 is a flow diagram of a four-bit carry process. 
     FIG. 7 is a flow diagram of an eight-bit carry process. 
     FIG. 8 is a flow diagram of a sixteen-bit carry process. 
     FIG. 9 is a logic diagram for a typical carry generator node implementation. 
     FIG. 10 is a block diagram of an 8-bit carry generator. 
     FIG. 11 is a logic diagram for an 8-bit propagation generator. 
     FIG. 12 is a logic diagram for a one-bit adder with carry input. 
     FIG. 13 shows a block diagram of a complete parallel adder. 
     FIG. 14 shows the structure of an m-bit two-level carry generator module. 
     FIG. 15 shows the interconnections for a 16-bit carry-generator using 4-bit two-level modules. 
     FIG. 16 shows the partitioning of a 16-bit first and second level carry-generate matrix for use with 4-bit two-level modules. 
     FIG. 17 shows the partitioning of a 16-bit third and fourth level carry-generate matrix for use with 4-bit two-level modules. 
     FIG. 18 shows the interconnections for a 64-bit carry-generator using 8-bit two-level modules. 
     FIG. 19 shows a modular 24-bit using three 8-bit conditional adder networks. 
     FIG. 20 shows the flow diagram of a simplified 4-bit carry generator with an input carry-bit. 
     FIG. 21 shows a block diagram of a 4-bit carry generator corresponding to FIG. 20. 
     FIG. 22 shows the flow diagram for a simplified 8-bit carry generator. 
     FIG. 23 shows a block diagram of an 8-bit carry generator corresponding to FIG. 22. 
     FIG. 24 shows a block diagram of a simplified propagation generator. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The sum, S, of two N-bit binary number operands (A,B) where 
     
         A=A.sub.N-1, A.sub.N-2, . . . , A.sub.0 
    
     
         B=B.sub.N-1, B.sub.N-2, . . . , B.sub.0 
    
     may be expressed as 
     
         S=S.sub.1, S.sub.N-2, . . . , S.sub.0 
    
     
         where 
    
     
         S.sub.i =A.sub.i ⊕B.sub.i ⊕C.sub.i-1 
    
     represents the value of the i th  sum bit expressed as the modulo-2 sum of the i th  operand bit values (Ai, Bi) and the carry-in bit Ci-1, from the modulo-2 sum of the next least significant bit pair (A i-1 , B i-1 ). Thus, by using the boolean logic operators (*) for &#34;AND&#34; and (+) for &#34;OR&#34;, the carry bits may be expressed as ##EQU1## 
     For convenience, let 
     
         G.sub.i =A.sub.i *B.sub.i 
    
     
         P.sub.i =A.sub.i +B.sub.i 
    
     so that the above carry bit expression become ##EQU2## (Note that for further convenience, the explicit &#34;AND&#34; operator symbol has been omitted so that P i  C i  ≡P i  * C i ). This convention will be used throughout the following description. 
     The above recursive expressions may be expanded as follows: ##EQU3## 
     This set of equations may, in turn, be expressed in matrix form as ##STR1## or simply 
     
         c=P.sup.(N) g 
    
     where 
     c is the carry column vector, 
     g is the carry generator column vector, and 
     P.sup.(N) is the lower triangular NXN carry propagation matrix. 
     Thus, g=[G 0  G 1  G 2  . . . G N-1  ] T  =[A 0  B 0  A 1  B 1  A 2  B 2  . . . A N-1  B N-1  ] T  represents the &#34;AND&#34;-ing of operand bit pairs which generate a carry-out when high. Matrix P, whose elements represent propagation control variables, describes the means by which the carry-outs are propagated to and through higher order bits. 
     Significantly, the P-matrix may be factorized into the product of sparse lower triangular matrices. For example, ##EQU4## 
     Thus, at each binary increment, 2 k  ≦r&lt;2 k+1 , P.sup.(r) is factorizable into (k+1) lower triangle matrices of the form shown. These factorized equations may be represented by the flow diagrams of FIGS. 6, 7 and 8. 
     FIG. 6 corresponds to the four-bit carry generation process represented by the factorization of P.sup.(4). The input to the process consists of the carry-generator vector, [G 0  G 1  G 2  G 3  ] T  shown at the bottom. The diagonal lines with arrow-heads correspond to multiple (&#34;AND&#34;) operations on the data of the node of origin by the corresponding labelled expression. Unlabeled vertical lines between nodes represent transmission paths with no modification of data transmitted from a lower node to a higher node. All nodes are summing (&#34;OR&#34;) junctions. For example, C 1  =G 1  +P 1  G 0  and C 3  =P 3  P 2  (G 1  +P 1  G 0 )+(G 3  +P 3  G 2 )=P 3  P 2  P 1  G 0  +P 3  P 2  G 1  +P 3  G 2  +G 3 . The carry-out vector, [C 0  C 1  C 2  C 3  ] T , is represented by the values present at the upper output nodes. 
     FIGS. 7 and 8 show flow diagrams for P.sup.(8) and P.sup.(16), respectively representing 8 and 16 bit carry generation processes. Clearly, flow diagrams for greater number of bits may be generated in a similar fashion by extending the principles expounded. 
     For each binary increment, 2 k  ≦r≦2 k+1  -1, or for each doubling of the number of bits used in the operands, one additional sparse lower triangular matrix is required to represent the factorized form of the P.sup.(r) matrix. Thus, for 2≦r≦3, P.sup.(r) factors into 2 matrices; for 4≦r≦7, P.sup.(r) factors into 3 matrices, and for 2 k  ≦r≦2 k+1  -1, P.sup.(r) factors into (k+1) matrices. 
     Each factorized matrix operation corresponds to a row of nodes shown in FIGS. 6, 7, and 8. The lowest (zero) level nodes correspond to the input carry generate vector values, g. The values at the next level of nodes corresponds to the column vector that would obtain if the extreme right hand factorized matrix of the examples given above were to operate on the input generate vector, g. Similarly, the second level of nodes has values corresponding to that which would obtain if the second most extreme right had factorized matrices operated on the vector resulting from product to its right. And so on for succeeding levels. 
     In general, k+1 factorized matrices (stages) are required for 2 k+1  bits in each operand, i.e., [log 2  N] stages for N-bit operands. 
     The flow diagrams of FIGS. 6, 7 and 8 also imply the logic network structures shown in FIGS. 9 through 11. 
     FIG. 9 represents a typical nodal processor 10 located at, say, node l, k of FIG. 8 producing G l ,k at its output. Processor 10 accepts as input operands G l-1 , k-2 l-1 , G l-1 ,k and P k  P k-1  . . . P k-2 .spsb.l-1 at its input terminals 11, 12 and 13 respectively. &#34;AND&#34;-gate 16 and &#34;OR&#34;-gate operate on these inputs to produce at output 14 the boolean function 
     
         G.sub.l,k =G.sub.l-1,k +P.sub.k P.sub.k-1 . . . P.sub.k-2.spsb.l-1 G.sub.l-1,k-2.spsb.l-1 
    
     FIG. 10 is an embodiment of an 8-bit carry generator having four rows (0-3) and 8 columns (0-7). Rows 1 through 3 comprises 7, 6 and 4 nodal processors 10, respectively, each of the type depicted in FIG. 9. Row 0 comprises 8 AND-gates 20 arranged to accept at input terminals 301 corresponding operand bit pairs, {A k , B k  }, forming G 0 ,k =A k  *B k  and supplied to processors 10 on line 11. The processors 10 of row 1 also accept the seven propagation variable P 1 , through P 7  on input lines 305. Propagation variable P k  being applied as an input to processor 10 located at row 1, column k on line 13 together with G 0 ,k-1 supplied by lines 12. The output of processor 10 located at 1,k is 
     
         G.sub.1,k =G.sub.0,k +PkG.sub.0,k-1 
    
     In a similar manner, processors 10 of row 2 are supplied the outputs of row 1 together with propagation variable P 21  through P 76  from input line 307. The output of processor 10 located at 2, k is 
     
         G.sub.2,k =G.sub.1,k +P.sub.k P.sub.k-1 G.sub.1,k-2 
    
     Processor 10 at location 3, k in a similar manner generates an output 
     
         G.sub.3,k =G.sub.2,k +P.sub.k P.sub.k-1 P.sub.k-2 P.sub.k-3 G.sub.2,k-4 
    
     from inputs provided by lower level processors and propagation variable P 4  P 3  P 2  P 1  through P 7  P 6  P 5  P 4  supplied on input lines 309. 
     Carry output C 0  is available directly from AND-gate 20 at location 0,0 on line 303; C 1  from output line 14 of processor 10 at location 1,1; C 2  and C 3  from processors 10 at location 2,2, and 2,3 respectively; and C 4  through C 7  from row 3 processor 10 outputs. 
     It is clear, by reference to the flow diagrams of FIGS. 6, 7 and 8 and carry generator 300 of FIG. 10, that the architecture and organization of the 8-bit carry generator 300 may be expanded indefinitely adding an additional row each time the number of bits in each operand is doubled. The number of parallel processors required in each row is summarized in Table I. 
     
                       TABLE I______________________________________Operand BitsRow     4          8     16       32  64______________________________________0       4          8     16       32  641       3          7     15       31  632       2          6     14       30  623                  4     12       28  604                         8       24  565                                 16  486                                     32______________________________________ 
    
     FIG. 11 is a logic circuit for implementing an 8-bit propagation generator suitable for supplying propagation variables to the 8-bit carry generator of FIG. 10. Propagation generator 400 comprises 7 OR-gates 40 in row 0 used to form propagation variables P 1 , P 2 , . . . P 7  from input operand bit pairs {A k , B k  } as follows: 
     
         P.sub.k =A.sub.k +B.sub.k 
    
     The set, {P k  }, is available on output lines 305. Subsequent rows are comprised of AND-gates 50. The k th  AND-gate of row 1 accepts the k th  and k-1 th  output of row 0 to form, at its output 307, P k  P k-1 . Similarly, the kth processor of row 2 accepts the k th  and k-2 th  output of row 1 to form the set of propagation variables, {P k  P k-1  P k-2  P k-3  }, provided at output 309. 
     Clearly, the organization and architecture of processor 400 may be extended to accommodate more operand bits by extending the structure of FIG. 11 to the left and adding an additional row of AND-gates 50 each time the number of input operand bits are doubled. The number of gates required per row are indicated in Table II. 
     
                       TABLE II______________________________________Operand BitsRow     4          8     16       32  64______________________________________0       3          7     15       31  631       2          6     14       30  622                  4     12       28  603                         8       24  564                                 16  485                                     32______________________________________ 
    
     FIG. 12 represents a logic network 60 for forming the complete bit sum of two operand bits (A k , B k ) and a carry-in bit, Ck, comprising exclusive-or (EOR) networks 61 and 62. EOR network 61 forms the modulo-2 sum A k  ⊕B k  and network 62 produces at its output 
     
         S.sub.k =A.sub.k ⊕B.sub.k ⊕C.sub.k-1 
    
     Based on the preceding description of summer network 60, carry generator 300 and propagation generator 400, a complete parallel binary adder may be defined as shown in FIG. 13, organized to accept two N-bit operands; 
     
         A=A.sub.0 A.sub.1 A.sub.2 . . . A.sub.N-1 
    
     
         B=B.sub.0 B.sub.1 B.sub.2 . . . B.sub.N-1 
    
     Operands A and B are applied to the inputs of propagation generator 400, carry generator 300 and sum unit 500. Propagation generator 400 and carry generator 300 are configured in accordance with the prior description. Sum unit 500 comprises N one-bit plus carry-in bit EOR networks 60, each as described in FIG. 12. The carry-in to each EOR network 60 is provided by the appropriate output terminal of carry generator 300. Propagation variables are provided to carry generator 300 by propagation generator 400 as determined by the two input operands A and B. The output of sum unit 500 is 
     
         S=S.sub.0 S.sub.1 . . . S.sub.N-1 
    
     
         where 
    
     
         S.sub.k =A.sub.k ⊕B.sub.k ⊕C.sub.k-1 
    
     Note that carry C N-1  is available at the output as an overflow bit of for use in extending the number of bits in the operands A and B. 
     The preferred implementation of carry generation 300 uses modular medium scale integrated circuit technology. For example, by properly sub-sectioning the flow graph of FIG. 8 into seven subsections as shown by the dotted outlines, a 4-bit wide and 2-level deep module may be defined that forms the basis for a modular building-block approach to the circuit implementation. The 4-bit wide partitioning is somewhat arbitrary and is mainly chosen for purposes of explanation because it probably represents the lowest level of modularization that allows the principle of modularity to be described. 
     FIG. 14 is a block diagram of an m-bit wide, 2-level module 500 comprising two layers of m nodal processors 10 of the type shown in FIG. 9. Five sets of m-input lines are accommodated: inputs 501 accept the corresponding I-level outputs, {G l ,k }; inputs 503 accept the I-level outputs displaced by 2 I-1 , {G l ,k-2 I-1  }; inputs 505 and 507 accept the propagation carry-terms ##EQU5## respectively; and inputs 509 accept the (I+1) th  inner layer output terms (displaced by 2 I ), {G I+1 ,k-2 I  }. 
     Two sets of output lines are provided: outputs 511 correspond to the first layer output terms, {G I+1 ,k }; and outputs 513 are the second layer (or module) outputs, {G I+2 ,k }. 
     FIG. 15 is an interconnection diagram for a carry generator 300 using 4-bit wide (m=4) 2-layer modules 500. Each logic unit 520 represents a set of four unit 20 AND-gates used to form {G k  }. 
     FIG. 15 may be best understood by referring to FIG. 16 that shows the matrix equation relating the zero level (I=0) inputs, {G 0 ,k }, to the second level (I=2) outputs, {G 2 ,k }, and to FIG. 17 showing the matrix equation relating the second level outputs to the fourth level outputs, {G 4 ,k }. In FIG. 16, the two 16×16 matrices (P 1 .sup.(16), P 2 .sup.(16)) are each partitioned into 16 4×4 submatrices. Each non-zero valued submatrix corresponds to a single layer 4-bit wide operation performed within a 500 module. The submatrices of the right-hand matrix correspond to first layer operations while those in the left-hand matrix correspond to the second layer operations previously described. Similarly, the right hand set of submatrices in FIG. 17 corresponds to third level (I=3) operations and the left set corresponds to fourth level (I=4) operations. These equations provide interconnect information by relating the individual module 500 inputs to their outputs. 
     For example, consider the input/output relationship of module 500 in the first row of FIG. 15 identified by coordinates (1,3). ##EQU6## 
     This latter equation expresses the required inputs to module 500 (1,3): the first expression on the right implies only two non-zero products ##EQU7## thus requiring ##EQU8## as inputs; the second expression requires ##EQU9## and the third requires the input quadruplet [G 0 ,8 G 0 ,9 G 0 ,10 G 0 ,11 ] T , and the triplet ##EQU10## Summarizing, the required inputs are: G 0 ,8-11, G 1 ,6-7, G 0 ,7, and ##EQU11## as shown in FIG. 15. (Please note that for FIG. 15, the output carries, {C k  }, are equal to {G 4 ,k }.) 
     A similar analysis for module 500 (2,4) results in the following expression: ##EQU12## The interconnections shown in FIG. 15 for module 500 (2,4) result. 
     FIG. 18 shows a simplified interconnection diagram for a 64-bit carry generator using 3-layers of 8-bit wide two layer modules. Specific details of the interconnections may be obtained by partitioning the carry-generator 300 matrices in the same manner as shown for the 4-bit wide two layer example. For the 64-bit case, however, three sets of equations, corresponding to the three layers of FIG. 18, must be used. 
     Another preferred embodiment using a slightly different concept of modularity is shown in FIG. 19. For purposes of explanation, a 24-bit adder network is shown comprising: three 8-bit conditional adder networks 141 each accepting two eight bit operands [(A 0-7 , B 0-7 ), (A 8-15 , B 8-15 ), (A 16-23 , B 16-23 )], and each outputting two conditional 8-bit sums (S E , S N ) as previously described in FIG. 1; multiplexer units 160 for selecting the S E  or S N  output of each conditional adder unit which is controlled by a two state carry signal; carry and propagation generator units 600 each comprising a carry generator 300&#39; and propagation generator 400&#39; for accepting two 8-bit operands and producing at its output the highest carry, say C 7 , out of a possible set of (C 0 , C 1 , . . . , C 7 ) for controlling its associated 2:1 MUX 160. Note that the lowest order (extreme right) MUX 160 is shown dotted so as to indicate that modularity consideration may require that each 8-bit conditional adder 141 be packaged with an associated MUX 160, in which case its control but would be set low because the absence of an input carry makes the S N  output always valid. In effect, each of the three vertical grouping of units 141, 160 and 600 constitute a modular adder and carry-out generator 700 requiring its associated two fields of operand bits and carry-in bit. The tandem ensemble of these units makes-up the complete adder. The output sum is represented by the 25-bit sum S 0-7 , S 8-15 , S 16-23 , S 24 . 
     In order to accommodate the carry-in bits (C-1, C7, C15) to units 600, a slight modification of the basic matrix and flow diagram must be made. Consider, the unit 600 shown on the extreme right of FIG. 19. The requisite matrix has the form ##STR2## Note that if the carry-in, C -1 , is zero (non-existent), the first row and column are effectively zero. Also, P 0  =C -1  so that P 0  and all its product terms vanish if C -1  =0. Thus, when C -1  =0, networks 300 and 400 are as previously defined. If C 1  =1, then the form of the matrix, carry-generator network 300 and propagation generator 400 have the same logic structure as previously described. 
     For example, FIG. 20 shows the flow diagram corresponding to a 4-bit carry-generator 300 with an input carry bit C -1 , suitable for concatenating 4-bit conditional adder units in a similar fashion to that shown for 8-bit conditional adder units 141 in FIG. 19. The necessary steps required for generating the output carry, C 3 , are shown by solid lines while the dotted-lines represent the other possible, but not required, processing steps previously shown. This implies the carry-out generator structure 300&#39; shown in FIG. 21 using processing modules 10. 
     FIG. 22 and FIG. 23 are the corresponding flow diagram and simplified carry-out generator structure 300 for an 8-bit unit respectively, as used in the adder network of FIG. 19. 
     FIG. 24 shows a simplified block diagram for propagation generator 400&#39; suitable for use with the 8-bit adder module 700 of FIG. 19. The subset of propagation terms required the 4-bit carry-out generator 300&#39; (P 3  P 2  P 1  P 0 , P 3  P 2 , P 3 , P 1 ) is also available from this unit. 
     The same flow diagram and logic networks are applicable to all concatenated units 600 of FIG. 19. However, in the case of the lowest significant unit 600 at the extreme right of FIG. 19, the carry-in from the previous stage is non-existent so that C -1  =0. For the other stages, the carry-out of the previous section is used as the carry-in. 
     Clearly, the concept of modular carry propagation for extended operand precision, an example of which is shown in FIG. 19 is adaptable to the use of 4, 8, 16, . . . or any other size modular bit units by implementing units 600, 160 and 141 for the word size desired. Also, mixed systems in which associated units 600, 160, and 141 of a given 700 section, are of the same word size, but not necessarily the same word size the other 700 units tandemly connected with it, can be constructed. 
     These and other similar variations will become apparent to those versed in the art.