Abstract:
A CMOS image sensor and a method of manufacturing the same are provided. The CMOS image sensor includes a semiconductor substrate including a plurality of photodiodes and a plurality of transistors, a first interlayer dielectric formed on the semiconductor substrate, a metal wiring and a second interlayer dielectric formed on the first interlayer dielectric, a plurality of color filter layers formed in the trenches formed in the second interlayer dielectric, and a plurality of micro lenses formed on the plurality of the color filter layers.

Description:
RELATED APPLICATION(S) 
       [0001]    This application claims the benefit under 35 U.S.C. § 119(e) of Korean Patent Application No. 10-2005-0132367 filed Dec. 28, 2005, which is incorporated herein by reference in its entirety. 
       FIELD OF THE INVENTION 
       [0002]    The present invention relates to an image sensor and a method of manufacturing the same. 
       BACKGROUND OF THE INVENTION 
       [0003]    An image sensor is a semiconductor device for converting an optical image into electrical signals, and a CCD (charge coupled device) is a type of semiconductor device in which individual MOS (Metal-Oxide-Silicon) capacitors are very closely positioned to each other and charge carriers are stored in the capacitor and transferred. 
         [0004]    A complimentary metal oxide semiconductor (CMOS) image sensor is a device that employs a switching mode to sequentially detect an output by providing MOS transistors corresponding to the number of pixels through a CMOS technology that uses peripheral devices, such as a control circuit and a signal processing circuit. 
         [0005]    CCDs have a complicated driving manner and high power consumption while requiring multi-step mask processes, so the manufacturing of CCDs is complicated. Moreover, the signal processing circuit cannot be realized within a single CCD chip. Recently, research has been conducted on developing a CMOS image sensor utilizing sub-micron CMOS technology to overcome the defects of CCDs. 
         [0006]    A CMOS image sensor realizes an image by sequentially detecting signals by means of a switching mode through forming a photodiode and a MOS transistor within a unit pixel. 
         [0007]    Since the CMOS image sensor is manufactured by using the CMOS manufacturing technology, the power consumption is small and the number of required masks is about 20, compared with a CCD manufacturing process requiring about 30-40 masks. In addition, a CMOS image sensor can be formed as a device in one chip including various signal processing circuits. Thus, CMOS image sensors have been spotlighted as the next generation image sensors and can be applied to various fields including DSCs (digital still cameras), PC cameras, and mobile cameras. 
         [0008]    The CMOS image sensor can be classified as a 3T type CMOS image sensor, a 4T type CMOS image sensor, or a 5T type CMOS image sensor, according to the number of the transistors formed in a unit pixel. The 3T type CMOS image sensor includes one photodiode and three transistors, and the 4T type CMOS image sensor includes one photodiode and four transistors. A description of the lay-out of a unit pixel of the 3T type CMOS image sensor follows. 
         [0009]      FIG. 1  is an equivalent circuit diagram of the conventional 3T type CMOS image sensor, and  FIG. 2  is a lay-out of a unit pixel of the conventional 3T type CMOS image sensor. 
         [0010]    Referring to  FIG. 1 , the unit pixel of the 3T type CMOS image sensor includes one photodiode PD and three nMOS transistors T 1 , T 2  and T 3 . The cathode of the photodiode PD is connected to the drain of the first nMOS transistor T 1  and the gate of the second nMOS transistor T 2 . 
         [0011]    The sources of the first and second NMOS transistors T 1  and T 2  are connected to a standard voltage VR supplying an electric source line. The gate of the first NMOS transistor T 1  is connected to a reset signal RST supplying reset line. 
         [0012]    The source of the third NMOS transistor T 3  is connected to the drain of the second nMOS transistor, and the drain of the third nMOS transistor T 3  is connected to a reading circuit (not shown in the drawings) through a signal line. The gate of the third NMOS transistor T 3  is connected to a thermal selecting line to which a select signal (SLCT) is supplied. 
         [0013]    Therefore, the first NMOS transistor T 1  is called a reset transistor Rx, the second nMOS transistor T 2  is called a drive transistor Dx, and the third NMOS transistor T 3  is called a select transistor Sx. 
         [0014]    Referring to  FIG. 2 , a unit pixel of the 3T type CMOS image sensor includes one photodiode  20  formed at a wide portion of an active area  10  among the defined active area  10 , and three gate electrodes of transistor  120 ,  130  and  140  formed while overlapping the remaining active area  10 . 
         [0015]    That is, a reset transistor Rx is formed by the first gate electrode  120 , a drive transistor Dx is formed by the second gate electrode  130 , and a select transistor Sx is formed by the third gate electrode. 
         [0016]    Impurity ions are implanted onto the active area  10  of each transistor to form a source/drain region on each transistor. 
         [0017]    A power source voltage Vdd is applied to the source/drain region between the reset transistor Rx and the drive transistor Dx. The source/drain region at one side of the select transistor Sx is connected to a reading circuit. 
         [0018]    The gate electrodes  120 ,  130  and  140  are connected to each signal line, and the signal line includes a pad at one terminal to be connected to an exterior driving circuit. 
         [0019]      FIG. 3  is a cross-sectional view of the conventional CMOS image sensor. 
         [0020]    Referring to  FIG. 3 , a p− type epitaxial layer  101  is shown on a p++ type semiconductor substrate  100 , which has an isolation region and an active area (a photodiode region and a transistor region) defined. A field oxide layer  102  is formed on the isolation region for isolating regions corresponding to input regions of green light, red light and blue light. An n− type diffusion region  103  is formed at the photodiode region of the semiconductor substrate  100 . 
         [0021]    A gate electrode  105  is formed on the transistor region of the semiconductor substrate  100  with a gate insulating layer  104  formed there between. Also, insulating layer sidewalls  106  are formed at both side walls of the gate electrode  105 . 
         [0022]    A first interlayer dielectric  108  is formed on the semiconductor substrate  100  including the gate electrode  105 , and various metal wirings  109  are formed with a predetermined interval on the first interlayer dielectric  108 . 
         [0023]    A second interlayer dielectric  110  is formed to a thickness of about 4000 Å on the semiconductor substrate  100  including the metal wiring  109 , and a nitride layer  111  is formed on the second interlayer dielectric  110 . A color filter layer  112  of red (R), green (G) and blue (B) color filters corresponding to each n− type diffusion region  103  is formed on the nitride layer  111 . 
         [0024]    A planarizing layer  113  is formed on the semiconductor substrate  100 , including each color filter layer  112 . Also, a microlens  114  is formed on the planarizing layer  113  corresponding to each color filter layer  112 . 
         [0025]    Reference number  107  represents an impurity region of the source and drain. 
         [0026]    The above-described CMOS image sensor includes a color filter layer  112  formed on a plurality of interlayer dielectrics and a nitride layer. It also includes a planarizing layer  113  formed on the substrate including the color filter layer  112  and a microlens formed on the planarizing layer  113 . The focal distance from the microlens  114  to the photodiode region is lengthened due to the many layers between the micro-lens  114  and the photodiode region. Therefore, cross-talk between neighboring pixels and a reduction of the photo-sensitivity may occur. 
       BRIEF SUMMARY 
       [0027]    An object of embodiments the present invention is to provide a CMOS image sensor of which cross-talk between neighboring pixels can be minimized or prevented and of which sensitivity can be improved by reducing the distance from a microlens to a photodiode region and a method of manufacturing the same. 
         [0028]    Accordingly, there is provided a CMOS image sensor comprising a semiconductor substrate including a plurality of photodiodes and a plurality of transistors, a first interlayer dielectric formed on the semiconductor substrate, a metal wiring and a second interlayer dielectric formed on the first interlayer dielectric, a plurality of color filter layers formed on the second interlayer dielectric and a plurality of micro lenses formed on the plurality of color filter layers. 
         [0029]    There is also provided a CMOS image sensor comprising: a semiconductor substrate including a plurality of photodiodes and a plurality of transistors; a first interlayer dielectric formed on the semiconductor substrate; a metal wiring; a plurality of color filter layers and a second interlayer dielectric formed on the first interlayer dielectric; and a plurality of micro lenses formed on the plurality of the color filter layers. 
         [0030]    There is also provided a method of manufacturing a CMOS image sensor comprising the steps: of forming a plurality of photodiodes and a plurality of transistors on a semiconductor substrate; forming a first interlayer dielectric on the semiconductor substrate including the plurality of the photodiodes and the plurality of the transistors; forming a metal wiring on the first interlayer dielectric; forming a second interlayer dielectric on the first interlayer dielectric and the metal wiring; forming a trench in the second interlayer dielectric; forming a plurality of color filter layers in the trench; and forming a plurality of micro lenses on the plurality of the color filter layers. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0031]      FIG. 1  is an equivalent circuit diagram of the conventional 3T type CMOS image sensor. 
           [0032]      FIG. 2  is a lay-out illustrating a unit pixel of the conventional 3T type CMOS image sensor. 
           [0033]      FIG. 3  is a cross-sectional view of the conventional CMOS image sensor. 
           [0034]      FIG. 4  is a cross-sectional view of a CMOS image sensor according to an embodiment of the present invention. 
           [0035]      FIGS. 5A &amp; 5B  are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an embodiment of the present invention. 
           [0036]      FIG. 6  is a cross-sectional view of a CMOS image sensor according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0037]    Hereinafter, a CMOS image sensor and a method of manufacturing the same according to preferred embodiments of the present invention will be described in detail referring to attached drawings. 
         [0038]      FIG. 4  is a cross-sectional view of a CMOS image sensor according to an embodiment of the present invention. 
         [0039]    Referring to  FIG. 4 , a p− type epitaxial layer  201  can be grown on a p++ type semiconductor substrate  200 , on which an isolation region and an active area (including a photodiode region and a transistor region) are defined. A field oxide layer  202  can be formed at the isolation region of the semiconductor substrate  200 . A gate electrode  204  can be formed on the transistor region of the semiconductor substrate  200  with a gate insulating layer  203  formed therebetween. 
         [0040]    In addition, n− type diffusion regions  205  can be formed on the photodiode region of the semiconductor substrate  200 , and insulating layer sidewalls  206  can be formed at both side portions of the gate electrode  204 . 
         [0041]    A first interlayer dielectric  208  can be formed on the semiconductor substrate  200  including the gate electrode  204 , and various metal wirings  209  can be formed on the first interlayer dielectric  208 . In one embodiment the metal wirings  209  can be formed at a constant interval. 
         [0042]    A second interlayer dielectric  210  can be formed on the semiconductor substrate  200  including the metal wirings  209 , and a nitride layer  211  can be formed on the second interlayer dielectric  210 . 
         [0043]    After that, trenches having a predetermined depth can be formed by selectively removing the nitride layer  211  and the second interlayer dielectric  210  in regions corresponding to the n− type diffusion regions  205 . Within the trenches, a color filter layer  213  of red (R), green (G) and blue (B) can be formed. 
         [0044]    A plurality of microlenses  214  corresponding to each n− type diffusion region  205  can be formed on each color filter layer  213 . 
         [0045]    Here, reference number  207  represents a source and a drain impurity region of the transistor. 
         [0046]      FIG. 6  is a cross-sectional view of a CMOS image sensor according to another preferred embodiment of the present invention. 
         [0047]    For the CMOS image sensor illustrated in  FIG. 6 , the trench can be formed to a deeper depth than the CMOS image sensor illustrated in  FIG. 4 . In a further embodiment, the trench can be formed to expose a surface of the first interlayer dielectric  208 , and each color filter layer  213  can be formed after the second interlayer dielectric  210  is removed and the first interlayer dielectric  208  is exposed. 
         [0048]    That is, each color filter layer  213  can be formed on the first interlayer dielectric  208 . 
         [0049]    Accordingly, the distance between the microlens  214  and the photodiode region is reduced even further. 
         [0050]      FIGS. 5A-5E  are cross-sectional views for illustrating the method of manufacturing the CMOS image sensor according to an embodiment of the present invention. 
         [0051]    Referring to  FIG. 5A , a low concentration first conductive type (p− type) epitaxial layer  201  can be formed on a semiconductor substrate  200  such as a high concentration first conductive type (p++ type) polysilicon substrate by means of an epitaxial process. 
         [0052]    The epitaxial layer  201  is formed to form a deep and wide depletion region at the photodiode area and to increase the capability of a low voltage photodiode to collect photo charges to further improve the photo-sensitivity. 
         [0053]    A photodiode region, a transistor region and an isolation region can be defined on the semiconductor substrate  200 , and an isolation layer  202  can be formed at the isolation region by using an STI process or a LOCOS process. 
         [0054]    Then, a gate insulating layer  203  and a conductive layer (for example, a high concentration polysilicon layer) can be sequentially deposited on the epitaxial layer  201  on which the isolation layer  202  is formed. The conductive layer and the gate insulation layer  203  can be selectively removed to form a gate electrode  204  for each transistor. 
         [0055]    Here, the gate insulating layer  203  can be formed by means of a thermal oxidation process or by a CVD method. In a further embodiment, a silicide layer can be further formed on the conductive layer to obtain a gate electrode. 
         [0056]    In an embodiment, a thermal oxidation process can be carried out with respect to the surface of the gate electrode  204  and the semiconductor substrate  200  to form a thermal oxidation layer (not shown). 
         [0057]    After that, low concentration second conductive type (n− type) impurity ions can be implanted onto the photodiode region of the semiconductor substrate  200  to form an n− type diffusion region  205 . 
         [0058]    Then, an insulating layer can be formed on the semiconductor substrate  200 , and an etch back process can be performed to form an insulating layer sidewall  206  on both side portions of the gate electrode  204 . 
         [0059]    High concentration second conductive type (n+ type) impurity ions can be implanted onto the transistor region of the semiconductor substrate  200  to form a high concentration n+ type diffusion region  207 . 
         [0060]    A thermal treatment process (for example, a rapid thermal treatment process) can be performed to diffuse the impurity ions within the n− type diffusion region  205  and the n+ type diffusion region  207 . 
         [0061]    In a further embodiment, an n− type diffusion region (not shown) can be formed at the transistor region by implanting n− type implanting ions at a lower implantation energy than that at the n− type diffusion region  205  before forming the high n+ type diffusion region  207 . 
         [0062]    Referring to  FIG. 5B , a first interlayer dielectric  208  can be formed on the semiconductor substrate  200 . 
         [0063]    In one embodiment, the first interlayer dielectric  208  can be formed as a silane-based insulating layer to recover dangling bonds within the semiconductor substrate  200  due to a large amount of hydrogen ions included therein and to effectively reduce a dark current. 
         [0064]    A metal layer can be deposited on the first interlayer dielectric  208  and selectively etched by a photolithography process and an etching process to obtain various metal wirings  209 . 
         [0065]    Referring to  FIG. 5C , a second interlayer dielectric  210  can be formed on the semiconductor substrate  200  including the metal wiring  209 . In a specific embodiment, the second interlayer  210  can be formed to a thickness of about 3000-4000 Å. 
         [0066]    Here, the second interlayer dielectric  210  can be formed by using USG (undoped silicate glass), PSG, BSG or BPSG. 
         [0067]    A nitride layer  211  can be formed on the second interlayer dielectric  210 . The nitride layer  211  can have a thickness of about 2000˜3000 Å. 
         [0068]    The nitride layer  211  and the second interlayer dielectric  210  can be selectively removed in regions corresponding to the photodiode regions by performing a photo process and an etching process to form a plurality of trenches  212  having a predetermined depth from the surface. 
         [0069]    Referring to  FIG. 5D , a color filter layer  213 , for example of red (R), blue (B) and green (G) can be formed within each trench through  212  corresponding to the n− type diffusion region  205 . 
         [0070]    Here, each color filter layer  213  for filtering light according to each wavelength region can be formed by coating dyeable photoresist on the semiconductor substrate including the trench  212 , and performing an exposing and developing process. 
         [0071]    Each color filter layer  213  may have a different thickness and so a planarization process such as a CMP (chemical mechanical polishing) process can be executed while setting the upper surface of the nitride layer  211  as an end point. 
         [0072]    Referring to  FIG. 5E , photoresist for a microlens used for improving the efficiency of the collection of the light at the n− type diffusion regions  205  can be coated on the semiconductor substrate  200  including each color filter layer  213 . 
         [0073]    Then, the photoresist can be selectively patterned by performing an exposing and developing process to form a microlens pattern. 
         [0074]    At this time, when the photoresist is positive resist, the photo active compound of an initiator, which is an absorbing material of the photoresist, decomposes to improve transmittance. Therefore, a flood exposure is applied to decompose the photo active compound remaining in the microlens pattern. 
         [0075]    Through the flood exposure for the microlens pattern, the transmittance is heightened and photo acid is generated to increase the flowability of the microlens. 
         [0076]    The semiconductor substrate  200  on which the microlens pattern is formed can be placed on a hot plate (not shown), and can be heat treated at about 150˜300° C. to reflow the microlens pattern to form a convex shaped microlens  214 . 
         [0077]    The heat treated and reflowed microlens  214  can then be cooled. Here, the cooling treatment can be implemented by putting the semiconductor substrate  200  on a cooling plate. 
         [0078]    As described above, the CMOS image sensor and the method of manufacturing the same according to the present invention can exhibit the following effects. 
         [0079]    Each color filter layer can be formed within a trench such that forming a separate planarizing layer is not necessary. Accordingly, the focal distance between the microlens and the photodiode region is reduced to prevent the cross talk between neighboring pixels and to improve the sensitivity of the image sensor at the same time. 
         [0080]    Although a preferred embodiment of the present invention has been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.