Abstract:
A charge pump circuit is disclosed which can perform high pumping by changing the condition of connection of the charge pump circuit by connecting a serial and parallel switching circuit and a level shift circuit between unit charge pumps to construct the charge pump circuit.

Description:
BACKGROUND OF INVENTION 
   Field of Invention 
   The present invention relates to a charge pump circuit and, more particularly, a charge pump circuit which can reduce pumping time. 
   Information Disclosure Statement 
   As shown in  FIG. 1 , in a conventional charge pump circuit, a plurality of unit charge pump circuits  1 A,  1 B,  1 C and  1 D are connected in series between a supply power source VDD and an output terminal Z. Therefore, the supply power source VDD is charged up at each unit charge pump  1 A,  1 B,  1 C and  1 D in accordance with a two(2)-phase clock signals; Φ, {overscore (Φ)} and transferred to the output terminal Z. 
     FIG. 2  is an equivalent circuit for illustration of  FIG. 1 . As shown in  FIG. 2 , each unit charge pump  1 A,  1 B,  1 C and  1 D comprises a capacitor C and a diode D for charge pumping. Such unit charge pumps  1 A,  1 B,  1 C and  1 D are connected in series between the supply power source VDD and an output terminal Z. The supply power source VDD is charged up at each unit charge pump  1 A,  1 B,  1 C and  1 D in accordance with the two(2)-phase clock signals Φ, {overscore (Φ)} and transferred to the output terminal Z through a diode Dz. CL denotes a load capacitor in both  FIGS. 1 and 2 . 
   However, such conventional charge pump circuit has a disadvantage in that a consumption power is high and a charge transfer efficiency at initial operation is lowered since the unit charge pumps are connected in series between the supply power source and the output terminal. 
   SUMMARY OF THE INVENTION 
   An object of the invention is to provide a charge pump circuit which can solve the above advantage by connecting switching circuit connected between unit charge pumps and by controlling the switching circuit with a level shift circuit. 
   To achieve the above object, a charge pump circuit according to the present invention, comprises: a first unit charge pump connected to a supply power source and performing a pumping operation according to clock signals; a second unit charge pump connected to the supply power source and performing a pumping operation according to the clock signals; and a switching circuit for selectively transferring an output of the first unit charge pump to an input or output of the second unit charge pump according to a control signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For fuller understanding of the nature and objects of the invention, reference should be had to the following detailed description taken in conjunction with the accompanying drawings in which: 
       FIG. 1  shows a conventional charge pump circuit; 
       FIG. 2  is an equivalent circuit for illustration of  FIG. 1 ; 
       FIG. 3  is a charge pump circuit of the present invention; 
       FIGS. 4A through 4C  are equivalent circuits for illustration of  FIG. 3 ; 
       FIG. 5  is a detailed circuit of a level shift circuit of  FIG. 3 ; 
       FIG. 6A  is a graph for comparing an output of the conventional charge pump circuit and an output of the charge pump circuit of the present invention; and 
       FIG. 6B  is a schematic diagram for illustration of  FIG. 6A . 
   

   Similar reference characters refer to similar parts through the several views of the drawings. 
   DETAILED DESCRIPTION OF THE INVENTION 
   A detailed description of an embodiment of the present invention is given below with reference to the accompanying drawings. 
     FIG. 3  is a charge pump circuit of the present invention. Circuits of first, second, third and fourth unit charge pumps  1 A,  1 B,  1 C and  1 D which are supplied an operating voltage from the supply power source VDD, respectively, are identical to the circuit of  FIG. 1 . A switching circuit  2  is provided between the first and second unit charge pumps  1 A and  1 B. An input terminal of the switching circuit  2  is connected to an output terminal of the first unit charge pump  1 A. An output terminal of the switching circuit  2  is connected to an input terminal of the second unit charge pump  1   b  and an output terminal Z respectively. Each switching circuit  2  is also connected between the second and third unit charge pumps  1 B and  1 C and connected between the third and fourth unit charge pumps  1 C and  1 D, and also connected to the output terminal Z. The switching circuit  2  has two transistors N 1  and N 2 . The transistor N 1  is connected. The transistor N 2  is connected to the output terminal of the first unit charge pump  1 A and the output terminal Z. The transistor N 1  and N 2  connected between the second and third unit charge pumps  1 B and  1 C, and the transistor N 1  and N 2  connected between the third and fourth unit charge pumps  1 C and  1 D are connected in the same way as the transistor N 1  and N 2  connected between the first and second unit charge pumps  1 A and  1 B. 
   The switching circuit  2  is controlled by output signals of a level shift circuit  3 . That is, the transistors N 1  and N 2  are turned on or off according to outputs the output signals KOUT and KOUTB of the level shift circuit  3 . The level shift circuit  3  produces output signal KOUT and KOUTB according to each control signal S 1 , S 2  or S 3  and an output signal S 4  of an auxiliary charge pump circuit  4  which is operated according to the two(2)-phase clock signals Φ, {overscore (Φ)}. The reference number CL denotes a load capacitor. If the transistors N 1  are turned on and the transistors N 2  are turned off, the first through fourth unit charge pumps  1 A through  1 D are connected in cascade. To the contrary, if the transistors N 1  are turned off and the transistors N 2  are turned on, the output terminals of the first through fourth unit charge pumps  1 A through  1 D are connected to the output terminal Z. 
     FIGS. 4A ,  4 B and  4 C are equivalent circuits for illustration of  FIG. 3 .  FIG. 4A  can be regarded as an equivalent circuit of  FIG. 3  in the condition that all the transistors N 1  are turned off and all the transistors N 2  are turned on. Therefore, the supply power source VDD is transferred to the output terminal Z through a diode D and Dz. The resultant capacitance is  4 C. 
     FIG. 4C  can be regarded as an equivalent circuit of  FIG. 3  in the condition that all the transistors N 1  are turned on and all the transistors N 2  are turned off. The first through fourth unit charge pumps  1 A through  1 D are transformed into diodes D. The resultant capacitance is C/4. The capacitance is reduced in the condition of  FIG. 4A . The supply power source VDD is transferred to the output terminal Z through the diodes D and Dz. The capacitor CL is a load capacitor. 
     FIG. 4B  can be regarded as an equivalent circuit of  FIG. 3  in the condition that the transistor N 1  is turned on and the transistor N 2  is turned off between the first and second charge pumps  1 A and  1 B, the transistor N 1  is turned on and the transistor N 2  is turned off between the third and fourth unit charge pumps  1 C and  1 D, and the transistor N 1  is turned off and the transistor N 2  is turned on between the second and third unit charge pumps  1 B and  1 C. 
     FIG. 5  is a detailed circuit diagram of the level shift circuit of  FIG. 3 . The output signals KOUT and KOUTB which are inverted from each other are generated according to an output signal S 4  of the auxiliary charge pump circuit  4  and control signals S 1 , S 2  and S 3 . The output signal S 4  of the auxiliary charge pump circuit  4  is maintained to be in a high voltage condition. Therefore, if the control signal S 1 , S 2  or S 3  is “HIGH”, the output of an invert gate G 1  becomes “LOW”, whereby a transistor Q 6  is turned off and a transistor Q 5  is turned on. At this time, since transistors Q 3  and Q 4  are in the condition of turn on, a transistor Q 2  is turned on while a transistor Q 1  is turned off. Therefore, the output KOUT signal becomes “HIGH” and the output KOUTB signal becomes “LOW”. 
     FIG. 6A  is a graph for comparing an output(X) of the conventional charge pump circuit and an output(Y) of the charge pump circuit of the present invention. 
   As shown in  FIG. 6A , the conventional charge pump circuit takes much time to rise up to VCC voltage since charge pumping starts at a voltage far lower than VCC voltage. 
   However, as shown in  FIG. 6B , the present invention increases the capacitance since the first through fourth unit charge pumps  1 A through  1 D are connected in parallel to the output terminal Z at the beginning (STEP  1 ) of pumping operation, and decreases the capacitance since the first and second unit charge pumps  1 A and  1 B and the third and fourth unit charge pumps  1 C and  1 D are connected in cascade, respectively, and the output terminals of the second and fourth unit charge pumps  1 B and  1 D are connected to the output terminal Z as shown in step  2 . At the final step (STEP  3 ), the first through fourth unit charge pumps  1 A through  1 D are connected in cascade as shown in  FIG. 1 . Therefore, as shown in  FIG. 6A , since the pumping operation starts at about 2.2V, the pumping time is reduced as well as the power consumption is reduced. 
   As described above, the present invention has an excellent effect that the charge transfer efficiency is increased at the initial operation of the charge pump circuit as well as the programming time can be reduced at the time of programming flash memory devices utilizing high voltage. 
   The foregoing description, although described in its preferred embodiment with a certain degree of particularity, is only illustrative of the principle of the present invention. It is to be understood that the present invention is not to be limited to the preferred embodiments disclosed and illustrated herein. Accordingly, all expedient variations that may be made within the scope and spirit of the present invention are to be encompassed as further embodiments of the present invention.