Abstract:
A method for fabricating semiconductor device capable of minimizing hillocks and voids. The method includes subjecting an interlayer dielectric having a multi-protective dielectric structure including a first barrier metal layer and a first copper line to a plurality of NH 3  treatment processes, forming a capping film on the first copper line, and planarizing the capping film via chemical mechanical polishing (CMP).

Description:
[0001]    The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2007-0088470 (filed on Aug. 31, 2007), which is hereby incorporated by reference in its entirety. 
       BACKGROUND 
       [0002]    Aspects of semiconductor fabricaton technology have focused on obtaining devices having ultra high integration. In the fabrication of semiconductor devices, metals such as aluminum (Al), aluminum alloys and tungsten (W) are generally used for metal lines. However, with the trend towards high-integration, semiconductor devices have decreased melting points and increased specific resistance. For this reason, currently used metals cannot be applied to ultra high-integration semiconductors devices. Accordingly, there is an increasing demand for development of alternative metal line materials. Examples of these alternative materials include metals exhibiting superior conductivity, such as copper (Cu), gold (Au), silver (Ag), cobalt (Co), chrome (Cr) and nickel (Ni) and the like. Of these, copper and copper alloys have been widely used since they have a low specific resistance, exhibit superior electromigration (EM) and stressmigration (SM) reliability and have low preparation costs. 
         [0003]    Since copper lines can reduce RC time delay due to resistivity lower than aluminum lines, they are being used for devices having a design rule of 0.13 μm or lower. Copper lines have tenfold thermal expansion coefficients of dielectric films, and thus, are rapidly expanded at temperatures above a specific level used for semiconductor processes. For this reason, compressive stress is applied to the copper lines. High compressive stress causes creation of small hill-like structures called “hillocks” on copper lines. As illustrated in example  FIG. 1 , hillocks make metal line residues left after chemical mechanical polishing (CMP). These residues cause short-circuits between metal lines and voids, thus negatively affecting process reliability. 
       SUMMARY 
       [0004]    Embodiments relate to a method for fabricating a semiconductor device that reduces generation of hillocks and voids. 
         [0005]    Embodiments relate to a method for fabricating a semiconductor device that can include at least one of the following steps: providing an interlayer dielectric having a multi-protective dielectric structure including a first barrier metal layer and a first copper line layer planarized by chemical mechanical polishing (CMP); and then subjecting the interlayer dielectric to an NH 3  treatment process; and then forming a capping film for copper diffusion prevention on and/or over the interlayer dielectric including the first copper line layer; and then planarizing the capping film using chemical mechanical polishing (CMP). 
         [0006]    Embodiments relate to a method for reducing the generation of hillocks on the surface of a metal line that can include at least one of the following steps: sequentially performing a plurality of NH 3  treatment processes on the metal line; and then forming a capping film over the metal line and then increasing the thickness of the capping film until it corresponds to the thickness of the hillocks; and then planarizing the capping film by performing a chemical mechanical polishing process. 
         [0007]    Embodiments relate to a method for reducing the generation of hillocks on the surface of a copper line that can include at least one of the following steps: forming a copper layer as the metal line in a first dielectric layer; and then sequentially performing a plurality of NH 3  treatment processes on the first copper line; and then forming a capping film over the first copper line such that the thickness of the capping film is increased until it corresponds to the thickness of the hillocks; and then planarizing the capping film; and then sequentially forming a second, third and fourth dielectric films over the capping film; and then forming a trench in the third and fourth dielectric films by performing an etching process; and then forming a second copper layer as a second metal line in the trench. 
     
    
     
       DRAWINGS 
         [0008]    Example  FIG. 1  illustrates formation of hillocks in a semiconductor device. 
           [0009]    Example  FIGS. 2A to 2E  illustrates a method of fabricating a semiconductor device in accordance with embodiments. 
       
    
    
     DESCRIPTION 
       [0010]    As illustrated in example  FIG. 2A , first protective dielectric film  100  is deposited on and/or over semiconductor substrate  90 , and an exposure process is performed in order to form a photoresist for forming a contact hole. First protective dielectric film  100  may be made of SiH 4 . The photoresist is formed by exposing the photoresist film coated on and/or over semiconductor substrate  90  to exposure equipment using a predetermined exposure mask, baking the resulting photoresist in baking equipment and removing the exposed photoresist using a predetermined developing solution. After the exposure, first protective dielectric film  100  is etched using the photoresist as a mask to form a contact hole. Plug  110  composed of a metal such as tungsten is then formed in the contact hole. 
         [0011]    As illustrated in example  FIG. 2B , second protective dielectric film  120  and third protective dielectric film  130  are sequentially deposited on and/or over first protective insulating layer  100  including tungsten plug  110 . Second protective dielectric film  120  may be formed of fluorosilicate glass (FSG) and third protective dielectric film  130  may be formed of silane (SiH 4 ). After the deposition of second protective dielectric film  120  and third protective dielectric film  130 , an exposure process is performed to form a photoresist for forming a trench. Second protective dielectric film  120  and third protective dielectric film  130  are dry-etched using the photoresist as a mask to form a trench exposing plug  110 . 
         [0012]    As illustrated in example  FIG. 2C , after the photoresist is removed, first barrier metal  140  and first copper line layer  150  are formed over the entire surface of semiconductor substrate  90  including the trench. First copper line layer  150  is then planarized via chemical mechanical polishing (CMP) such that the surface of third protective dielectric film  130  is exposed. First barrier metal  140  may be formed of Ta/TaN. An oxide layer such as cupric oxide (CuO) formed on and/or over the exposed first copper line layer  150  is reduced to pure copper by performing a NH 3  treatment process that includes a plurality of steps. The NH 3  treatment process may be carried out by perfoming respective steps for a predetermined period of time. For example, the NH 3  treatment process may be composed of two steps including a primary step performed for 7 seconds and a secondary step performed for 8 seconds. Alternatively, the NH 3  treatment process may be composed of three steps in which each step is performed for 5 seconds. As a result, it is possible to minimize the thickness of hillocks created on the surface of first copper line layer  150 . 
         [0013]    As illustrated in example  FIG. 2D , capping film  160  for preventing diffusion of copper may then be formed on and/or over the entire surface of semiconductor substrate  90  including first copper line layer  150 . Capping film  160  may be formed at 350 to 400° C. using at least one of silicon carbide (SiC), silicon carbon nitride (SiCN) and fluorine-doped silicon oxide (SiOF). In addition, the thickness of capping film  160  may be increased until it corresponds to the thickness of the hillock. Subsequently, capping film  160  is planarized via chemical mechanical polishing. 
         [0014]    As illustrated in example  FIG. 2E , fourth protective dielectric film  170 , fifth protective dielectric film  180  and sixth protective dielectric film  190  may then be sequentially deposited on and/or over capping film  160 . Fifth protective dielectric film  180  and sixth protective dielectric film  190  may then be subjected to exposure and etching to form a trench. Second barrier metal  200  and second copper line layer  210  are then formed on and/or over the entire surface of sixth protective dielectric film  190  including the trench. Fourth protective dielectric film  170  and sixth protective dielectric film  190  may be formed of SiH 4  and fifth protective dielectric film  180  may be formed of FSG. Capping film  160  is increased to a thickness not smaller than the thickness of hillocks formed on copper line  150  and is then planarized via CMP, thereby minimizing the thickness of hillocks via heat treatment during deposition of fourth protective dielectric film  170 , fifth protective dielectric film  180  and sixth protective dielectric film  190 . As a result, short-circuit between lines caused by first barrier metal layer  140  residues can be reduced. In addition, occurrence of voids can be prevented by controlling the thickness of hillocks. 
         [0015]    As apparent from the afore-going, the method of fabricating for a semiconductor device has at least the following advantages. First, a NH 3  plasma treatment process is performed through a plurality (i.e., two or three) steps, thereby minimizing hillocks on the copper line. Second, the capping film for copper diffusion prevention may deposited on and/or over the copper line to a thickness not smaller than the thickness of hillocks formed on the copper line and then planarized, thereby minimizing the hillock thickness via heat treatment during deposition of the IDL layer and reducing short-circuit caused by barrier metal layer residues. Third, occurrence of voids can be prevented by controlling the thickness of hillocks formed on the contact hole. 
         [0016]    It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.