Abstract:
Some embodiments relate to power detector including a voltage sensor configured to detect a voltage of a load and a current sensor configured to detect a current of the load. The power detector also includes circuitry configured to introduce a phase delay between the detected voltage of the load and the detected current of the load, thereby producing a voltage measurement and a current measurement. The circuitry is also configured to multiply the voltage measurement and the current measurement.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority to U.S. provisional application Ser. No. 62/160,807, titled “POWER DETECTOR AND CALIBRATION METHOD,” filed May 13, 2015, which is hereby incorporated by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The techniques described herein relate to accurately detecting power delivered to a load, such as the power delivered to an antenna by a power amplifier. 
         [0004]    2. Discussion of the Related Art 
         [0005]    In radio frequency (RF) communications, a radio signal is transmitted by driving an antenna using a power amplifier. Various techniques have been proposed for measuring the power delivered to an antenna, however, they suffer from limitations that affect the accuracy of the power measurement. 
       SUMMARY 
       [0006]    Some embodiments relate to power detector including a voltage sensor configured to detect a voltage of a load and a current sensor configured to detect a current of the load. The power detector also includes circuitry configured to introduce a phase delay between the detected voltage of the load and the detected current of the load, thereby producing a voltage measurement and a current measurement. The circuitry is also configured to multiply the voltage measurement and the current measurement. 
         [0007]    Some embodiments relate to a power detection method. The method includes detecting a voltage of a load. The method also includes detecting a current of the load. The method additionally includes introducing a phase delay between the detected voltage of the load and the detected current of the load, thereby producing a voltage measurement and a current measurement. The method further includes multiplying the voltage measurement and the current measurement. 
         [0008]    The foregoing summary is provided by way of illustration and is not intended to be limiting. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0009]    In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like reference character. For purposes of clarity, not every component may be labeled in every drawing. The drawings are not necessarily drawn to scale, with emphasis instead being placed on illustrating various aspects of the techniques and devices described herein. 
           [0010]      FIG. 1  shows a technique for detecting power that involves squaring the voltage at the output of a transmitter. 
           [0011]      FIG. 2  shows a technique in which the voltage at the transmitter output and the current of the transmitter are measured and multiplied to obtain an indication of output power. Specifically, the current of the transmitter is measured by multiplying the transmitter input voltage with a replica of the transconductance cell. 
           [0012]      FIGS. 3A and 3B  show another technique in which an additional coil is added to a transformer to measure current, and output voltage is sensed capacitively, as described in F. Francois, P. Reynaert, “A transformer-Coupled True-RMS Power Detector in 40 nm CMOS,” ISSCC Dig. Tech. Papers, pp. 62-63, February 2014. 
           [0013]      FIG. 4  shows a transmitter system with power control loop having a transmitter, a power control circuit, and a power detection circuit, according to some embodiments. 
           [0014]      FIG. 5  illustrates a variable load impedance. 
           [0015]      FIG. 6  illustrates a switching power amplifier. 
           [0016]      FIG. 7  shows a power amplifier having a plurality of power amplifier circuits. 
           [0017]      FIG. 8A  illustrates a technique for detecting load power, according to some embodiments, in which a phase delay unit is present in the voltage sensing path. 
           [0018]      FIG. 8B  shows an embodiment with a controller for controlling and/or calibrating the phase delay. 
           [0019]      FIG. 8C  illustrates a technique for detecting load power, according to some embodiments, in which a phase delay unit is present in the current sensing path. 
           [0020]      FIG. 8D  shows an embodiment in which a phase delay may be introduced in the voltage and/or current sensing path in the voltage and/or current sensors. 
           [0021]      FIG. 8E  shows an embodiment in which a phase delay may be introduced in the voltage and/or current sensing path in a multiplier. 
           [0022]      FIG. 8F  shows variable gains A I  and A v  in the current sense path and the voltage sense path. 
           [0023]      FIG. 9  shows an embodiment in which the current and voltage sensors are conductors. 
           [0024]      FIGS. 10A-D  show solutions to address to parasitics, especially for high frequency applications, according to some embodiments. 
           [0025]      FIG. 10E  shows a differential implementation of a power detector that can detect power from a drive circuit that is differentially connected to a load 
           [0026]      FIGS. 11A and 11B  show ways to implement the techniques described herein with different packages. 
       
    
    
     DETAILED DESCRIPTION 
       [0027]    As mentioned above, various techniques have been proposed for accurately measuring load power, but they suffer from limitations that affect their accuracy. 
         [0028]      FIG. 1  shows a technique for detecting power that squares the voltage at the output of a transmitter, and calculates power based on Pout=V 2   out /Z L . However, a difficulty with this technique is that the load impedance Z L  may vary, which may lead to an inaccurate power calculation. 
         [0029]      FIG. 2  shows a technique that can reduce the error caused by the change in the load impedance. The voltage at the transmitter output and the current of the transmitter are measured and multiplied to obtain an indication of output power. Specifically, the current of the transmitter is measured by multiplying the transmitter input voltage with a replica of a transconductance cell. A phase shifter may account for the phase difference between the current and the voltage. However, the sensed current may not track the output current, which may lead to an inaccurate power measurement. 
         [0030]      FIGS. 3A and 3B  show another technique in which an additional coil is added to a transformer to measure current, and output voltage is sensed capacitively. However, the measured voltage and current are not equal to the load current and voltage, which may lead to an inaccurate power measurement. 
         [0031]    In some embodiments, power may be detected by measuring the load current and the load voltage from conductors coupled to the load. A selected phase adjustment may be introduced to correct the phase difference between the measured current and the measured voltage that may arise due to the load impedance. 
         [0032]      FIG. 4  shows a transmitter system with power control loop  1  having a transmitter  2 , a power control circuit  4 , and a power detection circuit  6 . Power detection circuit  6  detects the load power P L . In some embodiments, the load may be an antenna and the power P L  may be the power delivered to the antenna. However, the techniques described herein are not limited to detecting the power delivered to an antenna. The transmitter  2  may produce a signal having any suitable frequency above 0 Hz. In some embodiments, the transmitter  2  may produce a signal having a frequency between 300 kHz and 300 GHz, however, the techniques described herein are not limited as to particular frequencies. The power detection circuit  6  may produce a TSSI (Transmitter Signal Strength Indication) that is proportional to P L . The power control circuit  4  controls the transmitter  2  based upon the TSSI signal. Accurate power detection by the power detection circuit  6  is important for appropriate control of the transmitter  2 . 
         [0033]      FIG. 5  illustrates a challenge with detecting the load power. If the load impedance Z L  is variable, the gain or attenuation between load power and detected power changes as Z L  changes. 
         [0034]      FIG. 6  illustrates that in some embodiments, the transmitter system with power control loop  1  may include a switching power amplifier  2 A. The switching power amplifier  2 A may be any suitable type of amplifier, including class D, E, and F power amplifiers, and digital power amplifiers. The power produced by switching power amplifier  2 A may be controlled using any suitable control technique, such as pulse-width modulation, for example. In some embodiments, the switching power amplifier  2 A may be controlled by power control circuit  4  based upon the TSSI signal. Since the switching power amplifier  2 A is non-linear, it can be more effective to measure the power at the load rather than the input or output of the power amplifier  2 A.  FIG. 6  also shows that passive components  7  may be included between the output of the switching power amplifier  2 A and the load. In some embodiments, the passive components  7  may tune out undesired harmonics. In some embodiments, passive components  7  may include an impedance matching network. 
         [0035]      FIG. 7  shows that in some embodiments, the transmitter system with power control loop  1  may include a power amplifier  2 B having a plurality of power amplifier circuits. The power from the plurality of power amplifier circuits may be combined and delivered to a load. Examples of such amplifiers include Doherty power amplifiers, outphasing power amplifiers and digital power amplifiers, Power control circuit  4  may control the power amplifier circuits based on the TSSI signal. Individual power amplifier circuits may be controlled to produce the same amount of power or different amounts of power. As with the circuit of  FIG. 6 , it can be more effective to measure the power at the load rather than the input or output of the power amplifier  2 B. 
         [0036]      FIG. 8A  illustrates a technique for detecting load power, according to some embodiments. In the embodiment of  FIG. 8A , a drive circuit  82  such as a power amplifier, for example, drives a load  84  having an impedance Z L  with a current I L , a voltage V L  and power P L . Load current I L  may be measured by using a current sensor  86 . Load voltage V L  may be measured by using a voltage sensor  88 . The inventors have recognized and appreciated that the magnitudes and phases of the measured current signal S I  and the measured voltage signal S V0  may vary as the load impedance Z L  varies. Variation in the load impedance changes the voltage standing wave ratio (VSWR), which can produce different magnitudes and phases in the voltage and current measurements. In some embodiments, a phase delay θ may be added to the measured voltage signal S V0  by a phase delay unit  90 . The phase delayed voltage signal S V  is multiplied by the measured current S I  by a multiplier  92 . The multiplied value may be low pass filtered by a low pass filter or averaging unit  94  to produce a determined load power P DET . However, the techniques described herein are not limited to adding a phase delay to the signal measured by the voltage sensor  88 , as in some embodiments a phase delay may be added to the signal measured by the current sensor  86 , or different phase delays may be added to both the current and voltage measurements to achieve the same result. 
         [0037]    The inventors have recognized and appreciated that a properly selected phase delay θ may accurately compensate for the variation in load impedance, which can produce an accurate power measurement. Although the power detector is capable of RMS power detection, sinusoidal waves are used to demonstrate the concept in the following analysis for simplicity. Assuming a complex load Z L , with magnitude of |Z| and phase of φ, is presented to the drive circuit  82 , the load voltage V L  and load current I L  can be represented by the following equations, where V m  and I m  are the magnitudes of the load voltage and the load current, respectively: 
         [0000]        V   L   =V   m  cos(ω t +φ)  (1)
 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     L 
                   
                   = 
                   
                     
                       
                         V 
                         m 
                       
                       
                          
                         Z 
                          
                       
                     
                      
                     cos 
                      
                     
                         
                     
                      
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                   ( 
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         [0000]    And in phasor notation: 
         [0000]          V     L   =V   m ≦φ  (3)
 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       _ 
                     
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         [0000]    The output of voltage sensor S VO  has a linear relationship with the output voltage V L , which does not change with |Z| or φ 
         [0000]        S   VO   =A   V   ×V   L  cos β V   =A   V   ×V   m  cos(ω t+φ+β   V )  (5)
 
         [0000]    S VO  experiences a phase delay of φ 
         [0000]        S   V   =A   V   ×V   m  cos(ω t+φ+β   V +θ)  (6)
 
         [0000]    Similarly, the output of current sensor S I  has a linear relationship with the output current I L , which does not change with |Z| or φ 
         [0000]    
       
         
           
             
               
                 
                   
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         [0000]    The multiplier multiplies S V  and S I . The generated product is filtered by an averaging unit or low pass filter (LPF)  94 : 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           
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         [0000]    Therefore, P DET  is linearly proportional to the delivered load power and independent of the load impedance variation, if (θ+β V −β I )=0. The inventors have appreciated that mathematically, accurate power detection may be obtained by properly selecting θ, which makes the measurement insensitive to VSWR changes. The phase delay θ that is appropriate for a particular implementation may be selected by calibration, modeling and/or simulation. In some embodiments, the phase delay θ is tunable, which allows compensating for variations in temperature and frequency as well as processing variations. 
         [0038]    In some embodiments, one or more attenuators and/or amplifiers may be included in the signal path(s) before or after the sensor(s), which may extend the dynamic range of the power detector. Such attenuator(s) and/or amplifier(s) may be considered part of the current sensor  86  and/or the voltage sensor  88 . This is illustrated in  FIG. 8A  as a gain A I  of the current sensor  86  and a gain A v  of the voltage sensor  88 . The gain A I  and/or the gain A v  may have a value less than one to attenuate a detected signal, equal to one to produce no attenuation or amplification, or greater than one to amplify a detected signal. The attenuators and/or amplifiers may be implemented in analog and/or digital circuitry. 
         [0039]    As shown in  FIG. 8F , in some embodiments, the gain A I  and/or the gain A v  may be variable. For example, the one or more attenuators and/or amplifiers may be tunable to produce selected gain(s) in the current and/or voltage sense path. 
         [0040]      FIG. 8B  shows an embodiment in which the phase delay θ is tunable and may be calibrated.  FIG. 8B  shows a phase shift controller  96  may be included in power detection circuit  6  that can control the phase delay θ. In some embodiments, the phase shift controller  96  may calibrate the phase delay θ based on a programmed calibration sequence. Phase shift controller  96  and power control circuit  4  may be implemented by the same controller (e.g., a microprocessor or control circuit) or different controllers. 
         [0041]      FIG. 8C  shows an embodiment for detecting load power, according to some embodiments, in which a phase delay unit  90  is present in the current sensing path. In such embodiments, the phase delay may be tunable and/or may be calibrated, as discussed above. In some embodiments, phase delays may be introduced in both the current sensing path and the voltage sensing path. 
         [0042]      FIG. 8D  shows an embodiment in which a phase delay may be introduced in the voltage and/or current sensing path in the voltage and/or current sensors. For example, a phase delay θ v  may be introduced in the signal measured by the voltage sensor  86 , a phase delay θ I  may be introduced in the signal measured by the current sensor  88 , or both phase delays θ v  and θ I  may be introduced. Phase delays θ v  and θ I  may be introduced digitally or using analog components. 
         [0043]      FIG. 8E  shows an embodiment in which a phase delay may be introduced in the voltage and/or current sensing path in a multiplier  92 , which may be a circuit and/or software. For example, a phase delay θ v  may be introduced to S V , a phase delay θ I  may be introduced to S I , or both phase delays θ v  and θ I  may be introduced. Thus, as seen from the above, one or more phase delays may be introduced anywhere in the voltage and/or current sensing paths. 
         [0044]    Referring to  FIG. 8A , in some embodiments, the voltage sensor  88  may include a conductor or other circuit element coupled to the load. For example, as discussed below, the conductor of the voltage sensor  88  may be a bondwire, trace, solder ball, via, coupled line or and/or any other suitable conductor. 
         [0045]    In some embodiments, the current sensor  86  may be a conductor that is positioned to inductively sense the load current from a conductor that provides the load current to the load. For example, as discussed below, the conductor of the current sensor  86  may be a bondwire, trace, solder ball, via, coupled line or and/or any other suitable conductor. 
         [0046]    The phase delay unit  90 , multiplier  92  and low pass filter and/or averaging unit  94  may be implemented using analog or digital component(s). For example, the phase delay unit  90  may be an analog circuit element that delays a signal. As another example, the phase delay unit  90  may be implemented digitally using a digital delay element or by converting S V0  and/or S I  to digital values and digitally delaying one or both signals. As discussed above, phase delay unit  90  may produce a delay θ that is tunable. If phase delay unit  90  is implemented digitally, the phase delay unit  90  may be controlled to change the delay using a programmable delay line, software or firmware, for example. Similarly, multiplier  92  may be implemented using an analog circuit or digitally using digital components and/or software or firmware. Also, the low pass filter and/or averaging unit  94  may be implemented using an analog circuit, a digital circuit, or in software or firmware. The low pass filter and/or averaging unit  94  need not be a “filter” per se, as it may implement any suitable time-averaging technique. 
         [0047]      FIG. 9  shows an embodiment in which a conductor L 0  connects the drive circuit  82  to the load  84 . A second conductor L 1  is coupled to the load  84  to make a voltage measurement S V0  that is provided to the phase delay unit  90 . Conductor L 1  is an example of a voltage sensor  88 . Phase delay unit  90  may be a circuit that presents a high impedance to L 1 , thus the current I L1  flowing through L 1  is zero, so S V0  is a faithful copy of V L . A third conductor L 2 , coupled between the multiplier  92  and ground, is positioned proximate the conductor L 0 , and due to inductive coupling, a current through conductor L 0  induces a current in conductor L 2 , which is provided as a measurement S I  of the load current I L . Thus, conductor L 2  is an example of a current sensor  86 . If L 0  and L 2  are inductors, S I  will be a faithful copy of I L  with close to a 900 phase shift if the multiplier input impedance is high. By inserting a θ=90° phase shift between L 1  and the multiplier  92 , P DET  will be a faithful copy of P L , independent of the change of |Z| or φ. In some embodiments, the conductors L 0 , L 1  may be bondwires. However, the techniques described herein are not limited in this respect, as any suitable conductors may be used such as solder balls, vias, traces, or coupled lines, by way of example and not limitation. 
         [0048]      FIG. 10A-D  address possible implementation issues related to parasitics, especially for high frequency applications. For the sake of discussion, L 0  and L 2  are assumed to be inductors. In  FIG. 10A , the sensed current S I  deviates from I L  because of current flowing through the parasitic capacitor C 3 . The effect of the parasitic capacitor C 3  can be compensated as shown in  FIG. 10B . In  FIG. 10B , an inductor L 3  is coupled between the ground and the output node coupled to the load, having an inductance selected to resonate with C 3  at the operating frequency, which cancels the current through C 3 . Accordingly, S I  will be a faithful copy of I L . 
         [0049]      FIG. 10C  shows an example in which S V0  is measured from the output of the drive circuit  82 . Due to the current flowing through L 0 , which has an inductance, S V0  deviates from V L . As shown in  FIG. 10D , a capacitor C 0  can be inserted coupled between L 0  and the drive circuit  82 , with a capacitance selected to resonate with L 0  at the operating frequency. Thus, S V0  is a faithful copy of V L . 
         [0050]      FIG. 10E  shows a differential implementation of a power detector that can detect power from a drive circuit  82  that is differentially connected to a load  84 . Conductors L 3  and L 0  couple the positive and negative output terminals of the drive circuit  82  to the positive and negative terminals of the load  84 , respectively. Conductors L 5  and L 1  are coupled to the load  84  to make a voltage measurement at the positive and negative terminals of the load  84 , respectively. The voltage measurements from conductors L 5  and L are provided to phase delay unit  90 , which delays the differential voltage measurement and provides it to multiplier  92 . Conductors L 4  and L 2  are inductively coupled to conductors L 3  and L 0 , respectively, and produce current measurements that are provided to multiplier  92 . Multiplier  92  multiplies the differential current measurement and delayed voltage measurement. In some embodiments, and as discussed above, the phase delay may be introduced in the current sensing path, or in both the voltage sensing path and current sensing path. In the example of  FIG. 10E , both current and voltage are measured differentially. However, the techniques described herein are not limited to measuring both current and voltage differentially, as a combination of a single-ended measurement and differential measurement may be used. For example, voltage may be measured differentially and current may be measured using a single-ended configuration, or current may be measured differentially and voltage may be measured using a single-ended configuration. 
         [0051]      FIGS. 11A and 11B  show ways to implement the above-described techniques with different packages.  FIG. 11A  shows a way to implement the power sensing technique in a SOC (system on chip) with a QFN (Quad flat no-lead) package. A bondwire L 0  is used to couple the output of the drive circuit  82  to the QFN load pin. A separate bondwire L 1  is arranged to sense the load voltage, coupled to the phase delay unit  90 . An additional bondwire L 2 , coupled to the QFN ground terminal, is placed proximate L 0  to sense the load current. Similarly, as shown in  FIG. 11B , the power sensing scheme can be implemented in CSP (chip-scale package) type package. The current sensing can be accomplished with magnetic couplings between either the vias (k 1 ) or the coupled lines (k 2 ). Solder balls are shown as connecting the die, substrate and PCB. 
         [0052]    In some embodiments, controller  96  and/or power control circuit  4  may be implemented using hardware or a combination of hardware and software. When implemented using software, suitable software code can be executed on any suitable processor (e.g., a microprocessor) or collection of processors. The one or more controllers can be implemented in numerous ways, such as with dedicated hardware, or with general purpose hardware (e.g., one or more processors) that is programmed using microcode or software to perform the functions recited above. 
         [0053]    Various aspects of the apparatus and techniques described herein may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing description and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments. 
         [0054]    Use of ordinal terms such as “first,” “second,” “third,” etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements. 
         [0055]    Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having,” “containing,” “involving,” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.