Abstract:
An array based communications system may comprise a plurality of element processors. Each element processor may comprise a combining circuit, a crest factor circuit, and a phase shifter circuit. The combining circuit may produce a weighted sum of a plurality of digital datastreams. The crest factor circuit may be operable to determine whether the weighted sum has a power above or below a power threshold. If the power is above the power threshold, the crest factor circuit is operable to reduce the power. If the power is below the power threshold, the crest factor circuit is operable to increase the power. The phase shifter circuit may introduce a phase shift to out-of-band components of the weighted sum according to the power increase or the power decrease by the crest factor circuit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE 
       [0001]    This patent application makes reference to, claims priority to, and claims the benefit from U.S. Provisional Application Ser. No. 62/206,365, which was filed on Aug. 18, 2015; U.S. Provisional Application Ser. No. 62/206,369, which was filed on Aug. 18, 2015; and U.S. Provisional Application Ser. No. 62/248,577, which was filed on Oct. 30, 2015. Each of the above applications is hereby incorporated herein by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    Limitations and disadvantages of conventional methods and systems for communication systems will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings. 
       BRIEF SUMMARY OF THE INVENTION 
       [0003]    Systems and methods are provided for per-element power control for array based communications, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. 
         [0004]    Advantages, aspects and novel features of the present disclosure, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings. 
     
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
         [0005]      FIG. 1A  shows a single-unit-cell transceiver array communicating with a plurality of satellites. 
           [0006]      FIG. 1B  shows details of an example implementation of the single-unit-cell transceiver array of  FIG. 1A . 
           [0007]      FIG. 2A  shows a transceiver which comprises a plurality of the unit cells of  FIG. 1B  and is communicating with a plurality of satellites. 
           [0008]      FIG. 2B  shows details of an example implementation of the transceiver of  FIG. 1A . 
           [0009]      FIG. 3  shows a hypothetical ground track of a satellite system in accordance with aspects of this disclosure. 
           [0010]      FIG. 4A  depicts transmit circuitry of an example implementation of the unit cell of  FIG. 1B . 
           [0011]      FIG. 4B  depicts an example implementation of the per-element digital signal processing circuit of  FIG. 4A . 
           [0012]      FIG. 4C  depicts an example nine-element antenna array. 
           [0013]      FIG. 4D  illustrates use of an antenna weighting window and single clipping threshold for driving the example array of  FIG. 4C . 
           [0014]      FIG. 4D  illustrates use of an antenna weighting window and window-weighted clipping thresholds for driving the example array of  FIG. 4C . 
           [0015]      FIG. 4E  illustrates use of an antenna weighting window and tapered clipping thresholds for driving the example array of  FIG. 4C . 
           [0016]      FIG. 4F  illustrates use of an antenna weighting window and tapered clipping thresholds for driving the example array of  FIG. 4C . 
           [0017]      FIG. 5  is a flowchart illustrating an example process for crest factor reduction in accordance with an example implementation of this disclosure. 
           [0018]      FIG. 6  illustrates an example weighting window applied to an array of antenna elements. 
           [0019]      FIG. 7A  illustrates an example of per-antenna-element PAPR using a single clipping threshold across all elements of an antenna array. 
           [0020]      FIG. 7B  illustrates an example antenna pattern achieved using the single clipping threshold technique of  FIG. 7A . 
           [0021]      FIG. 8A  illustrates an example of per-antenna-element PAPR when each antenna element&#39;s clipping threshold is scaled in proportion to the weighting window applied across the antenna array. 
           [0022]      FIG. 8B  illustrates an example of per-antenna-element PAPR using the window-weighted clipping technique of  FIG. 8A . 
           [0023]      FIG. 8C  illustrates an example antenna pattern achieved using the window-weighted clipping technique of  FIG. 8A . 
           [0024]      FIG. 9A  illustrates an example of per-antenna-element PAPR when using clipping thresholds whose absolute values decrease relative to the weighting window as the distance of the element from the center of the array increases. 
           [0025]      FIG. 9B  illustrates an example of per-antenna-element PAPR using the tapered clipping technique of  FIG. 9A . 
           [0026]      FIG. 9C  illustrates an example antenna pattern achieved using the tapered clipping technique of  FIG. 9A . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0027]      FIG. 1A  shows a single-unit-cell transceiver array communicating with a plurality of satellites. Shown in  FIG. 1A  is a device  116  comprising a transceiver array  100  operable to communicate with a plurality of satellites  102 . The device  116  may, for example, be a phone, laptop computer, or other mobile device. The device  116  may, for example, be a desktop computer, server, or other stationary device. In the latter case, the transceiver array  100  may be mounted remotely from the housing of the device  116  (e.g., via fiber optic cables). Device  116  is also connected to a network (e.g., LAN and/or WAN) via a link  118 . 
         [0028]    In an example implementation, the satellites  102  shown in  FIGS. 1A and 2A  are just a few of hundreds, or even thousands, of satellites having a faster-than-geosynchronous orbit. For example, the satellites may be at an altitude of approximately 1100 km and have an orbit periodicity of around 100 minutes. 
         [0029]    Each of the satellites  102  may, for example, be required to cover 18 degrees viewed from the Earth&#39;s surface, which may correspond to a ground spot size per satellite of ˜150 km radius. To cover this area (e.g., area  304  of  FIG. 3 ), each satellite  102  may comprise a plurality of antenna elements generating multiple spot beams (e.g., the nine spot beams  302  of  FIG. 3 ). In an example implementation, each of the satellites  102  may comprise one or more transceiver array, such as the transceiver array  100  described herein, operable to implement aspects of this disclosure. This may enable steering the coverage area of the spot beams without having to mechanically steer anything on the satellite  102 . For example, when a satellite  102  is over a sparsely populated area (e.g., the ocean) but approaching a densely populated area (e.g., Los Angeles), the beams of the satellite  102  may be steered ahead such that they linger on the sparsely populated area for less time and on the densely populated area for more time, thus providing more throughput where it is needed. 
         [0030]    As shown in  FIG. 1B , an example unit cell  108  of a transceiver array  100  comprises a plurality of antenna elements  106  (e.g., four antenna elements per unit cell  108  in the examples of  FIG. 1B and 2B ; and ‘N’ per unit cell in the example of  FIG. 4A ), a transceiver circuit  110 , and, for a time-division-duplexing (TDD) implementation, a plurality of transmit/receive switches  108 . The respective power amplifiers (PAs) for each of the four antenna elements  106   1 - 106   4  are not shown explicitly in  FIG. 1B  but may, for example, be integrated on the circuit  110  or may reside on a dedicated chip or subassembly (as shown, for example, in  FIG. 4A , below). The antenna elements  106 , circuit  110 , and circuit  108  may be mounted to a printed circuit board (PCB)  112  (or other substrate). The components shown in  FIG. 1B  are referred to herein as a “unit cell” because multiple instances of this unit cell  108  may be ganged together to form a larger transceiver array  100 . In this manner, the architecture of a transceiver array  100  in accordance with various implementations of this disclosure may be modular and scalable.  FIGS. 2A and 2B , for example, illustrate an implementation in which four unit cells  108 , each having four antenna elements  106  and a transceiver circuit  110 , have been ganged together to form a transceiver array  100  comprising sixteen antenna elements  106  and four transceiver circuits  110 . The various unit cells  108  are coupled via lines  202  which, in an example implementation represent one or more data busses (e.g., high-speed serial busses similar to what is used in backplane applications) and/or one or more clock distribution traces (which may be referred to as a “clock tree,” as described below with reference to  FIGS. 11A, 11B, 12A, and 12B ). 
         [0031]    Use of an array of antenna elements  106  enables beamforming for generating a radiation pattern having one or more high-gain beams. In general, any number of transmit and/or receive beams are supported. 
         [0032]    In an example implementation, each of the antenna elements  106  of a unit cell  108  is a horn mounted to a printed circuit board (PCB)  112  with waveguide feed lines  114 . The circuit  110  may be mounted to the same PCB  112 . In this manner, the feed lines  114  to the antenna elements may be kept extremely short. For example, the entire unit cell  108  may be, for example, 6 cm by 6 cm such that length of the feed lines  114  may be on the order of centimeters. The horns may, for example, be made of molded plastic with a metallic coating such that they are very inexpensive. In another example implementation, the antenna elements  106  may be, for example, stripline or microstrip patch antennas. 
         [0033]    The ability of the transceiver array  100  to use beamforming to simultaneously receive from multiple of the satellites  102  may enable soft handoffs of the transceiver array  110  between satellites  102 . Soft handoff may reduce downtime as the transceiver array  100  switches from one satellite  102  to the next. This may be important because the satellites  102  may be orbiting at speeds such that any particular satellite  102  only covers the transceiver array  100  for on the order of 1 minute, thus resulting in very frequent handoffs. For example, satellite  102   3  may be currently providing primary coverage to the transceiver array  100  and satellite  102   1  may be the next satellite to come into view after satellite  102   3 . The transceiver array  100  may be receiving data via beam  104   3  and transmitting data via beam  106  while, at the same time, receiving control information (e.g., a low data rate beacon comprising a satellite identifier) from satellite  102   1  via beam  104   1 . The transceiver array  100  may use this control information for synchronizing circuitry, adjusting beamforming coefficients, etc., in preparation for being handed-off to satellite  102   1 . The satellite to which the transceiver array  100  is transmitting may relay messages (e.g., ACKs or retransmit requests) to the other satellites from which transceiver array  100  is receiving. 
         [0034]      FIG. 4A  depicts transmit circuitry of an example implementation of the unit cell of  FIG. 1B . In the example implementation shown, circuit  110  comprises a SERDES interface circuit  402 , synchronization circuit  404 , local oscillator generator  442 , pulse shaping filters  406   1 - 406   M  (M being an integer greater than or equal to 1), squint filters  408   1 - 408   M , per-element digital signal processing circuits  410   1 - 410   N , DACs  412   1 - 412   N , filters  414   1 - 414   N , mixers  416   1 - 416   N , and drivers  418   1 - 418   N . The outputs of the PA drivers  418   1 - 418   N  are amplified by PAs  420   1 - 420   N  before being transmitted via antenna elements  106   1 - 106   N . 
         [0035]    The SERDES interface circuit  402  is operable to exchange data with other instance(s) of the circuit  110  and other circuitry (e.g., a CPU) of the device  116 . 
         [0036]    The synchronization circuit  404  is operable to aid synchronization of a reference clock of the circuit  110  with the reference clocks of other instance(s) of the circuit  110  of the transceiver array  100 . 
         [0037]    The local oscillator generator  442  generates one or more local oscillator signals  444  based on the reference signal  405 . 
         [0038]    The pulse shaping filters  406   1 - 406   M  (M being an integer greater than or equal to 1) are operable to receive bits to be transmitted from the SERDES interface circuit  402  and shape the bits before conveying them to the M squint processing filters  408   1 - 408   M . In an example implementation, each pulse shaping filter  406   m  processes a respective one of M datastreams from the SERDES interface circuit  402 . 
         [0039]    Each of the squint filters  408   1 - 408   M  is operable to compensate for the relatively wide bandwidth of the signals  409   1 - 409   M , such that the signals  409   1 - 409   M  can be phase shifted by circuits  410   1 - 410   N  without causing different transmit directionalities for different frequencies (i.e., without the squint filters/processors  408 , application of a uniform phase shift across all frequencies of a signal  409   m  may result in different frequencies pointing in different directions). Each squint filter/processor  408   m  is operable to receive a datastream  407   m , process it to compensate for squint effects, and then outputs it to an associated one or more transmit paths (each transmit path corresponding to one of antenna elements  106   1 - 106   N ). In the example shown, each squint filter  408   m  (m being an integer between 1 and M) processes datastream  407   m  to generate signal  409   m , which is then output to each of the N transmit paths. Thus, in this example, for C (an integer) instances of circuit  110  in a transceiver array  100 , each squint processor/filter  408   m  handles squint processing for N of the N×C antenna elements  106  of the transceiver array  100 . Which N antenna elements of the total of N×C antennas are coupled to any particular one of the C circuits  110  may be selected based on the squint effects seen at those elements (e.g., a first group of N antenna elements  106  which are a similar distance from a feed point of the antenna array may be coupled to a first circuit  110 , a second group of N antenna elements  106  which are a similar distance from a feed point of the antenna array may be coupled to a second circuit  110 , and so on). 
         [0040]    In another example implementation, each beam  407   m  may be coupled to a plurality of the squint filters/processors  408   1 - 408   M , and the output of each of the squint filters/processors  408   1 - 408  may go to only a subset of the N antenna elements (a subset experiencing similar squint effects). 
         [0041]    The number of squint processors/filters  408  (i.e., the value of M) and/or the number of  408   1 - 408   M  which are active (i.e., not powered down) on a circuit  110  may be configured based on a trade-off between power consumption and ability to tolerate squint effects. In general, squint effects are less pronounced for smaller arrays. Thus, aspects of this disclosure enable dividing the large array of N×C elements into smaller subarrays (e.g., of C, or fewer, elements) where the subarray is small enough—and the squint effects they experience similar enough—that uniform squint processing can be applied across the signals fed to the subarray. 
         [0042]    In an example implementation, the compensation applied by a squint processor/filter  408  may be dither (e.g., pseudorandomly) between the multiple values (e.g., the two values closest to the desired value), such that side lobes resulting from quantizing the squint values are spread out. 
         [0043]    Each of the per-element digital signal processing circuits  410   1 - 410   N  is operable to perform processing on the signals  409   1 - 409   M . Each one of the circuits  410   1 - 410   N  may be configured independently of each of the other ones of the circuits  410   1 - 410   N  such that each one of the signals  411   1 - 411   N  may be processed as necessary/desired without impacting the other ones of the signals  411   1 - 411   N . An example implementation of the per-element signal processing circuit  410  is described below with reference to  FIG. 4B . 
         [0044]    Each of the DACs  412   1 - 412   N  is operable to convert a respective one of the digital signals  411   1 - 411   N  to an analog signal. Each of the filters  414   1 - 414   N  is operable to filter (e.g., anti-alias filtering) the output of a respective one of the DACs  412   1 - 412   N . Each of the mixers  416   1 - 416   N  is operable to mix an output of a respective one of the filters  414   1 - 414   N  with the local oscillator signal  444 . Each of the PA drivers  418   1 - 418   N  conditions an output of a respective one of the mixers  416   1 - 416   N  for output to a respective one of PAs  420   1 - 420   N . In a non-limiting example, each PA driver  418   n  (n being an integer between 1 and N) is operated at 10 dB from its saturation point and outputs a 0 dBm signal. In a non-limiting example, each PA  420   n  is operated at 7 dB from its saturation point and outputs a 19 dBm signal. 
         [0045]      FIG. 4B  depicts an example implementation of the per-element digital signal processing circuit of  FIG. 4A . The circuit  410   n  comprises complex scaling circuits  452   1 - 452   M , a summer  454 , a scaling circuit  462 , a crest factor reduction circuit  456 , a digital predistortion circuit  464 , and coefficient generation circuit  466 . 
         [0046]    The weight generation circuit  466  receives the azimuthal angle θ m  and the elevation angle φ m  for each beam m of the M beams to be transmitted. The weight generation circuit  466  also receives information about one or more sidelobes that is desired to suppress/cancel. The sidelobes may be the result of the operations performed by the CFR circuit  456 . Example details of selecting the sidelobes to be suppressed and calculating the coefficients L 1   d  to L M   d  are described below with reference to  FIG. 10 . An example implementation of the weight generation circuitry  466  is described below with reference to  FIG. 4G . 
         [0047]    Each of the complex scaling circuits  452   1 - 452   M  is operable to apply a complex beamforming coefficient generated by circuit  466  to (i.e., adjust the phase and amplitude of) a respective one of signals  409   1 - 409   M . 
         [0048]    The summer  454  is operable to combine the M signals from the scaling circuits  452   1 - 452   M  to generate signal  463 . 
         [0049]    The digital predistortion circuit  464  is operable to modify (“predistort”) the signal  463   n  to generate signal  455   n  the result of the predistortion being suppression/cancellation of out-of-band distortion which will subsequently be generated by crest factor reduction circuit  456 . 
         [0050]    The scaling circuit  462   n  is operable to apply a gain S n  according to the array weighting window in use. Accordingly, the gain S n  used for any particular antenna element  106   n  may depend on the position of the antenna  106   n  within the array. For example, referring to the example nine-element array of  FIG. 4C , the gain S 1  applied by scaling element  462   1  may be different than the gain S 2  and so on. In an example implementation, the gain S n  of any scaling element  462   n  may be a function of the X and Y indexes of antenna element  106   n.  As just one example, for values of n from 1-9 in the example of  FIG. 4C , S n  may depend on √{square root over (X n   2 +Y n   2 )} (i.e., depend on the distance from the center of the array), where X n  is the X index of antenna element  106   n  (e.g., X n =−1 for n=1, X n =0 for n=2, X n =1 for n=3, X n =−1 for n=4, and so on), and Y n  is the Y index of antenna element  106   n  (e.g., Y n =1 for n=1, Y n =1 for n=2, Y n =1 for n=3, Y n =0 for n=4, and so on). 
         [0051]    Returning to  FIG. 4B , The crest factor reduction circuit  456  then operates on the signal  463  to determine if reduction of its peak-to-average power ratio (PAPR) is desired and, if so, to try and reduce the PAPR. In this manner, the PAPR may be managed separately for each transmit chain/antenna element. 
         [0052]    In an example implementation, each circuit  410   n  also comprises a circuit  460  to manage spectral regrowth/out-of-band power that results from clipping. Each circuit  460  may be configured to introduce a phase shift to out-of-band frequencies while leaving the phase of in-band frequencies unaffected. In this manner, undesired side lobes resulting from clipping may be suppressed to minimize their impact at the receiver. For example, each circuit  460  may introduce a random phase shift to the out-of-band power resulting from clipping in the various transmit paths does not coherently combine in the direction of an intended receiver (e.g., the out-of-band power may be scattered randomly over a wide range of angles). Alternatively, each circuit  460  may introduce a phase shift to the out-of-band power in the various transmit paths such that the undesired side lobes coherently combine in a direction away from the intended receiver(s). 
         [0053]    PAPR reduction performed by circuit  456   n  comprises digitally clipping the signal  463  if it is above a determined clipping threshold C n .  4 D- 4 F illustrate three example clipping techniques for the example nine-antenna array of  FIG. 4C . In each of  FIGS. 4D-4F , S 5  is set such that the peak power of signal  463   5  is level  482 ; S 1 , S 3 , S 7 , and S 9  are set such that the peak power of each of signals  463   1 ,  463   3 ,  463   7 , and  463   9  is level  484 ; and S 2 , S 4 , S 6 , and S 8  are set such that the peak power of each of signals  463   2 ,  463   4 ,  463   6 , and  463   8  is level  486 . This weighting window is just an example and is used in each of  FIGS. 4D-4F  for comparison of various clipping techniques. A 3-D plot of this type of weighting window is shown in  FIG. 6 . It is also noted that, for purposes of illustration, each signal  463   1 - 463   9  in  FIGS. 4D-4F  is shown swinging to the limit determined by the weighting window. In another example implementation, the CFR circuit  456  performs soft compression instead of, or in addition to, clipping. For example, it may perform soft compression above a first threshold and then clipping above a second threshold. 
         [0054]    A first example clipping technique, shown in  FIG. 4D , comprises using the same absolute clipping threshold for each of the scaling circuits  462   n . In the example shown, each of clipping thresholds C 1 -C 9  is set to a level which is located between  482  and  484 . In this example, only signal  463   5  may be clipped since the applied window prevents the other signals  463  from reaching the clipping threshold. The cross-hatched area indicates the clipped portion of the signal. Referring briefly to  FIG. 7A , using this clipping technique may result in lower PAPR where clipping occurs (near the center element(s) in the example shown). Referring briefly to  FIG. 7B , an example antenna pattern comprising 27 desired beams from an array using the clipping scheme of  FIG. 4C  is shown. 
         [0055]    A second example clipping technique, shown in  FIG. 4E , comprises using the same relative (relative to the weighting window) clipping threshold for each of the antenna elements in the array. In the example shown in  FIG. 4E , each of clipping thresholds C n  is set to Δ% below the limit determined by the weighting window (and set by  462   n ). In this example, up to Δ% of each signal  463  may be clipped. Referring briefly to  FIG. 8A , the clipping technique of  FIG. 4E  is illustrated by a 3D plot showing clipping level relative to the window weighting. As shown in  FIG. 8B , this clipping technique may result in relatively uniform PAPR across the array. This uniform PAPR may be desirable but, as shown in  FIG. 8C , may come at the cost of increased undesired side lobe levels as compared to  FIG. 7B . 
         [0056]    A third example clipping technique, shown in  FIG. 4F , comprises using different relative (relative to the weighting window) clipping thresholds for scaling circuits  462 . In the example shown in  FIG. 4F , the relative threshold is tapered based on distance from the center of the array. That is, C 5  is set α% below level  482 ; C 2 , C 4 , C 6 , and C 8  are set β% below  484 , and C 1 , C 3 , C 5 , and C 7  are set γ% below level  486 , wherein α&lt;β&lt;γ. Referring briefly to  FIG. 9A , the clipping technique of  FIG. 4E  is illustrated by a 3D plot showing a clipping level relative to the window weighting for an example implementation. As shown in  FIG. 9B , this clipping technique may result in PAPR that tapers off toward the center of the array. As shown in  FIG. 9C , this clipping technique may achieve side lobe levels that are between those of  FIGS. 7B and 8C . 
         [0057]    Now referring to  FIG. 5 , in block  502 , circuit  456  of each transmit chain receives a sample of its respective signal  455 . In block  505 , circuit  456  of each of a subset of the transmit chains (“Group A”) determines that the power of its sample is above a threshold and radially clips (i.e., clips the amplitude without affecting the phase) the sample to a level equal to or below the threshold. In an example implementation, the clipping may comprise a series of clips with filtering in between, with the series of clips and filters configured to optimize out-of-band power and/or in-band EVM. 
         [0058]    Each circuit  456  of Group A then reports the clipping event to a CFR coordinator (e.g., one of the circuits  456  of one of the circuits  110  or array  100  may be selected as CFR coordinator based on some selection criteria, a CPU of the device  116  may operate as CFR coordinator, or some other circuitry of the transceiver array  100 ). In block  506 , the CFR coordinator determines which transmit chains (“Group B”) can tolerate additional power (e.g., because there is at least a determined amount of headroom between their respective sample powers and the clipping threshold). In block  508 , the CFR coordinator computes compensating signals to be applied to one or more of the signal(s)  457  in Group B. The compensating signals may radially boost the power of such signals  457  in Group B a manner that compensates for the power “lost” in Group A due to the clipping. The compensating signal(s) may replace some or all of the power “lost” due to clipping. Due to the fact that the lost power radiates in a certain radiation pattern that can be precomputed (because the lost power only drives antennas elements of Group A), the amplitude and phase of the compensating signal(s) can be computed to restore the signal  457  in the desired directions of each beam. In an example implementation in which N beams are transmitted, each of compensating signals for each of the N beams may be computed individually, and then the N compensating signals may be superimposed. This may be applied in situations where the side lobes produced by the compensating signals are sufficiently low. In other situations, more complex methods for calculating the compensating signals may be used. 
         [0059]    Given constant adjacent channel leakage ratio and sidelobe level, the adding back of clipped power may enable a clipping threshold that is 0.5 dB or more below the clipping threshold that would otherwise be required. This translates to significant improvement in PA efficiency. 
         [0060]    As utilized herein the terms “circuits” and “circuitry” refer to physical electronic components (i.e. hardware) and any software and/or firmware (“code”) which may configure the hardware, be executed by the hardware, and or otherwise be associated with the hardware. As used herein, for example, a particular processor and memory may comprise a first “circuit” when executing a first one or more lines of code and may comprise a second “circuit” when executing a second one or more lines of code. As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. In other words, “x and/or y” means “one or both of x and y”. As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, “x, y and/or z” means “one or more of x, y and z”. As utilized herein, the term “exemplary” means serving as a non-limiting example, instance, or illustration. As utilized herein, the terms “e.g.,” and “for example” set off lists of one or more non-limiting examples, instances, or illustrations. As utilized herein, circuitry is “operable” to perform a function whenever the circuitry comprises the necessary hardware and code (if any is necessary) to perform the function, regardless of whether performance of the function is disabled or not enabled (e.g., by a user-configurable setting, factory trim, etc.). 
         [0061]    Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be realized in a centralized fashion in at least one computing system, or in a distributed fashion where different elements are spread across several interconnected computing systems. Any kind of computing system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computing system with a program or other code that, when being loaded and executed, controls the computing system such that it carries out the methods described herein. Another typical implementation may comprise an application specific integrated circuit or chip. Other embodiments of the invention may provide a non-transitory computer readable medium and/or storage medium, and/or a non-transitory machine readable medium and/or storage medium, having stored thereon, a machine code and/or a computer program having at least one code section executable by a machine and/or a computer, thereby causing the machine and/or computer to perform the processes as described herein. 
         [0062]    While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.