Abstract:
In an aspect of the present invention, a speech synthesizer timepiece is provided which is easy and convenient to handle by providing a single common switch useful for starting the timekeeping operation, outputting the results of the timekeeping and delivering an audible indication of the results of the timekeeping.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a speech synthesizer timepiece capable of providing an audible indication of time information. 
     In the past, timepieces capable of providing an audible indication of time information were proposed, which had a start/stop key (for use as a stopwatch) and a sound key (for delivery of an audible indication). However, provided that the stopwatch key and the sound key were separate and discrete, the user would look at a key input section to confirm which of the keys to depress. This is inconvenient for use as a stopwatch by which the user wishes to audibly confirm the results of timekeeping while tracing a moving object. In other words, the user would first visually confirm which of the keys to depress and then manually depress the selected key and hear an audible indication of the results of the timekeeping. 
     OBJECTS AND SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a speech synthesizer timepiece which provides ease of key operations. 
     It is another object of the present invention to provide a speech synthesizer timepiece which is easy and convenient to operate by providing a single common switch useful for starting a timekeeping operation, outputting the results of the timekeeping and delivering an audible indication of the results of the timekeeping. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and for further objects and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a block diagram of a speech synthesizer timepiece according to an embodiment of the present invention; and 
     FIG. 2 is a flow chart for explanation of the operation of the circuit of FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to FIG. 1, there is illustrated a speech synthesizer timepiece according to a preferred embodiment of the present invention, which generally includes an instruction storage RU (program memory) typically of a read only memory, an address register RAR, an address decoder RDC and an instruction selector RUG. Decision signals S b  from respective decision circuits are applied to the instruction selector, which signals S b  are used to branch program steps. An instruction decoder IM develops a string of microinstructions  1 ,  2 , . . .  n  and control signals S a  in response to signals transferred via an instruction selection gate RUG based on the contents of the program memory RU. 
     The timepiece comprises components as follows for the purpose of timekeeping; a clock generator CG, a divider DV connected to the clock generator CG for developing a time standard, a timekeeping counter CO connected via a timekeeping control gate GC to the divider DV, a counter C for counting elapsed time upon actuation of a key and a decision circuit JC for deciding whether the count of the counter C reaches a predetermined count. 
     A selection gate G is provided for the selection of information (word codes and the results of timekeeping) to be audibly delivered. A buffer register is labeled B, a voice output control VCC and a loud speaker SP. 
     There is further provided a key switch T for starting the timekeeping, and a means for outputting the results of the timekeeping and delivering an audible indication of the results of the timekeeping, which plays an important role in the present invention. There are further provided a decision circuit JT for deciding if the key switch T has been actuated, a mode selector slide switch M for selecting either a normal mode or an accumulation mode discussed hereafter, a decision circuit JM for the switch M, and flip flops F 1  and F 2  with associated decision circuits JF 1  and JF 2  for deciding if the flip flops F 1  and F 2  are in the set or reset state. 
     FIG. 2 is a flow chart for the explanation of the operation of the circuit of FIG. 1. The illustrated embodiment has two operation modes: the normal mode by which the results of the timekeeping are cleared when the timekeeping comes into a temporary stop for any reason and the next timekeeping starts beginning with &#34;0&#34;; and the accumulation mode by which the results of the timekeeping are kept unchanged when the timekeeping comes into a temporary stop and the timekeeping re-starts beginning with the previous or stored count. 
     It is noted that the flip flops F 1  and F 2  are reset before timekeeping starts. 
     (1) Normal Mode 
     Upon actuation of the key switch T the timepiece proceeds from operation of the step S 1  to S 2 . Step S 2  is carried out to reset the counter C (micro-instruction  3 ) and the next step S 3  is carried out to decide the operation state of the flip flop F 1 . With the flip flop F 1  in the reset state, step S 4  is effected to decide whether the mode is in the normal mode of the accumulation mode. Step S 5  is effected if in the normal mode so that the counter CO is reset (micro-instruction  4 ). This step is followed by step S 6  whereby timekeeping is initiated (micro-instruction  9 ). The next step S 7  resets the flip flop F 1  (micro-instruction  5 ). Then, the step S 8  delivers a timekeeping start sound P 1  (e.g., &#34;peep&#34;), while step S 9  delivers an audible indication of the count of the counter CO (e.g., &#34;its now 00 sec&#34;). Thereafter, the step S 1  is resumed. 
     Unless the switch T is actuated under the circumstance, the above timepiece effects step S 10  which decides whether the count of the counter C indicates the elapse of 2 sec. Since the timepiece has just started timekeeping, the count of the counter C does not show the elapse of 2 sec and executes step S 11  wherein the flip flop F 2  is reset (micro-instruction  7 ). Then, it is time for execution of a loop of the steps S 1  →S 10  →S 11  →S 1 . After the passage of 2 sec the step S 10  senses that 2 sec have passed as decided by the count of the counter C and the step S 12  serves to reset the flip flop F 2  (micro-instruction  8 ). The loop of the program steps S 1  →S 10  →S 12  →S 1  is repeated until the switch T is newly actuated. If the switch T is then actuated (instructing the results of timekeeping to be outputted), step S 7  is effected to set the flip flop F 1  via the steps S 2  and S 3 , followed by step S 13  which senses the operating state of the flip flop F 2 . With the flip flop F 2  being reset through step S 12 , the timepiece proceeds with step S 9  for delivering an audible indication of the results of the timekeeping or updated time of the day. Then, the timepiece returns to the step S 1  and executes a loop of the steps S 1  →S 10  →S 11  →S 1  →S 10  →S 12  →S 1  until the switch T is newly depressed. The above-described procedure measures the so-called lap time by which to count and display the elapsed time after the first actuation of the switch T whenever the switch T is actuated. 
     The following will set forth the manner by which timekeeping is discontinued upon first actuation of the switch T and started begining with &#34;0&#34; upon the second actuation of the switch T. This routine is executed when the switch T is actuated with the flip flop S 11  in the set state during this step S 11 . In other words, the situation results when the switch T is actuated sequentially twice. In this case, step S 13  provides the answer YES and leads to the step S 14  which discontinues timekeeping (micro-instruction  9 ). The flip flop F 1  is reset through the step S 15  (micro-instruction  6 ) and a sound P 2  indicating the interruption of timekeeping (e.g., &#34;peep peep&#34;) is delivered through the step S 16 . The next step S 9  permits an audible indication of the count of the counter CO to be delivered. If the switch T is newly depressed under this circumstance, then the flip flop F 1  is reset to execute the steps S 3  and S 4 . Since the flip flop F 1  is reset through the step S 5 , the next timekeeping starts beginning with &#34;0&#34; in the counter CO. In this manner, it is possible to start timekeeping beginning with the count &#34;0&#34; upon depression of the switch T. 
     (2) Accumulation Mode 
     This mode is substantially similar to the normal mode except for the step S 4  as follows. If step S 4  is answered YES, then step S 6  is effected. In this mode, the step S 5  is eliminated. Because of the counter CO not in the reset state, a new result timekeeping is added to the counter CO is in the stop state upon actuation of the switch T. 
     The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following claims.