Abstract:
A method drives a three-phase motor having first, second, and third coils. The method electrically connects the first coil to a first voltage reference and the second coil to a second voltage reference while leaving the other coil floating during a first driving phase. During a second driving phase, the first coil is electrically connected to the first voltage reference and the third coil is electrically connected to the second voltage reference while the second coil is left floating. During a transition phase that immediately follows the fast driving phase and immediately precedes the second driving phase, the second coil is electrically connected alternately to the first and second voltage references. By alternately connecting the second coil to the first second voltage references and during the transition phase, the method causes the current through the second coil to reduce to zero at a slower rate than prior methods. This enables the variations of the currents that the two phases in commutation, the second and third coils, to happen in a way that maintains their sum constant, as much as possible. This reduces the torque ripple during the phase commutations and its accompanying acoustic noise.

Description:
TECHNICAL FIELD 
     The present invention relates to DC motors, and more particularly, to reducing the noise generated during phase commutation of a three phase, current controlled motor. 
     BACKGROUND OF THE INVENTION 
     Three-phase brushless DC motors have many uses, among which are as spindle motors for computer hard disk drivers, digital video disk (DVD) drivers, CD players, and tape-drives for video recorders. Such motors are recognized as having the highest torque and power capability for a given size and weight Compared to DC motors employing brushes, brushless DC motors enjoy reduced noise generation and improved reliability because no brushes need to be replaced due to wear. 
     FIG. 1 shows such a three-phase brushless DC motor  10  with three phases A, B, C having three coils  12 ,  14 ,  16  connected to each other in a Y-configuration at a center tap  18 . As is well-known, the coils  12 ,  14 ,  16  are part of a stator that causes a permanent magnet rotor to rotate. The first coil  12  (phase A) is connected to a supply voltage Vret by a first high-side transistor  20  and to ground via a first low-side transistor  22  and a sense resistor  23 ; the second coil  14  (phase B) is connected to the supply voltage Vret by a second high-side transistor  24  and to ground via a second low-side ransistor  26  and the sense resistor; and the third coil  16  (phase C) is connected to the supply voltage Vret by a third high-side transistor  28  and to ground by a third low-side transistor  30  and the sense resistor  23 . Each of the transistors is an NMOS transistor as is typical. Represented in FIG. 1 by voltage supply symbols are respective back EMF sources EA, EB, EC that are inherently induced by the permanent magnets of the rotor while the rotor is rotated. 
     This type of motor is driven by exciting its phases in a suitable sequence while always keeping two phases under power and leaving a third phase in tristate or floating with a high impedance (Z). For example, assume that initially the fist high-side transistor  20  and the second low-side transistor  26  are activated with high control signals on their gates while the other transistors are inactive. This results in a current IA through the first phase A having a value of +I, a current IB through the second phase having a value of −I, and zero current IC through the third phase as shown in FIG.  2 . At predetermined instances (t1, t2, . . . ) the driving of the phase switches so that current is driven through the phase that was previously floatin and one of the other phases is left floating such that the algebraic sum of the currents in the three phases are always equal to zero. In FIG. 2 the driving sequence is as follows where the first letter indicates the phase of positive current flow and the second letter indicates the phase of negative current flow: 
     
       
         AB-AC-BC-BA-CA-CB. 
       
     
     In the instant of commutation from one stage to another (instances t1, t2, . . . ), if the current front were infinite, one would ideally find a system without perturbations. For example, at the instant t1, the phase A would maintain the current +I while the phases B and C would exchange the current flow, one from −I to 0 and the other from 0 to −I. 
     In reality, because of the presence of different time constants in the circuit, the commutation fronts of the two currents (IB and IC in the example of instant t1) would be non-ideal and non-synchronous. That is, the current IC increases more slowly than the current IB decreases. This translates into a variation of the current IA instead of the current IA remaining constant. The current variation generates torque ripple in the motor and much acoustic noise. 
     Analyzing the scheme of FIG. 1, it is possible to determine the reasons for the different commutation times in the two interested phases. At instant t1 (before the commutation) we would have: 
     VoutA=Vret IA=I 
     VoutB=0 IB=−I 
     VoutC=Vct IC=0 
     Vct=½ Vret 
     Given that the phases are out of phase by 120°, the electromotive forces driven will be instantaneously algebraically summed to zero. The commutation moreover happens at the instant t1 at the end of optimizing the torque ripple in the system. The back EMF in the three phases would have the following values: EA=E, EB=EC=−E/2, where E equals the maximum back EMF. 
     In the instant just after the commutation we would have: 
     VoutA=Vret 
     VoutB=Vret+Vbe (due to the current of coil B recirculating in the intrinsic diode of second high-side transistor  24 , where Vbe equals the drop across that intrinsic diode) 
     VoutC=0 
     Vct=⅔ Vret. 
     The back EMF values will remain instantaneously unchanged. 
     The voltage across the second coil  14  is therefore: 
     
       
         VoutB−(Vct+EB)=Vret+Vbe−(⅔Vret−E/2)=⅓Vret+Vbe+E/2, 
       
     
     while the voltage across the third coil  16  is: 
     
       
         VoutC−(Vct+EC=0−(⅔Vret−E/2)=E/2−⅔Vret. 
       
     
     The two voltages will therefore be significantly different, creating different time constants of charge/discharge of the two currents (IB will be reduced more quickly than C will be increased). 
     SUMMARY OF THE INVENTION 
     An embodiment of the invention is directed to a method and motor driver for driving a three-phase motor having first, second, and third coils. The method electrically connects the first coil to a first voltage reference and the second coil to a second voltage reference while leaving the other coil floating during a fist driving phase. During a second driving phase, the first coil is electrically connected to the first voltage reference and the third coil is electrically connected to the second voltage reference while the second coil is left floating. During a transition phase that immediately follows the first driving phase and immediately precedes the second driving phase, the second coil is electrically connected alternately to the first and second voltage references. By alternately connecting the second coil to the first and second voltage references and during the transition phase, the method causes the current through the second coil to reduce to zero at a slower rate than prior art methods. This enables the variations of the currents what the two phases in commutation, the second and third coils, to happen in a way that maintains their sum substantially constant. This reduces the torque ripple occurring during phase commutations and its accompanying acoustic noise. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a three-phase brushless motor according to the prior art. 
     FIG. 2 is a timing diagram of the currents through the respective phases of is the motor shown in FIG.  1 . 
     FIG. 3 is a circuit diagram of a three-phase brushless motor according to an embodiment of the present intention. 
     FIG. 4 is a timing diagram of the control signals applied to the gates of the control transistors of the motor shown in FIG.  3 . 
    
    
     DETAILED DESCRIPTION 
     A three-phase brushless motor  50  according to be present invention is shown in FIG.  3 . The motor  50  includes three coils  52 ,  54 ,  56  connected to each other in a Y-configuration at a center tap  58 . The first coil  52  is connected to a supply voltage Vret by a first high-side transistor  60  and to the ground via a first low-side transistor  62  and a sense resistor  64 ; the second coil  54  is connected to the supply voltage Vret by a second high-side transistor  66  and to ground via a second low-side transistor  68  and the sense resistor  64 ; and the third coil  56  is connected to the supply voltage Vret by a third high-side transistor  70  and to ground by a third low-side transistor  72  and the sense resistor  64 . Each of the transistors  60 - 62 ,  66 - 68 ,  70 - 72  is typically an NMOS transistor. Represented in FIG. 3 by voltage supply symbols are respective back EMF sources EA, EB, EC that are inherently introduced by the permanent magnets of the rotor while the rotor is rotated. 
     The motor  50  also includes control logic  74  coupled to the gates of the control transistors  60 - 62 ,  66 - 68 ,  70 - 72  in order to control the activation and deactivation of those transistors. In this matter, the control logic  74  controls which of the coils  52 - 56  are supplied with current and in which direction the current flows through those coils. The control logic  74  includes a pulse width modulation (PWM) signal generator  76  that generates PWM control signals as described in more detail below. The control logic is coupled to an output of a comparator  78  having an inverting input coupled to a voltage reference (Vref) and a non-inverting terminal coupled to a node  80  between the sense resistor  64  and each of the low-side transistors  62 ,  68 ,  72 . 
     Shown in FIG. 4 is a schematic timing diagram of the control signals applied to the gates of the control transistors  60 - 62 ,  66 - 68 ,  70 - 72  by the control logic  74  of FIG.  3 . During successive driving phases, we will have one phase driven in PWM, one phase short-circuited toward ground (through the sense resistor  64 ), and the third phase remains in tristate. In a first driving phase D 1 , the first coil  52  is driven in PWM, the second coil  54  is coupled to ground, and the third coil  56  is in tristate. Coil  52  drive is accomplished by driving the gate of the first high-side transistor  60  with a first PWM control signal, driving the gate of the first low-side transistor  62  with a second PWM control signal (an inversion of the first PWM control signal). Coil  54  drive is obtained driving the second low-side transistor  68  with a constant high signal. Remaining transistors  66 , 70 , 72  are driven by applying logic low control signals. The current IA through the first coil  52  will be I, the current IB through the second coil  54  will be −I and the current IC through the third coil  56  will be zero. The comparator  78  enables the control logic  74  to control the current through the coils by adjusting the first and second PWM control signals as needed based on the current Is through the sense resistor  64  as detected by the comparator. 
     If we want to effectuate a phase change between the phases B and C (coils  54 ,  56 ), at the end of the phase chance we should have IB=0 and IC=−I. At an instant t1, beginning a first transition phase I 1  from the first driving phase D 1  to a second driving phase D 2 , the control logic  74  drives phase A (coil  52 ) with a duty cycle equal to 100%, drives phase B (coil  54 ) with a PWM which is an inverted version of the one used in driving phase D 1  on phase A, and couples phase C (coil  56 ) to ground. Specifically, during the first transition phase I 1  the control logic  74  applies a constant high control signal to the gate of the first high-side transistor  60 ; a constant low signal to the gate of the first low-side transistor  62 ; the second and first PWM control signals to the second high- and low-side transistors  66 ,  68 , respectively; a constant low control signal to the third high-side transistor  70  and a constant high control signal to the third low-side transistor  72 . 
     By applying the PWM control signals to the second high- and low-side transistors  66 ,  68 , the absolute value of the current IB through the second coil  54  will tend to decrease while the second high-side transistor  66  is turned ON by the second PWM control signal and will tend to increase when the second low-side transistor  68  is turned ON by the first PWM control signal. The time of total discharge of the second coil  54  will be therefore longer than it would be if the same coil  54  had been immediately put in tristate as in the traditional systems. It will be appreciated that the application of the first and second PWM control signals could be reversed during the first transition phase I 1 , although with a less effective reduction of the discharge rate of the second coil  54 . 
     The current IC through the third coil  56  will grow with two different time constants according to whether the second high-side transistor  66  or the second low-side transistor  68  are turned ON by its respective PWM control signal during the first transition phase I 1 . When the second high-side transistor  66  is turned ON, the voltage at the center tap  58  is higher than when the low-side transistor  68  is turned ON. As a result, the time constant of the current IC through the third coil  56  is higher when the second high-side transistor  66  is turned ON and lower when the second low-side transistor  68  is turned ON. Overall what happens is a slowing of the discharge of the second coil  54  which will be forced to adapt itself to the time constant of the third coil  56 . 
     The current IA through the first coil  52  will be in each instant equal to the sum of the two currents IB and IC, Because the first high-side transistor  60  is kept ON during the entire first position phase I 1 , the current IA through the first coil  52  will increase throughout the first transition phase. The current IA will be substantially constant in the first transition phase I 1  because the variations in the currents IB and IC will substantially offset each other. 
     To determine when the first transition phase I 1  is completed and therefore when should enter the second driving phase D 2 , the motor  50  employs the comparator  78  to measure the current Is through the sense resistor  64 . During the portion of the first transition phase I 1  in which the second high-side transistor  66  is ON, the current Is through the sense resistor  64  is equal to IC, while during the portion of the first transition phase I 1  in which the second low-side transistor  68  is ON, the current Is through the sense resistor  64  is equal to the sum of the currents IB and IC. For this reason, measuring the current Is in the sense resistor  64  when only high side transistor  66  is ON, we can decide with security that the transition phase is terminated when Me voltage Is * Rs (resistance of sense resistor) reaches the voltage reference Vref. In response to determining that the voltage across the sense resistor  64  reaches the voltage reference Vref, the comparator  78  sends a signal to the control logic  74  which causes the control logic to end the first transition phase I 1  and begin the second driving phase D 2 . 
     During the second driving phase D 2 , the first coil  52  is again driven in PWM, the second coil  54  is in tristate, and the third coil  56  is coupled to a ground through the sense resistor  64  and the third low-side transistor  72 . As a result, the current IA through the first coil  52  equals I, the current IB through the second coil  54  equals zero, and the current IC through the third coil  56  equals −I. 
     If we effectuate a phase change between the phases A and B (coils  52 ,  54 ), at the end of the phase change we should have IA=0 and IB=I. At an instant t2, beginning a second transition phase I 2  from the second driving phase D 2  to a third driving phase D 3 , the control logic  74  drives phase A (coil  52 ) in PWM, drives phase B (coil  54 ) with a duty cycle equal to 100%, and leaves phase C (coil  56 ) coupled to ground. Specifically, during the second transition phase I 2  the control logic  74  applies the first and second PWM control signals to the first high- and low-side transistors  60 ,  62 , respectively; a constant high control signal to the second high-side transistor  66 ; a constant low signal to the second low-side transistor  68 ; a constant low control signal to the third high-side transistor  70  and a constant high control signal to the third low-side transistor  72 . 
     By applying the PWM control signals to the first high- and low-side transistors  60 ,  62 , the current IA through the first coil  52  will tend to increase while the first high-side transistor  60  is turned ON by the first PWM control signal and will tend to decrease when the first low-side transistor  62  is turned ON by the second PWM control signal. The time of total discharge of the first coil  52  will be therefore longer than it would be if the same coil  52  had been immediately put in tristate as in the traditional systems. 
     The current IB through the second coil  54  will grow with two different time constants according to whether the first high-side transistor  60  or the first low-side transistor  62  is turned ON by their respective PWM control signals during the second transition phase I 2 . When the first high-side transistor  60  is turned ON, the voltage at the center tap  58  is higher than when the first low-side transistor  62  is turned ON. As a result, the time constant of the current IB through the second coil  54  is lower when the first high-side transistor  60  is turned ON and higher when the first low-side transistor  62  is turned ON. Overall what happens is a slowing of the discharge of the first coil  52  which will be forced to adapt itself to the time constant of the second coil  54 . 
     The end of the second transition period I 2  can be triggered by the comparator  74  and effected by the control logic  74  as discussed above with respect to the end of the first transition phase I 1 . During the portion of the second transition phase I 2  in which the first high side transistor  60  is ON, the current Is through the sense resistor  64  equals IC and when the first low-side transistor  62  is ON, the current Is equals IC−IA, which equals IB. In fact, when the first low side transistor  62  is ON, the current through the first coil  52  recirculates through the first low side transistor  62 . Therefore the current IA is a current in the direction indicated by Iaric in FIG. 3, and thus is a current that is subtracted from IC to obtain the sense resistor current Is. 
     In response to determining that the voltage across the sense resistor  64  reaches the voltage reference Vref during the portion of transition phase I 2  in which first high-side transistor  60  is ON, the comparator  78  sends a signal to the control logic  74  which causes the control logic to end the second transition phase I 2  and begin the third driving phase D 3 . The control logic  74  continues to alternately drive current through two coils at a time during the driving phases as shown in FIG.  4 . Moreover, during each transition phases between successive driving phases, the control logic  74  drives in PWM whichever coil will be kept in tristate during the next driving phase. In doing so, the control logic  74  ensures that the variations of the current in the two phases in commutation during a phase change happen in a way that maintains their sum substantially constant. This greatly reduces the torque ripple that occurs during phase commutations in prior art three-phase motors, and thereby also reduces the acoustic noise accompanying the torque ripple. 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.