Abstract:
Various systems and methods for temperature measurement are disclosed. For example, some embodiments of the present invention provide methods for temperature measurement that include exciting a provided transistor with at least four sequential input signals of different magnitudes. In response, the transistor exhibits a sequence of output signals corresponding to the four sequential input signals. The sequence of output signals is sensed using a different gain for each of the output signals included in the sequence of output signals, and the output signals included in the sequence of output signals are combined such that the combined output signals eliminates a resistance error. The combined output signals are then used to calculate a temperature of the transistor.

Description:
BACKGROUND OF THE INVENTION 
   The present invention is related to temperature measurement, and more particularly to temperature measurements using a transistor or diode as a sensor. 
   Temperature measurement using a transistor as a sensor is a common application in the semiconductor area. Such a temperature measurement is done by applying two different currents to the transistor each resulting in a respective base-emitter voltage. The difference between the two different base-emitter voltages is proportional to the absolute temperature of transistor  144 . The following equation defines the relationship between the difference between base-emitter voltage measurements and absolute temperature:
 
Δ V   be   =V   be2   −V   be1   =n*kT/q * 1 n( I   2   /I   1 ).
 
The ‘n’ term is known as the non-ideality factor or emission coefficient is assumed to be a constant (n=1.008) for diodes and transistors.
 
   An example of such a temperature measurement circuit  100  is shown in  FIG. 1   a.  Turning to  FIG. 1   a,  temperature measurement circuit  100  includes a transistor  120  that is used as a temperature sensor. The collector and the base of transistor  120  are electrically coupled to a variable current source  110 . Further, the base of transistor  120  is electrically coupled to one input of an analog to digital converter  130 , and the emitter of transistor  120  is electrically coupled to another input of analog to digital converter  130 . Analog to digital converter  130  is operable to receive the voltages at the base and emitter of transistor  120 , and to provide a ΔV be  output  135  representing the difference between two different base to emitter voltages. ΔV be  output  135  is provided to a temperature calculation circuit  140  that provides an uncorrected temperature output  145 . 
   In some cases, an input filter  134  including a series resistor  131 , a series resistor  132 , a and a capacitor  133  is used. Input filter  134  is operable to filter noise from the voltages received from the base and emitter of transistor  120 . While input filter  134  operates to increase the accuracy ΔV be  output  135  and thereby increase the accuracy of uncorrected temperature  145 , the series resistance introduced by input filter  134  results in an error in uncorrected temperature  145 . In particular, the resistance introduced by series resistor  131  and series resistor  132  (and in some cases non-idealities of transistor  120 ) causes a voltage drop that is a function of the magnitude of an applied current. This voltage drop is described by the following equation:
 
Δ V   be   =V   be2   −V   be1 =( I   e2   −I   e1 )* R   s   +n*kT/q *ln( I   c2   /I   c1 ).
 
I e1  is the current passing through the emitter upon application of a first current, and I c1  is the current passing through the collector upon application of the same current. I e2  and I c2  are similarly emitter and collector currents corresponding to the application of a second current. R s  is the series resistance. The voltage drop described by the aforementioned equation will create a temperature measurement error if not taken into account by the circuit.
 
   To correct for the aforementioned temperature error, some circuits have included a backend offset circuit designed to add or subtract a calculated constant from uncorrected temperature  145  and thereby achieve a corrected temperature.  FIG. 1   b  shows an example of one such temperature calculation circuit  101 . As shown, temperature calculation circuit  101  is substantially similar to temperature calculation circuit  100 , except for the addition of a temperature offset adder circuit  150 . Temperature offset adder circuit  150  receives uncorrected temperature  145  and a programmed temperature offset input  147 . The two inputs are added together to create a corrected temperature output  155 . While such an offset approach can effectively correct calculation errors at a given point on an operational curve, the inaccuracy of the calculated temperature still exists as operation moves farther from the aforementioned offset corrected point on the operational curve. 
   Thus, for at least the aforementioned reasons, there exists a need in the art for advanced systems and devices for temperature measurement. 
   BRIEF SUMMARY OF THE INVENTION 
   The present invention is related to temperature measurement, and more particularly to temperature measurements using a transistor or diode as a sensor. 
   Various systems and methods for temperature measurement are described herein. For example, some embodiments of the present invention provide methods for temperature measurement that include exciting a provided transistor with at least four sequential input signals of different magnitudes. In response, the transistor exhibits a sequence of output signals corresponding to the four sequential input signals. The sequence of output signals is sensed using a different gain for each of the output signals included in the sequence of output signals, and the output signals included in the sequence of output signals are combined such that the combined output signals eliminates a resistance error. The combined output signals may then be used to calculate a temperature of the transistor. In some cases of the aforementioned embodiments, the transistor is a diode connected bipolar transistor, and the sequence of output signals are base-emitter voltages of the diode connected bipolar transistor. In such cases, the bipolar transistor may be either an NPN device or a PNP device. 
   Other embodiments of the present invention provide temperature measurement systems. Such temperature measurement systems include a transistor, a variable current source and an analog to digital converter. The variable current source is electrically coupled to the transistor. It should be noted that as used herein, the phrase “electrically coupled” implies either direct or indirect coupling. Direct coupling would be accomplished by, for example, a wire extending directly between two coupled devices. Indirect coupling may be accomplished by, for example, coupling via other components such as, for example, capacitors, resistors, transistors, or the like. The variable current source is operable to provide at least a first current, a second current, a third current and a fourth current. The first current produces a first base-emitter voltage on the transistor, the second current produces a second base-emitter voltage on the transistor, the third current produces a third base-emitter voltage on the transistor, and the fourth current produces a fourth base-emitter voltage on the transistor. The analog to digital converter is operable sample and integrate the first base-emitter voltage while applying a first gain, wherein the analog to digital converter is operable sample and integrate the second base-emitter voltage while applying a second gain, wherein the analog to digital converter is operable sample and integrate the third base-emitter voltage while applying a third gain, wherein the analog to digital converter is operable sample and integrate the fourth base-emitter voltage while applying a fourth gain, and wherein the analog to digital converter is operable to provide an integrated output combining the first base-emitter voltage, the second base emitter voltage, the third base emitter voltage and the fourth base emitter voltage. 
   In some embodiments of the aforementioned embodiments of the present invention, a magnitude of the first current, a magnitude of the second current, a magnitude of the third current, a magnitude of the fourth current, a sign and magnitude of the first gain, a sign an magnitude of the second gain, a sign and magnitude of the third gain, and a sign and magnitude of the fourth gain are selected such that a resistance error is eliminated from the integrated output. In various instances of the aforementioned embodiments, the analog to digital converter includes a differential operational amplifier, a differential comparator, and a result counter. The base of the transistor is electrically coupled to a first input of the differential operational amplifier via a first input circuit and to a second input of the differential operational amplifier via a second input circuit. Further, the emitter of the transistor is electrically coupled to the first input of the differential operational amplifier via a third input circuit and to the second input of the differential operational amplifier via a fourth input circuit. In such cases, the first input circuit and the third input circuit share a first gain circuit, and the first gain circuit includes a first selectable capacitance and a second selectable capacitance. The second input circuit and the fourth input circuit share a second gain circuit, and the second gain circuit includes a third selectable capacitance and a fourth selectable capacitance. Configuring the analog to digital converter to select the first gain and configuring includes selecting the first selectable capacitance of the first gain circuit and selecting the third selectable capacitance of the second gain circuit. Configuring the analog to digital converter to select the second gain includes selecting the second selectable capacitance of the first gain circuit and selecting the fourth selectable capacitance of the second gain circuit. 
   Yet other embodiments of the present invention provide methods for resistance compensated temperature measurement. Such methods include providing a diode connected transistor and applying a first current, a second current, a third current and a fourth current to the diode connected transistor. In response to each of the aforementioned excitation currents, a corresponding base-emitter voltage is exhibited on the diode connected transistor. The four corresponding base-emitter voltages are combined such that a resistance error is eliminated. 
   This summary provides only a general outline of some embodiments according to the present invention. Many other objects, features, advantages and other embodiments of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals are used throughout several drawings to refer to similar components. In some instances, a sub-label consisting of a lower case letter is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components. 
       FIG. 1   a  depicts a simplified temperature measurement system without series resistance compensation; 
       FIG. 1   b  shows the simplified temperature measurement system of  FIG. 1   a  augmented with a backend error offset circuit; 
       FIG. 2  is a temperature measurement system including a multiple gain input circuit able to perform series resistance compensation in accordance with some embodiments of the present invention; 
       FIG. 3  shows a timing diagram depicting performance of series resistance compensation in a temperature measurement circuit in accordance with one or more embodiments of the present invention; and 
       FIG. 4  is a flow diagram showing a method in accordance with various embodiments of the present invention for performing series resistance compensation in a temperature measurement scenario. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention is related to temperature measurement, and more particularly to temperature measurements using a transistor or diode as a sensor. 
   Various embodiments of the present invention provide temperature measurement methods and systems. In some cases, such temperature measurement systems and methods provide for series resistance compensation through use of four base-emitter voltages and corresponding gain factors. Using such approaches provides an efficient approach to compensating for series resistance that in many cases does not require additional circuitry when compared with a standard two base-emitter voltage measurement approach. Further, using such an approach may utilize only a multiplication and subtraction function to yield a resistance corrected delta base-emitter output value that corresponds to circuit temperature. 
   Turning to  FIG. 2 , a temperature measurement system  200  in accordance with one or more embodiments of the present invention is shown. Temperature measurement system  200  includes a static n-factor value  210 , a temperature calculation circuit  295 , and a first order integrating analog to digital converter  205 . In addition, temperature measurement system  200  includes a transistor  270  that is diode connected and used as a temperature sensor. It should be noted that while the figure shows an NPN transistor, that other circuits in accordance with one or more embodiments of the present invention may utilize a PNP transistor. 
   The collector and the base of transistor  270  are electrically coupled to a variable current source  260 . Further, the base and emitter of transistor  270  are electrically coupled to analog to digital converter  205  via an input filter  264 . Input filter  264  includes a series resistor  261 , a series resistor  262  and a capacitor  263 . Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of input filters that may be used to couple transistor  270  to analog to digital converter  205 . In particular, the base of transistor  270  is electrically coupled to an input of analog to digital converter  205  via a switch  235  (i.e., a positive input  243  of an operational amplifier  240  via switch  235  and an input circuit  299 ) and to another input of analog to digital converter  205  via a switch  236  (i.e., a negative input  242  of operational amplifier  240  via switch  236  and an input circuit  298 ). The emitter of transistor  270  is electrically coupled to one input of analog to digital converter  205  via a switch  237  (i.e., positive input  243  of operational amplifier  240  via switch  237  and input circuit  299 ) and to the other input of analog to digital converter  205  via a switch  238  (i.e., negative input  242  of operational amplifier  240  via switch  238  and input circuit  298 ). It should be noted that while the disclosed embodiments are described as canceling out resistance added in an input filter, that other sources of resistance in the circuit are also canceled out in the same process. Such other sources of resistance may include, but are not limited to, bus resistance, pin resistance, resistances due to transistor non-idealities, and the like. 
   Analog to digital converter  205  includes a loadable counter  271  that is synchronized to a sample clock  292 ; a result counter  260  that is also synchronized to sample clock  292 ; operational amplifier  240 ; a comparator  250 ; a number of switches that are also synchronized to sample clock  292 ; a number of sample and feedback capacitors; a voltage reference  249  and an inverted version of the aforementioned voltage reference  248 ; and a result register  280 . It should be noted that the inverted version of the voltage reference may be generated in any number of ways including, but limited to, applying a negative reference voltage, using a positive reference voltage and a defined sampling sequence, or the like. In particular, the inverted version of voltage reference  248  is electrically coupled to negative input  242  of operational amplifier  240  via a switch  225  and a sample capacitor  229 , and to positive input  243  of operational amplifier  240  via a switch  226  and a sample capacitor  221 . Voltage reference  249  is electrically coupled to negative input  242  of operational amplifier  240  via a switch  227  and sample capacitor  229 , and to positive input  243  of operational amplifier  240  via a switch  228  and sample capacitor  221 . 
   Input circuit  299  includes a sample capacitor  231  and a sample capacitor  232 . Sample capacitor  231  is selectively coupled via a switch  251 . Input circuit  299  is electrically coupled to positive input  243  of operational amplifier  240 . Input circuit  298  includes a sample capacitor  234  and a sample capacitor  235 . Sample capacitor  235  is selectively coupled via a switch  252 . Input circuit  298  is electrically coupled to negative input  242  of operational amplifier  240 . A switch  244   a  electrically couples a negative output of operational amplifier  240  to positive input  243 , and a switch  245   a  and a feedback capacitor  246   a  electrically couple the negative output of operational amplifier  240  to positive input  243 . A switch  244   b  electrically couples a positive output of operational amplifier  240  to negative input  243 , and a switch  245   b  and a feedback capacitor  246   b  electrically couple the positive output of operational amplifier  240  to negative input  242 . 
   The gain of operational amplifier  250  is proportional to the ratio of the input capacitance to the feedback capacitance. Thus, where switch  251  of input circuit  299  and switch  252  of input circuit  298  are open, one gain (i.e., G 1 ) is exhibited by operational amplifier  240 . Where switch  251  of input circuit  299  and switch  252  of input circuit  298  are closed, another gain (i.e., G 2 ) is exhibited by operational amplifier  240 . Thus analog to digital converter  205  may be operated with two distinct gains depending upon the position of switch  251  and switch  252 . In one embodiment of the present invention, capacitors  221 ,  229 ,  231 ,  232 ,  234  and  235  are all the same size. 
   The differential output of operational amplifier  240  is also electrically coupled to the differential input of comparator  250 . The output of comparator  250  is provided to result counter  260 , and as a feedback to control switches  225 ,  226 ,  227 ,  228 . Result counter  260  counts up synchronously each time the output of comparator  250  is a logic ‘1’ (i.e., each time the positive output of operational output is greater than the negative output). The number of samples that are counted is equivalent to the value loaded from static n-factor value  210 . Each time a sample is completed, loadable counter  271  is decremented. Once the output value of loadable counter  271  is a logic ‘0’, the output value of result counter  260  is stored to result register  280  and result counter  260  is reset. The output (i.e., Delta V be    265 ) of result register  280  is provided to a temperature calculation circuit  295 . The value of Delta V be    265  represents the difference between four or more different base-emitter voltages of transistor  270  compensated for series resistance (e.g., resistor  261  and resistor  262 ). The number of samples taken before a result is produced corresponds to static n-factor value  210 . In some embodiments of the present invention, static n-factor value  210  is replaced with a programmable register. In such cases, the n-factor value is programmable (i.e., the number of samples taken before producing a result is programmable in such a way that it effectively results in use of a different n-factor value). 
   In operation, variable current source  260  is set to apply four different currents to transistor  270 . Further, switches  235 ,  236 ,  237 ,  238 ,  251  and  252  are configured to apply a different gain when each of the four currents are applied to transistor  270 . Upon application of each of the currents, the base-emitter voltage (V be ) of transistor  270  is detected. In one particular embodiment of the present invention, a first current (I 1 ) is applied with a negative first gain (−G 1 ). Subsequently, a second current (I 2 ) is applied with a positive second gain (G 2 ). Subsequently, a third current (I 3 ) is applied with a negative second gain (−G 2 ). Finally, a fourth (I 4 ) is applied with a positive first gain (G 1 ). To apply I 1  with a gain −G 1 , variable current source  260  provides I 1  to transistor  270 , switch  236  and switch  237  are closed, switches  244  are closed, switch  235  and switch  238  are open, switches  245  are open, and switch  251  and switch  252  are open. To apply I 2  with a gain G 2 , variable current source  260  provides I 2  to transistor  270 , switch  236  and switch  237  are opened, switches  244  are closed, switch  235  and switch  238  are closed, switches  245  are open, and switch  251  and switch  252  are closed. To apply I 3  with a gain −G 2 , variable current source  260  provides I 3  to transistor  270 , switch  236  and switch  237  are closed, switches  244  are closed, switch  235  and switch  238  are open, switches  245  are open, and switch  251  and switch  252  are closed. To apply I 4  with a gain G 1 , variable current source  260  provides I 4  to transistor  270 , switch  236  and switch  237  are opened, switches  244  are closed, switch  235  and switch  238  are closed, switches  245  are open, and switch  251  and switch  252  are open. 
   Application of the aforementioned currents results in a corresponding charge being deposited on sample capacitors  232  and  234  where a gain of G 1  is selected, or a corresponding charge on sample capacitors  231 ,  232 ,  233  and  234  where a gain G 2  is selected. After the aforementioned sample phase is completed, the sampled charge is transferred to feedback capacitors  246  during an integration phase. Transferring the charge to feedback capacitors  246  involves opening switches  244  and closing switches  245 , and reversing particular ones of the input switches. In particular, where the charge corresponding to the aforementioned I 1  at a gain of −G 1  was previously sampled and is to be transferred to feedback capacitors  246 , switch  236  and switch  237  are opened, switches  244  are opened, switch  235  and switch  238  are closed, switches  245  are closed, and switch  251  and switch  252  are open. Where the charge corresponding to the aforementioned I 2  at a gain of G 2  was previously sampled and is to be transferred to feedback capacitors  246 , switch  236  and switch  237  are closed, switches  244  are opened, switch  235  and switch  238  are opened, switches  245  are closed, and switch  251  and switch  252  are closed. Where the charge corresponding to the aforementioned I 3  at a gain of −G 2  was previously sampled and is to be transferred to feedback capacitors  246 , switch  236  and switch  237  are opened, switches  244  are opened, switch  235  and switch  238  are closed, switches  245  are closed, and switch  251  and switch  252  are closed. Where the charge corresponding to the aforementioned I 4  at a gain of G 1  was previously sampled and is to be transferred to feedback capacitors  246 , switch  236  and switch  237  are closed, switches  244  are opened, switch  235  and switch  238  are opened, switches  245  are closed, and switch  251  and switch  252  are opened. The aforementioned sample phase and integration phase may be accomplished on succeeding edges (using both positive and negative edges) of a clock, on succeeding negative edges of the clock, or on succeeding positive edges of the clock. 
   Transferring the charge from sample capacitors  231 ,  232 ,  233  and  244  to feedback capacitors  246  results in an output from operational amplifier  240  at the input of comparator  250 . The output of operational amplifier  240  is processed by comparator  250  to produce either a logic ‘1’ or a logic ‘0’ depending upon the positive output of operational amplifier  240  relative to the negative output of operational amplifier  240 . Where the result is a logic ‘0’, result counter  260  is not incremented. In the next pass, the voltage at the base of transistor  270  is again sampled and integrated for the four currents and gains, and the same comparison process is repeated. 
   Alternatively, on any pass where the result of the comparison is a logic ‘1’, result counter  260  is incremented. Further, where the result is a logic ‘1’, the negative version of the voltage reference  248  is sampled along with the voltage at the base of transistor  270  on the next pass. This is done by closing switch  227 , switch  226  and switches  244 . This causes charge to build up on reference sample capacitor  221  and sample capacitor  229  representing the negative reference voltage, and charge to build up on the selected set of sample capacitors  231 ,  232 ,  234  representing the voltage at the base of transistor  270 . The charge from the aforementioned sample capacitors is then transferred to feedback capacitors during an integration phase where switch  225  and switch  227  are closed. By continually re-sampling the voltage at the base of transistor  270  and sampling the negative voltage reference any time a logic ‘1’ is noted, the following residue will remain for a counter value of X and a number of iterations N:
 
Residue= NV   in   −XV   ref ,
 
where V in  is the difference between two or more base-emitter voltages. The digital value representing the voltage at the base of transistor  270  is that maintained on result counter  260  at the end of the process. The process is continued for the number of samples loaded into loadable counter  271  (i.e., static n-factor value  210  or another programmed value). An increase in the number of samples reduces the residue and increases the resolution of Delta V be    265 .
 
   It should be noted that analog to digital converter  205  may be implemented as another type of analog to digital converter capable of sampling base-emitter voltages derived from application of four or more currents and exhibiting two or more gains. Based on the disclosure provided herein, one of ordinary skill in the art will recognize other types of analog to digital converters that may be used in relation to various embodiments of the present invention. 
   Further, it should be noted that in some embodiments of the present invention some form of processing circuit may be implemented between transistor  270  and analog to digital converter  205 . In such cases circuit operation is substantially as described above with the exception that transistor is electrically coupled to analog to digital converter  205  via the processing circuit and filter  264 . In any event, transistor  270  is electrically coupled to analog to digital converter  205 . In particular instances, the processing circuit performs the delta-V b e computation and analog to digital converter  205  converts the output of the intervening processing circuit. 
   Turning to  FIG. 3 , a timing diagram  300  depicts performance of series resistance compensation using temperature measurement system  200  in accordance with one or more embodiments of the present invention. As shown, during an operational period  310 , temperature measurement system  200  is initialized during an initialization period  320 . After initialization, a number of samples  360  are taken during a sampling period  340 . Each sample may include excitation of the sampled transistor using four or more excitation currents (I 1 , I 2 , I 3 , I 4 ) with at least four different gains (G 1 , −G 1 , G 2 , −G 2 ). In one particular embodiment of the present invention, I 1  is one hundred microamperes, I 2  is fifty microamperes, I 3  is five microamperes, I 4  is ten microamperes, G 1  is a unity gain, and G 2  is a gain of two. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of other currents and gains that may be used in accordance with one or more embodiments of the present invention to provide resistance and/or transistor non-ideality compensation. 
   As shown, during each sampling period represented by samples  361  and  362 , transistor  270  is excited using four excitation currents and four different gains: (1) I 1  and −G 1 , (2) I 2  and G 2 , (3) I 3  and −G 2 , and (4) I 4  and G 1 . As shown, this process of sampling and integrating base-emitter voltages corresponding to the aforementioned currents at the particular gains is completed a number of times, n, until the desired resolution of Delta V be    265  is achieved. At the end of sampling period  340  (e.g., once the output of loadable counter  271  is zero), the output of the analog to digital converter (e.g., Delta V be    265 ) represents a delta V be  created using four excitation currents and corresponding gains. In this case, Delta V be    265  is represented by the following equation:
 
Delta  V   be   =G   2 *( V   be2   −V   be3 )− G   1 *( V   be4   −V   be1 )
 
In the preceding equation, V be1  is the base-emitter voltage on transistor  270  upon application of I 1 . Similarly, V be2  is the base-emitter voltage on transistor  270  upon application of I 2 , V be3  is the base-emitter voltage on transistor  270  upon application of I 3 , and V be4  is the base-emitter voltage on transistor  270  upon application of I 4 . By incorporating four currents at different gains into the generation of Delta V be    265  errors due to series resistance and/or transistor non-idealities are reduced or eliminated.
 
   In particular, to compensate for errors introduced by series resistance, two independent ΔV be  values may be generated and used. Where the two independent ΔV be  values are created with the correct magnitude and gain, a simple subtraction between the ΔV be  values cancels out any effect of the series resistance. The following equations represent the method:
 
 G   2   *ΔV   be2-3   =G   2 *( V   be2   −V   be3 )= G   2 *[( I   e2   −I   e3 )* R   S   +n*kT/q *ln( I   c2   /I   c3 )]; and
 
 G   1   *ΔV   be4-1   =G   1 *( V   be4   −V   be1 )= G   1 *[( I   e4   −I   e1 )* R   s   +n*kT/q *ln( I   c4   /I   c1 )].
 
In the preceding equations, V be1  is the base-emitter voltage on transistor  270  upon application of I 1 . Similarly, V be2  is the base-emitter voltage on transistor  270  upon application of I 2 , V be3  is the base-emitter voltage on transistor  270  upon application of I 3 , and V be4  is the base-emitter voltage on transistor  270  upon application of I 4 . Again, the ‘n’ term is known as the non-ideality factor or emission coefficient is assumed to be a constant (n=1.008) for diodes and transistors. I e1  is the current passing through the emitter upon application of a first current, and I c1  is the current passing through the collector upon application of the same current. I e2 , I c2 , I e3 , I c3 , I e4 , I c4 , are similarly emitter and collector currents corresponding to the application of the respective second excitation current, third excitation current, and fourth excitation current. R s  is the series resistance.
 
   Each of the preceding equations includes an error component that is a function of the series resistance R s . In particular, the error component of G 2 *ΔV be2-3  is G 2 *(I e2 −I e3 )*R s , and the error component of G 1 *ΔV be4-1  is G 1 *(I e4 −I e1 )*R s . Where the gains (G 1  and G 2 ) and the currents (I 1 , I 2 , I 3 , I 4 ) are appropriately selected, subtraction of G 1 *ΔV be4-1  from G 2 *ΔV be2-3  causes the error components to drop out and leaves a differential base-emitter voltage value that is proportional to the absolute temperature of transistor  270 . The following equation represents Delta V be    265  and is equivalent to subtracting G 1 *ΔV be4-1  from G 2 *ΔV be2-3 :
 
Delta  V   be   =G   2 *[( I   e2   −I   e3 )* R   s   +n*kT/q *ln( I   c2   /I   c3 )]− G   1 *[( I   e4   −I   e1 )* R   s   +n*kT/q *ln( I   c4   /I   c1 )].
 
As an example, where I c2 =10*I c3 , I c4 =2*I c2 , I c1 =2*I c3 , I e2 =10*I e3 , I e4 =2I e2 , I e1 =2*I e3 , and G 2 =2*G 1 , then the following Delta V be    265  equation reduces to:
 
Delta  V   be =2 *G   1 *[(10 *I   e3   −I   e3 )* R   s   +n*kT/q *ln(10)]− G   1 *[(20 *I   e3 −2 I   e3 )* R   s   +n*kT/q *ln(10)];
 
thus,
 
Delta  V   be   =G   1   *[n*kT/q *ln(10)].
 
As can be seen from the preceding equations, Delta V be    265  does not include an error component due to the series resistance. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of ratios between the aforementioned currents and gains that can be used to eliminate the error component from Delta V be    265  in accordance with one or more embodiments of the present invention. Further, based on the disclosure provided herein, one of ordinary skill in the art will recognize a number of excitation currents and gains that may be used in relation to one or more embodiments of the present invention to perform serial resistance compensation.
 
     FIG. 4  is a flow diagram  400  showing a method in accordance with various embodiments of the present invention for performing series resistance compensation in a temperature measurement scenario. Following flow diagram  400 , a sample count is initialized (block  405 ), and a result count is initialized (block  410 ). In some embodiments of the present invention this initialization may include loading a predetermined number of samples to be taken into a loadable down counter, and resetting a result counter to zero. A gain of −G 1  and an excitation current I 1  is selected (block  415 ), and a temperature measurement circuit is excited using the aforementioned parameters (block  420 ). The temperature measurement circuit then samples and integrates the base-emitter voltage corresponding to the aforementioned excitation parameters (block  425 ). 
   Next, a gain of G 2  and an excitation current I 2  is selected (block  430 ), and the temperature measurement circuit is excited using the aforementioned parameters (block  435 ). The temperature measurement circuit then samples and integrates the base-emitter voltage corresponding to the aforementioned excitation parameters (block  440 ). Subsequently, a gain of −G 2  and an excitation current I 3  is selected (block  445 ), and the temperature measurement circuit is excited using the aforementioned parameters (block  450 ). The temperature measurement circuit then samples and integrates the base-emitter voltage corresponding to the aforementioned excitation parameters (block  455 ). Then, a gain of G 1  and an excitation current I 4  is selected (block  460 ), and the temperature measurement circuit is excited using the aforementioned parameters (block  465 ). The temperature measurement circuit then samples and integrates the base-emitter voltage corresponding to the aforementioned excitation parameters (block  470 ). 
   Once the preceding four sample and integration phases have been performed (block  415  to block  470 ), a comparison of the output of the integrator is performed (block  475 ). Where the result of the comparison is positive (block  475 ), the result count is incremented (block  480 ). It is next determined if the predetermined number of samples has been taken (block  485 ). Where all of the samples have not yet been taken (block  485 ), the processes of block  415  through block  480  are repeated. Alternatively, where the predetermined number of samples has been taken (block  485 ), the result is provided to a temperature calculation circuit (block  495 ). The provided result represents a Delta V be  incorporating series resistance compensation in accordance with various embodiments of the present invention. 
   In conclusion, the present invention provides novel systems, devices, methods for data temperature measurement. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. For example, other embodiments of the present invention, Delta V be    265  may be generated over two operational periods  310 . In the first operational period  310 , a gain of G 1  is selected and transistor  270  is repeatedly excited at a fourth current followed by a first current. This process is repeated for an appropriate number of samples to generate the aforementioned G 1 *ΔV be4-1 . During the second operational period  310 , a gain of G 2  is selected and transistor  270  is repeatedly excited at a second current followed by a third current. This process is again repeated for an appropriate number of samples to generate the aforementioned G 2 *ΔV be2-3 . In a post process, G 1 *ΔV be4-1  may be subtracted from G 2 *ΔV be2-3  to yield Delta V be    265 . As another example, the processes and systems are shown using a bipolar transistor, but other embodiments of the present invention may use other types of transistors or junction devices. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.