Abstract:
An apparatus comprising an Opto-coupler using LED and photo transistor as a basis for the isolation is provided. An Input of the opto-coupler based isolator is an LED. The opto-coupler uses PMOS MP 1  and MP 2  which act as reverse blocking diode, and thus providing −5V reverse bias breakdown voltage. Moreover, PMOS MP 1  and MP 2  act as switch for the forward input current and provides a conductive path between the ANODE and Supply node.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of Provisional Application No. 61/951,235, filed Mar. 11, 2014, the entirety of which is hereby incorporated by reference. 
     
    
     BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    This Patent Document relates generally to providing galvanic isolation between functional blocks of an electrical system, such as isolating a high voltage/power side from low voltage electronics. 
         [0004]    2. Related Art 
         [0005]    Galvanic isolation is used to prevent current flow (direct conduction path) from high voltage/power side to low voltage components. An example is an isolated driver for a power switching transistor (IGBT or power MOSFET). The low voltage gate driver electronics needs to be galvanically isolated from the power switching transistor. 
         [0006]      FIG. 1A  illustrates an optocoupler (opto-isolator) that includes and input side LED, and an output side photo transistor. The input LED is driven by input current from transmit electronics. 
         [0007]      FIG. 1B  illustrates an alternate capacitor based isolator. Capacitor based or transformer based isolators require a dedicated supply. The isolation capacitors allow AC flow, but block direct current, coupling AC signals between circuits at different DC voltages. 
         [0008]    Systems originally designed to use opto based isolators are designed to drive an LED. Substituting capacitor based or transformer based isolators in such systems requires emulating LED input characteristics for compatibility. 
         [0009]    While this Background information references an example isolated power switching application, the Disclosure provided in this Patent Document is not limited to such applications. 
       BRIEF SUMMARY 
       [0010]    This Brief Summary is provided as a general introduction to the Disclosure provided by the Detailed Description and Drawings, summarizing some aspects and features of the Disclosure. It is not a complete overview of the Disclosure, and should not be interpreted as identifying key elements or features of the invention, or otherwise characterizing or delimiting the scope of the invention disclosed in this Patent Document. 
         [0011]    This disclosure describes apparatus and methods for emulation of LED input characteristics in a BICMOS process, such as for constructing galvanic isolation interfaces. 
         [0012]    According to aspects of the Disclosure, LED input emulation can be used in a system suitable to provide galvanic isolation between a signal source block configured to drive source signals through an LED optocoupler characterized by a forward bias voltage VF and a reverse breakdown voltage VR, and an isolation circuit configured to receive the source signals through the LED input emulator circuit, and communicate the source signals through a galvanic isolation interface that is not based on optocoupling. 
         [0013]    An LED input emulator according to aspects of the Disclosure includes emulator anode and emulator cathode ports coupled to the signal source block, and an emulator output node. The LED input emulator can be configured to emulate LED forward bias voltage VF at the emulator output node, and LED reverse breakdown voltage VR across the emulator anode/cathode ports. The LED input emulator includes VR breakdown circuitry and VF control circuitry. The VR breakdown circuitry is coupled between the emulator anode port and both the emulator output node and the emulator cathode port, and configured to emulate the reverse breakdown voltage VR The VF control circuitry is coupled to the emulator output node, and configured to control the forward bias voltage at the emulator output node. 
         [0014]    The VR breakdown circuitry can include MP 1  and MP 2  PMOS transistors drain-coupled to the emulator anode port, and gate-coupled to the emulator cathode port, with MP 1  source-coupled to the emulator output node, and with MP 2  source-coupled to the emulator cathode port. The VF control circuitry can include: (a) variable resistance circuitry (such as an MP 3  PMOS transistor) coupled between the emulator anode/cathode ports, and configured to provide a variable resistance based on a VF control signal; and (b) current control circuitry coupled to the emulator output node, and configured to generate the VF control signal to control current through the variable resistance circuit based on a voltage at the emulator output node, such that the voltage at the emulator output node is maintained at the forward bias voltage VF. 
         [0015]    According to other aspects of the Disclosure, the current control circuitry can include an amplifier, and reference circuitry coupled to the amplifier non-inverting input that is configured to provide a reference voltage corresponding to the forward bias voltage VF, and feedback circuitry coupled between the emulator output node and the amplifier inverting input, that is configured to provide a feedback voltage corresponding to the voltage at the emulator output node. The amplifier circuit is operable to generate the VF control signal based on the reference voltage and the feedback voltage. According to other aspects of the Disclosure, the current control circuitry can be implemented with bandgap circuitry, including Q 1  and Q 2  NPN transistors; and a resistor network coupled to the Q 1 /Q 2  transistors, the Q 1 /Q 2  transistors and the resistor network configured to generate VBE and ΔVBE voltages, such that (a) the amplifier generates the VF control voltage based on VBE and ΔVBE, thereby controlling the current through the variable resistance, and (b) the forward bias voltage VF corresponds to a bandgap reference voltage that is a function of VBE and ΔVBE. 
         [0016]    Other aspects and features of the invention claimed in this Patent Document will be apparent to those skilled in the art from the following Disclosure. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIGS. 1A AND 1B  illustrate LED and capacitive based galvanic isolation configurations. 
           [0018]      FIG. 2  illustrates an example functional embodiment of an LED input emulator ( 10 ) suitable for use in a system providing galvanic isolation between a signal source ( 40 ) and an isolation block  50  that is not based on optocoupling, including VR breakdown circuitry (MP 1  and MP 2 ), and VF control circuitry including a variable resistance (R 1 ). 
           [0019]      FIG. 3  illustrates an example embodiment of an LED input emulator  10 , including VF control circuitry  30  implemented with a variable resistance (MP 3 ) controlled by an amplifier (A 1 ) and bandgap reference/feedback circuitry ( 35 ). 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    This Description and the Drawings constitute a Disclosure of example embodiments and applications that illustrate various features and advantages of an LED input emulator that emulates LED input characteristics. 
         [0021]    An objective of the LED input emulation according to aspects of the Disclosure is to emulate an LED input characteristics in a BiCMOS process. Example LED input characteristics include: (a) Forward bias voltage VF should be less than 1.95V and more than 1.2V for a given range of input current; (b) The reverse bias voltage VR should be at least −5V; and (c) They are driven by input current. For the example embodiments, a forward bias voltage of VF≈1.8V is an example design choice. 
         [0022]    In brief overview, an LED input emulator configured to interface a signal source designed for use with an LED optocoupler, to capacitive or other galvanic isolation circuitry, emulating LED forward bias and reverse breakdown voltages. VR breakdown circuitry includes MP 1  and MP 2  PMOS transistors coupled to an emulator anode port, and configured to emulate LED reverse breakdown voltage. VF control circuitry includes a variable resistance (MP 3 ) coupled between anode and cathode ports, and a current control circuit coupled to an output node, and configured to control current through the variable resistance to maintain a desired forward bias voltage at the output node. In an example embodiment, the VF control circuitry is implemented with an amplifier and a bandgap voltage reference circuit coupled to the output node, generating both reference and feedback voltages input to the amplifier to control the variable resistance. An example application is an isolated (capacitive) gate driver for a high voltage MOSFET or IGBT. 
         [0023]      FIG. 2  illustrates an example functional embodiment of an LED input emulator  10  suitable for use in a system providing galvanic isolation between functional blocks. As illustrated, the example system includes signal source functional block  40 , interfaced through LED input emulator  10 , to an isolation block  50 . 
         [0024]    Signal source block  40  is configured to drive source signals through an LED optocoupler that is characterized by a forward bias voltage VF and a reverse breakdown voltage VR. Isolation block  50  is configured to receive the source signals through LED input emulator circuit  10 , and communicate the source signals through a galvanic isolation interface that is not based on optocoupling. For example, isolation block  50  can be configured to provide capacitor-based isolation. 
         [0025]    LED input emulator  10  includes ANODE and CATHODE ports coupled to signal source  40 , and an emulator output node Ni coupled to isolation block  50 . LED input emulator  10  is configured to emulate LED input characteristics VR and VF in a BICMOS process. 
         [0026]    LED input emulator  10  is configured to emulate LED reverse breakdown voltage VR across the emulator anode/cathode ports, and an LED forward bias voltage VF at the emulator output node N 1 . It includes VR breakdown circuitry  20  configured to provide LED reverse breakdown voltage VR, and VF control circuitry  30  configured to control LED forward bias voltage at N 1 . 
         [0027]    VR breakdown circuitry  20  includes first and second PMOS transistors MP 1  and MP 2 , drain-coupled to the emulator ANODE port, and gate-coupled to the emulator CATHODE port. MP 1  is source-coupled to the emulator output node N 1 , and MP 2  is source-coupled to the emulator CATHODE port. VR breakdown circuitry  20  uses PMOS MP 1  and MP 2  which acts as reverse blocking diode and thus providing −5V reverse bias breakdown voltage. 
         [0028]    VF control circuitry  30  controls the emulator output node N 1  in forward bias/operation mode, emulating LED forward bias voltage. VF control circuitry  30  includes a variable resistance R 1 , and a current control circuit  31  that controls current through R 1 . Current control circuit  31 , such as an amplifier and voltage reference circuit, is coupled to the emulator output node N 1 , and configured to generate a VF control signal to maintain the voltage at the emulator output node N 1  at a design forward bias voltage VF within the LED forward bias voltage range (such as the example 1.8V). Variable resistance R 1  is coupled between the emulator anode/cathode ports, and configured to provide a variable resistance based on the VF control signal, thereby controlling current through R 1 . 
         [0029]    VF control circuitry  30  functions to maintain the voltage at the emulator output node N 1  at the forward bias voltage VF. That is, in forward bias/operation, VF control circuitry  30 , controls output node Ni coupled to isolation block  50 , acting as switch for the forward input current, providing a conductive path between the ANODE port coupled to receive the source signals, and an output node N 1  coupled to isolation block  50 . 
         [0030]      FIG. 3  illustrates an example embodiment of an LED input emulator  10 , including VF control circuitry  30  implemented with a bandgap voltage reference. For this embodiment, LED input emulator  10  not only emulates the LED input but also provides the supply to the isolation block  50 , required to drive isolation related circuits. 
         [0031]    VF control circuitry  30  includes a variable resistance implemented with an MP 3  PMOS transistor operated as a variable resistor. MP 3  is source-coupled to MP 2 , and drain-coupled to the emulator CATHODE port. MP 3  is gate-coupled to receive the VF control signal, which controls the resistance of MP 3 , and thereby current through MP 3 . 
         [0032]    VF control circuitry  30  includes current control circuitry ( FIG. 2 ,  31 ) implemented with an amplifier Al and reference/feedback circuit  35  implemented with bandgap reference circuitry. Amplifier Al includes inverting and non-inverting inputs coupled to reference/feedback circuitry  35 . 
         [0033]    Reference/feedback circuit  35  incudes reference circuitry and feedback circuitry. Reference circuitry is coupled to the amplifier non-inverting input, and configured to provide a reference voltage corresponding to the design forward bias voltage VF. Feedback circuitry is coupled between the emulator output node N 1  and the inverting input, and configured to provide a feedback voltage corresponding to the voltage at the emulator output node. 
         [0034]    Amplifier Al is operable to generate the VF control signal based on the reference voltage and the feedback voltage, thereby controlling current through the variable resistance MP 3 . 
         [0035]    For this example embodiment, reference/feedback circuitry  35  (reference circuitry and feedback circuitry) is implemented with bandgap reference circuitry. The bandgap reference/feedback circuitry  35  includes Q 1  and Q 2  NPN transistors, and a resistor network R 2 /R 3 /R 4  and R 5 /R 6 . 
         [0036]    The transistors Q 1 /Q 2  and the resistor network are configured to generate bandgap voltages VBE and ΔVBE: VBE is complementary-to-absolute-temperature (CTAT), and ΔVBE is proportional-to-absolute-temperature (PTAT). VBE is generated at the VBE node, and ΔVBE is generated across R 4 . 
         [0037]    The forward bias voltage VF at the emulator output node N 1  is controlled as a function of the bandgap voltages VBE and ΔVBE. R 5 /R 6  are configured to control VBE CTAT current through the bandgap reference circuitry, adjusting the forward bias voltage VF to a design value in the LED forward voltage range of between 1.2V and 1.95V, such as 1.8V. 
         [0038]    Amplifier A 1  generates the VF control voltage based on VBE and ΔVBE, thereby controlling the current through the variable resistor MP 3 . Current through the variable resistor MP 3  is controlled to adjust the forward bias voltage VF at the emulator output node N 1 , which corresponds to a bandgap reference voltage that is a function of VBE and ΔVBE. 
         [0039]    The Disclosure provided by this Description and the Figures sets forth example embodiments and applications illustrating aspects and features of the invention, and does not limit the scope of the invention, which is defined by the claims. Known circuits, functions and operations are not described in detail to avoid obscuring the principles and features of the invention. These example embodiments and applications can be used by ordinarily skilled artisans as a basis for modifications, substitutions and alternatives to construct other embodiments, including adaptations for other applications.