Abstract:
An integrated circuit device, in accordance with embodiments as claimed includes a central processing core; and a plurality of peripherals operably coupled to the RISC CPU core. In some embodiments, the plurality of peripherals include at least one configurable logic cell peripheral having more inputs than input-output connections on the integrated circuit device. In some embodiments, the inputs include one or more inputs from one or more integrated circuit subsystems.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 61/477,754 filed on Apr. 21, 2011, entitled “Configurable Logic Cells”, which is incorporated by reference herein in its entirety. This application is related to co-pending U.S. patent application Ser. No. 13/449,687, filed on Apr. 18, 2012, entitled “Selecting Four Signals From Sixteen Inputs”; U.S. patent application Ser. No. ______, filed on ______ entitled “Configurable Logic Cells”; and U.S. patent application Ser. No. ______, filed on ______ entitled “A Logic Device For Combining Various Interrupt Sources Into A Single Interrupt Source And Various Signal Sources To Control Drive Strength”, all filed concurrently herewith and incorporated by reference in their entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    This invention relates to configurable logic cells and, more particularly, to a RISC processor with combinatorial logic peripherals. 
         [0004]    2. Description of the Related Art 
         [0005]    Most logic devices are available in a package with a single pin for each logic input and output (not counting power and ground pins). For example, a 74L500 logic gate has four instances of a 2-input, 1-output device, requiring twelve pins, and is available in a fourteen pin package including power and ground. 
         [0006]    In a system employing a number of configurable logic cells, it is often required that software reads the outputs of all cells at about the same time. Since the cells are instantiated independently, the output register (bit) for each cell is in a different register, and requires the central processing unit (CPU) to perform a number of read operations to determine the state of each bit. Inherently, this means that the cells are never sampled at the same time, and could in fact be samples at widely spaced intervals or perhaps in different orders, and this can at times produce misleading results. 
         [0007]    Configurable logic cells of microcontrollers are versatile, but, having only a single logic function and/or state variable, can only be applied to a limited class of applications. FPGAs and PLDs provide configurable logic cells that are generally based on D flip-flop technology. While this is adequate for general purpose use and automated logic configuration, it does not always lead to a minimal circuit implementation solution. 
       SUMMARY OF THE INVENTION 
       [0008]    These and other drawbacks in the prior art are overcome in large part by a system and method according to embodiments of the present invention. 
         [0009]    An integrated circuit device, in accordance with embodiments as claimed includes a central processing core; and a plurality of peripherals operably coupled to the central processing core. In some embodiments, the plurality of peripherals include at least one configurable logic cell peripheral having more inputs than input-output connections on the integrated circuit device. In some embodiments, the inputs include one or more inputs from one or more integrated circuit subsystems. 
         [0010]    In some embodiments, the inputs include at least one input from at least one other configurable logic peripheral. In some embodiments, the integrated circuit device includes a single microprocessor register configured for reading outputs of a plurality of configurable logic cells. In some embodiments, at least two of configurable logic cells are cascaded. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference symbols in different drawings indicates similar or identical items. 
           [0012]      FIG. 1  illustrates an exemplary integrated circuit including a configurable logic cell. 
           [0013]      FIG. 2  illustrates an exemplary data and address lines in an integrated circuit including a configurable logic cell. 
           [0014]      FIG. 3  illustrates an exemplary module including a configurable logic cell. 
           [0015]      FIG. 4A  and  FIG. 4B  illustrate software control and configuration of a configurable logic cell. 
           [0016]      FIG. 5A  and  FIG. 5B  illustrate exemplary logic functions for a configurable logic cell that replaces two statically configured functions with a single, software-controlled function. 
           [0017]      FIG. 6A-FIG .  6 D illustrate logic function combinatorial options for an exemplary configurable logic cell. 
           [0018]      FIG. 7A-7D  illustrate logic function state options for an exemplary configurable logic cell. 
           [0019]      FIG. 8  illustrates an exemplary JK flip flop application and timing implemented with an exemplary configurable logic cell. 
           [0020]      FIG. 9  is a diagram of an exemplary integrated circuit pin configuration. 
           [0021]      FIG. 10  illustrates exemplary output register usage for a plurality of configurable logic cells. 
           [0022]      FIG. 11  illustrates exemplary cascading of configurable logic cells. 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    Turning now to the drawings and, with particular attention to  FIG. 1 , a diagram of a processor  100  according to an embodiment of the present invention is shown. The processor  100  includes a processor core (MCU)  102 , which may be embodied as a RISC core. The processor core  102  couples via a bus  106  to one or more on-chip peripheral devices, such as analog peripherals  108  and digital peripherals  110 . 
         [0024]    In addition, as will be explained in greater detail below, the processor  100  further includes one or more configurable logic cells (CLC)  104 , functioning as peripheral devices and coupled to the bus  106 . That is, the configurable logic cells  104  are addressable like other peripheral devices and provide logic functions for the system. These can include, for example, AND, OR, XOR functions, and D, JK, and SR storage. 
         [0025]    The processor  100  further includes one or more input and/or outputs  116 ,  118 ,  120 ,  122 ,  124 , and associated port drivers, input controls  114 , etc. 
         [0026]    In the embodiment illustrated, the configurable logic cell  104  receives inputs from external pin  124 , digital peripherals  110 , and a reset from the processor core  102 . These can include, for example, CWG source, DSM source, and DDS/Timer clock inputs. In general, inputs can come from I/O pins, register bits, other peripherals, and internal clocks. 
         [0027]    In addition, the configurable logic cell  104  can provide digital outputs to one or more of the analog peripherals  108 , the digital peripherals  110 , and the processor core  102 . Additional outputs (such as slew rate, pull-up tristate thresholds, etc.) can be provided to port drivers  112 , while others can be provided to external pins  118 . 
         [0028]    Thus, in general, the configurable logic cell  104  can receive inputs from any subsystem such as a digital peripheral, I/O port, or internal status bits, or reset signals, including for example, oscillator output, system clocks, etc., and provides outputs to I/O pins, peripherals, a processor core interrupt, I/O port control functions, status signals, system clock, and even to other configurable logic cells (not shown). 
         [0029]    As noted above, in some embodiments, the configurable logic cell  104  is addressed like other peripheral devices and may be configured at run-time. In some embodiments, the configurable logic cell  104  may be configured at run time using one or more special function registers (not shown). Thus, the configurable logic cell  104  is fully integrated into the processor address and data bus. Configuration can be applied statically or updated in real time based on the needs of the application. 
         [0030]    In some embodiments, configuration of the configurable logic cell  104  can come from software registers or non-volatile memory. In some embodiments, the memory may be read and data transferred to configuration registers. In others, the memory may be statically connected for configuration (as in generic logic arrays/programmable logic arrays (GAL/PAL)). Further, in some embodiments, after an initial configuration, software may update the configuration. 
         [0031]    As such, in some embodiments, system signals and I/O signals are routed to the configurable logic cell  104 , as shown in  FIG. 2 . The configurable logic cell  104  then performs the configured logic and provides an output. In particular, shown in  FIG. 2  is processor  100  including processor core  102 , a program flash memory  203 , and peripherals  202 . The program flash memory  203  couples via program address lines/bus  205  and program data lines/bus  207  to the processor core  102 . 
         [0032]    In the example illustrated, the peripherals include a timer  202   a , data memory  202   b , a comparator  202   c , and the configurable logic cell  104 . The peripherals couple to the processor core  102  by data address lines/bus  206  and data lines/bus  204 . The configurable logic cell  104  may receive further individual inputs from the peripherals  208  or from an input pin  124 . Thus, software and other peripherals can supply inputs to the configurable logic cell  104 . The configurable logic cell  104  performs a configured logic operation and provides an output  312 . 
         [0033]    As noted above, the configurable logic cell implements one or more logic functions and can do so independently of the status of the processor core, e.g., while the processor core is in a sleep or debug mode. 
         [0034]      FIG. 3  illustrates the configurable logic cell environment according to one embodiment more particularly. Configurable logic cell  104  receives four channel inputs  304  LxOUT 1 , LxOUT 2 , LxOUT 3 , and LxOUT 4  from a plurality of selectors  302 . Inputs to the selectors  302  can come from signals  208  and I/O  124 . In some embodiments, the selectors are multiplexers and/or configurable gates. For example, in some embodiments, the selectors  302  can reduce the number of inputs clc_in  208  from eight to four  304  to drive one of eight selectable single-output functions. Further details on particular implementations of the selectors  302  may be found in commonly-assigned patent application Ser. No. ______, titled “Selecting Four Signals from Sixteen Inputs,” filed Apr. 17, 2012, which is hereby incorporated by reference in its entirety as if fully set forth herein. 
         [0035]    In the example illustrated, the configurable logic cell  104  receives control inputs LCMODE&lt;2:0&gt;  314  and LCEN  316  from control registers (not shown). The output LxDATA of the configurable logic cell  104  is ANDed with the LCEN input  316 . The output of AND gate  308  is XORed with LCPOL a control signal from a control register (not shown) and then output as CLCxOUT, all of which are explained in greater detail below. 
         [0036]    As noted above, embodiments allow for real time configuration of the configurable logic cell. That is, configuration is provided through registers accessible from the microprocessor and can be updated based, for example, on external inputs, time of day, temperature of the system, coincidence with other events, or commands from a remotely controlling host. 
         [0037]      FIG. 4A  and  FIG. 4B  schematically illustrate such operation. In particular, shown is processor  100  including processor core  102  and configurable logic cell  104 . The processor  100  has an I/O input  406  to the processor core  102  and a pair of inputs  124   a ,  124   b  to the configurable logic core  104 . The configurable logic cell  104  outputs to pin  412 . 
         [0038]    In operation, the state of the I/O pin  406  can be used to set the configurable logic core function. In the example illustrated, when the logic state of the I/O input  406  is “0”, the processor core  102  writes to one or more registers (such as the L×Mode register  314  of  FIG. 3 ) to cause the configurable logic cell  104  to implement an AND function  402 , so that the outputs on pin  412  is the logical AND of inputs A  124   a  and B  124   b  (AB). In contrast, when the logic state of the I/O input  406  is “1”, the processor core  102  writes to one or more registers to cause the configurable logic cell  104  to implement an OR function  404 , so that the output on pin  412  is the logical OR of inputs A  124   a  and B  124   b  (A+B). As can be appreciated, once the functions are set, the configurable logic cell  104  implements the configured function regardless of the functioning of the processor core  102 . 
         [0039]    Advantageously, the configurable logic cell  104  of embodiments of the present invention allows for dynamic configuration and direct access to software, allowing software to reconfigure individual gates and inverters while the system is running That is, the configurable logic cell of embodiments of the invention allows real-time software access to internal configuration and signal paths, without requiring a microprocessor interface. 
         [0040]    For example, as shown in  FIG. 5A , a static configuration of a microprocessor interface for implementing the two functions ((A*B)+C)′ and ((A*B)&#39;+C)′ requires two versions  502 ,  504 , including AND gates  506 ,  510 , NOR gates  508 ,  514 , and inverter  512 . 
         [0041]    In contrast, an exemplary configurable logic cell  104  for implementing the functions is shown in  FIG. 5B . The configurable logic cell  104  includes AND gate  552 , XOR gate  554 , and NOR gate  556 . Inputs A and B are provided to AND gate  552 , while input C is provided to the NOR gate  556 . The output of the AND gate  552  is provided to the XOR gate  554 , while the XOR gate  554  provides its output to the input of NOR gate  556 . In addition, a direct software (SW) input  558  (e.g., from a control register) is provided to the input of the XOR gate  554 . In this way, both functions of circuits  502 ,  504  are implemented using a single circuit and yet allowing direct software control. 
         [0042]    Exemplary combinatorial options for a particular four-input configurable logic cell are shown in  FIG. 6A-6D . More particularly, in some embodiments, a LxMODE&lt;2:0&gt; configuration register  314  ( FIG. 3 ) defines the logic mode of the cell. When LxMODE=000, the configurable logic cell implements and AND-OR function. When LxMODE=001, the cell implements an OR-XOR function. When LxMODE=010, the cell implements an AND; when LxMODE=011, the cell is an RS latch. 
         [0043]    Correspondingly, the configurable logic cell  104  may incorporate a plurality of state logic functions. These are shown with reference to  FIG. 7A-7D . The state functions include both D ( FIG. 7A ) and JK flipflops ( FIG. 7B ) with asynchronous set (S) and Reset (R). Input channel  1  (LCOUT 1 ) provides a rising edge clock. If a falling edge is required, channel  1  (LCOUT 1 ) can be inverted in the channel logic (not shown). Input channel  2  (LCOUT 2 ), and sometimes channel  4  (LCOUT 4 ), provide data to the register or latch inputs. 
         [0044]    When LCMODE=100, the cell implements a one input D flipflop with S and R. When LCMODE=101, the cell implements a two input D flipflop with R. When LCMODE=110, the cell implements a JK flipflop with R. When LCMODE=111, the cell implements a one input transparent latch with S and R (The output Q follows D while LE is low and holds state while LE is high). 
         [0045]      FIG. 8  illustrates an example operation of a JK flip-flop in accordance with embodiments of the invention. In particular, shown is a clock gating example including a JK flip flop  800 , with input  806 , output  802 , and clock  804 . The output  802  is a gated FCLK/2. 
         [0046]    The JK flipflop can be configured according to  FIG. 7B , with the clock at LCOUT 1 , J input at LCOUT 2 , and K input (inverted) at LCOUT 4 . As can be seen, the output  802  always includes a whole number of cycles. It is noted that other logic and state functions can be implemented. Thus, the figures are exemplary only. 
         [0047]    As noted above, each configurable logic cell  104  has four inputs selectable from a constellation of eight available signals, and one output, although other numbers of signals and inputs are possible. In some embodiments, however, the integrated circuit package includes only four input-output pins. That is, the integrated circuit package includes one pin for output and three for input. This is shown by way of example in  FIG. 9 , integrated circuit  900  includes pins RA 0 , RA 1 , RA 2 , RA 3 , Vss and Vdd. RA 0 -RA 2  may be inputs, for example, and RA 3  may be the output. Other inputs to the configurable logic cell  104  come from other peripherals on the internal data bus. In some embodiments, in which the integrated circuit includes more than one peripheral logic cell, inputs can come from other peripheral logic cells, as will be discussed in greater detail below. 
         [0048]    More particularly, in implementations including more than one peripheral logic cell  104 , it is desirable to be able to read multiple cell outputs substantially simultaneously. Consequently, in accordance with embodiments of the present invention, a combined output register may be provided. This is shown in  FIG. 10 , which illustrates three configurable logic units  1002   a ,  1002   b ,  1002   c . It is noted that more or fewer than three may be provided. Thus, the figures are exemplary only. 
         [0049]    Each configurable logic unit  1002   a ,  1002   b ,  1002   c  includes a configurable logic cell  104   a ,  104   b ,  104   c , respectively. Each further includes an output CLCOUTA, CLCOUTB, CLCOUTC, respectively. In implementations in which only one configurable logic cell is employed, the output is provided to an associated output register  1004   a ,  1004   b ,  1004   c , respectively. 
         [0050]    However, when more than one configurable logic cell is in use, the outputs are provided to the common register  1006 , outside the configurable logic unit instances. By providing the combined output register  1004  outside the instances of each of the logic units, their combined outputs may be read substantially simultaneously. 
         [0051]    In addition, by providing multiple configurable logic cells having inputs other than external pins, the cells can be cascaded to create complex combinations. This is shown by way of example in  FIG. 11 . 
         [0052]    In particular, shown in  FIG. 11  is a system  1100  including a plurality of configurable logic units  1102   a ,  1102   b ,  1102   c ,  1102   d , each including a corresponding configurable logic cell  104   a ,  104   b ,  104   c ,  104   d , respectively. As shown, the configurable logic cell  104   a  provides its output to configurable logic cell  104   b  and  104   c , while configurable logic cell  104   b  provides outputs to an external pin  1106  as well as to inputs of configurable logic cell  104   c  and configurable logic cell  104   d . In addition, the configurable logic cell  104   d  provides its output to a output line, e.g., to another peripheral or to the processor core. 
         [0053]    As can be seen each of the configurable logic cells  104   a ,  104   b ,  104   c ,  104   d  has four inputs and can receive input signals from input pins  1104   a ,  1104   b ,  1104   c , from other configurable logic cells, or from other on-chip and peripheral devices. 
         [0054]    While specific implementations and hardware/software configurations for the mobile computing device have been illustrated, it should be noted that other implementations and hardware configurations are possible and that no specific implementation or hardware/software configuration is needed. Thus, not all of the components illustrated may be needed for the mobile computing device implementing the methods disclosed herein. 
         [0055]    As used herein, whether in the above description or the following claims, the terms “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” and the like are to be understood to be open-ended, that is, to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of,” respectively, shall be considered exclusionary transitional phrases, as set forth, with respect to claims, in the United States Patent Office Manual of Patent Examining Procedures. 
         [0056]    Any use of ordinal terms such as “first,” “second,” “third,” etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another, or the temporal order in which acts of a method are performed. Rather, unless specifically stated otherwise, such ordinal terms are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term). 
         [0057]    The above described embodiments are intended to illustrate the principles of the invention, but not to limit the scope of the invention. Various other embodiments and modifications to these preferred embodiments may be made by those skilled in the art without departing from the scope of the present invention.