Abstract:
In a semiconductor device including a substrate, a first semiconductor chip directly or indirectly on the substrate, and a second semiconductor chip located on the first semiconductor chip, the second semiconductor chip has a larger dimension than that of the first semiconductor chip.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a semiconductor device, and more particularly, to a stacked chip-size package (CSP) type semiconductor device.  
           [0003]    2. Description of the Related Art  
           [0004]    Recently, semiconductor packages have been developed to adopt stacked chip-size packages (CSPs) having substantially the same size as that of semiconductor chips.  
           [0005]    A prior art stacked chip-size package type semiconductor device (see: JP-A-2000-307057) is constructed by a plurality of semiconductor chips stacked on a substrate. In this case, an upper one of the semiconductor chips is smaller than an lower one of the semiconductor chips. This will be explained later in detail.  
           [0006]    In the above-described prior art stacked chip-size package type semiconductor device, however, since the largest semiconductor chip is the lowest semiconductor chip, all bonding wires connected between the semiconductor chips and the substrate are outside of the largest semiconductor chip, the substrate is much larger than the largest semiconductor chip, which would increase the stacked chip-size package in size.  
         SUMMARY OF THE INVENTION  
         [0007]    It is an object of the present invention to provide a stacked chip-size package type semiconductor device capable of being decreased in size.  
           [0008]    According to the present invention, in a semiconductor device including a substrate, a first semiconductor chip directly or indirectly on the substrate, and a second semiconductor chip located on the first semiconductor chip, the second semiconductor chip has a larger dimension than that of the first semiconductor chip.  
           [0009]    If the second semiconductor chip is largest, the largest semiconductor chip is not the lowest semiconductor chip. As a result, some of bonding wires are inside of the largest semiconductor chip, so that the size of the substrate can be brought close to that of the largest semiconductor chip. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    The present invention will be more clearly understood form the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:  
         [0011]    [0011]FIG. 1 is a cross-sectional view illustrating a prior art stacked chip-size package type semiconductor device;  
         [0012]    [0012]FIG. 2 is a cross-sectional view illustrating a first embodiment of the stacked chip-size package type semiconductor device according to the present invention;  
         [0013]    [0013]FIGS. 3A, 3B and  3 C are cross-sectional views for explaining a method for manufacturing the stacked chip-size package type semiconductor device of FIG. 2;  
         [0014]    [0014]FIG. 4 is a partly-cut perspective view of the thermoplastic adhesive layer of FIGS. 3B and 3C;  
         [0015]    [0015]FIGS. 5A and 5B are cross-sectional views for explaining the effect of the first embodiment of the present invention as compared with the prior art;  
         [0016]    [0016]FIG. 6 is a cross-sectional view illustrating a modification of the stacked chip-size package type semiconductor device of FIG. 2;  
         [0017]    [0017]FIG. 7 is a partly-cut, perspective view illustrating a modification of the thermoplastic adhesive layer of FIG. 4;  
         [0018]    [0018]FIG. 8 is a cross-sectional view illustrating a second embodiment of the stacked chip-size package type semiconductor device according to the present invention;  
         [0019]    [0019]FIGS. 9A and 9B are cross-sectional views for explaining a method for manufacturing the stacked chip-size package type semiconductor device of FIG. 8;  
         [0020]    [0020]FIG. 10 is a cross-sectional view illustrating a third embodiment of the stacked chip-size package type semiconductor device according to the present invention; and  
         [0021]    [0021]FIGS. 11A and 11B are cross-sectional views for explaining a method for manufacturing the stacked chip-size package type semiconductor device of FIG. 10. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0022]    Before the description of the preferred embodiments, a prior art stacked chip-size package type semiconductor device will be explained with reference to FIG. 1 (see: JP-A-2000-307057).  
         [0023]    In FIG. 1, reference numeral  101  designates a substrate made of glass epoxy or the like. Semiconductor chips  102 ,  103  and  104  are mounted in this sequence by adhesive sheets (not shown) on a front surface of the substrate  101 . Note that, the semiconductor chip  102  is larger than the semiconductor chip  103 , and the semiconductor chip  103  is larger than the semiconductor chip  104 . Bonding wires  105 ,  106  and  107  are connected between electrode pads (not shown) of the semiconductor chips  102 ,  103  and  104  and conductive pads (not shown) of the substrate  101 . The semiconductor chips  102 ,  103  and  104  associated with the bonding wires  105 ,  106  and  107  are sealed by an epoxy resin layer  108 . On the other hand, solder balls  109  are provided on a back surface of the substrate  101 , and are connected through internal connections (not shown) within the substrate  101  to the conductive pads thereof.  
         [0024]    In the stacked chip-size package type semiconductor device of FIG. 1, however, the bonding wire  105  is outside of the largest semiconductor chip  102 , the bonding wire  106  is outside of the bonding wire  107  and the bonding wire  107  is outside of the bonding wire  108 , thus preventing the bonding wires  105 ,  106  and  107  from being short-circuited. That is, all the bonding wires  105 ,  106  and  107  are outside of the largest semiconductor chip  102 , so that the substrate  101  is much larger than the largest semiconductor chip  102 , which would increase the stacked chip-size package in size.  
         [0025]    In FIG. 2, which illustrates a first embodiment of the stacked chip-size package type semiconductor device according to the present invention, reference numeral  1  designates a substrate made of glass epoxy or the like. Semiconductor chips  4 ,  3  and  2  are mounted in this sequence on a front surface of the substrate  1 . Note that, the semiconductor chip  2  is larger than the semiconductor chip  3 , and the semiconductor chip  3  is larger than the semiconductor chip  4 . In this case, the semiconductor chip  4  is adhered by an adhesive sheet (not shown) to the substrate  1 . Also, the semiconductor chip  3  is adhered by a thermoplastic adhesive layer  3   a  to the semiconductor chip  4 , and the semiconductor chip  2  is adhered by a thermoplastic adhesive layer  2   a  to the semiconductor chip  3 . Bonding wires  5 ,  6  and  7  are connected between electrode pads (not shown) of the semiconductor chips  2 ,  3  and  4  and conductive pads (not shown) of the substrate  1 . The semiconductor chips  2 ,  3  and  4  associated with the bonding wires  5 ,  6  and  7  are sealed by an epoxy resin layer  8 . On the other hand, solder balls  9  are provided on a back surface of the substrate  1 , and are connected through internal connections (not shown) within the substrate  1  to the conductive pads thereof.  
         [0026]    In the stacked chip-size package type semiconductor device of FIG. 2, since only the bonding wire  5  is outside of the largest semiconductor chip  2 , i.e., the bonding wires  6  and  7  hardly affect the size of the substrate  1 , the size of the substrate  1  is brought close to that of the largest semiconductor chip  2 , which would decrease the stacked chip-size package in size.  
         [0027]    The method for manufacturing the stacked chip-size package type semiconductor device of FIG. 2 is explained next with reference to FIGS. 3A, 3B,  3 C and  4 .  
         [0028]    First, referring to FIG. 3A, a semiconductor chip  4  is mounted by an adhesive sheet (not shown) on a front surface of a substrate  1 . Then, bonding wire  7  is connected between electrode pads (not shown) of the semiconductor chip  4  and conductive pads (not shown) of the substrate  1 .  
         [0029]    Next, referring to FIG. 3B, a semiconductor chip  3  with a back surface coated by a thermoplastic adhesive layer  3   a  is prepared. In this case, as illustrated in FIG. 4, the thermoplastic adhesive layer  3   a  is constructed by an about 100 to 200 μm thick centered pedestal portion  301  for being in contact with the semiconductor chip  4 , an about 100 to 400 μm thick peripheral reinforcement portion  302  for preventing the semiconductor chip  3  from being deformed by a wire bonding operation and a thin portion  303  between the centered pedestal portion  301  and the peripheral reinforcement portion  302  for encapsulating the bonding wire  7 . Then, the semiconductor chip  3  with the thermoplastic adhesive layer  3   a  is moved down to the semiconductor chip  4 , so that the centered pedestal portion  301  of the thermoplastic adhesive layer  3   a  is in contact with the semiconductor chip  4 . Then, a heat operation is performed upon the thermoplastic adhesive layer  3   a,  so that the semiconductor chip  3  is mounted on the semiconductor chip  4 . Then, bonding wire  6  is connected between electrode pads (not shown) of the semiconductor chip  3  and conductive pads (not shown) of the substrate  1 .  
         [0030]    Next, referring to FIG. 3C, a semiconductor chip  2  with a back surface coated by a thermoplastic adhesive layer  2   a  is prepared. In this case, as illustrated in FIG. 4, the thermoplastic adhesive layer  2   a  is also constructed by an about 100 to 200 μm thick centered pedestal portion  201  for being in contact with the semiconductor chip  4 , an about 100 to 400 μm thick peripheral reinforcement portion  202  for preventing the semiconductor chip  2  from being deformed by a wire bonding operation and a thin portion  203  between the centered pedestal portion  201  and the peripheral reinforcement portion  202  for encapsulating the bonding wire  6 . Then, the semiconductor chip  2  with the thermoplastic adhesive layer  2   a  is moved down to the semiconductor chip  3 , so that the centered pedestal portion  201  of the thermoplastic adhesive layer  2   a  is in contact with the semiconductor chip  3 . Then, a heat operation is performed upon the thermoplastic adhesive layer  2   a,  so that the semiconductor chip  2  is mounted on the semiconductor chip  3 . Then, bonding wire  5  is connected between electrode pads (not shown) of the semiconductor chip  2  and conductive pads (not shown) of the substrate  1 .  
         [0031]    Finally, the semiconductor chips  2 ,  3  and  4  associated with the bonding wires  5 ,  6  and  7  are sealed by an epoxy resin layer  8  (see: FIG. 2), and solder balls  9  (see FIG. 2) are provided on a back surface of the substrate  1 , to thereby complete the stacked chip-size package type semiconductor device of FIG. 2.  
         [0032]    In the stacked chip-size package type semiconductor device of FIG. 1, the bonding wires  105 ,  106  and  107  are outside of the largest semiconductor chip  102  (see: FIG. 5A). On the other hand, in the stacked chip-size package type semiconductor device of FIG. 2, the bonding wire  5  is outside of the largest semiconductor chip  5  while the bonding wires  6  and  7  are inside of the largest semiconductor chip  5  (see: FIG. 5B). Thus, the length of the substrate  1  can be shortened by 2·Δ L as compared with the substrate  101 , which would decrease the stacked chip-size package type semiconductor device of FIG. 2 in size. Additionally, the total length of bonding wire made of Au can be decreased, which would decrease the manufacturing cost.  
         [0033]    Further, since the peripheral reinforcement portion  303  ( 203 ) of the thermoplastic adhesive layer  2   a ( 3   a ) has a high rigidity, even when a load is applied by a wire operation to the semiconductor chip  3  or  2 , the semiconductor chip  3  or  2  is hardly deformed.  
         [0034]    Although the thin portion  303 ( 203 ) is provided in the thermoplastic adhesive layer  3   a ( 2   a ), the thin portion  303 ( 203 ) can be removed as illustrated in FIGS. 6 and 7 which are modifications of FIGS. 2 and 4, respectively.  
         [0035]    In FIG. 8, which illustrates a second embodiment of the stacked chip-size package type semiconductor device according to the present invention, the semiconductor chips  3 ,  4  and  2  are mounted in this sequence on a front surface of the substrate  1 . In this case, the semiconductor chip  3  is adhered by an adhesive sheet (not shown) to the substrate  1 . Also, the semiconductor chip  4  is adhered by an adhesive sheet (not shown) to the semiconductor chip  3 , and the semiconductor chip  2  is adhered by a thermoplastic adhesive layer  2   a  to the semiconductor chip  4 .  
         [0036]    Even in the stacked chip-size package type semiconductor device of FIG. 8, since only the bonding wire  5  is outside of the largest semiconductor chip  2 , i.e., the bonding wires  6  and  7  hardly affect the size of the substrate  1 , the size of the substrate  1  is brought close to that of the largest semiconductor chip  2 , which would decrease the stacked chip-size package in size.  
         [0037]    The method for manufacturing the stacked chip-size package type semiconductor device of FIG. 8 is explained next with reference to FIGS. 9A and 9B.  
         [0038]    First, referring to FIG. 9A, semiconductor chips  6  and  7  are mounted by adhesive sheets (not shown) on a front surface of a substrate  1 . Then, bonding wires  6  and  7  are connected between electrode pads (not shown) of the semiconductor chips  3  and  4  and conductive pads (not shown) of the substrate  1 .  
         [0039]    Next, referring to FIG. 9B, a semiconductor chip  2  with a back surface coated by a thermoplastic adhesive layer  2   a  as illustrated in FIG. 4 is prepared. Then, the semiconductor chip  2  with the thermoplastic adhesive layer  2   a  is moved down to the semiconductor chip  4 , so that the centered pedestal portion  201  of the thermoplastic adhesive layer  2   a  is in contact with the semiconductor chip  4 . Then, a heat operation is performed upon the thermoplastic adhesive layer  2   a,  so that the semiconductor chip  2  is mounted on the semiconductor chip  4 . Then, bonding wire  5  is connected between electrode pads (not shown) of the semiconductor chip  2  and conductive pads (not shown) of the substrate  1 .  
         [0040]    Finally, the semiconductor chips  2 ,  3  and  4  associated with the bonding wires  5 ,  6  and  7  are sealed by an epoxy resin layer  8  (see: FIG. 8), and solder balls  9  (see FIG. 8) are provided on a back surface of the substrate  1 , to thereby complete the stacked chip-size package type semiconductor device of FIG. 8.  
         [0041]    Even in the above-described second embodiment, although the thin portion  203  is provided in the thermoplastic adhesive layer  2   a,  the thin portion  203  can be removed.  
         [0042]    In FIG. 10, which illustrates a third embodiment of the stacked chip-size package type semiconductor device according to the present invention, the semiconductor chips  4 ,  2  and  3  are mounted in this sequence on a front surface of the substrate  1 . In this case, the semiconductor chip  4  is adhered by an adhesive sheet (not shown) to the substrate  1 . Also, the semiconductor chip  2  is adhered by a thermoplastic adhesive layer  2   a  to the semiconductor chip  4 , and the semiconductor chip  3  is adhered by an adhesive sheet (not shown) to the semiconductor chip  2 .  
         [0043]    In the stacked chip-size package type semiconductor device of FIG. 10, since the bonding wires  5  and  6  are outside of the largest semiconductor chip  2 , i.e., the bonding wire  7  hardly affects the size of the substrate  1 , the size of the substrate  1  is brought close to that of the largest semiconductor chip  2 , which would decrease the stacked chip-size package in size.  
         [0044]    The method for manufacturing the stacked chip-size package type semiconductor device of FIG. 10 is explained next with reference to FIGS. 11A and 11B.  
         [0045]    First, referring to FIG. 11A, a semiconductor chip  4  is mounted by an adhesive sheet (not shown) on a front surface of a substrate  1 . Then, bonding wire  7  is connected between electrode pads (not shown) of the semiconductor chip  4  and conductive pads (not shown) of the substrate  1 .  
         [0046]    Next, referring to FIG. 11B, a semiconductor chip  2  with a back surface coated by a thermoplastic adhesive layer  2   a  as illustrated in FIG. 4 is prepared. Then, the semiconductor chip  2  with the thermoplastic adhesive layer  2   a  is moved down to the semiconductor chip  4 , so that the centered pedestal portion  201  of the thermoplastic adhesive layer  2   a  is in contact with the semiconductor chip  4 . Then, a heat operation is performed upon the thermoplastic adhesive layer  2   a,  so that the semiconductor chip  2  is mounted on the semiconductor chip  4 . Then, a semiconductor chip  3  is adhered by an adhesive sheet (not shown) to the semiconductor chip  2 . Then, bonding wires  5  and  6  are connected between electrode pads (not shown) of the semiconductor chips  2  and  3  and conductive pads (not shown) of the substrate  1 .  
         [0047]    Finally, the semiconductor chips  2 ,  3  and  4  associated with the bonding wires  5 ,  6  and  7  are sealed by an epoxy resin layer  8  (see: FIG. 10), and solder balls  9  (see FIG. 10) are provided on a back surface of the substrate  1 , to thereby complete the stacked chip-size package type semiconductor device of FIG. 10.  
         [0048]    In the above-described third embodiment, although the thin portion  203  is provided in the thermoplastic adhesive layer  2   a,  the thin portion  203  can be removed.  
         [0049]    In the above-described embodiments, three semiconductor chips are stacked on a substrate, however, the present invention can be applied to a stacked chip-size package where two, four or more semiconductor chips are stacked.  
         [0050]    As explained hereinabove, according to the present invention, since the largest semiconductor chip is not the lowest semiconductor chip, the total number of bonding wires outside of the largest semiconductor chip is decreased, so that the size of a substrate can be brought close to that the largest semiconductor chip, thus decreasing the stacked chip-size package in size.