Abstract:
A high density static RAM integrated circuit including a pair of bit lines to which pull-up loads are respectively connected, a plurality of memory cells which are connected across the pair of bit lines, a pair of data buses which are connected to the pair of bit lines, and a sense amplifier which is connected to the pair of bit lines through the pair of data buses, the pair of data buses being respectively provided with charging circuits each of which has a control terminal for varying a pull-up current, amplified outputs of the sense amplifier being fed back to the control terminals of the charging circuits, the data bus on a high potential side being charged by the corresponding charging circuit. As a result, the current which flows across a common data bus line connected to a higher side of the selected bit lines is increased, thereby enabling a high speed read out operation in the high density static RAM.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a static RAM (random access memory) integrated circuit of high memory density. More particularly, it relates to a fast-access RAM which, in reading out stored data from a memory cell, changes a data bus line load in correspondence with the data to be read out, thereby realizing fast read-out. 
     When it is intended to make the memory density of a static RAM high, the size of each cell for storing data becomes small. Since the cell of the ordinary static RAM is constructed of a flip-flop circuit, the small cell size results in lowering the transconductances g m  of MIS field effect transistors (hereinbelow, termed &#34;MOS FETs&#34;) for a cell driver. In order to attain the function of the memory cell satisfactorily (that is, to cause the transistor on the &#34;ON&#34; side of the cell to pull down the corresponding bit line), current which flows through a load for pulling up the bit line must be reduced. By way of example, when a MOS FET is used as the load, its transconductance g m  must be made small. This causes degradation in the charging ability of the bit line, that is, lowering in the changing rate thereof from a low level to a high level, so that the rise of the potential of the bit line becomes slow. Under such a condition, it is difficult to make the operation of the high-density static RAM fast. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a high-density static RAM capable of fast operation. 
     In order to accomplish the above object, according to the present invention, current which flows through the load of a data bus line (which may be regarded as being equivalent to a bit line in points of potential changes etc. because it is connected to the bit line through a column selecting gate), e.g., a pull-up FET, in other words, a charging current is changed in accordance with a signal read out of one of the memory cells. 
     The memory circuit according to the present invention comprises: a pair of bit lines to which pull-up loads are respectively connected; a plurality of memory cells connected to said pair of bit lines; a pair of data bus lines operatively connected to said pair of bit lines; a sense amplifier which is connected to said pair of bit lines through said pair of data bus lines; and a charging circuit operatively connected to said pair of data bus lines for charging up one of said pair of data bus lines whose potential is higher than the other one of said pair of data bus lines, said charging circuit having a terminal for receiving an output from said sense amplifier and being activated by said output. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing an embodiment of the present invention; 
     FIG. 2 is a graph showing the characteristic curves of signal voltages versus the supply voltage; 
     FIG. 3A and 3B are waveform diagrams of signals in a conventional circuit; and 
     FIG. 3B is a waveform diagram of signals in the embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Hereunder, the present invention will be described in detail in conjunction with an illustrated embodiment. 
     FIG. 1 shows one embodiment of the present invention. MC indicates a memory cell, and SA a sense amplifier. X O  -X N  indicate word lines, and Y O  -Y N  column selecting signal lines. Q 1  -Q 4  denotes MOS FETs for column selecting gates, and Q 5  and Q 6  MIS FETs (hereinafter, MOS FETs) as bit line loads. MOS FETs Q 7  and Q 8  constitute a cell driver, and are respectively provided with load elements (resistors) R 1  and R 2 . MOS FETs Q 9  and Q 10  function as transfer gates. BL and BL designate a pair of bit lines, and DB and DB a pair of data bus lines. MOS FETs Q 11  and Q 12  form charging circuits for the data bus lines DB and DB, respectively. The sense amplifier SA is a differential amplifier in which two inverters include depletion-mode load MOS FETs Q 13  and Q 14  and enhancement-mode driving MOS FETs Q 15  and Q 16  having sources connected in common. In addition, MOS FETs Q 17  and Q 18  are connected to the common source in parallel with each other. Outputs DF and DF are fed back to the MOS FETs Q 17  and Q 18 , to correct a reference voltage V ref  into an appropriate value at all times so as to effect a linear operation. The input of the sense amplifier SA on the side of the MOS FET Q 15  is the potential of the data bus line DB, while the input thereof on the side of the MOS FET Q 16  is the potential of the data bus line DB. The amplified output DF identical in polarity to the potential of the data bus line DB is obtained from the drain side of the MOS FET Q 15 , and is fed back to the gate of the MOS FET Q 11 . On the other hand, the amplified output DF identical in polarity to the potential of the data bus line DB is obtained from the drain side of the MOS FET Q 16 , and it is fed back to the gate of the MOS FET Q 12 . Symbol V cc  signifies a power source, and a downward arrow signifies grounding. 
     In the sense amplifier SA, the outputs DF and DF are respectively fed back to the gates of the MOS FETs Q 17  and Q 18 . Therefore, the reference voltage V ref  is virtually grounded or becomes a constant voltage with respect to the inputs DB and DB. In addition, the reference voltage V ref  is in-phase with the supply voltage. That is, the reference voltage V ref  rises as the supply voltage becomes higher, and the former lowers as the latter becomes lower. When the input signal DB (here, a signal shall be indicated by the same symbol as that of the corresponding line) of the MOS FET Q 15  has changed to the high level (&#34;H&#34;) (increased) and the input signal DB of the MOS FET Q 16  has changed to the low level (&#34;L&#34;) (decreased), the output potential DF lowers and the output potential DF rises. Upon receiving these outputs, the MOS FET Q 17  lowers its degree of conduction, and the MOS FET Q 18  raises the same. The combined resistance of the parallel circuit comprising transistors Q 17  and Q 18  is substantially invariable. Accordingly, the reference voltage V ref  remains constant. In contrast, when both the input voltages of the MOS FETs Q 15  and Q 16  have increased, both the degrees of conduction of the transistors Q 17  and Q 18  lower, so that the reference voltage V ref  rises. In addition, when both the input voltages of the MOS FETs Q 15  and Q 16  have decreased, both the degrees of conduction of the transistors Q 17  and Q 18  rise, so that the reference voltage V ref  lowers. As a result, the voltages DB, DB and V ref  change as shown in FIG. 2. In the figure, the axis of the abscissa represents the supply voltage V cc  which causes the in-phase variations of the data bus line potentials, while the axis of the ordinate represents voltages DB&#39; and DB&#39; and the reference voltage V ref . The voltage DB&#39; is the voltage of the data bus DB at the high level thereof, while the voltage DB&#39; is the voltage of the data bus DB at the low level thereof. In order for the sense amplifier SA to execute a linear operation, a value obtained by adding the reference voltage V ref  and the source-drain voltage of each MOS FET Q 15  or Q 16  needs to lie between the voltages DB&#39; and DB&#39;. As is apparent from FIG. 2, the aforementioned value of the sense amplifier SA shown in FIG. 1 corresponds to a dotted line D in FIG. 2. Therefore, the MOS FETs Q 15  and Q 16  constituting the differential amplifier execute the linear operation. 
     Accordingly, when the potentials of the inputs DB and DB fluctuate even slightly, this amplifier generates the amplified outputs DF and DF following the fluctuations. That is, the amplifier operates as an analog linear amplifier in which when the input DB changes from &#34;L&#34; (low level) to &#34;H&#34; (high level) and the input DB from &#34;H&#34; to &#34;L&#34;, the output DF rapidly shifts from &#34;H&#34; to &#34;L&#34; and the output DF from &#34;L&#34; to &#34;H&#34;. In addition, the outputs DF and DF are respectively fed back to the gates of the MOS FETs Q 11  and Q 12  with the same polarity. Then, the potential changes of the data bus line and the bit line shifting from &#34;L&#34; to &#34;H&#34;, e.g., DB and BL are promoted by the charging due to the MOS FET Q 11  and are therefore effected quickly. This is equivalent to the fact that the transconductance g m  of the bit line load transistor Q 5  increases temporarily during the charging. On the other hand, regarding the potential changes of the data bus line and the bit line DB and BL shifting from &#34;H&#34; to &#34;L&#34;, the MOS FET Q 12  has its gate supplied with the amplified output DB changing from &#34;H&#34; to &#34;L&#34; and turns &#34;off&#34;. Therefore, the discharging characteristics of the data bus line and bit line are not different from those based on only the bit line load MOS FET Q 6 . Since the transconductance g m  of the MOS FET Q 6  remains low, the pull-down of the data bus line and bit line is satisfactorily effected by the cell driver MOS FET Q 8 . 
     In FIG. 1, OB is an output buffer which recives the signals DF and DF and outputs a read out signal to an output terminal OUT. 
     FIGS. 3A and 3B are signal waveform diagrams showing the variations of data bus line signals DB and DB, and output signals DF, DF in a conventional circuit and the embodiment of the present invention, respectively. The conventional circuit doesn&#39;t comprise the charging transistors Q 11  and Q 12  in FIG. 1. In the conventional circuit&#39;s signal waveform illustrated in FIG. 3A, when data to be read out changes from &#34;H&#34; to &#34;L&#34;, the signal DB changes from &#34;H&#34; to &#34;L&#34; rapidly, but the signal DB changes from &#34;L&#34; to &#34;H&#34; slowly. 
     This is the reason that the discharging ability of transistor Q 7  (Q 8 ) is better than the charging ability of transistor Q 6  (Q 5 ) generally. The slow change is attributed to a small charging current, and results in delaying the change of the output DF from &#34;H&#34; to &#34;L&#34;. In the embodiment of the present invention illustrated in FIG. 3B, the signal DB changes from &#34;H&#34; to &#34;L&#34; rapidly, and the charging current is consequently increased, so that the rise of the signal DB is fast. Also the signal DF falls faster than in the conventional circuit. Although FIG. 3B refers to the case where the data to be read out changes from &#34;H&#34; to &#34;L&#34;, changes from &#34;L&#34; to &#34;H&#34; or the rises of the signals DB and DF quicken in the converse case where the data to be read out changes from &#34;L&#34; to &#34;H&#34;. 
     As described above, in the memory of the present invention, in accordance with the read-out result, the charging MOS FET connected to the data bus line on the &#34;H&#34; side turns &#34;on&#34; and performs the pull-up operation, but the charging MOS FET connected to the data bus line on the &#34;L&#34; side turns &#34;off&#34; and contributes nothing. The next selection of a cell under this state will now be considered. It is supposed that the selected cell belongs to the same column as and a different word line from those of the preceding cell and that it stores data opposite to the data of the preceding cell. Then, the &#34;ON&#34; MOS FET of the selected cell pulls down the bit line and the data bus line on the &#34;H&#34; side (BL and DB in the present embodiment). In this regard, since the MOS FET Q 11  is included, the pull-down load becomes greater than in the conventional. However, the presence of the MOS FET Q 11  forms no special obstacle for reasons described hereunder. Unlike the nonlinear type sense amplifier of the conventional memory which does not operate unless a potential difference on the order of ±0.5 V arises, the sense amplifier SA of the memory of the present invention is a linear amplifier which has the widest possible range of proportional operation as described before. Therefore, as soon as the bit line and the data bus line begin to change their potential levels, the sense amplifier SA starts operating so as to promote the changes. Moreover, originally the memory cell of the specified type has the transconductance g m  ratio between the driver MOS FETs Q 7  and Q 8  and the transfer gate MOS FETs Q 9  and Q 10  selected properly, so that the bit line and the data bus line close to the power source as viewed from the minute or small memory cell can be sufficiently pulled down. After all, according to the present invention, the transconductance g m  of the data bus load is equivalently made high during the charging and low (as usual) during the discharging, so that the transconductance g m  of the bit line load can be set in a ratioless form relative to the transconductance g m  of the cell driver. Accordingly, the signal change of the bit line is efficiently rendered fast, and the read-out speed is enhanced. By the way, read-out outputs are derived by passing the outputs DF and DF of the sense amplifier SA through the output buffer OB. 
     While, in the embodiment of the present invention, the MOS FETs Q 5  and Q 6  have been used as the loads, they can be replaced with resistors. Further, while the MOS FETs have been referred to in the description, other semiconductor devices are also usable. 
     As set forth above, according to the present invention, a bit line load current, in other words, a charging current which is lower because of a high memory density of a memory is changed in response to a signal to be read out, so that fast read-out is permitted even when the transconductance g m  of a cell driver is low.