Abstract:
The present invention relates to a digital-to-digital code converter, or decimator, which implements sinc 3  processing. The input signal (X) to the code converter comprises a series of groups, each group including a series of N digital sample values occurring at high rate (1/τ) which are converted within the converter, using sinc 3  processing, into a single digital value occurring at, for example, a (1/N)τ rate for delivery to the converter output (Y). The code converter comprises three processing stages in cascade, where each stage includes separate accumulation means, each accumulation means arranged to add, during each series of N input sample values, the signal value received by that stage from the next preceding stage. Each of the three stages further includes a separate subprocessing means for processing the resultant accumulated digital value from the associated accumulation means at the end of each group period to produce a separated processed digital value which, when combined with the processed digital values from the other stages at the end of a group period, provides a single sinc 3  processed digital value for the N input signal samples of each input group.

Description:
TECHNICAL FIELD 
     The present invention relates to a digital-to-digital code converter for implementing sinc 3  processing to achieve very good resolution. 
     DESCRIPTION OF THE PRIOR ART 
     There is much interest in the oversampling method of analog-to-digital conversion since it eliminates the need for precision analog circuits and filters. In this regard see, for example, the articles by (1) J. C. Candy et al. in IEEE Transactions On Communications, Vol. COM-29, No. 6, June 1981, at pages 815-830; (2) J. C. Candy in IEEE Transactions On Communications, Vol. COM-33, No. 3, March 1985 at pages 249-258; and (3) J. C. Candy in IEEE Transactions On Communications, Vol. COM-34, No. 1, January 1986 at pages 72-76. The method relies on a simple modulator to convert signals into digital form at very high speeds. This modulation technique uses low pass filtering in a digital circuit and resampling at a low rate, a process that has been named &#34;decimation&#34;. More particularly, decimation transforms the digitally modulated signal from short words occurring at a high sampling rate to longer words at a lower rate, e.g., Nyquist rate. 
     It has been found that incorporating the resampling concept into a digital filter can greatly simplify the circuits. For example, in U.S. Pat. No. 4,281,318 issued to J. C. Candy et al. on July 28, 1981, a two-stage digital-to-digital code converter, or decimating filter, is disclosed which receives a series of input samples at rate mf 0  and generates a corresponding series of output samples at rate f 0 , using overlapping triangular accumulation. The Candy et al. patent, with its two-stage digital-to-digital code converter, discloses that for decimation with sigma delta modulation, the decimating filter requires one more stage than the modulator. 
     The problem in the prior art is to provide a digital-to-digital code converter similar to the Candy et al. patented arrangement which can achieve improved resolution in the output signal. 
     SUMMARY OF THE INVENTION 
     The problem of the prior art has been solved in accordance with the present invention which relates to a digital-to-digital code converter which includes three cascaded stages to implement sinc 3  processing and allow a second stage to be used in the sigma delta modulator and thereby achieve improved resolution. 
     It is an aspect of the present invention to provide a digital-to-digital code converter, or decimator, which includes an input terminal, an output terminal, and processing means interconnecting the input and output terminals which performs sinc 3  processing on each sequential input group of N digital sample values, received at the input terminal, to generate a representative single digital output value at a (1/N) rate at the output terminal. 
     Other and further aspects of the present invention will become apparent during the course of the following description and by reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a block diagram of a preferred digital-to-digital code converter arrangement in accordance with the present invention; 
     FIG. 2 illustrates typical clock signals for the code converter of FIG. 1; 
     FIGS. 3-13 graphically illustrate how each sample of an exemplary sequential 8-sample input group is weighted overall at separate points in the three stages of the digital-to-digital code converter of FIG. 1 to generate the sinc 3  processed associated output signal value; and 
     FIG. 14 graphically illustrates how each of the single output signal values of the code converter of FIG. 1 is generated from the overall weighting of each exemplary 8-sample serially received input group in accordance with the overall weighting diagrams of FIGS. 3-13. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 illustrates a preferred arrangement of a digital-to-digital code converter or decimator 10 in accordance with the present invention, which preferred arrangement includes three cascaded stages 11, 12, and 13 to implement sinc 3  processing of each group of N samples of an input signal. For purposes of definition, it is to be understood that each sample is described as a digital word which may comprise any number of bits. Hereinafter, however, it will be assumed that each input word comprises only one bit which has either a zero or a one value, but longer words will appear at other points in the circuit, particularly at the output. 
     More particularly, the code converter 10 of FIG. 1 receives an input signal X at a first sample rate of 1/τ samples per second at the input to first stage 11, and generates therefrom an output signal Y at the output of the third stage including a slower sample rate which is (1/N) that of the input signal X sample rate. With code converter 10 of FIG. 1, two clocks C 1  and C 2  are used for timing purposes in certain circuits within the three stages, with the pulse sequences of these two clocks, and an inverted clock sequence C 2 , being illustrated in FIG. 2. As shown in FIG. 2, clock pulses of clock C 1  correspond to the digital sample value rate (1/τ) within each group of N samples of input signal X, while the clock C 2  includes pulses which are &#34;N&#34; times slower than that of the input signal sample rate and correspond to the sample rate of the output signal Y. As stated above, clock C 2  is merely the inverse of clock C 2  . 
     In the code converter of FIG. 1, the input signal X at the sample rate (1/τ), is received at an adder 20 1  of first stage 11. Each digital sample value of input signal X is added to the contents of a register 21 1  in adder 20 1  every τ seconds, and the output of adder 20 1  is gated to register 21 1  via a gate 22 1  which is clocked by clock signal C 2 . Concurrent with this occurrence in first stage 11, the output from adder 20 1  is sent to adder 20 2  of second stage 12 where this output from adder 20 1  is added to the current contents of register 21 2  every τ seconds. The resultant output from adder 20 2  is then gated back into register 21 2  via gate 22 2  which is enabled by clock C 2 . This output from adder 20 2  is also sent to adder 20 3  in third stage 13 to which the current contents of register 21 3  is added every τ seconds before the resultant sum is used to update register 21 3  via gate 22 3 . 
     During the N th  sample period of each group of N samples, the input to each of adders 20 1 , 20 2  and 20 3  is added to the current contents of registers 21 1 , 21 2  and 21 3 , respectively. However, during this N th  sample period, clock C 2  inhibits gates 22 1 , 22 2  and 22 3  for one sample period, and clock C 2  diverts the resultant output sums from adders 20 1 , 20 2  and 20 3  to registers 24 1 , 24 2  and 24 3 , respectively. Therefore, during the N th  sample period of each group, registers 21 1 , 21 2  and 21 3  are cleared because they have no input as a result of the inhibiting of these registers by gates 22 1 , 22 2  and 22 3 . 
     These above-described actions result in the sum of N consecutive input sample values of a group being placed in register 24 1  at regular intervals of Nτ seconds. This sum in register 24 1  may be expressed as: ##EQU1## where x(nτ) represents the input samples, z -1  is a delay τ, and z -N  is a delay Nτ. The cycle then recommences in first stage 11. Concurrent with register 24 1  receiving the sum of N consecutive input sample values of a group as expressed in Equation (1), a sum of partial sums of the input samples of a group, as found at the output of adder 20 2  during the N th  sample period, is placed in register 24 2 , which sum of partial sums can be expressed as: ##EQU2## Concurrent therewith, a sum of partial sums of partial sums from the input sample group, as found at the output of adder 20 3  during the N th  sample period of a group, is placed in register 24 3 , which sum of partial sums of partial sums may be expressed as: ##EQU3## 
     At the outputs of registers 24 1 , 24 2  and 24 3  are three separate signals designated Y 1 , Y 6  and Y 10 , respectively, that are further processed in the three stages 11-13 at the desired output rate and combined in adder 37 to produce the net output y where ##EQU4## Three practical details significantly simplify the circuits needed for this decimation or code conversion. First, the input words are short, usually 1-bit long, so the accumulations need not be large, but they operate at high speed. Bits of the words are usually carried in parallel on separate wires. Second, words in registers 24 1  to 24 3  occur at a low rate and they may be outputted from registers 24 1 , 24 2  and 24 3  on single wires as bits in time sequence so that all of the circuits that follow are simple. Finally, the decimation ratio is usually a power of two, 2 n , therefore, multiplying by N or (N/2) is simply a shift in significance of the word involving no arithmetic operation. 
     In operation, it will be assumed hereinafter that an output word is generated for every 8 input samples (N=8), occurring at the C 1  clock rate. For purposes of explanation, a particular sequence of 8 input samples will be designated X 1  to X 8 . These eight digital sample values are accumulated, as will be described hereinafter, to form composite digital sample values at each of registers 24 1 , 24 2  and 24 3  which have been designated Y 1 , Y 6  and Y 10 , respectively. FIGS. 3-13 show how each of the 8 input digital sample vaues of the group received at the input are weighted overall, including any weights used for a sample value at all prior locations, at the location associated with that weighting diagram within the three stages 11-13, to achieve the sinc 3  processing and produce the accumulated single digital output value forming the final single digital output value Y. It should be realized that each of the input digital sample values X 1  to X 8  in an input group has a separate amplitude or value indication. Therefore, for each location associated with FIGS. 3-13, the overall resultant digital value Y i  at the associated code converter location is conceptually obtained by applying the indicated overall weight value shown in the associated Figure to each of the corresponding one of the eight exemplary original input digital sample values for accumulation of the resultant digital value. 
     In FIG. 1, the output signal Y 1  from register 24 1 , in first stage 11, includes a single digital value represented by an accumulation of the N=8 exemplary sequential input digital sample values X 1  to X 8  of each input group weighted with a separate corresponding unity weight W 1  to W 8 , respectively, as shown in FIG. 3. The output signal Y 1  from register 24 1  is then multiplied by N/2 in multiplier 25 to produce a digital value Y 2  representative of the accumulation of the 8 exemplary sequential input digital sample values with an overall weight, as shown in FIG. 4, including all weights used from the input through multiplier 25. More particularly, for the exemplary condition of N=8, the accumulated value Y 2  is derived from an accumulation of the eight digital samples of a group individually weighted by unity to produce Y 1 , as shown in FIG. 3, and then multiplied by individual weights of (N/2) effectively applid to each digital sample by multiplier 25 to form the overall single accumulated value Y 2 . Therefore, FIG. 4 shows the overall weight of value 4 applied up to that point to each corresponding input digital sample value of a group in the original accumulation signal Y 1  times the weights applied by multiplier 25 to produce the value Y 2 . 
     The Y 2  output signal is then multiplied by N in multipler 26 to produce a digital value Y 3  which is an accumulation of the eight exemplary sequential input digital sample values weighted overall as shown in FIG. 5. The Y 3  output digital value is added in adder 27 to the output digital value Y 10  from register 24 3  in third stage 13 to produce a Y 4  digital value which is the accumulation of the eight exemplary sequential digital input samples weighted overall as shown in FIG. 6. In subtracter 28, the Y 8  digital value from second stage 12 is subtracted from the Y 4  digital value to produce an output digital value Y 5  from first stage 11 which is delayed by one output word time period Nτ in delay unit 29. 
     In second stage 12, the output digital value Y 6  from register 24 2  is an overall digital value of the eight exemplary sequential input word sample weighted as shown in FIG. 8. This digital value is multiplied by N in multiplier 30 to generate an overall digital value Y 7  which is an accumulation of the eight exemplary sequential digital input samples weighted overall as shown in FIG. 9. The Y 2  digital value from multiplier 25 in first stage 11 is added in adder 31 to the Y 7  digital value to generate an overall digital value Y 8  which is an accumulation of the eight input digital samples weighted overall as shown in FIG. 10. Second stage 12 includes a combination of (1) the Y 3  digital value added, in adder 32, to the delayed Y 5  output digital value from first stage 11; (2) the output digital value from adder 32 added, in adder 33, to the Y 8  digital value; and (3) the output digital value Y 10  from third stage 13, which has been weighted by N in multiplier 34, subtracted from the output digital value from adder 33 in subtracter 35. The combination of these digital values before being added to the Y 5  digital value from first stage 11 is an overall digital value designated Y 9  which is an accumulated digital value of the exemplary sequential eight input digital samples weighted overall as shown in FIG. 11. Therefore, the output digital value from the first, second and third stages 11-13 correspond to the exemplary sequential eight input digital samples weighted as shown in FIGS. 7, 11, and 12, respectively, and make up the output digital value Y from code converter 10 at the output of adder 37. 
     It should be understood that the exemplary eight sequential input signal samples forming an input group and arriving at the input to adder 20 1  in first stage 11 generate (1) the Y 5  output digital sample from first stage 11 during a first output word period Nτ; (2) the Y 9  output digital value from second stage 12 during a second next subsequent output word period Nτ; and (3) the Y 10  output digital value from third stage 13 during a third next subsequent output word period Nτ because the sequential accumulations associated with an input group of N samples are transferred between the three stages based at the C 2  clock rate shown in FIG. 2. Therefore, by delaying the Y 5  output from first stage 11 by one output word period Nτ in delay 29 and adding the delayed Y 5  output to the Y 9  output from second stage 12 and then delaying the resultant digital value by another output word period in delay 36 before adding the delayed resultant value to the Y 10  output from third stage 13, a resultant output digital value Y is obtained which is the accumulation of the eight input digital samples weighted as shown in FIG. 13 in the three stages. 
     Since a new digital value is outputted once every output word period from each of the three stages, and it takes three output word periods before the overall accumulations in the three stages are combined to produce an associated single digital value output Y, the result of three sequential output words can be depicted as shown in FIG. 14. The top portion of FIG. 14 depicts three sequential weighting curves 40-42 of FIG. 13 corresponding to an exemplary first to third input group sequence, respectively, each sequential weighting curve 40-42 starting one output word period apart. The output digital value 43 associated with weighting curve 40 of the first output word, in the three output word sequence, occurs at the conclusion of the three output word period necessary for the sinc 3  processing in the three stages of code converter 10, followed by the output digital values 44 and 45 associated with weighting curves 41 and 42, respectively, spaced by one output word period Nτ. From the above description it can be seen that in accordance with the present invention, the code converter, or decimator, of FIG. 1 provides sinc 3  processing.