Abstract:
This invention discloses a semiconductor device with latch-up prevention mechanisms. According to one embodiment, it comprises a first doping region, wherein one or more semiconductor devices are disposed therein and coupling to a first supply voltage, a second doping region adjacent to the first doping region, wherein the second doping region is an Nwell, and at least one PMOS capacitor is disposed therein and coupled to a second supply voltage higher than the first supply voltage, wherein one or more deep N-type implant regions are disposed beneath a bulk pick-up N+ region of the PMOS device in the second doping region, and a P-type region disposed between the first and second doping regions.

Description:
CROSS REFERENCE  
       [0001]     The present application claims the benefit of U.S. Provisional Application Ser. No. 60/740,104, which was filed on Nov. 28, 2005. 
     
    
     BACKGROUND  
       [0002]     The present invention relates generally to semiconductor devices, and, more particularly, to prevention of latch-up in the semiconductor devices.  
         [0003]     Latch-up is defined as the creation of a low impedance path between power supply rails (a positive power supply voltage, or Vdd, and a complimentary low power supply voltage, or GND) as a result of triggering a parasitic device. In this condition, excessive current flow is possible, and a potentially destructive situation exists. After even a very short period of time in this condition, the device in which it occurs can be destroyed or weakened and potential damage can also occur to other components in the system.  
         [0004]     A cause of latch-up as stated earlier, is a result of triggering a parasitic device, a silicon controlled rectifier (SCR) in effect, formed by a four-layer pnpn device of at least one pnp and at least one npn bipolar transistors connected as shown in  FIG. 1A . The SCR is a device normally off in a “blocking state”, in which negligible current flows, but conducts from a node A to a node K only if an excitation is applied to a gate G.  
         [0005]     Referring to  FIG. 1A , the SCR conducts as a result of current from the gate G injected into the base of a npn bipolar transistor Q 2 , which causes current flow in the base-emitter junction of the a pnp bipolar transistor Q 1 . The pnp bipolar transistor Q 1  turns on causing further current to be injected into the base of the npn bipolar transistor Q 2 . This positive feedback condition ensures that both bipolar transistors, Q 1  and Q 2 , saturate. The current flowing through one bipolar transistor, Q 1  or Q 2 , ensures that the other transistor remains in saturation. Then the SCR is said to be “latched”.  
         [0006]     Once being latched, the SCR no longer depends on the trigger source applied to the gate G, a continual low-impedance path exists between the node A and the node K. Since the trigger source needs not to be constantly present, and removing it will not turn off the SCR, it could simply be a spike or a glitch. If, however, the voltage applied across the SCR can be reduced or the current flowing through it can be decreased to a point where it falls below a holding current value, Ih, as shown in  FIG. 1B , then the SCR will be switched off.  
         [0007]      FIG. 2A  shows a traditional complimentary metal-oxide-semiconductor (CMOS) structure, which forms a pair of parasitic bipolar transistors, Q 1  and Q 2  on a p-type semiconductor substrate. Rs and Rw represents resistances of a Psubstrate and an Nwell, respectively.  FIG. 2B  is a schematic diagram illustrating an equivalent parasitic SCR device formed by the two parasitic bipolar transistors, Q 1  and Q 2 .  
         [0008]     Traditional view of CMOS latch-up is a phenomenon between a P-type metal-oxide-semiconductor (PMOS) structure, which is connected to the Vdd, and an N-type metal-oxide-semiconductor (NMOS) structure, which is connected to GND. But parasitic SCR structure can also be formed between two adjacent PMOS cells as shown in  FIGS. 4A and 4B . Even though being applied to the same voltage Vdd, the node V 15  and V 16  belong to different packaging pads, and during an electrostatic discharge (ESD) test, a latch-up condition can also be created in these parasitic SCR circuits.  
         [0009]     Note that in  FIG. 4B , there is a shallow-trench-isolation (STI) between the two adjacent PMOS structures. But with advanced processes, where devices are very close to each other, the STI, and even a guard ring are too shallow to prevent the latch-up from happening.  
         [0010]     As such, what is desired is robust latch-up prevention circuit structure between two adjacent PMOS structures.  
       SUMMARY  
       [0011]     This invention discloses semiconductor latch-up prevention circuits. According to one aspect of the invention, one of the latch-up prevention circuits comprises a first doping region, wherein one or more semiconductor devices are disposed therein and coupling to a first supply voltage, a second doping region adjacent to the first doping region, wherein the second doping region is an Nwell, and at least one PMOS capacitor is disposed therein and coupled to a second supply voltage higher than the first supply voltage, wherein one or more deep N-type implant regions are disposed beneath a bulk pick-up N+ region of the PMOS device in the second doping region, and a P-type region disposed between the first and second doping regions.  
         [0012]     According to another aspect of the invention, one of the latch-up prevention circuits comprises a first doping region, wherein one or more semiconductor devices are disposed therein and coupling to a first pad, a second doping region adjacent to the first doping region, wherein the second doping region is an Nwell, and at least one PMOS capacitor is disposed therein and coupled to a second pad, wherein one or more deep N-type implant regions are disposed beneath a bulk pick-up N+ region of the PMOS device in the second doping region, and a P-type region disposed between the first and second doping regions.  
         [0013]     The construction and method of operation of the invention, however, together with additional objectives and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIG. 1A  illustrates a basic SCR circuit structure.  
         [0015]      FIG. 1B  illustrates the current-voltage (I-V) characteristic of a latch-up phenomenon.  
         [0016]      FIGS. 2A and 2B  show a parasitic SCR and its equivalent circuit formed in a traditional CMOS structure.  
         [0017]      FIG. 3  is a schematic diagram showing ESD protection circuits of two adjacent packaging pads.  
         [0018]      FIGS. 4A through 4D  illustrate parasitic SCR structures and their corresponding equivalent circuit formed in two adjacent P-cells that can be found in ESD protection circuits.  
         [0019]      FIG. 5  illustrates a P+ guard ring disposed between two adjacent P-cells according to one embodiment of the present invention.  
         [0020]      FIG. 6  illustrates an Nwell pick-up N+ moving away from the Nwell edge to increase Nwell resistance in the parasitic SCR according to another embodiment of the present invention.  
         [0021]      FIG. 7  illustrates a deep N+ implant added beneath a Nwell pick-up N+ of a PMOS device according to yet another embodiment of the present invention.  
         [0022]      FIG. 8  illustrates a deep P+ implant added beneath a STI between two adjacent Nwells according to yet another embodiment of the present invention. 
     
    
     DESCRIPTION  
       [0023]     The present invention discloses layout and implant methods for preventing latch-up between two metal-oxide-semiconductor (MOS) devices, particularly in ESD protection circuits.  
         [0024]      FIG. 1A  illustrates a basic silicon controlled rectifier (SCR) circuit structure, formed by a four-layer pnpn device  100  of at least one pnp bipolar transistor Q 1  and at least one npn bipolar transistor Q 2 . The SCR is a normally off device in a “blocking state”, in which negligible current flows, but conducts from a node A to a node K only if an excitation is applied to a gate G.  
         [0025]      FIG. 1B  illustrates the current-voltage (I-V) characteristic of the SCR shown in  FIG. 1A . When a voltage between node A and node K exceed a voltage Vs as being triggered, the SCR will latch up with the current flowing through it drastically rises. But when the current falls below a holding current value, Ih, the SCR will be switched off.  
         [0026]      FIGS. 2A and 2B  shows that a parasitic SCR exists in a traditional complementary metal-oxide-semiconductor (CMOS) structure and its equivalent circuit, respectively. Referring to  FIG. 2A , P+—Nwell—Psubstrate in a P-cell forms a pnp bipolar transistor  210 . Nwell—Psubstrate—N+ in an N-cell forms an npn bipolar transistor  220 . The higher the Nwell resistance  230  is, the easier the pnp bipolar transistor  210  can be triggered. Higher Psubstrate resistance  240  also makes the npn bipolar transistor  220  easier to trigger. So in order to prevent the parasitic SCR from latching up, both the Nwell and the Psubstrate resistances should be kept at a minimum.  
         [0027]     Conventionally, guard rings are widely used to prevent latch-ups between P-cell and N-cell in a CMOS circuit. A guard ring for a P-cell comprises a P+ active region connected to a low supply voltage (GND) outside the Nwell. A guard ring for an N-cell comprises an N+ active region connected to a complementary high supply voltage (Vdd). But parasitic SCR can also be found between two adjacent P-cells, which are traditionally not protected by guard rings.  
         [0028]      FIG. 3  is a schematic diagram showing ESD protection circuits  310  and  320  for two adjacent packaging pads  315  and  325 , respectively. P-type metal-oxide-semiconductor (PMOS) transistors  330  and  350  are connected as reversed biased diodes, so are N-type metal-oxide-semiconductor (NMOS) transistor  332  and  352 . The ESD protection circuits  310  and  320  also include junction diodes  334  and  354 , PMOS capacitors  336  and  356 , and NMOS capacitor  358 . The power Vdd is connected to the pad  15 &#39;s ESD protection circuit  310  at a node V 15 , while the GND is connected to the ESD protection circuit  310  at a node G 15 . The Vcc is connected to the pad  16 &#39;s ESD protection circuit  320  at a node V 16 , while the GND is connected to the pad  16 &#39;s ESD protection circuit  320  at a node G 16 . Among these ESD protection devices of two adjacent pads  315  and  325 , parasitic SCR structures can be found between two P-cells. The power Vdd and the power Vcc have the different voltage level for driving the transistors. For example,.the Vdd is 3.3 V and the Vcc is 1.5 V.  
         [0029]      FIGS. 4A through 4D  illustrate parasitic SCR structures and their corresponding equivalent circuit formed in two adjacent P-cells as well as between a P-cell and an N-cell.  FIG. 4A  shows two PMOS transistors  330  and  350  belonging to two different P-cells are disposed next to each other. Parasitic bipolar transistors  410  and  420  form a SCR as shown in  FIG. 4A . Note that like elements in the various figures are labeled with like reference numbers and are therefore not discussed again.  
         [0030]      FIG. 4B  shows the PMOS transistor  330  and the PMOS capacitor  356  are disposed next to each other. The PMOS transistor  330  and the PMOS capacitor  356  belong to two different P-cells. A shallow-trench-isolation (STI)  445  separates the PMOS transistor  330  and the PMOS capacitor  356 . But the STI  445  is quite shallow, a parasitic npn bipolar transistor  420  can still be formed underneath the STI  445 . So a parasitic SCR can also be formed in this structure as shown in  FIG. 4B .  
         [0031]      FIG. 4C  shows the NMOS transistor  332  and the PMOS capacitor  356  are disposed next to each other. Parasitic bipolar transistors  410  and  420  again form a SCR.  
         [0032]      FIG. 4D  is a schematic diagram illustrating an equivalent circuit to the parasitic SCRs shown in  FIG. 4A ˜ 4 C. Referring to  FIG. 4A ˜ 4 D, the bipolar transistor  410  is formed by P+—Nwell—Psubstrate. The bipolar transistor  420  is formed by Nwell—Psubstrate—N+ (through Nwell). During a latch-up test, a node V 15  and a node V 16  are coupled to the power Vdd and Vcc, respectively. The unexpected impulse on the power Vdd may turn the parasitic SCR  460  into latch-up. Then Nwell resistors  430  and  440  and a Psubstrate resistor  450  determine how well the parasitic SCR  460  is immune to latch-up. In general, decreasing the Nwell resistor  430  makes the bipolar transistors  410  harder to turn on, and decreasing the Psubstrate resistor  450  makes the bipolar transistor  420  harder to turn on. On the other hand, increasing the Nwell resistor  440  limits the current flowing through the SCR structure. So all these resistance modifications can boost latch-up immunity for the parasitic SRC  460 . Based on this understanding, the present invention proposes following embodiments to improve the latch-up immunity between two adjacent P-cells.  
         [0033]      FIG. 5  illustrates a P+ guard ring  510  is disposed between two adjacent P-cells  330  and  350  according to one embodiment of the present invention. The P+ guard ring reduces the resistance value of the Psubstrate resistor  450  shown in  FIG. 4C . As a layout rule, the minimum distance between an Nwell pick-up (N+) and nearest P+ in the PMOS device not in the same Nwell (a distance D as shown in  FIG. 5 ) is about 10 um.  
         [0034]      FIG. 6  illustrates a Nwell pick-up (N+)  620  for a PMOS capacitor  610  is moved away from the edge of the Nwell  600  to increase the resistance of the Nwell resistor  630 . As a layout rule, the minimum distance between the N+  620  and the nearest P+ in the PMOS device not in the same Nwell  600  (a distance D as shown in  FIG. 6 ) is about 15 um. The Nwell resistor  630  is equivalent to the Nwell resistor  440  shown in  FIG. 4C .  
         [0035]      FIG. 7  illustrates a deep N+ implant  710  is added beneath the Nwell pick-up (N+)  720  of a P-cell according to yet another embodiment of the present invention. A deep implant is ions implanted with high energy, so that they can penetrate deeper into a semiconductor substrate. The deep N+ implant  710  is to reduce the parasitic resistance of the Nwell  700 , which is equivalent to the Nwell resistor  430  shown in  FIG. 4C .  
         [0036]      FIG. 8  illustrates a deep P+ implant  840  added beneath a STI  445  between two adjacent Nwells  810  and  820  according to yet another embodiment of the present invention. Nwell  810  contains a PMOS transistor  815  and Nwell  820  contains a PMOS transistor  825 . Nwells  810  and  820  are next to each other, but are separated by a region of Psubstrate  830 . The deep P+ implant  840  is also to reduce the resistance value of the Psubstrate resistor  450  shown in  FIG. 4C . On the other hand, P+ implant  840  will make the npn (Q 2 ) bipolar transistor degrade because the high-concentration of the base of Q 2  will induce a lower β-Gain.  
         [0037]     The structures for reducing resistance of the Psubstrate resistor  450  and the resistance of the Nwell resistor  430 , as well as increasing the resistance of the Nwell resistor  440  as shown in  FIGS. 5 through 8  are effective ways to improve latch-up immunities between two adjacent P-cells. Even though these embodiments shows only structures for preventing latch-up between two adjacent P-cells, one who has skills in the art would be able to apply the structures according to the present invention to adjacent N-cells and P-cells, particularly to cell forms part of the ESD circuit.  
         [0038]     The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.  
         [0039]     Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.