Abstract:
In a bulk silicon process, an insulating layer is placed under the portion of the source and drain used for contacts, thereby reducing junction capacitance. The processing involves a smaller than usual transistor area that is not large enough to hold the contacts, which are placed in an aperture cut into the shallow trench isolation.

Description:
FIELD OF THE INVENTION 
     The field of the invention is integrated circuit processing, in particular low-capacitance high speed circuits. 
     BACKGROUND OF THE INVENTION 
     It is well known in the field that junction capacitance between sources and drains (S/D) and the substrate is an important limiting factor in circuit performance. In addition, S/D to substrate leakage results in useless power consumption. Furthermore, contacts to SID diffusions may suffer form reliability concerns if the etch of the contacts places the conductive material of the contact in close proximity to the bottom junction edge through overetch or misalignment. 
     Silicon on insulator technology has less junction capacitance than bulk technology because the buried insulator reduces the capacitance, but is more expensive. 
     It is desirable to develop a low-capacitance transistor structure with low SID leakage for bulk silicon integrated circuits that is economical to manufacture. 
     SUMMARY OF THE INVENTION 
     A feature of the invention is the formation of conductive contact pads over a portion of the STI to reduce the area, reduce capacitance and leakage between the source/drain and the silicon substrate. 
     Another feature of the invention is a reduced size of the transistor area within the shallow trench isolation (STI) that is less than would have been required to provide space for contacts to the rest of the circuit if these contacts were fully within the active region. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows in cross section a completed transistor constructed according to the invention. 
     FIG. 2A shows a top view of a prior art transistor area. 
     FIG. 2B shows a top view of a transistor area according to the invention. 
     FIGS. 3-5 show in cross section various steps in practicing the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 2A shows a top view of a prior art transistor area after the step of forming the shallow trench isolation  210 ′ (STI), in which area  220 ′ which will hold the transistor gate (centered on axis  202 ), source and drain, is defined by trench  210 ′, illustratively formed in a conventional etching process, filled with oxide and planarized in a chemical-mechanical polishing step (CMP). FIG. 2B shows a corresponding view of area  220  according to the invention bounded by STI  210 . Note that the length.  204  along the gate is the same but that area  220  is much smaller than area  220 ′ in the prior art. As will be described later, the area for the sources and drains is reduced below what is required for contacts to fit. The phrase “reduced source and drain areas” will be used in the claims to mean that the source and drain in the single-crystal substrate are too small to receive contacts in the ground rules in use in that particular process. Arrow  206  denotes the width of the gate to be formed and arrow  205  denotes the width of the gate sidewalls plus a small margin for manufacturing tolerance. Illustratively, in a 0.18 μm ground rule CMOS process, gate width  206  is 0.18 μm and width  205  is 0.49 μm. Contacts illustratively require a contact area of 0.46 μm×0.46 μm including manufacturing tolerance, so total active area width  205 ′ would be 1.1 μm, compared to about 1 μm in the contact pads. 
     Referring now to FIG. 3, there is shown in cross section the portion of the circuit that will hold an illustrative transistor. Substrate  10  has been prepared by forming a conventional pad oxide (SiO 2 )  22  and pad etch stop layer  20 , illustratively nitride (Si 3 N 4 ). STI member  110  has been etched in a conventional process using C 4 F 8  chemistry chemistry selective to nitride to form recess  26  having a contact pad depth denoted by arrow  208 . Resist  60  has been patterned with a noncritical contact etch aperture having a width denoted by arrow  207 . The contact recess apertures  26  define contact portions of the STI member  110  that will contain contact pads for interconnects to make contact with the source and drain. If the ground rules would be violated by placing contacts on the STI, then appropriate corrections will be made, such as increasing the width of the STI or spacing adjacent elements further away. The contact pad depth of aperture  26  is such that the vertical contact surface  24  that will be the electrical contact between the source/drain and the contact pads is sufficiently large. Illustratively the depth of the recess is 0.2 μm and the vertical contact surface is 0.08 μm high. 
     Referring now to FIG. 4, there is shown the same area after the deposition of conductive material  70  and CMP using the pad nitride  20  and STI  110  as a polish stop. Illustratively, the conductive material is polycrystalline silicon or amorphous silicon. 
     Next, as shown in FIG. 5, pad nitride  20  is stripped, wells are formed, pad oxide  22  is stripped, gate oxide  122  is grown, gate stack  120  is formed and patterned, the low dose implant is performed in the source/drain areas  122 , gate sidewalls  126  are formed, the source/drain and contact pads are implanted, and an activation anneal is performed. The circuit is completed by forming conventional interconnection members and interlayer dielectrics, denoted schematically by a box labeled  300 . 
     FIG. 1 shows the final structure, in which contact pads  70  bracket the transistor, comprising gate  120  and gate oxide  122 , with sidewalls  126  and gate silicide  132 . Silicide  132  is also formed on top of contact pads  70 . Beneath the gate, source/drain  112  is implanted at the same time as the contact pads. As can be seen, the portion of the S/D members extending outwardly past the sidewalls is only a manufacturing tolerance and not enough to hold a contact. S/D members of this size will be referred to in the claims as “reduced S/D members”. A conventional lower dose source/drain extension has been formed. Contact interconnect members  150  and  152  are shown. Contact  152  illustrates an advantageous feature of the invention—if the contact is misaligned so that it partly lands on the STI, no harm is done. The contact etch will merely penetrate into the STI, with additional contact area being formed on the vertical wall of the contact pad. Note that contact pad members  70  can be extended over an STI member to form a local interconnect between the diffusions on either side of that STI member. 
     While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced in various versions within the spirit and scope of the following claims. By way of example, the substrate may be silicon or silicon-germanium; the gate dielectric may be thermal oxide or a high-k material such as N 2 O 3  or silicon nitride; the planarizing step may be performed by etching instead of CMP; the conductive material may be polycrystalline silicon, amorphous silicon, SiGe, etc. The substrate is not necessarily bulk silicon. The invention may be performed in SiGe, or in an SOI substrate if the thickness of the silicon device layer is thick enough to give rise to significant capacitance, or if the thickness of the insulating layer is thin enough to give rise to significant capacitance.