Abstract:
A broadband power amplifier module for high bit-rate SONET/SDH transmission channels, such as OC-192 and OC-768 applications. The power amplifier module, or also frequently referred to as modulator driver module, comprises amplifiers connected in series to amplify an input signal. A bias tee circuit is incorporated into the power amplifier module by connecting a conical shape inductor between the output stage of the amplifiers and the supply voltage and connecting a pair of blocking capacitors also at the output stage of the amplifiers. The conical shape inductor is adapted to provide high impedance over the entire bandwidth. The capacitors are adapted to provide high self-resonant frequency that is approaching or exceeding the bandwidth frequency. A power detection circuit can also be incorporated into the power amplifier module at the output stage of the amplifiers. The power detection circuit has a voltage divider circuit connected between the output stage and a ground supply. The divider circuit taps off a portion of the energy from the output stage to be measured by a detection diode. A ¼-wave radial matching stub is connected to the detection diode to filter RF energy. Another ¼-wave matching stub is connected to the divider circuit to provide grounding. Capacitors are also connected to the output of the detection diode to filter noise in the detector output voltage over a entire frequency bandwidth.

Description:
FIELD OF THE INVENTION 
     The present invention relates to power amplification devices for optical and electronic communications network, and more specifically to super-wideband power amplifier and modulator driver modules for high bit-rate SONET/SDH transmission channels. 
     BACKGROUND OF THE INVENTION 
     Recently, the world has witnessed a phenomenal growth in the number of Internet users, applications and devices and in the amount of data traffic especially that of medium-rich content—all demanding higher speed communications and connectivity over the Internet. To accommodate this demand, network carriers have begun to provide fiber optical channels to achieve ultra high speed communications. 
     FIG. 1 is a simplified block diagram showing the physical media dependent and PHY layers of an optical network interface. The optical signals sent along the fiber optical channels, e.g. at OC-192 rate, are detected and received by receiver that includes the detector  10  and the trans-impedance amplifier  11 . After an optical signal is converted, which is then amplified to an electrical signal in the receiver, the clock signal and data are recovered by a clock and data recovery unit  12 . The recovered serial data signal is demultiplexed by the DEMUX  13  down to a lower-speed parallel data stream which is then forwarded to a framing and protocol handling unit  14 , for network processing. 
     On the transmitter&#39;s side, parallel data generated from network processing are multiplexed up to higher speed serial data by MUX  18 , which also multiplies the data clock speed to the serial data rate. The serial data signals are then amplified by the modulator driver  17  and the power amplifier  16  to a level sufficient to drive the optical modulator  15 . The required level is typically 7 to 8 volts peak to peak to drive a LiNbO 3  modulator. The modulator  15  then modulates a continuous-wave (CW) laser beam into on- or off-intervals each of which representing a digital  1  or  0  respectively. To improve output voltage swings for RF signals, the output of power amplifier  16  is typically connected to a bias tee circuit. The reason for using the bias tee is as follows: For a single chip implementation of the power amplifier  16 , its last stage consumes most of the current. In order to isolate this stage from the rest of the amplifier, a resistive network with shunting capacitors is normally used on chip to supply its power. The drawback of this approach is that due to the large current draw of the last stage, the resistive network causes a significant voltage drop, which in turn limits the peak-to-peak swing of its output. A bias tee then is used to provide the power supply directly to the last stage. A bias tee circuit consists of only passive components. Its function is to provide a DC block between its input and output and a DC bias voltage to its input node. The method of providing the DC voltage to its input node has to be such that it does not affect the RF signal going from the input to the output and that no appreciable DC voltage drop occurs between the voltage source and the input of the bias tee under high current draw conditions. 
     Also, in order to monitor the level of voltage swing applied to the modulator  15 , a power detector, which detects power levels for a wide band of RF frequencies, is typically implemented with the power amplifier  16 . 
     FIG. 2 is a simplified circuit diagram of a conventional bias tee for RF applications. For application in optical communications, the data can have a long string of “0s” or “1s” or alternate single 0 and 1. Therefore its frequency can be as low as tens of KHz or as high as tens of GHz, e.g. from 30 KHz to 15 GHz for OC-192 and from 30 KHz to 50 GHz for OC-768. Thus wide band bias tees have to be used. To achieve wideband performance, a conventionally designed bias tee may need multiple inductors in series and multiple capacitors in parallel in order to cover the required wide frequency range. For example, one inductor L 1  for 30 kHz to a few MHz, one L 2  for a few MHz to 1 GHz and a third one L 3  for 1 GHz to 15 GHz. Also, 3 capacitors, ranges from 0.1 uF to 1 pF, may be needed to cover the same bandwidth with the smaller one covering the higher frequency range. As can be appreciated by those skilled in the art, because of the use of multiple discrete components, a bias tee package for ultra wide bandwidth applications will end up with a physical dimension in excess of 1.5″×1.5″. This is quite bulky and prone to RF loss due to inherent parasitic capacitances associated with the large size of these components. Large size is especially undesirable for use in optical transponders as the entire transponder size is only around 3″×5″ or less. 
     FIG. 3 is a simplified circuit diagram of a conventional power detector for RF applications. Power detectors generally need to be in hermetically sealed packaging, with external RF feedthroughs at input and output, as well as an external coupler to couple RF energy. All these connected together end up with a package that tends to be quite bulky and costly. Most commercial power detectors also have limited bandwidth, insufficient for application in optical or electronic communications. Prior attempts to integrate the bias tee and power detector circuits into MICs such as power amplifiers or modulator drivers for ultra-wide bandwidth applications have not been entirely successful, largely due to the physical and performance limitations of the discrete components such as inductors and capacitors. 
     Therefore, for size and cost reduction there is a need to incorporate the bias tee into an MMIC package such as a power amplifier module in order to reduce overall size, and cost without compromising on performance. 
     There is also a need to incorporate the power detector into an MMIC package such as a power amplifier module for the same reason. 
     There is further a need to incorporate both the bias tee and power detector circuits into the same MMIC package such as a power amplifier module. 
     SUMMARY OF THE INVENTION 
     A broadband power amplifier module for high bit-rate SONET/SDH transmission channels, such as OC-192 and OC-768 applications, is disclosed. The power amplifier module, or also frequently referred to as modulator driver module, comprises first and second amplifiers connected in series to amplify an input signal. A bias tee circuit is incorporated into the power amplifier module by connecting a conical shape inductor between the output stage of the amplifiers and the supply voltage and connecting a pair of blocking capacitors also at the output stage of the amplifiers. The conical shape inductor is adapted to provide high impedance over the entire bandwidth. The capacitors are adapted to provide high self-resonant frequency that is approaching or exceeding the bandwidth frequency. 
     Additionally, a power detection circuit can also be incorporated into the power amplifier module at the output stage of the amplifiers. The power detection circuit has a voltage divider circuit connected between the output stage and a ground supply. The divider circuit taps off a portion of the energy from the output stage to be measured by a detection diode. A ¼-wave radial matching stub is connected to the detection diode to filter RF energy. Another ¼-wave matching stub is connected to the divider circuit to provide grounding. Capacitors are also connected to the output of the detection diode to filter noise in the detector output voltage over a entire frequency bandwidth. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an exemplary block diagram representing a PHY layer of the network interface topology. 
     FIG. 2 is an exemplary schematics diagram of a conventional bias tee circuit. 
     FIG. 3 is an exemplary schematics diagram of a conventional power detector circuit. 
     FIG. 4 is an exemplary block diagram representing a power amplifier module in accordance with one embodiment of the present invention. 
     FIG. 5 is an exemplary schematics diagram of a power amplifier module for high speed optical modulators in accordance with the present invention. 
     FIG. 6 is an exemplary simplified diagram showing an exemplary assembly packaging of a power amplifier in accordance with the present invention. 
     FIG. 7 is an exemplary graph showing small signal gain of a power amplifier module in accordance within the present invention from 30 KHz to 12.5 GHz. 
     FIG. 8 is an exemplary graph showing small signal gain of a power amplifier module in accordance with the present invention from 1 GHz to 15 GHz. 
     FIG. 9 is an exemplary graph showing output power level of a power amplifier module in accordance with the present invention from 1 GHz to 15 GHz. 
     FIG. 10 is an exemplary graph showing the group delay of a power amplifier module in accordance with the present invention over a frequency range from 130 MHz to 15 GHz. 
     FIG. 11 is an exemplary graph showing small signal gain vs. AGC voltage of a power amplifier module in accordance with the present invention over a frequency range from 130 MHz to 15 GHz. 
     FIG. 12 is an exemplary graph showing detector voltage vs. output power of a power amplifier module in accordance with the present invention at 5 GHz and at 7 GHz. 
     FIG. 13 is an exemplary eye diagram of a power amplifier module in accordance with one embodiment of the present invention. 
     FIG. 14 is an exemplary assembly packaging of a power amplifier in accordance one embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention provides a power amplifier module with a bias tee for ultra-wide bandwidth applications. The power amplifier module may further incorporate a power detector circuit for ultra-wide bandwidth application. In the following detailed description, numerous specific details are set forth to provide a full understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and techniques have not been shown in detail so as to avoid unnecessarily obscuring the present invention. It should also be appreciated by those skilled in the art of optical communications that the terms “power amplifier module” and “modulator driver module” are used interchangeably in connection with amplifying signals to drive an optical modulator. In the following description, a reference to “power amplifier module” should therefore be understood as reference to “modulator driver module” by those skilled in the art. Further, although the description makes reference to embodiments as applied to optical carrier (“OC”) applications, it should be apparent to those skilled in the art that the invention can also be applicable to high bit-rate electronic communication applications, where design specifications such as small signal gain, group delay, output voltage swings and ripples are taken into consideration. 
     Reference is made to FIG. 4, where an exemplary simplified functional block diagram for an ultra-wide bandwidth (30 KHz-15 GHz for OC-192, or 30 KHz-50 GHz for OC-768) power amplifier module in accordance with the present invention is shown. Input signal RF In  405  is applied to first stage amplifier  410  and second stage amplifier  415  through blocking capacitors  407 ,  412 , respectively. Output signal RF Out  418  is led from second stage amplifier  415  through blocking capacitor  417 . Gate bias voltages VG 1 A, VG 1 B are applied first stage amplifier  420  and second stage amplifier  425  through gate bias connections  420  and  425 , respectively. External AGC input control voltage VG 2   413  is applied to both first stage amplifier and second stage amplifier. Power Detection circuit  430  is connected to detect output level of output signal RF Out  418  throughout the desired range of different frequencies. The bias tee circuit consists of inductor  440  and capacitor  417 . It connects its inductor  440  to the output of second stage amplifier  415 . This provides a direct DC path between the power supply Vdd and the last stage of the amplifier  415 . The direct connection enables the output of amplifier  415  to swing fully in voltage to an extent which is sufficient to drive an optical modulator. The inductor  440  is preferably constructed with a large enough impedance over the wide bandwidth as required for optical and electronic communication so that signals do not leak through to the power supply Vdd. 
     Currently, the packaging for the power amplifier module in accordance with the present invention uses SMA connectors for RF In and RF Out. It utilizes solder tab-type connector for the ground DC GND return. It also utilizes coaxial feed-through connectors, which filter out noise in the cavity, for gate biases, detected RF voltage, AGC input control voltage and power supply Vdd. The power amplifier module has a dimension of 1.25″(L)×0.7″ (W)×0.5″ (D) in accordance with one embodiment of the present invention. Of course, those skilled in the art can determine the most suitable connector types for their packaging and connectors bases on their operating environment. 
     Reference is now to FIG. 5, where an exemplary schematics diagram of the power amplifier module in accordance with the present invention is shown. RF input  505  is applied to first stage amplifier  510  and second stage amplifier  515  through DC blocking capacitors  507  and  512 , respectively. The output of second stage amplifier  515  is connected to bias tee circuit  540  to generate RF output  518 , which may also be applied to power detector circuit  530 . Currently, amplifiers  510 ,  512  are medium power wideband amplifiers from Triquint Semiconductor (http://www.triquint.com) at 2300 N.E. Brookwood Parkway, Hillsboro, Oreg. 97124, under the part number of TGA1328-EPU. Of course, those skilled in the art may find other wideband amplifiers suitable for their applications based on the teaching of the present invention. 
     The amplifiers  510 ,  515  are powered by Vdd through DC bypassing circuit  527 . Bias voltages are applied to amplifiers  510  and  515  through DC bypassing circuits  520  and  525 , respectively. Of course, if more gain is desired, more amplifiers can be inserted into the module package. As shown in FIG. 5, DC bypassing circuit  520  is formed by capacitors C 5 , C 6 , C 7  in parallel. Similarly, DC bypassing circuit  525  is formed by capacitors C 13 , C 14 , C 15  in parallel and DC bypassing circuit  527  is formed by capacitors C 2 , C 3 , C 4 , C 10 , C 11 , C 12 , C 16  in parallel. The bypassing capacitor circuits serve to filter out noise in the DC power supply Vdd. They also serve to short-circuit the RF signal on the power line to ground so different amplifier stages or blocks do not couple to each other undesirably to cause oscillations. Capacitors of different values serve to short-circuit different frequency bands. 
     Referring to FIG. 5, bias tee circuit  540  is formed by connecting conical inductor  541  between the output of second stage amplifier  515  and Vdd, and by applying the output from amplifier  515  to capacitors  517 . Capacitors  517  provide DC blocking so that only RF energy is passed through to the output  518 . Currently, to achieve high self-resonant frequency without creating dips in the frequency response, capacitors  517  are two chip capacitors connected in parallel to allow passing of signals in both the low frequency range (KHz-a few MHz) and the high frequency range (a few MHz-15 GHz). Such chip capacitors, and DC blocking capacitors  507 ,  512 , are ultra broadband DC blocking capacitors available from Dielectric Labs (http://www.dilabs.com) as individual units (Part No.: C08BLBB1X5UX), or as combined units known as Opti-Caps™. Dips in the frequency response occur when capacitors have gaps in their coverage or low self-resonant frequency such that the gain reduces at one or more region within the desired bandwidth. Preferably, the self-resonant frequency of the one that covers the high frequency should be much higher than the highest frequency of the desired abandwidth to avoid dips within the operating frequency band. 
     Reference is to bias tee circuit  540  of FIG.  5 . For a bias tee circuit in an ultra wide bandwidth applications, the inductor should preferably provide high impedance at low frequency as well as at high frequency over the desired bandwidth. The difficulty in achieving high impedance over a wide bandwidth lies in the physical realization of an inductor. In order to achieve high impedance (200Ω) at the low frequency limit (say 50 KHz) we need 0.64 mH. This would be a physically large inductor with a ferrite core and a low self-resonance frequency. Consequently it will be capacitive at high GHz frequencies and provide low impedance. Thus for wideband coverage one needs to use a number of inductors in series, starting from the amplifier output node with a small inductor with small value (say 1 nH), high self resonance frequency, or low parasitic capacitance. Then one gradually increases the inductance of each of successive inductors until 0.64 mH is reached for the lowest frequency. In this approach one also has to be careful that no gaps of coverage is created by incrementing the inductor values too much in going from one inductor to the next. 
     A more preferable approach is to replace the series of inductors of successively increasing values by a single conical inductor, preferably mounted on a ceramic stand. In a conical inductor, the tip portion with its small dimension corresponds to an inductor with relatively low inductance, low parasitic capacitance, and high self-resonance frequency. Since the impedance of an inductor is proportional to the frequency, its low inductance still provides high impedance for the high end of the frequency range. As we go away from the tip, successive sections provide the required impedance for successively lower frequencies. In the current embodiment, inductor  541  is such a broadband conical inductor, which has a bandwidth extending from 10 MHz to 40 GHz and which is available as Model No. C011, from Piconics Inc, at 26 Cummings Road, Tyngsboro Mass. 01879. Without an inductor with such characteristics, multiple discrete inductors would have been needed to cover the ultra wide bandwidth, thus greatly increasing the physical dimension and potential RF loss. 
     For improved low-frequency coverage, e.g. at 20 KHz or 50 KHz, an inductor (e.g. a toroidal or a solenoidal inductor) with an exemplary value of 1 mH may be inserted between the conical inductor  541  and power supply Vdd. Those skilled in the art can, of course, determine the appropriate value for the inductor in their application to achieve the desired low frequency coverage. For example, a 1 mH toroidal inductor may be used in the module package, since it is generally considered more efficient due to its size advantage over a solenoidal inductor. 
     Reference is now to power detector circuit  530  of FIG.  5 . Power detector  530  may be incorporated into the power amplifier module for detection of RF energy at all frequencies. This would result in size and cost reduction when compared with using a separate module for power detection. As shown in FIG. 5, voltage divider circuit  551  is used to tap off the RF energy to be detected to prevent damage to power detector diode  560 . Currently, by a ratio of R 1 :R 2 =250:50, RF power being applied to detector diode  560  is limited to about 2 to 3% of the total RF power. It should be noted that while a resistor voltage divider circuit  551  is illustrated to achieve broader bandwidth capability for both input and output, those skilled in the art may apply other types of voltage dividers for their desired bandwidth. Also, instead of connecting between output node  518  and ground, voltage divider circuit  551  may be connected to a second voltage supply source, in place of ground, to bias detection diode  560 . 
     Currently, grounding of voltage divider circuit  551  is achieved through a via hole to the backside ground of the substrate. However, due to the inductance associated with the via hole, this grounding may be compromised at high end of the frequency band. To achieve better flatness of frequency response, a ¼-wave stub  553  is connected at the end of divider circuit  551  for better grounding at the high frequency end in addition to the via hole. The RF energy that is tapped off from the voltage divider circuit  551  is applied to detector diode  560  so that the RF energy is converted into a DC voltages which is indicative of the RF power level at the output  518 . A ¼-wave radial stub  555  serves as a broadband low-pass filtering for detector diode output. This would suppress all the higher frequency components. 
     Capacitors C 18 , C 19 , C 20 , C 21  provide proper low-pass filtering for lower frequency bands and minimize amplitude variation of the diode output over frequency. As such, a fairly constant DC voltage over the bandwidth can be maintained. It should be noted that different values, e.g. 0.1 uF, 1 pF, 10 pF, 100 pF of capacitors are used to cover different frequencies, since the larger the capacitance, the better it filters at lower frequency range. For example, stub  555  is for 10 to 15 GHz, 1 pF is for 2-10 GHz, 10 pF is for 0.5-2 GHz, 100 pF is for a few hundred MHz and below, 0.1 uF is for 1 MHz or below. For even higher frequency range of 40 GHz, more stubs can be added. 
     Reference is made to FIG. 6, where an exemplary assembly diagram of a power amplifier module is shown. RF Input  605  is applied to first stage amplifier  610  through a 50-ohm transmission line and DC blocking capacitors  607 . Second stage amplifier  615  is connected to first stage amplifier  610  through another 50-ohm transmission line and DC blocking capacitors  612 . RF Out is led through 50-ohm transmission line  618  from second stage amplifier  615 . It is also tapped off by resistor divider  651  with ¼-wave grounding stub  653  and detected by detector diode  660  with ¼-wave radial stub  655 . The detected output can be measured at connector  635 . The low-pass filtering capacitors for the power detector are implemented with capacitors C 18 /C 19 /C 20 /C 21 . It should, however, be appreciated by those skilled in the art that FIG. 6 provides merely one exemplary embodiment of the present invention and that the present invention may be practiced with or without some of these specific details. 
     Conical inductor  641  is connected between output of second amplifier  615  and Vdd. Bypass capacitors  620 ,  625 ,  627  are represented by capacitors C 5 /C 6 /C 7 , C 13 /C 14 /C 15 , C 2 /C 3 /C 4 /C 10 /C 11 /C 12 /C 16 , respectively. Blocking capacitors Cl 7 A/C 17 B are connected between the resistor divider network  651  and the output of amplifier  615 . A packaged power amplifier module such as the one shown in FIG. 6 may weigh about 2 ounces according to one embodiment of the present invention. 
     While the assembly diagram of FIG. 6 illustrates one embodiment of a power amplifier module with bias tee and power detector incorporated, it should be appreciated by those skilled in the art that other assemblies can be implemented based on the teaching of the present invention. For example, the bias tee may be incorporated in a power amplifier and the power detector may be applied to a modulator driver module, or other MMIC where it would be beneficial to be able to ensure its functionality. 
     FIG. 7 is an exemplary graph showing small signal gain of a power amplifier module in accordance within the present invention from 30 KHz to 12.5 GHz. 
     FIG. 8 is an exemplary graph showing small signal gain of a power amplifier module in accordance with the present invention from 1 GHz to 15 GHz. 
     FIG. 9 is an exemplary graph showing output power level of a power amplifier module in accordance with the present invention from 1 GHz to 15 GHz. 
     FIG. 10 is an exemplary graph showing the group delay of a power amplifier module in accordance with the present invention over a frequency range from 130 MHz to 15 GHz. 
     FIG. 11 is an exemplary graph showing small signal gain vs. AGC voltage of a power amplifier module in accordance with the present invention over a frequency range from 130 MHz to 15 GHz. 
     FIG. 12 is an exemplary graph showing detector voltage vs. output power at 5 GHz and at 7 GHz. 
     FIG. 13 is an exemplary eye diagram of a power amplifier module in accordance with one embodiment of the present invention. In this example, an input signal of about 250 mV peak-to-peak was provided to the node  505  in FIG.  5 . The input signal was a pseudo random bit data stream that was 2 31 −1 PRBS. The data rate was 12.5 Gbps. The power supply was at 9 V peak-to-peak, and the current was 250 mA. The overall power dissipation was about 2.25 Watt. The waveform observed at the output node  518  of FIG. 5 is shown in FIG.  13 . The output waveform is about 5 V peak-to-peak. The test setup used to generate the waveform shown in FIG. 13 did not include the inductor  541  in FIG.  5 . If the inductor  541  is included, the output amplitude is expected to be even larger (e.g., 7 V peak-to-peak). 
     FIG. 14 is an exemplary assembly packaging of a power amplifier in accordance with one embodiment of the present invention. The dimensions shown are in inches. 
     While the present invention has been particularly described with reference to the various figures and embodiments, it should be understood that these are for illustration only and should not be taken as limiting the scope of the invention. There may be many other ways to implement the invention. Many changes and modifications may be made to the invention, by one having ordinary skill in the art, without departing from the spirit and scope of the invention.