Abstract:
A CMOS translator which includes an amplifier having an input node and an output node; a first clamp for providing a clamped feedback signal from the output node to the input node of the amplifier; and a second clamp for providing a clamped feedforward signal from the input node to the output of the amplifier. ECL signals are translated up to CMOS voltage levels with high speed, low power consumption via a circuit with requires minimal die area. The unique clamping arrangement provides a self-biasing feature which affords a large error margin.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention: 
     The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits. More specifically, the present invention relates to translators for CMOS circuits. 
     While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility. 
     2. Description of the Related Art: 
     Complementary metal-oxide-semiconductor (CMOS) technology is used in many current digital applications because of the high switching speeds, low power consumption and small die size requirements associated therewith. Unfortunately, it is often necessary to interface CMOS circuits with circuits fabricated in other technologies. These other technologies include TTL (transistor-transistor logic) and ECL (emitter coupled logic). This may be somewhat problematic for many reasons, not the least of which is the fact that each logic family may operate at unique voltage levels. Such is the case with respect to the ECL family. ECL circuits typically operate with a 600 to 800 millivolt potential differential between logic levels. CMOS circuits generally operate at voltage levels between 0 to 5 volts (0 and 5000 millivolts). Thus, when an ECL signal is input to a CMOS circuit, an interface must be used to amplify the input voltage up to CMOS voltage levels. ECL to CMOS translators serve this purpose. 
     An ECL to CMOS translator amplifies digital ECL signals to CMOS levels. Unfortunately, prior art ECL/CMOS translators are too slow, consume too much power and are too large for many applications. Thus, there is an ongoing need in the art for faster, smaller ECL/CMOS translators which consume less power than conventional designs. 
     SUMMARY OF THE INVENTION 
     The need in the art is addressed by the CMOS translator of the present invention which includes an inverter functioning as an amplifier having an input node and an output node; and a bidirectional clamp for providing a feedback signal from the output node to the input node of the amplifier. 
     The invention is only part of an ECL to CMOS translator. ECL signals are translated up to CMOS voltage levels with high speed, low power consumption via a circuit with requires minimal die area. The unique clamping arrangement provides a self-biasing feature which affords a large error margin. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1(a) is an illustrative schematic representation of an unloaded CMOS inverter. 
     FIG. 1(b) is a graph of the voltage characteristics of the illustrative unloaded CMOS inverter of FIG. 1(a). 
     FIG. 2(a) is an illustrative schematic representation of a resistively loaded CMOS inverter. 
     FIG. 2(b) is a graph of the voltage characteristics of the resistively loaded CMOS inverter of FIG. 2(a). 
     FIG. 3(a) is an illustrative schematic representation of a resistively biased CMOS inverter driven by a non-ideal voltage source. 
     FIG. 3(b) is a graph of the voltage characteristics of the resistively biased CMOS inverter of FIG. 3(a). 
     FIG. 4(a) is a schematic diagram showing an illustrative implementation of the CMOS translator of the present invention driven by a non-ideal voltage source. 
     FIG. 4(b) is a graph of the voltage characteristics of the CMOS translator of the present invention. 
    
    
     DESCRIPTION OF THE INVENTION 
     Illustrative embodiments and exemplary applications will now be described with reference to the accompanying drawings. 
     The advantageous design and operation of the CMOS translator of the present invention is best described with reference to the illustrative schematic representation of an unloaded CMOS inverter 10 of FIG. 1(a). As is well known in the art, the CMOS inverter 10 includes a p-channel metal-oxide-semiconductor field effect transistor (MOSFET) 12 and an n-channel MOSFET 14. The gates of the p-channel and the n-channel transistors 12 and 14 are tied to a common input node A. Node A is attached to a source of input voltage V in . The source of the p-channel transistor 12 is connected to a source of supply voltage V cc . The drain of the p-channel transistor 12 and the drain of the n-channel transistor 14 are tied to a common output node, node B. The source of the n-channel transistor 14 is connected to ground. The output voltage V out  is measured with respect to node ground. 
     In operation, when the voltage of the signal at the input node V in  is high, the p-channel transistor 12 is off, the n-channel transistor 14 is on and the output voltage V out  is low. When V in  is low, the p-channel transistor 12 is on, the n-channel transistor 14 is off and V out  is high. Thus, the CMOS pair acts as an inverter. 
     As is known in the art and as illustrated in the graph of the voltage characteristics of a CMOS inverter of FIG. 1(b), CMOS inverters have high gain in the region around the trip point V trip . This recognition is significant with respect to the realization of the translator of the present invention. 
     That is, for the purpose of illustration, one could load the inverter 10 as shown in FIG. 2(a), with a resistor 16 and a voltage source 18 of V trip . As illustrated in FIG. 2(b) at the curve labeled &#34;resistively loaded&#34;, the result is lower gain and reduced output swing. As shown in FIG. 3(a), if the previous stage can be modeled by a voltage source 20 of V signal  in series with a resistor 22 in the desired operating range, a parallel resistor 24 can create the same effect as the resistor 16 and the voltage source 18. As shown as the curve labeled &#34;biased&#34; in the corresponding graph of the voltage characteristics of FIG. 3(b), this resistive biasing limits both the input and output swings and by providing a narrower input operating range 26 effectively self-biases the stage. Note that the voltage gain which is the slope of the transfer characteristic is also reduced. 
     FIG. 4(a) is a schematic diagram showing an illustrative implementation of the CMOS translator 100 of the present invention. The translator includes the inverter 10 of FIG. 1(a), with a third n-channel MOSFET 120 connected between the output node, node B, and the input node, node A and a fourth n-channel MOSFET 140 connected between the output node, node B, and the input node, node A. The drain and gate of the third n-channel MOSFET 120 are connected to the output node, node B. The source of the third n-channel MOSFET 120 is connected to the input node, node A. Similarly, the drain and gate of the fourth n-channel MOSFET 140 are connected to the input node, node A while the source thereof is connected to the output node, node B. Thus, the third n-channel MOSFET 120 and the fourth n-channel MOSFET 140 provide a feedback path for the inverter 10. The previous stage is modeled by a voltage source 20 and a resistor 22 connected to the input node as in FIG. 3(a). 
     In operation, the inverter 10 acts as an amplifier providing gain for the translator 100. When the output voltage of the inverter 10 exceeds a threshold equal to the conduction threshold of the third n-channel MOSFET 120 relative to the input voltage, the third n-channel MOSFET 120 conducts and clamps the output of the inverter 10. Similarly, when the input voltage of the inverter 10 exceeds a threshold equal to the conduction threshold of the fourth n-channel MOSFET 140 relative to the output voltage, the fourth n-channel MOSFET conducts and clamps the output of the inverter 10. Thus, the third and fourth MOSFETS 120 and 140 provide a bidirectional clamp for clamping a feedback signal from the output node to the input node of the inverter/amplifier 10. 
     As is known to those skilled in the art, the supply voltage and the ratio of the sizes of the p-channel and the n-channel transistors 12 and 14 are chosen to provide a gain and output voltage suitable for a particular application or environment. 
     The curve labeled &#34;clamped&#34; in FIG. 4(b) is a graph of the voltage characteristic of the translator 100 of the present invention. As shown in FIG. 4(b), the use of first and second clamps 120 and 140 in place of the parallel resistor 24 of FIG. 3, provides maximum gain in the operating region, controlled input and output swings and a four transistor self-biasing gain stage with a minimal die size requirement. In particular, the gain is improved relative to the circuit of FIG. 3(a) in the operating region 26 of FIG. 4(b) because the clamps are not engaged in this region. In addition, the clamps hold the input and output voltages close to the trip point. Thus, when it is necessary to trip the next stage, it is not necessary to go al the way from either ground or the power supply to the trip point. This is one factor militating in favor of a short propagation delay. 
     It is noted that while inverters have been used in the art to provide translation from one logic family to another, the transistors in the inverter may be of substantially different sizes. Thus, the rise time may be much slower than the fall time. Hence, the propagation time was long. Previously, two inverters had to be used in many applications to overcome this problem. One to set the input threshold and one to equalize propagation delays, i.e., to compensate for slow rise time or slew rate. The present invention allows the sizes of the p-channel and the n-channel transistors 12 and 14 to be close thereby affording a high slew rate. The self-biasing feature of the translator 100 allows for a considerable margin of error in the design thereof. 
     Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. The translator of the present invention may be viewed as an amplifier or inverter with a bidirectional clamp connected between the input and output terminals thereof. While bidirectional clamps may be known in the art, bidirectional clamps have not been known to bias gain stages. Nonetheless, those having ordinary skill in the art and access to the present teachings will recognize additional modifications applications and embodiments within the scope thereof. For example, one or both of the n-channel clamp transistors in the translator of the present invention may be replaced by p-channel transistors and vice versa without departing from the scope of the present invention. 
     It is therefore intended by the appended claims to cover any and all such applications, modifications and embodiments within the scope of the present invention. 
     Accordingly,