Abstract:
A management frame circuit has a set of inputs coupleable to a management bus for carrying management frames. Upon receiving the management frames from the management bus, the management frame circuit determines whether each of the management frames conforms to a frame template. The management frame circuit then asserts an indication that a management frame is bad, if the management frame is determined to not conform to the frame template. The bad fame indication is later deasserted in response to recognition of a predetermined set of bits on the management bus.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is directed towards the field of communications network management. More particularly, the present invention relates to processing management frames transmitted between a physical layer device and a station management entity. 
     2. Description of the Related Art 
     Communications networks provide for the transfer of information between pieces of data terminal equipment, such as personal computers. One standard for a communications network is the Institute of Electrical and Electronics Engineers (&#34;IEEE&#34;) 802.3u standard, which is set forth in IEEE Standards for Local and Metropolitan Area Networks: Supplement to Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, Media Access Control (MAC) Parameters, Physical Layer, Medium Attachment Units, and Repeater for 100 Mb/s Operation, Type 100BASE-T (Clauses 21-30), The Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, New York, N.Y. 10017-2394, 1995, which is hereby incorporated by reference. 
     A communications network may be required to transfer a great deal of information. Under heavy utilization conditions, a communications network&#39;s performance may be degraded, or the communications network may cease operating. By continually monitoring the operation of a communications network, it may be possible for a network management entity to detect the potential for such degradations and failures. The network management entity can then take actions that will assist in avoiding any degradations or failures. In order to provide a network management entity with the information necessary to manage a communications network, different components in the communications network may record network status information and make it available to the network management entity. 
     FIG. 1 illustrates a repeater set 100, as specified in the IEEE 802.3u standard, including a station management entity 106, which is also identified in the IEEE 802.3u standard. The repeater set 100 provides for the transfer of information between multiple medium connections in an IEEE 802.3u communications network. 
     The repeater set 100 includes a repeater unit 101 and a plurality of transceivers 102. Each transceiver 102 may be coupled to a respective medium 103 that carries information through the network. Each transceiver 102 is coupled to a respective medium 103 via a medium dependent interface (&#34;MDI&#34;) 104 that is specified in the IEEE 802.3u standard. Each medium 103 is also attached to either data terminal equipment (not shown), another repeater set (not shown), or another piece of networking equipment (not shown), such as a bridge or a router. Each transceiver 102 receives and transmits data over its respective MDI 104. 
     Each transceiver 102 is coupled to the repeater unit 101 through a medium independent interface (&#34;MII&#34;) as specified in the IEEE 802.3u standard. The MII includes a set of physical signaling sublayer signals (&#34;PLS&#34;) 105 for connecting the transceiver to the repeater unit 101. The PLS signals 105 provide for transmit data to be passed from the repeater unit 101 to the transceiver 102, receive data to be passed from the transceiver 102 to the repeater unit 101, and for carrier and collision signals to be passed to the repeater unit 101 by the transceiver 102. 
     The MII also includes a management bus (&#34;MB&#34;) 107, which is employed to couple a station management entity 106 to a set of transceivers 102. Each transceiver 102 may internally maintain a set of network status information, including information relating to the operation of the link between the transceiver 102 and its respective medium 103. Each transceiver 102 may also include a control register and other various registers that are programmable and readable by the station management entity 106. 
     The station management entity 106 retrieves such network status information and accesses transceiver registers via the management bus 107. The station management entity 106 thereby provides a means for a network administrator to gather network status information and program the operation of transceivers 102 to avoid future network degradations and failures. 
     The station management entity 106 communicates with each transceiver 102 coupled to the management bus 107 through the use of management frames. However, if a management frame deviates from the frame template specified in the IEEE 802.3u standard, a transceiver 102 may receive erroneous instructions, thereby causing the transceiver 102 to perform an erroneous operation. For example, an improper management frame may cause two transceivers 102 to erroneously believe that they are designated to drive the shared management bus 107. As a result, there may be contention on the management bus 107 and the network administrator may either receive erroneous data or have an instruction executed improperly. 
     SUMMARY OF THE INVENTION 
     The present invention includes a management circuit that can monitor a management bus to determine whether a management frame is in conformance with the required management frame template. Further, the management circuit responds to the detection of a non-conforming bad management frame by signaling a transceiver to not perform operations in response to the bad management frame. The management circuit later signals the transceiver to respond to a conforming good management frame that follows the bad management frame. 
     The management frame signals the transceiver to respond to such a good management frame upon detecting the good management frame&#39;s presence on the management bus. As a result, the present invention avoids the use of an additional dedicated input on either the management circuit or the transceiver to reactivate the transceiver, after operations in response to a bad management frame have been halted. Deactivation of transceiver operations in response to a bad management frame may be accomplished in the present invention by indicating to the transceiver to not drive one or more data lines connected to the management bus. 
     A good management frame following a bad management frame is recognized by its preamble, which may be for example 32 consecutive logic 1&#39;s. No designation of a specific management circuit is required in the preamble or otherwise, should more than one management circuit be coupled to the management bus. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Further details of the present invention are explained with the help of the attached drawings in which: 
     FIG. 1 illustrates a repeater set including a repeater unit, station management entity, and a plurality of transceivers. 
     FIG. 2 illustrates a transceiver, including a plurality of physical layer devices and a station management circuit, in accordance with the present invention. 
     FIG. 3 illustrates a frame template for a management frame conforming to the IEEE 802.3u standard. 
     FIG. 4 illustrates a station management entity coupled to a plurality of transceivers, including a transceiver as shown in FIG. 2. 
     FIG. 5 illustrates a flow diagram of a process of the present invention which may be performed by the station management circuit of FIG. 2. 
     FIG. 6 illustrates more detail of the transceiver of FIG. 2. 
     FIG. 7 illustrates an interface between the MII Interface circuitry and the management frame state machine illustrated in FIG. 6. 
     FIG. 8 illustrates a state diagram for one embodiment of the management frame state machine in FIG. 7. 
    
    
     DETAILED DESCRIPTION 
     FIG. 2 illustrates a transceiver 200 in accordance with the present invention. The transceiver 200 includes physical layer devices 201 1-N  and a station management circuit 202. Each physical layer device 201 1-N  provides a set of PLS signals 205 1-N  for the MII for interfacing to a repeater unit (not shown) or a media access controller (not shown) through a reconciliation layer (not shown). Each physical layer device 201 1-N  also provides an MDI interface 204 1-N  for coupling to a respective medium 203 1-N , such as category 5 unshielded twisted pair cable. Each physical layer device 201 1-N  transfers data between the PLS signals 205 1-N  and the MDI 204 1-N  in accordance with one of the physical layer device operational specifications set forth in the IEEE 802.3u standard. 
     Each physical layer device 201 1-N  and the station management circuit 202 are all coupled to a bus 207. The bus 207 provides a means for each physical layer device 201 1-N  to provide network status information to the station management circuit 202. The bus 207 also provides a means for the station management circuit 202 to provide instructions to each physical layer device 201 1-N , based on the data that is programmed into the station management circuit 202 by a network administrator. 
     The station management circuitry 202 may be coupled to a station management entity 206 via a management bus 210 which includes a management data input/output signal (&#34;MDIO&#34;) 208 and a management data clock signal (&#34;MDC&#34;) 209. The management bus 210 may be shared by a plurality of transceivers. The MDIO 208 is a bidirectional signal that can be driven by either the station management circuit 202 or the station management entity 206. In order to avoid contention on the MDIO 208, only one entity may drive the MDIO 208 at any instance. The remaining entities coupled to the MDIO 208 provide a tri-state output and treat the MDIO 208 as an input. 
     The MDC 209 is only driven by the station management entity. Each entity coupled to the MDIO 208 and MDC 209 signals uses the rising edge of the clock signal on MDC 209 to sample the MDIO 208. MDC 209 and MDIO 208 may be provided by the station management entity 206, so that the MDIO 208 is valid 10 nanoseconds before the rising edge of MDC 209 and 10 nanoseconds after the rising edge of MDC 209. 
     Data is transferred on the MDIO 208 in the form of management frames. FIG. 3 illustrates the frame template for a valid management frame 220 that is transferred over the MDIO 208 in accordance with the IEEE 802.3u standard. The management frame 220 consists of 8 fields. The first field is the preamble field (&#34;PRE&#34;) 221. The preamble field 221 consists of 32 contiguous bits having a logic 1 value. The preamble field 221 indicates that the management frame 220 is beginning to be transmitted onto the MDIO 208. The preamble field may be disabled if all of the station management circuits coupled to the MDIO 208 can recognize the beginning of the management frame 208 without being sent a preamble 221. 
     The second field in the management frame 220 is the start of frame field (&#34;ST&#34;) 222. The start of frame field 222 contains two bits. The first bit transmitted onto the MDIO 208 is a logic 0 value, which is followed by a logic 1 value. Some station management circuits may use the ST field 222 to recognize the start of the management frame 220, instead of using the preamble field 221. 
     The third field in the management frame 220 is the operation code field (&#34;OP&#34;) 223. The operation code field 223 provides a bit pattern, which indicates whether the station management entity 206 wishes to read data from the station management circuit 202 or write data to the station management circuit 202. If a read operation is desired, the first bit transferred onto the MDIO 208 will be a logical 1 value, and the second bit will be a logical 0 value. If a write operation is desired, the first bit transferred onto the MDIO 208 will be a logical 0 value, and the second bit will be a logical 1 value. 
     The fourth field in the management fame 220 is the PHY address field (&#34;PHYAD&#34;) 224. The PHYAD field 224 consists of five bits, which serve as an address for the physical layer device for which the management frame 220 is intended. A logic value of 00000 in the PHYAD field indicates that the management frame 220 is intended for all physical layer devices that are coupled to a station management circuit 202 receiving the MDIO 208. 
     The fifth field in the management frame 220 is the register address field (&#34;REGAD&#34;) 225. The REGAD field 225 consists of five bits, which serve as an address for a data storage location associated with the addressed physical layer device. As stated previously, these data storage locations provide for the storage of network status and other information, as well as providing a means for receiving instructions from a network administrator. 
     The sixth field in the management frame 220 is the turnaround field (&#34;TA&#34;) 226. The TA field 226 is a two bit field that provides for the avoidance of contention on the MDIO 208 during a read operation by the station management entity 206. If the operation called for in the OP field 223 is a read, the station management entity 206 and the station management circuit 202 will both provide a high impedance state to the MDIO 208 in the first bit time of the TA field 226. In the second bit time, the station management circuit 202 that is coupled to an addressed physical layer device 201 will drive a logic 0 value onto the MDIO 208. If the operation called for in the OP field 223 is a write, the station management entity 202 will drive a logic 1 value onto the MDIO 208 in the first bit time of the TA field 226. The station management entity 206 will then drive a logic 0 value onto the MDIO 208 for the second bit time. 
     The seventh field in the management frame is the data field (&#34;DATA&#34;) 227. The data field 227 consists of sixteen bits. If the OP field 223 called for a read operation, the data field 227 is provided to the MDIO 208 by the station management circuit 202 coupled to the addressed physical layer device 201. The data field 227 will contain the contents of a data storage location addressed in the REGAD field 225. If the OP field 223 called for a write operation, the data field 227 is provided to the MDIO 208 by the station management entity 206. The data field 227 will contain a value to be stored in a data storage location associated with the addressed physical layer device. The address of the data storage location will correspond to the address in the REGAD field 225. 
     The eighth field in the management frame 220 is the idle field (&#34;IDLE&#34;) 228. The IDLE field 228 is really a condition that exists on the MDIO 208 when none of the aforementioned fields in the management frame are present on the MDIO 208. In the IDLE condition 228, neither the station management entity 206 nor the station management circuitry 202 drive the MDIO 208. Both the station management entity 206 and the station management circuit 202 provide a high impedance state to the MDIO 208, which is coupled to a pull-up resistor (not shown). Also in the IDLE condition 228, the station management entity 206 does not provide a clock signal having rising and falling edges on MDC 209. Only a single pulse is provided on the MDC 209 immediately following the end of the DATA field 227. 
     FIG. 4 illustrates a repeater set 244 having an MDIO 208 and MDC 209 coupled to a station management entity 206 and a plurality of transceivers 230, 231, and 232, including the transceiver 200 depicted in FIG. 2. Each of these transceivers 200, 230, 231, and 233 has a station management circuit 202, 233, 234, and 235 coupled to both the MDC 209 and MDIO 208. Each station management circuit 202, 233, 234, and 235 is coupled to a respective set of physical layer devices 201 1-N , 236 1-N , 237 1-N , and 238 1-N  within a transceiver through a respective bus 207, 239, 240, 241. 
     Each physical layer device in the sets of physical layer devices 201 1-N  236 1-N , 237 1-N , 238 1-N  is coupled to a repeater unit 245 through a respective set of PLS signals 205 1-N , 247 1-N , 248 1-N , and 249 1-N . Each physical layer device may also be coupled to a respective medium (not shown) via a respective MDI 204 1-N , 255 1-N , 256 1-N , 257 1-N . The number of physical layer devices in each transceiver 200, 230, 231, and 232 may be either one or greater than one. In one embodiment of the present invention, the transceiver 200 includes four physical layer devices 201 1-N . 
     FIG. 5 illustrates a sequence of process steps in accordance with the present invention that the transceiver 200, including the station management circuit 202 and physical layer devices 201 1-N , may execute when processing management frames. In a preamble detection step 301, the station management circuit 202 monitors MDIO 208 to determine whether a preamble field 221 in a management frame 220 is being transmitted. This may be detected by sensing a clock rising edge on MDC 209 with MDIO 208 being a logic 1 value. 
     Next, a preamble validity detection step 302 is commenced. In step 302, the station management circuit 202 determines whether the transmitted preamble is valid. This may be achieved by monitoring the preamble field 221 for a logic 0 value. If a logic 0 value is detected in the preamble field 221, the preamble is invalid. If the preamble is invalid, the incoming management frame 220 is determined to not conform to the IEEE 802.3u management frame template, and a bad management frame step 303 is entered. If the preamble is valid, a receive ST bits step 306 is executed. Step 306 provides for the two bits in the ST field 222 to be received by the transceiver 200. 
     After step 306, a check ST bits step 307 begins. In step 307, the second ST bit is examined. If the second ST bit is a logic 0, the bad management frame step is executed, since a logic 0 in this bit indicates that the incoming management frame 220 does not conform to the IEEE 802.3u management frame template. If the second ST bit is a logic 1, the receive OP field step 308 is executed. In the receive OP field step 308, the transceiver 200 receives the OP field 223 of the incoming management frame 220. 
     After receiving the OP field, a check OP field step 309 is performed. In step 309, a determination is made of whether the two bits in the OP field 223 are the same. If the two bits are the same, the management frame 220 is not in conformance with the required template, and the bad management frame step 303 is executed. Otherwise, a receive PHYAD step 310 is performed. In step 310, the transceiver 200 receives the PHYAD field 224 of the management frame 220. Next, a receive REGAD step 311 is executed, during which the transceiver 200 receives the REGAD field 225 of the management frame 220. 
     After receiving the REGAD field 225, a receive TA field step 312 is executed. Step 312 provides for the transceiver 200 to receive the TA field 226 of the management frame 220. After receiving the TA field 226, a check TA field step 314 is commenced. In step 314, the station management circuit 202 determines whether the OP field 223 indicated a write operation and whether the TA field 226 bits are in conformance with the IEEE 802.3u frame template. If a write operation was indicated and the TA field 226 bits are not a logical 10 value, the bad management frame step 303 is executed, because the management frame 220 is not in conformance with the required frame template. Otherwise, a data operation step 315 is executed. 
     In the data operation step 315, the transceiver 200 performs the operation indicated by the OP field 223 to the register indicated in the REGAD field 225, only if the PHYAD field contains 00000 or the address of one of the physical layer devices 201 1-N  in the transceiver 200. Otherwise, the transceiver 200 waits idly until the sixteen bit times comprising the data field 227 have elapsed. After the data operation step 315 is completed, the preamble detection step 301 is re-executed. 
     After entering the bad management frame step 303, the transceiver 200 transitions to the detect preamble step 301. This enables the transceiver 200 to stop monitoring the incoming non-conforming management frame and resume the reception of management frames once the next management frame is transmitted by the station management entity 206. As a result, it is not necessary for the station management entity 206 or any other component to provide any special signal to the transceiver 200 to re-enable its ability to receive management frames. In the bad management frame step 303, an indication of the bad management frame may be provided as a statistic for a network administrator. 
     FIG. 6 illustrates a more detailed block diagram of transceiver 200, which is capable of performing the process steps shown in FIG. 5. As stated previously, the transceiver 200 includes physical layer devices 201 coupled to a bus 207 and a station management circuit 202 coupled to the bus 207. For purposes of describing the present invention, the transceiver 200 will be described as having four physical layer devices 201 1-4 , although different numbers of physical layer devices may be included. As shown in FIG. 6, each physical layer device 201 1-4  is coupled to the bus 207 through a set of PHY data signals 333 and a set of PHY address and control signals 334. The station management circuit 202 is coupled to the bus through a set of management data signals 235 and a set of management address and control signals 336. 
     The station management circuit 202 includes a MII interface circuit 320, a management data storage unit 322, and a management frame state machine circuit 321. The management data storage unit 322 is coupled to the management address and control signals 336 and the management data signals 335. The management data storage unit 322 contains a plurality of data storage elements, which contain data such as network status information and instructions. The network status information may be obtained from the physical layer devices 201 1-4  through the bus 207. The instructions may be received from incoming management frames via the MII interface circuit 320. The management data storage unit 322 may also include data storage elements containing the address of each physical layer device 201 1-4 . Each data storage element in the management data storage unit 322 has an address, which may be indicated in a REGAD field 225 of a management frame 220. 
     The MII interface circuit 320 has a MDC input 338 for coupling to the MDC 209 and a MDIO input/output 339 for coupling to the MDIO 208. The MII interface circuit 320 is also coupled to the management address and control signals 336 and the management data signals 335. This enables the MII interface circuit 320 to address the management data storage unit 322 using the bits in a REGAD field 225 and transfer data between the management data storage unit 322 and the MDIO 208. 
     The MII interface circuit 320 also provides a set of input signals 340 to the management frame state machine 321 and receives a set of outputs 341 provided by the management frame state machine 321. The management frame state machine 321 performs a series of operations to enable the station management circuit 202 to monitor incoming management frames 220 and detect bad management frames, which do not conform to the frame template specified in the IEEE 802.3u standard. 
     FIG. 7 provides a more detailed illustration of the interface between the MII interface circuit 320 and the management frame state machine 321. The following provides a description of each of the input signals 340: 
     
         ______________________________________Input           Description______________________________________mii.sub.-- clk  Provides the signal being           received on the MDC input 338.mdio.sub.-- in  Provides the signal being           received and transmitted on the           MDIO input/output 339.io.sub.-- reset Provides a reset signal           indicating that the station           management circuit 202 is being           reset.valid.sub.-- regid           Provides a signal indicating           that the REGAD field 225           corresponds to an address of a           location in the management data           storage unit 322.reg.sub.-- nomatch           Provides a signal indicating           that the REGAD field 225 does           not correspond to an address of           a location in the management           data storage unit 322.io.sub.-- cs.sub.-- 1           Provides a signal indicating           that the management data storage           unit 322 is to be loaded with           data on the MDIO input/output           339.m0.sub.-- phyid.sub.-- reg 4:0!           Provides the address for the           first physical layer device           201.sub.1.m1.sub.-- phyid.sub.-- reg 4:0!           Provides the address for the           second physical layer device           201.sub.2.m2.sub.-- phyid.sub.-- reg 4:0!           Provides the address for the           third physical layer device           201.sub.3.m3.sub.-- phyid.sub.-- reg 4:0!           Provides the address for the           fourth physical layer device           201.sub.4.______________________________________ 
    
     One with ordinary skill in the art will recognize that the inputs m0 --  phyid --  reg 4:0! through m3 --  phyid --  reg 4:0! may be expanded or reduced in number depending upon the number of physical layer devices included in the transceiver 200. 
     The following provides a description of each of the output signals 341: 
     
         ______________________________________Output          Description______________________________________ta.sub.-- cycle1           Asserted when a first bit of a           TA field 226 is provided on the           MDIO input/output 339.ta.sub.-- cycle2           Asserted when a second bit of a           TA field 226 is provided on the           MDIO input/output 339.op.sub.-- rd    Asserted when the OP field 223           in the management frame 220           calls for a read operation.op.sub.-- wr    Asserted when the OP field 223           in the management frame 220           calls for a write operation.man.sub.-- data Asserted during the bit times of           a data field 227 being provided           on the MDIO input/output 339.data.sub.-- done           Asserted to indicate that the           data field 227 is completed.inv.sub.-- manfrm           Asserted to indicate that the           management frame state machine           321 detects that a management           frame does not conform to the           specified IEEE 802.3u frame           template.cmp.sub.-- regid           Asserted to indicate that all of           the bits from the REGAD field           225 have been captured from the           MDIO 208 and are available for           decoding on the regid 4:0!           outputs.port.sub.-- 0.sub.-- reg           Asserted when the PHYAD field           224 matches the address of the           first physica1 layer device           201.sub.1.port.sub.-- 1.sub.-- reg           Asserted when the PHYAD field           224 matches the address of the           second physica1 layer device           201.sub.2.port.sub.-- 2.sub.-- reg           Asserted when the PHYAD field           224 matches the address of the           third physica1 layer device           201.sub.3.port.sub.-- 3.sub.-- reg           Asserted when the PHYAD field           224 matches the address of the           fourth physica1 layer device           201.sub.4.regid 4:0!      Provides the data in the REGAD           field 224.inv.sub.-- phyid           Asserted when the PHYAD field           224 does not match the address           of any physica1 layer device           201 in the transceiver 200.inv.sub.-- regid           Asserted when the REGAD field           225 does not match the address           of any data storage elements in           the management data storage           unit 322.______________________________________ 
    
     One with ordinary skill in the art will recognize that the number of port --  0 --  reg through port --  3.sub. reg outputs may be expanded or reduced based upon the number of physical layer devices 201 in the transceiver 200. 
     FIG. 8 illustrates a state diagram 400 for the management frame state machine 321 in FIG. 7. Further, Appendix A provides a Verilog functional description of the management frame state machine 321 having the state diagram 400 illustrated in FIG. 8. Using Verilog design tools, one with ordinary skill in the art will be able to have the functional description appearing in Appendix A converted to circuitry that forms an embodiment of the management frame state machine 321 having the state diagram shown in FIG. 8. 
     The state diagram 400 in FIG. 8 will now be described. In describing the state diagram 400, the state transitions will be explained with respect to events that are ascertained by examining data in a management frame 220. The signal names and logic equations appearing in state diagram 400, which cause the state transitions, will be more fully described with reference to Appendix A. 
     The management frame state machine 321 may begin in an IDLE state 401 and remain there until the management frame state machine 321 detects that a preamble field 221 of a management frame is beginning to be received at the MDIO input/output 339. Once the beginning of the preamble field 221 is detected; the state machine 321 transitions to a PREAMBLE state 402. Alternatively, the state machine 321 may transition to a ST state 403, if the ST field 222 of a management frame 220 is provided to the MDIO input/output 339. This may occur when the management frame 220 does not include a preamble field 221. 
     In the PREAMBLE state 402, the state machine 321 monitors the mdio --  in input to determine if thirty two consecutive logic 1 values have been received on the MDIO input/output 339. After receiving thirty two consecutive logic 1 values and the first logic 0 value bit of the ST field 222, the state machine 321 transitions to the ST state 403. If a logic 0 value is detected on the MDIO input/output 339 before the preamble field 221 is completed, the state machine 321 transitions to a BAD --  FR state 409. The BAD --  FR state 409 is entered because a logic 0 value in the preamble field 221 indicates that the incoming management frame 220 does not conform to the IEEE 802.3u specified frame template. 
     In the ST state 403, the state machine 321 determines whether the second bit in the ST field 222 is a logic 1 value. If this bit is a logic 1 value, the state machine transitions to a OP state 404. Otherwise, the state machine transitions to the BAD --  FR state 409, because the incoming management frame 220 does not conform to the required template. 
     In the OP state 404, the state machine 321 determines whether the OP field 223 has been received on the MDIO input/output 339 and whether the OP field 223 contains a valid bit pattern. If the received OP field 223 has a logic value 01 or 10 bit pattern, (with the left most bit value being the first bit received by the MDIO input/output 339) the state machine 321 transitions to a PHYID state 405. If the received OP field 223 has a logic value 11 or 00 bit pattern, then the state machine 321 transitions to the BAD --  FR state 409, because the management frame 220 is not in conformance with the required frame template. 
     In the PHYID state 405, the state machine 321 asserts either the op --  rd or op --  wr output, based upon the bit pattern in the OP field 223. The op --  rd signal is asserted if the OP field 223 contains a logic value 10 bit pattern. The op --  wr signal is asserted if the OP field 223 contains a logic value 01 bit pattern. The op --  wr or op --  rd signal will remain asserted until the io --  reset input is asserted or the state machine enters the ST state 403. In either of these instances, both the op --  rd and op --  wr outputs will be deasserted. 
     The state machine 321 remains in the PHYID state 405 for the time that the MDIO input/output 339 is receiving the PHYAD field 224 of the management frame 220. Once the entire PHYAD field 224 has been received, the state machine 321 transitions to the REGID state 406. 
     The state machine 321 remains in the REGID state 406 until the entire REGAD field 225 of the incoming management frame 220 is received by the MDIO input/output 339. In the second mii --  clk cycle in the REGID state 406, the port --  0 --  reg, port --  1 --  reg, port --  2 --  reg, port --  3 --  reg, and inv --  phyid outputs become valid. The outputs are set based upon a comparison by the state machine of the received PHYAD field 224 with the m0 --  phyid --  reg  4:0! through m3 --  phyid --  reg  4:0! inputs. The port --  0 --  reg, port --  1 --  reg, port --  2 --  reg, port --  3 --  reg, and inv --  phyid outputs remain valid until the io --  reset input is asserted or the ST state 403 is entered. In both of these instances, the aforementioned outputs are all deasserted. 
     Once the entire REGAD field 225 of the management frame 220 is received, the state machine 321 transitions to a TA state 407. The state machine remains in the TA state until the entire TA field 226 of the incoming management frame 220 is transferred on the MDIO input/output 339. In the first mii --  clk cycle in the TA state, the ta --  cycle1 output is asserted to indicate that the first TA field 226 bit is being received. In the same mii --  clk cycle, the cmp --  regid output is asserted and the regid 4:0! outputs become valid. The cmp --  regid output remains asserted until the io --  reset input is asserted or the ST state 403 is entered. The regid 4:0! outputs remain valid until either the io --  reset input is asserted or the ST state 403 is entered. 
     In a second mii --  clk cycle in the TA state, the ta --  cycle1 output is deasserted and the ta --  cycle2 output is asserted to indicate that the second TA field 226 bit is being received. In the same mii --  clk cycle, the inv --  regid output becomes valid to indicate whether the REGAD field 225 value corresponded to any of the data storage element addresses in the management data storage unit 322. The inv --  regid output remains unchanged until the io --  reset input is asserted or the ST state 403 is entered. Once the entire TA field 226 is received, the state machine transitions to a DATA state 408. 
     In the DATA state 408, the man --  data output is asserted, until the DATA state is exited, to indicate that the DATA field 227 portion of the management frame 220 has arrived. During the DATA state 408, the MII interface circuit 320 either performs a read operations, write operation, or no operation, in conformance with the IEEE 802.3u standard, based upon the values presented on the outputs of the state machine 321. If the inv --  manfrm output is asserted, the transceiver 200 will not drive the MDIO input/output 339 during the DATA state 408. 
     During the first mii --  clk cycle in the DATA state 408, the bits received from the TA field 226 are evaluated. If the op --  wr output is asserted and TA field 226 bits are not a logic value 10 bit pattern, the state machine 321 will transition to the BAD --  FR state. Otherwise, the state machine 321 will remain in the DATA state 408 until the entire DATA field 227 is transferred on the MDIO input/output 339. Once the last bit in the DATA field 227 has been transferred on the MDIO input/output 339, the state machine 321 transitions to the IDLE state 401. In the first mii --  clk cycle in the IDLE state 401, the data --  done output is asserted. In the second mii --  clk cycle in the IDLE state, the data --  done output is deasserted. 
     In the BAD --  FR state 409, the state machine 321 will transfer to the ST state 403 once a valid preamble field 221 has been received on the MDIO input/output 339 and the first logic 0 value bit of the ST field 222 has been provided to the MDIO input/output 339. Otherwise, the state machine 321 remains in the BAD --  FR state 409. This enables the management frame state machine 321 to exit the BAD --  FR state 409 upon recognizing that a new management frame is being provided to the MDIO input/output 339. While in the BAD --  FR state 409, the management frame state machine 321 asserts the inv --  manfrm output. 
     Appendix A provides a Verilog functional description of a state machine 321 of the present invention, which implements the state diagram 400 shown in FIG. 8. In order to describe the Verilog functional description in Appendix A, the description has been divided into numbered segments 500-508, which will each be described. In segment 500, each of the signals in the functional model is defined as being either an output, input, wire (internal signal), register, or combination thereof. Also in segment 500, each of the state machine 321 states 401-409 is defined. 
     In segment 503, certain signals are assigned to be asserted when the state machine 321 is in a specified state. The man --  pream signal is defined to be asserted when the state machine is in the PREAMBLE state 402. The man --  st signal is defined to be asserted when the state machine 321 is in the ST state 403. The man --  op signal is defined to be asserted when the state machine 321 is in the OP state 404. The man --  phyid signal is defined to be asserted when the state machine 321 is in the PHYID state 405. The man --  regid signal is defined to be asserted when the state machine 321 is in the REGID state 406. The man --  ta signal is defined to be asserted when the state machine is in the TA state 407. The man --  data signal is defined to be asserted when the state machine 321 is in the DATA state 408. The inv --  manfrm signal is defined to be asserted when the state machine 321 is in the BAD --  FR state 409. 
     In segment 501, an int --  reset signal is assigned the value provided on the io --  reset input. In segment 502, the transition conditions for each state 401-409 in the state machine 321 are specified. All state transitions are specified to take place on the rising edge of the mii --  clk input. When the int --  reset signal is asserted, the state machine 321 transitions to the IDLE state 401. When the state machine 321 is in the IDLE state 401 and the data --  done signal is not asserted and the mdio --  in signal is a logic 1 value, the state machine 321 transitions to the PREAMBLE state 402. When in the IDLE state 401 and the data --  done signal is not asserted and the mdio --  in signal is a logic 0 value, the state machine 321 transitions to the ST state 403. Otherwise, the state machine 321 remains in the IDLE state 401. 
     When the state machine 321 is in the PREAMBLE state 402 and the invalid --  pream signal is asserted, the state machine 321 transitions to the BAD --  FR state 409. When the invalid --  pream signal is not asserted and the state machine is in the PREAMBLE state 402 and the mdio --  in is a logic 0 value and either the cnt --  32 signal is asserted or the cnt --  32 --  flg signal is asserted, the state machine 321 transitions to the ST state 403. Otherwise, the state machine 321 remains in the PREAMBLE state 402. As a result, the ST state 403 is entered after the first bit in the ST field 222 is received by the MDIO input/output 339. 
     Segment 504 defines the invalid --  pream, cnt --  32, and cnt --  32 --  flg signals. A pream --  cntr is defined in segment 500 as a seven bit register. The pream --  cntr may be loaded or incremented at each rising edge of the mii --  clk. The pream --  cntr is set to a logic 0 value, if the int --  reset signal is asserted or the mdio --  in signal is a logic 0 value. Otherwise, the pream --  cntr is incremented by one if the mdio --  in signal is a logic 1 value. The cnt --  32 signal is asserted when the pream --  cntr reaches a value of 32 (20 hexadecimal). The cnt --  32 --  flg signal is set on each rising edge of the mii --  clk input. If the int --  reset is asserted or the state machine 321 is in the ST state 402, the cnt --  32 --  flg signal is set to a logic 0 value. Otherwise, if the cnt --  32 signal is asserted, the cnt --  32 --  flg signal is asserted to a logic 1 value. The invalid --  pream signal is asserted when the state machine 321 is in the PREAMBLE state 402 and the mdio --  in signal is a logic 0 value and neither cnt --  32 nor cnt --  32 --  flg is asserted. 
     As shown in segment 502 the state machine 321 transitions out of the ST state 403 and into the OP state when the mdio --  in signal is a logic 1 value. If the mdio --  in signal is a logic 0 value, the state machine 321 transitions to the BAD --  FR state 409, since a logic 0 value indicates that the management frame 220 does not conform to the IEEE 802.3 frame template. 
     Once the state machine 321 is in the OP state 404, the state machine 321 transitions to the PHYID state if the mdio --  in signal has a logic value different than the shft --  2 0! signal and the check --  op signal is asserted. The mdio --  in and shft --  2 0! are different when the OP field 223 contains either a logic value 01 or 10 bit pattern. If the mdio --  in signal and shft --  2 0! are not dissimilar and check --  op is asserted, the OP field 223 is not in conformance with the required frame template, and the state machine 321 transitions to the BAD --  FR state 409. Otherwise, the state machine 321 remains in the OP state 404. 
     Segment 505 defines the operation of the shft --  2 2:0!, invalid --  op, op --  wr, op --  rd, and check --  op signals. The shft --  2 2:0! is a three bit register value that is either loaded or shifted at the rising edge of the mii --  clk. If int --  reset is asserted or the state machine 321 is in the ST state 403, shft --  2 2:0! is loaded with a logic value 001 bit pattern, so that shft --  2 0! is 1, shft --  2 1! is 0, and shft --  2 2! is 0. If the state machine 321 is in the OP state 404, which lasts for two mii --  clk cycles, shft --  2 2:0! is shifted, so that shft --  2 1! is shifted into shft --  2 2!, shft --  2 0! is shifted into shft --  2 0! and shft --  2 0! is loaded with mdio --  in. During the second mii --  clk cycle in the OP state 404, which is the last mii --  clk cycle in the OP state 404, shft --  2 0! contains the first bit in the OP field 223 and mdio --  in is the second bit in the OP field 223. 
     The check --  op signal is asserted when shft --  2 1! is a logic 1 value and the state machine is in the OP state 404. This condition is true during the second mii --  clk cycle in the OP state 404. The invalid --  op signal is asserted when shft --  2 2! is a logic 1 value and shft --  2 ! and shft --  2 0! are the same logic value. The op --  wr signal is asserted when the shft --  2 2! is a logic 1 value and the shft --  2 1! is a logic 0 value and the shft --  2 0! is a logic 1 value. The op --  rd signal is asserted when the shft --  2 2! is a logic 1 value and the shft --  2 ! is a logic 1 value and the shft --  2 0! is a logic 0 value. The shft --  2 2:0! shifts for the last time when the state machine 321 transitions out of the OP state 404. At this instance, the op --  wr, op --  rd, and invalid --  op signals are set for the incoming management frame 220. 
     As shown in segment 502, the state machine 321 transitions from the PHYID state 405 to the REGID state 406 when the goto --  regid signal is asserted. Otherwise, the state machine 321 remains in the PHYID state 405. The state machine transitions from the REGID state 406 to the TA state 407 when the go --  ta signal is asserted. Otherwise, the state machine 321 remains in the REGID state 406. Once in the TA state 407, the state machine 321 transitions to the DATA state 408 when the goto --  data signal is asserted. Otherwise, the state machine 321 remains in the TA state 407. 
     Segment 506 shows the logic operations that are associated with the PHYID state 405 and REGID state 406. The shft --  11 10:0! is an eleven bit register value. The shft --  11 10:0! is either shifted or loaded on the rising edge of the mii --  clk input. When either int --  reset is asserted or the state machine 321 is in the ST state 403, the shft --  11 10:0! is loaded with a logic value 00000000001 bit pattern. Otherwise, if the state machine 321 is in either the PHYID state 405 or the REGID state 406, the shft --  11 10:0! is shifted in the same manner that shft --  2 2:0! is shifted. 
     The goto --  regid signal is asserted when the state machine 321 is in the PHYID state 405 and the shft --  11 4! bit is set to a logic 1 value. The goto --  ta signal is asserted when the state machine 321 is in the REGID state 406 and the shft --  11 9! bit is a logic 1 value. Upon entering the TA state 406, the PHYAD field 224 will be contained in shft --  11 9:5! and the REGID field 225 will be contained in shft --  11 4:0!. 
     A man --  phyid --  dly signal is defined as being set at the rising edge of each mii --  clk input. If int --  reset is asserted, the man --  phyid --  dly is deasserted to a logic 0 value. Otherwise, the man --  phyid --  dly signal is loaded with the man --  phyid signal value. A port --  0 signal is asserted when shft --  11 4:0! contains the value on the m0 --  phyid --  reg inputs. A port --  1 signal is asserted when shft --  11 4:0! contains the value on the m1 --  phyid --  reg inputs. A port --  2 signal is asserted when shft --  11 4:0! contains the value on the m2 --  phyid --  reg inputs. A port --  3 signal is asserted when shft --  11 4:0! contains the value on the m3 --  phyid --  reg inputs. An int --  inv --  phyid signal is asserted when the io --  cs --  1 input is a logic 1 value and man --  phyid --  dly is asserted and shft --  11 5! is a logic 1 value and neither port --  0, port --  1, port --  2, nor port --  3 is asserted. 
     The inv --  phyid output is set at the rising edges of the mii --  clk signal. If the int --  reset signal is asserted or the state machine 321 is in the ST state 403, inv --  phyid is deasserted to a logic 0 value. Otherwise, if int --  inv --  phyid is asserted, inv --  phyid is asserted. 
     The inv --  regid output is also set at the rising edges of the mii --  clk signal. If the int --  reset is asserted or the state machine 321 is in the ST state 403, inv --  regid is set to a logic 0 value. Otherwise, if the reg --  nomatch input is asserted and the ta --  cycle1 output is asserted, the inv --  regid output is asserted. 
     The port --  0 --  reg, port --  1 --  reg, port --  2 --  reg, and port --  3 --  reg outputs are each set on rising edges of the mii --  clk input. If the int --  reset signal is asserted or the state machine 321 is in the ST state 403, each of these outputs is deasserted to a logic 0 value. Otherwise, if the man --  phyid --  dly signal is asserted, port --  0 --  reg is loaded with the value in port --  0, port --  1 --  reg is loaded with the value in port --  1, port --  2 --  reg is loaded with the value in port --  2, and port --  3 --  reg is loaded with the value in port --  3. 
     The cmp --  regid output is set on each rising edge of the mii --  clk signal. If the int --  reset signal is asserted or the state machine 321 is in the ST state 403, the cmp --  regid output is set to a logic 0 value. Otherwise, if go --  ta is asserted, cmp --  regid is asserted to a logic 1 value. The regid 4:0! output is set to a logic value 00000 if cmp --  regid is a logic 0 value, but regid 4:0! is set to the value in shft --  11 4:0! if cmp --  regid is asserted to a logic 1 value. 
     Segment 507 defines the operation of the signals associated with the TA state 407. The shft --  3 2:0! is a three bit register value. On the rising edges of the mii --  clk input, shft --  3 2:0! may be either loaded or shifted. If int --  reset is asserted or go --  data is asserted, the shft --  3 2:0! is loaded with a logic value 001 bit pattern. Otherwise, if the state machine 321 is in the TA state 407, the shft --  3 2:0! is shifted in the same manner as shft --  2 2:0!, except that shft --  3 0! is loaded with the logical AND of the op --  wr output and the mdio --  in input. The goto --  data signal is asserted when shft --  3 1! is a logical 1 value, which will first occur after the first mii --  clk cycle in the TA state 407. 
     The ta --  cycle1 output is asserted when the state machine 321 is in the TA state 407 and the shft --  3 0! is a logic 1 value. The ta --  cycle2 output is asserted when the state machine 321 is in the TA state 406 and the shft --  3 1! is a logic 1 value. An invalid --  signal is asserted when op --  wr is asserted and shft --  3 2! is a logic 1 value and either shft --  3 1! is not a logic 1 value or shft --  3 0! is not a logic 0 value. This indicates that the management packet does not conform to the specified IEEE 802.3u frame template, since the TA field 226 does not have the proper bit pattern for a write operation. 
     As shown in Segment 502, the state machine 321 transitions from the DATA state 408 to the BAD --  FR state 409 when invalid --  ta is asserted. Otherwise, if int --  data --  done is asserted, the state machine 321 transitions from the DATA state 408 to the IDLE state 401. When neither invalid data nor int --  data --  done is asserted, the state machine remains in the DATA state 408. Segment 508 defines the operation of the signals associated with the DATA state 408. 
     A data --  cntr is defined to be a five bit register that is either loaded or incremented at the rising edges of the mii --  clk input. If the int --  reset is asserted or an int --  data --  done signal is asserted, the data --  cntr is loaded with a logical 0 value Otherwise, if the state machine 321 is in the DATA state 408, the data --  cntr is incremented by one. The int --  data --  done signal is asserted when the state machine 321 is in the DATA state 408 and the value in the data --  cntr is 15 (1111 binary). The data --  done output is set at each rising edge of the mii --  clk input, and if the int --  reset is asserted, the data --  done output is set to a logical 0 value. Otherwise, the data --  done output is loaded with the value of the int --  data --  done signal. 
     As shown in segment 502, the state machine 321 transitions from the BAD --  FR state 409 to the ST state 403 when mdio --  in is a logical 0 value and either cnt --  32 or cnt --  32 --  flg is asserted. Otherwise, the state machine 321 remains in the BAD --  FR state. This provides for the state machine 321 to transition out of the BAD --  FR state 409 upon recognizing that a new management frame is being transmitted on a management bus coupled to the MDIO input/output 339. 
     The station management circuit 202 may be formed alone on an integrated circuit. The station management circuit 202 may also be formed on an integrated circuit along with one or more physical layer devices to form a transceiver. Further, the station management circuit 202 may be formed on an integrated circuit along with one or more physical layer devices and a repeater unit to form a repeater set. 
     Although the invention has been described above with particularity, this was merely to teach one of ordinary skill in the art to make and use the invention. Many modifications will fall within the scope of the invention, as that scope is defined by the following claims. 
     
         ______________________________________APPENDIX AVERILOG FUNCTIONAL DESCRIPTION OF A MANAGEMENTFRAME STATE MACHINE CIRCUIT______________________________________Seqment 500module m.sub.-- frmsm(                     mii.sub.-- clk,                     io.sub.-- reset,                     mdio.sub.-- in,                     m0.sub.-- phyid.sub.-- reg,                     m1.sub.-- phyid.sub.-- reg,                     m2.sub.-- phyid.sub.-- reg,                     m3.sub.-- phyid.sub.-- reg,                     io.sub.-- cs.sub.-- 1,                     reg.sub.-- nomatch,                     ta.sub.-- cycle1, // outputs                     ta.sub.-- cycle2,                     man.sub.-- ta,                     op.sub.-- rd,                     op.sub.-- wr,                     regid,                     man.sub.-- data,                     data.sub.-- done,                     cmp.sub.-- regid,                     inv.sub.-- manfrm,                     inv.sub.-- phyid,                     inv.sub.-- regid,                     port.sub.-- 0.sub.-- reg,                     port.sub.-- 1.sub.-- reg,                     port.sub.-- 2.sub.-- reg,                     port.sub.-- 3.sub.-- reg);input                     mii.sub.-- clk;input                     mdio.sub.-- in,                     io.sub.-- reset,                     reg.sub.-- nomatch,                     io.sub.-- cs.sub.-- 1;input           4:0!      m0.sub.-- phyid.sub.-- reg;input           4:0!      m1.sub.-- phyid.sub.-- reg;input           4:0!      m2.sub.-- phyid.sub.-- reg;input           4:0!      m3.sub.-- phyid.sub.-- reg;output                    ta.sub.-- cycle1,                     ta.sub.-- cycle2,                     op.sub.-- rd,                     op.sub.-- wr,                     man.sub.-- ta,                     man.sub.-- data,                     data.sub.-- done,                     inv.sub.-- manfrm,                     cmp.sub.-- regid,                     port.sub.-- 0.sub.-- reg,                     port.sub.-- 1.sub.-- reg,                     port.sub.-- 2.sub.-- reg,                     port.sub.-- 3.sub.-- reg;output          4:0!      regid;output                    inv.sub.-- phyid;output                    inv.sub.-- regid;reg                       inv.sub.-- phyid;reg                       inv.sub.-- regid;wire                      ta.sub.-- cycle1;wire                      ta.sub.-- cycle2;wire                      op.sub.-- rd,                     op.sub.-- wr,                     int.sub.-- clk;wire                      man.sub.-- data;wire            4:0!      regid;reg                       cmp.sub.-- regid;reg                       port.sub.-- 0.sub.-- reg,                     port.sub.-- 1.sub.-- reg,                     port.sub.-- 2.sub.-- reg,                     port.sub.-- 3.sub.-- reg;wire                      int.sub.-- reset;wire                      int.sub.-- inv.sub.-- phyid;wire                      invalid.sub.-- op,                     valid.sub.-- phyid,                     cnt.sub.-- 32,                     cnt.sub.-- 5,                     goto.sub.-- data,                     invalid.sub.-- ta;reg             6:0!      pream.sub.-- cntr;reg             4:0!      data.sub.-- cntr;reg             2:0!      shft.sub.-- 2;reg             2:0!      shft.sub.-- 3;reg             10:0!     shft.sub.-- 11;wire                      invalid.sub.-- pream,                     man.sub.-- pream,                     man.sub.-- st ,                     man.sub.-- op ,                     man.sub.-- phyid ,                     man.sub.-- regid ,                     man.sub.-- ta ,                     inv.sub.-- manfrm ,                     goto.sub.-- regid,                     check.sub.-- op,                     goto.sub.-- ta;reg                       cnt.sub.-- 32.sub.-- flg;reg                       man.sub.-- phyid.sub.-- dly;reg             3:0! state;wire                      port.sub.-- 0,                     port.sub.-- 1,                     port.sub.-- 2,                     port.sub.-- 3;wire                      int.sub.-- data.sub.-- done;reg                       data.sub.-- done;parameter                 DLY = 5;// State parametersparameter    3:0!     IDLE        = 4&#39;h0,                 PREAMBLE    = 4&#39;h1,                 ST          = 4&#39;h3,                 OP          = 4&#39;h4,                 PHYID       = 4&#39;h5,                 REGID       = 4&#39;h6,                 TA          = 4&#39;h7,                 DATA        = 4&#39;h8,                 BAD.sub.-- FR                             = 4&#39;h9;Segment 501assign #DLY int.sub.-- reset = io.sub.-- reset;Segment 502always @( posedge mii.sub.-- clk)begin if ( int.sub.-- reset )  state &lt;= #DLY IDLE; else begin  case ( state)  IDLE:  if ( |data.sub.-- done)  begin   if ( mdio.sub.-- in)    state &lt;= #DLY PREAMBLE ;   else    state &lt;= #DLY ST;  end  else    state &lt;= #DLY IDLE;  PREAMBLE:  if ( invalid.sub.-- pream)    state &lt;= #DLY BAD.sub.-- FR;  else if ( (cnt.sub.-- 32 || cnt.sub.-- 32.sub.-- flg)&amp;&amp; |mdio.sub.-- in )    state &lt;= #DLY ST;  else    state &lt;= #DLY PREAMBLE;  ST:  if (mdio.sub.-- in)    state &lt;= #DLY OP;  else    state &lt;= #DLY BAD.sub.-- FR;  OP:  if ( check.sub.-- op)  begin    if ( mdio.sub.-- in .sup.  shft.sub.-- 2 0!)state &lt;= #DLY PHYID;    elsestate &lt;= #DLY BAD.sub.-- FR;  end  else    state &lt;= #DLY OP;  PHYID:  if ( goto.sub.-- regid)    state &lt;= #DLY REGID;  else    state &lt;= #DLY state;  REGID:  if (goto.sub.-- ta)    state &lt;= #DLY TA;  else    state &lt;= #DLY state;  TA:  if (goto.sub.-- data)    state &lt;= #DLY DATA;  else    state &lt;= #DLY state;  DATA:  if (invalid.sub.-- ta)    state &lt;= #DLY BAD.sub.-- FR;  else if ( int.sub.-- data.sub.-- done )    state &lt;= #DLY IDLE;  else    state &lt;= #DLY state;  BAD.sub.-- FR:  if ( ( cnt.sub.-- 32 || cnt.sub.-- 32.sub.-- flg) &amp;&amp;|mdio.sub.-- in )    state &lt;= #DLY ST;  else    state &lt;= #DLY state;  default:  state &lt;= #DLY IDLE;  endcaseend // end ifSegment 503assign #DLY      man pream   = state  == PREAMBLE;assign #DLY      man.sub.-- st        = state == ST ;assign #DLY      man.sub.-- op        = state == OP ;assign #DLY      man.sub.-- phyid                  = state  == PHYID;assign #DLY      man.sub.-- regid                  = state  == REGID;assign #DLY      man.sub.-- ta        = state == TA;assign #DLY      man.sub.-- data                  = state  == DATA;assign #DLY      inv.sub.-- manfrm                  = state  == BAD.sub.-- FR ;Segment 504always @ (posedge mii.sub.-- clk)begin  if ( int.sub.-- reset || |mdio.sub.-- in )   pream.sub.-- cntr &lt;= #DLY 7&#39;b0000.sub.-- 000;  else if ( mdio.sub.-- in )   pream.sub.-- cntr &lt;= #DLY pream.sub.-- cntr + 1 ;endassign #DLY cnt.sub.-- 32 = (pream.sub.-- cntr == 6&#39;h20) ;always @ (posedge mii.sub.-- clk)begin  if ( int.sub.-- reset || man.sub.-- st )   cnt.sub.-- 32.sub.-- flg &lt;= #DLY 1&#39;b0;  else if ( cnt.sub.-- 32)   cnt.sub.-- 32.sub.-- flg &lt;= #DLY 1&#39;b1;endassign #DLY invalid.sub.-- pream = man.sub.-- pream &amp;&amp; |mdio.sub.-- in&amp;&amp; |( cnt.sub.-- 32 || cnt.sub.-- 32.sub.-- flg) ;Segment 505always @(posedge mii.sub.-- clk)begin  if ( int.sub.-- reset || man.sub.-- st)   shft.sub.-- 2 &lt;= #DLY 3&#39;b001;  else if ( man.sub.-- op )  begin   shft.sub.-- 2  2! &lt;= #DLY shft.sub.-- 2  1!;   shft.sub.-- 2  1! &lt;= #DLY shft.sub.-- 2  0!;   shft.sub.-- 2  0! &lt;= #DLY mdio.sub.-- in;  endendassign #DLY invalid.sub.-- op = shft.sub.-- 2  2! &amp;&amp; |(shft.sub.-- 2 1!.sup.  shft.sub.-- 2  0!);assign #DLY op.sub.-- wr = shft.sub.-- 2 2! &amp;&amp; |shft.sub.-- 2 1! &amp;&amp;shft.sub.-- 2 0!;assign #DLY op.sub.-- rd = shft.sub.-- 2 2! &amp;&amp; shft.sub.-- 2 1! &amp;&amp;|shft.sub.-- 2 0!;assign #DLY check.sub.-- op = shft.sub.-- 2  1! &amp;&amp; man.sub.-- op ;Segment 506always @ (posedge mii.sub.-- clk)begin  if ( int.sub.-- reset || man.sub.-- st )   shft.sub.-- 11 &lt;= #DLY 11&#39;b00000000001;  else if ( man.sub.-- phyid || man.sub.-- regid )  beginshft.sub.-- 11 10! &lt;= #DLY shft.sub.-- 11 9!;shft.sub.-- 11 9! &lt;= #DLY shft.sub.-- 11 8!;shft.sub.-- 11 8! &lt;= #DLY shft.sub.-- 11 7!;shft.sub.-- 11 7! &lt;= #DLY shft.sub.-- 11 6!;shft.sub.-- 11 6! &lt;= #DLY shft.sub.-- 11 5!;shft.sub.-- 11 5! &lt;= #DLY shft.sub.-- 11 4!;shft.sub.-- 11 4! &lt;= #DLY shft.sub.-- 11 3!;shft.sub.-- 11 3! &lt;= #DLY shft.sub.-- 11 2!;shft.sub.-- 11 2! &lt;= #DLY shft.sub.-- 11 1!;shft.sub.-- 11 1! &lt;= #DLY shft.sub.-- 11 0!;shft.sub.-- 11 0! &lt;= #DLY mdio.sub.-- in;  endendassign #DLY goto.sub.-- regid = man.sub.-- phyid &amp;&amp; shft.sub.-- 11 4!;assign #DLY goto.sub.-- ta = man.sub.-- regid &amp;&amp; shft.sub.-- 11 9!;always @( posedge mii.sub.-- clk)  if ( int.sub.-- reset)   man.sub.-- phyid.sub.-- dly &lt;= #DLY 1&#39;b0;  else   man.sub.-- phyid.sub.-- dly = #DLY man.sub.-- phyid; assign #DLY port.sub.-- 0 = ( shft.sub.-- 11 4:0! == m0.sub.-- phyid.sub.-- reg );assign #DLY port.sub.-- 1 = ( shft.sub.-- 11 4:0! == m1.sub.-- phyid.sub.-- reg );assign #DLY port.sub.-- 2 = ( shft.sub.-- 11 4:0! == m2.sub.-- phyid.sub.-- reg );assign #DLY port.sub.-- 3 = ( shft.sub.-- 11 4:0! == m3.sub.-- phyid.sub.-- reg );assign #DLY int.sub.-- inv.sub.-- phyid =   io.sub.-- cs.sub.-- 1 &amp;&amp;man.sub.-- phyid.sub.-- dly &amp;&amp;shft.sub.-- 11 5! &amp;&amp;  (| ( port.sub.-- 0 || port.sub.--1 || port.sub.-- 2 || port.sub.-- 3));always @(posedge mii.sub.-- clk)begin  if (int.sub.-- reset || man.sub.-- st)   inv.sub.-- phyid &lt;= #DLY 1&#39;b0;  else if ( int.sub.-- inv.sub.-- phyid)   inv.sub.-- phyid &lt;= #DLY 1&#39;b1;endalways @(posedge mii.sub.-- clk)begin  if (int.sub.-- reset || man.sub.-- st)   inv.sub.-- regid &lt;= #DLY 1&#39;b0;  else if ( reg.sub.-- nomatch &amp;&amp; ta.sub.-- cycle1)   inv.sub.-- regid &lt;= #DLY 1&#39;b1;endalways @ ( posedge mii.sub.-- clk)begin  if ( int.sub.-- reset || man.sub.-- st)  begin   port.sub.-- 0.sub.-- reg &lt;= #DLY 1&#39;b0;   port.sub.-- 1.sub.-- reg &lt;= #DLY 1&#39;b0;   port.sub.-- 2.sub.-- reg &lt;= #DLY 1&#39;b0;   port.sub.-- 3.sub.-- reg &lt;= #DLY 1&#39;b0;  end  else if ( man.sub.-- phyid.sub.-- dly)  begin   port.sub.-- 0.sub.-- reg &lt;= #DLY port.sub.-- 0;   port.sub.-- 1.sub.-- reg &lt;= #DLY port.sub.-- 1;   port.sub.-- 2.sub.-- reg &lt;= #DLY port.sub.-- 2;   port.sub.-- 3.sub.-- reg &lt;= #DLY port.sub.-- 3;  endendalways @( posedge mii.sub.-- clk)begin  if ( int.sub.-- reset || man.sub.-- st)  cmp.sub.-- regid &lt;= #DLY 1&#39;b0;  else if ( goto.sub.-- ta)  cmp.sub.-- regid &lt;= #DLY 1&#39;b1;endassign #DLY regid = ( cmp.sub.-- regid ) ? shft.sub.-- 11 4:0!: 5&#39;b00000Segment 507always @(posedge mii.sub.-- clk)begin  if ( int.sub.-- reset || goto.sub.-- data)   shft.sub.-- 3 &lt;= #DLY 3&#39;b001 ;  else if ( man.sub.-- ta )  begin   shft.sub.-- 3 2! &lt;= #DLY shft.sub.-- 3  1!   shft.sub.-- 3 1! &lt;= #DLY shft.sub.-- 3  0!;   shft.sub.-- 3 0! &lt;= #DLY ( op.sub.-- wr &amp;&amp; mdio.sub.-- in ) ;  endendassign #DLY goto.sub.-- data = shft.sub.-- 3 1!;assign #DLY invalid.sub.-- ta = op.sub.-- wr &amp;&amp; shft.sub.-- 3 2! &amp;&amp;|(shft.sub.-- 3 1! &amp;&amp;|shft.sub.-- 3 0!);assign #DLY ta.sub.-- cycle1 = man.sub.-- ta &amp;&amp; shft.sub.-- 3 0! ;assign #DLY ta.sub.-- cycle2 = man.sub.-- ta &amp;&amp; shft.sub.-- 3 1! ;Segment 508always @(posedge mii.sub.-- clk)begin  if ( int.sub.-- reset || int data.sub.-- done )   data.sub.-- cntr &lt;= #DLY 4&#39;b0000;  else if (man.sub.-- data)   data.sub.-- cntr &lt;= #DLY data.sub.-- cntr + 1;endassign #DLY int.sub.-- data.sub.-- done = (man.sub.-- data) &amp;&amp;(data.sub.-- cntr == 4&#39;b1111);always @(posedge mii.sub.-- clk)begin  if ( int.sub.-- reset )   data.sub.-- done &lt;= #DLY 1&#39;b0;  else   data.sub.-- done &lt;= #DLY int.sub.-- data.sub.-- done;endendmodule // m.sub.-- frmsm______________________________________