Abstract:
The invention is embodied in a system comprising image memory and a display processor that automatically processes video data which alternate between having chrominance pixels of greater area than luminance pixels and having chrominance pixels of the same area as luminance pixels. Subsamples describing chrominance pixels of greater size are time-division-multiplexed with samples describing pixels in the image memory output when the former type of processing is done. Whichever format for video data is currently being used, the channel for reading subsamples from image memory to the display processor is used to transmit flag data controlling the mode of processing of video data performed by the video processor.

Description:
The present disclosure relates to display processors used as buffers between digital memories and display devices such as kinescopes. 
     BACKGROUND OF THE INVENTION 
     In kinescope displays drawn from computer memory that describe graphics, the practice is to sample both the luminosity and the chromaticity of the same picture elements (&#34;pixels&#34;). This is done to maintain high resolution edges in chrominance signal components as well as in luminance signal components. Since luminance and chrominance are sampled with equal spatial densities, the video data is stored in the form of pixel descriptors for successive pixels in raster scan, each descriptor containing both luminance and chrominance information concerning a particular pixel. These descriptors may be stored in a bit-map-organized format or in a run-length format, for example. These pixel descriptors may comprise luminance and chrominance signal components per se. But often these pixel descriptors are pointer data applied as read addresses to color map memories that store luminance and chrominance signal components in their addressed storage locations. 
     In kinescope displays based on camera-originated video, a practice has been to use narrower spatial bandwidths for chrominance than for luminance. A computer memory for storing such video in digital sampled-data form may sample luminance signal more densely than chrominance signal in the direction of line advance in the raster scan as well as in the direction of pixel scanning along a raster line. In effect, then, one chrominance pixel takes up the same area on the display screen as a rectangular array of smaller-area luminance pixels. Such systems particularly well-suited to storing luminance and chrominance data in a video random-access memory (VRAM) with serial output port are described in detail by D. L. Sprague, N. Fedele and L. D. Ryan in U.S. Pat. No. 4,740,832, filed Oct. 14. 1986, entitled &#34;IMAGE STORAGE USING SEPARATELY SCANNED LUMINANCE AND CHROMINANCE VARIABLES&#34; and assigned to RCA Corporation. In these systems, to accommodate the difference in luminance and chrominance signal sampling densities, luminance and chrominance are stored in separate bit-map-organized portions of the video random-access memory. The samples of luminance signal are read from VRAM serial output port on a real-time basis during line trace intervals. The samples of chrominance signal are read from VRAM serial output port on a compressed-and-advanced-in-time basis during line retrace intervals. The chrominance signal is retimed and is resampled in an interpolation process supported by rate-buffering line stores, to generate a new set of chrominance samples in suitable temporal relationship with related luminance samples. 
     SUMMARY OF THE INVENTION 
     The invention is embodied in a system comprising image memory and a display processor that automatically processes video data which alternate between having chrominance pixels of greater area than luminance pixels and having chrominance pixels of the same area as luminance pixels. Subsamples describing chrominance pixels of greater size are multiplexed with samples describing luminance pixels in the image memory output when the former type of processing is done. Whichever format for video data is currently being used, subsamples are read from image memory to the display processor to provide flag data that describe the coding standard for the image data currently being processed and control the mode of processing of video data performed by the video processor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a block schematic diagram of a computer graphics system embodying the invention. 
     FIG. 2 is a diagram showing how one may arrange to store, in the video random-access memory of the FIG. 1 system, two frames of video information in which chrominance is subsampled respective to full display resolution. 
     FIG. 3 is a block schematic diagram of another computer graphics system embodying the invention. 
     FIG. 4 is a diagram showing how one may arrange to store, in the video random-access memory of the FIG. 3 system, two frames of video information in which color map addressing is subsampled respective to full display resolution. 
     FIG. 5 is a block schematic diagram of a variant of the FIG. 1 computer graphics system. 
    
    
     DETAILED DESCRIPTION 
     In the FIG. 1 computer graphics processor, a drawing processor 2 controls writing into and reading from the random-access port 3 of a video random-access memory, or VRAM 4. VRAM 4 differs from conventional random-access memory, or RAM, in having a serial-access port 5 from which a row of memory data parallelly transferred to an internal buffer can be read serially at high clock rate. (In some VRAM structures data can be serially written into buffer memory via the serial-access port at high clock rate and transferred in parallel into the RAM portion of the VRAM.) Drawing processor 2 accepts compressed video data from a source 6 thereof and subsequently updates images stored in VRAM 4 in accordance with the instructions contained in that compressed video data. Drawing processor 2 does this updating in a portion of the time that VRAM 4 is available for random-access. In the remaining portion of the time that VRAM 4 is available for random-access, drawing processor 2 permits the interchange of data in either direction between VRAM 4 and a general purpose processor 7. That is, in addition to portions of VRAM 4 serving as the image memory for graphics, other portions of VRAM 4 are available for other computer memory functions. 
     VRAM 4 also is used to store higher-level operating instructions for drawing processor 2, which are programmed using general purpose processor 7 or from header information in the compressed video supplied from source 2. These higher-level operating instructions augment fundamental operating instructions stored in an instruction list within the drawing processor 2 itself. These fundamental, lower-level operating instructions for drawing processor 2 permit initial operation so higher-level instructions can be entered into VRAM 4. 
     A display synchronization signal generator 8 furnishes horizontal and vertical synchronizing signals to kinescope deflection circuitry 9, which controls the path of beam trace across the display screen of a kinescope 10 on which the computer graphics are to be displayed. These and other synchronizing signals are supplied by generator 8 to VRAM read-out control circuitry 11. Control circuitry 11, which has been incorporated in the same monolithic integrated circuit as drawing processor 2, includes a set of row counters for generating row addresses controlling the loading of rows of image data from the RAM portion of VRAM 4 into the buffer from which serial output is taken via serial access port 5. Control circuitry also supplies read-out clock signals via a connection 12 to VRAM 4 for clocking the selected row of image data serially through the serial-access port 5. 
     A formatter 13 accepts read-out from VRAM 4 which is a standard number (e.g., thirty-two) of bits wide and parses it into individual pixel data. Control circuitry 11 supplies a clock signal via connection 14 for formatter 7 output signal and also supplies control signals to control parsing into individual pixel data. Formatter 13 is the input stage of a display processor 15 including a mode switch 16 for selecting one of two sets of display information as its output signal. Each of these sets of information comprises a digitized luminance, or Y, signal and two digitized chrominance, or C 1  and C 2 , signals. The selected set is supplied by mode switch 16 to digital-to-analog converters 17, 18 and 19 to generate an analog Y signal, an analog C 1  signal and an analog C 2  signal respectively. The analog Y, C 1  and C 2  signals are supplied to a video matrixing circuit 20 which linearly combines them to generate red (R), green (G) and blue (B) color component signals. Video amplifiers 21, 22 and 23 respond to these R, G and B signals to apply drive signals to kinescope 10 controlling the color and intensity of the raster-scanned display. 
     Map memories 24, 25 and 26 are included in the display processor 15 for storing digital values of Y, C 1  and C 2  respectively. Map memories 24, 25 and 26 generate the first of the two sets of Y, C 1  and C 2  signals between which mode switch 16 selects. This first set of Y, C 1  and C 2  signals is generated responsive to read addresses supplied from formatter 13 at full pixel scan rate in real time during kinescope 10 line trace intervals. Map memories 24, 25 and 26 may be read-only memories (ROMs), programmable read-only memories (PROMs), or RAMs operated as ROMs. The latter choice is usually the most practical in terms of flexibility in graphics processing. The RAMs may be re-programmed during display retrace intervals, down-loading from VRAM 4 through formatter 13, to implement an adaptive pixel coding scheme. 
     Display processor 15 includes a chroma resampling apparatus 30 for generating the second set of Y, C 1  and C 2  digitized signals that the mode switch 16 may select. The Y component of this second set of digitized signals is supplied mode switch 16 from VRAM 4 via formatter 13 in real time during line trace intervals. Supplying of the Y signal to mode switch 16 is shown being done directly from formatter 13 via digital bus 28, but may be done instead through a second map memory for Y signal values. The C 1  and C 2  components of this second set of digitized signals that ar supplied to mode switch 16 is generated in chroma resampling apparatus 30, by interpolating from time-compressed digital signals supplied from VRAM 4 via formatter 13 during selected line retrace intervals. Suppose both C 1  and C 2  are sampled less densely than Y by a factor of 2 n  :1 in both the direction of line scan and the direction perpendicular thereto, n being a positive integer at least two. Odd-numbered lines of C 1  and C 2  in the subsampled raster scan are written into line store RAMs 31 and 32 in line retrace intervals immediately flanking the first active display line trace interval and every 2.sup.(n+1) th display line retrace interval thereafter in each display frame. Even-numbered lines of C 1  and C 2  are written into line store RAMs 33 and 34 in line retrace intervals immediately flanking the (2n+1)th active display line trace interval and every 2.sup.(n+1)th display line trace interval thereafter in each display frame. 
     Each of the RAMs 31-34 is read at 2 -  n times pixel scan rate during each line trace interval. A multiplexer 35 permutes the outputs of C 1  line store RAMs 31 and 33 at subsampled chrominance scan line rate to supply a two-dimensional interpolator 37 with two adjacent scan lines of chrominance subsamples. Interpolator 37 performs a bilinear interpolation between successive sets of four samples supplied to its inputs to generate a digitized C 1  signal at its output that is sampled at the same density as the digitized Y signals supplied with it to mode switch 16. A multiplexer 36 permutes the outputs of C 2  line store RAMs 32 and 34 at subsampled chrominance scan line rate to supply a two-dimensional interpolator 38 two adjacent scan lines of chrominance subsamples. Interpolator 38 performs a bilinear interpolation between successive sets of four samples supplied to its input to generate a digitized C 2  signal at its output that is sampled at the same density as the digitized C 1  and Y signals supplied with it to mode switch 16. (Bilinear interpolation is an interpolative process separable into consecutive linear interpolations in each of two mutually orthogonal dimensions.) Reading out from RAMs 31-34 is preferably started enough before line trace interval to compensate for the delay introduced into the resampled C 1  and C 2  signals by interpolators 37 and 38 respectively. 
     The system as thusfar described is essentially the same as that described by D. L. Sprague et al. in U.S. Pat. No. 4,740,832, filed Oct. 14, 1986 entitled &#34;IMAGE STORAGE USING SEPARATELY SCANNED LUMINANCE AND CHROMINANCE VARIABLES&#34; and assigned to RCA Corporation. The invention concerns how to control mode switch 16 selecting between the first and second sets of Y, C 1  and C 2  digital data it is supplied with. An underlying precept of the invention is to provide the mode flag information (or F signal) at a spatial subsampling density substantially less dense than spatial sampling density for the luminance component of video. The spatial subsampling density for the F signal may the same as that for the C 1  and C 2  signals, or it may be even less dense. The subsampling of the F signal as compared to the Y signal describing the luminance component of the video reduces the amount of memory taken up by the F signal in the VRAM 4. 
     The storing of mode switching flag information in bit-map organization in VRAM, albeit in a less densely sampled bit-map organization, provides for rapid switching between display modes using simple decoding procedures. Only one bit needs be decoded to switch between two display modes. Where a small number m of display modes are to be selected from, only log 2  m bits need to be decoded at pixel scan rate. There is no need for repetitive multi-bit comparisons as are required in schemes where mode switching is controlled by run-length codes. 
     In FIG. 1 a flag line store RAM 40 is loaded with a line of subsampled F signal every p th  line retrace interval and is read out iteratively at pixel scan rate divided by q during the following p line trace intervals. That is, the F signal is subsampled p times less densely than Y signal in the direction perpendicular to line scan and is subsampled q times less densely than Y signal in the direction parallel to line scan. RAM 40 read-out is supplied with an output latch (not specifically shown) to control which set of input signals mode switch 16 selects as input signals to digital-to-analog converters 17-19. 
     A one-bit F signal from RAM 41 suffices to control mode switch 16 in selecting between two sets of Y, C 1  and C 2  signals. By way of example, assume mode switch 16 responds to a ZERO-valued F signal by selecting real-time Y signal from VRAM 4 and resampled C 1  and C 2  signals from interpolators 37 and 38 to be supplied as input signals to digital-to-analog converters 17-19. Mode switch 16 responds to a ONE-valued F signal from RAM 41, then, by selecting Y, C l  and C 2  output signals from map memories 24-26 to be supplied as input signals to converters 17-19. 
     FIG. 2 shows how one may store in VRAM 4 two frames of video information in which chrominance information and priority information are subsampled respective to luminance information. Here, F, C 1  and C 2  are each subsampled 2:1 in the direction of line trace and 2:1 in the direction perpendicular to line trace. 
     So, there are about one half as many F signal scan lines and about one half as many chrominance scan lines as luminance scan lines. More particularly, if there are a number (p+1) of chrominance scan lines, p being a positive integer, there are 2p+1 luminance scan lines. These are active scan lines and p is usually about 120 or 240 where kinescope 10 is in a conventional monitor. 
     The luminance samples in each of the two frames are arranged in respective bit-map-organizations in successive respective rows of VRAM 4. The number of luminance pixels times the number of bits per Y value for a luminance pixel is shown as being somewhat short of filling a row of VRAM 4. The lines of luminance samples are successively parallelly transferred to the parallel-to-serial buffering in VRAM 4 during successive line retrace intervals and transferred out of VRAM 4 serial output port 5 one at a time in real time during line trace intervals. 
     In each of the two frames the C 1 , C 2  and F signals are interleaved line by line and stored in bit-map-organizations in successive rows of VRAM 4, separate from the luminance bit-map-organizations. 
     C 1  and C 2  have as many bits per sample as Y-e.g., eight. So, each scan line in chrominance (C 1  or C 2 ) is one half as long in terms of numbers of bits as each scan line in luminance (Y). F signal, having only one bit per sampled one-quarter as densely as Y signal in the direction of scan lies, has only one-sixteenth as many samples per scan line as Y signal. One scan line each of the C 1 , C 2  and F signals fit within a row of VRAM 4. 
     In actual practice 4:1 subsampling of C 1 , C 2  and F signals in both horizontal and vertical directions is preferred. (This practice is not illustrated by drawing since it is difficult to illustrate within the space constraints in the drawing.) In such case, two scan lines of C 1 , C 2  and F signals may be fitted within a row of VRAM; and the value of p is reduced, to a value usually about 60 or 120 when kinescope 10 is in a conventional monitor. The parallel to serial buffering in VRAM 4 allows serial read-out through serial-access port 5 to proceed from any column address, and only that portion of VRAM 4 row including C 1  signal, C 2  signal and F signal scan lines of interest are read out during a selected line trace interval or selected line trace intervals, to write chroma line store RAMs 31 and 32 (or 33 and 34) and flag lines store after parsing into individual pixels in formatter 13. Except for the inclusion of F signal information this operation is similar to that described by Sprague et al. in U.S. Pat. No. 4,740,832. 
     A number of variants of the VRAM packing shown in FIG. 2 are possible. For example, the interleaving of lines of F, C 1  and C 2  data may not be used; and instead the bit-map organizations of F, C 1  and C 2  may be in separate sets of VRAM rows. 
     FIG. 3 shows a computer graphics system with a video display processor 150 that differs from that of the FIG. 1 computer graphics system. As in the FIG. 1 system, in one mode of operation map memories 24, 25 and 26 are retained as first Y map memory, first C 1  map memory and first C 2  map memory. Memories 24, 25 and 26 are addressed at full display resolution to generate digital Y, C 1  and C 2  signals for application to digital-to-analog converters 17, 18 and 19 respectively. In the other mode of operation, the FIG. 3 system differs from the FIG. 1 system. A second color map mode is employed in which a second Y map memory 41 is addressed at a sampling rate corresponding to full display resolution, and in which a second C 1  map memory 42 and a second C 2  map memory 43 are addressed at a subsampling rate corresponding to a reduced display resolution. During line trace intervals the second Y map memory 41 is supplied via data bus 27 at the sampling rate corresponding to full display resolution. 
     During selected line retrace intervals subsampled F signal data is loaded a line at a time into flag line store RAM 40 as in the FIG. 1 computer graphics system. Rather than having to store lines of subsampled C 1  and C 2  data in RAMs 31-34, lines of subsampled color map address information are stored in line store memories 44 and 45 instead. Line store memory 44, shown as a RAM, stores odd lines of subsampled color map address information. Line store memory 45, shown as a RAM stores even lines of subsampled color map address information. 
     During line trace intervals, F signal data are read-out of flag line store RAM 40 as in the FIG. 1 to control mode switch 16. Subsampled color map address information is read out from RAMs 44 and 45 at subsampled pixel scan rate. A multiplexer 46 permutes the order of the scan lines of subsampled color map address information at subsample scan rate to supply upper and lower lines of subsampled color map address information. These lines of subsampled color map address information are converted each to respective lines of subsampled C 1  and C 2  signals using the second C 1  map memory 42 and the second C 2  map memory 43 on a time-division-multiplex basis. Time-division multiplexing avoids the need for duplicating map memories 42 and 43 for the odd and even subsample lines. This time-division multiplexing is done using multiplexers 47-49 switching at twice the subsampling rate in the direction of line scan. The upper and lower lines of subsampled C 1  signal are supplied to the interpolator 37; and the upper and lower lines of subsampled C 2  signal are supplied to the interpolator 38. As in the FIG. 1 system, interpolators 37 and 38 supply to mode switch 16 C 1  and C 2  signals sampled at a rate corresponding to full display resolution. 
     FIG. 4 shows how one may store in VRAM 4 two frames of video information in which color map addressing information and priority information are subsampled. Here, F signal and the addressing for color map memories 42 and 43 are each subsampled at the same density respective to the addressing for Y map memory 41, one quarter so densely in both the direction parallel to scan lines and the direction perpendicular to scan lines. Both sets of map memory addresses are assumed to have the same number of bits e.g., eight. The number of memory 41 addresses per scan line times the number of bits per address is shown as being somewhat short of filling a row of VRAM 4, and four lines of memories 42 and 43 addressing plus four lines of F signal are shown as exactly filling a row of VRAM 4. 
     FIG. 5 shows a variant of the FIG. 1 graphics system that can be used if C 1  and C 2  are properly chosen and if the subsampling of F signal is the same as that of the C 1  and C 2  signals. C 1  and C 2  are chosen in such a way that the toggling of the least significant bit of C 2  results in imperceptible color change in the display on kinescope 10. This has been determined to be the case for C l  and C 2  being eight-bit descriptions of I and Q color-difference signals as used in NTSC color television broadcasting. This allows the least significant bit of C 2  to be supplied to a mode flag delay circuit 39 the output of which controls the state of selection in mode switch 16. In somewhat oversimplified terms, operation is as follows. When one wishes to write on kinescope 10 screen using the subsampled-chrominance operational mode, rather than the map-memory look-up mode, the least significant bit of C 2  is forced to be a ZERO. When one wishes to write on kinescope 10 screen using the map-memory look-up mode, C 2  is forced to be a ONE. 
     The choice of bit condition to flag each operational mode is largely arbitrary, but the choice indicated is advantageous in that white purity is determined solely by luminance (or Y) signal if the flag bits are admitted into interpolator 38. One may alternatively choose not to admit the least significant bit in each of the C 2  value applied pairwise to interpolator 38. If one does not apply the flag bits to interpolator 38, then which bit place the flag bit accompanying C2 appears in is not important. It may be in the most significant bit place, with C 2  being halved in amplitude in the digital code outputs of RAMs 32 and 34, for example. C 2  values are then multiplied by two in simple bit place shifts before interpolator 38. 
     Suppose the output of multiplexer 36, a bit of which is used as flag signal to control mode switch 16, sends interpolator 38 a scan line of samples that is earlier in the display raster scan than the scan line of samples the other output of multiplexer 36 sends to interpolator 38. The flag bit that indicates display mode is switched to using interpolators 37 and 38 will be included in the scan line where the mode switch is to occur. During the reading out of that line from one of the line store RAMs 33 and 34 and during the succeeding lines (e.g., the next three) the contents of those RAMs are re-read, the flag bit condition will switch the display mode in the same way. 
     On the other hand, suppose the flag bit is drawn from the scan line of samples that is later in the display scan. The flag bit that indicates display mode is switched will be included in the scan line next after the scan line where the mode switch is to occur. 
     When more than two display modes are to be switched among , in other embodiments of the invention the flag data can be encoded in a plurality of bits and subsampled in image memory. 
     There are other embodiments of the invention, which use respective dedicated memories for storing picture element variables in bit-map organizations in each of the plurality of formats available for display, and which use a dedicated memory for storing flag data in a bit-map organization that subsamples the bit-map organizations of picture element variables. The bit-map organizations are simultaneously raster scanned at their respective sampling densities. The sparsely sampled flag data are used to control display mode switching.