Abstract:
An apparatus includes a cascode amplifier and an electrostatic discharge (ESD) protection circuit. The cascode amplifier includes a common source device and a common gate device. The electrostatic discharge (ESD) protection circuit includes a device channel coupled between a drain and a gate of the common gate device. The device channel provides a short circuit between the drain and gate of the common gate device when the cascade amplifier is unbiased.

Description:
FIELD OF THE INVENTION 
     The present invention relates to electrostatic discharge (ESD) protection generally and, more particularly, to a method and/or apparatus for implementing an ESD protection circuit for cascode amplifiers. 
     BACKGROUND OF THE INVENTION 
     Based on extensive electrostatic discharge (ESD) testing, common gate field effect transistors (FETs) have been identified as a weak point of a differential cascode amplifier circuit. Common source FETs of the differential cascode amplifier circuit have reverse diode chains that offer effective ESD protection. An output of the differential cascode amplifier circuit is provided by drains of the common gate FETs. In typical applications, the output nodes can operate at 24 VDC. Typical ESD protection, such as diode chains or clamps, are not viable options. Because of the high voltage, many series diodes are needed, which takes up too much area on a chip. Conventional ESD clamps have large parasitics and degrade radio frequency (RF) performance. 
     It would be desirable to implement an ESD protection circuit for cascode amplifiers that avoids the above problems. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus including a cascode amplifier and an electrostatic discharge (ESD) protection circuit. The cascade amplifier includes a common source device and a common gate device. The electrostatic discharge (ESD) protection circuit includes a device channel coupled between a drain and a gate of the common gate device. The device channel provides a short circuit between the drain and gate of the common gate device when the cascade amplifier is unbiased. 
     The objects, features and advantages of the present invention include providing an ESD protection circuit for cascade amplifiers that may (i) be utilized with both single ended and balanced cascade topologies, (ii) use a modest amount of chip area, and/or (iii) protect drain-gate and/or source-gate junctions of common gate FETs of cascode amplifiers. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
         FIG. 1  is a diagram illustrating a differential cascode amplifier with an ESD protection circuit in accordance with an embodiment of the present invention; 
         FIG. 2  is a diagram illustrating a first operating mode of the cascode amplifier and ESD protection circuit of  FIG. 1 ; 
         FIG. 3  is a diagram illustrating a second operating mode of the cascode amplifier and ESD protection circuit of  FIG. 1 ; 
         FIG. 4  is a schematic diagram illustrating an example implementation of a two-stage differential cascode amplifier and ESD protection circuit in accordance with an embodiment of the present invention; 
         FIG. 5  is a diagram illustrating an example die layout for the two-stage differential cascode amplifier and ESD protection circuit of  FIG. 4 ; and 
         FIG. 6  is a diagram illustrating a single ended cascade amplifier with an ESD protection circuit in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to  FIG. 1 , a block diagram of a circuit  100  is shown illustrating a simplified example of a differential cascode amplifier with electrostatic discharge (ESD) protection in accordance with an embodiment of the present invention. In various embodiments, the circuit  100  comprises a block (or circuit)  102  and a block (or circuit)  104 . The block  102  generally implements a differential amplifier having a balanced cascade topology. The block  104  generally implements an ESD protection circuit in accordance with an embodiment of the present invention. 
     The block  102  may comprise a number of transistors Q 1 , Q 2 , Q 3 , and Q 4 . The transistors Q 1 , Q 2 , Q 3 , and Q 4  may be implemented as field effect transistors (FETs). In various embodiments, the transistors Q 1 , Q 2 , Q 3 , and Q 4  may comprise depletion mode FETs. In various embodiments, the transistors Q 1  and Q 2  are configured as common source FETs of the differential cascade amplifier  102 . The transistors Q 3  and Q 4  are configured as common gate FETs of the differential cascade amplifier  102 . Gate terminals of the transistors Q 3  and Q 4  are connected together to form a node (e.g., A). The node A may be connected to a voltage reference or a bias network (not shown). In some embodiments, the transistors Q 3  and Q 4  may have series gate resistors. 
     A first input node (e.g., E) of the differential cascade amplifier  102  may be connected to a gate of the transistor Q 1 . A second input node (e.g., F) of the differential cascade amplifier  102  may be connected to a gate of the transistor Q 2 . A source of the transistor Q 1  and a source of the transistor Q 2  are connected to a voltage supply ground potential. A drain of the transistor Q 1  is connected to a source of the transistor Q 3 . A drain of the transistor Q 2  is connected to a source of the transistor Q 4 . A drain of the transistor Q 3  may be connected to a first output node (e.g., B) of the differential cascode amplifier  102 . A drain of the transistor Q 4  may be connected to a second output node (e.g., C) of the differential cascode amplifier  102 . 
     The block  104  may comprise a number of transistors Q 5  and Q 6 . In various embodiments, the transistors Q 5  and Q 6  may be implemented as field effect transistors (FETs). The transistors Q 5  and Q 6  have a channel that is normally ON (low impedance) when no bias is applied to terminals (drain, gate, and source) of the transistors Q 5  and Q 6 . For example, the transistors Q 5  and Q 6  may comprise depletion mode FETs. The channel of the transistors Q 5  and Q 6  is OFF (high impedance) when a control terminal (gate) is biased at a lower (e.g., lower than threshold voltage) potential than the channel terminals (drain and source). In some embodiments, the transistors Q 5  and Q 6  may be implemented using multi-gate FETs to further reduce parasitics. 
     In various embodiments, a gate of the transistor Q 5  is connected to a gate of the transistor Q 6 , forming a node (e.g., D). In some embodiments, the transistors Q 5  and Q 6  may have series gate resistors. The node D may be held at a bias potential via an internal or external reference voltage. The reference voltage may be generated using a resistive voltage divider, other bias circuitry, or a voltage source (not shown). The reference voltage is provided only when the amplifier is operating in a normally biased mode (or similar powered ON mode), an example of which is illustrated in  FIG. 2 . 
     In various embodiments, the block  104  is connected in such a way as to protect a drain gate junction and/or a source gate junction of the common gate transistors (e.g., transistors Q 3  and Q 4 ) of the block  102  from electrostatic discharge (ESD) damage. Protection of the transistor Q 3  from ESD energy between the nodes A and B is generally provided by the transistor Q 5 . A drain of the transistor Q 5  is connected to the output node B of the differential cascade amplifier  102 , which is also connected to the drain of the transistor Q 3 . A source of the transistor Q 5  is connected to the node A, which is also connected (often through a series resistor) to the gate of the transistor Q 3 . Protection of the transistor Q 4  from ESD energy between the nodes A and C is generally provided by the transistor Q 6 . A drain of the transistor Q 6  is connected to the output node C of the differential cascode amplifier  102 , which is also connected to the drain of the transistor Q 4 . A source of the transistor Q 6  is connected to the node A, which is also connected (often through a series resister) to the gate of the transistor Q 4 . 
     Referring to  FIG. 2 , a diagram is shown illustrating a first operating mode of the cascode amplifier and ESD protection circuit of  FIG. 1 . During operation of the circuit  100  in a first (e.g., normally biased) mode, the node D is held at a lower voltage than the nodes A, B, and C to ensure that transistors Q 5  and Q 6  are in an OFF state (e.g., deeply pinched off). In the OFF state the transistors Q 5  and Q 6  present a high impedance to the circuit  102 . The node D may be held at the lower potential via an internal or external reference voltage. The reference voltage may be generated using a resistive voltage divider, other bias circuitry, or a voltage source (not shown). The reference voltage is provided only when the amplifier is in the normally biased operating mode (or similar powered ON mode). In some embodiments, the transistors Q 5  and Q 6  have an offset gate (e.g., a gate that is closer to the source than to the drain). The offset gate reduces parasitic capacitance from the drain to the gate (e.g., Cgd), and minimizes degradation of performance of the output node B by the transistor Q 5  and the output node C by the transistor Q 6 . 
     Referring to  FIG. 3 , a diagram is shown illustrating a second operating mode of the cascade amplifier and ESD protection circuit of  FIG. 1 . When the circuit  100  is in a second (e.g., un-biased or un-powered) mode (e.g., such as during handling, assembly, etc.), the voltages on the nodes A, B, and D are generally equivalent (e.g., substantially equal) and the transistors Q 5  and Q 6  are in an ON state. Under this condition, the transistor Q 5  presents a low impedance path between the nodes A and B, and the transistor Q 6  presents a low impedance path between the nodes A and C. Any ESD energy will take the low impedance path through the transistors Q 5  and Q 6  instead of through the drain gate junction and/or source gate junction of the transistors Q 3  and Q 4 , respectively, thus protecting the transistors Q 3  and Q 4  from ESD damage. 
     Protection of transistors Q 3  and Q 4  from ESD energy between the nodes B and C is provided also by the transistors Q 5  and Q 6  as follows. During operation of the circuit  100  in the normally biased mode, the node D is held at a lower voltage than the node A, the node B, and the node C. Under this condition, the transistors Q 5  and Q 6  are in the OFF state and present a high impedance between the output nodes B and C of the circuit  100 . When the circuit  100  is un-biased or un-powered, the voltages on the nodes A, B, C and D are substantially equal and the transistors Q 5  and Q 6  are in the ON state. Under this condition, the transistors Q 5  and Q 6  provide a low impedance path between the output nodes B and C. ESD energy will take the low impedance path through the transistors Q 5  and Q 6 , instead of going through the transistors Q 1 , Q 2 , Q 3  and Q 4 , thus protecting the transistors Q 1 , Q 2 , Q 3  and Q 4  from ESD damage. 
     Referring to  FIG. 4 , a schematic diagram of a circuit  200  is shown illustrating an example implementation of a two-stage differential cascode amplifier and ESD protection circuit in accordance with an embodiment of the present invention. The circuit  200  comprises a block (or circuit)  202 , a block (or circuit)  204 , and a block (or circuit)  206 . The block  202  generally implements a first (or input) stage of the two-stage differential cascode amplifier. The block  204  generally implements a second (or output) stage of the two-stage differential cascode amplifier. The block  206  generally implements an ESD protection circuit in accordance with an embodiment of the present invention. The ESD protection circuit  206  is connected to the output stage (stage two)  204  of the two-stage differential cascode amplifier. 
     In various embodiments, the block  202  may implement a common source topology amplifier stage comprising a FET Q 7 , a FET Q 8 , a number of resistors R 1 -R 12 , a number of capacitors C 1 -C 6 , and a number of diodes D 1 -D 6 . The block  204  may implement a balanced cascode topology amplifier stage similar to the cascode topology of the circuit  100 . For example, the block  204  may comprise a FET Q 11 , a FET Q 12 , a FET Q 13 , a FET Q 14 , a number of resistors R 13 -R 29 , a number of capacitors C 7 -C 13 , and a number of diodes D 7 -D 12 . The FET Q 11  and the FET Q 12  may be configured as the common source transistors (e.g., similar to the FETs Q 1  and Q 2  in  FIG. 1 ). The FET Q 13  and the FET Q 14  may be configured as the common gate transistors (e.g., similar to the FETs Q 3  and Q 4  in  FIG. 1 ). 
     The block  206  generally comprises a pair of FETs Q 15  and Q 16 . The FETs Q 15  and Q 16  may be configured similarly to the FETs Q 5  and Q 6  of  FIG. 1 . For example, the FETs Q 15  and Q 16  are connected to the common gate transistors, Q 13  and Q 14 , respectively, of the block  204 . In this example, the gates of the transistors Q 15  and Q 16  are connected together (e.g., through gate resistors R 30  and R 31 ) as the node D of the ESD protection circuit, and the node D is connected (e.g., via a resistor R 32 ) to a ground reference of the second stage block  204 . The ground reference of the second stage block  204  may or may not be the same as the ground reference of the first stage block  202 . 
     The gates of the transistors Q 13  and Q 14  are connected together (e.g., through gate resistors R 16  and R 26 ) forming the node A, which is biased internally using a resistive divider circuit (e.g., R 17 , R 20 , R 21 , R 22 , R 27 , R 29 ). The FETs Q 7 , Q 8 , Q 11 , and Q 12  are protected from ESD strikes using traditional diode chains (e.g., D 1 -D 3 , D 4 -D 6 , D 7 -D 9 , D 10 - 12 , respectively) between the respective gates and sources. Since the voltage difference between the gate and source nodes is typical less than 1 volt, few diodes are needed. The voltage difference between the drain and gate nodes of the transistors Q 13  and Q 14  could be as high as 10 volts or more, protection of which would take a large number of diodes and would take up a significantly larger die area. 
     Referring to  FIG. 5 , a diagram is shown illustrating a representation of an example die layout  300  for the two-stage differential cascode amplifier and ESD protection circuit of  FIG. 4 . The two-stage differential cascade amplifier and ESD protection circuit in accordance with an embodiment of the present invention may be fabricated as a monolithic microwave integrated circuit (MMIC) having a die layout similar to the layout  300 . The two-stage differential cascode amplifier circuit with the ESD protection circuit in accordance with embodiments of the present invention generally demonstrates a higher ESD rating for the output nodes B and C when compared to a similar circuit without the ESD protection circuit. In some embodiments, the die layout  300  may use a 500 μm FET for the transistors Q 15  and Q 16 , while the amplifier FETs Q 11 , Q 12  and Q 13 , Q 14  may be implemented with 1100 μm and 1650 μm FETs, respectively. Protection from an ESD level greater than 700V on nodes B and C may be realized using the die layout  300 , as compared to 350V without the ESD protection circuit in accordance with embodiments of the present invention. A higher ESD level could be achieved with further optimization of the FET periphery and layout geometry. As illustrated in  FIG. 5 , the ESD protection circuit takes up minimal die area. 
     Referring to  FIG. 6 , a circuit  400  is shown illustrating a simplified single-ended cascode amplifier and ESD protection circuit in accordance with an embodiment of the invention. The single-ended cascode amplifier may comprise a transistor Q 20  and a transistor Q 21 . The transistors Q 20  and Q 21  may be implemented as field effect transistors (FETs). In various embodiments, the transistors Q 20  and Q 21  may comprise depletion mode FETs. However, other types of devices (e.g., enhancement mode FET, JFET, etc.) may be implemented accordingly to meet the design criteria of a particular implementation. 
     In various embodiments, the transistors Q 20  and Q 21  are configured as a common source FET and a common gate FET, respectively, of the single-ended cascade amplifier  400 . A gate terminal of the transistor Q 21  forms a node (e.g., A). The node A may be connected to a voltage reference or a bias network (not shown). In some embodiments, the transistor Q 21  may have a series gate resistor. An input node (e.g., E) of the single-ended cascade amplifier  400  may be connected to a gate of the transistor Q 20 . A source of the transistor Q 20  is connected to a voltage supply ground potential. In some embodiments, the source of the transistor Q 20  may be connected to the ground potential through a resistor. A drain of the transistor Q 20  is connected to a source of the transistor Q 21 . A drain of the transistor Q 21  is connected to an output node (e.g., B) of the single-ended cascade amplifier  400 . 
     In various embodiments, the transistor Q 22  may be implemented as a field effect transistor (FET). The transistors Q 22  has a channel that is normally ON (low impedance) when no bias is applied to respective terminals (drain, gate, and source) of the transistor Q 22 . For example, the transistor Q 22  may comprise a depletion mode FET. The channel of the transistor Q 22  is OFF (high impedance) when a control terminal (gate) is biased at a lower (e.g., lower than threshold voltage) potential than the channel terminals (drain and source). In some embodiments, the transistor Q 22  may be implemented using a multi-gate FET to further reduce parasitics. 
     In various embodiments, a gate of the transistor Q 22  forms a node (e.g., D) of the ESD protection circuit. The node D may be held at a bias potential via an internal or external reference voltage. The reference voltage may be generated using a resistive voltage divider, other bias circuitry, or a voltage source (not shown). The reference voltage is provided only when the amplifier  400  is operating in a normally biased mode (or similar powered ON mode). In some embodiments, the transistors Q 22  may have a series gate resistor. 
     In various embodiments, the transistor Q 22  is connected in such a way as to protect a drain gate junction and/or a source gate junction of the transistor Q 21  from electrostatic discharge (ESD) damage. Protection of the transistor Q 21  from ESD energy between the nodes A and B is generally provided by the transistor Q 22 . A drain of the transistor Q 22  is connected to the output node B of the cascode amplifier  400 , which is also connected to the drain of the transistor Q 21 . A source of the transistor Q 22  is connected to the node A, which is also connected (often through a series resistor) to the gate of the transistor Q 21 . The circuit  400  comprising the single-ended cascode amplifier and ESD protection circuit in accordance with an embodiment of the present invention may be fabricated as a monolithic microwave integrated circuit (MMIC). 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.