Abstract:
The present invention provides a low cost carrier tape designed to store chips during transportation. The invention comprises a carrier tape which contains receptacle holes designed to secure chips onto the carrier tape by clasping onto the chip&#39;s electrical contacts. The receptacle holes prevent the chip from rotating and physically moving. The receptacle holes are formed in patterns to match the standardized electrical contact patterns of flip chip families. The diameters of the receptacle holes may be sized slightly smaller than the diameter of electrical contacts such that a chip is secured by “snap-fitting” each electrical contact into a receptacle hole. Relief slits may be formed on the edges of the receptacle holes to facilitate the “snap-fitting” of electrical contacts into receptacle holes.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to semiconductor devices, and more specifically, to a universal carrier tape for transporting semiconductor devices. 
     BACKGROUND 
     Semiconductor integrated circuits (IC&#39;s) are typically fabricated in wafer form. After fabrication, the individual chips are scribed from the wafer and then undergo numerous processing and handling steps before they are tested and packaged. One type of common chip package, known as a “flip chip,” is a package having electrical contacts extending outwardly from the bottom surface of the package. Flip chip packages are manufactured in many different sizes. However, flip chips can be grouped into a number of families wherein each family has electrical contacts formed in a standardized pattern. 
     A carrier tape and reel assembly is typically used to transport the flip chips to the individual manufacturing stations for processing and testing. The carrier tape and reel assembly includes a carrier tape having a plurality of cavities designed to hold flip chips. Generally, there is nothing in the cavity to secure the chip. As a result, the chip may rotate or physically move within the cavity. If the chip rotates, an automated machine may pick up and place the device in the wrong orientation on a test machine or on a printed circuit board. A severe physical disturbance may damage the chip, thereby causing it to be unfit for use or causing a system utilizing the chip to malfunction. 
     To avoid these problems, the size of the cavity is customized for each flip chip package size. This tends to be expensive, particularly for semiconductor manufacturers which produce flip chips having many different package sizes. Sometimes, semiconductor manufacturers seal the chips within the cavities using a cover tape. Utilizing the cover tape material and implementing the extra steps to attach and remove the cover tape, however, increases the cost and complexity of transporting and handling the chips. Another method of securing the flip chips is through adhering the chip to adhesive tape placed on the bottom surface of the cavity. However, the adhesive substance may cause contamination of the electrical contacts on the chip as well as increase the cost and complexity of handling the devices. 
     In view of the foregoing, a low cost carrier tape that securely holds and protects flip chips, but that does not require the use of either cover tape or adhesive tape would be desired. 
     SUMMARY 
     The present invention provides a low cost carrier tape designed to store chips during transportation. The invention comprises a carrier tape which contains receptacle holes designed to secure chips onto the carrier tape by clasping onto the chip&#39;s electrical contacts. The receptacle holes are formed in patterns to match the standardized electrical contact patterns of each flip chip family. 
     The receptacle holes prevent the flip chip from rotating and physically moving. Preventing rotation ensures proper orientation of the flip chip in the testing and manufacturing processes. Preventing physical movement reduces the chance of damage occurring to the flip chip. Preventing rotation and physical movement makes the use of cover tape or adhesive tape unnecessary. This reduces the cost and complexity of the transportation process, as well as avoids possible contamination of the electrical contacts on the flip chips. Additionally, cavity sizes do not need to be customized to chip package sizes within each family of flip chips since the receptacle hole patterns are created to match the contact patterns of specific flip chip families. This further reduces the cost of transporting flip chips. In sum, this invention provides a more cost effective, more secure and contamination-free method for transporting flip chips. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention, together with further advantages thereof, may best be understood by reference to the following detailed description taken in conjunction with the accompanying drawings in which: 
     FIG. 1A is a perspective view of one embodiment of the carrier tape of the subject invention. 
     FIG. 1B is a cross-sectional view of the carrier tape of FIG.  1 A. 
     FIG. 1C is a top-plan view of an embodiment of the carrier tape in FIG. 1A wherein relief slits are formed the edges of the receptacle holes. 
     FIG. 2 is a top-plan view of an embodiment of the carrier tape having an alternative pattern of receptacle holes. 
     FIG. 3 is a top-plan view of an embodiment of the carrier tape having a single receptacle hole. 
     FIG. 4A is a perspective view of an alternative embodiment of the carrier tape wherein the receptacle holes are formed within cavities. 
     FIG. 4B is a cross-sectional view of the carrier tape in FIG.  4 A. 
     FIG. 4C is a top-plan view of the carrier tape in FIG.  4 A. 
     FIG. 5A is a perspective view of an alternative embodiment of the carrier tape wherein a continuous recessed region is formed along the longitudinal axis of the carrier tape. 
     FIG. 5B is cross-sectional view of the carrier tape of FIG.  5 A. 
     FIG. 5C is a top-plan view of the carrier tape of FIG.  5 A. 
     FIG. 6 is a cross-sectional view of an embodiment of the carrier tape in FIG. 1A which includes bottom ridges. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order to not unnecessarily obscure the present invention. 
     FIG. 1A illustrates a universal carrier tape  10  according to one embodiment of the invention. Carrier tape  10  is formed from a flexible material which may include, but is not limited to plastic or rubber. Formed on the surface of the carrier tape  10  are sets of receptacle holes  18 . The receptacle holes  18  secure chips  22  to the carrier tape by receiving and clasping onto electrical contacts located on the bottom surface of the chips. In this embodiment of the invention, each receptacle hole is sufficiently sized to receive a single electrical contact. The illustrated pattern of receptacle holes has eight receptacle holes which create an outline of a square. As may be appreciated by those of ordinary skill in the art, receptacle holes  18  may be formed in a variety of patterns, shapes and sizes, one of which is shown in FIG. 1A for purposes of illustration. Also included on the surface of tape  10  are a series of index holes  20  each associated with a set of receptacle holes  18 . The index holes  20  allow testing and packaging machines to guide the carrier tape  10  through chip processing steps. The distance between adjacent receptacle holes within a set is referred to as the “pitch” of the receptacle holes. It should be apparent that the invention may be used with devices having a wide variety of different pitches. By way of example, the invention works well with devices having pitches in the range of 0.4 to 1.0 mm (which are typical of the state of the art at the time of this writing). For example, pitches of approximately 1.0, 0.8, 0.75, 0.5, and 0.4 mm are common pitches in current BGA and flip chip devices. 
     FIG. 1B illustrates the cross-sectional view of the carrier  10  of FIG. 1A with a chip  22  attached to the carrier tape. Chip  22  takes the form of a packaged integrated circuit having electrical contacts  24  formed on the bottom surface thereof. In the embodiment shown, the electrical contacts  24  are balls. The lower portion of the balls have a somewhat spherical shape and thereby have an upper constricted portion (adjacent the package) that has a width less than a maximum diameter  23  of the ball. 
     In the illustrated embodiment of the invention as shown in FIG. 1B, each receptacle hole  18 , having a diameter  13 , is positioned to receive and clasp onto a single electrical contact  24  which is substantially spherical in shape. Additionally, the diameters  13  of the receptacle holes  18  are sized slightly smaller than a maximum diameter  23  of each electrical contact  24 . The chip  22  is secured to the carrier tape  10  by “snap-fitting” each electrical contact  24  into a respective receptacle hole  18 . A “snap-fit” is implemented by applying sufficient force to the chip  22  so that the electrical contacts  24  stretch open the receptacle holes  18  so to permit the maximum diameter  23  of the electrical contacts  24  to pass through the thickness of the carrier tape  10 . The receptacle hole  18  returns to its initial size after the electrical contacts  24  are fully inserted. In a preferred embodiment, as can be seen in the top-plan view of carrier tape  10  in FIG. 1C, a plurality of relief slits  26  are formed on the edges of receptacle holes  18 . Relief slits  26  facilitate “snap-fitting” electrical contacts  24  into respective receptacle holes  18  by relieving surface tension at the edges of the receptacle holes  18  during insertion of electrical contacts  24 . As can be appreciated by those of ordinary skill in the art, the number, shape and size of the relief slits formed around each receptacle hole can vary. It can also be appreciated that receptacle holes formed without relief slits can receive and secure electrical contacts in an effective manner. 
     In another embodiment of the invention, a chip  22  is secured to the carrier tape  10  by inserting each electrical contact  24  into a receptacle hole  18  which has a slightly smaller diameter than the diameter of the electrical contact  24 . In contrast to the “snap-fit,” in this embodiment of the invention each electrical contact  24  is secured in a receptacle hole through the frictional contact between the edge of receptacle hole and the electrical contact. As can be appreciated by those in the art, a cylindrically-shaped electrical contact can also be inserted and secured by the frictional force applied by the receptacle hole edges. 
     FIG. 2 illustrates an embodiment having an alternative pattern of receptacle holes. In this embodiment, receptacle holes  50  and  52  are formed in a parallel fashion and receptacle holes  54  and  56  are formed in between and adjacent to the ends of receptacle holes  50  and  52 . Receptacle holes  50  and  52  are each designed to secure multiple electrical contacts of a chip and receptacle holes  54  and  56  are each designed to secure one electrical contact of a chip. As may be appreciated by those of ordinary skill in the art, the receptacle holes may be formed in many various patterns, shapes and sizes and each receptacle-hole may receive and secure one or more electrical contacts. The techniques of “snap-fitting” the electrical contacts of a chip into the receptacle holes may be implemented and relief slits may be used in this embodiment of the invention. To implement “snap-fitting” in receptacle holes  50  and  52 , each of these receptacle holes must be sized slightly smaller than the path encircling the respective group of electrical contacts  24 , about their maximum diameters, which are to be secured. 
     FIG. 3 illustrates another embodiment of an alternative pattern of receptacle holes  18  wherein a single receptacle hole is designed to receive all of the contacts of a chip. The single receptacle hole  18  has a generally rectangular outline wherein the corners are round in shape. The chip is secured through the frictional force created at the points of contact between the electrical contacts and the edges of the receptacle hole. As illustrated in FIG. 3, the receptacle hole  18  may secure an extra-small chip  22  having four electrical contacts  24  formed in a square shaped pattern. In various embodiments, a chip with more or less than four electrical contacts may also be secured by a single receptacle hole  18  so long as the amount of contact between the electrical contacts and the edges of the receptacle hole provide a minimum amount of frictional force to secure and prevent the rotation of the chip within the cavity. As may be appreciated by those of ordinary skill in the art, the outline of the receptacle hole  18  may vary so long as receptacle hole  18  may receive all the electrical contacts of a chip. The techniques of “snap-fitting” the electrical contacts of a chip into the receptacle holes may be implemented and relief slits may be used in this embodiment of the invention. 
     FIG. 4A illustrates a universal carrier tape  10  according to an alternative embodiment of the invention. Carrier tape  10  includes a series of cavities  12  formed in the longitudinal direction along carrier tape  10 . Also included on the surface of tape  10  are a series of index holes  20  each associated with a cavity  12 . In one embodiment of the invention, each cavity  12  is substantially rectangular and includes four side surfaces  14  and a bottom surface  16 . As will be appreciated by those of skill in the art, index holes  20  and cavities  12  may be formed as is known in the art. Formed on the bottom surface  16  of each cavity  12  are one or more receptacle holes  18 . Since the receptacle holes  18  receive and clasp the electrical contacts located on the bottom surface of chips  22 , the chips  22  are secured within the cavities  12 . As may be appreciated, the receptacle holes  18  within the cavities  12  may be formed in a variety of patterns, shapes and sizes, one of which is shown in FIG. 4A for purposes of illustration. 
     FIG. 4B shows the cross-sectional view of the carrier tape  10  of FIG. 4A with a chip  22  inserted in a cavity  12 . In the illustrated embodiment of the invention as shown in FIG. 4B, each receptacle hole  18 , having a diameter  13 , is positioned to receive and clasp onto a single electrical contact  24  which is substantially spherical in shape. In this embodiment, as can be seen in the top-plan view of carrier tape  10  in FIG. 4C, a plurality of relief slits  26  are formed on the edges of receptacle holes  18 . As can be appreciated by those of ordinary skill in the art, the number, shape and size of the relief slits formed around each receptacle hole can vary. It can also be appreciated that the method of “snap-fitting” the electrical contacts  24  into the receptacle holes  18  may also be utilized in this embodiment of the invention. 
     FIG. 5A illustrates another alternative embodiment of the universal carrier tape  10 . In this embodiment, a continuous recessed region is formed along the longitudinal axis of the carrier tape  10 . Receptacle holes  18  are formed on the bottom surface  16  of the continuous recessed region. The index holes  20  are formed on one of the two upper flanges  17  of the carrier tape  10 . FIG. 5B illustrates the cross-sectional view of the carrier tape  10  of FIG. 5A with a chip  22  secured to the bottom surface  16  of the continuous recessed region. FIG. 5C illustrates the top-plan view of the carrier tape  10  of FIG.  5 A. The techniques of “snapfitting” the electrical contacts of a chip into the receptacle holes may be implemented and relief slits may be used in this embodiment of the invention. 
     FIG. 6 illustrates a cross-sectional view of an alternative embodiment of the carrier tape  10  of FIG. 1A wherein portions of the carrier tape are extended past the exposed ends of the electrical contacts  24 . The extended portions, forming bottom ridges  28 , are useful in protecting the electrical contacts  24  from contact with foreign objects. In this manner, the carrier tape  10  can be laid on a flat surface with the electrical contacts  24  remaining free from any physical contact. As can be appreciated by those in the art, the bottom ridges  28  can be formed in a variety of configurations, shapes and sizes. Additionally, the bottom ridges  28  may be formed on a variety of carrier tape  10  embodiments. For example, the bottom ridges  28  may be formed on the bottom surfaces of cavities or continuous recessed regions which may be formed within the carrier tape. 
     While this invention has been described in terms of several preferred embodiments, there are alterations, permutations and equivalents which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the apparatuses of the present invention. For example, the carrier tape  10  can have a width sufficient to contain multiple rows of cavities  12 . It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations and equivalents as fall within the true spirit and scope of the present invention.