Abstract:
A manufacturing method of a semiconductor package includes the follow steps. Firstly, a carrier is provided. Then, a package substrate is formed. Then, a first electronic component is disposed above the second conductive layer of the package substrate. Then, a second package body encapsulating the first electronic component and the second conductive layer is formed. Then, the carrier is carried. Wherein in the step of forming the package substrate includes a step of forming a first conductive layer on the carrier, a step of forming a first pillar layer on the first conductive layer, a step of forming a first package body encapsulating the first conductive layer and the first pillar layer and a step of forming a second conductive layer on the first pillar layer.

Description:
[0001]    This application is a continuation application (CA) of U.S. application Ser. No. 15/162,760, filed on May 24, 2016, which claims the benefit of U.S. Provisional application, No. 62/221,262 filed on Sep. 21, 2015, the contents of which are incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The invention relates to a manufacturing method of a semiconductor package and a manufacturing method of a semiconductor device, and more particularly to a manufacturing method of a thin semiconductor package and a manufacturing method of a thin semiconductor device. 
       BACKGROUND OF THE INVENTION 
       [0003]    In the electronics industry, high integration and multiple functions with high performance become essential for new products. And meanwhile, high integration may cause higher manufacturing cost, since the manufacturing cost is in proportional to its size. Therefore, demanding on miniaturization of integrated circuit (IC) packages has become more and more critical. 
         [0004]    Package-on-package (PoP) is now the fastest growing semiconductor package technology since it is a cost-effective solution to high-density system integration in a single package. In a PoP structure, various packages are integrated in a single semiconductor package to reduce the size. Accordingly, there exists a need to provide a semiconductor package to overcomes, or at least reduces the above-mentioned problems. 
         [0005]    Therefore, it is important to increase the performance of the 3D graphic processing circuit while reducing the consumption of the electric power and extending the operating time of the mobile device. 
       SUMMARY OF THE INVENTION 
       [0006]    In another embodiment of the invention, a manufacturing method of a semiconductor package is provided. The manufacturing method includes the following steps. A carrier is provided; a package body is formed and includes the steps of forming a first conductive layer on the carrier, forming a first pillar layer on the first conductive layer, forming a first package body encapsulating the first conductive layer and the first pillar layer, and forming a second conductive layer on the first pillar layer; a first electronic component is disposed above the second conductive layer of the package substrate; a second package body encapsulating the first electronic component and the second conductive layer is formed, and the carrier is removed. 
         [0007]    In another embodiment of the invention, a manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A carrier is provided; a package body is formed and includes the steps of forming a first conductive layer on the carrier, forming a first pillar layer on the first conductive layer, forming a first package body encapsulating the first conductive layer and the first pillar layer, and forming a second conductive layer on the first pillar layer; a first electronic component is disposed above the second conductive layer of the package substrate; a second package body encapsulating the first electronic component, the second conductive layer and the second pillar layer is formed, and the carrier is removed. 
         [0008]    Numerous objects, features and advantages of the invention will be readily apparent upon a reading of the following detailed description of embodiments of the invention when taken in conjunction with the accompanying drawings. However, the drawings employed herein are for the purpose of descriptions and should not be regarded as limiting. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The above objects and advantages of the invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
           [0010]      FIG. 1  illustrates a diagram of a semiconductor package according to an embodiment of the invention; 
           [0011]      FIG. 2  illustrates a diagram of a semiconductor package according to another embodiment of the invention; 
           [0012]      FIG. 3  illustrates a diagram of a semiconductor package according to another embodiment of the invention; 
           [0013]      FIG. 4  illustrates a diagram of a semiconductor package according to another embodiment of the invention; 
           [0014]      FIG. 5  illustrates a diagram of a semiconductor package according to another embodiment of the invention; 
           [0015]      FIG. 6  illustrates a diagram of a semiconductor device according to one embodiment of the invention; 
           [0016]      FIG. 7  illustrates a diagram of a semiconductor device according to another embodiment of the invention; 
           [0017]      FIGS. 8A to 8H  illustrate manufacturing processes of the semiconductor package of  FIG. 1 ; 
           [0018]      FIGS. 9A to 9B  illustrate manufacturing processes of the semiconductor package of  FIG. 2 ; 
           [0019]      FIGS. 10A to 100  illustrate manufacturing processes of the semiconductor package of  FIG. 3 ; 
           [0020]      FIGS. 11A to 11H  illustrate manufacturing processes of the semiconductor package of  FIG. 4 ; and 
           [0021]      FIGS. 12A to 120  illustrate manufacturing processes of the semiconductor package of  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0022]      FIG. 1  illustrates a diagram of a semiconductor package  100  according to an embodiment of the invention. The semiconductor package  100  includes a package substrate  110 , a first electronic component  120 , a second package body  130 , a second electronic component  140  and at least one conductive contact  150 . 
         [0023]    The package substrate  110  includes a first conductive layer  111 , a first pillar layer  112 , a first package body  113  and a second conductive layer  114 . 
         [0024]    The first conductive layer  111  includes a plurality of elements  1111 , such as pads, traces or combination thereof. Each element  1111  has a first lower surface  1111   b  and a first lateral surface  1111   s , and the first package body  113  has a second lower surface  113   b . The first lower surface  1111   b  is exposed from the second lower surface  113   b , and the first lower surface  1111   b  is aligned with the second lower surface  113   b . Each element  1111  may be a multi-layered structure or single-layered structure. For example, each element  1111  includes nickel layer, gold layer, palladium layer, copper layer or combination thereof. 
         [0025]    The first pillar layer  112  connects the first conductive layer  111  to the second conductive layer  114 . In the present embodiment, the first pillar layer  112  includes a plurality of pillars  1121 . The pillars  1121  are made of a material such as copper. Each pillar  1121  has a first upper surface  1121   u , and the first package body  113  has a second upper surface  113   u , wherein the first upper surface  1121   u  is exposed from the second upper surface  113   u  and aligned with the second upper surface  113   u.    
         [0026]    The first package body  113  encapsulates the first conductive layer  111  and the first pillar layer  112 . For example, the first package body  113  encapsulates the first lateral surface  1111   s  of the first conductive layer  111  and the lateral surface of each pillar  1121 . 
         [0027]    The first package body  113  may be a molding compound which is made of a material including, for example, a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. Suitable fillers also can be included, such as powdered SiO 2 . 
         [0028]    Since the first package body  113  is the molding compound, the package substrate  110  has thin thickness t 1 . Compared to the silicon substrate, the thickness t 1  of the package substrate  110  is much smaller. In general, the silicon substrate has a thickness larger than 100 micrometers. In the present embodiment, the thickness t 1  of the package substrate  110  is smaller, and accordingly the thickness t 2  of the semiconductor package  100  may be reduced. 
         [0029]    The second conductive layer  114  includes a plurality of elements  1141 , such as pads, traces or combination thereof. Each element  1141  may be a multi-layered structure or single-layered structure. For example, the element  1141  may be nickel layer, gold layer, copper layer, palladium layer or combination thereof. 
         [0030]    In the present embodiment, the first electronic component  120  is coupled to the second conductive layer  114  of the package substrate  110  in a “face-down” orientation and electrically connected to the second conductive layer  114  via a plurality of conductive contacts  121 . This configuration is sometimes referred to as “flip-chip”. The conductive contact  121  may be solder ball, conductive pillar, etc. 
         [0031]    In other embodiments, the first electronic component  120  may be coupled to the package substrate  110  in a “face-up” orientation, and electrically connected to the package substrate  110  via a plurality of conductive bond wires (not shown). The first electronic component  120  may be an active chip or a passive component, such as a resistor, an inductor or a capacitor. In another embodiment, the number of the first electronic component  120  may be several. In addition, the first electronic component  120  may be, for example, a chip, a passive component, etc. 
         [0032]    The second package body  130  formed on the second upper surface  113   u  of the package substrate  110  encapsulates the second conductive layer  114  and the first electronic component  120 . The second package body  130  may be made of a material which is the same as that of the first package body  113 . 
         [0033]    The second electronic component  140  is disposed on the first lower surface  1111   b  of the first substrate  110  and electrically connects to the first conductive layer  111 . In one embodiment, the second electronic component  140  is, for example, passive component, such as a resistor, an inductor or a capacitor. 
         [0034]    The conductive contacts  150  are disposed on the first lower surface  1111   b  of the first substrate  110 . The semiconductor package  100  is disposed on and electrically connected to an exterior circuit, such as a circuit board, through the conductive contacts  150 . The conductive contacts  150  may be solder ball, conductive pillar, etc. 
         [0035]      FIG. 2  illustrates a diagram of a semiconductor package  200  according to another embodiment of the invention. The semiconductor package  200  includes the package substrate  110 , the first electronic component  120 , the second package body  130 , the second electronic component  140 , at least one conductive contact  150 , a second pillar layer  260  and an interposer  270 . 
         [0036]    The second package body  130  further encapsulates the second pillar layer  260 . The second pillar layer  260  includes a plurality of pillars  261  connecting the second conductive layer  114  to the interposer  270 . 
         [0037]    The interposer  270  is disposed on the second package body  130  and electrically connects to the package substrate  110  through the second pillar layer  260  encapsulated within second package body  130 . The interposer  270  may be electrically connected to the first electronic component  120  through the second pillar layer  260  and the package substrate  110 . 
         [0038]    Each pillar  261  has a third upper surface  261   u , and the second package body  130  has a fourth upper surface  130   u , wherein the third upper surface  261   u  is exposed from the fourth upper surface  130   u  and aligned with the fourth upper surface  130   u.    
         [0039]      FIG. 3  illustrates a diagram of a semiconductor package  300  according to another embodiment of the invention. The semiconductor package  300  includes the package substrate  110 , the first electronic component  120 , the second package body  130 , the second electronic component  140 , at least one conductive contact  150 , the second pillar layer  260  and a fourth conductive layer  370 . 
         [0040]    The second package body  130  encapsulates the second conductive layer  114 , the second pillar layer  260  and the fourth conductive layer  370 . 
         [0041]    The second pillar layer  260  electrically connects the second conductive layer  114  to the fourth conductive layer  370 , such that the first electronic component  120  may electrically connect the fourth conductive layer  370  through the package substrate  110  and the second pillar layer  260 . 
         [0042]    The fourth conductive layer  370  includes a plurality of elements  371 , such as pads, traces or combination thereof. Each element  371  has a fifth upper surface  371   u , and the second package body  130  has the fourth upper surface  130   u , wherein the fifth upper surface  371   u  is exposed from the fourth upper surface  130   u  and aligned with the fourth upper surface  130   u.    
         [0043]    Each element  371  may be a multi-layered structure or single-layered structure. For example, the each element  371  includes nickel layer, gold layer, palladium layer, copper layer or combination thereof. 
         [0044]    The fourth conductive layer  370  is embedded in the second package body  130 . For example, each element  371  (trace or pad) has a second lateral surface  371   s  which is encapsulated by the second package body  130 . Since the fourth conductive layer  370  is embedded in the second package body  130 , the second package body  130  has a thin thickness t 3 . 
         [0045]      FIG. 4  illustrates a diagram of a semiconductor package  400  according to another embodiment of the invention. The semiconductor package  400  includes a package substrate  410 , the first electronic component  120 , the second package body  130 , the second electronic component  140 , at least one conductive contact  150 , the second pillar layer  260  and the interposer  270 . 
         [0046]    In the present embodiment, the package substrate  410  is multi-layered package structure. For example, the package substrate  410  includes the first conductive layer  111 , the first pillar layer  112 , the first package body  113 , the second conductive layer  114 , a third conductive layer  411 , a third pillar layer  412  and a third package body  413 . The first conductive layer  111 , the first pillar layer  112  and the first package body  113  together form a first single-layered package structure, and the third conductive layer  411 , the third pillar layer  412  and the third package body  413  form a second single-layered package structure. In another embodiment, the number of the layers of the package substrate  410  may be more than two. 
         [0047]    The third conductive layer  411  is formed on the second upper surface  113   u  of the first package body  113  and electrical connects to the first pillar layer  112 . The third pillar layer  412  connects the third conductive layer  411  to the second conductive layer  114 . The third package body  413  encapsulates the third pillar layer  412  and the third conductive layer  411 . In the present embodiment, the second conductive layer  114  is formed on a sixth upper surface  413   u  of the third package body  413  and electrically connects to the first conductive layer  111  through the third conductive layer  411 , the third pillar layer  412  and the first pillar layer  112 . 
         [0048]    In addition, the third package body  413  may be made of a material which is the same as that of the first package body  113 . 
         [0049]    Since the first package body  113  and the third package body  413  are the molding compounds, the package substrate  410  has thin thickness t 1 . Compared to the silicon substrate, the thickness t 1  of the package substrate  410  is much smaller. In general, the silicon substrate has the thickness larger than 100 micrometers. In the present embodiment, the thickness t 1  of the package substrate  410  is smaller, and accordingly the thickness t 2  of the semiconductor package  100  may be reduced. 
         [0050]      FIG. 5  illustrates a diagram of a semiconductor package  500  according to another embodiment of the invention. The semiconductor package  500  includes the package substrate  410 , the first electronic component  120 , the second package body  130 , the second electronic component  140 , at least one conductive contact  150 , the second pillar layer  260  and the fourth conductive layer  370 . 
         [0051]    In the present embodiment, since the fourth conductive layer  370  is embedded in the second package body  130 , the second package body  130  has the thin thickness t 3 . The second pillar layer  260  electrically connects the second conductive layer  114  to the fourth conductive layer  370 , such that the first electronic component  120  may electrically connect the fourth conductive layer  370  through the package substrate  410  and the second pillar layer  260 . 
         [0052]      FIG. 6  illustrates a diagram of a semiconductor device  10  according to one embodiment of the invention. The semiconductor device  10  includes the semiconductor package  200  and a third electronic component  11 . In another embodiment, the third electronic component  11  may be a semiconductor package including a plurality of dies, such as DRAMs stacked to each other. 
         [0053]    The third electronic component  11  is disposed on the interposer  270  of the semiconductor package  200  in a “face-down” orientation and electrically connected to the interposer  270  via a plurality of conductive contacts  115 . The conductive contacts  115  may be solder ball, conductive pillar, etc. In another embodiment, the third electronic component  11  is disposed on the interposer  270  in a “face-up” orientation and electrically connected to the interposer  270  via a plurality of conductive bond wires (not shown). The third electronic component  11  electrically connects to the first electronic component  120  through the interposer  270 , the second pillar layer  260  and the package substrate  110 . In addition, the third electronic component  11  electrically connects to the conductive contacts  150  through the interposer  270 , the second pillar layer  260  and the package substrate  110 . 
         [0054]      FIG. 7  illustrates a diagram of a semiconductor device  20  according to another embodiment of the invention. The semiconductor device  20  includes the semiconductor package  300  and a third electronic component  11 . 
         [0055]    The third electronic component  11  is disposed on the fourth conductive layer  370  of the semiconductor package  300  in a “face-down” orientation or in a “face-up” orientation. The third electronic component  11  electrically connects to the first electronic component  120  through the fourth conductive layer  370 , the second pillar layer  260  and the package substrate  110 . In addition, the third electronic component  11  electrically connects to the conductive contacts  150  through the fourth conductive layer  370 , the second pillar layer  260  and the package substrate  110 . 
         [0056]    In another embodiment, the third electronic component  11  may be disposed on the interposer  270  of the semiconductor package  400  of  FIG. 4  to form another semiconductor device. In other embodiment, the third electronic component  11  may be disposed on the fourth conductive layer  370  of the semiconductor package  500  of  FIG. 5  to form another semiconductor device. 
         [0057]      FIGS. 8A to 8H  illustrate manufacturing processes of the semiconductor package  100  of  FIG. 1 . 
         [0058]    Referring to  FIG. 8A , a carrier  180  is provided. The carrier  180  may be formed by a metal plate comprising of copper, iron or steel. 
         [0059]    Referring to  FIG. 8A , the first conductive layer  111  is formed on the carrier  180  using, for example, photolithography, electroless plating, electrolytic plating, printing, sputtering, vacuum deposition, etc. 
         [0060]    Referring to  FIG. 8B , the first pillar layer  112  is formed on the first conductive layer  111  using, for example, photolithography, electroless plating, electrolytic plating, printing, sputtering, vacuum deposition, etc. 
         [0061]    Referring to  FIG. 80 , the first package body  113  encapsulating the first conductive layer  111  and the first pillar layer  112  is formed on an upper surface  180   u  of the carrier  180 . The first package body  113  may be formed by various packaging technologies, such as, for example, compression molding, injection molding, transfer molding or dispensing technology. 
         [0062]    In the present embodiment, the first package body  113  may be grinded, such that the first upper surface  1121   u  of each pillar  1121  is exposed from the second upper surface  113   u  of the first package body  113 , wherein the first upper surface  1121   u  is aligned with the second upper surface  113   u.    
         [0063]    Referring to  FIG. 8D , the second conductive layer  114  is formed on the first pillar layer  112  using, for example, photolithography, electroless plating, electrolytic plating, printing, sputtering, vacuum deposition, etc. The first conductive layer  111 , the first pillar layer  112 , the first package body  113  and the second conductive layer  114  form the package substrate  110 . 
         [0064]    Referring to  FIG. 8E , the first electronic component  120  is disposed on second conductive layer  114  of the package substrate  110  through the conductive contacts  121  using, for example, surface mount technology (SMT). 
         [0065]    Referring to  FIG. 8F , the second package body  130  encapsulating the first electronic component  120  and the second conductive layer  114  is formed on the package substrate  110 . The second package body  130  may be formed by various packaging technologies, such as, for example, compression molding, injection molding, transfer molding or dispensing technology. 
         [0066]    Referring to  FIG. 8G , the carrier  180  is removed using, for example, etching, peeling, etc. After the carrier  180  is removed, the first lower surface  1111   b  of the first conductive layer  111  and the second lower surface  113   b  of the first package body  113  are exposed, wherein the first lower surface  1111   b  and the second lower surface  113   b  are aligned with each other. For example, the first lower surface  1111   b  and the second lower surface  113   b  are coplanar. 
         [0067]    Referring to  FIG. 8H , the conductive contacts  150  are formed on the first lower surface  1111   b  of the first conductive layer  111  using, for example, ball mounting technology. In addition, the second electronic component  140  is disposed on the first lower surface  1111   b  of the first conductive layer  111  using, for example, SMT. 
         [0068]      FIGS. 9A to 9B  illustrate manufacturing processes of the semiconductor package  200  of  FIG. 2 . 
         [0069]    Referring to  FIG. 9A , the interposer  270  connects to the package substrate  110  through the second pillar layer  260 . The interposer  270  may electrically connect to the first electronic component  120  through the second pillar layer  260  and the package substrate  110 . 
         [0070]    Referring to  FIG. 9B , the second package body  130  encapsulating the first electronic component  120 , the second conductive layer  114  and second pillar layer  260  is formed between the package substrate  110  and the interposer  270 . The second package body  130  may be formed by various packaging technologies, such as, for example, compression molding, injection molding, transfer molding or dispensing technology. 
         [0071]    Then, referring to  FIG. 9B , the carrier  180  is removed. After the carrier  180  is removed, the first lower surface  1111   b  of the first conductive layer  111  and the second lower surface  113   b  of the first package body  113  are exposed, wherein the first lower surface  1111   b  and the second lower surface  113   b  are aligned with each other. For example, the first lower surface  1111   b  and the second lower surface  113   b  are coplanar. 
         [0072]    Then, the conductive contacts  150  and the second electronic component  140  are formed on the first lower surface  1111   b  of the first conductive layer  111  to form the semiconductor package  200  of  FIG. 2 . 
         [0073]    In another embodiment, the third electronic component  11  of  FIG. 6  may be disposed on the interposer  270  of  FIG. 9B  to form the semiconductor device  10  of  FIG. 6 . 
         [0074]      FIGS. 10A to 100  illustrate manufacturing processes of the semiconductor package  300  of  FIG. 3 . 
         [0075]    Referring to  FIG. 10A , the fourth conductive layer  370  formed on a carrier  190  connects to the package substrate  110  through the second pillar layer  260 . The fourth conductive layer  370  may electrically connect to the first electronic component  120  through the second pillar layer  260  and the package substrate  110 . 
         [0076]    Referring to  FIG. 10B , the second package body  130  encapsulating the first electronic component  120 , the second conductive layer  114 , the second pillar layer  260  and the fourth conductive layer  370  is formed between the package substrate  110  and the carrier  190 . The second package body  130  may be formed by various packaging technologies, such as, for example, compression molding, injection molding, transfer molding or dispensing technology. 
         [0077]    Referring to  FIG. 100 , the carrier  190  is removed to expose the fourth upper surface  130   u  of the second package body  130  and the fifth upper surface  371   u  of the fourth conductive layer  370 , wherein the fourth upper surface  130   u  and the fifth upper surface  371   u  are aligned with each other. 
         [0078]    Referring to  FIG. 100 , the carrier  180  is removed. After the carrier  180  is removed, the first lower surface  1111   b  of the first conductive layer  111  and the second lower surface  113   b  of the first package body  113  are exposed, wherein the first lower surface  1111   b  and the second lower surface  113   b  are aligned with each other. For example, the first lower surface  1111   b  and the second lower surface  113   b  are coplanar. 
         [0079]    Then, the conductive contacts  150  and the second electronic component  140  are formed on the first lower surface  1111   b  of the first conductive layer  111  to form the semiconductor package  300  of  FIG. 3 . 
         [0080]    In another embodiment, the third electronic component  11  of  FIG. 7  may be disposed on the fourth conductive layer  370  of  FIG. 100  to form the semiconductor device  20  of  FIG. 7 . 
         [0081]      FIGS. 11A to 11H  illustrate manufacturing processes of the semiconductor package  400  of  FIG. 4 . 
         [0082]    Referring to  FIG. 11A , the carrier  180  is provided. The carrier  180  may be formed by a metal plate comprising of copper, iron or steel. 
         [0083]    Referring to  FIG. 11A , the first conductive layer  111 , the first pillar layer  112 , the first package body  113  are formed on the carrier  180  using the processes, as mentioned above. 
         [0084]    Referring to  FIG. 11B , the third pillar layer  411  is formed on the first pillar layer  112  using, for example, photolithography, electroless plating, electrolytic plating, printing, sputtering, vacuum deposition, etc. 
         [0085]    Referring to  FIG. 11B , the third pillar layer  412  is formed on the third pillar layer  411  using, for example, photolithography, electroless plating, electrolytic plating, printing, sputtering, vacuum deposition, etc. 
         [0086]    Referring to  FIG. 11C , the third package body  413  encapsulating the third conductive layer  411  and the third pillar layer  412  is formed on the second upper surface  113   u  of the first package body  113 . The third package body  413  may be formed by various packaging technologies, such as, for example, compression molding, injection molding, transfer molding or dispensing technology. 
         [0087]    In the present embodiment, the third package body  413  may be grinded, such that an upper surface  412   u  of the third pillar layer  412  is exposed from the sixth upper surface  413   u  of the third package body  413 , wherein the upper surface  412   u  is aligned with the sixth upper surface  413   u.    
         [0088]    Referring to  FIG. 11D , the second conductive layer  114  is formed on the third pillar layer  412  using, for example, photolithography, electroless plating, electrolytic plating, printing, sputtering, vacuum deposition, etc. The first conductive layer  111 , the first pillar layer  112 , the first package body  113 , the second conductive layer  114 , the third conductive layer  411 , the third pillar layer  412  and the third package body  413  form the package substrate  410 . 
         [0089]    Referring to  FIG. 11E , the first electronic component  120  is disposed on second conductive layer  114  of the package substrate  410  through the conductive contacts  121  using, for example, surface mount technology (SMT). 
         [0090]    Referring to  FIG. 11F , the interposer  270  connects to the package substrate  410  through the second pillar layer  260 . The interposer  270  may electrically connect to the first electronic component  120  through the second pillar layer  260  and the package substrate  410 . 
         [0091]    Referring to  FIG. 11G , the second package body  130  encapsulating the first electronic component  120 , the second conductive layer  114  and second pillar layer  260  is formed between the package substrate  410  and the interposer  270 . The second package body  130  may be formed by various packaging technologies, such as, for example, compression molding, injection molding, transfer molding or dispensing technology. 
         [0092]    Referring to  FIG. 11H , the carrier  180  is removed using, for example, etching, peeling, etc. After the carrier  180  is removed, the first lower surface  1111   b  of the first conductive layer  111  and the second lower surface  113   b  of the first package body  113  are exposed, wherein the first lower surface  1111   b  and the second lower surface  113   b  are aligned with each other. For example, the first lower surface  1111   b  and the second lower face  113   b  are coplanar. 
         [0093]    Then, the conductive contacts  150  and the second electronic component  140  are formed on the first lower surface  1111   b  of the first conductive layer  111  to form the semiconductor package  400  of  FIG. 4 . 
         [0094]    In another embodiment, the third electronic component  11  of  FIG. 6  may be disposed on the interposer  270  of  FIG. 11H  to form another semiconductor device. 
         [0095]      FIGS. 12A to 120  illustrate manufacturing processes of the semiconductor package  500  of  FIG. 5 . 
         [0096]    Referring to  FIG. 12A , the fourth conductive layer  370  formed on the carrier  190  connects to the package substrate  410  through the second pillar layer  260 . The fourth conductive layer  370  may electrically connect to the first electronic component  120  through the second pillar layer  260  and the package substrate  410 . 
         [0097]    Referring to  FIG. 12B , the second package body  130  encapsulating the first electronic component  120 , the second conductive layer  114 , the second pillar layer  260  and the fourth conductive layer  370  is formed between the package substrate  410  and the carrier  190 . The second package body  130  may be formed by various packaging technologies, such as, for example, compression molding, injection molding, transfer molding or dispensing technology. 
         [0098]    Referring to  FIG. 120 , the carrier  190  is removed to expose the fourth upper surface  130   u  of the second package body  130  and the fifth upper surface  371   u  of the fourth conductive layer  370 , wherein the fourth upper surface  130   u  and the fifth upper surface  371   u  are aligned with each other. 
         [0099]    Referring to  FIG. 120 , the carrier  180  is removed. After the carrier  180  is removed, the first lower surface  1111   b  of the first conductive layer  111  and the second lower surface  113   b  of the first package body  113  are exposed, wherein the first lower surface  1111   b  and the second lower surface  113   b  are aligned with each other. For example, the first lower surface  1111   b  and the second lower surface  113   b  are coplanar. 
         [0100]    Then, the conductive contacts  150  and the second electronic component  140  are formed on the first lower surface  1111   b  of the first conductive layer  111  to form the semiconductor package  500  of  FIG. 5 . 
         [0101]    In another embodiment, the third electronic component  11  of  FIG. 7  may be disposed on the fourth conductive layer  370  of  FIG. 120  to form another semiconductor device. 
         [0102]    While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.