Abstract:
A receiving circuit with an ultra-wide common-mode input voltage range applies to a controller area network (CAN) and comprises a resistor assembly electrically connected with a CANH and a CANL, a reference amplifier, a first input amplifier assembly, a second input amplifier assembly, and an analog adder. The receiving circuit receives voltages from the CANH and CANL. The resistor assembly bucks voltage, respectively generating CANH and CANL voltage divisions at first and second nodes and outputting the voltage divisions to the first and second input amplifier assemblies. The first and second input amplifier assemblies amplify the differential signal between the first and second nodes and convert the differential signal into single-end signals. The analog adder adds the single-end signals as the output signal. The receiving circuit can receive the signal ranging between the maximum and minimum common-mode voltages and reduce electromagnetic emission.

Description:
This application claims priority for Taiwan patent application no. 104132481 filed on Oct. 2, 2015, the content of which is incorporated in its entirely. 
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a receiving circuit of a controller area network, particularly to a receiving circuit with an ultra-wide common-mode input voltage range, which can receive a signal ranging between a maximum common-mode voltage and a minimum common-mode voltage. 
     Description of the Related Art 
     The controller area network (CAN) issued by International Standard Organization (ISO) (ISO-11898) is a communication system developed for European automobiles to transmit information in very harsh environments, integrating several in-vehicle controllers or computers to a network for sharing responsibilities and information, whereby to execute the demanded functions. The CAN bus is able to transmit information stably in harsh or instable electrical environments and usually applied to the control systems of various types of vehicles. The CAN bus adopts the two-wire differential technology and uses differential signals to transmit information. The common-mode signals on the two wires are maintained at a DC voltage, whereby only a very small amount of electromagnetic waves is emitted from the transmission lines, and whereby the CAN bus can transmit signals persistently while external common-mode signals interferes with the differential bus. 
     In a vehicular environment, great ground voltage shift exists between the ground terminals of different communication nodes. The maximum level of the ground shift voltage will be further increased by batteries with higher output voltage be applied in future vehicles. For example, the output voltage level of the batteries applied in traditional gasoline vehicles is 12V. However, the output voltage level of the batteries applied in modern electric vehicle has been increased to 48V for longer battery life currently. Therefore, the common-mode input voltage range of the CAN transceiver integration circuit must be improved continuously so as to normally receive information in the case that great ground voltage shift exists between the ground terminals of different communication nodes. Besides, in order to avoid electromagnetic emission (EME) from the communication network to interfere other functions of the vehicle, the common-mode signal of the CAN bus must be maintained at a fixed DC voltage and avoid any unnecessary high-frequency fluctuation on the common-mode signals during the circuit operation. 
     There have been many conventional technologies applied to the differential receiving circuit of the CAN transceiver. For an example, a U.S. Pat. No. 7,274,916B2 disclosed a differential receiving circuit and a method thereof. The conventional differential receiving circuit comprises a first voltage-current converter converting a voltage signal at a first input to a first current, a second voltage-current converter converting a voltage signal at a second input to a second current, and a current subtractor providing a differential current of the first current and the second current. For another example, a U.S. Pat. No. 7,567,105B2 disclosed a high-speed CAN receiving circuit with improved anti-electromagnetic interference ability, wherein the receiving circuit is connected with a resistor assembly among the power supply end, the ground end, the CAN high end and the CAN low end to attenuate the signals on the CAN bus. Next, the resistor assembly-attenuated signals are input to a front-end amplifier to amplify the reciprocal of the attenuation ratio of the resistor assembly. Thus, the intensity of the differential signal at the front-end amplifier output end is equal to the intensity of the differential signal on the CAN bus. The common-mode voltage at the front-end amplifier output end is attenuated to a range handleable by the comparator. Further, the front-end amplifier also outputs a common-mode voltage to a basic voltage generator for generating a reference voltage level to the comparator. Then, the comparator compares the signal output by the front-end amplifier and the reference voltage to determine the logics level of the received signal. For a further example, a U.S. Pat. No. 7,738,566B2 disclosed a circuit device for data transmission systems and an operating method thereof, wherein a resistor assembly is connected with the power supply end, the ground end, the CAN high end and the CAN low end to divide the voltages of the signals on the CAN bus and attenuate the common-mode signals to the range handleable by the rear-stage front-end amplifier, and wherein the output of the resistor assembly is electrically connected with a sets of front-end amplifiers which accepts the common-mode input voltage being limited by the power supply, whereby the range of the acceptable common-mode input voltage of the receiving circuit is increased. 
     All the abovementioned conventional technologies are used to improve the common-mode input voltage range of the receiving circuit of the CAN bus. However, each of them still has limitation in the input common-mode voltage range, not necessarily meet to the requirement of current CAN bus operation environment. For examples, in the U.S. Pat. No. 7,274,916, the highest common-mode input voltage is limited by the highest current driving capability of the transistors M 0  and M 3 , ands the lowest common-mode input voltage is limited by the values of the currents of ICM L  and ICM H ; in the U.S. Pat. No. 7,567,105, the common-mode input voltage range of the front-end amplifier is between (VCC−1.8)V and (−0.8) V; in the U.S. Pat. No. 7,738,566, the common-mode input voltage range of the front-end amplifier is between (VCC−1.1875)V and (−∞)V. Therefore, all the abovementioned conventional technologies respectively have their own limitations. Besides, in the U.S. Pat. No. 7,738,566 and U.S. Pat. No. 7,567,105, the common-mode voltage level of the CAN bus during recessive state is determined by the voltage divisions of the power supply voltage, and the voltage division is undertaken by the resistor assembly electrically connected with the power supply end, the ground end, the CAN high end and the CAN low end. However, the resistance values of the resistors are likely to deviate from the designed values in practical fabrication of chips. Thus, the common-mode voltage level of the CAN bus during the recessive state is likely to deviate from the common-mode voltage level output by the transmitter of the CAN transceiver integration circuit during the dominant state. Then, the common-mode signals of the CAN bus are likely to have high-frequency fluctuation, which causes EME to be increased during transceiver circuit operation. 
     Accordingly, the present invention proposes a receiving circuit with an ultra-wide common-mode input voltage range, which can be applied as the receiving circuit of a CAN transceiver integration circuit, to overcome the problems of the conventional technologies. 
     SUMMARY OF THE INVENTION 
     The primary objective of the present invention is to provide a receiving circuit with an ultra-wide common-mode input voltage range, which is applicable to a transceiver integration circuit of a controller area network (CAN). While input voltage signals enter the receiving circuit of the present invention, the receiving circuit can receive differential signals of a common-mode range between the positive infinite volt (+∞ V) and the negative infinite volt (−∞ V). The receiving circuit of the present invention can also decrease electromagnetic emission while the practical values of the elements deviate from the ideal values. 
     To achieve the abovementioned objective, the present invention proposes a receiving circuit with an ultra-wide common-mode input voltage range, which is electrically connected with the output end of the receiving circuit, and which comprises a resistor assembly, a reference amplifier, a first input amplifier assembly, a second input amplifier assembly, and an analog adder. The resistor assembly is electrically connected with a CAN high end (CANH) and a CAN low end (CANL). The resistor assembly includes a first resistor, a second resistor, a third resistor and a fourth resistor, which are cascaded with the CANH and the CANL in sequence. A first node is arranged between the first resistor and the second resistor. A second node is arranged between the third resistor and the fourth resistor. The first resistor is electrically connected with the CANH and the first node. The fourth resistor is electrically connected with the CANL and the second node. The resistor assembly receives the CANH voltage (VCANH) and the CANL voltage (VCANL). The resistor assembly bucks the voltage and generates a CANH voltage division (VCANH DIV ) and a CANL voltage division (VCANL DIV ) respectively at the first node and the second node. The reference amplifier has a reference amplifier input end and a reference amplifier output end. The reference amplifier input end is electrically connected with a reference voltage source. The reference amplifier output end is electrically connected with a contact between the second resistor and the third resistor. The first input amplifier assembly has a first input amplifier assembly output end. The first input amplifier assembly is electrically connected with a power source end, the first node and the second node. The second input amplifier assembly has a second input amplifier assembly output end. The second input amplifier assembly is electrically connected with a ground terminal, the first node and the second node. Each of the first input amplifier assembly and the second input amplifier assembly receives the VCANH DIV  from the first node and the VCANL DIV  from the second node. The first input amplifier assembly outputs a first single-end output signal from the first input amplifier assembly output end. The second input amplifier assembly outputs a second single-end output signal from the second input amplifier assembly output end. The analog adder has an analog adder input end and an analog adder output end. The analog adder input end is electrically connected with the first input amplifier assembly output end and the second input amplifier assembly output end. The analog adder output end is electrically connected with the output end of the receiving circuit. The analog adder receives and adds the first single-end output signal and the second single-end output signal and then outputs the resultant signal to the output end of the receiving circuit. Each of the first input amplifier assembly and the second input amplifier assembly can independently amplify the differential signal of the first node and the second node and convert the amplified signal into a single-end signal. The analog adder adds single-end signals output by the first input amplifier assembly and the second input amplifier assembly and obtains a received signal. 
     Below, embodiments are described in detail in cooperation with the attached drawings to make easily understood the objectives, technical contents, characteristics and accomplishments of the present invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram schematically showing the architecture of a receiving circuit according to one embodiment of the present invention; 
         FIG. 2  is a diagram schematically showing a dominant state and a recessive state according to one embodiment of the present invention; and 
         FIG. 3  is a diagram schematically showing the circuit where a resistor assembly is electrically connected with a transmitter according to one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The controller area network (CAN) is one of the field buses widely used internationally, featuring high bit rate, high anti-interference ability, and error detection capability. The controller area network has been extensively applied to the automobile industry and aircraft industry. The receiving circuit with an ultra-wide common-mode input voltage range of the present invention can receive a wider common-mode input voltage range than the conventional receiving circuits. In the case that the circuit parameters deviate from the designed values in practical fabrication, the receiving circuit of the present invention can still maintain the electromagnetic emission at a very low level. 
     Refer to  FIG. 1  a diagram schematically showing the architecture of a receiving circuit according to one embodiment of the present invention. The present invention proposes a receiving circuit  10  with an ultra-wide common-mode input voltage range. The receiving circuit  10  is electrically connected with an output end RXD of the receiving circuit of a controller area network (CAN) and applicable to a transceiver integration circuit of a controller area network. The receiving circuit  10  with an ultra-wide common-mode input voltage range comprises a resistor assembly  12 , a reference amplifier  14 , a first input amplifier assembly  16 , a second input amplifier assembly  18 , and an analog adder  20 . The resistor assembly  12  is electrically connected with a CAN high end CANH and a CAN low end CANL. The main function of the receiving circuit  10  is amplifying the differential signals of the CAN high end CANH and the CAN low end CANL and converting to single-end digital signals on output end RXD which voltage level is switched between power and ground. The resistor assembly  12  includes a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , and a fourth resistor R 4 , which are cascaded in sequence. A first node N 1  is arranged between the first resistor R 1  and the second resistor R 2 . A second node N 2  is arranged between the third resistor R 3  and the fourth resistor R 4 . The first resistor R 1  is electrically connected with the CAN high end CANH. The fourth resistor R 4  is electrically connected with the CAN low end CANL. The resistor assembly  12  receives a high end voltage VCANH from the CAN high end CANH and a low end voltage VCANL from the CAN low end CANL. The resistor assembly  12  bucks the voltage and generates a high end voltage division VCANH DIV  and a low end voltage division VCANL DIV  respectively at the first node N 1  and the second node N 2 . The resistor assembly  12  functions to provide a high impedance (normally about 30K ohms) between the high end CANH and the low end CANL during the recessive state and slightly attenuate the common-mode voltage of the high end CANH and the low end CANL lest too high an input voltage burn down internal transistors. The reference amplifier  14  has a reference amplifier input end and a reference amplifier output end. The reference amplifier input end is electrically connected with a reference voltage source VCM REF . The reference amplifier output end is electrically connected with a contact between the second resistor R 2  and the third resistor R 3 . The reference amplifier  14  is an inverting closed-loop amplifier, functioning to bias the common-mode voltage of the CAN bus to the reference voltage source VCM REF  during the recessive state. The first input amplifier assembly  16  has a first input amplifier assembly output end. The first input amplifier assembly  16  is electrically connected with a power source end VCC, the first node N 1  and the second node N 2 . The second input amplifier assembly  18  has a second input amplifier assembly output end. The second input amplifier assembly  18  is electrically connected with a ground terminal GND, the first node N 1  and the second node N 2 . Each of the first input amplifier assembly  16  and the second input amplifier assembly  18  can independently amplify the differential signal of the first node N 1  and the second node N 2  (VCANH DIV −VCANL DIV ) and convert the amplified signal into a single-end signal. The analog adder  20  has an analog adder input end and an analog adder output end. The analog adder input end is electrically connected with the first input amplifier assembly output end and the second input amplifier assembly output end. The analog adder output end is electrically connected with the output end RXD of the receiving circuit  10 . The analog adder  20  receives and adds the single-end output signals of the first input amplifier assembly  16  and the second input amplifier assembly  18 , and then the output end RXD of the receiving circuit  10  outputs the resultant signal as the received signal. 
     In this paragraph, the first input amplifier assembly  16 , the second input amplifier assembly  18  and other elements of the receiving circuit  10  of the present invention will be further described in detail. The first input amplifier assembly  16  includes a first voltage level shifter  162 , a first differential amplifier  164 , a second voltage level shifter  166 , and a first output amplifier  168 . The first voltage level shifter  162  is electrically connected with the power source end VCC and the first node N 1 . The first voltage level shifter  162  can upshift the DC voltage level of the high end voltage division VCANH DIV  to the voltage range handleable by the first differential amplifier  164 . The second voltage level shifter  166  is electrically connected with the power source end VCC and the second node N 2 . The second voltage level shifter  166  can upshift the DC voltage level of the low end voltage division VCANL DIV  to the voltage range handleable by the first differential amplifier  164 . The first differential amplifier  164  is electrically connected with the power source end VCC, the first voltage level shifter  162 , and the second voltage level shifter  166 . The first differential amplifier  164  receives a differential signal, which the direct-current voltage level is adjusted by the first voltage level shifter  162  and the second voltage level shifter  166  from the first node N 1  and the second node N 2 , to generate a first differential signal DS 1 . A first load L 1  and a second load L 2  are arranged between the output end of the first differential amplifier  164  and the power source end VCC. Each of the first load L 1  and the second load L 2  is electrically connected with the power source end VCC, the output end of the first differential amplifier  164 , and the input end of the first output amplifier  168 . The input end of the first output amplifier  168  is electrically connected with the output end of the first differential amplifier  164 . The output end of the first output amplifier  168  is electrically connected with a first input end of the analog adder  20 . The first output amplifier  168  receives the first differential signal DS 1  output by the first differential amplifier  164 , amplifying the first differential signal DS 1 , converting the first differential signal DS 1  into a first single-end output signal SS 1 , and outputting the first single-end output signal SS 1  to the analog adder  20 . The second input amplifier assembly  18  includes a third voltage level shifter  182 , a second differential amplifier  184 , a fourth voltage level shifter  186 , and a second output amplifier  188 . The third voltage level shifter  182  is electrically connected with the ground terminal GND and the first node N 1 . The third voltage level shifter  182  can downshift the DC voltage level of the high end voltage division VCANH DIV  to the voltage range handleable by the second differential amplifier  184 . The fourth voltage level shifter  186  is electrically connected with the ground terminal GND and the second node N 2 . The fourth voltage level shifter  186  can downshift the DC voltage level of the low end voltage division VCANL DIV  to the voltage range handleable by the second differential amplifier  184 . The second differential amplifier  184  is electrically connected with the third voltage level shifter  182 , the fourth voltage level shifter  186 , and the ground terminal GND. The second differential amplifier  184  receives a differential signal, which direct-current voltage level is adjusted by the third voltage level shifter  182  and the fourth voltage level shifter  186  from the first node N 1  and the second node N 2 , to generate a second differential signal DS 2 . A third load L 3  and a fourth load L 4  are arranged between the output end of the second differential amplifier  184  and the ground terminal GND. Each of the third load L 3  and the fourth load L 4  is electrically connected with the output end of the second differential amplifier  184 , the ground terminal GND, and the input end of the second output amplifier  188 . The second output amplifier  188  is electrically connected with the second differential amplifier  184  and a second input end of the analog adder  20 , receiving the second differential signal DS 2  from the second differential amplifier  184 , amplifying the second differential signal DS 2 , converting the second differential signal DS 2  into a second single-end output signal SS 2 , and outputting the second single-end output signal SS 2  to the analog adder  20 . The analog adder  20  adds the first single-end output signal SS 1  of the first output amplifier  168  and the second single-end output signal SS 2  of the second output amplifier  188  and then outputs the resultant signal as the output voltage of the receiving circuit. The user can control the stability of current, using a first constant current source IB 1 , a second constant current source IB 2 , a third constant current source IB 3 , and a fourth constant current source IB 4 . Each of the first load L 1 , the second load L 2 , the third load L 3  and the fourth load L 4  is a resistive load, an inductive load or a transistor load. In the receiving circuit  10  with an ultra-wide common-mode input voltage range, a fifth resistor R 5  and a sixth resistor R 6  are cascaded between the first node N 1  and the second node N 2 , and a third node N 3  is formed between the fifth resistor R 5  and the sixth resistor R 6 . The third node N 3  is electrically connected with the fifth resistor R 5 , the sixth resistor R 6 , the first differential amplifier  164  and the second differential amplifier  184 . The resistance of the fifth resistor R 5  is equal to the resistance of the sixth resistor R 6 . The fifth resistor R 5  and the sixth resistor R 6  can bias the emitters of the first differential amplifier  164  and the second differential amplifier  184  with a common-mode voltage of the high end voltage division VCANH DIV  and the low end voltage division VCANL DIV  (0.5*VCANH DIV +0.5*VCANL DIV ). 
     Refer to  FIG. 1  again. The first voltage level shifter  162 , the second voltage level shifter  166 , the first differential amplifier  164 , the third voltage level shifter  182 , the fourth voltage level shifter  186  and the second differential amplifier  184  will be described in further detail below. The first voltage level shifter  162  includes a seventh resistor R 7  and a first transistor  1622 . The seventh resistor R 7  is electrically connected with the first node N 1  and the first transistor  1662 . A first emitter E 1  of the first transistor  1622  is electrically connected with the seventh resistor R 7 . A first collector C 1  of the first transistor  1622  is electrically connected with the first constant current source IB 1 , a first base B 1  of the first transistor  1622  and the first differential amplifier  164 . The first base B 1  is electrically connected with the first constant current source IB 1 , the first collector C 1 , and the first differential amplifier  164 . The first constant current source IB 1  is electrically connected with the power source end VCC, the first collector C 1 , and the first base B 1 . The first voltage level shifter  162  can upshift the DC voltage level of the high end voltage division VCANH DIV  by V BE1 +IB 1 *R 7  to a voltage range handleable by a second base B 2  of the first differential amplifier  164 . The second voltage level shifter  166  includes an eighth resistor R 8  and a fourth transistor  1662 . The eighth resistor R 8  is electrically connected with the second node N 2  and the fourth transistor  1662 . A fourth emitter E 4  of the fourth transistor  1662  is electrically connected with the eighth resistor R 8 . A fourth collector C 4  of the fourth transistor  1662  is electrically connected with the second constant current source IB 2 , a fourth base B 4  of the fourth transistor  1662 , and the first differential amplifier  164 . The fourth base B 4  of the fourth transistor  1662  is electrically connected with the second current source IB 2 , the fourth collector C 4 , and the first differential amplifier  164 . The second constant current source IB 2  is electrically connected with the power source end VCC, the fourth collector C 4 , and the fourth base B 4 . The second voltage level shifter  166  can upshift the DC voltage level of the low end voltage division VCANL DIV  by V BE4 +IB 2 *R 8  to a voltage range handleable by a third base B 3  of the first differential amplifier  164 . The first differential amplifier  164  includes a second transistor  1642  and a third transistor  1644 . A second base B 2  of the second transistor  1642  is electrically connected with the first collector C 1  and the first base B 1  of the first transistor  1622 . A second emitter E 2  of the second transistor  1642  is electrically connected with the third node N 3 . A second collector C 2  of the second transistor  1642  is electrically connected with a contact between the first load L 1  and the first output amplifier  168 . A third base B 3  of the third transistor  1644  is electrically connected with the fourth collector C 4  and the fourth base B 4  of the fourth transistor  1662 . A third emitter E 3  of the third transistor  1644  is electrically connected with the third node N 3 . A third collector C 3  of the third transistor  1644  is electrically connected with a contact between the second load L 2  and the first output amplifier  168 . The third voltage level shifter  182  includes a ninth resistor R 9  and a fifth transistor  1822 . The ninth resistor R 9  is electrically connected with the first node N 1  and the fifth transistor  1822 . A fifth emitter E 5  of the fifth transistor  1822  is electrically connected with the ninth resistor R 9 . A fifth collector C 5  of the fifth transistor  1822  is electrically connected with the third constant current source IB 3 , a fifth base B 5  of the fifth transistor  1822 , and the second differential amplifier  184 . The fifth base B 5  of the fifth transistor  1822  is electrically connected with the third constant current source IB 3 , the fifth collector C 5  of the fifth transistor  1822 , and the second differential amplifier  184 . The third constant current source IB 3  is electrically connected with the ground terminal GND, the fifth collector C 5  and the fifth base B 5 . The third voltage level shifter  182  can downshift the DC voltage level of the high end voltage division VCANH DIV  by V BE5 +IB 3 *R 9  to a voltage range handleable by a sixth base B 6  of the second differential amplifier  184 . The fourth voltage level shifter  186  includes a tenth resistor R 10  and an eighth transistor  1862 . The tenth resistor R 10  is electrically connected with the second node N 2  and the eighth transistor  1862 . An eighth emitter E 8  of the eighth transistor  1862  is electrically connected with the tenth resistor R 10 . An eighth collector C 8  of the eighth transistor  1862  is electrically connected with the fourth constant current source IB 4 , an eighth base B 8  of the eighth transistor  1862 , and the second differential amplifier  184 . The eighth base B 8  of the eighth transistor  1852  is electrically connected with the fourth constant current source IB 4 , the eighth collector C 8 , and the second differential amplifier  184 . The fourth constant current source IB 4  is electrically connected with the ground terminal GND, the eighth collector C 8 , and the eighth base B 8 . The fourth voltage level shifter  186  can downshift the DC voltage level of the low end voltage division VCANL DIV  by V BE6 +IB 4 *R 10  to a voltage range handleable by a seventh base B 7  of the second differential amplifier  184 . The second differential amplifier  184  includes a sixth transistor  1842  and a seventh transistor  1844 . A sixth base B 6  of the sixth transistor  1842  is electrically connected with the fifth collector C 5  and the fifth base B 5  of the fifth transistor  1822 . A sixth emitter E 6  of the sixth transistor  1842  is electrically connected with the third node N 3 . A sixth collector C 6  of the sixth transistor  1842  is electrically connected with a contact between the third load L 3  and the second output amplifier  188 . A seventh base B 7  of the seventh transistor  1844  is electrically connected with the fourth voltage level shifter  186 . A seventh emitter E 7  of the seventh transistor  1844  is electrically connected with the third node N 3 . A seventh collector C 7  of the seventh transistor  1844  is electrically connected with a contact between the fourth load L 4  and the second output amplifier  188 . 
     Refer to  FIG. 1  and  FIG. 2 . The controller area network (CAN) has two states: a recessive state R while transmitting data of 1 and a dominant state D while transmitting data of 0. During the dominant state D, the transmitter generates the high end voltage VCANH and the low end voltage VCANL to the high end CANH and the low end CANL of the CAN bus. During the recessive state R, the transmitter turns off, and the reference amplifier  14  transmits a reference voltage VCM REF  to the resistor assembly  12 . The resistor assembly  12  further transmits the reference voltage VCM REF  to the high end CANH and the low end CANL of the CAN bus to determine the high end voltage VCANH and the low end voltage VCANL. In the resistor assembly  12 , the resistance of the first resistor R 1  is equal to the resistance of the fourth resistor R 4 ; the resistance of the second resistor R 2  is equal to the resistance of the third resistor R 3 ; the resistance of the first resistor R 1  plus the second resistor R 2  is designed to be about 15K ohms, and the resistance of the third resistor R 3  plus the fourth resistor R 4  is also about 15K ohms. Refer to  FIG. 3  also. The CAN transceiver integration circuit further comprises a transmitter  30 . The transmitter  30  is electrically connected with the high end CANH and the low end CANL of the CAN bus. The receiving circuit  10  with an ultra-wide common-mode input voltage range of the present invention is electrically connected with the transmitter  30  through the high end CANH and the low end CANL of the CAN bus. The transmitter  30  is a standard transmitter applied to CAN bus. The transmitter  30  includes a power source end VCC, a first field effect transistor MP 1 , a transmitter input end TXD, a second field effect transistor MN 1 , a phase inverter  32 , and a ground terminal  34 . A resistor  36  and a resistor  38 , each of which has a resistance of 30 ohms, are applied the transmitter  30  output to generate the voltage of the high end CANH and the low end CANL. While the voltage of the transmitter input end TXD is zero, it is during the dominant state D, and the first field effect transistor MP 1  and the second field effect transistor MN 1  turn on. The first field effect transistor MP 1 , the second field effect transistor MN 1 , the 30-ohm resistor  36 , and the 30-ohm resistor  38  are cascaded between the power source end VCC and the ground terminal GND to perform voltage division and generate the high end voltage VCANH and the low end voltage VCANL of the CAN bus. In the dominant state D, the high end voltage VCANH, the low end voltage VCANL, and the common-mode voltage of the high end CANH and the low end CANL of the CAN bus are respectively expressed by Equations (1)-(3):
 
VCANH=VCC*(RONMN1+60)/(RONMP1+RONMN1+60)  (1)
 
VCANL=VCC*(RONMN1)/(RONMP1+RONMN1+60)  (2)
 
The common-mode voltage during the dominant state D
 
=(VCANH+VCANL)/2
 
=VCC*(RONMN1+30)/(RONMP1+RONMN1+60)  (3)
 
wherein RONMP 1  is the turn-on resistance of the first field effect transistor MP 1 , RONMN 1  is the turn-on resistance of the second field effect transistor MN 1 , and 60 is the sum of the resistances of the resistor  36  and the resistor  38 .
 
     While the voltage of the transmitter input end TXD is equal to VCC, it is during the recessive state R. During the recessive state R, the first field effect transistor MP 1  and the second field effect transistor MN 1  turn off; both the high end voltage VCANH of the high end CANH and the low end voltage VCANL of the low end CANL are equal to the reference voltage VCM REF  which is transmitted to the resistor assembly  12  by the reference amplifier  14 . In the recessive state R, the common-mode voltage of the high end CANH and the low end CANL of the CAN bus is expressed by Equation (4): 
     The common-mode voltage in the recessive state R
 
=0.5*(VCANH+VCANL)=VCM  (4)
 
wherein the reference voltage VCM REF  is the voltage input to the reference amplifier  14 . Based on Equations (3) and (4), an external reference voltage generation circuit could be applied to the present invention to generate a reference voltage VCM REF , which is equal to the common-mode voltage shown in Equation (3) that the transmitter  30  transmits to the high end CANH and the low end CANL in the dominant state D, to the input of reference amplifier  14 . Thus, during the dominant state D and the recessive state R, the common-mode voltage keeps a fixed value. Then, the frequency spectrum of the common mode voltage on the CAN bus could be free of high-frequency spurious tones and noise, and the electromagnetic emission could be effectively reduced.
 
     Refer to  FIG. 1  again. While the common-mode input voltage of the high end voltage division VCANH DIV  and the low end voltage division VCANL DIV  is higher than the highest common-mode input voltage handleable by the first output amplifier  168  minus the collector-emitter voltage drops of the second transistor  1642  and the third transistor  1644  (VCE 2  and VCE 3 ), the first output amplifier  168  does not operate but generates a first single-end output signal SS 1  of 0. In such a case, the second differential amplifier  184  and the second output amplifier  188  amplify the high end voltage division VCANH DIV  and the low end voltage division VCANL DIV  and convert them into the second single-end output signal SS 2 ; the analog adder  20  then outputs the second single-end output signal SS 2  to the receiving circuit output end RXD. At this moment, the voltage output by the receiving circuit output end RXD is equal to the second single-end output signal SS 2 . While the common-mode input voltage of the high end voltage division VCANH DIV  and the low end voltage division VCANL DIV  is lower than the lowest common-mode input voltage handleable by the second output amplifier  188  plus the collector-emitter voltage drops of the sixth transistor  1842  and the seventh transistor  1844  (VCE 6  and VCE 7 ), the second output amplifier  188  does not operate but generates a second single-end output signal SS 2  of 0. In such a case, the first differential amplifier  164  and the first output amplifier  168  amplify the high end voltage division VCANH DIV  and the low end voltage division VCANL DIV  and convert them into the first single-end output signal SS 1 ; the analog adder  20  then outputs the first single-end output signal SS 1  to the receiving circuit output end RXD. At this moment, the voltage output by the receiving circuit output end RXD is equal to the first single-end output signal SS 1 . While the common-mode input voltage of the high end voltage division VCANH DIV  and the low end voltage division VCANL DIV  is between the highest common-mode input voltage handleable by the first output amplifier  168  minus the collector-emitter voltage drops of the second transistor  1642  and the third transistor  1644  (VCE 2  and VCE 3 ) and the lowest common-mode input voltage handleable by the second output amplifier  188  plus the collector-emitter voltage drops of the sixth transistor  1842  and the seventh transistor  1844  (VCE 6  and VCE 7 ), the first differential amplifier  164  and the first output amplifier  168  amplify the high end voltage division VCANH DIV  and the low end voltage division VCANL DIV  and convert them into the first single-end output signal SS 1 , and the second differential amplifier  184  and the second output amplifier  188  amplify the high end voltage division VCANH DIV  and the low end voltage division VCANL DIV  and convert them into the second single-end output signal SS 2 . Then, the analog adder  20  outputs the first single-end output signal SS 1  and the second single-end output signal SS 2  to the receiving circuit output end RXD. At this moment, the voltage output by the receiving circuit output end RXD is generated by the first single-end output signal SS 1  plus the second single-end output signal SS 2 . 
     Therefore, no matter what the value of the common-mode voltage of the high end voltage division VCANH DIV  and the low end voltage division VCANL DIV  is, the receiving circuit with an ultra-wide common-mode input voltage range of the present invention will transmit the signal received from the high end CANH and the low end CANL of the CAN bus to the receiving circuit output RXD. Further, the present invention uses the reference amplifier to control the common-mode voltage of the network in the recessive state to be equal to the common-mode voltage of the network in the dominant state. Thereby, the electromagnetic emission is reduced. 
     The embodiments mentioned above are to demonstrate the technical thought and characteristics of the present invention to enable the persons skilled in the art to understand, make, and use the present invention. However, these embodiments are not intended to limit the scope of the present invention. Any equivalent modification or variation according to the spirit of the present invention is to be also included within the scope of the present invention.