Abstract:
A 3DIC includes a die and a substrate. The die includes multiple bumps to provide electrical connection the substrate. The substrate includes multiple elongated contact pads. The elongated contact pads making electrical contact with the bumps and shaped to maintain alignment with the bumps over a temperature range.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 62/089,095, filed Dec. 8, 2014, which is incorporated by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    1. Field of the Invention 
         [0003]    This invention relates to elongated contact pad structures. 
         [0004]    2. Description of the Related Art 
         [0005]    Substrates with different coefficient of thermal expansion compared to silicon are used in three dimensional (3D) and 2.5D integrated circuits (collectively, 3DICs). Due to the difference in coefficient of thermal expansion, the substrates of the 3DICs may misalign. Furthermore, large monolithic dies with small contact bumps may also misalign from the contact pads of a substrate the monolithic die is connected to due to a mismatch om the coefficient of thermal expansion between the monolithic die and the substrate. 
         [0006]    Thus, there is a need for an improved contact pad structure that stays aligned at room temperature, as well as at elevated temperatures. 
       SUMMARY 
       [0007]    The present invention overcomes the limitations of the prior art by including an elongated pad that stays aligned at elevated temperatures. The elongation of the pads may depend on the distance between the pad and the center of the substrate. 
         [0008]    A 3DIC includes a die and a substrate. The die includes multiple bumps to provide electrical connection to elongated pads of a substrate. Each elongated pad of the substrate corresponds to a bump of the die at a first temperature and is also aligned to the same corresponding bump at a second temperature. In some embodiments, the first temperature is room temperature and the second temperature is a solder reflow temperature. 
         [0009]    In some embodiments, the amount of elongation of the pads is based on a position of the pad on the substrate, a mismatch between a coefficient of thermal expansion of the die and a coefficient of thermal expansion of the substrate, and/or the second temperature. Additionally, in some embodiments, the elongated pads are elongated radially from a central point of the substrate. 
         [0010]    Other aspects include components, devices, systems, improvements, methods, processes, applications and other technologies related to the foregoing. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The invention has other advantages and features which will be more readily apparent from the following detailed description of the invention and the appended claims, when taken in conjunction with the accompanying drawings, in which: 
           [0012]      FIG. 1  is a cross sectional side view of a three dimensional integrated circuit (3DIC), according to one embodiment of the invention. 
           [0013]      FIG. 2A  (prior art) is a cross sectional view of a die and a substrate with different coefficients of thermal expansion at room temperature. 
           [0014]      FIG. 2B  (prior art) is a cross sectional view of a die and a substrate with different coefficients of thermal expansion at an elevated temperature. 
           [0015]      FIG. 3A  is a cross sectional view of a die and a substrate with elongated pads at room temperature, according to one embodiment. 
           [0016]      FIG. 3B  is a cross sectional view of a die and a substrate with elongated pads at an elevated temperature, according to one embodiment. 
           [0017]      FIG. 4A  (prior art) is a top view of a die and a substrate with different coefficients of thermal expansion at room temperature 
           [0018]      FIG. 4B  (prior art) is a top view of a die and a substrate with different coefficients of thermal expansion at an elevated temperature. 
           [0019]      FIG. 5A  is a top view of a die and a substrate with elongated pads at room temperature, according to one embodiment. 
           [0020]      FIG. 5B  is a top view of a die and a substrate with elongated pads at an elevated temperature, according to one embodiment. 
           [0021]      FIG. 6A  is a top view of a die and a substrate with elongated pads at room temperature, according to one embodiment. 
           [0022]      FIG. 6B  is a top view of a die and a substrate with elongated pads at an elevated temperature, according to one embodiment. 
           [0023]      FIG. 7  is a flow diagram for designing the pads of a printed circuit board, according to one embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0024]    The Figures (FIGS.) and the following description relate to preferred embodiments by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of what is claimed. 
         [0025]    Reference will now be made in detail to several embodiments, examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments of the disclosed system (or method) for purposes of illustration only. Alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles described herein. 
         [0026]      FIG. 1  is a cross sectional side view of a three dimensional (3D) and 2.5D integrated circuit (3DIC). A 3DIC typically includes a stack of alternating active chips and silicon interposers. As shown in  FIG. 1 , an exemplary 3DIC may include several tiles  110  (e.g., logic, field programmable gate arrays or FPGA, memory-stacks, integrated passive devices or IPD, etc), a passive silicon interposer  120  and an organic laminate  130 . In order to route signals, one or more of these components may include thru-silicon vias (TSV). 
         [0027]    The tiles  110  may include integrated circuits fabricated on a piece of semiconductor material. Tiles  110  may be a logic tile (e.g., a microprocessor, an application specific integrated circuit or ASIC, a field programmable gate array or FPGA), a memory tile (e.g., a random access memory or RAM, a non-volatile such a NAND flash memory) or integrated passive devices (e.g., impedance matching circuits, harmonic filters, couplers, etc.). In some embodiments, a module may be spread across multiple tiles  110 . For instance, a 1 GB RAM module may be spread across two tiles  110 , each having 512 MB RAM module. 
         [0028]    The passive silicon interposer  120  interconnects multiple tiles  110  to each other. For instance, a silicon interposer may couple a logic tile with multiple memory tiles. The tiles connect to the silicon interposer through a microbump  115 . Microbumps  115  of the tiles  110  may be aligned to contact pads in one side of the silicon interposer  120  to form an electrical connection between the an input/output (IO) port of the tile  110  and an IO port of the silicon interposer  120 . In some embodiments, a thermal process may be used to bond the microbumps of the tiles  110  to the contact pads of the silicon interposer. For example, a solder reflow process may be used to reflow the microbumps of the tile  110  and bond the IO ports of the tiles  110  to the IO ports of the silicon interposer  120 . 
         [0029]    The organic laminate  130  is coupled to the silicon interposer  120  through bumps  125 . The organic laminate  130  routes the signals received through bumps  125  to out of the 3DIC though solder balls  135 , and routes the signals received through solder balls  135  to the silicon interposer  120  through bumps  125 . 
         [0030]    In some embodiments, the organic laminate  130  reduces the density of IO ports of the silicon interposer  120 . As such, the organic laminate  130  may have a larger area than the silicon interposer  120 . The organic laminate  130  may be manufactured with materials with lower cost than the material used to manufacture the silicon interposer  120 . Since the silicon interposer  120  and the organic laminates are manufactured with different materials, the silicon interposer  120  and the organic laminate  130  may have different coefficients of thermal expansion. As such, during thermal processes of the fabrication of the 3DIC and during the use of the 3DIC, the silicon interposer  120  and the organic laminate  130  will expand at different rates, which may cause misalignment between the IO ports of the silicon interposer  120  and the IO ports of the organic laminate  130 . 
         [0031]      FIG. 2A  is a cross sectional side view of a die and a substrate of a 3DIC with different coefficients of thermal expansion at room temperature and  FIG. 2B  is a cross sectional side view of the die and the substrate at an elevated temperature. The die  211  includes multiple bumps  215  that are aligned to the contact pads  205  of the substrate  201 . The die may, for example, be made of silicon, which has a low coefficient of thermal expansion (CTE). For instance, silicon has a CTE of about 1.5 ppm/° C. The substrate may be, for example, a printed circuit board (PCB) or an organic interposer with a higher CTE. For instance, a PCB has a CTE of that is 10 times larger than the CTE of silicon. As such, the substrate expands faster than the die. 
         [0032]    At room temperature, the bumps  215  of the die  211  are aligned to the contact pads  205  of the substrate  201  and provide an electrical connection between the die  211  and the substrate  201 . During certain fabrication steps and/or during the use of the 3DIC, the 3DIC may be subjected to elevated temperatures. For instance during a solder reflow process of the fabrication of the 3DIC, the 3DIC may be exposed to an elevated temperature to cause the solder to melt and reflow for establishing electrical and/or mechanical connections between the different components of the 3DIC. In another example, during the use of the 3DIC, certain components of the 3DIC may dissipate power in the form of thermal energy, causing the 3DIC to heat up. When the 3DIC is exposed to an elevated temperature, the die  211  and the substrate  201  may expand in accordance with their respective CTE. Since the die  211  and the substrate  201  have different CTE, beyond a certain temperature, the bumps  215  and the pads  205  may misalign. 
         [0033]    As shown in  FIG. 2B , at an elevated temperature, due to the mismatch in the coefficient of thermal expansion, the contact pads  205  of the substrate  201  are misaligned from the bumps  215  of the die  211 . That is, when the temperature of the die  211  and the substrate  201  is elevated, the substrate experiences a larger thermal expansion than the die. For instance, the amount of linear expansion of the die  211  and the substrate  201  is as follows: 
         [0000]      Δ L   s =α s   L   0   ΔT   (1)
 
         [0000]      Δ L   d =α d   L   0   ΔT (2)
 
         [0000]      Δ L =(α s −α d ) L   0   ΔT (3)
 
         [0034]    Where ΔL s  is the amount of thermal expansion experienced by the substrate  201 , ΔL d  is the amount of thermal expansion experienced by the die  211 , α s  is the linear CTE of the substrate  201 , α d  is the linear CTE of the die  211 , L 0  is the length at room temperature, and ΔT is the change in temperature. ΔL is the difference in thermal expansion between the substrate and the die due to the difference in the CTE between the substrate and the die. 
         [0035]    As illustrated in  FIG. 2B , the misalignment is more pronounced near the edge of the substrates. That is, the bumps  215  and contact pads  205  that are near the center of the substrates  201 ,  211  are still aligned at an elevated temperature, but the bumps  215  and contact pads  205  that are near the edge of the substrate are more severely misaligned. 
         [0036]    To maintain alignment of the bumps  215  and the pads  205  at room temperature and at elevated temperature, the pads may be designed with an elongated shape. When the 3DIC is at room temperature, the bumps  215  are aligned to a first end of the elongated pad and when the 3DIC is at an elevated temperature, the bumps  215  are aligned to a second end of the elongated pad. For instance, the pads may have an oval shape or an elliptical shape. 
         [0037]      FIG. 3A  is a cross sectional side view of a die and a substrate with elongated pads at room temperature and  FIG. 3B  is a cross sectional side view of the die and the substrate with elongated pads at an elevated temperature. As illustrated in  FIG. 3A , the contact pads  305  of the substrate are elongated. In some embodiments, the elongation of the pads may be dependent on the position of the pad. In this example, the contact pads  305  that are closer to the edge of the substrate are more elongated than the elongated contact pads  305  that are near the center of the substrate. Furthermore, the amount of elongation of the pads may further be dependent on the CTE mismatch between the die  211  and the substrate  301 , and a maximum temperature the 3DIC is expected to be exposed to. 
         [0038]    As illustrated in  FIG. 3B , since the pads are elongated, after the substrate is expanded at elevated temperatures, the elongated contact pads  305  of the substrate  301  are still aligned to the bumps  215  of the die  211 . As such, the bumps  215  of the die can be electrically connected to the elongated contact pads  305  of the substrate in an elevated temperature environment, such as during a solder reflow process. After the die  211  and the substrate  301  cool down to room temperature, the bumps  215  and the contact pads  305  would still be aligned. 
         [0039]    As shown in  FIG. 3A  and  FIG. 3B , at room temperature, the distance from the center of the die  211  to the center of a bump  215 A is L 0 , the distance between the center of the substrate  301  and a first end of a pad  305 A is L 0 , and the distance from the center of the substrate  301  to the second end of the pad  305 A is L 0 ′. Furthermore, at an elevated temperature, the distance from the center of the die  211  to the center of the bump  215 A is L 0 +ΔL d  and the distance from the center of the substrate  301  to the second end of the pad  305 A is L 0 ′+ΔL s . Since, at the elevated temperature, the second end of the pad  305 A is aligned to the bump  215 A: 
         [0000]        L   0   +ΔL   d   =L   0   ′+ΔL   s   (4)
 
         [0000]    which can be re-written as: 
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         [0040]      FIG. 4A  is a top view of a die and a substrate with different coefficients of thermal expansion at room temperature, and  FIG. 4B  is a top view of the die and the substrate at an elevated temperature. In  FIG. 4B , the dotted lines represent the die  211  with a lower CTE and the solid lines represent the substrate  201  with a higher CTE. As illustrated in  FIG. 4A , the bumps  215  of the die  211  and the pads  205  of the substrate  201  are designed to be aligned at room temperature (so they are overlapping in  FIG. 4A ). Due to the mismatch in CTE, as shown in  FIG. 4B , the substrate  201  expands more than the die  211  and thus, the bumps  215  of the die  211  are mis-aligned from the pads  205  of the substrate. 
         [0041]      FIG. 5A  is a top view of a die and a substrate with elongated pads at room temperature and  FIG. 5B  is a top view of a die and a substrate with elongated pads at an elevated temperature, according to one embodiment. As illustrated in  FIG. 5A , the bumps  215  of the die  211  are aligned, at room temperature, to the elongated contact pads  305  of the substrate  301 . In one embodiment, the bumps  215  of the die  211  are designed to be aligned near a first end of the elongated contact pads  305  of the substrate  301 . When the substrate  301  expands due to an elevated temperature, the bumps  215  of the die  211  stayed aligned to the elongated contact pads  305  of the substrate  301 . In one embodiment, the pads are designed to be aligned to the bumps  215  of the die  211 , at an elevated temperature, at near a second end of the elongated contact pads  305 , opposite to the first end. 
         [0042]    In some embodiments, the pads  305  are elongated in the direction of expansion of the substrate  301 . For instance, the pads  305  are elongated radially from the center of the substrate  301 . In another example, the pads  305  are elongated radially from a point other than the center of the substrate. 
         [0043]    In some embodiments, pads  305  that are closer to the center of the substrate have a smaller elongation than pads that are further away from the center of the substrate. In other embodiments, pads  305  that are closer to the center of the substrate have a smaller area than pads  305  that are further away from the center of the substrate. 
         [0044]      FIG. 6A  is a top view of a die and a substrate with elongated pads at room temperature and  FIG. 6B  is a top view of a die and a substrate with elongated pads at an elevated temperature, according to another embodiment. In the embodiment of  FIG. 6 , the elongated contact pads  305  of the substrate  301  have a circular shape. The size of the elongated contact pads  305  are based on the distance of the pad  305  to the center of the substrate. Elongated contact pads  305  that are further from the center of the substrate are larger than elongated contact pads  305  that are closer to the center of the substrate. In other embodiments, other shapes, such as hexagonal shapes, may be used for the elongated contact pads  305 . 
         [0045]      FIG. 7  is a flow diagram for designing the elongated pads of a printed circuit board, according to one embodiment. A contact pad layout at room temperature is received  701 . The contact pad layout is resized  703  based on the CTE of the substrate  301  and the elevated temperature. Base on the contact pad layout at room temperature and the resized contact pad layout, an elongated pad layout is determined  705 . 
         [0046]    Although the detailed description contains many specifics, these should not be construed as limiting the scope of the invention but merely as illustrating different examples and aspects of the invention. It should be appreciated that the scope of the invention includes other embodiments not discussed in detail above. Various modifications, changes, and variations which will be apparent to those skilled in the art may be made in the arrangement, operation, and details of the method and apparatus of the present invention disclosed herein without departing from the spirit and scope of the invention as defined in the appended claims. Therefore, the scope of the invention should be determined by the appended claims and their legal equivalents. Furthermore, no element, component or method step is intended to be dedicated to the public regardless of whether the element, component or method step is explicitly recited in the claims. 
         [0047]    In the claims, reference to an element in the singular is not intended to mean “one and only one” unless explicitly stated, but rather is meant to mean “one or more.” In addition, it is not necessary for a device or method to address every problem that is solvable by different embodiments of the invention in order to be encompassed by the claims.