Abstract:
A method of and apparatus for discriminator FSK signals using a tri-state phase detector is disclosed in which an input of known frequency is combined with the unknown FSK signal input and the output is fed to an integrator only after the minimum clearing time of the tri-state during each bit period. The integrator receives only the cleared signal for use in binary data signal determination thereby overcoming problems associated with lack of initial phase information at the tri-state phase detector.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to communication systems utilizing a frequency shift keyed technique and more particularly, to an improved detection system using a tri-state phase detector. 
     2. Description of the Prior Art 
     Many communication systems including those which utilize existing power lines use digital modulation techniques in signal transmission. One method of digital transmission is phase shift keyed (PSK) transmission. In PSK systems, the phase of the carrier wave is shifted by 180 degrees to indicate in binary a &#34;mark&#34; or &#34;1&#34; and transmitted without shifting to indicate a space or a &#34;0&#34;. Another digital transmission technique which is becoming more important involves frequency shift keyed (FSK) modulation. This is the type employed in the present invention. In this type of a system, one frequency is used to indicate a &#34;mark&#34; or &#34;1&#34; and another distinct frequency to indicate a space or &#34;0&#34;. Frequency shift keying involves the modulation of the base or carrier frequency to shift that frequency by predetermined increments in response to particular data to be transmitted. 
     In a frequency shift keying system, the frequency shift phase is continuous, i.e., the transmitted signal is a sinusoidal signal which varies in frequency but has no time phase shift continuity. Normally, a binary &#34;1&#34; or a &#34;mark&#34; signal is transmitted at a frequency above a selected center or carrier center frequency or &#34;carrier Plus&#34; frequency and a space or binary &#34;0&#34; is transmitted at a frequency below the center frequency of the carrier or &#34;carrier minus&#34; frequency. In such systems the differential between a transmitted, and thus received frequency, and the center frequency of the carrier may be made equal to or greater than the modulation rate, also known as the data rate, or bit rate, divided by two. 
     Systems for receiving frequency shift keyed transmission signals are well-known. Such systems must discriminate accurately between the carrier minus and carrier plus frequencies and reject spurious or &#34;noise signals&#34; which also may be transmitted. Many techniques and schemes have been used in the prior art in an attempt to achieve better, more accurate signal discrimination. These include the use of various input logic schemes in conjunction with bandpass filters, or the like to check for the presence or absence of certain frequencies. 
     In the prior art, in order to achieve commercially feasible reliability, most discriminator schemes have had to be quite complicated. There has long been a need for simplification of these systems so that inexpensive reliable units would be available. It would be desirable to employ a system using a tri-state phase detector in conjunction with an integrating circuit, the output of which would be used as the input to a comparator which, in turn, would be utilized to activate a latch or other signal utilization means. In the prior art, however, it has been difficult, if not impossible, to provide reliable FSK discrimination using a tri-state detector in combination with an integrating circuit because of the lack of phase information between the output of the tri-state and the bit time. Thus, if the phase relationship is unknown, at least part of the information fed to the integrating circuit can be wrong and this, of course, can lead to a misinterpretation of the input data signal. 
     SUMMARY OF THE INVENTION 
     By means of the present invention, the problems associated with the use of a tri-state phase detector in conjunction with an integrating circuit to produce reliable FSK signal discrimination are solved by the provision of a method and apparatus which overcomes the drawbacks associated with the tri-state phase detector occasioned by lack of phase information between the input FSK signals and the known or reference signal input to the tri-state phase detector. It has been found that if a reference signal of known frequency, which may be the carrier frequency in an FSK system, and an unknown frequency which may be a carrier plus or carrier minus frequency are used as the inputs to a tri-state phase detector, after the signals undergo a phase crossing the signal confusion will clear. An output consisting of all positive pulses or all negative pulses depending on whether the known input frequency is higher or lower than the known reference frequency will be produced after such a phase crossing by the two input frequencies. If a &#34;worst case condition&#34; is assumed, such a frequency phase crossing occurs at least once in the &#34;worst case time&#34; or minimum clearing time. This time will be as follows: ##EQU1## The present invention provides a method and apparatus for operating the tri-state phase detector in conjunction with an integrating circuit in a manner which assures that the tri-state phase detector has cleared prior to enabling the integrater circuit to integrate the FSK tri-state phase detector output. At the start of each bit period or FSK modulation period, integration is not allowed to begin until the passage of an interval equal to or greater than the minimum clearing time. In this manner, the integrater will always be loaded with &#34;cleared data&#34; from the tri-state phase detector thereby eliminating errors produced by initial undesirable phase relationships between the input frequencies. 
     In the preferred embodiment the output of the integrater is fed to a comparator circuit which determines from the voltage level of that signal whether a digital &#34;1&#34; or a &#34;0&#34; has been transmitted. This, in turn, is fed to a data latch or other signal utilization device for use in a well-known manner. The timing information to operate the system may also be derived in any conventional manner. The data timing, i.e. the Baud rate or bit time of the FSK system is known, and the carrier, carrier plus and carrier minus frequencies are known. Thus, for example, the reference frequency and timing signals may be derived from an oscillator operating on the input from the known sixty cycle power line frequency utilizing frequency synthesizers. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     In the drawing wherein like numerals are utilized to designate like parts throughout the same: 
     FIG. 1 is schematic block diagram of the FSK discriminator of the invention; and 
     FIG. 2 is a graphical representation of the waveforms associated with the components of FIG. 1 over a two bit time period. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 depicts the improved FSK discriminator system in accordance with the present invention in schematic block form. This includes a tri-state phase detector 10, which may be similar to the one used in the well-known integrated circuit, the 4046B which is available from several manufacturers, an integrate and discharge circuit 11, sometimes referred to as an &#34;integrate and dump circuit&#34; with associated input and output controls including switches 12 and 13 and an inverter or NOT gate 14. Which may be a data latch 16. 
     The system is shown using an arbitrarily chosen 120kHz reference signal input to the tri-state together with FSK signals, which may be power line carrier FSK signals, including a 122.4 kHz carrier plus or &#34;mark&#34; signal indicating a binary &#34;1&#34; and a 117.6 kHz carrier minus input frequency of &#34;space&#34; signal indicating a binary &#34;0&#34; to the tri-state phase detector. The 120 kHz reference signal input may be obtained in any well-known manner, as from an frequency synthesized signal derived from normal 60 Hz AC power line input. Likewise the timing signals for the control input to the integrater system (shown as waveform B) and the data latch (shown as waveform A) may be similarly derived as by using frequency synthesized techniques in conjunction with the 120 kHz oscillator system in a well-known manner. 
     In accordance with the present invention, if a reference frequency is used for one input and unknown frequency for the other input, the output of the tri-state phase detector, after it has been cleared, will consist of all positive pulses or all negative pulses, depending on whether the unknown frequency is higher or lower than the reference frequency. Thus, if it is higher, positive pulses will occur and, if lower, negative pulses will appear in the output. Clearing of the tri-state phase detector occurs each time the unknown and reference input waveforms coincide in phase. The time that it takes to clear the tri-state phase detector, then, depends on both the initial phase difference of the two frequencies and the amount of frequency difference or deviation between them. In order to build a reliable FSK detector using a tri-state phase detector, it must allow for the worst case conditions. Thus, the system must assume that the two signals initially are out of phase by almost an entire cycle or 359+ degrees. Based on this assumption, the minimum clearing time can be derived from the frequency differences between the reference frequency and the unknown frequency as follows: ##EQU2## using the input frequency associated with FIG. 1, this yields: ##EQU3## 
     In the case of power line carrier communications, data timing information is known. The Baud rate or digital bit time may be, for example, equal to one-half the frequency difference between the carrier plus or carrier minus signal frequency and the reference frequency of 1.2 kHz. It can readily be seen that the minimum clearing time equals one-half the bit time or Baud rate. Therefore, by controlling the operation of the integrater 11 by means of switches 12 and 13 together with NOT gate 14, the integrater may be caused not to integrate for an amount of time equal to the minimum clearing time at the beginning of each bit time, to assure that only cleared pulses will be integrated. 
     The operation of the system is better illustrated utilizing the waveform diagrams in accordance with FIG. 2. In that figure the integrater circuit is shown to integrate either down or up, depending upon whether negative or positive pulses are received from the tri-state phase detector. Integration takes place only during the last half of the bit period. In other words, any given bit period, then, the output of the tri-state phase detector does not become an input to the integrater during the minimum clearing time. After the minimum clearing time has elapsed, switches 12 and 13 are reversed and the integrater 11 begins to integrate the pulse signals from the output of the tri-state phase detector 10. The integrater output is fed to the comparator 15 which is, in turn, a voltage level detector having a digital 1 or 0 output depending on whether a positive or negative integrated signal above or below a certain level is received from the integrater 11. The output of the comparator 15 is fed to the data latch 16 which latches the appropriate digital 1 or 0. 
     The timing of the output is controlled by waveform A going high at the end of each bit period. Waveform A then goes low and waveform B goes high switching the switches 12 and 13 and disabling the integrater until the end of another minimum clearing time during the ensuing bit period. In the diagram of FIG. 2 during the first bit period the data input represents a 0 and during the second illustrated period a 1 in the FSK logic input. 
     It can readily be seen that the integrator, then, receives only cleared pulses from the tri-state phase detector and therefore the chances of digital error in the output of the integrater and, thus, in the output of the comparator are greatly reduced.