Abstract:
A strobed comparator circuit with reduced signal propagation time has a regenerative latch in which, during the reset phase of operation, its output nodes are discharged to a common potential which is close to the regenerative voltage level of the cross-coupled transistors forming such regenerative latch rather than to circuit ground. Accordingly, overall signal propagation time is reduced by the amount of reduction in charging time necessary for one of the discharged nodes to recharge above the threshold voltage of one of the cross-coupled latch transistors. Also included is an output monitoring circuit which determines whether the regenerative latch has remained in a metastable state.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to strobed comparator circuits, and in particular, to strobed comparator circuits using regenerative latches. 
     2. Description of the Related Art 
     The processing stage of a pipelined analog-to-digital (A/D) converter includes a coarse A/D converter, a digital-to-analog (D/A) converter and a subtractor/gain circuit for calculating the residue to be passed on to the subsequent pipeline stage. The D/A converter and subtractor/gain stages are typically combined into the same switched capacitor circuit. During the sampling phase, the analog value is acquired by the current processing stage. During the hold phase the D/A and subtraction/gain operations are performed. Following the sampling phase and prior to the hold phase a comparison phase occurs since the D/A conversion depends upon the result of such comparison. This comparison is performed by a comparator circuit. Due to the reciprocal nature of the operations of successive stages within the A/D pipeline, the propagation time of the comparator function is effectively subtracted from the time allowed for the hold phase. Hence, in high speed circuits it is important to minimize the comparator propagation time so as to maximize the settling time available during the hold phase of operation. 
     All signal comparators have a propagation delay which is dependent upon the magnitude of the input signal (e.g., lower delay for a higher magnitude input signal). However, in a pipeline A/D application, a fixed and relatively large delay is associated with the comparison phase so as to allow for the worst case situation of the lowest possible input signal. 
     Additionally, high speed comparators often suffer from metastability. A metastable state occurs in strobed comparators when the inputs to the comparator are very close to the threshold value. Such metastability cannot be completely avoided. However, some techniques have been developed for reducing the probability of the occurrence of such metastability. One conventional technique involves the use of cascade latching. However, cascade latching cannot be used for high speed pipelined AID converters due to the large comparator propagation time which degrades the high speed performance caused by a reduced settling time. 
     Accordingly, it would be desirable to have a high speed strobed comparator which further maximizes the available settling time and further minimizes the probability of problems due to metastability. 
     SUMMARY OF THE INVENTION 
     A high speed strobed comparator circuit in accordance with the present invention provides a reliable circuit design technique for further reducing comparator propagation time and thereby increasing the available settling time. Such a comparator circuit further reduces errors associated with metastability by allowing a small fixed delay for the comparator to reach a stable state. If metastability occurs, the comparison function is terminated and the previous comparison result is preserved. 
     In accordance with one embodiment of the present invention, a strobed comparator circuit with reduced signal propagation time includes first and second bias nodes, a regenerative latch circuit and a reset control circuit. The first and second bias nodes are configured to receive first and second bias voltage potentials. The regenerative latch circuit is coupled between the first and second bias nodes and includes: an associated regenerative voltage level between the first and second bias voltage potentials; a reset state with an associated reset voltage level which is between the regenerative voltage level and the second bias voltage potential and which is closer to the regenerative voltage level than to the second bias voltage potential; and an active state in which the regenerative latch circuit is configured to receive a differential analog signal which includes first and second analog signal phases and in accordance therewith provide a differential digital signal which is latched when one of the first and second analog signal phases transcends the regenerative voltage level. The reset control circuit is coupled to the regenerative latch circuit and is configured to receive a reset activation signal and in accordance therewith force the regenerative latch circuit into the reset state. The regenerative latch circuit and the reset control circuit together conduct a substantially constant current via the first and second bias nodes during the reset and active states of the regenerative latch circuit. 
     In accordance with another embodiment of the present invention, a strobed comparator circuit for generating a synchronous digital signal corresponding to a difference between first and second analog signals includes first and second bias nodes, a regenerative latch circuit and a reset circuit. The first and second bias nodes are configured to receive first and second bias voltage potentials. The regenerative latch circuit is coupled between the first and second bias nodes and is configured to: receive first and second reset signals and in accordance therewith provide a differential output voltage signal with first and second output voltage signal phases having first and second reset voltage values which, during an asserted state of the first and second reset signals, are both substantially equal to a reset voltage potential between the first and second bias voltage potentials; and receive and compare first and second analog current signals and in accordance therewith provide the differential output voltage signal which, during a non-asserted state of the first and second reset signals, identifies which one of the first and second analog current signals has a larger magnitude. The reset circuit is coupled to the regenerative latch circuit and is configured to receive an activation signal and in accordance therewith provide the first and second reset signals and, during the asserted state of the first and second reset signals, receive and conduct the first and second analog current signals and establish the reset voltage potential. 
     These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a conventional strobed comparator circuit using a regenerative latch. 
     FIG. 2 is a schematic diagram of a strobed comparator circuit using a regenerative latch circuit in accordance with one embodiment of the present invention. 
     FIGS. 3A and 3B are signal timing diagrams for the circuit of FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, high speed strobed comparators often use regenerative latches which offer a number of advantages, such as high gain due to positive feedback, low power dissipation, and small integrated circuit area requirements. The differential voltage input IN 1  /IN 2  is connected to the NMOS differential amplifier M 11  l/M 21  which is biased by a current supply I bias . The drain currents of transistors M 11  and M 21  are replicated by two PMOS current mirror circuits M 12  /M 13 , M 22  /M 23 . With good matching of the transistors M 11 , M 21 , M 12 , M 13 , M 22 , M 23 , the larger of the two replicated currents I 1 , I 2  will correspond to the larger of the two input voltages IN 1 , IN 2 . 
     During the reset phase (i.e., when the reset/latch signal RESET/LATCH is high), NMOS transistors M 14  and M 24  are turned on, thereby discharging nodes A 1  and A 2  to circuit ground potential. The comparison, or latching, phase starts at the falling edge of the reset/latch signal RESET/LATCH, whereupon transistors M 14  and M 24  are turned off and the replicated currents I 1 , I 2  gradually increase the potentials at nodes A 1  and A 2  at rates which are proportional to the respective values of such currents I 1 , I 2  (e.g., at equal rates assuming substantially equal node capacitances at nodes A 1  and A 2 ). 
     Once the potential at one of the nodes A 1 , A 2  reaches the threshold value of its associated latch transistor (NMOS transistor M 25  for node A 1  and NMOS transistor M 15  for node A 2 ), the regenerative action takes place. For example, if the first current I 1  is greater than the second current I 2 , the potential at node A 1  reaches the NMOS transistor threshold voltage first, and, therefore, transistor M 25  is gradually turned on, thereby reducing the rate at which the potential at node A 2  continues to increase. Once transistor M 25  is fully turned on, node A 2  is discharged back to circuit ground potential, thereby turning transistor M 15  completely off. Accordingly, the latch condition is with node A 1  at a high potential and node A 2  at a low potential at least until the next rising edge of the reset/latch signal RESET/LATCH. 
     For many applications, the output of the comparator circuit needs to be held valid for an entire clock cycle, i.e., one full cycle of the reset/latch signal RESET/LATCH. Therefore, an output latch formed by two invertors INV 1 , INV 2  and two cross-coupled NAND gates NAND 1 , NAND 2  is used. In addition to latching and maintaining the output of the regenerative latch circuit, this output latch also buffers the sensitive internal nodes A 1 , A 2  from the output nodes providing the latched output signals Q, Q. 
     Referring to FIG. 2, a high speed comparator circuit with a regenerative latch circuit in accordance with one embodiment of the present invention includes some additional devices and/or circuitry for reducing the propagation delay and minimizing errors due to metastability. For example, an additional NMOS transistor M 20  is connected between the source terminals of transistors M 14  and M 24  and circuit ground. During the reset phase, i.e., when the reset/latch signal RESET/LATCH is high, nodes A 1  and A 2  are no longer discharged to circuit ground, but instead are discharged to a common potential which is close to the regenerative level of the cross-coupled transistors M 15 , M 25 . Accordingly, the propagation time is reduced since the delay in charging up the nodes A 1 , A 2  above the NMOS transistor threshold is reduced. The regenerative level for the cross-coupled NMOS transistors M 15 , M 25  can be calculated in accordance with the following: ##EQU1## where V th  is the threshold voltage and (W/L) 15 , 25 is the geometric aspect ratio of the transistors M 15 , M 25 , and K is the process constant which includes the electron mobility in the channel and oxide unit capacitance. 
     Equation (1) is valid for the circuits of FIGS. 1 and 2. However, for the circuit of FIG. 2, the common voltage of nodes A 1  and A 2  during the reset phase, neglecting the relatively small ON resistances of transistors M 14  and M 24  (approximately linear with large gate-to-source overdrive voltages), can be computed in accordance with the following: ##EQU2## 
     Based upon the foregoing, it can be seen that the difference between the regenerative level (equation 1) and the reset level (equation 2) has been substantially reduced without requiring the use of an additional cross-coupled pair of PMOS transistors. This is particularly advantageous since such an additional cross-coupled pair of transistors would generate substantial discharge currents, along with their associated switching noise. Furthermore, by maintaining current flow (of currents I 1  and I 2  via the alternate current paths provided by reset transistors M 14 , M 24  and M 20 ) rather than terminating such current flow, the circuit of FIG. 2 maintains a substantially constant draw of power supply current on the part of the regenerative latch. 
     The invertors INV 1 , INV 2  of the output latch should be designed with input threshold voltages which are slightly above the regeneration level at nodes A 1  and A 2  (equation 1). Under such a condition, during the reset phase and a metastable state, both of the intermediate output nodes B 1 , B 2  are in a high logic state. This is important due to the fact that when either one of these nodes, B 1 , B 2  is in a low logic state, thereby indicating that the regenerative transistor pair M 15 , M 25  has been triggered, the result is stored by the output latch NAND 1 , NAND 2 . At the same time, the &#34;comparison done&#34; CMP --  DONE output from the comparison circuit NAND 4  becomes active in a high logic state. 
     The circuit of FIG. 2 also includes additional circuitry to minimize errors due to metastability on the part of the regenerative latch circuit. A metastable state occurs when nodes A 1  and A 2  stay at the common regenerative level. Under this condition, the intermediate output latch nodes B 1  and B 2  are in high logic states. This condition can persist until the next rising edge of the reset signal at node R which is generated by the digital timer circuit implemented with invertors INV 3  through INV 2k  and NAND gate NAND 3 . The number of invertors connected between nodes D and E is odd and the total propagation delay of such invertors determines the width of the low logic state of the signal at node R which represents the active comparison state. Accordingly, the signal at node E is an inverted and time-delayed version of the signal at node D. 
     Referring to FIGS. 3A and 3B, the reset transistors M 14 , M 24  are turned on at the rising edge of the signal at node R and nodes A 1  and A 2  are discharged to the common reset potential V reset  as determined in accordance with equation 2. The signal at node E activates the comparison done signal CMP --  DONE. The resulting timing relationships among the signals are as represented in FIG. 3A for maximum delay conditions, i.e., where intermediate output latch nodes B 1  and B 2  both stay in high logic states, and in FIG. 3B for the normal condition where one of the intermediate nodes B 1 , B 2  goes to a low logic state during the comparison phase of operation. Hence, the timing relationships of FIG. 3A correspond to periods of metastable conditions, while the timing relationships of FIG. 3B correspond to periods of stable conditions. 
     Based upon the foregoing, it can be seen that improved, i.e., reduced, propagation delay is achieved without causing large transients in the values of supply current drawn from the power supply, thereby minimizing switching noise. Further, to optimize the trade-off between settling time and propagation delay an additional output signal is provided to indicate the completion of the comparison phase and to initiate the hold phase. Further still, problems associated with metastability are minimized by allowing only a small fixed maximum delay for the comparator circuit to reach its stable state. If, by the end of such delay period, a metastable state exists, the present comparison result is discarded and the previous comparison result is preserved until such time as another comparison has taken place and a stable state has been achieved. 
     Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.