Abstract:
The physical layout of a semiconductor memory device having memory sectors of varying sizes can be arranged such that the larger and smaller memory sectors are addressed by x-decoders and y-decoders via word lines and bit lines, respectively. The smaller memory sectors are laid out such that some of the small memory sectors are connected with a y-decoder or multiple y-decoders via different bit-lines. The smaller memory sectors are interspersed with the large memory sectors and an area near a corner of the memory device that can be used for other components such as peripheral devices. Optional physical to logical mapping of address allow the smaller memory sectors to be addressed in the first or the last memory addresses.

Description:
BACKGROUND 
     The present invention relates generally to a method of laying out memory sectors. 
     Flash memory devices have been widely used in computers and mobile devices such as cellular telephones, digital cameras, and video games. The flash memory devices can include a memory array, an address decoder, and data lines. The memory array is often divided into sectors. Flash memory devices can have sector protection that protects the data stored in a memory sector; the sector protection blocks the erase and program functions. Multiple sectors can be protected at one time; the status of protection for each memory sector is stored. A memory sector includes one or more memory cells. 
     As illustrated in FIG. 1, a memory array  100  includes a set of memory sectors  102 , y-decoders  110 ,  112 ,  114 ,  116 , x-decoders  120 ,  122 , and peripheral circuits  130 ,  132 ,  134 . The memory sectors  102  are arranged in regular geometric patterns comprising rows and columns. The memory sectors  102  are of uniform physical dimensions and each hold the same amount of data. 
     BRIEF SUMMARY 
     The physical layout of a semiconductor memory device having memory sectors of varying sizes can be arranged such that the larger and smaller memory sectors are addressed by x-decoders and y-decoders via word lines and bit lines, respectively. The smaller memory sectors are laid out such that at least some of the small memory sectors are connected with a y-decoder or multiple y-decoders via different bit-lines. Such a bit-line can connect with smaller and larger memory sectors to a y-decoder. The smaller memory sectors are interspersed with the large memory sectors and an area near a corner of the memory device that can be used for other components such as peripheral devices. Optional physical to logical mapping of address allow the smaller memory sectors to be addressed in the first or the last memory addresses. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is described with reference to the accompanying figures. In the figures, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. 
     FIG. 1 is an illustration of a conventional memory array with a set of uniform sized memory sectors; 
     FIG. 2 is an illustration of a memory array with two sets of memory sectors with reduced area for peripheral circuits; and 
     FIG. 3 an illustration of a memory array with two sets of memory sectors with increase are for peripheral circuits. 
    
    
     DETAILED DESCRIPTION 
     The physical layout of a memory array with memory sectors of varying sizes can be made by arranging the memory cells such that a residual area is located near a corner of the memory array that is not traversed by data lines, address lines or control lines. Optionally, a modified addressing scheme is used to translate the physical addresses to the logical addresses. 
     Conventional memory arrays use regularly located memory sectors as illustrated in FIG.  1 . However, it is often desirable to have memory sectors of varying sizes in a single memory array. A common application where varying sized memory sectors are use is where it is desirable to have a memory sector dedicated to a specific task. Since memory can be locked sector-by-sector, it is desirable to have a memory sector dedicated to the specific task. Since the memory sectors are individually lockable and unlockable, it is desirable to match the size of the memory sector with the size of the data to be stored in each sector. It is desirable to be able to address the memory array containing memory sectors of various sizes in the same manner as conventional memory arrays. Thus, it is preferred that the size of the memory array remains the same whether the memory sectors have uniform memory size or whether the memory sectors include memory sectors of various memory sizes. Thus, in one embodiment the second size memory sectors have a total memory size equal to one or more of the first size memory sectors. 
     As illustrated in FIG. 2, a memory array  200  includes a set of large memory sectors  202 , a set of small memory sectors  208 A,  208 B,  208 C,  208 D, x-decoders  220 ,  222 , y-decoders  210 ,  212 ,  214 ,  216 , and peripheral circuits  230 ,  232 ,  234 . The large memory sectors  202  are labeled Sector  00 , Sector  01  . . . Sector  26 . An advantage of this configuration is that the y-decoder  216  and the x-decoder  222  have a similar addressing scheme as conventional y-decoder  116  (FIG. 1) and x-decoder  122  (FIG.  1 ). 
     The small memory sectors  208 A,  208 B,  208 C,  208 D and the large memory sectors  202  can not be arranged in a simple rectangular area. This results in a reduction of the available space for peripheral circuits  234 . Further, the word-lines the connect the x-decoder with the small memory sectors  208 A-D require more area. This results in the for the is reduced to accommodate the additional physical space required for the small memory sectors  208 A-D being shifted to the left. Also, such word-lines have undesirable characteristics including: different lengths and multiple right angle turns. 
     As illustrated in FIG. 3, a memory array  300  includes a set of large memory sectors  302 , a set of small memory sectors  308 A,  308 B,  308 C,  308 D, x-decoders  320 ,  322 , y-decoders  310 ,  312 ,  314 ,  316 , and the optional peripheral circuits  330 ,  332 ,  334 . The large memory sectors  302  are labeled Sector  00 , Sector  01  . . . Sector  26 . 
     The large memory sectors  302  are typically substantially rectangular when viewed from above the memory array, as illustrated in FIG.  3 . However, the large memory sectors  302  can be other shapes. The large memory sectors  302  have dimensions normally measured in the X and Y directions. When large memory sectors  302  is rectangular, its physical dimensions are its length in the X and Y directions. small memory sectors  308 A,  308 B,  308 C,  308 D ( 308 A-D) are arranged such that they are aligned with the y-decoders and the x-decoders. By aligning the small memory sectors  308 A-D is this manner, the area required for routing the signal lines from the y-decoders and the x-decoders is reduced. As illustrated by comparing FIGS. 2 and 3, the height of the peripheral circuits  334  (FIG. 3) is less than the height of the peripheral circuits  234  (FIG.  2 ). However, the width of the peripheral circuits  334  is greater than the width of the peripheral circuits  234 . Additionally, the peripheral circuits  334  in FIG. 3 also includes an additional area (also called a residual area) for peripheral circuits  334 A. Indeed, the total area for peripheral circuits  334 ,  334 A is over a third larger than the area for peripheral circuits  234 . The creation of the additional area for peripheral circuits, especially near a corner of the memory array  300  is a benefit of the present invention. 
     The small memory sectors  308 A-D are typically substantially rectangular when viewed from above the memory array, as illustrated in FIG.  3 . However, the small memory sectors  308 A-D can be other shapes. The small memory sectors  308 A-D have dimensions normally measured in the X and Y directions. When small memory sectors  308 A-D is rectangular, its physical dimensions are its length in the X and Y directions. The large memory sectors  302  have a dimension that is greater than a dimension of the small memory sectors  308 A-D. In a preferred embodiment, the smaller memory sectors  308 A-D have the same width (x-axis dimension as shown in FIG. 3) as the larger memory sectors  302 . This provides for a more uniform layout of the memory sectors. Consequently, the height of such small memory sectors  308 A-D is preferably less than the height of the larger memory sectors  302 . 
     It is preferred that in the embodiment shown in FIG. 3, the y-decoders  314 ,  316  and x-decoder  322  handle any logical to physical address mapping. It is desirable to have the small memory sectors  308 A-D addressed as either the first or last logical memory addresses. Because the small memory sectors  308 A-D are physically located between large memory sectors  302 , a logical to physical address mapping is desirable. 
     The small memory sectors  308 A-D have smaller memory capacity than the large memory sectors  302 . It is preferred that the sum of the memory capacity of the small memory sectors  308 A-D be substantially a whole number multiple of the memory capacity of a large memory sector  302 . For example, the small memory sectors  308 A-D can have a memory capacity of one-quarter of the memory capacity of a large memory sector  302 . The small memory sectors  308 A-D can have different memory capacities. For example, if the memory array  300  had only three small memory sectors, the small memory sectors could have memory capacities of substantially one-half, one-quarter, and one-quarter the memory capacity of a large memory sector  302 . 
     It is preferred that the additional area for peripheral circuits  334 A is located near a corner of the memory array  300 . Circuits are more easily located in areas closer to corners of the memory array because the corner areas can easily have signal lines route to circuits in the corners from both the X and the Y directions. The optional peripheral circuits  330 ,  332 , and  334  can be any circuit. It is preferred that the peripheral circuits  330 ,  332 , and  334  be related to the memory array  300 . 
     In an embodiment shown in FIG. 3, each of the small memory sectors  308 A-D are connected to one of the y-decoders  310 ,  312 ,  314 , and  316  via a different bit-line. That is, only one small sector  308 A-D is connected with each bit-line. Such bit-lines can also connect larger memory sectors  302  to the y-decoders  310 ,  312 ,  314 , and  316 . The memory sectors  302 ,  308 A-D are connected to the x-decoder via word-lines and to the y-decoders via bit-lines. 
     While FIG. 3 illustrates a memory array with two x-decoders and four y-decoders, the present invention can be applied to memory arrays with various numbers of x-decoders and y-decoders. For example, the memory array  300  could have only one x-decoder and only one y-decoder or it could have a single decoding means. Alternatively, the memory array  300  could have a large number of x-decoders and y-decoders. 
     While preferred embodiments have been shown and described, it will be understood that they are not intended to limit the disclosure, but rather it is intended to cover all modifications and alternative methods and apparatuses falling within the spirit and scope of the invention as defined in the appended claims or their equivalents.