Abstract:
A combinatorial digital filter apparatus utilizing a second order filter in which bits are processed simultaneously rather than serially.

Description:
STATEMENT OF GOVERNMENT INTEREST 
     The invention described herein may be manufactured and used by or for the Government for governmental purposes without the payment of any royalty thereon. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates broadly to digital filters and in particular to a combinatorial digital filter apparatus of the second order. 
     In the present state of art, digital filters have become increasingly attractive as replacements for analog filters due to recent advances in semi-conductor technology. As the speed of machine operations increase, either to permit real time processing of wideband signals or to time-share the arithmetic unit, there is a resultant rapid increase in hardware complexity, as measured by the number of IC&#39;s used, and in power consumption. The major factor causing this increase, lies with the wide spread use high speed multipliers to perform the required operations. 
     Researchers in the field have proposed an approach to the implementation of digital filters that is well suited to LSI construction. These technological advances center about a very efficient serial multiplier that produces a rounded binary number, and lends itself particularly well to multiplexed circuit operation. Using current TTL technology, multipliers of this type can accommodate a bit rate of approximately 25 MHz. The present invention provides a new approach for the hardware implementation of fixed point arithmetic digital filters. The new realization calls for the storing of the finite number of possible outcomes of an intermediate arithmetic operation, and using them to obtain the next output sample through repeated addition and shifting operations, thereby no multiplications are required. In addition, the present approach provides digital filters which operate at speeds that are difficult or impossible to achieve with the existing state of the art. 
     SUMMARY 
     The present invention utilizes a plurality of storage registers to store a finite number of mathematical results of an intermediate arithmetic operation which are used in repeated addition and shifting operations to provide a further output sample. The use of shift registers for data processing operations provides the flexibility of greatly increased operating speeds. 
     It is one object of the invention, therefore, to provide an improved digital filter apparatus to simultaneously process data bits. 
     It is another object of the invention to provide an improved digital filter apparatus which stores a finite number of intermediate arithmetic possibilities for further processing. 
     It is yet another object of the invention to provide an improved digital filter apparatus wherein repeated addition and shifting operations are utilized to process data. 
     These and other advantages, objects of the invention will become more apparent from the following description taken in connection with the illustrative embodiment in the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a combinatorial digital filter apparatus in accordance with the present invention, and, 
     FIG. 2 is a block diagram of a second order digital filter apparatus in a high speed configuration. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The operation of the combinatorial digital filter apparatus may be approximated by an N-th order digital filter which is characterized by an input-output relationship of the form ##EQU1## where {X n  } is the input sequence, {Y n  } the output sequence, and {a j  }{b j  } are the filter coefficients. 
     It will be recognized that the filter specified by equation (1) may be constructed with a basic building block of second order sections that may be connected in either parallel or cascade. The use of the second order sections as building blocks provides many practical advantages, such as better noise performance and more stable operation. It will also be recognized that the filter specified by equation (1) include the class of nonrecursive filters for which the coefficient {b i  } are all zero. 
     A second order section may be defined by an input output relationship. 
     
         Y.sub.n = a.sub.o x.sub.n +a.sub.1 x.sub.n.sub.-1 +a.sub.2 x.sub.n.sub.-2 -b.sub.1 Y.sub.n.sub.-1 -b.sub.2 Y.sub.n.sub.-2           (2) 
    
     Assuming that x n  and Y n  are represented in the arithmetic processor in a 2&#39;s complement code, with B binary bits, including sign bit, i.e., ##EQU2## Upon substituting equation (3) into equation (2) the following is obtained: ##EQU3## Defining the function with five binary arguments as follows: 
     
         φ (x.sup.1, x.sup.2, x.sup.3, x.sup.4, x.sup.5)= a.sub.0 x.sup.1 +a.sub.2 x.sup.2 +a.sub.3 x.sup.3 -b.sub.1 x.sup.4 -b.sub.2 x.sup.5, x.sup.j =0 or 1                                           (5) 
    
     then equation (5) may be rewritten as follows: ##EQU4## Since x j  can take on only the values 0 or 1 the function φ has only 2 5  =32 possible values. These values may be precomputed and stored in advance in a read only memory (ROM) or random access memory (RAM), or may be determined by a combinatorial circuit, such as programmable logic array. The bits (x n ,x n   -1 , x n   -2 ,Y n   -1 , Y n   -2 ) are used either to address the ROM or RAM or as input to the combinatorial circuit. Therefore, equation (7) can be mechanized using addition/subtraction and shifting operations only. FIG. 1 depicts the block diagram of a second order section which is realized through equation (7). The block diagram shown in FIG. 1 may be implemented with commercially available intetrated circuits and/or combinations thereof (mainly shift registers, adders and ROM&#39;s or RAM&#39;s. The absence of multipliers is evident. 
     There is shown in FIG. 1 a block diagram of a second order digital filter apparatus in which the data is entered into shift registers SR1-SR4, with the least significant bit leading. At each shift, a new vector (x n   j  , x n   -1   j  , x n   -2   j , Y n   -1   j , Y n   -2   j ) appears at the input of the circuit realizing φ. The output φ is loaded into register R5 which is connected to one of the two inputs of the accumulator with a sign change for j = 0. The other input of the accumulator is hardwired to the output register (R6) with a 1 bit right shift. After B such shifts, the value in register R6 is rounded and the accumulator cleared. This rounded value is Y n , which is shifted serially into SR3, and the processor is ready to compute the next sample Y n   +1 . 
     Table 1 below gives an example of a typical second-order section and its corresponding function defined by its truth table with B = 8. 
     
                       TABLE I______________________________________MEMORY MAP FOR SECOND-ORDER SECTIONMEMORY ADDRESS      CONTENTS______________________________________0   0     0     0   0         0   0   0   0   0   0                     0   0                     0   0 0 0 1  1 1 0 0 0 1 1 0                     0   0 0 1 0  0 1 1 1 0 1 0 0                     0   0 0 1 1  0 0 1 1 1 0 0 1                     0   0 1 0 0  0 0 0 0 0 1 1 0                     0   0 1 0 1  1 1 0 0 1 1 0 0                     0   0 1 1 0  0 1 1 1 1 0 1 0                     0   0 1 1 1  0 0 1 1 1 1 1 1                     0   1 0 0 0  1 1 1 1 0 1 0 1                     0   1 0 0 1  1 0 1 1 1 0 1 1                     0   1 0 1 0  0 1 1 0 1 0 0 1                     0   1 0 1 1  0 0 1 0 1 1 1 1                     0   1 1 0 0  1 1 1 1 1 0 1 1                     0   1 1 0 1  1 1 0 0 0 0 0 1                     0   1 1 1 0  0 1 1 0 1 1 1 1                     0   1 1 1 1  0 0 1 1 0 1 0 1                     1   0 0 0 0  0 0 0 0 0 1 1 0                     1   0 0 0 1  1 1 0 0 1 1 0 0                     1   0 0 1 0  0 1 1 1 1 0 1 0                     1   0 0 1 1  0 0 1 1 1 1 1 1                     1   0 1 0 0  0 0 0 0 1 1 0 0                     1   0 1 0 1  1 1 0 1 0 0 1 0                     1   0 1 1 0  0 1 1 1 1 1 1 1                     1   0 1 1 1  0 1 0 0 0 1 0 1                     1   1 0 0 0  1 1 1 1 1 0 1 1                     1   1 0 0 1  1 1 0 0 0 0 0 1                     1   1 0 1 0  0 1 1 0 1 1 1 1                     1   1 0 1 1  0 0 1 1 0 1 0 1                     1   1 1 0 0  0 0 0 0 0 0 1 0                     1   1 1 0 1  1 1 0 0 0 1 1 1                     1   1 1 1 0  0 1 1 1 0 1 0 1                     1   1 1 1 1  0 0 1 1 1 0 1 1     sign bit   ↑↑  binary point______________________________________ 
    
     words. In this example, a 1  = 0.095 , a 2  = -0.1665478 , a 3  = 0.095 , b 1  = 01.8080353, and b 2  = 0.9129197. The five columns of the memory address correspond to the five binary arguments of the function, i.e., (x n   j  , x n   -1   j  , x n   -2   j , Y n   -1   j , Y n   -2   j ). The first bit in the contents is the sign bit and the binary point is to the right of the sign bit. Here φ has been scaled down by 2 to avoid overflow. 
     There is shown in FIG. 2 another possible mechanization equation of (7) for the case of 8 bit data. Here data are loaded in parallel into R1 to R5 and there are eight separate but identical ROM&#39;s (RAM&#39;s) storing the values of the function. The outputs of the ROM&#39;s (RAM&#39;s) 0 to 7, are added in a tree like structure with a proper number of shifts hardwired, using seven adders in this case. Thus, by providing each adder with two storage registers, concurrent (pipelining) operation of all levels is possible. It is clear from the above that the number of bits used for the data will only determine the number of levels needed and will not affect the throughput rate. For B bit data, the configuration consists of five ROM&#39;s (RAM&#39;s) and (B-1) adders. 
     As an example, consider B = 8. Using standard TTL IC and bipolar memory, a word rate of 20 MHz for the second order section in FIG. 2 may be achieved. The package count is 60 IX&#39;s and the power consumption 24 watts. This word rate implies that the section can operate in real time on a signal with a 10 MHz bandwidth. It should be noted that to achieve such a speed using multipliers, it would be very difficult or impossible unless several ECL multipliers are used. Such multipliers dissipate considerably more power and have a high-package count (e.g., a 9 × 9-bit multiplier performs the multiplication in 35 ns and has 36 IC&#39;s dissipating 12.6 watts). If ECL IC&#39;s are used to implement the section of FIG. 2, it is possible to realize a 50 MHz word rate, an operating speed unachievable using present multipliers. Clearly, the two mechanizations of equation (7) which are illustrated in FIGS. 1 and 2 represent two extreme cases. In the first one the data bits are processed serially, while in the second one, all data bits are processed in parallel. Configurations that fall between these two extremes are also possible by operating k data bits 1 k B. The resulting system will have an operating speed between 2 MHz to 20 MHz word rate with a package count between 20 IC&#39;s to 60 IC&#39;s. 
     The new filter structure can be used to implement directly an N-th order filter, N 2. In this case, equation (6) becomes ##EQU5## where x k   j , and Y k   j  are the j-th bit of x k  and Y k  respectively. The function φ is a function of 2 2N   +1  binary arguments, defined by ##EQU6## It can only take 2 2N   +1  possible values. These may be stored in a ROM (RAM) which is addressed by the bits (x n   j , x n   -1   j , Y n   -1   j  . . . Y n   -N   j ). The overall filter configuration is similar to FIG. 1 but with (N+1) data registers for the input samples (x n ), N data registers for the output samples (Y n ) and the ROM (RAM) now has 2N+1 inputs. Similarly, it is also possible to operate several bits simultaneously and arriving at a configuration similar to that of FIG. 2 but with 2N+1 data registers and each ROM(RAM) has 2N+1 inputs. 
     Although the invention has been described with reference to a particular embodiment, it will be understood to those skilled in the art that the invention is capable of a variety of alternative embodiments within the spirit and scope of the amended claims.