Abstract:
An apparatus and method for visualizing faults in a circuit design includes simulating faults for a circuit design in a layout and a schematic, editing the layout and schematic to include the simulated fault, and linking the layout and schematic with the fault simulation.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application is related to U.S. application Ser. No. 13/683,810, entitled “System and Method For Fault Sensitivity Analysis Of Mixed-Signal Integrated Circuit Designs”, filed on the same day as the present application. This related application is hereby incorporated by reference in its entirety. 
     The present application also is related to U.S. application Ser. No. 13/683,853, entitled “System and Method For Fault Sensitivity Analysis Of Digitally-Calibrated-Circuit Designs”, filed on the same day as the present application. This related application is hereby incorporated by reference in its entirety. 
     BACKGROUND 
     The integrated circuit (“IC”) industry faces the challenge of reducing yield loss caused by defects during manufacturing. These defects can be either random defects or systematic defects. Random defects, as the name implies, result from random occurrences such as particulate contamination. Systematic defects are non-random and result from problems with the manufacturing process and/or IC design. Systematic defects will reoccur when a manufacturer uses a similar process or IC design. A designer may be able to categorize or anticipate certain systematic defects based on a shape or feature pattern on an IC. 
     As the IC industry moves to smaller IC features, an increasing number of various subtle design processes exist for manufacturing the ICs. Each subtle design process may cause unique systematic defects, thus increasing the number and type of systematic defects present in a manufactured IC. Circuit designers use a combination of various tools to reduce these systematic defects. While these tools help designers to account for systematic defects during the IC design process, the tools are often poorly integrated, if integrated at all, thus making designing robust fault free ICs difficult. Designers need a fault diagnostic system which allows for conducting fault analysis and visualization of the simulated faults in a schematic or layout. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating components of an exemplary fault analysis visualization system according to an embodiment. 
         FIG. 2  is a block diagram illustrating an embodiment of a fault analysis visualization method. 
         FIG. 3  is an exemplary flow chart of a fault generator using inductive fault analysis. 
         FIG. 4A  is an exemplary block diagram of the databases that a back annotation tool references or edits according to an embodiment. 
         FIG. 4B  is an exemplary flow chart of implementation of a back annotation tool according to an embodiment 
     
    
    
     DETAILED DESCRIPTION 
     As will be described hereinafter in greater detail, one aspect of the present invention relates to an analog fault visualization system and method by extracting data from a schematic and/or layout; creating a netlist; creating a fault list; simulating faults; and providing the faults in a schematic and/or layout editor for visualization, debugging, and/or modification. For purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present invention. Description of specific applications and methods are provided only as examples. Various modifications to the embodiments will be readily apparent to those skilled in the art and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Thus the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and steps disclosed herein. 
       FIG. 1  is a block diagram illustrating components of an exemplary analog fault visualization system  100  according to an embodiment. This system may provide simulator functionality, as will be discussed in greater detail below. A user may access the analog fault visualization system through a standalone client system, client-server environment, or a network environment. System  100  may comprise one or more clients or servers  110 , one or more storage systems  120 , and one or more connection  130  between and among these elements. 
     Client  110  may execute instructions stored on a computer readable medium that provides a user interface  111  which allows a user to access storage system  120 . According to an aspect of an embodiment, the instructions may be part of a software program or executable file that operates Electronic Design Automation (EDA) software. Client  110  may be any computing system, such as a personal computer, workstation, or other device employing a processor which is able to execute programming instructions. User interface  111  may be a GUI run in a user-controlled application window on a display. A user may interact with user interface  111  through one or more input/output (I/O) devices  114  such as a keyboard, a mouse, or a touch screen. 
     Storage system  120  may take any number of forms, including but not limited to a server with one or more storage devices attached to it, a storage area network, or one or a plurality of non-transitory computer readable media. In an aspect of one embodiment, databases  121  may be stored in storage system  120  such that they may be persistent, retrieved, or edited by the user. Databases  121  may include a schematic database  121 A, a layout database  121 B, and a user settings database  121 C. Databases  121  may also include other databases not listed but used in the system such as a netlist database, fault database, etc. These databases may be kept as separate files or systems, or may be merged together in any appropriate combination. 
     According to an aspect of an embodiment, only one client  110  is connected to storage system  120  through connection  130 , which may be a simple direct wired or wireless connection, a system bus, a network connection, or the like, to provide client  110  with access to storage system  120 . In another aspect, connection  130  may enable multiple clients  110  to connect to storage system  120 . The connection may be port of a local area network, a wide area network, or another type of network, again providing one or more clients with access to storage system  120 . Depending on system administrator settings, client  110 &#39;s access to system storage  120  or to other clients may be limited. 
       FIG. 2  is a block diagram illustrating one method of implementing the analog fault visualization system  200 . Analog fault visualization system  200  begins by receiving a data representation of a circuit design in the form of schematic data  201  and layout data  202 . Schematic data  201  may describe all of the electrical components and their relationships within the circuit design. Layout data  202  may describe the physical representation, including the specific shapes and geometric elements, of the circuit design for manufacturing. 
     An extraction tool  203  extracts information from schematic data  201  and layout data  202 . Extraction tool  203  may extract the data for particular shapes and geometric elements associated with higher probability of faults from layout data  202 . Extraction tool  203  may also extract devices, such as transistors, resistors, capacitors, inductors, diodes, or any other fundamental circuit elements, and their connectivity from schematic data  201 , and may combine the data extracted from schematic data  201  and layout data  202  to create fault view data  204 . In one embodiment, extraction tool  203  may combine all the information in schematic data  201  with layout data  202  to create fault view data  204 . Schematic data  201 , layout data  202 , and fault view data  204  may be in an EDA data format such as those used in OpenAccess, GDSII, OASIS, SEMI, Milkyway, or EDDM. It is within the contemplation of the invention to employ any other desired format as the EDA data format. Different data formats have certain naming conventions and rules, commonly referred to as a “namespace.” Different data format may use different namespaces and may have rules which make device names from one space to another incompatible. For example, one namespace may use the “-” character in a device name but another namespace may reserve the “-” character for other functions. Thus, device name “node-1” may be incompatible with certain namespaces. Some examples of namespaces are CDBA, CDBAFlat, Spectre, and SPICE. This exemplary listing is not intended to be exhaustive or limiting. The proper focus is on the more general namespace concept, rather than any particular namespace. 
     Additionally, when extraction tool  203  creates fault view data  204 , it may group or expand similar devices. Multiples of a device connected in parallel (“m-factored devices”) or in series (“s-factored devices”) may be grouped together. For example, there may be three separate instances of a resistor connected in parallel named A — 1, A — 2, and A — 3 which are grouped as a single device A_m3. Thus, in one database, a group of resistors may have unique names, while another database may use a single name for the group. As a result, these databases may use different namespaces. 
     In one embodiment, schematic data  201 , layout data  202 , and fault view data  204  use the same namespace. Fault view data  204  may contain information that maps grouped devices to their extracted counterparts. In another embodiment, different namespaces may be used, and extraction tool  203  may conduct a namespace transformation. In such a case, fault view data  204  may track and map the transformation. For example, “node-1” may be mapped to “node — 1.” In one embodiment, extraction tool  203  may be a parasitic extractor tool. 
     Netlister  205  is a tool that transforms a connectivity source such as a schematic or layout into a textual netlist. A netlist may be a textual coded description of every element, part, device, and connection in the schematic/layout. EDA tools commonly use netlists for simulating circuitry. In one embodiment, netlister  205  uses the information in fault view data  204  to create fault free netlist  206  which is a netlist of the original schematic/layout. When the netlister transforms a schematic/layout into a netlist, the namespace of the netlist may differ from the schematic/layout. In one embodiment, fault free netlist  206  may also store a namespace map between fault view data  204  and fault free netlist  206 . In one embodiment, certain devices in the schematic or layout may be grouped in the fault-free netlist  206  depending on the type of fault analysis implemented. For example, if a user is only simulating bridge faults, an m-factored device may be reduced to a single device in netlist  206  because a short in a parallel circuit will effectively short the entire group of m-factored devices. In this case, netlist  206  may contain a namespace map for the grouped devices. 
     Fault generator  207  uses information in fault view data  204  to generate fault list  208 . Fault list  208  may be in the same namespace as fault-free netlist  206 . In an alternative embodiment, fault generator  207  may be integrated with extraction tool  203 . Fault generator  207  may use one or more algorithms for generating fault list  208 . For example, faults may be generated using a fault generation algorithm such as RC based bridge pair extraction, inductive fault analysis, DFM Aware Bridge Pair Extraction, etc. 
       FIG. 3  is an exemplary flow chart depicting one implementation of a fault generator using one method of inductive fault analysis. At  301 , fault generator  300  determines an approximation of the min-width spacing rules for the circuit. Min-width is the minimum distance that must separate features, shapes, or geometries from each other for manufacturing. Fault generator  300  may approximate min-width by identifying the shortest feature spacing in the design layout. In another embodiment, min-width may be provided in a constraint specification provided by an IC manufacturer. 
     At  302 , fault generator  300  may search the design layout for net pairs that are within a multiple of min-width distance of each other. A user input or predetermined default value may be used as the multiple. 
     At  303 , fault generator  300  provides the resulting net pairs as faults in a fault list. In one embodiment, a user may limit the number of faults that fault generator  300  provides. In yet another embodiment, fault generator  300  may be encoded to provide a limited number of faults. If the fault limit is less than the number of faults that fault generator  300  detects, fault generator  300  may provide faults based on the probability of a defect. Fault generator  300  may determine the likelihood of a defect by analyzing the parallel run lengths of the resultant net pairs. The longer the parallel run length, the more likely it is that a defect will occur. In another embodiment, fault generator  300  may compute defect probabilities for a net pair by utilizing defect density equations or coefficients provided by an IC manufacturer. 
     Referring back to  FIG. 2 , fault generator  207  may provide a description of every generated fault as fault list  208 . Fault list  208  may contain a unique name of every fault generated, the type of fault, and the fault&#39;s parameters. For example, one of the generated faults may be a bridge fault. A bridge fault occurs when separate nodes are shorted together due to a defect. Fault list  208  may provide a unique name for the bridge fault and the nodes that are affected by the bridge fault, i.e., the two nodes that are shorted, and a resistance value between the nodes. 
     The type of information about a fault may vary from fault type to fault type. For instance, fault list  208  may contain an open fault which was generated by fault generator  207 . Open faults occur when a connection in a node is split into two, the original node and a fault node. Fault list  208  may specify the resistance between the original node and the fault node and which terminal for each instance is connected to which node. In one embodiment, fault list  208  may provide a numerical terminal list for each terminal of each instance. Fault list  208  may provide terminal numbers to determine which terminals are connected to the fault node. In one embodiment, fault list  208  may be in a format similar to a netlist such that a tool may use fault list  208  for simulation. 
     Simulator  209  references fault free netlist  206  and fault list  208  to conduct a fault sensitivity analysis on the circuit design. Simulator  209  may use the fault free netlist  206  to simulate the circuit design while including one or more faults in fault list  208 . Simulator  209  may continue to conduct circuit simulations of the circuit design until a circuit response is provided for every fault. Simulator  209  may create a fault table dataset  210 , which may contain the solution values for each fault from the simulation. The list of faults and corresponding simulation results may be displayed as a table on a GUI in connection with other EDA software. Simulator  209  may also create fault waveform dataset  211 , which contains information for creating a graphical representation of electrical signals in a circuit against time. Tools such as a waveform viewer may use the fault waveform dataset to display the waveform. As noted earlier, the system  100  in  FIG. 1  may function as a simulator, among other things. 
     Back annotation tool  212  may annotate/edit a circuit design schematic or layout to include faults from fault table  210  or from fault list  208 . Back annotation tool  212  may also be used to link a fault in fault table dataset  210 , and/or fault list  208  and/or a waveform in waveform dataset  211  to the corresponding annotations in the schematic and/or layout. Back annotation tool  212  may identify the particular node in the schematic that corresponds to a user selected waveform from waveform dataset  211 . Back annotation tool  212  may also identify shapes in the layout associated with the corresponding fault nodes when a user selects a fault from fault table dataset  210  or fault list  208 . 
       FIG. 4A  diagrams the databases that back annotation tool  212  of  FIG. 2  references or edits according to an embodiment. Database  401  and  402  contain fault tables and fault waveforms which may be provided by a circuit simulation tool. Database  403  is a schematic or layout database which contains information regarding a circuit design in a particular data format. Database  404 A is a fault view (FV) database which may be partly created from database  403 . Database  404 A may be in the same data format as database  403  and may use the same namespace. Alternatively, database  404 A may use a different namespace from database  403  and may contain namespace mapping (NSM)  404 B between the namespace(s) used in databases  403  and  404 A. Database  405 A is a fault free (FF) netlist database which contains namespace mapping  405 B between the netlist data and the fault view data. Database  406  is a fault list database which contains information regarding the faults used by a circuit simulation tool to create database  401  and  402 . Database  406  may contain the node and connectivity information for each fault. 
       FIG. 4B  is a flow chart for implementation of a back annotation tool according to an embodiment. At  41 , the back annotation tool may retrieve or receive fault tables and fault waveforms for a particular schematic or layout. At  42 , the back annotation tool may retrieve or receive information regarding individual faults within the fault list database corresponding to the faults in the fault table and waveforms. The information may include connection information regarding each fault and the respective nodes that are affected. At  43 , the back annotation tool may reference the namespace map in the netlist database and fault view database to translate the faults and nodes from the fault list to the data format of the schematic or layout database. At  44 , the back annotation tool may edit the schematic or layout database to include faults in the original schematic or layout. When a layout or schematic editor displays the circuit design on a GUI using the edited layout/schematic database, the circuit design may also display faults integrated into the circuit. In one embodiment, two annotation tools are used, one for editing a layout and the other for editing a schematic. In one embodiment, instead of each database containing name mappings, each database may use well known namespaces such as CDBA, CDBAFlat, Spectre, SPICE, etc. and may use a name mapping utility to map names from one namespace to another. 
     In one embodiment, the back annotation tool may take advantage of certain characteristics of a schematic or layout database to present faults on a schematic or layout. For example, some databases use marker objects for indicating design violations. The oaMarker object in OpenAccess is one such marker object. In one embodiment, the back annotation tool may replace shapes in a layout with oaMarker objects to indicate a fault. 
     While particular embodiments of the present invention have been described, it is to be understood that various different modifications within the scope and spirit of the invention are possible. The invention is limited only by the scope of the appended claims.