Abstract:
In order to provide a method for producing a SiC-MOSFET capable of increasing V th  without deteriorating channel mobility, before forming a gate insulation film, (a) silicon carbide substrate is oxidized by a low temperature oxidation method represented by plasma oxidation to form a silicon oxide film. Next, (b) the silicon oxide film is removed. After repeating the processes (a) and (b) once or more, (c) the gate insulation film is formed.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to a sacrificial oxidation film used in a method for producing a silicon carbide semiconductor device. 
       BACKGROUND ART 
       [0002]    A general method for producing a SiC-MOSFET will be hereinafter described. First, a SiC epitaxial layer is formed on a SiC substrate. Then, ion implantation of an impurity, which is to be a dopant, is carried out with respect to a drain region, a base region, and a source region. Next, activation annealing is carried out with respect to the ion-implanted impurity. In a case of annealing, for example, a carbon film with excellent heat resistance is deposited as a cap material so that Si in the SiC substrate is not sublimed. Then, the carbon film is treated with heat treatment at temperature of 1600° C. or more. After that, a carbon layer of the cap material is removed by oxygen plasma asking or by heat treatment under oxygen atmosphere, for example, at around 900° C. in which the SiC substrate is hardly oxidized. However, because of reaction between the cap material and the substrate, a carbon compound to be formed cannot be completely removed. The carbon compound becomes a factor of degrading reliability of a gate insulation film. Therefore, the following method is generally used to remove the reacted carbon compound. Herein, thermal oxidation is carried out at high temperature with respect to an interface on which the gate insulation film is formed. Then, a silicon oxide film (sacrificial oxidation film) is formed, followed by removing the silicon oxide film with diluted hydrofluoric acid. This process is so-called sacrificial oxidation. Then, after undergoing a gate insulation film process, a silicide electrode process, and an interlayer insulation film forming process, the SiC-MOSFET is completely produced. 
         [0003]    Most of the SiC-MOSFET formed in such a way has low V th , and is of normally-on type. However, threshold voltage (V th ) of the existing Si-IGBT is about 5 to 5.5 V. In order to replace the threshold voltage with that of the SiC-MOSFET, threshold voltage (V th ) of 5 V or more is required. An example of a method to increase the V th  includes, for example, one that thickens dopant concentration of a base region on which a channel is formed. 
         [0004]    On the other hand, in order to achieve a low-loss device, it is important to improve mobility, and to decrease on-resistance. However, in the existing SiC-MOSFET, a plurality of interface states exists on the silicon oxide film/a so-called silicon carbide MOS interface. Therefore, channel mobility decreases. Accordingly, it is necessary to improve MOS interface property and to increase the channel mobility. An example of a method to increase the channel mobility includes, for example, one that applies a deposited oxide film to a gate oxide film, and to carry out oxynitride treatment (NPL 1). 
       CITATION LIST 
     Non Patent Literature 
       [0000]    
       
         NPL 1: M. Noborio, J. Suda, S. Beljakowa, M. Krieger, and T. Kimoto, phys. stat. sol. (a) 206, 2374 (2009) 
       
     
       SUMMARY OF INVENTION 
     Technical Problem 
       [0006]    However, in a case of increasing V th  or channel mobility in the above-mentioned way, there is a technical problem hereinafter described. 
         [0007]    In a method for thickening dopant concentration of a base region on which channel is formed, in order to increase the V th , the V th  increases but the channel mobility decreases due to influence by high impurity concentration. 
         [0008]    In a method for carrying out oxynitride treatment while applying a deposited oxide film to a gate oxide film in order to improve the channel mobility, the channel mobility improves but the V th  decreases. 
         [0009]    An object of the present invention is to provide a SiC-MOSFET having both high channel mobility and high V th . 
       Solution to Problem 
       [0010]    The present inventors have studied various sacrificial oxidation processes before forming a gate insulation film. As a result, the present inventors have found that V th  increases by carrying out plasma oxidation instead of thermal oxidation at high temperature. In other words, by using the plasma oxidation instead of the thermal oxidation in the related art for the sacrificial oxidation, V th  of 5 V or more can be obtained without deteriorating channel mobility of a SiC-MOSFET. 
         [0011]    Among the inventions disclosed herein, a representative invention will be briefly described hereinafter. 
         [0012]    That is, in a method for producing a semiconductor device according to the present invention, before forming a gate insulation film, (a) a silicon carbide substrate is oxidized by a low temperature oxidation method represented by the plasma oxidation to form a silicon oxide film. Next, (b) the silicon oxide film is removed. After repeating the processes (a) and (b) once or more, (c) the gate insulation film is formed. 
       Advantageous Effects of Invention 
       [0013]    According to the present invention, there is provided a SiC-MOSFET having both high channel mobility and high V th . 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0014]      FIG. 1  is a cross-sectional view of a silicon carbide semiconductor device in Example 1. 
           [0015]      FIG. 2(   a ) is a cross-sectional view showing a part of a producing process of the silicon carbide semiconductor device in Example 1. 
           [0016]      FIG. 2(   b ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 1. 
           [0017]      FIG. 2(   c ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 1. 
           [0018]      FIG. 2(   d ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 1. 
           [0019]      FIG. 2(   e ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 1. 
           [0020]      FIG. 2(   f ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 1. 
           [0021]      FIG. 2(   g ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 1. 
           [0022]      FIG. 2(   h ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 1. 
           [0023]      FIG. 2(   i ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 1. 
           [0024]      FIG. 2(   j ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 1. 
           [0025]      FIG. 2(   k ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 1. 
           [0026]      FIG. 3  is a view showing gate voltage dependency of drain current of the silicon carbide semiconductor device in Example 1, together with a comparative example. 
           [0027]      FIG. 4  is a view showing gate voltage dependency of channel mobility of the silicon carbide semiconductor device in Example 1, together with a comparative example. 
           [0028]      FIG. 5  is a table showing a relation between a peak value of the channel mobility and gate threshold voltage of the silicon carbide semiconductor device in Example 1, together with a comparative example. 
           [0029]      FIG. 6  is a cross-sectional view of a silicon carbide semiconductor device in Example 2. 
           [0030]      FIG. 7(   a ) is a cross-sectional view showing a part of a producing process of the silicon carbide semiconductor device in Example 2. 
           [0031]      FIG. 7(   b ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 2. 
           [0032]      FIG. 7(   c ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 2. 
           [0033]      FIG. 7(   d ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 2. 
           [0034]      FIG. 7(   e ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 2. 
           [0035]      FIG. 7(   f ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 2. 
           [0036]      FIG. 7(   g ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 2. 
           [0037]      FIG. 7(   h ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 2. 
           [0038]      FIG. 7(   i ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 2. 
           [0039]      FIG. 7(   j ) is a cross-sectional view showing a part of the producing process of the silicon carbide semiconductor device in Example 2. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0040]    Hereinafter, Examples of the present invention will be described in detail with reference to the accompanying drawings. 
         [0041]    Note that in all the drawings for explaining Examples, the same members will be denoted with the same reference numerals and duplicative explanation will be omitted. Especially, regarding members having similar functions between different Examples, those members will be denoted with the same reference numerals even though they are different in shape, impurity concentration, crystallinity, and the like. 
         [0042]    Hereinafter, the following process will be referred to as “sacrificial oxidation”. Herein, an interface on which a gate insulation film is formed is oxidized to form a silicon oxide film. Then, the silicon oxide film is removed with diluted hydrofluoric acid. The above-mentioned treatment is repeated once or more. 
         [0043]    In Examples 1 and 2, silicon carbide semiconductor devices having a so-called metal-oxide-semiconductor (MOS) configuration shown in  FIGS. 1 and 6  will be described. 
         [0044]    Applicable examples of the semiconductor device having the MOS configuration are shown in  FIGS. 1 and 6 .  FIG. 1  shows a configuration in which a source  23  and a drain  24  are disposed in a direction parallel to a substrate surface (hereinafter referred to as a horizontal MOS configuration). On the other hand,  FIG. 6  shows a configuration in which a source  23  and a drain  26  are disposed in a direction vertical to a substrate surface (hereinafter referred to as a vertical MOS configuration). 
       Example 1 
     Horizontal MOS Configuration 
       [0045]    In  FIG. 1 , a silicon carbide MOSFET, that is, a silicon carbide semiconductor device, includes a silicon carbide substrate  10 , a silicon carbide layer  20 , an insulation film  32 , a gate electrode  42 , a source electrode  51 , a drain electrode  52 , and abase contact electrode  53 . The silicon carbide layer is formed on the silicon carbide substrate  10 . The insulation film  32  is formed on the silicon carbide layer  20 . The gate electrode is formed on the insulation film  32 . The source electrode  51 , the drain electrode  52 , and the base contact electrode  53  are formed on the silicon carbide layer  20 . 
         [0046]    The silicon carbide layer  20  includes a silicon carbide epitaxial layer  21 , a base region  22 , a source region  23 , a drain region  24 , and a base contact region  25 . The base region  22  is an ion-implanted region or an epitaxial layer. The source region  23 , the drain region  24 , and the base contact region  25  are ion-implanted regions. 
         [0047]    Herein, as an impurity implanted into a region to be of n-type, for example, nitrogen (N) ion is used. On the other hand, as an impurity implanted into a region to be of p-type, for example, boron (B) or aluminum (Al) ion is used. In  FIG. 1(   a ), an n +  region which is to be the source region  23  and the drain region  24  of the transistor and a p +  region which is to be the base contact region  25  is formed inside the p-type base region  22 . 
         [0048]    The gate insulation film  32 , the source electrode  51 , the drain electrode  52 , and the base contact electrode  53  are formed on a surface of the silicon carbide layer  20 . 
         [0049]    The source electrode  51 , the drain electrode  52 , and the base contact electrode  53  are respectively connected with the source region  23 , the drain region  24 , and the base contact region  25 . 
         [0050]    The gate electrode  42  is formed so as to cover a part of the source region  23  and a part of the drain region  24  by involving the gate insulation film  32  on the silicon carbide layer  20 . 
         [0051]    [Method for Producing Horizontal MOS Configuration] 
         [0052]    Next, a method for producing the above-mentioned horizontal MOS configuration will be described. 
         [0053]      FIGS. 2(   a ) to  2 ( k ) are cross-sectional views showing each of processes in producing a horizontal MOS transistor in Example 1. Note that these cross-sectional views only show configurations of main parts in the processes for fear that the drawings become complicated, and that they are not accurate cross-sectional views. 
         [0054]    First, as shown in  FIG. 2(   a ), the silicon carbide epitaxial layer  21  was laminated on the n-type silicon carbide substrate  10 . 
         [0055]    Next, as shown in  FIG. 2(   b ), Al ion was implanted into a surface layer of the silicon carbide epitaxial layer  21  to form the p-type base region  22 . Note that ion implanted into the base contact region  25  may be B ion. Moreover, a p-type silicon carbide epitaxial layer may be further formed on the silicon carbide epitaxial layer  21  to form the p-type base region  22 . 
         [0056]    Next, the source region  23  and the drain region  24  were masked for ion implantation. Then, N ion was implanted into the source region  23  and the drain region  24 , as shown in  FIG. 2(   c ). Then, the mask was removed. 
         [0057]    Next, the base contact region  25  was masked for ion implantation. Then, Al ion was implanted into the base contact region  25 , as shown in  FIG. 2(   d ). Note that the ion implanted into the base contact region  25  may be B ion. Then, the mask was removed. 
         [0058]    Next, as shown in  FIG. 2(   e ), a carbon film  60  was deposited around the silicon carbide substrate  10  and the silicon carbide layer  20 , as a cap material for impurity activation annealing. After that, the impurity activation annealing was carried out, for example, at temperature from 1600 to 1800° C. In the present Example, the impurity activation annealing was carried out at 1700° C. for 60 seconds. 
         [0059]    Next, as shown in  FIG. 2(   f ), a carbon layer of the cap material was removed by oxygen plasma asking. In this occasion, a carbon compound formed by reaction between carbon of the cap material and the substrate could not be completely removed. Therefore, the sacrificial oxidation using plasma oxidation was carried out. More specifically, after carrying out a predetermined cleansing, the plasma oxidation was carried out with respect to the surface of the silicon carbide layer  20  to form an oxidation film  31 , as shown in  FIG. 2(   g ). Then, the oxidation film  31  was removed by the diluted hydrofluoric acid. The above-mentioned process, a so-called sacrificial oxidation process, was repeated once or more. In the sacrificial oxidation process, when a removal thickness of the silicon carbide layer  20  is thin, the carbon compound cannot be completely removed. On the other hand, when the removal thickness thereof is thick, it affects impurity concentration of the ion-implanted region. Therefore, the removal thickness is preferably 3 nm to 30 nm. In the sacrificial oxidation process using the thermal oxidation in the related art, the source region  23 , the drain region  24 , the base contact region  25 , which are ion-implanted regions, and the silicon carbide epitaxial layer  21  have different oxidation rate. Therefore, a step is generated in an interface between the silicon carbide layer  20  and a gate oxide film  32 . This step causes degrading of device property such as electric field concentration with respect to the gate insulation film. In a method using the plasma oxidation of the present invention, it is possible to form an even interface with no steps, and to obtain excellent device property. In the present Example, plasma oxidation by an inductive coupled plasma (ICP) method was used at temperature of 500° C. or less in order to form the oxidation film  31 . In the present Example, the above-mentioned process, so-called sacrificial oxidation, was repeatedly carried out. The thickness of the silicon carbide layer  20  removed by the sacrificial oxidation was formed to be, for example, 10 nm. 
         [0060]    Next, as shown in  FIG. 2(   h ), the gate oxide film  32  was formed on the semiconductor substrate. In the present Example, a deposited oxide film having the thickness of 50 nm was formed, and oxynitride treatment was carried out at 1300° C. for 30 minutes. 
         [0061]    Next, as shown in  FIG. 2(   i ), a gate material film  41  including an n-type polycrystalline silicon film having the thickness of 200 nm was deposited. 
         [0062]    Next, as shown in  FIG. 2(   j ), the gate material film  41  was etched with using a resist as a mask to form the gate electrode  42  of the MOS transistor. 
         [0063]    Next, through-holes were formed on the gate material film located on the source region  23 , the drain region  24 , and the base contact region  25 , as shown in  FIG. 2(   k ). Then, contacts of the source electrode  51 , the drain electrode  52 , and the base contact electrode  53  were respectively formed on the source region  23 , the drain region  24 , and the base contact region  25 . In addition to this process (including a silicidation process), a process of forming wires were carries out to complete the semiconductor device in  FIG. 1 . 
         [0064]    [Device Evaluation of SiC-MOSFET] 
         [0065]      FIGS. 3 to 5  show device evaluation results of the SiC-MOSFET of specification in which the plasma oxidation has been used for the sacrificial oxidation (hereinafter abbreviated as plasma oxidation specification) and specification in which the thermal oxidation in the related art has been used for the sacrificial oxidation (hereinafter abbreviated as thermal oxidation specification). 
         [0066]      FIG. 3  shows gate voltage dependency (I d V g  property) of drain current of the silicon carbide semiconductor device in Example 1. “Thermal Oxidation” shows a property line in a case of using a thermal oxidation film, while “Plasma Oxidation” shows a property line in a case of using a plasma oxidation film. As shown in  FIG. 3 , V th  of the plasma oxidation specification became higher than that of the thermal oxidation specification. More specifically, in the thermal oxidation specification, V th =4.3 V. On the other hand, in the plasma oxidation specification, V th =6.6 V, which is about 2.3 V higher than the thermal oxidation specification. 
         [0067]      FIG. 4  shows gate voltage dependency of channel mobility μ of the silicon carbide semiconductor device in Example 1. “Thermal Oxidation” shows a property line in a case of using a thermal oxidation film, while “Plasma Oxidation” shows a property line in a case of using a plasma oxidation film. A value subtracting threshold voltage V th  from gate voltage Vg is taken along the abscissa in  FIG. 4 . Regarding the maximum value of the channel mobility, μ=21.8 cm2/V·s in the thermal oxidation specification, while μ=21.1 cm2/V·s in the plasma oxidation specification, as shown in  FIG. 4 . There is no great distinction between those two specifications. 
         [0068]      FIG. 5  shows a table summarizing values of the V th  and the channel mobility μ. “Thermal Oxidation” shows a data in a case of using the thermal oxidation film, while “Plasma Oxidation” shows a data in a case of using the plasma oxidation film. As seen from  FIG. 5 , the V th  in the plasma oxidation specification increased about 2.3 V with barely changing the channel mobility, compared to the thermal oxidation specification. As mentioned above, in the process of producing a normal MOS transistor, it is clear that it is possible to increase the V th  without changing the channel mobility of the SiC-MOSFET (with retaining the mobility comparable with that of the thermal oxidation film) by replacing a sacrificial oxidation film using the thermal oxidation in the related art with the plasma oxidation film. 
         [0069]    In Example 1, the n-type silicon carbide monocrystalline semiconductor substrate was used. However, a p-type silicon carbide substrate may be used as well. In such a case, the MOS configuration can be formed by inverting polar character of the impurity ion implanted into each region for forming the MOS configuration. 
       Example 2 
       [0070]    Hereinafter, an application of a vertical MOS configuration shown in  FIG. 6  will be described. Note that the same members as shown in Example 1 will not be described herein. 
         [0071]    [Vertical MOS Configuration] 
         [0072]    In  FIG. 6 , a silicon carbide MOSFET, that is, a silicon carbide semiconductor device, includes a silicon carbide substrate  10 , a backside contact region  26 , a drain electrode  54 , a silicon carbide layer  20 , an insulation film  32 , a gate electrode  42 , and a source base contact common electrode  55 . The backside contact region  26  is an ion-implanted region formed inside the silicon carbide substrate  10 . The drain electrode  54  is formed on the backside contact region  26 . The silicon carbide layer  20  is formed on the silicon carbide substrate  10  together with the drain electrode  54 . The insulation film  32  is formed on the silicon carbide layer  20 . The gate electrode  42  is formed on the insulation film  32 . The source base contact common electrode  55  is formed on the silicon carbide layer  20 . The silicon carbide layer  20  includes a silicon carbide epitaxial layer  21 , a base region  22  and a source region  23 . The base region  22  and the source region  23  are ion-implanted regions. 
         [0073]    Herein, as an impurity implanted into a region to be of n-type, for example, nitrogen (N) ion is used. On the other hand, as an impurity implanted into a region to be of p-type, for example, boron (B) or aluminum (Al) ion is used. For example, in the drawing, the p+ type backside contact region  26  is formed inside the silicon carbide substrate  10 , and the n+ type source region  23  is formed as similar to Example 1. 
         [0074]    The gate insulation film  32  and the source base contact common electrode  55  are formed on a surface of the silicon carbide layer  20 . The drain electrode  54  is formed in the backside of the silicon carbide layer  20 . 
         [0075]    The source base contact common electrode  55  is connected with the base region  22  and the source region  23 . The drain electrode  54  is connected with the backside contact region  26 . 
         [0076]    The gate electrode  40  is formed so as to cover a part of the n-type source region  23  by involving the gate insulation film  32  on the silicon carbide layer  20 . 
         [0077]    [Method for Producing Vertical MOS Configuration] 
         [0078]    Next, a method for producing the above-mentioned vertical MOS configuration will be described. Note that a duplicative explanation for the same producing method as shown in Example 1 will not be described in detail.  FIGS. 7(   a ) to  7 ( j ) are cross-sectional views showing each of processes in producing a vertical MOS transistor in Example 2. Note that these cross-sectional views only show configurations of main parts in the processes for fear that the drawings become complicated, and that they are not accurate cross-sectional views. 
         [0079]    First, the silicon carbide epitaxial layer  21  was laminated, as shown in  FIG. 7(   a ). 
         [0080]    Next, as shown in  FIGS. 7(   b ),  7 ( c ), and  7 ( d ), ions were implanted into the p-type base region  22 , the n-type source region  23 , and the backside contact region  26 . Further, regarding ion type used for implantation, Al ion was used for the backside contact region  26 . On the other hand, similar types in Example 1 were used for implantation into the p-type base region  22  and the n-type source region  23 . Note that the ion implanted into the backside contact region  26  maybe B ion. 
         [0081]    Next, as shown in  FIG. 7(   e ), a carbon film  60  was deposited on surfaces of the silicon carbide substrate  10  and the silicon carbide layer  20 . After that, annealing for impurity activation was carried out at temperature, for example, from 1600 to 1800° C. 
         [0082]    Next, a carbon layer of a cap material was removed by oxygen plasma ashing. In this occasion, a carbon compound formed by reaction between carbon of the cap material and the substrate could not be completely removed. Therefore, as shown in  FIG. 7(   f ), sacrificial oxidation using plasma oxidation was carried out. More specifically, after carrying out a predetermined cleansing, the plasma oxidation was carried out with respect to the surface of the silicon carbide layer  20 , to form an oxidation film  31 . Then, the oxidation film  31  was removed by diluted hydrofluoric acid. Further, in a case of utilizing sacrificial oxidation using thermal oxidation, not only the surface but also the backside is oxidized at the same time. Therefore, in a case of carrying out ion implantation with respect to the backside contact region  26 , ion implantation had to be carried out while considering a thickness to be removed by the sacrificial oxidation. In a case of utilizing the sacrificial oxidation using the above-mentioned plasma oxidation, the backside is hardly oxidized. Accordingly, in a case of carrying out ion implantation with respect to the backside contact region  26 , there is no need to consider removal due to the sacrificial oxidation. It is enough to carry out ion implantation into a part closest to a backside surface with concentration in which the backside contact region  26  can come into contact with the electrode. Due to this effect, it becomes easy to be in good contact with the electrode. 
         [0083]    Next, as shown in  FIG. 7(   g ), agate oxide film  32  was formed on the semiconductor substrate. In the present Example, a deposited oxide film having the thickness of 50 nm was formed, and oxynitride treatment was carried out at 1300° C. for 30 minutes. 
         [0084]    Next, as shown in  FIGS. 7(   h ) and  7 ( i ), the gate material film  41  was deposited, and the gate material film  41  was etched to form the gate electrode  42  of the MOS transistor. 
         [0085]    Next, as shown in  FIG. 7(   j ), a through-hole was formed on a boundary of the base region  22  and the source region  23 . Then, contacts of the source base contact common electrode  55  and the drain electrode  54  were formed respectively on the boundary of the base region  22  and the source region  23 , and on the backside contact region  26 . In addition to this process (including silicidation process), a process of forming wires was carries out to completely form the semiconductor device in  FIG. 6 . 
         [0086]    Similarly to Example 1, even in the configuration and the producing method in the present Example 2, it is possible to increase V th , without changing mobility by changing only the method of forming the lower part of the gate insulation film in the MOS transistor having the vertical MOS configuration. 
       REFERENCE SIGNS LIST 
       [0087]      10  . . . silicon carbide substrate,  20  . . . silicon carbide layer,  21  . . . silicon carbide epitaxial layer,  22  . . . base region,  23  . . . source region,  24  . . . drain region,  25  . . . base contact region,  26  . . . backside contact region,  31  . . . sacrificial oxidation film,  32  . . . gate insulation film,  41  . . . gate material film,  42  . . . gate electrode,  51  . . . source electrode,  52  . . . drain electrode,  53  . . . base contact electrode, . . . drain electrode,  55  . . . source base contact common electrode,  60  . . . carbon film