Abstract:
An amplifier includes differential current sensing circuitry and an input bridge. Two paths of the input bridge receive the input signals and provide proportional current flows to the differential current sensing circuitry. The input bridge is configured to provide a differential offset voltage in one current path, and a complimentary voltage drop of equal magnitude in the other current path. In the examples, the input bridge includes a matched pair of transistors. To remove parallel incremental or small-signal conductance-related error sources, both transistors are operated at matched V DS  (drain-to-source) voltages. The voltage offset, provided in association with one of the input transistors, serves to extend the range of certain circuits using the amplifier. The complimentary voltage drop in association with the other input transistor maintains the match of the V DS  voltages for the two transistors.

Description:
TECHNICAL FIELD 
   The present subject matter relates to techniques and circuits, typically for the input stage of a differential amplifier, for extending its input voltage range without disrupting linearity or common mode rejection. 
   BACKGROUND 
   Amplifier circuits are used in a variety of electronic systems for increasing the voltage, current, or power of a signal. A “differential” amplifier is a well-known type of amplifier circuit, which provides an output signal that is proportional to the difference between two input signals. An ideal differential amplifier is designed to amplify the difference between the two input signals while rejecting any signal element that is common to the two input signals. 
   Many types of electronic circuits, particularly for portable or mobile applications, use low operating voltages to increase battery life, reduce product weight, and enable use of denser integrated circuits. This is particularly advantageous in portable electronic devices. Lower voltages, however, may impose limits on circuit operation. For example, reducing circuit supply voltages also reduces the range of circuit signal voltages at which an amplifier or the like may operate. 
   The circuit of  FIG. 8  is a differential input stage of an amplifier circuit. The purpose of the circuit is to sense a voltage difference V ID  across its inputs, and to accurately reproduce that voltage across a resistor R 1 . The resulting current flow in R 1  (which is V ID  divided by R 1  by Ohm&#39;s Law) can be conveyed, through the metal oxide semiconductor (MOS) transistors M 1  and M 2 , as an accurate signal in the form of a current, for further use in load  1  and/or load  2 . The circuit uses two high DC gain type operational amplifiers A 1 , A 2  and two transistors M 1 , M 2 , interconnected in negative feedback loops. Each operational amplifier is itself a differential amplifier for amplifying the difference between the signal input at the non-inverting input of the amplifier and the respective feedback signal at the inverting input. 
   A typical application may utilize the illustrated circuit as a transconductance amplifier serving as the input stage of voltage amplifier circuitry. The input stage elements provide proportional currents to additional circuitry, connected as the loads. In such an application, the additional circuitry represented by the loads provides gain and current conversion to an amplified voltage output node not shown. The amplifier input stage circuit shown in detail in  FIG. 8 , however, has limitations. 
   Referring now to  FIG. 8  in more detail, consider initially an idle or equilibrium state where the input voltage difference, V ID , is 0, because the two input voltages V INP , V INN  are identical. Each of the two operational amplifiers A 1 , A 2  forms a local negative feedback loop with a transistor, M 1  or M 2 , respectively. As long as the operational amplifiers have high DC gain, and all components are functioning normally, the negative feedback loops force the nodes V SP , V SN  to attain values equal to V INP , V INN , respectively. This is the “virtual-short-circuit” principle of operational amplifiers, that is to say, the feedback drives the inputs of an operational amplifier toward the same potential. 
   If V INP , V INN  differ in value by a nonzero value V ID , the local feedback loops will continue, separately, to adjust to maintain each operational amplifier&#39;s inputs at the same potential. Consequently voltage V 1  across R 1  will tend to equal V ID , if all components function as intended. The two constant current sources I 1  and I 2  (with identical values) deliver fixed currents, and the operational amplifiers have high input resistances (assumed infinite for ease of explanation). Therefore, any current that flows in R 1  must flow also through the transistors M 1 , M 2  and appear as a difference in the drain currents of those transistors. This current will flow to subsequent circuitry (drawn abstractly as “loads”) connected to the drains of the transistors M 1 , M 2 . 
   A limitation of the circuit of  FIG. 8  becomes apparent when the input voltages V INP , V INN  approach the level of the negative power-supply voltage V − . Upon this condition, the negative feedback loops around operational amplifiers A 1  and A 2  tend to force V SP , V SN  toward the negative supply voltage V − . However, each of the transistors M 1  and M 2  needs at least some minimum voltage from its source to its drain, to function normally. Also, an added voltage drop of the load circuitry appears at the drain terminals of the transistors M 1 , M 2 , further reducing the available voltage range for the source-to-drain voltages of the transistors. Transistors require some nonzero voltage between gate and source (V GS ), a further constraint on the useful negative range of V SP , V SN , even if the outputs of the operational amplifiers can swing to the negative supply voltage. These factors limit the practical input voltage range at V INP , V INN  to some value more positive than V − . This can be a relatively severe operational constraint in many applications, particularly those using relatively low magnitude power supply voltages. 
   A need exists for an effective technique to extend the operational range of the input voltage of a differential amplifier stage, e.g. for use as a transconductance input stage of an amplifier circuit. 
   The inventor has considered solutions to this constraint, that have proved insufficient. For example, the inventor has considered extending the input range of the circuit of  FIG. 8  to the negative supply voltage by shifting V INP  and V INN  together.  FIG. 3  shows a conceptual version of this approach, using identical level-shifting fixed voltage sources of value V SHIFT . These voltage sources have other possible placements, but  FIG. 3  is illustrative. The voltage sources V SHIFT  in  FIG. 3  are symbolic of the offset voltage function performed, and do not represent physical components. Examples of possible circuit components are discussed, later, with regard to  FIGS. 5 to 7 . 
   The feedback loops as before force the voltages on opposite ends of the resistor R 1  to values corresponding to voltages at the inputs of the operational amplifiers A 1 , A 2 . However, these voltages now include the offset voltage V SHIFT . The offset can be chosen to provide necessary operational ranges across the respective transistors, even when the input signals approach the level of the negative supply voltage. Problems arise, however, with the considered circuit of  FIG. 3 , due to finite transistor output resistances associated with MOS transistors. 
     FIG. 4(   a ) represents an MOS transistor as may be used as an input transistor within operational amplifier A 1  or A 2 , or for the transistors M 1 , M 2 . The drain current of any MOS transistor depends partly on its drain-to-source voltage V DS , even when the transistor is biased for high output impedance (with a “saturated” or “pinched-off” channel), as is usual in amplifier circuits. This dependence can be modeled equivalently as an ideal transistor plus a parallel incremental or small-signal conductance, labeled r o  in the illustration of  FIG. 4(   b ) (this is a standard analytical technique). 
   The exemplary circuit shown in  FIG. 5  implements the hypothetical technique outlined above relative to  FIG. 3 , using P-channel MOS transistors M 11 , M 12  as “source followers” to provide the voltage offsets. The transistors M 11 , M 12  have isolated “well” or back-gate connections tied to their sources, which eliminates a complication otherwise referred to as the “body effect.” In principle, M 11  and M 12  exhibit constant voltage V GS  between gate and source because of constant drain currents, regardless of the voltage swing at the gates. This accomplishes a common voltage shift of the positive (+) input V INP  and the negative (−) input V INN , as shown at V SHIFT  in  FIG. 3 . 
   However, a problem tends to arise within this hypothetical technique. As V ID  swings, M 11  and M 12  experience varying drain-to-source voltage V DS . This V DS  variation, through r o , changes the V GS  voltage that is required to pass the current from each constant-current source. This effect appears as a DC gain error from V ID  to V 1 , and it introduces nonlinearity in the signal path because the r o  effect is not a true linear resistance. These can be dominant error sources for voltage amplification implementing the circuit described. 
   Transistors M 1  and M 2  also exhibit a finite r o , but there the finite r o  affects the signal path much less than with M 11  and M 12 . Finite r o  in the M 1 , M 2  transistors changes the value of gate-to-source voltage V GS  needed to induce the drain current in each transistor, but the gate-to-source voltage V GS  of each transistor M 1  or M 2  is driven by a high-gain operational amplifier A 1  or A 2 . The operational amplifier “absorbs” any V GS  error at M 1  or M 2  by shifting its output voltage. The equivalent change at inputs V INP  and V INN  consists of this output shift divided by the large voltage gain of the operational amplifiers. In contrast, the transistors M 11 , M 12  in the circuit of  FIG. 5  have gate-to-source voltage drops V GS , which are added directly to the input voltages. Errors from finite r o  in MOS transistors M 11 , M 12  add to the input signal voltage V ID , and these gate-to-source voltage drops are not reduced by any amplifier gain. 
   Another hypothetical approach to building a circuit to implement the voltage offset strategy of  FIG. 3  considered by the inventor, is to build the level-shift voltages into the operational amplifiers themselves. This approach exhibits problems similar to those found in the circuit of  FIG. 5 . 
   Consider now two practical approaches to build operational amplifiers with such hypothetical level shifting (that is, with large deliberate input offset voltage) built into input circuitry of the op-amps. The first approach introduces a voltage drop in series with the V GS  path of one of the input transistors, within the operational amplifier itself. The other approach induces a mismatch between the input transistors, within the operational amplifier.  FIG. 6  illustrates a voltage drop V BIAS  in series with the V GS  path of one of the input transistors of the operational amplifier, and  FIG. 7  depicts a mismatch of input transistors within the operational amplifier. Both these techniques, however, tried to introduce errors that are dependent on the r o  impedance characteristic of one or more of the transistors within the operational amplifier. 
   Considering now  FIG. 6  in more detail, depicted is an example of an operational amplifier circuit, such as might be used as the amplifier A 1 . A current-carrying diode D 1  interposes a voltage difference or drop between the source terminals of two input transistors M 13 , M 14  of the operational amplifier. Note also components R 19 , R 20 , Q 15 , Q 16  which are typical in such an operational amplifier; these components of the amplifier sense the current difference between the currents flowing from M 13  and M 14 , while maintaining the drain terminals of M 13  and M 14  at similar potentials. 
   The circuitry of  FIG. 6  can be used to produce an operational amplifier that will exhibit a voltage difference between its two inputs when a negative feedback loop is closed around it with high gain (a feedback path is omitted from this drawing). This voltage difference ideally equals the voltage drop across diode D 1  when conducting. The operational amplifier in  FIG. 6  corresponds to one of the operational amplifiers, together with its input shift-voltage source, shown in  FIG. 3 . 
   However, the amplifier of  FIG. 6  operates input transistor devices M 13 , M 14  at different V DS  voltages, because the drains are at the same potential but the sources are not. As the two input voltages of the operational amplifier move in common, even with a fixed difference between them (for example, under excursions of V ID  in  FIG. 3 ), the V DS  voltages of M 13  and M 14  will vary. These variations alter the V GS  voltage of each transistor, as in the circuit of  FIG. 5 , and the effect is not linear. Similar to the circuit of  FIG. 5 , this causes error in the path from V ID  to V 1 , which is undesirable. 
     FIG. 7  shows a fragment of another operational amplifier, in which the input transistors M 21 , M 22  are deliberately mismatched to create an input offset without adding a diode or other explicit voltage drop. The mismatch may, for example, use a difference in MOS width/length dimensions, or different threshold-implant doping, or different transistor types, such as mixing bipolar and MOS transistors. All of these hypothetical methods, however, lead to different r o  characteristics in M 21  and M 22 . The magnitude, or the V DS  dependence of both MOS transistors M 2 , and M 22 , of the r o  effects in the two transistors, will differ. This leads again to errors as the two input terminals move in unison and therefore M 21 , M 22  experience varying V DS  voltages. 
   As shown by the preceding discussion, simple voltage shift techniques for providing a shift on one input of each operational amplifier, considered by the inventor, may help somewhat to extend the range of the transconductance stage. However, such techniques introduce undesirable non-linear performance, and may also disadvantageously reduce common mode rejection. Hence, a need still exists for a technique to extend the operational range of the input voltage of a differential amplifier or stage, while avoiding problems such as noted above. 
   SUMMARY 
   The teachings herein address the above noted problems with differential amplification by implementing an input bridge, coupled to the differential current sensory circuitry of the amplifier, and producing currents proportional to respective input signals to the sensory circuitry. In examples discussed in detail later, an input bridge of a differential amplifier includes a matched pair of transistors; and to remove the r o -related error sources, both transistors are operated at matched V DS (drain-to-source) voltages. A voltage offset is provided in association with one of the input transistors. A voltage drop of substantially the same magnitude as the offset voltage is provided in association with the other input transistor so as to maintain the match of the V DS  voltages for the two transistors. 
   Hence, an amplifier for providing an output proportional to the difference between two input signals might include differential current sensing circuitry and an input bridge. Two paths of the input bridge receive the input signals and provide proportional current flows to the differential current sensing circuitry. The input bridge is configured to provide a differential offset voltage in one of the current paths and a complimentary voltage drop of equal magnitude in the other current path. 
   In the examples, the first current path of the input bridge comprises a first input transistor for receiving the first input signal, and a first circuit element coupled to the first input transistor so as to provide the differential offset voltage of the desired offset magnitude. The second current path comprises a second input transistor, matching the first input transistor, for receiving the second input signal. The second path further includes a second circuit element coupled to the second input transistor so as to provide a voltage drop of substantially the same magnitude as the differential offset. 
   In the two current paths, the matched transistors and the circuit elements are stacked in a complimentary fashion. In one path, the circuit element connects to a current supply, and the transistor connects to the current sensing circuitry. In the other path, the transistor connects to the current supply and the circuit element connects to the current sensing circuitry. 
   A variety of different matching circuit elements may be used to provide the offset voltage and the complimentary voltage drop, in the paths of the input bridge. Disclosed examples include matching diodes, matching diode connected transistors and matching resistors. However, in such examples, the transistors match; and the magnitude of the voltages across the circuit elements in the two paths are ‘equal’ (substantially the same). Although other transistors may be used, the examples of the bridge utilize metal oxide semiconductor (MOS) transistors. Each MOS transistor may have an isolated well or back-gate connection tied to its source. 
   The difference or differential amplifier may be utilized as one element of a circuit. The differential amplifier in such a circuit receives an input signal and a feedback signal on its inputs. A transistor coupled to the output of the differential amplifier produces a flow of current proportional to the output of the differential amplifier. The feedback signal is related to the flow of current produced by the transistor. Of course, this circuit itself may be utilized as a component of a larger circuit. For example, the input stage of a voltage-to-voltage amplifier might utilize a pair of such amplifier circuits. 
   Teachings discussed herein also encompass an improvement in a difference or differential amplifier. This improvement comprises first and second matched input transistors for receiving two input signals. The improvement also includes first and second matched circuit elements for providing equal magnitude voltage drops. The first element is coupled to the first input transistor, so as to provide current from a supply to the first input transistor. In this way, the first element provides a differential offset voltage of the desired magnitude. The first input transistor supplies a current proportional to the first input signal to further circuitry of the amplifier. The second input transistor is coupled to the supply, and the second circuit element is coupled to an output of the second input transistor so as to provide current proportional to the second input signal to the further circuitry of the amplifier. This second element also provides a voltage drop matching the differential offset voltage. 
   Teachings discussed herein also encompass a method of processing signals. The method involves producing a first current flow in a first path proportional to the first input signal and producing a second current flow in a second path proportional to the second input signal. A differential voltage offset is provided in the first path, and a complimentary voltage drop is provided in the second path. The magnitude of the complimentary voltage drop is equal to (substantially the same as) the magnitude of the differential voltage offset in the first path. A difference is sensed between the first and second proportional currents, e.g. to provide difference amplification. 
   Additional objects, advantages and novel features will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and the accompanying drawings or may be learned by production or operation of the examples. The objects and advantages of the present teachings may be realized and attained by practice or use of the methodologies, instrumentalities and combinations particularly pointed out in the appended claims. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The drawing figures depict one or more implementations in accord with the present teachings, by way of example only, not by way of limitation. In the figures, like reference numerals refer to the same or similar elements. 
       FIG. 1  illustrates a bridge circuit for an operational amplifier, providing a voltage offset and an equal magnitude complimentary voltage drop, in current paths of an input bridge that are responsive to the input signals to the operational amplifier. 
       FIG. 2  illustrates a differential input stage of an amplifier circuit, wherein the negative feedback amplifier circuits of the stage utilize the bridge circuit of  FIG. 1 . 
       FIG. 3  is a diagram of a differential input stage of an amplifier circuit, with hypothetical external voltage offsets on the inputs to increase operational voltage range. 
       FIG. 4(   a ) illustrates an MOS transistor; and  FIG. 4(   b ) illustrates a model of the transistor as a combination of an ideal transistor and a parallel output impedance. 
       FIG. 5  illustrates a hypothetical differential input stage of an amplifier circuit, which uses a transistors configured as source followers to provide voltage offset for each input signal. 
       FIG. 6  illustrates a hypothetical operational amplifier having a voltage drop associated with one of the input transistors, so as to provide voltage offset. 
       FIG. 7  illustrates an input circuit of a hypothetical operational amplifier, wherein input transistors of the circuit are mismatched, so as to provide one of the voltage offsets. 
       FIG. 8  is a diagram of a prior art differential input stage of an amplifier circuit. 
   

   DETAILED DESCRIPTION 
   In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant teachings. However, it should be apparent to those skilled in the art that the present teachings may be practiced without such details. In other instances, well known methods, procedures, components, and circuitry have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings. 
   In the following example, removal of the r o -related error sources requires operation of a matched pair of input transistors at matched V DS (drain-to-source) voltages, in which input transistors are configured in circuit to form part of a bridge. Other elements of the bridge provide a desired voltage offset in one path and a complimentary voltage drop of substantially the same magnitude in the other path. 
     FIG. 1  illustrates an example of the input circuitry of an operational amplifier which avoids problems of non-linearity or the like explained with reference to  FIG. 6 , caused by differences of the r o  effects in the two input transistors. MOS transistors M 3 , M 4  are input transistors of an operational amplifier, the drain-source path of each being stacked with a diode. These diodes are matched, so that when conducting, the voltage across them is substantially the same. The two paths are connected at the top, but the order of transistor and diode in each path is mutually reversed. As discussed more below, one of the diodes provides an offset voltage drop in relation to the input signal, whereas the other diode provides a complimentary voltage drop. The bottoms of the stacks (nodes x, y) connect to further circuitry of the amplifier that senses the current difference between the two stacks. 
   Considering the example of  FIG. 1  now in more detail, a current source connected to the positive voltage rail supplies constant current to the top of the bridge. On one side of the bridge, a first diode D 3  is connected between the constant current source and the source of the first transistor M 3  of the matched MOS input transistors M 3 , M 4 . When conducting, diode D 3  produces a constant voltage drop, and thus a voltage offset (from that at the current source) in the first path of the bridge through transistor M 3 . The drain of the first MOS input transistor M 3  is connected to node x, and from there through a resistor R 19  to the negative voltage supply rail. The gate of the MOS input transistor M 3  serves as the positive (+) input of the operational amplifier. 
   On the other side of, or path through, the input bridge, the source of matched MOS input transistor M 4  receives current flowing from the constant current supply. The voltage at this point (source of M 3 ) is the voltage as it appears at the output of the constant current source, that is without voltage offset. The drain of the MOS input transistor M 4 , however, is connected to a second diode D 4 , that when conducting, produces a constant voltage drop of substantially the same magnitude as that across the diode D 3 . The diode D 4  is connected to node y, and through a resistor R 20  to the negative voltage supply rail. The gate of the second MOS input transistor M 4  serves as the negative (−) input of the operational amplifier. 
   Those skilled in the art will understand that the transistor and diode types, the connections, and the resulting polarities are exemplary only. 
   The nodes x and y provide connections of the input bridge circuit to other elements of the respective operational difference amplifier. In  FIG. 6 , the further circuitry is shown as comprising R 19 , R 20 , Q 15 , Q 16  for current sensing and current to voltage conversion, although other operational amplifiers may utilize different elements for that circuitry. 
   Under high-gain negative feedback of the operational amplifier, this arrangement will tend to force the two stacks to carry identical currents, and also will maintain nodes x and y at substantially the same potential (another case of “virtual short circuit”). Because each stack or path has the same potential at top and bottom, the sums of voltages within each stack must be equal. As long as the diode voltage drops are equal, the drain-to-source voltages V DS  of the two transistors M 3 , M 4  will therefore be equal. 
   In this way, the “bridge” or “diamond” configuration of diodes and input transistors of  FIG. 1  maintains the same drain-to-source voltage V DS  on both MOS input transistors M 3  and M 4 . However, the complimentary placement of the diodes D 3  and D 4  imposes an offset voltage between the two op-amp inputs when they are in a negative feedback loop. This offset voltage is set by the voltage drop of diode D 3  (interposed between the two input-transistor V GS  paths). Stated another way, the voltage at the source of the transistor M 3  is offset lower than the voltage at the source of the transistor M 4  by the magnitude of the voltage appearing across conducting diode D 3 . This voltage offset serves as an input voltage shift, analogous to that discussed above relative to  FIGS. 3 and 6 . Because of the position of the diode D 4 , however, the voltage across that second diode does not affect differential processing by the input transistors M 3 , M 4 . Instead, that voltage drop compliments the voltage offset by diode D 3  so as to maintain matching of the drain-to-source voltages V DS  across the two transistors M 3 , M 4 . 
   Various numbers and types of diodes may be used, to provide the desired magnitude for the voltage offset and the complimentary voltage drop. Also, the diodes may be replaced by any other suitable sources of predictable voltage drops. Examples of other suitable elements include diode connected transistors and resistors with a fixed value and predictable current flow. 
     FIG. 2  illustrates an amplifier circuit, utilizing two operational amplifiers A 11  and A 12  with bridge type input circuits to provide voltage offsets, as discussed above relative to  FIG. 1 . The circuit of  FIG. 2 , however, may be used for an application similar to that of the prior art circuit of  FIG. 8 . 
   The operational amplifier A 11  includes an input bridge that includes matched MOS input transistors M 3  and M 4  and voltage offset diodes D 3  and D 4 . The drain-source path of each input transistor is stacked with a diode. The diodes are matched, so that when conducting, the voltage across each diode is substantially the same. The two current paths are connected at the top, but the order of the transistor and the diode in each stack is mutually reversed. As in the example of  FIG. 1 , one of the diodes provides an offset voltage drop in relation to the input signal, whereas the other provides a complimentary voltage drop. The bottoms of the stacks connect to further circuitry of the operational amplifier (current sensing circuitry) for sensing the current difference between the two paths. The output of the current sensing circuitry drives the gate of the MOS transistor M 1 . 
   It considering amplifier A 11  in more detail, a current source connected to the positive voltage rail supplies constant current to the top of the bridge in operational amplifier A 11 . The first diode D 3  connects to the source of the first transistor M 3  of the matched MOS input transistors M 3 , M 4 . When diode D 3  is conducting, a constant voltage appears across that diode, which serves as the differential voltage shift or offset for the amplifier A 11 . The drain of the MOS input transistor M 3  connects to one input of the current sensing circuitry. The gate of the MOS input transistor M 3  serves as the positive (+) input of the illustrated circuit. 
   On the other side of the input bridge, the source of the other matched MOS input transistor M 4  receives current from the constant current supply, that is to say without voltage offset. The drain of the MOS input transistor M 4  connects to a second diode D 4 . When conducting, the second diode D 4  provides a constant voltage drop, of substantially the same magnitude as the voltage across the diode D 3 . The diode D 4  connects to the other input of the current sensing circuitry. The gate of the second MOS input transistor M 4  serves as the negative (−) input of the operational amplifier A 11 . However, in this application, the negative input is used for feedback and is connected to the V SP  node (connection of R 1  to source of transistor M 1 ). 
   The operational amplifier A 12  includes a similar input bridge. The transistors and diodes of the second bridge are generally similar to those of the first bridge. This bridge includes matched MOS input transistors M 5  and M 6  and diodes D 5  and D 6 . The drain-source path of each input transistor is stacked with a diode. The diodes are matched, so that when conducting, the voltage across each diode is substantially the same. The two stacks are connected at the top, but the order of the transistor and the diode in each stack is mutually reversed. As in the bridge of amplifier A 11 , one of the diodes provides an offset voltage drop in relation to the respective input signal, whereas the other provides a complimentary voltage drop. The bottoms of the stacks connect to further circuitry of the operational amplifier for sensing the current difference between the two stacks. In the case of the second operational amplifier A 12 , the output of the current sensing circuitry drives the gate of the MOS transistor M 2 . 
   Considering now amplifier A 12  in more detail, a current source connected to the positive voltage rail supplies constant current to the top of the bridge in operational amplifier A 12 . The first diode D 5  is connected to the source of the first of the matched MOS input transistors M 5 . When conducting, a constant voltage appears across the first diode D 5 , which provides the differential voltage shift or offset for the input to amplifier A 12 . Since diode D 5  is similar to diode D 3 , this input voltage shift in differential amplifier A 12  will be equal to (i.e., substantially the same as) the input voltage shift in differential amplifier A 11 . The drain of the MOS input transistor M 5  is connected to one input of the current sensing circuitry. The gate of the MOS input transistor M 5  serves as the negative (−) input of the complete circuit, although it is the positive input of the operational amplifier A 12 . 
   On the other side of the input bridge of the second operational amplifier A 12 , the source of the other matched MOS input transistor M 6  receives current from the constant current supply, that is to say without voltage offset. The drain of the MOS input transistor M 6  is connected to a second diode D 6 . When conducting, the second diode D 6  produces a constant voltage drop of substantially the same magnitude as the voltage across the diode D 5 . Diode D 6  is connected to the other input of the current sensing circuitry. The gate of the second MOS input transistor M 6  serves as the negative (−) input of the operational amplifier A 12 . However, in this application, that negative input is used for feedback and is connected to the V SN  node (connection of R 1  to source of transistor M 2 ). 
   The purpose of the circuit of  FIG. 2  is to sense a voltage difference V ID  across its inputs (V INP  and V INN ), and to accurately reproduce that voltage across a resistor R 1 . Then, the resulting current flow in R 1  (which is V ID ÷R 1  by Ohm&#39;s Law) can be conveyed, through the metal oxide semiconductor (MOS) transistors M 1  and M 2 , as an accurate signal in the form of a current, for further use in load  1  and or load  2 . A typical application, for example, may utilize the illustrated circuit as a transconductance amplifier serving as the input stage of voltage amplifier circuitry. The input stage elements shown in the drawing provide proportional currents to additional circuitry, connected as the loads. In such an application, the further circuitry represented by the loads may provide gain and conversion of the current flows to an amplified voltage output. 
   The circuit of  FIG. 2  operates as follows. First consider an idle or equilibrium state where the input voltage difference V ID =0. The two input voltages V INP  and V INN  are accordingly identical. Each of the two operational amplifiers A 11 , A 12  forms a local negative feedback loop around a transistor M 1  or M 2 , respectively. As long as the operational amplifiers have high DC gain, and all components are functioning normally, the negative feedback loops force the nodes V SP , V SN  to values essentially equal to the input voltages of the amplifiers A 11  and A 12 , that is to say V INP  Plus the offset or shift voltage and V INN  plus the offset or shift voltage, respectively. Where the input voltage difference V ID =0, the voltage shifts cancel out, and the voltage V 1  (across R 1 ) remains 0. 
   However, the input shifts provided by the offset voltages (across D 3  and D 5 ) extend the input range of the circuit of  FIG. 2  nearer the negative supply voltage. The voltage V 1  across R 1  still tracks the differences between the input signals V INP  and V INN , because the feedback loops force the voltages on opposite ends of the resistor R 1  to values corresponding to voltages at the op-amp inputs, and the resulting currents follow the signal differences. When the input voltages V INP  and V INN  differ in value by a nonzero value V ID , the local feedback loops will continue, separately, to adjust to maintain each operational amplifier&#39;s inputs at the same potential. Consequently voltage V 1  across R 1  will tend to equal V ID , if all components function as intended, although V SP  and V SN  will both be shifted by an amount corresponding to the offset voltage V SHIFT  provided by diodes D 3 , D 5 . The two constant current sources I 1  and I 2  (with identical values) deliver fixed currents, and the operational amplifiers have high input resistances (assume infinite, for ease of explanation). Therefore any current that flows in R 1  must flow also through the transistors M 1 , M 2  and appear as a difference in the drain currents of those transistors. This current will flow to subsequent circuitry (drawn abstractly as “loads”) connected to the drains of the transistors M 1 , M 2 . 
   As noted, the individual voltages V SP  and V SN  now include the offset. The offset can be chosen to provide necessary operational ranges across the respective transistors M 1  and M 2 , even when the input signals approach the negative supply voltage. When the input voltages V INP  and V INN  approach the negative power-supply voltage V − , the negative feedback loops around A 1  and A 2  tend to force V SP , V SN  toward a value offset from the negative supply voltage by the offset voltage (that is to say the voltage across diodes D 3  and D 5 ). Assuming the offset is high enough, the voltages across the transistors M 1  and M 2  will be sufficient to maintain normal operation. 
   While the foregoing has described what are considered to be the best mode and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.