Abstract:
A transimpedance amplifier (TIA) circuit comprises an input and an amplifying stage that includes N amplifiers, that generates a first signal and that is AC coupled to the input. A bias stage generates a second signal and that is DC coupled to the input. An output stage is driven by the first signal from the amplifying stage and the second signal from the bias stage.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is related to U.S. patent application Ser. Nos. 10/072,843, filed on Feb. 6, 2002, Ser. No. 10/459,731, filed Jul. 11, 2003, Ser. No. 10/838,040, filed May 3, 2004 and 10/814,534, filed Mar. 31, 2004. The disclosures of the above applications are incorporated herein by reference in their entirety. 
     FIELD OF THE INVENTION 
     The present invention relates to amplifiers and more particularly to transimpedance amplifiers. 
     BACKGROUND OF THE INVENTION 
     Referring now to  FIG. 1 , a transimpedance amplifier (TIA)  2  has an input node  4  that is AC coupled through a capacitor  6  to amplifiers  7 - 1 ,  7 - 2 , and  7 - 3 , (collectively referred to as amplifiers  7 ). Each of the amplifiers  7  has a transconductance (g m ) and a respective feedback resistance  8 - 1 ,  8 - 2 , and  8 - 3  (collectively feedback resistances  8 ). An output of the last amplifier  7 - 3  is coupled to a gate of a transistor  10 . An output node  12  produces VOUT and is taken at a source of the transistor  10 . A drain of the transistor  10  is connected to a power supply voltage V DD . An AC feedback path is provided to the input node  4  through a feedback capacitor  14  and a feedback resistance  16 . A typical capacitance for the feedback capacitor  14  is 35 picofarads (pF). A current source  18  provides a constant current bias I BIAS  and is connected between a source of the transistor  10  and a power supply reference voltage V SS . 
     Referring now to  FIG. 1A , a gain of the TIA  2  of  FIG. 1  is shown as a function of frequency. It can be seen that the TIA  2  has an undesirably high gain at low frequencies that are identified at  20 . The high gain is caused by an impedance of the capacitor  14  at the low frequencies. At higher frequencies that are identified at  22 , the capacitor  14  has a lower impedance and the TIA  2  has a flat gain response. 
     SUMMARY OF THE INVENTION 
     A transimpedance amplifier (TIA) circuit comprises an input and an amplifying stage that includes N amplifiers, that generates a first signal and that is AC coupled to the input. A bias stage generates a second signal and is DC coupled to the input. An output stage is driven by the first signal from the amplifying stage and the second signal from the bias stage. 
     In other features, the N amplifiers are connected in series and each includes an input, an output, and a feedback resistance. The bias stage comprises an op amp having a non-inverting input that communicates with the input. 
     In yet other features, the bias stage further comprises a first current source and a first transistor having first and second terminals and a control terminal. The first current source communicates with the second terminal of the first transistor and an inverting input of the op-amp. A low pass filter communicates with an output of the bias stage. 
     In yet other features, a current limiting device communicates with the bias stage and the output stage. The output stage further comprises a second current source and a second transistor having first and second terminals and a control terminal. The second current source communicates with the second terminal of the second transistor. 
     In other features, the first current source provides a magnitude of current flow that is a fraction of the magnitude of current flowing through the second current source. The output stage is DC-coupled to the input. 
     Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
         FIG. 1  is an electrical schematic of a TIA according to the prior art; 
         FIG. 1A  is a graph depicting the frequency response of the TIA shown in  FIG. 1 ; 
         FIG. 2  is an electrical schematic of a TIA according to some implementation of the present invention; 
         FIG. 3  is an electrical schematic of a TIA according to another implementation of the present invention; and 
         FIG. 3A  is a graph depicting the frequency response of the differential mode TIA shown in  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. 
     Referring now to  FIG. 2 , one implementation of a TIA  30  is shown. An amplifying stage  32  has an AC coupled input from an input node  34 . A bias stage  36  has a DC coupled input from the input node  34  and generates a very low frequency bias. An output stage  38  receives an amplified signal from the amplifying stage  32  and the bias from the bias stage  36 . 
     The amplifying stage  34  has an input capacitor  40  coupled to an input of a series of amplifiers  42 - 1 ,  42 - 2 , . . . , and  42 -N (collectively amplifiers  42 ), each having a transconductance (g m ) and a respective feedback resistance  44 - 1 ,  44 - 2 , . . . , and  44 -N. While three amplifiers  42  are shown, additional or fewer amplifiers may be used depending on a desired power and/or stability. An output of the amplifiers  42  is connected to a series capacitor  46 . In some implementations, the capacitance of series capacitor  46  is less than 20 picofarads and preferably approximately 6 picofarads or less. An output of the amplifying stage  32  is connected at the other end of the series capacitor  46 . 
     The bias stage  36  includes an op-amp  48 . A non-inverting input of the op-amp  48  is DC coupled to the input node  34 . A current source  50  provides current having a magnitude I BIAS  and is connected between a source of a transistor  52  and a power supply reference voltage V SS . In some implementations, the magnitude of current flow through the current source  50  is a fraction of I BIAS  to conserve current and reduce power consumption of the TIA  30 . An inverting input of the op-amp  48  is connected to the source of the transistor  52 . An output of the op-amp  48  is connected to a gate of the transistor  52 . A drain of the transistor  52  is connected to a power supply voltage V DD . An output of the bias stage  36  is at the output of the op-amp  48 . 
     The output stage  38  has a transistor  54  having a gate connected to the output of the amplifying stage  32  and to the output of the bias stage  36 . A drain of the transistor  54  is connected to the power supply voltage V DD . A current source  56  provides current having a magnitude I BIAS  and is connected between a source of the transistor  54  and the power supply reference voltage V SS . The source of the transistor  54  is also DC coupled to the input node  34  through a feedback resistor  58 . An output node  60  for the TIA  30  is at the source of transistor  54 . 
     In operation, the amplifying stage  32  of the TIA  30  amplifies high frequency components of a signal appearing at the input node  34 . A low corner frequency of the amplifying stage  32  is determined by the capacitances of the input capacitor  40  and the series capacitor  46 . The high-frequency components are amplified by the amplifiers  42  and appear at the output of the amplifying stage  32 . 
     The bias stage  36  receives Vin and generates a DC-bias signal for the transistor  54  in the output stage. In the output stage  38 , the gate of the transistor  54  receives a gate signal from the combined output signals of the amplifying stage  32  and the bias stage  36 . In some implementations, the transistors  52  and  54  are performance matched. The transistors  52  and  54  may be performance matched by matching their dimensions or size on a semiconductor die. Through this matching, Vout at node  60  is close to the feedback voltage at node  62 , which in turn tracks Vin at node  34 . As a result, the current flowing through resistor  58  is minimized. 
     Referring now to  FIG. 3 , another implementation of a TIA  70  is shown. The TIA  70  is similar to the TIA  30  of  FIG. 2  with the exception of an additional resistor  72 , an additional capacitor  74 , and the magnitude of current flowing through a current source  76 . The resistor  72  is connected between the output of the op-amp  46  and the gate of the transistor  54 . The resistor  72  limits current flowing into the gate of the transistor  54  to prevent it from overshooting and driving current through resistor  58  back into the signal source (not shown) that is connected to the input node  34 . The resistor  72  also limits the negative effects of the bias stage  36  on the signal through the amplifying stage  32 . The capacitor  74  is connected between the output of the op-amp  46  and the power supply reference voltage V SS . In some implementations, the capacitance of capacitor  74  is greater than 1 pF such as approximately 3 pF, although other values may be used. The capacitances of capacitors  40 ,  46 , and  74  and resistance of resistor  72  are preferably selected such that an overall circuit gain from the input node  34  to the output node  60  is constant between the low frequency cutoff of the amplifying stage  32  and the high frequency cutoff at a later stage (not shown). For example, the current flowing through the current source  76  is one-fourth of the current I BIAS  to conserve current and reduce power consumption of the TIA  70   
     Referring now to  FIG. 3A , a frequency response of the TIA  70  is shown. There is a low frequency cutoff that is determined by the interaction between the capacitance  40  and the input impedance of stage  44 - 1  together with the interaction between the capacitance  46  and resistance  72 . The frequency response in a low frequency range  70  is flat due to the removal of the capacitance  14  in  FIG. 1  from the feedback path. 
     Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. For example, the TIA circuit can be operated in single ended and differential modes. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.