Abstract:
A power supply includes a source signal generating circuit, an output stage, and a feedback stage. The power supply further includes a replica stage configured to replicate a response of the output stage to the source signal, and an output regulator coupling the replica stage to the output stage, configured to adjust a feedback signal to the source signal generating circuit by shunting the feedback stage when a loaded output stage response does not match a response of the replica stage to the source signal.

Description:
BACKGROUND 
     Power regulator designs may compromise performance because high precision or high performance circuit blocks cannot be used, due to load current demands. This is particularly true for low and very low power regulators. 
     Regulators are often challenged to supply a load that has a wide current range, for example 1 nA to 100 uA.  FIG. 1  illustrates output voltage degradation for a conventional low power regulator as the load current is increased (linearly) from 0 nA to 1 mA. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the drawings, the same reference numbers and acronyms identify elements or acts with the same or similar functionality for ease of understanding and convenience. To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the figure number in which that element is first introduced. 
         FIG. 1  illustrates output voltage curves for some conventional low power regulators as the load current increases (linearly) from 0 nA to 1 mA. 
         FIG. 2  is a block diagram illustration of a power supply regulator employing an output current regulator. 
         FIG. 3  illustrates an embodiment of the power supply regulator of  FIG. 2  in more detail. 
         FIG. 4  illustrates the output voltages of an exemplary power supply regulator comprising a current regulator, for a range of load currents. 
         FIG. 5  illustrates the current regulator applied to multiple source follower circuits. 
         FIG. 6  illustrates an embodiment of a voltage protection circuit. 
     
    
    
     DETAILED DESCRIPTION 
     Preliminaries 
     References to “one embodiment” or “an embodiment” do not necessarily refer to the same embodiment, although they may. Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” Words using the singular or plural number also include the plural or singular number respectively, unless expressly limited to a single one or multiple ones. Additionally, the words “herein,” “above,” “below” and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. When the claims use the word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list, unless expressly limited to one or the other. 
     “Logic” refers to machine memory circuits, machine readable media, and/or circuitry which by way of its material and/or material-energy configuration comprises control and/or procedural signals, and/or settings and values (such as resistance, impedance, capacitance, inductance, current/voltage ratings, etc.), that may be applied to influence the operation of a device. Magnetic media, electronic circuits, electrical and optical memory (both volatile and nonvolatile), and firmware are examples of logic. 
     Those skilled in the art will appreciate that logic may be distributed throughout one or more devices, and/or may be comprised of combinations memory, media, processing circuits and controllers, other circuits, and so on. Therefore, in the interest of clarity and correctness logic may not always be distinctly illustrated in drawings of devices and systems, although it is inherently present therein. 
     The techniques and procedures described herein may be implemented via logic distributed in one or more computing devices. The particular distribution and choice of logic is a design decision that will vary according to implementation. 
     The term “grounded” refers to a connection to an electrical terminal that may be treated as “common” or “0V” for analytical purposes, but which may or may not in fact not be at earth ground (i.e., a “local ground” or “reference ground”). 
     The term “shunt” refers to a connection between two circuit points. A shunt may be made through one or more circuit components. In this description, a shunt is more particularly a configurable connection between two circuit points, which can be controllably opened (signaling connectivity removed) or closed (signaling connectivity activated) under different conditions. 
     The terms “current regulated”, “regulated current source”, “current sink”, or “constant current source” refer to logic to maintain a substantially constant amount of current to a load over a range of load impedances. In a non-regulated (non-constant) current source, the supplied current varies linearly with a change in the load resistance according to I=V/R, where V is the applied voltage. This is not the case for a regulated current source, in which I does not substantially over a range of different R for a particular V. The “load” is whatever logic is coupled across or between the terminals of the current regulated logic. 
     Overview 
     A plurality of FETs form an output regulator circuit for a power supply. The regulator comprises at least a pair of FETs sharing a common gate terminal. Typically, though not exclusively, the power supply utilizing the regulator is a low or ultra-low supply configured to supply a range of current to an attached load, without substantial (e.g., with less than 10% variation, and often less than 5% variation) drop in an output voltage to the load over the current range. At least two of FETs of the current regulator are coupled to one or more current sinks. A current sink is a circuit that maintains a constant amount of current flow through the circuit, despite increases or decreases in a voltage applied across the current sink circuit. One of the FETs drives a transistor (e.g., another FET), which modifies a feedback signal to a high impedance source that drives an output stage of the power supply. The high impedance source may comprise an OTA (operational transconductance amplifier) supplying a signal (the “source signal”) that drives a source follower circuit in the output stage of the power supply. 
     Detailed Description of Particular Embodiments 
       FIG. 2  is a block diagram illustration of a power supply employing an output current regulator. The power supply comprises a high impedance signal source  202 , which may be a voltage source or a current source. As known in the art, a voltage source is a circuit that produces a substantially constant output voltage irrespective of the load impedance, over a range of loads. The signal source  202  may alternatively be a current source, such as an OTA. As known in the art, a current source provides a substantially constant output current, irrespective of the load impedance, over a range of loads. 
     The output of the high impedance source  202  is provided to a replica stage  204 , and, in parallel, to an output stage  206 . The replica stage replicates the manufactured characteristics of the output stage  206 , and thus, when the output stage is not heavily loaded, mirrors the response of the output stage  206  to the signal (the “source signal”) from the high impedance source  202 . At the same time, the replica stage  204  isolates the feedback stage  208  from the output stage  206 . A scaled response of the replica stage to the source signal is provided through the feedback stage  208  to an input of the high impedance source  202 . 
     A current regulator  210  is coupled between the output stage  206  and the replica stage  204 . The current regulator  210  controls the signal supplied through the feedback stage  208 , to maintain the voltage at the output stage  206  relatively constant over a range of currents that may be demanded by the attached load. The current regulator  210  may be used with power supplies designed to operate at low currents, on the order of nanoamperes (nA). The regulator  210  provides load sensing and load voltage regulation while adding only a few nA to the overall power supply operating current under loaded conditions. The current regulator  210  is also generally applicable to higher current power supplies. 
       FIG. 3  illustrates an embodiment of the power supply of  FIG. 2  in more detail. The high impedance source may comprise an operational amplifier  302 . The op amp  302  inputs a reference signal and a feedback signal. If the operational amplifier  302  is an OTA, it may provide an output current (source signal) to node N G . The op amp  302  or similar circuit is thus referred to as a source signal generator for the power supply. The source signal is proportional to the difference between the reference signal and the feedback signal. The compensation capacitor  303  provides voltage regulator stability. The source signal is supplied to the gates of two or more FETs  304 ,  305  (e.g., nFETs/pFETs/MOSFETs). 
     The replica stage of the power supply comprises a transistor  304  which is fabricated with similar characteristics as the output stage transistor  305 . For example, transistor  304  may have a similar channel width/length ratio as transistor  305 . Both of transistors  304  and  305  are configured as source followers of the source signal. Each is provided a common supply voltage V D , thus the voltage at replica node N R  substantially tracks (replicates) the output stage voltage at node N L . The replica stage response is the voltage/current behavior of the replica stage in response to the source signal. 
     The feedback stage comprises a voltage divider  306 ,  307  coupled to the replica node N R  and coupled to the negative terminal of the differential amplifier  302 . Negative feedback of a portion of the replica voltage V R  is therefore provided to the negative input of the differential amplifier  302 . The feedback proportion of V R  is R/(R+R2). 
     The output stage comprises output transistor  305 . An attached load may be represented as a current I L , an impedance R L , and a capacitance C L . The capacitance C L  affects the stability of the power supply when coupled to the load. The current I L  is indicative of the load demand. The voltage/current behavior of the output stage in response to the source signal, under the influence of the load R L  and C L , is referred to as the loaded output stage response. 
     The current regulator stage comprises transistors P 1 , P 2 , and N 1 , and current sinks  308 ,  309 . The components P 1  and P 2  are preferably PFETs but may also be any device or devices that copy (i.e., convey) current proportional to the voltage V L  to control transistor N 1 . Transistor P 2  drives transistor N 1 , and by doing so alters the negative feedback signal level to differential amplifier  302 . The current sinks  308  and  309  maintain a substantially constant (in a typical low-power regulator, on the order of nanoamperes) current on the gates of P 1 , P 2  and N 1 . For applications where a larger amount of current is present at the regulated output, the current sinks  308  and  309  may provide more current (on the order of couple microamperes to 100s of microamperes) to speed up the control loop. 
     Transistor N 1  shunts the feedback stage to ground, meaning forms a parallel, alternate path for current supplied to the feedback stage (thus influencing the voltage fed back to the op amp  302 ). 
     When V L &gt;V R , the gate-to-source voltage of P 2  is lower than its threshold voltage, and P 2  is OFF (it conducts no current). Thus, the feedback voltage is V R *R/(R+R2). A sufficient increase in I L  will cause a drop in V L . If the load current is high enough, V L  will fall below V R . The gate-to-source voltage of P 2  becomes greater than the P 2  threshold voltage, and P 2  turns on and conducts an amount of current determined by current sinks  308  and  309 . P 1  is diode connected; therefore its gate voltage follows V L . When V L  decreases, the gate voltage of P 1  decreases and P 2  is affected (because both transistors P 1  and P 2  share the same gate voltage). The current sinks  308 ,  309  are always active regardless of the level of V L . Current sink  308  turns off N 1  by pulling its gate down. When the V L &lt;V R , the gate voltage comes down causing P 2  to have enough Vgs overdrive. Therefore, P 1  is at that point copying to P 2  the current present on  309 . When the current copied to P 2  is greater than the current on  308 , the gate voltage of N 1  starts to rise hence turning on N 1 . The N 1  device is biased to be in saturation. The amount of saturation will vary depending on the application and other circuit conditions (such as how much V L  dropped below V R ), pulling down V R , causing the op amp  302  to adjust the source signal to bring up V L . The loop gain of the feedback circuit is always less than one (1). The ratio of P 1 :P 2  is set by their channel width (it is preferred to adjust the ratio of a current mirror via channel width, a ratio of length and/or width may be selected). The ratio of P 1 :P 2  may be 1:1, but the ratio of current sinks  308  and  309  may be different, or both a ratio for P 1 :P 2  and the current sinks may be optimally selected for the application. The amount of current through current sources  308 ,  309  determines the specific conditions under which N 1  is turned on. 
     The dominant pole in the power supply is formed by the output impedance of the op amp  302  and the capacitance at Ng. The capacitance at Ng is primarily determined by the gate capacitances of transistors  304 ,  305  and by any compensation capacitor (C L ) in the regulated power supply. The regulated power supply becomes unstable when the pole formed by the load impedance R L  and capacitance C L  move close to the dominant pole. This condition reduces the phase margin in situations where the load capacitance C L  is large enough, or load current I L  is small enough. Instability is prevented by maintaining N 1  OFF when the output pole (C L *R L ) approaches the dominant pole. 
       FIG. 4  illustrates the output voltages of an exemplary power supply comprising a current regulator, for a range of load currents. As with  FIG. 1 , the graphs are skewed worst case corner. The load current is increased linearly from 0 nA to 2 mA. The output voltage does not change more than 10 mV once the feedback stage is operational. 
       FIG. 5  illustrates the current regulator applied to multiple source follower circuits. Source follower circuits are often employed to isolate a source voltage from noisy analog signals, for example. The current regulator may be utilized in multiple source follower stages in a daisy chain, providing load regulation to each stage. Note that P 1 /P 2  and the current sink values may vary from stage to stage. 
       FIG. 6  illustrates an embodiment of a voltage protection circuit. The voltage protection circuit can be used to prevent a signal from going above or below a certain voltage. The two transistors P 1  and P 2 , along with the current sinks, may be sized to limit the output voltage to a fraction of, or a multiple of, the input voltage. 
     Implementations and Alternatives 
     Those having skill in the art will appreciate that there are various logic implementations by which processes and/or systems described herein can be effected (e.g., hardware, software, and/or firmware), and that the preferred vehicle will vary with the context in which the processes are deployed. “Software” refers to logic that may be readily readapted to different purposes (e.g. read/write volatile or nonvolatile memory or media). “Firmware” refers to logic embodied as read-only memories and/or media. Hardware refers to logic embodied as analog and/or digital circuits. If an implementer determines that speed and accuracy are paramount, the implementer may opt for a hardware and/or firmware vehicle; alternatively, if flexibility is paramount, the implementer may opt for a solely software implementation; or, yet again alternatively, the implementer may opt for some combination of hardware, software, and/or firmware. Hence, there are several possible vehicles by which the processes described herein may be effected, none of which is inherently superior to the other in that any vehicle to be utilized is a choice dependent upon the context in which the vehicle will be deployed and the specific concerns (e.g., speed, flexibility, or predictability) of the implementer, any of which may vary. Those skilled in the art will recognize that optical aspects of implementations may involve optically-oriented hardware, software, and or firmware. 
     The foregoing detailed description has set forth various embodiments of the devices and/or processes via the use of block diagrams, flowcharts, and/or examples. Insofar as such block diagrams, flowcharts, and/or examples contain one or more functions and/or operations, it will be understood as notorious by those within the art that each function and/or operation within such block diagrams, flowcharts, or examples can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or virtually any combination thereof. Several portions of the subject matter described herein may be implemented via Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), digital signal processors (DSPs), or other integrated formats. However, those skilled in the art will recognize that some aspects of the embodiments disclosed herein, in whole or in part, can be equivalently implemented in standard integrated circuits, as one or more computer programs running on one or more computers (e.g., as one or more programs running on one or more computer systems), as one or more programs running on one or more processors (e.g., as one or more programs running on one or more microprocessors), as firmware, or as virtually any combination thereof, and that designing the circuitry and/or writing the code for the software and/or firmware would be well within the skill of one of skill in the art in light of this disclosure. In addition, those skilled in the art will appreciate that the mechanisms of the subject matter described herein are capable of being distributed as a program product in a variety of forms, and that an illustrative embodiment of the subject matter described herein applies equally regardless of the particular type of signal bearing media used to actually carry out the distribution. Examples of a signal bearing media include, but are not limited to, the following: recordable type media such as floppy disks, hard disk drives, CD ROMs, digital tape, and computer memory. 
     In a general sense, those skilled in the art will recognize that the various aspects described herein which can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or any combination thereof can be viewed as being composed of various types of “circuitry.” Consequently, as used herein “circuitry” includes, but is not limited to, electrical circuitry having at least one discrete electrical circuit, electrical circuitry having at least one integrated circuit, electrical circuitry having at least one application specific integrated circuit, circuitry forming a general purpose computing device configured by a computer program (e.g., a general purpose computer configured by a computer program which at least partially carries out processes and/or devices described herein, or a microprocessor configured by a computer program which at least partially carries out processes and/or devices described herein), circuitry forming a memory device (e.g., forms of random access memory), and/or circuitry forming a communications device (e.g., a modem, communications switch, or optical-electrical equipment). 
     Those skilled in the art will recognize that it is common within the art to describe devices and/or processes in the fashion set forth herein, and thereafter use standard engineering practices to integrate such described devices and/or processes into larger systems. That is, at least a portion of the devices and/or processes described herein can be integrated into a network processing system via a reasonable amount of experimentation. 
     The foregoing described aspects depict different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected”, or “operably coupled”, to each other to achieve the desired functionality.