Abstract:
A vector locked loop is disclosed having a topology somewhat similar to two cross coupled phase locked loops, but wherein both magnitude and phase are used as feedback signals. The output signal is generated by combining the outputs of two VCOs in a combiner network. This output signal is fed back to the input, where phase and magnitude detectors are used to generate error signals. These error signals are processed to yield control signals for controlling the frequencies of the two VCOs. The vector locked loop can be adapted for a number of applications, including frequency translation, modulation (phase, amplitude or arbitrary), and high efficiency linear power amplification.

Description:
FIELD OF THE INVENTION 
     The present invention relates to signal sources, and more particularly relates to signal sources that employ a feedback loop to lock both the phase and amplitude of the resultant output signal. 
     BACKGROUND AND SUMMARY OF THE INVENTION 
     The concept of feedback signal generators that are both phase- and amplitude-locked was first expounded by Daniel Senderowicz in his 1982 PhD dissertation at U.C. Berkeley, &#34;An NMOS Integrated Vector Lock Loop.&#34; An abbreviated form of this work was published by the IEEE in the Proceedings of the 1982 International Symposium on Circuits and Systems, volume 3, pp. 1164-1167. 
     In the decade since the Senderowicz publications, the vector locked loop has failed to gain widespread acceptance. Indeed, with the exception of a second PhD dissertation (Say, &#34;Vector-Locked Loop Interference Canceller,&#34; Polytechnic Institute of New York, 1985), the published literature seems devoid of any subsequent mention of the technology 
     The particular circuit topology taught by the Senderowicz publications, while advantageous in some respects, limits the circuit&#39;s utility and is believed to have contributed to the vector locked loop&#39;s lack of widespread acceptance In accordance with the present invention, a more versatile topology is disclosed by which the utility of the VLL is increased and the range of applications in which the circuit may be advantageously employed is expanded. 
     As an aid in understanding the circuit topology of the present invention, it will be helpful to first detail certain of its mathematical underpinnings. 
     A vector modulated carrier may be expressed as: 
     
         V(t)=A(t)cos ]ωt+φ(t)]                           (1) 
    
     where A(t) represents the amplitude modulation function and φ(t) represents the phase modulation. 
     Using complex notation the above expression becomes 
     
         V(t)=A(t)e.sup.jφ(t) e.sup.jωt                   ( 2) 
    
     It is often useful to think of a vector modulated signal in terms of a sum of real and imaginary components: 
     
         V(t)=[I(t)+jQ(t)]e.sup.jωt                           ( 3) 
    
     
         where: 
    
     
         I(t)=A(t)cos [φ(t)]                                    (4) 
    
     
         and 
    
     
         Q(t)=A(t)sin [φ(t)]                                    (5) 
    
     A vector modulated signal can be expressed graphically as shown in FIG. 1. A vector with amplitude A(t) and angle φ(t) is shown to be the sum of two orthogonal vectors I(t) and Q(t). The I-Q method is often used to generate vector modulated signals. Two signals with a phase difference of 90 degrees are generated. Their amplitudes are modulated with I(t) and Q(t) respectively. The two modulated signals are then added together to form the final signal 
     Another way of representing a vector modulated signal is to express it as the sum of two signals of equal amplitude, but with arbitrary phase. For simplicity, the signals may be assumed to be of unit amplitude 
     The signal 
     
         V(t)=A(t)cos [ωt+φ(t)]                           (6) 
    
     can be expressed as 
     
         V(t)=cos [ωt+φ1(t)]+cos [ωt+φ2(t)]     (7) 
    
     
         or 
    
     
         V(t)=[e.sup.iφ1(t) +e.sup.jφ2(t) ]e.sup.jωt  ( 8) 
    
     It can be shown that φ1(t) and φ2(t) are related to the amplitude and phase of the signal as: 
     
         φ1(t)=φ(t)+cos.sup.-1 [A(t)]                       (9) 
    
     
         and 
    
     
         φ2([t)=φ(t)-cos.sup.-1 [A(t)]                      (10) 
    
     The reverse relationships are: 
     
         φ(t)=[φ1(t)=φ2(t)]/2                           (11) 
    
     
         and 
    
     
         A(t)=2cos{[φ1(t)-φ2(t)]/2}                         (12) 
    
     FIG. 2 demonstrates that an arbitrary vector with length A(t) and angle φ(t) can be represented as the sum of two vectors of equal length and phases φ1(t) and φ2(t). The length, A(t), of the resultant vector must be less than twice the length of the component vectors. If the two vectors have unit amplitude as in FIG. 2, then: 
     
         A(t)≦2                                              (13) 
    
     Again, assuming component vectors of unit length, if the resultant vector has a length of 2, then φ1(t) is equal to φ2(t). If A(t) is reduced, the two component vectors move apart. 
     With the foregoing by way of background, it can be seen that a modulation signal of arbitrary magnitude and phase can be produced by combining two signals and controlling their phases in a controlled manner. It is on this principle that the vector locked loop circuit topology of the present invention is based 
     The features and advantages of the present invention will be more readily apparent from the following Detailed Description thereof, which proceeds with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram showing the graphical illustration of a vector modulated signal. 
     FIG. 2 is a diagram illustrating that an arbitrary vector can be decomposed into two vectors of equal magnitude. 
     FIG. 3 is a block diagram of a vector locked loop according to one embodiment of the present invention. 
     FIGS. 4A-4D are plots showing the frequency response of the vector locked loop transfer matrix elements. 
     FIG. 5 is a block diagram of the vector locked loop of FIG. 3 adapted for frequency translation. 
     FIG. 6 is a block diagram of the vector locked loop of FIG. 3 adapted for amplitude and/or phase modulation. 
     FIG. 7 is a block diagram of the vector locked loop of FIG. 3 employing class C amplifier stages. 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 3, the illustrated vector locked loop 10 includes first and second oscillators 12, 14, each of which produces an output signal whose frequency is responsive to a signal applied to control inputs 16, 18 thereof A combiner circuit 20 has inputs 22, 24 coupled to outputs 26, 28 of the first and second oscillators 12, 14, and an output 30 coupled to a first input 32 of a phase detector circuit 34 and first input 36 of a magnitude detector circuit 38. A difference circuit 40 has a first input 42 coupled to an output 44 of the phase detector 34, a second input 46 coupled to an output 48 of the magnitude detector 38, and an output 50 coupled to the control input 16 of the first oscillator 12 through a first loop filter 52. A summer circuit 54 has a first input 56 coupled to the output 48 of the magnitude detector 38, a second input 58 coupled to the output 44 of the phase detector 34, and an output 60 coupled to the control input 18 of the second oscillator 14 through a second loop filter 62. Each of the detector circuits 34, 38 also has a second input 64, 66 to which a reference signal can be applied. 
     In its operation, the illustrated vector locked loop 10 is somewhat similar to two cross coupled phase locked loops, where both magnitude and phase are used as feedback signals. The output signal is generated by combining the outputs of the two VCOs 12, 14 in the voltage combiner 20. This output signal is fed back to the input, where the phase and magnitude detectors 34, 38 are used to generate error signals. The difference between the phase error and the magnitude error is fed to the first VCO 12 through the first loop filter 52. The sum of the phase error and the magnitude error are fed to the second VCO 14 through the second loop filter 62. 
     When the loop is locked, the phase error and the magnitude error are driven to zero. The output signal will then track the phase, frequency, and amplitude of the input signal. 
     The operation of certain of the foregoing circuit elements is next examined in greater detail. 
     Phase detector 34 
     Operation of the phase detector 34 is characterized by the equation 
     
         V.sub.out =K.sub.d (φ.sub.i -φ.sub.o)=K.sub.d φ.sub.err(14) 
    
     where φ 1  and φ o  are phases of the input and output signals respectively. 
     Magnitude detector 38 
     Operation of the magnitude detector 38 is characterized by the equation 
     
         V.sub.out =K.sub.m (M.sub.i -M.sub.o)=K.sub.m M.sub.err    (15) 
    
     where M i  and M o  are the magnitudes of the input and output signals respectively. 
     Loop filters 52, 62 
     Elements 52, 62 represent arbitrary loop filter blocks. These blocks can be used to tailor the dynamics of the VLL, affecting bandwidth, acquisition time, etc. They are treated in the following discussion as arbitrary transfer functions F 1  (S) and F 2  (S). 
     Oscillators 12, 14 
     Operation of each of the oscillators (here voltage controlled oscillators) is characterized by the equations 
     
         φ.sub.1 =K.sub.v1 V.sub.in                             (16) 
    
     
         φ.sub.1 (s)=K.sub.v1 V.sub.in /S                       (17) 
    
     
         and 
    
     
         ω.sub.2 =K.sub.v2 V.sub.in                           (18) 
    
     
         φ.sub.2 (s)=K.sub.v2 V.sub.in /s                       (19) 
    
     Kv1 and Kv2 are the voltage to frequency conversion constants of the two VCO&#39;s. 
     The phases at the outputs of the VCO&#39;s can be expressed in matrix form as a function of the signals at the input to the loop filters: ##EQU1## 
     Combiner 20 
     For the sake of simplicity, the outputs of the two VCO&#39;s are assumed to be of unit amplitude. The signal at the output of the combiner 20 depends on the phases of the two VCO&#39;s. 
     
         φ.sub.o =(φ.sub.1 +φ.sub.2)/2                  (21) 
    
     
         M.sub.o =2cos[(φ.sub.1 -φ.sub.2)/2]                (22) 
    
     The expression for the output magnitude can be linearized by taking partial derivatives of M o  with respect to φ1 and φ2. ##EQU2## For values of M o  &lt;&lt;2, A=1 
     The combiner 20 can then be represented by a matrix: ##EQU3## 
     Difference circuit 40/Summer circuit 54 
     The signals at the input to the loop filters 52, 62 are: 
     
         b1=K.sub.d φ.sub.err -K.sub.m M.sub.err                (26) 
    
     
         and 
    
     
         b2=k.sub.d φ.sub.err +K.sub.m M.sub.err                (27) 
    
     These can be expressed in matrix form as: ##EQU4## 
     Transfer matrix: ##EQU5## G(S), when expanded, becomes; ##EQU6## The feedback equation in matrix form can be written as: 
     
         V.sub.o =[I+G(S)].sup.-1 G(S)V.sub.i                       (32) 
    
     where I is the identity matrix, and V o  and V  i  are the input and output vectors respectively. 
     Solving the above matrix equation yields: ##EQU7## 
     It is instructive to note that if F 2  (S)K v2  =F 1  (S)K v1 , the two paths are balanced and the cross terms t 12  and t 21  are zero. This means that the output magnitude is only dependent on the input magnitude, and the output phase is only dependent on the input phase. Even if perfect balance is not achieved, a good balance is desireable because it minimizes the effects of magnitude on phase and phase on magnitude. 
     It should also be noted that the dependencies of output magnitude on input magnitude, and of output phase on input phase, are low-pass functions while the dependencies of output phase on input magnitude, and of output magnitude on input phase, are band-pass functions. The maximum gain of the bandpass function becomes zero if the two paths in the loops are perfectly matched. At low modulation frequencies, the output phase will be equal to the input phase and the output magnitude will be equal to the input magnitude. These relationships are shown in the graphs of FIGS. 4A-4D. 
     The fact that the phase and amplitude of the output are equal to the phase and amplitude of the input makes the VLL useful in a variety of applications, a few of which are detailed below. 
     A first exemplary application of the VLL is as a frequency translator, such as may be used to up-convert low frequency signals that have arbitrary (i.e. vector) modulation. Referring to FIG. 5, the output of the VLL is applied to a mixer 68, to which a local oscillator signal is also applied. A low-pas filter 70 is used to eliminate any unwanted mixer products. The output of the filter 70 is then compared with the input signal, generating amplitude and phase error signals as before. When locked, the frequency of the VLL output signal will be the sum of that of the local oscillator signal and the input signal. Any modulation present in the input signal will also be present in the output signal. 
     A second exemplary application of the illustrated VLL is as a phase and/or amplitude (i.e. vector) modulator. The modulation signal is first decomposed into a phase component and an amplitude component. The phase component is added to the phase error by a summer circuit 72 after the phase detector 34. The amplitude component is added to the magnitude error by a summer circuit 74 at the output of the magnitude detector 38. The frequency of the output signal will be equal to that of the input signal, but it will be modulated in accordance with the AM and phase modulation inputs. 
     A third exemplary application of the illustrated VLL is as a RF power amplifier. 
     Signals with arbitrary modulation require linear amplifiers to maintain signal fidelity. Linear amplification is undesirable, however, due to the very low efficiencies of linear amplifier circuits. The VLL can be used to achieve linear amplification of bandpass signals while utilizing only non-linear power amplifiers. 
     Referring to FIG. 7, the output of each VCO 12, 14 is fed to an identical non-linear power amplifier 76, 78. The outputs of the power amplifiers are then added together in the combiner 20. The output of the combiner is sent to the load (typically an antenna) of the amplifier through a filter 82 that suppresses undesired spectral components. A portion of the signal is then attenuated by an attenuator 80 and compared to the input signal, thereby generating both a phase error and an amplitude error. Again, both of these errors are nulled. The output then is an accurate reproduction of the input signal. The gain of the system is the reciprocal of the attenuation. 
     Having described and illustrated the principles of my invention with reference to an illustrative embodiment, it will be recognized that the invention can be modified in arrangement and detail without departing from such principles. For example, while the invention has been illustrated with reference to circuits employing voltage controlled oscillators, it will be recognized that the invention can be practiced with any other signal sources that are responsive to control signals. Similarly, while the invention has been illustrated with reference to a pair of summer/difference circuits that combine the output signals from the phase and magnitude detectors and control the VCOs therefrom, it will be recognized that a variety of other circuit blocks can be substituted for these elements. Such other circuit blocks may produce output control signals according to a variety of different matrix transfer functions from the phase error and magnitude error input signals, of which only a single illustrative matrix transfer function has been illustrated. 
     Still further, while the invention has been illustrated with reference to VCOs that provide equal-amplitude output signals, it will be recognized that this need not be the case. While VCOs with different output amplitudes cannot ordinarily be combined to provide an output signal of zero magnitude (since the requirement of equal and opposite cannot be met), this is a limitation that does not matter in certain embodiments of the invention. In yet other cases it is desirable to provide an equalization circuit between at least one of the VCO outputs and the combiner circuit so that the signal amplitudes can be precisely matched prior to combining. 
     In view of the many possible embodiments to which the principles of my invention may be put, it should be recognized that the detailed embodiment is illustrative only and should not be taken as limiting the scope of my invention. Rather, I claim as my invention all such embodiments as may come within the scope and spirit of the following claims and equivalents thereto.