Abstract:
The detailed description described embodiments of highly efficient power management systems configurable to simultaneously generate various output voltage levels for different components, sub-assemblies, and devices of electronic devices, sub-systems, and systems. In particular, the described embodiments include power management systems that substantially reduce or eliminate the need for inductors, large numbers of capacitors, and complex switching techniques to transform an available voltage level from a system power source, such as a battery, to more desirable power supply voltages. Some described embodiments include a charge pump that uses only two flying capacitors to simultaneously generate multiple supply outputs, where each of the multiple supply outputs may provide either the same or a different output voltage level. The described embodiments also include efficient power management systems that flexibly provide highly accurate voltage levels that are substantially insensitive to the voltage level provided by a system power source, such as a battery.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. provisional patent application No. 61/387,600, filed Sep. 29, 2010, the disclosure of which is incorporated herein by reference in its entirety. 
     
    
     FIELD OF THE DISCLOSURE 
       [0002]    The embodiments described herein relate to a power management system for flexibly providing various output voltage levels to the components, sub-assemblies, and devices of electronic devices and systems. The embodiments described herein are further related to charge pump circuits that may be configured to simultaneously generate multiple supply voltage outputs, where each of the supply voltage outputs may be flexibly configured to provide a desired output voltage level. In addition, the embodiments described herein are still further related to various multiple output μC charge pump systems, where the supply voltage outputs provided by the charge pump circuits may be post regulated to provide highly accuralte voltage levels with a minimum impact on overall effeciency of the power management system. 
       BACKGROUND 
       [0003]    Electronic devices and systems typically include a wide variety of components, sub-assemblies, and devices. For example, new electronic devices, such as mobile devices, may include memory, microprocessors, communication interfaces, transceivers, receivers, and display components. In addition, in many cases, these components, sub-assemblies, and devices will have differing power supply voltage and current requirements. For example, a display component configured to be in a sleep mode or turned off in order to conserve power may require a different power supply voltage level than when the display component is normally operating. Likewise, the power supply voltages and current requirements of the components, sub-assemblies, and devices may also vary depending upon the operational mode of the electronic devices and systems. These varying system power supply needs may be further complicated in the case where a battery is used to provide a system power source. 
         [0004]    To meet the varying power supply needs of these diverse components, sub-assemblies, and devices, some electronic devices and systems rely upon power supply systems that use inductors to convert the voltage levels available from a system power source, such as a battery, to more desirable power supply voltages. In some cases, multiple inductors may be used. Other power supply systems may employ large numbers of capacitors to transform an available voltage level from a system power source, such as a battery, to more desirable power supply voltages. In addition, as the number of capacitors and inductors increase, the power supply systems may need to employ increased numbers of power switch and complex switching techniques to convert the voltage levels of an available system power source to more desirable power supply voltages. 
         [0005]    Also, in some cases, components, sub-assemblies, and devices of these electronic devices and systems may require highly accurate voltage levels in order to properly function. In some cases where the system power source is provided by a battery, power supply systems that employ large numbers of capacitors or multiple inductors to transform a voltage level from an available system power source to a highly accurate voltage level may consume substantial amounts of energy, require substantially increased silicon areas or module areas, and be economically expensive. 
         [0006]    Accordingly, there is a need to develop more efficient power management systems that may be reconfigured to provide a desired output voltage to each of the components, sub-assemblies, and devices of electronic devices and systems based upon the operational mode of the electronic devices and systems. In addition, there is also a need to develop power management systems that substantially reduce or eliminate the need for inductors and large numbers of capacitors to transform an available voltage level from a system power source, such as a battery, to more desirable power supply voltages. There is also a need to develop efficient power management systems that can flexibly provide highly accurate voltage levels that are substantially insensitive to a change in voltage level provided by a system power source, such as a battery. 
       SUMMARY 
       [0007]    Embodiments disclosed in the detailed description relate to highly efficient power management systems configurable to simultaneously generate various output voltage levels for different components, sub-assemblies, and devices of electronic devices, sub-systems, and systems. In particular, the described embodiments include power management systems that substantially reduce or eliminate the need for inductors, large numbers of capacitors, and complex switching techniques to transform an available voltage level from a system power source, such as a battery, to more desirable power supply voltages. Some described embodiments include a charge pump that uses only two flying capacitors to simultaneously generate multiple supply outputs, where each of the multiple supply outputs may provide either the same or a different output voltage level. The described embodiments also include efficient power management systems that flexibly provide highly accurate voltage levels that are substantially insensitive to the voltage level provided by a system power source, such as a battery. 
         [0008]    One embodiment of the efficient power management systems described here includes a method for simultaneously generating a first output voltage on a first charge pump output and a second output voltage on a second charge pump output of a charge pump, where the charge pump includes only a first flying capacitor and a second flying capacitor. The method may include a step of in a first phase of operation of the charge pump, configuring the first flying capacitor and the second flying capacitor to provide a first communication path between a supply voltage and a first charge pump output in order to store charge on a first output capacitor associated with the first charge pump output; The method may further include a step of establishing a first communication path through at least one of the first flying capacitor and the second flying capacitor to the first charge pump output. The method may further include a step of establishing a second communication path between the first charge pump output. 
         [0009]    In another embodiment of the efficient power management systems described herein may include another method for simultaneously generating a first output voltage on a first charge pump output and a second output voltage on a second charge pump output of a charge pump from a supply voltage, where the charge pump includes only a first flying capacitor and a second flying capacitor. The method may include a step for establishing a first communication path from the supply voltage through at least one of the first flying capacitor and the second flying capacitor to a first charge pump output capacitor associated with the first charge pump output such that a charge is transferred from at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or a combination thereof, to substantially establish the first output voltage on the first charge pump output capacitor. The method may further include a step of establishing a second communication path between the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that the charge transferred from at least one of the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output substantially maintains the first output voltage on the first charge pump output capacitor. In addition, the method may further include a step of establishing a third communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to a second output capacitor associated with the second charge pump output such that the charge transferred from the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or a combination thereof, substantially generates the second output voltage on a second charge pump output capacitor associated with the second charge pump output. 
         [0010]    Yet another embodiment of the efficient power management systems described herein may include another method for simultaneously generating with a charge pump a plurality of output voltages for a plurality of charge pump outputs, where charge pump derives each of the plurality of output voltages for each of the plurality of charge pump outputs from a supply voltage, wherein the charge pump includes only a first flying capacitor and a second flying capacitor. This method may include a step of establishing a first communication path from the supply voltage through at least one of the first flying capacitor and the second flying capacitor to a first charge pump output capacitor associated with a first charge pump output such that charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or a combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially generate a first output voltage on the first charge pump output capacitor, a step of establishing a second communication path from the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that charge flows between the at least one of the first flying capacitor, the second flying capacitor, the supply voltage and/or a combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially maintain generation of the first output voltage on the first charge pump output capacitor, and a further step of establishing a second charge pump output communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to a second charge pump output capacitor associated with a second charge pump output such that charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the second charge pump output capacitor associated with the second charge pump output to substantially generate a second output voltage on the second charge pump output capacitor associated with the second charge pump output. In addition, the first flying capacitor includes a first positively charged terminal and a first negatively charged terminal, and wherein the second flying capacitor includes a second positively charged terminal and a second negatively charged terminal. Accordingly, where establishing the first communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that the charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially generate a first output voltage on the first charge pump output capacitor, the method may further include a step of coupling the first flying capacitor and the second flying capacitor in series between the supply voltage and the first charge pump output capacitor to generate the first output voltage on the first charge pump output capacitor. Likewise, where the method includes coupling the first flying capacitor and the second flying capacitor in series between the supply voltage and the first charge pump output capacitor the method may further include a step of coupling the first positively charged terminal of the first flying capacitor to the supply voltage and the second negatively charged terminal of the second flying capacitor to the first charge pump output capacitor. Also, where the method further includes coupling the first flying capacitor and the second flying capacitor in series between the supply voltage and the first charge pump output capacitor generate the first output voltage on the first charge pump output capacitor, the method may include the further step of coupling the second negatively charged terminal of the second flying capacitor to the supply voltage and the first negatively charged terminal of the first flying capacitor to the first charge pump output capacitor. 
         [0011]    Likewise, where the method includes the step of coupling the first flying capacitor and the second flying capacitor in series between the supply voltage and the first charge pump output capacitor generate the first output voltage on the first charge pump output capacitor, the method may further include another step of establishing a communication path, which is included in the first communication path, from the first positively charged terminal of the first flying capacitor to the supply voltage. Moreover, in this case, the method may include another step of establishing a communication path, which is included in the first communication path, from the second positively charged terminal of the second flying capacitor to the supply voltage. In this case, the method may further include the addition step of coupling the first negatively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. 
         [0012]    In some embodiments of the method, which include the step of coupling the first flying capacitor and the second flying capacitor in series from the supply voltage and the first charge pump output capacitor, the method may also include establishing a communication path, which is included in the first communication path, from the second negatively charged terminal of the second flying capacitor to the supply voltage. In this case, the method may also couple the first positively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. 
         [0013]    In still other embodiments of this method, which include the step of coupling the first flying capacitor and the second flying capacitor in series from the supply voltage and the first charge pump output capacitor, the method may further establish a communication path, which is included in the first communication path, from the first negatively charged terminal of the first flying capacitor to the first charge pump output capacitor. In this case, the method may also establish a communication path, which is included in the first communication path, from the second negatively charged terminal of the second flying capacitor to the first charge pump output capacitor. Also in this case, the method may further coupled the first negatively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. 
         [0014]    In still other embodiments of the me method that include the step of coupling the first flying capacitor and the second flying capacitor in series from the supply voltage and the first charge pump output capacitor, the method may further establish a communication path, which is included in the first communication path, from the second positively charged terminal of the second flying capacitor to the first charge pump output capacitor. In this case, the method may also couple the first positively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. 
         [0015]    In still another embodiment of the method which includes the step of establishing the first communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that the charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially generate a first output voltage on the first charge pump output capacitor the method may further couple the first flying capacitor in parallel with the second flying capacitor between the supply voltage and the first charge pump output capacitor. In this case, the method may also couple the first positively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor to the supply voltage. 
         [0016]    In still another embodiment of this method, the method may establish the first communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that the charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially generate a first output voltage on the first charge pump output capacitor occurs during a first phase of operation of the charge pump. In this case, the method may also, during the first phase of operation of the charge pump, the second charge pump output capacitor associated with the second charge pump output is disconnected from the supply voltage, the first flying capacitor, and the second flying capacitor. 
         [0017]    In another embodiment of this method which establishes the second communication path from the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that charge flows between the at least one of the first flying capacitor, the second flying capacitor, the supply voltage and/or the combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially maintain generation of the first output voltage on the first charge pump output capacitor, the method may further couple the first flying capacitor and the second flying capacitor in series between the first charge pump output capacitor and ground. In doing so, the method may also establish a communication path, which is included in the second communication path, from the first positively charged terminal of the first flying capacitor to the first charge pump output capacitor. In this case, the method may establish a communication path, which is included in the second communication path, from the second positively charged terminal of the second flying capacitor to the first charge pump output capacitor. Likewise, in this case, the method may couple the first positively charged terminal of the first flying capacitor to the second negatively charged terminal of the second flying capacitor. In addition, where the method couples the first flying capacitor and the second flying capacitor in series between the first charge pump output capacitor and ground, the method may further establish a communication path, which is included in the second communication path, from the first positively charged terminal of the first flying capacitor to the first charge pump output capacitor. 
         [0018]    In another embodiment of this method, which includes the step of coupling the first flying capacitor and the second flying capacitor in series between the first charge pump output capacitor and ground the method may further establish a communication path, which is included in the second communication path, from the second positively charged terminal of the second flying capacitor to the first charge pump output capacitor Accordingly, the method may also couple the first negatively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. Also, the method may couple the first positively charged terminal of the first flying capacitor to the second negatively charged terminal of the second flying capacitor. 
         [0019]    Alternatively, where the method copies the first flying capacitor and the second flying capacitor in series between the first charge pump output capacitor and ground, the method may establish a communication path, which is included in the second communication path, from the second negatively charged terminal of the second flying capacitor to the first charge pump output capacitor. In this case, the method may establish a communication path, which is included in the second communication path, from the first positively charged terminal of the first flying capacitor to the first charge pump output capacitor. Accordingly, the method may also couple the first positively charged terminal of the first flying capacitor to the second negatively charged terminal of the second flying capacitor. 
         [0020]    In still another embodiment of the method, when the method establishes the second communication path from the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that charge flows between the at least one of the first flying capacitor, the second flying capacitor, the supply voltage and/or the combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially maintain generation of the first output voltage on the first charge pump output capacitor, the method may further couple coupling the second flying capacitor between the first charge pump output capacitor and one of the supply voltage and ground. In this case, the method may also alternatively couple the second positively charged terminal of the second flying capacitor to the first charge pump output capacitor and the second negatively charged terminal of the second flying capacitor to ground. In this case, the method may could the first positively charged terminal of the first flying capacitor to the first charge pump output capacitor and the first negatively charged terminal of the second flying capacitor to ground. In the case where the method couples the second flying capacitor between the first charge pump output capacitor and one of the supply voltage and the ground, the method may further couple the second positively charged terminal of the second flying capacitor to the supply voltage and the second negatively charged terminal of the second flying capacitor to the first charge pump output capacitor. 
         [0021]    In still other embodiments of the method may establish the second communication path from the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that charge flows between the at least one of the first flying capacitor, the second flying capacitor, the supply voltage and/or the combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially maintain generation of the first output voltage on the first charge pump output capacitor occurs during a second phase of operation of the charge pump. In this case, during the second phase of operation of the charge pump, the second charge pump output capacitor associated with the second charge pump output is disconnected from the supply voltage, the first flying capacitor, and the second flying capacitor. Also, when the method establishes the second charge pump output communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the second charge pump output capacitor associated with the second charge pump output such that the charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the second charge pump output capacitor associated with the second charge pump output to substantially generate the second output voltage, the method may further include coupling the first flying capacitor and the second flying capacitor in series between the supply voltage and the second charge pump output capacitor to generate the second output voltage on the second charge pump output capacitor. Also, in some cases, the method may further include coupling the first positively charged terminal of the first flying capacitor to the supply voltage and the second negatively charged terminal of the second flying capacitor to the second charge pump output capacitor. In still other cases, the method may couple the second negatively charged terminal of the second flying capacitor to the supply voltage and the first negatively charged terminal of the first flying capacitor to the second charge pump output capacitor. Likewise, when the method couples the first flying capacitor and the second flying capacitor in series between the supply voltage and the second charge pump output capacitor generate the first output voltage on the second charge pump output capacitor, the method may further establish a communication path, which is included in the second charge pump output communication path, from the first positively charged terminal of the first flying capacitor to the supply voltage. 
         [0022]    Where the method includes the step of coupling the first flying capacitor and the second flying capacitor in series from the supply voltage and the second charge pump output capacitor, the method may further establish a communication path, which is included in the second charge pump output communication path, from the second positively charged terminal of the second flying capacitor to the supply voltage. In this case, the method may couple the first negatively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. Likewise, where the method couples the first flying capacitor and the second flying capacitor in series from the supply voltage and the second charge pump output capacitor, the method may establish a communication path, which is included in the second charge pump output communication path, from the second negatively charged terminal of the second flying capacitor to the supply voltage. In this case, the method may further include the step of coupling the first positively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. In the case where the method couples the first flying capacitor and the second flying capacitor in series from the supply voltage and the second charge pump output capacitor, the method may further establish a communication path, which is included in the second charge pump output communication path, from the first negatively charged terminal of the first flying capacitor to the second charge pump output capacitor. As a result, in some embodiments, the method may couple the first flying capacitor and the second flying capacitor in series from the supply voltage and the second charge pump output. This may further include establishing a communication path, which is included in the second charge pump output communication path, from the second negatively charged terminal of the second flying capacitor to the second charge pump output capacitor. 
         [0023]    Accordingly, in some embodiments, the method may further couple the first negatively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. 
         [0024]    In the case where the method couples the first flying capacitor and the second flying capacitor in series from the supply voltage and the second charge pump output capacitor, the method may further establish a communication path, which is included in the second charge pump output communication path, from the second positively charged terminal of the second flying capacitor to the second charge pump output capacitor. In this case, the method may couple coupling the first positively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. 
         [0025]    In another embodiment of the method, which establishes the second charge pump output communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the second charge pump output capacitor associated with the second charge pump output such that the charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the second charge pump output capacitor associated with the second charge pump output to substantially generate the second output voltage, the method may also couple the first flying capacitor in parallel with the second flying capacitor between the supply voltage and the second charge pump output capacitor. In the where the method couples the first flying capacitor in parallel with the second flying capacitor between the supply voltage and the second charge pump output, the method may further couple the first positively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor to the supply voltage. 
         [0026]    In still other embodiments of the method, where establishing the second charge pump output communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the second charge pump output capacitor associated with the second charge pump output such that the charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the second charge pump output capacitor associated with the second charge pump output to substantially generate the second output voltage occurs during one of a third phase of operation of the charge pump and a fourth phase of operation of the charge pump. In this case, in some cases, during the fourth phase of operation of the charge pump the charge pump establishes the second charge pump output communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the second charge pump output capacitor associated with the second charge pump output in order to generate the second output voltage on the second charge pump output, the fourth phase of operation of the charge pump. Accordingly, the method may further include the step of disconnecting the first charge pump output capacitor associated with the first charge pump output from the supply voltage, the first flying capacitor, and the second flying capacitor. Likewise, in the case where the charge pump establishes the second charge pump output communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the second charge pump output capacitor associated with the second charge pump output in order to generate the second output voltage on the second charge pump output during the fourth phase of operation, the method may also, prior to establishing the second charge pump output communication path, establish a third communication path from the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that charge flows between the at least one of the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially maintain generation of the first output voltage on the first charge pump output capacitor. Accordingly, in this case, the method may further couple the first flying capacitor and the second flying capacitor in series between the first charge pump output capacitor and ground. In the case where the method couples the first flying capacitor and the second flying capacitor in series from the first charge pump output capacitor and ground by establishing a communication path, which is included in the third communication path, from the first positively charged terminal of the first flying capacitor to the first charge pump output capacitor. Otherwise, the method may, in some embodiments, establish a communication path, which is included in the third communication path, from the second positively charged terminal of the second flying capacitor to the first charge pump output capacitor. In these cases, the method may further couple the first positively charged terminal of the first flying capacitor to the second negatively charged terminal of the second flying capacitor. In the further case where the method couples the first flying capacitor and the second flying capacitor in series from the first charge pump output capacitor and ground, the method may further include the step of establishing a communication path, which is included in the third communication path, from the first positively charged terminal of the first flying capacitor to the first charge pump output capacitor. Also, when the method includes the step of coupling the first flying capacitor and the second flying capacitor in series from the first charge pump output capacitor and ground, the method may establishes a communication path, which is included in the third communication path, from the second positively charged terminal of the second flying capacitor to the first charge pump output capacitor. In some cases this permits the method to couple the first negatively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. 
         [0027]    Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0028]    The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. INSERT SUMMARY OF DRAWINGS HERE. 
           [0029]      FIG. 1A  depicts a first embodiment of a multiple output μC charge pump system  10 A. 
           [0030]      FIG. 1B  depicts a second embodiment of the multiple output μC charge pump system  10 B. 
           [0031]      FIG. 2A  depicts a first embodiment of a dual output μC charge pump circuit  12 A. 
           [0032]      FIG. 2B  depicts a second embodiment of the dual output μC charge pump circuit  12 A. 
           [0033]      FIG. 2C  depicts a third embodiment of the dual output μC charge pump circuit  12 A. 
           [0034]      FIG. 2D  depicts a fourth embodiment of the dual output μC charge pump circuit  12 A. 
           [0035]      FIGS. 3A-B  depict a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a first buck/buck mode. 
           [0036]      FIG. 4  depicts a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a second buck/buck mode. 
           [0037]      FIG. 5  depicts a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a third buck/buck mode. 
           [0038]      FIG. 6  depicts a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a fourth buck/buck mode. 
           [0039]      FIGS. 7A-B  depict a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a fifth buck/buck mode. 
           [0040]      FIGS. 8A-B  depict a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a first buck/boost mode. 
           [0041]      FIG. 9  depicts a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a second buck/boost mode. 
           [0042]      FIG. 10  depicts a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a third buck/boost mode. 
           [0043]      FIG. 11  depicts a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a fourth buck/boost mode. 
           [0044]      FIGS. 12A-B  depict a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a fifth buck/boost mode. 
           [0045]      FIGS. 13A-B  depict a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a sixth buck/boost mode. 
           [0046]      FIG. 14  depicts a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a seventh buck/boost mode. 
           [0047]      FIG. 15  depicts a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a ninth buck/boost mode. 
           [0048]      FIGS. 16A-B  depict a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a tenth buck/boost mode. 
           [0049]      FIGS. 17A-B  depict a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a first boost/buck mode. 
           [0050]      FIG. 18  depicts a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a second boost/buck mode. 
           [0051]      FIG. 19  depicts a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a third boost/buck mode. 
           [0052]      FIG. 20  depicts a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a fourth boost/buck mode. 
           [0053]      FIGS. 21A-B  depict a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a fifth boost/buck mode. 
           [0054]      FIGS. 22A-B  depict a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a sixth boost/buck mode. 
           [0055]      FIG. 23  depicts a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a seventh boost/buck mode. 
           [0056]      FIG. 24  depicts a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a ninth boost/buck mode. 
           [0057]      FIGS. 25A-B  depict a mode of operation of an embodiment of a dual output μC charge pump configured to operate in a tenth boost/buck mode. 
       
    
    
     DETAILED DESCRIPTION 
       [0058]    The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
         [0059]    One embodiment of the efficient power management systems described here includes a method for simultaneously generating a first output voltage on a first charge pump output and a second output voltage on a second charge pump output of a charge pump, where the charge pump includes only a first flying capacitor and a second flying capacitor. The method may include a step of in a first phase of operation of the charge pump, configuring the first flying capacitor and the second flying capacitor to provide a first communication path between a supply voltage and a first charge pump output in order to store charge on a first output capacitor associated with the first charge pump output; The method may further include a step of establishing a first communication path through at least one of the first flying capacitor and the second flying capacitor to the first charge pump output. The method may further include a step of establishing a second communication path between the first charge pump output. 
         [0060]    In another embodiment of the efficient power management systems described herein may include another method for simultaneously generating a first output voltage on a first charge pump output and a second output voltage on a second charge pump output of a charge pump from a supply voltage, where the charge pump includes only a first flying capacitor and a second flying capacitor. The method may include a step for establishing a first communication path from the supply voltage through at least one of the first flying capacitor and the second flying capacitor to a first charge pump output capacitor associated with the first charge pump output such that a charge is transferred from at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or a combination thereof, to substantially establish the first output voltage on the first charge pump output capacitor. The method may further include a step of establishing a second communication path between the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that the charge transferred from at least one of the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output substantially maintains the first output voltage on the first charge pump output capacitor. In addition, the method may further include a step of establishing a third communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to a second output capacitor associated with the second charge pump output such that the charge transferred from the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or a combination thereof, substantially generates the second output voltage on a second charge pump output capacitor associated with the second charge pump output. 
         [0061]    Yet another embodiment of the efficient power management systems described herein may include another method for simultaneously generating with a charge pump a plurality of output voltages for a plurality of charge pump outputs, where charge pump derives each of the plurality of output voltages for each of the plurality of charge pump outputs from a supply voltage, wherein the charge pump includes only a first flying capacitor and a second flying capacitor. This method may include a step of establishing a first communication path from the supply voltage through at least one of the first flying capacitor and the second flying capacitor to a first charge pump output capacitor associated with a first charge pump output such that charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or a combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially generate a first output voltage on the first charge pump output capacitor, a step of establishing a second communication path from the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that charge flows between the at least one of the first flying capacitor, the second flying capacitor, the supply voltage and/or a combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially maintain generation of the first output voltage on the first charge pump output capacitor, and a further step of establishing a second charge pump output communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to a second charge pump output capacitor associated with a second charge pump output such that charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the second charge pump output capacitor associated with the second charge pump output to substantially generate a second output voltage on the second charge pump output capacitor associated with the second charge pump output. In addition, the first flying capacitor includes a first positively charged terminal and a first negatively charged terminal, and wherein the second flying capacitor includes a second positively charged terminal and a second negatively charged terminal. Accordingly, where establishing the first communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that the charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially generate a first output voltage on the first charge pump output capacitor, the method may further include a step of coupling the first flying capacitor and the second flying capacitor in series between the supply voltage and the first charge pump output capacitor to generate the first output voltage on the first charge pump output capacitor. Likewise, where the method includes coupling the first flying capacitor and the second flying capacitor in series between the supply voltage and the first charge pump output capacitor the method may further include a step of coupling the first positively charged terminal of the first flying capacitor to the supply voltage and the second negatively charged terminal of the second flying capacitor to the first charge pump output capacitor. Also, where the method further includes coupling the first flying capacitor and the second flying capacitor in series between the supply voltage and the first charge pump output capacitor generate the first output voltage on the first charge pump output capacitor, the method may include the further step of coupling the second negatively charged terminal of the second flying capacitor to the supply voltage and the first negatively charged terminal of the first flying capacitor to the first charge pump output capacitor. 
         [0062]    Likewise, where the method includes the step of coupling the first flying capacitor and the second flying capacitor in series between the supply voltage and the first charge pump output capacitor generate the first output voltage on the first charge pump output capacitor, the method may further include another step of establishing a communication path, which is included in the first communication path, from the first positively charged terminal of the first flying capacitor to the supply voltage. Moreover, in this case, the method may include another step of establishing a communication path, which is included in the first communication path, from the second positively charged terminal of the second flying capacitor to the supply voltage. In this case, the method may further include the addition step of coupling the first negatively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. 
         [0063]    In some embodiments of the method, which include the step of coupling the first flying capacitor and the second flying capacitor in series from the supply voltage and the first charge pump output capacitor, the method may also include establishing a communication path, which is included in the first communication path, from the second negatively charged terminal of the second flying capacitor to the supply voltage. In this case, the method may also couple the first positively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. 
         [0064]    In still other embodiments of this method, which include the step of coupling the first flying capacitor and the second flying capacitor in series from the supply voltage and the first charge pump output capacitor, the method may further establish a communication path, which is included in the first communication path, from the first negatively charged terminal of the first flying capacitor to the first charge pump output capacitor. In this case, the method may also establish a communication path, which is included in the first communication path, from the second negatively charged terminal of the second flying capacitor to the first charge pump output capacitor. Also in this case, the method may further coupled the first negatively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. 
         [0065]    In still other embodiments of the me method that include the step of coupling the first flying capacitor and the second flying capacitor in series from the supply voltage and the first charge pump output capacitor, the method may further establish a communication path, which is included in the first communication path, from the second positively charged terminal of the second flying capacitor to the first charge pump output capacitor. In this case, the method may also couple the first positively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. 
         [0066]    In still another embodiment of the method which includes the step of establishing the first communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that the charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially generate a first output voltage on the first charge pump output capacitor the method may further couple the first flying capacitor in parallel with the second flying capacitor between the supply voltage and the first charge pump output capacitor. In this case, the method may also couple the first positively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor to the supply voltage. 
         [0067]    In still another embodiment of this method, the method may establish the first communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that the charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially generate a first output voltage on the first charge pump output capacitor occurs during a first phase of operation of the charge pump. In this case, the method may also, during the first phase of operation of the charge pump, the second charge pump output capacitor associated with the second charge pump output is disconnected from the supply voltage, the first flying capacitor, and the second flying capacitor. 
         [0068]    In another embodiment of this method which establishes the second communication path from the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that charge flows between the at least one of the first flying capacitor, the second flying capacitor, the supply voltage and/or the combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially maintain generation of the first output voltage on the first charge pump output capacitor, the method may further couple the first flying capacitor and the second flying capacitor in series between the first charge pump output capacitor and ground. In doing so, the method may also establish a communication path, which is included in the second communication path, from the first positively charged terminal of the first flying capacitor to the first charge pump output capacitor. In this case, the method may establish a communication path, which is included in the second communication path, from the second positively charged terminal of the second flying capacitor to the first charge pump output capacitor. Likewise, in this case, the method may couple the first positively charged terminal of the first flying capacitor to the second negatively charged terminal of the second flying capacitor. In addition, where the method couples the first flying capacitor and the second flying capacitor in series between the first charge pump output capacitor and ground, the method may further establish a communication path, which is included in the second communication path, from the first positively charged terminal of the first flying capacitor to the first charge pump output capacitor. 
         [0069]    In another embodiment of this method, which includes the step of 
         [0000]    coupling the first flying capacitor and the second flying capacitor in series between the first charge pump output capacitor and ground the method may further establish a communication path, which is included in the second communication path, from the second positively charged terminal of the second flying capacitor to the first charge pump output capacitor Accordingly, the method may also couple the first negatively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. Also, the method may couple the first positively charged terminal of the first flying capacitor to the second negatively charged terminal of the second flying capacitor. 
         [0070]    Alternatively, where the method copies the first flying capacitor and the second flying capacitor in series between the first charge pump output capacitor and ground, the method may establish a communication path, which is included in the second communication path, from the second negatively charged terminal of the second flying capacitor to the first charge pump output capacitor. In this case, the method may establish a communication path, which is included in the second communication path, from the first positively charged terminal of the first flying capacitor to the first charge pump output capacitor. Accordingly, the method may also couple the first positively charged terminal of the first flying capacitor to the second negatively charged terminal of the second flying capacitor. 
         [0071]    In still another embodiment of the method, when the method establishes the second communication path from the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that charge flows between the at least one of the first flying capacitor, the second flying capacitor, the supply voltage and/or the combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially maintain generation of the first output voltage on the first charge pump output capacitor, the method may further couple coupling the second flying capacitor between the first charge pump output capacitor and one of the supply voltage and ground. In this case, the method may also alternatively couple the second positively charged terminal of the second flying capacitor to the first charge pump output capacitor and the second negatively charged terminal of the second flying capacitor to ground. In this case, the method may could the first positively charged terminal of the first flying capacitor to the first charge pump output capacitor and the first negatively charged terminal of the second flying capacitor to ground. In the case where the method couples the second flying capacitor between the first charge pump output capacitor and one of the supply voltage and the ground, the method may further couple the second positively charged terminal of the second flying capacitor to the supply voltage and the second negatively charged terminal of the second flying capacitor to the first charge pump output capacitor. 
         [0072]    In still other embodiments of the method may establish the second communication path from the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that charge flows between the at least one of the first flying capacitor, the second flying capacitor, the supply voltage and/or the combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially maintain generation of the first output voltage on the first charge pump output capacitor occurs during a second phase of operation of the charge pump. In this case, during the second phase of operation of the charge pump, the second charge pump output capacitor associated with the second charge pump output is disconnected from the supply voltage, the first flying capacitor, and the second flying capacitor. Also, when the method establishes the second charge pump output communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the second charge pump output capacitor associated with the second charge pump output such that the charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the second charge pump output capacitor associated with the second charge pump output to substantially generate the second output voltage, the method may further include coupling the first flying capacitor and the second flying capacitor in series between the supply voltage and the second charge pump output capacitor to generate the second output voltage on the second charge pump output capacitor. Also, in some cases, the method may further include coupling the first positively charged terminal of the first flying capacitor to the supply voltage and the second negatively charged terminal of the second flying capacitor to the second charge pump output capacitor. In still other cases, the method may couple the second negatively charged terminal of the second flying capacitor to the supply voltage and the first negatively charged terminal of the first flying capacitor to the second charge pump output capacitor. Likewise, when the method couples the first flying capacitor and the second flying capacitor in series between the supply voltage and the second charge pump output capacitor generate the first output voltage on the second charge pump output capacitor, the method may further establish a communication path, which is included in the second charge pump output communication path, from the first positively charged terminal of the first flying capacitor to the supply voltage. 
         [0073]    Where the method includes the step of coupling the first flying capacitor and the second flying capacitor in series from the supply voltage and the second charge pump output capacitor, the method may further establish a communication path, which is included in the second charge pump output communication path, from the second positively charged terminal of the second flying capacitor to the supply voltage. In this case, the method may couple the first negatively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. Likewise, where the method couples the first flying capacitor and the second flying capacitor in series from the supply voltage and the second charge pump output capacitor, the method may establish a communication path, which is included in the second charge pump output communication path, from the second negatively charged terminal of the second flying capacitor to the supply voltage. In this case, the method may further include the step of coupling the first positively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. In the case where the method couples the first flying capacitor and the second flying capacitor in series from the supply voltage and the second charge pump output capacitor, the method may further establish a communication path, which is included in the second charge pump output communication path, from the first negatively charged terminal of the first flying capacitor to the second charge pump output capacitor. As a result, in some embodiments, the method may couple the first flying capacitor and the second flying capacitor in series from the supply voltage and the second charge pump output. This may further include establishing a communication path, which is included in the second charge pump output communication path, from the second negatively charged terminal of the second flying capacitor to the second charge pump output capacitor. Accordingly, in some embodiments, the method may further couple the first negatively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. 
         [0074]    In the case where the method couples the first flying capacitor and the second flying capacitor in series from the supply voltage and the second charge pump output capacitor, the method may further establish a communication path, which is included in the second charge pump output communication path, from the second positively charged terminal of the second flying capacitor to the second charge pump output capacitor. In this case, the method may couple coupling the first positively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. 
         [0075]    In another embodiment of the method, which establishes the second charge pump output communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the second charge pump output capacitor associated with the second charge pump output such that the charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the second charge pump output capacitor associated with the second charge pump output to substantially generate the second output voltage, the method may also couple the first flying capacitor in parallel with the second flying capacitor between the supply voltage and the second charge pump output capacitor. In the where the method couples the first flying capacitor in parallel with the second flying capacitor between the supply voltage and the second charge pump output, the method may further couple the first positively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor to the supply voltage. 
         [0076]    In still other embodiments of the method, where establishing the second charge pump output communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the second charge pump output capacitor associated with the second charge pump output such that the charge flows between the at least one of the supply voltage, the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the second charge pump output capacitor associated with the second charge pump output to substantially generate the second output voltage occurs during one of a third phase of operation of the charge pump and a fourth phase of operation of the charge pump. In this case, in some cases, during the fourth phase of operation of the charge pump the charge pump establishes the second charge pump output communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the second charge pump output capacitor associated with the second charge pump output in order to generate the second output voltage on the second charge pump output, the fourth phase of operation of the charge pump. Accordingly, the method may further include the step of disconnecting the first charge pump output capacitor associated with the first charge pump output from the supply voltage, the first flying capacitor, and the second flying capacitor. Likewise, in the case where the charge pump establishes the second charge pump output communication path from the supply voltage through the at least one of the first flying capacitor and the second flying capacitor to the second charge pump output capacitor associated with the second charge pump output in order to generate the second output voltage on the second charge pump output during the fourth phase of operation, the method may also, prior to establishing the second charge pump output communication path, establish a third communication path from the at least one of the first flying capacitor and the second flying capacitor to the first charge pump output capacitor associated with the first charge pump output such that charge flows between the at least one of the first flying capacitor, the second flying capacitor, and/or the combination thereof, and the first charge pump output capacitor associated with the first charge pump output to substantially maintain generation of the first output voltage on the first charge pump output capacitor. Accordingly, in this case, the method may further couple the first flying capacitor and the second flying capacitor in series between the first charge pump output capacitor and ground. In the case where the method couples the first flying capacitor and the second flying capacitor in series from the first charge pump output capacitor and ground by establishing a communication path, which is included in the third communication path, from the first positively charged terminal of the first flying capacitor to the first charge pump output capacitor. Otherwise, the method may, in some embodiments, establish a communication path, which is included in the third communication path, from the second positively charged terminal of the second flying capacitor to the first charge pump output capacitor. In these cases, the method may further couple the first positively charged terminal of the first flying capacitor to the second negatively charged terminal of the second flying capacitor. In the further case where the method couples the first flying capacitor and the second flying capacitor in series from the first charge pump output capacitor and ground, the method may further include the step of establishing a communication path, which is included in the third communication path, from the first positively charged terminal of the first flying capacitor to the first charge pump output capacitor. Also, when the method includes the step of coupling the first flying capacitor and the second flying capacitor in series from the first charge pump output capacitor and ground, the method may establishes a communication path, which is included in the third communication path, from the second positively charged terminal of the second flying capacitor to the first charge pump output capacitor. In some cases this permits the method to couple the first negatively charged terminal of the first flying capacitor to the second positively charged terminal of the second flying capacitor. 
         [0077]      FIG. 1  depicts a first example embodiment of multiple output μC charge pump system  10 A that uses two flyback capacitors to generate multiple output voltages. The multiple output μC charge pump system  10 A may be configured to provide multiple supply voltages to various circuits of an electronic system. 
         [0078]    As a first example, the multiple output μC charge pump system  10 A may include a first example of a dual output μC charge pump circuit  12 . The multiple output μC charge pump system  10 A may include a controller  14  coupled to the dual output μC charge pump circuit  12  via a control bus  16 . In some embodiments, the controller  14  may be coupled to a supply voltage sense circuit  18  via the control bus  16 . The supply voltage sense circuit  18  may be configured to provide the controller  14  a measured or estimated voltage of the supply voltage  20 . As an example, the supply voltage  20  may be derived from a battery  22  that provides the supply voltage  20 . The supply voltage  20  provided by the battery  22  may be a battery voltage, V BAT . 
         [0079]    Advantageously, in some alternative embodiments, (not shown), the supply voltage sense circuit  18  may be directly coupled to controller  14 . As an example, the supply voltage sense circuit  18  may be directly coupled to an interrupt input of the controller  14 . As a result, this configuration may permit the controller  14  to more quickly respond to changes in the supply voltage  20 . 
         [0080]    The dual output μC charge pump circuit  12  may also be coupled to the supply voltage  20 . The dual output μC charge pump circuit  12  may be configured to generate a first μC charge pump output  24  and a second μC charge pump output  26 . As an example, the controller  14  may configure the dual output μC charge pump circuit  12  to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  and a second μC charge pump output voltage, (V μC     —     OUT2 ), on the second μC charge pump output  26 . 
         [0081]    In some embodiments of the multiple output μC charge pump system  10 A, the controller  14  may configure the dual output μC charge pump circuit  12  such that the first μC charge pump output  24  operates in a “buck mode” of operation. In the case where the dual output μC charge pump circuit  12  operates the first μC charge pump output  24  in the buck mode of operation, the first μC charge pump output  24  provides a “bucked” output voltage level relative to the supply voltage  20  as the first μC charge pump output voltage, (V μC     —     OUT1 ). As an example, neglecting losses in the signal paths between the supply voltage  20  and the first μC charge pump output  24 , when the dual output μC charge pump circuit  12  is configured by the controller  14  to operate the first μC charge pump output  24  in the buck mode of operation, the first μC charge pump output voltage, (V μC     —     OUT1 ), may have a magnitude that is equal to or less than the supply voltage  20 . Illustratively, in the case where the supply voltage  20  is substantially equal to the battery voltage, V BAT , and the first μC charge pump output  24  is configured to operate in the buck mode of operation, the first μC charge pump output voltage, (V μC     —     OUT1 ), may have a magnitude less than or equal to the battery voltage, V BAT . 
         [0082]    In a similar fashion, in some embodiments of the multiple output μC charge pump system  10 A, the controller  14  may configure the dual output μC charge pump circuit  12  such that the second μC charge pump output  26  operates in a buck mode of operation. In the case where the dual output μC charge pump circuit  12  operates the second μC charge pump output  26  in the buck mode of operation, the second μC charge pump output  26  provides a bucked output voltage level relative to the supply voltage  20  as the second μC charge pump output voltage, (V μC     —     OUT2 ). As an example, neglecting losses in the signal paths between the supply voltage  20  and the second μC charge pump output  26 , when the dual output μC charge pump circuit  12  is configured by the controller  14  to operate the second μC charge pump output  26  in the buck mode of operation, the second μC charge pump output voltage, (V μC     —     OUT2 ), may have a magnitude that is equal to or less than the supply voltage  20 . Illustratively, in the case where the supply voltage  20  is substantially equal to the battery voltage, V BAT , and the second μC charge pump output  26  is configured to operate in the buck mode of operation, the second μC charge pump output voltage, (V μC     —     OUT2 ), may have a magnitude less than or equal to the battery voltage, V BAT . 
         [0083]    In other embodiments of the multiple output μC charge pump system  10 A, the controller  14  may configure the dual output μC charge pump circuit  12  such that the first μC charge pump output  24  operates in a “boost mode” of operation. In the case where the dual output μC charge pump circuit  12  operates the first μC charge pump output  24  in the boost mode of operation, the first μC charge pump output  24  provides a “boosted” output voltage level relative to the supply voltage  20  as the first μC charge pump output voltage, (V μC     —     OUT1 ). As an example, neglecting losses in the signal paths between the supply voltage  20  and the first μC charge pump output  24 , when the dual output μC charge pump circuit  12  is configured by the controller  14  to operate the first μC charge pump output  24  in the boost mode of operation, the first μC charge pump output voltage, (V μC     —     OUT1 ), may have a magnitude that is greater than the supply voltage  20 . Illustratively, in the case where the supply voltage  20  is substantially equal to the battery voltage, V BAT , and the first μC charge pump output  24  is configured to operate in the boost mode of operation, the first μC charge pump output voltage, (V μC     —     OUT1 ), may have a magnitude that is greater than the battery voltage, V BAT . 
         [0084]    Likewise, in some embodiments of the multiple output μC charge pump system  10 A, the controller  14  may configure the dual output μC charge pump circuit  12  such that the second μC charge pump output  26  operates in a boost mode of operation. In the case where the dual output μC charge pump circuit  12  operates the second μC charge pump output  26  in the boost mode of operation, the second μC charge pump output  26  provides the boosted output voltage level relative to the supply voltage  20  as the second μC charge pump output voltage, (V μC     —     OUT2 ). As an example, neglecting losses in the signal paths between the supply voltage  20  and the second μC charge pump output  26 , when the dual output μC charge pump circuit  12  is configured by the controller  14  to operate the second μC charge pump output  26  in the boost mode of operation, the second μC charge pump output voltage, (V μC     —     OUT2 ), may have a magnitude that is greater than the supply voltage  20 . Illustratively, in the case where the supply voltage  20  is substantially equal to the battery voltage, V BAT , and the second μC charge pump output  26  is configured to operate in the boost mode of operation, the second μC charge pump output voltage, (V μC     —     OUT2 ), may have a magnitude that is greater than the battery voltage, V BAT . 
         [0085]    The controller  14  may configure the dual output μC charge pump circuit  12  to operate in various modes of operation. As a non-limiting example of these modes of operation, the controller  14  may configure the dual output μC charge pump circuit  12  to operate in a “buck/buck mode” of operation, a “buck/boost mode” of operation, and/or a “boost/buck mode” of operation. As one example, when the controller  14  configures the dual output μC charge pump circuit  12  to operate in the buck/buck mode of operation, the dual output μC charge pump circuit  12  operates the first μC charge pump output  24  in a buck mode of operation and the second μC charge pump output  26  in a buck mode of operation. As another example, when the controller  14  configures the dual output μC charge pump circuit  12  to operate in the buck/boost mode of operation, the dual output μC charge pump circuit  12  operates the first μC charge pump output  24  in a buck mode of operation and the second μC charge pump output  26  in a boost mode of operation. As yet another example, when the controller  14  configures the dual output μC charge pump circuit  12  to operate in the boost/buck mode of operation, the dual output μC charge pump circuit  12  operates the first μC charge pump output  24  in a boost mode of operation and the second μC charge pump output  26  in a buck mode of operation. 
         [0086]    In some embodiments, the controller  14  may be configured to control the modes of operation of the dual output μC charge pump circuit  12  based upon the measured or estimated voltage of the supply voltage  20 . Alternatively, controller  14  may be configured to control the operation of the dual output μC charge pump circuit  12  based upon an operational mode of a system or an integrated chip in which the multiple output μC charge pump system  10 A is being used. 
         [0087]    The first μC charge pump output  24  may be configured to provide the first μC charge pump output voltage, (V μC     —     OUT1 ), to a first μLDO circuit  28 . The first μLDO circuit  28  may be a micro-low drop out regulator circuit. The second μC charge pump output  26  may be configured to provide the second μC charge pump output voltage, (V μC     —     OUT2 ), to a second μLDO circuit  30 . The second μLDO circuit  30  may be a micro-low drop out regulator circuit. 
         [0088]    The first μLDO circuit  28  may generate a first μLDO output  32  to provide a first μLDO output voltage, V μLDO1 , based upon a first μLDO reference signal  34 . The first μLDO reference signal  34  may provide a first μLDO reference voltage, V μLDO1     —     REF , as an input to the first μLDO circuit  28 . In some embodiments, the first μLDO reference voltage, V μLDO1     —     REF , may be based upon a first μLDO reference parameter provided by the controller  14 . In other embodiments, the first μLDO reference voltage, V μLDO1     —     REF , may be based upon a first reference signal provided from a first external circuit (not shown). 
         [0089]    Similarly, the second μLDO circuit  30  may generate a second μLDO output  36  to provide a second μLDO output voltage, V μLDO2 , based upon a second μLDO reference signal  38 . The second μLDO reference signal  38  may provide a second μLDO reference voltage, V μLDO2     —     REF , as an input to the second μLDO circuit  30 . In some embodiments, the second μLDO reference voltage, V μLDO2     —     REF , may be based upon a second μLDO reference parameter provided by the controller  14 . In other embodiments, the second μLDO reference voltage, V μLDO2     —     REF , may be based upon a second reference signal provided from a second external circuit (not shown). Advantageously, this permits the first μLDO output voltage, V μLDO1 , and the second μLDO output voltage, V μLDO2 , to be independently set. In this case, the multiple output μC charge pump system  10 A may optimize the voltage level provided to individual circuits. 
         [0090]    In some embodiments, the first μLDO reference signal  34  provided as an input to the first μLDO circuit  28  and the second μLDO reference signal  38  provided as an input to the second μLDO circuit  30  may be the same. In this case, the first μLDO output voltage, V μLDO1 , and the second μLDO output voltage, V μLDO2 , may provide a substantially same output voltage level. In this case, the multiple output μC charge pump system  10 A may ensure related circuits receive approximately the same supply voltage. 
         [0091]    As further depicted in  FIG. 1 , the dual output μC charge pump circuit  12  includes a multiple output μC charge pump switch matrix and control circuit  40  operably coupled to a first flying capacitor  42 , (C FLY1 ), and a second flying capacitor  44 , (C FLY2 ). The first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ), may be either polarized or non-polarized capacitors. The first flying capacitor  42 , (C FLY1 ), includes a first terminal  42 A and a second terminal  42 B. The second flying capacitor  44 , (C FLY2 ), includes a first terminal  44 A and a second terminal  44 B. During operation of the dual output μC charge pump circuit  12 , a first flying capacitor voltage, (V CAP     —     FLY1 ), may be developed across the first flying capacitor  42 , (C FLY1 ). Likewise, a second flying capacitor voltage, (V CAP     —     FLY2 ), may be developed across the second flying capacitor  44 , (C FLY2 ). 
         [0092]    The multiple output μC charge pump switch matrix and control circuit  40  may include the first μC charge pump output  24  coupled to a first μC charge pump output capacitor  46 , (C μC     —     OUT1 ). The multiple output μC charge pump switch matrix and control circuit  40  may further include the second μC charge pump output  26  coupled to a second μC charge pump output capacitor  48 , (C μC-     —     OUT2 ). 
         [0093]    As will be described below, during operation of the dual output μC charge pump circuit  12 , the multiple output μC charge pump switch matrix and control circuit  40  may operably couple the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ), in various series and parallel configurations between the supply voltage  20 , the first μC charge pump output  24 , the second μC charge pump output  26 , and ground to transfer charge from the supply voltage  20  to the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). The charge stored on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), may provide the first μLDO output voltage, V μLDO1 , on the first μC charge pump output  24 . The charge stored on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ), may provide the second μLDO output voltage, V μLDO2 , on the second μC charge pump output  26 . In some embodiments of the dual output μC charge pump circuit  12 , more than two flying capactiors may be used to generate the first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  and the second μC charge pump output voltage, (V μC     —     OUT2 ), on the second μC charge pump output  26 . However, advantageously, as depicted in  FIG. 1A , and to be described, the various embodiments of the dual output μC charge pump circuit  12  described herein may be configured to generate the desired output voltage levels, namely the first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  and the second μC charge pump output voltage, (V μC     —     OUT2 ), on the second μC charge pump output  26 , using only the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ). It may be appreciated that those embodiment of the dual output μC charge pump circuit  12  that only use the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ), to generate the desired output voltage levels on the first μC charge pump output  24  and the second μC charge pump output  26  may provide improved technical performance due to reduced complexity and reduced response time verses those embodiments that include more than two flying capacitors. 
         [0094]    In some embodiments, the first μLDO output voltage, V μLDO1 , on the first μC charge pump output  24 , and the second μLDO output voltage, V μLDO2 , on the second μC charge pump output  26  are provided directly to one or more circuits. In alternative embodiments, the first μLDO output voltage, V μLDO1 , on the first μC charge pump output  24 , and the second μLDO output voltage, V μLDO2 , may advantageously be further regulated by one or more micro-low drop out regulator circuits to provide separate supply outputs. Advantageously, the use of the one or more micro-low drop out regulator circuits permits a single μC charge pump output to provide multiple regulated voltage supplies to meet the needs of various circuits in an electronic integrated chip. As an example, one of the multiple regulated voltage supplies may be used to power a first digital logic circuit that uses a first supply voltage while another of the multiple regulated voltage supplies a second digital logic circuit or a microprocessor that uses a second supply voltage, where the magnitude of the first supply voltage differs from the magnitude of the second supply voltage. 
         [0095]    As an example, the multiple output μC charge pump system  10 A depicted in  FIG. 1A  further includes a first μLDO circuit  28 , that provides a first μLDO output voltage, V μLDO1 , based on the first μC charge pump output voltage, (V μC     —     OUT1 ), as a first μLDO output  32 . The multiple output μC charge pump system  10 A depicted in  FIG. 1A  also includes a second μLDO circuit  30 , that provides a second μLDO output voltage, V μLDO2 , based on the second μC charge pump output voltage, (V μC     —     OUT2 ), as a second μLDO output  36 . 
         [0096]    In still other embodiments, additional micro-low drop out regulator circuits may be coupled to the various μC charge pump outputs to generate additional post regulated output supply voltages. As an example, (not depicted in  FIG. 10A ), some embodiments may include two or more micro-low drop out regulator circuits providing independent output voltage levels based upon one of the μC charge pump outputs. 
         [0097]    The first μLDO circuit  28  may include a first power field effect transistor  50 , a first error amplifier  52 , a first resistor  54 , and a second resistor  56 . The first power field effect transistor  50  may include a first terminal  50 A, a second terminal  50 B, and a control terminal  50 C, The first error amplifier  52  may include a non-inverting error amplifier input  52 A, an inverting error amplifier input  52 B, and an error amplifier output  52 C. The first resistor  54  may have a first resistance R 1 . The second resistor  56  may have a second resistance R 2 . 
         [0098]    The first terminal  50 A of the first power field effect transistor  50  may be coupled to the first μC charge pump output  24 . The second terminal  50 B of the first power field effect transistor  50  may be coupled to the first μLDO output  32  and a first resistor terminal of the first resistor  54 . The control terminal  50 C of the first power field effect transistor  50  may be coupled to the error amplifier output  52 C of the first error amplifier  52 . The non-inverting error amplifier input  52 A of the first error amplifier  52  may be coupled to the first μLDO reference signal  34  and configured to receive the first μLDO reference voltage, V μLDO1     —     REF . 
         [0099]    The second terminal of the first resistor  54  may be coupled to the non-inverting error amplifier input  52 B of the first error amplifier  52  such that the first resistor  54  is coupled between the second terminal  50 B of the first power field effect transistor  50  and the non-inverting error amplifier input  52 A of the first error amplifier  52 . The first terminal of the second resistor  56  may be coupled to the second terminal of the first resistor  54  and the non-inverting error amplifier input  52 A of the first error amplifier  52 . The second terminal of the second resistor  56  may be coupled to ground. As a result, the first resistor  54  and the second resistor  56  may form a first resistor divider network configured to provide a first feedback signal to the non-inverting error amplifier input  52 A of the first error amplifier  52 . 
         [0100]    The magnitude of the first feedback signal may be based on the first μLDO output voltage, V μLDO1 , and a first ratio of the first resistor divider network created by the first resistor  54  and the second resistor  56 . The first ratio of the first resistor divider network may be based on the ratio of the first resistance, R 1 , of the first resistor  54  to the second resistance, R 2 , of the second resistor  56 . 
         [0101]    Operationally, the first μLDO circuit  28  may regulate the first μLDO output voltage, V μLDO1 , provided as the first μLDO output  32  based on the first μLDO reference voltage, V μLDO1     —     REF , and the first feedback signal provided to the non-inverting error amplifier input  52 A of the first error amplifier  52 , where the first feedback signal is based on the ratio of the first resistance, R 1 , of the first resistor  54  to the second resistance, R 2 , of the second resistor  56 . 
         [0102]    The second μLDO circuit  30  may include a second power field effect transistor  58 , a second error amplifier  60 , a third resistor  62 , and a fourth resistor  64 . The second power field effect transistor  58  may include a first terminal  58 A, a second terminal  58 B, and a control terminal  58 C, The second error amplifier  60  may include a non-inverting error amplifier input  60 A, an inverting error amplifier input  60 B, and an error amplifier output  60 C. The third resistor  62  may have a third resistance R 3 . The fourth resistor  64  may have a fourth resistance R 4 . 
         [0103]    The first terminal  58 A of the second power field effect transistor  58  may be coupled to the second μC charge pump output  26 . The second terminal  58 B of the second power field effect transistor  58  may be coupled to the second μLDO output  36  and a first resistor terminal of the third resistor  62 . The control terminal  58 C of the second power field effect transistor  58  may be coupled to the error amplifier output  60 C of the second error amplifier  60 . The non-inverting error amplifier input  60 A of the second error amplifier  60  may be coupled to the second μLDO reference signal  38  and configured to receive the second μLDO reference voltage, V μLDO2     —     REF . 
         [0104]    The second terminal of the third resistor  62  may be coupled to the non-inverting error amplifier input  60 B of the second error amplifier  60  such that the third resistor  62  is coupled between the second terminal  58 B of the second power field effect transistor  58  and the non-inverting error amplifier input  60 A of the second error amplifier  60 . The first terminal of the fourth resistor  64  may be coupled to the second terminal of the third resistor  62  and the non-inverting error amplifier input  60 A of the second error amplifier  60 . The second terminal of the fourth resistor  64  may be coupled to ground. As a result, the third resistor  62  and the fourth resistor  64  may form a second resistor divider network configured to provide a second feedback signal to the non-inverting error amplifier input  60 A of the second error amplifier  60 . 
         [0105]    The magnitude of the second feedback signal may be based on the second μLDO output voltage, V μLDO2 , and the second ratio of the second resistor divider network created by the third resistor  62  and the fourth resistor  64 . The second ratio of the second resistor divider network may be based on the ratio of the third resistance, R 3 , of the third resistor  62  to the fourth resistance, R 4 , of the fourth resistor  64 . 
         [0106]    Operationally, the second μLDO circuit  30  operates similarly to the first μLDO circuit  28 . The second μLDO circuit  30  may regulate the second μLDO output voltage, V μLDO2 , provided as the second μLDO output  36 , based on the second μLDO reference voltage, V μLDO2     —     REF , and the second feedback signal provided to the non-inverting error amplifier input  60 A of the second error amplifier  60 , where the second feedback signal is based on the ratio of the third resistance, R 3 , of the third resistor  62  to the fourth resistance, R 4 , of the fourth resistor  64 . 
         [0107]    The multiple output μC charge pump system  10 A may further include a μC charge pump clock circuit  66 . The μC charge pump clock circuit  66  generates a μC charge pump clock  68 , which is provided to the multiple output μC charge pump switch matrix and control circuit  40 . The multiple output μC charge pump switch matrix and control circuit  40  uses the μC charge pump clock  68  to govern the operation of the dual output μC charge pump circuit  12 . The controller  14  may be coupled to the μC charge pump clock circuit  66  via the control bus  16 . The controller  14  may be configured to place the μC charge pump clock circuit  66  in various operational modes. In addition, the μC charge pump clock circuit  66  may be configured to generate the μC charge pump clock  68  based upon various reference clock sources. As a non-limiting list of examples, the various refence clock sources used to generate the μC charge pump clock  68  may include a frequency locked loop (FLL) circuit, a reference clock from a sub-system of an integrated chip, a power supply system or a power management system. In still other embodiments, the various refence clock sources may be derived from a fixed reference oscillator, a variable oscillator, a voltage controlled oscillator, a programmable controlled oscillator, and/or a clock divider circuit. As another example, in some embodiments, the various reference clock sources may be dividing, multiplying, or a combination there of, to generate the μC charge pump clock  68 . In other embodiments, (not shown), the controller  14 , may advantageously be directly coupled to the μC charge pump clock circuit  66  in order to allow the controller  14  to directly control the operation of the μC charge pump clock circuit  66 . Advantageously, when the μC charge pump clock circuit  66  is directly coupled to the controller  14 , the controller more directly controls the μC charge pump clock circuit  66  without the protocol overhead sometimes associated with a shared control bus. 
         [0108]      FIG. 2A  depicts a first embodiment of the dual output μC charge pump circuit  12  depicted in  FIG. 1A  as a dual output μC charge pump circuit  12 A. For the sake of convenience, and not by way of limitation, the dual output μC charge pump circuit  12 A is described with continuing reference to various elements of the first embodiment of the multiple output μC charge pump system  10 A depicted in  FIG. 1A  including, but not limited to, the controller  14 , control bus  16 , the supply voltage sense circuit  18 , the supply voltage  20 , the battery  22 , the μC charge pump clock circuit  66 , the μC charge pump clock  68 , the first μLDO circuit  28 , the second μLDO circuit  30 , the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ). 
         [0109]    The dual output μC charge pump circuit  12 A includes a multiple output μC charge pump switch matrix and control circuit  40 A. The multiple output μC charge pump switch matrix and control circuit  40 A may include a dual output μC charge pump switch matrix circuit  70 A and a multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may include a μC charge pump control interface operably coupled to the control bus  16 . Similar to the dual output μC charge pump circuit  12  of  FIG. 1A , the controller  14  may configure the dual output μC charge pump circuit  12 A to operate in various modes of operation via the control bus  16 . As a non-limiting example, similar to the dual output μC charge pump circuit  12  of  FIG. 1A , the dual output μC charge pump circuit  12 A of  FIG. 2A  may be configured by the controller  14  to operate in a “buck/buck mode” of operation, a “buck/boost mode” of operation, and/or a “boost/buck mode” of operation. In addition, multiple output μC charge pump control circuit  72 A may be further configured to receive the μC charge pump clock  68  from the μC charge pump clock circuit  66 . 
         [0110]    The dual output μC charge pump switch matrix circuit  70 A may be configured by the multiple output μC charge pump control circuit  72 A to generate the first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  and the second μC charge pump output voltage, (V μC     —     OUT2 ), on the second μC charge pump output  26  based on a selected mode of operation of the dual output μC charge pump circuit  12 A. 
         [0111]    To simplify the description of the operation of the dual output μC charge pump circuit  12 A and the operation of the dual output μC charge pump switch matrix circuit  70 A,  FIG. 2A  depicts the first flying capacitor  42 , (C FLY1 ), the second flying capacitor  44 , (C FLY2 ), as being incorporated into the dual output μC charge pump switch matrix circuit  70 A. In addition, as discussed above relative to the dual output μC charge pump circuit  12 , depicted in  FIG. 1A , some embodiments of dual output μC charge pump circuit  12  may include and use more than two flying capactiors to generate the first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  and the second μC charge pump output voltage, (V μC     —     OUT2 ), on the second μC charge pump output  26 . However, advantageously, as depicted in  FIG. 2A , and to be described with respect to the modes of operation of the dual output μC charge pump circuit  12 A depicted in  FIG. 2A  and described below, some embodiments of the dual output μC charge pump circuit  12 A may be configured to generate the desired output voltage levels, namely the first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  and the second μC charge pump output voltage, (V μC     —     OUT2 ), on the second μC charge pump output  26 , using only the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ). In other words, as will be described below, some embodiments of the dual output μC charge pump circuit  12 A may be configured to generate the variously described output voltage levels corresponding to a “buck/buck mode” of operation, a “buck/boost mode” of operation, and/or a “boost/buck mode” of operation using only the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ). It may be appreciated that those embodiment of the dual output μC charge pump circuit  12 A that only use the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ), to generate the desired output voltage levels on the first μC charge pump output  24  and the second μC charge pump output  26  may provide improved technical performance due to reduced complexity and reduced response time verses embodiments that include more than two flying capacitors. 
         [0112]    The dual output μC charge pump switch matrix circuit  70 A may include the first flying capacitor  42 , (C FLY1 ), the second flying capacitor  44 , (C FLY2 ), a first switch  74 , (SW 1), a second switch  76 , (SW 2), a third switch  78 , (SW 3), a fourth switch  80 , (SW 4), a fifth switch  82 , (SW 5), a sixth switch  84 , (SW 6), a seventh switch  86 , (SW 7), an eighth switch  88 , (SW 8), a ninth switch  90 , (SW 9), a tenth switch  92 , (SW 10), an eleventh switch  94 , (SW 11), a twelfth switch  96 , (SW 12), a thirteenth switch  98 , (SW 13), a fourteenth switch  100 , (SW 14), and a fifteenth switch  102 , (SW 15). 
         [0113]    In some embodiments of the dual output μC charge pump switch matrix circuit  70 A, the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15), include solid state based switches, micro-electromechanical systems (MEMS) contact based switches, or combinations thereof. Illustratively, as a non-limiting example, solid state based switches may include field effect transistors, insulator-on-semiconductor based transistors, bipolar based transistors, and/or a combination thereof. The example solid state based switches may be fabricated using various semiconductor device fabrication processes, techniques, and materials. As an example, some solid state based switches may be based on a gallium nitride (GaN) process. In some embodiments, gallium nitride metal/oxide semiconductor field-effect transistors may be used to create the solid state switches. In still other embodiments, the gallium nitride metal/oxide semiconductor field-effect transistors may be a gallium nitride field effect transistor. As an example, the gallium nitride field effect transistor may be an enhancement mode gallium nitride metal-oxide-semiconductor field-effect transistor (MOSFET). [Nadim: what other processes could you invision being used?] 
         [0114]    Returning to the description of the multiple output μC charge pump control circuit  72 A, the multiple output μC charge pump control circuit  72 A may further include a first switch control configured to provide a first switch control signal  108  to the first switch  74 , (SW 1), to control the operation of the first switch  74 , (SW 1), a second switch control configured to provide a second switch control signal  110  to the second switch  76 , (SW 2), to control the operation of the second switch  76 , (SW 2), a third switch control configured to provide a third switch control signal  112  to the third switch  78 , (SW 3), to control the operation of the third switch  78 , (SW 3), a fourth switch control configured to provide a fourth switch control signal  114  to the fourth switch  80 , (SW 4), to control the operation of the fourth switch  80 , (SW 4), a fifth switch control configured to provide a fifth switch control signal  116  to the fifth switch  82 , (SW 5), to control the operation of the fifth switch  82 , (SW 5), a sixth switch control configured to provide a sixth switch control signal  118  to the sixth switch  84 , (SW 6), to control the operation of the sixth switch  84 , (SW 6), a seventh switch control configured to provide a seventh switch control signal  120  to the seventh switch  86 , (SW 7), to control the operation of the seventh switch  86 , (SW 7), an eighth switch control configured to provide an eighth switch control signal  122  to the eighth switch  88 , (SW 8), to control the operation of the eighth switch  88 , (SW 8), a ninth switch control configured to provide a ninth switch control signal  124  to the ninth switch  90 , (SW 9), to control the operation of the ninth switch  90 , (SW 9), a tenth switch control configured to provide a tenth switch control signal  126  to the tenth switch  92 , (SW 10), to control the operation of the tenth switch  92 , (SW 10), an eleventh switch control configured to provide an eleventh switch control signal  128  to the eleventh switch  94 , (SW 11), to control the operation of the eleventh switch  94 , (SW 11), a twelfth switch control configured to provide a twelfth switch control signal  130  to the twelfth switch  96 , (SW 12), to control the operation of the twelfth switch  96 , (SW 12), a thirteenth switch control configured to provide a thirteenth switch control signal  132  to the thirteenth switch  98 , (SW 13), to control the operation of the thirteenth switch  98 , (SW 13), a fourteenth switch control configured to provide a fourteenth switch control signal  134  to the fourteenth switch  100 , (SW 14), to control the operation of the fourteenth switch  100 , (SW 14), and a fifteenth switch control configured to provide a fifteenth switch control signal  136  to the fifteenth switch  102 , (SW 15), to control the operation of the fifteenth switch  102 , (SW 15). 
         [0115]    The first switch  74 , (SW 1), may be coupled between the supply voltage  20  and the first terminal  42 A of the first flying capacitor  42 , (C FLY1 ), The first switch  74 , (SW 1), may include a first switch control input configured to receive the first switch control signal  108  from the multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may configure the first switch control signal  108  to operably open and close the first switch  74 , (SW 1), based upon the various modes of operation of the dual output μC charge pump circuit  12 A. 
         [0116]    The second switch  76 , (SW 2), may be coupled between the first terminal  42 A of the first flying capacitor  42 , (C FLY1 ), and the first μC charge pump output  24 . The second switch  76 , (SW 2), may include a second switch control input configured to receive the second switch control signal  110  from the multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may configure the second switch control signal  110  to operably open and close the second switch  76 , (SW 2), based upon the various modes of operation of the dual output μC charge pump circuit  12 A. 
         [0117]    The third switch  78 , (SW 3), may be coupled between the second terminal  42 B of the first flying capacitor  42 , (C FLY1 ), and ground. The third switch  78 , (SW 3), may include a third switch control input configured to receive the third switch control signal  112  from the multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may configure the third switch control signal  112  to operably open and close the third switch  78 , (SW 3), based upon the various modes of operation of the dual output μC charge pump circuit  12 A. 
         [0118]    The fourth switch  80 , (SW 4), may be coupled between the second terminal  42 B of the first flying capacitor  42 , (C FLY1 ), and the first μC charge pump output  24 . The fourth switch  80 , (SW 4), may include a fourth switch control input configured to receive the fourth switch control signal  114  from the multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may configure the fourth switch control signal  114  to operably open and close the fourth switch  80 , (SW 4), based upon the various modes of operation of the dual output μC charge pump circuit  12 A. 
         [0119]    The fifth switch  82 , (SW 5), may be coupled between the second terminal  42 B of the first flying capacitor  42 , (C FLY1 ), and the first terminal  44 A of the second flying capacitor  44 , (C FLY2 ), The fifth switch  82 , (SW 5), may include a fifth switch control input configured to receive the fifth switch control signal  116  from the multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may configure the fifth switch control signal  116  to operably open and close the fifth switch  82 , (SW 5), based upon the various modes of operation of the dual output μC charge pump circuit  12 A. 
         [0120]    The sixth switch  84 , (SW 6), may be coupled between the first terminal  44 A of the second flying capacitor  44 , (C FLY2 ), and the supply voltage  20 . The sixth switch  84 , (SW 6), may include a sixth switch control input configured to receive the sixth switch control signal  118  from the multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may configure the sixth switch control signal  118  to operably open and close the sixth switch  84 , (SW 6), based upon the various modes of operation of the dual output μC charge pump circuit  12 A. 
         [0121]    The seventh switch  86 , (SW 7), may be coupled between the first terminal  44 A of the second flying capacitor  44 , (C FLY2 ), and the first μC charge pump output  24 . The seventh switch  86 , (SW 7), may include a seventh switch control input configured to receive the seventh switch control signal  120  from the multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may configure the seventh switch control signal  120  to operably open and close the seventh switch  86 , (SW 7), based upon the various modes of operation of the dual output μC charge pump circuit  12 A. 
         [0122]    The eighth switch  88 , (SW 8), may be coupled between the second terminal  44 B of the second flying capacitor  44 , (C FLY2 ), and ground. The eighth switch  88 , (SW 8), may include an eighth switch control input configured to receive the eighth switch control signal  122  from the multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may configure the eighth switch control signal  122  to operably open and close the eighth switch  88 , (SW 8), based upon the various modes of operation of the dual output μC charge pump circuit  12 A. 
         [0123]    The ninth switch  90 , (SW 9), may be coupled between the second terminal  44 B of the second flying capacitor  44 , (C FLY2 ), and the first μC charge pump output  24 . The ninth switch  90 , (SW 9), may include a ninth switch control input configured to receive the ninth switch control signal  124  from the multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may configure the ninth switch control signal  124  to operably open and close the ninth switch  90 , (SW 9), based upon the various modes of operation of the dual output μC charge pump circuit  12 A. 
         [0124]    The tenth switch  92 , (SW 10), may be coupled between the first terminal  42 A of the first flying capacitor  42 , (C FLY1 ), and the first terminal  44 A of the second flying capacitor  44 , (C FLY2 ). The tenth switch  92 , (SW 10), may include a tenth switch control input configured to receive the tenth switch control signal  126  from the multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may configure the tenth switch control signal  126  to operably open and close the tenth switch  92 , (SW 10), based upon the various modes of operation of the dual output μC charge pump circuit  12 A. 
         [0125]    The eleventh switch  94 , (SW 11), may be coupled between the second terminal  44 B of the second flying capacitor  44 , (C FLY2 ), and the supply voltage  20 . The eleventh switch  94 , (SW 11), may include an eleventh switch control input configured to receive the eleventh switch control signal  128  from the multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may configure the eleventh switch control signal  128  to operably open and close the eleventh switch  94 , (SW 11), based upon the various modes of operation of the dual output μC charge pump circuit  12 A. 
         [0126]    The twelfth switch  96 , (SW 12), may be coupled between the second terminal  44 B of the second flying capacitor  44 , (C FLY2 ), and the second μC charge pump output  26 . The twelfth switch  96 , (SW 12), may include a twelfth switch control input configured to receive the twelfth switch control signal  130  from the multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may configure the twelfth switch control signal  130  to operably open and close the twelfth switch  96 , (SW 12), based upon the various modes of operation of the dual output μC charge pump circuit  12 A. 
         [0127]    The thirteenth switch  98 , (SW 13), may be coupled between the first terminal  44 A of the second flying capacitor  44 , (C FLY2 ), and the second μC charge pump output  26 . The thirteenth switch  98 , (SW 13), may include a thirteenth switch control input configured to receive the thirteenth switch control signal  132  from the multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may configure the thirteenth switch control signal  132  to operably open and close the thirteenth switch  98 , (SW 13), based upon the various modes of operation of the dual output μC charge pump circuit  12 A. 
         [0128]    The fourteenth switch  100 , (SW 14), may be coupled between the second terminal  42 B of the first flying capacitor  42 , (C FLY1 ), and the second μC charge pump output  26 . The fourteenth switch  100 , (SW 14), may include a fourteenth switch control input configured to receive the fourteenth switch control signal  134  from the multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may configure the fourteenth switch control signal  134  to operably open and close the fourteenth switch  100 , (SW 14), based upon the various modes of operation of the dual output μC charge pump circuit  12 A. 
         [0129]    The fifteenth switch  102 , (SW 15), may be coupled between the second terminal  42 B of the first flying capacitor  42 , (C FLY1 ), and the supply voltage  20 . The fifteenth switch  102 , (SW 15), may include a fifteenth switch control input configured to receive the fifteenth switch control signal  136  from the multiple output μC charge pump control circuit  72 A. The multiple output μC charge pump control circuit  72 A may configure the fifteenth switch control signal  136  to operably open and close the fifteenth switch  102 , (SW 15), based upon the various modes of operation of the dual output μC charge pump circuit  12 A. 
         [0130]    Numerous example embodiments of the modes of operation of the dual output μC charge pump circuit  12 A, depicted in  FIG. 2A , will now be described. These example embodiments of the modes of operation of the dual output μC charge pump circuit  12 A are by illustration and not by limitation. For example, various other modes of operation of the dual output μC charge pump circuit  12 A may be used to generate different magnitudes of the first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  and the second μC charge pump output voltage, (V μC     —     OUT2 ), on the second μC charge pump output  26  are described herein. These additional various other modes of operation of the dual output μC charge pump circuit  12 A, as would be evident to one of ordinary skill in the art, are thereby included herein. In addition, for the sake of clarity and brevity, the foregoing description of the modes of operation of the dual output μC charge pump circuit  12 A, depicted in  FIG. 2A , will be accomplished by describing a configuration where the supply voltage  20  is derived from the battery  22  and has a voltage level substantially equal to the battery voltage, V BAT . The description of the modes of operation of the dual output μC charge pump circuit  12 A based on a configuration where the supply voltage  20  is derived from the battery  22  is not by way of limitation and only meant to aid the understanding of the modes of operation of the dual output μC charge pump circuit  12 A and the ratios between the first μC charge pump output voltage, (V μC     —     OUT1 ), generated on the first μC charge pump output  24  to voltage level of the supply voltage  20  and the ratios between the second μC charge pump output voltage, (V μC     —     OUT2 ), generated on the second μC charge pump output  26  to the voltage level of the supply voltage  20 . Accordingly, it will be understood that the use of the battery voltage, V BAT , as an example of the supply voltage  20 , is for illustrative convenience and not by limitation. 
         [0131]    A non-limiting set of example opererational modes of the dual output μC charge pump circuit  12 A will now be discussd with reference to various tables, provided herein. Example operational modes of the dual output μC charge pump circuit  12 A may include one or more buck/buck modes of operation, one or more buck/boost modes of operation, and/or one or more boost/buck modes of operation. 
         [0132]    Illustratively, TABLE 1A, entitled “MODES OF OPERATION TABLE FOR BUCK/BUCK OPERATION OF A DUAL OUTPUT μC CHARGE PUMP CIRCUIT,” describes, in tablulated form, several, non-limiting, example modes of operation of the dual output μC charge pump circuit  12 A configured to operate in a buck/buck mode of operation. The described non-limiting example modes of Buck/Buck modes of operation include: a First (1 st ) Buck/Buck Mode, a Second (2 nd ) Buck/Buck Mode, a Third (3 rd ) Buck/Buck Mode, a Fourth (4 th ) Buck/Buck Mode, a Fifth (5 th ) Buck/Buck Mode, and an OFF Mode. In addition, although not described in detail below, it will be understood that the dual output μC charge pump circuit  12 A may be further configured to operate in addition buck/buck modes of operation, as described in TABLE 1B, entitled “MODES OF OPERATION TABLE FOR BUCK/BUCK OPERATION OF A DUAL OUTPUT μC CHARGE PUMP CIRCUIT.” These addition, non-limiting examples, of Buck/Buck modes of operation may include: a Sixth (6 th ) Buck/Buck Mode, a Seventh (7 th ) Buck/Buck Mode, an Eighth (8 th ) Buck/Buck Mode, a Ninth (9 th ) Buck/Buck Mode, and a Tenth (10 th ) Buck/Buck Mode. 
         [0133]    As depicted in TABLE 1A, each example mode of operation corresponds to an operational ratio, (xμBB RATIO ), of the dual output μC charge pump circuit  12 A, where the operational ratio, (xμBB RATIO ), may provide a relationship between the first μC charge pump output voltage, (V μC     —     OUT1 ), generated by the first μC charge pump output  24  and the second μC charge pump output voltage, (V μC     —     OUT2 ), generated by the second μC charge pump output  26 . The operational ratio, (xμBB RATIO ), may be an operational ratio parameter that is configured by the controller  14  and stored locally in the multiple output μC charge pump control circuit  72 A. 
         [0134]    As described in Table 1A, the dual output μC charge pump circuit  12 A is configured to generate a first μC charge Pump output, (V μC     —     OUT1 ) such that V μC     —     OUT1 =(xμBB RATIO )×V BAT , where V BAT  is used to represent the magnitude of the voltage on the supply voltage  20 . In addition, the dual output μC charge pump circuit  12 A is further configured to generate a second μC charge Pump output, (V μC     —     OUT2 ) such that V μC     —     OUT2 =(1−XμBB RATIO )×V BAT , where V BAT  is used to represent the magnitude of the voltage on the supply voltage  20   
         [0135]    Accordingly, in the First Buck/Buck Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/4. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT . In the Second Buck/Buck Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/3. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/3×V SAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 2/3×V BAT . In the Third Buck/Buck Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/2. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/2×V SAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/2×V BAT . In the Fourth Buck/Buck Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 2/3. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 2/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/3×V BAT . In the Fifth Buck/Buck Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 3/4. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/4×V BAT . In the OFF Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the first μC charge pump output  24  to float and the second μC charge pump output  26  to float. 
         [0000]    
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 1A 
               
             
             
               
                   
               
               
                 MODES OF OPERATION TABLE FOR BUCK/BUCK OPERATION 
               
               
                 OF A DUAL OUTPUT μC CHARGE PUMP CIRCUIT 
               
             
          
           
               
                   
                   
                 FIRST μC CHARGE PUMP 
                 SECOND μC CHARGE PUMP 
               
               
                 MODES OF 
                 OPERATIONAL RATIOS, 
                 OUTPUT, (V μC     —     OUT1 ), where 
                 OUTPUT, (V μC     —     OUT2 ), where 
               
               
                 OPERATION 
                 (xμBB RATIO ) 
                 V μC     —     OUT1  = (xμBB RATIO ) × V BAT   
                 V μC     —     OUT2  = (1 − xμBB RATIO ) × V BAT   
               
               
                   
               
               
                 First Buck/ 
                 1/4 
                 1/4 × V BAT   
                 3/4 × V BAT   
               
               
                 Buck Mode 
               
               
                 Second Buck/ 
                 1/3 
                 1/3 × V BAT   
                 2/3 × V BAT   
               
               
                 Buck Mode 
               
               
                 Third Buck/ 
                 1/2 
                 1/2 × V BAT   
                 1/2 × V BAT   
               
               
                 Buck Mode 
               
               
                 Fourth Buck/ 
                 2/3 
                 2/3 × V BAT   
                 1/3 × V BAT   
               
               
                 Buck Mode 
               
               
                 Fifth Buck/ 
                 3/4 
                 3/4 × V BAT   
                 1/4 × V BAT   
               
               
                 Buck Mode 
               
               
                 OFF Mode 
                 OFF 
                 FLOATING 
                 FLOATING 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 1B 
               
             
             
               
                   
               
               
                 MODES OF OPERATION TABLE FOR BUCK/BUCK OPERATION 
               
               
                 OF A DUAL OUTPUT μC CHARGE PUMP CIRCUIT 
               
             
          
           
               
                   
                   
                 FIRST μC CHARGE PUMP 
                 SECOND μC CHARGE PUMP 
               
               
                 MODES OF 
                 OPERATIONAL RATIOS, 
                 OUTPUT, (V μC     —     OUT1 ), where 
                 OUTPUT, (V μC     —     OUT2 ), where 
               
               
                 OPERATION 
                 (xμBB RATIO ) 
                 V μC     —     OUT1  = (xμBB RATIO ) × V BAT   
                 V μC     —     OUT2  = (1 − xμBB RATIO ) × V BAT   
               
               
                   
               
               
                 Sixth Buck/ 
                 1/4 
                 3/4 × V BAT   
                 1/4 × V BAT   
               
               
                 Buck Mode 
               
               
                 Seventh Buck/ 
                 1/3 
                 2/3 × V BAT   
                 1/3 × V BAT   
               
               
                 Buck Mode 
               
               
                 Eighth Buck/ 
                 1/2 
                 1/2 × V BAT   
                 1/2 × V BAT   
               
               
                 Buck Mode 
               
               
                 Ninth Buck/ 
                 2/3 
                 1/3 × V BAT   
                 2/3 × V BAT   
               
               
                 Buck Mode 
               
               
                 Tenth Buck/ 
                 3/4 
                 1/4 × V BAT   
                 3/4 × V BAT   
               
               
                 Buck Mode 
               
               
                   
               
             
          
         
       
     
         [0136]    Based on the mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  may configure the multiple output μC charge pump control circuit  72 A to control the switch state (open or closed) of each of the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15), based upon the μC charge pump clock  68 . 
         [0137]    For example, in some embodiments of the dual output μC charge pump circuit  12 A, the multiple output μC charge pump control circuit  72 A may be configured to divide the operation of the dual output μC charge pump circuit  12 A into phases of operation. For example, multiple output μC charge pump control circuit  72 A may be configured to operate in a first phase, a second phase, a third phase, a fourth phase, and so forth. During each phase of operation of the dual output μC charge pump circuit  12 A, the multiple output μC charge pump control circuit  72 A may be configured to change the switch state (open or closed) of the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15), for a period of time. 
         [0138]    In some embodiments of the dual output μC charge pump circuit  12 A, depicted in  FIG. 2A , the multiple output μC charge pump control circuit  72 A may configure the period of time for each phase of operation of the dual output μC charge pump circuit  12 A to be substantially equal. For example, the dual output μC charge pump circuit  12 A may remain in each phase of operation for the same number of clock cycles of the μC charge pump clock  68 . 
         [0139]    In other embodiments of the dual output μC charge pump circuit  12 A, depicted in  FIG. 2A , the multiple output μC charge pump control circuit  72 A may configure the period of time for each phase of operation of the output μC charge pump circuit  12 A to be different to optimize the effeciency of the dual output μC charge pump circuit  12 A when operating in a particular mode of operation. For example, in some modes of operation, the multiple output μC charge pump control circuit  72 A may configure the dual output μC charge pump circuit  12 A to remain in a first phase of operation for a first number of clock cycles of the μC charge pump clock  68  and remain in a second phase of operation for a second number of clock cycles of the μC charge pump clock  68 . The period of time for each phase of operation may be based upon one or more of the various factors including, but not limited to, the size of each of the μC charge pump switches, the current load associated with each of the first μC charge pump output  24  and the second μC charge pump output  26 , the combination of the first μC charge pump output voltage, (V μC     —     OUT1 ), and the second μC charge pump output voltage, (V μC     —     OUT2 ), generated at the respective first μC charge pump output  24  and the second μC charge pump output  26 , the capacitance values of each of the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ), the capacitance values of the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ), and or combinations thereof. 
         [0140]    The maximum switching frequency between the phases of operation may a function of the setting times of the first μC charge pump output voltage, (V μC     —     OUT1 ), and the second μC charge pump output voltage, (V μC     —     OUT2 ), generated at the respective first μC charge pump output  24  and the second μC charge pump output  26 . The settling times may be a function of the series resistance of the μC charge pump switches used to generate each of the first μC charge pump output voltage, (V μC     —     OUT1 ), and the second μC charge pump output voltage, (V μ C   —     OUT2), and the associated capacitance values of the first μC charge pump output capacitor 46, (C   μC     —     OUT1 ), and the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0141]    In addition, to minimize switching noise and interference signals, in some embodiments of the dual output μC charge pump circuit  12 A, the multiple output μC charge pump control circuit  72 A may align the phases of operation of the dual output μC charge pump circuit  12 A such that the μC charge pump circuit switchs (the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15)) are temporally aligned with the switching of other power switches used to generate other power supply voltages used by various portions of an integrated chip that include the multiple output μC charge pump system  10 A. 
         [0142]    Continuing with the description of the various example embodiments of the modes of operation of the dual output μC charge pump circuit  12 A described in TABLE 1A, TABLE 1B-1 and TABLE 1B-2, entitled “SWITCH OPERATION TABLES FOR BUCK/BUCK OPERATION OF DUAL OUTPUT μC CHARGE PUMP,” describe, in tabular form, the switch state (open or closed) of each of the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15), of the dual output μC charge pump circuit  12 A when the dual output μC charge pump circuit  12 A is configured to operate in an identified buck/buck mode of operation. In addition, TABLE 1B-1 and TABLE 1B-2 also provide the corresponding operational ratio, (xμBB RATIO ), of the dual output μC charge pump circuit  12 A, used in the identified buck/buck mode of operation. Also, TABLE 1B-1 and TABLE 1B-2, describe the switch state of each of the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15), relative to a particular phase of operation of the dual output μC charge pump circuit  12 A. 
         [0143]    As used in TABLE 1B-1 and TABLE 1B-2, “PHASE 1” indicates that the dual output μC charge pump circuit  12 A is configured to operate in a first phase of operation, where the multiple output μC charge pump control circuit  72 A configures the switch state (open or closed) of the identified μC charge pump switch to be closed during the time period of the first phase of operation. “PHASE 2” indicates that the dual output μC charge pump circuit  12 A is configured to operate in a second phase of operation, where the multiple output μC charge pump control circuit  72 A configures the switch state (open or closed) of the identified μC charge pump switch to be closed during the time period of the second phase of operation. “PHASE 3” indicates that the dual output μC charge pump circuit  12 A is configured to operate in a third phase of operation, where the multiple output μC charge pump control circuit  72 A configures the switch state (open or closed) of the identified μC charge pump switch to be closed during the time period of the third phase of operation. “PHASE 4” indicates that the dual output μC charge pump circuit  12 A is configured to operate in a fourth phase of operation, where the multiple output μC charge pump control circuit  72 A configures the switch state (open or closed) of the identified μC charge pump switch to be closed during the time period of the fourth phase of operation. “OPEN” indicates that the multiple output μC charge pump control circuit  72 A configures the switch state (open or closed) of the identified switch to be closed during all the phases of operation of the dual output μC charge pump circuit  12 A. 
         [0000]    
       
         
               
             
               
               
             
               
               
               
               
             
           
               
                 TABLE 1B-1 
               
             
             
               
                   
               
               
                 SWITCH OPERATION TABLE FOR BUCK/BUCK MODE 
               
               
                 OF OPERATION OF DUAL OUTPUT μC CHARGE PUMP 
               
             
          
           
               
                   
                 MODES OF OPERATION FOR BUCK/BUCK OPERATION OF DUAL OUTPUT μC 
               
               
                   
                 CHARGE PUMP WITH CORRESPONDING OPERATIONAL RATIOS, (xμBB RATIO ) 
               
             
          
           
               
                 See, 
                 First Buck/Buck Mode, 
                 Second Buck/Buck Mode, 
                 Third Buck/Buck Mode, 
               
               
                 TABLE 1A 
                 (xμBB RATIO  = 1/4), where 
                 (xμBB RATIO  = 1/3), where 
                 (xμBB RATIO  = 1/2), where 
               
               
                 μC CHARGE PUMP 
                 V μC     —     OUT1  = 1/4 × V BAT  and 
                 V μC     —     OUT1  = 1/3 × V BAT , and 
                 V μC     —     OUT1  = 1/2 × V BAT , and 
               
               
                 SWITCHES 
                 V μC     —     OUT2  = 3/4 × V BAT   
                 V μC     —     OUT2  = 2/3 × V BAT   
                 V μC     —     OUT2  = 1/2 × V BAT   
               
               
                   
               
               
                 SW 1 
                 Phase 1 
                 Phase 1 and Phase 3 
                 Phase 1 and Phase 3 
               
               
                 SW 2 
                 OPEN 
                 Phase 2 
                 Phase 2 
               
               
                 SW 3 
                 Phase 3 
                 Phase 2 
                 Phase 2 
               
               
                 SW 4 
                 OPEN 
                 OPEN 
                 Phase 1 
               
               
                 SW 5 
                 Phase 1 
                 Phase 1 
                 OPEN 
               
               
                 SW 6 
                 OPEN 
                 Phase 3 
                 Phase 1 
               
               
                 SW 7 
                 Phase 2 
                 Phase 2 
                 Phase 2 
               
               
                 SW 8 
                 Phase 2 
                 Phase 2 
                 Phase 2 
               
               
                 SW 9 
                 Phase 1 and Phase 3 
                 Phase 1 
                 Phase 1 
               
               
                 SW 10 
                 Phase 3 and Phase 4 
                 OPEN 
                 Phase 3 
               
               
                 SW 11 
                 Phase 4 
                 OPEN 
                 OPEN 
               
               
                 SW 12 
                 OPEN 
                 Phase 3 
                 Phase 3 
               
               
                 SW 13 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 14 
                 Phase 4 
                 Phase 3 
                 Phase 3 
               
               
                 SW 15 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
             
               
               
               
               
             
           
               
                 TABLE 1B-2 
               
             
             
               
                   
               
               
                 SWITCH OPERATION TABLE FOR BUCK/BUCK MODE 
               
               
                 OF OPERATION OF DUAL OUTPUT μC CHARGE PUMP 
               
             
          
           
               
                   
                 MODES OF OPERATION FOR BUCK/BUCK OPERATION OF DUAL OUTPUT μC 
               
               
                   
                 CHARGE PUMP WITH CORRESPONDING OPERATIONAL RATIOS, (xμBB RATIO ) 
               
             
          
           
               
                 See, 
                 Fourth Buck/Buck Mode, 
                 Fifth Buck/Buck Mode, 
                 OFF Mode 
               
               
                 TABLE 1A 
                 (xμBB RATIO  = 2/3), where 
                 (xμBB RATIO  = 3/4), where 
                 where 
               
               
                 μC CHARGE PUMP 
                 V μC     —     OUT1  = 2/3 × V BAT , and 
                 V μC     —     OUT1  = 3/4 × V BAT , and 
                 V μC     —     OUT1  = FLOAT 
               
               
                 SWITCHES 
                 V μC     —     OUT2  = 1/3 × V BAT   
                 V μC     —     OUT2  = 1/4 × V BAT   
                 V μC     —     OUT2  = FLOAT 
               
               
                   
               
               
                 SW 1 
                 Phase 1 and Phase 3 
                 Phase 4 
                 OPEN 
               
               
                 SW 2 
                 Phase 2 
                 Phase 3 
                 OPEN 
               
               
                 SW 3 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 4 
                 Phase 1 
                 Phase 1 
                 OPEN 
               
               
                 SW 5 
                 Phase 2 and Phase 3 
                 Phase 3 and Phase 4 
                 OPEN 
               
               
                 SW 6 
                 Phase 1 
                 Phase 2 
                 OPEN 
               
               
                 SW 7 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 8 
                 Phase 2 
                 Phase 3 
                 OPEN 
               
               
                 SW 9 
                 Phase 1 
                 Phase 2 
                 OPEN 
               
               
                 SW 10 
                 OPEN 
                 Phase 1 
                 OPEN 
               
               
                 SW 11 
                 OPEN 
                 Phase 1 
                 OPEN 
               
               
                 SW 12 
                 Phase 3 
                 Phase 4 
                 OPEN 
               
               
                 SW 13 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 14 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 15 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                   
               
             
          
         
       
     
         [0144]    TABLE 1B-1 describes, and  FIGS. 3A-B  depict, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the First (1 st ) Buck/Buck Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/4. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into four phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT . 
         [0145]    In the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fifth switch  82 , (SW 5), and the ninth switch  90 , (SW 9), to place the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ), in series between the supply voltage  20  and the first μC charge pump output  24 . Charge is transferred from the supply voltage  20 , (V BAT ), to the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), via the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ). The first flying capacitor voltage, (V CAP     —     FLY1 ), and the second flying capacitor voltage, (V CAP     —     FLY2 ), are subtracted from the supply voltage  20 , (V BAT ), to provide a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/4×V BAT , on the first μC charge pump output  24 . Also, during the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A configures the remaining μC charge pump switches to be open, which disconnects the second μC charge pump output  26  from the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ). In this case, the second μC charge pump output  26  provides a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT , from the charge already stored on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0146]    In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the seventh switch  86 , (SW 7), and the eighth switch  88 , (SW 8), to place the second flying capacitor  44 , (C FLY2 ), between the first μC charge pump output  24  and ground. The charge stored on the second flying capacitor  44 , (C FLY2 ), and first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), is sourced to the first μC charge pump output  24  to provide the first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/4×V BAT . Similar to the first phase of operation, (Phase 1), the second μC charge pump output  26  continues to provide the second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT , from the charge already stored on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0147]    In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the third switch  78 , (SW 3), the ninth switch  90 , (SW 9), and the tenth switch  92 , (SW 10). As a result, the second terminal  42 B of the first flying capacitor  42 , (C FLY1 ), is tied to ground, the first terminal  42 A of the first flying capacitor  42 , (C FLY1 ), is coupled to the first terminal  44 A of the second flying capacitor  44 , (C FLY2 ), and the second terminal  44 B of the second flying capacitor  44 , (C FLY2 ), is coupled to the first μC charge pump output  24 . 
         [0148]    Accordingly, charge stored on the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ), is sourced to the first μC charge pump output  24  to maintain the first μC charge pump output voltage, (V μC     —     OUT1 ), at a voltage level substantially equal to 1/4×V BAT . The first μC charge pump output voltage, (V μC     —     OUT1 ), remains substantially equal to 1/4×V BAT , where the magnitude of the first μC charge pump output voltage, (V μC     —     OUT1 ), is determined by subtracting the second flying capacitor voltage, (V CAP     —     FLY2 ), from the first flying capacitor voltage, (V CAP     —     FLY1 ). Similar to the first phase of operation, (Phase 1), and the second phase of operation, (Phase 2), the second μC charge pump output  26  continues to provide the second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT , from the charge previously stored on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0149]    In the fourth phase of operation, (Phase 4), the multiple output μC charge pump control circuit  72 A operably closes the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), and the fourteenth switch  100 , (SW 14). During the fourth phase of operation, (Phase 4), charge is transferred from the supply voltage  20 , (V BAT ), to the second μC charge pump output capacitor  48 , (C μC -   —     OUT2 ), via the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ). The magnitude of the second μC charge pump output voltage, (V μC     —     OUT2 ), is determined by subtracting the second flying capacitor voltage, (V CAP     —     FLY2 ), from the first flying capacitor voltage, (V CAP     —     FLY1 ), and the supply voltage  20 , (V BAT ). Accordingly, the second μC charge pump output  26  provides a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT . During the fourth phase of operation, (Phase 4), the multiple output μC charge pump control circuit  72 A configures the remaining μC charge pump switches to be open, which disconnects the first μC charge pump output  24  from the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ). As a result, the first μC charge pump output  24  provides the first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/4×V BAT , from the charge stored on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), during the other phases of operation. 
         [0150]    Otherwise, the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15), remain open while the dual output μC charge pump circuit  12 A is configured to operate in the First (1 st ) Buck/Buck Mode. 
         [0151]    Having described the basic operation of the multiple output μC charge pump control circuit  72 A and the phases of operation of the dual output μC charge pump circuit  12 A in detail with respect to the case where the dual output μC charge pump circuit  12 A is configured to operate in the First (1st) Buck/Buck Mode, the remaining modes of operation of the dual output μC charge pump circuit  12 A will now be briefly described. 
         [0152]    TABLE 1B-1 describes, and  FIG. 4  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Second (2 nd ) Buck/Buck Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/3. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into three phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 2/3×V BAT . 
         [0153]    As described in TABLE 1B-1 and depicted in  FIG. 4 , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fifth switch  82 , (SW 5), and the ninth switch  90 , (SW 9). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the third switch  78 , (SW 3), the seventh switch  86 , (SW 7), and the eighth switch  88 , (SW 8). In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the sixth switch  84 , (SW 6), the twelfth switch  96 , (SW 12), and the fourteenth switch  100 , (SW 14). Otherwise, the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15), remain closed while the dual output μC charge pump circuit  12 A is configured to operate in the Second (2 nd ) Buck/Buck Mode. 
         [0154]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/3×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/3×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 2/3×V BAT . 
         [0155]    TABLE 1B-1 describes, and  FIG. 5  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Third (3 rd ) Buck/Buck Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/2. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into three phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/2×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/2×V BAT . 
         [0156]    As described in TABLE 1B-1 and depicted in  FIG. 5 , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fourth switch  80 , (SW 4), the sixth switch  84 , (SW 6), and the ninth switch  90 , (SW 9). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the third switch  78 , (SW 3), the seventh switch  86 , (SW 7), and the eighth switch  88 , (SW 8). In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), tenth switch  92 , (SW 10), the twelfth switch  96 , (SW 12), and the fourteenth switch  100 , (SW 14). As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/2×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/2×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/2×V BAT , on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/2×V BAT  on the second μC charge pump output capacitor  48 , (C μ C   —     OUT2 ). 
         [0157]    TABLE 1B-2 describes, and  FIG. 6  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Fourth (4 th ) Buck/Buck Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 2/3. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into three phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 2/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/3×V BAT . 
         [0158]    As described in TABLE 1B-2 and depicted in  FIG. 6 , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fourth switch  80 , (SW 4), the sixth switch  84 , (SW 6), and the ninth switch  90 , (SW 9). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the fifth switch  82 , (SW 5), and the eighth switch  88 , (SW 8). In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fifth switch  82 , (SW 5), and the twelfth switch  96 , (SW 12). 
         [0159]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/3×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/3×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 2/3×V BAT , on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/3×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0160]    TABLE 1B-2 describes, and  FIGS. 7A-B  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Fifth (5 th ) Buck/Buck Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 3/4. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into four phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/4×V BAT . 
         [0161]    As described in TABLE 1B-2 and depicted in  FIG. 7A , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the fourth switch  80 , (SW 4), the tenth switch  92 , (SW 10), and the eleventh switch  94 , (SW 11). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the sixth switch  84 , (SW 6), and the ninth switch  90 , (SW 9). As further described in TABLE 1B-2 and depicted in  FIG. 7B , in the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the fifth switch  82 , (SW 5), and the eighth switch  88 , (SW 8). In the fourth phase of operation, (Phase 4), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fifth switch  82 , (SW 5), and the twelfth switch  96 , (SW 12). 
         [0162]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 3/4×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/4×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/4×V BAT , on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/4×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0163]    As further described in TABLE 1B-2, the controller  14  may also configure the dual output μC charge pump circuit  12 A to operate in the OFF Mode of operation. As described in Table 1A, when the dual output μC charge pump circuit  12 A is configured in the OFF Mode of operation, both the first μC charge pump output  24  and second μC charge pump output  26  float. As described in TABLE 1B-2, when the controller  14  configures the dual output μC charge pump circuit  12 A to be in the OFF Mode of operation, the multiple output μC charge pump control circuit  72 A may operablely open the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15). As a result, the first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  floats relative to ground. Likewise, the second μC charge pump output voltage, (V μC     —     OUT2 ), on the second μC charge pump output  26  floats relative to ground. It will be appreciated, by those skilled in the art, that the configurations and phases of operation of the dual output μC charge pump circuit  12 A to achive the additional buck/buck modes of operation, as described in TABLE 1B, including the Sixth (6 th ) Buck/Buck Mode, the Seventh (7 th ) Buck/Buck Mode, the Eighth (8 th ) Buck/Buck Mode, the Ninth (9 th ) Buck/Buck Mode, and the Tenth (10 th ) Buck/Buck Mode, may be understood based on the foregoing description of the operation of the dual output μC charge pump circuit  12 A to operate in either a buck/boost mode of operation or a boost/buck mode of operation, as described below. Accordingly, a detailed description of the configurations and phases of operation of the dual output μC charge pump circuit  12 A to achive the additional buck/buck modes of operation, as described in TABLE 1B, are omitted for the sake of brevity and not by way of limitation. 
         [0164]    A non-limiting set of example operational modes of the dual output μC charge pump circuit  12 A configured to operate in a buck/boost mode of operation will now be discussed. As an example, TABLE 2A-1 and TABLE 2A-2, entitled “MODES OF OPERATION TABLE FOR BUCK/BOOST OPERATION OF A DUAL OUTPUT μC CHARGE PUMP CIRCUIT,” describe, in tablulated form, several, non-limiting, example modes of operation of the dual output μC charge pump circuit  12 A configured to operate in a buck/boost mode of operation. As an example, the non-limiting example modes of buck/boost modes of operation described in TABLE 2A-1 include: a First (1 st ) Buck/Boost Mode, a Second (2 nd ) Buck/Boost Mode, a Third (3 rd ) Buck/Boost Mode, a Fourth (4 th ) Buck/Boost Mode, a Fifth (5 th ) Buck/Boost Mode, and an OFF Mode. As another example, the non-limiting example modes of buck/boost modes of operation described in TABLE 2A-2 include: a Sixth (6 th ) Buck/Boost Mode, a Seventh (7 th ) Buck/Boost Mode, an Eighth (8 th ) Buck/Boost Mode, a Ninth (9 th ) Buck/Boost Mode, a Tenth (10 th ) Buck/Boost Mode, and an OFF Mode. 
         [0165]    As depicted in TABLE 2A-1 and TABLE 2A-2, each example buck/boost mode of operation of the dual output μC charge pump circuit  12 A corresponds to an operational ratio, (xμBB RATIO ), where the operational ratio, (xμBB RATIO ), may provide a relationship between the first μC charge pump output voltage, (V μC     —     OUT1 ), generated by the first μC charge pump output  24  and the second μC charge pump output voltage, (V μC     —     OUT2 ), generated by the second μC charge pump output  26 . The operational ratio, (xμBB RATIO ), may be an operational ratio parameter that is configured by the controller  14  and stored locally in the multiple output μC charge pump control circuit  72 A. 
         [0166]    For example, TABLE 2A-1 describes example buck/boost modes of operation of the dual output μC charge pump circuit  12 A where the first μC charge pump output  24  is configured to generate a first μC charge pump output voltage, (V μC     —     OUT1 ) such that V μC     —     OUT1 =(xμBB RATIO )×V BAT . For the sake of convenience, and without limitation, the battery voltage, (V BAT ), is used to represent the magnitude of the voltage on the supply voltage  20 . The second μC charge pump output  26  is configured to generate a second μC charge pump output voltage, (V μC     —     OUT2 ) such that V μC     —     OUT2 =(1+xμBB RATIO )×V BAT , where V BAT  is used to represent the magnitude of the voltage on the supply voltage  20 . 
         [0167]    Accordingly, as described in TABLE 2A-1, in the First Buck/Boost Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/4. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/4×V BAT . In the Second Buck/Boost Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/3. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 4/3×V BAT . In the Third Buck/Boost Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/2. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/2×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/2×V BAT . In the Fourth Buck/Boost Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 2/3. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 2/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/3×V BAT . In the Fifth Buck/Boost Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 3/4. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/4×V BAT ) and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 7/4×V BAT . In the OFF Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the first μC charge pump output  24  to float and the second μC charge pump output  26  to float. 
         [0168]    In contrast, TABLE 2A-2 describes other example buck/boost modes of operation of the dual output μC charge pump circuit  12 A where the first μC charge pump output  24  is configured to generate a first μC charge pump output voltage, (V μC     —     OUT1 ) such that V μC     —     OUT1 =(1−xμBB RATIO )×V BAT . For the sake of convenience, and without limitation, the battery voltage, (V BAT ), is used to represent the magnitude of the voltage on the supply voltage  20 . The second μC charge pump output  26  is configured generates a second μC charge pump output voltage, (V μC     —     OUT2 ) such that V μC     —     OUT2 =(1+xμBB RATIO )×V BAT , where V BAT  is used to represent the magnitude of the voltage on the supply voltage  20 . 
         [0169]    Accordingly, as described in TABLE 2A-2, in the Sixth Buck/Boost Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/4. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/4×V BAT . In the Seventh Buck/Boost Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/3. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 2/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 4/3×V BAT . In the Eighth Buck/Boost Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/2. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/2×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/2×V BAT . In the Ninth Buck/Boost Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 2/3. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/3×V BAT . In the Tenth Buck/Boost Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 3/4. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 7/4×V BAT . In the OFF Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the first μC charge pump output  24  to float and the second μC charge pump output  26  to float. 
         [0170]    TABLE 2B-1A and TABLE 2B-1B, entitled “SWITCH OPERATION TABLES FOR BUCK/BOOST OPERATION OF DUAL OUTPUT μC CHARGE PUMP,” describe, in tabular form, the switch state (open or closed) of each of the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15), of the dual output μC charge pump circuit  12 A when the dual output μC charge pump circuit  12 A is configured to operate in the buck/boost modes of operation described in TABLE 2A-1. In addition, TABLE 2B-1A and TABLE 2B-1B also provide the corresponding operational ratio, (xμBB RATIO ), used by the dual output μC charge pump circuit  12 A when operating in the buck/boost modes of operation described in TABLE 2A-1. TABLE 2B-1A and TABLE 2B-1B further describe the switch state of each of the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15), relative to the particular phases of operation used by the dual output μC charge pump circuit  12 A when operating in the buck/boost modes of operation described in TABLE 2A-1. 
         [0171]    TABLE 2B-2A and TABLE 2B-2B, also entitled “SWITCH OPERATION TABLES FOR BUCK/BOOST OPERATION OF DUAL OUTPUT μC CHARGE PUMP,” describe, in tabular form, the switch state (open or closed) of each of the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15), of the dual output μC charge pump circuit  12 A when the dual output μC charge pump circuit  12 A is configured to operate in the buck/boost modes of operation described in TABLE 2A-2. In addition, TABLE 2B-2A and TABLE 2B-2B also provide the corresponding operational ratio, (xμBB RATIO ), used by the dual output μC charge pump circuit  12 A when operating in the buck/boost modes of operation described in TABLE 2A-2. TABLE 2B-2A and TABLE 2B-2B further describe the switch state of each of the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15), relative to the particular phases of operation used by the dual output μC charge pump circuit  12 A when operating in the buck/boost modes of operation described in TABLE 2A-2. 
         [0172]    As used in TABLE 2B-1A, TABLE 2B-1B, TABLE 2B-2A, and TABLE 2B-2A, “PHASE 1” indicates that the dual output μC charge pump circuit  12 A is configured to operate in a first phase of operation, where the multiple output μC charge pump control circuit  72 A configures the switch state (open or closed) of the identified μC charge pump switch to be closed during the time period of the first phase of operation. “PHASE 2” indicates that the dual output μC charge pump circuit  12 A is configured to operate in a second phase of operation, where the multiple output μC charge pump control circuit  72 A configures the switch state (open or closed) of the identified μC charge pump switch to be closed during the time period of the second phase of operation. “PHASE 3” indicates that the dual output μC charge pump circuit  12 A is configured to operate in a third phase of operation, where the multiple output μC charge pump control circuit  72 A configures the switch state (open or closed) of the identified μC charge pump switch to be closed during the time period of the third phase of operation. “PHASE 4” indicates that the dual output μC charge pump circuit  12 A is configured to operate in a fourth phase of operation, where the multiple output μC charge pump control circuit  72 A configures the switch state (open or closed) of the identified μC charge pump switch to be closed during the time period of the fourth phase of operation. “OPEN” indicates that the multiple output μC charge pump control circuit  72 A configures the switch state (open or closed) of the identified switch to be closed during all the phases of operation of the dual output μC charge pump circuit  12 A. 
         [0000]    
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 2A-1 
               
             
             
               
                   
               
               
                 MODES OF OPERATION TABLE FOR BUCK/BOOST OPERATION 
               
               
                 OF A DUAL OUTPUT μC CHARGE PUMP CIRCUIT 
               
             
          
           
               
                   
                   
                 FIRST μC CHARGE PUMP 
                 SECOND μC CHARGE PUMP 
               
               
                 MODES OF 
                 OPERATIONAL RATIOS, 
                 OUTPUT, (V μC     —     OUT1 ), where 
                 OUTPUT, (V μC     —     OUT2 ), where 
               
               
                 OPERATION 
                 (xμBB RATIO ) 
                 V μC     —     OUT1  = (xμBB RATIO ) × V BAT   
                 V μC     —     OUT2  = (1 + xμBB RATIO ) × V BAT   
               
               
                   
               
               
                 First Buck/ 
                 1/4 
                 1/4 × V BAT   
                 5/4 × V BAT   
               
               
                 Boost Mode 
               
               
                 Second Buck/ 
                 1/3 
                 1/3 × V BAT   
                 4/3 × V BAT   
               
               
                 Boost Mode 
               
               
                 Third Buck/ 
                 1/2 
                 1/2 × V BAT   
                 3/2 × V BAT   
               
               
                 Boost Mode 
               
               
                 Fourth Buck/ 
                 2/3 
                 2/3 × V BAT   
                 5/3 × V BAT   
               
               
                 Boost Mode 
               
               
                 Fifth Buck/ 
                 3/4 
                 3/4 × V BAT   
                 7/4 × V BAT   
               
               
                 Boost Mode 
               
               
                 OFF Mode 
                 OFF 
                 FLOATING 
                 FLOATING 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 2A-2 
               
             
             
               
                   
               
               
                 MODES OF OPERATION TABLE FOR BUCK/BOOST OPERATION OF A DUAL OUTPUT μC CHARGE PUMP 
               
               
                 CIRCUIT 
               
             
          
           
               
                   
                   
                 FIRST μC CHARGE PUMP 
                 SECOND μC CHARGE PUMP 
               
               
                 MODES OF 
                 OPERATIONAL RATIOS, 
                 OUTPUT, (V μC _OUT1), where 
                 OUTPUT, (V μC _OUT2), where 
               
               
                 OPERATION 
                 (xμBB RATIO ) 
                 V μC _OUT1 = (1 − xμBB RATIO ) × V BAT   
                 V μC _OUT2 = (1 + xμBB RATIO ) × V BAT   
               
               
                   
               
               
                 Sixth Buck/Boost 
                 1/4 
                 3/4 × V BAT   
                 5/4 × V BAT   
               
               
                 Mode 
                   
                   
                   
               
               
                 Seventh Buck/ 
                 1/3 
                 2/3 × V BAT   
                 4/3 × V BAT   
               
               
                 Boost Mode 
                   
                   
                   
               
               
                 Eigth Buck/Boost 
                 1/2 
                 1/2 × V BAT   
                 3/2 × V BAT   
               
               
                 Mode 
                   
                   
                   
               
               
                 Ninth Buck/Boost 
                 2/3 
                 1/3 × V BAT   
                 5/3 × V BAT   
               
               
                 Mode 
                   
                   
                   
               
               
                 Tenth Buck/Boost 
                 3/4 
                 1/4 × V BAT   
                 7/4 × V BAT   
               
               
                 Mode 
                   
                   
                   
               
               
                 OFF Mode 
                 OFF 
                 FLOATING 
                 FLOATING 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
             
               
               
               
               
             
           
               
                 TABLE 2B-1A 
               
             
             
               
                   
               
               
                 SWITCH OPERATION TABLE FOR BUCK/BOOST MODE 
               
               
                 OF OPERATION OF DUAL OUTPUT μC CHARGE PUMP 
               
             
          
           
               
                   
                 MODES OF OPERATION FOR BUCK/BOOST OPERATION OF DUAL OUTPUT μC 
               
               
                   
                 CHARGE PUMP WITH CORRESPONDING OPERATIONAL RATIOS, (xμBB RATIO ) 
               
             
          
           
               
                 See, 
                 First Buck/Boost Mode, 
                 Second Buck/Boost Mode, 
                 Third Buck/Boost Mode, 
               
               
                 TABLE 2A-1 
                 (xμBB RATIO  = 1/4), where 
                 (xμBB RATIO  = 1/3), where 
                 (xμBB RATIO  = 1/2), where 
               
               
                 μC CHARGE PUMP 
                 V μC     —     OUT1  = 1/4 × V BAT  and 
                 V μC     —     OUT1  = 1/3 × V BAT , and 
                 V μC     —     OUT1  = 1/2 × V BAT , and 
               
               
                 SWITCHES 
                 V μC     —     OUT2  = 5/4 × V BAT   
                 V μC     —     OUT2  = 4/3 × V BAT   
                 V μC     —     OUT2  = 3/2 × V BAT   
               
               
                   
               
               
                 SW 1 
                 Phase 1 
                 Phase 1 
                 Phase 1 
               
               
                 SW 2 
                 OPEN 
                 Phase 2 
                 Phase 2 
               
               
                 SW 3 
                 Phase 3 
                 Phase 2 
                 Phase 2 
               
               
                 SW 4 
                 OPEN 
                 OPEN 
                 Phase 1 
               
               
                 SW 5 
                 Phase 1 
                 Phase 1 
                 OPEN 
               
               
                 SW 6 
                 OPEN 
                 OPEN 
                 Phase 1 
               
               
                 SW 7 
                 Phase 2 
                 Phase 2 
                 Phase 2 
               
               
                 SW 8 
                 Phase 2 
                 Phase 2 
                 Phase 2 
               
               
                 SW 9 
                 Phase 1 and Phase 3 
                 Phase 1 
                 Phase 1 
               
               
                 SW 10 
                 Phase 3 and Phase 4 
                 Phase 3 
                 Phase 3 
               
               
                 SW 11 
                 OPEN 
                 Phase 3 
                 Phase 3 
               
               
                 SW 12 
                 Phase 4 
                 OPEN 
                 OPEN 
               
               
                 SW 13 
                 OPEN 
                 Phase 3 
                 Phase 3 
               
               
                 SW 14 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 15 
                 Phase 4 
                 Phase 3 
                 Phase 3 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
             
               
               
               
               
             
           
               
                 TABLE 2B-1B 
               
             
             
               
                   
               
               
                 SWITCH OPERATION TABLE FOR BUCK/BOOST MODE 
               
               
                 OF OPERATION OF DUAL OUTPUT μC CHARGE PUMP 
               
             
          
           
               
                   
                 MODES OF OPERATION FOR BUCK/BOOST OPERATION OF DUAL OUTPUT μC 
               
               
                   
                 CHARGE PUMP WITH CORRESPONDING OPERATIONAL RATIOS, (xμBB RATIO ) 
               
             
          
           
               
                 See, 
                 Fourth Buck/Boost Mode, 
                 Fifth Buck/Boost Mode, 
                 OFF Mode 
               
               
                 TABLE 2A-1 
                 (xμBB RATIO  = 2/3), where 
                 (xμBB RATIO  = 3/4), where 
                 where 
               
               
                 μC CHARGE PUMP 
                 V μC     —     OUT1  = 2/3 × V BAT  and 
                 V μC     —     OUT1  = 3/4 × V BAT , and 
                 V μC     —     OUT1  = FLOAT 
               
               
                 SWITCHES 
                 V μC     —     OUT2  = 5/3 × V BAT   
                 V μC     —     OUT2  = 7/4 × V BAT   
                 V μC     —     OUT2  = FLOAT 
               
               
                   
               
               
                 SW 1 
                 Phase 1 
                 OPEN 
                 OPEN 
               
               
                 SW 2 
                 Phase 2 
                 Phase 3 
                 OPEN 
               
               
                 SW 3 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 4 
                 Phase 1 
                 Phase 1 
                 OPEN 
               
               
                 SW 5 
                 Phase 2 and Phase 3 
                 Phase 3 and Phase 4 
                 OPEN 
               
               
                 SW 6 
                 Phase 1 
                 Phase 2 
                 OPEN 
               
               
                 SW 7 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 8 
                 Phase 2 
                 Phase 3 
                 OPEN 
               
               
                 SW 9 
                 Phase 1 
                 Phase 2 
                 OPEN 
               
               
                 SW 10 
                 Phase 3 
                 Phase 1 and Phase 4 
                 OPEN 
               
               
                 SW 11 
                 Phase 3 
                 Phase 1 and Phase 4 
                 OPEN 
               
               
                 SW 12 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 13 
                 Phase 3 
                 Phase 4 
                 OPEN 
               
               
                 SW 14 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 15 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
             
               
               
               
               
             
           
               
                 TABLE 2B-2A 
               
             
             
               
                   
               
               
                 SWITCH OPERATION TABLE FOR BUCK/BOOST MODE 
               
               
                 OF OPERATION OF DUAL OUTPUT μC CHARGE PUMP 
               
             
          
           
               
                   
                 MODES OF OPERATION FOR BUCK/BOOST OPERATION OF DUAL OUTPUT μC 
               
               
                   
                 CHARGE PUMP WITH CORRESPONDING OPERATIONAL RATIOS, (xμBB RATIO ) 
               
             
          
           
               
                 See, 
                 Sixth Buck/Boost Mode, 
                 Seventh Buck/Boost Mode, 
                 Eighth Buck/Boost Mode, 
               
               
                 TABLE 2A-2 
                 (xμBB RATIO  = 1/4), where 
                 (xμBB RATIO  = 1/3), where 
                 (xμBB RATIO  = 1/2), where 
               
               
                 μC CHARGE PUMP 
                 V μC     —     OUT1  = 3/4 × V BAT  and 
                 V μC     —     OUT1  = 2/3 × V BAT , and 
                 V μC     —     OUT1  = 1/2 × V BAT , and 
               
               
                 SWITCHES 
                 V μC     —     OUT2  = 5/4 × V BAT   
                 V μC     —     OUT2  = 4/3 × V BAT   
                 V μC     —     OUT2  = 3/2 × V BAT   
               
               
                   
               
               
                 SW 1 
                 OPEN 
                 Phase 1 
                 Phase 1 
               
               
                 SW 2 
                 Phase 3 
                 Phase 2 
                 Phase 2 
               
               
                 SW 3 
                 OPEN 
                 OPEN 
                 Phase 2 
               
               
                 SW 4 
                 Phase 1 
                 Phase 1 
                 Phase 1 
               
               
                 SW 5 
                 Phase 3 
                 Phase 2 
                 OPEN 
               
               
                 SW 6 
                 Phase 2 
                 Phase 1 
                 Phase 1 
               
               
                 SW 7 
                 OPEN 
                 OPEN 
                 Phase 2 
               
               
                 SW 8 
                 Phase 3 
                 Phase 2 
                 Phase 2 
               
               
                 SW 9 
                 Phase 2 
                 Phase 1 
                 Phase 1 
               
               
                 SW 10 
                 Phase 1 and Phase 4 
                 Phase 3 
                 Phase 3 
               
               
                 SW 11 
                 Phase 1 
                 Phase 3 
                 Phase 3 
               
               
                 SW 12 
                 Phase 4 
                 OPEN 
                 OPEN 
               
               
                 SW 13 
                 OPEN 
                 Phase 3 
                 Phase 3 
               
               
                 SW 14 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 15 
                 Phase 4 
                 Phase 3 
                 Phase 3 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
             
               
               
               
               
             
           
               
                 TABLE 2B-2B 
               
             
             
               
                   
               
               
                 SWITCH OPERATION TABLE FOR BUCK/BOOST MODE 
               
               
                 OF OPERATION OF DUAL OUTPUT μC CHARGE PUMP 
               
             
          
           
               
                   
                 MODES OF OPERATION FOR BUCK/BOOST OPERATION OF DUAL OUTPUT μC 
               
               
                   
                 CHARGE PUMP WITH CORRESPONDING OPERATIONAL RATIOS, (xμBB RATIO ) 
               
             
          
           
               
                 See, 
                 Ninth Buck/Boost Mode, 
                 Tenth Buck/Boost Mode, 
                 OFF Mode 
               
               
                 TABLE 2A-2 
                 (xμBB RATIO  = 2/3), where 
                 (xμBB RATIO  = 3/4), where 
                 where 
               
               
                 μC CHARGE PUMP 
                 V μC     —     OUT1  = 1/3 × V BAT  and 
                 V μC     —     OUT1  = 1/4 × V BAT , and 
                 V μC     —     OUT1  = FLOAT 
               
               
                 SWITCHES 
                 V μC     —     OUT2  = 5/3 × V BAT   
                 V μC     —     OUT2  = 7/4 × V BAT   
                 V μC     —     OUT2  = FLOAT 
               
               
                   
               
               
                 SW 1 
                 Phase 1 
                 Phase 1 
                 OPEN 
               
               
                 SW 2 
                 Phase 2 
                 OPEN 
                 OPEN 
               
               
                 SW 3 
                 Phase 2 
                 Phase 3 
                 OPEN 
               
               
                 SW 4 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 5 
                 Phase 1 and Phase 3 
                 Phase 1 and Phase 4 
                 OPEN 
               
               
                 SW 6 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 7 
                 Phase 2 
                 Phase 2 
                 OPEN 
               
               
                 SW 8 
                 Phase 2 
                 Phase 2 
                 OPEN 
               
               
                 SW 9 
                 Phase 1 
                 Phase 1 and Phase 3 
                 OPEN 
               
               
                 SW 10 
                 Phase 3 
                 Phase 3 and Phase 4 
                 OPEN 
               
               
                 SW 11 
                 Phase 3 
                 Phase 4 
                 OPEN 
               
               
                 SW 12 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 13 
                 Phase 3 
                 Phase 4 
                 OPEN 
               
               
                 SW 14 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 15 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                   
               
             
          
         
       
     
         [0173]    The configurations and operations of the dual output μC charge pump circuit  12 A when the dual output μC charge pump circuit  12 A operates in the various buck/boost modes, described in the TABLE 2A-1 and the TABLE 2A-2, will now be discussed with reference to the TABLE 2B-1A, the TABLE 2B-1B, the TABLE 2B-2A, and the TABLE 2B-2B. 
         [0174]    TABLE 2B-1A describes, and  FIGS. 8A-B  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the First Buck/Boost Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμB BRATIO ), set to 1/4. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into four phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/4×V SAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/4×V BAT . 
         [0175]    As described in TABLE 2B-1A and depicted in  FIG. 8A , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fifth switch  82 , (SW 5), and the ninth switch  90 , (SW 9). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the seventh switch  86 , (SW 7), and the eighth switch  88 , (SW 8). As further depicted in  FIG. 8B , in the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the third switch  78 , (SW 3), the ninth switch  90 , (SW 9), and the tenth switch  92 , (SW 10). In the fourth phase of operation, (Phase 4), the multiple output μC charge pump control circuit  72 A operably closes the tenth switch  92 , (SW 10), the twelfth switch  96 , (SW 12), and the fifteenth switch  102 , (SW 15). 
         [0176]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/2×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/4×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/4×V BAT , on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/4×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0177]    TABLE 2B-1A describes, and  FIG. 9  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Second Buck/Boost Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/3. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into three phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 4/3×V BAT . 
         [0178]    As described in TABLE 2B-1A and depicted in  FIG. 9 , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fifth switch  82 , (SW 5), and the ninth switch  90 , (SW 9). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the third switch  78 , (SW 3), the seventh switch  86 , (SW 7), and the eighth switch  88 , (SW 8). In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the thirteenth switch  98 , (SW 13), and the fifteenth switch  102 , (SW 15). 
         [0179]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/3×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/3×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/3×V BAT , on the first μC charge pump output capacitor  46 , (C μ C   —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 4/3×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0180]    TABLE 2B-1A describes, and  FIG. 10  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Third Buck/Boost Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/2. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into three phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/2×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/2×V BAT . 
         [0181]    As further described in TABLE 2B-1A and depicted in  FIG. 10 , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), and the ninth switch  90 , (SW 9). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the third switch  78 , (SW 3), the seventh switch  86 , (SW 7), and the eighth switch  88 , (SW 8). In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the thirteenth switch  98 , (SW 13), and the fifteenth switch  102 , (SW 15). 
         [0182]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/2×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/2×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/2×V BAT , on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/2×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0183]    TABLE 2B-1B describes, and  FIG. 11  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Fourth Buck/Boost Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 2/3. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into three phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 2/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/3×V BAT . 
         [0184]    As further described in TABLE 2B-1B and depicted in  FIG. 11 , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fourth switch  80 , (SW 4), the sixth switch  84 , (SW 6), and the ninth switch  90 , (SW 9). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the fifth switch  82 , (SW 5), and the eighth switch  88 , (SW 8). In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the fifth switch  82 , (SW 5), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), and the thirteenth switch  98 , (SW 13). 
         [0185]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/3×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/3×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 2/3×V BAT , on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/3×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0186]    TABLE 2B-1B describes, and  FIGS. 12A-B  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Fifth Buck/Boost Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 3/4. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into four phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 7/4×V BAT . 
         [0187]    As further described in TABLE 2B-1B and depicted in  FIG. 12A , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the fourth switch  80 , (SW 4), the tenth switch  92 , (SW 10), and the eleventh switch  94 , (SW 11). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the sixth switch  84 , (SW 6), and the ninth switch  90 , (SW 9). As further depicted in  FIG. 12B , in the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the fifth switch  82 , (SW 5), and the eighth switch  88 , (SW 8). In the fourth phase of operation, (Phase 4), the multiple output μC charge pump control circuit  72 A operably closes the fifth switch  82 , (SW 5), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), and the thirteenth switch  98 , (SW 13). 
         [0188]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/2×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/4×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/4×V BAT , on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 7/4×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0189]    TABLE 2B-2A describes, and  FIGS. 13A-B  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Sixth Buck/Boost Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμB BRATIO ), set to 1/4. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into four phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/4×V BAT . 
         [0190]    As described in TABLE 2B-2A and depicted in  FIG. 13A , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the fourth switch  80 , (SW 4), the tenth switch  92 , (SW 10), and the eleventh switch  94 , (SW 11). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the sixth switch  84 , (SW 6), and the ninth switch  90 , (SW 9). As further depicted in  FIG. 13B , in the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the fifth switch  82 , (SW 5), and the eighth switch  88 , (SW 8). In the fourth phase of operation, (Phase 4), the multiple output μC charge pump control circuit  72 A operably closes the tenth switch  92 , (SW 10), the twelfth switch  96 , (SW 12), and the fifteenth switch  102 , (SW 15). 
         [0191]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/2×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/4×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/4×V BAT , on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/4×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0192]    TABLE 2B-2A describes, and  FIG. 14  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Seventh Buck/Boost Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/3. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into three phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 2/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 4/3×V BAT . 
         [0193]    As described in TABLE 2B-2A and depicted in  FIG. 14 , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fourth switch  80 , (SW 4), the sixth switch  84 , (SW 6), and the ninth switch  90 , (SW 9). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the fifth switch  82 , (SW 5), and the eighth switch  88 , (SW 8). In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the thirteenth switch  98 , (SW 13), and the fifteenth switch  102 , (SW 15). 
         [0194]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/3×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/3×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 2/3×V BAT , on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 4/3×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0195]    TABLE 2B-2A describes the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Eighth Buck/Boost Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/2. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into three phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/2×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/2×V BAT . 
         [0196]    As further described in TABLE 2B-2A, in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), and the ninth switch  90 , (SW 9). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the third switch  78 , (SW 3), the seventh switch  86 , (SW 7), and the eighth switch  88 , (SW 8). In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the thirteenth switch  98 , (SW 13), and the fifteenth switch  102 , (SW 15). 
         [0197]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/2×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/2×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/2×V BAT , on the first μC charge pump output capacitor  46 , (C μ C   —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/2×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0198]    TABLE 2B-2B describes, and  FIG. 15  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Ninth Buck/Boost Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 2/3. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into three phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/3×V BAT . 
         [0199]    As further described in TABLE 2B-2B and depicted in  FIG. 15 , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fifth switch  82 , (SW 5), and the ninth switch  90 , (SW 9). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the third switch  78 , (SW 3), the seventh switch  86 , (SW 7), and the eighth switch  88 , (SW 8). In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the fifth switch  82 , (SW 5), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), and the thirteenth switch  98 , (SW 13). 
         [0200]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/3×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/3×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/3×V BAT , on the first μC charge pump output capacitor  46 , (C μ C   —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/3×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0201]    TABLE 2B-2B describes, and  FIGS. 16A-B  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Tenth Buck/Boost Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 3/4. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into four phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 7/4×V BAT . 
         [0202]    As further described in TABLE 2B-2B and depicted in  FIG. 16A , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fifth switch  82 , (SW 5), and the ninth switch  90 , (SW 9). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the seventh switch  86 , (SW 7), and the eighth switch  88 , (SW 8). As further depicted in  FIG. 16B , in the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the third switch  78 , (SW 3), the ninth switch  90 , (SW 9), and the tenth switch  92 , (SW 10). In the fourth phase of operation, (Phase 4), the multiple output μC charge pump control circuit  72 A operably closes the fifth switch  82 , (SW 5), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), and the thirteenth switch  98 , (SW 13). 
         [0203]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/2×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/4×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/4×V BAT , on the first μC charge pump output capacitor  46 , (C μ C   —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 7/4×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0204]    Both the TABLE 2B-1B and the TABLE 2B-2B describe the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the OFF Mode. As described in both the TABLE 2B-1B and the TABLE 2B-2B, when the controller  14  configures the dual output μC charge pump circuit  12 A to be in the OFF Mode of operation, the multiple output μC charge pump control circuit  72 A may operablely open the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15). As a result, the first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  floats relative to ground. Likewise, the second μC charge pump output voltage, (V μC     —     OUT2 ), on the second μC charge pump output  26  floats relative to ground. 
         [0205]    A non-limiting set of example operational modes of the dual output μC charge pump circuit  12 A configured to operate in a boost/buck mode of operation will now be discussed. As an example, TABLE 3A-1 and TABLE 3A-2, entitled “MODES OF OPERATION TABLE FOR BOOST/BUCK OPERATION OF A DUAL OUTPUT μC CHARGE PUMP CIRCUIT,” describe, in tablulated form, several, non-limiting, example modes of operation of the dual output μC charge pump circuit  12 A configured to operate in a boost/buck mode of operation. As an example, the non-limiting example modes of boost/buck modes of operation described in TABLE 3A-1 include: a First (1 st ) Boost/Buck Mode, a Second (2 nd ) Boost/Buck Mode, a Third (3 rd ) Boost/Buck Mode, a Fourth (4 th ) Boost/Buck Mode, a Fifth (5 th ) Boost/Buck Mode, and an OFF Mode. As another example, the non-limiting example modes of boost/buck modes of operation described in TABLE 3A-2 include: a Sixth (6 th ) Boost/Buck Mode, a Seventh (7 th ) Boost/Buck Mode, an Eighth (8 th ) Boost/Buck Mode, a Ninth (9 th ) Boost/Buck Mode, a Tenth (10 th ) Boost/Buck Mode, and an OFF Mode. 
         [0206]    As depicted in TABLE 3A-1 and TABLE 3A-2, each example boost/buck mode of operation of the dual output μC charge pump circuit  12 A corresponds to an operational ratio, (xμBB RATIO ), where the operational ratio, (xμBB RATIO ), may provide a relationship between the first μC charge pump output voltage, (V μC     —     OUT1 ), generated by the first μC charge pump output  24  and the second μC charge pump output voltage, (V μC     —     OUT2 ), generated by the second μC charge pump output  26 . The operational ratio, (xμBB RATIO ), may be an operational ratio parameter that is configured by the controller  14  and stored locally in the multiple output μC charge pump control circuit  72 A. 
         [0207]    For example, TABLE 3A-1 describes example boost/buck modes of operation of the dual output μC charge pump circuit  12 A where the first μC charge pump output  24  is configured to generate a first μC charge pump output voltage, (V μC     —     OUT1 ) such that V μC     —     OUT1 =(1+xμBB RATIO )×V BAT . For the sake of convenience, and without limitation, the battery voltage, (V BAT ), is used to represent the magnitude of the voltage on the supply voltage  20 . The second μC charge pump output  26  is configured to generate a second μC charge pump output voltage, (V μC     —     OUT2 ) such that V μC     —     OUT2 =(xμBB RATIO )×V BAT , where V BAT  is used to represent the magnitude of the voltage on the supply voltage  20 . 
         [0208]    Accordingly, as described in TABLE 3A-1, in the First Boost/Buck Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/4. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/4×V BAT . In the Second Boost/Buck Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/3. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 4/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/3×V BAT . In the Third Boost/Buck Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/2. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/2×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/2×V BAT . In the Fourth Boost/Buck Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 2/3. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 2/3×V BAT . In the Fifth Boost/Buck Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 3/4. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 7/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT . In the OFF Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the first μC charge pump output  24  to float and the second μC charge pump output  26  to float. 
         [0209]    In contrast, TABLE 3A-2 describes other example boost/buck modes of operation of the dual output μC charge pump circuit  12 A where the first μC charge pump output  24  is configured to generate a first μC charge pump output voltage, (V μC     —     OUT1 ) such that V μC     —     OUT1 =(1+xμBB RATIO )×V BAT . For the sake of convenience, and without limitation, the battery voltage, (V BAT ), is used to represent the magnitude of the voltage on the supply voltage  20 . The second μC charge pump output  26  is configured to generate a second μC charge pump output voltage, (V μC     —     OUT2 ) such that V μC     —     OUT2 =(1−xμBB RATIO )×V BAT , where V BAT  is used to represent the magnitude of the voltage on the supply voltage  20 . 
         [0210]    Accordingly, as described in TABLE 3A-2, in the Sixth Boost/Buck Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/4. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT . In the Seventh Boost/Buck Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/3. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 4/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 2/3×V BAT . In the Eighth Boost/Buck Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/2. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/2×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/2×V BAT . In the Ninth Boost/Buck Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 2/3. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/3×V BAT . In the Tenth Boost/Buck Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 3/4. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 7/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/4×V BAT . In the OFF Mode of operation of the dual output μC charge pump circuit  12 A, the controller  14  configures the first μC charge pump output  24  to float and the second μC charge pump output  26  to float. 
         [0211]    TABLE 3B-1A and TABLE 3B-1B, entitled “SWITCH OPERATION TABLE FOR BUCK/BOOST OPERATION OF DUAL OUTPUT μC CHARGE PUMP,” describe, in tabular form, the switch state (open or closed) of each of the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15), of the dual output μC charge pump circuit  12 A when the dual output μC charge pump circuit  12 A is configured to operate in the boost/buck modes of operation described in TABLE 3A-1. In addition, TABLE 3B-1A and TABLE 3B-1B also provide the corresponding operational ratio, (xμBB RATIO ), used by the dual output μC charge pump circuit  12 A when operating in the boost/buck modes of operation described in TABLE 3A-1. TABLE 3B-1A and TABLE 3B-1B further describe the switch state of each of the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15), relative to the particular phases of operation used by the dual output μC charge pump circuit  12 A when operating in the boost/buck modes of operation described in TABLE 3A-1. 
         [0212]    TABLE 3B-2A and TABLE 3B-2B, also entitled “SWITCH OPERATION TABLE FOR BUCK/BOOST OPERATION OF DUAL OUTPUT μC CHARGE PUMP,” describe, in tabular form, the switch state (open or closed) of each of the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15), of the dual output μC charge pump circuit  12 A when the dual output μC charge pump circuit  12 A is configured to operate in the boost/buck modes of operation described in TABLE 3A-2. In addition, TABLE 3B-2A and TABLE 3B-2B also provide the corresponding operational ratio, (xμBB RATIO ), used by the dual output μC charge pump circuit  12 A when operating in the boost/buck modes of operation described in TABLE 3A-2. TABLE 3B-2A and TABLE 3B-2B further describe the switch state of each of the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15), relative to the particular phases of operation used by the dual output μC charge pump circuit  12 A when operating in the boost/buck modes of operation described in TABLE 3A-2. 
         [0213]    As used in TABLE 3B-1A, TABLE 3B-1B, TABLE 3B-2A, and TABLE 3B-2A, “PHASE 1” indicates that the dual output μC charge pump circuit  12 A is configured to operate in a first phase of operation, where the multiple output μC charge pump control circuit  72 A configures the switch state (open or closed) of the identified μC charge pump switch to be closed during the time period of the first phase of operation. “PHASE 2” indicates that the dual output μC charge pump circuit  12 A is configured to operate in a second phase of operation, where the multiple output μC charge pump control circuit  72 A configures the switch state (open or closed) of the identified μC charge pump switch to be closed during the time period of the second phase of operation. “PHASE 3” indicates that the dual output μC charge pump circuit  12 A is configured to operate in a third phase of operation, where the multiple output μC charge pump control circuit  72 A configures the switch state (open or closed) of the identified μC charge pump switch to be closed during the time period of the third phase of operation. “PHASE 4” indicates that the dual output μC charge pump circuit  12 A is configured to operate in a fourth phase of operation, where the multiple output μC charge pump control circuit  72 A configures the switch state (open or closed) of the identified μC charge pump switch to be closed during the time period of the fourth phase of operation. “OPEN” indicates that the multiple output μC charge pump control circuit  72 A configures the switch state (open or closed) of the identified switch to be closed during all the phases of operation of the dual output μC charge pump circuit  12 A. 
         [0000]    
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 3A-1 
               
             
             
               
                   
               
               
                 MODES OF OPERATION TABLE FOR BOOST/BUCK OPERATION 
               
               
                 OF A DUAL OUTPUT μC CHARGE PUMP CIRCUIT 
               
             
          
           
               
                   
                   
                 FIRST μC CHARGE PUMP 
                 SECOND μC CHARGE PUMP 
               
               
                 MODES OF 
                 OPERATIONAL RATIOS, 
                 OUTPUT, (V μC     —     OUT1 ), where 
                 OUTPUT, (V μC     —     OUT2 ), where 
               
               
                 OPERATION 
                 (xμBB RATIO ) 
                 V μC     —     OUT1  = (1 + xμBB RATIO ) × V BAT   
                 V μC     —     OUT2  = (xμBB RATIO ) × V BAT   
               
               
                   
               
               
                 First Boost/ 
                 1/4 
                 5/4 × V BAT   
                 1/4 × V BAT   
               
               
                 Buck Mode 
               
               
                 Second Boost/ 
                 1/3 
                 4/3 × V BAT   
                 1/3 × V BAT   
               
               
                 Buck Mode 
               
               
                 Third Boost/ 
                 1/2 
                 3/2 × V BAT   
                 1/2 × V BAT   
               
               
                 Buck Mode 
               
               
                 Fourth Boost/ 
                 2/3 
                 5/3 × V BAT   
                 2/3 × V BAT   
               
               
                 Buck Mode 
               
               
                 Fifth Boost/ 
                 3/4 
                 7/4 × V BAT   
                 3/4 × V BAT   
               
               
                 Buck Mode 
               
               
                 OFF Mode 
                 OFF 
                 FLOATING 
                 FLOATING 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 3A-2 
               
             
             
               
                   
               
               
                 MODES OF OPERATION TABLE FOR BOOST/BUCK OPERATION OF A DUAL OUTPUT μC CHARGE PUMP 
               
               
                 CIRCUIT 
               
             
          
           
               
                   
                   
                 FIRST μC CHARGE PUMP 
                 SECOND μC CHARGE PUMP 
               
               
                 MODES OF 
                 OPERATIONAL RATIOS, 
                 OUTPUT, (V μC _OUT1), where 
                 OUTPUT, (V μC _OUT2), where 
               
               
                 OPERATION 
                 (xμBB RATIO ) 
                 V μC _OUT1 = (1 + xμBB RATIO ) × V BAT   
                 V μC _OUT2 = (1 − xμBB RATIO ) × V BAT   
               
               
                   
               
               
                 Sixth Boost/Buck 
                 1/4 
                 5/4 × V BAT   
                 3/4 × V BAT   
               
               
                 Mode 
                   
                   
                   
               
               
                 Seventh Boost/ 
                 1/3 
                 4/3 × V BAT   
                 2/3 × V BAT   
               
               
                 Buck Mode 
                   
                   
                   
               
               
                 Eighth Boost/ 
                 1/2 
                 3/2 × V BAT   
                 1/2 × V BAT   
               
               
                 Buck Mode 
                   
                   
                   
               
               
                 Ninth Boost/Buck 
                 2/3 
                 5/3 × V BAT   
                 1/3 × V BAT   
               
               
                 Mode 
                   
                   
                   
               
               
                 Tenth Boost/Buck 
                 3/4 
                 7/4 × V BAT   
                 1/4 × V BAT   
               
               
                 Mode 
                   
                   
                   
               
               
                 OFF Mode 
                 OFF 
                 FLOATING 
                 FLOATING 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
             
               
               
               
               
             
           
               
                 TABLE 3B-1A 
               
             
             
               
                   
               
               
                 SWITCH OPERATION TABLE FOR BOOST/BUCK MODE 
               
               
                 OF OPERATION OF DUAL OUTPUT μC CHARGE PUMP 
               
             
          
           
               
                   
                 MODES OF OPERATION FOR BOOST/BUCK OPERATION OF DUAL OUTPUT μC 
               
               
                   
                 CHARGE PUMP WITH CORRESPONDING OPERATIONAL RATIOS, (xμBB RATIO ) 
               
             
          
           
               
                 See, 
                 First Boost/Buck Mode, 
                 Second Boost/Buck Mode, 
                 Third Boost/Buck Mode, 
               
               
                 TABLE 3A-1 
                 (xμBB RATIO  = 1/4), where 
                 (xμBB RATIO  = 1/3), where 
                 (xμBB RATIO  = 1/2), where 
               
               
                 μC CHARGE PUMP 
                 V μC     —     OUT1  = 5/4 × V BAT  and 
                 V μC     —     OUT1  = 4/3 × V BAT , and 
                 V μC     —     OUT1  = 3/2 × V BAT , and 
               
               
                 SWITCHES 
                 V μC     —     OUT2  = 1/4 × V BAT   
                 V μC     —     OUT2  = 1/3 × V BAT   
                 V μC     —     OUT2  = 1/2 × V BAT   
               
               
                   
               
               
                 SW 1 
                 Phase 1 
                 Phase 1 
                 Phase 1 
               
               
                 SW 2 
                 OPEN 
                 Phase 3 
                 Phase 3 
               
               
                 SW 3 
                 Phase 3 
                 Phase 2 
                 Phase 2 
               
               
                 SW 4 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 5 
                 Phase 1 
                 Phase 1 
                 OPEN 
               
               
                 SW 6 
                 OPEN 
                 OPEN 
                 Phase 1 
               
               
                 SW 7 
                 OPEN 
                 Phase 3 
                 Phase 3 
               
               
                 SW 8 
                 Phase 2 
                 Phase 2 
                 Phase 2 
               
               
                 SW 9 
                 Phase 4 
                 OPEN 
                 OPEN 
               
               
                 SW 10 
                 Phase 3 and Phase 4 
                 Phase 2 
                 Phase 2 
               
               
                 SW 11 
                 OPEN 
                 Phase 3 
                 Phase 3 
               
               
                 SW 12 
                 Phase 1 and Phase 3 
                 Phase 1 
                 Phase 1 
               
               
                 SW 13 
                 Phase 2 
                 Phase 2 
                 Phase 2 
               
               
                 SW 14 
                 OPEN 
                 OPEN 
                 Phase 1 
               
               
                 SW 15 
                 Phase 4 
                 Phase 3 
                 Phase 3 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
             
               
               
               
               
             
           
               
                 TABLE 3B-1B 
               
             
             
               
                   
               
               
                 SWITCH OPERATION TABLE FOR BOOST/BUCK MODE 
               
               
                 OF OPERATION OF DUAL OUTPUT μC CHARGE PUMP 
               
             
          
           
               
                   
                 MODES OF OPERATION FOR BOOST/BUCK OPERATION OF DUAL OUTPUT μC 
               
               
                   
                 CHARGE PUMP WITH CORRESPONDING OPERATIONAL RATIOS, (xμBB RATIO ) 
               
             
          
           
               
                 See, 
                 Fourth Boost/Buck Mode, 
                 Fifth Boost/Buck Mode, 
                 OFF Mode 
               
               
                 TABLE 3A-1 
                 (xμBB RATIO  = 2/3), where 
                 (xμBB RATIO  = 3/4), where 
                 where 
               
               
                 μC CHARGE PUMP 
                 V μC     —     OUT1  = 5/3 × V BAT  and 
                 V μC     —     OUT1  = 7/4 × V BAT , and 
                 V μC     —     OUT1  = FLOAT 
               
               
                 SWITCHES 
                 V μC     —     OUT2  = 2/3 × V BAT   
                 V μC     —     OUT2  = 3/4 × V BAT   
                 V μC     —     OUT2  = FLOAT 
               
               
                   
               
               
                 SW 1 
                 Phase 1 
                 OPEN 
                 OPEN 
               
               
                 SW 2 
                 Phase 3 
                 Phase 4 
                 OPEN 
               
               
                 SW 3 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 4 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 5 
                 Phase 2 and Phase 3 
                 Phase 3 and Phase 4 
                 OPEN 
               
               
                 SW 6 
                 Phase 1 
                 Phase 2 
                 OPEN 
               
               
                 SW 7 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 8 
                 Phase 2 
                 Phase 3 
                 OPEN 
               
               
                 SW 9 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 10 
                 Phase 2 
                 Phase 1 and Phase 3 
                 OPEN 
               
               
                 SW 11 
                 Phase 3 
                 Phase 1 and Phase 4 
                 OPEN 
               
               
                 SW 12 
                 Phase 1 
                 Phase 2 
                 OPEN 
               
               
                 SW 13 
                 Phase 2 
                 Phase 3 
                 OPEN 
               
               
                 SW 14 
                 Phase 1 
                 Phase 1 
                 OPEN 
               
               
                 SW 15 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
             
               
               
               
               
             
           
               
                 TABLE 3B-2A 
               
             
             
               
                   
               
               
                 SWITCH OPERATION TABLE FOR BOOST/BUCK MODE 
               
               
                 OF OPERATION OF DUAL OUTPUT μC CHARGE PUMP 
               
             
          
           
               
                   
                 MODES OF OPERATION FOR BOOST/BUCK OPERATION OF DUAL OUTPUT μC 
               
               
                   
                 CHARGE PUMP WITH CORRESPONDING OPERATIONAL RATIOS, (xμBB RATIO ) 
               
             
          
           
               
                 See, 
                 Sixth Boost/Buck Mode, 
                 Seventh Boost/Buck Mode, 
                 Eighth Boost/Buck Mode, 
               
               
                 TABLE 3A-2 
                 (xμBB RATIO  = 1/4), where 
                 (xμBB RATIO  = 1/3), where 
                 (xμBB RATIO  = 1/2), where 
               
               
                 μC CHARGE PUMP 
                 V μC     —     OUT1  = 5/4 × V BAT  and 
                 V μC     —     OUT1  = 4/3 × V BAT , and 
                 V μC     —     OUT1  = 1/2 × V BAT , and 
               
               
                 SWITCHES 
                 V μC     —     OUT2  = 3/4 × V BAT   
                 V μC     —     OUT2  = 2/3 × V BAT   
                 V μC     —     OUT2  = 3/2 × V BAT   
               
               
                   
               
               
                 SW 1 
                 OPEN 
                 Phase 1 
                 Phase 1 
               
               
                 SW 2 
                 OPEN 
                 Phase 3 
                 Phase 3 
               
               
                 SW 3 
                 OPEN 
                 OPEN 
                 Phase 2 
               
               
                 SW 4 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 5 
                 Phase 3 
                 Phase 2 
                 OPEN 
               
               
                 SW 6 
                 Phase 2 
                 Phase 1 
                 Phase 1 
               
               
                 SW 7 
                 OPEN 
                 Phase 3 
                 Phase 3 
               
               
                 SW 8 
                 Phase 3 
                 Phase 2 
                 Phase 2 
               
               
                 SW 9 
                 Phase 4 
                 OPEN 
                 OPEN 
               
               
                 SW 10 
                 Phase 1, Phase 3 and Phase 4 
                 Phase 2 
                 Phase 2 
               
               
                 SW 11 
                 Phase1 
                 Phase 3 
                 Phase 3 
               
               
                 SW 12 
                 Phase 2 
                 Phase 1 
                 Phase 1 
               
               
                 SW 13 
                 Phase 3 
                 Phase 2 
                 Phase 2 
               
               
                 SW 14 
                 Phase 1 
                 Phase 1 
                 Phase 1 
               
               
                 SW 15 
                 Phase 4 
                 Phase 3 
                 Phase 3 
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
             
               
               
               
               
             
           
               
                 TABLE 3B-2B 
               
             
             
               
                   
               
               
                 SWITCH OPERATION TABLE FOR BOOST/BUCK MODE 
               
               
                 OF OPERATION OF DUAL OUTPUT μC CHARGE PUMP 
               
             
          
           
               
                   
                 MODES OF OPERATION FOR BOOST/BUCK OPERATION OF DUAL OUTPUT μC 
               
               
                   
                 CHARGE PUMP WITH CORRESPONDING OPERATIONAL RATIOS, (xμBB RATIO ) 
               
             
          
           
               
                 See, 
                 Ninth Boost/Buck Mode, 
                 Tenth Boost/Buck Mode, 
                 OFF Mode 
               
               
                 TABLE 3A-2 
                 (xμBB RATIO  = 2/3), where 
                 (xμBB RATIO  = 3/4), where 
                 where 
               
               
                 μC CHARGE PUMP 
                 V μC     —     OUT1  = 5/3 × V BAT  and 
                 V μC     —     OUT1  = 7/4 × V BAT , and 
                 V μC     —     OUT1  = FLOAT 
               
               
                 SWITCHES 
                 V μC     —     OUT2  = 1/3 × V BAT   
                 V μC     —     OUT2  = 1/4 × V BAT   
                 V μC     —     OUT2  = FLOAT 
               
               
                   
               
               
                 SW 1 
                 Phase 1 
                 Phase 1 
                 OPEN 
               
               
                 SW 2 
                 Phase 3 
                 Phase 4 
                 OPEN 
               
               
                 SW 3 
                 Phase 2 
                 Phase 3 
                 OPEN 
               
               
                 SW 4 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 5 
                 Phase 1 and Phase 3 
                 Phase 1 and Phase 4 
                 OPEN 
               
               
                 SW 6 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 7 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 8 
                 Phase 2 
                 Phase 2 
                 OPEN 
               
               
                 SW 9 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 10 
                 Phase 2 
                 Phase 3 
                 OPEN 
               
               
                 SW 11 
                 Phase 3 
                 Phase 4 
                 OPEN 
               
               
                 SW 12 
                 Phase 1 
                 Phase 1 and Phase 3 
                 OPEN 
               
               
                 SW 13 
                 Phase 2 
                 Phase 2 
                 OPEN 
               
               
                 SW 14 
                 OPEN 
                 OPEN 
                 OPEN 
               
               
                 SW 15 
                 OPEN 
                 OPEN 
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         [0214]    The configurations and operations of the dual output μC charge pump circuit  12 A when the dual output μC charge pump circuit  12 A operates in the various boost/buck modes, described in the TABLE 3A-1 and the TABLE 3A-2, will now be discussed with reference to the TABLE 3B-1A, the TABLE 3B-1B, the TABLE 3B-2A, and the TABLE 3B-2B. 
         [0215]    TABLE 3B-1A describes, and  FIGS. 17A-B  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the First Boost/Buck Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμB BRATIO ), set to 1/4. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into four phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/4×V BAT . 
         [0216]    As described in TABLE 3B-1A and depicted in  FIG. 17A , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fifth switch  82 , (SW 5), and the twelfth switch  96 , (SW 12). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the eighth switch  88 , (SW 8) and the thirteenth switch  98 , (SW 13). As further depicted in  FIG. 17B , in the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the third switch  78 , (SW 3), the tenth switch  92 , (SW 10), and the twelfth switch  96 , (SW 12). In the fourth phase of operation, (Phase 4), the multiple output μC charge pump control circuit  72 A operably closes the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), and the fifteenth switch  102 , (SW 15). 
         [0217]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/2×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/4×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/4×V BAT , on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/4×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0218]    TABLE 3B-1A describes, and  FIG. 18  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Second Boost/Buck Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/3. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into three phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 4/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/3×V BAT . 
         [0219]    As described in TABLE 3B-1A and depicted in  FIG. 18 , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fifth switch  82 , (SW 5), and the tenth switch  92 , (SW 10). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the third switch  78 , (SW 3), the eighth switch  88 , (SW 8), the tenth switch  92 , (SW 10), and the thirteenth switch  98 , (SW 13). In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the seventh switch  86 , (SW 7), the eleventh switch  94 , (SW 11), and the fifteenth switch  102 , (SW 15). 
         [0220]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/3×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/3×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 4/3×V BAT , on the first μC charge pump output capacitor  46 , (C μ C   —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/3×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0221]    TABLE 3B-1A describes, and  FIG. 19  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Third Boost/Buck Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/2. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into three phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/2×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/2×V BAT . 
         [0222]    As further described in TABLE 3B-1A and depicted in  FIG. 19 , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the sixth switch  84 , (SW 6), the twelfth switch  96 , (SW 12), and the fourteenth switch  100 , (SW 14). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the third switch  78 , (SW 3), the eighth switch  88 , (SW 8), the tenth switch  92 , (SW 10), and the thirteenth switch  98 , (SW 13). In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the seventh switch  86 , (SW 7), the eleventh switch  94 , (SW 11), and the fifteenth switch  102 , (SW 15). 
         [0223]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/2×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/2×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/2×V BAT , on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/2×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0224]    TABLE 3B-1B describes, and  FIG. 20  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Fourth Boost/Buck Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 2/3. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into three phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/3×V BAT ) and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 2/3×V BAT . 
         [0225]    As further described in TABLE 3B-1B and depicted in  FIG. 20 , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the sixth switch  84 , (SW 6), the twelfth switch  96 , (SW 12), and the fourteenth switch  100 , (SW 14). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the fifth switch  82 , (SW 5), the eighth switch  88 , (SW 8), the tenth switch  92 , (SW 10), and the thirteenth switch  98 , (SW 13). In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the fifth switch  82 , (SW 5), and the eleventh switch  94 , (SW 11). 
         [0226]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/3×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/3×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/3×V BAT , on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 2/3×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0227]    TABLE 3B-1B describes, and  FIGS. 21A-B  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Fifth Boost/Buck Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 3/4. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into four phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 7/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT . 
         [0228]    As further described in TABLE 3B-1B and depicted in  FIG. 21A , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), and the fourteenth switch  100 , (SW 14). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the sixth switch  84 , (SW 6), and the twelfth switch  96 , (SW 12). As further depicted in  FIG. 21B , in the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the fifth switch  82 , (SW 5), the eighth switch  88 , (SW 8), the tenth switch  92 , (SW 10), and the thirteenth switch  98 , (SW 13). In the fourth phase of operation, (Phase 4), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the fifth switch  82 , (SW 5), and the eleventh switch  94 , (SW 11). 
         [0229]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/2×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/4×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 7/4×V BAT , on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0230]    TABLE 3B-2A describes, and  FIGS. 22A-B  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Sixth Boost/Buck Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμB BRATIO ), set to 1/4. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into four phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT . 
         [0231]    As described in TABLE 3B-2A and depicted in  FIG. 22A , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), and the fourteenth switch  100 , (SW 14). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the sixth switch  84 , (SW 6), and the twelfth switch  96 , (SW 12). As further depicted in  FIG. 22B , in the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the fifth switch  82 , (SW 5), the eighth switch  88 , (SW 8), the tenth switch  92 , (SW 10), and the thirteenth switch  98 , (SW 13). In the fourth phase of operation, (Phase 4), the multiple output μC charge pump control circuit  72 A operably closes the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), and the fifteenth switch  102 , (SW 15). 
         [0232]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/2×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/4×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/4×V BAT , on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0233]    TABLE 3B-2A describes, and  FIG. 23  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Seventh Boost/Buck Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/3. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into three phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 4/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 2/3×V BAT . 
         [0234]    As described in TABLE 3B-2A and depicted in  FIG. 23 , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the sixth switch  84 , (SW 6), the twelfth switch  96 , (SW 12), and the fourteenth switch  100 , (SW 14). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the fifth switch  82 , (SW 5), the eighth switch  88 , (SW 8), the tenth switch  92 , (SW 10), and the thirteenth switch  98 , (SW 13). In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the seventh switch  86 , (SW 7), the eleventh switch  94 , (SW 11), and the fifteenth switch  102 , (SW 15). 
         [0235]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/3×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/3×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 4/3×V BAT , on the first μC charge pump output capacitor  46 , (C μ C   —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 2/3×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0236]    TABLE 3B-2A describes the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Eighth Boost/Buck Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 1/2. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into three phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/2×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/2×V BAT . 
         [0237]    As further described in TABLE 3B-2A, in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the sixth switch  84 , (SW 6), the twelfth switch  96 , (SW 12), and the fourteenth switch  100 , (SW 14). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the third switch  78 , (SW 3), the eighth switch  88 , (SW 8), the tenth switch  92 , (SW 10), and the thirteenth switch  98 , (SW 13). In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the seventh switch  86 , (SW 7), the eleventh switch  94 , (SW 11), and the fifteenth switch  102 , (SW 15). 
         [0238]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/2×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/2×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/2×V BAT , on the first μC charge pump output capacitor  46 , (C μ C   —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/2×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0239]    TABLE 3B-2B describes, and  FIG. 24  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Ninth Boost/Buck Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 2/3. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into three phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/3×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/3×V BAT . 
         [0240]    As further described in TABLE 3B-2B and depicted in  FIG. 24 , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fifth switch  82 , (SW 5), and the twelfth switch  96 , (SW 12). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the third switch  78 , (SW 3), the eighth switch  88 , (SW 8), the tenth switch  92 , (SW 10), and the thirteenth switch  98 , (SW 13). In the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the fifth switch  82 , (SW 5), and the eleventh switch  94 , (SW 11). 
         [0241]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/3×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/3×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/3×V BAT , on the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/3×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0242]    TABLE 3B-2B describes, and  FIGS. 25A-B  depicts, the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the Tenth Boost/Buck Mode. The controller  14  configures the multiple output μC charge pump control circuit  72 A to use an operational ratio, (xμBB RATIO ), set to 3/4. The multiple output μC charge pump control circuit  72 A operably divides the operation of the dual output μC charge pump circuit  12 A into four phases of operation. The multiple output μC charge pump control circuit  72 A operably configures the dual output μC charge pump switch matrix circuit  70 A such that first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 7/4×V BAT , and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/4×V BAT . 
         [0243]    As further described in TABLE 3B-2B and depicted in  FIG. 25A , in the first phase of operation, (Phase 1), the multiple output μC charge pump control circuit  72 A operably closes the first switch  74 , (SW 1), the fifth switch  82 , (SW 5), and the twelfth switch  96 , (SW 12). In the second phase of operation, (Phase 2), the multiple output μC charge pump control circuit  72 A operably closes the eighth switch  88 , (SW 8), and the thirteenth switch  98 , (SW 13). As further depicted in  FIG. 25B , in the third phase of operation, (Phase 3), the multiple output μC charge pump control circuit  72 A operably closes the third switch  78 , (SW 3), the tenth switch  92 , (SW 10), and the twelfth switch  96 , (SW 12). In the fourth phase of operation, (Phase 4), the multiple output μC charge pump control circuit  72 A operably closes the second switch  76 , (SW 2), the fifth switch  82 , (SW 5), and the eleventh switch  94 , (SW 11). 
         [0244]    As a result, the first flying capacitor  42 , (C FLY1 ), develops a first flying capacitor voltage, (V CAP     —     FLY1 ), substantially equal to 1/2×V BAT , and the second flying capacitor  44 , (C FLY2 ), develops a second flying capacitor voltage, (V CAP     —     FLY2 ), substantially equal to 1/4×V BAT . Accordingly, first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 7/4×V BAT , on the first μC charge pump output capacitor  46 , (C μ C   —     OUT1 ), and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/4×V BAT  on the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ). 
         [0245]    Both the TABLE 3B-1B and the TABLE 3B-2B describe the operation of the dual output μC charge pump circuit  12 A when the controller  14  configures the dual output μC charge pump circuit  12 A to operate in the OFF Mode. As described in both the TABLE 3B-1B and the TABLE 3B-2B, when the controller  14  configures the dual output μC charge pump circuit  12 A to be in the OFF Mode of operation, the multiple output μC charge pump control circuit  72 A may operablely open the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15). As a result, the first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  floats relative to ground. Likewise, the second μC charge pump output voltage, (V μC     —     OUT2 ), on the second μC charge pump output  26  floats relative to ground. 
         [0246]      FIG. 2B  depicts another embodiment of the dual output μC charge pump circuit  12 , depicted in  FIG. 1A , as a dual output μC charge pump circuit  12 B. The dual output μC charge pump circuit  12 B is similar in form and function to the dual output μC charge pump circuit  12 A depicted in  FIG. 2A  except as described as follows: (1) the dual output μC charge pump circuit  12 B includes a multiple output μC charge pump switch matrix and control circuit  40 B instead of the multiple output μC charge pump switch matrix and control circuit  40 A; (2) the dual output μC charge pump circuit  12 B includes the dual output μC charge pump switch matrix circuit  70 B instead of the dual output μC charge pump switch matrix circuit  70 A; and (3) the dual output μC charge pump circuit  12 B includes a multiple output μC charge pump control circuit  72 B instead of a the multiple output μC charge pump control circuit  72 A. 
         [0247]    Unlike the dual output μC charge pump switch matrix circuit  70 A of the multiple output μC charge pump switch matrix and control circuit  40 A, the dual output μC charge pump switch matrix circuit  70 B omits the twelfth switch  96 , (SW 12), and the fourteenth switch  100 , (SW 14), as depicted in  FIG. 2A . Accordingly, the multiple output μC charge pump control circuit  72 B of the dual output μC charge pump circuit  12 B, depicted in  FIG. 2B , omits both a twelfth switch control configured to provide a twelfth switch control signal  130  to control the twelfth switch  96 , (SW 12) and a fourteenth switch control configured to provide a twelfth switch control signal  130  to control the fourteenth switch  100 , (SW 14), as depicted in  FIG. 2A . 
         [0248]    Even so, because the dual output μC charge pump circuit  12 B is otherwise similar in form and function to the dual output μC charge pump circuit  12 A depicted in  FIG. 2A , the controller  14  may configure the dual output μC charge pump circuit  12 B to operate in any of the modes of operation that may be performed by the dual output μC charge pump circuit  12 A, as described above, that do not require either the twelfth switch  96 , (SW 12), the fourteenth switch  100 , (SW 14), or a combination thereof, to be closed. Accordingly, for the sake of brevity, the specific operational modes of the dual output μC charge pump circuit  12 B will not be discussed in detail. Although the specific operational modes of the dual output μC charge pump circuit  12 B are not specifically discussed in detail, the modes of operation of the dual output μC charge pump circuit  12 B, as would be evident to one of ordinary skill in the art, are thereby considered to be within the scope of the concepts disclosed with respect to the modes of operation of the dual output μC charge pump circuit  12 B. 
         [0249]    Accordingly, the dual output μC charge pump circuit  12 B provides an advantage of being able to perform many of the numerous modes of operation of the dual output μC charge pump circuit  12 A without the added complexity of including the twelfth switch  96 , (SW 12), the fourteenth switch  100 , (SW 14), or a combination thereof. As a result, in come embodiments, the dual output μC charge pump circuit  12 B may be used to reduce both silicon foot print and power requirement of the multiple output μC charge pump system  10 A. This advantage is particularly useful in cases where the supply voltage  20  may be derived from a battery  22 , as depicted in  FIG. 1A . In addition, as discussed above relative to the embodiments of the dual output μC charge pump circuit  12 , depicted in  FIG. 1A , and the dual output μC charge pump circuit  12 A, depicted in  FIG. 2A , some embodiments of dual output μC charge pump circuit  12 B may include and use more than two flying capactiors to generate the first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  and the second μC charge pump output voltage, (V μC     —     OUT2 ), on the second μC charge pump output  26 . However, advantageously, as depicted in  FIG. 2B , and previously described with respect to the various modes of operation of the dual output μC charge pump circuit  12 , depicted in  FIG. 1A , and the dual output μC charge pump circuit  12 A, depicted in  FIG. 2A , some embodiments of the dual output μC charge pump circuit  12 B may be configured to generate the desired output voltage levels, namely the first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  and the second μC charge pump output voltage, (V μC     —     OUT2 ), on the second μC charge pump output  26 , using only the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ). In other words, some embodiments of the dual output μC charge pump circuit  12 B may be configured to generate the variously described output voltage levels corresponding to a “buck/buck mode” of operation, a “buck/boost mode” of operation, and/or a “boost/buck mode” of operation using only the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ). It may be appreciated that those embodiment of the dual output μC charge pump circuit  12 B that only use the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ), to generate the desired output voltage levels on the first μC charge pump output  24  and the second μC charge pump output  26  may provide improved technical performance due to reduced complexity and reduced response time verses those embodiments of the dual output μC charge pump circuit that include more than two flying capacitors. 
         [0250]      FIG. 2C  depicts another embodiment of the dual output μC charge pump circuit  12 , depicted in  FIG. 1A , as a dual output μC charge pump circuit  12 C. The dual output μC charge pump circuit  12 C is similar in form and function to the dual output μC charge pump circuit  12 A depicted in  FIG. 2A  except as described as follows: (1) the dual output μC charge pump circuit  12 C includes a multiple output μC charge pump switch matrix and control circuit  40 C instead of the multiple output μC charge pump switch matrix and control circuit  40 A; (2) the dual output μC charge pump circuit  12 C includes the dual output μC charge pump switch matrix circuit  70 C instead of the dual output μC charge pump switch matrix circuit  70 A; and (3) the dual output μC charge pump circuit  12 C includes a multiple output μC charge pump control circuit  72 C instead of a the multiple output μC charge pump control circuit  72 A. 
         [0251]    Unlike the dual output μC charge pump switch matrix circuit  70 A of the multiple output μC charge pump switch matrix and control circuit  40 A, the dual output μC charge pump switch matrix circuit  70 C omits the thirteenth switch  98 , (SW 13), as depicted in  FIG. 2A . Accordingly, the multiple output μC charge pump control circuit  72 C of the dual output μC charge pump circuit  12 C, depicted in  FIG. 2C , omits a thirteenth switch control configured to provide a thirteenth switch control signal  132  to control the thirteenth switch  98 , (SW 13), as depicted in  FIG. 2A . 
         [0252]    Even so, because the dual output μC charge pump circuit  12 C is otherwise similar in form and function to the dual output μC charge pump circuit  12 A depicted in  FIG. 2A , the controller  14  may configure the dual output μC charge pump circuit  12 C to operate in any of the modes of operation that may be performed by the dual output μC charge pump circuit  12 A, as described above, except those modes of operation that require the thirteenth switch  98 , (SW 13), as depicted in  FIG. 2A , to be closed. Accordingly, for the sake of brevity, the specific operational modes of the dual output μC charge pump circuit  12 C will not be discussed in detail. Although the specific operational modes of the dual output μC charge pump circuit  12 C are not specifically discussed in detail, the modes of operation of the dual output μC charge pump circuit  12 C, as would be evident to one of ordinary skill in the art, are thereby consider to be within the scope of the concepts disclosed with respect to the modes of operation of the dual output μC charge pump circuit  12 C. 
         [0253]    Accordingly, the dual output μC charge pump circuit  12 C may provide an advantage of being able to perform may of the numerous modes of operation of the dual output μC charge pump circuit  12 A without the added complexity of including a thirteenth switch  98 , (SW 13), as depicted in  FIG. 2A . As a result, in come embodiments, the dual output μC charge pump circuit  12 C may be used to reduce both silicon foot print and power requirement of the multiple output μC charge pump system  10 A. This advantage is particularly useful in cases where the supply voltage  20  may be derived from a battery  22 , as depicted in  FIG. 1A . In addition, as discussed above relative to the embodiments of the dual output μC charge pump circuit  12 , depicted in  FIG. 1A , the dual output μC charge pump circuit  12 A, depicted in  FIG. 2A , and the dual output μC charge pump circuit  12 B, depicted in  FIG. 2B , some embodiments of dual output μC charge pump circuit  12 C, depicted in  FIG. 2C , may include and use more than two flying capactiors to generate the first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  and the second μC charge pump output voltage, (V μC     —     OUT2 ), on the second μC charge pump output  26 . However, advantageously, as depicted in  FIG. 2C , and previously described with respect to the various modes of operation of the dual output μC charge pump circuit  12 , depicted in  FIG. 1A , the dual output μC charge pump circuit  12 A, depicted in  FIG. 2A , and the dual output μC charge pump circuit  12 B, depicted in  FIG. 2B , some embodiments of the dual output μC charge pump circuit  12 C may be configured to generate the desired output voltage levels, namely the first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  and the second μC charge pump output voltage, (V μC     —     OUT2 ), on the second μC charge pump output  26 , using only the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ). In other words, some embodiments of the dual output μC charge pump circuit  12 C may be configured to generate the variously described output voltage levels corresponding to a “buck/buck mode” of operation, a “buck/boost mode” of operation, and/or a “boost/buck mode” of operation using only the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ). It may be appreciated that those embodiment of the dual output μC charge pump circuit  12 C that only use the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ), to generate the desired output voltage levels on the first μC charge pump output  24  and the second μC charge pump output  26  may provide improved technical performance due to reduced complexity and reduced response time verses those embodiments of the dual output μC charge pump circuit that include more than two flying capacitors. 
         [0254]      FIG. 2D  depicts another embodiment of the dual output μC charge pump circuit  12 , depicted in  FIG. 1A , as a dual output μC charge pump circuit  12 D. The dual output μC charge pump circuit  12 D, depicted in  FIG. 2D , is operationally similar to the dual output μC charge pump circuit  12 A. Unlike the dual output μC charge pump circuit  12 A, the dual output μC charge pump circuit  12 D replaces the multiple output μC charge pump switch matrix and control circuit  40 A with a multiple output μC charge pump switch matrix and control circuit  40 D. Unlike the multiple output μC charge pump switch matrix and control circuit  40 A, the multiple output μC charge pump switch matrix and control circuit  40 D replaces the dual output μC charge pump switch matrix circuit  70 A with the dual output μC charge pump switch matrix circuit  70 D. Likewise, the multiple output μC charge pump switch matrix and control circuit  40 D replaces the multiple output μC charge pump control circuit  72 A with a multiple output μC charge pump control circuit  72 D. 
         [0255]    The dual output μC charge pump switch matrix circuit  70 D is operationally similar to the dual output μC charge pump switch matrix circuit  70 A, depicted in  FIG. 2A . However, unlike the dual output μC charge pump switch matrix circuit  70 A, the dual output μC charge pump switch matrix circuit  70 D further includes a sixteenth switch  104 , (SW 16), and a seventeenth switch  106 , (SW 17). 
         [0256]    Similarly, the multiple output μC charge pump control circuit  72 D is operationally similar to the multiple output μC charge pump control circuit  72 A, depicted in  FIG. 2A . However, unlike the multiple output μC charge pump control circuit  72 A, the multiple output μC charge pump control circuit  72 D further includes a sixteenth switch control configured to provide a sixteenth switch control signal  138  to the sixteenth switch  104 , (SW 16), to control the operation of the sixteenth switch  104 , (SW 16). In addition, unlike the multiple output μC charge pump control circuit  72 A, the multiple output μC charge pump control circuit  72 D further includes a seventeenth switch control configured to provide a seventeenth switch control signal  140  to the seventeenth switch  106 , (SW 17), to control the operation of the seventeenth switch  106 , (SW 17). 
         [0257]    Advantageously, the sixteenth switch  104 , (SW 16), may be coupled between the supply voltage  20  and the first μC charge pump output  24  to provide a “bypass path” for current to flow directly from the supply voltage  20  to the first μC charge pump output  24 . The sixteenth switch  104 , (SW 16), may include a sixteenth switch control input configured to receive the sixteenth switch control signal  138  from the multiple output μC charge pump control circuit  72 D. The multiple output μC charge pump control circuit  72 D may configure the sixteenth switch control signal  138  to operably open and close the sixteenth switch  104 , (SW 16), based upon the various modes of operation of the dual output μC charge pump circuit  12 D. 
         [0258]    In a similarly advantageous fashion, the seventeenth switch  106 , (SW 17), may be coupled between the supply voltage  20  and the second μC charge pump output  26  to provide a “bypass path” for current to flow directly from the supply voltage  20  to the second μC charge pump output  26 . The seventeenth switch  106 , (SW 17), may include a seventeenth switch control input configured to receive the seventeenth switch control signal  140  from the multiple output μC charge pump control circuit  72 D. The multiple output μC charge pump control circuit  72 D may configure the seventeenth switch control signal  140  to operably open and close the seventeenth switch  106 , (SW 17), based upon the various modes of operation of the dual output μC charge pump circuit  12 D. 
         [0259]    Accordingly, as an example advantage, when the multiple output μC charge pump control circuit  72 D configures the sixteenth switch control signal  138  to operably open the sixteenth switch  104 , (SW 16), and the seventeenth switch control signal  140  to operably open the seventeenth switch  106 , (SW 17), controller  14  may configure the dual output μC charge pump circuit  12 D to operate similarly to the operational modes previously described with respect to dual output μC charge pump circuit  12 A in TABLES 1A, 1B-1, 1B-2, 2A-1, 2A-2, 2B-1A, 2B-1B, 2B-2A, 2B-2B, 3A-1, 3A-2, 3B-1A, 3B-1B, 3B-2A, and 3B-2B and depicted in  FIGS. 3A through 25B . 
         [0260]    Otherwise, advantageously, the dual output μC charge pump circuit  12 D may configure the multiple output μC charge pump control circuit  72 D to operate in various bypass modes of operation. 
         [0261]    As an example of one of the various bypass modes of operation of the dual output μC charge pump circuit  12 D, unlike the dual output μC charge pump circuit  12 A, the controller  14  may advantageously configure the dual output μC charge pump circuit  12 D to operate in a first μC charge pump output bypass mode of operation. The controller  14  may configure the multiple output μC charge pump control circuit  72 D to operate in a first μC charge pump output bypass mode of operation by configuring the multiple output μC charge pump control circuit  72 D to operably close the sixteenth switch  104 , (SW 16), while also opening the second switch  76 , (SW 2), the fourth switch  80 , (SW 4), the seventh switch  86 , (SW 7), and ninth switch  90 , (SW 9). As a result, the first μC charge pump output  24  is operably coupled to the supply voltage  20  and disconnected from both the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ). When the multiple output μC charge pump control circuit  72 D is configured to operate in a first μC charge pump output bypass mode of operation, the multiple output μC charge pump control circuit  72 D may operably change the switch state (open or closed) of the first switch  74 , (SW 1), the third switch  78 , (SW 3), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the eighth switch  88 , (SW 8), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), the fifteenth switch  102 , (SW 15), and the seventeenth switch  106 , (SW 17), to generate a desired buck or boost voltage level on the second μC charge pump output  26  in a fashion similar to the previously described operations of the dual output μC charge pump circuit  12 A of  FIG. 2A . 
         [0262]    Notably, because the sixteenth switch  104 , (SW 16), is operably closed when the controller  14  configures the multiple output μC charge pump control circuit  72 D to operate in a first μC charge pump output bypass mode of operation, the first μC charge pump output  24  may be directly coupled to the supply voltage  20  during all phases of operation of the dual output μC charge pump circuit  12 D. As a result, when the multiple output μC charge pump control circuit  72 D is configured to operate in a first μC charge pump output bypass mode of operation, the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), may be continuously charged from the supply voltage  20  during all phases of operation of the dual output μC charge pump circuit  12 D. Accordingly, the phases of operation dedicated to transferring charge from the supply voltage  20 , first flying capacitor  42 , (C FLY1 ), the second flying capacitor  44 , (C FLY2 ), or a combination thereof, to the first μC charge pump output capacitor  46 , (C μC     —     OUT1 ), may be omitted. 
         [0263]    As another example of one of the various bypass modes of operation of the dual output μC charge pump circuit  12 D, unlike the dual output μC charge pump circuit  12 A, the controller  14  may advantageously configure the dual output μC charge pump circuit  12 D to operate in a second μC charge pump output bypass mode of operation. The controller  14  may configure the multiple output μC charge pump control circuit  72 D to operate in a second μC charge pump output bypass mode of operation by configuring the multiple output μC charge pump control circuit  72 D to operably close the seventeenth switch  106 , (SW 17), while operably opening the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), and the fourteenth switch  100 , (SW 14). As a result, the second μC charge pump output  26  is operably coupled to the supply voltage  20  and disconnected from both the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ). Because the second μC charge pump output  26  is operably disconnected from both the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ), the multiple output μC charge pump control circuit  72 D is free to change the switch state (open or closed) of the first switch  74 , (SW 1), the third switch  78 , (SW 3), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the eighth switch  88 , (SW 8), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the fifteenth switch  102 , (SW 15), and the sixteenth switch  104 , (SW 16), to generate a desired buck or boost voltage level on the first μC charge pump output  24  in a fashion similar to the previously described operations of the dual output μC charge pump circuit  12 A of  FIG. 2A . 
         [0264]    Also notably, because the seventeenth switch  106 , (SW 17), is operably closed when the controller  14  configures the multiple output μC charge pump control circuit  72 D to operate in a second μC charge pump output bypass mode of operation, the second μC charge pump output  26  may be directly coupled to the supply voltage  20  during all phases of operation of the dual output μC charge pump circuit  12 D. As a result, when the multiple output μC charge pump control circuit  72 D is configured to operate in a first μC charge pump output bypass mode of operation, the second μC charge pump output capacitor  48 , (C μC     —     OUT2 ), may be continuously charged from the supply voltage  20  during all phases of operation of the dual output μC charge pump circuit  12 D. Accordingly, the phases of operation dedicated to transferring charge from the supply voltage  20 , first flying capacitor  42 , (C FLY1 ), the second flying capacitor  44 , (C FLY2 ), or a combination thereof, to the second μC charge pump output capacitor  48 , (C μC-     —     OUT2 ), may be omitted. 
         [0265]    As another example of one of the various bypass modes of operation of the dual output μC charge pump circuit  12 D, unlike the dual output μC charge pump circuit  12 A, the controller  14  may advantageously configure the dual output μC charge pump circuit  12 D to simultaneously operate in both the first μC charge pump output bypass mode of operation and the second μC charge pump output bypass mode of operation, which may also be referred to as a Bypass/Bypass Mode of operation. To configure the dual output μC charge pump circuit  12 D to operate in Bypass/Bypass Mode of operation, the controller  14  may configure the multiple output μC charge pump control circuit  72 D to simultaneously close both the sixteenth switch  104 , (SW 16), and the seventeenth switch  106 , (SW 17), while operably opening the first switch  74 , (SW 1), the second switch  76 , (SW 2), the third switch  78 , (SW 3), the fourth switch  80 , (SW 4), the fifth switch  82 , (SW 5), the sixth switch  84 , (SW 6), the seventh switch  86 , (SW 7), the eighth switch  88 , (SW 8), the ninth switch  90 , (SW 9), the tenth switch  92 , (SW 10), the eleventh switch  94 , (SW 11), the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the fifteenth switch  102 , (SW 15) of the dual output μC charge pump switch matrix circuit  70 D. When the dual output μC charge pump circuit  12 D is set to operate in Bypass/Bypass Mode of operation, both the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ), are decoupled, respectively, from the first μC charge pump output  24  and the second μC charge pump output  26 . As a result, the first μC charge pump output voltage, (V μC     —     OUT1 ), provided on the first μC charge pump output  24  and the second μC charge pump output voltage, (V μC     —     OUT2 ), provided on the second μC charge pump output  26  are substantially equal to the voltage level present on the supply voltage  20 . As an example, if the supply voltage  20  is provided by the battery  22 , the first μC charge pump output voltage, (V μC     —     OUT1 ), and the second μC charge pump output voltage, (V μC     —     OUT2 ), will be substantially equal to the battery voltage, (V BAT ). 
         [0266]    As discussed above, the dual output μC charge pump circuit  12 D may configure the multiple output μC charge pump control circuit  72 D to operate in various bypass modes of operation. Various, non-limiting, examples of first μC charge pump output bypass modes of operation of the dual output μC charge pump circuit  12 D are described in TABLE 4A. Example first μC charge pump output bypass modes described in TABLE 4A include: a First Bypass/Buck Mode, a Second Bypass/Buck Mode, a Third Bypass/Buck Mode, a Fourth Bypass/Buck Mode, a Fifth Bypass/Buck Mode, a Sixth Bypass/Buck Mode, a Seventh Bypass/Buck Mode, an Eighth Bypass/Buck Mode, a Ninth Bypass/Buck Mode, a Tenth Bypass/Buck Mode, a First Bypass/Boost Mode, a Second Bypass/Boost Mode, a Third Bypass/Boost Mode, a Fourth Bypass/Boost Mode, and a Fifth Bypass/Boost Mode. 
         [0267]    Additional, non-limiting, examples of second μC charge pump output bypass modes of operation of the dual output μC charge pump circuit  12 D are described in TABLE 4B. Example second μC charge pump output bypass modes described in TABLE 4B include: a First Buck/Bypass Mode, a Second Buck/Bypass Mode, a Third Buck/Bypass Mode, a Fourth Buck/Bypass Mode, a Fifth Buck/Bypass Mode, a Sixth Buck/Bypass Mode, a Seventh Buck/Bypass Mode, an Eighth Buck/Bypass Mode, a Ninth Buck/Bypass Mode, a Tenth Buck/Bypass Mode, a First Boost/Bypass Mode, a Second Boost/Bypass Mode, a Third Boost/Bypass Mode, a Fourth Boost/Bypass Mode, and a Fifth Boost/Bypass Mode. 
         [0268]    Accordingly, as described in TABLE 4A, in the First Bypass/Buck Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/4 to generate a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/4×V BAT  on the second μC charge pump output  26  and operate in the first μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/4×V BAT . In the Second Bypass/Buck Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/3 to generate a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/3×V BAT  on the second μC charge pump output  26  and operate in the first μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/3×V BAT . In the Third Bypass/Buck Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/2 to generate a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/2×V BAT  on the second μC charge pump output  26  and operate in a first μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/2×V BAT . In the Fourth Bypass/Buck Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 2/3 to generate a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 2/3×V BAT  on the second μC charge pump output  26  and operate in the first μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 2/3×V BAT . In the Fifth Bypass/Buck Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 3/4 to generate a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT  on the second μC charge pump output  26  and operate in the first μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT . In the Sixth Bypass/Buck Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/4 to generate a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT  on the second μC charge pump output  26  and operate in the first μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/4×V BAT . In the Seventh Bypass/Buck Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/3 to generate a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 2/3×V BAT  on the second μC charge pump output  26  and operate in the first μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 2/3×V BAT . In the Eighth Bypass/Buck Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/2 to generate a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/2×V BAT  on the second μC charge pump output  26  and operate in the first μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/2×V BAT . In the Ninth Bypass/Buck Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 2/3 to generate a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/3×V BAT  on the second μC charge pump output  26  and operate in the first μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/3×V BAT . In the Tenth Bypass/Buck Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 3/4 to generate a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/4×V BAT  on the second μC charge pump output  26  and operate in the first μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 1/4×V BAT . In the First Bypass/Boost Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/4 to generate a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/4×V BAT  on the second μC charge pump output  26  and operate in the first μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/4×V BAT . In the Second Bypass/Boost Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/3 to generate a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 4/3×V BAT  on the second μC charge pump output  26  and operate in the first μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 4/3×V BAT . In the Third Bypass/Boost Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/2 to generate a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/2×V BAT  on the second μC charge pump output  26  and operate in a first μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 3/2×V BAT . In the Fourth Bypass/Boost Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 2/3 to generate a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/3×V BAT  on the second μC charge pump output  26  and operate in the first μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 5/3×V BAT . In the Fifth Bypass/Boost Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 3/4 to generate a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 7/4×V BAT  on the second μC charge pump output  26  and operate in the first μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to 7/4×V BAT . 
         [0269]    Accordingly, as described in TABLE 4B, in the First Buck/Bypass Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/4 to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/4×V BAT  on the first μC charge pump output  24  and operate in the second μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/4×V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In the Second Buck/Bypass Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/3 to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/3×V BAT  on the first μC charge pump output  24  and operate in the second μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/3×V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In the Third Buck/Bypass Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/2 to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/2×V BAT  on the first μC charge pump output  24  and operate in the second μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/2×V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In the Fourth Buck/Bypass Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 2/3 to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 2/3×V BAT  on the first μC charge pump output  24  and operate in the second μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 2/3×V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In the Fifth Buck/Bypass Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 3/4 to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/4×V BAT  on the first μC charge pump output  24  and operate in the second μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/4×V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In the Sixth Buck/Bypass Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/4 to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/4×V BAT  on the first μC charge pump output  24  and operate in the second μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/4×V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In the Seventh Buck/Bypass Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/3 to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 2/3×V BAT  on the first μC charge pump output  24  and operate in the second μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 2/3×V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In the Eighth Buck/Bypass Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/2 to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/2×V BAT  on the first μC charge pump output  24  and operate in the second μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/2×V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In the Ninth Buck/Bypass Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 2/3 to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/3×V BAT  on the first μC charge pump output  24  and operate in the second μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/3×V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In the Tenth Buck/Bypass Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 3/4 to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/4×V BAT  on the first μC charge pump output  24  and operate in the second μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 1/4×V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In the First Boost/Bypass Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/4 to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/4×V BAT  on the first μC charge pump output  24  and operate in the second μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/4×V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In the Second Boost/Bypass Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/3 to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 4/3×V BAT  on the first μC charge pump output  24  and operate in the second μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 4/3×V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In the Third Boost/Bypass Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 1/2 to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/2×V BAT  on the first μC charge pump output  24  and operate in the second μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 3/2×V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In the Fourth Boost/Bypass Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 2/3 to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/3×V BAT  on the first μC charge pump output  24  and operate in the second μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 5/3×V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In the Fifth Boost/Bypass Mode of operation of the dual output μC charge pump circuit  12 D, the controller  14  configures the multiple output μC charge pump control circuit  72 D to use an operational ratio, (xμBB RATIO ), set to 3/4 to generate a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 7/4×V BAT  on the first μC charge pump output  24  and operate in the second μC charge pump output bypass mode. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to 7/4×V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In the Bypass/Bypass Mode of operation, the controller  14  configures the multiple output μC charge pump control circuit  72 D to directly couple both the first μC charge pump output  24  and the second μC charge pump output  26  to the supply voltage. As a result, the first μC charge pump output  24  generates a first μC charge pump output voltage, (V μC     —     OUT1 ), substantially equal to V BAT  and the second μC charge pump output  26  generates a second μC charge pump output voltage, (V μC     —     OUT2 ), substantially equal to V BAT . In addition, as discussed above relative to the embodiments of the dual output μC charge pump circuit  12 , depicted in  FIG. 1A , the dual output μC charge pump circuit  12 A, depicted in  FIG. 2A , and the dual output μC charge pump circuit  12 B, depicted in  FIG. 2B , and embodiments of dual output μC charge pump circuit  12 C, depicted in  FIG. 2C , some embodiments of dual output μC charge pump circuit  12 D, depicted in  FIG. 2   d , may include and use more than two flying capactiors to generate the first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  and the second μC charge pump output voltage, (V μC     —     OUT2 ), on the second μC charge pump output  26 . However, advantageously, as depicted in  FIG. 2D , and previously described with respect to the various modes of operation of the dual output μC charge pump circuit  12 , depicted in  FIG. 1A , the dual output μC charge pump circuit  12 A, depicted in  FIG. 2A , and the dual output μC charge pump circuit  12 B, depicted in  FIG. 2B , and the embodiments of dual output μC charge pump circuit  12 C, depicted in  FIG. 2C , some embodiments of the dual output μC charge pump circuit  12 D may be configured to generate the desired output voltage levels, namely the first μC charge pump output voltage, (V μC     —     OUT1 ), on the first μC charge pump output  24  and the second μC charge pump output voltage, (V μ C   —     OUT2), on the second μC charge pump output 26, using only the first flying capacitor 42, (C   FLY1 ), and the second flying capacitor  44 , (C FLY2 ). In other words, some embodiments of the dual output μC charge pump circuit  12 D may be configured to generate the variously described output voltage levels corresponding to a “buck/buck mode” of operation, a “buck/boost mode” of operation, and/or a “boost/buck mode” of operation using only the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ). It may be appreciated that those embodiments of the dual output μC charge pump circuit  12 D that only use the first flying capacitor  42 , (C FLY1 ), and the second flying capacitor  44 , (C FLY2 ), to generate the desired output voltage levels on the first μC charge pump output  24  and the second μC charge pump output  26  may provide improved technical performance due to reduced complexity and reduced response time verses those embodiments of the dual output μC charge pump circuit that include more than two flying capacitors. 
         [0000]    
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 4A 
               
             
             
               
                   
               
               
                 FIRST μC CHARGE PUMP OUTPUT BYPASS MODES OF OPERATION 
               
               
                 TABLE FOR A DUAL OUTPUT μC CHARGE PUMP CIRCUIT 
               
             
          
           
               
                   
                   
                 FIRST μC CHARGE 
                   
               
               
                 FIRST μC CHARGE PUMP 
                   
                 PUMP OUTPUT, 
                 SECOND μC CHARGE 
               
               
                 OUTPUT BYPASS MODE OF 
                 OPERATIONAL 
                 (V μC     —     OUT1 ), 
                 PUMP OUTPUT, 
               
               
                 OPERATION 
                 RATIOS, (xμBB RATIO ) 
                 V μC     —     OUT1  = V BAT   
                 (V μC     —     OUT2 ) 
               
               
                   
               
               
                 First Bypass/Buck Mode 
                 1/4 
                 V BAT   
                 1/4 × V BAT   
               
               
                 Second Bypass/Buck Mode 
                 1/3 
                 V BAT   
                 1/3 × V BAT   
               
               
                 Third Bypass/Buck Mode 
                 1/2 
                 V BAT   
                 1/2 × V BAT   
               
               
                 Fourth Bypass/Buck Mode 
                 2/3 
                 V BAT   
                 2/3 × V BAT   
               
               
                 Fifth Bypass/Buck Mode 
                 3/4 
                 V BAT   
                 3/4 × V BAT   
               
               
                 Sixth Bypass/Buck Mode 
                 1/4 
                 V BAT   
                 3/4 × V BAT   
               
               
                 Seventh Bypass/Buck Mode 
                 1/3 
                 V BAT   
                 2/3 × V BAT   
               
               
                 Eighth Bypass/Buck Mode 
                 1/2 
                 V BAT   
                 1/2 × V BAT   
               
               
                 Ninth Bypass/Buck Mode 
                 2/3 
                 V BAT   
                 1/3 × V BAT   
               
               
                 Tenth Bypass/Buck Mode 
                 3/4 
                 V BAT   
                 1/4 × V BAT   
               
               
                 First Bypass/Boost Mode 
                 1/4 
                 V BAT   
                 5/4 × V BAT   
               
               
                 Second Bypass/Boost Mode 
                 1/3 
                 V BAT   
                 4/3 × V BAT   
               
               
                 Third Bypass/Boost Mode 
                 1/2 
                 V BAT   
                 3/2 × V BAT   
               
               
                 Fourth Bypass/Boost Mode 
                 2/3 
                 V BAT   
                 5/3 × V BAT   
               
               
                 Fifth Bypass/Boost Mode 
                 3/4 
                 V BAT   
                 7/4 × V BAT   
               
               
                   
               
             
          
         
       
     
         [0000]    
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 4B 
               
             
             
               
                   
               
               
                 SECOND μC CHARGE PUMP OUTPUT BYPASS MODES OF OPERATION 
               
               
                 TABLE FOR A DUAL OUTPUT μC CHARGE PUMP CIRCUIT 
               
             
          
           
               
                   
                   
                   
                 SECOND μC CHARGE 
               
               
                 SECOND μC CHARGE PUMP 
                   
                 FIRST μC CHARGE 
                 PUMP OUTPUT, 
               
               
                 OUTPUT BYPASS MODE OF 
                 OPERATIONAL 
                 PUMP OUTPUT, 
                 (V μC     —     OUT2 ), 
               
               
                 OPERATION 
                 RATIOS, (xμBB RATIO ) 
                 (V μC     —     OUT1 ) 
                 V μC     —     OUT2  = V BAT   
               
               
                   
               
               
                 First Buck/Bypass Mode 
                 1/4 
                 1/4 × V BAT   
                 V BAT   
               
               
                 Second Buck/Bypass Mode 
                 1/3 
                 1/3 × V BAT   
                 V BAT   
               
               
                 Third Buck/Bypass Mode 
                 1/2 
                 1/2 × V BAT   
                 V BAT   
               
               
                 Fourth Buck/Bypass Mode 
                 2/3 
                 2/3 × V BAT   
                 V BAT   
               
               
                 Fifth Buck/Bypass Mode 
                 3/4 
                 3/4 × V BAT   
                 V BAT   
               
               
                 Sixth Buck/Bypass Mode 
                 1/4 
                 3/4 × V BAT   
                 V BAT   
               
               
                 Seventh Buck/Bypass Mode 
                 1/3 
                 2/3 × V BAT   
                 V BAT   
               
               
                 Eighth Buck/Bypass Mode 
                 1/2 
                 1/2 × V BAT   
                 V BAT   
               
               
                 Ninth Buck/Bypass Mode 
                 2/3 
                 1/3 × V BAT   
                 V BAT   
               
               
                 Tenth Buck/Bypass Mode 
                 3/4 
                 1/4 × V BAT   
                 V BAT   
               
               
                 First Boost/Bypass Mode 
                 1/4 
                 5/4 × V BAT   
                 V BAT   
               
               
                 Second Boost/Bypass Mode 
                 1/3 
                 4/3 × V BAT   
                 V BAT   
               
               
                 Third Boost/Bypass Mode 
                 1/2 
                 3/2 × V BAT   
                 V BAT   
               
               
                 Fourth Boost/Bypass Mode 
                 2/3 
                 5/3 × V BAT   
                 V BAT   
               
               
                 Fifth Boost/Bypass Mode 
                 3/4 
                 7/4 × V BAT   
                 V BAT   
               
               
                 Bypass/Bypass Mode 
                 N/A 
                 V BAT   
                 V BAT   
               
               
                   
               
             
          
         
       
     
         [0270]    Returning briefly to  FIG. 1A , in some operational modes of the multiple output μC charge pump system  10 A, the dual output μC charge pump circuit  12  may be configured to provide various “floating” modes of operation, as depicted in TABLE 5. 
         [0000]    
       
         
               
             
               
               
               
             
           
               
                 TABLE 5 
               
             
             
               
                   
               
               
                 FLOATING MODES OF OPERATION FOR 
               
               
                 A MULTIPLE OUTPUT μC CHARGE PUMP 
               
             
          
           
               
                   
                 First Multiple Output μC 
                 Second Multiple Output μC 
               
               
                 MODES OF 
                 CHARGE PUMP OUTPUT, 
                 CHARGE PUMP OUTPUT, 
               
               
                 OPERATION 
                 (V μC     —     OUT1 ) 
                 (V μC     —     OUT2 ) 
               
               
                   
               
               
                 OFF Mode 
                 V μC     —     OUT1  = FLOATING 
                 V μC     —     OUT2  = FLOATING 
               
               
                 1 st  Floating Mode 
                 V μC     —     OUT1  = FLOATING 
                 Permissible Modes of 
               
               
                   
                   
                 Operation 
               
               
                 2 nd  Floating Mode 
                 Permissible Mode of 
                 V μC     —     OUT2  = FLOATING 
               
               
                   
                 Operation 
               
               
                   
               
             
          
         
       
     
         [0271]    Referring to the various example embodiments of the dual output μC charge pump circuit  12  of  FIG. 1A , depicted in  FIGS. 2A ,  2 B, and  2 C, first μC charge pump output  24  of the dual output μC charge pump circuit  12 A, the dual output μC charge pump circuit  12 B, and the dual output μC charge pump circuit  12 C may be placed in a float mode of operation by configuring the second switch  76 , (SW 2), the fourth switch  80 , (SW 4), the seventh switch  86 , (SW 7), and the ninth switch  90 , (SW 9), to remain operably open in all the modes of operation of the respective embodiments of the dual output μC charge pump circuit  12 A, first μC charge pump output  24  of the dual output μC charge pump circuit  12 B, and the dual output μC charge pump circuit  12 C. 
         [0272]    In the case of the embodiment of the dual output μC charge pump circuit  12  of  FIG. 1A  is the dual output μC charge pump circuit  12 D, depicted in  FIG. 2D , first μC charge pump output  24  of the dual output μC charge pump circuit  12 D may be placed in a float mode of operation by configuring the second switch  76 , (SW 2), the fourth switch  80 , (SW 4), the seventh switch  86 , (SW 7), the ninth switch  90 , (SW 9), and the sixteenth switch  104 , (SW 16) to remain operably open in all the permissible modes of operation of the dual output μC charge pump circuit  12 D. 
         [0273]    In similar fashion, referring to the dual output μC charge pump circuit  12 A, depicted in  FIG. 2A , the second μC charge pump output  26  of the dual output μC charge pump circuit  12 A may placed in a float mode of operation by configuring the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), and the fourteenth switch  100 , (SW 14) to remain operably open in all the permissible modes of operation of the dual output μC charge pump circuit  12 A. 
         [0274]    In addition, referring to the dual output μC charge pump circuit  12 B, depicted in  FIG. 2B , the second μC charge pump output  26  of the dual output μC charge pump circuit  12 B may placed in a float mode of operation by configuring the thirteenth switch  98 , (SW 13) to remain operably open in all the permissible modes of operation of the dual output μC charge pump circuit  12 B. 
         [0275]    Similarly, referring to the dual output μC charge pump circuit  12 C, depicted in  FIG. 2C , the second μC charge pump output  26  of the dual output μC charge pump circuit  12 C may placed in a float mode of operation by configuring the twelfth switch  96 , (SW 12), and the fourteenth switch  100 , (SW 14) to remain operably open in all the permissible modes of operation of the dual output μC charge pump circuit  12 C. 
         [0276]    Similarly, referring to the dual output μC charge pump circuit  12 D, depicted in  FIG. 2D , the second μC charge pump output  26  of the dual output μC charge pump circuit  12 D may placed in a float mode of operation by configuring the twelfth switch  96 , (SW 12), the thirteenth switch  98 , (SW 13), the fourteenth switch  100 , (SW 14), and the seventeenth switch  106 , (SW 17), to remain operably open in all the permissible modes of operation of the dual output μC charge pump circuit  12 D. 
         [0277]    Advantageously, the ability to independently and selectively place the first μC charge pump output  24 , the second μC charge pump output  26 , and/or a combination thereof, may permit the controller  14  to save battery power or conserve energy consumption by a device by powering down various portions of an integrated chip that include the multiple output μC charge pump system  10 A. As an additional benefit, the ability to independently and selectively place the first μC charge pump output  24 , the second μC charge pump output  26 , and/or a combination thereof in a floating mode of operation may provide integrated chip designers increased flexibility with respect to overall system configurations and re-configurations without impacting core system features. 
         [0278]      FIG. 1B  depicts a second embodiment of a multiple output μC charge pump system  10 B that is similar to the first embodiment of a multiple output μC charge pump system  10 A, which is depicted in  FIG. 1A . The multiple output μC charge pump system  10 B is operationally similar to the multiple output μC charge pump system  10 B. However, unlike the multiple output μC charge pump system  10 A, the multiple output μC charge pump system  10 B, depicted in  FIG. 1B , further includes a first bypass switch, (SW BYPASS1 ) coupled between the supply voltage  20  and the first μC charge pump output  24 . In addition, the multiple output μC charge pump system  10 B further includes a second bypass switch, (SW BYPASS2 ) coupled between the supply voltage  20  and the second μC charge pump output  26 . Also, as depicted in  FIG. 1B , the multiple output μC charge pump switch matrix and control circuit  40  is depicted as having a first bypass switch enable output coupled to a control input of the first bypass switch, (SW BYPASS1 ) and a second bypass switch enable output coupled to a control input of the second bypass switch, (SW BYPASS2 ). Accordingly, unlike the first embodiment of a multiple output μC charge pump system  10 A, depicted in  FIG. 1A , the second embodiment of the multiple output μC charge pump system  10 B depicted in  FIG. 1B  may be configured by controller  14 , via the control bus  16 , selectively couple the first μC charge pump output  24  to the supply voltage  20  and/or the second μC charge pump output  26  to the supply voltage  20 . 
         [0279]    It will be understood that prior to directly coupling the first μC charge pump output  24  to the supply voltage  20  and/or the second μC charge pump output  26  to the supply voltage  20 , the controller  14  configures the multiple output μC charge pump switch matrix and control circuit  40  to place the to be bypassed first μC charge pump output  24  or second μC charge pump output  26  into a floating modes of operation. Accordingly, in the case where one of the embodiments of the multiple output μC charge pump switch matrix and control circuit  40 , described above, does not inherently include a bypass mode the multiple output μC charge pump system  10 B may provide a bypass mode of operation. 
         [0280]    Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.