Abstract:
An integrated circuit with a frequency dividing test function includes a first frequency dividing circuit which divides a given frequency signal, a second frequency dividing circuit for dividing the output signal from the first frequency dividing circuit and a single terminal receptive of external test clock pulses. A test circuit is connected to the reset terminal for inhibiting the output signal from the first frequency dividing circuit when the external test clock pulses applied to the reset terminal have a higher frequency than the divided frequency of the first output signal and for applying the external clock pulses to the second frequency dividing circuit to test the second frequency dividing circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an integrated circuit with a frequency dividing test function. 
     2. Description of the Related Art 
     For example, in an integrated circuit for a crystal clock, high accuracy and reliability are essential. Therefore, it is necessary to test the integrated circuit one by one during manufacture in order to check whether the frequency dividing circuit operates normally or not and the time required for such test has been a large problem. 
     In a prior art circuit shown in FIG. 4, a test terminal has been provided on an integrated circuit in order to execute this test and the test has been carried out by supplying a high speed external clock pulse for test through gate G to the intermediate stage D 2  of the frequency dividing circuit from such terminal and view the outputs O 1 , 0 2  of the driver. Since the dividing circuit D 1  before such intermediate stage D 2  normally receives an oscillator output, it must be halted during the test, and thus a stop terminal must also be provided in addition to said test terminal. 
     SUMMARY OF THE INVENTION 
     As described previously, the test and stop terminals have been required in the prior art and this has resulted in an increase in size of the chip and the cost of the integrated circuit. 
     The present invention eliminates disadvantages of the prior art by providing an integrated circuit with the frequency dividing function which has been realized with providing only one terminal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a logical circuit diagram representing an embodiment of the present invention; 
     FIG. 2 and FIG. 3 are timecharts for explaining the operations in FIG. 1; and 
     FIG. 4 is a circuit diagram of a prior art test circuit 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1, the reference numeral 1 represents an oscillator; 2, 3, 4, frequency dividing stages which operate at the falling edge of a pulse; 5, a motor drive circuit; 6, 7, flip-flop circuits which operate respectively at the rising and falling edges of a pulse; 8 , 9, 10, gate circuits; 11, a reset terminal. 
     In normal operation mode, the reset terminal 11 is held at &#34;0&#34;, therefore the output R 1  of the gate circuit 8 is held at &#34;0&#34; and the dividing circuit 2 is kept operative, that is, the output pulses from it pass through the gate circuit 10 and are then supplied to the dividing circuit 3. Output pulses F 2  from the driving circuit 3 are supplied to the flip-floP circuits 6 and 7. Output Q of the flip-flop circuit 6 is held &#34;0&#34; because signal R is at &#34;0&#34; and the output Q is held &#34;1&#34;, since the D input is at &#34;0&#34;. Accordingly, the outputs of the gate circuits 8, 9 are at &#34;0&#34;, so dividing circuits 2, 4 are kept operative. Motor drive pulses 0 1 , 0 2  of FIG. 2 are generated from the motor drive circuit 5. The reset operation of the frequency dividing stages is now explained. In this case, the reset terminal 11 is held at &#34;1&#34;  as illustrated in FIG. 2R. Thereby, one input of the AND gate circuit 8 and the D input of the flip-flop circuit 6 are set to &#34;1&#34; and soon thereafter the output of the frequency dividing stage 3 falls as shown in F 2  of FIG. 2. The output Q of the flip-flop circuit 6 then turns to &#34;1&#34;. Since the output Q of flip-flop 7 is &#34;1&#34;, the outputs of the AND gate circuits 8, 9 are respectively changed to &#34;1&#34; as illustrated in FIGS. 2 R 1   1 , R 2  and thereby the frequency dividing stages 2, 4 are reset. 
     The dividing stage 3 is therefore held in the reset state where output is all &#34;0&#34;. 
     While the reset terminal 11 is thus held at &#34;1&#34;, the frequency dividing stages 2, 3, 4 are held in the reset state. 
     Such reset state can be released when the reset terminal 11 is turned to &#34;0&#34;. At this time, the output of the AND gate circuit 8 turns to &#34;0&#34; as illustrated in R 1  of FIG. 2, releasing the reset state of dividing stage 2. Thereafter, when the output of the dividing stage 3 rises as illustrated in F 2  in FIG. 2, the flip-flop circuit 7 is triggered, resulting in the output Q changing to the &#34;0&#34; state and thereby switching gate 9 so that R 2  is &#34;0&#34; and the counting state of dividing stage 4 is released. As a result, the drive pulses 0 1 , and 0 2  of FIG. 2 are generated from the drive circuit 5 alternately every other one second. 
     The test operation is now explained. In this case, the reset terminal 11 is once again set to &#34;1&#34; for attaining the reset state as described previously. Thereafter, a high test clock pulse is externally input as shown in R of FIG. 3, to the reset terminal 11. The pulse width of the &#34;0&#34; portion of such clock pulse is set to be shorter than 1/2 the width of output pulse sent from the frequency dividing stage 2. This clock pulse continues to reset the dividing stage 2. Since the pulse width of said clock pulse is set shorter than 1/2 the width of the output pulse from the dividing stage 2, the frequency dividing stage 2 is reset before the generation of output in spite of the period of this clock pulse and the output F 1  does not provide a pulse to NOR gate 10. Gate 10 passes test clock pulses R 1  to dividing stage 3. 
     The test clock pulse is level-inverted by the gate circuit 10 and is then supplied to the frequency dividing stage 3, causing it to operate at the falling edge. When said clock pulses are supplied in a specified number, the output of the dividing stage 3 rises as shown in F 2  of FIG. 3 and the flip-flop circuit 7 is triggered inverting the output Q to &#34;0&#34;. Accordingly, the output of the gate circuit 9 is inverted to &#34;0&#34; like R in FIG. 3 and the reset state of dividing stage 4 is released. The frequency dividing stages 3, 4 are thus operated at a high speed by said test clock pulse and are tested by the output of drive circuit 5. 
     Here, the flip-flop circuit 6 is triggered by the falling edge of pulse sent from the frequency dividing stage 3, but the D input thereof is synchronized with the output pulse of dividing stage 3. Therefore, the D input of the flip-flop circuit 6 is certainly set to &#34;1&#34; when the output pulse of dividing stage 3 falls. Accordingly, output Q of flip-flop circuit 6 is kept at &#34;1&#34;. 
     The present invention can be applied to a device providing a frequency dividing circuit which divides a standard reference frequency, as well as to an integrated circuit for a clock. 
     According to the present invention, the test of frequency dividing stages can be carried out by supplying external clock pulses to only one terminal. Therefore, the chip area of an integrated circuit can be made small and a cost reduction can be realized. Moreover, since the clock pulses for the test are supplied to the intermediate stage of a frequency dividing circuit, the test period can be curtailed and in this sense the present invention is more effective when it is applied to the test of a large amount of integrated circuits. 
     Further, a reset terminal is used as the test terminal, and it is no longer necessary to provide a separate test terminal.