Abstract:
The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of Korean Patent Application No. 10-2014-0121271, filed on Sep. 12, 2014, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
       BACKGROUND 
       [0002]    The inventive concepts relate to a semiconductor memory device, and more particularly, to a memory device and a memory system capable of quickly repairing a fail cell by copying and storing fail cell information in a memory cell. 
         [0003]    A memory capacity of memory devices is increasing with the development of manufacturing process technologies. However, progress with respect to microfabrication process technology has resulted in an increase in the number of “fail” memory cells. If the number of fail cells increases, not only it is difficult to guarantee a memory capacity, but also memory device production yield decreases. In order to increase the memory device yield, information about a fail cell may be stored in a nonvolatile memory device, such as an anti-fuse, and a fail cell may be repaired by using the fail cell information stored in the anti-fuse. However, it takes a long time to read the fail cell information from the anti-fuse. Thus, an operation delay of the memory device occurs while repairing the fail cell. Accordingly, a method of reducing a delay that occurs while repairing a fail cell is desired. 
       SUMMARY 
       [0004]    At least one embodiment relates to a memory device. 
         [0005]    In one embodiment, the memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform a recovery operation if the control logic determines to perform the recovery operation. 
         [0006]    In one embodiment, the control logic is configured to transfer only fail cell column address information in the fail cell information as the portion of the fail cell information to the second region. The fail cell column address information indicates column addresses of the identified failed cells. 
         [0007]    In one embodiment, the control logic is configured to access the fail cell column address information from the second region using a row address in the address information in the access request. 
         [0008]    In one embodiment, the fail cell column address information further includes flag information, and the flag information indicates whether the row address accesses one of the identified failed cells. 
         [0009]    In one embodiment, the fail cell column address information further includes order information, and the order information indicates which data associated with the column addresses is associated with the identified failed cells. 
         [0010]    In one embodiment, the fail cell column address information further includes flag information, and the flag information indicates whether the fail cell column address information is valid. 
         [0011]    In one embodiment, the fail cell column address information further includes parity information, and the parity information is for correcting errors in the fail cell column address information. 
         [0012]    In one embodiment, the fail cell column address information further includes recovery mode information respectively indicating which one of at least two recovery operations to perform for each of the column addresses. 
         [0013]    In one embodiment, the second region is divided into a plurality of blocks, and the control logic is configured to transfer the fail cell column address information to the second region such that at least two of the plurality of blocks collectively store the fail cell column address information for one of the identified failed cells. 
         [0014]    In one embodiment, the first region is divided into a plurality of first blocks; the second region is divided into a plurality of second blocks; and each of the plurality of second blocks shares a data line with a respective one of the plurality of first blocks. 
         [0015]    In one embodiment, the access request is a write request, the recovery circuit is configured to obtain the recovery information based on data to be written if the control logic determines to perform the recovery operation, and the memory device is configured to store the recovery information in the third region as part of the recovery operation. 
         [0016]    In one embodiment, the recovery operation is an error correction operation and the recovery information includes parity bits. 
         [0017]    In one embodiment, the recovery operation is a data replacement operation and the recovery information includes data to use as a replacement for the data in the identified failed cells. 
         [0018]    In one embodiment, the access request is a read request, the memory device is configured to read the recovery information if the control logic determines to perform the recovery operation, and the recovery circuit is configured to perform the recovery operation based on the read recovery information. 
         [0019]    In one embodiment, the recovery operation is an error correction operation and the recovery information includes parity bits. 
         [0020]    In one embodiment, the recovery circuit includes an error correction coding circuit configured to error correct code data output at a same time across a plurality of data lines. 
         [0021]    In one embodiment, the recovery operation is a data replacement operation and the recovery information includes data to use as a replacement for the data in the identified failed cells. 
         [0022]    In one embodiment, the recovery circuit is configured to perform an error correction operation as the recovery operation such that the recovery information includes parity bits, and the recovery circuit is configured to perform a data replacement operation as the recovery operation such that the recovery information includes data to use as a replacement for the data in the failed cell. The control logic is configured to control the recovery circuit to perform one of the error correction operation and the data replacement operation as the recovery operation for each of the column addresses based on mode information associated with each of the column addresses. 
         [0023]    In another embodiment, the memory device includes a memory array and a control logic configured to store fail cell information, the fail cell information identifying failed cells in the memory array. The control logic is configured to transfer only fail cell column address information in the fail cell information to the memory array. The fail cell column address information indicates column addresses of the identified failed cells. The control logic is configured to determine whether to perform a recovery operation based on address information in an access request and the fail cell column address information stored in the memory array, and the access request is a request to access the memory array. A recovery circuit is configured to perform the recovery operation if the control logic determines to perform the recovery operation. 
         [0024]    In one embodiment, the control logic is configured to access the fail cell column address information from the memory array using a row address in the address information in the access request. 
         [0025]    In one embodiment, the fail cell column address information further includes flag information, the flag information indicating whether the row address accesses one of the identified failed cells. 
         [0026]    In one embodiment, the fail cell column address information further includes order information, and the order information indicates which data associated with the column addresses is associated with the identified failed cells. 
         [0027]    In one embodiment, the fail cell column address information further includes flag information, the flag information indicating whether the fail cell column address information is valid. 
         [0028]    In one embodiment, the fail cell column address information further includes parity information, and the parity information is for correcting errors in the fail cell column address information. 
         [0029]    In one embodiment, the fail cell column address information further includes recovery mode information respectively indicating which one of at least two recovery operations to perform for each of the column addresses. 
         [0030]    In one embodiment, the recovery operation is an error correction operation. 
         [0031]    In one embodiment, the recovery operation is a data replacement operation. 
         [0032]    At least one embodiment relates to a method. 
         [0033]    In one embodiment, the method includes storing fail cell information in memory. The fail cell information identifies failed cells in the first region. The method further includes transferring a portion of the fail cell information to a first region of a memory array; determining whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the first region, and the access request being a request to access a second region of the memory array; and performing a recovery operation if the determining determines to perform the recovery operation. 
         [0034]    In another embodiment, the method includes storing fail cell information in a memory, the fail cell information identifying failed cells in a memory array; and transferring only fail cell column address information in the fail cell information to the memory array. The fail cell column address information indicates column addresses of the identified failed cells. The method further includes determining whether to perform a recovery operation based on address information in an access request and the fail cell column address information stored in the memory array. The access request is a request to access the memory array. The method still further includes performing the recovery operation if the control logic determines to perform the recovery operation. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0035]    Some example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0036]      FIG. 1  is a diagram of a memory device capable of quickly repairing a fail cell, according to an embodiment of the inventive concepts; 
           [0037]      FIG. 2  is a flowchart of a method of operating the memory device of  FIG. 1 ; 
           [0038]      FIGS. 3A through 3C  are diagrams for describing an X8 mode operation of the memory device of  FIG. 1 ; 
           [0039]      FIG. 4  is a diagram for describing an X4 mode operation of a memory device according to an embodiment of the inventive concepts; 
           [0040]      FIGS. 5A and 5B  are diagrams of a fail column select signal (FCS) cell array of the memory device of  FIG. 4 , according to some embodiments of the inventive concepts; 
           [0041]      FIGS. 6A and 6B  are diagrams for describing fail cell information stored in FCS cell blocks of  FIG. 5A ; 
           [0042]      FIG. 7  is a diagram of a data line structure in the memory device of  FIG. 5A ; 
           [0043]      FIGS. 8 and 9  are diagrams for describing a storage unit of  FIG. 1 ; 
           [0044]      FIG. 10  is a diagram for describing a comparator of  FIG. 1 ; 
           [0045]      FIG. 11  is a diagram for describing an error correction code (ECC) engine of  FIG. 1 ; 
           [0046]      FIG. 12  is a diagram for describing a first ECC engine of  FIG. 11 ; 
           [0047]      FIGS. 13A and 13B  are diagrams for describing an ECC encoding circuit and an ECC decoding circuit of  FIG. 12 ; 
           [0048]      FIG. 14  is a diagram of a memory device capable of quickly repairing a fail cell, according to another embodiment of the inventive concepts; 
           [0049]      FIG. 15  is a flowchart of a method of operating the memory device of  FIG. 14 ; 
           [0050]      FIGS. 16A and 16B  are diagrams for describing a data line repair (DLR) operation performed in units of a data line of the memory device of  FIG. 14 ; 
           [0051]      FIGS. 17A and 17B  are diagrams for describing a DLR operation in units of a bit line of the memory device of  FIG. 14 ; 
           [0052]      FIG. 18  is a diagram of a memory device capable of quickly repairing a fail cell, according to another embodiment of the inventive concepts; 
           [0053]      FIG. 19  is a block diagram of a mobile system to which a memory device capable of quickly repairing a fail cell is applied, according to an embodiment of the inventive concepts; and 
           [0054]      FIG. 20  is a block diagram of a computing system to which a memory device capable of quickly repairing a fail cell is applied, according to an embodiment of the inventive concepts. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0055]    Detailed example embodiments of the inventive concepts are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments of the inventive concepts. Example embodiments of the inventive concepts may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein. 
         [0056]    Accordingly, while example embodiments of the inventive concepts are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments of the inventive concepts to the particular forms disclosed, but to the contrary, example embodiments of the inventive concepts are to cover all modifications, equivalents, and alternatives falling within the scope of example embodiments of the inventive concepts. Like numbers refer to like elements throughout the description of the figures. 
         [0057]    It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. 
         [0058]    It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments. 
         [0059]    Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. 
         [0060]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0061]    Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments. 
         [0062]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly-used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. 
         [0063]    A memory capacity of semiconductor memory devices, such as a dynamic random access memory (DRAM), is increasing with the development of manufacturing process technologies. However, progress with respect to microfabrication process technology has resulted in an increase in the number of fail memory cells. In order to secure a better yield, fail memory cells may be repaired by being replaced with redundant memory cells or by using an error correction code (ECC) operation. 
         [0064]      FIG. 1  is a diagram of a memory device  100  capable of quickly repairing a fail cell, according to an embodiment of the inventive concepts. 
         [0065]    Referring to  FIG. 1 , the memory device  100  performs an ECC operation to repair a fail cell. The memory device  100  includes a memory cell array  110 , a control logic unit  120 , and an ECC engine  130 . 
         [0066]    The memory cell array  110  includes a plurality of memory cells arranged in rows and columns. In the memory cell array  110 , the rows include word lines accessed by a row decoder, and the columns include bit lines accessed by a column decoder. Memory cells connected to intersections of the word lines and bit lines may be DRAM cells. 
         [0067]    The memory cell array  110  may include a normal cell array  112 , a fail cell information storage cell array  114 , and an ECC cell array  116 . The normal cell array  112  is a memory block that determines a memory capacity of the memory device  100 . A fail cell indicated by  in  FIG. 1  may exist in the normal cell array  112 , from among memory cells connected in one row. Examples of the fail cell include a defective cell in terms of hardware and a cell showing deterioration in various device characteristics, for example, a cell having a short refresh time, a cell showing deterioration in a cell write characteristic, and a cell having a variable retention time. A row and a column connected to the fail cell may be addressed by a fail row address FRA and a fail column address FCA. 
         [0068]    The fail cell information storage cell array  114  is a memory block that copies and stores fail cell information stored in a storage unit  122  of the control logic unit  120 . The storage unit  122  may store the fail row address FRA and the fail column address FCA of the fail cell in the normal cell array  112 . The fail cell information storage cell array  114  may store the fail column address FCA in memory cells accessed by the fail row address FRA. 
         [0069]    The fail column address FCA may be generated according to a column select signal for selecting bit lines connected to the fail cell through the column decoder. The fail column address FCA stored in the fail cell information storage cell array  114  is a fail column select signal (FCS) for accessing the fail cell of the normal cell array  112 . Thus, the fail cell information storage cell array  114  may actually be a memory block that stores an FCS. For convenience of description, the fail cell information storage cell array  114  will now be referred to as the FCS cell array  114 . 
         [0070]    The FCS cell array  114  may copy and store the fail cell information including the fail column address FCA in the memory cells accessed by the fail row address FRA from the storage unit  122  of the control logic unit  120 , and provide the stored fail column address FCA to a comparator  124  of the control logic unit  120 . The comparator  124  may compare the fail column address FCA output from the memory cells of the fail row address FRA of the FCS cell array  114  with an access address of a write or read operation of the memory device  100 . 
         [0071]    The comparator  124  may compare the access address with the fail row address FRA and the fail column address FCA output from the FCS cell array  114  to obtain a comparison result quicker than when the access address is compared with the fail row address FRA and the fail column address FCA in the storage unit  122 . When the access address matches the fail row address FRA and the fail column address FCA, whether to perform an ECC operation on memory cells corresponding to the fail row address FRA and the fail column address FCA may be quickly determined. 
         [0072]    When there is one fail cell in memory cells connected to one row in the normal cell array  112 , the ECC cell array  116  is used to repair the one fail cell. The ECC cell array  116  may store parity bits to perform an ECC operation on the fail cell. The parity bits may be generated by the ECC engine  130 . 
         [0073]    The control logic unit  120  may determine whether an access address applied from an external source outside the memory device  100  addresses the fail cell. The control logic unit  120  may store fail cell information including the fail row address FRA and the fail column address FCA generated in the normal cell array  112 . The control logic unit  120  may compare the fail row address FRA and the fail column address FCA output from the FCS cell array  114  with the access address applied from the external source, and determine whether to perform an ECC operation based on a result of the comparison. The control logic unit  120  may include the storage unit  122  for storing the fail cell information, and the comparator  124  for comparing the fail column address FCA output from the FCS cell array  114  with an access column address CA[0:n]. 
         [0074]    The storage unit  122  may store the fail cell information about the fail cell generated in the normal cell array  112 . The fail cell information may include the fail row address FRA and the fail column address FCA, ordering information indicating a location of the fail cell, and master information indicating that the fail cell information is true. The fail cell information may be obtained during a test process performed while manufacturing the memory device  100 . If there is one fail cell from among the memory cells connected to the fail row address FRA, the storage unit  122  may store a column address of the one fail cell in the fail column address FCA. The fail cell information may be stored in the storage unit  122  when the memory device  100  is shipped. 
         [0075]    The storage unit  122  may enable a word line of the memory cell array  110 , which corresponds to the fail row address FRA, during initialization according to power-up of the memory device  100 . The storage unit  112  may store the fail cell information including the fail column address FCA in the memory cells of the FCS cell array  114 , from among the memory cells connected to the word line of the fail row address FRA. 
         [0076]    According to some embodiments, the storage unit  122  may be a one-time programmable memory, such as a laser-programmable fuse array, an anti-fuse array, or an electrical programmable fuse array, or may be a nonvolatile memory device, such as a magnetic random access memory (MRAM), a resistance random access memory (RRAM), a phase change random access memory (PRAM), or a flash memory. 
         [0077]    The comparator  124  may receive the access column address CA[0:n], and may receive the fail column address FCA from the FCS cell array  114 . If the access column address CA[0:n] and the fail column address FCA match each other, the comparator  124  may output an ECC control signal ECC_CNTL. The ECC control signal ECC_CNTL may be provided to the ECC engine  130  so that the ECC operation is performed on the fail row address FRA and the fail column address FCA of the normal cell array  112 . 
         [0078]    The ECC engine  130  may perform the ECC operation on the fail cell of the normal cell array  112  in response to the ECC control signal ECC_CNTL. The ECC engine  130  may generate parity bits with respect to write data bits written to the memory cells of the normal cell array  112  including the fail cell, and store the generated parity bits in the ECC cell array  116 . The ECC engine  130  may detect and correct an error bit included in read data bits by using the read data bit read from the memory cells including the fail cell of the normal cell array  112 , and the parity bits read from the ECC cell array  116 . 
         [0079]    The ECC engine  130  may perform the ECC operation on the fail cell information stored in the FCS cell array  114 , in response to the ECC control signal ECC_CNTL. The ECC engine  130  may generate the parity bits by performing the ECC operation on the fail cell information stored in the FCS cell array  114 , and store the generated parity bits in the FCS cell array  114 . The ECC engine  130  may detect and correct an error bit included in the fail cell information by using the fail cell information read from the FCS cell array  114  and the parity information. 
         [0080]      FIG. 2  is a flowchart of a method of operating the memory device  100  of  FIG. 1 . 
         [0081]    Referring to  FIG. 2  and  FIG. 1 , the memory cells of the memory cell array  110  may be determined to be good or bad during a test process of the memory device  100 . The memory device  100  may store fail cell information about a fail cell screened during the test process, in the storage unit  122 , in operation S 210 . 
         [0082]    The fail cell information may include a fail cell address including a 1-bit error from data written to or read from memory cells of one unit group. The fail cell address may include the fail row address FRA and the fail column address FCA. The storage unit  122  may store the fail row address FRA and the fail column address FCA, which address the memory cells in one unit group including the fail cell. The number of memory cells in one unit group may be 8, 16, 32, 64, or 128. 
         [0083]    The memory device  100  may perform initialization according to power-up when power is supplied to the memory device  100 . The memory device  100  may include a mode register that provides a plurality of operation options of the memory device  100 . During the initialization of the memory device  100 , the mode register may program various functions, characteristics, and modes of the memory device  100 . For example, the mode register may program a burst length, a read burst type, column address strobe (CAS) latency, delay-locked loop (DLL) enable/disable, output drive strength, additive latency, a power-down mode, and a data mask function. 
         [0084]    During the initialization of the memory device  100 , the fail cell information stored in the storage unit  122  may be copied and stored in the FCS cell array  114  of the memory cell array  110 , in operation S 220 . The memory device  100  enables the word line of the memory cell array  110 , which corresponds to the fail row address FRA of the storage unit  122 , and stores the fail column address FCA of the storage unit  122  in the memory cells of the FCS cell array  114  from among the memory cells connected to the word line of the fail row address FRA. The FCS cell array  114  will periodic refresh the data stored therein in operation S 225 . While shown sequentially in the flow chart of  FIG. 2 , it will be understood that the refresh operation is a separate periodic operation. 
         [0085]    The memory device  100  may receive a write or read command from a memory controller or a memory buffer. The memory device  100  may receive an access address together with the write or read command, in operation S 230 . The access address may include an access row address and an access column address. 
         [0086]    The memory device  100  may determine whether the access address matches a fail address of the FCS cell array  114 , in operation S 240 . If the access row address matches the fail row address FRA of the fail cell, the word line of the memory cell array  110 , which corresponds to the fail row address FRA, may be enabled. The fail column address FCA stored in the memory cells of the FCS cell array  114 , from among the memory cells connected to the word line of the fail row address FRA, may be read and provided to the comparator  124 . The comparator  124  may determine whether the fail column address FCA and the access column address CA[0:n] match each other. 
         [0087]    If it is determined that the fail column address FCA and the access column address CA[0:n] match each other in operation S 240 , the memory device  100  may perform the access operation (e.g., read or write) with the ECC operation on the memory cells of the normal cell array  112 , which correspond to the fail address, in operation S 250 . If the access column address CA[0:n] and the fail column address FCA match each other, the comparator  124  may generate and provide the ECC control signal ECC_CNTL to the ECC engine  130 . The ECC engine  130  may perform the ECC operation on the memory cells of the normal cell array  112 , which correspond to the fail row address FRA and the fail column address FCA, in response to the ECC control signal ECC_CNTL. For example, if reading, the ECC engine  130  performs error correction on the read data from the memory cell array  110  using the parity bits also read from the ECC cell array  116 . If writing, the ECC engine  130  generates parity bits from the write data. The write data is stored in the memory cell array  110  and the parity bits are stored in the ECC cell array  116 . 
         [0088]    If it is determined that the fail column address FCA and the access column address CA[0:n] do not match in operation S 240 , the memory device  100  may perform a read or write operation on the memory cells of the normal cell array  112 , which corresponds to the access address, without an ECC operation in operation S 260 . 
         [0089]    According to the method of the current embodiment, the fail row address FRA and the fail column address FCA stored in the storage unit  122  may be copied and stored in the FCS cell array  114  during the initialization of the memory device  100 . The fail row address FRA and the fail column address FCA stored in the FCS cell array  114  may be compared with the access address for performing the write or read operation of the memory device  100 , and whether to perform the ECC operation on the memory cells corresponding to the access address may be determined based on a result of the comparison. 
         [0090]    According to the method, the comparison result may be quickly obtained since only the access column address of the access address is compared with the fail column address FCA, and the access row address of the access address is not used. Also, since the access column address is compared with the fail column address FCA output from the FCS cell array  114 , the comparison result may be obtained quicker than when the access column address is compared with the fail row address FRA and the fail column address FCA of the storage unit  122 . Based on such a comparison result, the fail cell included in the memory cells addressed by the fail row address FRA and the fail column address FCA may be repaired via the ECC operation. 
         [0091]      FIGS. 3A through 3C  are diagrams for describing an X8 mode operation of the memory device  100  of  FIG. 1 . 
         [0092]    Referring to  FIG. 3A , the memory device  100  may support an X8 mode, wherein pieces of data written to or read from the memory cells in one unit group of the normal cell array  112  are input and output through 8 data input/output (IO) pads DQ 0  through DQ 7 . The ECC operation may be performed to repair an error bit included in data bits in one unit group written to or read from the memory cells in one unit group of the normal cell array  112 . According to the current embodiment, the number of memory cells in one unit group may be 64, and the number of data bits in one unit group may be 64 bits. 
         [0093]    The normal cell arrays  112  may include a plurality of normal cell blocks  301  through  308 . The normal cell blocks  301  through  308  may each include a plurality of memory cells arranged in rows and columns. Since pieces of data stored in the memory cells of the normal cell blocks  301  through  308  may be input or output respectively to or from the data IO pads DQ 0  through DQ 7 , for convenience of description, the normal cell blocks  301  through  308  will now be referred to as DQ 0  to DQ 7  cell blocks  301  through  308 . 
         [0094]    In each of the DQ 0  to DQ 7  cell blocks  301  through  308 , rows may include, for example, 8K word lines WL and columns may include, for example, 1K bit lines BL. Memory cells connected to intersections of the word lines WL and the bit lines BL may be DRAM cells indicated by ◯. In the DQ 0  to DQ 7  cell blocks  301  through  308 , the word lines WL are accessed by row addresses RA 0  through RAm, and the bit lines BL are accessed by column addresses CA 0  through CAn. 
         [0095]    The row addresses RA 0  through RAm are decoded by a row decoder  311 , and the word line WL is selected by the decoded row addresses RA 0  through RAm. The column addresses CA 0  through CAn are decoded by a column decoder  312 . The column decoder  312  generates column select signals CSL 0  through CSL 127  for selecting the bit lines BL by decoding the column addresses CA 0  through CAn. To support a burst length representing a maximum number of column locations for accessing the bit lines BL, bit lines BL corresponding to the burst length may be simultaneously accessed. 
         [0096]    For example, the memory device  100  may set the burst length to be 8. Accordingly, the bit lines BL may be connected to column selectors  321  to which the 128 column select signals CSL 0  through CSL 127  are supplied, respectively, and 8 bit lines BL may be simultaneously selected by one of the column selectors  321 . The column selectors  321  may each include 8 switches, and are turned on by the column select signals CSL 0  through CSL 127 , respectively. The column selectors  321  that are turned on or off by the column select signals CSL 0  through CSL 127  may form a column select circuit  320 . 
         [0097]    In the DQ 0  cell block  301 , a plurality of memory cells may be connected to the word line WL accessed by the row addresses RA 0  through RAm. 8 of the plurality of memory cells connected to the word line WL may be selected by a respective column selector  321  connected to the column select signal CSL 0  and connected to first data lines GIO[0:7]. The first data lines GIO[0:7] may include 8 bits. 
         [0098]    In the DQ 1  cell block  302  as well, 8 of a plurality of memory cells connected to the word line WL may be selected by respective column selector  321  to which the column select signal CSL 0  is provided, and connected to second data lines GIO[8:15]. Also, in each of the other DQ 2  to DQ 7  cell blocks  303  to  308 , 8 of a plurality of memory cells connected to the word lines WL are selected by respective column selector  321  to which the column select signal CSL 0  is provided, and connected to corresponding data lines among third to eighth data lines GIO[16:23] to GIO[56:63]. This description equally applies to column select signals CSL 1  to CSL 127 . 
         [0099]    In the memory device  100 , pieces of data Data[6:23] to be written to the DQ 0  to DQ 7  cell blocks  301  through  308  may be transmitted to the first through eighth data lines GIO[0:63]. Via the first through eighth data lines GIO[0:63], pieces of first to eighth burst data that are to be respectively written to the DQ 0  to DQ 7  cell blocks  301  to  308 , i.e., a total of 64 bits of data Data[0:63], may be received, respectively. The received data Data[0:63] may be written to eight memory cells of each of the DQ 0  to DQ 7  cell blocks  301  through  308  selected by the column selection unit  321  to which, for example, the column select signal CSL 0  is supplied from among the plurality of memory cells connected to the word lines WL. This description equally applies to column select signals CSL 1  to CSL 127 . 
         [0100]    If one fail cell exists in the memory cells connected to one word line WL in the DQ 0  to DQ 7  cell blocks  301  to  308 , the ECC cell array  116  may be used to repair the fail cell. For example, one fail cell (indicated by ) may exist in the DQ 0  cell block  301  from among the memory cells of the DQ 0  to DQ 7  cell blocks  301  through  308  selected by the word lines WL and the column selector  321  to which the column select signal CSL 0  is provided. On the other hand, the fail cell may not be the fail cell of the DQ 0  cell block  301 , but may be any fail cell generated in the memory cells of the DQ 1  to DQ 7  cell blocks  302  through  308  selected by the word line WL and the column selector  321  to which the column select signal CSL 0  is provided. The ECC cell array  116  may be controlled by the ECC engine  130 , and may be used to detect and correct a fail cell in any of the DQ 0  to DQ 7  cell blocks  301  through  308 . 
         [0101]    Like the DQ 0  to DQ 7  cell blocks  301  through  308 , the ECC cell array  116  may include 8K word lines WL. Unlike the DQ 0  to DQ 7  cell blocks  301  through  308 , the ECC cell array  116  may include 8 bit lines BL. Memory cells connected to intersections of the word lines WL and the bit lines BL of the ECC cell array  116  may also be DRAM cells. 
         [0102]    In the ECC cell array  116 , eight bit lines BL are connected to parity data lines ECCP[0:7]. Parity bits regarding the data Data[0:63] stored in a fail cell of any of the DQ 0  to DQ 7  cell blocks  301  through  308  may be transmitted to the parity data lines ECCP[0:7]. The parity bits may be stored in and read from eight memory cells in the ECC cell array  116  via the parity data lines ECCP[0:7]. In this case, the eight memory cells of the ECC cell array  116  may be connected to the word line WL to which the fail cell is also connected. 
         [0103]    The ECC engine  130  may detect and correct a fail cell of the DQ 0  to DQ 7  cell blocks  301  through  308 , in response to the ECC control signal ECC_CNTL. During a write operation, the ECC engine  130  may generate parity bits with respect to the data Data[0:63] received from a memory controller or a memory buffer, and transmit the parity bits to the parity data lines ECCP[0:7], in response to the ECC control signal ECC_CNTL. The parity bits on the parity data lines ECCP[0:7] may be stored in the memory cells of the ECC cell array  116  connected to the word line WL of the fail cell. 
         [0104]    During a read operation, the ECC engine  130  may receive data transmitted to the first through eighth data lines GIO[0:63] and data transmitted to the parity data lines ECCP[0:7], in response to the ECC control signal ECC_CNTL. The data transmitted to the first through eighth data lines GIO[0:63] is data read from the memory cells of the DQ 0  to DQ 7  cell blocks  301  through  308 , which are connected to the word line WL of the fail cell, and the data transmitted to the parity data lines ECCP[0:7] is parity bits read from the memory cells of the ECC cell array  116 , which are connected to the word line WL of the fail cell. 
         [0105]    The ECC engine  130  may detect and correct an error bit caused by the fail cell, by using the data transmitted to the first through eighth data lines GIO[0:63] and the parity data lines ECCP[0:7]. The ECC engine  130  may receive the data transmitted to the first through eighth data lines GIO[0:63] and the parity data lines ECCP[0:7], generate syndrome data, calculate a location of the fail cell, i.e., an error bit location, correct data corresponding to the error bit location, and output the data Data[0:63] having the corrected error bit. 
         [0106]    The memory device  100  may support the x8 mode, wherein pieces of data corresponding to a burst length of 8 are input and output to and from the 8 data IO pads DQ 0  through DQ 7 . As shown in  FIGS. 3B and 3C , first through eighth burst data, i.e., total 64 bits of data Data[0:63], may be output from the DQ 0  to DQ 7  cell blocks  301  through  308  to the data IO pads DQ 0  through DQ 7 , respectively. 
         [0107]    Referring to  FIG. 3B , at a time T 0 , first burst data, i.e., Data 0 , Data 8 , Data 16 , Data 24 , Data 32 , Data 40 , Data 48 , and Data 56  may be output respectively to the data IO pads DQ 0  through DQ 7 . At a time T 1 , second burst data, i.e., Data 1 , Data 9 , Data 17 , Data 25 , Data 33 , Data 41 , Data 49 , and Data 57  may be output. At a time T 2 , third burst data, i.e., Data 2 , Data 10 , Data 18 , Data 26 , Data 34 , Data 42 , Data 50 , and Data 58  may be output. Then, at times T 3  through T 7 , fourth through eighth burst data may be output, respectively. 
         [0108]    The memory device  100  may be required to perform a burst chop (BC) function. The memory device  100  may, for example, output the first through fourth burst data at times T 1  through T 3  according to BC=4. The memory device  100  may drive the ECC engine  130  to detect and correct an error bit with respect to the first through fourth burst data. 
         [0109]    The ECC engine  130  may generate parity bits ECCP 0 [0:3] with respect to the first burst data. The ECC engine  130  may generate parity bits ECCP 1 [0:3] with respect to the second burst data. Similarly, the ECC engine  130  may generate parity bits ECCP 2 [0:3] and ECCP 3 [0:3] with respect to the third and fourth burst data. Namely, each burst at a respective time slot T 0 , T 1 , etc. is a ECC coding unit for the ECC engine  130 . 
         [0110]    The ECC engine  130  may store the parity bits ECCP 0 [0:3], ECCP 1 [0:3], ECCP 2 [0:3], and ECCP 3 [0:3] generated with respect to the first through fourth burst data, in the ECC cell array  116 . The ECC engine  130  may detect and correct errors of the first through fourth burst data by using, respectively, the first through fourth burst data read from the DQ 0  to DQ 7  cell blocks  301  through  308  and the parity bits ECCP 0 [0:3], ECCP 1 [0:3], ECCP 2 [0:3], and ECCP 3 [0:3] read from the ECC cell array  116 . 
         [0111]    Referring to  FIG. 3C , the memory device  100  may be required to perform a data mask function. The memory device  100  may perform a data mask operation on, for example, the second, fourth, sixth, and eighth burst data. The memory device  100  may drive the ECC engine  130  to detect and correct an error bit with respect to the first, third, fifth, and seventh burst data that are not masked. 
         [0112]    The ECC engine  130  may perform an ECC operation on burst data that is not masked. The ECC engine  130  may generate the parity bits ECCP 0 [0:3] with respect to the first burst data, i.e., Data 0 , Data 8 , Data 16 , Data 24 , Data 32 , Data 40 , Data 48 , and Data 56 . The ECC engine  130  may generate the parity bits ECCP 2 [0:3] with respect to the third burst data, i.e., Data 2 , Data 10 , Data 18 , Data 26 , Data 34 , Data 42 , Data 50 , and Data 58 . Similarly, the ECC engine  130  may generate parity bits ECCP 4 [0:3] and ECCP 6 [0:3] with respect to the fifth and seventh burst data. 
         [0113]    The ECC engine  130  may store the parity bits ECCP 0 [0:3], ECCP 2 [0:3], ECCP 4 [0:3], and ECCP 6 [0:3] in the ECC cell array  116 . The ECC engine  130  may detect and correct error bits of the first, third, fifth, and seventh burst data by using, respectively, the first, third, fifth, and seventh burst data read from the DQ 0  to DQ 7  cell blocks  301  through  308  and the parity bits ECCP 0 [0:3], ECCP 2 [0:3], ECCP 4 [0:3], and ECCP 6 [0:3] read from the ECC cell array  116 . 
         [0114]    The memory device  100  according to the current embodiment may support the X8 mode since 64 data bits having a burst length of 8 with respect to each of the DQ 0  to DQ 7  cell blocks  301  through  308  are input to and output from the data IO pads DQ 0  through DQ 7 , respectively. The memory device  100  may be required to support an X4 mode as well as the X8 mode, according to user demand. If the memory device  100  in the X8 mode may also operate in X4 mode, compatibility of the memory device  100  may improve. At this time, the ECC operation for repairing a fail cell in the memory device  100  may also be required to adaptively operate in the X4 mode. 
         [0115]      FIG. 4  is a diagram for describing an X4 mode operation of a memory device  100   a  according to an embodiment of the inventive concepts. 
         [0116]    Referring to  FIG. 4 , the number of data bits in one unit group may be 32 bits for the memory device  100   a  to support an X4 mode. In the normal cell array  112 , a DQ 0 L cell block  401 L may correspond to the DQ 0  cell block  301  of  FIG. 3 . Also, a DQ 0 U cell block  401 U may correspond to the DQ 1  cell block  302 , a DQ 1 L cell block  402 L may correspond to the DQ 2  cell block  303 , a DQ 1 U cell block  402 U may correspond to the DQ 3  cell block  304 , a DQ 2 L cell block  403 L may correspond to the DQ 4  cell block  305 , a DQ 2 U cell block  403 U may correspond to the DQ 5  cell block  306 , a DQ 3 L cell block  404 L may correspond to the DQ 6  cell block  307 , and a DQ 3 U cell block  404 U may correspond to the DQ 7  cell block  308 . 
         [0117]    The DQ 0 L, DQ 1 L, DQ 2 L, and DQ 3 L cell blocks  401 L,  402 L,  403 L, and  404 L are cell blocks with an ‘L’ suffix, wherein L denotes ‘lower’, and DQ 0 U, DQ 1 U, DQ 2 U, and DQ 3 U cell blocks  401 U,  402 U,  403 U, and  404 U are cell blocks with an ‘U’ suffix, wherein U denotes ‘upper’. In order to support an X4 mode, 32 data bits corresponding to a burst length of 8 may be input or output with respect to the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L. Also, 32 data bits corresponding to a burst length of 8 may be input or output with respect to the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U. 
         [0118]    Bit lines BL of the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L and the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U may be connected to a column select circuit  420  including a column selector  421  connected to each of the 128 column select signals CSL 0  through CSL 127 . As shown in  FIGS. 5A and 5B , the column select circuit  420  may include a column selector  521  that selects bit lines of FCS 0 L and FCS 1 L cell blocks  406 L and  407 L and FCS 0 U and FCS 1 U cell blocks  406 U and  407 U in the FCS cell array  114 . The column selector  521  may be provided with FCS column select signals FCSL 0  and FCSL 1 . The column select signals CSL 0  through CSL 127 , FCSL 0 , and FCSL 1  may be provided from a column decoder that decodes the column addresses CA 0  through CAn. 
         [0119]    The column select circuit  420  may use the access column address CA[0:n] that generates the column select signals CSL 0  through CSL 127  such that the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L are selected or the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U are selected. For example, when the column address CA 11  is ‘0’ bit, the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L may be selected, and when the column address CA 11  is ‘1’ bit, the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U may be selected. 
         [0120]    The DQ 0 L cell block  401 L and the DQ 0 U cell block  401 U may share first data lines GIO[0:7], the DQ 1 L cell block  402 L and the DQ 1 U cell block  402 U may share second data lines GIO[8:15], the DQ 2 L cell block  403 L and the DQ 2 U cell block  403 U may share third data lines GIO[16:23], and the DQ 3 L cell block  404 L and the DQ 3 U cell block  404 U may share fourth data lines GIO[24:31]. 
         [0121]    The data Data[0:31] to be written to the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L may be transmitted to the first through fourth data lines GIO[0:31]. First through eighth burst data, i.e., total 32 bits of the data Data[0:31], to be respectively written to the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L may be received respectively through the first through fourth data lines GIO[0:31]. The received 32 bits of the data Data[0:31] may be written to 8 memory cells of each of the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L through the column select circuit  420  that is set to select the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L. 
         [0122]    The data Data[0:31] to be written to the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U may be transmitted to the first through fourth data lines GIO[0:31]. The first through eighth burst data, i.e., total 32 bits of the data Data[0:31], to be respectively written to the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U may be received respectively through the first through fourth data lines GIO[0:31]. The received 32 bits of the data Data[0:31] may be written to 8 memory cells of each of the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U through the column select circuit  420  that is set to select the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U. 
         [0123]    The ECC cell array  116  may include an ECCPL cell block  405 L and an ECCPU cell block  405 U. If there is one fail cell in memory cells connected to one word line WL in the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L, the ECCPL cell block  405 L may be used to repair the one fail cell. If there is one fail cell in memory cells connected to one word line WL in the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U, the ECCPU cell block  405 U may be used to repair the one fail cell. 
         [0124]    Like the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L and the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U, each of the ECCLPL cell block  405 L and the ECCPU cell block  405 U may include, for example, 8K word lines WL. Unlike the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L and the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U, each of the ECCLPL cell block  405 L and the ECCPU cell block  405 U may include, for example, 8 bit lines BL. 
         [0125]    The 8 bit lines BL of the ECCPL cell block  405 L may be connected to first parity data lines PL[0:7]. First parity bits regarding the data Data[0:31] stored in the fail cell of the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L may be transmitted to the first parity data lines PL[0:7]. The first parity bits may be stored in and read from the 8 memory cells in the ECCPL cell block  405 L through the first parity data lines PL[0:7]. Here, the 8 memory cells of the ECCPL cell block  405 L may be connected to the word line WL of the fail cell. 
         [0126]    The 8 bit lines BL of the ECCPU cell block  405 U may be connected to second parity data lines PU[0:7]. Second parity bits regarding the data Data[0:31] stored in the fail cell of the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U may be transmitted to the second parity data lines PU[0:7]. The second parity bits may be stored in and read from the 8 memory cells in the ECCPU cell block  405 U through the second parity data lines PU[0:7]. Here, the 8 memory cells of the ECCPU cell block  405 U may be connected to the word line WL of the fail cell. 
         [0127]    In response to the ECC control signal ECC_CNTL, the ECC engine  130  may detect and correct the fail cell of the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L. During the write operation, the ECC engine  130  may generate the first parity bits with respect to the data Data[0:31] to be written to the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L received from a memory controller or a memory buffer and transmit the generated first parity bits to the first parity data lines PL[0:7], in response to the ECC control signal ECC_CNTL. The first parity bits on the first parity data lines PL[0:7] may be stored in the memory cells of the ECCPL cell block  405 L, which are connected to the word line WL of the fail cell. 
         [0128]    During the reading operation, the ECC engine  130  may receive read data of the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L transmitted to the first through fourth data lines GIO[0:31] and the first parity bits of the ECCPL cell block  405 L transmitted to the first parity data lines PL[0:7], in response to the ECC control signal ECC_CNTL. The ECC engine  130  may receive the read data of the first through fourth data lines GIO[0:31] and the first parity bits of first parity data lines PL[0:7], generate syndrome data, calculate an error bit location in the read data of the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L, correct data corresponding to the error bit location, and output the data Data[0:31] having the corrected error bit. 
         [0129]    The ECC engine  130  detects and corrects a fail cell of the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U in response to the ECC control signal ECC_CNTL. During the write operation, the ECC engine  130  may generate the second parity bits with respect to the data Data[0:31] to be written to the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U received from the memory controller or the memory buffer and transmit the generated second parity bits to the second parity data lines PU[0:7], in response to the ECC control signal ECC CNTL. The second parity bits on the second parity data lines PU[0:7] may be stored in the memory cells of the ECCPU cell block  405 U connected to the word line WL of the fail cell. 
         [0130]    During the read operation, the ECC engine  130  may receive read data of the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U transmitted to the first through fourth data lines GIO[0:31] and the second parity bits of the ECCPU cell block  405 U transmitted to the second parity data lines PU[0:7], in response to the ECC control signal ECC_CNTL. The ECC engine  130  may receive the read data of the first through fourth data lines GIO[0:31] and the second parity bits of the second parity data lines PU[0:7], generate syndrome data, calculate an error bit location in the read data of the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U, correct data corresponding to the error bit location, and output the data Data[0:31] with the corrected error bit. 
         [0131]    In the memory device  100   a , fail cell information about the fail cell of the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L and fail cell information about the fail cell of the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U may be stored in the storage unit  122  of the control logic unit  120  as shown in  FIG. 5A  or  5 B. The fail row address and the fail column address FRA and FCA stored in the storage unit  122  may be copied and stored in the FCS cell array  114  of the memory cell array  110  of  FIG. 1 . 
         [0132]      FIGS. 5A and 5B  are diagrams of the FCS cell array  114  of the memory device  100   a  of  FIG. 4 , according to some embodiments of the inventive concepts. In  FIG. 5A , the fail cell information about the fail cell of the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L is copied and stored in the FCS 0 L and FCS 1 L cell blocks  406 L and  407 L having an ‘L’ suffix. In  FIG. 5B , the fail cell information about the fail cell of the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U is copied and stored in the FCS 0 U and FCS 1 U cell blocks  406 U and  407 U having an ‘U’ suffix. 
         [0133]    Referring to  FIG. 5A , the memory cell array  110  may include the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L and the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U of the normal cell array  112 , and the ECCPL cell block  405 L and the ECCPU cell block  406 U of the ECC cell array  116 , which are described above with reference to  FIG. 4 . Also, the memory cell array  110  may include the FCS cell array  114  including the FCS 0 L, FCS 0 U, FCS 1 L, and FCS 1 U cell blocks  406 L,  406 U,  407 L, and  407 U. Like the ECCPL and ECCPU cell blocks  405 L and  405 U, each of the FCS 0 L, FCS 0 U, FCS 1 L, and FCS 1 U cell blocks  406 L,  406 U,  407 L, and  407 U may include 8K word lines WL and 8 bit lines BL. 
         [0134]    The FCS 0 L cell block  406 L and the FCS 1 L cell block  407 L of the FCS cell array  114  may copy and store the fail cell information of the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L from the storage unit  122  through operation of the respective column selector  521 . The storage unit  122  may store the fail row address FRA and the fail column address FCA of the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L and, during initialization of the memory device  100   a , store the fail column address FCA in memory cells connected to the word lines WL of the fail row addresses FRA of the FCS 0 L cell block  406 L and the FCS 1 L cell block  407 L. 
         [0135]    Referring to  FIG. 5B , the FCS 0 U cell block  406 U and the FCS 1 U cell block  407 U of the FCS cell array  114  may copy and store the fail cell information of the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U from the storage unit  122  through the column selector  521 . The storage unit  122  may store the fail row address FRA and the fail column address FCA of the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U and, during the initialization of the memory device  100   a , store the fail column address FCA in memory cells connected to the word lines WL of the fail row addresses FRA of the FCS 0 U cell block  406 U and the FCS 1 U cell block  407 U. 
         [0136]    In  FIG. 5A , each of the FCS 0 L cell block  406 L and the FCS 1 L cell block  407 L may include 8 memory cells connected to the word line WL of the fail row address FRA, and thus the fail cell information of the DQ 1 L to DQ 3 L cell blocks  401 L through  404 L may be copied from the storage unit  122  and stored in the total 16 memory cells. The fail cell information stored in the FCS 0 L cell block  406 L and the FCS 1 L cell block  407 L may be indicated as shown in  FIGS. 6A and 6B . 
         [0137]      FIGS. 6A and 6B  are diagrams for describing fail cell information stored in FCS cell blocks of  FIG. 5A . In  FIGS. 6A and 6B , the numbers of bits assigned to ordering information are different. 
         [0138]    Referring to  FIG. 6A , the 8 memory cells of the FCS 0 L cell block  406 L and the 8 memory cells of the FCS 1 L cell block  407 L, which are connected to the word line of the fail row address FRA, may form 16 bits. The fail cell information of the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L may be stored by using 11 bits, i.e., 8 bits of the FCS 0 L cell block  406 L and 3 bits from 8 bits of the FCS cell block  407 L. 
         [0139]    The 7 bits, i.e., F 4 , F 5 , F 6 , F 7 , and F 8  bits of the FCS 0 L cell block  406 L, and F 9  and F 10  bits of the FCS 1 L cell block  407 L may indicate which one of the column selectors  421  of  FIG. 4 , to which the column select signals CSL 0  through CSL 127  are supplied, is connected to one fail cell generated in the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L. 
         [0140]    The F 1 , F 2 , and F 3  bits of the FCS 0 L cell block  406 L may store ordering information. The ordering information formed of 3 bits may indicate which of the first through eighth burst data (e.g., time slots T 0 , T 1 , etc.) described above with reference to  FIG. 3B  includes an error bit of a fail cell. The ordering information in 3 bits may be set to support an X8 mode of a memory device. 
         [0141]    An M bit of the FCS 1 L cell block  407 L may store master information indicating whether the fail cell information stored in the FCS 0 L cell block  406 L and the FCS 1 L cell block  407 L is true. The M bit may indicate whether there is one fail cell in the memory cells of the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L connected to the word line of the fail row address FRA. For example, if the M bit is ‘0’, the M bit indicates that there is no fail cell in the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L connected to the word line of the fail row address FRA and that the fail cell information stored in the FCS 0 L cell block  406 L and the FCS 1 L cell block  407 L is invalid. If the M bit is ‘1’, the M bit indicates that there is one fail cell in the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L connected to the word line of the fail row address FRA and that the fail cell information stored in the FCS 0 L cell block  406 L and the FCS 1 L cell block  407 L is valid. 
         [0142]    5 bits may be reserved from among the 8 bits of the FCS 1 L cell block  407 L. The reserved 5 bits may be used for an ECC operation performed on the 11 bits of the fail cell information stored in the FCS 0 L cell block  406 L and the FCS 1 L cell block  407 L. The 5 bits may be used to perform the ECC operation on the fail cell information stored in the FCS 0 L cell block  406 L and the FCS 1 L cell block  407 L and generate parity bits. The parity bits with respect to the fail cell information may be stored in the reserved 5 bits of the FCS cell block  407 L. 
         [0143]      FIG. 6B  is different from  FIG. 6A  in that ordering information is stored by using 2 bits, i.e., F 1  and F 2  bits of the FCS 0 L cell block  406 L. The first through eighth burst data described above with reference to  FIG. 3B  may form 4 groups as the first through eighth burst data are grouped in two. The ordering information in 2 bits may indicate which one of four groups includes an error bit of a fail cell. The ordering information in 2 bits may be set to support an X4 mode of a memory device. 
         [0144]    7 bits, i.e., F 3 , F 4 , F 5 , F 6 , F 7 , and F 8  bits of the FCS 0 L cell block  406 L and an F 9  bit of the FCS 1 L cell block  407 L may indicate which one of the column selectors  421  of  FIG. 4 , to which the column select signals CSL 0  through CSL 127  are supplied, is connected to one fail cell generated in the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L. An M bit of the FCS 1 L cell block  407 L may indicate whether there is one fail cell in the memory cells of the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L connected to the word line of the fail row address FRA. The 6 bits that are reserved from among the 8 bits of the FCS 1 L cell block  407 L may store parity bits with respect to the fail cell information stored in the FCS 0 L cell block  406 L and the FCS cell block  407 L. 
         [0145]      FIG. 7  is a diagram of a data line structure in the memory device  100   a  of  FIG. 5A .  FIG. 7  illustrates the data line structure wherein FCS cell blocks share data lines of DQ cell blocks. 
         [0146]    Referring to  FIG. 7 , the memory cell array  110  may include the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L, the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U, the ECCPL cell block  405 L, the ECCPU cell block  405 U, the FCS 0 L and FCS 1 L cell blocks  406 L and  407 L, and the FCS 0 U and FSC 1 U cell blocks  406 U and  407 U. 
         [0147]    The DQ 0 L cell block  401 L may be connected to the first data lines GIO[0:7], the DQ 0 U cell block  401 U may be connected to the second data lines GIO[8:15], the DQ 1 L cell block  402 L may be connected to the third data lines GIO[16:23], the DQ 1 U cell block  402 U may be connected to the fourth data lines GIO[24:31], the DQ 2 L cell block  403 L may be connected to the fifth data lines GIO[32:39], the DQ 2 U cell block  403 U may be connected to the sixth data lines GIO[40:47], the DQ 3 L cell block  404 L may be connected to the seventh data lines GIO[48:55], and the DQ 3 U cell block  404 U may be connected to the eighth data lines GIO[56:63]. 
         [0148]    In the memory cell array  110 , DRAM cells arranged in rows and columns have a small cell size due to microfabrication. In this regard, since the first through eighth data lines GIO[0:63] connected to the DRAM cells are arranged by considering line widths and line intervals, a large arrangement area is required compared to the cell size. 
         [0149]    In order to store fail cell information in the memory cells of the FCS 0 L, FCS 0 U, FCS 1 L, and FCS 1 U cell blocks  406 L,  406 U,  407 L, and  407 U, data lines connected to the FCS 0 L, FCS 0 U, FCS 1 L, and FCS 1 U cell blocks  406 L,  406 U,  407 L, and  407 U are required. Here, a data line arrangement of the memory device  100   a  may be convenient if the first through eighth data lines GIO[0:63] are shared rather than separately arranging data lines connected to the FCS 0 L, FCS 0 U, FCS 1 L, and FCS 1 U cell blocks  406 L,  406 U,  407 L, and  407 U. 
         [0150]    The FCS 0 L cell block  406 L may share the first data lines GIO[0:7] of the DQ 0 L cell block  401 L. The FCS 0 U cell block  406 U may share the second data lines GIO[8:15] of the DQ 0 U cell block  401 U, the FCS 1 L cell block  407 L may share the seventh data lines GIO[48:55] of the DQ 3 L cell block  404 L, and the FCS 3 U cell block  407 U may share the eighth data lines GIO[56:63] of the DQ 3 U cell block  404 U. Accordingly, the FCS 0 L cell block  406 L is disposed adjacent to the DQ 0 L cell block  401 L, the FCS 0 U cell block  406 U is disposed adjacent to the DQ 0 U cell block  401 U, the FCS 1 L cell block  407 L is disposed adjacent to the DQ 3 L cell block  404 L, and the FCS 1 U cell block  407 U may be disposed adjacent to the DQ 3 U cell block  404 U. 
         [0151]    According to some embodiments, the FCS 0 L, FCS 0 U, FCS 1 L, and FCS 1 U cell blocks  406 L,  406 U,  407 L, and  407 U may be respectively disposed adjacent to the DQ 1 L, DQ 1 U, DQ 2 L, and DQ 2 U cell blocks  402 L,  402 U,  403 L, and  403 U. The FCS 0 L, FCS 0 U, FCS 1 L, and FCS 1 U cell blocks  406 L,  406 U,  407 L, and  407 U may respectively share the third, fourth, fifth, and sixth data lines GIO[16:23], GIO[24:31], GIO[32:39], and GIO[40:47]. 
         [0152]      FIGS. 8 and 9  are diagrams for describing the storage unit  122  of  FIG. 1 . 
         [0153]    Referring to  FIG. 8 , the storage unit  122  may include a row address storage unit  810 , a column address storage unit  820 , an ordering storage unit  830 , and a master storage unit  840 . The row address storage unit  810  stores row addresses FRA[0:m] of a fail cell, and the column address storage unit  820  may store column addresses FCA[0:n] of the fail cell. The ordering storage unit  830  may store, for example, ordering information F[1:2] described above with reference to  FIG. 6B , and the master storage unit  840  may store master information M. 
         [0154]    Referring to  FIG. 9 , the row address storage unit  810 , the column address storage unit  820 , the ordering storage unit  830 , and the master storage unit  840  may be formed by an anti-fuse array including a plurality of anti-fuses  902 . The anti-fuse  902  has an electric characteristic opposite to a fuse device, and is a resistance fuse device that has a high resistance value in an un-programmed state and has a low resistance value in a programmed state. 
         [0155]    The anti-fuse  902  generally has a structure wherein a dielectric material is inserted between conductive materials, and is programmed by breaking down the dielectric material between the conductive materials by applying a high voltage to the dielectric material through the conductive materials. Then, the conductive materials of the anti-fuse  902  are short-circuited, and thus the anti-fuse  902  may have a low resistance value. 
         [0156]    The anti-fuse  902  includes a depletion mode metal oxide semiconductor (MOS) transistor wherein a source electrode  4  and a drain electrode  5  are connected to each other. In an initial state, resistance between a first node  6  connected to a gate electrode  3  and a second node  7  commonly connected to the source and drain electrodes  4  and  5  may be very high since a space between the first and second nodes  6  and  7  is separated by a gate oxide film. Accordingly, the space between the first and second nodes  6  and  7  is non-conductive. Such a state may be set to, for example, logic ‘low’ that is the un-programmed state. 
         [0157]    The anti-fuse  902  may apply a breakdown voltage between the first and second nodes  6  and  7  to break down the gate oxide film, so as to irreversibly change from a non-conductive state to a conductive state. When the gate oxide film breaks down, the resistance between the first and second nodes  6  and  7  may be decreased. Such a state may be set to logic ‘high’; that is the programmed state. 
         [0158]    The storage unit  122  may selectively program the anti-fuses  920  forming the row address storage unit  810 , the column address storage unit  820 , the ordering storage unit  830 , and the master storage unit  840  to respectively store the row addresses FRA[0:m], the column addresses FCA[0:n], the ordering information F[1:2] and the master information M of fail cells generated while manufacturing the memory device  100  of  FIG. 1 . 
         [0159]      FIG. 10  is a diagram for describing the comparator  124  of  FIG. 1 . 
         [0160]    Referring to  FIG. 10 , the comparator  124  may include an address comparator  910  and an ECC control single output unit  920 . The address comparator  910  may include XNOR gates  911  that compare each of the column addresses FCA[0:n] output from the FCS cell array  114  of  FIG. 1  and each of the access column addresses CA[0:n]. The ECC control signal output unit  920  may include a NAND gate  921  into which outputs of the XNOR gates  911  are input, and an inverter  922  into which an output of the NAND gate  921  is input. An output of the inverter  922  may be output as the ECC control signal ECC_CNTL. 
         [0161]      FIG. 11  is a diagram for describing the ECC engine  130  of  FIG. 1 . 
         [0162]    Referring to  FIG. 11 , the ECC engine  130  may include a first ECC engine  1110  and a second ECC engine  1120 . The first ECC engine  1110  may perform an ECC operation on a fail cell of the normal cell array  112  in response to the ECC control signal ECC_CNTL. The first ECC engine  1110  may generate parity bits with respect to write data bits written to the memory cells of the normal cell array  112 , which include the fail cell, and store the generated parity bits in the ECC cell array  116 . The first ECC engine  1110  may detect and correct an error bit included in read data bits read from the memory cells of the normal cell array  112 , which include the fail cell, by using the read data bits and the parity bits read from the ECC cell array  116 . 
         [0163]    The second ECC engine  1120  may perform an ECC operation on the fail cell information stored in the FCS cell array  114 , in response to the ECC control signal ECC_CTL. The second ECC engine  1120  may perform the ECC operation on the fail cell information stored in the FCS cell array  114  to generate parity bits, and store the generated parity bits in the FCS cell array  114 . For example, as described above with reference to  FIGS. 6A and 6B , the parity bits with respect to the fail cell information may be stored in the reserved 5 bits of the FCS 1 L cell block  407 L. The second ECC engine  1120  may detect and correct an error bit included in the fail cell information read from the FCS cell array  114  by using the fail cell information and the parity bits. 
         [0164]      FIG. 12  is a diagram for describing the first ECC engine  1110  of  FIG. 11 . The first ECC engine  1110  of  FIG. 12  adaptively operates in the X4 mode of the memory device  100   a  of  FIG. 4 . 
         [0165]    Referring to  FIG. 12 , the first ECC engine  1110  may include an ECC encoding circuit  1102  and an ECC decoding circuit  1104 . The ECC encoding circuit  1102  may generate parity bits ECCP[0:3] with respect to write data WData[0:7] to be written to the memory cells of the memory cell array  110 , in response to the ECC control signal ECC_CNTL. The parity bits ECCP[0:3] may be stored in the ECCPL cell block  405 L or the ECCPU cell block  405 U of the ECC cell array  116 . The write data WData[0:7] may be stored in the DQ 0 L to DQ 3 L cell blocks  401 L through  404 L or the DQ 0 U to DQ 3 U cell blocks  401 U through  404 U of the normal cell array  112 . 
         [0166]    In response to the ECC control signal ECC_CNTL, the ECC decoding circuit  1104  may correct an error bit included in read data RData[0:7] read from the normal cell array  112  by using the read data RData[0:7] and the parity bits ECCP[0:3] read from the ECC cell array  116 , and output data Data[0:7] with the corrected error bit. 
         [0167]      FIGS. 13A and 13B  are diagrams for describing the ECC encoding circuit  1102  and the ECC decoding circuit  1104  of  FIG. 12 . 
         [0168]    Referring to  FIG. 13A , the ECC encoding circuit  1102  may include a parity generator  1212  that receives the write data WData[0:7] in 8 bits in response to the ECC control signal ECC_CNTL, and generates the parity bits ECCP[0:3] by using any well-known logical operation between data bits used to generate parity bits. 
         [0169]    Referring to  FIG. 13B , the ECC decoding circuit  1104  may include a syndrome generator  1302 , a coefficient calculator  1304 , a 1-bit error position detector  1306 , and an error corrector  1308 . The syndrome generator  1302  may receive the read data RData[0:7] in 8 bits and the parity bits ECCP[0:3] in 4 bits in response to the ECC control signal ECC_CNTL, and generate syndrome data S[0:3] by using an XOR array operation. The coefficient calculator  1304  may calculate a coefficient of an error position equation by using the syndrome data S[0:3]. The error position equation is an equation that uses a reciprocal of an error bit as a root. The 1-bit error position detector  1306  may calculate a position of a 1-bit error by using the calculated error position equation. The error corrector  1308  may correct an error by reversing a logic value of a bit having an error from among the read data RData[0:7] in 8 bits according to the determined position of the 1-bit error and output the data Data[0:7] in which the error is corrected. 
         [0170]      FIG. 14  is a diagram of a memory device  1400  capable of quickly repairing a fail cell, according to another embodiment of the inventive concepts. 
         [0171]    Referring to  FIG. 14 , the memory device  1400  performs a data line redundancy operation to repair a fail cell. The memory device  1400  may include a memory cell array  1410 , a control logic unit  1420 , and a redundancy control circuit  1430 . The memory cell array  1410  may include a plurality of memory cells arranged in rows and columns. The memory cell array  1410  may include a normal cell array  1412 , an FCS cell array  1414 , and a redundancy cell array  1416 . The control logic unit  1420  may store fail cell information about a fail cell generated in the normal cell array  1412 . The redundancy control circuit  1430  may perform a repair operation by replacing a column connected to the fail cell of the normal cell array  1412  with a column of the redundancy cell array  1416 . 
         [0172]    A fail cell indicated by  and addressed by the fail row address FRA and the fail column address FCA may exist in the normal cell array  1412 . The FCS cell array  1414  may copy and store the fail cell information stored in a storage unit  1422  of the control logic unit  1420 . The storage unit  1422  may store the fail row address FRA and the fail column address FCA of the fail cell generated in the normal cell array  1412 . The FCS cell array  1414  may store the fail column address FCA in memory cells accessed by the fail row address FRA. 
         [0173]    The FCS cell array  1414  may provide the fail column address FCA to a comparator  1424  of the control logic unit  1420 . The comparator  1424  may compare the fail column address FCA output from the memory cells of the fail row address FRA of the FCS cell array  114  with an access address of a write or read operation of the memory device  1400 . 
         [0174]    The comparator  1424  may compare the access address with the fail row address FRA and the fail column address FCA output from the FCS call array  1414  to more quickly obtain a comparison result than when the access address is compared with the fail row address FRA and the fail column address FCA stored in the storage unit  1422 . If the access address matches the fail row address FRA and the fail column address FCA, whether to perform a data line repair (DLR) operation, wherein memory cells of the FCS cell array  1414 , which correspond to the fail column address FCA, are replaced with redundancy cells of the redundancy cell array  1416 , may be quickly determined. 
         [0175]    The redundancy cell array  1416  may be used to repair a column connected to the fail cell of the normal cell array  1412 . The redundancy cell array  1416  may include redundancy cells for repairing a fail cell. In order to repair a fail cell, the redundancy cell array  1416  may use redundancy cells in units of a data line or bit line connected to the fail cell. 
         [0176]    The control logic unit  1420  may determine whether an access address applied from an external source outside the memory device  1400  addresses the fail cell. The control logic unit  1420  may store the fail row address FRA or the fail column address FCA generated in the normal cell array  1412 . The control logic unit  1420  compares the access address applied from the external source with the fail row address FRA and the fail column address FCA, and determine whether to perform a DLR operation based on a result of the comparison. The control logic unit  1420  may include the storage unit  1422  that stores the fail row address FRA and the fail column address FCA, and the comparator  1424  that compares the fail column address FCA output from the FCA cell array  1414  with the access column address CA[0:n]. 
         [0177]    The storage unit  1422  may store the fail row address FRA and the fail column address FCA for a fail cell in the normal cell array  1412 . The fail row address FRA and the fail column address FCA may be obtained during a test process while manufacturing the memory device  1400 . The fail row address FRA and the fail column address FCA may be stored in the storage unit  1422  when the memory device  1400  is shipped. 
         [0178]    During initialization according to power-up of the memory device  1400 , the storage unit  1422  may enable a word line of the memory cell array  1410 , which corresponds to the fail row address FRA. The storage unit  1422  may store the fail column address FCA in memory cells of the FCS cell array  1414 , which are connected to a word line of the fail row address FRA. 
         [0179]    According to some embodiments, the storage unit  1422  may be a one-time programmable memory, such as a laser-programmable fuse array, an anti-fuse array, or an electric programmable fuse array, or may be a nonvolatile memory device, such as MRAM, RRAM, PRAM, or a flash memory. 
         [0180]    The comparator  1424  may receive the access column address CA[0:n], and receive the fail column address FCA from the FCS cell array  1414 . If the access column address CA[0:n] and the fail column address FCA match each other, the comparator  1424  may output a DLR control signal DLR_CNTL. The DLR control signal DLR_CNTL may be provided to the redundancy control circuit  1430  such that a column of the normal cell array  1412 , which corresponds to the fail column address FCA, is replaced with a column of the redundancy cell array  1416 . 
         [0181]    In response to the DLR control signal DLR_CNTL, the redundancy control circuit  1430  may replace the column of the normal cell array  1412 , which corresponds to the fail column address FCA, with the column of the redundancy cell array  1416 . The redundancy control circuit  1430  may replace the column corresponding to the fail column address FCA with the column of the redundancy cell array  1416  in units of a data line or bit line. 
         [0182]      FIG. 15  is a flowchart of a method of operating the memory device  1400  of  FIG. 14 . 
         [0183]    Referring to  FIG. 15  and  FIG. 14 , the memory cells of the memory cell array  1410  may be determined to be good or bad during a test process of the memory device  1400 . The memory device  1400  may store the fail cell information, i.e., the fail row address FRA and the fail column address FCA of the fail cell screened during the test process, in the storage unit  1422 , in operation S 1510 . 
         [0184]    The memory device  1400  may perform initialization according to power-up when power is supplied. The memory device  1400  may copy and store the fail cell information stored in the storage unit  1422 , in the FCS cell array  1414  of the memory cell array  1410 , during the initialization, in operation S 1520 . The memory device  1400  may enable a word line of the memory cell array  1410 , which corresponds to the fail row address FRA of the storage unit  1422 , and may store the fail column address FCA of the storage unit  1422  in the memory cells of the FCA cell array  1414 , which are connected to the word line of the fail row address FRA. The FCS cell array  1414  will periodic refresh the data stored therein in operation S 1525 . While shown sequentially in the flow chart of  FIG. 15 , it will be understood that the refresh operation is a separate periodic operation. 
         [0185]    The memory device  1400  may receive the access address together with a write or read command from a memory controller or a memory buffer, in operation S 1530 . 
         [0186]    The memory device  1400  may determine whether the access address matches a fail address of the FCS cell array  1414 , in operation S 1540 . 
         [0187]    If it is determined that an access row address matches the fail row address FRA of the fail cell in operation S 1540 , a word line of the memory cell array  1410 , which corresponds to the fail row address FRA, may be enabled. The fail column address FCA stored in the memory cells of the FCS cell array  1414 , which are connected to the word line of the fail row address FRA, may be read and provided to the comparator  1424 . The comparator  1424  may compare and determine whether the fail column address FCA and the access column address CA[0:n] match each other. 
         [0188]    If it is determined that the fail column address FCA and the access column address CA[0:n] match each other in operation S 1540 , the memory device  1400  may perform the access operation with the DLR operation in operation S 1550  by replacing the column of the FCS cell array  1414 , which corresponds to the fail column address FCA, with the column of the redundancy cell array  1416 . 
         [0189]    If the access column address CA[0:n] and the fail column address FCA match each other, the comparator  1424  may generate and provide the DLR control signal DLR_CNTL to the redundancy control circuit  1430 . In response to the DLR control signal DLR_CNTL, the redundancy control circuit  1430  may replace the column corresponding to the fail column address FCA with the column of the redundancy cell array  1416  in units of a data line or bit line. 
         [0190]    The memory device  1400  may perform a write or read operation on memory cells of the redundancy cell array  1416 , which corresponds to the access address that is repaired via the DLR operation. 
         [0191]    If it is determined that the fail column address FCA and the access column address CA[0:n] do not match each other in operation S 1540 , the memory device  1400  may perform a write or read operation on memory cells of the normal cell array  1412 , which corresponds to the access address, without the DLR operation in operation S 1560 . 
         [0192]    According to the method of the current embodiment, the fail row address FRA and the fail column address FCA stored in the storage unit  1422  may be copied and stored in the FCS cell array  1414  during the initialization of the memory device  1400 . The fail row address FRA and the fail column address FCA stored in the FCS cell array  1414  may be compared with the access address for performing the write or read operation of the memory device  1400 , and whether to perform the DLR operation on the memory cells corresponding to the access address may be determined based on a result of the comparison. 
         [0193]    According to the method, the comparison result may be quickly obtained since only the access column address of the access address is compared with the fail column address FCA, and the access row address of the access address is not used. Also, since the access column address is compared with the fail column address FCA output from the FCS cell array  1414 , the comparison result may be obtained quicker than when the access column address is compared with the fail row address FRA and the fail column address FCA of the storage unit  1422 . Based on such a comparison result, the fail cell addressed by the fail row address FRA and the fail column address FCA may be repaired via the DLR operation performed in the units of a data line or bit line. 
         [0194]      FIGS. 16A and 16B  are diagrams for describing the DLR operation performed in units of a data line of the memory device  1400  of  FIG. 14 .  FIGS. 16A and 16B  show the memory device  1400  respectively before and after data lines in 8 bits of the DQ 0  to DQ 7  cell blocks  1601  through  1608  are repaired to data lines in 8 bits of a DLR cell block  1609 . 
         [0195]    Referring to  FIG. 16A , the normal cell array  1412  may include a plurality of normal cell blocks. Each of the normal cell blocks includes a plurality of memory cells arranged in rows and columns. Since data stored in the memory cells of the normal cell blocks is input or output through the data IO pads DQ 0  through DQ 7 , respectively, for convenience of description, the normal cell blocks will now be referred to as the DQ 0  to DQ 7  cell blocks  1601  through  1608 . 
         [0196]    In each of the DQ 0  to DQ 7  cell blocks  1601  through  1608 , rows may include, for example, 8K word lines WL and columns may include, for example, 1K bit lines BL. Memory cells connected to intersections of the word lines WL and the bit lines BL may be DRAM cells indicated by ◯. The memory device  1400  may be set to have a burst length of 8. Accordingly, 8 bit lines BL may be simultaneously selected in the DQ 0  to DQ 7  cell blocks  1601  through  1608 . 
         [0197]    In order to repair the column connected to the fail cell of the normal cell array  1412 , the redundancy cell array  1416  may include, for example, 8K word lines WL, like the DQ 0  to DQ 7  cell blocks  1601  through  1608 . The redundancy cell array  1416  may include 8 bit lines BL, unlike the DQ 0  to DQ 7  cell blocks  1601  through  1608 . The redundancy cell array  1416  may include the DLR cell block  1609  that includes DRAM cells connected to intersections of the 8K word lines WL and the 8 bit lines BL. 
         [0198]    The redundancy control circuit  1430  may include first through eighth switching units  1611  through  1618  that respectively connect the DQ 0  to DQ 7  cell blocks  1601  through  1608  and the first through eighth data lines GIO[0:63], in response to the DLR control signal DLR_CNTL. If the fail column address FCA output from the FCS cell array  1414  of  FIG. 14  and the access column address CA[0:n] do not match each other, the redundancy control circuit  1430  may receive the DLR control signal DLR_CNTL in a deactivated state. 
         [0199]    The redundancy control circuit  1430  may connect the DQ 0  cell block  1601  and the first data lines GIO[0:7] through the first switching unit  1611 , in response to the DLR control signal DLR_CNTL in the deactivated state. Also, the DQ 1  cell block  1602  and the second data lines GIO[8:15] may be connected to each other through the second switching unit  1612 , and the DQ 3  through DQ 8  cell blocks  1603  through  1608  and the third through eighth data lines GIO[16:23] through GIO[56:63] may be connected to each other through the third through eighth switching units  1613  through  1618 , respectively. 
         [0200]    When there is a fail cell (indicated by ) in the DQ 0  to DQ 7  cell blocks  1601  through  1608 , the redundancy control circuit  1430  may receive the DLR control signal DLR_CNTL in an activated state. For example, as shown in  FIG. 16B , a plurality of fail cells may exist in the DQ 1  cell block  1602 . 
         [0201]    Referring to  FIG. 16B , if the fail column address FCA output from the FCS cell array  1414  of  FIG. 14  and the access column address CA[0:n] match each other, the redundancy control circuit  1430  may receive the DLR control signal DLR_CNTL in the activated state. The redundancy control circuit  1430  may connect the DQ 0  cell block  1601  and the first data lines GIO[0:7] to each other through the first switching unit  1611 , in response to the DLR control signal DLR_CNTL in the activated state. The redundancy control circuit  1430  may control the second switching unit  1612  such that the DQ 1  cell block  1602  including the fail cell and the second data lines GIO[8:15] are not connected to each other and the DQ 2  cell block  1603  and the second data lines GIO[8:15] are connected to each other, in response to the DLR control signal DLR_CNTL in the activated state. 
         [0202]    The redundancy control circuit  1430  may connect the DQ 3  cell block  1604  and the third data lines GIO[16:23] to each other through the third switching unit  1613 , connect the DQ 4  cell block  1605  and the fourth data lines GIO[24:31] to each other through the fourth switching unit  1614 , and connect the DQ 5  to DQ 7  cell blocks  1606  through  1608  and the fifth through seventh data lines GIO[32:39] through GIO[48:55] to each other through the fifth through seventh switching units  1615  through  1617 , respectively, in response to the DLR control signal DLR_CNTL in the activated state. Also, the redundancy control circuit  1430  may connect the DLR cell block  1609  and the eighth data lines GIO[56:63] to each other through the eighth switching unit  1618 , in response to the DLR control signal DLR_CNTL in the activated state. 
         [0203]    The memory device  1400  according to the current embodiment performs the DLR operation in units of a data line in 8 bits. According to some embodiments, the DLR operation may be performed in units of a data line in any number of bits, as well as in 8 bits. 
         [0204]      FIGS. 17A and 17B  are diagrams for describing the DLR operation in units of a bit line of the memory device  1400  of  FIG. 14 .  FIGS. 17A and 17B  show the memory device  1400  respectively before and after one bit line of the DQ 0  to DQ 7  cell blocks  1601  through  1608  is repaired by one bit line of the DLR cell block  1609 . 
         [0205]    Referring to  FIG. 17A , the redundancy control circuit  1430  may include a plurality of first through fourth switches  1711  through  1714  that connect bit lines of the DQ 0  to DQ 7  cell blocks  1601  through  1608  to the first through eighth data lines GIO[0:63], respectively, in response to the DLR control signal DLR_CNTL. If the fail column address FCA output from the FCS cell array  1414  of  FIG. 14  and the access column address CA[0:n] do not match each other, the redundancy control circuit  1430  may receive the DLR control signal DLR_CNTL in the deactivated state. 
         [0206]    In response to the DLR control signal DLR_CNTL in the deactivated state, the redundancy control circuit  1430  may connect a bit line BL 0  of the DQ 0  cell block  1601  and the data line GIO[0] to each other through the first switch  1711 . Also, a bit line BL 1  of the DQ 0  cell block  1601  and the data line GIO[1] may be connected to each other through the second switch  1712 , and a bit line BL 2  of the DQ 0  cell block  1601  and the data line GIO[2] may be connected to each other through the third switch  1713 . Then, bit lines of the DQ 0  to DQ 7  cell blocks  1601  through  1608  and the data lines GIO[3] through GIO[62] may be connected to each other through remaining switches, respectively, and a bit line of the DQ 7  cell block  1608  and the data line GIO[63] may be connected to each other through the fourth switch  1714 . 
         [0207]    When there is a fail cell (indicated by ) in the DQ 0  to DQ 7  cell blocks  1601  through  1608 , the redundancy control circuit  1430  may receive the DLR control signal DLR_CNTL in the activated state. For example, the fail cell may exist in the DQ 0  cell block  1601  as shown in  FIG. 17B . 
         [0208]    Referring to  FIG. 17B , if the fail column address FCA output from the FCS cell array  1414  of  FIG. 14  and the access column address CA[0:n] match each other, the redundancy control circuit  1430  may receive the DLR control signal DLR_CNTL in the activated state. In response to the DLR control signal DLR_CNTL in the activated state, the redundancy control circuit  1430  may connect the bit line BL 0  of the DQ 0  cell block  1601  and the data line GIO[0] to each other through the first switch  1711 . 
         [0209]    In response to the DLR control signal DLR_CNTL in the activated state, the redundancy control circuit  1430  may control the second switch  1712  such that the bit line BL 1  connected to the fail cell of the DQ 0  cell block  1601  is not connected to the data line GIO[1] and the bit line BL 2  adjacent to the bit line BL 1  is connected to the data line GIO[1]. Also, in response to the DLR control signal DLR_CNTL in the activated state, the redundancy control circuit  1430  may connect the bit line BL 3  of the DQ 0  cell block  1601  and the data line GIO[2] to each other through the third switch  1713 . 
         [0210]    In response to the DLR control signal DLR_CNTL in the activated state, the redundancy control circuit  1430  may control the first through fourth switches  1711  through  1714  such that bitline, shifted by one bitline as compared to  FIG. 17A , and a data line are connected to each other after skipping a bit line of one fail cell in a symmetrical bit line-data line connection structure. Accordingly, the redundancy control circuit  1430  may control the fourth switch  1714  such that the data line GIO[63] is connected to a redundant bit line RBL of the DLR cell block  1609 . 
         [0211]      FIG. 18  is a diagram of a memory device  1800  capable of quickly repairing a fail cell, according to another embodiment of the inventive concepts. 
         [0212]    Referring to  FIG. 18 , the memory device  1800  may include a control logic  1810 , a refresh address generator  1815 , an address buffer  1820 , a bank control logic  1830 , a row address multiplexer  1840 , a column address latch  1850 , a row decoder  1860  (e.g.,  1860   a - 1860   d ), a column decoder  1870  (e.g.,  1870   a - 1870   d ), a memory cell array  1880  (e.g.,  1880   a - 1880   d ), a sense amplifier  1885  (e.g.,  1885   a - 1885   d ), an input/output (I/O) gating circuit  1890 , a data I/O buffer  1895 , an ECC engine  1802 , and a DLR controller  1804 . The memory device  1800  may selectively include one of the ECC engine  1802  and the DLR controller  1804  or both. 
         [0213]    The memory cell region  1880  may include first through fourth bank arrays  1880   a  through  1880   d . Each of the first through fourth bank arrays  1880   a  through  1880   d  may include a normal cell array, an FCS cell array, an ECC cell array, and a DLR cell array. The normal cell array, the FCS cell array, the ECC cell array, and the DLR cell array may each include a plurality of memory cells arranged in rows and columns. 
         [0214]    The FCS cell array may copy and store fail cell information from a storage unit of the control logic  1810 . The ECC cell array may store ECC parity bits used for an ECC operation performed on data provided to or from fail cells of the normal cell array. The DLR cell array may include redundant cells for repairing the fail cells of the normal cell array via a DLR operation. 
         [0215]    The row decoder  1860  may include first through fourth bank row decoders  1860   a  through  1860   d  respectively connected to the first through fourth bank arrays  1880   a  through  1880   d . The column decoder  1870  may include first through fourth bank column decoders  1870   a  through  1870   d  respectively connected to the first through fourth bank arrays  1880   a  through  1880   d . The sense amplifier  1885  may include first through fourth bank sense amplifiers  1885   a  through  1885   d  respectively connected to the first through fourth bank arrays  1880   a  through  1880   d.    
         [0216]    The first through fourth bank arrays  1880   a  through  1880   d , the first through fourth bank row decoders  1860   a  through  1860   d , the first through fourth bank column decoders  1870   a  through  1870   d , and the first through fourth bank sense amplifiers  1885   a  through  1885   d  may form first through fourth memory banks, respectively. In  FIG. 18 , the memory device  1800  includes four memory banks, but according to some embodiments, the memory device  1800  may include an arbitrary number of memory banks. 
         [0217]    Also, according to some embodiments, the memory device  1800  may be DRAM, such as double data rate synchronous DRAM (DDR SDRAM), low power double data rate (LPDDR) SDRAM, graphic double data rate (GDDR) SDRAM, or Rambus DRAM (RDRAM), or an arbitrary volatile memory device that requires an ECC operation. 
         [0218]    The control logic  1810  may control operations of the memory device  1800 . For example, the control logic  1810  may generate control signals such that the memory device  1800  performs a write operation or a read operation. The control logic  1810  may store fail cell information including a fail cell address of a fail cell generated in the normal cell array, and compare the fail cell address output from the FCS cell array and an access address applied from an external source outside the memory device  1800 . Based on a result of the comparison, the control logic  1810  may generate an ECC control signal and provide the ECC control signal to the ECC engine  1802  to perform an ECC operation. Alternatively, based on the comparison result, the control logic  1810  may generate a DLR control signal and provide the DLR control signal to the DLR controller  1804  to perform a DLR operation. In one embodiment, one of the reserved bits (see  FIGS. 6A and 6B ) may be used to indicate whether to perform the ECC operation or the DLR operation. For example, during the testing phase of manufacture if a wordline (e.g., row) includes too many errors to be corrected by ECC, then this mode selection bit in the reserved bits is set to indicate the DLR mode, otherwise, the mode selection bit in the reserved bits is set to indicated the ECC mode. The control logic may send signals (not shown) to the ECC engine  180  and the DLR controller  1804  to respectively activate and deactivate the ECC engine  180  and the DLR controller  1804 . 
         [0219]    The control logic  1810  may include a command decoder  1811  that decodes a command CMD received from a memory controller, and a mode register  1812  that sets an operation mode of the memory device  1800 . The command decoder  1811  may generate control signals corresponding to the command CMD by decoding a write enable signal/WE, a row address strobe signal/RAS, a column address strobe signal/CAS, or a chip select signal/CS. The command decoder  1811  may receive an error count command ERR CNT from the memory controller. 
         [0220]    The mode register  1812  may provide a plurality of operation options of the memory device  1800  and program various functions, characteristics, and modes of the memory device  1800 . For example, 
         [0221]    The control logic  1810  may further receive differential clocks CK_t and CK_c and a clock enable signal CKE for driving the memory device  1800  in a synchronization manner. Data of the memory device  1800  may be operated at a double data rate. The clock enable signal CKE may be captured at a rising edge of the differential clock CK_t. 
         [0222]    The control logic  1810  may control the refresh address generator  1815  to perform an auto-refresh operation in response to a refresh command, or to perform a self-refresh operation in response to a self-refresh enter command. 
         [0223]    The refresh address generator  1815  may generate a refresh address REF_ADDR corresponding to a memory cell row on which a refresh operation is to be performed. The refresh address generator  1815  may generate the refresh address REF_ADDR in a refresh cycle defined by the standards of volatile memory devices. 
         [0224]    The address buffer  1820  may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller. Also, the address buffer  1820  may provide the received bank address BANK_ADDR to the bank control logic  1830 , provide the received row address ROW_ADDR to the row address multiplexer  1840 , and provide the received column address COL_ADDR to the column address latch  1850 . 
         [0225]    The bank control logic  1830  may generate bank control signals in response to the bank address BANK_ADDR. In response to the bank control signals, a bank row decoder corresponding to the bank address BANK_ADDR from among the first through fourth bank row decoders  1860   a  through  1860   d  may be activated, and a bank column decoder corresponding to the bank address BANK_ADDR from among the first through fourth bank column decoders  1870   a  through  1870   d  may be activated. 
         [0226]    The bank control logic  1830  may generate bank group control signals in response to the bank address BANK_ADDR for determining a bank group. In response to the bank group control signals, row decoders of a bank group corresponding to the bank address BANK_ADDR from among the first through fourth bank row decoders  1860   a  through  1860   d  may be activated, and column decoders of the bank group corresponding to the bank address BANK_ADDR from among the first through fourth bank column decoders  1870   a  through  1870   d  may be activated. 
         [0227]    The row address multiplexer  1840  may receive the row address ROW_ADDR from the address buffer  1820  and the refresh address REF_ADDR from the refresh address generator  1815 . The row address multiplexer  1840  may selectively output the row address ROW_ADDR or the refresh address REF_ADDR. The row address ROW_ADDR output from the row address multiplexer  1840  may be applied to each of the first through fourth bank row decoders  1060   a  through  1060   d.    
         [0228]    The bank row decoder activated by the bank control logic  1830  from among the first through fourth bank row decoders  1860   a  through  1860   d  may decode the row address ROW_ADDR output by the row address multiplexer  1840  and activate a word line corresponding to the row address ROW_ADDR. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address ROW_ADDR. 
         [0229]    The column address latch  1850  may receive the column address COL_ADDR from the address buffer  1820  and temporarily store the received column address COL_ADDR. The column address latch  1850  may gradually increase the column address COL_ADDR in a burst mode. The column address latch  1850  may apply the column address COL_ADDR that is temporarily stored or gradually increased to each of the first through fourth bank column decoders  1870   a  through  1870   d.    
         [0230]    The bank column decoder activated by the bank control logic  1830  from among the first through fourth bank column decoders  1870   a  through  1870   d  may activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I/O gating circuit  1890 . 
         [0231]    The I/O gating circuit  1890  may include, together with circuits for gating I/O data, an input data mask logic, read data latches for storing data output from the first through fourth bank arrays  1880   a  through  1880   d , and write drivers for writing data to the first through fourth bank arrays  1880   a  through  1880   d.    
         [0232]    Data for writing to a memory cell array of one of the first through fourth bank arrays  1880   a  through  1880   d  may be provided from the memory controller to the data I/O buffer  1895  through the memory buffer. The data provided to the data I/O buffer  1895  may be written to one bank array through a write buffer. The data provided to the data I/O buffer  1895  may be transmitted to the ECC engine  1802 . The ECC engine  1802  may generate parity bits with respect to data to be written to the normal cell array. The parity bits generated by the ECC engine  1802  may be stored in the ECC cell array of the bank array. 
         [0233]    Data read from the normal cell array of one of the first through fourth bank arrays  1880   a  through  1880   d  and parity bits read from the ECC cell array may be sensed and amplified by the sense amplifier, and stored in the read data latches. The data stored in the read data latches may be transmitted to the data I/O buffer  1895  and provided to the memory controller through the memory buffer. Also, the data stored in the read data latches may be transmitted to the ECC engine  1802 . The ECC engine  1802  may detect and correct an error bit included in the data read from the normal cell array by using the parity bits. 
         [0234]    In response to the ECC control signal, the ECC engine  1802  may perform the ECC operation on the fail cell of the normal cell array. The ECC engine  1802  may adaptively perform the ECC operation according to an X8 or X4 mode of the memory device  1800 . 
         [0235]    The DLR controller  1804  may replace a column of the normal cell array, which is connected to the fail cell, with a column of the redundancy cell array, in response to the DLR control signal. The DLR controller  1804  may perform the DLR operation in units of a data line or bit line. 
         [0236]    Again as described above, the ECC engine  1802  or the DLR controller  1804  will be respectively activated or deactivated based on a mode control bit in the reserved bits for the wordline (i.e., row) being addressed. 
         [0237]      FIG. 19  is a block diagram of a mobile system  1900  to which a first memory device  1930  capable of quickly repairing a fail cell is applied, according to an embodiment of the inventive concepts. 
         [0238]    Referring to  FIG. 19 , the mobile system  1900  may include an application processor  1910 , a connectivity unit  1920 , the first memory device  1930 , a second memory device  1940 , a user interface  1950 , and a power supply source  1960 , which are connected to each other via a bus  1902 . The first memory device  1930  may be a volatile memory device, and the second memory device  1940  may be a nonvolatile memory device. According to some embodiments, the mobile system  1900  may be an arbitrary mobile system, such as a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, or a navigation system. 
         [0239]    The application processor  1910  may execute applications that provide an Internet browser, a game, and/or a video. According to some embodiments, the application processor  1910  may include a single core or a multi-core processor. For example, the application processor  1910  may include a dual-core, a quid-core, a hexa-core processor, etc. Also, according to some embodiments, the application processor  1910  may further include an internal or external cache memory. 
         [0240]    The connectivity unit  1920  may perform wireless communication or wired communication with an external apparatus. For example, the connectivity unit  1920  may perform Ethernet communication, near field communication (NFC), radio frequency identification (RFID) communication, mobile telecommunication, memory card communication, or universal serial bus (USB) communication. For example, the connectivity unit  1920  may include a baseband chipset, and may support communication, such as global system for mobile communication (GSM), gross rating points (GRPS), wideband code division multiple access (WCDMA), high speed packet access (HSxPA), etc. 
         [0241]    The first memory device  1930  that is a volatile memory device may store data processed by the application processor  1910  or may operate as a working memory. The first memory device  1930  may include a memory cell array that stores fail cell information about a fail cell in some of a plurality of memory cells, and an ECC engine that performs an ECC operation on the fail cell. The memory cell array may store parity bits with respect to the fail cell in some of the other memory cells. The first memory device  1930  may include a storage unit that stores the fail cell information about the fail cell generated in the memory cell array, wherein the storage unit may store the fail cell information in some of the memory cells during initialization of the first memory device  1930 . The first memory device  1930  may include a comparator that outputs a control signal based on a result of comparing the fail cell information read from the some of the memory cells with an access address received from an external source outside the first memory device  1930 , and the ECC engine may perform the ECC operation in response to the control signal. 
         [0242]    The first memory device  1930  may include the memory cell array that stores the fail cell information in the some of the memory cells, and a redundancy control circuit that performs a DLR operation to repair the fail cell. The first memory device  1930  may include the storage unit that stores the fail cell information about the fail cell generated in the memory cell array, wherein the storage unit stores the fail cell information in the some of the memory cells during the initialization of the first memory device  1930 . The first memory device  1930  may include the comparator that outputs a control signal based on a result of comparing the fail cell information read from the some of the memory cells with the access address received from the external source outside the first memory device  1930 , and the redundancy control circuit may perform the DLR operation in response to the control signal. 
         [0243]    The second memory device  1940  that is a nonvolatile memory device may store a boot image for booting the mobile system  1900 . For example, the second memory device  1940  may be electrically erasable programmable read-only memory (EEPROM), a flash memory, phase change random access memory (PRAM), resistance random access memory (RRAM), nano-floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), a memory similar thereto, etc. 
         [0244]    The user interface  1950  may include at least one input device, such as a keypad or a touch screen, and/or at least one output device, such as a speaker a display device, etc. The power supply source  1960  may supply an operation voltage. Also, according to some embodiments, the mobile system  1900  may further include a camera image processor (CIP), and may further include a storage device, such as a memory card, a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. 
         [0245]      FIG. 20  is a block diagram of a computing system  2000  to which a memory device  2040  capable of quickly repairing a fail cell is applied, according to an embodiment of the inventive concepts. 
         [0246]    Referring to  FIG. 20 , the computing system  2000  includes a processor  2010 , an I/O hub (IOH)  2020 , an I/O controller hub (ICH)  2030 , the memory device  2040 , and a graphics card  2050 . According to some embodiments, the computing system  2000  may be an arbitrary computing system, such as a personal computer (PC), a server computer, a workstation, a laptop, a mobile phone, a smart phone, a PDA, a PMP, a digital camera, a digital television (DTV), a set-top box, a music player, a portable game console, or a navigation system. 
         [0247]    The processor  2010  may execute various computing functions, such as certain calculations or tasks. For example, the processor  2010  may be a microprocessor or a CPU. According to some embodiments, the processor  2010  may include a single core or a multi-core processor. For example, the processor  2010  may include a dual-core, a quad-core, or a hexa-core processor. Also, in  FIG. 20 , the computing system  2000  includes one processor  2010 , but according to embodiments, the computing system  2000  may include a plurality of the processors  2010 . Also, according to some embodiments, the processor  2010  may further include an internal or external cache memory. 
         [0248]    The processor  2010  may include a memory controller  2011  that controls operations of the memory device  2040 . The memory controller  2011  included in the processor  2010  may be referred to as an integrated memory controller (IMC). According to some embodiments, the memory controller  2011  may be disposed inside the IOH  2020 . The IOH  2020 , including the memory controller  2011 , may be referred to as a memory controller hub (MCH). 
         [0249]    The memory device  2040  may include a memory cell array that stores fail cell information about a fail cell in some of a plurality of memory cells, and an ECC engine that performs an ECC operation on the fail cell. The memory cell array may store parity bits with respect to the fail cell in some of the other memory cells. The memory device  2040  may include a storage unit that stores the fail cell information about the fail cell generated in the memory cell array, wherein the storage unit may store the fail cell information in some of the memory cells during initialization of the memory device  2040 . The memory device  2040  may include a comparator that outputs a control signal based on a result of comparing the fail cell information read from the some of the memory cells with an access address received from an external source outside the memory device  2040 , and the ECC engine may perform the ECC operation in response to the control signal. 
         [0250]    The memory device  2040  may include the memory cell array that stores the fail cell information in the some of the plurality of memory cells, and a redundancy control circuit that performs a DLR operation to repair the fail cell. The memory device  2040  may include the storage unit that stores the fail cell information about the fail cell generated in the memory cell array, wherein the storage unit stores the fail cell information in the some of the memory cells during the initialization of the memory device  2040 . The memory device  2040  may include the comparator that outputs a control signal based on a result of comparing the fail cell information read from the some of the memory cells with the access address received from the external source outside the memory device  2040 , and the redundancy control circuit may perform the DLR operation in response to the control signal. 
         [0251]    The memory device  2040  may output an error signal to notify the computing system  2000  about an error generated while the computing system  2000  is being used. Then, the computing system  2000  may replace the memory device  2040  if the memory device  2040  is determined to be unsuitable based on the error signal and a number of times the ECC operation is performed. As such, the computing system  2000  may replace the memory device  2040  before a system malfunction is caused by the memory device  2040 , and thus stable system operation may be guaranteed. 
         [0252]    The IOH  2020  may manage data transmission between apparatuses, such as the graphics card  2050 , and the processor  2010 . The IOH  2020  may be connected to the processor  2010  via any type of interface. For example, the IOH  2020  and the processor  2010  may be connected to each other via an interface according to any of various standards, such as a front side bus (FSB), a system bus, a HyperTransport, a lighting data transport (LDT), a quick pth interconnect (QPI), a common system interface, and peripheral component interface-express (CSI). In  FIG. 20 , the computing system  2000  includes one IOH  2020 , but according to some embodiments, the computing system  2000  may include a plurality of the IOHs  2020 . 
         [0253]    The IOH  2020  may provide various interfaces with apparatuses. For example, the IOH  2020  may provide an accelerated graphics port (AGP) interface, a peripheral component interface-express (PCIe) interface, a communication streaming architecture (CSA) interface, etc. 
         [0254]    The graphics card  2050  may be connected to the IOH  2020  through AGP or PCIe. The graphics card  2050  may control a display device (not shown) for displaying an image. The graphics card  2050  may include an internal processor and an internal semiconductor memory device for processing image data. According to some embodiments, the IOH  2020  may include a graphics device therein together with or instead of the graphics card  2050  disposed outside the IOH  2020 . The graphics device included in the IOH  2020  may be referred to as integrated graphics. Also, the IOH  2020 , including a memory controller and a graphics device, may be referred to as a graphics and memory controller hub (GMCH). 
         [0255]    The ICH  2030  may perform data buffering and interface arbitration such that various system interfaces efficiently operate. The ICH  2030  may be connected to the IOH  2020  through an internal bus. For example, the IOH  2020  and the ICH  2030  may be connected to each other via a direct media interface (DMI), a hub interface, an enterprise Southbridge interface (ESI), or PCIe. 
         [0256]    The ICH  2030  may provide various interfaces with peripheral devices. For example, the ICH  2030  may provide a USB port, a serial advanced technology attachment (SATA), a general purpose I/O (GPIO), a low pin count (LPC) bus, a serial peripheral interface (SPI), PCI, PCIe, etc. 
         [0257]    According to some embodiments, at least two of the processor  2010 , the IOH  2020 , and the ICH  2030  may be realized in one chipset. 
         [0258]    While the inventive concepts has been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.