Abstract:
A processor includes an arithmetic device, a storage device that holds arithmetic data, a data generator that generates test data, an address generator that generates an address at which the test data is to be written, a test data number counter that counts a number of test data, an error information holder that holds mismatch error information, an error occurrence bit position holder that holds a position of a bit at which a mismatch error has occurred, an error occurrence test data number holder that holds number of test data counted by the test data number counter, and a comparator that compares test data written to the storage device with test data read from the storage device and stores error information in the error information holder and a position of a bit and number of the test data in which the mismatch error has occurred.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2008-308419, filed on Dec. 3, 2008, the entire contents of which are incorporated by reference herein. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    The present invention relates to a processor and a method for controlling storage-device test unit. 
         [0004]    2. Description of the Related Art 
         [0005]    Recently, the degree of integration of large scale integration (LSI) circuits has been increasing, and the capacity and the number of random access memories (RAMs) included in LSI circuits have been increasing. Accordingly, the number of test patterns for RAM and the test time of RAM tests have also been increasing. 
         [0006]    In LSI circuits, many built-in self-test (BIST) circuits are currently used in testing RAMs included in the LSI circuits. 
         [0007]    A BIST circuit includes a pattern generator for generating a test pattern for testing a RAM in an LSI circuit and an address and a control signal for reading/writing the test pattern, and a comparator for comparing the test results. By externally performing the minimum setting of the pattern generator, the BIST circuit automatically tests the RAM and holds the comparison result therein. After the test is completed, the BIST circuit outputs the test result to the outside, and the good or bad of the RAM is checked. 
         [0008]    Accordingly, the number of test patterns and the test time can be significantly reduced, compared with a method of reading the details held in the RAM to the outside and comparing the results. 
         [0009]      FIG. 17  is a circuit diagram of a known RAM and a known BIST circuit. 
         [0010]    An LSI circuit  10  includes a RAM  11  and a BIST circuit  12 . 
         [0011]    The BIST circuit  12  includes a pattern generator  21 , a comparator  25 , an address holding circuit  26 , a bit position holding circuit  27 , and an error flag holding circuit  28 . 
         [0012]    The pattern generator  21  includes a sequencer  22 , a data generator  23 , and an address generator  24 . 
         [0013]    The sequencer  22  generates a predetermined pattern sequence that is a set of a combination of multiple test patterns and an address. The sequencer  22  also outputs a control signal based on the pattern sequence to the RAM  11  and the comparator  25 . 
         [0014]    The data generator  23  outputs data to be written to the RAM  11  at the time of writing a test pattern or outputs data (expected value) expected to be read from the RAM  11  at the time of reading a test pattern. 
         [0015]    The address generator  24  generates an address of data to be written to the RAM  11  or generates an address to be read from the RAM  11 , and outputs the address to the RAM  11  and the address holding circuit  26 . 
         [0016]    The comparator  25  compares the data read from the RAM  11  (read data) with the expected value output from the data generator  23 . When the read data does not match the expected value, the comparator  25  outputs a signal that instructs the address holding circuit  26  to hold the address to the address holding circuit  26 , outputs the bit position of the mismatch to the bit position holding circuit  27 , and outputs an error flag that indicates the occurrence of an error to the error flag holding circuit  28 . 
         [0017]    The address holding circuit  26  stores the address in the RAM  11  where the error has occurred, on the basis of the instruction from the comparator  25 . 
         [0018]    The bit position holding circuit  27  stores the bit position output from the comparator  25 . 
         [0019]    The error flag holding circuit  28  stores the flag indicating whether the RAM  11  has an error. 
         [0020]    The good or bad check of the RAM  11  is conducted by reading the error flag from the error flag holding circuit  28  after the test. 
         [0021]    The error flag indicates the presence of the defective RAM  11  but does not specify the defective portion. Thus, in addition to the error flag, the address information stored in the address holding circuit  26  and the bit position stored in the bit position holding circuit  27  are used as information for specifying the defective portion. 
         [0022]    The RAM  11 , the comparator  25 , the address holding circuit  26 , the bit position holding circuit  27 , and the error flag holding circuit  28  constitute a RAM-comparison/result holder  30 . 
         [0023]    When the LSI circuit  10  includes multiple RAMs (e.g., six RAMs), as illustrated in  FIG. 18 , multiple RAM-comparison/result holders  30 - k  ( k = 1  to  6 ) are connected to the single pattern generator  21 . 
         [0024]    Related art includes Japanese Unexamined Patent Application Publication NOs. 2004-86996 and 2006-38782. 
         [0025]    [Patent Document 1] Japanese Laid-Open Patent Publication No. 2004-86996 
         [0026]    [Patent Document 2] Japanese Laid-Open Patent Publication No. 2006-38782 
       SUMMARY 
       [0027]    According to an aspect of the invention, a processor includes an arithmetic device, a storage device that holds arithmetic data, a data generator that generates test data, an address generator that generates an address at which the test data is to be written, a test data number counter that counts a number of test data, an error information holder that holds mismatch error information, an error occurrence bit position holder that holds a position of a bit at which a mismatch error has occurred, an error occurrence test data number holder that holds number of test data counted by the test data number counter, and a comparator that compares test data written to the storage device with test data read from the storage device and stores error information in the error information holder and a position of a bit and number of the test data in which the mismatch error has occurred. 
         [0028]    The above-described embodiments of the present invention are intended as examples, and all embodiments of the present invention are not limited to including the features described above. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0029]      FIG. 1  is a block diagram of a processor according to a first embodiment; 
           [0030]      FIG. 2  is a detailed diagram of a RAM and a BIST circuit according to the first embodiment; 
           [0031]      FIG. 3  is a diagram illustrating a pattern sequence and a pattern number according to the first embodiment; 
           [0032]      FIG. 4A  is a diagram illustrating the format of a pattern number; 
           [0033]      FIG. 4B  is a diagram illustrating the format of a bit position; 
           [0034]      FIG. 4C  is a diagram illustrating the format of an error flag; 
           [0035]      FIG. 5  is a flowchart of a process performed by the BIST circuit according to the first embodiment; 
           [0036]      FIG. 6  is a diagram illustrating a modification of the processor according to the first embodiment; 
           [0037]      FIG. 7  is a block diagram of a processor according to a second embodiment; 
           [0038]      FIG. 8A  is a detailed diagram (upper portion) of RAMs and a BIST circuit according to the second embodiment; 
           [0039]      FIG. 8B  is a detailed diagram (lower portion) of the RAMs and the BIST circuit according to the second embodiment; 
           [0040]      FIG. 9  is a flowchart of a process performed by the BIST circuit according to the second embodiment; 
           [0041]      FIG. 10A  is a diagram (upper portion) illustrating a modification of the processor according to the second embodiment; 
           [0042]      FIG. 10B  is a diagram (lower portion) illustrating the modification of the processor according to the second embodiment; 
           [0043]      FIG. 11  is a block diagram of a processor according to a third embodiment; 
           [0044]      FIG. 12  is a detailed diagram of a RAM and a BIST circuit according to the third embodiment; 
           [0045]      FIG. 13  is a diagram illustrating a pattern sequence and an expected value number according to the third embodiment; 
           [0046]      FIG. 14  is a diagram illustrating the format of an expected value number; 
           [0047]      FIG. 15  is a flowchart of a process performed by the BIST circuit according to the third embodiment; 
           [0048]      FIG. 16  is a diagram illustrating a modification of the processor according to the third embodiment; 
           [0049]      FIG. 17  is a block diagram of a known RAM and a known BIST circuit; 
           [0050]      FIG. 18  is a block diagram of an LSI circuit including multiple RAMs; and 
           [0051]      FIG. 19  is a diagram illustrating a pattern sequence used in a RAM test. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0052]    Reference may now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. 
         [0053]    Hereinafter embodiments will be described with reference to the drawings. In the following description, portions given the same reference numerals in the drawings represent the same portions and have similar operations, and descriptions of these portions may be omitted. 
         [0054]      FIG. 1  is a block diagram of a processor according to a first embodiment. 
         [0055]    A processor  101  includes an arithmetic unit  102 , a RAM  103 , and a BIST circuit  104 . 
         [0056]    The processor  101  is an LSI circuit in, for example, a central processing unit (CPU), a digital signal processor (DSP), or a microcontroller. 
         [0057]    The arithmetic unit  102  performs arithmetic processing in the processor  101 . 
         [0058]    The RAM  103  stores data used in the arithmetic unit  102 . 
         [0059]    The BIST circuit  104  is a built-in self-test circuit that tests the RAM  103 . 
         [0060]      FIG. 2  is a detailed diagram of a RAM and a BIST circuit according to the first embodiment. 
         [0061]    The arithmetic unit  102  is not illustrated in  FIG. 2 . 
         [0062]    The RAM  103  reads/writes specified data at a specified address on the basis of a reading/writing control signal. In the present embodiment, for example, the RAM  103  has 1024 addresses and stores 72-bit data at each address. 
         [0063]    The BIST circuit  104  includes a pattern generator  201 , a comparator  211 , a bit position holding circuit  212 , and an error flag holding circuit  213 . 
         [0064]    The pattern generator  201  includes a sequencer  202 , a data generating circuit  203 , an address generating circuit  204 , a pattern counter  205 , and a pattern number holding circuit  206 . 
         [0065]    In the first embodiment, the pattern generator  201  generates a pattern sequence, as illustrated in  FIG. 3 . In  FIG. 3 , the memory address is plotted in ordinate and the time is plotted in abscissa. “WO” denotes writing 0 to the memory, and “W 1 ” denotes writing 1 to the memory. “R 0 ” denotes reading data and checking whether the data is 0, and “R 1 ” denotes reading data and checking whether the data is 1. 
         [0066]    What type of pattern sequence is to be used in a RAM test is set in advance or instructed from the outside of the LSI. Therefore, the user can be informed of what type of pattern sequence is used. Referring again to  FIG. 2 , the pattern generator  201  generates a predetermined pattern sequence on the basis of the setting or the instruction. 
         [0067]    The sequencer  202  generates a preset pattern sequence. The sequencer  202  also outputs a control signal based on the pattern sequence to the RAM  103  and the comparator  211 . 
         [0068]    The data generating circuit  203  outputs data to be written to the RAM  103  at the time of writing a test pattern or data (expected value) expected to be read from the RAM  103  at the time of reading a test pattern. The expected value is data previously written at the address in the RAM  103  that is read at the time of reading the pattern. 
         [0069]    The address generating circuit  204  includes an address counter  207 . 
         [0070]    The address counter  207  generates an address of data to be written to the RAM  103  or an address of data to be read from the RAM  103 , and outputs the address to the RAM  103 . 
         [0071]    The pattern counter  205  increments the pattern number every time a pattern is generated, and outputs the current pattern number to the pattern number holding circuit  206 . As illustrated in  FIG. 3 , one pattern number corresponds to one test pattern. For example, in  FIG. 3 , pattern number  0  corresponds to the first test pattern of a pattern sequence of writing data  0  to address  0 . 
         [0072]    Referring again to  FIG. 2 , the pattern number holding circuit  206  stores the pattern number output from the pattern counter  205 , upon receipt of a pattern number holding signal output from the comparator  211 . In the present embodiment, when the pattern sequence illustrated in  FIG. 3  is executed, six accesses are established to one address. Therefore, the total number of test patterns is 1024×6=6144, and the number of bits necessary for holding a pattern number is 13. Thus, in the present embodiment, the format of a pattern number is a 13-bit format, as illustrated in  FIG. 4A . 
         [0073]    The comparator  211  compares the data read from the RAM  103  (read data) with the expected value output from the data generating circuit  203 . When the read data does not match the expected value, the comparator  211  outputs a signal that instructs the pattern number holding circuit  206  to hold the pattern number (pattern number holding signal) to the pattern number holding circuit  206 , outputs the bit position of the mismatch to the bit position holding circuit  212 , and outputs an error flag that indicates the occurrence of an error to the error flag holding circuit  213 . 
         [0074]    The bit position holding circuit  212  stores the bit position output from the comparator  211 . In the present embodiment, the number of bits of the RAM  103  is 72 bits. Thus, the format of a bit position is a 72-bit format, as illustrated in  FIG. 4B . 
         [0075]    The error flag holding circuit  213  stores the flag indicating whether the RAM  103  has an error, which is output from the comparator  211 . In the present embodiment, the format of an error flag is a 1-bit format, as illustrated in  FIG. 4C . 
         [0076]      FIG. 5  is a flowchart of a process performed by the BIST circuit according to the first embodiment. 
         [0077]    In operation S 501 , the sequencer  202  causes the data generating circuit  203  to generate a predetermined test pattern. On the basis of the instruction from the sequencer  202 , the data generating circuit  203  outputs the test pattern to the RAM  103  and the comparator  211 . The address counter  207  outputs an address to be read or written to the RAM  103 . The pattern counter  205  increments the pattern number and outputs the current pattern number to the pattern number holding circuit  206 . 
         [0078]    In operation S 502 , the RAM  103  determines whether the RAM  103  is instructed to perform reading on the basis of the control signal from the sequencer  202 . When the RAM  103  is instructed to perform reading, the flow proceeds to operation S 503 . When the RAM  103  is instructed to perform writing, the flow proceeds to operation S 506 . 
         [0079]    In operation S 503 , the RAM  103  reads data at the address specified by the address generating circuit  204 , and outputs the data to the comparator  211 . 
         [0080]    In operation S 504 , the comparator  211  compares the data read from the RAM  103  (read data) with the expected value output from the data generating circuit  203 . When the read data matches the expected value, the flow proceeds to operation S 507 . When the read data does not match the expected value, the flow proceeds to operation S 505 . 
         [0081]    In operation S 505 , the comparator  211  outputs a pattern number holding signal that gives an instruction to hold the current pattern number, namely, the pattern number in which the error has occurred, to the pattern number holding circuit  206 . The pattern number holding circuit  206  stores the pattern number. The comparator  211  also outputs the bit position at which the error has occurred to the bit position holding circuit  212 . The bit position holding circuit  212  stores the received bit position. The comparator  211  further outputs an error occurrence signal indicating that the error has occurred to the error flag holding circuit  213 . The error flag holding circuit  213  stores an error flag indicating that the error has occurred. 
         [0082]    In operation S 506 , the RAM  103  writes the data received from the data generating circuit  203  at the address received from the address generating circuit  204 . 
         [0083]    In operation S 507 , the sequencer  202  determines whether the pattern is the final pattern. When the pattern is the final pattern, the process is terminated. When the pattern is not the final pattern, the flow returns to operation S 501 . 
         [0084]    According to the processor of the first embodiment, a pattern number in which an error has occurred can be detected. By applying the pattern number to a pattern sequence used in a RAM test, the position in the pattern sequence at which the error has occurred can be detected. Accordingly, more detailed failure analysis can be conducted. 
         [0085]      FIG. 6  is a diagram illustrating a modification of the processor according to the first embodiment. 
         [0086]    The arithmetic unit  102  is not illustrated in  FIG. 6 . 
         [0087]    In the modification of the processor according to the first embodiment, the processor  101  further includes a scan control circuit  601 , a scan in terminal  602 , and a scan out terminal  603 . 
         [0088]    The scan in terminal  602  is connected to the pattern number holding circuit  206 , and scan in data is input to the pattern number holding circuit  206 . 
         [0089]    The scan out terminal  603  is connected to the error flag holding circuit  213 , and scan out data is output from the error flag holding circuit  213  to the scan out terminal  603 . 
         [0090]    The pattern number holding circuit  206  is connected to the bit position holding circuit  212 , and scan data from the pattern number holding circuit  206  is input to the bit position holding circuit  212 . The bit position holding circuit  212  is connected to the error flag holding circuit  213 , and scan data from the bit position holding circuit  212  is input to the error flag holding circuit  213 . Accordingly, a scan chain is realized by connecting the scan in terminal  602 , the pattern number holding circuit  206 , the bit position holding circuit  212 , the error flag holding circuit  213 , and the scan out terminal  603  in this order. Also, the scan control circuit  601  is connected to the pattern number holding circuit  206 , the bit position holding circuit  212 , and the error flag holding circuit  213 . 
         [0091]    A scan control signal is input to the scan control circuit  601 . The scan control circuit  601  outputs a control signal that controls a scan operation to the pattern number holding circuit  206 , the bit position holding circuit  212 , and the error flag holding circuit  213 . 
         [0092]    Under control of the scan control circuit  601 , data stored in the pattern number holding circuit  206 , the bit position holding circuit  212 , and the error flag holding circuit  213  is read to the outside as scan out data via the scan chain. 
         [0093]    Next, the case where multiple RAMs are mounted will be described. 
         [0094]      FIG. 7  is a block diagram of a processor according to a second embodiment. 
         [0095]    A processor  701  includes an arithmetic unit  702 , RAMs  703 - i  ( i = 1  to  n ), and a BIST circuit  704 . 
         [0096]    The processor  701  is an LSI circuit in, for example, a CPU, a DSP, or a microcontroller. 
         [0097]    The arithmetic unit  702  performs arithmetic processing in the processor  701 . 
         [0098]    The RAMs  703 - i  store data used in the arithmetic unit  702 . 
         [0099]    The BIST circuit  704  is a built-in self-test circuit that tests the RAMs  703 - i.    
         [0100]    The processor  701  according to the second embodiment includes the multiple RAMs  703 - i.    
         [0101]      FIGS. 8A and 8B  are diagrams illustrating the detailed upper and lower portions of RAMs and a BIST circuit according to the second embodiment. 
         [0102]    The arithmetic unit  702  is not illustrated in  FIGS. 8A and 8B . 
         [0103]    The RAMs  703 - i  are the same as the RAM  103  in the first embodiment. 
         [0104]    The BIST circuit  704  includes a pattern generator  801 , comparators  811 - i  ( i = 1  to  n ), bit position holding circuits  812 - i  ( i = 1  to  n ), error flag holding circuits  813 - i  ( i = 1  to  n ), and pattern number holding circuits  806 - i  ( i = 1  to  n ). 
         [0105]    The pattern generator  801  includes a sequencer  802 , a data generating circuit  803 , an address generating circuit  804 , and a pattern counter  805 . 
         [0106]    The address generating circuit  804  includes an address counter  807 . 
         [0107]    The sequencer  802 , the data generating circuit  803 , the address generating circuit  804 , the pattern counter  805 , and the address counter  807  are the same as the sequencer  202 , the data generating circuit  203 , the address generating circuit  204 , the pattern counter  205 , and the address counter  207  in the first embodiment. 
         [0108]    The comparators  811 - i , the bit position holding circuits  812 - i , the error flag holding circuits  813 - i , and the pattern number holding circuits  806 - i  are the same as the comparator  211 , the bit position holding circuit  212 , the error flag holding circuit  213 , and the pattern number holding circuit  206  in the first embodiment. 
         [0109]    When compared with the first embodiment, the second embodiment is different in that the pattern number holding circuits  806 - i  ( i = 1  to  n ) are not included in the pattern generator  801 , and the number of the pattern number holding circuits  806 - i  is the same as the number of the RAMs  703 - i  to be tested. 
         [0110]      FIG. 9  is a flowchart of a process performed by the BIST circuit according to the second embodiment. 
         [0111]    In operation S 501 , the sequencer  802  causes the data generating circuit  803  to generate a predetermined test pattern. On the basis of the instruction from the sequencer  802 , the data generating circuit  803  outputs the test pattern to each of the RAMs  703 - i  and each of the comparators  811 - i . The address counter  807  outputs an address to be read or written to the RAM  703 - i . The pattern counter  805  outputs the pattern number to each of the pattern number holding circuits  806 - i.    
         [0112]    In operation S 902 , the RAM  703 - i  determines whether the RAM  703 - i  is instructed to perform reading on the basis of the control signal from the sequencer  802 . When the RAM  703 - i  is instructed to perform reading, the flow proceeds to operation S 903 . When the RAM  703 - i  is instructed to perform writing, the flow proceeds to operation S 906 . 
         [0113]    In operation S 903 , the RAM  703 - i  reads data at the address specified by the address generating circuit  804 , and outputs the data to the comparator  811 - i.    
         [0114]    In operation S 904 , the comparator  811 - i  compares the data read from the RAM  703 - i  (read data) with the expected value output from the data generating circuit  803 . When the read data matches the expected value, the flow proceeds to operation S 907 . When the read data does not match the expected value, the flow proceeds to operation S 905 . 
         [0115]    In operation S 905 , the comparator  811 - i  outputs a pattern number holding signal that gives an instruction to hold the current pattern number, namely, the pattern number in which the error has occurred, to the pattern number holding circuit  806 - i . The pattern number holding circuit  806 - i  stores the pattern number. The comparator  811 - i  also outputs the bit position at which the error has occurred to a corresponding one of the bit position holding circuits  812 - i . The bit position holding circuit  812 - i  stores the received bit position. The comparator  811 - i  further outputs an error occurrence signal indicating that the error has occurred to a corresponding one of the error flag holding circuits  813 - i . The error flag holding circuit  813 - i  stores an error flag indicating that the error has occurred. 
         [0116]    In operation S 906 , the RAM  703 - i  writes the data received from the data generating circuit  803  at the address received from the address generating circuit  804 . 
         [0117]    In operation S 907 , the sequencer  802  determines whether the pattern is the final pattern. When the pattern is the final pattern, the process is terminated. When the pattern is not the final pattern, the flow returns to operation S 901 . 
         [0118]    According to the processor of the second embodiment, a pattern number in which an error has occurred can be detected. By applying the pattern number to a pattern sequence used in a RAM test, the position in the pattern sequence at which the error has occurred can be detected. Accordingly, more detailed failure analysis can be conducted. 
         [0119]    Also, even when multiple RAMs are mounted, only a single pattern generator is required. Therefore, the cost can be reduced. 
         [0120]      FIGS. 10A and 10B  are diagrams illustrating the upper and lower portions of a modification of the processor according to the second embodiment. 
         [0121]    The arithmetic unit  702  is not illustrated in  FIGS. 10A and 10B . 
         [0122]    In the modification of the processor according to the second embodiment, the processor  701  further includes a scan control circuit  1001 , a scan in terminal  1002 , and a scan out terminal  1003 . 
         [0123]    The scan in terminal  1002  is connected to the pattern number holding circuit  806 - 1 , and scan in data is input to the pattern number holding circuit  806 - 1 . 
         [0124]    The scan out terminal  1003  is connected to the error flag holding circuit  813 - n , and scan out data is output from the error flag holding circuit  813 - n  to the scan out terminal  1003 . 
         [0125]    The pattern number holding circuit  806 - 1  is connected to the bit position holding circuit  812 - 1 . The bit position holding circuit  812 - 1  is connected to the error flag holding circuit  813 - 1 . The error flag holding circuit  813 - 1  is connected to the pattern number holding circuit  806 - 2 , . . . . The error flag holding circuit  813 -( n - 1 ) (not illustrated) is connected to the pattern number holding circuit  806 - n . The pattern number holding circuit  806 - n  is connected to the bit position holding circuit  812 - n . The bit position holding circuit  812 - n  is connected to the error flag holding circuit  813 - n.    
         [0126]    Accordingly, a scan chain is realized by connecting the scan in terminal  1002 , the pattern number holding circuit  806 - 1 , the bit position holding circuit  812 - 1 , the error flag holding circuit  813 - 1 , the pattern number holding circuit  806 - 2 , . . . , the error flag holding circuit  813 -( n - 1 ), the pattern number holding circuit  806 - n , the bit position holding circuit  812 - n , the error flag holding circuit  813 - n , and the scan out terminal  1003  in this order. Also, the scan control circuit  1001  is connected to the pattern number holding circuits  806 - i  ( i = 1  to  n ), the bit position holding circuits  812 - i , and the error flag holding circuits  813 - i.    
         [0127]    A scan control signal is input to the scan control circuit  1001 . The scan control circuit  1001  outputs a control signal that controls a scan operation to the pattern number holding circuits  806 - i , the bit position holding circuits  812 - i , and the error flag holding circuits  813 - i.    
         [0128]    Under control of the scan control circuit  1001 , data stored in the pattern number holding circuits  806 - i , the bit position holding circuits  812 - i , and the error flag holding circuit  813 - i  is read to the outside as scan out data via the scan chain. 
         [0129]      FIG. 11  is a block diagram of a processor according to a third embodiment. 
         [0130]    A processor  1101  includes an arithmetic unit  1102 , a RAM  1103 , and a BIST circuit  1104 . 
         [0131]    The processor  1101  is an LSI circuit in, for example, a CPU, a DSP, or a microcontroller. 
         [0132]    The arithmetic unit  1102  performs arithmetic processing in the processor  1101 . 
         [0133]    The RAM  1103  stores data used in the arithmetic unit  1102 . 
         [0134]    The BIST circuit  1104  is a built-in self-test circuit that tests the RAM  1103 . 
         [0135]      FIG. 12  is a detailed diagram of a RAM and a BIST circuit according to the third embodiment. 
         [0136]    The arithmetic unit  1102  is not illustrated in  FIG. 12 . 
         [0137]    The RAM  1103  is the same as the RAM  103  in the first embodiment. 
         [0138]    The BIST circuit  1104  includes a pattern generator  1201 , a comparator  1211 , a bit position holding circuit  1212 , an error flag holding circuit  1213 , an expected value counter  1205 , and an expected value number holding circuit  1206 . 
         [0139]    The pattern generator  1201  includes a sequencer  1202 , a data generating circuit  1203 , and an address generating circuit  1204 . 
         [0140]    The address generating circuit  1204  includes an address counter  1207 . 
         [0141]    The sequencer  1202 , the data generating circuit  1203 , the address generating circuit  1204 , and the address counter  1207  are the same as the sequencer  202 , the data generating circuit  203 , the address generating circuit  204 , and the address counter  207  in the first embodiment. 
         [0142]    In the third embodiment, the pattern generator  1201  generates a pattern sequence that is a set of a combination of multiple test patterns, as illustrated in  FIG. 13 . In  FIG. 13 , the memory address is plotted in ordinate and the time is plotted in abscissa. WO denotes writing 0 to the memory, and W 1  denotes writing 1 to the memory. R 0  denotes reading data and checking whether the data is 0, and R 1  denotes reading data and checking whether the data is 1. 
         [0143]    The bit position holding circuit  1212  and the error flag holding circuit  1213  are the same as the bit position holding circuit  212  and the error flag holding circuit  213  in the first embodiment. 
         [0144]    The comparator  1211  compares the data read from the RAM  1103  (read data) with the expected value output from the data generating circuit  1203 . When the read data does not match the expected value, the comparator  1211  outputs a signal that instructs the expected value number holding circuit  1206  to hold the expected value number (expected value number holding signal) to the expected value number holding circuit  1206 , outputs the bit position of the mismatch to the bit position holding circuit  1212 , and outputs an error flag that indicates the occurrence of an error to the error flag holding circuit  1213 . 
         [0145]    The expected value counter  1205  increments the expected value number every time an instruction to compare the read data with the expected value is given to the comparator  1211 , and outputs the expected value number to the expected value number holding circuit  1206 . As illustrated in  FIG. 13 , one reading corresponds to one expected value number. For example, as illustrated in  FIG. 13 , expected value number  0  corresponds to the first test pattern of reading data in which the expected value is 0 from address  0 . 
         [0146]    The expected value number holding circuit  1206  stores the expected value number output from the expected value counter  1205 , upon receipt of an expected value number holding signal output from the comparator  1211 . In the present embodiment, when the pattern sequence illustrated in  FIG. 13  is executed, three accesses are established to one address. Therefore, the total number of test patterns is 1024×3=3072, and the number of bits necessary for holding an expected value number is 12. Thus, in the present embodiment, the format of an expected value number is a 12-bit format, as illustrated in  FIG. 14 . 
         [0147]      FIG. 15  is a flowchart of a process performed by the BIST circuit according to the third embodiment. 
         [0148]    In operation S 1501 , the sequencer  1202  causes the data generating circuit  1203  to generate a predetermined test pattern. On the basis of the instruction from the sequencer  1202 , the data generating circuit  1203  outputs the test pattern to the RAM  1103  and the comparator  1211 . The address counter  1207  outputs an address to be read or written to the RAM  1103 . 
         [0149]    In operation S 1502 , the RAM  1103  determines whether the RAM  1103  is instructed to perform reading on the basis of the control signal from the sequencer  1202 . When the RAM  1103  is instructed to perform reading, the flow proceeds to operation S 1503 . When the RAM  1103  is instructed to perform writing, the flow proceeds to operation S 1506 . 
         [0150]    In operation S 1503 , the RAM  1103  reads data at the address specified by the address generating circuit  1204 , and outputs the data to the comparator  211 . The expected value counter  1205  increments the expected value number and outputs the current expected value number to the expected value number holding circuit  1206 . 
         [0151]    In operation S 1504 , the comparator  1211  compares the data read from the RAM  1103  (read data) with the pattern (expected value) output from the data generating circuit  1203 . When the read data matches the expected value, the flow proceeds to operation S 1507 . When the read data does not match the expected value, the flow proceeds to operation S 1505 . 
         [0152]    In operation S 1505 , the comparator  1211  outputs an expected value number holding signal that gives an instruction to hold the current expected value number, namely, the expected value number in which the error has occurred, to the expected value number holding circuit  1206 . The expected value number holding circuit  1206  stores the expected value number. The comparator  1211  also outputs the bit position at which the error has occurred to the bit position holding circuit  1212 . The bit position holding circuit  1212  stores the received bit position. The comparator  1211  further outputs an error occurrence signal indicating that the error has occurred to the error flag holding circuit  1213 . The error flag holding circuit  1213  stores an error flag indicating that the error has occurred. 
         [0153]    In operation S 1506 , the RAM  1103  writes the data received from the data generating circuit  1203  at the address received from the address generating circuit  1204 . 
         [0154]    In operation S 1507 , the sequencer  1202  determines whether the pattern is the final pattern. When the pattern is the final pattern, the process is terminated. When the pattern is not the final pattern, the flow returns to operation S 1501 . 
         [0155]    According to the processor of the third embodiment, an expected value number in which an error has occurred can be detected. By applying the expected value number to a pattern sequence used in a RAM test, the position in the pattern sequence at which the error has occurred can be detected. Accordingly, more detailed failure analysis can be conducted. 
         [0156]    Since the expected value number has a fewer number of bits than the pattern number used in the first embodiment, the number of bits of data used can be reduced in the third embodiment. 
         [0157]    Unlike the first and second embodiments, the pattern generator  1201  requires no pattern counter. Thus, a pattern generator that is the same as a known pattern generator can be used in the third embodiment. 
         [0158]      FIG. 16  is a diagram illustrating a modification of the processor according to the third embodiment. 
         [0159]    The arithmetic unit  1102  is not illustrated in  FIG. 16 . 
         [0160]    In the modification of the processor according to the third embodiment, the processor  1101  further includes a scan control circuit  1601 , a scan in terminal  1602 , and a scan out terminal  1603 . 
         [0161]    The scan in terminal  1602  is connected to the error flag holding circuit  1213 , and scan in data is input to the error flag holding circuit  1213 . 
         [0162]    The scan out terminal  1603  is connected to the expected value number holding circuit  1206 , and scan out data is output from the expected value number holding circuit  1206  via the scan out terminal  1603  to the outside. 
         [0163]    The error flag holding circuit  1213  is connected to the bit position holding circuit  1212 , and scan data from the error flag holding circuit  1213  is input to the bit position holding circuit  1212 . The bit position holding circuit  1212  is connected to the expected value number holding circuit  1206 , and scan data from the bit position holding circuit  1212  is input to the expected value number holding circuit  1206 . 
         [0164]    Accordingly, a scan chain is realized by connecting the scan in terminal  1602 , the error flag holding circuit  1213 , the bit position holding circuit  1212 , the expected value number holding circuit  1206 , and the scan out terminal  1603  in this order. Also, the scan control circuit  1601  is connected to the error flag holding circuit  1213 , the bit position holding circuit  1212 , and the expected value number holding circuit  1206 . 
         [0165]    A scan control signal is input to the scan control circuit  1601 . The scan control circuit  601  outputs a control signal that controls a scan operation to the error flag holding circuit  1213 , the bit position holding circuit  1212 , and the expected value number holding circuit  1206 . 
         [0166]    Under control of the scan control circuit  1601 , data stored in the error flag holding circuit  1213 , the bit position holding circuit  1212 , and the expected value number holding circuit  1206  is read to the outside as scan out data via the scan chain. 
         [0167]    Although a few preferred embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.