Abstract:
A method and apparatus for controlling an electrolysis reaction of the type used to produce chlorine gas and sodium hydroxide. Bus voltage and bus current are detected and utilized in connection with a plurality of control parameters. Oscillations in bus current are detected as one control parameter which is a precursor to shorts. The anode/cathode spacing is adjusted in response to the control parameters to avoid or reduce the frequency of shorts, minimize power consumption, and otherwise improve the efficiency of operation.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to the field of electrolysis and specifically to controlling an electrolysis process to minimize power consumption without causing shorts through adjustment of anode/cathode spacing. 
     Many electrolysis processes are well-known and are employed, for example, in the production of sodium hydroxide, chlorine, potassium hydroxide, sodium sulfide and sodium hydrosulfite. 
     An electrolytic cell for the production of chlorine gas, for example, employs an anode immersed in a salt brine and positioned above a cathode formed by a thin layer of mercury on the cell bed. When current is passed through the cell, chlorine gas and sodium amalgam are produced, with hydrogen formation a competing reaction. The reaction for chlorine formation is given by the following expression: ##EQU1## For the usual range of temperatures, concentrations, and pressure, the reversible equilibrium potential (E r ) for the reaction of Eq. (1) is -3.05 volts. Actual cell voltage drops are greater than E r  because of cathode and anode polarization, and ohmic drop through the brine layer, and in electrical conductors and contacts. 
     The value of E r  for the competing hydrogen reaction is lower than for the chlorine reaction, but high overvoltages kinetically limit hydrogen production rates during normal cell operation. Reduction of hydrogen overvoltage can result in a rapid increase in hydrogen concentrations in the chlorine gas and explosion hazards. Hydrogen overvoltage reduction will result from any of a number of causes, such as impurities in the brine or mercury, locally high current densities caused by poor current distribution, or by short circuiting between the cell anode and mercury cathode, across the brine gap (a &#34;cell short,&#34; or &#34;shorting&#34;). 
     With the electrolysis reaction proceeding in accordance with Eq. (1) the sodium-mercury amalgam formed is caused to flow to a decomposer where it is combined with water to produce sodium hydroxide, NaOH, as indicated by the following expression: 
     
         Na(Hg) + H.sub.2 O → NaOH + 1/2 H.sub.2 + (Hg)      Eq. (2) 
    
     The power consumed in carrying out the electrolysis reaction of Eq. (1) is a product of the cell potential, Ec, which is the potential drop across the cell and the cell current, Ic, which is the current through the cell. In order to employ the minimum power, the cell potential, Ec, is reduced to the smallest value which will maintain the electrolysis reaction of Eq. (1) without shorting or permitting the competing hydrogen reaction to predominate. 
     The component potentials which are summed to form the cell potential, Ec, are: the reversible potential, the ohmic potential due to the potential drop across the electrolyte, contact potential due to the potential drop at the bus joints, the bus potential due to the potential drop along the cell conductors, and the polarization voltages due to the polarization at each of the two electrodes. Over the normal range of cell operation conditions, polarization and ohmic voltage drops can be represented as the sum of constant terms plus terms dependent on temperature (τ) and cell current (Ic). The reversible potential, plus the constant portions of the polarization and ohmic potentials can be represented by the constant Eo. 
     For convenience, the current-dependent terms of the contact and bus potential drop can be combined as a temperature-varying resistance (Rτ) multiplied by the cell current (Ic), to yield (Rτ) (Ic). 
     The current-dependent terms of the brine potential drop can be expressed as the product of a temperature-dependent brine resistance term (ρτ) and the ratio of the brine gap (S) to the anode area (A) to yield (Ic) (ρτ) (S/A). 
     With these definitions, the cell potential is given by the following expression: 
     
         Ec = Eo + [Ic][Rτ] + [IC][ρτ][(S/A)]           Eq. (3) 
    
     In order to minimize the cell potential, Ec, the potential drop across the electrolyte, [Ic][(ρτ) (S/A)] is reduced by reducing the anode/cathode spacing, S. 
     Although it has long been known to be desirable to reduce the anode/cathode spacing to reduce power consumption, such a reduction can increase the hazards of cell shorts. These are undesirable in that they often require stopping and restarting of the electrolysis reaction, in that they cause damage to the anodes, and in that they are accompanied by undesirable alternative and dangerous hydrogen generation which reduces current efficiency and may result in explosions and cell damage. 
     In order to regulate an electrolysis reaction by adjusting anode/cathode spacing, others have previously suggested moving the anode momentarily into contact with the cathode. Such anode/cathode contact, besides resulting in a short circuit, theoretically is supposed to identify a reference position where a short will occur. After the harmful short is detected, the anode is retracted a predetermined amount from that reference position. In actual practice, of course, the objective is to avoid shorts and therefore &#34;reference positions&#34; are established by operators who known, through experience, the location of the reference positions which do not cause shorts. Notwithstanding suggestions in the prior art, it is not believed practical or desirable to actually induce short circuits for control purposes. This conclusion is believed true even though attempts have been made to detect shorts rapidly and, after detection, to retract the anode before substantial damage has occurred. Such attempts even when retraction is accomplished during early stages of an anode/cathode short, have not proved entirely satisfactory nor reliably stable. 
     Prior attempts at reducing the frequency of shorts have also monitored various electrical signals such as changes in anode/cathode voltage or current, to detect short-causing conditions. In one example, short-causing transients, like those output from a poorly regulated power supply, have been monitored. Such transients can be characterized as current &#34;spikes&#34; which are generally not oscillatory and which have a very high frequency spectrum when observed by Fourier analysis. While such monitors may be useful where poor power supply regulation exists, they have not heretofore been satisfactory for reducing shorts where good power supply regulation is present. 
     While other attempts at regulating anode/cathode spacing have also been tried, heretofore, no reliable or completely satisfactory indicators of shorts have been available in the absence of actually causing or detecting the actual undesirable shorts. 
     In accordance with the above background, it is the objective of the present invention to provide a method and apparatus, capable of use in production facilities, for controlling electrolysis reactions with reduced power consumption and with less damage from actual anode/cathode shorts. 
     SUMMARY OF THE INVENTION 
     The present invention is a method and apparatus for controlling and monitoring an electrolysis reaction so as to reduce or avoid anode/cathode shorts while minimizing power consumption, through minimizing anode/cathode spacing. A plurality of control parameters are utilized in the controlling and monitoring functions. One control parameter is current, which is analyzed to detect current oscillations which are precursors of shorts. When current oscillations are detected, the anode/cathode spacing is increased until stable current is regained. 
     Other parameters are excursions of current and voltage above or below predetermined upper and lower limits. 
     In an embodiment where a plurality of cells are connected in an array, apparatus is provided for periodically polling the cells to obtain control parameters and monitor the operation of all cells in the array. Where each cell includes a plurality of buses in each cell, apparatus is also provided for polling each bus within a cell. 
     In one specific embodiment of the invention, the array of electrolysis cells includes sixteen parallel buses with 52 cells serially connected along each bus with sixteen anode units per cell. Each anode unit may typically include three anodes. Each one of the 16 anode units in a cell connects to a cell instrumentation package where there are 52 cell instrumentation packages. Each of the instrumentation packages includes detectors for detecting the bus current, Ib, for each bus in a cell, the bus potential, Eb, from each bus to the cathode of each cell and the temperature associated with the cell. In each instrumentation package, the detected signals are selected one at a time by a multiplexer for input to an analog-to-digital converter which provides converted signals. The converted signals are transmitted to a computer where they are analyzed to determine the control parameters utilized to control and monitor the electrolysis reaction. 
     The control parameters include current oscillations, variations in current above or below upper and lower limits, variations in voltage above or below upper and lower limits, and variations of a particular bus current above or below the average current of multiple bus currents. Of particular interest for identifying shorts is the detection of a current above an upper limit simultaneously with a voltage below a lower limit for the same anode unit. For a typical system, current oscillations having a frequency of less than approximately one cycle per second are detected. 
     The current oscillations are detected in accordance with the following method. A change in current, ΔIb, is periodically obtained for each increment of time, Δt. The increment Δt is typically the polling interval established by the polling apparatus. The ΔIb determination for each increment Δt is compared with a predetermined constant, ε. Depending on the absolute value of ΔIb, an accumulated measurement signal Xb, is incremented or decremented thereby performing a running integration of ΔIb/Δt If the magnitude of Xb exceeds a predetermined constant, that condition signifies that current oscillations have been detected. Other control parameters are detected by additional methods. 
     In accordance with the above summary, the present invention achieves the objective of providing an improved method and apparatus for the control and monitoring of electrolysis reactions. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 depicts a schematic representation of a control apparatus connected to an electrolysis cell in accordance with the present invention. 
     FIG. 2 depicts a schematic representation of an array of 52 electrolysis cells, with sixteen units per cell, connected to a control apparatus in accordance with the present invention. 
     FIG. 3 depicts a cross-section view typical of one of the anode units of a cell in the array of FIG. 2. 
     FIG. 4 depicts a top-view of the beginning and ending anode units of a cell in the array of FIG. 2. 
     FIG. 5 depicts a schematic representation of a cell instrumentation package (CIP) which is typical of the 52 CIP&#39;s employed within the FIG. 2 apparatus. 
     FIG. 6 depicts a schematic representation of the control and transmitter/receiver utilized within the cell instrumentation package of FIG. 5. 
     FIG. 7 depicts a waveform representative of the data signal of the CIP control of FIG. 6. 
     FIG. 8 depicts a schematic representation of the current and voltage detectors associated with one anode unit and employed within the cell instrumentation package of FIG. 5. 
     FIG. 9 depicts a schematic representation of the isolator/driver circuit employed within the cell instrumentation package of FIG. 5. 
     FIG. 10 depicts waveforms representative of bus current and bus to anode voltages which are detected in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION 
     In FIG. 1, the apparatus is responsive to a plurality of control parameters for controlling and monitoring an electrolysis cell 3. The electrolysis cell 3 includes an anode 4, a mercury cathode 5 surrounded by cell walls 2. The cell is covered by a cover 8 with a flexible seal 11 to form a tight compartment. Within the compartment the anode 4 is immersed in an electrolyte solution 6. For electrolysis to form chlorine, the solution is salt brine, NaC1. A cover drive 9 is rigidly attached to the cover 8 by a drive shaft 30. Drive 9 functions to raise or lower the cover 8 and thereby raise or lower the anode 4 relative to the mercury cathode 5. 
     Current is supplied to the cell 3 by a power supply 7. The positive output from supply 7 connects along the anode bus 29 and conducts current through anode 4 and electrolyte 6 to the mercury cathode 5. The cathode 5 is in electrical contact with a cathode bus 31 which connects to the negative return path of a power supply 7. The anode bus 29 has a terminal 12 and the cathode bus 31 has a terminal 13 for measuring the cell anode/cathode potential, Ec. Terminal 13 and a second cathode terminal 14 are provided for detecting cell bus current, Ic. The terminals 13 and 14 are displaced a predetermined distance, for example 0.45 meters, upon the conductor 31. Conductor 31 is a high conductivity metal (e.g. copper). The temperature of the bus 31 is measured by a temperature transducer 10. 
     In FIG. 1, the cell potential, Ec, is detected by a voltage detector 15 connected to receive the signal between terminals 12 and 13. The cell current, Ic, is detected by a voltage detector 16 connected to receive the signal between the terminals 13 and 14. The temperature of the cell is detected by a voltage detector 17 connected to detect the signal from the temperature transducer 10. The detectors 15, 16 and 17 are conventional differential amplifiers or other circuits which produce outputs which are functions of the input voltages. The input voltage to detector 16, as measured between fixed terminals along the bus 31, is directly proportional to the current in the cell 3. 
     The output from detector 15, proportional to the cell potential, is input to the comparator 35. Comparator 25 compares the signal from detector 15 with a predetermined reference signal established by a reference circuit 22. The output from comparator 25 is the function of the difference between the reference signal established by circuit 22 and the detected signal from detector 15. 
     In a similar manner, the current signal from detector 16 is compared in comparator 24 with a reference signal established by reference circuit 21. The output from comparator 24 is proportional to the difference between the reference signal and the detected signal. The output from detector 16 is also input to an oscillation detector (OSC DET) 18 which functions to detect oscillations in the cell current. Oscillations of cell current of a predetermined frequency produce a signal output from detector 18 which connect to comparator 23. The difference between the detected oscillation signal from detector 18 and a reference signal provided by reference circuit 20 are compared in comparator 23 to produce an output proportional to the difference. 
     The outputs from comparators 23, 24 and 25 are combined in a conventional logic circuit 26. Logic circuit 26 provides a logical combination of the inputs from comparators 23, 24 and 25 in a conventional manner. For example, the signals from comparators 24 and 25 provide signals which when both are present (logical AND) define gross conditions, such as shorts, in the electrolysis cell. Fine conditions are defined by a signal from comparator 23 and the oscillation detector 18. Whenever the circuit 26 detects a signal from comparator 23, responsive to the presence of oscillations detected by detector 18, servo drive circuit 27 is responsively energized to cause cover drive 9 to raise the cover 8 and thereby increase the anode/cathode spacing. Whenever ocillations are absent, servo drive 27 responds to lower the cover and hence decrease the anode/cathode spacing. The anode/cathode spacing is not decreased, however, beyond an amount determined by the cell potential detector 15 and comparator 25 which prevents the cell potential, Ec, from dropping below a predetermining value. In one example, Ec is not permitted to drop below approximately 4.18 volts. Reference circuit 22 and detector 15 produce an output from comparator 25 which through logic circuit 26 prevents the servo drive 27 from reducing the anode/cathode spacing any farther. 
     In the case of a large current increase (e.g. 20% or more), as occurs when a short is present, the detector 16 in combination with the comparator 24 and reference circuit 21 produce an output signal which through circuit 26 overrides all other signals and causes servo drive 27 and cover drive 9 to immediately increase the anode/cathode spacing. 
     The cell potential and cell current signals vary as a function of temperature, τ. In order to neutralize the effects of temperature, the output from temperature detector 17 is input to shift the reference levels in the reference circuits 20 and 21. 
     The manual override circuit 28 provides an input to control the servo drive 27. The manual override 28 controls servo drive 27 and responsively the cover drive 9 to raise or lower the cell cover and attached anode. The manual control overrides any signal from the logic circuit 26. 
     An alarm circuit 41 is provided to indicate alarm conditions which exist in the signal output from circuit 26. 
     Detectors 15, 16 and 17 are conventional amplifiers which produce an output which is proportional to the input. The oscillation detector 18, the referenced circuits 20, 21 and 22 and the comparators 23, 24 and 25 and the logical circuit 26 may be either analog or digital devices. 
     In an analog embodiment of the control circuitry of FIG. 1, oscillation detector 18 is a low pass filter with a cutoff frequency of about 10Hz. The magnitude of the oscillations detected by the detector 16 are of the order of 2 out of 20. For a cell current, Ic, of 20K amperes, oscillations of approximately 2K amperes at a frequency of approximately 0.2Hz are detected prior to shorts. Comparator 24 and reference circuit 21 are conventional circuits operable, for example, to detect a 20 percent increase in cell current. 
     Comparator 25 and reference circuit 22 are conventional devices selected to provide an output if the signals from detector 15 exceed the level of reference 22. In one embodiment, the cell potential Ec is selected to be not less than 4.18 volts and comparator 25 and reference circuit 22 are conventional devices for producing an output whenever detector 15 has an output level representing less than 4.18 volts. 
     The reference circuit 20 and comparator 23 are connected so that the output from comparator 23 is linear as a function of the output of oscillation detector 18 above a minimum threshold determined by referenced circuit 20. In this operation, the linear output from comparator 23 controls, through circuit 26, servo drive 27 in the absence of any overriding output from comparators 24 and 25. Circuit 26 is a conventional device, such as a bank of summing resistors for analog operation or logical gates (AND, OR, etc.) for digital operation. 
     While the apparatus of FIG. 1 may be implemented with analog devices, a preferred embodiment is digital as hereinafter described. 
     Digital System -- FIG. 2 
     In FIG. 2, an array of 52 electrolysis cells is depicted. Each cell includes sixteen anode units. For example, the cell 1 includes the units A1,1; A1,2; . . . ; A1,16, the cell 2 includes the units A2,1; A2,2; . . . ; A2,16 and so forth. Each cell receives the sixteen anode buses 31-l through 31-16. The cell units which connect to anode bus 31-1 are the units A1,1; A2,1; . . . ; A52,1. 
     Each cell and each unit in a cell is connected to a cell instrumentation package (CIP). The 52 cells, cell 1, cell 2, . . . , cell 52 are connected to the cell instrumentation packages CIP-1, CIP-2, . . . , CIP-52, respectively. The anode buses 32 and the cathode buses 33 connect to the power supply 7. 
     Each cell instrumentation package 34 has an output data line (typically two wires per line) which forms one of the 52 lines in the data bus 35 to the data processor 38. Each cell instrumentation package 34 receives an address line (typically two wires per line) which is one of the 52 lines in the address bus 36 from data processor 38. Each of the cell instrumentation packages also receives a cover lift control line from the 52-line cover lift bus 37. 
     The data bus 35 and the address bus 36 are controlled by the data processing circuitry in FIG. 2. The data processing circuitry includes a programmable computer 42 and a digital multiplexer 43. In one preferred embodiment, the computer 42 is a NOVA 1200 computer and the digital multiplexer 43 is a model 4100, both manufactured by Data General Corporation. 
     The digital multiplexer 43 is addressed by the 12-bit MUX ADDR bus 47 from computer 42. The bus 47 is divided into two 6-bit fields. The high order six bits address the 52 cell instrumentation packages. The lower order six bits of the MUX ADDR define the individual measurements for each of the cells of FIG. 2. In each cell, a total of 33 measurements are made, specifically, 16 voltage measurements, 16 current measurements and one temperature measurement. Since there are 33 measurements per cell and since there are a total of 52 cells, a total of 1,716 measurements are made for the 52 electrolysis cells of FIG. 2. 
     The multiplex address on bus 47 sequentially steps through each of the 1716 addresses. The multiplexer 43 responsively addresses the cell instrumentation packages and the 33 measurements associated with each package. The computer 42 and multiplexer 43 complete the addressing in a fixed cycle period. The cycle period is selected, in one embodiment, to be approximately 0.1 second and therefore a sampling rate of ten samples per second is established. With a sampling rate of ten times per second, the 1,716 measurements are completed ten times per second. The sampling rate determines the highest frequency of oscillation which can be detected by the apparatus of FIG. 2. A sampling rate of ten samples per second will readily allow detection of oscillation frequencies up to five cycles per second. If higher frequencies are to be detected, then the sampling rate must be increased. For readily detecting frequencies of less than approximately one cycle per second, a sampling rate of two samples per second may be employed. 
     Cell Unit -- FIG. 3 
     In FIG. 3, a cross-section of anode unit A1,1 of FIG. 2 is shown. The anode unit includes three anodes 4-1, 4-2 and 4-3 which are electrically connected to the anode bus 29 and mechanically connected to the cell cover 8. The cover 8 and anodes 4-1, 4-2 and 4-3 are raised and lowered by the cover drive 9. The cell walls 2 are rubberized steel and spaced apart approximately 2.3 meters. The mercury cathode 5 sits on a steel bed 31 which is mechanically and electrically connected to the cathode bus 32-1-2. The cathode bus 32-1-2 from cell unit A1,1 (also see FIG. 2) is connected as the anode bus of the adjacent cell unit A2,1. 
     The terminal 12 is connected to the anode bus 29 and the terminals 13 and 14 are connected to the cathode bus 32-1-2. The cell bus potential, Eb, is measured between terminals 12 and 13 to form signal V1,1. The bus current, Ib, is measured as the potential difference between terminals 13 and 14. 
     A flexible rubber skirt 11 forms a seal between the cell walls 2 of the cell cover 8. The skirt 11 allows the cover 8, the anodes 4 and the anode bus 29 to be raised and lowered a short distance without breaking the seal. The anode bus 29 includes flexible straps 40 which connect to bus 32-1 which in turn connects to the power supply 7 of FIG. 2. The temperature transducer 10 is positioned on the cathode bus 32-1-2 for detecting the bus temperature. 
     Cell -- FIG. 4 
     In FIG. 4, a top view of cell 1, including the anode units A1,1 through A1,16, of FIG. 2 is shown. The cell walls 2 define a chamber approximately 2.3 meters by 13.3 meters. In FIG. 4, only the first anode unit A1,1 and the last anode unit A1,16 are shown. The first anode unit A1,1 is connected to the anode bus 29 which is in turn connected through flexes to the bus 32-1 and the power supply of FIG. 2. Similarly, the anodes 4-1&#39;, 4-2&#39; and 4-3&#39; of anode unit A1,16 are connected to a bus 29&#39; which is in turn connected to the bus 32-16 and the power supply of FIG. 2. The cathode bus 32-1-2 associated with anodes 4-1, 4-2 and 4-3 connects from the steel base 31 (see FIG. 3) which is substantially the same size as the area enclosed by the walls 2. The cathode bus 32-16-2 associated with the anodes 4-1&#39;, 4-2&#39; and 4-3&#39; also connects to the steel base 31. 
     In FIG. 4, the anode bus 32-1 has the terminal 12 and the cathode bus 32-1-2 has the terminals 13 and 14. The terminals 12 and 13 provide the contacts for the signal V1,1 and terminals 13 and 14 provide the contacts for the signal C1,1. In the similar manner for anode unit A1,16, terminal 12&#39; is located on bus 29 and terminals 13&#39; and 14&#39; are located on bus 32-16-2. The terminals 12&#39; and 13&#39; provide the signal V1,16 and the terminals 13&#39; and 14&#39; provide the signal C1,16. The temperature transducer 10 provides the signal T1. 
     Cell Instrumentation Package -- FIG. 5 
     In FIG. 5, an overall block diagram of one of the cell instrumentation packages (CIP) 34 of FIG. 2 is shown as typical. The instrumentation package receives the voltage, current and temperature signals of the type indicated in FIG. 3 and FIG. 4. In FIG. 5, those signals are input to the amplifiers 51. The instrumentation package of FIG. 5 functions to select the input signals one at a time, convert them from analog-to-digital form, and transmit them over a DATA OUT bus to the data processor in FIG. 2. The selection is controlled by the address received on the ADDR IN bus. 
     In FIG. 5, the V1 through V16 amplifiers 51 are conventional devices which are provided for receiving the voltage signals V1,1 through V1,16 from the cell of FIG. 4. Those voltage signals typically range from 0 to 6 volts. Amplifiers V1 through V16 provide the output signals V01,1 through V01,16, respectively, which are input to a multiplexer (MUX) 52. 
     In a similar manner, the sixteen C1 through C16 amplifiers 51 are also conventional devices which receive the sixteen current signals C1,1 through C1,16, respectively, from the cell of FIG. 4. Those current signals are represented as voltages which are proportional to current and which generally range from 0 to 20 millivolts. The amplifiers C1 through C16 provide the current output signals C01,1 through C01,16, respectively, which are input to the multiplexer 52. 
     The single temperature output signal T1 is input to the amplifier 51 which is also conventional and which has its single output connected as an input to multiplexer 52. 
     In FIG. 5, the multiplexer 52 functions to select input lines one at a time to connect to the single EO output line 59. Multiplexer 52 is responsive to the 6-bit address bus 60 for selecting one of the 33 input lines. Multiplexer 52 is a conventional device commonly available under model number AM3705C. 
     The analog signal on the Eo line 59 from multiplexer 52 is input to a conventional analog-to-digital converter (A/D CONV) 53. Converter 53 is responsive to a command on the START CONV line, from a CIP control 54 to convert the EO signal on line 59 to a digital value on the 8-bit converted data (CDATA) output bus 61. When the conversion has been completed in converter 53, the EOC signal is provided to the CIP control 54 to indicate the end of conversion. The converter 53 is a conventional device which performs a conversion in approximately 100 micro-seconds. The Datel Model ADC-D8B is such a converter. 
     The output from converter 53 on bus 61 is connected to the transmitter (TRANS) portion of the cell instrumentation package universal asynchronous receiver/transmitter (UART) 76. UART 76, among other things, converts the 8-bit parallel data on bus 61 to serial data on the XMIT DATA line. UART 76 also has a receive portion (REC) for receiving serial data on the RECV DATA line for producing the 6-bit address on the MUX ADR bus 60 for the multiplexer 52. UART 76, in one more embodiment, is a model TR 1602 manufactured by Western Digital Corporation. 
     The XMIT DATA line connects through isolator/driver circuit (ISO/DRIVE) 55-1 having optical isolators which provide up to 1500 volts of DC isolation. The drivers in the circuit 55 convert the 0 and 5 volt XMIT DATA digital potentials to a differential current signal DATA OUT for transmission to the data processing system of FIG. 2. In a similar manner, the receiver path of unit 55-2 contains a line receiver which converts the differential current signal DATA IN from the data processing system to 0 and 5 volt binary signal RECV DATA. 
     Cell Instrumentation Package Control -- FIG. 6 
     In FIG. 6, the CIP control 54 of FIG. 5 is shown in greater detail along with the manner of connecting control 54 to UART 76. The UART 76 receives the parallel input data from the 8-bit C DATA bus 61 and converts it to serial data output on the XMIT DATA line. Serial data into the unit 76 appears on the RECV DATA line and is converted to parallel form for output on the 6-bit MUX ADR bus 60. 
     The control 54 includes a conventional clock circuit 58. Clock circuit 58 produces a high speed clock (HS CLK) signal which has a frequency 16 times the highest baud rate at which data is to be transmitted by UART 76. In a particular embodiment, the highest transmission rate is 9.6K baud and the lowest transmission rate is 2.2K baud. The DATA CLK signal, input to UART 76, is selected at 16 times the actual operating baud rate which in a typical example is 4.4K baud. 
     The operation of the UART 76 is described in connection with the waveform of FIG. 7. The waveform shows a typical asynchronous bit stream. Each 8-bit character is preceded by a start bit which is a logic 0 (space). The 8-bit character follows the start bit which is then followed by a stop bit which is a logic 1 (mark). The stop indication can remain for any number of bits. 
     In order to receive a character, the negative-going edge of the start bit at t0 in FIG. 7 starts the receiver clock which is utilized to locate the center of each bit. After the start bit which occurs between t0 and t1, the unit 76 functions to load an 8-bit character, during t1 to t9, into a shift register internal to the unit 76. Next, the stop bit is received at t9 and thereafter the data in the shift register is transferred in parallel to a holding register. One half clock pulse later, between t9 and t10, the data receive output (DR) in FIG. 6 is set with a 1. 
     In order to transmit a word, the parallel word on the CDATA bus is loaded into the unit 76 by applying a negative-going transition to the THRL input which thereby functions to load a transmit holding register internal to unit 76. On the positive-going edge of the same pulse, the word is loaded into a transmit register with start and stop bits added for serial transmission between t16 and t26 of FIG. 7. 
     In view of the general description of the transmitter/receiver unit 76, the remainder of the operation of the control of FIG. 6 is now explained. Receipt of any serial data word on the RECV DATA line by the control of FIG. 6 is interpreted as a multiplexer address. When receipt of the word is complete and the STOP bit has been detected, the DR line is set to a 1. That 1 connects to the preset input of conventional D-type flip-flop 77 which then has a 1 on its complementary Q* output. The Q* output feeds to the DRR input of unit 76 to reset the DR output to 0. The transition on the Q output of flip-flop 77 clocks the conventional D-type flip-flop 78 to a 0 on its Q output. That 0 enables conventional divide-by-8 counter 79 to begin counting HS CLK pulses. The parallel outputs from counters 79 and 80 are input to the 2-input NAND gate 86. Depending on which of the parallel outputs from counters 79 and 80 are selected a delay of any quantity up to 64 clock pulses can be achieved. The proper outputs for a delay of 64 are selected in the FIG. 6 embodiments. When the count reaches 64, gate 86 is satisfied to produce an output pulse through inverter 87 which removes the set input from conventional D-type flip-flop 81. The same pulse when inverted is propagated through NAND gate 85 to set flip-flop 78; and conventional reset circuit 56, through gate 85, will also set flip-flop 78. In the preferred embodiment where the delay detected by gate 86 is 64 pulses and where a clock frequency of 153.6 KHz is employed, a delay of about 0.4167 milliseconds occurs. With the set input (S) removed from flip-flop 81, the HS CLK signal clocks flip-flop 81 to a 0 on its Q output thus providing the START CONV signal. 
     At the time that the DR signal was output from unit 76 to set flip-flop 77, the MUX ADR lines also received the 6-bit address and caused the multiplexer 52 in FIG. 5 to select one of the input signals. The delay of gate 86 enables the multiplexer output on line 59 to settle since multiplexer 52 has a bandwidth of approximately 10 KHz. The START CONV signal causes the conversion to start in converter 53 and when it is complete, the EOC signal has a 1 to 0 transition. When the EOC signal transition occurs, the flip-flop 83 is clocked to produce a 0 on its Q output and thereafter, flip-flop 82 is clocked by the HS CLK signal to store 0 and provide a 1 on its Q* output. That 1 enables NAND gate 88 which, in synchronism with the HS CLK signal, produces a pulse on the THRL input of unit 76. The output from gate 88 also through NAND gate 84 sets flip-flop 83 which in turn causes flip-flop 82 to be clocked with a 0 on its Q* output inhibiting any further output from gate 88. The THRL input to unit 76 occurs for only 1 clock pulse. The leading negative-going transition causes the holding register to be loaded and transmission is started on the trailing positive-going edge. The THRE output signifies that the transmit holding register is empty which through NAND gate 89 resets flip-flop 77 on the positive-going edge to indicate that transmission is complete. 
     CURRENT AMPLIFIERS -- FIG. 8 
     In FIG. 8, the unity-gain amplifier 93 receives the input V1,1 signal and produces the output 01,1 signal. Amplifier 93 is typically of the LM301 type. Amplifier 93 and the associated circuitry corresponds to the V1 amplifier 51 in FIG. 5. 
     In FIG. 8, the amplifiers 94 and 95 and associated circuitry correspond to the Cl current amplifier 51 in FIG. 5. The amplifiers 94 and 95 are conventional amplifiers of the OP-05 and LM301 type, respectively. Amplifier 94 is operated differentially at a gain of approximately 100 and amplifier 95 is operated single ended at a gain of about 5. The current amplifier pair 94 and 95 have a gain at 10 Hz of 460(51dB) and a frequency response from DC to 100 Hz. The amplifier 93 has a gain at 10 Hz of 1 (0dB) with a frequency response from DC to 150 Hz. 
     ISOLATION/DRIVER -- FIG. 9 
     In FIG. 9, the isolation driver circuits 55-1 and 55-2 of FIG. 5 are shown in detail. The transmit path receives the XMIT DATA signal with binary levels of 0 and 5 volts to produce the differential current mode output DATA OUT. Similarly, the receiver path receives the differential current on the DATA IN lines and converts it to a 0 and 5 volt binary signal on the RECV DATA line. Both the transmit and receive paths operate essentially in the same manner. The 2N3704 transistor drives the light emitting diode portion of the optical isolator. The isolator is typically a type 4N26. The LM311 comparator connected to the photo-transistor of the isolator reshapes the output voltage to assure that it is compatible with the logic levels. The two 1K resistors, the 4.7K resistors and the 0.01 microfarad capacitors eliminate uncertainty at the threshold in the presence of noise. 
     METHOD OF OPERATION 
     The apparatus of FIG. 2 operates to monitor and control an electrolysis reaction. The monitoring and control functions are carried out by the data processing circuitry 38. Specifically, the computer 42 samples, collects and stores data which is derived through the cell instrumentation packages 34. Also, computer 42 processes the data obtained and controls the electrolysis process in response to processed data. The control may be in the form of alarms and in energizing the cover lift electronics for raising and lowering the covers. To accomplish these tasks, the computer 42, in one preferred embodiment, is programmed with the Real Time Operating System supplied by Data General Corporation for the NOVA 1200 computer. 
     The data collection function is carried out by the real time operating system of computer 42 by addressing, one at a time, each of the 1,716 measurement locations in FIG. 2. The computer addresses all of the 1,716 measurements up to ten times per second. The addressing is carried out by addressing each of the CIP&#39;s of FIG. 2 one at a time. That addressing is carried out typically by a high order 6-bit address. For example, the CIP-1 is the first CIP addressed. During the period when CIP-1 is addressed with one address, 33 measurements associated with CIP-1 are carried out by serially stepping through 33 low-order addresses. First, 16 voltage measurements associated with the 16 units Al,1 through Al,16 are carried out. Thereafter, 16 current measurements associated with the units Al,1 through Al,16 are made. Finally, one temperature measurement is made. After the temperature measurement, the high-order 6-bit address is stepped one count so that the next CIP is addressed. Thereafter, the low-order 6-bit address is incremented 33 times, one address at a time, to obtain in order the 16 voltage measurements, the 16 current measurements and the single temperature measurement. 
     After completion of the 33 measurements for each CIP, the high order address is again incremented to a new CIP address. For each new CIP address, the 33 low-order addresses are repeated. This process continues until all 52 CIP&#39;s have been addressed and all 1,716 measurements have been completed. Thereafter, the addressing process starts all over again in the same manner again addressing the 1,716 measurements. The addressing is carried out so that each of the 1,716 measurements is taken uniformly ten times per second. 
     Each time the computer 42 steps to a new address, the multiplexer 43 receives that address and sends that address out to the address bus 36. Those addresses are received in the CIP&#39;s in the manner previously described in connection with FIGS. 5 and 6. In response to each address, measurement signals are returned over the measurement bus 35 to the digital multiplexer 43. The digital multiplexer 43 in turn transmits the measurements received to the computer 42. Computer 42 has a first set of storage locations for each of the 1,716 measurement signals obtained. There is a one to one correspondence between those memory locations within computer 42 and the addresses which appear on bus 47. A second set of locations is included within computer 42, for storing 1,716 measurements. Each time a new measurement is addressed and received from the electrolysis apparatus of FIG. 2, the measurement is stored in one of the first set of 1,716 locations. Any previous measurement in that location is transferred to one of the second set of 1,716 locations. For example, the first measurement, associated with CIP-1 and the first unit Al,1 is the voltage measurement Vl,1 and V01,1 of FIG. 7. That measurement value is transmitted and stored in a particular location (e.g. Vb1) of computer 42. After the remaining 1,716 measurements are made (each being stored in a different Vb1 location), the second set of 1,716 measurements are made while the initial contents of the Vb1 locations are transferred to new locations (e.g. Vb2) in computer 42. Since there are 832 voltage measurements, there are 832 Vb1 and 832 Vb2 locations within computer 42. 
     In a similar manner, there are 832 Ib1 and Ib2 locations within computer 42 for storing current measurements and 52 Tl locations for storing temperature measurements. The current and temperature measurements are addressed, stored in the Ib1 and Tl locations, and then current is transferred to the Ib2 locations. The addressing, storing and transferring steps operate on a real time basis and therefore constitute a data sampling operation. 
     In addition to the data sampling, collection and storage operation, the computer 42 additionally performs real time computations in order to provide the monitor and control signals associated with the FIG. 2 apparatus. 
     The computations include generation of (1) individual anode potential limit alarms, (2)average anode/cathode potential limit alarms, (3) individual bus current limit alarms, (4) individual bus current fluctuation alarms and (5) anode/cathode short alarms. 
     The individual anode/cathode potential limit alarms include both an upper limit alarm and a lower limit alarm. An upper limit alarm is generated by computer 42 if any individual anode/cathode potential exceeds the voltage upper limit, VUL, as defined by the following equation: ##EQU2## where: V[v] = individual bus potential 
     Kl = preset fraction (e.g.1/2) 
     v = cell bus number = 1, 2, . . . ,16 
     It is evident from Eq. (4) that the upper limit VUL is some increment, established by the constant Kl, greater than the average potential for all of the buses within one cell. 
     In a similar manner, a voltage lower limit (VLL) for the anode/cathode potential is defined by the following equation: ##EQU3## 
     The computer 42 performs the calculations for VUL and VLL for each cell in a conventional manner. Each individual anode/cathode potential V[v] is compared with the VUL values. If any value of V[v] is greater than VUL or is less than VLL, then computer 42 generates an alarm signal. That alarm signal is connected to the alarm board 45. Alarm board 45 may include a bell, lamp or any other indicating device to indicate the alarm condition. Also a teletype 46 in FIG. 2 is provided and alarms may be output there in a conventional manner. 
     The anode/cathode potential limit alarm is generated by comparing the average anode/cathode potential, Vave, with predetermined upper and lower limits. The value of Vave is determined by the following equation: ##EQU4## 
     The individual bus current limit alarms include both an upper limit, IUL, and a lower limit, ILL, as given by the following equations: ##EQU5## 
     The computer 42 performs the calculations of Eq. (7) and Eq. (8) in a conventional manner and compares IUL and ILL with each of the 16 values of C[u]. If any value of C[u] exceeds IUL or is less than ILL, then an alarm is generated. The values IUL and ILL define predetermined deviations from the average current. The amount of deviation is controlled by the magnitude of K2. The average current is given by Eq. (6) or Eq. (7) if K2 is made equal to zero. 
     An individual bus current fluctuation alarm is generated if oscillations in individual bus currents are detected. The presence of the oscillations is determined whenever a threshold integration function, Xb, exceeds a predetermined limit, K3. The function Xb is defined by the following equation: ##EQU6## 
     In equation 9, the function Yb[n] is equal to one of three values, 1, 0, or -1. 
     The value for Yb is determined by the valuation of the quantity ΔIb where ΔIb is the absolute value of the difference between Ib1 and Ib2. The values Ib1 and Ib2 are two successive measurements of bus current for an individual bus. A new bus current measurement is stored in an Ib1 location while the previous measurement is moved from the Ib1 location to the Ib2 location. Each new Ib1 measurement occurs at the sampling interval, Δt, which is typically every 0.1 second. The ΔIb value formed every Δt is a differential function ΔIb/Δt where Δt is a sampling interval. 
     If ΔIb, as formulated every Δt, is greater than a quantity ε, the value of Yb is equal to 1. If ΔIb is less than ε, then Yb is equal to 0 if Xb is equal to 0, or Yb is equal to -1 if Xb is greater than 0. Where the value Xb has a range between 0 and 256, the value of ε is equal to a small number such as 4. While many values of ε can be selected, ε generally is selected less than ten percent of the maximum Xb value. 
     The process of adding 1, 0, or -1 to the previous sum of Xb is defined by Eq. (9). Each new value of Ib1 is a new value for &#34;n&#34; in Eq. (9). Eq. (9) is a threshold approximation of integrating the differentialΔIb/Δt. Integration of that differential forms the value Xb which is approximately proportional to the derivative of the bus current. A threshold integration function Xb occurs, of course, for every one of the 832 individual buses in the electrolysis apparatus of FIG. 2. If any one of those 832 values for Xb exceeds a constant K3, then an alarm is generated. Where direct control of the anode covers is desired, the cover lift electronics provides a signal to lift the covers whenever Xb exceeds the threshold K3. The covers are lowered whenever the value of Xb is less than K3. In this manner, cover lifts may be automatically controlled in response to the Xb signal. 
     In light of the above discussion, the details of a suitable program for computer 42 to carry out the processing will be apparent to those skilled in the art. The Real Time Operation System provided by Data General Corporation in combination with the NOVA 1200 computer is a suitable vehicle for implementing those programs. Additionally, the following program presented in TABLE I and TABLE II will be explained as a representative of such programs. 
     In TABLE I, the steps of S1 through S18 are sequentially executed by the computer 42 of FIG. 2. 
     In Step S1, one of the CIP&#39;s 35 in FIG. 2 is addressed on the address bus 47. The particular one of the CIP&#39;s addressed is determined by the value of u where u has a value between 1 and 52. When the program starts, u is initially equal to 1. With u equal to 1, the CIP-1 in FIG. 2 is addressed. 
     In Step S2, the voltage measurement V[v] is addressed. Initially, the V is equal to 1 which signifies that the voltage Vl,1 in FIG. 5 is addressed. When addressed, voltage measurement is returned to the digital multiplexer 43 and from there to the computer 42. 
     In Step S3, the Vl,1 value of the V[l] measurement is stored in computer 42. 
     In Step S4, the program of TABLE I jumps to a subroutine program SUB-I to determine if a potential alarm should be generated as a result of the voltage measurement stored in S3. The SUB-1 subroutine is implemented to perform the calculations of Eqs. (4) and (5). After completion of SUB-1, the subroutine returns to Step S5. 
     In Step S5, +1 is added to the value of v. 
     In Step S6, v is compared to the constant 16. If v is greater than 16, then the program goes to Step S7. The steps 
     
                       TABLE I______________________________________S1   ADDRESS CIP[u][u = 1, 2, . . . 52]S2   ADDRESS V[v][v = 1, 2, . . . 16]S3   STORE V[v]S4   JUMP TO SUB-I (Potential Alarm) - [Return S5]S5   ADD +1 to vS6   COMPARE v to 16:If v ≦ 16, go to S2If v &gt; 16, go to S7S7   ADDRESS C[w][w = 1,2, . . . 16]S8   TRANSFER Ib1 to Ib2S9   STORE C[w] in Ib1S10  JUMP TO SUB-II (Current Fluctuation Alarm)-[Return S11]S11  JUMP TO SUB-III (Current Limit Alarm) - [Return S12 ]S12  ADD +1 to wS13  COMPARE w to 16:If w ≦ 16, go to S7If w &gt; 16, go to S14S14  ADDRESS TS15  ADD +1 to uS16  COMPARE u to 52:If u ≦ 52, go to S1If u &gt; 52. go to S17S17  SET u =  1,S18  JUMP to S1______________________________________ 
    
     
                       TABLE II______________________________________SS1  SUBTRACT Ib2 from Ib1 to form ΔIb = Ib1 - Ib2SS2  COMPARE Xb [n] with 0:[n = 1, 2, . . . ]If Xb = 0, go to SS3If Xb ≧ 0, go to SS4SS3  COMPARE ΔIb with ε:If ΔIb &lt; ε, go to SS5If Xb ≧ 0, go to SS7SS4  COMPARE ΔIb with ε:If ΔIb &lt; ε, go to SS9If Ib ≧ ε, go to SS7SS5  SET Yb = 0SS6  JUMP TO SS10SS7  SET Yb = +1SS8  JUMP to SS10SS9  SET Yb = -1SS10 ADD Yb to Xb[n] to form Xb [n + 1] = Xb[n] + YbSS11 COMPARE Xb[n + 1] with K3,If Xb[n + 1] ≧ K3, go to SS12If Xb[n + 1] &lt; K3, go to SS13SS12 SET ALARM [dI/dt]SS13 JUMP TO S11______________________________________ 
    
     S2 through S6 are a loop which functions to address, store and process the sixteen voltage measurements within the particular CIP addressed in Step S1. 
     After the sixteen voltage measurements have been processed, a second loop comprising Steps S7 through S13 is entered to process the 16 current measurements associated with the CIP specified in Step S1. The quantity w equals the values of 1 through 16. In Step S7, the value of w is equal initially to 1. With a w equal to 1, the current measurement Cl,1 of FIG. 5 is addressed. In Step S8, the contents of a storage location Ib1, in computer 42 is transferred to location Ib2 to make room for the measurement of S7. 
     In Step S9, the C[w] measurement of Step S7 is stored into a first Ib1 location of computer 42. 
     In Step S10, the program of TABLE I jumps to a subroutine, SUB-II. The SB-II subroutine is shown in TABLE II. 
     In TABLE II, the step SS1 forms the quantity ΔIb by subtracting Ib2 from Ib1. There are Ib1 and Ib2 locations in computer 42 for each of the 832 current measurement associated with the apparatus of FIG. 2. Accordingly, the subroutine of TABLE II is repeated 832 times, once each time one of the current measurements of FIG. 2 is addressed. 
     In Step SS2, the quantity Xb is compared with 0. The quantity Xb is the running integration function defined by Eq. (9) above. If Xb is equal to 0, then the subroutine goes to Step SS3. If Xb is greater than 0, then the subroutine goes to SS4. There are 832 different Xb quantities, one for each of the current measurements in FIG. 2. 
     In Step SS3, the quantity ΔIb formed in Step SS1 is compared with the quantity ε. If ΔIb is less than ε, then the subroutine jumps to Step SS5 to set the quantity Yb equal to 0. If ΔIb is greater than or equal to ε, then the program goes to Step SS7 to set the quantity Yb equal to +1. 
     In Step SS4, the quantity Ib is compared with ε. If ΔIb is less than ε, then the subroutine goes to Step SS9 to set Yb equal to -1. If ΔIb is greater than or equal to ε, then the subroutine goes to Step SS7 to set the Yb equal to +1. During any one pass through the subroutine of TABLE II, the value of Yb is set to only one of the values 0, +1, or -1. 
     In Step SS10, the newly determined value of Yb is added to the threshold integration function Yb[n] to form a new value Xb[n+1]. In a subsequent pass through TABLE II for the same current measurement, the new value Xb[n+1] becomes the old value Xb[n]. The variable n has no upper limit. 
     In Step SS11, the newly formed value Xb[n+1] is compared with the constant K3. If greater than or equal to K3, then the subroutine jumps to SS12 and if less than K3, then the subroutine jumps to SS13. 
     In Step SS12, the subroutine sets an alarm thereby indicating that a current oscillation proportional to DI/dt has been detected. 
     In Step SS13, the subroutine returns to Step S11 of the program of TABLE I. 
     In Step S11, the program of TABLE I jumps to a subroutine SUB-III to provide a current limit alarm. The current limit alarm is analagous to the potential alarm of Step S4. The current alarms are implemented to carry out the calculations of Eq. (7) and Eq. (8). 
     In Step S12, +1 is added to w. 
     In Step S13, the value of w is compared to 16. If w is less than or equal to 16, then the program jumps to Step S7. The Steps S7 through S13 are a loop for performing the calculations for all sixteen of the currents associated with CIP addressed in Step S1. After the sixteenth measurement signal, w greater than 16, the program goes to Step S14. 
     In Step S14, the single temperature measurement associated with the CIP addressed in Step S1 is performed. 
     In Step S15, +1 is added to u. 
     In Step S16, u is compared to the quantity of 52. If u is less than or equal to 52, then the program jumps back to Step S1. The Steps S1 through S16 are a loop which is repeated once for each of the 52 CIP&#39;s in FIG. 2. After the 52and completion, u greater than 52, the program goes back to Step S17. 
     In step S17, the quantity u is set equal to 1. 
     In Step S18, the program jumps back to Step S1 with the value of u equal to 1 so that the program is again repeated in the manner previously described. 
     ANODE ADJUSTMENT 
     In FIG. 10a, the A, B and C graphs represent the busbar current distribution on a typical one of the 52 cells of FIG. 2. In FIG. 10a, the overall power supply current on bus 32 of FIG. 2 is represented as I and is in units of thousands of amperes (KA). The other axis in FIG. 10a identifies the bus numbers (BUS NO.) 1 through 16 which represent, for example, the busbars (buses) (31-1 through 32-16 in FIG. 2. 
     In FIG. 10a, the broken line A represents the current distribution on the busbars prior to any adjustment of the anodes. The total current load equals 235KA, the average anode to cathode voltage is 4.74 volts, and the total power consumed is 1113.9 kilowatts. 
     In FIG. 10a, the broken line B represents the redistribution of current throughout the buses. The redistribution is effected by changing the relative heights of the anodes but without lowering the cover which controls the spacing for all anodes within a cell. For line B, the total current load is 242KA, the average anode to cathode voltage is 4.56 volts and the total power consumed is 1103.52 kilowatts. 
     In FIG. 10a, solid line C represents the current distribution after lowering the cell cover and hence a lowering of all anodes in the cell. For Line C, the total current is 240KA, the average potential is 4.41 volts, and the total power is 1058.4 kilowatts. The saving of power in the change from A to C operation is therefore 55.5 kilowatts. For operation 24 hours a day, 7 days a week, and 50 weeks a year, a total saving of 8.4 thousand kilowatt hours can be estimated. 
     The savings, of course, results from the ability to lower the cell covers the hence to reduce the anode cathode spacing. Such a reduction is not generally possible without the monitoring and control operations performed by the present invention. If the reduction in cell covers carried out between A and C lines in FIG. 10a is undertaken without control and monitoring as provided by the present invention, then the frequency of shorts is likely to be increased and the severity of the damage resulting from the shorts is also likely to be increased. 
     Using the control and monitoring functions of the present invention, however, not only is the voltage and power consumption reduced, but the frequency and severity of shorts is also reduced. With these reductions, the manpower required for anode adjusting and other cell maintenance is reduced. These features of the invention are achieved by employing the control parameters and processing steps described in connection with the programs of TABLES I and II above. 
     Of particular significance is the feature of the invention which provides the ability to detect current oscillations in individual busbars (for example, busbars 32-1 through 31-16 of FIG. 4) within the cell. 
     In FIG. 10b, the current, I, versus time, t, on a typical one of the busbars in a typical cell is shown. For a long period prior to t0 and t3, the current fluctuation about the average value Iave is small. The average current is typically of the order of 15 to 20 kiloamps. At a time betwen t3 and t4, the cell cover is lowered in a manner described in connection with FIG. 10a. In the FIG. 10b example, lowering the cover results in a current oscillation which is shown between t4 and t8. The duration of that oscillation generally continues for a much longer time than shown in FIG. 10b. The amplitude of the oscillation around the 15KA average is of the order of ± 400 amperes. It has been discovered, in accordance with the present invention, that oscillations of the type shown between t4 and t8 are precursors of shorts. When an oscillation of this type occurs in any busbar within the FIG. 2 apparatus, a current fluctuation alarm is produced in the manner previously described. (See Step SS12 of TABLE II.) When the alarm is generated, an operator manually initiates the raising of the cell covers. The covers are typically raised until the alarm disappears. In an alternate embodiment, the alarm signal from Step SS12 is employed to raise automatically the cell covers. 
     Raising of the cell covers causes fluctuation of the FIG. 10b waveform to be removed. After raising of the covers, the waveform from t4 through t8 again appears like the waveform between t0 and t3. 
     In FIG. 10c, another waveform is shown representative of a bus current as a function of time. Between the times t9 and t10, the waveform of FIG. 10c exhibits an oscillation which is a precursor to a short and which results in a short circuit approximately at t10. 
     In FIG. 10d, the anode to cathode voltage across the anode receiving the bus current of FIG. 10c is shown. After the initial drop in potential at t10, due to the short, a linear increase occured because the covers were lifted and hence the anode/cathode spacing was increased. 
     FURTHER EMBODIMENTS 
     Additional apparatus for controlling the electrolysis reaction is provided in FIGS. 2 and 3. In FIG. 3, that apparatus includes a current by-pass switch 97. Switch 97 is connected on one side to bus 32-1 and on the other side to the steel bed 31. As long as switch 97 is open (as shown), current is conducted as previously described between bus 32-1 and conductors 29, through the anodes 4-1, 4-2 and 4-3 to cathode 5 and steel bed 31. When switch 97 is closed, however, current is conducted directly form bus 32-1 to steel bed 31 and no current is conducted from anodes 4-1, 4-2 and 4-3 to cathode 5. Switch 97 is useful, therefore, in removing the anode unit of FIG. 3 from operation while allowing the other serially connected anode units (A2,1 through A52, 1 of FIG. 2) to remain operating. 
     While one typical switch 97 has been shown in FIG. 3, each of the other anode units of FIG. 2 typically includes a current by-pass switch like switch 97. 
     In FIG. 3, the switch 97 in one embodiment may be manually operable. In another embodiment, switch 97 is operated by an electrical switch control 99. Control 99 and switch 97 are typically a solenoid operated switch having consumable contracts. Any conventional switch and switch control capable of switching high currents may be employed. 
     In one preferred embodiment, the switch control 99 for each anode unit is actuated by the short electronics 98 in the data processing circuitry 38 of FIG. 2. The short electronics 98 is typically a register with one location for each of the switches and controls 97 and 99. Whenever the register location for a corresponding switch control is in one state (e.g. binary 0), the corresponding switch 97 is open. Whenever the location is in the other state (e.g. binary 0), the corresponding switch 97 is closed. The 1 or 0 states of the locations are typically set under command from the computer 42. The command to close a switch from the computer 42 may be generated, for example, whenever a short alarm is generated. 
     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.