Abstract:
A memory system and a method of reading and writing data to a memory device provide byte-by-byte write data insertion without adding extra pins or balls to the packaged device. Accordingly, the high frequency performance of the device can be improved.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
   This application claims priority under 35 U.S.C § 119 from Korean Patent Application No. 2003-44846, filed on 3 Jul. 2003 the entirety of which is hereby incorporated by reference for all purposes as if fully set forth herein. 
   BACKGROUND AND SUMMARY 
   1. Field 
   This invention pertains to the field of memory systems, and more particularly, to a memory system having data inversion, and to a method of data inversion for a memory system. 
   2. Description 
   Generally, it is a goal to improve the data transfer speed of a memory system. To this end, various techniques are employed to improve the high frequency characteristics (speed) of a memory device. For some memory devices, a data inversion scheme is employed to reduce the simultaneous switching noise in the device and thereby improve the high frequency operating characteristics. An example of such a memory device and associated memory system will now be described in further detail. 
     FIG. 1  is a block diagram of a conventional memory system  1 , having a memory device  100  and a memory controller  200 . 
   The memory system  1  operates with a data inversion scheme, as follows. During a data write operation, the signals DM&lt; 0 : 3 &gt; perform a data masking operation, WDQS&lt; 0 : 3 &gt; operate as data strobe signals, and DIM is a write data inversion flag in indicating whether or not the data (all four data bytes) should be inverted. Meanwhile, during a data read operation, the signals RDQS&lt; 0 : 3 &gt; operate as data strobe signals, and DM&lt; 0 : 3 &gt; are read data inversion flags. 
     FIG. 2  shows an exemplary ball (or pin) configuration of a conventional mode memory device  100  with data inversion. As can be seen from  FIG. 2 , the memory device  100  includes a dedicated pin or ball  160  for the write data inversion flag DIM. 
     FIG. 3  shows a data processing block diagram of the memory device  100 . The memory device  100  includes data processing circuit  110  for byte 0 , data processing circuit  120  for byte 1 , data processing circuit  130  for byte 2 , data processing circuit  140  for byte 4 , and memory cell array  150 . In the memory device  100 , each single bit of the RDQS&lt; 0 : 3 &gt; data strobe signals at pins  111 ,  121 ,  131  and  141 , and the WDQS&lt; 0 : 3 &gt; data strobe signals at pins  112 ,  122 ,  132  and  142 , is dedicated to one data processing unit  110 ,  120 ,  130  or  140  for processing one eight-bit byte of data for the memory cell array  150 . During a data write operation, DM&lt; 0 : 3 &gt; at pins  114 ,  124 ,  134 , and  144 , masks write data for the four data processing circuits  110 ,  120 ,  130  and  140 . Meanwhile, during a data read operation, each single bit of the DM&lt; 0 : 3 &gt; signals is dedicated as a read data inversion flag for one of the data processing unit  110 ,  120 ,  130  or  140 . On the other hand, during a data write operation, DIM at pin  160  is used as a write data inversion flag for all four data bytes. Four bytes of data comprising DQ&lt; 0 : 31 &gt; are input/output at the input/outputs  113 ,  123 ,  133  and  143 . 
     FIG. 4  shows a block diagram of the byte 0  data processing circuit  110  of the memory device  100 . The data processing circuits  120 ,  130 , and  140  in  FIG. 3  are configured similarly to data processing circuit  110 . The data processing circuit  110  comprises a number of components, including data strobe signal generator  113 , data control circuit  114 , and the data inversion block  115 . The data strobe signal generator  113  generates the read data strobe signal RDQS 0 . Data control circuit  114  controls data input/output during both data read and data write operations. DM 0  performs two functions: it masks write data during a data write operation, and it serves to output the read data inversion flag R_FLAG 0  during a data read operation. Meanwhile, DIM outputs the write data inversion flag W_FLAG during a data write operation. The data inversion block  115  performs a data inversion process during read and write operations according to the flags R_FLAG 0  and W_FLAG. 
     FIG. 5  shows a conventional data inversion block  115 . The data inversion block  115  includes the data toggle detection circuit  115 - 1  and the data inversion circuit  115 - 2 . The data toggle detection circuit  115 - 1  detects whether the read data input from a memory cell array are inverted or not, and then outputs the read data inversion flag R_FLAG 0  having the corresponding logic state. Data inversion circuit  115 - 2  inverts the data being written to, or read from, the memory cell array according to the logical states of the W_FLAG in a data write mode, or the R_FLAG 0  in a data read mode. 
   The data inversion block  115  reduces the simultaneous switching noise in the input/output buffers of the memory device  100  and thereby improves the high frequency characteristics of the device. 
     FIG. 6  shows a conventional data toggle detection circuit  115 - 1 . The data toggle detection circuit  115 - 1  compares input data DATA_INT&lt; 0 : 7 &gt; with a reference terminal having a reference current capability of 3.5 units. If, for example, DATA_INT&lt; 0 : 7 &gt; is 11111110, then the node N 1  will be pulled down to a logical low state ( 0 ), and the output signal R_FLAG 0  will be in a logical high state ( 1 ). Meanwhile, if DATA_INT&lt; 0 : 7 &gt; is 11100000, then the node N 1  will be pulled up to a logical high state ( 1 ), and the output signal R_FLAGO will be in a logical low state ( 0 ). Accordingly, if the number of bits of DATA_INT&lt; 0 : 7 &gt; which are logically high are greater than 4 then R_FLAG 0  will be logically high, while if the number of bits of DATA_INT&lt; 0 : 7 &gt; which are logically high are less than 4, then R_FLAG 0  will be logically low. 
     FIG. 7  shows a conventional data inversion circuit  115 - 2 . The data inversion circuit  115 - 2  includes data inverters  116 - 1 ,  116 - 2 ,  116 - 3 ,  116 - 4 ,  116 - 5 ,  116 - 6 ,  116 - 7 , and  116 - 8 . The data inverters  116 - 2 ,  116 - 3 ,  116 - 4 ,  116 - 5 ,  116 - 6 ,  116 - 7 , and  116 - 8  in  FIG. 7  are configured similarly to data inverter  116 - 1 . During a data read operation, the READ signal closes the switches S 5  and S 7 , while the R_FLAG 0  signal closes one of the switches S 1  and S 2  depending upon whether the corresponding data bit is to be inverted or not. Similarly, during a data write operation, the WRITE signal closes the switches S 6  and S 8 , while the W_FLAG signal closes one of the switches S 3  and S 4  depending upon whether the corresponding data bit is to be inverted or not. 
     FIG. 8  shows a timing diagram of a memory device with a data inversion scheme. In particular, the timing diagram of  FIG. 8  shows a memory device with so-called “Burst- 4 ” operation wherein four data bytes are written to, or read from, the memory device in a sequential burst. As can be seen from  FIG. 8 , read data (Q 0 , Q 1 , Q 2 , and Q 3 ) are output from the memory device in sync with the rising edge of RDQS 0 . Meanwhile, write data (D 0 , D 1 , D 2 , and D 3 ) are input to the memory device in sync with the center of the WDQS 0  pulses (center strobing). Furthermore, DM 0  operates as a read data inversion flag during data read operations, and to mask write data during data write operations. DIM operates as a write data inversion flag during data write operations. 
   Accordingly, operation of a conventional memory system  1  with a single DQS memory device  100  and a memory controller  200  has now been explained in relevant part with respect to  FIGS. 1–8 . 
   However, there are drawbacks to memory system with data inversion as described above. 
   For one thing, an additional pin (DIM pin) is required for the write data inversion flag. This increases the pin overhead of the memory device. 
   For another thing, only one write data inversion flag is provided for all of the data inputs (e.g., 32 DQ input pins) of the memory device. So, with the device and method illustrated in  FIGS. 1–8 , it is not possible to selectively apply data inversion to individual bytes during a data write operation. Meanwhile, applying write data inversion on a byte-by-byte basis improves the high frequency operation of the device. 
   Accordingly, it would be advantageous to provide a memory system and memory device having an improved data inversion function. It would also be advantageous to provide an improved method of data inversion for a memory device. Other and further objects and advantages will appear hereinafter. 
   The present invention is directed toward a memory system and memory device having an improved data inversion function, and an improved method of data inversion for a memory device. 
   In one aspect of the invention, a memory device comprises: a memory cell array that stores data; a data input/output (I/O) bus through which the data is written into and read from the memory device; a data inversion circuit that selectively inverts the data when it is written into and read from the memory cell array; and a first input/output (I/O) that carries a read data strobe when reading the data from the memory device, and that carries a write data inversion flag when writing the data into the memory device. 
   In another aspect of the invention, a controller adapted to write data into a memory device and to read the data out of the memory device in response to data strobe signals comprises: a data input/output (I/O) bus through which the controller writes data to, and reads data from, a memory device; and a first input/output (I/O) that carries a read data strobe when reading the data from the memory device, and that carries a write data inversion flag when writing the data into the memory device. 
   In yet another aspect of the invention, a memory system comprises: a memory device having a memory cell array that stores data; a controller, connected to the memory device, that writes the data into the memory device and to reads the data out of the memory device in response to data strobe signals; and a first input/output (I/O) line, between the controller and memory device, that carries a read data strobe when reading the data from the memory device, and that carries a write data inversion flag when writing the data into the memory device. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a memory system with a memory device having a data inversion scheme; 
       FIG. 2  shows a ball (or pin) configuration of a conventional memory device with data inversion; 
       FIG. 3  shows a data processing block diagram of a conventional memory device; 
       FIG. 4  shows a block diagram of a conventional byte 0  data processing circuit; 
       FIG. 5  shows a conventional data inversion circuit; 
       FIG. 6  shows a conventional data toggle detection circuit; 
       FIG. 7  shows a conventional data inversion block; 
       FIG. 8  shows a timing diagram of a memory device with a data inversion circuit; 
       FIG. 9  shows a block diagram of one embodiment of memory system according to one or more aspects of the present invention; 
       FIG. 10  shows a ball (or pin) configuration of one embodiment of a memory device system according to one or more aspects of the present invention; 
       FIG. 11  shows a data processing block diagram of one embodiment of a memory device system according to one or more aspects of the present invention; 
       FIG. 12  shows a block diagram of one embodiment of a byte 0  data processing circuit according to one or more aspects of the present invention; 
       FIG. 13  shows a timing diagram of one embodiment of a memory device with a data inversion circuit according to one or more aspects of the present invention; 
       FIG. 14  shows a timing diagram of another embodiment of a memory device with a data inversion circuit according to one or more aspects of the present invention 
   

   DETAILED DESCRIPTION 
     FIG. 9  shows one embodiment of a memory system  2  operating with data inversion. The memory system  2  includes a memory device  300  and a memory controller  400 . In clear distinction from the memory system  1  of  FIG. 1 , the memory system  2  does not include any DIM signal between the memory controller  400  and the memory device  300 . 
     FIG. 10  shows an exemplary ball (or pin) configuration of the memory device  300 . As can be seen from  FIG. 10 , the balls (or pins) of the memory device  300  similar to those for the memory device  100  shown in  FIG. 2 , except that the memory device  300  does not include the DIM pin  160 , and instead has an extra unused (NC) pin  360 . Also, the balls/pins  311 ,  321 ,  331  and  341  in  FIG. 10  are named RDQS&lt; 0 : 3 &gt;,WFLAG&lt; 0 : 3 &gt;, and the balls/pins  312 ,  322 ,  332  and  342  in  FIG. 10  are named WDQS&lt; 0 : 3 &gt;,RFLAG&lt; 0 : 3 &gt;, as will be explained in greater detail below. 
     FIG. 11  shows a data processing block diagram of one embodiment of the memory device  300 . The memory device  300  includes data processing circuit  310  for byte 0 , data processing circuit  320  for byte 1 , data processing circuit  330  for byte 2 , data processing circuit  340  for byte 4 , and memory cell array  350 . In the memory device  300 , each single bit of data on the RDQS&lt; 0 : 3 &gt;,WFLAG&lt; 0 : 3 &gt; signals at pins  311 ,  321 ,  331  and  341 , and the WDQS&lt; 0 : 3 &gt;,RFLAG&lt; 0 : 3 &gt; signals at pins  312 ,  322 ,  332  and  342 , is dedicated to one data processing unit  310 ,  320 ,  330  or  140  for processing one eight-bit byte of data for the memory cell array  350 . 
   During a data read operation, four bytes of data comprising DQ&lt; 0 : 31 &gt; are output from the data processing units  310 ,  320 ,  330  or  340  via the input/outputs  313 ,  323 ,  333  and  343 , with the RDQS&lt; 0 : 3 &gt;,WFLAG&lt; 0 : 3 &gt; signals functioning as read data strobes. Meanwhile, the WDQS&lt; 0 : 3 &gt;,RFLAG&lt; 0 : 3 &gt; signals function as read data inversion flags for each of the four data bytes. 
   On the other hand, during a data write operation four bytes of data comprising DQ&lt; 0 : 31 &gt; are input to the data processing units  310 ,  320 ,  330  or  340  via the input/outputs  313 ,  323 ,  333  and  343 , with the WDQS&lt; 0 : 3 &gt;,RFLAG&lt; 0 : 3 &gt; signals functioning as write data strobes. Meanwhile the RDQS&lt; 0 : 3 &gt;,WFLAG&lt; 0 : 3 &gt; signals function as write data inversion flags for each of the four data bytes. Also during a data write operation, DM&lt; 0 : 3 &gt; at pins  314 ,  324 ,  334 , and  344 , masks write data for the four data processing circuits  310 ,  320 ,  330  and  340 . 
     FIG. 12  shows a block diagram of one embodiment of the byte 0  data processing circuit  310  of the memory device  300 . The data processing circuits  320 ,  330 , and  340  in  FIG. 3  are configured similarly to data processing circuit  310 . The data processing circuit  310  comprises a number of components, including data strobe signal generator  113 , data control circuit  114 , and the data inversion block  115 . Data control circuit  114  controls data input/output during both data read and data write operations in response to the WDQS 0 ,RFLAG 0  signal, as will be explained below. 
   During a data read operation, the data control circuit  114  outputs the read data DATA&lt; 0 : 7 &gt; as the DQ&lt; 0 : 7 &gt; signals. The data strobe signal generator  113  generates the read data strobe signal and outputs the read data strobe through the output buffer OB 1  as the RDQS 0 ,WFLAG 0  signal. Meanwhile, the read data inversion flag is output from the data inversion block  115  through the output buffer OB 2  to the WDQS 0 ,RFLAG 0  signal. 
   During a data write operation, the data control circuit  114  inputs the read data DATA&lt; 0 : 7 &gt; from the DQ&lt; 0 : 7 &gt; signals in response to the write data strobe signal WDQS 0 ,RFLAG 0  and the data mask signal DM 0 . As shown in  FIG. 12 , during the data write operation, the write data strobe signal WDQS 0 ,RFLAG 0  is provided to a clock input of the data control circuit  114  to clock in the read data DQ&lt; 0 : 7 &gt;. The data mask DM 0  is supplied to an enable input of the data control circuit  114 , disabling operation when the write data is masked. The data inversion block  115  performs a data inversion process during write operations according to the write data inversion flag input to the input buffer IB 1  from the RDQS 0 ,WFLAG 0  signal. 
   The operation of the data inversion block  115  itself is the same as for the memory device  100 , which was described in detail previously with respect to  FIGS. 5–7 . So for brevity, that explanation is not repeated again here. 
     FIG. 13  shows a timing diagram of one embodiment of a memory device with a data inversion scheme. In particular, the timing diagram of  FIG. 13  shows a memory device with so-called “Burst- 4 ” operation wherein four data bytes are written to, or read from, the memory device in a sequential burst. As can be seen from  FIG. 13 , read data (Q 0 , Q 1 , Q 2 , and Q 3 ) are output from the memory device in sync with the rising edge of the RDQS 0 ,WFLAG 0  signal. The WDQS 0 ,RFLAG 0  signal operates as a read data inversion flag during data read operations. Meanwhile, write data (D 0 , D 1 , D 2 , and D 3 ) are input to the memory device in sync with the center of the WDQS 0 ,RFLAG 0  pulses (center strobing). Furthermore, DM 0  masks write data during data write operations. The RDQS 0 ,WFLAG 0  signal operates as a write data inversion flag during data write operations. 
   Table 1 below compares the function of various input/outputs for the memory device  300  of  FIGS. 9 and 11 , with those of the memory device  100  of  FIGS. 1 and 3 . 
   
     
       
             
             
             
           
             
             
             
             
             
           
         
             
                 
               TABLE 1 
             
           
           
             
                 
                 
             
             
                 
               READ OPERATION 
               WRITE OPERATION 
             
           
        
         
             
               INPUT/OUTPUT 
               MEMORY 
               MEMORY 
               MEMORY 
               MEMORY 
             
             
               PINS 
               DEVICE 100 
               DEVICE 300 
               DEVICE 100 
               DEVICE 300 
             
             
                 
             
             
               DM&lt;0:3&gt; 
               Read Data 
               DNC 
               Write Data 
               Write Data 
             
             
                 
               Inversion Flag 
                 
               Masking 
               Masking 
             
             
               DIM 
               DNC 
                 
               Write Data 
             
             
                 
                 
                 
               Inversion 
             
             
                 
                 
                 
               Flag 
             
             
               RDQS&lt;0:3&gt; 
               Read Data 
               Read Data 
               DNC 
               Write Data 
             
             
               (RDQS&lt;0:3&gt;, 
               Strobe 
               Strobe 
                 
               Inversion Flag 
             
             
               WFLAG&lt;0:3&gt;) 
             
             
               WDQS&lt;0:3&gt; 
               DNC 
               Read Data 
               Write Data 
               Write Data 
             
             
               (WDQS&lt;0:3&gt;, 
                 
               Inversion Flag 
               Strobe 
               Strobe 
             
             
               RFLAG&lt;0:3&gt;) 
             
             
                 
             
           
        
       
     
   
   Beneficially, because the memory device  300  operates with four write data inversion flags (RDQS&lt; 0 : 3 &gt;,WFLAG&lt; 0 : 3 &gt;), write data inversion can be individually performed on a data byte by byte basis. This is in contrast to the memory device  100  of  FIG. 1 , and improves the high frequency performance of the device. 
   While preferred embodiments are disclosed herein, many variations are possible which remain within the concept and scope of the invention. 
   For example,  FIG. 14  shows a timing diagram of another embodiment of a memory device with a data inversion scheme. In similarity to  FIG. 13 , the timing diagram of  FIG. 14  shows a memory device with so-called “Burst- 4 ” operation wherein four data bytes are written to, or read from, the memory device in a sequential burst. As can be seen from  FIG. 14 , read data (Q 0 , Q 1 , Q 2 , and Q 3 ) are output from the memory device in sync with the rising edge of the RDQS 0 ,WFLAG 0  signal. DM 0  operates as a read data inversion flag during data read operations. Meanwhile, write data (D 0 , D 1 , D 2 , and D 3 ) are input to the memory device in sync with the center of the WDQS 0  pulses (center strobing). Furthermore, DM 0  masks write data during data write operations. The RDQS 0 ,WFLAG 0  signal operates as a write data inversion flag during data write operations. 
   Table 2 below compares the function of various input/outputs for the memory device whose timing diagram is illustrated in  FIG. 14 , with those of the memory device  100  of  FIGS. 1 and 3 . 
   
     
       
             
             
             
           
             
             
             
             
             
           
         
             
                 
               TABLE 2 
             
           
           
             
                 
                 
             
             
                 
               READ OPERATION 
               WRITE OPERATION 
             
           
        
         
             
               INPUT/OUTPUT 
               MEMORY 
               MEMORY 
               MEMORY 
               MEMORY 
             
             
               PINS 
               DEVICE 100 
               DEVICE 300 
               DEVICE 100 
               DEVICE 300 
             
             
                 
             
             
               DM&lt;0:3&gt; 
               Read Data 
               Read Data 
               Write Data 
               Write Data 
             
             
                 
               Inversion Flag 
               Inversion Flag 
               Masking 
               Masking 
             
             
               DIM 
               DNC 
                 
               Write Data 
             
             
                 
                 
                 
               Inversion 
             
             
                 
                 
                 
               Flag 
             
             
               RDQS&lt;0:3&gt; 
               Read Data 
               Read Data 
               DNC 
               Write Data 
             
             
               (RDQS&lt;0:3&gt;, 
               Strobe 
               Strobe 
                 
               Inversion Flag 
             
             
               WFLAG&lt;0:3&gt;) 
             
             
               WDQS&lt;0:3&gt; 
               DNC 
               DNC 
               Write Data 
               Write Data 
             
             
                 
                 
                 
               Strobe 
               Strobe 
             
             
                 
             
           
        
       
     
   
   Beneficially, because the memory device described in Table 2 also operates with four write data inversion flags (RDQS&lt; 0 : 3 &gt;,WFLAG&lt; 0 : 3 &gt;), write data inversion can be individually performed on a data byte by byte basis. This is in contrast to the memory device  100  of  FIG. 3 , and improves the high frequency performance of the device. 
   These and other such variations would become clear to one of ordinary skill in the art after inspection of the specification, drawings and claims herein. The invention therefore is not to be restricted except within the spirit and scope of the appended claims.