Abstract:
A semiconductor device comprises a semiconductor chip which has a first surface, a pad which is formed directly on the first surface, an oxide film which is formed on the first surface, an insulating film which is formed on the oxide film and a part of the pad, a conductive film which is formed on the insulating film and the pad, a sealing material which covers a part of the conductive film and the insulating film and a bump which is formed over the conductive film, wherein the bump is exposed from a surface of the sealing material.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention generally relates to a semiconductor device, and more particularly, to a semiconductor device which has the improved radiation efficiency.  
           [0003]    This application is a counterpart of Japanese patent application, Serial Number 313592/2001, filed Oct. 11, 2001, the subject matter of which is incorporated herein by reference.  
           [0004]    2. Description of the Related Art  
           [0005]    Recently, spread of the mobile terminal has been accelerated toward smaller, thinner and lighter mobile terminal. In order to achieve compactness, effort has been made to reduce the size of the semiconductor device mounted on the mobile terminal. Such efforts are focused on the development of the semiconductor devices having a semiconductor package in the size of a chip referred to as Chip Size Package (hereinafter CSP).  
           [0006]    The size of CSP is substantially the same as that of the chip or slightly large as that of the chip. There is the resin sealed type semiconductor device which is referred to as Wafer Level Chip Size Package/Wafer Level Chip Scale Package (hereinafter W-CSP) among CSP. The size of W-CSP is the same as that of the chip.  
           [0007]    The conventional CSP type semiconductor device will be described with reference to FIG. 10. FIG. 10( a ) is a plane view showing the conventional semiconductor device having a wafer level chip size package structure individually divided from a wafer. FIG. 10( b ) is a cross sectional view taken line D-D′ of the conventional semiconductor device shown in FIG. 10( a ).  
           [0008]    The conventional semiconductor device comprises a semiconductor chip  1000 , an oxide film  1001 , a plurality of electrical pads  1002 , an insulating film  1003 , a plurality of redistributions  1004 , a plurality of posts  1005 , a plurality of solder bumps  1006  and a sealing resin  1007 . The semiconductor chip  1000  has a main surface having a central area  1000   a  and a peripheral area  1000   b  surrounding to the central area  1000   a . A circuit, e.g. a transistor etc, is formed on the main surface in the peripheral area  1000   b . There is nothing on the main surface in the central area  1000   a . The oxide film  1001  is formed on the main surface of the semiconductor chip  1000  in all areas. The electrical pad  1002  is formed on the oxide film  1001  in the peripheral area  1000   b . The electrical pad  1002  is electrically connected to the circuit formed on the semiconductor chip  1000 . The insulating film  1003  is formed on the oxide film  1001  in all areas and the electrical pad  1002 . The redistribution  1004  is formed on the electrical pad  1002  and the insulating film  1003  in the peripheral area  1000   b.  The redistribution  1004  is electrically connected to the electrical pad  1002 . The post  1005  is formed on the redistribution  1004  being formed on the insulating film  1003  and is electrically connected to the redistribution  1004 . The solder ball  1006  is formed on an end of the post  1005  and is electrically connected to the post  1005 . The sealing resin  1007  seals the insulating film  1003 , the redistribution  1004  and side surfaces of the post  1005 . The heat generated near the main surface of the semiconductor chip  1000  in the conventional semiconductor device, is radiated via the electrical pad  1002 , the redistribution  1004 , the post  1005  and the solder bump  1006  to outside of the semiconductor device.  
           [0009]    However, there is the oxide film  1001  having a low thermal conductivity between the main surface of the semiconductor chip  1000  and the electrical pad  1002 . Therefore, the heat of the semiconductor chip  1000  is hard to conduct to the electrical pad  1002 . In addition, no the conventional semiconductor device has a lot of heat passes. Consequently, the heat generated near the main surface of the semiconductor chip  1000  is not enough radiated so that the demand is satisfied.  
         SUMMARY OF THE INVENTION  
         [0010]    It is an object of the present invention to provide a semiconductor device that may improve radiation efficiency.  
           [0011]    It is another object of the present invention to provide a method for making a semiconductor device that may reduce manufacturing costs.  
           [0012]    It is still another object of the present invention to provide a method for making a semiconductor device that may reduce manufacturing steps.  
           [0013]    It is further object of the present invention to provide a method of making a semiconductor device that may reduce a manufacturing time period.  
           [0014]    According to one aspect of the present invention, for achieving the above object, there is provided a semiconductor device, is provided with a semiconductor device comprising a semiconductor device comprises a semiconductor chip which has a first surface, a pad which is formed directly on the first surface, an oxide film which is formed on the first surface, an insulating film which is formed on the oxide film and a part of the pad, a conductive film which is formed on the insulating film and the pad, a sealing material which covers a part of the conductive film and the insulating film and a bump which is formed over the conductive film, wherein the bump is exposed from a surface of the sealing material.  
           [0015]    The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    [0016]FIG. 1 is a plane view showing a semiconductor device according to a first preferred embodiment of the present invention.  
         [0017]    [0017]FIG. 2 is a cross sectional view taken line A-A′ of the semiconductor device shown in FIG. 1.  
         [0018]    [0018]FIG. 3 is a plane view showing a semiconductor device according to a second preferred embodiment of the present invention.  
         [0019]    [0019]FIG. 4 is a cross sectional view taken line B-B′ of the semiconductor device shown in FIG. 3.  
         [0020]    [0020]FIG. 5 is a plane view showing a semiconductor device according to a third preferred embodiment of the present invention.  
         [0021]    [0021]FIG. 6 is a cross sectional view taken line C-C′ of the semiconductor device shown in FIG. 5.  
         [0022]    [0022]FIG. 7 is a plane view showing a back surface of a semiconductor device according to a fourth or a fifth preferred embodiments of the present invention.  
         [0023]    [0023]FIG. 8 is a cross sectional view taken line D-D′ of the semiconductor device according to the fourth preferred embodiment shown in FIG. 7.  
         [0024]    [0024]FIG. 9 is a cross sectional view taken line D-D′ of the semiconductor device according to the fifth preferred embodiment shown in FIG. 7.  
         [0025]    [0025]FIG. 10 is a cross sectional view of the conventional semiconductor device. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0026]    In what follows, the present invention will be explained with embodiments of the present invention. However, the invention is not limited to the specific embodiments. Moreover, not all the combinations of the characteristics of the present invention described in the embodiments are essential to the problem solving means by the present invention.  
         [0027]    (First Preferred Embodiment)  
         [0028]    A semiconductor device according to a first preferred embodiment of the present invention will be described with reference to FIGS.  1 - 2 . FIG. 1 is a plane view showing the semiconductor device having a wafer level chip size package structure individually divided from a wafer. FIG. 2 is a cross sectional view taken line A-A′ of the semiconductor device shown in FIG. 1. In FIG. 1, the mark ‘S’ being written at the solder bump  211  shows a bump for transmitting a signal and the mark ‘R’ being written at the solder bump  210  shows a bump for conducting heat.  
         [0029]    The semiconductor device according to the first preferred embodiment of the present invention comprises a semiconductor chip  201 , a field oxide film  202 , a plurality of radiation pads (first pads)  203 , a plurality of electrical pads (second pads)  204 , a passivation film  205 , a polyimide film  206 , a plurality of conductive films (redistribution)  207 , a plurality of radiation posts (first posts)  208 , a plurality of electrical posts (second posts)  209 , a plurality of radiation bumps (first bumps)  210 , a plurality of electrical bumps (second bumps)  211 , a sealing resin (sealing material)  212 . Owing to an explanatory circumstance, the number of the pads, the redistributions, the posts and the bumps is limited in FIG. 2.  
         [0030]    The semiconductor chip  201  has a main surface (first surface)  201   a . The main surface  201   a  has a central area  200   a , an intermediate area  200   b  surrounding the central area  200   a  and a peripheral area  200   c  surrounding the intermediate area  200   b.  A circuit, e.g. a transistor or the like, is formed on the main surface  201   a  in the intermediate area  200   b.  The field oxide film  202  is formed on the main surface  201   a  in all areas. The radiation pads  203  are preferably made of aluminum or the like, and are formed on the main surface  201   a  and the field oxide film  202  in the peripheral area  200   c . The radiation pads  203  do not electrically connect to the circuit formed on main surface  201   a.  The radiation pads  203  contact the semiconductor chip  201 , directly. The electrical pads  204  which are preferably made of aluminum or the like, and are formed on the field oxide film  202  in the intermediate area  200   b . The electrical pads  204  electrically connect to the circuit formed on main surface  201   a . The passivation film  205  is formed on the radiation pads  203 , the electrical pads  204  and the field oxide film  202  in all areas. The polyimide film  206  is formed on the radiation pads  203 , the electrical pads  204  and the passivation film  205  in all areas. The conductive film  207  comprises a first conductive film  207   a  contacting the radiation pad  203  and a second conductive film  207   b  contacting the electrical pad  204 . The conductive film  207  is the dual layer structure and is preferably made of titanium film and copper or aluminum film or the like. First, titanium film is formed on the radiation pads  203  or the electrical pads  204  and the polyimide film  206 , and then copper or aluminum film is formed on the titanium film. The conductive film  207   b  electrically connects to the electrical pad  204 . The radiation posts  208  are preferably made of copper or aluminum or the like, and each one has a first edge, a second edge and side surfaces. The radiation posts  208  are formed on the conductive film  207   a  being formed on the radiation pads  203 . The first edges of the radiation posts  208  contact to the conductive film  207   a . The electrical posts  209  are preferably made of copper or aluminum or the like, and each one has a first edge, a second edge and side surfaces. The electrical posts  209  are formed on the conductive film  207   b  being formed on the polyimide film  206 , and electrically connect to the conductive film  207   b . The first edges of the electrical posts  209  contact to the conductive film  207   b . The radiation bumps  210  have the spherical shape and are preferably made of solder. Each of the radiation bumps  210  is mounted on the second edge of the radiation post  210 . The electrical bumps  211  have the spherical shape and are preferably made of solder. Each of the electrical bumps  211  is mounted on the second edge of the electrical post  209 . Shapes of the bumps  210 ,  211  are good as hemisphere or arcs. The electrical bumps  211  electrically connect to the electrical posts  209 . The sealing resin  212  which is preferably made of epoxy resin or the like, and seals the conductive film  207 , the polyimide film  206  and the side surfaces of the radiation posts  208  and the electrical posts  209 .  
         [0031]    The electrical pad  204 , the conductive film  207   b , the electrical post  204  and the electrical bump  211  are abbreviated as a signal bump group. The circuit formed on the semiconductor chip  210  and the electrical bumps  211  are electrically connected through the electrical pads  204 , the conductive film  207   b , the electrical posts  209 . The signal bump group transmits the electrical signal between the circuit formed on the semiconductor chip  201  and the electrical bumps  211 . The semiconductor device of the present invention can transmit signal to an external device through the electrical bump  211 , when the semiconductor device is mounted on the external device through the electrical bumps  211 . The radiation pad  203 , the conductive film  207   a , the radiation post  208  and the radiation bump  210  are abbreviated as a radiation bump group. The radiation bumps  210  radiates heat which is generated in the semiconductor chip  201  to outside the semiconductor device, through the radiation pads  203 , the conductive film  207   a  and the radiation posts  209 . By the way, the signal and radiation bump groups are not formed on the semiconductor chip  210  in the central area  200   a.    
         [0032]    For lack of space in FIG. 1, each of the radiation bump group and the signal bump group is only shown as one. However, it goes without saying that the number of the radiation bump group and the signal bump group should not be limited. In FIG. 1, the radiation bump group is formed as the farthest row from the center of the main surface  201   a . However, if heat being generated in the semiconductor device can be radiated efficiently, all structure elements of the row do not have to be the radiation bump group and it may be a few.  
         [0033]    The semiconductor device according to the first preferred embodiment of the present invention has the following effect.  
         [0034]    (1) The radiation pads are directly formed on the main surface of the semiconductor chip without the field oxide film. Heat generated in the semiconductor chip is directly conducted to the radiation pads, and is radiated to the outside of the semiconductor device through the radiation posts and the radiation bumps. Therefore, the semiconductor device according to the first preferred embodiment of the present invention can radiate heat efficiently as compared with the conventional semiconductor device. Thus, the semiconductor device according to the first preferred embodiment of the present invention can reduce thermal resistance and control high temperature of the semiconductor chip as compared with the conventional semiconductor device. As a result, the semiconductor device according to the first preferred embodiment having a longer lifetime can be obtained.  
         [0035]    (2) The radiation bump group is formed in the row which is the farthest from the center of the main surface of the semiconductor chip. In other words, the signal bump group is formed more inward than the radiation bump group. Therefore, even if water makes inroads into the semiconductor chip from the side surface of the semiconductor device, the radiation bump group can hinder it from making inroad toward the signal bump group. Thus, the signal bump group is hard to be eroded by water. As a result, the semiconductor device according to the first preferred embodiment having a longer lifetime can be obtained.  
         [0036]    (Second Embodiment)  
         [0037]    A semiconductor device according to a second preferred embodiment of the present invention will be described with reference to FIGS.  3 - 4 . FIG. 3 is a plane view showing the semiconductor device having a wafer level chip size package structure individually divided from a wafer. FIG. 4 is a cross sectional view taken line B-B′ of the semiconductor device shown in FIG. 3. The elements corresponding to the elements shown in the first preferred embodiment are given the same numerals, in order to avoid dual explanations about the same elements.  
         [0038]    The semiconductor chip  401  has a main surface (first surface)  401   a . The main surface  401   a  has a central area  400   a  and a peripheral area  400   b  surrounding the central area  400   a . A circuit, e.g. a transistor or the like, is formed on the main surface  401   a  in the peripheral area  400   b . As shown in FIG. 4, the radiation bump group (radiation pad, conductive film, radiation post and radiation bump) is formed on the semiconductor chip in the central area  400   a . The signal bump group (electrical pad, conductive film, electrical post and electrical bump) is formed on the semiconductor chip in the peripheral area  400   b.    
         [0039]    For lack of space in FIG. 3, there are four radiation bump groups in the central area  400   a . However, it goes without saying that the number of the radiation bump group should not be limited. In FIG. 3, the radiation bump group is not formed in the peripheral area  400   b . However, in order to radiate heat generated in the semiconductor device efficiently, the radiation bump group may be formed in the peripheral area  400   b.    
         [0040]    The semiconductor device according to the second preferred embodiment of the present invention can have the same effect (1) being described in the first preferred embodiment of the present invention.  
         [0041]    Furthermore, the semiconductor device according to the second preferred embodiment of the present invention can have the following effect.  
         [0042]    (3) The radiation bump group is formed on the semiconductor chip in the central area which is not used in the conventional semiconductor device. Therefore, it is not necessary to rearrange the circuit and the electrical pads etc. on the semiconductor chip in order to form the radiation bump group.  
         [0043]    (Third Embodiment)  
         [0044]    A semiconductor device according to a third preferred embodiment of the present invention will be described with reference to FIGS.  5 - 6 . FIG. 5 is a plane view showing the semiconductor device having a wafer level chip size package structure individually divided from a wafer. FIG. 6 is a cross sectional view taken line C-C′ of the semiconductor device shown in FIG. 5. The elements corresponding to the elements shown in the first or second preferred embodiments are given the same numerals, in order to avoid dual explanations about the same elements.  
         [0045]    The semiconductor chip  601  has a main surface (first surface)  601   a . The main surface  601   a  has a central area  600   a , an intermediate area  600   b  surrounding the central area  600   a  and a peripheral area  600   c  surrounding the intermediate area  600   b . A circuit, e.g. a transistor or the like, is formed on the main surface  601   a  in the intermediate and/or peripheral areas  600   b ,  600   c . As shown in FIG. 6, the radiation bump group (radiation pad, conductive film, radiation post and radiation bump) is formed the most inward in plurality of the bumps being formed on the semiconductor chip in the intermediate area  600   b . In FIG. 5, the radiation bump group is not formed in the peripheral area  600   c . However, in order to radiate heat generated in the semiconductor device efficiently, the radiation bump group may be formed in the peripheral area  600   c . By the way, the signal and radiation bump groups are not formed on the semiconductor chip in the central area  600   a.    
         [0046]    The semiconductor device according to the third preferred embodiment of the present invention can have the same effect (1) being described in the first preferred embodiment of the present invention.  
         [0047]    Furthermore, the semiconductor device according to the third preferred embodiment of the present invention can have the following effect.  
         [0048]    (4) The radiation bump group is formed the most inward in plurality of rows which the bumps are formed on the semiconductor chip in the intermediate area. Therefore, the semiconductor device according to the third embodiment of the present invention can effectively radiate heat generated in the semiconductor device.  
         [0049]    (Fourth Embodiment)  
         [0050]    A semiconductor device according to a fourth preferred embodiment of the present invention will be described with reference to FIGS.  7 - 8 . FIG. 7 is a plane view showing the semiconductor device having a wafer level chip size package structure individually divided from a wafer. FIG. 8 is a cross sectional view taken line D-D′ of the semiconductor device shown in FIG. 7. The elements corresponding to the elements shown in the first, second or third preferred embodiments are given the same numerals, in order to avoid dual explanations about the same elements.  
         [0051]    The semiconductor chip  800  has a main surface (first surface)  800   a  and a back surface (second surface)  800   b.  A circuit, e.g. a transistor or the like, is formed on the main surface  800   a.  A plurality of grooves  801  are formed on the back surface  800   b.  Each of the grooves  801  has a V-shape. Each of the grooves  801  is arranged in parallel each other. Each of the grooves  801  is arranged from a certain edge of the back surface  800   b  to another edge being in opposition to the certain edge. It goes without saying that the grooves may be formed in a grid pattern. The width, the depth and the number of each groove should be set in consideration of the strength (stress) of the semiconductor device. The groove  801  is formed by etching to become a V-shape.  
         [0052]    By the way, FIG. 9 is a cross sectional view of the semiconductor device showing the varied pattern of the fourth preferred embodiment. As shown in FIG. 9, the groove  901  does not have the V-sharp but a U-sharp. As mentioned above, the width, the depth and the number of each groove should be set in consideration of the strength (stress) of the semiconductor device. The groove  901  can be formed on the back surface  900   b  at the same time in a dicing process of the semiconductor device. There is no need to use the mask for forming the slit of the U-sharp, because the method does not have the etching step.  
         [0053]    The semiconductor device according to the fourth preferred embodiment of the present invention can have the following effect.  
         [0054]    (5) The slits are formed on the back surface of the semiconductor device. The distance between the main surface which has the circuits and the bottom of the back surface becomes short, and a surface area of the back surface becomes large. Therefore, the semiconductor device according to the fourth preferred embodiment of the present invention can effectively radiate heat generated in the semiconductor device.  
         [0055]    (6) When the semiconductor device has the slit of the U-sharp, there is no need to use the mask for forming the slit. Therefore, the semiconductor device according to the fourth preferred embodiment of the present invention can improve a working efficiency and reduce an increase of the costs.  
         [0056]    While the preferred form of the present invention has been described, it is to be understood that modifications will be apparent to those skilled in the art without departing from the spirit of the invention.  
         [0057]    The scope of the invention, therefore, is to be determined solely by the following claims.