Abstract:
A circuit for converting a phase signal to an amplitude signal comprises a signal separating circuit which receives a phase signal and provides in accordance therewith a phase conversion signal and a sign signal, and a conversion unit including a conversion table in which a predetermined signal wave in a reference phase angle range is stored. A phase angle of a phase signal is converted into a converted phase angle, when the phase angle is outside a reference phase angle range. An amplitude signal is obtained by reading an amplitude based on the phase angle or the phase converted angle from the conversion unit.

Description:
FIELD OF THE INVENTION 
     The invention relates to a circuit for converting a phase signal to an amplitude signal, and more particularly, to a circuit for converting a phase signal to an amplitude signal in which a Sine look-up table ROM is used in a conversion unit. 
     BACKGROUND OF THE INVENTION 
     One type of a conventional circuit for converting a phase signal to an amplitude signal is included, for instance, in a digital frequency modulator. The circuit for converting a phase signal to an amplitude signal has been described on pages 355 to 361 of &#34;IEEE Transactions on Consumer Electronics, Vol. CE-32, No. 3, August 1986,&#34; and comprises a Sine look-up table ROM, in which amplitude data of one period sinusoidal wave at addresses of 0 to 2 π are stored. In the digital frequency modulator, the look-up table ROM is specified to have an input bit width of 10 bits for an address bit width, and an output bit width of 8 bits for a data bit width, and a clock signal of approximately 20 MHz, by which an operating speed is determined in the processing of video signals, is used. The details of the digital frequency modulator will be explained later. 
     However, the circuit for converting a phase signal to an amplitude signal has a disadvantage in that the Sine look-up table ROM is of a large memory capacity as much as 8 Kbits. Furthermore, it has another disadvantage in that an access to the look up table ROM having the input bit width of 10 bits becomes difficult in the use of the 20 MHz clock signal. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of this invention to provide a circuit for converting a phase signal to an amplitude signal, in which an input bit width and an output bit width of a Sine look-up table ROM are decreased to lower a memory capacity thereof. 
     It is a further object of this invention to provide a circuit for converting a phase signal to an amplitude signal, in which an operating speed is increased. 
     According to this invention, a circuit for converting a phase signal to an amplitude signal, comprises: 
     a signal separating and selecting circuit for providing a phase conversion signal and a sign signal in accordance with an input of a phase signal thereto, the phase conversion signal being a phase angle of the phase signal in a first state that the phase angle is in a reference phase angle range of a predetermined signal wave, while the phase conversion signal being a converted phase angle in the reference phase angle range, at which an amplitude of the predetermined signal wave is equal in its absolute value to an amplitude of the phase signal in a second state that the phase angle of the phase signal is outside the reference phase angle range, and the sign signal being a signal indicating whether a sign of the phase signal is different from a sign of the predetermined signal wave at the converted phase angle; 
     a conversion unit having a conversion table in which the predetermined signal wave is stored in the reference phase angle range, and from which an amplitude signal is read out in accordance with the phase conversion signal; and 
     a sign modifying circuit for modifying a sign of the amplitude signal supplied thereto from the conversion unit in accordance with the sign signal, where the sign of the phase signal is different from the sign of the predetermined signal wave. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     This invention will be explained in more detail in conjunction with appended drawings, wherein: 
     FIG. 1 is a block diagram showing a digital frequency modulator including a conventional circuit for converting a phase signal to an amplitude signal; 
     FIG. 2 is an explanatory diagram showing a look-up table ROM included in the conventional circuit for converting a phase signal to an amplitude signal; 
     FIG. 3 is a block diagram showing a digital frequency modulator including a circuit for converting a phase signal to an amplitude signal in a first preferred embodiment according to the invention; 
     FIG. 4 is an explanatory diagram showing a look-up table ROM included in the circuit for converting a phase signal to an amplitude signal in the first preferred embodiment; 
     FIG. 5 is a block diagram showing a digital color encoder including a look-up table ROM in a second preferred embodiment according to the invention, 
     FIG. 6 is a block diagram showing a signal separating circuit included in the circuit for converting a phase signal to an amplitude signal in the second preferred embodiment; 
     FIG. 7A is an explanatory diagram showing a look-up table ROM included in the circuit for converting a phase signal to an amplitude signal in the second preferred embodiment; and 
     FIG. 7B is an explanatory diagram showing a conventional look-up table ROM, to which the look-up table ROM of FIG. 7A is compared in its memory capacity. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before explaining a circuit for converting a phase signal to an amplitude signal in the first preferred embodiment according to the invention, the aforementioned conventional circuit for converting a phase signal to an amplitude signal will be again explained in reference to FIGS. 1 and 2. 
     FIG. 1 shows the digital frequency modulator, in which the conventional circuit for converting a phase signal to an amplitude signal is included, comprising an input terminal T IN , to which a digital signal V(nT) is applied, a multiplier 11 for multiplying the digital signal V(nT) by a constant value &#34;m&#34; of a modulation index, an adder 12 A  for adding a first input signal which is an output signal of the multiplier 11 and a second input signal, an adder 12 B  for adding an output signal of the adder 12 A  and a constant value WcT, where Wc is a center angular frequency of a FM carrier, and T is a sampling interval, a delay circuit 13 for delaying an output signal of the adder 12 B  to provide the second input signal of the adder 12 A , and a phase-to-amplitude converting circuit 14 including a Sine look-up table ROM 15 for converting an output signal of the adder 12 B  to an amplitude signal which is a digital FM signal f(nT), and an output terminal T OUT , from which the digital FM signal f(nT) is supplied. 
     In operation, the digital signal V(nT) supplied to the input terminal T IN  is multiplied in the multiplier 11 by the modulation index &#34;m&#34;, so that the output signal of m·V(nT) is obtained in the multiplier 11. The output signal of m·V(nT) is supplied to a loop integral circuit composed of the adders 12 A  and 12 B  and the delay circuit 13, in which the output signal of m·V(nT) is integrated along with the constant value of WcT to provide a phase signal θ(nT) having information of a phase angle θ. 
     Accordingly, the phase signal θ(nT) is defined as follows: ##EQU1## 
     The phase signal θ(nT) is then converted to a digital FM signal f(nT) in the phase-to-amplitude converting circuit 14. Here, if it is assumed that the phase signal θ(nT) is of a binary digit of N bits, the phase-to-amplitude converting circuit 14 can be of the Sine look-up table ROM 15 representing a relation of A ##EQU2## where A is amplitude, θ is a phase input signal, and θ o  is an arbitrary phase. 
     FIG. 2 shows a converting characteristic in the look-up table ROM 15, assuming that the bit number N is 10, the arbitrary phase θ o  is 0, and the amplitude A is 127. As clearly shown therein, the look-up table ROM 15 stores data ranging from -127 to 127 along the vertical axis at addresses of 0 to 2 π ranging from 0 to 1023 along the horizontal axis. 
     Thus, the digital FM signal f(nT) is obtained at the output terminal T OUT  as follows: ##EQU3## 
     In the conventional circuit for converting a phase signal to an amplitude signal, however, the aforementioned disadvantages are resulted. 
     Next, a circuit for converting a phase signal to an amplitude signal in the first preferred embodiment according to the invention, which is included in the aforementioned digital frequency modulator, will be explained in FIG. 3, wherein like parts are indicated by like reference numerals as used in FIG. 1. 
     In FIG. 3, the circuit for converting a phase signal to an amplitude signal is shown by a phase to-amplitude converting circuit 100, which comprises a signal separating and selecting circuit 110, a conversion unit 120, and a sign modifying circuit 130. 
     The signal separating and selecting circuit 110 comprises a signal separating circuit 111, an inverter 112, and a multiplexer circuit 113 of conventional type, and supplies a phase conversion signal θ (nT)&#39; to the conversion unit 120 by receiving the phase signal θ(nT) from the adder 12 B . All multiplexers used in the conversion circuit of this invention are of conventional 88 as CMOS IC standard published in 1988 in Japan. The phase conversion signal θ(nT)&#39; is obtained by converting a phase angle of the phase signal θ(nT). Where the phase angle of the phase signal θ(nT) is in one of respective ranges in the table 1, the phase signal θ(nT) is converted to the phase conversion θ(nT)&#39; having a phase angle indicated in the table 1. 
     
                       TABLE 1______________________________________PHASE ANGLE θ OF               PHASE ANGLEPHASE SIGNAL θ (nT)               CONVERSION______________________________________θ˜π/2               NON-CONVERSIONπ/2˜π   π-θπ˜3π/2  θ-π3π/2˜2π 2π-θ______________________________________ 
    
     Furthermore, the signal separating and selecting circuit 110 supplies a sign signal Ss, which indicates whether or not an amplitude of the phase signal θ(nT) is equal in its sign to an amplitude of a reference signal having a phase angle range of 0 to π/2, to the sign modifying circuit 130. 
     The conversion unit 120 stores a conversion table of a sinusoidal wave having a range of 0 to π/2 in the form of ROM as shown in FIG. 4, by which the phase conversion signal θ(nT)&#39; is converted to an amplitude signal S A . 
     The sign modifying circuit 130 comprises a multiplier 131 for multiplying the amplitude signal S A  by a coefficient of &#34;-1&#34;, and a multiplexer circuit 132 of conventional type for supplying a signal selected from the amplitude signal S A  and an inverted signal which is obtained from the amplitude signal S A  by inverting a sign thereof. 
     In operation, the digital signal V(nT) is applied to the input terminal T IN , so that the phase signal θ(nT) is supplied from the adder 12 B  to the signal separating and selecting circuit 110 in the same manner as described in the conventional digital frequency modulator before. 
     Here, if it is assumed that the phase signal θ (nT) is of a binary digit of N bits &#34;θ N-1 , θ N-2 , . . . θ 1 , and θ o  &#34;, among which θ N-1  is the MSB, and θ o  is the LSB, and has information of a phase angle in a range of 0 to 2 π, the signal separating circuit 111 supplies the bit of θ N-1  which is the sign signal S S  to the sign modifying circuit 130, the bit of θ N-2  which is a control signal for the swiching over circuit 113 to a control terminal of the swiching over circuit 113, and the bits of θ N-3 , . . . , θ 1 , and θ o  which are data to an input terminal of the inverter 112 and the multiplexer circuit 113. 
     Where the bit of θ N-2  is &#34;0&#34;, that is, the phase angle θ of the phase signal θ(nT) is in a range of 0 to π/2 and π to 3π/2, the multiplexer circuit 113 supplies the data of θ N-3 , . . . , θ 1  and θ o , which are received directly from the signal separating circuit 111 as the phase conversion signal θ(nT)&#39;, to the conversion unit 120. On the other hand, where the bit of θ N-2  is &#34;1&#34;, that is, the phase angle θ of the phase signal θ(nT) is in a range of π/2 to π and 3π/2 to 2 π, the multiplexer circuit 113 supplies the data of θ N-3 , ... θ 1 , and θ o , which are inverted in the inverter 112 as the phase conversion signal θ (nT)&#39;, to the conversion unit 120. Thus, the phase signal θ(nT) is converted to the phase conversion signal θ(nT)&#39; of (N-2) bits in consideration of a range selected from ranges 0 to π/2, π/2 to π, π to 3π/2 and 3π/2 to 2 π, to which the phase angle θ of the phase signal θ(nT) belongs. 
     In the conversion unit 120, the phase conversion signal θ(nT)&#39; is considered to be a phase signal having a phase angle in a range of 0 to π/2, so that the amplitude signal S A  is obtained by reading data at a corresponding address from the Sine look-up table ROM. In other words, the phase conversion signal θ(nT)&#39; is converted to the amplitude signal S A  in accordance with a conversion represented by ##EQU4## where A is an amplitude, θ&#39; is a phase angle of the phase conversion signal θ(nT)&#39;, and θ o   &#39;   is a phase angle which is half a resolution of the phase conversion signal θ (nT)&#39; to be equal to π/2 N . The conversion characteristic of the conversion unit 120 is shown in FIG. 4, where the amplitude A is 127, the bit number N is 10. 
     In the sign modifying circuit 130, where the sign signal S S  is &#34;0&#34;, that is, the phase angle θ of the phase signal θ(nT) is in a range of 0 to π, the amplitude signal S A  directly supplied from the conversion unit 120 is supplied through the multiplexer circuit 132 to the output terminal T OUT . On the other hand, where the sign signal S S  is &#34;1&#34;, that is, the phase angle θ of the phase signal θ(nT) is in a range of π to 2 π, the amplitude signal S A  which is inverted in the multiplier 131 by multiplying &#34;-1&#34; thereto is supplied through the multiplexer circuit 132 to the output terminal T OUT . 
     Here, if it is assumed that the bits of θ N-1  and θ N-2  are both &#34;0&#34;, the phase signal θ(nT) has a phase angle θ which is in a range of 0 to π/2 (the reference phase angle range). 
     In this situation, the phase conversion signal θ (nT)&#39; is of a signal including the bits of θ N-3 , . . . , θ 1  and θ o , which is then converted in the conversion unit 120 to the amplitude signal S A  of ##EQU5## This amplitude signal S A  is passed through the multiplexer circuit 132 without the modification of a sign in the sign modifying circuit 130, so that an output signal of the phase-to-amplitude converting circuit 100 is the amplitude signal S A  of ##EQU6## 
     On the other hand, if it is assumed that the bit of θ N-1  is &#34;0&#34;, while the bit of θ N-2  is &#34;1&#34;, the phase angle θ of the phase signal θ(nT) is in a range of π/2 to π. 
     In this situation, the phase conversion signal θ  (nT)&#39; is a signal of the bits θ N-3 , . . . θ 1  and θ o . 
     Accordingly, the equation (3) is obtained, because the bits of θ N-1  and θ N-2  are &#34;0&#34; and &#34;1&#34;, respectively. ##EQU7## 
     Therefore, the amplitude signal S A  of the conversion unit 120 is defined in the equation (4). ##EQU8## 
     This amplitude signal S A  is directly the output signal f(nT) of the phase to amplitude conversion circuit 100. 
     Here, if it is assumed that the equations (5) and (6) are met, the right side R of the equation (4) is defined in the equation (7). ##EQU9## 
     Furthermore, if it is assumed that the bit of θ N-1  is &#34;1&#34;, while the bit of θ N-2  is &#34;0&#34;, the phase angle θ of the phase signal θ(nT) is in a range of π to 3π/2. Therefore, the equations (8) and (9) are obtained in the same manner as above. ##EQU10## 
     In this situation, the amplitude signal S A , which is multiplied in the multiplier 131 by the coefficient of &#34;-1&#34;, is passed through the multiplexer circuit 132, because the bit of θ N-1  is &#34;1&#34;. As a result, the output signal f(nT) of the phase to amplitude conversion circuit 100 is obtained as defined in the equation (10). ##EQU11## 
     where the bits of θ N-1  and θ N-2  are both &#34;1&#34;, the output signal f(nT) of the phase-to-amplitude conversion circuit 100 is also obtained as defined in the equation (11). ##EQU12## 
     As understood from the above, the phase-to-amplitude conversion circuit 100 is realized to operate in the same manner as the conventional circuit for converting a phase signal to an amplitude signal, in spite that a memory capacity of the look- up table ROM is decreased by one-eighth, because two bits are decreased in the input bit width, and one bit is decreased in the output bit width. 
     In the first preferred embodiment, although the offset value θ o   &#39;   of the phase conversion signal θ(nT)&#39; supplied to the look-up table ROM of the conversion unit 120 is limited as defined in the equation (6), no problem occurs in converting a phase signal to an amplitude signal. 
     FIG. 5 shows a circuit for converting a phase signal to an amplitude signal in the second preferred embodiment according to the invention which is included in a digital color encoder. The digital color encoder comprises an input terminal T IN , to which a constant value of &#34;K&#34; is applied, an adder 12 C  for adding the constant value &#34;K&#34; and a delayed signal which is explained later, a remainder calculation circuit 14 A  for carrying out a predetermined remainder calculation of an output signal of the adder 12 C , a delay circuit 13 A  for delaying an output signal of the remainder calculation circuit 14 A  to provide the delayed signal, an adder 12 D  for adding the output signal of the remainder calculation circuit 14 A  and a Sine/Cosine control signal S SC  applied to an input terminal T SC , a remainder calculation circuit 14 B  for carrying out a predetermined remainder calculation of an output signal of the adder 12 D , a phase to amplitude conversion circuit 100 which will be explained later, latch circuits 15 A  and 15.sub. B for latching an output signal of the phase-to-amplitude conversion circuit 100, a multiplier 11 A  for multiplying multiplying a latched signal of the latch circuit 15 A  by a color-difference signal (B-Y) applied to an input terminal T BY , a multiplier 11 B  by a color-difference signal (R-Y) applied to an input terminal T RY , and an adder 12 E  for adding output signals of the multipliers 11 A  and 11 B  to provide a digital color encoder output signal C(nT) which is supplied from an output terminal T OUT  to a following stage. 
     The phase-to-amplitude conversion circuit 100 includes a signal separating and selecting circuit 110 for providing a sign signal S S  and a phase conversion signal θ(nT)&#39; by receiving a phase signal θ 2  (nT) from the remainder calculation circuit 14 B , a conversion unit 120 including a look-up table ROM for converting the phase conversion signal θ 2  (nT)&#39; to an amplitude signal S A , and a sign modifying circuit 130 including a multiplier 131 for multiplying the amplitude signal S A  by a coefficient of &#34;-1&#34; and a switching-over multiplexer circuit 132 for selecting a signal from the amplitude signal S A  and an amplitude signal inverted in the multiplier 131 to provide the selected signal to the latch circuits 15 A  and 15 B . 
     FIG. 6 shows the signal separating and selecting circuit 110 included in the phase to amplitude conversion circuit 100, where a ratio between a sub-carrier frequency f SC  to be color-encoded and a sampling frequency f is K/L (K:L). Here, K is a natural number, and L is a binary digit of N bits and a natural number of a multiple of four. The signal separating and selecting circuit 110 comprises comparators 114 A , 114 B  and 114 C , first input terminals of which are connected to an input terminal T 1  for receiving the phase signal θ 2  (nT), and second input terminals of which are connected to corresponding input terminals T 2 , T 3  and T 4  for receiving constant values of &#34;L/4&#34;, &#34;L/2&#34; and 3L/4&#34;, respectively, subtracters 115 A , 115 B  and 115 C , first input terminals of which are connected to the input terminal T 1  for receiving the phase signal θ 2  (nT), and second input terminals of which are connected to corresponding input terminals T 5 , T 6  and T 7  for receiving constant values of &#34;L/2-1&#34;, &#34;L/2&#34; and &#34;L-1&#34;, respectively, and a multiplexer circuit 113 a for selecting a signal from the phase signal θ 2  (nT), and output signals of the subtracters 115 A , 115 B  and 115 C  in accordance with comparison results of the comparators 114 A , 114 B  and 114 C . 
     In operation, the constant value &#34;K&#34; is supplied to the input terminal T IN , and is integrated in an integral circuit including the adder 12 C , the remainder calculation circuit 14 A  and the delay circuit 13 A  to provide the phase signal θ 1  (nT) to the adder 12 D . In the remainder calculation circuit 14 A , a remainder calculation is carried out in accordance with the constant value of &#34;L&#34;. Therefore, the phase signal θ 1   (nT) is defined in the equation (12). 
     
         θ.sub.1 (nT)=n·k modulo L                   (12) 
    
     Then, the Sine/Cosine signal of &#34;0&#34; is applied to the input terminal T SC  connected to the adder 12 D , where an output signal of the phase to amplitude conversion circuit 100 corresponds to a Cosine value. In the latter case, the phase signal θ 1  (nT) is added in the adder 12 D  by the value of &#34;L/4&#34;, thereby leading a phase of the phase signal θ 1  (nT) by π/2, so that a Sine value is converted to a Cosine value in the state that the value 0 to L of the phase signal θ 1  (nT) corresponds to a phase angle of 0 to 2π. The output signal of the adder 12 D  is supplied to the remainder calculation circuit 14 B , in which a remainder calculation is carried out in accordance with the constant value of &#34;L&#34;. As a result, an output signal of the remainder calculation circuit 14 B  is a phase signal θ 2  (nT) resulted from a conversion of the output signal of the adder 12 D  to values of 0 to (L-1). The phase signal θ 2  (nT) is supplied to the phase-to-amplitude conversion circuit 100, in which the sign signal S S  and the phase conversion signal θ 2  (nT)&#39; are obtained depending on a phase angle θ 2  of the phase signal θ 2  (nT) in the signal separating and multiplexer circuit 110 as shown in the table 2. 
     
                       TABLE 2______________________________________PHASE ANGLE θ.sub.2 PHASE ANGLE θ.sub.2OF PHASE SIGNAL         SIGN        OF PHASE SIGNALθ.sub.2 (nT)         SIGNAL SS   θ.sub.2 (nT)&#39;______________________________________0 ≦ θ.sub.2 &lt; L/4         0           θ.sub.2L/4 ≦ θ.sub.2 &lt; L/2         0           L/2 - θ.sub.2 - 1L/2 ≦ θ.sub.2 &lt; 3L/4         1           θ.sub.2 - L/23L/4 ≦ θ.sub.2 &lt; L         1           L - θ.sub.2 - 1______________________________________ 
    
     In the conversion unit 120, a conversion represented by ##EQU13## is carried out, where A is an amplitude, and θ o  &#34; is a phase which is half a resolution of a phase input signal represented by θ 2   &#39;   and is equal to π/2 N . 
     FIG. 7A shows a conversion characteristic of the conversion unit 120, wherein the amplitude A is 127, the bit number N is 9, and the value L is 400. The amplitude signal S A  which is thus obtained in the conversion unit 120 is modified in its sign depending on a content of the sign signal S S , as explained in the first preferred embodiment. Consequently, tho Sine and Cosine values of an oscillation signal having a predetermined frequency of the color sub-carrier are obtained at the output terminal of the phase to amplitude conversion circuit 100. The output signal of the phase to amplitude conversion circuit 100 is latched in the latch circuits 15 A  and 15 B , so that the latched signals are processed in a calculation circuit including the multipliers 11 A  and 11 B , to which the color-difference signals (B Y) and (R-Y) are supplied along with the latched signals, respectively, and the adder 12 E , to which the multiplied results are supplied, thereby providing the color signal C(nT) at the output terminal T OUT  as defined in the equation (13). ##EQU14## 
     In this manner, even if a value of a phase signal which is in a range of 0 to 2 π is not a value which is an exponent of 2(2 N ), the present invention can be embodied. In a conventional digital color encoder, although a look-up table ROM is required to be provided in a conversion unit as shown in FIG. 7B, the look up table ROM becomes small in the second preferred embodiment as shown in FIG. 7A. That is, two bits are decreased in an input bit width, and one bit is decreased in an output bit width. 
     Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modification and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.