Abstract:
The voltages on the high voltage rails of sense amplifiers in dynamic random access memories are controlled during turn-on of the sense amplifiers to remain approximately at the voltage of the voltage source internal to the integrated circuit chip by connecting a voltage source external to the chip to the high voltage rails until the voltages on the rails equal the voltage from the chip&#39;s internal voltage source at which time the external voltage source is disconnected.

Description:
FIELD OF THE INVENTION 
     This invention relates to dynamic random access memories (&#34;DRAMs&#34;) with internal voltage converters and in particular to structure and a method for preventing the bit lines associated with DRAM arrays from being charged above or below the internal power supply voltage level. 
     BACKGROUND 
     Dynamic random access memories use sense amplifiers to sense the state of a memory cell containing information being read out of the memory. Each sense amplifier normally is off but to read out the state of the memory cell connected to the sense amplifier, the sense amplifier must be turned on. This is done by applying a pullup voltage SLP and a pull-down voltage SLN to the power supply and reference voltage rails, respectively, of the sense amplifier. Unfortunately, when the sense amplifiers in a DRAM are turned on the current drawn by the sense amplifiers is quite substantial and causes the internal voltage levels on the bit line BL and bit line BL connected to each sense amplifier to vary and in particular to either overcharge above the internal voltage IV CL  of the circuit or not charge high enough and therefore charge below IV CL . The larger the capacitance associated with the bit lines BL and BL the greater the dip in the internal voltage IV CL . 
     One prior art technique for overcoming this problem is to connect the external voltage EV CL  to the SLP line for a portion of the time during which the sense amps are being activated. Thus, FIG. 1A shows a prior art circuit for supplying the voltage SLP to the sense amp high voltage rail. In FIG. 1A, P-channel transistor P1 is turned on by a low voltage sensing control signal applied to the gate of P1. A voltage IV CL  is then applied directly to the SLP line. However, as shown in FIG. 1B, the current drawn by the SLP line is so substantial as to cause the voltage IV CL  to dip when the signal SLP is applied to the high voltage rails of the sense amplifiers to turn on the sense amplifiers. The signal SLP is applied to the high voltage rails of the sense amplifiers after the RAS (row address strobe) signal goes high as indicated in FIG. 1B by RAS, the complement of RAS, going low. 
     One circuit for overcoming this problem is shown in FIG. 1C. This prior art circuit uses an external voltage source EV CL  together with the internal voltage source IV CL  to supply current to the high voltage line SLP during the turning on of the sense amplifiers. As shown in FIG. 1D, voltage is applied to the sensing control signal associated with P channel transistors P3 and P4 to turn on these two transistors when RAS goes from high to low. In addition low voltage DC (not shown in FIG. 1D) is applied to P-type transistor P2 to turn on transistor P2. The current from the external voltage source EV CL  is then applied to the SLP line simultaneously with the current from the internal voltage source IV CL . Thus, the current supplied by the SLP line during the turning on of the sense amplifiers is sufficient to prevent a dip in IV CL . However, the duration of the voltage D.C. applied to the gate of transistor P2 is difficult to control and thus the actual voltage achieved by the SLP lead line is difficult to control. Since the voltage on the SLP lead determines the ultimate voltage on the bit line BL or BL, over-charging or under-charging of the SLP rail to the sense amplifiers (as shown in FIG. 1D) is important. The difficulty in controlling the duration of the voltage D.C. applied to P channel transistor P2 as a function of the characteristics of the particular memory array and of the particular portions of the memory array being activated results in a certain overcharge or undercharge of the rail SLP as shown in FIG. 1D. 
     SUMMARY OF THE INVENTION 
     In accordance with this invention, a structure and method are provided to prevent the bit lines and the SLP rails associated with the sense amps of a DRAM from being charged above or below the internal power supply level IV CL . This is done by monitoring the SLP and SLN signals. An output voltage is then produced proportional to the bit line voltage. Comparing this bit line voltage to a reference voltage in a feedback loop produces a feedback signal to control the turning on or turning off of the external voltage supply as a function of the bit line voltage level. This invention substantially eliminates overshoot or undershoot of the internal voltage level associated with a DRAM integrated circuit. 
     This invention will be more fully understood in connection with the following detailed description taken together with the drawings. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1A shows a prior art circuit for charging the SLP line from the internal voltage source IV CL . 
     FIG. 1B illustrates waveforms associated with the structure of FIG. 1A. 
     FIG. 1C shows an alternative prior art circuit for applying an external voltage EV CL  from an external voltage source to provide power to the SLP line during the turning on of the sense amplifiers for a selected period of time. 
     FIG. 1D shows waveforms associated with the circuit of FIG. 1C. 
     FIG. 2A shows the circuit arrangement of a sense amp and related circuitry associated with a memory array. 
     FIG. 2B shows waveforms associated with the circuit arrangement of FIG. 2A. 
     FIG. 3 shows a circuit for measuring the voltage applied to the SLP line in a memory array. 
     FIG. 4 shows the feedback circuitry using the signal generated by the circuitry of FIG. 3 and the reference voltage to control the voltage applied to the SLP rail. 
    
    
     DETAILED DESCRIPTION 
     While one embodiment of this invention will be described below those skilled in the art will recognize that other circuitry is capable of implementing this invention. Thus the following description is illustrative only and not limiting. 
     FIGS. 2A and 2B illustrate the circuitry associated with a single sense amplifier utilized in a dynamic random access memory and the waveforms associated with that circuitry to initiate a read operation. As shown in FIG. 2B, the signal RAS (complement of the row address strobe signal RAS) goes low to initiate a read cycle. When EQ is high, transistors Q3, Q4 and Q5 are on thereby equalizing the bitline BL and bitline BL voltages at V BP , a voltage halfway between VDD, the supply voltage, and VSS, the reference or ground voltage. The capacitance C C  shown in FIG. 2A represents the parasitic capacitance associated with the bitline BL and bitline BL. The sense amplifier is made up of N type transistors N1 and N2 and P type transistors P1 and P2. When the word line WL 21-1 associated with memory cell 20-1 goes high, N channel pass transistor Q associated with memory cell 20-1 turns on thereby allowing the charge on capacitor C in memory cell 20-1 to affect the voltage on bitline BL 22-1. The BL 22-2 is not connected to memory cell 20-1, but rather is connected to memory cell 20-2. Because the word line 21-2 has remained low, N channel pass transistor Q associated with memory cell 20-2 remains off and thus memory cell 20-2 does not affect the state of BL 22-2. After word line 21-1 goes high, the signal SLP goes high while the signal SLN goes low thereby activating the sense amp 23-1. Sense amp 23-1 senses the voltage on bitline BL 22-1 on node A and senses the voltage on BL 22-2 on node B. If the charge stored on capacitor C in memory cell 20-1 represents a binary 1, then typically charge would be dumped from capacitor C onto bitline 22-1 causing the voltage on bitline BL 22-1 to rise relative to the voltage on bitline BL 22-2. On the other hand, if the charge on capacitor C represents a binary 0, the turning on of transistor Q in memory cell 20-1 will cause charge to transfer from bitline 22-1 to capacitor C thereby lowering the voltage on bitline 22-1 relative to the voltage on bitline BL 22-2. 
     Assuming that charge on capacitor C represents a binary 1, then bitline 22-1, using conventional logic, will be at a higher voltage than bitline BL 22-2 and thus node A will be at a higher voltage than node B. When the signal SLP goes high, node A will cause N channel transistor N2 to turn on and P channel transistor P2 to turn off relative to N channel transistor N1 and P channel transistor P1. Consequently, the voltage on node B, which is connected to the drain of N type transistor N2 and to the drain of P type transistor P2, will be pulled down towards the voltage SLN on lead 24-1 and the voltage on node A will be pulled up to the voltage on SLP lead 24-2 by P type transistor P1 turning on. N type transistor N1 and P type transistor P2 will both be off. Accordingly sense amplifier will detect and amplify the signal difference between bitline 22-1 and bitline 22-2. 
     However, as shown above in FIGS. 1B and 1C, the application of a voltage to the SLP line requires a substantial amount of charge to lift the voltage on SLP line 24-2 to the high level corresponding to the internal voltage IV CL  on the chip. In accordance with this invention, a circuit is provided to assist the voltage on SLP line 24-2 to reach its desired level without overshoot or undershoot. 
     As shown in FIG. 3, the signal SLP is applied to the source of P channel transistor P3 and the signal SLN is applied to the source of N channel transistor N3. The drains of P3 and N3 are connected together. The gates of transistors N3 and P3 are connected together and to the SLN lead 24-1. The potential on lead SLN 24-1 is the circuit reference potential (usually the circuit ground). P type transistor P3 has its substrate connected to its source and N type transistor N3 has its source connected to the gates of both P3 and N3. Thus transistor N3 is essentially off but the voltage at node C corresponding to the drains of transistors P3 and N3 will essentially be the voltage SLP because P3 will be on, pulling the voltage on node C up to the voltage SLP on lead 24-2. This voltage is applied to the line 35 to produce the output signal BIT. The output signal BIT is used in a feedback loop to control the provision of external power from the external voltage source EV CL  to the SLP line 24-2. N type transistor N4 has its source connected to V BP , a voltage halfway between V DD  and V SS  and its drain connected to the line 35. The gate of N4 is driven by the signal EQ. When EQ goes low (see FIG. 2B), as it must to allow sense amp 23-1 (FIG. 2A) to be read out, N type transistor N4 is turned off thereby allowing line 35 to track the signal SLP. 
     The signal BIT is provided to the positive input lead of the differential amplifier shown in FIG. 4. The negative input lead of differential amplifier 41 is connected to the source of the reference signal IV CL . When the voltage SLP begins to rise, the signal BIT is approximately V BP , which is halfway between V DD , the external voltage supply to the chip and V SS , the reference voltage on chip. IV CL , the internal voltage of the chip, is typically at 3.3 volts. When V DD  is 5 volts, BIT will be approximately 2.5 volts when voltage SLP begins to rise. Accordingly op amp 41 produces a high level output signal which is applied to one input lead of the two input lead NAND gate 42. The other input lead to NAND gate 42 is driven by a sensing control signal. When the sensing control signal goes high, NAND gate 42 is enabled. Because the output signal of op amp 41 is high level when BIT is beneath IV CL , NAND gate 42 produces a low level output signal when the voltage SLP begins to rise. This low level output signal is applied to the gate of P type transistor P5 connected between the external voltage source EV CL  and the line SLP. Thus P type transistor P5 turns on and allows the external voltage source EV CL  to supply power to the line SLP. So long as the signal on bit line BIT remains beneath the signal IV CL , P type transistor P5 remains on. 
     The sensing control signal (which is high level when NAND gate 42 is enabled) is also inverted by invertor 43 and applied directly to P type transistor P6 connected between the internal, on-chip voltage source IV CL  and the SLP lead 24-2. The low level signal applied to the gate of P type transistor P6 turns on P type transistor P6 thereby allowing the internal voltage source IV CL  to apply power to the SLP lead 24-2. 
     So long as the voltage on lead Bit is beneath the voltage IV CL , the external voltage source EV CL  supplies power to P type transistor P5. When, however, the signal on line 35 (FIG. 3) reaches IV CL , the output signal from differential op amp 41 goes low thereby forcing the output signal from NAND gate 42 high. This shuts off P type transistor P5 and thereby disconnects the external voltage source supplying EV CL  from SLP line 24-2. The internal voltage supply IV CL  continues to supply whatever current is required to bring the charge on the SLP line 24-2 to a level such that the voltage on SLP line 24-2 corresponds to the voltage of the internal voltage supply IV CL . Note that the voltage on the SLP line ideally reaches IV CL  and will do so when EV CL  has been shut off as described above. Even if the sensing control signal remains high for a substantially longer period of time than transistor P5 remains on, the voltage on SLP line 24-2 will not exceed IV CL . 
     Thus this invention has provided a way of avoiding the drop in the voltage IV CL  produced by the internal power supply of the memory chip during the charging of the SLP line up to the voltage IV CL .