Abstract:
Various exemplary embodiments relate to an apparatus including: a first substrate including a planar dielectric layer on a semiconducting layer, and a silicon layer located directly on a planar surface of the dielectric layer, adjacent first and second segments of the silicon layer being optically end-coupled, the first segment being thicker than the second segment; and a second substrate including a III-V semiconductor layer segment on a top surface thereof, the first and second substrates being bonded together such that the III-V semiconductor layer segment is in direct contact with a portion of the first segment of the silicon layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application hereby incorporates by reference, in its entirety, “MONOLITHIC SILICON LASERS”, Attorney Docket No. 816123-US-PSP which is being concurrently filed on Jun. 26, 2014, by Po Dong. 
     
    
     TECHNICAL FIELD 
       [0002]    Various exemplary embodiments disclosed herein relate generally to hybrid semiconductor optical devices and lasers. 
       BACKGROUND 
       [0003]    Silicon based optical-electronic integration may offer low-cost solutions for optical communications and interconnects. Further, silicon may enable fabricating low-cost, compact circuits that integrate photonic and microelectronic elements. Silicon optical-electronic integration may address a wide range of applications from short distance data communication to long haul optical transmission. laser. Unfortunately, some devices may be difficult to make in integrated silicon-based chips. 
       SUMMARY 
       [0004]    A brief summary of various exemplary embodiments is presented below. Some simplifications and omissions may be made in the following summary, which is intended to highlight and introduce some aspects of the various exemplary embodiments, but not to limit the scope of the invention. Detailed descriptions of a preferred exemplary embodiment adequate to allow those of ordinary skill in the art to make and use the inventive concepts will follow in later sections. 
         [0005]    Various exemplary embodiments relate to an apparatus including: a first substrate including a planar dielectric layer on a semiconducting layer, and a silicon layer located directly on a planar surface of the dielectric layer, adjacent first and second segments of the silicon layer being optically end-coupled, the first segment being thicker than the second segment; and a second substrate including a III-V semiconductor layer segment on a top surface thereof, the first and second substrates being bonded together such that the III-V semiconductor layer segment is in direct contact with a portion of the first segment of the silicon layer. 
         [0006]    Various embodiments are described wherein the second segment of the silicon layer having a thickness that varies by less than 10 nanometers. 
         [0007]    Various embodiments are described further comprising a second dielectric layer located on the first dielectric layer and laterally surrounding the first segment, the second dielectric layer and the first segment having upper surfaces of the same height at interfaces therebetween. 
         [0008]    Various embodiments are described wherein substrate including a first silicon layer is a silicon on insulator (SOI) substrate. 
         [0009]    Various embodiments are described wherein the apparatus includes a laser whose optical gain medium includes, at least, part of the III-V semiconductor layer segment. 
         [0010]    Various embodiments are described wherein the apparatus includes an optical modulator or a photodetector including, at least, part of the III-V semiconductor layer segment. 
         [0011]    Various embodiments are described wherein the first segment has a lateral taper region at each end thereof. 
         [0012]    Various embodiments are described wherein the III-V semiconductor layer segment includes a lateral taper at each end thereof. 
         [0013]    Various embodiments are described wherein the first segment has third and fourth tapers overlapping the lateral tapers of the III-V layer segment. 
         [0014]    Various embodiments are described wherein the thickness of the first segment is greater than about 380 nm. 
         [0015]    Various embodiments are described wherein the thickness of the first segment is between about 380 nm and 420 nm. 
         [0016]    Various embodiments are described wherein the thickness of first segment is between about 100 nm to 350 nm. 
         [0017]    Various embodiments are described wherein the thickness of second segment is between about 200 nm to 240 nm. 
         [0018]    Further various exemplary embodiments relate to a method of manufacturing a hybrid optical semiconductor device, including: forming an opening in a first dielectric layer to expose a part of a first silicon layer segment, the first silicon layer segment being located on a planar surface of a second dielectric in a first substrate; forming a second silicon layer segment in the opening such that exposed surfaces of the second silicon layer segment and the second dielectric layer have about the same distance from the planar surface; and bonding a second substrate to the first substrate such that a III-V semiconductor layer segment of the second substrate is in direct contact with the exposed surface of the second silicon layer segment. 
         [0019]    Various embodiments are described further comprising polishing the first substrate to cause the exposed surfaces of the second silicon layer segment and the second dielectric layer to have a same distance from the planar surface. 
         [0020]    Various embodiments are described wherein the first substrate is a silicon on isolator (SOI) substrate. 
         [0021]    Various embodiments are described wherein the first silicon layer segment has a height over the planar surface that varies by less than 10 nanometers in regions within one micrometer of the second silicon layer segment. 
         [0022]    Various embodiments are described wherein the III-V semiconductor layer segment is a part of the optical gain medium of a laser. 
         [0023]    Various embodiments are described wherein III-V semiconductor layer segment is a part of one of an optical modulator and a photo-detector. 
         [0024]    Various embodiments are described wherein the second silicon layer segment has first and second taper regions at first and second ends thereof. 
         [0025]    Various embodiments are described wherein the III-V semiconductor layer segment includes a first laterally tapered segment at a first end thereof and second lateral taper segment at a second end thereof. 
         [0026]    Various embodiments are described wherein the second silicon layer segment has third and fourth lateral taper regions overlapping the first and second tapered segments of the III-V layer segment. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0027]    In order to better understand various exemplary embodiments, reference is made to the accompanying drawings, wherein: 
           [0028]      FIGS. 1 a -1 c    illustrate various structures formed while forming a device that integrates a III-V semiconductor layer with a silicon waveguide; 
           [0029]      FIGS. 2 a -2 c    illustrate structures formed by various steps of an embodiment of a method of forming the hybrid optical-electronic device; 
           [0030]      FIGS. 3 a - e    illustrate cross-sectional and top views of various structures formed by steps of an embodiment of a method of fabricating a hybrid optical-electronic device; 
           [0031]      FIG. 4  illustrates another embodiment of the hybrid optical-electronic device; and 
           [0032]      FIG. 5  illustrates another embodiment of the hybrid optical-electronic device. 
       
    
    
       [0033]    In the Figures, relative dimensions of some features may be exaggerated to more clearly show one or more of the structures being illustrated therein. To facilitate understanding, identical reference numerals have been used in the Figures and the text to designate elements having substantially the same or similar structure or substantially the same or similar function. 
         [0034]    Herein, various embodiments are described more fully by the Figures and the Detailed Description. Nevertheless, the inventions may be embodied in various forms and are not limited to the specific embodiments that are described in the Figures and Detailed Description. 
       DETAILED DESCRIPTION 
       [0035]    The description and drawings merely illustrate the principles of various ones of the inventions. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the inventions and are included within its scope. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the inventions and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Additionally, the term, “or,” as used herein, refers to a non-exclusive or (i.e., and/or), unless otherwise indicated (e.g., “or else” or “or in the alternative”). Also, the various embodiments described herein are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. As used herein, the terms “context” and “context object” will be understood to be synonymous, unless otherwise indicated. 
         [0036]    Silicon photonics is a technology, where optical components use silicon as an optical medium, e.g., using silicon-on-insulator (SOI) substrates. Silicon photonics may exploit methods, such as for example, complementary metal-oxide-semiconductor (CMOS) fabrication methods. These techniques may offer high yield and low cost photonic integrated circuits which may find applications from short reach interconnects to long-haul coherent optical transmission systems. Silicon photonics can monolithically integrate electro-optic modulators, photo-detectors, optical couplers, optical power splitters/combiners, optical filters, wavelength (de)multiplexing filters, arrayed waveguide gratings, micro rings, variable optical attenuators, variable optical couplers, polarization beam splitters/combiners, polarization rotators, etc. However, fabricating an efficient laser with silicon photonics has been difficult, because silicon is not an efficient light-emitting material. The fabrication if a laser on silicon is using wafer bonding a III-V semiconductor layer to a silicon-based substrate so that the III-V material provides the optical gain, and portions of the silicon provide parts of the laser cavity. In this so-called hybrid laser, the light is preferably efficiently coupled between III-V semiconductor and silicon layers. However, efficient light coupling between silicon waveguide cores and III-V gain layers typically requires a silicon thickness more than 400 nm, while the typical silicon thickness for silicon photonic integrated circuits are less, .e.g., around 220 nm. This thickness mismatch induces significant optical and/or physical coupling challenges. Some embodiments, which are described below, propose an integration structure between optical gain materials such as III-V semiconductors and silicon photonic circuits. 
         [0037]      FIGS. 1 a -1 c    a sequence of structures formed by a method for integrating a III-V semiconductor device layer with a substrate having one or more silicon waveguide core segments thereon.  FIGS. 1 a -1 c    are cross-sectional views along the length of the silicon waveguide core segments. It is noted that the gain III-V layer used to implement a laser may typically have an effective index of 3. Accordingly, to efficiently couple light between the top III-V layer and a bottom silicon waveguide segment, the silicon waveguide segment preferably should often have an effective index of around 3. Such an effective index matching may require that silicon waveguide segment have a thickness larger than about 400 nm. In many silicon photonic circuits, the silicon waveguides are much thinner, for example, often are about 220 nm thick. One way to solve this effective index matching problem is to increase the starting thickness of the silicon waveguide layer(s) to about 400 nm.  FIG. 1 a    illustrates an SOI substrate  100  with a silicon substrate  103 , a buried oxide (BOX) layer  105 , and a silicon layer  110  that is approximately 400 nm thick or greater. FIG. lb illustrates the silicon layer  110  after being etched down to a thickness of about 220 nm in the non-laser regions and region(s) of transition between laser and other circuits to form a thin waveguide region  125  leaving a thick waveguide region  115  that is about 400 nm thick.  FIG. 1 c    next illustrates a III-V laser  120  including a III-V waveguide layer bonded to the thick silicon waveguide region  115 . The laser radiation from the III-V waveguide layer  120  may now couple to the thick silicon waveguide region  115  first and then from the thick silicon waveguide region  115  to the thin silicon waveguide  125 . For efficient coupling, further tapers may at transitions between the different waveguide regions. Various horizontal or vertical taper structures may help avoid abrupt junction transitions in  FIG. 1 , which are not shown in this cross section. The etching method, however, can produce roughness on the top surface of thin silicon waveguide  125  as well as variations in the thickness of the thin silicon waveguide  125 . This roughness will increase optical losses in the thin silicon waveguide due to scattering at such rough surfaces.  FIGS. 2 a -2 c    illustrate structures formed at various steps of a method of forming a hybrid optical-electronic device according to an embodiment. Instead of etching down the thick silicon as shown in  FIGS. 1 a   - 1   c,  as shown in  FIG. 2   a,  the method starts with a silicon-on-insulator (SOI) wafer  200  with a silicon substrate  203 , a BOX layer  205 , and a thin silicon layer  210 , e.g., with a thickness of about 220 nm, or other thickness less than about 400 nm.  FIG. 2 b    illustrates a structure resulting from a selective deposition of silicon to form a thick waveguide segment  215 . The resulting thickness may be about 400 nm or greater to allow for efficient optical coupling with a III-V waveguide layer to be subsequently added.  FIG. 2 c    illustrates bonding of the III-V waveguide layer  220  to the top of the thick waveguide segment  215 . Transition tapers may be used between the various transition segments of the optical waveguides For example, such transition tapers may assist the coupling between III-V waveguide layer  220  and thick silicon waveguide segment  215  and also may assists the optical coupling between the thick silicon waveguide segment  215  and thin silicon waveguide segments  225 . 
         [0038]      FIGS. 3 a - e    illustrate cross-sectional and top views structures formed at various steps of an embodiment of a method of fabricating a hybrid optical-electronic device. The method may begin with a SOI with a thin top silicon layer on a BOX layer  305  and silicon substrate  303 . Portions of the thin top silicon layer may be etched leaving a silicon layer that will form segments of a silicon waveguide  310  after fabrication is complete. Additionally, photonic circuits may be also fabricated in other lateral portions of the thin top silicon layer that connect with the silicon waveguide  310 . The silicon waveguide  310  may be any type of waveguide including a ridge or channel waveguide. The photonic circuits may include optical devices as described above. Further electrical circuits may also be integrated into other lateral portions of the thin top silicon layer of the SOI. While this embodiment uses an SOI substrate, other types of silicon substrates may be used as well. The optical and/or electric devices formed in, on, and/or from the thin top silicon layer of the SOI may be manufactured using typical semiconductor manufacturing processes, such as for example CMOS processes. The thin top silicon layer may be, e.g., about 220 nm thick, or may have, e.g., a thickness in the range of about 100 nm to 350 nm. 
         [0039]      FIG. 3 b    illustrates an intermediate structure formed by a step of the method. The structure includes an insulator or dielectric layer such as a silicon oxide layer  335 . The insulator or dielectric layer may be made of another dielectric, for example other types of oxides, silicon nitride, or other optical cladding material. The silicon oxide layer  335  may be deposited over and around the silicon waveguide  310 . This silicon oxide layer  335  may be of the same or a different material as the BOX layer  305 . Again, this layer may be formed and processed using standard semiconductor manufacturing processes. 
         [0040]      FIG. 3 c    illustrates an intermediate structure formed by a step of the method which includes forming an opening  330  in the oxide layer  335 . This step may include etching the oxide layer using typical semiconductor manufacturing processes. This opening  330  may be further used as a mask to control the formation of an additional silicon layer at a subsequent step. The opening  330  may include taper structures as shown to allow for improved coupling of light between the different waveguide structures. 
         [0041]      FIG. 3 d    illustrates the intermediate structure produced by a step of the method that includes forming an additional silicon layer  315  in the opening  330 . This additional silicon layer  315  may be formed, e.g., by epitaxial growth of silicon inside the opening  330  or, e.g., by deposition of polysilicon or amorphous silicon by standard deposition techniques such as plasma-enhanced chemical vapor deposition (PECVD). This step may include performing any known silicon deposition method for producing a layer of silicon. The formation of this silicon layer  315  may also result in silicon deposited on the oxide layer  335 . Then, this step of the method may include, e.g., polishing the added silicon layer  315  and the oxide layer  335 , for example, using chemical-mechanical polishing (CMP). This polishing may result, e.g., in the grown silicon only residing inside the opening  330 . This step of the method typically provides a smooth top surface on the additional silicon layer  315  which reduces the loss of light passing this additional silicon layer  315  as well as improving the physical and optical coupling characteristics with the III-V waveguide by providing a flat surface. This may result in a polished surface e.g., with a substantially continuous joint upper surface including the upper surface of the additional silicon layer  315  and the upper surface of the oxide layer  335 . This polished surface may result in a thickness of the polished layers that varies less than about 10 nanometers. It is noted that these techniques could also be applied to substrates with some curvature, where the various layers would conform to the desired curvature. The thickness of the additional layer may be, e.g., about 180 nm resulting in a total thickness of about 400 nm. The total thicknesses may be, e.g., greater than about 380 nm or may be, e.g., between about 380 nm and about 420 nm. This additional layer  315  along with its underlying silicon layer will form a thick silicon waveguide in the final structure that facilitates the transmission of light from a III-V layer to the final thin silicon waveguide  325 . The thin silicon waveguide  325  is the portion of the silicon waveguide  310  that extends out from under the additional silicon layer  315 . 
         [0042]      FIG. 3 e    illustrates the structure resulting for the step of bonding a chip having the III-V semiconductor layer  320 , to the top surface of the structure formed in the previous step of the method, for example, to produce a hybrid laser cavity. The bonding step may use any conventional method for bonding portions of the surfaces of  2  chips together. The bonding step may position the III-V semiconductor layer  320  in direct and fixed contact with the silicon layer of the other chip. 
         [0043]    In  FIG. 3 e    four taper regions are shown of the lateral layout of an exemplary structure that may be produced by the bonding step. Taper  1  region shows a width taper in the additional silicon layer  315  that couples light between thin silicon waveguide and thick silicon waveguide. The taper  2  region, which may include both tapers on thick silicon waveguide and the III-V waveguide, may also couple light between thick silicon waveguide and the III-V waveguide. The taper  3  region may couple light between the III-V waveguide and the thick silicon waveguide, while the taper  4  region couples light between the thick silicon waveguide and the thin silicon waveguide. 
         [0044]      FIG. 4  illustrates another embodiment of the hybrid optical-electronic device. The hybrid optical-electronic device  400  is similar to the device  300  of  FIGS. 3 a -3 e    except for a difference in additional layer  315 . In the device of  FIG. 4 , the additional layer  315  in device  400  does not extend between the Taper regions  2  and  3 . Instead the tapers in the additional layer  315  that overlap the tapers of the III-V waveguide come to stops. Each stop is shown as a flat tip on the taper. 
         [0045]      FIG. 5  illustrates another embodiment of the hybrid optical-electronic device. The hybrid optical-electronic device  500  is similar to the device  300  of  FIGS. 3 a -3 e    except for a difference in additional layer  315 . The additional layer  315  in device  400  does not have tapers like the tapers in regions  2  and  3  of the device  300 . Instead the additional layer  315  maintains its width as it extends between the Taper regions at the end of the additional layer  315 . 
         [0046]    The various tapers illustrated in the different embodiments provide examples of the type of taper geometries that may be used. The tapers may come to a pointed, rounded or other shaped tip rather than a flat tip as shown. Further, the sides of the taper are shown as straight lines, but may be other shapes that result in the tapering of the width. Also, there may be tapers in the thickness of the waveguides that are coupled to one another. Manufacturing such a taper is more complex than tapering the width of the waveguides, but it may be done if needed to address certain coupling or other requirements. 
         [0047]    In the examples above the III-V semiconductor device is described as a laser. There are other types of devices that may be beneficially implemented using III-V semiconductor materials. Examples include modulators, photo-detectors, etc. Various combinations of III-V materials may be used for the III-V semiconductor device including for example, GaAs, InP, InGaAs, etc. Also various types of optical devices may be implemented in the silicon layer including, for example, electro-optic modulators, optical amplifiers, photo-detectors, optical couplers, optical power splitters/combiners, optical filters, wavelength (de)multiplexing filters, arrayed waveguide gratings, micro rings, variable optical attenuators, variable optical couplers, polarization beam splitters/combiners, polarization rotators, etc. 
         [0048]    It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the invention. 
         [0049]    Although the various exemplary embodiments have been described in detail with particular reference to certain exemplary aspects thereof, it should be understood that the invention is capable of other embodiments and its details are capable of modifications in various obvious respects. As is readily apparent to those skilled in the art, variations and modifications can be effected while remaining within the spirit and scope of the invention. Accordingly, the foregoing disclosure, description, and figures are for illustrative purposes only and do not in any way limit the invention, which is defined only by the claims.