Abstract:
Methods and systems for converting analog signals to digital signal using a cyclic analog-to-digital converter are disclosed. For example, such a cyclic analog-to-digital converter may include digitization circuitry configured to digitize either an input signal or an amplified feedback residue signal to produce first digital signals, digital accumulator circuitry configured to produce N-bits of digital information based on the first digital signals over N consecutive cycles, where N is a positive integer, and a residue amplifier configured to amplify a residue signal to produce the amplified feedback residue signal, wherein for at least M cycles, the residue amplifier operates using a capacitor averaging technique, where M is a positive integer and less than N, and wherein for P cycles the residue amplifier operates using a simple gain amplification technique, where P is a positive integer and less than N.

Description:
INCORPORATION BY REFERENCE 
     This application claims the benefit of U.S. Provisional Application No. 61/238,895, “An Improved Cyclic ADC Design Technique” filed on Sep. 1, 2009, which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of tiling, are neither expressly nor impliedly admitted as prior art against the present disclosure. 
     Analog-to-Digital Converters (ADCs) are electronic devices that have become a fundamental building block in everything from power supplies to cell phones. One of the challenges to designing ADCs is to assure that their performance meets design requirements, such as conversion speed and accuracy, while being made as inexpensively as possible. One particular type of known ADC is called a pipelined ADC, which uses a series of pipelined stages to digitize signals, for instance, one bit at a time. A variant of the pipelined ADC is known as the cyclic ADC, which applies the general concept of digitizing signals one bit at a time, but uses a single conversion stage with feedback so as to emulate a pipeline. While the cyclic approach takes far longer to convert signals than a pipelined ADC for the same number of bits, there is a proportionate saving in hardware. For example, while a 12-bit cyclic ADC may take twelve times longer to convert a given signal than a 12-bit pipelined converter, the cyclic ADC may use only one-twelfth of the conversion cells required by the pipelined ADC. Unfortunately, both cyclic and pipelined converters are subject to manufacturing constraints, and component mismatch caused by real world manufacturing limitations may cause substantial conversion errors. Accordingly, new technology for compensating for such manufacturing limitations may be desirable. 
     SUMMARY 
     Various aspects and embodiments of the invention are described in further detail below. 
     In an embodiment, a cyclic analog-to-digital converter includes a digitizer circuitry configured to digitize either an input signal or an amplified feedback residue signal to produce first digital signals, an accumulator configured to produce N-bits of digital information based on the first digital signals over N consecutive cycles, where N is a positive integer, and a residue amplifier configured to amplify a residue signal to produce the amplified feedback residue signal, wherein for at least M cycles, the residue amplifier operates using a capacitor averaging technique, where M is a positive integer and less than N, and wherein for P cycles the residue amplifier operates using a simple gain amplification technique, where P is a positive integer and less than N. 
     In another embodiment, a method for performing analog-to-digital conversion, includes digitizing either an input signal or an amplified feedback residue signal to produce first digital signals, producing N-bits of digital information based on the first digital signals over N consecutive cycles, where N is a positive integer, and amplifying a residue signal to produce the amplified feedback residue signal, wherein for at least M cycles, the step of amplifying may be done using a capacitor averaging technique, where M is a positive integer and less than N, and wherein for P cycles, the step of amplifying may be done using a simple gain amplification technique, where P is a positive integer and less than N. 
     In yet another embodiment, a cyclic analog-to-digital converter includes a means for digitizing either an input signal or an amplified feedback residue signal to produce first digital signals, a means for producing N-bits of digital information based on the first digital signals over N consecutive cycles, where N is a positive integer, and a means for amplifying a residue signal to produce the amplified feedback residue signal, wherein for at least M cycles, the means for amplifying uses a capacitor averaging technique, where M is a positive integer and less than N, and wherein for P cycles, the means for amplifying uses a gain amplification technique, where P is a positive integer and less than N. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various embodiments of this disclosure that are proposed as examples will be described in detail with reference to the following figures, wherein like numerals reference like elements, and wherein: 
         FIG. 1  depicts an exemplary system using an analog-to-digital converter (ADC). 
         FIG. 2  depicts details of the exemplary ADC of  FIG. 1 . 
         FIGS. 3A and 3B  depict details of the exemplary residue amplifier of  FIG. 2 , 
         FIG. 4  illustrates the gain transfer function for the operational amplifier depicted in  FIGS. 3A and 3B . 
         FIG. 5  is a flowchart outlining an exemplary operation of the disclosed methods and systems. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     The disclosed methods and systems below may be described generally, as well as in terms of specific examples and/or specific embodiments. For instances where references are made to detailed examples and/or embodiments, it should be appreciated that any of the underlying principles described are not to be limited to a single embodiment, but may be expanded for use with any of the other methods and systems described herein as will be understood by one of ordinary skill in the art unless otherwise stated specifically. 
       FIG. 1  depicts an exemplary system  100  using an analog-to-digital converter (ADC). As shown in  FIG. 1 , the system  100  includes an analog signal source  110 , an ADC  120  and a digital sink  130 . In operation, the analog signal source  110  may transmit an analog signal to the ADC  120 . In turn, the ADC  120  may convert the analog signal into a stream of digital signals representing the information of the analog signal, and provide the digital signals to the digital sink  130 . 
     The exemplary analog signal source  110  may be any one of a number of different sources such as an electronic data transmitter, a node in a power supply or other electronic system, a signal derived from an optical transducer or by some other form of transducer, or any other known or later developed device suitable for providing an analog signal. The exemplary digital sink  130 , accordingly, may be any one of a number of different devices suitable to receive, monitor or otherwise process digital signals derived from analog information as may be recognized by those skilled in the art. 
       FIG. 2  depicts details of the exemplary ADC  120  of  FIG. 1 , which is but one possible non-limiting embodiment of a cyclic ADC. As shown in  FIG. 2 , the exemplary ADC  120  includes a switch  210 , a comparator/digitizer  212 , an accumulator  214 , a digital-to-analog converter (DAC)  216 , a summing junction  218 , a residue amplifier  220 , a sample/hold device (S/H)  222 , and a timing controller  224 . 
     In operation and under control of the timing controller  224 , the switch  210  may be set to allow an analog input signal x(t) to pass to the comparator/digitizer  212 . In turn, the comparator/digitizer  212  may perform a 1-bit digitization process on the input signal x(t) to provide a digital signal to the accumulator  214 . Upon receiving the digital signal from the comparator/digitizer  212 , the accumulator  214 , under control of the timing controller  224 , may determine a most significant bit (MSB) of N-bits of digital information that the ADC  120  provides to some external device. For example, if the cyclic ADC  120  of  FIG. 2  is a 12-bit device (N=12), the accumulator  214  at this point may determine the top MSB leaving the remaining eleven bits for later determination in later conversion cycles. 
     The output of the accumulator  214  then may be provided to the DAC  216 , which may produce an analog signal to the summing junction  218 . In turn, the summing junction  218  may subtract the signal provided by the DAC  216  from the signal presented to the comparator/digitizer  212  to produce a residue signal r(t) that is then provided to the input of the residue amplifier  220 . 
     Upon receiving the residue signal r(t), the residue amplifier  220  may amplify the residue signal r(t) by two times, and provide the amplified residue signal to the S/H  222 . The S/H  222  (which may alternatively be a track/hold (T/H) or similar signal holding circuit) may then capture the amplified residue signal upon command from the timing controller  224 . 
     Once the amplified residue signal is captured by the S/H  222 , the timing controller  224  may then cause the switch  210  to change position so as to feed the captured amplified residue signal to the input of the comparator/digitizer  212 . The comparator/digitizer  212 , accumulator  214 , DAC  216 , summing junction  218 , residue amplifier  220  and S/H  222  may then cyclically repeat the above described process to produce even finer digital resolution with each cycle in a manner well understood by those skilled in the relevant arts based upon the disclosure and teachings provided herein. 
     Note that while the general principles of cyclic ADCs are well known, the exemplary ADC  120  may use a modified process in the residue amplifier  220  to improve performance in view of certain practical manufacturing limitations known in wafer processing. In particular, it is known that individual analog components made in wafer processing, such as resistors and capacitors, may have variances from component to component. While such variances may typically be kept to 1%, such differences nonetheless may have substantial detrimental effects on devices such as cyclic ADCs. 
     In order to compensate for such component variance or mismatch, a technique known as “capacitor averaging” may be used where the roles of two components may be exchanged during two different phases of a given conversion cycle. The benefit of capacitor averaging is that it may alleviate a need to perform extra wafer processing steps, such as laser trimming of capacitors, at the expense of some increased conversion time of a resultant ADC. 
     For the present disclosure, it is to be appreciated that the technique of capacitor averaging may be applied to the residue amplifier  220 .  FIGS. 3A and 3B  depict details of a capacitor averaging technique that may be used by the exemplary residue amplifier  220  of  FIG. 2  for a given conversion cycle. As shown in  FIG. 3A , a first configuration for a first capacitor averaging phase (Φ 1 ) is depicted where an operational amplifier AMP employs a first capacitor C 1  acting as an input capacitor, and a second capacitor C 2  acting as a feedback capacitor. The gain for this configuration may be described as G=−(C 1 /C 2 ), and the transfer function of the configuration may be described as V K(Φ1) =−(C 1 /C 2 )r(t). The output voltage V K(Φ1)  may be captured on capacitor C 3A  by virtue of the settings of switches S 3A  and S 3B . 
     Continuing to  FIG. 3B , a second configuration for a second capacitor averaging phase (Φ 2 ) is depicted where the same operational amplifier AMP and capacitors C 1  and C 2  are employed, but in this phase the rolls of the capacitors C 1  and C 2  are exchanged by virtue of a switching network (not shown) so that the second capacitor C 2  acts as an input capacitor, and the first capacitor C 1  acts as a feedback capacitor. The gain for this configuration may be described as G=−(C 2 /C 1 ), and the transfer function of the configuration may be described as V K2(Φ2) =−(C 2 /C 1 )r(t). The output voltage V K(Φ2)  may be captured on capacitor C 3B  by virtue of the settings of switches S 3A  and S 3B . 
     Once the respective voltages for phases Φ 1  and Φ 2  are captured on capacitors C 3A  and C 3B , such voltages may be averaged to mitigate the errors, passively by placing the capacitors in parallel for example, or by using any number of active techniques. Further details and examples of capacitor averaging techniques may be found in “A 14 bit, 12MSW/s CMOS Pipeline ADC with over 100-dB SFDR” by Yun Chiu et al.,  IEEE J. Solid State Circuits , vol. 39, pp. 2139-2151, (December 2004), the content of which is incorporated by reference in its entirety. 
       FIG. 4  illustrates the gain transfer function for the operational amplifier AMP depicted in  FIGS. 3A and 3B . As shown in  FIG. 4 , during the first gain stage (Φ 1 ), capacitor C 1  is assumed to be greater than C 2 , and the output of amplifier AMP (V K ) rises to a level Δ1 above the ideal case (C 1 =C 2 ), while during the second gain stage (Φ 2 ), the output of amplifier AMP (V K ) dips to a level Δ2 below the ideal case. As the magnitudes of Δ1 and Δ2 may be assumed to be very close, it may be apparent that, by combining the information developed during the two phases Φ 1  and Φ 2 , error due to component mismatch may be effectively alleviated as compared to the case of “simple amplification”, where the roles of capacitors C 1  and C 2  remain static, e.g., capacitor C 1  is used solely as an input capacitor and capacitor C 2  is used as a feedback capacitor. 
     Returning to  FIG. 2 , while it may be appreciated that capacitor averaging may improve device performance of the residue amplifier  220 , it may be also appreciated that capacitor averaging need not be employed for every one of the N conversion cycles of the ADC  120 . That is, it may be beneficial to employ capacitor averaging in the residue amplifier  220  for conversion cycles determining high-order bits, while using a simple gain amplification in the residue amplifier  220  for the latter cycles that determine the least significant bits (LSBs). For example, in various embodiments where 12-bit conversion (N=12) is desired, it may be desirable to employ capacitor averaging in all conversion cycles except those cycles used for the last four to eight LSBs. For example, the inventors of the disclosed methods and systems have determined (by rigorous analysis and simulation) that a 12-bit cyclic ADC may be fabricated with 1% component mismatch that maintains target performance when the first six conversion cycles employ capacitor averaging amplification in a residue amplifier while the remaining six conversion cycles employ simple amplification. For example, assuming that a semiconductor manufacturing facility can produce cyclic ADCs having capacitors with matching tolerances of about 1%, a 12-bit fully functional (e.g., almost no missing codes and no non-monotonicities) cyclic ADC may be designed and manufactured that uses capacitor averaging for the first six conversion cycles that determine MSBs, and simple gain for the last six cycles. Of course, depending on other circumstances, such as the acceptance of some missing codes and non-linearities, the number of simple amplification cycles may vary, e.g., from four to eight cycles. 
       FIG. 5  is a flowchart outlining an exemplary operation of the disclosed methods and systems for performing cyclic ADC conversion. While the below-described steps are described as occurring in a particular sequence for convenience, it is to be appreciated by those skilled in the art that the order of various steps may be changed from embodiment to embodiment. It is further to be appreciated that various steps may occur simultaneously or be made to occur in an overlapping fashion. 
     The process starts in step S 502  where an analog signal of interest may be sampled. Next, in step S 504  the sampled signal of step S 502  may be digitized to produce a digitized signal. Then, in step S 506  an accumulated number may be adjusted to reflect the digitized signal of step S 504 . Control continues to step S 510 . 
     In step S 510 , a determination may be made as to whether to continue the cyclic conversion process, i.e., enough bits of resolution have been determined. If the digitization process is to continue, control continues to step S 512 ; otherwise, control jumps to step S 550  where the process stops. 
     In step S 512 , an analog reference signal may be produced from the accumulated number of step S 506 . Next, in step S 514 , a residue signal may be produced by subtracting the reference signal of step S 512  from the signal used in the digitization process of step S 504  (and later for the digitization process of step S 528  below). Then, in step S 520 , a determination may be made as to whether capacitor averaging is to be used to amplify the residue signal. As discussed above, for N-bits of conversion it may be advantageous to use capacitor averaging for first conversion cycles that produce the most significant bits (MSBs), while using simple amplification for the later conversion cycles that determine the LSBs, as such an approach may appropriately compensate for capacitor mismatch while keeping total conversion time to a minimum. If capacitor averaging is to be employed, control continues to step S 524 ; otherwise, control continues to step S 522 . 
     In step S 522 , a simple gain technique may be performed on the residue signal of step S 514  to produce an amplified residue signal, and control continues to step S 526 . 
     In contrast to step S 522 , in step S 524  a capacitor averaging technique may be performed on the residue signal of step S 514  to produce an amplified residue signal, and control continues to step S 526 . 
     In step S 526  a sample/hold (or alternatively track/hold) operation may be performed on the amplified residue signal, and in step S 528  the sampled signal of step S 526  may be digitized to produce a digitized signal. Control then jumps back to step S 506 , where the cyclic conversion process may continue for a total of N steps noting that the MSBs of the conversion process may be developed using the capacitor averaging gain technique of step S 524  while the LSBs may developed using simple gain technique of step S 522 . 
     While the invention has been described in conjunction with the specific embodiments thereof that are proposed as examples, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, embodiments of the invention as set forth herein are intended to be illustrative, not limiting. There are changes that may be made without departing from the scope of the invention.