Abstract:
A high-speed, solid-state, electronic circuit for alternately coupling two separate video signal paths to a third video signal path in response to high frequency square wave excitation, the circuit utilizing two dual-gate metal oxide semiconductor field effect transistors having oppositely phased signals applied to respective switching gates for cancellation of switching transient signals.

Description:
FIELD OF THE INVENTION 
     This invention relates to a high-speed, solid-state, electronic video switching circuit responsive to high-frequency, square-wave switching signals. More particularly, the circuit of this invention relates to a high-speed switch for alternately connecting two separate video signal paths to a third video signal path in a manner which minimizes coupling of switching signal energy into said video paths. 
     BACKGROUND OF THE INVENTION 
     The development of time domain filtering techniques for television receiver circuits as well as the development of circuitry for simultaneous display on separate parts of the screen of parts of signals received from two television broadcast stations has created a requirement for an inexpensive video-signal switch capable of alternately connecting two separate video signal paths to a third video signal path at horizontal sweep frequency rates or multiples thereof. Necessarily, the switching at the required high frequency must be done electronically rather than mechanically. However, electronic switching at rapid rates generally requires use of semiconductor components having either junction or field effect phenomena for alternately transmitting and blocking high frequency signal passage and the use in switching circuits of such semiconductor components with junction phenomena generally results in some direct coupling of the switching signal energy into the signal path as the semiconductor junction is alternately forward biased and reverse biased. Additionally, the switching time of such devices is limited by the time required to inject and remove majority carriers into and out of the junction regions. 
     On the other hand, the use in switching circuits of semiconductor components with field effect phenomena results in capacitive-type coupling of the switching signal energy into the video signal paths because of the nature of the injection and removal of minority carriers into and out of the changing geometry of the non-conducting regions within such devices. Therefore, the frequency of switching of such devices is not limited by time required for injection and removal of majority carriers in circuits using junction devices. While use of field effect devices has resulted in faster switching rates, a problem heretofore existing has concerned minimization of the effect of the capacitive-type coupling while utilizing such devices. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention a video switch circuit provides alternate connection of two separate video signal paths to a third video signal path using a pair of dual-gate metal oxide semiconductor field effect transistors, (MOS-FETs). Oppositely phased switching signals are transmitted to the two MOS-FET devices, each of the devices is coupled to a separate video signal path and each of the devices is connected to a common third video signal path. As a result, the switching signal energy injected into the video signal output through one of the MOS-FET devices is substantially canceled by switching signal energy removed from the video signal output through the other MOS-FET device. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a preferred embodiment of the video switch of the present invention. 
     FIG. 2 is a graphic illustration of the switching characteristics of the gate elements of the switch circuit of the present invention. 
     FIG. 3 is a time domain representation of example video and switching signals illustrating the manner of operation of the video switch of this invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the embodiment indicated in FIG. 1 the video switch circuit has input terminals 10 and 11 for receiving a video signal from two separate sources (not shown). The video signals may be comprised of television broadcast signals processed by a television tuner-detector to frequencies ranging from 30Hz to 4.5 MHz. The output of the video switch circuit is indicated by the reference terminal 12 and may be applied to the video processing and driving circuits of a television receiver. Inputs 10 and 11 and output 12 are referenced with respect to ground. 
     First and second video signal paths V 1  and V 2  are A.C. coupled to first terminals of the source-drain paths of dual-gate metal oxide semiconductor field effect transistors (MOS-FETs) Q 1  and Q 2 , respectively, through optional buffer amplifiers 13 and 14. Second terminals of the source-drain paths of MOS-FETs Q 1  and Q 2  are shown D.C. coupled to each other and A.C. coupled to optional output buffer amplifier 15. Optional output amplifier 15 is coupled to third video path V O . The first terminals of the source-drain paths of Q 1  and Q 2  may be either the source connections or the drain connections of the device, with the opposite connections used for the second terminals. 
     Switching signal V S1  is D.C. coupled to the first of the two gate terminals of MOS-FET Q 1  through optional protective resistor 16. An oppositely phased switching signal V S2  is D.C. coupled to the first of the two gate terminals of MOS-FET Q 2  through optional protective resistor 17. Switching signal phase inversion means 18 may be used to convert switching signal V S1  to oppositely phased switching signal V S2 . 
     The term switching signal as used herein is defined to mean a time-varying substantially square wave voltage which is applied to a first gate of either of said MOS-FET devices and which has a lower voltage level V L  such that, with reference to the voltage level of the source-drain path of the device, level V L  is of sufficient magnitude to cause the said source-drain path to become essentially non-conductive. Similarly, the switching signal has a higher voltage level V H  which in reference to said source-drain voltage is sufficient to cause said source-drain path to become highly conductive. The magnitudes of V H  and V L  must, of course, be sufficient to hold the source-drain path substantially conductive or non-conductive as the voltage of said path varies according to the applied video signal voltage. 
     Switching signals V S1  and V S2  may be comprised of square-wave voltage as illustrated in FIG. 3 and may vary between a higher voltage level V H  and a lower voltage level V L . To minimize switching time required by MOS-FETs Q 1  and Q 2  the characteristics of those devices should be such that maximum impedance change occurs in the source-drain path for minimum change in level of switching signal. A family of curves such as that illustrated in FIG. 2 may be obtained for various fixed values of voltage V A  applied by D.C. voltage potential means 19 to the second gate terminals of dual-gate MOS-FETs Q 1  and Q 2 . For example, using a pair of commonly available 3N201 MOS-FETs for Q 1  and Q 2 , the curves illustrated in FIG. 2 illustrate switching conditions with a bias voltage V A  equal to approximately 14 volts and a drain-source voltage of approximately 10 volts, all voltages referenced to a common ground. The particular curves indicate that the switching voltages V S1  and V S2  may alternate between a lower voltage level V L  equal to 8 volts and a higher voltage level V H  equal to 12 volts. The foregoing switching signal levels were experimentally determined to be of sufficient amplitude for switching signals having a 200 milli-volt peak-to-peak amplitude. 
     The term bias voltage as used herein is defined to mean a voltage V A  applied to the second gate of said MOS-FET devices which voltage as measured with respect to the voltages of the source-drain paths and the switching signal is of value which substantially optimizes switching time. 
     The operation of the circuit is illustrated by FIG. 3 in which V 1  and V 2  are straight-line representations which in each case may be a horizontal line or part of a horizontal line of a video signal. Switching voltages V S1  and V S2  are indicated in FIG. 3 as oppositely phased square-wave voltages varying between the values V H  and V L  as described above. The graph illustrated as V O1  is representative of the output of MOS-FET Q 1  as it might be if the first gate of Q 2  was biased continuously at V H  rather than switched with signal V S1 . Similarly, the graph illustrated as V O2  is representative of the output of MOS-FET Q 2  with the first gate MOS-FET Q 1  biased continuously at V H  rather than switched with signal V S2 . The decaying exponential components of the waveforms of curves V O1  and V O2  represent switching signal energy coupled into the video path by the time varying capacitive nature of the geometry between the signal-drain path and the depletion region of the MOS-FET devices. It is noted that the exponential components of waveforms and the time constants of FIG. 3 are illustrations rendered for the purpose of using superposition theory to explain the principles of operation of the video signal switch. The true waveforms vary from those illustrated. Accordingly, the final output of the switch is illustrated as V O  and is the sum of V O1  and V O2 . The illustrated waveforms indicate that the switching signal energy coupled to the video signal paths as exemplified by exponential components of waveforms of V O1  and V O2  is canceled from the resulting output voltage V O . 
     Thus, in the video switch of this invention, equal amplitude signals V S1  and V S2  of opposite phase are applied to substantially identical MOS-FET devices Q 1  and Q 2 , resulting in substantially equal but opposite instantaneous switching signal energy transmission into and out of the video signal path. Therefore, the transmitted switching signal impulses from V S1  and V S2  are substantially canceled from the output V O . 
     Obviously, the difference between D.C. voltage levels applied to source and drain terminals and gate terminals of MOS-FET devices is critical. However, the applied voltages may all be measured from a different reference level which may depend upon the driving or the output circuits used. In the embodiment illustrated, the source-drain terminals have a D.C. voltage of approximately 10 volts established by the emitter-follower buffer amplifiers. The second gate terminal voltage value of 14 volts and the switching signal voltage levels of 8 and 12 volts were established after arbitrarily choosing the source-drain voltage value. A lower source-drain voltage would, of course, require design using correspondingly lower gate-terminal voltages. 
     Signal phase inversion means 18 may be comprised of three-terminal transistor Q 3  with switching signal V S1  coupled directly to the base terminal. Collector resistor 20 is coupled between the collector terminal of Q 3  and a potential source of value equal to at least the sum of twice V H  because of transistor biasing limitation. Emitter resistor 21 is coupled between the emitter terminal of Q 3  and zero voltage reference level, usually ground. For example, if resistors 20 and 21 are both chosen to be 1000 ohms and if the potential source is chosen to be 24 volts, the collector voltage will alternate between values of 16 and 12 volts as the switching voltage V S1   alternates between values of 8 and 12 volts. Zener diode 22 in series with zener conduction resistor 23 may be used to lower the switching output voltage by the value of the potential source less V H  + V L  or, for example, to lower the voltage from the 16 and 12 volt levels to the desired 12 and 8 volt levels. The cathode terminal of Zener diode 22 is connected to the collector terminal of Q 3  and the anode terminal is connected to one terminal of resistor 23, and the other terminal of resistor 23 is connected to ground potential. The junction of Zener diode 22 and resistor 23 is coupled to the first gate of Q 2  through optional protective resistor 17. 
     Buffer amplifiers 12, 13 and 14 are indicated in FIG. 1 as commonly used emitter follower circuits. The collector-base bias resistor may, for example, be approximately 14,000 ohms and the base-ground bias resistor approximately 9,000 ohms when used with a standard transistor, a 2,000 ohm emitter resistor and a 24 volt power supply. Certain bias resistors of amplifiers 13 and 14 are indicated as being variable to provide equalization or optimization of the D.C. voltage applied to the source-drain terminals of Q 3  and Q 4 . 
     Voltage potential means 19 may be comprised of the series combination comprising resistor 24a and a tapped resistor or trimming means 24b connected between a potential source and ground. The tapped voltage V A  may be applied to the second gate terminals of Q 1  and Q 2  through resistors 25 and 26 and may be adjusted to partially close the source-drain path, thereby decreasing switching time and required energy. Signal transmission between second terminals of Q 1  and Q 2  may be prevented by use of shunt capacitors 27 and 28. 
     While there has been described what is at present considered to be the preferred embodiment of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention as defined by the appended claims.