Abstract:
An improved photovoltaic device and methods of manufacturing the same that includes an interface layer adjacent to a semiconductor absorber layer, where the interface layer includes a material in the semiconductor layer which decreases in concentration from the side of the interface layer contacting the absorber layer to an opposite side of the interface layer.

Description:
CLAIM FOR PRIORITY 
       [0001]    This application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application Ser. No. 61/547,924 filed on Oct. 17, 2011, which is hereby incorporated by reference in its entirety. 
     
    
     TECHNICAL FIELD 
       [0002]    The present invention relates to photovoltaic devices and methods of manufacturing the same. 
       BACKGROUND 
       [0003]    Thin film photovoltaic devices can include semiconductor material deposited over a substrate, for example, with a first semiconductor layer serving as a window layer and a second semiconductor layer serving as an absorber layer. The semiconductor window layer, for example, a cadmium sulfide layer, can allow the penetration of solar radiation to the absorber layer, for example, a cadmium telluride layer, for conversion of solar energy to electricity. 
         [0004]    During conversion of solar energy to electricity in the photovoltaic device, some minority electron carriers penetrate through the absorber layer to a back contact adjacent to the semiconductor layer where they combine with hole carriers, causing power dissipation inside the device, thereby reducing power conversion efficiency. To eliminate power dissipation, an additional semiconductor layer may be deposited between the semiconductor absorber layer and the back contact layer as a barrier or reflector against minority electron carrier diffusion. The reflector layer is made of a semiconductor material with electron affinity lower than that of the absorber layer, which forces electron carrier flow back toward the electron absorber layer, minimizing recombination at the back contact. 
         [0005]    Although the reflector layer should reduce power dissipation and increase power conversion efficiency, lattice mismatch between the reflector layer and the absorber layer can partially negate this benefit. Semiconductor materials contain a lattice, or a periodic arrangement of atoms specific to a given material. Lattice mismatching refers to a situation wherein two materials featuring different lattice constants (a parameter defining the unit cell of a crystal lattice, that is, the length of an edge of the cell or an angle between edges) are brought together by deposition of one material on top of another. In general, lattice mismatch can cause misorientation of film growth, film cracking, and creation of point defects. In typical photovoltaic devices, lattice mismatching can occur, for example, between the semiconductor absorber layer and the semiconductor reflector layer. Lattice mismatch between the semiconductor absorber layer and the semiconductor reflector reduces desired electron reflection. Power dissipation within the photovoltaic device continues, thereby negating the desired benefits of the reflector layer and reducing power conversion efficiency. 
         [0006]    An improved photovoltaic device and method for manufacturing the same that mitigates against lattice mismatching between the semiconductor absorber layer and the semiconductor reflector layer is desirable. 
     
    
     
       DESCRIPTION OF DRAWINGS 
         [0007]      FIG. 1  is a schematic of a photovoltaic device having multiple layers; 
           [0008]      FIG. 2  is a schematic of a photovoltaic device having multiple layers; 
           [0009]      FIG. 3  is a schematic of a photovoltaic device having multiple layers; 
           [0010]      FIG. 4  is a schematic of a multilayered structure having multiple conductive layers; 
           [0011]      FIGS. 5   a - 5   b  illustrate mole-fraction profiles for various photovoltaic device configurations; 
           [0012]      FIG. 6  is a schematic of a photovoltaic device having multiple layers; 
           [0013]      FIGS. 7   a - 7   b  illustrate mole-fraction profiles for various photovoltaic device configurations; and 
           [0014]      FIG. 8  is a schematic of a system for generating electricity. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    Photovoltaic modules can include a plurality of interconnected photovoltaic cells formed from various material layers which are patterned into the cells. 
         [0016]    Referring to  FIG. 1 , by way of one example, a photovoltaic device may include a first substrate  15 , such as glass, with a front contact  23  formed adjacent thereto. The front contact  23  may include a multilayered stack including a transparent conductive oxide (TCO). 
         [0017]    A semiconductor layer  31  may be positioned adjacent to front contact  23 . A back contact  43  may be positioned adjacent to semiconductor layer  31 , and a back support  56  may be applied adjacent to the back contact  43 . Back contact  43  may include any suitable contact material, including, for example metals such as molybdenum, nickel, copper, aluminum, titanium, palladium, tungsten, cobalt, chrome, or oxidized or nitrided compounds of these materials. 
         [0018]    It should be noted and appreciated that any of the aforementioned layers may include multiple layers, and that adjacent does not necessarily mean “directly on,” such that in some embodiments, one or more additional layers may be positioned between the layers depicted. A “layer” can include any amount of any material that contacts all or a portion of a surface. For example, a barrier layer may optionally be positioned between first substrate  15  and transparent conductive oxide layer  23 . The barrier layer can be transparent, thermally stable, with a reduced number of pin holes (i.e., pin-sized holes which may develop as a result of the intrinsically imperfect nature of thin-film deposition) and having high sodium-blocking capability to impede sodium and/or contaminant diffusion from the first substrate  15 . A buffer layer may also optionally be positioned between transparent conductive oxide layer  23  and semiconductor layer  31  to decrease the likelihood of irregularities that may occur during the formation of the semiconductor window layer. The substrate  15  and back support  56  may serve as front and back supports for the photovoltaic device, and may both include glass. 
         [0019]    Referring to  FIG. 2 , the semiconductor layer  31  may include multiple layers, including, for example, a cadmium telluride absorber layer  33  adjacent to a cadmium sulfide window layer  34 . For improved performance, a semiconductor layer  31  may also include a zinc telluride reflector layer  32  adjacent to a cadmium telluride layer  31 , and adjacent to a back contact  43 . 
         [0020]    As described above, insertion of a zinc telluride reflector layer  32  at the interface between a semiconductor absorber layer  33  and the back contact  43  is intended to provide a barrier against diffusion of minority electron carriers to the back contact  43 , a technique called “electron reflection.” When a photovoltaic device with a cadmium sulfide layer  34  and a cadmium telluride absorber layer  33  but no reflective layer  32  is under illumination, the electron-hole pairs generated by light in the depletion region of the cadmium telluride bulk are separated by an electron field creating electron flow toward the cadmium sulfide/cadmium telluride interface. However, not all electron-hole pairs are generated inside the space-charge region due to deep penetration of the light into the cadmium telluride (absorber) layer, and some electrons are capable of escaping the space-charge region by diffusion into the quasi-neutral region of the absorber layer  33 . Minority electron carriers reaching the quasi-neutral regions can recombine with hole carriers in the cadmium telluride bulk or diffuse toward the back contact  43  and recombine with hole carriers there. Recombination causes power dissipation inside the device, thereby reducing power conversion efficiency. 
         [0021]    To minimize recombination in the quasi-neutral region of the cadmium telluride layer, the cadmium telluride layer thickness can be reduced such that the electric field from the cadmium sulfide/cadmium telluride junction penetrates across the entire cadmium telluride layer. However, reducing the cadmium telluride layer thickness substantially increases the number of electrons reaching the back contact  43 , resulting in higher recombination losses. Accordingly, semiconductor reflection layer  32  is provided, which is made of a semiconductor material with electron affinity lower than that of cadmium telluride, for example, zinc telluride. This reflection layer can be applied between the cadmium telluride and the back contact to minimize recombination at the back contact by acting as a barrier against electron flow toward the back contact  43 . 
         [0022]    Zinc telluride has the further advantage of being p-type dopable to carrier concentrations in excess of 1×10 18  cm −3  using different methods and dopants, which promote more efficient movement of holes in a photovoltaic device. High carrier concentration, i.e. in excess of 1×10 18  cm −3 , is desirable to maintain high built-in potential in the resulting photovoltaic device as well as to enable good ohmic contact between the zinc telluride layer and the back contact  43 . 
         [0023]    When a zinc telluride layer is formed on a cadmium telluride surface, lattice mismatching at the cadmium telluride/zinc telluride hetero-interface can occur. Lattice mismatching causes stress at the interface between the two semiconductors through the formation of interface defects. Electrically speaking, interface defects may increase recombination losses causing additional power dissipation and reducing power conversion efficiency within the photovoltaic device, thereby negating the desired benefits of the reflector layer  32 . 
         [0024]    The present invention minimizes the negative effect of lattice mismatch between cadmium telluride and zinc telluride layers by introducing an intermediate semiconductor layer as a substitute for the zinc telluride layer, or as an additional layer between the cadmium telluride and zinc telluride layers, that provides either gradual or stepwise transition of the lattice constant, thus forming a graded intermediate layer. In either case, such an intermediate layer may consist of one or several Cd(1−x)Zn(x)Te layers where x defines any suitable number between 0 and 1 and the zinc mole-fraction increases either gradually or stepwise as it gets farther from the cadmium telluride layer. For example, x may define a number of more than about 0.0001, more than about 0.1, more than about 0.2, more than about 0.3, more than about 0.4, less than about 0.9999, less than about 0.8, less than about 0.7, less than about 0.6, or less than about 0.5. Also, x may define a number in a range of about 0.1 to about 0.3, about 0.2 to about 0.4, about 0.3 to about 0.5, about 0.4 to about 0.6, about 0.5, to about 0.7, about 0.6 to about 0.8, about 0.7 to about 0.9, or about 0.8 to about 1. 
         [0025]    As a specific example, when introducing an intermediate layer as a substitute to the zinc telluride layer  32  ( FIG. 2 ), a single potential Cd(1−x)Zn(x)Te layer where x is in the range of 0.2 to 0.3 may be placed adjacent to a cadmium telluride layer. This intermediate layer is sufficient to enable significant electron reflection, increasing open-circuit voltage, while mitigating interface defects due to a reduced lattice mismatch of only approximately 20% to 40% of the offset experienced between cadmium telluride and zinc telluride. 
         [0026]    Changing the range of x as it defines the zinc mole-fraction of the Cd(1−x)Zn(x)Te layer may have advantages and disadvantages. For example, a potential Cd(1−x)Zn(x)Te layer where 0&lt;x&lt;0.2 may be placed adjacent to a cadmium telluride layer. This layer will have the advantage of more greatly reducing lattice mismatch, but the disadvantage of only slightly increasing electron reflection, reducing the benefit to open-circuit voltage. Conversely, a potential Cd(1−x)Zn(x)Te layer where 0.3&lt;x&lt;0.5 will have the benefit of increasing electron reflection, but, with this increased step in composition, the layer will have the disadvantage of increased lattice mismatch, causing power dissipation. An optimal value of x will balance these advantages and disadvantages relative to the specific needs of the intermediate layer. The optimal value for x may also depend on other factors affecting the interfacial quality, such as, the growth process employed, the growth temperature, and the growth rate. 
         [0027]    As another example embodiment, a single potential Cd(1−x)Zn(x)Te layer created where x is in the range of 0.2 to 0.3 may be introduced as an intermediate layer between the cadmium telluride layer  33  and the zinc telluride layer  32  ( FIG. 2 ). As described above, this intermediate layer will mitigate interface defects due to reduced lattice mismatch between the surface of the intermediate layer in contact with the cadmium telluride layer and the surface of the intermediate layer in contact with the zinc telluride layer  32 , while increasing electron reflection capabilities closer to the zinc telluride layer  32 . Other examples of the use of an intermediate layer Cd(1−x)Zn(x)Te, where the value of x changes within the intermediate layer are described in detail below. 
         [0028]    Referring to  FIG. 3 , by way of an example of introducing an intermediate layer as a substitute for the zinc telluride layer, a photovoltaic device  20  may include a cadmium sulfide layer  220  deposited adjacent to a transparent conductive oxide layer. The transparent conductive oxide layer may be part of an annealed transparent conductive oxide stack  210 . A cadmium telluride layer  230  may be deposited adjacent to cadmium sulfide layer  220 . A cadmium zinc telluride layer  240  may be deposited adjacent to a cadmium telluride layer  230 . Cadmium zinc telluride layer  240  may have any suitable thickness, including, for example, more than about 10 A, more than about 50 A, more than about 100 A, less than about 1 μm, less than about 0.5 μm, or less than about 0.2 μm. A back contact layer  250  may be deposited adjacent to cadmium zinc telluride layer  240 , and a back support  200  may be applied adjacent to contact layer  250 . Cadmium zinc telluride layer  240  can have a cadmium to zinc mole-to-mole ratio of about (1−x):x, where x defines a number from 0 to 1. 
         [0029]    The cadmium zinc telluride layer  240  may also include a stack of multiple layers of cadmium zinc telluride. Referring to  FIG. 4 , by way of example, cadmium zinc telluride layer  240  may contain three layers,  313   a - 313   c . Each of layers  313   a - 313   c  may be composed of a certain percent of cadmium or zinc. For example, layer  313   a  may be greater than 80% cadmium, layer  313   c  may be greater than 80% zinc and layer  313   b  may be less than approximately 80% cadmium and less than approximately 80% zinc. Each of layers  313   a - 313   c  may also be a layer of cadmium zinc telluride having a cadmium to zinc mole-to-mole ratio of (1−x):x, where x defines a number from 0 to 1. For example, x may define a number of more than about 0.0001, more than about 0.1, more than about 0.2, more than about 0.3, more than about 0.4, less than about 0.9999, less than about 0.8, less than about 0.7, less than about 0.6, or less than about 0.5. For example, x may define a number in a range of about 0.1 to about 0.3, about 0.2 to about 0.4, about 0.3 to about 0.5, about 0.4 to about 0.6, about 0.5, to about 0.7, about 0.6 to about 0.8, about 0.7 to about 0.9, or about 0.8 to about 1. Layer  313   b  can have a higher zinc mole-fraction than preceding layer  313   a . Likewise, layer  313   c  may have a higher zinc mole-fraction than layer  313   b . Each layer in the stack may have a thickness greater than about 10 A and less than about 1 μm. 
         [0030]    Although  FIG. 4  depicts three layers  313   a ,  313   b ,  313   c  within cadmium zinc telluride layer  240 , the invention is not thus restricted. The invention may have any number of cadmium/zinc telluride layers. For example, the cadmium/zinc telluride layer can go from one layer (in the case where the concentration of cadmium to zinc is gradually changed within the layer) to an indefinite number of layers (in the case where layers of different concentration of cadmium to zinc are used). 
         [0031]    The mole ratio of zinc to cadmium in a single cadmium zinc telluride layer  240  can also vary throughout the layer and increase as the distance from cadmium telluride layer  230  increases. For example, the concentration of cadmium in cadmium zinc telluride layer  240  and/or near the cadmium telluride/cadmium zinc telluride interface can be more than about 90%, but less than or equal to 99%. Conversely, the concentration of zinc can be less than about 10%, but more than or equal to 1%. Specifically, the cadmium concentration in cadmium zinc telluride layer  240  can gradually decrease while the relative zinc concentration increases, as the thickness of cadmium zinc telluride layer  240  (and thus the distance away from cadmium telluride layer  230 ) increases. Thus, the exposed surface of cadmium zinc telluride layer  240 , immediately following deposition, can have a substantially high zinc concentration, e.g., more than about 70%, more than about 80%, or more than about 90%, even substantially close to 100%. 
         [0032]    Cadmium zinc telluride layer  240  may be deposited using any suitable technique. For example, a gradual profile of zinc atoms may be introduced into the cadmium telluride layer using a diffusion process from a gaseous zinc source, or diffusion from a solid zinc source. Alternatively, the cadmium zinc telluride layer can be deposited by simultaneously depositing cadmium and zinc, and gradually varying the amount of each which is supplied. A plurality of cadmium zinc telluride layers may also be deposited, with each layer having a fixed composition. 
         [0033]      FIGS. 5   a  and  5   b  illustrate the zinc/cadmium mole-fraction profiles of two example layer configurations for introducing an intermediate layer or plurality of layers as a substitute for the zinc telluride layer.  FIG. 5   a  depicts a stepwise increase of a zinc mole-fraction in the intermediate layer from 0 to 1, moving away from the cadmium telluride layer towards the back contact.  FIG. 5   b  depicts a gradual increase (as opposed to the step-wise representation in  FIG. 5   a ) of a zinc-mole fraction in the intermediate layer from 0 to 1, moving away from the cadmium telluride layer towards the back contact. 
         [0034]    Referring to  FIG. 6 , by way of an example of introducing an intermediate layer between the cadmium telluride layer and a zinc telluride layer, a photovoltaic device  40  may include a cadmium sulfide layer  420  deposited adjacent to a transparent conductive oxide layer. The transparent conductive oxide layer may be part of an annealed transparent conductive oxide stack  410 . A cadmium telluride layer  430  may be deposited adjacent to cadmium sulfide layer  420 . A cadmium zinc telluride layer  440  may be deposited adjacent to a cadmium telluride layer  430 . A zinc telluride layer  445  may be deposited adjacent to the cadmium zinc telluride layer  440 . Cadmium zinc telluride layer  440  may have any suitable thickness, including, for example, more than about 10 A, more than about 50 A, more than about 100 A, less than about 1 μm, less than about 0.5 μm, or less than about 0.2 μm. A back contact layer  450  may be deposited adjacent to zinc telluride layer  445 , and a back support  400  may be deposited adjacent thereto. 
         [0035]    It should be noted and appreciated that any of the aforementioned descriptions of cadmium zinc telluride layer  240  with reference to  FIG. 3  or  FIG. 4  or any other embodiment of the intermediate layer described herein, may describe or apply to cadmium zinc telluride layer  440  with reference to  FIG. 6 . 
         [0036]      FIGS. 7   a  and  7   b  illustrate the zinc/cadmium mole-fraction profiles of two example layer configurations for introducing an intermediate layer between a cadmium telluride layer and a zinc telluride layer.  FIG. 7   a  depicts a stepwise increase of a zinc mole-fraction in the intermediate layer from 0 to 1, moving away from the cadmium telluride layer towards the zinc telluride layer.  FIG. 7   b  depicts a gradual increase (as opposed to the step-wise representation in  FIG. 7   a ) of a zinc-mole fraction in the intermediate layer from 0 to 1, moving away from the cadmium telluride layer towards the zinc telluride layer. 
         [0037]    Photovoltaic devices/cells fabricated using the methods discussed herein may be incorporated into one or more photovoltaic modules, which may in turn be connected into an array. Referring to  FIG. 8 , by way of example, a photovoltaic array  60  may include one or more interconnected photovoltaic modules  601 . One or more of photovoltaic modules  601  may include one or more photovoltaic cells  611  having any of the multilayered structure or photovoltaic device configurations discussed herein. 
         [0038]    The embodiments described above are offered by way of illustration and example. It should be understood that the examples provided above may be altered in certain respects and still remain within the scope of the claims. It should be appreciated that, while the invention has been described with reference to the above preferred embodiments, other embodiments are within the scope of the claims.