Abstract:
A universal tuning module may include an oscillator, a first tuner configured to process a first television signal, a second tuner configured to process a second television signal, a first switch configured to pass its input containing information associated with an output of the oscillator to said first tuner, and a second switch configured to pass its input containing information associated with the output of the oscillator to the second tuner.

Description:
[0001]    This application claims priority of China Patent Application No. 201320457563.4, filed on Jul. 29, 2013, the entirety of which is incorporated herein by reference. 
       BACKGROUND OF THE DISCLOSURE 
       [0002]    1. Field of the Disclosure 
         [0003]    The present invention relates generally to a universal tuning module, and more particularly to a universal tuning module configured to pass a clock signal from an oscillator to a hybrid tuner or a satellite tuner. 
         [0004]    2. Brief Description of the Related Art 
         [0005]    With the advances in communication technology, a global television broadcasting system has gradually developed into a digital mode. A tuner plays an important role in a digital television, set-top box and future receiving system. 
         [0006]      FIG. 1  is a block diagram of a traditional receiving system for a digital television. Referring to  FIG. 1 , the traditional receiving system includes a first tuner  10 , second tuner  11 , first receiving terminal  12 , second receiving terminal  13 , demodulator  14  and liquid-crystal-display (LCD) panel  15 , wherein the first tuner  10 , second tuner  11  and demodulator  14  are three integrated circuit chips arranged individually. The first receiving terminal  12  is configured to receive a first television signal. The second receiving terminal  13  is configured to receive a second television signal. The first tuner  10  processes the first television signal received by the first receiving terminal  12  to generate an intermediate-frequency (IF) signal. The second tuner  11  processes the second television signal received by the second receiving terminal  13  to generate a set of orthogonal signals. The intermediate-frequency (IF) signal and the set of orthogonal signals may be transmitted to the liquid-crystal-display (LCD) panel  15  for displaying them. The two tuners lead complex circuits with interference. 
       SUMMARY OF THE DISCLOSURE 
       [0007]    The present invention provides a universal tuning module to pass a clock signal from an oscillator to a hybrid tuner or a satellite tuner. 
         [0008]    The universal tuning module may include an oscillator, a first tuner configured to process a first television signal, a second tuner configured to process a second television signal, a first switch configured to pass its input containing information associated with an output of the oscillator to said first tuner, and a second switch configured to pass its input containing information associated with the output of the oscillator to the second tuner. 
         [0009]    In an embodiment, when the first switch is switched on to pass the its input to the first tuner, the second switch is switched off not to pass the its input to the second tuner. When the second switch is switched on to pass the its input to the second tuner, the first switch is switched off not to pass the its input to the first tuner. 
         [0010]    In an embodiment, the universal tuning module may further include a phase-lock-loop (PLL) circuit arranged upstream of the first and second switches and downstream of the oscillator, wherein the phase-lock-loop (PLL) circuit is configured to generate a clock signal with a frequency substantially equal to a multiple of that of the output of the oscillator or to generate a clock signal, based on the output of the oscillator, with any frequency that the first or second tuner needs. 
         [0011]    In an embodiment, the first and second tuners, the first and second switches, and the phase-lock-loop (PLL) circuit may be incorporated in an integrated circuit chip, and the oscillator is not incorporated in the integrated circuit chip. 
         [0012]    In an embodiment, the first and second tuners, the first and second switches, the oscillator and the phase-lock-loop (PLL) circuit are incorporated in a common integrated circuit chip. 
         [0013]    These, as well as other components, steps, features, benefits, and advantages of the present disclosure, will now become clear from a review of the following detailed description of illustrative embodiments, the accompanying drawings, and the claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    The drawings disclose illustrative embodiments of the present disclosure. They do not set forth all embodiments. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Conversely, some embodiments may be practiced without all of the details that are disclosed. When the same reference number or reference indicator appears in different drawings, it may refer to the same or like components or steps. 
           [0015]    Aspects of the disclosure may be more fully understood from the following description when read together with the accompanying drawings, which are to be regarded as illustrative in nature, and not as limiting. The drawings are not necessarily to scale, emphasis instead being placed on the principles of the disclosure. In the drawings: 
           [0016]      FIG. 1  is a block diagram of a traditional receiving system for a digital television; 
           [0017]      FIG. 2  illustrates a block diagram of a television and satellite receiving system in accordance with an embodiment of the present invention; 
           [0018]      FIG. 3  is a block diagram illustrating a universal tuning module of the television and satellite receiving system and components of a local oscillating module of the universal tuning module in accordance with an embodiment of the present invention; 
           [0019]      FIG. 4  is a block diagram illustrating the universal tuning module and components of the hybrid television tuner in accordance with an embodiment of the present invention; 
           [0020]      FIG. 5  is a block diagram illustrating the universal tuning module and components of the satellite television tuner in accordance with an embodiment of the present invention; 
           [0021]      FIG. 6  shows a schematically cross-sectional view of an electronic package for the integrated circuit chip in accordance with an embodiment of the present invention; and 
           [0022]      FIG. 7  illustrates a block diagram of a television and satellite receiving system in accordance with another embodiment of the present invention. 
       
    
    
       [0023]    While certain embodiments are depicted in the drawings, one skilled in the art will appreciate that the embodiments depicted are illustrative and that variations of those shown, as well as other embodiments described herein, may be envisioned and practiced within the scope of the present disclosure. 
       DETAILED DESCRIPTION OF THE INVENTION 
       [0024]    Illustrative embodiments are now described. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for a more effective presentation. Conversely, some embodiments may be practiced without all of the details that are disclosed. 
         [0025]      FIG. 2  illustrates a block diagram of a television and satellite receiving system in accordance with an embodiment of the present invention. Referring to  FIG. 2 , the television and satellite receiving system may include a receiving terminal  22 , such as very-high-frequency (VHF) antenna or ultra-high-frequency (UHF) antenna, for receiving a first signal, i.e. digital or analog television signal having a frequency band, for example, between 42 MHz and 1002 MHz, and a receiving terminal  23  provided with a reflector or reflecting disk and a feed or horn arranged at a focus of the reflector or reflecting disk, wherein the feed or horn may receive a second signal, i.e. digital television signal having a frequency band, for example, between 950 MHz and 2150 MHz, reflected by the reflector and transmitted from a-satellite. The television receiving system may further include a universal tuning module  20  arranged downstream of the receiving terminals  22  and  23  and configured to tune the first signal received from the receiving terminal  22  and/or tune the second signal received from the receiving terminal  23 . The television and satellite receiving system may further include a demodulator  24 , provided by an integrated circuit chip, coupled to the universal tuning module  20  and configured to demodulate the first signal and/or second signal tuned by the universal tuning module  20 . The television and satellite receiving system may further include a display panel  25 , such as liquid-crystal-display (LCD) panel, coupled to the demodulator  24  and configured to display the first signal and/or second signal demodulated by the demodulator  24 . 
         [0026]      FIG. 3  illustrates a block diagram of a universal tuning module of the television and satellite receiving system and components of a local oscillating module of the universal tuning module in accordance with an embodiment of the present invention. Referring to  FIGS. 2 and 3 , the universal tuning module  20  may include a hybrid television tuner  26  configured to tune the first television signal transmitted from the receiving terminal  22  and a satellite television tuner  27  configured to tune the second television signal transmitted from the receiving terminal  23 . 
         [0027]    Referring to  FIG. 3 , the universal tuning module  20  may include an external oscillator  28 , which may be provided with a quartz crystal, configured to generate a reference clock signal at an output of the external oscillator  28 . Alternatively, the external oscillator  28  may be provided with an RLC circuit, composed of resistors, inductors and capacitors, without any quartz crystal. 
         [0028]    Referring to  FIG. 3 , the universal tuning module may include a frequency synthesizer  21  arranged upstream of the hybrid television tuner  26  and satellite television tuner  27  and downstream of the external oscillator  28 . The frequency synthesizer  21  may include a phase-lock-loop (PLL) circuit  208  having an input coupled to the reference clock signal generated from the external oscillator  28 . The phase-lock-loop (PLL) circuit  208  is configured to generate a synthesized clock signal with a frequency substantially equal to a multiple of that of its input or to generate a clock signal, based on its input, with any frequency that the hybrid television tuner  26  or satellite television tuner  27  needs, wherein the frequency of the synthesized clock signal may be controlled by a voltage or current at an input (not shown) of the phase-lock-loop (PLL) circuit  208 . 
         [0029]    Referring to  FIGS. 2 and 3 , the universal tuning module  20  may further include a switch  30   a  arranged downstream of the phase-lock-loop (PLL) circuit  208  and upstream of the hybrid television tuner  26  and a switch  30   b  arranged downstream of the phase-lock-loop (PLL) circuit  208  and upstream of the satellite television tuner  27 . The switch  30   a  is arranged in parallel with the switch  30   b . The switch  30   a  may have an input coupled to the synthesized clock signal configured to be passed by the switch  30   a  from the phase-lock-loop (PLL) circuit  208  to the hybrid television tuner  26 . The switch  30   b  may have an input coupled to the synthesized clock signal configured to be passed by the switch  30   b  from the phase-lock-loop (PLL) circuit  208  to the satellite television tuner  27 . The universal tuning module  20  may further include an inter-integrated circuit (I 2 C)  29  configured to generate a first control signal based on instructions from the demodulator  24  to the switch  30   a  so as to control the switch  30   a  to be switched on to pass the synthesized clock signal from the phase-lock-loop (PLL) circuit  208  to the hybrid television tuner  26  or to be switched off not to pass the synthesized clock signal from the phase-lock-loop (PLL) circuit  208  to the hybrid television tuner  26 , and configured to generate a second control signal based on instructions from the demodulator  24  to the switch  30   b  so as to control the switch  30   b  to be switched on to pass the synthesized clock signal from the phase-lock-loop (PLL) circuit  208  to the satellite television tuner  27  or to be switched off not to pass the synthesized clock signal from the phase-lock-loop (PLL) circuit  208  to the satellite television tuner  27 . When the switch  30   a  is switched on to pass the synthesized clock signal to the hybrid television tuner  26 , the switch  30   b  is switched off not to pass the synthesized clock signal to the satellite television tuner  27 . When the switch  30   a  is switched off not to pass the synthesized clock signal to the hybrid television tuner  26 , the switch  30   b  is switched on to pass the synthesized clock signal to the satellite television tuner  27 . 
         [0030]      FIG. 4  is a block diagram illustrating the universal tuning module and components of the hybrid television tuner in accordance with an embodiment of the present invention. Referring to  FIGS. 3 and 4 , the hybrid television tuner  26  may include (1) a low noise amplifier  200 , e.g. single-ended-to-differential amplifier, arranged downstream of the receiving terminal  22 , (2) a band-pass filter (BPF)  201  arranged downstream of the amplifier  200 , (3) a pair of mixers  202   a  and  202   b , i.e. frequency-down converters, arranged in parallel and downstream of the band-pass filter (BPF)  201 , (4) a pair of variable-gain amplifiers (VGA)  203   a  and  203   b , e.g. differential-to-differential amplifiers, arranged in parallel and downstream of the pair of mixers  202   a  and  202   b  respectively, (5) an image reject filter  204  arranged downstream of the pair of amplifiers  203   a  and  203   b , (6) a band-pass filter (BPF)  205  arranged downstream of the image reject filter  204 , (7) a variable-gain amplifier  206 , e.g. differential-to-differential amplifier, arranged downstream of the band-pass filter (BPF)  205 , (8) a modulator  210   a , e.g. in-phase and quadrature (I/Q) modulator, arranged downstream of the switch  30   a  and upstream of the pair of mixers  202   a  and  202   b , and (9) a power detector  207  having multiple inputs coupled respectively to outputs of the amplifiers  200 ,  203   a  and  203   b.    
         [0031]    Referring to  FIG. 4 , the low noise amplifier  200  may have an input coupled to the first television signal transmitted from the receiving terminal  22  and is configured to amplify its input into an output, e.g. differential output with a phase difference of substantially 180 degrees to each other, of the amplifier  200 . The band-pass filter  201  may have an input, e.g. differential input, coupled to the output of the amplifier  200  and is configured to pass its input at frequencies within a first radio-frequency (RF) band, i.e. RF-1, ranging from 20 MHz to 2000 MHz and preferably ranging from 42 MHz to 1002 MHz, for example, and attenuate its input at frequencies outside the first radio-frequency (RF) band, i.e. RF-1, into an output, e.g. differential output, of the band-pass filter  201 . The universal tuning module may further include multiple inductors  221  coupled between a power source VDD and the band-pass filter  201  so as to reduce interference signals. 
         [0032]    Referring to  FIGS. 3 and 4 , the modulator  210   a  may have an input coupled to the output of the phase-lock-loop (PLL) circuit  208  of the frequency synthesizer  21  through the switch  30   a  and is configured to modulate the synthesized clock signal generated by the phase-lock-loop (PLL) circuit  208  and passed by the switch  30   a  into a first pair of mixing clock signals, e.g. in-phase and quadrature (I/Q) modulated signals, at a pair of outputs of the modulator  210   a . The first pair of mixing clock signals may be transmitted from the modulator  210   a  to the respective mixers  202   a  and  202   b . The first pair of mixing clock signals may have substantially the same frequency as that of the synthesized clock signal generated by the phase-lock-loop (PLL) circuit  208  and passed by the switch  30   a  and have a phase difference of substantially 90 degrees to each other. 
         [0033]    Referring to  FIG. 4 , the mixer  202   a  may have a first input, e.g. differential input, coupled to the output of the band-pass filter  201  and a second input coupled to the output of a first one of the pair of outputs of the modulators  210   a . The mixer  202   a  is configured to convert a second radio-frequency (RF) band, i.e. RF-2, ranging from 20 MHz to 2000 MHz and preferably ranging from 42 MHz to 1002 MHz, for example, at the first input of the mixer  202   a  into a first intermediate-frequency (IF) band, i.e. IF-1, ranging from 1 MHz to 50 MHz and preferably ranging from 1 MHz to 9 MHz with a center frequency of substantially 5 MHz, for example, at an output, e.g. differential output, of the mixer  202   a  based on a frequency of a first one of the first pair of mixing clock signals at the second input of the mixer  202   a , which may be subtracted from frequencies within the second radio-frequency (RF) band, i.e. RF-2, so as to obtain frequencies within the first intermediate-frequency (IF) band, i.e. IF-1, when the second radio-frequency (RF) band, i.e. RF-2, has a center frequency higher than the frequency of the first one of the first pair of mixing clock signals. Alternatively, frequencies within the second radio-frequency (RF) band, i.e. RF-2, may be subtracted from the frequency of the first one of the first pair of mixing clock signals so as to obtain frequencies within the first intermediate-frequency (IF) band, i.e. IF-1, when the second radio-frequency (RF) band, i.e. RF-2, has a center frequency less than the frequency of the first one of the first pair of mixing clock signals. The second radio-frequency (RF) band, i.e. RF-2, may have an upper limit substantially equal to an upper limit of the first radio-frequency (RF) band, i.e. RF-1, and above upper and lower limits of the first intermediate-frequency (IF) band, i.e. IF-1. The second radio-frequency (RF) band, i.e. RF-2, may have a lower limit substantially equal to a lower limit of the first radio-frequency (RF) band, i.e. RF-1, and above the upper and lower limits of the first intermediate-frequency (IF) band, i.e. IF-1. Accordingly, the mixer  202   a  may generate a first intermediate-frequency (IF) signal, e.g. differential signal, having frequencies within the first intermediate-frequency band, i.e. IF-1, transmitted from the output of the mixer  202   a  to the amplifier  203   a.    
         [0034]    Referring to  FIG. 4 , the mixer  202   b  may have a first input, e.g. differential input, coupled to the output of the band-pass filter  201  and a second input coupled to the output of a second one of the first pair of outputs of the modulators  210   a . The mixer  202   b  is configured to convert a third radio-frequency (RF) band, i.e. RF-3, ranging from 20 MHz to 2000 MHz and preferably ranging from 42 MHz to 1002 MHz, for example, at the first input of the mixer  202   b  into a second intermediate-frequency (IF) band, i.e. IF-2, ranging from 1 MHz to 50 MHz and preferably ranging from 1 MHz to 9 MHz with a center frequency of substantially 5 MHz, for example, at an output, e.g. differential output, of the mixer  202   b  based on a frequency of a second one of the first pair of mixing clock signals at the second input of the mixer  202   b , which may be subtracted from frequencies within the third radio-frequency (RF) band, i.e. RF-3, so as to obtain frequencies within the second intermediate-frequency (IF) band, i.e. IF-2, when the third radio-frequency (RF) band, i.e. RF-3, has a center frequency higher than the frequency of the second one of the first pair of mixing clock signals. Alternatively, frequencies within the third radio-frequency (RF) band, i.e. RF-3, may be subtracted from the frequency of the second one of the first pair of mixing clock signals so as to obtain frequencies within the second intermediate-frequency (IF) band, i.e. IF-2, when the third radio-frequency (RF) band, i.e. RF-3, has a center frequency less than the frequency of the second one of the first pair of mixing clock signals. The third radio-frequency (RF) band, i.e. RF-3, may have an upper limit substantially equal to an upper limit of the first radio-frequency (RF) band, i.e. RF-1, and the upper limit of the second radio-frequency (RF) band, i.e. RF-2, and above upper and lower limits of the second intermediate-frequency (IF) band, i.e. IF-2, and the upper and lower limits of the first intermediate-frequency (IF) band, i.e. IF-1. The third radio-frequency (RF) band, i.e. RF-3, may have a lower limit substantially equal to a lower limit of the first radio-frequency (RF) band, i.e. RF-1, and the lower limit of the second radio-frequency (RF) band, i.e. RF-2, and above the upper and lower limits of the second intermediate-frequency (IF) band, i.e. IF-2 and the upper and lower limits of the first intermediate-frequency (IF) band, i.e. IF-1. Accordingly, the mixer  202   b  may generate a second intermediate-frequency (IF) signal, e.g. differential signal, having frequencies within the second intermediate-frequency band, i.e. IF-2, transmitted from the output of the mixer  202   b  to the amplifier  203   b . The first and second intermediate-frequency (IF) signals generated by the respective mixers  202   a  and  202   b  may have a phase difference of substantially 90 degrees to each other. 
         [0035]    Referring to  FIG. 4 , the variable-gain amplifier  203   a  may have an input, e.g. differential input, coupled to the first intermediate-frequency (IF) signal transmitted from the mixer  202   a  and is configured to amplify its input into an output, e.g. differential output, of the amplifier  203   a . The amplifier  203   b  may have an input, i.e. differential input, coupled to the second intermediate-frequency (IF) signal transmitted from the mixer  202   b  and is configured to amplify its input into an output, i.e. differential output, of the amplifier  203   b.    
         [0036]    Referring to  FIG. 4 , the image reject filter  204  may have a first input, e.g. differential input, coupled to the first intermediate-frequency (IF) signal at the output of the amplifier  203   a  and a second input, e.g. differential input, coupled to the second intermediate-frequency (IF) signal at the output of the amplifier  203   b . The image reject filter  204  is configured to perform filtering on the first intermediate-frequency (IF) signal so as to attenuate an image part, i.e. unwanted part, of its first input and pass a real part, i.e. wanted part, of its first input into a first image-rejected signal, e.g. differential signal, and perform filtering on the second intermediate-frequency (IF) signal so as to attenuate an image part, i.e. unwanted part, of its second input and pass a real part, i.e. wanted part, of its second input into a second image-rejected signal, e.g. differential signal. Next, the image reject filter  204  may shift a phase of the first image-rejected signal and/or a phase of the second image-rejected signal such that the first image-rejected signal may be substantially in phase with the second image-rejected signal to be combined with the first image-rejected signal into an output, e.g. differential output, of the image reject filter  204 . 
         [0037]    Referring to  FIG. 4 , the band-pass filter  205  may have an input, e.g. differential input, coupled to the output of the image reject filter  204  and is configured to pass its input at frequencies within a third intermediate-frequency (IF) band, i.e. IF-3, ranging from 1 MHz to 50 MHz and preferably ranging from 1 MHz to 9 MHz with a center frequency of substantially 5 MHz, for example, and attenuate its input at frequencies outside the third intermediate-frequency (IF) band, i.e. IF-3, into an output, e.g. differential output, of the band-pass filter  205 . The third intermediate-frequency (IF) band, i.e. IF-3, may have an upper limit substantially equal to that of the first intermediate-frequency (IF) band, i.e. IF-1, and that of the second intermediate-frequency (IF) band, i.e. IF-2. The third intermediate-frequency (IF) band, i.e. IF-3, may have a lower limit substantially equal to that of the first intermediate-frequency (IF) band, i.e. IF-1, and that of the second intermediate-frequency (IF) band, i.e. IF-2. The variable-gain amplifier  206  may have an input, e.g. differential input, coupled to the output of the band-pass filter  205  and is configured to amplify its input into an output, e.g. differential output, of the variable-gain amplifier  206  based on instructions from the demodulator  24 . The demodulator  24  as shown in  FIG. 2  may have an input, e.g. differential input, coupled to the output of the variable-gain amplifier  206  and is configured to demodulate its input into an output, e.g. differential output, of the demodulator  24  to be displayed on the display panel  25 . 
         [0038]    Referring to  FIG. 4 , the power detector  207  may have a first input, e.g. differential input, coupled to the output of the amplifier  200 , a second input, e.g. differential input, coupled to the output of the amplifier  203   a  and a third input, e.g. differential input, coupled to the output of the amplifier  203   b . The power detector  207  is configured to detect a first power at its first input so as to generate a first output based on the first power, and the amplifier  200  is configured to amplify its input into the output of the amplifier  200  based on the first output of the power detector  207 . The power detector  207  is configured to detect a second power at its second input so as to generate a second output based on the second power, and the amplifier  203   a  is configured to amplify its input into the output of the amplifier  203   a  based on the second output of the power detector  207 . The power detector  207  is configured to detect a third power at its third input so as to generate a third output based on the third power, and the amplifier  203   b  is configured to amplify its input into the output of the amplifier  203   b  based on the third output of the power detector  207 . 
         [0039]      FIG. 5  is a block diagram illustrating the universal tuning module and components of the satellite television tuner in accordance with an embodiment of the present invention. Referring to  FIGS. 3 and 5 , the satellite television tuner  27  may include (1) a low noise amplifier  213 , e.g. single-ended-to-differential amplifier, arranged downstream of the receiving terminal  23 , (2) a band-pass filter (BPF)  214  arranged downstream of the amplifier  213 , (3) a pair of mixers  215   a  and  215   b , i.e. frequency-down converters, arranged in parallel and downstream of the band-pass filter (BPF)  214 , (4) a pair of variable-gain amplifiers  216   a  and  216   b , e.g. differential-to-differential amplifiers, arranged in parallel and downstream of the pair of mixers  215   a  and  215   b  respectively, (5) a pair of band-pass filters  217   a  and  217   b  arranged in parallel and downstream of the pair of amplifiers  216   a  and  216   b  respectively, (6) a pair of variable-gain amplifiers  218   a  and  218   b , e.g. differential-to-differential amplifiers, arranged in parallel and downstream of the pair of band-pass filters  217   a  and  217   b  respectively, (7) a modulator  210   b , e.g. in-phase and quadrature (I/Q) modulator, arranged downstream of the switch  30   b  and upstream of the pair of mixers  215   a  and  215   b , (8) a power detector  212  coupled to outputs of the amplifiers  213 ,  216   a  and  216   b , and (9) a direct-current (DC) offset cancellation circuit  219  arranged downstream of the variable-gain amplifiers  218   a  and  218   b  and with multiple outputs coupled to inputs of the pair of band-pass filters  217   a  and  217   b.    
         [0040]    Referring to  FIG. 5 , the low noise amplifier  213  may have an input coupled to the second television signal transmitted from the receiving terminal  23  and is configured to amplify its input into an output, e.g. differential output with a phase difference of substantially 180 degrees to each other, of the amplifier  213 . The band-pass filter  214  may have an input, e.g. differential input, coupled to the output of the amplifier  213  and is configured to pass its input at frequencies within a fourth radio-frequency (RF) band, i.e. RF-4, ranging from 950 MHz to 2150 MHz, for example, and attenuate its input at frequencies outside the fourth radio-frequency (RF) band, i.e. RF-4, into an output, e.g. differential output, of the band-pass filter  214 . The universal tuning module may further include multiple inductors  222  coupled between a power source VDD and the band-pass filter  214  so as to reduce a background noise. 
         [0041]    Referring to  FIGS. 3 and 5 , the modulator  210   b  may have an input coupled to the output of the phase-lock-loop (PLL) circuit  208  of the frequency synthesizer  21  through the switch  30   b  and is configured to modulate the synthesized clock signal generated by the phase-lock-loop (PLL) circuit  208  and passed by the switch  30   b  into a second pair of mixing clock signals, e.g. in-phase and quadrature (I/Q) modulated signals, at a pair of outputs of the modulator  210   b . The second pair of mixing clock signals may be transmitted from the modulator  210   b  to the respective mixers  215   a  and  215   b . The second pair of mixing clock signals may have substantially the same frequency as that of the synthesized clock signal generated by the phase-lock-loop (PLL) circuit  208  and passed by the switch  30   b  and have a phase difference of substantially 90 degrees to each other. 
         [0042]    Referring to  FIG. 5 , the mixer  215   a  may have a first input, e.g. differential input, coupled to the output of the band-pass filter  214  and a second input coupled to the output of a first one of the pair of outputs of the modulators  210   b . The mixer  215   a  is configured to convert a fifth radio-frequency (RF) band, i.e. RF-5, ranging from 950 MHz to 2150 MHz, for example, at the first input of the mixer  202   a  into a fourth intermediate-frequency (IF) band, i.e. IF-4, ranging from −30 MHz to 30 MHz with a center frequency of substantially 0 MHz, for example, at an output, e.g. differential output, of the mixer  215   a  based on a frequency of a first one of the second pair of mixing clock signals at the second input of the mixer  215   a , which may be subtracted from frequencies within the fifth radio-frequency (RF) band, i.e. RF-5, so as to obtain frequencies within the fourth intermediate-frequency (IF) band, i.e. IF-4. Alternatively, frequencies within the fifth radio-frequency (RF) band, i.e. RF-5, may be subtracted from the frequency of the first one of the second pair of mixing clock signals so as to obtain frequencies within the fourth intermediate-frequency (IF) band, i.e. IF-4. The fifth radio-frequency (RF) band, i.e. RF-5, may have a center frequency substantially equal to the frequency of the first one of the second pair of mixing clock signals. The fifth radio-frequency (RF) band, i.e. RF-5, may have an upper limit substantially equal to an upper limit of the fourth radio-frequency (RF) band, i.e. RF-4, and above absolute values of upper and lower limits of the fourth intermediate-frequency (IF) band, i.e. IF-4. The fifth radio-frequency (RF) band, i.e. RF-5, may have a lower limit substantially equal to a lower limit of the fourth radio-frequency (RF) band, i.e. RF-4, and above the absolute values of the upper and lower limits of the fourth intermediate-frequency (IF) band, i.e. IF-4. Accordingly, the mixer  215   a  may generate a third intermediate-frequency (IF) signal, e.g. differential signal, having frequencies within the fourth intermediate-frequency band, i.e. IF-4, transmitted from the output of the mixer  215   a  to the amplifier  216   a.    
         [0043]    Referring to  FIG. 5 , the mixer  215   b  may have a first input, e.g. differential input, coupled to the output of the band-pass filter  214  and a second input coupled to the output of a second one of the pair of outputs of the modulators  210   b . The mixer  215   b  is configured to convert a sixth radio-frequency (RF) band, i.e. RF-6, ranging from 950 MHz to 2150 MHz, for example, at the first input of the mixer  215   b  into a fifth intermediate-frequency (IF) band, i.e. IF-5, ranging from −30 MHz to 30 MHz with a center frequency of substantially 0 MHz, for example, at an output, e.g. differential output, of the mixer  215   b  based on a frequency of a second one of the second pair of mixing clock signals at the second input of the mixer  215   b , which may be subtracted from frequencies within the sixth radio-frequency (RF) band, i.e. RF-6, so as to obtain frequencies within the fifth intermediate-frequency (IF) band, i.e. IF-5. Alternatively, frequencies within the sixth radio-frequency (RF) band, i.e. RF-6, may be subtracted from the frequency of the second one of the second pair of mixing clock signals so as to obtain frequencies within the fifth intermediate-frequency (IF) band, i.e. IF-5. The sixth radio-frequency (RF) band, i.e. RF-6, may have a center frequency substantially equal to the frequency of the second one of the second pair of mixing clock signals. The sixth radio-frequency (RF) band, i.e. RF-6, may have an upper limit substantially equal to an upper limit of the fourth radio-frequency (RF) band, i.e. RF-4, and the upper limit of the fifth radio-frequency (RF) band, i.e. RF-5, and above absolute values of upper and lower limits of the fifth intermediate-frequency (IF) band, i.e. IF-5, and the absolute values of the upper and lower limits of the fourth intermediate-frequency (IF) band, i.e. IF-4. The sixth radio-frequency (RF) band, i.e. RF-6, may have a lower limit substantially equal to a lower limit of the fourth radio-frequency (RF) band, i.e. RF-4, and the lower limit of the fifth radio-frequency (RF) band, i.e. RF-5, and above the absolute values of the upper and lower limits of the fifth intermediate-frequency (IF) band, i.e. IF-5 and the absolute values of the upper and lower limits of the fourth intermediate-frequency (IF) band, i.e. IF-4. Accordingly, the mixer  215   b  may generate a fourth intermediate-frequency (IF) signal, e.g. differential signal, having frequencies within the fifth intermediate-frequency band, i.e. IF-5, transmitted from the output of the mixer  215   b  to the amplifier  216   b . The third and fourth intermediate-frequency (IF) signals generated by the respective mixers  215   a  and  215   b  may have a phase difference of substantially 90 degrees to each other. 
         [0044]    Referring to  FIG. 5 , the variable-gain amplifier  216   a  may have an input, e.g. differential input, coupled to the third intermediate-frequency (IF) signal transmitted from the mixer  215   a  and is configured to amplify its input into an output, e.g. differential output, of the amplifier  216   a . The amplifier  216   b  may have an input, e.g. differential input, coupled to the fourth intermediate-frequency (IF) signal transmitted from the mixer  215   b  and is configured to amplify its input into an output, e.g. differential output, of the amplifier  216   b.    
         [0045]    Referring to  FIG. 5 , the band-pass filter  217   a  may have an input, e.g. differential input, coupled to the output of the amplifier  216   a  and is configured to pass its input at frequencies within a sixth intermediate-frequency (IF) band, i.e. IF-6, ranging from −30 MHz to 30 MHz for example, and attenuate its input at frequencies outside the sixth intermediate-frequency (IF) band, i.e. IF-6, into an output, e.g. differential output, of the band-pass filter  217   a . The sixth intermediate-frequency (IF) band, i.e. IF-6, may have an upper limit substantially equal to that of the fourth intermediate-frequency (IF) band, i.e. IF-4, and that of the fifth intermediate-frequency (IF) band, i.e. IF-5. The sixth intermediate-frequency (IF) band, i.e. IF-6, may have a lower limit substantially equal to that of the fourth intermediate-frequency (IF) band, i.e. IF-4, and that of the fifth intermediate-frequency (IF) band, i.e. IF-5. 
         [0046]    Referring to  FIG. 5 , the band-pass filter  217   b  may have an input, e.g. differential input, coupled to the output of the amplifier  216   b  and is configured to pass its input at frequencies within a seventh intermediate-frequency (IF) band, i.e. IF-7, ranging from −30 MHz to 30 MHz for example, and attenuate its input at frequencies outside the seventh intermediate-frequency (IF) band, i.e. IF-7, into an output, e.g. differential output, of the band-pass filter  217   b . The seventh intermediate-frequency (IF) band, i.e. IF-7, may have an upper limit substantially equal to that of the fourth intermediate-frequency (IF) band, i.e. IF-4, that of the fifth intermediate-frequency (IF) band, i.e. IF-5 and that of the sixth intermediate-frequency (IF) band, i.e. IF-6. The seventh intermediate-frequency (IF) band, i.e. IF-7, may have a lower limit substantially equal to that of the fourth intermediate-frequency (IF) band, i.e. IF-4, that of the fifth intermediate-frequency (IF) band, i.e. IF-5 and that of the sixth intermediate-frequency (IF) band, i.e. IF-6. 
         [0047]    Referring to  FIG. 5 , the variable-gain amplifier  218   a  may have an input, e.g. differential input, coupled to the output of the band-pass filter  217   a  and is configured to amplify its input into an output, e.g. differential output, of the amplifier  218   a  based on instructions from the demodulator  24 . The variable-gain amplifier  218   b  may have an input, e.g. differential input, coupled to the output of the band-pass filter  217   b  and is configured to amplify its input into an output, e.g. differential output, of the amplifier  218   b  based on instructions from the demodulator  24 . The demodulator  24  as shown in  FIG. 2  may have a pair of inputs, e.g. differential inputs, coupled to the outputs of the amplifiers  218   a  and  218   b  respectively and is configured to demodulate its pair of inputs into an output of the demodulator  24  to be displayed on the display panel  25 . 
         [0048]    Referring to  FIG. 5 , the power detector  212  may have a first input, e.g. differential input, coupled to the output of the amplifier  213 , a second input, e.g. differential input, coupled to the output of the amplifier  216   a  and a third input, e.g. differential input, coupled to the output of the amplifier  216   b . The power detector  212  is configured to detect a fourth power at its first input so as to generate a first output based on the fourth power, and the amplifier  213  is configured to amplify its input into the output of the amplifier  213  based on the first output of the power detector  212 . The power detector  212  is configured to detect a fifth power at its second input so as to generate a second output based on the fifth power, and the amplifier  216   a  is configured to amplify its input into the output of the amplifier  216   a  based on the second output of the power detector  212 . The power detector  212  is configured to detect a sixth power at its third input so as to generate a third output based on the sixth power, and the amplifier  216   b  is configured to amplify its input into the output of the amplifier  216   b  based on the third output of the power detector  212 . 
         [0049]    Referring to  FIG. 5 , the direct-current (DC) offset cancellation circuit  219  may have a first input, e.g. differential input, coupled to the output of the amplifier  218   a  and a second input, e.g. differential input, coupled to the output of the amplifier  218   b . The direct-current offset cancellation circuit  219  is configured to generate a first output, e.g. differential output, to be coupled to the input of the band-pass filter  217   a  so as to reduce a direct-current (DC) component of the output of the amplifier  218   a  at its first input. The direct-current offset cancellation circuit  219  is configured to generate a second output, e.g. differential output, to be coupled to the input of the band-pass filter  217   a  so as to reduce a direct-current (DC) component of the output of the amplifier  218   b  at its second input. Thereby, the direct-current (DC) offset cancellation circuit  219  may reduce a direct-current (DC) component on signal paths for transmitting the third and fourth intermediate-frequency signals. 
         [0050]      FIG. 6  shows a schematically cross-sectional view of an electronic package for the integrated circuit chip in accordance with an embodiment of the present invention. Referring to  FIGS. 3 ,  4 ,  5  and  6 , the hybrid television tuner  26 , the satellite television tuner  27 , frequency synthesizer  21 , switches  30   a  and  30   b  and inter-integrated circuit (I 2 C)  29  may be incorporated or embedded in an integrated circuit chip  42 . The integrated circuit chip  42  may include a semiconductor substrate, such as silicon substrate, having its active devices, such as transistors, its passive devices, such as resistors, capacitors and/or inductors, and its conductive traces, such as damascene electroplated cupper traces or sputtered aluminum traces, formed on or over the silicon substrate. These active devices, passive devices and conductive traces compose the hybrid television tuner  26 , the satellite television tuner  27 , frequency synthesizer  21 , switches  30   a  and  30   b  and inter-integrated circuit (I 2 C)  29 . Another integrated circuit chip is provided with the external oscillator  28 . 
         [0051]    Referring to  FIG. 6 , the electronic package  40  may include (1) a lead frame  41 , (2) the integrated circuit chip  42  attached to a top surface of the lead frame  42 , (3) multiple wirebonded wires  43  each extending across over a corresponding edge of the integrated circuit chip  42  to electrically connect a corresponding metal pad  44  of the integrated circuit chip  42  to a corresponding metal lead or pin  45  of the lead frame  42  and (4) a mold  46  formed over the top surface of the lead frame  41  to encapsulate the integrated circuit chip  42  and the wirebonded wires  43 . 
         [0052]    Alternatively, referring to  FIGS. 3 ,  4 ,  5  and  6 , the hybrid television tuner  26 , the satellite television tuner  27 , frequency synthesizer  21 , switches  30   a  and  30   b , inter-integrated circuit (I 2 C)  29  and external oscillator  28  may be incorporated or embedded in a common integrated circuit chip, such as the integrated circuit chip  42 . 
         [0053]      FIG. 7  illustrates a block diagram of a television and satellite receiving system in accordance with another embodiment of the present invention. The same reference number illustrated in  FIGS. 2-7  indicates elements having the same functions. Referring to  FIG. 7 , the block diagram is similar to that shown in  FIG. 2  except that the demodulator  24  in  FIG. 2 , provided by an integrated circuit chip, is divided into a hybrid television demodulator  24   a  and a satellite television demodulator  24   b  provided by different integrated circuit chips. 
         [0054]    Referring to  FIGS. 3 ,  4 ,  5  and  7 , the hybrid television demodulator  24   a  may have an input, e.g. differential input, coupled to the output of the amplifier  206  of the hybrid television tuner  26  and is configured to demodulate its input into an output, e.g. differential output, of the hybrid television demodulator  24   a  to be displayed on the display panel  25 . The satellite television demodulator  24   b  may have a pair of inputs, e.g. differential inputs, coupled to the outputs of the amplifiers  218   a  and  218   b  of the satellite television tuner  27  respectively and is configured to demodulate its pair of inputs into an output, e.g. differential output, of the satellite television demodulator  24   b  to be displayed on the display panel  25 . The inter-integrated circuit (I 2 C)  29  is configured to generate the first control signal based on instructions from the hybrid television demodulator  24   a  to the switch  30   a  so as to control the switch  30   a  to be switched on to pass the synthesized clock signal from the phase-lock-loop (PLL) circuit  208  to the hybrid television tuner  26  or to be switched off not to pass the synthesized clock signal from the phase-lock-loop (PLL) circuit  208  to the hybrid television tuner  26 , and configured to generate the second control signal based on instructions from the satellite television demodulator  24   b  to the switch  30   b  so as to control the switch  30   b  to be switched on to pass the synthesized clock signal from the phase-lock-loop (PLL) circuit  208  to the satellite television tuner  27  or to be switched off not to pass the synthesized clock signal from the phase-lock-loop (PLL) circuit  208  to the satellite television tuner  27 . The amplifier  206  is configured to amplify its input into the output of the amplifier  206  based on instructions from the hybrid television demodulator  24   a . The amplifier  218   a  is configured to amplify its input into the output of the amplifier  218   a  based on instructions from the satellite television demodulator  24   b . The amplifier  218   b  is configured to amplify its input into the output of the amplifier  218   b  based on instructions from the satellite television demodulator  24   b.    
         [0055]    In accordance with the present invention, the hybrid television tuner  26  and satellite television tuner  27  are incorporated in a common integrated circuit chip, and thus space for the hybrid television tuner  26  and satellite television tuner  27  may be saved. The frequency synthesizer  21  may generate the synthesized clock signal to one of the hybrid television tuner  26  and satellite television tuner  27 , and thus space for circuits may be saved and interference between signals may be reduced. 
         [0056]    The components, steps, features, benefits and advantages that have been discussed are merely illustrative. None of them, nor the discussions relating to them, are intended to limit the scope of protection in any way. Numerous other embodiments are also contemplated. These include embodiments that have fewer, additional, and/or different components, steps, features, benefits and advantages. These also include embodiments in which the components and/or steps are arranged and/or ordered differently. 
         [0057]    Unless otherwise stated, all measurements, values, ratings, positions, magnitudes, sizes, and other specifications that are set forth in this specification, including in the claims that follow, are approximate, not exact. They are intended to have a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they pertain. Furthermore, unless stated otherwise, the numerical ranges provided are intended to be inclusive of the stated lower and upper values. Moreover, unless stated otherwise, all material selections and numerical values are representative of preferred embodiments and other ranges and/or materials may be used. 
         [0058]    The scope of protection is limited solely by the claims, and such scope is intended and should be interpreted to be as broad as is consistent with the ordinary meaning of the language that is used in the claims when interpreted in light of this specification and the prosecution history that follows, and to encompass all structural and functional equivalents thereof.