Abstract:
The present invention relates to a device of protection of a monolithic component including a MOS-type vertical diffused power transistor formed of a great number of identical cells, and a measurement transistor formed of a smaller number of cells identical to those of the power transistor, the drains and the gates of all cells being common, an inductive load being connected to the source of the power transistor, a short-circuiting circuit connected between the source of the power transistor and the source of the measurement transistor, and a control circuit that turns on the short-circuiting circuit when the power transistor turns off.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to vertical MOS power transistors and more specifically to the protection of a vertical MOS power transistor coupled with a vertical MOS current measurement transistor. 
     2. Discussion of the Related Art 
     A vertical MOS power transistor is generally formed of a large number of identical elementary cells in parallel. To measure the current in this transistor, it is usual to associate therewith a measurement transistor formed of a smaller number of the same elementary cells, submitted to the same biasing conditions. When the load of the power transistor is an inductive load, a negative voltage appears across the load upon turning-off of the power transistor. This voltage is likely to trigger the conduction of parasitic elements and to damage the power transistor. 
     FIG. 1 shows a circuit including a vertical MOS power transistor T 1  formed of n elementary cells T 11  to T 1   n , associated with a vertical MOS measurement transistor T 2  including m elementary cells T 21  to T 2   m , with m being much smaller than n. The drains D of the elementary cells of the power transistor and of the measurement transistor are connected together to a high potential Vcc. The gates G of the elementary cells of the power transistor and of the measurement transistor are connected together to a control terminal G. The sources S 1  of the elementary cells of the power transistors are interconnected and connected by an inductive load L to the ground. The sources S 2  of the elementary cells of the measurement transistor are interconnected and connected to a current source I ref . The voltage difference between terminals S 1  and S 2  gives an indication of the fact that the current in the power transistor is greater than or smaller than a threshold equal to (n/m)I ref . 
     It should be noted that in certain applications, current source Iref may be replaced with a resistor R, when the circuit is to measure a charge resistance instead of a charge current. 
     FIG. 2 schematically shows a vertical cross-sectional view of a portion of a silicon wafer  2  in which are made transistors T 1  and T 2 . The drain of an elementary cell corresponds to substrate  21  of the wafer. Area  21  is connected via a heavily-doped N-type (N + ) area  20  to a metallization  22  connected to drain terminal D of the circuit of FIG.  1 . 
     The source of an elementary cell corresponds to an N + -type ring  25  formed in a P-type well  23 . Well  23  generally comprises a heavily-doped P-type (P + ) central area  24 . A source metallization  26  is in contact with the central portion of each well  23  and with ring  25 . 
     The gate of an elementary cell is formed by a polysilicon layer  27 , isolated from the wafer surface by a dielectric, which covers a channel area included between the external periphery of ring  25  and the external periphery of well  23 . Gates  27  are interconnected to a gate node G. 
     FIG. 2 shows three elementary cells of power transistor T 1 . Metallizations  26  of these elementary cells are connected to a same source node S 1 . Similarly, two elementary cells of measurement transistor T 2  have been shown, metallizations  26  of these cells being connected to the same source node S 2 . 
     FIG. 3 shows at a greater scale a portion of FIG. 2 on which parasitic elements existing between two adjacent elementary cells have been shown. Conventionally, gate  27  also covers the area of substrate  21  included between the two elementary cells. This metallization, isolated from substrate  21 , corresponds to a gate of a parasitic transistor T 3  of PMOS type formed of a P-type well  23  of a first elementary cell, of an N-type substrate portion  21 , and of a second P-type well  33  of a second elementary cell. 
     On the other hand, the association of an N + -type area  25 , of a P-type well  23 , and of lightly-doped N-type substrate  21 , forms an NPN-type bipolar parasitic transistor, the emitter of which is area  25 , the collector of which is area  21 , and the base of which is well  23 . 
     Consider an elementary cell T 1   i  of the power transistor adjacent to an elementary cell T 2   j  of the measurement transistor, the sources of which are respectively S 1  and S 2 . An NPN-type bipolar transistor T 4  is connected between source S 1  and drain D of the cell of transistor T 1 . The base of transistor T 4  is connected to the drain of a parasitic PMOS transistor T 3 . Similarly, an NPN-type bipolar transistor T 5  is connected between source S 2  and drain D of the cell of transistor T 2 , the base of transistor T 5  is connected to the source of MOS transistor T 3 . MOS transistor T 3  is controlled by gate G common to transistors T 1  and T 2 . 
     As illustrated in FIG. 1, if load L of transistor T 1  is an inductive load, the voltage across the load, that is, on source S 1 , will become negative when the power transistor will be off. Gate G, which corresponds to the gate of transistor T 3  is then negative but at a voltage greater than source S 1 , and source S 2  is at a potential close to the ground. If the voltage is very negative on source S 1 , MOS transistor T 3  which is then on lets through a high current between terminals S 2  and S 1 . When this current, which flows, in particular, under N +  region  25 , exceeds given threshold, bipolar transistor T 4  turns on. This creates a short-circuit between source terminal  26  and drain terminal  22  of cell T 2   i . Terminal  26  being at a very negative potential and terminal  22  being at potential Vcc, a destructive breakdown of the structure may result therefrom. The current which flows through transistor T 4  depends on the gain of this transistor. Now, in the framework of modem technologies, the size of wells  23  decreases and the doping level of areas  24  is reduced. As a result, the gain of parasitic bipolar transistors T 4  increases and thus the destructive breakdown risk increases. 
     The present inventors have thus searched various ways for eliminating the destructive effects linked to the turning-on of parasitic bipolar transistors by the above-mentioned parasitic MOS transistors. 
     FIG. 4 very schematically shows a top view of a device such as shown in FIG.  1 . Block T 1  represents the surface occupied by the elementary cells of power transistor T 1  and block T 2  represents the surface occupied by the elementary cells of measurement transistor T 2 . T 3  symbolizes the parasitic MOS transistors existing between the adjacent cells of the power transistor and of the measurement transistor. 
     FIG. 5 shows a vertical cross-sectional view of a first solution to avoid the above-mentioned destructive breakdowns. The structure is very close to the structure shown in FIG. 2, and the same reference characters designate the same elements. Between two adjacent elementary cells T 1   i  and T 2   j , respectively belonging to the power transistor and to the measurement transistor, is interposed a buffer cell B. Such a buffer cell may be implemented by eliminating the N +  implantation of the sources in an elementary cell of T 1 . There no longer exist parasitic bipolar transistors. 
     FIG. 6 very schematically shows a top view of a device such as that in FIG.  5 . Block T 1  shows the surface occupied by the elementary cells of power transistor T 1 , block T 2  represents the surface occupied by the elementary cells of measurement transistor T 2 , and block B represents the surface occupied by the buffer cells placed between the power transistor and the measurement transistor. Transistor T 3  represents the parasitic MOS transistors existing between the elementary cells of measurement transistor T 2  and the adjacent buffer cells B. 
     In FIG. 5, the currents flowing in normal operation from the source of elementary cells of the power and measurement transistors have been represented by arrows. The elementary cells adjacent to buffer cells B receive, in normal operation, a greater current density than the other elementary cells. The ratio between the currents flowing through transistors T 1  and T 2  varies with the value of the currents. This imbalance of the currents no longer enables simply determining the current in power transistor T 1  based on the current flowing through measurement transistor T 2 . 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to implement the protection of a device such as that shown in FIG.  1 . 
     An object of the present invention is to implement a device including a power transistor and a measurement transistor in which there is, in normal operation, a constant ratio between the current flowing through the measurement transistor and the current flowing through the power transistor. 
     Another object of the present invention includes providing a low cost and easy to implement solution to the problems encountered in prior art. 
     These objects, as well as others, are achieved by a device that protects a monolithic component, comprising a MOS-type vertical diffused power transistor formed of a great number of identical cells, and a measurement transistor formed of a smaller number of cells identical to those of the power transistor, the drains and the gates of all cells being common, an inductive load being connected to the source of the power transistor, and comprising: 
     a short-circuiting means connected between the source of the power transistor and the source of the measurement transistor, and 
     a control means that turns on the short-circuiting means when the power transistor turns off. 
     According to an embodiment of the present invention, the short-circuiting means is a MOS transistor. 
     According to an embodiment of the present invention, the control means is a dividing bridge connected across the inductive load. 
     According to an embodiment of the present invention, the control means includes a diode, the anode of which is connected to the gate of the short-circuiting transistor and the cathode of which is connected to the cathode of an avalanche diode, the anode of which is connected to the source of the power transistor, and a resistor connected between the gate of the short-circuiting transistor and a reference voltage which may be, in one embodiment, ground. 
     According to an embodiment of the present invention, the substrate and the source of the short-circuiting transistor are interconnected. 
     According to an embodiment of the present invention, the short-circuiting means is a lateral transistor implemented in the same monolithic component as the vertical power and measurement transistors. 
     The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a device according to prior art; 
     FIG. 2 shows a partial cross-sectional view of the device shown in FIG. 1; 
     FIG. 3 shows parasitic components in a detail of FIG. 2; 
     FIG. 4 very schematically shows a top view of the embodiment shown in FIG. 1; 
     FIG. 5 shows the cross-sectional view of another embodiment according to prior art; 
     FIG. 6 very schematically shows a top view of the embodiment shown in FIG. 5; 
     FIG. 7 shows a diagram in the form of blocks according to the present invention; 
     FIG. 8 very schematically shows an embodiment according to the present invention; 
     FIG. 9 very schematically shows a cross-sectional view of the embodiment shown in FIG. 8; 
     FIG. 10 very schematically shows a top view of the embodiment shown in FIG. 8; and 
     FIG. 11 very schematically shows another embodiment according to the present invention. 
    
    
     DETAILED DESCRIPTION 
     In the various drawings, the same reference characters designate the same elements. Further, as is conventional in the field of the representation of semiconductor components, the various cross-sectional and top views are not drawn to scale. 
     FIG. 7 shows a simplified diagram of a circuit according to the present invention. A cell T 1   i  among the n elementary cells T 11  to T 1   n  of a power transistor T 1 , and an elementary cell T 2   j  among the m elementary cells T 2   l  to T 2   m  of a measurement transistor, cell T 1   i  being adjacent to cell T 2   j . The drains of elementary cells T 1   i  and T 2   j  are connected to a drain D common to all cells, themselves connected to a high supply potential Vcc. The gates G of cells T 1   i  and T 2   j  are connected together to a control terminal G common to all cells. The source of cell T 1   i  is connected to a terminal S 1  connected to all cells of power transistor T 1 , itself connected to the ground by an inductive load L. The source of cell T 2   j  is connected to a terminal S 2  common to all cells of measurement transistor T 2 , itself connected to a current source I ref . As in prior art, the voltage difference between terminals S 1  and S 2  gives an indication of the fact that the current in the power transistor is greater or smaller than a threshold equal to (n/m)I ref . It should be noted that FIG. 7 is very simplified, and that a resistor is conventionally connected in series with current source I ref , for example, to limit the current in T 3  when on, and to have the voltage on S 2  drop when S 1  becomes negative. This limits voltage V GS2  of T 2  when S 1  and G become negative and thus to avoids a breakdown of the gate oxide of T 2 . 
     FIG. 7 also shows parasitic transistors which are associated with cells T 1   i  and T 2   j . A bipolar parasitic transistor T 4  is connected in parallel on cell T 1   i . A bipolar parasitic transistor T 5  is connected in parallel on cell T 2   j . The bases of transistors T 4  and T 5  are respectively connected to the drain and the source of a parasitic MOS transistor T 3 . The gate of parasitic MOS transistor T 3  is connected to gate G of the circuit. These parasitic elements are such as described in relation with FIG.  3 . 
     According to the present invention, a short-circuiting means T 6  is connected between common source terminals S 1  and S 2 . Short-circuiting means T 6  is controlled by a control means C which is turns on means T 6  upon the turning-off of power transistor T 1 . 
     FIG. 8 shows an embodiment of short-circuiting means T 6  and of control means C. The short-circuiting means is a MOS transistor T 6 , the source S 6  of which is connected to source terminal S 1  and the drain D 6  of which is connected to source terminal S 2 . Two resistors R 1  and R 2  are connected in series across load L, the connection node of the two resistors is connected to gate G 6  of transistor T 6 . 
     Resistors R 1  and R 2  form a dividing bridge connected across load L. Resistors R 1  and R 2  are chosen to turn on transistor T 6  when power transistor T 1  is off, and the voltage across load L exceeds a predetermined negative threshold. This predetermined negative threshold can, for example, be chosen to be greater than the negative threshold for which the current flowing through the above-mentioned parasitic elements will turn on parasitic transistor T 4 . 
     When turned on, transistor T 6  short-circuits source terminals S 1  and S 2  of the circuit and eliminates any risk of crossing of parasitic MOS transistor T 3  and thus of turning-on of parasitic bipolar transistor T 4 . Any risk of breakdown of the structure is thus avoided. 
     In normal operating mode, the voltage across load L is such that transistor T 6  remains off, and the present invention thus does not affect the normal operating mode. 
     FIG. 9 shows a simplified cross-sectional view of a portion of the circuit according to the present invention. The right-hand portion of the circuit illustrates cells of vertical MOS transistors T 1  and T 2  described in relation with FIG.  2 . Further, in the left-hand portion of FIG. 9, an implementation of a short-circuiting transistor T 6  has been shown in the form of a lateral-type MOS transistor. The drain of transistor T 6  is formed of a heavily-doped N + -type area  40  formed in a P-type well  42 . Drain D 6  of transistor T 6  is connected to source terminal S 2  of the measurement transistor. The source of transistor T 6  is formed of a heavily-doped N + -type region  41  formed in well  42 . Source S 6  of transistor T 6  is connected to source terminal S 1  of the power transistor. Well  42  is biased by a heavily-doped P + -type area  43 , also formed in well  42 , and connected to terminal S 1 . Gate G 6  of transistor T 6  is formed by a polysilicon layer  44  located above the section of well  42  comprised between areas  40  and  41 , isolated from the surface of well  42  by a dielectric. 
     FIG. 10 shows a simplified top view of a circuit according to the present invention. Transistor T 6  has been implanted in the vicinity of transistors T 1  and T 2 . The respective sizes of transistors T 1 , T 2 , T 6  are determined according to the maximum currents meant to flow therethrough. 
     Short-circuiting transistor T 6  is, as has been seen previously, off in normal operating mode. The ratio between the currents flowing through power transistor T 1  and measurement transistor T 2  remains constant and determined (equal to n/m as described in relation with FIG.  1 ). The present invention thus protects the device described in prior art while keeping the same ratio between the measurement current and the current in a power transistor. The addition of transistor T 6  further is of low cost and easy to implement. 
     Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. Thus, short-circuiting means T 6  can be implemented by other structures than a MOS transistor, for example, a bipolar transistor or a thyristor. Similarly, control means C can be a dividing bridge, but other control means performing the same function may also be used. 
     FIG. 11 shows as an example an alternative of the control means of transistor T 6 . Instead of a resistive dividing bridge, a circuit including a diode D, an avalanche diode Z, and a resistor R is here used. The anode of diode D is connected to gate G 6  of transistor T 6 , its cathode being connected to the cathode of avalanche diode Z. The anode of avalanche diode Z is connected to source terminal S 1 . The second terminal of resistor R is connected to the ground. The reverse conduction voltage of avalanche diode Z is chosen so that transistor T 6  is turned on when the voltage at S 1  becomes more negative than a predetermined threshold. The control means formed by avalanche diode Z, diode D, and resistor R will consume less in normal operation mode than the dividing bridge formed of resistor R 1  and of resistor R 2  shown in FIG.  8 . 
     Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.