Abstract:
Two charge pump circuits are connected in a cascade manner. Each of the charge pump circuits includes two charging switches and two voltage-boosting switches. A voltage-boosting switch, provided on a side for adding a boosting voltage to a charging voltage in a second-stage charge pump circuit, includes a plurality of switches. One ends of the switches are commonly connected to a capacitor. Different boosting voltages are applied to other ends of the switches. A selecting unit selects one of the switches, during a boosting period, based on an input voltage or an output voltage to or from a first-stage charge pump circuit.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a charge-pump-type power supply circuit that boosts an input voltage with charging and discharging of a capacitor, and more particularly, to a charge-pump-type power supply circuit that can obtain a high voltage by a multistage cascaded-connection.  
         [0003]     2. Description of the Related Art  
         [0004]     Generally, a charge-pump-type power supply circuit uses a metal-oxide semiconductor (MOS) transistor for a switch forming a charging path and a discharging path, and boosts a voltage by applying an input voltage to a charging capacitor through the charging path to accumulate charges, applying the input voltage to the charging capacitor through the discharging path to add charges to the accumulated charges, and transferring total charges to an output capacitor. A conventional charge-pump-type power supply circuit is disclosed in, for example, Japanese application patent laid-open publication No. 11-150943, and Japanese application patent laid-open publication No. 2001-309641. Because the output voltage obtained is twice the input voltage, to obtain an even higher voltage, a configuration of a multistage cascaded-connection of the charge-pump-type power supply circuit is employed. For an easy understanding of the present invention, a two-stage-cascaded charge-pump-type power supply circuits will be described.  
         [0005]      FIG. 8  is a circuit diagram of the basic configuration of the charge-pump-type power supply circuit in a two-stage configuration according to a conventional technology. A first-stage charge-pump-type power supply circuit (hereinafter, “charge pump circuit”) CP 1  and a second-stage charge pump circuit CP 2  have the same configuration. The charge pump circuit CP 1  includes charging switches (PMOS transistor Q 11 , NMOS transistor Q 12 ) forming a charging path, discharging switches (NMOS transistor Q 13 , PMOS transistor Q 14 ) forming a discharging path, a charging capacitor C 11 , and an output capacitor C 12 .  
         [0006]     On the charging side of the charge pump circuit CP 1 , an input voltage Vin is applied to a source of the PMOS transistor Q 11 , and a drain of the PMOS transistor Q 11  is connected to one electrode of the charging capacitor C 11 . A drain of the NMOS transistor Q 12  is connected to the other electrode of the charging capacitor C 11 . A source of the NMOS transistor Q 12  is connected to the ground. A control circuit (not-shown) generates a charging control signal TC 1  that is directly applied to the gate of the NMOS transistor Q 12 . The signal TC 1  is also applied via an inverter Q 51  to the gate of the PMOS transistor Q 11 .  
         [0007]     On the discharging side of the charge pump circuit CP 1 , the input voltage Vin is applied to a source of the NMOS transistor Q 13 , and a drain of the NMOS transistor Q 13  is connected to the other electrode of the charging capacitor C 11 . A source of the PMOS transistor Q 14  is connected to the one electrode of the charging capacitor C 11 . The output capacitor C 12  is connected to a drain of the PMOS transistor Q 14  and the ground. An inverter Q 71  inverts the charging control signal TC 1  into a discharge control signal TD 1  that is directly applied to the gate of the NMOS transistor Q 13 . The signal TD 1  is also applied via an inverter Q 61  to a gate of the PMOS transistor Q 14 .  
         [0008]     The charge pump circuit CP 2  includes charging switches (PMOS transistor Q 21 , NMOS transistor Q 22 ) forming a charging path, discharging switches (NMOS transistor Q 23 , PMOS transistor Q 24 ) forming a discharging path, a charging capacitor C 21 , and an output capacitor C 22 .  
         [0009]     On the charging side of the charge pump circuit CP 2 , a source of the PMOS transistor Q 21  is connected to the drain of the PMOS transistor Q 14  in the charge pump circuit CP 1 . A drain of the PMOS transistor Q 21  is connected to one electrode of the charging capacitor C 21 . A drain of the NMOS transistor Q 22  is connected to the other electrode of the charging capacitor C 21 . A source of the NMOS transistor Q 22  is connected to the ground. The charging control signal TC 1  is applied to a gate of the NMOS transistor Q 22 , and to a gate of the PMOS transistor Q 21  via an inverter Q 52 .  
         [0010]     On the discharging side of the charge pump circuit CP 2 , a source of the NMOS transistor Q 23  is connected to the drain of the PMOS transistor Q 14  in the charge pump circuit CP 1 . A drain of the NMOS transistor Q 23  is connected to the other electrode of the charging capacitor C 21 . A source of the PMOS transistor Q 24  is connected to the one electrode of the charging capacitor C 21 . The output capacitor C 22  is arranged between a drain of the PMOS transistor Q 24  and the ground. The inverter Q 71  inverts the charging control signal TC 1  into the discharge control signal TD 1  that is directly applied to a gate of the NMOS transistor Q 23 . The signal TC 1  is also applied to a gate of the PMOS transistor Q 24  via an inverter Q 62 .  
         [0011]      FIG. 9  is a timing chart illustrating the voltage boosting operation of the charge-pump-type power supply circuit shown in  FIG. 8 . The charging control signal TC 1  and the discharge control signal TD 1  are binary signals, alternately repeating a high-level period and a low-level period with the same duty ratio with different polarities. The signals allow the charge pump circuit CP 1  and charge pump circuit CP 2  to switch alternately the charging path and discharging path at the same constant time interval.  
         [0012]     In the charge pump circuit CP 1  and the charge pump circuit CP 2 , the PMOS transistors Q 11 , Q 21  and the NMOS transistors Q 12 , Q 22  are ON during a charging period in which the charging control signal TC 1  is at a logical high (Hi) level and the discharge control signal TD 1  is at a logical low (Lo) level. On the other hand, the NMOS transistors Q 13 , Q 23  and the PMOS transistors Q 14 , Q 24  are ON during a discharging period in which the discharge control signal TD 1  is at the Hi level and the charging control signal TC 1  is at the Lo level.  
         [0013]     During the charging period, the PMOS transistor Q 11  and the NMOS transistor Q 12  are ON in a series circuit formed with the PMOS transistor Q 11 , the charging capacitor C 11 , and the NMOS transistor Q 12  between the input power supply Vin and ground, and a charging current I 11  flows to charge the charging capacitor C 11  up to a voltage VC 11 .  
         [0014]     During the discharging period, the NMOS transistor Q 13  and the PMOS transistor Q 14  are ON in a series circuit formed with the NMOS transistor Q 13 , the charging capacitor C 11 , the PMOS transistor Q 14 , and the output capacitor C 12  between the input power supply Vin and the ground, and a discharge current I 12  flows to perform a discharge operation (voltage boosting operation) in which a voltage obtained by adding the input power supply Vin to the charging voltage VC 11  of the charging capacitor C 11  is transferred to the output capacitor C 12 .  
         [0015]     Because the charge pump circuit CP 1  alternately performs the charging and discharging operations as above, an output voltage Vout 1  (2×Vin) corresponding to twice the input power-supply voltage Vin is obtained at the output capacitor C 12 .  
         [0016]     The charge pump circuit CP 2  also operates in a similar manner. During the charging period, a terminal voltage Vout 1  across the output capacitor C 12  causes a charging current I 21  to charge the charging capacitor C 21  up to a voltage VC 21 . During the discharging period, a voltage boosting operation is performed in which a voltage obtained by adding the terminal voltage Vout 1  to a charging voltage VC 21  of the charging capacitor C 21  is transferred to the output capacitor C 22 . With a repetition of the above procedures, if there is no voltage loss, an output voltage Vout 2  (4×Vin) corresponding to four times the input voltage Vin is obtained at the output capacitor C 22 .  
         [0017]     However, in the conventional multistage-cascade-connected charge-pump-type power supply circuits, because a second or a subsequent stage circuit simply doubles the input voltage, the output voltage is proportional to the number of the cascaded stages. As a result, an amount of a change of the output voltage becomes large with respect to an amount of a change of the input voltage. In addition, the output voltage at the same output terminal varies considerably with a change of the input voltage. Therefore, the circuit needs to be formed with an element that can withstand the maximum input voltage, which results in an increase in a circuit size.  
         [0018]     To solve the above problems, the conventional multistage-cascaded charge pump circuits adopt, for example, a constant voltage circuit inserted in a path for applying the input voltage to stabilize the input voltage. However, because this structure considerably deteriorates an efficiency of the power supply.  
       SUMMARY OF THE INVENTION  
       [0019]     It is an object of the present invention to at least solve the problems in the conventional technology.  
         [0020]     A charge-pump-type power supply circuit according to one aspect of the present invention includes two charge pump circuits connected in a cascade manner and a selecting unit. Each of the charge pump circuits includes two charging switches configured to charge a capacitor up to an input voltage; and two voltage-boosting switches configured to add the input voltage to a charging voltage of the capacitor as a boosting voltage. One of the voltage-boosting switches, which is provided on a side for adding the boosting voltage to the charging voltage in a second-stage charge pump circuit, includes a plurality of switches. One ends of the switches are commonly connected to the capacitor, and different boosting voltages are applied to other ends of the switches, respectively. The selecting unit is configured to select one of the switches, during a boosting period, based on the input voltage to a first-stage charge pump circuit or an output voltage from the first-stage charge pump circuit.  
         [0021]     A charge-pump-type power supply circuit according to another aspect of the present invention includes two charge pump circuits connected in a cascade manner and a selecting unit. Each of the charge pump circuits includes two charging switches configured to charge a capacitor up to an input voltage; and two voltage-boosting switches configured to add the input voltage to a charging voltage of the capacitor as a boosting voltage. One of the charging switches, which is provided on a high-voltage side for charging the capacitor in a second-stage charge pump circuit, includes a plurality of switches. One ends of the switches are commonly connected to the capacitor, and different charging voltages are applied to other ends of the switches, respectively. The selecting unit is configured to select one of the switches, during a charging period, based on the input voltage to a first-stage charge pump circuit or an output voltage from the first-stage charge pump circuit.  
         [0022]     A charge-pump-type power supply circuit according to still another aspect of the present invention includes two charge pump circuits connected in a cascade manner and a selecting unit. Each of the charge pump circuits includes two charging switches configured to charge a capacitor up to an input voltage; and two voltage-boosting switches configured to add the input voltage to a charging voltage of the capacitor as a boosting voltage. Each of a second-stage charge pump circuit and a third-stage charge pump circuit includes a first configuration or a second configuration. The first configuration is such that one of the voltage-boosting switches, which is provided on a side for adding the boosting voltage to the charging voltage, includes a plurality of switches, one ends of the switches are commonly connected to the capacitor, and different boosting voltages are applied to other ends of the switches, respectively. The second configuration is such that one of the charging switches, which is provided on a high-voltage side for charging the capacitor, includes a plurality of switches, one ends of the switches are commonly connected to the capacitor, and different boosting voltages are applied to other ends of the switches, respectively. The selecting unit configured to select one of the switches in the second-stage charge pump circuit and the third-stage charge pump circuit, during a boosting period or a charging period, based on the input voltage to a first-stage charge pump circuit or an output voltage from the first-stage charge pump circuit.  
         [0023]     A charge-pump-type power supply circuit according to still another aspect of the present invention includes a plurality of charge pump circuits connected in a cascade manner and a selecting unit. Each of the charge pump circuits includes two charging switches configured to charge a capacitor up to an input voltage; and two voltage-boosting switches configured to add the input voltage to a charging voltage of the capacitor as a boosting voltage. One of the voltage-boosting switches, which is provided on a side for adding the boosting voltage to the charging voltage in a second-stage charge pump circuit and subsequent-stage charge pump circuits, includes a plurality of switches. One ends of the switches are commonly connected to the capacitor, and different boosting voltages are applied to other ends of the switches, respectively. The selecting unit configured to select one of the switches, during a boosting period, based on at least the input voltage to a first-stage charge pump circuit or an output voltage from the first-stage charge pump circuit.  
         [0024]     A charge-pump-type power supply circuit according to still another aspect of the present invention includes a plurality of charge pump circuits connected in a cascade manner and a selecting unit. Each of the charge pump circuits includes two charging switches configured to charge a capacitor up to an input voltage; and two voltage-boosting switches configured to add the input voltage to a charging voltage of the capacitor as a boosting voltage. One of the charging switches, which is provided on a high-voltage side for charging the capacitor in a second-stage charge pump circuit and subsequent-stage charge pump circuits, includes a plurality of switches. One ends of the switches are commonly connected to the capacitor, and different charging voltages are applied to other ends of the switches, respectively. The selecting unit configured to select one of the switches, during a charging period, based on at least the input voltage to a first-stage charge pump circuit or an output voltage from the first-stage charge pump circuit.  
         [0025]     A charge-pump-type power supply circuit according to still another aspect of the present invention includes a plurality of charge pump circuits connected in a cascade manner and a selecting unit. Each of the charge pump circuits includes two charging switches configured to charge a capacitor up to an input voltage; and two voltage-boosting switches configured to add the input voltage to a charging voltage of the capacitor as a boosting voltage. Each of a second-stage charge pump circuit and subsequent-stage charge pump circuits includes a first configuration or a second configuration. The first configuration is such that one of the voltage-boosting switches, which is provided on a side for adding the boosting voltage to the charging voltage, includes a plurality of switches, one ends of the switches are commonly connected to the capacitor, and different boosting voltages are applied to other ends of the switches, respectively. The second configuration is such that one of the charging switches, which is provided on a high-voltage side for charging the capacitor, includes a plurality of switches, one ends of the switches are commonly connected to the capacitor, and different boosting voltages are applied to other ends of the switches, respectively. The selecting unit is configured to select one of the switches in the second-stage charge pump circuit and the subsequent-stage charge pump circuits, during a boosting period or a charging period, based on at least the input voltage to a first-stage charge pump circuit or an output voltage from the first-stage charge pump circuit.  
         [0026]     The above and other objects, features, advantages and technical and industrial significance of this invention will be better understood by reading the following detailed description of presently preferred embodiments of the invention, when considered in connection with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0027]      FIG. 1  is a circuit diagram of a charge-pump-type power supply circuit according to a first embodiment of the present invention;  
         [0028]      FIG. 2  is a circuit diagram of a charge-pump-type power supply circuit according to a second embodiment of the present invention;  
         [0029]      FIG. 3  is a circuit diagram of a charge-pump-type power supply circuit according to a third embodiment of the present invention;  
         [0030]      FIG. 4  is a circuit diagram of a charge-pump-type power supply circuit according to a fourth embodiment of the present invention;  
         [0031]      FIG. 5  is a circuit diagram of a charge-pump-type power supply circuit according to a fifth embodiment of the present invention;  
         [0032]      FIG. 6  is a circuit diagram of a selection-signal generating circuit shown in  FIG. 5 ;  
         [0033]      FIG. 7  is a table for explaining a voltage boosting operation of the charge-pump-type power supply circuit shown in  FIG. 5 ;  
         [0034]      FIG. 8  is a circuit diagram of a charge-pump-type power supply circuit in a two-stage-cascaded configuration according to a conventional technology; and  
         [0035]      FIG. 9  is a timing chart for illustrating a voltage boosting operation of the charge-pump-type power supply circuit shown in  FIG. 8 . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0036]     Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings.  
         [0037]      FIG. 1  is a circuit diagram of a charge-pump-type power supply circuit according to a first embodiment of the present invention, with an example of a two-stage-cascaded charge-pump-type power supply circuit. Note that, in  FIG. 1 , the same or equivalent components as those shown in  FIG. 8  are referred to by the same reference numerals. The input power-supply voltage is indicated by Vin 0  instead of Vin.  
         [0038]     A first-stage charge pump circuit  10  corresponds to the charge pump circuit CP 1  shown in  FIG. 8 , and the second-stage charge pump circuit  11  corresponds to the charge pump circuit CP 2 , in which the NMOS transistor Q 23  on the discharging side is replaced by two NMOS transistors Q 230 , Q 231  connected in parallel. The power supply circuit shown in  FIG. 1  also includes a selection-signal generating circuit  12 , and AND circuits  20 ,  21  forming a selection circuit.  
         [0039]     An output voltage Vout 1  from the first-stage charge pump circuit  10  is applied to a source of the NMOS transistor Q 230 , while the input voltage Vin 0  is applied to a source of the NMOS transistor Q 231 .  
         [0040]     The selection-signal generating circuit  12  includes a voltage dividing circuit that is formed with two resistors R 1 , R 2  connected in series, a comparison circuit  15 , a reference voltage source (Vref), and an inverter  16 . In the voltage dividing circuit (R 1 , R 2 ), one end of the resistor R 1  is connected to a supplying line of the input voltage Vin 0 , and one end of the resistor R 2  is connected to the ground. The other ends of the resistors R 1 , R 2  are connected together to a negative (−) input of the comparison circuit  15 . The reference voltage source (Vref) is connected to a positive (+) input of the comparison circuit  15 . An output of the comparison circuit  15  is connected to one input of the AND circuit  21 . The output is also connected to one input of the AND circuit  20  via the inverter  16 . The discharge control signal TD 1  from the inverter Q 71  is applied to the other inputs of the AND circuit  20 ,  21 . An output end of the AND circuit  20  is connected to a gate of the NMOS transistor Q 231 . An output end the AND circuit  21  is connected to a gate of the NMOS transistor Q 230 .  
         [0041]     The first-stage charge pump circuit  10  outputs twice the input voltage Vin 0  as the output voltage Vout 1  to the second-stage charge pump circuit  11 , as in the charge pump circuit CP 1  shown in  FIG. 8 .  
         [0042]     In the second-stage charge pump circuit  11 , during a charging period with the charging control signal TC 1  at a Hi level, a charging operation is performed in which the output voltage Vout 1  (corresponding to twice the input voltage Vin 0 ) from the first-stage charge pump circuit  10  charges the charging capacitor C 21 , as in the charge pump circuit CP 2  shown in  FIG. 8 . However, during a discharging period with the discharge control signal TD 1  at a Hi level, the circuit  11  selects a boosting voltage according to the level of the input voltage Vin 0 , rather than simply doubling the output voltage Vout 1  from the first-stage charge pump circuit  10 .  
         [0043]     In the selection-signal generating circuit  12 , the voltage dividing circuit (R 1 , R 2 ), which is disposed between the supplying line of the input voltage Vin 0  and the ground, provides a divided voltage to monitor a change of the level of the input voltage Vin 0 , as a monitor voltage. The comparison circuit  15  compares the monitor voltage from the voltage dividing circuit (R 1 , R 2 ) with a reference voltage Vref. When the discharge control signal TD 1  is at a Hi level, the following operation is performed according to a result of the comparison.  
         [0044]     If the monitor voltage is less than the reference voltage Vref, the comparison circuit  15  outputs a Hi level. The AND circuit  21  thus outputs a Hi level and the AND circuit  20  outputs a Lo level, which turns ON the NMOS transistor Q 230  and turns OFF the NMOS transistor Q 231 . As a result, the output voltage Vout 1  (corresponding to twice the input voltage Vin 0 ) from the first-stage charge pump circuit  10  is applied to the charging capacitor C 21  as the boosting voltage. The output voltage Vout 2  of the output capacitor C 22  becomes four times the input voltage Vin 0 . This is the same as the voltage boosting operation of the charge pump circuit CP 2  shown in  FIG. 8 .  
         [0045]     On the other hand, if the monitor voltage is greater than the reference voltage Vref, the comparison circuit  15  outputs a Lo level. The AND circuit  20  thus outputs a Hi level and the AND circuit  21  outputs a Lo level, which turns ON the NMOS transistor Q 231  and turns OFF the NMOS transistor Q 230 . As a result, the input voltage Vin 0  is applied to the charging capacitor C 21  as the boosting voltage. The output voltage Vout 2  of the output capacitor C 22  becomes three times the input voltage Vin 0 .  
         [0046]     According to the first embodiment, depending on the input voltage level of the first-stage charge pump circuit, the second-stage charge pump circuit selects the boosting voltage added to the voltage-boosting basic voltage charged in the charging capacitor. Therefore, the boosting ratio of the output voltage can be changed according to the input voltage level. The charge-pump-type power supply circuit can thus directly receive the input voltage without stabilizing it, thereby preventing a reduction of the power supply efficiency. The change of the voltage boosting ratio of the output voltage is controlled in an opposite direction to the change of the input voltage level. The charge-pump-type power supply circuit can thus respond to the change of the input voltage without causing any problem with a withstand voltage of an element, which can contribute to a compact size of the circuit.  
         [0047]      FIG. 2  is a circuit diagram of a charge-pump-type power supply circuit according to a second embodiment of the present invention. In  FIG. 2 , the same or equivalent components as those shown in  FIG. 8  and  FIG. 1  are referred to by the same reference numerals.  
         [0048]     As shown in  FIG. 2 , the charge-pump-type power supply circuit according to the second embodiment includes a second-stage charge pump circuit  25  as a second-stage charge pump circuit instead of the second-stage charge pump circuit  11  shown in  FIG. 1 . The second-stage charge pump circuit  25  corresponds to the charge pump circuit CP 2  shown in  FIG. 8  in which the PMOS transistor Q 21  on the charging side is replaced by two PMOS transistors Q 210 , Q 211  connected in parallel.  
         [0049]     The output voltage Vout 1  from the first-stage charge pump circuit  10  is applied to a source of the PMOS transistor Q 210 . The input voltage Vin 0  is applied to a source of the NMOS transistor Q 211 .  
         [0050]     The charging control signal TC 1  is applied to the AND circuit  20 ,  21 . The AND circuit  20  provides an output that is applied via an inverter Q 521  to a gate of the PMOS transistor Q 211 . The AND circuit  21  provides an output that is applied via an inverter Q 522  to a gate of the PMOS transistor Q 210 . Other configurations are the same as shown in  FIG. 1 .  
         [0051]     The first-stage charge pump circuit  10  outputs twice the input voltage Vin 0  as the output voltage Vout 1  to the second-stage charge pump circuit  11 , as in the charge pump circuit CP 1  shown in  FIG. 8 .  
         [0052]     In the second-stage charge pump circuit  25 , during the discharging period with the discharge control signal TD 1  at a Hi level, the voltage boosting operation is performed in which the output-voltage Vout 1  of the first-stage charge pump circuit  10  is added to the voltage-boosting basic voltage charged in the charging capacitor C 21  during the charging period, to provide the output voltage Vout 2  as the boosting voltage, as in the charge pump circuit CP 2  shown in  FIG. 8 . However, the second-stage charge pump circuit  25  can select a boosting voltage added to the charging capacitor C 21  according to a level of the input voltage Vin 0 .  
         [0053]     If the monitor voltage of the input voltage Vin 0  is less than the reference voltage Vref, the comparison circuit  15  outputs a Hi level. The AND circuit  21  thus outputs a Hi level and the AND circuit  20  outputs a Lo level, which turns ON the PMOS transistor Q 210  and turns OFF the PMOS transistor Q 211 . As a result, the voltage-boosting basic voltage charged in the charging capacitor C 21  is the output voltage Vout 1  (corresponding to twice the input voltage Vin 02 ) from the first-stage charge pump circuit  10 . During the discharging period, the output voltage Vout 1  (corresponding to twice the input voltage Vin 0 ) from the first-stage charge pump circuit  10  is added to the voltage-boosting basic voltage as the boosting voltage. The output voltage Vout 2  of the output capacitor C 22  becomes four times the input voltage Vin 0 . This is the same as the voltage boosting operation of the charge pump circuit CP 2  shown in  FIG. 8 .  
         [0054]     On the other hand, if the monitor voltage is greater than the reference voltage Vref, the comparison circuit  15  outputs a Lo level. The AND circuit  20  thus outputs a Hi level and the AND circuit  21  outputs a Lo level, which turns ON the PMOS transistor Q 211  and turns OFF the PMOS transistor Q 210 . As a result, the voltage-boosting basic voltage charged in the charging capacitor C 21  is the input voltage Vin 02  from the first-stage charge pump circuit  10 . During the discharging period, the output voltage Vout 1  (corresponding to twice the input voltage Vin 0 ) from the first-stage charge pump circuit  10  is added to the voltage-boosting basic voltage as the boosting voltage. The output voltage Vout 2  of the output capacitor C 22  becomes three times the input voltage Vin 0 .  
         [0055]     According to the second embodiment, depending on the input voltage level of the first-stage charge pump circuit, the second-stage charge pump circuit selects the voltage-boosting basic voltage charged in the charging capacitor, to which the boosting voltage is added. Therefore, the voltage boosting ratio of the output voltage can be changed according to the input voltage level, as in the first embodiment, providing the same operational advantage as in the first embodiment.  
         [0056]      FIG. 3  is a circuit diagram of a charge-pump-type power supply circuit according to a third embodiment of the present invention. In  FIG. 3 , the same or equivalent components as those shown in  FIG. 1  are referred to by the same reference numerals.  
         [0057]     In the charge-pump-type power supply circuit according to the third embodiment, the voltage dividing circuit (R 1 , R 2 ) of the selection-signal generating circuit  12  monitors the output voltage Vout 1  of the first-stage charge pump circuit  10  instead of the input voltage Vin 0 .  
         [0058]     According to this configuration, the same operational advantage as in the first embodiment and the monitor voltage corresponds to twice the input voltage Vin 0  are provided, which can double the inversion accuracy of the comparison circuit in the selection-signal generating circuit  12 .  
         [0059]      FIG. 4  is a circuit diagram of a charge-pump-type power supply circuit according to a fourth embodiment of the present invention. In  FIG. 4 , the same or equivalent components as those shown in  FIG. 2  are referred to by the same reference numerals.  
         [0060]     In the charge-pump-type power supply circuit according to the fourth embodiment, the voltage dividing circuit (R 1 , R 2 ) of the selection-signal generating circuit  12  monitors the output voltage Vout 1  of the first-stage charge pump circuit  10  instead of the input voltage Vin 0 .  
         [0061]     According to this configuration, the same operational advantage as in the second embodiment and the monitor voltage corresponds to twice the input voltage Vin 0  are provided, which can double the inversion accuracy of the comparison circuit in the selection-signal generating circuit  12 .  
         [0062]      FIG. 5  is a circuit diagram of a charge-pump-type power supply circuit according to a fifth embodiment of the present invention. In  FIG. 4 , the same or equivalent components as those shown in  FIG. 1  are referred to by the same reference numerals.  
         [0063]     The second embodiment shows a configuration example of three or more stage charge pump circuits connected.  FIG. 5  shows a configuration corresponding to that shown in  FIG. 1  with a third-stage charge pump circuit  30  added. The selection-signal generating circuit  12  is replaced by a selection-signal generating circuit  31 . In addition, three of AND circuits  33 ,  34 , and  35  are employed as the selection circuit.  
         [0064]     The charge pump circuit  30  includes charging switches (PMOS transistor Q 31 , NMOS transistor Q 32 ) forming the charging path, discharging switches (NMOS transistor Q 330 , Q 331 , and Q 332 , and PMOS transistor Q 34 ) forming the discharging path, a charging capacitor C 31 , and an output capacitor C 32 .  
         [0065]     On the charging side of the charge pump circuit  30 , the output voltage Vout 2  from the previous-stage charge pump circuit  11  is applied to a source of the PMOS transistor Q 31 . A drain of the PMOS transistor Q 31  is connected to one electrode of the charging capacitor C 31 . A drain of the NMOS transistor Q 32  is connected to the other electrode of the charging capacitor C 31 . A source of the NMOS transistor Q 32  is connected to the ground. The charge control signal TC 1  is directly applied to a gate of the NMOS transistor Q 32 . The signal TC 1  is also applied via an inverter Q 53  to a gate of the PMOS transistor Q 31 .  
         [0066]     On the discharging side of the charge pump circuit  30 , drains of the NMOS transistors Q 330 , Q 331 , and Q 332  are connected together to the other electrode of the charging capacitor C 31 . The output voltage Vout 2  from the second-stage charge pump circuit  11  is applied to a source of the NMOS transistor Q 330 . The output voltage Vout 1  from the first-stage charge pump circuit  10  is applied to a source of the NMOS transistor Q 331 . The input voltage Vin 0  is applied to a source of the NMOS transistor Q 332 . A source of the PMOS transistor Q 34  is connected to the one electrode of the charging capacitor C 31 . An output capacitor C 32  is provided between the drain of the PMOS transistor Q 34  and the ground is an.  
         [0067]     The discharge control signal TD 1  output from the inverter Q 71  is applied to a gate of the PMOS transistor Q 34  via an inverter Q 63 , The output from the AND circuit  33  is applied to agate of the NMOS transistor Q 330 . The output from the AND circuit  34  is applied to a gate of the NMOS transistor Q 331 . The output from the AND circuit  35  is applied to a gate of the NMOS transistor Q 332 .  
         [0068]     The selection-signal generating circuit  31  is configured as shown in  FIG. 6 , for example, and generates five selection control signals S 1  to S 5  from the input voltage Vin 0  as the input voltage Vi. The selection control signals S 1  to S 5  are applied to each of one input ends of the AND circuits  20 ,  21 , and  33  to  35 , respectively. The discharge control signal TD 1  is applied to each of the other input ends of the AND circuits  20 ,  21 , and  33  to  35 .  
         [0069]      FIG. 6  is a circuit diagram of a selection-signal generating circuit shown in  FIG. 5 . The selection-signal generating circuit  31  includes four voltage-dividing circuits (R 1 , R 2 ), (R 3 , R 4 ), (R 5 , R 6 ), and (R 7 , R 8 ) to monitor the input voltage Vi in parallel, four comparison circuits  40 ,  42 ,  43 , and  44  to compare the corresponding monitor voltage and corresponding reference voltage Vref, and an inverter  41  that inverts the output of the comparison circuit  40 . The output of the inverter  41  is the selection control signal S 1 . The outputs of the comparison circuits  40 ,  42 ,  43 , and  44  are the selection control signals S 2 , S 3 , S 4 , and S 5 , respectively.  
         [0070]      FIG. 7  is a table for explaining a voltage boosting operation of the charge-pump-type power supply circuit shown in  FIG. 5 . The input voltage Vi of the selection-signal generating circuit  31  is the detected voltage of the input voltage Vin 0 . The input voltage Vi falls into four levels of the detected voltage Vdet 1  to Vdet 4 , as shown in  FIG. 7 . A relation between the detected voltages Vdet 1  to Vdet 4  is Vdet 1 &lt;Vdet 2 &lt;Vdet 3 &lt;Vdet 4 . The voltage range is set such as the levels of the selection control signals S 1  to S 5  are as follows.  
         [0071]     When the input voltage Vi is the detected voltage Vdet 1 , S 1  is at the Hi level, S 2  is at the Lo level, S 3  is at the Hi level, and S 4  and S 5  are at the Lo level. When the input voltage Vi is the detected voltage Vdet 2 , S 1  is at the Hi level, S 2  and S 3  are at the Lo level, S 4  is at the Hi level, and S 5  is at the Lo level. When the input voltage Vi is the detected voltage Vdet 3 , S 1  is at the Lo level, S 2  is at the Hi level, S 3  is at the Lo level, S 4  is at the Hi level, and S 5  is at the Lo level. When the input voltage Vi is the detected voltage Vdet 4 , then S 1  is at the Lo level, S 2  is at the Hi level, S 3  and S 4  are at the Lo level, and S 5  is at the Hi level.  
         [0072]     During the discharging period in which the discharge control signal TD 1  is at the Hi level, the output voltage Vout 1  of the first-stage charge pump circuit  10  is 2Vin0 corresponding to twice the input voltage Vin 0 , for the detected voltages Vdet 1  to Vdet 4 . For the detected voltages Vdet 1  to Vdet 4 , the voltage boosting operation of the charge pump circuits  11 ,  30  is as follows.  
         [0073]     When the input voltage Vi is equal to or larger than the detected voltage Vdet 1 , the AND circuit  20  outputs a Hi level, the AND circuit  21  outputs a Lo level, the AND circuit  33  outputs a Hi level, and the AND circuits  34 ,  35  output a Lo level. In the second-stage charge pump circuit  11 , the NMOS transistor Q 230  is turned ON, and in the charge pump circuit  30 , the NMOS transistor Q 330  is turned ON.  
         [0074]     In the second-stage charge pump circuit  11 , therefore, the boosting voltage of 2Vin0 is added to the voltage-boosting basic voltage of the charging capacitor C 21 , providing the output voltage Vout 2  of 4Vin0. The voltage 4Vin0 is the voltage-boosting basic voltage charged in the charging capacitor C 31  in the charge pump circuit  30 . The output voltage Vout 2 =4Vin0 is then added to the voltage 4Vin0, providing the output voltage Vout 3  of 8Vin0.  
         [0075]     When the input voltage Vi is equal to or larger than the detected voltage Vdet 2 , the AND circuit  20  outputs a Hi level, the AND circuit  21  outputs a Lo level, the AND circuit  33  outputs a Lo level, the AND circuit  34  outputs a Hi level, and the AND circuit  35  outputs a Lo level. In the second-stage charge pump circuit  114 , the NMOS transistor Q 230  is turned ON, and in the charge pump circuit  30 , the NMOS transistor Q 331  is turned ON.  
         [0076]     In the second-stage charge pump circuit  11 , therefore, the boosting voltage of 2Vin0 is added to the voltage-boosting basic voltage of the charging capacitor C 21 , providing the output voltage Vout 2  of 4Vin0. The voltage 4Vin0 is the voltage-boosting basic voltage which is charged in the charging capacitor C 31  in the charge pump circuit  30 . The output voltage Vout 1 =2Vin0 is then added to the voltage 4Vin0, providing the output voltage Vout 3  of 6Vin0.  
         [0077]     When the input voltage Vi is equal to or larger than the detected voltage Vdet 3 , the AND circuit  20  outputs a Lo level, the AND circuit  21  outputs a Hi level, the AND circuit  33  outputs a Lo level, the AND circuit  34  outputs a Hi level, and the AND circuit  35  outputs a Lo level. In the second-stage charge pump circuit  11 , the NMOS transistor Q 231  is turned ON, and in the charge pump circuit  30 , the NMOS transistor Q 331  is turned ON.  
         [0078]     In the second-stage charge pump circuit  11 , therefore, the boosting voltage of the input voltage Vin 0  is added to the voltage-boosting basic voltage of the charging capacitor C 21 , providing the output voltage Vout 2  of 3Vin0. The voltage 3Vin0 is the voltage-boosting basic voltage which is charged in the charging capacitor C 31  in the charge pump circuit  30 . The output voltage Vout 1 =2Vin0 is then added to the voltage 3Vin0, providing the output voltage Vout 3  of 5Vin0.  
         [0079]     When the input voltage Vi is equal to or larger than the detected voltage Vdet 4 , the AND circuit  20  outputs a Lo level, the AND circuit  21  outputs a Hi level, the AND circuit  33  outputs a Lo level, the AND circuit  34  outputs a Lo level, and the AND circuit  35  outputs a Hi level. In the second-stage charge pump circuit  11 , the NMOS transistor Q 231  is turned ON, and in the charge pump circuit  30 , the NMOS transistor Q 332  is turned ON.  
         [0080]     In the second-stage charge pump circuit  11 , the boosting voltage of the input voltage Vin 0  is added to the voltage-boosting basic voltage of the charging capacitor C 21 , providing the output voltage Vout 2  of 3Vin0. The voltage 3Vin0 is the voltage-boosting basic voltage which is charged in the charging capacitor C 31  in the charge pump circuit  30 . The input voltage Vin 0  is then added to the voltage 3Vin0, providing the output voltage Vout 3  of 4Vin0.  
         [0081]     According to the fifth embodiment, when the second-stage charge pump circuit can provide the boosting voltage of three or four times the input voltage, the third-stage charge pump circuit can provide the boosting voltage selected from the three voltage levels of the input voltage Vin 0 , the output voltage Vout 1  from the first-stage charge pump circuit, and the output voltage Vout 2  from the second-stage charge pump circuit. The third-stage charge pump circuit can thus output a voltage of four to eight times the input voltage Vin 0 .  
         [0082]     Note that although the fifth embodiment has been described with respect to an example of the application to the first embodiment, the fifth embodiment is also applicable to the second and the third embodiments. In this case, although both of the second- and the third-stage charge pump circuits may select the voltage on the charging side and discharging side, one circuit may select on the charging side, and the other circuit may select on the discharging side.  
         [0083]     As seen from the description of the fifth embodiment, four or more stage charge pump circuits connected can be configured with reference to the fifth embodiment.  
         [0084]     According to the first to the fifth embodiments, the selection-signal generating circuit uses the comparison circuit to make the selection control signal. The selection-signal generating circuit may have hysteresis characteristics, and may be any circuit that can detect the voltage.  
         [0085]     Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art that fairly fall within the basic teaching herein set forth.