Abstract:
A clock switching circuit has a clock output circuit and clock signal transfer circuits. The output circuit provides a selected clock signal. The transfer circuits receive input clock signals and select signals, and output transfer signals to the output circuit. Each of the transfer circuits includes a transmitting circuit, a generating circuit and a passing circuit. The transmitting circuit is connected to the output circuit, and receives the select signal and provides the received select signal responsive to the selected clock signal. The generating circuit is connected to the transmitting circuit, and provides an internal select signal responsive to the received select signal and the input clock signal. The passing circuit is connected to the generating circuit and the output circuit, and provides the input clock signal to the output circuit responsive to the internal select signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a clock switching circuit for dynamically switching a plurality of clocks. 
     2. Related Background Art 
     A clock switching circuit according to a second embodiment in Unexamined Japanese Patent Publication No. 2001-332961 is conventionally present as a circuit wherein no hazard accompanies an output clock signal when a plurality of clocks are switched. According to this conventional example, the technique disclosed is intended to prevent the occurrence of a hazard in the output when a plurality of clock signals are switched. 
     However, two types of clock signals can not be switched in the circuit disclosed in this publication unless these signals interact with each other. Thus, when this circuit is employed to cope with the switching of an increased number of clocks, such as three or four types, all the clocks must be repeatedly and simultaneously supplied to the circuit, and this constitutes a barrier that forestalls a reduction in the power consumption. 
     SUMMARY OF THE INVENTION 
     To resolve this problem, according to the present invention, a clock switching circuit has a clock output circuit and clock signal transfer circuits. The clock output circuit provides a selected clock signal. The clock signal transfer circuits receive input clock signals and select signals. The clock signal transfer circuits output transfer signals to the clock output circuit. Each of the clock signal transfer circuits includes a select signal transfer circuit, an internal select signal generating circuit and a clock signal passing circuit. The select signal transfer circuit is connected to the clock output circuit and receives one of the select signals, and provides the received select signal responsive to the selected clock signal. The internal select signal generating circuit is connected to the select signal transfer circuit, and provides an internal select signal responsive to the received select signal and one of the input clock signals. The clock signal passing circuit is connected to the internal select signal generating circuit and the clock output circuit, and provides the one of the input clock signals to the clock output circuit responsive to the internal select signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram showing the configuration of a clock switching circuit according to a first preferred embodiment of the present invention; 
         FIG. 2  is a time chart showing the operation of the circuits in  FIGS. 1 and 3 ; 
         FIG. 3  is a diagram showing the configuration of a clock switching circuit according to a second preferred embodiment of the present invention; 
         FIG. 4  is a diagram showing the configuration of a clock switching circuit according to a third preferred embodiment of the present invention; 
         FIG. 5  is a diagram showing the shifting of the state of internal select signals generated by a select signal generator in  FIG. 4 ; 
         FIG. 6  is a time chart showing the operation of the circuit in  FIG. 4 ; and 
         FIG. 7  is a time chart for when a plurality of signals sel are simultaneously selected. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A clock switching circuit according to the present invention will now be described in detail while referring to the accompanying drawings. 
     First Preferred Embodiment 
       FIG. 1  is a diagram showing the configuration of a clock switching circuit according to a first preferred embodiment of the present invention. In this configuration, three types of clocks, clk 1 , clk 2  and clk 3 , are switched. The clock switching circuit comprises: a three-input OR gate  101 ; two-input AND gates  102 - 1 ,  102 - 2  and  102 - 3 ; reset-input negative edge operational D flip-flops (hereinafter referred to as D-FFs)  103 - 1 ,  103 - 2  and  103 - 3 , which have terminals for an input signal D, a clock input CKN, an asynchronous reset signal RN and an output signal Q; and low through latches  104 - 1 ,  104 - 2  and  104 - 3 , which have terminals for an input signal D, a gate control signal GN and a gate output signal Q. 
     In the reset input negative edge operational D-FFs  103 - 1 ,  103 - 2  and  103 - 3 , the gate output signal Q is reset to 0 when the reset input signal RN is 0, and in synchronization with the fall of the clock input CKN, the input signal D is set using the gate output signal Q. 
     At the low through latches  104 - 1 ,  104 - 2  and  104 - 3 , when the gate control signal GN is 0, the input signal D is output unchanged by the gate output signal Q, and when the gate control signal GN is 1, the value of the gate output signal Q is maintained. 
     In  FIG. 1 , signals sel 1 , sel 2  and sel 3  are transmitted to the input signal terminals D of the low through latches  104 - 1 ,  104 - 2  and  104 - 3 , and an output clock signal clkout is transmitted to the gate control signal terminals GN. The gate output signals Q of the low through latches  104 - 1 ,  104 - 2  and  104 - 3  are transmitted to the terminals for the input signals D and the asynchronous reset signals RN of the D-FFs  103 - 1 ,  103 - 2  and  103 - 3 , and clock signals clk 1 , clk 2  and clk 3  are transmitted to the clock signal terminals CKN. 
     The gate output signals Q of the D-FFs  103 - 1 ,  103 - 2  and  103 - 3  are called isel 1 , isel 2  and isel 3 . The signals clk 1  and isel 1  are transmitted to the two-input AND gate  102 - 1 ; the signals clk 2  and isel 2  are transmitted to the two-input AND gate  102 - 2 ; and the signals clk 3  and isel 3  are transmitted to the two-input AND gate  102 - 3 . The output signals of the two-input AND gates  102 - 1 ,  102 - 2  and  102 - 3  are transmitted as input signals for the three-input OR gate  101 , and the output of the three-input OR gate  101  serves as a signal clkout. It should be noted that only one of the signals sel 1 , sel 2  and sel 3  is set to level 1 (1-out-of-3) and two or more signals are not set to level 1 at the same time. 
       FIG. 2 , a time chart for the operation of the circuit in  FIG. 1 , will now be referred to while an explanation is given for the operation of the circuit. First, while sel 1 =1 (effective when the clock signal clk 1  is selected), sel 2 =0 and sel 3 =0 are established, the clock signals clk 1  and clk 2  are in the operating state and the clock signal clk 3  is halted. In this state, since isel 1 =1 and isel 2 =isel 3 =0, only the two-AND gate  102 - 1  outputs the clock signal clk 1 , and the three-input OR gate  101  outputs this clock signal clk 1  as the signal clkout. Thereafter, the signal clkout is transmitted to the gate control signal terminals GN of the low through latches  104 - 1 ,  104 - 2  and  104 - 3 . 
     Then, when the above described state is shifted by a controller (not shown) to the state wherein sel 1 =0, sel 2 =1 (effective when the clock signal clk 2  is selected) and sel 3 =0, clkout=0 is established for the state wherein clk 1 =0. Further, the output of the low through latch  104 - 1  is set to 0, and the asynchronous reset input RN of the D-FF  103 - 1  is set to 0, so that the state is shifted to isel 1 =0. Since this change is performed during the period wherein clk 1 =0, so long as this period is not shorter than the period wherein the state is changed from clk 1 =0 to clkout=0 to isel 1 =0, the signal clkout is not output during the period for the next clk 1 . Furthermore, since the state is not changed to isel 1 =0 during the period wherein clk 1 =1, the period for clkout=1, which is output during the last clk 1  period, will not be reduced. Thus, no hazard will accompany the signal clkout. 
     The signal isel 2  is set to level 1 when the signal clkout is 0, the gate output signal Q of the low through latch  104 - 2  is 1, the input signals D of the D-FFs  103  are 1, and the signal clk 2  falls thereafter. Since the signal clkout=0 is established before isel 2 =1 is set, and is maintained during the period wherein clk 2 =0, even after isel 2 =1 is established, the period, at the clock switching time, wherein clkout=0 will not be shorter than the period wherein clk 2 =0, and no hazard is produced. Then, when the clock signal clk 2  rises, the signal isel 2 =1 is established. So long as the period wherein clk 2 =0 is not extremely short, the state wherein isel 2 =1 is established before the clock signal clk 2  rises, so that the period wherein clkout=1 will not be shorter than the period wherein clk 2 =1 and no hazard accompanies the signal clkout. Thus, the operation is not adversely affected even when the clock clk 3  is halted during the switching from clk 1  to clk 2 . 
     In this embodiment, only one of the three types of clock signals is selected and changed. Therefore, two or more of the signals sel 1 , sel 2  and sel 3  are not set to 1 at the same time. 
     As is described above, according to the embodiment, the following effects are obtained. 
     (1) The clocks can be switched without a hazard being produced. 
     (2) Since even when clocks other than a target clock are halted the clock switching operation is not adversely affected, power consumption can be reduced. 
     (3) Since a regular structure is employed, the number of clocks to be switched can be easily increased. 
     (4) Clock select signals can be switched at an arbitrary timing. 
     Second Preferred Embodiment 
       FIG. 3  is a diagram showing the configuration of a clock switching circuit according to a second preferred embodiment of the present invention. The clock switching circuit for this embodiment comprises: three-input OR gates  201  and  206 ; two-input AND gates  202 - 1 ,  202 - 2  and  202 - 3 ; asynchronous reset D-FFs  203 - 1 ,  203 - 2  and  203 - 3 ; and low through latches  204 - 1 ,  204 - 2 ,  204 - 3 ,  205 - 1 ,  205 - 2  and  205 - 3 . The D-FFs and the low through latches are the same as those used for the first embodiment. 
     For the D-FFs  203 - 1 ,  203 - 2  and  203 - 3 , gate output signals Q are reset to 0 when reset input signals RN are 0, and in synchronization with the fall of input clock signals CKN, the values of input signals D are set for output. For the low through latches  204 - 1 ,  204 - 2 ,  204 - 3 ,  205 - 1 ,  205 - 2  and  205 - 3 , input signals D are output unchanged when gate control signals GN are 0, while the values of gate output signals Q are maintained when the gate control signals GN are 1. 
     Signals sel 1 , sel 2  and sel 3  are transmitted to the terminals for the input signals D of the low through latches  205 - 1 ,  205 - 2  and  205 - 3 , and input clock signals clk 1 , clk 2  and clk 3  are transmitted to the gate control signal terminals GN. The gate output signals Q of the low through latches  205 - 1 ,  205 - 2  and  205 - 3  are transmitted to the input signal terminals D of the low through latches  204 - 1 ,  204 - 2  and  204 - 3 , and the output of the three-input OR gate  206  is transmitted to the gate control signal terminals GN. 
     The gate output signals Q of the low through latches  204 - 1 ,  204 - 2  and  204 - 3  are transmitted to the input signal terminals D of the D-FFs  203 - 1 ,  203 - 2  and  203 - 3 . The gate output signals Q of the low through latches  205 - 1 ,  205 - 2  and  205 - 3  are transmitted to the asynchronous reset signal terminals RN, and the clock signals clk 1 , clk 2  and clk 3  are transmitted to the clock signal terminals CN. The gate output signals Q are called isel 1 , isel 2  and isel 3 . 
     The signals clk 1  and isel 1  are transmitted to the input terminals of the two-input AND gate  202 - 1 , the signals clk 2  and isel 2  are transmitted to the input terminals of the two-input AND gate  202 - 2 , and the signals clk 3  and isel 3  are transmitted to the input terminals of the two-input AND gate  202 - 3 . The output signals of the two-AND gates  202 - 1 ,  202 - 2  and  202 - 3  are transmitted to the input terminals of the input terminals of the three-input OR gate  201 , and the output signal of the three-input OR gate  201  serves as an output clock signal clkout. The signals isel 1 , isel 2  and isel 3  are transmitted to the input terminals of the three-input OR gate  206 , and the output signal of the three-input OR gate  206  is transmitted to the gate control signal terminals GN of the low through latches  204 - 1 ,  204 - 2  and  204 - 3 . 
     Each signal sel 1 , sel 2  or sel 3  is a clock select signal, which is a 1-out-of-3 signal such that only one of the signals can have a value of 1 at one time. 
     The operation of the clock switching circuit in  FIG. 3  will now be described. Since the operating time chart for this circuit is the same as that in  FIG. 2 , the time chart in  FIG. 2 , is employed for explaining the operation. 
     First, while sel 1 =1, sel 2  =0 and sel 3 =0 are established, the clock signals clk 1 , clk 2  and clk 3  are received at respective timings. Since in this state isel 1 =1, isel 2 =0 and isel 3 =0, the two-input AND gates  202 - 1 ,  202 - 2  and  202 - 3  and the three-input OR gate  201  constitute a multiplexer, which selects the clock signal clk 1  and outputs it to the terminal clkout. 
     When the state is shifted to sel 1 =0, sel 2 =1 and sel 3 =0, while during the period wherein clk 1 =0, the gate output signal Q of the low through latch  205 - 1  is changed to 0, as is the reset input signal RN of the D-FF  203 - 1 , so that the state is shifted to isel 1 =0. This change is performed during the period wherein clk 1 =0, so long as this period is not shorter than the delay for the low through latch  205 - 1  and the delay during which the D-FF  203 - 01  is reset. Therefore, the next clock signal clk 1  will not be output to the terminal clkout. Further, since the state is not changed to isel 1 =0 during the period wherein clk 1 =1, the period wherein clkout=1, which is output during the last period wherein clk 1 =1, is not reduced. Thus, no hazard accompanies the signal clkout. 
     The signal isel 2 =1 is established when clk 2 =0 is temporarily established, the gate output signal Q of the low through latch  205 - 2  is changed to level 1, all the signals isel 1 , isel 2  and isel 3  are set to 0, the output of the three-input OR gate  206  is set to 0, the gate output signal Q of the low through latch  204 - 2  is set to 0, and thereafter, the signal clk 2  falls. Since the signal clkout of 0 has already been output before isel 2 =1 is established, and since clkout=0 is maintained during the period wherein clk 2 =0, even after the state is changed to isel 2 =1, the period, at the clock switching time, wherein clkout=0 will not be shorter than the period wherein clk 2 =0, and no hazard is produced. Since isel 2 =1 is established when clk 2  falls, the period wherein clkout=1 is not shorter than the period wherein clk 2 =1, and no hazard accompanies the signal clkout. The clock signal clk 3  may be halted while the clock signal clk 1  is switched to the clock signal clk 2 , because the signal clk 3  does not adversely affect the operation. 
     When the correct input condition (1-out-of-3) for the signals sel 1 , sel 2  and sel 3  is not satisfied, and a plurality of these signals sel are simultaneously set to 1, as is shown in  FIG. 3 , sel 1 =1, sel 2 =0 and sel 3 =0 and isel 1 =1, isel 2 =0 and isel 3 =0 are established. Even when sel 2  and sel 3  are changed to 1 while the clock signal clk 1  is selected, the output of the three-input OR gate  206  is 1, so that the gate output signals Q of the low through latches  204 - 2  and  204 - 3  are maintained as 0. Therefore, the signals isel 2  and isel 3  do not change to 1, and the clock signal clk 2  or clk 3  is not included in the signal clkout. This is compensated for so long as a plurality of the clock select signals sel 1 , sel 2  and sel 3  are not 0 when all the clocks have not been selected, i.e., isel 1 =0, isel 2 =0 and isel 3 =0 is established. 
     As is described above, according to the second embodiment, in addition to the effects obtained in the first embodiment, even when the clock select signal does not correspond to the 1-out-of-3 condition, the output of an abnormal clock does not occur so long as two or more select signals are not effective at the same time when all the clocks are not selected. 
     Third Preferred Embodiment 
       FIG. 4  is a diagram showing the configuration of a clock switching circuit according to a third preferred embodiment of the present invention. This diagram is a circuit diagram that is more generalized than are those in  FIGS. 1 and 3 . According to this circuit, input clocks are clk 1 , clk 2  and clk 3 , internal select signals are isel 1 , isel 2  and isel 3 , and an output clock is clkout. A select signal generator  303  receives a timing signal and a clock select signal, and generates internal select signals. 
     The clock switching circuit for this embodiment comprises: a three-input OR gate  303 , and two-input AND gates  302 - 1 ,  302 - 2  and  302 - 3 . The two-input AND gates  302 - 1 ,  302 - 2  and  302 - 3  respectively receive the clock signals clk 1 , clk 2  and clk 3  and the internal select signals isel 1 , isel 2  and isel 3 , and transmit the output signals to the three-input OR gate  301 . The output of the three-input OR gate  301  serves as the output clock clkout. 
     The internal select signal (isel 1 , isel 2 , isel 3 ) can be either a 1-out-of-3 signal of (1, 0, 0), (0, 1, 0) or (0, 0, 1), or the initial state (0, 0, 0), wherein all the signals are 0, and this state change is shown in FIG.  5 . 
     As is shown in  FIG. 5 , only when the clock signals clk 1 , clk 2  and clk 3  are falling can the state (initial state) of (isel 1 , isel 2 , isel 3 )=(0, 0, 0) be changed to each of the states (1, 0, 0), (0, 1, 0) and (0, 0, 1). Further, only when clk 1 =0 is established can the state (isel 1 , isel 2 , isel 3 )=(1, 0, 0) be changed to isel 1 =0. Similarly, only when clk 2 =0 can the state (0, 1, 0) be changed to isel 2 =2, and only when clk 3 =0 can the state (0, 0, 1) be changed to isel 3 =0. 
     The select signal generator  303  employs the timing signal and the clock select signal to generate the internal select signals isel 1 , isel 2  and isel 3  that satisfy the above condition. The timing signals correspond to the signals clk 1 , clk 2 , clk 3  and clkout in the first embodiment, or the signals clk 1 , clk 2  and clk 3  and the output of the three-input OR gate  206  that receives the signals isel 1 , isel 2  and isel 3  in the second embodiment. It should be noted, however, that these are merely examples, and another combination of signals may be employed. Furthermore, while the clock select signals sel 1 , sel 2  and sel 3  are used in the first and second embodiments, these are not always 1-out-of-3 signals. 
       FIG. 6  is a time chart for the operation of the clock switching circuit in FIG.  4 . The operation of the clock switching circuit in  FIG. 4  will now be described while referring to FIG.  6 . 
     First, in the state wherein (isel 1 , isel 2 , isel 3 )=(1, 0, 0), the clock signals clk 1 , clk 2  and clk 3  are received at the individual timings. In this state, the two-input AND gates  302 - 1 ,  302 - 2  and  302 - 3  and the three-input OR gate  301  constitute a multiplexer, which selects the signal clk 1  and outputs it to the terminal clkout. 
     The clock signal is changed from the signal clk 1  to clk 2 , and the select signal generator  303  shifts isel 1  to 0 during the period wherein clk 1  is 0. Since this shifting is performed during the period wherein clk 1 =0, the next clk 1 =1 is not output to the terminal clkout so long as between the select signals there are no great delay differences. Further, the period wherein clkout=1, which is output in the last period of clk 1 , is not reduced. Therefore, no hazard accompanies the output clock clkout. In this manner, the state (0, 0, 0) is obtained in the internal state shifting diagram. 
     The select signal generator  303  sets isel 2  to 1 when the falling of the signal clk 2  occurs once or more after all the clocks have not been selected. As a result, the period wherein clkout=0 at the clock switching time will not be shorter than the period wherein clk 2 =0, and no hazard is produced. Then, when the signal clk 2  falls, isel 2 =1 is established, and since isel 2 =1 is set before the signal clk 2  rises, so long as the period wherein clk 2 =0 is not extremely short, the period wherein clkout=1 will not be shorter than the period wherein clk 2 =1, and no hazard will accompany the clock clkout. The signal clk 3  may be halted during the period wherein the signal clk 1  is switched to clk 2  because the signal clk 3  does not adversely affect the operation. 
     As is described above, according to the effects obtained by the third embodiment, (1) the clocks can be switched without a hazard occurring, and (2) a clock other than the clocks to be switched can be halted. 
     The present invention is not limited to these preferred embodiments, and can be variously modified based on the subject of the invention. For example, in the third embodiment, other gates, such as NAND gates, may be used to replace the three-input OR gate and the two-input AND gates. 
     Further, the clocks have been switched in the state wherein clkout=0. But when the three-input OR gate  301  is replaced with an AND gate, the two-input AND gates  302  are replaced with OR gates, and the internal select signals isel 1 , isel 2  and isel 3  are changed to 2-out-of-3 signals of (0, 1, 1), (1, 0, 1) or (1, 1, 0), or signals of (1, 1, 1), the clocks can be switched in the state wherein clkout=1. 
     In addition, although only three types of clocks have been employed for the first to third embodiment, an arbitrary number of clocks may be employed.