Abstract:
Method and system for developing low noise bandgap references. A stacked ΔV BE  generator is disclosed for generating ΔV BE . The stacked ΔV BE  generator includes an error amplifier configured to generate an output based on an error signal provided by a first stack of the ΔV BE  generator. The first stack of the ΔV BE  is coupled to a first sub-circuit and the error amplifier to form a closed loop. The first sub-circuit is coupled to a power supply and ground and configured to provide a source current between the power supply and the ground. The stacked ΔV BE  generator also includes a second sub-circuit coupled to the output of the error amplifier, the first and second stacks, and the ground, as well as a second stack of the ΔV BE  generator, which is coupled to the first stack and the second sub-circuit. The ΔV BE  is measured at outputs of the first and second stacks and equals the sum of individual ΔV BE s of the first and second stacks.

Description:
BACKGROUND 
     1. Technical Field 
     The present teaching is related to analog circuit design. More specifically, the present teaching is related to a method of and system for low noise bandgap reference circuit and systems incorporating the same. 
     2. Discussion of Technical Background 
     Bandgap voltage references are generally produced by summing a Proportional To Absolute Temperature (PTAT) voltage and a Complementary To Absolute Temperature (CTAT) voltage together to generate a temperature independent voltage. A CTAT voltage can be produced using a diode or diode connected Bipolar Junction Transistor (BJT). A PTAT voltage can be produced by developing a voltage across a resistor with a PTAT current. 
     A ΔV BE  circuit may be employed to generate a PTAT current using two BJTs with different current densities. The PTAT current used is usually proportional to the logarithm of the current density ratio of the two BJTs and can be mathematically described as I PTAT =ΔV BE /R=(V T /R)*ln(J 1 /J 2 ). The logarithm function attenuates the ratio, making it necessary to use a large number of transistors in order to achieve a higher performance bandgap voltage reference. 
     A different approach of producing a large ΔV BE  is to employ a “cross-connected quad”, illustrated in  FIG. 1 . In this illustrated cross-connected quad circuit  100 , transistors  120  and  150  have multiple emitters, each having a ratio of N and M, respectively. Transistor  120  is coupled to a power source at the collector via a resistor  110  and the multiple emitters of  120  are coupled to the ground via a transistor  130 . Specifically, the emitters of transistor  120  are connected in series to the collector of transistor  130 , whose emitter is connected to the ground. In addition, the collector of transistor  120  is connected to its base. 
     On the other side, transistor  150  is coupled to a source of PTAT at the emitter terminal via a transistor  140 . The collector of transistor  150  is connected to the single emitter of transistor  140  and the collector of transistor  140  is connected to the source of PTAT. The base of transistor  140  is directly connected to the base of transistor  120 , which is connected to its own collector. Transistor  150  is coupled to the ground at its emitter via a serially connected resistor  160 . The collector of transistor  150  is connected to the base of transistor  130 . 
     In this illustrated circuit, a ΔV BE  is developed that is proportional to the logarithm of the product of the ratio of emitter current densities. Specifically, the ΔV BE  can be characterized to be ΔV BE =V T *ln[(J 2 *J 3 )/(J 1 *J 4 )] or ΔV BE =V T *ln[(N*M)], where N and M are the current density ratios of transistor  120  to transistor  140  and transistor  150  to transistor  130 , respectively. It is clear that to achieve a larger ΔV BE , it is more efficient to use a method that incorporates a product of current density ratios. 
     There are other conventional approaches to bandgap cell design, including the Widlar cell, Brokaw cell, and Dobkin cell. A Dobkin cell is described in detail in U.S. Pat. No. 4,447,784 and depicted in  FIG. 2 . Circuit  200  in  FIG. 2  comprises an error amplifier  250  having its output coupled to a serially connected circuit, having two resistors R 3   255  and R 4   260  and a diode connected transistor Q 3   265 . The inputs of the error amplifier  250  are connected to the collectors of a pair of transistors Q 1   230  and Q 2   245 . The bases of transistors  230  and  245  are connected to the two ends of resistor R 3   255 , where the ΔV BE  is developed. The collectors of transistors Q 1  and Q 2  are coupled to a power source via, respectively, two resistors R 1   225  and R 2   240 . The emitters of transistors Q 1  and Q 2  are coupled together and connected to the collector of transistor Q 5   235 , whose emitter is connected to the ground. Between the power source and the ground, there is a serially connected sub-circuit, comprising a current source  215  and a serially connected diode connected transistor  220  having its collector connected to the current source  215  and its emitter connected to the ground. 
     As can be seen in  FIG. 2 , unlike Widlar and Brokaw cells which develop the ΔV BE  between the emitters of a BJT, the Dobkin cell develops the ΔV BE  between the bases of Q 1  and Q 2 . A voltage loop is formed around R 3  and the emitter-base junctions of Q 1  and Q 2 . 
     Mathematically, the ΔV BE  produced by the Dobkin cell is described as ΔV BE =V T *ln(J 2 /J 1 ). In this expression, V T =kT/q is the thermal voltage with k being the Boltzman&#39;s constant (1.38*10 −23  Joules/Kelvin), T an absolute temperature in Kelvin, and q an electronic charge (1.602*10 −19  Coulomb). J 1  and J 2  are the current densities of transistors Q 1  and Q 2 , respectively. Such a current density is dependent on transistor area A and the magnitude of current I going through the collector of the transistor. Accordingly, the ΔV BE  is proportional to J 2 /J 1 =(I 2 *A 1 )/(I 1 *A 2 ). Based on this observation, it can be seen that a design of a ΔV BE  generator can include appropriate ratios of either current or the area. When the current flowing through both transistors is identical, the emitter areas become the only factor that will determine the value of ΔV BE =V t *ln(A 1 /A 2 ). 
     In some prior art solutions, the error amplifier  250  is implemented based on a circuit shown in  FIG. 3  (PRIOR ART). In this illustration, the error amplifier  250  comprises 6 transistors,  350 ,  355 ,  360 ,  365 ,  370 , and  375 , connected as shown in  FIG. 3 . With this circuit  300 , when there are N emitters in Q 1  creating a N:1 ratio, ΔV BE  can be characterized to be ΔV BE =V t *ln(N). The output voltage of a Dobkin cell as shown in  FIG. 3  is:
 
 V   OUT =(1 +R   4   /R   3 )* V   T *ln( N )+ V   BE3  
 
This voltage loop forces the error amplifier to drive a PTAT current into resistor R 3 , R 4 , and transistor  265  whose sum of voltage drops develops the bandgap output voltage. Note that the above circuit is a series voltage reference and Dobkin&#39;s original circuit is a shunt voltage reference.
 
     It can be seen that to achieve a larger ΔV BE , a large ratio N of transistors is needed and, hence, a larger die area. In general, the higher the ratio N, the larger the die area. A larger die area costs more. When a ΔV BE  for a high performance bandgap voltage reference is needed, the cost may become a serious concern. For example, a reasonable ΔV BE  for a high performance bandgap voltage reference is about 108 mV at 25° C. Without stacking as in  FIG. 1 , this would require a ratio of about 64:1 or 65 transistors. Although conventional stacking solutions exist with a “cross-connected quad” approach as shown in  FIG. 1 , there are other issues that hinder the successful application of conventional stacking solutions. For instance, for each BJT stacked upon another, an additional 0.8V input voltage needs to be added and, thus, introduces the need for a higher input voltage. In addition, there are other negative effects, including a higher level of noise and sometimes unstable circuit behavior. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The inventions claimed and/or described herein are further described in terms of exemplary embodiments. These exemplary embodiments are described in detail with reference to the drawings. These embodiments are non-limiting exemplary embodiments, in which like reference numerals represent similar structures throughout the several views of the drawings, and wherein: 
         FIG. 1  (Prior Art) illustrates a circuit with a cross-connected quad; 
         FIG. 2  (Prior Art) illustrates a Dobkin bandgap reference cell; 
         FIG. 3  (Prior Art) illustrates a Dobkin bandgap reference cell with an implemented error amplifier; 
         FIG. 4  depicts a stacked Dobkin AVBE cell, according to an embodiment of the present teaching; 
         FIG. 5  depicts a stacked Dobkin AVBE cell, according to a different embodiment of the present teaching; 
         FIG. 6  depicts a triple stacked Dobkin AVBE cell, according to an embodiment of the present teaching; and 
         FIGS. 7-10  depict different implementations of a stacked Dobkin AVBE cell, according to different embodiments of the present teaching. 
     
    
    
     DETAILED DESCRIPTION 
     The present teaching relates to an improved apparatus and method for generating a large ΔV BE  without using a large number of transistors and without increasing the input voltage beyond that of a non-stacked bandgap cell. Consequently, ΔV BE  can be increased without consuming a large die area. In addition, the present teaching also aims at enhancing the performance of bandgap references via increasing the voltage of a ΔV BE  generator with reduction in bandgap output voltage noise. 
     In accordance with the present teaching, to reduce the number of transistors used in producing a larger ΔV BE , stacking is applied. For instance, to produce a ΔV BE  of 108 mV at 25° C., two stacks each having an 8:1 ratio can be used. Therefore, a total of 18 transistors can achieve the same level of performance as 65 transistors used in the prior art. This yields a significant reduction of transistors used, which provides exponential reduction in the number of transistors. 
     Although prior art solutions also adopt stacking, the present teaching stacks multiple ΔV BE s in a manner that does not increase noise, but rather decreases noise, and no additional input voltage beyond that of a non-stacked architecture is required. That is, the same input voltage required for a single ΔV BE  stack is used for a ΔV BE  generator with multiple stacks with the same ΔV BE  voltage. Using a similar example as discussed previously, without stacking, to achieve a ΔV BE  of 216 mV, a ratio of 2191:1 transistors would be required. In accordance with the stacking approach disclosed herein, four stacks each having an 8:1 ratio can be used to achieve 216 mV of ΔV BE  with the same input voltage. In other words, theoretically 36 transistors could achieve the same level of performance as 2192 transistors without increasing the input voltage and still minimizing the noise. 
     The present teaching is illustrated in  FIG. 4  having stacking shown with respect to a Dobkin cell. As shown, a stacked bandgap reference circuit  400  comprises two levels of ΔV BE  generators. The stacked bandgap reference circuit  400  comprises an error amplifier  465 , a current source path (a current source  415  and a diode connected transistor  420 ), a sub-circuit connecting between the output of the error amplifier V OUT  and the ground (resistors R 3 A  470 , R 3   475 , R 4   480 , and Q 3   485 ), a first stack (transistors  430 ,  435 , and  445 ) and a second stack (transistors  450 ,  455 , and  460 ). 
     Although prior art may also stack ΔV BE S, the present teaching stacks additional ΔV BE S in a way so that no additional input voltage is needed beyond that of a non-stacked bandgap cell. Moreover the stacking occurs where the ΔV BE  resistor is between the base terminal of the BJTs. To increase ΔV BE , the illustrated embodiment shows that the first level of ΔV BE  can be directly supplemented by adding a resistor, shown as R 3 A  470 , on top of the existing resistor, R 3   475 , and an additional emitter ratioed differential pair  450  and  455  with both emitters connected to transistor  460  to the ground. It is understood that although the illustrated embodiment applies stacking in the context of the Dobkin cell, the present teaching is not limited to such a particular context. 
     In some embodiments, identical stages may be employed. That is, the tail current sources Q 5    435  and Q 6    460  are identical. The ΔV BE  generators, Q 1    430 /Q 2   445  and Q 1A    450 /Q 2A    455 , also have identical current density ratios, say N. The current density ratio can be set by varying the emitter areas, the currents, or both in the corresponding ΔV BE  devices. Consider a Dobkin cell where a ΔV BE  generator comprises Q 1 , Q 2 , and R 3 . An expression to describe the circuit by going around a closed loop containing these devices is
 
 V   BE1   +V   BE2   +V   R3 =0
 
where V R3  is the voltage drop across R 3   475  and V BE1  and V BE2  are the emitter base voltages of devices Q 1    430  and Q 2    445 , respectively. As one skilled in the art of bandgap reference design would recognize,
 
 V   BE   =V   T *ln( I   C /( I   S   *A ))
 
where V T  is the thermal voltage, I c  is the collector current, I S  is the saturation current, and A is the emitter area. The argument of the natural logarithm term is called the current density as earlier denoted as J. The voltage across R 3  is given by the expression V R3 =I 1 *R 3 , where I 1  is the current through R 3 . Combining the natural logarithm terms discussed above, this equation becomes
 
 I   1   =V   T   /R   3 *ln( N )
 
where N is the current density ratio of devices Q 1    430  and Q 2    445 .
 
     When stacking is applied in a manner as disclosed herein, the expression for V OUT  can be similarly derived. Referring to  FIG. 4  where a stacked Dobkin cell is shown, based on the closed loop formed by different devices, V OUT  can be expressed as
 
 V   OUT   =V   R3A   +V   R3   +V   R4   +V   BE3  
 
Assuming that the base currents of Q 1 , Q 2 , Q 1 A, Q 2 A can be ignored, this expression can be rewritten as
 
 V   OUT =*( R   3A   +R   3   +R   4 )+ V   BE3  
 
Where I 1  is the current in resistor R 3A    470 , R 3    475 , R 4    480 , and Q 3    485  without the base currents. Considering the closed loop containing the two stacked ΔV BE  generators, we have
 
 V   R3A   +V   R3   +V   BE1   −V   BE2   +V   BE1A   −V   BE2A =0
 
Solving for the current I 1  yields
 
 I   1   =V   T /( R   3A   *R   3 )*ln( N   2 ).
 
Substituting the previous equation, we can derive the expression for V ouT  as follows
 
 V   OUT =(1 +R   4 /( R   3A   +R   3 ))* V   T *ln( N   2 )+ V   BE3  
 
In this expression, the first term corresponds to the PTAT term and the second term corresponds to the CTAT term. The natural logarithm term includes an exponent denoting the multiplying effect of stacking two ΔV BE  generators.
 
     By mathematical operation, the exponent in the natural logarithm term can be moved to the front of the PTAT term, making clear the multiplicative effect of the stacking described herein. That is
 
 V   OUT =2*(1 +R   4 /( R   3A   +R   3 ))* V   T *ln( N )+ V   BE3 .
 
The effect of the added stage is apparent in this derived equation where the PTAT term is doubled. Therefore, by stacking ΔV BE  generators in accordance with the present teaching described herein, the efficient multiplicative effect makes it possible to have much less die area to achieve the same result. In addition, the stacking as described herein does not need additional larger input voltage, as many architectures that achieve a multiplying effect of current densities would require.
 
     The required increase of input voltage for the present teaching is directly proportional to the increase in ΔV BE  as would be for a non-stacked architecture such as a Widlar or Brokaw cell. This is usually on the order of 100 mV. For example, if a 100 mV ΔV BE  is desired, using an architecture without stacking, a current density ratio of 48:1 is required. This in turn requires a total of 49 transistors. With our embodiment using two identical stages the same ΔV BE  can be developed using a current density ratio of 7:1 for a total of 16 transistors. 
     When additional increase in ΔV BE  is needed, more stages can be added as shown in  FIG. 5  where a triple stacked Dobkin cell is illustrated, according to an embodiment of the present teaching. With three stacked ΔV BE  generators, the expression for the output voltage is
 
 V   OUT =(1 +R   4 /( R   3B   +R   3A   +R   3 ))* V   T *ln( N   3 )+ V   BE3 , or
 
 V   OUT =3*(1 +R   4 /( R   3B   +R   3A   +R   3 ))* V   T *ln( N )+ V   BE3  
 
Generally, there is no inherent limit to the number of stages that can be stacked in accordance with the present teaching. When there are K stages stacked together, assuming K identical stages each having current density ratio N:1, a general expression for the output voltage can be derived as
 
 V   OUT   =K *(1 +R   4 /( K*R   3 ))* V   T *ln( N )+ V   BE3  
 
It is clear that the natural logarithm of the product of transistor ratios increases exponentially with respect to a conventional bandgap without a stacked ΔV BE  generator.
 
     The above discussion assumes that R 3 =R 3A =R 3B  . . . and the emitter ratios, N, of the differential pairs are perfectly identical. In practice due to mismatches in manufacturing, this will not be the case. However, the current ratio in the differential pairs will be close enough to dynamically adjust so that the PTAT current through R 3  is equal to the PTAT current through R 3A . 
     As discussed herein, the stacking according to the present teaching also reduces noise. Specifically, noise reduction is achieved by breaking up the ΔV BE  cell into multiple devices. When they are broken up, the noise in separate devices are uncorrelated, making the total noise a combination of RSS (root-sum-square) and, thus, smaller. As someone skilled in the art of analog design would recognize, devices at the input of the amplifier (e.g., error amplifier  465  in  FIG. 4  and error amplifier  580  in  FIG. 5 ) are usually the dominate contributors to noise. In some embodiments, such noise may be reduced by increasing the current density ratio, N. This reduces the noise because it lowers the gain required in the PTAT term. 
     In this embodiment, the emitter current density can be made arbitrarily large without much cost in the die area resulting in less gain needed. In addition, the overall PTAT resistance from various resistors, e.g., R 3A , R 3B B, . . . , is now broken up into several individual pieces. In a single stage ΔV BE  generator, the noise with respect to this overall resistance is 4kTRB, where k is Boltzman&#39;s constant, T is temperature in Kelvin, R is the resistance, and B is the bandwidth. That is, when a single stage is used, the noise is a combination of the noise sources from that stage. When stacking as disclosed herein is applied (e.g., three stage stacking), since the overall PTAT resistor is broken up into several individual pieces in corresponding stacks, the resulting overall noise is root, sum, squared (RSS) together as an overall resistance. This is shown in the equation below
 
 E   nT =( E   R3   2   +E   R3A   2   +E   R3B   2 ) 1/2  
 
where E nT  is the total noise level and E R3 , E R3A , E R3B  are the noise sources from the three individual ΔV BE  generators.
 
     Particularly, when identical stages are stacked, the total noise combined is determined by E′ n =E n /√N, where E n  is the noise from each stage and N is the number of stages. Thus, the total noise level of the stacked ΔV BE  generator is √N times less than that of each of the individual stages. 
     The above discussion is based on specific exemplary embodiments. Although not limiting, it is understood that there are various implementations that may be employed to realize the present teaching. For instance, in  FIG. 4  and  FIG. 5 , the circuit bias currents  415  and  515  are shown coming from a current source. This bias current can also be realized as a resistor. In addition, the current source could be temperature independent, PTAT, CTAT, or some other variations. The tail current sources, e.g., transistors Q 5  and Q 6  in  FIG. 4  and Q 7  in  FIG. 5  can be identical or set to have different values. The emitter ratios or current density of the ΔV BE  generators Q 1 /Q 2 , Q 1A /Q 2A , and Q 1B /Q 2B , can be identical or set to different ratios. The resistors R 3 , R 3A , and R 3B , can be identical or set to different values. The collector resistors, R 1  and R 2 , can be identical or set to different values. 
     The discussion above with respect to stacking is based on the assumption that the base current is ignored. Consider the double stacked Dobkin cell (shown in  FIG. 4 ). A source of output voltage error may occur due to the base currents flowing through transistors Q 1    430 , Q 2    445 , and Q 1A    450 . The current from the error amplifier  465  that reaches resistor R 3    475  is 2*I B  (combined base currents of transistors Q 1A    450  and Q 2    445 ) less than the current flowing through transistor R 3A    470 . It reduces by another I B  (base current of Q 1    430 ) when the current gets to resistor R 4    480  and transistor Q 3    485 . These base currents vary with temperature causing a temperature dependent error which detracts from the temperature independent circuit. 
     When base current is taken into account in the analysis, it can be shown that in addition to the ideal output voltage terms PTAT and CTAT, an error due to base currents exists. To eliminate this error,  FIG. 6  illustrates an exemplary solution. Circuit  600  as shown in  FIG. 6  includes all similar components as in  FIG. 4  with an additional resistor, R 5    657 , inserted between V OUT  and the base of transistor Q 2A    655 . To overcome the error caused by base currents, the value of R 5  can be determined as follows
 
 R   5   =R   4 *(3 *R   3A   +R   3 )/( R   3A   +R   3   +R   4 )
 
When two identical stages are stacked, i.e., R 3A =R 3 , this reduces to
 
 R   5 =4 *R   3   *R   4 /(2 *R   3   +R   4 )
 
     In some embodiments, as the number of stages and the ratio of emitter areas increase, the ΔV BE  PTAT term may eventually exceed the V BE  CTAT term, thus effectively eliminating resistor R 4  (e.g., resistor  590  in  FIG. 5 ) altogether. When this occurs, different exemplary approaches may be employed to boost the CTAT term. 
     The first exemplary approach is to employ a V BE  multiplier. This is illustrated in  FIG. 7 , where circuit  700  comprises four stages of stacking,  710 ,  720 ,  730 , and  740 , an error amplifier  755 , and a sub-circuit connecting the voltage output of the circuit  700  and the ground, including resistors R 3C    760 , R 3B    765 , R 3A    770 , R 3    775 , transistor Q 3    780  and resistors R 4A    785  and R 4B    790 . Resistors R 4A    785  and R 4B    790  are connected in series with the middle connection point coupled to the base of transistor Q 3    780 , one end of the series connected to the collector of transistor Q 3    780 , and the other end of the series connected to the emitter of transistor Q 3    780 . With this solution, the voltage across the transistor Q 3    780  is multiplied by a factor determined based on the ratio of R 4A    785  to R 4B    790 , i.e., (1+R 4A /R 4B ). This multiplying factor will enable an increase of the CTAT term and allow for an even larger PTAT term. 
     The second exemplary approach is to employ two V BE S and retain resistor, R 4 . This exemplary solution is illustrated in  FIG. 8 . In this illustrated embodiment, circuit  800  comprises four stages of stacking,  810 ,  820 ,  830 , and  840 , an error amplifier  855 , and a sub-circuit connecting the voltage output of the circuit  800  and the ground, including serially connected resistors R 3C    860 , R 3B    865 , R 3A    870 , R 3    875 , R 4    880 , and two transistors Q 3A    885  and Q 3    890 . The two V BE S require a larger PTAT term which can be accomplished by increasing ΔV BE  through additional stages and/or increasing the value of R 4    880 . The order of devices in the sub-circuit may not be important. For example, the diode connected devices Q 3    890  and Q 3A    885  need not be arranged together. 
     In some embodiments, another approach may be employed to increase the ΔV BE . This is shown in  FIG. 9 , where a cross-coupled V BE  loop is added within each PTAT generator. For instance, in PTAT generator  910 , a cross-coupled V BE  loop  920  is added between a pair of differential transistors and its corresponding tail current source. In PTAT generator  930 , a cross-coupled V BE  loop  940  is added between a pair of differential transistors and its corresponding tail current source. Resistors R 5 -R 8  in those added cross-coupled loops are for reducing the g m  of the additional devices to keep the circuit stable. The specific illustration of the sub-circuit  960  in  FIG. 9  used the same circuit as shown in  FIG. 8 . However, any implementation of the same circuitry described herein may be employed. 
     In some embodiments, still another approach may be adopted to increase the ΔV BE  within a stage. In accordance with this approach, diode connected devices may be introduced in PTAT generators. This is shown in  FIG. 10 . For instance, in PTAT generator  1010 , a pair of diode connected devices  1020  are added between a pair of differential transistors and their corresponding tail current source. In PTAT generator  1030 , another pair of diode connected devices  1040  are added between a pair of different transistors and their corresponding tail current source. The sub-circuit  1060  between the output of error amplifier  1050  and the ground can be implemented in accordance with any of the embodiments discussed herein. Using these alternative approaches, an additional diode connected BJT, Q 3A , is added to the output string. 
     There are other variations in implementing the present teaching. For example, NPN transistors may be replaced with PNP transistors. Without deviating from the present teaching, base current cancellation or curvature correction schemes may also be included in the implementations. In some embodiments, currents may be ratioed through ΔV BE  cells to increase the ΔV BE . Devices used for current source(s) or error amplifiers may be based on MOSFETS. A shunt regulator instead of series regulator may also be employed. In implementing the error amplifier (e.g.,  460 ,  580 ,  665 ,  755 ,  855 ,  950 ,  1050  in  FIGS. 4-10 ), an architecture different from what is shown in  FIG. 3  may be used. In addition, multiple input error amplifiers may also be used. Furthermore, in different implementations, an error amplifier therein may be biased differently. Rather than using a independent current source  415 , a current can be internally generated and bootstrapped eliminating the need for additional bias circuitry. 
     In some embodiments, the diode connected device Q 3  (see  FIGS. 4-10 ) may be similarly used as in a Dobkin cell to gain up the output voltage beyond a bandgap voltage. Moreover, components R 3 , R 4 , and Q 3  may be interchanged. Two or more diode connected devices may be used in the output. A current reference may be alternatively employed in place of a voltage reference. Overall, in accordance with the present teaching, a larger ΔV BE  can be achieved with fewer transistors without the penalty of a higher input voltage supply or increased noise. A larger ΔV BE  translates into a high performance low noise voltage or current reference. 
     While the inventions have been described with reference to the certain illustrated embodiments, the words that have been used herein are words of description, rather than words of limitation. Changes may be made, within the purview of the appended claims, without departing from the scope and spirit of the invention in its aspects. Although the inventions have been described herein with reference to particular structures, acts, and materials, the invention is not to be limited to the particulars disclosed, but rather can be embodied in a wide variety of forms, some of which may be quite different from those of the disclosed embodiments, and extends to all equivalent structures, acts, and, materials, such as are within the scope of the appended claims.