Abstract:
A digital data slicer circuit causes the slicing level to track a teletext signal in optimum fashion even if the teletext signal has many successive zero crossings. The digital data slicer circuit substantially prevents any lock-in in either of two other, stable states. This is achieved essentially by applying a zero signal via two changeover switches to an accumulator and a sign inverter when many successive zero crossings are detected by a logic circuit that controls the changeover switches.

Description:
FIELD OF THE INVENTION 
     The present invention is in the field of television and, more particularly, the present invention relates to a digital data slicer circuit for separating and recovering digital teletext signals from the composite color signal demodulated in color-television receivers and digitized with the aid of a clock signal. 
     BACKGROUND OF THE INVENTION 
     A data slicer circuit for separating and recovering digital teletext data is disclosed in EP-A 144 457, corresponding to U.S. Pat. No. 4,656,513. The disclosure of U.S. Pat. No. 4,656,513 is incorporated herein by reference. According to the fundamental idea of that application and that patent, the slicing level is determined by subtracting the teletext signal from the start-value-containing composite color signal. Since the exact shape of the teletext signal is unknown or is not reproducible, a corresponding reference signal is generated and subtracted, so that an error signal is obtained. Integration of the error signal provides the unsmoothed slicing level, which still contains high-frequency interfering signals. During the generation of the reference signal, those teletext-signal amplitudes which occur shortly before and shortly after a 0 to 1 transition are suppressed, so that only the peak values of the teletext signal are evaluated. 
     It turns out that in teletext signals with many successive 0 to 1 transitions, i.e., zeroes, the prior art arrangement leads to unacceptable errors in the reference signal. 
     SUMMARY OF THE INVENTION 
     The present invention provides a remedy to the above-described problem. The object of the invention described herein is to improve the prior art arrangement in such a way that, even if the teletext signal has many successive zero crossings, a substantially error-free reference signal will be generated, thus ensuring optimum tracking of the slicing level. The invention makes it highly unlikely for the improved arrangement, particularly at small signal amplitudes, to leave its desired state, so that it can no longer change to either of the two other, then stable states, which would render the separation of the teletext information impossible. Thus, the arrangement of the present invention does not lock in to any state other than the desired state. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of an embodiment of the invention; and 
     FIGS. 2 and 3 are schematic timing diagrams illustrating the operation of the circuit in accordance with the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the highly schematic block diagram of FIG. 1, the square and rectangular symbols represent digital circuit stages which process digital signals in parallel. If necessary, use is made of the so-called pipeline technique, which is advantageous particularly in the case of adders, subtracters, multiplers, etc. 
     The aforementioned parallel processing of multi-digit words is also symbolized in FIG. 1 by the fact that the interconnecting leads between the individual subcircuits are drawn as stripe-like lines where such multi-digit words occur. The solid lines commonly used in circuit diagrams represent leads over which a single-digit word is transferred, for example. 
     The input to the arrangement of FIG. 1 is assumed to be the start-value-containing composite color signal df as is described in the printed publications mentioned above. The &#34;composite color signal&#34; is the usual composite color signal in a television receiver. In the present case, this signal is a suitably digitized signal that has been converted into digital words by an analog-to-digital converter (not shown) in a conventional manner by being sampled by means of a clock signal ts from a clock oscillator os. If necessary, the subcircuits of the arrangement of FIG. 1, particularly the delay elements and the delay line described below, are also clocked by the clock signal ts. 
     The clock oscillator os can be any suitable oscillator circuit, including the driver stages and any pulse-shaping stages necessary to control the individual subcircuits. The pulse-shaping stages are advantageous, for example, if the arrangement of the present invention is to be implemented with insulated-gate field-effect transistor integrated circuit technology, using the so-called two-phase system. A two-phase system is a clock system in which the entire circuit is operated with a single square-wave clock signal and the inverse clock signal derived therefrom. 
     The start-value-containing composite color signal df, after being digitized by means of the clock signal ts, is applied to the minuend input of a first subtracter s1. The first subtracter s1 has an output that provides a digital signal x0. The output of the first subtracter s1 is connected to the minuend input of a second subtracter s2. The second subtracter s2 has an output that provides a signal x2. The signal x2 is coupled through a delay line vg to the first input of a first changeover switch u1 and to the first input of a second changeover switch u2. The delay provided by the delay line vg is equal to twice the period of the clock signal ts. The output of the first changeover switch u1 is coupled to the input of a first sign inverter w1. The first sign inverter w1 has an output that is connected to the input of a first weighted accumulator a1. A first weighting factor g1, having a magnitude less than one, is applied to the first weighted accumulator a1 so that the first weighted accumulator a1 acts as an integrator. The output of the first weighted accumulator a1 is coupled to the input of a second sign inverter w2. The second sign inverter w2 has an output that provides a signal x1. The output of the second sign inverter w2 is connected to the subtrahend input of the second subtracter s2. 
     The output of the second changeover switch u2 is coupled to the input of a second weighted accumulator a2, which has the weighting factor g2. The weighting factor g2 is preferably different from the weighting factor g1, and is less than one so that the second weighted accumulator a2 acts as an integrator. The second weighted accumulator a2 has an output that is coupled to the subtrahend input of the first subtracter s1. The output of the second accumulator a2 provides a signal sp, which is the as yet unsmoothed slicing level. If necessary, the unsmoothed slicing level signal sp can be smoothed, for example, by means of a first-order, low-pass filter tp. The output of the first-order, low-pass filter tp provides a smoothed slicing level sp&#39;. 
     The second input of each of the two changeover switches u1, u2 are fed by the digital word &#34;0&#34;, which corresponds to the numerical value zero, so that the two changeover switches u1, u2 transfer either the output signal of the delay element vg or the &#34;0&#34; digital word to the first sign inverter w1 and the second accumulator a2, respectively. The transfer is effected by means of an output signal from a logic circuit gc, as is illustrated by a line running to the switching contacts of the two changeover switches u1, u2 from the logic circuit gc. The switching contacts for the two changeover switches u1, u2 are shown in the positions in which the output signal of the delay element vg is transferred from the respective first inputs to the outputs of the changeover circuits in the manner described. 
     The logic circuit gc has five inputs e1, e2, e3, e4, e5. A delay element v is connected between each the first input e1 and the second input e2, the second input e2 and the third input e3, the third input e3 and the fourth input e4, and the fourth input e4 and the fifth input e5. Each of the delay elements v provides a delay equal to the period of the clock signal ts. The first input e1 of the logic circuit gc and a control input of the second sign inverter w2 are controlled by the sign bit vb of the output of the first subtracter s1. A control input of the first sign inverter w1 is controlled by the signal at the third input e3 of the logic circuit gc. The control inputs control the two sign inverters w1 and w2 in such a manner that when the sign bit vb indicates a negative word, the two sign inverters w1, w2 are put in their respective inverting conditions. In other words, when the two sign inverters are in their inverting conditions, a positive digital word applied at the respective inverter input appears as the corresponding negative digital word at the inverter output, and vice versa. Depending on the method used to represent positive and negative numbers, the two sign inverters w1, w2 will be conventional one&#39;s or two&#39;s complement inverters, for example. The two delay elements v between the first input e1 and the second input e2 and between the second input e2 and the third input e3 cause the switchover of the first sign inverter w1 to be delayed by two clock periods with respect to the signal x0. The two clock periods correspond to the delay through the delay element vg so that the switchover of the first inverter w1 takes place exactly at the instant the digital word x0 whose sign is applied to the input e1 appears at the output of the delay element vg. 
     The logic circuit gc provides at its output a binary level which causes the first inputs of the changeover switches u1, u2 to be connected to the respective outputs when the signals of the following table appear at its five inputs e1, e2, e3, e4, e5, where 0 and 1 are the two binary levels, and x indicates that either of the two binary levels may appear: 
     
         ______________________________________e1         e2    e3           e4  e5______________________________________x          0     x            0   xx          l     x            1   x0          l     1            0   x1          0     0            1   xx          0     1            1   0x          1     0            0   1______________________________________ 
    
     With the aid of this table, the logic can be constructed by those skilled in the art in the usual manner, taking account of known minimization laws. It can be seen that the logic circuit gc operates to suppress the passage of sample values near the zero-crossings of the start-value-containing composite color signal df so that such possibly erroneous values of the output quantity x2 are not added to the first weighted accumulator a1 or the second weighted accumulator a2. Rather, for certain of the sample values near the zero-crossings, the value of zero is added to the weighted accumulators rather than the quantity x2. Thus, the suppressed quantities x2 do not affect the magnitudes of the outputs of the two accumulators. 
     FIGS. 2 and 3 explain the operation of the slicer circuit in the presence of an ideal teletext signal (FIG. 2) and an actual, band-limited teletext signal (FIG. 3). The large dots (FIGS. 2a, 3a) represent the sample values df of the teletext signal corrected by the slicing level sp, and the small dots (FIGS. 2b, 3b) represent the output values x2 of the subtracter s2 corresponding to these sample values for a predetermined content x1 of the accumulator a1. The directions of the arrows in FIGS. 2a, 3a indicated how the output value x2 of the subtracter a2 is derived from the signed values x0, x1 and x1. 
     In the case of an idealized teletext signal (FIG. 2), whose sample values are only x0, the output quantity x2 of the subtracter s2 is comparatively small and varies only little. In contrast, the output quantity x2 can assume large absolute values in the case of a band-limited signal (FIG. 3) if sample values near zero occur at the application of the input value x0 to the second subtracter s2. These large absolute values are shown as peaks in the waveform of the signal x2 in FIG. 3band they represent an undesired, interfering signal that may lead to the above-mentioned disadvantageous lock-in in the arrangement described in the printed publications referenced above. The peaks are therefore suitably suppressed by the logic circuit gc, whose operation is specified in detail by the above table. 
     In contrast to the present invention, in the prior art arrangement described in the printed publications referenced above, the case of FIG. 3 would lead to the above-mentioned disadvantageous lock-in. Thus, the present invention provides a significant advantage over the prior art arrangement.