Abstract:
Test board configurations and test method for semiconductor devices with simultaneous bi-directional (SBD) data ports are disclosed. The devices have two SBD data ports with a pass mode that relays data between the ports. Significantly, each device contains configurable switching elements that allow a test mode, wherein unidirectional input/output data on one SBD data port is mapped to bi-directional data on the other SBD data port. This allows device testing with automated test equipment that employs unidirectional data signaling, and yet allows such test equipment to test the SBD capability of such devices.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to semiconductor devices employing simultaneous bi-directional transmission, and methods and apparatus for testing such devices. 
   2. Description of the Related Art 
   Semiconductor devices such as processors, controllers, memory devices, etc., are commonly equipped with data transceivers that allow them to receive and transmit digital signals. Conventionally, such transceivers are reconfigurable to either receive or transmit data across an attached transmission line. Recently, devices with simultaneous bi-directional (SBD) transmit/receive capability have received increased interest. As the name alludes to, SBD transceivers have the capability to receive and transmit digital data during the same clock cycle, on the same transmission line. 
     FIG. 1  shows a conventional SBD connection between two semiconductor devices  20  and  40 . Devices  20  and  40  contain, respectively, SBD transceivers  22  and  42 . SBD transceiver  22  contains a data driver  24  and a data receiver  26 . An internal data signal to be driven, Dout 1 , is supplied as an input to driver  24  and as a control signal to receiver  26 . The output of driver  24  is coupled to the input of receiver  26 . Receiver  26  also receives two reference voltages, VrefH and VrefL, which it uses for comparisons, as will be explained shortly. The output of receiver  26  is a data input, Din 1 , to device  20 . 
   Transceiver  42  of device  40  is preferably matched to transceiver  22  of device  20 . Transceiver  42  contains a driver  44  and a receiver  46  connected in an identical configuration as the driver and receiver of transceiver  22 . Driver  44  takes its input from an internal data signal Dout 2 , and receiver  46  generates a data input Din 2 . 
   Semiconductor devices  20  and  40  can be connected to each other in the configuration shown in  FIG. 1 , by connecting the outputs of drivers  24  and  44  to a transmission line  30 . Note that in this configuration, the drive state of both driver  24  and driver  44  determine the bit line voltage V BL  on transmission line  30 . A common reference voltage generator  32  supplies Vref 1  and VrefL to both circuits. 
     FIG. 2  contains waveforms illustrating the simultaneous exchange of data between devices  20  and  40  over transmission line  30 . Dout 1  is high during time periods T 1 , T 2 , and T 5 . Dout 2  is high during time periods T 1 , T 3 , and T 5 . Consequently, during T 1 , drivers  24  and  44  both pull the bit line voltage V BL  high, e.g., to an upper rail voltage V h . During T 2 , driver  24  attempts to pull bit line voltage V BL  high and driver  44  attempts to pull V BL  low, e.g., to a lower rail voltage V l . With matched drivers, V BL  will assume an approximate voltage V mid , halfway between upper rail voltage V h  and the lower rail voltage V l . During T 3 , both drivers reverse, and V BL  stays at V mid . During T 4 , both drivers pull V BL  low, to V l . 
   Receivers  26  and  46  determine the drive state of the other device&#39;s driver during each time period by selecting an appropriate comparison voltage, based on the known drive state of their own driver. For instance, during T 1  and T 2 , receiver  26  knows that driver  24  is driving line  30  high—thus the only two possible values of V BL  are V h  (if driver  44  is also driving line  30  high) and V mid  (if driver  44  is driving line  30  low). Thus during T 1  and T 2 , receiver  26  compares V BL  to VrefH, which is midway between V h  and V mid , and is able to determine that driver  44  was sending a high voltage during T 1  and a low voltage during T 2 . Similarly, during T 3  and T 4 , receiver  26  knows that driver  24  is driving line  30  low, and compares V BL  to VrefL. Receiver  46  operates similarly, but based on the known state of driver  44 , to determine the drive state of driver  24 . 
   One use of SBD transmission technology is in a point-to-point memory system such as in the partial system depicted in  FIG. 3 . In such a memory system, devices can communicate with an upstream device and a downstream device over separate connections. For instance, device  20  can be a memory controller, and devices  40  and  60  can be two memory devices connected to the controller. As the controller initiates memory operations, it is upstream of device  40 . And as device  40  is interposed between devices  60  and  20 , device  40  is upstream of device  60 . Address and control signal buses used to control memory operations are not shown in  FIG. 3 . 
   Although such a configuration can have any practicable data bus width,  FIG. 3  shows a bus width of four bits. One bus consists of point-to-point bit lines  30 - 0 ,  30 - 1 ,  30 - 2 , and  30 - 3 , with device  20  as an upstream device and device  40  as a downstream device. A second bus consists of point-to-point bit lines  50 - 0 ,  50 - 1 ,  50 - 2 , and  50 - 3 , with device  40  as an upstream device and device  60  as a downstream device. 
   Device  40  has an upstream port consisting of four upstream SBD transceivers  42 - 0 ,  42 - 1 ,  42 - 2 , and  42 - 3 , and a downstream port consisting of four downstream SBD transceivers  48 - 0 ,  48 - 1 ,  48 - 2 , and  48 - 3 . Within device  40 , upstream SBD transceiver is connected to a corresponding downstream SBD transceiver. Thus data received, e.g., at transceiver  42 - 0 , is both a data input Din 0  to device  40  and an input Ddn 0  to the downstream driver of transceiver  48 - 0 . And data Dup 0  received, e.g., at transceiver  48 - 0 , is multiplexed with device  40  output data Dout 0  at a multiplexer  45 - 0 , for input to the upstream driver of transceiver  42 - 0 . 
   Devices  20  and  40  communicate n bits of SBD data as previously described, with the bit lines  30 -n working in parallel. Depending on the memory operation, however, the data received by device  40  may be destined either for device  40  or for a downstream device (e.g., device  60 ), and the data transmitted by device  40  may be either internal data or data received from device  60 . Thus devices  20  and  60  communicate data between each other using their respective point-to-point buses to device  40 , and device  40  forwards data traffic between its upstream and downstream ports in a pass mode. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates two prior-art SBD transceivers, on separate semiconductor devices, connected by a transmission line; 
       FIG. 2  illustrates data input value/output value relationships for the transceivers of  FIG. 1 ; 
       FIG. 3  shows a prior art semiconductor device with a pass-through data port, allowing the device to connect two other devices over point-to-point data buses; 
       FIG. 4  is a block diagram for a semiconductor device according to an embodiment of the invention; 
       FIGS. 5A and 5B  show device testing configurations according to an embodiment of the invention, for two communicating SBD devices; 
       FIGS. 6A and 6B  show device testing configurations according to an embodiment of the invention, for three communicating SBD devices; 
       FIG. 7  shows a device configuration according to an embodiment of the invention, for five communicating SBD devices; 
       FIGS. 8A and 8B  show a second set of device testing configurations according to an embodiment of the invention, for two communicating SBD devices; and 
       FIGS. 9A ,  9 B, and  9 C show device testing configurations according to an embodiment of the invention, for one SBD device. 
   

   DETAILED DESCRIPTION OF THE EMBODIMENTS 
   Generally, automatic test equipment (ATE) is used to cull bad semiconductor devices from a lot of semiconductor devices. An ATE station is connected to a device to be tested via a test board. The ATE station is programmable, such that it can be configured to apply test signals to the inputs of a device under test (DUT), and receive signals from the outputs of the DUT. For instance, if the DUT is a memory device, the ATE station might emulate memory controller address and control signaling to write a certain bit pattern to the memory device, and then read the bit pattern back to see if what was written was stored and retrieved successfully. 
   Conventional ATE stations do not support SBD transfers. Even if such stations supported SBD transfers, the stations would have to use SBD transceivers that were matched to the SBD transceivers of a DUT, or else SBD transfers would be error-prone or impossible. Accordingly, it is desirable that test communications between an ATE station and a DUT remain unidirectional, even for DUTs with SBD data ports. And yet the SBD capability of a DUT is critical to device operation, and must be tested. 
   The described embodiments provide for testing of SBD devices, including the SBD capability of such devices, in an environment that allows for unidirectional communication between a device configuration under test and an ATE station. As will be illustrated, the invention encompasses various methods for testing such a device configuration, integrated circuit test boards, and semiconductor devices amenable to testing using the described methods and test boards. One concept found throughout these embodiments is an ability to configure an SBD semiconductor device such that two data port pads can be used in a test mode to respectively receive one unidirectional data signal and transmit another unidirectional data signal, with these two data signals coupled respectively to/from a third pad that operates as an SBD pad. This concept will be clarified as the following embodiments are explored in detail. 
     FIG. 4  illustrates a semiconductor device  100  according to one embodiment of the present invention. A north, or upstream, SBD data port comprises pads N 0 , N 1 , N 2 , and N 3 , connected respectively to SBD transceivers  102 - 0 ,  102 - 1 ,  102 - 2 , and  102 - 3 . A south, or downstream, SBD data port comprises pads S 0 , S 1 , S 2 , and S 3 , connected respectively to SBD transceivers  104 - 0 ,  104 - 1 ,  104 - 2 , and  104 - 3 . As with prior art devices, data input to the device and data output from the device utilize the north or upstream port in a normal mode. A pass mode uses a pass-through path that connects the north port with the south port in a one-to-one pad correspondence, e.g., transceiver  102 - 0  is connected to transceiver  104 - 0 , transceiver  102 - 1  is connected to transceiver  104 - 1 , etc. However, unlike prior art devices, this path is not fixed—at least one second pad correspondence is possible that is useful for testing, and is activated in a test mode. 
   Multiple pass-through paths are possible with device  100  due to the inclusion of cross-connecting switching elements that allow different correspondences between north and south port pads. Significantly for unidirectional test signaling, the switching elements can be configured to pass data in various two-pad-to-one-pad mappings. For instance, consider pads N 0 , N 1 , S 0 , and S 1 . Transceivers  102 - 0  and  102 - 1  both supply received signals to multiplexers (MUXs)  108 - 0  and  108 - 1 . A test mode signal TM determines which input forms the output for each MUX. Thus either Din 0  or Din 1  can be selected as signal Ddn 0 , to be driven externally by transceiver  104 - 0 . Likewise, either Din 0  or Din 1  can be selected as signal Ddn 1 , to be driver externally by transceiver  104 - 1 . 
   Similarly, MUXs  106 - 0  and  106 - 1  determine one of multiple sources to be driven externally by transceivers  102 - 0  and  102 - 1 , respectively. MUX  106 - 0 , e.g., can select between Dup 0 , Dup 1 , and Dout 0  (output data supplied from the chip core). 
   A similar switching element arrangement connects north port pads N 2  and N 3  with south port pads S 2  and S 3 . For devices with larger bus widths, the switching element configuration can be repeated for each set of two north and two south ports. Note that although multiplexers are illustrated in  FIG. 4  as the switching elements, individual switches can accomplish the same functionality, or a subset of this functionality. 
   With the preceding description of a semiconductor device embodiment in place, several device configurations will now be shown and described. Each of these device configurations allows some (or all) SBD pads of a DUT to be exercised in SBD mode as an internal SBD port, using other SBD pads as an external unidirectional port. 
     FIGS. 5A and 5B  illustrate a first device configuration consisting of semiconductor devices  120  and  140 . The external data port consists of the north port of device  120  and the south port of device  140 . The even-numbered port pads N 0  and N 2  (device  120 ) and S 0  and S 2  (device  140 ) are configured as a receive port to receive data from an attached tester (not shown). The odd-numbered port pads N 1  and N 3  (device  120 ) and S 1  and S 3  (device  140 ) are configured as a transmit port to send data to the attached tester. 
   Two internal data ports are shown. The first internal data port consists of the south port pads of device  120 , and the second internal data port consists of the north port pads of device  140 . The port pads of the first and second internal data ports are connected by a test board in a one-to-one correspondence, e.g., device  120  port pad S 0  connects to device  140  port pad N 0  via a bit line  130 - 0  formal in/on the test board. 
   In test mode, two test phases are used to conduct an SBD test of the internal data ports. In the first phase, internal data paths in device  120  and  140  are set as shown in  FIG. 5A . In the second phase, internal data paths are set as shown in  FIG. 5B . Each phase will be explained in turn. 
   In the first phase, the even-numbered south port pads of device  120  and the even-numbered north port pads of device  140  are tested. Thus in device  120 , the internal data paths are configured to pass write data received at N 0  and N 2 , respectively, to S 0  and S 2  and pass write data received at S 0  and S 2 , respectively, to N 1  and N 3 . In device  140 , the internal data paths are configured to pass write data received at S 0  and S 2 , respectively, to N 0  and N 2  and pass write data received at N 0  and N 2 , respectively, to S 1  and S 3 . This configuration can be done, e.g., by having the ATE set test mode fields in the mode register sets of devices  120  and  140 , to configure switching elements such as those shown in  FIG. 4 . 
   Once the data path configuration is complete, the ATE writes bit patterns to the designated external port write pads to test the SBD capability of the internal port. For instance, logic zero can be written to device  120  port pads N 0  and N 2 , at the same time that logic one is written to device  140  port pads S 0  and S 2 . This causes transceiver  124 - 0  to drive a logic zero on bit line  130 - 0  at the same time that transceiver  142 - 0  drives a logic one on the same bit line. If transceivers  124 - 0  and  142 - 0  are operating correctly, transceiver  124 - 0  will receive a logic one and transceiver  142 - 0  will receive a logic zero. The values received by transceivers  124 - 0  and  142 - 0  will be internally forwarded to transceivers  122 - 1  and  144 - 1 , respectively, and driven to the ATE from device  120  port pad N 1  and device  140  port pad S 1 . 
   As the ATE will normally also exercise the SBD capability for the opposite signal polarity to that just described, the ATE then repeats the above write/read process with a different bit pattern, e.g., logic one written to device  120  port pads N 0  and N 2  and logic zero written to device  140  port pads S 0  and S 2 . This causes, e.g., transceiver  124 - 0  to write a logic one and read a logic zero, and transceiver  142 - 0  to write a logic zero and read a logic one. 
   Because in this configuration the number of external port unidirectional-mode pads is equal to the number of internal port SBD pads, only half of the SBD pads can be tested simultaneously. The second phase, illustrated in  FIG. 5B , tests the other half of the internal port SBD pads. Referring to  FIG. 5B , in device  120 , the internal data paths are reconfigured to pass write data received at N 0  and N 2 , respectively, to S 1  and S 3  and pass write data received at S 1  and S 3 , respectively, to N 1  and N 3 . In device  140 , the internal data paths are configured to pass write data received at S 0  and S 2 , respectively, to N 1  and N 3  and pass write data received at N 1  and N 3 , respectively, to S 1  and S 3 . This configuration can be done, e.g., by having the ATE set test mode fields in the mode register sets of devices  120  and  140  to cause a switch from the configuration of  FIG. 5A  to the configuration of  FIG. 5B . 
   Once the test path reconfiguration is complete, the ATE repeats the previous write/read bit pattern test to test the odd SBD pads S 1  and S 3  on device  120  and N 1  and N 3  on device  140 . Although only two bit patterns have been described for each phase of the test, those skilled in the art recognize that a variety of bit patterns can be attempted, in varying sequences, during a test. 
   Assuming that the devices pass the described test, the south port on device  120  and the north port on device  140  have been verified as operational in SBD mode. If both devices are DUTs, swapping device positions in the device configuration and repeating the test can test their other ports. Alternately, one device can be a known good device (KGD). The other device is the device under test, and is fully tested by testing it first in the position of device  120 , with a KGD at device  140 , and then in the position of device  140 , with a KGD at device  120 . 
     FIGS. 6A and 6B  illustrate a second device configuration consisting of semiconductor devices  200 ,  220 , and  240 . The external data ports consist of the north port pads of device  200  and the south port pads of device  240 . The even-numbered port pads N 0  and N 2  (device  200 ) and S 0  and S 2  (device  240 ) are configured as receive ports to receive data from an attached tester (not shown). The odd-numbered port pads N 1  and N 3  (device  200 ) and S 1  and S 3  (device  240 ) are configured as transmit ports to send data to the attached tester. 
   Four internal data ports exist in the  FIG. 6A  configuration. The four internal data ports are: the south port of device  200 ; both the north and south ports of device  220 ; and the north port of device  240 . The south port pads of device  200  and the north port pads of device  220  are connected by a test board in a one-to-one correspondence, e.g., device  200  port pad S 0  connects to device  220  port pad N 0  via a bit line  210 - 0 . The south port pads of device  220  and the north port pads of device  240  are connected in a one-to-one correspondence as well, e.g., device  220  port pad S 0  connects to device  240  port pad N 0  via a bit line  230 - 0 . 
   Like in the previous example, two test mode phases are used to conduct an SBD test of the internal data ports. In the first phase, internal data paths are set as shown in  FIG. 6A . In the second phase, internal data paths are set as shown in  FIG. 6B . Each phase will be explained in turn. 
   In the first phase, the even-numbered internal ports are tested. Devices  200  and  240  are configured respectively like devices  120  and  140  in  FIG. 5A . Device  220  is configured in a straight pass-through configuration, e.g., port pad N 0  communicates bi-directionally with port pad S 0 , etc. This configuration can be done, e.g., by having the ATE set test mode fields in the mode register sets of devices  200  and  240  (the device  220  configuration may not be a test configuration, but could be). 
   Once the data path configuration is complete, the ATE proceeds with bit pattern testing as in the prior example to test the even-numbered port pads of the four internal data ports. The path difference from the prior example is internal to the configuration, as the data will pass through one more point-to-point bus than in the prior example. 
   Once bit pattern testing is complete for this configuration, the ATE proceeds to configure devices  200  and  240  in the configuration shown in  FIG. 6B  (like the respective configuration of devices  120  and  140  of  FIG. 5B ) to test the odd-numbered internal port pads, as in the previous example. 
   At the end of the test cycle, the SBD capability of device  220  has been fully tested. If devices  200  and  240  are KGDs, another candidate device can replace device  220  and the test cycle can be repeated. Alternately, if all devices are DUTs, devices  200  and  240  can be swapped, and a new candidate device inserted in the place of device  220 , and the test cycle repeated. This procedure fully tests the SBD capability of device  200 , the original and second devices  220 , and the device  240 , in two test cycles. 
     FIG. 7  illustrates a third device configuration consisting of five semiconductor devices  300 ,  310 ,  320 ,  340 , and  350 . The external data ports consist of the north port pads of devices  310  and  320  and the south port pads of devices  340  and  350 . The even-numbered port pads N 0  and N 2  (devices  310  and  320 ) and S 0  and S 2  (devices  340  and  350 ) are configured as receive ports to receive data from an attached tester (not shown). The odd-numbered port pads N 1  and N 3  (devices  310  and  320 ) and S 1  and S 3  (devices  340  and  350 ) are configured as transmit ports to send data to the attached tester. 
   Six internal data ports exist in the  FIG. 7  configuration. The six internal data ports are: the south port of devices  310  and  320 ; both the north and south ports of device  300 ; and the north port of devices  340  and  350 . Half of the south port pads of devices  310  and  320 , respectively, connect to respective halves of the north port pads of device  300 , e.g.: device  310  port pad S 1  connects to device  300  port pad NO via a bit line  330 - 0 ; device  310  port pad S 3  connects to device  300  port pad N 1  via a bit line  330 - 1 ; device  320  port pad S 0  connects to device  300  port pad N 2  via a bit line  330 - 2 ; and device  320  port pad S 2  connects to device  300  port pad N 3  via a bit line  330 - 3 . Similar connections connect half of the north port pads of devices  340  and  350 , respectively, to respective halves of the south port pads of device  300 , via bit lines  360 - 0 ,  360 - 1 ,  360 - 2 , and  360 - 3 . 
   In this example, twice as many external port pads are available as in the previous examples. Accordingly, all of the port pads of device  300  can be tested simultaneously. The data signal input at N 0  on device  310 , e.g., passes through to port pad S 1 , is driven to port pad N 0  on device  300 , passes through to port pad SO, is driven to port pad N 1  on device  340 , passes through to port pad S 1 , and is driven to the ATE. At the same time, another data signal input at S 0  on device  340  passes through to port pad N 1 , crosses the first data signal on bit lines  360 - 0  and  330 - 0  to port pad S 1  on device  310 , passes through to port pad N 1 , and is driven to the ATE. Other ATE inputs and outputs cross similarly for the other external and internal port pads. 
   One use of the configuration shown in  FIG. 7  is with KGD devices for all devices except device  300 . Note that half of the internal ports on all KGDs are still available, and could be connected to a second test socket and used to test a second DUT in a similar manner to device  300 . 
   It is generally preferred to test the SBD capability of a DUT using either other DUTs or KGDs. It is possible, however, to construct device configurations where some DUT SBD port pads are paired with other SBD port pads on the same DUT.  FIGS. 8A and 8B  show one such configuration;  FIGS. 9A ,  9 B, and  9 C show another. 
     FIG. 8A , like  FIG. 5A , shows a two-device test configuration. In the  FIG. 8A  configuration, however, the only external port is the north port of device  400 . Device  400  port pads N 0  and N 2  receive data signals from an attached ATE; device  400  port pads N 1  and N 3  transmit data signals to an attached ATE. 
   In  FIG. 8A , three internal SBD ports are present. The south port of device  400  connects with the north port of device  420  in a one-to-one port pad correspondence, e.g., device  400  port pad S 0  connects to device  420  port pad N 0  via a bit line  410 - 0 , etc. The south port of device  420  connects to itself—port pad S 0  connects to port pad S 2  via a bit line  430 - 0 , and port pad S 1  connects to port pad S 3  via a bit line  430 - 1 . 
   Two test phases are used to test the SBD capability of device  420 . In the first test phase, the ATE transmits a first data signal to device  400  port pad N 0  and a second data signal to device  400  port pad N 2 . The first data signal is internally routed to device  400  port pad S 0 , driven on bit line  410 - 0  to device  420  port pad N 0 , internally routed to device  420  port pad S 0 , driven on bit line  430 - 0  to device  420  port pad S 2 , internally routed again to device  420  port pad N 2 , driven on bit line  410 - 2  to device  400  port pad S 2 , internally routed to device  400  port pad N 3 , and driven to the ATE. Simultaneously, the second data signal is internally routed to device  400  port pad S 2 , driven in the opposite direction on bit lines  410 - 2 ,  430 - 0 , and  410 - 0  to reach device  400  port pad S 0 , internally routed to device  400  port pad N 1 , and driven to the ATE. 
   In the second test phase, the internal data paths of device  400  are reconfigured as shown in  FIG. 8B , such that device  400  port pads S 1  and S 3  are the active SBD pads of device  400 . Test bit patterns are driven once again to device  400 , this time testing the port pads connected to bit lines  410 - 1 ,  430 - 1 , and  410 - 3 . 
   After the second test phase, all port pads of device  420  have been tested for SBD capability. 
   One additional test device configuration set is illustrated in  FIGS. 9A ,  9 B, and  9 C. This configuration pair contains a single device, the DUT. In  FIGS. 9A and 9B , the north port of device  500  is used for unidirectional communication with an ATE, and the south port of device  500  connects to itself to form the internal port. In  FIG. 9C , the south port and north port of device  500  switch roles. 
   Four test phases are required to test all SBD port pads.  FIG. 9A  illustrates the first test phase. In the first test phase, the ATE transmits a first data signal to device  500  port pad N 0  and a second data signal to device  500  port pad N 2 . The first data signal is internally routed to device  500  port pad S 0 , driven on bit line  510 - 0  to device  500  port pad S 2 , internally routed to device  500  port pad N 3 , and driven to the ATE. Simultaneously, the second data signal is internally routed to device  500  port pad S 2 , driven in the opposite direction on bit line  510 - 0  to reach device  500  port pad S 0 , internally routed to device  500  port pad N 1 , and driven to the ATE. 
   In the second test phase, the internal data paths of device  500  are reconfigured as shown in  FIG. 9B , such that device  500  port pads S 1  and S 3  are the active SBD pads of the device. Test bit patterns are driven once again to device  400 , this time testing the port pads connected to bit lines  510 - 1 . 
   To test the SBD capability of the north ports, the third and fourth test phases use a device configuration (the third test phase is shown in  FIG. 9C ) that switches the roles of the north and south ports from that of  FIGS. 9A and 9B . During the third test phase, bit line  520 - 0  tests SBD capability between device  500  port pads N 0  and N 2 . During the fourth test phase, a bit line (not shown) between port pads N 1  and N 3  is tested. 
   Those skilled in the art will recognize that many other device configuration permutations can be envisioned. For example, two serial DUTs could occupy the position of device  220  ( FIG. 6A ) or device  300  ( FIG. 7 ). Most devices will have data port widths much larger than the four bits illustrated—the connection patterns shown can merely be repeated for each additional four-bit width at each port. Other alternate internal device cross-connection patterns and device-to-device port pad assignments are feasible, although it is believed that the simplest device layouts will generally result from pairing adjacent port pad circuitry. 
   Explicit instructions for construction of test boards for use with the described embodiments have been omitted. It is believed that given the device-to-device routing illustrations presented, the layout of such a test board is well within the skill of those in the applicable art. 
   Although the focus of the preceding description has been on SBD testing, embodiments of the present invention can be used in some instances for all testing of a DUT with a unidirectional ATE connection.