Abstract:
A device is disclosed that allows a host device that is the source of data transfer to detect whether or not data have been correctly written to a memory device without interfering with the effective data transfer. When the host device issues a request to write sector data, a host adapter deblocks the sector data into data blocks and transfers the data in data block units to a memory adapter. The memory adapter not only memory-writes the data blocks to a memory device, but also generates block CRC code from the data blocks and returns the code as a write reply to the host adapter. The host adapter receives the block CRC code, carries out a CRC operation to reconstruct CRC code of complete sector data, performs a correspondence check with the CRC code of the original sector data, and reports the check results to the host device.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a data transfer system, and in particular, to a data transfer system that performs a data check.  
           [0003]    2. Description of the Related Art  
           [0004]    If a device that is the source of a data transfer and a device that performs a memory write of data to a memory device are in the same LSI (Large-Scale Integrated Circuit), it is possible to detect whether the data has been reliably written, and it is also easy to detect an abnormal state of the device such as altered data.  
           [0005]    In a large-scale system such as a large-scale disk array device, however, the data is not necessarily processed in a single LSI, and writing to a target memory device may be realized by way of various types of buses within the system such as PCI (Peripheral Component Interconnect) buses, and system buses as well as the plurality of LSIs that control these buses.  
           [0006]    The above-described large scale system of the prior art was of a system configuration that did not allow a data transfer source to completely verify that data had been written correctly to the ultimate memory device, despite the possibility that erroneous data may be recorded in a memory device due to, for example, the alteration of data to invalid data while being transferred due to the occurrence of an abnormality caused by hardware breakdowns during the data transfer, or due to the occurrence of a parity error caused by electrical noise in the bus that is being used.  
           [0007]    The most reliable method for enabling the device of a data transfer source to completely verify that correct data has been written to the ultimate memory device involves the performance of a correspondence check (verification) in which the data transfer source device reads from the memory device the data that it has written to determine that the data have been written correctly, but this method has the attendant problems of lowering the effective data transmission rate and reducing performance.  
           [0008]    It is an object of the present invention to provide a data transfer system in which, in the device (LSI) that performs final writing to a memory device, the written data are sampled to produce CRC (Cyclic Redundancy Check) code of portions of the data as block CRC code and returns this block CRC code to the data transfer source device; and in the data transfer source device, the CRC code of all of the transferred data are reconstructed the CRC code of the sector data, which is main data to be deblocked to a plurality of blocks, from the returned block CRC code to perform a correspondence check; whereby the data transfer source can guarantee the values of data that are written to a memory device without interfering with the actual data transfer.  
           [0009]    As an example of the prior art, Japanese Patent Laid-open No. 15354/95 discloses a “Method For Confirming CRC Code and Device Thereof.” In this prior art, in a transmission device that divides data blocks (corresponding to sector data in the present invention) into sub-block (corresponding to data blocks in the present invention) and then transmits, initial setting values are used to generate partial CRC codes (corresponding to block CRC codes in the present invention) for each received sub-block. The CRC codes are assembled from the partial CRC codes for the entire data block and verification of this data block then performed. This example of the prior art therefore differs conclusively from the present invention with respect to the assembly, on the receiving side, of the CRC codes for the entire data block from the partial CRC codes, the present invention being constituted such that the CRC codes for all sector data are reconstructed from block CRC codes at the data transfer source.  
         SUMMARY OF THE INVENTION  
         [0010]    In a data transfer system that is provided with a host adapter that deblocks sector data for which a write request has been issued from a host device and that issues a write request as a plurality of data blocks, and a memory adapter that memory-writes to a memory device the data blocks for which the write request has been issued;  
           [0011]    the data transfer system of the present invention comprises:  
           [0012]    the memory adapter, which, when performing a memory write to the memory device of data blocks for which a write request has been issued from the host adapter, generates a particular determined code from the data blocks and returns this code to the host adapter as a write reply; and  
           [0013]    the host adapter, which reconstructs CRC code of all sector data from the particular determined code that has been returned as a write reply from the memory adapter, verifies that the code is the CRC code of the original sector data, and reports the presence or absence of errors to the host device.  
           [0014]    In addition, in the data transfer system of the present invention, the particular determined code is block CRC code that is computed for portions of the data blocks in a state that has particular initial values.  
           [0015]    Further, when generating the block CRC code in the data transfer system of the present invention, the initial values are zero.  
           [0016]    Still further, the data transfer system of the present invention is provided with a crossbar circuit between the host adapter and the memory adapter that repeats the data transfer.  
           [0017]    In addition, in a data transfer system that is provided with a host adapter that deblocks sector data for which a write request has been issued from a host device and that issues a write request as a plurality of data blocks, a memory adapter that memory-writes to a memory device data blocks for which a write request has been issued, and a bus that interconnects the host adapter and the memory adapter;  
           [0018]    the data transfer system of the present invention comprises:  
           [0019]    the memory adapter, which, when performing a memory write to the memory device of data blocks for which a write request has been issued from the host adapter by way of the bus, generates block CRC code for the data blocks and returns this code as a write reply to the host adapter by way of the bus; and  
           [0020]    the host adapter, which reconstructs CRC code of all sector data from the block CRC code that has been returned as a write reply from the memory adapter by way of the bus, verifies that the code is the CRC code of the original sector data, and reports the presence or absence of errors to the host device.  
           [0021]    In addition, in a data transfer system that is provided with a plurality of host adapters that deblocks sector data for which a write request has been issued from a host device and that issue a write request as a plurality of data blocks, a plurality of memory adapters that memory-write to a plurality of memory devices data blocks for which the write request has been issued, and a bus that interconnects the host adapters and the memory adapters;  
           [0022]    the data transfer system of the present invention comprises:  
           [0023]    the memory adapters, which, when performing a memory write to a memory device of data blocks for which a write request has been issued from one of the host adapters by way of the bus, generates block CRC code for the data blocks and returns this code as a write reply to said host adapter by way of said bus; and  
           [0024]    the host adapter, which reconstructs CRC code of all sector data from the block CRC code that has been returned as a write reply from the memory adapter by way of the bus, verifies that the code is the CRC code of the original sector data, and reports the presence or absence of errors to the host device.  
           [0025]    Still further, the host adapter in the data transfer system of the present invention includes: a data buffer for buffering the sector data; block CRC code to CRC code conversion circuit for reconstructing CRC code of all sector data from block CRC code that has been returned as the write reply; and a CRC code check circuit for verifying that the CRC code that has been reconstructed by the block CRC code to CRC code conversion circuit is the CRC code of the original sector data.  
           [0026]    In addition, in the data transfer system of the present invention, a plurality of the CRC code check circuits are provided in correspondence with channels, the channel of a data transfer source is specified by a channel number, and verification of reconstructed CRC code is realized using the CRC code check circuit that corresponds to that channel.  
           [0027]    Furthermore, the memory adapter in the data transfer system of the present invention includes: a data buffer for buffering data blocks for which a write request has been issued from the host adapter; and a block CRC code generation circuit that generates block CRC code for data blocks that have been memory-written from the data buffer to the memory device.  
           [0028]    Still further, the block CRC code generation circuit in the data transfer system of the present invention sets initial values to zero when generating the block CRC code.  
           [0029]    In a data transfer system that is provided with: a host adapter that deblocks sector data for which a write request has been issued from a host device and that issues a write request as a plurality of data blocks; a memory adapter that memory-writes to a memory device data blocks for which the write request has been issued; and a crossbar circuit that interconnects the host adapter and the memory adapter;  
           [0030]    the data transfer system of the present invention comprises:  
           [0031]    the memory adapter, which, when performing a memory write to the memory device of data blocks for which a write request has been issued from the host adapter by way of the crossbar circuit, generates block CRC code from the data blocks and returns this code as a write reply to the host adapter by way of the crossbar circuit; and  
           [0032]    the host adapter, which reconstructs CRC code of all sector data from the block CRC code that has been returned as a write reply from the memory adapter by way of the crossbar circuit, verifies that the code is the CRC code of the original sector data, and reports the presence or absence of errors to the host device.  
           [0033]    The host adapter in the data transfer system of the present invention includes: a data buffer for buffering the sector data; a block CRC code to CRC code conversion circuit for reconstructing the CRC code of all sector data from the block CRC code that has been returned as the write reply from the memory adapter; a CRC code check circuit for verifying that the CRC code that has been reconstructed by the block CRC code to CRC code conversion circuit is the CRC code of the original sector data; a host control circuit for controlling the host device; and a bus interface for controlling the interface with the crossbar circuit.  
           [0034]    Still further, in the data transfer system of the present invention, a plurality of the CRC code check circuits are provided in correspondence with channels, the channel of a data transfer source is specified by a channel number, and verification of reconstructed CRC code is realized using the CRC code check circuit that corresponds to that channel.  
           [0035]    Furthermore, the memory adapter in the data transfer system of the present invention includes: a data buffer for buffering data blocks for which a write request has been issued from the host adapter; a block CRC code generation circuit for generating block CRC code for data blocks that have been memory-written to the memory device from the data buffer; and a bus interface for controlling the interface with the crossbar circuit.  
           [0036]    Further, in the data transfer system of the present invention, the block CRC code generation circuit sets initial values to zero when generating the block CRC code.  
           [0037]    Still further, in the data transfer system of the present invention, the crossbar circuit includes: a first bus interface for controlling the interface with the host adapter; a second bus interface for controlling the interface with the memory adapter; and a plurality of data buffers provided between the first bus interface and the second bus interface.  
           [0038]    In the data transfer system of the present invention, when a host device issues to a memory device a write request for a particular collection of data (hereinbelow referred to as “sector data”), the host adapter deblocks the sector data into data (hereinbelow referred to as “data blocks”) for every particular fixed number of bytes and transfers the data blocks to the memory adapter in data block units. The memory adapter both memory-writes the data blocks to a memory device and generates CRC code (hereinbelow referred to as “block CRC code”) from the data blocks, and returns the block CRC code to the host adapter as a write reply to the write request. Upon receiving the block CRC code as the write reply, the host adapter performs a CRC operation on the block CRC code, reconstructs the CRC code of all sector data, performs a correspondence check with the CRC code of the original sector data, and reports the check results to the host device. In this way, the host device that is the data transfer source can detect whether or not sector data for which a write request has been issued have been normally written to a memory device.  
           [0039]    The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings, which illustrate examples of the present invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0040]    [0040]FIG. 1 is a circuit block diagram showing the configuration of the data transfer system according to the first embodiment of the present invention.  
         [0041]    [0041]FIG. 2 is a flow chart showing the processing of the data transfer system according to the first embodiment.  
         [0042]    [0042]FIG. 3 is a circuit block diagram showing the configuration of the data transfer system according to the second embodiment of the present invention.  
         [0043]    [0043]FIG. 4 is a circuit block diagram showing the configuration of the data transfer system according to the third embodiment of the present invention.  
         [0044]    [0044]FIG. 5 shows an example of the constitution of transfer data between the host device and the host adapter.  
         [0045]    [0045]FIG. 6 shows an example of the constitution of transfer data between the host adapter and the memory adapter.  
         [0046]    [0046]FIG. 7 shows an example of the constitution of transfer data between the host adapter and the memory device.  
         [0047]    [0047]FIG. 8 shows an example of the constitution of transfer data between the memory adapter and the host adapter.  
         [0048]    [0048]FIG. 9 is a view for explaining the principles of operation of the data transfer system of this embodiment.  
         [0049]    [0049]FIG. 10 is a circuit block diagram showing the unit composition of a normal CRC arithmetic circuit and the unit composition of the CRC arithmetic circuit following conversion of the computation sequence.  
         [0050]    [0050]FIG. 11 is a circuit block diagram showing an example of the unit composition of a CRC arithmetic circuit that is used in the present embodiment.  
         [0051]    [0051]FIG. 12 is a circuit block diagram showing an example of the overall configuration of the CRC arithmetic circuit that is used in the present embodiment. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0052]    Explanation next regards the details of embodiments of the present invention with reference to the accompanying drawings.  
       FIRST EMBODIMENT  
       [0053]    We refer first to FIG. 1, which is a circuit block diagram showing the configuration of the data transfer system according to the first embodiment of the present invention. The principal components of the data transfer system according to this embodiment are constituted by: host device  1  that issues a request to write sector data; host adapter  2  that deblocks the sector data for which a write request has been issued from host device  1  into data block units and that issues a write request to memory adapter  4 ; system bus  3  that connects host adapter  2  and memory adapter  4 ; memory adapter  4  that takes in data blocks for which a write request has been issued from host adapter  2 , memory-writes the data blocks to memory device  5 , generates block CRC code from the data blocks, and returns the block CRC code to host adapter  2  as a write reply; and memory device  5  for memory-writing the data blocks.  
         [0054]    [0054]FIG. 1 presents a simplified view of the arrangement in the data transfer between host device  1  and memory device  5 , and in the present invention, a limit is not set on the number of connections performed by the host devices  1  and memory devices  5 .  
         [0055]    Host adapter  2  is constituted to include: data buffer  21  for receiving the sector data for which a write request has been issued from host device  1 ; block CRC code to CRC code conversion circuit  22  for reconstructing the block CRC code that is returned as a write reply from memory adapter  4  to the CRC code of all sector data; and a plurality of CRC code check circuits  23  for verifying, for each channel, the correctness of the CRC code that has been reconstructed by the block CRC code to CRC code conversion circuit  22 . The results of the CRC code check that are reported to host device  1  from host adapter  2  are reported by way of an interrupt signal line (not shown in the figure).  
         [0056]    Memory adapter  4  is constituted to include: data buffer  41  for holding data blocks for which a write request has been issued from host adapter  2 ; and block CRC code generation circuit  42  for taking in data blocks that have been memory-written to memory device  5 , generating block CRC code, and returning the block CRC code to host adapter  2  as a write reply.  
         [0057]    The data transfer system according to the first embodiment is an example in which, for example, the sector data transferred from host device  1  to memory device  5  through a path within a disk array device, so other circuits such as some hard disks are actually necessary, but in this case, these components have been omitted here.  
         [0058]    Referring now to FIG. 2, the processing of host adapter  2  is constituted by: step S 101  for receiving sector data, step S 102  for deblocking to data blocks, step S 103  for initializing the counter, step S 104  for transferring data blocks, step S 105  for receiving block CRC code, step S 106  for selecting the CRC code check circuit, step S 107  for CRC operation, step S 108  for incrementing the counter, step S 109  for determining completion of data transfer, step S 110  for determining whether CRC code=0, step S 111  for reporting normal transfer, and step S 112  for reporting abnormal transfer.  
         [0059]    Referring to FIG. 2, the processing of memory adapter  4  is similarly made up by: step S 201  for receiving data blocks, step S 202  for storing in data buffers, step S 203  for executing memory write, step S 204  for generating block CRC code, and step S 205  for returning the block CRC code.  
         [0060]    In FIG. 2, the processing of host adapter  2  and the processing of memory adapter  4  are shown as a series of sequential flow charts to facilitate understanding, but the pipeline operation of host adapter  2  and memory adapter  4  can naturally operate independently as parallel sequences.  
         [0061]    Explanation next regards the operation of the data transfer system according to the first embodiment that is configured as described above.  
         [0062]    When a write request for sector data is issued from host device  1 , host adapter  2  takes in the sector data from host device  1  and stores the sector data in data buffer  21  (Step S 101 ).  
         [0063]    Host adapter  2  next deblocks the sector data that have been stored in data buffer  21  into n blocks having a prescribed number of m bytes each(Step S 102 ).  
         [0064]    After initializing counter to 0 (Step S 103 ), host adapter  2  then transfers the data blocks of block number i to memory adapter  4  (Step S 104 ). At this time, a block number and a channel number that are unique within the system are embedded in the header for each transferred data block and then the write request is issued.  
         [0065]    Upon receiving the data blocks from host adapter  2  by way of system bus  3  (Step S 201 ), memory adapter  4  stores the received transfer data in data buffer  41  (Step S 202 ).  
         [0066]    Memory adapter  4  next memory-writes the data blocks that have been stored in data buffer  41  to memory device  5  that is arranged to be under control of memory adapter  4 .  
         [0067]    Simultaneous with the memory-write of the data blocks, memory adapter  4  transfers the data blocks as is to block CRC code generation circuit  42 , and block CRC code generation circuit  42  generates CRC code in which initial values are set to zero as block CRC code (Step S 204 ). Details regarding an actual example of the generation of block CRC code by block CRC code generation circuit  42  are next described in embodiment 1 below.  
         [0068]    Memory adapter  4  next returns the generated block CRC code by way of system bus  3  to host adapter  2  as a write reply (Step S 205 ).  
         [0069]    Upon receiving the block CRC code that has been returned as a write reply from memory adapter  4  (Step S 105 ), host adapter  2  uses the block CRC code to CRC code conversion circuit  22  to specify the channel of the data transfer source and select the corresponding CRC code check circuit  23  (Step S 106 ), and then uses the selected CRC code check circuit  23  to perform a CRC computation of the block CRC code that has been returned as a write reply (Step S 107 ). An actual example of the CRC computation by means of the block CRC code to CRC code conversion circuit  22  is described in embodiment 1 below.  
         [0070]    Host adapter  2  next increments counter i by one (Step S 108 ); determines whether or not i&gt;n, i.e., whether or not the transfer of all data blocks has been completed (Step S 109 ); and if not completed, returns the control to Step S 104  to transfer the next data block to memory device  5 .  
         [0071]    If, on the other hand, i is not greater than n (“Yes” in Step S 109 ), the transfer of all data blocks has been completed; and host adapter  2  then determines whether or not the CRC codes of all sector data that have then been generated are all 0 (Step S 110 ); and if all 0 , reports to host device  1  that the sector data have been transferred normally (Step S 111 ). If the CRC codes for all sector data are not all 0 , host adapter  2  reports abnormal transfer to host device  1  as a CRC error (Step S 112 ).  
         [0072]    Thus, according to the first embodiment, host device  1 , which is the data transfer source, is able to detect whether sector data have been normally transferred to the ultimate memory device  5 , and as a result, the alteration of data at some point along the path of data transfer can be reliably detected and the integrity of data can be increased.  
         [0073]    In addition, because this data transfer system does not require that CRC codes always be added to data block units and transferred, the system can be adopted without causing any decrease in the transfer rate of system bus  3 .  
         [0074]    Further, because this data transfer system is equivalent to a data transfer system of the prior art with the exception of the path by which block CRC codes are returned as a write reply, the system of the present invention can be easily adopted to raise the integrity of data without requiring drastic alteration of circuits.  
         [0075]    Still further, since the block CRC code to CRC code conversion circuit  22  and CRC code check circuit  23  are located at host adapter  2 , a configuration that includes a plurality of host devices  1  does not result in an increase in hardware on the memory adapter  4  side, and circuit complexity can be prevented.  
         [0076]    In addition, the system is of a configuration that requires no more than one block CRC code generation circuit  42  in memory adapter  4 , which controls memory device  5 . As a result, the circuit scale and construction of memory adapter  4  need not be altered even when host device  1  performs a multiplex channel data transfer and a plurality of host devices  1  and host adapters silicon substrate are present, and the circuit scale of memory adapter  4  can therefore be decreased.  
       SECOND EMBODIMENT  
       [0077]    We now refer to FIG. 3, in which is shown a circuit block diagram of the configuration of the data transfer system according to the second embodiment of the present invention. The principal components of the data transfer system of this embodiment are constituted by: host devices  1 - 0 - 1 -p; host adapters  2 - 0 - 2 -p; request bus  31 ; reply bus  32 ; memory adapters  4 - 0 - 4 -q; and memory devices  5 - 0 - 5 -q.  
         [0078]    Host adapters  2 - 0 - 2 -p are constituted to include: data buffers  21 - 0 - 21 -p, block CRC code to CRC code conversion circuits  22 - 0 - 22 -p; and CRC code check circuits  23 - 0 - 23 -p.  
         [0079]    Memory adapters  4 - 0 - 4 -p are constituted to include: data buffers  41 - 0 - 41 -q and block CRC code generation circuits  42 - 0 - 42 -q.  
         [0080]    The operation of the data transfer system according to the second embodiment that is constructed according to the foregoing description is substantially the same as the data transfer system according to the first embodiment shown in FIG. 1, and despite the plurality of memory devices  5 - 0 - 5 -q, the circuits for verifying the correctness of data transfers are in host adapters  2 - 0 - 2 -p, which are the sources of data transfer, and data can therefore be spread between memory devices  5 - 0 - 5 -q and transferred.  
       THIRD EMBODIMENT  
       [0081]    We now refer to FIG. 4, in which is shown a circuit block diagram of the configuration of the data transfer system according to the third embodiment of the present invention.  
         [0082]    The data transfer system according to this embodiment includes crossbar circuit  6  connected as a device for repeating in communication between host device  1  and memory device  5 . To state in greater detail, the principal components of the data transfer system according to this embodiment are constituted by: host devices  1 - 0  and  1 - 1 ; host adapters  2 - 0  and  2 - 1 ; crossbar circuits  6 - 0  and  6 - 1 ; memory adapters  4 - 0 - 4 - 3 ; and memory devices  5 - 0 - 5 - 3 .  
         [0083]    Host adapters  2 - 0  and  2 - 1  are constituted to include: data buffers  21 - 0  and  21 - 1 ; the block CRC code to CRC code conversion circuits  22 - 0  and  22 - 1 ; CRC code check circuits  23 - 0  and  23 - 1 ; bus interfaces  24 - 0  and  24 - 1 ; and host control circuits  25 - 0  and  25 - 1 , respectively.  
         [0084]    Crossbar circuits  6 - 0  and  6 - 1  are constituted to include: bus interfaces  61 - 0  and  61 - 1 ; data, buffers  62 - 0 - 64 - 0  and  62 - 1 - 64 - 1 , and bus interfaces  65 - 0  and  65 - 1 , respectively.  
         [0085]    Memory adapters  4 - 0 - 4 - 3  are constituted to include: data buffers  41 - 0 - 41 - 3 ; block CRC code generation circuits  42 - 0 - 42 - 3 ; and bus interfaces  43 - 0 - 43 - 3 , respectively.  
         [0086]    The data transfer system according to the third embodiment is configured to allow any host device  1  to access all memory devices  5 , and the configurations of host adapters  2  and memory adapters  4  do not differ greatly from the configurations in the data transfer systems according to the first and second embodiments that are shown in FIG. 1 and FIG. 3 with the exception of the provision of bus interfaces  24  and bus interfaces  43 .  
         [0087]    In the data transfer system according to the third embodiment that is constituted as described above, although host adapters  2  spread and store data blocks among memory devices  5 , the correspondence check of CRC code is carried out in CRC code check circuits  23  in host adapter  2  that is the data transfer source, and the data blocks can therefore be spread among memory devices  5  and retained, with the effect that high-speed data transfer can be performed by means of the striping operation of memory devices  5 .  
         [0088]    On the other hand, not only is the correspondence check of the CRC codes carried out at all host adapters  2 , but data blocks are used that have been memory-written to memory devices  5 , whereby the advantage is obtained that data can be promptly checked in the event of alteration of data due to hardware breakdown or operation noise even if the hardware for repeating data transfer such as crossbar circuit  6  lacks the capability to check data.  
         [0089]    Next, as an actual embodiment that is based on the data transfer system according to the first embodiment shown in FIG. 1, a concrete and detailed explanation is next presented for embodiment-1 regarding the generation of block CRC code by block CRC code generation circuit  42  and the reconstruction of CRC codes by the block CRC code to CRC code conversion circuits  22 .  
         [0090]    Referring now to FIG. 5, the data that are transferred from host device  1  to host adapter  2  are constituted by an 8-byte header that includes: command code indicating a transfer command that accords with the protocol of system bus  3 , a channel number indicating the type of channel used in the transfer, data length indicating the length of the sector data, and a memory address; and 512 bytes of sector data that include an 8-byte trailer. The trailer is made up by one byte of CRC code and seven bytes that are all zero. When transferring sector data, host device  1  must perform a variety of data transfers such as the channel for transferring sector data, the channel for transferring directory information and file names of the sector data, and the channel for generating parity that is unique to RAID (Redundant Arrays of Inexpensive Disks). These transfers are designated by host device  1  that defines the address space in advance, and the channel numbers are embedded as a portion of the header.  
         [0091]    Referring now to FIG. 6, data that are transferred from host adapter  2  to memory adapter  4  are made up by: an eight-byte header that includes: command code indicating transfer commands that accords with the protocol of system bus  3 , a channel number indicating the type of channel used in the transfer, a block number indicating the number of data blocks that are being transferred, data length indicating the length of the data blocks, and the memory address; and 16-byte data blocks. For data blocks that are partitioned into 16-byte units as the data length that is transferred on a channel, the block number is set such that the initial value is 0 when the data transfer begins and then incremented by +1 with each 16-byte unit.  
         [0092]    Referring now to FIG. 7, a data block that is memory-written from memory adapter  4  to memory device  5  is constituted by a 12-bit header, which is a ROW/COLUMN address, and a 16-byte data block.  
         [0093]    Referring to FIG. 8, the eight-byte write reply that is returned from memory adapter  4  to host adapter  2  is constituted by: a command code indicating a transfer command that accords with the protocol of system bus  3 , a channel number indicating the type of channel used in the transfer, a block number indicating the number of the data block that is being transferred, data length indicating the length of the data blocks, and result status, which is status information of the transfer results. In addition, one byte of block CRC code is stored at the tail end of the result status.  
         [0094]    [0094]FIG. 9 shows the principles of operation of the data transfer system of this embodiment.  
         [0095]    [0095]FIG. 10 is a circuit block diagram showing the normal unit structure of a CRC arithmetic circuit and an example of the unit structure of a CRC arithmetic circuit following a change in the computation sequence.  
         [0096]    [0096]FIG. 11 is a circuit block diagram showing an example of the unit structure of a CRC arithmetic circuit that is used in the present embodiment.  
         [0097]    [0097]FIG. 12 is a circuit block diagram showing an example of the overall structure of a CRC arithmetic circuit that is used in the present embodiment.  
         [0098]    Since CRC code is represented by one byte (8 bits), if primitive polynomial G(x)=x 8 +x 5 +x 4 +x 3 +1 on finite field GF(2 8 ) is considered (Refer to: Imai Hideki, Electronics Essentials, No. 20: “The Essentials of Error Correcting Coding Techniques,” Nihon Kogyo Gijutsu Center, p.164-p.169), an arbitrary number on finite field GF(2 8 ) is represented by, for example, an eight-bit vector such as shown in the following equation, where α is the root (primitive element). In addition, the full-sized upper-case letters shown below indicate vectors and matrices, and the half-sized lower-case letters indicate the elements of vectors and matrices.  
             0   =     [     0   ,   0   ,   0   ,   0   ,   0   ,   0   ,   0   ,   0     ]                             1   =     [     1   ,   0   ,   0   ,   0   ,   0   ,   0   ,   0   ,   0     ]                             α   =     [     0   ,   1   ,   0   ,   0   ,   0   ,   0   ,   0   ,   0     ]                               α   2     =     [     0   ,   0   ,   1   ,   0   ,   0   ,   0   ,   0   ,   0     ]                               α   3     =     [     0   ,   0   ,   0   ,   1   ,   0   ,   0   ,   0   ,   0     ]                               α   4     =     [     0   ,   0   ,   0   ,   0   ,   1   ,   0   ,   0   ,   0     ]                               α   5     =     [     0   ,   0   ,   0   ,   0   ,   0   ,   1   ,   0   ,   0     ]                               α   6     =     [     0   ,   0   ,   0   ,   0   ,   0   ,   0   ,   1   ,   0     ]                               α   7     =     [     0   ,   0   ,   0   ,   0   ,   0   ,   0   ,   0   ,   1     ]                               α   8     =     [     1   ,   0   ,   0   ,   1   ,   1   ,   1   ,   0   ,   0     ]             (     =       α   5     +     α   4     +     α   3     +   1       )                 α   9     =     [     0   ,   1   ,   0   ,   0   ,   1   ,   1   ,   1   ,   0     ]             (     =       α   6     +     α   5     +     α   4     +   α       )             ⋮                           α   254     =     [     0   ,   0   ,   1   ,   1   ,   1   ,   0   ,   0   ,   1     ]             (     =       α   7     +     α   4     +     α   3     +     α   2         )                 α   255     =     [     1   ,   0   ,   0   ,   0   ,   0   ,   0   ,   0   ,   0     ]             (     =   1     )                               
 
         [0099]    The operations for these numbers on finite field GF(2 8 ) that are represented by these vectors are realized by vector operations by an 8×8 matrix. To obtain a cyclic code that takes primitive polynomial G(x) as a generator, association matrix T resulting from primitive polynomial G(x) may be used as a transformation matrix.  
             T   =     [         00000001           10000000           01000000           00100001           00010001           00001001           00000100           00000010         ]             [     Equation                 1     ]                               
 
         [0100]    The generation of CRC codes using association matrix T is carried out as described below.  
         [0101]    R(r( 0 ) . . . r( 7 )) is the vector representation of the register that stores CRC codes, and R 1 (ri( 0 ) . . . ri( 7 )) is the value of the CRC codes when the ith item of data Di(di( 0 ) . . . di( 7 ) is read.  
         [0102]    R 0 (r 0 ( 0 ) . . . r 0 ( 7 ))=TD 0 (d 0 ( 0 ) . . . d 0 ( 7 ))  
         [0103]    Ri+1=T {Ri (ri( 0 ) . . . ri( 7 ))+Di (di( 0 ) . . . di( 7 ))} 
         [0104]    Calculating Ri+1 row by row results in Formula 1.  
       Formula 1  
         ri + 1 ( 0 )= ri ( 7 )+ di ( 7 )  
           ri + 1 ( 1 )= ri ( 0 )+ di ( 0 )  
           ri + 1 ( 2 )= ri ( 1 )+ di ( 1 )+ ri ( 7 )+ di ( 7 )  
           ri + 1 ( 3 )= ri ( 1 )+ di ( 1 )+ ri ( 7 )+ di ( 7 )  
           ri + 1 ( 3 )= ri ( 2 )+ di ( 2 )+ ri ( 7 )+ di ( 7 )  
           ri + 1 ( 4 )= ri ( 3 )+ di ( 3 )+ ri ( 7 )+ di ( 7 )  
           ri + 1 ( 5 )= ri ( 4 )+ di ( 4 )  
           ri + 1 ( 6 )= ri ( 5 )+ di ( 5 )  
           ri + 1 ( 7 )= ri ( 6 )+ di ( 6 )  
         [0105]    However, because this is addition on finite field GF(2 8 ), the actual logical operation is an exclusive OR operation resulting in Formula 2. In the following formula, @ is an operator that indicates an exclusive OR operation.  
       Formula 2  
         ri + 1 ( 0 )= ri ( 7 )@ di ( 7 )  
           ri + 1 ( 1 )= ri ( 0 )@ di ( 0 )  
           ri + 1 ( 2 )= ri ( 1 )@ di ( 1 )@ ri ( 7 )@ di ( 7 )  
           ri + 1 ( 3 )= ri ( 2 )@ di ( 2 )@ ri ( 7 )@ di ( 7 )  
           ri + 1 ( 4 )= ri ( 3 )@ di ( 3 )@ ri ( 7 )@ di ( 7 )  
           ri + 1 ( 5 )= ri ( 4 )@ di ( 4 )  
           ri + 1 ( 6 )= ri ( 5 )@ di ( 5 )  
           ri + 1 ( 7 )= ri ( 6 )@ di ( 6 )  
         [0106]    Formula 2 is the CRC operation result when Ri(ri( 0 ) . . . ri( 7 )) reaches the current step, and an operation of this result and data Di(di( 0 ) . . . di( 7 )) by association matrix T finds the CRC code of the next step, which is the operation result.  
         [0107]    The calculation method in Formula 2 involves generating the one-byte CRC code R 1 (r 1 ( 0 ) . . . r 1 ( 7 )) from the two-byte data string of R 0 (r 0 ( 0 ) . . . r 0  ( 7 )) and D 0 (d 0 ( 0 ) . . . d( 7 )), but finding R 16 (r 16 ( 0 ) . . . r 16 ( 7 )), which generates a 16-byte portion data string, determines the block CRC codes when one data block is 16 bytes. In this regard, only “i” in Formula 2 changes, and Formula 3 can be found.  
       Formula 3  
         r   16 ( 0 )= r   15 ( 7 )@ d   15 ( 7 )  
           r   16 ( 1 )= r   15 ( 0 )@ d   15 ( 0 )  
           r   16 ( 2 )= r   15 ( 1 )@ d   15 ( 1 )@ r   15 ( 7 )@ d   15 ( 7 )  
           r   16 ( 3 )= r   15 ( 2 )@ d   15 ( 2 )@ r   15 ( 7 )@ d   15 ( 7 )  
           r   16 ( 4 )= r   15 ( 3 )@ d   15 ( 3 )@ r   15 ( 7 )@ d   15 ( 7 )  
           r   16 ( 5 )= r   15 ( 4 )@ d   15 ( 4 )  
           r   16 ( 6 )= r   15 ( 5 )@ d   15 ( 5 )  
           r   16 ( 7 )= r   15 ( 6 )@ d   15 ( 6 )  
         [0108]    Similarly, Formula 4 is resulted as R 15 (r 15 ( 0 ) . . . r 15 ( 7 )), and this is developed to between from R 14 (r 14 ( 0 ) . . . r 14 ( 7 )) to R 2 (r 2 ( 0 ) . . . r 2 ( 7 )).  
       Formula 4  
         r   15 ( 0 )= r   14 ( 7 )@ d   14 ( 7 )  
           r   15 ( 1 )= r   14 ( 0 )@ d   14 ( 0 )  
           r   15 ( 2 )= r   14 ( 1 )@ d   14 ( 1 )@ r   14 ( 7 )@ d   14 ( 7 )  
           r   15 ( 3 )= r   14 ( 2 )@ d   14 ( 2 )@ r   14 ( 7 )@ d   14 ( 7 )  
           r   15 ( 4 )= r   14 ( 3 )@ d   14 ( 3 )@ r   14 ( 7 )@ d   14 ( 7 )  
           r   15 ( 5 )= r   14 ( 4 )@ d   14 ( 4 )  
           r   15 ( 6 )= r   14 ( 5 )@ d   14 ( 5 )  
           r   15 ( 7 )= r   14 ( 6 )@ d   14 ( 6 )  
         [0109]    As for the formula for calculating R 1 (r 1 ( 0 ) . . . r 1 ( 7 )) that is originally calculated first, although the preceding operation result exists as R 0 (r 0 ( 0 ) . . . r 0 ( 7 )), it can here be represented as Formula 5 if redefined as initial value Z(z( 0 ) . . . z ( 7 )) for R 0 (r 0 ( 0 ) . . . r 0 ( 7 )). Regarding R 16 (r 16 ( 0 ) . . . r 16 ( 7 )), which is  16  bytes of block CRC code, the formula is calculated based on data D 0 (d 0 ( 0 ) . . . d 0 ( 7 )) to D 15 (d 15 ( 0 ) . . . d 15 ( 7 )) and the initial value Z(z( 0 ) . . . z( 7 )) at the time of this calculation.  
       Formula 5  
         r   1 ( 0 )= z ( 7 )@ d   0 ( 7 )  
           r   1 ( 1 )= z ( 0 )@ d   0 ( 0 )  
           r   1 ( 2 )= z ( 1 )@ d   0 ( 1 )@ z ( 7 )@ d   0 ( 7 )  
           r   1 ( 3 )= z ( 2 )@ d   0 ( 2 )@ z ( 7 )@ d   0 ( 7 )  
           r   1 ( 4 )= z ( 3 )@ d   0 ( 3 )@ z ( 7 )@ d   0 ( 7 )  
           r   1 ( 5 )= z ( 4 )@ d   0 ( 4 )  
           r   1 ( 6 )= z ( 5 )@ d   0 ( 5 )  
           r   1 ( 7 )= z ( 6 )@ d   0 ( 6 )  
         [0110]    At this time, the block CRC codes R 16 (r 16 ( 0 ) . . . r 16 ( 7 )) that were found for Formula 3 are used to find the CRC operation results that are carried out on D 0 (d 0 ( 0 )) . . . d 0 ( 7 )) to D 15 (d 15 ( 0 ) . . . d 15 ( 7 )) when the initial value is Z(z( 0 ) . . . z( 7 )).  
         [0111]    Accordingly, the condition is set that the data that are transferred are the same, and both R 16 (r 16 ( 0 ) . . . r 16 ( 7 )) having the operation result that initial values are Z(z( 0 ) . . . z( 7 )) and R′ 16 (r′ 16 ( 0 ) . . . r′ 16 ( 7 )) having the operation result that the initial values are “00” are found; and if the difference between R′ 16 (r′ 16 ( 0 ) . . . r′ 16 ( 7 )) and R 16 (r 16 ( 0 ) . . . r 16 ( 7 )) can be defined as Δ R 16 (Δr 16 ( 0 ) . . . Δr 16 ( 7 )), R 16 (r 16 ( 0 ) . . . r 16 ( 7 )) can be generated from R′ 16 (r′ 16 ( 0 ) . . . r′ 16 ( 7 )) and ΔR 16 (Δr 16 ( 0 ) . . . Δr 16 ( 7 )).  
         [0112]    R′ 16 (r′ 16 ( 0 ) . . . r′ 16 ( 7 )) is found by Formula 6 based on the fact that the initial value is “00” in Formula 3.  
       Formula 6  
         r ′ 16 ( 0 )= r ′ 15 ( 7 )@ d   15 ( 7 )  
           r ′ 16 ( 1 )= r ′ 15 ( 0 )@ d   15 ( 0 )  
           r ′ 16 ( 2 )= r ′ 15 ( 1 )@ d   15 ( 1 )@ r ′ 15 ( 7 )@ d   15 ( 7 )  
           r ′ 16 ( 3 )= r ′ 15 ( 2 )@ d   15 ( 2 )@ r ′ 15 ( 7 )@ d   15 ( 7 )  
           r ′ 16 ( 4 )= r ′ 15 ( 3 )@ d   15 ( 3 )@ r ′ 15 ( 7 )@ d   15 ( 7 )  
           r ′ 16 ( 5 )= r ′ 15 ( 4 )@ d   15 ( 4 )  
           r ′ 16 ( 6 )= r ′ 15 ( 5 )@ d   15 ( 5 )  
           r ′ 16 ( 7 )= r ′ 15 ( 6 )@ d   15 ( 6 )  
         [0113]    Similarly, Formula 7 is resulted from R′ 15 (r′ 15 ( 0 ) . . . r′ 15 ( 7 )) and is developed to the formula between from R′ 14 (r′ 14 ( 0 ) . . . r′ 14 ( 7 )) to R′ 2 (r′ 2 ( 0 ) . . . r′ 2 ( 7 )).  
       Formula 7  
         r ′ 15 ( 0 )= r ′ 14 ( 7 )@ d   14 ( 7 )  
           r ′ 15 ( 1 )= r ′ 14 ( 0 )@ d   14 ( 0 )  
           r ′ 15 ( 2 )= r ′ 14 ( 1 )@ d   14 ( 1 )@ r ′ 14 ( 7 )@ d   14 ( 7 )  
           r ′ 15 ( 3 )= r ′ 14 ( 2 )@ d   14 ( 2 )@ r ′ 14 ( 7 )@ d   14 ( 7 )  
           r ′ 15 ( 4 )= r ′ 14 ( 3 )@ d   14 ( 3 )@ r ′ 14 ( 7 )@ d   14 ( 7 )  
           r ′ 15 ( 5 )= r ′ 14 ( 4 )@ d   14 ( 4 )  
           r ′ 15 ( 6 )= r ′ 14 ( 5 )@ d   14 ( 5 )  
           r ′ 15 ( 7 )= r ′ 14 ( 6 )@ d   14 ( 6 )  
         [0114]    Regarding the formula R′ 1 (r′( 0 ) . . . r′ 1 ( 7 )) which is calculated at first substantively, R 0 (r 1 ( 0 ) . . . r 1 ( 7 )) exists as the preceding operation results, although the initial value “00” is inserted to R 0 (r 1 ( 0 ) . . . r 1 ( 7 )) to produce Formula 8.  
       Formula 8  
         r ′ 1 ( 0 )= d   0 ( 7 )  
           r ′ 1 ( 1 )= d   0 ( 0 )  
           r ′ 1 ( 2 )= d   0 ( 1 )@ d   0 ( 7 )  
           r ′ 1 ( 3 )= d   0 ( 2 )@ d   0 ( 7 )  
           r ′ 1 ( 4 )= d   0 ( 3 )@ d   0 ( 7 )  
           r ′ 1 ( 5 )= d   0 ( 4 )  
           r ′ 1 ( 6 )= d   0 ( 5 )  
           r ′ 1 ( 7 )= d   0 ( 6 )  
         [0115]    R 16 (r 16 ( 0 ) . . . r 16 ( 7 )) is defined to equal R 16 (r 16 ( 0 ) . . . r 16 ( 7 ))@R′ 16 (r′ 16 ( 0 ) . . . r′ 16 ( 7 )), and when the difference ΔR 16 (Δr 16 ( 0 ) . . . Δr 16 ( 7 )) between R 16 (r 16 ( 0 ) . . . r 16 ( 7 )) and R′ 16 (r′ 16 ( 0 ) . . . r′ 16 ( 7 )) is found, the formula ΔR 16 (Δr 16 ( 0 ) . . . Δr 16 ( 7 )=R 16 (r 16 ( 0 ) . . . r 16 ( 7 ))@R′ 16 (r′ 16 ( 0 ) . . . r′ 16 ( 7 )) is used.  
         [0116]    At this time, however, data Di(di( 0 ) . . . di( 7 )) transfers the same data, and only the difference between R 16 (r 16 ( 0 ) . . . r 16 ( 7 )), which is Formula 3, and R′ 16 (r′ 16 ( 0 ) . . . r′ 16 ( 7 )), which is Formula 4, is the difference between R 1 (r 1 ( 0 ) . . . r 1 ( 7 )) and R′ 1 (r′ 1 ( 0 ) . . . r′ 1 ( 7 )).  
         [0117]    (1) The Calculation of ΔR 1 (Δr 1 ( 0 ) . . . Δr 1 ( 7 ))  
         [0118]    Accordingly, Formula 9 is found for ΔR 1 (Δr 1 ( 0 ) . . . Δr 1 ( 7 )) at the step of transferring the first data.  
       Formula 9  
       Δ r   1 ( 0 )= r   1 ( 0 )@ r ′ 1 ( 0 )={ d ( 7 )@ z ( 7 )}@{ d ( 7 )}= z ( 7 )  
         Δ r   1 ( 1 )= r   1 ( 1 )@ r ′ 1 ( 1 )={ d ( 0 )@ z ( 0 )}@{ d ( 0 )}= z ( 0 )  
         Δ r   1 ( 2 )= r   1 ( 2 )@ r ′ 1 ( 2 )= {d ( 1 )@ z ( 1 )}@{ d ( 1 )@ d ( 7 )@ z ( 7 )}@{ d ( 1 )@ d ( 7 )}= z ( 1 )@ z ( 7 )  
         Δ r   1 ( 3 )= r   1 ( 3 )@ r ′ 1 ( 3 )= {d ( 2 )@ z ( 2 )}@{ d ( 2 )@ d ( 7 )@ z ( 7 )}@{ d ( 2 )@ d ( 7 )}= z ( 2 )@ z ( 7 )  
         Δ r   1 ( 4 )= r   1 ( 4 )@ r ′ 1 ( 4 )= {d ( 3 )@ z ( 3 )}@{ d ( 3 )@ d ( 7 )@ z ( 7 )}@{ d ( 3 )@ d ( 7 )}= z ( 3 )@ z ( 7 )  
         Δ r   1 ( 5 )= r   1 ( 5 )@ r ′ 1 ( 5 )={ d ( 4 )@ z ( 4 )}@{ d ( 4 )}= z ( 4 )  
         Δ r   1 ( 6 )= r   1 ( 6 )@ r ′ 1 ( 6 )={ d ( 5 )@ z ( 5 )}@{ d ( 5 )}= z ( 5 )  
         Δ r   1 ( 7 )= r   1 ( 7 )@ r ′ 1 ( 7 )={ d ( 6 )@ z ( 6 )}@{ d ( 6 )}= z ( 6 )  
         [0119]    Formula 9 for finding this ΔR 2 (Δr 1 ( 0 ) . . . Δr 1 ( 7 )) is equivalent to the formula in R 1 (r 1 ( 0 ) . . . r 1 ( 7 )) in Formula 3 in which data D 0 (d 0 ( 0 ) . . . d 0 ( 7 )) is “00.” 
         [0120]    Accordingly, when finding ΔR 16 (Δr 16 ( 0 ) . . . Δr 16 ( 7 )) as well, since ΔR 16 (Δr 16 ( 0 ) . . . Δr 16 ( 7 )) can be found by finding the case in which all data D 0 (d 0 ( 0 ) . . . d 0 ( 7 )) to D 15 (d 15 ( 0 ) . . . d 15 ( 7 )) are made “00” in Formula 3, R 16 (r 16 ( 0 ) . . . r 16  ( 7 )) can be found by applying Formula 3 for a case in which data are made “00” successively from ΔR 2 (Δr 2 ( 0 ) . . . Δr 2 ( 7 )) to ΔR 16 (Δr 16 ( 0 ) . . . Δr 16 ( 7 )).  
         [0121]    (2) The Calculation of ΔR 2 (Δr 2 ( 0 ) . . . Δr 2 ( 7 ))  
       Formula 10  
       Δ r   2 ( 0 )=Δ r   1 ( 7 )  
         Δ r   2 ( 1 )=Δ r   1 ( 0 )  
         Δ r   2 ( 2 )=Δ r   1 ( 1 )@ Δ r   1 ( 7 )  
         Δ r   2 ( 3 )=Δ r   1 ( 2 )@ Δ r   1 ( 7 )  
         Δ r   2 ( 4 )=Δ r   1 ( 3 )@ Δ r   1 ( 7 )  
         Δ r   2 ( 5 )=Δ r   1 ( 4 )  
         Δ r   2 ( 6 )=Δ r   1 ( 5 )  
         Δ r   2 ( 7 )=Δ r   1 ( 6 )  
         [0122]    ΔR 1 (Δr 1 ( 0 ) . . . Δr 1 ( 7 )) is shown in Formula 9, resulting in Formula 11.  
       Formula 11  
       Δ r   2 ( 0 )= z ( 6 )  
         Δ r   2 ( 1 )= z ( 7 )  
         Δ r   2 ( 2 )= z ( 0 )@ z ( 6 )  
         Δ r   2 ( 3 )= z ( 1 )@ z ( 7 )@ z ( 6 )  
         Δ r   2 ( 4 )= z ( 2 )@ z ( 7 )@ z ( 6 )  
         Δ r   2 ( 5 )= z ( 3 )@ z ( 7 )  
         Δ r   2 ( 6 )= z ( 4 )  
         Δ r   2 ( 7 )= z ( 5 )  
         [0123]    (3) The Calculation of ΔR 3 (Δr 3 ( 0 ) . . . Δr 3 ( 7 ))  
       Formula 12  
       Δ r   3 ( 0 )=Δ r   2 ( 7 )  
         Δ r   3 ( 1 )=Δ r   2 ( 0 )  
         Δ r   3 ( 2 )=Δ r   2 ( 1 )@Δ r   2 ( 7 )  
         Δ r   3 ( 3 )=Δ r   2 ( 2 )@Δ r   2 ( 7 )  
         Δ r   3 ( 4 )=Δ r   2 ( 3 )@Δ r   2 ( 7 )  
         Δ r   3 ( 5 )=Δ r   2 ( 4 )  
         Δ r   3 ( 6 )=Δ r   2 ( 5 )  
         Δ r   3 ( 7 )=Δ r   2 ( 6 )  
         [0124]    ΔR 2 (Δr 2 ( 0 ) . . . Δr 2 ( 7 )) is shown in Formula 11, resulting in Formula 13.  
       Formula 13  
       Δ r   3 ( 0 )= z ( 5 )  
         Δ r   3 ( 1 )= z ( 6 )  
         Δ r   3 ( 2 )= z ( 7 )@ z ( 5 )  
         Δ r   3 ( 3 )= z ( 0 )@ z ( 6 )@ z ( 5 )  
         Δ r   3 ( 4 )= z ( 1 )@ z ( 7 )@ z ( 6 )@ z ( 5 )  
         Δ r   3 ( 5 )= z ( 2 )@ z ( 7 )@ z ( 6 )  
         Δ r   3 ( 6 )= z ( 3 )@( 7 )  
         Δ r   3 ( 7 )= z ( 4 )  
         [0125]    (4) The Calculation of ΔR 4 (Δr 4 ( 0 ) . . . Δr 4 ( 7 ))  
       Formula 14  
       Δ r   4 ( 0 )=Δ r   3 ( 7 )  
         Δ r   4 ( 1 )=Δ r   3 ( 0 )  
         Δ r   4 ( 2 )=Δ r   3 ( 1 )@Δ r   3 ( 7 )  
         Δ r   4 ( 3 )=Δ r   3 ( 2 )@Δ r   3 ( 7 )  
         Δ r   4 ( 4 )=Δ r   3 ( 3 )@Δ r   3 ( 7 )  
         Δ r   4 ( 5 )=Δ r   3 ( 4 )  
         Δ r   4 ( 6 )=Δ r   3 ( 5 )  
         Δ r   4 ( 7 )=Δ r   3 ( 6 )  
         [0126]    ΔR 3 (Δr 3 ( 0 ) . . . Δr 3 ( 7 )) is shown in Formula 13, resulting in Formula 15.  
       Formula 15  
       Δ r   4 ( 0 )= z ( 4 )  
         Δ r   4 ( 1 )= z ( 5 )  
         Δ r   4 ( 2 )= z ( 6 )@ z ( 4 )  
         Δ r   4 ( 3 )= z ( 7 )@ z ( 5 )@ z ( 4 )  
         Δ r   4 ( 4 )= z ( 0 )@ z ( 6 )@ z ( 5 )@ z ( 4 )  
         Δ r   4 ( 5 )= z ( 1 )@ z ( 7 )@ z ( 6 )@ z ( 5 )  
         Δ r   4 ( 6 )= z ( 2 )@ z ( 7 )@ z ( 6 )  
         Δ r   4 ( 7 )= z ( 3 )@ z ( 7 )  
         [0127]    (5) The Calculation of ΔR 5 (Δr 5 ( 0 ) . . . Δr 5 ( 7 ))  
       Formula 16  
       Δ r   5 ( 0 )=Δ r   4 ( 7 )  
         Δ r   5 ( 1 )=Δ r   4 ( 0 )  
         Δ r   5 ( 2 )=Δ r   4 ( 1 )@Δ r   4 ( 7 )  
         Δ r   5 ( 3 )=Δ r   4 ( 2 )@Δ r   4 ( 7 )  
         Δ r   5 ( 4 )=Δ r   4 ( 3 )@Δ r   4 ( 7 )  
         Δ r   5 ( 5 )=Δ r   4 ( 4 )  
         Δ r   5 ( 6 )=Δ r   4 ( 5 )  
         Δ r   5 ( 7 )=Δ r   4 ( 6 )  
         [0128]    ΔR 4 (Δr 4 ( 0 ) . . . Δr 4 ( 7 )) is shown in Formula 15, resulting in Formula 17.  
       Formula 17  
       Δ r   5 ( 0 )= z ( 3 )@ z ( 7 )  
         Δ r   5 ( 1 )= z ( 4 )  
         Δ r   5 ( 2 )= z ( 5 )@ z ( 3 )@ z ( 7 )  
         Δ r   5 ( 3 )= z ( 6 )@ z ( 4 )@ z ( 3 )@ z ( 7 )  
         Δ r   5 ( 4 )= z ( 7 )@ z ( 5 )@ z ( 4 )@ z ( 3 )@ z ( 7 )  
         Δ r   5 ( 5 )= z ( 0 )@ z ( 6 )@ z ( 5 )@ z ( 4 )  
         Δ r   5 ( 6 )= z ( 1 )@ z ( 7 )@ z ( 6 )@ z ( 5 )  
         Δ r   5 ( 7 )= z ( 2 )@ z ( 7 )@ z ( 6 )  
         [0129]    (6) The Calculation of ΔR 6 (Δr 6 ( 0 ) . . . Δr 6 ( 7 ))  
       Formula 18  
       Δ r   6 ( 0 )=Δ r   5 ( 7 )  
         Δ r   6 ( 1 )=Δ r   5 ( 0 )  
         Δ r   6 ( 2 )=Δ r   5 ( 1 )@Δ r   5 ( 7 )  
         Δ r   6 ( 3 )=Δ r   5 ( 2 )@Δ r   5 ( 7 )  
         Δ r   6 ( 4 )=Δ r   5 ( 3 )@Δ r   5 ( 7 )  
         Δ r   6 ( 5 )=Δ r   5 ( 4 )  
         Δ r   6 ( 6 )=Δ r   5 ( 5 )  
         Δ r   6 ( 7 )=Δ r   5 ( 6 )  
         [0130]    ΔR 5 (Δr 5 ( 0 ) . . . Δr 5 ( 7 )) is shown in Formula 17, resulting in Formula 19.  
       Formula 19  
       Δ r   6 ( 0 )= z ( 2 )@ z ( 7 )@ z ( 6 )  
         Δ r   6 ( 1 )= z ( 3 )@ z ( 7 )  
         Δ r   6 ( 2 )= z ( 4 )@ z ( 2 )@ z ( 7 )@ z ( 6 )  
         Δ r   6 ( 3 )= z ( 5 )@ z ( 3 )@ z ( 7 )@ z ( 2 )@ z ( 7 )@ z ( 6 )  
         Δ r   6 ( 4 )= z ( 6 )@ z ( 4 )@ z ( 3 )@ z ( 7 )@ z ( 2 )@ z ( 7 )@ z ( 6 )  
         Δ r   6 ( 5 )= z ( 7 )@ z ( 5 )@ z ( 4 )@ z ( 3 )@ z ( 7 )  
         Δ r   6 ( 6 )= z ( 0 )@ z ( 6 )@ z ( 5 )@ z ( 4 )  
         Δ r   6 ( 7 )= z ( 1 )@ z ( 7 )@ z ( 6 )@ z ( 5 )  
         [0131]    (7) The Calculation of ΔR 7 (Δr 7 ( 0 ) . . . Δr 7 ( 7 ))  
       Formula 20  
       Δ r   7 ( 0 )=Δ r   6 ( 7 )  
         Δ r   7 ( 1 )=Δ r   6 ( 0 )  
         Δ r   7 ( 2 )=Δ r   6 ( 1 )@Δ r   6 ( 7 )  
         Δ r   7 ( 3 )=Δ r   6 ( 2 )@Δ r   6 ( 7 )  
         Δ r   7 ( 4 )=Δ r   6 ( 3 )@Δ r   6 ( 7 )  
         Δ r   7 ( 5 )=Δ r   6 ( 4 )  
         Δ r   7 ( 6 )=Δ r   6 ( 5 )  
         Δ r   7 ( 7 )=Δ r   6 ( 6 )  
         [0132]    ΔR 6 (Δr 6 ( 0 ) . . . Δr 6 ( 7 )) is shown in Formula 19, resulting in Formula 21.  
       Formula 21  
       Δ r   7 ( 0 )= z ( 1 )@ z ( 7 )@ z ( 6 )@ z ( 5 )  
         Δ r   7 ( 1 )= z ( 2 )@ z ( 7 )@ z ( 6 )  
         Δ r   7 ( 2 )= z ( 3 )@ z ( 7 )@ z ( 1 )@ z ( 7 )@ z ( 6 )@ z ( 5 )  
         Δ r   7 ( 3 )= z ( 4 )@ z ( 2 )@ z ( 7 )@ z ( 6 )@ z ( 1 )@ z ( 7 )@ z ( 6 )@ z ( 5 )  
         Δ r   7 ( 4 )= z ( 5 )@ z ( 3 )@ z ( 7 )@ z ( 2 )@ z ( 7 )@ z ( 6 )@ z ( 1 )@ z ( 7 )@ z ( 6 )@ z ( 5 )  
         Δ r   7 ( 5 )= z ( 6 )@ z ( 4 )@ z ( 3 )@ z ( 7 )@ z ( 2 )@ z ( 7 )@ z ( 6 )  
         Δ r   7 ( 6 )= z ( 7 )@ z ( 5 )@ z ( 4 )@ z ( 3 )@Z ( 7 )  
         Δ r   7 ( 7 )= z ( 0 )@ z ( 6 )@ z ( 5 )@ z ( 4 )  
         [0133]    (8) The Calculation of ΔR 8 (Δr 8 ( 0 ) . . . Δr 8 ( 7 ))  
       Formula 22  
       Δ r   8 ( 0 )=Δ r   7 ( 7 )  
         Δ r   8 ( 1 )=Δ r   7 ( 0 )  
         Δ r   8 ( 2 )=Δ r   7 ( 1 )@Δ r   7 ( 7 )  
         Δ r   8 ( 3 )=Δ r   7 ( 2 )@Δ r   7 ( 7 )  
         Δ r   8 ( 4 )=Δ r   7 ( 3 )@Δ r   7 ( 7 )  
         Δ r   8 ( 5 )=Δ r   7 ( 4 )  
         Δ r   8 ( 6 )=Δ r   7 ( 5 )  
         Δ r   8 ( 7 )=Δ r   7 ( 6 )  
         [0134]    ΔR 7 (Δr 7 ( 0 ) . . . Δr 7 ( 7 )) is shown in Formula 21, resulting in both Formula 23 and Formula 24.  
       Formula 23  
       Δ r   8 ( 0 )= z ( 0 )@ z ( 6 )@ z ( 5 )@ z ( 4 )  
         Δ r   8 ( 1 )= z ( 1 )@ z ( 7 )@ z ( 6 )@ z ( 5 )  
         Δ r   8 ( 2 )= z ( 2 )@ z ( 7 )@ z ( 6 )@ z ( 0 )@ z ( 6 )@ z ( 5 )@ z ( 4 )  
         Δ r   8 ( 3 )= z ( 3 )@ z ( 7 )@ z ( 1 )@ z ( 7 )@ z ( 6 )@ z ( 5 )@ z ( 0 )@ z ( 6 )@ z ( 5 )@ z ( 4 )  
         Δ r   8 ( 4 )= z ( 4 )@( 2 )@ z ( 7 )@ z ( 6 )@ z ( 1 )@ z ( 7 )@ z ( 6 )@ z ( 5 )@ z ( 0 )@ z ( 6 )@ z ( 5 )@ z ( 4 )  
         Δ r   8 ( 5 )= z ( 5 )@ z ( 3 )@ z ( 7 )@ z ( 2 )@ z ( 7 )  z ( 6 )@ z ( 1 )@ z ( 7 )@ z ( 6 )@ z ( 5 )  
         Δ r   8 ( 6 )= z ( 6 )@ z ( 4 )@ z ( 3 )@ z ( 7 )@ z ( 2 )@ z ( 7 )@ z ( 6 )  
         Δ r   8 ( 7 )= z ( 7 )@ z ( 5 )@ z ( 4 )@ z ( 3 )@ z ( 7 )  
       Formula 24  
       Δ r   8 ( 0 )= z ( 0 )@ z ( 6 )@ z ( 5 )@ z ( 4 )= z ( 0 )@ z ( 4 )@ z ( 5 )@ z ( 6 )  
         Δ r   8 ( 1 )= z ( 1 )@ z ( 7 )@ z ( 6 )@ z ( 5 )= z ( 1 )@ z ( 4 )@ z ( 5 )@ z ( 6 )  
         Δ r   8 ( 2 )= z ( 2 )@ z ( 7 )@ z ( 0 )@ z ( 6 )@ z ( 5 )@ z ( 4 )= z ( 0 )@ z ( 2 )@ z ( 4 )@ z ( 5 )@ z ( 7 )  
         Δ r   8 ( 3 )= z ( 3 )@ z ( 1 )@ z ( 0 )@ z ( 4 )= z ( 0 )@ z ( 1 )@ z ( 3 )@ z ( 4 )  
         Δ r   8 ( 4 )= z ( 2 )@ z ( 1 )@ z ( 0 )@ z ( 6 )= z ( 0 )@ z ( 1 )@ z ( 2 )@ z ( 6 )  
         Δ r   8 ( 5 )= z ( 3 )@ z ( 2 )@ z ( 1 )@ z ( 7 )= z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 7 )  
         Δ r   8 ( 6 )= z ( 4 )@ z ( 3 )@ z ( 2 )= z ( 2 )@ z ( 3 )@ z ( 4 )  
         Δ r   8 ( 7 )= z ( 5 )@ z ( 4 )@ z ( 3 )= z ( 3 )@ z ( 4 )@ z ( 5 )  
         [0135]    (9) The Calculation of ΔR 9 (Δr 9 ( 0 ) . . . Δr 9 ( 7 ))  
       Formula 25  
       Δ r   9 ( 0 )=Δ r   8 ( 7 )  
         Δ r   9 ( 1 )=Δ r   8 ( 0 )  
         Δ r   9 ( 2 )=Δ r   8 ( 1 )@Δ r   8 ( 7 )  
         Δ r   9 ( 3 )=Δ r   8 ( 2 )@Δ r   8 ( 7 )  
         Δ r   9 ( 4 )=Δ r   8 ( 3 )@Δ r   8 ( 7 )  
         Δ r   9 ( 5 )=Δ r   8 ( 4 )  
         Δ r   9 ( 6 )=Δ r   8 ( 5 )  
         Δ r   9 ( 7 )=Δ r   8 ( 6 )  
         [0136]    ΔR 8 (Δr 8 ( 0 ) . . . Δr 8 ( 7 )) is shown in Formula 24, resulting in Formula 26.  
       Formula 26  
       Δ r   9  ( 0 )= z ( 3 )@ z ( 4 )@ z ( 5 )  
         Δ r   9  ( 1 )= z ( 0 )@ z ( 4 )@ z ( 5 )@ z ( 6 )  
         Δ r   9  ( 2 )= z ( 1 )@ z ( 5 )@ z ( 6 )@ z ( 7 )@ z ( 3 )@ z ( 4 )@ z ( 5 )  
         Δ r   9  ( 3 )= z ( 0 )@ z ( 2 )@ z ( 4 )@ z ( 5 )@ z ( 7 )@ z ( 3 )@ z ( 4 )@ z ( 5 )  
         Δ r   9  ( 4 )= z ( 0 )@ z ( 1 )@ z ( 3 )@ z ( 4 )@ z ( 3 )@ z ( 4 )@ z ( 5 )  
         Δ r   9  ( 5 )= z ( 0 )@( 1 )@ z ( 2 )@ z ( 6 )  
         Δ r   9  ( 6 )= z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 7 )  
         Δ r   9  ( 7 )= z ( 2 )@ z ( 3 )@ z ( 4 )  
         [0137]    (10) The Calculation of ΔR 10 (Δr 10 ( 0 ) . . . Δr 10 ( 7 ))  
       Formula 27  
       Δ r   10 ( 0 )=Δ r   9 ( 7 )  
         Δ r   10 ( 1 )=Δ r   9 ( 0 )  
         Δ r   10 ( 2 )=Δ r   9 ( 1 )@Δ r   9 ( 7 )  
         Δ r   10 ( 3 )=Δ r   9 ( 2 )@Δ r   9 ( 7 )  
         Δ r   10 ( 4 )=Δ r   9 ( 3 )@Δ r   9 ( 7 )  
         Δ r   10 ( 5 )=Δ r   9 ( 4 )  
         Δ r   10 ( 6 )=Δ r   9 ( 5 )  
         Δ r   10 ( 7 )=Δ r   9 ( 6 )  
         [0138]    ΔR 9 (Δr 9 ( 0 ) . . . Δr 9 ( 7 )) is shown in Formula 26, resulting in both Formula 28 and Formula 29.  
       Formula 28  
       Δ r   10 ( 0 )= z ( 2 )@ z ( 3 )@ z ( 4 )  
         Δ r   10 ( 1 )= z ( 3 )@ z ( 4 )@ z ( 5 )  
         Δ r   10 ( 2 )= z ( 0 )@ z ( 4 )@ z ( 5 )@ z ( 6 )@ z ( 2 )@ z ( 3 )@ z ( 4 )  
         Δ r   10 ( 3 )= z ( 1 )@ z ( 5 )@ z ( 6 )@ z ( 7 )@ z ( 3 )@ z ( 4 )@ z ( 5 )@ z ( 2 )@ z ( 3 )@ z ( 4 )  
         Δ r   10 ( 4 )= z ( 0 )@ z ( 2 )@ z ( 4 )@ z ( 5 )@ z ( 7 )@ z ( 3 )@ z ( 4 )@ z ( 5 )@ z ( 2 )@ z ( 3 )@ z ( 4 )  
         Δ r   10 ( 5 )= z ( 0 )@ z ( 1 )@ z ( 3 )@ z ( 4 )@ z ( 3 )@ z ( 4 )@ z ( 5 )  
         Δ r   10 ( 6 )= z ( 0 )@ z ( 1 )@ z ( 2 )@ z ( 6 )  
         Δ r   10 ( 7 )= z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 7 )  
       Formula 29  
       Δ r   10 ( 0 )= z ( 2 )@ z ( 3 )@ z ( 4 )  
         Δ r   10 ( 1 )= z ( 3 )@ z ( 4 ) z ( 5 )  
         Δ r   10 ( 2 )= z ( 0 )@ z ( 2 )@ z ( 3 )@ z ( 5 )@ z ( 6 )  
         Δ r   10 ( 3 )= z ( 1 )@ z ( 2 )@ z ( 6 )@ z ( 7 )  
         Δ r   10 ( 4 )= z ( 0 )@ z ( 4 )@ z ( 7 )  
         Δ r   10 ( 5 )= z ( 0 )@ z ( 1 )@ z ( 5 )  
         Δ r   10 ( 6 )= z ( 0 )@ z ( 1 )@ z ( 2 )@ z ( 6 )  
         Δ r   10 ( 7 )= z ( 1 )@ z ( 2 )@ z ( 3 )@z( 7 )  
         [0139]    (11) The Calculation of ΔR 11 (Δr 11 ( 0 ) . . . Δr 11 ( 7 ))  
       Formula 30  
       Δ r   11 ( 0 )=Δ r   10 ( 7 )  
         Δ r   11 ( 1 )=Δ r   10 ( 0 )  
         Δ r   11 ( 2 )=Δ r   10 (i)@Δ r   10 ( 7 )  
         Δ r   11 ( 3 )=Δ r   10 ( 2 )@Δ r   10 ( 7 )  
         Δ r   11 ( 4 )=Δ r   10 ( 3 )@Δ r   10 ( 7 )  
         Δ r   11 ( 5 )=Δ r   10 ( 4 )  
         Δ r   11 ( 6 )=Δ r   10 ( 5 )  
         Δ r   11 ( 7 )=Δ r   10 ( 6 )  
         [0140]    ΔR 10 (Δr 10 ( 0 ) . . . Δr 10 ( 7 )) is shown in Formula 29, resulting in Formula 31.  
       Formula 31  
       Δ r   11 ( 0 )= z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 7 )  
         Δ r   11 ( 1 )= z ( 2 )@ z ( 3 )@ z ( 4 )  
         Δ r   11 ( 2 )= z ( 3 )@ z ( 4 )@ z ( 5 )@ z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 7 )  
         Δ r   11 ( 3 )= z ( 0 )@ z ( 2 )@ z ( 3 )@ z ( 5 )@ z ( 6 )@ z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 7 )  
         Δ r   11 ( 4 )= z ( 1 )@ z ( 2 )@ z ( 6 )@ z ( 7 )@ z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 7 )  
         Δ r   11 ( 5 )= z ( 0 )@ z ( 4 )@ z ( 7 )  
         Δ r   11 ( 6 )= z ( 0 )@ z ( 1 )@ z ( 5 )  
         Δ r   11 ( 7 )= z ( 0 )@ z ( 1 )@ z ( 2 )@ z ( 6 )  
         [0141]    (12) The Calculation of ΔR 12 (Δr 12 ( 0 ) . . . Δr 12 ( 7 ))  
       Formula 32  
       Δ r   12 ( 0 )=Δ r   11 ( 7 )  
         Δ r   12 ( 1 )=Δ r   11 ( 0 )  
         Δ r   12 ( 2 )=Δ r   11 (l)@Δ r   11 ( 7 )  
         Δ r   12 ( 3 )=Δ r   11 ( 2 )@Δ r   11 ( 7 )  
         Δ r   12 ( 4 )=Δ r   11 ( 3 )@Δ r   11 ( 7 )  
         Δ r   12 ( 5 )=Δ r   11 ( 4 )  
         Δ r   12 ( 6 )=Δ r   11 ( 5 )  
         Δ r   12 ( 7 )=Δ r   11 ( 6 )  
         [0142]    A ΔR 11 (Δr 11 ( 0 ) . . . Δr 11 ( 7 )) is shown in Formula 31, resulting in both Formula 33 and Formula 34.  
       Formula 33  
       Δ r   12 ( 0 )= z ( 0 )@ z ( 1 )@ z ( 2 )@ z ( 6 )  
         Δ r   12 ( 1 )= z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 7 )  
         Δ r   12 ( 2 )= z ( 2 )@ z ( 3 )@ z ( 4 )@ z ( 0 )@ z ( 1 )@ z ( 2 )@ z ( 6 )  
         Δ r   12 ( 3 )= z ( 3 )@ z ( 4 )@ z ( 5 )@ z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 7 )@ z ( 0 )@ z ( 1 )@ z ( 2 )@ z ( 6 )  
         Δ r   12 ( 4 )= z ( 0 )@ z ( 2 )@ z ( 3 )@ z ( 5 )@ z ( 6 )  z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 7 )@( 0 )@ z ( 1 )@ z ( 2 )@ z ( 6 )  
         Δ r   12 ( 5 )= z ( 1 )@ z ( 2 )@ z ( 6 )@ z ( 7 )@ z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 7 )  
         Δ r   12 ( 6 )= z ( 0 )@ z ( 4 )@ z ( 7 )  
         Δ r   12 ( 7 )= z ( 0 )@ z ( 1 )@ z ( 5 )  
       Formula 34  
       Δ r   12 ( 0 )= z ( 0 )@ z ( 1 )@ z ( 2 )@ z ( 6 )  
         Δ r   12 ( 1 )= z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 7 )  
         Δ r   12 ( 2 )= z ( 0 )@ z ( 1 )@ z ( 3 )@ z ( 4 )@ z ( 6 )  
         Δ r   12 ( 3 )= z ( 0 ) z ( 4 )@ z ( 5 )@ z ( 6 )@ z ( 7 )  
         Δ r   12 ( 4 )= z ( 2 )@ z ( 5 )@ z ( 7 )  
         Δ r   12 ( 5 )= z ( 3 )@ z ( 6 )  
         Δ r   12 ( 6 )=( 0 )@ z ( 4 )@ z ( 7 )  
         Δ r   12 ( 7 )= z ( 0 )@ z ( 1 )@ z ( 5 )  
         [0143]    (13) The Calculation of ΔR 13 (Δr 13 ( 0 ) . . . Δr 13 ( 7 ))  
       Formula 35  
       Δ r   13 ( 0 )=Δ r   12 ( 7 )  
         Δ r   13 ( 1 )=Δ r   12 ( 0 )  
         Δ r   13 ( 2 )=Δ r   12 ( 1 )@Δ r   12 ( 7 )  
         Δ r   13 ( 3 )=Δ r   12 ( 2 )@Δ r   12 ( 7 )  
         Δ r   13 ( 4 )=Δ r   12 ( 3 )@Δ r   12 ( 7 )  
         Δ r   13 ( 5 )=Δ r   12 ( 4 )  
         Δ r   13 ( 6 )=Δ r   12 ( 5 )  
         Δ r   13 ( 7 )=Δ r   12 ( 6 )  
         [0144]    ΔR 12 (Δr 12 ( 0 ) . . . Δr 12 ( 7 )) is shown in Formula 34, resulting in Formula 36.  
       Formula 36  
       Δ r   13 ( 0 )= z ( 0 )@ z ( 1 )@ z ( 5 )  
         Δ r   13 ( 1 )= z ( 0 )@ z ( 1 )@ z ( 2 )@ z ( 6 )  
         Δ r   13 ( 2 )= z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 7 )@ z ( 0 )@ z ( 1 )@ z ( 5 )  
         Δ r   13 ( 3 )= z ( 0 )@ z ( 1 )@ z ( 3 )@ z ( 4 )@ z ( 6 )@ z ( 0 )@ z ( 1 )@ z ( 5 )  
         Δ r   13 ( 4 )= z ( 0 )@ z ( 4 )@ z ( 5 )@ z ( 6 )@ z ( 7 )@ z ( 0 )@ z ( 1 )@ z ( 5 )  
         Δ r   13 ( 5 )= z ( 2 )@ z ( 5 )@ z ( 7 )  
         Δ r   13 ( 6 )= z ( 3 )@ z ( 6 )  
         Δ r   13 ( 7 )= z ( 0 )@ z ( 4 )@ z ( 7 )  
         [0145]    (14) The Calculation of ΔR 14 (Δr 14 ( 0 ) . . . Δr 14 ( 7 ))  
       Formula 37  
       Δ r   14 ( 0 )=Δ r   13 ( 7 )  
         Δ r   14 ( 1 )=Δ r   13 ( 0 )  
         Δ r   14 ( 2 )=Δ r   13 ( 1 )@Δ r   13 ( 7 )  
         Δ r   14 ( 3 )=Δ r   13 ( 2 )@Δ r   13 ( 7 )  
         Δ r   14 ( 4 )=Δ r   13 ( 3 )@Δ r   13 ( 7 )  
         Δ r   14 ( 5 )=Δ r   13 ( 4 )  
         Δ r   14 ( 6 )=Δ r   13 ( 5 )  
         Δ r   14 ( 7 )=Δ r   13 ( 6 )  
         [0146]    ΔR 13 (Δr 13 ( 0 ) . . . Δr 13 ( 7 )) is shown in Formula 36, resulting in both Formula 38 and Formula 39.  
       Formula 38  
       Δ r   14 ( 0 )= z ( 0 )@ z ( 4 )@ z ( 7 )  
         Δ r   14 ( 1 )= z ( 0 )@ z ( 1 )@ z ( 5 )  
         Δ r   14 ( 2 )= z ( 0 )@ z ( 1 )@ z ( 2 )@ z ( 6 )@ z ( 0 )@ z ( 4 )@ z ( 7 )  
         Δ r   14 ( 3 )= z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 7 )@ z ( 0 )@ z ( 1 )@ z ( 5 )@ z ( 0 )@ z ( 4 )@ z ( 7 )  
         Δ r   14 ( 4 )= z ( 0 )@ z ( 1 )@ z ( 3 )@ z ( 4 )@ z ( 6 )@ z ( 0 )@ z ( 1 )@ z ( 5 )@ z ( 0 )@ z ( 4 )@ z ( 7 )  
         Δ r   14 ( 5 )= z ( 0 )@ z ( 4 )@ z ( 5 )@ z ( 6 )@ z ( 7 )@ z ( 0 )@ z ( 1 )@ z ( 5 )  
         Δ r   14 ( 6 )= z ( 2 )@ z ( 5 )@ z ( 7 )  
         Δ r   14 ( 7 )= z ( 3 )@ z ( 6 )  
       Formula 39  
       Δ r   14 ( 0 )= z ( 0 )@ z ( 4 )@ z ( 7 )  
         Δ r   14 ( 1 )= z ( 0 )@ z ( 1 )@ z ( 5 )  
         Δ r   14 ( 2 )= z ( 1 )@ z ( 2 )@ z ( 4 )@ z ( 6 )@ z ( 7 )  
         Δ r   14 ( 3 )= z ( 2 )@ z ( 3 )@ z ( 4 )@ z ( 5 )  
         Δ r   14 ( 4 )= z ( 0 )@ z ( 3 )@ z ( 5 )@ z ( 6 )@ z ( 7 )  
         Δ r   14 ( 5 )= z ( 1 )@ z ( 4 )@ z ( 6 )@ z ( 7 )  
         Δ r   14 ( 6 )= z ( 2 )@ z ( 5 )@ z ( 7 )  
         Δ r   14 ( 7 )= z ( 3 )@ z ( 6 )  
         [0147]    (15) The Calculation of ΔR 15 (Δr 15 ( 0 ) . . . Δr 15 ( 7 ))  
       Formula 40  
       Δ r   15 ( 0 )=Δ r   14 ( 7 )  
         Δ r   15 ( 1 )=Δ r   14 ( 0 )  
         Δ r   15 ( 2 )=Δ r   14 ( 1 )@Δ r   14 ( 7 )  
         Δ r   15 ( 3 )=Δ r   14 ( 2 )@Δ r   14 ( 7 )  
         Δ r   15 ( 4 )=Δ r   14 ( 3 )@Δ r   14 ( 7 )  
         Δ r   15 ( 5 )=Δ r   14 ( 4 )  
         Δ r   15 ( 6 )=Δ r   14 ( 5 )  
         Δ r   15 ( 7 )=Δ r   14 ( 6 )  
         [0148]    ΔR 14 (Δr 14 ( 0 ) . . . Δr 14 ( 7 )) is shown in Formula 39, resulting in Formula 41.  
       Formula 41  
       Δ 15 ( 0 )= z ( 3 )@ z ( 6 )  
         Δ 15 ( 1 )= z ( 0 )@ z ( 4 )@ z ( 7 )  
         Δ 15 ( 2 )= z ( 0 )@ z ( 1 )@ z ( 5 )@ z ( 3 )@ z ( 6 )  
         Δ 15 ( 3 )= z ( 1 )@ z ( 2 )@ z ( 4 )@ z ( 6 )@ z ( 7 )@ z ( 3 )@ z ( 6 )  
         Δ 15 ( 4 )= z ( 2 )@ z ( 3 )@ z ( 4 )@ z ( 5 )@ z ( 3 )@ z ( 6 )  
         Δ 15 ( 5 )= z ( 0 )@ z ( 3 )@ z ( 5 )@ z ( 6 )@ z ( 7 )  
         Δ 15 ( 6 )= z ( 1 )@ z ( 4 )@ z ( 6 )@ z ( 7 )  
         Δ 15 ( 7 )= z ( 2 )@ z ( 5 )@ z ( 7 )  
         [0149]    (16) The Calculation of ΔR 16 (Δr 16 ( 0 ) . . . Δr 16 ( 7 ))  
       Formula 42  
       Δ r   16 ( 0 )=Δ r   15  ( 7 )  
         Δ r   16 ( 1 )=Δ r   15 ( 0 )  
         Δ r   16 ( 2 )=Δ r   15 ( 1 )@Δ 15 ( 7 )  
         Δ r   16 ( 3 )=Δ r   15 ( 2 )@Δ 15 ( 7 )  
         Δ r   16 ( 4 )=Δ r   15 ( 3 )@Δ 15 ( 7 )  
         Δ r   16 ( 5 )=Δ r   15 ( 4 )  
         Δ r   16 ( 6 )=Δ r   15 ( 5 )  
         Δ r   16 ( 7 )=Δ r   15 ( 6 )  
         [0150]    ΔR 15 (Δr 15 ( 0 ) . . . Δr 15 ( 7 )) is shown in Formula 41, resulting in both Formula 43 and Formula 44.  
       Formula 43  
       Δ r   16 ( 0 )= z ( 2 )@ z ( 5 )@ z ( 7 )  
         Δ r   16 ( 1 )= z ( 3 )@ z ( 6 )  
         Δ r   16 ( 2 )= z ( 0 )@ z ( 4 )@ z ( 7 )@ z ( 2 )@ z ( 5 )@ z ( 7 )  
         Δ r   16 ( 3 )= z ( 0 )@ z ( 1 )@ z ( 5 )@ z ( 3 )@ z ( 6 )@ z ( 2 )@ z ( 5 )@ z ( 7 )  
         Δ r   16 ( 4 )= z ( 1 )@ z ( 2 )@ z ( 4 )@ z ( 6 )@ z ( 7 )@ z ( 3 )@ z ( 6 )@ z ( 2 )@ z ( 5 )@ z ( 7 )  
         Δ r   16 ( 5 )= z ( 2 )@ z ( 3 )@ z ( 4 )@ z ( 5 )@ z ( 3 )@ z ( 6 )  
         Δ r   16 ( 6 )= z ( 0 )@ z ( 3 )@ z ( 5 )@ z ( 6 )@ z ( 7 )  
         Δ r   16 ( 7 )= z ( 1 )@ z ( 4 )@ z ( 6 )@ z ( 7 )  
       Formula 44  
       Δ r   16 ( 0 )= z ( 2 )@ z ( 5 )@ z ( 7 )  
         Δ r   16 ( 1 )= z ( 3 )@ z ( 6 )  
         Δ r   16 ( 2 )= z ( 0 )@ z ( 2 )@ z ( 4 )@ z ( 5 )  
         Δ r   16 ( 3 )= z ( 0 )@ z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 6 )@ z ( 7 )  
         Δ r   16 ( 4 )= z ( 1 )@ z ( 3 )@ z ( 4 )@ z ( 5 )  
         Δ r   16 ( 5 )= z ( 2 )@ z ( 4 )@ z ( 5 )@ z ( 6 )  
         Δ r   16 ( 6 )= z ( 0 )@ z ( 3 )@ z ( 5 )@ z ( 6 )@ z ( 7 )  
         Δ r   16 ( 7 )= z ( 1 )@ z ( 4 )@ z ( 6 )@ z ( 7 )  
         [0151]    By means of the above calculations, ΔR 16 (Δr 16 ( 0 ) . . . Δr 16 ( 7 )) is found by Formula 44, and the formula ΔR 16 (r 16 ( 0 ) . . . r 16 ( 7 ))=R′ 16 (r′ 16 ( 0 ) . . . r′ 16 ( 7 ))@ΔR 16 (Δr 16 ( 0 ) . . . Δr 16 ( 7 )) can be generated.  
         [0152]    Here, R′ 16 (r′ 16 ( 0 ) . . . r′ 16 ( 7 )) is shown in Formula 6 and is the block CRC code for sending a 16-byte data block when initial values (z( 0 ) . . . z′( 7 )) are made “00”; and ΔR 16 (Δr 16 ( 0 ) . . . Δr 16 ( 7 )) is shown in Formula 44 and is the amount of displacement of Z(z( 0 ) . . . z( 7 )) when sending a 16-byte data block when initial values are made Z(z( 0 ) . . . z( 7 )).  
         [0153]    [0153]FIG. 10 illustrates this point.  
         [0154]    If the formula R 16 (r 16 ( 0 ) . . . r 16 ( 7 ))=R′ 16 (r′ 16 ( 0 ) . . . r′ 16 ( 7 ))@ΔR 16 (Δr 16 ( 0 ) . . . Δr( 7 )) is defined as a “BCRC operation,” the process shown in FIG. 11 can be realized.  
         [0155]    At this time, the block CRC operation formula for finding R 16 (r 16 ( 0 ) . . . r 16 ( 7 )) is Formula 45.  
       Formula 45  
       Δ r   16 ( 0 )= r ′ 16 ( 0 )@ z ( 2 )@ z ( 5 )@ z ( 7 )  
         Δ r   16 ( 1 )= r ′ 16 ( 1 )@ z ( 3 )@ z ( 6 )  
         Δ r   16 ( 2 )= r ′ 16 ( 2 )@ z ( 0 )@ z ( 2 )@ z ( 4 )@ z ( 7 )  
         Δ r   16 ( 3 )= r ′ 16 ( 3 )@ z ( 0 )@ z ( 1 )@ z ( 2 )@ z ( 3 )@ z ( 4 )@ z ( 5 )@ z ( 7 )  
         Δ r   16 ( 4 )= r ′ 16 ( 4 )@ z ( 1 )@ z ( 3 )@ z ( 4 )@ z ( 7 )  
         Δ r   16 ( 5 )= r ′ 16 ( 5 )@ z ( 2 )@ z ( 4 )@ z ( 5 )@ z ( 6 )  
         Δ r   16 ( 6 )= r ′ 16 ( 6 )@ z ( 0 )@ z ( 3 )@ z ( 5 )@ z ( 6 )@ z ( 7 )  
         Δ r   16 ( 7 )= r ′ 16 ( 7 )@ z ( 1 )@ z ( 4 )@ z ( 6 )@ z ( 7 )  
         [0156]    Accordingly, the circuit of FIG. 11 is connected in data block units to constitute a circuit for finding the final CRC operation result, producing a circuit such as shown in FIG. 12.  
         [0157]    Here, CRC operation result R 512 (r 512 ( 0 ) . . . r 512 ( 7 )) is the CRC operation result when data from D 0 (d 0 ( 0 ) . . . d 0 ( 7 )) to D 512 (d 512 ( 0 ) . . . d 512 ( 7 )) are transferred, by the way applying the CRC codes contained in sector data to this as data D 513 (d 513 ( 0 ) . . . d 513 ( 7 )) indicates that normal transfer has been achieved if R 513 (r 513 ( 0 ) . . . r 513 ( 7 )) becoms “00.” 
         [0158]    In addition, in a “BCRC operation” for generating R 513 (r 513 ( 0 ) . . . r 513 ( 7 )) from the final R 512 (r 512 ( 0 ) . . . r 512 ( 7 )) and R′ 513 (r′ 513 ( 0 ) . . . r′ 513 ( 7 )), the data that are transferred are the single byte D 513 (d 513 ( 0 ) . . . r 513 ( 7 )), and since this differs from the “BCRC operation” in Formula 22 when transferring 16 bytes, an operation when transferring one byte is necessary. Since this results in the amount of displacement already defined by Formula 9, Formula 46 is used.  
       Formula 46  
       Δ r   513 ( 0 )= r ′ 513 ( 0 )@ r   512 ( 7 )  
         Δ r   513 ( 1 )= r ′ 513 ( 1 )@ r   512 ( 0 )  
         Δ r   513 ( 2 )= r ′ 513 ( 2 )@ r   512 ( 1 )@ r   512 ( 7 )  
         Δ r   513 ( 3 )= r ′ 513 ( 3 )@ r   512 ( 2 )@ r   512 ( 7 )  
         Δ r   513 ( 4 )= r ′ 513 ( 4 )@ r   512 ( 3 )@ r   512 ( 7 )  
         Δ r   513 ( 5 )= r ′ 513 ( 5 )@ r   512 ( 4 )  
         Δ r   513 ( 6 )= r ′ 513 ( 6 )@ r   512 ( 5 )  
         Δ r   513 ( 7 )= r ′ 513 ( 7 )@ r   512 ( 6 )  
         [0159]    In the above-described embodiment, although an example was described that is used in, for example, a disk array system, in which sector data and CRC code from host device  1  are combined to make 520 bytes, and initial values Z(z( 0 ) . . . z( 7 )) of the CRC codes are set to “00” when memory device  5  accesses one data block (16-byte unit) and generates block CRC codes, these initial values can be any value in the present invention, and no limit is placed on the scope of application of the present invention.  
         [0160]    As the first effect of the present invention, a device that is a data transfer source is able to detect how data were transferred to the ultimate memory device, whereby alteration of data midway on the path of data transfer can be reliably detected and the integrity of the data can be increased.  
         [0161]    As the second effect of the present invention, the checking logic of CRC codes exists on the host adapter side, which is the data transfer source, whereby increase in the hardware on the memory adapter side can be avoided and circuit complexity can be prevented even in a configuration that includes a plurality of host devices.  
         [0162]    As a third effect of the present invention, the invention is not a data transfer system in which CRC codes are always added to data block units, and the invention can therefore be employed without causing any reduction of the transmission rate of the bus; and further, the circuits of the invention other than the circuit portion in which block CRC codes are returned are identical to the circuits of a conventional data transfer system, and the invention can therefore be easily applied to raise the integrity of data without necessitating a drastic modification of circuits.  
         [0163]    While preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims.