Abstract:
A phase detecting apparatus comprises a first PLL and a second PLL having a response time shorter than the response time of the first PLL. An AC voltage signal produced by the first PLL which is in phase with the detected AC voltage except until the expiration of the response time of the first PLL after an abrupt change in the phase of the detected AC voltage is normally applied to the second PLL. Until expiration of the response time of the first PLL after rising of the detected AC voltage to a certain level, the detected AC voltage is applied, in place of the AC voltage signal produced by the first PLL, to the second PLL. The second PLL provides a digital signal indicative of the phase of the detected AC voltage.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a phase detecting apparatus particularly suitable for use in phase control or firing angle control of a power converter used for DC power transmission or frequency conversion. 
     Prior art phase detecting apparatus have a drawback in that they do not provide a satisfactory phase detection upon occurrence of a fault, as will be later described in detail. 
     SUMMARY OF THE INVENTION 
     An object of the invention is to provide a phase detecting apparatus which is capable of satisfactory detection of the phase even when the voltages are unbalanced because, for example, of a grounding fault, of the AC line, and is quick in resuming the phase detection operation upon restoration of the AC voltage after disappearance of the AC voltage. 
     According to the invention there is provided a phase detecting apparatus for detecting a phase of an AC voltage, comprising: 
     a first circuit comprising a phase-locked loop, receiving said AC voltage under detection, and producing an AC voltage signal which is in phase with said AC voltage under detection except until expiration of the response time of said phase-locked loop after any abrupt change in the phase of said AC voltage under detection, 
     a second circuit comprising a phase-locked loop having a response time which is shorter than the response time of the phase-locked loop of said first circuit, and 
     selecting means normally applying said AC voltage signal produced by said first circuit to said second circuit, and applying said AC voltage under detection or an AC voltage signal obtained by phase-number conversion from said AC voltage under detection to said second circuit until a predetermined time has expired after rising of said AC voltage under detection to a predetermined level, 
     said second circuit producing a digital signal indicative of the phase of said AC voltage under detection. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawings 
     FIG. 1 is a circuit diagram showing a three-phase thyristor bridge used in a power convertor; 
     FIG. 2 is a block diagram showing an example of a conventional phase detecting apparatus; 
     FIG. 3 is a block diagram showing an embodiment of a phase detecting apparatus according to the invention; and 
     FIG. 4 is a block diagram showing another embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PRIOR ART 
     FIG. 1 shows a three-phase thyristor bridge which receives three-phase AC voltages R, S, T. The bridge includes thyristors U, V, W, X, Y, Z, each forming an arm of the bridge. The firing phase angle of each thyristor is so regulated as to control the DC voltage across the DC terminals P, N. The thyristor bridge shown is used for a power converter in DC power transmission or in frequency conversion. 
     Nowadays, digital computers are used for the firing angle control, and it is required that the phase angles of the three-phase AC voltages be precisely detected or measured and digital signals indicative of the phase angles be provided. To meet such a requirement, phase detecting apparatus with a phase-locked loop circuit (hereinafter referred to as PLL) are often employed. 
     FIG. 2 shows an example of a prior art phase detecting apparatus disclosed in Japanese Patent Application Laid-open (Kokai) No. 34851/1980, which comprises a V/F (voltage-to-frequency) converter 1 consisting of a voltage-controlled oscillator 1 whose oscillating frequency varies depending on the input voltage, a counter 2 counting the output pulses from the oscillator 1 to produce a digital count signal θ indicative of the phase angle of AC signals, such as three-phase AC voltages R, S, T being detected, a phase comparator 3 receiving, on one hand, the digital count signal θ, and on the other hand, the three-phase AC voltages R, S, T to produce an analog phase difference signal Δθ, and a low-pass filter 4 inserted between the phase comparator 3 and the V/F converter 1, for removing the harmonic components in the output of the phase comparator 3. 
     The phase comparator 3 comprises a three-phase to two-phase converter 31 converting the three-phase AC voltages R, S, T into two-phase AC voltage signals V 1d , V 1q  in phase with the three-phase signals R, S, T and having substantially no response delay in the conversion, an ROM (read-only-memory) 32 receiving, as its address information, the digital count signal θ from the counter 2 and producing the contents at the address as outputs having values indicative of the sine and cosine of the inputted signal θ, successions of which form two-phase AC signals, D/A (digital-to-analog) converters 33a, 33b converting the outputs of the ROM 32 into analog signals V Fd , V Fq  which correspond to the two-phase AC signals V 1d , V 1q , and an analog-type arithmetic operation circuit 34 determining the phase difference Δθ between the two sets of two-phase AC signals V 1d , V 1q  and V Fd , V Fq . 
     In FIG. 2, the outputs of the three-phase to two-phase converter 31 may be expressed as follows: ##EQU1## where V 1  represents a predetermined amplitude, 
     θ 1  represents a phase of the set of the three-phase signals R, S, T. 
     The outputs of the D/A converters 33a, 33b are expressed as follows: ##EQU2## where θ 2  represents the detected phase, whose significance is identical to that of the signal θ. It is noted that the these signals V Fd , V Fq  have a unit amplitude. 
     The arithmetic operation circuit 34 performs the following arithmetic operation to determine the phase difference Δθ(=θ 1  -θ 2 ) between the sets of signals V 1d , V 1q  and V Fd , V Fq . ##EQU3## 
     The signal indicative of the phase difference Δθ is passed through the low-pass filter 4 and is applied to the V/F converter 1. Thus a feed-back loop is formed by which the phase difference Δθ is made smaller or zero, and a digital signal θ in synchronism with the detected three-phase AC voltages R, S, T are outputted by the counter 2. The digital signal θ thus obtained is used, e.g., for firing angle control of the three-phase thyristor bridge. The full-scale value of the counter 2 corresponds to 360°, and when the full-scale value is reached the counter 2 is automatically reset to zero and starts counting up again. 
     The response time of the phase detection is dependent mainly on the time constant of the low-pass filter 4, and a low-pass filter with an appropriate time constant is chosen for the particular application of the power converter. 
     The above-described phase detecting apparatus has a high performance and is very useful in digital control of firing angle control. But when it is used in a power converter for DC power transmission or the like it is not satisfactory for the following reason. 
     Namely, when a grounding fault and hence a voltage drop occur in one or two of the three-phase lines R, S, T, and if the phase detection response is designed to be quick, the detected value θ would be quite different from that obtained when the three-phase voltages are balanced. 
     The above-described problem could be overcome if the phase detection response is designed to be slower by making the low-pass filter 4 to have a larger time constant. But the slow phase detection response retards start of operation of the power converter after automatic reclosing of the line subsequent to (several hundreds msec. after) circuit breaking which is effected upon detection of a prolonged grounding fault of the line. 
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     FIG. 3 shows an embodiment of the invention. As illustrated, the phase detecting apparatus of this embodiment comprises a first phase detecting circuit 100, a second phase detecting circuit 200 and a signal selecting circuit 50. The first phase detecting circuit 100 receives the three-phase AC voltages R, S, T whose phase is to be detected, and produces analog three-phase AC voltage signals e R , e S , e T . The second phase detecting circuit 200 receives the three-phase AC voltages R, S, T or the three-phase AC voltage signals e R , e S , e T  and produces a digital phase detection signal θ 200 . The signal selecting circuit 50 selects the three-phase AC voltages R, S, T or the three-phase AC voltages e R , e S , e T  and makes the selected voltages to be applied to the second phase detecting circuit 200. 
     The first phase detecting circuit 100 comprises a V/F converter 101, a counter 102, a phase comparator 103, and a low-pass filter 104, which are similar to the V/F converter 1, the counter 2, the phase comparator 3, the low-pass filter 4 shown in FIG. 2, and the phase comparator 103 comprises a three-phase to two-phase converter 131, an ROM 132, D/A converters 133, 133, and an arithmetic operation unit 134 similar to the three-phase to two-phase converter 31, the ROM 32, the D/A converters 33, 33, and the arithmetic operation unit 34 shown in FIG. 2. 
     The first phase detecting circuit 100 further comprises ROM&#39;s (read only memories) 111a-111c which receive the outputs θ 100  of the counter 102 as their address information and produces the respective contents at the addresses, the successions of which form three-phase voltages, and D/A (digital-to-analog) converters 112a-112c converting the outputs of the ROMs 111a-111c into analog three-phase voltage signals e R , e S , e T . The three-phase voltage signals e R , e S , e T  are kept in phase with the three-phase voltages R, S, T, by the function of the phase-locked loop, except during a time period until the response time of the phase locked loop expires after an abrupt change occurs in the phase of the voltages R, S, T. 
     The second phase detecting circuit 200 comprises a V/F converter 201, a counter 202, a phase comparator 203, and a low-pass filter 204 which are similar to the V/F converter 1, the counter 2, the phase comparator 3 and the low-pass filter 4 shown in FIG. 2. Moreover, the phase comparator 203 comprises a three-phase to two-phase converter 231, an ROM 232, D/A converters 233, 233 and an arithmetic operation unit 234, which are similar to the three-phase to two-phase converter 31, the ROM 32, the D/A converters 33, 33 and the arithmetic operation unit 34 shown in FIG. 2. 
     Each of low-pass filters 104 and 204 is in the form of proportional plus integral type control amplifier, whose transfer function may for example be: ##EQU4## where S represents a Laplace transform variable, and T represents the time constant. The low-pass filter 104 has a relatively large time constant so that the phase detection response time of the first phase detecting circuit 100 may be a few hundreds msec to 1 sec, while the low-pass filter 204 has a relatively small time constant so that the phase detection response time of the second phase detecting circuit 200 may be 20-30 msec. 
     The signal selecting circuit 50 comprises a voltage detector 51 judging whether or not all of the three-phase voltages R, S, T are greater than a predetermined magnitude, in other words, whether or not none of the three phase voltages R, S, T is at or near zero because for example of a grounding fault, and a selecting switch 52 selecting the input to the second phase detecting circuit 200. 
     When the three-phase AC voltages R, S, T supplied to the three-phase thyristor bridge shown in FIG. 1 are greater than the predetermined value, i.e., they are established, the voltage detector 51 makes the selecting switch 52 to select the voltages e R , e S , e T  from the first phase detecting circuit 100. The second phase detecting circuit 200 operates substantially in the same manner as was described with reference to FIG. 2, and produces a digital phase detecting signal θ 200 . 
     Assume now the voltage disappears from one or two of the phase voltages R, S, T because, for example, of a grounding fault. In spite of the fault, the first phase detecting circuit 100 continues to produce the three-phase voltages e R , e S , e T  which are in phase with the balanced voltages R, S, T which existed before the occurrence of the fault and which would have continued to exist if the fault had not occurred. 
     The second phase detecting circuit 200, receiving the outputs e R , e S , e T  of the first phase detecting circuit 100, therefore keeps producing a digital signal θ 200  which is also in phase with the voltages R, S, T which existed before the occurrence of the fault. 
     This state is continued until the expiration of the phase detection response time of the first phase detecting circuit 100, which is a few hundreds msec-1 sec, or until the voltages rise again, whichever is the earlier. The voltages rise usually within 200 msec, so that production of an appropriate phase detecting digital signal θ 200  is not interrupted by the fault, or the instantaneous disappearance of the voltage. 
     Upon transition of the AC line from the &#34;broken&#34; state to &#34;reclosed&#34; state, i.e., when the voltages R, S, T rise from the zero voltage to the rated voltage, the voltage detector 51 detects such transition, and makes the selecting switch 52 to select the three-phase voltages R, S, T. 
     The output θ 200  of the second phase detecting circuit 200, having a quicker detection response, is promptly made to be in phase with the newly established voltages R, S, T. 
     Upon expiration of a predetermined time period after the rise of the voltages R, S, T, the voltage detector 51 makes the selecting switch 52 to select the outputs e R , e S , e T  of the first phase detecting circuit 100. The above-mentioned &#34;predetermined time period&#34; is set to be a little longer than the detection response time of the first phase detecting circuit 100, so that the switch 52 is made to select the outputs e R , e S , e T  of the first phase detecting circuit 100 after they are made in phase with the voltages R, S, T. 
     The digital signal θ 200  thus obtained may be applied to a firing angle control circuit 60 which determines, responsive to the signal θ 200 , the firing angle of the thyristors U, V, W, X, Y, Z of the thyristor bridge shown in FIG. 1 and produces firing pulses FU, FV, FW, FX, FY, FZ for the respective thyristors U, V, W, X, Y, Z. 
     FIG. 4 shows another embodiment of the invention. The same reference numerals as in FIG. 3 designate identical or similar components. As seen, the arrangement shown in FIG. 4 is similar to that shown in FIG. 3 but differs from that in FIG. 3 in that the phase comparator 203A does not have a three-phase to two-phase converter 231 of FIG. 3, and the selecting switch 52A is of two-pole type receiving the output of the three-phase to two-phase converter 131 and the outputs of the D/A converters 133, 133 and the arithmetic operation unit 234 receives either of the two-phase AC signals through the selecting switch 52A. Moreover, ROM&#39;s 111a-111c and D/A converters 112a-112c of FIG. 3 have been eliminated. 
     The two-phase voltage signals V Fd  &#39;, V Fq  &#39; from the D/A converters 233, 233 are kept in phase with the voltages R, S, T except during the time period until the expiration of the response time of the phase-locked loop of the first phase detecting circuit 100 after an abrupt change in the phase of the voltages R, S, T. These two-phase voltage signals V Fd  &#39;, V Fq  &#39; can therefore be used in place of the three-phase voltage signals e R , e S , e T  in FIG. 3, and the phase-locked loop of the second phase detecting circuit 200 may be made to &#34;follow&#34; the two-phase voltages V Fd  &#39;, V Fq  &#39;. 
     The embodiment of FIG. 4 is advantageous over the embodiment of FIG. 3 in that the arrangement is simplified because of elimination of the ROM&#39;s 111a-111c, D/A converters 112a-112c, and three-phase to two-phase converter 231. 
     Although the voltages R, S, T have been described as being directly applied to the first and the second phase detecting circuits, they may be applied after level conversion i.e., after they are converted to a smaller level suitable for processing. The reference in the claims to application to and reception by the phase detecting circuits of the AC voltage under detection should therefore be construed to cover application and reception of such converted voltages. 
     The invention has been described as being applied to phase detection of three-phase AC voltages supplied to a power converter for producing a DC voltage. But the invention is applicable to phase detection of two-phase voltages. This can be done, for instance, simply by eliminating the three-phase to two-phase converter 131 from the arrangement of FIG. 4. The invention is also applicable to phase detection of voltages of any other number of phases. This can be done, for instance, by use of an appropriate phase-number converters in place of the three-phase to two-phase converters. Moreover, use of the phase comparators including the above-described arithmetic operation unit is not essential but any other type of phase comparator can be used. 
     As has been described, the invention makes it possible to provide an appropriate phase detection signal even when the voltages are unbalanced because of a grounding fault or the like, and also to immediately resume phase detection operation after restoration of the AC voltage subsequent to its disappearance. For this reason, stable firing angle control of the power converter can be continued regardless of the operation condition of the AC line.