Abstract:
A preamplifier for a resistive transducer, configured to generate an amplified output indicative of potential difference across the transducer (while the transducer is biased and in the presence of a magnetic field) and to generate a resistance signal indicative of the transducer&#39;s resistance, and a method for measuring the resistance of a resistive transducer during operation of the transducer in the presence of a changing magnetic field. The preamplifier preferably includes circuitry for generating a current signal indicative of the instantaneous current through the transducer and analog divider circuitry for generating the resistance signal from a signal indicative of the potential difference across the transducer and the current signal. When the resistance signal is an analog signal, the preamplifier can include circuitry for processing the analog resistance signal to generate a word of binary data indicative of a value proportional to the transducer resistance. Alternatively, when the resistance signal is an analog signal the preamplifier can include a digital-to-analog (D-to-A) converter, and a comparator which receives an analog resistance signal and the output of the D-to-A converter. In operation of the latter class of embodiments, the output of the D-to-A converter is swept until the comparator is tripped, at which time the setting of the D-to-A converter is proportional to the transducer resistance.

Description:
FIELD OF THE INVENTION 
     The invention pertains to preamplifiers for resistive transducers (such as a magneto-resistive transducers), and to methods for measuring the resistance of a resistive transducer. In preferred embodiments, the inventive preamplifier includes circuitry for measuring resistance of a resistive transducer (as well as potential difference across the transducer) during normal transducer operation. 
     BACKGROUND OF THE INVENTION 
     When positioned in an external magnetic field, the resistance of a magneto-resistive transducer varies in response to variations of the magnetic field over time. Magneto-resistive transducers have been used as read heads in magnetic disk drives and are being more commonly used for this purpose. 
     A typical magneto-resistive transducer includes a strip of nickel-iron metallization on a silicon substrate. A preamplifier coupled to the strip applies a bias voltage across the strip (to cause current flow through the strip), and while doing so generates an amplified signal indicative of the potential difference across the strip. The amplified signal then undergoes further processing. 
     A typical preamplifier of this type is shown in FIG. 1A, and a portion of the FIG. 1A circuit is shown in FIG.  1 . In FIG. 1, the magneto-resistive transducer is represented as a resistor having resistance R MR . The drain of PMOS transistor M 1  is coupled to one end of the transducer, the source of M 1  is coupled to the top rail (at potential V CC ), the drain of NMOS transistor M 2  is coupled to the other end of the transducer, and the source of M 2  is coupled to the bottom rail (at potential V EE ). The transducer is biased by asserting bias potentials V BP  and V BN  to the gates of transistors M 1  and M 2 , thereby applying a bias potential across the transducer and causing current I MR  to flow through the transducer (and through transistors M 1  and M 2 ). The magnitudes of the bias potentials V BP  and V BN  are chosen as a function of the transducer resistance (e.g., the transducer resistance in the presence of no magnetic field) and other factors to optimize system performance. 
     The potential difference (V MR ) across the transducer is amplified to generate differential output OUT P , OUT N  (indicative of the potential difference across the transducer), by an amplifier comprising NPN bipolar transistors Q P1  and Q P2  (whose bases are coupled to opposite ends of the transducer), NPN bipolar transistors Q P3  and Q P4  (whose bases are coupled to receive bias voltages VB 3  and VB 4 ), current source  3  coupled to the common emitters of transistors Q P1  and Q P3 , and current source  4  coupled to the common emitters of transistors Q P2  and Q P4 . The output signal OUT P , OUT N  is produced at the collectors of transistors Q P1  and Q P2 . 
     With reference to FIG. 1A, we next describe typical circuitry for producing the above-mentioned bias potentials V BP , V BN , V B3 , and V B4  which are employed in FIG.  1 . 
     In FIG. 1A, circuit  40  (which includes above-discussed transistor M 1 ) is a current source which is biased, by potential V SETP  asserted at the output of digital-to-analog converter  61 , to function as the source of the current I MR  which flows through transducer R MR . 
     Op amp  62 , NPN bipolar transistor Q 62 , and resistor R REF  (connected as shown in FIG. 1A) provide reference current I REF  to digital-to-analog converter (“DAC”)  61 , when reference potential V REF  is asserted at the noninverting input of op amp  62 . To control the output of DAC  61 , control logic  60  asserts control bits to DAC  61 . In response to the control bits and reference current I REF  the output of DAC  61  is at the potential V SETP  (and circuit  40  draws current I DAC-RMR  therefrom). In response to potential V SETP , circuit  40  maintains the gate of transistor M 1  at a desired bias potential V BP . 
     More specifically, circuit  40  includes PMOS transistors M 0  and M 1  and capacitor C P  (connected as shown in FIG.  1 A), transconductance amplifier  50  (whose inverting input is coupled to the output of DAC  61  and whose noninverting input is coupled to the drain of transistor M 0 ), resistor R SETP  (coupled between ground and the inverting input of amplifier  50 ), and resistor R SNSP  (coupled between the drain of M 0  and ground). The gates of transistors M 1  and M 0  are coupled to the output of amplifier  50 , so that the output potential of amplifier  50  is the bias potential V BP  for the gate of transistor M 1 . Since transistor M 0  has characteristics which match those of transistor M 1 , the current at the drain of M 0  is proportional (with a known proportionality factor) to the current at the drain of M 1 , and the noninverting terminal of amplifier  50  thus receives feedback (from the drain of transistor M 0 ) indicative of the drain current of transistor M 1 . In response to this feedback, amplifier  50  maintains the bias potential V BP  at a level, determined by the reference potential V SETP , which will maintain the current through the transducer at a desired nominal level. 
     Circuit  42  includes NMOS transistor M 2 , capacitor C N , and resistors R CM , R DIF1 , and R DIF2  connected as shown in FIG. 1A (with R CM  connected between ground and Node  1 , R DIF1  connected between one end of the transducer and Node  1 , and R DIF2  connected between the other end of the transducer and Node  1 ), and transconductance amplifier  52  whose inverting input is coupled to receive bias potential V CM-SETN . The noninverting input of amplifier  52  is coupled to Node  1 , and thus is maintained at a potential (above ground) equal to the common mode voltage of the transducer, (V RMRP +V RMRN )/2, where V RMRP −V RMRN  is the voltage across the transducer (since R DIF1 =R DIF2  R CM /2, with R DIF1  typically equal to 20 KOhms). Thus, amplifier  52  (whose output is coupled to the gate of transistor M 2 ) forces the gate of M 2  to remain at a bias potential V BN , determined by the reference potential V CM-SETN , which will maintain the common mode voltage of the transducer at a desired level (typically at or near ground potential). 
     Still with reference to FIG. 1A, the abovediscussed differential output OUT P , OUT N  of the FIG. 1 circuit (which is indicative of the potential difference across the transducer and is produced at the collectors of transistors Q P1  and Q P2 ) undergoes amplification in second stage amplifier  51 . The resulting amplified differential output (V o2N , V o2P ) is asserted to a third stage (not shown). 
     The amplified differential output (V o2N , V o2P ) is also asserted to the inputs of transconductance amplifier  54 . In response, transconductance amplifier  54  asserts a first output having potential V B3  to the base of transistor Q P3  and a second output having potential V B4  to the base of transistor Q P4 . Current source  56  is coupled between the base of transistor Q P3  and the top rail, and current source  58  is coupled between the base of transistor Q P4  and the top rail, as shown. Thus, amplifier  54  determines the difference between bias potentials V B3  and V B4 . Circuit  45  (which includes transconductance amplifier  55 ) sets the common mode voltage V B3 +V B4 )/2 to an appropriate level determined by bias potential V CM-SET  (which is asserted to the inverting input of transconductance amplifier  55 ). The noninverting input of transconductance amplifier  55  is coupled between resistors R B1  and R B2 , and resistors R B1  and R B2  are connected in series between the base of Q P3  and the base of QP 4 . The output of amplifier  55  is connected to the common gates of NMOS transistors Q 54  and Q 55 . The drain of Q 55  is coupled to the base of Q P4 , and capacitor C B  is coupled between the base of Q P3  and the base of Q P4 . Capacitor C BN  is coupled between the output of amplifier  55  and the bottom rail. 
     It is well known that any of many different architectures are possible for implementing a preamplifier for a magneto-resistive transducer (e.g., the transducer shown in FIG. 1A whose resistance is R MR ). All the architectures (including that of FIG. 1A) must perform the following functions: generate an appropriate bias current through the transducer; maintain the common mode voltage of the transducer ((V 2 +V 1 )/2, where V 2 −V 1  is the voltage across the transducer) at an appropriate level to prevent electrical discharge to the disk (or other object being sensed) and to allow voltage headroom (source-to-drain or collector-to-emitter voltage) for the various current source and amplifier transistors; and bias the amplifier transistors at appropriate voltages to sense and amplify the differential voltage across the transducer while minimizing the d.c. or low frequency component of the preamplifier&#39;s differential output voltage. 
     Although the transducer&#39;s resistance R MR  varies with time during normal circuit operation, conventional circuitry for determining the magnitudes of bias potentials V BP  and V BN  cannot adjust the magnitudes of bias potentials V BP  and V BN  (in real time) during normal circuit operation to maintain optimized performance despite the varying transducer resistance. It would be desirable to generate a resistance signal indicative of the transducer resistance during normal operation (in addition to the conventional preamplifier output which is indicative of the potential difference across the transducer; not the transducer&#39;s resistance). Such a resistance signal could be used as feedback to circuitry for maintaining optimal biasing of the transducer. 
     It should be appreciated that the conventional preamplifier output (which is indicative of voltage across the transducer; not the transducer&#39; resistance) is indicative only of high frequency components of the voltage across the transducer, since the preamplifier acts as a high pass filter. Such a conventional output signal gives no indication of the d.c. component of the bias voltage for the transducer (or the low frequency components of such bias voltage). To indicate the d.c. bias voltage for the transducer, the standard practice in the prior art is to provide a separate, buffered d.c. output which can be either an analog voltage (indicative of the d.c. bias across the transducer) or the output of an analog-to-digital converter (in response to such an analog voltage). The output of such an analog-to-digital converter can be accessed through a serial port by an external microcontroller running appropriate firmware. It is conventional to employ firmware to deduce the resistance of the transducer by processing a signal indicative of the current through the transducer (usually selected by the firmware through a digital-to-analog converter coupled with the preamplifier), and the buffered d.c. output indicative of d.c. bias voltage across the transducer. However, this prior art technique is cumbersome and inaccurate. It would be desirable to generate a resistance signal indicative (accurately) of the instantaneous value of transducer resistance during normal operation (while the transducer is biased and in the presence of a magnetic field), so that the resistance signal can be used as feedback to circuitry for maintaining optimal biasing of the transducer. 
     When implementing magnetic disk drive systems (which use a magneto-resistive transducer as read heads), if the disk drive systems do not continuously optimize the d.c. bias voltage for the magneto-resistive transducer in real time, it is possible to make a one-time adjustment to the d.c. bias voltage as a result of determining part-to-part variation in the resistance of magneto-resistive heads. Such an adjustment could be performed during the manufacture of the disk drive system. However, it would be preferable during normal operation of such a disk drive system to monitor the resistance of the transducer and employ feedback to maintain optimal biasing of the transducer. 
     In resistive transducers other than magneto-resistive transducers, the resistance of the transducer varies in response to a parameter being sensed. As in the case of magneto-resistive transducers, it would often be useful (during preamplification of the potential difference across any of the other types of resistive transducers) to generate a signal indicative of the transducer&#39; resistance (in addition to the preamplifier output which is indicative of the potential difference across the transducer). 
     SUMMARY OF THE INVENTION 
     In preferred embodiments, the invention is a preamplifier for a resistive transducer, which is configure d to generate an amplified output signal indicative of high frequency components of the time-varying potential difference across the transducer (while the transducer is biased and in the presence of a magnetic field), and also to generate a resistance signal indicative of the transducer&#39; resistance (while the transducer is biased and in the presence of a magnetic field). The preamplifier preferably includes circuitry for generating a current signal indicative of the instantaneous current through the transducer and analog divider circuitry for generating the resistance signal from the amplified output signal (or other signal indicative of the potential difference across the transducer, including d.c. or low frequency components of this potential difference) and the current signal. 
     In cases in which the resistance signal is an analog signal, circuitry can be provided for processing the analog resistance signal to generate a word (e.g., byte) of binary data indicative of a value proportional to the transducer resistance (i.e., KR MR , where the proportionality constant K has a known value). Alternatively, when the resistance signal is an analog signal the inventive circuit can include a digital-to-analog (D-to-A) converter and comparator (which receives an analog resistance signal and the output of the D-to-A converter). In operation of the latter class of embodiments, the output of the D-to-A converter is swept until the comparator is tripped, at which time the setting of the D-to-A converter is proportional to the transducer resistance. 
     In other embodiments, the invention is a method for measuring the resistance of a resistive transducer (preferably while generating a signal indicative of potential difference across the transducer) during normal operation of the transducer, while the transducer is biased and in the presence of a magnetic field. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a portion of a conventional preamplifier circuit connected to a magneto-resistive transducer. 
     FIG. 1A is a schematic diagram of a conventional preamplifier circuit connected to a magneto-resistive transducer. 
     FIG. 2 is a schematic diagram of a preferred embodiment of the inventive circuit, connected to a magneto-resistive transducer. It is contemplated that this circuit will typically be implemented as an integrated circuit or portion of an integrated circuit. 
     FIG. 3 is a block diagram of an implementation of current source  5  of FIG.  2 . 
     FIG. 4 is a schematic diagram of a first portion of a preferred implementation of a portion of the FIG. 2 circuit, in which the current IRDV 48  corresponds to current (I MR )/N drawn from Node  5  of FIG.  2 . 
     FIG. 5 is a schematic diagram of a second portion of a preferred implementation of the FIG. 2 circuit, which performs the function of transistor Q 11  of FIG. 2, and whose nodes labeled Node  6  and Node  8  correspond respectively to the identically labelled nodes of FIG.  4 . 
     FIG. 6 is a schematic diagram of a third portion of a preferred implementation of the FIG. 2 circuit, whose nodes labeled Node  10  and Node  11  correspond respectively to the identically labelled nodes of FIG.  4 . 
     FIG. 7 is a block diagram of analog-to-digital conversion circuitry  10  for processing the output signal (V OUT ) of the FIG. 2 circuit. 
     FIG. 8 is a block diagram of circuitry for processing the output signal (V OUT ) of the FIG. 2 circuit. 
     FIG. 9 is a schematic diagram of part of a variation on the FIG. 2 embodiment of the inventive circuit, connected to a magneto-resistive transducer. The remaining portion of this variation has the same structure as does that portion of FIG. 2 other than elements M 1 , R MR , M 2 , M 3 , Q P1 , Q P2 ,  3 ,  4 , Q 1 , Q 2 , and R 1 . 
     FIG. 10 is a schematic diagram of part of another variation on the FIG. 2 embodiment of the inventive circuit, connected to a magneto-resistive transducer, in which transistors M 2  and M 4  are omitted and the transducer is connected between transistor M 1  and ground. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A preferred embodiment of the inventive preamplifier circuit will be described initially with reference to FIGS. 2 and 3. The FIG. 2 embodiment is an improved version of the FIG. 1 circuit, which includes amplifier  2  (having inputs coupled to opposite ends of the transducer whose resistance is R MR , as does the amplifier of FIG. 1 which comprises transistors Q P1 , Q P2 , Q P3 , and Q P4 , and current sources  3  and  4 ) and biasing transistors M 1  and M 2  as does FIG. 1, and which also includes circuitry for generating resistance signal V OUT  (having a value proportional to the resistance R MR  of the transducer) The FIG. 2 circuit is coupled between a top rail (at potential V CC ) and a bottom rail (at potential V EE ). 
     The FIG. 2 embodiment can measure the resistance R MR  of the transducer while the transducer is biased by assertion of bias potentials V BP  and V BN  to the gates of transistors M 1  and M 2 , resulting in a bias potential across the transducer and flow of current I MR  through the transducer (and through transistors M 1  and M 2 ). The magnitudes of the bias potentials V BP  and V BN  are chosen as a function of the transducer resistance (e.g., the transducer resistance in the presence of no magnetic field) and other factors to optimize system performance. Preferably, V BP  and V BN are controlled to allow the correct current I MR  to flow through the transducer while keeping the common mode voltage of the transducer, (V RMRP +V RMRN )/2, where V RMRP −V RMRN  is the voltage across the transducer, at an appropriate level to prevent electrical discharge to the disk (or other object) being sensed and to allow voltage headroom (source-to-drain or collectorto-emitter voltage) for the transistors employed in the circuit. It should be understood that circuitry for generating the bias potentials V BP  and V BN  for FIG. 2 can readily be implemented using well known principles, including the conventional principles discussed above with reference to FIG.  1 A. The resistance signal V OUT  output from the FIG. 2 circuit can be used (in a way that will be apparent to those of ordinary skill in the art in view of the present disclosure) to implement circuitry for generating the bias potentials V BP  and V BN  for FIG.  2 . 
     The FIG. 2 circuit includes analog divider circuitry, coupled between Nodes  1  and  2  (the emitters of transistors Q P1  and Q P2  of amplifier  2 ) and output Node  8 , which functions to divide a signal indicative of the instantaneous potential difference across the transducer (the potential difference between Nodes  1  and  2 ) by a signal (proportional to signal I SNSP  at Node  3  or signal I SNSN  at Node  4 ) indicative of the instantaneous current (I MR ) through the transducer. Signal I SNSP  or I SNSN  is used to implement current source  5 , so that current source  5  sinks (from Node  5 ) a known fraction of the instantaneous current I MR  through the transducer. Since only one of signals I SNSP  and I SNSN  is used, either PMOS transistor M 3  or NMOS transistor M 4  is preferably omitted. If transistor M 3  is omitted, the signal I SNSN  (the drain current of transistor M 4 ) is used as the signal indicative of instantaneous current through the transducer. If transistor M 4  is omitted, the signal I SNSP  (the collector current of transistor M 3 ) is used as the signal indicative of instantaneous current through the transducer. 
     Since the gates of PMOS transistors M 1  and M 3  are connected, the ratio of the currents at the drains of these transistors depends on the size ratio of transistors M 1  and M 3  (and the current I SNSP  is proportional to the current I MR ). Since the gates of NMOS transistors M 2  and M 4  are connected, the ratio of the currents at the drains of these transistors depends on the size ratio of transistors M 2  and M 4  (and the current I SNSN  is proportional to the current I MR ). 
     FIG. 3 is a block diagram of an implementation of current source  5  of FIG.  2 . In this implementation, current source  5  sinks (from Node  5  of FIG. 2) a known fraction of the current I SNSN  (determined by known characteristics of the components of the current source), so that the current sunk from Node  5  is I MR /N, where “N” is a known constant and I MR  is the instantaneous current through the transducer. In the FIG. 4 embodiment to be discussed below, N preferably has the value N=48. The current source of FIG. 3 preferably corrects for any error currents, such as the base currents of transistors Q P1  and Q P2  or any error currents resulting from other circuitry coupled to the bases of Q P1  and Q P2 , that may alter the proportionality between I MR  and either I SNSP  or I SNSN  With reference again to FIG. 2, the base of NPN bipolar transistor Q 1  is coupled to the emitter of transistor Q P1  (Node  1 ), and the base of NPN bipolar transistor Q 2  is coupled to the emitter of transistor Q P2  (Node  2 ). The potential difference between one end of the transducer and Node  1  is V BE  of transistor Q P1 , and the potential difference between the other end of the transducer and Node  2  is V BE  of transistor Q P2  (so that by choosing Q P1  and Q P2  to have substantially the same base-to-emitter voltage, the potential difference between Nodes  1  and  2  is substantially equal to the voltage drop V MR  across the transducer). 
     In a variation on the FIG. 2 embodiment (a portion of which is shown in FIG.  9 ), the bases of transistors Q 1  and Q 2  are coupled directly to opposite ends of transducer R MR  (as are the bases of Q P1  and Q P2 ). However, such a configuration requires modification of the conventional interface (embodied in FIG. 1) between the transducer and preamplifier. An advantage of the FIG. 2 design (over that of FIG. 9) is that the conventional implementation of the very sensitive transducer-biasing circuit (elements M 1 , R MR , and M 2  connected between the top and bottom rails) need not be modified, except in the minor respect that the gate of one of the biasing transistors M 1  and M 2  is connected to the base of a transistor (M 3  or M 4 ) for generating a signal indicative of the current I MR  through the biased transducer. 
     With reference again to FIG. 2, the emitter of Q 1  is coupled through resistor R 1  to the collector of NPN bipolar transistor Q 3 , the emitter of Q 2  is coupled to the collector of Q 3 , the collector of Q 1  is coupled to the base and collector of PNP bipolar transistor Q 7  and to the base of PNP bipolar transistor Q 8 , the collector of Q 2  is coupled to the collector of Q 8  and to the base of PNP bipolar transistor Q 9 , the collector of Q 9  is coupled through resistor R FB  to the bottom rail (and to the common bases of PNP transistors Q 4  and Q 5 , the emitter of Q 3  is coupled through resistor R 2  to Node  5 , the emitter of Q 4  is coupled through resistor R 3  to Node  5 , the collector of Q 5  is coupled to the top rail, the emitter of Q 5  is coupled through resistor R 4  to current source  6 , the emitter of NPN transistor Q 6  is coupled through resistor R 5  to current source  6 , the base of each of transistors Q 3  and Q 6  is biased at potential V BIAS , the collector of Q 6  is coupled to the collector and base of PNP transistor Q 10  and to the base of PNP transistor Q 11 , the emitters of Q 9 , Q 10  and Q 11  are coupled to the top rail, the collector of Q 11  is coupled to output Node  8 , and resistor K 1 R 1  is coupled between Node  8  and the bottom rail. Transistors Q 10  and Q 11  are a current mirror, in which current I C  (flowing from the collector of Q 10  to the collector of Q 6 ) is mirrored so that current I c  flows from the collector of Q 11  through resistor K 1 R 1  (to cause the voltage drop across resistor K 1 R 1  to determine the output potential V OUT  at Node  8 ). 
     The circuitry comprising transistors Q 1 , Q 2 , Q 3 , Q 4 , Q 5 , Q 6 , Q 7 , Q 8 , Q 9 , Q 10 , and Q 11 , current sources  5  and  6 , and resistors R 1 , R 2 , R 3 , RFB, R 4 , R 5 , and K 1 R 1  is an analog divider which divides a signal indicative of the instantaneous potential difference V MR  across the transducer (the potential difference between Nodes  1  and  2 ) by a signal indicative of the instantaneous current through the transducer (a signal proportional to the current, I MR /N, sunk from Node  5 ) to generate output potential V OUT  at Node  8  whose amplitude is indicative of the instantaneous resistance of the transducer. 
     It will be apparent to those of ordinary skill in the art that the current (I 2 ) flowing to the collector of Q 2  is identical to the current (I 1 ) flowing to the collector of Q 1 , and that both currents are equal to V MR /R 1 . The current I 3  flowing to the collector of Q 3  is (A)(I MR /N), where “A” is a coefficient determined by the loop. The current I 3  satisfies I 3 =(A)(I MR /N)=2 V MR /R 1 . It follows that A=2N(R MR )/(R 1 ). The current I C  flowing to the collector of Q 6  is I c =(A)(I DAC )=2N(R MR ) (I DAC )/(R 1 ) 
     The potential V OUT  at output Node  8  is V OUT =(I C )(K 1 R 1 )=[ 2 N(K 1 )(I DAC )](R MR ). Thus, since k 1  and N are known (I MR /N is the current sunk from Node  5  by current source  5 ), V OUT  determines R MR  provided that I DAC  is known. 
     In variations on the FIG. 2 embodiment, one end of the transducer R MR  is grounded (or coupled directly to the top or bottom rail) and the other end of the transducer R MR  is coupled to a biased transistor as shown in FIG.  2 . For example, in one such variation, transistors M 2  and M 4  are omitted, and one end of transducer R MR  is coupled directly to ground (rather than to the drain of M 2 ). For example, in the variation of FIG. 10, transistors corresponding to transistors M 2  and M 4  (of FIG. 2) are omitted, and the magneto-resistive transducer is connected between transistor M 1  and the bottom rail (at potential V EE , which can be ground potential). In the FIG. 10 embodiment, the analog divider can be implemented (in a manner that will be apparent to those of ordinary skill in the art given the present disclosure) more simply than the analog divider of FIG. 2, since only the potential at Node X (at one end of the transducer) is unknown, and the potential at Node X (the other end of the transducer) is known. In the FIG. 10 embodiment, the collector current of transistor M 3  is used as the signal indicative of instantaneous current through the transducer. 
     In other variations on the FIG. 2 embodiment, the analog divider receives as an input a signal (or signal pair) whose potential (or potential difference) is proportional to or a level-shifted version of V MR , the voltage across the transducer. 
     In other variations on the FIG. 2 embodiment, the analog divider is implemented without all or some of resistors R 2 , R 3 , R 4 , and R 5 . Among the advantages of including resistors R 2 , R 3 , R 4 , and R 5  are the following: they make it easier to stabilize the feedback loop, they result in more linear gain, and they result in better performance over a wide range of values of the transducer resistance. 
     With reference again to FIG. 2, the output signal V OUT  (of FIG. 2) is an analog voltage signal whose amplitude is proportional to the transducer resistance, and it can undergo any of a variety of further processing operations. For example, if I DAC  is a known reference current, then analog-to-digital conversion circuitry  10  (indicated in FIG. 7) can be coupled to Node  8  of FIG. 2 for processing the signal V OUT  to generate byte B of binary data (comprising bits B 1 -B 8 ) indicative of either the value R MR  or the value [2N(K 1 )(I DAC )](R MR ). 
     Alternatively, one input of comparator  20  (indicated in FIG. 8) is coupled to Node  8  of FIG. 2 for comparing the signal V OUT  with a reference signal (provided to the other input of comparator  20 ). 
     If I DAC  is a known, fixed reference current, the value of the reference signal is swept to generate an output signal “OUTPUT” (at the output of comparator  20 ) indicative of a match between a value of the reference signal and the signal V OUT . The reference signal (which is an analog voltage) is generated by performing digital-to-analog (D-to-A) conversion in D-to-A converter  22  on the digital signal “TRIAL RESISTANCE VALUE” which comprises binary bits indicative (at any instant of time) of a value [2N(K 1 )(I DAC )](R TRIAL ), where R TRIAL  is a trial value (e.g., an arbitrarily selected possible value) of the transducer resistance. In operation, the output of D-to-A converter  22  is swept until the comparator output signal (“OUTPUT”) indicates that comparator  20  has tripped. The value of the digital signal TRIAL RESISTANCE VALUE at the time comparator  20  trips is equal to V OUT  and thus the value of R TRIAL  at this time is the transducer resistance. Circuitry can be provided for displaying an indication of this value of R TRIAL  or processing a signal indicative of the value of R TRIAL  (e.g., in a microcontroller running appropriate firmware) to adjust critical parameters of the pre-amplifier or other circuitry. 
     Still with reference to FIG. 8, if I DAC  is a known (but variable) current, I DAC  can be swept (to produce a varying V OUT  at a first input of comparator  20 ) while a fixed reference signal is provided to a second input of comparator  20 . The value (V ref =[2N(K 1 )(I DAC )](R ref ) of the fixed reference signal (at the second input of comparator  20 ) at the time the comparator trips is equal to V OUT  and thus the value R ref =V ref /[2N(K 1 )(I DAC )] at this time is the transducer resistance R MR . Circuitry can be provided for displaying an indication of this value of R ref . 
     With reference to FIG. 2, resistor R FB  can be replaced by a current source. Among the advantages of using resistor R FB  (rather than a current source) is that the resistor is simpler and less expensive to implement. 
     A preferred implementation of the analog divider circuitry of FIG. 2 (the analog divider circuitry coupled between Nodes  1  and  2  and output Node  8  of FIG. 2) will next be described with reference to FIGS. 4-6. Nodes  1 ,  2 , and  5  are identically numbered in FIGS.  2  and  4 - 6 . 
     FIG. 4 is a schematic diagram of a first portion of such preferred analog divider implementation, in which the current “IRDV48” corresponds to current (I MR )/N drawn from Node  5  of FIG. 2 (with N=48). The FIG. 4 circuit includes current divider  7 , whose input is coupled to the drain of transistor M 4  of FIG.  2 . In a typical implementation of FIG. 2, the current I SNSN  flowing (from the input of circuit  7 ) into the drain of M 4  (when transducer M MR  is biased for normal operation) is equal to I SNSN =I MR /12, and current divider  7  divides this current by four so that the output current IRDV48 of divider  7  has amplitude IRDV48=I MR /48. 
     In variations on the preferred embodiment, the input current to circuit  7  is supplied by an FET transistor which mirrors the current I MR  through the biased transducer R MR  (optionally with a known scaling factor other than one or four), and circuit  7  is either omitted (replaced by a short circuit) or configured to scale the current it receives by a factor other than twelve) so that the current drawn from Node  5  is the current I MR  divided or multiplied by some factor other than 48. In the preferred implementation shown in FIG. 4, circuit  7  should not saturate at V EE +1.7 volts. 
     As explained above, the potential difference between Nodes  1  and  2  of FIG. 4 (and FIG. 2) is equal (or at least substantially equal) to the potential difference V MR  across the biased transducer. Node  1  is coupled through resistor R p  (having resistance 5 KOhms in the preferred implementation, as indicated) to the base of Q 1  and the base of NPN bipolar transistor Q 28  (whose emitter is coupled through diode-connected bipolar transistor Q 21  to ground potential “COM”), and Node  2  is coupled through resistor R n  (having resistance 5 KOhms in the preferred implementation, as indicated) to the base of Q 2 . Resistors R 1   a , R 1   b , R 1   c , and R 1   d  (coupled between the emitters of Q 1  and Q 2 ) correspond to resistor R 1  of FIG. 2, and have a total resistance of 12.22 KOhms in the preferred implementation. The emitter of Q 2  is coupled to the collector of Q 3 , the emitter of Q 3  is coupled to Node  5  through resistors R 3   a  and R 3   b  (corresponding to R 3  of FIG.  2 ), the collector of Q 4  is grounded, and the emitter of Q 4  is coupled to Node  5  through resistors R 4   a  and R 4   b  (corresponding to R 4  of FIG.  2 ). The sources of PMOS transistors M 5 , M 6 , M 7 , M 8 , M 17 , M 43 , and M 45  are coupled to the top rail (at potential V CC ) and the sources of NMOS transistors M 10  and M 11  are coupled to the bottom rail. The drain of M 5  is coupled to the drain of M 10 , the drain and gate of M 6  are coupled to the collector of Q 1 , the drain of M 7  is coupled to the collector of Q 2  and the gate of M 8 , and the drain of M 8  is coupled to the drain of M 11 . 
     Transistors M 6 , M 7 , and M 8  of FIG. 4 correspond respectively to Q 7 , Q 8 , and Q 9  of FIG.  2 . The collector of NPN bipolar transistor Q 34  is coupled to the top rail, the emitter of Q 34  is coupled to the collector of NPN bipolar transistor Q 56 , the emitter of Q 56  is connected through resistors R 59 A, R 59 B, and R 59 C to the bottom rail, the base of Q 56  is biased by V 2 , and the base of Q 34  is coupled to the common bases of Q 4  and Q 5 . 
     Diode-connected PMOS transistor M 17  of FIG. 4 corresponds to transistor Q 10  of FIG. 2, the drain of M 17  being connected to the collector of Q 6 . The collector of Q 5  is coupled to the top rail, the emitter of Q 5  is coupled through resistors R 5   a  and R 5   b  (corresponding to R 4  of FIG. 2) to Node  13 , and the emitter of Q 6  is coupled through resistors R 6   a  and R 6   b  (corresponding to R 5  of FIG. 2) to Node  13 . Circuit  16  (to be described below, and which corresponds to current source  6  of FIG. 2) sinks constant current I eeref  from Node  13 . 
     Circuit  18  (coupled between circuit common and Node  9 ), and bipolar transistor Q 58  and resistors R 63 A, R 63 B, and R 63 C of circuit  16  (coupled between Node  9  and the bottom rail), hold Node  9  at bias potential V bias . Thus, the bases of Q 3  and Q 6  are maintained at bias potential V bias . 
     PMOS transistor M 43  and resistor R 11  maintain Node  10  of FIG. 4 at reference potential V reffb . 
     With reference to FIG. 5, a portion (I 86 ) of the current I c  flowing from Node  6  to transistor Q 6  flows from PMOS transistor M 86  to Node  6 , and another portion (I 122 ) of the current I c  flows from PMOS transistor M 122  to Node  6 . In response, depending on the state of each of binary control signals C 1 , C 2 , and C 3  (which are asserted with different combinations of values depending on the range of resistances in which the transducer resistance R MR  falls). 
     Transistors M 18  and M 19  of FIG. 5 correspond functionally to transistor Q 11  of FIG. 2 in the following sense (and the other circuitry of FIG. 5 is logic circuitry for selectively turning one or both of M 18  and M 19  off or on and coupling one or both of M 18  and M 19  to Node  6  of FIG.  4 ). In FIG. 2, the current through the collector of Q 11  mirrors current I c  through the collector of Q 10 . In the embodiment of FIGS. 4 and 5, the combined current (K/2)I c  through the channels of PMOS transistors M 18  and M 19  mirrors (with a selectable scaling factor K/2) the current I c  through the channel of transistor M 17 . The sizes of devices M 17 , M 18 , and M 19  are different. Specifically, although the channel length and width characteristics of M 17 , M 18 , and M 19  are the same (“w”=53 u, and “1”=5 u), the multiplicity (“m”) characteristic of each is different (m=2 for transistor M 17 , m=7 for transistor M 18 , and m=4 for transistor M 19  as indicated). 
     For example, when C 2  is high and C 1  and C 3  are low, FET transistors M 83 , M 128 , M 102 , M 89 , M 99 , M 123 , M 127 , M 124 , M 90 , M 84 , M 125 , and M 126  (connected as shown) are respectively off, off, on, on, off, off, on, on, off, on, on, and off, so that PMOS transistor M 87  is on, PMOS transistor M 86  is off, PMOS transistor M 121  is off, and PMOS transistor M 122  is on. Thus, M 19  is off, the current I 18  through the channel of M 18  is (7/2)I c , and thus the current through resistors R 2   a , R 2   b , R 2   c , and R 2   d  is I 18 +I 19 =(7/2)I c . 
     For another example, when C 3  is high and C 1  and C 2  are low, FET transistors M 83 , M 128 , M 102 , M 89 , M 99 , M 123 , M 127 , M 124 , M 90 , M 84 , M 125 , and M 126  are respectively off, off, off, on, on, on, on, off, on, off, off, and on, so that PMOS transistor M 87  is off, PMOS transistor M 86  is on, PMOS transistor M 121  is on, and PMOS transistor M 122  is off. Thus, M 18  is off, the current I 19  through the channel of M 19  is (4/2)I c , and thus the current through resistors R 2   a , R 2   b , R 2   c , and R 2   d  is I 18 +I 19 =(4/2)I c =2I c . 
     For another example, when C 1  is high and C 2  and C 3  are low, PMOS transistor M 87  is off, PMOS transistor M 86  is on, PMOS transistor M 121  is off, and PMOS transistor M 122  is on. Thus, the current I 18  through the channel of M 18  is (7/2)I c , the current I 19  through the channel of M 19  is (4/2)I c , and thus the current through resistors R 2   a , R 2   b , R 2   c , and R 2   d  is I 18 +I 19 =(11/2)I c . 
     Thus, depending on the state of control bits C 1 -C 3 , output Node  8  is at potential V OUT =(N/2)I c (R 2   a +R 2   b +R 2   c +R 2   d ), where N=4, 7, or 11. Since (R 2   a +R 2   b +R 2   c +R 2   d )=R 1 =(R 1   a +R 1   b +R 1   c +R 1   d ), and I c  is related by a known proportionality constant to (V MR )/(I MR )=R MR , it follows that V OUT  is proportional to R MR  (with a known proportionality constant relating V OUT  and R MR ). 
     With reference next to FIG. 6, we next describe op amp circuitry for generating signal V 2  (at Node  11  of FIG. 4) for biasing transistors Q 57 , Q 58 , and Q 59  of circuit  16  of FIG.  4 . FIG. 6 is a schematic diagram of such op amp circuitry. The Nodes labeled Node  10  and Node  11  in FIG. 6 correspond to the identically labelled Nodes of FIG.  4 . The FIG. 6 circuitry receives reference current I 8 U (which is an  8  microAmp current in the preferred implementation) at Node  12 , and Node  10  (and thus the base of PNP bipolar transistor Q 47 ) is maintained at reference potential V reffb . Current I 8 U flows to ground (at ground potential COM) through resistor R 10  (comprising series-connected resistors R 10   a , R 10   b , R 10   c , R 10   d , R 10   e , R 10   f , and R 10   g ), and thus the base of PNP bipolar transistor Q 48  (coupled to Node  12 ) is at potential V I8U . 
     The source of PMOS transistor M 36  is coupled to the top rail, the drain and gate of M 36  are coupled to the collector of NPN bipolar transistor Q 50 , the emitter of Q 50  is coupled to ground through resistor R 26 , and Q 50  is biased by potential VP 1250  which is provided from an external source to its base. The source of PMOS transistor M 36  is coupled to the top rail, the drain of M 36  is coupled through resistors R 8   a ,R 8   b  and R 7   a ,R 7   b  respectively to the emitters of Q 47  and Q 48 , and the gate of M 36  the is coupled to the gate of M 36  so that the current at the drain of M 36  is mirrored to flow at the drain of M 36 . The collector of Q 47  is coupled to the collector of NPN bipolar transistor Q 46 , the collector of Q 48  is coupled to the collector of NPN bipolar transistor Q 45 , the emitters of Q 46  and Q 45  are coupled to the bottom rail, and the common bases of Q 45  and Q 46  are coupled through resistor R 60  to the bottom rail. The emitter of NPN bipolar transistor Q 51  is coupled to the bases of Q 46  and Q 45 , the collector of Q 51  is grounded, and the base of Q 51  is coupled to the collector of Q 45 . The base of NPN bipolar transistor Q 20  is coupled to the collector of Q 46 , the collector of Q 20  is grounded, and the emitter of Q 20  is coupled through resistors R 61  and R 62  to the bottom rail. The base of NPN transistor Q 21  is coupled to Node  11 , the collector of Q 21  is grounded, and the emitter of Q 21  is connected between resistors R 61  and R 62 . 
     Thus, the op amp circuitry of FIG. 6 maintains Node  11  at bias potential V 2 , whose level is chosen to bias transistors Q 57 , Q 58 , and Q 59  of circuit  16  of FIG. 4 (and transistor Q 56 ) so that circuit  16  operates in the manner described herein. 
     Within circuit  16 , NPN bipolar transistor Q 59  is biased (by potential V 2  at its base) so that the current I Q59  from transistor Q 51  into the collector of Q 59  is equal to I Q59 =4(R 10 /R 11 )(I 8 U)=32 microAmps (R 10 /R 11 ). NPN bipolar transistor Q 57  (also connected within circuit  16 ) is biased (by potential V 2  at its base) so that current I eeref  from Node  13  into the collector of Q 57  is equal to I eeref =[(R 65   a +R 65   b +R 65   c +R 65   d )/(R 64   a +R 64   b +R 64   c +R 64   d )]I Q59 =[(R 65   a +R 65   b +R 65   c +R 65   d )/(R 64   a +R 64   b +R 64   c +R 64   d )](R 10 /R 11 )(32 microAmps). 
     In operation of the embodiment of FIGS. 4-6, assuming that resistors R 1   a , R 1   b , R 1   c , and R 1   d  have a total resistance R 1 =12.22 KOhms (as indicated in FIG.  4 ), if the transducer resistance R MR  is equal to the nominal value R nom =63.6 Ohms, then half of the current IRDV48 flows through transistor Q 3  (and resistors R 1   a , R 1   b , R 1   c , and R 1   d ) and the other half through transistor Q 4 . If transducer resistance R MR  increases above R nom , then the potential at the base of Q 4  drops, less than half of the current IRDV48 flows through transistor Q 4 , and more than half of the current IRDV48 flows through Q 3  and resistors R 1   a , R 1   b , R 1   c , and R 1   d . Similarly, I c  (from transistor M 17  into the collector of transistor Q 6 ) increases, since current I eeref  drawn from Node  13  (by circuit  16 ) remains fixed. As a result, the output potential V OUT  at Node  8  increases in proportion to the increase in transducer resistance R MR . 
     In the embodiment of FIGS. 4-6, instead of mirroring the current I c  through M 17  (as in FIG. 2, assuming that transistors Q 10  and Q 11  of FIG. 2 have the same size) so that I c  flows to circuit common through resistors R 2   a , R 2   b , R 2   c , and R 2   d  (which correspond to resistor K 1 R 1  of FIG.  2 ), current I 18  (from the drain of M 18  and current I 19  (from the drain of M 19 ) combine to produce scaled current (N/2)I c  which flows through to circuit common through resistors R 2   a , R 2   b , R 2   c , and R 2   d  of FIG.  4 . As explained about with reference to FIG. 5, the factor N is selectable by controlling the state of each of control bits C 1 , C 2 , and C 3 . 
     It should be appreciated that in variations on the described embodiments, PNP bipolar transistors and a current source can replace NPN bipolar transistors and a current sink (e.g., NPN bipolar transistors Q 3  and Q 4 , with current source  5  for sinking current from Node  5 , of FIG.  2 ). In other variations on the described embodiments, FET transistors replace all or some of the bipolar transistors of the described embodiments, and bipolar transistors replace all or some of the FET transistors of the described embodiments. The invention can be implemented with circuitry whose transistors are all FET transistors, or all bipolar transistors, or a combination of FET and bipolar transistors. 
     Throughout the specification, including in the claims, the terms “connected” and “coupled” are used interchangeably, in a broad sense denoting either a direct electrical connection between the things connected or coupled (with no intermediate devices) or an indirect connection (e.g., through one or more passive or active intermediate devices). 
     The invention can be implemented by modifying any of the many different conventional architectures for implementing a preamplifier for a magneto-resistive transducer (R MR ), including the architecture of FIG. 1, to include resistance measurement circuitry including an analog divider in accordance with the invention. In all embodiments, the resistance measurement circuitry receives signals indicative of the current through the biased transducer and the potential at each end of the transducer (or any proportional analog of such signals). In the FIG. 2 embodiment, the resistance measurement circuitry receives signals indicative of current I MR  through biased transducer R MR  and the potentials at Nodes  1  and  2 . In alternative embodiments, the signal indicative of current I MR  through the biased transducer can be replaced by a signal indicative of the drain current of transistor M 0 , M 1 , or M 2  (of FIG.  1 A), the voltage across resistor R SETP , or the current I DAC-RMR , or any other signal proportional to I MR  (such as signals generated by current mirrors and sense resistors). Depending on the choice of signal, a correction circuit may be added or subtracted to compensate for the base currents of transistors Q P1  and Q P2  (or other transistors performing the same or similar function), and/or the current through resistors R DIF1  and R DIF2  (or other resistors performing the same or similar function). 
     Preferred embodiments of the invention have been described with reference to FIGS. 2-10. Although these embodiments have been described in some detail, it is contemplated that many changes from (and variations on) these embodiments can be made without departing from the spirit and scope of the invention as defined by the appended claims.