Abstract:
A method for producing a semiconductor device including the steps of forming an insulating layer on a substrate, the insulating layer having a plurality of concave portions, forming a non-single crystalline silicon layer on the surface of the insulating layer. The non-single crystalline silicon is patterned so that each concave portion is independently melted and the patterned non-single crystalline silicon layer flows into each of the concave portions to form a single crystalline region by irradiation with an energy ray; and, a semiconductor element is also formed in the single crystalline region.

Description:
This is a continuation of copending application Ser. No. 07/342,646 filed on Apr. 24, 1989, now abandoned, which is a continuation of application Ser. No. 233,890 filed on 8/18/88, abandoned; which is a continuation of application Ser. No. 105,495, filed 10/2/87, abandoned; which is a continuation of application Ser. No. 943,843, filed 12/22/86, abandoned; which is a continuation of application Ser. No. 823,839, filed 1/31/86, abandoned; which is a continuation of application Ser. No. 706,896, filed 2/28/85, abandoned; which is a continuation of application Ser. No. 454,078, filed 12/28/82, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a method for producing a semiconductor device, more particularly to a method for producing a semiconductor device on a single crystallized region which is formed in a concave portion of an insulating layer by melting polycrystalline silicon or amorphous silicon therein. 
     In one method for forming elements in a semiconductor device, proposed by the present inventors in Japanese Unexamined Patent Publication (Kokai) No. 55-98397 and Japanese Patent Application No. 56-154012 (filed Sept. 30, 1981), concave portions are formed in an insulating layer formed on a substrate, a polycrystalline silicon layer is formed on the insulating layer, and the polycrystalline silicon is melted by irradiation with a laser, electron beam, lamp, or other energy ray over the polycrystalline silicon layer to cause the polycrystalline silicon to flow into the concave portions, thereby forming single crystallized regions therein. 
     The problem with this method is that while the upper surfaces of the resultant single crystallized regions in the concave portions should be level with the nonconcave portions of the insulating layer, this is difficult in practice. When the molten polycrystalline silicon flows into the concave portions, more tends to flow into some portions than others. This results in some single crystallized regions protruding above and other regions recessed below the level of the nonconcave portions of the insulating layer. Further, some of the molten polycrystalline silicon may not flow into the concave portions and will remain on nonconcave portions. These problems complicate the process of production of the semiconductor device. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a method for producing a semiconductor device wherein a plurality of single crystallized regions can be formed in concave portions of an insulating layer with the upper surfaces of the regions level with the nonconcave portions of the insulating layer. 
     It is another object of the present invention to provide a method for producing a semiconductor device wherein the isolation, single crystallization of silicon, and uniform distribution as well as activation of impurities implanted or doped into the polycrystalline silicon formed in the concave portions can be simultaneously carried out. 
     According to the present invention, there is provided a method for producing a semiconductor device comprising the steps of: forming an insulating layer on a substrate, the insulating layer having a plurality of concave portions forming a non-single crystalline silicon layer on the surface of the insulating layer; patterning the non-single crystalline silicon layer so that each concave portion independently melt and flow into the concave portion to form a single crystalline region in the concave portion by irradiation with an energy ray; and forming a semiconductor element in the single crystalline region. 
     The present invention will now be explained in more with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIGS. 1A to 1U and FIG. 2 are schematic cross-sectional views of a method in accordance with an embodiment of the present invention and; 
     FIGS. 3 to 5 are schematic cross-sectional views of other embodiments of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIGS. 1A to 1U and FIG. 2, an embodiment of the method according to the present invention, first an insulating layer 12 having a thickness of approximately 1 μm (micron) is formed on a silicon substrate 11 (FIG. 1A). The insulating layer 12 is preferably selected from the group consisting of silicon dioxide, silicon nitride, oxi-nitride and alumina. 
     A photoresist layer 16 is formed on the insulating layer 12 and is exposed to ultraviolet rays or other energy rays 18 through a masking material 17, such as a glass mask (FIG. 1B). 
     The exposed region of the photoresist layer 16 is hardened by development thereof and the unexposed portion is removed, thereby forming exposed portions 12a of the insulating layer 12 (FIG. 1C). 
     Using the remaining photoresist layer 16 as a masking material, the exposed portions 12a of the insulating layer 12 are etched to form concave portions 14a having a depth of, for example, 0.9 μm, i.e., a thickness (d) of 0.1 μm, and nonconcave portions 14b (FIG. 1D). 
     A silicon layer 13 having a thickness of, for example, 0.4 μm is formed on the entire surface of the insulating layer 12, including the concave portion 14a and nonconcave portions 14b, by a chemical vapor deposition (CVD) process (FIG. 1E). The silicon layer 13 is preferably selected from the group consisting of polycrystalline silicon and amorphous silicon. 
     The silicon layer 13 is etched along the nonconcave portions 14b using, for example, a photoresist (not shown) as a masking material, to separate the layer 13 into different sections (FIG. 1F, FIG. 2). In the present invention, the width d 1  of the etched portion should be selected so that the amount of silicon in each section, i.e., the silicon remaining on the nonconcave portion 14b (regions 13a) around each concave portion 14a (regions 13b), corresponding to the amount of width d 2 , equals the volume of the concave portion 14a. In this example, the width d 1  is selected to be 5 μm. 
     A photoresist layer 20 is formed on the silicon layer 13 of the concave portions 14a to form the P channel regions (left portion FIG. 1G) and arsenic ions are implanted in the silicon layers 13 of the concave: portions 14a to form the N channel regions (right portion in FIG. 1G). 
     The above photoresist layer 20 is removed, another photoresist layer 20 is formed on the silicon layers 13 to form the N channel regions (right portion in FIG. 1H), and boron ions are implanted in the silicon layers 13 of the concave portions 14a to form the P channel regions (left portion in FIG. 1H). 
     The above photoresist layer 20 is removed and the surfaces of the silicon layers 13 are oxidized to form polyoxide layers 22 (FIG. 1I). The polyoxide layers 22 prevent the doped ions from diffusing to portions other than the silicon layers 13. 
     CVD or other processes are then used to form a capping insulating layer 23 of phosphosilicate glass or other materials of a thickness of approximately 1 μm over the entire surface of the insulating layer 12 and polyoxide layer 22. An energy ray 24, selected from the group consisting of laser beams, electron beam, lamps, carbon heaters, etc., is then irradiated over the insulating layer 23 to the silicon layers 13. The regions 13a of the silicon layers 13 in the concave portions 14a of the insulating layers 12 melt earlier than the regions 13b on the nonconcave portions 14b because the former is closer to the silicon substrate 11, which acts as a heat sink (FIG. 1J). 
     The silicon in the regions 13b melts and flows into the concave portions 14a, leaving the cavities 25. It mixes with the silicon of regions 13a and is single crystallized as regions 26. Simultaneously, the previously implanted impurities for forming the N and P channel regions are uniformly distributed and activated (FIG. 1K). 
     The insulating layer 23 and polyoxide layer 22 are removed. The upper surfaces of the regions 26 are substantially level with, for example only about 0.12 μm higher than, the nonconcave portions 14b of the insulating layer 12 (FIG. 1L). 
     After this, semiconductor elements, advantageously complementary metal oxide semiconductors (C-MOS), bipolar integrated circuits (IC), metal semiconductor, or junction and field effect transistor semiconductor display devices can be formed on the regions 26. Taking a C-MOS for example an insulating layer 27 of, for example, silicon dioxide having a thickness of 0.05 μm, is formed on the insulating layer 12 and the regions 26 (FIG. 1M). 
     Next, a silicon layer 28 of a thickness of, for example, about 0.3 μm is formed on the insulating layer 27 by a CVD or other process (FIG. 1N). 
     The silicon layer 28 is etched using a masking material (not shown) to form gate electrodes 28 on the insulating layer 27 (FIG. 10). 
     The surfaces of the gate electrodes 28 are oxidized to form thereon silicon dioxide layers 29 having a thickness of approximately 0.1 μm (FIG. 1P). 
     A photo mask 30 is formed on the P channel region, (left side in FIG. 1Q), and a 5×10 15  ions/cm 2  dose of arsenic ions 21a are implanted in the N channel regions (right side in FIG. 1Q) with 150 KeV to form source region S and drain region D of MOS therein (FIG. 1Q). 
     The above photo mask 30 is removed, after another photo mask 30 is similarly formed on the N channel region, and a 5×10 15  ions/cm 2  dose of boron ions 21b with 70 KeV are implanted in the P channel region to form source region S and drain region D therein (FIG. 1R). 
     The above photo mask 30 is removed, and insulating layers 31 are formed on the source regions S, drain regions D and insulating layers 29 by annealing (FIG. 1S). 
     A polycrystalline silicon layer 33 having a thickness of approximately 1 μm is formed on the insulating layers 12 and 31 (FIG. 1T). 
     Finally, the polycrystalline silicon layer 33 is etched at portions 34 to make contact holes on the source regions S and drain regions D. Aluminum wirings 35 are formed on the source regions S and drain regions D through the contact holes 34. 
     This completes the C-MOS. 
     In another embodiment of the present invention, a hole 40 penetrating to the silicon substrate 11 may be formed in the non-concave portion 14b of insulating layer 12, as shown in FIG. 3, so that the silicon of layer 43 is single crystallized with the same crystal orientation as that of the silicon substrate 11. 
     Further, another concave portion 51 may be formed at the bottom of the concave portion 14a, as shown in FIG. 4, so that the silicon positioned in the concave portion 51 melts and cools earlier than that in other portions and forms the nucleus for larger single crystalline silicon. 
     Still further, a hole 61 penetrating to the silicon substrate 11 may be formed in the bottom of the concave portion 14a, as shown in FIG. 5, so that the area of the silicon substrate 11 positioned near the hole 61 forms the nucleus for single crystallization of the molten silicon. 
     As is clear from the above explanation, according to the present invention, the process for producing a semiconductor device can be remarkably shortened.