Abstract:
A semiconductor transistor comprising a substrate having an active layer formed thereon, a source and a drain formed in the active layer, a gate insulating layer formed on the active layer and a gate electrode formed on the insulating layer, wherein the active layer has at least one recombination center which is located between the source and the drain and which extends from the substrate side through the active layer for less than the full depth thereof. The transistor can be fabricated by depositing the recombination centers on the substrate prior to depositing the active layer or by other methods such as diffusing material from the substrate side into the active layer.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention relates to semiconductor transistors and has particular application to thin film polycrystaline transistors. 
     2. Description of Related Art 
     Herein the abbreviation I D  is used to refer to the transistor drain current, V G  is used to refer to the transistor gate voltage generally, V DS  is used to refer to the transistor drain to source voltage, and V GS  is used to refer to the transistor gate to source voltage. Furthermore, herein the word “on”, such as in the description of one film or layer being “formed on another” is not intended to require direct contact between the two layers. That is, for example, it should not be interpreted as excluding arrangements in which another layer or film is interposed between the one layer which is formed “on” the other. 
     Unlike the output characteristics (I D V DS  ) of single crystal MOSFETs, a saturation regime is not observed, for example, in a polycrystaline silicon thin film transistor. Instead, as shown in FIG. 1, when the device.is operating above the so-called pinch-off level, generally when V DS &gt;V GS , high electric fields are formed near the drain and this results in so-called impact ionisation. The result is an increase in drain current I D  which is often referred to as the kink effect. This effect increases power dissipation and degrades the switching characteristics in digital circuits, whilst reducing the maximum obtainable gain as well as the common mode rejection ratio in analogue circuits. 
     The kink effect is also affected by the so-called parasitic bipolar effect, which is well known in silicon-on-insulator (SOI) devices. This occurs when electron-hole pairs are generated with impact ionisation at high electric fields near the drain, resulting in the holes drifting towards the source and causing a potential barrier lowering at the source junction. This effect also occurs in polysilicon thin film transistors and is due to the fact that the thin film active layer acts as the base of a bipolar transistor. 
     SUMMARY OF THE INVENTION 
     Against this background and with a view to providing an improved semiconductor transistor, in a first aspect the present invention provides a semiconductor transistor comprising a substrate having an active layer formed thereon, a source and a drain formed in the active layer, a gate insulating layer formed on the active layer and a gate electrode formed on the insulating layer, wherein the active layer has at least one centre which is located between the source and the drain and which extends ate side through the active layer for less than the full depth thereof. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     According to a second aspect of the present invention there is provided a method of manufacturing a semiconductor transistor according to the first aspect of the invention. 
     Embodiments of the present invention will now be described in more detail and by way of further example only with reference to the accompanying drawings, in which: 
     FIG. 1 illustrates the I D −V DS  output characteristic of a conventional polycrystaline silicon thin film transistor; 
     FIGS.  2 ( a )- 2 ( f ) illustrate the processing steps for forming a gate overlapped lightly doped drain device; 
     FIGS.  3 ( a )- 3 ( f ) illustrate the process steps for forming a split gate non-overlapped device; 
     FIGS.  4 ( a )- 4 ( c ) illustrate the-process steps for forming another split gate non-overlapped device; and 
     FIGS.  5 ( a )- 5 ( g ) illustrate the process steps for forming a transistor according to an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     The formation of a gate overlapped lightly doped drain transistor will now be described with reference to FIG.  2 . First, as shown in FIG.  2 ( a ), a basic layered arrangement of: a substrate  10 , a buffer oxide layer  12 , an active layer of silicon  14 , a gate oxide layer  16 , and a mask  18  are built up in that order using known techniques. The mask layer  18  is then patterned as shown in FIG.  2 ( b ). That is, two openings are formed in the mask such that ion implantation can be effected to form two lightly doped regions,  20  and  22 , in the active layer  14 ; as shown in FIG.  2 ( c ). Next the mask layer  18  is removed, as shown in FIG.  2 ( d ). A metal is then deposited and patterned so as to form the gate electrode  24 , as shown in FIG.  2 ( e ). As shown in FIG.  2 ( e ), the rightmost end of the gate electrode  24  is approximately aligned with the rightmost end of the lightly doped region  22 . A further stage of implantation is then performed, as shown in FIG.  2 ( f ), so as to form the heavily doped drain  26  and souece  28  of the transistor using the gate electrode as a mask. Thus, in the final device, the gate  24  overlaps the lightly doped region  22  which forms part of the drain. 
     The structure shown in FIG.  2 ( f ) has a two part drain, regions  22  and  26 , and a recombination region  20 . The lightly doped part of the drain, region  22 , reduces the kink effect by reducing the electric field, and hence impact ionisation, near the drain. In addition, the recombination region  20  suppresses the parasitic bipolar effect by reducing the number of holes which reach the source. These advantages are significant. However, it has been found that the structure illustrated in FIG.  2 ( f ) has a significant disadvantage in that a large gate-to-drain capacitance is established by virtue of the topography used to achieve the stated advantages. 
     The main processing steps for the formation of a transistor having a non-overlapped gate will now be described with reference to FIG.  3 . As shown in FIG.  3 ( a ), the starting position is the same as with the device described with reference to FIG.  2 ( a ). Thus, the same reference numerals are used and the description thereof will not be repeated. In this arrangement, however, the mask layer  18  is patterned in a different formation; as shown in FIG.  3 ( b ). Also, the next step is ion implantation to produce the heavily doped regions  30  and  32  in the active layer  14 ; as shown in FIG.  3 ( c ). These heavily doped regions  30  and  32  form the drain (part of) and source, respectively, of the final transistor. The mask layer  18  is removed, as shown in FIG.  3 ( d ) and then a metal layer is deposited and patterned so as to form the gate electrode  34 ; as shown in FIG.  3 ( e ). As shown in FIG.  3 ( e ), the gate electrode is split and the leftmost end of the gate electrode is aligned with the rightmost end of the source. The rightmost end of the gate electrode is not aligned with the leftmost end of the heavily doped region  30  but stops short thereof. Thus, the gate electrode is used as a mask for ion implantation to form two lightly doped regions  36  and  38 ; as shown in FIG.  3 ( f ). The lightly doped region  36  is, of course, thus aligned with the split in the gate electrode and the lightly doped region  38  abuts the heavily doped region  30 , so that regions  30  and  38  constitute the drain of the transistor. As will be readily apparent from this description and from FIG.  3 ( f ), in this structure the gate does not overlap the drain. In operation, the split parts of the gate would normally have the same voltage applied to them. 
     The arrangement shown in FIG.  3 ( f ) retains the advantages of the recombination centre and lightly doped drain of the structure shown in FIG.  2 ( f ). However, as already noted, this arrangement does not have the gate overlapping the drain. In fact, they are self aligned so that they do not overlap. The result is significantly to reduce the gate-drain capacitance which degrades the performance of the structure illustrated in FIG.  2 ( f ). 
     Another non-overlapped gate transistor is illustrated in FIG.  4 . Unlike the starting arrangements shown in FIGS.  2 ( a ) and  3 ( a ), in this arrangement the mask layer  18  is not provided but instead the metal layer  34  to form the gate electrode is first formed on the gate oxide layer  16 . This is shown in FIG.  4 ( a ). Next the metal layer is patterned to form a multiple split gate electrode  34 , as shown in FIG.  4 ( b ). It is to be noted that in the FIG. 3 arrangement a single split is formed in the gate whereas in this arrangement multiple splits are formed, with two such splits being shown. As illustrated in FIG.  4 ( c ), the multiple split gate electrode is used as a mask for ion implantation to form heavily doped regions  30 ,  32 ,  40  and  42  in the active layer  14 . The heavily doped regions  30  and  32  do, of course, form the drain and source respectively and the heavily doped regions  40  and  42  are two recombination centres, which act in a similar manner to the recombination centres  20  and  36  shown in FIGS. 2 and 3. 
     It will be immediately apparent that the number of processing steps in the arrangement of FIG. 4 is significantly reduced compared with the fabrication processes illustrated in FIGS. 2 and 3. Moreover, the whole structure is self aligned and the advantages of the FIGS.  2 ( f ) and  3 ( f ) structures are retained. Indeed, the suppression of the kink effect and the parasitic bipolar effect are enhanced due to the presence of multiple recombination centres, ie regions  40  and  42 . 
     In each of the structures shown in FIGS.  2 ( f ),  3 ( f ) and  4 ( c ) the respective recombination centres are formed by ion implantation through the gate oxide layer ( 16 ) and extend through the entire depth of the active layer ( 14 ). Difficulties can arise with such structures. Firstly, damage is often caused to the gate oxide layer during the ion implantation process used to form the recombination centres. Secondly, the fabrication processes limit the range of ion implantation materials which can be used. Thirdly, the “length” of the active layer is increased. These difficulties can be avoided by adopting the embodiment of the present invention illustrated in FIG.  5 . 
     As illustrated in FIG.  5 ( a ), the embodiment of the present invention is formed by depositing a buffer oxide layer  12  on a substrate  10  and then depositing a metal layer  44  on the buffer oxide  12 . The metal layer  44  is etched so as to leave two metal regions  46  and  48 , as shown in FIG.  5 ( b ). Next the semiconductor active layer  14  is deposited over the metal regions and the remainder of the buffer oxide  12 , as shown in FIG.  5 ( c ). A mask material  18  is deposited and etched, as shown in FIG.  5 ( d ). As shown in FIG.  5 ( e ), the mask  18  is used in ion implanting the source and drain regions,  32  and  30  respectively, in the active layer  14 . Subsequently, the mask  18  is removed and a gate oxide  16  is deposited over the active layer  14 . A metal layer  34  is deposited over the gate oxide  16 , as shown in FIG.  5 ( f ). The metal layer  34  and gate oxide  16  are etched so as to result in the final structure shown in FIG.  5 ( g ). As seen in FIG.  5 ( g ), a multiple-split gate electrode  34  is formed with the splits approximately aligned with the metal regions  46  and  48 . Also, the gate is non-overlapping with the drain. Of course, the fabrication process illustrated in FIG. 5 could be modified if desired so as to result in a gate/drain overlapped structure. 
     The metal regions  46  and  48  act as recombination centres for reducing the number of holes travelling to the source from the area next to the drain, in the same manner as described above. It will be appreciated that the various advantages discussed above with respect to the relevant features are obtained by the embodiment of the present invention. It will further be appreciated that damage to the gate oxide by ion implantation in formation of the source and drain is avoided. The range of materials which can be deposited to form the recombination centres  46  and  48  is very much less restricted than the materials which can form the recombination centres  20 , 22 ;  36 , 38  and  40 , 48 . The use of a metal to form recombination centres  46  and  48  has been described, but other material can be used. As described and illustrated, the recombination centres do not extend through the whole thickness of the active layer. As a result, the introduction of a series resistance in the active layer between the source and the drain is avoided and the ‘length’ of the active layer is thus not increased. Moreover, a thin active layer can be achieved between source and drain, which improves the driving current. That is, as the active layer becomes thinner, a point is reached at which there is insufficient active layer thickness for complete band bending to occur. This corresponds to less charge being trapped in defects and the resulting increase in free charge improves the drain current. Also, the thicker active layer region just besides the drain matches the drain junction depth and serves to decrease the lateral electric field. This reduces impact ionisation and thus the kink effect. 
     The depositing of the material for the recombination centres  46  and  48  has been described. However, other methods of establishing the recombination centres  46  and  48  can be used. For example, the recombination centres can be established by diffusing material from the substrate side or even, given the right materials and limited damage, ion implantation from the substrate side. 
     The fabrication of two recombination centres  46  and  48  has been described and illustrated. However, the number is not limited to two. One centre can be provided, or more than two. The extent of the recombination centre or centres in the thickness direction of the active layer  14  can vary from the minimum depth which it is possible to form (ie as close to zero as can be achieved) up to almost the full thickness of the active layer. 
     In the structure illustrated in FIG.  5 ( g ), the length of the active layer between the source and the drain (ie the channel length) may typically be between 0.2 μm and 100 μm, inclusive. The length of the recombination centres may typically be between 0.02 μm and 2 μm, inclusive. The distance between the-recombination centre near the drain and the drain itself may typically be between 0.02 μm and 2 μm inclusive and the distance between the recombination centres may typically be between 0.02 μm and 2 μm. From this discussion of typical dimensions it will be appreciated, inter alia, that the split gate structure of the FIG. 5 (as well as those of FIGS. 3 and 4) differs from known split gate devices since the known split gate devices have the splits evenly spaced in large dimensions across the length of the device. In this comparison reference is only being made to the gate electrode and the known split gate devices referred to have otherwise conventional structures in contrast to the recombination centres and lightly doped drains described herein. 
     The active thin film material may be an amorphous, polycrystalline or single crystal semiconductor material. 
     The devices described with reference to FIGS. 3,  4  and  5  provide suppression of the kink effect by reducing the electric field and the impact ionisation near the drain. They suppress the parasitic bipolar effect by reducing the number of generated holes reaching the source as a result of provision of the recombination centres spaced from the drain.