Abstract:
A method and a device for the coding and decoding of an information symbol for transmission over a transmission channel or a received signal value is described and illustrated, whereby a channel symbol used for coding is selected from at least two available channel symbols by means of a pre-calculated expected received signal value. The pre-calculation is achieved, based on the echo properties of the transmission channel and transmission values already sent. A pre-coding method with low receiver-side calculation requirement is thus prepared, whereby the information symbol can be transmitted by means of various channel symbols and thus various transmission values can also be transmitted. The possible selections may be used for minimization of the transmission energy and/or to achieve a minimal disturbance or even a constructive effect through the inter-symbol interference occurring on transmission.

Description:
RELATED APPLICATIONS 
     This application claims priority to U.S. Provisional Application Ser. No. 60/638,663, entitled “Bipolar Reading Technique for a Memory Cell Having an Electrically Floating Body Transistor”, filed Dec. 22, 2004. The contents of this provisional application are incorporated by reference herein in their entirety. 
    
    
     BACKGROUND 
     This invention relates to a semiconductor memory cell, array, architecture and device, and techniques for controlling and/or operating such cell and device; and more particularly, in one aspect, to a semiconductor dynamic random access memory (“DRAM”) cell, array, architecture and/or device wherein the memory cell includes an electrically floating body in which an electrical charge is stored. 
     There is a continuing trend to employ and/or fabricate advanced integrated circuits using techniques, materials and devices that improve performance, reduce leakage current and enhance overall scaling. Silicon-on-Insulator (SOI) is a material in which such devices may be fabricated on or in (hereinafter collectively “on”). Such devices are known as SOI devices and include, for example, partially depleted (PD), fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET. SOI devices have demonstrated improved performance (for example, speed), reduced leakage current characteristics and considerable enhancement in scaling. 
     One type of dynamic random access memory cell is based on, among other things, a floating body effect of SOI transistors. (See, for example, U.S. patent application Ser. No. 10/450,238, Fazan et al., filed Jun. 10, 2003 and entitled “Semiconductor Device”, hereinafter “Semiconductor Memory Device Patent Application”). In this regard, the memory cell may consist of a PD or a FD SOI transistor (or transistor formed in bulk material/substrate) on having a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation or non-conductive region (for example, in bulk-type material/substrate) disposed beneath the body region. The state of memory cell is determined by the concentration of charge within the body region of the SOI transistor. 
     With reference to  FIGS. 1A ,  1 B and  1 C, in one embodiment, semiconductor DRAM array  10  includes a plurality of memory cells  12  each consisting of transistor  14  having gate  16 , body region  18 , which is electrically floating, source region  20  and drain region  22 . The body region  18  is disposed between source region  20  and drain region  22 . Moreover, body region  18  is disposed on or above region  24 , which may be an insulation region (for example, in SOI material/substrate) or non-conductive region (for example, in bulk-type material/substrate). The insulation or non-conductive region may be disposed on substrate  26 . 
     Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s)  28 , a selected source line(s)  30  and/or a selected bit line(s)  32 . In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region  18  wherein the data states are defined by the amount of carriers within electrically floating body region  18 . Notably, the entire contents of the Semiconductor Memory Device Patent Application, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein. 
     As mentioned above, memory cell  12  of DRAM array  10  operates by accumulating in or emitting/ejecting majority carriers (electrons or holes)  34  from body region  18  of, for example, N-channel transistors. (See,  FIGS. 2A and 2B ). In this regard, accumulating majority carriers (in this example, “holes”)  34  in body region  18  of memory cells  12  via, for example, impact ionization near source region  20  and/or drain region  22 , is representative of a logic high or “1” data state. (See,  FIG. 2A ). Emitting or ejecting majority carriers  30  from body region  18  via, for example, forward biasing the source/body junction and/or the drain/body junction, is representative of a logic low or “0” data state. (See,  FIG. 2B ). 
     Notably, for at least the purposes of this discussion, a logic high or State “1” corresponds to an increased concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with a logic low or State “0”. In contrast, a logic low or State “0” corresponds to a reduced concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with a logic high or State “1”. 
     Conventional reading is performed by applying a small drain bias and a gate bias above the transistor threshold voltage. The sensed drain current is determined by the charge stored in the floating body giving a possibility to distinguish between the states “1” and “0”. Permanent scaling down of device size leads to increase of variations of the device characteristics. It is widely recognized that these variations (mismatch) is key to precision IC design. Due to mismatch, designers are forced to include substantial design margin or risk yield loss, both of which cost money and time. 
     A floating body memory device has two different current states corresponding to two different logical states: “1” and “0”. Reading is performed by comparison of a cell current with the current from a reference cell that is usually placed between the state “1” and state “0”. Large enough statistical variations in the device currents may cause an erroneous reading as it is shown in  FIG. 3 . 
     Small programming window reduces the speed or access time of the memory device, memory array, and/or memory cells. As such, there is a need for high performance reading techniques for floating body memory cells, devices and arrays providing better reading speed and robustness to technology fluctuations. 
     SUMMARY OF THE INVENTIONS 
     There are many inventions described and illustrated herein. The present inventions are neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Moreover, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For the sake of brevity, many of those permutations and combinations will not be discussed separately herein. 
     In one aspect, the present inventions are directed to an integrated circuit device comprising a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor includes a source region, a drain region, an electrically floating body region disposed between the source region and the drain region, and a gate disposed over the body region. Each memory cell includes at least (i) a first data state which is representative of a first charge in the body region of the transistor, and (ii) a second data state which is representative of a second charge in the body region of the transistor. The integrated circuit device further comprises data sensing circuitry, coupled to the memory cell, to sense the data state of the memory cell, wherein, in response to read control signals applied to the electrically floating body transistor, the electrically floating body transistor generates a bipolar transistor current which is representative of the data state of the memory cell and wherein the data sensing circuitry determines the data state of the memory cell substantially based on the bipolar transistor current. 
     The electrically floating body transistor may be an N-channel type transistor or a P-channel type transistor. 
     The read control signals may include a signal applied to the gate, source region, and drain region to cause, force and/or induce the bipolar transistor current which is representative of the data state of the memory cell. In one embodiment, the read control signals include a positive voltage pulse which is applied to the drain region of the electrically floating body transistor. In another embodiment, the read control signals include a negative voltage pulse which is applied to the drain region of the electrically floating body transistor. 
     In another principal, an integrated circuit device comprising a memory cell including an electrically floating body transistor which consists essentially of a source region and drain, each having impurities to provide a first conductivity type, a body region disposed between the source region and the drain region wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type, and a gate disposed over the body region. Each memory cell includes at least (i) a first data state which is representative of a first charge in the body region of the transistor, and (ii) a second data state which is representative of a second charge in the body region of the transistor. 
     The integrated circuit device further comprises (i) data sensing circuitry, coupled to the memory cell, to sense the data state of the memory cell, and (ii) control circuitry, coupled to the memory cell, to generate and apply read control signals to the electrically floating body transistor. In response to read control signals applied to the electrically floating body transistor, the electrically floating body transistor generates a bipolar transistor current which is representative of the data state of the memory cell and wherein the data sensing circuitry determines the data state of the memory cell substantially based on the bipolar transistor current. 
     The electrically floating body transistor of this aspect of the invention may be an N-channel type transistor or a P-channel type transistor. 
     The read control signals may include a signal applied to the gate, source region, and drain region to cause, force and/or induce the bipolar transistor current which is representative of the data state of the memory cell. In one embodiment, the read control signals include a positive voltage pulse which is applied to the drain region of the electrically floating body transistor. In another embodiment, the read control signals include a negative voltage pulse which is applied to the drain region of the electrically floating body transistor. 
     In another principal, an integrated circuit device comprising a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate. The electrically floating body transistor includes a source region and drain, each having impurities to provide a first conductivity type, a body region disposed between the source region and the drain region wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type, and a gate disposed over the body region. Each memory cell includes at least (i) a first data state which is representative of a first charge in the body region of the transistor, and (ii) a second data state which is representative of a second charge in the body region of the transistor. 
     The integrated circuit device further comprises (i) data sensing circuitry, coupled to the memory cell, to sense the data state of the memory cell, and (ii) control circuitry, coupled to the memory cell, to generate and apply read control signals to the electrically floating body transistor. In response to read control signals applied to the electrically floating body transistor, the electrically floating body transistor generates a bipolar transistor current which is representative of the data state of the memory cell and wherein the data sensing circuitry determines the data state of the memory cell substantially based on the bipolar transistor current. 
     The electrically floating body transistor of this aspect of the invention may be an N-channel type transistor or a P-channel type transistor. 
     The read control signals may include a signal applied to the gate, source region, and drain region to cause, force and/or induce the bipolar transistor current which is representative of the data state of the memory cell. In one embodiment, the read control signals include a positive voltage pulse which is applied to the drain region of the electrically floating body transistor. In another embodiment, the read control signals include a negative voltage pulse which is applied to the drain region of the electrically floating body transistor. 
     Again, there are many inventions, and aspects of the inventions, described and illustrated herein. This Summary of the Inventions is not exhaustive of the scope of the present inventions. Moreover, this Summary of the Inventions is not intended to be limiting of the inventions and should not be interpreted in that manner. While certain embodiments have been described and/or outlined in this Summary of the Inventions, it should be understood that the present inventions are not limited to such embodiments, description and/or outline, nor are the claims limited in such a manner. Indeed, many others embodiments, which may be different from and/or similar to, the embodiments presented in this Summary, will be apparent from the description, illustrations and claims, which follow. In addition, although various features, attributes and advantages have been described in this Summary of the Inventions and/or are apparent in light thereof, it should be understood that such features, attributes and advantages are not required whether in one, some or all of the embodiments of the present inventions and, indeed, need not be present in any of the embodiments of the present inventions. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the course of the detailed description to follow, reference will be made to the attached drawings. These drawings show different aspects of the present inventions and, where appropriate, reference numerals illustrating like structures, components, materials and/or elements in different figures are labeled similarly. It is understood that various combinations of the structures, components, materials and/or elements, other than those specifically shown, are contemplated and are within the scope of the present inventions. 
         FIG. 1A  is a schematic representation of a prior art semiconductor DRAM array including a plurality of memory cells comprised of one electrically floating body transistor; 
         FIG. 1B  is a three dimensional view of an exemplary prior art memory cell comprised of one electrically floating body transistor (PD-SOI NMOS); 
         FIG. 1C  is a cross-sectional view of the prior art memory cell of  FIG. 1B  cross-sectioned along line C-C′; 
         FIGS. 2A and 2B  are exemplary schematic illustrations of the charge relationship, for a given data state, of the floating body, source and drain regions of a prior art memory cell comprised of one electrically floating body transistor (PD-SOI NMOS); 
         FIG. 3  illustrates statistical variations in the currents read from an electrically floating body transistor; 
         FIG. 4A  is a schematic representation of an equivalent electrically floating body memory cell (N-channel type) including an intrinsic bipolar transistor in addition to the MOS transistor; 
         FIG. 4B  is a schematic representation of an equivalent electrically floating body memory cell (P-channel type) including an intrinsic bipolar transistor in addition to the MOS transistor; 
         FIGS. 5A and 5B  illustrate the statistical distributions for conventional reading technique versus bipolar reading; 
         FIG. 6  is an exemplary graphical illustration of selected control signals for writing State “1” and State “0” into a memory cell (having an electrically floating body transistor) wherein the memory cell state is read in accordance with the technique of the present invention; and 
         FIGS. 7A and 7B  are schematic block diagrams of embodiments of an integrated circuit device including, among other things, a memory cell array, data sense and write circuitry, memory cell selection and control circuitry, according certain aspects of the present inventions. 
     
    
    
     DETAILED DESCRIPTION 
     At the outset, it should be noted that there are many inventions described herein as well as many aspects and embodiments of those inventions. 
     In a first aspect, the present inventions are directed to a memory cell, having an electrically floating body transistor, and/or a technique of reading the data state in such a memory cell. In this regard, the present inventions employ the intrinsic bipolar transistor current to read and/or determine the data state of the electrically floating body memory cell (for example, whether the electrically floating body memory cell is programmed in a State “0” and State “1”). Here, during the read operation, the data state is determined primarily by, sensed substantially using and/or based substantially on the bipolar transistor current that is responsive to the read control signals and significantly less by the interface channel current component, which is negligible relatively to the bipolar component. 
     Notably, the bipolar transistor current may be very sensitive to the floating body potential due to the high gain of the intrinsic bipolar transistor. As such, the programming window obtainable with the bipolar reading technique may be considerably higher (for example, up two orders of magnitude higher) than the programming window employing a conventional reading technique (which is based primarily on the interface channel current component. The large programming window provides other opportunities/advantages, for example, simulations demonstrate that the bipolar reading may be accomplished significantly faster than conventional techniques (for example, in less than in 1 ns). 
     With reference to  FIG. 4A , in one embodiment, the present invention includes memory cell  12  having electrically floating body transistor  14 . In this exemplary embodiment, electrically floating body transistor  14  is an N-channel type transistor; as such, majority carriers are “holes”. The N-channel type transistor  14  equivalently includes an electrically floating body MOS transistor and an intrinsic bipolar transistor. In this regard, a N-type MOSFET includes an N +  source, the P-type body and the N +  drain wherein the N +  source, the P-type body and the N +  drain intrinsically form the emitter, the base, and the collector, respectively of an NPN bipolar transistor. 
     Notably, with reference to  FIG. 4B , the present inventions are fully applicable to a memory cell comprising a P-channel type electrically floating body transistor (here, the majority carriers are “electrons”). The P-channel type transistor also equivalently includes an electrically floating body MOS transistor and an intrinsic bipolar transistor. In this regard, a P-type MOSFET includes an P +  source, the N-type body and the P +  drain wherein the P +  source, the N-type body and the P +  drain intrinsically form the emitter, the base, and the collector, respectively of an PNP bipolar transistor. 
     In operation, during the read operation, suitable and predetermined control signals may be applied to gate  16 , source region  20 , and drain region  22  in order to cause, force and/or induce the bipolar transistor current in transistor  14  of memory cell  12 . For example, in one embodiment, 0 volts may be applied to source region  20  and gate  16  and a positive voltage (for example, +3.5 volts) may be applied to drain region  22 . Such control signals, in combination, induce and/or cause a bipolar transistor current which is considerably larger than any channel current. As such, sensing circuitry (for example, a cross-coupled sense amplifier), which is coupled to transistor  14  (for example, drain region  22 ) of memory cell  12 , senses the data state using primarily and/or based substantially on the bipolar transistor current. 
     Thus, in response to read control signals, electrically floating body transistor  14  generates a bipolar transistor current which is representative of the data state of memory cell  12 . Where the data state is a logic high or State “1”, electrically floating body transistor  14  provides a substantially greater bipolar transistor current than where the data state is a logic low or State “0”. Indeed, electrically floating body transistor  14  may provide little to no bipolar transistor current when the data state is a logic low or State “0”. As discussed in more detail below, data sensing circuitry determines the data state of the memory cell substantially based on the bipolar transistor current. 
     Where electrically floating body transistor  14  is an P-channel type transistor, in operation, during the read operation, in one embodiment, 0 volts may be applied to source region  20  and gate  16  and a negative voltage (for example, −4 volts) may be applied to drain region  22 . Such control signals, in combination, induce and/or cause a bipolar transistor current which is considerably larger than any channel current. Moreover, electrically floating body transistor  14  generates a bipolar transistor current which is representative of the data state of the memory cell. In this embodiment, where the data state is logic high or State “1”, electrically floating body transistor  14  provides a substantially greater bipolar transistor current than where the data state is a logic low or State “0”. Indeed, electrically floating body transistor  14  may provide little to no bipolar transistor current when the data state is a logic low or State “0”. The sensing circuitry (for example, a cross-coupled sense amplifier), which is coupled to transistor  14  (for example, drain region  22 ) of memory cell  12 , senses the data state using primarily and/or based substantially on the bipolar transistor current. 
     Notably, the exemplary voltage amplitudes to implement the read operation are merely exemplary. The indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.25, 0.5, 1.0 and 2.0 volts) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative. 
     With reference to  FIGS. 5A and 5B , by employing the bipolar current reading technique described herein, the operating and/or response characteristic(s) of memory cells  12  and the distributions of State “1” and State “0” are more uniform. This may provide higher confidence and greater reliability in correctly reading the data stored in memory cell  12 .  FIG. 6  is an exemplary graphical illustration of selected control signals, having exemplary values/characteristics, for reading State “1” and State “0” in memory cell  12  of  FIG. 4A . Although portions of this description include details directed to N-channel transistors, the inventions (and embodiments thereof) described herein are entirely applicable to P-channel transistors, as mentioned above. 
     In another aspect, the present inventions may be implemented an integrated circuit device (for example, a discrete memory device or a device having embedded memory) having a memory array including a plurality of memory cells each including an electrically floating body transistor. The memory arrays may be comprised of N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, data sense circuitry (for example, sense amplifiers or comparators), memory cell selection and control circuitry (for example, word line and/or source line drivers), as well as row and column address decoders) may include P-channel and/or N-channel type transistors. 
     For example, with reference to  FIGS. 7A and 7B , the integrated circuit device includes array  10 , having a plurality of memory cells  12 , data write and sense circuitry  34 , and memory cell selection and control circuitry  36 . The data write and sense circuitry  34  writes data into and senses the data state of one or more memory cells  12 . The memory cell selection and control circuitry  36  selects and/or enables one or more predetermined memory cells  12  to be read by data sense circuitry  34 . 
     The memory array  10  may be implemented using any number of architectures, layouts, and/or configurations employing electrically floating body memory cells  12 . In this regard, an electrically floating body transistor, which state is read using the techniques of the present invention, may be implemented in the memory cell, architecture, layout, structure and/or configuration described and illustrated in the following non-provisional and provisional U.S. patent applications: 
     (1) application Ser. No. 10/450,238, which was filed by Fazan et al. on Jun. 10, 2003 and entitled “Semiconductor Device”; 
     (2) application Ser. No. 10/487,157, which was filed by Fazan et al. on Feb. 18, 2004 and entitled “Semiconductor Device”; 
     (3) application Ser. No. 10/829,877, which was filed by Ferrant et al. on Apr. 22, 2004 and entitled “Semiconductor Memory Cell, Array, Architecture and Device, and Method of Operating Same”; 
     (4) application Ser. No. 10/840,009, which was filed by Ferrant et al. on May 6, 2004 and entitled “Semiconductor Memory Device and Method of Operating Same” 
     (5) application Ser. No. 10/941,692, which was filed by Fazan et al. on Sep. 15, 2004 and entitled “Low Power Programming Technique for a One Transistor SOI Memory Device &amp; Asymmetrical Electrically Floating Body Memory Device, and Method of Manufacturing Same”; and 
     (6) application Ser. No. 60/662,923, which was filed by Carman on Mar. 17, 2005 and entitled “Memory Device/Array Having Electrically Floating Body Memory Cells, and Method of Operating Same”. 
     The entire contents of these six (6) U.S. patent applications, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein. For the sake of brevity, those discussions will not be repeated; rather those discussions (text and illustrations), including the discussions relating to the memory cell, architecture, layout, structure, are incorporated by reference herein in its entirety. 
     Notably, the memory cells may be controlled (for example, programmed or read) using any of the control circuitry described and illustrated in the above-referenced six (6) U.S. patent applications. For the sake of brevity, those discussions will not be repeated; such control circuitry is incorporated herein by reference. Indeed, all memory cell selection and control circuitry for programming, reading, controlling and/or operating memory cells including electrically floating body transistors, whether now known or later developed, are intended to fall within the scope of the present invention. 
     For example, the present invention may also employ the read circuitry and techniques described and illustrated in U.S. patent application Ser. No. 10/840,902, which was filed by Portmann et al. on May 7, 2004, and entitled “Reference Current Generator, and Method of Programming, Adjusting and/or Operating Same”. 
     Moreover, the data write and sense circuitry  34  may include a sense amplifier (see,  FIG. 7B ) to read the data stored in memory cells  12 . The sense amplifier (for example, a cross-coupled sense amplifier as described and illustrated in the Non-Provisional U.S. Patent Application filed by Waller and Carman, on Dec. 12, 2005 and entitled “Sense Amplifier Circuitry and Architecture to Write Data into and/or Read from Memory Cells”, the application being incorporated herein by reference in its entirety) may sense the data state stored in memory cell  12  using voltage or current sensing circuitry and/or techniques. In the context of a current sense amplifier, the current sense amplifier may compare the cell current to a reference current, for example, the current of a reference cell (see, generally,  FIG. 7B ). From that comparison, it may be determined whether memory cell  12  contained a logic high (relatively more majority carries  34  contained within body region  18 ) or logic low data state (relatively less majority carries  28  contained within body region  18 ). Such circuitry and configurations thereof are well known in the art. 
     In addition, the present invention may employ the reference generation techniques (used in conjunction with the data sense circuitry for the read operation) described and illustrated in U.S. Provisional Patent Application Ser. No. 60/718,417, which was filed by Bauser on Sep. 19, 2005, and entitled “Method and Circuitry to Generate a Reference Current for Reading a Memory Cell Having an Electrically Floating Body Transistor, and Device Implementing Same”. The entire contents of the U.S. Provisional Patent Application Ser. No. 60/718,417 are incorporated herein by reference. 
     It should be further noted that while each memory cell  12  in the exemplary embodiments (described above) includes one transistor  14 , memory cell  12  may include two transistors, as described and illustrated in application Ser. No. 10/829,877, which was filed by Ferrant et al. on Apr. 22, 2004 and entitled “Semiconductor Memory Cell, Array, Architecture and Device, and Method of Operating Same”. 
     The electrically floating memory cells, transistors and/or memory array(s) may be fabricated using well known techniques and/or materials. Indeed, any fabrication technique and/or material, whether now known or later developed, may be employed to fabricate the electrically floating memory cells, transistors and/or memory array(s). For example, the present invention may employ silicon (whether bulk-type or SOI), germanium, silicon/germanium, gallium arsenide or any other semiconductor material in which transistors may be formed. Indeed, the electrically floating transistors, memory cells, and/or memory array(s) may employ the techniques described and illustrated in non-provisional patent application entitled “Integrated Circuit Device, and Method of Fabricating Same”, which was filed on Jul. 2, 2004, by Fazan, Ser. No. 10/884,481, provisional patent application entitled “One Transistor Memory Cell having Mechanically Strained Electrically Floating Body Region, and Method of Operating Same”, which was filed on Oct. 19, 2005, Ser. No. 60/728,060, by Bassin, and/or provisional patent application entitled “Memory Cell, Array and Device, and Method of Operating Same”, which was filed on Oct. 19, 2005, Ser. No. 60/728,061, by Okhonin et al. (hereinafter collectively “Integrated Circuit Device Patent Applications”). The entire contents of the Integrated Circuit Device Patent Applications, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein. 
     Indeed, memory array  10  (including SOI memory transistors) may be integrated with SOI logic transistors, as described and illustrated in the Integrated Circuit Device Patent Applications. For example, in one embodiment, an integrated circuit device includes memory section (having, for example, PD or FD SOI memory transistors  14 ) and logic section (having, for example, high performance transistors, such as FinFET, multiple gate transistors, and/or non-high performance transistors (for example, single gate transistors that do not possess the performance characteristics of high performance transistors—not illustrated)). Again, the entire contents of the Integrated Circuit Device Patent Applications, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference. 
     Further, the memory arrays may be comprised of N-channel, P-channel and/or both types of transistors, as well as partially depleted and/or fully depleted type transistors. For example, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include fully depleted type transistors (whether P-channel and/or N-channel type). Alternatively, such circuitry may include partially depleted type transistors (whether P-channel and/or N-channel type). There are many techniques to integrate both partially depleted and/or fully depleted type transistors on the same substrate (see, for example, application Ser. No. 10/487,157, which was filed by Fazan et al. on Feb. 18, 2004 and entitled “Semiconductor Device”). All such techniques, whether now known or later developed, are intended to fall within the scope of the present inventions. 
     Notably, electrically floating body transistor  14  may be a symmetrical or non-symmetrical device. Where transistor  14  is symmetrical, the source and drain regions are essentially interchangeable. However, where transistor  14  is a non-symmetrical device, the source or drain regions of transistor  14  have different electrical, physical, doping concentration and/or doping profile characteristics. As such, the source or drain regions of a non-symmetrical device are typically not interchangeable. This notwithstanding, the drain region of the electrically floating N-channel transistor of the memory cell (whether the source and drain regions are interchangeable or not) is that region of the transistor that is connected to the bit line/sense amplifier. 
     As mentioned above, the memory arrays may be comprised of N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include P-channel and/or N-channel type transistors. Where P-channel type transistors are employed as memory cells  12  in the memory array(s), suitable write and read voltages (for example, negative voltages) are well known to those skilled in the art in light of this disclosure. Accordingly, for sake of brevity, these discussions will not be repeated. 
     There are many inventions described and illustrated herein. While certain embodiments, features, attributes and advantages of the inventions have been described and illustrated, it should be understood that many others, as well as different and/or similar embodiments, features, attributes and advantages of the present inventions, are apparent from the description and illustrations. As such, the embodiments, features, attributes and advantages of the inventions described and illustrated herein are not exhaustive and it should be understood that such other, similar, as well as different, embodiments, features, attributes and advantages of the present inventions are within the scope of the present inventions. 
     For example, as mentioned above, the illustrated/exemplary voltage levels to implement the read and write operations are merely exemplary. The indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.1, 0.15, 0.25, 0.5, 1 volt) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative. 
     Notably, the present inventions may employ the circuitry and techniques for independently controlling certain parameters (for example, temporal or voltage), for a memory operation (for example, restore, write, refresh), to program or write a predetermined data state into a memory cell (for example, programming or writing data state “1” or “0” into a memory cell) as described and illustrated in U.S. Provisional Patent Application Ser. No. 60/731,668, which was filed by Popoff on Oct. 31, 2005, and entitled “Method and Apparatus for Varying the Programming Duration of a Floating Body Transistor, and Memory Cell, Array, and/or Device Implementing Same”. For example, the duration of programming/writing of a given memory state into a memory cell by the data sense amplifier circuitry may be controlled adjusted, determined and/or predetermined according to or based on the given memory operation (for example, restore, write, refresh). Likewise, the voltage conditions applied to the memory cell for programming/writing a given memory state into a memory cell by the data sense amplifier circuitry may be controlled and/or adjusted according to the memory operation (for example, restore, write, refresh). The entire contents of U.S. Provisional Patent Application Ser. No. 60/731,668, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein. 
     As mentioned above, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of such aspects and/or embodiments. For the sake of brevity, those permutations and combinations will not be discussed separately herein. As such, the present inventions are neither limited to any single aspect (nor embodiment thereof), nor to any combinations and/or permutations of such aspects and/or embodiments. 
     Moreover, the above embodiments of the present inventions are merely exemplary embodiments. They are not intended to be exhaustive or to limit the inventions to the precise forms, techniques, materials and/or configurations disclosed. Many modifications and variations are possible in light of the above teaching. It is to be understood that other embodiments may be utilized and operational changes may be made without departing from the scope of the present inventions. As such, the foregoing description of the exemplary embodiments of the inventions has been presented for the purposes of illustration and description. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the inventions not be limited solely to the description above.