Abstract:
Disclosed is a redundancy efficiency increasing circuit of semiconductor memory device. The circuit comprises 2N banks each having 2M redundancy lines; 2N redundancy control blocks; and an address signal switch unit for receiving first and second control signals, and an address signal. If the first signal is enabled, a bank address signal selecting (2n−1)th bank is provided to redundancy control blocks corresponding to (2n−1)th bank and (2n)th bank. If the second signal is enabled, a bank address signal selecting (2n)th bank is provided to the redundancy control blocks corresponding to (2n−1)th bank and (2n)th bank. If the first and second signals are enabled, a bank address signal selecting (2n−1)th bank is provided to the redundancy control block corresponding to (2n−1)th bank, and a bank address signal selecting (2n)th bank is provided to the redundancy control block corresponding to (2n)th bank.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a redundancy efficiency increasing circuit of semiconductor memory device and, more particularly, to a redundancy efficiency increasing circuit of semiconductor memory device which can increase efficiency of redundancy twice by using unused fuse having a block fail when a block fail is generated, thereby only a half of chip is used.  
           [0003]    2. Description of the Related Art  
           [0004]    [0004]FIG. 1 is a drawing showing the structure of column redundancy in a conventional semiconductor memory device. As shown in FIG. 1, bank i and bank k include 4 blocks  10 , respectively. The banks have two column redundancy lines RYS 0 , RYS 1  therein, respectively. When a column fail is generated less than two in one block, the column redundancy line RYS 0 , RYS 1  can be substituted and the same operation is performed in other block of the same bank. That is, only two column fails can be improved in one bank.  
           [0005]    And, Y fuse  20  is provided by each bank in a peripheral circuit to improve the column fail. In a redundancy control block  30  including the Y fuse  20 , AY&lt;0:m&gt; for comparing Y address, BAi for bank coding and BXi&lt;0:n&gt;, X block coding for substitution by X blocks, are inputted, thereby improving two column fails in one bank. However, when a block fail is generated in bank k and it is impossible to solve the fail, only bank i is commonly used. In this case, it is also difficult to improve two or more fails in one bank. That is, Y fuse of bank k cannot be used.  
         SUMMARY OF THE INVENTION  
         [0006]    Therefore, the present invention has been made to solve the above-mentioned problems and a primary objective of the present invention is to provide a redundancy efficiency increasing circuit of semiconductor memory device which can increase efficiency of redundancy by using unused fuse in a redundancy of another bank when a block fail is generated in one bank and it is impossible to improve the fail.  
           [0007]    In order to accomplish the above object, the present invention comprises 2 N banks having 2M redundancy lines-(2n−1)th bank and (2n)th bank have a corresponding relation, and n is a natural number in the range of 1 to N− and a fuse circuit, including: 2N redundancy control blocks for enabling redundancy lines of corresponding bank in the banks according to received address signal; and an address signal switch unit for receiving a first control signal, a second control signal and an address signal to provide a bank address signal selecting (2n−1)th bank to corresponding redundancy control block of (2n−1)th bank and (2n)th bank when only the first control signal is enabled, provide a bank address signal selecting (2n)th bank to corresponding redundancy control block of (2n−1)th bank and (2n)th bank when only the second control signal is enabled and provide a bank address signal selecting (2n−1)th bank to corresponding redundancy control block of (2n−1)th bank an a bank address signal selecting (2n)th bank to corresponding redundancy control block of (2n)th bank when both the first control signal and the second control signal are enabled.  
           [0008]    In the 2M redundancy lines, M redundancy lines are operated to improve fails of the bank and another M redundancy lines are operated to improve fails of the corresponding bank. The first control signal and the second control signal are generated by bonding option. The redundancy line is a column redundancy line.  
           [0009]    The redundancy efficiency increasing circuit of semiconductor memory device according to the present invention can increase redundancy efficiency twice by using a first to a third multiplexers to use the fuse of bank having the block fail when a block fail is generated and it is impossible to improve. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    [0010]FIG. 1 is a drawing showing the arrangement of column redundancy according to a conventional semiconductor memory device.  
         [0011]    [0011]FIG. 2 is a block diagram of redundancy efficiency increasing circuit of semiconductor memory device according to an embodiment of the present invention.  
         [0012]    [0012]FIG. 3 is a circuit diagram of a first multiplexer in FIG. 2.  
         [0013]    [0013]FIG. 4 is a circuit diagram of a second multiplexer in FIG. 2.  
         [0014]    [0014]FIG. 5 is a circuit diagram of a third multiplexer in FIG. 2. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0015]    The above objects, and other features and advantages of the present invention will become more apparent after reading the following detailed description when taken in conjunction with the drawings.  
         [0016]    [0016]FIG. 2 is a block diagram of semiconductor memory device according to an embodiment of the present invention, showing a column redundancy to improve column fails in a semiconductor memory device comprising 4 banks of i bank, j bank, k bank, and l bank. Referring to FIG. 2, the present semiconductor memory device  2000  comprises banks  210 , 2210 , 230 , 240  and address signal switch unit  250 . The address signal switch unit  250  comprises a first multiplexer  200 , a second multiplexer  300  and a third multiplexr  400 .  
         [0017]    The bank have 4 blocks  100  and 4 column redundancy lines RYS 0 , RYS 1 , RYS 2 , RYS 3  therein, respectively wherein two lines RYS 0 , RYS 1  are column redundancy lines when the bank is normally operated and another two lines RYS 2 , RYS 3  are obtained by using column redundancy lines of bank having fails when a fail is generated in one pair of banks i,j and k,l and it is impossible to improve. In the present invention, the one pair of banks relate to input/output structure, wherein banks i, j and banks k,l are operated by one pair and bank i corresponds to bank k and bank j corresponds to bank l.  
         [0018]    The column redundancy lines are arranged by multiplexers. That is, a first multiplexer  200 , a second multiplexer  300  and a third multiplexer  400  are arranged on the peripheral circuit of each bank and Y fuse  500  is arranged by banks to improve column fails. In bank i, AY&lt;0:m&gt; for comparing Y address, BAi for bank coding and Bxi&lt;0:n&gt; signal, X block coding, for substitution by X blocks are inputted to a redundancy control block  600  including Y fuse  500 , thereby generating a column redundancy select signals RYSi 0 , RYSi 1 .  
         [0019]    The first multiplexer  200  is employed as a switch of bank coding wherein bank coding signals BAi, BAk and X block coding signals BXi&lt;0:n&gt;, BXk&lt;0:n&gt; are inputted with BONDij and BONDkl through bonding option, thereby outputting BAi and BXi&lt;0:n&gt; signals to bank i and BAk and BXk&lt;0:n&gt; signals to bank k, respectively on the redundancy control block  600 .  
         [0020]    When a fail is generated in bank i or bank j and it is impossible to improve, BONDij signal generates ‘low’ level and BONDkl signal generates ‘high’ level by bonding option. It is determined by whether to connect the BONDING PAD to Vss in a circuit for generating BONDij and BONDkl signals having a BONDING PAD connected thereto.  
         [0021]    And, when a fail is generated in bank k or bnak l and it is impossible to improve, BONDij generates ‘high’ level and BOND kl generates ‘low’ level.  
         [0022]    The second multiplexer  300  is for input of the BOND ij signal and RYSi 0  or RYSi 1 , a column redundancy select signal of bank I, and the third multiplexer  400  is for input of the BOND kl signal and RYSk 0  or RYSk 1 , a column redundancy select signal of bank k. When a ‘high’ level is inputted to BOND ij and a ‘low’ level is inputted to BOND kl in a column redundancy line of bank i, RYSi 0  and RYSi 1  signals are loaded on redundancy lines of the RYS 0  and RYS 1  by the second multiplexer  300  and RYSk 0  and RYSk 1  signals are loaded on redundancy lines of the RYS 2  and RYS  3  by the third multiplexer  400 .  
         [0023]    When only BOND kl is inputted in a ‘high’ level in a column redundancy line of bank k, RYSk 0  and RYSk 1  signals are loaded on redundancy lines of the RYS 0  and RYS 1  by the third multiplexer  400  and RYSi 0  and RYSi 1  signals are loaded on redundancy lines of RYSi 0  and RYSi 1  by the second multiplexer  300 .  
         [0024]    And, on a peripheral circuit area, Y fuse  500  is arranged by banks to improve the column fail. For example of bank i, AY&lt;0:m&gt; for comparing Y address, BAi for bank coding and BXi&lt;0:n&gt;, X block coding, for substitution by X blocks are inputted to redundancy control block  600  including Y fuse  500 , thereby generating the column redundancy select signals RYSi 0 , RYSi 1 .  
         [0025]    [0025]FIG. 3 is a circuit diagram of the first multiplexer  200  in FIG. 2. As shown in the drawing, the first multiplexer  200  comprises an inverter INV, and a first, a second and a third NAND gates N 1 , N 2 , N 3 , including 1 to 4 groups having the same structure. The first multiplexer  200  comprises: a first NAND gate N 1  for receiving a first and a second signals; an inverter INV for inverting the first signal; a second NAND Gate for receiving a signal inverted by the inverter and a third signal; and a third NAND gate N 3  for receiving output signals of the first NAND gate N 1  and the second NAND gate N 2  and outputting a fourth signal.  
         [0026]    In the first group  210 , a first signal is BONDij signal, a second signal is BAi signal, a third signal is BAk signal and a fourth signal is BAi signal inputted to redundancy control block  600 . In the second group  220 , a first signal is BONDij signal, a second signal is BXi&lt;0:n&gt; signal, a third signal is BXk&lt;0:n&gt; signal and a fourth signal is BXi&lt;0:n&gt; signal inputted to redundancy control block  600 . In the third group  230 , a first signal is BONDkl signal, a second signal BAk signal, a third signal is BAi signal and a fourth signal is BAk signal inputted to redundancy control block  600 . In the fourth group  240 , a first signal is BONDkl signal, a second signal is BXk&lt;0:n&gt; signal, a third signal is BXi&lt;0:n&gt; signal and a fourth signal is BXk&lt;0:n&gt; signal inputted to redundancy control block  600 .  
         [0027]    When a fail is generated in bank k or bank l and it is impossible to improve, BONDij signal becomes ‘high’ level and BONDkl signal becomes ‘low’ level. Then, the second signal, BAi is loaded on BAi signal inputted to redundancy control block  600  of the first group  210  regardless of the third signal BAk and BAi is also loaded on BAk signal, a fourth signal of the third group  230  regardless of BAk. Therefore, coding of bank i is inputted to redundancy control block  600  of bank k, thereby it is possible to be controlled by bank i.  
         [0028]    In the same way, BXi&lt;0:n&gt; signal is loaded on BXi&lt;0:n&gt;, X row block coding, by the second group  220  and the fourth group  240 and BXi&lt;0:n&gt; signal is loaded on BXk&lt;0:n&gt;, regardless of BXk&lt;0:n&gt; signal. Therefore, coding of bank i is inputted to redundancy control block.  
         [0029]    [0029]FIGS. 4 and 5 are circuit diagrams of the second multiplexer  300  and the third multiplexer  400 . As shown in the drawing, the second multiplexer  300  and the third multiplexer  400  comprises one inverter INV and a first and a second transmission gates  310 , 320 , respectively including a fifth, a sixth, a seventh and a eighth groups  350 , 370 ,  450 ,  470  having the same structure.  
         [0030]    The fifth group  350  receives BONDij signal and column redundancy select signal RYSi 0 , output signal of redundancy control block  600  including Y fuse  500 , comprising: an inverter INV for inverting BONDij signal; a first transmission gate  310  for receiving the BONDij signal and inverted signal from the inverter INV and transmitting the RYSi 0  signal to column redundancy line RYS 0  of bank i; and a second transmission gate  320  for receiving the BONDij signal and inverted signal from the inverter INF and transmitting the RYSi 0  signal to column redundancy line RYS 2  of bank k.  
         [0031]    The sixth group  370  receives BONDij signal and column redundancy select signal RYSi 1 , output signal of redundancy control block  600  including Y fuse  500 , comprising: an inverter INV for inverting BONDij signal; a first transmission gate  310  for receiving the BONDij signal and inverted signal from the inverter and transmitting the RYSi 1  signal to column redundancy line RYS 1  of bank i; and a second transmission gate  320  for receiving the BONDij signal and inverted signal from the inverter INV and transmitting the RYSi 1  signal to column redundancy line RYS 3  of bank k.  
         [0032]    Referring to FIG. 5, the seventh group  450  of the third multiplexer  400  receives BONDkl signal and column redundancy select signal RYSk 0 , output signal of redundancy control block  600  including Y fuse  500 , comprising: an inverter for inverting BONDkl signal; a first transmission gate  410  for receiving the BONDkl signal and inverted signal from the inverter INV and transmitting the RYSk 0  signal to column redundancy line RYS 0  of bank k; and a second transmission gate  420  for receiving the BONDkl signal and inverted signal from the inverter INV and transmitting the RYSk 1  signal to column redundancy line RYS 3  of bank i.  
         [0033]    When all the banks are normally operated, BONDij and BONDkl signals are enabled to ‘high’ level. Therefore, RYSi 0  signal, column redundancy select signal in the second multiplexer  300 , is loaded on column redundancy line RYS 0  of bank i and RYSi 1  signal is also loaded on column redundancy line RYS 1  of bank i. Similarly, RYSk 0  signal, column redundancy select signal in the third multiplexer  400 , is loaded on column redundnay line RYS 0  of bank k and RYSk 1  signal is loaded on column redundancy line RYS 1  of bank k.  
         [0034]    When a plurality of fails are generated in bank i or bank j and then, BONDij signal becomes ‘low’ level, the RYSi 0  signal is loaded on column redundancy line RYS 2  of bank k in the second multiplexer  300  and the RYSi 1  signal is loaded on column redundancy line RYS 3  of bank k. As a result, two column redundancy lines are added to bank k.  
         [0035]    And, when a plurality of fails are generated in bank k or bank l and then, BONDkl signal becomes ‘low’ level, the RYSk 0  signal is loaded on column redundancy line RYS 2  of bank i in the third multiplexer  400  and the RYSk 1  signal is loaded on column redundancy line RYS 3  of bank i. As a result, two column redundancy lines are added to bank i. That is, the number of total column redundancy lines becomes 4, RYS 0 , RYS 1 , RYS 2 , RYS 3 , thereby it is possible to improve 4 column fails at maximum in a block  100 . As a result, the present invention can improve the yield of wafer since it is possible to improve device having 3 or 4 column fails.  
         [0036]    According to the above-mentioned embodiment, one pair of banks can use 4 redundancy lines by using 2 redundancy lines in a normal operation. However, it is also possible to use 2n redundancy lines by using n redundancy lines in each bank. And, the present invention can also be applied to row redundancy line to improve the yield of wafer by using device having row fails.  
         [0037]    Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.