Abstract:
A selector switch monolithically integrated to a CMOS technology circuit for electrically programmable memory cell devices having at least first and second input terminals for coupling to first and second voltage generators (HV and LV), respectively, and an output terminal. First and second field-effect selection transistors are respectively connected, via first and second terminals, between the first input terminal and the output terminal and between the second input terminal and the output terminal. These transistors are driven through control terminals at non-overlapping phases and have body terminals connected at a body circuit node which is coupled to the first and second voltage generators through a bias circuit block effective to bias the node to the higher of the instant voltages generated by the first and second generators.

Description:
TECHNICAL FIELD 
     This invention relates to high and low voltage selection circuits for non-volatile memories, and in particular to a high-speed selector switch integrated monolithically to a CMOS technology circuit. 
     BACKGROUND OF THE INVENTION 
     There is a growing demand for integrated circuits to be provided with different voltages for internal distribution according to which of their operative phases are to be activated. For example, semiconductor non-volatile storage devices (such as Flash, EPROM, E 2 PROM memories), require different internal voltages for wordline biasing at different phases of the device operation. For a NORed memory, for instance, a reading operation involves biasing the wordline of the addressed cell to a voltage equal to the supply voltage (V dd =3V or 5V), whereas that same wordline is to be applied suitably higher voltages (e.g., V pp =12V) during the programming phase; V dd  being a voltage supplied from outside the device, and V pp  either a voltage supplied from outside or produced inside from V dd . Furthermore, for multilevel EPROM storage devices, the wordline bias voltage during the read phase is a higher value than the supply voltage V dd  (being usually of 3V or 5V). In fact, for a larger number of levels than two to be reliably allocated, the range of possible cell currents must be stretched to values of 100 to 120 μA. Such current values can only be obtained, however, by using gate voltages in the 5V to 6V range. In addition, during specific operative phases (such as those activated for testing), the wordline of the selected cell is to be brought to an analog voltage ranging from 0 to V pp  for DMA (Direct Memory Access) reading, as those skilled in the art will recognize. 
     Accordingly, integrated circuits that are to operate in this way must be provided internally with a selector switch, to each time pick up and distribute an appropriate voltage to the working blocks, under control by suitable control signals. 
     A prior art electrically programmable non-volatile memory cell device  2  is shown in FIG.  1 . The memory cell device  2  includes a selector switch  4 , a row decoder  6 , and a set of final decoding stages  8  for biasing respective word lines of a memory cell matrix (not shown) as needed for the differential operational phases of the memory cell device, such as reading, programming, and DMA reading. 
     Specifically with a non-volatile memory, there are essentially two voltages (referenced LV and HV hereinafter) involved, and the selector switch  4  is mainly concerned with biasing the wordlines. In this case, the selector switch will switch the power supply to the final decoding stages  8 , as shown in FIG. 1, between the low voltage LV and the high voltage HV, according to whether the addressed cell is to be read or programmed, respectively. 
     It can be appreciated that, if positive voltages are to be output to the selector switch with no voltage drops, the use of p-channel pass transistors becomes mandatory. In the instance of n-well CMOS technology, the use of p-channel transistors within the selector switch creates quite a few problems because the source and drain regions of the transistors must be reverse biased, relative to the wells wherein the p-channel transistors are formed, all the time. Thus, the well regions would have to be connected to that terminal of their associated transistor which is at the highest voltage value. 
     However, as described in further detail hereinafter, it often is impossible to identify the highest voltage terminal of the p-channel transistors which make up the selector switch, because of its dependence on the specific operative phase being activated. A first simple circuit diagram of the selector switch is shown in FIG.  2  and includes just two p-channel transistors (P 1  and P 2 ) which are driven by a control signal PH for turning on either transistor to the exclusion of the other. 
     It is readily seen, however, that this simple approach rules out the possibility of using HV&lt;LV, since there would occur forward biasing between the well region of P 1  and the drain region of this transistor. 
     This is an important limitation placed on non-volatile storage devices, because proper operation of the selector switch cannot be assured in such modes as DMA testing and reading. In fact, the operation specifications usually provide for the user&#39;s ability to set up at will the value of HV during the read phases, with the single stipulation that it should not exceed the value of the supply voltage V dd . In addition, considerations of constructional simplicity point to the advisability of having the DMA mode implemented through the HV terminal for accessing the node OUT of the selector switch directly. During such operations, the applied voltages may take values in the range of 0V to 12V. 
     Thus, the value of HV can drop below that of LV in both the DMA testing and the reading modes, and this prior approach tends to be used in a less degree. 
     On the other hand, the problem can be solved by using more complicated schemes, with 3 or 4 transistors and a peculiar interconnection of the wells, like that shown schematically in FIG. 3 for a three-transistor construction. 
     But these prior approaches, when applied to commercial devices of the EPROM type, are ill-suited for use in applications where the switching rate of the selector switch (and hence of the voltage at the node OUT) is a parameter of major consideration. In fact, the use of such circuit constructions brings about a problem of transient control of the common node N of the transistors P 1  and P 3 . This node evolves, because of the great difference in capacitive load between it and the output terminal OUT (up to approximately 800 pF in a 4096-row memory), toward the voltage HV, upon switching the output node OUT from LV to HV (P 1  and P 3  being both turned on), at a definitely higher rate than the output node, so that the n-p junction formed of the N region and the well of P 3  becomes forward biased. 
     Unfortunately, the circuit setups currently investigated to limit this bias effect invariably result in the LV/HV switching time at the output node being increased. The significance of this problem can be appreciated by considering that the program algorithm for a non-volatile memory cell (also referred to as the program-and-verify algorithm) involves the application, to the selected wordline, of a large number of high-voltage pulses, regularly interspersed with an equal number of low-voltage pulses, during which the programmed state of the cell is verified. 
     On the other hand, during each HV-to-LV switch of the node OUT (P 1  and P 3  being turned off, P 2  being turned on), the problem arises that the two transistors P 1 , P 3  cannot be turned off simultaneously. In fact, the value of HV would then remain “stored” dynamically in the intermediate node N, while the output node goes quickly to LV; here again, the n-p junction between the N region and the well of P 3  becomes forward biased. 
     Therefore, during the HV-to-LV switching transient of the node OUT, P 1  should be turned off first (in order to isolate the node N from HV), and P 3  only turned off after a while (i.e., once the voltage at OUT has attained the value of LV). In this way, N and OUT are “equalized” during the transient through the transistor P 3 , still on. 
     Accordingly, the phase edges of the control signals PH and PH′ must have an interval (on the order of a few μs) of non-overlap, thereby introducing unavoidable delay in the overall switching time. 
     Thus, the prior solutions do not suit applications which require very fast (e.g., on the order of 100-200 ns) switching of the node OUT between the voltages HV and LV. 
     SUMMARY OF THE INVENTION 
     An embodiment of this invention provides a monolithically integrated selector switch for devices comprising electrically programmable memory cells, which can combine versatility of application with circuit simplicity and operability. The switch is effective to each time find out the highest voltage present within the circuit and bias the well regions thereto. 
     The features and advantages of a voltage-selecting switch according to the invention can be better understood by reading the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a circuit architecture for storage devices, including a voltage selecting switch for final decoding stages. 
     FIGS. 2 and 3 show circuit diagrams of conventional voltage-selecting switches suitable for implementation with CMOS technology. 
     FIG. 4 shows a main diagram of a voltage-selecting switch according to an embodiment of the invention suitable for implementation in multilevel storage devices. 
     FIG. 5 is a circuit diagram, partially in block form, of a bias circuit block employed in the voltage-selecting switch of FIG.  4 . 
     FIG. 6 is a circuit diagram of an input circuit block employed in the bias circuit block of FIG.  5 . 
    
    
     DETAILED DESCRIPTION 
     A voltage selecting switch according to an embodiment of the invention combines the construction and operation simplicity of the two-transistor selector switch with the versatility afforded by multi-transistor structures. In fact, having solved the problem of proper well biasing, a structure including but two transistors creates no problems of intermediate node control, as no such nodes exist therein, and is highly advantageous in terms of switching speed of the selector switch. 
     As shown in FIG. 4, a selector switch  10  according to the invention comprises two transistors P 1  and P 2  which are used as pass transistors (and form the HV/LV selector switch proper), and a Well Biasing Circuit (WBC)  12  capable of maintaining the transistor wells (connected together at the node BODY) biased to the higher of the two instant voltages HV and LV. Such a selector switch  10  is intended to replace the selector switch  4  of the prior art memory cell device  2  shown in FIG.  1 . 
     The transistors P 1 , P 2  are made to conduct at non-overlapping phases by control signals PH and /PH. 
     The selector switch  10  can be employed in two- or multi-level EPROM storage devices. 
     The tables herein below show possible voltage values in different modes of operation: 
     
       
         
               
             
               
               
               
               
             
           
               
                   
               
               
                 MULTI-LEVEL DEVICE 
               
             
          
           
               
                   
                 Mode 
                 LV 
                 HV 
               
               
                   
                   
               
               
                   
                 Read Mode 
                 5.5 V 
                 0 to V dd  = 3 V 
               
               
                   
                 Program Mode 
                 5.5 V 
                 6 to 12 V 
               
               
                   
                 DMA Mode 
                 5.5 V 
                 0 to 12 V 
               
               
                   
                   
               
             
          
         
       
     
     
       
         
               
             
               
               
               
               
             
           
               
                   
               
               
                 TWO-LEVEL DEVICE 
               
             
          
           
               
                   
                 Mode 
                 LV 
                 HV 
               
               
                   
                   
               
               
                   
                 Read Mode 
                 V dd  = 3 V 
                 0 to V dd  = 3 V 
               
               
                   
                 Program Mode 
                 V dd  = 3 V 
                 12 
               
               
                   
                 DMA Mode 
                 V dd  = 3 V 
                 0 to 12 
               
               
                   
                   
               
             
          
         
       
     
     The implementation of the proposed solution for multilevel applications involves, in the program mode, biasing the wells to a systematically varying voltage. 
     To ensure proper turn-on and turn-off of the transistors P 1  and P 2  at each operation phase, the generator of the PH and negated PH phases must be supplied each time with the higher of voltages HV and LV and must, therefore, be powered through the node BODY. 
     Actually, an optimum solution would be that of each time sensing a voltage HV″, which is the program voltage and provides HV. 
     The value of the voltage HV″ varies with the mode of operation. In the program mode, it may be V pp =12V, and in the read mode (which is made available to the user of the device), it may lie somewhere between 0V and V dd . 
     Thus, the transistor P 1  can be connected to the line of the voltage HV, while the WBC block  12  is coupled directly to the high-voltage terminal HV″ (whereto P 1  is actually also connected indirectly). In two-level applications, HV and HV″ would obviously be the same. 
     In the embodiment of the invention shown in FIG. 5, the bias circuit block  12  includes a comparator (COMP)  14  having a non-inverting (+) input terminal, an inverting (−) input terminal, and an output terminal. The inverting input terminal is coupled to the voltage LV. 
     Third P 3  and fourth P 4  field-effect transistors have respective control terminals connected to the comparator output terminal, with the control terminal of the third transistor P 3  being so connected through an inverter circuit (INV)  16 . 
     The bias circuit block further includes an input circuit block (IN_COMP)  18  having an output node V +  whereby the non-inverting input terminal of the comparator is coupled to the first voltage generator HV″. The input circuit block  18  also is connected to a supply terminal V alcomp  of the comparator  14 . 
     The third P 3  and fourth P 4  transistors are series connected together between said input circuit block  18  and the second voltage LV. These transistors are connected together at the body circuit node BODY. 
     As shown in FIG. 6, the input circuit block  18  comprises fifth P 5  and sixth P 6  field-effect transistors of the complementary type which are connected, in series with each other between a power supply line V dd  and a ground GND of the memory circuit to which the selector switch  10  is integrated. The fifth and sixth field-effect transistors P 5 , P 6  have respective control terminals connected to a linking circuit node  20  between the fifth transistor P 5  and the sixth transistor P 6 . 
     Seventh P 7  and eighth P 8  field-effect transistors of the complementary type are connected, in series with each other between the voltage generator HV″ and the ground GND. They have respective control terminals connected to the linking circuit node  20 , and are connected in series with each other at a circuit node which forms the output node V +  of the input circuit block. 
     This output node V +  of the input circuit block  18  is connected directly to the non-inverting (+) terminal of the comparator  14 , and via a voltage step-up circuit (ELEVATOR)  22 , to the supply terminal V alcomp  of the comparator. The construction of the voltage step-up circuit  22  is well within the capabilities of those skilled in the art. 
     A resistive element R 10  is connected between the first voltage HV″ and the third transistor P 3  at a node HV loc . 
     By means of the input circuit block  18  being connected to its non-inverting input terminal, the comparator  14  can output a logic zero in the presence of a voltage HV″≦V dd  (as in the read mode), or otherwise, a value same as HV″ (as in the program mode). 
     This solution ensures that the comparator  14  will be turned off (with attendant advantages in terms of power consumption), since it forces the supply to the comparator to be canceled at all the phases (read and test modes) where its operation is unnecessary. In fact, the voltage for well biasing is always LV, and the selection of this voltage is ensured by the logic zero value presented at the output by the turned off comparator  14 . 
     The time when HV″ reaches and exceeds the value of LV (at which time the well biasing circuit  12  should theoretically turn off the transistor P 5  and turn on P 4  in order to connect the well node BODY to the rising one of the voltages) should be preceded by activation of the comparator to enter the program mode operation. In fact, any delay in sensing this transition would result in the wells being forward biased, relative to the source diffusions connected to HV″, and the more so the higher the rate of change of the voltage HV″. 
     The well biasing circuit  12  unavoidably introduces a delay in input-to-output propagation, and accordingly, the activation of the comparator  14  is to take place substantially in advance of the crossing time of HV″ with respect to LV. This is provided by the input block  18  to the comparator  14  outputting a voltage equal to HV″ as soon as HV″ overtakes V dd  (that is, while it is still below the value of LV if V dd =3V or 5V). 
     While from a logic standpoint, the supply terminal (V alcomp ) of the comparator, the non-inverting input of the comparator (V + ), and the high voltage for well biasing (HV loc ) should be one signal during the transition to the program mode, from a physical standpoint it is advisable to have the three voltages clearly separated, as shown in FIG.  6 . 
     The input block  18  has three outputs, each dedicated to generating a different signal: one output will relate to the comparator input signal (V + ), another to the comparator supply (V alcomp ), and the third to the local HV signal (HV loc ) used to bias the wells. 
     In this way, during the initial phase of the transition from the read mode to the program mode (i.e., when HV″ begins to rise but is yet to reach LV), the three signals will be coincident, but become different upon HV″ crossing LV. In particular, the non-inverting input V +  of the comparator will keep evolving toward the steady-state value of 12V (following HV″), without undergoing any delay within the range of LV (with substantial advantages in terms of unbalance of the comparator inputs, and hence of comparator switching speed). On the contrary, the local HV loc  will be slowed down considerably within the very range of the trigger voltage LV, with substantial advantages in terms of limitation to possible well/diffusion forward biasings. In addition, HV loc  will suffer no voltage drop in its steady state from the current draw of the comparator, since this current is supplied from an independent leg (the leg V alcomp ). 
     In summary, an important advantage is that the switching rate of the selector switch  10  is high (switching time at the node OUT on the order of 100 ns, as against some μs of conventional designs having 3 or 4 transistors). 
     The simple construction of the selector switch itself, as provided by the use of just two pass transistors, avoids the need for intermediate nodes, whose transient control would bring about an unavoidably slower switching rate for the selector switch. 
     For a two- or multi-level non-volatile storage device, the high switching rate results in an important reduction of the programming times, in view of the programming involving continual HV/LV and LV/HV switching of the addressed wordline (by the program-and-verify technique). 
     Changes and modifications may be made to the embodiment discussed above. 
     For example, a second, highly conductive path may be added in parallel with a resistor R 10  which would be activated with delay from the time when LV is crossed. In this way, the transient RC time constant (as set by R 10 ) would be quite unrelated to the impedance (as set by the second path) presented by HV loc  in the steady-state condition. 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.