Abstract:
Disclosed is a one-sided rearrangeable connecting network employing fewer elemental switches, or crosspoints, than prior art networks of corresponding capability. In a three stage embodiment of this invention, the first stage comprises n input-mixed rearrangeable switches connected to input terminals, the second stage comprises n one-sided rearrangeable switches connected to the input-mixed switches of the first stage and n/2 two-sided rearrangeable switches interconnecting pairs of the one-sided rearrangeable switches of the second stage, and the third stage comprises n output-mixed rearrangeable switches connected to the one sided switches of the second stage and to output terminals.

Description:
FIELD OF THE INVENTION 
     This invention relates to switching networks and, more particularly, to rearrangeable switching networks. 
     BACKGROUND OF THE INVENTION 
     General 
     Switching systems such as the telephone switching network are generally designed to interconnect, upon request selected pairs of customer terminals from a large plurality of terminals connected to the system. The simplest connecting network capable of such interconnections is a single switching matrix designed to connect any idle customer terminal to any other idle terminals in the network, regardless of whether all other terminals in the network are interconnected therein. 
     To achieve this capability with a single switching matrix it is necessary to employ a number of elemental switches, or crosspoints, within the matrix which increases as the square of the number of customer terminals served by the network. This may result in matrices having prohibitively large numbers of crosspoints. 
     Fortunately it is not necessary to employ such a capable switching network because advantage can be taken of the theory of trunking probability which recognizes that seldom are more than 10 percent of the terminals active at any particular time. In view of this theory of trunking probability, it is possible, and economically advantageous, to use a less capable switching network. 
     One such less capable switching arrangement is realized with a multistage connecting network which comprises an ordered plurality of s interconnected stages ( v i ). In such a multistage network, each stage v i  includes a plurality of switches v i1 , v i2  . . . v ir .sbsb.i having input and output links. The input links of each switch in a stage are respectively connected to the output links of switches in the preceding stage while the output links of each switch in a stage are respectively connected to the input links of switches in the succeeding stage. The input links of the first stage switches are connected to customer terminals termed input terminals, and the output links of the last stage switches are connected to customer terminals termed output terminals. For purposes of the instant specification, it is assumed that each first stage switch, v 1j , has n input links, that each last stage switch, v sj , has n output links, that there are n input switches (r 1  =n) and that there are n output switches (r s  =n). Additionally, only a three-stage network (s=3) is described herein, although it is to be understood that the disclosed invention is applicable to any value of s. 
     The words &#34;input&#34; and &#34;output&#34; of phrases &#34;input terminals&#34; and &#34;output terminals&#34; refer, of course, to the arbitrary input and output designations of the switching network. Each &#34;input&#34; or &#34;output&#34; terminal can in fact be the calling or the called party of an interconnection request. In a telephone system, for example, the input terminals may be the telephones of one central office while the output terminals may be the telephones of another central office. 
     As implied above, it is possible for a customer terminal connected to a multistage switching network to be blocked from being connected as desired, if the network happens to be interconnected in a manner that prevents effecting the desired interconnection. This, of course, is an undesirable situation which in an appropriately designed network can be remedied by dismantling existing interconnections and by rearranging the interconnection paths to accommodate the new request. When such a rearrangement is possible, it is said that the new assignment, which is the new set of interconnections desired to be established, is realizable. A network which can realize all possible assignments without rearranging existing connections is said to be nonblocking, while a network which can realize all possible assignments only by occasionally rearranging existing connections is said to be merely rearrangeable. 
     A network is said to be one-sided rearrangeable if it can realize all assignments which interconnect input terminals to all other input terminals, input terminals to output terminals and vice versa, and output terminals to all other output terminals. 
     A network is said to be two-sided rearrangeable if input terminals can only connect to output terminals (and vice versa). 
     A network is said to be input-mixed rearrangeable if input terminals can be connected to other input terminals or to output terminals, but output terminals cannot connect to other output terminals. Similarly, a network is said to be output-mixed rearrangeable if output terminals can connect to other output terminals or to input terminals, but input terminals cannot connect to other input terminals. 
     The above definitions of one-sided rearrangeability, two-sided rearrangeability, input-mixed rearrangeability and output-mixed rearrangeability can be applied to a switch v ij  in the same manner as applied to a network. 
     Prior Art 
     FIG. 1 illustrates a prior art three-stage input-mixed rearrangeable network. It comprises stages v 1  (element 10), v 2  (element 20) and v 3  (element 30). Stage v 1 , in turn, comprises r 1  input-mixed rearrangeable switches v 11 , v 12  . . . v 1r .sbsb.1, stage v 2  comprises r 2  one-sided rearrangeable switches v 21 , v 22  . . . v 2r .sbsb.2, and stage v 3  comprises r 3  output-mixed rearrangeable switches v 31 , v 32  . . . v 3r .sbsb.3. As indicated above, r 1  =n, r 3  =n, switches v 1j  have n input links each and, similarly, switches v 3j  have n input links each. Since one output link of each v 1j  switch is connected to an input link of each v 2j  switch, and since there are r 2  second stage switches, each v 1j  switch must have r 2  output links. For corresponding reasons, each v 3j  switch has r 2  input links while each v 2j  switch has r 1  (equal to n ) input links and r 3  (equal to n ) output links. Because the v 2j  switches are one-sided rearrangeable, the distinction between input and output links need not be maintained. It may be said, therefore, that the v 2j  switches have 2n input/output links (I/O links). 
     To help in ascertaining the number of crosspoints required for each particular type of switch, switches v 11  and v 21  are illustrated in FIG. 1 with the prior art internal arrangement of elemental switches, or crosspoints, within each type of switch. Modeled after the switch arrangements shown in &#34;Mathematical Theory of Connecting Networks for Telephone Logic&#34; by V. E. Benes, Academic Press, 1965, Chap. 4, FIGS. 9 and 10, the one-sided rearrangeable switch v 21  is depicted as a triangular switch with each I/O link connected to a bus line that intersects bus lines connected to the other I/O links of the switch. The intersections of all of the bus lines are connected with normally open elemental switches such as switch 103, and the closure of those crosspoints effectuate the desired interconnection. It can mathematically be shown, as well as seen from the drawing of FIG. 1, that the triangular switch v 21  is nonblocking, i.e., any I/O link may be connected to any idle I/O link in the switch by the closure of a single crosspoint, irrespective of whether the other I/O links are connected. It can also be seen that in a v 21  type switch having x input links and y output links, the number of elemental switches, or crosspoints, required to implement the switch is equal to (x+y) (x+y-1)/2 or approximately (x+y) 2  /2. 
     Also in accordance with the above mentioned Benes book, the input-mixed rearrangeable switch v 11  is depicted as a trapezoidal switch. It may be viewed as a triangular switch section v 11 , which connects any input link of switch v 11 , and a square switch section v 11  &#34; which connects input links of v 11  to output links of v 11 . The square switch section v 11  &#34; function is achieved by connecting each input link of v 11  to a bus line, e.g., 104, and each output link of v 11  to a bus line, e.g., 105. The input link bus lines are arranged so that each input link bus line intersects all output bus lines, and the intersecting bus lines are interconnected with normally open elemental switches such as switch 106. It can be shown that the trapezoidal switch v 11   is nonblocking in the same sense that the triangular switch v 21  is nonblocking. 
     From the above it can be seen that the number of crosspoints required for the square switch section of the v 11  type switch (for x input links and y output links) is equal to xy, and that the total number of crosspoints required for the v 11  type switch is (x)(x-1)/2+xy, or approximately (x 2  /2)+xy. Of course, it should be noted that the output-mixed rearrangeable switches of stage v 3  are of the same construction as the input-mixed rearrangeable switches of stage v 1 . The stage v 3  switches are drawn in FIG. 1 as mirror images of the stage v 1  switches because the output links of v 3  are on the right side whereas the input links of v 1  are on the left side. 
     Since the stage v 1  and v 3  switches are rearrangeable (and nonblocking), any input terminal may be connected to any other terminal if a sufficient number of stage v 2  switches are made available, i.e., if r 2  is large enough to accommodate all input terminal/output terminal connections employing a particular v 2  switch, plus whatever input terminal/input terminal (and output terminal/output terminal) connections may need to be made through the same particular v 2  switch (e.g., connection between input (output) terminals associated with different v 1  ( v 2 ) switches). It can be shown that for the network of FIG. 1 to be rearrangeable, r 2  must at least be equal to the integer part of 3 n/2, which for large values of n is essentially equal to 3 n/2. Calculating the total number of crosspoints required for the network of FIG. 1 results in stages v 1  and v 3  requiring n(n 2  /2+ n3n/2), or 2 n 3  crosspoints each, and stage v 2  requiring 3n/2(4n/2), or 3 n 3  crosspoints, for a total of 7n.sup. 3 crosspoints. 
     SUMMARY OF THE INVENTION 
     It is an object of this invention to construct a one-sided rearrangeable network which has a number of crosspoints lower than the number of crosspoints required for the above prior art network. 
     This object, among others, is realized with a three stage one-sided rearrangeable switching network having input-mixed rearrangeable switches in the first switching stage, output-mixed rearrangeable switches in the third switching stage, and interconnected one-sided rearrangeable switches in the second switching stage. The interconnection of the one-sided switches in the second stage is accomplished by pairing off the switches and by interconnecting each pair with an auxiliary two-sided rearrangeable switch. Specifically, the I/O links of the first one-sided switch in a pair are connected to the input links of an associated auxiliary switch, and the output links of the associated auxiliary switch are connected to the I/O links of the second one-sided rearrangeable switch in the pair. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 depicts a block diagram of a prior art configuration for a one-sided rearrangeable multistage switching network; 
     FIG. 2 depicts a block diagram of a one-sided rearrangeable multistage switching network in accordance with the principles of this invention; 
     FIG. 3 describes the second stage interconnection requirements associated with a circular interconnection assignment in a FIG. 1 network; and 
     FIG. 4 illustrates the interconnection paths of the FIG. 2 network arranged to implement a selected assignment. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 depicts a block diagram of a prior art one-sided rearrangeable network which was, in the interest of simplicity, limited to three stages. To make the FIG. 1 network operate, however, a control section must be employed which would maintain the necessary data related to the existing assignment and which would be capable of altering the assignment of the FIG. 1 network in response to additional interconnection requests. This control section is not illustrated in FIG. 1 because it relates only peripherally to the subject matter of this invention, and inclusion thereof, it is believed, would only confuse the issue. 
     For similar reasons, FIG. 2, which presents the block diagram of a three stage one-sided rearrangeable network in accordance with the principles of this invention, also does not illustrate the control section associated with the network. It is noted, however, that a number of known controllers are suitable for use with the networks of FIGS. 1 and 2 and that whatever control section is employed in conjunction with the network of FIG. 1 may also be employed in conjunction with the network of FIG. 2. For those interested, reference is made to a control section described by M. C. Paull in U.S. Pat. No. 3,129,407 issued Apr. 14, 1964. 
     As illustrated, FIG. 2 comprises a first switching stage, 40, designated v 1 , a second switching stage, 50, designated v 2 , and a third switching stage, 60, designated v 3 . Each switching stage v i  contains an r i  plurality of switches v ij  j=1, 2 . . . r i  and each v ij  switch contains input links and output links. As in the network of FIG. 1, there are n input-mixed rearrangeable switches in stage v 1 , each having n input and r 2  output links respectively connected to r 2  switches in v 2 , and n output-mixed rearrangeable switches in stage v 3 , each having n output and r 2  input links respectively connected to the r 2  switches in v 2 . Also as in the network of FIG. 1, stage v 2  has r 2  one-sided rearrangeable switches each having 2n I/O links respectively connected to stages v 1  and v 3 . 
     The FIG. 2 network differs from the FIG. 1 network in that the number of stage v 2  switches, r 2 , is only equal to n, rather than 3n/2, and in that a number of auxiliary interconnecting switches are introduced into the stage v 2  of FIG. 2. The purpose, construction, and the interconnections of those auxiliary switches will become apparent when the reason for the FIG. 1 requirement of v 2  being equal to 3n/2 is more fully appreciated from the discussion below. 
     In general, any stage v 2  switch may be employed to interconnect more than one pair of I/O links. An unusual situation occurs, however, when a desired assignment includes a circular assignment, as for example, { (I 1 ,I 2 ), (I 2 ,I 3 ), (I 3 ,I 1 )} where I 1 , I 2 , and I 3  represent an input terminal connected to v 11 , v 12  and v 13 , respectively. FIG. 3 illustrates such an assignment for a FIG. 1 switching network with n=4 and shows that three stage v 2  switches must be employed to implement the above circular assignment. This is shown with solid lines 210, 211, 212, 213, 214 and 215. From FIG. 3 it can also be seen that in order to connect the other two terminals associated with switch v 11  to terminals associated with switches v 12   and v 13 , three additional stage v 2  switches are necessary. Thus, it appears that for n=4, r 2  must equal 6, or 3n/2. 
     I have discovered that but for the circular assignments as described above, the value of r 2  would need only be equal to n to make the network of FIG. 2 rearrangeable. Therefore, in accordance with the principles of this invention, the number of stage v 2  switches is permitted to be as low as n (r 2  ≧ n) and the circular assignments implemented with auxiliary switches. Actually, since two interconnections of each circular assignment can be implemented by a pair of stage v 2  triangular switches, the auxiliary switches need only implement the third interconnection in each circular assignment. 
     In FIG. 2, the auxiliary switches are depicted in FIG. 2 with blocks μ 1  . . . μ r .sbsb.2/2. To interconnect the auxiliary switches, stage v 2  switches, v 2j , are grouped in pairs (which, conveniently, may be grouped into pairs of adjacent switches v 2 ,2i -1  and v 2 ,2i i=1, 2 . . . n/2) and each pair of switches is interconnected with an auxiliary two-sided rearrangeable switch μ i . That is, the 2n I/O links of each switch v 2 ,2i -1  are connected to the 2n input links of a two-sided rearrangeable switch μ i , and the 2n I/O links of each switch v 2 ,2i are connected to the 2n output links of switch μ i . Again, since only one out of three possible interconnections needs to be implemented by any switch μ i , each two-sided μ i  switch may advantageously comprise a cascade of two two-sided rearrangeable switches with one switch, μ  i  &#39;, having 2n input links and 2n/3 output links and the other switch, μ i  &#34;, having 2n/3 output links (connected to the 2n/3 input links of μ i  &#39;) and 2n output links. This is shown diagrammatically within switch μ 1  of FIG. 2. 
     Computing the crosspoint count of individual switches, it can be seen that the number of crosspoints in stages v 1  and v 3  (having input-mixed and output-mixed switches) is ##EQU1## or 3n 3  /2 crosspoints in each stage, the number of crosspoints in stage v 2  (having triangular switches) is ##EQU2## and the number of crosspoints in switches μ i  is ##EQU3## for a total of ##EQU4## crosspoints (as compared to 7n 3  for the network of FIG. 1). 
     Another reduction in the crosspoint count may be achieved when it is realized that if more than one switch is permitted to be closed for any particular interconnection, and if a two-sided rearrangeable switch has a number of output links that is at least equal to the number of its input links, then such a two-sided rearrangeable switch can also serve as an input-mixed rearrangeable switch. This can easily be shown when it is realized that an input-mixed assignment can be decomposed into two two-sided assignments which may be connected to the same output link bus by the closure of two crosspoints. If this simplification is employed in the network of FIG. 2, the input-mixed rearrangeable and the output-mixed rearrangeable switches of stages v 1  and v 3 , respectively, can be replaced with two-sided rearrangeable switches, reducing thereby the crosspoint count of the FIG. 2 network to ##EQU5## crosspoints. 
     EXAMPLE 
     The following example is presented to illustrate the rearrangeability property of the FIG. 2 circuit. 
     Consider the assignment: 
     
         { (I.sub.11,I.sub.13) (I.sub.22,I.sub.31) (I.sub.21,I.sub.42) (I.sub.14,O.sub.13) (I.sub.12,O.sub.23) (I.sub.32,I.sub.41) (I.sub.33,O.sub.31) (I.sub.34,O.sub.12) (I.sub.44,O.sub.43) (O.sub.21,O.sub.41) (O.sub.14,O.sub.22) (O.sub.32,O.sub.34)} 
    
     where I ij  designates the j th  input terminal in the i th  switch of stage v 1 , where O ij  designates the j th  output terminal in the i th  switch of stage v 3  and where the two terminals within each parenthesized expression signify a desired interconnection. 
     FIG. 4 shows the interconnection of the above assignment in a switching network in accordance with the principles of this invention with n=4 and r 2  =4. The interconnections of FIG. 4 were derived by proceeding in accordance with the following method: 
     1. Any interconnection consisting of two customer terminals connected to the same switch (input or output) are interconnected within the switch. In the above example, interconnections (I 11 ,I 13 ) and (O 32 ,O 34 ) fall into this category. These interconnections are depicted in FIG. 4 within switches v 11  and v 33 , respectively. 
     2. Remaining interconnection pairs are partitioned into n/2 groups, subject to the condition that terminals associated with a particular switch of stage v 1  or stage v 3  appear within a group no more than twice. For example, I 11 , I 12  and I 14  relate to switch v 11  and therefore only two of them are permitted to be included in any one group. Such partitioning is always possible since there are n input terminals associated with stage v 1  switches and n output terminals associated with stage v 3  switches. A mathematical analysis proving that such partitioning is always possible is presented by J. Peterson in &#34;Die Theorie Der Regularen Graphen,&#34; Acta. Math. 15 (1891), 193-220. 
     In the above example, n=4 and the two groups arbitrarily chosen are: 
     
         G.sub.1 = { (I.sub.22,I.sub.31), (I.sub.21,I.sub.42), (I.sub.14,O.sub.13), (I.sub.12,O.sub.23), (I.sub.32,I.sub.41)} 
    
     
          g.sub.2 = { (i.sub.33,o.sub.31), (i.sub.34,o.sub.12), i.sub.41,o.sub.43), (o.sub.21,o.sub.41), (o.sub.14,o.sub.22)}. 
    
     3. each group is partitioned into three subgroups such that no switch is repeated within a subgroup. This is always possible because each switch appears at most twice in each group. In the above example, the subgroups chosen are 
     
          G.sub.11 = [ (I.sub.22,I.sub.32), (I.sub.14,O.sub.13)] 
    
     
          g.sub.12 = [ (i.sub.21,i.sub.42)] 
    
     
          g.sub.13 = [ (i.sub.12,o.sub.23), (i.sub.32,i.sub.41)] 
    
     and 
     
          G.sub.21 = [ (I.sub.33,O.sub.31), (I.sub.44,O.sub.43), (O.sub.14,O.sub. 22)] 
    
     
         g.sub.22 = [ (i.sub.34,o.sub.12), (o.sub.21,o.sub.41)] 
    
     
          g.sub.23 = empty. 
    
     4. Each subgroup G i1  assignment is implemented with switch v 2 ,2i -1 , subgroup G i2  assignment is implemented with switch v 2 ,2i and subgroup G i3  assignment is implemented with switch μ i . In the above example, groups G 11 , G 12 , G 13 , G 21 , and G 22  are implemented with switches v 21 , v 22 , μ i , v 23 , and v 24 , respectively. Switch μ 2  is not employed because subgroup G 23  is empty. 
     A perusal of FIG. 4 reveals that switch v 23  is employed by all four stage v 3  switches. It appears, therefore, that no additional interconnections to output terminals can be made in group G 2  since they would necessarily involve the output links of switch v 23 . That is not a calamity beacause an additional connection involving output terminals, such as (O 24 ,O 33 ), need not be placed in group G 2 . In the above example, the additional interconnection above may be placed in group G 1 , subgroup G 12 , and may be implemented with switch v 22  as depicted in FIG. 4. Alternatively, this interconnection could be placed in subgroup G 13  and implemented with switch μ 1 . 
     It should be noted that the embodiments illustrated and described herein are merely illustrative of the principles of this invention and should not be construed as fully depicting my invention. Particularly, it should be realized that the various simplifications introduced into the description were so introduced only to simplify the drawing and to make the discussion more concise. For example, the circuit of FIG. 2 can be implemented with any number of input and output terminals and with any number of stages. Also, any input-mixed one-sided or two-sided switch can be decomposed into a three stage network composed of smaller switches.