Abstract:
A circuit and method for providing a temperature compensated voltage comprising a voltage regulator circuit configured to provide a regulator voltage, a voltage reference circuit configured to provide a reference voltage, VREF, a comparison circuit configured to provide a control voltage VCTL, and an operational amplifier configured to provide amplification and coupling to said comparison circuit, wherein the voltage can be a high voltage greater than 1.2 V.

Description:
BACKGROUND 
       [0001]    1. Field 
         [0002]    The disclosure relates generally to a voltage regulator and, more particularly, to a low dropout regulator thereof. 
         [0003]    2. Description of the Related Art 
         [0004]    Low dropout (LDO) regulators are commonly used to regulate internal voltage supplies at lower voltage from higher voltages. Voltage regulation is important where circuits are sensitive to transients, noise and other types of disturbances. The control of the regulated voltage over variations in both semiconductor process variation, and temperature is key to many applications. Additionally, power consumption is also a key design requirement. 
         [0005]      FIG. 1  is a circuit schematic of a prior art low dropout (LDO) regulator with separate bandgap network.  FIG. 1  consists of three stages. The first stage, stage  1 , establishes the voltage reference. The second stage, stage  2 , is the voltage regulator, that uses this reference to make a regulated rail, VREG. The third stage, stage  3 , is the Power-On-Reset, which measures the regulated voltage, VREG and generates a rising edge on its output porb when the regulated voltage VREG exceeds a given percentage of its intended regulated value. It is desirable to merge the reference voltage, VREF, and regulated voltage generator VREG, by directly creating a voltage that is temperature compensated. 
         [0006]      FIG. 1  shows the circuit power supply voltage VDD  10 , and ground VSS  20 . The network can be understood as three stages. The first stage provides a voltage reference, VREF, as its output. The second stage consists of an operational amplifier, and a feedback loop which serves as a control of the regulator output transistor. The third stage establishes the regulated voltage, VREG, with a pass transistor, and a load. In the third stage, the output voltage of the network is VOUT  30  is also the regulated voltage VREG. The first operational amplifier OA 1   40  produces a reference voltage VREF and is electrically connected to a second operational amplifier OA 2   50 . The second operational amplifier OA 2   50  is electrically coupled to the PFET output device  60 . The PFET  60  is electrically coupled to the output VOUT  30  and load element  55 . The operational amplifier OA 2   50  has a first input  51  and second input  52 . The OA 2  input signal  52  is connected to resistor feedback network formed from resistor RLH  53 , and resistor RLL  54 . In the first stage, a resistor RF  70  and resistor RF  75  are electrically coupled to the first and second input of operational amplifier OA 1   40 . Additionally, resistor RF  70  and RF  75  are coupled to the npn transistors NPN 1 , and NPN 2 , respectively. The npn transistor NPN 1   80  is coupled to resistor element RPTAT  90 . The npn transistor NPN 2   85  is coupled to resistor element RA  95 . 
         [0007]      FIG. 2  is a circuit schematic of a network that provides a R-SHIFT method.  FIG. 2  shows a prior art bandgap circuit schematic. From the  FIG. 2  circuit schematic, an R-SHIFT method is described. In the circuit  200 , the voltage supply VDD  210  supports the network, with a ground VSS  220 . The output voltage is the regulated voltage VREG  230  at the output voltage. The operational amplifier OA 1   240  provides an output signal to the gate of the PMOS pass transistor  260 . A first resistor RF 1   270  and second resistor RF 2   275  are electrically coupled to the operational amplifier OA 1   240 . Additionally, there are a first and second device represented as a first diode  280  of size unity, and a second diode  285  of size N. The resistor RPTAT  290  is coupled to the diode  285 , RSHIFT resistor  250 , and operational amplifier OA 1   240 . 
         [0008]    A shift resistance RSHIFT increases the current through the resistances RF and shifts up from 1.2V to an arbitrarily value VREG. By setting properly RF, RSHIFT, RPTAT and N, VREG is directly compensated in temperature, but this comes at the cost of two very large resistors RF and an operational amplifier. 
         [0009]      FIG. 3  illustrates a circuit schematic  300  that highlights the R-String method. In  FIG. 3 , the bandgap cell is indirectly regulated to 1.25 V through a resistor ladder network. The ground potential VSS is  320 , and the output rail VOUT  310  is established by the resistor ladder network, and operational amplifier OA 1   340 . The regulated voltage node  330  is electrically coupled to the resistor ladder network resistor R 3   350  and resistor R 4   355 . The inputs of the operational amplifier OA 1   340  is coupled to resistor RF 1   370  and resistor RF 2   375 . The npn transistor  380  and  385  are coupled to the OA 1  input signals. Resistor R 1   390  (PTAT resistor), and resistor R 2   395  are coupled to the npn transistor  380  and  385 . 
         [0010]    The output voltage, VOUT, VOUT=VREG is adjusted by the operational amplifier OA 1   340  such that its fraction R 4 /(R 3 +R 4 ) matches ˜1.25V. Then it is possible to optimize only the left part (bandgap part) to compensate it in temperature, and so the same compensation will also result for VOUT=VREG. 
         [0011]      FIG. 4  illustrates an additional circuit schematic  400 . In the prior implementation of  FIG. 3  is a resistive path between VREG and ground VSS. This will require large resistor values which is not desirable.  FIG. 4  is a circuit schematic  400  that utilizes a power supply voltage VDD  410  and ground potential  420 . The npn transistor pair NPN 1   480  (size N) and NPN 2   485  (size 1) are coupled to resistor RPTAT  490  and resistor RS  495 . The base of the npn transistors establish the reference voltage VREF and is electrically connected to resistor RH  453 , and resistor RL  454 . The npn transistor are sourced by current mirror formed by PFET  430 A and PFET  430 B. The current mirror PFET  430 A is connected to the gate of the PFET MPLOOP  425 . A second PFET current mirror is electrically coupled to the power supply voltage VDD  410  formed by PFET mirror  435 A and  435 B. The transistor MPLOOP  425  is coupled to an NFET current mirror  445 A and  445 B. 
         [0012]    The disadvantage of this circuit topology is the sensitivity to the regulated voltage VREG. If the regulated voltage, VREG, has noise, it is amplified because applied on the gate-to-source voltage of the MPLOOP. 
         [0013]      FIG. 5  shows a circuit schematic of an indirect PTAT  500 . The power supply VDD  510  and the ground reference VSS  520  supplies circuit  500 . The network has a PFET current mirror M 1   530 A and M 3   530 B. The output pass transistor is a PFET (e.g. PMOS) M 4   540 . The PFET current mirror maintains a controlled current through the NPN Q 1   535  and NPN current mirror formed by Q 2   545 A and Q 3   545 B. The base of NPN Q 1  is coupled to resistor R 1   560 , resistor R 2   570 , and resistor R 3   580 , as well as NPN Q 4   550 . 
         [0014]    The PTAT effect is done by matching the current in Q 2   545 A (N elements) with the current in Q 1   535  (1 element) through the VREG loop. VREG is adjusted for this matching and {R 2   570 , R 3   580 } allow to adjust the value of VREG. This implementation has the following disadvantages and drawbacks:
       The loop gain is low, which leads to any fluctuation on VREG becomes as a current (VREG−VBE 4 )/R 2 , then copied with a low ratio to Q 1 . Only the line VCTL offers the gain.   The PSRR is poor because VCTL is supplied referenced. Noise on the power supply node, VDD, is applied on VGSM 4  and the loop needs to be very fast to compensate for this noise.   Mostly, it is not high-voltage compliant. For example, if the power supply voltage, VDD, is VDD=20V, then the gate of PMOS transistor M 1   530 A is 19V and npn Q 1   535  will undergo electrical breakdown for a standard 5V process. If transistors are stacked, in a series cascode configuration, the series cascode can protect its collector; this leads to a non-starting loop because the cascodes themselves need to be started, otherwise they are blocking the regulation path. The issue of high voltage compliance is also true for the transistor Q 3   545 B.   Addressing the issue with series cascode transistors is achievable, but with an impact toe the minimum voltage of operation (e.g. series cascode configuration leads to multiple drain-to-source voltage drops (VDSsat).       
 
         [0019]    U.S. Pat. No. 6,995,587 to Xi, describes a method for generating a bandgap reference current. The method for generating a band gap reference current includes the steps for mirroring the bandgap reference current, summing the mirrored currents, and modulating and outputting a bandgap reference voltage from the sum. Representative preferred embodiments are disclosed in which the methods of the invention are used in providing under-voltage protection and in providing a regulated output voltage. Preferred embodiments of the invention include a bandgap under-voltage detection circuit using a comparator and a voltage regulator circuit having a regulated voltage output capability. 
         [0020]    U.S. Pat. No. 6,512,398 to Sonoyama describes a circuit device with improved reliability by minimizing the fluctuations of the detection level of the supply voltage. In the circuit device comprises a differential amplifier circuit that amplifies the differential voltage representing the difference between the reference voltage V REF  generated by a reference voltage generating section and the detection voltage obtained by dividing a supply voltage. The reference voltage generating section generates reference voltage V REF  from the base-emitter voltage of a bipolar transistor. 
         [0021]    A bandgap voltage reference is discussed in the Analog Devices data sheet for AD 580 . The AD 580  Data Sheet discloses a 3-terminal, low cost, temperature-compensated, bandgap voltage reference, which provides a fixed 2.5V output for inputs between 4.5V and 30V. A unique combination of advanced circuit design and thin film resistors provide the AD 580  with an initial tolerance of ±0.4%, a temperature stability of better than 10 ppm/° C., and long-term stability of better than 250 μV. 
         [0022]    In these prior art embodiments, the solution to establish a utilized various alternative solutions. 
       SUMMARY 
       [0023]    It is desirable to provide a solution to address an efficient voltage regulator with minimal power consumption. 
         [0024]    A principal object of the present disclosure is to provide a circuit with a loop gain VCTL with a ground reference for better power supply rejection ratio (PSRR) and noise immunity. 
         [0025]    Another further object of the present disclosure is to provide a circuit that utilized field effect transistors that are voltage tolerant to high voltage. 
         [0026]    Another further object of the present disclosure is to provide a circuit that utilizes high voltage field effect transistors to avoid series-cascode of the bipolar junction transistors. 
         [0027]    In summary, a circuit providing a temperature compensated voltage comprising a voltage regulator circuit configured to provide a regulator voltage, a voltage reference circuit configured to provide a reference voltage a startup circuit configured to provide a control voltage VCTL, and an operational amplifier configured to provide amplification and coupling to said startup circuit. 
         [0028]    In addition, a method is disclosed in accordance with the embodiment of the disclosure. A method of providing a temperature compensated high voltage comprising the steps of a first step, providing a circuit on a semiconductor chip, the circuit comprising a voltage reference generator, and a voltage regulator generator; a second step, establishing a current in transistor QN; a third step, copying the current onto transistor QN 1 ; a fourth step, copying the current back to current mirror {MP 1 , MPN}; a fifth step, comparing the current in transistor Q 1  to current in transistor QN to establish a voltage VCTL; a sixth step, driving the current-mode operational amplifier {MNOA, MPOA, and MP}; and, a seventh step, adjusting a regulator voltage VREG to match currents in transistor Q 1  and QN. 
         [0029]    Other advantages will be recognized by those of ordinary skill in the art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0030]    The present disclosure and the corresponding advantages and features provided thereby will be best understood and appreciated upon review of the following detailed description of the disclosure, taken in conjunction with the following drawings, where like numerals represent like elements, in which: 
           [0031]      FIG. 1  is a circuit schematic of a prior art low dropout (LDO) regulator with separate bandgap network; 
           [0032]      FIG. 2  is a circuit schematic of a prior art network that is T-compensated using a shift resistance to regulate a voltage above the conventional ˜1.20V value; 
           [0033]      FIG. 3  is a circuit schematic of a prior art network highlighting the R-string method; 
           [0034]      FIG. 4  is a circuit schematic of an improved network of the R-string method network of  FIG. 3 ; 
           [0035]      FIG. 5  is a circuit schematic of a prior art network for Indirect PTAT; 
           [0036]      FIG. 6  is a circuit schematic in accordance with the first embodiment of the disclosure; 
           [0037]      FIG. 7  is a circuit schematic in accordance with the second embodiment of the disclosure; and, 
           [0038]      FIG. 8  is a method in accordance with the embodiment of the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0039]      FIG. 6  is a circuit schematic in accordance with the first embodiment of the disclosure. The circuit  600  comprises a power supply  610  and a ground VSS  620 . A first p-channel MOSFET current mirror MP  630 A and MP  630 B sources the circuit  600 . A second p-channel MOSFET current mirror MPN  632 A and MP 1   632 B, electrically coupled to p-channel MOSFET MP  630 A. The second p-channel MOSFET current mirror provides a 1:N MOSFET width ratio, where transistor MPN  632 A has a MOSFET width which is N times wider than transistor MP 1   632 B. The second p-channel MOSFET current mirror transistor MP 1   632 B is driven by the current flowing through the collector of the bipolar transistor QN 1   645 B. The bipolar transistor QN 1   645 B forms an n-type bipolar current mirror with a second bipolar transistor QN  645 A. The second p-channel MOSFET current mirror MPN  632 A sources the collector of the bipolar transistor Q 1   650  The emitter of the bipolar transistor Q 1   650  is electrically connected to the ground VSS  620 . The base of the bipolar transistor Q 1   650  is electrically coupled to the resistor RPTAT  660 , and the resistor network RUP  670  and RSHIFT  680 . The p-channel MOSFET MPOA  630 B is driven by the current flowing through the n-channel MOSFET MNOA  640 A. The gate of the n-channel MOSFET MNOA  640  is the control voltage VCTL. In the circuit  600 , the collector-to-emitter current in bipolar transistor QN  645 A is mirrored onto bipolar transistor QN 1   645 B with the ratio N:1. Using a current mirror {QN  645 A, QN  645 B} limits the current consumption. The current is then copied back to the p-channel current mirror MP 1   632 B and MPN  632 A where the 1:N ratio restores the previous N:1 scaling. Thus, the current in bipolar transistor Q 1   650  is compared to the current to QN  645  and the result pushes or pulls the signal line voltage VCTL. This establishes a drive current which establishes the current-mode operational amplifier formed from n-channel MOSFET MNOA  640 , and current mirror p-channel MOSFET MPOA  630 B and p-channel MOSFET MP  630 A, where the ratio MPOA:MP can be very large to be able to inject more current to the output. 
         [0040]    The regulator voltage, VREG, is adjusted such that the signal voltage VCTL drives a given current through n-channel transistor MNOA  640 ; this allows prevention of signal clipping of the signal VCTL. (e.g. VCTL is not clipping up nor down). The regulator voltage VREG is adjusted to match the currents in bipolar transistor Q 1   650  and bipolar transistor QN  645 A. This method emulates a PTAT, with the advantage that the regulation voltage itself is referenced to the ground VSS  620 . 
         [0041]    The derivation of the regulation voltage VREG is illustrated in the following equations. First, equating the currents of transistor QN  645 A, and transistor Q 1   650  where IQN=IQ 1 . This can be expressed as 
         [0000]    
       
         
           
             
               I 
                
               
                 ( 
                 RPTAT 
                 ) 
               
             
             = 
             
               
                 
                   
                     VBE 
                      
                     
                         
                     
                      
                     1 
                   
                   - 
                   VBEN 
                 
                 RPTAT 
               
               = 
               
                 
                   Δ 
                    
                   
                       
                   
                    
                   VBE 
                 
                 RPTAT 
               
             
           
         
       
     
         [0000]    The regulation voltage, VREG and can expressed as 
         [0000]    
       
         
           
             VREG 
             = 
             
               
                 
                   VBE 
                    
                   
                       
                   
                    
                   1 
                 
                 + 
                 
                   RUP 
                    
                   
                       
                   
                   · 
                   
                     I 
                      
                     
                       ( 
                       RUP 
                       ) 
                     
                   
                 
               
               = 
               
                 
                   VBE 
                    
                   
                       
                   
                    
                   1 
                 
                 + 
                 
                   RUP 
                    
                   
                       
                   
                   · 
                   
                       
                   
                    
                   
                     ( 
                     
                       
                         I 
                          
                         
                           ( 
                           RSHIFT 
                           ) 
                         
                       
                       + 
                       
                         I 
                          
                         
                           ( 
                           RPTAT 
                           ) 
                         
                       
                     
                     ) 
                   
                 
               
             
           
         
       
       
         
           
             VREG 
             = 
             
               
                 VBE 
                  
                 
                     
                 
                  
                 1 
               
               + 
               
                 RUP 
                  
                 
                     
                 
                 · 
                 
                     
                 
                  
                 
                   ( 
                   
                     
                       
                         VBE 
                          
                         
                             
                         
                          
                         1 
                       
                       RSHIFT 
                     
                     + 
                     
                       
                         Δ 
                          
                         
                             
                         
                          
                         VBE 
                       
                       RPTAT 
                     
                   
                   ) 
                 
               
             
           
         
       
     
         [0000]    The regulation voltage can be expressed as a ratios of the resistors RPTAT  660 , resistor RUP  670 , and RSHIFT  680   
         [0000]    
       
         
           
             VREG 
             = 
             
               
                 VBE 
                  
                 
                     
                 
                  
                 
                   1 
                    
                   
                       
                   
                   · 
                   
                       
                   
                    
                   
                     ( 
                     
                       1 
                       + 
                       
                         RUP 
                         RSHIFT 
                       
                     
                     ) 
                   
                 
               
               + 
               
                 Δ 
                  
                 
                     
                 
                  
                 
                   VBE 
                    
                   
                       
                   
                   · 
                   
                     ( 
                     
                       RUP 
                       RPTAT 
                     
                     ) 
                   
                 
               
             
           
         
       
     
         [0000]    This equation is made of a base-emitter voltage, VBE 1  term that decreases with temperature, and a ΔVBE term that increases with temperature. By calculating properly RUP, RPTAT, RSHIFT and N (that is embedded in ΔVBE), the value of VREG can be chosen and also compensate it in temperature. 
         [0042]      FIG. 7  is a circuit schematic in accordance with the second embodiment of the disclosure. The circuit  700  comprises a power supply VDD  710  and a ground VSS  720 . The circuit  700  power supply can be a battery power source (e.g. VDD=VBAT). A p-channel MOSFET current mirror MP  730 A and MP  730 B sources the circuit  700 . A second p-channel MOSFET current mirror MPN  732 A and MP 1   732 B is electrically coupled to p-channel MOSFET MP  730 A. The second p-channel MOSFET current mirror provides a 1:N MOSFET width ratio, where transistor MPN  732 A has a MOSFET width which is N times wider than transistor MP 1   732 B. The second p-channel MOSFET current mirror transistor MP 1   732 B is driven by the current flowing through the collector of the bipolar transistor QN 1   745 B. The bipolar transistor QN 1   745 B forms an n-type bipolar current mirror with a second bipolar transistor QN  745 A. The second p-channel MOSFET current mirror MPN  732 A sources the collector of the bipolar transistor Q 1   750 . The emitter of the bipolar transistor Q 1   750  is electrically connected to the ground VSS  720 . The base of the bipolar transistor Q 1   750  is electrically coupled to the resistor RPTAT  760 , and the resistor network RUP  770  and RSHIFT  780 . The p-channel MOSFET MPOA  730 B is driven by the current flowing through the n-channel MOSFET MNOA  740 A. The gate of the n-channel MOSFET MNOA  740  is the control voltage VCTL. 
         [0043]    In the circuit  700 , the collector-to-emitter current in bipolar transistor QN  745 A is mirrored onto bipolar transistor QN 1   745 B with the ratio N:1. Using a current mirror {QN  745 A, QN  745 B} limits the current consumption. The current is then copied back to the p-channel current mirror MPN  732 A and MP  1   732 B where the 1:N ratio restores the previous N:1 scaling. Thus, the current in bipolar transistor Q 1   750  is compared to the current to QN  745  and the result pushes or pulls the signal line voltage VCTL. This establishes a drive current which establishes the current-mode operational amplifier formed from n-channel MOSFET MNOA  740 , and current mirror p-channel MOSFET MPOA  730 B and p-channel MOSFET MP  730 A, where the ratio MPOA:MP can be very large to be able to inject more current to the output. Additionally, the implementation in general does not have to restore exactly the ratio N:1 to 1:N. An implementation when the ratio is not restored to 1:1, but to 1:M or M:1, where M is. As long as this ratio remains constant (using mirror ratios), a PTAT behaviour can also be implemented. For example, this can lead to current IQ 1  different from current IQN, but ratio well controlled between both. 
         [0044]    The regulator voltage, VREG, is adjusted such that the signal voltage VCTL drives a given current through n-channel transistor MNOA  740 ; this allows prevention of signal clipping of the signal VCTL. (e.g. VCTL is not clipping up nor down). The regulator voltage VREG is adjusted to match the currents in bipolar transistor Q 1   750  and bipolar transistor QN  745 A. This method emulates a PTAT, with the advantage that the regulation voltage itself is referenced to the ground VSS  720 . 
         [0045]    A startup function system includes a p-channel MOSFET  785 A, a p-channel MOSFET  785 B, and startup resistance  790 . The gate of p-channel MOSFET  785  is electrically connected to the drain of p-channel MOSFET  785 B, providing a startup signal GPSTART. The gate of p-channel MOSFET  785 B is connected to the p-channel current mirror {MP  730 A, and MPOA  730 B}. The p-channel MOSFET  785 B drain is electrically connected to the resistance RSTARTUP  790 . 
         [0046]    In this embodiment, the PTAT requires a p-channel MOSFET current mirror referenced to the supply from the current mirror MPN  732 A and MP 1   732 B; this can use the rail OUT=VREG. For example, the sources of the p-channel MOSFET current mirror are connected to the battery BAT instead of VREG. 
         [0047]    The start-up system components, GPSTART is initially discharged as long as no current flows through the amplifier. This allows the supply to connect to OUT using the “Startup MS” PMOS  785 A. Once current starts flowing, GPSTART goes up to the supply and deactivates MS. 
         [0048]    The resistance RSTARTUP  790  can be a passive or active element. For example, the resistance RSTARTUP  790  can be a source-drain resistance of a MOSFET or plurality of MOSFETs. In this embodiment, a very large startup resistance RSTARTUP  790  is desired to activate the regulator. 
         [0049]    Other equivalent circuit embodiments can be utilized. High-voltage transistors can replace the low-voltage transistor components within the circuit embodiment. For example, the transistor MNOA  740  can be a high-voltage transistor to drive the transistors MPOA  730 B, and transistor MP  730 A in a high voltage domain. Additionally, other equivalent circuit embodiments also can be utilized. It is worth noting that all the bipolar NPN transistors may be replaced by NMOS in weak inversion, to eliminate the base-current errors and to reduce the total size. 
         [0050]      FIG. 8  is a method in accordance with the embodiment of the disclosure. A method is disclosed in accordance with the embodiment of the disclosure. A method for providing a temperature compensated high voltage  800 , comprising the steps of a first step  810  providing a circuit on a semiconductor chip, the circuit comprising a voltage reference generator, and a voltage regulator generator, a second step  820  establishing a current in transistor QN, a third step  830  copying the current onto transistor QN 1 , a fourth step  840  copying the current back to current mirror {MP 1 , MPN}, a fifth step  850  comparing the current in transistor Q 1  to current in transistor QN to establish a voltage VCTL, a sixth step  860  driving the current-mode operational amplifier {MNOA, MPOA, and MP}, a seventh step  870  adjusting a regulator voltage VREG to match currents in transistor Q 1  and QN. 
         [0051]    In the method in accordance with the embodiment, the third step  830 , the current in QN is copied onto QN 1  with the ratio N:1 (to limit the consumption). 
         [0052]    In the method in accordance with the embodiment, the fourth step  840  the current is copied back to {MP 1 , MPN} where the 1:N ratio restores the previous N:1 scaling. 
         [0053]    In the method in accordance with the embodiment, the fifth step  850  the current in Q 1  is compared to the current to QN and the result pushes or pulls the line VCTL. 
         [0054]    In the sixth step  860 , this drives the current mode operational amplifier {MNOA, MPOA and MP} where the ratio MPOA:MP can be very large to be able to inject more current to the output. 
         [0055]    In the seventh step  870 , VREG is adjusted such that VCTL drives a given current through MNOA, and this means VCTL is not clipping up nor down: in other words VREG is adjusted to match the currents in Q 1  and QN. We have thus emulated a PTAT, with the advantage compared to prior art that the regulation itself is referenced to the ground. 
         [0056]    In the method in accordance with the embodiment, this can be further described from the equation from the equating of the current through transistor QN and the transistor Q 1 , starting with IQN=IQ 1 . This means: 
         [0000]    
       
         
           
             
               I 
                
               
                 ( 
                 RPTAT 
                 ) 
               
             
             = 
             
               
                 
                   
                     VBE 
                      
                     
                         
                     
                      
                     1 
                   
                   - 
                   VBEN 
                 
                 RPTAT 
               
               = 
               
                 
                   Δ 
                    
                   
                       
                   
                    
                   VBE 
                 
                 RPTAT 
               
             
           
         
       
     
         [0057]    In the method in accordance with the embodiment, the derivation of the regulated voltage VREG can be derived according to VREG: 
         [0000]    
       
         
           
             VREG 
             = 
             
               
                 
                   VBE 
                    
                   
                       
                   
                    
                   1 
                 
                 + 
                 
                   RUP 
                   . 
                   
                     I 
                      
                     
                       ( 
                       RUP 
                       ) 
                     
                   
                 
               
               = 
               
                 
                   VBE 
                    
                   
                       
                   
                    
                   1 
                 
                 + 
                 
                   RUP 
                    
                   
                       
                   
                   · 
                   
                       
                   
                    
                   
                     ( 
                     
                       
                         I 
                          
                         
                           ( 
                           RSHIFT 
                           ) 
                         
                       
                       + 
                       
                         I 
                          
                         
                           ( 
                           RPTAT 
                           ) 
                         
                       
                     
                     ) 
                   
                 
               
             
           
         
       
       
         
           
             VREG 
             = 
             
               
                 VBE 
                  
                 
                     
                 
                  
                 1 
               
               + 
               
                 RUP 
                  
                 
                     
                 
                 · 
                 
                   ( 
                   
                     
                       
                         VBE 
                          
                         
                             
                         
                          
                         1 
                       
                       RSHIFT 
                     
                     + 
                     
                       
                         Δ 
                          
                         
                             
                         
                          
                         VBE 
                       
                       RPTAT 
                     
                   
                   ) 
                 
               
             
           
         
       
     
       Finally: 
       [0058]    
       
         
           
             VREG 
             = 
             
               
                 VBE 
                  
                 
                     
                 
                  
                 
                   1 
                    
                   
                       
                   
                   · 
                   
                     ( 
                     
                       1 
                       + 
                       
                         RUP 
                         RSHIFT 
                       
                     
                     ) 
                   
                 
               
               + 
               
                 Δ 
                  
                 
                     
                 
                  
                 
                   VBE 
                    
                   
                       
                   
                   · 
                   
                     ( 
                     
                       RUP 
                       RPTAT 
                     
                     ) 
                   
                 
               
             
           
         
       
     
         [0059]    This equation is made of a VBE 1  term that decreases with temperature, and a ΔVBE term that increases with temperature. By calculating properly RUP, RPTAT, RSHIFT and N (that is embedded in ΔVBE), we can choose both the value of VREG and also compensate it in temperature. 
         [0060]    Other equivalent circuit embodiments are also can be utilized. Equivalent reference voltage and voltage regulator generators can be merged to provide temperature compensation at voltages above 1.2 V. 
         [0061]    It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the proposed methods and systems and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof. 
         [0062]    Other advantages will be recognized by those of ordinary skill in the art. The above detailed description of the disclosure, and the examples described therein, has been presented for the purposes of illustration and description. While the principles of the disclosure have been described above in connection with a specific device, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the disclosure.