Abstract:
A circuit comprising a plurality of input devices, a plurality of de-select devices and a selector device. The plurality of input devices may each be configured to receive an input signal. The plurality of de-select devices may each be configured to present an output in response (i) one of the plurality of inputs and (ii) one of a plurality of de-select signals. The selector device may be configured to present the plurality of de-select signals. In general, all but one of the de-select signals is active at a time.

Description:
FIELD OF THE INVENTION 
     The present invention relates to multiplexers generally and, more particularly, to a circuit and a method for implementing a multi-input multiplexer using Current Mode Logic (CML) or other swing logic. 
     BACKGROUND OF THE INVENTION 
     FIG. 1 a  illustrates a circuit  10  illustrating a conventional approach to implementing a multiplexer. The circuit  10  comprises a multiplexer  11  and a decoder  12 . The multiplexer  11  presents a first signal (i.e., a) or a second signal (i.e., b) in response to a control signal generated by the decoder  12 . The decoder  12  may generate the control signal in response to the select signal (i.e., SELO). FIG. 1 b  shows a more detailed diagram of the multiplexer  11 . The multiplexer  11  comprises a number of stages  13   a - 13   n.  The stage  13   a  comprises a number of transistor pairs  14   a - 14   b  and the stage  13   n  comprises a number of transistor pairs  16   a - 16   b.  Each of the transistor pairs receives a differential input signal (e.g., A and An or B and Bn, respectively). A number of select transistors  18   a - 18   n  respond to a number of control signals (i.e., SEL_A and SEL_B) generated by the decoder  12 . An example of the circuit  10  may be found in copending application, U.S. Ser. No. 09/182,556, filed on Oct. 19, 1998, entitled HIGH-SPEED, MULTIPLE-INPUT MULTIPLEXER SCHEME, which is hereby incorporated by reference in its entirety. The circuit  10  comprises N single ended select lines that are used for an N-input multiplexer. Only one select line is selected at a given time. This activates the selected stage  13   a - 13   n  while the non-selected stages are de-activated. 
     The circuit  10  is particularly useful for applications that have CML-type inputs and CML-type outputs. However, the circuit  10  may not be as useful where large output swings are required. For example, where the output swings higher than standard CML levels (e.g., 400 mV), the base collector may start leaking, and, in the extreme case, even forward bias. An additional limitation occurs when the input to the multiplexer  11  runs across two different power supplies. This means that potentially Vcb=Vswing+power supply drop (e.g., 0.4 v+0.2 v=0.6 v). Again, the base to collector junction could be forward biased. 
     Some of the disadvantages of the circuit  10  can be solved by adding an emitter follower on the input. However, such an approach generally requires three-level gating, which may not be practical for 3.3V supplies. 
     Referring to FIG. 2 a,  a circuit  50  is shown that can be used for instances where large output swings are required or an interface between two power supply zones is required. The circuit  50  generally comprises a multiplexer  52 , a decoder  54  and a boost circuit  56 . The multiplexer  52  is similar to the circuit  10 . The boost circuit  56  may comprise a transistor  58 , a transistor  60 , a transistor  62 , a transistor  64  and a number of current sources  66   a - 66   n.  A CML multiplexer can be used to do the functional selects followed by a swing boost circuit which contains an emitter follower (level shift) to keep the Vbc on the differential pair from forward biasing. 
     The circuit  50  has limitations associated with current, layout, stage distortion, noise induced distortion, matching, delay, and output swing variability. The additional circuitry generally increases the overall current use. The additional circuitry also generally increases the layout of the circuit  50  and increases distortion. Noise induced distortion can be caused if an additional buffer is far enough from the multiplexer  52 . Power supply noise could be an issue it both buffers do not experience identical noise environment. This could result in noise induced distortion when matching two data paths (such as in an output buffer application where a pump up signal is matched to a pump down signal) . The circuit  50  requires matching two buffers to two other buffers. The two stages will have a larger delay than desired. Output swing variability is difficult to achieve in the output level swing of the circuit  50  (or the circuit  10 ). 
     SUMMARY OF THE INVENTION 
     The present invention concerns a circuit comprising a plurality of input devices, a plurality of de-select devices and a selector device. The plurality of input devices may each be configured to receive an input signal. The plurality of de-select devices may each be configured to present an output in response (i) one of the plurality of inputs and (ii) one of a plurality of de-select signals. The selector device may be configured to present the plurality of de-select signals. In general, all but one of the de-select signals is active at a time. 
     The objects, features and advantages of the present invention include providing a multiplexer that may have reduced (i) current, (ii) layout, (iii) stage distortion, (iv) noise induced distortion, (v) matching delay, and (vi) output swing variability. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
     FIGS. 1 a  and  1   b  illustrate a conventional approach to the implementing multiplexer; 
     FIGS. 2 a  and  2   b  and  2   c  illustrate an alternate conventional approach to implementing a multiplexer; 
     FIGS. 3 a  and  3   b  illustrate a preferred embodiment of the present invention; and 
     FIGS. 4 a  and  4   b  illustrate an alternate embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 3 a,  a circuit  100  is shown in accordance with a preferred embodiment of the present invention. The circuit  100  generally comprises a multiplexer  102  and a decoder  104 . FIG. 3 b  illustrates a more detailed diagram of the multiplexer  102  that generally comprises a number of input devices  106   a - 106   n.  The input device  106   a  generally comprises a transistor  108   a,  a transistor  110   a  and a deselect circuit  112   a.  The deselect circuit  112   a  generally comprises a transistor  114   a,  a transistor  116   a  and a transistor  118   a.  The transistors  108   a  and  110   a  generally receive a differential data signal (e.g., A and An) at a first and a second gate. The source of the transistors  108   a  and  110   a  are generally connected to a supply voltage. The drains of the transistors  108   a  and  110   a  are generally connected to one of the current sources  120   a - 120   n  as well as to the deselect circuit  112   a . In one example, the drain of the transistor  108   a  may be connected to the gate of the transistor  116   a  and the drain of the transistor  100   a  may be connected to the gate of the transistor  118   a.  The drains of the transistors  116   a  and  118   a  are generally connected, along with the drain of the transistor  114   a , to the current source  120   b.    
     The transistor  114   a  generally receives a control signal (e.g., DESEL_A) that generally enables the transistor  114   a.  As a result, the transistors  116   a  and  118   a  generally shutdown the select circuit  106   a.  The input device  106   n  generally has similar components as the input device  106   a  (e.g.,  108   b,    110   b,    112   b,    114   b ,  116   b  and  118   b ). 
     An output signal OUTN may be presented through a resistor R 1  and an output signal OUTP may be presented through a resistor R 2 . The output signals OUTN and OUTP may be presented from the transistors  116   a  or  116   b  or the transistors  118   a  or  118   b , respectively. 
     The functionality of the multiplexer  102  is generally accomplished by stirring the current on top of a particular differential pair (e.g., the transistors  116   a  and  118   a ) instead of shutting off the current source (e.g.,  120   a - 120   n ) at the bottom as in some conventional approaches. Only one select line (e.g., desel_a, desel_b, etc.) is generally on at one time. By placing the current stir on top of the selected differential pair, enough head room may be present to level shift the inputs. The common collector structure may allow the sharing of the current path. 
     When the de-select signal (e.g., DESEL_A, DESEL_B, etc.) is high, current may be stirred away from the differential path, which may turn “off” the particular differential pair. An alternate implementation of the differential pair may be to connect one side at Vcc-Vbe and the other at Vcc. This allows a complete turn off of the non-selected differential pairs since the current travels to VCC through the select transistor. 
     When the de-select signal is low, the select transistor (e.g.,  114   a - 114   n ) is completely off and does not generally draw any current. This allows the selected differential pair to function as an emitter shifted buffer. 
     The present invention may provide a multiplexer that may (i) be used where the output of the CML is greater than standard CML swing, (ii) be used across power supplies, (iii) have a fast multiplexer functionality (e.g., does not relay on pass gates to charge or discharge nodes) and (iv) require only two levels of gates. 
     Referring to FIG. 4 a,  a circuit  100 ′ is shown illustrating an alternate embodiment of the present invention. The circuit  100 ′ comprises a multiplexer  102 ′ and a decoder  104 ′ that are similar to the multiplexer  102  and decoder  104  of the circuit  100  of FIG. 3 a.  The decoder has an additional input that receives a select signal (e.g., D/A SELECT) that may select between a digital and analog select signal presented to the multiplexer  102 ′. 
     An analog select circuit  150  may be connected to the input circuits  106   a  and  106   b.  The circuit  150  generally comprises a transistor  152 , a transistor  154  and a transistor  156 . The transistor  154  and the transistor  156  generally receive an input signal (e.g., B 1  and BN 1 ), respectively. The transistor  152  generally receives an analog de-select signal (e.g., DESEL_B 1 ). The circuit  150  may be used to add digital-to-analog capabilities to the multiplexer  102 ′. Similar to the circuit  100 , the circuit  100 ′ may have additional parallel stages that may be connected to increase the overall functionality of a multiplexer. 
     The circuit  100 ′ may (i) reduce current consumption, (ii) have a smaller layout, (iii) have less stage distortion, (iv) have less noise induced distortion, (v) have better matching, and (vi) have less delay. 
     The various components of the present invention may be modified to meet the design criteria of a particular implementation. For example, some or all of the NPN transistors may be implemented as NMOS or PMOS devices for operation with non-CML type logic. In another example, the resistor loads R 1  and R 2  may be implemented using active elements. Two or more branches may be selected (by de-selecting the current stir transistor) as long as the inputs are placed in parallel. This will increase the total current through the switching branch resulting in larger output swings. By selecting two or more branches, a swing select multiplexer digital to analog conversion may be implemented (e.g., a multiplexer which is capable of changing the output swing based on the select could be, but not necessary CMOS). 
     The present invention may be used to provide a multiplexer function, to provide a buffer across power supplies (e.g., a power supply buffer circuit) with increased output swing and/or to provide digital-to-analog conversion. One or more of the above functions may be combined which may result in a more efficient design. For example, a multiplexer with a buffering capability may be used in a wide range of applications. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.