Abstract:
This invention concerns improvements in the switching control of power or voltage into a load. Specifically it is concerned with a new time sequencing technique for the switching states of a four-switch configuration for the purpose of producing a three-state, pulse-duration-modulated output having a more ideal waveform and consequently better fidelity in the synthesis of a desired output signal. The new sequencing technique permits pulses of short time duration to be produced without requiring individual switches to recover quickly after having changed states from on to off or from off to on. This results in short pulses being produced with greater accuracy in the length of the pulse and consequently extends the useful dynamic range available at the output.

Description:
BACKGROUND OF THE INVENTION 
     Switching-mode power controllers (e.g., inverters, converters, switching-mode amplifiers) are used when voltage or current into a load is to be controlled with minimum loss of power of the controller. Frequently with a.c. outputs there is a desired output waveform. In d.c. to a.c. inverters, for example, it may be desirable that the output voltage into a load closely approximate some reference voltage, possibly sinusoidal. When the output is synthesized by a sequence of rectangular pulses as with pulse-duration modulation for example, the fidelity to which the output waveform conforms to the desired waveform depends on many factors, such as the frequency of switching, the particular modulating scheme chosen, the physical limitations of the switching devices, and the characteristics of any incorporated output filtering. 
     When the output signal from the switching mode power controller must span a relatively large dynamic range, such as might be necessary when the reference signal is a music or voice signal, the required output pulses from the power switches become very short in duration at the low power levels. In the past the ability to make pulses of short duration and therefore the ability to cover a large dynamic range has been limited by the finite rise, fall, and recovery times of the power switches themselves. 
     SUMMARY OF THE INVENTION 
     This invention presents a new time sequence technique and the circuit means for producing a three-state, pulse-duration-modulated output from a bridge configuration of controllable switches in such a way as to overcome some of the minimum pulse-length limitations of the power switches and thus to improve the useful dynamic range. 
     Basically, the invention is embodied in a circuit for producing a three-state (+E, 0, and -E) PDM (pulse duration modulation) output, and includes 
     A. SWITCHES S 1  and S 3  connected in series and across a voltage source, S 1  and S 3  being in opposite states of conduction, 
     B. SWITCHES S 2  and S 4  connected in series and across the voltage source, S 2  and S 4  being in opposite states of conduction, 
     C. A LOAD WITH ONE END CONNECTED WITH THE COMMON POINT BETWEEN SWITCHES S 1  and S 3  and the other end connected with the common point between switches S 2  and S 4 , and 
     D. MEANS TO PRODUCE A SHORT PULSE OF INTERVAL ΔT ACROSS THE LOAD BY CONTROLLING SAID SWITCHES TO CAUSE THE SWITCHES OF FIRST ONE PAIR S 1  and S 2  and then the other pair S 3  and S 4  to switch between OFF states. In other words, we provide means to produce a short pulse of interval Δt across the load by controlling the switches to switch from one of the two states which produce 0 voltage across the load (S 1  ON and S 2  ON, or S 3  ON and S 4  ON), to an intermediate state where voltage is produced across the load (S 1  ON and S 4  ON, or S 3  ON and S 2  ON) and then to other 0 voltage state. 
     As will be seen, such means includes control apparatus to cause S 1  and S 2  (or S 3  and S 4 ) to shift from ON state to OFF state by initiating shifting of first one and then the other of S 3  and S 4  (or S 1  and S 2 ) to ON state at sequential initiation times defining the interval Δt. Also, Δt is controllable, as will appear. In this regard, when S 1  is ON, S 3  will be OFF; and when S 1  is OFF, S 3  will be ON. The four states of conduction are: S 1  ON and S 2  ON; S 1  OFF and S 2  OFF; S 1  OFF and S 2  ON; and S 1  ON and S 2  OFF. The first two of these states produce zero volts across the load, and the last two of these states produce voltage across the load. Accordingly, there is provided control apparatus to cause a shift from a state where S 1  and S 2  (or S 3  and S 4 ) are both ON to the state where S 3  and S 4  (or S 1  and S 2 ) are both ON by first turning one and then the other of S 3  or S 4  (or S 1  or S 2 ) to ON states at sequential initiation times defining the interval Δt. 
     It is therefore an object of this invention to generate a three-state switched waveform by using a four-switch bridge configuration and alternating between the two different conditions which produce zero volts across the load, and referred to as &#34;alternating zero&#34; modes. 
     Another object of this invention is to extend the &#34;alternating zero&#34; principle to the circuit means using the bridge configuration in conjunction with a balancing transformer to provide single-ended, three-state output. 
     These and other objects and advantages of the invention, as well as the details of illustrative embodiments, will be more fully understood from the following description and drawings in which: 
    
    
     DRAWING DESCRIPTION 
     FIG. 1 shows the basic diagram of the four-switch bridge output circuit and FIG. 1a shows sequences of switch states for both the invention and for the prior art; 
     FIG. 2 shows one circuit means of the invention; 
     FIG. 3 shows the switching states and waveforms which correspond to the circuitry of FIG. 2; 
     FIG. 4 illustrates circuit diagram of another form of the invention which uses a balancing transformer to provide single-ended output; 
     FIG. 5 shows the switching states and waveforms which corresponds to the circuitry of FIG. 4. 
    
    
     DETAILED DESCRIPTION 
     A comparison of the invention to the prior art can be made with the help of FIG. 1. In FIG. 1 controllable switches S 1  through S 4  in bridge configuration are connected to d.c. voltage source 1 to supply power to load 2. The controlled switches may typically be power transistors. S 1  and S 3  are connected in series across source 1 as are S 2  and S 4 . Load 2 connects between the common point of S 1   and S 3  and the common point of S 2  and S 4 . Voltages V 1  and V 2  are the voltages existing across switches S 1  and S 2  respectively. S 1  and S 3  are in opposite states of conduction (i.e., conducting or nonconducting) and similarly S 2  and S 4  are in opposite state of conduction. The voltage V L  across load 2 is the difference of V 1  and V 2 . 
     By the prior art, the three voltage states of +E, 0, or -E across the load are produced by the following switch states; (1) +E corresponds to S 3  ON and S 2  ON; (2) 0 volts corresponds to S 1  ON and S 2  ON; and (3) -E volts corresponds to S 1  ON and S 4  ON. A positive pulse is produced across the load by holding S 2  On and switching S 3  from OFF to ON to OFF. A negative pulse is produced across the load by holding S 1  ON and switching S 4  from OFF to ON to OFF. Note that in order to make a short duration positive pulse across the load, S 3  must turn on and back off rapidly (S 1  must turn off and back on rapidly). This results in the previously described problems. 
     In the present invention, use is made of the fact that there are two different sets of switch states which produce 0 voltage across the load: (1) S 1  ON and S 2  ON, or (2) S 3  ON and S 4  ON. Short pulses can be produced by alternating between these two zero voltage states. A short positive pulse can be produced for example by the following sequence of states: (1) S 1  ON and S 2  ON; (2) S 3  ON and S 2  ON; and (3) S 3  ON and S 4  ON. Note that the pulse was produced by each switch making only one state transition with no recovery required. The switches need only recover in the time between pulses. Shown in FIG. 1a are the sequences of switch states for which ideally the same output waveform is produced by the prior art and by the invention. With real switches where the recovery times are finite, the new technique enables more accurate production of narrow pulses. 
     Referring to FIG. 2, there is illustrated a four-switch bridge-configuration power-output stage connected to d.c. voltage source 1 (voltage E) and controlled by control logic 11. Each of the power switches consists of a power transistor and a corresponding drive circuit. For example, S 1  includes the power transistor Q 1  (which could represent several paralleled transistors) and drive circuit DR1. Drive circuits per se as represented by DR1 are well-known art (power supplies for the drive circuits as well as for the logic circuits have been omitted from the diagram). Across each of the power switches is a corresponding diode (D 1  through D 4 ). These diodes permit reactively generated currents to flow against the normal conduction through the switches. 
     The control logic 11 comprises triangular wave generator 9, comparator amplifiers 4 and 6, unity-gain inverting amplifier 8, and logical inverters 5 and 7 connected as shown. All of these functional circuit units are available as integrated circuits. An example of the triangular wave generator is the Intersil model 8038 Precision Waveform Generator and Voltage Controlled Oscillator. The input signal V s  is a voltage reference waveform to which the voltage V 4  across load 2 is to be made proportional. The source of V s  in the case of a d.c. to a.c. inverter application would be typically from a sinusoidal waveform generator added to the inverter package (e.g., the Intersil model 8038 Waveform Generator can provide sinusoidal waveforms). When the power controller functions as an amplifier, V s  is the signal-to-be-amplified. 
     The frequency of the triangular wave V t  (seen in FIG. 3) output of generator 9 is typically chosen to be several times the highest frequency to be encountered for the signal V s . It is sometimes desirable to synchronize the triangular wave with the input signal. This synchronization is represented by dashed-line 10 in FIG. 3. There are many well-known suitable synchronization circuits (see for example the manufacturer&#39;s application notes on the intersil Model 8038 Waveform Generator) usable at 10. 
     Triangular wave V t  is compared to V s  by comparator 4 and to -V s  by comparator 6. The signal -V s  is produced by unity-gain inverting amplifier 8. The logical output of comparator 4 determines the conduction state of switch S 1  (S 1  is ON when V s  is more positive than V t ). Logical inverter 5 causes S 3  to be in a conduction state opposite to S 1 . Similarly, the logical output of comparator 6 determines the conduction state of switch S 2  (S 2  is On when the signal -V s  is more positive than V t ). Logical inverter 7 causes S 4  to be in a conduction state opposite to S 2 . 
     Voltage V 1  and V 2  are the voltages across switches S 1  and S 2  respectively. The voltage V 3 , which is the difference between V 1  and V 2 , is applied to the load through filter 3. The filter, if needed, is used to attenuate the higher-frequency components (relative to the frequency of V s ) which are approximately twice (and higher) the frequency of V t . Typically, the filter is a simple L-C low-pass filter (capacitor across the load and inductors between load and the output stage). In some narrow-band applications the filter is sometimes a simple series-resonant L-C circuit connected between the load and the output stage. The filter output is similar in waveform to V s . 
     FIG. 3 illustrates the switching states and waveforms which correspond to the circuit of FIG. 2. For clarity, V s  is shown as sinusoidal and V t  is shown synchronized with V s . Generally, the only restriction imposed on V s  is that the peak amplitude of V s  be less than the peak amplitude of V t  (this is to avoid a relatively large amount of distortion from occurring in the output). The intersections of V s  and -V s  with V t  are indicated in FIG. 3. The output voltage V 3  is the difference between V 1  and V 2 . Filtering applied to V 3  would produce a waveform approximating reference signal V s . 
     Because voltages V 1  and V 2  vary with respect to the common potential, the load must be isolated electrically from either the common or the switching bridge. When the load circuit cannot be electrically isolated from common and the V s  (and therefore V L ) does not contain a d.c. component, isolation may be provided by coupling V 3  to the load through a transformer in the usual way. In this regard, the box 3 labeled &#34;filter&#34; may be considered as alternately or inclusively representing a transformer. When V s  does contain a d.c. component, the circuit shown in FIG. 4 can be used. 
     For the FIG. 4 circuit, the bridge configuration of switches S 1  through S 4  is connected across two d.c. power supplies 14, series connected. The common connection 15 between the two equal power supplies is the common line for the load circuit. The output to the load is taken from the center-tap of balancing transformer 16 which connects to each side of the bridge. The operation of the control logic 11 is the same as previously described, except that the output of comparator 6 now goes to S 4  and the output of inverter 7 now goes to S 2  (i.e., the ON--OFF states of S 2  and S 4  have been reversed when compared to the previous circuitry). The output voltage V 7  is the average between voltage V 5  and V 6  ##EQU1## where V 5  is the voltage from the common line 15 to the connecting point between S 1  and S 3 , and V 6  is the voltage from the common line 15 to the connecting point between S 2  and S 4 . As in the case for the circuitry of FIG. 2, a filter 12 is used typically to attenuate the high-frequency components from the three-state output voltage V 7  to give a waveform across the load 13 which more closely approximates the reference signal V s . 
     FIG. 5 shows the switching states and waveforms which correspond to the circuit of FIG. 4. As in the previous case V s  is shown as sinusoidal and V t  is shown synchronized with V s . 
     From the foregoing, it is clear that the basic circuit of FIG. 2 includes: 
     a. switches S 1  and S 3  connected in series and across a voltage source, S 1  and S 3  being in opposite states of conduction, 
     b. switches S 2  and S 4  connected in series and across the voltage source, S 2  and S 4  being in opposite states of conduction, 
     c. a load connected with a common point between switches S 1  and S 3  and also connected with a common point between switch S 2  and S 4 , and 
     d. means to produce a short pulse of interval Δt across the load by controlling the switches to switch from one of the two states which produce 0 voltage across the load (S 1  ON and S 2  ON, or S 3  ON and S 4  ON), to an intermediate state where voltage is produced across the load (S 1  ON and S 4  ON, or S 3  ON and S 2  ON) and then to other 0 voltage state. 
     Further, such means typically may include control apparatus to cause a shift from a state where S 1  and S 2  (or S 3  and S 4 ) are both ON to the state where S 3  and S 4  (or S 1  and S 2 ) are both ON by first turning one and then the other of S 3  or S 4  (or S 1  or S 2 ) to ON states at sequential initiation times defining the interval Δt.