Abstract:
A nonvolatile memory device includes an array of rows and columns of memory cells and a plurality of word lines and bit lines associated with the memory cells. The memory device further includes a word line booster circuit coupled with the word lines for supplying a selected word line with a specific voltage as a drive voltage during an operation of the memory device. The word line booster circuit includes a first boosting capacitor and a second boosting capacitor connected in parallel to generate a boosting voltage and a first precharge circuit for precharging the first and second boosting capacitors. The word line booster circuit further includes a third boosting capacitor operatively connected to the first and second boosting capacitors via a charge-sharing transistor, the third boosting capacitor being connected to one end of a load resistor to generate an output signal at the other end of the load resistor when the charge sharing transistor is enabled.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to Chinese Patent Application No. 200810040285.6, filed Jul. 2, 2008, commonly assigned, and incorporated herein by reference for all purposes. 
     BACKGROUND OF THE INVENTION 
     The present invention generally relates to semiconductor integrated circuits and more particularly, the present invention provides a word line booster circuit to drive word lines for non-volatile memory devices. 
     A memory device includes an array of memory cells that are arranged in rows and columns. Parallel data transfer lines or bit lines are provided and connected to the current carrying electrodes of cell transistors in columns of memory cells. Parallel control lines or word lines are associated with the control electrodes of rows of memory cells. When a word line is activated, and a certain bit line is selected, the transistor in a selected memory cell is rendered conductive to transfer digital information from the cell capacitor to a corresponding bit line therein. The digital information is thus read from the selected memory cell. 
     A high voltage that is supplied via the word lines to the control gates of memory cell transistors should be arranged to be potentially greater in magnitude than the information voltage of high level on the bit lines. The difference between the voltages is necessary in order to compensate for a potential drop of a word line drive voltage due to the threshold voltages of the memory cell transistors. The high voltage is generated using a specific capacitor that is arranged within a word line booster circuit. The capacitor may act as the “booting” or bootstrap capacitor for producing a word line drive voltage that is higher than the power supply voltage Vcc of DRAM. Generally, the bootstrap capacitor is precharged at its one electrode toward the power supply voltage and the other electrode thereof is initially at the ground potential, and then driven to rise up to the power supply voltage, thereby producing the word line drive voltage of a suitable potential level with such a voltage booting system. 
     Generally, word line booster circuit generates word line voltage when address transition detection signal is triggered by address change. During write mode, write control signal from logic controller generates related signals to control charge pump. The pumping voltage generated by the charge pump drives row decoders and column decoders through the high voltage switch. During read mode, word line voltage from word line booster is provided instead of the pumping voltage. 
     In case of flash memory EEPROM, word line bias of around 9V and bit line bias of around 5V are required for the purpose of programming data into memory cells using the hot electron injection mechanism. During read mode, word line bias of around 3V and bit line voltage of about 1V are required to read information from the programmed cells or erased cells. For these memory operations, a word line booster circuit which generates a stable word line voltage with little variation in the power supply voltage having low power consumption is desired for manufacturing low power high voltage nonvolatile memory devices. 
     From the above, it is seen that an improved word line booster circuit with little variation in the power supply voltage during read mode or verify mode of the memory operation is desired. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention is generally related to semiconductor integrated circuits and more particularly, the present invention provides a word line driver circuit to drive word lines during read mode or data verification mode for non-volatile memory devices. 
     In a specific embodiment, a nonvolatile memory device includes an array of rows and columns of memory cells and a plurality of word lines and bit lines associated with the memory cells. The memory device further includes a word line booster circuit coupled with the word lines for supplying a selected word line with a word line voltage during an operation of the memory device, wherein the word line booster circuit includes a first boosting capacitor and a second boosting capacitor connected in parallel each other and a first precharge circuit for precharging the first boosting capacitor and the second boosting capacitor. The word line booster circuit further includes a third boosting capacitor operatively connected to the first boosting capacitor and the second boosting capacitor via a charge-sharing transistor, the third boosting capacitor being connected to one end of a load resistor to generate an output signal at the other end of the load resistor to be used as the word line voltage when the charge sharing transistor is enabled and a second precharge circuit for precharging the third boosting capacitor. In addition, the word line booster circuit includes a high voltage detector circuit to generate a detecting signal when the word line voltage reaches a target voltage during read mode of the nonvolatile memory device and a clock control circuit adapted to enable the charge sharing transistor and to disable one of the first boosting capacitor and the second boosting capacitor upon receiving a control signal from the address transition detector and the detecting signal from the voltage detector. 
     In another embodiment, the invention provides a nonvolatile memory device including an array of rows and columns of memory cells and a plurality of word lines and bit lines associated with the memory cells. The memory device further includes a word line booster circuit coupled with the word lines for supplying a selected word line with the specific voltage as a drive voltage during an operation of the memory device, wherein the word line booster circuit includes a first boosting capacitor and a second boosting capacitor connected in parallel each other adapted to generate a boosting voltage and a first precharge circuit for precharging the first boosting capacitor and the second boosting capacitor. The world line booster circuit further includes a third boosting capacitor operatively connected to the first boosting capacitor and the second boosting capacitor via a charge-sharing transistor, the third boosting capacitor being connected to one end of a load resistor to generate an output signal at the other end of the load resistor when the charge sharing transistor is enabled and a high voltage detector to generate a detecting signal in response to a control signal from an address transition detector and the output signal generated by the third boosting capacitor and load resistor. In addition, the word line booster circuit includes a clock control circuit adapted to enable the charge sharing transistor and to disable one of the first boosting capacitor and the second boosting capacitor upon receiving the control signal from the address transition detector and the detecting signal from the voltage detector and a discharge circuit to discharge the boosting voltage at a node connected to the third boosting capacitor. 
     Many benefits are achieved by way of embodiments of the present invention over conventional techniques. The present invention offers significant unobvious advantages in the fabrication of nonvolatile memory device having an improved short channel effect and leakage characteristics. Depending upon the embodiment, one or more of these benefits may be achieved. These and other benefits will be described in more throughout the present specification and more particularly below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Exemplary embodiments of the invention are more fully described in detail with reference to the accompanied drawings. The invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure is thorough and complete, and to convey the concepts of the invention to those skilled in the art. 
         FIG. 1  is a simplified block diagram illustrating a conventional flash memory device; 
         FIG. 2  is a simplified diagram illustrating a conventional word line booster circuit; 
         FIG. 3  is a simplified diagram illustrating a word line booster circuit according to an embodiment of the present invention; 
         FIG. 4  is a simplified diagram illustrating an embodiment of the precharge circuit; 
         FIG. 5  is a simplified diagram illustrating an embodiment of the voltage detector; 
         FIG. 6  is a simplified diagram illustrating an example the discharge circuit; 
         FIG. 7  is a simplified diagram illustrating an embodiment of the clock control circuit; 
         FIG. 8  is a simplified diagram illustrating an output voltage of the word line booster circuit vs. power supply voltage. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention generally relates to semiconductor integrated circuits and more particularly, the present invention provides a word line booster circuit to drive word lines during read mode or data verification mode for non-volatile memory devices. It is understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims. 
       FIG. 1  is a simplified block diagram illustrating a conventional flash memory device. 
     Logic controller including state machine  101  controls overall circuit blocks with input addresses and data. Address bus signals are input to address buffer  107  and address transition detector (ATD) circuit  105 . ATD circuit  105  generates related signals when there is an address transition in a read mode operation to control the memory access. Also, ATD  105  generate its output signal Vatd to control a word line booster  103 . Word line booster  103  generates word line voltage Vwl when ATD  105  outputs a signal Vatd that is triggered by an address change. During write mode, a write control signal Vwr from Logic Controller  101  generates related signals to control a charge pump  102 . The pumping voltage Vpp drives a row decoder  113  and a column decoder  115  through the High Voltage Switch  111 . During read mode, word line voltage Vwl from word line booster  103  is provided instead of the pumping voltage Vpp as shown in  FIG. 1 . 
     In case of flash memory EEPROM, word line bias of around 9V and bit line bias of around 5V are used to program data into memory cells using the hot electron injection mechanism. During the read mode, word line bias of around 3V and bit line voltage of about 1V are used to read information from the programmed cells or erased cells. Flash memory array  117  contains memory cells and decoder circuits. 
       FIG. 2  is a simplified diagram illustrating a conventional word line booster circuit  103  shown in  FIG. 1 . The function of each circuit block and element is as follows. The “EN” signal from ATD block  105  of  FIG. 1  is input to Clock Control Circuit  201 . Capacitors C 2 _ 1  and C 2 _ 2  are boosting capacitors and capacitor CL represents total load capacitance including all output junction capacitance and signal capacitances in driving the word lines during read mode. The precharge circuit blocks  203  and  205  are adapted to precharge nodes n 2 _ 2  and n 2 _ 4  before boosting these nodes. 
     Let&#39;s assume these capacitor nodes are precharged at Vcc (power supply voltage). When “EN” signal becomes “H” (enabled state), a potential increase at node n 2 _ 5  causes capacitor C 2 _ 1  to boost the voltage at node n 2 _ 2  to Vcc+αVcc (α: coupling coefficient). Responding to the increased node voltage at node n 2 _ 2 , PMOS transistor M 2  turns on, causing voltage at node n 2 _ 3  to be increased toward the voltage at node n 2 _ 2  by charge sharing. This charge-shared voltage at node n 2 _ 3  then causes load capacitors C 2 _ 2  and CL to bootstrap. Resistor R 2 _ 1  represents output resistance including signal loadings. From the above, output voltage Vout of the word line booster circuit  100  can be obtained as follows:
 
 V out= Vcc+C 2 — 2/( CL+C 2 — 2)×[( C 2 — 1 +C 2 — 2 //CL )]×( Vcc+αVcc )
 
     As shown above equation, output voltage Vout of the word line booster circuit is generally dependent on power supply voltage Vcc. However, it is desirable that more stable bias voltage be provided to the word lines. An improved word line booster circuit is described according to an embodiment of the present invention with reference to  FIG. 3 . 
       FIG. 3  is a simplified diagram illustrating a word line booster circuit according to an embodiment of the present invention. Referring to  FIG. 3 , voltage detector  309  is connected to output terminal of word line booster circuit  300  and its output is fed back to clock control circuit  301  to control output voltage Vout of the word line booster circuit  300 . In the present embodiment, capacitors C 3 _ 1  and C 3 _ 2  constitute boosting capacitors controlled by clock control circuit  301 . The “EN” signal coming from ATD block  105  of  FIG. 1  is input to the clock control circuit  301 . Load capacitor CL represents the sum of all output junction capacitances and signal capacitances in driving the word lines during read mode. 
     The precharge circuits  303  and  305  precharge nodes n 3 _ 5  and n 3 _ 7  before boosting these nodes. For the purpose of explanation, let&#39;s assume that these node voltages are precharged at Vcc (power supply voltage). When EN becomes “H” (enable state), voltage at nodes n 3 _ 3  and n 3 _ 4  causes capacitors C 3 _ 1  and C 3 _ 2  to boost the node voltage of n 3 _ 5  up to Vcc+αVcc (α: coupling coefficient). And PMOS transistor M 3  is turned on by the signal from the clock control circuit (see  FIG. 7 ). The node voltage at n 3 _ 5  causes charge sharing between the nodes n 3 _ 5  and n 3 _ 6  to occur. However, if the output signal DET of the voltage detector  309  is “L”, the node voltage at node n 3 _ 4  is “L” (see  FIG. 7 ), discharging capacitor C 3 _ 2 . 
     This charge-shared voltage at node n 3 _ 6  causes capacitor C 3 _ 3  and CL to boost output voltage Vout. Resistor R 3 _ 1  represents total resistance value at output node. From the above, Vout can be obtained as follows: Vout=Vcc+C 3 _ 3 /(CL +C 3 _ 3 )×[C 3 _ 1 +C 3 _ 2 /(C 3 _ 1 +C 3 _ 2 +C 3 _ 3 //CL)]×(Vcc+αVcc). As the equation indicates, the amount of charge coupling can be more flexibly adjusted by employing additional boosting capacitors controlled by clock control circuit  301 . Depending on the target output voltage Vout of the word line booster circuit, more than two boosting capacitors can be employed and coupled together. 
       FIG. 4  is a simplified diagram illustrating an embodiment of the precharge circuit  303  or  305  shown in  FIG. 3 . The signal “ENPRE” is controlled by the clock control circuit  301  shown in  FIG. 3 . When this signal is “L”, PMOS transistor M 4 _ 2  is turned on and VPRE node voltage goes up to boosting voltage, turning off PMOS M 4 _ 3 . If ENPRE signal is “H”, NMOS transistor M 4 _ 1  is turned on, causing node voltage Vn 4 _ 1  to be pulled down to 0V. Then, PMOS M 4 _ 3  is turned on and node voltage VPRE is precharged to Vcc. In the precharge circuit shown in the present embodiment, there is no threshold voltage loss across PMOS transistor M 4 _ 3 . Therefore, node voltage VPRE can be precharged up to full Vcc, which is not achieved by conventional precharge circuit composed of single NMOS transistor, in which case node voltage VPRE can be precharged only to Vcc−Vt because of Vt loss across NMOS transistor. 
       FIG. 5  is a simplified diagram illustrating an embodiment of the voltage detector  309  shown in  FIG. 3 . Referring to  FIG. 3  and  FIG. 5 , output voltage Vout to be used as a word line voltage is input to a source electrode of PMOS transistor M 5 _ 1 , which is connected to another PMOS transistor M 5 _ 2  in series, and the gate and drain nodes of these transistors are diode-connected as shown in  FIG. 5 . The drain node of PMOS M 5 _ 2  is connected to NMOS transistors M 5 _ 3  and M 5 _ 4  in series, and also connected to a gate electrode of NMOS transistor M 5 _ 5 . Voltage at node n 5 _ 2  is determined by the condition of PMOS transistors M 5 - 1 , M 5 _ 2  and NMOS transistor M 5 _ 3 . Transistor M 5 _ 4  is adapted to cut off the current at the inactive mode. The voltage at node n 5 _ 2  controls NMOS transistor M 5 _ 5 . NMOS transistors M 5 _ 5  and M 5 _ 6  are in a cascade arrangement. The resistor R 5  is a load resistor for the cascode amplifiers I 5 _ 1  and I 5 _ 2 . The voltage at node n 5 _ 2  is equal to Vout−2Vt of PMOS transistors M 5 _ 1  and M 5 _ 2 . The output signal DET of the voltage detector  309  is input to the clock control circuit  301 . As illustrated in  FIG. 7 , this DET signal is used to disable the boosting capacitor C 3 _ 2  when one of the EN and DET signals is “L” level. 
     When Vout node is initially Vcc (power supply voltage), the initial voltage at node n 5 _ 4  is “H” (M 5 _ 4  is turned on) and the voltage at node n 5 _ 2  is around threshold voltage of NMOS transistor M 5 _ 3  or Vtn. After boosting (EN is “H”, transistor M 5 _ 6  is turned on) from booster circuitry of  FIG. 3 , Vout voltage is increased above Vcc. As the Vout voltage increases, the voltage at node n 5 _ 2  also increases above threshold voltage of NMOS transistor M 5 _ 3 , turning M 5 _ 3  and M 5 _ 5  on. Thus, the voltage at node n 5 _ 4  is pulled down to ground level. DET signal then goes to “L”. Since the voltage at node n 5 _ 4  is “L”, NMOS transistor M 5 _ 4  is turned off. NMOS transistor M 5 _ 6  is controlled by EN signal as shown in  FIG. 3 . Voltage detector  309  output signal DET is fed back to clock control circuit to control booster circuit output voltage Vout. 
       FIG. 6  is a circuit diagram illustrating an example the discharge circuit  307  shown in  FIG. 3 . The signal ENDIS is generated by inverting the signal EN as illustrated in  FIG. 7  and is controlled by the clock control circuit  301  shown in  FIG. 3 . The voltage at node n 3 _ 6  shown in  FIG. 3  is discharged through the NMOS transistor M 6  after boosting. 
       FIG. 7  is a simplified circuit diagram illustrating an embodiment of the clock control circuit  301  shown in  FIG. 3 . The signal “EN” is connected to inverter I 7 _ 6  and NAND gate I 7 _ 4  to control the boosting clock at nodes n 3 _ 3  and n 3 _ 4  shown in  FIG. 3 . At the same time, it is input to inverter I 7 _ 1  to generate signal “ENDIS”. This ENDIS signal enables the discharge circuit shown in  FIG. 6  as mentioned above. The output signal of inverter I 7 _ 3  at node n 3 _ 1  controls PMOS transistor M 3  as shown in  FIG. 3 . 
       FIG. 8  is a diagram illustrating an output voltage Vout of the word line booster circuit vs. power supply voltage Vcc when the present invention is applied. Vread is a target word line voltage generated by the word line booster circuit for sensing data from nonvolatile memory cells during read mode or verify mode. A graph  801  illustrates a conventional boosting scheme. A graph  803  illustrates a boosting scheme according to one embodiment of the present invention. As illustrated in  FIG. 8 , a stable word line voltage is obtained from a wide range of power supply voltages. 
     While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.