Abstract:
The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual ONO floating gates with an isolation spacer between floating gates. Processes for making the memory device according to the invention are also provided.

Description:
RELATED APPLICATION 
     This application is based on Provisional Application Serial No. 60/181,479 filed Feb. 10, 2000, which is incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to semiconductor memory devices. 
     BACKGROUND OF THE INVENTION 
     Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), and electrically erasable programmable read only memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse. 
     Typically, an EEPROM device includes a floating-gate electrode upon which electrical charge is stored. The floating-gate electrode overlies a channel region residing between source and drain regions in a semiconductor substrate. The floating-gate electrode together with the source and drain regions forms an enhancement transistor. By storing electrical charge on the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively high value. Correspondingly, when charge is removed from the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively low value. 
     The threshold level of the enhancement transistor controls current flow through the transistor by application of appropriate voltages to the gate and drain. When the threshold voltage is high, no current will flow through the transistor, which is defined as a logic 0 state. Correspondingly, when the threshold voltage is low, current will flow through the transistor, which is defined as a logic 1 state. This feature is identical to FET operation, except the floating gate in an EEPROM FET alters the threshold voltage dependent upon the presence of charge within the floating gate. 
     One type of EEPROM device utilizes a polycrystalline silicon or metal layer for the floating-gate electrode. Electrons are transferred to the floating-gate electrode through a dielectric layer overlying the channel region of the enhancement transistor. The electron transfer is initiated by either hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage potential is applied to the floating-gate by an overlying control-gate electrode. 
     The EEPROM device is programmed by applying a high positive voltage to the control-gate electrode, and a lower positive voltage to the drain region which transfers electrons from the channel region to the floating-gate electrode. The EEPROM device is erased by grounding the control-gate electrode and applying a high positive voltage through either the source or drain region of the enhancement transistor. Under erase voltage conditions, electrons are removed from the floating-gate electrode and transferred into either the source or drain regions in the semiconductor substrate. 
     Another type of EEPROM device utilizes an oxide-nitride-oxide (ONO) layer for the fabrication of the floating-gate electrode. During programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO structure. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer and become trapped in the silicon nitride layer. 
     Electrons are trapped near the drain region because the electric fields are the strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the silicon nitride layer near the source region. Because silicon nitride is not electrically conductive, the charge introduced into the silicon nitride layer tends to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in discrete regions within a single continuous silicon nitride layer. 
     Non-volatile memory designers have taken advantage of the localized nature of electron storage within a silicon nitride layer and have designed memory circuits that utilize two regions of stored charge within the ONO layer. This type of non-volatile memory device is known as a two-bit EEPROM. 
     The two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left and right bit is stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two-bits to be programmed and read simultaneously. The two-bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions. The structure and operation of this type of memory device is described in a PCT application having the International Publication Number of WO/07000 entitled “TWO BIT NON-VOLATILE ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELL UTILIZING ASYMMETRICAL CHARGE TRAPPING”, the contents of which are fully incorporated herein by reference. 
     The present invention is directed to the type of memory cell described above that utilize ONO to achieve two-bit operation. Programming of such cells generates significant electrical fields that influence programming of adjacent cells. This can alter the programmed state of a cell adjacent to the one being programmed, or can draw charge to the center of the ONO layer between the opposing bit storage regions where it is extremely difficult, if not impossible, to remove. Therefore, a desirable two-bit ONO memory device would have improved isolation between bits stored on the same device. 
     SUMMARY OF THE INVENTION 
     A process for making an array of two-bit floating gate transistors for a semiconductor memory device, comprising: 
     forming the array of two-bit floating gate transistors having floating gates partially overlying parallel rows of bit-line oxide; and, 
     forming isolation spacers between the parallel rows of bit-line oxide that divide the floating gates. 
     According to an aspect of the invention, a process is provided for making an array of two-bit floating gate transistors for a semiconductor memory device, comprising: 
     providing a silicon wafer substrate having parallel rows of bit-line oxide and a floating gate ONO layer on said silicon wafer substrate and said bit-line oxide, said floating gate ONO layer comprising a first silicon dioxide layer, a silicon nitride layer on said first silicon dioxide layer, and a second silicon dioxide layer on said silicon nitride layer; 
     depositing a hard mask layer on said floating gate ONO layer; 
     creating a multitude of openings in said hard mask layer centered upon said rows of bit-line oxide and centered between said rows of bit-line oxide; 
     depositing a spacer layer on said hard mask layer; 
     reducing said spacer layer to spacers within said openings by anisotropically etching said spacer layer; 
     etching through said second silicon dioxide layer and said silicon nitride layer within said openings, thereby exposing said first silicon dioxide layer; 
     at least partially filling said openings with third silicon dioxide; and, 
     removing said hard mask layer and said spacers and leaving at least a portion of said third silicon dioxide at least partially filling said openings. 
     According to a further aspect of the invention, a process is provided for making a semiconductor device having an array of two-bit floating gate transistors, comprising: 
     providing a silicon wafer substrate having parallel rows of bit-line oxide and a floating gate ONO layer overlying said silicon wafer substrate and said bit-line oxide, said ONO layer comprising a first silicon dioxide layer, a silicon nitride layer on said first silicon dioxide layer, and a second silicon dioxide layer on said silicon nitride layer; and, 
     creating a multitude of isolated floating gates from said ONO layer arranged such that each said two-bit floating gate transistor has two of said isolated floating gates, one for each bit, comprising 
     depositing a hard mask layer on said ONO layer, 
     creating a multitude of openings in said hard mask layer centered upon said rows of bit-line oxide and centered between said rows of bit-line oxide, 
     depositing a spacer layer on said hard mask layer, 
     reducing said spacer layer to spacers within said openings by anisotropically etching said spacer layer, 
     etching through said second silicon dioxide layer and said silicon nitride layer within said openings, thereby exposing said first silicon dioxide layer, 
     at least partially filling said openings with third silicon dioxide, and 
     removing said hard mask layer and said spacers and leaving at least a portion of said third silicon dioxide at least partially filling said openings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates, in cross-section, a portion of a semiconductor substrate containing a dual polysilicon floating-gate two-bit transistor in accordance with the invention; 
     FIG. 2 illustrates, in plan, a portion of a semiconductor substrate containing a dual polysilicon floating-gate two-bit transistor in accordance with the invention; 
     FIG. 3 illustrates a cross-sectional view of a stage of a process for making a two bit memory device according to an aspect of the invention; 
     FIG. 4 illustrates a cross-sectional view of a subsequent stage of the process; 
     FIG. 5 illustrates a cross-sectional view of a subsequent stage of the process; 
     FIG. 6 illustrates a cross-sectional view of a subsequent stage of the process; 
     FIG. 7 illustrates a cross-sectional view of a subsequent stage of the process; 
     FIG. 8 illustrates a cross-sectional view of a subsequent stage of the process; 
     FIG. 9 illustrates a cross-sectional view of an alternative embodiment according to an aspect of the invention; 
     FIG. 10 illustrates a cross-sectional view of a subsequent stage resulting from the FIG. 9 embodiment; 
     FIG. 11 illustrates a cross-sectional view of an alternative embodiment according to an aspect of the invention; 
     FIG. 12 illustrates a cross-sectional view of a subsequent stage resulting from the FIG. 11 embodiment; 
     FIG. 13 illustrates a cross-sectional view of an alternative embodiment according to an aspect of the invention; and, 
     FIG. 14 illustrates a cross-sectional view of a subsequent stage resulting from the FIG. 13 embodiment. 
    
    
     DETAILED DESCRIPTION 
     Various aspects of the invention are presented in FIGS. 1-14, which are not drawn to scale, and wherein like components in the numerous views are numbered alike. Referring now to FIG. 1, a portion of a ROM memory device  10  showing, in schematic plan view, an array of floating-gate transistors  12  (a single transistor  12  indicated in phantom) formed upon a single crystal silicon substrate  16 . The columns of the array are defined by right and left bit-lines  36  and  38  between parallel rows of bit-line oxide  19 . The bit-lines  36  and  38  comprise a multitude of doped source/drain regions  14  disposed beneath the floating gates  24  on opposite sides of a doped common channel region  20 . The source/drain region  14  and channel regions  20  are doped with N type and P type atoms in a manner well known in the art that need not be explained in detail here, other than to say that the doping creates a multitude of transistors suitable for use in a ROM. Each floating-gate transistor  12  comprises such regions. 
     The rows of the matrix are comprised of wordlines  32  formed by parallel control gates  26 , which extend transversely or perpendicular to the direction of the bit-lines  36  and  38 . The floating-gates  24  are located beneath the control gates  26  (i.e., along the wordlines  32 ). As will be explained in detail below, each floating-gate transistor  12  is accessed by addressing the appropriate wordline  32  and bit-lines  36  and  38 . 
     Referring now to FIG. 2, a cross sectional view of the ROM memory device  10  is presented taken along line  2 — 2  of FIG.  1 . Elements previously discussed in relation to FIG. 1 are presented in FIG.  2 . The channel region  20  is located between each pair of adjacent source/drain regions  14  just below the floating gates  24 . As will be explained in greater detail below in connection with the operation of the floating-gate transistor  12 , the channel region  20  is the area through which charge carriers (electrons or holes) travel in response to a potential applied to or across a pair of source/drain regions  14 . The floating gates  24  are comprised of an ONO layer adjacent or between the bit-line oxide  19  rows. The floating gates  24  may partially overlay the bit-line oxide  19 , the channel  20  and/or source/drain regions  14 . The ONO layer comprises a first silicon dioxide layer  21  on the substrate  16 , a silicon nitride layer  22  on the first silicon dioxide layer  21 , and a second silicon dioxide layer  23  on the silicon nitride layer  22 . According to an aspect of the invention, each transistor  12  comprises dual floating gates  24  separated by an isolation spacer  25 . Floating gates of adjacent transistors  12  are also separated by isolation spacers  25 . 
     It should also be noted that the dual floating-gate transistor  12  of the present invention is a symmetrical device. Therefore, the use of the terms “source” and “drain,” as they are commonly used with conventional transistor devices, may be confusing. For example, each dual floating-gate transistor  12  comprises a pair of adjacent source/drain regions  14 . During program, erase and read functions, one of these two source/drain regions  14  will serve as a source, while the other will serve as a drain. 
     In conventional transistor terminology, electrons travel from the source to the drain. Which source/drain region  14  functions as a source, and which serves as a drain, depends on the function being performed and on the floating-gate  24  being addressed (i.e., programmed, erased or read). 
     To avoid confusion, the various components may be referred to as “left” and “right” in the orientation as they appear in the drawings. For example, the source/drain regions  14  and the floating gate  24  corresponding to the left bit-line  36  will be referred to as the left source/drain region  14  and the left floating gate  24 . The source/drain region  14  and the floating gate  24  corresponding to the right bit-line  38  will be designated as the right source/drain region  14  and the right floating gate  24 . In doing so, it is not intended to limit the invention to any particular orientation, since the terms left and right are used merely to indicate relative position. 
     Operation of Device 
     The dual floating-gate transistor  12  of the present invention is capable of storing two bits of information, one bit in each floating-gate  24 . Programming and reading each of the floating-gates  24 , however, requires asymmetrical operation. In particular, programming in one direction (e.g., left to right) will program the right floating-gate  24 . Programming in the other direction (e.g., right to left) will program the left floating-gate  24 . Likewise, which floating-gate  24  is read depends on which direction the read operation is performed. Which of a pair of source/drain regions  14  is utilized as a programming and reading. 
     To program the right floating-gate  24 , the left source/drain  14  is grounded and program voltages are applied to the control gate  26  and the right source/drain  38  to create lateral and vertical electric fields. Under conventional transistor terminology, the left source/drain  14  is considered the “source” and the right source/drain  14  is considered the “drain.” The lateral electric field causes electric charge (i.e., electrons) to propagate across the channel region  20  from the left source/drain  14  towards the right source/drain  14 . Once the charge gains enough energy and encounters a sufficiently strong vertical field, the charge is either injected (Channel Hot Electron injection) or tunnels (Fowler-Nordheim tunneling) from channel region  20  across the first silicon dioxide layer  21  and into the silicon nitride layer  22  of the right floating-gate  42 . Suitable “program voltages” to accomplish this are well known in the art. 
     A similar method is used to program the left floating-gate  24 . However, the “source” and the “drain” are reversed. In other words, the right source/drain  14  is grounded and program voltages are applied to the control gate  26  and the left source/drain  14 . Under conventional transistor terminology, the source/drain  14  is considered the “drain” and the right source/drain  14  is considered the “source.” The lateral and vertical fields generated cause electric charge to move towards the left source/drain  14  and subsequently into the left floating-gate  24 . 
     The floating gates  24  are read in the direction opposite to programming. For example, the right floating-gate  24  is read by grounding the right source/drain and applying read voltages to the control gate  26  and the left source/drain  14 . Under conventional transistor terminology, the left source/drain  14  is considered the “drain” and the right source/drain  14  is considered the “source.” A transistor  12  having a programmed floating gate  24  has a higher threshold voltage than a transistor  12  having an unprogrammed floating gate  24 . The voltage applied to the control gate  26  for reading is greater than the threshold voltage of an unprogrammed transistor  12 , but less than the threshold voltage of a programmed transistor  12 . 
     When reading a particular floating gate  24 , in this case the right one, a transistor  12  having a programmed floating gate  24  conducts current, and a transistor  12  having an unprogrammed floating gate  24  does not conduct current. This property reflects the 0 and 1 bit states, respectively. In this example, the right floating gate  24  determines the threshold voltage, thus corresponding to the right bit in transistor  12 . Suitable “read voltages” are well known in the art. 
     A similar method is used to read the left floating-gate  24 . However, the “source” and the “drain” are reversed. In other words, the left source/drain  14  is grounded and read voltages are applied to the right source/drain  14  and the control gate  26 . Under conventional transistor terminology, the left source/drain  14  is considered the “source” and the right source/drain is considered the “drain.” As described above, the flow of current through the dual floating-gate transistor  12  depends on whether the left floating-gate  24  is programmed or not. In this example, the left floating gate  24  determines the threshold voltage, thus corresponding to the left bit in transistor  12 . 
     It should be understood that the dual floating-gate transistor  12  of the present invention permits the status of one floating-gate  24  to be determined irrespective of the status of the other floating-gate  24 . In other words, the programmed state of one of the floating-gates  24  will not effect the ability to read the other floating-gate  24 . 
     The dual floating-gate transistor  12  is typically erased by simultaneously applying erase voltages to the source/drain regions  14  and the control gate  26  that generate electric fields that pull the trapped electrons out of the silicon nitride layer  22  into the corresponding source/drain. For example, a negative voltage may be applied to the control gate  26  and a positive voltage to the source/drain regions  14  so as to cause electron tunneling to occur from the floating-gates  24  to the source/drain regions  14 . Suitable erase voltages are well known in the art. 
     Programming, reading, and erasing the bits in the dual-bit transistor  12  is performed using support logic circuits disposed outside of the memory array. The configuration of the support logic circuits depends upon the desired parameters for a particular application according to circuit design and fabrication practices known in the art. 
     Process of Fabrication 
     According to a further aspect of the invention, a process for making an array of twobit floating gate transistors  12  for a semiconductor memory device  10  is provided. Still referring to FIGS. 1 and 2, an array of two-bit floating gate transistors  12  is formed having floating gates  24  partially overlying parallel rows of bit-line oxide  19 . Isolation spacers  25  are formed between the parallel rows of bit-line oxide  19  that divide the floating gates  24 . Isolation spacers  27  may also be formed centered over the rows of bit-line oxide  19  that divide the floating gates  24 . According to a further aspect of the invention, the semiconductor memory device  10  may be incorporated into an electronic device, such as a computer, without limitation. 
     Referring now to FIGS. 3-14 a process for making a semiconductor device  10  according to a further aspect of the invention is presented. Referring now specifically to FIG. 1, a silicon wafer substrate  16  is provided having parallel rows of bit-line oxide  19  and a floating gate ONO layer  24  overlying the silicon wafer substrate  16  and the bit-line oxide  19 . The floating gate ONO layer  24  comprises a first silicon dioxide layer  21 , a silicon nitride layer  22  on the first silicon dioxide layer  21 , and a second silicon dioxide layer on the silicon nitride layer  22 . 
     As shown in FIG. 4, a hard mask layer  40  is then deposited on the floating gate ONO layer  24  and a multitude of openings  42  are created in the hard mask layer  40  centered upon the rows of bit-line oxide  19  and centered between the rows of bit-line oxide  19 . The openings define sidewalls  43 . The hard mask layer may be comprised of any material suitable for such use, including SiON, SiN, and polysilicon, without limitation. The openings  42  are created using known masking and trimming techniques, for example by applying photoresist, creating openings in the photoresist, and etching the hard mask layer  40  by a dry or wet etch process. The openings  42  may be configured as rows of trenches parallel to the rows of bit-line oxide  19 , or may be configured as parallel rows of discrete openings corresponding in size to each isolation spacer  25  of FIG. 2, parallel to the rows of bit-line oxide  19 . 
     Referring now to FIG. 5, a spacer layer  44  is then deposited on the hard mask layer  40 . As presented in FIG. 6, the spacer layer  44  is reduced to spacers  46  within the openings  42  by anisotropically etching the spacer layer  44 . The spacers  46  are left adhered to the sidewalls  43 . The spacer layer  44  may be comprised of the same material as the hard mask. Etching is continued through the second silicon dioxide layer  23  and the silicon nitride layer  22  within the openings  42 , thereby exposing the first silicon dioxide layer  21 . 
     According to a preferred embodiment, the width of the openings  42  corresponds to the resolution limit of the lithographic process used to create the openings  42 . The spacers  46  reduce the width even further to a sublithographic dimension. The isolation spacers  25  of FIG. 2 may thus have a width that is less than the lithographic resolution limit. 
     Referring now to FIGS. 6 and 7, the openings  42  are at least partially filled with third silicon dioxide  48 , and the hard mask layer  40  and the spacers  46  are removed. At least a portion of the third silicon dioxide  48  is left at least partially filling the openings  42 , as presented in FIG.  7 . The third silicon dioxide  48  left filling the spacers forms the isolation spacers  25  of FIG.  2 . This may be accomplished, for example, by forming the hard mask layer  40  and the spacers  46  from the same material, but different from the third silicon dioxide  48 . An etch selective to the hard mask layer  40  and the spacers  46  is then performed. Referring now to FIG. 8, a polysilicon layer  50  may then be deposited to form the control gates  26  of FIG.  2 . 
     A preferred method of filling the openings  42  with third silicon dioxide is presented in FIGS. 9 and 10. According to this aspect of the invention, the openings are at least partially filled with the third silicon dioxide by depositing the third silicon dioxide  48  as a layer on the substrate  16  by a CVD process, as shown in FIG.  9 . The layer of third silicon dioxide  48 , the hard mask  40 , and the spacers  46  are removed, but at least a portion of the layer of third silicon dioxide  48  is left within the openings  42 , as shown in FIG.  10 . The layer of third silicon dioxide  48  is preferably grown to a thickness wherein it fills the openings  42  between the spacers  46 . An etch selective to the third silicon dioxide  48  before removing the hard mask  40  and the spacers  46 , but leaving at least some silicon dioxide  48  to form the isolation spacers  25  of FIG.  2 . 
     Referring now to FIG. 11, an alternative embodiment is presented wherein the third silicon dioxide  48  is created by thermally growing the first silicon dioxide layer  21 . The structure that results after the mask  40  and spacers  46  are removed is shown in FIG.  12 . 
     Referring now to FIG. 13, an alternative embodiment is presented wherein the third silicon dioxide  48  is created by implanting oxygen atoms into the substrate  16  within the openings  42 , as described by U.S. Pat. No. 5,939,750. The oxygen implantation is indicated by the arrows  50 . The structure that results after the mask  40  and spacers  46  are removed is shown in FIG.  14 . Other ways of generating the third silicon dioxide  48  are evident in light of the description provided herein. 
     A process for making a semiconductor device  10  having an array of two-bit floating gate transistors  12  is also provided. A silicon wafer substrate  16  is provided having parallel rows of bit-line oxide  19  and a floating gate ONO layer  24  overlying the silicon wafer substrate  16  and the bit-line oxide  19 . A multitude of isolated floating gates  24  are created from the ONO layer  24  arranged such that each two-bit floating gate transistor  12  has two of the isolated floating gates  24 , one for each bit, using the processes described in relation to FIGS. 3-14. 
     According to a further aspect of the invention, a semiconductor memory device  10  is provided made by any of the processes of the invention. According to a further aspect of the invention, a computer is provided comprising the semiconductor memory device  10  made by the processes of the invention. The semiconductor memory device  10  may be a flash EEPROM. 
     Although the invention has been described and illustrated with reference to specific illustrative embodiments thereof, it is not intended that the invention be limited to those illustrative embodiments. Those skilled in the art will recognize that variations and modifications can be made without departing from the true scope and spirit of the invention as defined by the claims that follow. It is therefore intended to include within the invention all such variations and modifications as fall within the scope of the appended claims and equivalents thereof.