Abstract:
The invention relates to a method of and a circuit for digitally demodulating a suppressed-carrier amplitude-modulated signal, of two carriers having the same frequencies Fs in a phase-quadrature relationship, and having a sinusoidal reference signal which is in synchronism with said modulated signal. The method consists in determining the initial angular phase shift α r , between the reference signal and the sampling signal of the frequency Fe by determining the peak amplitude, as well as the sign of the reference signal and the sign of its derivative for a given sampling instant t n+m . The successive values α r  +kφ of the angular phase shifts relative to said modulated signal are thereafter determined by successively adding the phase shift ##EQU1## The amplitudes of the modulated signal of the two quadrature sub-carriers are determined with the aid of tables containing the values of cos (α r  +kφ) and sin (α r  +kφ).

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a method of and circuit for digitally demodulating an amplitude-modulated signal, produced by suppressed-carrier amplitude modulation of two carriers of the same frequencies in a phase-quadrature relationship, provided with a circuit for determining the square a 2  of the peak amplitude a of a sinusoidal reference signal which is in synchronism with the modulated signal and with sampling means; it also relates to the use of such a method in, for example, an embodiment of a demodulation stage for the chrominance signal of a video-frequency signal of a television receiver and actually to any television receiver comprising such a demodulation stage. 
     The French Patent Application No. 8218254 filed by Applicants on Oct. 29th, 1982, describes a demodulation circuit in which measures are taken to recover, from the modulated signal, on the one hand, a first digital signal which is proportional to the frequency of the modulated signal, and, on the other hand, a second digital signal which is proportional to the square of the peak amplitude of the modulated signal. 
     It is necessary to describe briefly the demodulation procedure used to determine the frequency and the square of the peak amplitude of the modulated signal described in said patent application. 
     If the general expression of the analog input signal is of the type x=a·sin ωt, the digital signals at the outputs of the first and second registers 20, 21 and of the analog-to-digital converter 10 have the respective expressions, at a constant sampling frequency (Fe=1/T): 
     
         x.sub.n =a·sin ωt.sub.n for t=t.sub.n       ( 1) 
    
     
         x.sub.n+1 =a·sin (ωt.sub.n +φ) for t=t.sub.n +T (2) 
    
     
         x.sub.n+2 =a·sin (ωt.sub.n +2 φ) for t=t.sub.n +2T (3) 
    
     From these three consecutive measurements x n , x n+1 , x n+2 , it is possible to express the cosine of the angular phase shift φ by: ##EQU2## 
     As it is obvious that the phase shift φ is equal to ##EQU3## wherein Fe is the chosen, constant sampling frequency, Fs is the frequency of the modulated signal ##EQU4## it is obtained that: ##EQU5## which renders it possible to determine the frequency of the input signal and, for example, to demodulate the chrominance signal, which, for the SECAM system, is frequency-modulated. 
     In a similar way, it is possible to express, from three identical consecutive measurements, the square of the amplitude a of the signal by the following expressions, which can be easily derived from the expressions (1) to (3) by simple trigonometrical manipulations: ##EQU6## This can be expressed by the general formula: ##EQU7## 
     On the other hand, French Patent Specification No. 2,502,423, which corresponds to the French Patent Application No. 815,285,  on Mar. 17th 1981, describes a demodulator for demodulating digital frequency-modulated or amplitude-modulated chrominance signals obtained by amplitude modulation with suppressed carrier of two quadrature-phase carriers. The specification describes a demodulation method based on a representation of the frequency-modulated or amplitude-modulated signal by a vector turning in a plane OXY, said signal being sampled by a signal having a frequency 4F, that is to say four times higher than: 
     either the center frequency of the frequency band for the case of frequency modulation (SECAM); 
     or the carrier frequency in the case of amplitude modulation (PAL). 
     For the case of amplitude modulation of the PAL type, which is of interest for the present case, the demodulation procedure is limited to sampling the modulated signal by a signal having a frequency 4F, the case of amplitude modulation being converted to that of frequency modulation where simplifications become apparent connected with approximations relative to the frequency deviations. 
     SUMMARY OF THE INVENTION 
     The invention has for its object to provide a method and a digital demodulation circuit as defined in the opening paragraph, which are characterized in that the rate of the reference signals and the rate of the modulated signals may be synchronous or asynchronous, which rate may occur over a wide frequency range, it being possible to put the method into effect using simple algebraic expressions. 
     To this effect, the invention relates to a digital demodulation method of a signal of the type: 
     
         m.sub.p+1 =u·cos (α+kφ)+v·sin (α+kφ) p and k integers 
    
     characterized in that it comprises the following steps: 
     determining and thereafter storing the sign of the reference signal x n+m  and the sign of the derivative of said reference signal,at a predetermined instant t n+m  for which k is given the value zero; 
     determining at the instant t n+m  the square of the sine of the initial angular phase shift, denoted as the real angular phase shift α r , or the inverse of this square in accordance with the expression 1/sin 2  α r  =a 2  /x 2   n+m  ; 
     determining the values of sin α r , thereafter a value α t  corresponding to one of the values of arc sin α r  chosen in one of the four quadrants of a customary trigonometrical presentation; 
     determining the value of the real angular phase shift α r  from the value of α T , knowledge of the selected quadrant, and the signs of the reference signal and of the derivative of said reference signal for the same instant t n+m  ; 
     determining and thereafter storing, sequentially, at each instant of the sampling rate, the values α r  +kφ modulo 2π; 
     determining and storing, sequentially, the pairs of values sin (α r  +kφ) and cos (α r  +kφ), sin (α r  +(k-1)φ) and cos (α r  +(k-1)φ) for two consecutive instants of the rate; and 
     determining values which are proportional to the modulating signals u and v, from two samples m p  and m p+1  of the modulated signal, by : 
     
         m.sub.p ·sin (α.sub.r +kφ)-m.sub.p+1 ·sin (α.sub.r +(k-1)φ) proportional to u 
    
     and 
     
         m.sub.p+1 ·cos (α.sub.r +(k-1)φ)-m.sub.p ·cos (α.sub.r +kφ) proportional to v. 
    
    
    
     DESCRIPTION OF THE DRAWINGS 
     Particulars and advantages of the invention will become apparent from the following description which is given by way of non-limitative example with reference to the accompanying drawings, in which: 
     FIG. 1a shows a first circuit 11 for determining the square a 2  of the peak amplitude a in accordance with the prior art method and a third circuit 13 for determining the value of the real angular phase shift according to the invention; 
     FIG. 1b shows a second circuit 12 for calculating the derivative of the reference signal and the sign, the values of 1/x 2   n+m , the sign of the reference signal of its derivative; 
     FIG. 1c shows a fourth circuit 14 for calculating the values α r  +kφ at the beginning of each rate period, and the values sin (α r  +kφ) and cos (α r  +kφ)for two consecutive rate instants; 
     FIG. 1d shows a fifth circuit 15 for calculating the in-phase and quadrature components of said modulation signal; and 
     FIG. 2 shows an input multiplexing circuit of the calculating arrangement 62 in accordance with a further embodiment. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The method and the digital amplitude demodulation circuit according to the invention can process, in a preferred embodiment, the chrominance information components in accordance with the PAL system. To that end, the processing in the time of the television line is divided sequentially in a processing of the burst, used here as a reference, and thereafter in a processing operation on that portion of the line which comprises the chrominance information components, used here as the modulated signal to be analyzed. 
     The processing operation on the burst has for its object to determine, in each line, the data about the amplitude and the phase used during the subsequent processing of the chrominance information components. 
     The burst is a pure sinusoidal wave having a perfectly stabilized frequency and which can be represented by x=a·sin ωt wherein ω=2πFs, Fs being the burst frequency. This signal is sampled by a signal having a frequency Fe. 
     Samples x n+2 , x n+1 , x n  respectively, such as: 
     
         x.sub.n =a sin (ωt.sub.n), x.sub.n+1 =a sin (ωt.sub.n +φ), x.sub.n+2 =a sin (ωt.sub.n +2 φ), 
    
     become available at the outputs of the analog-to-digital converter 10, the first register 20 and the second register 21. It will be obvious that the angular phase shift between the burst and the rate signal is equal to ##EQU8## In accordance with the known method, by performing the calculation for the expression (6), it is possible to determine the square of the peak amplitude of the burst signal. 
     In the known PAL television system, the burst frequency is perfectly constant. By operating with a constant rate frequency, the angular phase shift φ is constant and perfectly determined. This also holds for sin 2  φ which is used as a constant in the calculation of a 2 . This calculation is effected in accordance with the method known from the above-mentioned patent application filed by Applicants, in which the second calculating arrangement 23, is, for example, a digital multiplier and the first calculation arrangement 22 is a memory in which all the already precalculated results of x n+1   2  are stored. The third calculating arrangement 24, is, for example, a subtractor, or an adder when the digital data are shown in a two&#39;s complement representation. The fifth calculation arrangement 32 receives at one input the result of the operation x n+1   2  -x n  ·x n+2  and at the other input a defined digital value representing 1/sin 2  φ, for the case in which the fifth calculation arrangement 32 is a multiplier. This digital value would represent sin 2  φ when the fifth calculating arrangement 32 were a divider. In both cases the value of a 2  is obtained as it is defined by the equation (6). This is already described in the abovementioned Applicants Patent Application. 
     For the case in which the frequency of the modulated signal or that of the sampling rate are not really constant, the fourth calculation arrangement 31 renders it possible to effect the calculation of 1/sin 2  φ  or sin 2  φ from previous measurements of a parameter connected with the angular phase shift, for example cos φ. This calculating arrangement may be omitted when these two frequencies are perfectly constant, in which case the value of 1/sin 2  φ or of sin 2  φ is directly entered into the fifth calculating arrangement 32. 
     The particulars and advantages of the invention will now become apparent from the following description. 
     The digital data, for example those from the output of the second register 21, are applied to the subcircuit 49 (FIG. 1b), which determines the derived of the input signal, for example, by means of a known digital filtering operation as, for example, described in Applicants Patent Application No. 8112412, filed June 24th 1981, The sixth calculating arrangement 44 employs the data x n+m+i  to x n+m-j  of a series of i+j1 registers, for example those from a third register 41 to a fifth register 43. Consequently, the information x n+m , the j preceding data and the subsequent i data are then stored around an instant t n+m . By weighting each information component with a coefficient, the derivative is calculated in accordance with a general expression of the type: ##EQU9## Advantageously, this digital filter 49 will have an odd number (i=j) of registers to ensure that the calculation of the derivative will be determined for a rate instant during which the data x n+m  is stored in the fourth register 42. An even digital filter (i≠j) may alternatively be used, but with an adapted rate. Similarly, the digital filter 44 would use advantageously coefficients a p  equal to integral powers of 2 so as to effect the calculation in accordance with equation (9) by simple shifts of the digital data. As the sole object is to preserve the sign of this derivative, the structure of the filter 44 is only determined by the fact that the correct sign must be obtained, the digital value itself is of no importance. Thus, a filter having, for example, 3 registers has proved to be satisfactory for shifting the data for the calculation operation. The sign of this derived and the sign of the sample x n+m  corresponding therewith are preserved in a memory device 45 for later use. 
     The digital values of x n+m  are entered in a seventh calculating arrangement 46, which supplies at its outputs the corresponding values 1/x 2   n+m . Advantageously, this seventh calculating arrangement 46 is constituted by a memory device in which the values which were already precalculated are stored. 
     Thus, the signal cc for the values of 1/x 2   n+m  and signals dd and qq for said two signs are available at the output of the second circuit 12. After the determination of a 2  has been effected, this second circuit 12 is operative at the instant near the ends of the burst but before the chrominance information components of the line begin to appear. This instant is defined by the operating speed of the arrangements used. 
     The signal cc is entered into the eighth calculating arrangement 50 (FIG. 1a), which is constituted by, for example, a multiplier, which calculates 1/sin 2  α r  in accordance with: 
     
         1/sin.sup.2 α.sub.r =a.sup.2 /x.sup.2.sub.n+m        (10) 
    
     By means of the ninth calculating arrangement 51, it is possible to determine from the values of 1/sin 2  α r , the values denoted by α T  and defined by α T  =arc sin α calculated in, for example, the first quadrant (0, π/2) of a customary trigonometrical presentation. The determination of the values of α r  is effected in the tenth calculating arrangement 52, taking into consideration the signs of the derivative and of the signal for the same sample as that processed in expression (10) in accordance with the following Table: 
     
         ______________________________________   sign of the           sign of the calculations   signal  derived     effected______________________________________1st quadrant     +         +           α.sub.r = α.sub.T2nd quadrant     +         -           α.sub.r = π - α.sub.T3rd quadrant     -         -           α.sub.r = π + α.sub.T4th quadrant     -         +           α.sub.r = 2π - α.sub.T______________________________________ 
    
     If α T  is calculated in an other quadrant, so shifted through π/2, π or ##EQU10## it is necessary to take this into account to effect the calculations of the Table in a manner which will be obvious for a person skilled in the art. 
     The value of α r  is obtained at the output of the tenth calculating arrangement 52 (signal rr). This value α r  is introduced in the fourth circuit 14 (FIG. 1c) which, for each selected rate period, increments the value α r  by the value ##EQU11## thereafter the values thus obtained in accordance with the equation: ##EQU12## and thereafter compares this value, each time, with the value 2π, and, if necessary, effects subtraction of the value 2π so as to maintain the value of α r  in the interval (0.2π). 
     For that purpose the fourth circuit 14 is formed by: 
     (a) a first input multiplexer 80 which selects the value of α r  supplied by the tenth calculating arrangement 52, thereafter the consecutive values α r  +kφ supplied by the twelfth calculating arrangement 83; 
     (b) an eleventh calculating arrangement 81 which receives at its first input the output value of the first multiplexer 80 and at its second input a digital representation of the angular phase shift ##EQU13## 
     (c) a sixth register 82 intended to divide over two consecutive periods of time of said selected rate the operation of the closed-loop circuit formed by the first multiplexer 80, the eleventh calculating arrangement 81, the twelfth calculating arrangement 83 and said sixth register 82; 
     (d) a digital comparator 84 effecting the comparison between the output of the sixth register 82 and a digital representation of the constant 2π; 
     (e) a twelfth calculating arrangement 83 effecting the subtraction of a digital representation of the constant 2π, when the comparator 84 detects that the result present at the output of the sixth register 82 exceeds the constant 2π. 
     The seventh and eight registers 90 and 91 preserve the calculated values during one rate period, this being necessary for the alternating operation of the calculating arrangements described hereinafter. The fourth calculating arrangement 93, for example a memory in which a precalculated Table is stored, supplies for each rate period the value sin (α r  +kφ)| signal f|, whose preceding value sin (α r  +(k-1)φ)| signal e| appears at the output of the tenth register 95. Similarly, the signal h corresponds to the value cos (α r  +kφ) and the signal g corresponds to the value cos (α r  +(k-1)φ) produced by the thirteenth calculating arrangement 92 and the ninth register 94, respectively. 
     When now in account is taken of the fact that the representation of the two signals which modulate two sub-carriers which have the same frequencies but are in a phase quadrature relationship is: 
     
         m.sub.p =u·cos (α.sub.r +(k-1)+v sin (α.sub.r +(k-1)φ)                                              (11) 
    
     the subsequent sample will be represented by: 
     
         m.sub.p+1 =u·cos (α.sub.r +kφ)+v sin (α.sub.r +kφ).                                                 (12) 
    
     Denoting: 
     
         e=sin (α.sub.r +(k-1)φ)f=sin (α.sub.r +kφ) 
    
     
         g=cos (α.sub.r +(k-1)h=cos (α.sub.r +kφ) 
    
     it is easy to see that: ##EQU14## It can also be demonstrated that g·f-h·e=sin φ. This value is a constant when the amplitude of one or a plurality of subcarriers having a constant frequency is modulated. It can be derived that the components u and v are proportional to, respectively, m p  ·f-m p+1  ·e and m p+1  ·g-m p  ·h. In an experimental embodiment, the calculation precision, i.e. the number of binary elements which constitute the data, must be adapted to the value of sin φ. 
     The samples m p  (equation 11) supplied by the first circuit 11, for example from the output of the first register 20 (signal bb), is entered into the delay device 60 of the fifth circuit 15 (FIG. 1d), while the samples m p+1  (equation 12) supplied by said first circuit 11 shifted through one rate period with respect to the sample m p , for example, taken from the output of the second register 21 (signal aa) is entered into the fifth circuit 15 in a further delay device which is identical to the delay device 60. These devices ensure phase agreement between the information components arriving in the fifteenth and eighteenth calculating arrangements 62 and 70. The second multiplexer 61 receives the two results f and h and the fifteenth calculating arrangement 62 determines, alternatively, during, each of the two rate periods, the values of the products m p  ·h and m p  ·f storing each, for each of said two periods, in the eleventh register 63 and the twelfth register 64. In an identical way the seventh circuit 17 supplied the results of the calculations of the products m p+1  ·g and m p+1  ·e. The phase and rate are defined in such a way that the sixteenth calculating arrangement 65, for example a subtractor, effects the operation m p+1  ·g-m p  ·h. The results obtained after each sampling instant are stored for the whole duration of a line of the chrominance information and preserved during the subsequent line in the first storage and calculating circuit 66, which also effects the processing of said two consecutive lines in accordance with the customary principles of processing a signal in accordance with the PAL system. 
     The seventeenth calculating arrangement 67 effects a processing operation which is similar to that of the sixteenth calculating arrangement 65 but does so on the samples m p  ·f and m p+1  ·e for the other rate phase. The results obtained at the end of the subtracting operation m p  ·f-m p+1  ·e are stored in the second storage and calculating circuit 68. 
     At the output of the fifth circuit 15, the two inphase components u and v are obtained at a rate which is, for example, half the rate of the fifth calculating arrangement 62. 
     The sampling operation can be effected over a very large frequency range. It is known that the lower limit of the sampling frequency is defined such that one has at least 2 samples available in each period of the signal to be analyzed for the highest frequency of said signal to be analyzed. For a correct sampling of the subcarrier itself, the lower limit will consequently be Fe≧2·(F carr ) max . When only said modulating signal is desired, the lower limit will be Fe≧2 (F mod ) max , which is, for example, effected in accordance with the equation (8). This second, less restrictive limitation must nevertheless be high, taking into account the desired resolution, consequently the number of samples, for the correct recovery of said modulating signal. 
     Without departing from the object of the invention, different variants of the description given in the foregoing can be conceived. More specifically, it is advantageous to arrange that, for example, the fifteenth calculating arrangement 62 (FIG. 2) effects the calculations of the second calculation arrangement 23, the fifth calculation arrangement 32 and the eight calculation arrangement 50 by means of a more extensive multiplexing of said fifteenth calculation arrangement 62. Thus, the third multiplexer 61a receives: 
     the signal 100 representing x n+2   
     the signal 101 representing m p   
     the signal 102 representing 1/sin  100   2   
     the signal 103 originating from the output of the register 110. 
     Similarly, the fourth multiplexer 61b receives: 
     the signal 105 representing x n   
     the signal 106 representing f 
     the signal 107 representing h 
     the signal 108 originating from the third calculating arrangement 24. 
     The register 110 preserves the results of calculating a 2  for later usage. 
     It is even possible to multiplex the fifteenth calculating arrangement 62 and the eighteenth calculating arrangement 70 differently for different operations to be effected without departing from the object of the invention. 
     It should be noted that the invention not only applies to the demodulation of a PAL chrominance signal, but that it may alternatively be used to demodulate any signal obtained by means of amplitude modulation with suppressed sub-carrier, of two sub-carriers of the same frequency and in a phase-quadrature relationship and comprising a synchronous sinusoidal reference signal. 
     Similarly, by a more extensive multiplexing of the fifteenth calculating arrangement 62 and/or of the eighteenth calculating arrangement 70, the frequency and amplitude demodulation of a frequency-modulated signal, for example the chrominance signal of the SECAM type, is effected in accorance with the known method represented by the equations (4) and (6). Thus, one has the disposal of a television receiver by means of which it is possible to demodulate the chrominance information components in accordance with, optionally, the PAL and/or SECAM system.