Abstract:
An image display apparatus having a plurality of image forming devices. In an output circuit provided between constant voltage supplies and wiring for driving each of the image forming devices, MOSFETs are successively turned on from the one having a higher ON resistance at the time of switching to make a stepwise transition between outputs from the constant voltage supplies, and have steady potential, thereby limiting undesirable variation in signal potential at the time of switching.

Description:
DETAILED DESCRIPTION OF THE INVENTION  
       [0001]     1. Technical Field of the Invention  
         [0002]     The present invention relates to an image display method and an apparatus therefore of a television image signal or the like. More particularly, the invention relates to an image display method and an apparatus therefore having a driving circuit permitting industrialization of a matrix image display panel at a low cost.  
         [0003]     2. Description of the Related Art  
         [0004]     Two kinds of electron emission element including a hot cathode element and a cold cathode element have conventionally known. Within the category of cold cathode element, for example, there are known an electric field emitting element (hereinafter referred to as the “FE type”), a metal/insulating layer/metal type emitting element (hereinafter referred to as the “MIM type”), and a surface conduction type emitting element.  
         [0005]     Known examples of the FE type element include W. P. Dyke &amp; W. W. Dolan, “Field emission”, Advance in Electron Physics, 8, 89 (1956), C. A. Spindt, “Physical properties of thin-film field emission cathodes with molybdenum cones”, J. Appl. Physics, 47, 5248 (1976).  
         [0006]     Among MIM-type elements, C. A. Mead, “Operation of tunnel-emission devices, J. Appl. Phys., 32, 646 (1961) is known.  
         [0007]     In the category of surface conduction type emission elements, for example, M. I. Elinson, Radio Eng. Electron Phys., 10, 1290 (1965) and other examples described later are known.  
         [0008]     The surface conduction type emission element is based on the utilization of a phenomenon in which electron emission occurs by supplying current to a small-area thin film formed on a substrate in parallel with the film surface. Reported examples of surface conduction type emission element include one using an SnO 2  thin film proposed by Elinson described above, one based on an Au thin film [G. Dittmer: “Thin Solid Films”, 9, 317 (1972)] one based on an In 2 O 3 /SnO 2  [M. Hartwell], and C. G. Fonstad: “IEEE Trans. ED Conf.” 519 (1975)] and one based on a carbon thin film [H. Araki: Vacuum, vol. 26, no. 1, 22 (1983)].  
         [0009]     As a typical element configuration of these surface conduction type emission elements, the plan view of the element proposed by M. Hartwell et al. described above is illustrated in  FIG. 16 . In  FIG. 16 , reference numeral  3001  represents a substrate, and  3004 , a conductive thin film comprising a metal oxide formed by sputtering. The conductive thin film  3004  is formed into an H-shaped flat surface as shown in the drawing. An electron emitting section  3005  is formed by applying an energizing processing known as an energizing forming described later to this conductive thin film  3004 . The distance L in the drawing is within a range from 0.5 to 1 [mm] and W is set as 0.1 [mm]. For convenience of illustration, the electron emitting section  3005  is represented by a rectangle at the center of the conductive thin film  3004 . This is however schematic, and does not accurately express the position or the shape of the actual electron emitting section.  
         [0010]     In the above-mentioned surface conduction type emission elements including that proposed by M. Hartwell and others, it is a common practice to form an electron emitting section  3005  by applying an energizing processing known as the energizing forming to the conductive thin film  3004  prior to electron emission. More specifically, energizing forming is defined as energizing the conductive thin film  3004  by applying a certain DC voltage or a DC voltage very slowly increasing at a rate of about 1 V/minute to the both ends of the film, causing a local breakage, deformation or deterioration of the conductive thin film  3004 , thereby forming an electron emitting section  3005  in an electrically highly resistant state. Cracks occur partially in the locally broken, deformed or deteriorated conductive thin film  3004 . When applying an appropriate voltage to the conductive thin film  3004  after the energizing forming, electrons are emitted near the cracks.  
         [0011]     The above-mentioned surface conduction type emission elements have a simple structure, providing an advantage of permitting formation of many elements over a wide area. Thus, as disclosed by the present inventor in Japanese Patent Laid-Open No. 64-31332, a method for driving many elements by arrangement is studied.  
         [0012]     Regarding applications of surface conduction type emission elements, research efforts have been made on image forming apparatuses such as image display apparatuses and image recording apparatuses, and charged beam sources.  
         [0013]     Particularly, in the area of application to image display apparatuses, studies are made on image display apparatuses using a combination of the surface conduction type emission element and a fluorescent member emitting light by irradiation of electro beam, as is disclosed in U.S. Pat. No. 5,066,883 and Japanese Patent Laid-Open No. 2-257551 by the present inventor. The image display apparatus based on the combination of a surface conduction type emission element and a fluorescent member is expected to provide properties more excellent that those of the conventional image display apparatuses based on the other principles. For example, as compared with the liquid crystal display apparatuses having become more popular recently, it is more excellent in that it does not require backlight since it is of the spontaneous emitting type, and has a wider viewing angle.  
         [0014]     3. Problems to be Solved by the Invention  
         [0015]     The present inventor and others have tried surface conduction type emission elements of various materials, manufacturing processes and constructions including those described above as the prior art. In addition, the inventor and others have studied a multi-electron beam source in which a number of surface conduction type emission elements are arranged, and an image display apparatus based on the application of this multi-beam source.  
         [0016]     The present inventor and others have tried, for example, a multi-electron beam source based on an electric wiring method shown in  FIG. 17 . More specifically, in the multi-electron beam source, many surface conduction type emission elements are two-dimensionally arranged and wired in a matrix shape as shown in the drawing.  
         [0017]     In the drawing, reference numeral  4001  schematically represents a surface conduction type emission element as shown in  FIG. 16 ;  4002  represents, a row-direction wiring line;  4003 , a column-direction wiring line. The row-direction wiring line  4002  and the column-direction wiring line  4003  have actually a limited electric resistance, but in the drawing, are represented by distribution resistances  4004  and  4005 . Such a manner of wiring is referred to as simple matrix wiring.  
         [0018]     For the convenience of illustration, a 6×6 matrix is shown, but the scale of the matrix is not of course limited to this. For example, in the case of a multi-electron beam source for an image display apparatus, elements in a number sufficient to perform a desired image display are arranged and wired.  
         [0019]     In a multi-electron beam source in which surface conduction type emission elements are simple-matrix-wired, an appropriate electric signal is applied to the row-direction wiring line  4002  and the column-direction wiring line  4003  to ensure desired electron beams. For example, in order to drive surface conduction type emission elements for an arbitrary line in the matrix, a selected voltage Vs is applied to the row-direction wiring line  4002  of the selected line, and simultaneously, a non-selected voltage Vns is applied to the non-selected row wiring line  4002 . In synchronization with this, a driving voltage Ve for output of electron beams to the column-direction wiring line  4003  is applied. According to this method, when ignoring the voltage drop caused by the distribution resistances  4004  and  4005 , a voltage Ve-Vs is applied to the surface conduction type emission elements of the selected line, and a voltage Ve-Vns is applied to the surface conduction type emission elements of the non-selected line. By selecting appropriate values for the individual voltages Ve, Vs and Vns, electron beams of a desired intensity should be outputted only from the surface conduction type emission elements of the selected line. By applying different driving voltages Ve to the different column-direction wiring lines, electron beams of different intensities should be outputted from each of the elements of the selected line. Since the response speed of the surface conduction type emission element is very high, it should be possible to change the length of time during which the electron beams are outputted by changing the length of time of application of the driving voltage Ve.  
         [0020]     The multi-electron beam source in which surface conduction type emission elements are simple-matrix-wired is therefore widely applicable. For example, it is suitably applicable as an electron source for an image display apparatus by appropriately applying an electric signal corresponding to the image information.  
         [0021]     However, problems described below have actually been encountered in the multi-electron beam source having simple-matrix-wired surface conduction type emission elements.  
         [0022]     When using a multi-electron beam source having simple-matrix-wired surface conduction type emission elements as a large-area image display panel, many driving circuits are required and this has prevented smooth commercialization at low costs. Particularly, the display panel is long in the transverse direction, and RGB stripe arrangement is necessary, leading to the necessity of numerous driving circuits of column wiring line as compared with the number of driving circuits for the row wiring lines, this having also prevented low-cost commercialization.  
         [0023]     In view of the above-mentioned problems, it is an object of the present invention to achieve a driving circuit of an image display apparatus with a modulated electron beam source, by low-cost and small-scaled hardware, particularly by a circuit configuration suitable for the tendency toward IC.  
         [0024]     4. Means for Solving the Problems  
         [0025]     The present invention provides an image display apparatus having a matrix image display panel, wherein the matrix image display panel comprises column wiring lines and row wiring lines, and a column wiring line driver and a row wiring line driver for driving electron emitting elements connected to these column wiring line and row wiring lines; the row wiring driver selectively and sequentially drives the row wiring lines at a horizontal synchronization timing; and the column wiring line driver has a shift register, a latch circuit, a pulse modulating circuit and a column wiring line driving circuit; wherein the shift register transfers image information sequentially, during the horizontal synchronization period, and after the completion of transfer, transfers the same in parallel with the latch circuit; the pulse width modulating circuit outputs modulation signals on the basis of the image information transferred in parallel; the column wiring driving circuit receives output modulated by the pulse width modulating circuit, and drives the electron emission elements connected to the column wiring lines; wherein an output circuit of the column wiring driving circuit comprises a complementary switching circuit (CMOS circuit) and has means for adjusting output impedance to the electron emission elements.  
         [0026]     The present invention also provides an image display method which drives a matrix image display panel, wherein the matrix display panel has a row wiring line and a column wiring line, and a row wiring line driver and a column wiring line driver which drive electron emission elements connected to the column wiring line and the row wiring line; selects and drives the row wiring lines sequentially at horizontal synchronization timings by means of the row wiring line driver; sequentially transfers pieces of image information by means of the column wiring line driver within the horizontal synchronization period; transfers all the pieces of image information in parallel to a latch circuit after the completion of transfer; outputs a modulation signal through a pulse width modulating circuit on the basis of the image information transferred in parallel; receives the output of the signal modulated by the pulse width modulating circuit in a column wiring line driving circuit; and drives the electron emission element connected to the column wiring lines; and wherein the output circuit of the column wiring line driving circuit comprises a complementary switching circuit (CMOS circuit); and adjusts an output impedance to the electron emission element.  
       EMBODIMENTS  
       [0027]     Embodiments of the present invention will now be described in detail with reference to the drawings.  
       First Embodiment  
       [0028]     A first embodiment will be described. The matrix image display panel used in the image display apparatus of the present invention comprises a multi-electron source having many electron sources such as cold cathode electron emission elements arranged on a substrate, and an image forming member which forms an image by irradiation of electron, arranged oppositely thereto.  
         [0029]     Such cold cathode electron emission elements can be formed by accurately positioning on a substrate by using, for example, a manufacturing technology such as photolithographic etching. It is therefore possible to arrange many pieces at slight intervals. Furthermore, as compared with hot cathode conventionally used in CRTs, the cathode itself or surroundings thereof can be driven in a relatively low-temperature state. A multi-electron source can therefore easily be achieved with a smaller arrangement pitch.  
         [0030]     In this embodiment of the present invention, the driving method of the matrix image display panel using surface conduction type elements as an electron source will be described. 
     
    
       [0031]     The embodiment of the present invention will now be described with reference to the drawings.  
         [0032]      FIG. 1  illustrates a block diagram of the driving circuit of the image display apparatus of the present invention, and  
         [0033]      FIG. 2 , a timing chart thereof. 
     
    
       [0034]     In  FIG. 1 , reference numeral P 2000  represents a matrix image display panel (hereinafter simply referred to as the “display panel”). In this embodiment, 240*720 surface conduction type elements P 2001  are matrix-wired vertically by 240 row wiring lines and horizontally by 720 column wiring lines, and electron beams from each surface conduction type elements P 2001  are accelerated by a high voltage applied from a high-voltage power supply unit P 30 . Fluorescence is obtained by the electron beams being irradiated onto a fluorescent member not shown. This fluorescent member not shown can be color-arranged in any of various manners in response to the use. As an example, an RGB upright stripe-shaped color arrangement is used here.  
         [0035]     In this embodiment, a case of application where a television image corresponding to a television signal NTSC (National Television System Committee) method is displayed on a display panel having a number of pixels comprising horizontally  240  (RGB trio)*vertically 240 lines is shown below. An image signal having different resolution or frame rate such as a highly precise image of a high definition (HDTV: high definition television) system, or an output signal of a computer can well be coped with, not limited to NTSC, with substantially the same configuration.  
         [0036]     P 1  represents an NTSC-RGB decoder unit which receives an NTSC-system composite video input and outputs a PGB component. Within this unit of the NTSC-RGB decoder unit P 1 , a synchronization (SYNC) signal superposed on the input video signal is separated and outputted. Similarly, a color burst signal superposed on the input video signal is separated, and a clock (CLK) signal (CLK 1 ) synchronized with the color burst signal is generated and outputted.  
         [0037]     P 2  represents a timing generating unit for generating subsequent timing signals necessary for converting an analog RGB signal decoded at the NTSC-RGB decoder unit P 1  into a digital graduation signal for brightness-modulating the matrix image display panel P 2000 .  
         [0038]     A clamp pulse for DC-regenerating an RGB analog signal from the NTSC-RGB decoder unit P 1  at the analog processing units; a blanking pulse (BLK pulse) for adding a blank period to an RGB analog signal from the NTSC-RGB decoder unit P 1  at the analog processing units P 3 ; a detection pulse for detecting the level of an RGB analog signal at the video detecting unit P 4  (not shown); a sample pulse (not shown) for converting an RGB analog signal into a digital signal at the A/D unit P 6 ; and a RAM controller control signal necessary for the RAM controller P 12  (not shown) to control the RAM P 8 , are generated within the timing generating unit P 2 .  
         [0039]     Upon entering a CLK 1 , a self-running CLK signal (CLK 2 ) synchronizing with CLLK 1  by the PLL circuit in the timing generating unit P 2 , a synchronizing signal (SYNC 2 ) generated on the basis of CLK 2  within the timing generating unit P 2 , and self-running CLK 2  generating means are provided. Thus, even when an input video signal is not present, CLK 2  and SYNC 2  which are reference signals can be generated. It is therefore possible to display an image by reading out image data of the RAM means P 8 .  
         [0040]     Reference numeral P 3  represents an analog processing unit provided for each of the output primary colors from P 1 , and mainly performs the following operations. It receives a clamp pulse from the timing generating unit and conducts DC regeneration. It receives a BLK pulse from the timing generating unit P 2  and adds a blanking period.  
         [0041]     Upon receipt of a gain adjusting signal of the D/A unit P 14  which is one of the control outputs of the system control unit composed centering around the MPU  11 , it control the amplitude of primary color signals entered from P 1 .  
         [0042]     It also receives an offset adjusting signal of the D/A unit P 14  which is one of the control outputs of the system control unit composed around the MPU  11 , and performs blank level control of primary color signals entered from P 1 .  
         [0043]     Reference numeral LPFP 5  represents prefilter means placed in the first stage of the A/D unit P 6 .  
         [0044]     The A/D unit P 6  receives a sample CLK from P 2 . It is A/D converter means which quantizes analog primary color signals having passed the LPFP 5  with the necessary number of graduations.  
         [0045]     The inverted γ table P 7  is graduation converting means provided for converting an entered video signal into light emitting properties held by the display panel. When expressing a brightness graduation by the pulse width modulation as in this embodiment, a linear feature is often shown in that the amount of emitted light is substantially proportional to the magnitude of brightness data. On the other hand, a video signal processed in a TV image receiver using a CRT is subjected to a γ processing for correcting the non-liner light emitting property of the CRT. Therefore, when causing display of a TV image on a panel having linear light emitting properties as in this embodiment, it is necessary to cancel the effect of γ processing by graduation converting means such as P 7 .  
         [0046]     It is also possible to change the light emitting properties into favorite ones by switching over the table data by means of the output of the I/O control unit P 13  which is one of control input/output of a system control unit composed centering around the MPU P 11 .  
         [0047]     Reference numeral P 10  represents horizontal 1-line memory means provided for each primary color signal. It rearranges brightness data (image information) entered into the R, G and B systems in parallel into a sequence corresponding to the panel color arrangement, converts the same into a single-system serial signals, and outputs them to the X driver unit via latch means P 22 .  
         [0048]     The system control unit mainly comprises an MPU P 1 , a serial communication I/F P 16 , an I/O control unit P 13 , a D/A unit P 14 , an A/D unit P 15 , a data memory P 17 , and user SW means P 18 .  
         [0049]     The system control unit receives user requests from the user SW means P 18  operated by the user or the serial communication I/F P 16  receiving control signals operated by instruction by external communication, and achieves the request by outputting the corresponding control signal from the I/O control unit P 13  or the D/A unit P 14 .  
         [0050]     In this embodiment, a user request on variability of graduation, brightness, color control and other display control is achievable.  
         [0051]     By providing a data memory P 17 , the amount of user adjustment can be stored.  
         [0052]     Reference numeral P 19  represents a Y-driver control timing generating unit, and P 20 , an X-driver control timing generating unit. Both these units generate Y-driver control and X-driver control signals upon receipt of CLK 1 , CLK 2  and SYNC 2  signals.  
         [0053]     P 21  represents a control unit for timing control of the line memory P 10 , and generates, upon receipt of CLK 2  and SYNC 2  signals, R, G and B WRT control signals for writing brightness data (image information) into the line memory, and R, G and B RD control signals for reading out brightness data (image information) in a sequence corresponding to the panel color arrangement from the line memory.  
         [0054]     T 104  shown in  FIG. 2  represents a waveform of a color sample data train written with a color from among R, G and B as an example, and comprises 240 data trains for a horizontal period. These data trains are written into the line memory P 10  by means of the above-mentioned control signals during one horizontal period. During the next horizontal period, the individual color line memories P 10  are read out at a frequency three time as high as that of write and validated, thus obtaining  720  brightness data trains (image information) per a single horizontal period as represented by T 105 .  
         [0055]     P 22  represents latching means. This latches an output of the line memory P 10  with a slight clock, and synchronizes the data output timing with a desired time.  
         [0056]     P 1001  represents an X, Y driver timing generating unit. Upon receipt of control signals from the Y-driver control timing generating unit P 19  and the X-driver control timing generating unit, it outputs the following signals for X-driver control: a shift clock which sequentially transfers brightness data trains (image information) entered into the shift register circuit P 101   a ; an LD pulse which latches the data transferred by the shift register circuit P 1101   a  in parallel to the latching circuit P 1101   b  (and an LD pulse serving as a trigger for the horizontal period of the PWM generator unit P 1102 ), a shift lock of the horizontal period for operating the Y-shift register P 1002  for Y-driver control, and a trigger signal of a vertical period for giving a row scanning starting trigger and outputted.  
         [0057]     The shift register circuit P 1101   a  reads in parallel brightness data trains (image information) of 720 column wiring lines for each horizontal period from the latching means P 22  by a shift clock in synchronization with the brightness data such as T 107  shown in  FIG. 2  from the X, Y driver timing generating unit P 1001 , and converts the same in parallel the 720 data. It latches the same in parallel with the latching circuit P 1101   b  by an LD pulse such as T 108 , and transfers  720  data for a single horizontal line in a batch to the PWM generator unit P 1002 .  
         [0058]     The PWM generator unit P 1102  provided for each column wiring line receives brightness data (image information) from the latching circuit P 1101   b , and generates pulse signals having a pulse width proportional to the size of brightness data (image information) for each horizontal period with a waveform as shown by T 10  in  FIG. 2 .  
         [0059]     P 1104  represents a column wiring line driving circuit. Upon receipt of a pulse signal having a pulse width proportional to the size of the brightness data (image data) which is an output of the PWM generator unit P 1102 , it drives the column wiring line. T 111  shown in  FIG. 2  represents an example of the column wiring line driving waveform.  
         [0060]     Details of the PWM generator unit P 1102  and the column wiring line driving circuit P 1104  are shown in  FIG. 3 . Detailed description follows.  
         [0061]     The Y-shift register unit P 1002  receives a horizontal period shift clock from the X, Y driver timing generating unit P 1001  and a vertical period trigger signal for giving a row scanning starting trigger, and outputs sequentially a selection signal for scanning the row wiring line to the pre-driver unit P 1003  provided for each row wiring line.  
         [0062]     The output unit which drives each row wiring line comprises, for example, FET means P 1006 , and another FET means P 1004 . The pre-driver unit P 1003  is provided for driving this output unit with a good response. The FET means P 1004  is switching means energized upon selecting a row which applies a −Vss potential from the constant-voltage regulator P 1005  to the row wiring line upon selection. For example, in the case of the present invention, it takes a value of −10 [V]. The FET means P 1006  is switching means energized upon non-selection of a row which drives the row wiring line at 0 [V], becoming the grounding potential upon non-selection. T 112  shown in  FIG. 2  illustrates an example of the row wiring line driving waveform.  
         [0063]     The row wiring lines are sequentially scanned in the above-mentioned manner, and the pulse width is modulated by means of the corresponding image information. The column wiring lines are driven with a driving current value set at an optimum value for each surface conduction type electron emitting element, thus forming an image on the display panel P 2000 .  
         [0064]     The PWM generator unit P 1102  and the column wiring line driving circuit P 1104  will now be described in detail. Details are illustrated in  FIG. 3 .  
         [0065]     In  FIG. 3 , P 1102   a  represents an up-counter circuit for entering the clock PCLK serving as a reference for determining a pulse width of PWM not shown into the clock input terminal; and P 1102   b , a comparator circuit which holds the output on low level until the count output of the up-counter circuit P 1102   a  becomes equal to the output (image information) of the latch circuit P 1101   d . P 1102   c , an AND circuit which outputs PCLK to the clock input terminal of the up-counter circuit P 1102   a  only when the output of the comparator circuit P 1102   b  is on a low level. The above-mentioned LD pulse is entered into the synchronization clear terminal, and after input of the LD pulse, the up-counter P 1102   a  counts PCLK. The output of the comparator circuit P 1102   b  becomes a pulse width depending upon the output (image information) of the latch circuit P 1101   d . P 1102   d  represents a NOT circuit which reverses the output of the comparator circuit P 1102   b  and outputs a high level with a pulse width proportional to the magnitude of the brightness data (image information).  
         [0066]     P 1104   a  represents a complementary switching circuit; and P 1104   b , a resistor of which the resistance value is determined by the display panel.  
         [0067]     The complementary switching circuit P 1104   a  is shown in detail in  FIG. 4 .  
         [0068]     In  FIG. 4 , P 1104   c  represents a NOT circuit; P 1104   d , a P-type MOSFET; and P 1104   e , an N-type MOSFET.  
         [0069]     In the above-mentioned configuration, for a high-level signal of a pulse width corresponding to the size of brightness data (image information) outputted by the PWM generation unit P 1102 , the logic level is reversed at the NOT circuit P 1104   c . The signal is again reverse-outputted by P-type MOSFET P 1104   d  and the N-type MOSFET P 1104   e  which are output circuits, and the source voltage is outputted. In the case of the present invention, upon IC conversion, a source voltage of 5 [V] permitting expectation of a high degree of integrity was used.  
         [0070]     The value of the resistor P 1104   b  in the column wiring line driving circuit P 1104  is set as follows. By appropriately adjusting the value of this resistor P 1104   b , the output impedance to the column wiring line can be effectively set.  
         [0071]     More specifically, a short period of time is set so as to satisfy the requirement for graduation of the pulse modulation. The capacity of the column wiring line, and other parameters are selected so that driving is possible at a frequency lower than the resonance frequency caused by inductance of the flexible substrate connecting the column wiring line, the display panel P 2000  not shown and the column wiring line driving circuit P 1104 .  
         [0072]     When driving the column wiring line with a driving waveform having further frequency components, resonance may occur (hereinafter referred to as “ringing”). In the worst case, ringing causes the driving voltage of the cold cathode element P 2001  to surpass the maximum rating value of the element, and may even break the cold cathode element P 2001 .  
         [0073]     For this display panel of about 10″, a value within a range from 100 [Ω] to 1 [kΩ] is optimum for the resistor P 1104   b . For a large-sized panel of over 30″, a value within a range from 500 [Ω] to 5 [kΩ] was optimum.  
         [0074]     In the present invention, the resistor P 1104   b  is arranged in series to the output of the complementary switching circuit P 1104   a . This may however be replaced by the ON resistance of the P-type MOSFET P 1104   d  and the N-type MOSFET P 1104   e  which are output circuits of the complementary switching circuit P 1104   a . In this case, the resistor P 1104   b  can of course be deleted, and in addition, the P-type MOSSFET P 1104   d  and the N-type MOSSFET P 1104   e  can be downsized, thus permitting further reduction of area, i.e., cost reduction upon IC conversion.  
       Second Embodiment  
       [0075]     A second embodiment of the present invention will now be described. In the second embodiment, the column wiring line driving circuit P 1104  is different from that in the first embodiment. Since the other configurations are the same as in the first embodiment, description of the configurations other then the column wiring line driving circuit P 1104  is omitted here.  
         [0076]     The PWM generator unit P 1102  and the column wiring line driving circuit P 1104  are illustrated in detail in  FIG. 5 .  
         [0077]     In  FIG. 5 , the PWM generator unit P 1102  performs the same operation as in the first embodiment. Description is therefore omitted. As in the first embodiment, the PWM generator unit P 1102  outputs the high level with a pulse width proportional to the size of brightness data (image information).  
         [0078]     In the column wiring line driving circuit P 1104 , P 1104   a  represents a complementary switching circuit as in the first embodiment. P 1104   b  represents a resistor for which a resistance value is determined so as to prevent occurrence of winging by the display panel P 2000  as in the first embodiment. P 1104   f  represents a switch circuit which is turned on or off through control input. P 1106  represents an enable control circuit, comprising a latch circuit P 1106   a  serving as an enable generator as shown in  FIG. 6  and an exclusive logical OR circuit P 1106   b . As shown by T 110   a  in the timing chart of  FIG. 7 , only rising and trailing of the output T 110  of the PWM generator unit P 1102  are on LOW level.  
         [0079]     In  FIG. 6 , P 1106   a  represents a latch circuit, and P 1106   b , an XNOR circuit.  
         [0080]     As shown in  FIG. 5 , the details of the complementary switching circuit P 1104   a  are the same as in the first embodiment, as shown in  FIG. 4 .  
         [0081]     As in the first embodiment, a pulse width high-level signal proportional to the size of the brightness data (image information) outputted by the PWM generator unit P 1102  is outputted. In a high-level signal, the logic level is reversed by the NOT circuit P 1104   c , reversed again and outputted by the P-type MOSFET P 1104   d  and the N-type MOSFET P 1104   e  which are output circuits, and a source voltage is outputted.  
         [0082]     In the present invention, a source voltage of 5 [V] permitting expectation of a high degree of integrity in IC conversion is used.  
         [0083]     In the above-mentioned configuration, the enable control circuit P 1106  time-differentiate the output of the PWM generator unit P 1102 . More specifically, in the latch circuit P 11006   a , using PCLK as a clock, the PWM generator unit P 1102  latches the output. The latched reversed output is reversed and outputted after exclusive OR of the output of the PWM generator unit P 1102  by the XNOR circuit P 1106   b . As a result, the enable control circuit P 1106  low-level-outputs only rising and trailing of the output of the PWM generator unit P 1102  as shown by T 110   a  in  FIG. 7 . The switching circuit P 1104   f  is turned off (open) only when the output of the enable control circuit P 1106  is on a low level, and a value dependent on the resistor P 1104   b  is selected as an internal resistance for driving the column wiring line. By appropriately adjusting the value of this resistor P 1104   b , it is possible to effectively set an output impedance to the column wiring line.  
         [0084]     The value dependent on this resistor P 1104   b  provides the following advantages in the following cases (1) and (2).  
         [0085]     (1) Upon rising and trailing, the output of the enable control circuit P 1106  is on a low level. As in the first embodiment, therefore, the resistor P 1104   b  is placed in series between the complementary switching circuit P 1104   a  and the column wiring line. The column wiring line can be driven without occurrence of ringing.  
         [0086]     (2) Since the output of the enable control circuit P 1106  is on a high level except upon rising and trailing, the resistor P 1104   b  is short-circuited by the switching circuit P 1104   f , and the apparatus is less subjected to voltage drop or power loss. The image display panel P 2000  could be driven satisfactorily without power loss more than in the first embodiment having shown a satisfactory operation.  
         [0087]     The value of the resistor P 1104   b  was selected so that no ringing occurs as in the first embodiment.  
         [0088]     In a panel having a display panel of about 10″, a value within a range from 100 [Ω] to 1 [kΩ] was optimum. For a large-sized panel having a size larger than 30″, a value within a range from 500 [Ω] to 5 [kΩ] was optimum.  
         [0089]     Ringing occurs when the driving waveform shows an abrupt change. In the second embodiment, in which the driving waveform is more gentle in correspondence only to rising and trailing, it is possible to drive the column wiring lines with a driving waveform free from ringing.  
       Third Embodiment  
       [0090]     A third embodiment of the present invention will now be described. In the third embodiment, the column-direction column wiring line driving circuit P 1104  for the display panel P 2000  is different from that in the second embodiment. Since the other configuration is the same as in the second embodiment, description of the configuration other than that of the column wiring line driving circuit P 1104  is omitted here.  
         [0091]     The PWM generator unit P 1102  and the column wiring line driving circuit P 1104  of the third embodiment will be illustrated in detail in  FIG. 8 .  
         [0092]     In  FIG. 8 , the PWM generator unit P 1102  operates in the same manner as in the first embodiment. Description is therefore omitted. The PWM generator unit P 1102  outputs the high level for a period of the pulse width proportional to the size of the brightness data (image information) as in the first embodiment.  
         [0093]     In the column wiring line driving circuit P 1104 , P 1104   a  represents a complementary switching circuit as in the first embodiment, and P 1104   b  represents, as in the first embodiment, a resistor of which a resistance value depends upon the matrix display panel. P 1104   g  represents a three-state control complementary switching circuit of which the output can be brought into a high impedance state by control input.  
         [0094]     P 1106  represents an enable control circuit which comprises a configuration as shown in  FIG. 6  as in the second embodiment. The description of  FIG. 6  is omitted here. The output of the enable control circuit P 1106  is on a low level only upon rising and trailing of the output T 110  of the PWM generator unit P 1102  as shown by T 110   a  in  FIG. 7 .  
         [0095]     The three-state complementary switching circuit P 1104   g  is illustrated in detail in  FIG. 9 .  
         [0096]     In  FIG. 9 , P 11104   h  represents a knot circuit, P 1104   i , a NAND circuit, P 1104   j , a NOR circuit, P 1104   k , a P-type MOSFET, and P 1104   m , an N-type MOSFET.  
         [0097]     In  FIG. 9 , the NAND circuit P 1104   i  and the NOR circuit P 1104   j  output a reversed input only when the enable terminal is on a high level, and reversed and outputted again by the P-type MOSFET P 1104   d  and the N-type MOSFET P 1104   e , and a source voltage is outputted to the output terminal. When the enable terminal is on a low level, outputs of the NAND circuit P 1104   i  and the NOR circuit P 1104   j  are fixed on a high level and a low level, respectively, irrespective of the input. Both the P-type MOSSSFET P 1104   d  and the N-type MOSFET P 1104   e  are pinched off, and the result thereof becomes a high impedance.  
         [0098]     In the present invention, a source voltage of 5 [V] permitting expectation of a high degree of integration upon IC conversion was used.  
         [0099]     In the above-mentioned configuration, the enable control circuit P 1106  outputs a waveform resulting from the time differentiation of the output by the PWM generator unit P 1102  as in the second embodiment. That is, in  FIG. 7 , as shown by T 110   a , the PWM generator unit P 1102  outputs a low level only upon rising and trailing of output.  
         [0100]     The three-state complementary switching circuit P 1104   g  is in a high-impedance state only when the output of the PWM generator unit P 1102  is on a LOW level.  
         [0101]     Since the complementary witching circuit P 1104   a  and the three-state complementary switching circuit P 1104   g  are connected in parallel,  
         [0102]     (1) Upon raising and trailing, output of the enable control circuit P 1106  is on a low level (because the enable input of the three-state complementary switching circuit P 1104   g  is on a low level and the output of the three-state complementary switching circuit P 1104   g  is of a high impedance). It is therefore possible to drive the column wiring line by means of the complementary switching circuit P 1104   a  and the serial circuit of the resistance P 1104   b . It is thus possible to drive the column wiring line without occurrence of ringing.  
         [0103]     (2) Furthermore, since at times other than rising and trailing times, the output of the enable control circuit P 1106  is on a high level (as the enable input of the three-state complementary switching circuit P 1104   g  is on a high level and the output of the three-state complementary switching circuit P 1104   g  is valid), the column wiring lines are driven by the output impedance based on parallel connected of the complementary switching circuit P 1104   a  and the three-state complementary switching circuit P 1104   g , thus leading to only slight voltage drop and power loss. These advantages are available. The image display panel P 2000  could be driven more satisfactorily than in the first embodiment showing a good operation.  
         [0104]     In a panel of about 10″, as in the first embodiment, a value of the resistor P 1104   b  within a range from 100 [Ω]to 1 [kΩ] was optimum. For a large-sized panel larger than 30″, a value within a range from 500 [Ω] to 5 [Ω] was optimum.  
         [0105]     In the present invention, the resistor P 1104   b  is arranged in series with the output of the complementary switching circuit P 1104   a . This may be replaced by an ON resistance of the P-type MOSFET P 1104   d  and the N-type MOSFET P 1104   e  which are output circuits of the complementary switching circuit P 1104   a . In this case, it is of course possible to delete the resistor P 1104   b , and downsize the P-type MOSFET P 11104   d  and the N-type MOSFET P 1104   e , thus permitting further reduction of area, i.e., cost reduction upon IC conversion.  
       Fourth Embodiment  
       [0106]     A fourth embodiment of the present invention will now be described. In the fourth embodiment, column wiring line driving circuit P 1104  in the column direction for the display panel P 2000  is different from that in the third embodiment. Since the other configuration is the same, the description of the configuration other than the column wiring line driving circuit P 1104  is omitted here.  
         [0107]     The PWM generator unit P 1102  and the column wiring line driving circuit P 1104  are shown in detail in  FIG. 10 .  
         [0108]     In  FIG. 10 , the PWM generator circuit P 1102  operates in the same manner as in the first embodiment. Description is therefore omitted. As in the first embodiment, the PWM generator unit P 1102  outputs the time high level of a pulse width proportional to the size of the brightness data (image information).  
         [0109]     In the column wiring line driving circuit P 1104 , reference numerals P 1104   g   1  and P 1104   g   2  represent three-state complementary switching circuits which can bring the output to a high impedance state by a control input. Since the details of the three-state complementary switching circuits P 1104   g   1  and P 1104   g   2  have the same configuration as the three-state complementary switching circuit P 1104   g  described in  FIG. 8 , the description thereof is omitted here.  
         [0110]     P 1104   b  represents a resistor having a resistance value determined by the same matrix display panel as in the first embodiment.  
         [0111]     P 1106  represents an enable control circuit which comprises a configuration as shown in  FIG. 11 . As shown by T 110   a  and T 110   b  in the timing chart illustrated in  FIG. 12 , only rising and trailing of the output T 110  of the PWM generator unit P 1102  exhibit a low level and a high level, respectively.  
         [0112]     The output of the enable control circuit P 1106  is such that, in  FIG. 7 , the output T 110  of the PWM generator unit P 1102  becomes a low level or a high level, as shown by T 110   a  and T 110   b , only upon rising and trailing.  
         [0113]     In  FIG. 11 , P 1106   a  represents a latch circuit, P 1106   c , an XOR circuit, and P 1106   d , a NOT circuit.  
         [0114]     In the present invention, a source voltage of 5 [V] permitting expectation of a high degree of integration upon IC conversion is used.  
         [0115]     In the above-mentioned configuration, the enable control circuit P 1106  time-differentiates the output of the PWM generator unit P 1102 . That is, PCLK is used as a clock at the latch circuit P 1106   a ; the PWM generator unit P 1102  latches the output; and after exclusive OR by the XOR circuit P 1106   c  of the output, the latched reverse output and the PWM generator unit P 1102  outputs the same (T 110   b ). The NOT circuit P 1106   d  reverse-outputs this output (T 110   a ). As a result, as shown in  FIG. 12 , the enable control circuit P 1106  outputs a signal (T 110   a ) causing output of a low level only upon rising and trailing of output of the PWM generator unit P 1102  and a reversed output thereof (T 110   b ). Consequently, the following advantages (1) and (2) are obtained.  
         [0116]     (1) Upon rising and trailing, the enable control circuit P 1106  outputs a high-level enable signal to the three-state complementary switching circuit P 1104   g   1 , and a low-level enable signal to the three-state complementary switching circuit P 1104   g   2 , respectively. As a result, the three-state complementary switching circuit P 1104   g   2  gives a high-impedance output and does not exert an influence on the column wiring line driving. On the other hand, the three-state complementary switching circuit P 1104   g   1  outputs the output of the PWM generator unit P 1102  as it is.  
         [0117]     Since a resistance P 1104   b  is connected in series between the three-state complementary switching circuit P 1104   g   1  and the column wiring line, the column wiring line can be driven with a driving waveform free from ringing.  
         [0118]     (2) At other times than rising and trailing, the enable control circuit P 1106  outputs a low-level enable signal to the three-state complementary switching circuit P 1104   g   1 , and a high-level enable signal to the three-state complementary switching circuit P 1104   g   2 , respectively. As a result, the three-state complementary switching circuit P 1104   g   1  gives a high-impedance output, and does not exert an influence on the column wiring line driving. On the other hand, the three-state complementary switching circuit P 1104   g   2  outputs the output of the PWM generator unit P 1102  as it is. By this output, the three-state complementary switching circuit P 1104   g   2  drives the column wiring line at a low impedance, leading to such advantages as slight voltage drop and power loss. The image display panel P 2000  could be driven satisfactorily more than the first embodiment which was satisfactory.  
         [0119]     For a display panel of about 10″, a value of the resistor P 1104   b  within a range from 100 [Ω] to 1 [kΩ] was optimum. For a large-sized panel larger than 30″, a value within a range from 500 [Ω] to 5 [kΩ] was optimum.  
         [0120]     In the present invention, the resistor P 1104   b  is arranged in series with the output of the complementary switching circuit P 1104   a . This may be replaced by an ON resistance of the P-type MOSFET P 1104   d  and the N-type MOSFET P 1104   e  which are output circuits of the complementary switching circuit P 1104   a . In this case, the resistor P 104   b  can of course be deleted, and the P-type MOSFET P 1104   d  and the N-type MOSFET P 1104   e  can be downsized, thus permitting achievement of further reduction of the area, i.e., reduction of cost upon IC conversion.  
       Fifth Embodiment  
       [0121]     A fifth embodiment of the present invention will now be described. In the fifth embodiment, three or more three-state complementary switching circuits are connected in parallel in the fourth embodiment.  
         [0122]     In  FIG. 13 , the PWM generator unit P 1102  operates in the same manner as in the first embodiment. The description is therefore omitted here. The PWM generator unit P 1102  outputs time high level of the pulse width proportional to the size of brightness data (image information) as in the first embodiment).  
         [0123]     In the column wiring line driving circuit P 1104 , reference numeral P 1104   a  represents a complementary switching circuit as in the first embodiment, and P 1104   b   1 , a first resistor of which a resistance value is determined by the matrix display panel as in the first embodiment. P 1104   g   1  represents a three-state complementary switching circuit of which the output can be brought into a high-impedance state by enable input. P 1104   b   2  represents a second resistor of which the resistance value is determined by the matrix display panel, as in the first embodiment.  
         [0124]     P 1104   g   2  represents a three-state complementary switching circuit of which the output can be brought into a high0impedance state by enable input.  
         [0125]     P 1106  represents an enable control circuit which outputs two kinds of enable outputs including T 110   c  and T 110   d  shown in  FIG. 14 , although the description of the configuration is omitted here.  
         [0126]     The output of the enable control circuit P 1106 , as shown by T 110   c  and T 110   d  in  FIG. 14 , becomes low level only upon rising and trailing of the output T 110  of the PWM generator unit P 1102 .  
         [0127]     The low level period of T 110   c  and T 110   d  has a relationship T 110   c &lt;T 110   d.    
         [0128]     Detailed description of the complementary switching circuit P 1104   a , and the three-state complementary switching circuit P 1104   g   1  and P 1104   g   2  is omitted here, being the same as in the above-mentioned embodiments.  
         [0129]     In the present invention, a source voltage of 5 [V] permitting expectation of a high degree of integration upon IC conversion. This embodiment provides the following advantages (1) and (2).  
         [0130]     (1) Upon rising and trailing (i), both outputs of the enable control circuit P 1106  (both T 110   c  and T 110   d ) are on a low-level (enable input of the three-state complementary switching circuits P 1104   g   1  and P 1104   g   2  are on a low level, and outputs of the three-state complementary switching circuits P 1104   g   1  and P 111104   g   2  show a high impedance). The column wiring line can therefore be driven by the serial circuit of the complementary switching circuit P 1104   a  and the resistor P 1104   b   1 , thus permitting driving of the column wiring line without occurrence of ringing.  
         [0131]     (2) Upon rising and trailing (ii), and further, after the lapse of a time, output T 110   c  of the enable control circuit P 1106  is on a low level and output  110   d  thereof is on a high level (since the enable input of the three-state complementary switching circuit P 1104   g   1  is on a high level, and the output of the three-state complementary switching circuit P 110   g   2  is valid). Therefore, the output impedance is substantially equal to the parallel-connection value of the resistor P 1104   b   1  and the resistor P 1104   b   2 , and this is sufficient to drive the column wiring line. It is therefore possible to drive the column wiring line without occurrence of ringing without slowing down the rising (trailing) waveform too much when the potential difference between the source voltage and the column wiring line voltage is reduced.  
         [0132]     (3) At times other than rising and trailing, outputs of the enable control circuit P 1106  (T 110   c , T 110   d ) are on a high level (because the enable input of the three-state complementary switching circuits P 1104   g   1  and P 1104   g   2  is on a high level, and the output of the three-state complementary switching circuits P 1104   g   1  and P 1104   g   2  is valid). The column wiring line is driven by means of a parallel-connection circuit of the complementary switching circuit P 1104   a  and the three-state complementary switching circuits P 1104   g   1  and P 1104   g   2 , i.e., the column wiring line is driven by the output of the three-state complementary switching circuit P 1104   g   2 , thus resulting in such advantages as reduced voltage drop and power loss. The image display panel P 2000  could thus be driven more satisfactorily than in the fourth embodiment showing satisfactory operation.  
         [0133]     For the resistor P 1104   b   1 , a value within a range from 100 [Ω] to 2 [kΩ] was optimum for a panel of about 10″ as in the first embodiment. For a large-sized panel larger than 30″, a value within a range from 500 [Ω] to 10 [kΩ] was optimum.  
         [0134]     A value of the resistor P 1104   b   2  within a range from 20 [Ω] to 1 [kΩ] was optimum for a display panel of about 10″. For a large-sized panel of over 30″, a value within a range from 100 [Ω] to 5 [kΩ] was optimum.  
         [0135]     In the present invention, the resistor P 1104   b   1  is arranged in series with the output of the complementary switching circuit P 1104   a . This may however be replaced by an ON resistance of the P-type MOSFET P 1104   d  and M-type MOSFET P 1104   e  which are output circuits of the complementary switching circuit P 1104   a . Moreover, the resistor P 1104   b   2  may be replaced by an ON resistance of a P-type MOSFET P 1104   k  and an N-type MOSFET P 1104   m  which are output circuits of the three-state complementary switching circuit P 1104   g   1 . In this case, the resistors P 1104   b   1  and P 1104   b   2  can be of course deleted, and further, the P-type MOSFETs P 11042  and P 1104   k , and the N-type MOSFETs P 1104   e  and P 1104   m  can be downsized, thus permitting reduction of area, hence cost reduction upon IC conversion.  
       Sixth Embodiment  
       [0136]      FIG. 15  illustrates a case of display apparatus configured so that image information provided by various image information sources including those from television broadcasting circles can be displayed on a display panel using the above-mentioned surface conduction type emission elements as an electron beam source.  
         [0137]     In  FIG. 15 , reference numeral  2100  represents a display panel forming an image by emitting electrons from electron emission elements onto a fluorescent member not shown as in the above-mentioned display panel P 2000 ;  2101 , a driving circuit for the display panel  2100 ;  2102 , a display controller;  2103 , multiplexor;  22104 , a decoder;  2105 , input/output interface circuit;  2108 ,  2109  and  2110 , image memory interface circuits;  2111 , an image input interface circuit;  2112  and  2113 , TV signal receiving circuits; and  2114 , an input unit. When receiving signals including both image information and audio information as in TV signals, this display apparatus regenerates voice at the same time as images. Description will however be omitted about circuits regarding receiving, separation, regeneration, processing and storage which have not direct relationship with the features of the present invention and the speaker.  
         [0138]     The functions of various parts and components will now be described along the flow of image signals.  
         [0139]     The TV signal receiving circuit  2113  is a circuit for receiving TV image signals transmitted by the use of a radio transmission system such as electromagnetic waves or space optical communication. The type of TV signals received is not limited to a particular one but may be any of various types including, for example, NTSC, PAL, and SECAM. TV signals comprising more scanning lines than those described above (including so-called high-definition TV such as MUSE method) are signal sources suitable for effective use of advantages of the above-mentioned display panel well adaptable to achievement of a larger area and increase in the number of pixels. TV signals received by the TV signal receiving circuit  2113  are outputted to the decoder  2104 .  
         [0140]     The TV signal receiving circuit  2112  is a circuit for receiving TV image signals transmitted by means of a CATV system such as a coaxial cable or an optical fiber. As in the above-mentioned TV signal receiving circuit  2113 , the type of received TV signals is not limited to a particular one, and TV signals received by this circuit are also outputted to the decoder  2104 .  
         [0141]     The image input interface circuit  2111  is a circuit for incorporating image signals supplied from image input apparatuses such as a TV camera and an image reading scanner. Image signals incorporated are outputted to the decoder  2104 .  
         [0142]     The image memory interface circuit  2110  is a circuit for incorporating image signals stored in a video tape recorder (hereinafter abbreviated as a “VTR”), and the incorporated image signals are outputted to the decoder  2104 .  
         [0143]     The image memory interface circuit  2109  is a circuit for incorporating image signals stored in the video disk, and the incorporated image signals are outputted to the decoder  2104 .  
         [0144]     The image interface circuit  2108  is a circuit for incorporating image signals from the apparatus storing still image data as in a still image disk, and the incorporated still image data are outputted to the decoder  2104 .  
         [0145]     The input/output interface circuit  2105  is a circuit for connecting this display apparatus to an external computer or a computer network or an output unit such as a printer. It conducts input/output of image data or characters or graphic information and in some cases, can perform input/output control signals and numerical data between the CPU  2106  provided in this display apparatus and an external device.  
         [0146]     The image generating circuit  2107  is a circuit for generating image data or character and graphic information entered from outside via the above-mentioned input-output interface circuit  2105 , or image data and character and graphic information outputted from the CPU  2106 . In this circuit, there are incorporated a rewritable memory for storing image data or character and graphic information, a read-only memory storing image patterns corresponding to character codes, and circuits necessary for generating images including processors for carrying out image processing. The image data for display generated by this circuit are outputted to the decoder  2104 , and as required, can be outputted to an external computer network or a printer via the above-mentioned input/output interface circuit  2105 .  
         [0147]     The CPU  2106  carries out mainly operational control of this display apparatus and operations relating to generation, selection or edition of displayed images.  
         [0148]     For example, the CPU outputs control signals to the multiplexer  2103 , and appropriately selects or combines image signals to be displayed on the display panel. It generates control signals to the display panel controller  2102  in response to the image signals to be displayed, and appropriately controls operations of the display apparatus such as the screen display frequency, the scanning method (for example, interlace or non-interlace), or the number of scanning lines per screen. It directly outputs image or character and graphic information to the image generating circuit  2107 , or accesses an external computer or a memory via the input/output interface circuit  2105  to enter image data or character or graphic information.  
         [0149]     The CPU  2106  may if course be engaged in operation for other purposes. For example, it may directly participate in functions generating or processing information as a personal computer or a wordprocessor.  
         [0150]     It may perform such operations as numerical calculation in cooperation with an external device through connection with an external computer network via the input/output interface  2105  as described above.  
         [0151]     The input unit  2114  is for the user to enter an instruction, a program or data into the CPU  2106 , and it is possible to use various input devices such as a joy stick, a barcode reader and voice recognizer, in addition to a keyboard and a mouse.  
         [0152]     The decoder  2104  is a circuit for reverse-converting various image signals entered from above-mentioned  2107  to  2113  into three primary color signals, or a brightness signal and an I-signal or a Q-signal. As shown by a dotted line in this drawing, the decoder  2104  should preferably have an image memory in the interior. This is to handle TV signals requiring an image memory upon reverse-converting as in the MUSE method. By having an image memory, display of a still image becomes easier. Another advantage is that image processing or edition including thinning, interpolation, enlargement, size reduction and synthesis of images becomes easier in cooperation with the image generating circuit  2107  and the CPU  2106 .  
         [0153]     The multiplexer  2103  appropriately selects displayed images in accordance with a control signal control from the CPU  2106 . More specifically, the multiplexer  2103  selects desired image signals from among reverse-converted image signals entered from the decoder, and enters the selected image signal to the driving circuit  2101 . In this case, it is possible to divide a screen into a plurality of regions to display different images as in the so-called multi-screen television set by selecting while switching image signals within a screen display time.  
         [0154]     The display panel controller  2102  is a circuit for controlling the operation of the driving circuit  2101  on the basis of control signals entered from the CPU  2106 .  
         [0155]     Regarding the basic operations of the display panel  2100 , for example, it outputs signals for controlling the operating sequence of the driving power supply (not shown) of the display panel  2100  to the driving circuit  2101 .  
         [0156]     Regarding the driving method of the display panel  2100 , it outputs signals for controlling the image display frequency or the scanning method (for example, interlace or non-interlace) to the driving circuit  2101 .  
         [0157]     As required, it may output control signals regarding adjustment of the image quality such as brightness of the displayed image, contrast, color tone and sharpness, to the driving circuit  2101 .  
         [0158]     The driving circuit  2101  is a circuit for generating driving signals to be applied to the display panel  2100 , and operates on the basis of an image signal entered from the multiplexer  2103  and a control signal entered from the display panel controller  2102 .  
         [0159]     The functions of the parts and components have been described above. Under the effect of the typical configuration shown in  FIG. 15 , in this display apparatus, it is possible to display image information entered from various image information sources onto the display panel  2100 .  
         [0160]     More specifically, various image signals including those of television broadcasting are reversely converted in the decoder  2104 , then, appropriately selected at the multiplexer  2103 , and are entered into the driving circuit  2101 . On the other hand, the display controller  2102  generates control signals for controlling operations of the driving circuit  2101  in response to the image signal to be displayed. The driving circuit  2101  applies a driving signal to the display panel  2100  on the basis of the image signal and the control signal.  
         [0161]     As a result, an image is displayed on the display panel  2100 . These series of operations are comprehensively controlled by the CPU  2106 .  
         [0162]     In this display apparatus, an image selected from among a plurality of pieces of image information is displayed by the participation of the image memory built in the decoder  2104 , and image generating circuit  2107  and the CPU  2106 . Furthermore, it is possible to apply image processing operations including enlargement, reduction, turning, moving, edge enhancement, thinning, interpolation, color conversion, and change of aspect ratio of image, and image editing operations such as synthesis, erasure, connection, replacement, and fitting. Although it has not been specifically pointed out in the description of the embodiments, special circuits for processing or edition also for audio information may be provided.  
         [0163]     This display apparatus can have in a single machine functions of a display device for television broadcasting, a terminal machine for TV conference, an image editing device handling still images and animations, a terminal device of a computer, a word processor and other office terminals, and a game machine, and is very widely applicable for industrial and non-industrial purposes.  
         [0164]     The above-mentioned  FIG. 15  illustrates only some examples of the configuration of the display apparatus using the display panel having surface conduction type emitting elements as an electron beam source. Its configuration is not of course limited to these examples. For example, from among the component elements shown in  FIG. 15 , circuits for functions not necessary for the purposes of use may be omitted. In contrast, further component elements may be added for purposes of use. For example, when this display apparatus is applied as a TV telephone, it would be appropriate to add a TV camera, a voice microphone, an illumination device, transmitting and receiving circuits including a modem to the component elements.  
         [0165]     In this display apparatus, it is possible to reduce the depth of the entire apparatus since the display panel having surface conduction type emission elements as an electron beam source can be made thinner. In addition, the display panel having surface conduction type emission elements as an electron beam source can easily have a larger screen, with a high brightness and excellent viewing angle properties. This display apparatus can therefore display a powerful image rich in feeling of presence with a high visual recognizability.  
       ADVANTAGES  
       [0166]     As described above, in the image display apparatus of the present invention, i.e., in the apparatus having a matrix image display panel having column and row wiring lines, a row wiring line driver and a column wiring line driver which drive the column wiring lines and the row wiring lines, the row wiring line driver sequentially selects and drives the row wiring lines at a horizontal synchronization timing. In this case, the column wiring line driver has a shift register, a latch circuit, a pulse width modulating circuit, and a column wiring line driving circuit. Within the horizontal synchronization period, the shift register sequentially transfers pieces of image information. After the completion of transfer, the image information is transferred in parallel with the latch circuit, and the pulse width modulating circuit outputs a modulation signal on the basis of the image information transferred in parallel. Upon receipt of output of the modulation signal modulated by the pulse width modulating circuit, the column wiring line driving circuit drives the column wiring line. The output circuit of the column wiring line driving circuit comprises a complementary switching circuit (CMOS circuit), thus having means for adjusting the output impedance. As a result, when using a multi-electron beam source in which surface conduction type emission elements are simple-matrix wired as a large-area image display panel, the column wiring line driving circuit so far prevented smooth commercialization at a low cost can drive a large-area display panel at a low cost without the risk ringing.  
         [0167]     In the conventional display apparatus, requiring a stripe arrangement, the number of driving circuits of column wiring lines has been very large as compared with the number of row wiring line driving circuits, and this prevented smooth commercialization at a low cost. According to the present invention, it is possible to achieve a high degree of integration, particularly upon IC conversion, of the driving circuits of the image display apparatus of modulating the electron beam source.  
       BRIEF DESCRIPTION OF THE DRAWINGS  
       [0168]      FIG. 1  is a configuration view illustrating an embodiment of the image display apparatus of the present invention.  
         [0169]      FIG. 2  is a timing chart of a first embodiment of the present invention.  
         [0170]      FIG. 3  illustrates details of a PWM generator and a column wiring line driving circuit of the first embodiment of the present invention.  
         [0171]      FIG. 4  illustrates details of the complementary switching circuit of the first embodiment of the present invention.  
         [0172]      FIG. 5  illustrates details of the PWM generator and the column wiring line driving circuit of a second embodiment of the present invention.  
         [0173]      FIG. 6  illustrates details of an enable control circuit of the second embodiment of the present invention.  
         [0174]      FIG. 7  is a timing chart of the second embodiment of the present invention.  
         [0175]      FIG. 8  illustrates details of a PWM generator and a column wiring line driving circuit of a third embodiment of the present invention.  
         [0176]      FIG. 9  illustrates details of the three-state complementary switching circuit of the third embodiment of the present invention.  
         [0177]      FIG. 10  illustrates details of a PWM generator and a column wiring line driving circuit of the fourth embodiment of the present invention.  
         [0178]      FIG. 11  illustrates details of the PWM generator and the column wiring line driving circuit of the fourth embodiment of the present invention.  
         [0179]      FIG. 12  is a timing chart of the fourth embodiment of the present invention.  
         [0180]      FIG. 13  illustrates details of a PWM generator and a column wiring line driving circuit of a fifth embodiment of the present invention.  
         [0181]      FIG. 14  is a timing chart of the fifth embodiment of the present invention.  
         [0182]      FIG. 15  is a block diagram of the multi-function image display apparatus using the image display apparatus of an embodiment of the present invention.  
         [0183]      FIG. 16  is a plan view of a conventional element proposed by M. Hartwell.  
         [0184]      FIG. 17  illustrates problems in an electron beam source in which wiring is in a matrix shape.  
       REFERENCE NUMERALS  
       [0000]    
       
          P 1 : NTSC-RGB decoder unit  
          P 2 : Timing generating unit  
          P 3 : Analog processing unit  
          P 4 : Video detecting unit  
          P 5 : Pre-filter means (LPF)  
          P 6 : LPF: A/D converter means (A/D unit) which quantize analog primary color signals having passed LPF and P 5  by means of the necessary number of graduations  
          P 7 : Inverted γ table  
          P 10 : Line memory means  
          P 11 : MPU  
          P 13 : I/O control unit  
          P 14 : D/A unit  
          P 16 : Serial communication I/F  
          P 17 : Data memory  
          P 18 : User SW means  
          P 19 : Y-driver control timing generating means  
          P 20 : X-driver control timing generating means  
          P 21 : Line memory control unit  
          P 22 : Latching means  
          P 30 : High-voltage power supply unit  
          P 1001 : X, Y driver timing generating unit  
          P 1002 : Y-shift register unit  
          P 1003 : Pre-driver unit  
          P 1004 : FET means  
          P 1005 : Constant-voltage regulator unit (−Vss)  
          P 1006 : FET means  
          P 1101   a : Shift register circuit  
          P 1101   b : Latch circuit  
          P 1102 : PWM generator unit  
          P 1102   a : Up-counter circuit  
          P 1102   b : Comparator circuit  
          P 1102   c : AND circuit  
          P 1104 : Column wiring line driving circuit  
          P 1104   a : Complementary switching circuit  
          P 1104   b : Resistor  
          P 1104   b   1 : Resistor  
          P 1104   b   2 : Resistor  
          P 1104   f : Switch circuit  
          P 1104   g : Three-state complementary switching circuit  
          P 1104   g   1 : Three-state complementary switching circuit  
          P 1104   g   2 : Three-state complementary switching circuit  
          P 1106 : Enable control circuit  
          P 2000 : Display panel  
          P 2001 : Surface conduction type emission element  
          P 2002 : Row wiring line  
          P 2003 : Column wiring line 
 
  FIG. 1  
 
          ( 1 ) DECODER UNIT  
          ( 2 ) TIMING GENERATING UNIT  
          ( 3 ) RAM CONTROLLER CONTROL SIGNAL  
          ( 4 ) HIGH-VOLTAGE POWER SUPPLY UNIT  
          ( 5 ) TO EXTERNAL HOST  
          ( 6 ) SERIAL COMMUNICATION I/F  
          ( 7 ) CLAMP PULSE  
          ( 8 ) BLK PULSE  
          ( 9 ) Y-DRIVER CONTROL TIMING GENERATING UNIT  
          ( 10 ) PRE-DRIVER  
          ( 11 ) DATA MEMORY  
          ( 12 ) Y-DRIVER CONTROL  
          ( 14 ) X-DRIVER CONTROL  
          ( 16 ) R.G.B. WRT CONTROL  
          ( 17 ) R.G.B. RD CONTROL  
          ( 18 ) X-DRIVER CONTROL TIMING GENERATING UNIT  
          ( 19 ) LINE MEMORY CONTROL UNIT  
          ( 20 ) Y SHIFT REGISTER  
          ( 21 ) DISPLAY PANEL  
          ( 22 ) RGB OFFSET ADJUSTMENT  
          ( 23 ) RGB GAIN ADJUSTMENT  
          ( 24 ) CLAMP PULSE  
          ( 25 ) BLANKING PULSE  
          ( 26 ) TABLE SWITCHING  
          ( 27 ) RRD CONTROL  
          ( 28 ) ANALOG PROCESSING UNIT  
          ( 29 ) R GAIN ADJUSTMENT  
          ( 30 ) R OFFSET ADJUSTMENT  
          ( 31 ) CLAMP PULSE  
          ( 32 ) BLANKING PULSE  
          ( 33 ) G GAIN ADJUSTMENT  
          ( 34 ) G OFFSET ADJUSTMENT  
          ( 35 ) CLAMP PULSE  
          ( 36 ) ANALOG PROCESSING UNIT  
          ( 37 ) B GAIN ADJUSTMENT  
          ( 38 ) B OFFSET ADJUSTMENT  
          ( 39 ) BLANKING PULSE  
          ( 40 ) INVERTED γ TABLE  
          ( 41 ) TABLE CONTROL  
          ( 42 ) INVERTED γ TABLE  
          ( 43 ) G WRT CONTROL  
          ( 44 ) TABLE CONTROL  
          ( 45 ) G LINE MEMORY  
          ( 46 ) GRD CONTROL  
          ( 47 ) X-DRIVER CONTROL  
          ( 48 ) XY DRIVER TIMING GENERATION  
          ( 49 ) B WRT CONTROL  
          ( 50 ) B LINE MEMORY  
          ( 51 ) BRD CONTROL  
          ( 52 ) H TABLE ROW CONTROL  
          ( 53 ) LATCH CIRCUIT  
          ( 54 ) SHIFT REGISTER CIRCUIT 
 
  FIG. 2  
 
          ( 1 ) DECODED COMPONENT VIDE SIGNAL  
          ( 2 ) COLOR SAMPLE DATA  
          ( 3 ) BRIGHTNESS DATA  
          ( 4 ) PWNGEN OUTPUT  
          ( 5 ) H-LEVEL  
          ( 6 ) OUUTPUT VOLTAGE WAVEFORM OF A LINE  
          ( 7 ) 1ST LINE OUTPUT  
          ( 8 ) 2ND LINE OUTPUT  
          ( 9 ) 3RD LINE OUTPUT  
          ( 10 ) 240THE LINE OUTPUT  
          ( 11 ) 2ND LINE  
          ( 12 ) 3RD LINE  
          ( 13 ) 4TH LINE  
          ( 14 ) mTH LINE  
          ( 15 ) 1ST LINE  
          ( 16 ) 2ND LINE  
          ( 17 ) 3RD LINE  
          ( 18 ) 240TH LINE 
 
  FIG. 7  
 
          SEE  FIG. 2  
 
  FIG. 12  
 
          SEE  FIG. 2  
 
  FIG. 14  
 
          SEE  FIG. 2  
 
  FIG. 15  
 
          ( 1 ) TV SIGNAL (RADIO TRANSMISSION SYSSTEM)  
          ( 2 ) TV SIGNAL (CABLE TRANSMISSION SYSSTEM)  
          ( 3 ) IMAGE INPUT UNIT (TV CAMERA)  
          ( 4 ) IMAGE MEMORY (VTR)  
          ( 5 ) IMAGE MEMORY (VIDEO DISK)  
          ( 6 ) IMAGE MEMORY (STILL IMAGE DISK)  
          ( 7 ) COMPUTER NETWORK  
          ( 8 ) PRINTER  
          ( 9 ) TV SIGNAL RECEIVING CIRCUIT  
          ( 10 ) TV SIGNAL RECEIVING CIRCUIT  
          ( 11 ) IMAGE INPUT INTERFACE CIRCUIT  
          ( 12 ) IMAGE INPUT MEMORY INTERFACE CIRCUIT  
          ( 13 ) IMAGE INPUT MEMORY INTERFACE CIRCUIT  
          ( 14 ) IMAGE INPUT MEMORY INTERFACE CIRCUIT  
          ( 15 ) INPUT/OUTPUT INTERFACE CIRCUIT  
          ( 16 ) INPUT UNIT (KEYBOARD, MOUSE, ETC.)  
          ( 17 ) IMAGE GENERATING CIRCUIT  
          ( 18 ) DISPLAY PANEL CONTROLLER  
          ( 19 ) DECODER  
          ( 20 ) IMAGE MEMORY  
          ( 21 ) MULLLTIPLEXER  
          ( 22 ) DRIVING CIRCUIT  
          ( 23 ) DISPLAY PANEL