Abstract:
The present invention integrates a WWTM circuit with the write driver circuitry, which is an inherent part of any conventional SRAM design. Thus, a circuit for writing data into and weak write testing a memory cell is provided. In one embodiment, the circuit comprises a write driver that has an output for applying a write or a weak write output signal at the memory cell. The write driver has first and second selectable operating modes. In the first mode, the write driver is set to apply a weak write output signal from the output for performing a weak write test on the cell. In the second mode, the write driver is set to apply a normal write output signal that is sufficiently strong for writing a data value into the cell when it is healthy.

Description:
BACKGROUND 
     FIG. 1A shows a conventional static random access memory (“SRAM”) cell  50 , which is represented on a transistor level at  50 A and on a more general gate level at  50 B. On the transistor level, cell  50  includes PMOS transistors M 1  and M 2  and NMOS transistors M 3  through M 6 . Transistors M 1  and M 3  are configured as a conventional inverter, which is shown as U 2  in FIGURE 50B. Likewise, transistors M 2  and M 4  are configured as a conventional static inverter, which is shown as U 1  in FIG.  50 B. Inverter M 1 /M 3  (U 2 ) is cross-coupled with inverter M 2 /M 4  (U 1 ) to form the memory storage portion of cell  50 . The input of inverter M 2 /M 4  (U 1 ), which is connected to the output of inverter M 1 /M 3  (U 2 ) provides a DATA storage node, and the input of inverter M 1 /M 3  (U 2 ), which is connected to the output of inverter M 2 /M 4  (U 1 ), provides a Not DATA storage node. Transistors M 5  and M 6  function as switches to control access to the DATA/Not DATA nodes from a differential BIT/Not BIT input. Their gates are connected to a Word Line (“WL”) signal that when active (high) enables writing to and reading from the DATA/Not DATA memory cell nodes. 
     The two cross-coupled PMOS pull-up transistors, M 1  and M 2 , retain a “1” value (at DATA, Not DATA) when written into the cell. These cross-coupled p-devices are designed to be strong enough to retain a 1 value in the cell indefinitely without any external refresh mechanism. However, if the P-devices are too weak due to a fabrication defect or a connection to either of the P devices is missing, the SRAM cell will no longer be able to hold its data indefinitely. The resulting fault in defective cell is referred to as a data retention fault (DRF) or a cell stability fault, depending on its severity. Thus, all SRAMs require some form of data retention and cell stability testing. 
     Traditionally, testing large static CMOS memory arrays for data retention faults (DRFs) and cell stability faults had been a time consuming and expensive effort. Test methods had also been partial in their test coverage. The algorithmic test methods used for detecting these faults were primarily functional in nature; that is they checked the cell stability or retention in a functional manner. These algorithmic test methods were time consuming and required extensive characterization of silicon to determine the worst case test conditions. Fortunately, improved test methodologies have been developed, which address these problems. One such test method is known as Weak Write Test Mode (“WWTM”). for additional information relating to weak write testing, as well as on more traditional methods, reference may be made to Meixner and Banik,  Weak Write Test Mode: An SRAM Cell Design Stability Design For Test Technique , IEEE 0-78033540-6/96 (1996), which is hereby incorporated by reference into this specification. 
     A weak write test is active—in contrast to former tests, which were passive. A WWTM circuit actively attempts to weakly overwrite a cell. It is only capable of overwriting an unstable cell due to the presence of a defect. If the cell can be weakly overwritten, it is assessed to be defective, and if it cannot be weakly overwritten, it is deemed healthy. A weak write test can be used to test an array of memory in much less time than the former passive tests. 
     FIG. 1B shows a WWTM circuit  60  for testing SRAM cell  50 . Weak write tests are implemented with a row of WWTM circuits attached to the bit line pairs of a memory array. WWTM circuit  60  generally includes a PMOS transistor Ma, an NMOS transistor Mb, and pass gate MOS devices Mc through Mf. Transistor Ma provides a high signal to a High node of the circuit  60 . Conversely, transistor Mb provides a low signal (ground) to a Low node. The WWTM circuit  60  includes BIT and Not BIT outputs that are respectively connected across the BIT and Not BIT inputs of he SRAM cell  50 . The BIT output is selectively connected to the High node through pass gate Mc and selectively connects the Low node through pass gate Mf. Alternatively, the Not BIT output is selectively connected to the High node through pass gate Md and selectively connected to the Low node through pass gate Me. A WR 1  input is connected to the gates of Mc and Mf for selecting them in order to weak write a “1” (i.e., apply a weak “1”) at the memory cell. Conversely, a WR 0  input is connected to the gates of pass gates Md and Me for selecting them in order to weak write a “0” at the memory cell. Transistors Ma and Mb are sized so that circuit  60  is not strong enough to override the value in a healthy cell yet strong enough to override the value in a defective cell. 
     WWTM circuit  60  may be used for implementing a weak write test in the following manner. Initially, a background of “0”s are written into a memory cell array. The WWTM circuit  60  is enabled, and a weak write “1” is written to the array, word line by word line, for a preselected time. WWTM circuit  60  is then disabled, and the cells are read to determine if any cell has been overwritten. A background of solid “1”s are then written into the array. The WWTM circuit  60  is once again enabled, but this time, weak write “0”s are written to the cells word line by word line for a preselected time. Circuit  60  is disabled, and the cells are read. The cells that have been written over—either with “1”s or “0”s—are identified as being defective. 
     The preselected time for weak writing to a cell is longer than the time for a normal write operation. For example, in a weak write test mode, a weak write to a cell can occur from 20 to 50 times longer than a typical write cycle time. With the types of processors currently being designed, such required weak write testing time is still far shorter than the milliseconds or even seconds that were required with the previous passive methods. 
     In a typical arrangement, the WWTM circuit  60  is attached at the end of each SRAM cell column in a memory array. Unfortunately, the WWTM circuit is about 1.5 times the size of a normal memory cell  50 . Thus, the area consumed by the WWTM circuits for a memory array is problematic. For example, with arrays having 32 rows in each column, the incorporation of WWTM circuits into memory arrays increases their required size by almost 5%. This is unacceptable in applications (e.g., microprocessor cache) where area is a critical issue. 
     Accordingly, what is needed is an improved scheme for implementing weak write testing. 
     SUMMARY OF THE INVENTION 
     These and other objects, features and technical advantages are achieved by a system and method which integrates a WWTM circuit with the write driver circuitry, which is an inherent part of any conventional SRAM design. Thus, a circuit for writing data into and weak write testing a memory cell is provided. In one embodiment, the circuit comprises a write driver that has an output for applying a write or a weak write output signal at the memory cell. The write driver has first and second selectable operating modes. In the first mode, the write driver is set to apply a weak write output signal from the output for performing a weak write test on the cell. In the second mode, the write driver is set to apply a normal write output signal that is sufficiently strong for writing a data value into the cell when it is healthy. 
     The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which: 
     FIG. 1A depicts a conventional SRAM memory cell; 
     FIG. 1B shows a conventional weak write test circuit operably connected to the memory cell of FIG. 1A; 
     FIG. 2 shows a conventional write driver circuit; and 
     FIG. 3 shows one embodiment of a WWTM mode capable write driver of the present invention. 
    
    
     DETAILED DESCRIPTION 
     Write driver circuits are used to write data into the cells of a memory array. Like conventional WWTM circuit, a write driver is normally operably connected to a column of cells across the BIT and Not BIT lines for differentially writing a value into a cell. The present invention takes advantage of the preexistence of a write driver for any memory array by incorporating into the already-existing driver the capability to also perform a weak write operation. 
     FIG. 2 shows a conventional write driver circuit  80 . Driver circuit  80  has BIT and Not BIT lines for connection to the corresponding BIT/Not BIT lines of a column of memory cells. It also has a DATAIN input, which receives a “0” or a “1” and causes it to be applied at the BIT/Not BIT outputs for writing to the memory cell column. 
     Write driver  80  generally includes PMOS transistors M 11  and M 14 , NMOS transistors M 12 , M 13 , M 15  and M 16 , and inverter U 11 . Transistors M 11  and M 12  are connected in a conventional static inverter gate configuration—as are M 14  and M 13 —forming driver gates for providing the write driver output signal. The gates of the M 11  and M 12  FETs are jointly connected forming the input for the M 11 /M 12  driver gate. Their drains are also jointly connected forming its output. Likewise, the gates of the M 13  and M 14  FETs are jointly connected forming the input for theM 13 /M 14  driver gate, and their drains are jointly connected to form its output. The sources of M 11  and M 14  serve as the supply inputs for their respective driver gates. These supply inputs are connected to V DD . Alternatively, the sources of M 12  and M 13  serve as the supply outputs for the driver gates. Accordingly, they are both connected to ground. Pass gate transistors M 15  and M 16  are connected between the outputs of the M 11 /M 12  and M 13 /M 14  driver gates on the one hand, and the BIT and Not BIT outputs on the other hand, respectively. Their gates are each connected to a WRITE signal for activating the write driver by passing the differential driver gate outputs to the BIT/Not BIT outputs. The DATA input node is at the input of the M 13 /M 14  driver gate, and inverter U 11  is connected between the DATA node and the input of the M 11 /M 12  driver gate, which causes the driver gates to generate a differential output across their outputs. 
     In operation, when a “0” value is applied at the DATA node, the output of the M 11 /M 12  driver gate (which is an inverter) is “0”, and the output of the M 13 /M 14  driver gate is “1”. If the WRITE input is active (e.g., high), pass gates M 15  and M 16  turn on and pass these values through to the BIT and Not BIT outputs for differentially applying a “0” at a memory cell. Conversely, when a “1” is at the DATA input, a “1” (or high value) is generated at the M 11 /M 12  driver gate output, and a “0” (low value) is generated at the M 13 /M 14  driver gate output. If the WRITE input is active, pass gates M 15  and M 16  turn on to pass these values through to the BIT and Not BIT outputs for differentially applying a “1” at the memory cell. 
     FIG. 3 shows one embodiment of a WWTM mode capable write driver circuit  100  of the present invention. Like Write Driver circuit  80 , circuit  100  has DATA and WRITE inputs and BIT and Not BIT outputs for either writing a data value into or weak write testing a memory cell. Circuit  100  also has a Not WWTM input for setting circuit  100  either to WWTM or to normal write mode. 
     Write driver circuit  100  generally includes PMOS transistors M 21  and M 24 , NMOS transistors M 22 , M 23 , and M 25  through M 28 , and inverter U 21 . Transistors M 21 -M 26  and inverter U 21  are similarly arranged and function equivalently as their respective counterparts, M 11 -M 16  and U 11  from circuit  80 . However, rather than being connected directly to ground, the supply outputs (M 22  and M 23  sources) of the driver gates (M 21 / 22  and M 23 /M 24 ) are connected to a BIAS node. Parallel configured first and second bias transistors, M 27  and M 28 , are connected between the BIAS node and ground. The Not WWTM input is at the gate of the first bias transistor M 27 . In contrast, the gate of the second transistor, M 28 , is connected to V DD  to keep M 28  turned on. 
     The amount of resistance between the BIAS node and ground proportionally affects the strength of the driver gates and thereby so affects the strength of the output signal at BIT/Not BIT for writing or weak write testing data into a memory cell. Accordingly, M 28  is designed to be very weak because it will be the only pathway to ground from the BIAS node when driver  100  is in weak write mode. In this way, the output signal when in weak write mode is sufficiently weak for implementing a weak write test. M 28  can have a value corresponding to that of the pull-down transistor, Mb, from FIG.  1 B. Conversely, M 27  is designed to be strong; it will be enabled when circuit  100  is in a normal write mode. In this way, the output signal is bolstered for the write mode when data is to be written into a healthy cell. 
     For a normal write operation, the Not WWTM input is active (high) so that both M 27  and M 28  are on. In this way, the BIT and Not BIT lines are pulled down strongly in order to perform a write operation. Alternatively, when the Not WWTM input is inactive (low), M 27  is turned off and only the relatively weak M 28  transistor remains on. This results in a weaker BIT/Not BIT output for performing a WWTM operation. The actual size of the strong first transistor, M 27 , is not so critical. It simply must be strong enough to allow circuit  100  to implement a write operation. However, the size of the second (WWTM) weak transistor, M 28 , should be selected or tweaked for a particular design so that the BIT/Not BIT signal is strong enough to write over data in a faulty cell but weak enough to not override data in a healthy cell. The actual size of M 28  will vary from design to design depending upon the parameters of the particular circuit and associated memory array. 
     Persons of ordinary skill will recognize that any suitable devices for controllably changing the resistive path between the BIAS node and ground may be used. Such devices could include but are not limited to transistors, pass gates, resistors, current sources and combinations thereof. In addition, with use of a controllably variable resistive pathway (e.g., a removably selectable strong pathway in parallel with a nominal weak path) for controlling the drive strength of a driver gate(s) in a driver circuit, almost any write driver design can be modified to allow it to do both write and weak write test operations. This controllably variable pathway may be implemented in any suitable place within the circuit including within the supply input path, as well as within the supply output path. 
     The WWTM circuitry of circuit  100  adds only two additional NMOS transistors to the write driver of circuit  80 . This is a negligible addition in terms of the whole array size. The design of circuit  100  takes advantage of the fact that Ma from WWTM circuit  60  does not nee to be rigorously sized. In fact, its function is the same as the function of the PMOS transistors in the write circuit  80 , thus allowing the same PFET to be used in both purposes. 
     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.