Abstract:
A programmable pulse code modulation encoder comprises a programmable controller arranged to receive a digital signal input and a plurality of parallel analog signal inputs. The said programmable controller is arranged to digitize the parallel analog signal inputs and modulate them with the digital signal input. A system clock is included to provide clock signals. A counter circuit is connected to the programmable controller to provide interrupt signals under the control of the system clock. A shift register is connected to the programmable controller to receive modulated parallel digital signals corresponding to the parallel analog signal inputs to the programmable controller. The shift register is also connected to the counter and is arranged to function as a parallel to serial converter to provide a serial data stream output at an output terminal of the shift register.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to telemetry instrumentation and particularly to a programmable pulse code modulation (PCM) encoder for encoding telemetry data. 
     2. Description of the Prior Art 
     Pulse code modulation is a sampling technique for digitizing analog signals. PCM samples the signal 8000 times per second, and each sample is represented by 8 bits for a total of 64 Kb per second. PCM is used with carrier systems that combine PCM signals from many lines and transmit them over a single cable or other medium. 
     Previous telemetry instrumentation required a custom PCM encoder made of several separate sub components. These sub components have included an analog signal multiplexer to provide a path from the signal being sampled to the input of an analog to digital (A/D) converter. The A/D converter is used to digitize the analog signal selected by the multiplexer. A typical custom PCM encoder also includes a universal asynchronous receiver, a logic controller and a parallel to serial converter. The universal asynchronous receiver receives data from a digital source such as a GPS receiver. The logic controller controls various sub components and formats the PCM data stream. The parallel to serial converter provides a continuous serial PCM output stream. 
     The logic controller is typically a field programmable gate array (FPGA) set up as a sequencer with its control store including either an external PROM or an internal discrete logic circuit. Because the logic of the FPGA (or code in the PROM) must be programmed by the original equipment manufacturer before being delivered to the user, the resultant PCM encoder is usable only for one, or, at most, a limited set of telemetry instrumentation applications. 
     SUMMARY OF THE INVENTION 
     This invention is directed to a programmable PCM encoder that may be used in a variety of telemetry instrumentation applications. 
     A PCM encoder according to the present invention comprises a programmable controller arranged to receive a digital signal input and a plurality of parallel analog signal inputs. The said programmable controller is arranged to digitize the parallel analog signal inputs and modulate them with the digital signal input. A system clock is included to provide clock signals. A counter circuit is connected to the programmable controller to provide interrupt signals under the control of the system clock. A shift register is connected to the programmable controller to receive modulated parallel digital signals corresponding to the parallel analog signal inputs to the programmable controller. The shift register is also connected to the counter and is arranged to function as a parallel to serial converter to provide a serial data stream output at an output terminal of the shift register. 
     The pulse code modulation encoder according to the present invention preferably further comprises an operational amplifier array arranged to provide the parallel analog signal inputs to the programmable controller. 
     The invention preferably further comprises a line receiver connected to the programmable controller. The line receiver is arranged to receive a balanced digital and provide a unipolar digital signal to the programmable controller for modulating digital signals corresponding to the parallel analog signal inputs. 
     The pulse code modulation encoder according to the present invention preferably further comprises an output buffer connected to the output terminal of the shift register; and a filter circuit connected to the output buffer to provide a filtered, encoded signal output. 
     The structure and function of the invention may be best understood by referring to the accompanying drawings, which are not to scale, and to the following detailed description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a generalized block diagram of a programmable microcontroller based PCM encoder according to the present invention; 
     FIGS. 2A-2J are schematic diagrams illustrating an operational amplifier array that may be included in the invention; 
     FIG. 3 illustrates a voltage divider circuit that may be included in the invention; 
     FIG. 4 illustrates a voltage reference source that may be included in the invention; 
     FIG. 5 illustrates a line receiver that may be included in the invention; 
     FIG. 6 illustrates a microcontroller that may be included in the embodiment of the invention shown in FIG. 1; 
     FIG. 7 illustrates a clock, a counter and a shift register that may be connected to the microcontroller of FIG. 6; 
     FIG. 8 illustrates a buffer circuit that may be used to provide output signals from the invention; and 
     FIG. 9 illustrates a voltage regulator circuit that may be included in the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     As shown in FIG. 1, a PCM encoder  20  according to the present invention includes a microcontroller  22  formed to have a peripheral integrated controller (PIC) architecture, which is well-known in the art. An operational amplifier array  24  amplifies analog signals input thereto and provides a plurality of channels of ANALOG IN signals to a microcontroller  22 . In a preferred embodiment of the invention there are ten channels of ANALOG IN signals. Microcontroller  22  preferably is a Microchip, Inc. device presently designated as PIC16C774QF or the equivalent. 
     The preferred embodiment of microcontroller  22  is powerful, yet easy to program, having only thirty-five single word instructions. It is a reduced instruction set computer (RISC) based 8-bit microcontroller employing Microchip&#39;s PIC architecture into either a 40 or 44 pin package. As shown in FIG. 6 microcontroller  22  has pins numbered  1 - 44 . Microcontroller  22  has ten channels of 12-bit A/D converter, which provides the capability of discriminating small signal changes and eliminating the need for high precision of analog signals. Microcontroller  22  is capable of receiving 40K samples of analog data per second with total throughput. As used in PCM encoder  20 , microcontroller  22  performs A/D conversions, acquires digital RS-232 data and sets up the order for the data going into a shift register  28 . 
     Microcontroller  22  also has an asynchronous serial data input channel that may be connected to a standard RS-422 receiver and receive signals having the standard RS-232 protocol (1 start bit, 8 data bits and 1 stop bit). RS-232 signals may be received at rates of up to 115.2 KBaud. Microcontroller  22  also preferably has on on-board first in/first out (FIFO) capability and can delay the entire data stream by up to 100 msec. 
     Microcontroller  22  receives CLOCK IN signals at a CLK 13  IN terminal. CLOCK IN signal are also input to a counter  26 . In a preferred embodiment of the invention counter  26  is a 12-bit binary counter. Counter  26  has an output terminal OJ that is connected to an INT IN terminal of microcontroller and has an output OG that is connected to the CLK_IN terminal of shift register  28 . Every time microcontroller  22  receives an interrupt signal at the INT IN terminal, it sends data from a DATA OUT terminal to shift register  28 . Shift register  28  converts parallel data output from microcontroller  22  into a serial data stream output. A Load/Shift (L/S) terminal of microcontroller  22  is connected to an L/S terminal of shift register  28 . After a data word in loaded into shift register  28 , microcontroller  22  causes it to shift and prepare to receive the next data word. 
     In an exemplary embodiment of the invention microcontroller  22  is programmed to receive eight channels of analog signals (0 to 5V) at 3.551K samples/sec. Data is output at 312.5K bits/sec. The data output has 8 bits per word and 11 words per frame. There are 2 synch words and 1 frame counter word. 
     FIGS.  2 A— 2 J show circuitry for a plurality of operational amplifiers  24 A— 24 J that may be included in operational amplifier array  24 . Operational amplifiers  24 A- 24 J serve as buffers for analog signals that are input to microcontroller  22  Microcontroller  22  has ten analog input pins numbered  10 ,  11  and  19 - 27  in FIG.  6 . Operational amplifiers  24 A- 24 H are connected to microcontroller  22  at input pins  19 - 27 , respectively; and operational amplifiers  24 I and  24 J are connected to microcontroller  22  at input pins  10  and  11 , respectively. Operational amplifier array  22  provides analog signal conditioning with attenuation or gain on five channels and attenuation only on five channels. Suitable operational amplifiers are commercially available from several manufacturers. In an exemplary preferred embodiment of the invention, operational amplifiers  24 A- 24 J are Burr-Brown model OPA2337 integrated circuits. 
     A resistor R 6  having one grounded terminal is connected to the negative input of operational amplifier  24 A. Resistor R 6  preferably has a resistance of about 10MΩ. A resistor R 8 , preferably having a resistance of about 10Ω, is connected between the output of operational amplifier  24 A and the negative input. An analog signal input passes through a resistor R 9  that is connected to the positive input of operational amplifier  24 A. Resistor R 9  preferably has a resistance of about 100Ω. A capacitor C 19 , preferably having a capacitance of about 1500 pF is connected between the positive input of operational amplifier  24 A and ground. A resistor R 10  is connected in parallel with capacitor C 19 . Resistor R 10  preferably has a resistance of about 150 kΩ. 
     Circuitry that is essentially identical to the circuitry connected to operational amplifier  24 A is also connected to operational amplifiers  24 C,  24 E,  24 G and  241  as shown in FIGS. 2C,  2 E,  2 G and  2 I, respectively. 
     Operational amplifier  24 B has its negative input terminal connected to its output terminal. An analog signal input passes through a resistor R 14  that is connected to the positive input of operational amplifier  24 A. Resistor R 14  preferably has a resistance of about 100 kΩ. A capacitor C 17 , preferably having a capacitance of about 1500 pF is connected between the positive input of operational amplifier  24 A and ground. A resistor R 17  is connected in parallel with capacitor C 19 . Resistor R 17  preferably has a resistance of about 150 kΩ. 
     Circuitry that is essentially identical to the circuitry connected to operational amplifier  24 B is also connected to operational amplifiers  24 D,  24 F,  24 H and  24 J as shown in FIGS. 2D,  2 F,  2 H and  2 J. 
     Referring to FIGS. 3 and 6, a voltage reference source  30  provides a reference voltage input to pin  28  of microcontroller  22  The reference voltage is applied to A/D converter circuitry (not shown) that is built into microcontroller  22 . A suitable circuit for voltage reference source  30  is commercially available from Linear-Technology Corporation under model designation LT1460, which is a 2.5V-output, precision series, band gap reference that combines very high accuracy and low drift with low power dissipation. Any device that is equivalent to the Linear Technology LT1460 may be used as voltage reference source  30 . 
     Referring to FIGS. 6 and 7, a clock circuit  32  provides clock (CLK) signals to pin  30  of microcontroller  22  and to pin  10  of counter  26 . Clock circuit  32  preferably is a Dallas Semiconductor&#39;s DS 1075 or the equivalent. The DS1075 can be programmed to produce a set frequency between 27 kHz and 100 MHz. In the present invention, clock circuit  32  is programmed to have an output frequency of 20 MHz. The DS 1075 includes a programmable EEPROM divider and a prescaler (not shown) that is used to produce the desired output frequency. 
     Counter  26  has a pin  12  that is connected to pin  8  of microcontroller  22  Counter  26  preferably is an SGS-Thomson Microelectronics high speed CMOS 74HC4040 twelve-stage binary counter. Each division stage has an output with the final frequency output being          1   4096          f   IN                            
     where f IN  is the frequency of the signal input from clock circuit  32 . Counter  26  divides the clock signal down to a word clock signal and a bit clock signal that are input to microcontroller  22 . 
     Still referring to FIGS. 6 and 7, shift register  28  has a pin  12  that is connected to pin  2  of counter  26 , which is also connected to pin  8  of microcontroller  22  Shift register  28  has pins  4 - 8  and  9  that are connected to pins  4 ,  40 ,  39 ,  38  and  8 , respectively, of microcontroller  22  Pins  12 - 16  of shift register  28  are connected to pins  2 ,  41 ,  3  and  5 , respectively, of microcontroller  22  A signal output is provided at pin  17  of shift register  28 . 
     As shown in FIG. 9, PCM encoder  20  includes a voltage regulator  34  that provides a regulated voltage Vcc to various components of the PCM encoder  20 . Voltage regulator  34  may be a Linear Technologies model LT1121, which is a micropower low dropout regulator capable of supplying 150 mA of output current with a dropout voltage of 0.4V. The Linear Technologies model LT1 121 has the ability to operate with very small output capacitors. In the present invention voltage regulator  34  has an output capacitor C 25  that is preferably about 1.0 μF. A plurality of grounded capacitors C 1 , C 7 , C 9 -C 12 , C 16 , C 18 , C 20 , C 21  and C 23  are arranged in parallel and connected to pin  1  of voltage regulator  34  to by-pass digital logic signals and to provide noise reduction. 
     As shown in FIG. 4, PCM encoder  20  receives signals from a line receiver  40  that preferably is a Linear Technologies model LTC1482 integrated circuit or the equivalent. Line receiver  40  receives a balanced signal input that may be in standard RS422 or RS485 format and provides a unipolar output that is either zero or five volts to microcontroller  22  Signals output from pin  1  of line receiver  38  are input to pin  1  of microcontroller  22  as indicated in FIGS. 4 and 6. 
     Shift register  28  preferably is an 8-bit universal shift/storage register sold by Fairchild Semiconductor as model No. 74AC299. Any equivalent device may be used in practicing the invention. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. A separate active LOW Master Reset is used to reset the register. Shift register  28  is arranged to receive control signals and data signals from microcontroller  22  Signals output from shift register  28  are input to a buffer circuit  36 , which may be a Phillips Semiconductors model 74AHC1G08 integrated circuit. Signals output from the buffer  36  pass through a resistor R 11  and filtered by a pi-filter circuit  38  that includes an inductor L 1  between two grounded capacitors C 2  and C 3 . Signals passed by the pi-filter  38  comprise the output of the PCM encoder  20  and are the voltage across a resistor R 17 . 
     Software that may be used to program microcontroller  22  and control the interrupt and shifting circuits is presented in an appendix. The software includes four sections: 
     1. Initialization, 
     2. interrupt service, 
     3. a main “frame,” and 
     4. individual word routines. 
     The initialization section sets up internal registers, inputs/outputs (I/O&#39;s), interrupts, peripheral functions of microcontroller  22  and default variable words. 
     The interrupt service routine places the next PCM data word on an output port, controls the L/S input of shift register  28  and resets the WAITING for interrupt flag. 
     The main “frame” is an endless loop used to acquire each progressive PCM data word from either internal registers in microcontroller  22  or from its peripherals. Each word output from microcontroller  22  is sequenced in a progressive order via a lookup table. Microcontroller  22  uses a function called “ADDWF PCL,  1 ” that adds the contents of a register W to the program counter. Register W had previously been loaded with a variable called CURRENT_WORD, which is a number that is incremented each time a PCM word is placed on the output port and then reset to zero after the entire PCM frame has been sequenced through. 
     Each time the ADDWF command is executed, it jumps to the next GOTO statement. Each GOTO statement then goes to the routine listed to execute the routine for that PCM word. After the routine is executed, it places the acquired data in a WORD_BUFFER register, sets a WAITING variable and then returns to the main routine. The main routine then waits in a loop for the next interrupt request. 
     The individual routines include code necessary to acquire data from the A/D converter, ASART, counters and preset synchronization patterns. 
     The structures and methods disclosed herein illustrate the principles of the present invention. The invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects as exemplary and illustrative rather than restrictive. Therefore, the appended claims rather than the foregoing description define the scope of the invention. All modifications to the embodiments described herein that come within the meaning and range of equivalence of the claims are embraced within the scope of the invention.