Abstract:
A common motherboard interface accommodates processor modules of different processor architectures. The system comprises an interface for communicating with a processor module inserted at the motherboard. The interface receives an identifier signal from the processor module. The identifier signal identifies the processor module architecture. An architecture selection circuit selectively exchanges processor architecture specific signals with the processor module based on the identifier signal. In this manner, a multiple of processor modules of completely different processor architectures can share a common motherboard, thereby providing a system that can be field-upgraded by processor modules of different architectures, or simply allowing the same motherboard to be employed in two different products of different processor architectures.

Description:
BACKGROUND OF THE INVENTION 
     Processor modules have become popular in recent years as a means for providing reliable and efficient computer system upgrades. In a processor module, a processor is mounted to a circuit panel containing electrical interconnection paths, for example a printed circuit board, along with support electronics, for example random access memory (RAM) in the form of processor cache. Module electronics communicate with electronics mounted to a computer motherboard via an interface in the form of a high-speed connector. Ideally, as system clock rates increase, and processor functions evolve, the outdated processor module assembly can be removed from the motherboard at its connector and replaced by an upgraded module capable of operating at the higher rate, and/or with improved functionality. 
     While some contemporary systems allow for an upgrade or replacement by a processor module within a same processor family, or having the same processor architecture, as the original, such systems do not accommodate replacement by a processor module from a different processor family, or different architecture. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a motherboard interface for a processor module that accommodates processors of different processor architectures sharing a common high-speed system bus architecture. In this manner, an interface is provided such that a processor module including a processor of a first architecture, for example the x86™ family of processors produced by AMD Corp., can be replaced by a processor module including a processor of a second, and distinct, architecture, for example the Alpha™ family of processors produced by Compaq Computer Corp. The present invention thus allows a multiple of completely different processor architectures to share a common motherboard, thereby providing a system that can be field-upgraded by processor modules of different architectures, or to simply allow the same motherboard to be employed in two different products of different processor architectures. 
     The present invention comprises a system for a motherboard adapted for interfacing with processor modules of a plurality of different processor architectures. The system comprises an interface for communicating with a processor module inserted at the motherboard. The interface receives an identifier signal from the processor module. The identifier signal identifies the processor module architecture. An architecture selection circuit selectively exchanges processor architecture specific signals with the processor module based on the identifier signal. 
     In a preferred embodiment, the interface comprises a connector for exchanging signals between the motherboard and processor module. The interface further communicates processor architecture specific signals and processor architecture common signals. 
     The architecture selection circuit may comprise a multiplexer bank for outputting one of a plurality of processor architecture specific signals to the interface selected by the identifier signal. The architecture selection circuit may further comprise a demultiplexer bank for inputting one of a plurality of processor architecture specific signals from the interface selected by the identifier signal. 
     The system may further comprise an initialization memory bank comprising processor architecture specific data stored in memory, the data being selected based on the identifier signal. The memory preferably comprises processor architecture specific BIOS ROM. The processor architecture specific data is preferably transferred to the processor module via processor common signals on the interface. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects, features and advantages of the invention will be apparent from the more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. 
     FIG. 1 is a perspective view of an interface between a motherboard and processor module that allows for automated recognition of a processor on the module independent of the processor family in accordance with the present invention. 
     FIG. 2 is a block diagram of the interface of FIG. 1 in accordance with the present invention. 
     FIG. 3 is a schematic circuit diagram of an exemplary circuit for the control logic of FIG. 2 in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 1 is a perspective view of an interface between a motherboard  34  and one of a plurality of processor modules  20 A,  20 B. The motherboard  34  includes a connector  27  for communicating with the processor modules  20 A,  20 B. The processor modules  20 A,  20 B are of different processor architectures, and include processors  22 A,  22 B from different processor families. As an example, processor  22 A may comprise a processor from the x86™ family of processors produced by AMD Corp., while processor  22 B may be of the Alpha™ family of processors produced by Compaq Computer Corp. Similarly, memory  24 A,  24 B, for example in the form of off-chip cache-RAM, are likewise mounted to the processor modules  20 A,  20 B and may be specifically adapted for use with each respective family of processors. Connectors  26 A,  26 B are further provided for interfacing with the motherboard connector  27 . 
     The present invention allows for either of the processor modules  20 A,  20 B to be mounted to the motherboard  34  at connector  27  and for the motherboard  34  electronics to automatically recognize the type of processor module and communicate directly with either processor  22 A,  22 B. The processor architecture is identified by an architecture identifier signal  32  which is hard-wired or otherwise stored in memory, for example in ROM, on the processor module  20 A,  20 B and provided to the motherboard electronics  34  via connector  27 . As an example, an x86™ family of processors may be indicated on line  32  by a binary zero, while an Alpha™ processor type may be indicated by a binary one. Additional lines, or encoding via serial transfer, are also possible to provide additional data to the motherboard  34  regarding the processor architecture, as needed. For example, the motherboard  34  may be configured to receive third or fourth family processor types, or processors of various generations within each family. In these cases, additional information can be provided via line  32 . A technique for transferring processor module information is disclosed in U.S. patent application Ser. No. 09/335,939, filed Jun. 18, 1999, entitled “Dynamic Initialization of Processor Module via Motherboard Interface”, by Gerry Talbot et al., incorporated herein by reference. 
     Ideally, processor modules of different architectures have a number of signals, for example address, data, and control signals, that are shared in common among the architectures. These common signals, referred to herein as “processor architecture common signals”, are represented by the common line  28  in FIG. 1, and are provided directly to the motherboard  34  through connector  27 . As an example, if both processors from different families  22 A,  22 B have a data bus of common nature, the bus bits can be provided directly from the motherboard  34  to connector  27  and exchanged directly with the processor modules  20 A,  20 B regardless of the type of module inserted. 
     The processors may also contain a number of signals that are unique to each processor. Such unique signals, referred to herein as “processor architecture specific signals”, are represented in FIG. 1 by line  30 A, for processor module  20 A, and line  30 B for processor module  20 B. Such signals may involve particular interrupt protocols or control signals specific to each processor that operate according to unique protocols, and therefore are not in common among the processor modules  20 A,  20 B. 
     FIG. 2 is a schematic block diagram of the interface of FIG.  1 . In FIG. 2, it can be seen that the processor architecture identifier signal  32  is transferred through connectors  26 ,  27  into the motherboard  34  where it is input to control logic  42  and employed, for example as a selector bit. In a more sophisticated embodiment, where the processor type indicator signal  32  involves an encoded signal, it may first be decoded by decoding circuitry on the motherboard  34  and passed to control logic  42 . 
     At the control logic  42 , x86-specific signals  33 A are provided, along with Alpha-specific signals  33 B. These processor architecture specific signals could optionally be provided directly to the connector  27  and selectively received by the corresponding connector  26 A,  26 B for the particular processor  22 A,  22 B; however, in order to reduce pin count at the connectors  26 ,  27  the processor architecture specific signals  33 A,  33 B are multiplexed by the control logic  42  into a single set of contacts at connector  27  via line  31 . 
     FIG. 3 is a schematic diagram illustrating the use of the processor architecture identifier signal  32  as a selection signal for multiplexing the processor architecture specific signals  33 A,  33 B. A number of x86™ processor specific signals x86 — 0 . . . x86-N are provided as first inputs to the multiplexer bank  44 . Similarly, a number of Alpha™ processor specific signals Alpha — 0 . . . Alpha_N are provided as second inputs to the multiplexer bank  44 . The processor architecture identifier signal  32  is used as a selector signal by the multiplexers  44  to determine which of the two input signals in the multiplexer bank are connected to line  31  and transferred to connector  27 . In similar fashion, signals input from line  31  to the control logic  42  can be demultiplexed and provided to processor-specific hardware via lines  33 A,  33 B based on the identifier signal  32  used as a demultiplexer selection bit. In many situations there will not be an equal number of processor-specific signals to be transferred for each architecture. In this case, the excess signals can be transferred directly to the connector  27  without first passing through the control logic  42 . 
     The processor architecture identifier signal  32  is further distributed to a memory bank  36 , for example comprising Basic Input/Output System (BIOS) ROM for the Alpha™ 36A and x86™ 36B processors. In the example given, the processor architecture identifier signal  32  is a single bit and therefore an inverter  48  is included to invert the signal as a selection signal for the x86™ BIOS ROM. In this manner, one of the two ROM units  36  is activated. During initialization of the processor, the initialization program is transferred out of the activated ROM  36  and provided to bridge  40  which performs a standard operation for converting the data from a ROM bus format to a format consistent with the processor bus, for example PCI bus format. From the bridge  40 , the BIOS ROM signals are transmitted through connector  27  to the processor  22 A or  22 B via common lines  28 . As shown in FIG. 2, any signals common to both processors  22 A,  22 B are preferably distributed on the motherboard  34  without first passing through the control logic  42 . 
     In this manner, the present invention allows for the configuration of a single motherboard  34  to be compatible with multiple processor architectures, the unique processor architectures being interchangeable and both operable on a common motherboard  34 . 
     While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and in detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. 
     For example, while the above description describes the use of two families of processors of unique architectures, specifically the Alpha™ family and x86™ family of processors, as being compatible with the common motherboard  34 , the utility of the motherboard can be extended beyond the two families of processors to include additional families and additional generations of processors within particular families.