Abstract:
In some embodiments, a ceramic interposer with silicon voltage regulator and array capacitor combination for integrated circuit packages is presented. In this regard, an apparatus is introduced having a bowl-shaped ceramic interposer containing conductive traces, one or more silicon voltage regulator(s) coupled with contacts on a first surface of the ceramic interposer, and one or more array capacitor(s) coupled with contacts on a second surface of the ceramic interposer. Other embodiments are also disclosed and claimed.

Description:
FIELD OF THE INVENTION 
       [0001]    Embodiments of the present invention generally relate to the field of integrated circuit packages and, more particularly, to a ceramic interposer with silicon voltage regulator and array capacitor combination for integrated circuit packages. 
       BACKGROUND OF THE INVENTION 
       [0002]    Silicon voltage regulators are being incorporated into integrated circuit (IC) packages as a way to improve power delivery to the IC device(s). However, the testing and assembly of conventional IC packages are burdensome in that the voltage regulator(s) is/are typically attached to a sub-assembly for electrical testing and then reworked to be removed from the sub-assembly and attached to the IC package substrate. Additionally, accommodations need to be made for bulk decoupling to ensure optimal performance. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements, and in which: 
           [0004]      FIG. 1  is a graphical illustration of a cross-sectional view of a ceramic interposer with silicon voltage regulator and array capacitor combination, in accordance with one example embodiment of the invention; 
           [0005]      FIG. 2  is a graphical illustration of a bottom view of an IC package including a ceramic interposer with silicon voltage regulator and array capacitor combination, in accordance with one example embodiment of the invention; 
           [0006]      FIG. 3  is a graphical illustration of a cross-sectional view of an IC package including a ceramic interposer with silicon voltage regulator and array capacitor combination, in accordance with one example embodiment of the invention; and 
           [0007]      FIG. 4  is a block diagram of an example electronic appliance suitable for implementing an IC package including a ceramic interposer with silicon voltage regulator and array capacitor combination, in accordance with one example embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that embodiments of the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the invention. 
         [0009]    Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. 
         [0010]      FIG. 1  is a graphical illustration of a cross-sectional view of a ceramic interposer with silicon voltage regulator and array capacitor combination, in accordance with one example embodiment of the invention. In accordance with the illustrated example embodiment, sub-assembly  100  includes one or more of ceramic interposer  102 , silicon voltage regulators  104 , array capacitors  106 , interposer bottom surface  108 , interposer wall  110 , lip contacts  112 , array capacitor contacts  114 , and interposer top surface  116 . 
         [0011]    Ceramic interposer  102  represents a bowl shaped interposer containing conductive traces. In one embodiment, ceramic interposer  102  electrically couples silicon voltage regulators  104 , small pitch devices on interposer top surface  116 , with array capacitors  106 , larger pitch components on interposer bottom surface  108 . 
         [0012]    Silicon voltage regulators  104  represent integrated circuits that convert an input voltage to one or more output voltages. Silicon voltage regulators  104  can be controlled and adjusted by input signals. In one embodiment, there are a plurality of voltage input and output contacts on silicon voltage regulators  104  to provide adequate current. In one embodiment, there are a plurality of voltage input and output contacts on silicon voltage regulators  104  to deliver power in multiple phases. 
         [0013]    Array capacitors  106  represents tiles containing many layers of conductive plates to store charge. One skilled in the art would appreciate that array capacitors  106  may be useful to decouple power to and from silicon voltage regulators  104 . 
         [0014]    Interposer  102  may have one or more walls  110  to provide mechanical support and trace routing. In one embodiment, control signals to silicon voltage regulator  104  are routed through wall(s)  110 . Lip contacts  112  and array capacitor contacts  114  are substantially flush to each other and allow sub-assembly  100  to be coupled with a test socket for electrical testing and/or burn-in testing before being attached to a substrate of an IC package. 
         [0015]      FIG. 2  is a graphical illustration of a bottom view of an IC package including a ceramic interposer with silicon voltage regulator and array capacitor combination, in accordance with one example embodiment of the invention. As shown, IC package  200  includes a sub-assembly  100 , ceramic substrate  204  and land grid array (LGA) region  206 . While sub-assembly  100  is shown as including four silicon voltage regulators  104 , sub-assembly  100  may include any number of silicon voltage regulators  104 . In one embodiment, sub-assembly  100  has passed quality testing prior to being attached to ceramic substrate  204 . While LGA region  206  comprises lands for coupling with pins in a socket, in other embodiments other interconnects may be utilized. 
         [0016]      FIG. 3  is a graphical illustration of a cross-sectional view of an IC package including a ceramic interposer with silicon voltage regulator and array capacitor combination, in accordance with one example embodiment of the invention. As shown, IC package  300  includes one or more of sub-assembly  100 , ceramic substrate  302 , package connections  304 , and IC dice  306 . While shown with two silicon voltage regulators  104 , two array capacitors  106  and two IC dice  306 , IC package  300  may include any number of silicon voltage regulators, array capacitors and dice. 
         [0017]    Ceramic substrate  302  represents dielectric material containing electrical traces, not shown, for power and data transmission to and from IC dice  306 . 
         [0018]    Package connections  304  provide an interface between IC package  300  and other components, for example through a socket. In one embodiment, control signals for silicon voltage regulators of sub-assembly  100  are routed through package connections  304  to lip contacts  112  while power and ground are routed through package connections  304  to array capacitor contacts  114 . 
         [0019]    IC Dice  306  may represent any type of integrated circuit device or devices that would benefit from having voltage regulation at the package substrate, for example multi-core processors. 
         [0020]      FIG. 4  is a block diagram of an example electronic appliance suitable for implementing an IC package including a ceramic interposer with silicon voltage regulator and array capacitor combination, in accordance with one example embodiment of the invention. Electronic appliance  400  is intended to represent any of a wide variety of traditional and non-traditional electronic appliances, laptops, desktops, cell phones, wireless communication subscriber units, wireless communication telephony infrastructure elements, personal digital assistants, set-top boxes, or any electric appliance that would benefit from the teachings of the present invention. In accordance with the illustrated example embodiment, electronic appliance  400  may include one or more of processor(s)  402 , memory controller  404 , system memory  406 , input/output controller  408 , network controller  410 , and input/output device(s)  412  coupled as shown in  FIG. 4 . Processor(s)  402 , or other integrated circuit components of electronic appliance  400 , may be housed in a package including a substrate with a ceramic interposer with silicon voltage regulator and array capacitor combination described previously as an embodiment of the present invention. 
         [0021]    Processor(s)  402  may represent any of a wide variety of control logic including, but not limited to one or more of a microprocessor, a programmable logic device (PLD), programmable logic array (PLA), application specific integrated circuit (ASIC), a microcontroller, and the like, although the present invention is not limited in this respect. In one embodiment, processors(s)  402  are Intel® processors. Processor(s)  402  may have an instruction set containing a plurality of machine level instructions that may be invoked, for example by an application or operating system. 
         [0022]    Memory controller  404  may represent any type of chipset or control logic that interfaces system memory  406  with the other components of electronic appliance  400 . In one embodiment, the connection between processor(s)  402  and memory controller  404  may be referred to as a front-side bus. In another embodiment, memory controller  404  may be referred to as a north bridge. 
         [0023]    System memory  406  may represent any type of memory device(s) used to store data and instructions that may have been or will be used by processor(s)  402 . Typically, though the invention is not limited in this respect, system memory  406  will consist of dynamic random access memory (DRAM). In one embodiment, system memory  406  may consist of Rambus DRAM (RDRAM). In another embodiment, system memory  406  may consist of double data rate synchronous DRAM (DDRSDRAM). 
         [0024]    Input/output (I/O) controller  408  may represent any type of chipset or control logic that interfaces I/O device(s)  412  with the other components of electronic appliance  400 . In one embodiment, I/O controller  408  may be referred to as a south bridge. In another embodiment, I/O controller  408  may comply with the Peripheral Component Interconnect (PCI) Express™ Base Specification, Revision 1.0a, PCI Special Interest Group, released Apr. 15, 2003. 
         [0025]    Network controller  410  may represent any type of device that allows electronic appliance  400  to communicate with other electronic appliances or devices. In one embodiment, network controller  410  may comply with a The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 802.11b standard (approved Sep. 16, 1999, supplement to ANSI/IEEE Std 802.11, 1999 Edition). In another embodiment, network controller  410  may be an Ethernet network interface card. 
         [0026]    Input/output (I/O) device(s)  412  may represent any type of device, peripheral or component that provides input to or processes output from electronic appliance  400 . 
         [0027]    In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form. 
         [0028]    Many of the methods are described in their most basic form but operations can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the present invention. Any number of variations of the inventive concept is anticipated within the scope and spirit of the present invention. In this regard, the particular illustrated example embodiments are not provided to limit the invention but merely to illustrate it. Thus, the scope of the present invention is not to be determined by the specific examples provided above but only by the plain language of the following claims.