Abstract:
A method of calibrating a transceiver circuit including transmission circuitry for processing an input signal to produce an output signal including the input signal modulated onto a carrier signal, and reception circuitry arranged to take a modulated signal including a signal modulated onto a carrier signal and to output the signal demodulated from the carrier signal. The method includes: selectively coupling the transmission circuitry to the reception circuitry; introducing a reference signal into the transmission circuitry, the reference signal causing a plurality of components of different frequencies to be present in a calibration signal in the reception circuitry; 
     measuring the power, and typically the received signal strength indication (RSSI) of the calibration signal including the plurality of components; and adjusting operation of the transmission and reception circuitry to increase the amplitude of a first set of the components relative to the amplitude of a second set of the components.

Description:
FIELD OF THE INVENTION 
       [0001]    This invention relates to a method of calibrating a transceiver circuit and to a transceiver circuit. 
       BACKGROUND OF THE INVENTION 
       [0002]    The proliferation of mobile communication devices including smart phones, notepads and laptops has resulted in significant efforts for efficient wireless transmission through adoption of new standards, hardware improvements and more sophisticated network management. As a result, there has been an ever increasing pressure to reduce cost, size and power consumption of such systems. This has driven designers to develop transceivers with higher levels of integration with much of the work focused on replacing the external components with integrated counterparts. This is not a trivial matter and often necessitates design of completely new transceiver architectures to achieve fewer off chip components. 
         [0003]    On the other hand, there is a very high demand for performance from the modern integrated transceivers in order to achieve high modulation orders and hence to fulfill the high data rates driven by today&#39;s wireless and mobile applications. In this respect, the transceivers are required to provide an exceptionally good noise figure performance, linearity, matching, IQ (in-phase/quadrature) phase/gain balance and radio frequency (RF) local oscillator (LO) phase noise performance. While the latter is determined by the performance of the synthesizer circuit, the rest of the parameters are dependent on the components used within the transmit and receive chains. 
         [0004]    Given the emphasis on integration and low cost, there is a major push for the adoption of, for example, sub-micron CMOS technology for the implementation of transceiver technology. The key characteristic of the technology is the low cost for implementing the digital functions but poor analogue and RF performance compared with other specialized technologies. Hence any use of digital functions in CMOS for improving the transceiver performance is very desirable and enables the use of the technology in high data rate wireless communication systems. 
       BRIEF SUMMARY OF THE INVENTION 
       [0005]    According to a first aspect of the invention, there is provided a method of calibrating a transceiver circuit, the circuit comprising transmission circuitry arranged to take at an input an input signal and to process the input signal so as to produce at an output an output signal comprising the input signal modulated onto a carrier signal; and reception circuitry arranged to take at an input a modulated signal comprising a signal modulated onto a carrier signal and to output at an output the signal demodulated from the carrier signal, in which the method comprises:
       selectively coupling the transmission circuitry to the reception circuitry;   introducing a reference signal into the transmission circuitry, the reference signal causing a plurality of components of different frequencies to be present in a calibration signal in the reception circuitry;   measuring the power of the calibration signal including the plurality of components; and   adjusting the operation of the transmission and reception circuitry so as to increase the amplitude of a first set of components comprising at least one of the components relative to the amplitude of a second set of the components comprising at least one of the components.       
 
         [0010]    As such, rather than having to measure the power distribution within the calibration signal, a simple single measure of power can be taken for the whole measurement. This can then be used to calibrate the operation of the circuit. Typically, there will be no need to determine the distribution of the power over frequency. 
         [0011]    The step of introducing the reference signal may comprise introducing the reference signal at the input of the transmission circuitry. The power of the calibration signal may be measured at the output of the reception circuitry. 
         [0012]    The transceiver circuit may comprise a signal source arranged to generate the reference signal, and so the step of introducing the reference signal may comprise introducing the reference signal using the signal source. The signal source may be a numerically controlled oscillator. 
         [0013]    The transmission circuitry may comprise a transmission local oscillator arranged to produce a transmission local oscillator signal and a transmission mixer having inputs for the transmission local oscillator signal and the input signal and an output and being arranged to mix the signals at its input and output a mixed signal at its output. Similarly, the reception circuitry may comprise a reception local oscillator arranged to produce a reception local oscillator signal and a reception mixer having inputs for the reception local oscillator signal and the modulated signal and an output and being arranged to mix the signals at its input and output a mixed signal at its output. 
         [0014]    The step of coupling the transmission circuitry to the reception circuitry may comprise introducing the mixed signal output by the transmission mixer as the modulated signal of the reception circuitry. Typically, the transceiver may comprise a switch that selectively couples the mixed signal output by the transmission mixer to one of the inputs of the reception mixer. The method may comprise amplifying the mixed signal output by the transmission mixer before introducing it to the reception mixer; typically, the amplification would occur in a low noise amplifier of the transmission circuitry. The reception circuitry may comprise a further low noise amplifier coupled to one of the inputs of the reception mixer, which is not used to amplify the mixed signal output from the transmission mixer. 
         [0015]    In such a case, the calibration signal may comprise a first component representing the reference signal which has been increased in frequency by the transmission local oscillator signal and decreased in frequency by the reception local oscillator signal. The frequency of the first component can therefore be seen to be a sum of the frequencies of the reference signal and the transmission local oscillator signal, less the frequency of the reception local oscillator signal. Thus, the first component may be a member of the first set of components. 
         [0016]    The calibration signal may also comprise a second component, which represents leakage of the transmission local oscillator signal and of any DC offset of the transmission circuitry. As such, any DC leakage will have been increased in frequency by the transmission local oscillator signal (where it is joined by any transmission local oscillator leakage) and then down converted by the reception local oscillator. As such, the frequency of the second component may be a difference in frequencies between the transmission and reception local oscillator signals. The second component may be a member of the second set of components. 
         [0017]    The calibration signal may comprise a third component, which is present at a frequency which is the difference in frequency between the transmission and reception local oscillator signals, less the reference frequency. This occurs due to phase (or “IQ”) imbalances in the transmission circuitry. The third component may be a member of the second set of calibration components. 
         [0018]    The calibration signal may comprise a fourth component, at zero frequency (DC). This represents the DC offset of the reception circuitry and leakage of the reception local oscillator signal. The fourth component may be a member of the second set of calibration components. 
         [0019]    Each of the components may have a corresponding component at negative frequency, due to phase/gain (or “IQ”) imbalances in the reception circuitry. Each negative component is a member of the second set of calibration components. 
         [0020]    The step of adjusting the operation of the transmission and reception circuitry may comprise configuring the circuit so that changing at least one variable of the transmission or reception circuitry causes at least one of the components to change in power relative to the other components, and then varying until an extreme, typically a minimum, in the measured power is reached. This step may comprise doing so several times, for different components. Each variable may be selected from the group comprising: the frequency of the transmission local oscillator, the frequency of the reception local oscillator, the frequency of the reference signal and a pass band of a low pass filter, whether analogue or digital. 
         [0021]    For example, in order to compensate for the presence of the fourth component, the transmission circuitry will not be coupled to the reception circuitry (the switch, if present, will be open). No signal will be applied to the input of the reception circuitry (which may be terminated appropriately). Thus, with no signal to be amplified, the only component of the calibration signal will be the fourth component, and so the measured power will be indicative of the presence of the fourth component. The reception circuitry can then be operated to minimize the power measurement and so the fourth component. In one embodiment, the reception circuitry will comprise at least one digital-to-analogue converter which outputs a DC bias, typically as part of a variable gain amplifier that acts upon the output of the reception mixer; the variable to be modified will then be the DC bias. 
         [0022]    In another example, which would typically occur after the example immediately above, the transmission local oscillator signal would be set to a first frequency and the reception local oscillator signal would be set to a second frequency less than the first frequency (although potentially only by a few megahertz, say less than  5  MHz), the transmission circuitry would be coupled to the reception circuitry and the reference signal set to zero frequency (DC). Minimizing the measured power will therefore reduce the negative frequency equivalent of the second component, and so also the second component. 
         [0023]    In yet another example, which would typically occur after the example immediately above, the transmission local oscillator signal would be set to a first frequency and the reception local oscillator signal would be set to a second frequency less than the first frequency (although potentially only by a few megahertz, say less than  5  MHz), the transmission circuitry would be coupled to the reception circuitry and the reference signal set to a frequency greater than the difference between the frequencies of the transmission and reception local oscillator signals. Thus, adjusting the response of the transmission circuitry to different phase signals, and the relative gain of differently phased signals (that is, phase and gain correction) can be used to minimise the measured power; this will have the effect of reducing the third component. 
         [0024]    In a further example, the reception circuitry also has a signal generator arranged to generate a reception reference signal, which is mixed with the calibration signal, the power of the calibration signal being measured after the mixing with the reception reference signal. Furthermore, the reception circuitry may comprise a decimation filter, which acts on the calibration signal after it has been mixed with the reception reference signal, the decimation filter having a passband; typically this will be symmetrical about zero frequency. In this example, the reception reference signal can be used to shift the mixed calibration signal in frequency before passing through the decimation filter. As such, whereas the first component and its negative component would otherwise be symmetric about zero frequency, by shifting the frequency, it is possible to include the negative component corresponding to the first component fall within the passband of the decimation filter and so contribute to the power being measured, but with the first component outside of the passband and so not contributing to the power. Therefore, by adjusting the gain and phase correction components of the reception circuitry, the negative component corresponding to the first component can be reduced. 
         [0025]    According to a second aspect of the invention, there is provided a transceiver circuit, comprising transmission circuitry arranged to take at an input an input signal and to process the input signal so as to produce at an output an output signal comprising the input signal modulated onto a carrier signal; and reception circuitry arranged to take at an input a modulated signal comprising a signal modulated onto a carrier signal and to output at an output the signal demodulated from the carrier signal, in which the circuit further comprises:
       a switch arranged to selectively couple the transmission circuitry to the reception circuitry;   a reference signal source arranged to introduce a reference signal into the transmission circuitry, the reference signal causing a plurality of components of different frequencies to be present in a calibration signal in the reception circuitry; and   power measurement circuitry arranged to measure the power of the calibration signal including the plurality of components.       
 
         [0029]    As such, rather than having to measure the power distribution within the calibration signal, a simple single measure of power can be taken for the whole measurement. This can then be used to calibrate the operation of the circuit. The circuit may not comprise a circuit which is arranged to determine the distribution of the power of the calibration signal over frequency. 
         [0030]    The reference signal may be introduced at the input of the transmission circuitry. The power of the calibration signal may be measured at the output of the reception circuitry. 
         [0031]    Typically, the signal source will be a numerically controlled oscillator. This is a particularly convenient method of carrying out the calibration of the circuit, particularly as described in the first aspect of the invention. 
         [0032]    The transmission circuitry may comprise a transmission local oscillator arranged to produce a transmission local oscillator signal and a transmission mixer having inputs for the transmission local oscillator signal and the input signal and an output and being arranged to mix the signals at its input and output a mixed signal at its output. Similarly, the reception circuitry may comprise a reception local oscillator arranged to produce a reception local oscillator signal and a reception mixer having inputs for the reception local oscillator signal and the modulated signal and an output and being arranged to mix the signals at its input and output a mixed signal at its output. 
         [0033]    Typically, the switch may selectively couple the mixed signal output by the transmission mixer to one of the inputs of the reception mixer. The transmission circuitry may further comprise an amplifier (typically a low noise amplifier) arranged to amplify the mixed signal output by the transmission mixer before introducing it to the reception mixer. The reception circuitry may also comprise a further amplifier (typically a low noise amplifier) coupled to one of the inputs of the reception mixer, which is not used to amplify the mixed signal output from the transmission mixer. 
         [0034]    The reception circuitry may also have a signal generator arranged to generate a reception reference signal, which is mixed with the calibration signal, the power measurement circuitry being arranged so as to measure the power of the calibration after the mixing with the reception reference signal. Furthermore, the reception circuitry may comprise a decimation filter, which acts on the calibration signal after it has been mixed with the reception reference signal, the decimation filter having a passband; typically this will be symmetrical about zero frequency. In this example, the reception reference signal can be used to shift the mixed calibration signal in frequency before passing through the decimation filter. As such, whereas the first component and its negative component would otherwise be symmetric around zero frequency, by shifting the frequency, it is possible to include the negative component corresponding to the first component fall within the passband of the decimation filter and so contribute to the power being measured, but with the first component outside of the passband and so not contributing to the power. 
         [0035]    The circuit may comprise a controller, such as a microprocessor. Typically, this will be arranged to control the circuit so as to carry out the method of the first aspect of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0036]    There now follows, by way of example only, an embodiment of the invention, described with reference to the accompanying drawings, in which: 
           [0037]      FIG. 1  shows an example transceiver circuit in accordance with an embodiment of the invention; 
           [0038]      FIG. 2  shows the structure of the reception transceiver signal processor (TSP) of  FIG. 1 ; 
           [0039]      FIG. 3  shows the structure of the transmission transceiver signal processor (TSP) of  FIG. 1 ; 
           [0040]      FIG. 4  shows the circuit of  FIG. 1 , configured for use in a method in accordance with the embodiment of the invention; 
           [0041]      FIG. 5  shows a graph of power against frequency for the configuration of  FIG. 4 ; 
           [0042]      FIG. 6  shows a graph of power against frequency for the configuration of  FIG. 4 , at the start of a first calibration step; 
           [0043]      FIG. 7  shows an equivalent graph to that of  FIG. 6 , after initial correction; 
           [0044]      FIG. 8  shows an equivalent graph to that of  FIG. 7 , after further correction; 
           [0045]      FIG. 9  shows an equivalent graph to that of  FIG. 5 , at the start of a second calibration step; 
           [0046]      FIG. 10  shows an equivalent graph to that of  FIG. 9 , after correction; 
           [0047]      FIG. 11  shows an equivalent graph to that of  FIG. 5 , at the start of a third calibration step; 
           [0048]      FIG. 12  shows an equivalent graph to that of  FIG. 11 , after initial correction; 
           [0049]      FIG. 13  shows an equivalent graph to that of  FIG. 12 , after further correction; 
           [0050]      FIG. 14  shows an equivalent graph to that of  FIG. 5 , at the start of a fourth calibration step; 
           [0051]      FIG. 15  shows an equivalent graph to that of  FIG. 14 , after initial processing; 
           [0052]      FIG. 16  shows an equivalent graph to that of  FIG. 15  after further processing; 
           [0053]      FIG. 17  shows an equivalent graph to that of  FIG. 16  after yet further processing; and 
           [0054]      FIG. 18  shows an equivalent graph to that of  FIG. 5 , after calibration has been completed. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0055]    A simplified block diagram of the key structure and blocks within a typical 2×2 MIMO (multiple input, multiple output) integrated transceiver, used as an example here, are shown in  FIGS. 1 to 3 , although calibration algorithms are applicable generally to any N×M MIMO and also to MO (single input, single output) transceivers. Note that the transceiver signal processor (TSP)  10  of  FIG. 1  contains the RXTSP (reception TSP)  11  and TXTSP (transmission TSP)  12  of  FIGS. 2 and 3 , respectively. The digital IQ (in-phase/quadrature) interface is used to interface the transceiver to a baseband circuit where the received data is processed and/or data is supplied to the transmitter for the up conversion to a radio frequency (RF) signal. 
         [0056]    Regarding  FIG. 1 , one complete RX (reception) chain and one TX (transmission) chain of the example 2×2 MIMO transceiver will be used in the algorithm explanation. Calibration of other TX/RX chains in N×M MIMO transceivers is exactly the same and will not be repeated here for clarity. Also, only one low noise amplifier (LNA) is active and will be used to calibrate RX DC offset and RX local oscillator (LO) leakage. RF loopback via switch  14  from the output of the TX chain to the input (post LNA) of the RX chain will be used during calibration hence only one TXPAD (TX power amplifier driver) and corresponding switch are left to construct TX to RX RF loopback. Whilst using RF loopback option all test signals are generated by on chip digital blocks (NCOs and digital filters) and key measurement block is digital received signal strength indicator (RSSI) which in fact measures received signal power. No external test equipment need be required for the calibration process. 
         [0057]    On the RXTSP side, during calibration all General Purpose FIR (finite impulse response) filters are bypassed/powered down as well as digital AGC (adaptive gain control) block. FIR filters take longer to configure since there would be a need to upload a significant number of coefficients. Hence, the reason to use a decimation filter as discussed below which has fixed coefficients and there is only a need to change decimation ratio to change its pass band characteristics, if required. Similarly, the same applies for TXTSP block and there is no need for any digital filtering within TXTSP block so both general purpose FIR filers as well as interpolation filter are bypassed/powered down. 
         [0058]    In this embodiment, test signals are generated by on chip NCOs (numerically controlled oscillators), a TX NCO  15  coupled to the input of the TX chain and a RX NCO  16  coupled to the output of the RX chain. The only measurement that is required is performed by digital RSSI. Having in mind that both baseband and on chip microcontroller can control NCOs and read RSSI means that both circuits can execute the calibration procedure. Of course, it is recommended to assign this to on chip microcontroller unit (MCU)  20  saving time and processing power of baseband processor to deal with other tasks. 
         [0059]    Digital RSSI block  17  has embedded averaging filter where averaging window is programmable. Maximum averaging window size is 1024 clock cycles, in the case of this example. Averaging RSSI output improves the measurement accuracy. During calibration process all is required is to read RSSI output after averaging is completed. 
         [0060]    Taking now the circuit as shown in  FIG. 4  (which shows a simplified block diagram of the transceiver without the blocks that are not used in calibration), the first step is to analyze the scenario with the following setup and/or algorithm:
       Drive TXTSP with digital n-bit two&#39; complement DC (12-bit in this example) i.e.
           TXI=011111111111=+max 12-bit word   TXQ=10000000000=−max 12-bit word   This can be done through an internal test option, hence there is no need to engage digital IQ interface to connect to a baseband processor.   
           Bypass IQ Gain Correction, IQ Phase Correction and TX DC Correction TXTSP blocks. Keep INVERSE sine filter running.   Tune TX LPF (low pass filter) pass band/stop band to be able to filter DAC images which are consequence of zero hold effect of the DACs.   Tune TX Synthesizer to a frequency f TXLO . Tune RX Synthesizer to f RXLO  offset from f TXLO  by few MHz and keep f TXLO &gt;f RXLO .   Set TXPAD gain not to overload RX mixer.   Close RF Loopback switch  14 .   Power down RXLNA 2  (optional).   Set RXVGA 1  (variable gain amplifier 1) (RXTIA transimpedance amplifier) and RXVGA 2  (RXPGA—programmable gain amplifier) gain not to overload ADCs (analogue to digital converters).   Open RXLPF (low passband) pass band as much as possible to clearly see all tones generated in this setup.   Bypass IQ Gain Correction, IQ Phase Correction and RX DC Correction RXTSP blocks. Bypass Decimation filter to see all tones generated by the whole setup.   Set RXNCO  16  frequency to 0. Set TXNCO  15  to f TXNCO  where f TXLO −f RXLO &gt;f TXNCO .       
 
         [0075]    The test setup described above uses minimum filtering to clearly show unwanted tones to be cancelled or calibrated out. The spectrum of  FIG. 5  shows RX output while the transceiver works in RF loopback mode (that is, with switch  17  closed). Tones and the reasons for their existence are given below:
       (1) TX DC and TX LO leakage. It is down converted by f RXLO  hence it appears in base band frequencies at f TXLO −f RXLO      (2) This is wanted TX sideband. Offset from TX LO leakage by TXNCO frequency f TXNCO .   (3) Unwanted TX sideband caused by TX IQ imbalance.   (4) RX DC offset and RX LO leakage. Appears at DC.   (3a) RX unwanted side band caused by component (3)   (1a) RX unwanted side band caused by component (1)   (2a) RX unwanted side band caused by component (2)       
 
         [0083]    Note that all tones at negative frequencies are the consequence of RX IQ imbalance. 
         [0084]      FIG. 5  shows that a single measurement can capture all the tones that are required to be cancelled. There are two problems with this approach. There would be a need to perform complex fast Fourier transform (FFT) which is computationally intensive i.e. takes a long time to execute and the circuitry for FFT is complex and power hungry. The novel approach proposed here is to use digital RSSI for measurement instead of FFT. RSSI can accurately measure only the power for a given spectrum and does not distinguish between multiple tones as in  FIG. 5 . However, by carefully choosing the order of calibration steps and with the help of digital filters and/or analogue LPFs as well as the Transmitter NCO (TXNCO) and Receiver NCO (RXNCO) this is possible, as detailed in the next sections. 
         [0085]    For the RX DC offset and RX LO leakage calibration, the TX setup is not relevant. Hence, the following algorithm is presented for the RX only:
       Tune RX LO Synthesizer to f RXLO  system target frequency.   Open RF Loopback switch  14 .   Keep RXLNA 2  powered up to take into account RX LO leakage which may happen through RXLNA 2  path. It is recommended to terminate LNA inputs with 50 Ohm in this example to minimize the noise which LNA can pick up through open inputs.   Set RXVGA 1  (RXTIA) and RXVGA 2  (RXPGA) gain not to overload ADCs.   RXLPF set up is not critical since DC is being measured.   Bypass IQ Gain Correction, IQ Phase Correction and RX DC Correction       
 
         [0092]    RXTSP blocks. Bypass Decimation filter.
       Set RXNCO frequency to 0.       
 
         [0094]    RSSI measures the level of DC as shown in  FIG. 6 . There are two options to minimize DC and LO leakage. 
         [0095]    First, one can use DC compensation DACs (digital to analogue converters) that are typically available in RXVGA 1  (RXTIA)  18  and alter the values to minimize RSSI output. This will reduce DC as shown in  FIG. 7 . 
         [0096]    There will be some residual DC due to limited resolution of on chip DC compensation DACs. This can be further improved by enabling RX DC cancelation loop in RXTSP. The loop is running all the time so it can track and correct any RX DC offset which may be caused by changing RX LO frequency, RF input signal level due to IP2 and temperature drift. A small residual DC will still be there due to LSB resolution of n-bit ADCs (12-bit considered in this example transceiver). After correcting for this, the DC component  4  can be seen to be reduced as shown in  FIG. 8 . 
         [0097]    The setup is now presented to have only TX DC Offset and TX LO leakage tone. This can be achieved as follows.
       Bypass IQ Gain Correction, IQ Phase Correction TXTSP blocks. Keep INVERSE sine filter and TX DC Correction block running.   Tune TX Synthesizer to f TXLO . Tune RX Synthesizer to f RXLO  offset from f TXLO  by few MHz and keep f TXLO &gt;f RXLO .   Set TXPAD gain not to overload RX mixer.   Close RF Loopback switch  14 .   Power down RXLNA 2  (optional).   Set RXVGA 1  (RXTIA) and RXVGA 2  (RXPGA) gain not to overload ADCs.   Open RXLPF pass band as much as possible to clearly see TX DC offset and TX LO leakage tone.   Bypass IQ Gain Correction, IQ Phase Correction and Decimation filter RXTSP blocks.   Keep RXVGA 1  (RXTIA) DC offset DAC values determined above. Keep RX DC cancelation loop running. This should keep DC at the level as shown above.   Set RXNCO frequency to 0. Set TXNCO frequency to 0.       
 
         [0108]    Spectrum driving RSSI is shown in  FIG. 9 . In fact RSSI measures the level of two tone signal. However tones are correlated i.e. (1a) is unwanted side band while (1) is wanted side band. (1a) is due to RX IQ imbalance. In other words, minimizing (1) tone (1a) will go down by the same amount. RSSI output will be composite power level of those two tones and is a valid measure. If RSSI output is minimized then TX DC offset and TX LO leakage are minimized, disregarding the presence of two (correlated) tones. 
         [0109]    In order to do so, we first alter set up of on chip DC calibration DACs if available to minimize RSSI output. Then alter TX IQ DC correction TXTSP block parameters to minimize RSSI output i.e. to further minimize residual TX DC offset and TX LO leakage. An example spectrum after this calibration is shown in  FIG. 10  of the accompanying drawings. It is important to note that component (1a) will probably disappear into measurement noise floor as it is lower level than (1) and since it is possible to reduce (1) by a significant amount, (1a) goes down for the same amount, hence hitting the measurement noise floor. 
         [0110]    In order to correct for any errors in TX IQ gain and phase error calibration, there will be four tones however not all are related, see  FIG. 11 . For example tones  2  and  2   a  are correlated as well as tones  3  and  3   a.  However  2  and  3  are not. The goal of this calibration is to minimize tone  3  keeping tone  2  untouched. Tone  2  will introduce an error in RSSI measurement so some filtering will be required. The setup can be as described below.
       Keep the blocks used above active and program them with calibration values obtained so far.   Drive TXTSP with digital n-bit ( 12 -bit in this example circuit) two&#39;s complement DC i.e.
           TXI=011111111111=+max 12-bit word   TXQ=10000000000=−max 12-bit word   This can be done through a test option, no need to engage digital IQ interface for the assistance of a baseband   
           Do not bypass IQ Gain Correction, IQ Phase Correction TXTSP blocks. TX DC Correction should be set with the parameters obtained as before. Keep INVERSE sine filter running.   Tune TX LPF pass band/stop band to be able to filter DAC images which are consequence of zero hold effect of the DACs.   Tune TX LO Synthesizer to f TXLO . Tune RX LO Synthesizer to f RXLO  offset from f TXLO  by few MHz and keep f TXLO &gt;f RXLO .   Set TXPAD gain not to overload RX mixer.   Close RF Loopback switch  14 .   Power down RXLNA 2  (optional).   Set RXVGA 1  (RXTIA) and RXVGA 2  (TXPGA) gain not to overload ADCs.   Open RXLPF pass band as much as possible to clearly see all tones generated in this setup.   Bypass IQ Gain Correction, IQ Phase Correction RXTSP blocks. Set Decimation filter decimation factor to 2 for the filter to provide some filtering. Decimation by 1 is in fact bypass i.e. no filtering at all.   Set RXNCO frequency to 0. Set TXNCO to f TXNCO  where f TXLO −f RXLO &gt;f TXNCO .       
 
         [0126]    Decimation filter  19  has a passband shown in  FIG. 11  that will cut off tones  2  and  2   a,  as shown in  FIG. 12 . This results in two tones  3  and  3   a  in the same way as above, so composite power that is measured by RSSI is a valid number to minimize to cancel TX unwanted signal  3  and  3   a.  Algorithm is similar as presented earlier. First alter on chip analog IQ phase/gain correction parameters, if available, to minimize 
         [0127]    RSSI output. This will be followed by altering TX Gain correction and TX Phase correction parameters of TXTSP digital block to further minimize RSSI output. Resulting spectrum is shown in  FIG. 13 . 
         [0128]    In order to correct for any errors in RX IQ Gain and Phase Calibration, as far as RX IQ imbalance is concerned, there are two tones  2  and  2   a.  The purpose is to change RX IQ gain and RX phase correction parameters to minimize unwanted RX side band  2   a  while keeping wanted side band  2  unaffected. This means that  2  and  2   a  are not correlated as in the above sections. In fact minimizing  2   a  is not going to affect the level of 2. Some filtering is required here to filter out wanted side band  2  and to leave only unwanted  2   a.  Filtering can be achieved by RXNCO set to frequency shift tones  2   a  and  2  so  2   a  appears in pass band and tone  2  in stop band of the decimation filter  19 . The setup for this calibration is as follows:
       Drive TXTSP with digital n-bit (12-bit in this example) two&#39; complement DC i.e.
           TXI=011111111111=+max 12-bit word   TXQ=10000000000=−max 12-bit word   This can be done through the test option, no need to engage the baseband through the digital interface   
           At this point TX is fully calibrated. Keep all correction blocks running and programmed by parameters obtained so far.   Keep INVERSE sine filter running.   Tune TX LPF pass band/stop band to be able to filter DAC images which are consequence of zero hold effect of the DACs.   Tune TX LO Synthesizer to f TXLO  . Tune RX LO Synthesizer to f RXLO  offset from f TXLO  by few MHz and keep f TXLO &gt;f RXLO .   Set TXPAD gain not to overload RX mixer.   Close RF Loopback switch  14 .   Power down RXLNA 2  (optional).   Set RXVGA 1  (RXTIA) and RXVGA 2  (RXPGA) gain not to overload ADCs.   Open RXLPF pass band as much as possible to clearly see all tones generated in this setup.   Activate IQ Gain Correction and IQ Phase Correction RXTSP blocks. Program analogue RX DC Correction block with the parameters obtained before. Keep digital RX DC cancelation loop running.   Set Decimation filter decimation factor to 2 for the filter to provide some filtering. Decimation by 1 is in fact bypass i.e. no filtering at all.   Set RXNCO frequency to shift RX unwanted side band ( 2   a ) into Decimation filter pass band. Set TXNCO frequency to f TXNCO  o where f TXLO −f RXLO &gt;f TXNCO .       
 
         [0145]      FIG. 14  shows the spectrum before the RXNCO causes a frequency shift, and  FIG. 15  afterwards. It can be seen that tone  2  is now outside of the decimation filter  19  passband. After digital filtering by decimation filter  19  ( FIG. 16 ), there is only one tone unwanted  2   a  and RSSI is able to measure its level accurately. Algorithm is similar as before. Alter on chip analogue IQ phase/gain correction parameters, if available, to minimize RSSI output. After that alter RX Gain and RX IQ Phase correction parameters of digital RXTSP to further minimize RSSI output. Resulting spectrum is shown in  FIG. 17 . 
         [0146]    After frequency shifted back (RXNCO frequency set to 0) and bypassing. Decimation filter,  FIG. 18  shows final spectrum of the calibrated chip. Essentially only wanted signal  2  is observed. 
         [0147]    Due to Phase Frequency Detector (PFD) and Charge Pump (CHP) ‘dead zone’ i.e. 
         [0148]    nonlinearity around zero, fractional-N PLLs used in transceivers are prone to generate unwanted spurs when set close to integer-N frequency. These spurs are in the loop pass band and cannot be filtered. A generally adopted solution is to set a constant charge pump current offset to shift PFD/CHP away from zero i.e. operating them into a more linear region. However, this CHP offset value usually depends how far the 
         [0149]    PLL output frequency is away from the nearest integer frequency and has to be tuned accordingly. This is cumbersome and prone to errors. 
         [0150]    On both TX and RX sides, NCO could be used to improve close to integer PLL spurs as follows.
       Set charge pump offset current to some middle value and keep it constant disregarding how close to integer frequency target LO is.   Offset PLL (LO) wanted frequency away from integer frequency by f offset  far enough not to have close to integer spurs.   This introduces PLL output frequency error which can be corrected by setting corresponding NCO to produce −f offset  frequency. In other words the NCO&#39;s ability in providing highly accurate frequencies in digital domain could be utilised in producing the required offset frequency to minimize the total frequency error of the system by compensation for the PLL error.