Abstract:
A method of programming memory cells in a nonvolatile memory, includes applying a programming voltage to a first bitline and setting a second bitline in a floating state. The method further includes applying a compensation voltage to a shield conductive line coupled to the bitline set in the floating state, and setting in the floating state a shield conductive line coupled to the bitline receiving the programming voltage. The method is applicable to the reduction of the parasitic programming phenomena of memory cells by capacitive coupling between bitlines.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a nonvolatile memory comprising at least one bitline and at least one memory cell linked to the bitline, and means for applying a programming voltage to the bitline or for setting the bitline in a floating state. 
         [0003]    The present disclosure also relates to a method of programming memory cells in a nonvolatile memory comprising at least two bitlines to which the memory cells are linked, comprising a step of applying a programming voltage to a first bitline and of setting a second bitline in a floating state. 
         [0004]    2. Description of the Related Art 
         [0005]      FIG. 1  schematically shows, in cross-section, a conventional nonvolatile memory structure M 1  integrated in a semiconductor microchip. The memory comprises a semiconductor substrate  10  in which memory cells  12  are formed. The memory cells  12  are linked by contacts  21  to electrically conductive bitlines BL (BL i−1 , BL i , BL i+1 ). The bitlines BL are embedded in a dielectric material  20  that covers the substrate  10 . The memory cells  12  linked to a same bitline BLi are isolated from memory cells linked to adjacent bitlines BLi−1, BLi+1 by electrically isolating trenches  11 . 
         [0006]    Programming data in a group of memory cells generally comprises a step of erasing the group of memory cells, followed by a step of selectively programming memory cells. During the programming step, the bitlines BL linked to memory cells to be programmed receive a programming voltage Vhv, whereas the bitlines linked to memory cells to remain in the erased state are set in a floating state FLT, that is to say, disconnected from the rest of the circuit. 
         [0007]    Due to the increasingly strict miniaturization specifications for integrated circuits, the distance separating two bitlines tends to reduce as well. A typical distance between two bitlines is for example 0.24 microns. This reduced distance causes a capacitive coupling between adjacent bitlines, resulting in the appearance of electrical field lines  22  between the bitlines receiving the voltage Vhv and the floating bitlines. 
         [0008]    A floating bitline BL i  next to a bitline BL i−1  receiving the voltage Vhv finds itself brought to a parasitic potential Vf 1  that tends to increase under the effect of capacitive coupling. The capacitive coupling effect is even more pronounced when the floating bitline BL i  is surrounded by two lines BL i−1  and BL i+1  receiving the voltage Vhv. The equivalent electrical diagram shown in  FIG. 2  shows that in such a case, the potential Vf 1  of the bitline BL i  may be estimated by means of the following equation: 
         [0000]        Vf 1=2 Vhv*C 2/( C 1+2 C 2)  (equation 1)
 
         [0009]    wherein C 1  is the capacitive coupling between the bitline BL i  and the ground of the circuit, and C 2  is the parasitic capacitive coupling between the bitline and each of the adjacent bitlines BL i−1  and BL i+1 . In practice, the parasitic potential Vf 1  can reach 8 to 9 V for a voltage Vhv on the order of 15 V. 
         [0010]    This parasitic potential Vf 1  can cause an involuntary injection of electrical charges in erased memory cells, leading to a parasitic programming of these memory cells. 
         [0011]    To resolve this problem, the bitlines that do not need to receive the voltage Vhv may be grounded. This solution is however not desirable due to the existence of leakage currents i 1  circulating between the memory cells  12  and ground (in particular between the drain regions of the memory cells and ground), and leakage currents i 2  circulating between the memory cells receiving the voltage Vhv and the memory cells linked to floating bitlines (currents passing under the isolating trenches  11 ). The leakage currents i 2  are weak, on the nanoampere level, and are limited by the potential Vf 1 . Grounding the bitlines that should not receive the voltage Vhv would lead to a considerable increase of leakage currents i 2 , which could reach the microampere level. Such an increase of leakage currents could cause the voltage source supplying the voltage Vhv, such as a charge pump, to collapse. 
       BRIEF SUMMARY 
       [0012]    One embodiment of the present disclosure provides another way to reduce the increase by capacitive coupling of the electrical potential of floating bitlines. 
         [0013]    Some embodiments of the disclosure relate to a nonvolatile memory comprising at least one bitline and at least one memory cell linked to the bitline, first means for applying a programming voltage to the bitline or for setting the bitline in a floating state, a shield conductive line extending above the bitline, capacitively coupled to the bitline, and second means for applying a compensation voltage to the shield conductive line when the bitline is set in the floating state, and setting the shield conductive line in the floating state when the programming voltage is applied to the bitline. 
         [0014]    According to one embodiment, the first means comprises a first control switch of the voltage of the bitline, and a first latch supplying a control signal of the first control switch as a function of the value of a data bit stored by the latch, and the seconds means comprises a second control switch of the voltage of the shield conductive line, and a second latch supplying a control signal of the second control switch as a function of the value of a data bit stored by the latch. 
         [0015]    According to one embodiment, the first means comprises a first control switch of the voltage of the bitline, and a first latch supplying a control signal of the first control switch as a function of the value of a data bit stored by the latch, and the second means comprises a second control switch of the voltage of the shield conductive line, and control means of the second switch supplying a control signal of the second control switch as a function of the value of the control signal of the first switch. 
         [0016]    According to one embodiment, the control means of the second switch comprises an inverting gate receiving the control signal of the first switch. 
         [0017]    According to one embodiment, the compensation voltage is a ground potential of the memory. 
         [0018]    According to one embodiment, the memory comprises rows of memory cells, a plurality of bitlines, each bitline being capacitively coupled to at least one adjacent bitline, a plurality of shield conductive lines arranged above the bitlines, and means for applying the programming voltage to first bitlines, setting second bitlines in the floating state, setting the shield conductive lines extending above the first bitlines in the floating state, and applying the compensation voltage to the shield conductive lines extending above second bitlines. 
         [0019]    According to one embodiment, a memory cell comprises an access transistor and a floating gate transistor. 
         [0020]    According to one embodiment, a memory cell comprises a floating gate transistor without an access transistor. 
         [0021]    Embodiments of the disclosure also relate to an electronic portable device comprising an integrated circuit IC comprising a nonvolatile memory according to the disclosure. 
         [0022]    Embodiments of the disclosure also relate to a method of programming memory cells in a nonvolatile memory comprising at least two bitlines to which memory cells are linked, comprising a step of applying a programming voltage to a first bitline and of setting a second bitline in a floating state, comprising a step of providing a shield conductive line above each bitline and capacitively coupled to the bitline, and a step of applying a compensation voltage to the shield conductive line coupled to the bitline set in the floating state, and setting in the floating state the shield conductive line coupled to the bitline receiving the programming voltage. 
         [0023]    According to one embodiment, the compensation voltage is a ground potential. 
         [0024]    According to one embodiment, the method comprises the steps of providing first means comprising a first control switch of the voltage of the bitline, and a first latch supplying a control signal of the first control switch as a function of the value of a data bit stored by the latch, and second means comprising a second control switch of the voltage of the shield conductive line, and a second latch supplying a control signal of the second control switch as a function of the value of a data bit stored by the latch. 
         [0025]    According to one embodiment, the method comprises the steps of providing first means comprising a first control switch of the voltage of the bitline, and a first latch supplying a control signal of the first control switch as a function of the value of a data bit B i  stored by the latch, and second means comprising a second control switch of the voltage of the shield conductive line, and control means of the second switch supplying a control signal of the second control switch as a function of the value of the control signal of the first switch. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0026]    These features as well as others of the present disclosure will be disclosed in further detail in the following description, presented in a non-limiting manner in relation with the appended drawings among which: 
           [0027]      FIG. 1 , previously described, is a schematic cross-sectional view of a conventional nonvolatile memory, 
           [0028]      FIG. 2 , previously described, is an electrical diagram illustrating capacitive coupling of bitlines in the memory of  FIG. 1 , 
           [0029]      FIG. 3  schematically shows a cross-sectional view of a nonvolatile memory according to the disclosure, 
           [0030]      FIG. 4  is an electrical diagram illustrating a capacitive coupling of bitlines in the memory of  FIG. 3 , 
           [0031]      FIGS. 5 ,  5 A,  6 , and  6 A show embodiments of programming latches according to the disclosure, 
           [0032]      FIG. 7  shows a first embodiment example of a nonvolatile memory according to the disclosure, 
           [0033]      FIG. 8  shows the structure of memory cells shown in block form in  FIG. 7 , 
           [0034]      FIG. 9  shows a second embodiment example of a nonvolatile memory according to the disclosure, 
           [0035]      FIG. 10  shows a third embodiment example of a nonvolatile memory according to the disclosure, and 
           [0036]      FIG. 11  shows a device equipped with a nonvolatile memory according to the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0037]      FIG. 3  schematically shows, in cross-section, an embodiment of a memory M 2  according to the disclosure, integrated in a semiconductor chip. Memory M 2  comprises a semiconductor substrate  10 , for example of the P type or a P type well, in which memory cells  12  are formed. The region of memory cells  12  shown in cross-sectional view in  FIG. 3  is a transistor drain region, shown along its width. The memory cells  12  are linked by contacts  21  to bitlines BL (BL i−1 , BL i , BL i+1 ), each bitline BL being linked to a plurality of memory cells (not shown in the cross-sectional view). The bitlines BL are embedded in a dielectric material  20  covering the substrate  10 , generally deposited in several layers. The memory cells  12  linked to a same bitline BLi are isolated from memory cells linked to adjacent bitlines BLi−1, BLi+1 by isolating trenches  11 , for example STI trenches (“Shallow Trench Isolation”) of silicon dioxide (SiO2). 
         [0038]    As previously indicated, the programming of data in a group of memory cells generally comprises a step of collectively erasing the group of memory cells followed by a step of programming certain memory cells. During the programming step, the bitlines linked to memory cells to be programmed receive a high programming voltage Vhv, for example 15V, whereas the bitlines linked to memory cells to remain in the erased state are set in the floating state. As shown above, in a conventional memory, the floating bitlines can be subjected to a parasitic electrical potential Vf 1  generated by capacitive coupling, which can lead to a parasitic programming of memory cells. 
         [0039]    To reduce this parasitic potential, memory M 2  comprises shield conductive lines CL (CL i−1 , CL i , CL i+1 ) arranged above the bitlines BL (BL i−1 , BL i , BL i+1 ) and also embedded in the dielectric  20 . Preferably, each bitline BL is associated with a corresponding shield conductive line CL that overlies the bitline. Exceptions may be provided, for example bitlines at the edge of the memory array and that will thus never be between two bitlines receiving voltage Vhv. 
         [0040]    The shield conductive lines CL are arranged at a distance from bitlines BL such that a capacitive coupling exists between each bitline and the shield conductive line overlying it. 
         [0041]    In one embodiment, the distance between the shield conductive lines and the bitlines is identical to the distance between the bitlines, for example 0.4 microns. The bitlines and the conductive lines have the same thickness, for example 0.4 microns, and the same width, for example 0.24 microns. 
         [0042]    In one embodiment, the bitlines are made by etching of a metal layer, for example the layer called “metal 1” in microelectronics, and the shield conductive lines are made by etching of a metal layer of a higher level, for example the layer “metal 2”. The distance between the shield conductive lines and the bitlines is in this case determined by the thickness of a dielectric layer separating the different metal layers. This distance may however be reduced by a local etching of the dielectric layer, to increase the coupling between the shield conductive lines and the bitlines. 
         [0043]    The shield conductive lines CL are not electrically linked to the bitlines and to the memory cells. They are brought to a compensation voltage Vc that is chosen in a manner to reduce if not limit an electrical potential that may appear by capacitive coupling in the bitlines when they are floating. 
         [0044]    More particularly, and as shown in  FIG. 3 :
       a shield conductive line CL, receives the compensation voltage Vc when the bitline BL, to which it is coupled is set in the floating state FLT,   a shield conductive line CL i−1 , CL i+1  is set in the floating state FLT when the bitline BL i−1 , BL i+1  to which it is coupled receives the programming voltage Vhv.       
 
         [0047]      FIG. 4  is an electrical diagram equivalent to  FIG. 3 . A capacitance C 1  represents the conventional capacitive coupling between the bitline BL, and the ground of the circuit. A capacitance C 2  represents the conventional coupling between bitline BL, and each of the adjacent bitlines BL i−1  and BL i+1 . A capacitance C 3  represents the capacitive coupling between floating bitline BL, and shield conductive line CL, receiving compensation voltage Vc. When the adjacent bitlines BL i−1  and BL i+1  receive voltage Vhv and bitline BL, is floating, bitline BL, is brought to a potential Vf 2  that may be estimated by means of the following equation, supposing that Vc=0: 
         [0000]        Vf 2=2 Vhv*C 2/( C 1+2 C 2 +C 3)  (equation 2).
 
         [0048]    By comparing equation 2 with equation 1 which determines the parasitic potential Vf 1  of a bitline present in a conventional memory, it follows that: 
         [0000]        Vf 2 /Vf 1=2 Vhv*C 2/( C 1+2 C 2 +C 3)/2 Vhv*C 2/( C 1+2 C 2) 
         [0000]      that is: 
         [0000]        Vf 2 /Vf 1=( C 1+2 C 2)/( C 1+2 C 2)+ C 3. 
         [0049]    It therefore may be noted that the potential Vf 2  is less than the potential Vf 1 . As a numerical example, if C 1 =C 2 =C 3 : 
         [0000]        Vf 2=¾ Vf 1.
 
         [0050]    Such a reduction of the parasitic potential Vf 2  considerably reduces the risk of involuntarily programming memory cells. If for example Vf 1 =8.7 V, then Vf 2 =6.5 V. As the programming of memory cells is due to the injection of charges by the tunnel effect, the risk of involuntarily programming may be large at 8.7 V and practically inexistent at 6.5 V, if 6.5 V is less than an injection threshold by tunnel effect. It will be noted that the injection threshold is a parameter that is, to some extent, technologically controllable, for example by controlling a tunnel oxide thickness. 
         [0051]    Voltage Vhv is generally applied to the bitlines by programming latches, each receiving the value of a bit to program in a memory cell. If this value is 1 for example, a programming latch supplies voltage Vhv, and if this value is 0 the latch sets the bitline in the floating state. 
         [0052]      FIG. 5  shows a shield and programming latch SPLT i  performing both the control of the voltage of a bitline BL i  and the control of the voltage of shield conductive line CL i  associated with bitline BL i . 
         [0053]    Shield and programming latch SPLT i  comprises a conventional programming latch PLT i  and a shield control circuit SCT i  controlled by programming latch PLT i . 
         [0054]    Programming latch PLT i  comprises a switch transistor SW 1  controlled by a binary latch LT 1   i . Transistor SW 1  links bitline BL i  to a programming line PL receiving voltage Vhv. Binary latch LT 1   i  is electrically supplied by programming line PL. It receives a data bit B i  and a selection signal SEL, and supplies a control signal CS to transistor SW 1 . For example, signal CS goes to 1 when bit B i  and signal SEL are equal to 1. When signal CS is equal to 1, transistor SW 1  conducts and bitline BL i  receives voltage Vhv. More precisely, bitline BL i  receives a voltage equal to Vhv−Vtn, Vtn being the threshold voltage of switch transistor SW 1 . For reasons of simplicity, this threshold voltage will be considered here as zero. When signal CS is equal to 0, bitline BL i  is floating. 
         [0055]    Shield control circuit SCT i  comprises an inverting gate IG and a switch transistor SW 2  that links shield conductive line CL i  to a circuit node supplying compensation voltage Vc (for example ground). Inverting gate IG receives signal CS and supplies an inverted signal /CS to transistor SW 2 . Transistor SW 2  conducts when signal/CS is at 1. The table below summarizes the functioning of the shield and programming latch SPLT i . 
         [0000]    
       
         
               
               
               
               
               
             
           
               
                   
               
               
                 Bit 
                 SEL 
                 CS 
                 Bitline BL i   
                 Shield conductive line CL i   
               
               
                   
               
             
             
               
                 0 
                 0 
                 0 
                 Floating 
                 Vc 
               
               
                 1 
                 0 
                 0 
                 Floating 
                 Vc 
               
               
                 0 
                 1 
                 0 
                 Floating 
                 Vc 
               
               
                 1 
                 1 
                 1 
                 Vhv 
                 Floating 
               
               
                   
               
             
          
         
       
     
         [0056]    Alternatively, as shown in  FIG. 6 , a shield latch SLT i  distinct from programming latch PLT i  may be provided to perform the voltage control of shield conductive line CL i . Shield latch SLT i  comprises a binary latch LT 2   i , inverting gate IG, and transistor SW 2 . Binary latch LT 2   i  receives data bit B i  and selection signal SEL, and its output supplies the same control signal CS as binary latch LT 1   i  to the inverting gate IG. Table 1 above also summarizes the functioning of the combined shield latch SLT i  and programming latch PLT i , which is identical to the functioning of the shield and programming latch SPLT i . 
         [0057]    In an embodiment of latches shown in  FIGS. 5A ,  6 A, programming line PL comprises two conductive tracks PL 1 , PL 2 . Track PL 1  electrically supplies binary latch LT 1   i  and track PL 2  is linked to bitline BL i  by the intermediary of switch SW 1 . This embodiment allows for example the application of a supply voltage Vdd to the binary latch LT 1   i  via track PL 1  to charge bit B i  before an erase phase, and to maintain the binary latch active during the erase phase, whereas track PL 2  is grounded. During the actual programming phrase, tracks PL 1 , PL 2  receive voltage Vhv. 
         [0058]      FIG. 7  shows an implementation example of a nonvolatile memory M 3  according to the disclosure, of the EEPROM type. The memory comprises horizontal rows and vertical rows of memory cells MC, wordlines WL, bitlines BL, and source lines SL. 
         [0059]    The memory cell MC structure is shown in  FIG. 8 . Each memory cell comprises an access transistor AT in series with a floating gate transistor FGT 1  of the tunnel effect programmable and erasable type. Transistor AT has its drain D linked to a bitline BL, its source S linked to the drain of transistor FGT 1  and its gate G linked to a wordline WL. Transistor FGT 1  has its gate G linked to a control gate line CGL and its source linked to a source line SL. 
         [0060]    In reference to  FIG. 7 , bitlines BL are grouped in word columns COL i  comprising N bitlines BL i,0 , BL i,1  . . . BL i,N−1 . Only a single column COL i  is shown in  FIG. 7  for legibility of the figure. The gates G of floating gate transistors FGT 1  of memory cells MC 0 , MC 1 , . . . MC N−1  of a same horizontal row and of a same column COL i  are linked to a column latch column CLT i  by the intermediary of a control gate transistor CGT and a control gate line CGL. The gates G of access transistors AT of memory cells MC 0 , MC 1 , . . . MC N−1  of a same horizontal row are connected to a same wordline WL (WL 0  . . . WL K ), as well as the gate of the control gate transistors CGT. 
         [0061]    Wordlines WL are controlled by a row decoder RDEC 1  that applies to them selection or non-selection voltages as a function of an address value ADD received on its input. 
         [0062]    The drain terminals D of access transistors AT of memory cells MC 0 , MC 1 , . . . MC N−1  of a same vertical row are connected to a same bitline BL (BL i,0 , BL i,1  . . . BL N−1 ). Each bitline BL is overlaid by a shield conductive line CL (CL i,0 , CL i,1  . . . CL N−1 ). Each pair of lines comprising a bitline BL and the corresponding shield conductive line CL is controlled by a shield and programming latch SPLT (SPLT i,0 , SPLT i,1  . . . SPLT i,N−1 ) of the type described above. 
         [0063]    The bitlines of each column are equally linked to sense amplifiers SA (SA 0 , SA 1 , . . . SA N−1 ) by the intermediary of column selection transistors CST and a multiplexing bus MB 1 . The column selection transistors CST are controlled by column selection signals SEL i  supplied by a column decoder CDEC 1  receiving address ADD. Each selection signal SEL i  of a column COL i  is also applied to shield and programming latches SPLT i,0 , SPLT i,1  . . . SPLT i,N−1  linked to bitlines of this column, as well as to the corresponding column latch CLT i . During phases of reading the memory, sense amplifiers SA supply bits B 0 , B 1  . . . B N−1  read in the memory cells belonging to a horizontal row selected by decoder RDEC 1  and a column COL i  selected by the decoder CDEC 1 . 
         [0064]    Now will be described, as an example only, a sequence of erasing and programming a binary word of N bits stored by the memory cells linked to wordline WL 0  and belonging to column COL i . 
         [0065]    Preparation of the Erase-Program Cycle 
         [0066]    Shield and programming latches SPLT (SPLT i,0 , SPLT i,1  . . . SPLT i,N−1 ) receive voltage Vc previously described, as well as the bits B 0 , B 1  . . . B N−1  to program in the memory cells. A programming line PL is used with two conductive tracks PL 1 , PL 2  of the type described above. The track PL 1 , which supplies the binary latches LT 1  of the screen and programming latches SPLT, receives the supply voltage Vdd of the circuit (generally comprised between 1.8 V and 5 V), whereas track PL 2 , linked to the bitlines BL, is grounded. Decoder CDEC 1  activates column latch CLT i  and the latches SPLT by means of selection signal SEL i . 
         [0067]    Erase: depending on the bit value that they received, latches SPLT i,0 , SPLT i,1  . . . SPLT i,N−1  set bitlines BL i,0 , BL i,1  . . . BL i,N−1  of column COL, in the floating state or apply to them the zero voltage present on track PL 2  of programming line PL, this detail being unimportant to the erase process. Column latch CLT i  applies an erase voltage Ver to control gate line CGL by the intermediary of the transistor CGT. Decoder RDEC 1  applies a selection voltage Vsel to wordline WL 0 , chosen in a manner such that transistor CGT lets the voltage Ver pass (at about the threshold voltage of the transistors). Source line SL is connected to ground. Transistors FGT 1  thus receive voltage Ver on their gates G whereas their sources S are grounded. Electrical charges are extracted by tunnel effect from the floating gates of transistors FGT 1 . 
         [0068]    Program: voltage Vhv is applied to the two tracks PL 1 , PL 2  of the programming line PL, such that the shield and programming latches SPLT i,0 , SPLT i,1  . . . SPLT i,N−1  now receive voltage Vhv. Decoder RDEC 1  applies a selection voltage Vsel to wordline WL 0  so that control gate transistor CGT is conducting. Column latch CLT i  grounds control gate line CGL by the intermediary of control gate transistor CGT. Source line SL is set in the floating state. The shield and programming latches SPLT that received a bit equal to 1 apply high voltage Vhv to the bitlines that they control, and set the corresponding shield conductive lines in the floating state. The shield and programming latches SPLT that received a bit equal to 0 set the bitlines that they control in the floating state, and apply the compensation voltage Vc to the corresponding shield conductive lines. Electrical charges are injected by tunnel effect in the floating gates of transistors FGT 1  receiving voltage Vhv. 
         [0069]      FIG. 9  shows an embodiment example of a nonvolatile memory M 4  according to the disclosure, of the FLASH type, of floating gate transistors FGT 2 , each forming a memory cell deprived of an access transistor. The memory comprises wordlines WL k  (WL 0  to WL K−1 ) and bitlines BL n,m (BL 0,0 -BL 0,M−1 , . . . BL N−1,0 -BL N−1,M−1 ). The bitlines BL n,m  are grouped in columns CL n  (CL 0 , . . . CL N−1 ). Each column CL n  comprises M bitlines BL n,0 -BL n,M− . In contrast to memory M 3 , wherein the columns receive bits of different ranks forming a binary word, the columns of memory M 4  receive bits of the same rank of different words. 
         [0070]    Transistors FGT 2  are arranged in horizontal rows and in vertical rows. The gates G of transistors FGT 2  of a same horizontal row are connected to a same wordline WL k  and the sources of these transistors are connected to a source line SL. The drains of transistors FGT 2  of a vertical row are connected to the same bitline BL n,m . 
         [0071]    The bitlines are linked to sense amplifiers SA 0 -SA N−1  by the intermediary of isolation transistors TI, selection transistors CST, and a multiplexing bus MB 2 . Isolation transistors TI are controlled by a read signal RD and are blocked during erasing and programming phases of the memory. When the memory is in the read phase, the output of each sense amplifier SA n  supplies the value of a bit B n  (B 0 -B N−1 ) of a word read in the memory. 
         [0072]    Memory M 4  also comprises shield conductive lines CL n,m  (CL 0,0 -CL 0,m−1 , . . . CL N−1,0 -CL N−1,M−1 ), each overlying a bitline, and shield and programming latches SPLT n,m  (SPLT 0,0 -SPLT 0,M−1 , . . . SPLT N−1,0 -SPLT N−1,M−1 ). 
         [0073]    A row decoder RDEC 2  and a column decoder CDEC 2  receive a binary word address ADD. Row decoder RDEC 2  applies a gate control voltage to each wordline WL k . The value of the gate control voltage depends on the state, selected or non selected, of the wordline, which is a function of the address ADD. 
         [0074]    Column decoder CDEC 2  supplies selection signals SEL (SEL 0  . . . SEL M−1 ) that are also a function of the value of the address ADD. A selection signal SEL of determined rank is applied to the shield and programming latches of the same rank in each column, as well as to the selection transistors CST of bitlines of corresponding rank. For example, signal SEL 0  is applied to the first latches SPLT 0,0 -SPLT N−1,0  of each column and to the selection transistors CST of corresponding bitlines. Signal SEL M−1  is applied to latches SPLT 0,M−1 -SPLT N−1,M−1  of each column and to selection transistors CST of the corresponding bitlines. 
         [0075]    Now will be described, as an example, a step of erasing all the memory cells connected to wordline WL 0  (page erase) and a step of programming a binary word in memory cells connected to this wordline WL 0  and to the first bitline BL n,0  of each column COL 0 -COL N−1 . 
         [0076]    Erase: Row decoder RDEC 2  applies an erase voltage Ver to wordline WL 0 . Source line SL is grounded. Electrical charges are extracted by tunnel effect from the floating gates of all the transistors FGT 2  connected to wordline WL 0 . 
         [0077]    Program: The shield and programming latches SPLT n,m  receive voltages Vhv, Vc previously described, and bits B 0 , B 1  . . . B N−1  to program in the memory cells. Column decoder CDEC 2  activates the shield and programming latches SPLT n,0  controlling the first bitline BL n,0  of each column. Row decoder RDEC 2  applies a programming selection voltage Vprg to wordline WL 0 . The shield and programming latches SPLT that received a bit equal to 1 apply programming voltage Vhv to the bitlines that they control, and set the corresponding shield conductive lines in the floating state. The shield and programming latches SPLT that received a bit equal to 0 set the bitlines that they control in the floating state, and apply compensation voltage Vc to the corresponding shield conductive lines. Electrical charges are injected in the floating gates of transistors FGT 2  receiving voltage Vhv. 
         [0078]      FIG. 10  shows a memory M 5  that differs from memory M 4  in that the shield and programming latches SPLT n,m  are replaced by separate shield latches SLT n,m  and programming latches PLT 0 -PLT N−1 , such as those previously described in relation with  FIG. 6 . The shield latches SLT n,m  are arranged instead of and in the place of the shield and programming latches SPLT n,m  of memory M 4 , and are connected to the shield conductive lines. Programming latches PLT 0 -PLT N−1  are arranged at the bottom of the memory array and are linked to the bitlines BL by the intermediary of multiplexing bus MB 2  and selection transistors CST. Isolation transistors TI controlled by the read signal RD are arranged between the inputs of sense amplifiers SA 0 -SA N−1  and the multiplexing bus MB 2 . 
         [0079]      FIG. 11  schematically shows a portable device HD comprising an integrated circuit IC according to the disclosure. Integrated circuit IC comprises a memory according to the disclosure, for example M 3 , M 4 , or M 5 , a central unit UC, and a communication interface circuit ICT. Communication interface circuit ICT may be of the contact type, for example an ISO 7816 interface circuit, or of the contactless type, for example an ISO14443 or ISO15693 interface circuit functioning by inductive coupling. Portable device HD is for example a chipcard or an electronic tag. Device HD may be generally any type of device equipped with a nonvolatile memory. 
         [0080]    The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.