Abstract:
A silicon accelerometer employing the piezoresistive effect of single crystal silicon to measure the flexure of semiconductor beams supporting a semiconductor mass. In one embodiment a rectangular semiconductor center mass is supported at each corner by a semiconductor beam parallel to one side of the center mass and perpendicular to the adjacent beams, each of the beams having an implanted resistor at the stationary end thereof. The crystal planes and relative orientations of the resistors are selected so that two resistors always increase, and two always decrease their resistance by the same amount as the center mass is displaced, which allows them to be connected in a Wheatstone bridge having a symmetric differential output.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to semiconductor acceleration sensors and specifically to such sensors which employ the piezoresistive effect of single crystal silicon. 
     Semiconductor accelerometers are particularly useful for biomedical, aerospace and automotive applications. The basic semiconductor accelerometer of the prior art comprises a cantilevered silicon beam and mass with a resistor implanted on the beam which changes its value with acceleration due to the stress induced in the beam. A second resistor may be included on the unstressed portion of the structure for temperature compensation and the two resistors connected together to form a half-bridge circuit. One such device is described by L. Roylance and J. Angell in an article entitled &#34;A Batch-Fabricated Silicon Accelerometer&#34;, I.E.E.E. Transactions on Electron Devices, vol. ED-26, No. 12, December 1979, pp. 1911-1917. 
     Another prior accelerometer includes a double-mass and employs the tensile and compressive loading of resistors simultaneously. However, this results in an asymmetric response, and metallization on the flexible portion of the device induces thermal deformation which contributes to nonlinearity and accuracy. 
     There is thus a need for a low-cost, accurate and sensitive semiconductor accelerometer which can be mass-produced using standard planar processing techniques. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention provides a semiconductor accelerometer and a process for the fabrication thereof which overcomes many of the disadvantages of prior art devices. 
     In one embodiment of the present invention a rectangular silicon center mass is supported at each corner by a silicon beam parallel to one side of the center mass and perpendicular to the adjacent beams, each of the beams having an implanted resistor at the stationary end thereof. The crystal planes and the relative orientations of the resistors are selected so that two resistors always increase, and two always decrease their resistance by the same amount as the center mass is displaced, which allows them to be connected in a Wheatstone bridge circuit having a symmetric differential output. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and advantages of the present invention will become apparent, and the invention will be better understood, by reference to the following detailed description and claims when read in conjunction with the following drawings in which like reference numerals represent the same or similar elements throughout the several views, and wherein: 
     FIG. 1 is a plan view of a semiconductor accelerometer according to one embodiment of the present invention; 
     FIG. 2 is a cross-sectional view of the accelerometer of FIG. 1 taken along line A--A; 
     FIG. 3 is an enlarged cross-sectional view of the accelerometer of FIG. 1 taken along line B--B showing the resistor structure in greater detail; 
     FIGS. 4a-4g are cross-sectional views of the accelerometer of FIG. 1 showing various stages in the fabrication thereof; and 
     FIG. 5 is a cross-sectional view of an assembled accelerometer according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to the drawings, there is shown in FIG. 1 a semiconductor accelerometer 10 according to the present invention. Accelerometer 10, referring also to FIG. 2, is formed of silicon and comprises a rectangular center mass portion 12 supported at its corners by four thin, flexible, perpendicular beams 14 each of which is attached at one end to center mass 12 and at the other end to a stationary rim 16. Disposed near the stationary end of each beam 14 is a resistor element 18 composed of semiconductor material of a conductivity type opposite that of beam 14, center mass 12, and rim 16. Each resistor 18 may conveniently be formed of two parallel portions, as shown in FIG. 1, to provide a compact resistance element of the desired value. Also disposed on the surface of accelerometer 10 are metal contact pads 20, 22, 24, 26 and 28, and metal interconnect lines 30 which are in ohmic contacct with resistors 18 for providing contact thereto and to external devices when accelerometer 10 is assembled in a package. Interconnect lines 30 also provide contact to the separate elements of each resistor 18. 
     The symmetrical formation of beams 14 at the periphery of center mass 12 provides a stable, compact structure which is sensitive to acceleration perpendicular to the surface of the mass 12, while it is particularly insensitive to cross-axis acceleration. Further, the disposition of resistors 18 at the stationary ends of beams 14 eliminates any parasitic thermal stress, or bimetal, effects. 
     FIG. 3 shows a resistor 18 in greater detail. Each resistor is formed by implanting a dopant of one conductivity type in an epitaxial layer of the other conductivity type, for example, a p-type region 32 is formed in an n-type epitaxial layer 34. Contact windows 36 in an oxide layer 38 provide for ohmic contact to each end of the p-type region 32 by metal interconnect lines 30 as described above. 
     Referring now to FIGS. 4a-4d, corresponding to the cross section taken along line B--B in FIG. 1, the structure illustrated in FIGS. 1-3 may be formed by the following method. The starting material is an n-type silicon substrate 40 having a (1,0,0) crystal orientation and a resistivity of about 1-10 ohm-cm. A highly doped p++ region 42 is formed in substrate 40, for example, by boron deposition at about 1150 degrees C. Region 42 serves as an etch stop as will be described below. Next, an n-type epitaxial layer 44 is grown on the surface of substrate 40 over region 42 as shown in FIG. 4b. Layer 44 is approximately 0.5-1.0 ohm-cm. and has a thickness of about 10 microns. This defines the thickness of beams 14 and provides a background for resistors 18. An insulating layer 46, e.g., silicon dioxide, is then thermally grown on layer 44 at a temperature of about 1000 degrees C. to a thickness of about 3000 Angstroms. Openings 48 are formed in oxide layer 46 by any known method to form a pattern for resistors 18, which are formed as shown in FIG. 4c by a boron implant at a density of about 10 14  atoms per cm 2 . P-type resistors 18 are composed of regions 32 as described above. An oxide layer 38 is formed by plasma deposition to a thickness of about 3000 Angstroms, followed by annealing at approximately 950 degrees C. to anneal the previous implant. Openings 36 are formed in oxide layer 38 as described above and shown in FIG. 4d, to form contact windows for the metal interconnect lines 30 as shown in FIG. 3. 
     FIGS. 4e-4g, corresponding to the cross section taken along line A--A in FIG. 1, illustrate the steps in the formation of beams 14 and center mass 12. Substrate 40, p++ region 42 and epitaxial n-type layer 44 are formed simultaneously with the corresponding portions of resistors 18 as described above and shown in FIGS. 4a-4d. A layer 50 of nitride is deposited on both sides of the slice to a thickness of about 20,000 Angstroms, and then openings 52 are formed therein as shown in FIG. 4e. Layer 50 is preferably formed of compressive nitride which has the advantage of a low deposition temperature of about 350 degrees C. The nitride may therefore be deposited after the metal patterning to minimize the number of process steps required when the slices are relatively thin and fragile. Because of the built-in compressive stress, layer 50 is virtually pinhole-free and can be formed to a greater thickness without cracking as compared to conventional nitride. Further, compressive nitride is easily removed after plasma etching, which stops at the oxide layer 38 and metal interconnects 30 and 20-28, which must remain intact. Compressive nitride layer 50 may be formed by methods known in the art, for example the process described by A. K. Sinha et al. in the Journal of Electrochemistry, vol. 125, 1978, p. 601 et seq. 
     Openings 52 in the backside nitride layer 50 must be accurately aligned to the resistor 18 pattern previously formed on the front of the slice in order for the resistors 18 to be properly positioned at the stationary end of beams 14. One method of aligning the patterns is to form a plurality of alignment holes (not shown) completely through the slice. However, the preferred method is to use an infrared aligner whereby mask patterns on each side of the slice are aligned simultaneously. One such infrared aligner is available from Research Devices, Inc. 
     Referring to FIG. 4f, a cavity 54 which forms the center mass 12 and bottom portions of beams 14 is formed from the backside of the slice by means of an orientation dependent etch (ODE). An ODE etchant has a different rate of etching along different axes of the silicon crystal. It has been found that one particularly useful etchant is comprised of a 15 per cent mixture of KOH in water with N-propanol at a temperature of approximately 80 degrees C. for about five hours. The etchant automatically follows the (1,1,1) plane of the crystal to produce the sloped sidewalls as shown in FIG. 4f. The KOH etchant stops when it reaches the p++ layer 42. Next, the backside of the slice is coated with a photoresist layer 56 and a pattern is formed into nitride layer 50 on the frontside of the slice. This pattern is used to etch a plurality of slots 58 as shown in FIGS. 4g, 1 and 2, which define beams 14 and center mass 12. First, compressive nitride layer 50 is plasma etched followed by a wet etch of any underlying oxide. The slots are then formed by etching epitaxial layer 44 and p++ region 42 with a silicion etch, for example, a mixture of nitric acid and hydrofluoric acid. Resist layer 56 and the front side nitride layer 50 are then removed, resulting in the structure shown in FIG. 2. The backside nitride layer 50 may either be left on or removed prior to the assembly of accelerometer 10 in a package. 
     FIG. 5 shows one method of assembling accelerometer 10 in a package. Accelerometer 10 is first attached to a header 60 and then a cover 62 is attached thereto, both of which may be silicon. Prior art packaging techniques required indentations or depressions to be etched into header 60 and cover 62 to permit mass 12 to move. A preferred method, illustrated in FIG. 5, is to use an epoxy compound, generally shown by numeral 64, filled with glass beads having a diameter of about 2-4 mils. Header 60 and cover 62 will then be automatically and properly spaced from center mass 12, allowing it to move freely and additionally providing an overload protection device which restricts the movement of mass 12 past a predetermined point under excessive acceleration forces. 
     The sensitivity of an accelerometer fabricated as described above is approximately 0.2 mV/V/g. It will be readily understood the sensitivity, as well as the frequency response of the accelerometer may be varied by varying the dimensions of the device as known in the art and described, for example in the above Roylance et al. reference, as well as a publication by T. Nunn entitled &#34;A Silicon Absolute Pressure Transducer For Biomedical Application&#34;, Stanford Electronics Laboratories Technical Report No. 4610-1, October 1977. There has thus been provided by the present invention a low-cost, sensitive and accurate semiconductor accelerometer suitable for mass production using standard planar semiconductor processing techniques.