Abstract:
A wafer level chip scale package (WLCSP) includes a packaged semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions, and encapsulation material surrounding the semiconductor die except for at least a portion of each of the solder bumps.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/841,100, filed Aug. 30, 2006, which is hereby incorporated by reference. 
     
    
     FIELD OF THE INVENTION  
       [0002]     This invention relates to semiconductor fabrication, and more specifically to a method for fabricating solder bumped wafer-level chip-scale packages (WLCSPs).  
       BACKGROUND OF THE INVENTION  
       [0003]     WLCSPs generally use a metal layer to redistribute very fine-pitch peripheral-arrayed pads on a chip to much larger pitch area-arrayed pads with tall solder joints on the substrate. As a result, solder joint reliability is one of the most critical issues faced during WLCSP fabrication. The present invention is directed toward a new and high-throughput process for assembling WLCSPs on a substrate featuring highly reliable solder joints and protection from moisture penetration.  
         [0004]     There exists a number of U.S. patents directed to improving the reliability of WLCSPs, including U.S. Pat. No. 6,287,893 issued to Elenius, et. al. Elenius teaches a chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. Elenius teaches the use of only one, non-conducting layer to cover redistribution lines.  
         [0005]     U.S. Pat. No. 6,821,876 issued to Yang, et. al. teaches a fabrication method for strengthening flip-chip solder bumps to form a solder bump on a UBM (under bump metallurgy) structure formed over a semiconductor chip, which can prevent the UBM structure against oxidation and contamination and also enhance bondability between the solder bump and UBM structure. This fabrication method is characterized in that before forming the solder bump, a dielectric layer made of BCB (benzo-cyclo-butene) or polyimide is deposited on the UBM structure, and used to protect the UBM structure against oxidation and contamination. Further, before forming the solder bump, a plasma-etching process is performed to remove the dielectric layer. Yang does not teach a fabrication process that includes non-conductive layers in the final structure.  
         [0006]     A process for fabricating reliable solder bumped wafer-level chip-scale packages where the bumps exhibit superior adhesion to the die, minimal resistance, and improved protection from moisture penetration is desired in the art.  
       SUMMARY OF THE INVENTION  
       [0007]     The invention comprises, in one form thereof, a packaged semiconductor device including a semiconductor die having at least one conductive bond pad formed upon a surface of the semiconductor die and a patterned first metallization layer disposed above the surface which provides at least one solder bump pad upon the surface, and electrically couples the at least one conductive bond pad to the at least one solder bump pad. The device also includes a patterned first non-conductive layer above first metallization layer, a patterned under bump metallization (UBM) layer above the first metallization layer and the first non-conductive layer, and a patterned second non-conductive layer over the front surface of the semiconductor wafer and above each of the first metallization layer, the first non-conductive layer, and the UBM layer. The device further includes a solder ball connection elements formed on each region of the UBM layer and encapsulation material around the semiconductor die except for at least a portion of each of the solder balls.  
         [0008]     The invention further comprises, in one form thereof, a method of fabricating a packaged semiconductor by forming a first metallization layer on a surface of a semiconductor wafer, selectively removing portions of the first metallization layer to provide a plurality of solder bump pads. Then forming a like plurality of first non-conductive regions over each of the plurality of solder bump pads, each of the first non-conductive regions having openings to a portion of a corresponding one of the solder bump pads, forming under bump metallurgical (UBM) regions over each of the openings and over a portion of a corresponding one of the first non-conductive regions, and forming a like plurality of second non-conductive regions over at least a portion of each of the first non-conductive regions, and over an outer portion of each of the UBM regions. Then forming solder balls above each of the solder bump pads, dicing the semiconductor wafer to provide individual integrated circuits and encapsulating at least some of the integrated circuits in an encapsulation material leaving unencapsulated at least a portion of each of the solder balls on the at least some of the individual integrated circuits. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     The aforementioned and other features, characteristics, advantages, and the invention in general will be better understood from the following more detailed description taken in conjunction with the accompanying drawings, in which:  
         [0010]      FIG. 1  is a diagrammatical view of a first embodiment of a WLCSP solder bump structure according to the present invention;  
         [0011]      FIG. 2  is a diagrammatical view of a second embodiment of a WLCSP solder bump structure according to the present invention;  
         [0012]      FIG. 3  is a SEM photograph of an edge of a solder ball wetting under an edge of a polyimide layer;  
         [0013]      FIG. 4  is a diagrammatical view of a third embodiment of a WLCSP solder bump structure according to the present invention;  
         [0014]      FIG. 5  is a diagrammatical view of a fourth embodiment of a WLCSP solder bump structure according to the present invention;  
         [0015]      FIG. 6  is a diagrammatical view of a fifth embodiment of a WLCSP solder bump structure according to the present invention; and  
         [0016]      FIG. 7  is a partial side view of a WLCSP according to the present invention.  
     
    
       [0017]     It will be appreciated that for purposes of clarity and where deemed appropriate, reference numerals have been repeated in the figures to indicate corresponding features. Also, the relative size of various objects in the drawings has in some cases been distorted to more clearly show the invention.  
       DETAILED DESCRIPTION  
       [0018]     Referring to  FIG. 1 , there is shown a diagrammatical view of a first embodiment of a WLCSP solder bump structure  10  according to the present invention. The structure  10  is formed on a semiconductor die  12  which is part of a semiconductor wafer  14  when the structure  10  is formed. The semiconductor wafer  14  includes multiple semiconductor die including the semiconductor die  16  shown in  FIG. 1 . A wafer scribe line  18  lies between the semiconductor die  12 ,  16 . The solder bump structure  10  includes a first metallization layer  20 , a first non-conductive layer  22 , a second metallization layer or under bump metallurgical (UBM) layer  24 , a second non-conductive layer  26 , and a solder bump  28 . The first metallization layer  20  is typically a redistribution layer.  
         [0019]     The WLCSP solder bump structure  10  may be formed by first depositing the top metallization layer  20 , then masking and etching the layer to form the desired metallization pattern. The top metallization layer  20  (which may sometimes be considered a seed layer) may be aluminum or other metals. The top metallization layer  20  is then coated with a first non-conductive layer applied over the front (top) surface of semiconductor wafer  14 . The first non-conductive layer (which may sometimes be considered a passivation layer) may be comprised of polyimide, BCB, silicon dioxide, silicon nitride, or other materials known to those skilled in the art. The first non-conductive layer is then patterned to form the first non-conductive layer  22  which allows access to first metal layer  20 . Conventional photolithography techniques may be used to form the patterned openings.  
         [0020]     The wafer  14  with aluminum layer  20  and first non-conductive layer  22  is then coated with UBM metallization which will form the UBM layer  24 . In one embodiment of the present invention, this layer is formed by sputtering onto the wafer  14  between 1000 and 2400 angstroms of Ti followed by between 500 and 3300 angstroms of Ni. This Ti—Ni metallization layer is then masked or etched in one photo process to leave the UBM layer  24  partially covering the first metallization layer  20 , and partially overlapping onto the first non-conductive passivation layer  22 .  
         [0021]     This UBM layer  24  may be a double or triple-metal stack. Other metals which may be used for the UBM layer  24  besides Ti—Ni include, but are not limited to, combinations of Ti, Ni, Au, Cu, or V. For example: Ti—Ni—Au, Ti—Ni—Cu, Ti—Ni—Cu—Au, Al, TiW—Al, Ti—Al, Ti—TiW—Al, Ti—Cu, Ti—Ni—Ag, Ni—V, TiW—Ni—Cu, or Ti—Ni—V. The selected metal(s) should have good adhesion to the first metallization layer  20 . The UBM layer  24  serves one or more of the following purposes: (a) it adheres to the underlying surfaces; (b) it acts as a solder diffusion barrier for inhibiting molten solder from passing into the front surface of semiconductor wafer  14 ; (c) it serves as a “wettable” layer for solderability purposes; and (d) it serves to minimize electrical contact resistance between the solder ball  28  and the conductive bond pad.  
         [0022]     The wafer  14  is then coated with a second non-conductive layer. In one embodiment of the invention the second non-conductive layer is of 1 to 6 microns in thickness, and may be polyimide, BCB, silicon dioxide, silicon nitride, or other materials known to those skilled in the art. Contact openings in this second non-conductive layer are made in one photo step by either etching or photo developing to form the second non-conductive layer  26 . These openings overlap outer edge of the UBM layer  24 , sealing the edge of the metal.  
         [0023]     The stack now has metal contacts upon which the solder ball or bump  28  can be formed by several methods. These methods include, but are not limited to, screen printing solder paste/reflow, electro plating solder, or solder ball attach/reflow. After the wafer level chip scale package is formed (as shown in  FIG. 7 ), the solder bumps  28  can be soldered, brazed, thermocompression bonded, or ultrasonic bonded as with conventional solder bumps to another assembly such a printed circuit board or a lead frame.  
         [0024]      FIG. 2  is a diagrammatical view of a second embodiment of a WLCSP solder bump structure  30  according to the present invention. In the embodiment shown in  FIG. 2 , the wafer  14  is placed in an electroless nickel plating process after the second non-conductive layer  26  is formed to deposit a low intrinsic stress electroless layer and then masked and etched to form the electroless nickel layer  32  only where the UBM layer  24  is exposed. The electroless nickel layer  32  shall be thick enough to separate the UBM layer  24  from metal deposits that will follow such as the solder bump  28 .  
         [0025]     In the embodiment shown in  FIG. 2  the electroless nickel layer  32  is thinner than the second non-conductive layer  26 . With the thinner electroless nickel layer  32 , the solder ball  28  attachment and reflow may result in some solder wetting under the second non-conductive layer  26  (in the case of polyimide) to consume some of the UBM layer  24 . Some solder will also travel over the top of the second non-conductive layer  26 . The resultant structure will “lock” or “seal” the entire under bump structure from moisture penetration as shown in  FIG. 3 .  
         [0026]      FIG. 4  is a diagrammatical view of a third embodiment of a WLCSP solder bump structure  40  according to the present invention. In  FIG. 4 , the periphery of the opening in the first non-conductive layer  20  is covered with a portion of the second non-conductive layer  42 . Thus, a second metallization layer or UBM layer  44  is in contact with the first metallization layer  20  in an opening in the second non-conductive layer  42 , but is not in contact with the first non-conductive layer  20 . Also, the UBM layer  44  is thicker than the second non-conductive layer  42 , and as a result the electroless nickel layer  46  will deposit on a portion of the top surface of the second non-conductive layer  42 , making the coverage of the electroless nickel layer  46  larger than the opening in the second non-conductive layer  42 . This overlapping electroless nickel layer  46  will promote adhesion of the second non-conductive layer  42  to the first metallization layer  20  below it, and provide additional protection from moisture penetration.  
         [0027]     In practice, the covering of the second non-conductive layer  44  (which, in one or more embodiments, is polyimide) by the first non-conductive layer  20  followed by electroless nickel plating of the UBM layer  44  results in a thin first non-conductive layer  22  that is protected by the second non-conductive layer  42  from moisture penetration, and promotes adhesion of the UBM layer  44  to the wafer  14 .  
         [0028]     In the embodiment shown in  FIG. 4 a  stack including the silicon wafer  14 , the first metallization layer  20 , and the first non-conductive layer  22  is assembled as discussed heretofore. The second non-conductive layer is then deposited to cover the first non-conductive layer  14 , and patterned to partially cover the first metallization layer  22 . A polyimide layer is thereafter deposited, masked, and etched to form the second non-conductive layer  42 . The second metallization layer is deposited and patterned to form the UBM layer  44  which partially overlaps the second non-conductive layer  44 . The stack is then subjected to the electroless nickel plating process. The electroless Ni layer  46  is plated where the UBM layer  44  is exposed, and, as a result, partially on top of the second non-conductive layer  42 . The stack is completed by solder ball  28  attachment as discussed above.  
         [0029]      FIG. 5  is a diagrammatical view of a fourth embodiment of a WLCSP solder bump structure  50  according to the present invention. The embodiment of  FIG. 5  includes the silicon wafer  14 , the first metallization layer  20 , the first non-conductive layer  22 , the second non-conductive layer  42 , and the UBM layer  44  shown in  FIG. 4 . A third non-conductive layer  52 , which in one or more embodiments of the present invention is polyimide, and an electroless nickel plated layer  54  to form a stack. The solder bump  28  is formed on the stack. The first non-conductive layer  20 , the second non-conductive layer  42 , and the UBM layer  44  are assembled as discussed heretofore. The third non-conductive layer is then deposited, masked, and etched to form the third non-conductive layer  52  which at least partially overlaps the second conductive layer  42  and overlaps the periphery of the UBM layer  44 . A thin electroless nickel layer is plated on top of UBM layer  44 , only where UBM layer  44  is exposed to form the electroless nickel layer  54 . The upper surface of the electroless nickel layer  54  is lower than the upper surface of the third non-conductive layer  52 . The stack is completed by solder ball  28  attachment as discussed above.  
         [0030]      FIG. 6  is a diagrammatical view of a fifth embodiment of a WLCSP solder bump structure  60  according to the present invention.  FIG. 6  is similar to  FIG. 5  except that In  FIG. 6  the upper surface of the electroless nickel layer  64  is higher than the upper surface of a third non-conductive layer  62 , and as a result the electroless nickel layer  64  will form on top of the inner periphery of the third non-conductive layer  62 , making the electroless nickel area larger than the opening in the third non-conductive layer  62 . This overlapping of electroless nickel layer  60  will promote adhesion of the third non-conductive layer  62  to the UBM layer  44  below it, and provide additional protection from moisture penetration. The stack is completed by solder ball  28  attachment as discussed above.  
         [0031]     In alternative embodiments of the present invention an electroless gold layer may be used instead of the electroless nickel layers.  
         [0032]      FIG. 7  is a partial side view of a WLCSP according to the present invention which contains a WLCSP solder bump structure according to an embodiment of the present invention.  
         [0033]     While the invention has been described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof to adapt to particular situations without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope and spirit of the appended claims.