Abstract:
A device to read a variable resistor has an analog to digital converter (ADC), a first switch and a second switch. The ADC has a first ADC input, a second ADC input and an ADC output. The first switch selectively couples a first voltage indicative of a voltage across a first resistance to the first ADC input. The second switch selectively couples a second voltage indicative of a voltage across a second resistance to the second ADC input. The ADC outputs a signal indicative of a value of the second resistance.

Description:
BACKGROUND 
       [0001]    Technical Field 
         [0002]    The present disclosure relates to measuring an unknown resistance using a reference resistance of a known value. 
         [0003]    The measuring of unknown resistances can be applied in the field of sensor electronic interfaces, for example for automotive applications. 
         [0004]    Description of the Related Art 
         [0005]    The disclosure relates to electronics that manage sensors of a resistive type, for example for the automotive field. The operating principle of these sensors is based upon the variation of an electrical resistance as the physical quantity to be measured varies, with a known law of correspondence, which is possibly proportional. 
         [0006]    Examples of physical quantities that can be measured with this type of solution are: level of liquids (fuel, oil, coolant), temperatures, and positions (engines, axles). 
         [0007]    The circuit of  FIG. 1  measures and converts into a first digital quantity D 2  the voltage V 2  across an unknown resistance R X  (of unknown value). 
         [0008]    Furthermore, the circuit measures and converts into a second digital quantity D 1  the voltage V 1  across a reference resistance of a known value R REF . 
         [0009]    The circuit is arranged for calculating the digital representation D X  of the value of the unknown resistance R X , in particular as ratio between the two voltages. 
         [0010]    With reference to  FIG. 1 , the two resistances R REF  and R X  are set in series and connected between the supply voltage V SUP  and ground gnd. The current I X  that flows in the unknown resistance R X  is 
         [0000]    
       
         
           
             
               I 
               X 
             
             = 
             
               
                 
                   V 
                   1 
                 
                 
                   R 
                   REF 
                 
               
               . 
             
           
         
       
     
         [0011]    Consequently, the value of the unknown resistance R X  can be calculated, as a function of the quantities identified in the circuit, as: 
         [0000]    
       
         
           
             
               R 
               X 
             
             = 
             
               
                 
                   V 
                   2 
                 
                 
                   I 
                   X 
                 
               
               = 
               
                 
                   
                     R 
                     REF 
                   
                    
                   
                     
                       V 
                       2 
                     
                     
                       V 
                       1 
                     
                   
                 
                 = 
                 
                   
                     
                       R 
                       REF 
                     
                      
                     
                       
                         D 
                         2 
                       
                       
                         D 
                         1 
                       
                     
                   
                   = 
                   
                     
                       R 
                       REF 
                     
                      
                     
                       D 
                       X 
                     
                   
                 
               
             
           
         
       
     
         [0012]    where R REF  is the value of the known resistance, and D X  is the digital representation of the value of the resistance R X . 
         [0013]    The unknown resistance R X  may, for example, be the sensitive element of a generic sensor device, such as for example a temperature sensor or a liquid-level sensor (for fuel or oil). 
         [0014]    The two voltages V 1  and V 2  measured across the two resistances R REF  and R X  are supplied to two analog-to-digital converters ADC 1  and ADC 2 . In alternative embodiments, the two analog-to-digital converters ADC 1  and ADC 2  can be implemented as a single converter ADC, in which the input is multiplexed between the input voltages V 1  and V 2 . 
         [0015]    To obtain the result sought, for example it is possible to calculate the ratio between the two voltages across the two resistances considered. In particular, the output of the second A/D converter may be divided by the output of the first A/S converter to supply a value that corresponds to the ratio between the two quantities and that is proportional to the unknown resistance. 
         [0016]    The digital representation D X  of the value of the unknown resistance R X  is typically further processed, for example with filtering steps. 
         [0017]    The known value of the resistance R REF  is considered a scale factor for the digital representation D X  of the value of the unknown resistance R X . Consequently, the operation of multiplication R REF D X  is practically never carried out. 
         [0018]    The background art described above corresponds to what is commonly presented in the specifications of the components that contain the function of interface/management of the resistive sensors. 
       BRIEF SUMMARY 
       [0019]    In the scenario outlined previously, there is consequently felt the need for techniques that will provide devices capable of measuring efficiently unknown resistances. 
         [0020]    In one or more embodiments, the device for measuring an unknown resistance comprises a reference resistance in series with the unknown resistance, and is arranged for measuring a first voltage and a second voltage, across the reference resistance and the unknown resistance, respectively. The device comprises changeover-switch modules, which receive at input the first and second voltages and supply values representing the first and second voltages, and a single analog-to-digital converter, which supplies at output the digital representation of the value of the unknown resistance as a ratio between the values at input to the converter. 
         [0021]    In an embodiment, the analog-to-digital converter contains two negative feedback loops, which function in an alternative way according to the outputs of the changeover-switch modules. 
         [0022]    In various embodiments, the negative feedback loops are first-order continuous-time sigma-delta converters. 
         [0023]    In an embodiment, alternatively one or the other of the two sigma-delta converters has a constant digital output at a high level. 
         [0024]    In various embodiments, each sigma-delta converter comprises an integrator module, a comparator module, and a sequential electronic circuit. 
         [0025]    In an embodiment, the sequential electronic circuit is a D flip-flop. 
         [0026]    In various embodiments, the changeover-switch modules are multiplexers, and the outputs of the sequential electronic circuits are sent back at input as negative feedback and used as selection input of the multiplexer. 
         [0027]    In an embodiment, the outputs of the sequential electronic circuits are filtered and sent at input to a digital divider, which supplies at output the digital representation of the value of the unknown resistance as a ratio between the values representing the first and second voltages. 
         [0028]    In an embodiment, a device comprises: an analog to digital converter (ADC) having first ADC input, a second ADC input and an ADC output; a first switch having a first switch input and a first switch output and which, in operation, receives at the first switch input a first voltage indicative of a voltage across a first resistance and selectively couples the first switch input to the first ADC input; a second switch having a second switch input and a second switch output and which, in operation, receives at the second switch input a second voltage indicative of a voltage across a second resistance and selectively couples the second switch input to the second ADC input, wherein the ADC, in operation, outputs at the ADC output a signal indicative of a value of the second resistance. In an embodiment, the signal indicative of the value of the second resistance is a ratio of a value of the first voltage and a value of the second voltage. In an embodiment, said ADC comprises two negative feedback loops, which, in operation, function according to a value of the first switch output and a value of the second switch output. In an embodiment, said two negative feedback loops comprise first-order continuous-time sigma-delta converters. In an embodiment, in operation, alternatively one or the other of the two sigma-delta converters has a constant digital output at a level of 1. In an embodiment, the ADC comprises an integrator, and each sigma-delta converter comprises a comparator and a sequential electronic circuit coupled to the integrator. In an embodiment, said sequential electronic circuits are D flip-flops. In an embodiment, said first switch and said second switch are multiplexers having respective selection inputs coupled to respective outputs of said sequential electronic circuits of the sigma-delta converters, and, in operation, the outputs of the sequential electronic circuits provide negative feedback of the negative feedback loops. In an embodiment, the device comprises: low-pass filters coupled to respective outputs of said sequential electronic circuits; and a digital divider having respective inputs coupled to respective outputs of the low-pass filters, wherein the digital divider, in operation, outputs a digital representation of the value of the second resistance as a ratio between values representing said first voltage and said second voltage. In an embodiment, the device comprises: a comparator, wherein, said first switch comprises a third switch input, and, in operation the third switch input receives the second voltage and the first switch selectively couples the third switch input to the first ADC input; said second switch comprises a fourth switch input, and, in operation the fourth switch input receives the first voltage and the second switch selectively couples the fourth switch input to the second ADC input; and the comparator, in operation, compares the first voltage and the second voltage and generates a signal to control the first and second switches based on the comparison. In an embodiment, said first and second switches comprise first multiplexers having selection inputs coupled to an output of the comparator. In an embodiment, the ADC, in operation, generates a signal based on a ratio of a voltage at the first input of the ADC and a voltage at the second input of the ADC. In an embodiment, the device comprises: two second multiplexers each having: an input coupled to the ADC output; an input which, in operation, is fixed at a value of 1; and a selection input coupled to the output of the comparator. In an embodiment, the device comprises: a digital-divider having inputs coupled to respective outputs of the second multiplexers, wherein in operation, the digital divider generates a digital representation of a value of the second resistance. In an embodiment, the device comprises: a digital divider having an input coupled to the output of the ADC; and an output multiplexer having a first input coupled to the output of the ADC, a second input coupled to an output of the digital divider, and a selection input coupled to an output of the comparator. 
         [0029]    In an embodiment, a system comprises: a sensor including a variable resistor; and circuitry coupled to the sensor, which, in operation, generates a signal indicative of a resistance of the variable resistor, the circuitry comprising: an analog to digital converter (ADC) having first ADC input, a second ADC input and an ADC output; a first switch having a first switch input and a first switch output and which, in operation, receives at the first switch input a reference voltage and selectively couples the first switch input to the first ADC input; a second switch having a second switch input and a second switch output and which, in operation, receives at the second switch input a second voltage indicative of a voltage across the variable resistor and selectively couples the second switch input to the second ADC input. In an embodiment, the signal indicative of the resistance of the variable resistor is a ratio of a value of the reference voltage and a value of the second voltage. In an embodiment, said ADC comprises: an integrator; and two negative feedback loops, said two negative feedback loops being first-order continuous-time sigma-delta converters having a comparator and a sequential electronic circuit coupled to the integrator. In an embodiment, said first switch and said second switch are multiplexers having respective selection inputs coupled to respective outputs of said sequential electronic circuits of the sigma-delta converters, and, in operation, the outputs of the sequential electronic circuits provide negative feedback of the negative feedback loops. In an embodiment, the circuitry comprises: low-pass filters coupled to respective outputs of said sequential electronic circuits; and a digital divider having respective inputs coupled to respective outputs of the low-pass filters, wherein the digital divider, in operation, outputs a digital signal indicative of the resistance of the variable resistor. In an embodiment, the circuitry comprises: a comparator, wherein, said first switch comprises a third switch input, and, in operation the third switch input receives the second voltage and the first switch selectively couples the third switch input to the first ADC input; said second switch comprises a fourth switch input, and, in operation the fourth switch input receives the reference voltage and the second switch selectively couples the fourth switch input to the second ADC input; and the comparator, in operation, compares the reference voltage and the second voltage and generates a signal to control the first and second switches based on the comparison. In an embodiment, the circuitry comprises: two output multiplexers each having: an input coupled to the ADC output; an input which, in operation, is fixed at a value of 1; and a selection input coupled to the output of the comparator; and a digital-divider having inputs coupled to respective outputs of the output multiplexers, wherein in operation, the digital divider generates a digital representation of a resistance of the variable resistor. In an embodiment, the circuitry comprises: a digital divider having an input coupled to the output of the ADC; and an output multiplexer having a first input coupled to the output of the ADC, a second input coupled to an output of the digital divider, and a selection input coupled to an output of the comparator. In an embodiment, the sensor includes a reference resistor and the reference voltage is a voltage across the reference resistor. 
         [0030]    In an embodiment, a method comprises: sensing a voltage across a variable resistance; selectively coupling the sensed voltage to a first input of an analog to digital converter (ADC); selectively coupling a reference voltage to a second input of the ADC; and generating a signal indicative of a value of the variable resistance as a ratio of a value of the sensed voltage and a value of the reference voltage. In an embodiment, said ADC comprises: an integrator; and two negative feedback loops, said two negative feedback loops being first-order continuous-time sigma-delta converters having a comparator and a sequential electronic circuit coupled to the integrator. In an embodiment, the method comprises: low-pass filtering output signals of said sequential electronic circuits, generating first and second filtered signals; and dividing, using a digital divider, the first filtered signal by the second filtered signal, generating a digital signal indicative of the resistance of the variable resistor. In an embodiment, the method comprises: selectively coupling the sensed voltage to the second input of the ADC; selectively coupled the reference voltage to the first input of the ADC; comparing the sensed voltage to the reference voltage; and controlling the selective coupling based on the comparing of the sensed voltage to the reference voltage. In an embodiment, the method comprises: selectively coupling one of an output of the ADC and a signal having a value of one to a first input of a digital divider; selectively coupling one of an output of the ADC and the signal having a value of one to a second input of the digital divider; and generating, using the digital divider, a digital signal indicative of the resistance of the variable resistor. In an embodiment, the method comprises: generating, using a digital divider, an inverse of a signal generated by the ADC; and selecting one of the signal generated by the ADC and the inverse of the signal generated by the ADC. In an embodiment, the method comprises: sensing the reference voltage. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0031]    One or more embodiments will now be described purely by way of non-limiting example, with reference to the annexed drawings, wherein: 
           [0032]      FIG. 1 , which regards the prior art, has already been described; 
           [0033]      FIGS. 2A and 2B  are functional block diagrams of embodiments of resistive sensor systems; 
           [0034]      FIG. 3  shows an architecture of an embodiment of a resistive sensor system; 
           [0035]      FIG. 4  shows a variant of the embodiment of  FIG. 3 ; 
           [0036]      FIG. 5  shows a functional block diagram of a known sigma-delta converter; 
           [0037]      FIG. 6  shows an embodiment of a sigma-delta converter; and 
           [0038]      FIG. 7  shows example diagrams representing the ripple on the output of the integrator present in the embodiment of a converter of  FIG. 6 . 
       
    
    
     DETAILED DESCRIPTION 
       [0039]    In the ensuing description, one or more specific details are illustrated, aimed at enabling an in-depth understanding of various embodiments provided by way of example. The embodiments may be obtained without one or more of the above specific details, or else with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not represented or described in detail so that certain aspects of the embodiments will not be obscured. 
         [0040]    Reference to “an embodiment” or “one embodiment” in the context of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment”, or the like, that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Furthermore, particular configurations, structures, or characteristics may be combined in any adequate way in one or more embodiments. 
         [0041]    The references used herein are provided simply for convenience and hence do not define the sphere of protection or the scope of the embodiments. 
         [0042]    An embodiment facilitates exploiting an efficient architecture for implementing the function described above with reference to  FIG. 1 . 
         [0043]    In particular, in the ensuing description, various embodiments will be described to enable understanding of the example embodiments described. In what follows, the various embodiments will be described at the level of conceptual block diagram and at the level of implementation. In an embodiment, there will be two different circuits for two different situations, for R X &lt;R REF  or for R X &gt;R REF . The two conditions of the relation between the resistances being treated in different ways. 
         [0044]      FIGS. 2A and 2B  provide two different diagrams for the aforesaid two different conditions of relation between the unknown resistance R X    104  and the reference resistance R REF    102 . 
         [0045]    In particular,  FIG. 2A  regards the case where the unknown resistance R X    104  is lower than the reference resistance R REF    102  (R X &lt;R REF ), whereas  FIG. 2B  refers to the opposite case where the unknown resistance R X    104  is higher than the reference resistance R REF    102  (R X &gt;R REF ). 
         [0046]    In the case represented in  FIG. 2A , R X &lt;R REF , the voltage V 2  across R X    104  will be lower than the voltage V 1  across the resistance R REF    102 . 
         [0047]    In these conditions, the circuit represented converts into a digital value the voltage V 2  across the unknown resistance R X , taking as reference the voltage V 1  across the known reference resistance R REF . The output of the analog-to-digital converter ADC  106  in this case reproduces directly the digital representation D X  of the unknown resistance R X . 
         [0048]    In particular, in this case, the voltage V 1  across the reference resistance R REF  is sent at input to the analog-to-digital converter ADC  106  between the inputs Vref, and in particular between ref+ and ref−. 
         [0049]    Instead, the voltage V 2  measured across the unknown resistance R X  is sent to the inputs Vin, between in+ and in−. 
         [0050]    In particular, with reference to  FIG. 2A  the following equations may be written: 
         [0000]    
       
         
           
             
               D 
                
               
                   
               
                
               2 
             
             = 
             
               Vin 
               Vref 
             
           
         
       
       
         
           
             
               R 
               X 
             
             = 
             
               
                 
                   R 
                   REF 
                 
                  
                 
                   
                     V 
                      
                     
                         
                     
                      
                     2 
                   
                   
                     V 
                      
                     
                         
                     
                      
                     1 
                   
                 
               
               = 
               
                 
                   
                     R 
                     REF 
                   
                    
                   
                     Vin 
                     Vref 
                   
                 
                 = 
                 
                   
                     
                       R 
                       REF 
                     
                     · 
                     D 
                   
                    
                   
                       
                   
                    
                   2 
                 
               
             
           
         
       
     
         [0000]    where D X =D 2 . 
         [0051]    In the second case, where the unknown resistance R X  is higher than the reference resistance R REF  (R X &gt;R REF ), the circuit of  FIG. 2B  converts into a digital value the voltage V 1  across the known reference resistance R REF , taking as reference the voltage V 2  across the unknown resistance R X . The digital divider DD  108  in this case calculates the digital representation D X  of the unknown resistance R X . 
         [0052]    In particular, with reference to  FIG. 2B , the following equations may be written: 
         [0000]    
       
         
           
             
               D 
                
               
                   
               
                
               1 
             
             = 
             
               Vin 
               Vref 
             
           
         
       
       
         
           
             
               R 
               x 
             
             = 
               
              
             
               
                 
                   R 
                   REF 
                 
                  
                 
                   
                     V 
                      
                     
                         
                     
                      
                     2 
                   
                   
                     V 
                      
                     
                         
                     
                      
                     1 
                   
                 
               
               = 
                 
                
               
                 
                   
                     R 
                     REF 
                   
                    
                   
                     Vref 
                     Vin 
                   
                 
                 = 
                 
                   
                     R 
                     REF 
                   
                   · 
                   
                     1 
                     
                       D 
                        
                       
                           
                       
                        
                       1 
                     
                   
                 
               
             
           
         
       
       
         
           
             
               where 
                
               
                   
               
                
               
                 D 
                 x 
               
             
             = 
             
               
                 1 
                 
                   D 
                    
                   
                       
                   
                    
                   1 
                 
               
               . 
             
           
         
       
     
         [0053]    This embodiment facilitates using fewer analog-to-digital operations and providing greater accuracy and precision as compared to the embodiment of  FIG. 1 . 
         [0054]    In greater detail, the two cases just described with reference to  FIGS. 2A and 2B  differ from one another as regards the way in which the two voltages acquired across the two resistances R X    104  and R REF    102  are sent at input to the converter ADC  106 . 
         [0055]    The converter employs a reference voltage for calculating a ratio between voltages. 
         [0056]    In the first case, when R X &lt;R REF , the inputs to the converter ADC are chosen in such a way that Vin is set equal to V 2 , to the voltage measured across R X , whereas Vref is set equal to V 1 , the voltage measured across R REF . 
         [0057]    In the second case, when R X &gt;R REF , the inputs to the converter ADC are chosen in an opposite way; namely, Vin is set equal to V 1 , to the voltage measured across R REF , whereas Vref is set equal to V 2 , the voltage measured across R X . 
         [0058]    In an embodiment, a device for measuring an unknown resistance R X  comprises a reference resistance R REF  in series with the unknown resistance R X . The device measures a first voltage V 1  and a second voltage V 2  across the reference resistance R REF  and the unknown resistance R X , respectively. In an embodiment, the device comprises changeover-switch modules, which receive at input the voltages and return values representing the voltages. In an embodiment, the device comprises a single analog-to-digital converter ADC, which supplies at output the digital representation D X  of the value of the unknown resistance R X  as a ratio between the values V 1 , V 2  at input to the converter ADC. 
         [0059]      FIG. 3  shows an architecture of an embodiment, which also comprises a comparator block comp  110 , which compares the voltage V 1  with the voltage V 2  to decide whether the relation between the resistances falls in the first case (R X &lt;R REF ) or else in the second case (R X &gt;R REF ). 
         [0060]    The architecture of  FIG. 3  further comprises a plurality of changeover switches  112  that couple the converter ADC  106  according to the two cases. 
         [0061]    The two resistances R X    102  and R REF    104  are coupled together in series between ground gnd and the supply voltage V SUP  as indicated in  FIG. 3 . Measured across the reference resistance R REF  is the voltage V 1 , which is proportional to the value of the resistance R REF . In particular, the current that reaches the unknown resistance R X  is equal to 
         [0000]    
       
         
           
             
               I 
               x 
             
             = 
             
               
                 
                   V 
                    
                   
                       
                   
                    
                   1 
                 
                 
                   R 
                   REF 
                 
               
               . 
             
           
         
       
     
         [0062]    Consequently, we have that: 
         [0063]    the two resistances have the same current I(R REF )=I(R X )=I X ; 
         [0064]    the voltage V 1  is the voltage across R REF ; and 
         [0065]    the voltage V 2  is the voltage across R X . 
         [0066]    Generally, present between the two resistances there may be a transistor (not shown) with function of electronic switch, which has a certain value of resistance. This resistance does not present drawbacks provided that the three conditions referred to above are respected. 
         [0067]    The two voltages V 1  and V 2  measured across the resistances are sent at input to a comparator comp  110 , which supplies at output OUT a high value (HIGH corresponding to the logic value “1”) when the voltage V 1  is higher than the voltage V 2  (V 1 &gt;V 2 ) and supplies a low value (LOW corresponding to the logic value “0”) when the voltage V 1  is lower than the voltage V 2  (V 1 &lt;V 2 ). 
         [0068]    The output OUT of the comparator comp  110  is sent, together with the two values V 1  and V 2 , at input to two multiplexers mux 1   112  and mux 2   112 , and the output OUT of the comparator comp  110  drives the selection terminal of the aforesaid multiplexers  112 . 
         [0069]    When the output OUT is at a high level “1”, the output of the multiplexer mux is equal to the first input (V 1  for the multiplexer mux 1  at the top in  FIG. 3  and V 2  for the multiplexer mux 2  at the bottom). Instead, when the output OUT is at the low level “0”, the output of the multiplexer mux is equal to the second input (V 2  for the multiplexer mux 1  at the top in  FIG. 3  and V 1  for the multiplexer mux 2  at the bottom). 
         [0070]    The outputs of the multiplexers OM 1  and OM 2  are supplied to the converter ADC  106 . In particular OM 1  is supplied to the input Vref, whereas OM 2  is supplied to the input Vin. The output D of the converter ADC (which is equal to 
         [0000]    
       
         
           
             
               D 
                
               
                   
               
               = 
               
                 Vin 
                 Vref 
               
             
             ) 
           
         
       
     
         [0000]    is sent at input to other two multiplexers mux 3   114  and mux 4   114 . 
         [0071]    These second multiplexers  114  have one input fixed at the value “1”, and as selection input receive the output OUT of the comparator comp  110 . In this case, the value “1” is a binary number with as many bits as the number of bits of the output of the ADC. If the latter has 10 bits, then “1” of  FIG. 3  is the binary number “0000 0000 01”. 
         [0072]    In particular, the multiplexer mux 3  receives, as first input, the output D of the converter ADC  106  and, as second input, the constant value “1”. Instead, the multiplexer mux 4  receives, as first input, the constant value “1” and, as second input, the output D of the converter ADC  106 . 
         [0073]    At output from the multiplexer mux 3  there is the value D 2 , and at output from the multiplexer mux 4  there is the value D 1 . These two values are sent at input to a digital divider DD  108 , which supplies at output the value of D X  calculated as 
         [0000]    
       
         
           
             
               D 
               x 
             
             = 
             
               
                 
                   D 
                    
                   
                       
                   
                    
                   2 
                 
                 
                   D 
                    
                   
                       
                   
                    
                   1 
                 
               
               . 
             
           
         
       
     
         [0074]    In particular, when the signal OUT at output from the comparator is high “1” (OUT=1), when V 1 &gt;V 2  (event that occurs when the unknown resistance R X  is lower than the reference resistance R REF ), the selector signals S 3  and S 4  are equal to “1” and enable transfer at output of the signal set on the first input of the multiplexers. Consequently, at output from the multiplexer mux  3  there is the value D, whereas at output from the multiplexer mux  4  there is the value “1”. Consequently, the digital divider DD supplies at output the ratio between D 2  and D 1 , where in this case D 1 =1, 
         [0000]    
       
         
           
             
               D 
               x 
             
             = 
             
               
                 
                   D 
                    
                   
                       
                   
                    
                   2 
                 
                 
                   D 
                    
                   
                       
                   
                    
                   1 
                 
               
               = 
               
                 D 
                  
                 
                     
                 
                  
                 2. 
               
             
           
         
       
     
         [0075]    In particular, the switches inside the multiplexers mux 3  and mux 4  are in the position indicated in  FIG. 3 ; they enable transfer at output of the value present on the first input of the multiplexers. 
         [0076]    Instead, when the signal OUT at output from the comparator is low “0”, when V 1 &lt;V 2  (event that occurs when the unknown resistance R X  is higher than the reference resistance R REF ), the selector signals S 3  and S 4  are equal to “0” and enable transfer at output of the signal set on the second input of the multiplexers. Hence, at output from the multiplexer mux 3  there is the value “1”, whereas at output from the multiplexer mux 4  there is the value D. Consequently, the digital divider DD supplies at output the ratio between D 2  and D 1 , where in this case D 2 =1, 
         [0000]    
       
         
           
             
               D 
               x 
             
             = 
             
               
                 
                   D 
                    
                   
                       
                   
                    
                   2 
                 
                 
                   D 
                    
                   
                       
                   
                    
                   1 
                 
               
               = 
               
                 
                   1 
                   
                     D 
                      
                     
                         
                     
                      
                     1 
                   
                 
                 . 
               
             
           
         
       
     
         [0077]    In this case, the switches inside the multiplexers mux 3  and mux 4  are in a position opposite to the one represented in  FIG. 3 ; they enable transfer at output of the value present on the second input of the multiplexers. 
         [0078]    Consequently, the architecture represented in  FIG. 3  comprises the functions of the two circuits of  FIG. 2  that are each specific for a particular case of relation between the resistances R X  and R REF . 
         [0079]    With this single architecture, it is consequently possible to measure the unknown resistance R X , which represents the value that is to be measured by means of the sensor. 
         [0080]    In particular, these sensors measure the variation of electrical resistance as a function of the physical quantity to be measured. In particular, for example in measuring a level of liquid, the higher the level of liquid, the higher the value of the unknown resistance R X  measured. This measurement is made on the basis of a reference resistance R REF  of a known value. 
         [0081]    To sum up, when R X &lt;R REF , we have: 
         [0000]    
       
         
           
             
               D 
                
               
                   
               
                
               2 
             
             = 
             
               Vin 
               Vref 
             
           
         
       
       
         
           
             
               R 
               x 
             
             = 
               
              
             
               
                 
                   R 
                   REF 
                 
                  
                 
                   
                     V 
                      
                     
                         
                     
                      
                     2 
                   
                   
                     V 
                      
                     
                         
                     
                      
                     1 
                   
                 
               
               = 
                 
                
               
                 
                   
                     R 
                     REF 
                   
                    
                   
                     Vin 
                     Vref 
                   
                 
                 = 
                 
                   
                     
                       
                         R 
                         REF 
                       
                       · 
                       D 
                     
                      
                     
                         
                     
                      
                     2 
                   
                   = 
                   
                     
                       R 
                       REF 
                     
                     · 
                     
                       D 
                       x 
                     
                   
                 
               
             
           
         
       
       
         
           
             
               where 
                
               
                   
               
                
               D 
                
               
                   
               
                
               2 
             
             = 
             
               Vin 
               Vref 
             
           
         
       
     
       and D X =D 2 , 
       [0082]    whereas, when R X &gt;R REF , we have: 
         [0000]    
       
         
           
             
               R 
               x 
             
             = 
               
              
             
               
                 
                   R 
                   REF 
                 
                  
                 
                   
                     V 
                      
                     
                         
                     
                      
                     2 
                   
                   
                     V 
                      
                     
                         
                     
                      
                     1 
                   
                 
               
               = 
                 
                
               
                 
                   
                     R 
                     REF 
                   
                    
                   
                     Vref 
                     Vin 
                   
                 
                 = 
                 
                   
                     
                       R 
                       REF 
                     
                     · 
                     
                       1 
                       
                         D 
                          
                         
                             
                         
                          
                         1 
                       
                     
                   
                   = 
                   
                     
                       R 
                       REF 
                     
                     · 
                     
                       D 
                       x 
                     
                   
                 
               
             
           
         
       
       
         
           
             
               
                 where 
                  
                 
                     
                 
                  
                 D 
                  
                 
                     
                 
                  
                 1 
               
               = 
               
                 
                   
                     Vin 
                     Vref 
                   
                    
                   
                       
                   
                    
                   and 
                    
                   
                       
                   
                    
                   
                     D 
                     x 
                   
                 
                 = 
                 
                   
                     1 
                     
                       D 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   . 
                 
               
             
              
             
                 
             
           
         
       
     
         [0083]    In this case, when V 1 ≅V 2 , the multiplexers may switch too fast, and problems may arise. 
         [0084]      FIG. 4  shows an embodiment alternative to the one illustrated in  FIG. 3 . 
         [0085]    The first part of the architecture as illustrated is identical to that of  FIG. 3 , whereas the second part varies. 
         [0086]    In particular, in this embodiment, the divider DD 1   116  is shifted upstream, and just one multiplexer mux 5   118  is used at output. 
         [0087]    In particular, the divider DD 1   116  supplies at output the inverse of the input, namely, 
         [0000]    
       
         
           
             y 
             = 
             
               
                 1 
                 x 
               
               . 
             
           
         
       
     
         [0088]    In this embodiment, the output D of the converter ADC  106  is sent directly, as first input (D 2 ), to the multiplexer mux 5   118 , and is sent at input to the divider DD 1   116 . 
         [0089]    The output of the divider DD 1   116  is 
         [0000]    
       
         
           
             
               D 
                
               
                   
               
                
               1 
             
             = 
             
               1 
               D 
             
           
         
       
     
         [0000]    and is sent, as second input, to the multiplexer mux 5   118 . The output of the multiplexer mux 5   118  is driven by the selection input S 5 , which is connected to the output OUT of the comparator comp  110 . When the output OUT of the comparator comp  110  is at the high value “1” (when V 1 &gt;V 2 , and R X &lt;R REF ) the output of the multiplexer mux 5   118  is connected to the top input D 2 =D (as viewed in the figure). 
         [0090]    Instead, when the output OUT of the comparator comp is at the low value “0” (when V 1 &lt;V 2 , and R X &gt;R REF ), the output of the multiplexer mux 5   118  is connected to the bottom input 
         [0000]    
       
         
           
             
               D 
                
               
                   
               
                
               1 
             
             = 
             
               1 
               D 
             
           
         
       
     
         [0000]    (as viewed in the figure). 
         [0091]    Also in this case, the same equations as the ones written for the embodiment of  FIG. 3  apply. 
         [0092]      FIG. 5  shows one of various embodiments of a known ΣΔ analog-to-digital converter module with a first-order continuous-time ΣΔ modulator. 
         [0093]    Consequently, illustrated in  FIG. 5  is one of the possible representations, by means of a block diagram, of a first-order continuous-time sigma-delta converter module, in which the representation of the various blocks is useful for understanding operation of an embodiment of an architecture here proposed and represented in  FIG. 6 . 
         [0094]    The converter module comprises a negative feedback loop. The integrator module integ has a zero-mean input, an infinite DC gain, and is included in the negative feedback loop. 
         [0095]    In particular, the module envisages measuring at input the two voltages Vin and Vref. 
         [0096]    The voltage Vref measured across the reference resistance R REF  is sent, as first input, to a multiplexer muxx. The second input of the multiplexer muxx receives the zero value “0”, and the selection input sel receives the value D 0  as feedback of the circuit. The output of the multiplexer muxx is equal to (Vref·D 0 ). If D 0  is at the low level “0”, the output is zero “0”. 
         [0097]    The two voltages Vin and (Vref·D 0 ) are sent at input to an adder node Som, where Vin is sent with positive sign, whereas (Vref·D 0 ) with negative sign. The output of the adder node Som, equal to Vin−(Vref·D 0 )=0, is sent at input to an integrator node integ, which supplies at output a nonzero value due to its infinite amplification factor. The output of the integrator integOUT is sent at input to a comparator compC for comparison with a threshold value th set on the other input of the comparator. 
         [0098]    The output of the comparator compC is sent at input to the data terminal D of a sequential electronic circuit (D flip-flop). The flip-flop has a data input D, a clock synchronization input, and an output Q. Upon switching of the clock signal, the D flip-flop transfers the value on the terminal input D at output Q and holds it until the aforesaid input changes according to the characteristic equation: Q+=D. The output Q of the flip-flop is equal to 
         [0000]    
       
         
           
             
               
                 D 
                  
                 
                     
                 
                  
                 0 
               
               = 
               
                 Vin 
                 Vref 
               
             
              
             
                 
             
           
         
       
     
         [0000]    and is sent back as feedback to the multiplexer muxx and used as selection input sel. In particular, the sequential electronic circuit (D flip-flop) provides a fast elementary memory device. 
         [0099]    Consequently, this sigma-delta converter contains just one feedback loop and supplies just one output, which represents the digital conversion of the input voltage Vin. 
         [0100]    Starting from this known ΣΔ analog-to-digital converter module, illustrated in  FIG. 5  in one of its possible representations, it is possible to arrive at a modified converter for use in an embodiment for measuring an unknown resistance. 
         [0101]      FIG. 6  illustrates an embodiment of a modified converter. 
         [0102]    As already mentioned previously, the two resistances R REF    104  and R X    102  are coupled together in series between the supply voltage V SUP  and the ground terminal gnd. The two respective voltages, V 1  and V 2 , are measured across the resistances. The two voltages measured are sent to the first input of two respective multiplexers, in particular muxA  222  and muxB  224 . Sent at input to the second terminal of the multiplexer muxA  222  and muxB  224  is the zero value “0”. 
         [0103]    Furthermore, the two multiplexers muxA and muxB receive on the selection terminal the two feedback signals D 2  and D 1 . In particular, the signal D 2  controls the output of the multiplexer muxA  222 , whereas the signal D 1  controls the output of the multiplexer muxB  224 . 
         [0104]    As already said previously, the value of the signal on the selection input enables transfer at output of one of the two signals present on the two input terminals to the multiplexer. For example, when the selection signal is equal to “1”, the multiplexer supplies at output the value of the signal present on the first input. 
         [0105]    Consequently, at output from the multiplexers muxA  222  and muxB  224  there will be the values V 1 ·D 2  and V 2 ·D 1 . These two values are sent to an adder node  226 , the second with negative sign. The output of the adder node  226  ((V 1 ·D 2 )−(V 2 ·D 1 )) is sent at input to the integrator integ  228 . 
         [0106]    We have V 1 ·D 2 =V 2 ·D 1  in so far as the input of the integrator integ  228  is equal to zero. 
         [0107]    The input of the integrator integ  228  is on average zero because the integrator has an infinite gain and is set in a negative feedback loop. Like an operational amplifier, it has a differential input voltage that is zero when it is properly inserted in a feedback loop. The output voltage of the integrator  228  instead is not zero by virtue of its infinite amplification factor. 
         [0108]    The output of the integrator integOUT is sent at input to two comparators compA  230  and compB  232 . In greater detail, the output integOUT of the integrator  228  is sent, as negative input, to the comparator compA  230 , which compares it with a threshold th 2 , and moreover the output integOUT of the integrator  228  is set also, as positive input, to the comparator compB  232 , which compares it with a threshold th 1 . 
         [0109]    The outputs of the comparators are sent at input to two D flip-flops DFFA  234  and DFFB  236 , on the data input D. The outputs of these flip-flops are filtered by two low-pass filters LPF  238 ,  240 , and the filtered values represent D 2  and D 1 , respectively. These values are also sent at input as selection values for the two multiplexers muxA  222  and muxB  224 . 
         [0110]    Finally, the values D 2  and D 1  obtained are sent to a digital divider DD  234 , which calculates the ratio 
         [0000]    
       
         
           
             
               D 
               x 
             
             = 
             
               
                 
                   D 
                    
                   
                       
                   
                    
                   2 
                 
                 
                   D 
                    
                   
                       
                   
                    
                   1 
                 
               
               . 
             
           
         
       
     
         [0111]    Consequently, in the case where R X &lt;R REF , we have V 2 &lt;V 1 . 
         [0112]    Hence, D 1 =1 since the output integOUT of the integrator  228  reaches the threshold th 2 , and the ripple of the output of the integrator  228  is lower than th 2 −th 1 . 
         [0113]    Consequently, V 1 ·D 2 =V 2  because the input of the integrator  228  is zero, equal to “0”. 
         [0114]    Thus, we can write: 
         [0000]    
       
         
           
             
               R 
               x 
             
             = 
               
              
             
               
                 
                   R 
                   REF 
                 
                  
                 
                   
                     V 
                      
                     
                         
                     
                      
                     2 
                   
                   
                     V 
                      
                     
                         
                     
                      
                     1 
                   
                 
               
               = 
               
                 
                   
                     R 
                     REF 
                   
                    
                   D 
                    
                   
                       
                   
                    
                   2 
                 
                 = 
                 
                   
                     R 
                     REF 
                   
                    
                   
                     D 
                     x 
                   
                 
               
             
           
         
       
     
         [0000]    where D X =D 2 
   thus obtaining the same result as for the previous embodiments.   
 
         [0116]    Furthermore, in the case where R X &gt;R REF , we have V 2 &gt;V 1 . 
         [0117]    Hence, D 2 =1 since the output of the integrator integ  228  reaches the threshold th 1  and the ripple of the output of the integrator  228  is less than th 2 −th 1 . 
         [0118]    Consequently, V 1 =V 2  because the input of the integrator  228  is zero, equal to “0”. 
         [0119]    Thus, we can write: 
         [0000]    
       
         
           
             
               R 
               x 
             
             = 
               
              
             
               
                 
                   R 
                   REF 
                 
                  
                 
                   
                     V 
                      
                     
                         
                     
                      
                     2 
                   
                   
                     V 
                      
                     
                         
                     
                      
                     1 
                   
                 
               
               = 
               
                 
                   
                     R 
                     REF 
                   
                    
                   
                     1 
                     
                       D 
                        
                       
                           
                       
                        
                       1 
                     
                   
                 
                 = 
                 
                   
                     R 
                     REF 
                   
                    
                   
                     D 
                     x 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 where 
                  
                 
                     
                 
                  
                 
                   D 
                   x 
                 
               
               = 
               
                 1 
                 
                   D 
                    
                   
                       
                   
                    
                   1 
                 
               
             
              
             
                 
             
           
         
       
     
         [0000]    thus obtaining the same result as for the previous embodiments. 
         [0120]    Reproduced in  FIG. 7  are the plots representing the ripple of the output integOUT of the integrator  228  (where the thresholds th 1  and th 2  are indicated) and the plots of the values of D 2  and of D 1  according to the values of the resistances. In particular, appearing on the left is the case R X &lt;R REF  and appearing on the right is the case R X &gt;R REF . 
         [0121]    In an embodiment, a ripple will be smaller than the difference between the two thresholds (ripple&lt;th 2 −th 1 ), a variability less than the difference between the thresholds. 
         [0122]    The condition ripple&lt;th 1 −th 2  may be useful because one of the two terms of the division is 1, thus facilitating improving the efficiency of the calculations. If this condition were not satisfied, there would in any case be proper operation, but possibly without optimization of a term=1. 
         [0123]    Consequently, the solution illustrated in  FIGS. 2A and 2B  has been introduced to explain working principles and derive the formulas useful for explaining an embodiment, whereas  FIG. 6  shows an example of a possible embodiment that is equivalent to that of  FIGS. 2A and 2B  because it uses the same formulas. Just a glance at the formulas reveals that the two solutions perform the same function. 
         [0124]    Instead, with reference to the known sigma-delta converter of  FIG. 5 , which contains just one loop and supplies just one output that represents the digital conversion of the input voltage, the solution proposed in  FIG. 6  contains two loops that function in an alternative way. In an embodiment, one of the two has a digital output equal to 1, whereas the other functions as the loop of the known sigma-delta converter. 
         [0125]    In particular, there are two feedback loops, two comparators, and two outputs that sense the output of the integrator integ  228  and are sent back at input. 
         [0126]    If one of the two inputs is equal to 1 this may facilitate maximizing the precision. 
         [0127]    Consequently, we have that only one of the two thresholds at a time is stimulated, and hence the outputs are a datum that changes and a constant datum equal to “1”. 
         [0128]    The embodiment described represents an implementation of a concept expressed by the embodiment described in  FIGS. 2A and 2B  that is efficient from the standpoint of performance and from the economic standpoint. 
         [0129]    In an embodiment, the concepts of  FIGS. 2A and 2B  are implemented respecting the advantage of a single A/D converter, of a sigma-delta type, which that presents high efficiency and performance using silicon integration technologies. Finally, an embodiment manages in a simple and effective way transition between the two cases V 2 &lt;V 1 , and vice versa, and facilitates doing so without malfunctioning in the case of multiple transitions close to one another in time. 
         [0130]    An embodiment described herein envisages a single sigma-delta converter, which generates two different outputs, which are sent to the logic for being processed with two digital filters. In an embodiment, one of the two is constant at the high value. 
         [0131]    In an embodiment, a device for measuring an unknown resistance comprises a single analog-to-digital converter, which contains two negative feedback loops that function in an alternative way according to the outputs of the changeover-switch modules upstream of the converter. 
         [0132]    In an embodiment, the two negative feedback loops are first-order continuous-time sigma-delta converters. Typically, one or the other, alternatively, of the two sigma-delta converters has its digital output constant at the high level. 
         [0133]    Each sigma-delta converter comprises an integrator  228 , a comparator, and a sequential electronic circuit. In an embodiment, the sequential electronic circuits are D flip-flops, and the changeover-switch modules are multiplexers. Furthermore, the outputs of the sequential electronic circuits are sent back at input as negative feedback and used as selection input of the multiplexers. The outputs of the sequential electronic circuits are filtered with low-pass filters and sent at input to a digital divider, which supplies at output the digital representation of the value of the unknown resistance. 
         [0134]    Of course, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present disclosure. 
         [0135]    The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
         [0136]    These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.