Abstract:
A dual integration circuit is disclosed for extending the dynamic range of on focal plane signal processor used in a space based infrared detection system. The circuit comprises an input port in connection with a dedicated detector element and first and second integration circuits operative to generate an output signal responsive to a detected infrared image. The first and second integration circuits are provided with associated switching circuitry for generating output signals at different times to facilitate detection of objects having bright and dim infrared images.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to electronic signal processing circuitry and, more particularly, to a dual integration circuit for varying the integration period of multiple channel infrared detector systems to allow detection of both bright and dim targets. 
     BACKGROUND OF THE INVENTION 
     Current infrared detector systems incorporate arrays of large numbers of discrete, highly sensitive detector elements, the outputs of which are connectable to sophisticated processing circuitry. By rapidly analyzing the pattern and sequence of detector element excitations, the processing circuitry can identify and monitor sources of infrared radiation. A contemporary subarray of detectors may contain 256 detectors on a side, or a total of 65,536 detectors. The size of each square detector may be approximately 0.009 cm on a side with 0.00127 cm spacing between detectors. Such a subarray would therefore be 2.601 cm on a side. The subarray may, in turn, be joined to form an array that connects many millions of detectors. As might be expected, the processing requirements for such a highly populated and closely spaced array are strenuous, particularly considering the demands of a space environment. 
     The response of the infrared detector elements and their associated electronic processing channel is preferably linear with an output in volts per watt of absorbed infrared radiation. A DC offset is associated with each detector and signal processing channel and is defined as fixed pattern noise. The detector response and DC offset are unique for each channel, i.e. they are different for each channel but all within a given range of values. Satisfactory detector input circuits exist to reduce or eliminate noise while providing near unity gain and stable operation. One such circuit is disclosed in U.S. Pat. No. 4,633,086 for INPUT CIRCUIT FOR INFRARED DETECTOR, issued to William J. Parrish, and assigned to the common assignee hereof. 
     A further requirement particularly significant in highly populated infrared detection systems, concerns the circuit for normalizing gain among the analog signal channels. Gain normalization to a high level is required by the sophisticated algorithms which analyze the detector array outputs. The variation in gain from detector channel to another increases the dynamic range requirements for the output amplifier when detector channels are multiplexed into a common output amplifier. The dynamic range of the analog-to-digital converter and the signal processing hardware must likewise have sufficient dynamic range to handle the multiplexed data. Increasing the dynamic range requirements of the output amplifier, analog-to-digital converter, and signal processing hardware results in an increase in system weight and cost. Therefore, it is desirable to maintain the best possible uniformity in gain among all detector channels. One suitable gain normalization circuit is disclosed in U.S. Pat. No. 5,039,879 for GAIN NORMALIZATION CIRCUIT, issued to William J. Parrish, and assigned to the common assignee hereof. 
     Having addressed the concern of noise and gain normalization, the signal processing circuitry must further have a sufficient range of response to accurately identify and quantify inputs from both dim targets and bright targets. For example, the infrared detection system must be sufficiently sensitive to distinguish and quantify dim infrared images corresponding to particular events of interest. However, the circuit must also produce an accurate response, i.e. avoid saturation, when a bright target is detected. The present invention addresses these concerns by providing a dual integration circuit which utilizes a long integration period to detect and quantify dim targets, as well as a short integration period for detecting and quantifying bright targets. In view of the constraints of highly populated, space based systems, the present invention implements a dual integration circuit in each channel of the infrared detection system, on the same chip as the input and gain normalization circuitry. 
     SUMMARY OF THE INVENTION 
     A dual integration circuit is disclosed for extending the dynamic range of on focal plane signal processor used in a space based infrared detection system. The circuit comprises an input port in connection with a dedicated detector element and first and second integration circuits operative to generate an output signal responsive to a detected infrared image. The first and second integration circuits are provided with associated switching circuitry for generating output signals at different times to facilitate detection of objects having bright and dim infrared images. 
     In the presently preferred embodiment, the first integration circuit produces an output signal representative of a target having a bright infrared image, and the second integration circuit generates an output signal representative of an object having a dim infrared image. 
     The first and second integration circuits output at different times corresponding to the different integration of each circuit. In the presently preferred embodiment, the second integration circuit, corresponding to a long integration time, generates an output signal after a time equal to sixteen times the length of the period of the short integration circuit. 
     The dual integration circuit may further be provided with analog-to-digital conversion circuitry for receiving outputs from the first and second integration circuit and generating a responsive digital output signal representative of a composite of signals from the first and second integration circuits. 
     In the preferred embodiment, the dual integration circuit is implemented on an integrated circuit chip which is supported by a module which also supports multiple detector elements. A plurality of dual integration circuits may be formed on a single integrated circuit chip useful in a space based infrared detection system. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram illustrating the operation of the dual integration circuit; 
     FIG. 2 is a more detailed schematic representation of the dual integration circuit illustrated at FIG. 1; and 
     FIG. 3 is a timing diagram of signals applied to the circuit illustrated at FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The detailed description set forth below in connection with the appended drawings is intended merely as a description of the presently preferred embodiments of the invention, and is not intended to represent the only form in which the present invention may be constructed or utilized. The description sets forth the functions and sequence of steps for construction and implementation of the invention in connection with the illustrated embodiments. It is to be understood, however, that the same or equivalent functions and sequences may be accomplished by different embodiments that are also intended to be encompassed within the spirit and scope of the invention. 
     FIG. 1 is a high level representation of the present invention in conjunction with a detector input circuit and an analog-to digital (A/D) converter. The circuitry illustrated at FIG. 1 represents a single channel circuit, dedicated to processing the output signal of a single detector element 11. It is to be understood that the circuitry illustrated at FIG. 1 may be repeated for each detector element in the array. In the presently preferred embodiment the circuitry of FIG. 1 is repetitively implemented many times on a single chip disposed adjacent the detector focal plane. A suitable module for supporting such chips adjacent the detector focal plane is illustrated in U.S. Pat. No. 4,659,931 for HIGH DENSITY MULTI-LAYERED INTEGRATED CIRCUIT PACKAGE, issued to Schmitz et al. Such modules are suitable to support a substantial number of such chips in electrical communication with both the individual detector elements and off-focal plane processing circuitry. It is to be understood, however, that the broader aspects of the present invention are not intended to be limited to use in conjunction with a particular type of module or detector array. 
     Referring again to FIG. 1 detector element 11 responds to an infrared frequency signal to generate an output which is communicated to the suitable input amplifier circuit 13. In practice amplifier circuit 13 may be implemented as an input amplifier effective to reduce interchannel offset and normalize interchannel gain, as described above. Thereafter the signal is communicated to reset integrator 15 described in more detail below. The output of reset integrator 15 is simultaneously communicated to long integration circuit 17 and short integration circuit 19. The long integration circuit 17 is useful for small signals and the short integration circuit 19 is useful for large signals, which would normally saturate the associated integration capacitance by the end of a long integration period. In practice the long integration circuit 17 and short integration circuit 19 may be implemented as sample and hold circuits as described in more detail below. The long integration circuit is the equivalent of a high gain mode, while the short integration circuit is the equivalent of a low gain mode. The outputs of integration circuits 17 and 19 are communicated to an A/D converter consisting of comparators 21, 23, OR gate circuit 25 and latch circuit 27. The appropriate digital count is then communicated to the parallel to serial converter 29 and then to the chip output multiplexer (not shown). If the long integration channel saturates, the short integration signal is sent to the output along with the gain bit indicating the short integration sample is being used. 
     In the preferred embodiment, each sampled signal is converted using a 13-bit A/D converter so that 13-bit resolution may be obtained for signals from both short integration circuit 17 and long integration circuit 19. 
     FIG. 2 illustrates in more detail a portion of the circuitry represented at FIG. 1. As shown at FIG. 2 the reset integrator 15 may be formed to incorporate an MWIR integration capacitor (C INT .sbsb.MW) or an SWIR integration capacitor (C INT .sbsb.SW) depending upon the selected mode of operation. As is well known to those skilled in the art space based infrared detection systems may be used to monitor a variety of different locations and conditions which are more effectively monitored by examining different portions of the infrared frequency spectrum. Thus, the operation of SW1 allows the circuitry to ultimately examine medium wave infrared circuitry, or short wave infrared circuitry, depending upon the condition of switch SW. 
     For each channel there are two sample and hold capacitors: C SH .sbsb.S for sample-and-holding the short integration time signal value, and C SH .sbsb.L for sample-and-holding the longer integration time signal value. The operation of the sample-and-hold circuits is controlled externally through a sample-and-hold clock. Thus, the ratio of short to long integration time may be externally controlled. The presently preferred embodiment was designed to operate in the ratio of short to long integration time of 16:1 and the size of the sample-and-hold capacitors were chosen for this ratio. Both CSH S  and CSH L  are approximately 1.5 pF. In the presently preferred embodiment the designed value for C INT .sbsb.MW was 3.9 pF, while the design value of C INT .sbsb.SW was 9 pF. 
     Each of the redundant channels may contain two single slope, 13-bit A/D converters, that digitize the long and short integration time sample-and-hold voltages. The sample-and-hold voltages are compared with a reference ramp voltage and, when the comparator transitions, this latches a digital word being generated by an internal counter. Both the reference ramp and the internal counter are synchronized so that the latched counter value will represent the digital value of the sample-and-hold voltage. Only one counter is required for all A/D converters. It should be recognized that the dual integration circuit of the present invention can be used in conjunction with a variety of different types of A/D converter circuits, and is not intended to be limited to use in conjunction with the particular A/D converter circuits described herein. 
     In the presently preferred embodiment, a 14-bit latch is used to capture the output from the 13-bit internal counter and the state of gain bit illustrated at FIGS. 1 and 2. Each channel contains a long and short integration time comparator. The output from each comparator is connected to a pulse generator that will latch the internal count just after the comparator transition. In the circuit operation, the short integration time comparator will always transition first and latch in the counter&#39;s value. If the long integration sample is not saturated, its comparator will latch in the counter&#39;s count sometime later. This will overwrite the digital word, latched by the short integration time comparator. However, if the long integration time sample is saturated, its comparator will not transition and the short integration time digital word will be used. The gain bit is preset for the high gain mode (indicating the short integration time sample is being used) and remains at this preset condition unless the long integration sample is not saturated. 
     In the presently preferred embodiment, the output from the chip is a serial, current mode with a gain bit followed by 13 data bits for each channel. The data output is at the A/D clock rate of 150 kHz with a logical &#34;1&#34; corresponding to 10 μamps and the logical &#34;0&#34; corresponding to 0 μamps. The presently preferred embodiment is further designed to operate at 250 millisecond frame time. Signal integration and readout take place during a 200 msec time period while the A/D conversion of the integrated signal occurs during a 30 msec time period. Also during the 30 msec period is the command and control time where the command latch may receive information to place the device in various operating modes, e.g., to select SWIR or MWIR. 
     FIG. 3 illustrates certain signals generated in the course of the operation of the circuit illustrated FIG. 2. FIG. 3 illustrates the value of V DD  in relation to the reset signal RST and the state of the short integration and long integration circuits. 
     As shown at FIG. 3, the operation of the reset switch (RST) causes V DD  to return to its normal value. The pulse of signal SH S  illustrates closing of switch SH S  which defines the short integration time. The pulse of signal SH L  illustrates the closing of switch SH L  and defines the long integration time. As previously noted, the ratio of short integration time to long integration time may be varied according to design requirements. The amplitude of the signal from the input circuit, in combination with the time at which the SH S  and SH L  switches are closed, will determine the signal communicated to the comparator portion of the analog-to-digital converter. In the presently preferred embodiment that signal is then compared to a ramp reference signal generating an output pulse which is then communicated to the latch.