Abstract:
A comparator circuit for comparing a first voltage signal to a second voltage signal is described. The comparator circuit includes a first comparator and a second comparator and a selection unit for selecting one of the comparators depending on a selection condition. The invention also provides a method for operating a comparator circuit.

Description:
CLAIM OF PRIORITY  
       [0001]     This application claims priority to Application No. 06117795.2 filed Jul. 25, 2006, the entire content of which is incorporated by reference herein.  
       BACKGROUND OF THE INVENTION  
       [0002]     The invention relates to a comparator circuit and a method for operating a comparator circuit according to the preambles of the independent claims.  
         [0003]     Successive approximation analog-to-digital converters (ADC) are well known in the art. Such ADCs use a comparator to reject ranges of voltages, eventually settling on a final voltage range, and convert one bit per cycle. A typical successive approximation ADC comprises a reference voltage generator, a comparator and a successive approximation register. A general description of this kind of ADCs can be found for example in Allen/Holberg: “CMOS Analog Circuit Design”, Oxford University Press 2002, 668-672.  
         [0004]     A single-rail comparator supports a limited input voltage range only. Normally asymmetric input range, starting at some value and ranging to one of the power supply rails. A rail-to-rail comparator supports full input voltage swing, starting at ground and ending at the supply voltage.  
         [0005]     Although the algorithm approach does not lead to highest speeds possible in state-of-the-art technologies, this kind of ADCs offers high resolution at low area costs. Additionally, the overall power consumption is low, especially compared to so called flash analog-to-digital converters. Besides other factors the overall conversion accuracy is mainly influenced by the comparator. It is known that offset-errors and gain-errors affect the comparator accuracy. Additionally, the comparator gain is a function of the common mode input voltage which results in limiting the useable input voltage and, further, an available input voltage swing is limited by the input buffer/sample-and-hold circuit, which is usually used at the comparator input.  
         [0006]     Various attempts have been made to overcome these problems.  
         [0007]     A pipelined ADC architecture which achieves high resolution at high conversion rates is suggested by Won-Chul Song, Hae-Wook Choi, Sung-Ung Kwak and Bang-Sup Song, “A 10-b 20-Msamples/s Low-Power CMOS ADC”, IEEE Journal of Solid-State Circuits, Vol. 30, No. 5, pages 514-521, May 1995. In this paper a latch-type comparator in nMOS technology with an asymmetric output load is disclosed.  
         [0008]     Another pipelined algorithmic ADC is disclosed by Hae-Seung Lee, “A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC”, IEEE Journal of Solid-State Circuits, Vol. 29, No. 4, pages 509-515, April 1994.  
         [0009]     M. K. Mayes, Sing W. Chin disclose an alternative approach in their paper “A 200 mW, 1Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 12, page 1868, December 1996.  
         [0010]     A time-interleaved ADC combining two three-step flash converters is presented by Michael K. Mayes, Sing W. Chin, Lee L. Stoian, “A Low-Power 1 MHz, 25 mW 12-Bit Time-Interleaved Analog-to-Digital Converter”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 2, pages 169-178, February 1996.  
         [0011]     Another comparator ADC with a level shifter is proposed by M. K. Mayes and Sing W. Chin “A 200 mW, 1 Msample/s, 16-b Pipelined A/D Converter with on-chip 32-b Microcontroller”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 12, pages 1862-1872, December 1996.  
         [0012]     A rail-to-rail comparator is disclosed in D. Gardino and F. Maloberti “High Resolution Rail-to-rail ADC In CMOS Digital Technology”, Proc. of the ISCAS 1999, Vol. 2, 339-342. This comparator design also needs a rail-to-rail input stage. But as already mentioned above, the comparator is one of the main sources of inaccuracy in such a circuitry. Very low or very high input voltages close to the power supply rail voltages show a very low gain and yield high inaccuracy. However, a rail-to-rail comparator or operational amplifier design introduces additional offset and error sources. Full rail-to-rail operation can still not be achieved.  
       SUMMARY OF THE INVENTION  
       [0013]     It is therefore an object of the invention to provide a comparator circuit which provides a rail-to-rail operation with high accuracy. Another object is to provide a method for operating the comparator circuit.  
         [0014]     The objects are achieved by the comparator circuit and the method according to the independent claims.  
         [0015]     The other claims and the description disclose advantageous embodiments of the comparator circuit and the method operating a comparator circuit according to the invention.  
         [0016]     A comparator circuit is proposed for comparing a first voltage signal with a second voltage signal, the circuit comprising a first comparator and a second comparator and a selection unit for selecting one of the comparators depending on a selection condition. Advantageously, the gain of each comparator can be chosen independently from each other. Each comparator can be optimized for a different voltage regime, for example for high input voltages or low input voltages. Therefore, each comparator can work at its optimum. With an actual input signal present, the selecting unit advantageously selects one of the comparators according to its optimum voltage regime. Due to this digital selection of that one comparator working in its optimum range, the useable input voltage can be extended from single rail to a rail-to-rail, although each individual comparator can be a single-rail comparator. Due to the digital selection of the proper comparator, introduction of additional offsets and errors can be avoided, and mismatch compared to analog arrangements is avoided, where distortions/mismatch can occur. A degradation of operation speed can be prevented when using the inventive comparator circuit.  
         [0017]     High accuracy with low process dependency, low voltage dependency as well as low temperature dependency can be achieved. By expanding the operating voltage range of the comparator circuit according to the invention, a higher resolution for measurements of on-chip data is available, such as thermal sensors, supply voltage sensors, noise sensors. A rail-to rail comparator circuit is provided, although single-rail comparators, preferably performance-optimized single-rail comparators, can be used. A self-calibration comparator mode of operation is possible, providing a still more exact calibration.  
         [0018]     Generally spoken, the invention can be applied to any circuit which has a limited operating voltage range, e.g. a reference voltage generator. For such a circuit it is also possible to build two versions, one optimized for low output voltage operation and another one optimized for high output voltage operation. The comparator circuit can be preferably used in a successive approximation analog-to-digital converter and the method can be favorably used for converting analog signals to digital signals.  
         [0019]     Preferably, the selection condition is the voltage signal being above or below a threshold voltage. The threshold voltage can be a constant or can be variable.  
         [0020]     In a preferred embodiment, the selection unit selects one of the comparators if the voltage level is above the threshold voltage and the other one of the comparators if the voltage level is below the threshold voltage. This yields a high gain, high accuracy comparator circuit. In a preferred analog-to-digital converter, where such a comparator circuit is implemented, this decision is made as a first step of the conversion procedure. Once the most accurate one of the comparators has been selected selected, the conversion can be continued with the selected comparator. Using a successive approximation type of analog-to-digital converter, the selection of the comparator can be included in the first (most significant bit) conversion step, when only a low comparator accuracy is needed.  
         [0021]     In a favorable embodiment, one of the comparators is a pMOS (p-channel Metal-Oxide Semiconductor field effect) transistor based device adapted for a first input voltage range and the other one of the comparators is an nMOS (n-channel Metal-Oxide Semiconductor field effect) transistor based device adapted for a second input voltage range. The pMOS-transistor based comparator works best at low input voltage levels, where its gain is high, whereas the gain of the nMOS-based comparator is high at high input voltage levels, yielding the comparator working at its best at high input voltage levels. At an input voltage level in the middle of the supply voltage both types of comparators show comparable gains and accuracies.  
         [0022]     In a further preferred embodiment, the selection unit selects the nMOS-based comparator if the voltage level is above the threshold voltage and the pMOS-based comparator is selected if the voltage level is below the threshold voltage. This yields a high gain, high accuracy comparator circuit.  
         [0023]     In another preferred embodiment, the selection unit comprises a selection output port, wherein the selection unit connects an output port either of the first comparator or the second comparator to the selection output port, depending on the selection of the selection unit. Thus, the output signal of the selected comparator can be processed further, for example in a preferred ADC or a preferred rail-to-rail comparator building block.  
         [0024]     According to a preferred embodiment, the reference voltage is defined by the voltage signals which are being compared by the comparators. Preferably, this is the case for applications in analog-to-digital converters. In such an ADC the reference voltage applied to the comparators is altered step by step during determining the most significant bit down to the least significant bit. In general, such a successive approximation procedure is well known in the art.  
         [0025]     According to a further embodiment, means for adjusting the reference voltage depending on the voltage signals which are being compared by the comparators are coupled to the selection unit. This is preferred in an ADC using the successive approximation operation mode.  
         [0026]     According to another preferred embodiment, the means comprises a voltage divider and a third comparator with an input port for a threshold voltage and an output port for a digital decision signal. This can be favorably used in a general comparator circuit. Preferably in this embodiment, the third comparator comprises an input port for a voltage signal which is also applied to one of the comparators. In this configuration the third comparator is working as a voltage plane detector. The third comparator can be a single-rail comparator of simple design.  
         [0027]     Preferably, in a rail-to-rail comparator building block the selection unit comprises a multiplexor, the output port of which is selectably connectable to one of the comparator output ports via the selection unit. By using a multiplexor, it is not necessary to choose a special kind of comparator type. Additionally or alternatively, it is possible to switch off that one comparator which has not been selected by the selection unit. In this case it may be appropriate to replace the multiplexor by a NAND (Not AND) or a NOR (Not OR) gate. Switching off the comparator means that a strobe signal is not generated in the respective comparator and/or the supply voltage is disconnected or the like. For this purpose it is advisable to choose a comparator with appropriate properties which are well known to skilled persons.  
         [0028]     In a very useful embodiment, the comparators are assigned to the comparator stage of an analog-to-digital converter, where, preferably, a sample-and-hold unit is assigned to each of the two comparators.  
         [0029]     Principally, it is even possible that at least one of the sample-and-hold units is equipped with a first and a second comparator and a selection unit for selecting one of the comparators depending on a selection condition.  
         [0030]     Most preferably, the analog-to-digital converter is of a successive-approximation type.  
         [0031]     At least one of the first and second comparators can be a single-rail-type unit. A mismatch as known from analog rail-to-rail solutions as well as a speed degradation can be avoided.  
         [0032]     Most preferably, at least one of the first and second comparators is a latch-type device. This yields a very fast comparator circuit. Advantageously, the latch type device is equipped with a dummy inverter yielding a nearly symmetric output.  
         [0033]     A method for operating a comparator circuit is proposed, wherein a first voltage signal is compared with a second voltage signal, and either a first comparator or a second comparator is selected depending on a selection condition.  
         [0034]     Preferably, the selection condition is the voltage signal being above or below a threshold voltage. The most accurate one of the two comparators can be selected depending on the threshold voltage. Being a digital selection, distortions, inaccuracies as well as speed degradation can be avoided. Further, one of the two comparators is preferably adapted for a first input voltage range and the other is adapted for a second input voltage range essentially different from the first input voltage range.  
         [0035]     Particularly, the threshold voltage and/or a reference voltage can be defined by the voltage signals which are being compared by the comparators.  
         [0036]     A preferential step is to select an nMOS-based comparator if the voltage level is above the threshold voltage and a pMOS-based comparator if the voltage level is below the threshold voltage. Each comparator can work in an input voltage range where its gain is high, yielding a high accuracy voltage comparison.  
         [0037]     An analog-to-digital conversion can be made, wherein in or during a first step one of the comparators is chosen depending on the threshold voltage as selection decision.  
         [0038]     Favorably, in the beginning of the successive approximation analog-to-digital conversion the selection of one of the comparators and a first analog-to-digital conversion is performed in the same step. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0039]     The present invention together with the above-mentioned and other objects and advantages may best be understood from the following detailed description of the embodiments, but not restricted to the embodiments, wherein is shown in:  
         [0040]      FIG. 1 a  first preferred embodiment in the form of a rail-to-rail comparator building block;  
         [0041]      FIG. 2 a  second preferred embodiment in the form of an analog-to-digital converter;  
         [0042]      FIG. 3   a,b  a preferred pMOS based comparator (a) and a preferred nMOS based comparator (b); and  
         [0043]      FIG. 4 a  flow diagram of a successive-approximation algorithm applied on the preferred analog-to-digital converter of  FIG. 2 . 
     
    
       [0044]     In the drawings identical elements or elements with identical functions are referred to with the same reference numeral.  
       DETAILED DESCRIPTION  
       [0045]     A preferred embodiment of the invention is depicted in  FIG. 1 . A comparator circuit comprises a first comparator  20  and a second comparator  30  and a selection unit  60 . The selection unit  60  is indicated with a dotted line. In this embodiment, the comparator circuit represents a high accuracy rail-to-rail comparator building block.  
         [0046]     An input voltage signal Vin_p is fed into an input port  22  and an input voltage signal Vin_n is fed into an input port  24  of the first comparator  20 . An output port  26  of the first comparator  20  feeds an output signal to the selection device  60 .  
         [0047]     An input voltage signal Vin_p is fed into an input port  32  and an input voltage signal Vin_n is fed into an input port  34  of the second comparator  30 . An output port  36  of the second comparator  30  feeds an output signal to the selection unit  60 .  
         [0048]     Most preferably, the first comparator  20  is equipped with pMOS transistors and therefore adapted for low input voltage levels and the second comparator  30  is equipped with nMOS transistors and therefore adapted for high input voltage levels. Details of the implementations are described in more detail in  FIG. 3   a  and  3   b.    
         [0049]     A voltage source is coupled to the selection unit  60  which, for example, comprises a simple voltage divider  120  with a first resistor unit  122  and a second resistor unit  124 . The center tap of the voltage divider  120  is connected to an input port  104  of a third comparator  100 . Another input port  102  of the third comparator  100  is connected to one of the input voltage signals Vin_p or Vin_n fed to the two comparators  20 ,  30 . In this example, the input port  102  is connected to the positive Vin_p voltage signal.  
         [0050]     The third comparator  100  can be a low accuracy component of a simpler design than the first and second comparators  20 ,  30  the third comparator  30  feeds a digital selection signal Vs from its output port  106  to a select input port  118  of a multiplexor  110  which assigned to the selection unit  60 .  
         [0051]     The output ports  26 ,  36  of the first and second comparators  20 ,  30  are connected to input ports  112 ,  114  of the multiplexor  110 . Depending on a selection condition one of the input ports  112 ,  114  and thus one of the output ports  26 ,  36  of the first and second comparators  20 ,  30  are connected through to an output port  116  of the multiplexor  110 .  
         [0052]     Preferably, the selection condition is a threshold voltage signal. The selection unit  60  selects one of the comparators  20 ,  30  depending on the voltage signal Vin_n, Vin_p being above or below a threshold voltage V 0 . The threshold voltage V 0  is generated by the voltage divider  120  and is, for example, in the middle of the operating voltage Vdd of the devices with V 0 =Vdd/2. If the input voltage Vin_p, Vin_n is above V 0 , the output port  36  of the second comparator  30  is connected to the output port  106  of the multiplexor  110 . If the input voltage Vin_p, Vin_n is below V 0 , the output port  26  of the first comparator  20  is connected to the output port  106  of the multiplexor  110 . The third comparator  100  feeds the appropriate decision signal Vs to the select port  118  of the multiplexor  110 . The selection unit  60  selects the very comparator  20  or  30  with the best gain for the actual input voltage Vin_p, Vin_n in a digital way.  
         [0053]     This results in an optimal selection of the most sensitive component, either comparator  20  or comparator  30 , especially for the most critical cases, where both input voltage signals Vin_p and Vin_n are close together and a high comparator gain is needed.  
         [0054]     The preferred embodiment depicted in  FIG. 2  represents a preferred high accuracy rail-to-rail analog-to digital converter. A comparator circuit comprises a first comparator  20  and a second comparator  30  and a selection unit  60 . The selection unit  60  is indicated with a dotted line.  
         [0055]     An input buffer stage  40  with an input port  42  and an output port  44  is assigned to the first comparator  20  and an input buffer stage  50  with an input port  52  and an output port  54  is assigned to the second comparator  30 .  
         [0056]     An input voltage signal Vin is fed through the buffer  40  into an input port  22  and an input voltage signal Vref is fed into an input port  24  of the first comparator  20 . An output port  26  of the first comparator  20  feeds an output signal to the selection device  60 .  
         [0057]     An input voltage signal Vin is fed through the buffer  50  into an input port  32  and an input voltage signal Vref is fed into an input port  34  of the second comparator  30 . An output port  36  of the second comparator  30  feeds an output signal to the selection unit  60 .  
         [0058]     Most preferably, the first comparator  20  is equipped with pMOS transistors and therefore adapted for low input voltage levels and the second comparator  30  is equipped with nMOS transistors and therefore adapted for high input voltage levels. Details of the implementations are described in more detail in  FIG. 3   a  and  3   b.    
         [0059]     A voltage source  70  is coupled to the selection unit  60 , yielding a reference voltage Vref, which can be biased by a digital control unit  62 . In the first conversion step for the most significant bit MSB, the reference voltage Vref corresponds to a threshold voltage V 0  equal to Vdd/2, wherein V 0  represents the selection condition. The comparator  20  or  30  selected in the first step is used for the following conversions steps.  
         [0060]     The output port  26  of the first comparator  20  and the output port  36  of the second comparator  30  are connected to the selection unit  60  via input ports  64   a  and  64   b , respectively. Depending on the selection condition either the output port  26  or the output port  36  is connected directly or indirectly to an output port  66  of the selection unit  60 .  
         [0061]     For a first conversion step of the analog to digital conversion, when the most significant bit MSB is determined, V 0  is at Vdd/2 and equals Vref, i.e. both comparators  20 ,  30  work at a high gain operating point resulting in a high accuracy. Therefore the first conversion step can be based on one of the two comparators  20 ,  30  without preference. The result of the first conversion step indicates the voltage plane of the input voltage Vin, i.e. in the range Vin&gt;Vdd or Vin&lt;Vdd.  
         [0062]     This result can be used to switch to the comparator  20  or  30  with the appropriate gain for the expected input voltage Vin for all following conversions down to the least significant bit LSB, finally yielding in a high accuracy rail-to-rail operation of the analog-to-digital converter. The shown principle can even be generally expanded to the input buffer stages  40 ,  50 .  
         [0063]     Preferably, the first and second comparators  20 ,  30  are latch-type comparators, as depicted in  FIG. 3   a  and  FIG. 3   b . Such comparator types are generally known in the art, as for example suggested for an nMOS latch-type comparator by Won-Chul Song et al., which has already been discussed in the introduction.  
         [0064]      FIG. 3   a  shows a comparator  20  equipped with pMOS transistors and  FIG. 3   b  shows a comparator  30  equipped with nMOS transistors. Other than in the prior art cited above, these devices comprise a dummy inverter  130  and  140 , respectively, to provide a more symmetric output stage, and are adapted to a preferred SOI technology (SOI=silicon-on-insulator) with body contact devices, which in principle is common to skilled persons.  
         [0065]     Whereas the gain of the nMOS based comparator is in acceptable range at high input voltages Vin, with Vin&gt;2Vdssat.n, wherein Vdssat.n is a saturation voltage of the nMOS-transistors, the pMOS based comparator works at its optimum for low input voltages Vin, with Vin&lt;Vdd−2Vdssat.p, wherein Vdd is the operation voltage and 2Vdssat.p is a saturation voltage of the pMOS-transistors. As known in the art, Vdssat is the saturation voltage of a transistor where the transistor is operated in its pinch-off regime, where the gain of the transistor is at its maximum. Vdssat is the voltage drop between the drain and the source of the transistor which is necessary to operate the transistor in its saturation regime at the respective gate-source-voltage (or the respective drain-source current).  
         [0066]     A preferred algorithm for operating the analog-to-digital converter shown in  FIG. 2  is a successive approximation mode as depicted in  FIG. 4 . In principle, an analog-to-digital conversion working with successive approximation is known in the art. For the preferred embodiment of  FIG. 2 , the successive approximation conversion method is expanded to two comparators  20 ,  30 .  
         [0067]     For a first conversion step  200  of the analog to digital conversion, when the most significant bit MSB is determined, V 0  is set to Vdd/2. After the first conversion step  200 , the appropriate comparator is selected in step  210 . In this first step  200 , the threshold voltage V 0  is equal to the reference voltage Vref.  
         [0068]     At this point, both comparators  20 ,  30  work at a high gain operating point resulting in a high accuracy. Therefore the first conversion step  200  can be based on one of the two comparators  20 ,  30  without preference. The result of the first conversion step indicates the voltage plane of the input voltage Vin, i.e. in the range Vin&gt;Vdd/2 or Vin&lt;Vdd/2. In this example, the second comparator  30  is used in the first step  200 .  
         [0069]     In step  210  a comparison is made if the input voltage signal Vin is above the threshold voltage V 0 , Vin&gt;V 0 . If Vin is below Vin, the first comparator  20  is selected in step  400  and the MSB is cleared. If yes, that is if a high input voltage is present, the conversion is continued with the second comparator  30  and the MSB is set in step  300 . As already mentioned, the second comparator  30  is used for the following conversions in this example.  
         [0070]     In step  302 , following after step  300 , the reference voltage Vref is set to the middle of the voltage interval: Vref=Vdd/2+Vdd/4, which is equal to middle of the detected voltage interval in the first step and the proper voltage interval for the next bit is selected.  
         [0071]     In step  304 , following after step  302 , a comparison is made if the input voltage signal Vin is above the reference voltage Vref: Vin&gt;Vref and so on, according to a usual successive approximation conversion.  
         [0072]     If after step  210  the comparison shows that the input voltage signal Vin is below the threshold, the first comparator  20  is selected in step  400  and the MSB is cleared. In this case, the first comparator  20  is used throughout the following conversions.  
         [0073]     Then in step  402 , following after step  400 , the reference voltage Vref is set to Vref=Vdd/2−Vdd/4, which is equal to middle of the detected voltage interval in the first step.  
         [0074]     In step  404 , following after step  402 , a comparison is made if the input voltage signal Vin is below the reference voltage Vref: Vin&lt;Vref, according to a usual successive approximation conversion. The conversion is continued with the first comparator  20 .  
         [0075]     Several following steps  306  and/or  406  are continued until the conversion is complete in step  220 .