Abstract:
A voltage generator includes a first voltage generation unit and a second voltage generation unit suitable for generating a second power supply voltage using a first power supply voltage, and being selectively driven, and a control signal generation unit suitable for activating the first voltage generation unit until the second power supply voltage reaches a specific level and activating the second voltage generation unit after the second power supply voltage reaches the specific level. The first voltage generation unit has less driving ability than the second voltage generation unit.

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
       [0001]    The present application claims priority of Korean Patent Application No. 10-2015-0046258, filed on Apr. 1, 2015, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    Exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a voltage generator for generating internal voltages. 
         [0004]    2. Description of the Related Art 
         [0005]    Semiconductor devices are supplied with a voltage from an external source. The external voltage rises to its target voltage at a specific rate during initial operations. If the external voltage is directly applied to the internal circuits of a semiconductor device, the internal circuits will likely malfunction because the target voltage is still rising (i.e. has not stabilized). In order to prevent such malfunctions, semiconductor devices perform a power-up operation for guaranteeing stable operation of the internal circuits. The power-up operation includes activating a power-up signal when the external voltage reaches its target voltage level. After the power-up signal is activated and the external voltage stabilizes, the external voltage is supplied to the internal circuits of the semiconductor device. 
         [0006]      FIG. 1  is a block diagram of a conventional voltage generator of a semiconductor device. 
         [0007]    Referring to  FIG. 1 , the voltage generator includes a regulator  110  and a charging unit  120 . 
         [0008]    The regulator  110  receives a first power supply voltage VCCE from an external source and generates a second power supply voltage VCCI that is lower than the first power supply voltage VCCE. The charging unit  120  includes a capacitor and stably outputs the second power supply voltage VCCI using the regulator  110 . That is, the charging unit  120  makes the second power supply voltage VCCI steady using the dampening characteristics of the capacitor. 
         [0009]    During a power-up section of a semiconductor device, the regulator  110  receives the first power supply voltage VCCE that rises to its target voltage level and generates the second power supply voltage VCCI. The internal circuits of the semiconductor device receive the first and the second power supply voltages VCCE and VCCI and generate various internal voltages, in response to a power-up signal that is activated when the first power supply voltage VCCE and the second power supply voltage VCCI reach a specific level or higher. 
         [0010]    During a fast power-up section, that is, if a power-up operation is performed at high speed, the semiconductor device rapidly generates the second power supply voltage VCCI by filling the charging unit  120  with a large amount of current. Accordingly, as the amount of peak current is increased during the power-up section, power consumed by the semiconductor device is increased. 
       SUMMARY 
       [0011]    Various embodiments are directed to a voltage generator for reducing the amount of peak current during a power-up section. 
         [0012]    In an embodiment, a voltage generator may include a first voltage generation unit and a second voltage generation unit suitable for generating a second power supply voltage using a first power supply voltage, and being selectively driven; and a control signal generation unit suitable for activating the first voltage generation unit until the second power supply voltage reaches a specific level and activating the second voltage generation unit after the second power supply voltage reaches the specific level, wherein the first voltage generation unit has less driving ability (i.e. cannot drive with as much power) than the second voltage generation unit. 
         [0013]    The control signal generation unit may drive the first voltage generation unit during a power-up section and drives the second voltage generation unit when the second power supply voltage reaches the specific level after the power-up section, in response to the second power source voltage. 
         [0014]    The control signal generation unit may receive the first power supply voltage and the second power supply voltage and generates a control signal for driving the first voltage generation unit and the second voltage generation unit. 
         [0015]    The control signal generation unit may include a driving unit suitable for driving the control signal with a first voltage level in response to the first power supply voltage; a feedback unit suitable for maintaining the control signal at the first voltage level; a control unit suitable for driving the control signal with a second voltage level; and a trigger unit suitable for driving the control unit in response to the second power source voltage. 
         [0016]    The driving unit may include a first charging element coupled between a first power supply voltage terminal for applying the first power supply voltage and a first node; and a first NMOS transistor and a first PMOS transistor coupled in series between the first node and a ground voltage terminal for applying a ground voltage, and wherein sources of the first NMOS transistor and the first PMOS transistor are coupled to a second node. 
         [0017]    The feedback unit may include a first resistor element coupled between the first power supply voltage terminal and a third node; a second NMOS transistor coupled between the third node and the ground voltage terminal and suitable for being driven in response to a voltage level of the first node; and a second PMOS transistor coupled between the first power supply voltage terminal and the second node and suitable for being driven in response to a voltage level of the third node. 
         [0018]    The trigger unit may receive a reference bias voltage, compares the second power supply voltage with the reference bias voltage, and drives the control unit if the second power supply voltage is higher than the reference bias voltage. 
         [0019]    The trigger unit may drive the control unit if the second power supply voltage is a predetermined voltage level or higher. 
         [0020]    The trigger unit may include a third NMOS transistor suitable for being driven in response to the second power supply voltage; a fourth NMOS transistor suitable for being driven in response to the reference bias voltage; a fifth NMOS transistor coupled between source regions of the third and the fourth NMOS transistors and the ground voltage terminal and being driven in response to the reference bias voltage; a third PMOS transistor suitable for being coupled between the first power source voltage terminal and a fourth node coupled to a drain of the third NMOS transistor; and a fourth PMOS transistor suitable for being coupled between the first power source voltage terminal and a drain region of the fourth NMOS transistor, wherein gate regions of the third and the fourth PMOS transistors are coupled to a drain region of the fourth PMOS transistor in common. 
         [0021]    The control unit may include a fifth PMOS transistor and a second charging element coupled in series between the first power supply voltage terminal and the ground voltage terminal, wherein the fifth PMOS transistor is driven in response to a voltage level of the fourth node, and a drain of the fifth PMOS transistor and a first end of the second charging element are coupled to a sixth node; a sixth NMOS transistor coupled between the fourth node and the ground voltage terminal and suitable for being driven in response to a voltage level of the sixth node; and a seventh NMOS transistor coupled between the first node and the ground voltage terminal and suitable for being driven in response to the voltage level of the sixth node. 
         [0022]    The control unit may further include an eighth NMOS transistor coupled between the sixth node and the ground voltage terminal and suitable for being driven in response to a power-on reset signal. 
         [0023]    The trigger unit may include a third NMOS transistor suitable for being driven in response to the second power supply voltage; and a third PMOS transistor coupled between the third NMOS transistor and the ground voltage terminal and having a gate and a drain coupled to the ground voltage terminal. 
         [0024]    The control unit may include a second resistor element coupled between the first power supply voltage terminal and a fourth node coupled to a drain of the third NMOS transistor; a fourth PMOS transistor and a second charging element coupled in series between the first power supply voltage terminal and the ground voltage terminal, wherein the fourth PMOS transistor is driven in response to a voltage level of the fourth node, and a drain of the fifth PMOS transistor and a first end of the second charging element are coupled to a fifth node; a fourth NMOS transistor coupled between the fourth node and the ground voltage terminal and suitable for being driven in response to a voltage level of the fifth node; and a fifth NMOS transistor coupled between the first node and the ground voltage terminal and suitable for being driven in response to the voltage level of the fifth node. 
         [0025]    The second voltage generation unit may include a regulating unit suitable for receiving the first power supply voltage and generating the second power supply voltage by regulating the received first power supply voltage; and a blocking unit suitable for receiving a control signal and deactivating the regulating unit in response to the control signal that is enabled. 
         [0026]    In an embodiment, a voltage generator may include a first voltage generation unit and a second voltage generation unit suitable for generating a second power supply voltage using a first power supply voltage, and being selectively driven, wherein the first voltage generation unit has less driving ability than the second voltage generation unit; and a control signal generation unit suitable for activating the first voltage generation unit during a power-up section and activating the second voltage generation unit when the first power supply voltage reaches a specific level after the power-up section. 
         [0027]    The control signal generation unit may include a first charging element coupled between a first power supply voltage terminal for applying the first power supply voltage and a first node; first and second NMOS transistors coupled in series between the first node and a ground voltage terminal for applying a ground voltage; a first PMOS transistor and a second charging element coupled in series between the first power supply voltage terminal and the ground voltage terminal; and a third NMOS transistor and a resistor element coupled in series between the first node and the ground voltage terminal, wherein the third NMOS transistor is driven in response to a voltage level of a second node to which a drain of the first PMOS transistor and a first end of the second charging element are coupled, wherein the first PMOS transistor is driven in response to a voltage level of the first node. 
         [0028]    The control signal generation unit may include a first charging element coupled between a first power supply voltage terminal for applying the first power supply voltage and a first node; and first NMOS and PMOS transistors coupled in series between the first node and a ground voltage terminal for applying a ground voltage, wherein sources of the first NMOS transistor and the first PMOS transistor are coupled to a second node. 
         [0029]    The voltage generator may further include a first resistor element coupled between the first power supply voltage terminal and a third node; a second NMOS transistor coupled between the third node and the ground voltage terminal and suitable for being driven in response to a voltage level of the first node; and a second PMOS transistor coupled between the first power supply voltage terminal and the second node and suitable for being driven in response to a voltage level of the third node. 
         [0030]    The voltage generator may further include a third PMOS transistor coupled between the first power supply voltage terminal and a fourth node and suitable for being driven in response to a voltage level of the first node; and a second charging element coupled between the fourth node and the ground voltage terminal. 
         [0031]    The voltage generator may further include a third NMOS transistor and a second resistor element coupled in series between the first node and the ground voltage terminal, wherein the third NMOS transistor is driven in response to a voltage level of the fourth node. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0032]      FIG. 1  is a block diagram of a conventional voltage generator of a semiconductor device. 
           [0033]      FIG. 2  is a block diagram of a voltage generator in accordance with an embodiment of the present invention. 
           [0034]      FIG. 3  is a circuit diagram of a first voltage generation unit illustrated in  FIG. 2 . 
           [0035]      FIG. 4  is a circuit diagram of a second voltage generation unit illustrated in  FIG. 2 . 
           [0036]      FIG. 5  is a circuit diagram illustrating the first embodiment of a control signal generation unit illustrated in  FIG. 2 . 
           [0037]      FIG. 6  is a circuit diagram illustrating the second embodiment of the control signal generation unit illustrated in  FIG. 2 . 
           [0038]      FIG. 7  is a circuit diagram illustrating the third embodiment of the control signal generation unit illustrated in  FIG. 2 . 
           [0039]      FIG. 8  is a circuit diagram illustrating the fourth embodiment of the control signal generation unit illustrated in  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION 
       [0040]    Various embodiments will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference in numerals refer to like parts throughout the various figures and embodiments of the present invention. 
         [0041]    Hereinafter, a power-up section is defined as the time until the first power supply voltage VCCE, which is externally applied, rises and reaches a target voltage level. 
         [0042]      FIG. 2  is a block diagram of a voltage generator in accordance with an embodiment of the present invention. 
         [0043]    Referring to  FIG. 2 , the voltage generator may include a control signal generation unit  210 , a first voltage generation unit  220 , a reference voltage generation unit  230 , a second voltage generation unit  240 , and a voltage output unit  250 . 
         [0044]    The control signal generation unit  210  may externally receive a first power supply voltage VCCE. The control signal generation unit  210  may generate a control signal VTEM in response to the first power supply voltage VCCE. The control signal generation unit  210  may enable the control signal VTEM in an initial section in which the first power supply voltage VCCE rises and may disable the control signal VTEM in a section in which the first power supply voltage VCCE stabilizes and reaches its target level. The control signal VTEM controls the driving of the first voltage generation unit  220  and the second voltage generation unit  240 . Specifically, the first voltage generation unit  220  may be driven in response to the control signal VTEM that is enabled. The driving of the first voltage generation unit  220  may be deactivated and the second voltage generation unit  240  may be driven in response to the control signal VTEM that is disabled. 
         [0045]    The first voltage generation unit  220  may receive the first power supply voltage VCCE and the control signal VTEM outputted by the control signal generation unit  210 . The first voltage generation unit  220  may generate a first output voltage V_OUT 1  in response to the control signal VTEM. 
         [0046]    The reference voltage generation unit  230  may generate a first reference voltage VREF 1  and a second reference voltage VREF 2 . 
         [0047]    The second voltage generation unit  240  may receive the first power supply voltage VCCE, the control signal VTEM from the control signal generation unit  210 , and the second reference voltage VREF 2  from the reference voltage generation unit  230 . The driving of the second voltage generation unit  240  may be controlled in response to the control signal VTEM. The second voltage generation unit  240  may generate a second output voltage V_OUT 2  based on the first power supply voltage VCCE and the second reference voltage VREF 2 . For example, the second voltage generation unit  240  may include a regulator. The first voltage generation unit  220  has weaker driving ability than the second voltage generation unit  240 . 
         [0048]    The voltage output unit  250  may receive the first output voltage V_OUT 1  or the second output voltage V_OUT 2  and output a second power supply voltage VCCI. The voltage output unit  250  may include a capacitor. The voltage output unit  250  may charge the first output voltage V_OUT 1  and output the charged voltage as the second power supply voltage VCCI. Furthermore, the voltage output unit  250  may charge the second output voltage V_OUT 2  and output the charged voltage as the second power supply voltage VCCI. 
         [0049]    The operation of the voltage generator is described below. 
         [0050]    First, in the power-up section, the control signal generation unit  210  may enable the control signal VTEM in response to the first power supply voltage VCCE. The first voltage generation unit  220  may be driven in response to the enabled control signal VTEM, and the second voltage generation unit  240  may be deactivated in response to the enabled control signal VTEM. The first voltage generation unit  220  may receive the first power supply voltage VCCE and generate the first output voltage V_OUT 1 . The voltage output unit  250  may output the second power supply voltage VCCI using the first output voltage V_OUT 1 . 
         [0051]    After the power-up section, when the first power supply voltage VCCE reaches a target voltage level the control signal generation unit  210  may disable the control signal VTEM. The first voltage generation unit  220  may be deactivated in response to the disabled control signal VTEM. The second voltage generation unit  240  may be driven in response to the disabled control signal VTEM. The second voltage generation unit  240  may receive the first power supply voltage VCCE that has reached the target voltage level and the second reference voltage VREF 2  outputted by the reference voltage generation unit  230  and generate the second output voltage V_OUT 2 . The voltage output unit  250  may output the second output voltage V_OUT 2  as the second power supply voltage VCCI. 
         [0052]    The voltage generator in accordance with an embodiment of the present invention may generate the second power supply voltage VCCI using the first voltage generation unit  220  in the power-up section and generate the second power supply voltage VCCI using the second voltage generation unit  240  after the power-up section. Accordingly, although a power-up operation is performed at high speed, a large amount of peak current is not generated because the second power supply voltage VCCI is generated using the first voltage generation unit  220  having a weaker driving ability than the second voltage generation unit  240 . 
         [0053]    Furthermore, in an embodiment of the present invention, the control signal generation unit  210  may generate the control signal VTEM by sensing the second power supply voltage VCCI outputted by the voltage output unit  250 . The control signal generation unit  210  may generate the control signal VTEM in response to the first reference voltage VREF 1  outputted by the reference voltage generation unit  230 , and a detailed operation thereof is described with reference to  FIGS. 5 to 8 . 
         [0054]      FIG. 3  is a circuit diagram of the first voltage generation unit  220  illustrated in  FIG. 2 . 
         [0055]    Referring to  FIG. 3 , the first voltage generation unit  220  may include a resistor element R and an NMOS transistor MN 1  coupled in series between terminals of the first power supply voltage VCCE and a ground voltage VSSE. The first voltage generation unit  220  may further include a PMOS transistor MP 1  coupled between the terminals of the first power supply voltage VCCE and the ground voltage VSSE. Specifically, the NMOS transistor MN 1  may be driven in response to the control signal VTEM and may be coupled between a first node N 1  and the terminal of the ground voltage VSSE. The PMOS transistor MP 1  may be driven in response to the signal of the first node N 1 . 
         [0056]    If the control signal VTEM is enabled to a “high” level, a current path may be formed between the terminals of the first power supply voltage VCCE and the ground voltage VSSE because the NMOS transistor MN 1  is driven. If a voltage of the first node N 1  is higher than the threshold voltage of the PMOS transistor MP 1  based on the current path, the PMOS transistor MP 1  may be driven. When the PMOS transistor MP 1  is driven, a current path may be formed between the terminals of the first power supply voltage VCCE and the ground voltage VSSE. A voltage of the second node N 2  may be outputted as the first output voltage V_OUT 1  based on the current path. 
         [0057]      FIG. 4  is a circuit diagram of the second voltage generation unit  240  illustrated in  FIG. 2 . 
         [0058]    Referring to  FIG. 4 , the second voltage generation unit  240  may include a blocking unit  410  and a regulating unit  420 . 
         [0059]    The blocking unit  410  may receive the control signal VTEM and generate a blocking signal BLOCK. If the control signal VTEM is enabled, the blocking unit  410  may output the blocking signal BLOCK that has been enabled. In contrast, if the control signal VTEM is disabled, the blocking unit  410  may output the blocking signal BLOCK that has been disabled. 
         [0060]    The regulating unit  420  may include a PMOS transistor MP 1 , a register unit  421 , and an amplification unit  423 . 
         [0061]    The PMOS transistor MP 1  may have a source-drain path between the terminal of the first power supply voltage VCCE and a first node N 1  in order to apply the first power supply voltage VCCE to the first node N 1  and include a gate that responds to a signal of a second node N 2 . 
         [0062]    The amplification unit  423  may generate a driving signal DRVP corresponding to a difference between the second reference voltage VREF 2  and a feedback voltage VFEDB fed back by the register unit  421 . The amplification unit  423  may apply the generated driving signal DRVP to the second node N 2 . The second reference voltage VREF 2  may be generated by the reference voltage generation unit  230 . The amplification unit  423  may control the driving of the PMOS transistor MP 1  using the driving signal DRVP so that the feedback voltage VFEDB and the second reference voltage VREF 2  become the same. 
         [0063]    The blocking unit  410  is coupled between the amplification unit  423  and the PMOS transistor MP 1 , and may block the driving of the PMOS transistor MP 1  through the blocking signal BLOCK. 
         [0064]    The operation of the second voltage generation unit  240  is described below. 
         [0065]    For example, if the control signal VTEM is enabled, the blocking unit  410  may output the blocking signal BLOCK having a “high” level. The PMOS transistor MP 1  is unable to be driven in response to the blocking signal BLOCK having a “high” level. 
         [0066]    In contrast, if the control signal VTEM is disabled, the blocking unit  410  may output the blocking signal BLOCK having a “low” level to the second node N 2 . The PMOS transistor MP 1  may be driven in response to the blocking signal BLOCK having a “low” level. When the PMOS transistor MP 1  is driven, the first power supply voltage VCCE may be applied to the first node N 1 . As a result, when the PMOS transistor MP 1  is driven, a current path may be formed between the terminals of the first power supply voltage VCCE and the ground voltage VSSE. The feedback voltage VFEDB may be formed in a third node N 3  through the current path formed in the register unit  421 . The amplification unit  423  may output a voltage, corresponding to a difference between the feedback voltage VFEDB and the second reference voltage VREF 2 , to the gate of the PMOS transistor MP 1  as the driving signal DRVP. The amplification unit  423  may control the driving of the PMOS transistor MP 1  using the driving signal DRVP until the feedback voltage VFEDB and the second reference voltage VREF 2  become the same. 
         [0067]      FIG. 5  is a circuit diagram illustrating the first embodiment of the control signal generation unit  210  illustrated in  FIG. 2 . 
         [0068]    Referring to  FIG. 5 , the control signal generation unit  210  may include a driving unit  510  and a control unit  520 . 
         [0069]    The driving unit  510  may include a first charging element C 1 , a first NMOS transistor MN 1 , and a second NMOS transistor MN 2 . 
         [0070]    The first charging element C 1  may be coupled between the terminal of the first power supply voltage VCCE and a first node N 1 . The first NMOS transistor MN 1  and the second NMOS transistor MN 2  are coupled in series between the first node N 1  and the terminal of the ground voltage VSSE. Each of the first NMOS transistor MN 1  and the second NMOS transistor MN 2  may have a diode structure in which a gate is coupled to a drain. A voltage level of the first node N 1  may correspond to a voltage level of the control signal VTEM. 
         [0071]    The control unit  520  may include a first PMOS transistor MP 1 , a third NMOS transistor MN 3 , a resistor element R, and a second charging element C 2 . 
         [0072]    The first PMOS transistor MP 1  may have a source-drain path between the terminal of the first power supply voltage VCCE and a second node N 2  and include a gate that responds to the signal of the first node N 1 . The second charging element C 2  may be coupled between the second node N 2  and the terminal of the ground voltage VSSE. 
         [0073]    The third NMOS transistor MN 3  may have a drain-source path between the first node N 1  and the resistor element R and include a gate that responds to the signal of the second node N 2 . The resistor element R may be coupled between the third NMOS transistor MN 3  and the terminal of the ground voltage VSSE. 
         [0074]    The operation of the control signal generation unit  210  in accordance with the first embodiment of the present invention is described below. 
         [0075]    If the first power supply voltage VCCE starts to rise, a current path may be formed through the first charging element C 1 , the first NMOS transistor MN 1 , and the second NMOS transistor MN 2  of the driving unit  510 . A voltage of the first node N 1  rises in response to the first power supply voltage VCCE and it may rise by drain-source voltages of the first and the second NMOS transistors MN 1  and MN 2 . When a difference between the voltage of the first node N 1  and the first power supply voltage VCCE becomes higher than the threshold voltage of the first PMOS transistor MP 1 , the first PMOS transistor MP 1  may be driven in response to the voltage of the first node N 1 . When the first PMOS transistor MP 1  is driven, a current path may be formed between the terminals of the first power supply voltage VCCE and the ground voltage VSE. Accordingly, the second node N 2  may have a voltage of a “high” level. The third NMOS transistor MN 3  may be driven in response to the voltage of the second node N 2  having a “high” level. When the third NMOS transistor MN 3  is driven, a current path may be formed between the first node N 1  and the terminal of the ground voltage VSSE. The first node N 1  may be discharged to a “low” level by the current path. 
         [0076]    In other words, while the first power supply voltage VCCE gradually rises, the voltage of the first node N 1  may rise by the drain-source voltages of the first and the second NMOS transistors MN 1  and MN 2 . Thereafter, when the first power supply voltage VCCE rises up to a target level, the control unit  520  may change the voltage level of the first node N 1  to a “low” level. Accordingly, the control signal generation unit  210  in accordance with the first embodiment of the present invention may output the control signal VTEM having a “high” level to the first voltage generation unit  220  and the second voltage generation unit  240  during the power-up section and output the control signal ITEM having a “low” level to the first voltage generation unit  220  and the second voltage generation unit  240  after the power-up section. 
         [0077]      FIG. 6  is a circuit diagram illustrating the second embodiment of the control signal generation unit  210  illustrated in  FIG. 2 . 
         [0078]    Referring to  FIG. 6 , the control signal generation unit  210  may include a driving unit  610 , a feedback unit  620 , and a control unit  630 . 
         [0079]    The driving unit  610  may include a first charging element C 1 , a first NMOS transistor MN 1 , and a first PMOS transistor MP 1 . 
         [0080]    The first charging element C 1  may be coupled between the terminal of the first power supply voltage VCCE and a first node N 1 . The first NMOS transistor MN 1  may have a drain-source path between the first node N 1  and a second node N 2 , and may have a diode structure in which a gate is coupled to a drain. The first PMOS transistor MP 1  may have a source-drain path between the second node N 2  and the terminal of the ground voltage VSSE, and may have a diode structure in which a gate is coupled to a drain. A voltage level of the first node N 1  may correspond to that of the control signal VTEM. 
         [0081]    The feedback unit  620  may include a first resistor element R 1  a second NMOS transistor MN 2 , and a second PMOS transistor MP 2 . 
         [0082]    The first resistor element R 1  may be coupled between the terminal of the first power supply voltage VCCE and a third node N 3 . The second NMOS transistor MN 2  may have a drain-source path between the third node N 3  and the terminal of the ground voltage VSSE and include a gate that responds to the signal of the first node N 1 . The second PMOS transistor MP 2  may have a source-drain path between the terminal of the first power supply voltage VCCE and the second node N 2  and include a gate that responds to the signal of the third node N 3 . 
         [0083]    The control unit  630  may include a third PMOS transistor MP 3 , a third NMOS transistor MN 3 , a second resistor element R 2 , and a second charging element C 2 . 
         [0084]    The third PMOS transistor MP 3  may have a source-drain path between the terminal of the first power supply voltage VCCE and a fourth node N 4  and include a gate that responds to the signal of the first node N 1 . The second charging element C 2  may be coupled between the fourth node N 4  and the terminal of the ground voltage VSSE. The third NMOS transistor MN 3  may have a drain-source path between the first node N 1  and the second resistor element R 2  and include a gate that responds to the signal of the fourth node N 4 . The second resistor element R 2  may be coupled between the third NMOS transistor MN 3  and the terminal of the ground voltage VSSE. 
         [0085]    The operation of the control signal generation unit  210  in accordance with the second embodiment of the present invention is described below. 
         [0086]    When the first power supply voltage VCCE starts to rise, a current path may be formed through the first charging element C 1  the first NMOS transistor MN 1 , and the first PMOS transistor MP 1  of the driving unit  610 . A voltage of the first node N 1  rises in response to the first power supply voltage VCCE. The second NMOS transistor MN 2  may be driven in response to the voltage of the first node N 1 . When the second NMOS transistor MN 2  is driven, a current path may be formed through the first resistor element R 1  and the drain-source of the second NMOS transistor MN 2 . When the second NMOS transistor MN 2  is driven, the voltage of the third node N 3  may have a “low” level. The second PMOS transistor MP 2  may be driven in response to the voltage of the third node N 3  having a “low” level. When the second PMOS transistor MP 2  is driven, the voltage of the second node N 2  may have a “high” level. Accordingly, the first node N 1  may maintain a “high” level by the voltage of the second node N 2  because the first NMOS transistor MN 1  has been driven. That is, as indicated by a dotted line of  FIG. 6 , the voltage of the first node N 1  may maintain a “high” level by the feedback unit  620 . 
         [0087]    Thereafter, a difference between the voltage of the first node N 1  and the first power supply voltage VCCE may become higher than the threshold voltage of the third PMOS transistor MP 3 . At this point of time, the third PMOS transistor MP 3  may be driven in response to the voltage of the first node N 1 . When the third PMOS transistor MP 3  is driven, a current path may be formed between the terminals of the first power supply voltage VCCE and the ground voltage VSSE. Accordingly, the voltage of the fourth node N 4  may have a “high” level. The third NMOS transistor MN 3  may be driven in response to the voltage of the fourth node N 4  having a “high” level. When the third NMOS transistor MN 3  is driven, a current path may be formed between the first node N 1  and the terminal of the ground voltage VSSE. The first node N 1  may be discharged to a level by the current path. 
         [0088]    In other words, while the first power supply voltage VCCE gradually rises, the voltage of the first node N 1  may rise by the drain-source voltages of the first NMOS transistor MN 1  and the first PMOS transistor MP 1 . Thereafter when the first power supply voltage VCCE rises up to a target level, the control unit  630  may change the voltage level of the first node N 1  to a “low” level. Accordingly, in the control signal generation unit  210  in accordance with the second embodiment of the present invention, the control signal VTEM can maintain a “high” level in both cases of high and low speed power-up operations through the feedback unit  620 . The control signal generation unit  210  may output the control signal VTEM having a “high” level to the first voltage generation unit  220  and the second voltage generation unit  240  during the power-up section and output the control signal VTEM having a “low” level to the first voltage generation unit  220  and the second voltage generation unit  240  after the power-up section. 
         [0089]      FIG. 7  is a circuit diagram illustrating the third embodiment of the control signal generation unit  210  illustrated in  FIG. 2 . 
         [0090]    Referring to  FIG. 7 , the control signal generation unit  210  may include a driving unit  710 , a feedback unit  720 , a trigger unit  730  and a control unit  740 . 
         [0091]    The driving unit  710  may include a first charging element C 1 , a first NMOS transistor MN 1 , and a first PMOS transistor MP 1 . 
         [0092]    The first charging element C 1  may be coupled between the terminal of the first power supply voltage VCCE and a first node N 1 . The first NMOS transistor MN 1  may have a drain-source path between the first node N 1  and a second node N 2  and may have a diode structure in which a gate is coupled to a drain. The first PMOS transistor MP 1  may have a source-drain path between the second node N 2  and the terminal of the ground voltage VSSE and may have a diode structure in which a gate is coupled to a drain. A voltage level of the first node N 1  may correspond to that of the control signal VTEM. 
         [0093]    The feedback unit  720  may include a first resistor element R 1 , a second NMOS transistor MN 2 , and a second PMOS transistor MP 2 . 
         [0094]    The first resistor element R 1  may be coupled between the terminal of the first power supply voltage VCCE and a third node N 3 . The second NMOS transistor MN 2  may have a drain-source path between the third node N 3  and the terminal of the ground voltage VSSE and include a gate that responds to the signal of the first node N 1 . The second PMOS transistor MP 2  may have a source-drain path between the terminal of the first power supply voltage VCCE and the second node N 2  and include a gate that responds to the signal of the third node N 3 . 
         [0095]    The trigger unit  730  may include a third NMOS transistor MN 3  and a third PMOS transistor MP 3  coupled in series between a fourth node N 4  and the terminal of the ground voltage VSSE and each configured to have a source-drain path. 
         [0096]    The second power supply voltage VCCI may be applied to the gate of the third NMOS transistor MN 3 . The third PMOS transistor MP 3  may have a diode structure in which a gate is coupled to a drain. 
         [0097]    The control unit  740  may include a second resistor element R 2 , a fourth PMOS transistor MP 4 , a fourth NMOS transistor MN 4 , a fifth NMOS transistor MN 5 , and a second charging element C 2 . 
         [0098]    The second resistor element R 2  may be coupled between the terminal of the first power supply voltage VCCE and the fourth node N 4 . The fourth PMOS transistor MP 4  may have a source-drain path between the terminal of the first power supply voltage VCCE and a fifth node N 5  and include a gate that responds to the signal of the fourth node N 4 . The fourth NMOS transistor MN 4  may have a drain-source path between the fourth node N 4  and the terminal of the ground voltage VSSE and include a gate that responds to the signal of the fifth node N 5 . The in fifth NMOS transistor MN 5  may have a drain-source path between the first node N 1  and the terminal the ground voltage VSSE and include a gate that responds to the signal of the fifth node N 5 . The second charging element C 2  may be coupled between the fifth node N 5  and the terminal of the ground voltage VSSE. 
         [0099]    The operation of the control signal generation unit  210  in accordance with the third embodiment of the present invention is described below. 
         [0100]    The operations of the driving unit  710  and the feedback unit  720  may be the same as those of  FIG. 6 . The first voltage generation unit  220  may be driven in response to the control signal VTEM of the first node N 1  having a “high” level. The voltage output unit  250  may generate the second power supply voltage VCCI by the first voltage generation unit  220 . The second power supply voltage VCCI gradually rises and may become higher than the threshold voltages of the third NMOS transistor MN 3  and third PMOS transistor MP 3  of the trigger unit  730 . At this point in time, the voltage of the fourth node N 4  may have a “low” level by the trigger unit  730 . The fourth PMOS transistor MP 4  may be driven in response to the voltage of the fourth node N 4  having a “low” level. A current path may be formed through the fourth PMOS transistor MP 4  and the second charging element C 2 . The voltage of the fifth node N 5  may have a “high” level by the current path. The fourth NMOS transistor MN 4  and the fifth NMOS transistor MN 5  may be driven in response to the voltage of the fifth node N 5  having a “high” level. When the fourth NMOS transistor MN 4  is driven, the voltage of the fourth node N 4  may maintain a “low” level. When the fifth NMOS transistor MN 5  is driven, a current path may be formed through the fifth NMOS transistor MN 5 . Accordingly, the voltage of the first node N 1  may be discharged to a “low ” level. 
         [0101]    In the control signal generation unit  210  in accordance with the third embodiment of the present invention, the control signal VTEM can maintain a “high” level by the feedback unit  720  in both cases of high and low speed power-up operations. Furthermore, the control signal generation unit  210  can sense the second power supply voltage VCCI by the trigger unit  730 . When the second power supply voltage VCCI becomes a specific voltage or higher, the control unit  740  operates, and thus the control signal VTEM may be changed to a “low’ level. 
         [0102]    Accordingly, during a power-up section, the control signal generation unit  210  may output the control signal VTEM having a “high” level to the first voltage generation unit  220  and the second voltage generation unit  240 . The second power supply voltage VCCI may rise through the first voltage generation unit  220 . After the second power supply voltage VCCI reaches a target voltage level after the power-up section, the control signal VTEM having a “low” level may be outputted to the first voltage generation unit  220  and the second voltage generation unit  240 . The first voltage generation unit  220  may be deactivated in response to the control signal VTEM having a “low” level. 
         [0103]      FIG. 8  is a circuit diagram illustrating the fourth embodiment of the control signal generation unit  210  illustrated in  FIG. 2 . 
         [0104]    Referring to  FIG. 8 , the control signal generation unit  210  may include a driving unit  810 , a feedback unit  820 , a trigger unit  830 , and a control unit  840 . 
         [0105]    The driving unit  810  may include a first charging element C 1  a first NMOS transistor MN 1 , and a first PMOS transistor MP 1 . 
         [0106]    The first charging element C 1  may be coupled between the terminal of the first power supply voltage VCCE and a first node N 1 . The first NMOS transistor MN 1  may have a drain-source path between the first node N 1  and a second node N 2  and may have a diode structure in which a gate is coupled to a drain. The first PMOS transistor MP 1  may have a source-drain path between the second node N 2  and the terminal of the ground voltage VSSE and may have a diode structure in which a gate is coupled to a drain. A voltage level of the first node N 1  may correspond to that of the control signal VTEM. 
         [0107]    The feedback unit  820  may include a resistor element R, a second NMOS transistor MN 2 , and a second PMOS transistor MP 2 . 
         [0108]    The resistor element R may be coupled between the terminal of the first power supply voltage VCCE and a third node N 3 . The second NMOS transistor MN 2  may have a drain-source path between the third node N 3  and the terminal of the ground voltage VSSE and include a gate that responds to the signal of the first node N 1 . The second PMOS transistor MP 2  may have a source-drain path between the terminal of the first power supply voltage VCCE and the second node N 2  and include a gate that responds to the signal of the third node N 3 . 
         [0109]    The trigger unit  830  may include third to fifth NMOS transistors MN 3  to MN 5  and third and fourth PMOS transistors MP 3  and MP 4 . 
         [0110]    The third NMOS transistor MN 3  may have a drain-source path between a fourth node N 4  and a fifth node N 5  and include a gate that responds to the second power supply voltage VCC 1 . 
         [0111]    The fourth NMOS transistor MN 4  may have a drain-source path between the drain of the fourth PMOS transistor MP 4  and the fifth node N 5  and include a gate that responds to the first reference voltage VREF 1 . 
         [0112]    For example, the third NMOS transistor MN 3  to which the second power supply voltage VCCI is applied and the fourth NMOS transistor MN 4  to which the first reference voltage VREF 1  is applied may have different driving capabilities because there is a difference between the second power supply voltage VCCI and the first reference voltage VREF 1 . 
         [0113]    The fifth NMOS transistor MN 5  may have a drain-source path between the fifth node N 5  and the terminal of the ground voltage VSSE and include a gate that responds to the first reference voltage VREF 1 . 
         [0114]    The third PMOS transistor MP 3  may have a source-drain path between the terminal of the first power supply voltage VCCE and the fourth node N 4 . The gate of the third PMOS transistor MP 3  may be coupled to the gate of the fourth PMOS transistor MP 4 . 
         [0115]    The fourth PMOS transistor MP 4  may have a source-drain path between the terminal of the first power supply voltage VCCE and the fourth NMOS transistor MN 4 . The gate and drain of the fourth PMOS transistor MP 4  may be coupled. 
         [0116]    The control unit  840  may include a fifth PMOS transistor MP 5 , sixth to eighth NMOS transistors MN 6  to MN 8 , and a second charging element C 2 . 
         [0117]    The fifth PMOS transistor MP 5  may have a source-drain path between the terminal of the first power supply voltage VCCE and a sixth node N 6  and include a gate that responds to the signal of the fourth node N 4 . The sixth NMOS transistor MN 6  may have a drain-source path between the fourth node N 4  and the terminal of the ground voltage VSSE and include a gate that responds to the signal of the sixth node N 6 . The seventh NMOS transistor MN 7  may have a drain-source path between the first node N 1  and the terminal of the ground voltage VSSE and include a gate that responds to the signal of the sixth node N 6 . The second charging element C 2  may be coupled between the sixth node N 6  and the terminal of the ground voltage VSSE. Furthermore, the control unit  840  may include the eighth NMOS transistor MN 8  coupled between the gate of the seventh NMOS transistor MN 7  and the terminal of the ground voltage VSSE. The eighth NMOS transistor MN 8  may be driven in response to a power on reset (POR) signal POR. 
         [0118]    The operation of the control signal generation unit  210  in accordance with the fourth embodiment of the present invention is described below. 
         [0119]    The operations of the driving unit  810  and the feedback unit  820  may be the same as those of  FIG. 6 . The first voltage generation unit  220  may be driven in response to the control signal VTEM of the first node N 1  having a “high” level. The voltage output unit  250  may generate the second power supply voltage VCCI by the first voltage generation unit  220 . The second power supply voltage VCCI may become higher than the first reference voltage VREF 1  by a specific voltage or higher. At this point in time, a greater current path may be formed through the third NMOS transistor MN 3  than the fourth NMOS transistor MN 4  because the third PMOS transistor MP 3  and the fourth PMOS transistor MP 4  form a current mirror. Accordingly, the fourth node N 4  may have a “low” level. Furthermore, the third PMOS transistor MP 3  and the fourth PMOS transistor MP 4  may be deactivated in response to a current path that is formed through the fourth PMOS transistor MP 4  and the fourth NMOS transistor MN 4  and have a “high” level. The third PMOS transistor MP 3  and the fourth PMOS transistor MP 4  being deactivated may block the current path. As a result, when the second power supply voltage VCCI is a specific voltage or higher, the third and the fourth PMOS transistors MP 3  and MP 4  are deactivated to reduce current consumption that in the trigger unit  830 . 
         [0120]    The fifth PMOS transistor MP 5  may be driven in response to the voltage of the fourth node N 4  having a “low” level. When the fifth PMOS transistor MP 5  is driven, a current path may be formed through the source-drain of the fifth PMOS transistor MP 5  and the second charging element C 2 . The voltage of the sixth node N 6  may have a “high” level. The sixth NMOS transistor MN 6  and the seventh NMOS transistor MN 7  may be driven in response to the voltage of the sixth node N 6  having a “high” level. When the sixth NMOS transistor MN 6  is driven, the voltage of the fourth node N 4  may maintain a level. When the seventh NMOS transistor MN 7  is driven, the voltage of the first node N 1  may changed to a “low” level. Furthermore, when the eighth NMOS transistor MN 8  is driven in response to the POR signal POR, the driving of the sixth NMOS transistor MN 6  can be controlled. That is, during the power-up section, the initial voltage level of the sixth node N 6  can maintain a “low” level. 
         [0121]    In the control signal generation unit  210  in accordance with the fourth embodiment of the present invention, the control signal VTEM can maintain a “high ” level by the feedback unit  820  in both cases of high and low speed power-up operations. Furthermore, the control signal generation unit  210  can sense the second power supply voltage VCCI by the trigger unit  830 . When the second power supply voltage VCCI becomes a specific voltage or higher, the control unit  840  operates, and the control signal VTEM may change to a “low’ level by the control unit  840 . Furthermore, the third and the fourth PMOS transistors MP 3  and MP 4  of the trigger unit  830  may be deactivated to reduce current consumption. 
         [0122]    Accordingly, during a power-up section, the control signal generation unit  210  may output the control signal VTEM having a “high” level to the first voltage generation unit  220  and the second voltage generation unit  240 . The second power supply voltage VCCI may rise through the first voltage generation unit  220 . When the second power supply voltage VCCI reaches a target voltage level after the power-up section, the control signal VTEM having a “low” level may be outputted to the first voltage generation unit  220  and the second voltage generation unit  240 . The first voltage generation unit  220  may be deactivated in response to the control signal VTEM having a “low” level. Furthermore, an electric current consumed by the control signal generation unit  210  can be reduced because the current path of the trigger unit  830  is blocked when the second power supply voltage VCCI becomes a target voltage level. 
         [0123]    The voltage generator according to the proposed embodiment can reduce the amount of a peak current generated in a power-up section when it internally generates voltages using an external voltage. 
         [0124]    Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.