Abstract:
A substrate includes a single-layer capacitor and various external contacts. A first external contact provides a first electrical connection to the single-layer capacitor. A second external contact provides a second electrical connection to the single-layer capacitor. The first and third external contacts are electrically connectable to another electrical component, and internal metallization structures or vias of conductive material electrically connect the second contact and the third contact to facilitate the single-layer capacitor being connectable in a parallel circuit with the other electrical component.

Description:
FIELD OF THE INVENTION 
   The present invention relates to miniature monolithic capacitors. 
   BACKGROUND OF THE INVENTION 
   The development of integrated circuits has made it possible to place many circuit elements in a single semiconductor chip. Where part or all of the circuit is an analog circuit, such as a radio frequency transmitter or receiver, audio amplifier, or other such circuit, circuit design requires lumped elements that cannot be readily realized in monolithic integrated circuits. Capacitors in particular are frequently created as separate elements from the integrated circuit. The electronic device thus typically includes monolithic integrated circuits combined with external capacitors. 
   For such applications, monolithic ceramic capacitors have been used. For example, single capacitors made of ceramic materials, are known in the art. These are relatively small in size and can be surface mounted to a surface mount circuit board, or glued and wire bonded to a substrate in a hybrid circuit layout. 
   In an ideal model of a lumped element capacitor, the capacitor provides an ideal voltage/current relationship: 
           i   =     C   ⁢       ⅆ   v       ⅆ   t               
Unfortunately, particularly at high frequencies, capacitors used in electronic circuits deviate substantially from this ideal relationship. These deviations are generally modeled as an equivalent series resistance and equivalent series inductance, along with a capacitance that varies over frequency. In accordance with this model, a capacitor behaves as a series L-R-C circuit. At lower frequencies, the dominant impedance is the capacitive element C. However, at increasing frequencies, the impedance of the capacitive element C decreases; and the impedance of the inductive element L increases. Then, at the resonant angular frequency (LC) −0.5 , the inductive element becomes predominant; and the element ceases performing as a capacitor. Simultaneously, the capacitor dissipates some stored energy (typically through heating of conducting plates and traces), as represented by the series resistance R.
 
   Capacitor design typically must compromise between capacitance value and equivalent series resistance and inductance; greater capacitance typically can be created only at the cost of increased series resistance and inductance. Accordingly, equivalent series resistance and inductance are not avoidable, and electronic design must take them into account, particularly in high frequency products such as broadband receiver/transmitters, short wave devices, and the like. 
   Various monolithic ceramic structures have been developed to provide relatively small capacitors for highly integrated applications. A first such structure is known as a “multilayer ceramic capacitor”. This structure is formed by stacking sheets of green tape or greenware, i.e., thin layers of a powdered ceramic dielectric material held together by a binder that is typically organic. Such sheets, typically, although not necessarily, are of the order of five inches by five inches, can be stacked with additional layers, thirty to one hundred or so layers thick. After each layer is stacked, conductive structures are printed on top of the layer, to form internal plates that form the desired capacitance. When all layers are stacked, they are compressed and diced into capacitors. Then, the compressed individual devices are heated in a kiln according to a desired time-temperature profile, driving off the organic binder and sintering or fusing the powdered ceramic material into a monolithic structure. The device is then dipped in conductive material to form end terminations for the internal conductive structures, suitable for soldering to a surface mount circuit board or gluing and wire bonding to a hybrid circuit. 
   The design of known broadband capacitors involves a tradeoff between capacitance value and broadband performance. One known approach to managing series resistance and series inductance, is to parallel connect a multilayer capacitor with a single-layer capacitor. The larger value capacitor is chosen for its large capacitance value and is parallel connected to the smaller value capacitor that is chosen for its small equivalent series resistance. As will be appreciated, such a circuit exhibits multiple resonant frequencies, a first at the frequency (L1C1) −0.5 , and a second at the frequency (L2C2) −0.5 . Typically the larger valued capacitor has the larger series resistance and inductance value and thus, the lower resonant frequency. The smaller valued capacitor is chosen for high frequency performance resulting from low series resistance and series inductance values. At lower frequencies, the larger capacitor will produce acceptable performance; however, at higher frequencies, where the larger capacitor behaves increasingly less like a capacitor and more like an inductance, the smaller capacitor will be below its resonant frequency and perform well as a capacitor throughout the frequency of interest. 
   The parallel capacitor approach has been utilized in conjunction with ceramic chip capacitors to improve the high frequency performance of those capacitors. Multilayer and single-layer capacitor combinations are often designed to utilize surface mount technologies; and therefore, the capacitor terminal plates or contacts are on opposed upper and lower sides of the capacitor. In applications where it is desirable to use wirebonding connections, it is necessary to provide electrical connections with a wire bonded to an upper contact. As shown in  FIG. 4 , an integrated broadband capacitor  18  has a multilayer capacitor  20  with sets of opposed and parallel plates  21 ,  23  disposed in a ceramic dielectric body  25 . Each set of plates  21 ,  23  is electrically connected to a different one of the conductive contacts  22 ,  24  on opposite sides of a ceramic dielectric body  26  in a known manner. A higher frequency, single-layer capacitor  28  is formed from opposed plates  30 ,  32  that also serve as end contacts, with the contact  32  being electrically connected to a conductor  34 . The multilayer capacitor  20  is connected in parallel with a single-layer capacitor  28  to provide an equivalent circuit shown in  FIG. 4A . A connecting wire  36  connects an integrated circuit (“IC”)  38  with the contact  30  of the single-layer capacitor  28 . The connecting wire  36  is relatively long; and the inductance of the wire  36  increases loss in the system, thereby adversely affecting its performance. 
   Referring to  FIG. 5 , another known integrated broadband capacitor  40  made for wirebonding also has an equivalent circuit of parallel connected capacitors as shown in  FIG. 4A . The integrated capacitor  40  also has the multilayer capacitor  20  identical to the multilayer capacitor  20  of  FIG. 4 . The multilayer capacitor  20  is connected to a double single-layer capacitor  42 . The double single-layer capacitor is a substrate-like piece containing two single-layer capacitors. A first capacitor  44  is formed between plate contacts  46 ,  48 . Plate contact  46  is electrically connected by the wire  36  to IC  38 , and plate contact  48  is electrically connected to conductor  34 . Contact plates  50 ,  52 , which would normally form a capacitor therebetween, are shorted with a silver paste  54  that is fired at about 800 degrees C. A disadvantage of using such a capacitor  42  is that it is difficult to handle a 5 mil thick ceramic device in order to dip the plates  50 ,  52  in the silver paste; and often, the device is broken in the dipping process. 
   Thus, there is a need for a multilayer and single-layer broadband capacitor suitable for use with wirebonding that can be produced using existing automated production equipment and processes and does not require special handling and operations. 
   SUMMARY OF THE INVENTION 
   The present invention provides a capacitor having an effective broadband performance in an integrated, cost-effective structure that facilitates its use with wirebonding. Further, the integrated capacitor array of the present invention can be produced with existing automated equipment and processes and does not require special handling to make it suitable for wirebonding applications. 
   In accordance with principles of the present invention, a substrate includes a single-layer capacitor and various external contacts. A first external contact provides a first electrical connection to the single-layer capacitor and is electrically connectable to a first side of another electrical component. A second external contact provides a second electrical connection to the single-layer capacitor. A third external contact is electrically connectable to a second side of the other electrical component, and internal metallization structures or vias of conductive material electrically connect the second contact and the third contact to facilitate the single-layer capacitor being connectable in a parallel circuit with the other electrical component. 
   In one aspect of the invention, the single-layer capacitor is a lower value, higher frequency, multilayer capacitor, and the other electrical component is a higher value, lower frequency, multilayer capacitor. Those two capacitors are connected in a parallel circuit to form an integrated broadband capacitor. 
   These embodiments, and the above and other objects and advantages of the present invention shall be made apparent from the accompanying drawings and the description thereof. 

   
     BRIEF DESCRIPTION OF THE DRAWING 
     The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with a general description of the invention given above, and the detailed description of the embodiments given below, serve to explain the principles of the invention. 
       FIG. 1  illustrates one embodiment of an integrated broadband capacitor in accordance with one aspect of the present invention. 
       FIG. 2  illustrates another embodiment of an integrated broadband capacitor in accordance with further aspects of the present invention. 
       FIG. 3  illustrates a further embodiment of an integrated broadband capacitor in accordance with further aspects of the present invention. 
       FIG. 4  illustrates a known parallel combination of capacitors to form a broadband capacitor, and  FIG. 4A  illustrates an equivalent circuit diagram for this embodiment. 
       FIG. 5  illustrates another known parallel combination of capacitors to form a broadband capacitor. 
   

   DETAILED DESCRIPTION 
   Referring now to  FIG. 1 , in a first embodiment of an integrated broadband capacitor  60 , a higher value, lower frequency, multilayer capacitor  62  with conductive contacts  64 ,  66  is substantially identical to capacitor  20  previously described with respect to  FIG. 4 . A ceramic dielectric substrate  68 , which is normally used to provide two single-layer capacitors, is modified for this application. Often, the substrate  68  is made of a plurality of ceramic tape layers laminated together in a green ceramic state and fired to form a cured monolithic ceramic structure. A lower value, higher frequency, single-layer capacitor  69  is formed at one end of the substrate  68  by two internal plates  70 ,  72 . One or more internal metallization structures or vias of conductive material  80 ,  82  electrically connect the respective internal plates  70 ,  72  to respective external contacts  74 ,  76 . Examples of the vias  80 , 82  are described in U.S. Pat. No. 6,753,218, which patent and the references incorporated therein by reference are hereby incorporated in their entirety herein by reference. The external contacts  74 ,  76  are printed on the exterior of the substrate  68 . External contact  74  is connected by the wire  36  to IC  38 , and external contact  76  is electrically connected to the conductor  34 . 
   At an opposite end of the substrate  68 , two internal plates  84 ,  86  are electrically connected to respective external conductive contacts  88 ,  90  by one or more internal metallization structures or vias of conductive material  92 ,  94 . The external contact  88  is electrically connected to contact  66  of multilayer capacitor  60 , and external contact  90  is electrically connected to the conductor  34 . Normally, a capacitor would be formed by the internal plates  84 ,  86 . However, one or more other internal metallization structures or vias of conductive material  96  electrically connect the respective internal plates  84 ,  86 . The plates  84 ,  86  and vias  92 ,  94 ,  96  provide a substantially zero resistance current path through the substrate  68  between the conductive contacts  88 ,  90  and maintain the conductive contacts  88 ,  90  at substantially the same voltage potential. Thus, the external contacts  88 ,  90  in combination with the vias  92 ,  94 ,  96  are operable to electrically connect the contact  66  of multilayer capacitor  60  to the conductor  34 . Further, the vias  96  cause the integrated broadband capacitor  60  to have an equivalent circuit of parallel connected capacitors  62 ,  69  identical to that shown in  FIG. 4A . The integrated broadband capacitor  60  of  FIG. 1  has the advantage of being suitable for use with wirebonding processes while being made with automated production equipment and processes. 
   In another embodiment, referring to  FIG. 2 , an integrated broadband capacitor  100  includes the higher value, lower frequency, multilayer capacitor  62  with conductive contacts  64 ,  66  and a lower value, higher frequency, single-layer capacitor  102  at one end of a ceramic dielectric substrate  104 . The lower value, higher frequency capacitor  102  is formed by an internal plate  106  and the external conductive contact  74 . One or more internal metallization structures or vias of conductive material  108  connects the internal plate  106  with the external contacts  76 . External contact  74  is connected by the wire  36  to IC  38 , and external contact  76  is electrically connected to the conductor  34 . At an opposite end of the substrate  104 , an internal plate  110  is electrically connected to external conductive contacts  88 ,  90  by one or more respective internal metallization structures or vias  112 ,  114 . The plate  110  and vias  112 ,  114  provide a substantially zero resistance current path through the substrate  104  between the conductive contacts  88 ,  90  and maintain the conductive contacts  88 ,  90  at substantially the same voltage potential. The external contact  88  is electrically connected to contact  66  of multilayer capacitor  60 , and external contact  90  is electrically connected to the conductor  34 . The internal plate  110  and vias  112 ,  114  are operable to electrically connect the contact  66  of multilayer capacitor  60  to the conductor  34 . Thus, the integrated broadband capacitor  100  has an equivalent circuit of parallel connected capacitors  62 ,  102  identical to that shown in  FIG. 4A . 
   In a further embodiment, referring to  FIG. 3 , an integrated broadband capacitor  120  includes the higher value, lower frequency, multilayer capacitor  62  with conductive contacts  64 ,  66  and a higher frequency, single-layer capacitor  122  at one end of a ceramic dielectric substrate  124 . The higher frequency capacitor  122  is formed by the external conductive contacts  74 ,  77 . External contact  74  is connected by the wire  36  to IC  38 , and external contact  77  extends across a lower side of the substrate  124  and is electrically connected to the conductor  34 . At an opposite end of the substrate  124 , one or more internal metallization structures or vias of conductive material  126  electrically connect the external contacts  88 ,  77 . The via  126  provides a substantially zero resistance current path through the substrate  124  between the conductive contacts  88 ,  90  and maintains the conductive contacts  88 ,  90  at substantially the same voltage potential. The external contact  88  is electrically connected to contact  66  of multilayer capacitor  60 . Thus, the vias  126  are operable to electrically connect the contact  66  of multilayer capacitor  60  to the conductor  34 , and the integrated broadband capacitor  120  has an equivalent circuit of parallel connected capacitors  62 ,  122  identical to that shown in  FIG. 4A . It should be noted that with the contact  77  differing in length from the contacts  74 ,  88 , the substrate  124  is not reversible in use. However, as will be appreciated, in an alternative embodiment, the contact  77  can be split into two spaced-apart contacts similar to that shown in  FIGS. 1 and 2 , so that the substrate  124  would then be reversible in use. 
   While the present invention has been illustrated by a description of various embodiments and while these embodiments have been described in considerable detail, there is no intention to restrict or in any way limit the scope of the appended claims to such detail. Additional advantages and modifications will readily appear to those skilled in the art. Specifically, techniques described in these multiple embodiments may be combined in many ways beyond the particular combinations shown herein. For example, the independently adjustable parameters in forming a device in accordance with aspects of the invention include at least the following: 
   1. the use, or not, of floating interior plates in the lower value, higher frequency, single-layer capacitors, 
   2. the gap between the external, conductive contacts on the lower value, higher frequency, single-layer capacitors and any fringe-effect capacitances created thereby, and 
   3. the relative geometry of external conductive plates or contacts on the higher value, lower frequency multilayer capacitor, the lower value, higher frequency single-layer capacitor, and the conductors or traces to which the components are mounted. 
   A further potential variable to adjust is the type of ceramic used. Indeed, different layers in the ceramic structure may be made of ceramic materials having different molecular structures. Different ceramic materials may exhibit different performance in various attributes, such as relative dielectric constant, polarization, breakdown field strength, curing behavior, mechanical strength and mechanical stress and strain behavior. For example, a relatively low dielectric ceramic having relatively good high frequency behavior may be used in the lower value, higher frequency, single-layer capacitor, while a relatively high dielectric ceramic having relatively poorer high frequency behavior may be used in the higher value, lower frequency, multilayer capacitor. 
   The invention in its broader aspects is therefore not limited to the specific details, representative apparatus and method, and illustrative example shown and described. Accordingly, departures may be made from such details without departing from the spirit or scope of applicant&#39;s general inventive concept.