Abstract:
An interface detection circuit is used for detecting whether an interface of an electronic device is in good contact with an interface of a connection device. The interface detection circuit includes a pressure sensing module, a signal processing module, and a warning module. The pressure sensing module detects whether the pins of the interface of the electronic device is suffered pressure and transmits the detecting results to the signal processing module. The signal processing module magnifies and calculates the detecting results. The signal processing module outputs a control signal to the warning module. The warning module alerts the user whether the two interfaces make good contact with each other.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to an interface detection circuit. 
         [0003]    2. Description of Related Art 
         [0004]    Universal serial bus (USB) and serial advanced technology attachment (SATA) are popular interface communication standards used on most electronic devices. For example, a USB device or a USB data cable with a USB interface is usually connected to a computer for transmitting data. However, when the transmission of data fails, it is difficult to estimate whether the USB interface has a poor contact with the computer or the USB device is defective, which is inconvenient. 
         [0005]    Therefore, there is need for improvement in the art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    Many aspects of the present disclosure can be better understood with reference to the following drawing(s). The components in the drawing(s) are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawing(s), like reference numerals designate corresponding parts throughout the several views. 
           [0007]      FIG. 1  is a block diagram of an embodiment of an interface detection circuit connected to an electronic device and a connection device. 
           [0008]      FIG. 2  is a circuit diagram of the interface detection circuit of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0009]      FIG. 1  shows an embodiment of an interface detection circuit  12  set inside an electronic device  10  for detecting the connection of an interface  11  of the electronic device  10  and an interface  21  of a connection device  20 . Both of the interfaces  11  and  21  are universal serial bus (USB) interfaces. The interface detection circuit  12  is used for detecting and showing whether the interfaces  21  and  11  are contacted well, after each of the interfaces  21  and  11  are connected to each other. 
         [0010]    Each of the interfaces  21  and  11  includes a power pin VCC, a first data pin D+, a second data pin D−, and a ground pin GND. In the embodiment, the electronic device  10  can be a computer or a server. The connection device  20  can be a hard disk drive or a data card. 
         [0011]    Referring to  FIG. 2 , the interface detection circuit  12  includes a pressure sensing module  120 , a signal processing module  130 , a protection module, and a warning module  150 . The pressure sensing module  120  includes four bridge circuits  122 ,  124 ,  126 , and  128 . The signal processing module  130  includes four operation units  301 ,  303 ,  305 , and  307 . The protection module includes four protection switches, i.e. first to fourth diodes D 1 -D 4 . 
         [0012]    The bridge circuit  122  is located under the power pin VCC of the interface  11  and is connected to the operation unit  301  of the signal processing module  130 . The operation unit  301  is connected to the warning module  150  through the diode D 1  of the protection module. The bridge circuit  124  is located under the first data pin D+ of the interface  11  and is connected to the operation unit  303 . The operation unit  303  is connected to the warning module  150  through the diode D 2  of the protection module. The bridge circuit  126  is located under the second data pin D− of the interface  11  and is connected to the operation unit  305 . The operation unit  305  is connected to the warning module  150  through the diode D 3  of the protection module. The bridge circuit  128  is located under the ground pin GND of the interface  11  and is connected to the operation unit  307 . The operation unit  307  is connected to the warning module  150  through the diode D 4  of the protection module. 
         [0013]    The bridge circuit  122  includes four piezoresistors R 1 -R 4 . A first end of the piezoresistor R 1  is connected to a power source VCC. A second end of the piezoresisitor R 1  functions as a first output of the bridge circuit  122  and is grounded through the piezoresistor R 2 . A first end of the piezoresistor R 3  is connected to the power source VCC. A second end of the piezoresistor R 3  functions as a second output of the bridge circuit  122  and is grounded through the piezoresistor R 4 . 
         [0014]    The operation unit  301  includes a first amplifier U 1 , a second amplifier U 2 , and a third amplifier U 3 . A non-inverting input of the first amplifier U 1  is connected to the first output of the bridge circuit  122 . An inverting input of the first amplifier U 1  is connected to an output of the first amplifier U 1  through a resistor R 5 . A non-inverting input of the second amplifier U 2  is connected to the second output of the bridge circuit  122 . An inverting input of the second amplifier U 2  is connected to an output of the second amplifier U 2  through a resistor R 6 . A non-inverting input of the third amplifier U 3  is connected to the output of the first amplifier U 1  through a resistor R 7  and is ground by a resistor R 9 . An inverting input of the third amplifier U 3  is connected to the inverting input of the second amplifier U 2  through a resistor R 8 . The inverting input of the third amplifier U 3  is also connected to an output of the third amplifier U 3  through a resistor R 10 . The output of the third amplifier U 3  is connected to an anode of the diode D 1 . A cathode of the diode D 1  is grounded through a resistor R 11  and is connected to the warning module  150  through a resistor R 12 . The operation unit  301  also includes an adjustable resistor RV 1  connected between the inverting input of the amplifier U 1  and the output of the amplifier U 2 , for regulating magnification of the first amplifier U 1  and the second amplifier U 2 . 
         [0015]    The warning module  150  includes a transistor Q 1  and a light emitting diode (LED) D 5 . A base of the transistor Q 1  is connected to the cathode of the diode D 1  through the resistor R 12  and is grounded through a resistor R 13 . An emitter of the transistor Q 1  is grounded. A collector of the transistor Q 1  is connected to a cathode of the LED D 5 . An anode of the LED D 5  is connected to the power source VCC through a resistor R 14 . In one embodiment, the transistor Q 1  is an npn bipolar junction transistor. 
         [0016]    When any of the four piezoresistors R 1 -R 4  of the bridge circuit  122  is not pressed by the power pin VCC of the interface  11 , a voltage difference between the first output and the second output of the bridge circuit  122  is zero, which means the bridge circuit  122  is balanced. A voltage received by the non-inverting input of the first amplifier U 1  is equal to a voltage received by the non-inverting input of the second amplifier U 2 . A voltage output of the first amplifier U 1  is equal to a voltage output of the second amplifier U 2 . A voltage of the non-inverting input of the third amplifier U 3  is equal to a voltage of the inverting input of the third amplifier U 3 . The output of the third amplifier U 3  outputs a low level signal, such as logic 0. 
         [0017]    When any of the four piezoresistors R 1 -R 4  of the bridge  122  is pressed by the power pin VCC of the interface  11 , a voltage difference between the first output and the second output of the bridge  122  is generated, which means the bridge circuit  122  is unbalanced. The resistance of the adjustable resistor RV 1  is adjusted by testers when debugging or troubleshooting the interfaces at the manufacturer during production. The resistance of RV 1  is adjusted to make the voltage of the non-inverting input of the third amplifier U 3  greater than the voltage of the inverting input of the third amplifier U 3 . The output of the third amplifier U 3  outputs a high level signal, such as logic 1. In the embodiment, a same phase parallel differential amplifier consisted of the first amplifier U 1  and the second amplifier U 2  composes a two stage amplifier circuit with the third amplifier U 3 . The two stage amplifier circuit can enlarge the magnification of the operation unit  301  and improve the detection precision and efficiency. 
         [0018]    The work principle of each of the bridge circuits  124 ,  126 , and  128  is same as the bridge circuit  122 . The circuit structure and work principle of each of the operation units  303 ,  305 , and  307  are same as the operation unit  301 . The connection relationship and work principle between the diode D 2  and the operation unit  303 , the diode D 3  and the operation unit  305 , the diode D 4  and the operation unit  307  are same as the diode D 1  and operation unit  301 . 
         [0019]    If the interface  21  of the connection device  20  is in good contact with the interface  11  of the electronic device  10  after the interface  21  is inserted in the interface  11 , each pin of the interface  11  is respectively in contact with each pin of the interface  21 . The power pin VCC, the first data pin D+, the second data pin D−, and the ground pin GND of the interface  11  can get pressure respectively from the power pin VCC, the first data pin D+, the second data pin D−, and the ground pin GND of the interface  21 . Each of the bridge circuits  122 ,  124 ,  126 , and  128  gets pressure from the power pin VCC, the first data pin D+, the second data pin D−, and the ground pin GND of the interface  11 . The output of each of the operation units  301 ,  303 ,  305 , and  307  outputs a high level signal. The diodes D 1 -D 4  are turned on. A voltage of the base of the transistor Q 1  reaches a turn-on voltage of the transistor Q 1 . Therefore, the transistor Q 1  is turned on and the LED D 5  is turned on to emit light to indicate the interface  11  and the interface  21  make good contact with each other. In the embodiment, only when all the diodes D 1 -D 4  are turned on, the voltage of the base of the transistor Q 1  can reach the break-over voltage of the transistor Q 1 . 
         [0020]    If the interface  21  of the connection device  20  does not contact well with the interface  11  of the electronic device  10  after the interface  21  is inserted to the interface  11 , at least one of the pins of the interface  11  may not be in contact with the corresponding pin of the interface  21 . For example, the power pin VCC of the interface  11  is not in contact with the power pin VCC of the interface  21 . The bridge circuit  122  cannot get a pressure reading. The output of the operation unit  301  outputs a low level signal. The diode D 1  is turned off. The voltage of the base of the transistor Q 1  cannot reach the break-over voltage of the transistor Q 1 . The transistor Q 1  is turned off. Therefore, the LED D 5  does not emit light for showing the interface  11  has a poor contact with the interface  21 . 
         [0021]    The diodes D 1 -D 4  can also prevent the output of any one of the operation units from outputting signals to the outputs of the other operation units. 
         [0022]    The interface circuit  12  not only can detect the contact of the USB interfaces, but also can detect the contact of other types of interfaces, such as serial advanced technology attachment (SATA) interfaces. 
         [0023]    While the disclosure has been described by way of example and in terms of preferred embodiment, it is to be understood that the disclosure is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.