Abstract:
An electrostatic clamp for securing a semiconductor wafer during processing. The electrostatic clamp comprises a base member, a resistive layer, a dielectric layer including a gas pressure distribution micro-groove network, a gas gap positioned between a backside of a semiconductor wafer and the dielectric layer, and a pair of high voltage electrodes positioned between the resistive layer and the dielectric layer. The electrostatic clamp can further comprise at least one ground electrode positioned between the resistive layer and the dielectric layer that provides shielding for the gas pressure distribution micro-groove network. The electrostatic clamp is characterized by a heat transfer coefficient of greater than or about 200 mW/Kcm 2 , a response time of less than or about 1 second, and gas leakage of less than or about 0.5 sccm. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR §1.72(b).

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The present invention relates in general to apparatus used in fabricating semiconductor wafers and, more particularly, to a high-performance electrostatic clamp comprising a resistive layer, micro-grooves, and dielectric layer.  
           [0002]    There are several applications in the semiconductor manufacturing industry that require an electrostatic clamp (“ESC”) having significantly higher performance characteristics than existing ESCs. The application with the most challenging requirements is the SIMOX Ion Shower, which requires a heat transfer coefficient (“HTC”) of greater than or about 200 mW/Kcm 2  and HTC uniformity (up to within 3 mm of the edge of a semiconductor wafer) of less than or about 1%. Another application with high ESC requirements is that of the high current serial implanter, which also requires a HTC of greater than or about 200 mW/Kcm 2  (with a somewhat relaxed uniformity requirement), but which also requires a response time of less than or about 1 second and gas leakage of less than or about 0.5 sccm.  
           [0003]    Consequently, the inventors have recognized a need for improvements in ESC design.  
         SUMMARY OF THE INVENTION  
         [0004]    The present invention meets the above-mentioned need by providing a high-performance electrostatic clamp comprising a resistive layer, micro-grooves, and dielectric layer.  
           [0005]    Although the present invention is not limited to specific advantages or functionality, it is noted that the high-performance electrostatic clamp achieves a HTC of greater than or about 200 mW/Kcm 2 , uniformity of less than or about 1%, a response time of less than or about 1 second, and gas leakage of less than or about 0.5 sccm. Accordingly, the electrostatic clamp of the present invention successfully achieves the technical challenges presented by SIMOX, serial implanter, and other like semiconductor manufacturing applications by providing electrostatic clamping pressures of greater than or about 200 Torr (in order to accommodate back side gas pressures of greater than or about 100 Torr) without the occurrence of discharges in the dielectric. The electrostatic clamping pressure or force extends to the edge of a semiconductor wafer in order to get back side cooling gas to the edge, while avoiding the occurrence of wafer peel-off. In order to avoid plasma discharges, the electrostatic fields do not protrude beyond the wafer.  
           [0006]    In one embodiment of the present invention, an electrostatic clamp for securing a semiconductor wafer during processing is provided comprising a base member, a resistive layer, a dielectric layer, a gas gap, and a pair of high voltage electrodes. The dielectric layer includes a gas pressure distribution micro-groove network. The gas gap is positioned between a backside of a semiconductor wafer and the dielectric layer. The high voltage electrodes are positioned between the resistive layer and the dielectric layer.  
           [0007]    In accordance with another embodiment of the present invention, an electrostatic clamp for securing a semiconductor wafer during processing is provided comprising a base member, a resistive layer, a dielectric layer, a gas gap, a pair of high voltage electrodes, and at least one ground electrode. The dielectric layer includes a gas pressure distribution micro-groove network including a circumferential gas pressure distribution micro-groove and a plurality of radial gas pressure distribution micro-grooves in fluid communication with the circumferential gas pressure distribution micro-groove. The gas gap is positioned between a backside of a semiconductor wafer and the dielectric layer. The high voltage electrodes are positioned between the resistive layer and the dielectric layer. The ground electrode, which is positioned between the resistive layer and the dielectric layer, provides shielding for the gas pressure distribution micro-groove network.  
           [0008]    In accordance with still another embodiment of the present invention, an electrostatic clamp for securing a semiconductor wafer during processing is provided comprising a base member, a resistive layer, a dielectric layer, a gas gap, a pair of high voltage electrodes, and at least one ground electrode. The dielectric layer includes a gas pressure distribution micro-groove network and a circumferential gas scavenging micro-groove. The gas pressure distribution micro-groove network includes an outer gas pressure distribution micro-groove and a plurality of radial gas pressure distribution micro-grooves in fluid communication with the outer gas pressure distribution micro-groove. The gas gap is positioned between a backside of a semiconductor wafer and the dielectric layer. The high voltage electrodes are positioned between the resistive layer and the dielectric layer. The ground electrode, which is positioned between the resistive layer and the dielectric layer, provides shielding for the gas pressure distribution micro-groove network.  
           [0009]    These and other features and advantages of the present invention will be more fully understood from the following description of the invention taken together with the accompanying drawings. It is noted that the scope of the claims is defined by the recitations therein and not by the specific discussion of features and advantages set forth in the present description. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    [0010]FIG. 1 is a partial, cross-sectional view of an electrostatic clamp for securing a semiconductor wafer during processing according to the present invention;  
         [0011]    [0011]FIG. 2 is a schematic block diagram illustrating one application for an electrostatic clamp for securing a semiconductor wafer during processing according to the present invention;  
         [0012]    [0012]FIG. 3 is a plan view of a gas pressure distribution micro-groove network of an electrostatic clamp according to the present invention;  
         [0013]    [0013]FIG. 4 is a plan view of a gas pressure distribution micro-groove network and a circumferential gas scavenging micro-groove of an electrostatic clamp according to the present invention;  
         [0014]    [0014]FIG. 5 is a plan view of a ground electrode and a pair of high voltage electrodes of an electrostatic clamp according to the present invention; and  
         [0015]    [0015]FIG. 6 is a graph illustrating cooling gas flow (sccm) versus gap width (μm) for an electrostatic clamp according to the present invention. 
     
    
       [0016]    Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of the present invention.  
       DETAILED DESCRIPTION OF THE INVENTION  
       [0017]    Referring initially to FIG. 1, an electrostatic clamp  1  for securing a semiconductor wafer during processing in accordance with one exemplary embodiment of the present invention, is illustrated. The clamp  1  comprises a base member  2 , a resistive layer  4 , a dielectric layer  6 , and a pair of high voltage electrodes  5 . The high voltage electrodes  5  are positioned between the resistive layer  4  and the dielectric layer  6 . The base member  2 , which can comprise an alumina material, is positioned adjacent the resistive layer  4  and can be bonded thereto by a layer of adhesive epoxy material  3 . The resistive layer  4  can comprise a non-conductive material (i.e., glass) and can be produced using standard thick film screening techniques, which are well known in the art of semiconductor processing apparatus design. The dielectric layer  6  typically comprises a sapphire material, but can also comprise other aluminum oxide materials, such as alumina or combinations of sapphire and alumina, inter alia. The base member  2  and the dielectric layer  6  can be about 300 μm and about 200 μm thick, respectively. The resistive layer  4  can be about 25 μm thick.  
         [0018]    In accordance with the present invention, the electrostatic clamp  1  can be employed to hold a semiconductor wafer  12  for processing within a high-vacuum chamber. The chamber, shown generally as numeric indicator  15 , provides a controlled environment for processing semiconductor wafers and can have an internal pressure of less than 1 Torr. The wafer  12 , which can be about 300 mm in diameter and about 1.0 mm thick, defines a front side  12   a  and a backside  12   b . In addition, typically in processing semiconductor wafers, an energy source (not shown) can be provided that is configured to focus a high-energy beam onto the front side  12   a  of the semiconductor wafer  12 . The energy beam can be focused onto the front side  12   a  of the wafer  12  in a uniform manner across the diameter of the wafer  12 , and can be selected from an ion beam, an electron beam, a gas plasma, and combinations thereof.  
         [0019]    Although the present invention is configured to provide thermal conductivity for controlling the temperature of an article in a vacuum environment for a variety of potential applications, it is particularly applicable to providing means for securing a semiconductor wafer and scavenging of gasses employed for cooling a semiconductor wafer in an ion implantation system. Accordingly, the invention is described herein with respect to such an ion implantation system, for example, a SIMOX ion shower.  
         [0020]    Referring now to FIG. 2, there is schematically illustrated an ion shower implantation system for use with the present invention, wherein ions  8  from a uniform energy source  21  are generated for projection through a vertical accelerator column  23 , along a beam line  24 , to an end station  25 . Here ions  8  are directed onto a semiconductor wafer. The uniform energy source  21  is connected to a high-voltage power supply  22  and the uniform energy source  21 , the accelerator column  23 , the beam line  24 , and the end station  25  are all contained within the high-vacuum chamber  15 . The chamber  15  is maintained under high vacuum by a vacuum pumping device  26 . Typically, the ion implantation system is operated at a pressure level that is less than or about 1×10 −5  Torr when the ion beam is directed onto the wafer.  
         [0021]    With reference again to FIG. 1, the wafer  12  is positioned against the electrostatic clamp  1  with the backside  12   b  of the wafer  12  facing the dielectric layer  6 . A gas gap  13  is defined between the backside  12   b  of the wafer  12  and the dielectric layer  6 . The gas gap  13  can be less than or about 1 μm wide, more particularly, about 0.1 μm wide.  
         [0022]    As illustrated in FIG. 3, in accordance with one embodiment of the present invention, the dielectric layer  6  includes a gas pressure distribution micro-groove network. The network can include a circumferential gas pressure distribution micro-groove  8   a  and a plurality of radial gas pressure distribution micro-grooves  8   b  in fluid communication with the circumferential distribution micro-groove  8   a . The circumferential gas pressure distribution micro-groove  8   a  is positioned within about 1 mm of the outer perimeter of the electrostatic clamp  1 , and the radial micro-grooves  8   b  extend from the circumferential micro-groove  8   a  inward towards the center of the clamp  1 .  
         [0023]    In accordance with another embodiment of the present invention that is illustrated in FIG. 4, the gas pressure distribution micro-groove network includes an outer gas pressure distribution micro-groove  8   c  and a plurality of radial gas pressure distribution micro-grooves  8   d . The outer gas pressure distribution micro-groove  8   c  defines a semi-circumferential channel that is positioned within about 3 mm of the outer perimeter of the electrostatic clamp  1 . The radial micro-grooves  8   d  are in fluid communication with the outer micro-groove  8   c  and extend from the outer micro-groove  8   c  inward towards the center of the electrostatic clamp  1 .  
         [0024]    As further illustrated in FIG. 4, the dielectric layer  6  further comprises a circumferential gas scavenging micro-groove  10  that is positioned within about 1 mm of the outer perimeter of the electrostatic clamp  1  and within about 1 mm of the outer gas pressure distribution micro-groove  8   c . Accordingly, the gas scavenging micro-groove  10  is positioned between the outer perimeter of the electrostatic clamp  1  and the outer micro-groove  8   c . The circumferential gas scavenging micro-groove  10  can be greater than or about 100 μm wide and less than or about 200 μm deep. The gas distribution micro-grooves  8   a - 8   d  and the gas scavenging micro-groove  10  can be formed in the dielectric layer  6  using etching techniques well known in the art.  
         [0025]    Upon coming in contact with the semiconductor wafer  12 , the high-energy beam is converted into heat energy, which raises the temperature of the wafer  12 . In order to control the temperature of the semiconductor wafer  12 , a source of cooling gas can be introduced into the circumferential or outer gas pressure distribution micro-groove  8   a ,  8   c , which flows into and fills the gas gap  13  (see FIG. 1) to provide thermal conductivity for transferring heat from the wafer  12  to the electrostatic clamp  1  as described in commonly assigned U.S. Pat. Nos. 4,514,636 and 4,261,762, which are hereby incorporated by reference for their teaching of gas conduction cooling. The source of cooling gas can be under pressure of greater than or about 1 Torr, and can comprise gas with a high thermal conductivity, such as, for example, nitrogen, neon, helium, hydrogen, and combinations thereof. The source of cooling gas can be directed from a distant source through a regulator and leak valve (not shown) to the circumferential or outer micro-groove  8   a ,  8   c  via a gas supply hole  9  (see FIGS. 3 and 4). The electrostatic clamp  1  can further include a gas fitting (not shown) that is in fluid communication with the gas supply hole  9  and that extends through the clamp  1  for connection with the source of cooling gas.  
         [0026]    The gas gap  13  further defines a uniform heat conduction area, which is bounded by the gas pressure distribution micro-groove network, more specifically, by the circumferential or outer gas pressure distribution micro-groove  8   a ,  8   c . Cooling gas is initially fed from the source of cooling gas through the circumferential or outer  8   a ,  8   c  and then the radial distribution micro-grooves  8   b ,  8   d  until the gas pressure within the uniform heat conduction area of the gas gap  13  reaches equilibrium. Once this steady state is established, cooling gas flow occurs only in the area of the gas gap  13  that is between either the circumferential gas distribution micro-groove  8   a  and the outer edge of the clamp  1  (see FIG. 3), or the outer gas distribution micro-groove  8   c  and the circumferential gas scavenging micro-groove  10  (see FIG. 4). The gas scavenging micro-groove  10  can be in fluid communication with a scavenging pump (not shown), which draws spent cooling gas through a scavenging hole  11  (see FIG. 4) and out of the high-vacuum chamber  15 . There is no flow of cooling gas within the uniform heat conduction area of the gas gap  13  after the initial transient condition of establishing equilibrium pressure. Consequently, the gas pressure remains uniform across the majority of the semiconductor wafer  12  that is adjacent the uniform heat conduction area and, therefore, provides constant heat conductivity. Gas pressure within the gas gap  13  can be greater than or about 100 Torr. (Note that for the pressures and gaps considered here, the heat conduction is in the molecular free regime, and so the heat conduction is proportional only to the pressure).  
         [0027]    The radial gas pressure distribution micro-grooves  8   b ,  8   d  are not limited to any particular number, pattern or length. However, the gas pressure distribution micro-grooves  8   a - 8   d  can have a width such that the gas is at the viscous flow limit (i.e., 100× the mean free path). For H 2  gas pressure at 100 Torr, the width of the micro-grooves  8   a - 8   d  need only be about 100 μm. This allows the circumferential gas pressure distribution micro-groove  8   a  to be within 1 mm of the outer perimeter of the electrostatic clamp  1 , and the outer micro-groove  8   c  to be within 3 mm of the outer perimeter of the clamp  1 , which ensures uniformity of heat conduction over the wafer  12  with minimal edge exclusion.  
         [0028]    The radial gas pressure distribution micro-grooves  8   b ,  8   d , which can be about 100 μm wide, extend inward so that a high pressure gas “reservoir” is brought closer to the center of the electrostatic clamp  1 . By maintaining all areas of a semiconductor wafer within about 2 cm of such radial micro-grooves  8   b ,  8   d , the time to establish an equilibrium pressure at all points on the wafer  12  will be less than or about 1 second. The conductance in the section of dielectric between the circumferential or outer gas pressure distribution micro-groove  8   a ,  8   c  and the outer diameter of the clamp  1  or scavenging micro-groove  10 , respectively, is such that for a gap of about 100 μm, only about 0.2 sccm of H 2  gas is needed to establish a pressure of 100 Torr within the gas pressure distribution micro-grooves  8   a - 8   d . Accordingly, the present invention provides a uniform and responsive backside gas pressure distribution system, wherein cooling gas within the gas gap  13  remains in the molecular free regime (so that conductance is insensitive to gap width), while the gas within the gas pressure distribution micro-groove network remains in the viscous flow regime (where there are no pressure gradients along the micro-grooves). The gas pressure distribution micro-groove network provides efficient conductance to the gas gap  13  so that gas pressure within the gap  13  quickly achieves equilibrium.  
         [0029]    In order to maintain the molecular free condition of the greater than 100 Torr gas pressure within the gap  13  between the wafer  12  and the dielectric layer  6 , the surface of the dielectric  6  is polished to the same degree or a level exceeding that of the wafer  12 , which backside  12   b  is polished. The smoothness of the polished dielectric layer  6  should be at or near the 0.1 μm level and can be produced using chemical mechanical polishing (“CMP”) techniques that are well known in the art.  
         [0030]    However, there is a flow of gas between the outer gas pressure distribution micro-groove  8   c  and the circumferential gas scavenging micro-groove  10 , or the circumferential gas distribution micro-groove  8   a  and the outer edge of the clamp  1 , respectively. Gas leakage at these points is less than or about 0.5 sccm. This leads to a gradient in the pressure, which drops the pressure within the high-vacuum chamber  15  (&lt;1 Torr) at the wafer edge. This means that the conduction to the electrostatic clamp  1  drops to a very low value near the wafer edge. If a wafer is being uniformly heated by a uniform energy source, such as an ion beam, an imbalance of heating and cooling at the wafer edge amounts to edge heating. Since the conductivity of the semiconductor wafer is higher than the gas gap conductance, a hot spot can extend toward the center of the wafer. Although there is an edge exclusion of 3 mm on semiconductor wafers, the temperature effects at this 1 mm reduced thermal conductance area can extend well beyond this exclusion. Consequently, reference is made to commonly assigned U.S. patent application Ser. No. 10/278,640, which addresses the issue of edge heating by providing a lip for shielding the uncooled edge of a semiconductor wafer. The entire disclosure of U.S. Ser. No. 10/278,640 is incorporated herein by reference, as it is contemplated that the apparatus disclosed in that application could be used in combination with the electrostatic clamp  1  of the present invention.  
         [0031]    The temperature of the base member  2  can be controlled by circulating a fluid (i.e., water) through a channel (not shown), which is configured for receiving the flow of a cooling fluid. The channel can be formed as a spiral, a meandering path, or a series of interconnected channels. The channels are closed to define an enclosed conduit or conduits by a backing plate (not shown), which can be sealed against the underside of the base member  2 , opposite the resistive layer  4 . Openings are provided in the backing plate for coolant inlet and outlet fittings. Because the electrostatic clamp  1  is configured to perform under a wide range of temperature conditions, the cooling medium flowing through the channel can be either a liquid or a gas, depending on the application.  
         [0032]    In accordance with the present invention, the electrostatic clamp  1  further comprises a pair of high voltage electrodes  5  that are positioned between the resistive layer  4  and the dielectric layer  6  (see FIG. 1). The electrodes  5  comprise a positive electrode  5   a  and a negative electrode  5   b  (see FIG. 5), and can be connected to a switching power supply via a pair of high voltage electrode connectors  25   a ,  25   b . The switching power supply provides an electric signal to create an electrostatic clamping force on the wafer  12 , which is positioned above the dielectric layer  6 . The electric signal can be about 3 kilovolts DC and the clamping force can be greater than or about 200 Torr. Moreover, the electrostatic clamp  1  can optionally comprise one or more field clamping ground electrodes  7  that are positioned within about 1 mm of the outer perimeter of the clamp  1  (see FIGS. 1 and 5). The ground line formed by the ground electrode  7  need only be about 500 μm wide and can be positioned within about 300 μm of the high voltage electrodes  5 , thus allowing the clamping pressure to extend within 1 mm of the outer perimeter of the wafer  12 . The ground electrode  7  comprises a ground electrode connector  27 . Both the ground electrode  7  and high voltage electrodes  5  can be produced using standard thick film screening techniques.  
         [0033]    As illustrated in FIGS. 1 and 5, the ground electrode  7  can also be employed as a shield for the gas pressure distribution micro-groove network by positioning ground electrode lines, formed by the ground electrode  7 , between the resistive layer  4  and the dielectric layer  6  adjacent or under the distribution micro-grooves  8   a - 8   d . Here, the ground line need only be about 200 μm wide and positioned within about 300 μm of the high voltage electrodes  5 . The ground electrode  7  produces a field free region around the distribution micro-grooves  8   a - 8   d , thus preventing discharges within the micro-groove or dielectric. The field free region can be about 100 μm wide and does not significantly affect the clamping force provided by the electrostatic clamp  1 .  
         [0034]    Alternatively, the gas pressure distribution micro-grooves  8   a - 8   d  can be dimensioned such that the field intensification next to the micro-grooves is only about 30%. A discharge will be limited to charging the bottom of the micro-groove, after which the field intensification under the micro-groove will also be about 30%. Therefore, if the clamping field is reduced by about 30% of the dielectric breakdown (about 10 kV/mm for sapphire), no breakdown will occur in the dielectric layer  6 , and the discharge in the gas will be limited to only charging the micro-groove. Although this can reduce the clamping pressure, and therefore the cooling capability of the electrostatic clamp  1  by about 30%, it simplifies construction and still provides sufficiently high cooling capability.  
         [0035]    The ground electrode  7  can also provide a shield for the gas supply hole  9 . This is a particularly sensitive area for discharges due to the high gas pressure and long path length. By positioning the ground electrode  7  around the gas supply hole  9 , this inlet can be kept field free, without perturbing the clamping pressure for more than about 2 mm.  
         [0036]    As further illustrated in FIG. 1, the dielectric layer  6  separates the gas pressure distribution micro-groove network and the gas scavenging micro-groove  10  from the ground electrode  7 . The resistive layer  4  is laid over (or under, depending upon the orientation of the clamp  1 ) and in between the high voltage  5  and ground  7  electrodes. This removes field intensification at the edge of the electrodes and allows a field to be established with the dielectric layer  6 , with a magnitude up to the dielectric breakdown of the material, thus maximizing the attainable clamping pressure. For sapphire material, given its relatively high dielectric constant, this maximal field is greater than or about 15 kV/mm, which can result in a clamping pressure close to about 1 atmosphere.  
         [0037]    In processing semiconductor wafers, it is sometimes necessary to have a wafer positioned in an upside down orientation. Accordingly, it is contemplated that the electrostatic clamp  1  can be positioned in an opposite orientation than is shown in FIG. 1.  
         [0038]    In order that the invention may be more readily understood, reference is made to the following example, which is intended to illustrate the invention, but not to limit the scope thereof.  
         [0039]    [0039]FIG. 6 shows a graph of gas leakage flow (sccm) versus gas gap width (μm) for an electrostatic clamp in accordance with the present invention. The distance between the circumferential gas distribution micro-groove and the edge of a 300 mm semiconductor wafer was about 1 mm. N 2  gas was provided at 100 Torr. The values were dependent upon the surface smoothness of the electrostatic clamp and the semiconductor wafer.  
         [0040]    While the invention has been described by reference to certain typical embodiments, it should be understood that numerous changes could be made within the spirit and scope of the inventive concepts described. Accordingly, it is intended that the invention not be limited to the disclosed embodiments, but that it have the full scope permitted by the language of the following claims.