Abstract:
A method for forming a contact of a semiconductor deices is disclosed. More specifically, in the method for forming a contact of a semiconductor device, an interlayer dielectric (hereinafter, referred to as “ILD”) layer is polished using a CMP slurry having high selectivity to an oxide film in a STI (shallow trench isolation) etching process for forming a line-type storage node contact (hereinafter, referred to as “SNC”, and an ILD layer having a predetermined thickness is re-formed on the semiconductor substrate to secure a sufficient etching margin to a subsequent etching process, thereby preventing loss of a hard mask nitride film of a bit line and reducing fail of a self-aligned contact (hereinafter, referred to as “SAC”) between a storage node and a bit line.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention generally relates to a method for forming a contact of a semiconductor device, and more specifically, to a method for forming a contact of a semiconductor device wherein an interlayer dielectric (hereinafter, referred to as “ILD”) layer is polished using a CMP slurry having high selectivity to an oxide film in a STI (shallow trench isolation) etching process for forming a line-type storage node contact (hereinafter, referred to as “SNC”), and an ILD layer having a predetermined thickness is re-formed on the semiconductor substrate to secure a sufficient etching margin to a subsequent etching process, thereby preventing loss of a hard mask nitride film of a bit line and reducing fail of a self-aligned contact (hereinafter, referred to as “SAC”) between a storage node and a bit line.  
         [0003]     2. Description of the Prior Art  
         [0004]     The development of fine pattern formation technology has affected the high-integration trend of semiconductor devices, and the size of a unit cell of a semiconductor memory device has been reduced depending on high integration and high capacity of the semiconductor memory device.  
         [0005]     Specifically, in case of DRAM (Dynamic Random Access Memory) which leads increase of integration degree, vertical structures become complicated according to reduction of memory cell size. As a result, in order to increase the effective area of a capacitor, a capacitor is formed after a bit line is formed.  
         [0006]     In addition, when the bit line is formed, it is important to form a SNC for performing an electrical operation between a transistor and a capacitor.  
         [0007]     The SNC is formed by a line-type SAC process. In the line-type SAC process, a bit line is patterned, an ILD layer is formed, and the semiconductor substrate is etched except a part of the ILD layer for separating a contact.  
         [0008]     Here, in order to secure an etching margin for the etching process, the ILD layer having a predetermined thickness is required to remain on the bit line in the planarization process on the ILD layer. However, as a semiconductor device becomes microscopic, it is difficult to perform the planarization process on the ILD layer on the bit line, thereby forming the ILD layer of non-uniformity.  
         [0009]      FIGS. 1   a  to  1   f  are diagrams illustrating a conventional method for forming a contact of a semiconductor device.  
         [0010]     Referring to  FIG. 1   a,  a first ILD layer  5  using an oxide film is formed on a semiconductor substrate  1  having a cell transistor (not shown) and a lower poly silicone plug  3 .  
         [0011]     As shown in  FIG. 1   b,  the stacked structure of a barrier layer (not shown) material for bit line, a conductive layer (not shown) for bit line and a hard mask nitride film (not shown) are formed on the first ILD layer  5  of  FIG. 1   a,  and a selectively etching is performed the stacked structure to form a bit line  13  comprising a barrier layer pattern  7  for bit line, a conductive layer pattern  9  for bit line and a hard mask nitride film pattern  11 .  
         [0012]     As shown in  FIG. 1   c,  a bit line spacer  15  is formed at a sidewall of the bit line  13  of  FIG. 1   b.    
         [0013]     As shown in  FIG. 1   d,  a second ILD layer  17  is formed on the semiconductor substrate including bit line of  FIG. 1   c.    
         [0014]     The second ILD layer  17  of  FIG. 1   d  is polished using common CMP slurry. Due to the polishing process, an ILD layer having a predetermined thickness remains on the bit line  13 .  
         [0015]     The common CMP slurry including a colloidal or fumed SiO 2  abrasive and additive such as KOH/NH 4 OH has a pH ranging from 10 to 11 and a polishing selectivity in the range of 1:4 for a nitride film: oxide film.  
         [0016]     As shown in  FIG. 1   f,  a SNC etching process is performed on the planarized second ILD layer  17  shown in  FIG. 1   e  until the poly silicone plug  3  is exposed to form a SNC opening  19 .  
         [0017]     When the ILD layer is polished using the common slurry so that the ILD layer having a predetermined thickness remains on the bit line, the ILD layer on the bit line has large difference in the thickness, thereby causing loss of the hard mask nitride film in a subsequent SNC etching process.  
         [0018]     For example, if an etching process is performed after an etching target for forming a SNC opening is determined in the ILD layer having a thick thickness formed on the bit line, the hard mask nitride  11  is severely lost on the ILD layer  17  having a thick thickness as shown in  FIG. 2   a.  In this way, since the thickness of the hard mask nitride film becomes thinner by a SNC CMP process, errors of the bit line and SAC are generated in the etching process for forming a subsequent SN.  
         [0019]     On the other hand, if an etching process is performed after an etching target is determined in the ILD layer having a thin thickness formed on the bit line, the upper portion of the ILD layer  17  having a thin thickness is not polished but remains on the bit line as shown in  FIG. 2   b.  As a result, the SNC is not open.  
         [0020]     This shortcoming generates between area difference of the SNC region and size difference of the bottom region in the etching process. As a result, it is difficult to embody uniform device characteristics on the whole surface of the wafer.  
       SUMMARY OF THE INVNETION  
       [0021]     It is an object of the present invention to provide a method for forming a contact of a semiconductor device wherein an ILD layer is polished using a CMP slurry having more excellent polishing selectivity to an oxide film than to an nitride film and an ILD layer having a predetermined thickness is re-deposited to form the uniform ILD layer on a bit line, thereby securing a sufficient etching margin for performing a subsequent SNC etching process.  
         [0022]     In an embodiment, a method for forming a contact of a semiconductor device comprises the steps of:  
         [0023]     forming a first interlayer dielectric (ILD) layer on a semiconductor substrate having a cell transistor and a lower poly silicon plug thereon;  
         [0024]     forming a stacked structure of a barrier layer, a conductive layer and a hard mask nitride film on the first ILD layer, and selectively etching the stacked structure to form a bit line;  
         [0025]     forming an oxide film spacer at a sidewall of the bit line;  
         [0026]     forming a second ILD layer on the semiconductor substrate including the bit line;  
         [0027]     polishing the second ILD layer using CMP slurry having high selectivity for oxide film to expose the hard mask nitride film;  
         [0028]     forming a third ILD layer on the semiconductor substrate; and  
         [0029]     performing an etching process to form an opening for storage node contact exposing the lower poly silicon plug. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0030]      FIGS. 1   a  to  1   f  are diagrams illustrating a conventional method for forming a contact of a semiconductor device.  
         [0031]      FIGS. 2   a  to  2   b  are cross-sectional diagrams illustrating a thickness of an ILD layer on a bit line formed according to the conventional method.  
         [0032]      FIGS. 3   a  to  3   g  are diagrams illustrating a method for forming a contact of a semiconductor device according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0033]     The present invention will be described in detail with reference to the accompanying drawings.  
         [0034]     Referring to  FIG. 3   a,  a first ILD layer  25  is formed by depositing an oxide film on the semiconductor substrate  21  having a cell transistor (not shown) and a lower poly silicone plug  23 .  
         [0035]     As shown in  FIG. 3   b,  the stacked structure of a barrier layer (not shown) material for bit line, a conductive layer (not shown) for bit line and a hard mask nitride film (not shown) are formed on the first ILD layer  25  of  FIG. 3   a,  and a selectively etching is performed the stacked structure to form a bit line  33  comprising a barrier layer pattern  27  for bit line, a conductive layer pattern  29  for bit line and a hard mask nitride film pattern  31 .  
         [0036]     The barrier layer material for bit line is formed of Ti/TiN, and the conductive layer is tungsten.  
         [0037]     As shown in  FIG. 3   c,  a bit line spacer  35  is formed at a sidewall of the bit line  33  of  FIG. 3   b.    
         [0038]     As shown in  FIG. 3   d,  a second ILD layer  37  is formed on the semiconductor substrate of  FIG. 3   c.  Here, the first ILD layer and the second ILD layer are preferably formed using a common oxide film.  
         [0039]     As shown in  FIG. 3   e,  a CMP process is performed on the second ILD layer  37  of  FIG. 3   d  by using CMP slurry having selectivity for oxide film to expose the hard mask nitride film  31  as a polishing barrier film.  
         [0040]     The CMP slurry for oxide film comprises Ceria (CeO 2 ) as an abrasive and has a pH ranging from 4 to 10, preferably from 6 to 8 as CMP slurry composition for a STI process having. Distilled water or ultra-pure water is used as the solvent.  
         [0041]     Also, the CMP slurry for oxide film comprises an organic polymer as an additive which is preferably polyacrylic acid salt.  
         [0042]     An amount of the abrasive ranges from 0.5 to 10 wt %, preferably from 1 to 5 wt %, and an amount of the additive ranges from 0.5 to 10 wt %, preferably from 1 to 5 wt %.  
         [0043]     The selectivity ratio of slurry composition for a nitride film to oxide film according to an embodiment of the present invention ranges 1:10˜200, preferably 1:30˜200.  
         [0044]     The second ILD layer  37  is polished using CMP slurry for oxide film having high selectivity ratio of 1:10˜200 for a nitride film to oxide film to exposed the hard mask nitride film.  
         [0045]     As shown in  FIG. 3   f,  a third ILD layer  38  is uniformly formed on the second ILD layer  37  planarized by the polishing process of  FIG. 3   e.    
         [0046]     Here, the third ILD layer  38  is formed from a source selected from a group consisting of HDP PSG (high density plasma phosphosilicate glass), BPSG (borophosphosilicate glass), PSG (phosphosilicate glass), HDP USG (high density plasma undoped silicate glass), FSG (fluorosilicate glass), PE-SiH 4  (plasma enhanced-silane), LP-TEOS (low pressure-tetraethoxysilicate glass) and PE-TEOS (plasma enhanced-tetraethoxysilicate glass).  
         [0047]     Here, a thickness of the third ILD layer ranges from 500 to 5000 Å, preferably from 500 to 2000 Å.  
         [0048]     The SNC etching process is performed on the semiconductor substrate of  FIG. 3   f  to form an opening  39  for the SNC exposing the lower poly silicone plug as shown in  FIG. 3   g.    
         [0049]     In this way, after the hard mask nitride film is exposed and the third ILD layer having a predetermined thickness is re-deposited on the hard mask nitride film, the ILD layer having the uniform thickness can be formed on the bit line. As a result, loss of the hard mask nitride film can be prevented in a subsequent etching process for forming the SNC, thereby securing a sufficient etching margin and reducing errors between the SN and the bit line.  
         [0050]     As discussed earlier, in an embodiment of the present invention, after a second ILD layer is polished, a third ILD layer having a predetermined thickness is formed on the second ILD layer. As a result, loss of a bit line hard mask nitride film can be prevented in a subsequent etching process for forming a SNC, thereby a sufficient etching margin and reducing errors between the SN and the bit line. Accordingly, stable devices can be manufactured.