Abstract:
Integrated output driver circuits have sourcing and sinking current characteristics that reduce power (Vdd) and ground (Vss) bounce effects by making the dl/dt characteristic of the sourcing current to a load and/or sinking current from the load more nearly uniform during a pull-up or pull-down driving event. Improved speed characteristics can also be achieved using capacitive bootstrapping to quickly turn on a NMOS pull-down transistor, which controls the sinking current from the load, and/or PMOS pull-up transistor, which controls the sourcing current to the load.

Description:
FIELD OF THE INVENTION 
     The present invention relates to integrated circuit devices, and more particularly to integrated output driver circuits. 
     BACKGROUND OF THE INVENTION 
     Integrated circuits typically include output drivers therein for driving on-chip and off-chip loads. To reduce power (Vdd) bounce and ground (Vss) bounce problems in integrated circuits, circuit designers have developed techniques to slowly turn on the output drivers to minimize power and ground bounce effects. Such techniques typically result in a trade off between operating speed and power and ground bounce. One conventional technique for minimizing power and ground bounce in an output driver is illustrated by FIG.  1 . The output driver of FIG. 1 includes an NMOS pull-down transistor N 2  having a drain electrically coupled to an output OUT of the driver. When the NMOS pull-down transistor N 2  is turned on, the output OUT is pulled low to Vss. When the NMOS pull-down transistor N 2  is turned off, the output OUT is disposed in a high impedance state. The gate of the NMOS pull-down transistor N 2  is controlled by a driver control circuit. This control circuit includes a totem pole arrangement of a PMOS pull-up transistor P 1 , a resistor R 1  and an NMOS pull-down transistor N 1 , connected as illustrated. A gate of the PMOS pull-up transistor P 1  and a gate of the NMOS pull-down transistor N 1  are electrically connected together and responsive to an input signal IN. 
     In the output driver of FIG. 1, the resistor R 1  is included in order to slow down the rate at which the NMOS pull-down transistor N 2  is turned on in response to a logic 0 input signal IN. The inclusion of the resistor R 1  slows down the driver by slowing down the rate at which the voltage at the gate of NMOS pull-down transistor N 2  transitions from 0 volts to Vth volts (where Vth is the threshold voltage of the NMOS pull-down transistor N 2 ). However, the inclusion of the resistor R 1  does not significantly improve the ground bounce characteristics of the driver. The slow down in speed of the driver is particularly serious when Vdd is relatively low. In contrast, when Vdd is high, the sinking current provided by resistor R 1  increases and causes the voltage at the gate of the NMOS pull-down transistor N 2  to ramp up faster and this increases ground bounce. Thus, the use of a resistor makes speed slower at low Vdd and ground bounce greater at high Vdd. Moreover, at low temperature, the sinking current through resistor R 1  increases (because the resistance of resistor R 1  decreases) and the drain-to-source current through the NMOS pull-down transistor N 2  increases. This makes ground bounce worse at lower temperatures and speed slower at high temperatures. What is needed, therefore, are driver circuits having excellent ground and Vdd bounce characteristics that are at least substantially independent of changes in Vdd and temperature. 
     SUMMARY OF THE INVENTION 
     Integrated output driver circuits according to embodiments of the present invention have sourcing and sinking current characteristics that reduce power (Vdd) and ground (Vss) bounce effects by making the dl/dt characteristic of the sourcing current to a load and/or sinking current from the load more nearly uniform and substantially independent of Vdd and temperature. Improved speed characteristics can also be achieved using capacitive bootstrapping to quickly turn on an NMOS pull-down transistor, which controls the sinking current from the load, and/or PMOS pull-up transistor, which controls the sourcing current to the load. 
     In particular, an integrated driver circuit according to one embodiment of the present invention includes a first driver transistor and an output signal line electrically coupled to a first current carrying terminal of the first driver transistor. The first driver transistor may be an NMOS pull-down transistor having a drain connected to the output signal line and a source electrically coupled to a reference power supply line (e.g., Vss). The first driver transistor may also be a PMOS pull-up transistor having a drain connected to the output signal line and a source electrically coupled to a positive power supply line (e.g., Vdd). The driver circuit also includes a preferred driver control circuit. According to one aspect of this embodiment, the driver control circuit has a switchable pull-up path therein that extends between a gate of the first driver transistor and the positive power supply line. This switchable pull-up path includes a depletion mode transistor (NMOS or PMOS) having a first current carrying terminal electrically coupled to the gate of the first driver transistor. The depletion mode transistor may be a buried channel device. The gate and the first current carrying terminal of the depletion mode transistor are electrically connected together. The switchable pull-up path may also include a PMOS pull-up transistor having a drain electrically coupled to a second current carrying terminal of the depletion mode transistor and a source electrically coupled to the positive power supply line. 
     To improve speed characteristics, a bootstrap capacitor is provided having a first electrode electrically connected to the second current carrying terminal of the depletion mode transistor and a second electrode electrically connected to the first current carrying terminal of the depletion mode transistor. In particular, preferred high speed characteristics can be achieved by sizing the capacitor so that its capacitance is in a range between about 0.75 and 1.25 times C ideal , where C ideal =|Vth|(Cin)/(Vdd−|Vth|), Vth is a threshold voltage of the NMOS pull-down transistor, Cin is an input capacitance of the NMOS pull-down transistor and Vdd represents a magnitude of a power supply voltage applied to the positive power supply line. The on-state characteristics of the depletion mode transistor are also chosen so that its l dsat  characteristic has a right positive temperature coefficient (i.e., dl dsat /dT is positive). The value of the positive temperature coefficient is sufficient to at least substantially compensate for a reduction in majority carrier mobility in an N-type inversion layer channel of the NMOS pull-down transistor. This reduction in majority carrier mobility occurs in response to an increase in temperature over a first operating temperature range. According to another embodiment of the present invention, the driver control circuit has a switchable pull-down path that extends between the gate of the first driver transistor and the reference power supply line. This switchable pull-down path includes a depletion mode transistor having a first current carrying terminal electrically coupled to the gate of the first driver transistor, which is preferably a PMOS pull-up transistor. 
     Still further embodiments of an integrated driver circuit include a first NMOS pull-down transistor and a first PMOS pull-up transistor connected together in a totem pole arrangement that extends between a positive power supply line and a reference power supply line. A gate of the first NMOS pull-down transistor and a gate of the first PMOS pull-up transistor may be connected together or independently controllable in the event a high impedance output condition is desired. A first driver control circuit is provided having a switchable pull-up path therein that extends between a gate of the first NMOS pull-down transistor and the positive power supply line. This pull-up path includes a first depletion mode transistor having a first current carrying terminal electrically coupled to the gate of the first NMOS pull-down transistor. The first depletion mode transistor may be a PMOS or NMOS depletion mode transistor having its gate and source terminals connected together. A second driver control circuit is also provided having a switchable pull-down path therein that extends between a gate of the first PMOS pull-up transistor and the reference power supply line. This pull-down path includes a second depletion mode transistor having a first current carrying terminal electrically coupled to the gate of the first PMOS pull-up transistor. 
     The first and second depletion mode transistors are preferably buried channel devices having improved mobility characteristics resulting from reduced Si/SiO 2  interface scattering. It is also preferred that these buried channel devices have a peak channel dopant concentration therein at a level of about 1×10 18  cm −3  or less to reduce phonon scattering and impurity scattering. To achieve preferred device characteristics by reducing ground bounce, the l dsat(NMOS)  characteristics of the NMOS pull-down transistor should be made independent of temperature. This can be achieved by designing the first depletion mode transistor to compensate for reductions in mobility (and reductions in l dsat(NMOS) ) within the NMOS pull-down transistor. In particular, the first depletion mode transistor is designed to have temperature dependent l dsat  characteristic that meets the following relationship over at least a first portion of an operating temperature range: 0.005≦∂l dsat /∂T≦0.015, where T designates a temperature (° C.) within the operating temperature range. This temperature dependent characteristic of the first depletion mode transistor can be used to compensate for an NMOS pull-down transistor having a temperature dependent l dsat(NMOS)  characteristic that meets the following relationship over at least a second portion of the operating temperature range: −0.01≧∂l dsat(NMOS) /∂T≧−0.015. 
     The switchable pull-up path also includes a second PMOS pull-up transistor having a drain electrically connected to a second current carrying terminal of the first depletion mode transistor and a source electrically connected to the positive power supply line. The switchable pull-down path also includes a second NMOS pull-down transistor having a drain electrically connected to a second current carrying terminal of the second depletion mode transistor and a source electrically connected to the reference power supply line. A third NMOS pull-down transistor is provided that is electrically coupled to the pull-up path. The third NMOS pull-down transistor preferably has a drain electrically connected to the first current carrying terminal of the first depletion mode transistor. A third PMOS pull-up transistor is provided that is electrically coupled to the pull-down path. The third PMOS pull-up transistor preferably has a drain electrically connected to the first current carrying terminal of the second depletion mode transistor. A gate of the third NMOS pull-down transistor and a gate of the second PMOS pull-up transistor may be electrically connected together and responsive to a first input signal. A gate of the third PMOS pull-up transistor and a gate of the second NMOS pull-down transistor may be electrically connected together and responsive to a second input signal. 
     To improve speed characteristics, first and second bootstrap capacitors are provided. The first bootstrap capacitor has a first electrode electrically connected to a second current carrying terminal of the first depletion mode transistor and a second electrode electrically connected to the first current carrying terminal of the first depletion mode transistor. The second bootstrap capacitor has a first electrode electrically connected to a second current carrying terminal of the second depletion mode transistor and a second electrode electrically connected to the first current carrying terminal of the second depletion mode transistor. The first and second bootstrap capacitors are preferably sized to achieve fast turn on of the first NMOS pull-down transistor and first PMOS pull-up transistor, respectively. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an electrical schematic of a conventional integrated driver circuit. 
     FIG. 2 is an electrical schematic of an integrated driver circuit according to a first embodiment of the present invention. 
     FIG. 3 is an electrical schematic of an integrated driver circuit according to a second embodiment of the present invention. 
     FIG. 4 is an electrical schematic of an integrated driver circuit according to a third embodiment of the present invention. 
     FIG. 5 is an electrical schematic of an integrated driver circuit according to a fourth embodiment of the present invention. 
     FIG. 6 is an electrical schematic of an integrated driver circuit according to a fifth embodiment of the present invention. 
     FIG. 7 is an electrical schematic of an integrated driver circuit according to a sixth embodiment of the present invention. 
     FIG. 8A is a graph illustrating drain current (Id) versus drain-to-source voltage for an N-channel depletion mode MOSFET. 
     FIG. 8B is a graph illustrating saturated drain current versus temperature for an N-channel depletion mode MOSFET. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout and signal lines and signals thereon may be referred to by the same reference symbols. 
     Referring now to FIG. 2, an output driver circuit  10  according to one embodiment of the present invention includes an NMOS pull-down transistor N 2  as a first driver transistor and a driver control circuit that controls turn on and turn off of the first driver transistor. The driver control circuit includes a pull-up path defined by a PMOS pull-up transistor P 1  in series with a resistor R 1 . Additional elements may be provided in the pull-up path and one or more of these elements may extend between the resistor R 1  and the drain of the PMOS pull-up transistor P 1 . As illustrated, the pull-up path extends between the positive power supply line (e.g., Vdd) and the gate of the NMOS pull-down transistor N 2 . An NMOS pull-down transistor N 1  is also provided at the bottom of the pull-up path, as illustrated. A gate of the NMOS pull-down transistor N 1  and a gate of the PMOS pull-up transistor P 1  are electrically connected together and responsive to an input signal IN. An output OUT of the driver circuit  10  can be disposed in a high impedance state or pulled low to a ground reference potential (e.g., Vss). A bootstrap capacitor C 1  is provided in a pull-up path to increase the speed at which the NMOS pull-down transistor N 2  turns on when the PMOS pull-up transistor P 1  turns on in response to a logic 0 input signal IN. In particular, the bootstrap capacitor C 1  is provided to quickly pull-up the gate of the NMOS pull-down transistor N 2  to a voltage level of at least about Vth, where Vth is the threshold voltage of the NMOS pull-down transistor N 2 . To achieve preferred high speed characteristics, the bootstrap capacitor C 1  can be sized so that its capacitance is in a range between about 0.75 and 1.25 times C ideal , where C ideal =|Vth|(Cin)/(Vdd−|Vth|), Vth is a threshold voltage of the NMOS pull-down transistor N 2 , Cin is an input capacitance of the NMOS pull-down transistor N 2  and Vdd represents a magnitude of a power supply voltage applied to the positive power supply line (e.g., Vdd). 
     As illustrated by the driver circuit  20  of FIG. 3, it is preferable that the resistor R 1  of FIG. 2 be replaced by an NMOS depletion mode transistor DN 3  that can be designed to supply a more uniform displacement current to the gate of the NMOS pull-down transistor N 2 . The NMOS depletion mode transistor DN 3  may be replaced by a PMOS depletion mode transistor DP 7 , as illustrated by FIG.  6 . By connecting the gate and source of the NMOS depletion mode transistor DN 3  together so that Vgs(DN 3 )=0 volts, the displacement current provided to the MOS capacitor defined between the gate of NMOS pull-down transistor N 2  and the source, channel (body) and drain regions of NMOS pull-down transistor N 2 , becomes substantially independent of changes in the power supply voltage Vdd. This is because the saturated drain current (l dsat ) through the NMOS depletion mode transistor DN 3  stays relatively constant, notwithstanding changes in Vds(DN 3 ). This relative independence between Idsat and Vds is illustrated by FIG. 8A, which is a graph illustrating drain current (Id) versus drain-to-source voltage for an N-channel depletion mode MOSFET (at Vgs=0 volts). The driver circuit  20  also preferably includes a bootstrap capacitor C 1  to increase the speed at which the NMOS pull-down transistor N 2  turns on in response to turn on of the PMOS pull-up transistor P 1 . Like the driver circuit  10  of FIG. 2, the output OUT of the driver circuit  20  of FIG. 3 can be disposed in a high impedance state (when the input signal IN switches high to a logic 1 level) or pulled low to a ground reference potential (e.g., Vss) (when the input signal IN switches low to a logic 0 level). 
     The driver circuit  50  of FIG. 6 is similar to the driver circuit  20  of FIG. 3, however, the NMOS depletion mode transistor DN 3  of FIG. 3 has been replaced by a PMOS depletion mode transistor DP 7 . In particular, the driver circuit  50  of FIG. 6 includes an NMOS pull-down transistor N 11  that drives an output OUT and a pull-up path that drives a gate of the NMOS pull-down transistor N 11 . The pull-up path includes a PMOS depletion mode transistor DP 7  having a first current carrying terminal (e.g., drain) that is electrically connected to the gate of the NMOS pull-down transistor N 11 . A gate and a second current carrying terminal (e.g., source) of the PMOS depletion mode transistor DP 7  are connected together. A PMOS pull-up transistor P 6  is also provided in the pull-up path. A drain of the PMOS pull-up transistor P 6  is electrically connected to the second current carrying terminal of the PMOS depletion mode transistor DP 7  and a source of the PMOS pull-up transistor P 6  is connected to a positive power supply line Vdd, as illustrated. A bootstrap capacitor C 5  is also provided. The bootstrap capacitor C 5  has first and second electrodes connected to the first and second current carrying terminals of the PMOS depletion mode transistor DP 7 , respectively. To achieve preferred high speed characteristics, the bootstrap capacitor C 5  can be sized so that its capacitance is in a range between about 0.75 and 1.25 times C ideal , where C ideal =|Vth|(Cin)/(Vdd−|Vth|), Vth is a threshold voltage of the NMOS pull-down transistor N 11 , Cin is an input capacitance of the NMOS pull-down transistor N 11  and Vdd represents a magnitude of a power supply voltage applied to the positive power supply line (e.g., Vdd). 
     NMOS pull-down transistor N 10  is also included at a bottom of the pull-up path. As illustrated, a drain of the NMOS pull-down transistor N 10  is connected to the first current carrying terminal of the PMOS depletion mode transistor DP 7  and a source of the NMOS pull-down transistor N 10  is connected to a reference power supply line Vss. A gate of the NMOS pull-down transistor N 10  and a gate of the PMOS pull-up transistor P 6  are connected together and responsive to an input signal IN. When the input signal IN is driven high to a logic 1 level, NMOS pull-down transistor N 10  turns on to pull the gate of NMOS pull-down transistor N 11  low and dispose the output OUT in a high impedance state. Alternatively, when the input signal IN is driven low to a logic 0 level, the PMOS pull-up transistor P 6  turns on to pull the second current carrying terminal (and gate) of PMOS depletion mode transistor DP 7  high to a logic 1 level. The bootstrapping function provided by bootstrap capacitor C 5  will quickly pull the gate of NMOS pull-down transistor N 11  to Vth. Here, the bootstrap capacitor C 5  and the MOS capacitor defined at the input of the NMOS pull-down transistor N 11  operate as pair of capacitors that are electrically connected in series between the positive power supply line Vdd and the reference power supply line Vss. 
     Referring now to FIG. 4, an output driver circuit  30  according to another embodiment of the present invention includes a first driver transistor and a pull-down path that drives a gate of the first driver transistor. The first driver transistor is illustrated as a PMOS pull-up transistor P 3  having a source electrically coupled to a positive power supply line and a drain electrically coupled to an output signal line OUT. A gate of the PMOS pull-up transistor P 3  is electrically connected to a first current carrying terminal of an NMOS depletion mode transistor DN 5 . This NMOS depletion mode transistor DN 5  may be a buried channel device. The pull-down path also includes an NMOS pull-down transistor N 4  having a drain electrically connected to a second current carrying terminal of the NMOS depletion mode transistor DN 5 . The gate and source of the NMOS depletion mode transistor DN 5  are electrically connected together. A bootstrap capacitor C 2  is also provided across the first and second current carrying terminals of the NMOS depletion mode transistor DN 5 . This bootstrap capacitor C 2  can be sized so that its capacitance is in a range between about 0.75 and 1.25 times C ideal , where C ideal =|Vth|(Cin)/(Vdd−|Vth|), Vth is a threshold voltage of the PMOS pull-up transistor P 3 , Cin is an input capacitance of the PMOS pull-up transistor P 3  and Vdd represents a magnitude of a power supply voltage applied to the positive power supply line (e.g., Vdd). 
     A PMOS pull-up transistor P 2  is provided between the first current carrying terminal of the NMOS depletion mode transistor DN 5  and the positive power supply line. A gate of the PMOS pull-up transistor P 2  and a gate of the NMOS pull-down transistor N 4  are electrically connected together and responsive to an input signal IN. When the input signal IN is driven to a logic 0 level, the PMOS pull-up transistor P 2  turns on and pulls the gate of the PMOS pull-up transistor P 3  to a logic 1 level, thereby disposing the output OUT in a high impedance state. In contrast, when the input signal IN is driven to a logic 1 level, the NMOS pull-down transistor N 4  turns on. By capacitive coupling, the bootstrap capacitor C 2  quickly pulls the gate of PMOS pull-up transistor P 3  sufficiently low to enable turn on of the PMOS pull-up transistor P 3 . In particular, the size of the bootstrap capacitor C 2  relative to the MOS input capacitance of the PMOS pull-up transistor P 3  is chosen so that the gate of the PMOS pull-up transistor P 3  is pulled quickly to a level of less than about Vdd−|Vth|, where Vth is a threshold voltage of the PMOS pull-up transistor P 3 . Furthermore, the on-state characteristics of the NMOS depletion mode transistor DN 5  are also chosen so that its l dsat  characteristic has a right positive temperature coefficient (i.e., dl dsat /dT is positive). The value of the positive temperature coefficient, which causes the gate of PMOS pull-up transistor P 3  to be charged faster, is sufficient to at least substantially compensate for a reduction in majority carrier mobility in an P-type inversion layer channel of the PMOS pull-up transistor P 3 . This reduction in majority carrier mobility occurs in response to an increase in temperature over a first operating temperature range. 
     The output driver circuit  40  of FIG. 5 includes a CMOS inverter defined by an NMOS pull-down transistor N 9  and a PMOS pull-up transistor P 5 , connected as illustrated. The input of the CMOS inverter is connected to a first current carrying terminal of NMOS depletion mode transistor DN 6  and a first current carrying terminal of NMOS depletion mode transistor DN 7 . A pull-up path is provided by the NMOS depletion mode transistor DN 6  and a PMOS pull-up transistor P 4 . A pull-down path is provided by the NMOS depletion mode transistor DN 7  and NMOS pull-down transistor N 8 . As illustrated, a gate of the NMOS pull-down transistor N 8  and a gate of the PMOS pull-up transistor P 4  are connected together and responsive to an input signal IN. A first bootstrap capacitor C 3  and a second bootstrap capacitor C 4  are connected across the NMOS depletion mode transistors DN 6  and DN 7 , respectively. These NMOS depletion mode transistors DN 6  and DN 7  may be buried channel transistors and may be replaced by PMOS depletion mode transistors in an alternative embodiment. When the input signal IN provided to the output driver circuit  40  transitions to a logic 1 voltage level, the NMOS pull-down transistor N 8  turns on and through capacitive bootstrapping quickly pulls down the gate of PMOS pull-up transistor P 5  to a level sufficient to turn on the PMOS pull-up transistor P 5 . The depletion mode transistor DN 7  provides a substantially uniform current sinking characteristic that lowers a voltage at an input of the CMOS inverter in a manner that inhibits Vdd bounce. Alternatively, when the input signal IN provided to the output driver circuit  40  transitions from a logic 1 voltage level to a logic 0 voltage level, the PMOS pull-down transistor P 4  turns on and through capacitive bootstrapping quickly pulls up the gate of NMOS pull-down transistor N 9  to a level sufficient to turn on the NMOS pull-down transistor N 9 . The depletion mode transistor DN 6  also provides a substantially uniform current sourcing characteristic that raises a voltage at an input of the CMOS inverter in a manner that inhibits Vss bounce. 
     Referring now to FIG. 7, an output driver circuit  60  according to another embodiment of the present invention is similar to the driver circuit  40  of FIG. 5, however, the CMOS inverter at the output stage of the driver circuit  40  of FIG. 5 is replaced by independently controllable PMOS and NMOS transistors that provide a high impedance output state. In particular, the output driver circuit  60  of FIG. 7 includes a PMOS pull-up transistor P 9  that is driven by a first driver control circuit  62   a . The first driver control circuit  62   a , which is similar to the driver control circuit of FIG. 4, includes a pull-down path defined by an NMOS depletion mode transistor DN 12  in series with an NMOS pull-down transistor N 13 . A bootstrap capacitor C 6  is also provided across the current carrying terminals of the NMOS depletion mode transistor DN 12 . A PMOS pull-up transistor P 8  is also provided to turn off the PMOS pull-up transistor P 9  when a second input signal IN 2  is driven low. The output driver circuit  60  of FIG. 7 also includes an NMOS pull-down transistor N 16  that is driven by a second driver control circuit  62   b . The second driver control circuit  62   b , which is similar to the driver control circuit of FIG. 3, includes a pull-up path defined by an NMOS depletion mode transistor DN 14  in series with an PMOS pull-up transistor P 10 . A bootstrap capacitor C 7  is also provided across the current carrying terminals of the NMOS depletion mode transistor DN 14 . An NMOS pull-down transistor N 15  is also provided to turn off the NMOS pull-down transistor N 16  when a first input signal IN 2  is driven high. 
     The NMOS depletion mode transistors DN 12  and DN 14  are preferably buried channel devices having improved mobility characteristics resulting from reduced Si/SiO 2  interface scattering. It is also preferred that these buried channel devices have a peak channel dopant concentration therein at a level of about 1×10 18  cm −3  or less to reduce phonon scattering and impurity scattering. To achieve preferred device characteristics by reducing ground bounce, the l dsat(NMOS)  characteristics of the NMOS pull-down transistor N 16  should be made independent of temperature. This can be achieved by designing the depletion mode transistor DN 14  to compensate for reductions in mobility (and reductions in l dsat(NMOS) ) within the NMOS pull-down transistor N 16 . In particular, the depletion mode transistor DN 14  is designed to have temperature dependent l dsat  characteristic that meets the following relationship over at least a first portion of an operating temperature range: 
     
       
         0.005 ≦∂l   dsat   /∂T ≦0.015  (1) 
       
     
     where T designates a temperature (° C.) within the operating temperature range. This temperature dependent characteristic of the depletion mode transistor DN 14  can be used to compensate for an NMOS pull-down transistor N 16  having a temperature dependent l dsat(NMOS)  characteristic that meets the following relationship over at least a second portion of the operating temperature range: 
     
       
         −0.01 ≧∂l   dsat(NMOS)   /∂T ≧−0.015  (2) 
       
     
     From a gate control point of view, l dsat(NMOS)  is proportional to (Vg−Vth) N , where 1≦N≦2, where Vg is the voltage at the gate of the NMOS pull-down transistor N 16 . Accordingly, l dsat(NMOS)  is proportional to (exp(−αT))(Vg−Vth) N , where α is defined as ∂l dsat(NMOS) /∂T|. To keep l dsat(NMOS)  independent of temperature, the difference Vg−Vth should be made proportional to exp(αT/N). This implies that (∂(Vg−Vth)/∂T)/(Vg−Vth)=α/N. Because Vg is roughly proportional to l dsat  of the depletion mode transistor DN 14 , then it is preferably that ∂l dsat /∂T, which is approximately equal to α/N, fall within the range defined by equation (1). The relationship between l dsat  and T is graphically illustrated by FIG. 8B, over an operating temperature range between T 1  and T 2 , where T 1  is no less than about −40° C. and T 2  is no greater than about 100° C. 
     In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.