Abstract:
A system and method is disclosed for providing a strobed comparator with reduced offset and reduced charge kickback. The strobed comparator circuit comprises a differential pair of transistors coupled to a first switch circuit, a regenerative latch circuit, a first strobe signal line coupled to the switch circuit and a second strobe signal line coupled to the regenerative latch circuit. The first and second strobe signal lines provide separate strobe controls. The differential pair of transistors reduces the charge kickback effect by remaining in an “on” state. The differential pair of transistors is enabled when the regenerative latch circuit is in a reset condition and the regenerative latch circuit is enabled when the differential pair of transistors is in a saturation condition.

Description:
TECHNICAL FIELD OF THE INVENTION 
   The present invention is generally directed to manufacturing technology for semiconductor devices and, in particular, to a system and method for providing a strobed comparator with reduced offset and reduced charge kickback. 
   BACKGROUND OF THE INVENTION 
   Integrated circuit designers often use strobed comparators to achieve extremely high gains and good resolution. A strobed comparator is ideally designed to have low offset, a quick decision time and no static current. A strobed comparator works in two phases, a comparison phase and a reset phase. The comparison phase is carried out by two differentially connected transistors. In the comparison phase, input voltages are supplied to the two differentially connected transistors. A difference in the input voltages results in a difference in current that is fed to a regenerative latch that comprises two cross coupled transistors. 
   After the comparison phase has been completed, a reset phase is carried out. The regenerative latch must be reset to a balanced state to prepare the regenerative latch for the next comparison phase. The outputs of the strobed comparator become invalid after the strobed comparator has been placed in a reset phase. For this reason, a set reset (SR) latch coupled to the output of the strobed comparator holds the output values during the reset phase. 
   There are generally three methods to reset a strobed comparator. The first method employs a switch device on the common point of the differential pair of transistors. The second method employs a switch device on the output nodes of the differential pair of transistors. The third method employs a switch device across the regenerative latch in order to short the outputs together or to a common point. The third method is usually employed in conjunction with the first method or the second method in order to ensure a zero static current in the strobed comparator. 
   For purposes of illustrating the first method, consider an exemplary prior art strobed comparator circuit  100  shown in  FIG. 1 . The differential pair of transistors comprises N-type metal oxide semiconductor (NMOS) transistors M 40  and M 41 . The regenerative latch comprises P-type metal oxide semiconductor (PMOS) transistors M 10 , M 11 , M 20  and M 21 . PMOS transistors M 20  and M 21  are cross coupled. The switch device on the common point of the differential pair of transistors (M 40  and M 41 ) comprises NMOS transistor M 31 . 
   A strobe signal (designated “latch_b”) is provided to the gate of NMOS transistor M 31 . As shown in  FIG. 1 , the “latch_b” strobe signal is also provided to the gates of PMOS transistors M 10  and M 11  of the regenerative latch circuit. Prior art strobed comparator  100  provides the lowest value of offset as the differential pair of transistors (M 40  and M 41 ) go from the “off” region to the “saturation” region. As a result, the differential pair of transistors (M 40  and M 41 ) has a gain that is greater than one (“1”). This gain reduces the effect of the offset from the regenerative latch portion of the circuit. 
   Furthermore, the strobe signal is common to the differential pair of transistors (M 40  and M 41 ) and does not contribute to the offset. The disadvantage of the approach illustrated in strobed comparator  100  is that the input capacitance of the differential pair of transistors (M 40  and M 41 ) must be charged by the preceding stage (not shown in  FIG. 1 ) during the comparison phase and discharged during the reset phase. This creates a charge kickback effect in which the outputs of the previous stage create a glitch when the strobed comparator  100  is strobed. This feature makes it very difficult and challenging to design an appropriate preceding stage for strobed comparator  100 . 
   For purposes of illustrating the second method, consider an exemplary prior art strobed comparator circuit  200  shown in  FIG. 2 . The differential pair of transistors comprises N-type metal oxide semiconductor (NMOS) transistors M 40  and M 41 . The regenerative latch comprises P-type metal oxide semiconductor (PMOS) transistors M 10 , M 11 , M 20  and M 21 . PMOS transistors M 20  and M 21  are cross coupled. The two switch devices on the output nodes of the differential pair of transistors (M 40  and M 41 ) comprise NMOS transistors M 30  and M 31 . 
   A strobe signal (designated “latch_b”) is provided to the gate of NMOS transistor M 30  and to the gate of NMOS transistor M 31 . As shown in  FIG. 2 , the “latch_b” strobe signal is also provided to the gates of PMOS transistors M 10  and M 11  of the regenerative latch circuit. Prior art strobed comparator  200  provides a lower value of charge kickback but a much worse value of offset. The differential pair of transistors (M 40  and M 41 ) in strobed comparator  200  remains in the “linear” region during the reset phase and continue to be in the “linear” region during the start of the comparison phase. As a result, the differential pair of transistors (M 40  and M 41 ) has a gain that is less than one (“1”) and amplifies the offset from the regenerative latch portion of the circuit. 
   However, because the differential pair of transistors (M 40  and M 41 ) remains always in the “on” state, the preceding stage (not shown in  FIG. 2 ) does not have to provide significant charge during the comparison phase and during the reset phase. This reduces the charge kickback effect. 
   In view of the deficiencies of the prior art, there is a need for a system and method that is capable of providing a strobed comparator circuit that has a reduced value of offset and a reduced level of charge kickback. In particular, there is a need in the art for a system and method that is capable of minimizing the amount of offset and charge kickback in a strobed comparator circuit. 
   Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like. 
   Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts: 
       FIG. 1  illustrates a circuit diagram of a first type of prior art strobed comparator circuit; 
       FIG. 2  illustrates a circuit diagram of a second type of prior art strobed comparator circuit; 
       FIG. 3  illustrates a circuit diagram of a strobed comparator circuit of the present invention; 
       FIG. 4  illustrates a circuit diagram showing a set reset (SR) latch coupled to a strobed comparator circuit of the present invention; and 
       FIG. 5  illustrates four timing diagrams showing the variation over time of voltage signals utilized in the strobed comparator circuit of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 3 through 5 , discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any type of suitably arranged strobed comparator circuit. 
   A strobed comparator circuit  300  of the present invention is shown in  FIG. 3 . The strobed comparator circuit  300  provides (1) the reduced offset feature of prior art strobed comparator circuit  100 , and (2) the reduced charge kickback feature of prior art strobed comparator circuit  200 , and (3) zero static power. 
   The differential pair of transistors comprises N-type metal oxide semiconductor (NMOS) transistors Q 40  and Q 41 . The regenerative latch comprises P-type metal oxide semiconductor (PMOS) transistors Q 10 , Q 11 , Q 20  and Q 21 . PMOS transistors Q 20  and Q 21  are cross coupled. The two switch devices on the output nodes of the differential pair of transistors (Q 40  and Q 41 ) comprise NMOS transistors Q 30  and Q 31 . 
   A first strobe signal (designated “latch_b”) is provided to the gate of NMOS transistor Q 30  and to the gate of NMOS transistor Q 31 . A second strobe signal (designated “latch_b 1 ”) is provided to the gates of PMOS transistors Q 10  and Q 11  of the regenerative latch circuit. The use of two strobe signals separates the strobe control of the regenerative latch and the strobe control of the differential pair. 
   The differential pair of transistors (Q 40  and Q 41 ) in strobed comparator  300  remains in the “linear” region during the reset phase and continue to be in the “linear” region during the start of the comparison phase. As a result, the differential pair of transistors (Q 40  and Q 41 ) has a gain that is less than one (“1”) and amplifies the offset from the regenerative latch portion of the circuit. 
   However, because the differential pair of transistors (Q 40  and Q 41 ) remains always in the “on” state, the preceding stage (not shown in  FIG. 3 ) does not have to provide significant charge during the comparison phase and during the reset phase. This reduces the charge kickback effect. 
   During the reset phase, the regenerative latch transistors (Q 10 , Q 11 , Q 20 , Q 21 ) and the differential pair transistors (Q 40  and Q 41 ) are in reset, just the same as in strobed comparator  200 . However, there is an immediate pre-charge phase of operation where the differential pair transistors (Q 40  and Q 41 ) are enabled but the regenerative latch transistors (Q 10 , Q 11 , Q 20 , Q 21 ) are still held in reset. 
   During this pre-charge phase the differential pair transistors (Q 40  and Q 41 ) transition from the linear region (low gain) to the saturation region (high gain). After the differential pair transistors (Q 40  and Q 41 ) are in saturation and are ready for the comparison phase, the regenerative latch is released. This release defines the actual strobe point. Then the comparator makes a decision. 
   After the comparison phase, both the differential pair transistors (Q 40  and Q 41 ) and the regenerative latch transistors (Q 10 , Q 11 , Q 20 , Q 21 ) enter the reset phase nearly simultaneously. During the entire operation the differential pair transistors (Q 40  and Q 41 ) remain in the “on” region. This reduces the charge kickback effect. Because the pre-charge phase enables the differential pair transistors (Q 40  and Q 41 ) to be in the saturation region, the offsets from the regenerative latch transistors (Q 10 , Q 11 , Q 20 , Q 21 ) and the switch transistors (Q 30  and Q 31 ) are attenuated. This results in low overall offset. The strobed comparator  300  of the present invention provides reduced offset, reduced charge kickback and zero static power. 
     FIG. 4  illustrates a circuit diagram  400  showing a set reset (SR) latch coupled to strobed comparator  300  of the present invention. The “op” output of strobed comparator  300  is coupled to an input of inverter circuit  410 . The output of inverter circuit  410  is coupled to a “B” input of NOR gate  420 . The “on” output of strobed comparator  300  is coupled to an input of inverter circuit  430 . The output of inverter circuit  430  is coupled to a “B” output of NOR gate  440 . 
   The output of NOR gate  420  provides the “q” output of the set reset (SR) latch. The output of NOR gate  420  is also coupled to an “A” input of NOR gate  440 . The output of NOR gate  440  provides the “qb” output of the set reset (SR) latch. The output of NOR gate  440  is also coupled to an “A” input of NOR gate  420 .  FIG. 4  illustrates how the strobed comparator  300  of the present invention is utilized in conjunction with a set reset (SR) latch. 
     FIG. 5  illustrates four timing diagrams showing the variation over time of voltage signals utilized in the strobed comparator  300  of the present invention. The vertical scale of the timing diagrams represents voltage and the horizontal scale of the timing diagrams represents time. The “Precharge” phase is shown in each diagram as occurring in time between the two lines that extend vertically across all four timing diagrams. 
   In the first timing diagram (top diagram) the output voltage signals “on” and “op” of strobed comparator  300  are shown. The “Decision Point” is located in time immediately after the end of the “Precharge” phase. In the second timing diagram (the first diagram under the top diagram) the voltage signals at the drain of transistor Q 40  and the drain of transistor Q 41  are shown. During the “Precharge” phase the differential pair of transistors (Q 40  and Q 41 ) transition from the linear region (low gain) to the saturation region (high gain). 
   In the third timing diagram (the second diagram under the top diagram) the voltage signals for the “latch_b” strobe signal and the “latch_b 1 ” strobe signal are shown. The “latch_b” strobe signal begins its transition from “low” to “high” at the beginning of the “Precharge” phase. The “latch_b 1 ” strobe signal begins its transition from “low” to “high” at the end of the “Precharge” phase. The regenerative latch portion of strobed comparator  300  is released after the differential pair of transistors (Q 40  and Q 41 ) is in saturation and ready for the comparison phase. 
   In the fourth timing diagram (the third diagram under the top diagram) the voltage signal for the comparator output is shown. The comparator makes a decision after the regenerative latch portion of strobed comparator  300  has been released. 
   As may be seen in the timing diagrams shown in  FIG. 5 , the voltage signals shown in the first three timing diagrams are subsequently reset. As shown in the third timing diagram the strobe signal “latch_b” for the differential pair of transistors and the strobe signal “latch_b 1 ” for the regenerative latch circuit transistors are reset nearly simultaneously. The comparator output signal shown in the fourth timing diagram is not reset. 
   The foregoing description has outlined in detail the features and technical advantages of the present invention so that persons who are skilled in the art may understand the advantages of the invention. Persons who are skilled in the art should appreciate that they may readily use the conception and the specific embodiment of the invention that is disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Persons who are skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form. 
   Although the present invention has been described with an exemplary embodiment, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.