Abstract:
Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes shallow trench isolation filled with liquid phase deposited silicon dioxide (LPD-SiO 2 ). The shallow trench isolation region is used to isolate two active regions formed on a silicon-on-insulator (SOI) substrate. By selectively depositing the oxide so that the active areas are not covered with the oxide, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO 2  does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO 2  is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a continuation-in-part of application Ser. No. 11/760,477, filed on Jun. 8, 2007, which is divisional of application Ser. No. 10/732,953, filed Dec. 11, 2003. The disclosure of each application is hereby incorporated by reference herein in its entirety. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates to integrated circuit fabrication and, more particularly, to design structures for shallow trench isolation used in integrated circuits.  
       BACKGROUND OF THE INVENTION  
       [0003]     Using current photolithography practices, a number of semiconductor devices can be formed on the same silicon substrate. One technique for isolating these different devices from one another involves the use of a shallow trench between two devices, or active areas, that is filled with an electrically-insulative material. Known as shallow trench isolation, a trench is formed that extends from a top material layer on a wafer to a buried oxide layer, for example, and the trench is then filled with an electrically-insulative material, such as oxide. In particular, chemical vapor deposition (CVD) is used to cover the entire wafer with the oxide material and then planarized.  
         [0004]     This method of filling the trench with oxide introduces a number of problems. First, the oxide, typically silicon dioxide, must be planarized across the entire wafer to a level that coincides with the top of the trench. Through a planarizing process, such as chemical mechanical polishing (CMP), all the oxide must be completely removed from the active areas without over polishing either the active areas or the trenches. As wafer sizes have increased, uniform polishing over the entire wafer is difficult to accomplish and, as a result, some areas of the wafer have too much of the oxide removed while other areas have too little removed. Especially as wafer sizes have increased to 300 mm, “dishing”, or over polishing of the oxide is a common occurrence.  
         [0005]     Additionally, CVD deposition of oxide results in growth from the bottom and sides of the trench. Thus, three growing fronts exist within the trench as the oxide is being formed. When two growing fronts meet, a seam is formed that behaves differently during wet etching, such as with buffered hydrofluoric acid (BHF) or diluted hydrofluoric acid (DHF). When etched with a wet etching solution, the seams etch at a faster rate than the other portions of silicon dioxide. As a result, trenches, or cavities, are formed in the silicon dioxide along the seams. During later fabrication steps that deposit material on the wafer, these cavities can collect the deposited material resulting in unintended consequences. For example, deposition of polysilicon followed by a polysilicon etch step will result in polysilicon unintentionally remaining in some of the cavities along the seams in the silicon dioxide. Under these circumstances, if two gate conductors cross a common seam, then an electrical short could develop between the conductors.  
         [0006]      FIG. 1  illustrates a silicon-on-insulator (SOI) wafer  100  with shallow trench isolation regions formed using the conventional methods just described. In this figure, a silicon substrate  102  supports a buried oxide layer  104  and a SOI layer  106 . In four active areas  120 ,  122 ,  124 ,  126 , a pad oxide layer  108  and pad nitride layer  110  cover the SOI layer  106 . Three trenches are formed between the active areas  120 ,  122 ,  124 ,  126  and are filled with an electrically-insulative oxide such as silicon dioxide  112 . Because the silicon dioxide  112  is thermally grown using a CVD process, the silicon dioxide  112  in each trench includes seams  114  where growth fronts met when the silicon dioxide  112  was being formed. Furthermore,  FIG. 1  depicts the over and under polishing that occurs when a thick layer of silicon dioxide  112  must be planarized over the entire surface of the wafer  100 . For example, the right-side of the wafer  100  shows that the planarization step removed silicon dioxide  112  from the trench while the left-side of the wafer  100  shows that some silicon dioxide  112  still remains on the pad nitride layer  110 .  
         [0007]     Accordingly, there remains a need within the field of semiconductor fabrication for design structures for shallow trench isolation formed by a technique that minimizes the mechanical polishing needed to planarize the oxide layer and that utilizes an oxide layer that has a uniform etch rate.  
       SUMMARY OF THE INVENTION  
       [0008]     Therefore, embodiments of the present invention involve filling a shallow trench isolation region with liquid phase deposited silicon dioxide (LPD-SiO 2 ) while avoiding covering active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a CVD oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO 2  does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO 2  is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate at the growth seams exceeds that of the other oxide areas.  
         [0009]     One aspect of the present invention relates to a method of forming shallow trench isolation regions. In accordance with this aspect, a plurality of active regions are formed on a silicon substrate and a shallow trench isolation region is formed between two of the active regions. Silicon dioxide is selectively deposited within the shallow trench isolation region and not deposited on the two active regions.  
         [0010]     Another aspect of the present invention relates to a semiconductor substrate on an SOI substrate that includes first and second active regions separated by a shallow trench isolation region. In particular, the shallow trench isolation region is filled with liquid-phase deposited silicon dioxide (LPD-SiO 2 ).  
         [0011]     Yet another aspect of the present invention relates to a semiconductor device forming area on an SOI substrate that includes at least two active areas and a shallow trench isolation region between the two areas. This forming area also includes an electrically-insulative material filling the shallow trench isolation region, the electrically-insulative material comprised substantially of silicon dioxide and having a uniform etch rate when exposed to wet etching solution.  
         [0012]     One additional aspect of the present invention relates to a method of forming shallow trench isolation regions. In accordance with this aspect, a plurality of active regions are formed on a silicon substrate and a shallow trench isolation region is formed between two of the active regions. Silicon dioxide is selectively deposited within the shallow trench isolation region by liquid phase deposition of the silicon dioxide.  
         [0013]     In yet another aspect of the invention, a design structure embodied in a machine readable medium is provided for designing, manufacturing, or testing a design. The design structure includes a first active region containing a semiconductor material, a second active region containing the semiconductor material, and a shallow trench isolation region separating the first and second active regions. The shallow trench isolation region contains liquid-phase deposited silicon dioxide that is free of growth seams.  
         [0014]     The design structure may comprise a netlist, which describes the design. The design structure may reside on storage medium as a data format used for the exchange of layout data of integrated circuits. The design structure may include at least one of test data files, characterization data, verification data, or design specifications. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]      FIG. 1  illustrates a SOI wafer having shallow trench isolation regions formed using conventional fabrication methods.  
         [0016]      FIG. 2  illustrates an initial SOI wafer on which shallow trench isolation regions are formed according to an embodiment of the present invention.  
         [0017]      FIG. 3  illustrates the SOI wafer of  FIG. 2  with a pad nitride layer and an optional pad oxide layer according to an embodiment of the present invention.  
         [0018]      FIG. 4  illustrates the SOI wafer of  FIG. 3  with a plurality of shallow isolation trenches.  
         [0019]      FIG. 5  illustrates the SOI wafer of  FIG. 4  with the plurality of shallow isolation trenches filled with an electrically insulative material in accordance with one embodiment of the present invention.  
         [0020]      FIG. 6  illustrates the SOI wafer of  FIG. 5  once the electrically insulative material within the trenches has been planarized.  
         [0021]      FIG. 7  is a flow diagram of a design process used in semiconductor design, manufacturing, and/or test. 
     
    
     DETAILED DESCRIPTION  
       [0022]      FIG. 2  illustrates a silicon-on-insulator (SOI) wafer that can be formed by a variety of conventional methods, such as SIMOX or wafer bonding and etch back. The wafer  200  includes a silicon or other semiconductor substrate  202 , a buried oxide (BOX) layer  204 , and a silicon on insulator (SOI) layer  206 . To continue the process, and referring to  FIG. 3 , a pad oxide layer  308  and a pad nitride layer  310  are formed over the SOI layer  206 . The pad oxide layer  308  is typically silicon dioxide and is approximately between 2-10 nm in thickness. Some embodiments of the present invention omit the pad oxide layer  308  such as when a buffer between the pad nitride layer  310  and the silicon  206  is not needed. For example, as the thickness of the pad nitride layer  310  is reduced, it causes less damage when formed over the silicon  206 . In some instances, therefore, the pad nitride layer  310  can be formed directly on the silicon  206  without the protection of the pad oxide layer  308 . The pad nitride layer is typically Si 3 N 4  and is approximately between 10-150 nm thick.  
         [0023]     Using standard photolithographic and etching techniques, a photo resist pattern can be formed on the top of the pad nitride layer  310  so as to form shallow isolation trenches down to the BOX layer  204 . As shown in  FIG. 4 , the trenches  402 ,  404 ,  406 , and  408  separate a number of active areas in which separate devices, such as transistors, can be formed. To create the trenches, a photo resist layer (not shown) is patterned on the pad nitride layer  310  and etching of the pad nitride layer  310  and pad oxide layer  308  is performed using the pattern. The photo resist can then be stripped and the resulting pattern of the pad nitride layer  310  is typically used to control the etch area of the SOI layer  206 . As one alternative, the photo resist pattern can be used as the guide for etching all three layers, as well.  
         [0024]     At this point, the sidewalls of the trenches  402 - 408  can be cleaned to reduce or eliminate native oxide along the exposed sidewalls of the SOI layer  208 . This cleaning step can be accomplished by a hydrogen peroxide based cleaning step or other RCA cleaning methods in combination with DHF and/or BHF cleans known to a skilled artisan. After being cleaned, the trenches  402 - 408  are ready to be filled.  FIG. 5  depicts the SOI wafer  300  with its trenches  402 - 408  filled with oxide  502 . In particular the oxide is formed by depositing silicon dioxide by means of Liquid Phase Deposition. This deposition occurs in such a manner that the oxide nucleates on, and grows from, the exposed surface of the BOX layer  204 . Thus, liquid-phase deposited silicon dioxide (LPD-SiO 2 ) differs in physical structure than silicon dioxide deposited via a conventional CVD process.  
         [0025]     The formation of silicon dioxide  502  is localized to the trenches and does not cover the active areas  504 - 512 . Furthermore, the silicon dioxide  502  in each trench is formed without seams caused by the intersection of different growth fronts and, therefore, has a uniform etch rate across its entire surface. As shown in  FIG. 5 , the liquid phase deposited silicon dioxide  502  (LPD-SiO 2 ) overfills the trenches and extends above the pad nitride layer  310  by approximately 10 to 100 nm, although as much as 500 nm is contemplated.  
         [0026]     Generally, LPD-SiO 2  tends to be less dense than thermally grown silicon dioxide, such as that resulting from a CVD process. Accordingly, a high temperature anneal or oxidation, such as at 800-1200° C., can be performed to densify the LPD-SiO 2    502  so that it is more characteristic of thermally grown silicon dioxide. The annealing step can be performed using rapid thermal annealing that lasts for seconds to minutes or a slow furnace annealing that can last for hours. In either case, the ambient atmosphere is preferably inert to slightly oxidizing. This annealing step can be performed before or after the LPD-SiO 2    502  is planarized to the level of the pad nitride layer  310  as shown in  FIG. 6 . Chemical mechanical polishing (CMP) can be used to planarize the LPD-SiO 2    502 . However, only a few areas of oxide  502  (i.e., just the trenches) need to been planarized which reduces the amount of polishing, and the resulting time, needed to planarize the wafer  200 .  
         [0027]     Also, because the CMP of the oxide  502  is reduced, less protection is needed over the active areas as compared to planarizing a CVD deposited oxide layer over an entire wafer as was performed historically. Thus, the thickness of the pad nitride layer  310  can be reduced as compared to conventional methods. Reducing the thickness of the pad nitride layer  310  is beneficial because it reduces the time needed to deposit the layer  310  and remove the layer  310 ; both of which are slow processes. In the past protective pad nitride layers have commonly exceeded 200 nm and more.  
         [0028]     Once the trenches are filled and planarized to define the shallow trench isolation generally indicated by reference numeral  500  and as shown in  FIG. 6 , conventional semiconductor fabrication processes can continue to form a variety of devices within the active areas on the SOI wafer  300 . For example, the pad nitride layer  310 , and possibly the pad oxide layer  308 , would be stripped off and well implantation would occur to form source/drain regions over which a gate could be constructed. Additionally, if the optional pad oxide layer  308  was omitted during fabrication, a sacrificial oxide layer can be grown over the exposed SOI regions before additional manufacturing steps are performed.  
         [0029]      FIG. 7  shows a block diagram of an example design flow  700 . Design flow  700  may vary depending on the type of integrated circuit (IC) being designed. For example, a design flow  700  for building an application specific IC (ASIC) may differ from a design flow  700  for designing a standard component. Design structure  710  is preferably an input to a design process  705  and may come from an IP provider, a core developer, or other design company, or may be generated by the operator of the design flow, or from other sources. Design structure  710  comprises a circuit incorporating the shallow trench isolation  500  in the form of schematics or HDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.). Design structure  710  may be contained on one or more machine readable medium. For example, design structure  710  may be a text file or a graphical representation of the circuit. Design process  705  preferably synthesizes (or translates) the circuit into a netlist  715 , where netlist  715  is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. This may be an iterative process in which netlist  715  is resynthesized one or more times depending on design specifications and parameters for the circuit.  
         [0030]     Design process  705  may include using a variety of inputs; for example, inputs from library elements  720  which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications  725 , characterization data  730 , verification data  735 , design rules  740 , and test data files  745  (which may include test patterns and other testing information). Design process  705  may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. A person having ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process  705  without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow.  
         [0031]     Design process  705  preferably translates an embodiment of the invention as shown in  FIG. 6 , along with any additional integrated circuit design or data (if applicable), into a second design structure  750 . Design structure  750  resides on a storage medium in a data format used for the exchange of layout data of integrated circuits (e.g. information stored in a GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures). Design structure  750  may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the invention as shown in  FIG. 6 . Design structure  750  may then proceed to a stage  755  where, for example, design structure  750 : proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.  
         [0032]     While the invention has been illustrated by a description of various embodiments and while these embodiments have been described in considerable detail, it is not the intention of the applicants to restrict or in any way limit the scope of the appended claims to such detail. Additional advantages and modifications will readily appear to those skilled in the art. Thus, the invention in its broader aspects is therefore not limited to the specific details, representative apparatus and method, and illustrative example shown and described. Accordingly, departures may be made from such details without departing from the spirit or scope of applicants&#39; general inventive concept.