Abstract:
A raw signal is delayed in a delay circuit ( 1 ) and then supplied to one of the input terminals of a selection circuit ( 8 ). The raw signal is also supplied to another delay circuit ( 2 ) to be delayed. Subsequently, data of this delayed signal is processed by spline interpolation in an interpolation circuit ( 4 ), and the interpolation values are supplied to the other of the input terminals of the selection circuit ( 8 ). Further, a timer ( 7 ) is operated according to an output signal from a noise detection circuit ( 6 ) which detects noise in the raw signal. When noise is detected, the selection circuit ( 8 ) switches to select the output from the interpolation circuit ( 4 ), thereby achieving interpolation of noisy sections.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a noise cancel circuit which removes noise using an interpolation technique. 
   2. Description of the Background Art 
   Generally, when a pulse noise generated by a vehicle engine overlaps with the audio band, a car radio receiver will produce an audible noise unpleasant to listeners. To prevent this, radio receivers usually include a noise cancel circuit. Such a noise cancel circuit removes a pulse noise from an audio signal by performing pre-hold processing on the signal during noise generation. A conventional noise cancel circuit is shown in  FIG. 3 . 
   In  FIG. 3 , an input signal including noise is supplied via the input terminal  31  to the delay circuit  32  and HPF  33 . After passing through the HPF  33 , if noise exceeding a certain predetermined level is detected by the noise detection circuit  34 , the noise detection circuit  34  produces an output pulse. The output pulse is applied to the gate generation circuit  35 , which generates a gate signal having a predetermined width. 
   In response to the gate signal, the switch  36  is turned off. As a result, application of a pilot cancel signal to the subtraction circuit  37  is stopped, thereby allowing the output signal from the delay circuit  32  to be supplied to both input terminals of the subtraction circuit  37 . The output AC signal from the delay circuit  32  is canceled by the subtraction circuit, and the DC voltage between the two ends of the capacitor  38  results at the output end of the subtraction circuit  38 . The delay time of the delay circuit  32  equals the time required for the processing from the HPF  33  to the switch  36 . In this way, noise within the input signal is removed. Subsequently, when the gate signal generation is stopped, the switch  36  is turned on, and the pilot cancel signal is applied to the subtraction circuit  37 . The pilot signal component within the input signal is then canceled by the subtraction circuit  37 . 
   However, as the frequency band of noise such as pulse noise is often within the audio frequency band, the noise removal by pre-hold processing removes not only noise, but also sound. While noise removal by pre-hold processing may produce an output that sounds improved to the ear, the pre-hold processing also actually decreases the distortion factor, thereby newly introducing deterioration of sound quality. 
   SUMMARY OF THE INVENTION 
   The object of the present invention is to provide a noise cancel circuit for removing noise, such as pulse noise, from an audio signal while minimizing decrease in the distortion factor. 
   According to the present invention, during pulse noise generation, interpolation is performed on the noise portion of a detected radio signal. As a result, the noise portion is interpolated to a smooth curve, and the distortion factor of the detected radio signal can be improved. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram illustrating an embodiment of the present invention. 
       FIG. 2  is a characteristic diagram for explaining the operation according to the present invention. 
       FIG. 3  is a block diagram showing a conventional example. 
       FIG. 4  is a block diagram illustrating a specific configuration example of the interpolation circuit  4  in  FIG. 1 . 
       FIG. 5  is a flowchart for explaining the operation according to  FIG. 4 . 
       FIG. 6  is a diagram for explaining the timing of pulse removal. 
       FIG. 7  is another diagram for explaining the timing of pulse removal. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1  is a block diagram illustrating a preferred embodiment of the present invention. Numerals  1  and  2  denote delay circuits which are supplied with a signal such as a detected FM signal.  3  is an LPF which passes only a predetermined band within the output signal from delay circuit  2 .  4  is an interpolation circuit for interpolating a data of a time point using data of previous and later time points.  5  denotes an AGC amplifier which detects the magnitude of white noise and performs amplification while suppressing the white noise level.  6  is a noise detection circuit for detecting pulse noise in the output signal from the AGC amplifier  5 .  7  is a timer for counting during a predetermined time period T according to the output signal from the noise detection circuit  6 , and generating an output signal during the counting.  8  denotes a selection circuit for selecting an output signal from either the delay circuit  1  or the interpolation circuit  4  depending on the presence of the output signal from the timer  7 . 
   In a device employing the arrangement of  FIG. 1 , a detected FM signal is supplied to three circuits. In delay circuit  1 , the detected FM signal is delayed by delay time τ 1  and supplied to one of the input terminals of the selection circuit  8 . In delay circuit  2 , the detected FM signal is delayed by delay time τ 2  and supplied to the LPF  3 . When the detected FM signal is an FM composite signal, for example, the LPF  3  blocks the sub-signal and the pilot signal by reducing their levels, and allowing only the main signal to be passed. The output signal from the LPF  3  is applied to the interpolation circuit  4  for interpolation processing. By applying only the main signal to the interpolation circuit  4 , erroneous processing due to sub-signals and pilot signals is prevented. The interpolation circuit  4  may be configured using a DSP or a logic circuit as shown in  FIG. 4 , and may comprise an A/D converter  41  for converting the output from the LPF  3  into digital data, an arithmetic unit  42  for performing interpolation processing on the output data from the A/D converter  41 , a D/A converter  43  for converting the output from the arithmetic unit  42  into an analog signal, and a memory  44  for storing audio data. For the interpolation processing, spline interpolation, especially Lagrange interpolation, is performed. The interpolation circuit  4  constantly performs the interpolation processing to produce an analog interpolation signal which is supplied to the other of the input terminals of the selection circuit  8 . 
   Further, the detected FM signal is applied to the AGC amplifier  5 . When the white noise level is high, the AGC amplifier amplifies the detected FM signal while reducing the gain such that the white noise level becomes suppressed. The output signal from the AGC amplifier is supplied to the noise detection circuit  6 . The noise detection circuit  6  extracts and detects the pulse noise components. The detection output signal from the noise detection circuit  6  is applied to the timer  7 . The counting operation of the timer  7  is started in response to the input of the detection signal. The timer  7  counts during a predetermined time period T, and generates an output signal during the counting. In response to this output signal, the selection circuit  8  selects the output signal from the interpolation circuit  4  as shown in  FIG. 1 . 
   In the arrangement of  FIG. 1 , when no pulse noise component is detected within the input audio signal, the noise detection circuit  6  generates no output signal. As a result, the selection circuit  8  indicates a state opposite from that shown in  FIG. 1 , and the audio signal output from delay circuit  1  is transmitted, via the selection circuit  8 , to the circuitry of the next stage. When pulse noise components are generated, the selection circuit  8  selects the output signal from the interpolation circuit  4 , allowing a signal subjected to interpolation processing in its noise portions to be transmitted to the circuitry of the next stage. 
   Each of the raw input signal line, the interpolation circuit line, and the noise detection line require different processing time periods. Accordingly, noise cannot be appropriately removed if the processes in those lines are performed without delaying the signals. Delay circuits  1  and  2  are therefore provided to make timing adjustments such that appropriate noise removal can be accomplished. 
   An example case is described below in which a pulse noise is generated at time t 0  as shown in  FIG. 6 . The noise detection circuit  6  detects the pulse noise by detecting a change in the input signal level. The noise detection circuit  6  usually conducts pulse noise detection based on the state of change in the data obtained after performing A/D conversion, thus requiring time for such processing. Because the time point of pulse noise detection is always later than that of the noise generation, and also because performing processing for detection requires a certain amount of time, the time point that the noise detection output signal is generated from the actual noise detection circuit  6  is t 1 . Delay time τ 1  of delay circuit  1  may be designated to correspond to the period of time between time point t 1  of the output signal generation from the noise detection circuit  6  and time point t 0  of the pulse generation. With this arrangement, the selection circuit  8  can be switched at a timing matching the pulse generation. In the interpolation circuit  4 , processing time is similarly required because D/A conversion and interpolation processing are executed. Assuming that the time required for interpolation processing is τa, delay time τ 2  of delay circuit  2  may be designated as follows: τ 2 =τ 1 −τa (τ 1 =τ 2 +τa). According to this arrangement, an interpolation output corresponding to the noise generation time point t 1  is supplied from the interpolation circuit  4  via the selection circuit  8  at the timing when the selection circuit  8  is switched. In this way, the timing of the interpolation output is also matched. It should be noted that, in  FIG. 6 , the timing is illustrated diagrammatically without accurately reflecting the actual scale of the timing. The count time T of the timer  7  is generally set at the pulse width of the pulse noise. Accordingly, the interpolation output from the interpolation circuit  4  is supplied from the selection circuit  8  during a time period corresponding to the generation of the pulse. 
   Delay time τ 2  is further explained with reference to  FIG. 7 . In  FIG. 7 , the processing times of the noise detection circuit  6  and the interpolation circuit  4  are assumed to be 0. Furthermore, the signal forward direction in  FIG. 7  is the opposite from  FIG. 6 . 
   The noise detection circuit  6  detects a pulse noise at the peak of the noise. If delay circuit  2  is not provided in the interpolation line including the interpolation circuit  4 , the latter, not the former, half of the pulse noise can be removed when the selection circuit  8  is switched at the timing of the peak. By inserting delay circuit  2 , all pulse noise can be removed. It is to be noted that, in comparison with the detection processing time of the noise detection circuit  6 , the interpolation processing time of the interpolation circuit  4  is longer. Accordingly, when taking into account the processing times of both of the circuits, delay time τ 2  of delay circuit  2  may be designated shorter than the time period indicated in  FIG. 7  by the time period difference between the interpolation processing time and the detection processing time. 
   The operation of the interpolation circuit  4  is next described referring to  FIG. 4 . The output data from the A/D converter circuit  41  is transmitted to the arithmetic unit  42  and sequentially stored in the memory  44 . The data read out from the memory  44  is used to calculate interpolation data by spline or Lagrange interpolation. The output interpolation data is converted into an analog data by the D/A converter circuit  44  and supplied to the selection circuit  8  in  FIG. 1 . 
   The processing of the arithmetic unit  42  is explained using the flowchart of  FIG. 5 . With respect to the data to be interpolated, data for three points from previous and later time points, respectively, are read out (S 1 ). Subsequently, interpolation data is calculated using a Lagrange interpolation technique. For example, when point X in  FIG. 2  is to be interpolated, data of previous and later time points, data x 0  to data x 5 , and their function values f 0  to f 5 , are read out according to S 1 . The read out data are substituted in the following equation: 
                   P   ⁡     (   x   )       =         ∑   n       k   =   0       ⁢         L   k     ⁡     (   x   )       ⁢     f   k                 (   1   )               
L k (X) is the Lagrange interpolation coefficient, which can be expressed as
 
   
     
       
         
           
             
               
                 
                   
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   Using the example of  FIG. 2 , the function value f(x) to be interpolated is given by
 
 P ( x )= L (0) f 0 +L (1) f 1 +L (2) f 2 +L (3) f 3 +L (4) f 4 +L (5) f 5  (3)
 
and can be calculated by substituting the read out data. In this case, the Lagrange interpolation coefficient is
 
                   Lk   ⁡     (   x   )       =         (     x   -     x   ⁢           ⁢   0       )     ⁢     (     x   -     x   ⁢           ⁢   1       )     ⁢     (     x   -     x   ⁢           ⁢   2       )     ⁢     (     x   -     x   ⁢           ⁢   3       )     ⁢     (     x   -     x   ⁢           ⁢   4       )     ⁢     (     x   -     x   ⁢           ⁢   5       )           (     xk   -     x   ⁢           ⁢   0       )     ⁢     (     xk   -     x   ⁢           ⁢   1       )     ⁢     (     xk   -     x   ⁢           ⁢   2       )     ⁢     (     xk   -     x   ⁢           ⁢   3       )     ⁢     (     xk   -     x   ⁢           ⁢   4       )     ⁢     (     xk   -     x   ⁢           ⁢   5       )                 (   4   )               
According to this Lagrange interpolation, a smooth curve passing through all given points, points x 0  to x 5  in  FIG. 2 , can be obtained. By performing interpolation using this technique, the noise portion of the raw signal can be interpolated into a smooth curve, allowing improvement of the distortion factor.
 
   The calculated value is output from the arithmetic unit  42  (S 3 ), and then the next interpolation data, namely, the interpolation data which corresponds to f 3  in  FIG. 2 , is calculated. The arithmetic unit sequentially calculates interpolation data based on the data stored in the memory  44 . 
   Although Lagrange interpolation is used in the interpolation circuit  4  of the present embodiment to calculate the interpolation value, other interpolation techniques may be used for the calculation of the present invention. Furthermore, a plurality of interpolation techniques may be employed in combination such that the optimal interpolation technique can be selected to calculate the interpolation value according to the condition of noise generation. 
   According to the present invention, noise portions can be smoothly interpolated by spline interpolation. Sound components are therefore prevented from being deleted by noise removal, allowing further improvement of the distortion factor and sound quality.