Abstract:
A semiconductor package including a package body which is uniquely configured to partially expose the semiconductor die of the package. The partial exposure of the semiconductor die enhances heat dissipation from the die. Additionally, the reduced amount of encapsulant material used in the fabrication of the semiconductor package attributable to only the partial encapsulation of the semiconductor die facilitates a reduction in the overall manufacturing cost related to the semiconductor package, and further allows one or more additional semiconductor packages to be stacked upon the package while still maintaining an overall profile of reduced thickness in the resultant stack.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     Not Applicable 
     STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT 
     Not Applicable 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to integrated circuit chip package technology and, more particularly, to a semiconductor package including a package body which is uniquely configured to partially expose the semiconductor die of the package for enhancing heat dissipation from the die, and to allow for the stacking of one or more additional semiconductor packages upon the package while still maintaining an overall profile of reduced thickness in the resultant stack. 
     2. Description of the Related Art 
     Semiconductor dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and an underlying substrate such as a printed circuit board (PCB) or motherboard. The elements of such a package include a metal leadframe, an integrated circuit or semiconductor die, bonding material to attach the semiconductor die to the leadframe, bond wires which electrically connect pads on the semiconductor die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the semiconductor package commonly referred to as the package body. 
     The leadframe is the central supporting structure of such a package, and is typically fabricated by chemically etching or mechanically stamping a metal strip. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant or package body. Portions of the leads of the leadframe extend externally from the package body or are partially exposed therein for use in electrically connecting the package to another component. In certain semiconductor packages, a portion of the die attach pad or die pad of the leadframe also remains exposed within the package body. In other semiconductor packages, the metal leadframe is substituted with a laminate substrate to which the semiconductor die is mounted and which includes pads or terminals for mimicking the functionality of the leads and establishing electrical communication with another device. 
     As indicated above, both the semiconductor die and the bond wires used to electrically connect the semiconductor die to the leadframe or substrate of the semiconductor package are covered by the package body thereof. Typically, the encapsulant material used to form the package body is molded such that the completed package body is substantially thicker than the roof height of the conductive wires. The package body is also molded to be relatively thick at the central area of the top surface of the semiconductor die. Typically, the pads or terminals of the semiconductor die to which the conductive wires are electrically connected are located along the peripheral edge of the semiconductor die, and not within the central area thereof. Due to the aforementioned manner in which the package body is typically formed, the thickness of the semiconductor package is increased as a whole. Moreover, as the thickness of the package body is increased, heat generated from the semiconductor die is predominantly discharged to ambient air through the leadframe or substrate, rather than through the package body. As a result, the entire heat release performance of the semiconductor package is typically poor. Further, because the encapsulant material used to form the package body is molded thick on the central area of the top surface of the semiconductor die, the quantity of the encapsulant included in the semiconductor package is increased, which in turn gives rise to an increase in the overall cost thereof. 
     Once the semiconductor dies have been produced and encapsulated in the semiconductor packages described above, they may be used in a wide variety of electronic devices. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically includes a printed circuit board on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic devices are typically manufactured in reduced sizes and at reduced costs, which results in increased consumer demand. Accordingly, not only are semiconductor dies highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density. 
     Even though semiconductor packages have been miniaturized, space on a printed circuit board remains limited and precious. Thus, there is a need to find a semiconductor package design to maximize the number of semiconductor packages that may be integrated into an electronic device, yet minimize the space needed to accommodate these semiconductor packages. One method to minimize space needed to accommodate the semiconductor packages is to stack the semiconductor packages on top of each other, or to stack individual semiconductor device or other devices within the package body of the semiconductor package. 
     With regard to stacked semiconductor packages, the term PoP (package on package) is often used to describe the arrangement wherein two semiconductor packages are vertically stacked and electrically interconnected through the use of solder balls. Within the PoP arrangement, it is possible to implement various structures, such as analogue plus digital memory, logic plus flash memory, application process plus combo memory, image processor plus memory, audio/graphic processor plus memory, etc. Accordingly, it is possible not only to make a logic device with high density, but also to obtain a memory with high capacity. However, because the individual semiconductor packages in a PoP arrangement each typically include a relatively thickly molded package body, a problem that arises is that the entire thickness of the PoP is increased. With such increase in the thickness of the PoP, it is difficult to miniaturize an electronic device in which such PoP is to be integrated. Moreover, since semiconductor packages are typically stacked in the same direction, if the thickness of the package body is excessive, the number and pitch of solder balls which can be formed on one semiconductor package to facilitate the electrical interconnection of the semiconductor packages within the PoP to each other is seriously limited. That is, assuming that an upper semiconductor package is stacked on a lower semiconductor package, the number and pitch of solder balls formed on the leadframe or substrate of the upper semiconductor package is limited by the package body formed on the lower semiconductor package. As a result, it is typically not possible to form solder balls at a given area of the upper semiconductor package corresponding to the package body of the lower semiconductor package. Therefore, the number and pitch of solder balls for electrically interconnecting the upper semiconductor package and the lower semiconductor package to each other is limited, thus rendering difficulties in designing PoP&#39;s. 
     The present invention addresses and overcomes these problems by providing a semiconductor package including a package body which is uniquely configured to partially expose the semiconductor die of the package for enhancing heat dissipation from the die, and to allow for the stacking of one or more additional semiconductor packages upon the package while still maintaining an overall profile of reduced thickness in the resultant stack. These, as well as other features and attributes of the present invention will be discussed in more detail below. 
     BRIEF SUMMARY OF THE INVENTION 
     I accordance with one aspect of the present invention, there is provided a semiconductor package including a package body which is uniquely configured to partially expose the semiconductor die of the package. The partial exposure of the semiconductor die enhances heat dissipation from the die. Additionally, the reduced amount of encapsulant material used in the fabrication of the semiconductor package attributable to only the partial encapsulation of the semiconductor die facilitates a reduction in the overall manufacturing cost related to the semiconductor package. 
     In accordance with another aspect of the present invention, there is provided a semiconductor package stack wherein at least one of the semiconductor packages of the stack includes a semiconductor package as described above having a package body which is configured to partially expose the semiconductor die of the package. The uniquely formed package body of such semiconductor package, in addition to partially exposing the semiconductor die for enhancing heat dissipation therefrom, allows for one or more additional semiconductor packages to be stacked upon the package while still maintaining an overall profile of reduced thickness in the resultant stack. 
     The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These, as well as other features of the present invention, will become more apparent upon reference to the drawings wherein: 
         FIG. 1A  is a cross-sectional view of a semiconductor package constructed in accordance with a first embodiment of the present invention; 
         FIG. 1B  is a cross-sectional view of a variant of the semiconductor package shown in  FIG. 1A ; 
         FIG. 2A  is a cross-sectional view of a chip stack assembled to include one of semiconductor packages shown in  FIG. 1A ; 
         FIG. 2B  is a cross-sectional view of a variant of the chip stack shown in  FIG. 2A  and assembled to include one of semiconductor packages shown in  FIG. 1B ; 
         FIG. 3A  is a cross-sectional view of a semiconductor package constructed in accordance with a second embodiment of the present invention; 
         FIG. 3B  is a cross-sectional view of a variant of the semiconductor package shown in  FIG. 3A ; 
         FIG. 4A  is a cross-sectional view of a chip stack assembled to include one of semiconductor packages shown in  FIG. 3A ; 
         FIG. 4B  is a cross-sectional view of a variant of the chip stack shown in  FIG. 4A  and assembled to include one of semiconductor packages shown in  FIG. 3B ; 
         FIGS. 5A-5C  depict an exemplary sequence of steps which may be used to facilitate the fabrication of the semiconductor package shown in  FIG. 1A ; 
         FIGS. 6A-6C  depict an exemplary sequence of steps which may be used to facilitate the fabrication of the semiconductor package shown in  FIG. 1B ; 
         FIGS. 7A-7C  depict an exemplary sequence of steps which may be used to facilitate the fabrication of the semiconductor package shown in  FIG. 1B  as an alternative to the steps shown in  FIGS. 6A-6C ; 
         FIG. 8  is an exploded view of the chip stack shown in  FIG. 2A ; 
         FIG. 9  is an exploded view of the chip stack shown in  FIG. 2B ; 
         FIG. 10  is an exploded view of the chip stack shown in  FIG. 4A ; and 
         FIG. 11  is an exploded view of the chip stack shown in  FIG. 4B . 
     
    
    
     Common reference numerals are used throughout the drawings and detailed description to indicate like elements. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to the drawings wherein the showings are for purposes of illustrating various embodiments of the present invention only, and not for purposes of limiting the same,  FIG. 1A  depicts a semiconductor package  101  constructed in accordance with a first embodiment of the present invention. The semiconductor package  101  comprises a substrate  110 . The substrate  110  itself comprises a substantially flat insulation layer  111  which defines a generally planar top surface and an opposed, generally planar bottom surface. The insulation layer  111  typically has a generally quadrangular configuration defining four (4) peripheral edge segments or side surfaces. The insulation layer  111  may be formed of epoxy resin, polyimide resin, BT (bismaleimide triazine) resin, FR4 (glass fiber reinforced resin), FR5, ceramic, silicon, glass, or an equivalent thereof. However, those of ordinary skill in the art will recognize that the present invention is not limited to any particular material for the insulation layer  111 . 
     Disposed on the top surface of the insulation layer  111  is a conductive circuit pattern  112  which may comprise pads, traces, or combinations thereof. Similarly, formed on the bottom surface of the insulation layer  111  is a plurality of conductive contacts  113 . In the substrate  110 , the contacts  113  are electrically connected to the circuit pattern  112  by conductive vias  114  which extend through the insulation layer  111 . It is contemplated that the circuit pattern  112 , contacts  113  and vias  114  may be formed of copper, gold, silver, nickel, iron, aluminum or an alloy thereof. However, those of ordinary skill in the art will recognize that the present invention is also not limited by any particular material used to form the circuit pattern  112 , contacts  113  and vias  114 . 
     In the substrate  110 , portions of the top surface of the insulation layer  111  and the circuit pattern  112  formed thereon are each covered by a solder mask  115 . Similarly, the bottom surface of the insulation layer  111  and a portion of each of the contacts  113  formed thereon are each covered by a solder mask  116 . The solder masks  115 ,  116  are shown in  FIG. 1A , and in  FIGS. 5A-5C  which depict an exemplary sequence of steps which may be used to facilitate the fabrication of the semiconductor package  101 . Those of ordinary skill in the art will recognize that the substrate  110  may be formed so as not to include the solder masks  115 ,  116 . Additionally, though the substrate  110  may be a substantially rigid or flexible printed circuit board, those of ordinary skill in the art will recognize that the substrate  110  may also comprise a conventional leadframe rather than a circuit board. 
     In addition to the substrate  110 , the semiconductor package  101  comprises a semiconductor die  120  which is preferably bonded to the top surface of the insulation layer  111  through the use of a layer  124  of a suitable adhesive. The semiconductor die  120  defines a generally planar top surface  121  which is opposite the generally planar bottom surface thereof which is affixed to the insulation layer  111  via the layer  124  of adhesive. In addition to the top surface  121 , the semiconductor die  120  defines a plurality of generally planar side surface  122  which extend generally perpendicularly between the top surface  121  and the bottom surface thereof. Typically, the semiconductor die  120  has a generally quadrangular configuration. Disposed on the top surface  121  in relative close proximity to the side surfaces  122  are a plurality of bond pads or terminals  123  of the semiconductor die  120 . In the semiconductor die  120 , the terminals  123  are arranged in pair of spaced, generally parallel rows which extend along respective ones of an opposed pair of the side surfaces  122 . However, those of ordinary skill in the art will recognize that the semiconductor die  120  may be provided with terminals  121  which are arranged so as to extend along each of the side surfaces  122  thereof. 
     In the semiconductor package  101 , the terminals  123  are electrically connected to the circuit pattern  112  of the substrate  110  through the use of conductive wires  130 . Such wires  130  may be formed from gold wire, aluminum wire, copper wire or an equivalent thereof. However, those of ordinary skill in the art will recognize that the present invention is not limited to any particular material for the conductive wires  130 . Additionally, as shown in  FIG. 1A , if the solder mask  115  is included in the substrate  110 , the wires  130  will typically be extended to portions of the circuit pattern  112  which are not covered by the solder mask  115 , and are disposed in relative close proximity to the side surfaces  122  of the semiconductor die  120 . Though not shown, it is contemplated that conventional solder bumps or gold bumps may be used instead of the wires  130  to facilitate the electrical connection of the semiconductor die  120  to the circuit pattern  112  of the substrate  110 . 
     In the semiconductor package  101 , the wires  130 , a peripheral portion of the top surface  121  of the semiconductor die  120 , at least two side surfaces  122  of the semiconductor die  120 , a portion of the top surface of the insulation layer  111 , and that portion of the circuit pattern  112  to which the wires  130  are extended are each covered by an encapsulant material which, upon hardening, forms two (2) separate and identically configured package body sections  140  of the semiconductor package  101 . The semiconductor package  101  includes the two separate package body sections  140  as a result of the terminals  123  of the semiconductor die  120  being arranged on the top surface  121  in a pair of spaced, generally parallel rows as indicated above. Each package body section  140  includes a generally planar, beveled first surface  141  which extends to the top surface  121  of the semiconductor  120 , a generally planar second surface  142  which extends in spaced, generally parallel relation to the top surface  121 , and a generally planar, beveled third surface  143  which extends from the second surface  142  to the top surface of the insulation layer  111 . As seen in  FIG. 1A , the solder mask  115 , if included in the substrate  110 , extends to the third surface  143  of each package body section  140 . The top surface  121  of the semiconductor die  120  and the package body sections  140  (and in particular the first surfaces  141  thereof) collectively define a recess  144  which is of a predetermined depth. The use of the recess  144  will be described in more detail below. 
     As further seen in  FIG. 1A , the package body sections  140  are formed such that the central area of the top surface  121  of the semiconductor die  120  is not covered thereby. Additionally, if only two separate package body sections  140  are included in the semiconductor package  101 , the entirety or at least portions of the opposed pair of the side surfaces  122  of the semiconductor die  120  not having the terminal  123  extending therealong may also be exposed. In this regard, only peripheral portions of the top surface  121  extending along the opposed pair of the side surfaces  122  having the terminals  123  extending therealong is covered by the package body sections  140 . Due to the exposure of a substantial portion of the top surface  121  of the semiconductor die  120  within the recess  144 , the heat release performance of the semiconductor die  120  within the semiconductor package  101  is substantially increased. Additionally, the semiconductor package  101  may be fabricated using a reduced amount of the encapsulant material which ultimately hardens into the package body sections  140 , thus reducing its cost. Though not shown, it is contemplated that a small amount of the encapsulant used to form the package body sections  140  may flow out to the central area of the top surface  121  of the semiconductor die  120  during the encapsulation process, so that a very thin layer of encapsulant may be formed and ultimately cover the top surface  121 . Those of ordinary skill in the art will recognize that the separate package body sections  140  may be substituted by a single, unitary package body having a continuous, ring-like configuration in the event that the semiconductor die  120  is provided with terminals  123  which extend along each of the side surfaces  122 . If such a unitary package body is included in the semiconductor package  101 , it is contemplated that the cross-sectional configuration of such package body will mirror the cross-sectional configuration of each of the package body sections  140  as shown in  FIG. 1A . It is further contemplated that such unitary package body will also define the above-described recess  144 . 
     The semiconductor package  101  further comprises a plurality of solder balls  150  which are preferably deposited onto respective ones of the contacts  113  formed on the bottom surface of the insulation layer  111 . As will be recognized by those of ordinary skill in the art, the solder balls  150  are used to facilitate the mounting and electrical connection of the semiconductor package  101  to a printed circuit board of an electronic device. The solder balls  150  may be formed from eutectic SnPb, Pb free solder, or an equivalent thereof. Additionally, though in  FIG. 1A  the solder balls  150  are depicted as being formed at only certain areas on the bottom surface of the substrate  110 , those of ordinary skill in the art will recognize that the solder balls  150  may be evenly distributed over the entire area of the bottom surface of the substrate  110 . 
     As indicated above,  FIGS. 5A-5C  depict an exemplary sequence of steps which may be used to facilitate the fabrication of the semiconductor package  101 . In the substrate seating step shown in  FIG. 5A , the substrate  110  having the semiconductor die  120  electrically connected thereto through the use of the wires  130  is seated in a mold  500 . The mold  500  includes one or more cavities  501  which are formed to spatially and positionally correspond to the wires  130  used to interconnect the semiconductor die  120  to the substrate  110 . The mold  500  also includes a truncated portion  502  which is formed to positionally correspond to the central area of the top surface  121  of the semiconductor die  120 . Also formed within the mold  500  are apertures  503  for injecting the encapsulant material which ultimately hardens into the package body sections  140  into respective ones of the cavities  501 . 
     In the encapsulation step shown in  FIG. 5B , a suitable encapsulant material at high temperature and high pressure is injected through the holes  503  of the mold  500  so as to fill respective ones of the cavities  501 . As is seen in  FIG. 5B , when the injection of the encapsulant material into the mold cavities  501  occurs, the truncated projection  502  of the mold  500  is seated against the central area of the top surface  121  of the semiconductor die  120 , with lower peripheral surfaces of the mold  500  being seated against the solder mask  115  of the substrate  110  which is disposed on the top surface of the insulation layer  111  thereof in the above-described manner. The injection of the encapsulant material into the cavities  501  causes the wire bonded areas on the semiconductor die  120  (i.e., the terminals  123  having the wires  130  connected thereto) to be covered and thus sealed by the encapsulant material. Also covered by the encapsulant material are peripheral portions of the top surface  121  surrounding the terminals  123 , those opposed side surfaces  122  of the semiconductor die  120  along which the terminals  123  extend as indicated above, and the wires  130 . The encapsulant material also covers portions of the top surface of the insulation layer  111  which are not covered by the solder mask  115 , and those portions of the circuit pattern  112  to which the wires  130  extend and are electrically connected. Because the projection  502  is in close contact with the central area of the top surface  121  of the semiconductor die  120 , no encapsulant material is applied to such central area of the top surface  121 . However, if the contact force between the projection  502  and the central area of the top surface  121  is not particularly high, a small amount of the encapsulant material may be caused to flow over the central area of the top surface  121 . As a result, a thin layer of the encapsulant material may be formed over the central area of the top surface  121  as also explained above. 
     Upon the removal of the fully formed package body sections  140  from within the mold  500 , the exposed central area of the top surface  121  of the semiconductor die  120  and the package body sections  140  collectively define the recess  144  which is of predetermined volume as indicated above. Thereafter, in a solder ball reflow step as shown in  FIG. 5C , volatile flux is dotted onto those portions of the contacts  113  not covered by the solder mask  116  applied to the bottom surface of the insulation layer  111  in the substrate  110 . Thereafter, a plurality of solder balls  150  are temporarily bonded to respective ones of the contacts  113 . If the substrate  110  with the temporarily bonded solder balls  150  is thereafter put into and taken out of a suitable furnace, the solder balls  150  melt and solidify, thereby being rigidly fixed to the contacts  113 . The flux is volatized and completely removed. The solder ball reflow step is preferably performed in a state in which the substrate  110  is inverted. The semiconductor package  101  completely fabricated in the above-described manner can be electrically connected to various types of electronic appliances through the use of the solder balls  150 . 
     Referring now to  FIG. 1B , there is shown a semiconductor package  102  which comprises a relatively minor variant of the semiconductor package  101  shown in  FIG. 1A . In this regard, only the distinctions between the semiconductor packages  101 ,  102  will be described below. In the semiconductor package  102 , a protective layer  125  of predetermined thickness is formed on the exposed central area of the top surface  121  of the semiconductor die  120 . Such protective layer  125  may be formed from a polymer, glassivation or an equivalent thereto. In addition, the protective layer  125  may be formed from any material which attaches well to the semiconductor die  120  and encapsulant  140 . Furthermore, the protective layer  125  may be formed from a thermal conductor so as to further improve the heat release performance of the semiconductor die  120 . Such a thermal conductor may not only be fabricated from a conventional metallic material, but also from a non-metallic material. Moreover, it is contemplated that the protective layer  125  may extend to the first surfaces  141  of the package body sections  140 , or may be spaced inwardly from such first surfaces  141 . 
     Referring now to  FIGS. 6A-6C , there is shown an exemplary sequence of steps which may be used to facilitate the fabrication of the semiconductor package  102  shown in  FIG. 1B . The fabrication methodology for the semiconductor package  102  shown in  FIGS. 6A-6C  is identical to that shown and described above in relation to  FIGS. 5A-5C , with the sole distinction being that the projection  502  of the mold  500  comes into close contact with the protective layer  125  applied to the central area of the top surface  121  of the semiconductor die  120  in the fabrication process related to the semiconductor package  102 , as opposed to being directly engaged to the top surface  121 . Advantageously, the engagement of the projection  502  to the protective layer  125  as opposed to the top surface  121  itself assists in protecting the semiconductor die  120  from damage attributable to the engagement of the mold  500  thereto. The protective layer  125  such as the polymer may be attached or dispensed to the first surface  121  of the semiconductor die  120  by shape of the adhesive tape or a liquid adhesive before the encapsulation. Moreover, the protective layer  125  such as the glassivation may be formed to the first surface  121  of the semiconductor die  120  by using chemical vapor deposition. Namely, silicon or nitride may be deposited to the first surface  121  of the semiconductor die  120 . 
     Referring now to  FIGS. 7A-7C , there is shown an exemplary sequence of steps which may be used to facilitate the fabrication of the semiconductor package  102  shown in  FIG. 1B  as an alternative to the fabrication methodology shown in  FIGS. 6A-6C  discussed above. The fabrication methodology shown in  FIGS. 7A-7C  is virtually identical to that shown in  FIGS. 6A-6C , with the sole distinction lying in the above-described one piece type mold  500  being replaced with separate mold sections  600   a ,  600   b . As will be recognized by those of ordinary skill in the art, the mold section  600   a ,  600   b , when cooperatively engaged to the substrate  110  and to the semiconductor die  120  in the proper manner, facilitate the formation of respective ones of the package body sections  140  of the semiconductor package  102 . The primary advantage attendant to the use of the separate mold sections  600   a ,  600   b  as an alternative to the above-described mold  500  is that the use of the separate mold section  600   a ,  600   b  rarely causes the possibility of poor molding such as mold flash and incomplete molding as compared with a one piece type mold. 
     As seen in  FIG. 7B , when the separate mold sections  600   a ,  600   b  are used in lieu of the above-described mold  500 , a lower peripheral surface of each of the mold sections  600   a ,  600   b  is seated against the protective layer  125  disposed on the top surface  121  of the semiconductor die  120 . Those of ordinary skill in the art will recognize that the use of the mold sections  600   a ,  600   b  as an alternative to the mold  500  is also applicable to the fabrication of the semiconductor package  101  shown in  FIG. 1A . If used to facilitate the fabrication of the semiconductor package  101 , it will further be appreciated that a lower peripheral surface of each of the mold sections  600   a ,  600   b  will be firmly seated directly against the top surface  121  of the semiconductor die  120  since no protective layer  125  is included on the top surface  121  in the semiconductor package  101 . Further, though two mold sections  600   a ,  600   b  are shown in  FIGS. 7A-7C , those of ordinary skill in the art will recognize that more than two mold sections may be used to facilitate the fabrication of a semiconductor package wherein the semiconductor die  120  of such semiconductor package includes terminals  123  which extend along more than two of the side surfaces  122  defined thereby. 
     Referring now to  FIG. 2A , there is shown a semiconductor package stack  10  which is assembled to include the semiconductor package  101  shown and described above in relation to  FIG. 1A . An exploded view of the stack  10  is shown in  FIG. 8 . The stack  10  shown in  FIGS. 2A and 8  includes three (3) vertically stacked semiconductor packages  101 ,  201 ,  301 . Of these, the semiconductor package  101  constitutes the lowermost semiconductor package in the stack  10 . Stacked upon the semiconductor package  101  is a semiconductor package  201 . The semiconductor package  201  includes a substrate  210  having a construction which is virtually identical to that of the substrate  110  of the semiconductor package  101 . In this regard, the  200  series reference numerals included in  FIGS. 2A and 8  correspond to respective ones of the  100  series reference numerals included in  FIGS. 1A ,  2 A and  8 . In the semiconductor package  201 , attached to the top surface of the substrate  210  is a semiconductor die  220 , the terminals of which are electrically connected to portions of the circuit pattern  212  not covered by the solder mask  215  through the use of conductive wires  230 . An adhesive layer  224  is used to attach the semiconductor die  220  to the substrate  210 , and in particular to the top surface of the insulation layer  211  thereof. The semiconductor die  220 , wires  230 , a portion of the top surface of the insulation layer  211 , and those portions of the circuit pattern  212  not covered by the solder mask  215  are each covered by a package body  240  of the semiconductor package  201  which is formed from a hardened encapsulant material. Importantly, the package body  240  has a configuration which is complementary to that of the recess  144  of the semiconductor package  101  for reasons which will be discussed in more detail below. 
     In the stack  10 , solder balls  250  which may be preformed on prescribed portions of the circuit pattern  212  of the semiconductor package  201  are used to electrically connect the circuit pattern  212  of the semiconductor package  201  to the circuit pattern  112  of the semiconductor package  101  in the manner shown in  FIGS. 2A and 8 . In this regard, it is contemplated that if the semiconductor package  101  is to be integrated into the stack  10 , the solder mask  115  may be altered slightly from the form shown in  FIG. 1A  to that shown in  FIG. 8  such that prescribed peripheral portions of the circuit pattern  112  are not covered by the solder mask  115  and thus remain exposed so as to more easily facilitate the interface of the solder balls  250  thereto. The solder balls  250  are sized such that when the semiconductor package  201  is electrically connected to the semiconductor package  101  through the use thereof, the package body  240  of the semiconductor package  201  is nested within the recess  144  of the semiconductor package  101  in the manner shown in  FIG. 2A . In the stack  10 , it is preferable that a slight gap or space be defined between the package body  240  and the top surface  121  of the semiconductor die  120  and package body sections  140  of the semiconductor package  101  for the purpose of defining an airflow passage between the stacked semiconductor packages  101 ,  201 , thereby improving the heat release performance thereof. However, it is contemplated that the package body  240  may directly engage the top surface  121  of the semiconductor die  120 . Advantageously, the receipt of the package body  240  of the semiconductor package  201  into the complimentary recess  144  of the underlying semiconductor package  101  reduces the overall thickness of the stack semiconductor packages  101 ,  201 . In this regard, the stack thickness of the semiconductor packages  101 ,  201  is reduced by the depth of the recess  144  defined by the semiconductor package  101 . As will be recognized, the solder balls  250  used to electrically connect the semiconductor packages  101 ,  201  to each other in the stack  10  are sized as necessary to achieve the desired gap or clearance between the package body  240  and the top surface  121  of the semiconductor die  120 . 
     As indicated above, also included in the stack  10  is the semiconductor package  301  which is vertically stacked upon the semiconductor package  201 . The semiconductor package  301  includes a substrate  310  which is also substantially identical in construction to the above-described substrate  110 . In this regard, the  300  series reference numerals included in  FIGS. 2A and 8  also correspond to respective ones of the  100  series reference numerals included in  FIGS. 1A ,  2 A and  8 . In the semiconductor package  301 , attached to the top surface of the insulation layer  311  of the substrate  310  through the use of a first layer  324   a  of an adhesive is a first semiconductor die  320   a . Attached to the top surface of the first semiconductor die  320   a  via a second layer  324   b  of a suitable adhesive is a second semiconductor die  320   b . The terminals of the lower first semiconductor die  320   a  are electrically connected to exposed portions of the circuit pattern  312  not covered by the solder mask  315  through the use of conductive wires  330   a . Similarly, the terminals of the upper semiconductor die  320   b  stacked upon the lower semiconductor die  320   a  are electrically connected to exposed portions of the circuit pattern  312  not covered by the solder mask  315  through the use of conductive wires  330   b . In the semiconductor package  301 , the first and second semiconductor dies  320   a ,  320   b , the conductive wires  330   a ,  330   b , those portions of the circuit pattern  312  not covered by the solder mask  315 , and an exposed portion of the top surface of the insulation layer  311  of the substrate  310  are each covered by a package body  340 . The package body  340  is sized so as to extend in substantially flush relation to each of the peripheral edges or side surfaces defined by the insulation layer  311  of the substrate  310 , as shown in  FIGS. 2A and 8 . 
     In the stack  10 , solder balls  350  are used to electrically connect the contacts  313  of the semiconductor package  301  to the contacts  213  of the underlying semiconductor package  201 . In this regard, it is contemplated that the semiconductor package  301  will be fabricated to include the solder balls  350  which are formed on those portions of respective ones of the contacts  313  which are exposed in the solder mask  316 . The solder balls  350  are then mated and electrically connected to those portions of respective ones of the contacts  213  which are exposed in the solder mask  216  of the semiconductor package  201  in the manner shown in  FIG. 2A . Since the semiconductor package  201  is inverted when electrically connected to the semiconductor package  101 , a full array of the contacts  213  may be formed on the bottom surface of the insulation layer  211  of the substrate  210 , the contacts  213  thus covering almost the entirety of the bottom surface of the insulation layer  211 . Accordingly, the contacts  313  may likewise be formed on the bottom surface of the insulation layer  311  of the substrate  310  as a full array in the semiconductor package  301 , thus also covering virtually the entirety of the bottom surface of the insulation layer  311  of the substrate  310 . As a result, in the stack  10 , a greater number of electrical connection areas may be created between the stacked semiconductor packages  201 ,  301 , thus resulting in greater ease in the design and implementation of desired logic functions. Those of ordinary skill in the art will recognize that the semiconductor package  301  as shown in  FIGS. 2A and 8  is merely an example, the present invention not being limited to the form of the semiconductor package  301  as described above. In this regard, the semiconductor package  301  may be a conventional semiconductor package which includes only a single semiconductor die, and not the stacked first and second semiconductor dies  320   a ,  320   b  described above. Along these lines, the structural attributes of the semiconductor package  201  described above is also exemplary only, the present invention not being limited to the above-described form for the semiconductor package  201 . 
     Referring now to  FIG. 2B , there is shown a semiconductor package stack  20  which comprises a relatively minor variant of the semiconductor package stack  10  shown in  FIG. 2A .  FIG. 9  provides an exploded view of the stack  20  shown in  FIG. 2B . The only distinction between the stacks  10 ,  20  is that the semiconductor package  101  in the stack  10  is substituted with the semiconductor package  102  shown in  FIG. 1B  in the stack  20 . Thus, in the stack  20 , when the semiconductor package  201  is vertically stacked upon and electrically connected to the underlying semiconductor package  102 , the package body  240  of the semiconductor package  201  will typically directly engage the protective layer  125  disposed on the top surface  121  of the semiconductor die  120  in the underlying semiconductor package  102  in the manner shown in  FIG. 2B . 
     Referring now to  FIG. 3A , there is depicted a semiconductor package  401  constructed in accordance with a second embodiment of the present invention. The semiconductor package  401  comprises a substrate  410 . The substrate  410  itself comprises a substantially flat insulation layer  411  which defines a generally planar top surface and an opposed, generally planar bottom surface. The insulation layer  411  typically has a generally quadrangular configuration defining four (4) peripheral edge segments or side surfaces. The insulation layer  411  may be formed of epoxy resin, polyimide resin, BT (bismaleimide triazine) resin, FR4 (glass fiber reinforced resin), FR5, ceramic, silicon, glass, or an equivalent thereof. However, those of ordinary skill in the art will recognize that the present invention is not limited to any particular material for the insulation layer  411 . 
     Disposed on the top surface of the insulation layer  411  is a conductive circuit pattern  412  which may comprise pads, traces, or combinations thereof. Similarly, formed on the bottom surface of the insulation layer  411  is a plurality of conductive contacts  413 . In the substrate  410 , the contacts  413  are electrically connected to the circuit pattern  412  by conductive vias  414  which extend through the insulation layer  411 . It is contemplated that the circuit pattern  412 , contacts  413  and vias  414  may be formed of copper, gold, silver, nickel, iron, aluminum or an alloy thereof. However, those of ordinary skill in the art will recognize that the present invention is also not limited by any particular material used to form the circuit pattern  412 , contacts  413  and vias  414 . 
     In the substrate  410  as shown in  FIG. 3A , portions of the top surface of the insulation layer  411  and the circuit pattern  412  formed thereon are each covered by a solder mask  415 . Similarly, the bottom surface of the insulation layer  411  and a portion of each of the contacts  413  formed thereon are each covered by a solder mask  416 . Those of ordinary skill in the art will recognize that the substrate  410  may be formed so as not to include the solder masks  415 ,  416 . Disposed in the approximate center of the insulation layer  411  of the substrate  410  is an opening  417  which may have a quadrangular configuration and extends between the top and bottom surfaces of the insulation layer  411 . The use of the opening  417  will be discussed in detail below. Though the substrate  410  may be a substantially rigid or flexible printed circuit board, those of ordinary skill in the art will recognize that the substrate  410  may also comprise a conventional leadframe rather than a circuit board. 
     In addition to the substrate  410 , the semiconductor package  401  comprises a semiconductor die  420  which is disposed within the opening  417  of the substrate  410  in the manner shown in  FIG. 3A . The semiconductor die  420  defines a generally planar top surface  421  which extends in generally parallel relation to the top surface of the insulation layer  411  when the semiconductor die  420  is properly positioned within the opening  417 . The semiconductor die also defines a generally planar bottom surface  426  which is disposed in opposed relation to the top surface  421  and extends in generally parallel relation to the solder mask  416  applied to the bottom surface of the insulation layer  411  when the semiconductor die  420  is properly positioned within the opening  417 . In addition to the top and bottom surfaces  421 ,  426 , the semiconductor die  420  defines a plurality of generally planar side surface  422  which extend generally perpendicularly between the top surface  421  and the bottom surface  426  thereof. Typically, the semiconductor die  420  also has a generally quadrangular configuration. Disposed on the top surface  421  in relative close proximity to the side surfaces  422  are a plurality of bond pads or terminals  423  of the semiconductor die  420 . In the semiconductor die  420 , the terminals  423  are arranged in pair of spaced, generally parallel rows which extend along respective ones of an opposed pair of the side surfaces  422 . However, those of ordinary skill in the art will recognize that the semiconductor die  420  may be provided with terminals  421  which are arranged so as to extend along each of the side surfaces  422  thereof. 
     In the semiconductor package  401 , the terminals  423  are electrically connected to the circuit pattern  412  of the substrate  410  through the use of conductive wires  430 . Such wires  430  may be formed from gold wire, aluminum wire, copper wire or an equivalent thereof. However, those of ordinary skill in the art will recognize that the present invention is not limited to any particular material for the conductive wires  430 . Additionally, as shown in  FIG. 3A , if the solder mask  415  is included in the substrate  410 , the wires  430  will typically be extended to portions of the circuit pattern  412  which are not covered by the solder mask  415 , and are disposed in relative close proximity to the side surfaces  422  of the semiconductor die  420 . 
     In the semiconductor package  401 , the wires  430 , a peripheral portion of the top surface  421  of the semiconductor die  420 , at least two (and preferably all) of the side surfaces  422  of the semiconductor die  120 , a portion of the top surface of the insulation layer  411 , and that portion of the circuit pattern  412  to which the wires  430  are extended are each covered by an encapsulant material which, upon hardening, forms two (2) identically configured package body sections  440  of the semiconductor package  401 . The semiconductor package  401  includes the two package body sections  440  as a result of the terminals  423  of the semiconductor die  420  being arranged on the top surface  421  in a pair of spaced, generally parallel rows as indicated above. Each package body section  440  includes a generally planar, beveled first surface  441  which extends to the top surface  421  of the semiconductor  420 , a generally planar second surface  442  which extends in spaced, generally parallel relation to the top surface  421 , and a generally planar, beveled third surface  443  which extends from the second surface  442  to the top surface of the insulation layer  411 . As seen in  FIG. 3A , the solder mask  415 , if included in the substrate  410 , extends to the third surface  443  of each package body section  440 . The top surface  421  of the semiconductor die  420  and the package body sections  440  (and in particular the first surfaces  441  thereof) collectively define a recess  444  which is of a predetermined depth. The use of the recess  444  will be described in more detail below. 
     As further seen in  FIG. 3A , the package body sections  440  are formed such that the central area of the top surface  421  of the semiconductor die  420  is not covered thereby. Additionally, if only two package body sections  440  are included in the semiconductor package  401 , only peripheral portions of the top surface  421  extending along the opposed pair of the side surfaces  422  having the terminals  423  extending therealong may be covered by the package body sections  440 . Due to the exposure of a substantial portion of the top surface  421  of the semiconductor die  420  within the recess  444 , the heat release performance of the semiconductor die  420  within the semiconductor package  401  is substantially increased. Additionally, the semiconductor package  401  may be fabricated using a reduced amount of the encapsulant material which ultimately hardens into the package body sections  440 , thus reducing its cost. Though not shown, it is contemplated that a small amount of the encapsulant used to form the package body sections  440  may flow out to the central area of the top surface  421  of the semiconductor die  420  during the encapsulation process, so that a very thin layer of encapsulant may be formed and ultimately cover the top surface  421 . Those of ordinary skill in the art will recognize that the package body sections  440  may be substituted by a single, unitary package body having a continuous, ring-like configuration in the event that the semiconductor die  420  is provided with terminals  423  which extend along each of the side surfaces  422 . If such a unitary package body is included in the semiconductor package  401 , it is contemplated that the cross-sectional configuration of such package body will mirror the cross-sectional configuration of each of the package body sections  440  as shown in  FIG. 3A . It is further contemplated that such unitary package body will also define the above-described recess  444 . 
     The semiconductor package  401  further comprises a plurality of solder balls  450  which are preferably deposited onto respective ones of the contacts  413  formed on the bottom surface of the insulation layer  411 . As will be recognized by those of ordinary skill in the art, the solder balls  450  are used to facilitate the mounting and electrical connection of the semiconductor package  401  to a printed circuit board of an electronic device. The solder balls  450  may be formed from eutectic SnPb, Pb free solder, or an equivalent thereof. Though not shown, it is contemplated that a sequence of steps mirroring those as shown and described above in relation to  FIGS. 5A-5C  may be used to facilitate the fabrication of the semiconductor package  401 . 
     Referring now to  FIG. 3B , there is shown a semiconductor package  402  which comprises a relatively minor variant of the semiconductor package  401  shown in  FIG. 3A . In this regard, only the distinctions between the semiconductor packages  401 ,  402  will be described below. In the semiconductor package  402 , a protective layer  425  of predetermined thickness is formed on the exposed central area of the top surface  421  of the semiconductor die  420 . Such protective layer  425  may be formed from a polymer or an equivalent thereto. Furthermore, the protective layer  425  may be formed from a thermal conductor so as to further improve the heat release performance of the semiconductor die  420 . Such a thermal conductor may not only be fabricated from a conventional metallic material, but also from a non-metallic material. Moreover, it is contemplated that the protective layer  425  may extend to the first surfaces  441  of the package body sections  440 , or may be spaced inwardly from such first surfaces  441 . Though not shown, it is contemplated that a sequence of steps mirroring those as shown and described above in relation to  FIGS. 6A-6C  and  7 A- 7 C may be used to facilitate the fabrication of the semiconductor package  402 . The sequence of steps shown in  FIGS. 7A-7C  may also be used to facilitate the fabrication of the semiconductor package  401 . 
     Referring now to  FIG. 4A , there is shown a semiconductor package stack  30  which comprises a relatively minor variant of the semiconductor package stack  10  shown in  FIG. 2A .  FIG. 10  provides an exploded view of the stack  30  shown in  FIG. 4A . The only distinction between the stacks  10 ,  30  is that the semiconductor package  101  in the stack  10  is substituted with the semiconductor package  401  shown in  FIG. 3A  in the stack  30 . 
     Referring now to  FIG. 4B , there is shown a semiconductor package stack  40  which comprises a relatively minor variant of the semiconductor package stack  30  shown in  FIG. 4A .  FIG. 11  provides an exploded view of the stack  40  shown in  FIG. 4B . The only distinction between the stacks  30 ,  40  is that the semiconductor package  401  in the stack  30  is substituted with the semiconductor package  402  shown in  FIG. 3B  in the stack  40 . Thus, in the stack  40 , when the semiconductor package  201  is vertically stacked upon and electrically connected to the underlying semiconductor package  402 , the package body  240  of the semiconductor package  201  will typically directly engage the protective layer  425  disposed on the top surface  421  of the semiconductor die  420  in the underlying semiconductor package  402  in the manner shown in  FIG. 4B . 
     This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process may be implemented by one of skill in the art in view of this disclosure.