Abstract:
A non-quadrangular display panel includes a plurality of first signal lines disposed in a non-quadrangular display area, wherein the non-quadrangular display area includes a plurality of pixels. A switching circuit is disposed in a peripheral area of the non-quadrangular display panel. The peripheral area is disposed adjacent to the non-quadrangular display area. The switching circuit passes a signal to at least one of the plurality of first signal lines. A plurality of second signal lines is disposed in the peripheral area. At least two adjacent second signal lines are uniformly spaced apart from each other and transmit signals at different times to the switching circuit. A plurality of third signal lines is disposed in the peripheral area orthogonal to the plurality of second signal lines and connected to the switching circuit.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2015-0065448, filed on May 11, 2015, in the Korean Intellectual 
         [0002]    Property Office, the disclosure of which is incorporated by reference herein in its entirety. 
       TECHNICAL FIELD 
       [0003]    Exemplary embodiments of the present invention relate to a non-quadrangular display panel. 
       DISCUSSION OF THE RELATED ART 
       [0004]    A plurality of pixels and signal lines are formed on a display panel configuring a display. Conventionally, a plurality of signal lines include a scan line extending in a first direction and a data line extending in a second direction that is perpendicular to the first direction. 
         [0005]    A demultiplexer may be formed on one side of a non-display area provided near a display area. The demultiplexer uses a clock signal and a signal applied by a driver integrated circuit (IC) connected to a display panel to apply a data signal to a data line. 
         [0006]    The driver IC is connected to the demultiplexer through data fanout wires disposed on the display panel. A clock signal wire for transmitting the clock signal and the fanout wires are disposed in a peripheral area of the display area. The fanout wires formed near the demultiplexer extend in parallel in a first direction and the clock signal wires extend in parallel in a second direction, so the fanout wires and the clock signal wires overlap each other. 
         [0007]    Resistance and capacitance are generated by the overlapping of the wires. In the case of a quadrangular display panel, the fanout wires and the clock signal wires overlap each other substantially orthogonally so areas of the overlapped regions are substantially the same. Therefore, resistance and capacitance formed by the overlapped regions are substantially the same. 
         [0008]    In the case of a display panel having an arbitrary shape, the areas or forms in which the clock signal wires and the fanout wires overlap are not predetermined. Accordingly, resistance and capacitance formed by the overlapped regions are different from each other. 
       SUMMARY 
       [0009]    According to an exemplary embodiment of the present invention, a non-quadrangular display panel includes a plurality of first signal lines disposed in a non-quadrangular display area. The non-quadrangular display area includes a plurality of pixels. A switching circuit is disposed in a peripheral area of the non-quadrangular display panel. The peripheral area is disposed adjacent to the non-quadrangular display area. The switching circuit passes a signal to at least one of the plurality of first signal lines. A plurality of second signal lines is disposed in the peripheral area. At least two adjacent second signal lines are uniformly spaced apart from each other. The plurality of second signal lines transmit signals at different times to the switching circuit. A plurality of third signal lines is disposed in the peripheral area orthogonal to the plurality of second signal lines and connected to the switching circuit. 
         [0010]    In an exemplary embodiment of the present invention, the non-quadrangular display area is circular. 
         [0011]    In an exemplary embodiment of the present invention, the plurality of first signal lines and the plurality of third signal lines are disposed on a first layer. 
         [0012]    In an exemplary embodiment of the present invention, the plurality of second signal lines are disposed on a second layer. 
         [0013]    In an exemplary embodiment of the present invention, an insulating layer is disposed between the first and second layers. 
         [0014]    In an exemplary embodiment of the present invention, the non-quadrangular display panel further includes a driver integrated circuit (IC) connected to the plurality of third signal lines, and generating the signal passed to the at least one of the plurality of first signal lines. 
         [0015]    In an exemplary embodiment of the present invention, the switching circuit includes a switching element including input terminals connected to the plurality of third signal lines, output terminals connected to the plurality of first signal lines, and gate terminals connected to the plurality of second signal lines. 
         [0016]    In an exemplary embodiment of the present invention, a first area of a first region in which a second signal line of the plurality of second signal lines overlaps with a third signal line of the plurality of third signal lines is substantially equal to a second area of a second region in which the second signal line of the plurality of second signal lines overlaps with another third signal line of the plurality of third signal lines. 
         [0017]    In an exemplary embodiment of the present invention, imaginary lines extending from the plurality of third signal lines meet at a point in the non-quadrangular display area. 
         [0018]    According to an exemplary embodiment of the present invention, non-quadrangular display panel includes a plurality of first signal lines disposed in a non-quadrangular display area. A plurality of second signal lines are curved and disposed in a peripheral area. The peripheral area is disposed adjacent to the non-quadrangular display area. At least two adjacent second signal lines of the plurality of second signal lines are uniformly spaced apart from each other. A plurality of third signal lines is disposed in the peripheral area. Each third signal line of the plurality of third signal lines crosses at least one second signal line of the plurality of second signal lines at a perpendicular angle. The plurality of first signal lines, the plurality of second signal lines, and the plurality of third signal lines are connected to a switching circuit. The switching circuit passes a signal from one of the plurality of third signal lines to a first pixel through a first signal line of plurality of first signal lines. 
         [0019]    In an exemplary embodiment of the present invention, the plurality of second signal lines are circular. 
         [0020]    In an exemplary embodiment of the present invention, the plurality of second signal lines are oval. 
         [0021]    In an exemplary embodiment of the present invention, the plurality of second signal lines include a concave portion and a convex portion. 
         [0022]    In an exemplary embodiment of the present invention, the plurality of first signal lines and the plurality of third signal lines are disposed on a first layer. 
         [0023]    In an exemplary embodiment of the present invention, the plurality of second signal lines are disposed on a second layer. 
         [0024]    In an exemplary embodiment of the present invention, an insulating layer is disposed between the first and second layers. 
         [0025]    In an exemplary embodiment of the present invention, the non-quadrangular display panel further includes a driver IC connected to the plurality of third signal lines, wherein the driver IC generates the signal passed to the first pixel. 
         [0026]    In an exemplary embodiment of the present invention, the switching circuit includes a first switching element. The first switching element includes input terminals connected to the plurality of third signal lines, output terminals connected to the plurality of first signal lines, and gate terminals connected to the plurality of second signal lines. 
         [0027]    In an exemplary embodiment of the present invention, a first overlap area between one of the third signal lines and one of the second signal lines is substantially equal to a second overlap area between another third signal line and the one of the second signal lines. 
         [0028]    According to an exemplary embodiment of the present invention, a non-quadrangular display panel includes a plurality of first signal lines disposed in a non-quadrangular display area. The peripheral area is disposed adjacent to the non-quadrangular display area. At least two adjacent second signal lines of the plurality of second signal lines are uniformly spaced apart from each other. A plurality of third signal lines is disposed in the peripheral area and crosses the plurality of second signal lines substantially orthogonally. The plurality of first signal lines, the plurality of second signal lines, and the plurality of third signal lines are connected to a switching circuit. The switching circuit passes a signal from one of the plurality of third signal lines to a first pixel through a first signal line of plurality of first signal lines. Imaginary lines extending from the plurality of third signal lines meet at a point in the non-quadrangular display area. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0029]      FIG. 1  shows a non-quadrangular display panel, according to an exemplary embodiment of the present invention. 
           [0030]      FIG. 2  shows part of a configuration of a non-quadrangular display panel, according to an exemplary embodiment of the present invention. 
           [0031]      FIG. 3  shows clock signal wires and a fanout wire of a non-quadrangular display panel, according to an exemplary embodiment of the present invention. 
           [0032]      FIG. 4  shows part of a configuration of a non-quadrangular display panel, according to an exemplary embodiment of the present invention. 
           [0033]      FIG. 5  shows clock signal wires and a fanout wire of a non-quadrangular display panel, according to an exemplary embodiment of the present invention. 
           [0034]      FIG. 6  shows clock signal wires and a fanout wire of a non-quadrangular display panel, according to an exemplary embodiment of the present invention. 
           [0035]      FIG. 7  shows part of a configuration of a non-quadrangular display panel, according to an exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0036]    Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present disclosure, the same or similar components may be be denoted by the same or similar reference numerals. The accompanying drawings are provided to illustrate exemplary embodiments of the present invention and are not to be interpreted as limiting the spirit and scope of the present invention thereto. It is to be understood that the present invention includes all modifications, equivalents, and substitutions that can be made to the disclosed exemplary embodiments without departing from the spirit and scope of the present invention. 
         [0037]    It is to be understood that when one component is referred to as being “connected” or “coupled” to another component, it may be directly connected or coupled to the other component or intervening components may be connected therebetween. 
         [0038]    Singular forms may include plural forms unless the context clearly indicates otherwise. 
         [0039]      FIG. 1  shows a non-quadrangular display panel, according to an exemplary embodiment of the present invention. As shown in  FIG. 1 , a plurality of first signal lines D 1  to Dm, a plurality of second signal lines S 1  to Sn, and a plurality of pixels PX disposed in a region in which the first signal lines D 1  to Dm cross the second signal lines S 1  to Sn, are disposed on a non-quadrangular display panel  20 . 
         [0040]    A driver integrated circuit (IC)  10  for generating signals on corresponding signal lines disposed on the non-quadrangular display panel  20  may be disposed on a side of the non-quadrangular display panel  20 . The driver IC  10  generates a plurality of scan signals that are supplied to the second signal lines S 1  to Sn, and generates a plurality of data signals that are supplied to the first signal lines D 1  to Dm. The second signal lines S 1  to Sn and the first signal lines D 1  to Dm are connected to the pixels PX disposed in a non-quadrangular display area  30 . 
         [0041]    The non-quadrangular display panel  20  may have a predetermined shape that is not quadrangular (e.g., a circle, an oval, a polygon, a polygon having a part which is curved, or a polygon other than a quadrangle). In an exemplary embodiment of the present invention, the non-quadrangular display panel  20  has a shape having a curved portion (e.g., a portion of the perimeter of the non-quadrangular display panel  20  is curved). 
         [0042]    The non-quadrangular display panel  20  may be flexible. The non-quadrangular display panel  20  may also be curved, or may have an outer perimeter that is partially curved. 
         [0043]    With reference to  FIG. 2 , the driver IC  10  outputs a driving signal to a demultiplexer  40  (e.g., a switching circuit). The demultiplexer  40  passes the driving signal to the pixels PX through the first signal lines D 1  to Dm and the second signal lines S 1  to Sn disposed on the non-quadrangular display panel  20 . 
         [0044]    The plurality of first signal lines D 1  to Dm extend along an y-axis direction, are arranged in an x-axis direction, and are connected to the driver IC  10 . The plurality of second signal lines S 1  to Sn extend along the x-axis direction, are arranged in the y-axis direction, and are connected to the driver IC  10 . 
         [0045]    The plurality of pixels PX are connected to corresponding first signal lines, from among the plurality of first signal lines D 1  to Dm, and corresponding second signal lines, from among the plurality of second signal lines S 1  to Sn. For example, the pixels PX indicated with a plurality of dotted line boxes exemplarily show regions in which the pixels PX may be disposed. However, the present inventive concept is not limited thereto. The plurality of pixels PX may be disposed in various forms in a display area  30  of the non-quadrangular display panel  20 . 
         [0046]    An additional signal line and the demultiplexer  40  for applying a signal to the first signal lines D 1  to Dm will now be described with reference to  FIG. 2 . 
         [0047]      FIG. 2  shows part of a configuration of a non-quadrangular display panel, according to an exemplary embodiment of the present invention. The non-quadrangular display panel  20  includes the display area  30 , and a peripheral area bordering the display area  30 . In an exemplary embodiment of the present invention, the peripheral area of the non-quadrangular display panel  20  surrounds the display area  30 . As shown, clock signal wires CL 1  and CL 2  and power supply wires DCL 1  and DCL 2  are disposed in the peripheral area of the non-quadrangular display panel  20 , around the display area  30 . In an exemplary embodiment of the present invention, the clock signal wires CL 1  and CL 2  may be disposed in the peripheral area, around the display area  30 , and at a distance from the display area  30 , and the power supply wires DCL 1  and DCL 2  may be disposed around the clock signal wires CL 1  and CL 2  at a distance from the clock signal wires CL 1  and CL 2 . The clock signal wires CL 1  and CL 2  are disposed in concentric circles at a distance from the display area  30 . In an exemplary embodiment of the present invention, when a shape of the display area  30  is not circular but it is curved, elliptical, oval, and the like, the clock signal wires CL 1  and CL 2  may be equally distant from each other and their shape may be similar to the shape of the display area  30 . For example, in an exemplary embodiment of the present invention, when the display area  30  of the non-quadrangular display panel  20  includes a convex portion and a concave portion, the clock signal wires CL 1  and CL 2  may be shaped to conform to the curvature of the concave and convex portion of the display area  30 , the clock signal wires CL 1  and CL 2  may be disposed at a substantially constant distance away from each other, and the clock signal wires CL 1  and CL 2  may be disposed at a predetermined distance from the display area  30 . In other words, the shape of the clock signal wires CL 1  and CL 2  depends on the shape of the display area  30 . 
         [0048]    The clock signal wires include the first clock signal wire CL 1  for applying a first clock signal enabled at a first time and the second clock signal wire CL 2  for applying a second clock signal enabled at a second time that is different from the first time. The clock signal wires may further include an n-th signal wire for applying an n-th clock signal enabled at a predetermined time that is different from the first time and the second time. 
         [0049]    The power supply wires may include a first power supply wire DCL 1  for applying a first power source voltage and a second power supply wire DCL 2  for applying a second power source voltage. The first power supply wire DCL 1  and the second power supply wire DCL 2  may supply a power source voltage to the pixels PX. 
         [0050]    The plurality of first signal lines D 1  to Dm are connected to the demultiplexer  40 . The demultiplexer  40  includes a first terminal connected to the first signal lines D 1  to Dm, a second terminal connected to the driver IC  10 , and switching elements including gates connected to the clock signal wires CL 1  and CL 2 . The switching elements may be turned on by the clock signal supplied to the clock signal wires CL 1  and CL 2  to pass the signals supplied by the driver IC  10  to the first signal lines D 1  to Dm. 
         [0051]    The driver IC  10  is disposed in the peripheral area. The driver IC  10  is connected to the demultiplexer  40  through fanout wires FL 1  to FLq. The driver IC  10  may be mounted in the peripheral area of the display panel  20  as a chip-on-glass (COG) type. The fanout wires FL 1  to FLq may be connected to the driver IC  10  through a pad. The driver IC  10  may include a data driver for supplying a data signal. 
         [0052]    The fanout wires FL 1  to FLq and the first signal lines D 1  to Dm may be disposed on a first layer. The clock signal wires CL 1  and CL 2  may be disposed on a second layer that is different from the first layer. The first layer may be disposed on the second layer and an insulating layer may be provided between the first layer and the second layer. Alternately, the second layer may be disposed on the first layer and an insulating layer may be provided between the first layer and the second layer. 
         [0053]    The fanout wires FL 1  to FLq are disposed in an inverse trapezoidal form near the driver IC  10 . The fanout wires FL 1  to FLq, disposed in an inverse trapezoidal form, extend in the y-axis direction and are connected to the demultiplexer  40  and to the driver IC  10 . The fanout wires FL 1  to FLq extending in the y-axis direction and the clock signal wires CL 1  and CL 2  are disposed on different layers and overlap each other. 
         [0054]    In an exemplary embodiment of the present invention, the clock signal wires CL 1  and CL 2  may be disposed along the circumference of the non-quadrangular display area  30 . In an exemplary embodiment of the present invention, with reference to  FIG. 2 , the clock signal wires CL 1  and CL 2  are circularly disposed in the peripheral area, at a distance from display area  30 . The fanout wires FL 1  to FLq extend in the y-axis direction and are arranged in the x-axis direction. The fanout wires FL 1  to FLq overlap the clock signal wires CL 1  and CL 2  in different regions of the peripheral area. 
         [0055]    For example, fanout wires FLk−1 to FLk+1 overlap the clock signal wires CL 1  and CL 2  in a center region of the peripheral area, which is different from an external region CA 1  of the peripheral area in which the fanout wires FLq−3 to FLq overlap the clock signal wires CL 1  and CL 2 . 
         [0056]    The overlapping of the fanout wires FLq−3 to FLq of the external region CA 1  and the clock signal wires CL 1  and CL 2  will now be described with reference to  FIG. 3 . 
         [0057]      FIG. 3  shows clock signal wires CLk 1  to CLk 6  and a fanout wire FLq of the non-quadrangular display panel  20 , according to an exemplary embodiment of the present invention. The clock signal wires CLk 1  to CLk 6  are disposed to be inclined with a predetermined angle with respect to the y axis in the external region CA 1  because the clock signal wires CLk 1  to CLk 6  are disposed in the peripheral area depending on the shape of the display area  30 . It will be described in  FIG. 3  that the clock signal wires CL 1  and CL 2  include first to sixth clock signal wires CLk 1  to CLk 6 . Also, clock signal wire connecting lines CCL 1  and CCL 2  include clock signal wire connecting lines CCL 11 , CCL 13 , CCL 21 , and CCL 22 . 
         [0058]    The first to sixth clock signal wires CLk 1  to CLk 6  are connected to the clock signal wire connecting lines CCL 11 , CCL 13 , CCL 21 , and CCL 22  through contact holes for applying clock signals to the demultiplexer  40 . The clock signal wire connecting lines CCL 11 , CCL 13 , CCL 21 , and CCL 22  extend in the y-axis direction and are connected to the demultiplexer  40 . 
         [0059]    The fanout wire FLq extends in the y-axis direction. The fanout wire FLq overlaps at least one of the first to sixth clock signal wires CLk 1  to CLk 6 . A shape of a region OA 1  in which the first clock signal wire CLk 1  overlaps the fanout wire FLq may include a parallelogram. 
         [0060]    As shown in  FIG. 2 , the region in which the fanout wires FLk−1 to FLk+1 of the center region overlap the clock signal wires CL 1  and CL 2  includes a substantially rectangular shape. However, as shown in  FIGS. 2 and 3 , the region OA 1  in which the fanout wires FLq−3 to FLq of the external region CA 1  overlap the clock signal wires CL 1  and CL 2  is disposed to be a parallelogram. 
         [0061]    A width of the fanout wires FLk−1 to FLk+1 of the center region corresponds to a width of the fanout wires FLq−3 to FLq of the external region CAL Further, a width of the clock signal wires CL 1  and CL 2  of the center region corresponds to a width of the clock signal wires CL 1  and CL 2  of the external region CAL Therefore, the area of the region OA 1  overlapping in a parallelogram shape is greater than the area of the region overlapping in a rectangular shape. 
         [0062]    Accordingly, a resistance and capacitance generated by overlapping one fanout wire, for example, the fanout wire FLk, and the clock signal wires CL 1  and CL 2  in the center region is generally less than a resistance and capacitance generated by overlapping one fanout wire, for example, the fanout wire FLq, and the clock signal wires CL 1  and CL 2  in the external region CA 1 . 
         [0063]    Loads of the fanout wires FL 1  to FLq connected to the demultiplexer  40  have different values depending on the region of the peripheral area in which they cross the clock signal wires CL 1  and CL 2 . The driver IC  10  transmits a signal of the same intensity to the fanout wires FL 1  to FLq but the intensity of the signal transmitted to the pixels PX is varied depending on the region of the peripheral area in which the fanout wires FL 1  to FLq cross the clock signal wires CL 1  and CL 2 . 
         [0064]    A non-quadrangular display will now be described with reference to  FIGS. 4 to 7 , according to exemplary embodiments of the present invention. 
         [0065]      FIG. 4  shows part of a configuration of a non-quadrangular display panel, according to an exemplary embodiment of the present invention. 
         [0066]    As shown in  FIG. 4 , the fanout wires FL 1  to FLq of the non-quadrangular display panel  20 , according to an exemplary embodiment of the present invention, are disposed with a slope (e.g., angle) corresponding to an alignment of the clock signal wires CL 1  and CL 2 . The fanout wires FLk−1 to FLk+1 of a center region CA 3  of the peripheral area, and the fanout wires FLq−3 to FLq of an external region CA 2  of the peripheral area, may be disposed and inclined to be orthogonal to the clock signal wires CL 1  and CL 2 . 
         [0067]    Therefore, the fanout wires FLk−1 to FLk+1 of the center region CA 3  and the fanout wires FLq−3 to FLq of the external region CA 2  may be orthogonal to the clock signal wires CL 1  and CL 2  and overlap the clock signal wires CL 1  and CL 2 . The overlapping between the fanout wires FLk−1 to FLk+1 of the center region CA 3  with the clock signal wires CL 1  and CL 2  and the overlapping of the fanout wires FLq−3 to FLq of the external region CA 2  with the clock signal wires CL 1  and CL 2  will be described with reference to  FIGS. 5 and 6 . 
         [0068]      FIG. 5  shows the first to sixth clock signal wires CLk 1  to CLk 6  and the fanout wire FLq of the non-quadrangular display panel  20 , according to an exemplary embodiment of the present invention.  FIG. 6  shows the first to sixth clock signal wires CLk 1  to CLk 6  and the fanout wire FLk of the non-quadrangular display panel  20 , according to an exemplary embodiment of the present invention. 
         [0069]    As shown in  FIG. 5 , the first to sixth clock signal wires CLk 1  to CLk 6  are disposed to be inclined with a predetermined angle with respect to the y axis in the external region CA 2 . In  FIG. 5 , the clock signal wires CL 1  and CL 2  will be described to include first to sixth clock signal wires CLk 1  to CLk 6 . 
         [0070]    The first to sixth clock signal wires CLk 1  to CLk 6  are connected to the clock signal wire connecting lines CCL 11 , CCL 13 , CCL 21 , and CCL 22  for applying clock signals to the demultiplexer  40  through contact holes. The clock signal wire connecting lines CCL 11 , CCL 13 , CCL 21 , and CCL 22  extend to be orthogonal to the first to sixth clock signal wires CLk 1  to CLk 6  and are connected to the demultiplexer  40 . 
         [0071]    The fanout wire FLq extends to be orthogonal to the first to sixth clock signal wires CLk 1  to CLk 6 . The fanout wire FLq overlaps at least one of the first to sixth clock signal wires CLk 1  to CLk 6 . A shape of the region OA 2  in which the first clock signal wire CLk 1  overlaps the fanout wire FLq is a rectangle or substantially rectangular. However, the shape of any region at which the fanout line FLq are overlapped with any of the first to sixth clock signal wires CLk 1  to CLk 6  is substantially rectangular. The fanout wire FLq was chosen as an exemplary line to illustrate the present inventive concept. However, the present invention is not limited thereto. For example, a region at which any of the fanout lines FLq−3 to FLq of the external region CA 2  are overlapped with any of the first to sixth clock signal wires CLk 1  to CLk 6  is substantially rectangular. 
         [0072]    As shown in  FIG. 6 , the first to sixth clock signal wires CLk 1  to CLk 6  are disposed to extend in the x-axis direction in the center region CA 3 . The first to sixth clock signal wires CLk 1  to CLk 6  are connected to the clock signal wire connecting lines CCL 11 , CCL 13 , CCL 21 , and CCL 22  through contact holes for applying clock signals to the demultiplexer  40 . The clock signal wire connecting lines CCL 11 , CCL 13 , CCL 21 , and CCL 22  extend in the y-axis direction that is orthogonal to the first to sixth clock signal wires CLk 1  to CLk 6  and are connected to the demultiplexer  40 . 
         [0073]    The fanout wire FLk extends in the y-axis direction that is orthogonal to the first to sixth clock signal wires CLk 1  to CLk 6 . A shape of the region OA 3  in which the first clock signal wire CLk 1  overlaps the fanout wire FLk is a rectangle or substantially rectangular. However, the shape of any region at which the fanout line FLk are overlapped with any of the first to sixth clock signal wires CLk 1  to CLk 6  is substantially rectangular. The fanout wire FLk was chosen as an exemplary line to illustrate the present inventive concept. However, the present invention is not limited thereto. For example, a region at which any of the fanout lines FLk−1 to FLk+1 of the center region CA 3  are overlapped with any of the first to sixth clock signal wires CLk 1  to CLk 6  is substantially rectangular. 
         [0074]    The regions formed by the overlapping of the fanout wires FLq−3 to FLq with the first to sixth clock signal wires CLk 1  to CLk 6  in the external region CA 2 , as shown in  FIG. 5 , and the regions formed by the overlapping of the fanout wires FLk−1 to FLk+1 with the first to sixth clock signal wires CLk 1  to CLk 6  in the center region CA 3 , as shown in  FIG. 6 , are substantially rectangular. In addition, a width of the fanout wires FLk−1 to FLk+1 of the center region CA 3  corresponds to a width of the fanout wires FLq−3 to FLq of the external region CA 2 . A width of the first to sixth clock signal wires CLk 1  to CLk 6  of the center region CA 3  corresponds to a width of the first to sixth clock signal wires CLk 1  to CLk 6  of the external region CA 2 . Therefore, an area of the overlapping region OA 3  in the center region CA 3  is substantially the same as an area of the overlapping region OA 2  in the external region CA 2 . 
         [0075]    Accordingly, a resistance and capacitance generated by overlapping one fanout wire, for example, the fanout wire FLk, and the first to sixth clock signal wires CLk 1  to CLk 6  in the center region CA 3  of the peripheral area is substantially the same as a resistance and capacitance generated by overlapping one fanout wire, for example, the fanout wire FLq and the first to sixth clock signal wires CLk 1  to CLk 6  in the external region CA 2  of the peripheral area. 
         [0076]    Loads of the fanout wires FL 1  to FLq connected to the demultiplexer  40  may have a same value in the center region CA 3  or the external region CA 2 . Accordingly, when the driver IC  10  supplies signals with a same intensity to the fanout wires FL 1  to FLq, the signals passed to the pixels PX through the demultiplexer  40  may have the same intensity. 
         [0077]    A non-quadrangular display panel will now be described with reference to  FIG. 7 , according to an exemplary embodiment of the present invention. 
         [0078]      FIG. 7  shows part of a configuration of a non-quadrangular display panel, according to an exemplary embodiment of the present invention. 
         [0079]    As shown in  FIG. 7 , the fanout wires FL 1  to FLq of a non-quadrangular display panel, according to an exemplary embodiment of the present invention, are disposed with an angle with respect to the clock signal wires CL 1  and CL 2  on the right and the left with respect to a center of a region of the peripheral area where the fanout wires FL 1  to FLq are disposed. The fanout wires FL 1  to FLk−1 in a left area LA of the peripheral area are inclined to be substantially orthogonal to the clock signal wires CL 1  and CL 2  and are disposed with angles so that imaginary lines extending from the fanout wires FL 1  to FLk−1 may gather (e.g., meet) at a first point P 1  of the display area  30 . The fanout wires FLk to FLq in a right area RA of the peripheral area are inclined to be substantially orthogonal to the clock signal wires CL 1  and CL 2  and are disposed with angles so that imaginary lines extending from the fanout wires FLk to FLq may gather at a second point P 2  of the display area  30 . 
         [0080]    When a size of an acute angle formed when a fanout wire, for example, the fanout wire FL 1 , crosses the clock signal wires CL 1  and CL 2  is “A” and a size of an acute angle formed when a (k−1)-th fanout wire, for example, the fanout wire FLk−1, crosses the clock signal wires CL 1  and CL 2  is “B”, “A” is not equal to “B”. 
         [0081]    However, a difference between “A” and “B”, according to an exemplary embodiment of the present invention, is less than a difference between an acute angle formed when the fanout wire FL 1  crosses the clock signal wires CL 1  and CL 2  and an acute angle formed when the (k−1)-th fanout wire FLk−1 crosses the clock signal wires CL 1  and CL 2  as shown in  FIG. 2 . Therefore, regarding the fanout wires FL 1  to FLq in to  FIG. 7 , according to an exemplary embodiment of the present invention, a deviation of the areas of the regions in which the fanout wires FL 1  to FLq cross the clock signal wires CL 1  and CL 2  is reduced when compared to the deviation of the areas of the regions in which the fanout wires FL 1  to FLq cross the clock signal wires CL 1  and CL 2  in  FIG. 2 . 
         [0082]    The present invention is applicable to any kind of non-quadrangular display panels. The fanout wires FL 1  to FLq for applying a signal to the demultiplexer  40  have been exemplarily described with reference to the above-noted drawings. The present invention is applicable to designing fanout wires for applying signals to driving circuits (e.g., a scan driver) for transmitting signals to pixels PX and overlapping the clock signal wires CL 1  and CL 2 . 
         [0083]    The above-noted drawings do not describe that a portion of the display panel  20  may include a convex curve and a concave curve. However, when the display panel  20  includes the convex curve and the concave curve, the fanout wires FL 1  to FLq may be disposed to cross the clock signal wires CL 1  and CL 2  perpendicularly or substantially perpendicularly. 
         [0084]    The present disclosure relates to a non-quadrangular display panel having substantially the same loads formed on wires for supplying a signal to a pixel PX and having reduced deviation of a data signal supplied to a pixel PX. 
         [0085]    While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims.