Abstract:
A serial peripheral interface (SPI) includes a mask read only memory (ROM). The mask ROM stores a basic input/output system (BIOS) boot block so that the BIOS boot block is protected from being compromised.

Description:
FIELD 
       [0001]    The subject matter herein generally relates to using mask read only memory (ROM) for protecting basic input/output system (BIOS). 
       BACKGROUND 
       [0002]    In electronic devices using BIOS to boot operating systems of the devices, running the BIOS during the booting process can encounter issues due to data corruption caused by damaged or modified BIOS, sudden power interruption, or other reasons. Therefore, better protection of the BIOS is needed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    Implementations of the present technology will now be described, by way of example only, with reference to the attached figures, wherein: 
           [0004]      FIG. 1  is a diagrammatic view of a SPI memory with a mask ROM, in accordance with an embodiment; 
           [0005]      FIG. 2  is another diagrammatic view of a SPI memory with a mask ROM, wherein a BISO region is stored in the SPI memory and a BIOS boot block is stored in the mask ROM, in accordance with an embodiment; 
           [0006]      FIG. 3  is a diagrammatic view showing a device using a SPI memory with a mask ROM to store a BIOS; and 
           [0007]      FIG. 4  is a flowchart showing a process of booting BIOS using the SPI memory of  FIG. 1  or  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts have been exaggerated to better illustrate details and features of the present disclosure. 
         [0009]    Several definitions that apply throughout this disclosure will now be presented. 
         [0010]    The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “outside” refers to a region that is beyond the outermost confines of a physical object. The term “inside” indicates that at least a portion of a region is partially contained within a boundary formed by the object. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like. 
         [0011]    The present disclosure is described in relation to the accompanying  FIGS. 1-4 . 
         [0012]      FIG. 1  illustrates a SPI memory  100  with a mask ROM  200 . In this embodiment, the SPI memory is a ROM and the mask ROM  200  is built within the SPI ROM  100 . The mask ROM  200  can be coupled to the SPI memory. The mask ROM  200  provides protection, such as write protection, for software stored within it. This way the software is protected against malicious hacking, computer virus, unexpected power interruption, and other damaging factors. 
         [0013]      FIG. 2  illustrates an embodiment of a SPI memory  300  which includes a mask ROM  400 . The SPI memory has a flash region  301 , the flash region  301  has a BIOS region  500  to store a BIOS which includes a BIOS boot block  501  stored inside the mask ROM  400  to protect the BIOS boot block  501  against data corruption, and a main BIOS, or rest of the BIOS, stored outside the mask ROM  400  and in the BIOS region  500 . 
         [0014]      FIG. 3  illustrates, via an embodiment, an electronic device  2  using a SPI ROM  900  with the mask ROM  400  built inside it. The device  2  include micro controller unit (MCU)  30 . The MCU  30  has a central processing unit (CPU)  31  and a platform controller hub (PCH)  33 , coupled to the CUP  31 . A memory  60  is coupled to the MCU  30 . A universal serial bus (USB) connection  24  is provided for connecting the MCU  30  to a thumb key  40  for the purpose of BIOS recovery. The thumb key  40  can contain a BIOS image file for reflashing the BIOS. Storage  50 , such as a hard disk drive, can be provided and coupled to the MCU  30  via a connection, such as a SATA connection cable. The storage  50  can contain a BIOS image for reflashing the BIOS in case of data corruption of the BIOS. 
         [0015]    The SPI ROM  900  is coupled to the MUC  30  via a SPI bus  29 , and can have a descriptor region  600 , a gigabit Ethernet (GBE) region  700 , a management engine (ME) region  800  and the BIOS region  500 . The BIOS are stored in the BIOS region  500 , where the BIOS boot block  501  of the BIOS is stored in the mask ROM  400  for write protection. 
         [0016]    Referring to  FIG. 4 , a flowchart of booting the BIOS stored in the SPI memories  100 ,  300 , or  900  (not shown) is presented in accordance with an example embodiment which is being thus illustrated. The example process is provided by way of example, as there are a variety of ways to carry out the method. The process described below can be carried out using the configurations illustrated in  FIGS. 1 to 3 , for example, and various elements of these figures are referenced in explaining example method. Each block shown in  FIG. 4  represents one or more processes, methods or subroutines, carried out in the exemplary process of  FIG. 4 . Additionally, the illustrated order of blocks is by example only and the order of the blocks can change according to the present disclosure. The exemplary process can begin at block  70 . 
         [0017]    At block  70 , booting the BIOS is stared, by, for example, supplying power to the device  2  (as shown in  FIG. 3 ) to cause the BIOS stored in the SPI ROM  900  to be run. In block  72 , the BIOS boot block stored in the mask ROM  200  or in mask ROM  400  is first executed. At next stage in block  74 , an integrity check of the main BIOS stored in the BIOS region  500  to make sure that the BIOS data is not corrupt. The integrity check can be a cyclic redundancy check (CRC) for the main BIOS stored outside the mask ROM  400 . When the result of the integrity check in block  74  turns to be good, the main BIOS is be executed in block  78  following a normal booting of the BIOS. However, when the result of the integrity check in block  74  is bad, i.e., the main BIOS has been damaged or corrupted, then the recovery of the BIOS in block  76  will be performed. The recovery can be done by reflashing the BIOS using BIOS data saved in the thumb key  40  or in the storage  50 , which are connected to the device  2 . 
         [0018]    The embodiments shown and described above are only examples. Many details are often found in the art such as the other features of a SPI memory containing a BIOS. Therefore, many such details are neither shown nor described. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, especially in matters of shape, size and arrangement of the parts within the principles of the present disclosure up to, and including the full extent established by the broad general meaning of the terms used in the claims. It will therefore be appreciated that the embodiments described above may be modified within the scope of the claims.