Abstract:
A structure for selectively programming interconnections between an input contact and an output contact segment in a multilayer semiconductor, comprising a first group of metal segments each being formed on successive layers of the semiconductor and being interconnected by vias, the first group including the output contact segment; a second group of metal segments each formed on successive layers of the semiconductor and being interconnected by vias, the second group including the input contact segment; and means for connecting a metal segment in the first group to a metal segment in a corresponding layer in the second group, thereby connecting the input contact to the output contact.

Description:
BACKGROUND OF THE INVENTION 
     Taking a semiconductor device from a prototype stage to a volume production manufacturing stage often requires multiple revisions of the device with each revision correcting various deficiencies in the device&#39;s operation. Such revisions typically involve changes made to one or more metal layers in order to correct errors or modify the existing circuits. Such changes are often referred to as metal mask changes or metal spins. In order to implement such changes, a new metal mask layer is required to be created. Creating new metal masks can add considerable expense during the development of a new semiconductor product. Accordingly, there is a need to provide a mask, which maximizes the ability of a device to be made functional, and thereby minimizing the number of new masks required. 
     SUMMARY OF THE INVENTION 
     The present invention provides to a method and structure for selectively programming interconnections between a plurality of metal segments in a multilayer semiconductor devices. These metal programmable segments can be used for programming respective bits of a semiconductor device identification number by providing a plurality of possible changes for each bit of an identification number. The metal programmable layers can also be used for selectively adjusting characteristics of an electronic component such as a resistor or capacitor on the semiconductor device. 
     In accordance with this invention there is provided a structure for selectively programming interconnections between an input contact and an output contact segment in a multilayer semiconductor, comprising a first group of metal segments each being formed on successive layers of the semiconductor and being interconnected by vias, the first group including the output contact segment; a second group of metal segments each formed on successive layers of the semiconductor and being interconnected by vias, the second group including the input contact segment; and means for connecting a metal segment in the first group to a metal segment in a corresponding layer in the second group, thereby connecting the input contact to the output contact. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     An embodiment of the invention will now be described by way of example only with reference to the following drawings in which: 
     FIG. 1 is a plan view of a programmable interconnect according to an embodiment of the invention; 
     FIG. 2 is a perspective view of the programmable interconnect of FIG. 1; and 
     FIG. 3 is a perspective view of the programmable interconnect, programmed according to an embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the following description like numerals refer to like structures in the drawings. Referring to FIG.  1  and FIG. 2 there are shown respective plan and perspective views of a programmable interconnect chain, shown in an initial state, according to an embodiment of the invention. The programmable interconnect chain appears as a serpentine-like structure  20  when viewed in plan as shown in FIG.  1 . As illustrated in FIG. 2 the structure  20  is comprised of metal segments formed on successive metal layers, in this case from a first metal layer M 1 (shown as the lowermost layer) to a fifth metal layer M 5  (shown as the uppermost layer) in a stair-like configuration. The structure  20  has multiple ascending and descending stair-like configurations. 
     The successive metal segments are interconnected by vias, starting from metal one M 1  up to metal five M 5  and then returning to metal one M 1  passing through the intermediate layers of metals, namely metal two M 2 , three M 3  and four M 4  respectively. Thus, the first metal layer M 1  is connected through a plurality of vias V 1 - 2   a  and V 1 - 2   b  to the second metal layer M 2 . The second metal layer M 2  is connected through vias V 2 - 3   a  and V 2 - 3   b  to the third metal layer M 3 . The third metal layer M 3  is connected through vias V 3 - 4   a  and V 3 - 4   b  to the fourth metal layer M 4 . Finally, the fourth metal layer M 4  is connected through vias V 4 - 5   a  and V 4 - 5   b  to the fifth metal layer M 5 . 
     Five metal layers have been shown for the purpose of illustration, however, it is understood that any number of metal layers could be employed, according to the type of semiconductor process that is available for manufacturing the device. 
     Referring again to FIG. 2, there is shown structures for making selective contacts which are located in regions between the serpentine structure  20 . The selective contact structures are provided adjacent to the metal programmable interconnect chain in a plurality of regions  30 ,  32 ,  34  and  36  and are also constructed in a similar stair-like ascending or descending connection configuration to the structure  20 . However these may also be constructed in a stacked configuration. 
     In the embodiment shown, the contact points  36 ,  32  and  30 ,  34  are selectively connected to a voltage supply VDD, and a ground supply VSS, respectively. Alternately, as will be described in more detail later, the selective contact points can also be connected to an electronic component integrated on the semiconductor surface, such as a capacitor or a resistor. 
     As illustrated in FIG. 2, a left-most portion of the metal programmable interconnect chain  20  is connected through a metal connection C 1  on metal layer M 1  to the first selective contact structure  30 . 
     All the metal segments interconnected by vias carry the same voltage signal to collectively represent a single conductive layer. Since the programmable interconnect chain  20  is connected through connector C 1  to the selective contact  30 , which in turn in connected to VSS, the ground voltage is carried by the chain up to the right-most portion of metal programmable interconnect  20  to its output OUT. This may then be used to provide a logic “0” level on layer M 1 . 
     If during the process of developing the chip a change in any one of the metal layers is required, then a new mask may be required to implement the change. For example, if there is a problem with a connection made in metal M 3 , then a new metal M 3  mask would be required. Typically, a new metal mask is designated as a new revision of the chip, for example, Rev B or Rev C, etc, which is typically identified by a revision ID code stored in an on-chip register. By using the circuit and apparatus of the present invention, such a revision ID change can be implemented without requiring a new metal mask just for a change in the revision ID code. Thus in a multibit ID, a programmable interconnect chain is used for each bit to be programmed. 
     Referring to FIG. 3, there is shown the programmable interconnect chain  20  which is programmed to provide a change from logic 0, at the OUT contact, 0 to a logic 1, assuming that a change in metal layer M 3  is required. In order to propagate a logic 1, at the OUT contact the chain  20  has to be connected to the VDD source. Since the chain  20  is originally connected by metal connector C 1  to the VSS source  30 , the metal three M 3  mask has to be modified in order to break the chain  20 , and to connect the chain to a VSS source in one of its metal three layer M 3  portions. 
     Choosing the left-most portion of the metal three layer M 3  in the chain  20 , a part  22  of the metal segment in layer M 3  is removed to break the chain  20  in two parts P 1  and P 2  respectively. In the same metal layer M 3  a connector C 2  is provided for connecting the right-most part P 2  of the chain  20  to the VDD source  32 , so the output contact OUT provides a logic 1. 
     Since the connection C 1  is still connected to VSS source  30 , the part P 1  of the chain  20  remains at VSS. 
     Even though any metal portion in the metal programmable interconnect chain  20  can be used for performing such a change, it will be evident to the reader that the left-most metal portion is preferred, since the chain  20  can be amended through multiple changes from the left-most side of the chain to the right-most side where the output OUT is taken. Of course if the OUT is located on the left then the opmposite to the above will apply. 
     A person skilled in the art will note that to implement the present invention, all changes should comply with the layout design rules specified for that particular integrated circuit, i.e. metal-to-metal spacing, minimum via area, minimum wire width and the minimum overlap of the metal over the vias, among others. For this reason, the break and connection of the metal programmable chain  20  should not be done on the same metal layer portion. In the above mentioned example, the left-most portion of the chain  20  is used to break the chain, and the following metal portion available to the right is used for connecting the chain  20  to the desired selective contact. 
     In a further embodiment of the present invention, the metal programmable interconnect chain  20  can be used not just for programming a bit, but also for selecting or deselecting other elements such as resistors or capacitors. If in FIGS. 1 and 2, the sources  30  to  36  are connected to capacitors instead of being connected to VDD and VSS sources, and each capacitor having a particular capacitance, then the chain  20  can be used to increase or decrease the number of capacitors connected to it, so the overall capacitance provided at the output OUT can be easily modified by changing a metal section on a single layer. A similar implementation can also be constructed for a resistance chain. 
     While the invention has been described in connection with a specific embodiment thereof and in a specific use, various modifications thereof will occur to those skilled in the art without departing from the spirit of the invention. 
     The terms and expressions which have been employed in the specification are used as terms of description and not of limitations, there is no intention in the use of such terms and expressions to exclude any equivalents of the features shown and described or portions thereof, but it is recognized that various modifications are possible within the scope of the invention.