Abstract:
A circuit of electrical materials forming an electrical device so that when power is applied, it provides a cascade switching of power into a multiple load system such as in automotive power windows. When use as an automatic switching device to control a power windows system, a signal that latches or unlatches the power door locks triggers the controller causing the windows to fully close—to enhance security on a parked vehicle, or to fully open—to give convenience to the operator or safety to the endangered passengers.

Description:
BRIEF DESCRIPTION OF DRAWINGS  
       [0001]      FIG. 1  is an electrical circuit of a cascade switching controller and a set of five dc motors connected in a typical fashion to a box that contains the factory built switches and other control devices. (We present a typical car power windows electrical system as an application example.)  FIG. 2  is a dc source that supplies power to the circuits in  FIG. 1 .  
         [0002]      FIG. 1  is subdivided into 7 circuit blocks. Block  1  is an automatic on-off switch and timer circuit that powers on the system at a predetermined period of time. Block  2  is a sequential circuit that controls the switching of power from one motor to another and provides current drivers for various circuit outputs. Block  3  is a voltage regulator and filter circuit that supplies a regulated noise-free voltage needed by some elements of the system. Block  4  is a sync-sensor circuit that sensing the noise generated by the drive motors. Block  5  is an array of single pole double throw power relays that switch the high current required by the drive motors. Block  6  shows a wiring circuit of the drive motors and a box of factory devices as mentioned before. And Block  7  is a deterrent circuit, a safety feature used to suspend, when needed, the operation of the circuit in Block  2 .  
         [0003]     The circuit design applies the versatility of a combination of flip/flop, timer, and op-amp chips to perform a cascaded switching operation. The main component is a chip that contains an array of six sets of d-type positive-triggered flip/flop, controlled by a timer chip by generating the clock signal to it. The op-amp chip is sensing the motors noise current use to synchronize the switching operation. A ground potential signal supplied to the circuit common terminal powers up the system causing the first flip/flop to set into active state sending a high voltage signal to a power relay that energizes its associated drive motor. When a motor either spins or stalls, the op-amps send a corresponding signal to the clock input of the flip/flops through a timer chip.  
         [0004]     A spinning motor causes its designated flip/flop to latch so that it remains energized. A stalled motor deactivates its designated flip/flop and sends its high state output signal down to the next flip/flop. The second motor is then energized while the first one is de-energized. Like the first flip/flop, the same functions of operation takes place and the sequence of switching power to the motors continues down to the third, and to the forth, and then to the last motor until the last active flip/flop high output state signal is sent to a timer power disable circuit that disconnects power from the source. 
     
    
     DETAILED DESCRIPTION  
       [0005]     In Blocks  5  and  6 , a set of five dc motors are connected to a source positive potential Vb and ground through the power relays and a factory installed device box Bx. The power supply positive potential Vb is supplied to each dc motor through a main relay K 2  contact pins  1  and  3  and through each of their designated driver relay K# contact pins  1  and  3 , while the negative ground potential is provided through power relay K 3  contact pins  1  and  3 , P− terminal, box Bx, and d# terminals respectively. The relays pin  2  is a normally close contact pin, so that when the system is on the standby mode, the Vb potential is always present at a terminal P+ of the box Bx allowing a manual operation of the system. Likewise at standby mode, all terminals u# and d# of the box Bx are connected to the negative ground potential, so that, with the activation of the power relays by the controller circuit, an automatic switching operation can be performed. A power relay K 3  is added to ensure that a ground potential is always applied to the P− terminal, even when a factory built switch S is left open.  
         [0006]     For automatic operation, which is the purpose of this invention, Block  1  circuit is preferably needed to function in order to power up the controller. Block  1  circuit has two main components, a Timer chip U 1  and a double-pole-double-throw relay switch K 1 . A double-pole-single-throw switch S 1  is added to use as a manual disable switch. The other associate components are the rectifier diodes D 1 , D 2 , D 3 , D 4 , and D 5  that block the undesired signals. The terminals C, D, E, and G are intended for optional devices that can be interfaced with the sys-tem. The VCC pin of the timer U 1  is connected to the Vb potential through the diode D 1 , while its GND pin is connected to the common terminal of the circuit. A capacitor C 1  is shunted across the pin  1  of the relay K 1  and the circuit common terminal to shunt any suppress noise to the ground developed by its switching contacts.  
         [0007]     The Vb potential is applied to the relay K 1  coil pin c 1  through the diode D 1 , and the pin c 2  is connected to the circuit common terminal through a driver transistor integrated inside the chip U 4  of Block  2 . Two resistors, R 1  and R 2 , are connected to DIS pin of U 1 . The other side of R 1  is connected to the Vb potential through D 1 , while the other side of R 2  is connected in series with a capacitor C 2  which other pin is connected to the circuit common terminal. The line of connection between R 2  and C 2  is then connected to the joint pins TRIG and THRE of the timer U 1 . The values of R 1  and C 2  determine the length of time the system keeps the power on, that limits the operation time to avoid damage to the motors when malfunction occurs.  
         [0008]     The Timer chip and its associated components form a basic astable timer circuit that provides 3 different functions as; a power-on switch, a time-delay timer, and a power disable circuit. A NPN transistor Q 1  is used as a switch to reset the timer U 1  that is its function as a power disable device. The collector pin of Q 1  is connected to a line between the RSET pin of the timer and the resistor R 5  forming a junction. The other side of R 5  is connected to the source Vb via the diode D 1 . The emitter pin of Q 1  is connected to the circuit common terminal. Two resistors R 3  and R 4  and a diode D 4  are connected together forming a junction that is connected to the base pin of the transistor Q 1 . The other side of R 4  is connected to the circuit common terminal and the opposite side of R 3  is connected to the cathode pins of D 2  and D 3 . Their anodes are then connected to each input terminal, D 2  to A and D 3  to B respectively. The diode D 4  passes the positive signal that comes from a source in Block  2  that is to be discussed later.  
         [0009]     When a momentary negative signal, with a time duration that is not less than 20 milliseconds, is applied to the input terminal F, it is instantly supplied to the circuit common terminal through the switch S 1  and the diode D 5 . At this instance, when both terminals A and B receive no power-disable signals, the timer U 1  starts the cycle causing C 2  to charge. Without positive signal applied to both terminals A and B, the base of transistor Q 1  has no bias voltage and causes it to maintain a high impedance or non-conducting state, that keeps the RSET pin of U 1  to remain disconnected from the ground potential. This condition causes a high voltage output at the OUT pin of the timer U 1 . Otherwise, the output is remained relatively low at ground potential that disables the system power application.  
         [0010]     The high voltage at the OUT pin of U 1 , which is connected to the input INA pin of a driver chip U 4  in Block  2  as describe before, causes a low output signal at the OUTA pin that is a ground potential at the circuit common terminal. This ground potential activates the relay K 1  that causes its pin  4  to close contact with pin  6  that is permanently connected to the circuit common terminal. The negative ground potential of the power supply will be directly applied to the circuit common terminal through closed contact pins  1  and  2  of switch S 1  as well with close contact pins  4  and  6  of the relay K 1 . Then the negative signal at the terminal F eventually becomes irrelevant. At the same instance, the relay K 1  pin  1 , that is ganged with pin  4 , and pin  3  make a close contact that connects the potential Vb to the various segments of the circuit making the system power on and ready to perform an automatic switching operation. The relay K 1  remains activated until either a complete operation is accomplished or the time delay set by C 2  and R 1  expires.  
         [0011]     Right after the relay K 1  becomes activated, both relays K 2  and K 3  parallel connected coil pins c 1  and c 2 , that are shunted with a suppressor diode D 12  (the cathode at pin c 1  and the anode at pin c 2 ), are connected to the power supply; c 1  pins—to the Vb potential through relay K 1  pins  3  and  1  through diode D 1 , while c 2  pins—to the ground potential through the circuit common terminal. This makes the relays K 2  and K 3  active that causes K 2  pin  1  to close contact with pin  3  that supplies the Vb potential straight to the coil pins c 1  of all the rest of the power relays. The closed contact pins  1  and  3  of the relay K 3  bypasses switch S that connects a ground potential to the P− terminal of the box Bx. This condition makes all the drive motors to have a potential to spin just by applying a negative voltage to pin c 2  of their designated power relay.  
         [0012]     In Block  2 , three chips are used to form the main circuit that generates and processes the switching signals fed to the power relays in Block  5 . The Vb potential that is supplied to the VCC pins of the chips U 2  and U 3  as well with the other chips in Blocks  4  and  7  is dropped, regulated, and filtered by a voltage regulator of the Block  3  circuit which is typically consists of; a Zener diode D 11 , a voltage dropping resistor R 13 , and two filter capacitors C 8  and C 9 . Hereafter, we will alternately refer to the regulated voltage Vcc and the negative circuit common terminal as V+ and V− for simplicity. The chip U 3 , that is an array of six positive-edge triggered D-type flip/flops, is used to provide a cascaded signal needed by the driver chip U 4  to activate the power relays one at a time. The chip U 2  is another Timer chip that is used to generate clock pulses required by the flip/flops chip. The chip U 4  as mentioned before is an array of drivers consists of eight Darlington transistors, each with integral suppression diode, and with its Com pin directly connected to Vb through diode D 1 . An astable timer circuit of chip U 2 , like the first timer chip U 1 , is associated with two resistors and a capacitor. The two resistors, R 14  and R 15 , and a capacitor C 6  are connected in series. The line between R 14  and R 15  is connected to a DIS pin of the timer U 2 , while the other side of R 15  is connected to a junction formed by C 6  and the timer joint pins THRE and TRIG respectively. This junction is also connected to the other components of the circuit that responsively react to suspend the timer U 2  operation. The other side of C 6  and the timer GND pin are connected to the circuit common terminal while the other side of the resistor R 14 , the pins of VCC and RSET, are all connected to the V+ source. The pulse signal generated by the timer U 2  that comes out from its OUT pin is then fed to the input CLK pin of U 3 .  
         [0013]     The flip/flops chip U 3  is associated with two resistors, R 16  and R 17 , a capacitor C 7 , and five rectifier diodes D 6 , D 7 , D 8 , D 9  and D 10 . Two common inputs, CLK and CLR, control the flip/flops. The V+ and V− potentials are applied across the VCC and GND pins accordingly. A resistor R 17  is used as a load resistor connected to a driver output OUTG pin of U 4 . The connection line between R 17  and the output OUTG pin of U 4  is then connected to the input  1 D terminal pin. Both resistor R 16  and capacitor C 7  combine a series connection as a timer to delay an input signal. The other side of R 16  is connected to the V+ while the other side of C 7  is grounded through the circuit common terminal. The CLR pin of U 3  is connected to the joint pins of R 16  and C 7  forming a junction that is then connected to a line going to the Deterrent circuit of Block  7 .  
         [0014]     When power is applied, the V+ voltage is instantly supplied to the first flip/flop input  1 D pin through R 17 . The capacitor C 7  starts charging through the resistor R 16 . The RC Time Constant of their combined values causes the CLR pin of U 3  to receive a slow increasing voltage. Just before C 7  starts to charge, the low voltage at the CLR pin initially set all the flip/flops output to low. When the voltage across C 7  has increased into a high level of signal required by the CLR pin of U 3 , the rising positive voltage of a pulse signal at the CLK pin sets the output IQ of U 3  into a high state. This output pin is connected to a junction that splits into three different lines; the first line directly connects the input INB of U 4 , the second line leads to the input ING of the same chip through a diode D 6 , and the third line goes to the Input  2 D of the second flip/flop.  
         [0015]     The high voltage signal at the output  1 Q of U 3  is utilized to perform three different functions: First, the high voltage it sends to the input INB of the chip U 4  causes its designated output OUTB to set a low state signal that is a negative ground potential. This ground potential is then applied to the coil pin c 2  of the power relay K 4 . Since the other side of the coil is already connected to the Vb potential through relay K 2  contacted pins  1  and  3 , relay K 4  will be activated causing its common contact pin  1  to open contact with pin  2 —disconnecting the ground potential, and to close contact with pin  3  connecting the Vb potential. Both terminals of the dc motor M 1  are now connected to the Vb and ground of the power supply. The Vb potential is connected through contact pins  1  and  3  of the power relays K 2  and K 4  respectively, while the ground potential is obtained through contact pins  1  and  3  of the power relay K 3 , P− terminal, box Bx, and d 1  terminal. The motor M 1  spins if the window driven by it is open, otherwise, it remains stalled.  
         [0016]     A spinning motor generates noise in form of current pulses at both sides of the terminal of the power supply. Base from our experience, we have observed that the best spot to sense motor noise is at the negative line close to the motor. The noise current and the conductor resistance between the negative terminal of the motor and the power supply produce a few milli-volt of varying voltage drops. The Op Amp chip U 5  in Block  4  (this circuit will be described later) amplifies these small varying voltages. The amplified motor noise becomes a high power of pulses that is good enough to use as a sync signal. This sync signal that comes out from the amplifier circuit is fed to the input base of a driver transistor, that is integrated inside the chip U 4 , through the input INH and causes a changing state output at the collector that is internally connected to the output OUTH. This signal is then fed to a junction formed by C 6 , D 13 , R 15 , and the joint pins THRE and TRIG of the timer chip U 2 . The frequency of this motor noise signal is practically much greater than the oscillating frequency produced by the timer U 2 , so that every time a motor noise is present, the capacitor C 6  is repeatedly discharging before attaining a Threshold voltage. Therefore, the timer stops generating pulses sending a steady state of signal at the input CLK of U 3 . This latches the high state output of  1 Q that further keeps the motor M 1  spinning until the window is fully closed.  
         [0017]     The second function of the high state output Q is to switch its input D from high to low state. This is done by converting the high state signal of  1 Q to low state signal and feeds back to its input  1 D through its designated rectifier diode D 6  and its designated driver transistor integrated inside the chip U 4 . The output  1 Q pin is connected to the anode of D 6  and its cathode is then connected to the input ING pin of U 4 . The high state signal at the input ING corresponds a low or ground potential at the output OUTG. This ground potential signal is then sent to a line of connection between the load resistor R 17  and the input  1 D of U 3  that practically changes its state from high to low. At the same time, the high output  1 Q sets the input  2 D to high state by a direct connection between their pins. This setup prepares the transfer of the switching operation to the next flip/flop, which is the third function of the high output Q.  
         [0018]     A stalled or non spinning motor produces no noise signal at all. When the motor M 1  is stalled or stops from spinning for any reason, the high output state of  1 Q will keep it energized in a short period of time set by the combined values of R 14 , R 15 , and C 6 . And when there is no motor noise to use as signal to stop the timer U 2  from generating clock pulses, the positive going edge of a clock pulse sets the output  2 Q of the second flip/flop to high state while the output  1 Q of the first flip/flop changes from high to low state. Therefore, the second motor M 2  is energized while the first motor M 1  becomes de-energized, and all the three functions of the previously high output  1 Q will be performed as well by the currently high output  2 Q. The same circuit operation takes place when the switching sequence advances to the next motor M 3 , then to M 4 , and then to the last motor M 5 .  
         [0019]     The Block  2  drawing is also showing that all the cathodes of the rectifier diodes, from D 6  to D 10 , are commonly connected to a single input ING pin of the chip U 4 . While their anode pins are separately connected in the following manner: Like the diode D 6 , the anode pin of D 7  is connected to a junction formed by the input  3 D of U 3 , the output  2 Q, and the input INC of U 4 . The Diode D 8  anode similarly goes to a junction formed by the input  4 D, the output  3 Q, and the input IND of U 4 . The anode pin of D 9  is likewise connected to a junction formed by the input  5 D, the output  4 Q, and the input INE of U 4 . And the last diode D 10 , its anode pin is connected going to a junction made up by the input  6 D, the output  5 Q, and the input INF of U 4 . These diodes make the flip/flops outputs ( 1 Q to  5 Q) isolated from each other.  
         [0020]     When the last motor M 5  is energized, the high state output of  5 Q is fed to the input  6 D of the last flip/flop so that the positive going edge of the next clock pulse will trigger a high state output at  6 Q. This high state of signal is then fed to the base of the power transistor Q 1  through the diode D 4 , that causes Q 1  to set into a low impedance or conducting state. This conducting state of Q 1  connects the RSET pin of U 1  to the ground. When a negative potential is applied to the RSET pin of the timer U 1 , its Out pin switches from high into a relatively low state. This low state of voltage applied to the input INA of U 4  corresponds to a high or non-conducting output state at OUTA that is connected to the coil pin c 2  of the relay K 1 . A disconnected c 2  pin from the ground potential deactivates the relay K 1  causing the common pin  1  to release contact with pin  3  disconnecting the Vb potential, while the common pin  4 , that is ganged with common pin  1 , releases contact with pin  6  disconnecting the circuit common terminal from the negative ground potential. Therefore, the system shuts off before a predetermined period of time sets by R 1  and C 2  expires.  
         [0021]     The Deterrent circuit in Block  7  is mainly made up of another Timer chip and two NPN power transistors. The timer U 6  is used as a time delay device that provides a high state output at OUT pin when cycle begins. Typically, the V+ is applied on both pins of VCC and RSET while V− is applied at GND pin. The cycle time is set by the combined values of resistor R 21  and capacitor C 11 . One side of R 21  is connected to the V+ and the other side is connected in series with C 11  with negative pin connected to the circuit common terminal. The line between R 21  and C 11  is connected to the joint pins of THRE and DIS. A capacitor C 10  is shunted across CONT pin and the circuit common terminal. The TRIG pin is connected to a junction formed by a load resistor R 22 , a rectifier diode D 18 , and a NPN transistor Q 3 . The other side of R 22  and the cathode of D 18  are both connected to the V+ potential while the emitter pin of the transistor Q 3  is connected to the circuit common terminal. The anode of D 18  is connected to the TRIG pin to protect the timer against any suppress voltage that may develop on the TRIG line, while the capacitor C 10  is use to provide a bounce-free CONT line, so that the timer is protected against any false trigger signal. Two resistors R 23  and R 24  are connecting a line that provides a biasing network to the base of Q 3 . The other side of R 24  is connected to the circuit common terminal while the other side of R 23  is connected to an input J terminal via a blocking diode D 19 . The diode D 19  is used to pass a positive signal that comes from external source.  
         [0022]     The drawing also illustrates that the OUT pin of U 6  is connected to the base pin of the power transistor Q 2  through a rectifier diode D 17  and a resistor R 19 . Another input point designated as terminal I, that also receives a positive signal from external source, is connected to a line between the D 17  and R 19  through a dropping resistor R 18  and a rectifier diode D 15 . The resistor R 20  shunts the base pin of Q 2  from the ground forming a junction with R 19  to provide a biasing circuit. The diode D 17  is used to block the OUT pin of U 6  from the positive signal that comes in the input I terminal. The collector pin of Q 2  is connected to the cathode of two diodes, D 14  and D 16 . The anode of D 14  is connected to a junction formed by R 16 , C 7 , and the CLR pin of U 3 . While the anode of D 16  goes to a junction formed by C 2 , R 2 , and the joint pins of THRE and TRIG of U 1 . The emitter pin of Q 2  is grounded through the circuit common terminal.  
         [0023]     A momentary positive signal applied to the input J terminal causes Q 3  to have a low impedance output. This low impedance or conducting state of Q 3  momentarily connects the TRIG pin of the timer U 6  to the ground that starts a timer cycle causing the OUT pin to deliver a high voltage signal to the base of the power transistor Q 2 . This voltage causes Q 2  to switch to its conducting state that connects a ground potential to both the CLR pin of U 3  and the high side terminal of C 2 . A grounded CLR pin of U 3  clears or switches all the flip/flops output into low state. This causes a closing window to stop moving up that is a safety feature of this invention. Likewise, a grounded C 2  causes to discharge so that the timer U 1  extends its on-cycle. When the timer cycle of U 6  expires, its OUT pin becomes low that switches Q 2  back to non-conducting state disconnecting the ground from CLR pin of U 3  and capacitor C 2 . Then U 3  restarts its operation, setting all outputs, from  1 Q to  6 Q, into momentarily high state one at a time, a cascade switching as described before, causing the interrupted open window to resume closing. The capacitor C 2  begins to recharge voltage for a full time cycle. When a positive signal is applied to the input I terminal, the base of Q 2  receives a biasing voltage through D 15 , R 18 , and R 19  that makes Q 2  to switch into a conducting state. This has the same effect when a positive signal is applied to the J input terminal except that Q 2  remains conducting only during the presence of a positive signal at the input I terminal.  
         [0024]     The Block  4  sync-sensor circuit is mainly made up of a dual op-amp chip that comprises two stages, U 5 A and U 5 B, amplifier that convert the motor noise into high voltage square waves signal. Like a typical single supply dual op-amp, the power supply V+ and ground are connected to its VCC and GND pins respectively. Two resistors R 7  and R 9  are connected in series forming a voltage divider that supplies a stable voltage to the non-inverting (+) inputs of the op-amps. The other side of R 7  is connected to the circuit common terminal while the other side of R 9  is directly connected to the V+ source. When a motor spins, the first stage op-amp chip U 5 A amplifies the motor noise signal that is sensing by the inverting input (−) pin through the input K terminal, capacitor C 3 , and resistor R 6 . The terminal K links the sync signal, that is motor noise in this application, that comes from the Box Bx in Block  6  as described before.  
         [0025]     The same components configuration makes the circuit of the second stage op-amp identical with the first op-amp. The amplified motor noise from the first stage output pin is then fed to the inverting input (−) pin of the second op-amp U 5 B through a link capacitor C 4  and an input resistor R 10 . More voltage amplification takes place in U 5 B before the signal is fed to a driver transistor inside U 4 . The high voltage signal is then applied to the input INH pin of U 4 , as described before, through a capacitor C 5  and a resistor R 11 . The reactance value of resistor R 11  combined with capacitor C 12  creates a low-pass filter allowing the needed signal to pass.  
         [0026]     The terminals H and K can be connected to other appropriate source of sync signal to enable the device to control different types of load or system. To conclude, there are many options that may rise and offer a great deal of opportunity in the application as well with the modification or variation on this invention as long as the original scope remains intact.