Abstract:
A method and apparatus for performing serial communication between a host apparatus and a plurality of peripheral devices, such as an optional sheet bank, using an I 2 C bus. The host apparatus includes a processor connected to the I 2 C bus. A respective logic circuit is provided in each of the plurality of peripheral devices. The logic circuits are configured to be serially-connectable and communicable with the host apparatus through the I 2 C bus and to output a unique logic value based on a number of the peripheral devices serially connected to the host apparatus. Further, the host apparatus assigns an identification to each of the plurality of peripheral devices using the unique logic value.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to Japanese patent application No. JPAP11-358147 filed on Dec. 16, 1999 in the Japanese Patent Office, the entire contents of which are hereby incorporated by reference. 
     BACKGROUND 
     1. Field 
     The present invention relates to a method and apparatus for serial communications, and more particularly to a method and apparatus for serial communications effectively performed between a host apparatus and optional peripherals. 
     2. Description of the Related Arts 
     Many image forming apparatuses, such as copying machines, printers, and so on, have a configuration to allow users to add optional equipment such as an optional sheet bank. For example, a user may install two optional sheet banks in addition to a standard sheet bank, thereby having three sheet banks in total. In many cases, the optional sheet banks are identical to each other and even to the standard sheet bank. Therefore, the image forming apparatus needs to identify each sheet bank. 
     FIG. 1 shows a configuration of a prior art image forming apparatus  100  including first and second optional sheet banks  11  and  12  which are connected to a main unit  10 . In this example, the main unit  10  is provided with at least two sets of requisite signals to be used for the first and second optional sheet banks  11  and  12 . One set of signals includes two output signals labeled as S 1  and S 2  and six input signals labeled as S 3  through to S 8 . This prior art image forming apparatus is configured to be equipped with up to two optional sheet banks, and the set of signals for the second optional sheet bank are arranged to pass through the first optional sheet bank, as shown in FIG.  1 . Therefore, each optional sheet bank is provided with 16 signal lines. 
     In this case, as a number of optional sheet banks is increased, a number of requisite cables, a number of requisite connectors, etc. are also increased which is not desirable from the viewpoint of a cost of equipment. 
     FIG. 2 shows a configuration of another prior art image forming apparatus  200  including first and second optional sheet banks  21  and  22  which are connected to a main unit  20 . In this example, input signals labeled as S 3  through to S 8  are multiplexed with a plurality of AND gates plus a select signal line S 9  so that a total number of signal lines is reduced from 16 to 11. 
     Thus, the input signals of S 3 -S 8  can be commonly used by the optional sheet banks. However, the output signals of S 1 -S 2  are increased as the number of optional sheet banks is increased, which will lead to a problem similar to the one caused in the case of the prior art image forming apparatus of FIG.  1 . 
     A 2-bit serial I 2 C (Inter IC) bus is known as a way for serially connecting a plurality of peripherals to a host apparatus. By using the I2C serial bus, a number of signal lines can be decreased. In this case, however, identification of each equipment becomes problematic. 
     A Published Unexamined Japanese Patent Application No. 9-244986 describes a method of dynamically changing an address of each constituent in order to connect a number of constituents, which is actually of limitless, to the I 2 C bus, regardless of a number of requisite address lines. 
     Another Published Unexamined Japanese Patent Application No. 11-96090 describes a method of eliminating a limit for a number of I 2 C buses to be connected to one I 2 C bus. 
     SUMMARY 
     The present invention provides a novel method of performing serial communications between a host apparatus and a plurality of peripherals using an I 2 C bus. In one example, a novel method includes the steps of providing, making, and mounting. The providing step provides the host apparatus with a processor connected to the I 2 C bus. The making step makes a logic circuit. The mounting step mounts the logic circuit on each of the plurality of peripherals. In such a method, the making step makes the logic circuit configured to be serially-connectable and communicable with the host apparatus through the I 2 C bus. Further, the making step makes the logic circuit configured to output a unique logic value based on a number of the peripherals serially connected upstream relative to the host apparatus so that the host apparatus assigns an identification to each of the plurality of peripherals using the unique logic value. 
     The above-mentioned novel method may further include a sending the steps of sending a command sequentially to the plurality of peripherals using the identification and checking if an acknowledgement signal is returned from each of the plurality of peripherals so as to recognize an existence of a peripheral. 
     The above-mentioned novel method may further include the steps of sending a command sequentially to the plurality of peripherals using the identification and checking if an acknowledgement signal is returned from each of the plurality of peripherals so as to detect whether a number of peripherals connected is greater than a maximum number of peripherals connectable to the host apparatus. 
     The present invention further provides a novel image forming apparatus. In one example, a novel image forming apparatus includes a processor and at least one option sheet bank. The processor is configured to be connected to an I 2 C bus. Each of the at least one optional sheet bank includes a logic circuit configured to be serially-connectable and communicable with the processor through the I 2 C bus. This logic circuit is further configured to output a unique logic value based on a number of the above-mentioned at least one optional sheet bank serially connected upstream relative to the processor so that the processor assigns an identification to each of the above-mentioned at least one optional sheet bank using the unique logic value. 
     The processor may send a command sequentially to the above-mentioned at least one optional sheet bank using the identification and check if an acknowledgement signal is returned from each of the above-mentioned at least one optional sheet bank so as to recognize an existence of an optional sheet bank. 
     The image forming apparatus may send a command sequentially to the above-mentioned at least one optional sheet bank using the identification and check if an acknowledgement signal is returned from each of the above-mentioned at least one optional sheet bank so as to detect whether a number of the optional sheet banks connected is greater than a maximum number of the optional sheet banks connectable to the image forming apparatus. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A more complete appreciation of the present application and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
     FIG. 1 is a schematic block diagram of a prior art image forming apparatus; 
     FIG. 2 is a schematic block diagram of another prior art image forming apparatus; 
     FIG. 3 is a schematic block diagram of an image forming apparatus according to an embodiment of the present invention; 
     FIG. 4 is a schematic block diagram of another image forming apparatus according to an embodiment of the present invention; and 
     FIGS. 5A and 5B are time charts for showing cases of returning and not returning an ACK signal. 
    
    
     DETAILED DESCRIPTION 
     In describing preferred embodiments illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the invention is not intended to be limited to the specific terminology so selected and it is to be understood that each specific element includes all technical equivalents which operate in a similar manner. 
     Referring now to the drawings, wherein like reference numeral designate identical or corresponding parts throughout the several views, particularly to FIG. 3, an image forming apparatus  300  using a method for controlling optional equipment according to an embodiment of the present invention is described. As one example, FIG. 3 shows a case in which up to two optional sheet banks are installable in the image forming apparatus  300 . Actually, first and second sheet banks  31  and  32  are installed in the image forming apparatus  300  and have electrical connections to a main unit  30  of the image forming apparatus  300 . In this image forming apparatus  300 , a 2-bit I 2 C (Inter IC) serial bus including a clock-signal (SCL) line and a data (SDA) line is used for a serial communication between each of the first and second sheet banks  31  and  32  and the main unit  30 . The I 2 C bus is defined by N. V. Philips Gloeilampenfabrieken in the Netherlands. 
     As shown in FIG. 3, the optional sheet bank  31  includes a control circuit  31   a  and an I 2 C-bus-compatible device  31   b  which are connected to each other with 8 signal lines. Also, the optional sheet bank  32  includes a control circuits  32   a  and an I 2 C-bus-compatible device  32   b  which are connected to each other with 8 signal lines. The I 2 C-bus-compatible device  31   b  has a clock-signal terminal (SCL) and a data terminal (SDA). The SCL terminal of the I 2 C-bus-compatible device  31   b  is connected to an SCL terminal of a CPU  30   a  of the main unit  30 , through the SCL line of the I 2 C bus. The SDA terminal of the I 2 C-bus-compatible device  31   b  is connected to an SDA terminal of the CPU  30   a  of the main unit  30 , through the SDA line of the I 2 C bus. Also, the I 2 C-bus-compatible device  32   b  has a clock-signal terminal (SCL) and a data terminal (SDA). The SCL terminal of the I 2 C-bus-compatible device  32   b  is connected to the SCL terminal of the CPU  30   a  of the main unit  30 , through the SCL line of the I 2 C bus. The SDA terminal of the I 2 C-bus-compatible device  32   b  is connected to the SDA terminal of the CPU  30   a  of the main unit  30 , through the SDA line of the I 2 C bus. 
     The sheet banks  31  and  32  include inverters  31   c  and  32   c , respectively. Each of the I 2 C-bus-compatible devices  31   b  and  32   b  further includes at least one identification terminal (ID). In this example, each of the I 2 C-bus-compatible devices  31   b  and  32   b  uses one identification terminal (ID) for determining its identification. The ID terminal of the I 2 C-bus-compatible device  31   b  is connected to a single ID line which is grounded in the main unit  30 , and the ID terminal of the I 2 C-bus-compatible device  32   b  is connected to, via the inverter  31   c , the single ID line which is grounded in the main unit  30 . Thus, the ID terminals of the I 2 C-bus-compatible devices  31   b  and  32   b  are preset to 0 and 1, respectively, on the basis of the ID information of the I 2 C-bus-compatible device located at an immediate upstream position. Accordingly, the main unit  30  can selectively communicate with the first and second sheet banks  31  and  32  using these identifications of the I 2 C-bus-compatible devices  31   b  and  32   b  which are 0 and 1. 
     In this way, the image forming apparatus can handle up to two optional sheet bank units with three signal lines instead of using the 16 signal lines of the case shown in FIG. 1 or the 11 signal lines of the case shown in FIG.  2 . 
     The I 2 C-bus-compatible devices  31   b  and  32   b  may be a CPU (central processing unit), an I/O (input and output) expander, or the like. 
     Referring to FIG. 4, an image forming apparatus  400  using a method for controlling optional equipment according to an embodiment of the present invention is described. FIG. 4 shows a case in which up to four optional sheet banks are installable in the image forming apparatus  400 . As shown in FIG. 4, the image forming apparatus  400  is provided with optional sheet banks  41 - 44  which are configured to have electrical connections to a main unit  40 . In this case, the image forming apparatus  400  uses a two-bit-ID configuration and the I 2 C bus for the serial communication between each of the sheet banks  41 - 44  and the main unit  40 . 
     As shown in FIG. 4, the optional sheet bank  41  includes a control circuit  41   a  and an I 2 C-bus-compatible device  41   b  which are connected to each other with 8 signal lines. Also, the optional sheet bank  42  includes a control circuits  42   a  and an I 2 C-bus-compatible device  42   b  which are connected to each other with 8 signal lines. Also, the optional sheet bank  43  includes a control circuits  43   a  and an I 2 C-bus-compatible devices  43   b  which are connected to each other with 8 signal lines. Also, the optional sheet bank  44  includes a control circuits  44   a  and an I 2 C-bus-compatible devices  44   b  which are connected to each other with 8 signal lines. 
     The I 2 C-bus-compatible device  41   b  is provided with a clock-signal terminal (SCL) and a data terminal (SDA) which are connected to SCL and SDA terminals, respectively, of a CPU (central processing unit)  40   a  of the main unit  40 . Also, the I 2 C-bus-compatible device  42   b  is provided with a clock-signal terminal (SCL) and a data terminal (SDA) which are connected to the SCL and SDA terminals, respectively, of the CPU (central processing unit)  40   a  of the main unit  40 . Also, the I 2 C-bus-compatible device  43   b  is provided with a clock-signal terminal (SCL) and a data terminal (SDA) which are connected to the SCL and SDA terminals, respectively, of the CPU (central processing unit)  40   a  of the main unit  40 . Also, the I 2 C-bus-compatible device  44   b  is provided with a clock-signal terminal (SCL) and a data terminal (SDA) which are connected to the SCL and SDA terminals, respectively, of the CPU (central processing unit)  40   a  of the main unit  40 . 
     The sheet bank  41  includes an inverter  41   c  and an OR gate  41   d . Also, the sheet bank  42  includes an inverter  42   c  and an OR gate  42   d . Also, the sheet bank  43  includes an inverter  43   c  and an OR gate  43   d . Also, the sheet bank  44  includes an inverter  44   c  and an OR gate  44   d . These inverters  41   c - 44   c  and the OR gates  41   d - 44   d  are provided along the 2-bit-ID lines for assigning identifications of the I 2 C-bus-compatible devices  41   b - 44   b , respectively, so that the CPU  40   a  of the main unit  40  can perform serial communications using the SCL and SDA lines of the I 2 C bus. Each of the I 2 C-bus-compatible devices  41   b - 44   b  further includes two identification terminals (IDs). 
     The inverters  41   c - 44   c  determine most significant bits (MSB) of the 2-bit IDs of the I 2 C-bus-compatible devices  41   b - 44   b , respectively. That is, the inverter  41   c  determines the MSB of the 2-bit ID of the I 2 C-bus-compatible device  41   b  as 1, the inverter  42   c  determines the MSB of the 2-bit ID of the I 2 C-bus-compatible device  42   b  as 0, the inverter  43   c  determines the MSB of the 2-bit ID of the I 2 C-bus-compatible device  43   b  as 1, and the inverter  44   c  determines the MSB of the 2-bit ID of the I 2 C-bus-compatible device  44   b  as 0. The OR gates  41   d - 44   d  determine least significant bits (LSB) of the 2-bit IDs of the I 2 C-bus-compatible devices  41   b - 44   b , respectively. That is, the OR gate  41   d  determines LSB of the 2-bit ID of the I 2 C-bus-compatible device  41   b  as 0, the OR gate  42   d  determines the LSB of the 2-bit ID of the I 2 C-bus-compatible device  42   b  as 0, the OR gate  43   d  determines the LSB of the 2-bit ID of the I 2 C-bus-compatible device  43   b  as 1, and the OR gate  44   d  determines the LSB of the 2-bit ID of the I 2 C-bus-compatible device  44   b  as 1. 
     Thus, the 2-bit-ID of the I 2 C-bus-compatible devices  41   b - 44   b  are assigned to be as 10, 00, 11, 01, respectively, on the basis of the ID signal sent from the sheet bank located at an immediate upstream position, so that each sheet bank  41 - 44  thereby has a unique identification value set in accordance with a number of the sheet banks  41 - 44  connected to the main unit  40  and a relative connecting position of the sheet banks  41 - 44  connected to the main unit  40 . Thereby, the main unit  40  can selectively communicate with the sheet banks  41 - 44  using these ID signals. 
     According to the standard specification of the I 2 C bus, a communication apparatus is required to return an ACK (acknowledgement) signal as a response to a signal received during the communications. Therefore, when an optional sheet bank is installed and accordingly the I 2 C-bus-compatible device is connected to the CPU  40   a  of the main unit  40 , an ACK signal is returned from the I 2 C-bus-compatible device to the CPU  40   a . But, when an optional sheet bank is not installed and accordingly the I 2 C-bus-compatible device is not connected to the CPU  40   a  of the main unit  40 , no ACK signal is returned from the I 2 C-bus-compatible device to the CPU  40   a  Using this, the CPU  40   a  of the main unit  40  checks as to which I 2 C-bus-compatible device returns the ACK signal while sending commands to all the I 2 C-bus-compatible devices  41 - 44  by changing the ID signals. Thus, the CPU  40   a  can recognize which sheet banks are installed based on the ACK signal of the I 2 C bus without the needs of extra detection tools for detecting the connections of the optional sheet banks. 
     Each of FIGS. 5A and 5B shows a time chart of a case in which the CPU  40   a  of the main unit  40  is configured to detect the connections of the optional sheet banks using the ACK signal returning from the corresponding optional sheet banks. In FIG. 5A, the SDA signal includes an ACK signal and therefore the CPU  40   a  of the main unit  40  detects no connection of the corresponding optional sheet bank. In FIG. 5B, the SDA signal includes an ACK signal and therefore the CPU  40   a  of the main unit  40  detects the connection of the corresponding optional sheet bank. 
     In addition, in a case when the main unit  40  of FIG. 4 is actually configured to be equipped with up to three optional sheet banks, for example, if an ACK signal is returned from the fourth optional sheet bank, the CPU  40   a  of the main unit  40  can detect a problematic event in that a number of option apparatuses greater than the maximum allowable number are installed in the image forming apparatus. 
     Numerous additional modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the present application may be practiced otherwise than as specifically described herein.