Abstract:
Disclosed in a non-volatile (NV) memory device and a method of manufacturing the same. The method includes forming transistor and EEPROM regions by implanting first and second conductive impurity ions into a semiconductor substrate, depositing a gate oxide on an entire surface of the semiconductor substrate, forming a first gate poly on the EEPROM region, removing the gate oxide not below the first gate poly, forming a logic gate oxide, a tunnel oxide and a coupling oxide, forming a logic gate poly on the transistor region and a second gate poly on a sidewall of the first gate poly, forming source/drain extension regions by implanting first and second conductive impurity ions, forming a sidewall spacer on the logic gate poly and the second gate poly, and forming a silicide on the source, drain and logic gate poly of the transistor region.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application claims the benefit under 35 U.S.C. §119 of Korean Patent Application No. 10-2006-0083859, filed Aug. 31, 2006, which is hereby incorporated by reference in its entirety. 
       BACKGROUND 
       [0002]    An embedded NV (non-volatile) memory is formed by integrating an NV memory device and a logic circuit for driving the NV memory device on a single chip, and is manufactured through a combination of basic logic and NV memory technologies. 
         [0003]    Various types of embedded NV memories exist, and a proper embedded NV memory is used according to purposes thereof. 
         [0004]    An embedded NV memory includes a single poly EEPROM (electrically erasable programmable read-only memory), in which a polycrystal silicon layer functioning as a gate is a single layer, a stack gate (ETOX), in which two polycrystal silicon layers are vertically stacked, a dual poly EEPROM which is an intermediate type between the single poly EEPROM and the stack gate, and a split gate. 
         [0005]    The stack gate is suitable for a high density and high performance memory device and is not suitable for a low density memory device because it has the smallest cell size and a complicated circuit. The EEPROM is mainly used for a low density memory device. For example, the single poly EEPROM can be manufactured by simply adding two mask processes in a logic procedure, but it is not suitable for a high density memory device because it has a cell size greater than the stack gate by about 200 times. 
         [0006]    The dual poly EEPROM, which is an intermediate type between the single poly EEPROM and the stack gate, and the split gate are disadvantageous in that their manufacturing process is complicated. 
       BRIEF SUMMARY 
       [0007]    An embodiment of the present invention provides an embedded non-volatile (NV) memory, which has small cell size and a simple manufacturing process, and a method of manufacturing the same. 
         [0008]    In one embodiment, there is provided a method of manufacturing an embedded NV memory, the method including: forming transistor and EEPROM regions by implanting first and second conductive impurity ions into a semiconductor substrate; depositing a gate oxide and polysilicon on an entire surface of the semiconductor substrate; forming a first gate poly on the EEPROM region through patterning and etching processes; removing the gate oxide not below the first gate poly; forming a logic gate oxide, a tunnel oxide and a coupling oxide; depositing a second polysilicon layer; forming a logic gate poly on the transistor region, and a second gate poly on a sidewall of the first gate poly through an etching process of the second polysilicon layer; forming source/drain extension regions by implanting first and second conductive impurity ions into the substrate; forming a sidewall spacer; forming a source and drain in the transistor region using the sidewall spacer as a mask; and forming a silicide on the source, drain and logic gate poly. 
         [0009]    In another embodiment, there is provided an embedded NV memory including: CMOS (complementary metal oxide semiconductor) and EEPROM well regions on a semiconductor substrate; a gate oxide and a first gate poly on the EEPROM well region; a logic gate oxide on the CMOS well region, and a tunnel oxide and a coupling oxide on the EEPROM well region; a logic gate poly on the CMOS well region; a second gate poly on a sidewall of the first gate poly with the coupling oxide therebetween; and a sidewall spacer on the logic gate poly and a sidewall of the second gate poly. 
         [0010]    In another embodiment, there is provided an embedded NV memory including: a transistor and an EEPROM. The EEPROM can include a first conductive well in a semiconductor substrate; source/drain regions in the first conductive well; a gate oxide and a first gate poly on the first conductive well; a tunnel oxide and a coupling oxide on the source/drain regions and the first gate poly, respectively; a second gate poly on a sidewall of the first gate poly with the coupling oxide therebetween; and a sidewall spacer on a sidewall of the second gate poly. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIGS. 1 and 2  are cross-sectional views showing a vertical structure of a NV memory according to an embodiment of the present invention. 
           [0012]      FIG. 3  is a view showing a layout of a NV memory according to an embodiment of the present invention. 
           [0013]      FIG. 4  is a view showing a cell array of a NV memory according to an embodiment of the present invention. 
           [0014]      FIGS. 5 to 11  are cross-sectional views sequentially showing a procedure of manufacturing an embedded NV memory according to a first embodiment of the present invention. 
           [0015]      FIGS. 12 and 13  are cross-sectional views sequentially showing a procedure of forming a suicide according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    Hereinafter, an embedded NV memory and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
         [0017]    When the terms “on” or “over” are used herein, when referring to layers, regions, patterns, or structures, it is understood that the layer, region, pattern or structure can be directly on another layer or structure, or intervening layers, regions, patterns, or structures may also be present. When the terms “under” or “below” are used herein, when referring to layers, regions, patterns, or structures, it is understood that the layer, region, pattern or structure can be directly under the other layer or structure, or intervening layers, regions, patterns, or structures may also be present. 
         [0018]      FIGS. 1 and 2  are views showing a vertical structure of a NV memory according to an embodiment, and  FIG. 3  is a view showing a layout of the NV memory according to an embodiment. 
         [0019]    Referring to  FIGS. 1 and 2 , a first gate poly  10  serves as a control gate and a select gate. 
         [0020]    A second gate poly  11  operates similarly to a floating gate in the related floating gate EEPROM, and controls source and drain regions  12  and  13 . 
         [0021]    In the embodiment as shown in  FIG. 2 , a triple well structure is provided, in which a P-well  14  is surrounded by a deep N-well  15  in order to enhance the isolation of the P-well  14 . 
         [0022]      FIG. 3  is a view showing the layout of the NV memory according to an embodiment. 
         [0023]    Referring to  FIG. 3 , the layout of the NV memory according to an embodiment can be similar to that of a MOS transistor, but the first gate poly  10  is surrounded by the second gate poly  11  which is different from the layout of the MOS transistor in which a gate poly is surrounded by a sidewall spacer. 
         [0024]    Further, N-type impurities are not implanted below the second gate poly  11  in order to form an LDD region. 
         [0025]    Thus, the method for manufacturing the NV memory of the embodiment can adopt most of a related CMOS device manufacturing processes, while replacing the sidewall spacer formation process with the second gate poly formation process. 
         [0026]    That is, instead of performing a sidewall spacer formation process, the poly is deposited and an etchback process is performed such that the sidewall of the first gate poly  10  is surrounded by the second gate poly  11 . 
         [0027]    Accordingly, the NV memory can be manufactured through a very simple process as compared with the related floating gate EEPROM. Further, since the NV memory can have a general MOS transistor structure, the unit cell area thereof is very small. 
         [0028]    Accordingly, the NV memory structure of the above described embodiments can be used to manufacture a high density EEPROM at a very low cost. 
         [0029]    Next, bias conditions for the operation of the NV memory structure according to one embodiment are as follows. 
         [0030]    [Program Method] 
         [0031]    F/N Tunneling scheme: Vg=+Vp1, Vd=Vs=GND, Vb=Floating or GND 
         [0032]    Hot Electron Injection scheme: Vg=+Vp2, Vd=+Vd1, Vs=Vb=GND 
         [0033]    [Erase Method] 
         [0034]    F/N Tunneling scheme 1: Vg=−Ve1, Vd=Vs=GND, Vb=Floating or GND 
         [0035]    F/N Tunneling scheme 2: Vg=GND, Vd=Vs=−Ve1, Vb=Floating or GND 
         [0036]    [Reading Method] 
         [0037]    Vg=+Vref, Vd=+Vd2, Vs=Vb=GND 
         [0038]    According to the program method as described above, electrons are injected to the second gate poly  11  through one of the F/N Tunneling and Hot Electron Injection schemes. According to the erase method, the electrons are extracted from the second gate poly  11  through the F/N Tunneling scheme. 
         [0039]    Reference voltage +V ref  is applied to the first gate poly  10  in order to read a program or erase state, and proper positive voltage is applied to the drain  13 . 
         [0040]    In the case of the program state in which electrons have been injected to the second gate poly  11 , threshold voltage at a portion corresponding to the source/drain extension region under the second gate poly  11  is greatly increased. 
         [0041]    Accordingly, although the reference voltage is applied to the first gate poly  10 , the source/drain extension region under the second gate poly  11  is not inverted because the threshold voltage of the second gate poly  11  is much higher than the reference voltage, so that electric current does not flow and thus the program state is sensed. 
         [0042]    However, in the case of the erase state in which electrons have been extracted from the second gate poly  11 , the threshold voltage at the portion corresponding to the source/drain extension region under the second gate poly  11  is decreased. 
         [0043]    Accordingly, as the reference voltage is applied to the first gate poly  10 , the source/drain extension region under the second gate poly  11  is inverted because the threshold voltage of the second gate poly  11  is lower than the reference voltage, so that electric current flows from the drain  13  to the source  12  and thus the erase state is sensed. 
         [0044]    Voltage coupled to the second gate poly  11  is determined by the ratio (i.e. coupling ratio) of capacitance between the second gate poly  11  and the source/drain region to capacitance between the first gate poly  10  and the second gate poly  11 . According to an embodiment, since the capacitance between the source/drain region and the second gate poly  11  is much smaller than the capacitance between the second gate poly  11  and the first gate poly  10 , the coupling ratio can have a value of more than 0.8. 
         [0045]    A method for manufacturing the NV memory of an embodiment adopts a related CMOS device manufacturing process where the sidewall spacer formation process of the CMOS device manufacturing process is replaced with a second gate poly formation process. Accordingly, the NV memory can be manufactured through a very simple process as compared with the related floating gate EEPROM. 
         [0046]    Further, since the NV memory of an embodiment has a general MOS transistor structure, the unit cell area thereof is very small similarly to the related floating gate EEPROM. 
         [0047]    Furthermore, when the NV memory structure of the above described embodiment is used, the high density EEPROM can be manufactured at a very low cost. 
         [0048]    Moreover, since the NV memory can have a high coupling ratio, most of the voltage applied to the first gate poly is induced to the second gate poly, and thus the voltage efficiency can be improved. 
         [0049]    In addition, since the NV memory can adopt the related CMOS device manufacturing processes, it can be easily embedded into a logic device. 
         [0050]      FIG. 4  is a view showing a cell array of the NV memory according to an embodiment of the present invention. 
         [0051]    As shown in  FIG. 4 , the NV memory has a structure in which the periphery of the first gate poly  10  is completely surrounded by the second gate poly  11 . 
         [0052]    Accordingly, the coupling ratio can be significantly increased as compared with the related floating gate device structure. 
         [0053]    Moreover, different from the related floating gate device, since the second gate poly  11  does not need to be separately defined in the word line and bit line directions, the NV memory can be manufactured through a very simple process. 
         [0054]      FIGS. 5 to 11  are cross-sectional views sequentially showing a procedure of manufacturing the embedded NV memory according to a first embodiment. 
         [0055]    Referring to  FIG. 5 , active regions of a semiconductor substrate can be isolated by shallow trench isolation regions (STIs)  20 . A P well  21  can be formed in active regions for a logic NMOS, an N well  22  can be formed in active regions for a logic PMOS, and a P well  23  can be formed in active regions for an EEPROM. A pad oxide  24  can be formed on the substrate  25  before forming the P well  21 , N well  22 , and P well  23 . 
         [0056]    Referring to  FIG. 6 , the pad oxide  24  can be removed, and a gate oxide  26  can be grown on the entire surface of the semiconductor substrate  25 . Polysilicon can be deposited on the entire surface of the semiconductor substrate  25 , and the first gate poly  10  can be formed through patterning/etching processes. 
         [0057]    Referring to  FIG. 7 , the gate oxide  26  that is not below the first gate poly  10  can be removed from the substrate and a logic gate oxide  27  can be grown. 
         [0058]    In one embodiment, during the process of growing the logic gate oxide  27 , a tunnel oxide  28  and a coupling oxide  29  can be simultaneously formed on the EEPROM region. 
         [0059]    According to another embodiment, the tunnel oxide  28  and the coupling oxide  29  can be formed first and then the logic gate oxide  27  can be formed. 
         [0060]    In yet another embodiment, the logic gate oxide  27  can be formed first and then the tunnel oxide  28  and the coupling oxide  29  can be grown. 
         [0061]    Referring to  FIG. 8 , a second polysilicon layer  30  can be deposited on the entire surface of the semiconductor substrate  25 . A photoresist pattern  31  for a logic gate poly can be formed through a patterning process. That is, the photoresist pattern  31  is not formed in the EEPROM region, but is formed in the logic PMOS and logic NMOS regions. 
         [0062]    Referring to  FIG. 9 , a logic gate poly  32  is formed through an etching process using the photoresist pattern  31  as an etch mask. During the etching process for the logic gate poly  32 , a second gate poly  11  is fabricated around the first gate poly  10  in the form of a sidewall spacer. 
         [0063]    Referring to  FIG. 10 , source/drain extension regions  39 ,  40 ,  41 , and  42  are formed through an impurity implantation process. Then, a sidewall spacer  34  can be formed. Next, source/drain regions  35 ,  36 ,  37 ,  38 ,  12 , and  13  can be formed through an impurity implantation process. The implantation process for P-type and N-type impurities can be separately performed. 
         [0064]    The source/drain regions  12  and  13  in the EEPROM region can be formed through an N-type impurity implantation process. However, other embodiments can provide an EEPROM region in PMOS form. 
         [0065]    According to an embodiment, since the impurity ions are implanted after forming the second gate poly  11 , the impurity ions are not directly implanted into the substrate below the second gate poly  11 . 
         [0066]    Referring to  FIG. 11 , a silicide  43  can be formed on the sources  35  and  37 , drains  36  and  38 , and gate  32  of the CMOS devices. A silicide blocking layer  44  can be formed on the EEPROM region, so that the silicide is prevented from being formed on the source  12 , drain  13 , first gate poly  10  and second gate poly  11  of the EEPROM device when silicide is being formed in the logic regions. 
         [0067]    According to another embodiment, the silicide blocking layer  44  can be formed only on the first gate poly  10  and the second gate poly  11 , so that the silicide can be formed on the source  12  and the drain  13  of the EEPROM region. 
         [0068]      FIGS. 12 and 13  are cross-sectional views of a method of manufacturing a NV memory device according to another embodiment. 
         [0069]    Referring to  FIGS. 12 and 13 , an etching process of forming the logic gate poly  32  can be performed such that the second gate poly  11  in the form of a sidewall can have a height lower than the top surface of the first gate poly  10 . 
         [0070]    Then, the sidewall spacer  34  can be formed on the second gate poly  11  covering the second gate poly  11 . 
         [0071]    Here, a silicide blocking layer is not formed on the EEPROM region, so that the silicide is formed on the first gate poly  10 , source  12  and drain  13  of the EEPROM device as well as the logic NMOS and PMOS devices. 
         [0072]    According to embodiments of the present invention, the embedded NV memory can be achieved by adding only one photo patterning process to the related CMOS device manufacturing process, so that the entire procedure can be simply implemented as compared with the related floating gate embedded EEPROM, lowering the manufacturing cost and significantly shortening the process development period. 
         [0073]    Further, according to an embodiment, the unit cell area can be greatly reduced to a level corresponding to that of the related floating gate embedded EEPROM cell, so that a high density EEPROM can be achieved with a low manufacturing cost. Accordingly, the embodiment is suitable for embedding a MTP (Multi-Time Program) or OTP (One-Time Program) EEPROM of less than 1 Mb into the related back-bone standard logic process. 
         [0074]    Furthermore, according to an embodiment, the first gate poly is completely surrounded by the second gate poly, so that the coupling ratio can be significantly increased, thereby improving the efficiency of voltage applied during the program/erase operation. 
         [0075]    Any reference in this specification to “one embodiment,” “an embodiment,” “example embodiment,” etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments. 
         [0076]    Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.