Abstract:
A bus interface system includes a processor unit 10 a local bus 11 coupled to the processor unit and interface circuitry 12 coupled to the local bus 11 for providing continuous generation of addresses on the local bus 11 or on a system bus 15. The local bus 11 may be a processor bus on a computer board while the system bus 15 may be an architectural bus standard such as Futurebus+. The interface circuitry 12 includes a universal address generator 14 that provides proper address generation on both system bus 15 and local bus 11. Also a method of generating addresses includes loading an address into an address register, saving the address if it is the first address, outputting the address to a local or system bus, incrementing the address, and repeating sequence at the loading step.

Description:
This application is a Continuation of application Ser. No. 07/915,150 filed Jul. 17, 1992, now abandoned. 
    
    
     FIELD OF THE INVENTION 
     This invention generally relates computers and more specifically to bus system interface circuitry and methods. 
     BACKGROUND 
     Futurebus+ is an IEEE specification for backplane-based computing that permits architectural consistency across a broad range of computer products. Key attributes of Futurebus+ are discussed in the article of J. Theus appearing in Microprocessor Report, Volume 6, Number 7, May 27, 1992. Futurebus+ is a comprehensive architectural specification designed as an open standard; that is, an interface standard for which there are no preconceived restrictions in terms of architecture, microprocessor, and software implementations. It is also designed to support multiple generations of computer technology, leading to system speeds significantly greater than current systems. 
     Futurebus+ provides a 64-bit architecture with a compatible 32-bit subset and data path extensions to 128 or 256 bits. The protocols, while providing headroom for system growth, explicitly support real-time scheduling, fault tolerance, and high-availability and high-reliability systems. 
     The logical layering of the Futurebus+ specifications offers a wealth of architectural features with which designers may implement a wide variety of systems. Both loosely coupled and tightly coupled compute paradigms are supported via the parallel protocols and in the message-passing and cache-coherence protocols. The control and status registers provide a standard software interface to the Futurebus+, easing the development and transportability of I/O drivers and other system software. 
     Unlike older standard buses, Futurebus+ is optimized for a backplane environment. Backplane transceiver logic (BTL) circuits provide incident-wave switching capability (thus no stop and hold times), low capacitance with high current drive capability, and controlled one-volt voltage swings for fast switching. 
     Interface circuits connect local buses to system buses such as Futurebus+. New interface circuits are needed to connect local buses to backplane buses like Futurebus+. It is accordingly an object of the invention to provide a bus interface circuit for connecting a local bus to a standard system bus architecture. It is also an object of the invention to provide a method of connecting a backplane system bus to a local bus. 
     There are many advantages of the invention. First, the universal address generator is compatible with dual bus architecture. Additionally, the circuit can be implemented in standard cell technology, providing system design time reduction, program risk reduction, a greater degree of integration, greater specification complexity, and joint development opportunities. 
     Other objects and advantages of the invention will become apparent to those of ordinary skill in the art having reference to the following specification together with the drawings herein. 
     SUMMARY 
     An address generator providing continuous generation of proper addresses on a local bus or on a system bus is included within a bus interface circuit. The bus interface circuit is coupled between a local bus and a system bus. 
     Preferably the address generation circuitry comprises means for loading an address register, means for saving the first address loaded, means for incrementing said address, and means for saving said incremented address. The address register is loaded from a cache tag register, the system bus, the local bus, or the incremented address. Preferably the system bus is a Futurebus+. 
     This is also a method of generating addresses comprising loading address into an address register, saving the address if it is the first address, outputting the address to a local or system bus, incrementing the address, and repeating sequence at the loading step. 
     Preferably, the method also includes determining whether to load the address from the cache tag, the local address bus, the system address bus, or the incremented address; and determining the size of the increment. Also, the system bus is preferably a Futurebus+. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a bus interface circuit; 
     FIG. 2 is a logic diagram of the universal address generator shown in FIG. 1. 
     FIG. 3 is a flow chart depicting a set of steps which may be used by an address generator of FIG. 2 in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 is a block level diagram illustrating a computer system 19 within which the preferred embodiment of the invention operates. The computer system 19 includes a plurality of computer boards such as 16, 17, 18 . . . n connected to a system bus, 15. System bus 15 is preferably Futurebus+. The computer boards 16 . . . n may have a plurality of memory chips and/or peripheral (I/O) chips on them. The plurality of memory chips and I/O chips may communicate with one another via the system bus 15. Board 18 may be a high-end computer board, performing a function such as, for example, regulating a flow system for the Space Shuttle. Board 18 may contain a microprocessor, 10, and an interface circuit, 12 coupled to local bus, 11. The interface circuit, 12, is also coupled to system bus, 15. Microprocessor 10, for example may comprise a Intel 486, or a Motorola 68040; while local bus 11, may comprise an Intel 486 bus or a Motorola 68040 bus. Interface circuit 12, may comprise common electrical components which together function as a bus interface bridge between a local bus and system bus as known to those skilled in the art. This interface circuitry has been significantly improved by the addition of Universal Address Generator 14 and a Cache Tag Register 13. To maintain the addresses between local buss 11 and system bus 15, interface circuit 12 incorporates the inventive Universal Address Generator, 14. 
     Interface circuitry 12 contains the control logic necessary to translate Futurebus+ transactions into local bus transactions and vice versa. It interfaces easily to the buses that service a variety of microprocessors such as R4000, 680X0, 88XXX and 80X86. Additionally, interface circuitry 12 provides the parallel-protocol support that is required to be in compliance with Futurebus+ standard. Interface circuity 12 performs the transactions required to service the local bus or Futurebus+. It provides information such as the location to which the data is to be routed along with the correct protocol and information (packet or compelled, address, data, or disconnect data). 
     FIG. 2 is a representative circuit diagram of a preferred embodiment of the Universal Address Generator 14 of FIG. 1. A the Universal Address Generator Multiplexor, 21, has four inputs: an incremented address signal 31 from an Increment Multiplexor 24, a cache tag signal 32 from Cache Tag 13, a system address bus signal 33 from bus 15, and a local bus signal 34 from bus 11. The output of Multiplexor 21 is coupled to an Address Register, 22, while the output of Address register 22 is part of the bus 26 which interfaces to both the system bus 15 and the local bus 11. Save Latch 23 receives as inputs, the output of Address Register 22 and an Enable signal 35. It&#39;s output goes to Increment Multiplexor 24. Increment Multiplexor 24 also receives a Count signal input 36. The output of Increment Multiplexor 24 is coupled to the Multiplexor 21. 
     As will be explained in more detail below, Universal Address Generator 14 1) knows where to send the address, 2) keeps a consistent address 3) keeps the address updated and 4) knows how much to increment the address. 
     Additionally, Universal Address Generator 14 provides continuous generation of proper addresses on two buses for disjoint transactions, partial transactions, aligning critical word, and sequential transactions with programmable data lengths, data widths, and address widths. 
     FIG. 3 is a flow diagram illustrating the functional steps followed by the invention. Referring to FIG. 3, a first step 51 is loading the Address Register 22 from one of four locations: 1) Cache Tag Registers 13 2) System Bus 15 via Bus 33 3) Local Bus 11 via Bus 34, or 4) Incrementer circuitry 24. The location selection is based on the signal input on Select line 38. For example, if the Select signal on line 38 indicates that a transaction originates from the system bus, Multiplexor 21 will choose as its input the address from the System Bus input 33. Therefore, signal 38 tells Multiplexor 21 which signal to load. A signal on Latch Enable 39 tells the Address Register when to latch the address. 
     In step 52 of FIG. 3 a signal on Enable 35 determines if the address output of Address Register 22 is saved in the Save Latch 23. Save Latch 23 saves the starting address. When a new address is needed, Multiplexor 24 takes the starting address from Latch 23 and the Count 36 input to generate a new address. Step 52 occurs after the original address is stored. Thus, the original address is loaded in the save register at the beginning of an address transaction in step 53. In transactions that require multiple addresses, the original address is loaded in the address register and also in the Save Latch 23. When the transaction begins, on either bus, the Count (36) is updated and added to the save value. When the transaction is finished the new address is loaded in the address register 22 via the Multiplexor 21 input 31. 
     After the address save of Step 53, the Address Register outputs its address on Bus 26 to be used by System Bus 15 or Local Bus 11. Simultaneous with Step 55, a decision is made whether to increment the saved address, this is step 54. In step 54 the signal on Count 36 determines how much to increment the address in Save Latch 23 for the next transaction. Therefore the value in count 36 is simply added to the address output form Save Latch 23. The decision whether to increment and by how much is based on such things as which bus the transaction is master for, whether it is a read or a write and the data length. This information is fed from line 36, Count received from internal memory and data pointers. 
     In the preferred embodiment there is always an address increment. The decisions made by the Universal Address Generator circuitry 14 are how much to increment by (determined by Count 36). 
     The advantage of Steps 54 and 55 occurring simultaneously is faster back-to-back transaction time. For example, if the output of Step 55 is fed to a slave that decides it must break up a large block transfer into several small transfers with different addresses, by the time the current transaction is finished, the increment has already been performed and is ready to be loaded into the address Register 22 for the next transaction in a multiple transaction set and proceed once again through Step 22. 
     Therefore the increment is performed simultaneous to when the current address is out on the bus. The advantage is that when one transaction is going on with one address, that same address is latched into the save 23 and then incremented and held until the current transaction is complete. When Select 38 is activated the output of Increment Multiplexor 24 feeds the new address into the Address Register, 22 and the method begins again at step 51. 
     The Universal Address Generator 14 maintains the address between two buses 11 and 15. The transactions for the buses can contain multiple pieces of data and can be totally disjoint. For instance, the Local Bus 11 might be doing a critical word first operation while the System Bus 15 does a block transfer. Therefore different addresses can be sent to the local bus 11 while one address for the block is sent to the system bus 15. In another situation, a single transfer can be done on one bus requiring a separate address for each transfer and it can be converted to a block transfer on another bus and vice versa. Another possibility is a block transfer to a block transfer of different sizes. 
     The local bus 11 is capable of performing a single transfer, block transfer, or a block critical word first transfer or a multiple block, while the system bus can simultaneously perform a single, block, or multiple block transfer. 
     An advantage of the Universal Address Generator 14 is that it is capable of handling many transaction modes on the Local and System Bus. Some of the transaction modes the Universal Address Generator handles are End of Data Transactions, 64 Bit Partials, Critical Word First, Multiple Block and Cache Copy Back as described below. 
     The End of Data transaction occurs when a block transfer is split up into multiple data pieces with multiple addresses. In this situation the Universal Address Generator 14 is located on Board 18 acting as a System Bus master when a slave board (for instance Board 16) has run out of data. The slave Board 16 tells master Board 18 that it has hit End of Data. Then the Master board 18 must first increment the address from where the slave stopped and then find a new slave board (possibly board 17) to continue the block transfer in order to finish data transfer in the intended address range. 
     Another possible transaction situation is Critical Word First (CWF) which is a block read on the Local Bus 11. As an example, Interface Circuitry 12 is a System Bus 15 master and a Local Bus 11 slave. The Universal Address Generator 14 is a gateway between the System Bus 15 and the Local Bus 11. In a CWF operation there is an address transformation. For example, Local Bus 11 will request data in the following order: Data #3, Data #4, Data #1, Data #2. This transformation order on the local bus 11 is determined by the interface circuitry 12. Local Bus 11 really wants Data #3 as the current instruction to be executed but will usually request the whole block of data for storage as instruction cache for later access in order to increase overall throughput. This order is prohibited on the System Bus 15. On System Bus 15 the data order is: Data #1, Data #2, Data #3, Data #4. 
     Unlike a CWF operation, a single transaction will have no address transformation. A single address will be loaded from one bus and outputted to the other bus. 
     In a multiple block transaction, Interface circuitry 12 is usually a slave on System bus and master on the Local Bus. The format requires the address to be incremented after every block. 
     For Cache Copyback the complete address is stored in the Cache Tag Register, 13. Board 18 is a system bus master and cannot be a slave anyplace. In this mode, the data in Cache tag Register 18 is directly output onto the System Bus 15. 
     FIG. 2 does not necessarily represent the mechanical structural arrangement of the exemplary system because the Universal Address Generator is preferably generated in Verilog as shown in TABLES 1-7. FIG. 2 is primarily intended to illustrate the major structural components of the system in a convenient format, whereby the present invention may be more readily understood. 
     While in accordance with the provisions and statutes there has been illustrated and described the best form of the invention, certain changes may be made without departing from the spirit of the invention as set forth in a appended claims. Various modifications of the disclosed embodiment will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention. 
     
                       TABLE 1______________________________________MODULE DEFINITION______________________________________module add.sub.-- gen    ( //Inputs - from internal blocksglobal.sub.-- sel,       // Hbus/Fbus cache datah.sub.-- slv.sub.-- addr,       // Hbus block transfer addr36.sub.-- en* ,       // Hbus 36 bit address modehbaddr ,    // Hbus incoming addresslb.sub.-- ptr,       // Hbus FIFO/Store Cache pointerbyte ,      // Hbus partial informationsec.sub.-- wrd,       // Hbus second word of a two word partialtag ,       // Cache tag address sel.sub.-- en* ,       // Fbus selected slavefb.sub.-- master,       // Fbus master indicatorfbaddr ,    // Fbus incoming addressfb.sub.-- ptr ,       // FIFO read pointerwr.sub.-- ptr ,       // FIFO write pointerpartial.sub.-- l,       // Fbus x-fer was a partial transactionfbwidth64.sub.-- 1,       // Fbus x.sub.-- fer was a 64 bit data width //Inputs - from I/O pads fb.sub.-- grant.sub.-- i* ,       // load addreg from Hbus new.sub.-- addr.sub.-- i* ,       // incrment addregdma.sub.-- mode.sub.-- i,       // Hbus no critical word first indicatordlength.sub.-- i ,       // Hbus data lengthh.sub.-- mode.sub.-- i,       // Hbus mode of operation dpu.sub.-- rd* ,       // Fbus Fifo direction reset* ,   // reset signal //Outputsaddress ,   // FBus addressb.sub.-- a.sub.-- o       // Hbus address );______________________________________ 
    
     
                       TABLE 2______________________________________PORT DECLARATIONS______________________________________inputglobal.sub.-- sel, h.sub.-- slv.sub.-- addr,  addr36.sub.-- en* ,sel.sub.-- en* ,fb.sub.-- master,  fb.sub.-- grant.sub.-- i* ,  new.sub.-- addr.sub.-- i*, sec.sub.-- wrd,dma.sub.-- mode.sub.-- i,  dpu.sub.-- rd* ,  reset* , partial.sub.-- 1,fbwidth64.sub.-- 1 ;input [1:0]dlength.sub.-- i ;input [2:0]h.sub.-- mode.sub.-- i;input [3:0]byte;input [6:0]lb.sub.-- ptr, fb.sub.-- ptr, wr.sub.-- ptr ;input [29:0]tag ;input [35:0]hbaddr, fbaddr ;output [35:0]address , b.sub.-- a.sub.-- o ;______________________________________ 
    
     
                       TABLE 3______________________________________NET ASSIGNMENTS AND DECLARATION______________________________________wire [35:0]nxt.sub.-- addr, addr.sub.-- sav, inc.sub.-- add, addreg ;wire [6:0]count;wire [3:0]loaddr;wire [2:0]loaddr.sub.-- sel ;wire [1:0]addreg.sub.-- sel;// *** Define latch elementslch.sub.-- rs # (36)//       * transaction address latch    adreg ({(nxt.sub.-- addr[35:32] &amp; {4{˜ addr36.sub.-- en*    }}),         nxt.sub.-- addr[31:0]},         addreg, reset* ,1&#39;b1, addreg.sub.-- en* ) ;lch # (36)  ad.sub.-- sav(addreg[35:0],addr.sub.-- sav, addr.sub.-- sav.sub.--  en* ) ;______________________________________ 
    
     
                                           TABLE 4__________________________________________________________________________GATE AND STRUCTURAL DECLARATIONS__________________________________________________________________________// *** h.sub.-- mode decoder//  h-mode [2:0]      = 100   sc &lt;-&gt; hbus (block)//         = 000   sc &lt;-&gt; hbus (compelled)//         = 001   fifo &lt;-&gt; hbus (compelled)//                 if lcl.sub.-- csr = 1 then hbus &lt;-&gt; csr//                 if dpu.sub.-- csr = 1,lcl.sub.-- csr=0 csr -&gt; fifo//         = 101   fifo &lt;-&gt; hbus (block)//         = 110   sc -&gt; fifo (block)//         = 111   fifo -&gt; sc (block)//         = 011   hbus invalidate//         = 010   fifo -&gt; csr (compelled)//                 if dpu.sub.-- csr = 1 fifo -&gt; csr// *** Define low address bit zero enableassign  loaddr.sub.-- sel = addr.sub.-- sel.sub.-- enc(global.sub.--  sel,h.sub.-- slv.sub.-- addr,dma.sub.-- mode.sub.-- i,              dlength.sub.-- i) ;// loaddr[3:0] = addreg[5:2] for non-fb cache line trans.// loaddr[3:0] = 4&#39;b0 for fbus+ cache line   assign  loaddr = lo.sub.-- addr.sub.-- algn(loaddr.sub.-- sel,addreg[5:2])  ;   assign  address [35:0] = (addreg[35:6],loaddr,2&#39;b0} ;   assign  b.sub.-- a.sub.-- o = {addreg[31:3],byte.sub.-- addr(byte,partial.s  ub.-- 1,fbwidth64.sub.-- 1,        sec.sub.-- wrd,addreg[2]),addreg[35:32]};// *** Define address register enable line and input mux// addreg.sub.-- sel     = 01 -&gt; fbaddr//        = 00 -&gt; hbaddr//        = 10 -&gt; inc.sub.-- addr//        = 11 -&gt; tag   assign  addreg.sub.-- sel = addrse1.sub.-- dec( sel.sub.-- en* , fb.sub.--  grant.sub.-- i* ,          new.sub.-- addr.sub.-- i* ,h.sub.-- mode.sub.-- i ) ,   addreg.sub.-- en* = &amp;{  fb.sub.-- grant.sub.-- i* ,          sel.sub.-- en* ,  new.sub.-- addr.sub.-- i* } ,   addr.sub.-- sav.sub.-- en* = &amp;{ fb.sub.-- grant.sub.-- i* ,  sel.sub.-- en* } ;// *** Define address register mux// nxt.sub.-- addr =     hbaddr for addreg.sub.-- sel = 2&#39;b00//        fbaddr for addreg.sub.-- sel = 2&#39;b01//        inc.sub.-- add for addreg.sub.-- sel = 2&#39;b10//        tag for addreg.sub.-- sel = 2&#39;b11   assign   nxt.sub.-- addr = mux4.sub.-- 36 ({hbaddr[3:0],hbaddr[35:4]},          fbaddr,inc.sub.-- add,{tag,6&#39; b0},            addreg.sub.-- sel) ;// *** Define incrementor input count for addreg// when h.sub.-- mode.sub.-- i = invalidate -&gt; count = hbus burst   datalength// else count = compelled mode datawidth on fbus// The addreg is updated with fb.sub.-- ptr fbwidth64 during// each transaction. In this way, if an ED occurs, the// addreg has the address of the starting address   assign   count = cnt.sub.-- mux(h.sub.-- mode.sub.-- i,fb.sub.-- master,   dpu.sub.-- rd* ,        dlength.sub.-- i,fb.sub.-- ptr[5:0],        wr.sub.-- ptr[5:0],lb.sub.-- ptr) ;// *** Define address incrementor for &#34;end of data&#34; disconnectsassign   inc.sub.-- add = addr.sub.-- sav + { 27&#39;b0 , count ,2&#39;b0}__________________________________________________________________________   ; 
    
     
                       TABLE 5______________________________________FUNCTION DEFINITIONS______________________________________function [1:0] addrsel.sub.-- dec ;input  sel.sub.-- en* , fb.sub.-- grant.sub.-- i* , new.sub.-- addr.sub.-- i* ;input [2:0] h.sub.-- mode.sub.-- i ;begincasez ({ sel.sub.-- en* , fb.sub.-- grant.sub.-- i* , new.sub.-- addr.sub.-- i* ,  &amp;{(h.sub.-- mode.sub.-- i[2],h.sub.-- mode.sub.-- i[1],˜h.sub.--mode.sub.-- i[0]} })4&#39;b011? : addrsel.sub.-- dec = 2&#39;b01 ;4&#39;b1010 : addrsel.sub.-- dec = 2&#39;b00 ;4&#39;b1100 : addrsel.sub.-- dec = 2&#39;b10 ;4&#39;b1011,4&#39;b1111 : addrsel.sub.-- dec = 2&#39;b11 ;default addrsel.sub.-- dec = 2&#39;b01 ;endcaseendendfunctionfunction [6:0] cnt.sub.-- mux ;input [2:0] h.sub.-- mode.sub.-- i ;input fb.sub.-- master, dpu.sub.-- rd* ;input [1:0] dlength.sub.-- i ;input [5:0] fb.sub.-- ptr ;input [5:0] wr.sub.-- ptr ;input [6:0] lb.sub.-- ptr ;begincasez ({h.sub.-- mode.sub.-- i,fb.sub.-- master, dpu.sub.-- rd* })5&#39;b0110? : cnt.sub.-- mux = dlength.sub.-- dec(dlength.sub.-- i) ;5&#39;b0010?,5&#39;b1010? : cnt.sub.-- mux = lb.sub.-- ptr ;5&#39;b???10 : cnt.sub.-- mux = {1&#39;b0,wr.sub.-- ptr} ;5&#39;b???11 : cnt.sub.-- mux = {1&#39;b0,fb.sub.-- ptr} ;default cnt.sub.-- mux = {1&#39;b0,fb.sub.-- ptr} ;endcaseendendfunctionfunction [6:0] dlength.sub.-- dec ;input [1:0] dlength.sub.-- i ;begincase (dlength.sub.-- i)2&#39;b11 : dlength.sub.-- dec = 7&#39;h02 ;2&#39;b10 : dlength.sub.-- dec = 7&#39;h04 ;2&#39;b01 : dlength.sub.-- dec = 7&#39;h08 ;2&#39;b00 : dlength.sub.-- dec = 7&#39;h10 ;endcaseendendfunctionfunction [2:0] addr.sub.-- sel.sub.-- enc ;input global.sub.-- sel, h.sub.-- slv.sub.-- addr ,dma.sub.-- mode.sub.--i ;input [1:0] dlength.sub.-- i ;begincasez ({global.sub.-- sel,h.sub.-- slv.sub.-- addr,dma.sub.-- mode.sub.--i,dlength.sub.-- i})5&#39;b1.sub.-- ?.sub.-- ?.sub.-- ??,5&#39;b0.sub.-- 1.sub.-- 0.sub.-- 00 : addr.sub.-- sel.sub.-- enc = 3&#39;b000 ;5&#39;b0.sub.-- 1.sub.-- 0.sub.-- 01 : addr.sub.-- sel.sub.-- enc = 3&#39;b001 ;5&#39;b0.sub.-- 1.sub.-- 0.sub.-- 10 : addr.sub.-- sel.sub.-- enc = 3&#39;b010 ;5&#39;b0.sub.-- 1.sub.-- 0.sub.-- 11 : addr.sub.-- sel.sub.-- enc = 3&#39;b011 ;5&#39;b0.sub.-- 1.sub.-- 1.sub.-- ?? : addr.sub.-- sel.sub.-- enc = 3&#39;b100 ;default addr.sub.-- sel.sub.-- enc = 3&#39;b100 ;endcaseendendfunctionfunction [3:0] lo.sub.-- addr.sub.-- algn ;input [2:0] loaddr.sub.-- sel ;input [3:0] addreg ;begincasez (loaddr.sub.-- sel)3&#39;b000 : lo.sub.-- addr.sub.-- algn = 4&#39;bo ;3&#39;b001 : lo.sub.-- addr.sub.-- algn = {addreg[3],3&#39;b0} ;3&#39;b010 : lo.sub.-- addr.sub.-- algn = {addreg[3:2],2&#39;b0} ;3&#39;b011 : lo.sub.-- addr.sub.-- algn = {addreg[3:1],1&#39;b0} ;3&#39;b100 : lo.sub.-- addr.sub.-- algn = addreg ;default lo.sub.-- addr.sub.-- algn = addreg ;endcaseendendfunctionfunction [2:0] byte.sub.-- addr ;input [3:0] byte ;input partial.sub.-- 1 , fbwidth64.sub.-- 1, sec.sub.-- wrd ,addreg ;begincasez ({byte,partial.sub.-- 1,fbwidth64.sub.-- 1})6&#39;b???011 : byte.sub.-- addr = {sec.sub.-- wrd,2&#39;b00} ;6&#39;b??0111 : byte.sub.-- addr = {sec.sub.-- wrd,2&#39;b01} ;6&#39;b?01111 : byte.sub.-- addr = {sec.sub.-- wrd,2&#39;b10} ;6&#39;b011111 : byte.sub.-- addr = {sec.sub.-- wrd,2&#39;b11} ;6&#39;b???010 : byte.sub.-- addr = {addreg,2&#39;b00} ;6&#39;b??0110 : byte.sub.-- addr = {addreg,2&#39;b01} ;6&#39;b?01110 : byte.sub.-- addr = {addreg,2&#39;b10} ;6&#39;b011110 : byte.sub.-- addr = {addreg,2&#39;b11} ;6&#39;b????0? : byte.sub.-- addr = {addreg,2&#39;b00} ;default    byte.sub.-- addr = { addreg, 2&#39;b00} ;endcaseendendfunctionfunction [35:0] mux4.sub.-- 36 ;input [35:0] in1, in2, in3, in4 ;input [1:0] mux.sub.-- sel ;begincase (mux.sub.-- sel)2&#39;b00 :  mux4.sub.-- 36 = in1 ;2&#39;b01 :  mux4.sub.-- 36 = in2 ;2&#39;b10 :  mux4.sub.-- 36 = in3 ;2&#39;b11 :  mux4.sub.-- 36 = in4 ;default mux4.sub.-- 36 = 36&#39;bx ;endcaseendendfunction______________________________________ 
    
     
                       TABLE 6______________________________________LIBRARY MODEL FOR LATCH WITH END______________________________________//**********************************************************// Module Definition//**********************************************************module lch ( in,out,  en* ) ;//**********************************************************// Define Parameters {optional}//**********************************************************parameter width = 1 ,  delay = 1 ;//**********************************************************// Port Declarations//**********************************************************input [ width-1:0 ] in ;input  en* ;output [ width-1:0 ] out ;//**********************************************************// Net Assignments and Declarations//**********************************************************reg [width-1:0] out ;//**********************************************************// Procedural Assignments//**********************************************************always @ ( en* or in)  begin    if ( en* == 0)           #(delay) out = in ;    else if ( en* == 1 || out == in)      #(delay) out = out ;    else      #(delay) out = &#39;bx ;  endendmodule______________________________________ 
    
     
                       TABLE 7______________________________________LIBRARY MODEL FOR LATCHWITH SET, RESET, AND ENAB______________________________________//**********************************************************// Module Definition//**********************************************************module lch.sub.-- rs ( in,out,  reset* , set* ,  en* ) ;//**********************************************************// Define Parameters {optional}//**********************************************************parameter width = 1 ,  delay = 1 ,  ones = 64&#39;hffffffff ;//**********************************************************// Port Declarations//**********************************************************input [ width-1:0 ] in ;input  reset* ,  set* ,  en* ;output [ width-1:0 ] out ;//**********************************************************// Net Assignments and Declarations//**********************************************************reg [width-1:0] out ;//**********************************************************// Procedural Assignments//**********************************************************always @ ( reset* or  set* )  begin    if ( reset* == 1&#39;b0 &amp;&amp;  set* == 1&#39;b1)      assign out = 1&#39;b0 ;    else if ( set* == 1&#39;b0 &amp;&amp;  reset* == 1&#39;b1)      assign out = ones ;    else if ( reset* == 1&#39;b1 &amp;&amp;  set* ==1&#39;b1)      deassign out ;    else      assign out = &#39;bx ;  endalways @ ( en* or in )  begin    if ( en* == 0)     #(delay) out = in ;    else if ( en* == 1 || out == in)      #(delay) out = out ;    else      #(delay) out = &#39;bx ;  endendmodule______________________________________