Abstract:
A method for forming a damascene with improved electrical properties and resulting structure thereof including providing at least one dielectric insulating layer overlying a first etch stop layer; forming an anti-reflectance coating (ARC) layer prior to a photolithographic patterning process; forming at least one opening extending through a thickness portion of the at least one dielectric insulating layer and first etch stop layer according to said photolithographic patterning and an etching process; blanket depositing a barrier layer including material selected from the group consisting of silicon carbide and silicon oxycarbide to line the at least one opening; blanket depositing a refractory metal liner over the barrier layer; blanket depositing at least one metal layer to fill the at least one opening; and, removing at least the at least one metal layer overlying the at least one opening level according to a chemical mechanical polish (CMP) process.

Description:
FIELD OF THE INVENTION  
       [0001]     This invention generally relates to multi-layered semiconductor structures and more particularly to an improved copper damascene and method for forming the same with barrier layers and capping layers provided for improved electrical performance.  
       BACKGROUND OF THE INVENTION  
       [0002]     The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require increasingly sophisticated interconnection technology. As device sizes decrease it has been increasingly difficult to provide metal interconnection technology that satisfies the requirements of low RC (resistance capacitance), particularly where device sizes decrease to about 0.1 microns and smaller.  
         [0003]     In the fabrication of semiconductor devices, increased device density and interconnect requirements has made the provision of multiple metallization levels extending through multiple dielectric insulating levels necessary. Signal transport speed is of great concern in the semiconductor processing art for obvious performance reasons. The signal transport speed of semiconductor circuitry is in part dependent on the RC (Resistance-Capacitance) time constant (delay) which varies inversely with the resistance and capacitance (RC) of the circuitry. Considerations of signal propagation speed is a driving force for adopting technology using copper interconnects extending through low dielectric constant (low-K) insulating layers to form the device circuitry.  
         [0004]     The use of copper for device interconnects has created a number of constantly changing technological problems in semiconductor device manufacturing that must be overcome to provide reliable devices. One problem with copper interconnects has been the fact that copper readily diffuses through silicon dioxide or silicon oxide based materials, a typical IMD material. The diffusion of copper into the IMD layer reduces both the effectiveness of the electrical interconnect and the electrical insulation properties of the IMD layers. Another problem is that copper has poor adhesion to silicon oxide based IMD layers. In a parallel effort to reduce capacitance contributions to the circuitry, low dielectric constant (low-K) insulating layers, also referred to as inter-metal dielectric (IMD) or inter-level dielectric (ILD) layers, have been formed of porous silicon oxide based materials such as carbon doped oxide also frequently referred to as organo-silicate glass (OSG). The use of such low-K materials has necessitated the use of barrier layers also referred to as adhesion or barrier/adhesion layers to line damascene openings prior to filling the openings with metal, e.g., copper, to prevent copper diffusion and improve the adhesion of overlying layers. The barrier layers of the prior art have included metal nitrides such as TaN and TiN.  
         [0005]     One problem with barrier/adhesion layers of the prior art is that their undesired contribution to the overall capacitance of the multi-level device and the added metal interconnect electrical resistance. Approaches to solve these problems have included making the barrier layer increasingly thinner as device sizes decrease below 0.25 microns to 0.1 micron and below. IN addition, efforts have been made to thin or remove remaining portions of the barrier layer overlying the low-K layer at the opening level following metal filling of the opening in a CMP process prior to subsequent processing. These approaches have introduced new problems including the undesired effect of polishing the underlying low-K IMD layer which frequently results in surface scratching and other surface defects which can degrade electrical reliability. For example, it is believed that a phenomenon referred as time dependent dielectric breakdown (TDDB) is related to IMD layer surface scratching during CMP where such scratching provides areas for charge accumulation over time which can result in spontaneous discharge and dielectric breakdown. In addition, the metal nitride barrier layers themselves are believed contribute to TDDB by providing a capacitive interface for electrical charge buildup.  
         [0006]     Another problem with copper damascene structures formed with metal nitride barrier layers is that increasingly thin barrier layers required as device sizes are reduced to 0.1 micron and lower, causes the barrier layer to exhibit unacceptable current leakage performance. In addition, the resistance to crack propagation through IMD layers caused by thermal stresses is compromised by thinner barrier/adhesion layers.  
         [0007]     There is therefore a need in the semiconductor processing art to provide an improved method for forming copper damascene structures including improved barrier layers and capping layers to achieve improved electrical performance of copper circuitry formed in low-K IMD layers.  
         [0008]     It is therefore an object of the invention to provide an improved method for forming copper damascene structures including improved barrier layers and capping layers to achieve improved electrical performance of copper circuitry formed in low-K IMD layers in addition to overcoming other shortcomings and deficiencies in the prior art.  
       SUMMARY OF THE INVENTION  
       [0009]     To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for forming a damascene with improved electrical properties and resulting structure thereof.  
         [0010]     In a first embodiment, the method includes providing at least one dielectric insulating layer overlying a first etch stop layer; forming an anti-reflectance coating (ARC) layer prior to a photolithographic patterning process; forming at least one opening extending through a thickness portion of the at least one dielectric insulating layer and first etch stop layer according to said photolithographic patterning and an etching process; blanket depositing a barrier layer including material selected from the group consisting of silicon carbide and silicon oxycarbide to line the at least one opening; blanket depositing a refractory metal liner over the barrier layer; blanket depositing at least one metal layer to fill the at least one opening; and, removing at least the at least one metal layer overlying the at least one opening level according to a chemical mechanical polish (CMP) process.  
         [0011]     These and other embodiments, aspects and features of the invention will become better understood from a detailed description of the preferred embodiments of the invention which are described in conjunction with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIGS. 1A-1E  are cross sectional views of a portion of a multiple layer semiconductor device showing the improved damascene structure at stages in fabrication according to an embodiment of the present invention.  
         [0013]      FIGS. 2A-2E  are cross sectional views of a portion of a multiple layer semiconductor device showing the improved damascene structure at stages in fabrication according to an embodiment of the present invention.  
         [0014]      FIGS. 3A-3C  are graphical data representations showing improved electrical properties of the improved damascene structure according to embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0015]     Although the method of the present invention is explained by exemplary reference the formation of copper damascene structures in a multi-level semiconductor device it will be appreciated that the method of the present invention is equally applicable to the formation of dual or single damascene structures including use of other filling metals such as copper alloys, tantalum, aluminum, and alloys thereof. The method of the present invention is advantageously used to form metal damascenes, particularly copper damascenes, to improve electrical performance including reducing capacitance contributions to RC signal propagation delay, reducing current leakage, reducing the incidence of time dependent dielectric breakdown (TDDB) by improving time to dielectric breakdown, avoiding CMP of a dielectric insulating layer including a low-K dielectric insulating layer to avoid scratching defects, and increasing a resistance to stress induced crack propagation through a dielectric insulating layer.  
         [0016]     For example, referring to  FIGS. 1A-1E  are shown schematic representations of cross sectional portions of a multiple layer semiconductor device at stages in fabrication according to an embodiment of the present invention. For example, shown in  FIG. 1A  is shown a first dielectric insulating layer  12 A, for example a first inter-layer dielectric (ILD) layer or inter-metal dielectric (IMD) layer formed of a conventional silicon oxide material such as undoped silicate glass (USG), fluorinated silicate glass, or doped or undoped TEOS oxide. Beginning with formation of a metallization layer e.g., M 1 , a conventional etch stop layer  14 A, for example, silicon nitride, is formed over the ILD layer by a LPCVD, HDP-CVD, or PECVD process at a thickness of about 300 Angstroms to about 600 Angstroms.  
         [0017]     Still referring to  FIG. 1A , following the formation of the etch stop layer  14 A, a low-K (low dielectric constant) inter-metal dielectric (IMD) layer  16 A is formed at a thickness of about 1200 Angstroms to about 5000 Angstroms. Preferably the low-K IMD layer  16 A is formed by a PECVD or HDP-CVD process to form an inorganic silicon oxide based material, for example carbon doped silicon oxide, also referred to as organo-silicate glass (OSG), formed using organo-silane precursors. For example, suitable silicon oxide based low-K materials are known by the trade names BLACK DIAMOND™, LKD™, and Orion™. Preferably the low-K IMD layer is formed having a dielectric constant of less than about 3.2.  
         [0018]     Still referring to  FIG. 1A , following formation of the low-K IMD layer  16 A, according to an embodiment of the invention, silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), or silicon nitrocarbide (SiCN) capping (polishing stop) layer  18 A, more preferably SiC, is formed overlying the low-K IMD layer  16 A. Preferably, the SiC capping layer  18 A is formed at a thickness of from about 300 Angstroms to about 500 Angstroms in a PECVD or HDP-CVD process using conventional silicon and carbon precursors.  
         [0019]     Still referring to  FIG. 1A , following formation of the silicon carbide capping layer  18 A, an inorganic anti-reflectance coating (ARC) layer  20 A, preferably silicon oxynitride (e.g., SiON), is deposited overlying the SiC capping layer  18 A at a suitable thickness, for example from about 600 Angstroms to about 1000 Angstroms, to reduce light reflectance in a subsequent photolithographic patterning process.  
         [0020]     Referring to  FIG. 1B , a conventional photolithographic patterning and reactive ion etch (RIE) process is carried out to form openings, e.g.,  22 A and  22 B extending through the IMD layer  16 A to the first ILD layer  12 A. It will be appreciated that the openings  22 A and  22 B may be formed to make closed communication with an underlying conductive area (not shown) to electrically communicate with a semiconductor device (not shown).  
         [0021]     Referring to  FIG. 1C , following formation of openings  22 A and  22 B, according to an aspect of the present invention, a barrier layer  24  of silicon oxycarbide (e.g., SiOC) or silicon carbide (e.g., Sic), more preferably SiOC, is blanket deposited by a conventional PECVD or HDP-CVD process to a thickness of about 100 Angstroms to about 300 Angstroms to line (cover the sidewalls and bottom portion) the openings  22 A and  22 B as well as forming a layer over the process surface. Still referring to  FIG. 1C , following deposition of the SiOC barrier layer  24 , an ultra-thin liner layer  25 A of refractory metal such as Ta or Ti, more preferably tantalum (Ta), is blanket deposited over the SiOC layer by conventional methods to a thickness of about 40 Angstroms to about 60 Angstroms.  
         [0022]     Referring to  FIG. 1D , following deposition of the ultra-thin Ta layer  25 A, a metal filling, for example copper or an alloy thereof is deposited by conventional methods including electro-chemical deposition (ECD) where a copper seed layer (not shown) is first blanket deposited over the openings  22 A and  22 B followed by and ECD process to blanket deposit a copper layer to fill the openings. Following copper deposition, a CMP process is carried out to removes excess copper above the opening levels including removing the ultra-thin Ta liner layer  25 A, the SiOC barrier layer  24 , and the ARC layer  20  above the opening level to stop on the SiC capping layer  18 A thereby forming copper filled damascene structures e.g.,  26 A and  26 B. Advantages of forming the SiC capping layer  18 A include the fact that SiC is a superior polish stop to silicon nitride (e.g., SiN) or SiO 2  having a CMP removal rate of about 5 to 10 times less compared to a conventional capping layer such as SiN or SiO 2 , thereby maintaining a capping layer design thickness to reduce current leakage while avoiding over-polish to induce surface polishing defect to the underlying IMD layer thereby increasing a time to dielectric breakdown. Additionally, capacitance contributions to RC signal propagation delay is reduced by both the capping layer  18 A as well as the SiOC barrier layer  24  compared to metal nitride barrier layers of the prior art such as tantalum and titanium nitrides.  
         [0023]     Referring to  FIG. 1E , following the CMP process to remove materials above the SiC capping layer  18 A level, a conventional etch stop layer  28 A, for example silicon nitride, is deposited in a similar manner as etch stop layer  14 A to begin the formation of the next metallization layer, e.g., M 2 .  
         [0024]     Referring to  FIGS. 2A-2E , in another embodiment of the present invention, an SiC or SiOC layer is deposited to form a continuous layer, acting as both a capping and barrier layer, following formation of damascene structure openings and removal of an overlying organic ARC layer. For example referring to  FIG. 2A , ILD layer  12 B, etch stop layer  14 B, and low-K IMD layer  16 B are deposited as discussed with reference to  FIG. 1A . However, in this embodiment, a conventional organic ARC layer  20 B is deposited over the low-K IMD layer  16 B.  
         [0025]     Referring to  FIG. 2B , damascene structure openings e.g.,  22 C,  22 D, are formed according to a conventional photolithographic patterning and RIE etching process. Subsequently the organic ARC layer  20 B is removed according to a conventional wet etching process as indicated in  FIG. 2C .  
         [0026]     Referring to  FIG. 2C , following removal of the organic ARC layer  20 B, according to the present embodiment, an SiC or SiOC, more preferably an SiC barrier layer  18 B is blanket deposited over the low-K IMD layer  16 B to line the openings e.g.,  22 C and  22 D in addition to forming a capping (polishing stop) layer over the IMD layer  16 B, preferably formed at a thickness of about 100 Angstroms to about 300 Angstroms. Next, an ultra-thin liner layer  25 B of refractory metal such as Ta or Ti, more preferably tantalum (Ta), is blanket deposited over the SiC layer  18 B by conventional methods to a thickness of about 40 Angstroms to about 60 Angstroms.  
         [0027]     Referring to  FIG. 2D , the processes to complete the damascene structure previously discussed are carried out a metal filling process, for example blanket deposition of a copper seed layer followed by deposition of a copper ECD filling layer. Next, a copper CMP process is carried out to stop on the barrier/polishing stop layer  18 B to form copper filled damascenes e.g.,  26 C and  26 D.  
         [0028]     Referring to  FIG. 2E , following formation of the copper damascene structures e.g.,  26 C and  26  to complete the metallization layer, e.g., M 1  a second etch stop layer e.g.  28 B, for example formed of SiN is deposited to begin the formation of the next metallization level, e.g., M 2 .  
         [0029]     The various exemplary improvements in electrical properties of the improved copper damascene formation process including an SiC and/or SiOC capping and barrier layer are illustrated in  FIGS. 3A-3C . For example, referring to  FIG. 3A  is shown a relative contribution to RC delayer shown on the vertical axis as a function of barrier layer or capping layer thickness in Angstroms shown on the horizontal axis for copper damascene structures. For example, the results for a conventional barrier TaN layer are represented by Line A 1 , while the results for SiC and SiOC are represented respectively by Lines B 1  and C 1 . Both SiC and SiOC give superior results in terms of a lower contribution to RC delay compared to TaN having about the same dielectric constant of about 2.5.  
         [0030]     Referring now to  FIG. 3B , increasing current leakage for copper damascene structures having different barrier layers is represented on the vertical axis as a function of applied electric field in MV/cm, represented on the horizontal axis. The results for SiC (Line B 2 ) and SiOC (Line C 2 ) barrier layers indicate superior current leakage properties compared to TaN (Line A 2 ) barrier layers.  
         [0031]     Referring now to  FIG. 3C , is shown time to dielectric breakdown on the vertical as a function of applied stress field in units of MV/cm on the horizontal axis. Line A 3 , represents a linear response derived for TaN data measurements, e.g. data points  32 A, while line B 3 , represents a linear response derived from SiC data measurements, e.g.,  32 B and SiOC data measurements, e.g.,  32 C. The relative measurements represent the performance of copper damascene structures with barrier layers as well as capping layers formed according to embodiments of the present invention compared to TaN barrier layers according to the prior art.  
         [0032]     The preferred embodiments, aspects, and features of the invention having been described, it will be apparent to those skilled in the art that numerous variations, modifications, and substitutions may be made without departing from the spirit of the invention as disclosed and further claimed below.