Abstract:
A cache memory is provided which adjusts its response to addresses in accordance with the number of identical cache memory cards installed in the motherboard. Upon its installation in the motherboard a card is informed of its status as a master or a slave. As long as a slave is not installed the master responds to processor accesses over the entire address range of the computer. When a slave is installed a signal is sent to the master. Circuitry on the memory cards restricts the master response to half the address range. The slave being informed of its status restricts its response to the other half of the address range.

Description:
FIELD OF INVENTION 
     The present application relates to cache memories and more particularly cache memories that are expandable in modular units. 
     BACKGROUND OF THE INVENTION 
     Modularity of storage elements allows for addition of storage capacity to computer systems in segments. Mechanisms are generally provided in computer systems to determine the amount of installed main memory and to adjust memory addressing to accommodate changes in installed memory capacity. For instance, Brown et al., U.S. Pat. No. 3,898,631, issued on Aug. 5, 1975 and entitled &#34;Storage Indicator&#34;, discloses apparatus to sense and provide a digital indication of the number of installed segments where each segment is on a separate memory card. The insertion of each memory card into a connector in the memory board transmits a signal to a logic circuit that provides a binary count of the number of installed segments. 
     In certain situations, the system is not able to respond to information about changes in a memory&#39;s configuration. For instance, a computer system&#39;s memory hierarchy may consist of a level 1 (L 1 ) cache, a level 2 (L 2 ) cache, a main memory random access memory (RAM) and storage on a magnetic media. The L 2  cache resides between the L 1  cache and main memory to help speed up accesses on frequently requested data. While the system may be able to adjust its addressing to changes in the size of the RAM, it is difficult to do so with respect to a cache. Without a change in the addressing by the system processor the L 2  cache is unable to adapt to changes in its capacity without being provided with some &#34;intelligence&#34; to split memory accesses in accordance with L 2  cache capacity. One solution is to &#34;throw out&#34; the original L 2  cache unit and replace it entirely with a larger capacity cache unit that will appropriately access its added capacity. 
     BRIEF DESCRIPTION OF THE INVENTION 
     In accordance with the present invention, expansion of cache size is in modular units accomplished by addition of circuitry which enables each of the modular units to detect the presence or absence of other units in the cache unit and adjust their addressable ranges to appropriately respond to processor instructions. Insertion of a modular unit into the motherboard informs the unit of its status in the cache either as a master or a slave. A line in the motherboard interconnecting the modular units informs the other unit of its presence. Circuitry responsive to the presence or absence of the signals adjusts the range of addresses accepted by each of the modular units. 
     Therefore, it is an object of the present invention to provide for automatic adaption of modular units to changes in the quantity of installed storage. 
     It is another object of the present invention to provide for a cache memory which is expandable in modular units. 
     The foregoing and other objects, features and advantages of the present invention will be apparent from the following description of a preferred embodiment of the invention as illustrated in the accompanying drawings of which: 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of main memory and the L 1  and L 2  caches linked together by data and address busses; 
     FIG. 2 is a more detailed block diagram of the L 2  cache shown in FIG. 1; 
     FIG. 3 is a schematic representation of addressing circuitry in the controllers of the L 2  cache memory cards shown in FIG. 2; 
     FIG. 4 is a logic diagram of L 2  memory board circuitry for allocation of memory addresses; and 
     FIG. 5 is a timing diagram for a flush cycle of the L 2  cache. 
    
    
     DETAILED DESCRIPTION 
     Referring now to FIG. 1, a data buss 110 and an address and a control line buss 112 are shown linking the L 2  cache 116 to the L 1  cache 114,the random access main memory (RAM) 118 and the central processing unit (CPU) 120. The various memory units 114 to 118 respond to instructions of the CPU 120. The L 1  cache is the fastest and most costly per bit of the three memory units. The response of the L 2  cache is not quite as fast as that of the L 1  cache and its cost per bit is less. The RAM isthe slowest of the three units and cost the least per bit. 
     The sizes of the L 1 , L 2  and RAM memories are in inverse proportion to their speed. The L 2  cache stores a portion of the content of the RAM while the L 1  cache contains a portion of the entries of the L 2  cache. The disclosed arrangement is part of a personal computer system using an Intel Pentium microprocessor. The microprocessor configuration and requirements for a system using that microprocessor can be found in a manual entitled &#34;Pentium Family Users Manual Volume 1: Data Book&#34; published by the Intel Corporation in 1994. This manual is hereby incorporated by reference. 
     As shown in FIG. 2, the motherboard 200 contains two connectors 210 and 212for receipt of one or two L 2  cache memory cards 214 and 216. The cards214 and 216 are identical. They each contain three basic components, a controller 218, a TAG RAM 220 and a data RAM 222. The data RAM 222 stores the data and instructions of the CPU 120. The TAG RAM 220 stores address bits and operational state of data in the storage elements of the data RAM222. The controller 218 uses the information in the TAG RAM to determine whether the data in the data RAM 222 can be transmitted to the CPU 120. 
     Referring to FIG. 3, of the 32-bit CPU address word 310, bits 3 to 29 are pertinent to the operation of the L 2  cache. Bits 0 to 2 are for a byte address in a word. The L 2  cache is addressable only down to the word level so bits 0 to 2 are not pertinent. Bits 30 and 31 are for addresses above the gigabyte range which are not used in the present system. Therefore bit 29 is the highest order bit in the system. 
     Referring to both FIGS. 2 and 3, controller 218 addresses the data RAM 222 on line 230 with bits 3 to 20. Bits 5 to 20 select a 32 byte line of the data RAM 222 and bits 3 and 4 select the requested 8 byte word of that line. The CPU 120 also addresses the TAG RAM 220 with bits 5 to 20 of the address 310. This reads a 12 bit word 312 out of the TAG RAM which includes the high order address bits 21 to 29 of data stored in RAM 222. Acompare circuit 314 in the controller 218 determines if there is a match between the stored and requested address bits. If there is a match, a gate316 transmits state bits 0 to 2 of the TAG RAM word 312 to other circuitry to determine status of data stored in RAM 222. If the access in the data RAM 222 is the requested address, the status bits determine the accessibility of that location to a read or write operation by the CPU 120. When bit 0 is a &#34;0&#34; the location is read only. When it is &#34;1&#34; it is writable. When bits 1 and 2 are &#34;1, 1&#34; respectively, the data are modified(M) from the copies of the data in the RAM. When they are &#34;0, 1&#34; the data are exclusive (E) and can be modified. When bits 1 and 2 are &#34;1, 0&#34; the data are shared (S) and cannot be modified and when they are &#34;0, 0&#34; the data are invalid. 
     When there is only one memory card 214 in the motherboard 200, that card must respond to address requests over the entire range addressed by bits 3to 29. However, when the second memory board 216 is added, the first board 214 responds to only half the address range. When address bit 21 is &#34;0&#34; the data RAM 222 on card 214 is to be accessed. When address bit 21 is &#34;1&#34;the data RAM in memory card 216 is to be accessed. 
     In accordance with the present invention, means are provided, as shown in FIGS. 2 and 4, to permit changes in accessing in the L 2  cache with changes in the number of cache memory modules installed in the motherboard. First referring to FIG. 2, a line referred hereinafter as the &#34;buddy&#34; line 224 is provided that goes through the motherboard 200 and theconnectors 210 and 212 between the controllers on the two modules 214 and 216. Further, the controllers of the modules are provided with different one bit binary indicia 226 and 228 from the motherboard 200 to denote the status of the memory card either as a master or a slave. These signals arethe master/not master signals (M/NM). The master 214 receives a binary &#34;1&#34; M/NM signal from the motherboard through connector 210 and the slave 216 receives a binary &#34;0&#34; M/NM signal from the motherboard 200 through connector 212. 
     Now referring to FIG. 4, it will be seen that the controllers on both memory cards 214 and 216 contain circuitry responsive to the binary M/NM signals 226 and 228, the address bit 21, and a reset command from the system, to set the address range of the cards. On the slave card, enablement of the drivers of the data RAM 222 is always limited to responding to half of the address range. When the address bit 21 is &#34;1&#34; that bit in combination with the inverted &#34;0&#34; M/NM signal enables gate 414. 
     On the master card, gate 412 enables the data RAM drivers to pass any address in the entire address range unless there is a slave card 216 in socket 212. More specifically, without a slave card in socket 212 of the motherboard, the output line of latch 416 or &#34;single&#34; line is a &#34;1&#34; which in combination with the &#34;1&#34; M/NM signal enables AND gate 419. When there is a slave card in the socket 212, a compare output signal is provided to latch 416 by comparator 418 resulting in a &#34;0&#34; output on the &#34;single&#34; lineof latch 416 disabling the gate 419. 
     The comparator 418 responds to signal generators 420 on both cache memory cards. The signal generators are both activated on the falling edge of thesystem reset pulse to generate synchronized pulse sets. On the slave card 216 the binary &#34;0&#34; M/NM signal 226 sets the bidirectional (BiDi) circuit 422 through AND gates 425 and 426 to transmit the pulse set from its signal generator 416 to the master card 214. The binary &#34;1&#34; M/NM signal supplied to the master card 214 allows the BiDi circuit 422 on the master card to receive the pulse set transmitted from the slave card. When synchronized pulse sets from both the master and slave are provided to thecomparator circuit 418 on the master it produces a compare output. The compare output in combination with the cache-reset signal latches latch 416 dropping the &#34;single&#34; line disabling the gate 419. The master card gate 424 is enabled by a binary &#34;0&#34; in address bit position 21 in combination with a binary &#34;1&#34; M/NM signal allowing enablement of the drivers of the data RAM irrespective of the state of gate 419. Therefore, the drivers are always enabled for low end addresses. 
     The buddy line can be used for other purposes. For instance, it is also used during a flush operation where the controller for the RAM 118 directsthe L 1  and L 2  caches to transfer to the RAM 118 modified data (changed from the copy of the data in RAM 118). As shown in FIGS. 4 and 5,when the master receives the start flush command, AND gates 428 and 425 activate the BiDi 422 to allow the flush control circuitry 432 on the master to drive the buddy line 224 active. This sends a &#34;buddy&#34; signal to the slave from the flush control logic 432 of the master. The buddy signalinhibits the flush operation by the flush control logic 432 in the slave while the master performs its flush process. When master finishes its flush process on clock cycle 6 it allows the buddy line to go inactive for1 cycle and then through AND gate 426 releases the buddy line in cycle 7. When the slave senses the buddy line as inactive it drives the buddy line active on cycle 8. When the slave finishes its flush process, it drives the buddy line inactive. The master senses the buddy line 224 as being inactive and provides an L 2  complete signal to the CPU. 
     Above we have described one embodiment of the invention in which either oneor two identical memory cards can constitute a cache. A number of changes can be made in this embodiment without departing from the invention. For instance, the memory could use different designs for master and slave cards. In such a case the buddy line could be used to transmit informationfrom the slave to the master about the configuration of the slave. Also provisions could be made for expansion to more than two cards by using more than one buddy line and multiple digit binary numbers to code the cards. Therefore, it will be understood by those skilled in the art that the above and other changes in form and details may be made without departing from the spirit and scope of the invention.