Abstract:
The present invention provides an improved Chua&#39;s circuit providing current mode operation, access to all state variables, minimum use of grounded passive elements, and freedom from passive component matching comprising a dual output current conveyer based inductor having one grounded terminal, a capacitor connected across the second terminal of said inductor, a resistor having one terminal connected to the second terminal of said inductor, the second terminal of said resistor connected to one terminal of a second capacitor the other end of which is grounded, and a pair of dual output current conveyers connected together to form a 2-terminal negative resistance having one terminal connected to ground and the second terminal connected to the second terminal of said resistance.

Description:
RELATED APPLICATION 
   This application is a continuation of Ser. No. 10/985,327 filed Nov. 10, 2004, the entire disclosure of which is incorporated by reference herein. 

   FIELD OF THE INVENTION 
   The invention relates to Chua&#39;s circuits, and more particularly, to a Chua&#39;s circuit using a Dual Output Current Conveyer (DO-CCII), and to a Chua&#39;s circuit using a Multiple Output Current Conveyor (MO-CCII) for generating a hyper-chaotic circuit. 
   BACKGROUND OF THE INVENTION 
     FIG. 1  shows a generalized Chua&#39;s circuit that has a parallel combination of a capacitor C 2 , a Chua&#39;s diode NR 1  connected to an L-C tank circuit that includes a second capacitor C 1  connected in parallel with a serially connected inductor L 1 . In addition, a first voltage V 1  is defined across capacitor C 1  and a second voltage V 2  is defined across capacitor C 2  with the positive orientation of voltages V 1  and V 2  both being at the positive end of the corresponding capacitor. Finally, there is a linear resistor R 1  connected between the positive terminals of each capacitor. 
   In a typical configuration, the non-linear curve is piece-wise linear with symmetrical slope discontinuities around the current axis. It satisfies the following equation: I R =G a V R +(½) (G a −G b ) {|v R +B P |−|v R −B p |}, where G a  and G b  are the slopes of respective linear portions of the piece-wise linear current/voltage curve characterizing the nonlinear resistor, and B p  is the absolute value of the two voltage points at which discontinuities in the current/voltage curve lie, as shown in  FIG. 2 . The circuit has a circuit driving subsystem, an L-C tank circuit, and a response subsystem with a parallel combination of a capacitor and a non-linear resistor interconnected through a resistor. 
   By choosing values of R, L, C 1 and C   2 , the circuit can operate in different operating regions, for example, the double scroll region. Herein, a Chua&#39;s circuit can be made that will oscillate chaotically or quasi-periodically. Given a specified physical configuration, a specified initial state specified by V 1 , V 2  and I L , the voltage across the capacitors C 1  and C 2 , and the current through the inductor L, the evolution of the Chua&#39;s circuit is deterministic, but chaotic. That is, any Chua&#39;s circuit with the same physical parameters and initial conditions will follow the same course of states over time, and this course will repeat itself over a very long period. However, to an observer it looks mainly like noise. Also, such a system&#39;s trajectory is sensitive to initial conditions. In addition, the power spectral density function is spread over a wide range of frequencies, with the peak frequency of the fundamental being governed by the L-C tank circuit. 
   Due to its simple circuitry and ability to demonstrate most well known routes to chaos, a Chua&#39;s Circuit and Chua&#39;s Oscillator (CC/CO) are an active topic of research in the study of non-linear dynamic circuits and systems. Recently, there has been an increasing interest in designing inductor-less Chua&#39;s circuits and Chua&#39;s oscillators (CC/CO). Moreover, due to its advantages, the attainability of all the three state variables of a CC/CO is also attracting the designers. Simultaneously, literature is also witnessing the shift of analog integrated circuit designs from voltage mode processing to current-mode processing (CMP). A number of chaotic circuits have been implemented using current-mode active building blocks. The Dual-Output Current Conveyor (DO-CCII) is also emerging as a versatile block to implement current-mode circuits. 
   To improve the performance of the circuit, different researchers have done extensive research. A paper by Kennedy M. P. (Kennedy M. P., ‘Robust op-amp realization of Chua&#39;s circuit’, Frequenz, 1992, 46, pp. 66–80) suggests a Chua&#39;s circuit using off the shelf components. Further, in another research paper by Torres, L. A. B. and Aguirre, L. A. (Torres, L. A. B. and Aguirre, L. A., Inductorless Chua&#39;s circuit, Electron. Lett., 2000, 36, (23), pp. 1915–1916) report a Chua&#39;s circuit using an operational amplifier to generate a Chua&#39;s oscillation at a very low frequency for bio-medical operations. 
   In a design proposed by Morgul,  0 . (Morgul, O., ‘Inductorless realization of Chua&#39;s oscillator’, Electron. Lett., 1995, 31, pp. 1403–1404) synthetic inductors using op-amps were used along with the operational amplifier, thereby making the design suitable for monolithic implementation. 
   Senani R. and Gupta S. S. (Senani R. and Gupta S. S., ‘Implementation of Chua&#39;s chaotic circuit using current feedback op-amps’, Electron. Lett., 1998, 34, (9), pp. 829–830) proposed a Chua&#39;s circuit using a Current Feedback Operational Amplifier (CFOA), thus making available the third state variable through the inductor (i L ). 
   In another architecture designed by Elwakil A. S. and Kennedy M. P. (Elwakil A. S. and Kennedy M. P., ‘Improved implementation of Chua&#39;s chaotic oscillator using current-feedback op-amp.’, IEEE Trans. CAS-I, 2000, 47, (1), pp. 76–79) the CFOA was efficiently used in the Chua&#39;s circuit to provide a higher bandwidth of the chaotic signal with a buffered output of one state variable. 
   All the above architectures individually provide advantages of a Chua&#39;s circuit, but so far, there is no circuit that simultaneously provides: current mode operation; use of minimum grounded passive elements; availability of all the state variables; availability of two state variables in the form of current which can be used to further generate other complex chaotic circuits; a circuit free from passive component matching; use of lesser active components as compared to that represented by  FIG. 2 ; and generation of a reduced hardware higher order chaotic circuit (also called a hyper-chaotic circuit) using one of the available currents mentioned above. Thus, there is a need to develop a circuit that can provide all of these simultaneously. 
   A Chua&#39;s circuit, apart from being a device for demonstrating, studying and modeling a chaotic real world system, has been proposed to generate a hyper-chaotic circuit (T. Kapitaniak, L. O. Chua and G. Zhong, ‘Experimental Hyperchaos in Coupled Chua&#39;s Circuits’, IEEE Trans. CAS-I, Vol 41, No.7, July 1994). Referring to  FIG. 3 , it has been shown in (T. Kapitaniak, L. O. Chua and G. Zhong, ‘Experimental Hyperchaos in Coupled Chua&#39;s Circuits’, IEEE Trans. CAS-I, Vol 41, No.7, July 1994) that a Chua&#39;s circuit ( 100 ) may be coupled to a similar Chua&#39;s circuit ( 101 ) such that the non-grounded terminal of the inductor is connected to the input of a voltage buffer ( 10 ) whose output is connected to one of the terminals of a controlling resistor ( 11 ), and another end of the controlling resistor is connected to the non-grounded terminal of another Chua&#39;s circuit ( 101 ). The system coupling is achieved by interconnecting n Chua&#39;s circuit in the fashion described above, and the last Chua&#39;s circuit of the ring is either connected to the first Chua&#39;s circuit ( 100 ) or is left open. This type of coupling results in the following cases: 
   For the value of the controlling resistor greater than a specific value (called a threshold value), all the Chua&#39;s circuits will synchronize with each other. This value of the controlling resistor depends on the number of Chua&#39;s circuits used in the chain. During this state, the curve between the state variable of one Chua&#39;s circuit to the corresponding state variable in another Chua&#39;s circuit of the chain will be a straight line. 
   If the value of the controlling resistor is less than the specific value (called a threshold value), the Chua&#39;s circuits will loose synchronization with each other and the system will undergo a state of hyper-chaos, which is more sensitive to the initial condition. This value of the controlling resistor depends on the number of Chua&#39;s circuits used in the chain. During this state the curve between the state variable of one Chua&#39;s circuit to the corresponding state variable in another Chua&#39;s circuit of the chain will not be a straight line. 
   With such a proposal, a monolithic implementation of the hyper-chaotic circuit can be achieved by using any of the above-mentioned variations of the Chua&#39;s circuit (i.e., prior art Chua&#39;s circuits can be used to generate the hyper-chaotic circuit using the above described scheme). However, the use of any of these circuits will not only add to the disadvantage of those proposed Chua&#39;s circuits, but also one voltage buffer and one floating resistor per coupling is required, which in turn, makes the final circuit bulky and inefficient in terms of power consumption. 
   SUMMARY OF THE INVENTION 
   An object of the invention is to prevent the above drawbacks associated with prior art Chua&#39;s circuits. 
   Another object of the invention to design a Chua&#39;s circuit using four Dual Output Current Conveyors (DO-CCII), two grounded resistors, three grounded capacitors and three floating resistors. 
   Yet another object of the invention is to use a minimum number of grounded elements as compared to those used in the prior art. 
   A further object of the invention is to have voltage across the inductor in the form of current for current mode processing of the system without any extra hardware requirement. 
   Another object of the invention is to derive a Chua&#39;s diode using two grounded resistors, two floating resistors and two MO-CCIIs. 
   Yet another object of the invention is to derive a Chua&#39;s diode using two grounded resistors, two floating resistors and two DO-CCIIs. 
   A further object of the invention is to achieve current through the z-terminal of a DO-CCII and a MO-CCII used in designing non-linear resistors. 
   Yet another object of the invention is to design a Chua&#39;s circuit using a Multiple Output Current Conveyor. 
   A further object of the invention is to achieve a grounded controlling resistor for a hyper-chaotic system designed by the coupling of a Chua&#39;s circuit, which is done by using the above derived current of the voltage across an inductor. 
   According to one embodiment, an improved Chua&#39;s circuit is provided based upon another embodiment. The CCII presented in (Seguin F. and Fabre A., ‘New second generation current conveyor with reduced parasitic resistance and band-pass filter application’, IEEE Trans. CAS-I, 2001, 48,(6), pp. 781–785) is modified to achieve a DO-CCII and a MO-CCII as shown in  FIG. 4 . The schematic diagram of the MO-CCII and DOCCII used to further design the Chua&#39;s chaotic circuit and its coupling is shown in  FIGS. 6A and 6B . 
   According to another embodiment, the above DO-CCII based Chua&#39;s circuit can be implemented using a MO-CCII based Chua&#39;s circuit, as shown in  FIG. 5 . 
   To achieve the above objectives, the present invention provides an improved Chua&#39;s circuit providing current mode operation, access to all state variables, minimum use of grounded passive elements, and freedom from passive component matching. The Chua&#39;s circuit comprises a multiple output current conveyer based inductor having one grounded terminal, a capacitor connected across the second terminal of the inductor, and a resistor having one terminal connected to the second terminal of the inductor. The second terminal of the resistor may be connected to one terminal of a second capacitor. The other end of the second capacitor may be grounded. A pair of multiple output current conveyers may be connected together to form a 2-terminal negative resistance having one terminal connected to ground and the second terminal connected to the second terminal of the resistance. The multiple output current conveyers may be the multiple output (second generation) current conveyers (MO-CCII). 
   The inductor comprises two multiple output current conveyers having their x terminals grounded through resistors, a capacitor having one terminal grounded and its second terminal connected to the terminal z P1  of the second multiple output current conveyer, and in parallel to the y terminal of the first multiple output current conveyer. The y terminal of the second multiple output current conveyers and the terminal z N1  of the first multiple output current conveyers are joined together, which acts as one of the terminals of a simulated grounded inductance. 
   The 2-terminal negative resistance circuit comprises two multiple output current conveyers having their x terminals grounded through resistors, and their y terminals connected together and to the terminals z P1  of both the multiple output current conveyers through two different resistors. 
   An improved Chua&#39;s circuit may provide current mode operation, access to all state variables, minimum use of grounded passive elements, and freedom from passive component matching. The Chua&#39;s circuit comprises a dual output current conveyer based inductor having one grounded terminal, a capacitor connected across the second terminal of the inductor, and a resistor having one terminal connected to the second terminal of the inductor. The second terminal of the resistor may be connected to one terminal of a second capacitor, the other end of which is grounded. A pair of dual output current conveyers may be connected together to form a 2-terminal negative resistance having one terminal connected to ground, and the second terminal connected to the second terminal of the resistance. The dual output current conveyer may be a dual output (second generation) current conveyer. 
   The inductor comprises two dual output current conveyers having their x terminals grounded through resistors, a capacitor having one terminal grounded and its second terminal connected to the terminal z +  of the second dual output current conveyer and in parallel to the y terminal of the first dual output current conveyer. This is while the y terminal of the second dual output current conveyers and the terminal z −  of the first dual output current conveyers are joined together, and which acts as one of the terminals of a simulated grounded inductance. 
   The 2-terminal negative resistance circuit comprises two dual output current conveyers having their x terminals grounded through resistors, and their y terminals connected together and to the terminals z +  of both dual output current conveyers through two different resistors. 
   An improved Chua&#39;s circuit for use in a hyper-chaotic circuit comprising a plurality of the Chua&#39;s circuit symmetrically coupled together enables a monolithic implementation of a hyper-chaotic circuit. 
   A method for improving a Chua&#39;s circuit to provide a current mode operation, access to all state variables, minimum use of grounded passive elements, and freedom from passive component matching is provided. The method may comprise the steps of simulating a grounded inductor using a multiple output current conveyer, connecting a capacitor connected across the second terminal of the inductor, and connecting one terminal of a resistor to the second terminal of the inductor. The second terminal of the resistor is connected to one terminal of a second capacitor, the other end of which is grounded. The method further includes providing a 2-terminal negative resistance device using a pair of multiple output current conveyers. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will now be described with reference to the accompanying drawings. 
       FIG. 1  is a schematic diagram of a generalized Chua&#39;s circuit diagram according to the prior art. 
       FIG. 2  is a plot showing the response of a non-linear resistor (Chua&#39;s diode) according to the prior art. 
       FIG. 3  is a schematic diagram showing the coupling of Chua&#39;s circuit according to the prior art. 
       FIG. 4  is a schematic diagram showing implementation of a MO-CCII according to the invention. 
       FIG. 5  is block diagrams of a DO-CCII and a MO-CCII according to the invention. 
       FIG. 6A  is a schematic diagram of the DO-CCII based inductor according to the invention. 
       FIG. 6B  is a schematic diagram of the MO-CCII based inductor according to the invention. 
       FIG. 7A  is a schematic diagram of the DO-CCII based non-linear negative resistor according to the invention. 
       FIG. 7B  is a schematic diagram of the MO-CCII based non-linear negative resistor according to the invention. 
       FIG. 8  is a plot showing the characteristic of a non-linear negative resistor according to the invention. 
       FIG. 9A  is a schematic diagram showing implementation of a Chua&#39;s diode using the DO-CCII according to the invention. 
       FIG. 9B  is a schematic diagram showing implementation of a Chua&#39;s diode using the MO-CCII according to the invention. 
       FIG. 10  is a schematic diagram of a Chua&#39;s circuit using the DO-CCII according to the invention. 
       FIG. 11  is a schematic diagram of a Chua&#39;s circuit using the MO-CCII according to. the invention. 
       FIG. 12  is a plot showing a Double Scroll attractor derived from the MO-CCII based Chua&#39;s Circuit according to the invention. 
       FIG. 13  is a schematic diagram of a MO-CCII based hyper-chaotic circuit according to the invention. 
       FIG. 14  is a plot showing simulation results of a hyper-chaotic circuit validating the theory according to the invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The invention provides a Chua&#39;s circuit using a Dual Output (second-generation) Current Conveyer (DO-CCII) as one embodiment. The invention also provides implementation of a Chua&#39;s circuit using a Multiple Output Current Conveyor (MO-CCII), and provides a hyper-chaotic circuit using the Multiple Output Current Conveyor. 
     FIG. 3  shows the coupling of n Chua&#39;s circuits to achieve synchronization. The system thus formed is used to solve the following set of equations: 
   
     
       
         
           
             
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   The dynamics of the system is dependent on the controlling resistor R K . This aspect has been discussed in the prior art. 
     FIG. 4  shows the implementation of a Multiple Output Current Conveyor which has been designed by modifying the current conveyor proposed in (Seguin F. and Fabre A., ‘New second generation current conveyor with reduced parasitic resistance and band-pass filter application’, IEEE Trans. CAS-I, 2001, 48,(6), pp. 781–785). Herein, one additional output terminal z− is taken by using current mirrors. This scheme then corresponds to implementation of a DO-CCII. Further, two additional outputs, one similar in behavior to terminal z+ and one similar in behavior to terminal z− have been added. The final scheme as shown in the figure forms a MO-CCII. 
     FIG. 5  shows a schematic block diagram of a DO-CCII and a MO-CCII. The DO-CCII has six terminals. Terminals VSS and VDD are the supply voltage terminals while the terminals x, y, z+ and z− allow different voltages and currents to flow in and out of the circuit. 
   A basic DO-CCII has a current mirror circuit that reflects the current of terminal x in the terminal z+. The magnitude of the current through in the terminal z− and the current through the terminal z+ is the same except for their directions. Also, the voltages at the terminals x and y are the same and the current through the terminal y is zero. This can be represented in the following equations:
 
v x =v y   (1)
 
i y =0  (2)
 
i z+ =i x   (3)
 
 i   z−   =−i   x   (4)
 
   The subscripts with currents I and voltages V represent currents and voltages in the respective terminals of the DO-CCII. 
   The MO-CCII has eight terminals. Terminals VSS and VDD are the supply voltage terminals while the terminals x, y, zp 1 , zp 2 , zn 1  and zn 2  allow different voltages and currents to flow in and out of the circuit. 
   A basic MO-CCII has a current mirror circuit that reflects the current of terminal x in the terminal zp 1 . The magnitude of the current through the terminal zn 1  and the current through the terminal zp 1  is the same except for their directions. Also, the voltages at the terminals x and y are the same and the current through the terminal y is zero. Further, the terminals zp 1  and zp 2  show similar behavior in terms of current movement. Similarly, the terminals zn 1  and zn 2  show similar behavior. This can be represented in following equations:
 
v X =v Y   (1)
 
i y =0  (2)
 
i zp1 =i x   (3)
 
 i   zp2   =−i   X   (4)
 
i zn1 =i X   (5)
 
 i   zn2   =−i   X   (6)
 
   The subscript with the currents I and voltages V represent currents and voltages in the respective terminals of the MO-CCII. 
   These characteristics of the DO-CCII and the MO-CCII can be used to form inductive properties as discussed below.  FIG. 6A  shows a DO-CCII based inductor. This inductor has two DO-CCIIs D 3  and D 4  having their x terminals grounded through the resistors R L1 , R L2 . A capacitor CL has its one terminal grounded and its second terminal coupled to the terminal z +  of the DO-CC II D 3  and to the terminal y of the DO-CCII D 4 . The terminal z −  of D 4  and the terminal y of D 3  are joined together to connect the one terminal of the input supply. 
   When a voltage v is applied at node  1 , a similar voltage is induced at node  2  that is at the terminal x of D 3  according to equation  1  of the DO-CCII. This results in current i 2  through the resistor R L2  given by i 2 =v/R L2 . 
   Because of the relations 3 and 4, current through terminal x is reflected at terminals z −  and z + , accordingly, thus producing a voltage across the capacitor C L  which is seen by the y terminal of D 4  and is given by the following: 
   
     
       
         
           
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   The voltage V 3  is then induced at the terminal x of D 4  according to relation 1, thus causing a current i 5  through the resistor R L1  that is then reflected in the terminals z+ and z− of D 4 . The current i 5  through the resistor R L1  can be given as follows: 
   
     
       
         
           
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                   v 
                   
                     
                       C 
                       L 
                     
                     ⁢ 
                     
                       R 
                       L2 
                     
                     ⁢ 
                     
                       R 
                       L1 
                     
                   
                 
                 ⁢ 
                 
                   ⅆ 
                   t 
                 
               
             
           
         
       
     
   
   From  FIG. 2  it is clear that the current i 5 =i L  because of relation 2, thus the following equation can be written: 
   
     
       
         
           
             i 
             L 
           
           = 
           
             ∫ 
             
               
                 v 
                 
                   
                     C 
                     L 
                   
                   ⁢ 
                   
                     R 
                     L2 
                   
                   ⁢ 
                   
                     R 
                     L1 
                   
                 
               
               ⁢ 
               
                 ⅆ 
                 t 
               
             
           
         
       
     
   
   From above, the following equation can be written: 
   
     
       
         
           
             
               C 
               L 
             
             ⁢ 
             
               R 
               L1 
             
             ⁢ 
             
               R 
               L2 
             
             ⁢ 
             
               
                 ⅆ 
                 
                   i 
                   L 
                 
               
               
                 ⅆ 
                 t 
               
             
           
           = 
           v 
         
       
     
   
   The characteristic equation of an inductor is given by the following: 
   
     
       
         
           
             L 
             ⁢ 
             
               
                 ⅆ 
                 
                   i 
                   L 
                 
               
               
                 ⅆ 
                 t 
               
             
           
           = 
           v 
         
       
     
   
   Upon comparing the above two equations we get the following:
 
L=C L R L1 R L2 
 
   Thus, it can be said that the circuit shown is  FIG. 6A  is equivalent to an inductor having a value determined by L=C L R L1 R L2 . Further, it is important to note that the circuit provides terminals z+ and z− of D 4  and D 3 , respectively, to tap current flowing through the inductor and the voltage across capacitor (of a tank circuit) in the form of current. More specifically, since D 3  provides voltage across the capacitor in the form of current, current through the inductor is available at the terminal z +  of D 4 . 
   Similar results can be achieved by using the MO-CCII by replacing terminal x of the DO-CCII by terminal x of the MO-CCII, terminal y of the DO-CCII by terminal y of the MO-CCII, terminal z+ of the DO-CCII by terminal z 1 + of the MO-CCII, terminal z− of the DO-CCII by terminal z 1 − of the MO-CCII, terminal VDD of the DO-CCII by terminal VDD of the MO-CCII, terminal VSS of the DO-CCII by terminal VSS of the MO-CCII, and the rest of the terminals of the MO-CCII, i.e., terminals z 2 + and z 2 − remain floating. Thus, the MO-CCII based inductor is also formed as shown in  FIG. 6B . 
     FIG. 7A  shows a schematic block diagram of the DO-CCII based negative resistor. The DO-CCII has the terminal x connected to a resistance R 3  whose other terminal is connected to ground and has a resistance R 1  connected between its terminals z+ and y. 
   A Dual Output Current Conveyer based non-linear device basically works in three different regions as depicted in the current versus voltage plot shown in  FIG. 8 . The region of operation can be classified as follows. 
   A negative saturation region is the region when the input voltage to this non-linear device is highly negative with respect to ground, while the positive saturation region when the input voltage to this non-linear device is highly positive with respect to ground. The input voltage is the voltage applied at the y terminal of the non-linear device described in  FIG. 7A . The linear region is when the input voltage to this non-linear device is comparable to the supply voltage. 
   In the negative or positive saturation regions when the input voltages are either highly negative or positive, the terminal z +  of the DO-CCII assumes a constant voltage (negative or positive, respectively) thus, allowing a current to flow through the resistance R 3  exhibiting positive resistive properties beyond a Break point (Bp), as shown in  FIG. 8 . 
   In the linear region when the input voltage is comparable to the supply voltage, the current flowing inside the terminal z+equals current through the terminal x according to the relation  3 . Also, the voltage at the terminal x and the voltage at the terminal y are similar according to the relation  1  for a DO-CCII. Thus, current through the input supply terminal i in  is equal to the current through the resistor R 3 , and hence, the current i x  through the terminal x. Thus, the voltage at the terminal y can be given as: v y =−i x *R 3  or i x /v y =−1/R 3 =m 1 , where m 1  is the slope in the linear region. 
   Due to its linearity in the three regions, positive linearity in the positive and negative saturation regions and negative linearity in the linear region, the non-linear device operates as a non-linear resistor with positive resistance at the positive and negative saturation region and negative resistance in the linear region. Hence, the DO-CCII of  FIG. 7A  exhibits a negative resistance in the linear region as shown in the corresponding current versus voltage plot in  FIG. 8 . 
   Similar results can be achieved by using the MO-CCII by replacing terminal x of the DO-CCII by terminal x of the MOCCII, terminal y of the DO-CCII by terminal y of the MO-CCII, terminal z+ of the DO-CCII by terminal zp 1  of the MO-CCII, terminal z− of the DO-CCII by terminal zn 1  of the MO-CCII, terminal VDD of the DO-CCII by terminal VDD of the MO-CCII, terminal VSS of the DO-CCII by terminal VSS of the MO-CCII, and the rest of the terminals of the MO-CCII, i.e., terminals zp 2  and zn 2  remain floating. Thus, the MO-CCII based negative resistor is also formed, as shown in  FIG. 7B . 
     FIG. 9A  shows two DO-CCIIs connected in parallel to achieve a variable slope in the linear region and a specified break point as required for the Chua&#39;s circuit. The total conductance of the parallel combination of the two DO-CCIIs is a linear addition of the individual conductance of each DO-CCII. Thus, the I-V characteristics of the parallel combination exhibit a variable slope, as shown in  FIG. 2 . Note that this type of non-linear resistor is also called a Chua&#39;s diode. 
   Similar results can be achieved by using the MO-CCII by replacing terminal x of the DO-CCII by terminal x of the MO-CCII, terminal y of the DO-CCII by terminal y of the MO-CCII, terminal z+ of the DO-CCII by terminal zp 1  of the MO-CCII, terminal z− of the DO-CCII by terminal zn 1  of the MO-CCII, terminal VDD of the DO-CCII by terminal VDD of the MO-CCII, terminal VSS of the DO-CCII by terminal VSS of the MO-CCII, and the rest of the terminals of the MO-CCII, i.e., terminals zp 2  and zn 2  remain floating. Thus, the MO-CCII based Chua&#39;s diode is also formed, as shown in  FIG. 9B . 
   Without limiting the scope of the invention to the discussed embodiment and the values thereof, the invention will now be discussed with reference to the circuit shown in  FIG. 10 . A person skilled in art will appreciate that the invention can also be practiced with other embodiments without deviating from the concept described below. 
     FIG. 10  shows a schematic block diagram of a Chua&#39;s circuit according to one embodiment of the invention. The circuit shown is basically a current mode implementation of the Chua&#39;s circuit using a Dual Output second generation Current Conveyor. The Chua&#39;s chaotic circuit according to the invention comprises four Dual Output Second Generation Current Conveyors D 1 , D 2 , D 3  and D 4 . The DO-CCIIS D 3  and D 4  form an inductor as described in  FIG. 6A , and the DO-CCIIS D 1 , D 2  form a non-linear component as described in the  FIG. 9A . The capacitors C 1  and C 2  are the first and second energy storing elements of the Chua&#39;s circuit, and are connected to terminals y of D 3 , D 2  respectively. Resistor R is the passive component of the Chua&#39;s circuit and is connected to the terminals y of D 1  and D 2 . The terminals y of D 1  and D 2  are coupled together and the terminals x of D 1  and D 2  are connected to ground through the resistive loads R 4  and R 3 . The terminals z +  of D 1  and D 2  are connected to their terminals y through the resistances R 1  and R 2  and the terminals y of D 2  and D 1  are connected, as shown in  FIG. 9A . 
   For this Chua&#39;s circuit, the equation can be written as follows: 
   
     
       
         
           
             
               C 
               2 
             
             ⁢ 
             
               
                 ⅆ 
                 
                   V 
                   2 
                 
               
               
                 ⅆ 
                 t 
               
             
           
           = 
           
             
               
                 1 
                 R 
               
               ⁢ 
               
                 ( 
                 
                   
                     V 
                     1 
                   
                   - 
                   
                     V 
                     2 
                   
                 
                 ) 
               
             
             - 
             
               g 
               ⁡ 
               
                 ( 
                 
                   V 
                   1 
                 
                 ) 
               
             
           
         
       
     
     
       
         
           
             
               C 
               1 
             
             ⁢ 
             
               
                 ⅆ 
                 
                   V 
                   1 
                 
               
               
                 ⅆ 
                 t 
               
             
           
           = 
           
             
               
                 1 
                 R 
               
               ⁢ 
               
                 ( 
                 
                   
                     V 
                     2 
                   
                   - 
                   
                     V 
                     1 
                   
                 
                 ) 
               
             
             + 
             
               i 
               L 
             
           
         
       
     
     
       
         
           where 
           , 
           
             
 
           
           ⁢ 
           
             
               g 
               ⁡ 
               
                 ( 
                 
                   V 
                   1 
                 
                 ) 
               
             
             = 
             
               
                 
                   m 
                   0 
                 
                 ⁢ 
                 
                   V 
                   1 
                 
               
               + 
               
                 
                   1 
                   2 
                 
                 ⁢ 
                 
                   
                     ( 
                     
                       
                         m 
                         0 
                       
                       - 
                       
                         m 
                         1 
                       
                     
                     ) 
                   
                   ⁡ 
                   
                     [ 
                     
                       
                          
                         
                           
                             V 
                             1 
                           
                           + 
                           
                             B 
                             p 
                           
                         
                          
                       
                       - 
                       
                          
                         
                           
                             V 
                             1 
                           
                           - 
                           
                             B 
                             p 
                           
                         
                          
                       
                     
                     ] 
                   
                 
               
             
           
         
       
     
   
   The value of m 0  and m 1  are determined by resistor values R 1 , R 2 , R 3 , R 4  and the supplies VSS 1 , VSS 2 , VDD 1 , VDD 2 . 
     FIG. 12  shows the results obtained by simulations of the above Chua&#39;s circuit for values selected as follows. This is called the double scroll-operating region. 
   Non Linear resistance: 
   R 1 =190 Ω, R 2 =25.6 kΩ, R 3 =2 kΩ, R 4 =2.2 kΩ; and VSS 1 =−7V, VDD 1 =7.8V, VSS 2 =−7.8V, VDD 2 =7V. 
   Inductor: 
   CL=100 nF, R L1 =400 Ω, R L2 =400 Ω. 
   Other components: 
   C 1 =100 nF, C 2 =10 nF, R=1.550 k. 
   Similar results can be achieved by using the MO-CCII by replacing terminal x of the DO-CCII by terminal x of the MOCCII, terminal y of the DO-CCII by terminal y of the MOCCII, terminal z+ of the DO-CCII by terminal z 1 + of the MOCCII, terminal z− of the DO-CCII by terminal z 1 − of the MO-CCII, terminal VDD of the DO-CCII by terminal VDD of the MO-CCII, terminal VSS of the DO-CCII by terminal VSS of the MO-CCII, and the rest of the terminals of the MO-CCII, i.e., terminals z 2 + and z 2 − remain floating. Thus, the MO-CCII based Chua&#39;s circuit is also formed, as shown in  FIG. 11 . 
   As described earlier, the Chua&#39;s circuit can be coupled by using one voltage buffer and one floating resistor using the scheme presented in  FIG. 2 . It is actually solving the following equations of the system: 
   
     
       
         
           
             
               C 
               1 
             
             ⁢ 
             
               
                 ⅆ 
                 
                   v 
                   
                     C 
                     1 
                   
                   
                     ( 
                     1 
                     ) 
                   
                 
               
               
                 ⅆ 
                 t 
               
             
           
           = 
           
             
               G 
               ⁡ 
               
                 ( 
                 
                   
                     v 
                     
                       C 
                       2 
                     
                     
                       ( 
                       1 
                       ) 
                     
                   
                   - 
                   
                     v 
                     
                       C 
                       1 
                     
                     
                       ( 
                       1 
                       ) 
                     
                   
                 
                 ) 
               
             
             - 
             
               f 
               ⁡ 
               
                 ( 
                 
                   v 
                   
                     C 
                     1 
                   
                   
                     ( 
                     1 
                     ) 
                   
                 
                 ) 
               
             
           
         
       
     
     
       
         
           
             
               C 
               2 
             
             ⁢ 
             
               
                 ⅆ 
                 
                   v 
                   
                     C 
                     2 
                   
                   
                     ( 
                     1 
                     ) 
                   
                 
               
               
                 ⅆ 
                 t 
               
             
           
           = 
           
             
               G 
               ⁡ 
               
                 ( 
                 
                   
                     v 
                     
                       C 
                       1 
                     
                     
                       ( 
                       1 
                       ) 
                     
                   
                   - 
                   
                     v 
                     
                       C 
                       2 
                     
                     
                       ( 
                       1 
                       ) 
                     
                   
                 
                 ) 
               
             
             + 
             
               i 
               L 
               
                 ( 
                 1 
                 ) 
               
             
             + 
             
               f 
               ⁡ 
               
                 ( 
                 
                   v 
                   
                     C 
                     1 
                   
                   
                     ( 
                     1 
                     ) 
                   
                 
                 ) 
               
             
             + 
             
               
                 1 
                 
                   R 
                   K 
                 
               
               ⁢ 
               
                 ( 
                 
                   
                     v 
                     
                       C 
                       2 
                     
                     
                       ( 
                       2 
                       ) 
                     
                   
                   - 
                   
                     v 
                     
                       C 
                       2 
                     
                     
                       ( 
                       1 
                       ) 
                     
                   
                 
                 ) 
               
             
           
         
       
     
     
       
         
           
             L 
             ⁢ 
             
               
                 ⅆ 
                 
                   v 
                   L 
                   
                     ( 
                     1 
                     ) 
                   
                 
               
               
                 ⅆ 
                 t 
               
             
           
           = 
           
             - 
             
               v 
               
                 C 
                 2 
               
               
                 ( 
                 1 
                 ) 
               
             
           
         
       
     
     
       
         
           
             
               C 
               1 
             
             ⁢ 
             
               
                 ⅆ 
                 
                   v 
                   
                     C 
                     1 
                   
                   
                     ( 
                     2 
                     ) 
                   
                 
               
               
                 ⅆ 
                 t 
               
             
           
           = 
           
             
               G 
               ⁡ 
               
                 ( 
                 
                   
                     v 
                     
                       C 
                       2 
                     
                     
                       ( 
                       2 
                       ) 
                     
                   
                   - 
                   
                     v 
                     
                       C 
                       1 
                     
                     
                       ( 
                       2 
                       ) 
                     
                   
                 
                 ) 
               
             
             - 
             
               f 
               ⁡ 
               
                 ( 
                 
                   v 
                   
                     C 
                     1 
                   
                   
                     ( 
                     2 
                     ) 
                   
                 
                 ) 
               
             
           
         
       
     
     
       
         
           
             
               C 
               2 
             
             ⁢ 
             
               
                 ⅆ 
                 
                   v 
                   
                     C 
                     2 
                   
                   
                     ( 
                     2 
                     ) 
                   
                 
               
               
                 ⅆ 
                 t 
               
             
           
           = 
           
             
               G 
               ⁡ 
               
                 ( 
                 
                   
                     v 
                     
                       C 
                       1 
                     
                     
                       ( 
                       2 
                       ) 
                     
                   
                   - 
                   
                     v 
                     
                       C 
                       2 
                     
                     
                       ( 
                       2 
                       ) 
                     
                   
                 
                 ) 
               
             
             + 
             
               i 
               L 
               
                 ( 
                 2 
                 ) 
               
             
             + 
             
               f 
               ⁡ 
               
                 ( 
                 
                   v 
                   
                     C 
                     1 
                   
                   
                     ( 
                     2 
                     ) 
                   
                 
                 ) 
               
             
             + 
             
               
                 1 
                 
                   R 
                   K 
                 
               
               ⁢ 
               
                 ( 
                 
                   
                     v 
                     
                       C 
                       2 
                     
                     
                       ( 
                       3 
                       ) 
                     
                   
                   - 
                   
                     v 
                     
                       C 
                       2 
                     
                     
                       ( 
                       2 
                       ) 
                     
                   
                 
                 ) 
               
             
           
         
       
     
     
       
         
           
             L 
             ⁢ 
             
               
                 ⅆ 
                 
                   v 
                   L 
                   
                     ( 
                     2 
                     ) 
                   
                 
               
               
                 ⅆ 
                 t 
               
             
           
           = 
           
             - 
             
               v 
               
                 C 
                 2 
               
               
                 ( 
                 2 
                 ) 
               
             
           
         
       
     
     
       
         ⋮ 
       
     
     
       
         
           
             
               C 
               1 
             
             ⁢ 
             
               
                 ⅆ 
                 
                   v 
                   
                     C 
                     1 
                   
                   
                     ( 
                     n 
                     ) 
                   
                 
               
               
                 ⅆ 
                 t 
               
             
           
           = 
           
             
               G 
               ⁡ 
               
                 ( 
                 
                   
                     v 
                     
                       C 
                       2 
                     
                     
                       ( 
                       n 
                       ) 
                     
                   
                   - 
                   
                     v 
                     
                       C 
                       1 
                     
                     
                       ( 
                       n 
                       ) 
                     
                   
                 
                 ) 
               
             
             - 
             
               f 
               ⁡ 
               
                 ( 
                 
                   v 
                   
                     C 
                     1 
                   
                   
                     ( 
                     n 
                     ) 
                   
                 
                 ) 
               
             
           
         
       
     
     
       
         
           
             
               C 
               2 
             
             ⁢ 
             
               
                 ⅆ 
                 
                   v 
                   
                     C 
                     2 
                   
                   
                     ( 
                     n 
                     ) 
                   
                 
               
               
                 ⅆ 
                 t 
               
             
           
           = 
           
             
               G 
               ⁡ 
               
                 ( 
                 
                   
                     v 
                     
                       C 
                       1 
                     
                     
                       ( 
                       n 
                       ) 
                     
                   
                   - 
                   
                     v 
                     
                       C 
                       2 
                     
                     
                       ( 
                       n 
                       ) 
                     
                   
                 
                 ) 
               
             
             + 
             
               i 
               L 
               
                 ( 
                 n 
                 ) 
               
             
             + 
             
               f 
               ⁡ 
               
                 ( 
                 
                   v 
                   
                     C 
                     1 
                   
                   
                     ( 
                     n 
                     ) 
                   
                 
                 ) 
               
             
             + 
             
               
                 1 
                 
                   R 
                   K 
                 
               
               ⁢ 
               
                 ( 
                 
                   
                     v 
                     
                       C 
                       2 
                     
                     
                       ( 
                       
                         n 
                         + 
                         1 
                       
                       ) 
                     
                   
                   - 
                   
                     v 
                     
                       C 
                       2 
                     
                     
                       ( 
                       n 
                       ) 
                     
                   
                 
                 ) 
               
             
           
         
       
     
     
       
         
           
             L 
             ⁢ 
             
               
                 ⅆ 
                 
                   v 
                   L 
                   
                     ( 
                     n 
                     ) 
                   
                 
               
               
                 ⅆ 
                 t 
               
             
           
           = 
           
             - 
             
               v 
               
                 C 
                 2 
               
               
                 ( 
                 n 
                 ) 
               
             
           
         
       
     
   
   Here n is taken to be equal to 5. R K  is the controlling resistor whose value describes the behavior of the entire system. 
   The invention tries to achieve the solution of the above equations without any additional hardware by proposing the scheme, as shown in  FIG. 13 . 
   Referring to  FIG. 13 ,  11  of the Chua&#39;s circuit ( 100 ) is connected to  17  of the same Chua&#39;s circuit  100 ,  11  of the Chua&#39;s circuit ( 100 ) is also connected to  18  of a next Chua&#39;s circuit ( 101 ). Similarly,  18  of the Chua&#39;s circuit ( 100 ) is connected with  11  of a previous Chua&#39;s circuit ( 99 ), thereby forming a ring using several Chua&#39;s circuit connected in a similar and in a symmetric fashion. The resistor RL 2  of each Chua&#39;s circuit acts as a controlling resistor, and the coupling is achieved without an additional resistor or voltage buffer. The additional advantage of this embodiment of a hyper-chaotic circuit is that the controlling resistor is grounded, and hence, can be beneficial in a straightforward monolithic implementation. 
   For the above stated values of components and with RL 1 =300 Ohm and RL 2 =600 ohm for a Chua&#39;s circuit designed using the MO-CCII and using a similar Chua&#39;s circuit for coupling with the scheme as shown in  FIG. 13 , the system of  FIG. 13  thus derived is a hyper-chaotic circuit. This is proved by the fact that none of the Chua&#39;s circuits are in synchronization with each other as reflected by the simulation results shown in  FIG. 14 . 
   A DO-CCII/MO-CCII based implementation of a Chua&#39;s circuit is presented. The circuit has advantages of a grounded resistor and capacitor, minimum active and passive components and accessibility of current across the inductor. Moreover, apart from these advantages the voltage across the capacitor (of the tank circuit) is also available in the form of current at a high impedance node. One of the applications of this current is in generating a hyper-chaos coupled Chua&#39;s circuit with reduced hardware. 
   The Chua&#39;s circuit uses a DO-CCII/MO-CCII based inductor and non-linear component that allows tapping of current through the inductor and voltage across the capacitor of the tank circuit without requiring any additional hardware. The available third state variable can be observed, and therefore, it is possible to make more complex chaotic circuits using this additional information. Also, the inductor of the present invention does not use any additional components, such as capacitors and resistors as compared to the prior art. 
   The invention does not use operational amplifiers but instead it uses current conveyors to operate in the current mode. Also, the invention does not require a precise component matching unlike in the prior art that used op-amps for forming a Chua&#39;s circuit. 
   The invention also relates to the use of available current in designing a reduced hardware hyper-chaos circuit. The final hyper-chaotic circuit thus designed offers several advantages, such as minimum active and passive components for a coupled Chua&#39;s circuit, coupling of a Chua&#39;s circuit without additional hardware such as a voltage buffer and a floating resistor, a controlling resistor being grounded, etc. These advantages are non-existent when the same coupling is achieved using any of the prior art Chua&#39;s circuits.