Abstract:
A level shift semiconductor device converts a signal level into another level between circuits connected to each other having different supply voltages. An input signal is supplied to the source of a first MOS transistor of a first-conductivity type (NMOS). The drain of the 1st NMOS transistor is connected to the input terminal of an inverter. An output signal is outputted via the output terminal of the inverter. The drain and gate of a first MOS transistor of a second-conductivity type (PMOS) are connected to the input and output terminals of the inverter, respectively. The gate and source of a second NMOS transistor are connected to the output terminal of the inverter and the gate of the 1st NMOS transistor, respectively. The gate and source of a second PMOS transistor are connected to the gate and source of the 2nd NMOS transistor. A first supply voltage is supplied to the drain of the 2nd PMOS transistor. And, a second supply voltage is supplied to the inverter, the source of the 1st PMOS transistor, and the drain of the 2nd NMOS transistor. The second voltage is larger in absolute value than the first voltage.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor device. More specifically, this invention relates to a level shift semiconductor device for converting a signal level into another signal level between circuits connected to each other and having different supply voltages. 
     A conventional level shift semiconductor device incorporated in a semiconductor integrated circuit device is shown in FIG. 1A. This circuit shifts a level of a logical signal changing between a first supply voltage V DDL  and a ground GND into another level of a second logical signal changing between a second supply voltage V DDL  higher than the first supply voltage V DDL  and the ground GND, as shown in FIG. 1B. 
     The level shift circuit shown in FIG. 1A includes inverters IV 1  and IV 2 , an N-channel MOS transistor MN N1 , and a P-channel MOS transistor M P1 . 
     The operation of this circuit will be described hereinbelow. Here, the assumption is made that the supply voltage V DDL  is 1.5V; the supply voltage V DDH  is 3V; and the threshold level of the NMOS transistor V th  is 0.5V. 
     When an &#34;H&#34; level signal (=1.5V) is applied to an input terminal S 1 , a node n 1  is set to an &#34;L&#34; level (=0V) by the inverter IV 1 . Since the supply voltage V DDL  (=1.5V) is kept applied to the gate of the NMOS transistor M N1 , the transistor M N1  is turned on to discharge a charge at a node n 2 , so that the node n 2  changes to the &#34;L&#34; level (=0V). Further, a node n 3  changes to the &#34;H&#34; level (=3V) by the inverter IV 2  whose input is an input node n 2 . As a result, the &#34;H&#34; level input signal with an amplitude V DDL  can be level-shifted to the &#34;H&#34; output signal with an amplitude V DDH , and then outputted from an output terminal S 2 . The PMOS transistor M p1  is then turned off. 
     On the other hand, when an &#34;L&#34; level signal (=0V) is applied to the input terminal S 1 , the node n 1  is set to the &#34;H&#34; level (=1.5V) by the inverter IV 1 . Since the supply voltage V DDL  (=1.5V) is kept applied to the gate of the NMOS transistor M N1 , the node n 2  is charged up to &#34;H&#34;-V thn  (=1.0V) before the transistor M N1  is turned off. Here, when the threshold level of the inverter IV 2  is set to a voltage lower than 1V, since the input to the inverter IV 2  changes to the &#34;H&#34; level, the node n 3  changes to the &#34;L&#34; level (=0V). This &#34;L&#34; level is applied to the output terminal S 2  and the gate of the PMOS transistor M p1 . The PMOS transistor M p1  is then turned on to pull up the node n 2  to V DDH  (=3V). This pulled-up potential at the node n 2  prevents the voltage level applied to the input terminal of the inverter IV 2  from being kept at an input level for current flow through the inverter IV 2 . Under these conditions, the source of the NMOS transistor M N1  is the node n 1 . Here, since the gate-source voltage of M N1  is lower than V thn , the transistor M N1  is kept turned off, so that the potential at the node n 1  cannot be charged beyond V DDL . 
     This conventional level shift semiconductor device, however, has the following drawbacks: 
     When the &#34;L&#34; level signal is propagated, the node n 2  is charged from the &#34;L&#34; level to &#34;H-V thn  &#34; by the transistor M N1  . In this case, since the input to the inverter IV 2  is fairly lower than V DDH , a relatively large dc current (through current) flows through the inverter IV 2 , with the result that a power loss increases inevitably. 
     In addition, since the &#34;H&#34; level at the node n 2  drops from the supply voltage V DDL  by V thn  of the transistor M N1 , it is necessary to set the threshold level of the inverter IV 2  to a relatively low level, with the result that a delay time required to shift the signal level is lengthened. 
     In other words, when the supply voltage V DDL  drops, since the potential at the node n 2  cannot increase beyond the threshold level of the inverter IV 2 , there exists a problem in that the &#34;L&#34; input signal cannot be propagated or the operation margin is too small. 
     To overcome these problems, Japanese Laid-Open Patent No. 2(1990)-134918 discloses a level shift circuit as shown in FIG. 2. 
     The difference between the circuits in FIGS. 1A and 2 is that the circuit of FIG. 2 includes an N-channel D(depletion)-type MOS transistor MN N1a  whose gate is connected to the gate of a P-channel E(enhancement)-type MOS transistor M P1a . 
     The operation of this circuit shown in FIG. 2 will be described hereinbelow: 
     When the voltage applied to the input terminal S 1  changes from V DDL  to the ground GND, the voltage at the node n 0  changes from V DDL  to GND. The voltage a the node n 1  then changes from GND to V DDL  by the inverter IV 1 . The cut-off transistor M N1a  of D-type is turned on to charge the node n 2  up to about V DDL . When the voltage at the node n 2  increases beyond the threshold level of the inverter IV 2 , the voltage at the node n 3  changes from V DDL  to GND. The GND level of the node n 3  turns on the feedback transistor M P1a  to charge node n 2  up to V DDH . This results in no charge current flow through the inverter IV 2 . Further, the gate potential of the cut-off transistor M N1a  decreases with decreasing potential at the node n 3 . The transistor M N1a  is turned off when this gate potential decreases below the threshold voltage V thn . Current flow from the high voltage circuit to the low voltage circuit is then cut off. The voltage at the node n 2  can be held at V DDH  by the transistor M P1a  after the transistor M N1a  is turned off. 
     When the &#34;L&#34; level signal is propagated by this level shift circuit, since the node n 2  can be charged up to roughly V DDL  by the transistor M N1a , even if V DDL  is low, it is possible to propagate the signal of the low voltage circuit to the high voltage circuit. 
     Next, when the voltage applied to the input terminal S 1  changes from the ground GND to V DDL , the voltage at the node n 0  changes from GND to V DDL . The voltage at the node n 1  then changes from V DDL  to GND by the inverter IV 1 . The cut-off transistor MN N1a  is turned according to a change of the voltage at the node n 1 . Here, the feedback transistor M P1a  is also turned on. The voltage at the node n 2  then drops to a level determined on the basis of the turn-on resistance of the transistor M N1a  and that of the transistor M P1a . When the voltage at the node n 2  drops below the threshold level of the inventer IV 2 , the voltage at the node n 3  changes from GND to V DDH . This causes the feedback transistor M P1a  to be turned off. The voltage at the node n 2  then drops to GND via cut-off transistor M N1a , so that no dc current flows through the inverter IV 2 . 
     In the conventional level shift circuit as shown in FIG. 2, however, the gate potential of the cut-off transistor M N1a  depends on the potential of the node n 3 . Therefore, a delay time required to shift the signal level is not so shortened. Further, the circuit of FIG. 2 includes both the depletion and enhancement-type transistors. This results in a complicated manufacturing process. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is the object of the present invention to provide a level shift semiconductor device, which can decrease the power loss and delay time both required to shift the signal level and increase the operation margin. 
     To achieve the above-mentioned object, the present invention provides a level shift semiconductor device, comprising: a first MOS transistor of a first-conductivity type having a source supplied with an input signal; an inverter having an input terminal connected to a drain of the first MOS transistor of the first-conductivity type and an output terminal for outputting an output signal; a first MOS transistor of a second-conductivity type having a drain connected to the input terminal of the inverter and a gate connected to the output terminal of the inverter, the second conductivity type being opposite of the first conductivity type; a second MOS transistor of the first-conductivity type having a gate connected to the output terminal of the inverter and a source connected to a gate of the first MOS transistor of the first-conductivity type; a second MOS transistor of the second-conductivity type having a gate connected to the gate of the second MOS transistor of the first-conductivity type and a source connected to the source of the second MOS transistor of the first-conductivity type; a first voltage supply for supplying a first supply voltage to a drain of the second MOS transistor of the second-conductivity type; and a second voltage supply for supplying a second voltage to the inverter, a source of the first MOS transistor of the second-conductivity type, and a drain of the second MOS transistor of the first-conductivity type, the second voltage being larger in absolute value than the first voltage. 
     Further, the present invention provides a level shift semiconductor device, comprising: a first-conductivity type MOS transistor having a source supplied with an input signal; an inverter having an input terminal connected to a drain of the first-conductivity type MOS transistor and an output terminal for outputting an output signal; a second-conductivity type MOS transistor having a drain connected to the input terminal of the inverter and a gate connected to the output terminal of the inverter, the second conductivity type being opposite of the first-conductivity type; a bias circuit for applying a first voltage obtained by adding a maximum voltage of the input signal and a threshold voltage of the first-conductivity type MOS transistor, to a gate of the first-conductivity type MOS transistor; and a voltage supply for supplying a second voltage to a source of the second-conductivity type MOS transistor and the inverter, the second voltage being larger in absolute value than the maximum voltage of the input signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a circuit diagram of a conventional level shift semiconductor device; 
     FIG. 1B shows the voltage level change of the semiconductor device shown in FIG. 1A; 
     FIG. 2 is a circuit diagram of another conventional level shift semiconductor device; 
     FIG. 3A is a circuit diagram showing a first embodiment of the level shift semiconductor device according to the present invention; 
     FIG. 3B shows the voltage level change of the semiconductor device shown in FIG. 3A; 
     FIG. 4A is a circuit diagram showing a second embodiment of the level shift semiconductor device according to the present invention; 
     FIG. 4B shows the voltage level change of the semiconductor device shown in FIG. 4A; 
     FIG. 5A is a circuit diagram showing a third embodiment of the level shift semiconductor device according to the present invention; 
     FIG. 5B shows the voltage level change of the semiconductor device shown in FIG. 4B; 
     FIG. 6A is a circuit diagram showing a fourth embodiment of the level shift semiconductor device according to the present invention; 
     FIG. 6B shows the voltage level change of the semiconductor device shown in FIG. 6A; 
     FIG. 7A is a circuit diagram showing a fifth embodiment of the level shift semiconductor device according to the present invention; 
     FIG. 7B shows the voltage level change of the semiconductor device shown in FIG. 7A; 
     FIG. 8A is a circuit diagram showing a sixth embodiment of the level shift semiconductor device according to the present invention; 
     FIG. 8B shows the voltage level change of the semiconductor device shown in FIG. 8A; 
     FIG. 9 is a circuit diagram showing an example of the bias circuit shown in FIG. 7A; 
     FIG. 10 is a circuit diagram showing another example of the bias circuit shown in FIG. 8A; and 
     FIGS. 11A, 11B, and 11C are circuit diagrams each showing an example of the current source shown in FIGS. 9 and 10. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiments of the level shift semiconductor device according to the present invention will be described hereinbelow with reference to the attached drawings. 
     A first embodiment of the semiconductor device according to the present invention will be described hereinbelow with reference to FIGS. 3A and 3B. The same reference numerals have been retained in FIGS. 3A and 3B for similar parts and voltages having the same function as with the case of the prior art semiconductor device shown in FIGS. 1A and 1B. 
     In the first and other embodiments, all the transistors are of enhancement type. Here, in general, the threshold levels of MOS transistors differ according to the manufacturing process, and further there exists such a tendency that the threshold levels are determined to be lower gradually with decreasing supply voltage. Herein, however, the description will be made on assumption that the threshold level V thn  of the NMOS transistor is 0.5V and the threshold level V thp  of the PMOS transistor is -0.5V, respectively for convenience. 
     In the circuit shown in FIG. 3A, two inverters IV 1  and IV 2  are constructed by a well-known CMOS transistor circuit of a PMOS and an NMOS transistor (both not shown). Two gates of the PMOS NMOS transistors are connected to each other. Their drains are also connected to each other. A source of the PMOS transistor of the inverter IV 1  is connected to the supply voltage V DDL  and a source of the NMOS transistor of the inverter IV 1  is connected to the ground GND (0V). Further, a source of the PMOS transistor of the inverter IV 2  is connected to the supply voltage V DDH  and a source of the NMOS transistor of the inverter IV 2  is connected to the ground GND (0V). 
     Further, in the circuit shown in FIG. SA, an NMOS transistor M N2  and a PMOS transistor M P2  are connected between the node n 3  and the gate (i.e., a node n 4 ) of an NMOS transistor M N1 . The gates of both the, transistors M N2  and M P2  are connected in common to the node n 3  and also to the gate of a PMOS transistor the M P1 . The sources of the transistors M N2  and M P2  are connected in common to the node n 4 . Further, the drain of the transistor M N2  is connected to the supply voltage V DDH , and the drain of the transistor M P2  is connected to the supply voltage V DDL . 
     Owing to the two transistors M N2  and M P2 , when the node n 3  is set to the &#34;L&#34; level (=0V), the node n 4  is set to V DDL . On the other hand, when the node n 3  is set to the &#34;H&#34; level (=V DDH , 3V), the node n 4  is set to V DDH  -V thn  (=2.5V). 
     The operation of the first embodiment of the level shift circuit according to the present invention will be explained hereinbelow. 
     When the &#34;H&#34; level signal (=1.5V) is supplied to the input terminal S 1 , the node n 1  is set to the &#34;L&#34; level (=0V) by the inverter IV 1 . In this case, since the gate of the transistor M N1  is at V DDL  (=1.5V), the transistor M N1  is turned on, so that the node n 2  is discharged down to the &#34;L&#34; level (=0). The &#34;L&#34; level of the node n 2  is inputted to the inverter IV 2 , the node n 3  changes to the &#34;H&#34; level (=3V), so that the &#34;H&#34; level is outputted to the output terminal S 2 . 
     Accordingly, as shown in FIG. 3B, the &#34;H&#34; level input signal having a voltage amplitude of V DDL  is level-shifted to the &#34;H&#34; level output signal having a voltage amplitude of V DDH , and then outputted from the output terminal S 2 . 
     When the node n 3  changes to the &#34;H&#34; level (=3V), the NMOS transistor M N2  is turned on, while the PMOS transistors M P1  and M P2  are turned off. As a result, the gate potential (i.e., the node n 4 ) of the transistor M N1  is set to V DDH  -V thn  (=2.5V). Therefore, the transistor M N1  is kept turned on, so that the node n 2  is held at the &#34;L&#34; level and the node n 3  is held at the &#34;H&#34; level. 
     On the other hand, when the &#34;L&#34; level signal (=0V) is supplied to the input terminal S 1 , the node n is set to the &#34;H&#34; level (=1.5V) by the inverter IV 1 . At this time, the node n 3  is still kept at V DDH  ; the node n 4  is kept at V DDH  -V thn  (=2.5V); the NMOS transistor M N1  is kept turned on; and the PMOS transistor M P1  is kept turned off. As a result, the node n 2  is charged up to V DDL  (=1.5V) at high speed. Therefore, when the threshold level of the inverter IV 2  is set to a value lower than 1.5V, the node n 3  can be set to the &#34;L&#34; level (=0V) by the inverter IV 2 . 
     Accordingly, as shown in FIG. 3B, the &#34;L&#34; level input signal having a voltage amplitude of GND and supplied to the input terminal S 1  is propagated to the output terminal S 2  as the &#34;L&#34; level output signal having a voltage amplitude of GND. When the node n 3  changes to the &#34;L&#34; level (=0V), the PMOS transistors M P1  and M P2  are turned on, while the NMOS transistor M N2  is turned off. As a result, the gate potential (i.e., the node n 4 ) of the transistor M N1  is set to V DDL  (=1.5V). Therefore, the transistor M N1  is turned off to pull the node n 2  up to the &#34;H&#34; level (=3V), and then the node n 3  is held at the &#34;L&#34; level. In this case, since the transistor M N1  is turned off, the potential at the node n 1  is not charged beyond V DDL . 
     In the above-mentioned propagation of the &#34;L&#34; level signal, since the initial input level V DDL  to the inverter IV 2  is lower than the supply voltage V DDH  to the inverter IV 2 , a dc current somewhat flows through the inverter IV 2  at the beginning. However, when the node n 3  changes to the &#34;L&#34; level (=0V), the PMOS transistor M P1  is turned on, so that the node n 2  is soon charged up to V DDL  (=3V). The PMOS transistor M P1  is then turned off. As a result, since the input level to the inverter IV 2  becomes equal to V DDH , no dc current flows through the inverter IV 2 . 
     In the first embodiment shown in FIG. 3A, when the &#34;H&#34; level (=V DDL ) signal propagates from the node n 1  to the node n 2  , the delay caused by the transistor M N1  can be shortened. Because the gate voltage of the transistor M N1  is set to V DDH  -V thn  (=2.5V); that is, the gate voltage higher than the conventional gate voltage (1.5V, FIG. 1A) is applied to the transistor M N1  to turn on the transistor M N1  deeply. 
     Further, in the first embodiment, the &#34;H&#34; level (=V DDL ) signal can be propagated by the transistor M N1  from the node n 1  to the node n 2  without reducing the signal level below the &#34;H&#34; level (=V DDL  ). It is thus possible to set the threshold level of the inverter IV 2  at an ordinary level, so that the delay time required for the level shift can be shortened. In other words, even when the V DDL  is lowered, the &#34;H&#34; level at the node n 2  will not be lowered below the threshold level of the inverter IV 2 , so that the operation margin can be increased. This is because the &#34;H&#34; level at the node n 2  will not be reduced to V DDL  -V thn  (=1.0V) by the transistor M N1  as with the case of the circuit of FIG. 1A, that is, the &#34;H&#34; level at the node n 1  can be propagated, as it is, to the node n 2  . 
     A second embodiment of the semiconductor device according to the present invention will be described hereinbelow with reference to FIGS. 4A and 4B. In the figures, the same reference numerals have been retained for similar parts and voltages having the same function as with the case of the semiconductor device shown in FIGS. 3A and 3B, without repeating the similar description thereof. 
     In this second embodiment, the transistor M N2  is diode-connected; that is, their drain and gate are connected to each other. In this case, since the transistor M N2  is turned on only when the &#34;H&#34; level (=V DDH )is supplied to its gate, the second embodiment shown in FIG. 4A can operate in the same way as with the case of the first embodiment shown in FIG. 3A. That is, the &#34;H&#34; level input signal having a voltage amplitude of V DDL  can be level-shifted to the &#34;H&#34; level output signal having a voltage amplitude of V DDH , as shown in FIG. 4B. 
     Further, when the threshold level V thn  of the NMOS transistor M N2  shown in FIGS. 3A and 4A is set to a value lower than the ordinary value (e.g., 0.5V), it is possible to set the voltage applied to the gate of the transistor M N1  to a higher value. This high gate voltage application to the transistor M N1  can be applied in the same way to the threshold level (e.g., -0.5V) of the PMOS transistor M P2  of the circuit shown in FIG. 5A and 6A, described later, in which two negative supply voltages are used. 
     A third embodiment of the semiconductor device according to the present invention will be described hereinbelow with reference to FIGS. 5A and 5B. In the figures, the same reference numerals have been retained for similar parts and voltages having the same function as with the case of the semiconductor device shown in FIGS. 3A and 3B, without repeating the similar description thereof. 
     In this third embodiment, the level shift circuit shown in FIG. 3A is applied to a negative voltage supply circuit. That is, a voltage V SSH  of a smaller absolute value and a voltage V SSL  of a larger absolute value are supplied to the circuit. The inverter IV 1  is driven between the voltage V SSH  and the ground GND, while the inverter IV 2  is driven between the voltage V SSL  and the ground GND. In correspondence to the operation by the negative supply voltage circuit, the NMOS transistor M N1  shown in FIG. 3A is replaced with the PMOS transistor M P1  and the PMOS transistor M P1  shown in FIG. 3A is replaced with the NMOS transistor M N1  . 
     In the circuit construction of the negative supply voltage, as shown in FIG. 5B, V DDL  shown in FIG. 3B corresponds to V SSH , and V DDH  shown in FIG. 3B corresponds to V SSL . The circuit operation of the third embodiment is the same as with the case of the first embodiment shown in FIG. 3A. 
     A fourth embodiment of the semiconductor device according to the present invention will be described hereinbelow with reference to FIGS. 6A and 6B. In the figures, the same reference numerals have been retained for similar parts and voltages having the same function as with the case of the semiconductor device shown in FIGS. 5A and 5B, without repeating the similar description thereof. 
     In this fourth embodiment, the transistor M P2  of the third embodiment using the negative supply voltage circuit shown in FIG. 5A is diode-connected in the same way as with the case of the second embodiment shown in FIG. 4A. In this circuit construction as shown in FIG. 6A, it is possible to obtain the same operation as with the case of the circuit shown in FIG. 5A. 
     A fifth embodiment of the semiconductor device according to the present invention will be described hereinbelow with reference to FIGS. 7A and 7B. In the figures, the same reference numerals have been retained for similar parts and voltages having the same function as with the case of the circuit shown in FIG. 1A, without repeating the similar description thereof. 
     In this embodiment, a bias circuit BC is additionally provided for the circuit shown in FIG. 1A, to have a higher gate bias voltage of the NMOS transistor M N1  . In more detail, in this embodiment, the gate potential of the NMOS transistor M N1  is always kept at V DDL  +V thn  (=2V) by the bias circuit BC. 
     In the circuit shown in FIG. 7A, when the &#34;H&#34; level signal (=1.5V) is supplied to the input terminal S 1 , the node n 1  is set to the &#34;L&#34; level (=0V) by the inverter IV 1 . Here, since V DDL  (=2V) is applied to the gate of the NMOS transistor M N1 , the transistor M N1  is turned on to discharge the charge at the node n 2  , so that the node n 2  changes to the &#34;L&#34; level (0V). Therefore, the node n 3  changes the &#34;H&#34; level (=3V) by the inverter IV 2  having the input at the node n 2  . As a result, the &#34;H&#34; level input signal having a voltage amplitude of V DDL  Can be level-shifted to the &#34;H&#34; level output signal having a voltage amplitude of V DDH , and then outputted from the output terminal S 2 , as shown in FIG. 7B. At this time, the PMOS transistor M P1  is turned off. 
     On the other hand, when the &#34;L&#34; level signal (=0V) is supplied to the input terminal S 1 , the node n 1  is set to the &#34;H&#34; level (=1.5V) by the inverter IV 1 . Here, since V DDL  (=2V) is applied to the gate of the NMOS transistor M N1 , after the node n 2  has been charged up to the &#34;H&#34; level (=1.5V), the transistor M N1  is turned off. Here, when the threshold level of the inverter IV 2  is set to a potential lower than 1.5V, the input to the inverter IV 2  changes to the &#34;H&#34; level, and the node n 3  changes to the &#34;L&#34; level (=0V). This &#34;L&#34; level is propagated to the output terminal S 2  and the gate of the PMOS transistor M P1 . When the &#34;L&#34; level signal is applied to the gate of the PMOS transistor M P1 , since the transistor M P1  is turned on, the potential at the node n 2  is pulled up to V DDL  (=3V). The pulled-up potential at the node n 2  can prevent the through current from being kept flowing through the inverter IV 2  (i.e., the input level status). In this circuit, since the source side of the NMOS transistor M N1  is at the node n 1  and further since the gate-source voltage is lower than V thn , the transistor M N1  is kept turned off, so that the potential at the node n 1  is not charged beyond V DDL . 
     As described above, since the gate bias voltage of the transistor M N1  is set a higher value, the level of the &#34;H&#34; level (V DDL ) signal will not be lowered at the node n 1  and propagated to the node n 2  as it is. In other words, since a relatively high &#34;H&#34; level signal can be applied to the inverter IV 2 , it is possible to obtain the same function as with the case of the circuit shown in FIG. 3A. 
     FIG. 9 shows an example of the bias circuit BC shown in FIG. 7A. As shown, the bias circuit BC is connected between the supply voltage V DDL  and V DDL , and consists of a constant current source and a diode-connected NMOS transistor M N2 . The output voltage of this bias circuit is an addition of the voltage V DDL  and a voltage drop V thn  between the gate and the source of the transistor M N2  as (V DDL  +V thn ). 
     A sixth embodiment of the semiconductor device according to the present invention will be described hereinbelow with reference to FIGS. 8A and 8B. In this embodiment, the semiconductor device shown in FIG. 7A is applied to a negative voltage supply circuit. That is, the NMOS transistor M N1  shown in FIG. 7A is replaced with the PMOS transistor M N1 , and the PMOS transistor M P1  shown in FIG. 7A is replaced with the NMOS transistor M N1  . Further, the gate potential of the transistor M P1  is always biased at V SSh  -|V thp  |. 
     FIG. 10 shows an example of a bias circuit BCa shown in FIG. 8A. As shown, the bias circuit BCa is connected between the supply voltage V SSH  and V SSL , and consists of a constant current source and a diode-connected PM N1  OS transistor M P2a . The output voltage of this bias circuit is an addition of the negative voltage V SSH  and a negative voltage drop V thp  between the gate and the source of the transistor M P2  as -(V SSH  +V thp ). 
     FIGS. 11A to 11C show examples of the constant current source. FIG. 11A shows a constant current source for generating a constant current by a relatively high resistance; FIG. 11B shows a constant current source formed by a fixedly-biased PMOS transistor; and FIG. 11C shows a constant current source formed by a fixedly-biased NMOS transistor. 
     Further, in the respective embodiments, the inverter IV 1  is not necessarily required, but can be replaced with another logical gate which can operate on the basis of the first supply voltage. 
     As described above, in the level shift semiconductor device according to the present invention, it is possible to achieve a level shift circuit that can shift a signal level to another signal level at a high speed and at a low power loss, while increasing the operation margin.