Abstract:
A Differential Phase Shift Keying (DPSK) optical transmission system provides time division multiplexing, channel routing and channel add/replace functions. The DPSK transmitter comprises a laser to generate an optical carrier signal; a delay encoder to provide a different delay for each of a plurality, M, of input signal channels; and a M channel phase modulator which phase modulates the optical carrier signal with each of the differently delayed M input signal channels to form a Time Division Multiplexed (TDM) phase modulated optical signal. A DPSK receiver demodulates a received TDM phase modulated optical signal. The system may also include apparatus to route, add, and replace TDM channels.

Description:
TECHNICAL FIELD OF THE INVENTION 
     This invention relates to optical transmission systems and, more particularly, to an optical Differential Phase Shift Keying (DPSK) transmission system having multiplexing, routing and add/replace capabilities. 
     BACKGROUND OF THE INVENTION 
     Cost is an important parameter in optical Local Area Networks (LANs) and Metropolitan Area Networks (MANs). The cost of lasers is a prime component of the costs in such networks. Also, the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) protocols (e.g., Ethernet, IEEE 802.3, etc.) of traditional LANs may not readily be adopted for optical LAN/WANs because of the longer distances involved. 
     What is desired is an optical LAN/MAN network where multiple users can share the same laser source and at the same time provide an efficient way of allocating bandwidth among users. 
     SUMMARY OF THE INVENTION 
     The apparatus and method of the present invention solves the above problems in a Differential Phase Shift Keying (DPSK) optical transmission system which provides time division multiplexing, channel routing and channel add/replace functions. Our techniques also provide a flexible way of allocating bandwidth among multiple users. This makes DPSK attractive for LAN/MAN applications because the cost of one laser (or several lasers in case of a WDM system) can be shared among multiple users. 
     More particularly, our DPSK transmitter comprises a laser to generate an optical carrier signal; a delay encoder to provide a different delay for each of a plurality, M, of input signal channels; and a M channel phase modulator to phase modulate the optical carrier signal with each of the differently delayed M input signal channels to form a Time Division Multiplexed (TDM) phase modulated optical signal. A TDM phase modulated DPSK system is formed by combining the transmitter with a receiver for demodulating a received TDM phase modulated optical signal. 
     In another embodiment, an add node is disclosed for adding a signal channel to an empty time slot channel of a received TDM phase modulated optical signal. The add node includes a receiver to demodulate the received TDM phase modulated optical signal to form an output TDM signal including the empty time slot channel; a clock recovery circuit to provide a synchronization signal for the add signal; and a flip-flop to gate the add signal onto a phase modulator. As a result, the add signal is added into the empty time slot channel of the received TDM signal. 
     In yet another embodiment, a channel replace node is disclosed for replacing a selected channel of a received TDM phase modulated optical signal with a new channel signal. The channel replace node includes a receiver to demodulate the received TDM phase modulated optical signal to form an output signal; a demultiplexer and clock recovery circuit to recover data and clock signals of all TDM channels; a channel reset circuit; a flip-flop to add the new channel to the TDM signal; and a channel phase modulator to phase modulate the product signal so as to overwrite the selected channel of the received TDM signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     In the drawing, 
     FIG. 1 shows an illustrative block diagram of an optical Differential Phase Shift Keying (DPSK) transmission system in accordance with the present invention; 
     FIG. 2 is a table showing the demodulated output signal, Y, during one bit period of the low speed input channel; 
     FIG. 3 shows three frames of the demodulated output signal resulting from the multiplexing of 3 input channels, with the dashed vertical lines indicating the framing of the output signal, Y; 
     FIG. 4 shows an illustrative block diagram of a router in accordance with the present invention; 
     FIG. 5 shows an output signal of demodulator/receiver when the input channels have different data rates; 
     FIG. 6 shows an add node, for use in the system of FIG. 1, having an add channel capability; 
     FIG. 7 shows a replace node having a overwrite/replace channel capability; and 
     FIG. 8 shows another embodiment of a replace node having a overwrite/replace channel capability. 
    
    
     DETAILED DESCRIPTION 
     In the following description, each item or block of each figure has a reference designation associated therewith, the first number of which refers to the figure in which that item is first described (e.g.,  101  is first described in FIG.  1 ). 
     With reference to FIG. 1, there is shown an illustrative block diagram of an optical Differential Phase Shift Keying (DPSK) transmission system including a transmitter  101 , one or more nodes  102 - 103 , and a receiver  104 . In accordance with the present invention we describe a simple technique to incorporate time division multiplexing, channel routing and channel add/replace functions in the DPSK optical transmission system of FIG.  1 . Our techniques also provide a flexible way of allocating bandwidth among multiple users (i.e. data channels D 0 -D M−1 ). This makes DPSK attractive for certain LAN/MAN applications because the cost of laser  105  (or several lasers in case of a WDM system) can be shared among multiple users. 
     Our novel technique allows multiple users to phase modulate the same optical carrier (i.e., laser  105 ) signal. Normally this would produce a phase modulated optical signal that—when demodulated—becomes the exclusive-OR of all channels. However, by offsetting the phase of the individual input channels, the demodulated signal becomes a time division multiplexed (TDM) version of the individual input channels, with no interrelation between the channels. 
     (1) Mx 1  Multiplexing DPSK Transmitter 
     As shown in FIG. 1, unlike the standard DPSK transmitter, the multiplexing (D)PSK transmitter  101  incorporates a M electrode phase modulator  106  and a delay encoder  107  for providing time division multiplexing of M NRZ data channels, D 0 -D M−1 . 
     The inputs to the transmitter  101  are M low speed NRZ data channels, D 0  to D M−1 . The amplitude of each input channel is adjusted so that the voltage for a logic “1” equals Vπ and 0 V for a logic “0”, where Vπ is the voltage required to induce a π phase shift of the optical field of carrier signal  108 . Each of the low speed channels are fed to a well known pre-encoder (i.e., delay encoder  107 ) where each of the data channels are delayed (electrically) by different amounts. The amount of delay induced on the input channels increase in steps of τ, where τ equals the bit duration of the low speed channel, τ 0 , divided by M. Thus, each of the different delays provided by the delay encoder is equal to mτ, where τ=τ 0 /M and m is an integer 0≦m≦M−1. The bit time τ then becomes the bit duration of the multiplexed data stream, Y. The resulting output signal of transmitter  101  is an optical carrier signal that has been modulated by each of the M NRZ data channels. 
     It should be noted, more generally, that the time interval τ 0  can be divided by an integer number X which is greater than the number of input data channels M. In such an arrangement, τ=τ 0 /X, where X is an integer greater than or equal to M. The resulting extra time slots formed can be used for signaling, control or made available for other data channels. 
     For the moment, we assume that the nodes  102  through  103  of FIG. 1 merely pass the modulated signal unaltered. The receiver  104  is a standard DSPK receiver/demodulator which includes a delay line  110 , followed by a square law detector  112 . The square-law detector  112  is illustratively shown as a PIN diode. A splitter  115  splits the incoming signal into two portions. One signal portion φ u  is coupled via combiner  116  to detector  112  while the second signal portion is delayed in delay-line  110  (becoming signal φ l ) before being coupled, via combiner  116 , to detector  112 . The delay in the delay-line  110  of the receiver/demodulator  104  must also be τ, where τ is the bit time of the multiplexed data signal. At detector  112  each bit of the TDM signal φ l ,  113 , is combined with a subsequent bit of that TDM signal φ u ,  114 . Note, since the time delay is τ, adjacent bits of the TDM signal are Exclusive-ORed in detector  112 . The resulting detector  112  output signal is of the form D m   N+1 ⊕D m   N , which is a output bit for only one channel m. Thus, if the phase of the bit of TDM signal φ l ,  113 , has the same phase as the subsequent bit of that TDM signal φ u ,  114 , the resulting phase difference of the combined signal is zero. That is if the adjacent bits of signals φ l ,  113 , and φ u ,  114  are both logic “0” or logic “1” then the output of detector  112  is logic “0”. If however, the bits of signals φ l ,  113 , and φ u ,  114  are not the same, e.g., one bit is a logic “0” and the other bit a logic “1”, then the output of detector  112  is logic “1”. The result is that the detector  112  performs an exclusive-OR function on the signals φ l ,  113 , and φ u ,  114 . The output signal, Y, of detector  112  is a high speed (M times the speed of the D-channels) NRZ data channel which contain the multiplexed D 0  to D M−1  data channels. 
     While the receiver/demodulator  104  has been shown using separate fibers for the paths, it should be understood that the relative delay in the two paths can be obtained by other means, such as, using two orthogonally polarized signals in the same fiber or by using the delay between the guiding and cladding modes of a single fiber. 
     The output signal, Y, is a time division multiplexed version of the M input channels D 0  to D M−1  except that the bits of each channel have been exclusive-ORed with the preceding bit of that channel. This is a general feature of any DPSK system and is caused by the differential detection in the demodulator/receiver  104 . (Note, it is easy to obtain the original data by placing a pre-encoder in the transmitter before the signal is applied to the phase modulator  106 , or by decoding the signal in the receiver) The important thing to notice is that correlation exists only between adjacent bits of the same input channel, i.e. there is no correlation between bits from different channels and each input channel can therefore be extracted from the output signal by simple electrical de-multiplexing. The underlying mechanism is that the change in the phase of the transmitted optical signal during a time interval of τ is attributed to one—and only one—of the input channels changing value. The incremental delay step, τ, in the encoder  107  must be equal to the delay, τ, used in the demodulator/receiver  104  and is equal to τ 0 /M where τ 0  is the bit period of the input channels. 
     The resulting output signal, Y can be interpreted as framed (with a frame time of τ 0 =M·τ) with each frame containing 1 bit from each input channel, i.e. each input channel is allocated one time-slot per TDM frame. It should be noted that the multiplexing scheme applies for odd as well as even numbers of M. 
     The FIG. 2 table and FIG. 3 illustrates in detail how the multiplexing of the N&#39;th bit of the M input channels D 0  to D M−1  is performed. FIG. 2 is a table showing the time slots τ,  201 , the signals φ l , φ u , and Δφ 202 , and the demodulated output signal Y,  203  during each bit period τ of frame N (Note, a frame time is one bit period τ 0  of the low speed input data channels D 0  to D M−1 ). FIG. 3 shows three frames of the demodulated output signal resulting from the multiplexing of, illustratively, 3 input channels, with the spacing between the dashed vertical lines,  301 , indicating the framing of the output signal Y. 
     In FIGS. 2 and 3, values in bold are logical values, where D x   y  is the optical phase induced by the y&#39;th bit in the x&#39;th input channel and D x   y  is the corresponding logical value. Numbers in brackets (as in D x   y [z]), describes the value of D x   y  during the Z&#39;th interval of D x   y  (of which there are M). The center column,  202 , of the FIG. 2 table gives the phase (φ u ) of the optical field in the upper arm,  114  of FIG. 1, in the receiver/demodulator and the phase (φ l ) in the lower arm,  113  of FIG. 1, after delay τ. Finally, Δφ gives the difference between φ u  and φ l . In reducing the expressions for Δφ, the equivalence D x   y [p]=D x   y [q] is used. 
     (2) Mx 1  Multiplexing DPSK Transmitter With Routing Functionality 
     With reference to FIG. 1 again, the order in which the input channels, D 0  to D M−1 , appear in the frames of the output signal, Y, depends on the electrical delays dialed into the delay encoder  107  of the transmitter  101 . To switch the order of e.g. D 1  and D 2 , one only need swap the two delays in the transmitter. A re-configurable/tunable delay encoder  107  combined with a receiver/demodulator  104  incorporating a de-multiplexer with M output lines can therefore serve as a router of the M input channels, D 0  to D M−1 . This router arrangement is shown in FIG.  4 . As shown, control signals C 0  through C M−1  are used to set the electrical delays of delay encoder  107 . These control signals, C 0  through C M−1 , thereby control to which of the M outputs of demultiplexer  401  each of the input channels, D 0  to D M−1 , can be switched. 
     (3) Mx 1  Multiplexing DPSK Transmitter Where Input Channels Can Have Different Bit-rates 
     The multiplexing DPSK transmitter  101  also handles input channels with different bit-rates. The only requirement is that the bit period of any input channel, τ d , be a non-zero integer (p) multiple of τ 0 , where τ 0 =M·τ, i.e. the bit period of any input channel must satisfy τ d =p·M·τ. More generally, as previously noted, τ d =p·X·τ, where τ is equal to τ 0 /X and where X is an integer greater than or equal to M. 
     Consider an arbitrary input channel D x : If the bit period of D x  equals τ 0 =M·τ (corresponding to p=1) the resulting demodulated output signal, Y, will contain data in each and every frame in the time slot allocated to D x . If p&gt;1 (corresponding to a reduced bit rate of D x ) the data of D x  will only be transferred to D x &#39;s time slot in every p&#39;th frame of the demodulated Y signal while the rest of the frames contains a logic “0”. This is illustrated in FIG. 4 for the case of 3 input channels D 0 -D 2 , with the bit rate of D 1  being half that of D 0  and D 2 , i.e. D 1  has p=2. The resulting demodulated output signal contains a 0 in every second frame in the time slot allocated to D 1 , see  501 , while the remaining frames contains the D x  data. Note that the demodulated output signal for input channel D 1  is “return-to-zero (RZ) like” since it returns to zero after each bit. Any combination of bit rates and number of input channels is possible as long as τ d =p·M·τ is satisfied with p being an integer number. 
     (4) DPSK System With Add Functionality 
     If the transmitter  101  is less than fully loaded, i.e., it has less than M input channels and/or the bit rate of one or more channels is reduced, empty time slots will be available for users at node  102 ,  103  further down the transmission line  109 . As illustrated in FIG. 6, a new Non-Return-to-Zero (NRZ) data channel  608  can be added using a single electrode phase modulator  603  inserted in the transmission line  605 . The added channel must satisfy the condition τ d =p·M·τ. Synchronization (which will be required to clock the new data into the phase modulator  603 ) can be implemented very easily by tapping, using coupler  604 , some of the input signal,  605 , to a demodulator/receiver  601 . The output of this demodulator/receiver  601  will have a distinct frequency component (f=1/τ 0 ) at the frequency at which empty time slots occur (because the logic value in a free time slot always is “0”). The output of demodulator/receiver  601  is connected to a frame clock recovery circuit  602  which locks onto the first logic “0” signal of each frame (occurring every To seconds) to generate a bit wide clock signal that repeats at the frame rate frequency f=1/τ 0 . The frame clock signal  606  is used as the clock input (CL) of a “D” type flip-flop  607 , while the new (or add) channel  608  is connected to the data input D of flip-flop  607 . The flip-flop  607  is used to clock or gate the new (add) channel  608  into the phase modulator  603  in frame and bit synchronization with the empty data channel of the TDM signal that it is to placed. This synchronization method applies independent on whether the free capacity is a result of a reduced number of channels or a reduced bit-rate of one or more channels. This is because any free capacity will show up as demodulated “0&#39;s” 
     (5) DPSK System With Overwrite Functionality 
     A channel of the M channel multiplexed input signal, which already contains data, can be overwritten with new data (i.e. a new channel can replace an existing channel). The process includes extracting data and clock of the channel to be replaced. The time slot in the optical signal that corresponds to this channel is then reset. The new (or add) channel is then added in the manner described in FIG.  6 . Note that channel clock does not have to be extracted again. 
     Circuits for providing a network node with a overwrite/replace channel capability are illustrated in FIGS. 7 and 8. With reference to FIG. 7, the overwrite/replace node includes a demodulator/receiver  701 , a coupler  702 , a clock recovery and demultiplexer  703 , a D-type flip flop  706 , a channel reset circuit  707 , and a phase modulator  710 . The first step is to demodulate the received TDM signal  700  in demodulator  701 . The clock recovery and demultiplexer  703  is responsive to an external channel select signal  714  and generates a frame clock signal  704  bit synchronized to the timing of the bit to be replaced. The clock recovery and demultiplexer  703  also recovers the data of the channel to be replaced. The channel select signal  714  is provided by a node management control unit (not shown) to indicate which channel is to be replaced. This channel select signal is determined by the node management control unit from signaling or other control information associated with the received TDM signal or from other sources. 
     The recovered data signal  705  is used to drive the channel reset unit  707  (e.g., a toggle flip-flop) which causes the first modulator  708  of inline phase modulator  710  to generate the phase needed to cancel the phase of the channel data to be replaced. Thus, for example, assume the phase of a group of channels of received TDM data was π, π, −π, π, −π, −π, the differential phase demodulator  701  would produce the corresponding data sequence 0,1,1,1,0. If we assume that the second channel, first logic “1” of the data sequence, was to be replaced then the −τ phase associated with that second channel must be changed to τ. The channel reset  707  would produce the channel select signal  712  to cause the first modulator  708  of inline phase modulator  710  to generate the phase τ. Similarly, if the third channel, the second logic “1”, was to be replaced 0, then the τ phase associated with that second channel must be changed to −τ. The channel reset  707  would produce the channel select signal  712  to cause the first modulator  708  of inline phase modulator  710  to generate the phase −τ. 
     The frame clock signal  704 , which is bit synchronized to the timing of the bit to be replaced, is used to clock the D-type flip-flop  706  to accept the new data channel  711 . The output of flip-flop  706 , which has the same bit, or channel timing, as the channel being replaced, is used to drive the second modulator  709  of inline phase modulator  710  to establish the proper phase for the replaced channel in the TDM signal outputted on line  711 . It should be noted that the circuits of FIG. 7 can be arranged to delete one or more selected data bits in a variety of time slots (or channels) of the received TDM signal  700 . By reusing time-slots it is possible to maximize the capacity of the overall system. 
     Shown in FIG. 8 is another embodiment of a network node having a overwrite/replace channel capability. The circuit of FIG. 8 is the same as that of FIG. 7 except that instead of first clearing and then replacing a data channel as in FIG.7, the data channel is overwritten directly in FIG.  8 . In FIG. 8 only a single electrode  802  is needed in phase modulator  801 . The circuits  701 ,  703 ,  706  and  707  operate as previously described. The outputs from channel reset  707  and flip-flop  706  are connected to an exclusive-OR circuit  803 . The output from exclusive-OR circuit  803  is a new data channel signal having the proper channel timing. The new data channel signal is applied to the single electrode  802  of phase modulator  801  to overwrite the selected channel to be replaced. 
     What has been described is merely illustrative of the application of the principles of the present invention. Other arrangements and methods can be implemented by those skilled in the art without departing from the spirit and scope of the present invention.