Abstract:
A charge-redistribution low-swing differential logic circuit combining a differential logic network and a charge-redistribution circuit so as to provide a pair of complementary signals having only a small difference, thereby avoiding a time delay. Further, after a sense amplifier is used to amplify the signals, the resulting signals are outputted to sequential differential logic network, wherein the output swing can be reduced by a threshold voltage V tn  (V tp ) on a transistor. In addition, a pipeline is formed by the series connection structure controlled by a true-single-phase clock or by pseudo-single-phase clock, thereby achieving a designed circuit having high-speed and low power dissipation.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a differential logic circuit, and more particularly to a charge-redistribution low-swing differential logic circuit. 
     2. Description of the Related Art 
     For a current logic system, especially in design for a complicated high-speed circuit, a differential logic circuit is adopted in order to achieve both true signal and its complementary signal. For example, as shown in FIG. 1, in U.S. Pat. No. 4,570,084, this logic system comprises logic networks  10  and  12  each acting as a switch so that when logic network  10  is closed, logic network  12  is open. Input signal INPUTS and its complementary signal COMPLEMENTARY INPUTS are applied to logic networks  10  and  12 , respectively, for controlling its switching operation in networks  10  and  12 . Network  10  is connected between an output node  14  and a NMOS pull down transistor  16  connected to ground. Network  12  is connected between an output node  18  and a NMOS pull down transistor  20  connected to ground. A clock pulse φ c  is applied to the control of whether or not the transistors  16  and  20  are active. 
     A load circuit  22  comprises PMOS transistors  24  and  26  connected between a source of potential Vdd and output node  14 , and PMOS transistors  28  and  30  connected between source Vdd and output node  18 . An inverter  32  is connected between an output Q and output node  14 . An inverter  34  is connected between a complementary output terminal {overscore (Q)} of terminal Q and output node  18 . Also, clockφ c  is applied to the control of whether or not the transistors  24  and  28  are active. 
     In the operation of precharging and equalizing, clockφ c  is at a potential level of logic 0. This turns off NMOS transistors  16  and  20  and turns on PMOS transistors  24  and  28 . Therefore output node  14  and  18  are precharged to source Vdd. At this time, both output terminals Q and {overscore (Q)} are at logic 0 level through corresponding inverters  32  and  34 . As a result, PMOS transistors  26  and  30  are turned on in order to maintain the conductive state. 
     In the operation of evaluating the information provided by the complementary input signals INPUTS and COMPLEMENTARY INPUTS of its associated logic networks  10  and  12 , clockφ c  is at a potential level of logic 1. This turns on NMOS transistors  16  and  20  and turns off PMOS transistors  24  and  28 . Because network  10  is closed, output node  14  is effectively grounded. Because network  12  is open, output node  18  is prevented from discharging so as to maintain at logic 1 level. At this time, output terminal Q is at logic 1 level through inverter  32  and output terminal {overscore (Q)} is at logic 0 level through inverter  34 . As a result, PMOS transistor  26  is maintained in an off condition, and PMOS transistor  30  is maintained in an on condition. 
     In the foregoing conventional art, the complementary output signal pair are obtained by the differential logic circuit at the same time; additionally, its full swing is from source Vdd to ground Vss. 
     In current SRAM or DRAM applications, a sense amplifier is often used to detect and amplify an input signal pair; for example an input signal pair from a bit line and its complementary bit line, which have a slight voltage difference, such as a difference of about 100 mV. 
     Hereinafter, the schematic diagrams of FIG.  2  through FIG. 6 are used to depict the corresponding prior art applications. 
     Referring to FIG. 2A, as described in U.S. Pat. No. 4,843,264, a sense amplifier is used to rapidly amplify the difference between input signal IN and its complementary input signal INB. In the configuration of FIG. 2A, input signal pair IN and INB are coupled to two NMOS sensing transistors M 5  and M 6 . A latch is formed by two cross coupled CMOS inverters M 1 -M 3  and M 2 -M 4 , wherein a common gate input G 1  of M 2  and M 4  are coupled to node n 1 , which is formed by the source-drain series connection of M 1  and M 3 , thereby providing a complementary output signal OUTB. Likewise, a common gate input G 2  of M 1  and M 3  are coupled to node n 2  which is formed by the source-drain series connection of M 2  and M 4 , thereby providing an output signal OUT. Nodes n 3  and n 4  couple the sources of the NMOS pull down transistors M 3  and M 4  to the drains of the NMOS sensing transistors M 5  and M 6 , respectively. Pull down transistor M 7  is activated when sensing is to be performed. 
     Referring to FIG. 2B, a sense amplifier combining with precharging and equalizing circuitry is illustrated. During precharging, since PMOS transistors M 13 , M 14 , and M 17  constitute a precharge circuit and equalizing signal EQB is at logic 0 level, transistors M 13 , M 14 , and M 17  are turned on, which will consequently activate nodes n 1 , n 2  being precharged by equalizing signal EQB to Vdd and so equalized. Likewise, PMOS transistors M 18 , M 19 , and M 20  also constitute a precharge circuit, therefore nodes n 3 , n 4  are precharged by equalizing signal EQB to Vdd and so equalized. Further, during sensing, equalizing signal EQB is at logic 1 level, which will consequently disable two precharge circuits, then transistor M 7  is turned on by control signal SE to pull down the potential on node n 5 . Assume that the voltage on signal IN is 100 mV higher than the voltage on signal INB, thereby producing a current difference between transistor M 5  and transistor M 6 . The gate-to-source voltage of transistor M 5  is higher than that of transistor M 6 . As a result, when sensing begins, node n 3  will begin pulling down sooner than n 4 , and thus node n 1  will be pulled down faster than n 2 . Therefore, the potential on node  4  is higher compared to node  3 , and the potential on node  1  is lower compared to node  2 . Thus, transistor M 4  is less conductive than transistor M 3  because the gate-to-source voltage on M 4  (not shown in figure) will be decreased relative to the gate-to-source voltage on M 3 . The voltage on node n 2  will quickly rise back towards Vdd (OUT) with transistor M 4  beginning to shut down. Finally, the relatively high voltage on node n 2  will keep transistor M 1  off reinforcing the rate at which node n 1  is pulled down to Vss (OUTB). 
     Accordingly, only a small voltage difference is required for detecting an input signal pair. For example, as the voltage on signal IN is 100 mV higher than the voltage on signal INB, two cross coupled CMOS inverters M 1 -M 3  and M 2 -M 4 , which form a latch, will rapidly amplify the signal differential between signal IN and INB, and to thereby latch the sensed voltages into nodes n 1  and n 2  as signals Vss and Vdd, where nodes n 1  and n 2  constitute a complementary signal pair labeled OUTB and OUT. 
     Moreover, because one of the two devices on each of the latch (two cross coupled CMOS inverters M 1 -M 3  and M 2 -M 4 ) will be off, either the pull up transistor (M 1  or M 2 ) or the pull down transistor (M 3  or M 4 ) will be off on each side of the latch. Thus, after the same amplifier has latched, it consumes no d.c. power. The foregoing techniques provide the advantages of low power consumption, high speed operation, and sense amplifier outputting full swing from power Vdd to ground Vss. 
     Referring to FIG. 3A, which is another sense amplifier  9  as described in U.S. Pat. No. 4,910,713. Comparing sense amplifier  9  of FIG. 3A to the one in FIG. 2A, the main difference of both is that two sensing transistors exchange the positions with two lower NMOS transistors of the latch. 
     An input signal pair  15 , 17  of a sense amplifier  9  are coupled to NMOS sensing transistors N 4  and N 5 . A latch is formed by two cross-coupled CMOS inverters  11 , 13 . Inverter  11  with a common gate input G 1  comprises a PMOS pull up transistor P 2  and a NMOS pull down transistor N 1  both coupled in series by a NMOS sensing transistor N 4 . The common gate input G 1  of inverter  11  is coupled to an output node  25 , which is a series connection point of source-to-drain electrode of PMOS transistor P 3  and NMOS transistor N 5 , thereby providing output signal  23 . Likewise, inverter  13  with a common gate input G 2  comprises a PMOS pull up transistor P 3  and a NMOS pull down transistor N 2  both coupled in series by a NMOS sensing transistor N 5 . The common gate input G 2  of inverter  13  is coupled to a complementary output node  27  which is a series connection point of source-to-drain electrode of PMOS transistor P 2  and NMOS transistor N 4 , thereby providing output signal  21 . 
     In addition, inverters  11 , 13  are coupled respectively to source Vdd and ground Vss by the coupling transistors P 1 , P 4 , and N 3 . Two PMOS pull up transistors P 2 , P 3  couple transistors P 1 , P 4  in parallel, respectively. NMOS coupling transistor N 3  is coupled between ground Vss and two inverters  11  and  13  in series. During sensing operations, the gates of all three of the coupling transistors P 1 , P 4 , and N 3  are connected together and are strobed by a control signal AMP STROBE on the line  29 , i.e., during non-sensing operation, a low potential of the signal AMP STROBE on the line  29  will deactivate or electrically isolate the latching pairs of two cross coupled CMOS inverters  11 , 13 , whereas, during sensing operation, a high potential of the signal AMP STROBE on the line  29  will activate the latching pairs of two cross coupled CMOS inverters  11 , 13 . 
     During sensing operation, when NMOS coupling transistor N 3  is activated under a high potential of the signal AMP STROBE on the line  29  and is therefore to be pulled down to ground Vss, PMOS coupling transistors P 1  and P 4  are then simultaneously disabled making the sensing operation perform the same as the processes in FIG.  2 A. Meanwhile, only the voltage difference of input signal pair  15 , 17  is amplified and appeared on the corresponding output nodes  25  and  27 . 
     During non-sensing operation, when NMOS coupling transistor N 3  is deactivated under a low potential of the signal AMP STROBE on the line  29 , PMOS coupling transistors P 1  and P 4  are then simultaneously active. Therefore the output nodes  25  and  27  corresponding to the cross coupled CMOS inverters  11  and  13  are pulled up to source Vdd, and no Vdd-to-Vss path and drain current exist through the CMOS inverters  11  and  13 , thereby avoiding power dissipation. 
     Referring to FIG. 3B, an alternate embodiment is illustrated. An input signal pair  15 ′,  17 ′ of a sense amplifier  9 ′ are coupled to PMOS sensing transistors P 11 , P 12 . A latch is formed by two cross-coupled CMOS inverters  11 ′ and  13 ′ which are coupled to transistors P 11  and P 12 , respectively. Inverter  11 ′ with a common gate input G 1 ′ comprises a NMOS pull up transistor N 16  and a PMOS pull down transistor P 13 . The common gate input G 1 ′ of inverter  11 ′ is coupled to an output node  25 ′, which is a series connection point of the source-to-drain electrode of NMOS transistor N 17  and PMOS transistor P 14  of inverter  13 ′, thereby providing output signal  23 ′. Inverter  13 ′ with a common gate input G 2 ′ comprises a NMOS pull up transistor N 17  and a PMOS pull down transistor P 14 . The common gate input G 2 ′ of inverter  13 ′ is coupled to an output node  27 ′, which is a series connection point of the source-to-drain electrode of NMOS transistor N 16  and PMOS transistor P 13  of inverter  11 ′, thereby providing complementary output signal  21 ′. 
     In addition, inverters  11 ′,  13 ′ are coupled respectively to source Vdd and ground Vss by the coupling transistors N 15 , N 18 , and P 10 . NMOS transistor N 16  of inverter  11 ′ and NMOS transistor N 17  of inverter  13 ′ are coupled to transistors N 15  and N 18  in parallel, respectively. PMOS coupling transistor P 10  is coupled between source Vdd and two inverters  11 ′ and  13 ′ in series. During sensing operations, the gates of all three of the coupling transistors N 15 , N 18 , and P 10  are connected together and are strobed by a control signal  31 , i.e., during non-sensing operation, a high potential of the control signal  31  will deactivate or electrically isolate the latching pairs of two cross coupled CMOS inverters  11 ′,  13 ′, whereas, during sensing operation, a low potential of the control signal  31  will activate the latching pairs of two cross coupled CMOS inverters  11 ′,  13 ′. 
     As noted above, during sensing operation, when PMOS coupling transistor P 10  is activated under a low potential of the control signal  31  and is therefore to be pulled up to source Vdd, NMOS coupling transistors N 15  and N 18  are then simultaneously disabled making the sensing operation perform the same as the processes in FIG.  2 A. Meanwhile, only the voltage difference of input signal pair  15 , 17  is amplified and sequentially appearing on the corresponding output nodes  25  and  27 . 
     During non-sensing operation, when PMOS coupling transistor P 10  is deactivated under a high potential of the control signal  31 , NMOS coupling transistors N 15  and N 18  are then simultaneously active. Therefore the output nodes  25 ′ and  27 ′ corresponding to the cross coupled CMOS inverters  11 ′ and  13 ′ are pulled down to ground Vss, and no Vdd-to-Vss path and drain current exists through the CMOS inverters  11 ′ and  13 ′, thereby avoiding power dissipation. 
     In the conventional sensing operation as described above, when a pair of input signals are amplified up to full swing from the potential of power source to the potential of ground, the sensing amplifier will output the corresponding output pair of input signal pair. Therefore, when the delay time for pulling up from the potential of power source to the potential of ground is longer, this design will not work well for a high-speed device such as a memory. To improve the above, an alternate conventional technique is applied, wherein the sense amplifier will output the correspondingly resulting signal pair as soon as the input signal pair is amplified up to an acceptable level having a small difference between input signals. 
     Referring to FIGS. 4A and 4B, in the article in “IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 29, NO. 12. DECEMBER 1994” by Mastaka Matsui etc., there is disclosed an alternate sensing-amplifying technique. The sensing-amplifying technique combines NMOS dynamic differential logic network, for example, DPTL (differential pass transistor logic) or CPL (complementary pass transistor), with SA-FF (sense amplifying pipeline flip-flop circuit), wherein the basic concept of SA-FF is that a sense amplifier is merged into a latch which is synchronous to system clock CLK. SA-FF amplifies low-swing differential (ΔVin) inputs D, {overscore (D)}. Here, Q, {overscore (Q)} are the full-swing outputs of SA-FF. In this case, there is no need of additional inverter to generate a local clock with the opposite polarity because SA-FF can be operated in the control of a true single-phase clock. 
     In an operating manner, combinational logic mainly outputs the signals A, B to an NMOS differential logic network. Differential inputs D, {overscore (D)} are generated from the NMOS differential logic network controlled by a φp pulse. The differential inputs D, {overscore (D)} are pre-discharged to ground while pulse φp is active at logic 1 potential in a pre-discharging state. The foregoing outputs Q, {overscore (Q)} of SA-FF latch the result last time while complementary system clock {overscore (CLK)} is at logic 1 potential; pulse φp is at logic 0 potential for evaluation of the logic network, therefore NMOS differential logic network has the outputs with a difference ΔVin (about 100 mV) from inputs D, {overscore (D)}. At this time, as soon as clock {overscore (CLK)} transits from logic 1 to the falling edge of logic 0, SA-FF is activated immediately without waiting for the difference ΔVin further developed and performs the sense-amplified and latch operation for inputs, thereby obtaining a complementary pair of differential outputs Q, {overscore (Q)}. Alternately, during clock {overscore (CLK)} remaining on logic 0 potential, the difference ΔVin is further developed. Because only NMOS logic is adopted, the full-swing of inputs D, {overscore (D)} is the difference Vdd-Vtn between Vss-to-Vdd (not shown) and NMOS transistor threshold voltage Vtn (about 700 mV). 
     NMOS differential logic is mainly used in the circuit mentioned above. With the circuit of pre-discharging to ground during non-sensing, one of input signals D, {overscore (D)} will be pulled up from ground to the difference Vdd-Vtn between source Vdd and NMOS transistor threshold voltage Vtn. Also, when the difference ΔVin of inputs D, {overscore (D)} is a small value (about 100 mV), SA-FF is active immediately and performs the sense-amplified and latch operation, thereby obtaining a complementary output pair Q, {overscore (Q)}. But, it is disadvantageous in a low-frequency device for one of inputs D, {overscore (D)} to be pulled up continually from Vss to Vdd-Vtn when pulse φp remains on logic 0 potential for a long time, thereby suffering from high power dissipation. 
     Referring to FIG. 5, in the article in “1998 Symposium on VLSI Circuits Digest of Technical Papers”, there is disclosed a sense-amplifier SA combined with isolated transistors I 1 , I 2 , wherein the sense-amplifier SA comprises cross-coupled CMOS inverters M 41 , M 42 , M 43 , M 44 , and NMOS pull down transistor M 45 . 
     During non-sensing, bit line BL and its complementary bit line{overscore (BL)} is charged to source potential. Meanwhile, isolated signal ISO is at logic 0 potential, therefore isolated transistors I 1 , I 2  are turned on, and nodes Al′, A 2 ′ are charged to a source potential. During sensing, one of the complementary bit line pair BL, {overscore (BL)} will be pulled down so that the voltage difference is developed to a constant difference such as 100 mV. Also, one of nodes A 1 ′, A 2 ′ will therefore be pulled down. Sequentially, isolated signal ISO is at logic 1 potential, therefore nodes A 1 ′, A 2 ′ are isolated due to isolated transistors I 1 , I 2 . The sense-amplifier is enabled after pull down transistor M 45  is active under signal SET at logic 1 potential. As a result, the output terminal of NAND gate A 1  on the side of the complementary bit line {overscore (BL)} outputs a true signal, and the output terminal of NAND gate A 2  on the side of the bit line BL outputs the true signal complement. 
     Namely, during sensing operation, one of the input signal pair will be pulled down to ground as mainly mentioned above. Then, input terminals BL, {overscore (BL)} as soon as they have only a small difference such as 100 mV, are isolated by transistors I 1 , I 2  and immediately sense-amplified and latched by the sense-amplifier, thereby obtaining a complementary differential output pair. However, it is disadvantageous when the power is continuously dissipated by pulling down one of input signal pair BL, {overscore (BL)} from source to ground. 
     In addition, referring to  6 A- 6 B, in the article in “IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 4. APRIL 1995” by Mitsuru Hiraki etc., there is disclosed a DDL bus (data-dependent logic bus) technique, which reduces its voltage swing using charge sharing between bus wires and an additional bus wire such as a dummy ground wire. First, according to a conventional n-bit bus of FIG. 6A, the voltage swing of bus signals coincides with the supply voltage Vdd. Thus, the bus power dissipation P required to switch n bits of the bus signals is given by: 
     
       
         P=n*f*Cw*V 2 dd 
       
     
     where f and Cw are the switching frequency and wiring capacitance. 
     According to a n-bit bus signals of FIG. 6B, after adding a dummy ground bus wire (which is grounded at initial, then floated), the voltage swing of DDL bus wires based on n-bit charge sharing is reduced to Vdd/n+1, and the bus power dissipation required to switch the n-bit bus signals is reduced to P′: 
     
       
         P′=[(n)/(n+1)]*f*Cw*V 2 dd 
       
     
     In the foregoing conventional scheme, because each bit of the n-bit bus signals is different at logic 0 potential (for it is not the real ground potential), an alternate sense-amplifier is applied to sense and amplify the bus signals. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a charge-redistribution low-swing differential logic circuit. This circuit combines a differential logic network and a charge-redistribution circuit so as to provide a pair of complementary signals having only a small difference, thereby avoiding a time delay. Further, after a sense-amplifier is used to amplify the signals, the resulting signals are then outputted to a differential logic network, wherein the output swing can be reduced by a threshold voltage V tn  (V tp ) on a transistor. In addition, a pipeline is formed by a series connection structure controlled by a true-single-phase clock or by a pseudo-single-phase clock, thereby achieving a designed circuit having high-speed and low power dissipation. 
     The present invention provides a charge-redistribution low-swing differential logic circuit comprising: a charge-redistribution circuit including a first CMOS transistor and a second CMOS transistor, each coupled to a first potential terminal, wherein the gates of two CMOS transistors are coupled together to receive a clock pulse which is used to control the first and second CMOS transistors, thereby outputting a first complementary signal pair; a differential logic network having a first train of a plurality of nodes and a second train of a plurality of nodes, each train being respectively coupled between one of the first complementary signal pair and a second potential terminal, wherein one of the first complementary signal pair performs the charge-redistribution with one of the two trains of a plurality of nodes, and there is an input voltage difference between the first and second potential; a sense amplifier, coupled between the first and second potential, which is controlled by the clock pulse to sense and amplify the voltage difference of the first complementary signal pair, then to output a second complementary signal pair; and a precharge circuit, controlled by the clock pulse, and used by the sense amplifier before sensing for precharging terminals of the second complementary signal pair to a third potential with a value between the first and second potential. 
     The present invention provides another charge-redistribution low-swing differential logic circuit comprising: a charge-redistribution circuit, including a first transistor pair with a first common gate node connected to a clock, and a second transistor pair with a second common gate node connected to a complementary signal of the clock, wherein, the first transistor pair, coupled in series between a first potential and the second transistor pair, is controlled by the clock, and the second transistor pair is controlled by the complementary signal for outputting a first complementary signal pair; a differential logic network having a first train of a plurality of nodes and a second train of a plurality of nodes, each train being respectively coupled between one of the first complementary signal pair and a second potential, wherein one of the first complementary signal pair performs the charge-redistribution with one of the two trains, and there is a voltage difference between the first and second potential; a sense amplifier, coupled between the first and second potential, which is controlled by the clock to sense and amplify the voltage difference of the first complementary signal pair, then to output a second complementary signal pair; and a precharge circuit, controlled by the clock, and used by the sense amplifier before sensing for precharging terminals of the second complementary signal pair to a third potential that is between the first and second potential. 
     The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limited of the present invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates A block diagram of a conventional differential logic system; 
     FIGS. 2A-2B illustrate A block diagram of a conventional sense-amplifier circuit; 
     FIGS. 3A-3B illustrate A block diagram of another conventional sense-amplifier circuit; 
     FIG. 4A illustrates A block diagram of a circuit typically combining a NMOS differential logic system and a sense-amplifier; 
     FIG. 4B illustrates timing charts of the operation in FIG.  4 A. 
     FIG. 5 illustrates A block diagram of a conventional sense-amplifier circuit with isolated transistors; 
     FIG. 6A illustrates a schematic diagram of a conventional n-bit bus wire circuit with true ground; 
     FIG. 6B illustrates a schematic diagram of a conventional n-bit bus wire circuit with dummy ground; 
     FIG. 7A is a schematic diagram of a first A block circuit illustrating a charge-redistribution low-swing differential logic circuit of the present invention; 
     FIG. 7B is a schematic diagram of a first B block circuit illustrating the charge-redistribution low-swing differential logic circuit of the present invention; 
     FIG. 7C illustrates timing charts of the operation in the charge-redistribution low-swing differential logic circuit of FIGS. 7A and 7B; 
     FIG. 7D illustrates schematic block diagrams of the charge-redistribution low-swing differential logic circuit of FIGS. 7A and 7B in series connection structure controlled by a true-single-phase clock; 
     FIG. 8A is a schematic diagram of a second A block circuit illustrating the charge-redistribution low-swing differential logic circuit of the present invention; 
     FIG. 8B is a schematic diagram of a second B block circuit illustrating the charge-redistribution low-swing differential logic circuit of the present invention; 
     FIG. 9A is a schematic diagram of a third A block circuit illustrating the charge-redistribution low-swing differential logic circuit of the present invention; 
     FIG. 9B is a schematic diagram of a third B block circuit illustrating the charge-redistribution low-swing differential logic circuit of the present invention; 
     FIG. 10A is a schematic diagram of a fourth A block circuit illustrating the charge-redistribution low-swing differential logic circuit of the present invention; 
     FIG. 10B is a schematic diagram of a fourth B block circuit illustrating the charge-redistribution low-swing differential logic circuit of the present invention; 
     FIG. 10C illustrates timing charts of the operation in the charge-redistribution low-swing differential logic circuit of FIGS. 10A and 10B; 
     FIG. 10D illustrates schematic block diagrams of the charge-redistribution low-swing differential logic circuit of FIGS. 10A and 10B in series connection structure controlled by a true-single-phase clock; and 
     FIG. 11 illustrates schematic block diagrams of the present invention in series connection structure controlled by a pseudo-single-phase clock φ, {overscore (φ)}. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     For easy description, the same reference numerals in drawings indicate the same elements. The present invention assumes that a first potential indicates a power potential and a second potential indicates a ground potential. In addition, a third potential has a value between the first and second potential. 
     Charge-redistribution low-swing differential logic circuits of the present invention are illustrated in FIGS. 7A and 7B, wherein FIGS. 7A,  7 B illustrate first A and B block circuits, respectively. Also, FIG. 7C illustrates timing charts of the operation in FIGS. 7A,  7 B, and FIG. 7D illustrates the blocks in a series connection structure controlled by a true-single-phase clock. 
     First, referring to FIG. 7A, the A block circuit comprising: a charge-redistribution circuit  100 , a NMOS differential logic network  120 , a sense-amplifier  160 , and a precharge circuit  180 . 
     The charge-redistribution circuit  100  has a CMOS transistor including a PMOS transistor PP 1   a  and a NMOS transistor NC 1   a , both coupled in series and having a common gate input G 1 , and another CMOS transistor including a PMOS transistor PP 2   a  and a NMOS transistor NC 2   a , both coupled in series and having a common gate input G 2 , wherein the two PMOS transistors PP 1   a , PP 2   a  are coupled in series between source Vdd and the NMOS transistors NC 1   a , NC 2   a , respectively, and the common gate inputs G 1 , G 2  are coupled together to receive a true-single-phase clock φ. 
     The NMOS differential logic network  120  is coupled between the NMOS transistors NC 1   a , NC 2   a  and ground Vss. 
     Furthermore, because a full-swing output signal is necessary, the same sense amplifier in FIG. 2A is adapted for the use of a low voltage operation. The sense-amplifier  160  includes sub-elements described as follows: a pair of sensing PMOS transistors PI 1   a , PI 2   a , a pull-up PMOS transistor PC 1   a , and two CMOS transistors. The pair of sensing PMOS transistors PI 1   a , PI 2   a  have gate inputs g 1 , g 2 , respectively. Gate inputs g 1 ,  92  are coupled in series between the NMOS transistors NC 1   a , NC 2   a  and the NMOS differential logic network  120 , respectively. A pull-up PMOS transistor PC 1   a  is coupled in series between source Vdd and the sensing PMOS transistors PI 1   a , PI 2   a  and its gate input g 3  is used to receive the true-single-phase clock φ. 
     One of the CMOS transistors of the sense-amplifier  160  includes a PMOS transistor PS 1   a  and a NMOS transistor NS 1   a , both coupled in series between ground Vss and the sensing PMOS transistor PI 1   a , thereby having a common gate input G 3 , and the another CMOS transistor includes a PMOS transistor PS 2   a  and a NMOS transistor NS 2   a , both coupled in series between the ground Vss and the sensing PMOS transistor PI 2   a , thereby having a common gate input G 4 , wherein the two NMOS transistors NS 1   a , NS 2   a  are coupled in series between ground Vss and the PMOS transistors PS 1   a , PS 2   a , respectively. In addition, the common gate input G 3  is connected to a series connection node where the PMOS transistor PS 2   a  is connected in series to the NMOS transistor NS 2   a , so as to output a first output L, and the common gate input G 4  is connected to a series connection node where the PMOS transistor PS 1   a  is connected in series to the NMOS transistor NS 1   a , so as to output a second output {overscore (L)}. 
     The precharge circuit  180 , coupled between ground Vss and the first and second outputs L, {overscore (L)}, has a pair of precharging NMOS transistors NP 1   a , NP 2   a  coupled in parallel with the NMOS transistors NS 1   a , NS 2   a , respectively. 
     Referring to FIG. 7B, the B block circuit comprising: a charge-redistribution circuit  200 , a PMOS differential logic network  220 , a sense amplifier  260 , and a precharge circuit  280 . 
     The charge-redistribution circuit  200  has a CMOS transistor including a NMOS transistor NP 1   b  and a PMOS transistor PC 1   b , both coupled in series and thereby having a common gate input G 1 , and another CMOS transistor including a NMOS transistor NP 2   b  and a PMOS transistor PC 2   b , both coupled in series and thereby having a common gate input G 2 , wherein two NMOS transistors NP 1   b , NP 2   b  are coupled in series between ground Vss and the PMOS transistors PC 1   b , PC 2   b , respectively, and the common gate inputs G 1 , G 2  are coupled together to receive a true-single-phase clock {overscore (φ)}. 
     The PMOS differential logic network  220  is coupled between the PMOS transistors PC 1   b , PC 2   b  and source Vdd. 
     Furthermore, because a full-swing output signal is necessary, the same sense amplifier in FIG. 2A is adapted for the use of a low voltage operation. The sense-amplifier  260  includes sub-elements described as follows: a pair of sensing NMOS transistors NI 1   b , NI 2   b , a pull-down NMOS transistor NC 1   b , and two CMOS transistors. The pair of sensing NMOS transistors NI 1   b , NI 2   b  have gate inputs g 1 , g 2 , respectively. Gate inputs g 1 , g 2  are coupled in series between the PMOS transistors PC 1   b , PC 2   b  and the NMOS differential logic network  220 , respectively. The pull-down NMOS transistor NC 1   b  is coupled in series between ground Vss and the sensing NMOS transistors NI 1   b , NI 2   b  and its gate input g 3  is used to receive the true-single-phase clock φ. 
     One of the CMOS transistors of the sense-amplifier  260  includes an NMOS transistor NS 1   b  and a PMOS transistor PS 1   b , both coupled in series between ground Vss and the sensing NMOS transistor NI 1   b , thereby having a common gate input G 3 , and the other CMOS transistor includes a NMOS transistor NS 2   b  and a PMOS transistor PS 2   b , both coupled in series between source Vdd and the sensing NMOS transistor NI 2   b , thereby having a common gate input G 4 , wherein two PMOS transistors PS 1   b , PS 2   b  are coupled in series between source Vdd and the NMOS transistors NS 1   b , NS 2   b , respectively. In addition, the common gate input G 3  is connected to a series connection node where the NMOS transistor NS 2   b  is connected in series to the PMOS transistor PS 2   b , so as to output a first output H, and the common gate input G 4  is connected to a series connection node where the NMOS transistor NS 1   b  is connected in series to the PMOS transistor PS 1   b , so as to output a second output {overscore (H)}. 
     The precharge circuit  280 , coupled between source Vdd and the first and second outputs H, {overscore (H)}, has a pair of precharging PMOS transistors PP 1   b , PP 2   b  coupled in parallel with the PMOS transistors PS 1   b , PS 2   b , respectively. 
     Referring to FIG. 7D, both the first A or B block circuits are controlled by a true-single-phase clock φ. For example, when the true-single-phase clock φ transits from logic 1 to logic 0, the sense-amplifier  160  of the first A block circuit is active and outputs an amplified complementary signal pair L, {overscore (L)} to the PMOS differential logic network  220  of the first B block circuit. At this time, the full swing is the value from ground Vss to source Vdd. Likewise, when the true-single-phase clock φtransits from logic 0 to logic 1, the sense-amplifier  260  of the first B block circuit is active and outputs an amplified complementary signal pair H, {overscore (H)} to the NMOS differential logic network  120  of the first A block circuit. At this time, the full swing is the value from source Vdd to ground Vss. 
     Timing of the present invention is illustrated in FIG.  7 C. When the true-single-phase clock φ is pulled up from logic 0 to logic 1, the first B block circuit outputs the signal pair H, {overscore (H+L , )} to the next first A block circuit. On the contrary, when the true-single-phase clock φ is pulled down from logic 1 to logic 0, the first A block circuit outputs the signal pair L, {overscore (L)} to the next first B block circuit. Both are described in detail as follows. 
     (1) First, when the true-single-phase clock φ is pulled up from logic 0 to logic 1, the first B block circuit outputs the signal pair H, {overscore (H+L , )} to the next first A block circuit. 
     When the true-single-phase clock φ is at logic 0 potential, in the first A block circuit, nodes A, {overscore (A)} are precharged to the first potential level, i.e., to the source Vdd level, while the PMOS transistors PP 1   a , PP 2   a  are active. In the first B block circuit, output nodes H, {overscore (H+L , )} are precharged to the source Vdd level while the PMOS transistors PP 1   b , PP 2   b  are active. Therefore, the NMOS differential logic network  120  in the first A block circuit is active, therefore a plurality of internal nodes X, {overscore (X)} of the NMOS differential logic network  120  and nodes B, {overscore (B)} are discharged to the second potential level, i.e., to the ground Vss level. 
     When the true-single-phase clock φ is pulled up from logic 0 to logic 1, in the first B block circuit, the sense-amplifier  260  is active so as to turn off the PMOS transistors PP 1   b , PP 2   b . Therefore, the complementary signal pair on output nodes H, {overscore (H+L , )} are amplified and outputted to the NMOS differential logic network  120  in the first A block circuit. Here, assume that output node {overscore (H)} is pulled down to the ground Vss level. 
     When the true-single-phase clock φ is on logic 1 potential, in the first A block circuit (FIG. 7 A), nodes A, {overscore (A)} and B, {overscore (B)}, and a plurality of internal nodes X, {overscore (X)} of the NMOS differential logic network  120  are electrically connected respectively while the NMOS transistors NC 1   a , NC 2   a  are active. Because output nodes H, {overscore (H+L , )} connected to the NMOS differential logic network  120  output a pair of complementary signals (such as in a situation that output node H maintains on the source potential Vdd while output node {overscore (H)} in the first B block circuit is pulled down to the ground potential Vss), in both sides of internal nodes X, {overscore (X)} of the NMOS differential logic network  120 , only one of both sides is active at a time. Nodes A, B, and X are equal to zero (i.e., node A=B=X=0) if left node X is active. For node {overscore (B)} and a portion of internal node {overscore (X)} of the NMOS differential logic network  120  are not connected to the ground Vss, the charge on node {overscore (A)} is distributed onto node {overscore (B)} and a portion of internal node {overscore (X)} of the NMOS differential logic network  120 . Assume that the voltage difference (swing) between nodes A, {overscore (A)} is VCR,N, capacitance C1 on node {overscore (A)} and capacitance C2 on both of node {overscore (B)} and a portion of internal node {overscore (X)} of the NMOS differential logic network  120 . In addition, the charge conservation equation is: 
     
       
         C1×Vdd=(C1+C2)×VCR,N 
       
     
     Therefore VCR,N=[C1/(C1+C2)]×Vdd 
     According to the equation, in a complicated NMOS differential logic network  120 , C2 is much greater than C1 (i.e., C2&gt;&gt;C1) so as to achieve a voltage difference between nodes A, {overscore (A)} that is slight but sufficient to be sensed by the sense amplifier, and thus to avoid sequentially sensing time delay. 
     (2) Second, when the true-single-phase clock φ is pulled down from logic 1 to logic 0, the first A block circuit outputs the signal pair L, {overscore (L)} to the next first B block circuit. 
     When the true-single-phase clock φ is at logic 1 potential, outputs L, {overscore (L)} of the first A block circuit are pre-discharged to the second potential level, i.e., to the ground Vss level, while the NMOS transistors PP 1   a , PP 2   a  of the precharge circuit  180  are active. 
     When the true-single-phase clock φ is pulled down from logic 1 to logic 0, in the first B block circuit (FIG.  7 B), the sense-amplifier  160  is active so as to turn off the NMOS transistors NP 1   a , NP 2   a . Therefore, the complementary signal pair on output nodes L, {overscore (L)} are amplified and outputted to the NMOS differential logic network  220  in the first B block circuit. Assume that output node L is pulled up to the source Vdd level. 
     When the true-single-phase clock φ is on logic 0 potential, in the first B block circuit, nodes C, {overscore (C)} and D, {overscore (D)} and a plurality of internal nodes Y, {overscore (Y)} of the NMOS differential logic network  220  are electrically connected respectively while the PMOS transistors PC 1   b , PC 2   b  are active. Because output nodes L, {overscore (L)} connected to the PMOS differential logic network  220  output a pair of complementary signals (i.e., in a condition that output node {overscore (L)} maintains on the ground potential Vss while output node L in the first A block circuit is pulled up to the source potential Vdd), on both sides of internal nodes Y, {overscore (Y)} of the PMOS differential logic network  220 , only one of both sides is active at a time. Nodes C, D, and Y are equal to Vdd (i.e., node C=D=Y=Vdd) if left node Y is active. For node {overscore (D)} and a portion of internal node {overscore (Y)} of the PMOS differential logic network  220  are not connected to the source Vdd, the charge on node is distributed onto node {overscore (D)} and a portion of internal node {overscore (Y)} of the PMOS differential logic network  220 . Assume that the voltage difference (swing) between nodes C, {overscore (C)} is VCR,P, capacitance C3 on node {overscore (C)} and capacitance C4 on both of node {overscore (D)} and a portion of internal node {overscore (Y)} of the PMOS differential logic network  220 . In addition, the charge conservation equation is: 
     
       
         C3×Vdd=(C3+C4)×VCR,P 
       
     
     Therefore VCR,P=[C3/(C3+C4)]×Vdd 
     According to this equation, complicated PMOS differential logic network  220 , C4 is much greater than C3 (i.e., C4&gt;&gt;C3) so as to achieve a voltage difference between nodes C, {overscore (C)} that is slight but sufficient to be sensed by the sense amplifier, and thus to avoid sequentially sensing time delay. 
     Charge-redistribution low-swing differential logic circuits are illustrated as follows in FIGS. 8A to  8 B, wherein FIG. 8A illustrates a second A block circuit and FIG. 8B illustrates a second B block circuit. In the circuit of  8 A, the charge-redistribution circuit  100  of the first A block circuit is replaced with charge-redistribution circuit  100 ′ to simplify the layout design. The circuit  100 ′ includes two NMOS inverters, wherein one of two NMOS inverters is formed by NMOS transistors NP 1   c , NC 1   c  coupled in series, and the other of two NMOS inverters is formed by NMOS transistors NP 2   c , NC 2   c  coupled in series. In addition, transistors NP 1   c , NP 2   c  are coupled in series between source Vdd and transistors NC 1   c , NC 2   c , respectively. Transistors NC 1   c , NC 2   c  have a common gate input G 1 ′ to receive a true-single-phase clock φ, and transistors NP 1   c , NP 2   c  have a common gate input G 2 ′ to receive a complementary clock φ. 
     The layout design for the above can be easily made by replacing PMOS transistors PP 1   a , PP 2   a  of FIG. 7A with NMOS transistors NP 1   c , NP 2   c  of FIG.  8 A. Therefore, node A (or {overscore (A)}) is precharged only to a third potential, i.e., a difference Vdd−Vtn (not source voltage) between source voltage Vdd and threshold voltage Vtn (about 0.7 Volts) of NMOS transistor (NP 1   c ,NP 2   c ), which can reduce the power dissipation. 
     Similarly, in the second B block circuit of  8 B, the charge-redistribution circuit  200  of the first B block circuit of FIG. 7B is replaced with charge-redistribution circuit  200 ′ to simplify the layout design. The circuit  200 ′ includes two PMOS inverters, wherein one of two PMOS inverters is formed by PMOS transistors PP 1   d , PC 1   d  coupled in series, and the other of two PMOS inverters is formed by PMOS transistors PP 2   d , PC 2   d  coupled in series. In addition, transistors PP 1   d , PP 2   d  are coupled in series between ground Vss and transistors PC 1   d , PC 2   d , respectively. Transistors PC 1   d , PC 2   d  have a common gate input G 1 ′ to receive the true-single-phase clock φ, and transistors PP 1   d , PP 2   d  have a common gate input G 2 ′ to receive the complementary clock φ. 
     The layout design for the above is easily made by replacing NMOS transistors NP 1   b , NP 2   b  of FIG. 7B with PMOS transistors PP 1   d , PP 2   d  in FIG.  8 B. Therefore, node C (or {overscore (C)}) is pre-discharged only to a third potential, i.e., threshold voltage |Vtp| of PMOS transistor (PP 1   d ,PP 2   d ) (not ground voltage), which can reduce the power dissipation. 
     Charge-redistribution low-swing differential logic circuits of the present invention are illustrated as following in FIGS. 9A to  9 B. FIGS. 9A,  9 B illustrate a third A and B block circuits, respectively. The difference between FIG. 7A and 9A is that the charge-redistribution circuit  100  of the first A block circuit is replaced with charge-redistribution circuit  100 ″ to simplify the layout design. The circuit  100 ″ includes two PMOS inverters, wherein one of two PMOS inverters is formed by PMOS transistors PP 1   e , PC 1   e  coupled in series, and the other of two PMOS inverters is formed by PMOS transistors PP 2   e , PC 2   e  coupled in series. In addition, transistors PP 1   e , PP 2   e  are coupled in series between source Vdd and transistors PC 1   e , PC 2   e . Transistors PP 1   e , PP 2   e  have a common gate input G 1 ″ to receive the true-single-phase clock φ, and transistors PC 1   e , PC 2   e  have a common gate input G 2 ″ to receive the complementary clock φ. 
     The layout design for the above is easily made by replacing NMOS transistors NC 1   a , NC 2   a  in FIG. 7A with PMOS transistors PC 1   e , PC 2   e  in FIG.  9 A. Therefore, node A (or {overscore (A)}) is precharged to the first voltage potential, i.e., the source voltage Vdd, hence, the potential is pulled down only to the third potential, i.e., the voltage potential |Vtp| (PC 1   e , PC 2   e ) when the true-single-phase clock φ is pulled down from logic 1 to logic 0, which can reduce the power dissipation. 
     Similarly, the difference between FIGS. 9B and 7B is that the charge-redistribution circuit  200  of the first B block circuit is replaced with charge-redistribution circuit  200 ″ to simplify the layout design. Circuit  200 ″ includes two NMOS inverters, wherein one of two NMOS inverters is formed by NMOS transistors NP 1   f , NC 1   f  coupled in series, and the other of two NMOS inverters is formed by NMOS transistors NP 2   f , NC 2   f  coupled in series. In addition, transistors NP 1   f , NP 2   f  are coupled in series between ground Vss and transistors NC 1   f , NC 2   f . Transistors P 1   f , NP 2   f  have a common gate input G 1 ″ to receive the true-single-phase clock φ, and Transistors NC 1   f , NC 2   f  have a common gate input G 2 ″ to receive the complementary clock {overscore (φ)}. 
     The layout design for the above is easily made by replacing PMOS transistors PC 1   b , PC 2   b  in FIG. 7B with NMOS transistors NC 1   f , NC 2   f  in FIG.  9 B. Therefore, node {overscore (C)} (or C) is precharged to the source voltage Vdd, hence, the potential of node {overscore (C)} (or C) is pulled up only to the third potential Vdd−Vtn (NC 1   f , NC 2   f ) when the true-single-phase clock φ is pulled up from logic 0 to logic 1, which can reduce the power dissipation. 
     Charge-redistribution low-swing differential logic circuits are illustrated as following in FIGS. 10A to  10 B. FIGS. 10A,  10 B illustrate fourth A and B block circuits, respectively. The difference between FIGS. 10A and 7A is that the sense amplifier  160  of the first A block circuit of FIG. 7A is replaced with sense-amplifier  160 ′, so to create the fourth A block circuit. Sense amplifier  160 ′, adapted for the configuration in FIG. 3B, is formed by following elements: two CMOS transistors, a pair of sensing PMOS transistors PI 1   g , PI 2   g , a pull-up PMOS transistor PC 1   g , and a precharge circuit  180 . The difference between the sense-amplifier  160 ′ in FIG.  10 A and the configuration in FIG. 3B is the output node. 
     One of the CMOS transistors is comprised of coupling a PMOS transistor PS 1   g  and a NMOS transistor NS 1   g  in series and thereby having a common gate input G 3 , and the other CMOS transistor is comprised of coupling a PMOS transistor PS 2   g  and a NMOS transistor NS 2   g  in series and thereby having a common gate input G 4 . 
     The pair of sensing PMOS transistors PI 1   g , PI 2   g  have gate inputs g 1 , g 2 , respectively. The NMOS transistors NS 1   g , NS 2   g  are coupled in series between ground Vss and the sensing PMOS transistors PI 1   g , PI 2   g , respectively. And the gate inputs g 1 , g 2  are coupled in series between the NMOS transistors NC 1 , NC 2  and the NMOS differential logic network  120 , respectively. 
     The pull-up PMOS transistor PC 1   g  is coupled in series between source Vdd and the sensing PMOS transistors PI 1   g , PI 2   g  and its gate input g 3  is used to receive true-single-phase clock φ. In addition, a series connection node where the PMOS transistor PS 2   g  is connected to the PMOS transistor PI 2   g , is used for a first output {overscore (L)} of sense amplifier  160 ′, and another series connection node where the PMOS transistor PS 1   g  is connected to the PMOS transistor PI 1   g , is used for a second output {overscore (L)} of sense amplifier  160 ′. 
     The precharge circuit  180 , coupled in parallel with the NMOS transistors NS 1   g , NS 2   g , has a pair of precharging NMOS transistors NP 1   g , NP 2   g  coupled between ground Vss and the sensing PMOS transistors PI 1   g , PI 2   g , respectively, and its gate inputs are used to receive the true-single-phase clock φ. 
     Similarly, the difference between FIGS. 10B and 7B is that the sense amplifier  260  of the first B block circuit of FIG. 7B is replaced with sense-amplifier  260 ′, so to create the fourth B block circuit. Sense amplifier  260 ′, adapted for the configuration in FIG. 3A, is formed by following elements: two CMOS transistors, a pair of sensing NMOS transistors NI 1   h , NI 2   h , a pull-down NMOS transistor NC 1   h , and a precharge circuit  280 . The difference between the sense-amplifier  260 ′ in FIG.  10 B and the configuration in FIG. 3A is the output node. 
     One of the CMOS transistors comprises a NMOS transistor NS 1   h  and a PMOS transistor PS 1   h  coupled in series and thereby having a common gate input G 3 , and the other CMOS transistor comprises a NMOS transistor NS 2   h  and a PMOS transistor PS 2   h  coupled in series and thereby having a common gate input G 4 . 
     The pair of sensing NMOS transistors NI 1   h , NI 2   h  have gate inputs g 1 , g 2 , respectively. The PMOS transistors PS 1   h , PS 2   h  are coupled in series between source Vdd and the sensing NMOS transistors NI 1   h , NI 2   h , respectively. And gate inputs g 1 , g 2  are coupled in series between the PMOS transistors PC 1   h , PC 2   h  and the PMOS differential logic network  220 , respectively. 
     The pull-down NMOS transistor NC 1   h  is coupled in series between ground Vss and the sensing NMOS transistors NS 1   h , NS 2   h  and gate input g 3  is used to receive the true-single-phase clock φ. In addition, a series connection node where the NMOS transistor NS 2   h  is connected to the NMOS transistor NI 2   h , is used for a first output H of sense amplifier  260 ′, and another series connection node where the NMOS transistor NS 1   h  is connected to the NMOS transistor NI 1   h  is used for a second output {overscore (H)} of sense amplifier  260 ′. 
     The precharge circuit  280 , coupled in parallel with the PMOS transistors PS 1   h , PS 2   h , has a pair of precharging PMOS transistors PP 1   h , PP 2   h  coupled between source Vdd and the sensing NMOS transistors NI 1   h , NI 2   h , respectively, and its gate inputs are used to receive the true-single-phase clock φ. 
     FIG. 10D illustrates a series connection structure controlled by the true-single-phase clock the same as that of FIG.  7 D. Also, FIG. 10C illustrates the same operating mode as FIG. 7C except that the voltage swing of output nodes L, {overscore (L)} in the fourth A block circuit is from source voltage Vdd to PMOS transistor threshold voltage |Vtp| but the voltage swing of output nodes H, {overscore (H+L , )} in the fourth B block circuit is the difference Vdd−Vtn between the Vss-Vdd and NMOS transistor threshold voltage Vtn. 
     Furthermore, because a full-swing output signal is necessary, the same output node of the sense-amplifier as shown in FIGS. 3A and 3B is adapted for the use of a low voltage operation. 
     A high-speed pipeline structure is created because the series connection structure is controlled by a true-single-phase clock in the charge-redistribution low-swing differential logic circuit. 
     To illustrate the function of the charge-redistribution low-swing differential logic circuit of FIGS. 8A,  8 B and FIGS. 9A,  9 B, FIG. 11 is provided. Referring to FIG. 11, a series connection train controlled by a pseudo-single-phase clock φ, {overscore (φ)} includes the second A block circuit in FIG. 8A, the second B block circuit in FIG. 8B, the third A block circuit in FIG. 9A, and the third B block circuit in FIG.  9 B. Inverters  300  are used in the series connection structure under the conditions of A and B block connection, some different block circuit type connections, and time of clock φ, {overscore (φ)} transition. 
     When different types of differential logic circuits are connected in series between each other to form a pipeline structure, the input signal for the block has to be ensured in an output state of predetermined phase so that both terminals of the next differential logic network are turned on. For example, the input signal of NMOS differential logic network has a predetermined value “1”, and input signal of PMOS differential logic network has a predetermined value “0”. Therefore, an inverter is added into previous output circuit to turn on the sequential circuit if the predetermined value of previous output circuit turns both terminals of sequential differential logic network off. 
     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.