Abstract:
A circuit for transient voltage clamping, the circuit being internal to a motor driver ASIC for a hard drive and including a power transistor for sinking a power supply voltage subjected to transient variation, a reference circuit for deriving a first reference voltage from a second reference voltage and the power supply voltage, and an amplifier circuit for receiving the first reference voltage as input and for driving the power transistor.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a circuit for transient voltage clamping and, in particular, a circuit for transient voltage clamping within an ASIC that is a motor driver for a disk drive. 
   2. Description of the Related Art 
   In typical hard disk drive (HDD) applications, specific integrated circuits (ASICs) are used for driving the spindle and voice coil motors. Under certain conditions, inductive loads may dump their stored energy (in the form of large currents) on the power supply of the ASIC causing the voltage in the power supply to rise. Reverse isolation blocking diodes are usually provided to prevent the system power supply from absorbing the excess energy. As a result, the drain voltage of the high side drivers may rise to levels which cause the destruction of the ASIC. Therefore a voltage clamp is required to be placed on the supply voltage of the ASIC for reducing the effects of such transient voltages from the inductive loads. 
   In order to address the above-mentioned problem, prior art solutions provide the following: 
   1. A transient voltage suppressor (TVS) can be used externally to the ASIC to clamp the voltage. This increases the cost of the HDD and the voltage tolerance of the TVS is often wide, which can lead to inadequate suppression of transient voltages. For example, if the required TVS operating range is 13.2V (i.e., 12V supply +10%) to 16V (the absolute rating) and TVS voltage tolerance is wide, it may not be able to effectively clamp in the required range. 
   2. An alternative is to put a very large capacitor on the ASIC power supply to absorb the dumped energy. However, such large capacitors are costly. 
   3. A simple voltage clamp circuit consisting of zener-npn or zener-nmos devices can also be used to absorb the dumped energy. Such a circuit can be integrated into the ASIC or may be external. However, the wide tolerance of activation voltage and long response time makes this circuit unsuitable for use in applications where the operating voltage range and the absolute maximum voltage of the ASIC are relatively close to each other. HDDs of small dimension require lower tolerances in activation voltage than are provided by these circuits. 
   BRIEF SUMMARY OF THE INVENTION 
   The present invention provides a transient voltage clamping circuit of an integrated circuit for a disk drive, the circuit including a power transistor for sinking a power supply voltage subjected to transient variation; a reference circuit for deriving a first reference voltage from a second reference voltage and the power supply voltage; and an amplifier circuit for receiving said first reference voltage as an input and for driving the power transistor. 
   Preferably, the transient voltage clamping circuit further includes a pull-down circuit connected to a gate terminal of the power transistor and an output of the amplifier circuit for controlling operation of the power transistor. Preferably, the pull-down circuit is adapted to sink the gate voltage at the gate terminal when the power supply voltage is less than a first threshold voltage, thereby turning off the power transistor. Preferably, the first threshold voltage is about 5 volts, and preferably, the pull-down circuit is adapted to sink the gate voltage at the gate terminal when the second reference voltage is less than a second threshold voltage. Preferably, the second threshold voltage is about 0.7 volts. 
   In accordance with another aspect of the present invention, the amplifier circuit includes a level shift circuit, a voltage multiplier circuit, and a buffer circuit. 
   In accordance with yet a further aspect of the present invention, the first reference voltage is derived from the second reference voltage via coupled n-MOS and p-MOS current mirror circuits. 
   Advantageously, embodiments of the transient voltage clamping circuit of the invention provide accurate activation, low cost and low tolerance in activation threshold voltage relative to the prior art. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of an ASIC and motor driver for a hard disk drive; 
       FIG. 2  shows a circuit for transient voltage clamping according to an embodiment of the invention; 
       FIG. 3A  shows a level shift circuit used in the embodiment of the transient voltage clamping circuit shown in  FIG. 2 ; 
       FIG. 3B  shows the level shift circuit of  FIG. 3A  in combination with a multiplier-circuit used in the embodiment of the transient voltage clamping circuit shown in  FIG. 2 ; and 
       FIG. 3C  shows a buffer circuit used in the embodiment of the transient voltage clamping circuit shown in  FIG. 2 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Referring to  FIG. 1 , a hard disk drive (not shown) includes a motor  20  which receives power through a power ASIC  10 . The motor  20  receives power on lines A, B, C from power ASIC  10 , each of those lines having an impedance model which includes inductive and resistive impedances. UA, UB and UC are gate drive signals for upper power DMOS transistors for each line A, B and C. LA, LB and LC are for corresponding lower power DMOS transistors. These DMOS transistors provide current to the motor  20 . 
   Power ASIC  10  receives power from an external  12  volt power supply VP 12 . Power ASIC  10  includes a voltage clamping circuit  12  for clamping transient voltages which are dumped from the inductive loads in the motor  20  and is powered from the power supply rail of the power ASIC  10 . The duty cycle of the dumped current is generally small (typically in the order of 3%) and therefore the location of the clamping circuit on the power ASIC  10  does not pose a power dissipation problem if an appropriate package is used. 
     FIG. 2  shows the voltage clamping circuit  12  in further detail. A reference voltage V ref , feeds into an amplifier circuit  13  which drives a power transistor (M 0 ) for sinking dumped current I d . The reference voltage, V ref , is determined according to the following equation: 
                   V   ref     =       [       V   ⁢           ⁢   pwr     -     R   ⁢           ⁢     2   ·   I     ⁢           ⁢   2       ]     =     [       V   ⁢           ⁢   pwr     -     (     R   ⁢           ⁢     2   ·       V   ⁢           ⁢   bg       R   ⁢           ⁢   1           )       ]               (   1   )               
Current I 2  is generated at node V ref  through p-MOS and n-MOS current mirrors  17 , 18  and is driven by an operational amplifier  16  in combination with MOSFETM 1 . The operational amplifier  16  is supplied with a band gap reference voltage, V bg .
 
   Resistor R 2  and capacitor C are compensation components provided for increased circuit stability. 
   Coupled p-MOS and n-MOS current mirrors  17 ,  18  allow V ref  to be varied with variations in the band gap reference voltage and the power supply voltage V pwr . 
   Amplifier circuit  13  includes a level shift circuit (LSH), a multiplier circuit (M) and a buffer circuit (X 1 ). These circuits are shown in  FIGS. 3A ,  3 B and  3 C, respectively. The level shift circuit is also shown in  FIG. 3B , in combination with the multiplier circuit. The level shift circuit takes the reference voltage V ref  and provides a higher operating voltage (by about 1×V be =0.7V) to the multiplier circuit. 
   The multiplier circuit receives the level shifted voltage and multiplies this by a factor, M, which is determined as the ratio of the resistances of resistors RB and RA shown in  FIG. 3B . The multiplier circuit is included here in order to provide M times more V gs  to the power transistor. This in turn enables the power transistor to handle greater current (by a factor of M 2 ) for the same gate, width and length without changing the activation voltage of the clamping circuit  12 . The buffer circuit is provided between the multiplier circuit and the gate terminal of the power transistor so as to form a buffer between the power transistor and pull-down circuit  14  on the one hand and the driving circuits (including the multiplier, level shift, current mirrors and op-amp, etc.) on the other hand. 
   The equations for the circuit are as follows: 
                   V   gs     =         [       V   ⁢           ⁢   pwr     ⁢           -     (     R   ⁢           ⁢     2   ·       V   ⁢           ⁢   bg       R   ⁢           ⁢   1           )       ]     ·   M     +     (     R   ⁢           ⁢     3   ·       V   ⁢           ⁢   bg       R   ⁢           ⁢   1           )               (   2   )                 V   gs     =       V   TH     +         I   d     K                 (   3   )               
Solving (1) and (2), we have
   I   d   =K·M   2 ·( V pwer− V clamp) 2   (4) 
Where:
 
   
     
       
         
           
             
               
                 K 
                 = 
                 
                   
                     1 
                     2 
                   
                   · 
                   μ 
                   · 
                   
                     C 
                     ox 
                   
                   · 
                   
                     ( 
                     
                       W 
                       L 
                     
                     ) 
                   
                   · 
                   λ 
                 
               
             
             
               
                 ( 
                 5 
                 ) 
               
             
           
         
       
     
       
       μ is the channel mobility in power transistor M 0 ; 
       C ox  is the gate capacitance per unit area of power transistor M 0 ; 
       W is the gate width for the power transistor M 0 ; 
       L is the gate length for the power transistor M 0 ; 
       λ is the channel length modulation effect; and 
       M is the Multiplication Factor defined by the resistor ratio (RB/RA) of the multiplier circuit;
 
Vclamp is defined as:
 
     
  
   
     
       
         
           
             
               
                 
                   V 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   clamp 
                 
                 = 
                 
                   
                     V 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       bg 
                       · 
                       
                         
                           R 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                         
                           R 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                     
                   
                   + 
                   
                     
                       [ 
                       
                         
                           V 
                           TH 
                         
                         + 
                         
                           ( 
                           
                             R 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               3 
                               · 
                               
                                 
                                   V 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   bg 
                                 
                                 
                                   R 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                 
                               
                             
                           
                           ) 
                         
                       
                       ] 
                     
                     M 
                   
                 
               
             
             
               
                 ( 
                 6 
                 ) 
               
             
           
         
       
     
       
       V TH  is the DMOS Threshold voltage; and 
       R 3  is resistor RB in the multiplier circuit. 
     
  
   The most important of the formulae shown above is the formula for determining Vclamp, which defines the threshold voltage of V pwr  above which the clamp will activate. The clamping activation voltage can be adjusted using different resistor ratios (RB/RA) within the multiplier circuit. For example, if V pwr  is 5 volts instead of 12 volts then the ratio RB/RA must be adjusted accordingly to ensure that the clamping circuit  12  operates properly within the ASIC. 
   A further feature of the clamping circuit  12  is the pull-down circuit  14 . The pull-down circuit  14  operates to pull-down the gate voltage of the power transistor where V pwr  is small (i.e., below 5 volts) or where V pwr  rises quickly. 
   For the low V pwr  cut off function, transistor M 3  is designed (along with resistors R 5  and R 6 ) so as to be off until V pwr  reaches 5 volts or greater. Resistors R 5  and R 6  form a voltage divider for providing a gate voltage to M 3  which is selected so that its turn-on threshold voltage is just below 5 volts. When V pwr  is less than 5 volts, M 3  is off and consequently transistors M 2  and M 7  form a current mirror circuit which pulls down the gate of the power transistor M 0 , thereby disabling the clamping function. When M 3  is turned on, it pulls the gates of transistors M 2  and M 7  to ground, thus disabling the current mirror formed by those transistors so that the gate of the power transistor is not pulled to ground. This part of the pull-down circuit  14  ensures that the clamping circuit  12  will not operate unless the power supply voltage, V pwr  is at a sufficient level to enable correct operation of the clamping circuit  12 . This is particularly important if the V pwr  rises very slowly. For example, if V pwr  rises slowly, V bg  may have risen to the correct operating level before V pwr  reaches a sufficient level to enable the clamping circuit  12  to work. 
   On the other hand, if the power supply rises very quickly, the clamping circuit  12  can be wrongly activated due to the time that it takes the band gap and operational amplifier to settle to the correct voltage levels. Transistor M 4  is turned on or off by the level of the band gap reference voltage V bg . The turn-on threshold of M 4  is about 0.7 volts, which is the normal n-MOS operating threshold. M 4  will not operate until V bg  reaches the n-MOS threshold. The normal operating level of V bg  is about 1.3 volts. Where the power supply voltage rises quickly and V bg  lags behind, M 4  will be off, thereby allowing transistors M 5  and M 6  (which form a current mirror) to operate to pull-down the gate terminal of the power transistor. After V bg  rises to the correct level, M 4  turns on and thereby pulls down the gates of transistors M 5  and M 6  to disable the current mirror and allow the clamp to operate without the gate of power transistor M 0  being pulled down. 
   The described clamping circuit  12  is capable of handling large currents while having accurate clamping activation with low tolerance in activation threshold voltage and may be provided at a low cost. These advantages are provided as follows. 
   1. Low Cost 
   Use of a multiplying circuit reduces the necessary power transistor size by the factor M for the same current. Thus it is very silicon effective. 
   2. Low Tolerance in Activation Threshold Voltage 
   Given that (R 2 /R 1 )*&gt;&gt;[VTH+Vbg* (R 3 /R 1 )]/M Vclamp≅(R 2 /R 1 )*Vbg, which is independent of temperature. The tolerance is limited as the resistance matching between R 1  and R 2  can be achieved to within 0.5% and the band gap voltage (Vbg) can be trimmed with a trimming facility. This means that a total tolerance between R 1  and R 2  of +/−2% can be achieved. 
   3. Accuracy of Activation 
   The pull-down circuit ensures the correct clamping activation with minimal spurious clamping due to different power supply rise/fall slope. 
   All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, including but not limited to [insert list], are incorporated herein by reference, in their entirety. 
   From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims and the equivalents thereof.