Abstract:
The invention enables extremely quick and reliable recovery of the synchronization of a communication signal transmitted in a half-duplex link. Such a communication signal comprises first time intervals including useful data, and second time intervals devoid of useful data and in a given logic state. At the beginning of each of the first time intervals is included a digital synchronization pattern which is then considered as associated with the second time intervals to form synchronization words of great length. The synchronization of the communication signal is recovered by detecting the synchronization words of great length in the communication signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the synchronization of digital signals in communication links in general. More specifically, the invention relates to the synchronization of digital signals of packets and frames of packets in half-duplex communication links especially by means of optical fibers. 
     Half-duplex transmission of communication signals is an interesting solution for optical fiber telecommunications networks. In fact, this solution enables a single optical fiber to be used for two transmission directions and for several subscriber communications, thereby ensuring optimum efficiency of the fiber&#39;s very high capacity. 
     In a half-duplex communication, e.g. between a telephone exchange and a subscriber installation, the link between the exchange and the subscriber installation is not permanent. This requires synchronization to be recovered at the beginning of each communication period. In order to achieve good listening comfort for the communication, synchronization recovery, also known as frame alignment recovery in ISDN type telecommunications networks, should be performed extremely quickly, usually in less than 10 milliseconds. 
     2. Description of the Prior Art 
     The known frame alignment recovery devices are usually designed for duplex type bidirectional communications. In these devices, frame alignment is declared acquired, when the communication is set up, after a specific frame alignment pattern has been successively received several times; this entails a relatively long frame alignment recovery time. Such devices are therefore not suited to speedy recovery of frame alignment in a half-duplex communication. 
     OBJECT OF THE INVENTION 
     The main object of this invention is to provide a synchronization method and synchronization recovery devices intended for half-duplex communication, taking advantage of a particular waveform of the half-duplex communication signals, to introduce into said signals very long synchronization words from which synchronization recovery is obtained very quickly and with good reliability. 
     SUMMARY OF THE INVENTION 
     Accordingly, the invention relates to a synchronization method wherein a communication signal is transmitted from a first end of a half-duplex bidirectional link and received at a second end of the link. The signal comprises alternate first and second time intervals. 
     The first time intervals are occupied by useful data. The second time intervals are devoid of useful data and are in a first given logic state. 
     In the first (transmitting) link end, a predetermined digital synchronization pattern is included at the beginning of each of the first time intervals. In the second link end, the pattern is considered as being associated with said second time intervals with which it constitutes synchronization words which are detected in said communication signal thereby recovering synchronization of said signal. 
     A synchronization recovery device embodying the invention therein comprises 
     first means for detecting sequences of bits in the first logic state in the communication signal; each sequence has a duration equal to at least the duration of the second time intervals, 
     second means for detecting the synchronization pattern in the communication signal, and 
     means connected to the first and second detecting means for deriving a synchronization pulse when a synchronization pattern is detected immediately after detection of one of said sequences of bits. 
     According to another feature, the synchronization recovery device further comprises means connected to the deriving means for signalling a synchronization anomaly after a predetermined number of successive failures to detect the synchronization pulse. 
     According to the invention, the synchronization word is practically inimitable due to its great length, and the synchronization is reliably recovered after just one detection of the synchronization word. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     Further features and advantages of the invention will be apparent from the following particular description of the synchronization process and of several preferred embodiments of a synchronization recovery device embodying this invention as illustrated in the corresponding accompanying drawings in which: 
     FIG. 1 is an illustration of the format of a half-duplex communication digital signal; and 
     FIG. 2 is a schematic block-diagram of a synchronization recovery device embodying the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In a transmitting-receiving end equipment in a half-duplex link, a synchronization recovery device embodying the invention is situated after a duplexing device having a bidirectional port connected to the transmission support of the link, such as an optical fiber, for half-duplex transmitting and receiving digital signals such as e.g. digital packets or frames, an input receiving an digital signal outgoing through the port to be transmitted in the transmission support, and an output providing a digital signal incoming into the port and coming from the transmission support. 
     It is considered a half-duplex transmission e.g. with a repetition period TR=500 μs and a bit transmission frequency Fb=5.120 MHz to transmit digital frames of length L=1024 bits. 
     In reference to FIG. 1, the incoming digital signal PE has first and second alternate time intervals IT 0  and IT 1  respectively having lengths of L=1024 bits and L 1  =1536 bits. The repetition period TR of intervals IT 0  and IT 1 , combined has corresponds also to a length L+L 1  =2560=5.120×500 bits. The time intervals IT 0  each contain an incoming frame coming from the transmission support. During the second time intervals IT 1 , the transmitting-receiving end equipment in which the synchronization recovery device is included, is in an outgoing frame transmission phase. The incoming digital signal PE has then a constant value throughout the duration of intervals IT 1 , e.g. a zero value corresponding to logic state &#34;0&#34;. The time intervals IT 1  are hereafter referred to as empty time intervals i.e., devoid of useful data. The empty intervals IT 1  have a length L 1  =1536 bits which is greater than the length L=1024 bits of the time intervals IT 0  due to an idle time which is scheduled between the end of the transmission of an outgoing frame and the switching of the communication direction to receive an incoming frame. 
     According to the method of the invention, the empty time intervals IT 1  are used for synchronization. An empty interval IT 1  is associated with a given pattern MF placed at the beginning of the data bit frame following the interval IT 1  to constitute a synchronization word or frame alignment word MVT. The insertion of the pattern MF into the second time intervals IT 1  is performed in the receiving part of the other end equipment supplying outgoing frames to the transmission. The pattern MF comprises a first bit in the state &#34;1&#34;, i.e., in a state that is complementary to the state &#34;0&#34; corresponding to the empty intervals IT 1 . The length of the pattern MF is very short by comparison, e.g. equal to n=4 bits. The pattern MF is e.g. comprised of the binary combination &#34;1110&#34;. Thus to the frame alignment word MVT corresponds the binary combination &#34;00 . . . 01110&#34; comprising a sequence of L 1  =1536 bits in the state &#34;0&#34; followed by the pattern MF=&#34;1110&#34;. 
     In reference to FIG. 2, the synchronization recovery device embodying the invention is mainly comprised of a shift register 1, a word comparator 2, a binary counter 3, and a frame alignment loss signalling circuit 4. 
     The shift register 1 comprises n=4 stages. It receives the incoming packet signal PE at a data input D and a bit transmission rate signal Hb of frequency Fb=5.120 MHz at a clock input CL. Four parallel data outputs Q1 to Q4 of the register 1 are respectively connected to four inputs of the comparator 2. A serial data output QS of the register 1 provides the packet signal PE delayed by n=4 binary elements. 
     The purpose of the comparator 2 is to detect the pattern MF=&#34;1110&#34; in the signal PE when the pattern is loaded in the shift register 1. Four second inputs of the comparator 2 respectively receive the n=4 bits of the pattern MF which are stored e.g. in a wired read-only memory. The comparator 2 issues from output a signal EG in state &#34;1&#34; when the pattern MF is detected in the signal PE. 
     The binary counter 3 is a modulo-L 1  =1536 bits counter. The purpose of the counter 3 is to detect the empty time intervals IT 1  in the signal PE. To do so, the counter 3 receives the rate signal Hb at a clock input CL and a zero-resetting signal RAZ at a reset input R. An overflow indicating signal DE in the state &#34;1&#34; is supplied by the counter 3 when a sequence of at least L 1  =1536 consecutive bits is detected in the signal PE. 
     The resetting signal RAZ is produced by a two-input logic AND gate 300 receiving the signal PE coming from the register 1 and a complementary rate signal Hb. The signal Hb is produced by a logic inverter 301 from the rate signal Hb. 
     Another two-input logic AND gate 302 is provided in the device so as to produce a frame alignment signal VT from the signals EG and DE. 
     The loading and shifting of the bits of signal PE in the register 1 are controlled by states &#34;1&#34; of the rate signal Hb occurring during first half-periods of the signal Hb having a duration equal to 1/ (2·Fb). During second half-periods of the rate signal Hb corresponding to states &#34;0&#34; of said signal Hb, the resetting of the counter 3 at zero is controlled by bits in the state &#34;1&#34; of the signal PE contained in the time intervals IT 0 . 
     Subsequent to serial output QS of the register 1 transmitting the last of the L 1  =1536 bits in the state &#34;0&#34; contained in an empty time interval IT 1 , the signal RAZ has been in the inactive state &#34;0&#34; for a duration equal to at least IT 1 . The counter 3 has then counted at least L 1  =1536 pulses of the rate signal Hb and is in an overflow state. The signal DE is therefore in the state &#34;1&#34;. When the first bit in the state &#34;1&#34; of the pattern MF=&#34;1110&#34; is supplied by the serial output QS of the register 1 responsive to a rise edge of the signal Hb, all the bits of the pattern MF are loaded in the register 1 and the signal EG derived by comparator 2 switches to state &#34;1&#34;. The frame alignment signal VT=DE·EG also switches over to state &#34;1&#34;. At the end of a duration equal to 1/ (2· Fb) after the transfer of the first bit of the pattern MF via the serial output QS of the register 1 and the switching of the signal EG to state &#34;1&#34;, the signal Hb switches over to state &#34;1&#34; and opens the gate 300. The signal RAZ then switches over to state &#34;1&#34; and resets the counter 3 at zero. The signal DE jumps to the state &#34;0&#34;, the gate 302 closes, and the frame alignment signal VT returns to state &#34;0&#34;. A detection of the frame alignment word MVT in the incoming digital signal is thereby signalled by a pulse in the state &#34;1&#34; of duration equal to 1/ (2·Fb) figuring in the signal VT. 
     The purpose of the frame alignment loss signalling circuit 4 is to signal frame alignment loss after e.g. m=3 consecutive failures to detect the frame alignment word MVT. Circuit 4 comprise m=3 analogous flips-flops 400 to 402 connected in cascade. 
     The m=3 flips-flops are preferably of type D. A state &#34;1&#34; is applied at a data input D of the first flip-flop 400. The data inputs D of the flips-flops 401 and 402 are respectively connected to data outputs Q of the flips-flops 400 and 401. Zero-resetting inputs R of the flips-flops 400 to 402 receive the &#34;1&#34; state pulses of the frame alignment signal VT. A frame rate signal Ht of period Tt=TR=500 us is applied at clock inputs CL of the flips-flops 400 to 402. 
     Only when at least m=3 successive pulses in the state &#34;1&#34; are missing in the frame alignment signal VT, i.e., after m=3 failures to detect the frame alignment word MVT, does the state &#34;1&#34; applied at the data input D of the flip-flop 400 go through the m=3 flips-flops to be provided from the data output Q of the last flip-flop 402 and to produce a frame alignment loss signal PVT in the state &#34;1&#34;. 
     A light-emitting diode 403 supplied via a resistor 404 by the signal PVT is provided in the circuit 4 so as to produce a visual alarm display in the event of frame alignment loss.