Abstract:
The present disclosure provide a pixel driving circuit, a pixel driving method for the same, and a display apparatus. A voltage related to a threshold voltage of a driving unit is stored in a storage unit by a charge controlling unit at a compensating phase for the pixel driving circuit, such that the driving unit can be compensated by the storage unit at a driving phase for the pixel driving circuit. Thus, an influence of the threshold voltage of the driving unit on an operating current of the driving unit can be eliminated, and the problem of uneven brightness of light emitting elements resulted from the threshold voltages being different can be solved, thereby improving a display quality of the display apparatus.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates to a field of display technology, and more particular, to a pixel driving circuit, a pixel driving method for the same, and a display apparatus, which can improve a display quality by compensating a threshold voltage of a driving unit for a light emitting element. 
       BACKGROUND 
       [0002]    Active matrix organic light emitting diodes (AMOLED) display becomes one of hot spots in a field of panel displays. Compared with liquid crystal displays (LCD), organic light emitting diodes (OLED) panel has advantages, such as, a lower power consumption, a lower cost, be capable of self-luminous, a broader view, a faster response and the like. Currently, conventional LCD displays in the display field such as mobile phones, PDAs, digital cameras and the like, have been replaced by AMOLED displays. Pixel driving is a core of AMOLED display and is of great importance. 
         [0003]    Differently from a thin film transistor-liquid crystal display (TFT-LCD) which controls brightness by a stable current, the AMOLED is driven by a current, and thus needs a stable current to control light emission. As shown in  FIG. 1 , a conventional AMOLED pixel driving circuit may use a 2T1C pixel driving circuit. The circuit only comprises one driving thin film transistor T 1 , one switch thin film transistor T 2  and a storage capacitor C. When a scanning line select (i.e. scan) a row, a scanning signal Vscan is at a high level. Thus, T 2  is turned on and a data signal Vdata is written into the storage capacitor C. When the scanning of the row is completed, Vscan is turned into a low level signal, and T 2  is turned off. T 1  is driven by a gate voltage stored on the storage capacitor C, and will generate a current to drive the AMOLED. Thus, the AMOLED can emit light during a displaying of a frame continuously. The current of the driving thin film transistor T 1  in a saturated state can be represented by: I oled =K(Vgs−Vth)̂2, wherein K is a parameter related with the process and design of T 1 , Vgs is a gate-source voltage of the driving thin film transistor, and Vth is a threshold voltage of the driving thin film transistor. Once the size and process of the transistor is determined, the parameter K is determined.  FIG. 2  is an operation timing diagram of the pixel driving circuit of  FIG. 1 , and shows a relationship in timing between the scanning signal provided by the scanning line and the data signal provided by the data line. 
         [0004]    The light emission of the AMOLED is caused by the current generated when the driving thin film transistor (DTFT) is in a saturated state, irrespective of using a low temperature poly silicon (LTPS) process or a oxide process. Due to an unevenness of the process, threshold voltage difference at different locations of the driving thin film transistor may be generated, which will influence the consistency of the current driving device greatly. When inputting a same driving voltage, different threshold voltages will generate different driving currents, thereby leading to an inconsistency of the current passing through the OLED. This will further cause an unevenness brightness of the display, thereby affecting the displaying of a whole image. 
         [0005]    Thus, there is a need for a method which can improve a consistency for driving currents of driving transistors so as to improve the display quality. 
       SUMMARY 
       [0006]    The present disclosure relates to a pixel driving circuit, a pixel driving method for the same, and a display apparatus, which can improve a display quality by compensating a threshold voltage of a driving unit for a light emitting element. The compensation can be implemented, irrespective of the threshold voltage of a driving unit being positive or negative. 
         [0007]    According to an aspect of the present disclosure, a pixel driving circuit is provided for driving a light emitting element. The pixel driving circuit may comprise: a scanning line Scan, configured to provide a scanning signal Vscan; a power line, comprising a first power line ELVss and a second power line ELVdd, and configured to supply a power to the pixel driving circuit; and a data line, configured to provide a data signal Vdata; a reference signal line Ref, configured to provide a reference signal Vref; a first controlling signal line S 1 , configured to providing a first controlling signal V s1 ; a second controlling signal line S 2 , configured to providing a second controlling signal V s2 ; a third controlling signal line S 3 , configured to providing a third controlling signal V s3 ; a resetting signal lineInt, configured to provide a resetting signal Vint; a driving unit  310 , having an input terminal connected to an output terminal of a light emission controlling unit, a control terminal connected to a first intermediate node N 1 , an output terminal connected to a second intermediate node N 2 , wherein the light emitting element is connected between the second intermediate node and the first power line ELVss; the light emission controlling unit  330 , having an input terminal connected to the second power line ELVdd, a control terminal connected to the first controlling signal line S 1 , and the output terminal connected to the input terminal of the driving unit; a compensating unit  340 , having an input terminal connected to the first intermediate node N 1 , a control terminal connected to the second controlling signal line S 2 , and an output terminal connected to a third intermediate node N 3 ; a storage unit  350 , having a first terminal connected to the third intermediate node N 3  and a second terminal connected to the second intermediate node N 2 ; a charge controlling unit  320 , having a first input terminal connected to the reference signal line Ref, a second input terminal connected to the data line Data, a control terminal connected to the scanning line Scan, a first output terminal connected to the first intermediate node N 1  and a second output terminal connected to the third intermediate node N 3 ; a resetting unit  360 , having an input terminal connected to the resetting signal lineInt, a control terminal connected to the third controlling signal line S 3 , and an output terminal connected to the second intermediate node N 2 ; wherein at an initializing phase for the pixel driving circuit, under the control of the scanning signal and the third controlling signal, the charge controlling unit is configured to connect the reference signal line Ref with the first intermediate node N 1  and to connect the data line Data with the third intermediate node N 3 , and the resetting unit is configured to connect the resetting signalInt with the second intermediate node N 2 , so as to charge the storage unit via the data signal and the resetting signal and to turn on the driving unit; at a compensating phase for the pixel driving circuit, under the control of the scanning signal and the first controlling signal, the charge controlling unit is configured to connect the reference signal line Ref with the first intermediate node N 1  and to connect the data line Data with the third intermediate node N 3 , so as to keep the driving unit being turned on, and the driving unit is configured to charge the second intermediate node N 2  until the driving unit  310  is turned off; at a driving phase for the pixel driving circuit, under the first controlling signal and the second controlling signal, the compensating unit is configured to connect the first intermediate node N 1  and the third intermediate node N 3 , so as to turn on the driving unit, such that the driving unit provides a driving current being independent of a threshold voltage of the driving unit  310  to the light emitting element. 
         [0008]    In one implementation, the driving unit  310  may comprise a driving transistor T 1 , which has a gate connected to the first intermediate node N 1 , a first electrode connected to the output terminal of the light emission controlling unit, and a second electrode connected to the second intermediate node N 2 , wherein the first electrode is one of a source and a drain, and the second electrode is the other of the source and the drain. 
         [0009]    In one implementation, the light emission unit  330  may comprise a third transistor T 3 , which has a gate connected to the first controlling signal line S 1 , a first electrode connected to the second power line ELVdd, and a second electrode connected to the input terminal of the driving unit, wherein the first electrode is one of a source and a drain, and the second electrode is the other of the source and the drain. 
         [0010]    In one implementation, the compensating unit  340  may comprise a fourth transistor T 4 , which has a gate connected to the second controlling signal line S 2 , a first electrode connected to the first intermediate node N 1  and a second electrode connected to the third intermediate node N 3 , wherein the first electrode is one of a source and a drain, and the second electrode is the other of the source and the drain. 
         [0011]    In one implementation, the storage unit may comprise a storage capacitor. 
         [0012]    In one implementation, the charge controlling unit  320  may comprise a second transistor and a fifth transistor, wherein the second transistor has a gate connected to the scanning line Scan, a first electrode connected to the reference signal line Ref and a second electrode connected to the first intermediate node N 1 ; and the fifth transistor has a gate connected to the scanning line Scan, a first electrode connected to the data line Data and a second electrode connected to the third intermediate node N 3 , wherein the first electrode is one of a source and a drain, and the second electrode is the other of the source and the drain. 
         [0013]    In one implementation, the resetting unit  360  may comprise a sixth transistor T 6 , which has a gate connected to the third controlling signal line S 3 , a first electrode connected to the resetting signal lineInt and a second electrode connected to the second intermediate node N 2 , wherein the first electrode is one of a source and a drain, and the second electrode is the other of the source and the drain. 
         [0014]    In one implementation, each of the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor may be a P-type thin film transistor or a N-type thin film transistor. 
         [0015]    According to a second aspect of the present disclosure, a pixel driving method which is applicable to the pixel driving circuit discussed above is provided. The pixel driving method may comprise: providing the scanning signal through the scanning line, providing the data signal through the data line, and providing the third controlling signal through the third controlling signal line, so as to enable the pixel driving circuit to enter the initializing phase; providing the scanning signal through the scanning line, providing the data signal through the data line, and providing the first controlling signal through the first controlling signal line, so as to enable the pixel driving circuit to enter the compensating phase; and providing the first controlling signal through the first controlling signal line and providing the second controlling signal through the second controlling signal line, so as to enable the pixel driving circuit to enter the driving phase. 
         [0016]    According to a third aspect of the present disclosure, a display apparatus comprising the pixel driving circuit discussed above is provided. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    The above and other objectives, features and advantages will be obvious by illustrating the preferred embodiments of the present disclosure with reference to the drawing, in which: 
           [0018]      FIG. 1  is a structural diagram of a pixel driving circuit in the prior art; 
           [0019]      FIG. 2  is an operation timing diagram of the pixel driving circuit in the prior art; 
           [0020]      FIG. 3  is a structural diagram of a pixel driving circuit in a display apparatus according to an embodiment of the present disclosure; 
           [0021]      FIG. 4  is a structural diagram of the pixel driving circuit in the display apparatus according to another embodiment of the present disclosure; 
           [0022]      FIG. 5  is an operation timing diagram of the pixel driving circuit in the display apparatus according to another embodiment of the present disclosure; and 
           [0023]      FIG. 6  is a flow chart for the pixel driving method according to the embodiment of the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0024]    In the following, embodiments of the present disclosure will be described in detail with reference to the drawings. Hereinafter, the specific embodiments are only intended to illustrate the disclosure, which should be construed as examples of the disclosure, rather than to limit it. Functions or elements known in the related art are not described in detail when they would obscure the disclosure with unnecessary detail. 
         [0025]      FIG. 3  is a structural diagram of a pixel driving circuit  300  in a display apparatus according to an embodiment of the present disclosure. The pixel driving circuit  300  is used for driving a light emitting element  3000 . In  FIG. 3 , the light emitting element  3000  is implemented with a light emitting diode (OLED). As shown in  FIG. 3 , the pixel driving circuit  300  according to the embodiments of the present disclosure may comprise a scanning line Scan, configured to provide a scanning signal Vscan; a power line comprising a first power line ELVss and a second power line ELVdd, and configured to supply a power to the pixel driving circuit  300 ; and a data line configured to provide a data signal Vdata. 
         [0026]    In  FIG. 3 , the pixel driving circuit  300  may further comprise: a reference signal line Ref, configured to provide a reference signal Vref; a first controlling signal line S 1 , configured to providing a first controlling signal V s1 ; a second controlling signal line S 2 , configured to providing a second controlling signal V s2 ; a third controlling signal line S 3 , configured to providing a third controlling signal V s3 ; a resetting signal lineInt, configured to provide a resetting signal Vint. 
         [0027]    In  FIG. 3 , the pixel driving circuit  300  may further comprise a driving unit  310 , having an input terminal connected to an output terminal of a light emission controlling unit, a control terminal connected to a first intermediate node N 1 , an output terminal connected to a second intermediate node N 2 , wherein the light emitting element  3000  is connected between the second intermediate node N 2  and the first power line ELVss; the light emission controlling unit  330 , having an input terminal connected to the second power line ELVdd, a control terminal connected to the first controlling signal line S 1 , and the output terminal connected to the input terminal of the driving unit; a compensating unit  340 , having an input terminal connected to the first intermediate node N 1 , a control terminal connected to the second controlling signal line S 2 , and an output terminal connected to a third intermediate node N 3 ; a storage unit  350 , having a first terminal connected to the third intermediate node N 3  and a second terminal connected to the second intermediate node N 2 ; a charge controlling unit  320 , having a first input terminal connected to the reference signal line Ref, a second input terminal connected to the data line Data, a control terminal connected to the scanning line Scan, a first output terminal connected to the first intermediate node N 1  and a second output terminal connected to the third intermediate node N 3 ; a resetting unit  360 , having an input terminal connected to the resetting signal lineInt, a control terminal connected to the third controlling signal line S 3 , and an output terminal connected to the second intermediate node N 2 . 
         [0028]    At an initializing phase for the pixel driving circuit  300 , under the control of the scanning signal and the third controlling signal, the charge controlling unit  320  is configured to connect the reference signal line Ref with the first intermediate node N 1  and to connect the data line Data with the third intermediate node N 3 , and the resetting unit  360  is configured to connect the resetting signalInt with the second intermediate node N 2 , so as to charge the storage unit  350  via the data signal and the resetting signal and to turn on the driving unit  310 . 
         [0029]    At a compensating phase for the pixel driving circuit  300 , under the control of the scanning signal and the first controlling signal, the charge controlling unit  320  is configured to connect the reference signal line Ref with the first intermediate node N 1  and to connect the data line Data with the third intermediate node N 3 , so as to keep the driving unit  310  be turned on, and the driving unit  310  is configured to charge the second intermediate node N 2  until the driving unit  310  is turned off. 
         [0030]    At a driving phase for the pixel driving circuit  300 , under the first controlling signal and the second controlling signal, the compensating unit  340  is configured to connect the first intermediate node N 1  and the third intermediate node N 3 , so as to turn on the driving unit  310 , such that the driving unit  310  provides a driving current being independent of a threshold voltage of the driving unit  310  to the light emitting element  3000 . 
         [0031]      FIG. 4  is a structural diagram of the pixel driving circuit in the display apparatus according to another embodiment of the present disclosure. 
         [0032]    As shown in  FIG. 4 , the pixel driving circuit  400  according to the embodiments of the present disclosure may comprise: a scanning line Scan, configured to provide a scanning signal Vscan; a power line, comprising a first power line ELVss and a second power line ELVdd, and configured to supply a power to the pixel driving circuit  300 ; and a data line, configured to provide a data signal Vdata; a reference signal line Ref, configured to provide a reference signal Vref; a first controlling signal line S 1 , configured to providing a first controlling signal V s1 ; a second controlling signal line S 2 , configured to providing a second controlling signal V s2 ; a third controlling signal line S 3 , configured to providing a third controlling signal V s3 ; a resetting signal lineInt, configured to provide a resetting signal Vint. 
         [0033]    Similarly with the pixel driving circuit  300  shown in  FIG. 3 , the pixel driving circuit  400  according to the embodiments of the present disclosure may comprise a driving unit  310 , a charge controlling unit  320 , a light emission controlling unit  330 , a compensating unit  340 , a storage unit  350  and a resetting unit  360 . 
         [0034]    As shown in  FIG. 4 , in the pixel driving circuit  400  according to the embodiments of the disclosure, the driving unit  310  may comprise a driving transistor T 1 , which has a gate connected to the first intermediate node N 1 , a drain connected to the output terminal of the light emission controlling unit, and a source connected to the second intermediate node N 2 . In one embodiment, the drain of the driving transistor T 1  may correspond to the input terminal of the driving unit, the gate of the driving transistor T 1  may correspond to the control terminal of the driving unit, and the source of the driving transistor T 1  may correspond to the output terminal of the driving unit. 
         [0035]    As shown in  FIG. 4 , in the pixel driving circuit  400  according to the embodiments of the disclosure, the light emission unit  330  may comprise a third transistor T 3 , which has a gate connected to the first controlling signal line S 1 , a drain connected to the second power line ELVdd, and a source connected to the input terminal of the driving unit  310 . In the embodiment, the drain of the third transistor T 3  may correspond to the input terminal of the light emission controlling unit  330 , the gate of the third transistor T 3  may correspond to the control terminal of the light emission controlling unit  330 , and the source of the third transistor T 3  may correspond to the output terminal of the light emission controlling unit  330 . 
         [0036]    As shown in  FIG. 4 , in the pixel driving circuit  400  according to the embodiments of the disclosure, the compensating unit  340  may comprise a fourth transistor T 4 , which has a gate connected to the second controlling signal line S 2 , a drain connected to the first intermediate node N 1  and a source connected to the third intermediate node N 3 . In the embodiment, the drain of the fourth transistor T 4  may correspond to the input terminal of the compensating unit  340 , the gate of the fourth transistor T 4  may correspond to the control terminal of the compensating unit  340 , and the source of the fourth transistor T 4  may correspond to the output terminal of the compensating unit  340 . 
         [0037]    As shown in  FIG. 4 , in the pixel driving circuit  400  according to the embodiments of the disclosure, the storage unit  350  may comprise a storage capacitor C. The storage capacitor C may be connected between the second intermediate node N 2  and the third intermediate node N 3 . 
         [0038]    As shown in  FIG. 4 , in the pixel driving circuit  400  according to the embodiments of the disclosure, the charge controlling unit  320  may comprise a second transistor T 2  and a fifth transistor T 5 , wherein the second transistor T 2  has a gate connected to the scanning line Scan, a drain connected to the reference signal line Ref and a source connected to the first intermediate node N 1 ; and the fifth transistor T 5  has a gate connected to the scanning line Scan, a drain connected to the data line Data and a source connected to the third intermediate node N 3 . In the embodiment, the gates of the second transistor T 2  and the fifth transistor T 5  may correspond to a control terminal of the charge controlling unit  320 , the drain may correspond to the first input terminal of the charge controlling unit  320 , and its source may correspond to the first output terminal of the charge controlling unit; the drain of the fifth transistor T 5  may correspond to the second input terminal of the charge controlling unit  320 , and its source may correspond to the second output terminal of the charge controlling unit  320 . 
         [0039]    As shown in  FIG. 4 , in the pixel driving circuit  400  according to the embodiments of the disclosure, the resetting unit  360  may comprise a sixth transistor T 6 , which has a drain connected to the resetting signal lineInt, a gate connected to the third controlling signal line S 3  and a source connected to the second intermediate node N 2 . In the embodiment, the drain of the sixth transistor T 6  may correspond to the input terminal of the resetting unit  360 , the gate may correspond to the control terminal of the resetting unit  360 , and a source may correspond to the output terminal of the resetting unit  360 . 
         [0040]    Each of the driving transistor T 1 , the second transistor T 2 , the third transistor T 3 , the fourth transistor T 4 , the fifth transistor T 5  and the sixth transistor T 6  shown in  FIG. 4  may be a N-type thin film transistor or a P-type thin film transistor. According to the different types of the used transistors, the source and the drain of each of the driving transistor T 1 , the second transistor T 2 , the third transistor T 3 , the fourth transistor T 4 , the fifth transistor T 5  and the sixth transistor T 6  may be interchangeable. 
         [0041]      FIG. 5  is an operation timing diagram of the pixel driving circuit  400  according to the embodiment of the present disclosure. As shown in  FIG. 5 , the pixel driving circuit  400  may comprise three phases, i.e. a first phase (a initializing phase); a second phase (a compensating phase); and a third phase (a driving phase). For an easy understanding, in the embodiment, it is assumed that each transistor is a N-type transistor, which is turned on at a high level and turned off at a low level. A high level of a power supply is shown as ELVdd, and a low level of the power supply is shown as ELVss. In a level design, the following condition should be satisfied: Vref&gt;Vint+|Vth|, i.e. the high level of ELVss should be higher than Vref+|Vth|, wherein Vth is a threshold voltage for driving transistor T 1 . Those skilled in the art will understand that the disclosure is not limited to this. 
         [0042]    At the first phase T 1 , it is an initializing phase. At this phase, the scanning signal Vscan provided by the scanning line Scan is at a high level, and the third controlling signal V S3  provided by the third controlling signal line S 3  is also at a high level. ELVss is at a high level. Thus, transistors T 2 , T 5  and T 6  are turned on. Since the signals V S2 , V S2  provided by the first controlling signal line S 1  and the second controlling signal line S 2  are at a low level, the transistors T 3  and T 4  are turned off. At this time, the level of the reference signal provided by the reference signal line Ref is written into the gate of the driving transistor T 1 , and the data voltage is written into one end of the storage capacitor C, i.e. V_N 1 =Vdata, and the resetting signal is written into the other end of the storage capacitor C, i.e. V_N 2 =Vint. In other words, the voltage at the source of the driving transistor T 1  is Vint. Thus, a difference between the voltage at the gate and the voltage at the drain of the driving transistor T 1  is Vref−Vint&gt;Vth, and the driving transistor T 1  is accordingly turned on. Since the signal ELVss is at a high level at this time, and the high level of ELVss is higher than Vint as described above, OLED is at inverting connection, and will emit no light. 
         [0043]    At the second phase T 2 , it is a compensating phase. At this phase, the scanning signal Vscan provided by the scanning line Scan is at a high level, and the first controlling signal V S1  provided by the first controlling signal line S 1  is also at a high level. ELVss is at a high level. The transistors T 2  and T 5  are still turned on. Thus, the Vref is still written into the gate of the driving transistor T 1 , and the one end of the storage capacitor is maintained at the data voltage, i.e. V_N 1 =Vdata. Since the first controlling signal V S1  is at a high level, the transistor T 3  is turned on. Meanwhile the transistor T 6  is turned off, since the third controlling signal V S3  is at a low level. In view of above, the driving transistor T 1  is turned on at this time, and it will charge the second intermediate node N 2  until the voltage V_N 2  at N 2  is equal to Vref−Vth, i.e. V_N 2 =Vref−Vth. The voltage cross two ends of the storage capacitor C is V_N 1 N 2 =Vdata−(Vref−Vth)=Vdata−Vref+Vth. Since the ELVss is at a high level at this time, and the high level of ELVss is higher than Vref−Vth as described above, OLED is at inverting connection, and will emit no light. According to the above description, it is known that the driving transistor T 1  is turned on to store the threshold voltage at this phase, irrespective of the threshold voltage of the driving transistor T 1  being positive or negative. 
         [0044]    At the third phase T 3 , it is a driving phase. At this phase, the first controlling signal V S1  provided by the first controlling signal line S 1  and the second controlling signal V S2  provided by the second controlling signal line S 2  are both at a high level. ELVss is at a low level. The transistors T 3  and T 4  are turned on. Since the scanning signal Vscan and the third controlling signal V S3  are both at a low level, the transistors T 2 , T 5  and T 6  are turned off. At this time, the difference between the voltage at the gate and the voltage at the drain of the driving transistor T 1  is kept as a value at an end of the second phase T 2 , i.e. Vgs=V_N 1 N 2 =Vdata−Vref+Vth. Furthermore, since a value obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs of the driving transistor T 1  is smaller than or equal to the drain-source voltage Vds of the driving transistor T 1 , i.e. Vgs−Vth≦Vds, the driving transistor T 1  is in a saturated turning on state, wherein the current provided to the light emitting element OLED depends on the gate-source voltage Vgs of the driving transistor. In particular, I=K(Vgs−Vth) ̂2=K(Vdata−Vref+Vth−Vth) ̂2=K(Vdata−Vref) ̂2, wherein K is a constant related to process parameters and physical dimensions of the driving transistor T 1 . 
         [0045]    It is seen that the light emission current for driving the OLED only relates to the reference voltage Vref and the data voltage Vdata, and is independent of the threshold voltage Vth for the driving transistor. 
         [0046]    At the subsequent phases, each controlling signal is the same as the controlling signal at the phase T 3 . Accordingly, OLED keeps in emitting light until a high level scanning signal is received again. 
         [0047]    Although specific structures of the driving unit, the charge controlling unit, the light emission controlling unit, a compensating unit, a storage unit and a resetting unit are illustrated in  FIG. 4 , those skilled in the art will understand that these units may have other structures.  FIG. 4  only shows one example of the present disclosure. 
         [0048]      FIG. 6  is a flow chart for the pixel driving method according to the embodiment of the disclosure. The pixel driving method is applicable to the pixel driving circuit according to the embodiments of the present disclosure. As shown in  FIG. 6 , the driving method may comprise: firstly, in S 610 , providing the scanning signal through the scanning line, providing the data signal through the data line, and providing the third controlling signal through the third controlling signal line, so as to enable the pixel driving circuit to enter the initializing phase; then, in S 620 , providing the scanning signal through the scanning line, providing the data signal through the data line, and providing the first controlling signal through the first controlling signal line, so as to enable the pixel driving circuit to enter the compensating phase; and in S 630 , providing the first controlling signal through the first controlling signal line and providing the second controlling signal through the second controlling signal line, so as to enable the pixel driving circuit to enter the driving phase. In order to ensure that the OLED does not emit light at the initializing phase and the compensating phase for the pixel driving circuit, the supply voltage of the first power line is at a high level during the initializing phase and the compensating phase. The supply voltage of the first power line is higher than a sum of a voltage of the reference signal and a threshold voltage of the driving unit, wherein the voltage of the reference signal is higher than a sum of a voltage of the resetting signal and the threshold voltage of the driving unit. 
         [0049]    In particular, with reference to the pixel driving circuit shown in  FIG. 4 , by applying the operation timing diagram shown in  FIG. 5 , at the initializing phase for the pixel driving circuit, the charge controlling unit, the resetting unit and the driving unit are turned on, and the light emission controlling unit and the compensating unit is turned off. In other words, the driving transistor, the second transistor, the fifth transistor and the sixth transistor are turned on, and the third transistor and the fourth transistor are turned off. At the compensating phase for the pixel driving circuit, the charge controlling unit, the light emission controlling unit and the driving unit are turned on, and the resetting unit and the compensating unit is turned off. In other words, the driving transistor, the second transistor, the third transistor and the fifth transistor are turned on, and the fourth transistor and the sixth transistor are turned off. At the driving phase for the pixel driving circuit, the driving unit, the light emission controlling unit and the compensating unit are turned on, and the charge controlling unit and the resetting unit is turned off. In other words, the driving transistor, the third transistor and the fourth transistor are turned on, and the second transistor, the fifth transistor and the sixth transistor are turned off. 
         [0050]    The present disclosure may further provide a display apparatus comprising the above pixel driving circuit, the detailed description of which has been described in the above embodiments, and the same content will no longer be repeated. 
         [0051]    It should be noted that the present disclosure is exemplarily illustrated in the above description, which is not intended to limit the disclosure to the above steps and structures. One or more steps and structures can be modified or omitted if it is necessary. Thus, some of the steps or units are not essential elements for implementing the inventive concept of the present disclosure. Thus, the essential features of this disclosure only limit to a minimum requirement for implementing the inventive concept of the present disclosure, and are not defined by the specific implementations discussed above. 
         [0052]    The present disclosure has been illustrated in combination with the preferred embodiments. It is understood that those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, the scope of the present disclosure is not limited to the above embodiments, and it is defined by the attached claims.