Abstract:
A control circuit for a motherboard with a power supply unit arranged thereon includes a processing unit. To save consumption of electrical energy, the processing unit controls a switch unit to discontinue regulating a first power to a second power in a condition where a state of the motherboard is changed from state S 0  to state S 5.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a control circuit for a computer. 
         [0003]    2. Description of Related Art 
         [0004]    A power supply of the computer outputs various voltages when connected to the commercial power source, even if the computer shuts down. Accordingly, the computer will still consume a lot of power when connected to the commercial power source, which is not energy-efficient. 
         [0005]    Therefore, there is room for improvement in the art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    Many aspects of the present disclosure can be better understood with reference to the following drawing(s). The components in the drawing(s) are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawing(s), like reference numerals designate corresponding parts throughout the several views. 
           [0007]      FIG. 1  is a block diagram of an embodiment of a control circuit for a computer of the present disclosure, wherein the control circuit includes a processing unit, a switch unit, a delay unit, and a control unit. 
           [0008]      FIG. 2  is a circuit diagram of the processing unit of  FIG. 1 . 
           [0009]      FIG. 3  is a circuit diagram of the switch unit of  FIG. 1 . 
           [0010]      FIG. 4  is a circuit diagram of the delay and control units of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0011]      FIG. 1  illustrates an embodiment of a control circuit for a computer of the present disclosure. The control circuit includes a processing unit  10 , a switch unit  30 , a delay unit  20 , and a control unit  40 . 
         [0012]    The processing unit  10  outputs an enable signal and a status signal according to a power signal (such as a PS_ON signal outputted by a motherboard  50 ) to the switch unit  30  and to the delay unit  20  respectively. The switch unit  30  regulates or does not regulate a first power to a second power, according to the enable signal. The delay unit  20  outputs a corresponding signal to the control unit  40  according to the status signal, so as to prompt the control unit  40  to power on or power off the motherboard  50 . In the embodiment, the second power is a standby power, such as a power source P 5 V_STBY, by which the computer can be wakened from a standby state. 
         [0013]    According to the working principle of the computer, when the computer is in a standby state, such as in ACPI (Advanced Configuration and Power Interface) S 5  state, in which the computer shuts down with a power supply unit  60  still outputting the standby power, the power signal outputted from the motherboard  50  of the computer is at a high level, such as logic 1. When a power button of the computer is pushed, the power signal is changed to a low level, such as logic 0. When the power supply unit  60  of the computer receives the low level power signal (defined as a first switch signal), the power supply unit  60  will output all voltages, such as P 1 V 5 _AUX, P 1 V 0 _AUX, P 0 V 75 _AUX, and 12 volts (V). The motherboard will turn on, and an ACPI_S 0  state entered, in which the computer operates. When the computer shuts down by pressing the power button again, the power signal is changed from a low level to a high level, the computer will shut down when receiving the high level power signal (defined as a second switch signal) from the motherboard  50 . The computer is thus changed from the S 0  state to the S 5  state. 
         [0014]      FIG. 2  shows that the processing unit  10  includes a control chip IC, four resistors R 1 -R 4 , and a capacitor C 1 . A configuration pin DEEPS 5 _SEL of the control chip IC is coupled to a power terminal P 5 V_STBY_PSU, which outputs the first power, through the resistor R 2 . When configuration pin DEEPS 5 _SEL of the control chip IC receives a high level from the power terminal P 5 V_STBY_PSU, the control chip IC is configured to control the motherboard  50  to enter a +S 5  state, in which the power supply  80  outputs no standby power, such as the power source P 5 V_STBY being turned off. 
         [0015]    A status output pin PS_OUT of the control chip IC is coupled to a power terminal 
         [0016]    P 3 V 3 _AUX through the resistor R 4 . The control chip IC outputs a status signal to the delay unit  20  through the status output pin PS_OUT when an input pin PS_IN of the control chip IC receives the first or second switch signal. For example, when the input pin PS_IN of the control chip IC receives the first switch signal, the control chip IC outputs a low level status signal with a first determined time duration, such as 160 milliseconds (ms), after delaying for a second predetermined time, such as 160 ms, to the delay unit  20  through the output pin PS_OUT of the control chip IC. When the input pin PS IN of the control chip IC receives the second switch signal, the control chip IC outputs a high level status signal. 
         [0017]      FIG. 3  shows that the switch unit  30  includes an electronic switch T 1 , two resistors R 5  and R 6 , and four capacitors C 2 -C 5 . A first terminal of the electronic switch Ti is coupled to an enable pin SYS 5 VSB of the control chip IC through the resistor R 6 , to receive the enable signal. The first terminal of the electronic switch T 1  is connected to ground through the capacitor C 3 . A second terminal of the electronic switch T 1  is coupled to the power terminal P 5 V_STBY_PSU. A third terminal of the electronic switch T 1  is connected to ground through the capacitor C 5 , and is also coupled to the first terminal of the electronic switch T 1  through the capacitor C 4 . The third terminal of the electronic switch T 1  is configured to provide a power terminal P 5 V_STBY, which outputs the second power. The first terminal of the electronic switch T 1  is also coupled to the power terminal P 5 V_STBY_PSU through the resistors R 6  and R 5 , in that order. When the first terminal of the electronic switch T 1  is at a high level, the second terminal of the electronic switch T 1  is disconnected from the third terminal of the electronic switch T 1 , and the power terminal P 5 V_STBY provides no power. When the first terminal of the electronic switch T 1  is at a low level, the second terminal of the electronic switch T 1  is connected to the third terminal of the electronic switch T 1 , and the first power from the power terminal P 5 V_STBY_PSU is regulated to the second power according to the enable signal. In the embodiment, the electronic switch T 1  is a p-channel metal oxide semiconductor field effect transistor (pMOSFET), where a gate, a drain, and a source of the pMOSFET are respectively the first, the second, and the third terminals of the electronic switch T 1 . 
         [0018]      FIG. 4  shows that the delay unit  20  includes four electronic switches T 2 -T 5  and four resistors R 7 -R 10 . A first terminal of the electronic switch T 2  is coupled to the power terminal P 5 V_STBY through the resistor R 9 , to receive the second power. A second terminal of the electronic switch T 2  is connected to a first terminal of the electronic switch T 5 . The second terminal of the electronic switch T 2  is coupled to a power terminal P 3 V 3 _AUX through the resistor R 8 . A third terminal of the electronic switch T 2  is connected to ground. A second terminal of the electronic switch T 5  is coupled to the power terminal P 3 V 3 _AUX through the resistor R 7 . A third terminal of the electronic switch T 5  is coupled to the status output pin PS_OUT of the control chip IC, to receive the status signal from the control chip IC. The second terminal of the electronic switch T 5  is also connected to the control unit  40 , and is configured to output the control signal to the control unit  40 . A first terminal of the electronic switch T 3  is configured to receive a reset signal from a southbridge chip  80  of the motherboard  50 , where the reset signal is a high level signal outputted by the motherboard  50  within 0.5 seconds after the power terminal P 3 V 3 _AUX is activated by the power supply unit  60 . The southbridge chip  80  controls the motherboard  50  to reboot when the high level reset signal is received. A second terminal of the electronic switch T 3  is coupled to the power terminal P 5 V_STBY through the resistor R 9 , and is coupled to a first terminal of the electronic switch T 4 . A third terminal of the electronic switch T 3  is connected to ground. A second terminal of the electronic switch T 4  is coupled to the status output pin PS_OUT of the control chip IC, to receive the status signal from the control chip IC. A third terminal of the electronic switch T 4  is connected to ground. When the first terminals of the electronic switches T 2 -T 5  are at high level, the second terminals of the electronic switches T 2 -T 5  are respectively connected to the third terminals of the electronic switches T 2 -T 5 . When the first terminal of the electronic switches T 2 -T 5  are at low level, the second terminals of the electronic switches T 2 -T 5  are respectively disconnected from the third terminals of the electronic switches T 2 -T 5 . In the embodiment, the electronic switches T 2 -T 5  are n-channel metal oxide semiconductor field effect transistors (NMOSFETs), where gates, drains, and sources of the NMOSFETs are respectively the first, second, and third terminals of the electronic switches T 2 -T 5 . 
         [0019]    The control unit  40  receives the control signals from the second terminal of the electronic switch T 5 , to power the motherboard  50  on or off. For example, when the control unit  40  receives a low level control signal with duration of the first predetermined time, the control unit  40  controls the motherboard  50  to reboot. 
         [0020]    When the state of the motherboard  50  is changed from the state S 5  to S 0 , which indicates that the computer is ready to be turned on, the motherboard  50  outputs the first switch signal. The control chip IC of the input pin PS_IN receives the first switch signal, and outputs a low level enable signal to the switch unit  30  through the enable pin SYS 5 VSB of the control chip IC. The first terminal of the electronic switch T 1  receives the low level enable signal, and the second terminal of the electronic switch T 1  is thus connected to the third terminal of the electronic switch T 1 , so as that the first power is regulated to the second power. Thus, the power terminal P 3 V 3 _AUX is able to provide power regulated from the power terminal P 5 V_STBY. In the meantime, the control chip IC of the processing unit  10  receives the first switch signal, and outputs a low level status signal with duration of the first predetermined time to the delay unit  20  through the status output pin PS_OUT. Meanwhile, the southbridge chip  80  will not receive a high level reset signal sooner than the end of a third predetermined time (such as 0.5 seconds), when the power terminal P 3 V 3 _AUX is generated. Accordingly, the electronic switch T 3  is turned off, the electronic switches T 2  and T 4  are turned on and the electronic switch T 5  is turned off. Hence, the second terminal of the electronic switch T 5  is at high level, and the control unit  40  controls the motherboard  50  not to power on because of the high level signal. The southbridge chip  80  receives a high level reset signal after the third predetermined time, such as 0.5 seconds, so that the first terminal of the electronic switch T 3  receives a high level. The second terminal of the electronic switch T 3  is connected to the third terminal of the electronic switch T 3 . Accordingly, the electronic switches T 2  and T 4  are turned off, and the electronic switch T 5  is turned on. The electronic switch T 5  outputs the low level status signal with duration of the first predetermined time to the control unit  40 . The control unit  40  controls the motherboard  50  to power on when the control signal is changed from a high level to a low level with duration of the first predetermined time. Accordingly, the delay unit  20  delays the low level status signal for the third predetermined time duration after the reset signal is changed to a high level. 
         [0021]    When the state of the computer  50  is changed from the state S 0  to S 5 , which indicates that the computer is turned off, the motherboard  50  outputs the second switch signal, and the control chip IC outputs a high level enable signal to the switch unit  30  through the enable pin SYS 5 VSB of the control chip IC. The electronic switch Ti is turned off when the first terminal of the electronic switch Ti receives the high level enable signal. Accordingly, the first power provided by the power terminal P 5 V_STBY_PSU cannot be regulated to the second power. Thus, the power terminal P 5 V_STBY outputs no voltage; neither does the power terminal P 3 V 3 _AUX. In the meantime, the control chip IC outputs the high level status signal through the status output pin PS_OUT to the third terminal of the electronic switch T 5 . Accordingly, the electronic switches T 2 -T 5  are turned off. The second terminal of the electronic switch T 5  is at a low level. The control unit  40  receives the low level signal, and controls the motherboard  50  to power off, such that the power terminals P 5 V_STBY and P 3 V 3 _AUX are turned off, to further reduce the power-consumption of the motherboard  50 . 
         [0022]    While the disclosure has been described by way of example and in terms of a preferred embodiment, it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.