Abstract:
To provide an address generation apparatus and an operation apparatus that is possible to generate a complex address and to suppress an increase of a mounted area even if a bit width of a counter is widened. An address generation apparatus has at least one counter setting a count value by an operated value, at least one operation section being arranged corresponding to the counter respectively, operating a supplied step value and a count value of the corresponding counter in response to a control signal and supplying the operated count value to the corresponding counter, a selection section selecting either a set value or the operation result of the operation section in response to a control signal and inputting it to the counter, and an address operation section performing an operation in response to a control signal for the count value of the counter and outputting the operation result as an address.

Description:
CROSS REFERNCES TO RELATED APPLICATIONS  
       [0001]     The present invention contains subject matter related to Japanese Patent Application JP 2004-141613 filed in the Japanese Patent Office on May 11, 2004, the entire contents of which being incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to an address generation apparatus applicable to an operation system and a reconfigurable operation apparatus that this address generation apparatus is applied.  
         [0004]     2. Description of the Related Art  
         [0005]     A general operation system has, for example, a CPU, an address generation apparatus, a plurality of configuration information memory and a reconfigurable operation apparatus.  
         [0006]     In this operation system, a selection of a plurality of the configuration information memory is controlled by using the CPU.  
         [0007]     In this case, the selection of the memory is performed by using the CPU during the period that the address generation apparatus generates an address.  
         [0008]     In a DSP and so on in the related art, an address pattern to be generated is limited to a simple pattern such as a for loop of the C language. When performing a complex access, an address generated automatically was insufficient and it was necessary to perform the address calculation by using, for example, an ALU of the DSP.  
         [0009]     Therefore, cycle number necessary for the processing is more inefficient than that of the automatic address generation.  
         [0010]     For improving this, an address generation apparatus using, for example, a counter has been proposed (refer to Japanese Unexamined Patent Publication (Kokai) No. 2002-215388).  
       SUMMARY OF THE INVENTION  
       [0011]     However, it suffered from a disadvantage that it was inefficient or it was difficult to generate the address when generating a complex address even when the address generation apparatus described in Japanese Unexamined Patent Publication (Kokai) No. 2002-215388 is used.  
         [0012]     Further, it suffered from a disadvantage that it was necessary to enlarge a bit width of the counter because the address range was widened, and an area was enlarged when mounted on an LSI.  
         [0013]     It is desirable to provide an address generation apparatus and an operation apparatus able to generate a complex address efficiently and able to suppress an increase of the mounted area even when the bit width of the counter is widened.  
         [0014]     According to a first aspect of the present invention, there is provided an address generation apparatus generating an address of a memory, and the address generation apparatus has at least one counter setting a count value by an operated value, at least one operation section being arranged corresponding to the counter, operating a supplied step value and a count value of the corresponding counter in response to a control signal and supplying the operated count value to the corresponding counter, a selection section selecting either a set value or the operation result of the operation section in response to a control signal and inputting it to the counter, and an address operation section performing an operation in response to a control signal for the count value of the counter and outputting the operation result as an address.  
         [0015]     Preferably, the address generation apparatus of the present invention has a plurality of the counters and operation sections, and has a control section enabling to make a part of the counters operate with dividing them by a control signal, or enabling to make a plurality of counters operate with coupling them by a control signal.  
         [0016]     Preferably, the address operation section outputs an operated result obtained by operating an input value, a resistor value and an output of a plurality of the counters at the operation section as an address.  
         [0017]     Preferably, the operation section performs a calculation of a count value in response to the control signal by using the step value, the count value of the counter and a modification value.  
         [0018]     Preferably, the address generation apparatus has a control section enabling to change a start time of the address generation.  
         [0019]     Preferably, the control section counts the start time by a part of the counter of a plurality of the counters.  
         [0020]     Preferably, the address generation apparatus further has a parameter resistor set an address generation delay value, and a timing counter for starting a count in response to a trigger signal and delaying the address generation until the count becomes the value set in the parameter resistor, wherein the control section make a count action of the counter effective when the value of the timing counter approaches to the value set in the parameter resistor.  
         [0021]     Preferably, the address generation apparatus has a control section enabling to define a validity period of the address generation based on an input of a control signal.  
         [0022]     Preferably, a reconfigurable operation apparatus of a second aspect of the present invention has at least a first address generation apparatus, a second address generation apparatus, a third address generation apparatus, a first memory, a second memory, a third memory and an operation apparatus, and the each address generation apparatus has at least one counter setting a count value by an operated value, at least one operation section being arranged corresponding to the counter, operating a supplied step value and a count value of the corresponding counter in response to a control signal and supplying the operated count value to the corresponding counter, a selection section selecting either a set value or the operation result of the operation section in response to a control signal and inputting it to the counter, and an address operation section performing an operation in response to a control signal for the count value of the counter and outputting the operation result as an address, and a readout of the first memory is performed with an address generated by the first address generation apparatus, a readout of the second memory is performed with an address that the second address generation apparatus has generated by using the readout data, and a writing of an operated result that the data read out from the second memory is operated by the operation apparatus, is performed into the third memory with an address generated by the third address generation apparatus.  
         [0023]     Preferably, the reconfigurable operation apparatus of a third aspect of the present invention has at least a first address generation apparatus, a second address generation apparatus, a third address generation apparatus, a first memory, a second memory, a third memory, a first operation apparatus and a second operation apparatus, and the each address generation apparatus has at least one counter setting a count value by an operated value, at least one operation section being arranged corresponding to the counter, operating a supplied step value and a count value of the corresponding counter in response to a control signal and supplying the operated count value to the corresponding counter, a selection section selecting either a set value or the operation result of the operation section in response to a control signal and inputting it to the counter, and an address operation section performing an operation in response to a control signal for the count value of the counter and outputting the operation result as an address, and a readout of the first memory is performed with an address generated by the first address generation apparatus, the data read out from the first memory is operated by the first operation apparatus, a readout of the second memory is performed with an address that the second address generation apparatus has generated by using the operated data, and a writing of an operated result that the data read out from the second memory is operated by the second operation apparatus is performed into the third memory with an address generated by the third address generation apparatus.  
         [0024]     According to the present invention, for example, the address generation when the counter is not divided is performed as the followings.  
         [0025]     For example, the first operation section and the second operation section perform addition respectively, and transmit the carry of the second operation section to the first operation section to use it without dividing the counter.  
         [0026]     The first operation section performs addition by using the carry information and, for example, a step value that is an input value and a count value of the counter.  
         [0027]     For example, the first operation section and the second operation section select the input of set value for every predetermined cycle, and select values of the operation result of the first operation section and the second operation section at the time except for the predetermined cycles.  
         [0028]     As a result, the count value of a first counter and a second counter takes predetermined values. Then, the address operation section calculates an address based on the value of the first and the second counters.  
         [0029]     Further, for example, the address generation when the counter is not divided is performed as the followings.  
         [0030]     For example, the first operation apparatus and the second operation apparatus perform addition respectively.  
         [0031]     For example, the second selection apparatus selects the input of the selection value for every predetermined cycle and selects the result of the second operation apparatus at the time except for the predetermined cycles.  
         [0032]     The first selection apparatus for example, constantly selects the value of the first operation apparatus.  
         [0033]     As a result, the count values of the first counter and the second counter take predetermined values. Then, the address operation circuit calculates the address based on the counter value of the first and the second counters. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0034]     These and other objects and features of the present invention will become clearer from the following description of the preferred embodiments given with reference to the accompanying drawings, in which:  
         [0035]      FIG. 1  is a block diagram showing an address generation apparatus according to a first embodiment of the present invention;  
         [0036]      FIGS. 2A  to  2 E are timing charts for explaining address generation actions when a counter is not divided in the address generation apparatus of  FIG. 1 ;  
         [0037]      FIGS. 3A  to  3 E are timing charts for explaining address generation actions when a counter is divided in the address generation apparatus of  FIG. 1 ;  
         [0038]      FIG. 4  is a block diagram showing an address generation apparatus according to a second embodiment of the present invention;  
         [0039]      FIGS. 5A  to  5 G are timing charts for explaining address generation actions of the address generation apparatus of  FIG. 4 ;  
         [0040]      FIG. 6  is a block diagram showing an address generation apparatus according to a third embodiment of the present invention;  
         [0041]      FIGS. 7A  to  7 D are timing charts for explaining address generation actions of the address generation apparatus of  FIG. 6 ;  
         [0042]      FIG. 8  is a block diagram showing an address generation apparatus according to a fourth embodiment of the present invention;  
         [0043]      FIGS. 9A  to  9 G are timing charts for explaining address generation actions of the address generation apparatus of  FIG. 8 ;  
         [0044]      FIG. 10  is a block diagram showing a reconfigurable operation apparatus according to a fifth embodiment of the present invention;  
         [0045]      FIG. 11  is a view showing an example of stored data for every address in the memory in  FIG. 10 ;  
         [0046]      FIGS. 12A  to  12 F are timing charts for explaining actions of the operation apparatus of  FIG. 10 ;  
         [0047]      FIG. 13  is a block diagram showing a reconfigurable operation apparatus according to a sixth embodiment of the present invention;  
         [0048]      FIG. 14  is a view showing an example of stored data for every address in the memory of  FIG. 13 , and  
         [0049]      FIGS. 15A  to  15 G are timing charts for explaining actions of the operation apparatus of  FIG. 13 . 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0050]     Preferred embodiments of the present invention will be described with reference to the accompanying drawings.  
         [0051]     An address generation apparatus according to the present embodiment has a plurality of expressly controllable counters, and the address generation apparatus can set parameters such as an update, an end, a reconfiguration value, a step value, the maximum value, a dividing method, an offset and a start timing of the counter and so on. The address generation apparatus according to the present embodiment can control an address generation by using these parameters.  
         [0052]     The address generation apparatus can generates a control signal of a data path and a memory interface control signal in parallel with an address.  
         [0053]     &lt;First Embodiment&gt; 
         [0054]      FIG. 1  is a block diagram showing an address generation apparatus according to a first embodiment of the present invention.  
         [0055]     An address generation apparatus  100  according to the present first embodiment shows a configuration example when a counter is divided or coupled to generate addresses.  
         [0056]     The address generation apparatus  100  according to the first embodiment has resistors  101  and  102  for setting an initial value, resistors  103  and  104  for setting a step value, operation apparatuses  105  and  106 , selection apparatuses  107  and  108 , counters  109  and  110 , an operation apparatus  111 , a control apparatus  112 , a counter apparatus  113  and an operation apparatus  114 .  
         [0057]     In the address generation apparatus  100  of  FIG. 1 , the resistors  101  and  102 , the resistors  103  and  104 , the operation apparatuses  105  and  106 , the selection apparatuses  107  and  108 , the counters  109  and  110  form a pair respectively and they are possible to be used by dividing in a control of a not illustrated control system.  
         [0058]     The operation apparatus  105  performs a predetermined operation such as, for example, addition based on a set value of the resistor  103  and a value fed back from the counter  109  in accordance with a control signal S 112  showing a dividing state of counters from the control apparatus  112  and an operation result of the operation apparatus  106 , and outputs the operation result to the selection apparatus  107 .  
         [0059]     The operation apparatus  106  performs a predetermined operation such as, for example, addition based on a set value of the resistor  104  and a value fed back from the counter  110  in accordance with a control signal S 112  showing a dividing state of counters from the control apparatus  112 , and outputs the operation result to the selection apparatus  108 .  
         [0060]     The selection apparatus  107  selects either a set value of the resistor  101  or an output of the operation apparatus  105  based on a not illustrated control signal, and outputs the operation result to the counter  109 .  
         [0061]     The selection apparatus  108  selects either a set value of the resistor  102  or an output of the operation apparatus  106  based on a not illustrated control signal, and outputs the operation result to the counter  110 .  
         [0062]     The counter  109  sets a count value by a set value (initial value) of the resistor  101  selected by the selection apparatus  107  or a value of the operation result of the operation apparatus  105 , and outputs the count value CNT 109  to the operation apparatus  105  and the operation apparatus  111 .  
         [0063]     The counter  110  sets a count value by a set value (initial value) of the resistor  102  selected by the selection apparatus  108  or a value of the operation result of the operation apparatus  106 , and outputs the count value CNT 110  to the operation apparatus  106  and the operation apparatus  111 .  
         [0064]     The operation apparatus  111  operates count results of the counter  109  and the counter  111  based on the control signal S 112  generated by the control apparatus  112 , calculates a first address calculation count value ACNTV 11  and outputs it to the operation apparatus  114 .  
         [0065]     The operation apparatus  114  calculates an address ADR based on the first address calculation count value ACNTV 11  by the operation apparatus  111  and a second address calculation count value ACNTV 12  that is a count result of the counter apparatus  113  performing an action similar to that of the above-mentioned counter.  
         [0066]     Here, an address generation action of the address generation apparatus  100  of  FIG. 1  when the counter is not divided and an address generation action when the counter is divided will be explained.  
         [0067]     First, the address generation action when the counter is not divided will be explained with reference to the timing charts of  FIGS. 2A  to  2 E.  
         [0068]      FIG. 2A  shows a count value CNT 109  of the counter  109 ,  FIG. 2B  shows a count value CNT 110  of the counter  110 ,  FIG. 2C  shows the first address calculation count value ACNTV 11  by the operation apparatus  111 ,  FIG. 2D  shows the second address calculation count value ACNTV 12  by the counter apparatus  113  and  FIG. 2E  shows the address ADR calculated in the operation apparatus  114  respectively.  
         [0069]     The address generation when the counter is not divided is performed as the followings.  
         [0070]     “ 0 ” is stored in the resistor  101  and the resistor  102  as the initial value of the counter, and “ 1 ” is stored in the resistor  103  and the resistor  104  as the step value.  
         [0071]     The operation apparatus  105  and the operation apparatus  106  perform addition respectively, and transfer the carry of the operation apparatus  106  to the operation apparatus  105  to enable to use without dividing the counter.  
         [0072]     The operation apparatus  105  performs addition by using the carry information, the step value of the resistor  103  that is an input data and the count value CNT 109  of the counter  109 .  
         [0073]     The selection apparatus  107  and the selection apparatus  168  select the values of the resistor  101  and the resistor  102  for every three cycles, and select the values of the operation results of the operation apparatus  105  and the operation apparatus  106  at the time except for the three cycles.  
         [0074]     As a result, the count values CNT 109  and CNT 110  of the counter  109  and the counter  110  take values shown in  FIGS. 2A and 2B .  
         [0075]     By making it act as mentioned above, the first address calculation count value ACNTV 11  and the second address calculation count value ACNTV 12  take values shown in  FIGS. 2C and 2D .  
         [0076]     The operation apparatus  111  performs the following operation by using the output value CNT 109  of the counter  109  and the output value CNT 110  of the counter  110 , and calculates the first address calculation count value ACNTV 11 . 
 
[the output value CNT 109  of the counter  109 , the output value CNT 110  of the counter  110 ]  (Eq. 1) 
 
         [0077]     Note that, here, an operation of [A, B] is an operation coupling the higher bit and the lower bit.  
         [0078]     The operation apparatus  114  performs the following operation with the first address calculation count value ACNTV 11  by the operation apparatus  111  and the second address calculation count value ACNTV 12  outputted by the counter apparatus  113 , and calculates the address ADR. 
 
ADR=ACNTV 11 +ACNTV 12   (Eq. 2) 
 
         [0079]     Next, the address generation action when the counter is divided will be explained with reference to the timing charts of  FIGS. 3A  to  3 E.  
         [0080]      FIG. 3A  shows a count value CNT 109  of the counter  109 ,  FIG. 3B  shows a count value CNT 110  of the counter  110 ,  FIG. 3C  shows the first address calculation count value ACNTV 11  by the counter apparatus  111 ,  FIG. 3D  shows the second address calculation count value ACNTV 12  by the operation apparatus  113  and  FIG. 3E  shows the address ADR calculated in the operation apparatus  114  respectively.  
         [0081]     The address generation when the counter is divided is performed as the followings.  
         [0082]     “ 0 ” is stored in the resistor  102  as the initial value of the counter and “ 1 ” is stored in the resistor  103  and the resistor  104  as the step value.  
         [0083]     The operation apparatus  105  and the operation apparatus  106  perform addition respectively.  
         [0084]     The selection apparatus  108  selects the value of the resistor  102  for every three cycles, and select the value of the operation result of the operation apparatus  106  at the time except for three cycles.  
         [0085]     As a result, the count values CNT 109  and CNT 110  of the counter  109  and the counter  110  take values shown in  FIGS. 3A and 3B .  
         [0086]     By making it to act as mentioned above, the first address calculation count value ACNTV 11  and the second address calculation count value ACNTV 12  take values shown in  FIGS. 3C and 3D .  
         [0087]     The operation apparatus  111  performs the following operation by using the output value CNT 109  of the counter  109  and the output value CNT 110  of the counter  110 , and calculates the first address calculation count value ACNTV 11 . 
 
ACNTV 11 =CNT 109 +CNT 110    (Eq. 3) 
 
         [0088]     The operation apparatus  114  performs the following operation with the first address calculation count value ACNTV 11  by the operation apparatus  111  and the second address calculation count value ACNTV 12  outputted by the counter apparatus  113 , and calculates the address ADR. 
 
ADR=ACNTV 11 +ACNTV 12   (Eq. 4) 
 
         [0089]     Note that, the operation performed in the operation apparatus  105  and the operation apparatus  106  may be a common binary operation such as subtraction and multiplication, it is not limited to addition.  
         [0090]     It may switch the operation performed in the operation apparatus  111  to an operation shown in the following except for addition by the control signal. 
 
ACNTV 11 =(CNT 109 &lt;&lt;shift amount)+CNT 110   (Eq. 5) 
 
ACNTV 11 =CNT 109 −CNT 110    (Eq. 6) 
 
ACNTV 11 =CNT 109 *CNT 110    (Eq. 7) 
 
         [0091]     In the present first embodiment, it is described as division of the counter, since the carry information is used to widen a range of a computable address calculation count value by using a plurality of operation apparatuses and counters, it can be considered that the case of utilizing it by coupling the counters is a similar action.  
         [0092]     As explained above, according to the present first embodiment, the following effect can be obtained, because the address generation apparatus of the present embodiment has the resistors  101  and  102  setting the initial value, the resistors  103  and  104  setting the step value, the operation apparatus  105  performing a predetermined operation such as, for example, addition based on the set value of the resistor  103  and the value fed back from the counter  109  in accordance with the control signal S 112  showing a state of the division of the counters from the control apparatus  112  and the signal based on the operation result of the operation apparatus  106 , the operation apparatus  106  performing a predetermined operation such as, for example, addition based on the set value of the resistor  104  and the value fed back from the counter  110  in accordance with the control signal S 112  showing a state of the division of the counters from the control apparatus  112 , the selection apparatus  107  selecting either the set value of the resistor  101  or the output of the operation apparatus  105  based on the not illustrated control signal, the selection apparatus  108  selecting either the set value of the resistor  102  or the output of the operation apparatus  106  based on the not illustrated control signal, the counter  109  setting the count value by the set value (initial value) of the resistor  101  selected by the selector  107  or the value of the operation result of the operation apparatus  105  to make the count value CNT 109  to feed back to the operation apparatus  105 , the counter  110  setting the count value by the set value (initial value) of the resistor  102  selected by the selector  108  or the value of the operation result of the operation apparatus  106  to make the count value CNT 110  feed back to the operation apparatus  106 , the operation apparatus  111  operating the count results of the counter  109  and the counter  110  based on the control signal S 112  generated by the control apparatus  112  to calculate the first address calculation count value ACNTV 11 , and the operation apparatus  114  calculating the address ADR based on the first address calculation count value ACNTV 11  and the second address calculation count value ACNTV 12  that is the count result of the counter apparatus  113  performing the action similar to that of the counter shown in the above.  
         [0093]     Namely, the address generation apparatus of the present embodiment can generate a complex address pattern in comparison with a simple address pattern generated by a DSP in the related art.  
         [0094]     Further, since the address generation apparatus of the present embodiment is used by dividing the counter, it has an advantage that the influence that the area is enlarged when mounted on an LSI can be suppressed even when an address range is widen and a bit width of the counter is enlarged.  
         [0000]     &lt;Second Embodiment&gt; 
         [0095]      FIG. 4  is a block diagram showing an address generation apparatus according to a second embodiment of the present invention.  
         [0096]     An address generation apparatus  200  according to the present second embodiment shows a configuration example when generating an address by using an input data.  
         [0097]     The address generation apparatus  200  has resistors  201  and  202  for setting an initial value, resistors  203  and  204  for setting a step value, a resistor  205  for setting a constant value, operation apparatuses  206  and  207 , selection apparatuses  208  and  209 , counters  210  and  211 , and an operation apparatus  212 .  
         [0098]     The operation apparatus  206  performs a predetermined operation such as, for example, addition based on a step value of the resistor  203  and a value fed back from the counter  210 , and outputs the operation result to the selection apparatus  208 .  
         [0099]     The operation apparatus  207  performs a predetermined operation such as, for example, addition based on a step value of the resistor  204  and a value fed back from the counter  211 , and outputs the operation result to the selection apparatus  209 .  
         [0100]     The selection apparatus  208  selects either a set value of the resistor  201  or an output of the operation apparatus  206  based on a not illustrated control signal, and outputs the operation result to the counter  210 .  
         [0101]     The selection apparatus  209  selects either a set value of the resistor  202  or an output of the operation apparatus  207  based on a not illustrated control signal, and outputs the operation result to the counter  211 .  
         [0102]     The counter  210  sets a count value by a set value (initial value) of the resistor  201  selected by the selection apparatus  208  or a value of the operation result of the operation apparatus  206 , feeds back this value to the operation apparatus  206 , and outputs it as a first address calculation count value ACNTV 21  to the operation apparatus  212 .  
         [0103]     The counter  211  sets a count value by a set value (initial value) of the resistor  202  selected by the selection apparatus  209  or a value of the operation result of the operation apparatus  207 , feeds back this value to the operation apparatus  207 , and outputs it as a second address calculation count value ACNTV 22  to the operation apparatus  212 .  
         [0104]     The operation apparatus  212  performs a predetermined operation based on the first address calculation count value ACNTV 21  by the counter  210 , the second address calculation count value ACNTV 22  by the counter  211 , the constant value set in the resistor  205  and an input data DIN depending on a not illustrated control signal.  
         [0105]     Here, an address generation action of the address generation apparatus  200  of  FIG. 4  will be explained with reference to the timing charts of  FIGS. 5A  to  5 G.  
         [0106]      FIG. 5A  shows a count value CNT 210  of the counter  210 ,  FIG. 5B  shows a count value CNT 211  of the counter  211 ,  FIG. 5C  shows the first address calculation count value ACNTV 21 ,  FIG. 5D  shows the second address calculation count value ACNTV 22 ,  FIG. 5E  shows the constant value SCV set in the resistor  205 ,  FIG. 5F  shows the input data DIN to the operation apparatus  212  and  FIG. 5G  shows the address ADR calculated in the operation apparatus  212  respectively.  
         [0107]     The address generation is performed as the followings.  
         [0108]     “ 0 ” is stored in the resistor  201  and the resistor  202  as the initial value of the counter, and “ 1 ” is stored in the resistor  203  and the resistor  204  as the step value.  
         [0109]     The operation apparatus  206  and the operation apparatus  207  perform addition respectively.  
         [0110]     The selection apparatus  208  selects the value of the resistor  201  for every three cycles, and selects the value of the operation result of the operation apparatus  206  at the time except for the three cycles.  
         [0111]     The selection apparatus  209  selects the value of the operation result of the operation apparatus  207  constantly.  
         [0112]     As a result, the count values CNT 210  and CNT 211  of the counter  210  and the counter  211  take values shown in  FIGS. 5A and 5B .  
         [0113]     By making it to act as mentioned above, the first address calculation count value ACNTV 21  and the second address calculation count value ACNTV 22  take values shown in  FIGS. 5C and 5D .  
         [0114]     Further, as shown in  FIGS. 5E and 5F , “ 0 ” is set in the resistor  205  as the constant value SCV and the operation apparatus  212  is supplied with the input data DIN (0, 1, 3, 5, 7, 9 . . . ) for every cycles.  
         [0115]     Then, the operation apparatus  212  performs the following operation and calculates the address ADR. 
 
ADR=ACNTV 21 +ACNTV 22 +SCV+DIN  (Eq. 8) 
 
         [0116]     Here, data read out from a memory by using the no illustrated other address generation apparatus and a result that a predetermined operation is performed to the data read out from the memory can be used as the input data.  
         [0117]     The operation performed in the operation apparatus  212  may be a common operation such as subtraction and multiplication, it is not limited to addition obviously.  
         [0118]     According to the present second embodiment, the address generation apparatus of the present embodiment can generate a complex address pattern in comparison with a simple address pattern generated by a DSP in the related art.  
         [0119]     &lt;Third Embodiment&gt; 
         [0120]      FIG. 6  is s block diagram showing an address generation apparatus according to a third embodiment of the present invention.  
         [0121]     The address generation apparatus  300  according to the present third embodiment shows a configuration example when generating an address by using a step value, a count value and a modification value.  
         [0122]     The address generation apparatus  300  has resistors  301  and  302  for setting an initial value, resistors  303  and  304  for setting a step value, resistors  305 ,  306  and  307  for setting a modification value, operation apparatuses  308  and  309 , selection apparatuses  310  and  311 , counters  312  and  313 , and an operation apparatus  314 .  
         [0123]     The operation apparatus  308  performs a predetermined operation such as, for example, addition based on a step value of the resistor  303 , a modification value of the resistor  305  and a value fed back from the counter  312 , and outputs the operation result to the selection apparatus  310 .  
         [0124]     The operation apparatus  309  performs a predetermined operation such as, for example, addition based on a step value of the resistor  304 , a modification value of the resistor  306  and a value fed back from the counter  313 , and outputs the operation result to the selection apparatus  311 .  
         [0125]     The selection apparatus  310  selects either a set value of the resistor  301  or an output of the operation apparatus  308  based on a not illustrated control signal, and outputs the operation result to the counter  312 .  
         [0126]     The selection apparatus  311  selects either a set value of the resistor  302  or an output of the operation apparatus  309  based on a not illustrated control signal, and outputs the operation result to the counter  313 .  
         [0127]     The counter  312  sets a count value by a set value (initial value) of the resistor  301  selected by the selection apparatus  310  or a value of the operation result of the operation apparatus  308 , feeds back this value to the operation apparatus  308 , and outputs it as a first address calculation count value ACNTV 31  to the operation apparatus  314 .  
         [0128]     The counter  313  sets a count value by a set value (initial value) of the resistor  302  selected by the selection apparatus  311  or a value of the operation result of the operation apparatus  309 , feeds back this value to the operation apparatus  309 , and outputs it as a second address calculation count value ACNTV 32  to the operation apparatus  314 .  
         [0129]     The operation apparatus  314  performs a predetermined operation based on the first address calculation count value ACNTV 31  by the counter  312 , the second address calculation count value ACNTV 32  by the counter  313  and the modification value set in the resistor  307 .  
         [0130]     Here, an address generation action of the address generation apparatus  300  of  FIG. 6  will be explained with reference to the timing charts of  FIGS. 7A  to  7 D.  
         [0131]      FIG. 7A  shows the first address calculation count value ACNTV 31 ,  FIG. 7B  shows the second address calculation count value ACNTV 32 ,  FIG. 7C  shows the modification value MDV set in the resistor  307 ,  FIG. 7D  shows the address ADR calculated in the operation apparatus  314  respectively.  
         [0132]     The address generation is performed as the followings.  
         [0133]     “ 0 ” is stored in the resistor  301  and the resistor  302  as the initial value of the counter, “ 3 ” and “ 1 ” are stored in the resistor  303  and the resistor  304  as the step value and “ 5 ” is stored in the resistor  305  and the resistor  306  as the modification value.  
         [0134]     The operation apparatus  308  and the operation apparatus  309  perform the following operations. 
 
(STV 303 +CNT 312 ) mod (MDV 305 )  (Eq. 9) 
 
(STV 304 +CNT 313 ) mod (MDV 306 )  (Er. 10) 
 
         [0135]     Here, in Equations 9 and 10, STV 303  indicates the step value set in the resistor  303 , CNT 312  indicates the count value of the counter  312 , MDV 305  indicates the modification value set in the resistor  305 , STV 304  indicates the step value set in the resistor  304 , CNT  313  indicates the count value of the counter  313  and MDV 306  indicates the modification value set in the resistor  306 . Further, “mod” indicates a modulo operation.  
         [0136]     The modulo operation can be realized by performing the following operation when condition of STV 303 &lt;MDV 305  and INV 301 &lt;MDV 305  is satisfied. Note that, INV 301  indicates the initial value set in the resistor  301 . 
 
STV 303 +STV 304 −MDV 305   (Eq. 11) 
 
         [0137]     The selection apparatus  310  selects the value of the resistor  301  for every five cycles, and selects the value of the operation result of the operation apparatus  308  at the time except for the five cycles.  
         [0138]     By making it to act as mentioned above, the first address calculation count value ACNTV 31  and the second address calculation count value ACNTV 32  take values shown in  FIGS. 7C and 7D .  
         [0139]     Further, as shown in  FIG. 7C , “ 10 ” is set in the resistor  307  as the modification value  307 .  
         [0140]     The operation apparatus  314  performs the following operation and calculates the address ADR. 
 
ADR=(ACNTV 31 +ACNTV 32 ) mod (MDV 307 )  (Eq. 12) 
 
         [0141]     The operation performed in the operation apparatus  314  may be a modulo operation for a common operation such as subtraction and multiplication, it is not limited to the modulo operation for addition.  
         [0142]     Further, there is two kinds of input data in the present embodiment, however, it id possible to take a modulo value for an operation of arbitrary combination for an input exceeding two kinds, and to enable the change of them selectively by using the control signal like examples shown in the followings. 
 
(input data A+input data B+input data C) mod modulo value A  (Eq. 13) 
 
(input data A+input data B) mod modulo value A+input data C  (Eq. 14) 
 
         [0143]     According to the present third embodiment, the effect similar to that of the above-mentioned second embodiment can be obtained.  
         [0144]     &lt;Fourth Embodiment&gt; 
         [0145]      FIG. 8  is a block diagram showing an address generation apparatus according to a fourth embodiment of the present invention.  
         [0146]     The address generation apparatus  400  shows a configuration example when generating an address by changing the start time of address generation.  
         [0147]     The address generation apparatus  400  has a resistor  401  setting an initial value, a resistor  402  setting a step value, an operation apparatus  403 , a selection apparatus  404 , a counter  405 , an operation apparatus  406 , a parameter resistor  407 , a timing counter  408 , a control apparatus  409  and a control signal generation apparatus  410 . Further, it has a start value TRG and a control input CTLIN as inputs.  
         [0148]     The operation apparatus  403  performs a predetermined operation such as, for example, addition based on a step value of the resistor  402  and a value fed back from the counter  405 , and outputs the operation result to the selection apparatus  404 .  
         [0149]     The selection apparatus  404  selects either a set value of the resistor  401  or an output of the operation apparatus  403  based on a not illustrated control signal, and outputs the operation result to the counter  405 .  
         [0150]     The counter  405  sets a count value by a set value (initial value) of the resistor  401  selected by the selection apparatus  404  or a value of the operation result of the operation apparatus  403 , feeds back this value to the operation apparatus  403 , and outputs it as a first address calculation count value ACNTV 41  to the operation apparatus  406  and the control signal generation apparatus  410 .  
         [0151]     The counter  405  starts a count up action in response to the control signal S 409   a  by the control apparatus  409 .  
         [0152]     The operation apparatus  406  performs a predetermined operation based on the first address calculation count value ACNTV 41  by the counter  405  based on the not illustrated control signal, and calculates the address ADR.  
         [0153]     An address generation delay value is set to the parameter resistor  407  from the external.  
         [0154]     The timing counter  408  counts up of the count value when the start value TRG is inputted, and counts the timing for delaying the address generation until the count value becomes to the value set in the parameter resistor  407 .  
         [0155]     The control apparatus  409  judges whether or not the timing count value CNT 408  of the timing counter  408  approaches to the predetermined delay value set in the parameter resistor  407 , outputs the control signal  409   a  to the counter  405  to make the count up of the counter  405  valid when judging that it has approached.  
         [0156]     Further, after the timing count value CNT 408  of the timing counter  408  has approached to the set value, the control apparatus  409  outputs the control signal S 409   b  to the control signal generation apparatus  410 , and controls it to make an address valid signal AVLD valid.  
         [0157]     The control signal generation apparatus  410  generates the address valid signal AVLD by the control input CTLIN and this valid state.  
         [0158]     The control signal generation apparatus  410  make the address valid AVLD signal valid in response to the control signal s 409   b  by the control apparatus  409 . Further, the control signal generation apparatus  410  makes the address valid signal AVLD invalid when the count value of the counter  405 , that is, the first address calculation count value ACNTV 41  has approached to a predetermined value.  
         [0159]     The control signal generation apparatus  410  can be made a control output CTLOUT valid or invalid when the count value of the counter  405  becomes a specific value.  
         [0160]     Here, an address generation action of the address generation apparatus  400  of  FIG. 8  will be explained with reference to the timing charts of  FIGS. 9A  to  9 G.  
         [0161]      FIG. 9A  shows the trigger signal TRG given to the timing counter  408 ,  FIG. 9B  shows the timing count value CNT 408  of the timing counter  408 ,  FIG. 9C  shows the first calculation count value ACNTV 41  by the counter  405 ,  FIG. 9D  shows the address ADR calculated in the operation apparatus  406 ,  FIG. 9E  shows the address valid signal AVLD generated in the control signal generation apparatus  410 ,  FIG. 9F  shows the control input CTLIN, and  FIG. 9G  shows the control output CTLOUT respectively.  
         [0162]     The address generation is performed as the followings.  
         [0163]     The address generation delay value “ 4 ” is set in the parameter resistor  407 , and as shown in  FIG. 9A , the count up of the timing counter  408  is performed by the trigger signal TRG inputted from the external.  
         [0164]     Then, as shown in  FIG. 9B , when the count value CNT 408  approaches to the predetermined delay value “ 4 ” set in the parameter resistor  407 , the control apparatus  409  outputs the control signal S 409   a  so that the address generation counter  405  acts and makes the count up of the counter  405  valid.  
         [0165]     “ 0 ” is stored in the resistor  401  as the initial value of the counter and “ 2 ” is stored in the resistor  402  as the step value. The operation apparatus  403  performs, for example, addition.  
         [0166]     The selection apparatus  404  selects the value of the operation apparatus  403  constantly.  
         [0167]     By making it to act as mentioned above, the first address calculation count value ACNTV 41  has a value shown in  FIG. 5C .  
         [0168]     The operation apparatus  406  calculates the address ADR by using the first address calculation count value ACNTV 41 .  
         [0169]     It can output the address valid signal AVLD and the control output CTLOUT in parallel with the above-mentioned address generation.  
         [0170]     As shown in  FIGS. 9E  to  9 G, the address valid signal AVLD is generated by the control apparatus  409  and the control signal generation apparatus  410  based on the control input CTLIN, the trigger signal TRG and the timing count value CN-T 408 .  
         [0171]     After the timing count value CNT 408  of the timing counter  408  has approached to the set value, the control apparatus  409  makes an address valid signal AVLD valid by the control signal S 409   b , and when the count value of the counter  405  has approached to an end value, the control apparatus  409  makes the address valid signal AVLD invalid.  
         [0172]     The control signal generation apparatus  410  makes the control output CTLOUT valid or invalid when the count value of the counter  405  becomes a specific value.  
         [0173]     As shown in  FIGS. 9C and 9G , in the present example, when the first address calculation count value ACNTV 41  becomes “ 6 ” and “ 12 ”, the control output CTLOUT is made valid.  
         [0174]     According to the present fourth embodiment, since the address generation apparatus  400  can output the control signal and the address valid signal together with the address generation, the address generation apparatus  400  has an advantage that the control of a memory and an operation apparatus can be controlled flexibly by using those signals.  
         [0175]     Further, since the timing of the address generation can be controlled by the parameter, it is enabled to respond easily when there is a time dependency in reading-out from a plurality of memories and writing.  
         [0176]     &lt;Fifth Embodiments&gt; 
         [0177]      FIG. 10  is a block diagram showing a reconfigurable operation apparatus according to a fifth embodiment of the present invention.  
         [0178]     The reconfigurable operation apparatus  500  according to the present fifth embodiment shows a configuration example when an address is generated and an operation is performed by using a memory output as input data of the address generation apparatus.  
         [0179]     The reconfigurable operation apparatus  500  has an address generation apparatuses  501 ,  502  and  503 , memories  504 ,  505  and  506 , and an operation apparatus  507 .  
         [0180]     In the reconfigurable operation apparatus  500  in  FIG. 10 , an address ADR 501  generated by the address generation apparatus  501  is used as an address of the memory  504 , an address ADR 502  generated by the address generation apparatus  502  is used as an address of the memory  505 , and an address ADR 503  generated by the address generation apparatus  503  is used as an address of the memory  506 .  
         [0181]     Readout data of the memory  504  is used as an input data of the address generation apparatus  502 . The operation apparatus  507  calculates readout data of the memory  505  and outputs the result to the memory  506 .  
         [0182]      FIG. 11  is a view showing an example of stored data for every address in the memory  504  in  FIG. 10 .  
         [0183]     Further,  FIGS. 12A  to  12 F are timing charts for explaining actions of the operation apparatus  500  of  FIG. 10 .  
         [0184]      FIG. 12A  shows an address ADR  501  generated by the address generation apparatus  501 ,  FIG. 12B  shows an output MR 504  of the memory  504 ,  FIG. 12C  shows an address ADR 502  generated by the address generation apparatus  502 ,  FIG. 12D  shows an output MR 505  of the memory  505 ,  FIG. 12E  shows an output S 507  of the operation apparatus  507  and  FIG. 12F  shows an address ADR  503  generated by the address generation apparatus  503  respectively.  
         [0185]     The data is stored in the memory  504  for every address as shown in  FIG. 11 .  
         [0186]     As shown in  FIG. 12A , the address generation apparatus  501  issues  0 ,  1 ,  2  . . .  11  sequentially as the address ADR 501 .  
         [0187]     Along with that, as shown in  FIG. 12B , data  0 ,  1 ,  0 ,  1 ,  2  . . . is read out from the memory  504 .  
         [0188]     The address generation apparatus  502  uses the output data from the memory  504  as an input data DIN of the second embodiment of the present invention ( FIG. 4 ), performs the similar action and generates the address ADR  502  as shown in  FIG. 12C .  
         [0189]     As shown in  FIGS. 12D and 12E , an operation {x[i]=m[i]*2} is performed in the operation apparatus  507  for the data m[i] read out from the memory  505 , and the result is written into the memory  506 . The address supplied to the memory  506  is generated by the address generation apparatus  503  as shown in  FIG. 12F .  
         [0190]     Note that, in the present fifth embodiment, the operation apparatus  507  is defined as an operation apparatus having one input and one output, however, number of the data of the input and the output is not limited, the similar action can be performed with an operation apparatus having multi-input and multi-output by using the values of the address generation apparatus, the memory or the resistor in response to the corresponding input data and the output data.  
         [0191]     Further, the type of the operation is not limited to the operation shown in the example, it is apparent that four arithmetic operations, a logical operation a modulo operation and so on are included.  
         [0192]     &lt;Sixth Embodiment&gt; 
         [0193]      FIG. 13  is a block diagram showing a reconfigurable operation apparatus according to a sixth embodiment of the present invention.  
         [0194]     A reconfigurable operation apparatus  600  according to the present sixth embodiment generates shows a configuration when generating an address by using a memory output as an input data of an address generation apparatus and performing an operation.  
         [0195]     The reconfigurable operation apparatus  600  has address generation apparatuses  601 ,  602  and  603 , memories  604 ,  605  and  606  and operation apparatuses  607  and  608 .  
         [0196]     In the reconfigurable operation apparatus  600  of  FIG. 13 , an address ADR 601  generated by the address generation apparatus  601  is used as an address of the memory  604 , an address ADR 602  generated by the address generation apparatus  602  is used as an address of the memory  605  and an address ADR 603  generated by the address generation apparatus  603  is used as an address of the memory  606 .  
         [0197]     Read out data of the memory  604  is used as an input data of the operation apparatus  607  and an operation result of the operation apparatus  607  is used as an input data of the address generation apparatus  602 . The operation apparatus  608  operates readout data of the memory  605  and outputs the result to the memory  606 .  
         [0198]      FIG. 14  is a view showing an example of stored data in the memory  604  of  FIG. 13  for every address.  
         [0199]     Further,  FIGS. 15A  to  15 G are timing charts for explaining actions of the operation apparatus  600  of  FIG. 13 .  
         [0200]      FIG. 15A  shows an address ADR  601  generated by the address generation apparatus  601 ,  FIG. 15B  shows an output MR 604  of the memory  604 ,  FIG. 15  shows an output S 607  of the operation apparatus  607 ,  FIG. 15D  shows an address ADR  602  generated by the address generation apparatus  602 ,  FIG. 15E  shows an output MR 605  of the memory  605 ,  FIG. 15F  shows an output S 608  of the operation apparatus  608 ,  FIG. 15G  shows an address ADR 603  generated by the address generation apparatus  603 .  
         [0201]     The data is stored in the memory  604  for every address as shown in  FIG. 14 .  
         [0202]     As shown in  FIG. 15A , the address generation apparatus  601  issues  0 ,  1 ,  2  . . .  11  sequentially as the address ADR 601 .  
         [0203]     Along with that, as shown in  FIG. 15B , data  0 ,  1 ,  0 ,  1 ,  2  . . . is read out from the memory  604 .  
         [0204]     The operation apparatus  607  performs the following operation to the output data MR 604  from the memory  604  and supplies it as input data to the address generation apparatus  602 . 
 
S 607 =MR 604  &amp; 0xffffffff  (Eq. 15) 
 
         [0205]     The address generation apparatus  602  uses the operation result output S 607  from the operation apparatus  607  as an input data DIN of the second embodiment of the present invention ( FIG. 4 ), performs the similar action and generates the address ADR  602  as shown in  FIG. 15D .  
         [0206]     As shown in  FIGS. 15E and 15F , an operation {x[i]=m[i]*2} is performed in the operation apparatus  608  for the data m[i] read out from the memory  605 , and the result is written into the memory  606 . The address supplied to the memory  606  is generated by the address generation apparatus  603  as shown in  FIG. 15G .  
         [0207]     Note that, in the present sixth embodiment, the operation apparatuses  607  and  608  are defined as operation apparatuses having one input and one output, however, number of the data of the input and the output is not limited, the similar action can be performed with an operation apparatus having multi-input and multi-output by using the values of the address generation apparatus, the memory or the resistor in response to the corresponding input data and the output data.  
         [0208]     Further, the type of the operation is not limited to the operation shown in the example, it is apparent that four arithmetic operations, a logical operation a modulo operation and so on are included.  
         [0209]     As explained above, according to the present embodiment, a complex address pattern can be generated in comparison with a simple address pattern generated by the DSP in the related art.  
         [0210]     Further, there is an advantage that the effect that the area is enlarged when mounted on an LSI can be suppressed, even if a bit width of the counter such that an address range is enlarged, by using the counter with divided.  
         [0211]     Further, since the control signal and the address effective signal can be outputted together with the address generation, there is an advantage that the control of the memory and the operation apparatus can be performed flexibly by using these signals.  
         [0212]     Further, there is an advantage that it is enabled to respond easily when there is a time dependency in reading-out from a plurality of memories and writing, since the timing of the address generation can be controlled by the parameter.  
         [0213]     It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.