Abstract:
A reference voltage generator includes a mirroring circuit generating a first sub-voltage and a second sub-voltage that are constant, a first voltage generator including a first switch generating a first voltage based on the first sub-voltage, and a second voltage generator including a second switch generating a second voltage that is lower than the first voltage based on the second sub-voltage, wherein the second switch has a threshold voltage that is lower than the first switch to keep a voltage difference between the first voltage and the second voltage as a first reference voltage.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application claims priority to Korean patent application number 10-2014-0180685, filed on Dec. 15, 2014, the entire disclosure of which is herein incorporated by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field of Invention 
         [0003]    Various embodiments of the present invention relate to a reference voltage generator. 
         [0004]    2. Description of Related Art 
         [0005]    A reference voltage generator generates a reference voltage. Reference voltage generators are used in both semiconductor devices and semiconductor systems. To generate a constant reference voltage, the reference voltage generator needs to be designed so it is not affected by changes in input power and temperature. 
         [0006]    As the integration of semiconductor devices is increased and operations thereof become more complicated, changes in temperature may increase performance degradation of semiconductor devices. For example, when temperature increases, the amount of current flowing through the elements in the semiconductor devices may be reduced, resulting in the operation speed of the semiconductor devices being reduced. 
       SUMMARY 
       [0007]    Various embodiments of the present invention are directed to a reference voltage generator capable of generating a reference voltage that is constant regardless of changes in temperature. 
         [0008]    According to an embodiment of the present invention, a reference voltage generator may include a first circuit suitable for generating a first sub-voltage and a second sub-voltage that are constant, and a second circuit keeping a constant voltage difference based on the first and second sub-voltages to output a reference voltage. 
         [0009]    According to an embodiment of the present invention, a reference voltage generator may include a mirroring circuit suitable for generating a first sub-voltage and a second sub-voltage that are constant, a first voltage generator suitable for generating a first current based on the first sub-voltage and generating a first voltage based on the first current, and a second voltage generator generating a second current based on the second sub-voltage and a second voltage that is lower than the first voltage based on the second current, wherein the second voltage generator keeps a voltage difference between the first voltage and the second voltage as a reference voltage. 
         [0010]    According to an embodiment of the present invention, a reference voltage generator may include a mirroring circuit generating a first sub-voltage and a second sub-voltage that are constant; a first voltage generator suitable for generating a first voltage based on the first sub-voltage; and a second voltage generator suitable for generating a second voltage that is lower than the first voltage based on the second sub-voltage, wherein the second switch has a threshold voltage that is lower than the first switch to keep a voltage difference between the first voltage and the second voltage, and outputs a first reference voltage corresponding to the voltage difference. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a circuit diagram illustrating a reference voltage generator according to an embodiment of the present invention; 
           [0012]      FIG. 2  is a circuit diagram illustrating a reference voltage generator according to an embodiment of the present invention; 
           [0013]      FIG. 3  is a circuit diagram illustrating a reference voltage generator according to an embodiment of the present invention; 
           [0014]      FIG. 4  is a block diagram illustrating a memory system according to an embodiment of the present invention; 
           [0015]      FIG. 5  is a block diagram illustrating a memory system according to an embodiment of the present invention; and 
           [0016]      FIG. 6  is a diagram illustrating a computing system according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings. In the drawings, thicknesses and lengths of components may be exaggerated for convenience of illustration. In the following description, a detailed explanation of related functions and constitutions may be omitted for simplicity and conciseness. Like reference numerals refer to like elements throughout the specification and drawings. 
         [0018]    The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated to clearly illustrate features of the embodiments. It is also noted that in this specification, “connected/coupled” refers to one component not only directly coupling another component, but also indirectly coupling another component through an intermediate component. In addition, a singular form may include a plural form as long as it is not specifically mentioned. 
         [0019]      FIG. 1  is a circuit diagram illustrating a reference voltage generator  100  according to an embodiment of the present invention. 
         [0020]    Referring to  FIG. 1 , the reference voltage generator  100  may include a mirroring circuit  110 , a first voltage generation circuit  120  and a second voltage generation circuit  130 . 
         [0021]    The mirroring circuit  110  may be coupled between a first node N 1 , to which a power voltage VDD is applied, and a ground terminal, and generate a first sub-voltage and a second sub-voltage that are constant. For example, the mirroring circuit  110  may include a first switch S 1 , a second switch S 2 , a third switch S 3 , a fourth switches S 4  and a first resistor R 1 . The first switch S 1  may include a PMOS transistor which is coupled between the first node N 1  and a second node N 2 , and controlled by a voltage of a third node N 3 . Initial values of the second node N 2  and the third node N 3  may be set low. The second switch S 2  may include an NMOS transistor which is coupled between the second node N 2  and a fourth node N 4 , and controlled by a voltage of a fifth node N 5 . The first resistor R 1  may be coupled between the fourth node N 4  and the ground terminal. The third switch S 3  may include a PMOS transistor which is coupled between the first node N 1  and the fifth node N 5 , and controlled by the voltage of the third node N 3 . The fourth switch S 4  may include an NMOS transistor which is coupled between the fifth node N 5  and the ground terminal, and controlled by the voltage of the fifth node N 5 . The first and third switches S 1  and S 3  and the second and fourth switches S 2  and S 4  may be coupled in a mirrored configuration. However, since the first resistor R 1  is coupled to the fourth node N 4 , a voltage difference may occur between the second node N 2  and the fifth node N 5 . A voltage applied to the second node N 2  may be defined as the first sub-voltage, and a voltage applied to the fifth node N 5  may be referred to as the second sub-voltage. The first and second sub-voltages may be obtained by dividing the power voltage VDD applied to the first node N 1 . 
         [0022]    The first voltage genera on circuit  120  may include a fifth switch S 5  and a sixth switch S 6 . The fifth switch S 5  may include a PMOS transistor which is coupled between the first node N 1  and a sixth node N 6 , and is controlled by a voltage of the second node N 2 . The sixth switch S 6  may include an NMOS transistor which is coupled between the sixth node N 6  and a ground terminal, and controlled by a voltage of the sixth node N 6 . A current flowing through the fifth switch S 5  by the first sub-voltage may be defined as a first current I 1 . The voltage of the sixth node N 6  caused by the first current I 1  may be defined as a first voltage Vgs 1 . 
         [0023]    The second voltage generation circuit  130  may include a seventh switch S 7  and an eighth switch S 8 . The seventh switch S 7  may include an NMOS transistor which is coupled between the first node N 1  and a seventh node N 7 , and controlled by the voltage of the sixth node N 6 . The eighth switch S 8  may include an NMOS transistor which is coupled between the seventh node N 7  and a ground terminal, and controlled by the voltage of the fifth node N 5 . A current flowing through the eighth switch S 8  by the second sub-voltage may be defined as a second reference current I 2 . A voltage of the seventh node N 7  caused by the second reference current I 2  may be defined as a second voltage Vgs 2 . The seventh node N 7  may be an output node of the reference voltage generator  100 . In other words, the second voltage Vgs 2  may be a first reference voltage Vref 1 . 
         [0024]    To achieve temperature compensation, the sixth switch S 6  of the first voltage generation circuit  120  and the seventh switch S 7  of the second voltage generation circuit  130  may include NMOS transistors having different threshold voltages. For example, when the sixth switch S 6  has a first threshold voltage, the seventh switch S 7  may have a second threshold voltage that is lower than the first threshold voltage. The difference in threshold voltage between the switches may be obtained by using various methods. For example, switches may be formed with different sizes, or doping regions may have different impurity concentrations, so that a threshold voltage difference may occur between the switches. 
         [0025]    Operations of the reference voltage generator  100  are described below. 
         [0026]    Since the third node N 3  has a low initial voltage, a constant current may flow through the first and third switches S 1  and S 3 . Therefore, divided voltages of the power voltage VDD may be transferred to the second node N 2  and the fifth node N 5 . Since a lower positive voltage than the power voltage VDD is applied to the fifth node N 5 , the channel formed in the second and fourth switches S 2  and S 4  may result in a current path formed through the first node N 1 , the second node N 2 , the second switch S 2 , the fourth node N 4 , the first resistor R 1  and the ground terminal and a current path formed through the first node N 1 , the third switch S 3  the fifth node N 5 , the fourth switch S 4  and the ground terminal. Since the first to fourth switches S 1  to S 4  are coupled in the current mirror configuration, the first sub-voltage that is constant may be applied to the second node N 2 , and the second sub-voltage that is constant may be applied to the fifth node N 5 . Since the channel of the fifth switch S 5  remains constant by the first sub-voltage, the first current I 1  that is constant may flow through the fifth switch S 5 . Since the channel of the eighth switch S 8  remains constant by the second sub-voltage, the second current I 2  that is constant may flow through the eighth switch S 8 . Since the threshold voltages of the sixth and seventh switches S 6  and S 7  are different from each other, a difference may occur between the first current I 1  and the second current I 2 . Therefore, a difference may also occur between the first voltage Vgs 1  and the second voltage Vgs 2 . However, since both the sixth and seventh switches S 6  and S 7  include NMOS transistors, electrical characteristics thereof may change in the same manner in response to changes in temperature. Therefore, the difference between the first voltage Vgs 1  and the second voltage Vgs 2  may have a constant value. The difference between the first voltage Vgs 1  and the second voltage Vgs 2  may be the first reference voltage Vref 1 , which is output through the seventh node N 7 . Therefore, the first reference voltage Vref 1  may have a constant value regardless of changes in temperature. 
         [0027]      FIG. 2  is a circuit diagram illustrating a reference voltage generator  200  according to an embodiment of the present invention. 
         [0028]    Referring to  FIG. 2 , the reference voltage generator  200  may further include a voltage correction circuit  210  that corrects the first reference voltage Vref 1  output from the reference voltage generator  100 . 
         [0029]    The reference voltage generator  200  may include the mirroring circuit  110 , the first voltage generation circuit  120 , the second voltage generation circuit  130  and the voltage correction circuit  210 . 
         [0030]    The mirroring circuit  110  may be coupled between the first node N 1  to which the power voltage VDD is applied and a ground terminal, and generate a first sub-voltage and a second sub-voltage that are constant. For example, the mirroring circuit  110  may include the first to fourth switches S 1  to S 4  and the first resistor R 1 . The first switch S 1  may include a PMOS transistor which is coupled between the first node N 1  and the second node N 2 , and controlled by a voltage of the third node N 3 . Initial values of the second node N 2  and the third node N 3  may be set low. The second switch S 2  may be coupled between the second node N 2  and the fourth node N 4 , and controlled by a voltage of the fifth node N 5 . The first resistor R 1  may include an NMOS transistor which is coupled between the fourth node N 4  and the ground terminal. The third switch S 3  may include a PMS transistor which is coupled between the first node N 1  and the fifth node N 5 , and controlled by the voltage of the third node N 3 . The fourth switch S 4  may include an NMOS transistor which is coupled between the fifth node N 5  and the ground terminal, and controlled by the voltage of the fifth node N 5 . The first and third switches S 1  and S 3  and the second and fourth switches S 2  and switch S 4  may be coupled in a mirrored configuration. However, since the first resistor R 1  is coupled to the fourth node N 4 , a voltage difference may occur between the second node N 2  and the fifth node N 5 . A voltage applied to the second node N 2  may be defined as the first sub-voltage, and a voltage applied to the fifth node N 5  may be defined as the second sub-voltage. The first and second sub-voltages may be obtained by dividing the power voltage VDD applied to the first node N 1 . 
         [0031]    The first voltage generation circuit  120  may include the fifth switch S 5  and the sixth switch S 6 . The fifth switch S 5  may include a PMOS transistor which is coupled between the first node N 1  and the sixth node N 6 , and controlled by a voltage of the second node N 2 . The sixth switch S 6  may include an NMOS transistor which is coupled between the sixth node N 6  and the ground terminal, and controlled by a voltage of the sixth node N 6 . A current flowing through the fifth switch S 5  by the first sub-voltage may be defined as the first current I 1 , and the voltage of the sixth node N 6  generated by the first current I 1  may be defined as the first voltage Vgs 1 . 
         [0032]    The second voltage generation circuit  130  may include the seventh switch S 7  and the eighth switch S 8 . The seventh switch S 7  may include an NMOS transistor which is coupled between the first node N 1  and the seventh node N 7 , and controlled by the voltage of the sixth node N 6 . The eighth switch S 8  may include an NMOS transistor which is coupled between the seventh node N 7  and the ground terminal, and controlled by the voltage of the fifth node N 5 . A current flowing through the eighth switch S 8  by the second sub-voltage may be defined as the second reference current I 2 . A voltage of the seventh node N 7  generated by the second reference current I 2  may be defined as the second voltage Vgs 2 . The seventh node N 7  may be an output node of the reference voltage generator  100 . In other words, the second voltage Vgs 2  may be the first reference voltage Vref 1 . 
         [0033]    To achieve temperature compensation, the sixth switch S 6  of the first voltage generation circuit  120  and the seventh switch S 7  of the second voltage generation circuit  130  may include NMOS transistors having different threshold voltages. For example, when the sixth switch S 6  has a first threshold voltage, the seventh switch S 7  may have a second threshold voltage that is lower than the first threshold voltage. The difference in threshold voltage between the switches may be obtained by various methods. For example, switches may be formed with different sizes, or doped regions may have different impurity concentrations, so that a threshold voltage difference may occur between the switches. 
         [0034]    When the threshold voltages of the sixth and seventh switches S 6  and S 7  are different from each other, a difference may occur between the currents flowing through the sixth node N 6  and the seventh node N 7 . As a result, a difference may occur between the first voltage Vgs 1  and the second voltage Vgs 2 . Since the sixth and seventh switches S 6  and S 7  include NMOS transistors, electrical characteristics thereof may equally change (i.e. change in a uniform or substantially similar manner) according to changes in temperature. Thus, the difference between the first voltage Vgs 1  and the second voltage Vgs 2  may have a constant value. Since the difference between the first voltage Vgs 1  and the second voltage Vgs 2  may be the first reference voltage Vref 1  which is output through the seventh node N 7 , the first reference voltage Vref 1  may have a constant value regardless of changes in temperature. 
         [0035]    The voltage correction circuit  210  may include a ninth switch S 9  and a tenth switch S 10 . The ninth switch S 9  may include an NMOS transistor which is coupled between the seventh node N 7  and an eighth node N 8 , and controlled by the voltage of the seventh node N 7 , i.e., the first reference voltage Vref 1 . The tenth switch S 10  may include an NMOS transistor which is coupled between the eighth node N 8  and a ground terminal, and controlled by a voltage of the eighth node N 8 . The ninth and tenth switches S 9  and S 10  may include NMOS transistors having substantially the same electrical characteristics. A voltage divided by the ninth and tenth switches S 9  and S 10  may be applied to the eighth node N 8  and be a second reference voltage Vref 2 . In other words, when a constant first reference voltage Vref 1  is output, regardless of changes in temperature, the voltage correction circuit  210  may divide the first reference voltage Vref 1  to generate the second reference voltage Vref 2 , which is lower than the first reference voltage Vref 1 , and has a constant voltage. 
         [0036]      FIG. 3  is a circuit diagram illustrating a reference voltage generator  300  according to an embodiment of the present invention. 
         [0037]    Referring to  FIG. 3 , the reference voltage generator  300  may include the mirroring circuit  110 , a third voltage generation circuit  310  and a fourth voltage generation unit  320 . 
         [0038]    The mirroring circuit  110  may be coupled between the first node N 1  to which the power voltage VDD is applied and a ground terminal, and generate a first sub-voltage and a second sub-voltage that are constant. For example, the mirroring circuit  110  may include the first to fourth switches S 1  to S 4  and the first resistor R 1 . The first switch S 1  may include a PMOS transistor which is coupled between the first node N 1  and the second node N 2 , and controlled by a voltage of the third node N 3 . Initial values of the second node N 2  and the third node N 3  may be set low. The second switch S 2  may include an NMOS transistor which is coupled between the second node N 2  and the fourth node N 4 , and controlled by a voltage of the fifth node N 5 . The first resistor R 1  may be coupled between the fourth node N 4  and the ground terminal. The third switch S 3  may include a PMOS transistor that is coupled between the first node N 1  and the fifth node N 5  and controlled by the voltage of the third node N 3 . The fourth switch S 4  may include an NMOS transistor that is coupled between the fifth node N 5  and the ground terminal and controlled by the voltage of the fifth node N 5 . The first and third switch S 1  and S 3  and the second and fourth switches S 2  and S 4  may be coupled in a mirrored configuration. However, since the first resistor R 1  is coupled to the fourth node N 4 , a difference may occur between the second node N 2  and the fifth node N 5 . A voltage applied to the second node N 2  may be defined as the first sub-voltage, and a voltage applied to the fifth node N 5  may be defined as the second sub-voltage. The first and second sub-voltages may be obtained by dividing the power voltage VDD, which is applied to the first node N 1 . 
         [0039]    The third voltage generation circuit  316  may include the fifth switch S 5  and the sixth switch S 6 . The fifth switch S 5  may include a PMOS transistor which is coupled between the first node N 1  and the sixth node N 6 , and controlled by a voltage of the sixth node N 6 . The sixth switch S 6  may include an NMOS transistor which is coupled between the sixth node N 6  and the ground terminal, and controlled by a third current I 3 . A current flowing through the sixth switch S 6  may be defined as the third current I 3 , and a voltage of the sixth node N 6  may be defined as a third voltage Vgs 3 . 
         [0040]    The fourth voltage generation unit  320  may include an eleventh switch S 11  and a twelfth switch S 12 . The eleventh switch S 11  may include a PMOS transistor which is coupled between the first node N 1  and the seventh node N 7 , and controlled by a fourth current I 4 . The twelfth switch S 12  may include a PMOS transistor which is coupled between the seventh node N 7  and a ground terminal, and controlled by the third voltage Vgs 3 . A current flowing through the eleventh switch S 11  may be defined as the fourth current I 4 . A voltage of the seventh node N 7  may be defined as a fourth voltage Vgs 4 . The seventh node N 7  may be an output node of the reference voltage generator  300 . In other words, the fourth voltage. Vgs 4  may be a third reference voltage Vref 3 . 
         [0041]    To achieve temperature compensation, the fifth switch S 5  of the third voltage generation circuit  310  and the twelfth switch S 12  of the fourth voltage generation unit  320  may include PMOS transistors having different threshold voltages. For example, when the fifth switch S 5  has a third threshold voltage, the twelfth switch S 12  may have a fourth threshold voltage that is lower than the third threshold voltage. The difference in threshold voltage between the switches may be obtained by various methods. For example, switches may be formed with different sizes, or doped regions may have different impurity concentrations, so that a threshold voltage difference may occur between the switches. 
         [0042]    When the threshold voltages of the fifth and twelfth switches S 5  and S 12  are different from each other, a difference may occur between the third reference current I 3  and the fourth reference current I 4 . As a result, a difference may occur between the second voltage Vgs 2  and the fourth voltage Vgs 4 . Since the fifth and twelfth switches S 5  and S 12  include PMOS transistors, electrical characteristics thereof may change equally according to changes in temperature. Therefore, the difference between the third voltage Vgs 3  and the fourth voltage Vgs 4  may remain constant. The difference between the third voltage Vgs 3  and the fourth voltage Vgs 4  may be the third reference voltage Vref 3 , which is output through the seventh node N 7 . Therefore, the third reference voltage Vref 3  may have a constant value regardless of changes in temperature. 
         [0043]    Though not illustrated in  FIG. 3 , the reference voltage may be controlled by coupling the voltage correction circuit  210  shown in  FIG. 2  to the seventh node N 7  of the reference voltage generator  300 . 
         [0044]      FIG. 4  is a block diagram illustrating a memory system  2000  according to an embodiment of the present invention. 
         [0045]    Referring to  FIG. 4 , the memory system  2000  may include a host  2100  and a solid-state drive (SSD)  2200 . The SSD  2200  may include an SSD controller  2210 , a buffer memory  2220  and a plurality of semiconductor memory devices  1100 s. The components of the memory system  2000  may be driven by a reference voltage generated by the reference voltage generator according to the embodiments of the present invention. 
         [0046]    The SSD controller  2210  may provide a physical connection between the host  2100  and the SSD  2200 . In other words, the SSD controller  2210  may perform interfacing with the SSD  2200  according to a bus format of the host  2100 . The SSD controller  2210  may decode a command provided from the host  2100 . According to the decoding result, the SSD controller  2210  may access the semiconductor memory devices  1100 s. As the bus format of the host  2100 , universal serial bus (USB), small computer system interface (SCSI), peripheral component interconnect express (PCI-E) advanced technology attachment (ATA), parallel ATA (DATA), serial ATA (SATA), and serial attached SCSI (SAS) may be included. 
         [0047]    The buffer memory  2220  may temporarily store program data provided from the host  2100  or data read from the semiconductor memory devices  1100 s. When a read request is made by the host  2100 , if data read from the semiconductor memory devices  1100 s is cached, the buffer memory  2220  may support a cache function to directly provide the cached data to the host  2100 . In general, a data transfer speed by the bus format (for example, SATA or SAS) of the host  2100  may be higher than a transfer speed of a memory channel of the SSD  2200 . In other words, when an interface speed of the host  2100  is higher than the transfer speed of the memory channel of the SSD  2200 , performance degradation caused by the speed difference may be minimized by providing buffer memory  2220  having a large capacity. The buffer memory  2220  may be provided as synchronous DRAM to provide sufficient buffering in the SSD  2200 . 
         [0048]    The semiconductor memory devices  1100 s may be provided as a storage medium of the SSD  2200 . For example, each of the semiconductor memory devices  1100 s may be provided as a nonvolatile memory device having large storage capacity. Each of the semiconductor memory devices  1100 s may be provided as a NAND-type flash memory. 
         [0049]      FIG. 5  is a block diagram illustrating a memory system  3000  according to an embodiment of the present invention. 
         [0050]    Referring to  FIG. 5 , the memory system  3000  may include a memory control unit  3100  and the semiconductor memory device  1100 . The components of the memory system  3000  may be driven by a reference voltage generated by the reference voltage generator according to the embodiments of the present invention. 
         [0051]    The semiconductor memory device  1100  may be provided as a storage medium of the memory system  3000 . 
         [0052]    The memory control unit  3100  may control the semiconductor memory device  1100 . The memory control unit  3100  may include a static random access memory (SRAM)  3110 , a central process unit (CPU)  3120 , a host interface (I/F)  3130 , an error correction circuit (ECC)  3140 , and a semiconductor I/F  3150 . The SRAM  3110  may be used as a working memory of the CPU  3120 . The host interface (I/F)  3130  may include a data exchange protocol of a host electrically coupled with the memory system  3000 . The error correction circuit (ECC)  3140  may detect and correct errors in data read from the semiconductor memory device  1100 . The semiconductor I/F  3150  may interface with the semiconductor memory device  1100 . The CPU  3120  may perform a control operation for data exchange of the memory control unit  3100 . In addition, although not illustrated in  FIG. 5 , a read only memory (ROM) (not shown) for storing code data for interfacing with a host may be provided in the memory system  3000 . 
         [0053]    The memory system  3000  may be applied to one of a computer, an ultra mobile PC (UMPC), a workstation, a net-book, a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a smartphone, a digital camera, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device of transmitting and receiving information in a wireless environment, and various devices constituting a home network. 
         [0054]      FIG. 6  is a block diagram illustrating a computing system  4000  according to an embodiment of the present invention. 
         [0055]    Referring to  FIG. 6 , the computing system  4000  may include the semiconductor memory device  1100 , a memory controller  4100 , a modem  4200 , a microprocessor  4400 , and a user interface  4500  which are electrically coupled to a bus  4300 . When the computing system  4000  is a mobile device, a battery  4600  for supplying an operation voltage of the computing system  4000  may be additionally provided. The computing system  4000  may include an application chip set (not shown), a camera image processor (not shown), a mobile DRAM (not shown), and the like. 
         [0056]    The semiconductor memory device  1100  may be provided as a storage medium of the computing system  4000 . 
         [0057]    The memory controller  4100  and the semiconductor memory device  1100  may be components of an SSD. 
         [0058]    The semiconductor memory device  1100  and the memory controller  4100  may be mounted using various types of packages. For example, the semiconductor memory device  1100  and the memory controller  4100  may be mounted using packages such as package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PICC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), wafer-level processed stack package (WSP), and the like. 
         [0059]    According to an embodiment of the present invention, a constant reference voltage may be generated regardless of changes in temperature, so that semiconductor device performance degradation that uses a reference voltage generator may be prevented. 
         [0060]    It will be apparent to those skilled in the art that various modifications can be made to the above-described exemplary embodiments of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover all such modifications provided they come within the scope of the appended claims and their equivalents.