Abstract:
A programmable Pulse Width Modulation (PWM) generator is disclosed wherein a single module provides four different signals utilized to control a ballast for a light device. By changing the value in a single register, various waveforms are achieved.

Description:
TECHNICAL FIELD  
         [0001]    The present invention relates to the control of lighting systems, and more specifically, to an improved method and apparatus for controlling a ballast to drive a lighting device or similar such device.  
         BACKGROUND OF THE INVENTION  
         [0002]    Pulse Width Modulation (PWM) generators are used in a variety of applications to control power delivered to an electronic device. In the control of a ballast for use in driving a electronic lighting or similar device, one of four different modes is typically utilized. More specifically, the control circuitry for the ballast usually generates one of four different sets of signals, and wherein the mode defines the particular relationship of two different sequences of pulses (i.e. wave forms) that emanate from the control circuitry and are utilized to drive the ballast. The two control waveforms are then input into the gates of different transistor switches, turning the switches off and on to generate the required pulse width modulated signal. The two waveforms are therefore referred to as G 1  and G 2 , since they are used as gating signals to two different switches. The switches are usually implemented as transistors.  
           [0003]    In the first mode, the waveforms shown as  201  in FIG. 2 are generated. The control waveforms G 1  and G 2  utilized in additional modes are depicted as  202  through  204 , respectively in FIG. 2. The four different modes all generate the two gating signals G 1  and G 2 , but these are differences between the modes.  
           [0004]    As shown in FIG. 2, in the first mode the waveforms are opposites of one another, no offset or delay between the two. In a second mode  202 , the waveforms are separated by a delay of T 3  between the end of G 1  and the beginning of the pulse G 2 . In mode three, the wave forms are also separated by a delay T 3 , but the pulse width of the two waves is different between the two waveforms, and in mode four the waveforms are overlapping and of different widths.  
           [0005]    In practical systems, such as those utilized by the assignee of the present invention, the four sets of waveforms described herein are suitable to meet the command and control needs of most systems.  
           [0006]    Typically, the control waveforms are generated using either analog or hardwired digital circuitry. An analog implementation conventionally uses a voltage-controlled oscillator (VCO) and an analog comparator to control a pulse width based upon an analog feedback loop. A digital PWM control circuit is typically implemented using a digital counter and register.  
           [0007]    The digital implementation is normally preferred due to its increased accuracy and the fact that it is not as susceptible to temperature changes, etc. However, to date, there does not exist a flexible PWM generator that can create any of the required four waveforms, and which also includes reliable protection circuitry. There exists a need for such a system, along with the ability to change modes for different types of operation.  
         SUMMARY OF THE INVENTION  
         [0008]    The above and other problems of the prior art are overcome in accordance with the present invention. More specifically, a multi-function PWM module is designed to generate any of several waveforms that may be utilized to drive a ballast.  
           [0009]    The inventive technique uses a programmable set of registers in combination with configurable logic circuitry in order to emulate different hardware arrangements that would otherwise generate a specific one of the four possible sets of waveforms.  
           [0010]    In the preferred embodiment, values are programmed into a control register, and such values are then used to configure the logic circuitry for a specified delay and offset with respect to two signals. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    [0011]FIG. 1 depicts an exemplary hardware and functional diagram of an exemplary embodiment of the present invention;  
         [0012]    [0012]FIG. 2 shows a set of waveforms that may be used to drive an electronic ballast of the type that the present invention may be used in conjunction with;  
         [0013]    [0013]FIG. 3 depicts an exemplary arrangement that can be used to generate the signals required for a first mode of operation of the present invention;  
         [0014]    [0014]FIG. 3A depicts a timing diagram of several signals utilized in said first mode;  
         [0015]    [0015]FIG. 4 depicts an exemplary arrangement that can be used to generate the signals required for a second mode of operation of the present invention;  
         [0016]    [0016]FIG. 4A depicts a timing diagram of several signals utilized in said second mode;  
         [0017]    [0017]FIG. 5 depicts an exemplary arrangement that can be used to generate the signals required for a third mode of operation of the present invention;  
         [0018]    [0018]FIG. 5A depicts a timing diagram of several signals utilized in said third mode;  
         [0019]    [0019]FIG. 6 depicts an exemplary arrangement that can be used to generate the signals required for a third mode of operation of the present invention;  
         [0020]    [0020]FIG. 6A depicts a timing diagram of several signals utilized in said third mode; 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0021]    [0021]FIG. 1 depicts an exemplary block diagram of an arrangement in accordance with the present invention. The arrangement comprises basic logic circuitry  1  that may be implemented utilizing discrete components, and a programmable logic array, or other similar arrangement. The system of FIG. 1 also includes a control register  102  for storing various values described below and loading those values for use by logic circuitry  101 . Counters  103  and  104  and registers  105  and  106  serve to apply the relevant signals for use in circuitry  101 . Counters  110  and  112  feed the output logic  114  as shown in order generate the signals G 1  and G 2 . These counters are loaded via registers  16  and  118  as shown.  
         [0022]    The storage locations  0  through  7  in control register  102  contain the information for operating the PWM module. SR position  0  is software reset with functions to reset all counters and registers, other than the control register, to 0. Locations  1  and  2  designated PM ( 1 ) and PM ( 2 ) represent two bits utilized to specify the particular one of the four possible modes that should be utilized to generate the signals G 1  and G 2 . Locations  3  and  4  represent synchronous stop bits for the signals G 1 , G 2  and the signals GE 1  and GE 2  (GE 1  and GE 2  used for electrode heating control).  
         [0023]    Locations  5  through  6  of control register  102  represent protection control bits, which serve to set a maximum voltage to be delivered. This protects the circuitry in the event the PWM duty cycle becomes large enough to otherwise produce an overvoltage condition. Finally, location  7  is labeled T lock, and represents a timing parameter lock control bit. The T lock location is set when all other parameters for the PWM signal are valid. This prevents the PWM signal from starting until all parameters for the signal are correctly set.  
         [0024]    Registers  105 ,  106 ,  116 ,  118  and  120  are utilized to set the various timing, frequency, and pulse width parameters for the generation of waveforms G 1  and G 2 . More specifically, in the exemplary embodiment, register  105  represents the frequency of the PWM signal to be generated. Register  116  is a parameter T 1 , which represents the pulse width of signal G 1 . Register  118  is a parameter denoted T 2 , which represents the pulse width of G 2 . Finally, register  106  is a parameter T 3 , which is set equal to the desired delay between G 1  and G 2  pulses in order to obtain the proper off-set.  
         [0025]    The register  120  is used to store a parameter TE, which is a desired pulse width of GE 1 /GE 2 . GE 1  and GE 2  are used for electrode heating control, rather than ballast control. Register  122  stores the value of the minimum pulse width in order to provide protection of the circuit in the case of an overvoltage condition.  
         [0026]    All counters shown as  103 ,  104 ,  110 ,  112 , and  128  are binary programmable counters. The counters utilize numbers stored in their associated registers are shown and then count up to or down from those numbers in order to generate the required pulse width timers, delays, etc.  
         [0027]    The operation of the system in the four different desired modes will now be described with reference to FIG. 1 through FIG. 4.  
         [0028]    In mode one, it is desirable to generate the waveforms indicated as  201  in FIG. 2. When control register  102  is set to implement mode 1, logic  101  is in the state shown in FIG. 3. The remaining elements of FIG. 1 are not utilized in mode 1. The timing diagram of the system shown in FIG. 3 is shown in FIG. 3A. The operation of the PWM module in mode 1 is as follows: During the time designated when G_FC=1, A 1  remains high and A 2  is low. The counter  110  is enabled and counter  112  is disabled. Since register  116  represents the pulse width of G 1 , output Q 1  of counter  110  will remain high until counter  110  finishes counting. Counter  110  will then stop counting and set G 1  equal to 0.  
         [0029]    As indicated in the timing diagram, FIG. 3A, the second counter  112  will then begin counting after pulling G 2  up to a logical high. When T 2 , the value in counter  112  is reached, the counter will stop counting and set G 2  back to 0 as shown in timing diagram of FIG. 3A. The dashed lines in FIG. 3A show the possible length of each of signals G 1  and G 2 . It can be appreciated that the operation in mode one provides that G 1  and G 2  are separate non-overlapping pulse trains and that each is typically the inverse of the other.  
         [0030]    Mode two is depicted in FIG. 4, with the corresponding timing diagram depicted below in FIG. 4A. Note that unlike the previous mode of operation, the arrangement of mode two includes the signals generated by counter  104 , and thus causes the delay shown as T 3  in the timing diagram of FIG. 4A. During the operation of the system in mode two, counters  104  and  110  are enabled and start counting. When the appropriate delay time T 3  is reached, counter  104  will stop counting and place a logical low on output Q 3 . This will cause signal G 1  to be placed high for a duration set by T 1 . When G 1  goes low, the circuitry of FIG. 4 causes an additional delay of T 3  before placing it high on signal G 2 . Thus, the two signals G 1  and G 2  represent square pulse trains separated by a delay T 3 .  
         [0031]    The additional logic shown in FIG. 4 is not the same as that of FIG. 3. Instead, the additional logic  402  implements the delay T 3  through a latch  409 , logic gates  410 , and a mutiplexer  411  as shown. The particular implementation of the appropriate logic is not material, and those of skill in the art will readily be able to implement the proper logic functions to generate a specified delay T 3  between signals.  
         [0032]    In a third mode shown in FIG. 5, the equivalent circuit established by programming the appropriate state into locations  1  and  2  of register  102  is depicted. As can be seen from the timing diagram of FIG. 5A, mode three is intended to generate pulse trains G 1  and G 2  separated by a delayed T 3  but wherein the pulse trains may overlap and thus be on at the same time. Additionally, the pulse trains may be different lengths. In operation, a small negative pulse A 1  is produced as shown in FIG. 5A. This causes counter  110  to begin counting in an amount sufficient to designate T 1 , with a pulse G 1 . After Q 3  maintains the appropriate delay T 3  as defined by counter  104 , the counter  112  will count out the appropriate amount to T 2 , in order to set the width of the pulse G 2 . Thus, the system generates two pulse trains delayed from each other by a distance T 3 , and the width of each is independent of the other. Additionally, the duty cycle can be as much as needed, even if greater than 50% of the entire cycle of the PWM signal.  
         [0033]    Finally, mode four of the operation is depicted in FIG. 6, with the corresponding timing diagram in FIG. 6A. Mode 4 allows the width of G 1  and G 2  to be over 50% of the entire cycle of each of the signals, and also allows G 1  and G 2  to be overlapped by an amount set by T 3 . All four possible sets of signals needed for ballast control may be generated.  
         [0034]    It can be appreciated from the above that any of the four desired modes may be generated in a single logic circuit and from the same clock and signal sources. Thus, changing the mode of operation is a simple matter of software programming.  
         [0035]    The above describes the preferred embodiment of the invention, but various modifications will be apparent to those of skill in the art. Such modifications include utilizing different circuitry for generation of the signals.