Abstract:
A control system is disclosed for the control of sequential flow of functions in teletypewriters and data typewriters. Input signals are presented to the control system which release the carrying out of the functions. The control system produces output signals which correspond to individual steps of the functions to be carried out successively. A plurality of control units are provided in the control system with each of the control units being provided with a respective allocator. The control units produce control signals which are formed in accordance with the state of signals presented at inputs of the control units. These control unit input signals may correspond to the control system input signals and/or the control signals at the outputs of the control units. At least a portion of the control signals are utilized as the output signals for the control system.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to a control system for the control of the sequential flow of functions in an apparatus, particularly in teletypewriters or data typewriters. The control system to which input signals are connected releases the carrying-out of functions and produces output signals assigned to individual steps of the functions to be carried out at successive points in time. 
     Control systems are provided in communications technology equipment and electronic data processing. They control the sequential or chronological flow of functions in the apparatus. These control systems are normally constructed of a multiplicity of binary logic elements and storage elements. These logic elements and storage elements are put together by the designer of such a control system. The type and number of the logic elements and storage elements and also their arrangement in the control system in prescribed functions to be carried out are determined in accordance with the estimates of the designer. The internal logical functions of the control system are completely defined by this process and are documented in the form of a logic plan. The consequence of this is that the structure of the control system, particularly in irregular networks, is not uniform and is topographically very complicated. Therefore the diagram becomes unclear and function alterations can only be carried out with great difficulty. Furthermore, the description of the control systm must proceed on the level of the logic and storage elements as only at this level are the logical functions completely defined. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to disclose a control system in which the structure of the logic and storage elements is predefined so that a flow diagram illustrating an arbitrary function can be unequivocally imaged by the logic elements and storage elements. 
     The objective is inventively resolved with a control system of the invention wherein the control system contains a multiplicity of control units which are respectively provided with an allocator that produces control signals in dependence upon signals at its inputs, that the input signals and/or the control signals connect with the inputs of the control units, and that at least some of the control signals represent the output signals. 
     The control system in accordance with the present invention has the advantage that it exhibits a topographically simple structure, and in conjunction with the flow diagrams simplicity even with complicated functions is provided. Furthermore, the construction of the control unit is very well suited for simulations in data processing setups. 
     A particularly uncomplicated structure of the control system is obtained when the control units are hierarchically arranged, wherein a first control unit controls the execution of a main function, and additional control units control the execution of secondary functions. 
     In case a multiplicty of functions is to proceed in parallel, it is of advantage when the control units are arranged in parallel, whereby each control unit controls the execution of at least one function. 
     The production of individual steps of the functions to be carried out which are allocated to the output signals is obtained in a simple manner when each control unit contains a counter which can be continuously switched by means of counting impulses. An output of the counter is connected to the inputs of the allocator which respectively calls portions of the allocator which are assigned to individual component functions, depending upon its counter position. 
     The control unit is inexpensive if at least one control stage is provided for the execution of special functions which has control signals connected to its inputs and whose outputs can be connected to inputs of the control units. Such special functions can be storage fields, counters, arithmetic logic units etc. 
     A uniform design of the control system is obtained since the allocators are respectively formed from a plurality of logic elements carrying out an AND function. Additional logic elements are connected at an output side of the first mentioned logic elements to carry out an OR function. 
     One control unit and one sample embodiment of a control system in accordance with the invention are shown in the drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a block circuit diagram of a control unit of the control system; 
     FIG. 2 illustrates a block circuit diagram of the control system; 
     FIG. 3 shows a flow diagram of a function to be controlled by the control system; and 
     FIG. 4 shows a circuit diagram of a portion of the control system. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The control unit illustrated in FIG. 1 contains an allocator ZU, an input stage ES, and also a pulse generator TG. Signals X1 are conveyed to the control unit which are output by an input unit, for example, a keyboard. The control unit provides control signals Y1 at its output which are conveyed to an apparatus to be controlled, for example to a teletypewriter or data typewriter. The input stage ES consists of a first sub-stage ESX, in which the signals X1 can be intermediately stored. This sub-stage, however, is not necessarily required as, for example, the signals X1 can also be stored in the input unit of the keyboard, for example, as described above. Signals Z1 which represent a portion of the control signals Y1 are intermediately stored in a second sub-stage ESZ of the input stage ES. The conveyance of the signals X1 or Z1 into the input stage results with the aid of clock pulses T produced in the pulse generator TG. After each clock pulse T, the control signals Y1 assume values which are corresponding to the signals X1 and Z1 before the clock pulse T. This occurs for each of the clock pulses. The allocation proceeds with the aid of the allocator ZU which, for example, consists of a fixed value store or of an AND field formed of a multiplicity of AND elements A1 through An, and of an OR field which is connected at the output side and formed of a multiplicity of OR elements D1 through Dn. The control signal SY1, for example, assumes the binary value of 1 when the signals SX1 and SZ1 have the binary value of 1, and the signal SXn has simultaneously the binary value of 0 at the input of the allocator or when the signals SX1 and SZn have the binary value of 1 and the signal SX2 has the binary value of 0. 
     Allocators which are formed from an AND and an OR field are already known and are available under the name PLA (programmable logic array) modules. Such modules, however, did not generally succeed as they do not exhibit a module-like structure since the chronological function flows cannot readily be observed and regular sequential networks such as counters, shift registers, etc. can only be reproduced in a very redundant manner. 
     The control system illustrated in FIG. 2 exhibits a hierarchical design of a multiplicity of control units. Each of these control units is similarly constructed as the control unit illustrated in FIG. 1. Each of these control units contains in addition to respective allocators ZH, ZU1, ZU2 an additional counter ZAH, ZAU1, ZAU2 whose counter position can be altered step-by-step by means of clock pulses. The outputs of the counters are connected to inputs of AND elements in the AND field in the respectively corresponding control electronics, and, in dependence upon the counter positions of the respective counters, only a portion of the allocator is released. With the aid of the counters, the functions to be carried out by the control system can be divided into simplified sub-functions (such as U1 and U2 explained hereafter) in a very simple manner. 
     The input signals X, a portion of the output signals Y conveyed as signals Z and signals W which are produced from a control stage SS are conveyed to the stage ESH. The control stage SS is provided in order to carry out special functions. The control stage SS, for example, is fashioned as a known counter (e.g. T.I. SN 74 161) which is continuously switched by means of clock pulses and which is released or blocked by means of one or more output signals Y. The control stage SS can also be structured in a similar fashion as a control unit. 
     The input stage ESU is connected at the input side with the outputs of the allocator ZH. With the aid of the input stage ESU, the secondary functions are called which are carried out with the aid of the allocator ZU1 and ZU2. If, for example, a binary value of 1 is stored in a storage stage U1 of the input stage ESU, the allocator ZU1 is released and the secondary function represented by this allocator ZU1 is carried out. In case the binary value 1, for example, is stored in the storage stage U2 of the input stage ESU, the subfunction represented by the allocator ZU2 is carried out in accordance therewith. It is also possible to carry out two subfunctions simultaneously. 
     It is assumed that the counter ZAH which controls the chronological flow of the main function has the counter position 0. Thus, only those portions are released in the allocator ZH which are allocated to this counter position. If, for example, the main function consists of three steps, the counter ZAH consecutively assumes the step-by-step counter position 0, 1, 2. If a subfunction, dependent upon the main function is to be carried out, the respective allocator is called with the aid of a control signal SU via the input stage ESU. With control by the respective counter ZAU, the execution of the respective subfunctions is controlled. During the execution of the subfunction, a continuous switching of the counter ZAH is prevented with the aid of output signals Y. After the execution of the subfunction is concluded, the counter ZAH is again released and the next step of the main function is carried out. When the last step of the main function has been carried out, a respective output signal Y results. The counter ZAH can thus be reset to its initial value. 
     In the flow diagram of a main function to be carried out by the control system as illustrated in FIG. 3, the diamond-shaped boxes represent interrogations in a fashion similar to program flow diagrams. The rectangular boxes indicate that a specific command is to be carried out. The main function, for example, consists of three steps 0, 1 and 2. In the steps 0 and 2 a subfunction U1 or U2 is respectively carried out. 
     Additional details of FIG. 3 are described in conjunction with the circuit diagram illustrated in FIG. 4. 
     The circuit diagram illustrated in FIG. 4 exhibits a portion of the control unit provided with the allocator ZH. The control unit carries out the main function illustrated in FIG. 3. The control unit contains the allocator ZH and the input stage ESH which consists of four flip flops FB through FE and an inverter N. Furthermore, the input stage contains the counter ZAH which is formed by the counter stages Z1 and Z2 and is actuated by a counting pulse ZT. The allocator ZH consists of an AND field which is formed by the vertical lines and the horizontal lines at the outputs of the input stage ESH and the counter ZAH. An OR field is formed of the horizontal lines at which the signals S and also SU1 and SU2 are given off. The cross marks at the intersections of the lines respectively indicate which signals are conveyed to the inputs of the AND or OR elements. 
     At the beginning of the main function at the starting point in FIG. 3, the counter ZAH has a counter position of 0 and the first step of the main function is carried out. The signals at the inverting outputs of the counter stages Z1 and Z2 have the binary value of 1. The first step of the main function interrogates whether the signal A provided at the output of the input stage ESH has the binary value of 1. The signal A is therefore conveyed to an input of an AND element in the AND field where the signals at the inverting outputs of the counter stages Z1 and Z2 are conveyed to the additional inputs of the AND element. If the signal A has the binary value of 1, the signal SU1 results at the output of the allocator which sets the storage stage U1 in the input stage ESU and causes a flow of a subfunction U1&#39;. If the signal A does not have the binary value of 1, no signal is given off at the output of the allocator ZH. 
     When a counting pulse ZT appears at the input of the counter ZAH, it assumes the counter position 1 and the second stage of the main function is carried out. Signals with the binary value of 1 result at the non-inverting output of the counting stage Z1 and at the inverting output of the counting stage Z2 during the second step. If the signals A, C, and D have the binary value of 0 during this second step and if the signal B simultaneously has the binary value of 1, the signal S results at the output of the allocator ZH in accordance with the flow diagram in FIG. 3. This signal S is also present when the signals A, B, C, D, and E have the binary value of 0. The signal S prevents clock pulses ZT for the counter ZAH so that the counter position of the counter ZAH does not change as long as S has the logic binary value of 1. 
     By means of an additional clock pulse ZT, the counter position of the counter ZAH is increased to 2 in order to carry out the third step of the main function. Signals with the binary value of 1 are given off at the inverting output of the counting stage Z1 and at the non-inverting output of the counting stage Z2. In case the signal A has the binary value of 0 during the third step and thus the signal inverted by means of the inverter N has the binary value of 1, a signal SU2 results at the output of the allocator ZH which sets the storage stage U2 in the input stage ESU. By means of a signal at the output of the storage stage U2, the allocator ZU2 is called and the subfunction U2&#39; is carried out. In a manner similar to the carrying out of the subfunction U1&#39;, the counter ZAU2 is continuously switched step-by-step during the execution of the subfunction U2&#39; and signals assigned to the individual steps of the subfunction U2&#39; are given off as singals Y at the output of the control system. In case the signal A has the binary value of 1 in the third step of the main function, no signal is given off at the output of the allocator ZH. 
     With the aid of a signal RS, which is conveyed to the counter ZAH, the counter can be reset to an initial counter position. The signal RS, for example, may be provided at the output of the allocator ZU2 after the subfunction U2&#39; is carried out. 
     Although various minor modifications may be suggested by those versed in the art, it should be understood that I wish to embody within the scope of the patent warranted hereon, all such embodiments as reasonably and properly come within the scope of my contribution to the art.