Abstract:
A memory system manages memory blocks of a nonvolatile memory device by determining at least one memory block property of a selected memory block among the multiple memory blocks in the nonvolatile memory device, storing memory block property information indicating the at least one memory block property, arranging a free memory block list based on the stored memory block property information, and designating a free memory block from the arranged free memory block list as an active memory block, wherein the designation of the free memory block as an active memory block is based on an ordering of the free memory block list.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2013-0010019 filed on Jan. 29, 2013, the subject matter of which is hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    The inventive concept relates generally to electronic memory technologies. More particularly, certain embodiments of the inventive concept relate to memory systems and block management methods for the memory systems. 
         [0003]    Memory devices are generally subject to deterioration according to usage. In some devices, deterioration may occur on a memory cell by memory cell basis. For example, individual memory cells in a flash memory may fail after they are programmed, erased, or read a predetermined number of times. 
         [0004]    To prevent some memory cells from failing well before others, memory devices often implement so-called wear-leveling schemes to ensure that memory cells are used—and therefore wear out—at a similar rate. Such wear-leveling schemes typically keep track of the number of access operations (e.g., erase and/or program operations) performed on each memory cell or group of memory cells (e.g., a memory block), and they select memory cells to be programmed or erased based on the number. For instance, a memory block that has been programmed or erased fewer times may be selected so that some memory blocks are not erased substantially more than others. 
         [0005]    A drawback of conventional wear-leveling schemes is that they generally ignore small variations between individual memory cells. For instance, by equalizing the number of access operations performed on different memory cells, these schemes assume that the memory cells are destined to endure approximately the same number of access operations, even though they may in fact differ substantially in their actual endurance. Consequently, these schemes may lead to relatively high bit error rates (BERs) and early failure for some memory blocks and relatively low BERs and later failure for others. 
       SUMMARY OF THE INVENTION 
       [0006]    In one embodiment of the inventive concept, a method is provided for managing memory blocks in a memory system comprising a nonvolatile memory device. The method comprises determining at least one memory block property of a selected memory block among the multiple memory blocks in the nonvolatile memory device, storing memory block property information indicating the at least one memory block property, arranging a free memory block list based on the stored memory block property information, and designating a free memory block from the arranged free memory block list as an active memory block, wherein the designation of the free memory block as an active memory block is based on an ordering of the free memory block list. 
         [0007]    In another embodiment of the inventive concept, a memory system comprises a nonvolatile memory device comprising multiple memory blocks and a meta area, and a memory controller configured to control the nonvolatile memory device. The meta area stores erase count information, a ready-to-use list of memory blocks, a long term list of memory blocks, and memory block retry information for memory blocks in the ready-to-use list and the long term list. The memory controller performs a wear-leveling operation on the memory blocks using the erase count and the memory block retry information. The ready-to-use list is a list of memory blocks each having a relatively low threshold voltage offset, the long term list is a list of memory blocks each having a relatively high threshold voltage offset, and the memory block retry information is obtained from read retry operations performed on the memory blocks in the ready-to-use list and the long term list. 
         [0008]    These and other embodiments of the inventive concept can potentially improve the reliability of a nonvolatile memory device by performing wear leveling according to both usage information of memory blocks, as well as operational characteristics of the memory blocks. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The drawings illustrate selected embodiments of the inventive concept. In the drawings, like reference numbers indicate like features. 
           [0010]      FIG. 1  is a memory block diagram illustrating a memory system according to an embodiment of the inventive concept. 
           [0011]      FIG. 2  is a diagram illustrating life-cycle of memory blocks illustrated in  FIG. 1 . 
           [0012]      FIG. 3  is a diagram illustrating a read retry operation of a memory block having memory cells with relatively low threshold voltage offsets. 
           [0013]      FIG. 4  is a diagram illustrating a read retry operation of a memory block having memory cells with relatively high threshold voltage offsets. 
           [0014]      FIG. 5  is a diagram illustrating a method of managing free memory blocks according to an embodiment of the inventive concept. 
           [0015]      FIG. 6  is a diagram illustrating a method of sorting a ready-to-use list of memory blocks according to an embodiment of the inventive concept. 
           [0016]      FIG. 7  is a diagram illustrating a method of sorting a long term list of memory blocks according to an embodiment of the inventive concept. 
           [0017]      FIG. 8  is a flowchart illustrating a method of performing wear-leveling in a memory system according to an embodiment of the inventive concept. 
           [0018]      FIG. 9  is a flowchart illustrating a method of performing block management in a memory system according to an embodiment of the inventive concept. 
           [0019]      FIG. 10  is a memory block diagram illustrating a solid state drive according to an embodiment of the inventive concept. 
           [0020]      FIG. 11  is a memory block diagram illustrating an eMMC according to an embodiment of the inventive concept. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    Embodiments of the inventive concept are described below with reference to the accompanying drawings. These embodiments are presented as teaching examples and should not be construed to limit the scope of the inventive concept. 
         [0022]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0023]      FIG. 1  is a memory block diagram illustrating a memory system  10  according to an embodiment of the inventive concept. 
         [0024]    Referring to  FIG. 1 , memory system  10  comprises at least one nonvolatile memory device  100  and a memory controller  200  controlling nonvolatile memory device  100 . 
         [0025]    For explanation purposes, it will be assumed that nonvolatile memory device  100  is a NAND flash memory device, although the inventive concept is not limited to a NAND flash memory device. For example, concepts described with reference to nonvolatile memory device  100  could also be applied to a NOR flash memory device, a Resistive Random Access Memory (RRAM) device, a Phase-Change Memory (PRAM) device, a Magnetroresistive Random Access Memory (MRAM) device, a Ferroelectric Random Access Memory (FRAM) device, a Spin Transfer Torque Random Access Memory (STT-RAM), and the like. Further, the nonvolatile memory device can be implemented to have a three-dimensional array structure. The inventive concept may be applied to a Charge Trap Flash (CTF) memory device including a charge storage layer formed of an insulation film as well as a flash memory device including a charge storage layer formed of a conductive floating gate. 
         [0026]    Nonvolatile memory device  100  comprises multiple memory blocks BLK 0  to BLKz, each comprising multiple cell strings. Each cell string typically comprises at least one string selection transistor, multiple memory cells, and at least one ground selection transistor which are connected in series. Each of the memory cells may store at least one bit of data, and may be driven by a voltage transferred through a corresponding one of word lines. 
         [0027]    A meta area  110  stores management information used to manage nonvolatile memory device  100 . Meta area  110  stores a ready-to-use list  111 , a long term list  112 , and memory block retry information  113 . Ready-to-use list  111  is a list of memory blocks having a memory cells with relatively low threshold voltage offsets, and long term list  112  is a list of memory blocks having memory cells with relatively high threshold voltage offsets. 
         [0028]    The relatively low and high threshold voltage offsets are determined through a read retry operation in which a sequence of different read voltages are applied to selected memory cells until the memory cells are successfully read. The read retry operation typically applies an initial default read voltage to the selected memory cells and then either increases or decreases the default read voltage until a desired outcome is achieved. For instance, in an example illustrated in  FIG. 3 , a read voltage is decreased until it falls below an upper one of two adjacent threshold voltage distributions of the selected memory cells. Similarly, in an example illustrated in  FIG. 4 , a read voltage is increased until it rises above a lower one of two adjacent threshold voltage distributions of the selected memory cells. 
         [0029]    Where the read voltage required to successfully read the selected memory cells is greater than the default read voltage, the selected memory cells (or alternatively, memory block) are deemed to have a relatively high threshold voltage offset. More particularly, their threshold voltages are deemed to have a positive offset relative to the default read voltage. On the other hand, where the read voltage required to successfully read the selected memory cells is less than the default read voltage, the selected memory cells (or alternatively, memory block) are deemed to have a relatively low threshold voltage offset. More particularly, their threshold voltages are deemed to have a negative offset relative to the default read voltage. The use of the terms “relatively low” and “relatively high” in this context merely indicates that the relatively low threshold voltage offset is below the relatively high threshold voltage offset. 
         [0030]    Memory block retry information  113  comprises an offset voltage and address information for a memory block. The offset voltage indicates actual offset of the read voltage required to successfully read the selected memory cells. 
         [0031]    Ready-to-use list  111  and long term list  112  may be determined based on memory block retry information  113 . For example, where an offset voltage is a negative value (e.g., a memory cell has a relatively low threshold voltage offset), a memory block corresponding to address information may be included in ready-to-use list  111 . On the other hand, where an offset voltage is a positive value (e.g., a memory cell has a relatively high threshold voltage offset), a memory block corresponding to address information may be included in long term list  112 . 
         [0032]    Memory controller  200  controls nonvolatile memory device  100 . Memory controller  200  comprises a memory block management unit  220  to manage the memory blocks BLK 0  to BLKz. 
         [0033]    Memory block management unit  220  manages wear-leveling of the memory blocks BLK 0  to BLKz based on memory block usage information and property information of memory cells (or, memory blocks). In other words, in contrast to certain conventional approaches that merely use memory block usage information, memory block management unit  220  manages wear-leveling based on the usage and the properties of memory cells and/or memory blocks. The memory block usage information typically comprises an erase count, a program count, and/or a read count. Although not shown in  FIG. 1 , the memory block usage information may be stored at meta area  110 . Also, the memory cell property information may be memory block retry information  113  associated with retention or endurance. 
         [0034]    After a read retry operation is performed on a memory block, memory block management unit  220  stores memory block retry information  113  associated with the read retry operation in meta area  110 . Memory block management unit  220  sorts ready-to-use list  111  and long term list  112  based on memory block retry information  113 . Memory block management unit  220  may assign a memory block, having the best relatively low threshold voltage offset, from among free memory blocks to an active memory block for a data write operation. 
         [0035]    In contrast to conventional systems, memory system  10  may perform wear-leveling in consideration of both an erase count and memory cell properties, such as a threshold voltage offset. This can be accomplished through the use of ready-to-use list  111  and long term list  112 , as will be apparent from the description that follows. 
         [0036]      FIG. 2  is a diagram illustrating life-cycle of blocks BLK 0  to BLKz of  FIG. 1 . 
         [0037]    Referring to  FIG. 2 , first, an unused block  121  is in an erase state. Unused block  121  can be designated as an active memory block  122  in which data is to be written. If data is successfully written in active memory block  122  assigned, active memory block  122  may be designated as a valid memory block  123 . Where a write operation on active memory block  122  fails, the active memory block may be designated as a bad memory block  124 . Otherwise, if data of valid memory block  123  is determined to be invalid in a merge operation, valid memory block  123  may be designated as an invalid memory block  125 . 
         [0038]    If an erase operation is successfully performed, invalid memory block  125  may be designated as a free memory block  126 . Free memory block  126  may be designated as a ready-to-use block  127  or a long term block  128  according to a memory cell property (e.g., a threshold voltage offset determined by a read retry operation). Ready-to-use block  127  is a free memory block comprising memory cells each having a relatively low threshold voltage offset, and the long term block  128  may be a free memory block comprising memory cells each having an relatively high threshold voltage offset. Ready-to-use block  127  may be newly designated as an active memory block  122 . For example, ready-to-use block  127  having a lowest threshold voltage offset may be designated as an active memory block  122 . Long term block  128  may be designated as a ready-to-use block  127  after a predetermined lapse of time. 
         [0039]    Meanwhile, if an erase operation fails, invalid memory block  125  may be designated as a bad memory block  124 . In some situations, although not shown in  FIG. 2 , the bad memory block  124  can be designated as a free memory block  126  if an erase operation is successfully performed under a predetermined condition. 
         [0040]      FIG. 3  is a diagram illustrating a read retry operation for a memory block having a relatively low threshold voltage offset, and  FIG. 4  is a diagram illustrating a read retry operation for a memory block having a relatively high threshold voltage offset. In each of  FIGS. 3 and 4 , solid curves represent ideal threshold voltage distributions of selected memory cells, and dotted curves represent actual threshold voltage distributions that may exist among selected memory cells. As indicated by a tallest vertical line in each of  FIGS. 3 and 4 , a default read voltage Vdflt falls between the ideal threshold voltage distributions, and could be used to read the selected memory cells if their threshold voltage distributions did not deviate from the ideal. Meanwhile, shorter vertical lines indicate read voltages used in successive iterations of the read retry operation. A threshold voltage offset Vost represents a difference between the default read voltage Vdflt and a read voltage that results in successful reading of the selected memory cells. 
         [0041]    Referring to  FIG. 3 , the read retry operation proceeds by decreasing the read voltage from default read voltage Vdflt in successive iterations. The read retry operation is generally successful once the read voltage falls below an upper one of two threshold voltage distributions. Once this occurs, a memory block property is determined to be “relatively low threshold voltage offset”, and corresponding block retry information is stored as memory block retry information  113 . Memory block retry information  113  may be, for instance, a bit or a value indicative of the relatively low threshold voltage offset, or it may be a read retry number corresponding to the offset voltage Vost. As used in this description, the term “memory block property” denotes an operational characteristic of memory cells belonging to a memory block, as opposed to mere historical information, such as an erase count, for example. 
         [0042]    Referring to  FIG. 4 , the read retry operation proceeds by increasing the read voltage from default read voltage Vdflt in successive iterations. The read retry operation is generally successful once the read voltage rises above a lower one of two threshold voltage distributions. Once this occurs, a memory block property is determined to be “relatively high threshold voltage offset”, and corresponding block retry information is stored as memory block retry information  113 . Memory block retry information  113  may be, for instance, a bit or a value indicative of the relatively high threshold voltage offset, or it may be a read retry number corresponding to the offset voltage Vost. 
         [0043]      FIG. 5  is a diagram illustrating a method of managing free memory blocks according to an embodiment of the inventive concept. 
         [0044]    Referring to  FIG. 5 , a free memory block list comprises a ready-to-use list and a long term list. The ready-to-use list indicates memory blocks having a relatively low threshold voltage offset. The long term list comprises memory blocks having an relatively high threshold voltage offset. The memory blocks listed in the long term list may be subsequently transferred to the ready-to-use list after a predetermined lapse of time, e.g., several weeks or months. 
         [0045]      FIG. 6  is a diagram illustrating a method of sorting a ready-to-use list of memory blocks according to an embodiment of the inventive concept. 
         [0046]    Referring to  FIG. 6 , the ready-to-use list is sorted sequentially according to a determined threshold voltage offset, starting with a memory block address “0x25” having a largest threshold voltage offset. The first memory block in the list will be the first memory block to be re-designated as an active memory block according to the life-cycle illustrated in  FIG. 2 . 
         [0047]      FIG. 7  is a diagram illustrating a method of sorting a long term list of memory blocks according to an embodiment of the inventive concept. 
         [0048]    Referring to  FIG. 7 , the long term list is sorted sequentially according to a determined threshold voltage offset, starting with a memory block address “0x25” having a smallest threshold voltage offset. The first memory block in the list will be the first memory block to be re-assigned to the ready-to-use list according to the life-cycle illustrated in  FIG. 2 . 
         [0049]      FIG. 8  is a flowchart illustrating a method of performing wear-leveling in a memory system according to an embodiment of the inventive concept. 
         [0050]    Referring to  FIGS. 1 to 8 , the method determines whether an invalid memory block erase count (BLK EC) is less than an average erase count (Avg. EC) (S 110 ). If the memory block erase count is less than the average erase count, garbage collection may be performed on the memory block. The garbage collection operation is intended to reclaim invalid memory blocks as free memory blocks. The garbage collection operation may comprise, for instance, erasing an invalid memory block and performing a read retry operation on the erased memory block. During the read retry operation, the method may determine and set memory block retry information  113 , as illustrated for instance, in  FIGS. 3 and 4  (S 120 ). 
         [0051]    Thereafter, the method determines whether the memory block retry information  113  indicates that the memory block has a relatively low or relatively high threshold voltage offset (S 130 ). If so, the memory block is assigned to the ready to use list (S 140 ), and if not, the memory block is assigned to the long term list (S 145 ). 
         [0052]    Following operations S 140  and S 145 , data is programmed in a first memory block in the ready to use list (S 150 ). 
         [0053]    Although the above description assumes that a memory block property is determined by a read retry operation, the inventive concept is not limited to this type of determination. For example, in alternative embodiments a memory block property may be determined according to other methods. 
         [0054]      FIG. 9  is a flowchart illustrating a method of managing memory blocks in a memory system according to an embodiment of the inventive concept. 
         [0055]    Referring to  FIG. 9 , the method determines whether a memory block has a relatively low threshold voltage offset or a relatively high threshold voltage offset (S 210 ). Under these circumstances, the threshold voltage offset may be expressed, for example, as a numerical value. Next, memory block property information, including a the threshold voltage offset, is stored (S 220 ). Then, a free memory block list is arranged (e.g., sorted) based on the stored memory block property information (S 230 ). Here, the free memory block list may be arranged so that a memory block having a lower threshold voltage offset (i.e., more negative or less positive) is to be preferentially designated as an active memory block. Then, an active memory block is selected from the free memory blocks arranged to program data (S 240 ). 
         [0056]      FIG. 10  is a memory block diagram illustrating a solid state drive according to an embodiment of the inventive concept. 
         [0057]    Referring to  FIG. 10 , a solid state drive (SSD)  1000  comprises multiple flash memory devices  1100  and an SSD controller  1200 . Flash memory devices  1100  may be configured to receive an external high voltage VPPx. A wear-leveling method described with reference to  FIGS. 1 to 9  may be applied to each flash memory device  1100 . SSD controller  1200  may be connected to flash memory devices  1100  via multiple channels CH 1  to CHi. SSD controller  1200  comprises at least one processor  1210 , a buffer memory  1220 , a host interface  1250 , and a flash interface  1260 . 
         [0058]      FIG. 11  is a memory block diagram illustrating an embedded MMC (eMMC) according to an embodiment of the inventive concept. 
         [0059]    Referring to  FIG. 11 , an eMMC  2000  comprises at least one NAND flash memory device  2100  and controller  2200  integrated in a chip. NAND flash memory device  2100  may be a single data rate (SDR) NAND flash memory device or a double data rate (DDR) NAND flash memory device. In example embodiments, the NAND flash memory device  2100  may comprise NAND flash memory chips. Herein, the NAND flash memory device  2100  may be implemented by stacking the NAND flash memory chips at one package (e.g., FBGA, Fine-pitch Ball Grid Array, etc.). A wear-leveling or block management method described with reference to  FIGS. 1 to 9  may be applied to each NAND flash memory device. 
         [0060]    Controller  2200  may be connected with the flash memory device  2100  via multiple channels. Controller  2200  comprises at least one controller core  2210 , a host interface  2110 , and a NAND interface  2260 . Controller core  2210  controls overall operations of eMMC  2000 . Host interface  2110  may be configured to interface between controller  2210  and a host. NAND interface  2260  is configured to provide an interface between NAND flash memory device  2100  and controller  2200 . Host interface  2110  may be a parallel interface (e.g., an MMC interface). In other example embodiments, host interface  2110  of eMMC  2000  may be a serial interface (e.g., UHS-II, UFS, etc.). 
         [0061]    EMMC  2000  typically receives power supply voltages Vcc and Vccq from the host. Herein, the power supply voltage Vcc (about 3.3V) may be supplied to the NAND flash memory device  2100  and the NAND interface  2260 , and the power supply voltage Vccq (about 1.8V/3.3V) may be supplied to controller  2200 . 
         [0062]    EMMC  2000  is applicable to small-sized and low-power mobile products (e.g., Galaxy S series, Galaxy note series, iPhone, iPad, Nexus, etc.). 
         [0063]    The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the scope of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.