Abstract:
Methods of operating a power supply switching circuit including selecting a first power supply signal for provisioning through the power supply switching circuit to a electronic storage device. A current draw can be detected via the first power supply signal that exceeds a predetermined current limit and a second power supply signal can be coupled to the first power supply signal for provisioning through the power supply switching circuit to the electronic storage device responsive to the current draw exceeding the predetermined current limit.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This U.S. Non-provisional application claims priority under 35 USC §119 to Korean Patent Application No. 10-2015-0123984, filed on Sep. 2, 2015, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated by reference in its entirety herein. 
       FIELD 
       [0002]    Example embodiments relate generally to power circuits, and more particularly to power circuits using a plurality of power sources having different voltages. 
       BACKGROUND 
       [0003]    A solid state drive (SSD) may use a plurality of voltages (for example, 12[V], 5[V] and 3.3[V]) as input voltages. Some conventional SSDs use one of the plurality of voltages. Some conventional SSDs use two or more voltages of the plurality of voltages. 
       SUMMARY 
       [0004]    Embodiments according to the inventive concept can provide methods of operating a power supply switching circuit including selecting a first power supply signal for provisioning through the power supply switching circuit to a electronic storage device. A current draw can be detected via the first power supply signal that exceeds a predetermined current limit and a second power supply signal can be coupled to the first power supply signal for provisioning through the power supply switching circuit to the electronic storage device responsive to the current draw exceeding the predetermined current limit. 
         [0005]    Embodiments according to the inventive concept can provide a power circuit that includes a first power signal generator configured to generate a first input power signal having a first input voltage. A second power signal generator can be configured to generate a second input power signal having a second input voltage whose level is less than a level of the first input voltage. A regulator can be configured to generate a first internal power signal based on the first input voltage, the first internal power signal having a first internal current and a first internal voltage that is greater than the second input voltage by an offset voltage. A current damper can be configured to clamp the first internal power signal based on a limited current amount and configured to generate a second internal power signal having a second internal voltage and a second internal current and a switch circuit can be configured to output one of the second internal power signal and a sum of the second input power signal and the second internal power signal as an output power signal, based on a difference between the second internal voltage and the second input voltage. 
         [0006]    Embodiments according to the inventive concept can a power circuit that includes a first signal generator configured to generate a first input power signal having a first input voltage. A second signal generator can be configured to generate a second input power signal having a second input voltage whose level is less than a level of the first input voltage. A regulator can be configured to generate a first internal power signal based on the first input voltage, the first internal power signal having a first internal current and a first internal voltage that is greater than the second input voltage by an offset voltage and a current damper can be configured to clamp the first internal power signal based on a limited current amount and configured to generate a second internal power signal having a second internal voltage and a second internal current. A switch circuit can be configured to output one of the second internal power signal and a sum of the second input power signal and the second internal power signal as an output power signal, based on a difference between the first internal voltage and the second internal voltage. 
         [0007]    Some example embodiments are directed to provide a power circuit capable of generating sufficient power signal by changing a route through which a power is supplied based on amount of load current. 
         [0008]    According to some example embodiments, a power circuit includes a first power signal generator, a second power signal generator, a regulator, a damper and a switch circuit. The first power signal generator generates a first input power signal having a first input voltage. The second power signal generator generates a second input power signal having a second input voltage whose level is smaller than a level of the first input voltage. The regulator generates a first internal power signal based on the first input voltage and the first internal power signal has a first internal voltage greater than the second input voltage by an offset voltage and a first internal current. The damper clamps the first internal power signal based on a limited current amount and generates a second internal power signal having a second internal voltage and a second internal current. The switch circuit outputs one of the second internal power signal and a sum of the second input power signal and the second internal power signal as an output power signal, based on a difference between the second internal voltage and the second input voltage. 
         [0009]    In example embodiments, when the level of the second input voltage is smaller than a level of the second internal voltage, the switch circuit may output the second internal power signal as the output power signal. When the level of the second input voltage is equal to or greater than the level of the second internal voltage, the switch circuit may output the sum of the second input power signal and the second internal power signal as the output power signal. 
         [0010]    In example embodiments, when the level of the second input voltage is smaller than a level of a sum of the second internal voltage and a threshold voltage, the switch circuit may output the second internal power signal as the output power signal. When the level of the second input voltage is equal to or greater than the level of the sum of the second internal voltage and the threshold voltage, the switch circuit may output sum of the second input power signal and the second internal power signal as the output power signal. 
         [0011]    In example embodiments, the limited current amount is adjusted by a limited current adjusting signal. 
         [0012]    In example embodiments, when a magnitude of the first internal current is smaller than the limited current amount, the damper may generate the second internal current whose magnitude is same as the magnitude of the first internal current and the second internal voltage whose level is same as the level of the first internal voltage. When the magnitude of the first internal current is equal to or greater than the limited current amount, the damper may generate the second internal current whose magnitude is same as the limited current amount and the second internal voltage whose level is smaller than the level of the first internal voltage. 
         [0013]    When the magnitude of the first internal current may be equal to or greater than the limited current amount, the level of the second internal voltage may decrease as the magnitude of the first internal current increases. 
         [0014]    In example embodiments, the regulator may include an operational amplifier, a power transistor and first through fourth resistors. The first resistor may have a first terminal receiving the second input voltage and a second terminal connected to a first node. The second resistor may have a first terminal connected to the first node and a second terminal connected to a ground voltage. The operational amplifier may have a first input terminal connected to the first node, a second input terminal connected to a second node and an output terminal connected to a third node. The power transistor may have a source connected to the first input voltage, a gate connected to the third node and a drain connected to the third resistor. The third resistor may have a first terminal connected to the power transistor and a second terminal connected to the second node. The fourth resistor may have a first terminal connected to the second node and a second terminal connected to the ground voltage. The first internal voltage may be a voltage of the second node and the first internal current may be output from the second node. 
         [0015]    In example embodiments, the damper may include a first p-channel metal-oxide semiconductor (PMOS) transistor, a second PMOS transistor, a sensing resistor, a protection resistor and a variable resistor. The first internal voltage may be a voltage of a first node and the first internal current may be input to the first node. The first PMOS transistor may have a source connected to the first node, a gate connected to a second node and a drain connected to a third node. The sensing resistor may have a first terminal connected to the first node and a second terminal connected to a fourth node. The protection resistor may have a first terminal connected to the second node and a second terminal connected to the fourth node. The variable resistor may have a first terminal connected to the third node and a second terminal connected to a ground voltage. The second PMOS transistor may have a source connected to the fourth node, a gate connected to the third node and a drain connected to a fifth node. The second internal voltage may be a voltage of the fifth node and the second internal current is output from the fifth node. 
         [0016]    A resistance of the variable resistor may be varied by a limited current adjusting signal. 
         [0017]    The damper may further include a resistance controller. The resistance controller may store a limited current adjusting signal and may adjust a resistance of the variable resistor based on the limited current adjusting signal. 
         [0018]    In example embodiments, the switch circuit may include a diode. The diode may have a cathode connected to a first node and an anode connected to a second node. The second internal voltage may be a voltage of the second node and the second internal current may be input to the second node. The second input voltage may be a voltage of the first node and a second input current of the second input power signal may be input to the first node. An output voltage of the output power signal may be a voltage of the second node and an output current of the output power signal may be output from the second node. 
         [0019]    The switch circuit may include an operational amplifier and an adjusting transistor. The operational amplifier may have a first input terminal connected to a first node, a second input terminal connected to a second node and an output terminal connected to a third node. The adjusting transistor may have a drain connected to the second node, a gate connected to the third node and a source connected to the first node. The second internal voltage may be a voltage of the second node and the second internal current may be input to the second node. The second input voltage may be a voltage of the first node and a second input current of the second input power signal may be input to the first node. An output voltage of the output power signal may be a voltage of the second node and an output current of the output power signal may be output from the second node. 
         [0020]    According to some example embodiments, a power circuit includes a first power signal generator, a second power signal generator, a regulator, a damper and a switch circuit. The first power signal generator generates a first input power signal having a first input voltage. The second power signal generator generates a second input power signal having a second input voltage whose level is smaller than a level of the first input voltage. The regulator generates a first internal power signal based on the first input voltage and the first internal power signal has a first internal voltage greater than the second input voltage by an offset voltage and a first internal current. The damper clamps the first internal power signal based on a limited current amount and generates a second internal power signal having a second internal voltage and a second internal current. The switch circuit outputs one of the second internal power signal and a sum of the second input power signal and the second internal power signal as an output power signal, based on a difference between the first internal voltage and the second internal voltage. 
         [0021]    In example embodiments, when the level of the first internal voltage is smaller than a level of the second internal voltage, the switch circuit may output the second internal power signal as the output power signal. When the level of the first internal voltage is equal to or greater than the level of the second internal voltage, the switch circuit may output the sum of the second input power signal and the second internal power signal as the output power signal. 
         [0022]    In example embodiments, when the level of the first internal voltage is smaller than a level of a sum of the second internal voltage and a threshold voltage, the switch circuit may output the second internal power signal as the output power signal. When the level of the first internal voltage is equal to or greater than the level of the sum of the second internal voltage and the threshold voltage, the switch circuit may output sum of the second input power signal and the second internal power signal as the output power signal. 
         [0023]    Accordingly, the power circuit may generate sufficient power signal by changing a route through which a power is supplied from a plurality of power sources, based on amount of load current while preventing heating phenomenon due to overcurrent. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]    Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings. 
           [0025]      FIG. 1  is a block diagram illustrating a power circuit according to example embodiments. 
           [0026]      FIGS. 2A and 2B  are diagrams illustrating power systems using a plurality of powers. 
           [0027]      FIG. 3  is a block diagram illustrating a power system including the power circuit of  FIG. 1  according to example embodiments. 
           [0028]      FIG. 4  is a circuit diagram illustrating the regulator in the power circuit of  FIG. 1  according to example embodiments. 
           [0029]      FIGS. 5A and 5B  are circuit diagrams illustrating examples of the clamper in the power circuit according to example embodiments. 
           [0030]      FIG. 6  is a circuit diagram illustrating an example of the switch circuit in the power circuit of  FIG. 1  according to example embodiments. 
           [0031]      FIG. 7  is a timing diagram illustrating an operation of the power circuit of  FIG. 1 , which includes the switch circuit of  FIG. 6 . 
           [0032]      FIG. 8  is a circuit diagram illustrating an example of the switch circuit in the power circuit of  FIG. 1  according to example embodiments. 
           [0033]      FIG. 9  is a timing diagram illustrating an operation of the power circuit of  FIG. 1 , which includes the switch circuit of  FIG. 8 . 
           [0034]      FIG. 10  is a block diagram illustrating a power circuit according to example embodiments. 
           [0035]      FIG. 11  is a block diagram illustrating a power circuit according to example embodiments. 
           [0036]      FIG. 12  is a block diagram illustrating a power circuit according to example embodiments. 
           [0037]      FIG. 13  is a circuit diagram illustrating an example of the switch circuit in the power circuit of  FIG. 12  according to example embodiments. 
           [0038]      FIG. 14  is a circuit diagram illustrating an example of the switch circuit in the power circuit of  FIG. 12  according to example embodiments. 
           [0039]      FIG. 15  is a block diagram illustrating a power circuit according to example embodiments. 
           [0040]      FIG. 16  is a block diagram illustrating a power circuit according to example embodiments. 
           [0041]      FIG. 17  is a block diagram illustrating a solid state drive (SSD) system according to example embodiments. 
           [0042]      FIG. 18  is a block diagram illustrating a mobile system according to example embodiments. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0043]    Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like numerals refer to like elements throughout. 
         [0044]    It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
         [0045]    It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). 
         [0046]    The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0047]    Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. 
         [0048]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0049]      FIG. 1  is a block diagram illustrating a power circuit according to example embodiments. 
         [0050]    Referring to  FIG. 1 , a power circuit  100  includes a first power signal generator  140 , a second power signal generator  150 , a regulator  110 , a current damper  120  and a switch circuit  130 . It will be understood that each of the elements shown in  FIG. 1  can be separate circuits or integrated with one another or in any combination with one another. 
         [0051]    The first power signal generator  140  generates a first input power signal PSIGIN 1  having a first input voltage PSIGIN 1 _V. The second power signal generator  150  generates a second input power signal PSIGIN 2  having a second input voltage PSIGIN 2 _V whose level is less than a level of the first input voltage PSIGIN 1 _V. 
         [0052]    The regulator  110  generates a first internal power signal PSIG 1  based on the first input voltage. The first internal power signal PSIG 1  may have a first internal current PSIG 1 _I and a first internal voltage PSIG 1 _V whose level is greater than the second input voltage PSIGIN 2 _V by an offset voltage. The current damper  120  clamps the first internal power signal PSIG 1  based on a limited current amount and generates a second internal power signal PSIG 2  having a second internal voltage PSIG 2 _V and a second internal current PSIG 2 _I. The switch circuit  130  outputs the second internal power signal PSIG 2  or a sum of the second input power signal PSIGIN 2  and the second internal power signal PSIG 2  as an output power signal PSIGOUT, based on a difference between the second internal voltage PSIG 2 _V and the second input voltage PSIGIN 2 _V. 
         [0053]    The current damper  120  clamps based on the limited current amount which can be adjusted using a limited current adjusting signal SIGLIMIT. In some embodiments, when a magnitude of the first internal current PSIG 1 _I is less than the limited current amount, the current damper  120  may generate the second internal current PSIG 2 _I to be the same as the first internal current PSIG 1 _I and the second internal voltage PSIG 2 _V to have the same level as the first internal voltage PSIG 1 _V. When, however, the magnitude of the first internal current PSIG 1 _I is equal to or greater than the limited current amount, the current damper  120  may generate the second internal current PSIG 2 _I to have the same magnitude as that specified by the limited current amount and the second internal voltage PSIG 2 _V to have a level that is not less than the level of the first internal voltage PSIG 1 _V. The current damper  120  is also described with reference to  FIGS. 5A and 5B . 
         [0054]    In some embodiments, when the level of the second input voltage PSIGIN 2 _V is less than the level of the second internal voltage PSIG 2 _V, the switch circuit  130  may output the second internal power signal PSIG 2  as the output power signal PSIGOUT. When, however, the level of the second input voltage PSIGIN 2 _V is equal to or greater than the level of the second internal voltage PSIG 2 _V, the switch circuit  130  may output the sum of the second input power signal PSIGIN 2  and the second internal power signal PSIG 2  as the output power signal PSIGOUT. 
         [0055]    In some embodiments, when the level of the second input voltage PSIGIN 2 _V is less than the level of the sum of the second internal voltage PSIG 2 _V and a threshold voltage, the switch circuit  130  may output the second internal power signal PSIG 2  as the output power signal PSIGOUT. When, however, the level of the second input voltage PSIGIN 2 _V is equal to or greater than the level of the sum of the second internal voltage PSIG 2 _V and the threshold voltage, the switch circuit  130  may output sum of the second input power signal PSIGIN 2  and the second internal power signal PSIG 2  as the output power signal PSIGOUT. 
         [0056]    In some embodiments, the first power signal generator  140  and the second power signal generator  150  may not be included in the power circuit  100 . 
         [0057]      FIGS. 2A and 2B  are diagrams illustrating power systems using a plurality of powers. 
         [0058]      FIG. 2A  illustrates that a memory system MD  1  is designed to include a first power domain PD 11  and a second power domain PD 12 . A controller CTRL 1  and a NAND flash memory device NAND  1  operate in the first power domain PD 11 . A volatile memory device DRAM 1  operates in the second power domain PD 12 . 
         [0059]    When a high voltage power source HVS 1  supplies a first power signal PS 11  to the first power domain PD 11  sufficiently and a low voltage power source LVS 1  supplies a second power signal PS 12  to the second power domain PD 12  sufficiently, the memory system MD 1  operates normally. However, when either the high voltage power source HVS 1  or the low voltage power source LVS 1  does not supply a sufficient power signal, the memory system MD  1  may not operate normally. 
         [0060]    In a general personal computer, at least one of the high voltage power source HVS 1  and the low voltage power source LVS 1  are mounted on a main board and the memory system MD 1  is mounted on the main board. Since the memory system MD 1  draws power from the main board, the personal computer may not operate normally when the power from the high voltage power source HVS 1  or the low voltage power source LVS 1  is not sufficient. 
         [0061]      FIG. 2B  illustrates that a memory system MD 2  is designed to include one power domain PD 2 . A controller CTRL 2 , a NAND flash memory device NAND 2  and a volatile memory device DRAM 2  operate in the power domain PD 2 . 
         [0062]    When a high voltage power source HVS 2  supplies a first power signal PS 21  to the first power domain PD  11  sufficiently, the memory system MD 2  operates normally. However, when a fixed amount of power is assigned to the high voltage power source HVS 2  and the low voltage power source LVS 2 , and a constant amount of power is assigned to the low voltage power source LVS 2  that supplies a second power signal PS 22 , the memory system MD 2  may not operate normally if the high voltage power source HVS 2  outputs the first power signal PS 21  insufficiently. 
         [0063]      FIG. 3  is a block diagram illustrating a power system including the power circuit of  FIG. 1  according to example embodiments. 
         [0064]    Referring to  FIG. 3 , a power system  10  includes a high voltage power source HVS 3 , a low voltage power source LVS 3 , a power circuit PC and a memory system MD 3 . The power circuit PC may include the regulator  110 , the current damper  120  and the switch circuit  130  in  FIG. 1 . The memory system MD 3  is configured to have one power domain PD 3  and a controller CTRL 3 , a NAND flash memory device NAND 3  and a volatile memory device DRAM 3  each which operate in the power domain PD 3 . 
         [0065]    The power circuit PC can be configured to selectively sum a first power signal PS 31  generated by the high voltage power source HVS 3  and a second power signal PS 32  generated by the low voltage power source LVS 3  according to a power amount required by the memory system MD 3 , and configured to generate a third power signal PS 33  having a sufficient power and may provide the third power signal PS 33  to the power domain PD 3 . Therefore, the memory system MD 3  needs not to be modified in view of the powers provided by the high voltage power source HVS 3  and the low voltage power source LVS 3 . 
         [0066]      FIG. 4  is a circuit diagram illustrating the regulator  110  in the power circuit of  FIG. 1  according to example embodiments. 
         [0067]    Referring to  FIG. 4 , the regulator  110  may include an operational amplifier  111 , a power transistor PT and first through fourth resistors RD 1 , RD 2 , RD 3  and RD 4 . 
         [0068]    The first resistor RD 1  has a first terminal connected to the second input voltage PSIGIN 2 _V and a second terminal connected to a first node N 11 . The second resistor RD 2  has a first terminal connected to the first node N 11  and a second terminal connected to a ground voltage GND. The operational amplifier  111  has a first (positive) input terminal connected to the first node N 11 , a second (negative) input terminal connected to a second node N 12  and an output terminal connected to a third node N 13 . The power transistor PT has a source connected to the first input voltage PSIGIN 1 _V, a gate connected to the third node N 13  and a drain connected to the third resistor RD 3 . The third resistor RD 3  has a first terminal connected to the power transistor PT and a second terminal connected to the second node N 12 . The fourth resistor RD 4  has a first terminal connected to the second node N 12  and a second terminal connected to the ground voltage GND. The first internal voltage PSIG 1 _V is a voltage of the second node N 12 , and the first internal current PSIG 1 _I is output from the second node N 12 . 
         [0069]    The level of first internal voltage PSIG 1 _V is adjusted to be greater than the level of the second input voltage PSIGIN 2 _V by the offset voltage by adjusting resistances of the first through fourth resistors RD 1 , RD 2 , RD 3  and RD 4 . The offset voltage may be in a range of 0 through few volts. In some embodiments, the offset voltage may be in a range of 0.2 through 0.3 volts. 
         [0070]      FIGS. 5A and 5B  are circuit diagrams illustrating examples of the current damper in the power circuit according to example embodiments. 
         [0071]    Referring to  FIG. 5A , a current damper  120 A is connected to a load stage  170 A. The load stage  170 A includes a load resistor RLOADA representing all loads connected to the switch circuit  130  and to a latter part connected to the switch circuit  130 . 
         [0072]    The current damper  120 A includes a first p-channel metal-oxide semiconductor (PMOS) transistor PT 11 A, a second PMOS transistor PT 12 A, a sensing resistor RSENSEA, a protection resistor RPROTECTA and a variable resistor R 1 A. 
         [0073]    The first internal voltage PSIG 1 _V is a voltage of a first node N 21 A and the first internal current PSIG 1 _I is input to the first node N 21 A. The first PMOS transistor PT 11 A has a source connected to the first node N 21 A, a gate connected to a second node N 22 A and a drain connected to a third node N 23 A. The sensing resistor RSENSEA has a first terminal connected to the first node N 21 A and a second terminal connected to a fourth node N 24 A. The protection resistor RPROTECTA has a first terminal connected to the second node N 22 A and a second terminal connected to the fourth node N 24 A. The variable resistor R 1 A has a first terminal connected to the third node N 23 A and a second terminal connected to the ground voltage GND. The second PMOS transistor PT 12 A has a source connected to the fourth node N 24 A, a gate connected to the third node N 23 A and a drain connected to a fifth node N 25 A. The second internal voltage PSIG 2 _V is a voltage of the fifth node N 25 A and the second internal current PSIG 2 _I is output from the fifth node N 25 A through the load resister RLOADA. 
         [0074]    A resistance of the variable resistor R 1 A may be varied by the limited current adjusting signal SIGLIMIT. 
         [0075]    The second PMOS transistor PT 12 A may be turned-on or off in response to a voltage at the third node N 23 A. When the second PMOS transistor PT 12 A may be turned-on, the current damper  120 A outputs the first internal power signal PSIG 1  as the second internal power signal PSIG 2 . Therefore, the second internal voltage PSIG 2 _V is the same as the first internal voltage PSIG 1 _V and the second internal current PSIG 2 _I is the same as the first internal current PSIG 1 _I. 
         [0076]    When a magnitude of a current flowing through the sensing resistor RSENSEA exceeds a limited current amount, the first PMOS transistor PT 11 A is turned on, the second PMOS transistor PT 12 A is turned off, the second internal current PSIG 2 _I is limited to the limited current amount and the level of the second internal voltage PSIG 2 _V decreases. As the level of the second internal voltage PSIG 2 _V decreases, the power consumed in the current damper  120 A increases and a heat generated in the current damper  120 A increases. Therefore, in some embodiments, the magnitude of the first internal current PSIG 1 _I is maintained below the limited current amount. The protection resistor RPROTECTA protects the first PMOS transistor PT 11 A when a resistance of the load resistor RLOADA is relatively small. 
         [0077]    Referring to  FIG. 5B , a current damper  120 B is connected to a load stage  170 B. The load stage  170 B includes a load resistor RLOADB representing all loads connected to the switch circuit  130  and to a latter part of the switch circuit  130 . 
         [0078]    The current damper  120 B includes a first PMOS transistor PT 11 B, a second PMOS transistor PT 12 B, a sensing resistor RSENSEB, a protection resistor RPROTECTB, a variable resistor R 1 B and a resistance controller RCTRL. 
         [0079]    The first internal voltage PSIG 1 _V is a voltage of a first node N 21 B and the first internal current PSIG 1 _I is input to the first node N 21 B. The first PMOS transistor PT 11   b  has a source connected to the first node N 21 B, a gate connected to a second node N 22 B and a drain connected to a third node N 23 B. The sensing resistor RSENSEB has a first terminal connected to the first node N 21 B and a second terminal connected to a fourth node N 24 B. The protection resistor RPROTECTB has a first terminal connected to the second node N 22 B and a second terminal connected to the fourth node N 24 B. The variable resistor R 1 B has a first terminal connected to the third node N 23 B and a second terminal connected to the ground voltage GND. The second PMOS transistor PT 12 B has a source connected to the fourth node N 24 B, a gate connected to the third node N 23 B and a drain connected to a fifth node N 25 B. The second internal voltage PSIG 2 _V is a voltage at the fifth node N 25 B and the second internal current PSIG 2 _I is output from the fifth node N 25 B. The resistance controller RCTRL stores the limited current adjusting signal SIGLIMIT and adjusts a resistance of the variable resistance R 1 B based on the limited current adjusting signal SIGLIMIT. 
         [0080]    The second PMOS transistor PT 12 B may be turned-on or off in response to a voltage of the third node N 23 B. When the second PMOS transistor PT 12 B may be turned-on, the current damper  120 B outputs the first internal power signal PSIG 1  as the second internal power signal PSIG 2 . Therefore, the second internal voltage PSIG 2 _V is the same as the first internal voltage PSIG 1 _V and the second internal current PSIG 2 _V is the same as the first internal current PSIG 1 _I. When a magnitude of a current flowing through the sensing resistor RSENSEB exceeds a limited current amount, the first PMOS transistor PT 11 B is turned on, the second PMOS transistor PT 12 B is turned off, the second internal current PSIG 2 _I is limited to the limited current amount and the level of the second internal voltage PSIG 2 _V decreases. As the level of the second internal voltage PSIG 2 _V decreases, the power consumed in the current damper  120 B increases and a heat generated in the current damper  12 B increases. Therefore, in some embodiments, the magnitude of the first internal current PSIG 1 _I is maintained below the limited current amount. The protection resistor RPROTECTB protects the first PMOS transistor PT 11 B when a resistance of the load resistor RLOADB is relatively small. 
         [0081]      FIG. 6  is a circuit diagram illustrating an example of the switch circuit in the power circuit of  FIG. 1  according to example embodiments. 
         [0082]    Referring to  FIG. 6 , a switch circuit  130 A includes a diode  131 A. The diode  131 A has an anode connected to a first node N 31  and a cathode connected to a second node N 32 . The second internal voltage PSIG 2 _V is a voltage at the second node N 32  and the second internal current PSIG 2 _I is input to the second node N 32 . The second input voltage PSIGIN 2 _V is a voltage at the first node N 31  and a second input current PSIGIN 2 _I of the second input power signal PSIGIN 2  is input to the first node N 31 . An output voltage PSIGOUT_V of the output power signal PSIGOUT is a voltage at the second node N 32  and an output current PSIGOUT_I of the output power signal PSIGOUT is output from the second node N 32 . 
         [0083]    When the threshold voltage is a threshold voltage of the diode  131 A, the switch circuit  130 A operates as follows. When the level of the second input voltage PSIGIN 2 _V is less than a level of the sum of the second internal voltage PSIG 2 _V and the threshold voltage, the switch circuit  130 A outputs the second internal power signal PSIG 2  as the output power signal PSIGOUT. When the level of the second input voltage PSIGIN 2 _V is equal to or greater than the level of the sum of the second internal voltage PSIG 2 _V and the threshold voltage as the magnitude of the first internal current PSIG 1 _I increases and the magnitude of the second internal voltage PSIG 2 _V decreases, the switch circuit  130 A outputs the sum of the second input power signal PSIGIN 2  and the second internal power signal PSIG 2  as the output power signal PSIGOUT. When an amount of current required by the load stage exceeds the limited current amount, the switch circuit  130 A generates the output current PSIGOUT_I by fixing the magnitude of the first internal current PSIG 1 _I to the limited current amount and summing the second input current PSIGIN 2 _I and the fixed first internal current PSIG 1 _I. 
         [0084]      FIG. 7  is a timing diagram illustrating an operation of the power circuit of  FIG. 1 , which includes the switch circuit of  FIG. 6 . 
         [0085]    In  FIG. 7 , it is assumed that the first input voltage PSIGIN 1 _V corresponds to 12 [V], the first input voltage PSIGIN 2 _V corresponds to 5 [V], the offset voltage corresponds to 0.2 [V] and the threshold voltage of the diode  131 A corresponds to 0.7[V]. 
         [0086]    The switch circuit  130 A outputs the second internal power signal PSIG 2  as the output power signal PSIGOUT until a time T 11  when the magnitude of the second internal current PSIG 2 _I reaches the limited current amount LIMIT_CUR. Since the second internal current PSIG 2 _I reaches the limited current amount LIMIT_CUR at the time T 11 , the level of the second internal voltage PSIG 2 _V decreases until a time T 12 . The diode  131 A is turned-on from the time T 12  to a time T 13 , and the switch circuit  130 A outputs the sum of the second input power signal PSIGIN 2  and the second internal power signal PSIG 2  as the output power signal PSIGOUT which having the output current PSIGOUT_I corresponding to the sum of the limited current amount LIMIT_CUR and the second input current A. 
         [0087]      FIG. 8  is a circuit diagram illustrating an example of the switch circuit in the power circuit of  FIG. 1  according to example embodiments. 
         [0088]    Referring to  FIG. 8 , a switch circuit  130 B includes an operational amplifier  131 B and an adjusting transistor CT 1 . The operational amplifier  131 B has a first (positive) input terminal connected to a first node N 41 , a second (negative) input terminal connected to a second node N 42  and an output terminal connected to a third node N 43 . The adjusting transistor CT 1  has a drain connected to the second node N 42 , a gate connected to the third node N 43  and a source connected to the first node N 41 . The second internal voltage PSIG 2 _V is a voltage at the second node N 42  and the second internal current PSIG 2 _I is input to the second node N 42 . The second input voltage PSIGIN 2 _V is a voltage at the first node N 41  and a second input current PSIGIN 2 _I of the second input power signal PSIGIN 2  is input to the first node N 41 . An output voltage PSIGOUT_V of the output power signal PSIGOUT is a voltage at the second node N 42  and an output current PSIGOUT_I of the output power signal PSIGOUT is output from the second node N 42 . 
         [0089]    When the level of the second input voltage PSIGIN 2 _V is less than the level of the second internal voltage PSIG 2 _V, the switch circuit  130 B outputs the second internal power signal PSIG 2  as the output power signal PSIGOUT. When the second input voltage PSIGIN 2 _V is equal to or greater than the level of the second internal voltage PSIG 2 _V as the level of the second input voltage PSIGIN 2 _V, the adjusting transistor CT 1  is turned-on and the switch circuit  130 B outputs the sum of the second input power signal PSIGIN 2  and the second internal power signal PSIG 2  as the output power signal PSIGOUT. When an amount of current required by the load stage exceeds the limited current amount, the switch circuit  130 B generates the output current PSIGOUT_I by fixing the magnitude of the first internal current PSIG 1 _I to the limited current amount and summing the second input current PSIGIN 2 _I and the fixed first internal current PSIG 1 _I. 
         [0090]      FIG. 9  is a timing diagram illustrating an operation of the power circuit of  FIG. 1 , which includes the switch circuit of  FIG. 8 . 
         [0091]    In  FIG. 9 , it is assumed that the first input voltage PSIGIN 1 _V corresponds to 12 [V], the first input voltage PSIGIN 1 _V corresponds to 5 [V] and the offset voltage corresponds to 0.2 [V]. 
         [0092]    The switch circuit  130 B outputs the second internal power signal PSIG 2  as the output power signal PSIGOUT until a time T 21  when the magnitude of the second internal current PSIG 2 _I reaches the limited current amount LIMIT_CUR. Since the second internal current PSIG 2 _I reaches the limited current amount LIMIT_CUR at the time T 21 , the level of the second internal voltage PSIG 2 _V decreases until a time T 22 . The adjusting transistor  131 B is turned-on from the time T 22  to a time T 23 , and the switch circuit  130 B outputs the sum of the second input power signal PSIGIN 2  and the second internal power signal PSIG 2  as the output power signal PSIGOUT which having the output current PSIGOUT_I corresponding to the sum of the limited current amount LIMIT_CUR and the second input current A. 
         [0093]      FIG. 10  is a block diagram illustrating a power circuit according to example embodiments. 
         [0094]    Referring to  FIG. 10 , a power circuit  200  includes a first power signal generator  250 , a second power signal generator  260 , a regulator  210 , a first current damper  220 , a second current damper  240  and a switch circuit  230 . 
         [0095]    The first power signal generator  250  generates a first input power signal PSIGIN 1  having a first input voltage PSIGIN 1 _V. The second power signal generator  260  generates a second input power signal PSIGIN 2  having a second input voltage PSIGIN 2 _V whose level is less than a level of the first input voltage PSIGIN 1 _V. 
         [0096]    The regulator  210  generates a first internal power signal PSIG 1  based on the first input voltage PSIGIN 1 _V. The first internal power signal PSIG 1  may have a first internal current PSIG 1 _I and a first internal voltage PSIG 1 _V whose level is greater than the second input voltage PSIGIN 2 _V by an offset voltage. The first current damper  220  clamps the first internal power signal PSIG 1  based on a first limited current amount and generates a second internal power signal PSIG 2  having a second internal voltage PSIG 2 _V and a second internal current PSIG 2 _I. The second current clamper  240  clamps the second input power signal PSIGIN 2  based on a second limited current amount and generates a third internal power signal PSIG 3  having a third internal voltage PSIG 3 _V and a third internal current PSIG 3 _I. The switch circuit  230  outputs one of the second internal power signal PSIG 2  and a sum of the second internal power signal PSIG 2  and the third internal power signal PSIG 3  as an output power signal PSIGOUT, based on a difference between the second internal voltage PSIG 2 _V and the third internal voltage PSIG 3 _V. 
         [0097]    The first limited current amount may be adjusted by a first limited current adjusting signal SIGLIMIT 1  and the second limited current amount may be adjusted by a second limited current adjusting signal SIGLIMIT 2 . The operation of the power circuit  200  may be well understood based on the description with reference to  FIGS. 1 through 9 , for example. 
         [0098]      FIG. 11  is a block diagram illustrating a power circuit according to example embodiments. 
         [0099]    Referring to  FIG. 11 , a power circuit  300  includes a first power signal generator  360 , a second power signal generator  370 , a third power signal generator  380 , a first regulator  310 , a second regulator  330 , a first current damper  320 , a second current damper  340  and a switch circuit  350 . 
         [0100]    The first power signal generator  360  generates a first input power signal PSIGIN 1  having a first input voltage PSIGIN 1 _V. The second power signal generator  370  generates a second input power signal PSIGIN 2  having a second input voltage PSIGIN 2 _V whose level is less than a level of the first input voltage PSIGIN 1 _V. The third power signal generator  380  generates a third input power signal PSIGIN 3  having a third input voltage PSIGIN 3 _V whose level is less than a level of the second input voltage PSIGIN 2 _V. 
         [0101]    The first regulator  310  generates a first internal power signal PSIG 1  based on the first input voltage PSIGIN 1 _V. The first internal power signal PSIG 1  may have a first internal current PSIG 1 _I and a first internal voltage PSIG 1 _V whose level is greater than the third input voltage PSIGIN 3 _V by a first offset voltage. The second regulator  320  generates a second internal power signal PSIG 2  based on the second input voltage PSIGIN 2 _V. The second internal power signal PSIG 2  may have a second internal current PSIG 2 _I and a second internal voltage PSIG 2 _V whose level is greater than the third input voltage PSIGIN 3 _V by a second offset voltage. 
         [0102]    The first current damper  320  clamps the first internal power signal PSIG 1  based on a first limited current amount and generates a third internal power signal PSIG 3  having a third internal voltage PSIG 3  V and a third internal current PSIG 3 _I. The second current damper  340  clamps the second internal power signal PSIG 2  based on a second limited current amount and generates a fourth internal power signal PSIG 4  having a fourth internal voltage PSIG 4 _V and a fourth internal current PSIG 4 _I. The switch circuit  350  outputs the third internal power signal PSIG 3 , a sum of the third internal power signal PSIG 3  and the fourth internal power signal PSIG 4  or a sum of the third internal power signal PSIG 3 , the fourth internal power signal PSIG 4  and the third input power signal PSIGIN 3  as the output power signal PSIGOUT, based on a difference between the third internal voltage PSIG 3 _V, the fourth internal voltage PSIG 4 _V and the third input voltage PSIGIN 3 _V. 
         [0103]    In example embodiments, a level of the first offset voltage is greater than a level of the second offset voltage. 
         [0104]    In example embodiments, when the level of the third internal voltage PSIG 3 _V is greater than the level of the fourth internal voltage PSIG 4 _V, the switch circuit  350  outputs the third internal power signal PSIG 3  as the output power signal PSIGOUT. When the level of the third internal voltage PSIG 3 _V is equal to the level of the fourth internal voltage PSIG 4 _V and the level of the third internal voltage PSIG 3 _V is greater than the level of the third input voltage PSIGIN 3 _V, the switch circuit  350  outputs the sum of the third internal power signal PSIG 3  and the fourth internal power signal PSIG 4  as the output power signal PSIGOUT. When the levels of the third internal voltage PSIG 3  y, the fourth internal voltage PSIG 4 _V and the third input voltage PSIGIN 3 _V are the same, the switch circuit  350  outputs the sum of the third internal power signal PSIG 3 , the fourth internal power signal PSIG 4  and the third input power signal PSIGIN 3  as the output power signal PSIGOUT. 
         [0105]    The first limited current amount may be adjusted by a first limited current adjusting signal SIGLIMIT 1  and the second limited current amount may be adjusted by a second limited current adjusting signal SIGLIMIT 2 . The operation of the power circuit  300  may be well understood based on the description with reference to  FIGS. 1 through 10 , for example. 
         [0106]      FIG. 12  is a block diagram illustrating a power circuit according to example embodiments. 
         [0107]    Referring to  FIG. 12 , a power circuit  400  includes a first power signal generator  440 , a second power signal generator  450 , a regulator  410 , a current damper  420  and a switch circuit  430 . 
         [0108]    The first power signal generator  440  generates a first input power signal PSIGIN 1  having a first input voltage PSIGIN 1 _V. The second power signal generator  450  generates a second input power signal PSIGIN 2  having a second input voltage PSIGIN 2 _V whose level is less than a level of the first input voltage PSIGIN 1 _V. 
         [0109]    The regulator  410  generates a first internal power signal PSIG 1  based on the first input voltage PSIGIN 1 _V. The first internal power signal PSIG 1  may have a first internal current PSIG 1 _I and a first internal voltage PSIG 1 _V whose level is greater than the second input voltage PSIGIN 2 _V by an offset voltage. The current damper  420  clamps second input power signal PSIGIN 2  based on a limited current amount and generates a second internal power signal PSIG 2  having a second internal voltage PSIG 2 _V and a second internal current PSIG 2 _I. The switch circuit  430  outputs one of the second internal power signal PSIG 2  and a sum of the first internal power signal PSIG 1  and the second internal power signal PSIG 2  as an output power signal PSIGOUT, based on a difference between the first internal voltage PSIG 1 _V and the second internal voltage PSIG 2 _V. 
         [0110]    In example embodiments, when the level of the first internal voltage PSIG 1 _V is less than the level of the second internal voltage PSIG 2 _V, the switch circuit  430  outputs the second internal power signal PSIG 2  as the output power signal PSIGOUT. When the level of the first internal voltage PSIG 1 _V is equal to or greater than the level of the second internal voltage PSIG 2 _V, the switch circuit  430  outputs the sum of the first internal power signal PSIG 1  and the second internal power signal PSIG 2  as the output power signal PSIGOUT. 
         [0111]    In some embodiments, when the level of the first internal voltage PSIG 1 _V is less than a level of a sum of the second internal voltage PSIG 2 _V and a threshold voltage, the switch circuit  400  outputs the second internal power signal PSIG 2  as the output power signal PSIGOUT. When the level of the first internal voltage PSIG 1 _V is equal to or greater than the level of the sum of the second internal voltage PSIG 2 _V and the threshold voltage, the switch circuit  400  outputs the sum of the first internal power signal PSIG 1  and the second internal power signal PSIG 2  as the output power signal PSIGOUT. 
         [0112]    The power circuit  100  of  FIG. 1  uses the first input power signal PSIGIN 1  preferentially to the second input power signal PSIGIN 2  whereas the power circuit  400  of  FIG. 12  uses the second input power signal PSIGIN 2  preferentially to the first input power signal PSIGIN 1 . 
         [0113]      FIG. 13  is a circuit diagram illustrating an example of the switch circuit in the power circuit of  FIG. 12  according to example embodiments. 
         [0114]    Referring to  FIG. 13 , a switch circuit  430 A includes a diode  431 A. The diode  431 A has an anode connected to a first node N 51  and a cathode connected to a second node N 52 . The second internal voltage PSIG 2 _V is a voltage of the second node N 52  and the second internal current PSIG 2 _I is input to the second node N 52 . The first input voltage PSIGIN 1 _V is a voltage at the first node N 51  and a first input current PSIGIN 1 _I of the first input power signal PSIGIN 1  is input to the first node N 51 . An output voltage PSIGOUT_V of the output power signal PSIGOUT is a voltage of the second node N 52  and an output current PSIGOUT_I of the output power signal PSIGOUT is output from the second node N 52 . 
         [0115]    When the threshold voltage is a threshold voltage of the diode  431 A, the switch circuit  430 A operates as follows. When the level of the first input voltage PSIGN 1 _V is less than a level of the sum of the second internal voltage PSIG 2 _V and the threshold voltage, the diode  431 A is turned off and the switch circuit  430 A outputs the second internal power signal PSIG 2  as the output power signal PSIGOUT. When the level of the first input voltage PSIGIN 1 _V is equal to or greater than the level of the sum of the second internal voltage PSIG 2 _V and the threshold voltage, as the magnitude of the second internal current PSIG 2 _I increases and the magnitude of the second internal voltage PSIG 2 _V decreases, the switch circuit  430 A outputs the sum of the first internal power signal PSIG 1  and the second internal power signal PSIG 2  as the output power signal PSIGOUT. 
         [0116]      FIG. 14  is a circuit diagram illustrating an example of the switch circuit in the power circuit of  FIG. 12  according to example embodiments. 
         [0117]    Referring to  FIG. 14 , a switch circuit  430 B includes an operational amplifier  431 B and an adjusting transistor CT 2 . The operational amplifier  431 B has a first (negative) input terminal connected to a first node N 61 , a second (positive) input terminal connected to a second node N 62  and an output terminal connected to a third node N 63 . The adjusting transistor CT 2  has a drain connected to the first node N 61 , a gate connected to the third node N 63  and a source connected to the second node N 62 . The second internal voltage PSIG 2 _V is a voltage at of the second node N 62  and the second internal current PSIG 2 _I is input to the second node N 62 . The first internal voltage PSIG 1 _V is a voltage at the first node N 61  and the first internal current PSIG 1 _I is input to the first node N 61 . An output voltage PSIGOUT_V of the output power signal PSIGOUT is a voltage at the second node N 62  and an output current PSIGOUT_I of the output power signal PSIGOUT is output from the second node N 62 . 
         [0118]    When the level of the first internal voltage PSIG 1 _V is less than the level of the second internal voltage PSIG 2 _V, the switch circuit  430 B outputs the second internal power signal PSIG 2  as the output power signal PSIGOUT. When the first internal voltage PSIG 1 _V is equal to or greater than the level of the second internal voltage PSIG 2 _V, the adjusting transistor CT 2  is turned-on and the switch circuit  440 B outputs the sum of the first internal power signal PSIG 1  and the second internal power signal PSIG 2  as the output power signal PSIGOUT. 
         [0119]      FIG. 15  is a block diagram illustrating a power circuit according to example embodiments. 
         [0120]    Referring to  FIG. 15 , a power circuit  500  includes a first power signal generator  550 , a second power signal generator  560 , a regulator  510 , a first current damper  520 , a second current damper  530  and a switch circuit  540 . 
         [0121]    The first power signal generator  550  generates a first input power signal PSIGIN 1  having a first input voltage PSIGIN 1 _V. The second power signal generator  560  generates a second input power signal PSIGIN 2  having a second input voltage PSIGIN 2 _V whose level is less than a level of the first input voltage PSIGIN 1 _V. 
         [0122]    The regulator  510  generates a first internal power signal SPIG 1  based on the first input voltage PSIGIN 1 _V. The first internal power signal PSIG 1  may have a first internal current PSIG 1 _I and a first internal voltage PSIG 1 _V whose level is greater than the second input voltage PSIGIN 2 _V by an offset voltage. The first current damper  520  clamps the first internal power signal PSIG 1  based on a first limited current amount and generates a second internal power signal PSIG 2  having a second internal voltage PSIG 2 _V and a second internal current PSIG 2 _I. The second current damper  530  clamps the second input power signal PSIGIN 2  based on a second limited current amount and generates a third internal power signal PSIG 3  having a third internal voltage PSIG 3 _V and a third internal current PSIG 3 _I. The switch circuit  540  outputs one of the third internal power signal PSIG 3  and a sum of the second internal power signal PSIG 2  and the third internal power signal PSIG 3  as an output power signal PSIGOUT, based on a difference between the second internal voltage PSIG 2 _V and the third internal voltage PSIG 3 _V. 
         [0123]    The first limited current amount may be adjusted by a first limited current adjusting signal SIGLIMIT 1  and the second limited current amount may be adjusted by a second limited current adjusting signal SIGLIMIT 2 . The operation of the power circuit  500  may be understood based on the description with reference to  FIGS. 1 through 14 , for example. 
         [0124]      FIG. 16  is a block diagram illustrating a power circuit according to example embodiments. 
         [0125]    Referring to  FIG. 16 , a power circuit  600  includes a first power signal generator  660 , a second power signal generator  670 , a third power signal generator  680 , a first regulator  610 , a second regulator  620 , a first current damper  630 , a second current damper  640  and a switch circuit  650 . 
         [0126]    The first power signal generator  660  generates a first input power signal PSIGIN 1  having a first input voltage PSIGIN 1 _V. The second power signal generator  670  generates a second input power signal PSIGIN 2  having a second input voltage PSIGIN 2 _V whose level is less than a level of the first input voltage PSIGIN 1 _V. The third power signal generator  680  generates a third input power signal PSIGIN 3  having a third input voltage PSIGIN 3 _V whose level is less than a level of the second input voltage PSIGIN 2 _V. 
         [0127]    The first regulator  610  generates a first internal power signal PSIG 1  based on the first input voltage PSIGIN 1 _V. The first internal power signal PSIG 1  may have a first internal current PSIG 1 _I and a first internal voltage PSIG 1 _V whose level is greater than the third input voltage PSIGIN 3 _V by a first offset voltage. The second regulator  620  generates a second internal power signal PSIG 2  based on the second input voltage PSIGIN 2 _V. The second internal power signal PSIG 2  may have a second internal current PSIG 2 _I and a second internal voltage PSIG 2 _V whose level is greater than the third input voltage PSIGIN 3 _V by a second offset voltage. 
         [0128]    The first current damper  630  clamps the second internal power signal PSIG 2  based on a first limited current amount and generates a third internal power signal PSIG 3  having a third internal voltage PSIG 3 _V and a third internal current PSIG 3 _I. The second current damper  640  clamps the third input power signal PSIGIN 3  based on a second limited current amount and generates a fourth internal power signal PSIG 4  having a fourth internal voltage PSIG 4 _V and a fourth internal current PSIG 4 _I. The switch circuit  650  outputs one of the first internal power signal PSIG 1 , a sum of the first internal power signal PSIG 1  and the third internal power signal PSIG 3  and a sum of the first internal power signal PSIG 1 , the third internal power signal PSIG 3  and the fourth internal power signal PSIG 4  as the output power signal PSIGOUT, based on a difference between the first internal voltage PSIG 1 _V, the third internal voltage PSIG 3 _V and the fourth internal voltage PSIG 4 _V. 
         [0129]    In example embodiments, a level of the first offset voltage is greater than a level of the second offset voltage. 
         [0130]    The first limited current amount may be adjusted by a first limited current adjusting signal SIGLIMIT 1  and the second limited current amount may be adjusted by a second limited current adjusting signal SIGLIMIT 2 . The operation of the power circuit  600  may be understood based on the description with reference to  FIGS. 1 through 15 , for example.  FIG. 17  is a block diagram illustrating a solid state drive (SSD) system according to example embodiments. 
         [0131]    Referring to  FIG. 17 , an SSD system  700  includes a host  710  and an SSD  720 . The SSD  720  includes first through n-th non-volatile memory devices  723 - 1 ,  723 - 2 , . . . ,  723 - n  and a SSD controller  722 . Here, n represents an integer greater than or equal to 2. The first through n-th non-volatile memory devices  723 - 1 ,  723 - 2 , . . . ,  723 - n  may be used as a storage medium of the SSD  720 . 
         [0132]    Each of the first through n-th non-volatile memory devices  723 - 1 ,  723 - 2 , . . . ,  723 - n  may include a memory cell array formed on a substrate with a three-dimensional structure. Memory cells included in the memory cell array may be formed in a direction perpendicular to the substrate. The memory cells included in the memory cell array may be connected to a plurality of word lines, which are stacked in a direction perpendicular to the substrate, and a plurality of bit lines, which are formed in a direction parallel to the substrate. 
         [0133]    The SSD controller  722  is coupled to the first through n-th non-volatile memory devices  723 - 1 ,  723 - 2 , . . . ,  723 - n  through first to n-th channels CH 1 , CH 2 , . . . CHn, respectively. 
         [0134]    The SSD controller  722  exchanges a signal SGL with the host  710  through a signal connector  724 . The signal SGL may include a command, an address and data. The SSD controller  722  may perform a program operation and a read operation on the first through n-th non-volatile memory devices  723 - 1 ,  723 - 2 , . . . ,  723 - n  according to the command received from the host  710 . 
         [0135]    The SSD  720  may further include an auxiliary power supply  726 . The auxiliary power supply  726  may receive power PWR from the host  710  through a power connector  725  and provide power to the SSD controller  722 . The auxiliary power supply  726  may be placed inside or outside the SSD  720 . For example, the auxiliary power supply  726  may be placed on a main board and provide auxiliary power to the SSD  720 . 
         [0136]    The auxiliary power supply  726  may include one of the power circuits  100 ,  200 ,  300 ,  400 ,  500  and  600  of respective  FIGS. 1, 10, 11, 12, 15 and 16 . 
         [0137]      FIG. 18  is a block diagram illustrating a mobile system according to example embodiments. 
         [0138]    Referring to  FIG. 18 , a mobile system  800  includes an application processor (AP)  810 , a connectivity unit  820 , a user interface  830 , a non-volatile memory device  840 , a volatile memory device  850  and a power supply  860 . 
         [0139]    In some embodiments, the mobile system  800  may be a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, etc. 
         [0140]    The application processor  810  may execute applications, such as a web browser, a game application, a video player, etc. In some example embodiments, the application processor  810  may include a single core or multiple cores. For example, the application processor  810  may be a multi-core processor, such as a dual-core processor, a quad-core processor, a hexa-core processor, etc. The application processor  810  may include an internal or external cache memory. 
         [0141]    The connectivity unit  820  may perform wired or wireless communication with an external device. For example, the connectivity unit  820  may perform Ethernet communication, near field communication (NFC), radio frequency identification (RFID) communication, mobile telecommunication, memory card communication, universal serial bus (USB) communication, etc. In some embodiments, the connectivity unit  820  may include a baseband chipset that supports communications, such as global system for mobile communications (GSM), general packet radio service (GPRS), wideband code division multiple access (WCDMA), high speed downlink/uplink packet access (HSxPA), etc. 
         [0142]    The non-volatile memory device  840  may store a boot image for booting the mobile system  800 . 
         [0143]    The non-volatile memory device  840  may include a memory cell array formed on a substrate in a three-dimensional structure. Memory cells included in the memory cell array may be formed in a direction perpendicular to the substrate. The memory cells included in the memory cell array may be connected to a plurality of word lines, which are stacked in a direction perpendicular to the substrate, and a plurality of bit lines, which are formed in a direction parallel to the substrate. 
         [0144]    The volatile memory device  850  may store data processed by the application processor  810 , or may operate as a working memory. 
         [0145]    The user interface  830  may include at least one input device, such as a keypad, a touch screen, etc., and at least one output device, such as a speaker, a display device, etc. 
         [0146]    The power supply  860  may supply an operating voltage to the mobile system  800 . The power supply  860  may include one of the power circuits  100 ,  200 ,  300 ,  400 ,  500  and  600  of respective  FIGS. 1, 10, 11, 12, 15 and 16 . 
         [0147]    In some embodiments, the mobile system  800  may further include an image processor, and/or a storage device, such as a memory card, a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. 
         [0148]    In some embodiments, the mobile system  800  and/or components of the mobile system  800  may be packaged in various forms, such as package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline IC (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi-chip package (MCP), wafer-level fabricated package (WFP), or wafer-level processed stack package (WSP). 
         [0149]    The present disclosure may be applied to various electronic devices including a regulator circuit. For example, the present disclosure may be applied to systems such as be a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, etc. 
         [0150]    The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.