Abstract:
The present disclosure relates to a semiconductor package having encapsulated dies with enhanced thermal performance. The semiconductor package includes a carrier, an etched flip chip die attached to a top surface of the carrier, a first mold compound, and a second mold compound. The etched flip chip die includes a device layer and essentially does not include a substrate. The first mold compound resides on the top surface of the carrier, surrounds the etched flip chip die, and extends beyond a top surface of the etched flip chip die to form a cavity, to which the top surface of the etched flip chip die is exposed. The second mold compound fills the cavity and is in contact with the top surface of the etched flip chip die. The second mold compound having a high thermal conductivity improves thermal performance of the etched flip chip die.

Description:
RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 14/959,129, filed Dec. 4, 2015, which claims priority to provisional patent application Ser. No. 62/138,177, filed Mar. 25, 2015, the disclosures of which are hereby incorporated herein by reference in their entirety. 
     
    
     FIELD OF THE DISCLOSURE 
       [0002]    The present disclosure relates to a semiconductor package, and more particularly to a semiconductor package having encapsulated dies with enhanced thermal performance. 
       BACKGROUND 
       [0003]    With the current popularity of portable communication devices and developed semiconductor fabrication technology, high speed and high performance transistors are more densely integrated on semiconductor dies. Consequently, the amount of heat generated by the semiconductor dies will increase significantly due to the large number of transistors integrated on the semiconductor dies, the large amount of power passing through the transistors, and the high operation speed of the transistors. Accordingly, it is desirable to package the semiconductor dies in a configuration for better heat dissipation. 
         [0004]    Flip chip assembly technology is widely utilized in semiconductor packaging due to its preferable solder interconnection between flip chip dies and laminate, which eliminates the space needed for wire bonding and die surface area of a package and essentially reduces the overall size of the package. In addition, the elimination of wire connections and implementation of a shorter electrical path from the flip chip die to the laminate reduces undesired inductance and capacitance. 
         [0005]    In flip chip assembly, mold compounds, formulated from epoxy resins containing silica particulates, are used to encapsulate and underfill flip chip dies to protect the dies against damage from the outside environment. Some of the mold compounds can be used as a barrier withstanding chemistries such as potassium hydroxide (KOH), sodium hydroxide (NaOH) and acetylcholine (ACH) without breakdown; while some of the mold compounds having good thermal conductive features can be used for heat dissipation of dies. 
         [0006]    To accommodate the increased heat generation of high performance dies and to utilize the advantages of flip chip assembly, it is therefore an object of the present disclosure to provide an improved semiconductor package design with flip chip dies in a configuration for better heat dissipation. In addition, there is also a need to enhance the thermal performance of the flip chip dies without increasing the package size. 
       SUMMARY 
       [0007]    The present disclosure relates to a semiconductor package having encapsulated dies with enhanced thermal performance. The semiconductor package includes a carrier having a top surface, an etched flip chip die attached to the top surface of the carrier, a first mold compound, and a second mold compound. The etched flip chip die includes a device layer and essentially does not include a substrate. The first mold compound resides on the top surface of the carrier, surrounds the etched flip chip die, and extends beyond a top surface of the etched flip chip die to form a cavity, to which the top surface of the etched flip chip die is exposed. The second mold compound fills the cavity and is in contact with the top surface of the etched flip chip die. The second mold compound is a high thermal conductivity mold compound, which improves thermal performance of the etched flip chip die. 
         [0008]    Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
         [0009]    The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
           [0010]      FIG. 1  provides a flow diagram that illustrates an exemplary etching and filling process according to one embodiment of the present disclosure. 
           [0011]      FIGS. 2-8  illustrate the steps associated with the etching and filling process provided in  FIG. 1 . 
           [0012]      FIG. 9  illustrates an exemplary application of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
         [0014]    It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
         [0015]    It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
         [0016]    Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. 
         [0017]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0018]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0019]    The present disclosure relates to a semiconductor package having encapsulated dies with enhanced thermal performance.  FIG. 1  provides a flow diagram that illustrates an exemplary etching and filling process to fabricate the disclosed semiconductor package.  FIGS. 2-8  illustrate the steps associated with the etching and filling process provided in  FIG. 1 . Although various types of materials may be used for the substrate, the following examples incorporate silicon as the preferred material. 
         [0020]    Initially, a plurality of flip chip dies  10  are attached on a top surface of a carrier  12  as depicted in  FIG. 2  (Step  100 ). The carrier of the described embodiment is formed from a laminate, but may also be formed from a wafer level fan out (WLFO) carrier, a lead frame, a ceramic carrier, or the like. For the purpose of this illustration, each flip chip die  10  includes a substrate  14  with approximately 150-500 μm thickness, a device layer 16 with approximately 4-7 μm thickness, layer contacts  18  located on a bottom surface of the device layer  16 , and solder interconnections  20  provided on each of the layer contacts  18 . The device layer  16  may be formed from silicon dioxide, gallium arsenide, gallium nitride, silicon germanium, and the like and includes various devices, such as diodes, transistors, mechanical switches, resonators, and the like. The carrier  12  includes a carrier body  22 , carrier contacts  24  on a top surface of the carrier  12  and input/output (I/O) pads (not shown) on a bottom surface of the carrier  12 . The I/O pads on the bottom surface of the carrier  12  may be formed by a ball grid array (BGA) or land grid array (LGA) method and selectively connect to the carrier contacts  24  through any number of vias (not shown). The solder interconnections  20  of the flip chip dies  10  are used to electrically and physically connect to the carrier contacts  24  of the carrier  12 . As such, the backside of the substrate  14  of the plurality of flip chip dies  10  will generally be the tallest component after the attaching process. The height between the device layer  16  and the carrier body  22  often varies from 15-200 μm. 
         [0021]    A first mold compound  26  is then applied over the top surface of the carrier  12  such that the flip chip dies  10  are encapsulated by the first mold compound  26  as illustrated in  FIG. 3  (Step  102 ). The first mold compound  26  may be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dam fill encapsulation and screen print encapsulation. The first mold compound  26  is an organic epoxy resin system or the like, such as Hitachi Chemical Electronic Materials GE-100LFC, which can be used as an etchant barrier to protect the flip chip dies  10  against etching chemistries such as KOH, NaOH and ACH. A curing process (Step  104 ) is then used to harden the first mold compound. 
         [0022]    With reference to  FIGS. 4 through 6 , a process for etching away substantially the entire substrate  14  of each encapsulated flip chip die  10  is provided according to one embodiment of the present disclosure. The process begins by forming a protective coating  28  over the bottom surface of the carrier  12 , as shown in  FIG. 4  (Step  106 ). The purpose of the protective coating  28  is to prevent potential damage to the I/O pads (not shown) on the bottom surface of the carrier  12  in subsequent processing steps. The protective coating  28  may be a chemical resistant tape or liquid protective coating, which can withstand etching chemistries such as KOH, NaOH and ACH without breakdown. Alternately, a rigid carrier can be sealed on the bottom surface of the carrier  12  as a protective coating  28  to prevent the I/O pads (not shown) on the bottom surface of the carrier  12  from contacting the destructive etchant materials in later etching processes. 
         [0023]    The next process step is to thin the first mold compound  26  down to expose the back side of the flip chip dies  10 , wherein the only exposed component of the flip chip dies  10  will be the substrate  14 , as shown in  FIG. 5  (Step  108 ). The thinning procedure may be done with a mechanical process. An alternate process step would be to leave the back side of the flip chip dies  10  always exposed during the molding process with the first mold compound  26 . 
         [0024]    Next, a wet/dry etchant chemistry, which may be KOH, ACH, NaOH or the like, is used to etch away substantially the entire substrate  14  of each flip chip die  10  to provide an etched flip chip die  10 E that has an exposed surface at the bottom of a cavity, as shown in  FIG. 6  (Step  110 ). Herein, etching away substantially the entire substrate  14  refers to removal of at least 95% of the entire substrate  14 , and perhaps a portion of the device layer  16 . As such, in some applications, there is a thin layer of the substrate  14  left at the bottom of the cavity of each etched flip chip die  10 E, which covers the device layer  16 , to protect the devices located on the device layer  16 . For other cases, the substrate  14  is etched away completely and the device layer  16  is exposed at the bottom of the cavity of each etched flip chip die  10 E. 
         [0025]    With reference to  FIGS. 7 through 8 , a process for filling the remaining cavity of each etched flip chip die  10 E is provided according to one embodiment of the present disclosure. After the etching step is done, a second mold compound  30  is applied to substantially fill the remaining cavity of each etched flip chip die  10 E, as illustrated in  FIG. 7  (Step  112 ). The second mold compound  30  may be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dam fill encapsulation, and screen print encapsulation. The second mold compound  30  is a high thermal conductivity mold compound. Compared to the normal mold compound having 1 w/m·k thermal conductivity, a high thermal conductivity mold compound has 2.5 w/m·k˜10 w/m·k or greater thermal conductivity, such as Hitachi Chemical Electronic Materials GE-506HT. The higher the thermal conductivity, the better the heat dissipation performance of the encapsulated etched flip chip dies  10 E. Additionally, the second mold compound  30  directly contacts the exposed surface of each etched flip chip die  10 E at the bottom of each cavity. If the substrate  14  is removed completely in the etching step (Step  110 ), the second mold compound  30  directly contacts the device layer  16 . If there is a thin layer of substrate  14  left in the etching step (Step  110 ), the second mold compound  30  directly contacts the thin layer of substrate  14 . Notably, the first mold compound  26  could be formed from the same material as the second mold compound  30 . However, unlike the second mold compound  30 , the first mold compound  26  does not have a thermal conductivity requirement in higher performing embodiments. A curing process (Step  114 ) is then provided to harden the second mold compound. The normal curing temperature is 175° F. and could be higher or lower depending on which material is used as the second mold compound  30 . 
         [0026]    The top surface of the second mold compound  30  is then planarized to ensure each encapsulated etched flip chip die  10 E has a flat top surface as shown in  FIG. 8  (Step  116 ). A package grinding process may be used for planarization. Next, the protective coating  28  applied over the bottom surface of the carrier  12  is removed as illustrated in  FIG. 9  (Step  118 ). Lastly, the product could be marked, singulated and tested as a module (Step  120 ). 
         [0027]    Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.