Abstract:
Apparatus for indicating proper compensation of an adjustable frequency compensation network comprises a signal source operable to apply a rectangular pulse train having a preselected peak magnitude to the frequency compensation network, and a peak detector circuit for comparing the output voltage of the frequency compensation network to at least one threshold value. The peak detector circuit is used to determine whether, at a time that follows a transition of a pulse of the pulse train by an interval that is less than one time constant of the frequency compensation network, the output voltage of the frequency compensation network bears a predetermined relationship to the threshold value.

Description:
This invention relates to apparatus for indicating proper compensation of an adjustable frequency compensation network, particularly, but not exclusively, an attenuation probe network for an oscilloscope. 
     BACKGROUND OF THE INVENTION 
     Attenuation probes are generally associated with oscilloscopes; however, they may be used as a means for coupling an input signal to any electronic test and measurement instrument. 
     An attenuator probe network typically comprises two resistors connected in series between the probe tip and ground, the resistance values of the resistors being in a predetermined ratio, and two capacitors connected in parallel with the two resistors respectively. The output of the probe is taken from the junction point of the resistors. Therefore, one of the resistors is connected in series between the probe tip and the probe&#39;s output terminal and the other resistor is a shunt resistor. Similarly, the capacitors comprise a series capacitor and a shunt capacitor. The ratio of the resistance values of the resistors establishes the DC attenuation factor of the network whereas the AC performance of the network is governed by the capacitance values of the capacitors. The impedance of a capacitor is frequency dependent, and therefore it is necessary to adjust the relative capacitance values of the probe network to provide a constant attenuation factor over the frequency range of the signals of interest. The operation of adjusting the relative capacitance values of the capacitors of an attenuation probe is known as compensation. An apparatus for indicating proper compensation of an adjustable attenuation probe network is described in U.S. Pat. No. 4,253,057. In the case of U.S. Pat. No. 4,253,057, the series resistor and the series capacitor are incorporated in the probe itself, while the shunt resistor is part of the instrument&#39;s input amplifier stage. The shunt capacitor comprises a fixed capacitor in the input amplifier stage and a variable capacitor in the probe itself. The apparatus described in U.S. Pat. No. 4,253,057 operates by applying a square wave signal to the probe network and comparing the peak value of the signal at the output terminal of the Probe network with a previously-detected and stored reference value. 
     A disadvantage of a Practical implementation of the apparatus described in U.S. Pat. No. 4,253,057 is that it is necessary for the operator to adjust the variable capacitor to its minimum capacitance value prior to making the final adjustment, because the adjustment must be made from the undercompensated state. Moreover, owing to charge redistribution when the compensation capacitor is adjusted, an erroneous voltage may be developed across the compensation capacitor, giving rise to false indications of compensation. Further, the stored reference value is detected by adjusting the compensation capacitor to the undercompensated state, and the reference value is subject to error due to the possibility of the voltage developed across the compensation capacitor being erroneous. 
     SUMMARY OF THE INVENTION 
     In a preferred embodiment of the invention, apparatus for indicating proper compensation of an adjustable frequency compensation network having a predetermined time constant comprises a source of a constant reference voltage. A gate has its input terminal connected to the source. The output terminal of the gate is connected to the frequency compensation network, and the gate also has an enable terminal connected to a gate enable circuit. In a first mode of operation of the gate enable circuit, the reference voltage that is applied to the input terminal of the gate is conducted to the output terminal and is applied to the compensation network for an interval that is substantially longer than the time constant of the frequency compensation network. In a second mode of operation of the gate enable circuit, the gate is alternately enabled and disabled, so that the reference voltage is applied intermittently to the frequency compensation network. The duration of the interval during which the reference voltage is applied to the frequency compensation network in the second mode is less than the time constant of the frequency compensation network. The peak output voltage of the frequency compensation network during the interval for which the reference voltage is applied to the compensation network is equal to the output voltage in the first mode of operation only if the frequency compensation network is properly adjusted. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawing in which: 
     FIG. 1 is a block diagram of apparatus embodying the present invention, and 
     FIG. 2 shows waveforms useful in explaining operation of the FIG. 1 apparatus. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 shows an attenuation probe 12 that is connected to an input buffer amplifier stage 14 of an electronic instrument, other details of which are not shown. For the purpose of determining proper compensation of the probe 12, the output of the amplifier stage 12 is connected to a peak detector circuit 44. Signals for use in adjusting the compensation of the probe 12 are applied to the probe tip from a signal source 10. 
     The input buffer amplifier stage 14 comprise an amplifier 30. The input impedance of the amplifier stage 14 is established by the parallel combination of a shunt resistor 34 and a shunt capacitor 36. The resistor 34 may, for example, be a 1 megohm resistor, and the value of the capacitor 36 is chosen to provide a predetermined input time constant. Generally, the value of the capacitor 36 is small. In conventional instruments, the capacitor 36 has a value of 15 or 20 pF. 
     The attenuation probe 12 comprises a series resistor 20, a fixed series capacitor 22 and a variable shunt capacitor 24. The value of the resistor 20 is chosen to provide the proper voltage divider ratio in conjunction with the shunt resistor 34. For example, if it is desired that the probe 12 have an attenuation ratio of 10:1, so that its output voltage is one-tenth of its input voltage, age, the resistance value of the series resistor 20 is nine times that of the shunt resistor 34. The time constant of the probe 12 should be matched to the time constant of the input buffer amplifier stage 14 in order to provide a flat frequency response so that a signal that is passed through the probe is not distorted because of variation in attenuation factor with signal frequency. Proper matching is achieved by establishing the appropriate capacitance divider ratio for the values of the capacitors 22 and 24, in conjunction with the value of the capacitor 36. 
     The signal source 10 comprises a circuit 80 that provides a DC output voltage V ref , a gate enable circuit 82, and a NAND gate 84. The value of the DC output voltage need not be established with precision: it is necessary only that the voltage be stable with time, so that it does not vary during the compensation operation. The gate enable circuit 82 has two operating modes, and is placed in one mode or the other in dependence on a control signal provided by a controller 86. In the first operating mode (from time t 0  to time t 1  in FIG. 2), the gate enable circuit 82 provides a constant output at logic level 0, and the NAND gate 84 provides a constant DC voltage level V ref  at its output (waveform A). This voltage is applied to the probe 12, and results in application to the input terminal of the amplifier 20 of a constant voltage V peak  (waveform B). Because the voltage V ref  is constant, the value of V peak  is determined by the ratio of the resistors 20 and 34, and is not affected by the capacitors 22, 24 and 36. The output voltage of the amplifier 30 is applied to the peak detector 44. 
     The peak detector 44 comprises a comparator 50 which receives the output signal from the amplifier 30, and a digital-to-analog converter (DAC) 54. The DAC 54 receives digital signals from the controller 86 and generates therefrom an analog voltage that is applied to the threshold input of the comparator. The comparator provides an output signal to the controller 86 that is at logical zero if the voltage of the input signal received from the amplifier 30 is below the threshold voltage provided by the DAC 54, at logical one if the voltage of the input signal is above the threshold voltage, and oscillates between logical zero and logical one if the input signal voltage is equal to the threshold voltage. The controller 86 causes the lamp 70 u  or 70 o  to be illuminated depending on whether the comparator provides a logical zero or logical one output signal. If the output signal of the comparator oscillates, both lamps are illuminated. Therefore, the lamps provide a visual indication as to the nature of the signal received from the comparator. 
     In the first mode of operation, the controller 86 causes the threshold voltage to increase monotonically until the output signal of the comparator oscillates, indicating that the input signal voltage is equal to the threshold voltage. In fact, there will be a range of values of the input signal voltage over which the output signal of the comparator oscillates, and the size of this range depends on the sensitivity of the comparator. This range of values provides a window function. The controller responds to oscillation of the comparator&#39;s output signal by latching the digital signal applied to the DAC 54, and accordingly the threshold voltage then remains constant. In addition, the controller 86 switches the signal source 10 to its second operating mode (beyond time t 1  in FIG. 2). In this mode, the gate enable circuit 82 generates alternate high and low logic levels, so that the output voltage of the circuit 80 is chopped by the NAND gate 84. The voltage V ref  is thus applied intermittently to the probe 12, so that the probe network receives a rectangular waveform input signal. The rise and fall times of the rectangular waveform are each about one-fifth to one-tenth of the time constant of the probe network. The period of the output signal of the gate enable circuit 82 and the duty cycle of that signal are selected so that the output signal of the gate 84 remains at the voltage V ref  for a time shorter than the time constant of the network comprising the resistors 20 and 34 and the capacitors 22, 24, and 36. This implies that the voltage level at the input of the amplifier 30 cannot attain the value V peak  during the active interval (the interval for which the output voltage of the NAND gate 84 is V ref ) unless the capacitor 24 has the value such that the network is properly compensated. Assuming that only one of the lamps 70 u  and 70 o  is illuminated, the operator notes which lamp 70 is illuminated and increases or decreases the capacitance of the capacitor 24, depending on whether the lamp 70 u  or 7- o  is illuminated, until both lamps are illuminated, indicating that the probe network is properly compensated. 
     It will be seen that in the case of the illustrated apparatus it is not necessary to adjust the compensation capacitor 24 in order to generate the threshold voltage that is applied to the comparator in the second mode of operation. Therefore, error in the threshold voltage due to displacement of charge on the capacitor does not arise. Moreover, it is not necessary to adjust the capacitor to its minimum capacitance value and therefore the rate of change of capacitance can be smaller. 
     It will be appreciated that the present invention is not restricted to the particular apparatus that has been described and illustrated, and that variations may be made therein without departing from the scope of the invention as defined in the appended claims and equivalents thereof. For example, instead of using the simple comparator 50 that receives a single threshold voltage from the DAC 54 and has two defined output states, it would be possible to use a window comparator that receives two threshold voltages from the DAC 54 and has three defined output states. Use of a window comparator provides the advantage that it is possible to adjust the difference between the threshold values by way of the controller. The comparison could take place in the digital domain, by converting the output signal from the amplifier 30 to digital form and using a digital comparator. Such a digital comparator would have three defined output states depending on the relationship between the digital signals received at its inputs. The size of the window established by the digital comparator could be enlarged through use of at least one &#34;don&#39;t care&#34; bit. Moreover, if the active interval of the pulse train is more than one time constant of the probe network, it is possible to obtain the same result as if the active interval of the train were less than one time constant by examining the output of the comparator within one time constant following the first transition of each pulse of the pulse train. It is not necessary that the positive peak value of the output voltage from the amplifier 30 be compared to the threshold voltages if the negative peak of the signal provided by the source 10 in its second operating mode is known and is non-zero. The voltages applied to the input terminal of the probe network by the signal source may be the NAND gate&#39;s internal high and low output reference voltages. Other switching means than a NAND gate may be used to provide the desired output signals of the signal source. 
     It is not necessary to use a peak detector to determine whether the signal input voltage to the comparator is equal to the threshold voltage, since an oscilloscope may be used instead.