Abstract:
This invention disclosed a novel manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that an oxide-nitride-oxide (ONO) sandwich structure is employed instead of oxide-nitride dual layer structure before trench etching. Another aspect is, through the formation of silicon oxide spacer in trench sidewall and silicon oxide remaining in trench bottom in the deposition and etch back process, the new structure hard mask can effectively protect active region from impurity implanted in ion implantation process.

Description:
The current invention claims a foreign priority to application China 200910202069.1 filed on Dec. 31, 2009. 
     FIELD OF THE INVENTION 
     This invention belongs to one type of bipolar transistor (BJT). More particularly it relates to one type of collector of a bipolar transistor. 
     BACKGROUND OF THE INVENTION 
     A conventional bipolar transistor is illustrated in  FIG. 1 . PNP bipolar transistor has same structure as NPN bipolar transistor, with only reverse impurity type of every parts of the device. NPN bipolar transistor is illustrated here as example. N type heavily doped region  11  is above p type substrate  10 . N type epitaxy layer  12  (doping level is lower than buried layer  11 , normally medium to low doped) is above heavily doped n buried layer  11 . There are a few shallow trench isolation (STI) structures  13   a / 13   b / 13   c / 13   d  among n type epitaxy layer  12 . The bottom of these STI is in contact of buried layer  11 . N type heavily doped region  14  exists between STI  13   a / 13   b  or  13   c / 13   d  inside epitaxy layer  12 , which is used as collector pick up (sinker). P type base  15  is on top of n type epitaxy layer  12 . Base  15  is a semiconductor material, such as silicon, silicon germanium alloy, etc. It is connected to base pick up B. Heavily doped emitter poly  16  is on top of base  15 . It is connected to pick up E. In all, n type emitter  16 , p type base  15 , n type epitaxy layer  12  and n type buried layer  11  formed NPN bipolar transistor vertically. 
     In bipolar transistor illustrated in  FIG. 1 , n type epitaxy layer  12  between STI  13   b  and  13   c  is collector of the bipolar transistor. The collector is picked up to C through n type heavily doped buried layer  11  (collector buried layer) and n type heavily doped sinker  14 . The collector buried layer area is large by this approach. Consequently the parasitic capacitance with substrate is also large. A deep trench isolation structure  130   a / 130   d  is commonly formed under STI  13   a / 13   d  to enclose entire bipolar transistor periphery. Deep trench isolation structure  130   a / 130   d  extend through n type heavily doped buried layer  11  until inside p type substrate  10 . It cuts through n type heavily doped layer  11 , in order to reduce junction area of collector buried layer to p type substrate  10 , and reduce parasitic capacitance between them. 
       FIG. 1  is only illustration of a bipolar transistor. There may be variations of each portion during real manufacturing. 
     Following process steps are normally adopted for collector and buried layer of above mentioned bipolar transistor: 
     Step 1: n type impurity is ion implanted into p type substrate. The commonly used n type impurity is Phosphorus (P), Arsenic (As), Antimony, etc. N type heavily doped buried layer  11 , also called collector buried layer, is formed then. 
     Step 2: N type epitaxy layer  12  is grown (deposit one layer of n type single crystal  12 ) on top of n type heavily doped buried layer  11 . The doping level of  12  is lower than heavily doped buried layer  11 . 
     Step 3: Shallow trench was etched inside silicon. The depth of shallow trench is normally below 2 um. The position of shallow trench is shown in  FIG. 1  as  13   a / 13   b / 13   c / 13   d.    
     A deep trench is then etched at the bottom of STI which encloses entire bipolar transistor. The depth of deep trench is normally more than Tum. The position of deep trench is indicated as  130   a / 130   d  in  FIG. 1 . 
     Dielectric such as polysilicon is then filled into deep trench. Deep trench isolation structure  130   a / 130   d  is formed. 
     Shallow trench is also filled with dielectric such as silicon oxide. The shallow trench isolation structure  13   a / 13   b / 13   c / 13   d  is formed. 
     N type epitaxy layer  12  between STI  13   b / 13   c  is the collector region. There are a few disadvantages of the approach that forms collector and buried layer of bipolar transistor. First, the cost of growing n type single crystal  12  on top of silicon substrate  12  is high. Second, the depth of deep trench isolation structure  130   a / 130   d  is more than 7 um, etch and fill in process are complex and expensive. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to offer a manufacturing approach of collector and buried layer of one type of bipolar transistor. No process of buried layer and epitaxy is required. Following process steps are included in the manufacturing approach of collector and buried layer of bipolar transistor: 
     Step 1, an ONO(oxide-nitride-oxide) structure hard mask is deposited on the silicon substrate surface, and then shallow trench isolation (STI) is adopted. The shallow trenches  20   a  and  20   b  is etched in silicon substrate  20 . The depth of the trench is less than 2 um. 
     The ONO hard mask  30  mentioned above includes isolation oxide layer  30   a  in bottom, silicon nitride  30   b  in middle and silicon oxide  30   c  on top. 
     Step 2, a silicon oxide film  31  is deposited on wafer surface. Then this oxide film  31  is etched back to the ONO hard mask. Now, a silicon oxide spacer is shaped in the sidewall of the shallow trenches  20   a  and  20   b . Some silicon oxide will remain at the bottom of shallow trenches  20   a  and  20   b.    
     Step 3, the bottom of STI  20   a  and  20   b  mentioned above is doped with impurity by ion implantation. A doped region  21   a  and  21   b  in the substrate  20  is formed near the bottom of above stated STI  20   a  and  20   b.    
     Step 4, the oxide  30   c ,  31   a  and  31   b  is stripped by wet etch. 
     Step 5, dielectric is filled into above stated shallow trenches  20   a  and  20   b . Shallow trench isolation  22   a  and  22   b  is then formed. 
     Step 6, the wafers undergo high temperature anneal process. Highly doped area  21   a  and  21   b  mentioned above links between STI  22   a  and  22   b  through lateral diffusion. Pseudo buried layer  21  is formed. The pseudo buried layer  21  is collector buried layer of above stated bipolar transistor. 
     Step 7, the silicon substrate between STI  22   a  and  22   b  and above pseudo buried layer goes through single or multiple ion implantation. The above mentioned active region  20  is converted into doped region  23 . The dope concentration should be lower than that of pseudo buried layer  21 . 
     The doped region  23  is the collector of the bipolar transistor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing and the object, features, and advantages of the invention will be apparent from the following detailed description of the invention, as illustrated in the accompanying drawings, in which: 
         FIG. 1  is conventional bipolar transistor structure cross section view;.  FIG. 2  is collector and buried layer of present invented bipolar transistor; 
         FIGS. 3   a ˜ 3   g  are step by step illustration of manufacturing approach of collector and buried layer of present invented bipolar transistor. 
         FIG. 4  presents an illustration of dopant concentration of collector buried layer of present invention. 
     
    
    
     EXPLANATION OF THE LABELS 
     
         
           10 : P type substrate;  11 : N type heavily doped buried layer; 
           12 : N type epitaxy layer;  13   a / 13   b / 13   c / 13   d : Shallow trench isolation structure 
           130   a / 130   d : Deep trench isolation;  14 : N type heavily doped region; 
           15 : Base;  16 : Emitter; 
           20 : Silicon substrate;  20   a / 20   b : Shallow trench; 
           21   a / 21   b : Doped zone;  21 : Pseudo buried layer; 
           22   a / 22   b : Shallow trench isolation structure;  23 : Doped region. 
         C: Collector pick up; B: Base pick up; E: Emitter pick up; 
       
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Refer to  FIG. 2 , silicon substrate  20  of present invented bipolar transistor includes: 
     Shallow trench isolation structure  22   a / 22   b , the active region between shallow trench isolation region  22   a / 22   b  is the collector of bipolar transistor. 
     Pseudo buried layer  21 , lies at the bottom of STI region  22   a / 22   b , is continuous between  22   a / 22   b  (merge together instead of two separate regions). Above stated pseudo buried layer is the collector buried layer of the bipolar transistor. 
     Doped region  23  is the active region between STI  22   a / 22   b  and above pseudo buried layer  21 . The doping level of  23  is less than that of pseudo buried layer  21 . Doped region  23  is the collector of bipolar transistor. 
     For NPN bipolar transistor, above stated substrate  10  is p type. Pseudo buried layer  21  and doped region  23  are all n type. For PNP bipolar transistor, above stated substrate  10  is n type. Pseudo buried layer  21  and doped region  23  are all p type. 
     As indicated in  FIG. 1 , conventional buried layer  11  is formed by ion implantation to silicon substrate before epitaxy growth, the area is big. It is necessary to use deep trench isolation structure  130   a / 130   d  to divide buried layer  11  in order to reduce parasitic capacitance. Present invented pseudo buried layer  21  as indicated in  FIG. 2  is formed by ion implantation and high temperature anneal after shallow trench etch, the area is small. It is un-necessary to use deep trench structure in subsequent process. In other hand, doped region  23  is used to replace epitaxy layer  12 . Above invention not only simplify the device structure and manufacturing approach, but also conserve the manufacturing cost. 
     Following process steps have been included to make the collector of the bipolar transistor indicated in  FIG. 2 : 
     Step 1: refer to  FIG. 3   a , an ONO hard mask is deposited on silicon substrate, shallow trench  20   a / 20   b  is etched using STI process. The depth of the trench is less than 2 um. This step further includes: 
     In step 1.1, thin silicon oxide (SiO 2 ) layer is grown thermally on silicon surface. This SiO 2  layer is called pad oxide. It is used to protect active region from chemical contamination when silicon nitride (Si 3 N 4 ) is removed in subsequent process. 
     In step 1.2, a silicon nitride (Si 3 N 4 ) thin film is deposited on silicon surface. Si 3 N 4  is a hard dielectric material used here as hard mask. It is used to protect the active region when perform STI dielectric fill-in and use as a stop layer in subsequent chemical-mechanical polish (CMP) process. 
     In step 1.3, a thin film of SiO 2  is deposited on silicon surface. The thickness is 300-800 A. The SiO 2    30   a , Si 3 N 4    30   b , and SiO 2    30   c  forms ONO hard mask  30 . 
     In step 1.4, photo resist is spin coated on silicon surface, followed by exposure and develop step. An etch window is exposed. 
     In step 1.5, the hard mask in exposed window is etched away, together with part of silicon substrate. Shallow trench  20   a    20   b  is formed. 
     Step 2: refer to  FIG. 3   b , a silicon oxide film  31  is deposited on wafer surface, then this oxide film  31  is etched back to the ONO hard mask. Silicon oxide spacer is shaped in the sidewall of the shallow trenches  20   a  and  20   b  mentioned above. Some silicon oxide will be remained on the bottom of shallow trenches  20   a  and  20   b , as shown in  FIG. 3   c.    
     It is a common practice that, after shallow trench is etched, a thermal grown oxide is grown on shallow trench sidewall and bottom. This silicon oxide calls liner oxide. It is used to improve the interface characteristics between shallow trench silicon and the dielectric filled. This liner oxide is very thin which have no impact to ion implantation. Also there is no indication in  FIG. 3   b ,  FIG. 3   c  and other figures. 
     Step 3: refer to  FIG. 3   d , the bottom of STI  20   a / 20   b  is doped with impurity by high dose, low energy ion implant. High doped regions  21   a    21   b  are then formed near the bottom of STI  20   a    20   b  in substrate  20 . 
     There is ONO hard mask  30  on silicon substrate surface  20 , and silicon oxide spacer  31   a  on sidewall of STI  20   a / 20   b , ion implant is stopped to penetrate to active region below ONO hard mask  30  and active region below sidewall of STI  20   a / 20   b.    
     Step 4, refer to  FIG. 3   e , silicon oxide is removed by wet etch. The oxide includes  30   c  above hard mask  30 ,  31   a  on sidewall of STI  20   a / 20   b ,  31   b  at bottom of STI  20   a / 20   b . After silicon oxide is removed from silicon surface, the hard mask remained on silicon surface includes bottom silicon oxide  30   a  and silicon nitride  30   b  dual layers. 
     Step 5, refer to  FIG. 3   f , dielectric is filled into above stated shallow trenches  20   a / 20   b . Shallow trench isolation  22   a  and  22   b  is then formed. 
     The process in forming STI also includes: 
     Step 5.1, a layer of dielectric such as silicon oxide is filled in. The dielectric should at least fill in shallow trench fully. 
     Step 5.2, silicon wafer is polished using chemical-mechanical polish process. The filled dielectric should be in same height as silicon top surface. 
     Step 5.3, Si 3 N 4  is removed by wet etch process. 
     Step 6, refer to  FIG. 3   g , thermal anneal process is carried out for the wafer, two heavily doped regions  21   a / 21   b  diffuse laterally and vertically. The lateral diffusion results in link of two heavily doped region  21   a / 21   b  between shallow trench isolation structure  22   a / 22   b . Pseudo buried layer  21  is then formed. The n type heavily doped region  21  is the collector buried layer of whole bipolar transistor. 
     In  FIG. 3   g , as main part (Si 3 N 4  deposited in step 1.2) of hard mask  30  is removed, hard mask is no longer illustrated in  FIG. 3   g . The pad oxide grown in step 1.1 is not shown in  FIG. 3   g  as it is too thin. 
     Step 7, the silicon substrate between STI  22   a  and  22   b  and above pseudo buried layer goes through single or multiple ion implantation. The above mentioned active region  20  is converted into doped region  23 . The dope concentration should below that of pseudo buried layer  21 . 
     For NPN bipolar transistor, in step 1, silicon substrate  20  is p type. In step 3, n type impurity is implanted, heavily doped n type regions  21   a / 21   b  are formed. In step 6, n type heavily doped pseudo buried layer  21  is formed. In step 7, n type impurity is implanted and n type doped region  23  is formed; 
     For PNP bipolar transistor, in step 1, silicon substrate  20  is n type. In step 3, p type impurity is implanted, heavily doped n type regions  21   a / 21   b  are formed. In step 6, p type heavily doped pseudo buried layer  21  is formed. In step 7, p type impurity is implanted and p type doped region  23  is formed; 
     In above mentioned step 3, ion implant is carried out in high dose, low energy method. The so called high dose, for Phosphorous, Arsenic, Antimony, Titanium, Indium, the ion dose is 1×10 14 ˜1×10 16  per square centimeter. For Boron, Boron Fluoride, the ion dose is 10 13 ˜1×10 16  per square centimeter. The low energy stated above means ion implant energy is less than 30 keV. 
     In above mentioned step 6, the best choice of thermal anneal process is rapid thermal anneal (RTA) process. 
     In above mentioned step 6, ion implant is conducted in medium to low dose. The so called medium to low dose means the ion dosage is less than 1×10 14  atoms per square centimeter (or ions per square centimeter). 
     In conventional shallow trench isolation (STI) process, before shallow trench etch, a thin silicon oxide film is grown on silicon surface followed by a silicon nitride thin film deposition. This means the hard mask on silicon surface before shallow trench etch is consisted of bottom silicon oxide and top silicon nitride dual layers. In present invented shallow trench process, the hard mask before shallow trench etch is consisted of bottom silicon oxide, middle silicon nitride, and top silicon oxide triple layers. 
     In conventional shallow trench isolation (STI) process, only a liner oxide of thickness around 150 A is grown at sidewall and bottom of shallow trench before shallow trench fill in. In STI process of present invention, a liner oxide is grown at sidewall and bottom of shallow trench before shallow trench fill in, followed by deposition of a thin silicon oxide layer, then an etch back is performed and an oxide spacer is formed on STI sidewall together with some oxide remain on STI bottom. The thickness of spacer and bottom oxide is much thicker than that of liner oxide, thus it can be used to stop ion penetration and protect the active region. 
     In above mentioned step 6, after thermal anneal process, it is possible that two high doped regions  21   a / 21   b  still can not link between STI  22   a  and  22   b  through lateral diffusion, instead they are two separate regions. For such circumstance, an improvement to collector of bipolar transistor is give by this invention. In above mentioned step 1, partial or full hard mask  30  on top of silicon substrate  20  between STI  20   a / 20   b  are removed by litho and etch process. In above mentioned step 3, silicon substrate  20  below had mask  30  and between STI  20   a / 20   b  is doped with ion impurity through heavy dose high energy ion implantation process. The so called high energy is, ion implant energy is above 30 keV, the higher projection is then obtained. Finally three doped regions exist in silicon substrate  20 . It is the best that the three doped region have same depth. After such improvement, the three doped region can link together and form pseudo buried layer  21  through lateral diffusion after step 6 high temperature thermal anneal. 
     As to when to use this improved approach, it can be decided by TCAD simulation after detail manufacturing process is confirmed. TCAD simulation is first carried out with basic process (shown in  FIG. 3   a ˜ FIG. 3   b , and  FIG. 2 ). If simulation indicates two heavily doped region  21   a  and  21   b  can not merge after high temperature anneal, then it is necessary to adopt one of the improved approach or a combination of improved approaches. 
     Refer to  FIG. 4 , according to TCAD simulation of present invented bipolar transistor, the p type impurity across cross section A-A (collector buried layer) of  FIG. 2  has a lowest concentration below base. Thus the up diffusion of the impurity to collector is low. It will not affect the breakdown voltage of collector to base of the bipolar transistor. Also, pseudo buried layer is with high dose low energy, the dopant concentration inside pseudo buried layer is high but the junction area is small, the junction capacitance of buried layer to substrate is low. 
     In present invention, the collector buried layer is picked up by a deep contact hole. The contact holes etch through two STI structures at both sides of active region then fill the hole with conduction material.