Abstract:
An apparatus having one or more lookup tables and a decoder is disclosed. The lookup tables are configured to store a plurality of sets of values of log likelihood ratios. The decoder is configured to (i) receive a codeword read from a memory, (ii) receive an initial one of the sets from the lookup tables and (iii) generate read data by decoding the codeword based on the values.

Description:
This application relates to U.S. Provisional Application No. 61/909,529, filed Nov. 27, 2013, which is hereby incorporated by reference in its entirety. 
     FIELD OF THE INVENTION 
     The invention relates to soft decoding generally and, more particularly, to a method and/or apparatus for implementing decoding with log likelihood ratios stored in a controller. 
     BACKGROUND 
     Raw bit error rates of NAND flash memory are becoming poorer due to aggressive process scaling. To maintain the same level of reliability, conventional solid-state drive controllers are adopting error correction codes with soft decoding capability, such as low density parity check codes. The low density parity check codes provide good error correction by using soft inputs to aid in decoding decisions. The soft inputs are normally in the form of log likelihood ratio values. Since conventional flash devices do not provide soft decision values, the solid-state drive controllers have no natural values to utilize. 
     SUMMARY 
     The invention concerns an apparatus having one or more lookup tables and a decoder. The lookup tables are configured to store a plurality of sets of values of log likelihood ratios. The decoder is configured to (i) receive a codeword read from a memory, (ii) receive an initial one of the sets from the lookup tables and (iii) generate read data by decoding the codeword based on the values. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       Embodiments of the invention will be apparent from the following detailed description and the appended claims and drawings in which: 
         FIG. 1  is a block diagram of an apparatus; 
         FIG. 2  is a block diagram of a controller circuit in accordance with an embodiment of the invention; 
         FIG. 3  is a flow diagram of a read error recovery of a codeword; 
         FIG. 4  is a flow diagram of a soft decision decode; 
         FIG. 5  is a diagram of charge-state distributions with a single read voltage; 
         FIG. 6  is a diagram of the charge-state distributions with two read voltages; 
         FIG. 7  is a diagram of the example charge-state distributions with three read voltages; 
         FIG. 8  is a diagram of the example charge-state distributions with seven read voltages; 
         FIG. 9  is a set of tables of the log likelihood ratio values for one or four reads; 
         FIG. 10  is a set of tables of the log likelihood ratio values for five and six reads; and 
         FIG. 11  is a table of the log likelihood ratio values for seven reads. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Embodiments of the invention include providing decoding with log likelihood ratio values stored in a controller that may (i) operate independently of flash cell voltage distributions, (ii) decode with different log likelihood ratio values for different number of retry reads, (iii) operate independently of channel distribution properties, (iv) have low complexity, (v) be suitable for firmware implementation and/or (vi) be implemented as one or more integrated circuits. 
     Embodiments of the invention provide one or more lookup tables (e.g., LUTS) in a solid-state drive (e.g., SSD) controller. The lookup tables are generally populated with decoding parameters (e.g., log likelihood ratio (e.g., LLR) values) suitable for use in a soft-decoder. The parameters in the lookup tables are predetermined in simulations or test scenarios. Each value corresponds to a number of reads and/or retry reads, patterns resulting from the reads and/or retry reads, a number of previously failed decoding attempts and the page that is being accessed. 
     Although cell voltages in flash devices are continuous, flash devices only provide binary sequences (e.g., hard decisions) after each read operation. When soft decoding techniques are used for error correction, the hard decisions are converted into the decoding parameters fed into the decoder operation. The decoding parameters are associated with a single read or multiple reads. The multiple reads are performed with varying read voltages to obtain more information from the flash devices, which results in better quality of the decoding parameters. 
     Referring to  FIG. 1 , a block diagram of an example implementation of an apparatus  90  is shown. The apparatus (or circuit or device or integrated circuit)  90  implements a computer having a nonvolatile memory circuit. The apparatus  90  generally comprises a block (or circuit)  92 , a block (or circuit)  94  and a block (or circuit)  100 . The circuits  94  and  100  form a drive (or device)  102 . The circuits  92  to  102  may represent modules and/or blocks that may be implemented as hardware, software, a combination of hardware and software, or other implementations. 
     One or more signals (e.g., HOSTIO) are exchanged between the circuit  92  and the circuit  100 . The host input/output signal HOSTIO generally includes, but is not limited to, a logical address component used to access data in the circuit  102 , a host command component that controls the circuit  102 , a write data component that transfers write data from the circuit  92  to the circuit  100  and a read data component that transfers error corrected read data from the circuit  100  to the circuit  92 . One or more signals (e.g., NVMIO) are exchanged between the circuit  100  and the circuit  94 . The nonvolatile memory input/output signal NVMIO generally includes, but is not limited to, a physical address component used to access data in the circuit  94 , a memory command component that controls the circuit  94  (e.g., read or write commands), a write codeword component that carries error correction coded and cyclical redundancy check protected write codewords written from the circuit  100  into the circuit  94  and a read codeword component that carries the error correction coded codewords read from the circuit  94  to the circuit  100 . 
     The circuit  92  is shown implemented as a host circuit. The circuit  92  is generally operational to read and write data to and from the circuit  94  via the circuit  100 . When reading or writing, the circuit  92  transfers a logical address value in the signal HOSTIO to identify which set of data is to be written or to be read from the circuit  94 . The address generally spans a logical address range of the circuit  102 . The logical address can address individual data units, such as SATA (e.g., serial-ATA) sectors. 
     The circuit  94  is shown implementing one or more nonvolatile memory circuits (or devices). According to various embodiments, the circuit  94  comprises one or more nonvolatile semiconductor devices. The circuit  94  is generally operational to store data in a nonvolatile condition. When data is read from the circuit  94 , the circuit  94  accesses a set of data (e.g., multiple bits) identified by the address (e.g., a physical address) in the signal NVMIO. The address generally spans a physical address range of the circuit  94 . 
     In some embodiments, the circuit  94  may be implemented as a single-level cell (e.g., SLC) type circuit. A single-level cell type circuit generally stores a single bit per memory cell (e.g., a logical 0 or 1). In other embodiments, the circuit  94  may be implemented as a multi-level cell type circuit. A multi-level cell type circuit is capable of storing multiple (e.g., two) bits per memory cell (e.g., logical 00, 01, 10 or 11). In still other embodiments, the circuit  94  may implement a triple-level cell type circuit. A triple-level cell circuit stores multiple (e.g., three) bits per memory cell (e.g., a logical 000, 001, 010, 011, 100, 101, 110 or 111). A four-level cell type circuit may also be implemented. The examples provided are based on two bits per cell type devices and may be applied to all other types of nonvolatile memory. 
     Data within the circuit  94  is generally organized in a hierarchy of units. A block is a smallest quantum of erasing. A page is a smallest quantum of writing. A codeword (or read unit or Epage or ECC-page) is a smallest quantum of reading and error correction. Each block includes an integer number of pages. Each page includes an integer number of codewords. 
     The circuit  100  is shown implementing a controller circuit. The circuit  100  is generally operational to control reading to and writing from the circuit  94 . The circuit  100  includes an ability to decode the read codewords received from the circuit  94 . The resulting decoded data is presented to the circuit  92  via the signal HOSTIO and/or re-encoded and written back into the circuit  94  via the signal NVMIO. The circuit  100  comprises one or more integrated circuits (or chips or die) implementing the controller of one or more solid-state drives, embedded storage, or other suitable control applications. 
     As part of the decoding, the circuit  100  looks up decoding parameters (e.g., the log likelihood ratio values) stored in one or more internal tables. The decoding parameters are used as part of an iterative decoding procedure that attempts to correct any errors that may be present in the codewords. The decoding parameters generally inform the decoding procedure of a reliability for each respective bit of the codewords. 
     The circuit  102  is shown implementing a solid-state drive. The circuit  102  is generally operational to store data generated by the circuit  92  and return the data to the circuit  92 . According to various embodiments, the circuit  102  comprises one or more: nonvolatile semiconductor devices, such as NAND Flash devices, phase change memory (e.g., PCM) devices, or resistive RAM (e.g., ReRAM) devices; portions of a solid-state drive having one or more nonvolatile devices; and any other volatile or nonvolatile storage media. The circuit  102  is generally operational to store data in a nonvolatile condition. 
     Referring to  FIG. 2 , a block diagram of an example implementation of the circuit  100  is shown in accordance with an embodiment of the invention. The circuit  100  generally comprises a block (or circuit)  110 , a block (or circuit)  112 , a block (or circuit)  114 , a block (or circuit)  116 , a block (or circuit)  118  and a block (or circuit)  120 . The circuits  110  to  120  may represent modules and/or blocks that may be implemented as hardware, software, a combination of hardware and software, or other implementations. 
     The circuit  110  is shown implemented as a host interface circuit. The circuit  110  is operational to provide communication with the circuit  92  via the signal HOSTIO. Other signals may be implemented between the circuits  92  and  110  to meet the criteria of a particular application. 
     The circuit  112  is shown implemented as a nonvolatile memory (e.g., flash) interface circuit. The circuit  112  is operational to provide communication with the circuit  94  via the signal NVMIO. Other signals may be implemented between the circuits  94  and  110  to meet the criteria of a particular application. 
     The circuit  114  is shown implemented as a buffer circuit. The circuit  114  is operational to buffer codewords received from the circuit  94  via the circuit  112 . The circuit  114  is also operational to buffer decoding parameters generated by the circuit  116 . The read codewords and the decoding parameters are presented from the circuit  114  to the circuit  118 . 
     The circuit  116  is shown implemented as a soft-decision table circuit. The circuit  116  is operational to store and present decoding parameters used in a soft-decision decoding performed by the circuit  118 . The decoding parameters are presented by the circuit  116  to the circuit  114  for buffering and/or, in other embodiments, directly to circuit  118 . A hardware or firmware unit within the circuit  116  processes the sequences of bits received from the circuit  94  into hard decision patterns. The values are generally stored within the circuit  116  as one or more lookup tables. The lookup tables are indexed into groups based on the number of reads of a current codeword. Each group has several sets of values indexed by a sequence of decoding attempts. Each set is indexed by the binary hard decision patterns for each read of each bit in the current codeword. 
     The circuit  118  is shown implemented as a soft-decision decoder circuit. In some embodiments, the circuit  118  is implemented as one or more low density parity check decoder circuits. The circuit  118  is operational to perform both hard-decision (e.g., HD) decoding and soft-decision (e.g., SD) decoding of the codewords received from the circuit  114 . The soft-decision decoding generally utilizes the decoding parameters presented by the circuit  116 . 
     The circuit  120  is shown implemented as a processor circuit. The circuit  120  is operational to command and/or assist with the multiple read/write requests and to control one or more reference voltages used in the circuit  94  to read the codewords. 
     Referring to  FIG. 3 , a flow diagram of an example method  140  for a read error recovery of a codeword is shown. The method (or process)  140  is implemented by the circuit  100 . The method  140  generally comprises a step (or state)  142 , a step (or state)  144 , a step (or state)  146  and a step (or state)  148 . The steps  142  to  148  may represent modules and/or blocks that may be implemented as hardware, software, a combination of hardware and software, or other implementations. The sequence of the steps is shown as a representative example. Other step orders may be implemented to meet the criteria of a particular application. 
     In the step  142 , a codeword is read from the circuit  94  by the circuit  100  and buffered in the circuit  114 . A hard-decision decoding is performed by the circuit  118  in the step  144 . If the hard-decision decoding converges per the step  146 , the decoded data is presented in the signal HOSTIO from the circuit  110  to the circuit  92 . If the hard-decision decoding does not converge per the step  146 , a soft-decision decoding process is performed by at least one or more of the circuits  114 ,  116 ,  118  and  120  in the step  148 . The soft-decision decoding generally utilized the log likelihood values stored in the tables in the circuit  116 . 
     Referring to  FIG. 4 , a flow diagram of an example implementation of the soft decision decode step  148  is shown. The step  148  is implemented by the circuit  100 . The step  148  generally comprises a step (or state)  160 , a step (or state)  162 , a step (or state)  164 , a step (or state)  166 , a step (or state)  168 , a step (or state)  170 , a step (or state)  172 , a step (or state)  174  and a step (or state)  176 . The steps  160  to  176  may represent modules and/or blocks that may be implemented as hardware, software, a combination of hardware and software, or other implementations. The sequence of the steps is shown as a representative example. Other step orders may be implemented to meet the criteria of a particular application. 
     In the step  160 , the circuit  116  presents a set of normal log likelihood ratio (e.g., NLLR) values as the log likelihood ratio values for a current read of a current codeword. The set is one of many sets in an initial set group stored in the tables of the circuit  116 . The circuit  118  uses the log likelihood ratio values in a soft decision decoding of the current codeword. If the decoding converges, the step  148  is ended and the decoded data is presented to the circuit  92  in the signal HOSTIO. 
     In situations where the decoding does not converge, the circuits  116  and  118  will use a set of compensated log likelihood ratio (e.g., CLLR) values in an attempt to decode the current codeword. If the decoding converges with the compensated log likelihood ratio values, the decoded data is presented to the circuit  92  in the signal HOSTIO. 
     If the decoding does not converge, a check is performed by the circuit  100  to decide if additional sets of the compensated log likelihood ratio values are available in the tables within the circuit  116  for the current read. If one or more additional compensated sets are available, the circuit  116  presents a next compensated set to the circuit  118  in the step  170 . The step  148  subsequently returns to the step  164  to decode the current codeword again using the next compensated set of log likelihood ratio values. A loop around the step  164  to the step  170  and back again generally continues until either a convergence is reached in the step  166  or all of the compensated sets in the group have been tried per the step  168 . 
     If decoding has not been successful after utilizing all of the log likelihood ratio values in all of the sets in the initial group, the circuit  100  checks to see of a read retry is an available option. If more retry reads are available in the attempt to decode the current codeword, the circuit  100  requests a read retry in the step  174 . The circuit  120  may adjust the read voltage used in the circuit  94  and start the decoding step  148  again. 
     Each retry read results in the circuit  116  using a different group of log likelihood ratio values in the lookup tables. A loop around the steps  160  to  174  and back to the step  160  continues until either the decoding converges (e.g., in the steps  162  or  166 ) or all available retry reads have been exhausted per the step  172 . If decoding has not been successful after a last retry read has been made and a last compensated set has been used in the decoding, the circuit  100  declares a decoding failure in the step  176  and the step  148  ends. 
     Referring to  FIG. 5 , a diagram of example charge-state distributions in two bits per cell type nonvolatile memory cells with a single read voltage is shown. Each cell can be programmed into one of multiple (e.g., four) states  200 - 206 . Each of the multiple states is interpreted as multiple (e.g., 2) bits. Half the bits are considered part of an upper page. The other half of the bits are considered part of a lower page. 
     The four charge-state distributions  200 - 206  from left to right are mapped to states “11”, “01”, “00” and “10”, respectively. By reading the cell with a single read voltage (e.g., V0), the voltage axis (e.g., x-axis V) is divided into two regions (or areas) A0 and A1. A read using the voltage V0 that senses a cell to be programmed in the region A0 (e.g., state  200  or  202 ) results in a decision that the lower page of the cell stores a binary one value. A read using the voltage V0 that senses the cell to be in the region A1 (e.g., state  204  or  206 ) results in a decision that the lower page of the cell stores a binary zero value. Therefore, possible decision patterns [1, 0] exist on the lower page for decision regions [A0, A1]. An additional read and decision are used to decide what value is stored in the upper page. 
     Referring to  FIG. 6 , a diagram of the example charge-state distributions with two read voltages is shown. By reading the cell with two read voltages (e.g., V0 and V1), the voltage axis is divided into three regions (or areas) A0, A1 and A2. A read at both voltages V0 and V1 that sense the cell to be in the region A0 results in a decision that the lower page of the cell stores a binary one value. A read at both voltages V0 and V1 that sense the cell to be in the region A1 results in a decision that the lower page of the cell stores either a binary zero value (e.g., a program state sensed using V1) or a binary one value (e.g., an erased state sensed using V0). A read at both voltages V0 and V1 that sense the cell to be in the region A2 results in a decision that the lower page of the cell stores a binary zero value. Therefore, possible decision patterns [11, 01, 00] exist for decision regions [A0, A1, A2]. Additional reads and decisions are used to determine what value is stored in the upper page. 
     Referring to  FIG. 7 , a diagram of the example charge-state distributions with three read voltages is shown. By reading the cell with three read voltages (e.g., V0, V1 and V2), the voltage axis is divided into four regions (or areas) A0, A1, A2 and A3. The possible decision patterns [111, 011, 001, 000] exist for decision regions [A0, A1, A2, A3]. Generally, the number of decision patterns is N+1 for N reads of the lower page. For the upper page (with conventional Gray coding), a maximum of 2×N hard decision patterns exist, since a pair of read voltages is used for each read. 
     Referring to  FIG. 8 , a diagram of the example charge-state distributions with seven read voltages is shown.  FIG. 8  shows reads on an upper page of a multi-level cell. For multi-level cell channels, the log likelihood ratio values are a function of the four charge-state distributions (e.g., means and variances) and the read reference voltages for reading. 
     Referring to  FIG. 9 , example tables of the log likelihood ratio values for one to four reads are shown. Table 1 illustrates a set  210  of normal log likelihood ratio (e.g., NLLR) values and two sets  212 - 214  of compensated log likelihood ratio (e.g., CLLR1 and CLLR2) values for a single read. The three sets  210 - 214  form an initial group  216  of values stored in the circuit  116 . Based on (i) the decision pattern [1, 0] and page (e.g., least significant bit page or most significant bit page) of a hard read and (ii) the current set being used to decode (e.g., NLLR, CLLR1 or CLLR2), the circuit  116  indexes a particular log likelihood ratio value from Table I and presents the value. The log likelihood ratio values corresponding to decision pattern 1 have positive values. The log likelihood ratio vales corresponding to decision pattern 0 have negative values. 
     Table 2 illustrates another set of normal log likelihood ratio values and two additional sets of compensated log likelihood ratio values for two reads (e.g., a read and a retry read). The three sets for another group  218  of values used stored in the circuit  116 . Based on (i) the decision pattern [11, 01, 00] and page (e.g., column) of hard reads and (ii) the current set being used to decode (e.g., row), the circuit  116  indexes a particular log likelihood ratio value from Table 2 and presents the value. The log likelihood ratio values corresponding to decision patterns having mostly 1 have positive values. The log likelihood ratio vales corresponding to decision patters having mostly 0 have negative values. 
     Table 3 illustrates a set of normal log likelihood ratio values and two more sets of compensated log likelihood ratio values for three reads (e.g., a read and two retry reads). The three sets form another group  220  of values used stored in the circuit  116 . 
     Table 4 illustrates a set of normal log likelihood ratio values and two more sets of compensated log likelihood ratio values for four reads (e.g., a read and three retry reads). The three sets for another group of values are stored in the circuit  116 . 
     Referring to  FIG. 10 , example tables of the log likelihood ratio values for five and six reads are shown. Table 5 and Table 6 are arranged in a manner similar to Tables 1-4. Table 5 is illustrated with a normal set NLLR and two compensated sets CLLR1-CLLR2. Table 6 shows the normal set NLLR and five compensated sets CLLR1-CLLR5. 
     Referring to  FIG. 11 , an example table of the log likelihood ratio values for seven reads is shown. Table 7 is arranged in a manner similar to Tables 1-6. Table 7 is illustrated with the normal set NLLR and six compensated sets CLLR1-CLLR6. 
     After each read operation of NAND flash, the read back data is a binary sequence. The binary sequence, together with the sequences of previous reads, forms a sequence of the hard decision patterns. The values in the lookup tables in the circuit  116  are calculated for all possible hard decision patterns (including invalid patterns). The log likelihood ratio values shown in Tables 1-7 are examples that are determined by analysis or experiments. An initial row (or set) of each table contains the normal log likelihood ratio values. The remaining rows (or sets) of each table contains the compensated log likelihood ratio values, which generally have different values from the normal set. The different values for the compensated sets are determined with the consideration of adjusting the normal sets for mis-estimating of read voltages and/or for accommodating variations of means/variances of cell voltage distributions. 
     Depending on the amount of available memory and the cases specified to be covered, the number of compensated sets can be different after each retry read. For the examples shown in Tables 1-7, two compensated sets are created for one to five reads, five CLLR sets for six reads, and six compensated sets for seven reads. 
     Estimating cell voltage (or charge-state) distributions (e.g., means/variances) is a difficult job for solid-state drive controllers, especially for estimating an erase state. Therefore, the circuit  100  operates independently of the estimations of the means/variances, making the circuit  100  simpler and more robust. 
     For a different number of retry reads, a different number of log likelihood ratio values correspond to the hard decision patterns. So for different numbers of retry reads, different groups (e.g., different tables) are accessed. Instead of calculating the log likelihood ratio values online (based on the estimates of the means/variances), the circuit  100  uses a group of log likelihood ratio value sets for each number of retry reads. The log likelihood ratio values stored in the lookup tables are pre-defined by either analysis or experiments. A resulting advantage is a lack of online calculations, and so the circuit  100  is suitable for high speed soft retires. Each group of values (for a particular number of retry reads) includes a set of nominal values and several sets of compensated values. The nominal lookup table values are used for the initial soft decoding attempt. If decoding fails, the rest of the compensated lookup table values will be tried, one by one, for decoding. 
     The circuit  100  operates independently of knowledge of a channel distribution. The channel distributions are not assumed to be Gaussian, which is a realistic situation for high program/erase cycles. In various embodiments, the lookup tables can be measured from flash data processing. In other embodiments, the lookup tables can be estimated from simulations. Use of the tables generally involves low complexity and is suitable for firmware implementations. 
     The functions performed by the diagrams of  FIGS. 1-4 and 9-11  may be implemented using one or more of a conventional general purpose processor, digital computer, microprocessor, microcontroller, RISC (reduced instruction set computer) processor, CISC (complex instruction set computer) processor, SIMD (single instruction multiple data) processor, signal processor, central processing unit (CPU), arithmetic logic unit (ALU), video digital signal processor (VDSP) and/or similar computational machines, programmed according to the teachings of the specification, as will be apparent to those skilled in the relevant art(s). Appropriate software, firmware, coding, routines, instructions, opcodes, microcode, and/or program modules may readily be prepared by skilled programmers based on the teachings of the disclosure, as will also be apparent to those skilled in the relevant art(s). The software is generally executed from a medium or several media by one or more of the processors of the machine implementation. 
     The invention may also be implemented by the preparation of ASICs (application specific integrated circuits), Platform ASICs, FPGAs (field programmable gate arrays), PLDs (programmable logic devices), CPLDs (complex programmable logic devices), sea-of-gates, RFICs (radio frequency integrated circuits), ASSPs (application specific standard products), one or more monolithic integrated circuits, one or more chips or die arranged as flip-chip modules and/or multi-chip modules or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s). 
     The invention thus may also include a computer product which may be a storage medium or media and/or a transmission medium or media including instructions which may be used to program a machine to perform one or more processes or methods in accordance with the invention. Execution of instructions contained in the computer product by the machine, along with operations of surrounding circuitry, may transform input data into one or more files on the storage medium and/or one or more output signals representative of a physical object or substance, such as an audio and/or visual depiction. The storage medium may include, but is not limited to, any type of disk including floppy disk, hard drive, magnetic disk, optical disk, CD-ROM, DVD and magneto-optical disks and circuits such as ROMs (read-only memories), RAMS (random access memories), EPROMs (erasable programmable ROMs), EEPROMs (electrically erasable programmable ROMs), UVPROM (ultra-violet erasable programmable ROMs), Flash memory, magnetic cards, optical cards, and/or any type of media suitable for storing electronic instructions. 
     The elements of the invention may form part or all of one or more devices, units, components, systems, machines and/or apparatuses. The devices may include, but are not limited to, servers, workstations, storage array controllers, storage systems, personal computers, laptop computers, notebook computers, palm computers, personal digital assistants, portable electronic devices, battery powered devices, set-top boxes, encoders, decoders, transcoders, compressors, decompressors, pre-processors, post-processors, transmitters, receivers, transceivers, cipher circuits, cellular telephones, digital cameras, positioning and/or navigation systems, medical equipment, heads-up displays, wireless devices, audio recording, audio storage and/or audio playback devices, video recording, video storage and/or video playback devices, game platforms, peripherals and/or multi-chip modules. Those skilled in the relevant art(s) would understand that the elements of the invention may be implemented in other types of devices to meet the criteria of a particular application. 
     The terms “may” and “generally” when used herein in conjunction with “is(are)” and verbs are meant to communicate the intention that the description is exemplary and believed to be broad enough to encompass both the specific examples presented in the disclosure as well as alternative examples that could be derived based on the disclosure. The terms “may” and “generally” as used herein should not be construed to necessarily imply the desirability or possibility of omitting a corresponding element. 
     While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.