Abstract:
Described are a technique and an apparatus for deskewing data transmitted via a dispersive medium such as a fiber optic link. The relative delays in arrival time for a plurality of bits, propagated in separate channels are measured. The relative delays are used to calculate the wavelength (λ) of one channel and the zero dispersion wavelength (λ 0 ) of the medium. The relative delays in arrival times for the remaining bits in a group of bits are predicted using the measured relative delays, the spacing (δ) between the transmitters and the calculated wavelengths. An adjustable delay for storing data bits is provided in each channel. The relative delays are used to deskew the individual bits.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to data communications in general and more particularly to a method and an apparatus for deskewing wavelength division multiplexed data which is transmitted through a dispersive medium. 
     2. Prior Art 
     The proliferation of computers and other data handling devices have created a need for more effective and efficient communications systems for interconnecting the computers and/or other data handling devices. The wavelength division multiplexing (WDM) system has been used to interconnect computers and other data handling devices. The WDM communications systems are attractive in that they can provide parallel data transmission on a single transmission link such as a single wire and/or single optical fiber. 
     In a conventional optical WDM communications system, the individual bits of a group of bits, e.g., a byte, are applied to different encoders in a set of optical encoders. The encoders modulate each bit or channel at a different optical frequency or wavelength. The modulated optical signals are merged into a single beam which is transmitted through a single fiber to a receiving location. At the receiving location, the single beam is separated into its bit signal components to re-establish the originally transmitted byte of data. Optical filters and/or gratings are used to separate the beam into its component parts. 
     One known problem in using WDM in an optical fiber system is that the respective bits of a byte of data arrive at different times at the receiver. This phenomenon is referred to as bit skew. A probable reason for bit skew is that an optical fiber is a dispersive medium which tends to delay optical signals at different rates. Thus, optical signals at some frequencies are delayed more than optical signals at other frequencies. Since a byte of WDM data contains signals with different frequencies or wavelengths, the effect of dispersion is to delay some bits in the byte more than others. 
     For relatively low transmission rate and/or relatively short length of transmission link, the amount of bit skew may fall within acceptable limits. However, for relatively high transmission rate and/or long transmission links, the bit skew may become so large that bits in one byte may at least partially overlap with bits in another byte. 
     Even for relatively long transmission links, if the exact length of the transmission link is known, the retardation or delay of a bit transmitted at a particular wavelength can be readily calculated. However, the exact length of transmission links in practical commercial communications systems is influenced by several conditions and as such is not normally known. For example, the exact length of a transmission link depends on the manner in which it is installed and will vary from one installation to the next, depending on the installer&#39;s technique. Even if the exact length is known initially, it can change due to changes in temperature or it may change if connectors and/or sections of the fiber must be replaced after installation. 
     Furthermore, it is believed that the bit skew problem is aggravated by drifts in the wavelengths of the lasers which generate the light beams and/or shifts in the group delay curves. 
     The prior art has proposed several techniques for solving the bit skew problem. Among the proposed techniques, perhaps the best technique is the one set forth in U.S. Pat. No. 4,677,618. In the subject patent, the time delays between two different wavelength (sub-channels) are measured. The measured time delays and known information about the fiber are used in an algorithm which predicts the arrival time of bits in the other sub-channels. The prediction scheme requires that the central wavelengths of the transmitting lasers and the fiber group delay curve must be stable. Any unexpected drift of the laser wavelengths or a shift of the fiber group delay may cause the predicted arrival times to be incorrect. As a result, the sampling time would not be at the bit center and the probability of errors would increase. 
     SUMMARY OF THE INVENTION 
     It is a general object of the invention to provide a more efficient communications system for transmitting information between communicating units. 
     It is a more specific object to provide a communications system in which bit skew caused by drifts in the laser wavelengths and/or shifts in the group delay curve and/or changes in the fiber lengths are corrected. 
     It is still another object of the present invention to provide a communications system in which bit skew is corrected without any prior knowledge of the fiber characteristics. 
     The above and other objects are achieved by measuring the relative delays between a plurality of bits in parallel channels at a receiving location. The wavelengths (λ) for at least one of the channels and the zero dispersion wavelength of the fiber (λ 0 ) are determined from these measurements. These wavelengths, relative delays and the wavelength spacing (δ) between the light emitting devices which transmit the bits are used to predict the relative delays for the other bits in the group. The relative delays are used to control adjustable delay devices located in each channel so that the bits for the transmitted group or byte are properly (linearly) aligned in time. 
     In particular, the skew alignment process includes the steps of: 
     A. Measuring the time delays between the bit clocks in the first four sub-channels, Δt 1 ,2, Δt 1 ,3 and Δt 1 ,4. 
     B. Calculating λ 1  from the quadratic equation below ##EQU1## where a=2(3Δt 1 ,3 -Δt 1 ,4 -3Δt 1 ,2) 
     b=4δ(-4Δt 1 ,3 +Δt 1 ,4 +5Δt 1 ,2) 
     c=δ 2  (39Δt 1 ,3 -7Δt 1 ,4 -57Δt 1 ,2) 
     The positive square root corresponds to wavelengths greater than λ 0 , and the negative square root corresponds to wavelengths smaller than λ 0 . δ is the wavelength spacing between the subchannels. 
     C. Calculating λ 0  from the equation below. ##EQU2## 
     D. Calculating the delay times for the other bits from the equation below using the measured Δt 1 ,2, the channel number, m, and the channel spacing, δ. ##EQU3## 
     E. Setting the adjustable delay in each channel an amount equal to its corresponding measured or calculated delay. 
     The foregoing features and advantages of the invention will be more fully described in the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a functional block diagram of a system within which the present invention is practiced. 
     FIG. 2 is a detailed diagram of the wavelength division multiplexing and demultiplexing sections of the system shown in FIG. 1. 
     FIG. 3 is a block diagram of an apparatus used to implement the invention. 
     FIG. 4 is a graphic representation showing the effects of frequency-related dispersion in a dispersive medium. 
     FIG. 5 is a flow chart of the algorithm which generates the respective channel delays. 
     FIG. 6 shows a block diagram of a circuit arrangement for an adjustment delay. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows a functional block diagram of a system embodying the teachings of the present invention. The system includes a source system 10 which can be any kind of digital processing system or device capable of providing digital data which is transmitted on parallel bus 12 to a wavelength division multiplexing circuit 14. For example, bus 12 is 8-bit-wide (eight data channels). However, busses of any widths can be used. The only limitation is that a wavelength division multiplexing circuit must be capable of handling or processing all data channels in the selected bus. The function of the wavelength division multiplexing circuit 14 is to encode each bit optically, combine them into an optical bit stream with a single multi-wavelength signal which is transmitted through medium 16 (such as an optical fiber) with frequency-related dispersion characteristics. The signal is received by the wavelength division demultiplexing circuit 18 which separates the multi-wavelength signal into parallel signals onto bus 20. Each of the signals on bus 20 has different wavelengths. The bit signals on bus 20 are transmitted to bit skew correction system 22. As will be described in detail hereinafter, the function of the bit skew correction system 22 is to deskew (that is, align) the bits from bus 20 into a parallel data stream which are transmitted over bus 23 to utilization system 25. 
     FIG. 2 shows details of the wavelength division multiplexing circuit 14 and wavelength division demultiplexing circuit 18. The bit stream in each channel of parallel bus 12 is used to modulate optical devices 24A through 24H. Each of the optical devices generates an optical signal at a predetermined optical frequency or wavelength. The optical signals are transmitted by optical fibers 36A through 36H to optical combiner 26. The optical combiner 26 combines or merges the individual optical signals to form a composite (multi-wavelength) signal which is transmitted through optical fiber 16 to an optical grating 28 at a receiving system 27. The optical grating 28 separates the received signal into its components and sends each of the components to separate optical detectors 30A through 30H. The electrical bit signals produced by the optical detectors 30A through 30H are aligned via the system to be described hereinafter and transmitted to the utilization system 25. 
     Still referring to FIG. 2, the optical devices 24A through 24H are conventional devices which can be obtained from several different manufacturers. The details of these devices will not be discussed any further. Suffice it to say that optical devices such as those described in U.S. Pat. No. 4,677,618 can be used in the embodiment of the present invention. The subject patent is incorporated herein by reference. In addition, the wavelength division multiplexer and the wavelength division demultiplexer are conventional devices such as those described in the referenced patent. It should also be noted that the functions performed by the optical combiner or multiplexer 26 and the optical grating or demodulator 28 can be performed using the same component with appropriate changes in beam direction. 
     FIG. 4 shows the arrival of three bytes of data at the receiver 27 (FIG. 2) for a system operating at its maximum link length for a particular bit error rate. The system would be designed to operate at the maximum length by choosing the minimum time between bytes to be limited by the dispersion in subchannel N since that subchannel has the most dispersion and, thus, the greatest intersymbol interference. This figure is also helpful in identifying the problem which the present invention solves. The problem is bit-skew caused by the variation of optical group velocity versus wavelength. As a result, even though the bits of a byte or any other grouping are transmitted simultaneously from a source system the constituent bits are skewed or shifted relative to one another. 
     Still referring to FIG. 4, the sub-channels at the receiver are plotted on the vertical coordinate while the relative delay are plotted on the horizontal axis of the graph. The symbol (δ) represents the spacing between the optical signal generating devices 24A and 24B (FIG. 2) at the transmitter section of system. For purposes of the present invention, this spacing is assumed to be constant. Finally, Δ t  represents the relative delay between bits in a particular byte. Thus, Δt 1 ,2 represents the delay between bits 1 and 2 of a byte. Similarly, Δt 1 ,3 represents the relative delay between bits 1 and 3 and so forth. As will be described subsequently, the relative delay between respective bits of a byte, the spacing δ between channels and other relevant characteristics of the group delay curve for each byte are used in correcting the skew associated with a particular byte of transmitted data. 
     As can be seen in FIG. 4, the bits (depicted by triangular symbols) for a particular byte such as byte A or byte B or byte C are arranged on a curve relative to each other. Even though the individual bits can be easily detected, it is very difficult to tell which bit goes with which byte. Ideally, each byte should be parallel with the vertical axis of the graph. If this were the case, then it would be simple to tell (that is, recover) the entire byte at the receiver. However, in the practical system, the bits of a particular byte are skewed relative to one another and the present invention makes the correction in the received data so that all the bits of a particular byte or group are aligned in a straight line. 
     Still referring to FIG. 4, the curves labeled Byte A, B and C may be characterized as group delay curves for (WDM) encoded bytes of data. If this characterization is adopted λ (representing the wavelengths of transmitted signals) is plotted on the vertical axis of the graph while time (t) is plotted on the horizontal axis. A mathematical expression called fiber group delay equation can be written for the curve. The equation is then solved to generate other equations which are used in the below process (steps A through E) to align the bits in a particular byte. The process steps are: 
     A. Measuring the time delays between the bits clocks in the first four sub-channels, Δt 1 ,2, Δt 1 ,3 and Δt 1 ,4. 
     B. Calculating λ 1  from the quadratic equation below ##EQU4## where a=2(3Δt 1 ,3 -Δt 1 ,4 -3Δt 1 ,2) 
     b=4δ(-4Δt 1 ,3 +Δt 1 ,4 +5Δt 1 ,2) 
     c=δ 2  (39Δt 1 ,3 -7Δt 1 ,4 -57Δt 1 ,2) 
     The positive square root corresponds to wavelengths greater than λ 0 , and the negative square root corresponds to wavelengths smaller than λ 0 . δ is the wavelength spacing between the sub-channels. 
     C. Calculating λ 0  from below. ##EQU5## 
     D. Calculating the delay times for the other bits from the equation below using the measured Δt 1 ,2, the channel number, m, and the channel spacing, δ. ##EQU6## 
     E. Setting the adjustable delay in each channel an amount equal to its corresponding measured or calculated delay. 
     The process is based on the group delay, τ, found by integrating the dispersion equation given by Jeunhomme &#34;Single Mode Fiber Optics, Principles and Applications&#34;, New York, Marcel Decker, 1983, p. 113. 
     The group delay, τ, is 
     
         τ=τ.sub.0 +S.sub.0 λ.sub.0 λ-S.sub.0 λ.sub.0.sup.2 lnλ                           (1) 
    
     where τ 0  is a constant, λ 0  is the zero-dispersion wavelength and S 0  is the value of the dispersion slope at λ 0 . The delay between sub-channels l and m is ##EQU7## where δ is the wavelength spacing between the sub-channels. Since Δt=LΔτ, ##EQU8## This removes the unknown, L, from the equations. Divide numerator and denominator by S 0  λ 0 . ##EQU9## Since there are still two unknowns, λ 0  and λ 1 , we need two equations in order to solve for λ 1 . ##EQU10## Solve both equations for λ 0 . ##EQU11## Combine these two equations: ##EQU12## Cross multiply. ##EQU13## Combine similar logarithmic terms: ##EQU14## The series expansion for ln(l+z) is ##EQU15## if |z|≦1 and z≠-1. These conditions will be true for all of our choices of λ 1  and δ. Using a 4-term expansion: ##EQU16## Group terms by decreasing order of λ 1 . 
     
         λ.sub.1.sup.3 (36P-24Q+24Q-72-36P+72)+λ.sub.1.sup.2 δ(-18P+12Q-24Q+72+54P31 108) +λ.sub.1 δ.sup.2 (12P-8Q+32Q-96-108P+216)+δ.sup.3 (-9P+6Q-48Q+144+243P+486)=0(14) 
    
     Since the coefficient of λ 1   3  is zero, (14) reduces to a quadratic equation in λ 1 . Dividing by δ, 
     
         λ.sub.1.sup.2 (36P-12Q-36)+λ.sub.1 δ(-96P+24Q+120)+δ.sup.2 (234P-42Q-342)=0      (15) 
    
     Divide each term by 6: 
     
         2(3P-Q-3)λ.sub.1.sup.2 +4δ(-4P+Q+5)λ.sub.1 +δ.sup.2 (39P-7Q-57)=0                              (16) 
    
     Replace P with Δt 1 ,3 /Δt 1 ,2 and Q with Δt 1 ,4 /Δt 1 ,2. 
     
         2(3Δt.sub.1,3 -Δt.sub.1,4 -3Δt.sub.1,2)λ.sub.1.sup.2 +4δ(-4Δt.sub.1,3 +Δt.sub.1,4 +5Δt.sub.1,2)λ.sub.1 +δ.sup.2 (39 Δt.sub.1,3 -7Δt.sub.1,4 -57Δt.sub.1,2)=0(17) 
    
     FIGS. 3A and 3B show a block diagram of the bit skew correction system 22 (FIG. 1). The individual bit signals in each of the bit channels of bus 20 (FIG. 1) are applied to channel receiver and clock recovery circuit means 66A through 66N. Such circuits are well known in the art and will not be described in detail. Suffice it to say that the channel receiver and clock recovery circuit set forth in the above referenced patent may be used in the present invention. Each of the channel recovery and clock recovery circuit means derives a bit or channel clock signals which are supplied to comparators 61, 63 and 65 via conductors labeled CLOCK 1, CLOCK 2, CLOCK 3 and CLOCK 4. In addition, each of the channel receiver and clock recovery circuits derives bit signals which are delivered to adjustable delay means 72A through 72D. The function of the adjustable delay means 72A through N is to delay the fastest bits in a transmitted byte to provide linear alignment between the bits. The output from the adjustable delay means are fed into the output register 74 from which the aligned data for each byte is delivered to utilization device 25 (FIG. 1). 
     Still referring to FIGS. 3A and 3B, the comparators 61, 63 and 65 compare the phase of the clock signals on channels 2, 3 and 4 with the phase of the clock signal on channel 1. With reference to FIG. 2, device 30A represents channel 1, device 30B represents channel 2 and so forth. Referring again to FIG. 3A, the output signal Δt 1 ,2 represents the delay between clock 1 and 2. Similarly, the delay signal Δt 1 ,3 is the delay between clock 1 and 3. Finally, Δt 1 ,4 is the delay between clock 1 and clock 4. The respective delays are fed into channel delay control means 67 which generates the byte clock signal on conductor 78, delay control signals 70A, 70B, 70C through 70N and a signal called clock for the delay lines. The clock signal is used to gate the adjustable delay means while the delay control signals set the adjustable delay means at a position that reflects the value of the calculated and measured delay. The channel delay control means 67 may be formed from hardware circuits generated from the flow chart set forth in FIG. 5 or the controller may be a computer programmed in accordance with the process steps set forth in said flow chart. 
     In the preferred embodiment of the invention, a microcomputer program according to the flow chart is preferred. With reference to the flow chart, a value for the spacing δ between the laser element 24A through 24H is set 80. A value can be obtained from the manufacturers of the laser devices. The respective delays between selected clock signals are determined (82, 84, 86). In block 88 λ1 is calculated in accordance with equation B. Similarly, λ0 (block 90) is calculated in accordance with equation C. The relative delay Δt 1 ,m for the next channel is calculated (92). In block 94, the calculated delays are used for setting the adjustable channel delay means 72A, 72B, 72C and 72D. From block 94, the program descends into block 96 where it tests to see if the delay for the last channel is calculated. If it is the last channel, the program descends into block 98 where it exits the program. If additional channels remain to be calculated, the program branches back to block 92 to repeat the calculation for that channel. 
     FIG. 6 shows a block diagram of a circuit arrangement for the adjustable delay means. The adjustable delay means includes a selector circuit 102, shift register 100, a common clock line, a select line, a data line and an output line. 
     With reference to FIG. 3B, the output line is connected to register 74. The common clock line is connected to the line labeled Clock for the Delay lines. The data line is connected to the channel receiver and clock recovery circuit means and the select line is connected to one of the delay controls 70A-70D. 
     When the maximum delay expected in a link is less than one bit time, the variable delay is simply a one bit register which is gated on to sample the receiver output at Δt 1 ,m after the channel one is gated into its register. 
     When more than a bit time delay is expected, the design must include storage such as a shift register 100. The algorithm must be expanded to make use of the fact that Δt 1 ,j will be smaller than Δt 1 ,k if and only if the delay of the k th  bit clock beyond the j th  bit clock is more than one bit time. Using this fact, each pair of bit clock delays can be examined, and one bit delay added to all those after the first inversion (smaller rather than larger) of successive bit clock delays. This procedure makes use of the fact that the group delay curve is monotonic on one side of the zero dispersion wavelength. 
     For many links, such complications are not required. But if they are, the variable delay can be realized in several ways. The easiest to visualize is a shift register b×r sections long. Where b is the maximum number of complete bit times of delay expected in the longest link, and is the desired sub-bit time delay resolution. 
     The variable delay also contains a selector circuit 102 such that one particular section of the shift register is coupled to the output, and thus to the output register (FIG. 3B). 
     The delay algorithm output to each individual adjustable delay means or variable delay means sets the selector so that the section of the shift register connected to the output register (FIG. 3B) corresponds to a delay of Δt 1 ,n -Δt 1 ,m for channel m where Δt 1 ,n is the calculated delay on the channel farthest from λ 0 . Thus, the longest delay is for channel 1 which is closest to λ 0  and the shortest delay is for channel n which is farthest from λ 0  . Therefore, the variable delay added to the delay of information in a channel yields a total delay which is equal for all channels. 
     The algorithm was presented such that the delays Δt 1 ,m were calculated since this simplifies the mathematics. If the variable delay illustrated here were used, the algorithm should convert these delays to 
     
         Δt.sub.n,m =Δt.sub.1,n -Δt.sub.1,m 
    
     for simplicity in setting the selector section of the delay. If other types of variable delay are used, this may not be necessary. 
     In the variable delay being described, the clock to the shift registers is r times faster than the channel bit clocks. Each register samples its channel receiver output and holds a pattern corresponding to the channel receiver output bits sampled every time periods for b bits. By connecting the proper sample time (register section) to the output register, the appropriate data bit is selected. It should be noted that other types of delay can be used without departing from the teachings of the present invention. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.