Abstract:
A data output driver device includes a noise detecting unit configured to output a noise detection signal to detect variations of power supply voltage due to noise, and a driver circuit unit configured to drive and output data with the variable driving capability in response to the noise detection signal.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2008-0015207, filed on Feb. 20 2008, in the Korean Intellectual Property Office, which is incorporated herein in its entirety by reference as if set forth in full. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The embodiments described there relate to an output driver, and more particularly, to a data output driver for a semiconductor integrated circuit (IC). 
         [0004]    2. Related Art 
         [0005]    Generally, a data output driver includes buffers IV 1  and IV 2 , a first transistor M 1  whose source is connected to an external voltage (VDD) terminal, and a second transistor M 2  whose source is connected to a ground voltage (VSS) terminal, as shown in  FIG. 1 . The data output driver that receives data (DATA) drives either HIGH level data though the first transistor M 1  or LOW level data through the second transistor M 2 . 
         [0006]    In many instances, an external voltage VDD is input through an exposed pin of a semiconductor integrated circuit and an inductance may exist on transmission path connected to the pin, wherein the external voltage VDD contains noise, especially low frequency noise. Due to the low frequency noise, levels of the external voltage VDD can greatly vary. When a data output driving operation is performed using the external voltage VDD having the noise, the level of output data is unstable and, moreover, the slew rate of output data abnormally varies. Accordingly, as the levels of the external voltage VDD vary due to the noise, integrity of the output data decreases due to distortions of the output data directly related to the noise. Thus, due to the distorted output data, there exists a high probability that critical operation errors will occur in the semiconductor integrated circuit, in particular, where low voltage and high speed operation is needed. 
       SUMMARY 
       [0007]    A data output driver capable of preventing abnormal variation of the level and slew rate of output data due to noise is described herein. 
         [0008]    In one aspect, a data output driver includes a noise detecting unit configured to output a noise detection signal to detect variations of power supply voltage due to noise, and a driver circuit unit configured to drive and output data with the variable driving capability in response to the noise detection signal. 
         [0009]    In another aspect, a data output driver includes a noise detecting unit configured to output noise detection signal to detect variations of a power supply voltage due to noise, at least one first driver configured to drive and output received data through a data output terminal, and at least one second driver configured to drive and output the received data through the data output terminal according to the noise detection signal. 
         [0010]    These and other features, aspects, and embodiments are described below in the section “Detailed Description.” 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0012]      FIG. 1  is a schematic circuit diagram of a conventional data output driver of a semiconductor integrated circuit; 
           [0013]      FIG. 2  is a schematic circuit diagram of an exemplary data output driver according to one embodiment; 
           [0014]      FIG. 3  is a schematic circuit diagram of an exemplary noise detecting unit of  FIG. 2  according to one embodiment; and 
           [0015]      FIG. 4  is an output simulation waveform of an exemplary data output driver according to one embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]      FIG. 2  is a schematic circuit diagram of an exemplary data output driver according to one embodiment. Referring to  FIG. 2 , a data output driver  100  of a semiconductor integrated circuit can be configured to include first to third inverters IV 11  to IV 13 , a noise detecting unit  200 , and a driver circuit unit  300 . For example, the data output driver  100  may be connected to a semiconductor integrated circuit (IC) to drive the semiconductor IC. 
         [0017]    The first inverter IV 11  can arranged to inversely output a noise detection signal ‘OUT’ through the noise detecting unit  200 . In addition, the second and third inverters IV 12  and IV 13  can buffer a data signal ‘DATA’ so as to transmit the drive circuit unit  300  with a substantially stable signal level. 
         [0018]    The drive circuit unit  300  can be configured to include a first driver  310  and a second driver  320 , wherein the drive circuit unit  300  can use an external voltage VDD as a power supply voltage. The first driver  310  can be configured to include a first transistor M 11  to which an external voltage terminal VDD is connected and a second transistor M 12  to which a ground voltage terminal VSS is connected. The data signal ‘DATA’ can be commonly provided as input to the gate terminals of the first and second transistors M 11  and M 12 . 
         [0019]    The second driver  320  can be configured to include a third transistor M 13  having a gate terminal that receives an inverted noise detection signal ‘OUTb’ and a source terminal that is connected to an external voltage terminal VDD. A fourth transistor M 14  can have a gate terminal that receives the data signal ‘DATA’, a source terminal that is connected to the drain terminal of the third transistor M 13 , and a drain terminal that is connected to a data output terminal DQ. A fifth transistor M 15  can have a gate terminal that receives the data signal ‘DATA’ and a drain terminal that is connected to the data output terminal DQ. A sixth transistor M 16  can have a gate terminal that receives the noise detection signal ‘OUT’, a drain terminal that is connected to the source of the fifth transistor M 15 , and a source terminal that is connected to a ground voltage terminal VSS. Although the drive circuit unit  300  is shown to be configured having the first driver  310  and the second driver  320 , additional drivers may be included. 
         [0020]      FIG. 3  is a schematic circuit diagram of an exemplary noise detecting unit of  FIG. 2  according to one embodiment. Referring to  FIG. 3 , the noise detecting unit  200  can be configured to include a differential amplifying unit  210 , a filter circuit unit  220 , and a buffer circuit unit  230 . The differential amplifying unit  210  can output a detection signal ‘DET’ having different output levels depending on whether the external voltage VDD is higher or lower than a reference voltage VDDR. When the external voltage VDD is higher than the reference voltage VDDR, the differential amplifying unit  210  can output the detection signal ‘DET’ at a HIGH level. Conversely, the differential amplifying unit  210  can output the detection signal ‘DET’ at a LOW level. The differential amplifying unit  210  can be configured to include first to fifth transistors M 21  to M 25 . 
         [0021]    The filter circuit unit  220  can be configured to generate the reference voltage VDDR, and to remove noise components of the external voltage VDD. The reference voltage VDDR can be generated via the filter circuit unit  220  in order to set a normalized standard level of a noiseless external voltage VDD. The filter circuit unit  220  can be configured to include a resistor R 1  and a capacitor C 1  disposed between the external voltage terminal VDD and the ground voltage terminal VSS. The reference voltage VDDR can be output through a common node of the resistor R 1  and capacitor C 1 . The buffer circuit unit  230  can be configured to buffer the detection signal ‘DET’ and produce the noise detection signal ‘OUT’. For example, the buffer circuit unit  230  can include first to third inverters IV 21  to IV 23 , wherein the first inverter IV 21  can include sixth to ninth transistors M 26  to M 29 . The sixth and ninth transistors M 26  and M 29  can function as load elements to not include noise components in an output signal of a buffer circuit unit  230 , i.e., the noise detection signal ‘OUT’. 
         [0022]      FIG. 4  is an output simulation waveform of an exemplary data output driver of a semiconductor integrated circuit according to one embodiment. In  FIG. 4 , waveforms of an external voltage VDD and a reference voltage VDDR are shown. Referring to  FIG. 4 , while an external voltage VDD can vary due to the presence of noise components, i.e., voltage drops of under about 1.5V during some intervals, the reference voltage VDDR produced by removing noise of the external voltage VDD using the filter circuit unit  220  (in  FIG. 3 ) can constantly maintain a substantially stable level in contrast to simply using the external voltage VDD alone. 
         [0023]    During an interval where the level of an external voltage VDD is higher than an interval level of a reference voltage VDDR, the differential amplifying unit  210  ( in  FIG. 3 ) can be configured to output the detection signal ‘DET’ at a HIGH level. However, during another interval where the level of an external voltage VDD is lower than an interval level of a reference voltage VDDR, the differential amplifying unit  210  (in  FIG. 3 ) can output the detection signal ‘DET’ at a LOW level. 
         [0024]    In  FIG. 3 , the buffer circuit unit  230  can invert the detection signal ‘DET’ to a level opposite of its original state in order to output a noise detection signal ‘OUT’. As shown in  FIG. 4 , the noise detection signal ‘OUT’ can be inactivated to a LOW level during an interval where the level of an external voltage VDD is higher than an interval level of a reference voltage VDDR. Conversely, the noise detection signal ‘OUT’ can be activated to a HIGH level during another interval where the level of an external voltage VDD is lower than an interval level of a reference voltage VDDR. 
         [0025]    When the noise detection signal ‘OUT’ is inactivated to a LOW level, the level of an external voltage VDD is substantially high enough to enable stable output data driving with the driving capability of only the first driver  310  (in  FIG. 2 ). Conversely, when the noise detection signal ‘OUT’ is activated to a HIGH level, the level of an external voltage VDD is low, whereby stable output data driving with the driving capability of only the first driver  310  (in  FIG. 2 ) is not enabled. Thus, when the noise detection signal ‘OUT’ is activated, simultaneous operation of the first driver  310  and the second driver  320  can improve data driving capability and stabilize output level and slew rate of output data. 
         [0026]    For example, when the noise detection signal ‘OUT’ is inactivated to a LOW level, the third and sixth transistors M 13  and M 16  of second driver  320  (in  FIG. 2 ) can be inactivated to stop their operation. Accordingly, only the first driver  310  can drive the data output terminal DQ in accordance with the level of received data signal ‘DATA’ by operation of the first and second transistors M 11  and M 12 . 
         [0027]    In  FIG. 2 , the first and second transistors M 11  and M 12  of the first driver  310  can be activated regardless of the noise detection signal ‘OUT’. Thus, the first driver  310  and the second driver  320  can simultaneously drive the data output terminal DQ according to the level of the received data signal ‘DATA’ by operation of the first and second transistors M 11  and M 12 . Accordingly, improvement of the data driving capability obtained by simultaneously operating the first driver  310  and the second driver  320  makes it possible to drive the data output terminal DQ at a substantially stable level, even if the level of the external voltage VDD is relatively low. While the output data DQ is substantially unstable during an interval where the level of the external voltage VDD is relatively low, the output data ‘DQ_N’ can maintain a substantially stable level during the same interval where the level of the external voltage VDD is relatively low due to the compensation provided by operation of the second driver  320 . 
         [0028]    While certain embodiments have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the and method described herein should not be limited based on the described embodiments. Rather, the s and methods described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.