Abstract:
In a drive circuit of a half-bridge inverter circuit, a stable operation cannot be performed at a start-up time and a problem exists such that if a high side output signal is first outputted, main switching elements and are simultaneously turned on. In the present invention, a start-up circuit comprising a latch circuit and a gate circuit are provided, the latch circuit is set while prioritizing a low-side signal, and a low-side output signal is always first made high level, thereby realizing a half-bridge inverter circuit which can start up wit a stability.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a half-bridge inverter circuit and, in particular, to a half-bridge inverter circuit to which a load driven at a high voltage is connected.  
           [0003]    2. Description of the Related Art  
           [0004]    A configuration of a half-bridge inverter circuit for lighting is shown in FIG. 1. Q 1  and Q 2  denote main switching elements, each including a power MOSFET. D 1  and D 2  are resonance current-commutating diodes, each including a parasitic diode between the drain and source of the power MOSFET. In a ballast circuit, L denotes a resonance reactor, C 1  denotes a direct current component-cutting capacitor, C 2  denotes a filament-preheating capacitor, and a circuit configuration is provided such that a fluorescent lamp  3  is connected in parallel with the filament-preheating capacitor C 2 .  
           [0005]    [0005]FIG. 2 shows operating waveforms when the lamp of the circuit of FIG. 1 is on. VGS 1  and VGS 2  denote gate-source voltages of the main switching elements Q 1  and Q 2 , respectively. During operation, the main switching elements Q 1  and Q 2  are alternately repeatedly turned on and off, and in order to prevent the main switching elements Q 1  and Q 2  from simultaneously being turned on, dead time periods, during which both main switching elements Q 1  and Q 2  are off, are provided.  
           [0006]    The high-side main switching element Q 1  is turned on when VGS 1  becomes high and a drain current shown by ID1 flows. Thereby, a square wave voltage is applied to the ballast circuit composed of L, C 1 , C 2  and fluorescent lamp  3 , and a sine wave-shaped ballast current I 1  flows. The ballast current I 1  when the lamp is on is a composite current formed of a filament current I 2  and a lamp current I 3 .  
           [0007]    The low-side main switching element Q 2  is turned on when VGS 2  becomes high and a drain current ID 2  flows. When that happens, energy which has been accumulated in the ballast circuit is discharged and the ballast current I 1 , the filament current I 2 , and the lamp current I 3  decrease in the negative direction.  
           [0008]    In an ordinary half-bridge inverter circuit, operations are carried out at a frequency in a delayed phase band which is higher than a resonance frequency. Accordingly, since the ballast current I 1  can be changed by a switching frequency of the main switching elements Q 1  and Q 2 , it becomes possible to adjust brightness.  
           [0009]    Referring to FIG. 1, an input signal from a control circuit  1  is converted to appointed drive signals (for example, VGS  1  and VGS 2 ) at a drive circuit  2 , whereby the main switching elements Q 1  and Q 2  are driven.  
           [0010]    A detailed circuit block of this drive circuit  2  is shown in FIG. 6. This drive circuit  2  includes a signal input circuit  21 , dead time control circuits  22  and  23  which perform dead time control on the high side and the low side, respectively, a pulse generating circuit  24 , a level shifting circuit  25 , a pulse filter circuit  26 , a latch circuit including an RS flip-flop circuit  27 , and output circuits  28  and  29  which supply drive signals HO and LO for driving the main switching elements Q 1  and Q 2  on the high side and the low side.  
           [0011]    In such a drive circuit  2 , an output signal from the control circuit  1  is shaped by the signal input circuit  21 , then inputted into the dead time control circuits  22  and  23  which perform dead time control on the high side and the low side, and as shown in FIG. 7, a high-side output signal HO, which is delayed from the input signal (output signal from the control circuit  1 ), and a low-side output signal LO, which falls before the high-side output signal HO rises, are formed. For the high-side output signal HO and the low-side output signal LO, dead time periods are provided during which both become low level so that the main switching elements Q 1  and Q 2  are not simultaneously turned on.  
           [0012]    In the drive circuit  2  on the high side, since the main switching element Q 1  is driven at a voltage of approximately 600V, it is necessary to form a drive signal VGS 1  by shifting the high-side output signal HO to a high voltage of approximately 600V. An output signal PGIN from the dead time control circuit  22  is inputted into the pulse generating circuit  24  and a set output signal OUT (Set) and a reset output signal OUT (Reset) are outputted therefrom. These signals are inputted into the subsequent level shifting circuit  25  for shifting to a high voltage and converted to a high-voltage set output signal OUT (Set) and a high-voltage reset output signal (Reset). These signals allow signals of a predetermined pulse width or longer to pass through the pass filter circuit  26 , thereby setting and resetting the latch circuit  27 , and a high side output signal HO is outputted from the output circuit  28 , thereby driving the main switching element Q 1  on the high side.  
           [0013]    In such a half-bridge inverter circuit, in order to prevent the main switching elements Q 1  and Q 2  from simultaneously being turned on, dead times are provided during which both drive signals (for example, VGS 1  and VGS 2 ) are off.  
           [0014]    However, at a start-up time, it is uncertain whether a high-side output signal is first outputted from the drive circuit or a low-side output signal is first outputted therefrom, and therefore a stable start-up condition cannot be obtained. A problem exists that if the high-side output signal is first outputted, the main switching elements Q 1  and Q 2  are simultaneously turned on.  
         SUMMARY OF THE INVENTION  
         [0015]    The present invention is provided to solve the foregoing problem such that at a startup time two main switching elements simultaneously may turn to the on-mode, and provides a half-bridge inverter circuit including dead time control circuits on the high side and the low side which form dead time periods based on an input signal to be inputted from a control circuit, and a start-up circuit including a latch circuit, which is reset upon detection of a rise in power supply on the low side, then set by a low-side output signal from the dead time control circuit on the low side, and a gate circuit, which receives the low-side output signal in response to an output from the latch circuit, then allows a high-side output signal from the dead time control circuit on the high side to pass. This configuration prevents the two main switching elements from being simultaneously turned on at a start-up time.  
           [0016]    According to the present invention, by providing the start-up circuit which prioritizes a low side signal, the main switching element on the low side is always first turned on at start-up. Thus, an advantage exists such that a stable start-up of the half-bridge inverter circuit can be performed.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    [0017]FIG. 1 is a diagram for explaining a half-bridge inverter circuit according to the present invention and prior art,  
         [0018]    [0018]FIG. 2 is a diagram for explaining operating waveforms of a half-bridge inverter circuit according to the present invention and prior art,  
         [0019]    [0019]FIG. 3 is a diagram for explaining a start-up circuit of the half-bridge inverter circuit according to an embodiment of the present invention,  
         [0020]    [0020]FIG. 4 is a diagram for explaining operating waveforms of a start-up circuit of the half-bridge inverter circuit according to the embodiment of FIG. 3,  
         [0021]    [0021]FIG. 5A is a diagram for explaining a start-up circuit and FIG. 5B is a diagram for explaining operating waveforms of the half-bridge inverter circuit including the circuit of FIG. 5A,  
         [0022]    [0022]FIG. 6 is a diagram for explaining a drive circuit of the half-bridge inverter circuit according to the present invention and prior art, and  
         [0023]    [0023]FIG. 7 is a diagram for explaining operations of a drive circuit of the half-bridge inverter circuit according to the present invention and prior art. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0024]    An embodiment of the present invention will be described in detail with reference to FIGS. 3, 4,  5 A and  5 B.  
         [0025]    The half-bridge inverter circuit of this invention includes a start-up circuit (denoted by the dotted rectangular in FIG. 3) and a power-supply voltage detection circuit  33  of FIG. 3, which cooperate with other components of the conventional driver circuit of FIG. 6 to operate as a driver circuit of this embodiment. Besides the driver circuit, the half-bridge inverter circuit of this invention also includes components of the conventional half-bridge inverter circuit of FIG. 1. Many of the conventional components are omitted from FIG. 3 for simplicity.  
         [0026]    Accordingly, the half-bridge inverter circuit of this invention includes main switching elements Q 1 , Q 2 , each including a power MOSFET, and resonance current-commutating diodes D 1 , D 2 , each including a parasitic diode between the drain and source of the power MOSFET. In a ballast circuit, there provided a resonance reactor L, a direct current component-cutting capacitor C 1 , and a filament-preheating capacitor C 2 , so that a fluorescent lamp  3  is connected in parallel with the filament-preheating capacitor C 2 . The inverter circuit of this invention also includes a dead time control circuit on a high side  22  and a dead time control circuit on a low side  23 .  
         [0027]    Operating waveforms of the inverter circuit of this invention is similar to the one shown in FIG. 2, and operating waveforms of the start-up circuit are shown in FIG. 4. Since the basic operation mechanism and circuit configuration are the same as those described in the section concerning prior arts, herein, a description will only be given of different aspects.  
         [0028]    [0028]FIG. 3 shows the input side of the driver circuit  2  of the inverter circuit of this invention, which includes the start-up circuit and the power-supply voltage detection circuit  33 . The signal input circuit  21  receives signals HIN and LIN from the control circuit  1  of FIG. 1. The output signal PGIN from the dead time control circuit  22  is inputted to the pulse generating circuit  24 , which is connected to the level shifting circuit  25  of the driver circuit  2  of FIG. 6.  
         [0029]    The start-up circuit shown in FIG. 3 comprises a latch circuit  31  which is reset upon detection of a rise in power source on the low side, then set by a low-side output signal from a dead time control circuit  23  on the low side, a gate circuit  32 , which receives the low-side output signal in response to an output from the latch circuit, then allows a high-side output signal from a dead time control circuit  22  on the high side to pass, and a start-up power-supply voltage detection circuit  33  (a UV circuit in the drawing) for detecting a rise in power-supply voltage V CC  on the low side.  
         [0030]    The latch circuit  31  consists of an RS flip-flop circuit (FF in the drawing), which receives an input of a detection signal from the power-supply voltage detection circuit  33  at a reset terminal R, is reset when the power-supply voltage V CC  on the low side rises, receives an input of a low-side output signal from the dead time control circuit  23  at a set terminal S, and operates so as to prioritize the low-side output signal.  
         [0031]    When the latch circuit  31  is set, a high-side output signal from the dead time control circuit  22  on the high side passes through the NOR gate circuit  32 , and is supplied to the pulse generating circuit  24 , resulting in outputting a high-side output signal HO. Although the drive circuit of FIG. 3 is a double-input type and receives two signals HIN and LIN from the control circuit  1 , a single-input type drive circuit, which receives only one signal from the control circuit  1  and outputs two signals corresponding to HIN and LIN, such as shown in FIG. 6, may be also used in the embodiment.  
         [0032]    Referring to FIG. 4, operations at start-up will be described.  
         [0033]    Before a rising signal in the power-supply voltage V CC  exceeds a reference voltage V REF , the latch circuit  31  is reset by an output from the power-supply voltage detection circuit  31 . For input signals LIN and HIN into the input circuit  21 , dead times are provided so that simultaneous turning-on does not occur, and when the input signal HIN arrives first after the rising signal in the power-supply voltage V CC  exceeds the reference voltage V REF , since the latch circuit  31  has not been set, this signal does not pass through the gate circuit  32 . The latch circuit  31  is set by the first arrival input signal LIN, whereby the next input signal HIN passes through the gate signal  32 .  
         [0034]    Now, referring to FIGS. 5A, 5B, a detailed circuit configuration and operations of a comparator circuit  331  of the power-supply voltage detection circuit  33  will be described.  
         [0035]    First, the power-supply voltage detection circuit  33  shown in FIG. 5A comprises two split resistances R 1  and R 2 , which are connected between the power source voltage V CC  on the low side and ground, a comparator circuit  331  which is provided with a noninverting input terminal (+in the drawing), into which a rising signal in the power-supply voltage V CC  from the junction between the two split resistances R 1  and R 2  is inputted, and an inverting input terminal (−in the drawing), into which a reference voltage V REF  is inputted, and an inverter circuit  332  for inverting an output from the comparator  331 .  
         [0036]    In such a comparator circuit  331 , as shown in FIG. 5B, at start-up, the rising signal in the power-supply voltage V CC  from the junction between the two split resistance R 1  and R 2  and the reference voltage V REF  are compared by the comparator circuit  331 , an output from the power supply detection circuit  33  becomes high level until the power-supply voltage V CC  reaches the reference voltage V REF , and the output from the power supply detection circuit  33  becomes low level after the rising signal in the power-supply voltage V CC  exceeds the reference voltage V REF . Accordingly, before the rising signal in the power-supply voltage V CC  exceeds the reference voltage V REF , the latch circuit is reset and subsequently, the latch circuit  31  is set by a low-side output signal from the low-side dead time control circuit  23 . As a result, since operation is carried out, at a start-up time, while prioritizing the low-side signal, electric supply to the high-side bootstrap configuration is supplied after the main switching element Q 2  is turned on, therefore a sufficient initial charging can be given to the high-side boot-strap configuration.  
         [0037]    The above embodiment of the invention may be applied to various types of input circuits  21  including a self-excitation type with an internal oscillator, a double input/double output type and a single input/double output type, as described above. As a modification to the embodiment of the invention, when a double input/double output type is used as the input circuit  21 , signals in which dead time is already created may be inputted to the input circuit  21  for eliminating the dead time controller circuit  22  on the high side and the dead time controller circuit  23  on the low side. Other obvious modifications may occur to a person skilled in the art. Those modifications will be included in the scope of this invention.