Abstract:
A semiconductor memory device of a bipolar-transistor type including a memory cell array, a redundancy array, a defective address memory circuit for storing a defective address and a comparing circuit for comparing an input address with the defective address. The defective address memory circuit includes a plurality of information memory circuits. The information memory circuits include a plurality of diode stages for determining their output amplitudes. When an input address coincides with the defective address stored in the address memory circuit, the redundancy array is selected instead of the memory cell array.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a bipolar-transistor type random access memory (RAM) having a redundancy configuration. More particularly, the present invention is directed to a defective address memory portion of a RAM. 
     2. Description of the Related Art 
     In a RAM device, a large number of memory cells are arranged along rows and columns. The density of defects generated in such a semiconductor memory device during the manufacture thereof is relatively independent of the integration density of the device. The density of defects is due to semiconductor manufacturing technology. In general, the higher the integration density of the device, the greater the ratio of normal memory cells to defective memory cells. This is one of the advantages of increasing the integration density of a semiconductor memory device. 
     Even if a device includes only one defective memory cell, however, the device cannot be operated normally, and therefore, must be scrapped. As a result, despite the lower ratio of defective memory cells, greater integration density means reduced manufacturing yield. 
     In a metal-insulator-semiconductor (MIS) RAM, in order to overcome the problem of defective memory cells, use is made of redundancy memory cells. When a defective memory cell is detected, a redundancy memory cell row or column is selected instead of the memory cell row or column including the defective memory cell. In general, one or two redundancy memory cell rows or columns are usually provided. 
     In such a redundancy configuration, in order to store address information of such a defective row or column and to disable regular decoders so that the redundancy row or column is selected in response to an address of the defective row or column, a defective address memory circuit is required. 
     In the prior art, however, since there has been no preferable defective address memory circuit for a bipolar-transistor type RAM, there has been no bipolar-transistor type RAM having a redundancy configuration. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to provide a bipolar-transistor type RAM having a redundancy configuration. 
     It is another object of the present invention to provide a novel information memory circuit suitable for a defective address memory circuit of the bipolar-transistor type RAM having a redundancy configuration. 
     Accordingly, the present invention provides a semiconductor memory device of a bipolar-transistor type including a memory cell array, a redundancy array, a defective address memory circuit for storing a defective address, and a comparing circuit for comparing an input address with the defective address. The defective address memory circuit comprises a plurality of information memory circuits which includes a plurality of diode stages for determining output amplitudes of the information memory circuits. When an input address coincides with the defective address stored in the address memory circuit, the redundancy array is selected instead of the memory cell array. 
     According to the present invention, there is also provided an information memory circuit including at least three diode stages connected in a forward bias direction between a first power supply V CC  and a mode, a diode stage linked in a reverse bias direction between a write power supply V P  and the first power supply V CC , a shorted-junction type programmable read-only memory (PROM) cell linked between the write power supply V P  and the node, and a switching element linked between the node and a second power supply V EE . The circuit thereby generates a high or low potential at the node in accordance with the short-circuited or non-short-circuited state of the PROM cell. 
     In the above-mentioned information memory circuit, two diode stages can be provided instead of the three diode stages, and in this case, the diode along the reverse bias direction is changed by one resistor, or one diode stage connected in a forward bias direction is provided on the side of the first power supply V CC . 
     According to the present invention, there is further provided an information memory circuit including at least three diode stages connected in a forward bias direction between the power supply V CC  and a node N 1 , a resistor linked between the node N 1  and the second power supply V EE , and a diode stage linked between the nodes N 1  and N 2 , and having the same conduction direction as the at least three diode stages. In addition, a resistor is linked between the node N 2  and the second power supply V EE , and a diode stage is linked in a reverse bias direction between the first power supply V CC  and the write power supply V P . A short-circuited-junction type PROM cell PC is linked between the write power supply V P  and the node N 2 , and a switching element is linked between the node N 2  and the power supply V EE . An output circuit is connected to the nodes N 1  and N 2 , for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of the PROM cell. 
     In the above-mentioned information memory circuit, in order to separate the circuits for determining each potential at the nodes N 1  and N 2 , three diode stages are added to the node N 2 . Also, the diode between the power supply V CC  and the write power supply V P  can be replaced by a resistor, and one stage of the three diode stages can be omitted. In addition, the diode stage between the power supply V CC  and the write power supply V P  can be deleted, however, a diode stage is provided on the power supply V CC . 
     According to the above-mentioned configuration, if the short-circuited junction type PROM cell is not destroyed, the potential at the node N 1  is low. On the other hand, if the short-circuited junction type PROM cell is destroyed, the potential at the node N 1  is high. The data of the PROM cell can be read out by detecting the potential at the node N 1 . Note that the difference in potential at the node N 1  between the non-destroyed state and destroyed state of the PROM cell corresponds to the forward direction potential of one diode stage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description as set forth below with reference to the accompanying drawings, wherein: 
     FIG. 1 is a block diagram of an embodiment of the semiconductor device of a bipolar-transistor type having a redundancy configuration according to the present invention; 
     FIG. 2 is a block circuit diagram of the address memory circuit of FIG. 1; 
     FIGS. 3 through 10 are circuit diagrams of the 1-bit memory circuit of FIG. 2; 
     FIGS. 11A and 11B are circuit diagrams of the comparing circuit of FIG. 2; and 
     FIGS. 12A and 12B are circuit diagrams of another embodiment of the semiconductor memory device of a bipolar-transistor type having a redundancy configuration according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1, which is an embodiment of the present invention, reference numeral 1 designates a 64K static memory cell array, and 2 designates a redundancy array. Note that the redundancy array can be comprised of more than two rows or columns, however, in this case, a one-row array is described to simplify the explanation. One row of the memory cell array 1 is selected by row address buffers 3, word decoders 4, and word drivers 5. That is, external row address signals A 0 , A 1 , . . . , A 7  are received by emitter-followers Q 11  and are converted by the row address buffers 3 into internal row address signals A 0 , A 1 , . . . , and A 7 , and their inverted signals A 0 , A 1 , . . . , and A 7 , which are received by the word decoders 4 which drive one of the 256 word drivers 5, i.e., one of the word lines WL 0 , WL 1 , . . . , WL 255 . Similarly, one column of the memory cell array 1 is selected by a column selection means (not shown). 
     In FIG. 1, reference 6 designates a defective address memory circuit, 7 is an address comparing circuit for comparing an input address defined by the external address signals A 0 , A 1 , . . . , and A 7  with the defective address defined by signals A 0R , A 1R , . . . , and A 7R  stored in the defective address memory circuit 6, and 8 is a driver circuit for driving the redundancy array 2. 
     If all the memory cells are normal, no problem occurs, and accordingly, the circuit of FIG. 1 operates in the same way as the conventional devices. However, if a defective cell is detected in the memory cell array 1 of FIG. 1, a row address of a row including the defective cell (hereinafter, referred to as a defective row address) is written into the defective address memory circuit 6. The row address signals A 0 , A 1 , . . . , and A 7  are always compared with the defective address signals A 0R , A 1R , . . . , and A 7R  written into the address memory circuit 6. As a result, when the row address signals A 0 , A 1 , . . . , and A 7  coincide with the defective row address signals A 0R , A 1R , . . . , and A 7R , respectively, the address comparing circuit 7 operates the driver 8 to select the word line WL R  and drive the redundancy array 2, and simultaneously to disable the word drivers 5, thereby causing a non-selection of the memory cell array 1. 
     In FIG. 2, which is a detailed block diagram of the defective address memory circuit 6 of FIG. 1, the circuit 6 comprises 1-bit memory circuits 6-0, 6-1, . . . , and 6-7 corresponding to each of the row address signals A 0 , A 1 , . . . , and A 7 . That is, the row address signals A 0 , A 1 , . . . , and A 7  are applied thereto, a high voltage such as +5 V is applied as a write voltage to the write terminal V P , and a low voltage such as -5 V is applied to the other terminal V n . Then, the row address signals A 0 , A 1 , . . . , and A 7  are written into the 1-bit memory circuits 6-0, 6-1, . . . , and 6-7, respectively. Thus, these signals can be read out as the defective address signals, . . . , A 0R , A 1R , . . . , and A 7R . 
     Hereinafter, the 1-bit memory circuits will be explained in more detail. 
     In FIG. 3, which is a first example of the 1-bit memory circuit of FIG. 2, a power supply V CC  is, for example, ground level GND, and a power supply V EE  is, for example, -5 V. If in a write mode for breaking down the PROM cell PC, the write power supply V P  is +5 V, otherwise V P  equals V CC  (GND). Also, if in a write mode, the write power supply V n  is lower than -5 V, otherwise V n  equals V EE  (-5 V). Further, PC designates a short-circuited junction type PROM Cell which has diode characteristics after a write mode. That is, during a write mode, a larger voltage than the endurance voltage C E  of the PROM cell, which is a type of transistor, is applied to the emitter-collector, thereby breaking it down. 
     Provided between the power supply V CC  and node N 1  is a series of three diode stages D 1 , D 2 , and D 3 , and a current source I S , which generates a voltage at node N 1  for a non-broken mode. In this case, the diode stages D 1 , D 2 , and D 3  are forward biased. That is, the potential at node N 1  is 
     
         -0.8×3=-2.4 V 
    
     and is determined by the diode stages D 1 , D 2 , and D 3 . Here, note that 0.8 V is the forward voltage of one diode stage. Also, in order to determine the potential at node N 1  after a writing node for the PROM cell PC, diode stage D 0  is provided between the power supply V CC  and the write power supply V P . The diode stage D 0  is reverse biased during a write mode. After a write mode, since the PROM cell PC serves as a diode stage, the potential at node N 1  is the voltage corresponding to two diode stages, i.e., 
     
         -0.8×2=-1.6 V. 
    
     Thus, in the circuit of FIG. 3, during a non-write (non broken-down) mode of the PROM cell PC, the potential at node N 1  is -2.4 V, and after a write mode, the potential at node N 1  is -1.6 V. Thus, the difference of 0.8 V in the potential is generated at node N 1 . Note that a transistor Q 1  is used for a write operation of the PROM cell PC. 
     Next, the write operation of the circuit of FIG. 3 will be explained. In order to carry out a write operation, the write power supply V P  is raised to +5 V from the exterior, while the write power supply V n  is retained at -5 V. At this time, when the address signal A i  is at a high level the write transistor Q 1  is turned ON. The duration voltage C E  is approximately 7 V. As a result, a voltage higher than the duration voltage C E  (which is, in this case, about 10 V) is applied to the PROM cell PC, and accordingly, a current I W  flows through the emitter-collector of the PROM cell PC, thereby breaking down the emitter-base thereof. 
     In FIG. 4, which is a second example of the 1-bit memory circuit of FIG. 2, the diode stages D 0  and D 3  of FIG. 3 are deleted, and a resistor R 0  is provided between the power supplies V CC  and V P . Note that the value of the resistor R 0  is relatively small. Therefore, the potential at node N 1  for a non-broken-mode is 
     
         -0.8×2=-1.6 V 
    
     and is determined by the diodes D 1  and D 2 , and the potential at node N 1  after a write operation is -0.8 V. Thus, also in the circuit of FIG. 4, a difference in potential of 0.8 V is generated at node N 1 . 
     In FIG. 5, which is a third example of the 1-bit memory circuit of FIG. 2, the resistor R 0  of FIG. 4 is deleted, and a diode D 0  is provided on the side of the power supply V CC . However, the operation of the circuit of FIG. 5 is approximately the same as that of FIG. 4. 
     In FIGS. 3, 4, and 5, a resistor can be provided instead of the current source I S . 
     In FIG. 6, which is a fourth example of the 1-bit memory circuit of FIG. 2, provided between the power supplies V CC  and V n  is a series circuit formed by three diode stages D 1 , D 2 , and D 3 , and resistors R 1  and R 2  for generating a reference voltage. That is, the potential at node N 1  is the reference voltage which equals 
     
         -0.8×3=-2.4 V 
    
     and is determined by the diode stages D 1 , D 2 , and D 3 . Also, in order to determine the potential at node N 2  during a non-broken-mode of the PROM cell PC, a diode D 4  and the resistor R 2  are added to the diodes D 1 , D 2 , and D 3  between the power supplies V CC  and V n . That is, in this case, the potential at node N 2  is 
     
         -0.8×4=-3.2 V 
    
     and is determined by the diodes D 1 , D 2 , D 3 , and D 4 . Also, in this case, the potential at node N 2  after a write operation is 
     
         -0.8×2=-1.6 V 
    
     and is determined by the diode stage D 0  and the PROM cell PC. Thus, in the circuit of FIG. 6, during a non-broken-mode of the PROM cell PC, the potential at node N 1  is -2.4 V, and the potential at node N 2  is -3.2 V. As a result, among transistors Q 2  and Q 3  which form a current switch, the transistor Q 2  is turned ON, while the transistor Q 3  is turned OFF, and therefore, the potential at node N 3  becomes at a high level (V CC ). Thus, as the base potential of an output transistor Q 4  increases, the potential of the defective address signal A iR  becomes high. On the other hand, after a write mode of the PROM cell PC, the potential at node N 1  is -2.4 V, and the potential at node N 2  is -1.6 V. As a result, among the transistors Q 2  and Q 3  forming a current switch, the transistor Q 2  is turned OFF, while the transistor Q 3  is turned ON, and therefore, the potential at node N 3  becomes a low level. Thus, as the base potential of the output transistor Q 4  decreases, the potential of the defective address signal A iR  becomes low. 
     In FIG. 7, which is a fifth example of the 1-bit memory circuit of FIG. 2, in order to separate the circuit for determining the potential at node N 1  from the circuit for determining the potential at node N 2  during a non-broken-mode, three diode stages D 1  &#39;, D 2  &#39;, and D 3  &#39; are provided. However, the operation of the circuit of FIG. 7 is the same as that of FIG. 6. 
     Thus, in the circuits of FIGS. 6 and 7, the potential at node N 2  is increased or decreased by the potential corresponding to one diode stage as compared with the reference voltage at node N 1 , in accordance with the presence or absence of a write operation (breakdown) of the PROM cell PC. Also, the logic amplitude corresponding to one diode stage is read out by the following transistors Q 2 , Q 3 , and Q 4 . 
     In FIG. 8, which is a sixth example of the 1-bit memory circuit of FIG. 2, the diode D 3  of FIG. 6 is deleted, and a resistor R 0  is provided between the power supplies V CC  and V P . Note that the value of the resistor R 0  is relatively small. Therefore, the reference voltage potential at node N 1  is 
     
         -0.8×2=-1.6 V 
    
     and is determined by the diodes D 1  and D 2 . The potential at node N 2  during a non-broken-mode of the PROM cell PC is 
     
         -0.8×3=-2.4 V 
    
     and is determined by the diodes D 1 , D 2 , and D 4 . The potential at node N 2  after a write mode of the PROM cell PC is 
     
         -0.8 V 
    
     and is determined by the PROM cell PC which corresponds to one diode stage. Thus, after a write mode of the PROM cell PC, the potential at node N 1  is -1.6 V; and the potential at node N 2  is -2.4 V. Thus, in the same manner as in the circuit of FIG. 6, the potential of the defective address signal A iR  is high. On the other hand, after a write mode of the PROM cell PC, the potential at node N 1  is -1.6 V; and the potential at node N 2  is -0.8 V. Thus, in the same manner as in the circuit of FIG. 6, the potential of the defective address signal A iR  is low. 
     In FIG. 9, which is a seventh example of the 1-bit memory circuit of FIG. 2, the resistor R 0  of FIG. 8 is deleted, and a diode D 0  is provided on the side of the power supply V CC . However, the operation of the circuit of FIG. 9 is similar to that of FIG. 8. 
     In FIG. 10, which is an eighth example of the 1-bit memory circuit of FIG. 2, in order to separate the circuit for determining the potential at node N 1  from the circuit for determining the potential at node N 2 , two diode stages D 1  &#39; and D 2  &#39; are added. However, the operation of the circuit of FIG. 10 is the same as that of FIG. 8. 
     Thus, in the circuits of FIGS. 8, 9, and 10, the potential at node N 2  is increased or decreased by the potential corresponding to one diode stage as compared with the reference voltage at node N 1 , in accordance with the presence or absence of a write operation (breakdown) of the PROM cell PC. Also, the logic amplitude corresponding to one diode stage is read out by the following transistors Q 2 , Q 3 , and Q 4 . 
     The output A iR  of the circuit of FIGS. 3, 4, 5, 6, 7, 8, 9, or 10 is supplied to the address comparing circuit 7 of FIG. 1. As illustrated in FIGS. 11A and 11B, the address comparing circuit 7 comprises eight exclusive OR circuits EOR 0 , EOR 1 , . . . , EOR 7 , and a NOR circuit NR. When the address signals A 0 , A 1 , . . . , and A 7  coincide with the defective address signals A 0R , A 1R , . . . , and A 7R , the outputs S 0 , S 1 , . . . , and S 7  of the exclusive OR circuits ERO 0 , EOR 1 , . . . , and EOR 7  are all low, so that the output S out  of the NOR circuit NR becomes high, thereby operating the driver 8, and, simultaneously, disabling the word drivers 5. On the other hand, when at least one bit of the address signals A 0 , A 1 , . . . , and A 7  does not coincide with a corresponding one of the defective address signals A 0R , A 1R , . . . , and A 7R , at least one of the outputs S 0 , S 1 , . . . , and S 7  of the exclusive OR circuits EOR 0 , EOR 1 , . . . , and EOR 7  is high, so that the output S out  of the NOR circuit NR becomes low, thereby disabling the driver 8, and, simultaneously, enabling the word drivers 5. 
     In FIG. 11, note that V R  is a reference voltage, which is predetermined as suitable for the logic amplitude of the defective address memory circuit 6-i. For example, in the case of the circuit in FIGS. 3 or 5, V R  is approximately -2.0 V, while in the case of the circuit as illustrated in FIG. 4, V R  is about -1.2 V. Also, V RD  of FIG. 11 is a predetermined reference voltage. 
     Note that the number of diode stages (D 1 , D 2 , and D 3 ) of FIGS. 3 through 10 can be increased. However, in FIG. 7 (or 10), when the number of diode stages D 1  to D 3  (or D 1  and D 2 ) is increased, the number of diode stages D 1  &#39; to D 3  &#39; (or D 1  &#39; and D 2  &#39;) must also be increased. 
     In the 1-bit memory circuits in FIGS. 3 through 10, the logic amplitude is defined by the number of diode stages. Accordingly, such circuits are helpful in the configuration of the defective address memory circuit for storing a defective address in a bipolar-transistor type RAM having a redundancy configuration. 
     However, in the case of a write operation in the circuits of FIGS. 3 through 10, a very large write current I W  is necessary, and as a result, the write transistor Q 1  becomes large and also its load becomes large. Therefore, in FIG. 1, when the address signals A 0 , A 1 , . . . , and A 7  having a large logic amplitude are supplied directly to the row address buffers 3 and to the defective address memory circuit 6, the large load of the write transistor Q 1  is also applied to the address signals A 0 , A 1 , . . . , and A 7  even during a non-write mode. This causes a problem wherein an address access time is delayed during a normal state. 
     In FIGS. 12A and 12B, which are another embodiment of the present invention, each of the row address signals A 0 , A 1 , . . . , and A 7  are supplied via emitter-follower transistors Q 11  and Q 12 , diodes D 11 , D 12 , and D 13 , and resistors R 11  and R 12  to the defective address memory circuit 6. For example, if the high and low levels of an address signal are -0.8 V and -1.8 V, respectively, the address amplitude is 1.0 V (i.e., 1.8-0.8), and therefore, the high and low levels at the inputs of the row address buffers 3 are -1.6 V (i.e., -0.8-0.8) and -2.6 (i.e., -1.8-0.8), respectively, and the address amplitude is also 1.0 V. On the other hand, at each node N 4  on the input side of the defective address memory circuit 6, the high level -0.8 V of the address signals A 0 , A 1 , . . . , and A 7  becomes 
     
         -0.8-0.8×5=-4.8 V 
    
     and is determined by two stages of the emitter-follower transistors Q 11  and Q 12  and three stages of the diodes D 11 , D 12 , and D 13 , and also the low level -1.8 V becomes 
     
         -1.8-0.85×5=-5.8 V 
    
     and is determined by two stages of the emitter-follower transistors Q 11  and Q 12  and three stages of the diodes D 11 , D 12 , and D 13 . In this case, since the lowest power supply voltage is -5.0 V, the low level at each node N 3  is -5.0 V. Therefore, the address amplitude at each node N 3  is small and is 0.2 V (i.e., 5.0-4.8). The address amplitude of the gates of the write transistors Q 1  is further decreased by resistors R 11  and R 12 . For example, when the address amplitude is at the gates of the write transistors Q 1 , the address amplitude is reduced 0.1/1=1/10 by the two stages of the emitter-follower transistors, the three stages of the diodes, and the resistors. 
     Thus, during a non-write mode, since the address amplitude input to the defective address memory circuit 6 is reduced as compared with the address amplitude input to the row address buffers 3, application of a large load of the write transistors Q 1  can be substantially avoided. That is, even when the gate capacity C G  of the transistor Q 1  is large, the fluctuation of charges C G  ΔV is reduced if the voltage amplitude ΔV is reduced. Thus, the load of the write transistors can be neglected. 
     During a write mode, since the voltage V P  is increased from 0 V to 5 V, the address amplitude at the write transistors Q 1  becomes large, and in this case, the address amplitude at the address buffers 3 also increases. This, however, has no effect on the address buffers 3 during a write mode. 
     Note that, in FIG. 12, two stages of emitter-followers, three stages of diodes, and the like are used as the level shift means. The number of stages, however, can be modified as occasion demands or in accordance with the power supply voltage. For example, all the five stages may consist of diodes. Also, if the write voltage is high, the number of stages can be more than six. Further, if the lowest power supply voltage is higher than -5 V, the number of stages can be less than four. 
     Thus, in FIGS. 12A and 12B, during a non-write mode, since the address amplitude applied to the write transistors Q 1  can be reduced, the large load of these write transistors is not applied to the address signals, and as a result, the address access time can be reduced.