Abstract:
A digitally controlled signal attenuator circuit which allows an incoming DC-clamped signal to be selectively attenuated using a set of digital control signals while maintaining its DC clamping. Multiple stages of such a circuit can be cascaded to provide for multiple forms of signal attenuation without affecting the clamping. Preferred forms of the attenuator circuit use pass transistors and transmission gates as switches for selectively altering the resistance values of resistive circuits connected in shunt to and in series with the signal being attenuated. In the case of where the subject signal is a variable DC signal such a brightness control voltage, such circuit configurations also allow the output signal voltage range to include values which are more negative than the DC clamp voltage as well as more positive.

Description:
This is a continuation-in-part of application Ser. No. 09/322,681, filed May 28, 1999. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to signal attenuation circuit architectures, and in particular, signal attenuator circuits that are controlled by digital signals. 
     2. Description of the Related Art 
     Many high speed analog signal systems require some form of high speed signal magnitude control, such as a variable attenuator circuit. Perhaps one of the more common techniques for providing this function is the use of analog multiplier circuits. However, such circuits are generally not very accurate and do not interface well with the digital control systems that have become more prevalent. 
     Accordingly, it would be desirable to have some form of digitally controlled signal magnitude control circuit architecture that provides accurate signal attenuation characteristics and interfaces more directly with a digital control system. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a high speed digitally controlled signal magnitude control circuit architecture is provided in which a digital control signal controls solid state switches for configuring a resistor ladder architecture to achieve desired signal attenuation values. The subject architecture can be duplicated and cascaded to provide an Nth-order digitally controlled signal magnitude control circuit, and is particularly advantageous for use in multimedia applications in which high speed audio and video signals are processed. 
     In accordance with one embodiment of the present invention, a digitally controlled signal magnitude control circuit includes a reference DC signal source circuit, a composite signal source circuit and a signal magnitude control circuit. The reference DC signal source circuit is configured to provide a reference DC signal. The composite signal source circuit is configured to provide a first composite signal with a first AC component and a first DC component which is substantially equal to the reference DC signal. The signal magnitude control circuit has a programmable signal magnitude transfer function, is coupled to the reference DC signal source circuit and the composite signal source circuit, and is configured to receive a plurality of digital control signals, the reference DC signal and the first composite signal and in accordance therewith provide a second composite signal with a second AC component which corresponds to the first AC component and a second DC component which is substantially equal to the reference DC signal. Respective values of the plurality of digital control signals define corresponding values of the programmable signal magnitude transfer function and a ratio of the second AC component and the first AC component is substantially equal to one of the values of the programmable signal magnitude transfer function. 
     In accordance with another embodiment of the present invention, a digitally controlled signal magnitude control circuit includes a reference DC signal source circuit, a variable DC signal source circuit and a signal magnitude control circuit. The reference DC signal source circuit is configured to provide a reference DC signal. The variable DC signal source circuit is configured to provide a variable DC signal with a first range of magnitudes defined by lower and upper first range limits. The signal magnitude control circuit has a programmable signal magnitude transfer function, is coupled to the reference DC signal source circuit and the variable DC signal source circuit, and is configured to receive a plurality of digital control signals, the reference DC signal and the variable DC signal and in accordance therewith provide a composite DC signal with a variable DC component which corresponds to the variable DC signal and a reference DC component which is substantially equal to the reference DC signal. Respective values of the plurality of digital control signals define corresponding values of the programmable signal magnitude transfer function. The variable DC component includes a second range of magnitudes defined by lower and upper second range limits. The lower and upper second range limits are more negative and more positive than the reference DC component, respectively. A ratio of the second range of variable DC component magnitudes and the first range of variable DC signal magnitudes corresponds to one of the values of the programmable signal magnitude transfer function. 
     In accordance with still another embodiment of the present invention, a digitally controlled signal attenuator circuit includes a reference terminal, an input terminal, an output terminal, resistive circuits and a resistive switching circuit. The reference terminal is configured to convey a reference DC signal. The input terminal is configured to convey an input signal with an input AC component and an input DC component. The input DC component is substantially equal to the reference DC signal. The output terminal is configured to convey an output signal with an output AC component and an output DC component. The output DC component is substantially equal to the reference DC signal and a ratio of the input AC component and the output AC component is substantially equal to one of a plurality of programmable signal attenuation values. One resistive circuit is coupled between the input terminal and the reference terminal and has a resistive circuit resistance. Another resistive circuit is coupled between the input terminal and the output terminal. The resistive switching circuit is coupled between the input terminal, the output terminal, the reference terminal the first resistive circuit, has a resistive switching circuit resistance and is configured to receive a plurality of digital control signals and in accordance therewith establish effective values of resistance for the resistive circuit resistance and the resistive switching circuit resistance. Respective ones of the effective resistance values define corresponding ones of the plurality of programmable signal attenuation values. 
     In accordance with yet another embodiment of the present invention, a digitally controlled signal attenuator circuit includes a reference terminal, an input terminal, an output terminal, resistive circuits and a resistive switching circuit. The reference terminal is configured to convey a reference DC signal. The input terminal is configured to convey a variable DC input signal with an input range of magnitudes defined by lower and upper input range limits. The output terminal is configured to convey a composite DC output signal with a variable DC component which corresponds to the variable DC input signal and a reference DC component which is substantially equal to the reference DC signal. The variable DC component includes an output range of magnitudes defined by lower and upper output range limits. The lower and upper output range limits are more negative and more positive than the reference DC component, respectively. A ratio of the input range of variable DC input signal magnitudes and the output range of variable DC component magnitudes corresponds to one of a plurality of programmable signal attenuation values. One resistive circuit is coupled between the input terminal and the reference terminal and has a resistive circuit resistance. Another resistive circuit is coupled between the input terminal and the output terminal. The resistive switching circuit is coupled between the input terminal, the output terminal, the reference terminal and the first resistive circuit, has a resistive switching circuit resistance and is configured to receive a plurality of digital control signals and in accordance therewith establish effective values of resistance for the resistive circuit resistance and the resistive switching circuit resistance. Respective ones of the effective resistance values define corresponding ones of the plurality of programmable signal attenuation values. 
    
    
     These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a functional block diagram of an analog signal system using a digitally controlled signal magnitude control circuit in accordance with one embodiment of the present invention. 
     FIG. 2 is a circuit schematic diagram representing the operation of the digitally controlled signal magnitude control circuit of FIG. 1. 
     FIG. 3 is a signal diagram representing the signal magnitude control provided by the circuit of FIG. 1. 
     FIG. 4 is a functional block diagram of an analog signal system using a digitally controlled signal magnitude control circuit in accordance with another embodiment of the present invention. 
     FIG. 5 is a graph representing the operation of the digitally controlled signal magnitude control circuit of FIG. 4 when used to control the attenuation profile of a variable DC signal. 
     FIG. 6 is a signal diagram representing the signal magnitude control provided by the circuit of FIG. 4. 
     FIG. 7 is a circuit schematic diagram of an example embodiment of the digitally controlled signal magnitude control circuits of FIGS. 1 and 4. 
     FIG. 8 is a circuit schematic diagram of another example embodiment of the digitally controlled signal magnitude control circuits of FIGS. 1 and 4. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, an analog signal system using a digitally controlled signal magnitude control circuit in accordance with one embodiment of the present invention includes a magnitude control circuit 10, buffer amplifiers 12, 14, a DC reference voltage source 16, a synchronous switching circuit 18 and a series coupling capacitor 20. The input signal 25, which typically includes both AC and DC signal components, is AC-coupled to node 22 where it is summed with the DC reference voltage 17, via the switch circuit 18, during the DC clamping intervals as defined by the clamp signal 23 (e.g., such as during the horizontal blanking interval in the case of a video input signal). This DC-clamped signal 21 is buffered by the buffer amplifier 12. The DC reference voltage 17 is also buffered by a buffer amplifier 14. 
     These buffered composite (i.e., AC and DC) 13 and DC 15 signals are provided to the magnitude control circuit 10. In accordance with a digital control signal 9, the output signal 11 is another composite signal. This signal 11 includes a DC component equal to the buffered DC reference voltage 15 (as well as the buffered DC component of the input composite signal 13). This signal 11 further includes an AC component which is equal to the buffered AC component of the input composite signal 13 multiplied by the transfer function of the stage 10 as determined by the digital control signal 9. (For example, if the digital control signal 9 defines an attenuation of 5 decibels, the AC component in the output signal 11 is 5 decibels less than the AC component of the input signal 13.) 
     Referring to FIG. 2, the magnitude control circuit 10 of FIG. 1 can be represented by the embodiment 10a which includes an input buffer amplifier 30 and a digitally controlled resistive attenuator circuit 32. The DC reference voltage 15 is applied at the bottom, while the buffered composite signal 31 is applied at the top. In accordance with the digital control signal 9, variable resistances 36a, 36b, 36c are adjusted, thereby producing, in conjunction with a series resistance 34, a resistive attenuation factor. (Specific and more detailed embodiments of this resistive circuit 32 are discussed in more detail below.) 
     Referring to FIG. 3, operation of the circuit of FIG. 1 when used to process a clamped video signal can be better understood. During the horizontal blanking interval, the DC reference voltage 17 (FIG. 1) clamps the AC-coupled input signal. During the active video or OSD (on screen display) portions of the input signal 25, the digital control signal 9 determines the attenuation of the buffered composite signal 13 to establish the level of the output signal 11. In this example, for a 7-bit control signal 9, the output signal 11 can be adjusted over the range of 2.05 volts (maximum attenuation) through 3.0 volts (minimum attenuation). 
     Referring to FIG. 4, in accordance with another embodiment of the present invention, the magnitude control circuit 10 can be used to process, in accordance with the reference voltage 15, a variable DC voltage signal 13. In the case of a video signal system, for example, this voltage 13 can be the brightness control for the display monitor. A digital input signal 47 is varied in value in accordance with the desired brightness setting. This signal 47 drives a digital-to-analog converter circuit (DAC) 42, thereby producing a variable analog voltage signal 43 which is buffered by the buffer amplifier 12 to drive the top of the magnitude control circuit 10. Similarly, the DC reference source can be implemented using another DAC 40, thereby allowing the DC reference voltage 15 to also be established in accordance with a digital control signal 45. 
     Referring to FIG. 5 the effect of the digital control signal 9 upon the resulting variable DC output signal 11 from the circuit of FIG. 4 can be better understood. For a minimum attenuation (or maximum gain) as defined by the digital control signal 9, the output signal 11 will vary between values A1 and B1 with a slope G1 as shown. Conversely, for a maximum attenuation (or minimum gain), the output signal 11 will vary over a range of A2 through B2 with a slope of G2 as shown. These ranges can be shifted up (more positive) or down (more negative) in accordance with the bias voltage BIAS which is established by the DC reference voltage 15. These ranges of values of the variable DC output signal 11, as compared to the corresponding ranges of values of the input variable DC voltage signal 13, are determined by the attenuation factor established by the digital control signal 9. 
     Referring to FIG. 6, operation of the circuit of FIG. 4 in a video signal system can be better understood. During the horizontal blanking interval, the brightness control range, as defined by the digital control signal 9, can be varied as shown. This control range, as noted above, can be shifted by varying the DC reference voltage in more positive or more negative directions. For example, for a DC reference, or bias, voltage of 1.3 volts (as established by the control signal 45 to the DC reference voltage source DAC 40) and a 400 millivolt brightness control voltage (as established by the brightness control signal 47), the digital magnitude control signal 9 can vary the brightness control output signal 11 over a range of 1.1 volts (maximum attenuation) through 1.48 volts (minimum attenuation). 
     Referring to FIG. 7, one embodiment 10b of the magnitude control circuit 10 (FIGS. 1 and 4) can be implemented as shown. The input buffer amplifier 30 is implemented as a complementary MOSFET amplifier 30a. As discussed above (in connection with FIG. 2), the buffered signal 31 drives the top of the resistive array 32a, while the DC reference voltage 15 drives the bottom. Series-connected pass transistors in the form of P-type MOSFETs 50 and N-type MOSFETs 52 and a set of series resistances 54 are connected between the nodes driven by the signal 31 and reference voltage 15. (In this example, due to the integrated circuit structure being used, the various resistors 54, 56, 58 are implemented using MOSFET devices with fixed bias potentials (PWRP or PWRN, as appropriate) applied to their respective gate 15 terminals.) 
     In accordance with the binary states of the bits A0-A6 (in this case 7 bits) of the digital control signal 9a, the pass transistors 50, 52 cause the bottom ends of resistor circuits 56 to be driven by either the buffered signal 31 or the reference voltage 15. This has the effect of connecting various permutations of series resistors 58 and shunt resistors 56 across either the upper portion 54a or lower portion 54b of the shunt resistive circuit 54 on the input side. The resulting net resistance interacts with the series fixed resistance 34a to produce the desired attenuation factor. This selective connecting of the various resistances in this manner produces the variable resistances 36a, 36b, 36c depicted in the circuit diagram of FIG. 2. 
     Referring to FIG. 8, another embodiment 10c of the magnitude control circuit 10 uses the same basic technique of switching resistances to produce the variable resistive network depicted in FIG. 2, but uses transmission gate circuits 60, 62 in place of the pass transistors 50, 52. Accordingly, the individual bits A0-A5 (in this case 6 bits) of the digital control signal 9b are also inverted using inverter circuits 64 for driving the transmission gate circuits 60, 62. This circuit 32b operates in an manner similar to that of the circuit 32a of FIG. 7. However, the transmission gate circuits 60, 62 provide improved isolation for when the incoming signal 31 is a variable DC voltage which may, at times, be more negative than the DC reference voltage 15. This allows the nodes driven by the signal 31 and reference voltage 15 to &#34;flip&#34; in polarity with respect to each other as needed. In other words, as shown in the graph of FIG. 5, the output signal 11 may sometimes be more negative than the DC reference voltage 15 providing the bias potential. Using transmission gate circuits 60, 62 allows this to be done more reliably. 
     Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.