Abstract:
In accordance with the present invention, an adder tree structure includes at least two adder stages. In the circuit and method according to the present invention, the first of the two adder stages generates two bits of a common weight and other more significant bits of a weight one bit more significant than the two bits of the common weight. The second of the two adder stages includes an adder that receives the more significant bits generated in the first of the two adder stages. The second adder stage also includes an AND gate which receives and logically AND&#39;s the two bits of the common weight to generate a carry-in bit for the adder in the second stage. The above adder tree structure and adding method have an advantage of permitting more input terminals of adders to contain information about the input values to the adder tree structure. Therefore, the adders are used more efficiently and less adders are required to perform a specific function.

Description:
BACKGROUND OF THE INVENTION 
     Wallace tree structures are well-known adder tree structures in the art and are used in a variety of application. Each Wallace tree is composed of several basic adder units positioned in several stages. 
     One Wallace tree structure implements a 4:2 adder as a basic adder unit. This unit has five input terminals for receiving bits of a common weight and has three output terminals, one representing a sum value and the other two terminals representing carry-out values in redundant form. In the conventional Wallace tree structure, many of the input terminals to various basic adder units are forced to carry a zero bit value resulting in a Wallace tree structure that occupies significant area. It is desirable to reduce this circuit area. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, an adder tree structure includes at least two adder stages. In the circuit and method according to the present invention, the first of the two adder stages generates two bits of a common weight and other more significant bits of a weight one bit more significant than the two bits of the common weight. The second of the two adder stages includes an adder that receives the more significant bits generated in the first of the two adder stages. The second adder stage also includes an AND gate which receives and logically AND&#39;s the two bits of the common weight to generate a carry-in bit for the adder in the second stage. 
     The above adder tree structure and adding method permit more input terminals of adders to contain information about the input values to the adder tree structure. In other words, fewer input terminals of the adders of the adder tree structure are forced to ground thereby containing no information about the input values to the adder tree structure. Therefore, the adders are used more efficiently and less adders are required to perform a specific function. 
     The present invention will be more fully understood in view of the following drawings taken together with the detailed description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a modified Wallace tree according to the present invention. 
     FIG. 2 is a circuit diagram of the preliminary adder of FIG. 1. 
     FIG. 3 is a circuit diagram of the final adder of FIG. 1. 
     FIG. 4 is a schematic diagram of the basic adding unit of the tree structures of FIGS. 1, 2 and 3. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description refers to several figures. Throughout the description and figures, the same or similar elements are referred to with common reference symbols. 
     FIG. 1 is a schematic diagram of a modified Wallace tree 100 (&#34;tree 100&#34;) according to the present invention. The basic unit of tree 100 is the 4:2 adder shown in FIG. 4. Referring to FIG. 4, each adder n is configured to receive 5 input bits (e.g., A, B, C, D and E) and to generate bit an of the common weight and carry-out bits b n  and c n  according to the following Table 1. 
     
                       TABLE 1______________________________________# of values A, B,       # of values of b.sub.n  andC, D, and E which equal one             a.sub.n                   c.sub.n  that equal one______________________________________0                 0     01                 1     02                 0     13                 1     14                 0     25                 1     2______________________________________ 
    
     Thus, if bits A, B, C, D and E are of a common weight, bit a n  represents a sum bit of the common weight, while bits b n  and c n  represent carry bits one bit more significant than the common weight. Tree 100 works with any 4:2 adder configured according to Table 1. 
     Referring again to FIG. 1, tree 100 is configured to compress and add 64 two bit values i 0  [1:0], i 1  [1:0], . . . , i 62  [1:0] and i 63  [1:0] into an eight bit sum value z[7:0]. Tree 100 contains four preliminary adders 200a, 200b, 200c and 200d, which feed five bit sum values (e.g., bits j 0  [4:0], j 2  [4:0], j 4  [4:0] and j 6  [4:0], respectively) and carry values (e.g., bits j 1  [4:0], j 3  [4:0], j 5  [4:0] and j 7  [4:0], respectively to a final adder 300. The final adder 300 compresses the 4 five bit sum values and the 4 five bit carry values into a single sum value y[6:0] and a single carry value x[6:0]. A 2:1 adder tree 301 adds the sum and carry value together to generate the final sum value z[7:0]. 
     The details of preliminary adder 200a are described with reference to FIG. 2. Adder 200a includes fourteen 4:2 adders labeled, respectively, 1-14 in the upper left corners of the adders. Adder 1 receives the more significant bits i 0  [1], i 1  [1], i 2  [1] and i 3  [1] and adder 2 receives the less significant bits i 0  [0], i 1  [0], i 2  [0] and i 3  [0] of 4 two bit values i 0  [1:0], i 1  [1:0], i 2  [1:0] and i 3  [1:0]. The carry-in terminal of adder 2 is grounded while the carry-out bit c2 of adder 2 is received by adder 1. Each two-adder group formed by adders 3 and 4, 5 and 6, and 7 and 8 are configured to receive four of the two-bit values in a manner similar to bit groupings in adders 1 and 2. Using adders 1-8, bits a1 to a8, b1 to b8 and c1 to c8 are generated in Stage 1 of adder 200a in accordance with Table 1 and FIG. 4 and with weights according to Table 2. 
     
                       TABLE 2______________________________________Two bits more One bit moresignificant   significant Common weightthan bit i.sub.0 [0]         than bit i.sub.0 [0]                     with bit i.sub.0 [0]______________________________________c.sub.1, b.sub.1, c.sub.3, b.sub.3,         a.sub.1, b.sub.2, a.sub.3, b.sub.4,                     a.sub.2, a.sub.4, a.sub.6, a.sub.8c.sub.5, b.sub.5, c.sub.7, b.sub.7         a.sub.5, b.sub.6, a.sub.7, b.sub.8hereinafter,  hereinafter,                     hereinafter,&#34;Stage 1 2.sup.2         &#34;Stage 1 2.sup.1                     &#34;Stage 1 2.sup.0bits&#34;         bits&#34;       bits&#34;______________________________________ 
    
     In Stage 2 of adder 200a, four of the Stage 1 2 2  bits (e.g., bits c 1 , b 1 , c 3  and b 3 ) are received by adder 9 and four of the Stage 1 2 2  bits (e.g., bits c 5 , b 5 , c 7  and b 7 ) are received by adder 11. Four of the Stage 1 2 1  bits (e.g., bits a 1 , b 2 , a 3  and b 4 ) are received by adder 10 and four of the Stage 1 2 1  bits (e.g., bits a 5 , b 6 , a 7  and b 8 ) are received by adder 12. 
     Rather than requiring two additional 4:2 adders for receiving the stage 1 2 0  bits, an AND gate 202 receives Stage 1 2 0  bits a 2  and a 4  and generates bit f. An XOR gate 204 (or &#34;logic unit 204&#34;) also receives Stage 1 2 0  bits a 2  and a 4 , but generates bit d. An AND gate 212 receives Stage 1 2 0  bits a 6  and a 8  and generates bit g. An XOR gate 214 also receives Stage 1 2 0  bits a 6  and a 8 , but generates bit e. Bits f and g are carried in to respective adders 10 and 12. Bits c 10  and c 12  are carried into respective adders 9 and 11. As a result, bits a9 to a12, b9 to b12, c9 to c12, e and f are created with weights according to Table 3. 
     
                       TABLE 3______________________________________Three bits more     Two bits more                 One bit more                            Common weightsignificant     significant significant                            with bitthan bit i.sub.0 [0]     than bit i.sub.0 [0]                 than bit i.sub.0 [0]                            i.sub.0 [0]______________________________________c.sub.9, b.sub.9, c.sub.11,     a.sub.9, b.sub.10,                 a.sub.10  and a.sub.12                            d and eb.sub.11  a.sub.11, b.sub.12hereinafter,     hereinafter,                 hereinafter,                            hereinafter,&#34;Stage 2 2.sup.3     &#34;Stage 2    &#34;Stage 2   &#34;Stage 2bits&#34;     2.sup.2  bits&#34;                 2.sup.1  bits&#34;                            2.sup.0  bits&#34;______________________________________ 
    
     In Stage 3 of adder 200a, adder 13 receives all Stage 2 2 3  bits while adder 14 receives all Stage 2 2 2  bits. The carry-out bit c 14  is carried in to adder 13 while the carry-in terminal of adder 14 is grounded. Resulting bits c13, b13, a13, b14, a14, ground, a10, a12, d and e have weights as given in Table 4. 
     
                       TABLE 4______________________________________Four bits   Three     Two bits   One bit Commonmore signifi-   bits more more signifi-                        more signifi-                                weightcant than   significant             cant than  cant than                                with bitbit i.sub.0 [0]   than bit i.sub.0 [0]             bit i.sub.0 [0]                        bit i.sub.0 [0]                                i.sub.0 [0]______________________________________c.sub.13, b.sub.13   a.sub.13, b.sub.14             a.sub.14, ground                        a.sub.10, a.sub.12                                d, ehereinafter,   hereinafter,             hereinafter,                        hereinafter,                                hereinafter,j.sub.1 [4]   j.sub.1 [3]             j.sub.1 [2]                        j.sub.1 [1]                                j.sub.1 [0]and j.sub.0 [4],   and j.sub.0 [3],             and j.sub.0 [2],                        and j.sub.0 [1],                                and j.sub.0 [0],respectively   respectively             respectively                        respectively                                respectively______________________________________ 
    
     Thus, the sum of sixteen two bit values i 0  [1:0], i 1  [1:0], . . . , i 14  [1:0] and i 15  [1:0] is represented by values j 0  [4:0] and j 1  [4:0]. 
     Adders 200b, 200c and 200d may be structured similar to adder 200a. However, instead of receiving the sixteen two bits i 0  [1:0], i 1  [1:0], . . . , i 14  [1:0], i 15  [1:0], adder 200b receives bits i 16  [1:0], i 17  [1:0], . . . , i 30  [1:0], i 31  [1:0], adder 200c receives bits i 32  [1:0], i 33  [1:0], . . . , i 46  [1:0], i 47  [1:0], and adder 200d receives bits i 48  [1:0], i 49  [1:0], . . . , i 62  [1:0], i 63  [1:0]. Adder 200b generates bits j 2  [4:0] and j 3  [4:0], adder 200c generates bits j 4  [4:0] and j 5  [4:0], and adder 200d generates bits j 6  [4:0] and j 7  [4:0]. 
     As shown in FIG. 1 and FIG. 3, adder 300 receives values j 0  [4:0], j 1  [4:0], j 2  [4:0], j 3  [4:0], j 4  [4:0], j 5  [4:0], j 6  [4:0] and j 7  [4:0]. Adder 300 contains Stage IV which has ten 4:2 adders labeled 57 to 66. Adder 57 receives four of j 0  [4] to j 7  [4] (e.g., j 0  [4], j 1  [4], j 2  [4] and j 3  [4]) and adder 62 receives the remaining four of j 0  [4] to j 7  [4]. Similarly, adders 58 and 63 receive bits j 0  [3] to j 7  [3], adders 59 and 64 receive bits j 0  [2] to j 7  [2], adders 60 and 65 receive bits j 0  [1] to j 7  [1], and adders 61 and 66 receive bits j 0  [0] to j 7  [0]. A ripple carry chain propagates a carry bit through adders 61, 60, 59, 58 and 57, successively. Similarly, another ripple carry chain propagates a carry bit through adders 66, 65, 64, 63 and 62, successively. Stage 4 generates bits a 57  to a 66 , b 57  to b 66 , c 57  and c 62  with weights as in Table 5. 
     
                                           TABLE 5__________________________________________________________________________Five bits more  Four bits more         Three bits more                Two bits more                       One bit more                             Commonsignificant  significant         significant                significant                       significant                             weightthan bit i.sub.0 [0]  than bit i.sub.0 [0]         than bit i.sub.0 [0]                than bit i.sub.0 [0]                       than bit i.sub.0 [0]                             with bit i.sub.0 [0]__________________________________________________________________________c.sub.57, b.sub.57,  a.sub.57, b.sub.58,         a.sub.58, b.sub.59,                a.sub.59, b.sub.60,                       a.sub.60, b.sub.61,                             a.sub.61, a.sub.66c.sub.62, b.sub.62  a.sub.62, b.sub.63         a.sub.63, b.sub.64                a.sub.64, b.sub.65                       a.sub.65, b.sub.66hereinafter,  hereinafter,         hereinafter,                hereinafter,                       hereinafter,                             hereinafter,&#34;Stage 4  &#34;Stage 4         &#34;Stage 4                &#34;Stage 4                       &#34;Stage 4                             &#34;Stage 42.sup.5  bits&#34;  2.sup.4  bits&#34;         2.sup.3  bits&#34;                2.sup.2  bits&#34;                       2.sup.1  bits&#34;                             2.sup.0  bits&#34;__________________________________________________________________________ 
    
     Stage 5 has five 4:2 adders 67 to 71. Adder 67 receives all Stage 4 2 5  bits, adder 68 receives all Stage 4 2 4  bits, adder 69 receives all Stage 4 2 3  bits, adder 70 receives all Stage 4 2 2  bits, and adder 71 receives all Stage 4 2 1  bits. Adders 67 to 71 are connected by a rippled carry chain with the carry-in to adder 71 being ground. Stage 5 generates bits a 67  to a 71 , b 67  to b 71 , c 67  to c 71 , a 61  and a 66  with weights as in Table 6. 
     
                                           TABLE 6__________________________________________________________________________Six   Five  Four  Three Two   One   Commonbits more bits more       bits more             bits more                   bits more                         bit more                               weightsignificant significant       significant             significant                   significant                         significant                               with bitthan bit i.sub.0 [0] than bit i.sub.0 [0]       than bit i.sub.0 [0]             than bit i.sub.0 [0]                   than bit i.sub.0 [0]                         than bit i.sub.0 [0]                               i.sub.0 [0]__________________________________________________________________________c.sub.67, b.sub.67 a.sub.67, b.sub.68       a.sub.68, b.sub.69             a.sub.69, b.sub.70                   a.sub.70, b.sub.71                         a.sub.71, ground                               a.sub.61, b.sub.66hereinafter, hereinafter,       hereinafter,             hereinafter,                   hereinafter,                         hereinafter,                               hereinafter,&#34;x[6]&#34; and &#34;x[5]&#34; and       &#34;x[4]&#34; and             &#34;x[3]&#34; and                   &#34;x[2]&#34; and                         &#34;x[1]&#34; and                               &#34;x[0]&#34; and&#34;y[6]&#34;, &#34;y[5]&#34;,       &#34;y[4]&#34;,             &#34;y[3]&#34;,                   &#34;y[2]&#34;,                         &#34;y[1]&#34;,                               &#34;y[0]&#34;,respectively respectively       respectively             respectively                   respectively                         respectively                               respectively__________________________________________________________________________ 
    
     Thus, the sum of sixty-four two bit values i 0  [1:0], i 1  [1:0], . . . , i 62  [1:0] and i 63  [1:0] is represented by values x[6:0] and y[6:0]. 2:1 adder tree 301 (FIG. 1) receives values x[6:0] and y[6:0] and generates the final sum z[7:0]. 
     Throughout the description and claims, &#34;AND gate&#34; and &#34;XOR gate&#34; means any circuit capable of generating a bit representing the logical AND and XOR, respectively, of the input bits. 
     Although the invention has been described in connection with a specific embodiment, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications which would be apparent to one of ordinary skill in the art. Thus, the invention is limited only by the following claims.