Abstract:
In a time division multiplex video reproducing apparatus, a dual purpose memory serves to (a) perform time compression for time division multiplexing and (b) perform as a variable delay line for time base error correction. Seemingly unavoidable conflicts in the allocation of memory space (between multiplexing operations and time base error correction operations) are eliminated by performing the time base error correction operations during a memory idle time inherent in the time division multiplexing process. As a result, time base error correction in this invention requires little additional hardware and no additional space in the memory beyond that required for time division multiplexing.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention is related to video tape recorder and playback systems employing time division multiplexing and requiring time base error correction. 
     2. Description of the Related Art 
     Video tape recorder and playback systems using time division multiplexing are well known in the art, one exemplary description being given in a patent application Ser. No. 725,873 entitled &#34;VIDEO REPRODUCING APPARATUS&#34; filed by Carl Nelson Schauffele on Apr. 22, 1985. Another description is given in U.S. Pat. No. 4,300,161. Time division demultiplexing typically requires a switch to divide the video signal into time segments, and a memory to time-decompress each of the segments. 
     PROBLEM 
     A significant problem with video tape recorders such as video cassette recorders (VCR&#39;s) involves time base errors. This problem is particularly acute in VCR&#39;s using time division multiplexing (TDM). Specifically, the required accuracy for time base error correction is increased in approximate proportion of the time compression of the TDM format. 
     Various techniques are known for effecting time base error correction, such as those exemplified in U.S. Pat. Nos. 4,099,204, 4,283,744 and 4,297,728. These time base error correction techniques require additional hardware such as delay lines and are not specifically adapted to TDM VCR&#39;s. 
     U.S. Pat. No. 4,084,181 to Mita et al. discloses a TDM VCR in which timing errors are corrected by varying, in a phase lock loop, the clock signal frequency thereof using a voltage controlled oscillator (VCO). However, the range of correctable error in this technique is limited by the maximum phase difference which the phase lock loop is capable of handling. 
     In summary, prior time base error correction techniques are of only limited value in TDM VCR&#39;s. It appears that a complete time base error correction system useful in TDM VCR&#39;s and having the capacity to correct a large range of errors would require additional circuitry and would therefore increase the manufacturing cost, a significant disadvantage. Therefore, there is a great need for a time base error correction system for use in TDM VCR&#39;s which is accurate, has a large error correction capacity and does not require a significant amount of additional circuitry. 
     SUMMARY OF THE INVENTION 
     Solution To The Problem 
     In this invention, the TDM memory ordinarily required to perform time compression for time division multiplexing is used for a dual purpose, namely to perform time compression for multiplexing and to act as a variable delay line under the control of a time base error correction control loop. Thus, time base error correction (time delay) and TDM multiplexing (time compression) are accomplished together in this invention without requiring additional memories or delay lines, a significant advantage. 
     One problem encountered in implementing this solution is that, in a typical well-designed TDM VCR, nearly all of the memory is used in the time division multiplexing process. Thus, unless more memory is added, the multiplexing and time delay operations cannot have their own separate allocations of memory space and therefore would apparently conflict. This seemingly unavoidable conflict is eliminated by performing the time delay function only during a recurring interval of time in the multiplexing process in which the memory is essentially idle. (This idle time is attributable to the time compression function performed by the memory.) As a result, the variable delay line function for time base error correction requires no separate or additional space in the memory beyond that already allocated to the time compression function for multiplexing. 
     Specifically in TDM memory demultiplex/time decompression operations, there is an idle time window following the completion of the writing-in of the various serial time-compressed segments (e.g., the luminance and chrominance segments) of each horizontal line of video data. Readout from memory of the plurality of video segments comprising one horizontal line must commence sometime within the idle time window. The duration of the idle time window is a function of the difference between the time required to serially write in all time compressed video segments of each horizontal line and the time allotted to read them out in parallel. (It is also a function of the manner in which the memory is partitioned, as will be described later herein.) 
     In this invention, a time base error correction control loop varies the time delay between the completion of each memory write operation and commencement of the next memory read operation (the &#34;write-read time delay&#34;) strictly within the idle time window. For example, during playback of a video signal previously recorded in TDM format, the time of commencement of each memory read operation is varied within the idle time window by a comparator which compares a reference horizontal sync pulse with the playback video signal horizontal sync pulse. If the comparator senses a time difference between the two sync pulses, it changes the write-read time delay in subsequent horizontal video lines. 
     A principal advantage of the invention is that the dual use of the memory for both TDM time compression and as a variable delay line not only results in hardware savings and design simplicity but also provides a large capacity for time base error correction proportional to the duration of the idle time window of the memory. 
     While it will be appreciated that various well-known devices may be employed to vary the memory write-read time delay in accordance with the invention, a digital control loop is preferred because it is readily adapted to operate within a range that takes full advantage of the entire memory idle time window, thereby guaranteeing the maximum possible error correction capacity. In the preferred digital control loop, the write and read timing in the memory is locked to the frequency of the incoming horizontal sync pulse, but the read timing (only) is phase shifted with respect to the incoming horizontal sync pulse whenever necessary to maintain the read timing constant with respect to absolute time. However, this phase shift never exceeds the memory idle time window. The start time of the reading out of memory of each horizontal video line is controlled by a divide counter stimulated by each incoming horizontal sync pulse to count pulses from an oscillator. The modulus of the divide counter is set by an up/down counter having its output connected to the input of the divide counter. The sync pulse comparator causes the up/down counter to increment or decrement the divide counter modulus by one count each time the comparator senses that an incoming horizontal sync pulse is either early or late, respectively. The capacity of the up/down counter is selected to just accommodate the maximum possible change in the write-read time delay within the memory idle time window. 
     DESCRIPTION OF THE DRAWINGS 
     The invention may best be understood by reference to the accompanying drawings, of which: 
     FIG. 1 is a simplified block diagram illustrating the basic concept of the invention; 
     FIGS. 2a and b are simplified block diagrams illustrating TDM playback and record systems, respectively, embodying the invention; 
     FIG. 3 is a simplified logic diagram of the sync comparator of FIG. 2; 
     FIG. 4 is a simplified block diagram of a three-way partitioned TDM memory useful in the system of FIG. 2; 
     FIG. 5 includes contemporaneous timing diagrams illustrating the operation of the system of FIG. 2 in playback mode; and 
     FIG. 6 includes contemporaneous timing diagrams illustrating the operation of the system of FIG. 2 in record mode. 
    
    
     DETAILED DESCRIPTION 
     Prior Art 
     1. TDM Recording 
     Each horizontal video line of an incoming composite video signal is separated into its three video components Y, I and Q. The Y, I and Q components are digitally sampled at frequencies f 1 , f 2  and f 3 , respectively, and separately stored in Y, I and Q memories, respectively. The Y, I and Q components are then read out of memory during three respective time division multiplexing intervals at a frequency f 4 , converted to analog, FM modulated and recorded on a video tape. 
     2. TDM Playback 
     The playback process is the reverse of the recording process. The Y, I and Q video components of each horizontal video line played back from the video tape are FM demodulated and digitally sampled at the frequency f 4  during their respective time division intervals. They are then loaded into the Y, I and Q memories, respectively. Next, the Y, I and Q components are simultaneously unloaded from memory at the frequencies f 1 , f 2 , and f 3 , respectively, converted to analog and combined to form a composite video signal. 
     CONCEPT OF THE INVENTION 
     Referring to FIG. 1, a TDM VCR system configured in playback mode includes a video tape 1a, a head and drum assembly 1b and TDM memory 2. One horizontal line of a TDM video signal played back from the tape 1a includes three time-compressed color components Y, I and Q and the usual synchronization pulses. These components are separated by a demultiplexing switch 3 and written (loaded) sequentially into respective Y, I and Q memories 2a, 2b, 2c within the memory 2. They are then simultaneously read out (unloaded) from the memory 2 to generate one horizontal line of a composite video signal in the well-known manner. Alternatively, the demultiplexed Y, I and Q components are not combined into a composite video signal but are transmitted separately in parallel. 
     Ordinarily, adding a time base error correction function with a large error correction capacity to such a system would entail adding hardware including variable delay lines capable of storing about one horizontal line of video data for each of the video components Y, I and Q. The present invention adds a time base error correction function having a large error correction capacity without adding delay lines to the system. Instead, the variable delay line function required for time base error correction is incorporated into the already existing TDM memory 2 without requiring additional memory space and without conflicts between the TDM function (already performed by the TDM memory 2 as just described) and the variable delay line function, a remarkable result. 
     The manner in which this result is obtained by the invention is best understood by first considering an often-overlooked feature of the typical TDM playback system: Referring to FIG. 1, there is an idle time window of limited duration following the completion of the serial writing (loading) into the memory 2 of the three components Y, I and Q, of each horizontal line of the TDM video signal. Commencement of the simultaneous reading (unloading) out of the memory 2 of these Y, I and Q components must occur sometime within the idle time window in order to avoid conflicting with the writing in of the next horizontal line of video data. Otherwise, such a conflict would disrupt the video signal. The duration of the idle time window is constant and is a function of the time period p write  (see FIG. 1) required to write into the memory 2 the serial Y, I and Q components of each horizontal video line, and the time period p read  (see FIG. 1) allotted to read them out of the memory 2. 
     Assuming that each of the Y, I and Q memories 2a, 2b, 2c is divided into two sub-memories Y1, Y2; I1, I2; Q1, Q2, as shown in FIG. 1, which alternate every horizontal line between the reading out of one horizontal line of video data and the writing in of the next horizontal line of video data, the duration D of the memory idle time window is just equal to p write  -p read . The commencement of each memory read operation must occur sometime within the idle time window duration D=p write  -p read  following the completion of the previous memory write operation. The duration of the idle time window may be further expanded by dividing each of the Y, I and Q memories into three (or more) sub-memories, and this will be discussed later herein in greater detail. The write-read time delay between the completion of a memory write operation and the commencement of the next memory read operation may be therefore no greater than the duration D of the memory idle time window and may be virtually as small as zero. 
     In this invention, the write-read delay is varied (strictly within the limits of the memory idle time window) by a write-read delay controller 8 in such a manner as to compensate for time base errors. The controller 8 responds to a comparison -- made by a sync comparator 10 -- between the incoming horizontal sync pulse H sync  received from the switch 3 and a reference (local) horizontal sync pulse H&#39; sync  furnished by a highly stable reference sync pulse generator 14, which may include a crystal controlled oscillator. The local horizontal sync pulse H&#39; sync  may be generated by the generator 14 in accordance with the invention disclosed in U.S. patent application Ser. No. 915,487, filed Oct. 6, 1986, entitled &#34;Noise-Impervious Video Timing Recovery and Automatic Skew Compensation&#34;, by William K. Hickok. In the absence of any time base errors in the incoming H sync  pulse, the reference H&#39; sync  pulse and the incoming H sync  pulse have the same frequency and phase. They are of different phases whenever a time base error occurs. 
     In case of a variation in the timing of the incoming H sync  pulse, the write-read delay is changed so as to compensate for the variation. The variation in the write-read time delay thus provided has the effect of a variable time delay. A principal advantage of the invention illustrated in FIG. 1 is that the variable delay line function performed by the TDM memory 2 under the control of the comparator 10 requires no other space in the memory 2 besides the memory space already allocated to store each horizontal line of video data for the time-decompression/demultiplexing operation. Instead of realizing the variable delay line function as additional memory space in the TDM memory 2, the delay line function is realized instead as a shift in time of the memory write-read delay (but strictly within the memory idle time window during which such a shift will not interfere with the demultiplexing operation). Thus, the invention avoids any conflicts in memory use without requiring additional memory space. 
     PLAYBACK SYSTEM DESIGN 
     FIG. 2a is a block diagram illustrating the TDM playback system of the invention. It includes the switch 3, and Y, I and Q analog-to-digital converters 28, 30, 32, each having its input connected to the Y, I and Q outputs, respectively, of the switch 3. The switch 3 operates in synchronism with the H sync  pulse of the playback TDM video signal derived through a sync pulse separator 4. The outputs of the analog-to-digital converters 28, 30 and 32 are applied to the write inputs of the Y, I and Q memories 2a, 2b, 2c, respectively, whose read outputs are applied to the inputs of Y, I and Q digital-to-analog converters 40, 42, 44, respectively. The outputs of the digital-to-analog converters 40, 42, 44 are combined in a circuit 46. While the term &#34;memory&#34; is applied herein to the three devices 2a, 2b, 2c of FIG. 2, they may be three serial shift registers or three random access memories or any other equivalent form. 
     The write inputs of the Y, I and Q memories 2a, 2b, 2c operate at the data sampling frequency f 4 . For this purpose, write timing logic 48 transmits to the Y, I and Q memories write enable signals WRITE-Y , WRITE-I, WRITE-Q in synchronism with the incoming H sync  pulse during the individual TDM intervals of the Y, I and Q components, respectively. 
     The read-out from memory of data corresponding to even and odd numbered horizontal video lines is controlled by READ ENABLE 1 and READ ENABLE 2 logic signals, respectively, applied to respective portions of each of the memories 2a, 2b, 2c. For example, the READ ENABLE 1 and 2 signals are applied to the Y1 and Y2 memories, respectively. The Y, I and Q video data previously written into memory is simultaneously read out at the three different frequencies f, f 2  and f 3 , respectively. 
     TIME BASE ERROR CORRECTION 
     A time base error correction digital control system controlling the READ ENABLE logic signals will now be described. The incoming H sync  pulse is applied to a &#34;start count&#34; input of a divide counter 50. The divide counter 50 begins counting pulses, from a voltage controlled oscillator (VCO) 52, by a modulus M with the occurrence of each incoming H sync  pulse. Read timing logic 60 produces one of the READ ENABLE signals each time the divide counter 50 reaches its maximum count, 2 N  -1. The VCO 52 is phase-locked with the pulse generator 14 through a phase lock loop 53 in the well-known manner. 
     The divide counter modulus M is determined by the output of an N-bit up/down counter 54 whose count and up/down control inputs 54a, 54b, respectively, are controlled by the sync pulse comparator 10. The sync pulse comparator 10 receives the incoming H&#39; sync  pulse through the switch 3 and receives the reference horizontal sync pulse H&#39; sync  from the reference pulse generator 14. Each time the comparator 10 determines that the previous incoming H sync  pulse is either early or late with respect to the reference H&#39; sync  pulse, it transmits a count pulse to the count input 54a of the up/down counter 54 and transmits a high (late) or a low (early) up/down signal, respectively, to the up/down input 54b of the up/down counter 54. 
     Prior to operation, the up/down counter 54 is initialized with an N-bit word corresponding to the modulus M of the divide counter 50. Whenever the sync comparator 10 senses a late incoming H sync  pulse, for example, the up/down counter 54 counts up by one so that the modulus of the divide counter 50 decreases by one. This incrementally advances the occurrence of the next READ ENABLE pulse (by one VCO count) with respect to the timing of the incoming H sync  pulse, and therefore decreases the delay between the end of the present write operation and the beginning of the next read operation in each memory 2a, 2b, 2c. 
     The digital control system just described is just one of a number of ways that the variable read-write time delay 8 of FIG. 1 could be implemented in accordance with the present invention. However, the digital control system described here is readily endowed with a capacity for tracking large time base errors precisely within the memory idle time window. The capacity to track time base errors may be increased by increasing the number N of bits of the two counters 50, 54 or by decreasing the frequency of the VCO 52 and the initial modulus M of the divide counter 50, or any combination of the foregoing. The number N of bits of the counters 50, 54 and the period T of the VCO 52 are preferably chosen so that the maximum shift, (2 N  -1)T, in the write-read time delay just equals the duration D of the memory idle time window. Thus, the system will correct an ever-increasing time base error, for example, until the error exceeds D, after which no further corrections will be made. The maximum error correction capacity therefore lies just within the strict confines of the memory idle time window, avoiding any conflict between memory write and read operations. 
     One of skill in the art may readily implement the sync pulse comparator 10 of FIG. 2. One example is illustrated in FIG. 3. The comparator 10 receives the H sync  and H&#39; sync  pulses at its inputs 10a, 10b and generates the &#34;count&#34; and &#34;up/down&#34; signals at its outputs 10c, 10d, respectively. Each &#34;Delay τ&#34; depicted in FIG. 3 is less than half the H&#39; sync  pulse width. The pulse width of both One Shot #1 and One Shot #2 is (1/2)D-τ. The delay of One Shot #2 is the period of the H&#39; sync  pulse minus twice the pulse width of One Shot #1. This arrangement helps prevent the comparator 10 from exceeding the range of the counters 50, 54. The three delays (labeled &#34;Delay τ&#34; in FIG. 3) serve to limit the duty cycle of the up/down counter 54. 
     MULTIPLEX MEMORY PARTITIONING 
     A technique for avoiding conflicts between simultaneous memory write and read operations is to partition or divide each memory 2a, 2b, 2c into two sub-memories and to alternate simultaneous read and write operations between the sub-memories, as mentioned previously. As illustrated in FIG. 1, each Y, I and Q memory 2a, 2b, 2c is partitioned or divided into two sub-memories Y1, Y2; I1, I2; Q1, Q2, each sub-memory storing one complete line of video information and each sub-memory pair being operated together in complementary fashion. As previously described in reference to FIG. 1, the memory idle time window duration D of this arrangement is no greater than p write  -p read . 
     The memory idle time window duration D, within which the READ ENABLE logic signals are shifted in this invention, may be increased by dividing each of the memories 2a, 2b, 2c into three sub-memories (or more) instead of two. This advantageously increases the maximum time base error that the system is capable of correcting. FIG. 4 illustrates the division of each of the Y, I and Q memories 2a, 2b, 2c into three sub-memories Y1, Y2, Y3; I1, I2, I3; Q1, Q2, Q3, respectively. In the Y memory 2a, for example, writing one line of video data into the Y1 sub-memory is accompanied by reading the previous line of data from the Y2 sub-memory while the Y3 sub-memory is idle for a time period p write . (It will be recalled p write  is the time required to write one line of video data into memory.) Subsequently, reading out data from the Y2 sub-memory is accompanied by writing in data to the Y3 sub-memory while the Y1 sub-memory is idle for a time period p write . Reading and writing in the I and Q memories 2b, 2c occurs in the same manner as in the Y memory 2a. Thus, by partitioning each memory 2a, 2b, 2c into three sub-memories instead of two, the memory idle time window duration is increased by the time period p write . In the embodiment of FIG. 4, the READ ENABLE logic signals may be shifted in time over a much larger window to correct much larger time base errors. Accordingly, the error correction capacity of the time base error correction system of FIG. 2 may be increased by adding to the capacity of the Y, I and Q TDM memories 2a, 2b, 2c. 
     PLAYBACK SYSTEM OPERATION 
     Playback operation of the system of FIG. 2 will now be described with reference to FIG. 5. In the example of FIG. 5, it is assumed each of the memories 2a, 2b, 2c of FIG. 2 is partitioned into sub-memory pairs, as illustrated in FIG. 1. 
     WRITE TIMING 
     In FIGS. 5d-i, alternate horizontal video lines of the serial succession of Y, I and Q components of the incoming TDM video signal of FIG. 5c are written (loaded) into alternate ones of the Y1, I1, Q1 sub-memories and the Y2, I2, Q2 sub-memories, respectively, in order of occurrence. Thus, the Y component of video line 1 is written into the Y1 sub-memory between times t 0  and t 1  (FIG. 5d), the line 1 I component is written into the I1 sub-memory between times t 1  and t 2  (FIG. 5e) and the line 1 Q component is written into the Q1 sub-memory between times t 2  and t 3  (FIG. 5f). Each of the three components, Y, I, Q, of the second line of the incoming TDM video signal of FIG. 5c are written in a similar manner into the Y2, I2 and Q2 sub-memories, respectively, between times t 3  and t 6  as illustrated in FIGS. 5g, h and i. Thus, the Y1, I1, Q1 sub-memories are ready for simultaneous read-out of their contents at time t 3  while the Y2, I2, Q2 sub-memories are ready at time t 6 . 
     READ TIMING 
     Reading (unloading of data from the Y1, I1 and Q1 sub-memories occurs simultaneously in synchronism with the READ ENABLE 1 logic signal of FIG. 5a. Reading from the Y2, I2 and Q2 sub-memories occurs simultaneously in synchronism with the READ ENABLE 2 logic signal of FIG. 5b. 
     The first line (and each subsequent odd number line) of the demultiplexed video signal of FIG. 5j is read out from the Y1, I1, Q1 sub-memories. Reading of the first line occurs from time t 4  to time t 5 , as illustrated in FIGS. 5d, e and f. The second line (and each subsequent even number line) of the demultiplexed video signal of FIG. 5j is read out from the Y2, I2, Q2 sub-memories. Reading of the second line occurs from time t 7  to time t 9 , as illustrated in FIGS. 5g, h and i. Reading of the first video line occupies a time interval p read  between times t 4  and t 5  and must lie within a restrictive envelope of duration p write  starting at time t 3  and ending at time t 6  (which is after the Y1, I1 and Q1 sub-memories are fully loaded and before receipt of the next odd number video line to be written). Otherwise, conflicts may arise between the writing and successive reading of the same line of video data in memory or between the simultaneous writing and reading of two successive lines of data in memory. A similar restriction applies to reading from the Y2, I2 and Q2 sub-memories. 
     Initially, in the absence of any time base errors, each read period p read  (e.g., from time t 4  to time t 5 ) is arranged symmetrically with respect to the corresponding restrictive envelope p write  to accommodate the maximum shift of the read period p read  in either direction within the restrictive envelope. In order to remain within the restrictive envelope p write , the read period time-shift must not exceed D/2=(p write  -p read )/2 in either direction. 
     OPERATION OF THE TIME BASE ERROR CORRECTION CONTROL LOOP 
     Referring to FIG. 5c, a time base error occurs at time t 7  because incoming video line 3, which should have arrived earlier, is late. Therefore, at time t 7 , the comparator 10 detects a late incoming H sync  pulse and transmits a count pulse and a high up/down signal to the count and up/down inputs 54a, b, respectively, of the up/down counter 54. This decrements by one the modulus M of the divide counter 52. As a result, the next READ ENABLE 1 pulse occurring at time t 11  is advanced with respect to the incoming H sync  pulse timing by one VCO count. The next READ ENABLE 2 pulse is similarly advanced. 
     The result is that the timing of the output demultiplexed video signal of FIG. 5j is unaffected by the time base error which occurred in the incoming multiplexed video signal of FIG. 5c at time t 7 . 
     In this very simple example, an advance by one VCO count in the READ ENABLE pulse timing, with respect to the H sync  pulse timing, shifted the read period by the maximum allowable amount--to the beginning edge of the restrictive envelope. Therefore, the maximum swing in the up/down counter 54 would be just a few VCO counts, and the idle time window D would correspond to only about two VCO counts. In the preferred embodiment, however, the idle time window D would correspond to 256 VCO counts, the counter 50 would have eight bits, and the correction of a single time base error may occur over the course of several horizontal video lines. 
     The digital control loop comprising the comparator 10, the counters 50, 54 and the VCO 52 maintains the timing of the READ ENABLE pulses of FIGS. 5a and b constant with respect to absolute time--but not necessarily with respect to the incoming H sync  pulse timing--as long as the time base error does not exceed one-half the memory idle time window duration D in either direction of time. Thus, the digital loop prevents the system from exceeding the limits of the idle time window duration D. At the same time, the digital loop locks the frequency of the READ ENABLE signals of FIGS. 5a and b to the frequency of the incoming H sync  pulse. 
     RECORD SYSTEM 
     The system of FIG. 2b may be employed with great advantage to perform time base error correction during TDM recording of an incoming composite video signal produced by, for example, another video tape player. The incoming video signal to be recorded may contain large time base errors (due, for example, to the defective condition or inferior quality of the other video tape player), which errors ought to be removed prior to recording. In this invention, time base error correction is performed during the multiplexing process prior to recording. 
     Referring to FIG. 2b, an incoming composite video signal which is to be recorded is separated by a filter 80 into its constituent Y, I and Q components. The Y, I and Q components (FIG. 6d) are then fed through the Y, I and Q analog-to-digital converters 28, 30 and 32 to the Y, I and Q memories 2a, 2b, 2c, respectively. A WRITE ENABLE signal initiates simultaneous writing of the Y, I and Q video signals into the memories 2a, 2b, 2c at the frequencies f 1 , f 2 , f 3 , respectively. The WRITE ENABLE signal is synchronized by the write timing logic with the incoming H sync  pulse. 
     Reading out from each of the Y, I and Q memories 2a, 2b, 2c is performed sequentially at the data frequency f 4 , respectively. The three video signals sequentially read-out of the three memories 2a, 2b, 2c are combined serially in the circuit 46 prior to recording to form the multiplexed video signal of FIG. 6e. 
     Three signals, READ-Y, READ-I, READ-Q (FIGS. 6a, 6b, 6c) applied to the memory read control inputs 2a&#39;, 2b&#39;, 2c&#39; (instead of the READ ENABLE signals) control the sequence of reading from the memories 2a, 2b, 2c, respectively. These three signals are produced in synchronism with the VCO 52 whose output is fed to the divide counter 50. The N-bit output of the divide counter 50 is fed to a timing logic circuit 60 which generates the READ-Y, READ-I, READ-Q signals. 
     The comparator 10 receives the incoming H sync  pulse and the reference H&#39; sync  pulse. The comparator 10 controls the up/down counter 54 in the manner discussed previously in reference to playback operation. In the event of a time base error indicated by a late or early incoming H sync  pulse, the comparator 10 causes the up/down counter 54 to count up or down, respectively. This shifts the timing of the READ-Y, READ-I and READ-Q signals with respect to the timing of the incoming H sync  pulse in order to compensate for the time base error. 
     In summary, the invention frequency-locks the multiplexing or demultiplexing of a video signal to its horizontal line frequency and simultaneously time-shifts the signal to perform time base error correction using just the TDM memory, without requiring any additional memory space, and while avoiding conflicting uses of the memory, a remarkable achievement. 
     The invention has been described in detail with particular reference to preferred embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.