Abstract:
A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner spacer of a first material and a second nanosheet FET structure having second inner spacer of a second material. The first material is different than the second material.

Description:
BACKGROUND 
     Semiconductor structures or devices may be embodied as field effect transistors (FETs), such as metal-oxide-semi conductor FETs (MOSFETs). One or more such FETs may comprise an integrated circuit (IC or chip). As ICs are being scaled to smaller dimensions, stacked nanosheet FETs, or nanosheet FETs, have been developed to increase effective conduction width in a given area. A nanosheet is a nanostructure with a thickness in a scale ranging from, e.g., about 1 to 100 nanometers (nm). A nanosheet FET is a FET that is formed by stacking multiple such nanostructures. 
     SUMMARY 
     Illustrative embodiments of the invention provide techniques for fabricating nanosheet semiconductor structures. 
     For example, in one embodiment, a method for forming a nanosheet semiconductor structure comprises forming a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having a second inner spacer comprised of a second material. The first material is different than the second material. In one example, the first nanosheet FET structure is an n-type FET structure and the second nanosheet FET structure is a p-type FET structure. The first nanosheet FET structure and the second nanosheet FET structure are collectively formed to construct a hybrid channel nanosheet semiconductor structure. 
     For example, the forming step further comprises creating a first inner spacer formation within a first silicon germanium (SiGe) channel comprised in a first channel region of a first FET region, and a second inner spacer formation within a second SiGe channel comprised in a second channel region of a second FET region. The first SiGe channel is formed from one or more SiGe nanosheets and the second SiGe channel is formed from one or more second SiGe nanosheets. A first sacrificial liner is deposited on the first FET region and a second sacrificial liner is deposited on the second FET region. A mask is formed on the second sacrificial liner, and a source/drain region is formed on a first silicon (Si) channel of the first channel region. The first Si channel is formed from one or more first Si nanosheets. The mask and the first and second sacrificial liners are removed. A third inner spacer formation is created within a second Si channel comprised in the second channel region, and a source/drain region is formed on the second SiGe channel. The second Si channel is formed from one or more second Si nanosheets. The first source/drain region is filled with a first oxide and the second source/drain region is filled with a second oxide. A first gate of the first FET region is replaced with a first metal and the first SiGe channel is replaced with a first work function metal. A second gate of the second FET region is replaced with a second metal and the second Si channel is replaced with a second work function metal. 
     By way of further example, creating the first inner spacer formation comprises forming a first divot within the first SiGe channel and filling the first divot with a first ceramic material, and creating the second inner spacer formation comprises forming a second divot within the second SiGe channel and filling the second divot with a second ceramic material. For example, the first and/or ceramic material may be comprised of silicon-boron-carbide-nitride (SiBCN). In one illustrative embodiment, creating the third inner spacer region comprises forming a divot within the second Si channel and filling the divot with a silicate glass. For example, the silicate glass may be silicon oxycarbide (SiCO). 
     In another embodiment, a nanosheet semiconductor structure comprises a first nanosheet FET structure having a first inner spacer comprised of a first material, and a second nanosheet FET structure having a second inner spacer comprised of a second material. The first material is different than the second material. 
     In a further embodiment, an integrated circuit comprises a first nanosheet FET structure having a first inner spacer comprised of a first material, and a second nanosheet FET structure having a second inner spacer comprised of a second material. The first material is different than the second material. 
     These and other exemplary embodiments of the invention will be described in or become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a schematic cross-sectional side view of a portion of a semiconductor device at a first-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1B  is a schematic cross-sectional side view of a portion of a semiconductor device at a second-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1C  is a schematic cross-sectional side view of a portion of a semiconductor device at a third-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1D  is a schematic cross-sectional side view of a portion of a semiconductor device at a fourth-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1E  is a schematic cross-sectional side view of a portion of a semiconductor device at a fifth-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1F  is a schematic cross-sectional side view of a portion of a semiconductor device at a sixth-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1G  is a schematic cross-sectional side view of a portion of a semiconductor device at a seventh-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1H  is a schematic cross-sectional side view of a portion of a semiconductor device at an eighth-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1I  is a schematic cross-sectional side view of a portion of a semiconductor device at a ninth-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1J  is a schematic cross-sectional side view of a portion of a semiconductor device at a tenth-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1K  is a schematic cross-sectional side view of a portion of a semiconductor device at an eleventh-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1L  is a schematic cross-sectional side view of a portion of a semiconductor device at a twelfth-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1M  is a schematic cross-sectional side view of a portion of a semiconductor device at a thirteenth-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1N  is a schematic cross-sectional side view of a portion of a semiconductor device at a fourteenth-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1O  is a schematic cross-sectional side view of a portion of a semiconductor device at a fifteenth-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1P  is a schematic cross-sectional side view of a portion of a semiconductor device at a sixteenth-intermediate fabrication stage, according to an embodiment of the invention. 
         FIG. 1Q  is a schematic cross-sectional side view of a portion of a semiconductor device at a seventeenth-intermediate fabrication stage, according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     In illustrative embodiments, techniques are provided for fabricating semiconductor devices comprised of one or more FETs. More particularly, illustrative embodiments provide techniques for fabricating semiconductor devices comprised of one or more hybrid channel nanosheet FETS. As will be explained in illustrative embodiments, such fabrication techniques advantageously improve performance of semiconductor devices. While illustrative embodiments are described herein with respect to hybrid channel nanosheet FETs, alternative embodiments may be implemented with other types of semiconductor structures. 
     Furthermore, it is to be understood that embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to fabrication (forming or processing) steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the steps that may be used to form a functional integrated circuit device. Rather, certain steps that are commonly used in fabricating such devices are purposefully not described herein for economy of description. 
     Moreover, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, layers, regions, or structures, and thus, a detailed explanation of the same or similar features, elements, layers, regions, or structures will not be repeated for each of the drawings. It is to be understood that the terms “about,” “approximately” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error is present such as, by way of example only, 1% or less than the stated amount. Also, in the figures, the illustrated scale of one layer, structure, and/or region relative to another layer, structure, and/or region is not necessarily intended to represent actual scale. 
       FIGS. 1A-1Q  illustrate an exemplary process for fabricating a semiconductor structure for increasing control of fin reveal in a dense fin region.  FIG. 1A  illustrates a semiconductor structure  100  at a first-intermediate fabrication stage. For the purpose of clarity, several fabrication steps leading up to the production of the semiconductor structure  100  as illustrated in  FIG. 1A  are omitted. In other words, semiconductor structure  100  does not necessarily start out in the form illustrated in  FIG. 1A , but may develop into the illustrated structure over one or more well-known processing steps which are not illustrated but are well-known to those of ordinary skill in the art. Also, note that the same reference numeral ( 100 ) is used to denote the semiconductor structure through the various intermediate fabrication stages illustrated in  FIGS. 1A through 1Q . Note also that semiconductor structure  100  can also be considered to be a semiconductor device and/or an integrated circuit, or some part thereof. Still further, note that details for any etching, deposition, forming steps mentioned herein that are not specifically specified may be performed using conventional fabrication processes known to those of ordinary skill in the art. 
     Semiconductor structure  100  in  FIG. 1A  is shown having n-FET region  102 A comprising stack  104 A and p-FET region  102 B comprising stack  104 B. In one embodiment, the stacks may be formed on top of a substrate layer (not expressly shown). Each stack is comprised of a substrate and alternating nanosheets of material arranged on the substrate. In one embodiment, each nanosheet may have a thickness ranging from about 1 nm to about 100 nm. For example, as shown in this illustrative embodiment, stack  104 A is comprised of substrate  103 A and nanosheets  105 A. In one embodiment, and as shown, substrate  103 A is comprised of silicon (Si). As shown, nanosheets  105 A may comprise alternating nanosheets comprised of silicon-germanium (SiGe) and nanosheets comprised of Si. It is to be understood that the arrangement of SiGe and Si nanosheets on the substrate, including the number of nanosheets, is purely exemplary and should not be considered limiting. 
       FIG. 1B  illustrates semiconductor structure  100  at a second-intermediate fabrication stage. During this stage, pad insulator  106 A is formed on stack  104 A, and pad insulator  106 B is formed on stack  104 B. Gate  108 A is formed on pad insulator  106 A and gate  108 B is formed on pad insulator  106 B. Gate hard mask  110 A is formed on gate  108 A and gate hard mask  110 B is formed on gate  108 B. Spacer  112 A is deposited along n-FET region  102 A and spacer  112 B is deposited along p-FET region  102 B, as shown in  FIG. 1B . Accordingly, gate formation and spacer deposition occur in the fabrication stage illustrated in  FIG. 1B . 
       FIG. 1C  illustrates semiconductor structure  100  at a third-intermediate fabrication stage. During this stage, n-FET region  102 A and p-FET region  102 B are each etched as shown to form channel regions  113 A and  113 B. Accordingly, the nanosheets of each FET region form respective channel regions of the semiconductor structure. 
       FIG. 1D  illustrates semiconductor structure  100  at a fourth-intermediate fabrication stage. During this stage, divots are created within channel region  113 A and channel region  113 B via an etching process (e.g., an isotropic etching process), and each divot is filled with an inner spacer. For example, as shown, the divots of channel region  113 A are filled with inner spacer  114 A, and the divots of channel region  113 B are filled with inner spacer  114 B. In one embodiment, inner spacer  114 A and inner spacer  114 B are comprised of a ceramic material. For example, inner spacer  114 A and/or inner spacer  114 B may be comprised of silicon-boron-carbide-nitride (SiBCN). However, any suitable material may be implemented for use as an inner spacer in accordance with the embodiments described herein. 
       FIG. 1E  illustrates semiconductor structure  100  at a fifth-intermediate fabrication stage. During this stage, sacrificial liner  116 A is deposited on n-FET region  102 A and sacrificial liner  116 B is deposited on p-FET region  102 B. In one embodiment, sacrificial liners  116 A and  116 B are comprised of a ceramic material. For example, sacrificial liners  116 A and/or  116 B may be comprised of SiBCN. However, any suitable material may be implemented for use as a sacrificial liner in accordance with the embodiments described herein. 
       FIG. 1F  illustrates semiconductor structure  100  at a sixth-intermediate fabrication stage. During this stage, mask  118 B is patterned on sacrificial liner  116 B. The function of mask  118  is to protect p-FET region  102 B. After mask  118  is patterned on sacrificial liner  116 B, sacrificial liner  116 A is removed. 
       FIG. 1G  illustrates semiconductor structure  100  at a seventh-intermediate fabrication stage. During this stage, the source/drain region  120 A of n-FET region  102 A is created by growing an epitaxial layer along the Si channel of channel region  113 A of n-FET region  102 A, as shown. In one embodiment, the epitaxial layer along the Si channel of channel region  113 A is grown via high temperature epitaxy with phosphorus (P) implantation. Additionally, mask  118 B is removed from p-FET region  102 B. 
       FIG. 1H  illustrates semiconductor structure  100  at an eighth-intermediate fabrication stage. During this stage, sacrificial liner  121 A is deposited on n-FET region  102 A and sacrificial liner  121 B is deposited on p-FET region  102 B (i.e., along sacrificial liner  116 B). Sacrificial liner  121 A protects the epitaxial layer of source/drain region  120 A. 
       FIG. 1I  illustrates semiconductor structure  100  at a ninth-intermediate fabrication stage. During this stage, mask  118 A is patterned on sacrificial liner  121 A. The function of mask  118 A is to protect n-FET region  102 A. After mask  118 A is patterned on sacrificial liner  121 A, sacrificial liners  116 B and  121 B are removed from p-FET region  102 B. 
       FIG. 1J  illustrates semiconductor structure  100  at a tenth-intermediate fabrication stage. During this stage, divots are created within the Si channel of channel region  113 B of p-FET region  102 B via an etching process, inner spacer material is deposited within the divots (e.g., inner spacer  122 B), and mask  118 A is removed. In one embodiment, the etching process is isotropic. Inner spacer  122 B may be comprised of a silicate glass. For example, inner spacer  122 B may be comprised of silicon oxycarbide (SiCO). However, any material may be implemented for use as an inner spacer in accordance with the embodiments described herein. In one embodiment, the width of inner spacer  122 B is smaller than the width of inner spacer  114 B to avoid exposing the SiGe channel of channel region  113 B. Accordingly, conformal liner deposition is performed to create a SiCO inner spacer for the Si channel of channel region  113 B. 
       FIG. 1K  illustrates semiconductor structure  100  at an eleventh-intermediate fabrication stage. During this stage, inner spacer  114 B is removed, and source/drain region  120 B of p-FET region  102 B is created by growing an epitaxial layer along the SiGe channel of channel region  113 B of p-FET region  102 B, as shown. In one embodiment, the epitaxial layer along the SiGe channel of channel region  113 B is grown via high temperature epitaxy with Ge implantation. After source/drain region  120 B is created, mask  118 A is removed. 
       FIG. 1L  illustrates semiconductor structure  100  at a twelfth-intermediate fabrication stage. During this stage, interlayer dielectric  128 A is formed on source/drain region  120 A of n-FET region  102 A, and interlayer dielectric  128 B is formed on source/drain region  120 B of p-FET region  102 B. In one embodiment, interlayer dielectric  128 A and interlayer dielectric  128 B are comprised of an oxide. However, interlayer dielectrics  128 A and  128 B may be comprised of any dielectric material in accordance with the embodiments described herein. 
       FIG. 1M  illustrates semiconductor structure  100  at a thirteenth-intermediate fabrication stage. During this stage, a polysilicon pull process, or “poly-pull” process, is performed to remove the gate from n-FET region  102 A, and a channel release is performed to remove the SiGe portion of channel region  113 A. In one embodiment, performing the poly-pull process and channel release comprises performing an isotropic SiGe etch selective to Si. 
       FIG. 1N  illustrates semiconductor structure  100  at a fourteenth-intermediate fabrication stage. During this stage, work function metal  130 A is deposited in channel region  113 A to replace the channel released from channel region  113 A. In one embodiment work function metal  130 A is deposited via a conformal atomic layer deposition (ALD) process. As further shown, metal  132 A is deposited to replace gate  108 A. Metal  132 A may be tungsten (W), but any metal may be used in accordance with the embodiments described herein. In one embodiment, metal  132 A is deposited via a chemical vapor deposition (CVD) process. For example, metal  132 A may be deposited via plasma-enhanced CVD (PECVD). A chemical mechanical planarization (CMP) may be performed after metal  132 A is deposited. 
       FIG. 1O  illustrates semiconductor structure  100  at a fifteenth-intermediate fabrication stage. During this stage, a “poly-pull” process is performed to remove the gate from p-FET region  102 B, and a channel release is performed to remove the Si portion of channel region  113 B. 
       FIG. 1P  illustrates semiconductor structure  100  at a sixteenth-intermediate fabrication stage. During this stage, work function metal  130 B is deposited in channel region  113 A to replace the Si channel released from channel region  113 B. In one embodiment work function metal  130 B is deposited via a conformal ALD process. As further shown, metal  132 B is deposited to replace gate  108 B. Metal  132 B may be W, but any metal may be used in accordance with the embodiments described herein. In one embodiment, metal  132 B is deposited via a CVD process. For example, metal  132 B may be deposited via PECVD. A chemical mechanical planarization (CMP) may be performed after metal  132 B is deposited. 
       FIG. 1Q  illustrates semiconductor structure  100  at a seventeenth-intermediate fabrication stage. During this stage, metal  132 A and metal  132 B are recessed, and gate cap layers  134 A and  134 B are formed on n-FET region  102 A and p-FET region  102 B, respectively, to create a self-aligned source/drain contact. In one embodiment, gate cap layers  134 A and  134 B are formed by etching metal  132 A and  132 B to form recesses and depositing gate cap material within the recesses. A CMP process may be performed to remove excess portions of the deposited gate cap material (i.e., to remove overflow material). The gate cap material may be comprised of silicon mononitride (SiN). However, any material may be used as gate cap material in accordance with the embodiments described herein. Accordingly, the embodiments described herein provide for a method for fabricating a hybrid channel nanosheet FET. 
     It is to be understood that the methods discussed herein for fabricating semiconductor structures can be incorporated within semiconductor processing flows for fabricating other types of semiconductor devices and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as transistors, diodes, capacitors, inductors, etc. An integrated circuit in accordance with embodiments can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. 
     Furthermore, various layers, regions, and/or structures described above may be implemented in integrated circuits (chips). The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
     Although illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope or spirit of the invention.