Abstract:
A mixing circuit for combining biasing and signals using a selectively variable signal gain which is independent of the biasing and using biasing which is independent of the selectively variable signal gain. A Gilbert cell is used to multiply a differential control voltage, which represents a normalized signal gain factor, with input currents which include biasing components and input signal components. The resultant output current includes a bias component which is independent of the differential control voltage and a signal component which is independent of the input current biasing components. The gain factor has a value between zero and unity which varies in relation to the differential input control voltage.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to adaptive signal equalizers for adaptively equalizing high data rate signals received via long lengths of cable, and in particular, to gain controllers for controlling the signal gain of such adaptive signal equalizers. 
     2. Description of the Related Art 
     As part of the process of recovering data which has been transmitted over a long length of cable at a high data rate, equalization of the received data signal is required in order to compensate for the loss and phase dispersion characteristics of the cable. For example, referring to FIG. 1, the signal losses associated with a cable increase with frequency, and such signal losses become greater as the cable length is increased from a virtually zero length L 0  to greater cable lengths L 1 , L 2 , L 3 , . . . . Therefore, higher order frequency components of the data signal become increasingly attenuated as compared to the lower order frequency components. Accordingly, the degree of signal equalization required increases with frequency as well as cable length. 
     Further, in those applications where the transmission cable lengths may vary, such equalization must be adaptive by being able to adapt to variations in the transfer function of the cable due to variations in the cable length. 
     Referring to FIG. 2, a conventional adaptive equalizer 20 includes a unity-gain buffer 22, a high-pass filter 24, a mixer 26 and a signal summation stage 28, interconnected as shown. The input signal V i  is processed by both the unity-gain buffer stage 22 and filtered by the high-pass filter 24. The high-pass filtered signal 25 is mixed with a gain control signal a in the mixer 26. The unity-gain buffered signal 23 and gain-controlled, high-pass filtered signal 27 are summed together in the summation circuit 28 to produce the final output signal V O . 
     Referring to FIG. 3, it can be seen that by varying the value of the control signal α, the overall gain of the high-pass filter profile can be adjusted, thereby providing for adaptive equalization of the output signal V O . 
     While this conventional technique performs reasonably well, a number of disadvantages exist, particularly when more precise equalization control is desired. For example, depending upon a number of operating parameters of the equalization circuit 20, such as variations in processing during manufacturing and variations in operating voltages and temperatures, the gain factor α may affect the DC biasing of portions of the circuit 20. Further, the output signal V O  may be affected by variations in the DC bias components within the circuit 20. Accordingly, it would be desirable to have a gain-controlled adaptive equalizer in which the output signal is independent of DC bias conditions and in which DC bias conditions are independent of the gain control input. 
     SUMMARY OF THE INVENTION 
     A gain controller for an adaptive equalizer in accordance with the present invention provides an output signal which is independent of DC bias conditions and maintains DC bias conditions which are independent of the gain control input. Such a gain controller includes a circuit for combining biasing and signals with a selectively variable signal gain which is independent of such biasing and with biasing which is independent of such selectively variable signal gain. 
     In accordance with one embodiment of the present invention, a circuit for combining biasing and signals with a selectively variable signal gain which is independent of the biasing and with biasing which is independent of the selectively variable signal gain includes differential amplifier circuits and circuit nodes. A first differential amplifier circuit is configured to receive and multiply a first single-ended input current and a differential input control voltage and in accordance therewith provide a first differential output current. The first single-ended input current includes a bias component and a signal component, the differential input control voltage includes noninverse and inverse components, and the first differential output current includes noninverse and inverse components. A second differential amplifier circuit is configured to receive and multiply a second single-ended input current and the differential input control voltage and in accordance therewith provide a second differential output current. The second single-ended input current is substantially equal to the first single-ended input current bias component, and the second differential output current includes noninverse and inverse components. A first node, coupled to the first and second differential amplifier circuits, is configured to receive and combine a third single-ended input current, the first differential output current inverse component and the second differential output current noninverse component and in accordance therewith provide a first single-ended output current. The third single-ended input current includes a bias component and a signal component, and the first single-ended output current includes a bias component and a signal component. The first single-ended output current bias component is substantially equal to a sum of the second single-ended input current and the third single-ended input current bias component and is substantially independent of the differential input control voltage. The first single-ended output current signal component is substantially equal to a sum of the third single-ended input current signal component and a product of the first single-ended input current signal component and a gain factor and is substantially independent of the first and third single-ended input current bias components and the second single-ended input current. The gain factor has a value between zero and unity which varies in relation to the differential input control voltage. A second node, coupled to the first and second differential amplifier circuits, is configured to receive and combine the first differential output current noninverse component and the second differential output current inverse component and in accordance therewith provide a second single-ended output current. The second single-ended output current includes a bias component and a signal component. The second single-ended output current bias component is substantially equal to the first single-ended input current bias component and is substantially independent of the differential input control voltage. The second single-ended output current signal component is substantially equal to a product of the first single-ended input current signal component and a difference between unity and the gain factor and is substantially independent of the first and third single-ended input current bias components and the second single-ended input current. 
     In accordance with another embodiment of the present invention, a circuit for mixing biasing and signals with a selectively variable signal gain which is independent of the biasing and with biasing which is independent of the selectively variable signal gain includes transistors and shared terminals. A first transistor includes a first input terminal configured to receive a noninverse component of a differential input control voltage, a second input terminal configured to receive a first portion of a first single-ended input current with a bias component and a signal component, and a first output terminal configured to provide an inverse component of a first differential output current. A second transistor includes a third input terminal configured to receive an inverse component of the differential input control voltage, a fourth input terminal configured to receive a second portion of the first single-ended input current, and a second output terminal configured to provide a noninverse component of the first differential output current. A third transistor includes a fifth input terminal configured to receive the differential input control voltage inverse component, a sixth input terminal configured to receive a first portion of a second single-ended input current, wherein the second single-ended input current is substantially equal to the first single-ended input current bias component, and a third output terminal configured to provide a noninverse component of a second differential output current. A fourth transistor includes a seventh input terminal configured to receive the differential input control voltage noninverse component, an eighth input terminal configured to receive a second portion of the second single-ended input current, and a fourth output terminal configured to provide an inverse component of the second differential output current. A first shared terminal, coupled to the first and third output terminals, is configured to receive and combine a third single-ended input current, the first differential output current inverse component and the second differential output current noninverse component and in accordance therewith provide a first single-ended output current. The third single-ended input current includes a bias component and a signal component, and the first single-ended output current includes a bias component and a signal component. The first single-ended output current bias component is substantially equal to a sum of the second single-ended input current and the third single-ended input current bias component and is substantially independent of the differential input control voltage. The first single-ended output current signal component is substantially equal to a sum of the third single-ended input current signal component and a product of the first single-ended input current signal component and a gain factor and is substantially independent of the first and third single-ended input current bias components and the second single-ended input current. The gain factor has a value between zero and unity which varies in relation to the differential input control voltage. A second shared terminal, coupled to the second and fourth output terminals, is configured to receive and combine the first differential output current noninverse component and the second differential output current inverse component and in accordance therewith provide a second single-ended output current. The second single-ended output current includes a bias component and a signal component. The second single-ended output current bias component is substantially equal to the first single-ended input current bias component and is substantially independent of the differential input control voltage. The second single-ended output current signal component is substantially equal to a product of the first single-ended input current signal component and a difference between unity and the gain factor and is substantially independent of the first and third single-ended input current bias components and the second single-ended input current. 
     In accordance with still another embodiment of the present invention, a method of combining biasing and signals with a selectively variable signal gain which is independent of the biasing and with biasing which is independent of the selectively variable signal gain includes the steps of: 
     receiving a first single-ended input current which includes a bias component and a signal component; 
     receiving a second single-ended input current which is substantially equal to the first single-ended input current bias component; 
     receiving a third single-ended input current which includes a bias component and a signal component; 
     receiving a differential input control voltage which includes noninverse and inverse components; 
     multiplying the first single-ended input current and the differential input control voltage and in accordance therewith generating a first differential output current which includes noninverse and inverse components; 
     multiplying the second single-ended input current and the differential input control voltage and in accordance therewith generating a second differential output current which includes noninverse and inverse components; 
     combining the third single-ended input current, the first differential output current inverse component and the second differential output current noninverse component and in accordance therewith generating a first single-ended output current, wherein 
     the first single-ended output current includes a bias component and a signal component, 
     the first single-ended output current bias component is substantially equal to a sum of the second single-ended input current and the third single-ended input current bias component and is substantially independent of the differential input control voltage, 
     the first single-ended output current signal component is substantially equal to a sum of the third single-ended input current signal component and a product of the first single-ended input current signal component and a gain factor and is substantially independent of the first and third single-ended input current bias components and the second single-ended input current, and 
     the gain factor has a value between zero and unity which varies in relation to the differential input control voltage; and 
     combining the first differential output current noninverse component and the second differential output current inverse component and in accordance therewith generating a second single-ended output current, wherein 
     the second single-ended output current includes a bias component and a signal component, 
     the second single-ended output current bias component is substantially equal to the first single-ended input current bias component and is substantially independent of the differential input control voltage, and 
     the second single-ended output current signal component is substantially equal to a product of the first single-ended input current signal component and a difference between unity and the gain factor and is substantially independent of the first and third single-ended input current bias components and the second single-ended input current. 
     In accordance with yet another embodiment of the present invention, a method of mixing biasing and signals with a selectively variable signal gain which is independent of the biasing and with biasing which is independent of the selectively variable signal gain includes the steps of: 
     receiving, via a first input terminal of a first transistor, a noninverse component of a differential input control voltage; 
     receiving, via a second input terminal of the first transistor, a first portion of a first single-ended input current which includes a bias component and a signal component; 
     outputting, via a first output terminal of the first transistor, an inverse component of a first differential output current; 
     receiving, via a third input terminal of a second transistor, an inverse component of the differential input control voltage; 
     receiving, via a fourth input terminal of the second transistor, a second portion of the first single-ended input current; 
     outputting, via a second output terminal of the second transistor, a noninverse component of the first differential output current; 
     receiving, via a fifth input terminal of a third transistor, the differential input control voltage inverse component; 
     receiving, via a sixth input terminal of the third transistor, a first portion of a second single-ended input current, wherein the second single-ended input current is substantially equal to the first single-ended input current bias component; 
     outputting, via a third output terminal of the third transistor, a noninverse component of a second differential output current; 
     receiving, via a seventh input terminal of a fourth transistor, the differential input control voltage noninverse component; 
     receiving, via an eighth input terminal of the fourth transistor, a second portion of the second single-ended input current; 
     outputting, via a fourth output terminal of the fourth transistor, an inverse component of the second differential output current; 
     receiving a third single-ended input current which includes a bias component and a signal component; 
     via a first shared terminal, receiving and combining the third single-ended input current, the first differential output current inverse component and the second differential output current noninverse component and in accordance therewith generating a first single-ended output current, wherein 
     the first single-ended output current includes a bias component and a signal component, 
     the first single-ended output current bias component is substantially equal to a sum of the second single-ended input current and the third single-ended input current bias component and is substantially independent of the differential input control voltage, and 
     the first single-ended output current signal component is substantially equal to a sum of the third single-ended input current signal component and a product of the first single-ended input current signal component and a gain factor and is substantially independent of the first and third single-ended input current bias components and the second single-ended input current, wherein the gain factor has a value between zero and unity which varies in relation to the differential input control voltage; and 
     via a second shared terminal, receiving and combining the first differential output current noninverse component and the second differential output current inverse component and in accordance therewith generating a second single-ended output current, wherein 
     the second single-ended output current includes a bias component and a signal component, 
     the second single-ended output current bias component is substantially equal to the first single-ended input current bias component and is substantially independent of the differential input control voltage, and 
     the second single-ended output current signal component is substantially equal to a product of the first single-ended input current signal component and a difference between unity and the gain factor and is substantially independent of the first and third single-ended input current bias components and the second single-ended input current. 
     These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a graph of gain versus frequency for illustrating the complementary relationship between signal strength and corresponding equalization provided by a signal equalizer. 
     FIG. 2 is a functional block diagram of a conventional adaptive signal equalizer. 
     FIG. 3 is a graph of gain versus frequency for the gain-controlled, high-pass filtered portion of the equalizer of FIG. 2. 
     FIG. 4 is a functional block diagram of an adaptive signal equalizer in accordance with one embodiment of the present invention. 
     FIG. 5 is a schematic diagram of the unity-gain, voltage-to-current converter stage of the circuit of FIG. 4. 
     FIG. 6 is a schematic diagram of the high-pass, voltage-to-current converter stage of the circuit of FIG. 4. 
     FIG. 7 is a schematic diagram of the &#34;noninverse component&#34; section of the variable-gain mixer stage of the circuit of FIG. 4. 
     FIG. 8 is a functional block diagram of the gain controller and tracking circuit stage of the circuit of FIG. 4. 
     FIG. 9 is a graph of the voltage versus gain factor for the digital-to-analog converter stage of the circuit of FIG. 8. 
     FIG. 10 is a schematic diagram of the gain control level generator stage of the circuit of FIG. 8. 
     FIG. 11 is a schematic diagram of the &#34;noninverse component&#34; section of the current-to-voltage converter stage of the circuit of FIG. 4. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 4, an adaptive equalizer 40 in accordance with one embodiment of the present invention includes a unity-gain voltage-to-current converter 50, a high-pass voltage-to-current converter 60, a variable-gain mixer 70, a gain controller and tracking circuit 80 and a current-to-voltage converter 110, interconnected substantially as shown. The input signal voltage V i  (which is differential with noninverse V i   +   and inverse V i   -   components) is buffered by the unity-gain voltage-to-current converter 50 which is biased by a bias current I Bias  to produce a differential output current signal (I 1  +i 1 )/(I 1  -i 1 ) which includes a bias component I 1  and a signal component i 1 . (As should be understood, the bias component is that which is due to the DC biasing of the circuit, while the signal component is that which is due to the input signal.) The input signal V i  is also high-pass filtered by the high-pass voltage-to-current converter 60, which is also biased by the DC bias current I Bias . This stage 60 produces a differential high-pass filtered signal (I H (f) +i H (f))/(I H (f) -i H (f)) which includes a bias component I H (f) and a signal component i H (f). Both of these signals (I 1  +i 1 )/(I 1  -i 1 ), (I H (f) +i H (f))/(I H (f) -i H (f)) are provided to the variable-gain mixer 70. 
     The gain controller and tracking circuit 80 is also biased by the DC bias current I Bias , and receives a digital (e.g., 8-bit) gain control signal α. In accordance with such gain control signal α, the gain controller and tracking circuit 80 generates a differential gain control signal V c , which has a noninverse component V c   +  and an inverse component V c   - . These differential control voltage components V c   + , V c   -   are provided to the variable-gain mixer 70. 
     The variable-gain mixer 70 is also biased by the DC bias current I Bias . In accordance with the control voltage components V c   + , V c   - , which represent the gain factor α, the variable gain mixer 70 mixes its three input current signals: the DC bias current I Bias  ; the unity-gain current signal (I 1  +i 1 ); and the high-pass filtered current signal (I H (f) +i H (f))/(I H (f) -i H (f)). Based upon the mixing of these signals, the variable-gain mixer 70 generates an output current (I O  +i O )/(I O  -i O ) which includes a bias component I O  and a signal component i O . 
     The output current (I O  +i O )/(I O  -i O ) from the variable-gain mixer 70 is converted to an output voltage V O  (which is differential with noninverse V O   +   and inverse V O   -  components) by the current-to-voltage converter 110. 
     Referring to FIG. 5, the unity-gain voltage-to-current converter 50 includes a differential amplifier combined with two current mirrors biased between the positive VDD and negative VSS/GND terminals of the power supply. The differential amplifier includes transistors P51, P52, N51, N52, N53 and N54 (the prefix &#34;P&#34; designates a P-channel metal oxide semiconductor field effect transistor (P-MOSFET) and the prefix &#34;N&#34; designates an N-channel MOSFET (N-MOSFET)). The bias current mirror includes transistors N55, N53 and N54. The signal current mirror includes transistors P51, P52, P53 and P54. 
     The DC biasing for the differential amplifier includes driving the bias current mirror with the DC bias current I Bias , The gain for the differential amplifier is established by a resistor R connected between the two differential amplifier circuit branches. The inputs to the differential amplifier are driven by the noninverse V i   +   and inverse V i   -   components of the differential input signal voltage V i . The resulting differential currents, i.e., the drain currents of transistors N51 and N52, are replicated by the signal current mirror to produce a differential output current with a noninverse component (I 1  +i 1 ) and an inverse component (I 1  -i 1 ). The bias component I 1  is that component of the output current signal which corresponds to the DC biasing for the circuit, i.e., the input DC bias current I Bias  The signal component i 1  is that component of the output current signal which corresponds to the input signal, i.e., the input signal voltage V i . 
     Referring to FIG. 6, the high-pass voltage-to-current converter 60 also includes a differential amplifier combined with two current mirror circuits biased between the positive VDD and negative VSS/GND terminals of the power supply. The differential amplifier includes transistors P61, P62, N61, N62, N63 and N64. The bias current mirror includes transistors N65, N63 and N64. The signal current mirror includes transistors P61, P62, P63 and P64. 
     The DC biasing for the differential amplifier includes driving the input to the bias current mirror with the DC bias current I Bias . The high-pass filter transfer function for the differential amplifier is established by connecting a high-pass filter circuit 62 between the two differential amplifier circuit branches. The differential amplifier is driven by the noninverse V i   +   and inverse V i   -   components of the differential input signal voltage V i . The resulting differential currents, i.e., the drain currents of transistors N61 and N62, are replicated by the signal current mirror to provide a differential output current with a noninverse component (I H (f) +i H (f)) and an inverse component (I H (f) -i H (f)). The bias component I H (f) and signal component i H (f) of the output current signals correspond to the DC bias current I Bias  and input signal voltage V i , respectively. 
     Referring to FIG. 7, the &#34;noninverse component&#34; section 70n of the variable-gain mixer 70 includes two cross-connected differential amplifier circuits: transistors N71 and N72; and transistors N73 and N74. (Only that portion 70n of the variable-gain mixer 70 which is responsible for processing the noninverse components of the differential signals is shown here; however, it should be understood that a similar section is used for processing the inverse components.) All of the differential amplifier transistors N71, N72, N73, N74 have equal channel widths W A  and lengths L A . The first differential amplifier is driven by the noninverse component (I H (f) +i H (f)) of the high-pass filtered signal current and the differential control voltage V c  (which represents the gain factor α). This results in a differential output current with an inverse component (I 01   -  +i 01   - ) which is provided to an output summing node 72 and a noninverse component (I 01   +  +i 01   + ) which is provided to a &#34;discard&#34; summing node 74. 
     The second differential amplifier is driven by the DC bias current I Bias  and the differential control voltage V c . This produces a differential output current with a noninverse component (I 02   + ) which is provided to the output summing node 72 and an inverse component (I 02   - ) which is provided to the &#34;discard&#34; summing node 74. The output summing node 72 also receives the noninverse unity-gain signal current component (I 1  +i 1 ) and sums it together with the first inverse differential output current component (I 01   31  +i 01   - ) and second noninverse differential output current component (I 02   + ) to produce an output current (I O  +i O ). Similarly, the &#34;discard node&#34; 74 sums together the second noninverse differential output current component (I 01   +  +i 01   + ) and second inverse differential output current component (I 02   - ) to produce a &#34;discard&#34; current (I D  +i D ). 
     The output current (I O  +i O ) can be expressed in terms of the DC bias current I Bias , the gain factor α (represented by the differential gain control signal V c ), the high-pass signal component (I H (f) +i H (f)) and the unity-gain signal current component (I 1  +i 1 ) as shown below in Equation 1. 
     
         I.sub.O +i.sub.O =(I.sub.1 +i.sub.1)+α(I.sub.H(f) +i.sub.H(f))+(1-α)(I.sub.Bias)                      Eq. 1 
    
     This expression can be rewritten to separate the bias and signal components as shown below in Equation 2. 
     
         I.sub.O +i.sub.O =(i.sub.1 +αi.sub.H(f))+(I.sub.1 +αI.sub.H(f) +(1-α)I.sub.Bias)                                   Eq. 2 
    
     Accordingly, the signal i O  and bias I O  output current components can be expressed as shown below in Equations 3 and 4, respectively. 
     
         i.sub.O =i.sub.1 +αi.sub.H(f)                        Eq. 3 
    
     
         I.sub.O =I.sub.1 +αI.sub.H(f) +I.sub.bias -αI.sub.BiasEq. 4 
    
     With the bias component I H (f) of the high-pass filtered signal current component (I H (f) +i H (f)) equal to the DC bias current I Bias  the bias component I O  of the output current (I O  +i O ) can be expressed as shown below in Equation 5. 
     
         I.sub.O =I.sub.1 +I.sub.Bias                               Eq. 5 
    
     Similarly, the &#34;discard&#34; current (I D  +i D ) can be expressed as shown below in Equation 6. 
     
         I.sub.D +i.sub.D =(1-α)(I.sub.H(f) +i.sub.H(f))+αI.sub.BiasEq.6 
    
     This expression can be rewritten to show its dependence upon the gain control actor α as shown below in Equation 7. 
     
         I.sub.D +i.sub.D =I.sub.H(f) -α(I.sub.H(f) -I.sub.Bias)+(1-α)i.sub.H(f)                        Eq. 7 
    
     Accordingly, the signal i D  and bias I D  current components can be expressed as shown below in Equations 8 and 9, respectively. 
     
         i.sub.D =(1-α)i.sub.H(f)                             Eq. 8 
    
     
         I.sub.D =I.sub.H(f) -αI.sub.H(f) +αI.sub.Bias  Eq. 9 
    
     With the bias component I H (f) of the high-pass filtered signal (I H (f) +i H (f)) equal to the DC bias current I Bias , as noted above, the &#34;discard&#34; current bias component I D  can be expressed as shown below in Equation 10. 
     
         I.sub.D =I.sub.H(f)                                        Eq. 10 
    
     Referring to FIG. 8, a gain controller and tracking circuit 80 (FIG. 4) in accordance with one embodiment of the present invention includes a digital-to-analog converter 82 and a gain control level generator 100. (Alternatively, instead of a digital-to-analog converter, a pulse density modulator could be used.) The digital-to-analog converter 82 converts the digital gain control factor a into the differential control voltage components V c   + , V c   -   used by the variable-gain mixer 70. These differential control voltage components V c   + , V c   -   are generated based upon two reference voltages V High , V Low  provided by the gain control level generator 100 which is biased by the DC bias current I Bias . 
     Referring to FIG. 9, the differential control voltage components V c   + , V c   -   vary in value, in a differential manner, between the low V Low  and high V High  reference voltage values, in accordance with the value of the gain control factor α. For example, when the gain control factor α is equal to zero, the noninverse V c   +   and inverse V c   -   components are equal to the high V High  and low V Low  reference voltages, respectively. Conversely, when α is at its maximum value, e.g., FF(hex), the noninverse V c   +   and inverse V c   -   control voltage components are equal to the low V Low  and high V High  reference voltages, respectively. 
     Referring to FIG. 10, a gain control level generator 100 (FIG. 8) in accordance with one embodiment of the present invention includes four transistors P101, P102, P103, P104, a diode 103 and five current sources 101, 102, 104, 105, 106, all interconnected substantially as shown. Transistors P101 (with channel width and length dimensions of W B  and L B , respectively) and P102 (with channel width and length dimensions of W C  and L C , respectively) are biased by a current source circuit 102 and current sink circuit 101, each of which generates a bias current I B . The diode 103 is used to reduce the voltage drop across transistor P102, but is not necessary and, therefore, can be omitted by connecting the drain of transistor P102 directly to VSS/GND. Transistors P101 and P102 have identical threshold voltages V th  and respective gate-to-source &#34;on&#34; voltages V on (P101) and V on (P102). Accordingly, the compensated voltage V(PVT) generated at the source of transistor P102 can be expressed as shown below in Equation 11. 
     
         V(PVT)=VDD-V.sub.gs(P101) +V.sub.gs(P102)                  Eq. 11 
    
     This expression can be rewritten by substituting for the gate-to-source voltages V gs (P101) and V gs (P102) of transistors P101 and P102, respectively, as shown below in Equation 12. 
     
         V(PVT)=VDD-(V.sub.th +V.sub.on(P101))+(V.sub.th +V.sub.on(P102))Eq. 12 
    
     Simplifying further, this expression reduces to that shown below in Equation 13. 
     
         V(PVT)=VDD-(V.sub.on(P101) -V.sub.on(P102))                Eq. 13 
    
     Accordingly, the voltage V on  across current sources 102 and 104, which is set equal to or greater than the required voltage V P64  across the current mirror transistor P64 providing the noninverse component of the high-pass filtered signal (I H (f) +i H (f)) in the high-pass voltage-to-current converter 60 (FIG. 6), can be expressed as shown below in Equation 14. 
     
         V.sub.on =V.sub.on(P101) -V.sub.on(P102)                   Eq. 14 
    
     This voltage V(PVT) is used, along with current sources 104, 105 and 106 to bias transistors P103 and P104 to generate the high V High  and low V Low  reference voltages. Diode-connected transistors P103 and P104 have equal channel width W A  and length L A  dimensions, which also equal the corresponding device dimensions of the transistors in the variable-gain mixer 70 (FIG. 7). Current source circuit 104 and sink circuit 105 generate bias currents I Bias  equal to the DC bias currents I Bias  used to bias the unity-gain voltage-to-current converter 50, the high-pass voltage-to-current converter 60 and the variable-gain mixer 70 (FIG. 4). Current sink circuit 106 generates a trickle current I T  which is very low in value and is used to maintain transistor P104 in a minimal on state. 
     This circuit 100, because of the above-noted relationships between bias currents I Bias  and transistor channel dimensions W A , L A , generates the high V High  and low V Low  reference voltages such that these voltages V High , V Low  track variations in the bias current I Bias  as well as variations in the operating parameters of the transistors such as threshold voltage and charge carrier mobility. In turn, this allows the output current signal (I O  +i O ) to also track variations in the bias current I Bias  as well as variations in the operating parameters of the transistors such as threshold voltage and charge carrier mobility (e.g., due to variations in manufacturing processes and operating voltages and temperatures). 
     Referring to FIG. 11, the &#34;noninverse component&#34; section 110n of the output current-to-voltage converter 110 (FIG. 4) can be implemented as follows. (Only that portion 110n of the output current-to-voltage converter 110 which is responsible for processing the noninverse component of the differential output current is shown here; however, it should be understood that a similar section is used for processing the inverse component.) The output current signal (I O  +i O ) drives the input to a current mirror formed by transistors N111 and N112. The output current through transistor N112 produces a voltage drop across the load resistor R L , thereby generating the output voltage V O   + . 
     Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.