Abstract:
A single cell voltage reference operates under low power supply requirements to provide a configurable voltage reference. The single cell voltage reference includes a diode device that is biased as a voltage source. Two series connected resistive devices are connected in parallel with the diode device. The diode is biased with a current that is proportional to delta Vbe/R, such that the impedance of the diode tracks R. Another current source that is also proportional to delta Vbe/R is provided at the junction of the two resistors such that the voltage across one of the two resistors may be employed as a reference voltage that is less than 1.2V. The ratio of the resistors and scales the reference voltage level. Voltages that are below 1.2V are provided that are temperature compensated similar to a band-gap reference. The diode voltage as driven by a current source determines the lower limit of the reference voltage. The reference voltage may be combined with a buffer or an operational amplifier such that a regulated supply can be provided that is below 1.2V. Metal masks may be arranged to permit reconfiguration of the voltage reference cell for use above 1.2V, or to change the regulation voltage without redesigning the voltage reference cell.

Description:
FIELD OF THE INVENTION 
     The present invention is related to a method and system for generating a low voltage reference that operates with a low power supply voltage. More particularly, the present invention is related to a single cell voltage reference that operates on low-voltage power supplies such as a single cell battery. 
     BACKGROUND OF THE INVENTION 
     Band-gap voltage references are used as voltage references in electronic systems. The energy band-gap of Silicon is on the order of 1.2V, and is independent from temperature and power supply variations. Bipolar transistors have a negative temperature drift with respect to their base-emitter voltage (Vbe decreases as operating temperature increases on the order of −2 mV/deg C.). However, the thermal voltage of a bipolar transistor has a positive temperature drift (Vt=kT/q, thus Vt increases as temperature increases). The positive temperature drift in the thermal voltage (Vt) may be arranged to compensate the negative temperature drift in the bipolar transistor&#39;s base-emitter voltage. Band-gap reference circuits use the inherent characteristics of bipolar transistors to compensate for temperature effects and provide a stable operating voltage over various power supply and temperature ranges. 
     One example bandgap reference circuit includes two bipolar transistors that are arranged with a common base. Two resistors are series connected between the emitter of the first bipolar transistor and a common ground. The emitter of second bipolar transistor is connected to the common point between the two resistors. The two bipolar transistors are arranged to provide a ten-to-one (10:1) current density difference with respect to one another. The ten-to-one current density results in a 60 mV difference between the base-emitter voltages of two bipolar transistors (ΔVbe=Vt*ln(I 1 /I 2 )=26 mV*ln( 10 )=60 mV, at room temperature). The 60 mV difference appears across the first resistor. The voltage between the base of the bipolar transistors and the ground terminal provides a voltage reference (VREF) that is roughly given as VREF=Vbe+X*Vt, where X is a constant that is used to scale the temperature correction factor. The temperature correction factor (X) is adjusted by the ratio of the resistors. Typical temperature corrected reference voltages of 1.25V are achieved by this configuration. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to providing a voltage reference that operates from a low power supply voltage. More specifically the present invention is directed to providing a voltage reference that is below 1.2 volts and operated from a low power-supply voltage such as in battery-operated applications. 
     Briefly stated, a single cell voltage reference operates under low power supply requirements to provide a configurable voltage reference. The single cell voltage reference includes a diode device that is biased as a voltage source. Two series connected resistive devices are connected in parallel with the diode device. The diode is biased with a current that is proportional to delta Vbe/R, such that the impedance of the diode tracks R. Another current source that is also proportional to delta Vbe/R is provided at the junction of the two resistors such that the voltage across one of the two resistors may be employed as a reference voltage that is less than 1.2V. The ratio of the resistors and scales the reference voltage level. Voltages that are below 1.2 V are provided that are temperature compensated similar to a band-gap reference. The diode voltage as driven by a current source determines the lower limit of the reference voltage. The reference voltage may be combined with a buffer or an operational amplifier such that a regulated supply can be provided that is below 1.2V. Metal masks may be arranged to permit reconfiguration of the voltage reference cell for use above 1.2V, or to change the regulation voltage without redesigning the voltage reference cell. 
     In accordance with a feature of the invention, an apparatus is directed to provide a reference voltage that operates from a low-voltage power supply. The apparatus includes a current source circuit that provides a current that is proportional to a change in base-emitter voltage and inversely proportional to a reference resistance value. A diode circuit is coupled to the current source, wherein the diode circuit has an associated diode voltage. A first resistive circuit that is series coupled to a second resistive circuit, the first resistive circuit and the second resistive circuit sharing a common node, the first and second resistive circuits are arranged in parallel with the diode device to provide a first voltage contribution at the common node that is associated with the current source that is lower than the associated diode voltage. Another current source circuit provides another current to the common node, wherein the another current is proportional to the current such that a second voltage contribution is provided at the common node, wherein the reference voltage is given as the sum of the first voltage contribution and the second voltage contribution. 
     In accordance with another feature of the invention, an apparatus is directed to providing a regulated voltage from an unregulated power supply that has a first and a second power supply terminal, where the first terminal is coupled to the regulated voltage through a resistor circuit. The apparatus includes a first current source circuit that provides a first current to a first node in response to a control signal. A second current source circuit provides a second current to a second node in response to the control signal. A control signal generator provides the control signal in response to a reference current that is proportional to a change in base-emitter voltage and inversely proportional to a resistance such that the first current and the second current are proportional to the reference current. A diode circuit is coupled between the first node and the second power supply terminal, the diode circuit having an associated diode voltage. A resistance circuit is coupled between the first node and the second node. Another resistance circuit is coupled between the second node and the second power supply terminal. A buffer circuit that has an input that is coupled to the second node and an output that provides the regulated voltage such that the regulated voltage is associated with a reference voltage at the second node. 
     In accordance with an aspect of the invention, an apparatus is directed to providing a regulated voltage from an unregulated power supply that has a first and a second power supply terminal, where the first terminal is coupled to the regulated voltage through a resistor circuit. The apparatus includes a means for providing a first current is arranged to provide the first current in response to a control signal. A means for providing a second current is arranged to provide the second current in response to the control signal. A means for providing a control signal is arranged to provide the control signal in response to a reference current such that the first current and the second current are proportional to the reference current, wherein the reference current is proportional to a change in base-emitter voltage and inversely proportional to a resistance. A diode means is arranged to provide a diode voltage that is responsive to the first current. A first resistance means is coupled between the diode means and a reference node. A second resistance means is coupled between the reference node and the second power supply terminal. A means for buffering is arranged to produce the regulated voltage from a reference voltage that is associated with the reference node. 
     In accordance with another aspect of the invention, a method is directed to providing a regulated voltage from an unregulated power supply that is coupled to the regulated voltage through a series circuit. The method includes generating a first current that is proportional to a reference current, wherein the reference current is proportional to a change in a base-emitter voltage and inversely proportional to a resistance value, generating a second current that is proportional to the reference current, biasing a diode circuit with at least one of the first current and the second current to provide a diode voltage, coupling a first resistance circuit between the diode and a reference node, coupling a second resistance circuit to between the reference node and a circuit ground potential such that the first and second resistance circuits produce a portion of a reference voltage at the reference node by dividing the diode voltage, coupling the second current to the reference node to produce a portion of a reference voltage at the reference node such that associated temperature coefficients of the first resistance circuit and the second resistance circuit are cancelled by another associated temperature coefficient of the resistance value wherein the reference voltage is given by the sum of a first constant times the diode voltage and a second constant times the change in the base-emitter voltage, and buffering the reference voltage to produce the regulated voltage from the reference voltage. 
     A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detail description of presently preferred embodiments of the invention, and to the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a single cell voltage reference; 
     FIG. 2 is a schematic diagram of another single cell voltage reference; 
     FIG. 3 is a schematic diagram of a shunt regulator including a single cell voltage reference; 
     FIG. 4 is a schematic diagram of another shunt regulator including a single cell voltage reference; and 
     FIG. 5 is a schematic diagram of a reconfigured shunt regulator including a single cell voltage reference, in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Throughout the specification, and in the claims, the term “connected” means a direct electrical connection between the things that are connected, without any intermediate devices. The term “coupled” means either a direct electrical connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means either a single component or a multiplicity of components, either active or passive, that are coupled together to provide a desired function. 
     The present invention relates to voltage references that operate from a low power supply voltage. Typically, it is necessary for the power supply voltage to be higher than the reference voltage. In some applications, such as portable devices or other devices that operate on reduced power supply levels, the maximum power supply voltage may be lower than 1.2 Volts. Conventional band-gap reference circuits require their power supply voltages to exceed 1.2 Volts for proper operation. The present invention is directed to providing a temperature compensated reference circuit that operates on power supply levels that are lower than 1.2 Volts. However, it is understood and appreciated that the concepts discussed in reference to the present invention may be adapted for use in reference circuits that have power supply voltages that exceed 1.2 volts. 
     FIG. 1 is a schematic diagram of an exemplary reference ( 100 ) circuit that is in accordance with the present invention. The circuit includes a diode (D 10 ), a current source (I 10 ), two resistors (R 10 , R 11 ), and a single power supply (VCC) that is less than 1.2 volts. The current source (I 10 ) provides a current to node N 10  that is proportional to ΔVbe/R. The diode (D 10 ) has an anode coupled to node N 10 , and a cathode coupled to a circuit ground potential (GND). The first resistor (R 10 ) is series coupled between node N 10  and the output node (OUT 1 ). The second resistor (R 11 ) is series coupled between the output node (OUT 1 ) and the circuit ground potential (GND). A voltage (VREG 1 ) appears across the second resistor (R 11 ) between the output node (OUT 1 ) and the circuit ground potential (GND). 
     The diode (D 10 ) in FIG. 1 will have an associated forward bias voltage. In one example, the forward bias voltage across the diode is on the order of 600 mV. Resistors R 10  and R 11  form a voltage divider that divides the diode voltage based on the ratio between the resistors (VREG 1 =Vdiode/(1+R 10 /R 11 )). For example, when R 10  and R 11  are of equal values, and the diode voltage is 600 mV, the potential (VREG 1 ) at the output node (OUT 1 ) will be roughly 300 mV. 
     An equivalent circuit ( 100 ′) of circuit arrangement  100  includes a voltage source with a source impedance as shown in FIG.  1 . The voltage source has a source impedance that corresponds to the parallel combination of resistors R 10  and R 11 . The voltage source provides a voltage that corresponds to the voltage drop (VREG 1 ) that appeared across resistor R 11 . 
     The diode (D 10 ) actually includes a source impedance (not shown) that corresponds to a resistance given by: Re=(kT/q)/Ie. The impedance (Re) of the diode (D 10 ) is included in the value of R 10  for purposes of the above-described model. Since the diode is biased with a current that is proportional to ΔVbe/R, the impedance of the diode (Re) will track R. 
     FIG. 2 is a schematic diagram of an exemplary reference circuit ( 200 ) that includes temperature compensation in accordance with the present invention. The circuit includes a diode (D 20 ), a first and second current source (I 20 , I 21 ), two resistors (R 20 , R 21 ), and a single power supply (VCC) that is less than 1.2 volts. The first current source (I 20 ) delivers a current that is equal to ΔVbe/R through node N 20 . The second current source (I 21 ) delivers a current, which is also equal to ΔVbe/R, through an output node (OUT 2 ). The diode (D 20 ) has an anode coupled to node N 20 , and a cathode coupled to a circuit ground potential (GND). The first resistor (R 20 ) is series coupled between node N 20  and the output node (OUT 2 ). The second resistor (R 21 ) is series coupled between the output node (OUT 2 ) and the circuit ground potential (GND). A voltage (VREG 2 ) appears across the second resistor (R 21 ) between the output node (OUT 2 ) and the circuit ground potential (GND). 
     The circuit configuration shown in FIG. 2 is similar to that shown in FIG. 1 with the addition of the second current source (I 21 ). The diode (D 20 ) in FIG. 2 has an associated forward bias voltage. In one example, the forward bias voltage across the diode is on the order of 600 mV. Using superposition, the first current source (I 20 ) and the diode (D 20 ) form a first voltage source that contributes a first portion to the output voltage (VREG 2 ), while the second current source (I 21 ) contributes a second portion to the output voltage (VREG 2 ). Resistors R 20  and R 21  form a voltage divider that divides the diode voltage based on the ratio between the resistors. For example, when R 20  and R 21  are of equal values, and the diode voltage is 600 mV, the first portion of the potential (VREG 2 ) at the output node (OUT 2 ) will be roughly 300 mV. The second portion of the potential (VREG 2 ) at the output node (OUT 2 ) is contributed by the second current source (I 21 ), which sources current into the parallel combination of resistors R 20  and R 21  (where R 20  includes the resistance of diode D 20 ). 
     An equivalent circuit ( 200 ′) of circuit arrangement  200  includes a voltage source with a source impedance as shown in FIG.  2 . The voltage source has a source impedance that corresponds to the parallel combination of resistors R 20  and R 21 . The voltage source provides a voltage (VREG 2 ) that corresponds to the diode voltage divided by the resistor divider network formed by R 20  and R 21 . The second current source is connected to the output node of the equivalent circuit. In one example, the diode has a nominal voltage of 600 mV, and the current sources together with resistors R 20  and R 21  produce an output voltage of 900 mV. In this example, the equivalent circuit has a voltage source (VREG 2 ) with a voltage of 450 mV that is determined by the resistance of the diode and resistors R 20  and R 21 , and the output impedance of the voltage source is the parallel combination of R 20  and R 21 . 
     In FIG. 2, the reference circuit ( 200 ) provides an output voltage that is well below 1.2 volts. The lower limit of the supply voltage is determined by the current requirements of the diode. Since both current sources (I 20 , I 21 ) provide a current that is proportional to ΔVbe/R, the impedance (Re) of the diode will track R, and the temperature coefficient of the diode is effectively canceled. 
     FIG. 3 is a schematic diagram of a shunt regulator circuit ( 300 ) that that includes a reference circuit that is in accordance with the present invention. The circuit includes a diode (D 30 ), three bipolar junction transistors (Q 30 -Q 31 ), a buffer circuit (X 30 ), three resistors (R 30 -R 32 ), and a current source (I 30 ). 
     The current source (I 30 ) sinks a current out of node N 30  that is given as ΔVbe/R. Resistor R 30  is coupled in series between an unregulated power source (VCC) and the output node (OUT 4 ). Transistor Q 30  is a PNP type transistor that has an emitter connected to node OUT 4 , and a base and collector that are connected to node N 30 . Transistor Q 31  is a PNP transistor that has an emitter connected to node OUT 3 , a base connected to node N 30 , and a collector connected to node N 31 . Transistor Q 32  is a PNP transistor that has an emitter connected to node OUT 3 , a base connected to node N 30 , and a collector connected to node N 32 . Diode D 30  has an anode connected to node N 31  and a cathode connected to the circuit ground potential (GND). Resistor R 31  is connected between nodes N 31  and N 32 . Resistor R 32  is connected between node N 31  and the circuit ground potential (GND). Buffer X 30  has an input connected to node N 32  and an output (OUT) connected to node OUT 3 . 
     Transistor Q 30  is a diode-connected device that is arranged in series with current source I 30 , transistor Q 30  will conduct a current that is given by ΔVbe/R. Transistor Q 30  is also arranged to operate as a current mirror with transistors Q 31  and Q 32 . Thus, transistors Q 31  and Q 32  will deliver currents (I 31 , I 32 ) to their respective loads at node N 31  and N 32  that is also given by ΔVbe/R. Transistors Q 31  and Q 32  are configured to operate similar to current sources I 20  and I 21  from FIG.  2 . 
     The circuit configuration shown in FIG. 3 is similar to that shown in FIG. 2 with the addition of resistor R 30 , buffer X 30 , and current sources I 20  and I 21  are replaced by transistors Q 31  and Q 32  respectively. Buffer X 30  produces the output voltage of the reference circuit (VREG 3 ) at node OUT 3  in response to the voltage that appears across resistor R 32  (VSNS 3 ). Using superposition, transistor Q 31  provides a portion of current I 31  through diode D 30  to form a first voltage source that contributes a first portion of the sense voltage (VSNS 3 ). Transistor Q 32  provides current I 32  to node N 32 , which contributes a second portion to the sense voltage (VSNS 3 ). Resistors R 30  and R 31  form a voltage divider that divides the diode voltage based on the ratio between the resistors. 
     Buffer X 30  may be configured to operate as an amplifier with gain, an amplifier with attenuation, or another configuration as may be desired. Buffer X 30  has a high impedance input (IN) and does not load down node N 32 . In one example, buffer X 30  includes a level shifter between the input of the buffer and the output of the buffer. The voltage (VSNS 3 ) at node N 32  is the reference voltage for the circuit. The buffer circuit (X 30 ) provides a stable regulated output voltage at node OUT 3  as given by VREG 3 . The lower limit on the reference voltage (VSNS 3 ) at node N 32  is determined by the minimum current requirements of the diode and the minimum collector to emitter voltages of transistors Q 30 -Q 32  for proper conduction. 
     Another example of a shunt regulator that employs the teachings of the present invention is shown in FIG.  4 . The schematic shown in FIG. 4 is identical to the schematic shown in FIG. 3, except that the buffer X 30  has been replaced by buffer X 40 . Like components and connection nodes from FIG. 3 are labeled identically in FIG.  4 . Node OUT 4  replaces node OUT 3 . The output (VREG 4 ) of the shunt regulator ( 400 ) shown in FIG. 4 now appears at node OUT 4  instead of OUT 3 . The reference voltage (VSNS 4 ) appears across resistor R 32 . 
     As shown in FIG. 4, the buffer (X 40 ) includes an operational amplifier (X 41 ) and an offset generator circuit (X 42 ). The operational amplifier (X 41 ) includes a non-inverting input (+) that is coupled to node N 32 , an inverting input (−) that is coupled to node N 44 , and an output coupled to node OUT 4 . The offset generator circuit (X 42 ) has an input (IN) that is coupled to node OUT 4 , and an output (OUT) that is coupled to node N 44 . 
     The offset generator produces an offset voltage (VOS) that is defined between the input terminal (IN) and the output terminal (OUT) of the offset generator (X 42 ). In this configuration, the operational amplifier will provide an output voltage to node OUT 4  that is given as the sum of the sense voltage (VSVS 4 ) and the offset voltage (VOS). For example, when the offset voltage is roughly 200 mV and the sense voltage (VSNS 4 ) at node N 32  is roughly 700 mV, the regulated output voltage (VREG 4 ) will be roughly 900 mV. The 200 mV offset, in this example will result in a collector-emitter voltage for transistors Q 30 -Q 32  that is also 200 mV. 
     The offset generator and the operational amplifier may be combined into a single electronic circuit (not shown). For example, an offset can be built into the operational amplifier by area scaling the transistor geometries in the input stage of the operational amplifier. In one embodiment of the present invention, the operational amplifier has two stages with a sixty-to-one (60:1) are scaling factor to generate an offset voltage of approximately 200 mV. In light of the above description, it is understood and appreciated that other methods may be used to generate an offset voltage in accordance with the present invention. 
     Another example of a shunt regulator that employs the teachings of the present invention is shown in FIG.  5 . The schematic shown in FIG. 5 is identical to the schematic shown in FIG. 4, except that the resistor R 32  has been eliminated, and the collector of transistor Q 31  is connected to node N 32  instead of node N 31 . Like components and connection nodes from FIG. 4 are labeled identically in FIG.  5 . Node OUT 5  replaces node OUT 4 . The output (VREG 5 ) of the shunt regulator ( 500 ) shown in FIG. 5 now appears at node OUT 5  instead of OUT 4 . The reference voltage (VSNS 5 ) appears between node N 42  and the circuit ground potential (GND). 
     As shown in FIG. 5, the collectors of transistors Q 31  and Q 32  are connected in common to node N 42 . Currents I 31  and I 32  sum together (2*ΔVbe/R) and flow through the series combination of resistor R 31  and diode D 30 . The voltage drop (VSNS 5 ) across the series combination will be higher than the diode voltage as given by: 2*R 1 *ΔVbe/R+Vdiode. When the offset generator (X 42 ) generates an offset voltage that is 213 mV and the diode voltage (Vdiode) is 600 mV, the voltage reference (VSNS 5 ) can provide a voltage of 987 mV at node N 32 . With a 987 mV reference the output voltage of the regulator (VREG 5 ) is roughly 1.2V. 
     By the above-described arrangement, the same circuit components used for the other arrangements (e.g., as shown in FIGS. 3-5) may be reconfigured for use as other voltage references. Thus, the arrangement of components may be integrated into a single chip with a single metal mask change to provide variations in use. In the example where the reference is configured as a 1.2 V reference, resistor R 32  is decoupled from the circuit by a metal mask change, and the collector of transistor Q 31  is coupled to node N 32  by the same metal mask change. By simplifying the overall design of the shunt regulator, the shunt regulator can be implemented as a standard cell component with minimal mask changes to provide other variations in regulation voltage. 
     In light of the above description, it is understood and appreciated that the circuit shown in FIGS. 3-5 may be arranged to operate with NPN transistors instead of PNP transistors. Additionally, it is understood and appreciated that the design may be further arranged to operate using one or more other transistor types including, but not limited to JFET transistors, MOSFET transistors, GaAsFET transistors as well as others. 
     The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.