Abstract:
As devices are often different in the characteristics from one another, semiconductor chips based on the devices have discrepancies in the performance. A semiconductor device having a semiconductor switching element and a drive controlling means ( 1 ) for generating from input signals (A) and (B) drive signals (a) and (b) to control the action of the semiconductor switching element is provided comprising a characteristic compensating means ( 2 ) for generating from a characteristic compensation input signal a compensation signal to eliminate variations in the transmission delay time of the drive controlling means ( 1 ).

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This is a Divisional of Application of application Ser. No. 10/139,750, filed May 7, 2002, now U.S. Pat. No. 7,132,868. This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-194904, the entire contents of which are incorporated herein by reference. 

   BACKGROUND OF THE INVENTION 
   The present invention relates to a circuit configuration in a semiconductor device and particularly to a circuit provided in a power module which has semiconductor switching elements of an insulating gate type such as IGBTs, for trimming electrical characteristics of the power module. 
   DESCRIPTION OF THE RELATED ART 
     FIG. 13  illustrates a power module for an inverter circuit. A drive controller circuit when receiving input signals UPin, VPin, WPin, UNin, VNin, and WNin supplies a group of IGBTs 1 to 6 with corresponding drive signals UPout, VPout, WPout, UNout, VNout, and WNout (only UPout and UNout shown in  FIG. 13 ). While the power module shown in  FIG. 13  includes a single drive controller circuit provided for driving six IGBTs, it may have two or more drive controller circuits. 
   Shown at the upper right of the drawing is a rectifier circuit of silicon bridge type for feeding the power module with a DC power. As a resistor Rs for current detection is installed in any emitter circuit of the IGBT 2 , it may produce a considerable level of current loss and preferably installed in the second emitter circuit. 
     FIG. 14  is a timing chart showing input and output actions of the input signals UPin and UNin. Denoted by t 1  is a delay time taken from the inversion of the input signal UPin from high level to low level to the inversion of the output signal UPout from low level to high level. As apparent from an output current Iup, the IGBT 1  is switched on after a delay of time tonP. The delay time t 1  of the former is attributed to the drive controller circuit while the delay time tonP of the latter is a response time of the IGBT. More specifically, the IGBT 1  is switched on after a time tconP from the inversion of the input signal UPin from high level to low level. 
   Denoted by t 2  is a delay time taken from the inversion of the input signal UPin from low level to high level to the inversion of the output signal UPout from high level to low level. As apparent from an output current Iup, the IGBT 1  is switched off after a delay time toffp. More particularly, the IGBT 1  is switched off after a time tcoffP from the inversion of the input signal UPin from low level to high level. 
   Similarly, the IGBT 2  is switched off after a time tcoffN(=t 3 +toffN) from the inversion of the input signal UNin from low level to high level. The IGBT 2  is switched on after a time tconN(=t 4 +tonN) from the inversion of the input signal UNin from high level to low level. As explicitly shown in  FIG. 14 , the output signals UPout and UNout are inverted from their respective input signals UPin and UNin. 
   The delay times t 1  to t 4 , tonP, toffp, toffN, and tonN are not uniform but varied depending on the drive controller circuit and the IGBTs. It is hence schemed for inhibiting the IGBT 1  and the IGBT 2  from switching on at the same time to have the off period of the IGBT 2  set longer than the on period of the IGBT 1 . 
   For the purpose, the high level duration of the input signal UNin has to be set longer than the low level duration of the input signal UPin as shown in the drawing. This causes the input signal UNin to contain an input cancel period (Tdead), thus allowing a higher level of the inverter control action with much difficulty. 
     FIG. 15  illustrates an over-current protection circuit provided in the drive controller circuit shown in  FIG. 13 . As the sense resistor Rs connected to the IGBT 2  receives a current Irs, it produces a potential VRs=Rs·Irs at one end. When the potential VRs exceeds a specific trip level, the over-current protection circuit  3 ′ detects the generation of short-circuit and conducts its function of protection from short-circuit to stop the action of the drive controlling means  4 ′. However, the action of the sense resistor may hardly be uniform while the trip level determined by the over-current protection circuit  3 ′ is inconstant. This will discourage the over-current protection thus providing inadequate protection from the short-circuit. 
   Moreover, the greater the gradient of the current change at the rise or fall of a corrector current of each IGBT, the more noises may be produced. The smaller the gradient, the switching loss may be increased. There is a trade-off relationship between the generation of noises and the increase of the switching loss. For compensation, each IGBT in the prior art has to be accompanied with its dedicated drive controller circuit for enduring optimum driving conditions. 
   SUMMARY OF THE INVENTION 
   The present invention has been developed for eliminating the foregoing drawbacks and its object is to provide a semiconductor device for trimming the electrical characteristics of devices to eliminate discrepancies between the devices thus enabling a higher level of inverter controlling action, a semiconductor device for carrying out the short-circuit protection and the over-temperature protection at higher precision, and a semiconductor device for favorably determining the gradient at the rise and fall of the collector current of an output device. 
   As a feature of the present invention defined in claim  1 , a semiconductor device is provided comprising: a semiconductor switching element; a drive controlling means for controlling the action of the semiconductor switching element with the use of an input signal; and a characteristic compensating means for arbitrarily determining the transmission delay time of the drive controlling means with the use of a characteristic compensation input signal to eliminate discrepancies in the delay time of the semiconductor switching element. 
   As another feature of the present invention defined in claim  2 , a semiconductor device is provided comprising: a semiconductor switching element; a current detecting means for detecting the current flowing across the semiconductor switching element; an over-current protecting means for canceling the action of the semiconductor switching element when the detection signal from the current detecting means exceeds a predetermined trip level; and a characteristic compensating means for modifying the trip level. 
   As a further feature of the present invention defined in claim  3 , a semiconductor device having a semiconductor switching element and a drive controlling means for controlling the action of the semiconductor switching element based on an input signal is provided comprising a characteristic compensating means for compensating the operational characteristics of the semiconductor switching element through selecting and using one or more of driving devices which are provided in the drive controlling means and arranged different in the driving capability. 

   
     BRIEF DESCRIPTION OF THE DRAWING 
       FIG. 1  is a controller block diagram showing a first embodiment of the present invention; 
       FIG. 2  is a circuit diagram having shown the details of  FIG. 1 . 
       FIG. 3  is a timing chart of signals shown in  FIG. 1 ; 
       FIG. 4  is a controller block diagram showing a second embodiment of the present invention; 
       FIG. 5  is a circuit diagram having shown the details of  FIG. 4 . 
       FIG. 6  is a timing chart of signals shown in  FIG. 4 ; 
       FIG. 7  is a controller block diagram showing a third embodiment of the present invention; 
       FIG. 8  is a circuit diagram having shown the details of  FIG. 7 . 
       FIG. 9  is a timing chart of signals shown in  FIG. 7 ; 
       FIG. 10  is a controller block diagram showing a fourth embodiment of the present invention; 
       FIG. 11  is a circuit diagram having shown the details of  FIG. 10 . 
       FIG. 12  is a timing chart of signals shown in  FIG. 10 ; 
       FIG. 13  is a circuitry diagram showing a conventional power module; 
       FIG. 14  is a timing chart showing input and output actions shown in  FIG. 13 ; and 
       FIG. 15  is a timing chart showing an action of protecting against short-circuits. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   Embodiment 1 
     FIG. 1  is a controller block diagram showing the first embodiment of the present invention. A drive controller circuit  1  is responsive to the input signals UPin and UNin from signal input terminals respectively for delivering the output signals UPout and UNout to the gates of the IGBT 1  and IGBT 2  at the U phase which are connected in series between the output terminals P 2  and N 2  of the power module.  FIG. 1  illustrates only the U phase although it contains identical circuits for driving the IGBT 3  and IGBT 4  at the V phase and the IGBT 5  and IGBT 6  at the W phase. 
     FIG. 2  shows a detailed circuit configuration of the drive controller circuit  1  and a characteristic compensator circuit  2 . The drive controller circuit  1  includes a logic circuit  11  for converting the input signal UPin into a logic signal received by the line L 1  of a delay interleave circuit  12 . The delay interleave circuit  12  has three capacitors C 1 , C 2 , and C 3  connected with corresponding switches S 1 , S 2 , and S 3  between the line L 1  and the ground. The line L 1  is supplied with a current  11 . 
   The line L 1  is connected via an inverter INV 1  to the line L 2  of another delay interleave circuit  13 . Similarly, the delay interleave circuit  13  has three capacitors C 4 , C 5 , and C 6  connected with corresponding switches S 4 , S 5 , and S 6  between the line L 2  and the ground. The line L 2  is supplied with a current  12 . The line L 2  is further connected via an inverter INV 2  to a driver circuit  14 . The driver circuit  14  feeds the IGBT 1  with a driving signal UPout. 
   The capacitors C 1 , C 2 , C 3 , C 4 , C 5 , and C 6  may be adapted identical or different in the capacitance. The number of the grouped capacitors is not limited to three. 
   The characteristic compensator circuit  2  includes a write-in circuit  21  for writing a characteristic compensation signal into an EPROM  22  of which the data is then latched by a register  23 . The register  23  generates and delivers latch data d 1  to d 6  as the driving signals to the corresponding switches S 1  to S 6 . This allows the switches S 1  to S 6  to be switched on and off desirably with the characteristic compensation signal. 
   The action of the drive controller circuit  1  shown in  FIG. 2  will now be described referring to the timing chart shown in  FIG. 3 . The input signal UNin is different from that shown in  FIG. 14  as having no input cancel period (Tdead) and being precisely synchronized with the input signal UPin which is inverted. Denoted by t 11  is a delay time taken from the inversion of the input signal UPin from high level to low level to the inversion of the output signal UPout from low level to high level in the drive controller circuit  1 . When the switches S 1  to S 3  remain switched off, the delay time in the delay interleave circuit  12  is zero and the delay time t 11  is equal to the delay time t 1  shown in  FIG. 14 . 
   Denoted by t 12  is a delay time taken from the inversion of the input signal UPin from low level to high level to the inversion of the output signal UPout from high level to low level in the drive controller circuit  1 . When the switches S 4  to S 6  remain switched off, the delay time in the delay interleave circuit  33  is zero and the delay time t 12  is equal to the delay time t 2  shown in  FIG. 14 . 
   While the drive controller circuit  1  shown in  FIG. 2  illustrates one circuit for the input signal UPin, it actually includes other identical circuits (having the delay interleave circuits and the characteristic compensator circuit) for the input signals UNin, VPin, VNin, WPin, and WNin respectively. Hence, denoted by t 13  is a delay time taken from the inversion of the input signal UNin from low level to high level to the inversion of the output signal UNout from high level to low level. Denoted by t 14  is a delay time taken from the inversion of the input signal UNin from high level to low level to the inversion of the output signal UNout from low level to high level. Those delay times may arbitrarily be determined like t 11  ad t 12 . 
   As its output signal UPout is inverted from low level to high level after the delay time t 11  from the inversion of the input signal UPin from high level to low level, the IGBT 1  is switched on after a period tonP (its response time). More particularly, the IGBT 1  is switched on after a period tconP from the inversion of the input signal UPin from high level to low level. 
   On the contrary, as its output signal UPout is inverted from high level to low level after the delay time t 12  from the inversion of the input signal UPin from low level to high level, the IGBT 1  is switched off after a period toffP (its response time). More particularly, the IGBT 1  is switched off after a period tcoffP from the inversion of the input signal UPin from low level to high level. 
   Similarly, as its output signal UNout is inverted from high level to low level after the delay time t 13  from the inversion of the input signal UNin from low level to high level, the IGBT 2  is switched off after a period toffN (its response time). More particularly, the IGBT 2  is switched on after a period tcoffN from the inversion of the input signal UNin from low level to high level. 
   As its output signal UNout is inverted from low level to high level after the delay time t 14  from the inversion of the input signal UNin from high level to low level, the IGBT 2  is switched on after a period tonN (its response time). More particularly, the IGBT 2  is switched off after a period tconN from the inversion of the input signal UNin from high level to low level. 
   Even when the two input signals UPin and UNin are synchronized with each other as shown in  FIG. 3 , the delay time and the response time of each IGBT are not uniform in the drive controller circuit  1  and tconP≠tcoffN is thus established. As a result, the switching on of the IGBT 1  is not timed with the switching off of the IGBT 2 . Also, as tcoffP≠tconN is established, the switching off of the IGBT 1  is not timed with the switching on of the IGBT 2 . 
   However, the delay time t 11  or t 13  can be adjusted by the characteristic compensation signal selecting the action of the switches between
     the switching off of all the switches,   the switching on of any one of the switches,   the switching on of any two of the switches, and
 
the switching on of all the switches. More practically, at tconP≅tcoffN shown in  FIG. 3 , the IGBT 1  can be switched on at the timing of switching off of the IGBT 2 . Similarly, as the delay times t 12  and t 14  are adjusted to have tcoffP≅tconN, the IGBT 1  can be switched off at the timing of the switching on of the IGBT 2 .
   

   When tconP≅tcoffN and tcoffP≅tconN are given, discrepancies in the delay time including the response time of the drive controller circuit  1  and the IGBTs can be eliminated in the entire arrangement of the device. This will require no use of the input cancel period (Tdead), thus allowing a higher level of the inverter controlling action. Alternatively, as the delay time is slightly drifted due to deterioration with time and temperature variation, the input cancel period Tdead may preferably be provided for offsetting the effect of drift. In that case, the period Tdead is too short as compared with that in any prior art and will hardly disturb the highly advanced inverter controlling action. 
   The EPROM  22  in the characteristic compensation circuit  2  may be a nonvolatile memory or one-time ROM. The characteristic compensation circuit  2  may be installed in an integrated circuit form in the drive controller circuit  1 . 
   Embodiment 2 
     FIG. 4  is a controller block diagram showing the second embodiment of the present invention. A drive controller circuit  4  comprises a logic circuit  41  for transferring its input signal C as a logic signal and a driver circuit  42  arranged responsive to the logic signal for delivering a drive signal c. 
   An over-current protection circuit  3  includes a comparator  31  of which the non-inverting input terminal receives a voltage Vs developed at one end of a sense resistor Rs connected to the second emitter of the IGBT 2 . The reference voltage Vref is divided by the action of four series connected resistors into three components Vref 1  to Vref 3  which are selectively connected as different trip levels to the inverting input terminal of the comparator  31  by the action of three switches S 1  to S 3 . A signal output of the comparator  31  is transferred as a disconnection signal to the logic circuit  41   
   A characteristic compensation circuit  5  is provided for switching on any of the switches S 1  to S 3  and its circuit configuration is identical to that of the characteristic compensation circuit  2  shown in  FIG. 2 . The characteristic compensation circuit  5  also includes an EPROM which may be a nonvolatile memory or one-time ROM. The characteristic compensation circuit  5  may be implemented in an integrated circuit form in the drive controller circuit  4 . 
   As described, the trip level or the emitter shunting ratio predetermined in the sense resistor Rs and the over-current protection circuit  3  is varied between different units. This will discourage the over-current protection thus providing inadequate protection from the short-circuit. The present invention allows the trip level to be favorably selected from Vref 1 , Vref 2 , and Vref 3  on the basis of actual measurements, as shown in  FIG. 6 . As a result, the overcurrent protection can correctly be carried out. The number of the trip levels from which the optimum is selected is not limited to three. 
   Embodiment 3 
     FIG. 7  is a controller block diagram showing the third embodiment of the present invention.  FIG. 8  illustrates details of  FIG. 7 . Throughout  FIGS. 7 and 8 , like components are denoted by line numerals. An over-current protection circuit  7  is substantially identical in the arrangement to the over-current protection circuit  3 . In particular, its comparator  71  receives at the non-inverting input terminal a temperature signal Vt from a temperature sensing means  8 . 
   When the temperature of the IGBT 1  in operation increases and the temperature signal Vt exceeds a predetermined trip level, the disconnection signal is delivered to the drive controller circuit  4  where the drive signal d generated from the input signal D is thus disconnected. There are yet variations in the trip level for over-temperature protection and the measurement of the temperature sensing means  8  in the over-current protection circuit  7 , hence permitting no precise over-temperature protection. 
   This embodiment allows the trip level to be favorably selected from Vref 1 , Vref 2 , and Vref 3 , as shown in  FIG. 9 . As the trip level is controlled to an optimum setting from the actual measurements, the over-temperature protection can be carried out at higher precision. 
   Embodiment 4 
     FIG. 10  is a controller block diagram showing the fourth embodiment of the present invention.  FIG. 11  illustrates details of  FIG. 10 . A drive controller circuit  9  comprises a logic circuit  91  for transferring an input signal E as a logic signal and a driver circuit  92 . Each of n-type FET transistors T 1 , T 3 , and T 5  is connected at the drain to the output terminal of the drive controller circuit  9 . Their gates can be connected by the action of corresponding switches S 1 , S 3 , and S 5  to the output terminal of the logic circuit  91  or their own sources. 
   Similarly, each of p-type FET transistors T 2 , T 4 , and T 6  is connected at the drain to the output terminal of the drive controller circuit  9 . Their gates can be connected by the action of corresponding switches S 2 , S 4 , and S 6  to the output terminal of the logic circuit  91  or their own sources. The switches S 1  to S 6  are operated with corresponding signals d 1  to d 6  received from a register provided in a characteristic compensator circuit  10 . 
   As timed with the fall of the input signal E, one of the transistors T 1 , T 3 , and T 5  connected to the output terminal of the logic circuit  91  is driven. When the input signal E rises, one of the transistors T 2 , T 4 , and T 6  connected to the output terminal of the logic circuit  91  is driven. The sum of current outputs of the driven transistors is released as a drive signal e. 
   This action is illustrated in the timing chart of  FIG. 12 . A drive signal e 1  is a combination of the outputs of the two transistors T 1  and T 2 . Also, a drive signal e 2  is a combination of the outputs of the two transistors T 3  and T 4 . As apparent, the combination of the two transistors T 3  and T 4  is greater in the driving force than that of the transistors T 1  and T 2 . Accordingly, the drive signal e 2  can be more moderate at the rise and fall edges than the drive signal e 1 . Denoted by I 1  and I 2  are corrector currents of the IGBT 2  with the drive signals e 1  and e 2  respectively. 
   In the prior art, the driving force of the drive controller circuit has to be modified depending on the current capacity of each IGBT. This embodiment allows the driver to be favorably selected from a group of transistors having different driving capacities to determine an optimum gradient at the rise or fall of the corrector current (output) of the IGBT 2 . Also, the characteristic compensator circuit  10  includes an EPROM which may be a nonvolatile memory or one-time ROM and may be installed in an integrated circuit form in the drive controller circuit  9 . 
   A set of the transistors to be driven is not limited to T 1 -T 2 , T 3 -T 4 , and T 5 -T 6  but may be any pair such as T 1 -T 4  or any combination such as (T 1 +T 3 )-(T 2 +T 4 ). 
   As defined in claim  2 , the delay time of the semiconductor switching elements is set to a desired length in the driver circuit to eliminate its discrepancies. Accordingly, the setting of input cancel period (Tdead) can be unnecessary and the inverter controlling action can be carried out at higher precision. 
   As defined in claim  3 , the trip level used for judging the over-current can arbitrarily be determined to a desired setting, hence allowing a higher degree of the protection against short-circuits. 
   As defined in claim  5 , the driver circuit includes a plurality of driving devices which are different in the current capacity so that optimum one can be selected from the driving devices. Accordingly, the gradient at the rise and fall of the corrector current of the semiconductor switching element can arbitrarily be determined.