Abstract:
A dual bus matrix architecture comprising: a first interconnect matrix connected to a plurality of high performance peripherals and having a plurality of master ports and a plurality of slave ports; a second interconnect matrix connected to a plurality of limited bandwidth peripherals and having a plurality of master ports and a plurality of slave ports; and a shared multiport controller connected to one (or more) of the slave ports of the first interconnect matrix and to one (or more) of the master ports of the second interconnect matrix, wherein the shared multiport controller controls accesses to the high performance peripherals and the limited bandwidth peripherals by directing accesses to the high performance peripherals through the first interconnect matrix and accesses to the limited bandwidth peripherals through the second interconnect matrix.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to microcontrollers. More specifically, the present invention relates to a dual bus matrix architecture for microcontrollers. 
   2. Background 
   The increasing number of peripherals connected onto a system bus creates routability problems. Moreover, the data path size of peripherals may not be the same due to their different inherent bandwidth requirements. When interconnecting all of these heterogeneous peripherals to the same bus matrix, it may be difficult to match all the requirements. These requirements may include, but are not limited to, maximum frequency and routability. Although, wrapper logic may be added, it can lead to a reduction in performance. 
   Currently, high-end microcontrollers use a single bus matrix because it is sufficient to cover the needs of today&#39;s applications. However, increasing demands for portable multimedia applications require more peripherals of heterogeneous bandwidth requirements and different clock frequencies to achieve appropriate bandwidth with optimal power consumption. 
   SUMMARY 
   The present invention takes place in a microcontroller integrated circuit where a microprocessor is configured to perform accesses to many peripheral circuitries. These accesses are performed by means of system bus. The peripherals may act as masters or slaves on the system bus. In order to provide maximum flexibility of the connections while keeping routability between all these peripherals, a dual bus matrix is employed. A first matrix is used to directly connect peripherals of very high bandwidth, while a second matrix is used to connect peripherals having limited bandwidth requirements. A slave port of one matrix may act as a master port of the other matrix in order to maintain communications between peripherals of both matrices. 
   This dual bus matrix architecture enhances the routability beyond a single bus matrix because the bandwidth is not at the maximum for all peripheral connections. Rather, the bandwidth is just what is required. The microprocessor may increase the MIPS (Million Instructions Per Second) when a software application so requires, such as with a lot of off-chip or on-chip memory accesses. This is possible because limited number of peripherals may interfere directly on the same bus. 
   In one aspect of the present invention, a dual bus matrix architecture is disclosed comprising a first interconnect matrix connected to a plurality of high performance peripherals and having a plurality of master ports and a plurality of slave ports, and a second interconnect matrix connected to a plurality of limited bandwidth peripherals and having a plurality of master ports and a plurality of slave ports. The architecture further comprises a shared multiport controller connected to one (or more) of the slave ports of the first interconnect matrix and to one (or more) of the slave ports of the second interconnect matrix The shared multiport controller is accessed at the same by all master peripherals. Both limited bandwidth peripherals and high performance peripherals can access the shared memory through the multiport memory controller. The role of the multiport controller is to schedule high performance (64 bit) accesses and limited bandwidth peripheral (32 bit) accesses to optimize the shared memory. 
   In another aspect of the present invention a method for accessing peripherals is disclosed. A shared multiport controller determines whether an access is required to either a high performance peripheral or a limited bandwidth peripheral. The shared multiport controller is connected to one (or more) of a plurality of slave ports of a first interconnect matrix and to one (or more) of a plurality of slave ports of a second interconnect matrix. The first interconnect matrix is connected to a plurality of high performance peripherals and further comprises a plurality of master ports. The second interconnect matrix is connected to a plurality of limited bandwidth peripherals and further comprises a plurality of master ports. If access is required by one of the plurality of high performance master peripherals, the shared multiport controller directs an access to the shared memory through the first interconnect matrix when the shared resource is not busy. If access is required by one of the plurality of limited bandwidth master peripherals, the shared multiport controller directs that access to the shared memory of limited bandwidth peripherals through the second interconnect matrix when the shared resource is not busy. 
   As a result of the present invention, routability is enhanced. Furthermore, there is no need to redesign peripherals when the data path size is increased, nor to add a wrapper logic to fit the new data path size, nor to redesign the peripherals to prevent performance reduction. 

   
     DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram of an exemplary dual bus matrix architecture in accordance with the principles of the present invention; 
       FIG. 2  is a flowchart of an exemplary method for accessing shared memory resources of peripherals in accordance with the principles of the present invention; and 
       FIG. 3  is a schematic diagram of another exemplary dual bus matrix architecture illustrating the clock domain boundary in accordance with the principles of the present invention. 
   

   DETAILED DESCRIPTION 
   Persons of ordinary skill in the art will realize that the following disclosure is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons having the benefit of this disclosure. 
     FIG. 1  is a schematic diagram of exemplary dual bus matrix architecture  10  in accordance with the principles of the present invention. The architecture  10  may be divided into three different areas. The first area is a high performance area, such as the 64-bit high performance area shown in  FIG. 1 . The second area is a standard system area, such as the 32-bit standard system area shown in  FIG. 1 . The third area is a low throughput area, such as the 32-bit low throughput area shown in  FIG. 1 . 
   The high performance area comprises a first interconnect matrix  12 , such as a 64-bit AHB (AMBA High-Performance Bus). First interconnect matrix  12  has a plurality of master ports (M) and slave ports (S) and is used to directly connect peripherals of very high bandwidth. The high performance area preferably includes a processor  14 , such as a 64-bit core processor (for example, ARM1176). Processor  14  is connected to two master ports (one instruction port and one for data port) of first matrix  12 . As seen in  FIG. 1 , a cache controller  16  may be connected in between processor  14  and first matrix  12 . In an exemplary embodiment, cache controller  16  is an L2 cache controller connected to an L2 cache memory  18 . 
   The high performance area may also include a 64-bit data processing unit  20  connected to one of the master port of first matrix  12 , a 64-bit direct memory access (DMA) assisted peripheral  22  connected to one of the master ports of first matrix  12 , and a 64-bit RAM interface  24  connected to one of the slave ports of first matrix  12 . 
   A multiport controller  26  is connected to at least one of the slave ports of first matrix  12 . As seen in  FIG. 1 , one port of controller  26  may be connected to one of the slave ports of first matrix  12  through a 64-bit memory interface  28 , while another port of controller  26  may be connected to another slave port of first matrix  12  through another 64-bit memory interface  30 . In a preferred embodiment, multiport controller  26  is a 64-bit multiport SDR/DDR/DDR2 controller. 
   The standard system area comprises a second interconnect matrix  32 , such as a 32-bit AHB. Second interconnect matrix  32  has a plurality of slave ports (S) and master ports (M). A slave port of that matrix may be connected to an AHB master port of an AHB master peripheral. Respectively, a master port of that matrix may be connected to an AHB slave port of an AHB slave peripheral. The second interconnect matrix is used to connect peripherals having limited bandwidth requirements. In a preferred embodiment, a slave port of second interconnect matrix  32  may be connected to a slave port of the first interconnect matrix  12 . This connection may be made through a bridge  34 , such as a 64-bit to 32-bit downsizer. In this configuration, the master port of the second interconnect matrix  32  may act as a slave port of first interconnect matrix  12  in order to maintain communication between peripherals of both matrices. 
   Second interconnect matrix  32  may have another master port connected to a multiport DMA controller  36 . In an exemplary embodiment, multiport DMA controller  36  is also connected to a master port of first interconnect matrix  12 . 
   Yet another master port of second interconnect matrix  32  may be connected to a video processing unit  38 . In an exemplary embodiment, video processing unit may comprise a universal video decoder and/or a graphics accelerator. 
   Second interconnect matrix  32  may also have a master port used as a video input/output  40  for connection to video devices. Such devices may include, but are not limited to a camera interface and an LCD controller. 
   Another master port of second interconnect matrix  32  may be connected to devices used for high-speed communication  42 , such as Ethernet, Universal Serial Bus (USB), and Serial ATA (SATA). 
   Multiport controller  26  is connected to at least one of the slave ports of second matrix  32 . The multiport memory controller acts as a slave peripheral. As seen in  FIG. 1 , one port of controller  26  may be connected to one of the slave ports of second matrix  32  through a 32-bit to 64-bit bridge local cache  44  and a 64-bit memory interface  46 , while another port of controller  26  may be connected to another slave port of second matrix  32  through another 32-bit to 64-bit bridge local cache  48  and another 64-bit memory interface  50 . 
   The slave ports of second interconnect matrix  32  may also be connected to memory devices. Such memory devices may include, but are not limited to, a 32-bit SRAM  52 , a 32-bit ROM  54 , and a NAND flash controller  58 . 
   Second interconnect matrix  32  can also be connected to the low throughput area. In an exemplary embodiment, one of the slave ports of second interconnect matrix  32  is connected to a peripheral bus interconnect  60  in the low throughput area through a 32-bit peripheral bridge  56 . In a preferred embodiment, peripheral bus interconnect  60  is a 32-bit peripheral bus interconnect. 
   Peripheral bus interconnect  60  may be connected to a plurality of low throughput components. These low throughput components may include, but are not limited to, cryptography cores  62  and low speed interfaces  64 . Examples of cryptography cores  62  include Advanced Encryption Standard (AES) and Data Encryption Standard (DES), while examples of low speed interfaces  64  include a Universal Asynchronous Receiver-Transmitter (UART), which is a computer component that handles asynchronous serial communication, and a Serial Peripheral Interface, which is a synchronous serial interface for connecting low/medium-bandwidth external devices. 
     FIG. 2  is a flowchart of an exemplary method  200  for accessing the shared memory resource in accordance with the principles of the present invention. At step  202 , both high performance master peripherals and limited performance peripherals may request from the multiport memory controller access to the shared memory resource through their respective matrices. At step  204 , the multiport memory controller grants access to the shared resource. An appropriate resource-dependent scheduling algorithm is used to sort and find the highest pending request among all master requests (if several requests are active at the same time). Then, the access is performed and a chunk of data is read from or written to the shared memory. At step  206 , high performance access is performed through the first interconnect matrix if access is granted. At step  208 , limited bandwidth access is performed through the second interconnect matrix if access is granted. Depending on the scheduling algorithm, more of less bandwidth is available for high performance master peripheral and limited bandwidth master peripheral. While accesses are pending, the multiport controller arbitrates between requests until all (both high performance and limited bandwidth) masters are serviced. At step  210 , it is determined whether or not all pending accesses have been serviced. If they have not all been serviced, then the process continues to arbitrate between requests. If all pending accesses have been serviced, then the process comes to an end. 
   The present invention uses a shared memory controller to avoid the bottlenecks commonly found in the bridges of the prior art. Whereas the architectures of the prior art can be described as being bridge-centric, the architecture of the present invention is centered around the shared memory controller. This design helps provide maximum flexibility of the connections, while maintaining routability between all of the peripherals. If an additional high performance master is required, first interconnect matrix  12  is simply updated by adding a master port. Similarly, if an additional limited bandwidth master, such as a 32-bit standard master, is required, second interconnect matrix  32  is simply updated by adding a master port. There is no need in either situation to add a bridge or a bus. 
   While the different clock domains in the architecture of the present invention may be synchronous, they may alternatively be asynchronous.  FIG. 3  is a schematic diagram of another exemplary dual bus matrix architecture  300  illustrating the clock domain boundary in accordance with the principles of the present invention. Dotted line  336  illustrates the boundary between the DDR Clock Domain for the multiport shared memory controller, the Core System Clock Domain for 64-bit high performance, and the 32 System Clock Domain for the 32-bit standard system area. 
   The Core System Clock Domain comprises a first interconnect matrix  302 , such as a 64-bit AHB matrix. The Core System Clock Domain also preferably includes a core processor  304  (such as ARM1176), high performance masters  306  (such as 64-bit AHB masters), and high performance slaves  308  (such as 64-bit AHB slaves) connected to first interconnect matrix  302 . 
   The 32 System Clock Domain comprises a second interconnect matrix  316 , such as a 32-bit AHB matrix. First interconnect matrix  302  may be connected to second interconnect matrix  316  through a bridge  322 , such as a 64-bit to 32-bit Double Domain Interface. The 32 System Clock Domain also preferably comprises standard masters  324  (such as 32-bit AHB masters) and standard slaves  326  (such as 32-bit AHB slaves) connected to second interconnect matrix  316 . The 32 System Clock Domain may also comprise a peripheral bus interconnect  330  connected to second interconnect matrix  316  through a 32-bit peripheral bridge  328 . In an exemplary embodiment, peripheral bus interconnect  330  is a 32-bit peripheral bus interconnect. Peripheral bus interconnect  330  may be connected to a plurality of components, such as cryptography cores  332  and low speed interfaces  334 . 
   The DDR Clock Domain comprises a multiport shared memory controller  310 , such as a 64-bit multiport SDR/DDR/DDR2 controller. First interconnect matrix  302  is connected to shared memory controller  310 , such as through Double Domain Interface  312  for port  0  and Double Domain Interface  314  for port  1 . Second interconnect matrix  316  is also connected to shared memory controller  310 , such as through Double Domain Interface  318  for port  2  and Double Domain Interface  320  for port  3 . 
   As mentioned above, the different clock domains in the architecture of the present invention may be asynchronous. For example, the Core System Clock Domain may run at 133 Mhz, while the 32 System Clock Domain runs at 100 Mhz and the DDR Clock Domain runs at 200 Mhz. In this embodiment, only a limited region is running at the maximum frequency. 
   While the invention has been described with reference to an exemplary embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention.