Abstract:
To correct for any source of non-linearity and noise introduced in the power amplification of a pulse modulated signal, a correction unit is applied in-between the pulse modulator and the switching power amplification stage. The correction unit is controlled to have a compensating effect, by introducing continuous delays on the individual pulse edges on the basis of error information provided by an error processing block. One preferred embodiment of the invention comprises: a Correction Unit with means to control the delays of the individual pulse edges as a function of a control input signal V e ; a state feedback block A with compensation; a reference shaping block R to modify the pulsed reference v r  for optimized error estimation; a difference block to generate an error signal and a compensator C to shape this error. The invention makes it possible to implement practical digital to analog power conversion, with efficient compensation of any non-linearity and noise introduced in the switching power stage and filter, such that great efficiency, high performance and low system complexity is combined. Applications are direct digital to audio power conversion and improved general DC-DC or DC-AC power conversion systems controlled from the digital domain.

Description:
TECHNICAL FIELD 
     This invention relates to power amplification of pulse modulated signals by a switching power stage. The invention may advantageously be used for improved conversion of a digital signal directly to analog power. Applications are direct digital audio power conversion and general DC-DC or DC-AC power conversion systems controlled from the digital domain. 
     BACKGROUND 
     The advantages of power amplification based on a switching power stage are well known. The high efficiency provides several advantages, in terms of minimal weight and volume, higher power handling capability and improved reliability. The fundamental elements in switching power amplification are the modulator, the switching power stage and the demodulation filter to reconstitute the modulated signal. The non-linearity of the switching power stage presents a significant impediment to maintain the modulator performance throughout the subsequent power conversion by a switching power stage. This problem is fundamental and independent on the use of analog modulation as analog PWM, or digital modulation as direct digital PCM-PWM conversion. 
     In prior art, compensation for the non-ideal behavior has generally been attempted with various feedback control methods. U.S. Pat. No. 4,724,396 and U.S. Pat. No. 5,521,549 discloses examples of this method with audio power amplification as specific application. However, linear feedback control methods require an analog low frequency reference. It is desirable with a more direct digital source to power conversion to simplify the power conversion in that no separate D/A converter is needed. Furthermore, analog modulation circuitry and carrier generators will not be required. International patent application no. WO92/11699 and international patent application no. WO97/37433 discloses improved methods for digital PCM-PWM conversion for digital digital to power amplification. In practice, these systems are hardly easy to implement, since compensation for the fundamental error sources within the switching power conversion are not provided. The application of digital feedback control referenced to the digital source is complicated in that an analog—digital converter is needed in the feedback path. This renders normal feedback control impractical. 
     The published international patent application EP758164 discloses a feedback method local to the switching power stage, in which the power stage output is feed back and summed with a pulse width modulated input. The resulting signal is used to drive the switching power stage. The compensation effect however will be limited and it is difficult to control the improvements towards all error sources. 
     In conclusion, no invention in prior art exist for general power amplification of a pulse-modulated signal, that incorporates simple and effective means to eliminate any source of non-linearity and noise in the switching power amplification stage. 
     Accordingly, the primary objective of the present invention is to enable improved power amplification of a pulse modulated signal, where all error sources related to the power stage and demodulation filter are eliminated, such that the modulator performance can be maintained throughout the subsequent elements all the way to the output. Another objective of the invention is to provide a practical digital PCM—power conversion system, that is insensitive to power stage non-linearity, perturbation on the power supply and any other non-ideal elements. 
     SUMMARY OF THE INVENTION 
     According to claims  1  and  2 , the objectives of the invention are achieved by the introduction of a correction unit in-between the pulse modulator and the switching power amplification stage. The correction unit provides compensation by means of pulse re-timing on the pulse edges, said re-timing controlled to have a “predistorting” effect, such that the resulting switching power stage output is free from distortion, noise or any other undesired contribution. 
     According to claim  3 , one preferred embodiment of the invention is particular in that pulse re-retiming in the correction unit is a linear function of an error signal input. This is advantageous in that the resulting control system is linear, whereby system design and optimization is simplified and the performance improvement controllable. 
     According to claim  4 , it is expedient that the pulse reference control system comprises the following fundamental elements: 
     An input terminal taking a pulse modulated signal. 
     A Correction Unit with means to correct the delays of the individual pulse edges, controlled by a control input. 
     A state feedback with compensation. 
     A reference-shaping block to modify the pulsed reference input for optimal error estimation. 
     A difference block to generate an error signal and a compensator to shape this error. 
     The invention includes various embodiments regarding actual realization of the control function within the correction unit. According to claims  6 - 10 , the invention includes various advantageous embodiments concerning improved digital—analog power conversion suitable for audio power amplification. 
     The invention is a fundamentally new control method for improved amplification of a pulse modulated input signal. The application range is extremely broad in that the invention can be used with any pulse-modulated input, modulated in the analog or digital domain, and feed any load where a pulsed power signal of controllable quality is needed. Ultimately, the principle of the invention may realize perfect reproduction of the pulsed reference such that the output is a constant times the input, independent on any disturbances that is introduced during power conversion. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be further described with reference to the drawings in which: 
     FIG. 1 shows a principle of power amplification based on either analog or digital input that is well known to the art. 
     FIG. 2 shows a method of power conversion based on digital pulse modulation. This approach is well known to the art. 
     FIG. 3 shows a general model of the invention. 
     FIG. 4 shows a preferred embodiment of the invention, in terms of a dual input pulse referenced control method based on state feedback from the power stage. 
     FIG. 5 shows various embodiments of the invention regarding pulse edge delay error correction methods. 
     FIG. 6 shows the principle for one preferred embodiment of the invention regarding edge delay correction unit implementation that implements the expedient linear control function, by operating on both edges of the pulse. 
     FIG. 7 shows a system block diagram for one preferred implementation for a double-sided edge delay correction unit. 
     FIG. 8 shows an advantageous application of the invention, in terms of a digital—power conversion system for audio purposes, where the reference shaping block R is unity and the feedback block A has a constant attenuation characteristic. 
     FIG. 9 shows a linear model for the advantageous application of the invention in FIG.  8 . The model defines an appropriate compensator for the application. 
     FIG. 10 shows yet another advantageous embodiment of the invention, in terms of a digital—power conversion system for audio purposes, where the reference shaping block and feed-back block have first order characteristics to improved error estimation. 
     FIG. 11 shows yet another advantageous embodiment of the invention, in terms of a digital—power conversion system for audio purposes, where a global feedback source is used for error correction. 
     FIG. 12 shows the control loop characteristics for one preferred design approach for the preferred embodiment of FIG.  8 . 
     FIG. 13 shows the closed loop system characteristics for one preferred design approach for the preferred embodiment of FIG.  8 . 
     FIG. 14 shows the results of a simulation of error correction towards a deterministic pulse timing error source in the switching power stage. The example embodiment of the invention reduces the distortion considerably. 
     FIG. 15 shows a simulation of the effects of power supply perturbations. The example embodiment of the invention eliminates the intermodulation caused by this error source. 
    
    
     DETAILED DESCRIPTION 
     To fully understand the invention it is helpful to discuss the fundamental physical limitations that lies within amplification of a pulse modulated signal to power levels. Most problems relate to the switching power stage that serves to amplify the pulses coming from the modulator. It is expedient to divide the error sources in to pulse timing errors (PTE) and pulse amplitude errors (PAE). Pulse Timing Errors arise from: 
     Delays from turn-on or turn-off to the actual transition at the output of the switching power stage are different in the turn-on and turn-off case. The delays depend on various parameters in the power switch physics and in the hardware, that drives the switches. 
     The delay between a turn-off and the following turn-on in a switching leg. 
     The finite rise- and fall-times as opposed to the infinitely fast switching required by theory. 
     Pulse Amplitude Errors (PAE) mainly arise from: 
     Noise from the power supply that feeds the switching power stage. Any power supply ripple or noise will intermodulate with the modulated audio signal, and the switching power stage has a Power Supply Rejection Ratio (PSRR) of 0 dB. 
     Finite impedance for the power switches. 
     High frequency resonant transients on the resulting pulse power signals. 
     There are additional error sources relating to the non-ideal modulation and non-ideal demodulation. The demodulation filter errors may introduce further distortion, since magnetic core materials are not ideal. In addition, the filter increases the total output impedance. Accordingly, changes in load impedance will distort the frequency response. 
     FIG. 1 shows a method, well known in the art, to realize power amplification based on analog pulse modulation techniques. The modulator output feeds a switching power stage, the output of which is demodulated and feed to the load. A linear control system referenced to the analog input serves to minimize the errors within the power conversion, such that the effects of the above mentioned errors can be minimized. A digital input requires a separate D/A converter to generate the analog input that serves as input to the control system. FIG. 2 illustrates the simplified and desirable system for direct digital to analog power conversion using digital pulse modulation techniques, also well known in prior art. The application of error feedback control is complicated in that an analog/digital converter would be needed to enable comparison with the digital reference source. This compromises both performance and complexity and renders the method impractical. 
     The new principle of the invention is shown by the general block diagram in FIG.  3 . The modulator is feed to a correction unit that serves to correct or “predistort” the pulse modulated signal v r  to generate the compensated pulse signal v c , such that the said non-ideal behavior within the subsequent power conversion and demodulation are eliminated. This is carried out by means of intelligent pulse edge delays on each of the pulse edges, controlled by an input control signal v e  to the correction unit. The method will henceforth be referenced to as Pulse Edge Delay Error Correction (PEDEC). 
     The invention is a fundamentally new control method for improved amplification of a pulse modulated input signal. The application range is broad in that the invention can be used with any pulse-modulated input, modulated in the analog or digital domain, and feed any load where a pulsed power signal of controllable quality is needed. 
     The invention relies on two fundamental facts: 
     The pulse modulator can generate a very high quality pulsed waveform, that may be used as reference for the control system. 
     All error sources (PAE or PTE) within the switching power conversion can be corrected by intelligent pulse re-timing and all error sources only need minor pulse edge re-timing for perfect elimination. 
     The edge correction may be implemented using single-sided or double-sided edge delay correction, as shown conceptually in FIG.  5 . The choice of single or double edge correction is independent of the type of modulation method. The control of both edges leads to efficient correction and furthermore has simple implementation strategies. Subsequently, the following description of this aspect of the invention will focus on double edge correction. 
     One preferred embodiment of the invention is shown FIG.  6 . The dual input pulse referenced feedback control system comprises: 
     An input terminal that is feed by a pulse modulated reference signal v r . 
     A Correction Unit (PEDEC unit) with means to control the delays of the individual pulse edges and generate the corrected output pulse signal v c . 
     A state feedback block A including compensation from the power stage block. 
     An optional reference shaping block R. 
     A subtraction unit to derive error information. 
     A compensator C to shape said error and feed the Correction Unit with said shaped error v e . 
     The correction unit may be realized by various linear and also non-linear methods. A particularly advantageous embodiment of the invention regarding PEDEC unit realization is described hereinafter. It proves advantageous to let the control error signal v e  to the PEDEC unit realizes an effective change in pulse width Δt w  at the end of each switching cycle that is proportional to the control signal input v e :                       t   w              v   e         =     k   w             (   1   )                                
     By averaging within a single switching cycle, the relationship between an increment in pulse width Δt w  and the corresponding, change in the average ox the PEDEC unit output Δ{overscore (v)} c  can be established. Assume for simplicity in the following that the PEDEC unit output pulse amplitude is unity. Δ{overscore (v)} c  is related to Δt w  as:                Δ          v   ~     c       =         1     t   s            (         ∫   0       d   ·     t   s       +     Δ                   t   w                1   ·                   t         +       ∫       d   ·     t   s       +     Δ                   t   w           t   s              (     -   1     )     ·                   t           )       =       2     t   s          Δ                   t   w                 (   2   )                                
     Where d is the duty-cycle within the present switching cycle and f s  is the switching period. Hence:                         v   ~     c              t   w         =     2     t   s               (   3   )                                
     Combining and (1) and (3), the linear control function arrives:                k   PEDEC     =                v   ~     c              v   e         =       2        k   w         t   s                 (   4   )                                
     This preferred linear control function is advantageous in that it simplifies controller design and provides controllable performance improvements compared to e.g. the implementation of a non-linear control function. 
     A preferred embodiment of the invention is particular in that the implementation of a double-sided correction unit that implements (4) is simple. The method is shown in FIG.  6 . The linear control function is realized by a limited integration of the reference v r , thus generating the signal v i . A comparison between the modified reference with the control signal v e  caused the pulse edges to be re-timed. From FIG. 6 in follows that:                  t   ^     w     =           t   w     -       t   0            v   e       V   l                      ⇒     
          Δ                   t   w         =           t   ^     t     -       t   ^     t       =     {           t   0           (       v   e     &gt;   1     )                 t   0          v   e             (       -   1     ≤     v   e     ≤   1     )               -     t   0             (       v   e     &lt;   1     )                         (   5   )                                
     Where ({circumflex over ( )}) indicates the corrected variable after passing the PEDEC unit. It is assumed that all pulse amplitudes are normalized to unity. In this preferred implementation, k w  as defined in (1) is:                k   w     =              t   w              v   e         =     t   0               (   6   )                                
     The following equivalent control gain emerge for the proposed implementation of double sided edge correction:                k   PEDEC     =       2        t   0         t   s               (   7   )                                
     FIG. 7 shows a preferred implementation of the double-sided edge correction method. The method is very simple and straightforward. 
     For optimal control in this preferred solution, the pulses should have a certain minimal width. The minimum pulse width for optimal performance is related to the modulation index M and switching period t s  as:                    t     w   ,   min       ≥     t   0       ⇒     M   max       =     1   -                  2        t   0         t   s                 (   8   )                                
     This constraint on pulse width and maximal modulation index M max  does not present a fundamental limitation, since the correction still will work partially beyond this limit. Since only a limited correction range is generally needed, t 0  is preferably on order of magnitude or more lower that t i . 
     The invention includes several embodiments regarding the application of the invention specifically in digital to analog power conversion. One preferred embodiment is the system shown in FIG.  8 . Using PEDEC in combination with one of the high performance digital pulse width modulation methods (PCM-PWM methods) that are known to the art, the signal will remain digital or pulsed throughout the main audio chain. No analog modulator or carrier generator is needed as with analog pulse modulation, since the system is controlled exclusively by the digital modulator. In this particular embodiment of the invention, the state feedback is a voltage feedback from the switching power stage output v p . The feedback path compensator is a simple attenuation, and the compensator block C(s) is a linear filter. Despite the simple controller structure of this particular embodiment, the system introduces a very powerful and flexible control of system performance. 
     The preferred linear control function provides great flexibility in performance optimization. An example of PEDEC control system design is specified in the following. The compensator is defined in the linear model of the system as shown in FIG.  9 . The PEDEC unit has been replaced by its equivalent linear gain and the resulting system has been redrawn to emphasize the dual input character of the PEDEC based digital to power conversion system. The specified compensator provides sufficient flexibility to optimize the performance to various characteristics. The resulting loop transfer function is derived directly from the system model:                L        (   s   )       =             K   p          k   PEDEC       K          C        (   s   )         =           K   C          K   P          k   PEDEC       K                           τ   p1        s     +   1         (         τ   p1        s     +   1     )          (         τ   p2        s     +   1     )          (         τ   p3        s     +   1     )                     (   9   )                                
     All non-ideal effect as noise, distortion or power supply perturbations that influence the power stage gain K p  are reduced by the sensitivity function S(s)=(1+L(s)) −1 . The actual loop shaping is a compromise between loop bandwidth and the desired sensitivity function. Further considerations are stability and robustness to uncertainty in system parameters. Table 1 gives as set of normalized system parameter values that will lead an appealing compromise between these aspects. 
     The compensator DC gain K C  is optimized to yield the desired loop bandwidth. A bandwidth of 6-8 times target bandwidth is a good compromise between efficiency and error correction capability. FIG. 12 shows Bode plots for each component and the resulting loop transfer function. 
     
       
         
               
             
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Example of frequency normalized parameters 
               
             
          
           
               
                 Parameter 
                 Value 
                 Comment 
               
               
                   
               
               
                 k PEDEC   
                  0.2 
                 Equivalent PEDEC unit gain 
               
               
                 K 
                 10 
                 System gain = 20dB 
               
               
                 K P   
                 10 
                 Equivalent power stage gain = 20dB 
               
               
                 f u   
                  6 
                 Bandwidth 
               
               
                   
               
               
                 
                   
                     
                       
                         
                           f 
                           p1 
                         
                         = 
                         
                           1 
                           
                             2 
                              
                             x 
                              
                             
                                 
                             
                              
                             
                               τ 
                               p1 
                             
                           
                         
                       
                     
                             
                     
                         
                     
                   
                 
                 
                   
                     
                       
                         
                           f 
                           w 
                         
                         20 
                       
                     
                             
                     
                         
                     
                   
                 
                 Loop parameter 
               
               
                   
               
               
                 
                   
                     
                       
                         
                           f 
                           p2 
                         
                         = 
                         
                           1 
                           
                             2 
                              
                             x 
                              
                             
                                 
                             
                              
                             
                               τ 
                               p2 
                             
                           
                         
                       
                     
                             
                     
                         
                     
                   
                 
                 
                   
                     
                       
                         
                           f 
                           w 
                         
                         20 
                       
                     
                             
                     
                         
                     
                   
                 
                 Loop parameter 
               
               
                   
               
               
                 
                   
                     
                       
                         
                           f 
                           p3 
                         
                         = 
                         
                           1 
                           
                             2 
                              
                             x 
                              
                             
                                 
                             
                              
                             
                               τ 
                               p3 
                             
                           
                         
                       
                     
                             
                     
                         
                     
                   
                 
                 2f u   
                 Loop parameter 
               
               
                   
               
               
                 
                   
                     
                       
                         
                           f 
                           z1 
                         
                         = 
                         
                           1 
                           
                             2 
                              
                             x 
                              
                             
                                 
                             
                              
                             
                               τ 
                               z1 
                             
                           
                         
                       
                     
                             
                     
                         
                     
                   
                 
                 
                   
                     
                       
                         
                           f 
                           w 
                         
                         2 
                       
                     
                             
                     
                         
                     
                   
                 
                 Loop parameter 
               
               
                   
               
               
                 f f   
                  2 
                 Filter natural frequency 
               
               
                   
               
               
                 Q f   
                 
                   
                     
                       
                         1 
                         
                           3 
                         
                       
                     
                             
                     
                         
                     
                   
                 
                 Filter Q (Bessel characteristic) 
               
               
                   
               
             
          
         
       
     
     The gain of the system is controlled by the A-block, and with the given example embodiment, the PEDEC control system will force the system gain to be constant within the target bandwidth. This stabilizes both system gain and the frequency response. According to the linear model for this example embodiment of the invention in FIG. 9, the resulting system response is constituted of two contributions, since the reference has two inputs in the loop. The system transfer function is:                H        (   s   )       =             C        (   s   )            K   P          k   PEDEC           1   +     L        (   s   )                H   A           +       K   P         1   +     L        (   s   )                H   S             =         K   P          [         C        (   s   )            k   PEDEC       +   1     ]         1   +     L        (   s   )                     (   10   )                                
     In the special (but not unusual) case where K=K p  the system transfer function is constant:                H        (   s   )       =         K        [         C        (   s   )            k   PEDEC       +   1     ]         1   +       C        (   s   )            k   PEDEC           =   K             (   11   )                                
     In the general case:                H        (   s   )       ≈     {         K         (     f   &lt;     f   u       )               K   P           (     f   &gt;&gt;     f   u       )                     (   12   )                                
     FIG. 13 shows the resulting Bode plots for the closed system, consisting of two contributions forming the loop response and a total system response with the demodulation filter. The constant gain characteristic of the loop caused by K=K p . The demodulation filter exclusively determines the response of the system. 
     The parameters of the example embodiment above are only illustrative and various other system characteristics can be devised by other loop transfer function gain/bandwidth compromises etc. 
     Other advantageous embodiments, also suitable for high quality digital to power conversion are shown FIG.  10  and FIG.  11 . These alternative embodiments are characterized by using different compensator and reference shaping blocks. The embodiment in FIG. 10 is preferably based on a first order characteristic in both the reference shaping block R(s) and the feedback compensator A(s). The advantages in the demodulation of both reference and feedback signal are minimized noise within the control system and furthermore lower bandwidth requirements for the feedback compensator. The embodiment in FIG. 11 is based on a global feedback source such that demodulation filter errors are included within the loop and also corrected for. This requires a second order reference shaper for optimal error estimation. 
     The correction effects towards pulse timing errors (PTE) is shown in FIG. 14, where THD for the open loop system and three PEDEC controller configurations have been investigated at the worst case signal frequency. Clearly, the controller considerably reduces the effects of this particular error source. Furthermore, adjusting the compensator gain K C  can control the improvements. In this particular situation the distortion is reduced 20 dB-30 dB. FIG. 15 shows an investigation of PAE with a severe power supply perturbation of 10 Vpp. Top figure visualizes the clear intermodulation between power supply and signal. Bottom figure shows how the PEDEC controller eliminates this effect such that the intermodulation is no more visible in the time domain. The intermodulation distortion is reduced more than 40 dB compared to the open loop case, as predicted by the sensitivity function in theory. 
     Although the invention is described hereinbefore with respect to illustrative embodiments thereof, it will be appreciated that the foregoing and various other changes, omissions and additions may be made without departing from the spirit and scope of this invention.