Abstract:
A method of forming a spacer structure adjacent to the sidewall of a floating gate electrode with a top surface and sidewalls, the floating gate electrode being formed on a silicon oxide dielectric layer, and the silicon oxide dielectric layer being formed on the top surface of a semiconductor substrate include the following steps. Form a cap layer on the floating gate electrode, and a blanket tunnel oxide on the device. Form an inner dielectric, spacer layer over the device including the cap layer and the sidewalls thereby with conforming sidewalls, and an outer dielectric, spacer layer over the inner dielectric, spacer layer including the conforming sidewalls. Partially etch away the outer dielectric, spacer layer with a dry etch to form a outer dielectric spacer adjacent to the conforming sidewalls. Then partially etch away more of the outer dielectric, spacer layer with a wet etch to expose a portion of the conforming sidewalls of the inner dielectric, spacer layer. Finally, etch away the portion of the inner dielectric, spacer layer unprotected by the outer dielectric spacer before forming interelectrode dielectric layers and the control gate electrode.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to method and structures for the manufacture of semiconductor memory devices and more particularly to improved flash EPROM devices. 
     2. Description of Related Art 
     The processing of a silicon nitride (Si 3  N 4 ) spacer (180 A) etching is very critical for this type of manufacturing process for flash EPROM devices. Because the dimensions of the Si 3  N 4  spacers are so small, it is difficult to control and maintain this process. The function of this thin silicon nitride spacer is to prevent write disturbance that is caused by reverse tunneling. 
     In general sidewall spacers formed of multiple layers are known in the industry. 
     U.S. Pat. No. 5,573,965 of Chen et al. for &#34;Method of Fabricating Semiconductor Devices and Integrated Circuits Using Sidewall Spacer Technology&#34; shows a method of forming a transistor using multi-layered structures of silicon dioxide alone or of silicon dioxide/silicon nitride. Chen shows the first spacer layer underlying subsequent spacers which is similar in structure as the invention. 
     U.S. Pat. No. 5,183,771 of Mitsui et al. for &#34;Method of Manufacturing LDDFET Having Double Sidewall Spacers&#34; shows a method of forming a transistor having double sidewall spacers both formed from silicon oxide layers over silicon substrate adjacent to the polysilicon gate electrode of a compound polysilicon/polycide gate electrode of a CMOS device, without a floating gate electrode. 
     U.S. Pat. No. 5,489,546 of Ahmad et al. &#34;Method of Forming CMOS Devices Using Independent Thickness Spacers in a Split-Polysilicon DRAM Process&#34; shows a transistor having a double sidewall spacer formed over a gate oxide layer with both layers composed of silicon nitride designed to vary the channel length in a CMOS device with a compound polysilicon/polycide gate electrode, without any floating gate electrode. Ahmad et al. also shows the first spacer layer underlying the subsequent spacer. 
     The above patents do not show the details/(exact compositions of the two spacer layers) of the invention. 
     SUMMARY OF THE INVENTION 
     In accordance with this invention a spacer structure is formed of a combination of a silicon nitride spacer with a silicon oxide spacer. 
     In accordance with this invention where an EPROM device includes an HTO silicon oxide structure formed over a polysilicon floating gate electrode, the HTO oxide is protected by a silicon nitride spacer formed by depositing a blanket silicon nitride layer over the HOT oxide layer formed by depositing a blanket silicon oxide over the blanket silicon nitride layer. Then the following step is to etch back the silicon oxide layer to form sidewall spacers adjacent to the silicon nitride layer. Then, a combination silicon nitride/silicon oxide sidewall spacer is formed adjacent to the floating gate electrode. 
     In accordance with this invention a method is provided for forming a spacer structure adjacent to the sidewall of a floating gate electrode composed of doped polysilicon with a top surface and sidewalls, the floating gate electrode being formed on a silicon oxide dielectric layer, and the silicon oxide dielectric layer being formed on the top surface of a semiconductor substrate, the steps of the method comprising steps performed in the following sequence of steps. 
     a) Form a cap layer of polysilicon oxide over the top surface of the floating gate electrode followed by Form a thin, blanket, tunnel oxide film over the device. 
     b) Form a inner dielectric, spacer layer over the device including the cap and the tunnel oxide layer and adjacent to the sidewalls of the floating gate electrode thereby forming conforming sidewall spacers adjacent to the sidewalls of the floating gate electrode. 
     c) Form an outer dielectric, spacer layer over the inner dielectric, spacer layer including the conforming sidewalls. 
     d) Partially etch away the outer dielectric, spacer layer with a dry etch to form a outer dielectric spacer adjacent to the conforming sidewalls. 
     e) Perform the additional step of partially etching away more of the outer dielectric, spacer layer with a wet etch to expose a portion of the conforming sidewalls of the inner dielectric, spacer layer, and 
     f) Etch away the portion of the inner dielectric, spacer layer unprotected by the outer dielectric spacer. 
     Preferably, the cap layer has a thickness of about 100 Å; the inner dielectric, spacer layer has a thickness of about 180 Å; and the outer dielectric, spacer layer comprises a thick silicon oxide layer. 
     Preferably, the wet etch of of step (e) is performed with a hydrofluoric acid solution of about 50 H 2  O: 1 HF, the step (f) is performed in a wet etching process using a hot phosphoric acid solution (H 3  PO 4 ); form an interelectrode dielectric layer over the device; and form a control gate electrode over the interelectrode dielectric layer to form a memory cell. 
     In accordance with another aspect of this invention, an EPROM semiconductor memory device is formed on a semiconductor substrate. There is a first gate oxide layer formed on the surface of the substrate; a floating gate electrode with a top surface and sidewalls formed on the surface of the gate oxide layer, the floating gate electrode being composed of doped polysilicon; a cap layer composed of an oxide of the floating gate electrode over the top surface of the floating gate electrode; a thin tunnel oxide layer covering the cap layer, the floating gate electrode and the gate oxide layer; a spacer structure adjacent to the sidewall of the floating gate electrode formed on the tunnel oxide layer above the gate oxide layer, the spacer structure comprising an inner dielectric, spacer layer and an outer dielectric, spacer layer formed over the device; the inner dielectric, spacer layer being formed as conforming L-shaped sidewalls adjacent to the sidewalls of the floating gate electrode; the outer dielectric, spacer layer being formed over the inner dielectric, spacer layer, the outer dielectric, spacer layer forming a spacer on the conforming L-shaped sidewalls of the inner dielectric, spacer layer; an interelectrode dielectric layer over the device cap, the spacer structure and the substrate; a control gate electrode over the interelectrode dielectric layer patterned with the floating gate electrode to form an gate electrode stack; the substrate including source/drain regions in the substrate cooperating with the gate electrode stack to form a memory cell. 
     Preferably, the cap layer has a thickness of about 100 Å, the inner dielectric, spacer layer comprises a silicon nitride layer having a thickness of about 180 Å, and the outer dielectric, spacer layer comprises a thick silicon oxide layer. 
     An advantage of the method of this invention is that it is easy to control and maintain the process. 
     Another advantage of the method of this invention is that the loss of the HTO (tunnel) oxide layer is reduced by the protection thereof provided by this method. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other aspects and advantages of this invention are explained and described below with reference to the accompanying drawings, in which: 
     FIGS. 1A-1G illustrate the process steps of a method for producing an EPROM device with a HTO thermal oxide cap and above the floating gate of the EPROM device. 
     FIGS. 2A-2I illustrate the process steps of a method for producing an EPROM device with a HTO thermal oxide cap and above the floating gate of the EPROM device in accordance with the method of this invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The process of FIGS. 1A-1G illustrate a first method for producing an EPROM device 10 with a HTO thermal oxide cap 18 and above the floating gate of the EPROM device 10. The problem with this method is that the silicon nitride spacers 24S, 24S&#39; are thinned by the process used which makes it difficult to satisfy manufacturing specifications. 
     Referring to FIG. 1A, an EPROM device 10 is shown in a early stage of a possible manufacturing process which exemplifies the problem solved by this invention. A P-doped, silicon, semiconductor substrate 12 has a gate oxide layer 14 formed on the surface thereof. Above the gate oxide layer 14, a doped polysilicon conductor layer 16 has been deposited. Then a silicon nitride (Si 3  N 4 ) mask 20 with opening 20&#39; has been formed over the doped polysilicon conductor layer 16 by a process of Chemical Vapor Deposition (CVD) in a furnace in an atmosphere of HN 3  and silane SiH 4  to form the silicon nitride mask layer 20. 
     Referring to FIG. 1B the EPROM device 10 of FIG. 1A is shown after a thermal oxidation process has been employed to form a polyoxide (poly-silicon oxide) cap 18 with a by a HTO (High Temperature Oxide) process thickness of about 1,500 Å through the opening 20&#39; in the Si 3  N 4  mask 20 in a conventional HTO (High Temperature Oxidation) process by CVD (Chemical Vapor Deposition). 
     Referring to FIG. 1C the EPROM device 10 of FIG. 1B is shown after the silicon nitride (Si 3  N 4 ) mask 20 has been stripped away. The newly exposed portion of the doped polysilicon conductor layer 16 which was unprotected by the silicon oxide cap 18 was etched away by an anisotropic plasma etching process with an etchant gas mixture composed of C 2  F 6  gas and helium (He) gas which gas mixture removes the exposed portion of blanket polysilicon layer 16 but does not attack the exposed silicon oxide cap 18 forming the floating gate electrode 16F from the blanket polysilicon layer 16. 
     Referring to FIG. 1D the EPROM device 10 of FIG. 1C is shown after deposition of a blanket tunnel oxide layer 22T covering device 10. Tunnel oxide layer 22T comprises a thin silicon oxide layer as will be well understood by those skilled in the art. 
     Referring to FIG. 1E the EPROM device 10 of FIG. 1D is shown after deposition of a blanket silicon nitride (Si 3  N 4 ) spacer layer 24 covering blanket tunnel oxide (silicon oxide) layer 22T with a thickness of about 180 Å. 
     Referring to FIG. 1F the EPROM device 10 of FIG. 1E is shown after the silicon nitride spacer layer 24 has been etched by a plasma etching step with an etchant composed of sulfur hexafluoride (SF 6 ) and oxygen gas (O 2 ) to produce silicon nitride spacers 24S, 24S&#39; adjacent to the sidewalls of floating gate electrode 16F. The spacers 24S, 24S&#39;, which are substantially shorter than the sidewalls of floating gate electrode 16F, have a remaining thickness of about 300 Å vertically (y axis) and a thickness of about 50 Å horizontally (x axis) from the sidewall of the floating gate electrode 16F. The silicon nitride spacers 24S, 24S&#39; adjacent to the sidewalls of floating gate electrode 16F are used to protect against the reverse tunneling from the control gate electrode 28 in FIG. 1G to the floating gate electrode 16F. 
     Referring to FIG. 1G the EPROM device 10 of FIG. 1F is shown after an N+ doped source region 32 and an N+ doped drain region 34 have been formed in the substrate 12 by ion implantation in accordance with a conventional process of angular ion implantation so that the source region 32 underlies the floating gate 16F. 
     After source region 32 and drain region 34 were formed a blanket second gate oxide layer 26 and a blanket control gate electrode layer were deposited on the device 10. Next followed etching of control gate electrode layer to form the control gate electrode 28. 
     The blanket second gate oxide layer 26 was deposited to cover the exposed surfaces of the tunnel oxide layer 22T and silicon nitride spacers 24S, 24S&#39; as well as exposed portions of the upper sidewalls of floating gate electrode 16F, and silicon oxide cap 18. The doped polysilicon control gate electrode 28 has been patterned to lie over the left side of the device 10 overlying the left edge of the silicon oxide cap 18. 
     In addition note that the source region 32 is connected to the voltage source V ss  as indicated by the schematic line 33 and the drain region 34 is connected to the bit line BL by schematic line 35. 
     One problem with the process of FIGS. 1A-1G is that it is very difficult to maintain the process because the process has an etching window which is very small on the order of a 3&#34; process. It is difficult to maintain an etch recipe with a low etch rate and good uniformity. In addition, the problem of thinning the silicon nitride spacer layer 22 with a thickness of about 180 Å led to the design described below with reference to FIGS. 2A-2I. 
     Referring to FIG. 2A, an EPROM device 40 is shown in a early stage of a manufacturing process in accordance with this invention. A P-doped, silicon, semiconductor substrate 42 has a gate oxide layer 44 formed on the surface thereof. A doped polysilicon conductor layer 46 has been deposited above gate oxide layer 44. Then a silicon nitride (Si 3  N 4 ) mask 50 with opening 50&#39; has been formed over the doped polysilicon conductor layer 46. 
     Referring to FIG. 2B the EPROM device 40 of FIG. 2A is shown after a thermal oxidation process has been employed to form a polyoxide (poly-silicon oxide) cap 48 with a thickness of about 1,500 Å through the opening 50&#39; in the Si 3  N 4  mask 50 in a conventional HTO (High Temperature Oxidation) process by Chemical Vapor Deposition (CVD). 
     Referring to FIG. 2C the EPROM device 40 of FIG. 2B is shown after the silicon nitride (Si 3  N 4 ) mask 50 has been stripped away with the portion of the doped polysilicon conductor layer 46 which was unprotected by the silicon oxide cap 48. Layer 46 was etched using an anisotropic plasma etching process with an etchant gas mixture composed of C 2  F 6  gas and helium (He) gas which gas mixture removes the exposed portion of blanket polysilicon layer 46 but does not attack the exposed silicon oxide cap 48 forming the floating gate electrode 46F from the blanket polysilicon layer 46. 
     Referring to FIG. 2D the EPROM device 40 of FIG. 2C is shown after deposition of a blanket tunnel oxide layer 52T covering device 40. Tunnel oxide layer 52T comprises a thin silicon oxide layer as will be well understood by those skilled in the art. 
     Referring to FIG. 2E the EPROM device 40 of FIG. 2D is shown after deposition of a blanket silicon nitride (Si 3  N 4 ) spacer layer 53 has a thickness within a range from about 140 Å to about 180 Å, preferably with a thickness of about 180 Å. The silicon nitride (Si 3  N 4 ) spacer layer 53 has sidewalls adjacent to the sidewalls of the floating gate electrode 46F conforming to the pattern thereof. 
     Referring to FIG. 2F the EPROM device 40 of FIG. 2E is shown after formation of a blanket silicon oxide film 54 by a deposition process such as low temperature PECVD (Plasma Enhanced Chemical Vapor Deposition) using a TEOS (TetraEthylOrthoSilicate) source. The blanket silicon oxide film 54 has a thickness from about 700 Å to about 1,200 Å, (preferably a thickness of about 1000 Å) over the silicon nitride (Si 3  N 4 ) spacer layer 53. 
     Referring to FIG. 2G the EPROM device 40 of FIG. 2F is shown after anisotropic dry etching of the silicon oxide film 54 leaving silicon oxide sidewall spacers 54S, 54S&#39;, which are substantially shorter than the sidewalls of floating gate electrode 46F, adjacent to the sidewalls of the silicon nitride layer 53. The dry etching is performed by plasma etching of the silicon oxide film 54 in an atmosphere comprising a mixture of etchant gases composed of C 2  F 6  gas and helium (He) gas which gas mixture etches back the exposed portion of blanket silicon oxide layer 54 with a high degree of selectivity between the silicon oxide layer 54 and the silicon nitride layer 53 below. 
     Referring to FIG. 2H the EPROM device 40 of FIG. 2G is shown after a wet oxide etch with an etchant (such as a hydrofluoric acid solution of 50 H 2  O: 1 HF) to remove an additional portion of the material of the silicon oxide spacers 54S to adjust the radius thereof to a radius from about 200 Å to about 400 Å to provide reduced size silicon oxide spacers 54S&#39; covering the silicon nitride (Si 3  N 4 ) layer 53 to provide protection thereof and to provide the precisely planned size of silicon nitride (Si 3  N 4 ) spacers 53S, 53S&#39; to be formed in the next step. 
     Then in the next step, the exposed surfaces of silicon nitride (Si 3  N 4 ) spacer layer 53 are etched in wet hot H 3  PO 4  (phosphoric acid) to remove the portions thereof unprotected by the silicon oxide spacers 54S&#39; producing silicon nitride spacers 53S, 53S&#39;. Note that the silicon oxide spacers 54S, 54S&#39; fill in the space defined by the &#34;L&#34; shaped silicon nitride spacers 53S, 53S&#39;. The precisely planned L-shaped silicon nitride spacers 53S, 53S&#39; adjacent to the floating gate electrode 46F protect against the reverse tunneling from the floating gate electrode 46F to the control gate electrode 58, as seen in FIG. 2I. 
     The silicon nitride spacers 53S, 53S&#39; have a thickness as stated above from about 140 Å to about 180 Å have a height of the upright portion of the &#34;L&#34; of about 300 Å vertically (y axis) and a width of the horizontal portion of the &#34;L&#34; of about 200 Å horizontally (x axis) from the sidewall of the floating gate electrode 46F. The silicon oxide spacers 54S, 54S&#39; have dimensions of from about 150 Å to about 300 Å. 
     The height and width of the Si 3  N 4  spacers 53S, 53S&#39; can be controlled easily using the process of this invention because the wet etching rate of silicon nitride layer 53 is very low, (about 60 Å/minute) so it is very easy to control the process time (process window&lt;5&#39;). 
     Referring to FIG. 2I the EPROM device 40 of FIG. 2H is shown after an N+ doped source region 62 and an N+ doped drain region 66 have been formed in the substrate 42 by ion implantation in accordance with a conventional process of angular ion implantation so that the source region 62 partially underlies the floating gate 46F. 
     After source region 62 and drain region 66 were formed a blanket second gate oxide layer 56 and a blanket control gate electrode layer 58 composed of doped polysilicon were deposited on the device 40. Next followed etching of control gate electrode layer to form the control gate electrode 58. The doped polysilicon control gate electrode 58 has been patterned to lie over the left side of the device 40 overlying the left edge of the silicon oxide cap 48. 
     Note that the blanket second gate oxide layer 56 was deposited over device 40 covering the exposed surfaces of the tunnel oxide layer 52T, silicon nitride spacers 53S, 53S&#39;, silicon oxide spacers 54S, 54S&#39; as well as exposed portions of the upper sidewalls of floating gate electrode 46F. Note that polysilicon oxide cap 48 is already covered by tunnel oxide layer 52T. 
     In addition note that the source region 32 is connected to the voltage source V ss  as indicated by the schematic line 63 and the drain region 66 is connected to the bit line BL by schematic line 67. 
     Also, a doped polysilicon control gate electrode 58 has been formed over the left size of the device overlying the left edge of the silicon oxide cap 48. Second gate oxide layer 56 preferably has a thickness from about 100 Å to about 150 Å. 
     Table I below lists experimental data which was recorded using the process of FIGS. 2A-2H. Table II below lists the data for the process of FIGS. 1A-1E. 
     
                       TABLE I______________________________________W.A.T. DATA SHEETPRODUCT: TM418     PROCESS: 05TW17S1LOT ID: A52531.5   DATE: 03/27/1997         BVOX.sub.-- NHACWAF    SITE   V             FTV/.6   RTV/.6ID     ID     I = -100 nA   V        V______________________________________1      -1     -23.00        7.500    -19.301      -2     -21.80        7.670    -20.501      -3     -23.80        7.930    -20.601      -4     -23.50        7.620    -20.301      -5     -21.50        7.720    -20.302      -1     -24.20        0.0000E + 00                                -18.002      -2     -23.70        7.790    -20.402      -3     -23.90        7.790    -20.302      -4     -24.20        0.0000E + 00                                -20.302      -5     -24.00        7.740    -20.20______________________________________ FTV = Forward Tunneling Voltage RTV = Reverse Tunneling Voltage BVOX.sub.-- NHAC = Breakdown Voltage OXide.sub.-- N(Ntype) High voltage ACtive device. WAF ID = Wafer Identification Site ID = Site Identification Specifications about FTV &lt; RTV about 7V &lt; -18.0 V BVOX.sub.-- NHAC about -23.00 V 
    
     
                                           TABLE II__________________________________________________________________________W.A.T. DATA SHEETPRODUCT: TM418    PROCESS: 05TW17S1LOT ID: A52531.5  DATE: 03/27/1997 BVOX.sub.-- NHACWAF   SITE V       FTV/.6 RTV/.6ID ID I = -100 nA         V      V__________________________________________________________________________ 6 -1 -19.80  7.390  -17.00 M/E 20&#34; HTO = 100Å 6 -2 -19.00  7.680  -17.60 6 -3 -19.80  7.890  -17.10 O/E 33&#34; 6 -4 -20.00  7.530  -17.30 6 -5 -19.90  7.590  -17.50 7 -1 -20.30  7.500  -19.90 7 -2 -19.90  7.660  -20.20 O/E 30&#34; 7 -3 -19.30  7.930  -20.10 7 -4 -19.50  7.650  -20.40 7 -5 -20.30  7.680  -19.80 8 -1 -20.70  7.630  -20.60 8 -2 -20.50  7.850  -20.70 O/E 25&#34; 8 -3 -21.10  8.060  -20.60 8 -4 -20.80  0.0000E + 00                -20.50 8 -5 -20.70  7.750  -20.60 9 -1 -21.00  9.250  -21.10 9 -2 -19.80  9.640  -21.20 O/E 15&#34; 9 -3 -20.10  9.730  -21.20 9 -4 -20.90  0.0000E + 00                -21.10 9 -5 -20.10  9.550  -21.2010 -1 -20.60  10.20  -21.2010 -2 20.20   10.50  -21.20 O/E 10&#34;10 -3 -21.30  10.80  -21.2010 -4 -20.20  10.20  -21.2010 -5 -21.20  10.60  -21.2011 -1 -22.60  11.00  -21.2011 -2 -22.20  11.00  -21.301i -3 -23.30  11.00  -21.30 O/E 5&#34;11 -4 -22.20  0.0000E + 00                -21.2011 -5 -22.20  11.00  -21.3012 -1 -23.20  11.00  -21.3012 -2 -24.90  11.00  -21.3012 -3 -23.00  11.00  -21.30 O/E 0&#34;12 -4 -22.80  0.4000E - 03                -21.2012 -5 -24.70  11.00  -21.3013 -1 -29.60  0.0000E + 00                -21.3013 -2 -29.80  11.00  -21.30 M/E 20&#34; HTO = 200Å13 -3 29.40   11.00  -21.30 M/E 20&#34; HTO = 200Å13 -4 -28.50  2.750  -21.30 O/E 0&#34;13 -5 -29.40  0.0000E + 00                -21.3014 -1 -23.10  11.00  -21.3014 -2 -25.70  11.00  -21.30 O/E 5&#34;14 -3 -24.50  11.00  -21.4014 -4 -24.20  11.00  -21.3014 -5 -23.50  11.00  -21.4015 -1 -25.50  0.0000E + 00                0.0000E + 0015 -2 -25.80  0.0000E + 00                -21.20 O/E 10&#34;15 -3 -26.10  0.0000E + 00                -21.2015 -4 -25.90  0.0000E + 00                0.0000E + 0015 -5 -25.80  0.0000E + 00                0.0000E + 0016 -1 -23.30  8.770  -21.0016 -2 -21.90  8.810  -21.00 O/E 20&#34;16 -3 -22.50  8.990  -21.0016 -4 -23.00  8.950  -21.1016 -5 -22.30  8.950  -21.1017 -1 -23.80  8.360  -18.0017 -2 -23.80  8.520  -18.00 O/E 30&#34;17 -3 -24.00  8.750  -18.4017 -4 -23.40  0.0000E + 00                -17.5017 -5 -24.10  0.0000E + 00                -17.7018 -1 -22.20  8.220  -15.0018 -2 -20.80  8.340  -15.30 O/E 35&#34;18 -3 -21.50  8.570  -14.9018 -4 -22.60  0.0000E + 00                -15.5018 -5 -21.10  0.0000E + 00                -15.1019 -1 -30.00  11.00  -21.30 M/E 40&#34; HTO = 200Å19 -2 0.0000E + 00         11.00  -21.3019 -3 -29.90  11.00  -21.30 O/E 0&#34;19 -4 -29.10  0.0000E + 00                -21.3019 -5 -29.90  11.00  -21.3020 -1 -22.70  9.240  -21.3020 -2 -23.70  9.690  -21.30 O/E 5&#34;20 -3 -22.70  9.900  -21.3020 -4 -23.50  9.670  -21.3020 -5 -22.20  0.0000E + 00                -21.3021 -1 -24.20  0.0000E + 00                -21.20 O/E 10&#34;21 -2 -24.40  9.440  -21.3021 -3 -25.30  9.350  -21.3021 -4 -24.20  0.0000E + 00                -21.2021 -5 -24.60  0.0000E - 00                -21.2022 -1 -21.90  8.440  -21.10 O/E 20&#34;22 -2 -20.80  8.650  -21.2022 -3 -21.06  8.980  -21.3022 -4 -21.50  0.0000E + 00                -21.2022 -5 -22.20  0.0000E + 00                -21.1023 -1 -22.50  8.280  -17.80 O/E 30&#34;23 -2 -22.50  8.560  -17.8023 -3 -23.00  8.710  -17.2023 -4 -22.30  0.0000E + 00                -17.5023 -5 -22.70  0.0000E + 00                -17.6024 -1 -21.20  8.120  15.10  O/E 35&#34;24 -2 20.00   8.300  -15.6024 -3 -21.30  8.480  -15.2024 -4 -20.80  8.270  -15.5024 -5 -20.50  0.0000E + 00                -15.10__________________________________________________________________________ 
    
     Summary 
     1. The stability of the process of FIGS. 2A-2H is better than the process of FIGS. 1A-1E because the etching process window (etching time) is longer than the original process. 
     2. The method of FIGS. 2A-2I controls the height and width of the &#34;L&#34; shape Si 3  N 4  spacer. 
     3. With the method of FIGS. 2A-2I loss of HTO oxide is easily controlled, i.e. HTO oxide loss is less than about 20 Å. 
     While this invention has been described in terms of the above specific embodiment(s), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims, i.e. that changes can be made in form and detail, without departing from the spirit and scope of the invention. Accordingly all such changes come within the purview of the present invention and the invention encompasses the subject matter of the claims which follow.