Abstract:
A packaging substrate includes an insulating layer, a wiring layer and a solder mask. The insulating layer and the solder mask being arranged on two opposite sides of the wiring layer. The insulating layer defines a via hole. The wiring layer covers the via hole. The wiring layer includes a pad area. Two sides of the pad area are respectively exposed outside from the solder mask and in the via hole.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a packaging substrate for mounting a chip and a method for manufacturing the packaging substrate. 
         [0003]    2. Description of Related Art 
         [0004]    Chip packages may include a packaging substrate and a chip. The printed circuit board (PCB) is configured to form a connecting pad. Most of the packaging substrates include a plurality of patterned electrically conductive layers, which make the packaging substrate thick. 
         [0005]    What is needed therefore is a packaging substrate, a method for manufacturing the same and a chip package having the packaging substrate to overcome the described limitations. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    Many aspects of the present embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. Moreover, in the drawings, all the views are schematic, and like reference numerals designate corresponding parts throughout the several views. 
           [0007]      FIG. 1  is a schematic view of a roll of flexible copper clad laminate according to an exemplary embodiment, the flexible copper clad laminate including a copper layer and an insulating layer. 
           [0008]      FIG. 2  is a schematic, cross-sectional view of part of the flexible copper clad laminate of  FIG. 1 . 
           [0009]      FIG. 3  shows a plurality of via holes to penetrate the insulating layer of  FIG. 2 . 
           [0010]      FIG. 4  shows a second dry film photoresist layer and a third dry film photoresist layer formed on the single-sided strip-shaped flexible copper clad laminate in  FIG. 3 . 
           [0011]      FIG. 5  shows a wiring layer obtained by patterning the copper layer of  FIG. 4 . 
           [0012]      FIG. 6  is a schematic view of a sheet obtained by cutting the patterned flexible copper clad laminate, the sheet having a plurality of substrate strips. 
           [0013]      FIG. 7  shows a solder mask formed on the sheet of  FIG. 6  to cover the entire surface except pad or finger areas defined at predetermined positions on the wiring layer. 
           [0014]      FIG. 8  shows a thin copper layer formed on the insulation layer of the sheet in  FIG. 7 . 
           [0015]      FIG. 9  shows a first dry film photoresist layer formed on the thin copper layer of  FIG. 7 . 
           [0016]      FIG. 10  shows a plating layer formed on the pad or finger areas in  FIG. 8 , the third dry film photoresist layer removed from the thin copper layer, and the thin copper layer removed from the insulating layer. 
           [0017]      FIG. 11  is a schematic view of a substrate strip with circuit board units obtained by stripping the sheet with plating layer of  FIG. 10 . 
           [0018]      FIG. 12  is a schematic view of a packaging substrate obtained by cutting the substrate trip of  FIG. 11 , the packaging substrate being the circuit board unit. 
           [0019]      FIG. 13  shows an electrically conductive material formed in each via hole of the packaging substrate in  FIG. 12  to obtain a packaging substrate with electrically conductive material. 
           [0020]      FIG. 14  shows a supporting board on the package substrate of  FIG. 13 . 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    A packaging substrate and a method for manufacturing the packaging substrate according to embodiments will be described with reference to the drawings. 
         [0022]    A method of manufacturing a packaging substrate according to an exemplary embodiment includes the steps as follows. 
         [0023]      FIGS. 1 and 2  show step  1 , a roll of flexible copper clad laminate  10   a  is provided. The flexible copper clad laminate  10   a  includes an insulating layer  11   a  and a copper layer  14   a.  The insulating layer  11  a includes a first surface  111   a  and a second surface  112   a  facing away from the first surface  111   a.  The copper layer  14   a  covers the first surface  111   a.  The insulating layer  11   a  may be made of flexible material, for example, Polyimide, Polyethylene Naphthalate, Polyethylene Terephthalate. In the present embodiment, the insulating layer  11   a  is Polyimide. The thickness of the insulating layer  11   a  is in a range from 15 micrometers to 250 micrometers, and preferably from 25 micrometers to 50 micrometers. The copper layer  14   a  may be a roll copper foil, an electrolytic foil, for example. The thickness of the copper layer  14   a  is in a range from about 12 micrometers to about 35 micrometers. 
         [0024]      FIG. 3  shows step  2 , in which a plurality of via holes  13  are defined in the copper clad laminate  10   a.  Each via hole  13  penetrates the insulating layer  11   a.  That is, each via hole  13  passes through the first surface  111   a  and the second surface  111   b.  The via holes  13  may be formed by a laser beam or a blanking die. In the present embodiment, the via holes  13  are formed by a laser beam, and a cross section of each via hole  13  taken in a plane parallel with the first surface  111   a  is round. In other embodiments, the cross section of each via hole  13  taken in a plane parallel with the first surface  111   a  may be square, or triangle, for example. 
         [0025]      FIGS. 4 and 5  shows steps  3 , in which the copper layer  14   a  is patterned to form a wiring layer  12 . In the present embodiment, the copper layer  14   a  is converted into the wiring layer  12  by an image transfer process and an etching process. The method for manufacturing the wiring layer  12  includes the following steps. 
         [0026]    First, the surfaces of the copper layer  14   a  and the insulating layer  11  a are processed by a surface etching process to remove contaminants, from the surfaces of the copper layer  14   a  and the insulating layer  11   a.  In addition, lightly etch the surface of the copper layer  14   a  to make the surface of the copper layer  14   a  rough, thereby improving a cohesion force between the copper layer  14   a  and a dry film photoresist layer (described below). Thus, bubbles and contaminants are prevented from being generated between the copper layer  14   a  and the dry film photoresist layer. In other embodiments, the surfaces of the copper layer  14   a  and the insulating layer  11  a may be processed by plasma treatment. 
         [0027]    Second, as  FIG. 4  shows, a second dry film photoresist layer  113  is laminated onto the copper layer  14   a,  and a third dry film photoresist layer  114  is laminated onto the second surface  112 . In other embodiments, the second surface  112  may be covered with a coverlay, an adhesive tape, for example. 
         [0028]    Third, as  FIG. 5  shows, the copper layer  14   a  is patterned to form the wiring layer  12  by a exposing process, a developing process, a etching process, and a striping process, thereby obtaining a roll of patterned flexible copper clad laminated  10   b.  In the present embodiment, the second dry film photoresist layer  113  is selectively exposed. The exposed second dry film photoresist layer  113  is developed to be converted into a patterned dry film photoresist layer, such that portions of the copper layer  14   a,  which will be removed, are exposed from the patterned dry film photoresist layer, and the other portions of the copper layer  14   a,  which will be converted into the a wiring layer  12 , are covered by the patterned dry film photoresist layer. The portions of the copper layer  14   a,  which will be removed, are etched by copper-etching solution to be removed from insulating layer  11   a,  thereby converting the other portions of the copper layer  14   a,  which is covered by the patterned dry film photoresist layer, into the a wiring layer  12 . The wiring layer  12  cover the via holes  13 . Striping means stripping the patterned dry film photoresist layer and the third dry film photoresist layer  114  off the wiring layer  12  and the second surface  112   a,  such that the a wiring layer  12  and the second surface  112  are exposed. In other embodiments, the copper layer  14   a  is converted into the wiring layer  12  by a wet film processing. In addition, after converting the copper layer  14   a  into the wiring layer  12 , there may be a step of forming a plurality of tooling holes (not shown) by a punching process. The tooling holes pass through the insulating layer  11   a  and the wiring layer  12 , and are configured for locating the circuit board in the following steps. 
         [0029]      FIGS. 5 and 6  shows steps  4 , in which the patterned flexible copper clad laminated  10   b  is cut from roll type into a plurality of sheets  10   c.  Each sheet  10   c  includes a plurality of substrate strip  10   d  without a solder mask. Each substrate strip  10   d  includes a plurality of via holes  13 . Wherein before the step of cutting the patterned flexible copper clad laminate  10   b,  the flexible copper clad laminate  10   a  is transferred to each adjoined process in a roll-to-roll manner. 
         [0030]      FIGS. 7  shows steps  5 , in which a solder mask  15  is formed on the wiring layer  12  of the sheet  10   c  to cover the entire surface of the wiring layer  12  except pad areas  123  or finger areas  121  defined at predetermined positions on the wiring layer  12 . In the present embodiments, each of pad areas  123  or fingers areas  123  spatially corresponds to a via hole  13 ; the finger areas  121  are located at an edge of the wiring layer  12 , and the pad areas  123  are located at a central area of the wiring layer  12 . 
         [0031]    In the present embodiment, the solder mask  15  is made of liquid photoimageable solder resist ink. The method for forming the solder mask  15  includes the following steps: first, printing the liquid photoimageable solder resist ink on the entire surface of the wiring layer  12 , selectively exposing the liquid photoimageable solder resist ink by a ultraviolet light to make first portions of the liquid photoimageable solder resist ink generate a cross-linking reaction, in which the first portions spatially correspond the pad areas  123  and finger areas  121 ; removing second portions of the liquid photoimageable solder resist ink which does not generate a cross-linking reaction, from the wiring layer  12  by a developing process; finally, thermal curing the retaining liquid photoimageable solder resist ink, thereby forming the solder mask  15 . There may be one finger area  121 , or any number of finger areas  121 . There may be one pad area  123 , or any number of pad areas  123 . For better understand, there is one finger area  121  shown in figures and there is one pad area  123  shown in figures. 
         [0032]    In other embodiments, the solder mask  15  may be made of a thermosetting ink. In such case, exposing and developing can be omitted, and the thermosetting ink is printed on the entire surface of the wiring layer  12  except pad areas  123  or finger areas  121  defined at predetermined positions on the wiring layer  12  using a patterned screen. Then, the thermosetting ink is cured to obtain the solder mask  15 . 
         [0033]      FIGS. 8 to 10  show step  6 , in which a plating layer  122  is formed on the finger area  121  by plating, a plating layer  124  is formed on the pad area  123  by plating. Thus, a sheet  10   e  with the plating layers (i.e. a plated sheet) is obtained. The plating layer  122  includes gold. The plating layer  124  includes nickel and gold. The plating layer  122  and the plating layer  124  are configured for protecting the finger area  121  and the pad area  123  from being oxidized, and the plating layer  122  and the plating layer  124  may be formed by the following steps. 
         [0034]    First,  FIG. 8  shows that a thin copper layer  18  is formed on the second surface  112 , the inner surface of the via holes  13 , and the surface of finger area  121  exposed at the side of the second surface  112 , and the surface of the pad area  122  exposed at the side of the second surface  112  by sputtering. In other embodiments, the thin copper layer  18  may be formed by an electro-less copper plating. 
         [0035]    Second,  FIG. 9  shows that a first dry film photoresist layer  115  is laminated on the thin copper layer  18 , and the first dry film photoresist layer  115  is entirely exposed to make the first dry film photoresist generate cross-linking reaction. The first dry film photoresist layer  115  is configured for protecting the thin copper layer  18  from being etched and contaminated by gold plating solution, and for preventing the thin copper layer  18  from being plated with gold. The reason of wholly exposing the first dry film photoresist layer  115  is that the exposed first dry film photoresist layer  115  can substantially resist the gold plating solution. In alternative embodiments, if portions of the thin copper layer  18  need to be plated with gold, the first dry film photoresist layer  115  may be selectively exposed and developed. In further alternative embodiments, the thin copper layer  18  may be covered with an anti-plating film or an anti-plating adhesive tape to replace the first dry film photoresist layer  115 . In still further alternative embodiments, the thin copper layer  18  may be printed with a peelable solder mask ink to replace the first dry film photoresist layer  115 . 
         [0036]    Finally,  FIG. 10  shows that the plating layer  122  and the plating layer  124  are respectively formed on the finger area  121  and the pad area  123  by electroplating, and the exposed first dry film photoresist layer  115  and the thin copper layer  18  are removed from the insulating layer  11 . In other embodiments, silver layer or tin layer may be formed on the finger area  121  and the pad area  123  to replace the plating layer  122  and the plating layer  124 . 
         [0037]      FIG. 11  shows steps  6 , in which the sheet  10   e  with plating layer  122  and the plating layer  124  is stripped into a plurality of substrate strips  10   f  with plating layer  122  and the plating layer  124  and solder mask  15 . Each substrate strip  10   f  includes a plurality of circuit board units  10   g.  Each circuit board unit  10   g  includes at least one via hole  13 . In the present embodiment, each circuit board unit  10   g  includes at least two via hole  13 . 
         [0038]      FIG. 12  shows steps  7 , in which the substrate strip  10   f  is cut into a plurality of separate circuit board units  10   g.    
         [0039]      FIG. 13  shows steps  8 , in which each via hole  13  in the circuit board unit  10   g  is filled with an electrically conductive material  131 , thereby obtaining a packaging substrate  20 . The electrically conductive material  131  may be made of copper, silver, for example, and may be formed by sputtering or printing. The electrically conductive material  131  in the via hole  13 , which exposes the finger area  121 , is securely connected to the finger area  121 , and the electrically conductive material  131  in the via hole  13 , which exposes the pad area  123 , is securely connected to the pad area  123 . In the present embodiment, each via hole  13  is fully filled with the electrically conductive material  131 , and the surface of the electrically conductive material  131 , which is adjacent to the second surface  112 , is coplanar with the second surface  112 . In alternative embodiments, the via hole  13  exposing the finger area  121  may be not filled with an electrically conductive material  131 . In further alternative embodiments, the via hole  13  exposing the pad area  123  may be not filled with an electrically conductive material  131 . In still further alternative embodiments, all of the via holes  13  may not be filled with the electrically conductive material  131 . In such case, each circuit board units  10   e  can be a packaging substrate. In also still further alternative embodiments, each circuit board units  10   e  may includes a plurality of packaging substrates. In such case, the circuit board unit  10   e  should be cut to obtain separate packaging substrates. 
         [0040]      FIG. 14  shows step  9 , in which a supporting substrate  19  is formed on the second surface  112  of the insulating layer  11 , thereby obtaining a packaging substrate  21  with a backing. The supporting substrate  19  is configured for supporting the packaging substrate  20 . 
         [0041]    The supporting substrate  19  includes a supporting base  191  and an adhesive layer  192  on the supporting base  191 . The supporting base  191  is adhered to the second surface  112  by the adhesive layer  192 . The supporting base  191  may be made of epoxy, phenolic resin, or metal. 
         [0042]    In the present embodiment, the flexible copper clad laminate  10   a  is processed in a roll-to-roll manner to manufacture the patterned flexible copper clad laminate  10   a,  and the patterned flexible copper clad laminate  10   a  is separated into a plurality of sheets  10   c.  Then, each sheets  10   c  is covered with a solder mask  15 , and the plating layer  122  and the plating layer  124  are formed on each sheet  10   c,  thereby obtaining the sheet  10   c  with the plating layer  122  and the plating layer  124 . The sheet  10   c  is stripped into a plurality of substrate strips  10   d  with circuit board units  10   e.  Each substrate strip  10   d  is cut into to obtain separate circuit board units  10   e.  Each circuit board unit  10   e  can be a packaging substrate. The efficiency of manufacturing the packaging substrate is thus improved. 
         [0043]    The packaging substrate  20  includes the insulating layer  11 , the wiring layer  12 , and the solder mask  15 . The wiring layer  12  includes a finger area  121  and a pad area  123 . 
         [0044]    The insulating layer  11  includes the first surface  111  and the second surface  112 . Two via holes  13  are defined in the insulating layer  11 , and passes through the first surface  111  and the second surface  112 . One via hole  13  exposes the finger area  121  at the side of the second surface  112 , and the other via hole  13  exposes the pad area  123  at the side of the second surface  112 . Each via hole  13  is filled with the electrically conductive material  131 . The electrically conductive material  131  in the via hole  13  exposing the finger area  121  is securely connected to the finger area  121 , and the electrically conductive material  131  in the via hole  13  exposing the pad area  123  is securely connected to the pad area  123 . In the present embodiment, the via hole  13  is fully filled with the electrically conductive material  131 , and the surface of the electrically conductive material  131 , which is adjacent to the second surface  112 , is coplanar with the second surface  112 . 
         [0045]    The solder mask  15  covers the entire surface of the wiring layer  12  except pad area  123  or finger area  121  defined at predetermined positions on the wiring layer  12 . The finger area  121  is located at the edge of the wiring layer  12 , and the plating layer  122  is formed on the finger area  121 . The plating layer  122  is electrically connected to the finger  121 . The pad area  123  is located at the central area of the wiring layer  12 , and the plating layer  124  is formed on the pad area  123 . The plating layer  124  is electrically connected to the pad area  123 . 
         [0046]    In other embodiments, there may be two, three or more via holes  13 ; there may be two, three, or more fingers  121 ; and there may be two, three, or more pads  123 . The number of the finger area  121  and the pad area  123  is equal to the number of the via holes  13 ; as such each of the finger area  121  and the pad area  123  spatially correspond to an via hole  13 , respectively. 
         [0047]    In other embodiments, the supporting substrate  19  may be formed on the second surface  112  to obtaining the packaging substrate  21  with a backing. 
         [0048]    The insulation material of the packaging substrate  20  and the packaging substrate  21  with a backing is a flexible material. In addition, the wiring layer  12  is a single layer structure, and the packaging substrate  20  can thus be thinner. 
         [0049]    While certain embodiments have been described and exemplified above, various other embodiments will be apparent from the foregoing disclosure to those skilled in the art. The disclosure is not limited to the particular embodiments described and exemplified but is capable of considerable variation and modification without departure from the scope and spirit of the appended claims.