Abstract:
A switch branch that improves voltage uniformity across a series stack of an n-number of transistors is disclosed. A first one of the n-number of transistors is coupled to an input terminal, and an nth one of the n-number of transistors is coupled to an output terminal, where n is a positive integer greater than one. Predetermined parasitic capacitances associated with each of the n-number of transistors are adjustable with respect to capacitance value by predetermined amounts by dimensioning and arranging at least one metal layer element in proximity to the series stack of the n-number of transistors. Capacitance values for the predetermined parasitic capacitances are selected such that a voltage across the series stack of the n-number of transistors is uniformly distributed. In this way, the n-number of transistors can be reduced without risking a transistor breakdown within the series stack of the n-number of transistors.

Description:
RELATED APPLICATIONS 
     This application claims the benefit of provisional patent application Ser. No. 61/371,809, filed Aug. 9, 2010, the disclosure of which is hereby incorporated herein by reference in its entirety. 
    
    
     FIELD OF THE DISCLOSURE 
     The present disclosure relates to a radio frequency (RF) switch used for wireless communication, and in particular to providing voltage equalization for a series stack of transistors making up a switch branch of the RF switch. 
     BACKGROUND 
     High power radio frequency (RF) switches typically include at least one switch branch made up of a series stack of transistors that distribute a relatively high RF voltage to prevent transistor breakdown within the series stack of transistors. However, parasitic capacitances from the series stack of transistors to ground or to a wafer substrate create non-uniformities in the voltage distribution while the at least one switch branch is in an off mode and blocking an RF signal. As a result, more transistors must be included in the series stack of transistors in order to withstand the relatively high RF voltage. Adding more transistors to the series stack of transistors increases the area taken up by the at least one switch branch. Moreover, these additional transistors increase an insertion loss for the at least one switch branch made up of the series stack of transistors. Thus, there is a need for a switch branch that more uniformly distributes a relatively high RF voltage across the series stack of transistors so that the number of transistors making up the series stack of transistors can be reduced without risking a transistor breakdown within the series stack of transistors. 
     SUMMARY 
     The present disclosure provides a switch branch that more uniformly distributes a relatively high RF voltage across a series stack of transistors so that the number of transistors making up the series stack of transistors can be reduced without risking a transistor breakdown within the series stack of transistors. In particular, the present disclosure provides a switch branch that includes an input terminal, an output terminal, and a series stack of an n-number of transistors, wherein a first one of the n-number of transistors is coupled to the input terminal, and an nth one of the n-number of transistors is coupled to the output terminal, where n is a positive integer greater than one. Parasitic capacitances are associated with each of the n-number of transistors. At least one metal layer element is dimensioned and arranged in proximity to the series stack of the n-number of transistors to modify capacitance values of predetermined ones of the parasitic capacitances by predetermined amounts. An iterative method incorporating a computer simulation of operational conditions for the switch branch is provided to predetermine capacitance values for the predetermined ones of the parasitic capacitances needed to more uniformly distribute the relatively high RF voltage to be withstood by the switch branch. 
     Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
       The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
         FIG. 1  is a circuit diagram of a prior art switch branch having a non-uniform distribution of voltage. 
         FIG. 2  is a circuit diagram representing an off-state circuit model of the prior art switch branch of  FIG. 1 . 
         FIG. 3  is a circuit diagram of the prior art switch branch of  FIG. 1  including traditional capacitor compensation for improving voltage distribution. 
         FIG. 4  is a cross-section of a series stack of transistors having first and second metal parallel connections between parallel metal stripes. 
         FIG. 5  is a cross-section of the series stack of transistors having first and second metal parallel connections between only selected parallel metal stripes. 
         FIG. 6A  is a cross-section of the series stack of transistors having a continuous metal stripe within a second metal layer that is separated from the first metal layer by a distance Z. 
         FIG. 6B  is a top view of the continuous metal stripe within the second metal layer of  FIG. 6A . 
         FIG. 7  is a cross-section of the series stack of transistors having a second metal layer with a pattern of metal stripes that is not coupled to the first metal layer. 
         FIG. 8  is a cross-section of the series stack of transistors having a second metal layer with a pattern of metal stripes that is coupled to the first metal layer in an alternating fashion. 
         FIG. 9  is a circuit diagram of a switch branch that is usable to test the effectiveness of the metal stripe layouts of  FIGS. 4 through 8  in uniformly distributing a voltage across the series stack of transistors. 
         FIG. 10  is a table that lists capacitance values for the total drain to source capacitance for each of the transistors of  FIG. 9 . 
         FIG. 11  depicts results of a simulation for the switch branch of  FIG. 9  without application of the capacitance values of the table of  FIG. 10 . 
         FIG. 12  depicts results of a simulation for the switch branch of  FIG. 9  with the application of the capacitance values of the table of  FIG. 10 . 
         FIG. 13  is a table that provides the first metal layer and second metal layer metal stripe widths X for a metal stripe layout like that depicted in  FIG. 5 . 
         FIG. 14  is a block diagram of a mobile terminal that includes a parasitic capacitance adjusted switch branch that is in accordance with the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
       FIG. 1  is a circuit diagram of a prior art switch branch  10  having a non-uniform distribution of voltage while the switch branch  10  is in an off-mode blocking a signal transmission between a radio frequency (RF) input RF IN  and an RF output RF OUT . The switch branch  10  is made up of a series stack of transistors MS 1 , MS 2 , MS 3 , and MS 4 , each of which is a field effect transistor (FET). Drain to source voltages V 1 , V 2 , V 3 , and V 4  across the transistors MS 1 , MS 2 , MS 3 , and MS 4  are not uniformly distributed in that the voltage values are different from one another. Therefore, one of the transistors MS 1  through MS 4  will experience a minimum drain to source voltage, while another one of the transistors MS 1  through MS 4  will experience a maximum drain to source voltage. 
       FIG. 2  is a circuit diagram representing an off-state circuit model  12  of the prior art switch branch  10  of  FIG. 1 . In an off-state, the transistors MS 1 , MS 2 , MS 3 , and MS 4  can be represented by parasitic capacitors CMS 1 , CMS 2 , CMS 3 , and CMS 4 , respectively. Parasitic shunt capacitance CSH represents the value for the parasitic capacitances between the drain and source of each of the transistors MS 1  through MS 4  and ground or a wafer substrate onto which the transistors MS 1  through MS 4  are fabricated. 
       FIG. 3  is a circuit diagram of the prior art switch branch  10  further including a traditional capacitor compensation technique for improving the voltage distribution across the switch branch  10 . Compensation capacitors CX 1 , CX 2 , CX 3 , and CX 4  are coupled directly to each respective transistor MS 1 , MS 2 , MS 3 , and MS 4 . Each of the capacitors is sized to provide enough additional capacitance to the parasitic capacitors CMS 1  through CMS 4  ( FIG. 2 ) so that the drain to source voltages V 1  through V 4  are more equal to one another, to provide a more uniform voltage distribution across the switch branch  10 . However, this traditional capacitor compensation technique is less than ideal because the compensation capacitors undesirably increase the area of the switch branch  10 . 
     Another traditional technique used to reduce the drain to source voltage of any one of the transistors MS 1  through MS 4  is to include additional transistors (not shown) in the series stack of transistors making up the switch branch  10 . In this way, individual ones of the transistors MS 1  through MS 4  and the additional transistors are ensured not to experience enough drain to source voltage to break down. However, including additional transistors in the series stack of transistors making up the switch branch  10  is not ideal because the additional transistors increase the area taken up by the switch branch  10 . Moreover, these additional transistors increase an insertion loss for the switch branch  10 . 
     Beginning with  FIG. 4 , the present disclosure provides structures and methods for new integrated circuit layout practices that improve the uniformity of voltage distribution across a series stack of transistors  14 . As shown in  FIG. 4 , the series stack of transistors  14  makes up a first embodiment of an improved switch branch  16 . The series stack of transistors  14  is typically formed in an active device layer  18  by a process of wafer bonding followed by cleaving and polishing. The active device layer is on top of a buried oxide layer  20  that insulates the active device layer  18  from a silicon handle wafer  22 . 
     A first FET  24 , a second FET  26 , a third FET  28 , and a fourth FET  30  make up the series stack of transistors  14 . A first contact  32  is coupled to the drain of the first FET  24 . The first contact  32  is usable as an input or an output for the series stack of transistors  14 . A second contact  34  is coupled to the source of the first FET  24 , and to the drain of the second FET  26 . A third contact  36  is coupled to the source of the second FET  26 , and to the drain of the third FET  28 . A fourth contact  38  is coupled to the source of the third FET  28 , and to the drain of the fourth FET  30 . A fifth contact  40  is coupled to the source of the fourth FET  30 . The fifth contact  40  is usable as an input or as an output for the series stack of transistors  14 . A first metal layer  42  includes a metal stripe  44  coupled to the first contact  32 , a metal stripe  46  coupled to the second contact  34 , a metal stripe  48  coupled to the third contact  36 , a metal stripe  50  coupled to the fourth contact  38 , and a metal stripe  52  coupled to the fifth contact  40 . 
     In modern silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) processes, a gate pitch for the FETS  24  through  30  is 1 μm or less. Therefore, a significant portion of a total drain to source capacitance (Cds) is attributable to a parasitic capacitor coupled between adjacent metal stripes, such as the metal stripe  44  and the metal stripe  46 . In  FIG. 4 , a parasitic capacitor C 1   a  is shown symbolically coupled between the metal stripe  44  and the metal stripe  46 . A parasitic capacitor C 2   a  is shown symbolically coupled between the metal stripe  46  and the metal stripe  48 . Similarly, a parasitic capacitor C 3   a  is shown symbolically coupled between the metal stripe  48  and the metal stripe  50 . Likewise, a parasitic capacitor C 4   a  is shown symbolically coupled between the metal stripe  50  and the metal stripe  52 . 
     A second metal layer  54  includes metal stripes  56 ,  58 ,  60 ,  62 , and  64 . The metal stripe  56  is coupled to the metal stripe  44  through a via  66 , and the metal stripe  58  is coupled to the metal stripe  46  through a via  68 . The metal stripe  60  is coupled to the metal strip  48  through a via  70 . The metal stripe  62  is coupled to the metal stripe  50  through a via  72 , and the metal stripe  64  is coupled to the metal stripe  52  through a via  74 . A parasitic capacitor C 1   b  is shown symbolically coupled between the metal stripe  56  and the metal stripe  58 . A parasitic capacitor C 2   b  is shown symbolically coupled between the metal stripe  58  and the metal stripe  60 . Similarly, a parasitic capacitor C 3   b  is shown symbolically coupled between the metal stripe  60  and the metal stripe  62 . Likewise, a parasitic capacitor C 4   b  is shown symbolically coupled between the metal stripe  62  and the metal stripe  64 . 
     The width of each of the metal stripes  44  through  64  is represented by a variable X, and the space between adjacent ones of the metal stripes  44  through  64  is represented by a variable Y. If the variable X is increased for an individual one of the metal stripes  44  through  64 , the variable Y for the space separating the individual one of the metal stripes  44  through  64  from at least one of the adjacent ones of the metal stripes  44  through  64  will decrease. As a result, the parasitic capacitance between the individual one of the metal stripes  44  through  64  and at least one of the adjacent ones of the metal stripes  44  through  64  will increase. For example, if the width of the metal stripe  58  is uniformly increased, the space between the metal stripe  58  and the adjacent metal stripes  56  and  60  will decrease. As a result, the parasitic capacitors C 1   b  and C 2   b  respectively will increase in capacitance. In a contrasting example, if the width of the metal stripe  62  is reduced, the space between the adjacent metal stripes  60  and  64  will increase. As a result, the parasitic capacitors C 3   b  and C 4   b  will decrease in capacitance. 
     Standard metallization design rules of a CMOS technology will limit the minimum width of each of the metal stripes  44  through  64 , as well as limit the minimum spacing between adjacent ones of the metal stripes  44  through  64 . For example, a CMOS technology with 0.25 μm minimum feature size will allow a ratio of a maximum metal capacitance Cmax to a minimum metal capacitance Cmin to be on the order of two to four without any change in gate pitch for the FETs  24  through  30 . Thus, the total Cds for individual ones of the FETs  24  through  30  can be increased by as much as 50% to 100% from a minimum total Cds, wherein the width of the metal stripes  44  through  64  is minimized. 
     Adjustments to the capacitance values of parasitic capacitors represented by C 1   a  through C 4   b  can be made by varying the width of the metal stripes  44  through  64 . Preferably, the width in the metal stripes  44  through  64  is reduced gradually along the series stack of transistors  14 . In this way, the values of the parasitic capacitors represented by C 1   a  through C 4   b  are decreased from higher to lower values of capacitance along the series stack of transistors  14 . As such, the drain to source voltages (Vds) for each of the FETs  24  through  30  is more uniformly distributed. 
       FIG. 5  is a cross-section of the series stack of transistors  14  having first and second metal parallel connections between only the metal stripes  44  through  60 , which make up a switch branch  76 . The metal stripe  62  ( FIG. 4 ) and the metal stripe  64  ( FIG. 4 ) are absent from the switch branch  76 . As a result, the parasitic capacitances C 3   b  and C 4   b  shown symbolically in  FIG. 4  are absent from the switch branch  76 . The absence of the metal stripe  62  and the metal stripe  64  from the switch branch  76  allows for an even greater range of parasitic capacitances represented symbolically as C 1   b  and C 2   b . It is to be understood that the embodiments of the switch branch  16  ( FIG. 4 ) and the switch branch  76  may include a smaller or greater number of FETs making up the series stack of transistors  14 . Moreover, additional metal layers beyond the first metal layer  42  and the second metal layer  54  may be used to adjust the value of the total Cds for each transistor making up the series stack of transistors  14 . 
       FIG. 6A  is a cross-section of the series stack of transistors  14  having a second metal layer  78  with a continuous metal stripe  80  that is separated from the first metal layer  42  by a distance Z. The series stack of transistors  14  together with the first metal layer  42  and second metal layer  78  comprises a switch branch  82 . In the particular case of the switch branch  82 , the continuous metal stripe  80  is not directly coupled to the first metal layer  42 . Furthermore, the second metal layer  78  is not necessarily associated with the switch branch  82  for purposes other than to adjust the capacitance values of parasitic capacitances shown symbolically as C 1   c , C 2   c , and C 3   c.    
     The continuous metal stripe  80  may be an element of an adjacent circuitry (not shown), or the continuous metal stripe  80  may be added to the switch branch  82  for the sole purpose of adjusting the parasitic capacitances represented by C 1   c , C 2   c , and C 3   c . Preferably, the distance Z separating the continuous metal stripe  80  is less than about 5 μm so that the parasitic capacitances represented by C 1   c , C 2   c , and C 3   c  are adjusted to more uniformly distribute the Vds for each of the FETs  24  through  30 . 
     As shown in  FIG. 6B , the metal stripe  80  has lateral dimensions of a length L and a width W that can be adjusted to further adjust the capacitance values of the parasitic capacitances shown symbolically as C 1   c , C 2   c , and C 3   c.    
     For example, the width W can be tapered to incrementally decrease the capacitance values of the parasitic capacitances C 2   c  and C 3   c  as the length L of the continuous metal stripe  80  extends along at least a portion of the series stack of transistors  14 . 
       FIG. 7  is a cross-section of the series stack of transistors  14  having a second metal layer  84  with a pattern of metal stripes  86 ,  88 , and  90  that are located above and separated from the first metal layer  42  by the distance Z. The series stack of transistors  14 , together with the first metal layer  42  and second metal layer  84 , comprises a switch branch  92 . The metal stripe  86  is centered between and above the metal stripes  44  and  46  of the first metal layer  42 . A parasitic capacitance symbolically represented by the capacitor C 1   d  is formed between the metal stripe  44  and the metal stripe  46 . Likewise, a parasitic capacitance symbolically represented by the capacitor C 2   d  is formed between the metal stripe  46  and the metal stripe  86 . The capacitance values for the capacitor C 1   d  and the capacitor C 2   d  are adjusted by altering the width X of the metal stripe  86  and the separation distance Z. Parasitic capacitances symbolically represented by the capacitor C 3   d  and the capacitor C 4   d  are adjusted by altering the width of the metal stripe  88  and/or changing the separation distance Z. Similarly, the parasitic capacitances symbolically represented by the capacitor C 5   d  and the capacitor C 6   d  are adjusted by altering the width of the metal stripe  90  and/or changing the separation distance Z. 
     Notice, that as shown in  FIG. 7 , the combined capacitance values for the capacitor C 1   d  and the capacitor C 2   d  will be larger than the combined capacitance values for the capacitor C 5   d  and the capacitor C 6   d . The combined capacitance values for the capacitor C 3   d  and the capacitor C 4   d  will be less than the combined capacitance values for the capacitor C 1   d  and the capacitor C 2   d  and greater than the combined capacitance values for the capacitor C 5   d  and the capacitor C 6   d . In this way, the values of the parasitic capacitances represented by C 1   d  through C 6   d  are decreased from higher to lower values of capacitance along the series stack of transistors  14 . As such, the Vds for each of the FETs  24  through  30  becomes more uniformly distributed. 
     In the particular case of the switch branch  92 , the metal stripes  86 ,  88 , and  90  are not directly coupled to the first metal layer  42 . Furthermore, the second metal layer  84  is not necessarily associated with the switch branch  92  for purposes other than to adjust the capacitance values of parasitic capacitances shown symbolically as the capacitors C 1   d  through C 6   d.    
       FIG. 8  is a cross-section of the series stack of transistors  14  having a second metal layer  94  with a pattern of metal stripes  96 ,  98 , and  100  that are coupled to the first metal layer  42  in an alternating fashion. The series stack of transistors  14  together with the first metal layer  42  and the second metal layer  94  makes up a switch branch  102 . The metal stripe  96  is directly coupled to the metal stripe  44  through the via  66 . The width X of the metal stripe  96  is modified to adjust a parasitic capacitance formed between the metal stripe  96  and the metal stripe  46  and is represented symbolically by a capacitor C 1   e . The metal stripe  98  is directly coupled to the metal stripe  48  through the via  70 . The width X of the metal stripe  98  is modified to adjust a parasitic capacitance formed between the metal stripe  46  and the metal stripe  98 , and is represented symbolically by a capacitor C 2   e . The width X of the metal stripe  98  is also modified to adjust a parasitic capacitance formed between the metal stripe  50  and the metal stripe  98 , and is represented symbolically by a capacitor C 3   e . The metal stripe  100  is directly coupled to the metal stripe  52  through the via  74 . The width X of the metal stripe  100  is modified to adjust a parasitic capacitance formed between the metal stripe  50  and the metal stripe  100 , and is represented symbolically by a capacitor C 4   e . The Vds for each of the FETs  24  through  30  is made more uniformly distributed by adjusting the parasitic capacitances represented symbolically by the capacitors C 1   e  through C 4   e.    
       FIG. 9  is a circuit diagram of a switch branch  104  that is usable to test the effectiveness of the metal stripe layouts of  FIGS. 4 through 8  in uniformly distributing voltages across a series stack of transistors, such as FETs M 1  through an nth FET MN. An RF IN  is coupled to the drain of the FET M 1 , whereas an RF OUT  is coupled to the source of MN. The total drain to source capacitance for each of the FETs M 1  through MN is represented symbolically by the capacitors C 1  through C 13 .  FIG. 10  is a table of capacitance values for the capacitors C 1  through C 13  for each of the transistors M 1  through MN of  FIG. 9 . Preferred values for the parasitic capacitances for the various metal stripe layouts depicted in  FIGS. 4 through 8  can be derived from the table of capacitance values listed in  FIG. 10 . Further still, a preferred width X and or separation distance Z for each of the metal stripes depicted in  FIGS. 4 through 8  can be derived from the preferred parasitic capacitance values. 
       FIG. 11  is a one-dimensional graph depicting normalized maximum AC voltages (VM 1  through VMN) from drain to source for each of the FETs M 1  through MN without including the preferred capacitance values for the capacitors C 1  through C 13 . For example, the voltage VM 1  represents the normalized maximum voltage across the FET M 1 . A normalized voltage value of 100 indicates an expected maximum AC voltage for uniform (i.e., equal) voltages across each of the FETs M 1  through MN. Notice that due to no adjustments being made to the parasitic capacitances, the voltages across each of the FETs M 1  through M 3  ( FIG. 9 ) near the RF IN  range as much as 85% higher than uniform voltages for the FETs M 1  through MN. In contrast, the FETs M 12  through MN ( FIG. 9 ) near the RF OUT  range as much as 25% lower than uniform voltages for the FETs M 1  through MN. 
       FIG. 12  is a one-dimensional graph depicting VM 1  through VMN from drain to source for each of the FETs M 1  through MN, wherein the preferred capacitance values for the capacitors C 1  through C 13  are included. Notice that with appropriate adjustments to the parasitic capacitances, the voltages across each of the FETs M 1  through M 3  ( FIG. 9 ) near the RF IN  only range about 4% higher than exactly uniform voltages for the FETs M 1  through MN. Moreover, the FETs M 12  through MN ( FIG. 9 ) near the RF OUT  only range about 2% lower than exactly uniform voltages for the FETs M 1  through MN. Therefore, the metal stripe layouts of  FIGS. 4 through 8  greatly improve the uniformity of voltages from drain to source for each of the FETs M 1  through MN.  FIG. 13  is a table that provides the first metal layer and second metal layer metal stripe widths X for a metal stripe layout similar to that depicted in  FIG. 5 . 
     The switch branch  104  of the present disclosure is preferably incorporated in a mobile terminal  106 , such as a mobile telephone, personal digital assistant (PDA), personal computer, or the like. The basic architecture of the mobile terminal  106  is represented in  FIG. 14 , and may include a receiver front end  108 , an RF transmitter section  110 , an antenna  112 , a transmit/receive (T/R) switch  114  that includes one or more of the switch branch  104 , a baseband processor  116 , a control system  118 , a frequency synthesizer  120 , and an interface  122 . 
     The receiver front end  108  receives information-bearing RF signals from one or more remote transmitters provided by a base station (not shown). A low noise amplifier  124  amplifies the RF signal. A filter circuit  126  minimizes broadband interference in the RF signal, while a downconverter  128  downconverts the filtered, received RF signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams. The receiver front end  108  typically uses one or more mixing frequencies generated by the frequency synthesizer  120 . 
     The baseband processor  116  processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. As such, the baseband processor  116  is generally implemented in one or more digital signal processors (DSPs). 
     On the transmit side, the baseband processor  116  receives digitized data from the control system  118 , which it encodes for transmission. The encoded data is output to the radio frequency transmitter section  110 , where it is used by a modulator  130  to modulate a carrier signal that is at a desired transmit frequency. Power amplifier (PA) circuitry  132  amplifies the modulated carrier signal to a level appropriate for transmission from the antenna  112 . In an on-state, the switch branch  104  transfers signal power to the antenna  112 . In an off-state, the switch branch  104  blocks RF signals. The PA circuitry  132  provides gain for the signal to be transmitted under control of power control circuitry  134 , which is preferably controlled by the control system  118  using an adjustable power control signal (V RAMP ). Further still, a directional coupler  136  samples output power from the PA circuitry  132  and provides a small sample of the output power to the RF detector  138 , which in turn provides the DETECTOR OUT signal to the power control circuitry  134 . 
     In response to the RF detector  138  providing the DETECTOR OUT signal to the power control circuitry  134 , the bias for the PA circuitry  132  is adjusted to maintain a desired output power under varying conditions, such as decreasing battery voltage and/or fluctuating voltage standing wave ratio (VSWR), etc. The control system  118  may also provide a transmit enable signal (TX ENABLE) to effectively enable the PA circuitry  132  during periods of transmission. 
     A user may interact with the mobile terminal  106  via the interface  122 , which may include interface circuitry  140  associated with a microphone  142 , a speaker  144 , a keypad  146 , and a display  148 . The interface circuitry  140  typically includes analog-to-digital converters, digital-to-analog converters, amplifiers, and the like. Additionally, the interface circuitry  140  may include a voice encoder/decoder, in which case it may communicate directly with the baseband processor  116 . 
     The microphone  142  will typically convert audio input, such as the user&#39;s voice, into an electrical signal, which is then digitized and passed directly or indirectly to the baseband processor  116 . Audio information encoded in the received signal is recovered by the baseband processor  116  and converted into an analog signal suitable for driving the speaker  144  and the interface circuitry  140 . The keypad  146  and the display  148  enable the user to interact with the mobile terminal  106 , inputting numbers to be dialed, address book information, or the like, as well as monitoring call progress information. 
     Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.