Abstract:
We describe and claim an apparatus and method for testing a memory device. The apparatus includes a test signal path to provide a test signal to a memory cell array responsive to an address generating command, the test signal to access a memory cell within the memory cell array, a failure address path to generate a failure address responsive to the address generating command, and a failure discriminator to determine a result responsive to the access, the result to indicate whether the memory cell is faulty, and to store the result according to the failure address.

Description:
REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority from Korean Patent Application No. 2004-36627 filed on May 22, 2004, which we incorporate by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to an apparatus and a method for testing a memory device.  
         [0004]     2. Description of the Related Art  
         [0005]     A typical memory device includes a plurality of memory cells, each memory cell to store data. To access the data stored in a memory cell, the memory device receives an address of the memory cell, and provides the stored data corresponding to the address after a time delay, or latency. The duration of the latency may be controlled by a mode register set (MRS).  
         [0006]     An electric die sorting (EDS) process may be used to test memory cells of the memory device. When a faulty cell is found during the EDS process, a redundancy algorithm is applied to the memory device so that the faulty cell is replaced with a redundancy cell. The redundancy algorithm is capable of recognizing the address of the faulty cell and replacing the memory cell located at the address with the redundancy cell. Faulty cells are typically replaced by cutting or maintaining a fuse. To correctly test faulty cells during the EDS process the address of the faulty cell should be correctly recognized.  
         [0007]      FIG. 1  is a block diagram illustrating a conventional memory test device. Referring to  FIG. 1 , the memory test device includes an address generator  100 , a data generator  110 , a timing generator  122 , and a failure discriminator  120 . The address generator  100  receives an address generating command from a pattern generator (not shown). The address generator  100  includes a register  102 , an Arithmetic and Logic Unit/Multiplexer (ALU/MUX)  104  and an address counter  106  to generate an address of a memory cell to be tested. The address counter  106  provides the address to the data generator  110 .  
         [0008]     The data generator  110  generates data to be written to the memory device under test (DUT)  124  according to the address and provides the data and address to an address/data bus  115 . The data generator  110  includes a memory data generator  112  and an address scrambler  114 . The memory data generator  112  generates the data to be written into the DUT  124 . The address scrambler  114  may be used in some testing modes to replace the address with another address (not shown) provided external to the memory test device, and the address or the replaced address to the address/data bus  115 .  
         [0009]     Timing generator  122  receives the address and optionally the data from the data generator  110 , and operation commands for controlling the operation of the DUT  124 , over the address/data bus  115 . The timing generator  122  provides the address and command(s) to the DUT  124 , causing the DUT  124  to provide data stored in a memory cell corresponding to the address to the failure discriminator  120 .  
         [0010]     The failure discriminator  120  compares the data from the DUT  124  with an expected value and stores a comparison result for failure analysis and the redundancy algorithm. The comparison result indicates whether a memory cell of the DUT  124  is faulty. The failure discriminator  120  includes a comparator  126  and a failure memory  128 .  
         [0011]     The comparator  126  receives and compares the data from the DUT  124  and the expected value, and stores the result of the comparison in the failure memory  128  according to the address from the data generator  110  carried on the address/data bus  115 . However, since the retrieval of stored data from the DUT  124  has a delay, in a high-speed test operation, the address provided to the failure memory  128  may not be the same address used to access the DUT  124 . Consequentially, a faulty memory cell may be undetected, and a correctly operating memory cell may be mistakenly replaced.  
         [0012]      FIG. 2  is a timing diagram illustrating operation of the conventional memory test device shown in  FIG. 1 . Referring to  FIG. 2 , a memory command is generated in response to an input clock signal having a predetermined frequency. A row active command ACT is detected at a rising edge of the input clock, and activates a word line of a memory cell array of the DUT  124 . When the row active command ACT is detected, an address applied to the DUT  124  is identified as a row address, and a word line corresponding to the identified row address is activated. When a read command RD is detected at the rising edge of the input clock, a corresponding bit line of the DUT  124  is electrically connected to a local data line, allowing the data stored on the bit line to pass through internal finctioning blocks (not shown) of the DUT  124 . In other words, when a row address and a column address are provided to the DUT  124 , the data stored in the memory cell corresponding intersection of the row and column addresses are provided to the failure discriminator  120  after predetermined number of clock cycles, or latency.  
         [0013]     At internal clock periods CK 5  and CK 6 , data stored in a memory cell corresponding to a row address X 1  and a column address Y 1  is provided to failure discriminator  120 , where the failure discriminator  120  compares the stored data to the expected result and stores the result of the comparison to the failure memory  128  at a row address X 3  and a column address Y 3 . Therefore, due to the latency of the DUT  124  the test result is stored at failure memory addresses X 3  and Y 3  instead of the failure addresses X 1  and Y 1 .  
         [0014]      FIG. 3  is a diagram showing the addressing of a failure memory and a memory device under test shown in  FIG. 1 . Referring to  FIG. 3 , data D 1 , D 2 , D 3 , and D 4  stored in the DUT  124  is provided to the comparator  126  and compared with an expected value. When data D 1  corresponding to the cell address X 1  and Y 1  is compared with the expected value, a test result T 1 , i.e., a result of the comparison, should be stored in the failure address X 1  and Y 1 . Due to the latency of the DUT  124 , however, the test result T 1  is erroneously stored in a failure address X 3  and Y 3 . When data D 2  corresponding to the memory address X 2  and Y 2  is compared with an expected value and a test result T 2  is stored in a failure address X 4  and Y 4 . Similarly, when data D 3  and D 4  are read and compared with corresponding expected values, both of test results T 3  and T 4  are stored in the failure address X 4  and Y 4 . The test result T 2  stored in the failure memory  128 , therefore, may be erased when the test result T 3  is stored, and test result T 3  may be erased when T 4  is stored. This errant storage of test results may cause the redundancy algorithm to perform improperly.  
         [0015]     One solution to overcome this problem is to delay accessing the DUT  124  the latency period. This solution, however, requires an additional testing time. A separate addressing approach is disclosed in Korea Patent No. 0199217, where an address generated from an address generator is divided into an address to a test memory and an address to a failure memory. This approach, however, however, does not allow independent addressing of a memory device under test and to a failure memory, and thus the may erroneously store failure test results.  
       SUMMARY OF THE INVENTION  
       [0016]     The present invention provides an apparatus for testing a memory device comprising a test signal path to provide a test signal to a memory cell array responsive to an address generating command, the test signal to access a memory cell within the memory cell array, a failure address path to generate a failure address responsive to the address generating command, and a failure discriminator to determine a result responsive to the access, the result to indicate whether the memory cell is faulty, and to store the result according to the failure address. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     The features and advantages of the present invention will become more apparent a detailed description of the exemplary embodiments referencing the attached drawings.  
         [0018]      FIG. 1  is a block diagram illustrating a conventional memory test device.  
         [0019]      FIG. 2  is a timing diagram illustrating operation of the conventional memory test device shown in  FIG. 1 .  
         [0020]      FIG. 3  is a diagram showing the addressing of a failure memory and a memory device shown in  FIG. 1 .  
         [0021]      FIG. 4  is a block diagram illustrating a memory test device according to an embodiment of the present invention.  
         [0022]      FIG. 5  is a timing diagram illustrating operation of a memory test device according to an embodiment of the present invention.  
         [0023]      FIG. 6  is a diagram showing the addressing of a failure memory according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0024]      FIG. 4  is a block diagram illustrating a memory test device according to an embodiment of the present invention. Referring to  FIG. 4 , the memory test device includes a test signal path  200 , a failure address path  300  and a failure discriminator  400 . The test signal path  200  provides a test signal to a memory device under test (DUT)  228 . The DUT  228  may be a memory cell array including a plurality of memory cells, where each memory cell is accessed with a corresponding address. The test signal includes a command(s) for controlling the DUT  228  and an address corresponding to a memory cell within the DUT  228 .  
         [0025]     The test signal path  200  includes an address generator  210 , a data generator  220  and a timing generator  226 . The address generator  210  generates an address corresponding to a memory cell within the DUT  228 . The address generator  210  includes a first register  212 , a first ALU/MUX  214  and a first address counter  216 . The first register  212  receives an address generating command and transfers the command to the first ALU/MUX  214  and the first address counter  216  for processing. The first address counter  216  provides the address to data generator  220 . Alternatively, the address generating command may be directly applied to the first address counter  216 , where the command is provided to the data generator  220  as the address.  
         [0026]     The data generator  220  provides an address corresponding to a memory cell to the DUT  228 . In a write operational mode, the data generator  220  may generate data responsive to the address from the address generator  210  and provide the data to the DUT  228 . In other words, the data is generated and provided to the DUT  228  during a write operation of the DUT  228 . The data generator  220  may replace the address received from the address generator  210  with another address provided externally to the data generator  220 . The data generator  220  includes a memory data generator  222  and optionally an address scrambler  224 . The memory data generator  222  generates the data to be written to the memory cell addressed by the address received from the address generator  210 . The address scrambler  224  may replace the addresses of the memory cell with an externally provided replacement addresses. The address scrambler  224  may provide the address, or the externally provided replacement address, to an address/data bus  225 . Alternatively, the address generator  210  may directly provide an address to the address/data bus  225  without passing through the address scrambler  224 . A timing generator  226  controls timing for a test operation responsive to the address, and the operation of the DUT  228  responsive to an operation command. The operation command is used to determine operations to be performed by the DUT  228 , e.g., read, write, etc.  
         [0027]     The data stored in a memory cell of the DUT  228  is provided to the failure discriminator  400  in response to the test signal from the test signal path  200 . The failure discriminator  400  includes a comparator  402  to compare the data from the DUT  228  with an expected value, and to store the comparison result. The comparison result indicates whether the addressed memory cell is faulty. To determine and correct failures of the memory cells in the DUT  228  with a redundancy algorithm, the comparison result needs to be stored. Thus, the failure discriminator  400  includes a failure memory  404 .  
         [0028]     The failure address path  300  generates a failure address corresponding to a test result of the DUT  228  based on the address generating command. To generate the failure address, the failure address path  300  has a failure address generator  310 . The failure address generator  310  generates the failure address responsive to the address generating command. The failure address corresponds to the address generated by the address generator  210 . The failure address generator  310  includes a second register  312 , a second ALU/MUX  314  and a second address counter  316  to generate the failure address during a read operation. The failure address generator  310  operates similarly to address generator  210 . The failure address is provided to the failure memory  404  over a failure address/data bus  317 .  
         [0029]      FIG. 5  is a timing diagram illustrating the operation of a memory test device according to an embodiment of the present invention. Referring to  FIG. 5 , memory commands are generated in response to a clock signal. A row active command ACT detected at a rising edge of the clock signal, activates a word line of the DUT  228 . When the row active command ACT is detected, an address applied to the DUT  228  is recognized as a row address and a word line corresponding to the row address is activated. When a read command RD is detected at the rising edge of the clock signal, a corresponding bit line of the DUT  228  is electrically connected to a local data line, allowing the data stored on the bit line to pass through internal functioning blocks (not shown) of the DUT  228 . In other words, when a row address and a column address are provided to the DUT  124 , the data stored in the memory cell corresponding intersection of the row and column addresses are provided to the failure discriminator  120  after predetermined number of clock cycles, or latency.  
         [0030]     At clock periods CK 5  and CK 6 , data stored in a memory cell corresponding to a row address X 1  and a column address Y 1  is provided to failure discriminator  400 , where the failure discriminator  400  compares the stored data to the expected result and stores the comparison result to the failure memory  404  at a row address X 1  and a column address Y 1  according to the failure address from the failure address generator  310 . Additionally, at clock periods CK 7  and CK 8 , data stored in a memory cell corresponding to a row address X 2  and a column address Y 2  of the DUT  228  is provided to failure discriminator  400 , where the failure discriminator  400  compares the stored data to the expected result and stores the comparison result to the failure memory  404  at row address X 2  and column address Y 2  according to the failure address from the failure address generator  310 . Likewise, data stored in a row address X 3  and a column address Y 3 , and row address X 4  and a column address Y 4  of the DUT are independently compared and the results stored in a row address X 3  and a column address Y 3 , and row address X 4  and a column address Y 4 , of the failure memory  404 , respectively.  
         [0031]     The memory test device of the present invention has the failure address path  300 , which is independent of the test signal path  200 , thus allowing storage of test results at failure addresses independent of the testing address.  
         [0032]      FIG. 6  is a diagram showing the addressing of a failure memory according to an embodiment of the invention. Referring to  FIG. 6 , data corresponding to a memory cell of the DUT  228  is compared with an expected value and the comparison result is stored in the failure memory  404  according to the failure address from the failure address generator  310 . The failure address is provided to the failure memory  404  in consideration of the latency of the DUT  228 .  
         [0033]     Data D 1  stored in a row address X 1  and a column address Y 1  of the DUT  228  is compared with a corresponding expected value by comparator  402 , and the comparison result T 1  is stored in a memory cell corresponding to the row address X 1  and the column address Y 1  of the failure memory  404 . Data D 2 , D 3 , and D 4  are similarly compared and the corresponding comparison results T 2 , T 3 , and T 4 , respectively, are stored in failure memory  404  at their appropriate failure addresses. The redundancy algorithm, therefore, correctly determine which memory cells are faulty responsive to there test result and their address in failure memory  404 .  
         [0034]     Having thus described exemplary embodiments of the present invention, it is to be understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description as many apparent variations thereof are possible without departing from the spirit or scope thereof as hereinafter claimed.