Abstract:
A memory test system injects phase jitter in memory command, address and write data signals in respective pin groups. A phase interpolator receiving a clock signal is provided for each of the pin groups to generate respective delayed clock signals. The phase shift produced by each of the phase interpolators is determined by delay control values, which are passed to the phase interpolators from respective memory arrays. Each of the memory arrays stores at each address a next address along with a delay control value. The next address is used to access the memory array to obtain next delay control value. The delayed clock signals are applied to a clock input of a respective set of registers for each pin group, and a data input of each of the registers receives one of the memory device signals in the respective pin group.

Description:
TECHNICAL FIELD  
       [0001]     This invention relates to testing integrated circuit devices, and, more particularly, to testing integrated circuits in the presence of phase jitter in a manner that causes the signals to have phase jitter of the type that is likely to occur in an operating environment.  
       BACKGROUND OF THE INVENTION  
       [0002]     As the operating speeds of integrated circuits such as memory devices continues to increase, the timing margins for test signals applied to and received from the integrated circuits continues to decrease. For example, the period for which a digital signal is valid, known as the “eye,” decreases as the data rate increases, thereby making it more difficult for the digital signal to be acquired or captured by a receiving device during the eye. In memory systems, write data signals are normally transmitted to a memory device along with a write data strobe signal. The timing of the write data strobe signal is selected so that a transition of the write data strobe signal will occur at the center of the data eye of the write data signals. As the rate at which the write data signals are transmitted is increased, the period of the data eye is correspondingly decreased.  
         [0003]     One factor affecting the location of the data eye is “phase jitter,” which is high frequency phase noise that causes rapid changes in the timing at which transitions of digital signals occur. Phase jitter can be caused by a number of sources, such as noise coupled to digital circuits, which causes the switching time of a digital circuit to vary in a random manner. Jitter can also be caused by variations in the propagation time of digital signals coupled through signal lines. The location of the data eye can also be affected by timing skew, duty cycle variation, and other types of unwanted signal distortion. For example, if, as is normally the case, phase jitter is present on write data signals and/or a write strobe signal coupled to a memory device, a transition of the write strobe signal may no longer occur at the center of the data eye for the write data signals. Under these circumstances, the correct write data will not be stored in the memory device. Similar problems exist in coupling other signals, such as command and address signals, to the memory device, as well as coupling read data signals and a read strobe signal from the memory device and coupling digital signals to other devices.  
         [0004]     During the fabrication of integrated circuits such as memory devices, it is conventional to test such integrated circuits at several stages during the fabrication process. For example, the integrated circuits are normally connected to a tester with a probe card when the integrated circuits are still in wafer form. In a final test occurring after the integrated circuits have been diced from the wafer and packaged, the integrated circuits are placed into sockets on a load board. The load board is then placed on a test head, typically by a robotic handler. The test head makes electrical contact with conductors on the load board that are connected to the integrated circuits. The test head is connected through a cable to a high-speed tester so that the tester can apply signals to and receive signals from the integrated circuits.  
         [0005]     It is important for integrated circuits to be tested under conditions that accurately simulate the conditions they will encounter in normal use. Therefore, phase jitter should be injected into signals applied to an integrated circuit in the course of testing the integrated circuit both during fabrication and after packaging. In the past, attempts have been made to inject phase jitter into test signals using various systems. A typical example of a prior art test system  10  performing this function is shown in  FIG. 1 . The test system  10  includes a test signal generator  14 , which outputs a number of signals on a bus  16 . The signals output from the test signal generator  14  may have a pattern determined by data applied to the test signal generator  14  through a JTAG interface. The number of test signals generated will determine the width of the bus  16 , and both will be determined by the number of signals that a device under test (“DUT”) is adapted to receive. The test signals provided by the test signal generator  14  may be, for example, a set of memory command signals, a set of address signals, and a set of write data signals accompanied by a write data strobe signal.  
         [0006]     The test signals coupled through the bus  16  are applied to an interface  20 , which includes a register  24  for each of the test signals. Each of the registers  24  has a data input, a clock input and an output. The data input of each of the registers  24  receives a respective one of the test signals from the test signal generator  14 . The output of each of the registers  24  is coupled to a respective signal line of a bus  28 . The bus  28  is, in turn, connected to the DUT.  
         [0007]     The clock inputs of all of the registers  24  in the interface  20  receive an interface clock signal ICLK from the output of a phase interpolator  30 . As is well-known in the art, a phase interpolator produces a delayed signal from an input signal by shifting the phase of the input signal by a precisely controlled amount. The degree of precision of the delay of the ICLK signal depends on the precision of the input signal frequency. The phase interpolator  30  can, for example, vary the delay of the ICLK signal in 1 nanosecond increments by using an input signal having a frequency of 5 mHz and using a phase interpolator having 200 phase increments. The phase shift provided by the phase interpolator  30  is determined by a control circuit  34 , which receives a phase control value at its control “C” input. The phase control value is a binary number generated by an analog-to-digital (“A/D”) converter  36 . The magnitude of the phase control value corresponds to the amplitude of an analog signal applied to the input of the A/D converter  36 . In the past, this analog signal has been a periodic signal, such as a sine wave.  
         [0008]     The clock signal applied to the phase interpolator  30  is generated by a phase-lock loop (“PLL”)  38  from an input clock signal CLKIN. The PLL  38  ensures that the clock signal applied to the phase interpolator  30  has relatively little jitter and a duty cycle of substantially 50 percent.  
         [0009]     In operation, the ICKL signal causes the test signals from the test signal generator  14  to be clocked into respective registers  20 . When the test signals are clocked into the registers  24 , they also become present at the outputs of the registers  24 . Therefore, the transitions of the ICKL signal determines the times that the test signals are applied to the DUT through the bus  28 . The sine wave applied to the input of the A/D converter  36  causes the phase interpolator  30  to increase the phase of the ICLK signal responsive to the positive portion of the sine wave and to decrease the phase of the ICLK signal responsive to the negative portion of the sine wave. As the phase of the ICKL signal increases and decreases, the timing at which the test signals are applied to the DUT also increases and decreases in a corresponding manner.  
         [0010]     The increase and decrease in the timing at which the test signals are applied to the DUT are intended to simulate phase jitter that are expected to be present in signals received by the DUT during normal use. However, normal jitter is neither regular nor periodic. Instead, jitter is normally somewhat random, and the amplitude of the jitter varies substantially. Therefore, conventional testing systems and methods for injecting jitter in digital test signals do not accurately simulate the jitter that will be present in signals during normal operation. For this reason, a test conducted with the system  10  may indicate that the DUT will function properly under normal operation conditions, when, in fact, it may fail to function properly in normal use because of the presence of phase jitter.  
         [0011]     There is therefore a need for a system and method that is capable of injecting phase jitter in digital test signals in a manner that causes the jitter to accurately simulate the type of jitter that is likely to be present in normal operation.  
       SUMMARY OF THE INVENTION  
       [0012]     A system and method for injecting phase jitter in a digital signal includes a delay circuit having an input to which an input clock signal is applied. The delay circuit delays the input clock signal by a delay corresponding to a delay control value applied to a control input of the delay circuit thereby providing a delayed clock signal. The system also includes a memory array storing a plurality of the delay control values at respective addresses. The memory array is coupled to the delay circuit to provide one of the delay control values to the delay circuit when the memory array is accessed at a corresponding address. The memory array is sequentially addressed by a memory array access circuit coupled to the memory array to cause the memory array to sequentially apply corresponding delay control values to the delay circuit. An interface circuit included in the system receives the delayed clock signal and the digital signal. The interface circuit transmits the digital signal responsive to a transition of the delayed clock signal. Therefore, as different delay control values are applied to the delay circuit, the timing of the transitions of the delayed clock signal, and hence the transmissions of the digital signal, vary in a corresponding manner. When providing each of the delay control values to the delay circuit, the memory array may also provide a corresponding next address to the memory array access circuit, which may be used by the access circuit for the next memory array access. As a result, the sequence of delay control values transferred to the delay circuit may be controlled by the data stored in the memory array. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]      FIG. 1  is a block diagram of one example of a prior test system that attempts to inject jitter in signals used to test digital integrated circuits.  
         [0014]      FIG. 2  is a block diagram of a test system according to one example of the invention, which attempts to inject jitter in signals used to test digital integrated circuits.  
         [0015]      FIG. 3  is a block diagram of a system for testing memory devices according to one example of the invention.  
         [0016]      FIG. 4  is an isometric view of a test system according to one example of the invention.  
         [0017]      FIGS. 5A  and SB are top and bottom plan views, respectively, of a load board used in the test system of  FIG. 4 .  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]     A test system  50  according to one example of the present invention is shown in  FIG. 2 . The test system  50  includes a clock phase adjustment system  52  that uses some of the same components that are used in the prior art test system  10  of  FIG. 1 . Therefore, in the interest of brevity, an explanation of their operation will not be repeated. The test system  50  differs from the test system  10  shown in  FIG. 1  in the manner in which the clock jitter system generates the phase control values that are applied to the control input of the control circuit  34 . More specifically, in the test system  50 , the phase control values are read from a memory array  54  at a location corresponding to an address from a program controller  58 .  
         [0019]     As shown in  FIG. 2 , the memory array  54  includes two fields at each address, namely the phase control value (“PCV”) field and a next address word (“NA”) field. The memory array  54  may be programmed with the phase control value and next address word pairs through a JTAG interface  56 . In operation, when the phase control value is applied to the control circuit  34 , the next address is passed to the program controller  58 . The program controller  58  then uses the next address for the next access of the memory array  54 . On the first access to the memory array  54 , the programmer controller  58  will not have received a next address from the memory array  54 . Therefore, an initial address that is used by the program controller to initially access the memory array  54  is passed to the program controller  58  from a configuration register  60 . The configuration register  60  is programmed with the initial address through the JTAG interface  62  of the test signal generator  14  through the test signal generator  14  and a bus  64 .  
         [0020]     In operation, the initial address that was provided to the program controller  58 , as previously explained, is used by the program controller  58  to access the memory array  54 . An initial phase control value stored in the array  54  at the initial address is then applied to the control input of the control circuit  34 . The control circuit  34  causes the phase interpolator  30  to increase or decrease the phase of the ICLK signal by a magnitude corresponding to the magnitude of the initial phase control value. When the array  54  is accessed at the initial address, the next address stored at the initial address is also passed to the program controller  58 . This next address is then used to access the next phase control value stored in the array  54 . When the next phase control value is passed to the control circuit  34 , the control circuit  34  causes the phase interpolator to change the phase of the ICLK signal by a magnitude and polarity corresponding to the value of the next phase control value. The operation proceeds in this manner until the phase control value stored in the array  54  at a final address is reached. At this final address, the next address field is either blank, or it links to an address that prevents further phase control values from being accessed. Alternatively, a final address may be stored into the program controller  58  in the same manner that the initial address is stored in the program controller  58 . In such case, the program controller compares each “next address” to the final address, and halts the passing of addresses to the memory array  54  in the event of a match.  
         [0021]     By properly selecting the next addresses that are used to program the array  54 , the addresses in the array  54  can be accessed in a loop so that the array  54  can output phase control values indefinitely. In fact, the array  54  can store next addresses arranged in several different loops so that the corresponding phase control values can create different jitter algorithms. Each of these jitter algorithms can be selected by programming the configuration register  60  with an initial address that links to the selected loop.  
         [0022]     The phase control values stored in the memory array  54  are preferably chosen so that the phase control values sequentially read from the array  54  will have magnitudes that vary in a fairly random manner. As a result, the phase shifts provided by the phase interpolator  30  can accurately simulate the type of phase jitter that the device under test can be expected to encounter in normal operation.  
         [0023]     A system  70  for testing memory devices according to one example of the invention is shown in  FIG. 3 . The memory testing system  70  includes a test signal generator  74  that is similar to the test signal generator  14  used in the example of  FIG. 2 . The test signal generator  74  generates three sets of parallel signals. The test signal generator  74  outputs a set of command signals (which may include a write data strobe signal) on a command bus (“CMD”)  76 , a set of address signals on an address bus (“ADDR”)  78 , and a set of write data signals on a write data bus (“WD”)  80 . Each of these sets of signals are sometimes referred to as “pin groups” of signals.  
         [0024]     The command signals are applied to the respective data inputs of a plurality of command registers  90  (although only one command register  90  is shown for purposes of clarity). Similarly, the address signals are applied to the respective data inputs of a plurality of address registers  94 , and the write data signals are applied to the respective data inputs of a plurality of write data registers  96 . The outputs of the registers  90 ,  94 ,  96  are applied to the command bus, address bus and data bus of a memory device  99  that is being tested.  
         [0025]     The clock inputs of the command registers  90  receive a first internal clock signal ICLKCMD, the clock inputs of the address registers  94  receive a second internal clock signal ICLKADDR, and the clock inputs of the write data registers  96  receive a third internal clock signal ICLKWD. These internal clock signal are generated by respective clock phase adjustment systems  52  of the type used in the test system  50  of  FIG. 2 . The memory array  54  in each of the clock phase adjustment systems  52  may be individually programmed through the JTAG interface  56  with phase control values and next addresses so that the clock phase adjustment systems  52  may provide different clock jitter algorithms. Furthermore, each of the systems  52  may receive a different initial address from the test signal generator  74  through the JTAG interface  62 , as explained above.  
         [0026]     In normal operating environments, the phase jitter of the command signals, may be different from the phase jitter of the address signals, and the phase jitter of both of those signals may be different from the phase jitter of the write data signals. Therefore, by allowing the phase jitter of each pin group of signals to be individually controlled, the memory testing system  70  provides a realistic testing environment that accurately simulates the normal operating environment of the memory device  98 .  
         [0027]     Although the memory testing system  70  uses three separate clock phase adjustment systems  52  to provide the three internal clock signals ICLKCMD, ICLKADDR, and ICLKWD, it should be understood that certain components of a clock phase adjustment system  52  may be shared. For example, three phase control values and a next address can be stored in each location in a single memory array  54 . The single array  54  would then be accessed by a single program controller  58  and configuration register  60 . The three phase control values output from the array  54  would be coupled to respective phase interpolators  30 . The three phase interpolators  30  would then output the internal clock signals ICLKCMD, ICLKADDR, and ICLKWD, respectively, which would be coupled to the clock inputs of the command registers  90 , the address registers  94  and the write data registers  96 , respectively.  
         [0028]     A test system  100  using the memory testing system  70  according to one example of the invention is illustrated in  FIG. 4 . The test system  100  includes a test head  112  on which several load boards  114   a - d  are placed. Each of the load boards  114   a - d  have a printed circuit substrate  116  on which several integrated circuit sockets  118   a - h  are mounted. Each of the integrated circuit sockets  118   a - h  receives a respective integrated circuit memory device (not shown in  FIG. 4 ). In the example shown in  FIG. 4 , the sockets  118   a - h  are adapted to receive dynamic random access memory (“DRAM”) devices. Prior to final testing of the memory devices, an integrated circuit handler loads a memory device into each of the sockets  118   a - h , and then places each of the load boards  114   a - d  on the test head  112 .  
         [0029]     As explained in greater detail below, each of the load boards  114   a - d  includes an integrated test circuit (not shown in  FIG. 4 ) mounted on the surface of the substrate  116  opposite the surface on which the sockets  118   a - h  are mounted. The sockets  118   a - h  are shown mounted on the upper surface of the substrate  116  in greater detail in  FIG. 5A . The lower surface of the substrate  116  is shown in  FIG. 5B . An integrated test circuit  120  is mounted at the center of the substrate  116 , and it is connected to the sockets  118   a - h  through conventional printed circuit traces (not shown in  FIG. 5B ). Also mounted on the lower surface of the substrate  116  are a conventional JTAG connector  122  and a power supply connector  124 , which are used as the JTAG interfaces  56 ,  62  ( FIG. 3 ). High-level test commands are applied to the test circuit  120  through the JTAG connector  122 , and high-level results data are received from the test circuit  120  through the JTAG connector  122 . Power is applied to the test circuit  120  as well as to integrated circuits mounted in the sockets  118   a - h  through the power supply connector  124 .  
         [0030]     According to one embodiment of the invention, the integrated test circuit  120  uses the memory testing system  70  or some other example of the invention to inject phase jitter into the command, address, and write data signals applied to the memory devices in the sockets  118   a - h . The memory arrays  54  ( FIG. 2 ) and the configuration register  60  in each of the clock phase adjustment systems  52  is programmed through the JTAG connector  122  in the manner explained above with reference to  FIG. 2 .  
         [0031]     In operation, the test circuit  120  applies predetermined command, address and write data signals to the integrated circuits mounted in the sockets  118   a - h  to write data into the memory devices in the sockets  118   a - h . The test circuit  120  then receives read data from the memory devices, and it determines whether the data read from each address corresponds to the data written to the same addresses. Insofar as the integrated test circuit  120  is mounted on the same substrate  116  as the memory devices being tested, the timing at which the pattern of signals are applied to the memory devices can be more precisely controlled. Furthermore, the relatively short length of the conductors extending from the integrated test circuit  120  to the memory devices in the sockets  118   a - h  allows the circuitry in the integrated test circuit  120  to be less complex and therefore less expensive than with testers in which a pattern of test signals is applied through a long cable. In fact, the close proximity between the integrated test circuit  120  and the memory devices being tested will normally be similar to the proximity between the memory devices and memory access devices in normal operation. The test system  100  therefore accurately replicates the normal operating environment of the memory device in both the presence of phase jitter and the path length of signals coupled to and from the memory devices.  
         [0032]     With further reference to  FIG. 4 , the test head  112  is mounted on the upper ends of several power supplies  126   a - d , which generate DC supply voltages at respective magnitudes for use by the test head  112  and the load boards  114   a - d . As mentioned above, the DC supply voltages are applied to the test head  112  through the power supply connector  124  ( FIG. 5B ). The test head  112  also includes fluid couplings  129   a,b  that receive and discharge a cooling fluid, respectively, for maintaining the temperature of the test circuit  120  at a stable acceptably cool temperature.  
         [0033]     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, it will be understood by one skilled in the art that various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.