Abstract:
An architecture for resonant clock distribution networks is proposed. The proposed architecture allows for the energy-efficient operation of the resonant clock distribution network in conventional mode, so that it meets target specifications for the clock waveform. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to at-speed testing and to binning of semiconductor devices according to achievable performance levels.

Description:
CLAIM OF PRIORITY AND RELATED APPLICATIONS 
     This patent application is a conversion of and claims priority to U.S. Provisional Patent Application No. 61/250,830, entitled S YSTEMS AND  M ETHODS FOR  R ESONANT  C LOCKING  I NTEGRATED  C IRCUITS , filed Oct. 12, 2009, which is incorporated herein in its entirety. This patent application is related to the technologies described in the following patents and applications, all of which are incorporated herein in their entireties: 
     U.S. patent application Ser. No. 12/125,009, entitled R ESONANT  C LOCK AND  I NTERCONNECT  A RCHITECTURE FOR  D IGITAL  D EVICES WITH  M ULTIPLE  C LOCK  N ETWORKS , filed Oct. 12, 2009, which claims priority to U.S. Provisional Patent Application No. 60/931,582, entitled R ESONANT  C LOCK AND  I NTERCONNECT  A RCHITECTURE FOR  P ROGRAMMABLE  L OGIC  D EVICES , filed May 23, 2007; 
     U.S. patent application Ser. No. 12/903,154, entitled R ESONANT  C LOCK  D ISTRIBUTION  N ETWORK  A RCHITECTURE WITH  P ROGRAMMABLE  D RIVERS , filed Oct. 12, 2010; 
     U.S. patent application Ser. No. 12/903,158, entitled A RCHITECTURE FOR  C ONTROLLING  C LOCK  C HARACTERISTICS , filed Oct. 12, 2010; 
     U.S. patent application Ser. No. 12/903,163, entitled M ETHOD FOR  S ELECTING  N ATURAL  F REQUENCY IN  R ESONANT  C LOCK  D ISTRIBUTION  N ETWORKS WITH NO  I NDUCTOR  O VERHEAD , filed Oct. 12, 2010; 
     U.S. patent application Ser. No. 12/903,166, entitled A RCHITECTURE FOR  A DJUSTING  N ATURAL  F REQUENCY IN  R ESONANT  C LOCK  D ISTRIBUTION  N ETWORKS , filed Oct. 12, 2010; 
     U.S. patent application Ser. No. 12/903,168, entitled A RCHITECTURE FOR  F REQUENCY -S CALED  O PERATION IN  R ESONANT  C LOCK  D ISTRIBUTION  N ETWORKS , filed Oct. 12, 2010; 
     U.S. patent application Ser. No. 12/903,172, entitled A RCHITECTURE FOR  S INGLE -S TEPPING IN  R ESONANT  C LOCK  D ISTRIBUTION  N ETWORKS , filed Oct. 12, 2010; 
     U.S. patent application Ser. No. 12/903,174, entitled A RCHITECTURE FOR  O PERATING  R ESONANT  C LOCK  N ETWORK IN  C ONVENTIONAL  M ODE , filed Oct. 12, 2010; and 
     U.S. patent application Ser. No. 12/903,188, entitled R ESONANT  C LOCK  D ISTRIBUTION  N ETWORK  A RCHITECTURE FOR  T RACKING  P ARAMETER  V ARIATIONS IN  C ONVENTIONAL  C LOCK  D ISTRIBUTION  N ETWORKS  filed Oct. 12, 2010. 
     FIELD OF INVENTION 
     This disclosure relates generally to clock distribution network architectures for digital devices with multiple clock networks and various clock frequencies such as microprocessors, application-specific integrated circuits (ASICs), and System-on-a-Chip (SOC) devices. 
     BACKGROUND OF THE INVENTION 
     Resonant clock distribution networks have been proposed for the energy-efficient distribution of clock signals in synchronous digital systems. In these networks, energy-efficient operation is achieved using one or more inductors to resonate the parasitic capacitance of the clock distribution network. Clock distribution with extremely low jitter is achieved through the reduction in the number of clock buffers. Moreover, extremely low skew is achieved among the distributed clock signals through the design of relatively symmetric all-metal distribution networks. Overall network performance depends on operating speed and total network inductance, resistance, size, and topology, with lower-resistance symmetric networks resulting in lower jitter, skew, and energy consumption when designed with adequate inductance. 
     In practice, digital devices are often specified and designed to operate at multiple clock frequencies. For example, a high-performance microprocessor may be designed to operate at multiple clock frequencies ranging from 100 MHz to 3 GHz. The technique of operating a clock signal at different clock frequencies over time is commonly referred to as frequency scaling and is motivated by the need to reduce power consumption in semiconductor devices. Power consumption in digital semiconductor devices grows in proportion with the rate at which these devices switch between their digital values. When performance requirements decrease, this rate can be reduced by reducing the frequency of the clock signal, thereby reducing power consumption. 
     The operation of clock signals at more than a single frequency also arises in the context of device binning, that is, the practice of selling at a premium a device that, due to manufacturing variations, is capable of operating at a higher peak clock frequency than another device of identical design and functionality. For example, a batch of microprocessors that was fabricated on a “fast” semiconductor manufacturing corner may contain microprocessors capable of running at clock frequencies of up to 3 GHz, while an identical-in-design batch of microprocessors that was fabricated on a “typical” semiconductor manufacturing corner may contain microprocessors that can run at clock frequencies of at most 2 GHz. While of identical design, the microprocessors in the first “fast” batch can be sold at significantly higher prices, due to their better achieved performance. 
     The challenge with the deployment of resonant clock distribution networks in multi-frequency operation contexts is that these networks typically achieve their highest energy efficiency for a relatively narrow range of clock frequencies centered around the natural frequency of the resonant network. For clock frequencies outside this narrow range, energy efficiency degrades significantly, and to an extent that outweighs the inherent energy advantages of resonant clocking. For example, consider a microprocessor that has been designed with a target frequency of 3 GHz, but its digital logic can only achieve a peak clock rate of 2 GHz after manufacturing. In a non-resonant clock implementation of the microprocessor, the clock network can be operated at 2 GHz, consuming power in proportion to its 2 GHz operating frequency. In a resonant clock design, however, if the resonant clock network operates at 2 GHz, instead of its natural frequency of 3 GHz, its power consumption may significantly exceed the power consumption of the non-resonant design at 2 GHz. As a general principle, it is desirable that the design with the resonant clock network does not consume more power than its counterpart with a conventional clock network under all operating frequencies. 
     In addition to excessive power consumption, when a resonant clock network operates away from its natural frequency, the shape of the clock waveform is increasingly deformed, as the mismatch between the natural and the operating frequency increases. In extreme situations, the peak clock frequency after manufacturing may be so far from the natural frequency of the resonant clock network that the clock waveform at the peak clock frequency becomes deformed to such an extent that incorrect operation of the clocked elements results, and the function of the overall device becomes faulty. 
     At-speed testing presents yet another challenge related with the use of resonant clock distribution networks in digital devices. In this kind of testing, a specific bit pattern is first loaded onto specified scan registers (scan-in mode) using a clock frequency that is significantly slower (for example, 5 times or more) than the target clock frequency that operation is to be tested at. The digital system is then operated for one or more clock cycles at the target clock frequency (at-speed-test mode), and to validate correct function, the contents of the scan registers are then read (scan-out mode) using a clock frequency that is once again significantly slower than the target clock frequency. Resonant clock distribution networks typically require multiple clock cycles of operation before they are able to provided their specified clock amplitude. Therefore, switching from scan-in mode to at-speed-test mode (or from at-speed-test mode to scan-out mode) is a challenge, due to the requirement for full-amplitude clock signals right from the beginning of the at-speed-test mode, and due to the difference in the clock frequencies between the scan modes and the at-speed-test mode. Furthermore, the great difference in clock frequency between scan modes and at-speed-test mode implies a significant difference in the rise and/or fall time of the clock waveform, and typically it is critical that the rise and/or fall times during at-speed testing match that of the resonant clock waveform at the same frequency when the network is operating in resonant mode. 
     An approach that can be used to address the above challenges is to essentially disable the inductive elements of the resonant clock network, and thereby allow the clock drivers to swing the normally resonant clock distribution network in a conventional (i.e., non-resonant) mode. The energy efficiency of the resonant clock network and the characteristics of the clock waveform depend on the way that the inductive elements are disabled. Consequently, in a resonant clock distribution network that allows for the disabling of its inductive elements, to ensure that energy efficiency remains high and that the clock waveform meets its target specification, certain resonant clock network architectures are preferable. 
     Architectures for resonant clock distribution networks have been described and empirically evaluated in several articles, including “A 225 MHz Resonant Clocked ASIC Chip,” by Ziesler C., et al.,  International Symposium on Low - Power Electronic Design , August 2003; “Energy Recovery Clocking Scheme and Flip-Flops for_Ultra Low-Energy Applications,” by Cooke, M., et al.,  International Symposium on Low - Power Electronic Design , August 2003; and “Resonant Clocking Using Distributed Parasitic Capacitance,” by Drake, A., et al.,  Journal of Solid - State Circuits , Vol. 39, No. 9, September 2004; “900 MHz to 1.2 GHz two-phase resonant clock network with programmable driver and loading,” by Chueh J.-Y., et al.,  IEEE  2006  Custom Integrated Circuits Conference , September 2006; “A 0.8-1.2 GHz frequency tunable single-phase resonant-clocked FIR filter,” by Sathe V., et al.,  IEEE  2007  Custom Integrated Circuits Conference , September 2007. However, the resonant clock networks described in all these articles always operate in resonant mode. Moreover, the resonant clock distribution networks described in these articles do not describe any approaches for disabling their inductive elements 
     A resonant clock distribution network design that can also operate in conventional mode is mentioned in the article “A Resonant Global Clock Distribution for the Cell Broadband Engine Processor,” by Chan S., et al.,  IEEE Journal of Solid State Circuits , Vol. 44, No. 1, January 2009. However, the article does not provide any specifics of such a clock network design, such as circuit topologies and any design and optimization issues associated with them, and therefore is purely conceptual with respect to the use of conventional mode operation. 
     Overall, the examples herein of some prior or related systems and their associated limitations are intended to be illustrative and not exclusive. Other limitations of existing or prior systems will become apparent to those of skill in the art upon reading the following Detailed Description. 
     SUMMARY OF THE DESCRIPTION 
     An architecture for resonant clock distribution networks is proposed. The proposed architecture allows for the energy-efficient operation of the resonant clock distribution network in conventional mode, so that it meets target specifications for the clock waveform. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to at-speed testing and to binning of semiconductor devices according to achievable performance levels. 
     Disclosed is a clock driver comprising: a resonance element electrically coupled to a clock node of the clock driver, the resonance element configured to enable the clock driver to operate in a resonant mode; a drive element electrically coupled to the clock node, the drive element configured to receive and propagate a reference clock of the clock distribution network based on a logical input signal; a mid-point supply node configured to provide a power supply to the resonance element; a first switch element, wherein a first end of the first switch element is electrically coupled to the mid-point supply node and a second end of the first switch element is electrically coupled to a first end of the resonance element; a second switch element connected in parallel to the resonance element, wherein a first end of the second switch element is electrically coupled to the first end of the resonance element and a second end of the second switch element is electrically coupled to a second end of the resonance element; wherein, the clock driver is configured to selectively operate either in a resonant mode or a non-resonant mode based on an operating state of the first switch element and the second switch element, wherein: when the first switch element is switched on and the second switch element is switched off, the clock driver operates in a resonant mode; and when the second switch element is switched on, the resonance element is bypassed and the clock driver operates in a non-resonant mode. 
     This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Other advantages and features will become apparent from the following description and claims. It should be understood that the description and specific examples are intended for purposes of illustration only and not intended to limit the scope of the present disclosure. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       These and other objects, features and characteristics of the present invention will become more apparent to those skilled in the art from a study of the following detailed description in conjunction with the appended claims and drawings, all of which form a part of this specification. In the drawings: 
         FIG. 1  shows a typical architecture of a resonant clock distribution network. 
         FIG. 2  shows a typical driver design for resonant clocking with the clock load modeled as a lumped capacitor. 
         FIG. 3  shows an approach to the design of a resonant driver that supports both resonant and conventional operation. 
         FIG. 4  shows an alternative approach to the design of a resonant clock driver that supports both resonant and conventional operation. 
         FIG. 5  shows an embodiment of the proposed approach for the design of a resonant clock driver that supports both resonant and conventional operation. 
         FIG. 6  shows an alternative embodiment of the proposed approach for the design of a resonant clock driver that supports both resonant and conventional operation. 
         FIG. 7  shows another alternative embodiment of the proposed approach for the design of a resonant clock driver that supports both resonant and conventional operation. 
         FIG. 8  shows another alternative embodiment of the proposed approach for the design of a resonant clock driver that supports both resonant and conventional operation. 
     
    
    
     The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claimed invention. 
     In the drawings, the same reference numbers and any acronyms identify elements or acts with the same or similar structure or functionality for ease of understanding and convenience. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Various examples of the invention will now be described. The following description provides specific details for a thorough understanding and enabling description of these examples. One skilled in the relevant art will understand, however, that the invention may be practiced without many of these details. Likewise, one skilled in the relevant art will also understand that the invention can include many other obvious features not described in detail herein. Additionally, some well-known structures or functions may not be shown or described in detail below, so as to avoid unnecessarily obscuring the relevant description. 
     The terminology used below is to be interpreted in its broadest reasonable manner, even though it is being used in conjunction with a detailed description of certain specific examples of the invention. Indeed, certain terms may even be emphasized below; however, any terminology intended to be interpreted in any restricted manner will be overtly and specifically defined as such in this Detailed Description section. 
       FIG. 1  shows a typical resonant clock distribution network architecture for a semiconductor device. In this network, a buffered distribution network is used to distribute a reference clock signal to multiple resonant clock drivers that are in turn used to drive the clock signal across an all-metal clock distribution network. Typically, this all-metal network has an approximately symmetric topology, delivering the clock signal to the clocked elements (for example, flip-flops and clock gaters) of the semiconductor device with very low skew. Each resonant clock driver incorporates an inductor that is used to provide additional drive strength with low energy consumption by resonating the parasitic capacitance of the load seen by the driver. 
       FIG. 2  shows a typical resonant clock driver design, in which the part of the overall clock distribution network serviced by the resonant clock driver, is modeled as a lumped capacitor C in series with a lumped resistance R. This driver comprises a pull-up PMOS and a pull-down NMOS device for driving the clock. The PMOS device is connected between the clock node and the power supply terminal. The NMOS device is connected between the clock node and the ground terminal. Both devices are driven by the reference clock signal. An inductor L is connected between the clock node and a supply node with voltage at approximately the mid-point of the clock signal oscillation. For example, if the clock signal oscillates between 0V and 1V, the mid-point supply voltage is approximately 0.5V. In the driver of this figure, the mid-point is implemented using two capacitors Cdd and Css. Capacitor Cdd is connected between the mid-point and the power supply terminal. Capacitor Css is connected between the mid-point and the ground terminal. To maximize energy savings, the value of the inductor is approximately chosen so that the LC tank set-up by the inductor and the parasitic capacitance of the clock distribution network has a natural frequency that is approximately equal to the frequency of the reference clock signal. 
     The energy efficiency of the resonant clock driver depends on various design and operating parameters. The quality factor Q of the resonant system is an indicator of its energy efficiency. This factor is proportional to (L/C) 1/2 /R. In general, energy efficiency decreases as R increases, due to the I 2 R losses associated with the flow of the current I that charges and discharges the parasitic clock load C through the resistance R. Also, for a fixed natural frequency, energy efficiency decreases as capacitance C increases, since the current flowing through resistance R increases. 
     The mismatch between the natural frequency of the resonant LC-tank systems and the frequency of the reference clock signal is another important factor that affects the energy efficiency of the resonant clock network. As the frequency of the reference clock that drives the resonant clock driver moves further away from the natural frequency of the resonant clock driver&#39;s LC-tank, energy efficiency decreases. When the mismatch between the two frequencies becomes too large, the energy consumption of the resonant clock driver becomes excessive and impractically high. Moreover, the shape of the clock waveform is so distorted that it cannot be reliably used to clock flip-flops or other clocked storage elements. Consequently, resonant clock drivers tend to have a narrower range of clock frequencies within which they operate efficiently than the range of clock frequencies typically supported by a semiconductor device that uses frequency scaling. 
     To support the broad range of operating frequencies used in a frequency-scaled semiconductor device, and to provide support for at-speed testing, resonant clock drivers are designed so that the resonant clock network can also be operated in conventional mode.  FIG. 3  shows a possible resonant clock driver design which supports operation in resonant and conventional mode. This design is an adaptation of the resonant clock driver in  FIG. 2 , which has been extended to include a switch S between the clock node and the inductor terminal that is connected to the clock node. In this design, the switch S has been implemented as a transmission gate with a PMOS and an NMOS device. Switch S can be used to disable the inductor by selectively decoupling it from the clock node, thus providing the option of driving the clock network in conventional (i.e., non-resonant mode). When the control signal ENS turns the switch on, the inductor is part of the resonant clock network, and the resonant clock driver operates the resonant clock network in resonant mode. When the control signal ENS turns the switch off, the inductor is decoupled from the resonant clock network, and the resonant clock driver operates the resonant clock network in conventional mode. 
     The architecture of the resonant clock driver shown in  FIG. 3  has certain advantages and disadvantages. The main advantage is that it completely decouples the inductor from the resonant clock network. Therefore, when the network is operating, the inductor does not affect the characteristics of the clock waveform in any significant way. However, the main disadvantage of this architecture is that when the resonant clock network is operating in resonant mode, the parasitic capacitance of switch S is part of the clock load that is driven by the clock driver. It therefore exhibits an increased total clock capacitance on the clock node, compared to a conventional clock network design, thus limiting the relative energy savings potential of resonant clock distribution. 
       FIG. 4  shows an alternative resonant clock driver design which supports operation in resonant and conventional mode, and overcomes some of the disadvantages of the resonant clock driver design shown in  FIG. 3 . In this driver design, switch S has been connected between the mid-point supply node and the inductor terminal that is originally connected to that node. In this design, switch S has been implemented as a transmission gate with a PMOS and an NMOS device. Switch S can be used to disable the inductor by selectively decoupling it from the mid-point supply node, thus providing the option of driving the clock network in conventional mode. When the control signal ENS turns the switch on, the inductor is part of the resonant clock network, and the resonant clock driver operates the resonant clock network in resonant mode. When the control signal ENS turns the switch off, the inductor is decoupled from the mid-point supply node, and the resonant clock driver operates the resonant clock network in conventional mode. In this design, when the resonant clock network is operating in resonant mode, the capacitance of switch S is combined with the capacitors Cdd and Css that yield the mid-point supply voltage. Therefore, this capacitance is not part of the clock node, and the relative energy savings potential of the resonant clock distribution network is not limited as with the driver design shown in  FIG. 3 . 
     A main disadvantage of the resonant clock driver design in  FIG. 4  is that when the resonant clock network operates in conventional mode, one inductor terminal is still connected to the clock node, whereas the other inductor terminal is connected to one of the terminals of switch S, which generally presents a tangible, but relatively small, capacitance compared to the capacitance of the clock node. With the clock node switching at a high rate, the flow of current through the inductor to and from the switch S terminal capacitance generates high frequency components that distort the shape of the clock waveform on the main clock node. Moreover, the same flow of current through the inductor to and from the switch S terminal capacitance can drive the voltage of the switch S terminal capacitance to values that will momentarily allow the conduction of current through the NMOS and PMOS devices that are used to implement the switch S. To offset this conduction of current, the NMOS and PMOS devices driving the clock node must provide additional current to the clock node, resulting in increased energy consumption. 
       FIG. 5  shows an embodiment of the proposed architecture for supporting the energy efficient operation of a resonant clock network in conventional mode. In this embodiment, the resonant clock driver design from  FIG. 4  has been augmented to include an additional switch B that is placed in parallel to the inductive element of the resonant clock driver. When the resonant clock network is operating in resonant mode, switch B is turned off using the control signal ENB. In this case, the switch does not conduct any current, and the inductor is connected to the resonant clock network. When the resonant clock network is operating in conventional mode, switch B is turned on, and the inductor is bypassed. Current build-up in the inductor is thus limited, reducing distortion in the shape of the clock waveform, and reducing momentary currents through switch S. 
     An alternative embodiment of the proposed architecture is shown in  FIG. 6 . This embodiment is an extension of the embodiment shown in  FIG. 5 , in which the resonant clock driver includes multiple pairs of NMOS/PMOS devices to drive the clock node, that can be selectively enabled using control signals EN 1 , . . . , ENn. 
     Another alternative embodiment of the proposed architecture is shown in  FIG. 7 . This embodiment is an extension of the embodiment shown in  FIG. 6 , in which switch S has been relocated. Specifically, the PMOS device of the switch has been placed between the mid-point node, and the non-VDD terminal of the capacitor Cdd, and the NMOS device has been placed between the mid-point node and the non-VSS terminal of the capacitor Css. 
       FIG. 8  shows another alternative embodiment of the proposed architecture. This embodiment is an extension of the one shown in  FIG. 6 , in which the pull-down devices can be driven by a separate reference clock signal from the pull-up devices. This embodiment allows for the pull-up devices to be driven using a reference clock with a different duty cycle from the pull-down devices. 
     Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense (i.e., to say, in the sense of “including, but not limited to”), as opposed to an exclusive or exhaustive sense. As used herein, the terms “connected,” “coupled,” or any variant thereof means any connection or coupling, either direct or indirect, between two or more elements. Such a coupling or connection between the elements can be physical, logical, or a combination thereof. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or,” in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. 
     The above Detailed Description of examples of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific examples for the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. While processes or blocks are presented in a given order in this application, alternative implementations may perform routines having steps performed in a different order, or employ systems having blocks in a different order. Some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified to provide alternative or sub-combinations. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed or implemented in parallel, or may be performed at different times. Further any specific numbers noted herein are only examples. It is understood that alternative implementations may employ differing values or ranges. 
     The various illustrations and teachings provided herein can also be applied to systems other than the system described above. The elements and acts of the various examples described above can be combined to provide further implementations of the invention. 
     Any patents and applications and other references noted above, including any that may be listed in accompanying filing papers, are incorporated herein by reference. Aspects of the invention can be modified, if necessary, to employ the systems, functions, and concepts included in such references to provide further implementations of the invention. 
     These and other changes can be made to the invention in light of the above Detailed Description. While the above description describes certain examples of the invention, and describes the best mode contemplated, no matter how detailed the above appears in text, the invention can be practiced in many ways. Details of the system may vary considerably in its specific implementation, while still being encompassed by the invention disclosed herein. As noted above, particular terminology used when describing certain features or aspects of the invention should not be taken to imply that the terminology is being redefined herein to be restricted to any specific characteristics, features, or aspects of the invention with which that terminology is associated. In general, the terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification, unless the above Detailed Description section explicitly defines such terms. Accordingly, the actual scope of the invention encompasses not only the disclosed examples, but also all equivalent ways of practicing or implementing the invention under the claims. 
     While certain aspects of the invention are presented below in certain claim forms, the applicant contemplates the various aspects of the invention in any number of claim forms. For example, while only one aspect of the invention is recited as a means-plus-function claim under 35 U.S.C. §112, sixth paragraph, other aspects may likewise be embodied as a means-plus-function claim, or in other forms, such as being embodied in a computer-readable medium. (Any claims intended to be treated under 35 U.S.C. §112, ¶ 6 will begin with the words “means for.”) Accordingly, the applicant reserves the right to add additional claims after filing the application to pursue such additional claim forms for other aspects of the invention.