Abstract:
A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This is a continuation-in-part of pending application Ser. No. 11/787,716, filed Apr. 17, 2007. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a method of a multiplier operation, and in particular relates to a method of operation of a low-error reduced-width multiplier. 
     BACKGROUND OF THE INVENTION AND PRIOR ART 
     Multiplier is one of the most common basic operations for digital signal processing. When performing a digital signal processing, in order to prevent data&#39;s bit width from overflow as the operation burden increases, therefore multiplication operation usually incorporates a reduced (or fixed) width characteristic so as to prevent the occurrence of the case of the numerical overflow during the process of the operation. Generally speaking, the reduced-width characteristic is commonly realized by employing a post-truncated multiplier, where the truncation operation is executed at the output of the multiplier in order to maintain the fixed width of bits. In contrast to the post-truncated multiplier, the direct-truncated multiplier only executes a partial product accumulation on the portions that are willing to preserve the output bit of the multiplication so as to reduce the computation complexity; but, however, usually it will result in a relatively large error. 
     For the direct-truncated fixed-width multiplier, the bit width of input/output is the same; and for the fixed-width multiplier, the error is compensated by adding a number. However, error compensation methods proposed in prior arts are only applicable for multipliers that utilize a single partial product generating approach, and most of them need to be accompanied with an acquisition of a large amount of simulation auxiliary compensated terms. Because of the lack of effective analysis method, it is difficult to further apply to the system-level analysis. Therefore, a direct-truncated multiplier of the known art only realizes the partial product accumulation corresponding to the remaining parts after truncation. 
     Figure depicts a circuit block diagram of a well-known multiplier, in which the bit width of an input data A is n 1 , and the bit width of an input data B is n 2 . The product of these two inputs has a bid width of (n 1 +n 2 ) bits. This product must be truncated by the truncator (denoted by T) in order to keep the bit width at n (n£n 1 +n 2 ) bits and therefore to prevent overflow. 
     Although there are many kinds of method being proposed in the literature to compensate for this error, however, they all are applicable for those multipliers which utilize a certain partial product generating method. Hereafter a survey of patent literature and non-patent literature relevant to the present invention will be given and analyzed as follows:
     1. R.O.C. Patent No. 396321, Jul. 1, 2000, “Low-Error Fixed-Width 2&#39;s Complement Parallel Multiplier.” This patent application only provided a compensation for a 2&#39;s complement fix-width multiplier, which may dynamically generate a quantity of compensation in accordance with the input value of the multiplier, but, however, due to the lack of theoretic analysis, it is not able to mitigate errors in accordance with the statistical characteristics of the input data, and furthermore it is not applicable for the multipliers that adopt different partial products generating methods.   2. R.O.C. Patent No. 484092, Apr. 21, 2002, “A Reducible Bit Length Low-Error Multiplier.” This patent application provided a dynamic compensation method for a 2&#39;s complement and modified Booth multipliers. The mechanism for generating an amount of compensation is simple, but is not able to efficiently compensate for errors.   3. K. K. Parhi, J. G. Chung, K. C. Lee, and K. J. Cho, “Low-Error Fixed-Width Modified Booth Multiplier,” Dec. 20, 2005, U.S. Pat. No. 6,978,426B2. This patent application provided a dynamic compensation method for the modified Booth multiplier, which is able to effectively compensate for errors; but, however, the hardware complexity for generating a quantity of compensation may increase as the width of the input of the multiplier become larger.   4. Y. C. Lim, “Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications,”  IEEE Trans. Computers , Vol. 41, pp. 1333-1336, October 1992. This non-patent literature proposed generating a constant of compensation via a preliminary analysis, and also pointed out the concept of dynamic compensation, but, however, is lack of a detailed and concrete analysis and realization method.   5. M. J. Schulte and E. S. Jr., “Truncated Multiplication with Correction Constant,” in  Workshop on VLSI Signal Processing , October 1993, pp. 388-396.   6. S. S. Kidambi, F. El-Guibaly, and A. Antoniou, “Area-Efficient Multipliers for Digital Signal Processing Applications,”  IEEE Trans. Circuits Syst. II , Vol. 43, pp. 90-95, February 1996.
       (A) The non-patent literature, item 5 and item 6 mentioned above, both proposed a constant compensation method, which is not able to effectively compensate for errors.   (B) The non-patent literature, item 4 to item 6 mentioned above, put a special emphasis on the constant compensation method, which, besides being not able to effectively compensate for errors, it is also difficult to change the way of analysis in accordance with different generating method for partial products.   
       7. T. B. Juang and S. F. Hsiao, “Low-Error Carry-Free Fixed-Width Multipliers with Low-Cost Compensation Circuits,”  IEEE Trans. Circuits Syst. II , Vol. 52, No. 6, pp. 299-303, June 2005. This non-patent literature provided a dynamic compensation mechanism only for signed-magnitude modified Booth multiplier, and did not provide any other multiplication compensation method for different partial products generating methods.   8. L. D. Van and C. C. Yang, “Generalized Low-Error Area-Efficient Fixed-Width Multipliers,”  IEEE Trans. Circuits Syst. I , Vol. 52, No. 8, pp. 1608-1619, August 2005. This non-patent literature can be treated as a derivative of the above-mentioned patent literature item 1, but these two methods were designed only for 2&#39;s complement fixed-width multipliers, and are not appropriate for other multipliers employing different partial products generating method.   

     SUMMARY OF THE INVENTION 
     One of the objectives of the present invention is to provide an operational method of a low-error reduced-width multiplier for reducing computational complexity and compensating for truncation errors, which is applicable to different types of multipliers. 
     Another objective of the present invention is to provide a low-error reduced-width multiplier for reducing computational complexity and compensating for truncation errors. 
     Another objective of the present invention is to provide a method for carry estimation of truncated-width multiplier, comprising: (a) processing a n-bit Baugh-Wooly 2&#39;s complement multiplier and an input multiplication of A×B, where 
                 A   =         -     a     n   -   1         ⁢     2     n   -   1         +       ∑     j   =   0       n   -   2       ⁢       a   j     ⁢     2   j             ;     B   =         -     b     n   -   1         ⁢     2     n   -   1         +       ∑     i   =   0       n   -   2       ⁢       b   i     ⁢     2   i               ,         
to generate a first group of n partial products and a second group of n partial products; (b) associating each partial product of the first group with a most significant part (MSP) and associating each partial product of the second group with a least significant part (LSP); (c) dividing the least significant part (LSP) into two groups, a first least significant group of
 
               β   =       ∑     i   =   0       n   -   1       ⁢     P     i   ,     n   -   i   -   1             ,         
P i,j =a j b i , which contains a plurality of elements (P i,j ) of partial product of P i,j =a j b i  depending on input information (a j , b i ), and a second least significant group containing n−1 bits; (d) truncating the second least significant group and using a compensating circuit to generate a estimated group of
 
             λ   =       ∑     i   =   0       n   -   2       ⁢       ∑     j   =   0       n   -   i   -   2       ⁢       P     i   ,   j       ⁢     2     j   -   n                   
in accordance with the input information implied in the first least significant group (β); (e) generating a carry estimation value of
 
               σ   =       2     n   -   z   +   1       ⁢       ⌊       β   2     +   λ     ⌋     r         ,         
where └x┘ r  is a round operation for rounding x to its nearest number, for the most significant part (MSP) in accordance with the first least significant group (β) and a estimated group (λ); and (f) using an adder circuit to accumulate the most significant part (MSP) and the carry estimation value.
 
     Another objective of the present invention is provided with a method for carry estimation of truncated-width multiplier, comprising: (a) processing a Booth-encoded multiplier and reducing the number of row in partial product of an input of B={b n−1 , b n−2 , . . . , b 0 } where b −1  is equal to 0, into 
               ⌊     n   2     ⌋     ;         
(b) converting an input multiplication of A×B into an another multiplication of A×y, where y={y └n/2┘−1 , y └n/2┘−2 , . . . , y 0 }), to generate a first group of n partial products and a second group of n partial products; (c) associating each partial product of the first group with a most significant part (MSP) and associating each partial product of the second group with a least significant part (LSP); (d) dividing the least significant part (LSP) into two groups, a first least significant group of β={P 0,n−1 , P 1,n−3 , . . . , P └n/2┘−t,1 }, which contains a plurality of elements (P i,j ) of partial product (P ij =a j y i ) depending on input information (a j , y i ) and a second least significant group containing n−1 bits; (e) truncating the second least significant group and using a compensating circuit to generate a carry estimation value of
 
               σ   =       2   n     ⁢       ⌊       β   2     +   λ     ⌋     r         ,         
where └x┘ r  is a round operation for rounding x to its nearest number, for the most significant part (MSP) in accordance with the input information implied in the first least significant group (β) and a estimated group (λ) and (f) using an adder circuit to accumulate the most significant part (MSP) and the carry estimation value in accordance with the first least significant group (β) and the estimated group (λ).
 
     To achieve the above-mentioned objectives, in accordance with a first aspect of the present invention, there is provided an operational method of a low-error reduced-width multiplier for reducing computational complexity and compensating for truncation errors, comprising the following steps: dynamically generating a compensation term by using an input value of a multiplier; and an accumulating operation for which the part that is set to be the truncated part in the multiplier is omitted, while the compensation term is used for compensation, in order to reduce the width. 
     Furthermore, to achieve the above-mentioned objectives, in accordance with a second aspect of the present invention, there is provided a low-error reduced-width multiplier, in which the multiplier can reduce the width by an accumulating operation for which the part that is set to be the truncated part in the multiplier is omitted, while the compensation term dynamically generated by an input value is used for compensation. 
     Therefore, because of the utilization of an accumulating operation that use a dynamically generated compensation term to compensate for the part that is set to be a truncated part, the present invention is able to reduce the computational complexity and compensate for truncation errors, and is also applicable to different types of multipliers. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For the purpose that the said and other objectives, characteristics, and advantages of the present invention can be clearly seen, and be easily and obviously understood, preferred embodiments of the present invention are subsequently described by referring to the enclosing drawings, wherein: 
         FIG. 1  depicts a circuit block diagram of a prior art multiplier. 
         FIG. 2  depicts a circuit block diagram for an n-bit low-complexity reduced-width multiplier  200  proposed in a preferred embodiment of the present invention. 
         FIG. 3  depicts a partial product generating diagram for an n-bit low-complexity reduced-width multiplier  200 . 
         FIG. 4  depicts another partial product generating diagram for an n-bit multiplier  200 . 
         FIG. 5  and  FIG. 6  depict, respectively, three kinds of diagrams of compensation generating formulae for used in different bit-width 2&#39;s complement multipliers. 
         FIG. 7  depicts three kinds of diagrams of compensation generating formulae for different bit-width modified Booth multipliers. 
         FIG. 8  and  FIG. 9  depict a first preferred embodiment for estimating a carry-in of a truncated-width multiplier, wherein FA indicated a full adder, HA indicated a half adder, a 0 ˜a 3  and b 0 ˜b 3  indicated multiplier&#39;s inputs and p 4 ˜p 7  indicated final multiplication results. 
         FIG. 10  depicts a second preferred embodiment for estimating a carry-in of a truncated-width multiplier, wherein FA indicated a full adder, HA indicated a half adder, a 1 ˜a 3  and b 1 ˜b 3  indicated multiplier&#39;s inputs and p 4 ˜p 7  indicated final multiplication results, wherein FA indicated a full adder, HA indicated a half adder. 
         FIG. 11  depicts a third preferred embodiment for estimating a carry-in of a truncated-width multiplier, wherein FA indicated a full adder, HA indicated a half adder, P 07 , P 15 , P 23  and P 31  indicated the information included in the first least significant group (β). 
         FIG. 12  depicts a fourth preferred embodiment for estimating a carry-in of a truncated-width multiplier, wherein FA indicated a full adder, HA indicated a half adder, P 07 , P 15 , P 23  and P 31  indicated the information included in the first least significant group (β). 
         FIG. 13  depicts a simplified circuit diagram for an orthogonal frequency division multiplexing (OFDM) system. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following, preferred embodiments of the present invention are subsequently described by referring to the enclosing drawings. 
     The present invention discloses a dynamic generation of compensation and estimation analysis method that is applicable to different bit-width and different parts of products generating procedure of a multiplier. By utilizing this analysis method, it is able to further provide a system level analysis so as to provide a design choice while considering the design cost such as complexity and compensation accuracy. In accordance with the present invention, to achieve low complexity, a direct-truncated multiplier together with a compensating circuit for dynamically generating a quantity of compensation are adopted, where the mechanism for dynamically generating compensation still fulfills the low-error and low-complexity requirements. In connection with those requirements, distribute the correlations among the elements of the products, and observe parts of the partial products to calculate and arrange the state expectation value of the partial products to serve as a quantity of compensation needed in the dynamic compensation. Therefore, the analysis method in accordance with the present invention has a low complexity, and is applicable to the multipliers employing different kinds of partial products generating methods. Hence, under the condition that the statistical characteristics of the input signals to the multiplier are known, it offers much more accurate compensation, and can further provide a system-level truncation error analysis. 
     The present invention can be used in LAN\WAN, DVB-T/H, xDSL and high-speed low-power signal processors (such as the kernel processor of fast Fourier transform (FFT) or digital filter, equalizer). 
       FIG. 2  depicts a circuit block diagram for an n-bit low-complexity reduced-width multiplier  200  proposed in a preferred embodiment of the present invention. As shown in  FIG. 2 , a direct product of an A having n 1  bits and a B having n 2  bits results in a product of n bits; in the mean time, a compensation C is added to the product in order to correct the induced error while decreasing the complexity. The computational complexity and hardware cost of a low-complexity reduced-width multiplier  200  can be reduced by omitting the partial products accumulation corresponding to the last part of the bits.  FIG. 3  depicts a partial product generating diagram for an n-bit low-complexity reduced-width multiplier  200 . Taking the product of A×B as an example, if 
               A   =         -     a     n   -   1         ⁢     2     n   -   1         +           a   ∘       n   -   2         j   =   0       ⁢     a   j     ⁢     2   j           ,     B   =         -     b     n   -   1         ⁢     2     n   -   1         +           a   ∘       n   -   2         i   =   0       ⁢     b   i     ⁢     2   i           ,         
and P ij =a j b i . Then the result of the multiplication can be represented as the following equation:
 
               A   ×   B     =       MSP   +       2   n     ⁢     (       [       β   2     +   λ     ]     r     )         ≈     MSP   +       2   n     ⁢     (     [       1   2     ⁢       (       2   ⁢   β     +     2   ⁢   λ     -   1     ]     r       )                   
where [ ] r  denotes round-off.
 
     The multiplier  200  provided by the present invention is able to reduce the complexity by omitting the partial products accumulating operation of λ, while adding an estimation of λ to compensate for the error induced by this simplification. Because any two elements P ij   1 =a j b i   1 , P ij =a j b i  that construct the partial product are both related to a j , and P ij   1 =a j   1 b i   1 , P ij =a j b i  are related to b i , therefore, by observing the partial product accumulation value of the nth bit 
               (     B   =         P     0   ,     n   -   1         +     P       n   -   1     ,   0       +       ∑     i   =   1       n   -   2       ⁢     P     i   ,     n   -   i   -   1             =       P     0   ,     n   -   1         +     P       n   -   1     ,   0       +       ∑     i   =   1       n   -   2       ⁢     P       n   -   j   -   1     ,   j               )     ,         
and by substituting P ij , which constitute λ, with E[P ij |P i,n−i−1, ], or by substituting P ij , which constitute λ, with E[P ij |P n−j−1,j ], it is possible to estimate the value of λ that has been omitted to further compensate for this error. The quantity of compensation provided by the present invention is obtained by observing β, which corresponds to a quantity of compensation that changes dynamically in accordance with the input to an multiplier.
 
     The multiplier provided by the present invention is capable of changing its omitting ratio of the partial product in accordance with the requested amount of error and complexity requirement of its applications or systems.  FIG. 4  depicts another partial product generating diagram for an n-bit multiplier  200 , where the number of percentage occupied by λ can be determined by the parameter z. The compensation estimation method proposed by the present invention can be used with different numbers of the parameter z. The present invention also takes the 2&#39;s complement multiplier and the modified Booth multiplier as illustrating examples and provides respectively three types of compensation estimation methods for each of the multipliers.  FIG. 5  and  FIG. 6  depict, respectively, three kinds of diagrams of compensation generating formulae for used in different bit-width 2&#39;s complement multipliers.  FIG. 7  depicts three kinds of diagrams of compensation generating formulae for different bit-width modified Booth multipliers. The present invention further provides an analysis method for analyzing the compensation C in accordance with the statistical characteristics of the input signals A, B of the multiplier. 
     According to the present invention, a method for carry estimation of a truncated-width multiplier is provided and comprising: (a) processing a n-bit Baugh-Wooly 2&#39;s complement multiplier and an input multiplication of A×B, where 
                 A   =         -     a     n   -   1         ⁢     2     n   -   1         +       ∑     j   =   0       n   -   2       ⁢       a   j     ⁢     2   j             ;     B   =         -     b     n   -   1         ⁢     2     n   -   1         +       ∑     i   =   0       n   -   2       ⁢       b   i     ⁢     2   i               ,         
with a j , b i ε{0,1}), to generate a first group of n partial products and a second group of n partial products; (b) associating each partial product of the first group with a most significant part (MSP) and associating each partial product of the second group with a least significant part (LSP); (c) dividing the least significant part (LSP) into two groups, a first least significant group of
 
               β   =       ∑     i   =   0       n   -   1       ⁢     P     i   ,     n   -   i   -   1             ,         
P i,j =a j b i , which contains a plurality of elements P i,j  of partial product P i,j =a j b i  depending on input information a j , b i , and a second least significant group containing n−1 bits; (d) truncating the second least significant group and using a compensating circuit to generate a estimated group of
 
             λ   =       ∑     i   =   0       n   -   2       ⁢       ∑     j   =   0       n   -   i   -   2       ⁢       P     i   ,   j       ⁢     2     j   -   n                   
in accordance with the input information implied in the first least significant group β; (e) generating a carry estimation value of
 
               σ   =       2   n     ⁢       ⌊       β   2     +   λ     ⌋     r         ,         
where └x┘ r  is a round operation for rounding x to its nearest number, for the most significant part (MSP) in accordance with the first least significant group β and a estimated group λ; and (f) using an adder circuit to accumulate the most significant part (MSP) and the carry estimation value.
 
     According to abovementioned method and referring to  FIGS. 8˜9 , the compensating circuit including: a first cell  81  that comprises a half adder and a NAND logical gate receiving the input information (a n , b 0 ); a plurality of second cells  84 , each of the second cells  84  comprises a full adder and an AND logical gate receiving the input information (a n−1 , a n−2 , . . . a 1 , b 1 , b 2 , . . . b n−1 ); a third cell  82  that comprising a full adder and a NAND logical gate receiving the input information (a 0 , b n ); and a fourth cell  85  that comprises a plurality of half adders for receiving the input information and respectively outputting the estimated group (λ) composed of 
               2     -   1       ⁢       ∑     j   =   0       n   -   2       ⁢     a   j             
to the second cells  84  and the third cell  82 . A total number of the first cell, the second cells and the third cell are equal to n, and the second cells  84  are connected between the first cell  81  and the third cell  84 . The carry estimation value σ is estimated as
 
             σ   =       [       1   2     ⁢     (     β   +       1   2     ⁢       ∑     j   =   0       n   -   2       ⁢     a   j           )       ]     r           
when conditional expectation values are E[P ij |a j =0]=0 and
 
                 E   ⁡     [         P   ij     |     a   j       =   1     ]       =     1   2       ,         
where P ij  is generated from a j ×b i  and estimated as
 
     
       
         
           
             
               
                 
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     Alternatively, referring to  FIG. 10 , according to a second preferred embodiment of the present invention, the compensating circuit includes a plurality of second cells  84 , each of the n−2 second cells  84  comprising a full adder and an AND logical gate receiving the input information (a n−1 , a n−2 , . . . a 1 , b 1 , b 2 , . . . b n−1 ) and an expectation value ‘1’; the estimated group λ is composed of 
                 2     -   1       ⁢       ∑     j   =   0       n   -   2       ⁢       (         α   j     3     +     1   6       )     ⁢     (     1   -     2     -     (     n   -   1   -   j     )           )           ;         
and the carry estimation value σ is estimated as
 
             σ   =         ∑     j   =   1       n   -   2       ⁢     α   j       +       [   δ   ]     r             
when conditional expectation values of any partial product conditioned on α j  are
 
                 E   ⁡     [         P   ij     |     α   j       =   0     ]       =         1   6     ⁢           ⁢   and   ⁢           ⁢     E   ⁡     [         P   ij     |     α   j       =   1     ]         =     1   2         ,         
where α j =P n−1−j,j ,
 
             δ   =         α   0     2     +         α   n     -   1     2     +   λ   -       1   2     ⁢       ∑     j   =   1       n   -   2       ⁢     α   j                 
and a conditional expectation P ij  is determined as
 
     
       
         
           
             
               
                 
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     Furthermore, the present invention is provided with an another method for carry estimation of a truncated-width multiplier, the method comprising: (a) processing a Booth-encoded multiplier and reducing the number of row in partial product of an input of B={b n−1 , b n−2 , . . . , b 0 }, where b −1  is equal to 0, into 
               ⌊     n   2     ⌋     ;         
(b) converting an input multiplication of A×B into an another multiplication of A×y, where y={y └n/2┘−1 , y └n/2┘−2 , . . . , y 0 }, to generate a first group of n partial products and a second group of n partial products; (c) associating each partial product of the first group with a most significant part (MSP) and associating each partial product of the second group with a least significant part (LSP); (d) dividing the least significant part (LSP) into two groups, a first least significant group of β={P 0,n−1 , P 1,n−3 , . . . , P └n/2┘−1,1 }, which contains a plurality of elements P i,j  of partial product P ij =a j y i  depending on input information (a j , y i ) and a second least significant group containing n−1 bits; (e) truncating the second least significant group and using a compensating circuit to generate a carry estimation value of
 
               σ   =       2   n     ⁢       ⌊       β   2     +   λ     ⌋     r         ,         
where └x┘, is a round operation for rounding x to its nearest number, for the most significant part (MSP) in accordance with the input information implied in the first least significant group β and a estimated group λ; and (f) using an adder circuit to accumulate the most significant part (MSP) and the carry estimation value in accordance with the first least significant group β and the estimated group λ.
 
       FIG. 11  depicts a third preferred embodiment for estimating a carry-in of a truncated-width multiplier, wherein FA indicated a full adder, HA indicated a half adder, P 07 , P 15 , P 23  and P 31  indicated the information included in the first least significant group β. 
     In this preferred embodiment, the compensating circuit  111  includes: a plurality of AND logical gates for receiving an input information of the first least significant group β and outputting the estimated group λ composed of 
                 2     -   1       ⁢     (       β   10     +       3   20     ⁢     ⌈     n   2     ⌉         )       ;         
and n/4 full adders for receiving the information of the first least significant group β and the estimated group λ, and outputting the carry estimation value to the Booth-encoded multiplier, where P ij  is estimated by conditional expectations of E[P ij |β i ], where
 
                 E   ⁡     [         P   ij     |     β   i       =   0     ]       =     3   10       ,       E   ⁡     [         P   ij     |     β   i       =   1     ]       =     1   2       ,     
     ⁢       E   ⁡     [         n   i     |     β   i       =   0     ]       =     3   10       ,       E   ⁡     [         n   i     |     β   i       =   1     ]       =     1   2             
and n i  in Booth encoding equals to 1 only when y i &lt;0
 
       FIG. 12  depicts a fourth preferred embodiment for estimating a carry-in of a truncated-width multiplier, wherein FA indicated a full adder, HA indicated a half adder, P 07 , P 15 , P 23  and P 31  indicated the information included in the first least significant group β. 
     In this preferred embodiment, the compensating circuit  121  includes n/4 full adders for receiving the input information of the first least significant group β and the estimated group λ composed of 
                 2     -   1       ⁢       ⌊     (       3   8     ⁢     ⌈     n   2     ⌉       )     ⌋     r       ,         
and outputting the carry estimation value to the Booth-encoded multiplier, where P ij  is related to α j  and estimated by conditional expectations of E[P ij |α j =a j y i ], where
 
               E   ⁡     [         P   ij     |     α   j       =   1     ]       =       E   ⁡     [         P   ij     |     α   j       =   0     ]       =       E   ⁡     [     n   i     ]       =     3   8               
and n i  in Booth encoding equals to 1 only when y i &lt;0.  FIG. 13  depicts a simplified circuit diagram for an orthogonal frequency division multiplexing (OFDM) system, where the information source is inputting to the modulator  1301 , passing through an IFFT (Inverse Fast Fourier Transform) unit  1302 , transferring from RF (radio frequency) unit  1303  through the channel  1304  to RF unit  1305 , and further inputting to FFT (Fast Fourier Transform) unit  1308  through the digital filter  1306  and the synchronizer  1307 , and then generating received data by adjusting the signal frequency using the equalizer  1309  and further processing by the demodulator  1310 , in which a great amount of complex multipliers needed in the required correlation calculation of the synchronization of the timing sequence and the calculation and compensation of the frequency offset of the digital filter, equalizer, and synchronizer in the above-mentioned system can all be implemented by the low-complexity, low-error multipliers provided by the present invention.
 
     To sum up, from the previous description, the low-error reduced-width multiplier and it operation method provided in the present invention, because of the utilization of an accumulating operation that use a dynamically generated compensation term to compensate for the part that is set to be a truncated part, is able to reduce the computational complexity and compensate for truncation errors, and therefore is also applicable to different types of multipliers having different bit widths and using different partial products generating methods. 
     Although the present invention is disclosed in a plurality of preferred embodiments described above, the inventive idea should not be limited only to those. It will be understood by those skilled in the art that various other changes in the form and details may be made without departing from the spirit and scope of the present invention. It is to be understood that various changes may be made in adapting to different embodiments without departing from the broader concepts disclosed herein and comprehended by the claims that follow.