Abstract:
A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.

Description:
TECHNICAL FIELD  
         [0001]    The invention relates to a method for storing a temperature threshold in an integrated circuit. The invention also relates to a method for storing a temperature threshold in a dynamic random access memory and a method of modifying dynamic random access memory operation in response to temperature. The invention also relates to a programmable temperature sensing circuit and a memory integrated circuit.  
         BACKGROUND OF THE INVENTION  
         [0002]    It is frequently desired to read and write data from dynamic random access memory (DRAM) integrated circuits (ICs). As the amount of data stored in each DRAM IC increases, there is need to be able to write data into, and read data out of, DRAMs with progressively higher bandwidth. This need requires new kinds of data input/output (I/O) systems and is not easily met.  
           [0003]    Previous generations of DRAMs have included fast page mode DRAM and extended data output DRAM. These devices capture input data and drive output data at the falling edge of a column address strobe* (CAS*) signal, where the “*” indicates complement.  
           [0004]    In synchronous DRAM (SDRAM), the data trigger point for read and write operations is the rising edge of the clock signal. These conventional DRAMs are referred to as single data rate (SDR) devices. The peak bandwidth (megabytes/second) of a memory system with such memories is given as:  
           (memory system bus width)×(clock frequency)  (Eq. 1)  
           [0005]    Providing a higher peak bandwidth from a SDR DRAM system thus requires making the clock as fast as possible and expanding the system bus width to be as wide as possible.  
           [0006]    However, the clock driver has to drive all DRAMs in the memory system in parallel. Accordingly, higher clock speeds may be difficult to achieve in practice. Additionally, because increasing the bus width also requires greater area on the board holding the DRAM system, it is not easy to increase the peak bandwidth of a SDR DRAM system by increasing bus width.  
           [0007]    Double data rate (DDR) DRAM systems are a more attractive way to get a higher data rate and thus greater system bandwidth. In DDR systems, both the rising and falling edges of the clock signal or data strobe signal are trigger points for read and write operations. DDR DRAM systems thus provide double the peak data rate of comparable SDR DRAM systems for the same clock speed and bus width, but require increased timing accuracy.  
           [0008]    In turn, new kinds of applications in which DRAMs are used for information storage and retrieval have been developed. These include applications involving PCs, servers, workstations, graphics processors and multimedia processors. As these kinds of applications have developed, needs for progressively larger amounts of data storage and retrieval, and therefore for more rapid data storage and retrieval, have also developed. In order to more rapidly access information stored in DRAMs, new kinds of interface architectures have been developed, including DDR I/O systems.  
           [0009]    A differential clock (CLK and CLK*) scheme is used in DDR DRAM memory systems to address the increased timing accuracy requirements. However, there is still a need to synchronize internal clock signals with clocking signals in the circuitry external to the DDR DRAM. Further, because transitions in these clock signals at which data are transferred occur substantially more frequently than those of CAS* signals in SDR DRAMs, the timing tolerances are much tighter. As a result, there is need to maintain tighter timing tolerances in generating internal clocking signals CLK and CLK* that are synchronized with external clocking signals XCLK.  
           [0010]    The clock speeds used in DDR DRAMs are increased relative to clock speeds for SDR DRAMs. One effect of the increased clock speed is to generate more heat in the DDR DRAM. In turn, timing of signals within the chip is modified by changes in the operating temperature of the DDR DRAM. When the timing of the signals within the DDR DRAM is shifted by too great an amount, errors occur in exchanging data between the DDR DRAM and circuitry external to the DDR DRAM.  
           [0011]    Additionally, processing variations occurring during manufacturing of DRAMs can affect delays within a given DRAM. In turn, this may lead to situations where nominally identical DRAMs show different timing behavior and behavior variations over temperature. Moreover, some specific applications may require different temperature behavior than others.  
           [0012]    Further, storage times for data stored in DRAM memory cells are a decreasing function of temperature, as is discussed in more detail in U.S. Pat. Nos. 5,278,796 and 5,276,843, which are assigned to the same assignee as the present invention and which are incorporated herein by reference. As the DRAM temperature increases, the time period during which data stored in memory cells in the DRAM are valid decreases. As a result, excessive temperatures can lead directly to loss of data stored in DRAMs.  
           [0013]    What is needed is a capability for detecting the temperature of DRAMs that allows I/O operations to be slowed or suspended when the DRAM temperature exceeds a first threshold temperature and that allows I/O operations to speed up or resume when the temperature of the DRAM drops below a second threshold temperature. What is further needed is an ability to modify threshold temperatures and provide nonvolatile memory for storing modified threshold temperatures in DRAMs in response to measured performance criteria or specific application requirements.  
         SUMMARY OF THE INVENTION  
         [0014]    The invention provides a method of storing a temperature threshold in an integrated circuit. The method includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing antifuses in the comparison circuit.  
           [0015]    In another aspect, the present invention includes a method for storing a temperature threshold in a dynamic random access memory (DRAM). The method includes measuring operating parameters of the DRAM versus temperature, calculating a maximum temperature at which the DRAM performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a nonvolatile memory formed from fusable devices in a comparison circuit in the DRAM.  
           [0016]    In yet another aspect, the present invention includes a method of modifying dynamic random access memory operation in response to temperature. The method includes measuring an operating temperature of the memory and comparing the measured operating temperature to a temperature threshold stored in a nonvolatile memory. The temperature threshold was previously stored by blowing fusable devices in the nonvolatile memory. The method also includes reducing a data input/output rate for the memory when the measured operating temperature exceeds the temperature threshold and maintaining the data input/output rate for the memory when the measured operating temperature does not exceed the temperature threshold.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    Preferred embodiments of the invention are described below with reference to the following accompanying drawings.  
         [0018]    [0018]FIG. 1 is a simplified block diagram of a dynamic random access memory circuit including a temperature detection circuit described below with reference to FIG. 2, in accordance with an embodiment of the present invention.  
         [0019]    [0019]FIG. 2 is a simplified block diagram of the temperature detection circuit of FIG. 1, in accordance with an embodiment of the present invention.  
         [0020]    [0020]FIGS. 3A and 3B provide simplified schematic diagrams of current mirror circuits, in accordance with the prior art.  
         [0021]    [0021]FIG. 4 is a simplified schematic diagram of an adjustable gate width field effect transistor, in accordance with an embodiment of the present invention.  
         [0022]    [0022]FIG. 5 is a simplified schematic diagram of a fusing circuit for storing a temperature threshold, in accordance with an embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]    This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the Progress of Science and useful Arts” (Article 1, Section 8).  
         [0024]    [0024]FIG. 1 is a simplified block diagram of a dynamic random access memory circuit  20  including a temperature sensing circuit  21 , as described below with reference to FIG. 2, in accordance with an embodiment of the present invention. In one embodiment, the memory circuit  20  is a DDR DRAM.  
         [0025]    The memory circuit  20  includes an array  22  of memory cells organized into rows and columns, a row addressing circuit  24 , a column addressing circuit  26 , sense amplifiers  28  and an I/O bus  30  coupling the memory array  22  to pins (not shown) of the memory circuit  20  and thus to an processor  32  such as a computer (not shown), microprocessor or other device. In one embodiment, the memory circuit  20  has an I/O bus  30  that is two bytes wide and that can operate at clock speeds up to at least 400 MHz, providing a data I/O bandwidth of 800 megabytes per second.  
         [0026]    The temperature sensing circuit  21  of FIG. 2 includes an output signal line  34  providing an OVERTEMPERATURE output signal to the processor  32  or other device external to the memory circuit  20 .  
         [0027]    When the memory circuit  20  is being manufactured, a variety of tests are carried out to verify proper operation of the row addressing circuit  24 , the column addressing circuit  26 , the sense amplifiers  28  and of memory cells in the memory array  22 . Tests are also carried out to characterize operation of the memory circuit  20  for different power supply voltages, clock frequencies and the like and to characterize operation of the memory circuit  20  at different temperatures. Results from these tests are then used to repair portions of the memory circuit  20 , to sort memory circuits  20  into “speed bins” or ranges of clock speeds over which particular memory circuits  20  operate etc. Results from these tests may also be programmed into the temperature sensing circuit  21  by blowing fusable devices to set a temperature setpoint based on measured characteristics of that memory circuit  20 , as is explained below in more detail with reference to FIGS.  2 - 5 .  
         [0028]    In normal operation, data coupled from the processor  32  through the I/O bus  30  may be written to the memory array  22 . The processor  32  may also read data from the memory array  22  through the I/O bus  30 .  
         [0029]    When the temperature of the memory circuit  20  rises above the setpoint that has been programmed into the temperature sensing circuit  21 , an OVERTEMPERATURE signal is generated and is communicated to the processor  32  via the output signal line  34 . The OVERTEMPERATURE signal indicates that data coming from or being written to the memory circuit  20  may be compromised by, for example, temperature-induced clock skew problems.  
         [0030]    In one embodiment, the processor  32  may reduce a clock speed for clocking data into or out from the memory circuit  20  in response to presence of the OVERTEMPERATURE signal on the output line  34 . In one embodiment, the processor  32  may suspend data read or data write operations in response to presence of the OVERTEMPERATURE signal on the output line  34 .  
         [0031]    When the temperature of the memory circuit  20  drops below the setpoint temperature that is programmed into the temperature sensing circuit  21 , the OVERTEMPERATURE signal on the output signal line  34  indicates that the temperature has dropped and that the memory circuit  20  may be operated at the maximum clock frequency without temperature-induced compromise of data integrity. The processor  32  may then resume or speed up data input or output operations with the memory circuit  20 .  
         [0032]    [0032]FIG. 2 is a simplified block diagram of the temperature detection circuit  21  of FIG. 1, in accordance with an embodiment of the present invention. The temperature detection circuit  21  may be realized in a variety of different ways. In general, temperature setpoint detector circuits  21  employ first  42  and second  44  current (or voltage) generators, where the first  42  and second  44  current generators provide output parameters such as currents I 1  and I 2  that vary differently with temperature.  
         [0033]    The temperature setpoint circuit  21  of FIG. 2 also includes a scaling circuit  46  coupled to a nonvolatile memory  47 . In one embodiment, the scaling circuit  46  is formed from, for example, conventional operational amplifiers having gains set using negative feedback. In one embodiment, the scaling circuit  46  is formed using conventional current (or voltage) dividers. In one embodiment, the scaling circuit  46  is formed using current mirrors, with gate area ratios determining relationships between input currents I 1  and I 2 , and output currents I 1OUT  and I 2OUT , respectively.  
         [0034]    The temperature setpoint circuit  21  of FIG. 2 also includes a comparator circuit  48 . The comparator circuit  48  compares the currents I 1OUT  and I 2OUT  and generates an output signal V OUT  providing an indication of which of the currents I 1OUT  and I 2OUT  is larger. The output signal V OUT  then may be used to provide the OVERTEMPERATURE signal on the output line  34  of FIG. 1.  
         [0035]    Examples of temperature sensing circuits  21  suitable for manufacturing as part of an integrated circuit include, for example, a temperature setpoint detection circuit discussed in U.S. Pat. No. 5,873,053, which is incorporated herein by reference. This circuit compares two subthreshold FET drain currents, where each of the currents is derived from a respective one of two FETs having different geometries and that are provided with different gate voltages. The geometries and gate voltages are chosen so that the two currents will have the same magnitude at a setpoint temperature, with one of the two currents being larger than the other below the setpoint temperature and the other of the two currents being larger above the setpoint temperature. This type of temperature setpoint detection circuit uses two current sources having the same sign, but different slopes, of temperature coefficient.  
         [0036]    Another type of temperature sensing circuit  21  is described in U.S. Pat. No. 4,768,170, which is incorporated herein by reference. This temperature setpoint detection circuit also uses two current sources having the same sign, but different slopes, of temperature coefficient. Currents from the two current sources are compared in order to determine when a setpoint temperature has been exceeded. Examples of semiconductor devices employing other types of temperature sensing circuits  21  are described in U.S. Pat. Nos. 5,703,521; 5,500,547; 5,485,127; 5,213,416 and 4,931,844, all of which are incorporated herein by reference.  
         [0037]    Other kinds of temperature sensing circuits  21  may use current sources having opposite slopes of temperature coefficient. For example, many kinds of resistors have a positive temperature coefficient of resistance (i.e., resistance increases with increasing temperature). As a result, a voltage drop across a resistor that is biased by a constant current source will increase with temperature. In contrast, a voltage drop across a p-n diode that is forward biased by a constant current source decreases with temperature.  
         [0038]    Accordingly, when a first current source (e.g., current source  42 ) provides a current that is proportional to a voltage drop across a resistor that is biased by a constant current source, and a second current source (e.g., current source  44 ) provides a current that is proportional to a voltage drop across a diode that is forward biased by another constant current source, the first and second current sources will have opposite slopes of current output versus temperature. Alternatively, the resistor and the diode may be biased by currents having a known relationship to each other.  
         [0039]    In all of these arrangements, when the currents I 1  and I 2  from the two current sources are appropriately scaled and offset, the currents I 1OUT  and I 2OUT  will be equal at a threshold temperature, one will be greater than the other below the threshold temperature and the other will be greater above the threshold temperature. The scaled and offset currents I 1OUT  and I 2OUT , or voltages derived from these currents, are compared in the comparator  48 . The output signal V OUT  from the comparator  48  changes from a first logical state when the measured temperature is less than the threshold temperature to a second logical state when the measured temperature is greater than the threshold temperature.  
         [0040]    [0040]FIGS. 3A and 3B provide simplified schematic diagrams of current mirror circuits  50  and  51 , respectively, in accordance with the prior art. The current mirror circuit  50  includes an input section  52  including a first transistor  54  having a drain that is coupled to a gate of the first transistor  54 . The current mirror circuit  50  also includes one or more output sections  56 . The output section  56  includes a second transistor  58  having a gate that is coupled to the gate of the first transistor  54 . Sources of both the first  54  and second  58  transistors are coupled to a common power supply node  60 . As a result, both the first  54  and the second  58  transistors have the same gate-source voltage.  
         [0041]    When a first current I n  is passed through the drain of the first transistor  54 , the drain and the gate of the first transistor  54  together equilibrate to provide a gate-source voltage that corresponds to a saturated drain current equal to the input current I n . In turn, this gate-source voltage is impressed on the second transistor  58 . As a result, the saturated drain current of the second transistor  58  is a scaled current I SC  that is proportional to the current I n  that is input to the drain of the first transistor  54 .  
         [0042]    When gate widths W 1  and W 2  of the first  54  and second  58  transistors are equal, the scaled current I SC  is equal to the input current I n . When the gate widths W 1  and W 2  of the first  54  and second  58  transistors are chosen to be different, the currents I SC  and I n  are related as follows:  
           I   SC   /I   n   =W   2   /W   1   (Eq. 2)  
         [0043]    Similarly, FIG. 3B shows the current mirror  51  having an input section  62  using a p-channel FET  64  and an output section  66  using a p-channel FET  68 . The power supply node  70  is coupled to sources of both FETs  64  and  68 . The current mirror  51  operates in a fashion analogous to that of the current mirror  50  but is referenced to the positive power supply node  70  rather than to the negative power supply node  60 .  
         [0044]    Current mirrors operating analogously to the current mirrors  50  and  51  may also be constructed using other types of transistors, such as bipolar transistors. Additionally, an arbitrarily large number of output sections  56  (or  66 ) may be coupled to the input section  52  (or  62 ) to provide a number of scaled output currents I SCn , each having a known relationship to the input current I n .  
         [0045]    Further, multiple current mirrors  50  and  51  may be interconnected to form the comparator  48  (FIG. 2) or a comparison stage prior to the comparator  48 . For example, a first current having a first temperature coefficient may be coupled to a p-channel FET current mirror  51  having an output section  66 , and a second current having a second temperature coefficient may be coupled to another p-channel FET current mirror  51  having an output section  66 .  
         [0046]    When output currents from these two p-channel FET current mirrors  51  are fed to the input  52  and output  56  sections, respectively, of an n-channel FET current mirror  50 , a voltage developed on the drain of the output transistor  58  is indicative of which of the two currents is larger. When the current fed into the input section  52  is larger than the current fed into the output section  56 , the drain voltage on the output transistor  58  will be low. Conversely, when the current fed into the output section  56  is larger than the current fed into the input section  52 , the drain voltage on the output transistor  58  will be high.  
         [0047]    [0047]FIG. 4 is a simplified schematic diagram of an adjustable gate width field effect transistor  80 , in accordance with an embodiment of the present invention. The adjustable gate width transistor  80  includes multiple transistors  82  and  84 , digital switches  92  and  94 , outputs  96  and  98  and inverters  102 ,  104 ,  106  and  108 . The adjustable gate width transistor  80  also includes a gate bias signal source  110  and inputs  112  and  114 . While the adjustable gate width transistor  80  is shown as having only two transistors  82  and  84  for clarity of explanation and ease of understanding, it will be understood that more transistors analogous to the transistors  82  and  84  may be included.  
         [0048]    The adjustable gate width transistor  80  switches one or more transistors  82  and  84  into or out of a circuit, such as the current mirror  50  of FIG. 3A, that is coupled to one of the outputs  96  and  98 . The transistors  82  and  84  are switched into or out of the circuit in response to digital input signals provided at inputs  112  and  114 .  
         [0049]    For example, when the input  112  is switched to logic “1”, signal  1 * is set to logic “0”, signal  1  is set to logic “1” and the switch  92  is turned ON. When the input  114  is switched to logic “0”, signal  2 * is set to logic “1”, signal  2  is set to logic “0” and the switch  94  is turned OFF. As a result, for these input signals, the transistor  82  is connected to the terminal  96  but the transistor  84  is not connected to the terminal  98 .  
         [0050]    When the terminal  96  is coupled to the drain of the transistor  54  in FIG. 3A, and the gate of the transistor  82  is coupled to a voltage source that provides a voltage that is related to the gate voltage of the transistors  54  and  58 , the transistor  82  modifies (reduces) the gate width ratio W 2 /W 1  of the current mirror  50  when the switch  92  is turned ON. Similarly, when the terminal  98  is coupled to the drain of the transistor  58  and the gate of the transistor  94  is biased as described above, the transistor  84  modifies (increases) the gate width ratio W 2 /W 1  of the current mirror  50  when the switch  94  is turned ON.  
         [0051]    One way to provide a voltage that is related to the gate voltage in the current mirror  50  is to couple a current I′ n  that is a replica of the current I n  into a drain of a separate transistor  116  having drain, gate and source electrodes coupled in the same way as are corresponding electrodes of the transistor  54 . When the current I n  is derived, for example, from a current mirror  51  formed from p-channel FETs, the replica current I′ n  may be taken from an additional output section  68  of the p-channel current mirror  51 .  
         [0052]    Many variations of this arrangement for coupling transistors such as  82  and  84  into and out of current mirrors such as the current mirror  50  are possible. In one embodiment, selectively coupling multiple transistors such as the transistor  82  into the output portion  56  of the current mirror  50  allows the gate width ratio W 2 /W 1  to be increased by a chosen number of successive increments. Alternatively, selectively coupling multiple transistors such as the transistor  84  into the input portion  52  allows the gate width ratio W 2 /W 1  to be decreased by a chosen number of successive increments.  
         [0053]    As a result, the ratio of the currents I SC /I n  may be adjusted in response to digital signals present on inputs such as the inputs  122  and  124 . In turn, when the current mirror  50  is used to compare currents having different temperature coefficients or different signs of temperature coefficient to provide the OVERTEMPERATURE signal on the output line  34  of FIG. 1, the temperature threshold or setpoint of the temperature sensing circuit  21  of FIGS. 1 and 2 may be adjusted up or down from an initial setpoint determined from the as-fabricated values of the components of the temperature sensing circuit  21 .  
         [0054]    Additionally, when the gate bias for the transistors  82  and  84  is derived from other sources, the transistors  82  and  84  may act to provide an offset to the current I SC  that the output section  56  of the current mirror  50  (FIG. 3A) provides. When currents from different current mirrors  50 ,  51  are compared in the comparator  48  (FIG. 2), this offset may be used to adjust the temperature at which two different currents are equal and thus may be used to adjust the setpoint temperature of the temperature sensing circuit  21 .  
         [0055]    [0055]FIG. 5 is a simplified schematic diagram of a fusing circuit  120  for storing a temperature threshold, in accordance with an embodiment of the present invention. The fusing circuit  120  may be used to form the nonvolatile memory  47  of FIG. 2. In one embodiment, the fusing circuit  120  includes a bank of fusable devices  122 , bias current sources  124 , buffers  126  and outputs  128  and  130 . The fusing circuit  120  may also include a programming voltage source  132  couplable (as represented by dashed lines) to the fusable devices  122  if the fusable devices  122  are electrically programmable. The fusable devices  122  may be fuses or antifuses.  
         [0056]    Fusable devices  122  are typically two-terminal devices capable of having two different conductive states, corresponding to either an open or a short circuit between the two terminals. Fuses are fusable devices  122  that present a short circuit between the two terminals until they are programmed, which irreversibly causes the fuse to manifest an open circuit between the two terminals. Antifuses are fusable devices  122  that present an open circuit between the two terminals until they are programmed, which irreversibly causes the antifuse to manifest a short circuit or a resistive connection between the two terminals.  
         [0057]    Fuses and antifuses are described in U.S. Pat. Nos. 5,811,869 and 5,812,441, which are assigned to the assignee of the present invention and which are incorporated herein by reference. Fuses typically are programmed by focusing an intense light source on a conductive material forming a portion of the fuse to cause an open circuit by ablation of the portion of the conductive material.  
         [0058]    Antifuses may be programmed through focusing of radiation from a source external to the integrated circuit on which the antifuses are formed, as discussed in U.S. Pat. No. 5,811,869, which is assigned to the assignee of the present invention and which is incorporated herein by reference. Alternatively, antifuses may be programmed through operation of electrical circuitry on the integrated circuit or by electrical circuitry external to the integrated circuit, as described, for example, in U.S. Pat. Nos. 5,793,224 and 5,812,468, which are assigned to the same assignee as the present invention and which are incorporated herein by reference. Antifuses may provide advantages due to reduced substrate area requirements compared to fuses. When fusable devices  122  are blown using a voltage, the circuit incorporating the fusable devices  122  may be programmed after being encapsulated in a package. States of antifuses may be read using circuitry as described, for example, in U.S. Pat. Nos. 5,831,923 and 5,872,740, which are assigned to the assignee of the present invention and which are incorporated herein by reference.  
         [0059]    Antifuses may be formed in the same manner as DRAM memory cell capacitors and read using similar circuitry. In one embodiment, antifuses are formed to have a silicon nitride dielectric having a thickness of about fifty Angstroms. A resistive element may be used to bias the antifuse by coupling the resistive element and the antifuse in series between a power supply node and ground. A buffer circuit having an input coupled to both the antifuse and the resistive element will provide an output signal having a first state or a second state, depending on whether the antifuse has been blown or not.  
         [0060]    The circuit  120  may be used to provide digital signals to the inputs  112  and  114  of FIG. 4 that correspond to the states of the fusable devices  122  associated with the inputs  112  and  114 . When a desired temperature setpoint for the memory circuit  20  has been determined by testing the memory circuit  20  as described above with reference to FIG. 1, one or more fusable devices  122  may be blown in the circuit  120  to set the setpoint temperature that is stored in the nonvolatile memory  47  temperature sensing circuit  21  of FIG. 2.  
         [0061]    The temperature at which the memory circuit  20  of FIG. 1 provides a signal on the output line  34  to indicate that the memory circuit  20  is too hot for reliable operation may then be set without having to resort to a custom masking step, and may be adjusted to account for processing variations that may occur from one memory circuit  20  to another in manufacturing. As a result, greater flexibility is provided in categorization of the memory circuits  20  after the memory arrays  22  and other portions of the memory circuits  20  have been fabricated.  
         [0062]    Further, memory circuits  20  made from a common design may be adjusted, after the memory circuits  20  have been formed, to different operating specifications for different applications by setting initially similar temperature setpoints to different values for different ones of the memory circuits  20 . This feature may be used to customize memory integrated circuits  20  to particular specifications, even after most manufacturing operations have been completed.  
         [0063]    In one embodiment, a nominal temperature setpoint of 90 degrees Celsius is set for the temperature sensing circuit  21  of FIGS. 1 and 2. In one embodiment, a range of +/−10 degrees Celsius may be programmed by blowing fusable devices  122  in the fusing circuit  120 . In one embodiment, the range of temperatures over which the temperature sensing circuit  21  may be programmed is provided in five degree increments. In one embodiment, the temperature setpoint may increased or decreased by two or more temperature increments.  
         [0064]    In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.