Abstract:
In a digital/analog converter, a digital-to-analog converting section includes a constant current source circuit having a plurality of binary-coding weighted current output terminals and including a plurality of MOS transistor type current switches driven by digital input signals. Each of the MOS transistor type current switches is connected between one of the binary-coding weighted current terminals and an analog output current terminal. A reference voltage generating section generates at least one reference voltage and supplies it to the constant current source circuit. A current-to-voltage converting section converts an analog output current flowing through the analog output current terminal into an analog output voltage in response to the analog output current and supplies the analog output voltage to an analog output voltage terminal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a digital/analog (D/A) converter. 
     2. Description of the Related Art 
     In a prior art D/A converter (see: JP-A-57-83924), a digital-to-analog converting section includes a constant current source circuit having a plurality of binary-coding weight current output terminals and including a plurality of bipolar transistor type current switches driven by digital input signals. Each of the bipolar transistor type current switches is connected between one of the binary-coding weighted current terminals and an analog output current terminal. A reference voltage generating section generates at least two reference voltages and supplies them to the constant current source circuit. Particularly, one of the reference voltages is supplied to the bipolar transistor type current switches. A current-to-voltage converting section converts an analog output current flowing through the analog output current terminal into an analog output voltage in response to the analog output current and supplies the analog output voltage to an analog output voltage terminal. This will be explained later in detail. 
     In the above-described prior art D/A converter, however, since the current switches use bipolar transistors, collector currents flowing through the bipolar transistors, which contributes to the analog output current, are smaller than emitter currents flowing through the bipolar transistors. Therefore, in order to compensate for the caused error, an additional reference voltage source is provided in the reference voltage generating circuit, which makes the D/A converter more complex, thus increasing the manufacturing cost. Additionally, in order to operate the bipolar transistors of the current switches in a non-saturated state, a control circuit for adjusting the binary data signal is required, which also makes the D/A converter more comples. Thus, the manufacturing cost is further increased. 
     Also, in the above-described prior art D/A converter, since the analog output current of the D/A converting section is directly supplied to the current-to-voltage reference voltage generating section, the D/A converter is disadvantageous in terms of lowering the power supply voltage of the D/A converter. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a simplified D/A converter with a wide dynamic output range. 
     According to the present invention, in a D/A converter, a digital-to-analog converting section includes a constant current source circuit having a plurality of binary-coding weighted current output terminals and including a plurality of MOS transistor type current switches driven by digital input signals. Each of the MOS transistor type current switches is connected between one of the binary-coding weighted current terminals and an analog output current terminal. A reference voltage generating section generates at least one reference voltage and supplies it to the constant current source circuit. A current-to-voltage converting section converts an analog output current flowing through the analog output current terminal into an analog output voltage in response to the analog output current and supplies the analog output voltage to an analog output voltage terminal. 
     Also, a current mirror circuit is connected between the analog output current terminal and the current-to-voltage converting section. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein: 
     FIG. 1 is a circuit diagram illustrating a prior art D/A converter; 
     FIGS. 2A,  2 B,  2 C,  2 D and  2 E are circuit diagrams for explaining the binary circuits flowing through the master ladder circuit of FIG. 1; 
     FIGS. 3A,  3 B,  3 C and  3 D are circuit diagrams for explaining the binary currents flowing through the slave ladder circuit of FIG. 1; 
     FIG. 4 is a circuit diagram of the current switch of FIG. 1; 
     FIG. 5 is a graph showing the analog output current characteristics of the D/A converter of FIG. 1; 
     FIG. 6 is a circuit diagram illustrating an embodiment of the D/A converter according to the present invention; 
     FIG. 7 is a circuit diagram for explaining the binary currents flowing through the master ladder circuit of FIG. 6; 
     FIG. 8 is a circuit diagram of the current switch of FIG. 6; 
     FIG. 9 is a circuit diagram for explaining the operation of the current switch of FIG. 8; 
     FIGS. 10A and 10B are diagrams for showing the drain current characteristics of the circuit of FIG. 9; 
     FIG. 11 is an actual circuit diagram of the current switch of FIG. 8; 
     FIG. 12 is a circuit diagram illustrating a modification of the current switch of FIG. 8; 
     FIG. 13 is an actual circuit diagram of the current switch of FIG. 8; 
     FIG. 14 is a partial circuit diagram of the D/A converter of FIG. 6; 
     FIG. 15A is a graph showing the analog output voltage characteristics of the D/A converter of FIG. 6; 
     FIG. 15B is a partly-enlarged graph of the graph of FIG. 15A; 
     FIG. 16 is a circuit diagram illustrating a modification of the slave ladder circuit of FIG. 6; and 
     FIG. 17 is a circuit diagram illustrating a D/A converter to which a plurality of D/A converters of FIG. 6 are applied. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before the description of the preferred embodiment, a prior art D/A converter will be explained with reference to FIGS. 1,  2 A through  2 E,  3 A through  3 D,  4  and  5  (see JP-A-57-83924). 
     In FIG. 1, which illustrates a prior art 8-bit D/A converter, the D/A converter is constructed by a D/A converting section  100 , a reference voltage generating circuit  200 , and a current-to-voltage converting section  300 . 
     The D/A converting section  100  is constructed by a master ladder circuit  110 , a slave ladder circuit  120  and a current switch circuit  130 . 
     In more detail, the master ladder circuit  110  is formed by a constant current transistor circuit  111  including bipolar transistors Q 1 , Q 2 , Q 3 , Q 4  and Q 5  having emitter areas  8 X,  4 X,  2 X,  1 X and  1 X, respectively, an R- 2 R resistance ladder circuit  112  connected to the emitters of the bipolar transistors Q 1 , Q 2 , Q 3 , Q 4  and Q 5 , and a current compensating circuit  113  including bipolar transistors Q 6 , Q 7 , Q 8  and Q 9  having an emitter area  1 X connected to the collectors of the bipolar transistors Q 1 , Q 2 , Q 3  and Q 4 , respectively. 
     Similarly, the slave ladder circuit  120  is formed by a constant current transistor circuit  121  including bipolar transistors Q 10 , Q 11 , Q 12 , Q 13  and Q 14  having emitter areas  8 X,  4 X,  2 X,  1 X and  1 X, respectively, and an R- 2 R resistance ladder circuit  122  connected to the emitters of the bipolar transistors Q 10 , Q 11 , Q 12 , Q 13  and Q 14 . 
     The current switch circuit  130  is formed by bipolar current switches S 1 , S 2 , . . . , S 8  connected to the collectors of the transistors Q 6 , Q 7 , . . . , Q 13 , respectively. 
     The reference voltage generating circuit  200  is constructed by four reference voltage sources V 1 , V 2 , V 3  and V 4 , a resistor R′ connected to the reference voltage source V 1  for converting a current flowing therethrough into a voltage, bipolar transistors Q 15 , Q 16  and Q 17  connected in series between the resistor R′ and the ground terminal, emitter resistor  2 R connected to the emitter of the transistor Q 15 , and an operational amplifier AMP 1  for controlling the base voltage of the transistors Q 15 . In this case, the operational amplifier AMP 1  has a positive input terminal connected to the resistor R′ and a negative input terminal connected to the reference voltage source V 2 . 
     The current-to-voltage converting section  300  is formed by an operational amplifier AMP 2  having a positive input terminal connected to a reference voltage source V R  and a negative input terminal connected to the current switches S 1 , S 2 , . . . , S 8 , and a feedback resistor R′/2 connected between the output terminal and the negative input terminal of the operational amplifier AMP 2 . As a result, the current-to-voltage converting section  300  converts a total current I out  flowing through the current switches S 1 , S 2 , . . . , S 8  into an output voltage V out . 
     The bases of the transistors Q 1 , Q 2 , Q 3 , Q 4  and Q 5  as well as the base of the transistor Q 15  are connected to the output of the operational amplifier AMP 1 , so that the voltages at the bases of the transistors Q 1 , Q 2 , Q 3 , Q 4 , Q 5  and Q 15  are controlled at V 2 . Also, the bases of the transistors Q 6 , Q 7 , Q 8 , Q 9 , Q 10 , Q 11 , Q 12 , Q 13  and Q 14  as well as the base of the transistor Q 16  are controlled at V 3 . 
     The four upper bits are subject to a D/A conversion by the master ladder circuit  110  through which binary cirremts flow as illustrated in FIGS. 2A,  2 B,  2 C,  2 D and  2 E. In FIG.  2 E, a reference current I r  is approximately determined by (V 2 −V 1 )/R′. In this case, a current I flowing through the node N between the constant current transistor circuit  111  and the R- 2 R resistance ladder circuit  122  is represented by I=I r /8. 
     The four lower bits are subject to a D/A conversion by the slave ladder circuit  120  through which binary currents flow as illustrted in FIGS. 3A,  3 B,  3 C and  3 D. In this case, a current I′ flowing through the transistor Q 14  is represented by I′=I/16=I r /128. 
     Returning to FIG. 1, the base of the transistor Q 17  is controlled at V 4  which is also supplied to the current switches S 1 , S 2 , . . . , S 8 . Each of the current switches S 1 , S 2 , . . . , S 8  is illustrated in FIG.  4 . That is, the current switch Si is formed by bipolar transistors Q 41  and Q 42  having a common emitter. In this case, the base and collector of the transistor Q 41  are controlled at V 4  and V 5 , respectively, and the base of the transistor Q 42  receives a binary data signal bi. As a result, if the binary data signal bi is “0” (low), the transistor Q 41  and Q 42  are turned ON and OFF, respectively. On the other hand, if the binary data signal bi is “1” (high), the transistor Q 41  and Q 42  are turned OFF and ON, respectively. 
     The operation of the D/A converter of FIG. 1 is explained below. 
     In the master ladder circuit  110 , the collector currents I C (Q 1 ), I C (Q 2 ), I C (Q 3 ), I C (Q 4 ), and I C (Q 5 ) are represented by 
     
       
           I   C (Q 1 ): I   C (Q 2 ): I   C (Q 3 ): I   C (Q 4 ): I   C (Q 5 )=1:½:¼:⅛:⅛  (1)  
       
     
     In the slave ladder circuit  120 , the collector currents I C (Q 10 ), I C (Q 11 ), I C (Q 12 ), and I C (Q 13 ) are represented by 
     
       
           I   C (Q 10 ): I   C (Q 11 ): I   C (Q 12 ): I   C (Q 13 )=1:½:¼:⅛  (2)  
       
     
     In this case, 
     
       
           I   C (Q 5 )= I   C (Q 10 )+ I   C (Q 11 )+ I   C (Q 12 )+ I   C (Q 13 )+ I   C ( Q 14)  (3)  
       
     
     Therefore, from the equations (1), (2) and (3), 
     
       
           I   C (Q 1 ): I   C (Q 2 ): I   C (Q 3 ): I   C (Q 4 ): I   C (Q 10 ): I   C (Q 11 ):  I   C (Q 12 ): I   C (Q 13 )=1:½:¼:⅛:{fraction (1/16)}:{fraction (1/32)}:{fraction (1/64)}:{fraction (1/128)}  (4)  
       
     
     Thus, an analog output current I out  is represented by 
     
       
           I   out   =I   r ·2( b   1 2 −1   +b   2 2 −2   +b   3 2 −3   +b   4 2 −4   +b   5 2 −5   +b   6 2 −6   +b   7 2 −7   +b   8 2 −8 )  (5)  
       
     
     where I r =(V 1 −V 2 )/R′. 
     The analog output current I out  is converted by the current-to-voltage converting section  300  into an analog output voltage V out  represented by 
     
       
           V   out   =V   R   −I   out   ·R′/ 2= V   R −( V   1   −V   2 )( b   1 2 −1   +b   2 2 −2   +b   3 2 −3   +b   4 2 −4   +b   5 2 −5   +b   6 2 −6   +b   7 2 −7   +b   8 2 −8 )  (6)  
       
     
     In the D/A converter of FIG. 1, however, since the current switches S 1 , S 2 , . . . , S 8  use bipolar transistors Q 41  and Q 42 , a collector current I C  flowing through the transistor Q 42 , which contributes to the analog output current I out , is smaller than an emitter current IE flowing through the transistor Q 42 . That is, 
     
       
           I   C   =I   E   ·h   FE /(1 +h   FE ).  
       
     
     where h FE  is an emitter ground current amplification factor. Therefore, in order to compensate for the error caused by the emitter ground current amplification factor h FE , the transistor Q 17  and the reference voltage source V 4  are provided in the reference voltage generating circuit  200 , which complexes the D/A converter of FIG. 1, thus increasing the manufacturing cost. Additionally, in order to operate the transistors Q 41  and Q 42  in a non-saturated state, a control circuit for adjusting the binary data signal bi (i=1˜8) is required, which also makes the D/A converter of FIG. 1 more complex. Thus, the manufacturing cost is further increased. 
     Also, in the D/A converter of FIG. 1, since the analog output current I out  of the D/A converting section  100  is directly supplied to the current-to-voltage converting section  300 , the dynamic range of the analog output voltage V out  is, from V R  to V CC . For example, if V R  is 5V and V CC  is 6.5V, the dynamic range of the analog output voltage V out  is 5V to 6.5V, which is very narrow. 
     Further, in the D/A converter of FIG. 1, the transistors Q 15 , Q 16  and Q 17  are connected in series in the reference voltage generating circuit  200 , the following condition is required: 
     
       
         V 1 &gt;V 2 ≧V 4   
       
     
     This is disadvantageous in terms of lowering the power supply voltage of the D/A converter. 
     In FIG. 6, which illustrates an embodiment of the present invention, the D/A converting section  100  of FIG. 1 is replaced by a D/A converting section  100 ′ including a current switch circuit  130 ′ formed by MOS transistor current switches S 1 ′, S 2 ′, . . . , S 8 ′. Also, the reference voltage generating circuit  200  of FIG. 1 is replaced by a reference voltage generating circuit  200 ′ where the reference voltage source V 2  is connected to the base of the transistor Q 16 , and the transistor Q 17  and the reference voltage source V 4  are not provided. 
     Also, a current mirror circuit  400  is provided between the D/A converting section  100 ′ and the current-to-voltage converting section  300 . 
     Even in the D/A converter of FIG. 6, the analog output current I out  is represented by the above-mentioned equation (5), and the analog output voltage V out  is represented by the above-mentioned equation (6). 
     In the D/A converter of FIG. 6, the equivalent circuit of FIG. 2E is replaced by an equivalent circuit as illustrated in FIG.  7 . Therefore, if the emitter ground current amplification factor h FE  of the transistors Q 15  and Q 16  is the same as those of the transistors Q 1  and Q 6 , the analog output current I out  is accurately dependent on I r , i.e., (V 1 −V 2 )/R′ independently of the emitter ground current amplification factor h FE . 
     Each of the current switches S 1 ′, S 2 ′, . . . , S 8 ′ is illustrated in FIG.  8 . That is, the current switch Si′ is formed by two N-channel MOS transistors Q 81  and Q 82  having a common source and an inverter I. The transistor Q 81  has a drain controlled at V 5  and a gate controlled by the binary data signal bi, and the transistor Q 82  has a drain for supplying the analog output current I OUT  and a base controlled by the inverted signal of the binary data signal bi through the inverter I. Generally, since a source current of a MOS transistor is approximately the same as a drain current thereof, the current flowing therethrough does not involve the problem that a collector current of a bipolar transistor depends upon the emitter ground current amplification factor h FE  thereof. 
     The input/output characteristics of the current switch Si of FIG. 8 is explained next with reference to FIG.  9 . 
     Generally, if a MOS transistor is operated in a five-electrode tube and the back gate effect is negligible, a drain current I d  of the MOS transistor is represented by 
     
       
           I   d =β( V   GS   −V   th ) 2   (7)  
       
     
     where β=μ n C 0 W/2L; 
     μ n  is the mobility of electrons; 
     C 0  is a MOS capacitance per unit area of a MOS insulating layer; 
     W is a gate width; 
     L is a gate length; 
     V GS  is a gate-to-source voltage; and 
     V th  is a threshold voltage. Therefore, in FIG. 9, 
     
       
           I   d1 =β( V   GS1   −V   th ) 2   (8)  
       
     
     
       
           I   d2 =β( V   GS2   −V   th ) 2   (9)  
       
     
       I   d1   +I   d2   =I   SS   (10) 
     
       
           V   i1   −V   GS1   +V   GS2   −V   i2 =0  (11)  
       
     
     From the equations (8) and (9), 
     
       
           V   GS1 ={square root over ( I   d1 /β)}+ V   th   (12)  
       
     
     
       
           V   GS2 ={square root over ( I   d2 /β)}+ V   th   (13)  
       
     
     Therefore,                      Δ                 V     =       V   i1     -     V   i2                   =       V   GS1     -     V   GS2                   =       (         I   d1       -       I   d2         )     /     β                     (   14   )                                
     From the equations (10) and (14), 
     
       
         Δ V= ({square root over ( I   d1 )}−{square root over ( I   SS   −I   d1 )})/{square root over (β)}  (15)  
       
     
     
       
         ∴ I   d1 =( I   SS /2)·(1 +ΔV·β ({square root over (2/ I   SS β)−(Δ V/I   SS ) 2 )})  (16)  
       
     
     Similarly, 
     
       
           I   d2 =( I   SS /2)·(1 −ΔV·β{square root over ((2/ I   SS β)−(Δ V/I   SS ) 2 )})   (17)  
       
     
     For example, if 
     ε 0X =3.83×8.842×10 −14 F/cm; 
     T 0X =1.6×10 −16  cm(Typ); 
     μ n =3.8058557×10 2  cm 2 /V·sec; 
     V th =0.7V(Typ.); 
     L=0.56 μm; and 
     W=5 μm, then, 
     β=μ n C 0 W/2L=μ n ε 0X W/2T 0X L=3.596×10 −13    
     The drain current characteristics of the equations (16) and (17) are shown in FIGS. 10A and 10B, where I SS =128 μA and I SS =1 μA, respectively. That is, if the input voltage difference ΔV is about 0.2V for I SS =128 μA, the state of the current switch can be easily switched. Similarly, if the input voltage difference ΔV is about 0.02V for I SS =1 μA, the state of the current switch can be easily switched. 
     The current switch Si′ of FIG. 8 is constructed by two CMOS inverters I 1  and I 2  as illustrated in FIG.  11 . In FIG. 11, the inverter I 1  corresponds to the inverter I of FIG. 8, and the inverter I 2  is added to apply a non-inverted binary data signal bi. Therefore, the input voltages V i1  and V i2  are changed from 0V to 5V, so that the state of the current switch Si′ can be easily switched. 
     In FIG. 12, which illustrates a modification of the current switch Si′ of FIG. 8, a P-channel MOS transistor Q 82 ′ is provided instead of the N-channel MOS transistor Q 82  of FIG.  8 . As a result, the binary data signal bi is logically applied directly to the gate of the transistor Q 82 ′. In this case, however, in order to increase the amplitude of the input voltage V i1 , and V i2 , as illustrated in FIG. 13, the CMOS inverters I 1  and I 2  are also provided in the same way as in FIG. 11, so that the same input voltage V i1 (=V i2 ) is applied to the gates of the transistors Q 81  and Q 82 ′. 
     The relationship between the reference voltage source V 2  and the operation of the transistor Q 6  is explained next with reference to FIG. 14 which is a partial circuit diagram of the circuit of FIG. 6 regarding the most significant bit MSB portion thereof. 
     In order to determine the value of the reference voltage source V 2 , the transistors Q 15 , Q 1 , Q 16  and Q 6  have to be operated in a non-saturated region, which limits the base voltage of the transistors Q 15  and Q 1 , the gate-to-source voltages of the transistors Q 81  and  82  and their gate control voltages such as 0V and 5V. 
     First, the base voltages V B  (Q 15 ) and V B  (Q 1 ) of the transistors Q 15  and Q 1  are represented by 
     
       
           V   B (Q 15 )= V   B (Q 1 )  
       
     
     
       
           V   BE (Q 15 )+128  μA· 2 R   (18)  
       
     
     where V BE  (Q 15 ) is a base-to-emitter voltage of the transistor Q 15 . For example, if R=2.5 kΩ and V BE  (Q 15 )=0.8V, then, 
     
       
           V   BE (Q 15 )=1.44 V    
       
     
     Therefore, in order to operate the transistor Q 15  in a non-saturated region, 
     
       
           V   C  (Q 15 )≧ V   BE  (Q 15 )  
       
     
     where V C  (Q 15 ) is a collector voltage of the transistor Q 15 . Thus,              V2   ≧                    V   C                     (   Q15   )       +       V   BE                     (   Q16   )                     =                1.44   +   .08                 =                2.24                 V                                  
     As a result, if the value of the reference voltage source V 2  can be 2.5V, the collector voltage and base voltage of the transistor Q 16  are also 2.5V due to the imaginary shortage between the inputs of the operational amplifier AMP 1 . Thus, the transistor Q 16  is operated in a non-saturated region. 
     Next, the non-saturated operation of the transistor Q 6  is explained below. 
     The gate-to-source voltages V GS1 , and V GS2  of the transistors Q 81  and Q 82  are represented using the equations (12) and (13) in view of the back gate voltage V B  by 
     
       
           V   GS1 ={square root over ( I   d1 /β)}+( V   th +γ{square root over ( V   B )})  (19)  
       
     
     
       
           V   GS2 ={square root over ( I   d2 /β)}+( V   th +γ{square root over ( V   B )})  (20)  
       
     
     In order to operate the transistor Q 6  in a non-saturated region, the base voltage of the transistor Q 6  is not higher than the collector voltage of the transistor Q 6 . That is, 
     
       
         V 2 ≦5V−V GS1    
       
     
     
       
         ∴2.5 V≦ 5 V− ({square root over ( I   d2 /β)}+ V   th +γ{square root over ( V   B )}))  (21)  
       
     
     For example, if 
     ε 0X =3.83×8.842×10 −14 /cm; 
     T 0X =1.7×10 −6  cm&gt;1.6×10 6  cm(Typ.); 
     μ n =3.8058557×10 2  cm 2 cm/V·sec; 
     V th =0.85V&gt;0.7V (Typ.); 
     L=0.56 μm; 
     W=5 μm; 
     V B  =3V; 
     γ=0.5; and 
     I d2 =128 μA(MSB), then, the left term of the formula (21) is 3.085V. Note that the thickness T 0X  of the gate insulating layer and the threshold voltage V th  are set at worse conditions, and the drain current I d2  is a maximum value, i.e., 128 μA. Thus, the formula (21) is completely satisfied, so that the transistor Q 6  can be operated in a non-saturated region. 
     The dynamic range of the analog output voltage V out  is determined by the condition that the MOS transistors Q 81  and Q 82  are not operated in a non-saturated region (a triode region), i.e., 
     
       
           V   DS   ≧V   GS   −V   th   (22)  
       
     
     where V GS  is a drain-to-source voltage; and 
     V GS  is a gate-to-source voltage. In this case, if the source voltage of the MOS transistors Q 81  and Q 82  is at worst about 3V, the threshold voltage V th  is at worst 0.55V and the back gate voltage V B  is 3V, then, the formula (22) is 
     
       
           V   DS ≧(5 V− 3 V )−(0.55 V+ 0.87 V )=0.58 V    
       
     
     Therefore, the drain voltage of the transistor Q82 has to be higher than 3V+0.58V (=3.58V). Note that, if the current mirror circuit  400  is powered by V CC =6.0V and has a voltage drop of about 1.9V, the output voltage of the current mirror circuit  400  is 6.0−1.9=4.1V. Thus, the above-mentioned drain voltage of the transistor Q 82  is satisfied, so that the D/A converter of FIG. 6 can be operated under the condition that the power supply voltage V CC  is 6.0V. 
     The analog output voltage characteristics of the D/A converter of FIG. 6 are obtained by a simulation method using V CC =6.0V as shown in FIG.  15 A and FIG. 15B which is a partly-enlarged graph of the graph of FIG.  15 A. As shown in FIGS. 15A and 15B, linearity characteristics of the analog output voltage V out  are excellent and a dynamic output voltage range of 2V can be obtained. 
     In the above-mentioned embodiment, the R- 2 R resistance ladder circuit  112  or  122  of FIG. 6 can be replaced by a weighted resistance circuit. For example, as illustrated in FIG. 16, the R- 2 R resistance ladder circuit  122  of FIG. 6 is replaced by a weighted resistance circuit  122 ′. For example, the collector currents I C (Q 10 ) and I C (Q 11 ) of the transistors Q 10  and Q 11  satisfy the following: 
     
       
           kT/q  ln( I   C (Q 10 )/8 I   C )+ I   C (Q 10 )· r/ 8 =kT/q 1 n ( I   C (Q 11 )/4 I   C )+I C (Q 11 )· r/ 4  
       
     
     where k is the Boltzmann constant; 
     T is an absolute temperature; and 
     q is an electron charge. Therefore, 
     I C (Q 10 )= 2 I C (Q 11 ) 
     Similarly, 
     I C (Q 11 )= 2 I C (Q 12 ) 
     I C (Q 12 )= 2 I C (Q 13 ) 
     Thus, the equation (2) is also satisfied. 
     In FIG. 17, which is a circuit diagram illustrating a circuit including multiple D/A converters, a plurality of D/A converters of FIG. 6, i.e., 32 D/A converters of FIG. 6, are provided. In this case, 32 D/A converting sections  100 ′- 1 ,  100 ′- 2 , . . . ,  100 ′- 32 ,  32  current-to-voltage converting sections  300 - 1 ,  300 - 2 , . . . ,  300 - 32 , and  32  current mirror circuits  400 - 1 ,  400 - 2 , . . . ,  400 - 32  are provided, but only one reference voltage generating circuit  200 ′ is provided, thus decreasing the size of the D/A converter. In addition, the characteristics of fluctuation between the analog output voltages V out1 , V out2 , . . . , V out32  for the same digital input signal can be suppressed, thus increasing the relative accuracy between the analog output voltages V out1 , V out2 , . . . , V out32 . 
     In the above-described embodiment, the current mirror circuit  400  can provide a high accuracy D/A conversion and a wide dynamic analog output range while the power supply voltage V CC  can be decreased. In FIG. 4, although the current mirror circuit  400  is of a Wilson type, the current mirror circuit  400  can be of another type. 
     As explained hereinabove, according to the present invention, since the current switches use MOS transistors, the reference voltage generating circuit can be simplified, thus decreasing the manufacturing cost. Additionally, a control circuit for adjusting the binary data signal is unnecessary, which also simplifies the D/A converter, thus further decreasing the manufacturing cost. 
     Also, since an analog output current of a D/A converting section is supplied via a current mirror circuit to a current-to-voltage reference voltage generating circuit, a wide dynamic output range can be obtained while lowering the power supply voltage of the D/A converter.