Abstract:
A pre-amplifier circuit can be cascaded and drive a latch for use in a precision analog-to-digital converter (ADC). The pre-amplifier has a main section and a feedback section connected by feedback resistors that do not produce voltage drops in the main section. Offset is stored on offset capacitors during an autozeroing phase and isolated by transmission gates during an amplifying phase. The offset capacitors drive the gates of feedback transistors that drive output nodes in the main section. Autozeroing sink transistors in the feedback section operate in the linear region while current sink transistors in the main section operate in the saturated region. Kickback-charge isolation transistors may be added for charge isolation. The output may also be equalized by an equalizing transmission gate. A very low power-supply voltage is supported even for high-speed operation with offset cancellation, due to the folded feedback resistor arrangement.

Description:
FIELD OF THE INVENTION 
     This invention relates to Analog-to-Digital Converters (ADC), and more particularly to a comparator for an ADC. 
     BACKGROUND OF THE INVENTION 
     Offset voltages on differential inputs cannot be tolerated for some high-precision applications. One common application is a high-resolution Analog-to-Digital Converter (ADC). An ADC cannot tolerate an input offset that is greater than the least-significant-bit (LSB) since the LSB precision would be lost. 
     Since the gain-bandwidth product of a single stage amplifier is constant, several amplifier stages are often cascaded together. The cascade provides a desired amplification factor with minimal delay. A cascade of pre-amplifiers can amplify a small input charge to produce a sufficiently large output charge that may then drive a latch that is part of a precision device such as an ADC. 
     However, any random input offsets in the cascade of pre-amplifiers can be propagated through the cascade of amplifier stages and the final amplified offset can significantly degrade the precision of the system. 
     Auto-zeroing techniques may be used to cancel such offsets. Often two phases are used to clock the cascade of amplifiers, where offset charges are stored in one phase and signal amplification occurs in the other phase. 
     Power supply voltages have been reduced to avoid damaging transistors that have been shrunk for advanced semiconductor processes. The lower power-supply voltage results in circuit design challenges since transistor saturation voltages may cut the remaining power-supply voltage in some circuits. The remaining voltage may be further reduced by I*R voltage drops through resistors. Traditional amplifier circuits with a saturated transistor in series with a resistor may leave little room for amplifying transistors to operate when the supply voltage is reduced. 
     What is desired is a pre-amplifier stage that eliminates an I*R drop due to a resistor in series with a saturated transistor. An amplifier that can operate with reduced power supply voltages is desirable. An amplifier with auto-zeroing and a folded resistor circuit design is desired for precision applications such as for an ADC. 
     Precision ADC Application— FIGS. 1-2   
     A pre-amplifier with auto-zeroing of input offsets may be used in a precision ADC application such as described below for  FIGS. 1-2 . The pre-amplifier may be used for other precision applications such as a low noise amplifier, a high precision instrumentation amplifier, a high precision comparator, any offset cancellation amplifier, DAC, etc. 
     Successive-approximation ADC&#39;s use a series of stages to convert an analog voltage to digital bits. Each stage compares an analog voltage to a reference voltage, producing one digital bit. In sub-ranging ADC&#39;s, each stage compares an analog voltage to several voltage levels, so that each stage produces several bits. Succeeding stages generate lower-significant digital bits than do earlier stages in the pipeline. 
     Algorithmic, re-circulating, or recycling ADC&#39;s use a loop to convert an analog voltage. The analog voltage is sampled and compared to produce a most-significant digital bit. Then the digital bit is converted back to analog and subtracted from the analog voltage to produce a residue voltage. The residue voltage is then multiplied by two and looped back to the comparator to generate the next digital bit. Thus the digital bits are generated over multiple cycles in the same comparator stage. 
       FIG. 1  shows a Successive-Approximation-Register ADC. Successive-Approximation-Register SAR  302  receives a clock CLK and contains a register value that is changed to gradually zero-in on a close approximation of the analog input voltage VIN. For example, the value in SAR  302  may first be 0.5, then 0.25, then 0.32, then 0.28, then 0.30, then 0.31, then 0.315, then 0.313, then 0.312, when comparing to a VIN of 0.312 volts. SAR  302  outputs the current register value to digital-to-analog converter (DAC)  300 , which receives a reference voltage VREF and converts the register value to an analog voltage VA. 
     The input analog voltage VIN is applied to sample-and-hold circuit  304 , which samples and holds the value of VIN. For example, a capacitor can be charged by VIN and then the capacitor isolated from VIN to hold the analog voltage. The sampled input voltage from sample-and-hold circuit  304  is applied to the inverting input of comparator  306 . The converted analog voltage VA is applied to the non-inverting input of comparator  306 . 
     Comparator  306  compares the converted analog voltage VA to the sampled input voltage and generates a high output when the converted analog voltage VA is above the sampled VIN, and the register value in SAR  302  is too high. The register value in SAR  302  can then be reduced. 
     When the converted analog voltage VA is below the sampled input voltage, comparator  306  generates a low output to SAR  302 . The register value in SAR  302  is too low. The register value in SAR  302  can then be increased for the next cycle. 
     The register value from SAR  302  is a binary value of N bits, with D(N-1) being the most-significant-bit (MSB) and D0 being the least-significant-bit (LSB). SAR  302  can first set the MSB D(N-1), then compare the converted analog voltage VA to the input voltage VIN, then adjust the MSB and/or set the next MSB D(N-2) based on the comparison. The set and compare cycle repeats until after N cycles the LSB is set. After the last cycle, the end-of-cycle EOC signal is activated to signal completion. A state machine or other controller can be used with or included inside SAR  302  to control sequencing. 
     Comparator  306  can be replaced with a series of pre-amplifier stages and a final latch.  FIG. 2A  is a response graph of pre-amplifier and latch stages. The pre-amplifier stages have a negative response shown by curve  312 , while the final latch has a positive response as shown by curve  310 . For low voltages, curve  312  is above and to the left curve  310 , indicating that the pre-amplifiers require less time to achieve the same VOUT voltage than the latch. However, for higher VOUT voltages, curve  310  is above curve  312 , indicating that for larger values of VOUT, the latch can achieve these larger voltage outputs much faster than the pre-amplifiers. 
       FIG. 2B  shows a series of pre-amplifiers and a final latch. Pre-amplifier stages  320 ,  322 ,  324 ,  326 ,  328  are amplifiers that boost the voltage difference between VIN and VA. Especially near the end of comparison when the LSB is being set, the difference between VIN and VA can be quite small. This voltage difference is gradually increased by the pre-amplifier stages until the final stage. Latch stage  330  latches this voltage difference to generate the compare signal that is fed back to SAR  302 . Thus stages  320 - 330  replace comparator  306  of  FIG. 1 . 
     By combining a series of pre-amplifier stages with the positive response of the final latch, a fast response time can be achieved. The pre-amplifier stages can gradually amplify and enlarge the voltage difference between VIN and VA until the amplified voltage difference is large enough to drive the final latch. The delay time can be minimized by using low-gain, wide bandwidth pre-amplifiers. 
     What is desired is a pre-amplifier stage that can be used in a precision ADC. A pre-amplifier that eliminates an I*R drop due to a resistor in series with a saturated transistor and can operate with reduced power supply voltages is desirable. An amplifier with auto-zeroing and a folded resistor circuit design is desired for precision applications such as for the ADC of  FIG. 1 . 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a Successive-Approximation-Register ADC. 
         FIG. 2A  is a response graph of pre-amplifier and latch stages. 
         FIG. 2B  shows a series of pre-amplifiers and a final latch. 
         FIG. 3  is a diagram of a high-speed latch. 
         FIG. 4  is a schematic of a first embodiment of a pre-amplifier stage with a folded resistor. 
         FIG. 5  is a waveform showing autozeroing by the pre-amplifier. 
         FIG. 6  is a waveform showing an offset being stored in the pre-amplifier. 
         FIG. 7  is a second embodiment of the pre-amplifier with kickback charge isolation. 
         FIG. 8  is a third embodiment of the pre-amplifier with equalization. 
     
    
    
     DETAILED DESCRIPTION 
     The present invention relates to an improvement in precise auto-zeroing comparators and amplifiers. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed. 
       FIG. 3  is a diagram of a high-speed latch. The high-speed latch of  FIG. 3  generates latched output OUT that can be part of an ADC, such as SAR  302  of  FIG. 1 . The latch inputs LATP, LATN can be the output of a final stage in a cascade of pre-amplifiers such as shown in  FIG. 2B , using one of the circuits of  FIGS. 4-6  for each stage in the cascade. 
     A bias voltage BIASP is applied to the gate of p-channel bias transistor  46 , which provides current to the sources of p-channel differential transistors  48 ,  49 . The latch input LATP, LATN is a differential signal that is output from a final stage in a cascade of pre-amplifier stages. LATP is applied to the gate of p-channel differential transistor  48  while LATN is applied to the gate of p-channel differential transistor  49 . 
     Cross-coupled NAND gates  40 ,  42  form a bi-stable that drive output OUT through inverter  44 . Cross-coupled p-channel transistors  22 ,  24  assist the settling of the bi-stable when CLK is high and CLKB is low, turning off transmission gate transistors  30 ,  32 ,  34 ,  36  and turning on p-channel source transistors  20 ,  26  to hold the state of the inputs to NAND gates  40 ,  42 . 
     When CLK is low and CLKB is high, p-channel source transistors  20 ,  26  turn off and transmission gate transistors  30 ,  32 ,  34 ,  36  turn on, allowing the latch to be set or reset by inputs LATP, LATN. N-channel cascode transistors  28 ,  29  receive a cascode bias voltage CASCN on their gates and each form a source-follower connection to the transmission gates. Current is pulled through n-channel cascode transistors  28 ,  29  by n-channel current sink transistors  38 ,  39  when transmission gates are open (CLKB high). 
     LATP applied to the gate of p-channel differential transistor  48  steers less current to the drain of n-channel current sink transistor  38  when LATP is higher than LATN. This allows more current to flow through cascode transistor  28 , pulling the input to NAND gate  42  lower and setting OUT high. 
       FIG. 4  is a schematic of a first embodiment of a pre-amplifier stage with a folded resistor. Feedback resistors  50 ,  52  are not in series between the power supply and ground, and thus do not reduce the available voltage by a V=I*R drop. This allows for two p-channel transistors and one saturated n-channel transistor in series between Vcc and ground in the main section of the amplifier (transistors  68 ,  60 ,  54 ), and two p-channel transistors, one transmission gate, and one saturated n-channel transistor in series between Vcc and ground in the feedback section of the amplifier (transistors  30 ,  74 ,  70 / 72 ,  76 ). The power supply can be as low as three times the saturated transistor voltage drop, or 3*VDSAT. 
     The circuit of  FIG. 4  can be the first stage in a cascade of pre-amplifiers, or any of the intermediate stages, or the final stage that drives the latch of  FIG. 3 . Inputs INP, INN can be the LATP, LATN outputs from a prior stage amplifier, or can be the external inputs when the amplifier is the first stage. Similarly, outputs LATP, LATN can drive the INP, INN inputs of a next stage in the cascade, or can drive the LATP, LATN inputs of the latch of  FIG. 3 . 
     Switches  61 ,  65  connect INP to gate node GP of p-channel differential transistor  60  when autozeroing signal AZ is low, but ground gate node GP during autozeroing. Similarly, switches  63 ,  67  connect INN to gate node GN of p-channel differential transistor  62  when autozeroing signal AZ is low, but ground gate node GN during autozeroing. 
     N-channel current sink transistors  54 ,  56  receive common-mode feedback bias voltage CMFB on their gates and sink current from the drains of p-channel differential transistors  60 ,  62 , which are also latch outputs LATN, LATP, respectively. 
     P-channel source transistor  68  receives a bias voltage BIASP and provides current to the sources of p-channel differential transistors  60 ,  62  in the main amplifier section. In the feedback section, p-channel source transistor  30  also receives bias voltage BIASP, and provides current to the sources of p-channel feedback transistors  74 ,  84 . 
     The feedback section of the pre-amplifier has n-channel autozeroing sink transistors  76 ,  86  that receive autozeroing signal AZB on their gates and turn on in the linear (triode) region when AZB is high. Since AZB swings to Vcc, while CMFB is a lower voltage, transistors  54 ,  56  in the amplifier section operate in the saturated region while transistors  76 ,  86  in the feedback section operate in the linear region. 
     During autozeroing, offset charges are stored on offset capacitors  78 ,  88 . Transmission gate transistors  70 ,  72 ,  80 ,  82  turn on and autozeroing sink transistors  76 ,  86  turn off. Gates nodes GP, GN are grounded by switches  65 ,  67  so that inputs are disconnected from the main amplifier section. This isolation during autozeroing allows and offsets on differential transistors  60 ,  62  to pass through feedback resistors  50 ,  52  and transmission gate transistors  70 ,  72 ,  80 ,  82  to be stored on offset capacitors  78 ,  88 . 
     The offsets stored on offset capacitors  78 ,  88  are applied to the gates of p-channel feedback transistors  74 ,  84 , which have drains driving LATN, LATP. Thus the offsets are fed back through a feedback loop of feedback resistors  50 ,  52  and feedback transistors  74 ,  84 . Charges stored on offset capacitors  78 ,  88  are adjusted by the feedback loop until steady-state is reached. The pre-amplifier is configured as a high-gain amplifier during autozeroing to store the offsets. 
     When autozeroing is completed, the offset charges are stored on offset capacitors  78 ,  88 . During the next (amplifying) phase, AZB is high and AZ is low. Comparison and amplification of the INP, INN inputs can occur since switches  61 ,  63  close to connect INP, INN to the gates of differential transistors  60 ,  62 . 
     Autozeroing sink transistors  76 ,  86  turn on and operate in the linear region. Transmission gate transistors  70 ,  72 ,  80 ,  82  turn off to isolate nodes RN, RP from nodes FN, FP, The offset charges on offset capacitors  78 ,  88  are applied to the gates of feedback transistors  74 ,  84  and are amplified to drive the stored offsets onto LATN, LATP to compensate for offsets in differential transistors  60 ,  62  or other parts of the circuit. 
     During the amplifying phase, the pre-amplifier is configured as a high-speed low-gain amplifier. The gain of the pre-amplifier during this phase is determined by the resistance of feedback resistors  50 ,  52 , such as 300K-Ohms. Since feedback resistors  50 ,  52  are in a folded circuit configuration, the power-supply voltage to differential transistors  60 ,  62  is not reduced by the I*R drop through feedback resistors  50 ,  52 . 
       FIG. 5  is a waveform showing autozeroing by the pre-amplifier. An offset voltage of −2.92 mV is applied to the inputs INP, INN during a simulation. Autozeroing starts at about 345 us and ends at about 349 us in the simulation. The pre-amplifier performs sample and conversion during the several pulses shown. During several cycles this offset is stored on offset capacitors  78 ,  88  and the feedback loop causes LATP, LATN to eventually equalize and settle at about 0.3 volts. 
       FIG. 6  is a waveform showing an offset being stored in the pre-amplifier. An offset voltage of −2.92 mV is applied to the inputs INP, INN during a simulation. During several autozeroing cycles, nodes FP, FN, which are also the voltages of offset capacitors  78 ,  88 , settle between 0.48 and 0.49 volts, with a difference of −2.97 mV representing the stored offset. Note that the stored offset of −2.97 mV is only 0.05 mV off from the true offset of −2.92 mV. This represents an error of only 1.7% of the injected offset. 
       FIG. 7  is a second embodiment of the pre-amplifier with kickback charge isolation. Kickback-charge isolation transistors  172 ,  174 ,  176 ,  178  are grounded-gate p-channel transistors that isolate kickback charge between the feedback and main amplifier sections. Kickback charge refers to charge injection during switching. Isolating the kickback charge has the advantage of preventing charge injection from disturbing the comparator. 
     Since the gates of kickback-charge isolation transistors  172 ,  174 ,  176 ,  178  are grounded, these operate in the linear region and do not cut a significant part of the supply voltage headroom. However, there is some voltage loss due to these transistors. 
       FIG. 8  is a third embodiment of the pre-amplifier with equalization. Equalizing transistors  160 ,  162  are added. When an equalization clock CLK is high, transistors  160 ,  162  turn on, shorting LATP to LATN. CLK can be pulsed high just before every comparison to allow for a faster settling of LATP, LATN. This forces and adjustment to the charge stored on offset capacitors  78 ,  88 . 
     CMFB is Common Mode Feedback. The CMFB signal is used during autozeroing as the preamplifier is reconfigured as a fully differential opamp. The CMFB signal is generated by another copy of the low voltage preamplifier with an output diode connected. This copy of the preamplifier does not require a high gain and is off during comparison An example of voltages of internal nodes is AZ=1V, AZB=0V, FB and FN=0.5V, CMFB=0.5V, and the power Vcc voltage is 1V. The process gate length in microns is 0.18 um in this example. 
     ALTERNATE EMBODIMENTS 
     Several other embodiments are contemplated by the inventors. For example other embodiments may be combinations of those shown. Equalizing transistors  160 ,  162  could be added without adding kickback-charge isolation transistors  172 ,  174 ,  176 ,  178 . Switches can be implemented as transmission gates with p-channel and n-channel transistors in parallel, or as a single transistor, either p-channel or n-channel. A different latch circuit may be used with the pre-amplifier. While an ADC application has been shown, the pre-amplifier could be used in other circuits, such as DACs, comparators, low noise amplifiers, instrumentation amplifiers, or any offset cancellation amplifier. 
     Buffers, inverters, gating logic, capacitors, resistors, or other elements may be added at various locations in the circuit for a variety of reasons unrelated to the invention, such as for power savings modes. 
     Signals may be encoded, compressed, inverted, combined, or otherwise altered. Clocks may be combined with other signals or conditions. The entire circuit or portions of it could be inverted and p-channel and n-channel transistors swapped. 
     Directional terms such as upper, lower, up, down, top, bottom, etc. are relative and changeable as the system, circuit, or data is rotated, flipped over, etc. These terms are useful for describing the device but are not intended to be absolutes. Signals may be active high or active low, and may be inverted, buffered, encoded, qualified, or otherwise altered. 
     Additional components may be added at various nodes, such as resistors, capacitors, inductors, transistors, etc., and parasitic components may also be present. Enabling and disabling the circuit could be accomplished with additional transistors or in other ways. Pass-gate transistors or transmission gates could be added for isolation. Inversions may be added, or extra buffering. The final sizes of transistors and capacitors may be selected after circuit simulation or field testing. Metal-mask options or other programmable components may be used to select the final capacitor, resistor, or transistor sizes. 
     P-channel rather than n-channel transistors (or vice-versa) may be used for some technologies or processes, and inversions, buffers, capacitors, resistors, gates, or other components may be added to some nodes for various purposes and to tweak the design. Timings may be adjusted by adding delay lines or by controlling delays. Separate power supplies and grounds may be used for some components. Various filters could be added. Active low rather than active high signals may be substituted. 
     While positive currents have been described, currents may be negative or positive, as electrons or holes may be considered the carrier in some cases. Source and sink currents may be interchangeable terms when referring to carriers of opposite polarity. Currents may flow in the reverse direction. A fixed bias voltage may be switched to power or ground to power down the circuit. 
     While Complementary-Metal-Oxide-Semiconductor (CMOS) transistors have been described, other transistor technologies and variations may be substituted, and materials other than silicon may be used, such as Galium-Arsinide (GaAs) and other variations. 
     The background of the invention section may contain background information about the problem or environment of the invention rather than describe prior art by others. Thus inclusion of material in the background section is not an admission of prior art by the Applicant. 
     Any methods or processes described herein are machine-implemented or computer-implemented and are intended to be performed by machine, computer, or other device and are not intended to be performed solely by humans without such machine assistance. Tangible results generated may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio-generating devices, and related media devices, and may include hardcopy printouts that are also machine-generated. Computer control of other machines is another tangible result. 
     Any advantages and benefits described may not apply to all embodiments of the invention. When the word “means” is recited in a claim element, Applicant intends for the claim element to fall under 35 USC Sect. 112, paragraph 6. Often a label of one or more words precedes the word “means”. The word or words preceding the word “means” is a label intended to ease referencing of claim elements and is not intended to convey a structural limitation. Such means-plus-function claims are intended to cover not only the structures described herein for performing the function and their structural equivalents, but also equivalent structures. For example, although a nail and a screw have different structures, they are equivalent structures since they both perform the function of fastening. Claims that do not use the word “means” are not intended to fall under 35 USC Sect. 112, paragraph 6. Signals are typically electronic signals, but may be optical signals such as can be carried over a fiber optic line. 
     The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.