Abstract:
A semiconductor device, comprising: a conductive layer which includes a metal and is formed on a silicon substrate via an insulation layer, the insulation layer being formed by implanting an impurity ion and having a stress changing region with stress different from that of the other region.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-304584, filed on Oct. 19, 2004, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a semiconductor device with a conductive layer formed on a silicon substrate via an insulation layer, and a method of manufacturing the semiconductor device.  
         [0004]     2. Related Art  
         [0005]     Along the progress of miniaturization of semiconductor integrated circuits, gate electrodes made of metal materials having no gate depletion layer has come to be used in place of conventional polysilicon electrodes. In order to improve electric performance of a silicon semiconductor, a channel part is deformed by applying stress to improve mobility, thereby increasing a drive current of a transistor (Japanese Patent Application No. 2002-93921).  
         [0006]     The gate electrode made of a metal material essentially has compressive stress or tensile stress, and mobility of either a PMOS transistor or an NMOS transistor can be improved. This may lead to lower the mobility of the transistor different from the transistor of which mobility is improved.  
       SUMMARY OF THE INVENTION  
       [0007]     The present invention provides a semiconductor device of which mobility can be improved regardless of conduction types of transistors formed on a silicon substrate, and a method of manufacturing the semiconductor device.  
         [0008]     A semiconductor device according to one embodiment of the present invention, comprising:  
         [0009]     a conductive layer which includes a metal and is formed on a silicon substrate via an insulation layer, said insulation layer being formed by implanting an impurity ion and having a stress changing region with stress different from that of the other region.  
         [0010]     Furthermore, a semiconductor device according to one embodiment of the present invention, comprising:  
         [0011]     an insulation layer formed on a silicon substrate;  
         [0012]     a first conductive layer formed on said insulation layer; and  
         [0013]     a second conductive layer which includes a metal and is formed on said first conductive layer,  
         [0014]     wherein said second conductive layer has a stress changing region which is formed by implanting an impurity ion and has stress different from that of the other region.  
         [0015]     Furthermore, a method of fabricating a semiconductor device, comprising:  
         [0016]     forming a conductive layer including a metal on a silicon substrate via an insulation layer; and  
         [0017]     forming a stress changing region with stress different from that of the other region by implanting an impurity ion to a portion of said conductive layer. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]      FIG. 1  is a cross-sectional diagram showing a cross-sectional configuration of a semiconductor device according to a first embodiment of the present invention.  
         [0019]      FIG. 2  is a cross-sectional diagram showing one example of a process of manufacturing the semiconductor device shown in  FIG. 1 .  
         [0020]      FIG. 3  is a cross-sectional diagram subsequent to  FIG. 2 .  
         [0021]      FIG. 4  is a cross-sectional diagram subsequent to  FIG. 3 .  
         [0022]      FIG. 5  is a cross-sectional diagram showing a cross-sectional structure of a semiconductor device according to a second embodiment of the present invention.  
         [0023]      FIG. 6  is a cross-sectional diagrams showing one example of a process of manufacturing the semiconductor device shown in  FIG. 5 .  
         [0024]      FIG. 7  is a cross-sectional diagram subsequent to  FIG. 6 .  
         [0025]      FIG. 8  is a cross-sectional diagram subsequent to  FIG. 7 .  
         [0026]      FIG. 9  is a cross-sectional diagram subsequent to  FIG. 8 .  
         [0027]      FIG. 10  is a cross-sectional diagram showing one example of a semiconductor device.  
         [0028]      FIG. 11  is a cross-sectional diagram showing a cross-sectional configuration of the semiconductor device according to the third embodiment of the present invention.  
         [0029]      FIG. 12  is a cross-sectional diagrams showing one example of the process of manufacturing the semiconductor device shown in  FIG. 11 .  
         [0030]      FIG. 13  is a cross-sectional diagram subsequent to  FIG. 12 .  
         [0031]      FIG. 14  is a cross-sectional diagram subsequent to  FIG. 13 .  
         [0032]      FIG. 15  is a cross-sectional diagram subsequent to  FIG. 14 .  
         [0033]      FIG. 16  is a cross-sectional diagram subsequent to  FIG. 15 .  
         [0034]      FIG. 17  is a diagram showing a modified example of the gate electrode.  
         [0035]      FIG. 18  is a cross-sectional diagram showing a cross-sectional configuration of a semiconductor device according to the fourth embodiment of the present invention.  
         [0036]      FIG. 19  is a cross-sectional diagram of a modification of the configuration shown in  FIG. 18 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0037]     An embodiment according to the present invention will be described more specifically with reference to the drawings.  
       FIRST EMBODIMENT  
       [0038]      FIG. 1  is a cross-sectional diagram showing a cross-sectional configuration of a semiconductor device according to a first embodiment of the present invention. The semiconductor device shown in  FIG. 1  has a PMOS transistor  2  and an NMOS transistor  3  that are adjacently formed on a silicon substrate  1 . Each transistor has a gate insulation film  4  formed on the silicon substrate  1 . The PMOS transistor  2  has a gate electrode  5   a , and the NMOS transistor  3  has a gate electrode  5   b , which are formed on the gate insulation film  4 . The gate electrodes  5   a  and  5   b  are formed with tungsten (W), for example.  
         [0039]     While the gate electrode  5   a  of the PMOS transistor  2  has tensile stress, the gate electrode  5   b  of the NMOS transistor  3  has compressive stress. Stresses in the channel regions  6   a  and  6   b  are opposite type of the stresses in the gate regions  5   a  and  5   b , respectively. Therefore, the channel region  6   a  of the PMOS transistor  2  has compressive stress, and the channel region  6   b  of the NMOS transistor  3  has tensile stress.  
         [0040]     In the PMOS transistor  2 , the channel region  6   a  having compressive stress can improve mobility. Similarly, in the NMOS transistor  3 , the channel  6   b  region having tensile stress can improve mobility. As a result, in the semiconductor device shown in  FIG. 1 , both the PMOS transistor  2  and the NMOS transistor  3  can improve the drive current respectively.  
         [0041]      FIG. 2  to  FIG. 4  are cross-sectional diagrams showing one example of a process of manufacturing the semiconductor device shown in  FIG. 1 . The process of manufacturing the semiconductor device shown in  FIG. 1  is explained below with reference to these drawings. First, a silicon nitride film that becomes a mask is deposited on the silicon substrate  1  via a buffer film. Next, the silicon nitride film, the buffer film, and the silicon substrate  1  are etched to a predetermined depth, according to a pattern transfer method using a resist.  
         [0042]     Next, after removing the resist, a silicon oxide film is deposited on the whole surface, and the surface is flattened by CMP (chemical mechanical polishing) or the like. The silicon nitride film and the buffer film are removed to form an element isolation region (STI: shallow trench isolation)  11  ( FIG. 2 ).  
         [0043]     A gate insulation film  4  is formed on the whole surface of the substrate ( FIG. 2 ). The thickness of the gate insulation film  4  is 3 nanometers or smaller, for example. For the gate insulation film  4 , a thermally-oxidized film that is formed by thermally oxidizing the silicon substrate  1  can be used. Alternatively, an oxynitride film or a nitride film formed by nitriding the silicon substrate  1  can be used. Alternatively, after surface processing, a high dielectric film such as a hafnium nitride film or a hafnium silicate may be formed.  
         [0044]     Next, a metal layer for an electrode is formed on the gate insulation film  4 . For example, a tungsten (W) film  12  having tensile stress is formed ( FIG. 2 ). This film has a thickness of about 100 nanometers, for example.  
         [0045]     A resist  13  or the like is used to mask the region that holds tensile stress ( FIG. 3 ). For example, the PMOS transistor region  2  is covered with the resist  13 , and the tungsten film  12  in the NMOS transistor region  3  is exposed. Impurity ion such as arsenic (As) and boron (B) is injected into the tungsten film  12 . A tungsten film  12   a  injected with the impurity ion has its tensile stress released, so that the stress of the region can be substantially disregarded, or the region changes to the region having compressive stress ( FIG. 4 ).  
         [0046]     The tungsten films  12  and  12   a  are processed by patterning and anisotropic etching like RIE (reactive ion etching) to form the gate electrodes  5   a  and  5   b  ( FIG. 1 ). Widths of the gate electrodes  5   a  and  5   b  are determined according to needs, in a range from a fine pattern of about 10 nanometers to a large pattern of about 10 micrometers or above.  
         [0047]     The surface of the channel disposed opposite to the gate electrode  5   a  of the PMOS transistor  2  made of the tungsten film  12  having tensile stress has compressive stress. The surface of the channel disposed opposite to the gate electrode  5   b  of the NMOS transistor  3  made of the tungsten film  12   a  having compressive stress has tensile stress.  
         [0048]     After forming the configuration as shown in  FIG. 1 , an extension diffusion layer is formed, sidewalls of the gate electrodes  5   a  and  5   b  are formed, and source/drain diffusion layers are formed, using known techniques. Then, an inter-layer film is formed on the whole surface of the substrate, and wiring is formed using a contact process, thereby completing transistors.  
         [0049]     As explained above, according to the first embodiment, the gate electrode  5   a  of the PMOS transistor  2  and the gate electrode  5   b  of the NMOS transistor  3  have mutually different stresses. Therefore, the stress of the channel surface of the PMOS transistor  2  and the stress of the channel surface of the NMOS transistor  3  become opposite to each other. As a result, mobility of both transistors can be improved using stresses, which increases the drive current of the transistors.  
       SECOND EMBODIMENT  
       [0050]     According to the first embodiment, the gate electrode has a single-layer structure including only a tungsten film. Therefore, an electric characteristic like a threshold voltage of a transistor also depends on the characteristic of the tungsten film. More specifically, the electric characteristic like a threshold voltage depends on a work function of a metal that is brought into contact with the gate insulation film  4 . According to a second embodiment, gate electrodes are in a laminated structure, having different metal layers, one metal layer for determining an electric characteristic and the other metal layer for determining stress.  
         [0051]      FIG. 5  is a cross-sectional diagram showing a cross-sectional structure of a semiconductor device according to a second embodiment of the present invention. According to the semiconductor device shown in  FIG. 5 , configurations of the gate electrodes  5   c  and  5   d  are different from those of the gate electrodes  5   a  and  5   b  of the semiconductor device shown in  FIG. 1 . Each of the gate electrodes  5   c  and  5   d  shown in  FIG. 5  has a two-layer structure, having a first metal layer  21  formed on the gate insulation film  4  and a second metal layer formed on the first metal layer  21 . The gate electrode  5   c  has a second metal layer  22   a , and the gate electrode  5   d  has a second metal layer  22   b.    
         [0052]     Each first metal layer  21  is in contact with the gate insulation film  4 , and determines an electric characteristic of the transistor. The first metal layer  21  is formed with titanium nitride (TiN), for example, and has a film thickness of about 5 nanometers. The second metal layers  22   a  and  22   b  determine stress on the channel surface, respectively. Each second metal layer is formed with tungsten, having a film thickness of about 100 nanometers, like the metal layer according to the first embodiment.  
         [0053]      FIG. 6  to  FIG. 9  are cross-sectional diagrams showing one example of a process of manufacturing the semiconductor device shown in  FIG. 5 . The process of manufacturing the semiconductor device shown in  FIG. 5  is sequentially explained with reference to these diagrams. After the gate insulation film  4  is formed on the silicon substrate  1 , titanium nitride  23  is formed on this film  4  to have a thickness of about 5 nanometers ( FIG. 6 ). Tungsten (W)  12  is laminated on the titanium nitride  23  to have a thickness of about 100 nanometers ( FIG. 7 ).  
         [0054]     The subsequent steps are substantially the same as those according to the first embodiment. Briefly explaining, the formation region of the PMOS transistor  2  is masked with the resist  13 , and arsenic (As) or boron (B) ion is injected into the formation region of the NMOS transistor  3 , thereby releasing the tensile stress of the tungsten film  12  in the formation region of the NMOS transistor  3  or providing the tungsten film  12  with compressive stress ( FIG. 8 ).  
         [0055]     Thereafter, the resist  13  is removed ( FIG. 9 ), and the tungsten film  12  is processed to form the gate electrodes  5   c  and  5   d  ( FIG. 5 ).  
         [0056]     As explained above, when the first metal layer  21  is formed with titanium nitride, electric characteristics of the transistors  2  and  3  are determined based on the characteristic of titanium nitride. More specifically, work functions of the gate electrodes  5   c  and  5   d  depend on the work function of titanium nitride, and materials of the second metal layers  22   a  and  22   b  do not influence on electric characteristics, like threshold voltages, of the transistors  2  and  3 . Therefore, electric characteristics of the transistors  2  and  3  and stress on the channel surface can be controlled separately.  
         [0057]     According to the above explanation, the second metal layers  22   a  and  22   b  that determine stresses on the channel surfaces are disposed on the upper surfaces of the first metal layers that determine electric characteristics of the transistors  2  and  3 , respectively. When the first metal layer  21  and the corresponding one of the second metal layers  22   a  and  22   b  react to each other, it is preferable to dispose a reaction prevention film between the first metal layer  21  and the corresponding one of the second metal layers  22   a  and  22   b.    
         [0058]     According to the second embodiment, after obtaining the cross-sectional configuration as shown in  FIG. 5 , an extension diffusion layer is formed, sidewalls of the gate electrodes  5   c  and  5   d  are formed, and source/drain diffusion layers are formed, using known techniques. Then, an inter-layer film is formed on the whole surface of the substrate, and a wiring layer is formed using a contact process, thereby completing transistors.  
         [0059]     The first metal layer  21  of the NMOS transistor  3  and the first metal layer  21  of the PMOS transistor  2  can be formed by using mutually different metals, thereby employing what is called a dual-metal electrode. For example, platinum silicon (PtSi) is used for the first metal layer  21  of the PMOS transistor  2 , and titanium carbide (TiC) is used for the first metal layer  21  of the NMOS transistor  3 . The gate electrodes  5   c  and  5   d  can be formed in laminated structure having three or more film layers, respectively. Alternatively, one of the PMOS transistor  2  and the NMOS transistors  3  can have a laminated structure, and the other transistor has a single-layer structure.  
         [0060]      FIG. 10  is a cross-sectional diagram showing one example of a semiconductor device in which the gate electrode  5   a  of the PMOS transistor  2  has a single-layer structure, and the gate electrode  5   d  of the NMOS transistor  3  has a two-layer structure. In  FIG. 10 , the gate electrode  5   d  of the NMOS transistor  3  has the first metal layer  21  formed on the gate insulation film  4 , and the second metal layer  22   b  formed on the first metal layer  21 , like the gate electrode  5   d  shown in  FIG. 5 .  
         [0061]     As explained above, according to the second embodiment, the first metal layers  21  that determine the electric characteristics of the corresponding transistors  2  and  3 , and the second metal layers  22   a  and  22   b  that determine the stresses of the channel surfaces of the corresponding transistors  2  and  3  are used to form the gate electrodes  5   a  and  5   d , respectively. Therefore, the electric characteristics of the transistors and the stresses of the channel surfaces can be controlled mutually independently. Consequently, transistors having excellent electric characteristics and high mobility can be formed.  
       THIRD EMBODIMENT  
       [0062]     According to a third embodiment, a semiconductor device is manufactured using a damascene process.  
         [0063]      FIG. 11  is a cross-sectional diagram showing a cross-sectional configuration of the semiconductor device according to the third embodiment of the present invention. The semiconductor device shown in  FIG. 11  has the PMOS transistor  2  and the NMOS transistor  3  manufactured according to the damascene process.  
         [0064]     The gate electrode  5   a  of the PMOS transistor  2  and the gate electrode  5   b  of the NMOS transistor  3  are formed using tungsten (W) around a gate trench formed on the substrate, respectively. The gate electrode  5   a  of the PMOS transistor  2  has tensile stress, and the gate electrode  5   b  of the NMOS transistor  3  has compressive stress.  
         [0065]      FIG. 12  to  FIG. 16  are cross-sectional diagrams showing one example of the process of manufacturing the semiconductor device shown in  FIG. 11 . The process of manufacturing the semiconductor device shown in  FIG. 11  is explained sequentially with reference to these diagrams. First, the element region and the element isolation region (STI)  11  are formed on the silicon substrate  1 , and a silicon oxide film is formed on the whole surface as a buffer film, in a similar manner to that according to the first embodiment.  
         [0066]     Next, polysilicon and a silicon nitride film  30  are formed on the whole surface of the substrate as a dummy gate film. Anisotropic etching is carried out using a resist, to form a dummy gate electrode. An extension diffusion layer region is formed, and a sidewall  24  is formed around the gate electrodes  5   a  and  5   b , using known techniques. An impurity iron is injected to form a source/drain diffusion layer. By activating the impurity ion, a source/drain region  25  is formed. According to needs, a silicide film is formed in the source/drain region  25 .  
         [0067]     Next, for example, a silicon oxide film is deposited on the whole surface of the substrate, and the deposited silicon oxide film is etched by the CMP method or the etch-back method, thereby flattening the surface and exposing the upper surface of the dummy gate film.  
         [0068]     The silicon nitride film and the polysilicon film are etched, and the buffer oxide film is removed with diluted hydrofuloric acid solution to expose the silicon substrate  1 , thereby forming a gate trench  26  to form the gate electrodes  5   a  and  5   b  ( FIG. 12 ).  
         [0069]     Next, the gate insulation film  4  is formed on the upper surface of the substrate including the inside of the gate trench  26  ( FIG. 13 ). For example, the silicon substrate  1  can be oxidized, or a high dielectric film can be deposited on the whole surface of the substrate.  
         [0070]     The metal layer (for example, tungsten having tensile stress)  12  that becomes the gate electrodes  5   a  and  5   b  is formed on the upper surface of the gate insulation film  4  ( FIG. 14 ). The upper surface of the metal layer is flattened with CMP (chemical mechanical polishing) or the like, and the tungsten and the gate insulation film  4  other than the gate trench  26  are removed ( FIG. 15 ).  
         [0071]     The region having tensile stress (the formation region of the PMOS transistor  2 ) is masked with the resist  13 , and impurity ion such as arsenic (As) and boron (B) is injected into the formation region of the NMOS transistor  3  ( FIG. 16 ), in a similar manner to that according to the first embodiment. As a result, the formation region of the NMOS transistor  3  has its tensile stress released, and the stress of the region can be substantially disregarded, or the region has compressive stress ( FIG. 11 ).  
         [0072]     While an example of forming the gate electrodes  5   a  and  5   b  in a single-layer structure is explained above with reference to  FIG. 11  to  FIG. 16 , the gate electrodes  5   a  and  5   b  in a laminated structure can be also formed in a similar manner to that according to the second embodiment. Alternatively, the gate electrodes  5   a  and  5   b  can be in a T-shape as shown in  FIG. 17 . After the process shown in  FIG. 14 , the gate electrodes  5   a  and  5   b  shown in  FIG. 17  are formed by processing the tungsten film  12  according to patterning and reactive ion etching.  
         [0073]     The inter-layer film and the contact are sequentially formed, in a similar manner to that applied to usual transistors.  
         [0074]     As explained above, according to the third embodiment, when the PMOS transistor  2  and the NMOS transistor  3  are formed using the damascene process, stresses of the gate electrodes  5   a  and  5   b  of both transistors are reversed, and mobility can be improved regardless of types of transistors.  
       FOURTH EMBODIMENT  
       [0075]     According to a fourth embodiment, the gate electrodes are in a laminated structure, respectively, and a metal layer that influence stress on the channel is formed on upper layer of both the gate electrodes.  
         [0076]      FIG. 18  is a cross-sectional diagram showing a cross-sectional configuration of a semiconductor device according to the fourth embodiment of the present invention. The semiconductor device shown in  FIG. 18  has the PMOS transistor  2  and the NMOS transistor  3 , and both transistors have gate electrodes  5   e  and  5   f  in a three-layer structure, respectively. Each of the gate electrodes  5   e  and  5   f  has the polysilicon layer  21  formed on the gate insulation film  4 , a barrier layer  27  formed on the polysilicon layer  21 , and a tungsten film formed on the barrier layer  27 . The gate electrode  5   e  has a tungsten film  28   a , and the gate electrode  5   f  has a tungsten film  28   b.    
         [0077]     The tungsten film as the material for the gate electrode  5   e  of the PMOS transistor  2  has tensile stress, and the tungsten film as the material for the gate electrode  5   f  of the NMOS transistor  3  has compressive stress.  
         [0078]     A process of manufacturing the semiconductor device shown in  FIG. 18  is briefly explained below. The element region and the element isolation region  11  are formed on the silicon substrate  1 . The gate insulation film  4  is formed on the substrate  1 , and the polysilicon layer  21  is formed on the gate insulation film  4 . An impurity ion is injected into the polysilicon layer  21 . Alternatively, the polysilicon layer  21  containing the impurity ion can be formed on the gate insulation film  4  in advance. The impurity ion is activated in a thermal process, and tungsten nitride (WN) is formed as the barrier layer  27  on the upper surface of the substrate. The tungsten film  12  is formed on the upper surface of the barrier layer  27 .  
         [0079]     The formation region of the PMOS transistor  2  is masked with a resist, and impurity ion such as arsenic (As) or boron (B) is injected into the formation region of the NMOS transistor  3 , thereby releasing the tensile stress of the tungsten film  12  or providing the tungsten film  12  with compressive stress, in a similar manner to that according to the first to the third embodiments.  
         [0080]     Then, in a similar manner to that according to the first to the third embodiments, the gate electrodes  5   e  and  5   f  are processed, and an extension diffusion layer is formed, gate sidewalls are formed, and source/drain diffusion layers are formed, using known techniques. Then, an inter-layer film is formed on the whole surface of the substrate, and wiring is formed using a contact process, thereby completing transistors, in a similar manner to that according to the first to the third embodiments.  
         [0081]     The polysilicon layer  21  is used to determine work functions of the gate electrodes  5   e  and  5   f , and electric characteristics like threshold voltages of the transistors are determined based on the work functions.  
         [0082]     As explained above, according to the fourth embodiment, a polysilicon layer is formed as a lower layer of the gate electrodes  5   e  and  5   f , respectively. Therefore, the electric characteristics of the transistors can be controlled. The tungsten film  12  is formed as an upper layer of the gate electrodes  5   e  and  5   f , respectively, to control stress. Therefore, the stress of the channel surface of the PMOS transistor  2  and the stress of the channel surface of the NMOS transistor  3  can be reversed, thereby improving mobility of both transistors.  
         [0083]      FIG. 19  is a cross-sectional diagram of a modification of the configuration shown in  FIG. 18 . Each of gate electrodes  5   g  and  5   h  shown in  FIG. 19  has a silicide layer  29  formed on the upper surface of the tungsten film  28   a  or  28   b  via the barrier layer  27 . By forming the silicide layer  29  as a top layer of the gate electrodes  5   g  and  5   h , respectively, the total resistance of the gate electrodes  5   g  and  5   h  can be lowered.  
         [0084]     The present invention is not limited to the above embodiments, and can be implemented by modifying the embodiments without departing from the scope of the present invention. For example, the substrate is not limited to the silicon substrate  1 , and the invention can be applied to an SOI (silicon-on-insulator) substrate having a silicon active layer formed on the insulation film. While mobility is different depending on a plane direction of the substrate, a plane direction is not limited according to the present invention.  
         [0085]     The present invention can be also applied to transistors having a three-dimensional configuration such as Fin-type channel gate electrodes  5   g  and  5   h , in addition to a plane transistor.  
         [0086]     In the above embodiments, while ion injection to release stress is carried out before processing the gate electrodes, ion can be injected after processing the gate electrodes. To release stress, thermal processing can be carried out in addition to the ion injection.  
         [0087]     While tungsten has been taken up as an example of a metal having stress, silicide such as titanium silicon can be also used. Injected impurity ion is not limited to arsenic (As) or boron (B). Various other kinds of impurity ion, such as germanium (Ge) and indium (In), can be also used.  
         [0088]     While TiN has been taken up as an example of a metal that influences the electrical characteristics, nitrides (TiN, ZrN, HfN, Ta 2 N, and WN) or bromides (TiB 2 , ZrB 2 , HfB 2 , TaB 2 , MoB 2 , and WB) of other metals (Ti, Zr, Hf, Ta, and W), and silicides (PtSi, and WSi) can be also used.  
         [0089]     For the gate electrode  4 , high dielectric and its oxide, oxynitride, and silicate can be also used, other than an oxidized film or hafnium.