Abstract:
A protection circuit used to protect a first metal-oxide-semiconductor field effect transistor (MOSFET) includes a control circuit and a conversion circuit. The control circuit includes a negative temperature coefficient thermistor. When a temperature of the first MOSFET is not higher than a preset value, the control circuit controls the conversion circuit to operate normally. When the temperature of the first MOSFET is higher than the preset value, the control circuit stops the operating of the first MOSFET.

Description:
FIELD 
       [0001]    The present disclosure relates to a protection circuit. 
       BACKGROUND 
       [0002]    Heat is generated when a metal-oxide-semiconductor field effect transistor (MOSFET) is operating in a circuit. If a temperature of the MOSFET is higher than a breakdown temperature, the MOSFET can be punctured which may damage the circuit. 
         [0003]    Therefore, there is room for improvement in the art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
         [0004]    Many aspects of the present disclosure can be better understood with reference to the following drawing(s). The components in the drawing(s) are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawing(s), like reference numerals designate corresponding parts throughout the several views. 
           [0005]    The FIGURE is a circuit diagram of an embodiment of a protection circuit of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0006]    The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.” The reference “a plurality of” means “at least two.” 
         [0007]    The FIGURE shows an embodiment of a protection circuit  10  of the present disclosure. 
         [0008]    The protection circuit  10  comprises a conversion circuit  20  and a control circuit  30 . 
         [0009]    The conversion circuit  20  comprises a driving chip U 1 , a inductor L, capacitors C 1  and C 2 , resistors R 1  and R 2 , and n-channel metal-oxide-semiconductor field effect transistors (MOSFETs) Q 1  and Q 2 . A power pin VCC of the driving chip U 1  is connected to a power input terminal V1. A first driving pin Hgate of the driving chip U 1  is connected to a gate of the MOSFET Q 1 . A drain of the MOSFET Q 1  is connected to a second power input terminal V2. The drain of the MOSFET Q 1  is also grounded through the capacitor C 1 . A source of the MOSFET Q 1  is connected to a phase pin Phase of the driving chip U 1 . A second driving pin Lgate of the driving chip U 1  is connected to a gate of the MOSFET Q 2 . A drain of the MOSFET Q 2  is connected to the phase pin Phase of the driving chip U 1 . A source of the MOSFET Q 2  is grounded. The phase pin Phase of the driving chip U 1  is grounded through the inductor L, the resistors R 1  and R 2  in that order. A node between the inductor L and the first resistor R 1  is grounded through the capacitor C 2 . A node between the resistors R 1  and R 2  is connected to a feedback pin FB of the driving chip U 1 . 
         [0010]    The control circuit  30  comprises an electronic switch, such as a n-channel MOSFET Q 3 , resistors R 3  to R 6 , and an operational amplifier U 2 . A terminal of the resistor R 3  is connected to a third power input terminal V3. Another terminal of the resistor R 3  is grounded through the resistor R 4 . A terminal of the resistor R 5  is connected to the first power input terminal V1. Another terminal of the resistor R 5  is grounded through the resistor R 6 . A non-inverting input of the operational amplifier U 2  is connected to a node between the resistors R 5  and R 6 . An inverting input of the operational amplifier U 2  is connected to a node between the resistor R 3  and R 4 . An output of the operational amplifier U 2  is connected to a gate of the MOSFET Q 3 . A drain of the MOSFET Q 3  is connected to the gate of the MOSFET Q 1 . A source of the MOSFET Q 3  is grounded. The resistor R 5  is a negative temperature coefficient thermistor and placed near the MOSFET Q 1 . A resistance of the resistor R 5  has a negative temperature coefficient with a temperature of the MOSFET Q 1 . When the temperature of the MOSFET Q 1  is not higher than a first preset value, the resistance of the resistor R 5  is not less than a second preset value. A voltage of the non-inverting input of the operational amplifier U 2  is not higher than a voltage of the inverting input of the operational amplifier U 2 . The operational amplifier U 2  outputs a low level signal, such as logic 0. When the temperature of the MOSFET Q 1  is higher than the first preset value, the resistance of the resistor R 5  is less than the second preset value. The voltage of the non-inverting input of the operational amplifier U 2  is higher than the voltage of the inverting input of the operational amplifier U 2 . The operational amplifier U 2  outputs a high level signal, such as logic 1. 
         [0011]    When the protection circuit  10  is operating, the driving chip U 1  outputs pulse signals alternately through the first driving pin Hgate and the second driving pins Lgate. Thus when the MOSFET Q 1  is turned on, the MOSFET Q 2  is turned off. The second power input terminal V2 charges the inductor L and the capacitor C 2 . When the MOSFET Q 1  is turned off, the MOSFET Q 2  is turned on. The inductor L and the capacitor C 2  discharges. When the temperature of the MOSFET Q 1  is not higher than the first preset value, the operational amplifier U 2  outputs a low level signal, such as logic 0. The MOSFET Q 3  is turned off The conversion circuit  20  operates normally. When the temperature of the MOSFET Q 1  is higher than the first preset value, the operational amplifier U 2  outputs a high level signal, such as logic 1. The MOSFET Q 3  is turned on. The gate of the MOSFET Q 1  is grounded. The MOSFET Q 1  is turned off to stop generating heat. 
         [0012]    While the disclosure has been described by way of example and in terms of preferred embodiment, it is to be understood that the disclosure is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.