Abstract:
An embedded system and method for controlling such are disclosed. The embedded system includes a direct memory controller comprising a plurality of channels, wherein a plurality of channel arbitration schemes are programmable, wherein the DMA controller is programmable to split a block data transfer on a specified channel into a plurality of separate data transfers, wherein a data transfer on a specified channel can be interrupted between separate data transfers of the data transfer.

Description:
CROSS-REFERENCE To RELATED APPLICATIONS 
       [0001]    This application claims priority to commonly owned U.S. Provisional Patent Application No. 62/169,354 filed Jun. 1, 2015, which is hereby incorporated by reference herein for all purposes. 
     
    
     TECHNICAL FIELD 
       [0002]    The present disclosure relates to a method and apparatus for split burst bandwidth arbitration in particular in direct memory access (DMA) controllers. 
       BACKGROUND 
       [0003]    Many embedded systems, such as microcontrollers, comprise a DMA controller that allows for an efficient and fast data transfer over the internal system bus of the microcontroller. A bus, in particular a system bus in an embedded system, generally allows various components of the embedded system to communicate. DMA controllers often provide for a so-called burst operations that provide for a large data transfers at high speed. However, such burst operations may block the entire bus and other components that require access will not be able to access the bus until the burst transfer has been completed. Thus, additional measures to keep account of the request and status of the pending transactions are required. 
       SUMMARY 
       [0004]    There exists a need to prevent a low priority agent to occupy the bus for an extended period of time in burst operation. By splitting the burst operation into transactions, the bus bandwidth can be shared among other modules. 
         [0005]    An embedded system and method for controlling such are disclosed. The embedded system includes a direct memory controller comprising a plurality of channels, wherein a plurality of channel arbitration schemes are programmable, wherein the DMA controller is programmable to split a block data transfer on a specified channel into a plurality of separate data transfers, wherein a data transfer on a specified channel can be interrupted between separate data transfers of the data transfer. 
         [0006]    According to various embodiments, an embedded system is disclosed. The embedded system may include a direct memory controller comprising a plurality of channels, wherein a plurality of channel arbitration schemes are programmable, wherein the DMA controller is programmable to split a block data transfer on a specified channel into a plurality of separate data transfers, wherein a data transfer on a specified channel can be interrupted between separate data transfers of the data transfer. 
         [0007]    In some embodiments, the arbitration schemes includes a round-robin scheme and a fixed priority scheme. In other embodiments, the arbitration schemes includes a round-robin scheme and an assignable priority scheme. In some embodiments, a block data transfer may be split into the plurality of separate data transfers upon setting of a bit in a control register. 
         [0008]    In some embodiments, a separate data transfers may include a programmable maximum of data bytes. In such embodiments, the programmable maximum is a value stored in a control register. 
         [0009]    In some embodiments, a separate data transfers may include a fixed number of data bytes. In such embodiments, the fixed number of data bytes may be one byte. 
         [0010]    In various embodiments, a method for operating an embedded system is disclosed. The method may include operating a direct memory controller comprising a plurality of channels, wherein a plurality of channel arbitration schemes are programmable, and programming the DMA controller to split a block data transfer on a specified channel into a plurality of separate data transfers, wherein a data transfer on a specified channel can be interrupted between separate data transfers of the data transfer. 
         [0011]    In some embodiments of the method, the arbitration schemes may include a round-robin scheme and a fixed priority scheme. In other embodiments, the arbitration schemes may include a round-robin scheme and a assignable priority scheme. 
         [0012]    In some embodiments of the method a block data transfer may be split into the plurality of separate data transfers upon setting of a bit in a control register. In the same or alternative embodiments, a separate data transfers may include a programmable maximum of data bytes. In such embodiments, the programmable maximum is a value stored in a control register. 
         [0013]    In some embodiments of the method, a separate data transfers may include a fixed number of data bytes. In such embodiments, the fixed number of data bytes may be one byte. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  shows a typical embedded system, such as a microcontroller including a central processing unit coupled with an internal system bus which connects the various peripheral devices of the microcontroller, in accordance with certain embodiments of the present disclosure; 
           [0015]      FIG. 2  illustrates an example typical data transfer of three channels according to this scheme, in accordance with certain embodiments of the present disclosure; and 
           [0016]      FIG. 3  shows an example in which the transfer for channel  1  is broken into a number of sub-transactions, in accordance with certain embodiments of the present disclosure 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    There exists a need to prevent a low priority agent to occupy the bus for an extended period of time in burst operation. By splitting the burst operation into transactions, the bus bandwidth can be shared among other modules. 
         [0018]      FIG. 1  shows a typical embedded system  100 , such as a microcontroller including a central processing unit (CPU)  110  coupled with an internal system bus which connects the various peripheral devices  130 - 150  of the microcontroller, in accordance with certain embodiments of the present disclosure. One of the peripheral devices can be a direct memory access controller (“DMA” or “controller”)  150  that allows data transfers between the peripherals  130 ,  140 , etc. and memory  160  or within the memory  160 . An embedded DMA controller  150  provides for a plurality of transmission channels, for example 16 channels, wherein each channel may have an assignable or fixed channel priority or the controller  150  may use a round-robin assignment. Each channel operation may be triggered by a respective signal. If multiple selected triggers occur among multiple channels simultaneously, the DMA macro is designed to select the next channel for service, based on either the round-robin or a fixed priority scheme. Note that both schemes share the following common characteristics according to some embodiments: 
         [0019]    In some embodiments, for each trigger, all associated transactions must be completed. For a “one-shot” transfer mode, the next channel may be serviced while the current channel is waiting for the next trigger. For a “continuous” modes, the next channel will only get serviced when the current channel&#39;s counter (e.g., “CNT[15:0]”) is decremented to zero. In the same or alternative embodiments, both read and write transaction combinations must be completed before servicing another channel to avoid data ordering issues. 
         [0020]    In some embodiments, grant determination is evaluated for every instruction cycle. The process starts with determining the requesting channel that currently has the highest priority based on a set scheme. Then the grant is given only when the bus bandwidth of the winning DMA channel is available. If the bandwidth of the particular bus being requested by the winning DMA channel is unavailable, the process is repeated in the next instruction cycle. 
         [0021]    In some embodiments, a “round robin” priority scheme may be used. In such a scheme, priority may be used (for example) at least when a priority bit is set in a control register. For example, when the DMACON.PRIORITY bit in a respective control register is set low, a round-robin priority scheme is employed in selecting the next DMA channel for service. For example, if the scheme begins with channel  0 , the next channel to be selected is the channel with the lowest channel number down the round. For example, if channels 0, 1, and 2 are triggered simultaneously, channel 0 will be scheduled for service first, then channel 1 and channel 2 are serviced, respectively. Table 1 below illustrates this example default setting.  FIG. 2  illustrates an example typical data transfer of three channels according to this scheme, in accordance with certain embodiments of the present disclosure. 
         [0000]    
       
         
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 CH0 req 
                 CH1 req 
                 CH2 req 
                 CH3 req 
                 CH granted 
               
               
                   
               
             
             
               
                 — 
                 — 
                 — 
                 — 
                 none 
               
               
                 — 
                 yes 
                 — 
                 — 
                 CH1 
               
               
                 yes 
                 yes 
                 yes 
                 — 
                 CH2 
               
               
                 yes 
                 yes 
                 — 
                 — 
                 CH0 
               
               
                 yes 
                 yes 
                 — 
                 — 
                 CH1 
               
               
                 yes 
                 yes 
                 — 
                 yes 
                 CH3 
               
               
                 yes 
                 yes 
                 — 
                 — 
                 CH0 
               
               
                   
               
             
          
         
       
     
         [0022]    In some configurations however, if channel 0 is triggered again at any time thereafter, it will be serviced first only at the start of the next round. Even if channel 1 is triggered again after having been serviced before channel 0 is triggered the second time, channel 1 will be serviced after channel 0 at the second round. 
         [0023]    In some embodiments, a “fixed” priority scheme may be used. In such a scheme, priority may be used (for example) at least when a priority bit is set in a control register. For example, when the DMACON.PRIORITY bit is set high in a respective control register, the priority scheme is fixed based on the channel number. For example, starting with channel 0, the next channel to be selected is the channel with the lowest channel priority regardless of what has transpired before. For example, if channel 0, 1, and 2 are triggered simultaneously, channel 0 will be scheduled for service first, followed by channel 1 and channel 2, respectively. If channel 0 is triggered again, it will be scheduled for service once the current iteration (made up of one or more transactions) is completed. Table 2 below illustrates an example setting for such a scheme. 
         [0000]    
       
         
               
               
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 CH0 req 
                 CH1 req 
                 CH2 req 
                 CH3 req 
                 CH granted 
               
               
                   
               
             
             
               
                 — 
                 — 
                 — 
                 — 
                 none 
               
               
                 — 
                 yes 
                 — 
                 — 
                 CH1 
               
               
                 yes 
                 yes 
                 yes 
                 — 
                 CH0 
               
               
                 yes 
                 yes 
                 — 
                 — 
                 CH0 
               
               
                 — 
                 yes 
                 — 
                 — 
                 CH1 
               
               
                 — 
                 yes 
                 — 
                 yes 
                 CH1 
               
               
                 — 
                 — 
                 — 
                 yes 
                 CH3 
               
               
                   
               
             
          
         
       
     
         [0024]    In many systems, multiple DMA channels are found. Certain arbitration schemes typically use fixed priorities and bus access may typically be granted for an entire transfer which cannot be interrupted as shown in  FIG. 2 . These type of schemes allow long running low priority transfers to delay the servicing of high priority requests significantly. 
         [0025]    According to various embodiments, the channel state is maintained which makes transfers interruptible and makes transfers resumable. Furthermore, a transfer is broken into a number of sub-transactions (e.g., at byte level) which may allow as many arbitration opportunities as possible.  FIG. 3  shows an example in which the transfer for channel  1  is broken into a number of sub-transactions  210   a ,  210   b ,  210   c ,  210   d , and  210   e , in accordance with certain embodiments of the present disclosure. Similarly, the transfer on channel 0 is broken into sub-transactions  200   a ,  200   b , and  200   c.  A transfer on channel  2  is broken into sub-transactions  220   a  and  220   b.  Various arbitration schemes can be implemented, and they can be applied per transaction rather than per-transfer, which may allow the splitting of a low priority burst transfer by a higher priority transfer. The example in  FIG. 3  illustrates the referenced sub-transactions in a fixed priority scheme similar to that describe above with reference to  FIG. 2 . Assuming channel 1 and channel 2 request a transfer at a first time t1, due to the higher priority the transfer of channel 1 starts first. However, the transfer may be broken into the interruptible sub-transactions  210   a - e.  Thus, when channel 0 requests a transfer at time t2, the channel 0 transfer will be interrupted and will resume at time t3. At time t4, channel 2 requests a transfer which will be granted because no higher priority transfer is pending. 
         [0026]    The various embodiments provide for the following advantages: Embedded systems have different usage profiles from other computers. In embedded systems latency is a more likely critical system characteristic instead of throughput. Systems will be able to meet minimum reaction times orders of magnitude better than currently possible. This increases the problem domain serviceable with 8-bit microcontrollers.