Abstract:
A high gain integrated circuit amplifier is arranged in the form of a pair of cascaded common emitter stages. A current mirror is employed to track the stage currents. A high gain d-c negative feedback loop is employed to stabilize the amplifier, and each stage employs emitter diode degeneration to control gain as a function of current. Gain control is obtained by sinking current at a single node in one stage.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to signal amplifying circuits such as the r-f and i-f amplifiers found in radio receivers. The circuit is adapted for integrated circuit (IC) construction, and represents a variable gain block that can be employed singly or cascaded as desired. Prior art circuits often tended to become unstable, particularly with the application of automatic gain control (AGC). Accordingly, the prior art AGC circuits have been complicated and the circuits difficult to temperature compensate. In addition, the prior art circuits tend to overload in the presence of strong signals. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to provide an IC amplifier circuit having a single terminal wide range gain control action. 
     It is a further object of the invention to provide a simple temperature compensated, d-c stabilized, signal amplifier in IC form that has wide AGC range and responds to strong signals without overloading. 
     These and other objects are achieved in an amplifier circuit configured as follows. A first common emitter gain stage is emitter follower coupled to a second common emitter gain stage. The two gain stages are operated from a current mirror so that their currents track and both stages employ forward biased diode emitter resistance degeneration to control gain as a function of current. A d-c negative feedback loop is employed to stabilize the two stages. Gain control is applied by current sinking a single circuit node to provide a large control range. By cascading a plurality of forward biased diodes in the emitter of the input stage, signal overload is substantially reduced. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a schematic diagram of the circuit of the invention,  and 
     FIG. 2 is a fragmentary schematic diagram of an improved portion of the circuit of FIG. 1. 
    
    
     DESCRIPTION OF THE INVENTION 
     In the description that follows, a rigorous transistor current analysis will be avoided. The approximate description is sufficiently accurate to determine how the circuit and the invention operate. For example, in describing transistor action to a first approximation, base currents can be neglected. Since the base current in a typical transistor in its active state will be on the order of 0.5% of the collector current, ignoring the base current will not introduce serious error. 
     In the circuit of FIG. 1, power is supplied at +V, terminal 10, with respect to ground. An input signal at terminal 11 is coupled by capacitor 12 to the base of transistor 13 which acts as the first gain stage. Resistor 14 acts as the load for transistor 13. Emitter follower transistor 15 with its output load resistor 16 couples the output from transistor 13 to the base of transistor 17 at substantially unity voltage gain. Transistor 17 is the second gain stage and employs Z L  at 18 as its output load. Z L  is typically an antiresonant tank circuit which establishes the amplifier frequency characteristics. Terminal 19 comprises the amplifier output. 
     The emitter of transistor 13 is returned to ground through a pair of diode connected transistors 21 and 22. These diodes are forward biased, and conduct the emitter current of transistor 13. Diodes 21 and 22 each present a series resistance known as r e  which is defined as the forward biased emitter junction resistance. Its value will be: ##EQU1##   where:k = Boltzmanns constant 
     T = absolute temperature 
     q = Charge on an electron; and 
     I = current flow 
     The resistance r e  is relatively small, typically 26 ohms at 25° C and at one ma., and decreases with increasing current. 
     Transistors 22 and 23 are connected as a conventional current mirror. Thus, any current flowing in diode connected transistor 22 will be tracked as collector current in transistor 23. If the emitter areas of transistors 22 and 23 are the same, the emitter current of transistor 23 will equal the emitter current of transistor 22. Typically, these two emitters are made equal, but, if desired can be ratioed. 
     Diode connected transistor 24 returns the emitter of transistor 17 to circuit node 25 which is at signal ground by virtue of signal bypass capacitor 26. Resistor 27 returns the base of transistor 13 to circuit node 25. As indicated in dashed outline at 33, resistor 27 can be shunted or replaced by an inductor. If desired, inductor 33 can be the secondary winding of an input transformer, the primary of which constitutes the circuit input terminals. In this latter case, capacitor 12 would be omitted. 
     Circuit node 29 is the automatic gain control (AGC) terminal. Current labeled I AGC  sunk out of terminal 29 to ground will act to reduce the overall amplifier gain. The AGC action requires a detector 30 and a d-C amplifier 31, shown in block form, to complete the circuit. 
     The gain stages, which involve transistors 13 and 17, are stabilized by a negative d-c feedback loop. It can be seen that the collector of transistor 13 is directly coupled via transistors 15, 17, and 24 and resistor 27 (or inductor 33) back to its base. Since this loop involves no inversions, the feedback is negative. Bypass capacitor 26 acts as a signal ground for node 25 and ensures that the negative feedback is only present at low frequencies and not for signal frequencies. 
     It can be seen that circuit node 25 is 3V BE  above ground due to transistors 13, 21, and 22. Circuit node 29 is 3V BE  above circuit node 25 due to transistors 15, 17, and 24. Accordingly: ##EQU2## where: +V is the supply potential; and R14 is the value of resistor 14. 
     An inspection of the circuit at node 29 shows that: 
     
         I.sub.2 = I.sub.1 - I.sub.AGC                              (3) 
    
     by virtue of the current mirror action of transistors 22 and 23, I 3  equals I 2 . 
     The gain of transistor 13 is: ##EQU3## where: R14 is the resistance of resistor 14; and 3r e  is the emitter resistances of series connected transistors 13, 21, and 22. 
     The gain of transistor 17 is: ##EQU4## where: Z L  is the impedance of load 18; and 2r e  is the emitter resistances of transistors 17 and 24. 
     The overall gain between terminals 11 and 19 is the cascaded gain of transistors 13 and 17 which is: ##EQU5## 
     Equation (6 ) shows that substantial overall gain is available because Z L  and R14 can be made extremely large compared with 6r e .sup. 2. Equation (5) further shows that since r e  is a function of current, the gain can be varied strongly as a function of current due to the 6r e .sup. 2 term. From a circuit standpoint it can be seen that transistor 13 has its gain degenerated by three series connected r e  values. Transistor 17 will have its gain degenerated by two series connected r e  values. The cascade then responds to the square of the r e  value. 
     As I AGC  is pulled out of circuit node 29, I 2  and hence I 3  will be decreased by the magnitude of I AGC . This causes r e  to increase and the amplifier gain will be reduced in proportion to the square of r e . Since three r e  drops appear in the emitter circuit of transistor 13, and these values rise with increasing signal at terminal 11, the amplifier is highly resistant to overloading. 
     From the above, it can be seen that a single circuit node is used to gain control the amplifier. The amplifier is extremely stable, difficult to overload, and highly responsive to AGC action. 
     The circuit of FIG. 1 was fabricated in conventional IC form using state of the art devices and components. The transistors were of the NPN variety with Beta values of about 200. Capacitors 12 and 26, Z L  18, and resistor 27 were located off chip. 
     The following component values were employed: 
     
         ______________________________________Capacitor 12   .01 microfaradsResistor 14    2K OhmsResistor 16    3.6K OhmsLoad 18        455 KHz antiresonant circuit          Z.sub.L = 35K OhmsCapacitor 26   5 microfaradsResistor 27    2K Ohms______________________________________ 
    
     The circuit operated from a 8-volt supply. 
     The zero signal value of I 1  was about 2 ma. The circuit had a small signal gain of 97 db, an AGC range in excess of 90 db, and an overload level of about 100 millivolts. 
     For the circuit of the example, node 29 will operate at about 4 volts above ground at 25° C. If tamperature rises, the amplifier gain will tend to fall as r e  has a positive coefficient. However, the potential at node 29 will decrease and cause a compensating increase in current through resistor 14 or I 1 , and hence I 2  and I 3 . This increased current will reduce r e  of transistors 13, 21, 22, 17, and 24 so as to increase gain. For the conditions shown in the example, the gain will be substantially compensated. 
     FIG. 2 shows a useful modification of the circuit of FIG. 1. Transistor 30 is coupled in series with the collector of transistor 17 and two resistors 31 and 32 from a voltage divider to set the base voltage of transistor 30. This cascode amplifier connection improves the performance of the gain stage by reducing Miller effect capacitance loading at the base of transistor 17. This substantially increases the high frequency gain of the amplifier. 
     Clearly, there are other modifications and equivalents that could be applied within the spirit and intent of the invention. For example, diode connected transistors 21 and 24 could be omitted with an attendant reduction in AGC and overload performance. Additional diode connected transistors could be added in series with transistors 21 and 24 with further performance improvements. However, the addition of more diode connected transistors produces diminishing performance increases. 
     Accordingly, it is intended that the invention be limited in scope by the claims that follow.