Abstract:
A method for reclosing a temporarily opened circuit breaker in a manner which assures that generation of unwanted overvoltage stresses is avoided during the reclosure process. An oscillating line voltage typically develops in a shunt-compensated line after a circuit breaker connecting the line to a voltage source is opened. When the circuit breaker is reclosed the source voltage and the oscillating voltages must be properly phased to avoid the overstressing problem. In operation, the polarities of the feed voltage and the oscillating line voltage are detected and the instant when the circuit breaker may be reclosed is calculated. The periods T L  and T S  of the line voltage and the feed voltage are measured. Also measured is the time ΔT which elapses from a zero crossing of the line voltage waveform to a subsequent zero crossing of the feed voltage waveform having the same phase angle as that of the line voltage zero crossing. The circuit breaker is reclosed upon satisfying the relationship: 
     
       |nT.sub.L -(ΔT+mT.sub.S)|≦(T.sub.L 
     
      -T S )/2 
     where m, n are natural numbers which are sequentially entered in the above equation.

Description:
BACKGROUND AND SUMMARY OF THE INVENTION 
     The invention is directed to a method for determining the time of reclosing a circuit breaker. 
     The invention relates to a prior art as described in the report &#34;Measures taken to reduce overvoltages when energizing no-load lines&#34; by G. Koppl in Surges in High Voltage Networks, edited by K. Ragaller, Plenum Press New York 1980. 
     In electric systems which feed voltages of greater than or equal to 362 kV, the necessary insulation is determined by the circuit voltage loading. A critical situation arises during rapid reclosing of circuit breakers which were interrupted in response to earth shorts on a line. The problem is due to certain voltages which may develop on the line due to the prior interruption which voltage may interact adversely with the line voltage during reclosing of the circuit breaker. With a three-phase interruption due to a single-phase short, that is to say when all three poles of the circuit breaker are open, the last-quenching two poles of the unaffected phase interrupt an open line. 
     For the case of uncompensated lines containing capacitive voltage transformers, a load which changes only very slowly is left on the line. Therefore, during the rapid reclosing, switching does not take place when feed voltage and load are of opposite polarity. Thus, the polarities of the feed voltage and of the load remaining on the disconnected line are detected in the known method and reclosing takes place when the polarities are identical. 
     In shunt-compensated lines the precharged line capacity and the inductances of compensating chokes form a tuned circuit. Consequently, the voltage on the line side oscillates with a natural frequency which is determined by the degree of compensation and which is lower than the frequency of the feed voltage. It is therefore possible to close the circuit breaker when supply and line voltage have opposite polarities. In such case, unacceptably high switching overvoltages occur at the open end of the line. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a generic method and an apparatus for carrying out the method which make it possible to reclose the breakers in the presence of alternating voltages on the supply side and on the line side without creating unacceptably high switching overvoltages. 
     The method according to the invention and the device provided therefore make it possible to limit closing overvoltages to values which dispense with the need to use switching resistors even in lines having a relatively low degree of compensation and/or long lines. At the circuit breaker, therefore, additional switching paths for the switching resistors can also be omitted as can the necessary coordination of insulation between the open power switching path and the switching path, arranged in parallel to this, for the switching resistors in the case of the action of lightning or switching voltage loading. Also avoided is the need for costly and complicated mechanisms for controlling the sequence of movements, which must be accurately staggered in time, of the contacts of the power and of the resistor switching paths. The use of relatively expensive and sensitive ceramic material for the switching resistors is rendered unnecessary. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     An illustrative embodiment of the invention is described below by reference to the drawings, in which: 
     FIG. 1 shows a basic circuit diagram of a three-phase line which is interrupted by a circuit breaker and which is provided with shunt compensation, comprising a reclosing device according to the invention which controls one pole of the circuit breaker. 
     FIG. 2 is a graphic representation of the line voltage acting in one phase conductor of the line according to FIG. 1 and a feed voltage, which can be switched onto the line via the circuit breaker. 
     FIG. 3 is a graphic representation of line and feed voltage similar to FIG. 2, from which the condition can be seen at which line and feed voltage have the same polarity. 
     FIG. 4 shows an embodiment of a measuring circuit used in the reclosing device according to the invention. 
     FIG. 5 shows an embodiment of an arithmetic unit, which follows the measuring circuit of FIG. 4, of the reclosing device according to the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1, L 1 , L 2  and L 3  are three phase conductors of a line L which is switched off at both ends and which is shunt-compensated, for example via chokes D 1 , D 2  and D 3 . These chokes can also be constructed as a three-phase unit. The left-hand end of the line L can be connected via a three-pole circuit breaker A to a three-phase voltage source S. Instrument transformers M S1 , M S2 , and M S3  and M L1 , M L2  and M L3 , which, for example, act capacitively, supply signals E S1 , E S2  and E S3 , which are proportional to the feed or source voltages delivered by the phases of the voltage source S, and signals E L1 , E L2  and E L3  which are proportional to the line voltages acting on the phase conductors L 1 , L 2  and L 3 . The signals E S1  and E L1 , delivered by the instrument transformers M S1  and M L1 , are fed to a reclosing device W the output of which is applied to an exciter element B of a pole 1 of the circuit breaker A. The exciter element B is activated by the delivery of a reclosing command, generated by the device W. It then recloses the pole 1 of the circuit breaker A at an appropriate time. The poles 2 and 3 of the circuit breaker A are controlled identical reclosing devices, not shown. 
     After circuit breaker A is opened, the voltages on the line L oscillate at a dominant frequency which is lower than the frequency of the feed voltage of source S. This is due to the fact that the capacitance, which is precharged by the feed source S, of the line L and the chokes D 1 , D 2  and D 3  form a tuned circuit which, upon opening of circuit breaker A, oscillates at a natural frequency determined by the chokes D 1 , D 2  and D 3 . To prevent circuit breaker A from reclosing when feed and line voltages have opposite polarities, method steps are specified, in accordance with the invention, which reliability permit the reclosing process to take place when feed and line voltages have identical polarities. The general concept of the present invention is explained with the aid of FIGS. 2 and 3. 
     To provide controlled reclosing, it is first necessary to measure the line and feed voltages continuously at each phase. FIG. 2 shows line voltage (shown by a solid line) and the higher-frequency feed voltage (dashed line) of one phase. T 0  is the reference point from which the time for reclosing is determined. The point T 0  is determined by a zero transition of the line voltage. T L  and T S  are the periods, previously determined through measuring zero transitions, of the line and feed voltages. ΔT represents the time which elapses from the first zero transition of the line voltage at time T 0  to the zero transition of the feed voltage from which the feed voltage has the same polarity as the line voltage in the half period following T 0 . 
     For all times T n  -T 0  =ΔT+m T S , the feed voltage has a half wave of identical polarity to the line voltage, to which applies the following reclosing condition: ##EQU1## where n, m=1, 2, 3, . . . . 
     The reason for this is as follows: 
     Since at time T 0 , the line voltage begins to oscillate with the same polarity as the feed voltage at time T 0  +ΔT, both will oscillate with the same polarity after nT L  or mT S . For this reason, they have the same polarity in the half period immediately before the zero transition at time T o  +nT L  or T 0  +mT S  +ΔT if nT L  ≧mT S  +ΔT. This can be seen from FIG. 3. If nT L  ≦ΔT+mT S  and the reclosing condition is met, the feed and the line voltage have identical polarity in the feed voltage half period following time T 0  +ΔT+mT S . The aforementioned condition then ensures that the higher-frequency half wave of the feed voltage is wholly contained in a lower-frequency half wave of the same polarity of the line voltage so that reclosing is guaranteed to occur when line and feed voltage are of identical polarity. 
     However, a circuit breaker has a natural mechanical period whose exact value is statistically varied. T mech  designates the mean of the natural mechanical period of one switch pole. For a mechanical circuit breaker, the aforementioned reclosing condition must be completed by meeting the condition: ##EQU2## which assumes that the natural period T el  of an electronic reclosing circuit used in this arrangement is negligible compared with the natural mechanical periods of the switch and the durations of the periods T L  and T S . 
     For each pair m, n, for which the two above conditions are met, the time at which the ON command is given to the circuit breaker, is then determined from ##EQU3## 
     Taking into consideration the natural period T el  of the reclosing device, this time is then determined from ##EQU4## 
     If an ON command is given at time t E , the mean of the closing time occurs at the maximum of the feed voltage. Since the line voltage then has the same polarity, the potential difference across the switch is very small during the closing process (see FIG. 3). 
     The reclosing control method in accordance with the invention can be carried out, for example, by means of a microcomputer with a programmed search loop. In this case, the index m is incremented by 1 with each run through the loop and the reclosing condition is interrogated with each run. If (mT S  +ΔT)≧nT L  without the reclosing condition being met, n is incremented by 1 and the program again runs through the m loop until the reclosing condition is met. 
     The condition, which takes into consideration the natural mechanical period of the circuit breaker, can already be met by the initial condition. Instead of beginning with n=1, n=n min  is used, n min  being the smallest integer for which ##EQU5## 
     However, the reclosing condition can also be realized by two counters. One counter continues to count by T S  and if 
     
         mT.sub.S &gt;nT.sub.L 
    
     the second counter continues to count by T L . The counter status can be continuously interrogated to find the reclosing condition. In order to accelerate the search process, T S  and T L  can be reduced by a constant common factor. This makes it possible to continue to count the periods more rapidly. 
     FIGS. 4 and 5 show in detailed form the circuit arrangement for carrying out the method according to the invention. In this arrangement, in FIG. 4 a measuring circuit is shown which determines the durations of the periods T L  and T S  of line voltage and feed voltage and the time ΔT and in FIG. 5 an arithmetic unit is shown which follows the measuring circuit and uses analogue techniques and which determines the reclosing time t E  from the quantities determined in the measuring circuit, taking into consideration the reclosing condition and the natural periods T mech  and T el . 
     In the measuring circuit shown in FIG. 4, F L  and F S  are designations for low-pass filters which in each case precede a signal converter W L  and W S . The output of the signal converter W L  is connected, on the one hand, via an inverter I L  and a diode, which follows this inverter, to one of two inputs of an AND gate G LN  the output of which acts on a controllable member SP LN  and to one of two inputs of an OR gate, which precedes a shift register SR L . On the other hand, the output of the signal converter W L  is connected via another diode to one of two inputs of another AND gate G LP , the output of which acts on a controllable memory SP LP  and to the second input of the OR gate preceding the shift register SR L . 
     The output of the signal converter W S  is connected, on the one hand, via an inverter I S  and a diode, which follows this inverter, to one of two inputs of an AND gate G VN , the output of which acts on a controllable memory SP SN  and to one of two inputs of an OR gate which precedes a shift register SR S . On the other hand, the output of the signal converter W S  is connected via another diode to one of two inputs of an AND gate G VP , the output of which acts on a controllable memory SP SP  and to the other input of the OR gate preceding the shift register SR S . Between the OR gate preceding the shift register SR S , an AND gate is located, one input of which is operatively connected to the output of an OR gate which follows the controllable memories SP SN  and SP SP  and the output of which is also connected to the input of a controllable integrator for the duration of the period T S . The outputs of the controllable memories SP LN  and SP LP  are respectively connected to one of two inputs of an OR gate, the output of which acts on the inputs of controllable integrators for the duration of the period T L , the natural electronic period T el  and the time ΔT. In addition, the output SP LN  is also connected to an inverting input of the AND gate G LP  and to one input of the AND gate G VN . The output of SP LP  is also connected to an inverting input of the AND gate G LN  and to one input of the AND gate G VP . The outputs of the shift registers SR L  and SR S  act on an AND gate G St , which generates and activates the start command St needed for the arithmetic unit, and the controllable integrators for T L  and T S . 
     The measuring section is activated only when a closing command ON, which turns on switching transistors, not designated, is issued by the reclosing device. This enables voltages E L1  and E S1  supplied from the instrument transformers M L1  and M S1  to be input to the measuring circuit. These voltages are processed in converters W L  and W S  to produce &#34;needle pulses&#34; i.e. a sharp and narrow pulse at each zero transitions of the respective voltages. Inverters I L  and I S  function to invert the negative needle pulses. The diodes function to allow only pulses belonging to the negative sign of the oscillation to pass through the channel for negative sign and only those pulses belonging to the positive sign of the oscillation to pass through the channel for positive sign. If a negative line voltage pulse passes through, both inputs of the AND gate G LN  are enabled and the output of G LN  is the input of the controllable memory SP LN  and, simultaneously, the control input for the &#34;follow&#34; state of operation. Thus the output of the memory SP LN  is also enabled and drives SP LN  to the &#34;hold&#34; state, that is to remain enabled. The inverting input of G LP  is thus at zero and, therefore, holds the output of the memory SP LP  at zero for the remainder of the measurement. Thus one input of G VP  also remains at zero so that G VP  is disabled. Now an integrator for measuring T S  can be enabled via the negative channel of the feed voltage. This can take place only after the first zero transition of the line voltage because prior to that one input of G VN  is at zero. The first zero transition of the line voltage starts the integrators for T L , ΔT and T el . 
     The shift register SR L  is clocked with the pulses of the line voltage. When the first value has been shifted by 3 places in the shift register, 3 voltage zero transitions have been counted and the output of the third position in the shift register is enabled. At that time the integrator for T L  is put in its &#34;hold&#34; state and at its output representing the value T L  is available. 
     As soon as a negative pulse is available also from the feed voltage, the output of G VN  is enabled and thus also the output of the controllable memory SP SN . This starts the integrator for T S  and simultaneously the integrator for ΔT is driven to the &#34;hold&#34; state and at its output ΔT becomes available. Similarly, the path to the shift register SR S  is opened. As soon as the contents of shift register SR S  have also been shifted by three places, the integrator for T S  is driven to the &#34;hold&#34; state and T S  becomes available at its output. 
     Once the measurement of the duration of the periods both of the line and of the feed oscillation is completed, both inputs of the AND gate G St  are enabled and the St command for starting the arithmetic unit (FIG. 5) is output. 
     The arithmetic unit has two pulse generators C L  and C S , the outputs of which are applied via switching transistors to the first of two inputs of AND gates G K  and G S , respectively. 
     The output of G K  acts on a first input of an OR gate T K  preceding an adding unit R L . The adding unit R L  contains a shift register SR LR  having a storage function and a summing unit S L  having a number of inputs which corresponds to the number of outputs of the shift register SR LR . In each case, the outputs of the shift register drive a switching transistor A L1 , A L2 , . . . A LN , which is connected between an input of the summing unit S L  and a branch point to which the signal of the duration of the period T L  is applied. In this arrangement, the outputs of the shift register SR LR  are associated with the inputs of the summing unit S L  in such a manner that the inputs of the summing unit S L  are successively activated when the shift register SR LR  is enabled. The output of the summing unit S L  is supplied to a first input of a comparing element V and, also to a first input of a comparator K 0 . A second input of the comparator K 0  continuously receives a signal T mech  +T S  /4, which takes into consideration the natural mechanical period of the circuit breaker A. The output of the comparator is connected to the second input of G K . 
     The output of G S  is supplied to a register R S . Register R S  contains a shift register SR SR  used as a storage and a summing unit S S  having a number of inputs which corresponds to the number of outputs of shift register SR SR . The outputs of the shift register SR SR  in each case drive one switching transistor A S1 , A S2 , . . . A SM  which is located between one input of the summing unit S S  and a branching point to which the signal T S  is applied. Corresponding to the outputs of the shift register SR LR , the outputs of the shift register SR SR  are associated with the inputs of the summing unit S S . The output of the summing unit S S  is supplied to a first input of a summing unit S D  which precedes the comparing element V. The second input of summing unit S D  receives the signal ΔT. The output of the summing unit acts, on the one hand, via a switching thyristor A S , on a first input of a summing unit S V  and, on the other hand, on a second input of the comparing element V. 
     Comparing element V has a third input to which a signal (T L  -T S )/2 is applied. The foregoing quotient is formed by a summing unit S A  and a following coefficient potentiometer. A first output of the comparing element V is output to a first input of an OR element T R  and to the second input of T K . A second output acts on a second input of T R  and on the second input of G S . A switch A SP  receives a third output and a fourth output of element V acts on switch A SN . The output of T R  is supplied to the switch A S  and to an integrator I A , the output of which integrator is connected to a first of the two inputs of a comparator K A . The output of comparator K A  is applied via an amplifier to the exciter element B of the circuit breaker. 
     The comparing element V is provided with two summing units S P  and S M . First inputs of said summing units are connected to the output of the adding unit R L , the signal coming from the adding unit R L  being made negative at the first input of the summing unit S P . Second inputs of the summing units S P  and S M  are connected to the output of the summing unit S D . In this arrangement, the signal accepted from the second input of the summing unit S M  is made negative. The outputs of the summing units S P  and S M  act on first inputs of two comparators K P  and K M , at the second inputs of which the signal (T L  -T S )/2 is input and the outputs of which act on the inputs of T R . 
     Immediately upon generation of starting signal St by the measuring circuit of FIG. 4, the switching transistors located between the pulse generators C L  and C S  and the AND gates G L  and G K , and other transistors preceding the summing units S A  and S D  are turned on in the arithmetic unit of FIG. 5. THe signal T L  is now present at the switching transistors A L1 , . . . , A LN  of the summing unit S L  and the signal T S  is presented at the switching transistors A S1 , . . . , A SM  of summing unit S S . As long as none of these transistors has been turned on, the output of the summing unit S L  is zero and the output of the comparator K O  remains enabled. With each pulse received from pulse generator G L , G K  will therefore remain enabled for as long as the signal at the output of S L  is less than T mech  +(T S  /4), that is the shift register SR LR  is clocked such that each clock pulse turns on the respective next one of the switching transistors A Li , where i=1, . . . N. Thus the signal T L  is applied to a new input of the summing unit S L . As soon as the output of the summing unit S L  is greater than T mech  +(T S  /4), the output of the comparator K 0  becomes to zero to disable G K . The shift register SR LR  can no longer be then clocked by the pulse generator. The signal at the output of the summing unit S L  is n min  T L  &gt;T mech  +(T S  /4). The inverting input of G S  is enabled, so that G S  is no longer disabled. At the output of the summing unit S M , the signal (n min  ·T L  -ΔT) is present which is greater than the signal (T L  -T S )/2. The output of the comparator K M  is therefore enabled and the output of the comparator K P  is disabled. The inverting OR gate T R  is disabled. 
     If K M  is enabled, G S  is able to pass every pulse from the pulse generator I S . The signal T S  is in each case applied to a new input of the summing unit S L  via the shift register SR SR  which is clocked by these pulses. At the output of S S  the signal mT S  now appears. If mT S  +ΔT&gt;nT L , the output of the summing unit S M  becomes negative and the output of K M  goes to zero and disables G S . If, in addition, (mT S  +ΔT)-nT L  &gt;(T L  -T S )/2, K P  is enabled. This causes the shift register SR LR  associated with the summing unit S L  to be clocked and nT L  to be incremented by T L . At the output of S L , (n+1)T L  appears. This causes the output of S M  to become positive again. K M  is enabled again and clocking of the shift register SR SR  for the summing unit S S  can be continued. if /-(mT S  +ΔT)+nT L  /≦(T L  -T S )/2, both comparators K P  and K M  are at zero and T R  is enabled. Further clocking of the shift registers SR LR , SR SR  is no longer Possible. The switching transistor A S  driven by T R  switches the value mT S  +ΔT at the output of the summing unit S D  to the summing unit S V . 
     T R  drives an integrator for T el  to the &#34;hold&#34;  state and starts the integrator I A . At the output of the summing unit S V  the closing time t&#39; E  =(mT S  +ΔT)-(T mech  +(T S  /4)-T el  or t&#39; E  =(mT S  +ΔT)-T mech  +(T S  /4)-T el . As soon as this time has elapsed (integrator I A  has reached this value), the comparator K A  is enabled and the exciter element B of the circuit breaker A is activated via an amplifier. All elements and memories are reset with the command T E  occurring when the closing command is outpt to the exciter element B and the device is ready for the next rapid reclosing operation.