Abstract:
This disclosed electric circuit substantially eliminates error output which is caused by unbalanced characteristics of a pair of transistors in a current mirror circuit. An input signal is amplified by a differential amplifier. A current mirror circuit is coupled between said differential amplifier and a power supply. Switching means is coupled to said current mirror circuit for cyclically switching input and output points of said mirror circuit.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to an electronic circuit and more particularly, to a phase comparison circuit and other electronic circuits including a current mirror circuit. 
     A phase comparison circuit, for example, can utilize an electronic circuit including a current mirror circuit. The circuit can function as a pilot signal detecting circuit in a PLL-MPX (phase locked type-multiplex) decoder IC which demodulates a stereophonic signal. Such a pilot signal detecting circuit is shown in FIG. 1. As shown, a stereophonic signal, which comprises main and sub-audio signals and a pilot signal, is supplied across the base electrodes of transistors Q 1 , Q 2 . Transistors Q 1 , Q 2  constitute a differential amplifier 11. After the stereophonic signal is amplified by amplifier 11, it is supplied from the collector electrodes of Q 1 , Q 2  to each common base electrodes of transistors Q 3 , Q 4  and transistors Q 5 , Q 6 . Transistors Q 3  to Q 6  constitute a double balanced differential amplifier 12. A switching signal from a switching signal source 13, which has the same frequency as the pilot signal (e.g., 19KHz) is supplied across the base electrodes of transistors Q 3 , Q 6  and transistors Q 4 , Q 5 . Amplifier 12 multiplies the stereophonic signal by the switching signal and produces an output signal from the collector electrodes of transistors Q 4 , Q 5  to an output terminal 15. An AC component in the output signal is supplied to power supply line L 11  through a condenser C 11 , connected between the terminal 15 and line L 11 . Consequently, a DC level corresponding only to the pilot signal is provided from terminal 15 to a stereo indicative lamp (not shown). 
     Voltage fluctuation in the power supply are reduced by a current mirror circuit 14, positioned between amplifier 12 and L 11 , which comprises a pair of transistors Q 7  and Q 8 . Although it is desired for transistors Q 7 , Q 8  to have identical characteristics so the current can be balanced, this is generally not possible due to the mass production of transistors. In general, therefore, an error current flows from mirror circuit 14 to output terminal 15. If the current gain of circuit 14 is 1+ε, the error current flowing into terminal 15 is (ε/2)I o  ; where ε is the error factor due to the unbalance of transistors Q 7 , Q 8 , and I o  is a current value produced by current source I 11 . Source I 11  is connected to the common emitter electrode of transistors Q 1 , Q 2 . In general, ε equals (approximately) ±0.1; as a result, 5% of the current value I o  is the error output current supplied to terminal 15. 
     This error output current, however, is not negligible. In the stereophonic signal, the modulation factor of the pilot signal is 10% and that of each audio signal is 90%. Accordingly, the level of each audio signal is nine times the level of the pilot signal. Furthermore, the current value I o  need be large to secure the dynamic range of the stereophonic signal. If I o  is 600 μA, the variation of the pilot signal becomes approximately ±10 μA provided that the upper and lower dynamic ranges of the stereophonic signal is three times the level of the audio signal. If I o  is 600 μA, then the error signal current becomes approximately ±30 μA. Consequently, the output including a large error component, in comparison with the pilot signal, will be supplied from terminal 15 to the stereo indicative lamp even when a stereophonic program is not be received. Accordingly, this high level error signal should not be detected. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide an electronic circuit which substantially eliminates the error output current produced by an unbalance of the mirror circuit. 
     Another object of the present invention is to provide an electronic circuit which can be formed in a integrated semiconductor circuit. 
     According to the present invention, an electronic circuit comprises: a signal input and output terminals; a differential amplifier having at least one input terminal and a pair of output terminals, the input terminal coupled to said signal input terminal; a first transistor having its collector electrode coupled to one of said output terminals of said differential amplifier; a second transistor having its collector electrode coupled to the other output terminal of said differential amplifier, its base electrode coupled to the base electrode of said first transistor; a first switching means having a movable contact, a first stationary contact, and a second stationary contact, its movable contact coupled to the base electrode of said first transistor, its first stationary contact coupled to the collector electrode of said first transistor, and its second stationary contact coupled to the collector electrode of said second transistor; second switching means having a movable contact, first stationary contact and a second stationary contact, its movable contact coupled to said signal output terminal, its first stationary contact coupled to the collector electrode of said first transistor, and its second stationary contact coupled to the collector electrode of said second transistor; and, a control means for cyclically controlling the positioning of said movable contacts of said first and second switching means between said first and second stationary contacts. 
     The objects and advantages of the present invention will become apparent to persons skilled in the art from a study of the following description and the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic circuit diagram of a conventional phase comparison circuit. 
     FIG. 2 is a schematic circuit diagram explaining the operation and construction of an electronic circuit according to the present invention, for example, shown in FIGS. 3-4. 
     FIG. 3 is a schematic circuit diagram of a phase comparison circuit according to the present invention. 
     FIG. 4 is a schematic circuit diagram of another embodiment of a phase comparison circuit according to the present invention. 
     FIG. 5 is a schematic circuit diagram explaining the operation and constitution of a modification of an electronic circuit according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention will be described in detail with reference to the accompanying drawings. Throughout the drawings, like reference numerals will be used to designate like or equivalent portions, for simplicity of explanation. 
     The fundamental constitution of an electronic circuit according to the present invention is shown in FIG. 2. An input signal is applied across the base electrodes of transistors Q 20  and Q 21  which form a differential amplifier 20. Their emitter electrodes are grounded through a common current source I 21 . 
     An amplified signal is supplied from the collector electrode of each transistor Q 20 , Q 21  to a current mirror circuit 21 comprising transistors Q 22  and Q 23 . The collector electrode of transistor Q 22  is coupled to the collector electrode of transistor Q 20 , while its emitter electrode is coupled to a power supply line 24. The collector electrode of transistor Q 23  is coupled to the collector electrode of transistor Q 21 , while its base electrode is coupled to the base electrode of transistor Q 23 , and its emitter electrode is coupled to line 24. A first switching means 22 has a movable contact S 1  coupled to base electrode of the transistor Q 22 , its stationary contact S 2  coupled to the collector electrode of transistor Q 22 , and its stationary contact S 3  coupled to the collector electrode of transistor Q 23 . A second switching means 23 has a movable contact S 4  coupled to a signal output terminal 26, its stationary contact S 5  coupled to the collector electrode of transistor Q 22 , and its stationary contact S 6  coupled to the collector electrode of transistor Q 23 . A capacitor C 21  is connected between terminal 26 and line 24 to average the output supplied by contact S 4 . The movement of contacts S 1 , S 4  are cyclically controlled by a control means 25 as follows: movable contact S 4  contacts stationary contact S 6  at the time movable contact S 1  contacts stationary contact S 2 . During the time, however, movable contact S 4  contacts stationary contact S 5 , movable contact S 1  contacts stationary contact S 3 . As a result, the error current flowing into output terminal 26 is reduced from (ε/2) I o , as in the prior art circuit, to ##EQU1## as will be developed in detail below. 
     The error output current supplied to output terminal 26 is as follows: It is assumed that the error factor of circuit 21, due to the unbalance of transistors Q 22  and Q 23 , is ε. Control means 25 is a count-down circuit for producing a symmetric square wave output having a one-half duty cycle. When contact S 1  contacts contact S 2 , and contact S 4  contacts contact S 6 , the current gain of the circuit 21 is 1+ε. When, alternately, contact S 1  contacts contact S 3 , and contact S 4  contacts with contact S 5 , the current gain of circuit 21 becomes ##EQU2## Consequently, the error output current, which is averaged by condenser C 21  and supplied to the terminal 26, is ##EQU3## where I o , is a value of current supplied from current source I 21 . 
     When ε is 0.1 the error output current is approximately 0.00227 I o , namely, 0.23% of the current I o . Now, if the current I o  is 600 μA, the error output current becomes approximately 1.38 μA. Accordingly, when compared with the error output current of the prior art circuit (i.e., 30 μA), the error current is substantially reduced. 
     This invention, for example, may be applied to a pilot signal detecting circuit in a PLL-MPX decoder IC which demodulates a stereophonic signal. Such a pilot signal detecting circuit is shown in FIG. 3. As shown, a stereophonic signal, comprising a main and sub-audio signals and a pilot signal (19 KHz), is applied across the base electrodes of transistors Q 20 , Q 21  which form a differential amplifier 20. After the stereophonic signal is amplified by the amplifier 20, it is supplied from the collector electrodes of transistors Q 20 , Q 21  to the respective collector electrode of transistors Q 22  and Q 23 . Transistors Q 22 , Q 23  constitute a current mirror circuit 21. The emitter electrode of transistor Q 22  is connected to a power supply line 24, while its base electrode is connected to the base electrode of transistor Q 23 . The emitter electrode of transistor Q 23  is connected to line 24. The collector electrodes of transistors Q 24 , Q 25  are connected to the base electrode of transistor Q 22 . The emitter electrode of transistor Q 24   is connected to the collector electrode of transistor Q 22 , while its base electrode is connected to the gate electrode of a field-effect transistor FET 20 . The source electrode of transistor FET 20  is connected to the collector electrode of transistor Q 23 , while its drain electrode is connected to an output terminal 26 and to line 24 through a condenser C 21 . The emitter electrode of transistor Q 25  is connected to the collector electrode of transistor Q 23 , while its base electrode is connected to the gate electrode of a field-effect transistor FET 21 . The source electrode of FET 21  is connected to the collector electrode of transistor Q 22 , while its drain electrode is connected to terminal 26. Transistors Q 24 , Q 25 , FET 20  and FET 21  function as switching means 22, 23 (FIG. 2). 
     One of a pair of output terminals of a 19KHz signal source 25 (e.g., symmetrical square wave) is connected to the base electrode of transistor Q 24 . The other terminal of source 25 is connected to the base electrode of transistor Q 25 . Source 25 functions as control means 25 (FIG. 2). As a result of the positive periodic output of source 25, transistor Q 24 , FET 20  conduct while transistors Q 25 , FET 21  are cut off. During the negative periodic output of source 25, transistors Q 24 , FET 20  are cut off while transistors Q 25 , FET 21  conduct. A DC signal, have very little error component and corresponding only to the pilot signal, is provided from terminal 26 to a stereo indicative lamp (not shown). Except for connection pin 27 for line 24, this circuit has only one outside connection pin 28 (i.e., for condenser C 21 ); consequently, it may be easily fabricated into a semiconductor integrated circuit. 
     Another embodiment of the pilot signal detecting circuit according to the present invention is shown in FIG. 4. For simplicity of explanation, portions similar to the circuit of FIG. 3 have been omitted. The base electrode of a transistor Q 30  is connected to one output terminal of 19KHz signal source 25. The base electrode of a transistor Q 31  is connected to the other terminal of source 25. The emitter electrodes of transistors Q 30 , Q 31  are grounded through a common current source I 31 . The emitter electrodes of transistors Q 32 , Q 33  are connected to the collector electrode of transistor Q 30 , while the base electrode of transistor Q 32  is connected to the collector electrode of transistor Q 22 . The collector electrode of transistor Q 32  is connected to power supply line 24. The collector electrode of transistor Q 33  is connected to the collector electrode of a transistor Q 36  and the base electrode of a transistor Q 37 . The base electrode of transistor Q 36  is connected to the base electrode of transistor Q 22 , while its emitter electrode is connected to line 24. The emitter electrode of transistor Q 37  is connected to the base electrode of transistor Q 22 , while its collector electrode is grounded. The emitter electrodes of transistors Q 34 , Q 35  are connected to the collector electrodes of transistor Q 31 . The base electrode of transistor Q 35  is connected to the collector electrode of transistor Q 23 , while its collector electrode is connected to line 24. The base electrode of transistor Q 34  is connected to the base electrode of transistor Q 33  and a negative electrode of a reference voltage source V 30 . A positive electrode of source V 30  is connected to line 24. The collector electrode of transistor Q 34  is connected to the collector electrode of transistor Q 33 . Transistors Q 30  to Q 37  function as switching means 22 (FIG. 2). Rather than utilizing a switching circuit for means 23 as shown in FIG. 2, FIG. 4 employs serially connected resistors R 30 , R 31 , connected between the collector electrodes of transistors Q 22 , Q 23 , to perform a similar function. In this case, the output signal is divided by resistors R 30  and R 31  to reduce the error signal. 
     As a result of the output of source 25, transistors Q 30 , Q 31  conduct alternatively. During the positive cycle of source 25 when transistor Q 30  conducts and transistor Q 31  is cut off, transistors Q 32 , Q 33  conduct and transistors Q 34 , Q 35  are cut off. During the negative cycle of source 25 when transistor Q 30  is cut off and transistor Q 31  conducts, transistors Q 32 , Q 33  are cut off and transistors Q 34 , Q 35  conduct. 
     A modification of the electronic circuit according to the present invention is shown in FIG. 5. For example, this circuit can be used as an operational amplifier. As shown, a small offset input voltage is applied across the base electrodes of transistors Q 20 , Q 21  which constitute a differential amplifier 20. The emitter electrodes of transistors R 20 , R 21  are grounded through a common current source I 21 . The collector electrode of transistor Q 20  is connected to a switching means 50. Switching means 50 has a movable contact S 51  connected to the collector electrode of a transistor Q 20 , its stationary contact S 52  connected to the collector electrode of a transistor Q 22 , and its stationary contact S 53  connected to the collector electrode of a transistor Q 23 . The collector electrode of transistor Q 21  is connected to a switching means 51 and an output terminal 26. Switching means 51 has a movable contact S 54  connected to the collector electrode of the transistor Q 21 , its stationary contact S 56  connected to the collector electrode of transistor Q 23  and its stationary contact S 55  connected to the collector electrode of transistor Q 22 . As shown in the previous embodiments, transistors Q 22 , Q 23  constitute a current mirror circuit 21. The emitter electrode of transistor Q 22  is connected to a power supply line 24, while its base electrode is connected to the base electrode of transistor Q 23 . The emitter electrode of transistor Q 23  is connected to line 24. A switching means 22 has its movable contact S 1  connected to the base electrode of transistor Q 22 , its stationary contact S 2  connected to the collector electrode of transistor Q 22 , and its stationary contact S 3  connected to the collector electrode of transistor Q 23 . The movements of contacts S 1 , S 51  and S 54  are cyclically controlled by a switching signal from a control means 25, which has a higher frequency than the input signal. During the time movable contact S 1  contacts stationary contact S 2 , movable contact S 51  contacts stationary contact S 52  and movable S 54  contacts stationary contact S 56 . During the time, however, movable contact S 1  contacts stationary contact S 3 , movable contact S 51  contacts stationary contact S 53 , and movable contact S 54  contacts stationary contact S 55 . 
     It should be readily apparent to a person skilled in the art that this invention can be employed in various types of electronic circuits including, for example, a phase comparator circuit in a FM quadrature detecting circuit, a AM synchronous detecting circuit and a phase-locked loop circuit.