Abstract:
A print-distortion compensating apparatus and method for an improved electrostatic type ink jet printing apparatus including a print-distortion compensating means, in which the compensating amounts for the print-distortion due to the influence of the neighboring ink droplets, such print-distortion being variable depending on the respective deflection steps, for instance, the print-distortion caused by the variation of aerodynamic resistance due to the preceding ink droplets, the Coulomb&#39;s force due to the preceding and subsequent charged ink droplets, and the charge induction due to the preceding charged ink droplets are memorized into and read out from the afore-mentioned print-distortion compensating means and those are finally added to or not added to the basic charging codes depending on presence or absence of the PRINT data on the ink droplets adjacent to an ink droplet to be charged.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to an improved apparatus and method for compensating for distortion in an ink jet printing apparatus. 
     In general, ink jet printing apparatus produce a series of ink droplets which are successively charged, deflected electrostatically, and conveyed with a trajectory towards a recording medium to perform printing by a series of dots thereon in response to print information. During the time when the respective ink droplets are conveyed, the respective ink droplets effect the flow of air behind them. When a subsequent ink droplet enters into the flow of air, the aerodynamic resistance acting on the subsequent ink droplet becomes smaller. In consequence, the preceding and subsdquent ink droplets may move closer to each other or may combine into one droplet while being conveyed toward the recording, causing distortion of the printed image or character. 
     Moreover, the respective ink droplets for printing are typically charged by an amount corresponding to the magnitude of the print or charging signal, and a Coulomb&#39;s force (electrostatic repulsive force) thus acts between the respective charged ink droplets. This electrostatic repulsive force may further disturb the distance between the respective ink droplets, causing a distortion in the information printed on the record medium. Further, under the influence of the preceding charged ink droplets, the amount of charge applied to the ink droplet just about to be charged may be decreased, thereby causing a similar distortion. For the purpose of solving the afore-mentioned defects, a method as shown in the U.S. Pat. No. 3,946,399 has already been proposed, for example. The invention disclosed in the U.S. Pat. No. 3,946,399 relates to a method of compensating for the charging amount, wherein the pattern to be printed is detected in advance and signals are developed to compensate for the expected distortion of the deflection of the ink droplets due to the mutual influence of the Coulomb&#39;s force working between the respective charged ink droplets and the aerodynamic resistance variation, and the charging amount is compensated for in response to these signals. 
     However, this method is not efficient in the case where many deflection steps, 32 steps for example, are possible for the ink droplets. The reason for that is as follows. As the number of deflection steps increase, the respective ink droplets are positioned more closely together so that the amount of print distortion may increase. In addition, due to the different flight time of each ink droplet which is dependent on the amount of deflection, the amount of distortion differs depending on the amount of deflection. In order to properly compensate for the print distortion, therefore, it is necessary to perform appropriate compensation for each deflection step. The afore-mentioned deflects often present rather difficult problems in the ink jet printing technology. 
     SUMMARY OF THE INVENTION 
     In view of the afore-mentioned, a primary object of the present invention is to provide an ink jet printing apparatus and method for improving the quality of printing by compensating for the distortion of the printed information by improving methods and apparatus for compensating such distortion. 
     A further object of the present invention is to provide an ink jet printing apparatus and method for improving the quality of printing by compensating for the distortion of the printed information which is caused by variation of aerodynamic resistance due to the preceding ink droplets, by the Coulomb&#39;s force due to the preceding and subsequent charged ink droplets, and by electrostatic induction due to the preceding charged ink droplets. 
     A still further object of the present invention is to provide an ink jet printing apparatus and method in which a precise print position for the ink droplets can be obtained by use of an apparatus having the compensation amounts for the print-distortion recorded into the memory such as a ROM, reading out the compensation amounts from the memory device, and finally adding or not adding those signals from the memory device to the basic charging codes. 
     Other objects, effects and features of the present invention will become more apparent from the following description of preferred embodiments thereof taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram illustrating the main parts of embodiments of the present invention. 
     FIG. 2 is a diagram showing the contents in the memory of a first embodiment of the present invention. 
     FIG. 3 is a detailed circuit diagram of the charge compensating circuit shown in FIG. 1 of the first embodiment. 
     FIG. 4 is a diagram showing the contents in the memory of a second embodiment of the present invention. 
     FIG. 5 is a detailed circuit diagram of the charge compensating circuit shown in FIG. 1 of the second embodiment. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     While the ink jet printing apparatus of the present invention is susceptible of numerous physical embodiments, depending upon the environment and requirements of use, a substantial number of the herein shown and described embodiments have been made, tested and used, and all have performed in an eminently satisfactory manner. 
     FIG. 1 schematically shows the overall construction of an exemplary ink jet printing apparatus to which the present invention is applicable. In the diagram, an ink ejection head 1 is provided for forming a stream of ink droplets at a frequency determined by a piezoelectric element 2. A charging electrode 3 is provided for applying a voltage to the ink droplets to charge them, and a charging-phase checking electrode 4 is provided for sensing the charge on the ink droplets for checking the phase of the charging signals. A pair of deflection electrodes 5 are connected to a high voltage direct current source 6. A sheet 7 of recording paper or a recording medium is moved transversely across the path of the ink droplets by a recording medium conveyor 10 for enabling the charged ink droplets to impinge on the recording medium to form an image or a character thereon. A gutter 8 collects unused ink and a pump 9 serves to withdraw ink from the gutter 8 and supply it back to the ink ejection head 1. A clock pulse generator 11 and a frequency divider 12 are provided along with a phase shifter 13, amplifiers 14 and 15, a check pulse generator 16, a charge compensating circuit 17, a digital-to-analog (D/A) converter 18, and an amplifier 19 for applying the proper signals to the ink droplets. 
     The ink ejection head 1 is excited by the piezoelectric element 2 with a frequency of 132 kHz. While, in the present description, two uncharged guard ink droplets are provided for each charged ink droplet in order to decrease the extent of distortion, these guard ink droplets are not always necessary. Consequently, the frequency of the charging signal applied to the ink droplets is 44 kHz in order to apply a charge to every third ink droplet. The charging voltage may be adjustable in the range of 80 V to 240 V depending on the input signal representing character information and information to compensate for expected distortion. In FIG. 1, the clock pulse generated by the clock pulse generator 11 has a frequency of 1,056 kHz and that frequency is divided into one eighth, one third and one twenty-fourth, respectively, by the frequency divider 12. The signal having the frequency f 1  divided into one eighth is used as an exciting pulse, whose frequency is equal to the breaking-into-droplets frequency, 132 kHz. The signal having the frequency f 2  divided into one twenty-fourth is used as a charging pulse of 44 kHz, and the signal having the frequency f 3  divided into one third as a compensation clock pulse of 352 kHz. 
     The charge compensating circuit 17 includes a memory storing information corresponding to the compensating amounts which can be successively read out later, and controls addition or non-addition of the compensating amounts to the basic charging codes depending on the presence or absence of the compensating data. The data added in such a manner are converted into analogue signals with the digital-to-analog converter 18. These converted signals are applied to the charging electrode 3 through the amplifier 19. For this purpose, the compensating amounts are binarily stored in a memory device such as a ROM (Read Only Memory) or RAM (Random Access Memory) provided in the charge compensating circuit 17. Together with the compensating amounts, the basic charging codes are also stored in the same memory device. The basic charging codes have such values as to cause the respective ink droplets to impinge precisely on the desired position on the recording medium, without being subjected to the influence of any other preceding and subsequent ink droplets. 
     FIRST EMBODIMENT, FIGS. 2 AND 3 
     FIG. 2 is a diagram of the contents stored in the memory of a first embodiment and shows the afore-mentioned situation. In the diagram, information stored at any memory address has eleven bits which are divided into three bits, four bits and another four bits to represent the forms of octal, hexadecimal and another hexadecimal, respectively. Accordingly, the memory device is of a construction having eleven parallel bits. In any case, it may be of a construction having address locations of more than eleven, i.e.×eight dots×thirty-two steps. In FIGS. 2 and 4, the term &#34;stage&#34; is used instead of &#34;step&#34;. By way of description, the code 7FF at the thirty-first step of F 2  shown in the table of FIG. 2 is the code for adding a complement added to the basic charging code to perform a subtraction of &#34;1&#34; from the basic charging code. Also, since the aerodynamic resistance varies depending on the amount of deflection, the charging code becomes non-linear. The compensating amount is determined on the basis of the single ink droplet. The basic charging code and the compensating amount can be calculated from the simulation results using an electronic computer, and they may be corrected later according to the result of experiments. 
     The relationship between the codes shown in the table of FIG. 2 and the voltages applied to the charging electrode 3 is described as follows; For example, the code value &#34;618&#34; shown at the thirty-second step of V cs  is equivalent to 240 V. Namely, the code value &#34;618&#34; represented in the forms of octal, hexadecimal and another hexadecimal is equivalent to the value in the decimal form, shown below; 
     
         __________________________________________________________________________THE CODE VALUE &#34;618&#34; =           1 1 0 / 0 0 0 1 / 1 0 0 0           ↑             ↑               ↑                   ↑                     ↑                       ↑                         ↑                             ↑                               ↑                                 ↑                                   ↑           2.sup.10             2.sup.9               2.sup.8                   2.sup.7                     2.sup.6                       2.sup.5                         2.sup.4                             2.sup.3                               2.sup.2                                 2.sup.1                                   2.sup.0=               2.sup.10 + 2.sup.9 + 2.sup.4 + 2.sup.3=               1024 + 512 + 16 + 8=               1560__________________________________________________________________________ 
    
     And the voltage V cs32  applied to the charging electrode is equal to 240 V. 
     
         V.sub.cs32 =(1560/1560)×(240 V)=240 V 
    
     The code value &#34;209&#34; shown at the first step of V cs  is equivalent to 80 V. Namely, the code value &#34;209&#34; is equivalent to the value in the decimal form, shown below; 
     
         ______________________________________THE CODE VALUE &#34;209&#34; =             0 1 0 / 0 0 0 0 / 1 0 0 1=                 2.sup.9 + 2.sup.3 + 2.sup.0=                 512 + 8 + 1=                 521______________________________________ 
    
     And the voltage V cs1  applied to the charging electrode is nearly equal to 80 V. 
     
         V.sub.cs1 =(521/1560)×(240 V)≈80 V 
    
     Generally, the code value &#34;CV csi  &#34; shown at the i-th step of V cs  is equivalent to V csi  V. ##EQU1## With respect to F 1  to F 3  and P 1  to P 4 , the equivalent voltage values can also be obtained in a similar manner. 
     The code value &#34;7FF&#34; shown at the thirty-first step of F 2  is represented as follows; ##EQU2## Namely, adding the code value &#34;7FF&#34; to the basic charging code means subtracting &#34;1&#34; from the basic charging code. The code value &#34;7FF&#34; is added to the basic charging code value &#34;5F9&#34;, and in consequence the added value becomes 
     
         101/1111/1000 
    
     as shown below; ##EQU3## The symbols A to F in the table of FIG. 2 represent 10 to 15, respectively, in the hexodecimal form. In the foregoing, the method of converting the code value shown in the table of FIG. 2 into the value of voltage applied to the charging electrode has been described. The method of converting the code value shown in the table of FIG. 4 into the voltage value is quite the same. In such a manner, the code value is converted into the voltage value by use of the digital-to-analog converter. 
     FIG. 3 is a detailed circuit diagram of the charge-compensating circuit 17 of the first embodiment. In the diagram, 21 indicates an address counter; 22, a memory (ROM, for example); 23, a gate circuit; 24, an adder, 25, a shift register; 26, a multiplexer, 28, a latch circuit; 29, a D type flip-flop circuit; and 30, a gate circuit. The performance of the respective circuits is described below; 
     (1) When the PRINT ORDER signal reaches a high level, the address counter 21 becomes enabled to operate and is counted up by the compensation clock signal f 3 . As the frequency of the compensation clock signal f 3  is eight times as great as that of the charging pulse signal f 2 , the eight groups of data shown in the table of FIG. 2 are serially read out during one cycle of the charging pulse. 
     (2) The PRINT datum is delayed with the shift register 25. The output O 3  represents the datum to be charged. Stated more precisely, O 0 , O 1  and O 2  represent the subsequent charged ink droplets and correspond to F 3 , F 2  and F 1  shown in FIG. 2, respectively. O 4  to O 7  represent the preceding charged ink droplets and correspond to P 1  to P 4  shown in FIG. 2, respectively. 
     (3) The lower-column three bits in the address counter 21 are applied to the multiplexer 26, which is controlled so as to output the content of O 0  when the content of the lower-column three bits is &#34;0&#34; and output the content of O 1  when the content of the lower-column three bits is &#34;1&#34;. In other words, the total of eight data, that is 4 preceding data, the PRINT datum, and 3 subsequent data, are selected in accordance with the content of the lower-column three bits in the address counter 21. 
     (4) The output of the multiplexer 26 is applied to the gate circuit 23. The output of the memory 22 is controlled by the gate circuit 23. Namely, if the output of the multiplexer 26 indicates a compensation to be needed, the output of the memory 22 is applied to the adder 24 through the gate circuit 23 and added to the basic PRINT signal as a compensating value. Then, the output of the adder 24 is delayed with the latch circuit 28 and added to the next compensating value. However, it is constructed such that the input signal of the latch circuit 28 is inhibited and the content of the latch circuit 28 is set at &#34;0&#34;, when the content of the lower-column three bits in the address counter 21 becomes &#34;7&#34;. 
     (5) The output of the adder 24 is also applied to the D type flip-flop circuit 29 and sampled at the leading edge of the charging pulse signal. In consequence, the compensated value is memorized in the D type flip-flop circuit 29 and printing is controlled so as to eliminate or reduce distortion in accordance with the presence or absence of the PRINT data. Namely, when the print data exist, those data are transmitted as the charging code to the digital-to-analog converter 18 through the gate circuit 30, whereby printing may be compensated. 
     As is apparent from the afore-mentioned description, an adequate compensation corresponding to the presence or absence of the PRINT data and the number of the deflection steps may be accomplished according to the present invention. While the present invention has been described with respect to the first embodiment in which the basic charging code amount V cs  corresponding to the number of deflection steps is memorized in the same memory, it is also possible to use other compensation-signal-generating means. Further, although the description has been made with respect to a successive printing, it is also possible to compensate for the printing positions in the case of a non-successive printing by memorizing the amount V cs  in the form of non-successive pattern in the memory (ROM). In case of a non-successive printing, the flying row is assumed, and the compensating amount for the designated ink droplets on the preceding row is determined. 
     SECOND EMBODIMENT, FIGS. 4 AND 5 
     Up to here, the apparatus and method of the present invention have been described on the assumption that the basic charging signals have the values compensated for their non-linear error distortion. In the case of deflection of a single ink droplet, the relationship between the charging code and the deflection amount is not linear in practice, because the aerodynamic resistance differs depending on the deflection amount. In addition, the charging code is also not linear when the deflection amounts are linearly arranged, and so the distortion amount from the linear value is memorized in the afore-mentioned memory as a compensating amount. 
     As a second embodiment, FIG. 4 represents the contents of the memory; the charging code linearly generated, the charging code compensated for the non-linear error (non-linear charging code in the table of FIG. 4), the non-linearity compensating amount (c), and the PRINT data compensating amount. This means that the compensating amount corresponding to the PRINT data and the non-linearity compensating amount for a single ink droplet are stored in the memory. These compensating amounts are represented in the form of hexadecimal code. The charging codes are composed of eleven bits, which are divided into the groups of three bits, four bits and another four bits to be represented in the forms of octal, hexadecimal and another hexadecimal, respectively. The linear charging code is set at a smaller value than the non-linear charging code to enable compensation by the performance of addition only. The respective compensating amounts can be calculated from the results of simulation using an electronic computer, and they may be corrected later according to the result of experiments. 
     FIG. 5 is a detailed circuit diagram of the charge-compensating circuit 17 of the second embodiment. In the diagram, 21 to 26 and 28 to 30 indicate the same circuit blocks as those shown in FIG. 3, and 27 indicates a charging code generating circuit. The performance of the respective circuits is described below; 
     (1) when the PRINT ORDER signal reaches a high level, the address counter 21 becomes enabled to operate and then the counter 21 is counted up by the compensation clock signal f 3 . As the compensation clock signal f 3  has a frequency eight times as great as that of the charging pulse signal f 2 , the eight groups of data shown in the table of FIG. 4 are laterally read out during one cycle of the charging pulse. 
     (2) The PRINT datum is delayed with the shift register 25. The output O 3  represents the datum to be charged. Namely, stated more precisely, O 0 , O 1  and O 2  represent the subsequent charged ink droplets and correspond to F 3 , F 2  and F 1  shown in FIG. 4, respectively. O 4  to O 7  represent the preceding charged ink droplets and correspond to P 1  to P 4  shown in FIG. 4, respectively. 
     (3) The lower-column three bits in the address counter 21 are applied to the multiplexer 26. When the content of the lower-column three bits of the address counter 21 is &#34;0&#34;, the output of the multiplexer 26 is set at &#34;high&#34; as the input I 0  of the multiplexer 26 becomes &#34;high&#34;, whereby the compensating amount (c) for the non-linear error in the memory 22 is applied to the adder 24 through the gate circuit 23. At the same time, &#34;200&#34; is loaded into the charging code generating circuit 27, which is counted up by the charging pulse f 2 , whose content is applied to the adder 24 when the lower-column three bits are &#34;0&#34;. In consequence, the amount compensated for the non-linear error is obtained as an output of the adder 24 and is memorized in the latch circuit 28. When the content of the lower-column three bits becomes &#34;1&#34;, the content of O 0  is generated as the output of the multiplexer 26 and the content of F 3  is controlled by the gate circuit 23 depending on the state of &#34;low&#34; or &#34;high&#34; in the multiplexer 26, with the result that whether or not the content of F 3  is applied to the adder 24 is controlled according to the PRINT data. Namely, O 1  to O 3  or O 4  to O 7  are selected as an output of the multiplexer 26 in accordance with the contents 2 to 7 of the lower column three bits and the application of the respective compensating amount to the adder 24 is controlled by the PRINT data. The output of the adder 24 is delayed by the latch circuit 28 and added to the next compensating amount. However, the input to be applied to the latch circuit 28 is inhibited and its content is set at &#34;0&#34; when the content of the lower-column three bits becomes &#34;7&#34;. 
     (4) The output of the adder 24 is also applied to the D type flip-flop circuit 29 and sampled at the leading edge of the charging pulse. Consequently, the compensated amount is memorized in the D type flip-flop circuit 29 and printing is controlled by the presence or absence of the PRINT datum. Namely, when the data represents &#34;presence&#34;, the compensated amount is transmitted as a charging code to the digital-to-analog (D/A) converter 18 through the gate circuit 30, whereby the print distortion may be compensated. 
     As is apparent from the afore-mentioned description, an adequate compensation corresponding to the presence or absence of the PRINT data and the number of the deflection steps is possible according to the present invention. In the case of the second embodiment shown in FIG. 5, the compensating amount to be memorized may be 8×8×32 bits, as it is so arranged that the basic charging code is generated from the charging code generating circuit 27. Although the second embodiment in which printing is successively performed has heretofore been described, it will be readily understood that, in the case of non-successive printing, too, the print distortion may adequately be compensated through re-arrangement of the compensating pattern and the basic charging code. 
     Moreover, by separating the memory into several blocks, the print distortion due to pressure, temperature, viscosity of ink, and so on, may be compensated. While, in the preferred embodiments compensation is performed with respect to the influence by 4 preceding ink droplets and 3 subsequent ink droplets, the number of ink droplets that may be compensated is not limited to that described here, since the number may vary depending on the distance from the ink ejection head to the recording medium. 
     While the present invention has been particularly disclosed and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention.