Abstract:
A motherboard includes a first memory, a power supply, a jumper, a second memory slot and a conversion board. A first idle pin of the second memory slot is coupled to the power supply through the jumper. The motherboard supplies power to the first memory and ensures communication with the first memory by virtue of the conversion board. A conversion board is also provided.

Description:
FIELD 
       [0001]    The subject matter herein generally relates to a conversion board and a motherboard having the conversion board. 
       BACKGROUND 
       [0002]    A double data rate synchronous dynamic random access memory III (DDR3) cannot be driven by a double data rate synchronous dynamic random access memory IIII (DDR4) slot. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    Implementations of the present technology will now be described, by way of example only, with reference to the attached figures. 
           [0004]      FIG. 1  is a block diagram of an embodiment of a motherboard. 
           [0005]      FIG. 2  is a circuit diagram of an embodiment of a conversion board of the motherboard. 
       
    
    
     DETAILED DESCRIPTION 
       [0006]    It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts have been exaggerated to better illustrate details and features of the present disclosure. 
         [0007]    Several definitions that apply throughout this disclosure will now be presented. 
         [0008]    The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like. 
         [0009]    The present disclosure is described in relation to a motherboard  100 . 
         [0010]      FIG. 1  illustrates an embodiment of the motherboard  100 . The motherboard  100  is capable of coupling with a DDR4 (not shown) or a DDR3  200 , and can comprise a power supply  10 , a jumper  30 , a DDR4 slot  50 , and a conversion board  70 . A DDR3  200  is capable of coupling to the conversion board  70 . In at least one embodiment, the power supply  10  can supply 3 volts. 
         [0011]    The DDR4 can be inserted in the DDR4 slot  50 . A plurality of terminals disposed in the DDR4 slot  50  corresponds to a plurality of pins of the DDR4. A first idle terminal of the DDR4 slot  50  is coupled to the power supply  10  through the jumper  30 . 
         [0012]      FIG. 2  illustrates an embodiment of the conversion board  70 . In at least one embodiment, the conversion board  70  is a printed circuit board (PCB). The conversion board  70  can comprise a first interface  71 , a second interface  73 , and a conversion circuit  75 . A plurality of pins, corresponding to the terminals of the DDR4 slot  50  is disposed in the first interface  71 . The pins of the first interface  71  follow pins specification of the DDR4. There is a one-to-one correspondence between the pins of the first interface  71  and the terminals of the DDR4 slot  50  when the first interface  71  is inserted in the DDR4 slot  50 . A first idle pin RFUO of the first interface  71  is coupled to the first idle terminal of the DDR4 slot  50 . In at least one embodiment, the power supply  10  outputs 3 volts. 
         [0013]    A plurality of terminals, corresponding to a plurality of pins of the DDR3, is disposed in the second interface  73 . The terminals of the second interface  73  follow terminals specification of a DDR3 slot for inserting the DDR3  200 . A first power terminal VDDSPD of the second interface  73  is coupled to the first idle pin RFUO of the first interface  71 . The 3 volts from the first power terminal VDDSPD of the second interface  73  is converted to 1.5 volts by the conversion circuit  75 , and then the 1.5 volts is output to second power terminals VTT, VDDQ, VDD of the second interface  73 . The 3 volts from the first power terminal VDDSPD of the second interface  73  is also converted to 0.75 volts by the conversion circuit  75 , and then the 0.75 volts is outputted to third power terminals VREFCA, VREFDQ of the second interface  73 . A fourteenth signal terminal A 14  of the second interface  73  is coupled to a seventeenth signal pin All of the first interface  71 . A fifteenth signal terminal A 15  of the second interface  73  is coupled to a second idle pin RFUl of the first interface  71 . There is a one-to-one correspondence between the other pins of the first interface  71  and other terminals of the second interface  73 . 
         [0014]    The conversion circuit  75  can comprise resistors R 1 -R 4  and a capacitor C. The first power terminal VDDSPD of the second interface  73  is coupled to the second power terminals VTT, VDDQ, VDD of the second interface  73  through the resistor R 1 . The second power terminals VTT, VDDQ, VDD of the second interface  73  are coupled to ground through the resistor R 2 . The second power terminals VTT, VDDQ, VDD of the second interface  73  are also coupled to ground through the capacitor C. The third power terminals VREFCA, VREFDQ of the second interface  73  are coupled to the second power terminals VTT, VDDQ, VDD of the second interface  73  through the resistor R 3 . The third power terminals VREFCA, VREFDQ of the second interface  73  are also coupled to ground through the resistor R 4 . 
         [0015]    When using the DDR3  200 , the jumper  30  is coupled to the motherboard  100  and the DDR3  200  is coupled to the second interface  73 , the power supply  10  is coupled to the DDR4 slot  50 . An input voltage of 3 volts is received by the first power terminal VDDSPD from the power supply  10 . The conversion circuit  75  converts the input voltage to 1.5 volts and 0.75 vols. The 1.5 volts is output to second power terminals VTT, VDDQ, VDD. The 0.75 volts is output to third power terminals VREFCA, VREFDQ of the second interface  73 . The DDR3  200  can be driven. 
         [0016]    When to use the DDR4, the jumper  30  is detached from the motherboard  100 , and the DDR4 is inserted in the DDR4 slot  50 . 
         [0017]    In at least one embodiment, the DDR4 slot  50  is closest to a memory controller on the motherboard  100  for protection the communication quality. 
         [0018]    The embodiments shown and described above are only examples. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, especially in matters of shape, size and arrangement of the parts within the principles of the present disclosure up to, and including the full extent established by the broad general meaning of the terms used in the claims. It will therefore be appreciated that the embodiments described above may be modified within the scope of the claims.