Abstract:
A method and an apparatus for balancing the power loss in at least two electrically parallel-connected cascode circuits, which each have a low-blocking semiconductor switch composed of silicon and a high-blocking-capability semiconductor switch composed of silicon carbide is disclosed. According to the present invention, an output voltage of each low-blocking-capability semiconductor switch is detected, with correction values being established as a function of them, and being superimposed on corresponding control signals for the low-blocking-capability semiconductor switches. An unbalanced current distributor can thus be actively balanced.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a method and an apparatus for balancing the power loss in at least two electrically parallel-connected cascode circuits, each of which has a low-blocking-capability semiconductor switch composed of silicon and a high-blocking-capability semiconductor switch composed of silicon carbide.  
         BACKGROUND OF THE INVENTION  
         [0002]    A a cascode circuit which has a low-blocking-capability semiconductor switch composed of silicon and a high-blocking-capability semiconductor switch composed of silicon carbide is known from German Patent 196 10 135. This cascode circuit has a normally off n-channel MOSFET, e.g. a low-voltage power MOSFET, and a high-blocking-capability junction field effect transistor (JFET). This cascode circuit is also referred to as a hybrid power MOSFET and is designed for a high blocking voltage of more than 600 V, while nevertheless having low loss when switched on.  
           [0003]    The two FETs in this known cascode circuit are electrically connected in series in such a way that the source connection of the junction FET is electrically conductively connected to the drain connection of the MOSFET. Further, the gate connection of the junction FET is electrically conductively connected to the source connection of the MOSFET. The normally off n-channel MOSFET is composed of silicon. The normally off n-channel JFET is composed of silicon carbide.  
           [0004]    The above-described cascode circuit is controlled by means of the gate voltage of the normally off MOSFET. When this MOSFET is switched on, its drain voltage is approximately zero. This drain voltage is fed back so that the gate voltage of the normally on JFET is also zero. In a normally on junction FET, the maximum drain current flows when the gate voltage is equal to zero. When the normally off MOSFET is switched off, its drain voltage rises, and the gate voltage of the normally on junction FET falls due to the feedback. As soon as the gate voltage of the junction FET reaches or falls below a threshold voltage, the drain current of this junction FET is zero. This cascode circuit is thus switched off.  
           [0005]    In principle, these cascode circuits can be connected in parallel. When a number of semiconductor switches are connected in parallel, a problem occurs in that the load current to be carried is not shared uniformly between the parallel-connected semiconductor switches. This non-uniform current distribution results from production aspects of the semiconductor switch.  
           [0006]    The problem of non-uniform current distribution in parallel-connected semiconductor switches will be explained using the example of a parallel circuit formed by two semiconductor switches, T 1  and T 2 , which are two MOSFETs FIG. as shown in FIG. 1. FIG. 2 shows the associated output characteristics of these two MOSFETs T 1  and T 2  in the form of a graph. These output characteristics for the parallel-connected MOSFETs T 1  and T 2  are produced for two gate voltages which are the same. It can be seen from FIG. 2 that the output characteristics of the two MOSFETs T 1  and T 2  differ from one another when the gate voltage is the same. This discrepancy results from production. In the illustrated case, a load current of 1000 A/cm 2  is not split uniformly between the two parallel-connected MOSFETs T 1  and T 2 . The MOSFET T 1  carries a greater proportion of the current than the MOSFET T 2 . The MOSFET T 1  carries a portion of the current I T1  of 600 A/cm 2 , and the MOSFET T 2  carries a portion of the current I T2  of 400 A/cm 2 . Since the forward voltage across the two semiconductor switches T 1  and T 2  is the same since they are connected in parallel, the greater proportion of the current I T1  carried in the semiconductor switch T 1  results in more power being lost at T 1 . Such an increased power loss can in some circumstances destroy, or at least damage, the semiconductor switch T 1 .  
           [0007]    This problem can be solved by the overall current load level in a number of parallel-connected semiconductor switches being limited such that none of the parallel connector semiconductor switches is overloaded at a maximum unbalanced level guaranteed by the manufacturer. However, this solution has the disadvantage that the parallel circuit formed by a number of semiconductor switches has to be severely derated, and it is thus not very economical.  
           [0008]    The semiconductor switches can be designed by the manufacturer to have a positive temperature coefficient. The publication “A New Generation of 600 V IGBT-Modules”, printed in the Conference Proceedings “POWER CONVERSION”, May 1998, pages 23 to 31, describes an IGBT module which has a positive temperature coefficient. This publication also states that such semiconductor switches can be used in a particularly advantageous manner in parallel circuits. A semiconductor switch designed in such a way does not allow the power loss in parallel-connected semiconductor switches to be balanced completely. Furthermore, this compensation mechanism involves a long time constant, by virtue of the positive temperature coefficients. Particularly in the case of bipolar semiconductor switches, this positive temperature coefficient requirement restricts the rest of the semiconductor switch optimization process. Using this method, the problem is only ameliorated, but is not completely solved.  
           [0009]    This described problem occurs not only with parallel-connected MOSFETs T 1  and T 2  but, with any parallel-connected semiconductor switches. In a semiconductor circuit which is composed of two semiconductor switches, e.g. the cascode circuit described above, this problem cannot be solved by conventional means, since each semiconductor switch in a cascode circuit has been optimized for use in that cascode circuit.  
         SUMMARY OF THE INVENTION  
         [0010]    The present invention provides a method and an apparatus for balancing the power loss in a number of parallel-connected cascode circuits.  
           [0011]    In accordance with the present invention, an output voltage of each low-blocking-capability semiconductor switch in the parallel-connected cascode circuits is detected, and then a signal is produced for the current flowing in the parallel-connected cascode circuits. Thus, the current distribution when a number of cascode circuits are connected in parallel is determined. This determined current distribution is balanced actively by making use of the fact that the output voltage of the low-blocking-capability power semiconductor switch varies with the control variable as a parameter. To this end, correction values are established as a function of the determined output voltages of the low-blocking-capability semiconductor switches in the parallel-connected cascode circuits, and are superimposed on corresponding control signals for the low-blocking-capability semiconductor switches. These correction values are used to vary the control signals for the low-blocking-capability semiconductor switches in a manner such that the output voltages of the parallel-connected cascode circuits are equal. The current distribution in this parallel circuit formed by a number of parallel-connected cascode circuits is thus balanced.  
           [0012]    The present invention also provides an apparatus for balancing the power loss in a number of parallel-connected cascode circuits. For each cascode circuit the apparatus has a voltage measurement device, a device for establishing a correction value, and an adder. Each voltage measurement device is linked on the input side to a main connection and a reference connection of a low-blocking-capability semiconductor switch in a cascode circuit, and is linked on the output side to an input of the associated device for establishing a correction value. On the output side, each device is linked to a first input of an adder. A control signal for a corresponding low-blocking-capability semiconductor switch is applied to the second input of the adder. Since the output voltage of the low-blocking-capability semiconductor switch in each cascode circuit is determined, the voltage measurement device is not subject to any particular voltage requirements, even though a blocking voltage with a value of more than 600 V is applied to the cascode circuit. An apparatus of the present invention, using simple means, uses the current distribution in a number of parallel-connected cascode circuits to actively balance the cascode circuits.  
           [0013]    In an advantageous method of the present invention, the determined correction values are not used to vary the control signals of the low-blocking-capability semiconductor switches in the parallel-connected cascode circuits, but are each supplied to a controllable decoupling device. Each of these controllable decoupling devices links a control connection of a high-blocking-capability semiconductor switch to a reference connection of its associated low-blocking-capability semiconductor switch. The determined correction values are used to modify the coupling levels between the high-blocking-capability and low-blocking-capability semiconductor switches in the parallel-connected cascode circuits in such a manner that the determined output voltages from the low-blocking-capability semiconductor switches are equalized, thus actively balancing the current distribution. In comparison to the previously known method, there is no voltage increase across the high-blocking-capability semiconductor switch, and there is no longer any increase in the voltage across the low-blocking-capability semiconductor switch in a cascode circuit. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    For a complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numbers indicate like features, components and method steps, and wherein:  
         [0015]    [0015]FIG. 1 shows a parallel circuit formed by two MOSFETs;  
         [0016]    [0016]FIG. 2 shows the output characteristics of the MOSFETs shown in FIG. 1;  
         [0017]    [0017]FIG. 3 shows the variation in the output characteristics of a MOSFET as a function of the control voltage;  
         [0018]    [0018]FIG. 4 illustrates an apparatus for balancing the power loss in a number of electrically parallel-connected cascode circuits, in accordance with an exemplary embodiment of the present invention;  
         [0019]    [0019]FIGS. 5 and 6 each show one exemplary embodiment of the apparatus shown in FIG. 4;  
         [0020]    [0020]FIG. 7 illustrates another embodiment of the apparatus according to the present invention; and  
         [0021]    [0021]FIGS. 8 and 9 each show one exemplary embodiment of the apparatus shown in FIG. 7. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0022]    Now referring to the drawings, FIG. 4 shows a first exemplary embodiment of an apparatus  2  according to the invention for balancing the power loss in a number of cascode circuits  4   1 ,  4   2 , . . . ,  4   n . Each cascode circuit  4   1 ,  4   2 , . . . ,  4   n  has a low-blocking-capability semiconductor switch  6   1 ,  6   2 , . . . ,  6   n , composed of silicon, and a high-blocking-capability semiconductor switch  8   1 ,  8   2 , . . . ,  8   n  composed of silicon carbide. In the illustrated embodiment of FIG. 4, an n-channel MOSFET is provided with a low-blocking-capability semiconductor switch  6   1 ,  6   2 , . . . ,  6   n , in particular a low-voltage power MOSFET, and a junction FET, also referred to as a junction field effect transistor (JFET), is provided as the high-blocking-capability semiconductor switch  8   1 ,  8   2 , . . . ,  8   n . Thus, FIG. 4 shows a number of cascode circuits  4   1 ,  4   2 , . . . ,  4   n  which are known from German Patent 196 10 135 and are electrically connected in parallel. To this end, the main connections D 1 , D 2 , . . . , D n  of the high-blocking-capability semiconductor switches  8   1 ,  8   2 , . . . ,  8   n  and the reference connections S′ 1 , S′ 2 , . . ., S′ n  of the parallel-connected cascode circuits  4   1 ,  4   2 , . . . ,  4   n  are each electrically conductively connected. Each cascode circuit  4   1 ,  4   2 , . . . ,  4   n  is driven by means of a control signal U St1 , U St2 , . . . , U Stn , with this control voltage U St1 , U St2 , . . . , U Stn  being applied to a control connection G′ 1 , G′ 2 ,. . . G′ n  of the low-blocking-capability semiconductor switch  6   1 ,  6   2 , . . . ,  6   n . The control connection G 1 , G 2 , . . . , G n  of the high-blocking-capability semiconductor switch  8   1 ,  8   2 , . . . ,  8   n  is electrically conductively connected to the reference connection S′ 1 , S′ 2 , . . . , S′ n  of the cascode circuit  4   1 ,  4   2 , . . . ,  4   n .  
         [0023]    As already mentioned and illustrated in FIG. 4, each cascode circuit  4   1 ,  4   2 , . . . ,  4   n  has a MOSFET composed of silicon as the low-blocking-capability semiconductor switch  6   1 ,  6   2 , . . . ,  6   n  and a JFET composed of silicon carbide as the high-blocking-capability semiconductor switch  8   1 ,  8   2 , . . . ,  8   n . Thus, in this embodiment, the cascode circuit  4   1 ,  4   2 , . . . ,  4   n  is also referred to as a hybrid power MOSFET. An insulated gate bipolar transistor or a bipolar transistor can, in each case, be provided as the semiconductor switch  6   1 ,  6   2 , . . . ,  6   n  composed of silicon and as the semiconductor switch  8   1 ,  8   2 , . . . ,  8   n  composed of silicon carbide. It is also possible to provide a MOSFET in each case as the semiconductor switches  6   1 ,  6   2 , . . . ,  6   n  and  8   1 ,  8   2 , . . ,  8   n    
         [0024]    The apparatus  2  for balancing the power loss in a number of electrically parallel-connected cascode circuits  4   1 ,  4   2 , . . . ,  4   n  has, for each cascode circuit  4   1 ,  4   2 , . . . ,  4   n , correction value U K1 , U K2 , . . . , U Kn , and an adder  14   1 ,  14   2 , . . . ,  14   n . Further, this apparatus has a nominal value former  6 . Each voltage measurement device  10   1 ,  10   2 , . . . ,  10   n  is linked on the input side to a main connection D′ 1 , D′ 2 , . . . , D′ n  and to a reference connection S′ 1 , S′ 2 , . . . , S′ n  of an associated low-blocking-capability semiconductor switch  6   1 ,  6   2 , . . . ,  6   n . On the output side, each voltage measurement device  10   1 ,  10   2 , . . . ,  10   n  is connected to an actual value input of the device  12   1 ,  12   2 , . . . ,  12   n . On the output side, this device  12   1 ,  12   2 , . . . ,  12   n  is linked to a first input of an associated adder  14   1 ,  14   2 , . . . ,  14   n , to whose second input a control signal U St1 , U St   2 , . . . , U Stn  is applied.  
         [0025]    The nominal value former  16  has a current measurement device  18 , a divider  20  and a multiplier  22 . The current measurement device  18  is arranged in the supply lead  24  to the parallel circuit comprising the n cascode circuits  4   1 ,  4   2 , . . . ,  4   n , and is linked on the output side to a first input of the divider  20 . A number n is applied to the second input of this divider  20 . On the output side, this divider  20  is connected to an input of the multiplier  22 , to whose second input a proportionality factor k is applied. The output of this multiplier  12  is in each case linked to a nominal value input of the device  12   1 ,  12   2 , . . . ,  12   n  for establishing a correction value U K1 , U K2 , . . ., U Kn . The divider  20  is used to obtain an n-th part of this current from a measured load current I L . This n-th part of the load current I L  flows through the n cascode circuits  4   1 ,  4   2 , . . . ,  4   n  when the current distribution is balanced. This n-th part of the load current I L  is converted by the multiplier  22  and a proportionality factor k to a voltage value which is supplied as a nominal value U *   D′S′  to each device  12   1 ,  12   2 , . . . ,  12   n  in the apparatus  2 .  
         [0026]    Each device  12   1 ,  12   2 , . . . ,  12   n  for establishing a correction value U K1 , U K2 , . . . , U Kn  has a control loop, which comprises a comparator  26   1 ,  26   2 , . . . ,  26   n  and a regulator  28   1 ,  28   2 , . . . ,  28   n . The inputs of the comparator  26   1 ,  26   2 , . . . ,  26   n  are connected to the actual value input and to the nominal value input of the device  12   1 ,  12   2 , . . . ,  12   n . The output of the regulator  28   1 ,  28   2 , . . . ,  28   n  is linked to the output of the device  12   1 ,  12   2 , . . . ,  12   n . In the illustration, the regulator  28   1 ,  28   2 , . . . ,  28   n  is a P regulator. The regulator  28   1 ,  28   2 , . . . ,  28   n  can also be a PI regulator.  
         [0027]    Each determined correction value U K1 , U K2 , . . . , U Kn  is superimposed, by means of an adder  14   1 ,  14   2 , . . . ,  14   n , on a corresponding control signal U St1 , U St2 , . . . . , U Stn . Each output of the n adders  14   1 ,  14   2 , . . . ,  14   n  produces a corrected control signal U′ St1 , U′ St2 , . . . , U′ Stn  which drives the low-blocking-capability semiconductor switch  6   1 ,  6   2 , . . . ,  6   n  in the corresponding cascode circuit  4   1 ,  4   2 , . . . ,  4   n  in such a manner that the output voltage U D′S′  of the low-blocking-capability semiconductor switch  6   1 ,  6   2 , . . . ,  6   n  is increased or reduced as a function of the unbalance in such a way that the unbalance is cancelled out. This means that each output voltage U D′S′  of the low-blocking-capability semiconductor switches  6   1 ,  6   2 , . . . ,  6   n  in the n cascode circuits  4   1 ,  4   2 , . . . ,  4   n  is regulated to the predetermined nominal value U *   D′S′ .  
         [0028]    [0028]FIG. 5 shows, in more detail, an exemplary embodiment of the first embodiment of the apparatus  2  for balancing the power loss in a number of electrically parallel-connected cascode circuits  4   1 ,  4   2 , . . . ,  4   n  as shown in FIG. 4. This embodiment differs from the embodiment shown in FIG. 4 in that no nominal value former  16  is used. To this end, each device  12   1 ,  12   2 , . . . ,  12   n  has an adding device  30   1 ,  30   2 , . . . ,  30   n  which has n inputs. Each input of this adding device  30   1 ,  30   2 , . . . ,  30   n  forms an actual value input of a device  12   1 ,  12   2 , . . . ,  12   n , which is linked to an output of the n voltage measurement devices  10   1 ,  10   2 , . . . ,  10   n . On the output side, each adding device  30   1 ,  30   2 , . . . ,  30   n  is linked to a divider  32   1 ,  32   2 , . . . ,  32   n , to whose second input a number n is applied. On the output side, each divider  32   1 ,  32   2 , . . . ,  32   n  is connected to a nominal value input of an associated control loop, whose output forms an output of a device  12   1 ,  12   2 , . . . ,  12   n  for establishing a correction value U K1 , U K2 , . . . , U Kn . Each adding device  30   1 ,  30   2 , . . . ,  30   n  and each divider  32   1 ,  32   2 , . . . ,  32   n  each form a mean-value former.  
         [0029]    [0029]FIG. 6 shows, in more detail, a further advantageous embodiment of the apparatus  2  for balancing, as shown in FIG. 4. In comparison to the embodiment shown in FIG. 5, the apparatus  2  in this embodiment has only one mean-value former instead of n mean-value formers, each comprising an adding device  30   1 ,  30   2 , . . . ,  30   n  with a downstream divider  32   1 ,  32   2 , . . . ,  32   n . Otherwise, this embodiment is identical to the embodiment shown in FIG. 5.  
         [0030]    FIGS.  7  to  9  illustrate embodiments of the apparatus  2  for balancing the power loss in a number of electrically parallel-connected cascode circuits  4   1 ,  4   2 , . . . ,  4   n  as shown in FIGS.  4  to  6 , with each cascode circuit  4   1 ,  4   2 , . . . ,  4   n  having a controllable decoupling device  34   1 ,  34   2 , . . . ,  34   n . This controllable decoupling device  34   1 ,  34   2 , . . . ,  34   n  connects the control connection G 1 , G 2 , . . . , G n  of the high-blocking-capability semiconductor switch  8   1 ,  8   2 , . . . ,  8   n  to the reference connection S′ 1 , S′ 2 , . . . , S′ n  of the associated low-blocking-capability semiconductor switch  6   1 ,  6   2 , . . . ,  6   n . A controllable voltage source is provided as the controllable decoupling device  34   1 ,  34   2 , . . . ,  34   n . If a resistor is connected electrically in series with the controllable voltage source, then this controlled voltage source generates a current value as a function of the resistance. This embodiment is required for current-controlled semiconductor switches  8   1 ,  8   2 , . . . ,  8   n  in the cascode circuit  4   1 ,  4   2 , . . . ,  4   n .  
         [0031]    The embodiment of the apparatus  2  shown in FIGS.  7  to  9  differs by virtue of the use of the controlled decoupling device  34   1 ,  34   2 , . . . ,  34   n  from the embodiments of the apparatus  2  shown in FIGS.  4  to  6  in that there is no longer any need for any adders  14   1 ,  14   2 , . . . ,  14   n . The correction values U K1 , U K2 , . . . , U Kn  generated by the device or devices  12  or  12   1 ,  12   2 , . . . ,  12   n  are supplied to the associated controlled decoupling devices  34   1 ,  34   2 , . . . ,  34   n . Otherwise, the apparatuses  2  shown in FIGS.  7  to  9  correspond to the apparatus  2  shown in FIGS.  4  to  6 . The use of the n controlled decoupling devices  34   1 ,  34   2 , . . . ,  34   n  in a parallel circuit of n cascode circuits  4   1 ,  4   2 , . . . ,  4   n  results in an increased forward voltage in each case being dropped across the high-blocking-capability semiconductor switches  8   1 ,  8   2 , . . . ,  8   n  in the cascode circuits  4   1 ,  4   2 , . . . ,  4   n .  
         [0032]    Although the present invention has been described in detail with reference to specific exemplary embodiments thereof, various modifications, alterations and adaptations may be made by those skilled in the art without departing from the spirit and scope of the invention. It is intended that the invention be limited only by the appended claims.