Abstract:
A sorting apparatus is composed of sort processors connected in a pipeline fashion. Each sort processor 106 merge sorts data from the preceding sort processor and then outputs the merge sort result to the succeeding sort processor. The sort processor includes sort core portions and a front end internal storage and a back end internal storage for the respective sort core portions. Outside the sort processors, there are added external memories for the respective sort core portions. The front and back end internal storages and the external memories constitute a local memory. The sort core portions use, when a faulty area is found in the local memory, part of the front end and back end internal storages as an alternative memory.

Description:
This application is a continuation of application Ser. No. 08/190,272, filed Feb. 2, 1994 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to an apparatus for sorting a large quantity of data at high speed, and more particularly to an apparatus for continuously sorting a large quantity of data with sort-dedicated processors connected in a pipeline fashion. 
     2. Description of the Related Art 
     A sorting apparatus is currently known in which a number of sort processors are connected in a pipeline fashion to sort a large quantity of data at high speed. In the conventional sorting apparatus shown in FIG. 9 of the accompanying drawings, a device in which two sort cores are contained in a package (i.e., doublestage sort processor) is used. An alternative device in which one sort core is contained in a single package (i.e., a singlestage processor) may be used for the same operation. 
     As shown in FIG. 9, firstly data to be sorted from an input/output path 1 is inputted in series. One item of data inputted to a sort processor 6 via the input/output path 1 is then stored in a front end internal storage 4 corresponding to a front end sort core portion 2 in the sort processor 6. 
     When another item of data is inputted from the input/output path 1, the front end sort core portion 2 merge-sorts one item of such newly inputted data and the data stored in the front end internal storage 4 as mentioned above, and outputs the sorted output string. Namely, this output string contains two items of data. Thus the front end sort core portion 2 outputs successively the sorted strings each containing two items of data. The storage situated at an each end is called a local memory. 
     The output string containing these two items of data is then supplied to the back end sort core portion 3. The back end sort core portion 3 stores the string, which is to be outputted from the front end sort core portion 2, firstly in the back end internal storage 5 corresponding to the back end sort core portion 3. When another output string is outputted from the front end sort core portion 2, the stored string and the new string inputted to the back end sort core portion 3 are merge-sorted, and an output string containing four items of (sorted) data is outputted. 
     Thus the back end sort core portion 3 merge-sorts two strings, i.e. those containing two items of data, which are to be outputted from the front sort core portion 2, and outputs successively an output string containing four items of data. As shown in FIG. 9, the back end internal storage 5 has a capacity two times larger than that of the front end internal storage 4. This is because the back end internal storage 5 is required to have a larger capacity in order that the back end sort core portion 3 can deal with longer strings, compared to the front end sort core portion 2. 
     FIG. 10 is a timing chart showing the access timing for the front end and back end internal storages (local memories) 4, 5 in the conventional sorting apparatus. 
     In either the front end or the back end sort core portion 2, 3, sorting by 2-way merging takes place so that the strings each containing two items of sorted data are outputted successively in the j-th front end (or back end) sort core portion 2 (or 3). 
     In the conventional art, two connected sort core portions, i.e. front end and back end sort core portions 2, 3, are stored in a single sort processor 6. A number of sort processors 6 are connected in series to form a pipeline. In FIG. 9, a nineteen-step pipeline is shown. In order to constitute the nineteen-step pipeline, as shown in FIG. 8, 9 and 11, ten sort processors are used, and the front end sort core portion 2 of the first sort processor 6 is not used. 
     According to the conventional arrangement of FIG. 9, on the back side of the back end sort core portion 3 of the fourth sort processor 6, external memories 7, 8, 9 are situated outside the sort processor 6 as local memories. This is because as merge-sort is repeated, the string will become progressively longer towards the last sort processor so that the front end and back end internal storage 4, 5 situated in the sort processor 6 will not suffice. 
     Generally, for the front end and back end internal storages 4, 5 in the sort processor 6, high speed SRAMs are often used. For the external memories 7, 8, 9, whose capacity is large, it is more usual to use DRAMs. 
     In FIG. 9, of the storage, the portion to be used as a local memory is indicated by hatching. Specifically, at the step in which the external memories 7, 8, 9 are to be used as a local memory, none of the front end or back end internal storages 4, 5 are used at all. This is because it is difficult to make addresses continuous between the internal and external memories. 
     In the conventional art of FIG. 9, ten sort processors 6 are used, and nineteen sort core portions are connected in a pipeline fashion. Therefore the result of sorting 2 19  items of data can be obtained as the final output. 
     With this conventional arrangement, at the step in which the external memories are used as a local memory, none of the front end or back end internal storages 4, 5 are used. Also at the step in which only the front end and back end internal storages 4, 5 are used, the local memory requires a different capacity for every step so that an unused portion will inevitably be created. 
     As shown in FIG. 9, for example, in the first sort processor 6-1 including the first and second sort core portions 2, 3, such an unused portion is larger than in the second sort processor 6-2 including the third and fourth sort core portions 2, 3. This problem can be avoided by using a dedicated processor for every step, but it would result in a massive increase in production costs. 
     In the conventional sorting apparatus, since all the sort processors constitute a pipeline, operations at the individual steps must take place in synchronism. Consequently, it has been customary to supply a common clock signal to the sort core portions at the individual steps; this clock signal must be set so as to be usable by the lowest speed component in the system. In this conventional art, since the step in which DRAM situated outside as a local memory is used will become slowest, the entire operating speed will be adjusted to the operating speed at the stage whose local memory&#39;s access speed is the slowest. This is because generally an external DRAM has a slower access speed than the internal SRAM. 
     Further, when a fault occurs in a local memory, it is necessary to stop operation of the sorting apparatus and to specify the location of the fault, whereupon the faulty part must be changed with a new one. As a result, it used to take rather a long time for the apparatus to recover from the faulty condition. 
     SUMMARY OF THE INVENTION 
     With foregoing problems in mind, the objective of this invention is to provide a sorting apparatus which enables downsizing. 
     Another objective of the invention is to provide a sorting apparatus which enables high speed operation. 
     Still another objective of the invention is to provide a sorting apparatus which can improve RAS for the entire apparatus. 
     According to the first aspect of the invention, there is provided a sorting apparatus equipped with a number of sort processors connected in a pipeline fashion, wherein each of the sort processors comprises: a local memory for storing the first output string, which is to be outputted from the preceding sort processor, as the first data string; a sort core unit for merge-sorting the second output string, which is to be outputted from the preceding sort processor next to the first output string, and the first data string stored in the local memory and for outputting the result of sorting by merging to the succeeding sort processor; and the sort core unit in operation, when a faulty area is detected in the local memory, to use as an alternative memory of an area in which the first output string in the local memory is not stored. 
     With the first arrangement of the invention, since the unused area of the local memory can be used as an alternative memory of the faulty part, it is not necessary to change the faulty part with a new one and it is possible to continue the operation. 
     Therefore, since the unused portion of the local memory is used when a fault is found in the local memory, it is possible to continue sorting without removing the faulty part. As a result, an improved rate of operation can be achieved. 
     According to the second aspect of the invention, there is provided a sorting apparatus equipped with a number of sort processors, wherein each of the sort processors comprises: a local memory for storing the first output string, which is to be outputted from the preceding sort processor, as the first data string, the local memory including a low speed portion whose access speed is slow, and a high speed portion whose access speed is fast; a sort core unit for merge sorting the second output string, which is to be outputted from the preceding sort processor next to the first output string, and the first data string stored in the local memory and for outputting the merge sort result to the succeeding sort processor; and the sorting core unit including transfer means for, when reading of the first data string from the high speed portion of the local memory is started, transferring data from the low speed portion to an address in the high speed portion from which the data has been read, and access adjusting means for, when data from the low speed portion is read, returning the data, which is transferred by the transfer means, to the sort core unit at high speed. 
     With the second arrangement of the invention, since the high speed portion of the local memory acts as a buffer storage for the low speed portion, it is possible to improve the access speed to the low speed portion remarkably. 
     Thus since the high speed portion is used as a high speed buffer storage, it is possible to reduce the access time to the low speed portion whose access time is long. As a result, it is possible to realize a sorting apparatus which is inexpensive to manufacture and enables improved performance. 
     According to the third aspect of the invention, there is provided a sorting apparatus equipped with a number of sort processors connected in a pipeline fashion, and a number of external local memories, one for each of the sort processors, for storing the first output string, which is to be outputted from the preceding sort processor, as the first data string, wherein each of the sort processors includes a sort core unit for merge-sorting the second output string, which is to be outputted from the preceding sort processor next to the first output string, and the first data string stored in the local memory and for outputting the merge-sort result to the succeeding sort processor, and wherein two or more of the external local memories are situated in a common memory which is shared by a number of the sort processors. 
     With the third arrangement of the invention, since the common memory is shared by the plural sort processors, it is possible to reduce the unused portions so that efficient use of the local memory can be achieved. 
     Thus since the local memory is shared by the plural sort processors, it is possible to reduce the unused portions of the local memory. As a result, it is possible to improve the efficiency of use of memories so that a compact-size apparatus can be realized. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a fragmentary block diagram showing a sorting apparatus according to the first embodiment of this invention; 
     FIG. 2 is a detailed view showing a sort core unit of FIG. 1; 
     FIG. 3 is a flow diagram showing the error recovery procedure of the sorting apparatus of the first embodiment; 
     FIG. 4 is a block diagram showing one of the sort processors to be used in a sorting apparatus according to the second element; 
     FIG. 5 is a diagram showing the data transfer between an internal storage and an external memory in the sorting apparatus of FIG. 4; 
     FIG. 6 is a timing diagram showing the operation of the sorting apparatus of FIG. 2; 
     FIG. 7 is a diagram showing the manner of use of a local memory in a sorting apparatus according to the third embodiment; 
     FIG. 8 is a block diagram showing a sorting apparatus according to the fourth embodiment; 
     FIG. 9 is a block diagram showing a conventional sorting apparatus; 
     FIG. 10 is a timing diagram showing the memory access of the conventional sorting apparatus; and 
     FIG. 11 is a block diagram showing another conventional double-sorter sorting apparatus. 
    
    
     DETAILED DESCRIPTION 
     Several preferred embodiments of this invention will now be described with reference to the accompanying drawings. 
     Embodiment 1 
     FIG. 1 is a block diagram showing a sorting apparatus according to the first embodiment of this invention. A number of sort processors 106 constituting the sorting apparatus of this embodiment each include, as shown in FIG. 1, a front end sort core portion 102, a back end sort core portion 103, and a decoder 130 for designating a memory, which is to be used as a local memory, for the front end and back end sort core portions 102, 103. The decoder 130 supplies an access switching bit to the front end and back end sort core portions 102, 103 to designate front end and back end internal storages 104, 105 or external memories 107, 108, 109 to be used. 
     The decoder 130 designates the access switching bit according to a selection signal (1)-(4) from an external source. 
     This embodiment is characterized in that the access switching bit for changeover between the front end and back end internal storages 104, 105 and the external memories 107, 108, 109 is designated by the decoder 130. Accordingly it is possible to designate from outside so that access will be made to the internal storages if the switching bit is &#34;0&#34; and to the external memories if the switching bit is &#34;1&#34;. It is therefore possible to make access to the front end and back end internal storages 104, 105 and external memories 107, 108, 109 successively. 
     FIG. 2 is a detailed block diagram showing the front end and back end sort core portions 102, 103 of FIG. 1. As shown in FIG. 2, each of the front end and back end sort core portions 102, 103 includes a local memory address generating block 100. Each sort core portion 102, 103 also includes an error address register 170, a comparator 171, a 2-to-1 selector 172, and an address translator 173. 
     The operation of the sorting apparatus will now be described. 
     The sorting apparatus of the first embodiment is designed so as to make a self-diagnosis by a diagnostic program at the start of the system. In the diagnostic program at the start of the system or in the memory read cycle during the actual operation, if an ECC (Error Correction Code) 2-bit error is detected, an unable-to-continue-sort-operation error will be reported to a host unit, which is a sorter drive unit serving as an interface between a host computer and the sorting apparatus. 
     FIG. 3 is a flow diagram showing such an error recovery procedure. As shown in FIG. 3, when this unable-to-continue-sort-operation error is reported, the host unit issues a temporary stop signal for every step of the sorting apparatus to store in an error address register 170 an address at which the error has occurred (step ST3-2). 
     If an ECC error occurs once again at the same address stored in the error address register while `retry` is set, namely, while `yes` is selected at step ST3-3 (if `yes` is selected at step ST3-5), the comparator 171 detects this. At that time, the address translator 173 of FIG. 2 designates empty areas of the front end and back end storages 104, 105 according to a detection signal outputted from the comparator 171. In other words, the empty areas are used as an alternative memory (step ST3-6). Thus an address signal designating the empty areas will be outputted via the selector 172. 
     If no coincidence is found by the comparator 171 (if `no` is selected at step ST3-5), an address signal will be outputted from address buses 110, 120 via the selector 172. 
     If the address to be stored in the error address register 170 is to be processed by an error recovery system, it will be held until a reset signal is inputted. The comparison of the comparator 172 will be executed at every memory access after retry. If coincidence is found as a result of the comparison, the address translator 173 will output an address signal to the front end and back end internal storages 104, 105. 
     According to the first embodiment, since the unused portions in the front end and back end internal storages 104, 105 are used as an alternative memory, it is not necessary to change any part with a new one, during which the apparatus must be stopped, even when a faulty portion is found in the external local memory. 
     Embodiment 2 
     FIG. 4 is a block diagram showing one of the sort processors 106 used in a sorting apparatus according to the second embodiment. As shown in FIG. 4, according to the sort processor 106 of the second embodiment, switching signals outputted from the sort core portion 102 as local memory address signals are supplied to the front end internal storage 104 via an internal bus 110 and to the external memory via an external bus 120, respectively. 
     The data read from the front end internal storage 104 is inputted to the front end sort core portion 102 via an internal read bus 115. In this embodiment, for data writing, a block pointer, which indicates the next address, is stored in the local memory together with the data. 
     A feature of this embodiment is that the front and back end internal storages 104, 105 are used as a high-speed buffer storage. 
     In merge sort, addresses are continuously accessed. Therefore, the data stored in the external memory 107 can be read after it has been read from the front end or back end internal storage 104, 105. In this embodiment, with a view to this point, every time data is read from the front end internal storage 104, data from the external memory 107 will be transferred to the front internal storage 104. When access is made to the external memory 107, the data transferred to the front end internal storage 104 will be read. 
     FIG. 5 is a diagram showing the access timing in the case where the front end internal storage 104 is used as a high-speed buffer storage. In FIG. 5, the boxes shown on the left side indicate the front end internal storages 104 serving as high-speed buffer storages, while the boxes shown on the right side indicate the external memories 107. 
     The operation of the sorting apparatus of the second embodiment will now be described in detail. 
     FIG. 5 shows the block transfer of data between the front end internal storage 104 and the external memory 107 as mentioned above. In the example of operation shown in FIG. 5, a string A is stored in the external memory 107, and it will then be read before the next string B is stored there. In FIG. 5, time lapses vertically, i.e., from (1) toward (6). 
     At (2) of FIG. 5, the front end or back end sort core portion 102, 103 reads one block of data from the front end internal storage 104. Then at (3), one block of data is transferred from the external memory 107 to the front end internal storage 104. Since the block of data read at (2) will not read again, another block data read from the external memory 107 will be stored if one block of data has been read from the front end internal storage 104. 
     According to this embodiment, in the sorting apparatus in which the high-speed front end internal storage 104 and the low-speed external memory 107 are used as local memories, it is possible to make the access time to the external memory 107 considerably short by previously transferring the data of the external memory 107 to the front end internal storage 104 every time the data is read from the external memory 107. FIG. 6 is a timing diagram showing the operation of the sorting apparatus of this embodiment. 
     In the second embodiment, either the front end internal storage 104 or the external memory is used as a local memory. Alternatively only the external memory 107 may be used as a local memory. Namely, in this alternative case, since the front end internal storage 104 is unused, not only effective use of hardware but also improved performance can be achieved by using the entire front end internal storage 104 as a high-speed buffer storage for the external memory 107. 
     Embodiment 3 
     FIG. 7 shows the manner of use of a local memory in a sorting apparatus of the third embodiment. In FIG. 7, an address signal from one of adjacent sort core portions will be outputted to the local memory via a buffer 269, while an address signal from the other sort core portion will be outputted to the same local memory via an inverter 200. As a result, although the same addresses may be outputted between the adjacent sort core portions 202, 208, these addresses would not overlap each other. 
     By allocating the access timing for the local memory shared by the adjacent sort core portions 202, 203 to the front and back halves of the fundamental clock, it is possible to shift the mutual access timings so that any access conflict can be prevented. 
     According to the third embodiment, it is possible for two sort core portions to share a single local memory. Therefore it is possible to reduce unused portions in the local memory. 
     Embodiment 4 
     FIG. 8 is a block diagram showing a sorting apparatus according to the fourth embodiment. In a conventional structure, two sorting apparatuses are arranged in opposite directions. Whereas in the fourth embodiment, a single local memory is shared by two sorting apparatuses like the third embodiment. Specifically, in the third embodiment, a single local memory is shared by a number of sort core portions in one sorting apparatus. In the fourth embodiment, one local memory is shared by different sorting apparatuses. 
     As shown in FIG. 8, the address signals outputted from the sort core portions of one sorting apparatus will be supplied to the local memories 379, 380, 390 via inverters 300. These shared local memories 379, 380, 390 are memories whose access speed is more than twice as quick as the non-shared external memories 7, 8, 9 (FIG. 10.). 
     In this embodiment, since one local memory is shared by two sorting apparatuses, it is possible to reduce unused portions in the local memory so that the sorting apparatus can be manufactured at a reduced cost without impairing the performance.