Abstract:
The invention relates to a semiconductor structure and a method for minimizing non-idealities in a semiconductor structure, in which a drain; a source, a floating gate ( 102 ) and at least one input ( 108 ) capacitively connected&#39;to the floating gate ( 102 ) are disposed on a substrate ( 105 ) so as to form a v-MOSFET transistor. According to the invention, a conductive layer insulated from the floating gate ( 102 ) and at least partially superimposed on the gate ( 102 ) is formed in the semiconductor structure and the conductive layer is connected to a constant potential.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     The present application is the U.S. national stage application of International Application PCT/FI99/00494, filed Jun. 8, 1999, which international application was published on Dec. 29, 1999 as International Publication WO 99/67827 in the English language. The International Application claims the priority of Finnish Patent Application 981301, filed Jun. 8, 1998. 
     The present invention relates to micro-electronics. In particular, the invention concerns a semiconductor structure and a method for minimising non-idealities in semiconductors. 
    
    
     BACKGROUND OF THE INVENTION 
     In the prior art, a semiconductor structure is known in which one or more inputs are capacitively connected to the gate of a MOSFET transistor (Metal Oxide Semiconductor Field Effect Transistor). In the present publication, components thus formed are referred to with the designation v-MOSFET. These components can be connected together to form more complex assemblies. FIG. 1 presents the circuit diagram and a cross-sectional view of a possible implementation. 
     The basic idea of the v-MOSFET transistor is that the input voltages are summed at the gate of the transistor in accordance with capacitive weighting co-efficients. The voltage summed at the gate is given by the equation.          φ   F     =         ∑     i   =   1     n            C   i          V   i             ∑     i   =   1     n          C   i                                
     where is the voltage at the floating gate, C i  is the weighting coefficient (capacitance) of input i and V i  is the voltage at input i. By using different combinations of weighting coefficients and inputs, it is possible to implement many functions, such as electric neurons or A/D and D/A converters. 
     In the V-MOSFET structures presented, a problem is that there are variations and non-idealities in the semiconductor manufacturing process. In addition to the designed inputs, the capacitive coupling between the gate and the substrate causes distortion of the summing. 
     In the manufacturing process of semiconductor circuits, certain parameters change from one process run to the next, e.g. when there are variations in the alignment of manufacturing masks or in layer thickness. The properties of complex components, such as transistors, are determined by the combined effect of several parameters. Thus, for instance, the threshold voltage of a transistor may vary by as much as ten per cent. FIG. 2 illustrates simulation of the effects of process variations on the threshold voltage of a transistor. In the design of complex v-MOSFET structures, it would be desirable to be able to increase the number of inputs to provide as many inputs as possible. Process variations can be reduced by developing the process itself or by lowering the tolerances permitted in the process, but this leads to increased manufacturing costs. It would also preclude the use of known advantageous manufacturing processes. 
     The object of the present invention is to eliminate or at least to significantly reduce the problems described above. A further object of the invention is to disclose a new type of semiconductor structure and a method by which non-idealities due to variations in the IC process as well as internal non-idealities in semiconductors can be minimised by electric means. 
     BRIEF DESCRIPTION OF THE INVENTION 
     The invention concerns a method for minimising non-idealities in a semiconductor structure in which a drain, a source, a floating gate and at least one input are disposed on a substrate, the input being capacitively connected to the floating gate. Said semiconductor structure is preferably a v-MOSFET transistor. According to the invention, a conductive layer insulated from the floating gate and at least partially superimposed on the gate is formed in the semiconductor structure. The conductive layer is connected to a constant potential suitably selected, allowing non-idealities of the semiconductor structure to be minimised. 
     In a preferred embodiment of the invention, an eliminating grid at least partially covering the floating gate is formed from the conductive layer. In this case, the constant potential can be used to eliminate the parasitic substrate capacitance of the floating gate. 
     In a preferred embodiment of the invention, a control grid of the same material with the input is formed from the conductive layer. The control grid is capacitively connected to the floating gate, in a manner corresponding to the input connection. The control grid is preferably formed in the same layer with the input. 
     In a preferred embodiment of the invention, a basin located at least partially under the floating gate is formed from the conductive layer. 
     In a preferred embodiment of the invention, the conductive layer according to the above-described methods is divided into at least two sections so that the potentials of different sections can be controlled independently of each other. The sections can be controlled digitally. The proportions of the sections can also be distributed with a binary weighting. 
     Moreover, the invention concerns a semiconductor structure comprising a substrate with a drain, source, floating gate and at least one input disposed on it, the input being capacitively connected to the floating gate. According to the invention, the semiconductor structure comprises a conductive layer insulated from the floating gate and at least partially superimposed on the gate. In addition, the conductive layer is connected to a constant potential. 
     A semiconductor structure according to the invention comprises an eliminating grid formed from the semiconductor structure and at least partially extending over the floating gate. 
     A semiconductor structure according to the invention comprises a control grid formed from the conductive layer and made of the same material with the input, said control grid being capacitively connected to the floating gate. The control grid is preferably formed in the same layer with the input. 
     A semiconductor structure according to the invention comprises a basin formed from the conductive layer and disposed at least partially under the floating gate. 
     In certain embodiments, the semiconductor structures described above are implemented by dividing the conductive layer into at least two sections, allowing the potentials in different sections to be controlled independently of each other. In a preferred case, different sections are provided with digital control. The proportions of the sections can also be distributed with a binary weighting. 
     The semiconductor structure of the invention can be applied in various implementations, such as A/D converters, digital logic gates, neural network connections, D/A converters or comparators, in which the offset can be electrically corrected. 
    
    
     LIST OF ILLUSTRATIONS 
     In the following, the invention will be described by the aid of a few examples of its embodiments with reference to the attached drawing, in which 
     FIG. 1 a  presents an example of a circuit diagram for a v-MOSFET transistor; 
     FIG. 1 b  presents a sectional side view of a v-MOSFET transistor provided with an eliminating grid; 
     FIG. 1 c  presents a sectional top view of a v-MOSFET transistor provided with an eliminating grid; 
     FIG. 2 presents the DC transfer function of a simulated inverter with different transistor parameters; 
     FIG. 3 a  presents an example representing the simulated potential of the floating gate of a v-MOSFET transistor as a function of the voltage of the eliminating grid; 
     FIG. 3 b  presents the circuit used in the simulation; 
     FIG. 4 a  presents the DC transfer function of a simulated inverter when the states of the control grids are varied; 
     FIG. 4 b  presents the circuit used in the simulation; 
     FIG. 5 a  presents a sectional side view of another V-MOSFET structure comprising control grids; 
     FIG. 5 b  presents a sectional top view of a v-MOSFET structure comprising control grids; 
     FIG. 6 presents a diagram representing a circuit for generating control grid voltages; 
     FIG. 7 a  presents a sectional side view of a V-MOSFET structure comprising a conductive layer below the floating gate; 
     FIG. 7 b  presents a sectional top view of a v-MOSFET comprising a conductive layer below the floating gate; 
     FIG. 8 a  presents the DC transfer function of a simulated inverter when the states of the control grids are varied; and 
     FIG. 8 b  presents the circuit used in the simulation. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 b  shows a side view and FIG. 1 c  a top view of a semiconductor structure according to the invention, presented by way of example. It is to be noted that the dimensions shown in the figures are only one example of an implementation according to the present invention. 
     The semiconductor structure is implemented on a substrate  105 . The substrate usually consists of single-crystal silicon. The v-MOSFET transistor comprises an active region  104  and a floating gate  102 , which has been formed from a second polysilicon layer. Polysilicon can also be replaced with some other conductive material applicable. The transistor may be an enhancement-type or a depletion-type transistor. Gate insulation  103  is provided between the active region  104  and the gate  102 . The floating gate  102  is controlled by control grids  108 , which have been formed from the lower polysilicon layer and insulated from the upper polysilicon layer by using e.g. nitride in the manufacturing process. The control grids  108  are insulated from the substrate  105  by a dielectric layer  106  of field oxide. Between the polysilicon layers and the metal layer formed on top of them there is a protecting dielectric layer  101  of silicon dioxide. 
     Elimination of parasitic substrate capacitance can be implemented by processing e.g. a metallic conductor layer onto the floating gate  102  and forming an eliminating grid  107  from this layer. The eliminating grid  107  can also be disposed below the floating gate  102 . The eliminating grid is insulated from the floating gate by an insulating layer  101 . According to the invention, a constant potential is applied to the eliminating grid  107 . 
     FIG. 3 illustrates a simulation arrangement in which the voltage of the eliminating grid  107  is varied while at the same time applying a constant voltage, e.g. VDD/ 2 , to the main inputs  108 . It can be seen from the figure that, with this structure, when the eliminating grid voltage is 10 V, the floating gate voltage V(FG) equals VDD/ 2 , in other words, the effect of parasitic substrate capacitance has been completely eliminated. 
     Due to other non-idealities in the semiconductor, it is not necessarily appropriate trying to achieve complete compensation of substrate capacitance by this method. In some non-critical applications, sufficient compensation can be accomplished by connecting the eliminating grid  107  to the operating voltage. 
     In v-MOSFET circuits, the non-idealities described in the preamble can also be cancelled by using a circuit as illustrated in FIG. 4. A cross-section of the structure implemented in this case is presented in FIG.  5 . In addition to the main inputs  108 , the structure comprises control grids  109  formed in the lower polysilicon layer. The order of the polysilicon layers relative to each other is of no importance as regards the invention; the essential point is that capacitive coupling is provided between the control grids  109  and the floating gate  102 . In conjunction with the same structure, an eliminating grid  107  can also be used. Control voltages, which may be digital voltages, are applied to the control grids  109 . For the control grids  109 , it is possible to select weighting coefficients [] capacitances with e.g. binary weighting C i ∝ 2 i−1  (i=1, 2, . . . , n). In this case, by using n control grids  109 , n 2  different base levels are obtained, regardless of the voltages at the main inputs  108 . 
     FIG. 4 a  illustrates a simulation arrangement with three control grids  109  to which all possible states are connected in turn while a ramp voltage is applied to the main inputs  108 . The number of control grids  109  required and their total capacitance are determined by the desired control accuracy and the technology used. In the example simulation, the ratio between the total coupling capacitance of the inputs  108  and the sum of the capacitances of the control grids  109  is {fraction (10/1)}. The smallest voltage change occurring at the floating gate  102  is obtained from the equation:          Δ                   φ     F                 min         =         C   1   c          V   DD             ∑     i   =   1     n          C   i       +       ∑     j   =   1     m          C   j   c                                  
     where the superscript c means control grid, n is the number of main inputs, C C   1 , is the lowest capacitance of the control grids and m is the number of control grids. The largest voltage change is obtained from the equation:          Δ                   φ     F                 max         =         ∑     j   =   1     m            C   j   c          V   DD               ∑     i   =   1     n          C   i       +       ∑     j   =   1     m          C   j   c                                  
     In the above equations, substrate capacitance and the effect of a possible eliminating grid  107  are omitted. 
     This solution provides the advantage of allowing the use of digital control. A digital control signal can be generated within the microcircuit e.g. using a circuit as shown in FIG.  6 . Using an accurate comparator and logic, a signal for controlling the control grids  109  is defined that will bring the output of the v-MOSFET circuit as close to the desired level as possible. With a control sequence generated, several v-MOSFET circuits can be controlled as the variations in process parameters between different parts of the same microcircuit are small. Thus, using this method, regulation of microcircuits containing many functions of similar nature, such as neural network circuits, can be implemented with a relatively small increase in surface area. As the price of microcircuits is directly proportional to area, considerable advantages are achieved for a small increase in price. 
     In an embodiment, corresponding digital control is implemented for an eliminating grid  107 , in which case the eliminating grid  107  processed onto the floating gate  102  is divided into several sections, in which the control is implemented. 
     Non-idealities in v-MOSFET circuits can also be compensated by forming a conductive layer, e.g. an n-type basin  110  connected to a constant potential, below the floating gate  102 . FIGS. 7 a-b  present a schematic view of a possible structure. Connected to the basin  110  via a contact  111  is a piece of conductor metal  112  to apply a constant potential to the basin  110 . In this case, the potential of the floating gate  102  will be          φ   F     =           ∑     i   =   1     n            C   i          V   i         +       C   0     ·     V   0               ∑     i   =   1     n          C   i       +     C   0                                
     where φF is the floating gate voltage, C i  is the weighting coefficient (capacitance) of input i, and V i  is the voltage at input i. In the above equation, the potential of the conductor below the floating gate  102  and the weighting coefficient have the subscript  0 . In typical IC technology, the capacitance ratio of an (actual) capacitor to be processed is typically 5-20. When an analogue control voltage (V a ) having a magnitude such that V ss &lt;V a &lt;V DD  is used, the effects of process variations on MOSFET transistors can be almost completely eliminated. FIG. 8 a  presents a simulation diagram with typical transistor parameters, with a constant voltage, e.g. V DD /2, applied to the main inputs and a ramp voltage applied to the controlling n-basin  110 . In another simulation arrangement, the transistor parameters have been changed while keeping the same input voltages. From FIG. 8 a  it can be seen that, regardless of the transistor parameters, a control voltage is found that allows the desired output voltage to be achieved. 
     It is possible to implement digital control as described above for the lower basin  110  as well. In this case, the basin below the floating gate  102  is divided into several sections and a separate control potential is applied to each section. 
     The invention is not restricted to the examples of its embodiments described above, but many variations are possible within the scope of the inventive idea defined in the claims.