Abstract:
A low drop-out (LDO) voltage regulator with a wide bandwidth power supply rejection ratio (PSRR) is described. In one aspect, the LDO voltage regulator includes two individual voltage regulator circuit stages. A first stage voltage regulator circuit output is at an intermediate voltage (VINT) between an input supply voltage (VDD) and a final regulated output voltage (VREG). A second stage voltage regulator circuit output is at the final regulated output voltage (VREG) and is optimized for noise-sensitive analog circuits across a wide operating bandwidth. The first stage voltage regulator circuit has a zero frequency while the second stage voltage regulator circuit has a matching pole frequency to minimize the AC response from VDD to VREG across all frequencies.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates generally to the field of integrated circuits, and more specifically to low drop-out (LDO) voltage regulators for noise-sensitive individual analog circuits, such as phase-lock loops (PLLs) and other embedded analog cores within a system-on-chip (SoC). 
       BACKGROUND 
       [0002]    Embedded analog circuits such as phase lock loops (PLLs), voltage controlled oscillators (VCOs), digital to analog converters (DACs), analog to digital converters (ADCs), and radio frequency (RF) transceivers rely on a wide bandwidth noise-free power supply voltages to meet phase-noise, timing-jitter, spurious-free dynamic range, and low-noise figure requirements in individual blocks. 
         [0003]      FIG. 1  is an example integrated circuit die block diagram of a SoC  100  utilizing multiple LDOs  110  connected to multiple circuit blocks  120  tied to a common externally supplied voltage VDD. 
         [0004]    As more SoC designs progress toward embedding more analog circuits along with digital processors in the same silicon die, it is desirable to include independent low-noise voltage regulators for each embedded analog core to improve circuit isolation. 
         [0005]    Low Drop-Out (LDO) voltage regulators have been traditionally used to meet this requirement. However, it is a design challenge to implement a wide bandwidth power supply rejection ratio (PSRR) LDO voltage regulator using only on-chip components. 
         [0006]    Traditionally phase lock loops (PLLs) and embedded analog cores use independent power-supply bumps to get a clean power supply connection. The number of power-supply bumps and silicon die bond pads increases as multiple PLLs and embedded analog cores are integrated into a system-on-chip (SoC). 
         [0007]    The power-supply bumps refer to a solder ball connection between a packaged integrated circuit (IC) and the main application circuit board. By incorporating LDO voltage regulators on the IC, the number of power-supply and ground connections can be minimized, thereby reducing the packaged IC pin count, chip and main application circuit board routing complexity. 
         [0008]      FIG. 2  is a schematic diagram of a known single-stage low drop-out (LDO) voltage regulator. A typical single stage LDO voltage regulator  200 , as shown, may be implemented using an error amplifier circuit  202  driving a common-source P-channel metal oxide semiconductor (PMOS) device  204 . PMOS device  204  has a decoupling capacitor (CL)  205  coupled at the drain D of PMOS device  204  to suppress power-supply noise leakage from an input voltage VDD. At the drain D of PMOS device  204  is an output node VREG. PMOS device  204  is usually large (in terms of integrated circuit die area) to maintain the voltage drop low across PMOS device  204  (VDD-VREG). Node VREG is also connected to an integrated circuit (IC) load  208 . IC load  208  includes the decoupling capacitor (CL)  205  which is in parallel with a resistive load (RL)  209  and a current device (IL)  210 . 
         [0009]    The configuration of PMOS device  204  and IC load  208  results in two closely-spaced poles that require compensation for stability. In general, a Miller-compensation capacitor (Cc)  206  is used to realize a dominant pole at gate G of PMOS device  204 . However, the Miller-compensation capacitor (Cc)  206  results in a zero in the transfer function between the supply voltage (VDD) to LDO voltage regulator output voltage (VREG) (herein after referred to the “supply-to-output transfer function”). A zero in the supply-to-output transfer function compromises the power supply rejection ratio (PSRR) at frequencies above the stated zero frequency. 
         [0010]    A reference voltage VREF is provided on the inverting terminal  211  of the error amplifier circuit  202 . The output voltage from the error amplifier circuit  202  is denoted as Vout. A feedback loop extends from the VREG node to the non-inverting terminal  212  of the error amplifier circuit  202 . VREF is typically provided by a precision band-gap reference and is equal to the desired VREG voltage. Alternatively, VREF may be a programmable voltage by using a band-gap reference in conjunction with a digital-to-analog converter to set the desired VREG voltage. 
         [0011]      FIG. 3  is an example graph of the wide bandwidth supply rejection from VDD (input) to VREG (output) vs. Frequency (Hz) for the single-stage LDO voltage regulator shown in  FIG. 2 . 
         [0012]    As shown in  FIG. 3 , the supply rejection from VDD to VREG vs. Frequency (Hz), for LDO voltage regulator  200  of  FIG. 2 , may be compromised by the zero frequency location. The rejection is limited to −40 dB at low frequencies (less than 400 kHz in this example) and worsens from approximately 1 MHz to 10 GHz as a result of the zero in the transfer function. The worst case supply rejection is approximately −15 dB at 100 MHz in this example. In the presence of wide bandwidth noise on the VDD source voltage, an LDO voltage regulator, with such poor PSRR, will compromise analog circuit block performance in PLLs, VCOs, DACs, ADCs, and RF transceivers utilizing a suitable VREG output voltage. 
         [0013]    There is a need therefore for a low drop-out (LDO) voltage regulator integrated circuit with improved wide bandwidth power supply rejection ratio (PSRR). 
       SUMMARY 
       [0014]    A low drop-out (LDO) voltage regulator with a wide bandwidth power supply rejection ratio (PSRR) is described. In one aspect, the LDO voltage regulator includes two individual voltage regulator circuit stages. A first stage voltage regulator circuit output is at an intermediate voltage (VINT) between an input supply voltage (VDD) and a final regulated output voltage (VREG). A second stage voltage regulator circuit output is at the final regulated output voltage (VREG) and is optimized for noise-sensitive analog circuits across a wide operating bandwidth. The first stage voltage regulator circuit has a zero frequency while the second stage voltage regulator circuit has a matching pole frequency to minimize the AC response from VDD to VREG across all frequencies. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is an example integrated circuit die block diagram with LDOs for multiple circuit blocks tied to a common externally supplied voltage, VDD. 
           [0016]      FIG. 2  is a schematic diagram of a conventional single-stage low drop-out (LDO) voltage regulator. 
           [0017]      FIG. 3  is an example graph of the wide bandwidth supply rejection from VDD (input) to VREG (output) vs. Frequency (Hz) for the single-stage LDO voltage regulator shown in  FIG. 2 . 
           [0018]      FIG. 4  is a schematic diagram of a two-stage, wide bandwidth, power supply rejection ratio LDO voltage regulator in accordance with a preferred embodiment. 
           [0019]      FIG. 5  is an example graph of supply rejection for the transfer functions between VDD to VINT, VINT to VREG, and VDD to VREG vs. Frequency (Hz) for the LDO voltage regulator shown in  FIG. 4 . 
           [0020]      FIG. 6  is an example graph of stage 1 open-loop gain and open-loop phase vs. Frequency (Hz) for the first LDO stage (stage 1) of the LDO voltage regulator shown in  FIG. 4 . 
           [0021]      FIG. 7  is an example graph of stage 2 open-loop gain and open loop phase vs. Frequency (Hz) for the second LDO stage (stage 2) of the LDO voltage regulator shown in  FIG. 4 . 
       
    
    
       [0022]    To facilitate understanding, identical reference numerals have been used where possible to designate identical elements that are common to the figures, except that suffixes may be added, when appropriate, to differentiate such elements. The images in the drawings are simplified for illustrative purposes and are not necessarily depicted to scale. 
         [0023]    The appended drawings illustrate exemplary configurations of the disclosure and, as such, should not be considered as limiting the scope of the disclosure that may admit to other equally effective configurations. Correspondingly, it has been contemplated that features of some configurations may be beneficially incorporated in other configurations without further recitation. 
       DETAILED DESCRIPTION 
       [0024]    The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. 
         [0025]    The wide bandwidth power supply rejection ratio (PSRR) low drop-out (LDO) voltage regulator generates a clean voltage supply for noise-sensitive individual analog circuits, such as phase lock loops (PLLs), voltage controlled oscillators (VCOs), reference current generator for high-speed digital to analog converters (DACs), reference band-gap voltage generator for high-speed analog to digital converters (ADCs), and other wide-bandwidth analog cores. Utilizing individual wide bandwidth PSRR LDO voltage regulators for separate analog circuit blocks in a SoC allows package power-supply bumps to be shared between multiple PLLs and other analog embedded cores; thereby reducing the number of package power supply-bumps required for noise-sensitive analog circuits. 
         [0026]      FIG. 4  is a schematic diagram of a two-stage, wide bandwidth, power supply rejection ratio LDO voltage regulator  300  in accordance with a preferred embodiment. 
         [0027]    LDO voltage regulator  300  functions to decouple the dominant zero from the dominant pole in the supply-to-output transfer function. LDO voltage regulator  300  includes a first stage voltage regulator circuit  301   a  and a second stage voltage regulator circuit  301   b . First stage voltage regulator circuit  301   a  is a wide bandwidth stage and has an output gain that is higher than that of second stage voltage regulator circuit  301   b . Second stage voltage regulator circuit  302   b  is a narrow bandwidth stage. First stage voltage regulator circuit  301   a  and second stage voltage regulator circuit  301   b  include a first-stage error amplifier circuit  302   a  and a second-stage error amplifier circuit  302   b , respectively. The outputs of each of the first-stage error amplifier circuit  302   a  and second-stage error amplifier circuit  302   b  are coupled to the drains of PMOS devices  304  and  305 , respectively. LDO voltage regulator  300  as configured has pole-zero cancellation in the supply-to-output transfer function resulting in a wide-bandwidth PSRR, as shall be explained in greater detail below. 
         [0028]    First stage voltage regulator circuit  301   a  further includes regulator loop  310   a  which is configured to be approximately 10 times wider in frequency bandwidth than that of regulator loop  310   b  in second stage voltage regulator circuit  301   b . Regulator loops  310   a  and  310   b  have little to no effect on settling behavior of the each other. 
         [0029]    Additionally, the supply-to-output transfer function dominant pole of second stage voltage regulator circuit  301   b  and the supply-to-output transfer function dominant zero of first stage voltage regulator circuit  301   a  are placed on top of each other (at the same frequency) to achieve a wide bandwidth PSRR. The supply-to-output transfer function dominant zero of the first stage voltage regulator circuit  301   a  is created by a Miller-compensation capacitor (Cc 1 )  307 . 
         [0030]    First stage voltage regulator circuit  301   a  has a supply voltage VDD that is regulated down to an intermediate voltage VINT. VINT is regulated down to a final voltage VREG at the output of second stage voltage regulator circuit  301   b . Since the intermediate voltage VINT provides a low-impedance source node, the output of the first-stage error amplifier circuit  302   a  in the first stage voltage regulator circuit  301   a  forms the dominant pole in the loop transfer function. 
         [0031]    A low-impedance on node VINT helps place the dominant pole in the loop transfer function at a high frequency and achieve a wide-band design. In the supply-to-output transfer function for the first stage voltage regulator circuit, this is equivalent to pushing the dominant zero, created by the Miller compensation capacitor (Cc 1 )  307 , further out in frequency. Furthermore, the low-impedance node at the intermediate voltage VINT also provides additional PSRR between VDD and VINT. 
         [0032]    In the presently shown embodiment, first stage voltage regulator circuit  301   a  and second stage voltage regulator circuit  301   b  include individual one-stage error amplifier circuits. Second stage voltage regulator circuit  301   b  is designed such that node VREG forms the dominant pole of loop transfer function. In order to ensure regulator loop stability, the second-stage error amplifier circuit  302   b  is designed for a moderate to low gain. 
         [0033]    Each stage voltage regulator circuit  301   a  and  301   b  of the two-stage LDO voltage regulator  300  is implemented using a corresponding error amplifier circuit  302   a  or  302   b  driving a common-source PMOS device  304  or  305 , at the output stage, of the respective error amplifier circuit, as shown in  FIG. 4 . 
         [0034]    PMOS device  304  includes drain D 1 , gate G 1  and source S 1 . PMOS device  305  similarly has a drain D 2 , gate G 2  and source S 2 . PMOS device  305  is further coupled to decoupling capacitor (CL)  312  at the drain D 2  to suppress LDO voltage regulator output noise at higher frequencies and to provide compensation by forming the dominant pole in loop transfer function. Node VREG sits between the drain D 2  and output load  306 . Output load  306  includes decoupling capacitor (CL)  312  which is in parallel with resistive load (RL)  314  and current device (IL)  316 , the latter representing the load current of one or more active analog core circuits (PLL, VCO, DAC, ADC, etc). 
         [0035]    A reference voltage VREF is provided on the inverting terminal  320  of the error amplifier circuit  302   a . The output voltage from the error amplifier circuit  302   a  is denoted as Vout 1 . A feedback loop  310   a  of first stage voltage regulator circuit  301   a  extends from node VINT to the non-inverting input  322  of error amplifier circuit  302   a  with resistor divider circuit  308  composed of R 2  and R 1  to set the loop gain. The positive supply voltage terminal of the error amplifier circuit  302   a  is coupled to the source S 1  of PMOS device  304  with a source voltage VDD. 
         [0036]    A reference voltage VREF is provided on the inverting terminal  324  of the error amplifier circuit  302   b . The source S 2  of PMOS device  305  is coupled to node VINT from first stage voltage regulator circuit  301   a . The output voltage from the error amplifier circuit  302   b  is denoted as Vout 2 . A feedback loop  310   b  of second stage voltage regulator circuit  301   b  extends from node VREG at the drain D 2  of PMOS device  305  to the non-inverting terminal  326  of error amplifier circuit  302   b . The positive supply voltage terminal of the error amplifier circuit  302   b  is coupled to node VINT. The loop gain is set to unity, as node VREG will track the DC voltage present at VREF (VREG=VREF). 
         [0037]    As mentioned previously, first stage voltage regulator circuit  301   a  is a wide bandwidth stage. Assuming a one-stage error amplifier circuit, gain (Ao1) for the output device of first stage  301   a  is defined according to equation (1): 
         [0000]    
       
         
           
             
               
                 
                   
                     Ao 
                      
                     
                         
                     
                      
                     1 
                   
                   := 
                   
                     gmo 
                      
                     
                         
                     
                      
                     
                       1 
                       · 
                       
                         ( 
                         
                           ro 
                            
                           
                               
                           
                            
                           
                             1 
                             · 
                             
                               
                                 1 
                                 
                                   gmo 
                                    
                                   
                                       
                                   
                                    
                                   2 
                                 
                               
                               
                                 
                                   ro 
                                    
                                   
                                       
                                   
                                    
                                   1 
                                 
                                 + 
                                 
                                   1 
                                   
                                     gmo 
                                      
                                     
                                         
                                     
                                      
                                     2 
                                   
                                 
                               
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where gmo1, gmo2, and ro1 are defined as the transconductance of PMOS devices  304  and  305 , and the output impedance of first stage voltage regulator circuit  301   a  respectively. Exemplary values are provided in Table 1 below. 
         [0038]    At the drain D 1  of PMOS device  304  and specifically, node VINT, a non-dominant pole is formed. The transfer function between VDD and the intermediate voltage node VINT has a pole frequency (ωo1) defined as according to equation (2): 
         [0000]    
       
         
           
             
               
                 
                   
                     ω 
                      
                     
                         
                     
                      
                     o 
                      
                     
                         
                     
                      
                     1 
                      
                     
                       ( 
                       
                         
                           ro 
                            
                           
                               
                           
                            
                           1 
                         
                         , 
                         
                           gmo 
                            
                           
                               
                           
                            
                           2 
                         
                         , 
                         
                           Co 
                            
                           
                               
                           
                            
                           1 
                         
                       
                       ) 
                     
                   
                   := 
                   
                     1 
                     
                       
                         ro 
                          
                         
                             
                         
                          
                         
                           1 
                           · 
                           
                             ( 
                             
                               1 
                               
                                 gmo 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                             ) 
                           
                           · 
                           Co 
                         
                          
                         
                             
                         
                          
                         1 
                       
                       
                         
                           ro 
                            
                           
                               
                           
                            
                           1 
                         
                         + 
                         
                           1 
                           
                             gmo 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where Co1, gmo2, and ro1 are defined as the capacitance at VINT node in  FIG. 3 , the transconductance of PMOS devices  305  and the output impedance of first stage voltage regulator circuit  301   a  respectively. Exemplary values are provided in Table 1 below. 
         [0039]    The output node of error amplifier circuit  302   a  forms the dominant pole. The error amplifier circuit  302   a  pole frequency (ωa1) is defined as according to equation (3): 
         [0000]    
       
         
           
             
               
                 
                   
                     ω 
                      
                     
                         
                     
                      
                     a 
                      
                     
                         
                     
                      
                     1 
                      
                     
                       ( 
                       
                         
                           ra 
                            
                           
                               
                           
                            
                           1 
                         
                         , 
                         
                           Ca 
                            
                           
                               
                           
                            
                           1 
                         
                       
                       ) 
                     
                   
                   := 
                   
                     1 
                     
                       ra 
                        
                       
                           
                       
                        
                       
                         1 
                         · 
                         Ca 
                       
                        
                       
                           
                       
                        
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where ra1, and Ca1 are defined as the output impedance of error amplifier circuit  302   a , and the effective output capacitance at error amplifier circuit  302   a , respectively. Exemplary values are provided in Table 1 below. 
         [0040]    The DC supply rejection (Svint_Vdd) at node VINT node is defined according to equation (4): 
         [0000]    
       
         
           
             
               
                 
                   
                     Svint_vdd 
                      
                     
                       ( 
                       
                         
                           gmo 
                            
                           
                               
                           
                            
                           2 
                         
                         , 
                         
                           ro 
                            
                           
                               
                           
                            
                           1 
                         
                       
                       ) 
                     
                   
                   := 
                   
                     
                       1 
                       
                         gmo 
                          
                         
                             
                         
                          
                         2 
                       
                     
                     
                       
                         ro 
                          
                         
                             
                         
                          
                         1 
                       
                       + 
                       
                         ( 
                         
                           1 
                           
                             gmo 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where gmo2 and ro1 are defined as the transconductance of PMOS device  305 , and the output impedance of first stage voltage regulator circuit  301   a , respectively. Exemplary values are provided in Table 1 below. 
         [0041]    The supply to the intermediate voltage VINT node transfer function (Hvint_vdd) is defined according to equation (5): 
         [0000]    
       
         
           
             
               
                 
                   
                     Hvint_vdd 
                      
                     
                       ( 
                       
                         Svint_vdd 
                         , 
                         
                           Aa 
                            
                           
                               
                           
                            
                           1 
                         
                         , 
                         
                           Ao 
                            
                           
                               
                           
                            
                           1 
                         
                         , 
                         
                           ω 
                            
                           
                               
                           
                            
                           a 
                            
                           
                               
                           
                            
                           1 
                         
                         , 
                         
                           ω 
                            
                           
                               
                           
                            
                           o 
                            
                           
                               
                           
                            
                           1 
                         
                         , 
                         s 
                       
                       ) 
                     
                   
                   := 
                   
                     Svint_vdd 
                     * 
                     
                       
                         1 
                         + 
                         
                           s 
                           
                             ω 
                              
                             
                                 
                             
                              
                             a 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                       
                       
                         
                           Aa 
                            
                           
                               
                           
                            
                           1 
                           * 
                           Ao 
                            
                           
                               
                           
                            
                           1 
                         
                         + 
                         
                           
                             ( 
                             
                               1 
                               + 
                               
                                 s 
                                 
                                   wo 
                                    
                                   
                                       
                                   
                                    
                                   1 
                                 
                               
                             
                             ) 
                           
                           * 
                           
                             ( 
                             
                               1 
                               + 
                               
                                 s 
                                 
                                   wa 
                                    
                                   
                                       
                                   
                                    
                                   1 
                                 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where Svint_vdd is defined in equation (4) above; Aa1 is the open-loop amplifier gain of first stage voltage regulator circuit  301   a ; Ao1 is the gain of the first stage output PMOS device  304  calculated in equation (1); ωo1 is the pole frequency of equation (2) in radians/sec; ωa1 is the error amplifier circuit  302   a  pole frequency in radians/sec according to equation (3) above; and s is a variable corresponding to frequency jω in radians/sec. Exemplary values are provided in Table 1 below. 
         [0042]    The open-loop gain function (Holoop1) for first stage voltage regulator circuit  301   a  is defined according to equation (6): 
         [0000]    
       
         
           
             
               
                 
                   
                     Holoop 
                      
                     
                         
                     
                      
                     1 
                      
                     
                       ( 
                       
                         
                           Aa 
                            
                           
                               
                           
                            
                           1 
                         
                         , 
                         
                           Ao 
                            
                           
                               
                           
                            
                           1 
                         
                         , 
                         
                           ω 
                            
                           
                               
                           
                            
                           a 
                            
                           
                               
                           
                            
                           1 
                         
                         , 
                         
                           ω 
                            
                           
                               
                           
                            
                           o 
                            
                           
                               
                           
                            
                           1 
                         
                         , 
                         s 
                       
                       ) 
                     
                   
                   := 
                   
                     
                       Aa 
                        
                       
                           
                       
                        
                       
                         1 
                         · 
                         Ao 
                       
                        
                       
                           
                       
                        
                       1 
                     
                     
                       
                         ( 
                         
                           1 
                           + 
                           
                             s 
                             
                               ω 
                                
                               
                                   
                               
                                
                               o 
                                
                               
                                   
                               
                                
                               1 
                             
                           
                         
                         ) 
                       
                       · 
                       
                         ( 
                         
                           1 
                           + 
                           
                             s 
                             
                               ω 
                                
                               
                                   
                               
                                
                               a 
                                
                               
                                   
                               
                                
                               1 
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where Aa1 is the open-loop amplifier gain of the first stage voltage regulator circuit  301   a ; Ao1 is the loop gain of the first stage voltage regulator circuit  301   a  calculated in equation (1); ωo1 is the pole frequency of equation (2) in radians/sec; ωa1 is the error amplifier circuit  302   a  pole frequency in radians/sec according to equation (3) above; and s is a variable corresponding to frequency jω in radians/sec. Exemplary values are provided in Table 1 below. Similar expressions are defined below for second stage voltage regulator circuit  301   b . Second stage voltage regulator circuit  301   b  is a narrow-band stage. The output gain (Ao2) at PMOS device  305  is defined according to equation (7): 
         [0000]    
       
         
           
             
               
                 
                   
                     Ao 
                      
                     
                         
                     
                      
                     2 
                   
                   := 
                   
                     gmo 
                      
                     
                         
                     
                      
                     
                       2 
                       · 
                       
                         ( 
                         
                           ro 
                            
                           
                               
                           
                            
                           
                             2 
                             · 
                             
                               rload 
                               
                                 
                                   ro 
                                    
                                   
                                       
                                   
                                    
                                   2 
                                 
                                 + 
                                 rload 
                               
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where gmo2, ro2, and rload are defined as the transconductance of PMOS device  305 , the output impedance of second stage voltage regulator circuit  301   b , and the load resistance RL within output load  306 , respectively. Exemplary values are provided in Table 1 below. 
         [0043]    Node VREG forms the dominant pole. The VREG pole frequency (ωo2) is defined below according to equation (8): 
         [0000]    
       
         
           
             
               
                 
                   
                     ω 
                      
                     
                         
                     
                      
                     o 
                      
                     
                         
                     
                      
                     2 
                      
                     
                       ( 
                       
                         
                           
                             
                               
                                 ro 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                               , 
                               - 
                             
                           
                         
                         
                           
                             
                               
                                 ro 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                               , 
                               rload 
                             
                           
                         
                         
                           
                             Cd 
                           
                         
                       
                       ) 
                     
                   
                   := 
                   
                     1 
                     
                       
                         ro 
                          
                         
                             
                         
                          
                         
                           2 
                           · 
                           rload 
                           · 
                           Cd 
                         
                       
                       
                         
                           ro 
                            
                           
                               
                           
                            
                           2 
                         
                         + 
                         rload 
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where ro2, rload, and CL are defined as the output impedance of second stage voltage regulator circuit  301   b , the load resistance RL, and CL within output load  306  respectively. Exemplary values are provided in Table 1 below. 
         [0044]    The second-stage error amplifier circuit  302   b  pole forms the non-dominant pole. The non-dominate pole frequency (ωa2) is defined below according to equation (9): 
         [0000]    
       
         
           
             
               
                 
                   
                     ω 
                      
                     
                         
                     
                      
                     a 
                      
                     
                         
                     
                      
                     2 
                      
                     
                       ( 
                       
                         
                           ra 
                            
                           
                               
                           
                            
                           2 
                         
                         , 
                         
                           Ca 
                            
                           
                               
                           
                            
                           2 
                         
                       
                       ) 
                     
                   
                   := 
                   
                     1 
                     
                       ra 
                        
                       
                           
                       
                        
                       
                         2 
                         · 
                         Ca 
                       
                        
                       
                           
                       
                        
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where ra2 and Ca2 are the resistance and capacitance at the output of the second stage error amplifier circuit  302   b , respectively. Exemplary values are provided in Table 1 below. 
         [0045]    DC rejection Svreg_vdd from VDD to the VREG node is defined according to equation (10): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       Svreg_vdd 
                        
                       
                         ( 
                         
                           rload 
                           , 
                           
                             ro 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                         ) 
                       
                     
                     := 
                     
                       rload 
                       
                         rload 
                         + 
                         
                           ro 
                            
                           
                               
                           
                            
                           2 
                         
                       
                     
                   
                    
                   
                       
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where ro2 and rload are defined as the output impedance of second stage voltage regulator circuit  301   b  and the load resistance RL within output load  306 , respectively. Exemplary values are provided in Table 1 below. 
         [0046]    The AC transfer function from VINT to the VREG node (Hvreg_vint) is defined according to equation (11): 
         [0000]    
       
         
           
             
               
                 
                   
                     Hvreg_vint 
                      
                     
                       ( 
                       
                         Svreg_vint 
                         , 
                         
                           Aa 
                            
                           
                               
                           
                            
                           2 
                         
                         , 
                         
                           Ao 
                            
                           
                               
                           
                            
                           2 
                         
                         , 
                         
                           ω 
                            
                           
                               
                           
                            
                           a 
                            
                           
                               
                           
                            
                           2 
                         
                         , 
                         
                           ω 
                            
                           
                               
                           
                            
                           o 
                            
                           
                               
                           
                            
                           2 
                         
                         , 
                         s 
                       
                       ) 
                     
                   
                   := 
                   
                     Sveg_vint 
                     * 
                     
                       
                         1 
                         + 
                         
                           s 
                           
                             ω 
                              
                             
                                 
                             
                              
                             a 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                       
                       
                         
                           Aa 
                            
                           
                               
                           
                            
                           2 
                           * 
                           Ao 
                            
                           
                               
                           
                            
                           2 
                         
                         + 
                         
                           
                             ( 
                             
                               1 
                               + 
                               
                                 s 
                                 
                                   wo 
                                    
                                   
                                       
                                   
                                    
                                   2 
                                 
                               
                             
                             ) 
                           
                           * 
                           
                             ( 
                             
                               1 
                               + 
                               
                                 s 
                                 
                                   wa 
                                    
                                   
                                       
                                   
                                    
                                   2 
                                 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where Svreg_vint is the DC rejection according to equation (10) above; Aa2 is the open-loop amplifier gain of second stage voltage regulator circuit  301   b ; Ao2 is the loop gain of second stage voltage regulator circuit  301   b  calculated in equation (7); ωo2 is the pole frequency of equation (8) in radians/sec; ωa2 is the error amplifier circuit  302   b  pole frequency in radians/sec according to equation (9) above; and s is a variable corresponding to frequency jω in radians/sec. Exemplary values are provided in Table 1 below. 
         [0047]    Open-loop gain function of second stage voltage regulator circuit  301   b  is defined below according to equation (12) 
         [0000]    
       
         
           
             
               
                 
                   
                     Holoop 
                      
                     
                         
                     
                      
                     2 
                      
                     
                       ( 
                       
                         
                           Aa 
                            
                           
                               
                           
                            
                           2 
                         
                         , 
                         
                           Ao 
                            
                           
                               
                           
                            
                           2 
                         
                         , 
                         
                           ω 
                            
                           
                               
                           
                            
                           a 
                            
                           
                               
                           
                            
                           2 
                         
                         , 
                         
                           ω 
                            
                           
                               
                           
                            
                           o 
                            
                           
                               
                           
                            
                           2 
                         
                         , 
                         s 
                       
                       ) 
                     
                   
                   := 
                   
                     
                       Aa 
                        
                       
                           
                       
                        
                       
                         2 
                         · 
                         Ao 
                       
                        
                       
                           
                       
                        
                       2 
                     
                     
                       
                         ( 
                         
                           1 
                           + 
                           
                             s 
                             
                               ω 
                                
                               
                                   
                               
                                
                               o 
                                
                               
                                   
                               
                                
                               2 
                             
                           
                         
                         ) 
                       
                       · 
                       
                         ( 
                         
                           1 
                           + 
                           
                             s 
                             
                               ω 
                                
                               
                                   
                               
                                
                               a 
                                
                               
                                   
                               
                                
                               2 
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where Aa2 is the open-loop amplifier gain of second stage voltage regulator circuit  301   b ; Ao2 is the gain of PMOS device  305  in second stage voltage regulator circuit  301   b  calculated in equation (7); ωo2 is the pole frequency of equation (8) in radians/sec; ωa2 is the error amplifier circuit  302   b  pole frequency in radians/sec according to equation (9) above; and s is a variable corresponding to frequency jω in radians/sec. Exemplary values are provided in Table 1 below. 
         [0048]    The AC transfer function from VDD to the VREG node (Hvreg_vdd) is defined according to equation (13): 
         [0000]        H vreg_vdd:= Hv  int vdd· H vreg —   v  int   (13) 
         [0000]    where Hvint_vdd is the AC transfer function from VDD to node VINT according to equation (5) above and Hvreg vint is the AC transfer function from VINT to node VREG according to equation (11) above. Exemplary values are provided in Table 1 below. 
         [0049]    Example small-signal parameters for error amplifier circuits  302   a  and  302   b  as well as PMOS devices  304  and  305  are defined below. First-stage voltage regulator circuit  301   a  is a wide bandwidth loop with a dominant pole at the error amplifier circuit  302   a  output and a non-dominant pole at the output (drain D 1 ) of PMOS device  304 . Other values are possible depending on the integrated circuit process selected (affecting error amplifier parameters), PMOS device size (transconductance, voltage drop, and drain capacitance), in addition to the load capacitance (CL) and load resistance changes. 
         [0000]    
       
         
               
             
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Example Device Parameters for FIG. 4 
               
             
          
           
               
                   
                 Component 
                 Value 
               
               
                   
                   
               
               
                   
                 Aa1 
                 10 
               
               
                   
                 R2/R1 
                 1.4/1.1 = 1.27 
               
               
                   
                 (VDD = 1.8 V, VINT = 1.4 V, &amp; VREF = 1.1 V) 
               
               
                   
                 Aa2 
                 2 
               
               
                   
                 ra1 
                 10 kohm 
               
               
                   
                 ra2 
                 5 kohm 
               
               
                   
                 ro1, ro2 
                 1 kohm 
               
               
                   
                 gmol, gmo2 
                 10 mA/V 
               
               
                   
                 Co1 
                 1 pf 
               
               
                   
                 Ca1, Ca2 
                 0.5 pF 
               
               
                   
                 CL 
                 80 pF 
               
               
                   
                 rload (RL) 
                 2 kohm 
               
               
                   
                   
               
             
          
         
       
     
         [0050]      FIG. 5  is an example graph of a supply rejection for the transfer functions from VDD to VINT (Hvint_vdd), VINT to VREG (Hvreg_vint) and VDD to VREG (Hvreg_vdd) vs. Frequency (Hz). In  FIG. 5 , the graph of the transfer function 20*LOG10(VINT/VDD) (transfer function from VDD to VINT) is represented as a solid line. The graph of the transfer function 20*LOG10(VREG/VINT) (transfer function from VINT to VREG) is represented as a dotted line. The graph of the transfer function 20*LOG10(VREG/VDD) (transfer function from VDD to VREG) is represented as a dashed line. The VDD to VREG transfer function is from the input of first stage voltage regulator circuit  301   a  to the final output of second stage voltage regulator circuit  301   b  vs. Frequency (Hz). 
         [0051]      FIG. 6  is an example graph of a first stage voltage regulator circuit  301   a  open-loop gain and open-loop phase vs. Frequency (Hz). The graph of the loop-gain is shown as a solid line and there is an arrow pointing to the appropriate vertical dB axis. The graph of the phase in degrees is shown as a dotted line and there is an arrow pointing to the appropriate vertical degrees axis. 
         [0052]      FIG. 7  is an example graph of a second stage voltage regulator circuit  301   b  open-loop gain and open-loop phase vs. Frequency (Hz). The graph of the loop-gain is shown as a solid line and there is an arrow pointing to the appropriate vertical dB axis. The graph of the phase in degrees is shown as a dotted line and there is an arrow pointing to the appropriate vertical degrees axis. 
         [0053]    The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.