Abstract:
A device for the electric scanning of luminous images. It includes a matrix of N lines and M columns of photosensitive points. A system incorporating a line memory of M points receives in parallel the electric charges supplied by the M points of the same line parasitic charge are removed by diodes. The system insures the injection of the same predetermined quantity of charges between each of the photosensitive points and the output of the device. An output shift register receives in parallel the charges supplied by the line memory and supplies in series a picture scanning electric signal. This device is particularly intended for use in a television camera.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to the electrical scanning of luminous images in successive lines forming frames, using a charge transfer device incorporating a line memory. 
     Various solid state devices scan an image and supply a television camera with a video electrical signal. They differ in the way in which the photosensitive zone is formed and in the system for reading and removing the charges produced by the image. 
     Charge transfer devices perform these, as described, for example, by SEQUIN and TOMPSETT, in &#34;Charge Transfer Devices&#34;, pp. 152 to 169. In &#34;frame transfer&#34; or &#34;interline structure&#34; organisations the light radiation is received on charge transfer registers. The charge transfer then takes place over large areas, which is a disadvantage, since it is difficult to obtain high efficiency levels for such large areas. CID&#39;s (charge injection devices), do not have these disadvantages, but generally require reinjection of the charges into the semiconductor substrate, resulting in noise and difficulties in connecting with the capacitance values during and after reading. 
     There is also the question of compatibility between the time necessary for light integration and for charge transfer when the latter solution is adopted e.g. with the sweep time of the television screen. A 625 line standard, these times are generally about 52 μs for the display time of a line and 12 μs for the line return time. 
     In order to meet these different requirements, the Applicant Company has proposed a so-called &#34;line transfer&#34; structure, described in U.S. Pat. No. 4,430,672. This structure has a matrix of N lines×M photosensitive zones or points onto which an image to be scanned is projected and converted into electric charges called signal charges; a memory of M points, called the line memory, for successively receiving the signal charges stored by each line; a device for removing the parasitic charges associated with the line memory; and a CCD-type (charge coupled device) shift register receiving in parallel the content of the line memory and supplying in series the image scanning electric signal. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention relates to a picture scanning device of the line transfer type, as described above, in which improvements have been made to insure the storage of successive lines and the removal of parasitic charges, in order to improve the processing of small signals and reduce noise. 
     The device according to the invention has many of elementary photosensitive zones, called points, formed on the same semiconductor substrate in accordance with N lines and M columns, which are isolated from one another and form a matrix in which are created electrical charges, called signal charges, as a function of the illumination received; a charge transfer system with M columns incorporating a memory of M points, called the line memory, formed in the same semiconductor substrate and receiving in parallel the signal charges supplied by the M points of the same line; the line memory including a first grid (G 1 ), placed on the path of the charges and receiving a constant potential (V 1 ), which ensures the decoupling of this grid from the upstream part of the device; a parasitic charge removal device incorporating a many diodes and draining the parasitic charges from each of the columns, which insures the injection of the same predefined quantity of charges into each of the points of the line memory; and an analog shift register receiving in parallel the charges supplied by the line memory and supplying in series a picture scanning electric signal. 
     The invention also relates to a television camera incorporating such a picture scanning device. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention is described in greater detail hereinafter relative to non-limitative embodiments and the attached drawings, which show: 
     FIG. 1 is a block diagram of the general organisation of a line transfer structure. 
     FIG. 2 a plan view of a first embodiment of the device according to the invention. 
     FIGS. 3 (a to h) a sectional view of the device of FIG. 2, illustrating the potentials at different times. 
     FIGS. 4 (a to f) signals which can be applied to the device of FIG. 2. 
     FIG. 5 a plan view of a second embodiment of the device according to the invention. 
     FIGS. 6 (a to h) a sectional view of the device of FIG. 5 illustrating the potentials at different times. 
     FIGS. 7 (a to f) signals which can be applied to the device of FIG. 5. 
     FIG. 8 a plan view of a third embodiment of the device according to the invention. 
     FIGS. 9 (a to i) a sectional view of the device of FIG. 8 illustrating the potentials at different times. 
     FIGS. 10 (a to d) signals which can be applied to the device of FIG. 8. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the various drawings, the same references designate the same elements. 
     FIG. 1 shows the general organisation of a line transfer structure, as described in U.S. Pat. No. 4,430,672. This structure includes a photosensitive zone 1, a line memory 2 and an analog output shift register 3. 
     The photosensitive zone 1 receives the luminous image to be scanned and converts it into electrical charges, called signal charges. The term &#34;luminous image&#34;, relates not only to the detection of visible wavelengths, but also the surrounding wavelengths, particularly in the infrared. The photosensitive zone has many elementary zones 15, which are also called points, arranged in N lines, designated L 1 , L 2  . . . L N  and M columns, designated C 1 , C 2  . . . C M  and forming a matrix. The photosensitive points of the same line are interconnected and connected to a control device 14, which enables successive addressing of the lines. This device has e.g. a MOS-type shift register. The photosensitive points 15 of the same column are connected to the same connection, subsequently called the column connection towards line memory 2. 
     Thus, in parallel, line memory 2 receives the signal charges produced at each of the photosensitive points 15 of the same line and then transfers them in parallel to register 3. A device for restoring the level of the column connections (RAN connection in the drawing) and a device for eliminating parasitic charges (not shown in FIG. 1) are also associated with line memory 2. 
     Register 3 is an analog shift register supplying the information received in parallel in the series mode. This information constitutes the optical image scanning video signal received in photosensitive zone 1. The register is preferably of the charge transfer or CCD type. 
     The coordination of the different picture integration operations in photosensitive zone 1, the transfer of lines into line memory 2 and then the transfer of signals into register 3 for the different lines are effected in the following manner. 
     The integration of the image is permanently carried out over the entire photosensitive matrix 1, except for the line addressed by register 14. During the line return time, the content of line memory 2 is transferred into shift register 3, and the input of the line memory is then closed. During the following line time, the content of register 3 is removed in series and the connection between line memory 2 and register 3 is interrupted. During this time, in a first phase there is a level restoring of the reader of points 15 (RAN connection), connected to line memory 2; and in a second phase one of the lines L of zone 1 is transferred to line memory 2, with the selection (or addressing) of a line being insured by register 14. 
     The following stage corresponds to the line return time during which the content of line memory 2 is discharged into register 3, the latter having been entirely scanned during the preceding stage. 
     According to another embodiment, the selection of a line, its transfer into the line memory and then into the shift register takes place entirely during the line return time, the line time being reserved for the level restoring of the reader, which improves as it becomes longer, and for the series removal from the shift register. 
     FIG. 2 shows a plane view of a first embodiment of the device according to the invention. The connections coming from the M column C of the photosensitive matrix (C i-1 , C i , C i+1 ), each lead to a receiving diode D 2 , of the signal charges Q si  coming from the matrix. It is produced, for example, by doping a semiconductor substrate, which is advantageously the same as that on which the photosensitive matrix 1 is formed. Thus, the device has M charge transfer columns, delimited by insulating barriers 42, corresponding respectively to the M column connections of the photosensitive matrix. 
     The diodes D are aligned and are adjacent on the underside to electrode or grid G 1  in strip form, which forms a screen for the charges between diodes D 2  and the remainder of the device shown in FIG. 2, which prevents parasitic charges from being transmitted on column connection C. In charge transfer devices it is particularly important to provide protection against parasitic charges, whose amplitude can vary from one point to another of the circuit as a function of the geometrical variations of the elements, and which limit the dynamics of the signal. To this end, grid G 1  is connected to a constant potential V 1 . 
     Following the screen grid G 1 , there is a grid G 2  in the form of a strip parallel to G 1  and raised to a second potential V 2 , this has the function of fixing the potential of the column connections. 
     There is then a grid G 4 , whose function is to store the charges, and is in strip form having e.g. rectangular notches 24 between two columns and every other column. In at least part of each of the notches 24, there is a diode D 5  having the function of removing the parasitic charges. The diodes D 5  are connected to a periodic potential V D5 . 
     It may be seen on FIG. 3 that grid G 2  is surrounded by two coplanar grids G 1  and G 4 . So the width of grid G 2  is defined in a single photogravure operation by the distance between grids G 1  and G 4 . A better homogeneity is thus obtained on the width of grid G 2  which can greatly be reduced. 
     The parasitics due to a variable penetration of diodes D 2  under the grid G 2  for the different photosensitive points are eliminated. This variable penetration produces variable transfer times for the charge signal of each diode D 2  towards the memory; moreover, it increases the rapidity of the charge signal transfer from D 1  and D 2  to the memory, because of the small width of G 2 . 
     The device also has a grid G 5  in the form of a strip covering storage grid G 4  with an insulating layer level with notches 24, so as to be adjacent to above diodes D 5 . Grid G 5  receives a periodic potential V 5  and makes it possible to control the access of the charges to diodes D 5 . 
     Parallel to grid G 5  and slightly covering the lower part of diodes D 5  there is a grid G 7  to which is applied a periodic potential V 7  making it possible to control the access to shift register 3. 
     The insulating barriers 42 are interrupted level with the notches 24 or are terminated, if there is no notch, by an extension, e.g. in the form of a triangle 43. Diodes D 5  are surrounded by a U-shaped insulating barrier 44 in such a way that diode D 5  remains accessible to charges coming from the diodes D 2  of each of the columns. In this way, two channels per column are defined: a first channel CL 1  limited by an insulating barrier 42, its extension 43 and a U-shaped branch 44 on the outside; and a second channel CL 2  limited by the inside of the same U-shaped branch 44 and the second insulating barrier 42 limiting the column in question. 
     Register 3 is a C.C.D. register with two phases φ 1  and φ 2 . It has two series of storage electrodes 31, 32 and two series of transfer electrodes 33, 34, all having a substantially rectangular shape and positioned perpendicular to grids G 1  to G 7 . Grids 31 are connected to the periodic potential φ 1  and grids 32 to the periodic potential φ 2 . Grids 33 and 34 are respectively placed between the grid pairs 32, 31 and 31, 32 in the charge transfer direction on an extra thickness of insulant and are respectively connected to potentials φ 1  and φ 2 . Moreover, the electrodes of register 3 are positioned in such a way that electrodes 31 originate on insulating barriers 43 or 44, electrodes 32 being located in the extension of channel CL 1 . The registers 3 is bounded at the bottom by a horizontal insulating barrier 44, in the same way as the device is bounded at the top, also by an horizontal insulating barrier 41. 
     In this embodiment, as in the following embodiments, the various insulating barriers described can be constructed in a known manner, e.g. by overdoping a substrate having the same type of conductivity as the latter, or a localized extra-thickness of the insulating layer (generally oxide) covering the substrate. The latter solution is possibly accompanied by an overdoping of the substrate formed beneath the extra-thick insulation. The various electrodes can also be formed in known manner using e.g. metal or polycrystalline silicon. Finally, to prevent the formation of interference charges, each diode and part of the adjacent grids is covered with a layer which is opaque to light beams, such as an aluminium layer. 
     FIG. 3a is a sectional view of the device of FIG. 2 and diagrams 3b to 3h illustrate the surface potential in the semiconductor substrate at different times, the surface potential being represented on these and the following diagrams as increasing in the downward direction. To facilitate the understanding of the operation of the device, the diagram of FIG. 3a is a section made at different locations. 
     To the left of an axis XX is shown a photosensitive point of matrix 1. For example, it is constituted by a grid G L  formed by an electrode with a photodetecting MOS capacitance raised to a periodic potential V GL  and which slightly overlaps the following grid G E . This is a screen for the charges, separating the actual photosensitive zone from the column connection and is raised to a constant potential V GE . The screen grid G E  is followed by reading diode D L  formed in the substrate, which constitutes the starting point for the column connection c i . In a variant not shown, the photosensitive point has a second image detection zone, whose frequency sensitivity is complementary to the MOS capacitance realised e.g. by a photodiode. 
     To the right of axis XX is shown a section in the device of FIG. 2 along a line AA passing through diode D 2 , grid G 1 , grid G 4  and the second channel CL 2 . Grid G 4  is followed by grid G 5 , which also slightly overlaps it, G 5  is followed by diode D 5 . It can be seen that grid G 2  slightly overlaps the surrounding grids G 1  and G 4 . It is also possible to see the column connections c i  connecting diodes D L  and D 2 . 
     Following diode D 5 , it is possible to see a section in the device of FIG. 2 along a line BB along the first channel CL 1  and separated in FIG. 3a from what precedes it by an axis YY. The section of the first channel starts level with grid G 4  and continues up to an electrode 32 of register 3, G 4  and 32 being separated by grid G 7 , which slightly overlaps them. It should be noted that, both in this and the following embodiments, the operation of the device is compatible with a &#34;volume&#34; charge transfer into output register 3. As is known, the charge transfer in the volume of the semiconductor substrate is faster than the surface transfer and its efficiency is better. Volume transfer differs from surface transfer mainly through the higher potentials applied and a doping of that part of the semiconductor substrate where there is a transfer having a conductivity type which is opposite to that of the remainder of the substrate. 
     The drawings show a volume transfer operation and consequently a &#34;hatched&#34; doped area, designated T.V., extending beneath the electrodes of register 3 up to half of grid G 7 . 
     These different elements are preferably formed on the same semiconductor substrate 21, covered with a insulating layer which is not shown. The various electrodes are separated, in the case where they overlap, by an insulating layer, which, for reasons of clarity, also is not shown. 
     The various diagrams (a to e) of FIG. 4 show the evolution in time of control signals applied to the device of FIG. 3. 
     FIG. 4a represents the potential V GL , which is at a constant high level (V H ), except during a time interval T 4  to T 7  corresponding to the time for the transfer of the charges accumulated in a considered photosensitive point to the line memory and then to register 3 of FIG. 2 and which essentially corresponds to the line return time. 
     FIG. 4d represents potential V 4 , which is at a constant high level (V H ), except between times T 3  and T 5  surrounding time T 4 . 
     FIG. 4c represents the potential V 5 , which is at a high level (V H ) up to time T 0 , when it passes to an intermediate level (V I ) and remains there up to a time T 2 , T 0  and T 2  being before time T 3 . As from time T 2 , V 5  remains at a low level V B  up to a time T 8 , which is after time T 7 , when it again rises to the high level V H . 
     FIG. 4d represents potential V D5 , which is at a constant high level (V H ) , except between time T 0  and a time T 1  between T 0  and T 2  during which it is at a low level (V B ). 
     FIG. 4e represents potential V 7 , which is at a constant low level, except between time T 6 , which precedes time T 7 , and T 7 , during which it is at a high level (V H ). 
     In FIG. 3b, at a time t o  between time T 0  and T 1 , diode D 5  is at low level permitting the injection of charges beneath grid G 4 . This injection is limited by a constant potential V 2  applied to grid G 2 , which implies that the low level of V D5  exceeds potential V 2 . Thus, it would appear that grid G 2  fixes the potential level of the column connections c i . Moreover, to the left of line XX, a signal charge quantity Q si  is present beneath grid G L  (hatched area). 
     The diagram of FIG. 3c shows the potentials at a time t 1  between T 1  and T 2 . At this time, potential V D5  is at high level and therefore a charge quantity Q 0  is isolated beneath grid G 4  (hatched area) by potentials V 2  and V 5  respectively applied to grids G 2  and G 5 . This charge quantity Q 0  is dependent on the potential V 1 , which is then applied beneath grid G 5 , potential V 2  being assumed lower than V I . 
     At a time t 2  between T 3  and T 4 , voltages V 4  and V 5  are returned to low level, which has the effect of transferring the charge quantity Q 0  to diodes D 2  and, via connections c i , to diodes D L . This is represented by an arrow 51 on the part of diagram 3d between lines XX and YY. 
     At a subsequent time t 3 , between T 4  and T 5 , the potential applied to grid G L  of the MOS capacitance of the photosensitive zone is brought to a low level, which has the effect of transferring charge quantity Q si  to diodes D L  (arrow 52 in the left-hand part of FIG. 3d). 
     Diagram 3e represents the situation at a time t 4 , between times T 5  and T 6 . During this time, the potential applied to grid G 4  is raised to a high level, which makes it possible to transfer (arrow 53) charges Q 0  +Q si  beneath grid G 4  in two channels, which is illustrated to the right and left of axis YY. 
     Diagram 3f represents the situation at a time t 5  between T 6  and T 7  during which the potentials of channel CL 2  are unchanged, while the potential of grid G 7  placed on channel CL 1  rises enabling the transfer (arrow 54) of the charges Q 0  +Q si  present beneath grid G 4  to shift register 3, materialised by one of its electrodes 32. Thus, the known charge quantity Q 0  is effectively transferred into register 3 at the same time as signal charge Q si . 
     Generally, it is possible to avoid the transfer of the charge Q 0  into register 3, in which case only signal charge Q si  is transferred. This makes it possible to eliminate the so-called spatial noise on Q 0  from one column to the next, the noise being due to variations in the changes caused by variations in the oxide thickness covering the substrate, variations in the threshold voltages, etc. This can be brought about by raising grid G 7  to an intermediate potential V 1 , represented in diagram 4f and whose amplitude is between V B  and V H  during times T 6  to T 7 . The value V I  of this intermediate potential is advantageously equal to the intermediate potential applied to grid G 5  between times T 0  and T 2 . In this way, an operation described by diagram 3g is obtained, where it is possible to see that the potential applied to grid G 7  is such that only the signal charge Q si  (arrow 55) can be transferred from grid G 4  to electrode 32 above grid G 7 , charge Q 0  remaining beneath grid G 4 . It should be noted that in this variant, the phase corresponding to diagram 3b can be eliminated. This stage is an injection stage of Q 0  into the device, which is no longer necessary because this charge is no longer eliminated. 
     It is essential that the charge signal transfer Q si  from diodes D 2  under grid G 2  then under grid G 4  includes the addition of a charge quantity Q o , the capacity of the diodes D 2  being quite important. But the transfer of the charge signal Q si  to the reading register doesn&#39;t necessitate the addition of the charge quantity Q O , the capacity of the grid G 4  being small, of the same dimension as the capacity of the register. 
     At a time t 6 , following time T 8  and at a random point during the line time, the potential applied to grid G 5  being raised to the high level V H , there is an elimination of any parasitic charge (Q B ) from a column connection, by channel CL 2  to diode D 5 . These parasitic charges result e.g. from overilluminated points of the photosensitive matrix. 
     On referring to the variant described by diagrams 4f and 3g, it is necessary that at time t 6 , the potential applied to grid G 5  is equal to the intermediate level V 1  and not to V H  in order to ensure that only charge Q 0  is beneath grid G 4  and to eliminate possible parasitic charges by D 5 . 
     In this latter variant, the residual spatial noise can only be due to variations of the threshold, doping or insulation thickness between grids G 7  and G 5 , which is minimal in practice, bearing in mind the geometrical proximity of these grids. 
     Thus, this structure permits the injection of a predetermined quantity of Q 0 , first beneath the storage grid G 4  and then onto diodes D L  and D 2  establishing the connection between photosensitive matrix and the line memory, in order to improve the transfer of signal charges Q si . This quantity of charges Q 0  is consequently injected by using the structure of the line memory and the parasitic charge elimination device, so that no auxiliary device is required. 
     Moreover, in this embodiment, each parasitic charge removal diode D 5  is common to both columns making it possible either to increase the storage capacity of the line memory (more extensive grid G 4 ) or to permit a smaller horizontal spacing and consequently a reduced overall size of the device. 
     FIG. 5 is a plan view of a second embodiment of the invention, where the generation of the charge quantity Q 0  is completely free from spatial noise. 
     In FIG. 5, it is possible to see diodes D 2 , grid G 1 , grid G 2  and G 4 , which in this case has a notch 25 level with each of the columns and, as before, each of these notches contains a diode D 5 . Grids G 5  and G 7  are arranged parallel to the other grids on either side of diodes D 5 . Perpendicular to these, it is possible to see the electrodes 31 to 34 of register 3. 
     Once again, there are vertical insulating barriers 42 between the columns which extend up to electrodes 34 of register 3. Moreover, each of the columns is vertically subdivided by an insulating barrier 45, defining to its left a first channel CL 1  extending from grid G 4  to an electrode 32, and to its right a second channel CL 2  containing diode D 5 , which then extends between barriers 45 and 42, and finally a third channel CL 3  extending from electrode 31 of register 3 to diode D 5 , i.e. opposite to channel CL 2 . 
     To the left of axis ZZ, FIG. 6a shows a section along a closed line CC formed as from diode D 5  around the insulating barrier 45 of FIG. 5; to the right of axis ZZ there is a section along a line DD from grid G 4  to diode D 2 , these two sections being joined to make it easier to explain the operation of the device of FIG. 5. 
     In succession starting from the left, FIG. 6 shows channel CL 2  represented by diode D 5 , grid G 5  slightly overlapping the following grid G 4 , the latter being common to channel CL 2  and CL 1 , then channel CL 1  represented by grid 32 separated from grid G 4  by grid G 7 , which slightly overlaps both of them. Grid 31 is separated from grid 32 by grid 33, which slightly overlaps them and which forms the separation between channels CL 1  and CL 3 , then channel CL 3  constituted by grid G 7  and diode D 5 . To the right of line ZZ are successively provided grid G 4 , grid G 1  separated from G 4  by grid G 2  which slightly overlaps them, followed by diode D 2 , which receives column connections c i . 
     As before, there is a doping zone extending from grid G 7  to electrodes 31, 32 and 33 of register 3 corresponding to the volume transfer type of operation of the register. 
     The various diagrams (a to f) of FIG. 7 show the evolution in time of the various control signals applied to the device of FIG. 5. These control signals are periodic potentials, whose amplitude varies between a low level V B  for all the diagrams and a high level V H  for all the diagrams, but these different potentials are not necessarily equal. 
     Diagram 7a represents potential V 5  which is at a high level, except from a time T 2  and up to a time T 8 , the time between T 2  and T 8  being essentially that of the line return. 
     Diagram 7b represents potential V D5  which is at a high level, except between times T 1  and T 3  surrounding time T 2 , when it is at a low level. 
     Diagram 7c represents potential V 7  which is at a low level up to a time T 4  after time T 3  at which it passes to a high level, up to a subsequent time T 5  when it again passes to a low level, up to a subsequent time T 6  when it again passes to a high level, up to T 8  when it again passes to a low level. 
     Diagram 7d represents potential φ 2 , which is a square wave signal of cycle or period T up to a time T 0  preceding time T 1  at which it passes to a high level up to time T 5 . It then passes to a low level, which it maintains up to a time T 6 , when it passes to a high level up to a time T 8 , and then it again becomes a square wave signal of the same period as before. 
     Diagram 7e shows potential φ 1 , which is complementary to potential φ 2 . 
     Diagram 7f represents potential V 4  which is at a high level up to time T 5 , at which it passes to a low level up to time T 7  between T 6  and T 8 , when it again passes to a high level. 
     FIG. 6b shows the surface potential in the semiconductor level with FIG. 6a at a time t 0  between T 1  and T 2 . For reasons of clarity in this and the following diagrams, each of them shows the surface of the semiconductor substrate 22. At this time t 0 , potential V D5  applied to diode D 5  is at a low level, but potential V 5  applied to grid G 5  is at a high level. As a result, it is possible for the charges to invade the area located beneath grid G 4 , but this invasion (hatched area) is limited by grid G 7  raised to potential V 7 , which is at low level. 
     FIG. 6c shows the surface potential at a time t 1  between T 2  and T 3 . The only change from the preceding drawing is the passage of potential V 5  to low level, which isolates a charge quantity Q&#39; 0  beneath grid G 4 . 
     Diagram 6d represents the surface potential at a time t 2  between times T 4  and T 5 . The difference from the previous diagram is that potential V 7  applied to grid G 7  passes to a high level, which has the effect of subdividing the charge quantity Q&#39; 0  beneath electrode G 4  into a quantity Q 0  remaining beneath this grid as a function of the potential level V H  of V 7 , and defined by the surface potential beneath G 7  out of the doped zone T.V., and a residual charge quantity Q r , which is transferred beneath grid 32 to which is applied potential φ 2 , which at this instant is at high level. 
     Diagram 6e shows the surface potential at time t 3  between times T 5  and T 6 . During this period, potential φ 2  is brought to low level, which has the effect of transferring charge Q r  beneath electrode 31, potential φ 1  then being at high level. Moreover, as the potential V 4  of grid G 4  is at low level, the charge quantity Q 0  is transferred to diode D 2  and to column connections c i , which is shown to the right of axis ZZ, reference again being made to the fact that potentials V 1  and V 2  are constant and higher than the low level of V 4 . The potential V 7  applied to grid G 7  is at a low level during this time, so that access to register 3 is impossible. 
     Moreover, at time t 3  the presence of charges Q si  are shown on the column connection c i . The transfer of Q si  from a photosensitive point of column c i  takes place in the manner described relative to FIG. 3d. This transfer can take place at any time before t 5  (FIG. 6g) but it is preferable for Q 0  to be transferred before or at the same time as Q si  on column connection c i . 
     Diagram 6f represents the surface potential at a time t 4  between times T 6  and T 7 . During this period, the passage of potential V 7  to a high level makes it possible to remove the charges Q r , previously beneath electrode 31, to diode D 5  via channel 3. During this same period, φ 2  returns to a high level and φ 1  to low level. 
     Diagram 6g represents the surface potential at a time t 5  between T 7  and T 8 . During this period, the potential applied to grid G 4  returns to high level, so that the charge quantity Q 0  +Q si  present on connection c i  (right-hand part of the drawing) is transferred beneath grid G 4  and then partly beneath electrode 32, while charge quantity Q 0  is held back by the potential barrier beneath grid G 7  in the same way as at time t 2 . In this way, only Q si  is transferred beneath electrode 32 of output register 3. 
     Diagram 6h represents the surface potential at a time t 6  following time T 8 , potentials φ 1  and φ 2  then being respectively at high level and at low level. During this time, potential V 4  applied to grid G 4  is at high level, which makes it possible to eliminate all the parasitic charges Q p  present on column connection c i , the charges being transferred over grid G 2  to grid G 4  and from grid G 4  to the parasitic charge elimination diode D 5 , grid G 5  then being raised to a high level potential V 5 . Throughout this period, charge Q si  is transferred beneath the following electrode 31 of output register 3. 
     This second embodiment described in FIGS. 5 and 7 consequently permits the generation of charge Q 0  at the line memory in a completely spatial noise-free manner, because it is determined by the potential applied to grid G 7  and then stopped by the same grid during the transfer of the signal charges Q si  to output register 3. The residual charges Q r  or parasitic charges Q p  are eliminated before any scan by diode D 5  by means of channel CL 2  or channel CL 3  and in this case via register 3. 
     FIG. 8 shows a third embodiment of the device according to the invention, which also makes it possible to eliminate the spatial noise in the generation of charge Q 0  by means of a two-stage line memory structure. Here the two functions previously fulfilled by storage grid G 4  are realised by two separate grids. 
     FIG. 8 shows a structure identical to that of FIG. 2, one diode D 2  per column receiving the column connection c i-1 , c i  and c i+1 , followed by grid G 1 , which is itself followed by grid G 2 , respectively raised to constant potentials V 1  and V 2 . Grid G 4  is now replaced by a first grid G 41  in the form of a strip and raised to a periodic potential V 41 . Its function is to maintain charge Q 0 , whose value is determined by a grid G3 which follows G 41  and raised to a periodic potential V 3 . Grid G 3  is followed by a second grid such as G 4 , designated in this case G 42  and having notches 26 identical to the notches 24 of FIG. 2 in which are formed diodes D 5 . It has the function of branching charges between register 3 and the parasitic charge elimination diodes D 5 . G 42  is raised to a periodic potential, V 41  and the diodes D 5  are raised to a constant potential V D5 . 
     The columns are separated from one another, as before, by an insulation barrier 42 and diodes D 5 , surrounded by U-shaped insulation barriers 44 arranged in such a way that one diode D 5  is common to two columns and the flow of charges transferred into a column is divided into two channels CL 1  and CL 2  at grid G 5 , which is adjacent to diodes D 5 , as before. The device also has grid G 7 , raised to potential V 7 , and output register 3, constructed in the same way as hitherto. Insulation barriers 42 either terminate before diodes D 5  or beneath grid G 7  by an e.g. square extension 46, in such a way that the charges transferred into channel CL 1  can only be transferred towards electrode 32. 
     FIG. 9a represents a sectional view of the device of FIG. 8 along with a line EE extending from diode D 2  to diode D 5 , then from diode D 5  to an electrode 32 of the reading register. 
     Thus, in FIG. 9a and starting from the left, it is possible to see diode D 2  receiving column connection c i , grid G 1 , grid G 41 , grid G 2  between grids G 1  and G 41  and slightly overlapping the latter, grid G 42 , grid G 3  placed between grids G 41  and G 42  and slightly overlapping them, grid G 5  slightly overlapping the latter and diode D 5 , then grid G 5  and grid G 42 , and then grid G 7  and grid 32 of the reading register 3. 
     The various diagrams (a to d) of FIG. 10 represent the control signals which can be used in the device of FIG. 8. These control signals are periodic potentials, whose amplitude varies between a high level and a low level, designated V H  and V B  respectively for all the diagrams. However, these different potentials are not necessarily equal to one another or equal to the potentials of the previous drawings. 
     Diagram 10a shows potentials V 41  and V 42  applied to grids G 41  and G 42 . It is at low level, except at times t 1 , t 2 , t 3  and t 6 , t 7 , t 8 , when it is at high level. 
     Diagram 10b represents potentials V 3  and V 2  applied to grids G 3  and G 2  ; it is at high level during times t 2  and t 7 . 
     Diagram 10c represents potential V 5  applied to grid G 5 . It is at low level V B , except during times t 1 , t 2 , t 3  and t 4 . 
     Diagram 10d represents potential V 7  applied to grid G 7 . It is at low level except during times t 6 , t 7 , t 8  and t 9 , when it is at high level. 
     Diagrams 9b to 9i represent the potential on the surface of the semiconductor substrate, at different times and increasing in the downward direction. 
     FIG. 9b represents the surface potential during time t 1 . Grid G 2  is at a low level V B  and isolates the photosensitive zone from the remainder of the device. On the columns, there is the training charge quantity Q o  and a charge quantity Q B  due to a possible overlighting. 
     FIG. 9c represents the surface potential during time t 2 . Grids G 2  and G 3  are at a high level. The charge quantity Q o  +Q B  is transferred in the line memory. Charge quantity Q o  fullfils the potential well beneath grid G 41  and charge quantity Q B  is transferred under grids G 42 . 
     FIG. 9d represents the surface potential during time t 3 . Grid G 2  is at a low level. The photosensitive zone is isolated from the remainder of the device. Grid G 3  is at a low level separating the grids G 41  and G 42 . 
     FIG. 9e represents the surface potential during time t 4 . Grids G 41  and G 42  are at a low level. Charge quantity Q o  is transferred from columns and charge quantity Q B  is evacuated by drain D 5 . 
     FIG. 9f represents the surface potential during times t 5  and t 6 . 
     At time t 5 , grid G 5  is at a low level and isolates the line memory from the drain D 5 . Moreover a clock signal, not shown on the figure, produces the arrival of the charge quantity Q S  on the column connections. There is then on the columns connections Q o  +Q S . 
     At time t 6 , grid G 7  and grids G 41  and G 42  are at a high level. 
     FIG. 9g represents the surface potential during time t 7 . Grid G 3  is at a high level and there is communication between grids G 41  and G 42 . Grid G 2  is at a high level and there is transfer from charge quantity Q o  +Q S  from the column connections in the line memory. The charge quantity Q o  is blocked under grid G 41  and the signal charge quantity Q S  is transferred under grid G 42 . 
     FIG. 9h represents the surface potential during time t 8 . Grid G 2  is at a low level; so is grid G 3 . 
     FIG. 9i represents the surface potential during time t 9  : Grids G 41  and G 42  are at a low level and there is transfer of the signal charge quantity Q S  in the reading register 32 and transfer of the charge quantity Q o  on the columns. The transfer of Q o  on the columns at time t 9  explains that at time t 1  the charge quantity Q o  +Q B  is on the columns. 
     In the embodiments of FIGS. 5 and 8, the generation of the charge quantity Q o  in the line memory is quite independent from the spatial noise because this charge is created then stopped by the same grid receiving the same potential. For FIGS. 6d and g, it is the grid G 7  at the potential V 7 . For FIG. 9d and g, it is the grid G 3  at potential V 3 . 
     In the embodiment of FIG. 8, the transfer from the columns to the line memory of the signal charge quantity Q S  and of the charge quantity Q B  constituted by overlighting charges is made by adding the training charge Q o , independent from the spatial noise, to these charge quantities. 
     In the embodiments of FIGS. 2 and 5, it would be also possible to add the charge quantity Q o  to the charge quantities Q S  and Q B  when there is transfer of the charges from the columns to the line memory. 
     In the operating mode of FIG. 8, the grid G 2  is no longer at a constant potential as it was in the operating modes of FIGS. 2 and 5. 
     Where G 2  is at a constant potential, after signal charges Q S  have been transferred from D 2  to G 4 , the surface potential at diode D 2  is equal to that of grid G 2 . New signal charges will arrive under D 2  only at the time of the next line return. During the time interval between these two arrivals of charges, there is a leakage current which, although the MOS transistor formed by diode D 2 , grid G 2  and the potential well under G 3  is blocked, evacuates some charges from D 2  to G 4 . This leakage current is known as subthreshold current. The surface potential at D 2  increases slightly from ΔV compared with that of G 2 . When the signal charges of the following line are transferred on the column, they must first fill the potential &#34;pocket&#34; ΔV before charge Q si  can be transferred to G 4 . A quantity of charges Q p  =C 1  ·ΔV, where C 1  is the column capacity, is blocked on the column and only the difference Q si  -Q P  is transferred, so there is a diminution of the useful signal. Sometimes, there is even Q P  &gt;Q si . In the operating mode of FIG. 8, the leakage current is delated by applying to grid G 2  not a continuous voltage V 2 , but a periodic signal V 2  having periodically a high and a low level. 
     So, during the line time, the signal V 2  is at a low level. There is a large potential barrier between the potential at D 2  and the potential under grid G 2 . The leakage current is then negligible. 
     During the line return time when charges have to be transferred from the columns to G 4 , the signal V 2  is at a high level. The potential barrier becomes zero, so the potential at D 2  equals that of grid G 2 . 
     This pulse on G 2  occurs each time there is transfer from the columns to the line memory, of reading signal charges or of overlighting charges Q B  at the end of the line time, for example. 
     The amplitude of the pulse on G 2  is approximately 1V to efficaciously reduce the leakage current, and it is approximately 10 to 15 Volts for the different control signals referred to hereinbefore. 
     Grid G 1  is quite important in this mode of operating. It deletes the parasitic coupling between G 2  and D 2  which would have maintained the potential barrier when there is a pulse on G 2 . The diode D 2 , whithout the grid G 1 , whould follow the potential of G 2  because of its coupling capacity with G 2 . 
     In the embodiments of FIGS. 2 and 5, it is also possible to maintain the grid G 1  at a constant potential and to apply to grid G 2  a periodic signal so as to maintain it at a low level, except when there is transfer of charges to the line memory. 
     The above description has been given relative to a non-limitative embodiment. Thus, the relative positioning of grids G 1 , G 5  and G 7  of diodes D 2  and D 5 , as well as their dimensions, have no particular function and instead only devolve from the technological construction procedure. In the same way, the shape of the insulation barriers 43 and 46 are of a random nature, which also applies with respect to the shape of notches 24 and 26.