Abstract:
The present invention relates to an apparatus for detecting a signal received from a channel signal and for transforming this signal into a binary code sequence. More particularly the invention refers to a signal processing apparatus, which can perform a maximum likelihood detection of the reproduced data from an optical disk.  
     It is an object of the invention to propose a maximum likelihood detector having reduced complexity.  
     According to the invention a method to detect a signal (EBS) received from a channel signal (HF), comprises the steps of digitizing the signal received from the channel, equalizing the digitized signal (A k ), generating branch metrics (b_mp, b_pm) from the equalized signal (B k ), determining the minimum (b_ml) of the generated branch metrics (b_mp, b_pm), determining a merge (m−, m+, m0) from the minimum (b_ml), and generating a bitstream signal from the succession of merges (m−, m+, m0).

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to an apparatus for detecting a signal received from a channel signal and for transforming this signal into a binary code sequence. More particularly the invention refers to a signal processing apparatus, which can perform a maximum likelihood detection of the reproduced data from an optical disk.  
         BACKGROUND OF THE INVENTION  
         [0002]    The idealized recording channel has a low pass nature, just as the Duobinary (1+D) partial response (PR 1  class) and therefore, for detecting the data read from an optical disk the (1+D) partial response signaling technique can be used.  
           [0003]    A method and the respective hardware architecture for implementing a known method requires many computations, particularly for branch metrics calculations and for difference path metric calculations, that requires the additional time and leads to decrease the performance of the detector.  
           [0004]    In a known maximum likelihood detector, also referred to herein as ML detector or as MLD apparatus, has been implemented a method, which is also called “Viterbi Detection”. This Method is based on the assumption, that the recording channel has a precoder. This method is extremely sensitive to the input signal amplitude variations, because a large number of threshold conditions, for example comparers are used.  
         SUMMARY OF THE INVENTION  
         [0005]    An object of the invention is to develop a maximum likelihood detector with minimal hardware complexity, maximum computational speed, which maximum likelihood detector is not sensitive to variations in the input signal amplitude. In order to reach this goal the following principles are used.  
           [0006]    The so-called maximum likelihood detection boils down to finding the admissible sequence x=x 0 , x 1 , . . . , x n  that is closest to the detector input sequence B=B 0 , B 1 , . . . , B n  in the Euclidean sense. The Euclidean distance λ between detector input B and admissible sequence x is  
             λ   =       ∑     k   =   0     n            (       B   k     -     x   k       )     2               (   1   )                               
 
           [0007]    This is a sum of so-called branch metrics b k  wherein  
             b   k ( B   k   −x   k ) 2   (2)  
           [0008]    All metrics b k  may be computed as soon as the k th  detector input Bk becomes available. The detector must determine the path through the trellis for which the sum of all branch metrics is smallest. In FIG. 5 there is shown an example of a state transition diagram for two states 0 and 1, which are also indicated as p and m, respectively. The different transitions are indicated by b_pp, b_mp, b_pm, and b_mp, wherein the first index indicates the actual state while the second index indicates the previous state.  
           [0009]    For a two state (1+D) maximum likelihood detection the branch metrics are:  
           [0010]    1. The data transition path from 1 to 0 in the state transition diagram  
             b   —   mp= ( B   k   +Am ) 2 ;  (3)  
           [0011]    2. The data transition path from 0 to 1 in the state transition diagram  
             b   —   pm= ( B   k   −Am ) 2 ;  (4)  
           [0012]    3. The data transition path from 0 to 0 in the state transition diagram  
             b   —   mm= ( B   k +2* Am ) 2 ;  (5)  
           [0013]    4. The data transition path from 1 to 1 in the state transition diagram  
             b   —   pp= ( B   k −2* Am ) 2 ;  (6)  
           [0014]    wherein the MLD has as input the output of the (1+D) equalizer,  
             B   k   =A   k   +A   k−1 ,  (7)  
           [0015]    where  
             A   k   =Y   k   −Am ,  (8)  
           [0016]    and wherein Y k  is a sampled value of an HF signal read from a recording medium after analog-to-digital conversion and Am is a reference value, especially a current value of a so-called slicer.  
           [0017]    [0017]FIG. 1 shows the signals Y k , A k , B k  respectively. The time axis kT is subdivided in equidistant parts, each vertical line indicating a k-th point in time at which a sample, indicated by a dot, is taken from the continuous signal. The four branch metrics b_mp, b_pm, b_mm, b_pp are calculated at the same time in each decision point (k). One can see that the branch metrics values are the absolute values, which are always positive. This is caused by the square operation. The absolute values undergo the operation  
             b   —   ml=MIN ( b   —   mp, b   —   pm, b   —   pp, b   —   mm ),  (9)  
           [0018]    where b_ml is the value that corresponds to the at most smallest branch metric. b_ml is thus the branch metric having maximum likelihood of corresponding to the correct transition. Later the value b_ml is used for a merge determination operation.  
           [0019]    It is an object of the invention to propose a maximum likelihood detector having reduced complexity.  
           [0020]    In order to increase the performance of the maximum likelihood detector, also referred to herein as ML detector or as MLD, without loss of the detecting ability, and in order to reduce the hardware complexity some modifications are implemented into the branch metrics calculation block and the different path metric calculation block is deleted according to the invention.  
           [0021]    According to the invention the above-mentioned computations are simplified as follows:  
           [0022]    First the square performance operation is rejected. This has the advantage to reduce complexity of the maximum likelihood detector. In the example described above four multiplication operations are avoided.  
           [0023]    Second the branch metrics for non-changing state are not determined. This does not influence the maximum likelihood detection in a negative way as nearly no such transitions happen because the HF signal shape is not flat. This property makes possible to reject the branch metric computations (5) and (6).  
           [0024]    Further, the branch metrics are calculated by using some properties of the arithmetic system of hardware. This procedure will be described in more detail below.  
           [0025]    Minimum branch metrics are determined by computing a sum of absolute values of two branch metrics and using the sign of this sum for determining the minimum branch metrics. This sign is e.g. indicated by the most significant bit in the two&#39;s complement binary notation or in any other way, depending on the kind of notation used, known to the skilled person. Advantage of this feature is that summation operation and determination of the sign of a variable are operations which are easy to implement and quickly to perform.  
           [0026]    Preferably, the absolute value to be input to the adding operation is generated differently for different branch metrics. For a first branch metric the most significant bit is checked. If it is set to “low” level, the remaining less significant bits, which correspond to the absolute level, are also taken as absolute level for the summation. If the most significant bit is set to “high” level, then the inverted less sigificant bits are taken as absolute value for the summation. For a second branch metric, the selection is done in the opposite way. In this case the absolute value is taken unchanged if the most significant bit is set to “high” level, and its inverted value is taken else. This is true for the two&#39;s complement binary notation, however, similar evaluation of the sign, which here corresponds to the most significant bit, and transformation of the absolute value can easily be performed by a skilled person using a different notation than the two&#39;s complement notation.  
           [0027]    According to the invention, the type of merge is detected from two successive minima of the generated branch metrics. This allows to determine the type of merge even if not all possible types of branch metrics are generated. The types of merges in case of two states are: Change of state from “high” to “low”; change of state from “low” to “high”; and no change of state. In case that branch metrics are generated only for “change of state” then a change of state is determined only if the type of two successive minimum branch metrics changes. No change of state is determined if successive minimum branch metrics are identical.  
           [0028]    The device according to the invention comprises the elements as indicated in the independent device claim. An advantage of this device is its relatively easy construction without need of complex or space consuming elements. The equalizer preferably is a (1+D) linear equalizer, combining two successive input values, thus reducing noise in a simple way.  
           [0029]    The branch metrics calculator preferably comprises an adder to calculate a branch metric from an equalized signal and an average value or a negated average value. An advantage of using an adder for generating a branch metric is that this is a simple, cost effective element. Although the calculated result might not be as exact as according to known methods, it has proven to be sufficiently exact to receive reliable working results.  
           [0030]    The merge determining unit comprises an adder, two multiplexers and two negators for determining a minimum absolute value of two input signals. This has the advantage that a small number of relatively easy elements is sufficient for determining the minimum absolute value of two branch metrics.  
           [0031]    Further features and advantages of the invention will become apparent from the description of preferred embodiments using the figures. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0032]    FIG  1   a )- e ) show examplary signals which occur at different steps of the method according to the invention,  
         [0033]    [0033]FIG. 2 shows a maximum likelihood detector according to the invention,  
         [0034]    [0034]FIG. 3 shows an equalizer used in a maximum likelihood detector according to the invention,  
         [0035]    [0035]FIG. 4 shows a merge detection unit of a maximum likelihood detector according to the invention,  
         [0036]    [0036]FIG. 5 shows an exemplary state transition diagram. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0037]    The content of FIG. 1 a )- c ) is already described above. According to the invention, only two branch metrics are to calculate: The data transition path from 1 to 0 in the state transition diagram  
           b   —   mp=B   k   +Am;   (10)  
         [0038]    and the data transition path from 0 to 1 in the state transition diagram  
           b   —   pm=B   k   −Am;   (11)  
         [0039]    From these values the smallest branch metric b_ml is to be determined according to  
           b   —   ml=MIN ( b   —   mp, b   —   pm ),  (12)  
         [0040]    where b_mp and b_pm are the absolute values.  
         [0041]    In each decision point (k) are, at same time, to calculate the values of equations (10) and (11) and then to calculate the value of equation (12). The information from equation (12) is sufficient to determine the merges m−, m+ or m 0 , wherein m 0  indicates a transition with no change of state, m− indicates a transition from “low” to “high” and m+ indicates a transition from “high” to “low”. The merges are determined under the following conditions, see also FIG. 1 d ):  
         [0042]    1) if b_ml(k+1)=b_pm and b_ml(k)=b_mp then the merge is of type m−;  
         [0043]    2) if b_ml(k+1)=b_pm and b_ml(k)=b_pm then the merge is of type m 0 ;  
         [0044]    3) if b_ml(k+1)=b_mp and b_ml(k)=b_pm then the merge is of type m+;  
         [0045]    4) if b_ml(k+1)=b_mp and b_ml(k)=b_mp then the merge is or type m 0 ;  
         [0046]    The sequence of merges is detected and transformed into a sequence of bits. FIG. 1 e ) shows the estimated bits sequence output from the path metrics memory.  
         [0047]    The drawing in FIG. 2 illustrates a maximum likelihood detector apparatus according to the invention. The ML Detector consists of six main blocks, a slicer  1 , a subtractor  2 , a (1+D) Linear equalizer  3 , a branch metrics calculation unit  4 , a merge determining unit  5  and a merge detecting unit  6 .  
         [0048]    For the description of an embodiment of the invention it is assumed that the two&#39;s complement fixed point arithmetic is used in the ML detector apparatus. Other notations would make necessary slight modifications lying within the knowledge of the skilled person.  
         [0049]    A high-frequent data signal HF is read from an optical recording medium in a known way. The high-frequent data signal HF is fed to an analog-to-digital converter  7 . The analog-to-digital converter  7  samples its input signal at a given rate and outputs a sampled data signal Y. Each sample of data signal Y is provided with an index k, indicating that it is the k-th sample taken. All other values used in this description and being provided with an index k refer to the k-th sample. Each sampled data signal Y k  is fed to slicer  1  as well as to subtractor  2 .  
         [0050]    The slicer  2  calculates the average value Am of the sampled data signal Y k . At the same time the slicer  2  calculates the negated value −Am. The average value Am is fed to the subtractor  2 . Both, the average value Am and the negated average value −Am are fed to the branch metrics calculation unit  4 . The subtractor  2  calculates the value A k , with A k =Y k −Am.  
         [0051]    The linear equalizer  3  generates the detector input values Bk from two successive values A k , A (k−1) . The branch metrics calculation unit  4  calculates from detector input value B k  the branch metrics b_mp and b_pm, using average value Am and negated average value −Am.  
         [0052]    The merge determining unit  5  generates, from the branch metrics b_mp, b_pm, merge determination signals BR 0 , BR 1 , which are fed to a merge detection unit  6 . Merge detection unit  6  comprises a control block  8  and a path metrics memory  9 , its output signal is an estimated bit sequence EBS.  
         [0053]    [0053]FIG. 3 shows the (1+D) linear equalizer  3 , the branch metrics calculation unit  4  and the merge determining unit  5  in more detail. The equalizer  3  handles the data according to expression:  
           B   k   =A   k   +A   (k−1) ,  k =1, 2, . . .  
         [0054]    It is therefore provided with two registers REG 1 , REG 2  and an adder ADD 1 . The value A k  is fed to the first register REG 1 , the output value A k  of which is fed to adder ADD 1  as well as to the second register REG 2 . The output of second register REG 2 , corresponding to the previous value A (k−1) , is also fed to the adder ADD 1 , the output signal of which is the detector input value B k .  
         [0055]    The Branch metrics calculation unit  4  comprises two adders ADD 2 , ADD 3  for calculating the branch metrics b_mp and b_pm according to b_mp=B k +Am; b_pm=B k −Am from detector input value B k , average value Am and negated average value −Am.  
         [0056]    The merge determining unit  6  judges the merges of the sampled data Y k . The values of the branch metrics b_mp and b_pm are used to compute the merges m 0 , m+, m− of the sampling data, see FIG. 1 d.    
         [0057]    In FIG. 3 the merge determining unit is illustrated. This block consist of two circuits for the performance of the negation operation, indicated by X(−1) and named negators  10 ,  11 , an adder ADD 4 , two multiplexers MUX 1 , MUX 2  and two registers REG 3  and REG 4 . Two circuits for the negation operation, negators  10 ,  11 , two multiplexers MUX 1 , MUX 2  and an adder ADD 4  are used to determine which of branch metrics b_mp and b_pm is the one having minimum absolute value.  
         [0058]    To perform this determination, the sign of each branch metric b_mp, b_pm is taken as control signal for multiplexers MUX 1 , MUX 2 . In the two&#39;s complement notation as used in this description, the sign is represented by the most significant bit msb_mp, msb_pm. The sign, represented by the most significant bit msb_mp, msb_pm, is taken from the branch metrics b_mp and b_pm at separators  12 ,  13 . Branch metric b_mp is fed to input  2  of multiplexer MUX 1 , its negated value, after having passed negator  10 , is fed to input  1  of multiplexer MUX 1 . Branch metric b_mp is fed to input  2  of multiplexer MUX 1 , while its negated value, after having passed negator  10 , is fed to input  1  of multiplexer MUX 1 . Branch metric b_pm, is directly fed to input  1  of multiplexer MUX 2 , while its negated value is fed to input  2 .  
         [0059]    If the branch metric b_mp value is negative, i.e. if its most significant bit msb_mp equals 1, then the negated b_mp value goes through input  1  of multiplexer MUX 1  to input  1  of adder ADD 4 . If the branch metric b_mp value is positive, i.e. if msb_mp equals 0, then b_mp value goes through the input  2  of multiplexer MUX 1  to the input  1  of adder ADD 4 .  
         [0060]    If the value of branch metric b_pm is negative, i.e. if msb_pm=1, then b_mp value goes through input  1  of multiplexer MUX 2  to the input  2  of adder ADD 4 . If the value of branch metric b_pm is positive, i.e. if msb_pm=0, then the negated b_pm value goes through the input  2  of multiplexer MUX 2  to the input  2  of adder ADD 4 .  
         [0061]    The minimum absolute value is defined after the addition in adder ADD 4  by the following: The sign of the sum, which is the output of adder  4 , is evaluated. Here, it is the most significant bit msb s of the sum.  
         [0062]    If msb_s is equal to 1 then branch metric b_mp has the minimum absolute value.  
         [0063]    If msb_s is equal to 0 then the branch metric b_pm has minimum absolute value.  
         [0064]    The sign of the sum, here msb_s, is stored into a register REG 3 .  
         [0065]    The output of register REG 3  is output from merge determining unit  5  as merge determination signal BR 1  as well as fed to a register REG 4 , the output of which is output as merge determination signal BR 0 .  
         [0066]    The merge determination signals BR 1  and BR 0  determine the merges, which are output to the merge detecting unit  6 . The merges are determined under the following conditions:  
         [0067]    If BR 1 =1 and BRO=0, that means if minimum branch metric b_mp is preceded by minimum branch metric b_pm, see FIG. 1 d , then a positive merge m+ has occurred.  
         [0068]    If BR 1 =0 and BR 0 =1, that means if minimum branch metric b_pm is preceded by minimum branch metric b_mp, see FIG. 1 d , then a negative merge m− has occurred.  
         [0069]    If (BR 1 =0 and BR 0 =0) or if (Br 1 =1 and Br 0 =1), that means if two successive minimum branch metrics are identical either b_mp, b_mp or b_pm, b_pm, then a merge m 0  without change of state has occurred.  
         [0070]    [0070]FIG. 4 illustrates the merge detecting unit  6 . The merge detecting unit  6  consist of a control block  8  and cross-coupled shift registers SH_SP, SH_SM, which constitute the path metrics memory  9 . The control block  6  controls the path metrics memory  9 .  
         [0071]    Depending on the merges m 0 , m+, m−, indicated by merge determination signals BR 0 , BR 1 , the control block generates the following signals (FIG. 4):  
         [0072]    LD_SP: load parallel the SH_SP register from the SH_SM register;  
         [0073]    LD_SM: load parallel the SH_SM register from the SH_SP register;  
         [0074]    SHT_SP: shift the contents of the SH_SP register to the right;  
         [0075]    SHT_SM: shift the contents of the SH_SM register to the right;  
         [0076]    SHT_PM: shift the contents of the SH_SM and SH_SP register to the right;  
         [0077]    These registers are controlled as follows: If a merge m 0  occurs, i.e. if merge determination signals BR 0  and BR 1  have equal value, then both registerd SH_SP and SH_SM are shifted at the same time and a “high” value is input to register SH_SP while a “low” value is input to register SH_SM. An according algorithm, using well known operators and conditions, is:  
         [0078]    if(((BR 1 ==0)&amp;&amp;(BR 0 ==0)||( (BR 1 ==1)&amp;&amp;(BR 0 ==1))) { 
         [0079]    for(j=0; j&lt;14; ++j) { 
         [0080]    sh_sp[14−j]=sh_sp[13−j];  
         [0081]    sh_sm[14−j]=sh_sm[13−j];  
         [0082]    } 
         [0083]    sh_sp[0]=0; sh_sm=0;  
         [0084]    } 
         [0085]    In case of a merge m−, i.e. if a “low” level BR 0 =0 is followed by a “high” level BR 1 =1, the register SH_SP is loaded from register SH_SM, while register SH_SM is shifted and both registers have “low” level as input. An according algorithm is:  
         [0086]    if((BR 1 ==1)&amp;&amp;(BR 0 ==0)) { 
         [0087]    for(j=0; j&lt;14; ++j) sh_sp[j+1]=sh_sm[j];  
         [0088]    for(j=0; j&lt;14; ++j) sh_sm[14−j]=sh_sm[13−j];  
         [0089]    sh_sp[0]=0; sh_sm[0]=0;  
         [0090]    } 
         [0091]    In case of a merge m+, i.e. transition from “high” to “low”, register SH_SM is loaded from register SH_SP and register SH_SP is shifted. Both registers have, in this case, high level input. An according algorithm is:  
         [0092]    if((BR 1 ==0)&amp;&amp;(BR 0 ==1)) { 
         [0093]    for(j=0; j&lt;14; ++j) sh_sm[j+1]=sh_sp[j];  
         [0094]    for(j=0; j&lt;14; ++j) sh_sp[14−j]=sh_sp[13−j];  
         [0095]    sh_sp[0]=1; sh_sm[0]=1;  
         [0096]    } 
         [0097]    The estimated bits sequence EBS is output from last element SH_SP [14] of register SH_SP.  
         [0098]    The maximum likelihood detector according to the invention is not sensitive to variations of the input signal amplitude. It is independent of threshold conditions. It has a simple construction and simple working as only two branch metrics are computed in the matrix likelihood detector. A square operation, hitherto used for the calculation of the absolute values, is not performed by the computation of branch metrics according to the invention. According to the invention calculation of the absolute values is performed by using some properties like adders, multiplexers etc. of the arithmetic system of the hardware. The above mentioned positive properties lead to increase the ML detector speed and to decrease the hardware complexity without the loss of the ML detection power. The general idea of the invention can be applied also to audio or video CD and to DVD applications in an acquisition part to improve the detection of data read from a recording medium, especially an optical recording medium.