Abstract:
In a semiconductor memory device having a shared sense amplifier configuration, a control circuit outputting a-bit line isolation signal latches a block selection signal in accordance with a change in a trigger signal. With this configuration, when the same block is selected, no change is caused in the bit line isolation signal. Consequently, charge/discharge current is reduced, and power consumption is reduced. Since a specific bit in a refresh counter is not used, unlike the conventional technique, the design changes little even in the case of changing the configuration of an array.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to semiconductor memory devices, and specifically to such a semiconductor memory device as a DRAM (Dynamic Random-Access Memory) performing a precharge operation.  
           [0003]    2. Description of the Background Art  
           [0004]    A conventional semiconductor memory device disclosed in Japanese Patent Laying-Open No. 2000-207883 has an additional external control signal line dedicated to the precharge operation. Then, regardless of commands, input of an external control signal from the external control signal line forces the precharge operation to be performed and thus the memory cycle time can be shortened.  
           [0005]    The conventional semiconductor memory device, however, has a problem that a new external signal line as well as external control are required in order to effect the forced precharge operation by the input of the external control signal from the dedicated external control signal line.  
         SUMMARY OF THE INVENTION  
         [0006]    One object of the present invention is to provide a semiconductor memory device achieving a higher speed of the memory operation without the need for a new external signal line and external control.  
           [0007]    A semiconductor memory device according to the present invention includes: a plurality of memory blocks each including a plurality of memory cells arranged in rows and columns, a plurality of word lines respectively arranged correspondingly to a plurality of rows of the memory cells, and a plurality of pairs of bit lines respectively arranged correspondingly to a plurality of columns of the memory cells; a plurality of sense amplifier bands provided correspondingly to each of the memory blocks to sense and amplify data read from the memory cells; a plurality of pairs of read data lines extended commonly from the sense amplifier bands; and a logic circuit having input terminals connected to one pair of read data lines respectively of the pairs of read data lines. The logic circuit provides a self-precharge signal when an increased potential difference is generated between the pair of read data lines connected respectively to the input terminals.  
           [0008]    According to the present invention, the memory operation can be increased in speed without the need for a new external signal line and external control.  
           [0009]    The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    [0010]FIG. 1 is a schematic block diagram showing an entire configuration of a semiconductor memory device  1 A according to a first embodiment of the present invention.  
         [0011]    [0011]FIG. 2 is a schematic block diagram showing a modification of the entire configuration of semiconductor memory device  1 A according to the first embodiment of the present invention.  
         [0012]    [0012]FIG. 3 is a circuit diagram partially showing a circuit configuration of a sense amplifier band  4 . 2 A according to the first embodiment of the present invention.  
         [0013]    [0013]FIG. 4 is a circuit diagram showing a circuit configuration of a central control circuit  2 A- 1  according to the first embodiment of the present invention.  
         [0014]    [0014]FIG. 5 is an operational waveform chart illustrating a circuit operation of sense amplifier band  4 . 2 A controlled by central control circuit  2 A- 1 .  
         [0015]    [0015]FIG. 6 is a circuit diagram showing a circuit configuration of a central control circuit  2 A- 2  according to the first embodiment of the present invention.  
         [0016]    [0016]FIG. 7 is a circuit diagram showing a circuit configuration of a central control circuit  2 A- 3  according to the first embodiment of the present invention.  
         [0017]    [0017]FIG. 8 is an operational waveform chart illustrating a circuit operation of sense amplifier band  4 . 2 A controlled by central control circuit  2 A- 3 .  
         [0018]    [0018]FIG. 9 is a schematic block diagram showing an entire configuration of a semiconductor memory device  1 B according to a second embodiment of the present invention.  
         [0019]    [0019]FIG. 10 is a circuit diagram partially showing a circuit configuration of a sense amplifier band  4 . 2 B according to the second embodiment of the present invention.  
         [0020]    [0020]FIG. 11 is a circuit diagram showing a circuit configuration of a central control circuit  2 B- 1  according to the second embodiment of the present invention.  
         [0021]    [0021]FIG. 12 is an operational waveform chart illustrating a circuit operation of sense amplifier band  4 . 2 B controlled by central control circuit  2 B- 1 .  
         [0022]    [0022]FIG. 13 is a circuit diagram showing a circuit configuration of a central control circuit  2 B- 2  according to the second embodiment of the present invention.  
         [0023]    [0023]FIG. 14 is a circuit diagram showing a circuit configuration of a central control circuit  2 B- 3  according to the second embodiment of the present invention.  
         [0024]    [0024]FIG. 15 is an operational waveform chart illustrating a circuit operation of sense amplifier band  4 . 2 B controlled by central control circuit  2 B- 3 .  
         [0025]    [0025]FIG. 16 is a schematic block diagram showing an entire configuration of a semiconductor memory device  1 C according to a third embodiment of the present invention.  
         [0026]    [0026]FIG. 17 is a schematic block diagram showing an entire configuration of a semiconductor memory device  1 D according to a fourth embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0027]    Embodiments of the present invention are hereinafter described in detail with reference to the drawings. It is noted that the same or corresponding components in the drawings are denoted by the same reference character and description thereof is not repeated.  
       First Embodiment  
       [0028]    A semiconductor memory: device  1 A according to a first embodiment shown in FIG. 1 includes a central control circuit  2 A, a row decoder  3 , sense amplifier bands  4 . 1 A,  4 . 2 A,  4 . 3 A, memory blocks  5 . 1 ,  5 . 2 ,  5 . 3 , an XOR gate  6 , a preamplifier  40 , and a main amplifier  41 .  
         [0029]    Central control circuit  2 A receives control signals extACT, extPRE, extSREF, extREAD indicative of commands, a clock signal extCLK and a row address signal extRA that are externally supplied thereto, to provide internal control signals ACT, RXT, RAL, SELFREF, READ, PAE and address signals XO&lt;1:0&gt;, XN&lt;3:0&gt;, XM&lt;3:0&gt;, XSD&lt;3:0&gt;, RA&lt;7:2&gt;to row decoder  3 . A specific configuration of central control circuit  2 A is detailed hereinlater.  
         [0030]    Row decoder  3  receives these various signals supplied from central control circuit  2 A to perform row-related decoding for sense amplifier bands  4 . 1 A,  4 . 2 A,  4 . 3 A and memory blocks  5 . 1 ,  5 . 2 ,  5 . 3 .  
         [0031]    From sense amplifier bands  4 . 1 A,  4 . 2 A,  4 . 3 A, a pair of read data lines GIOR and /GIOR common to sense amplifier bands  4 .  1 A,  4 . 2 A,  4 . 3 A are extended to connect to the input terminals of XOR gate  6  and preamplifier  40  respectively. Although one pair of read data lines GIOR and /GIOR connected to XOR gate  6  and preamplifier  40  is representatively shown in FIG. 1, a plurality of pairs of read data lines are actually extended from sense amplifier bands  4 . 1 A,  4 . 2 A,  4 . 3 A and one pair of read data lines GIOR and /GIOR of these pairs of read data lines is connected to the input terminals of XOR gate  6  and preamplifier  40  respectively.  
         [0032]    XOR gate  6  outputs a self-precharge signal SELFPRE to central control circuit  2 A when there arises an increased potential difference between paired data lines GIOR and /GIOR. Preamplifier  40  is connected to the pair of data lines GIOR and /GIOR. Preamplifier  40  receives data which is read onto the pair of read data lines GIOR and /GIOR to produce a single-ended output of the data in response to a preamplifier activation signal PAE. Main amplifier  41  buffers the data of the single-ended output from preamplifier  40  to output the data to a data output pin Q.  
         [0033]    [0033]FIG. 2 is a schematic block diagram showing a modification of the entire configuration of semiconductor memory device  1 A according to the first embodiment of the present invention. A semiconductor memory device  1 A- 2  of the first embodiment that is shown in FIG. 2 differs from semiconductor memory device  1 A in FIG. 1 in that XOR gate  6  is replaced by a NAND gate  7 .  
         [0034]    The XOR gate and NAND gate have only one difference therebetween that these gates produce different outputs respectively for an input (0,0). When paired read data lines GIOR and /GIOR are both precharged to a logical high level, i.e., H level, it never occurs in a normal operation that both of the paired read data lines GIOR and /GIOR have a logical low level, i.e., L level. For this reason, NAND gate  7  may be used instead of XOR gate  6  for generating self-precharge signal SELFPRE.  
         [0035]    The NAND gate can generally be formed of a smaller number of transistors as compared with the XOR gate. Then, NAND gate  7  can be employed instead of XOR gate  6  to generate self-precharge signal SELFPRE with a smaller occupying area. Any XOR gate  6  of other embodiments may be replaced by NAND gate  7  as well.  
         [0036]    Description is given below of a specific circuit configuration of a neighboring region, in sense amplifier band  4 . 2 A as a representative of sense amplifier bands  4 . 1 A,  4 . 2 A,  4 . 3 A, of paired read data lines GIOR and /GIOR connected respectively to the input terminals of XOR gate  6 .  
         [0037]    [0037]FIG. 3 is a circuit diagram partially showing a circuit configuration of sense amplifier band  4 . 2 A according to the first embodiment of the present invention.  
         [0038]    As shown in FIG. 3, sense amplifier band  4 . 2 A is adjacent to memory block  5 . 2  including a memory cell  20  and includes a sense amplifier  10 , a P-channel MOS transistor  15 , an N-channel MOS transistor  16 , an isolation gate circuit  17 , a read gate circuit  30 .  
         [0039]    Sense amplifier  10  is connected between paired bit lines BL and /BL and includes P-channel MOS transistors  11 ,  12  connected to a sense amplifier drive line SPL and N-channel MOS transistors  13 ,  14  connected to a sense amplifier drive line SNL.  
         [0040]    Sense amplifier drive line SPL is driven to a power-supply potential VCC by a sense amplifier activation signal /SOP provided to P-channel MOS transistor  15 . Sense amplifier drive line SNL is driven to a ground potential GND by a sense amplifier activation signal SON provided to N-channel MOS transistor  16 .  
         [0041]    Memory cell  20  in memory block  5 . 2  includes an N-channel MOS transistor  21  having its gate connected to a word line WL and its drain connected to bit line /BL and a capacitor having one terminal connected to the source of N-channel MOS transistor  21  and the other terminal fixed at a predetermined potential. This memory cell  20  is shown representatively as one of a plurality of memory cells included in memory block  5 . 2 .  
         [0042]    Isolation gate circuit  17  includes N-channel MOS transistors  18 ,  19  to electrically connect/disconnect circuitry on one side, with respect to the pair of bit lines BL and /BL, including memory block  5 . 2 , and circuitry on the other side including sense amplifier band  4 . 2 A, to/from each other, in response to a bit line isolation signal BLI.  
         [0043]    Read gate circuit  30  is connected between paired bit lines BL and /BL. Read gate circuit  30  includes N-channel MOS transistors  31 ,  32  having respective gates connected to paired bit lines BL and /BL respectively and respective sources both connected to a ground node, and N-channel MOS transistors  33 ,  34  having respective sources connected to respective drains of N-channel MOS transistors  31 ,  32  and respective drains connected to paired read data lines GIOR and /GIOR respectively. N-channel MOS transistors  33 ,  34  are turned on/off in response to activation/inactivation of a column selection line CSLR.  
         [0044]    [0044]FIG. 4 is a circuit diagram showing a circuit configuration of a central control circuit  2 A- 1  according to the first embodiment of the present invention.  
         [0045]    Referring to FIG. 4, central control circuit  2 A- 1  of the first embodiment includes a D flip-flop circuit  51  taking in control signal extACT at a rising edge of clock signal extCLK to output signal ACT, a D flip-flop circuit  52  taking in control signal extPRE at a rising edge of clock signal extCLK, an OR gate  53  receiving an output from D flip-flop circuit  52  and self-precharge signal SELFPRE generated from XOR gate  6  in FIG. 1 or NAND gate  7  in FIG. 2 to output a precharge signal PRE, a latch circuit  54  receiving signals ACT and PRE, and an inverter  57  receiving an output from latch circuit  54  to invert the output and provide a signal intRAS.  
         [0046]    OR gate  53  outputs precharge signal PRE not only at a rising edge of the output from D flip-flop circuit  52  but also at a rising edge of self-precharge signal SELFPRE. Thus, a self-precharge operation can be performed without an externally-supplied precharge command by control signal extPRE.  
         [0047]    Latch circuit  54  includes an OR gate  55  having one input receiving signal ACT and a NAND gate  56  receiving the inverted signal of signal PRE and an output from OR gate  55 . An output from NAND gate  56  is inverted to be provided to the other input of OR gate  55  and to an input of inverter  57 .  
         [0048]    Central control circuit  2 A- 1  further includes a NOR gate  58  receiving signals intRAS and SRAS, a delay circuit  59  receiving and delaying an output from NOR gate  58 , a NAND gate  60  receiving respective outputs from delay circuit  59  and NOR gate  58 , a delay circuit  61  delaying an output from NAND gate  60 , a NAND gate  62  receiving respective outputs from delay circuit  61  and NAND gate  60 , and an inverter  63  receiving and inverting an output from NAND gate  62  to output signal RXT. Signal RXT is a trigger signal indicating an activation timing of the word line.  
         [0049]    Central control circuit  2 A- 1  further includes a delay circuit  64  receiving and delaying the output from NAND gate  62 , a NAND gate  65  receiving respective outputs from delay circuit  64  and NAND gate  62 , a delay circuit  66  receiving and delaying an output from NAND gate  65 , a NAND gate  67  receiving respective outputs from delay circuit  66  and NAND gate  65 , and an inverter  68  receiving and inverting an output from NAND gate  67  to provide signal RAL. Signal RAL is a signal indicating a row-address latch timing.  
         [0050]    Central control circuit  2 A- 1  further includes selectors  71  and  75 . Selector  71  receives externally supplied row address signals extRA&lt;12:8&gt;and extRA&lt;1:0&gt;and a bit corresponding to address QA&lt;12:0&gt;at the time of refresh to output a refresh address when self-refresh signal SELFREF has H level and output an external row address signal when self-refresh signal SELFREF has L level.  
         [0051]    Selector  75  receives externally supplied row address signal extRA&lt;7:2&gt;and a bit corresponding to address QA&lt;12:0&gt;at the time of refresh to output an address for self-refresh when self-refresh signal SELFREF has H level and output an external row address signal when self-refresh signal SELFREF has L level.  
         [0052]    Central control circuit  2 A- 1  further includes a decode circuit  72  decoding the output from selector  71 , an OR gate  73  receiving clock signals extCLK and PHY, a D flip-flop circuit  74  taking in an output from decode circuit  72  at a rising edge of an output from OR gate  73  to output decoded address signals XO&lt;1:0&gt;, XN&lt;3:0’, XM&lt;3:0&gt;, and XSD&lt;3:0&gt;, an OR gate  76  receiving signals extCLK and PHY, and a D flip-flop circuit  77  taking in the output from selector  75  at a rising edge of an output from OR gate  76  to output row address signal RA&lt;7:2&gt;.  
         [0053]    Moreover, central control circuit  2 A- 1  includes a D flip-flop circuit  78  taking in control signal extSREF at a rising edge of clock signal extCLK to output self-refresh signal SELFREF, and a self-refresh signal generation circuit  79  providing signal SRAS which is a row address strobe signal at the time of self-refresh in response to activation of self-refresh signal SELFREF, generating address signal QA&lt;12:0&gt;at the time of refresh and providing clock signal PHY.  
         [0054]    Further, central control circuit  2 A- 1  includes a D flip-flop circuit  81  taking in control signal extREAD at a rising edge of clock signal extCLK to output signal READ, a delay circuit  82  receiving and delaying signal READ, a NAND gate  83  receiving an output from delay circuit  82  and signal READ, a delay circuit  84  receiving and delaying an output from NAND gate  83 , a NAND gate  85  receiving respective outputs from delay circuit  84  and NAND gate  83 , and an inverter  86  receiving and inverting an output from NAND gate  85  to output preamplifier activation signal PAE.  
         [0055]    [0055]FIG. 5 is an operational waveform chart illustrating a circuit operation of sense amplifier band  4 . 2 A controlled by central control circuit  2 A- 1 .  
         [0056]    At time t 1 , ACT command (activate command) is issued and a row address is input.  
         [0057]    Upon reception of the input row address, word line WL is activated at time t 2 . Activation of word line WL causes N-channel MOS transistor  21  in memory cell  20  to turn on thereby causing charges to flow from capacitor  22  to bit line /BL. Consequently, a slight potential difference is generated between paired bit lines BL and /BL that are equalized to VCCa/2 in advance. Here, VCCa represents an amplitude voltage in the memory cell array of the semiconductor memory device.  
         [0058]    Upon the input of the row address, sense amplifier drive lines SPL and SNL that are both equalized to VCCa/2 in advance are driven respectively to power-supply potential VCC and ground potential GND. Accordingly, the slight potential difference between paired bit lines BL and /BL is amplified to a potential difference between power-supply potential VCC and ground potential GND.  
         [0059]    At time t 3 , RD command (read command) is issued and a column address is input. Upon reception of the input column address, read column selection line CSLR is activated at time t 4 .  
         [0060]    Read column selection line CSLR is thus activated to drive paired read data lines GIOR and /GIOR that are precharged in advance to H level (logical high level), to H level and L level respectively according to data read onto paired bit lines BL and /BL.  
         [0061]    The increased potential difference between paired read data lines GIOR and /GIOR causes self-precharge signal SELFPRE to be generated through XOR gate  6  in FIG. 1 or NAND gate  7  in FIG. 2. Upon the generation of self-precharge signal SELFPRE, word line WL is inactivated and, at time t 5 , sense amplifier drive lines SPL and SNL are both equalized to VCCa/2. Then, paired bit lines BL and/BL are both equalized to VCCa/2.  
         [0062]    Further, the input of the column address activates preamplifier activation signal PAE. Upon the activation of preamplifier activation signal PAE, the data output onto paired read data lines GIOR and /GIOR is output through preamplifier  40  and main amplifier  41  to data output pin Q.  
         [0063]    Thus, when RD command is issued and immediately after the increase in potential difference arises between paired read data lines GIOR and /GIOR, a precharge operation is carried out autonomically. For this reason, the semiconductor memory device of the first embodiment eliminates the need for an external precharge command when RD command is issued and readily achieves a higher-speed operation.  
         [0064]    Moreover, the timing of the precharge operation depends on such conditions under which the operating speed is generally changed, as variations in the process, the upper and lower limits of the voltage and high temperature/low temperature for example. Then, the timing is designed here more easily as compared with the case in which the precharge command with its timing fixed by an external command is issued.  
         [0065]    In the discussion above, it is supposed that the self-precharge operation is performed in a read operation only and a precharge command is externally supplied in a write operation. However, the precharge operation can be performed in the write operation as well, by performing the write operation simultaneously with the read operation all the time. Then, in central control circuit  2 A- 1  in FIG. 4, D flip-flop circuit  52  and OR gate  53  may be eliminated and self-precharge signal SELFPRE may directly be supplied to latch circuit  54 . An embodiment in this case is detailed later in connection with a second embodiment.  
         [0066]    [0066]FIG. 6 is a circuit diagram showing a circuit configuration of a central control circuit  2 A- 2  according to the first embodiment of the present invention.  
         [0067]    Central control circuit  2 A- 2  of the first embodiment shown in FIG. 6 differs from central control circuit  2 A- 1  in FIG. 4 in that a delay element  69  is inserted to precede the stage in which self-precharge signal SELFPRE is input to OR gate  53 . Self-precharge signal SELFPRE can thus be delayed by delay element  69  and then input to OR gate  53  so as to improve the operation margin of the semiconductor memory device of the present invention and facilitate adjustment of the timing.  
         [0068]    [0068]FIG. 7 is a circuit diagram showing a circuit configuration of a central control circuit  2 A- 3  according to the first embodiment of the present invention.  
         [0069]    Central control circuit  2 A- 3  of the first embodiment shown in FIG. 7 differs from central control circuit  2 A- 1  in FIG. 4 in that self-precharge signal SELFPRE and its delay signal are input to NAND gate  83  instead of signal READ and its delay signal to generate the preamplifier activation signal PAE in the end.  
         [0070]    [0070]FIG. 8 is an operational waveform chart illustrating a circuit operation of sense amplifier band  4 . 2 A controlled by central control circuit  2 A- 3 .  
         [0071]    The operational waveform chart shown in FIG. 8 differs from the chart in FIG. 5 in that preamplifier activation signal PAE is activated not by the input of the column address but by generation of self-precharge signal SELFPRE.  
         [0072]    Preamplifier activation signal PAE is thus activated upon generation of self-precharge signal SELFPRE, and accordingly the delay time up to activation of preamplifier activation signal PAE is shorter than that when preamplifier activation signal PAE is activated by the input of the column address. Further, as the activation of preamplifier activation signal PAE depends on the increase in potential difference between paired read data lines GIOR and /GIOR, design of the timing is facilitated.  
         [0073]    As discussed above, according to the first embodiment, immediately after a potential difference between paired read data lines GIOR and /GIOR increases when RD commend is issued, the precharge operation is autonomically carried out, which eliminates the need for an externally supplied precharge command when RD commend is issued and achieves a higher-speed operation.  
       Second Embodiment  
       [0074]    A semiconductor memory device  1 B of a second embodiment shown in FIG. 9 includes a central control circuit  2 B and sense amplifier bands  4 . 1 B,  4 . 2 B,  4 . 3 B instead of central control circuit  2 A and sense amplifier bands  4 . 1 A,  4 . 2 A,  4 . 3 A. Specific configurations respectively of central control circuit  2 B and sense amplifier band  4 . 2 B as a representative of sense amplifier bands  4 . 1 B,  4 . 2 B,  4 . 3 B are detailed hereinlater. It is noted that, as described in connection with FIG. 2 of the first embodiment, XOR gate  6  in FIG. 9 may be replaced by NAND gate  7 .  
         [0075]    [0075]FIG. 10 is a circuit diagram partially showing, a circuit configuration of sense amplifier band  4 . 2 B according to the second embodiment of the present invention.  
         [0076]    Sense amplifier band  4 . 2 B of the second embodiment shown in FIG. 10 includes a read gate circuit  30   a  instead of read gate circuit  30  of sense amplifier band  4 . 2 A shown in FIG. 2. Read gate circuit  30   a  differs from read gate circuit  30  in that respective sources of N-channel MOS transistors  31  and  32  are not connected to the ground node but to sense amplifier drive line SNL.  
         [0077]    In sense amplifier band  4 . 2 B of the second embodiment, as respective sources of N-channel MOS transistors  31  and  32  are connected to sense amplifier drive line SNL, N-channel MOS transistors  31  and  32  both stay in an OFF state until sense amplifier  10  is activated.  
         [0078]    Then, even if read column selection line CSLR is selected before activation of sense amplifier  10 , charges on the paired read data lines GIOR and /GIOR that have been precharged are never pulled down toward the ground since both of N-channel MOS transistors  31  and  32  are in the OFF state. Then, it never occurs that the inputs of the preamplifier both have L level, and normal data-reading can thus be accomplished.  
         [0079]    Respective sources of N-channel MOS transistors  31  and  32  can be connected to sense amplifier drive line SNL to select read column selection line CSLR prior to activation of sense amplifier  10 . Accordingly, it is achieved to eliminate the waiting time from the issuance of ACT command to the issuance of RD command that is required for the conventional semiconductor memory device.  
         [0080]    The semiconductor memory device of the second embodiment can thus read data more speedily as compared with the conventional semiconductor memory device which activates the column selection line after waiting for sufficient amplification of a voltage difference between the bit lines upon activation of the sense amplifier. The same is applied similarly to high-speed writing of data.  
         [0081]    A delay element is generally employed for adjusting the timing so as to activate the column selection line after sufficient amplification by the sense amplifier. The delay value of the delay element, however, could considerably vary depending on variations in the process as well as variations of the power-supply voltage and ambient temperature, for example. For the conventional semiconductor memory device, these variations must be included in the margin to adjust the timing, and this is one of factors of delay in the output of data.  
         [0082]    On the other hand, the semiconductor memory device of the second embodiment requires no fine adjustment of the operation timing of the column selection line and therefore, the semiconductor memory device is hardly influenced by variations in the process and variations of the power-supply voltage and ambient temperature for example. Then, even under the conditions of the worst process variation, the minimum voltage and high temperature for example that generally result in operational delay of the semiconductor memory device, the degree of delay can be reduced as compared with that of the conventional semiconductor memory device.  
         [0083]    [0083]FIG. 11 is a circuit diagram showing a circuit configuration of a central control circuit  2 B- 1  according to the second embodiment of the present invention. Here, some differences between this central control circuit and central control circuit  2 A- 1  of the first embodiment shown in FIG. 4 are described.  
         [0084]    Referring to FIG. 11, central control circuit  2 B- 1  includes a D flip-flop circuit  101  taking in control signal extWRITE at a rising edge of clock signal extCLK, an OR gate  102  receiving output signal WRITE from D flip-flop circuit  101  and output signal READ from D flip-flop circuit  81  to output signal ACT, a latch circuit  54   a  receiving signal ACT and self-precharge signal SELFPRE, and an inverter  57   a  receiving and inverting an output from latch circuit  54   a  to output signal intRAS.  
         [0085]    OR gate  102  outputs signal ACT upon rising of signal WRITE or signal READ. Latch circuit  54   a  receives, at its one input, signal ACT which is thus generated and receives, at the other input, self-precharge signal SELFPRE which is directly provided to the input.  
         [0086]    Latch circuit  54   a  includes an OR gate  55   a  having one input receiving signal ACT and a NAND gate  56   a  receiving the inverted signal of self-precharge signal SELFPRE and an output from OR gate  55   a.  An output from NAND gate  56   a  is inverted to be supplied to the other input of OR gate  55   a  and simultaneously supplied to the input of inverter  57   a.    
         [0087]    In this way, elimination of D flip-flop circuit  52  and OR gate  53  and supply of self-precharge signal SELFPRE directly to latch circuit  54  further facilitate design of the timing.  
         [0088]    [0088]FIG. 12 is an operational waveform chart illustrating a circuit operation of sense amplifier band  4 . 2 B controlled by central control circuit  2 B- 1 .  
         [0089]    At time t 1 , RD command (read command) is issued and a row address and a column address are input simultaneously. It is supposed, for the second embodiment, that a read operation is always performed simultaneously with a write operation.  
         [0090]    Upon the input of the row address, word line WL is activated. The activation of word line WL turns on N-channel MOS transistor  21  in memory cell  20  and, charges then flow from capacitor  22  to bit line /BL. Consequently, a slight potential difference occurs between paired bit lines BL and /BL that are both equalized to VCCa/2 in advance.  
         [0091]    Upon the simultaneous input of the column address with the input of the row address, read column selection line CSLR is activated before activation of sense amplifier  10 .  
         [0092]    After the activation of read column selection line CSLR and upon the input of the row address, sense amplifier drive lines SPL and SNL that are both equalized to VCCa/2 in advance are driven respectively to power-supply potential VCC and ground potential GND. Accordingly, the slight potential difference between paired bit lines BL and /BL is amplified to a potential difference between power-supply potential VCC and ground potential GND.  
         [0093]    As the slight potential difference between paired bit lines BL and /BL is amplified to a potential difference between power-supply potential VCC and ground potential GND, paired read data lines GIOR and /GIOR that are both precharged to H level (logical high) in advance and are complementary to each other are driven respectively to H level and L level according to data read onto paired bit lines BL and /BL.  
         [0094]    The increased potential difference between paired read data lines GIOR and /GIOR causes generation of self-precharge signal SELFPRE through XOR gate  6  in FIG. 9 (or NAND gate  7 ). Upon generation of self-precharge signal SELFPRE, word line WL is inactivated and sense amplifier drive lines SPL and SNL are both equalized to VCCa/2. Then, paired bit lines BL and /BL are both equalized to VCCa/2.  
         [0095]    Further, as the column address is input, preamplifier activation signal PAE is activated. Upon the activation of preamplifier activation signal PAE, the data output onto paired read data lines GIOR and /GIOR is output to data output pin Q through preamplifier  40  and main amplifier  41 .  
         [0096]    Thus, when RD command is issued and immediately after the increase in potential difference occurs between paired read data lines GIOR and /GIOR, a precharge operation is carried out autonomically. For this reason, the semiconductor memory device of the second embodiment eliminates the need for an external precharge command when RD command is issued and readily achieves a higher-speed operation.  
         [0097]    The timing of the precharge operation depends on such conditions under which the operating speed is generally changed, as variations in the process, the upper and lower limits of the voltage and high temperature/low temperature for example. Further, self-precharge signal SELFPRE is input directly to latch circuit  54   a.  Then, the timing is designed here more easily as compared with the case in which the precharge command with its timing fixed by an external command is issued.  
         [0098]    [0098]FIG. 13 is a circuit diagram showing a circuit configuration of a central control circuit  2 B- 2  according to the second embodiment of the present invention.  
         [0099]    Central control circuit  2 B- 2  of the second embodiment shown in FIG. 13 differs from central control circuit  2 B- 1  in FIG. 11 in that a delay element  69  is inserted to precede the stage in which self-precharge signal SELFPRE is input to OR gate  102 . Self-precharge signal SELFPRE can thus be delayed by delay element  69  and then input to OR gate  102  so as to further improve the operation margin of the semiconductor memory device of the present invention and facilitate adjustment of the timing.  
         [0100]    [0100]FIG. 14 is a circuit diagram showing a circuit configuration of a central control circuit  2 B- 3  according to the second embodiment of the present invention.  
         [0101]    Central control circuit  2 B- 3  of the first embodiment shown in FIG. 14 differs from central control circuit  2 B- 1  in FIG. 11 in that self-precharge signal SELFPRE and its delay signal are input to NAND gate  83  instead of signal READ and its delay signal to generate the preamplifier activation signal in the end.  
         [0102]    [0102]FIG. 15 is an operational waveform chart illustrating a circuit operation of sense amplifier band  4 . 2 B controlled by central control circuit  2 B- 3 .  
         [0103]    The operational waveform chart shown in FIG. 15 differs from the chart in FIG. 12 in that preamplifier activation signal PAE is activated not by the input of the column address but by generation of self-precharge signal SELFPRE.  
         [0104]    Preamplifier activation signal PAE is thus activated upon generation of self-precharge signal SELFPRE, and accordingly the delay time up to activation of preamplifier activation signal PAE is shorter than that when preamplifier activation signal PAE is activated by the input of the column address. Further, as the activation of preamplifier activation signal PAE depends on the increase in potential difference between paired read data lines GIOR and /GIOR, design of the timing is facilitated.  
         [0105]    As discussed above, the second embodiment achieves the effect of the first embodiment and further makes it possible to normally read data all the time while achieving a high-speed random access by connecting respective sources of N-channel MOS transistors  31  and  32  to sense amplifier drive line SNL.  
         [0106]    Moreover, the direct input of self-precharge signal SELFPRE to latch circuit  54   a  further facilitates design of the timing.  
       Third Embodiment  
       [0107]    A semiconductor memory device  1 C of a third embodiment shown in FIG. 16 is configured, as compared with the configuration of semiconductor memory device  1 B of the second embodiment, to have a plurality of pairs of read data lines GIOR&lt;m&gt; and /GIOR&lt;m&gt; (m=1−n, n is a natural number) that are connected to preamplifier  40   —   m  and one pair of read data lines GIOR&lt;0&gt;and /GIOR&lt;0&gt;, having the shortest distance (length) to the input terminals of XOR gate  6 , connected to XOR gate  6 .  
         [0108]    Preamplifier  40   —   m  receives data which is read onto the pair of read data lines GIOR&lt;m&gt; and /GIOR&lt;m&gt; to produce a single-ended output of the data in response to a preamplifier activation signal PAE. Main amplifier  41   —   m  buffers the data of the single-ended output from preamplifier  40   —   m  to output the data to a data output pin Q&lt;m&gt;. It is noted that the configuration of semiconductor memory device  1 C of the third embodiment is applicable to semiconductor memory device  1 A of the first embodiment.  
         [0109]    In this way, the distance of the paired read data lines to the input terminals of XOR gate  6  can be shortened to allow the timing of self-precharge to occur earlier.  
         [0110]    The distance of the pair of read data lines to the input terminals of XOR gate  6  is not necessarily the shortest. Instead, any pair of read data lines except for the pair of read data lines GIOR&lt;n&gt; and /GIOR&lt;n&gt; having the longest distance to the input terminals of XOR gate  6  may provide the same effect. Further, as described in connection with FIG. 2 of the first embodiment, XOR gate  6  may be replaced by NAND gate  7 .  
         [0111]    As discussed above, according to the third embodiment, the distance of the pair of read data lines to the input terminals of XOR gate  6  can be shortened to achieve a still higher operation of the semiconductor memory device.  
       Fourth Embodiment  
       [0112]    A semiconductor memory device  1 D of a fourth embodiment shown in FIG. 17 is configured, as compared with the configuration of semiconductor memory device  1 B of the second embodiment, to have a plurality of pairs of read data lines GIOR&lt;m&gt; and /GIOR&lt;m&gt; (m=1−n, n is a natural number) that are connected to preamplifier  40   —   m,  and additionally include an IO selection circuit  8 .  
         [0113]    Preamplifier  40   —   m  receives data which is read onto the pair of read data lines GIOR&lt;m&gt; and /GIOR&lt;m&gt; to produce a single-ended output of the data in response to a preamplifier activation signal PAE. Main amplifier  41   —   m  buffers the data of the single-ended output from preamplifier  40   —   m  to output the data to a data output pin Q&lt;m&gt;. The configuration of semiconductor memory device  1 D of the fourth embodiment is applicable to semiconductor memory device  1 A of the first embodiment as well.  
         [0114]    IO selection circuit  8  receives inputs from a plurality of pairs of read data lines GIOR&lt;m&gt; and /GIOR&lt;m&gt; to select an arbitrary pair of read data lines therefrom and output data from the selected pair of read data lines to XOR gate  6 . As selection means of IO selection circuit  8 , mask switching means or any known programming means like fuse programming means, for example, may be employed.  
         [0115]    In this way, an arbitrary one of the pairs of read data lines can be selected to set the timing for self-precharge in a more flexible manner and consequently, the operation of the semiconductor memory device is improved. As described in connection with FIG. 2 of the first embodiment, XOR gate  6  may be replaced by NAND gate  7 .  
         [0116]    As discussed above, according to the fourth embodiment, an arbitrary pair of read data lines can be selected from a plurality of pairs of read data lines to achieve, in addition to the effect of the third embodiment, improvement in the operation of the semiconductor memory device.  
         [0117]    In the embodiments heretofore discussed, it is possible to allow read data to be read onto only the read input/output lines used for the self-precharge in a write operation as well and, to allow read data to be read onto read input/output lines not used for the self-precharge in a read operation only. Accordingly, the operation current in the write operation can be decreased.  
         [0118]    Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.