Abstract:
Disclosed is a subscriber loop carrier system wherein, to synchronize the phases of frames and multiframes from a plurality of subscriber loop carriers, corrections are made on the phases of frames and multiframes without relying on memory storage. The phase difference of the frame and multiframe phases with respect to a reference phase is detected at the receiving end. The detected phase difference is transmitted from the receiving end to the transmitting end. At the transmitting end, the phases of frames and multiframes being formed are controlled on the basis of the detected phase difference.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method and apparatus for correcting the phase of transmitted data frames, and more particularly to a method and apparatus for correcting the phase of frames/multiframes transmitted over incoming lines in subscriber loop carrier systems. 
     2. Description of the Related Art 
     Subscriber loop carrier systems have been employed to accommodate subscribers, at geographically remote locations from switching offices, economically and with high transmission quality, and also to alleviate the problem of the ever increasing number of telephone cables in urban areas. In conventional subscriber loop carrier systems, a plurality of subscriber lines are multiplexed as PCM data with a frame/multiframe structure at a remote terminal (RT), and the thus multiplexed PCM data are then transmitted over a fiber optic or other transmission medium to a central office terminal (COT), where the data are demultiplexed into a plurality of subscriber lines for connection to switching equipment. Furthermore, in recent years, high-order multiplexing has come to be adopted wherein a plurality of multiplexed data, instead of undergoing demultiplexing at a COT, are further multiplexed into a high-level multiplexed signal, for direct connection to a switching network such as SONET. To achieve this, a multiplexer for remultiplexing a plurality of multiplexed data is provided with a time slot interchanger (TSI) for interchanging time slots to accomplish dynamic rearrangement on a user-by-user basis. The TSI is provided to accommodate a larger number of subscriber lines than the number of channels in a multiplexed transmission path. To facilitate the interchanging of time slots in the TSI, the phases of the frames/multiframes of the PCM data transmitted over different transmission paths from different RTs must be corrected to achieve synchronization. In the prior art, this phase correction is done by storing the data in memory at the receiving end. This requires the provision of a memory for storing the data, and furthermore, transmission delays are caused because of temporarily storing the data. 
     If the differences between transmission delay times from the different RTs are within one-frame period, the phase correction is only necessary for the frame, but no phase correction is needed for the multiframe. In this case, a memory that can store one frame of data will suffice for the purpose, and the transmission delay can be kept within one frame period. On the other hand, if the differences between transmission delay times from the different RTs are larger than one frame period, the phase correction must be done not only for the frame but for the multiframe that typically consists of 12 frames. In such a case, the memory capacity required will be much larger, and significant transmission delays will result. Furthermore, in order to use a single fiber optic cable for carrying both the incoming and outgoing lines, the adoption of a time compression multiplexing (TCM) system is considered. If the TCM system is adopted, phase correction for the multiframe becomes essential. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a method and apparatus for phase correction in subscriber loop carrier systems, whereby phase correction can be done for frames and multiframes without relying on memory storage. 
     According to the present invention, there is provided a frame phase correction method for correcting the phase of data frames at a receiving end for the data transmitted to the receiving end from a transmitting end, comprising the steps of: detecting a phase difference between the phase of received frames and a reference phase at the receiving end; transmitting the detected frame phase difference to the transmitting side; and controlling the phase of frames being formed at the transmitting end on the basis of said frame phase difference. 
     According to the present invention, there is also provided a frame phase correcting apparatus for correcting the phase of data frames at a receiving end for the data transmitted to the receiving end from a transmitting end, comprising: means for detecting a phase difference between the phase of received frames and a reference phase at the receiving end; means for transmitting the frame phase difference detected by the frame phase difference detecting means to the transmitting end; and means for controlling the phase of frames being formed at the transmitting end on the basis of said frame phase difference. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing the basic configuration of a subscriber loop carrier system in which the present invention is embodied; 
     FIG. 2 is a block diagram showing the configuration of a low-order channel interface according to one embodiment of the present invention; 
     FIG. 3 is a block diagram showing the configuration of a multiplexer according to one embodiment of the present invention; 
     FIG. 4 is a diagram showing the timing for various signals in association with a frame structure; 
     FIG. 5 is a diagram showing the timing for various signals in association with a multiframe structure; 
     FIG. 6 is a circuit block diagram showing a configurational example of a frame or multiframe phase difference detector; 
     FIG. 7 is a circuit block diagram showing a configurational example of a frame or multiframe timing generator; and 
     FIGS. 8 and 9 are flowcharts for controllers. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a diagram showing the basic configuration of a subscriber loop carrier system in which the present invention is embodied; the overall configuration of the system is shown here in a simplified form. In the figure, the numeral 1 designates a subscriber interface (CH), provided for each subscriber, and via which an analog signal from the subscriber (telephone) side is converted to a PCM signal for transmission over each individual channel and vice versa. A low-order channel interface (CH inf) 2 is provided via which PCM signals from the individual channels are multiplexed into or demultiplexed from a multiframe signal. Line terminations (LT) 3 and 4 each perform conversion between a multiplexed signal and a signal transmitted or for transmission over an optical or metallic transmission path 5. A multiplexer 6 converts the multiplexed signals into a higher-level multiplexed signal for connection to a switching network and vice versa. 
     FIG. 2 is a diagram showing the configuration of a low-order channel interface according to one embodiment of the invention. The same parts as those shown in FIG. 1 are designated by the same numerals. In the low-order channel interface 2, the numeral 11 is a codec which consists of a digital-to-analog (D/A) converter 12 for converting PCM signals into analog signals, and an analog-to-digital (A/D) converter 13 for converting analog signals into PCM signals. 
     A channel interface converter (CH-inf) 14 for outgoing lines separates multiframe-structured data (VFR) transferred from the LT 3 into PCM signals for individual channels by using a clock (MCKR), frame timing pulse (FPR), and multiframe timing pulse (ABR), and transfers data (VFR&#39;) to the respective D/A converter units 12 together with a clock (MCKR&#39;), frame timing pulse (FPR&#39;), and multiframe timing pulse (ABR&#39;). 
     A channel interface converter (CH-inf) 15 for incoming lines supplies a clock (MCKS&#39;) to the A/D converter 13 for each channel in response to a clock (MCKS) fed from the LT 3, and multiplexes data (VFS&#39;), i.e., PCM signals supplied from the A/D converter 13 in synchronism with the clock (MCKS&#39;), into frame/multiframe-structured data (VFS) which is transferred to the LT 3. 
     A frame timing generator (FP-GEN) 16 performs phase correction on the frame timing pulse (FPR) fed from the LT 3 by using frame timing phase difference information supplied from a controller 18, and produces outputs, one being supplied to the LT 3 as a frame timing pulse (FPS) and the other supplied to the A/D converter 13 as a frame timing pulse (FPS&#39;) for each channel. 
     A multiframe timing generator (AB-GEN) 17 performs phase correction on the multiframe timing pulse (ABR) fed from the LT 3 by using multiframe timing phase difference information supplied from the controller 18, and produces outputs, one being supplied to the LT 3 as a multiframe timing pulse (ABS) and the other supplied to the A/D converter 13 as a multiframe timing pulse (ABS&#39;) for each channel. 
     The controller 18 supplies the frame timing phase difference information to the FP-GEN 16 and the multiframe phase difference information to the AB-GEN 17 in accordance with frame/multiframe timing phase difference information supplied from the multiplexer 6 (FIG. 3). 
     FIG. 3 is a diagram showing the configuration of a multiplexer according to one embodiment of the invention, wherein the same parts as those shown in FIG. 1 are designated by the same numerals. The multiplexer 6 consists of a demultiplexing unit (DMUX) 21 for demultiplexing a higher-level multiplexed signal, and a multiplexing unit (MUX) 22 for multiplexing lower-level multiplexed signals into a higher-level multiplexed signal. The DMUX 21 demultiplexes the higher-level multiplexed signal and distributes each of the demultiplexed multiframe data (VFR) to the LT 4 together with a clock (MCKR), frame timing pulse (FPR), and multiframe timing pulse (ABR). 
     The MUX 22 sends a clock (MCKS) to the LT 4 and multiplexes data (VFS) from the LT 4 into a higher-level multiplexed signal for transmission to higher-order equipment. 
     A frame phase difference detector (FP-DET) 23 compares a frame timing pulse (MFPS) fed from the MUX 22 with a frame timing pulse (FPS) fed from the LT 4, and produces frame timing phase difference information. A multiframe phase difference detector (AB-DET) 24 compares a multiframe timing pulse (MABS) fed from the MUX 22 with a multiframe timing pulse (ABS) fed from the LT 4, and produces multiframe timing phase difference information. 
     A controller 25 transmits the frame timing phase difference information from the FP-DET 23 and the multiframe timing phase difference information from the AB-DET 24 to the controller 18 (FIG. 2) in the low-order channel interface 2. 
     Thus, according to the invention, the frame phase difference and the multiframe phase difference occurring between the MUX 22 and the LT 4 are detected in the multiplexer 6, and the detected information is transmitted to the low-order channel interface 2, where, based on this information, the phase differences of the frame timing and multiframe timing pulses between the A/D converter 13 and the LT 3 are corrected, compensating for differences in delay time between LT 3 and LT 4 and thus reducing the phase differences of the frame and multiframe signals, respectively, to zero. 
     FIG. 4 shows the timing for the various signals in association with the frame structure. In the example shown, one frame consists of 24 time slots (TS), but this is only illustrative and not restrictive. 
     In the figure, VFS/R indicates frame-structured data for incoming and outgoing lines. TS1 to TS24 are time slots; each TS consists of 8-bit data, b1 to b8, and a 1-bit framing bit (F) is added at the beginning of the frame, so that each frame consists of a total of 193 bits (in 125 μs). 
     FPS/R is a frame timing pulse for incoming and outgoing lines, MFPS is a frame timing pulse output from the multiplexer 6, and MCKS/R is a clock signal for incoming and outgoing lines. 
     FIG. 5 shows the timing of the various signals in association with the multiframe structure. In the example shown, one multiframe consists of 12 frames, but this is only illustrative and not restrictive. 
     In the figure, VFS/R indicates multiframe-structured data for incoming and outgoing lines. F1 to F12 are frames each corresponding to the 193-bit frame illustrated in FIG. 4. 
     ABS is a multiframe timing pulse for incoming lines, MABS is a multiframe timing pulse output from the multiplexer 6, ABR is a multiframe timing pulse for outgoing lines, FPS/R is a frame timing pulse for incoming and outgoing lines, and MCKS/R is a clock signal for incoming and outgoing lines. 
     FIG. 6 is a circuit block diagram showing a configurational example of the frame phase difference detector (or multiframe phase difference detector). These detectors can be easily implemented using relatively simple logic circuits. In the figure, the signals associated with the multiframe phase difference detector 24 are shown in square brackets along with the corresponding signals associated with the frame phase difference detector 23. 
     In the frame phase difference detector 23 or the multiframe phase difference detector 24, the numeral 31 indicates a counter which counts the number of clock pulses (MCKS) or frame timing pulses (MFPS), starting from the pulse position of the frame timing pulse (MFPS) or multiframe timing pulse (MABS) applied at a start signal input (STR) from the MUX 22 and ending at the pulse position of the frame timing pulse (FPS) or multiframe timing pulse (ABS) applied at a stop signal input (STP) from the LT 4. The resulting counter value is latched into a counter value holding latch 32 before transfer to the controller 25. Delay circuits 33 and 34 are provided which delay the frame timing pulse (FPS) or multiframe timing pulse (MFPS) in accordance with the clock (MCKS) or frame timing pulse (MFPS), and which produce a latch timing signal for the counter value holding latch 32 and a reset signal for the counter 31, respectively. 
     In the example shown in FIG. 6, the counter 31 is started by the application of MFPS or MABS, and stopped by the application of FPS or ABS, upon which the counter value is read out. It will be appreciated, however, that the counter value may also be read out by starting the counting upon FPS or ABS and stopping it upon MFPS or MABS. 
     FIG. 7 is a circuit block diagram showing a configurational example of the frame timing generator (multiframe timing generator). These generators also can be easily implemented using relatively simple logic circuits. In the figure, the signals associated with the multiframe timing generator 17 are shown in square brackets along with the corresponding signals associated with the frame timing generator 16. 
     In the frame timing generator 16 or the multiframe timing generator 17, the numeral 41 indicates a data buffer where the phase correction data from the controller 18 is stored. A counter 42 is reset by the frame timing pulse (FPR) or multiframe timing pulse (ABR) applied from the LT 3, and counts the number of clock pulses (MCKR) or frame timing pulses (FPR) by a period equal to the phase correction data written in the data buffer 41. When the counting is completed, a signal is output from a carry signal output (CO) whereby an FPS [ABS] timing generator 44 is driven to generate frame timing pulses (FPS, FPS&#39;) or multiframe timing pulses (ABS, ABS&#39;). 
     A delay circuit 43 delays FPR or ABR and supplies the resulting output to the data buffer 41 as a loading signal by which the phase correction data is written into the data buffer 41 immediately after the resetting of the counter 42. At the completion of the counting by the counter 42, the FPS [ABS] timing generator 44 generates the frame timing pulses (FPS, FPS&#39;) or the multiframe timing pulses (ABS, ABS&#39;). 
     FIGS. 8 and 9 are flowcharts illustrating the operations of the controllers: FIG. 8 for the controller 25 and FIG. 9 for the controller 18. Referring to FIG. 8, when the line termination (LT) is in synchronization and no alarm is issued, the controller 25 reads the frame phase difference data and multiframe phase difference data from the frame phase difference detector 23 and multiframe phase difference detector 24, respectively, and transmits the phase difference data to the controller 18 if the frame phase difference or multiframe phase difference is not zero. Then, after waiting for a prescribed time, the operation returns to the beginning of the control process. The prescribed waiting time is inserted to perform the control in an intermittent manner. 
     Referring to FIG. 9, when the phase difference data is received from the controller 25, the controller 18 writes the frame phase difference data into the frame timing generator 16 and the multiframe phase difference data into the multiframe timing generator 17. 
     In this embodiment, the processing in the controllers 18 and 25 is implemented in software, but since the processing is relatively simple, it can also be easily implemented in hardware using logic circuits. 
     Communication between the controllers 18 and 25 is accomplished, for example, by using overhead bits appended to the data transmitted between the LT 3 and LT 4.