Abstract:
Overlapping gate electrodes are selectively energized to vary the electrical length and thus the resistance of the conductive path through a field effect attenuator. The electrical width can also be varied to provide additional control over the resistance.

Description:
CROSS REFERENCE TO A RELATED PATENT APPLICATION 
     The subject matter of the present application is related to the subject matter of a patent application entitled &#34;DIGITALLY CONTROLLED FIELD EFFECT ATTENUATOR DEVICES&#34; having a filing date of JUNE 5, 1989, and a Ser. No. of 361,470, and which is assigned to the same assignee as the present application. 
     BACKGROUND OF THE INVENTION 
     The subject invention relates generally to attenuator circuitry and particularly to variable attenuator devices employing field effect technology. 
     Present day electronic applications often require the utilization of attenuator circuits or components which are responsive to control signals to vary the amount of resistance provided thereby. Such attenuators are useful for automatic gain control circuits, position locating systems, telephone systems, television systems, etc. 
     Prior art, electronically variable solid state attenuators for use at Radio Frequencies (RF) typically employ PIN diodes. PIN diode attenuators may be arranged in a variety of network configurations. Biasing control circuitry which include Field Effect Transistors (FETs) have been utilized to bias the PIN diodes in response to various analog control signal magnitudes, thereby causing the PIN diode network to provide any one of a variety of resistance magnitudes. Discrete PIN diode attenuators are capable of outstanding performance but require an undesirable amount of electrical power for some applications. Moreover, PIN diodes are not easily integrated into monolithic circuitry. 
     Other prior art approaches for providing electronically variable attenuators sometimes utilize FETs such as gallium arsenide (Ga As) Metal Semiconductor Field Effect Transistors (MESFETs). These devices also may be arranged in a variety of networks and each device may operate without bias and therefore consume almost no electrical power except during switching operations. Analog control signals are applied to the gates of these devices to adjust the attenuation level. The resistance magnitude provided by each FET is adjusted by controlling the depth of the undepleted channel in the device in accordance with the magnitude of the analog signal. Unfortunately, such variation of the depth of the undepleted channel tends to result in a nonlinear transfer characteristic which provides high intermodulation levels between RF signals applied to these devices. This causes the generation of unwanted frequency components that result in distortion. 
     To minimize such distortion, some prior art attenuators utilize additional circuitry which undesirably increases cost, size, weight and undesirably decreases reliability. Moreover, prior art attenuators sometimes require precise control of the magnitudes of the analog control signals. Such precision is difficult to achieve because analog signal magnitudes tend to drift with temperature, age of the semiconductors, variations of process parameters from device to device, etc. Also, some MESFET attenuator networks tend to have a limited tuning range. 
     Monolithic Microwave Integrated Circuits (MMIC) applications using GaAs semiconductor material are presently being developed because of the high frequency handling capabilities and the small size of such circuits. These applications require electronically variable attenuators which are compatible with the presently available MMIC semiconductor fabricating processes. The aforementioned prior art attenuators tend to be too expensive to fabricate, take too much space and/or have an unduly high failure rate for some of these applications. Also, some complex prior art attenuators utilizing analog control signals tend to operate too slowly to take advantage of the inherent speed characteristics of MMIC circuitry. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide electronically variable attenuators which are capable of high speed, digitally controlled operation over wide bandwidths. 
     Another object of the invention is to provide electronically variable attenuators which are compatible with MMIC applications and which can be provided in monolithic integrated circuit form. 
     An electronically variable field effect attenuator in accordance with an embodiment of the invention includes semiconductor material providing a signal path between an input electrode and an output electrode. Overlapping gate electrodes are arranged to extend across the semiconductor material from different directions. Gate electrode control lines are selectively coupled to the gate electrodes. These control lines are adapted to selectively apply digital control signals in the form of &#34;1&#39;s&#34; or &#34;0&#39;s&#34; to the gate electrodes to control the conductivity of the semiconductor regions underlying the gate electrodes to thereby control the magnitude of the attenuation provided by the attenuator by changing the length of the conductive path between the input and output electrodes. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     A more complete understanding of the present invention may be derived by reference to the detailed description and the claims considered along with the accompanying drawings wherein like reference numbers designate similar parts. 
     FIG. 1 shows a resistive element; 
     FIG. 2 is a top view of an embodiment of a field effect attenuator; 
     FIG. 3 is a cross-sectional view of the field effect attenuator of FIG. 1; 
     FIGS. 4 illustrates one mode of operation for the attenuator of FIG. 2; 
     FIG. 5 shows a mode of operation of another attenuator configuration having interconnected gate electrodes; 
     FIG. 6 illustrates an attenuator having unequally spaced gate electrodes; and 
     FIG. 7 illustrates a dimensioned attenuator. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a resistive semiconductor element 10 having a width 12, a length 14, and a depth 16. Current is assumed to flow in the direction of arrow 18 between front surface 15 and the hidden back surface. The magnitude of the resistance of resistive element 10 is determined by the geometry thereof and the material properties of the active semiconductor material. More specifically, the resistance R can be given to a first order as: ##EQU1## where (rho) is the bulk resistivity of the active semiconductor material, L is the electrical length of the conductor path and A is the cross-sectional area of the active semiconductor region. In FIG. 1, the cross-sectional area A of element 10 is width 12 times depth 16. 
     The bulk resistivity of the semiconductor material of element 10 can be estimated to a first order as: ##EQU2## where q is an electronic charge, u o  is the low-field mobility of the semiconductor material and N is the free carrier density of the semiconductor. If part of the semiconductor material of a resistive element is depleted then the cross-sectional area A of the active semiconductor is the product of the active region depth times the active region width. 
     FIG. 2 shows a top view of the layout of an electronically variable field effect attenuator device 20 in accordance with one embodiment of the invention. Discrete levels of attenuation may be provided by device 20 depending on the arrangement of the digital &#34;1&#39;s&#34; and &#34;0&#39;s&#34; applied to the gate electrodes thereof. Device 20 may be fabricated using any one of a plurality of different technologies including standard silicon or gallium arsenide (GaAs) fabrication. For many microwave circuit applications, it would be useful to fabricate device 20 using depletion mode gallium arsenide (GaAs) MESFET technology. This technology is compatible with MMIC fabrication approaches. 
     More specifically, device 20 includes semiconductor material 21 which has a resistance determined generally by the principles explained for element 10. Rectangular top surface 22 of material 21 has first and second parallel ends 23 and 25 and first and second parallel sides 27 and 29. Ohmic input electrode 24 is placed near end 23 of semiconductor surface 22 and output ohmic contact 26 is placed near the other end 25 of semiconductor surface 22. Assuming no interaction with other control mechanisms, semiconductor material 21 would normally provide a current path between electrodes 24 and 26 having a predetermined length L1. Parallel Schottky gate electrodes 28, 30, 32, 34 and 36 are placed on and overlie portions of surface 22. The practical limit to the number of gate electrodes is determined by the particular fabrication technology being utilized. Gate electrodes 28, 32 and 36 form a first plurality or group of gate electrodes extending partially across semiconductor surface 22 from first side 27 in a direction perpendicular to the normal current flow between electrodes 24 and 26. Gate electrodes 30 and 34 form a second group or plurality of gate electrodes extending partially across semiconductor surface 22 from second side 29. Gate electrodes 30 and 34 are interdigitated with electrodes 28, 32 and 36. Ends 31 and 33 of electrodes 30 and 34 are closer to side 27 than ends 35, 37 and 39 of electrodes 28, 32 and 36. The electrodes from each group overlap each other as shown in FIG. 2. 
     FIG. 3 indicates a cross section of device 20 along lines 40 of FIG. 2. More specifically, ohmic contacts 24 and 26 are located on surface 22 of the semiconductor material 21 of resistive element 20. Active N channel semiconductor layer 21 supports ohmic contacts 24 and 26 and the rectifying Schottky gate electrodes including contacts 30 and 34. The Schottky rectifying junction formed by the gate electrodes with semiconductor 21 can be provided in a known manner by utilizing gate electrodes made from a proper combination of metals such as tungsten, gold and titanium. N+ regions 44 and 48 are respectively provided underneath electrodes 24 and 26 by known processes. 
     Gate electrode 34, for instance, includes the portion of the conductor overlying surface 22. The remainder 41 of the conductor can be considered to be a gate control line. Semiconductor material 21 is located on semi-insulating substrate 50. The mere placement of Schottky gate electrodes on semiconductor material 21 results in some depletion of the region of semiconductor material 21 immediately beneath each contact of available free charges. The depletion region 54 for contact 34 extends a distance 52, as shown in FIG. 3. This action takes place because of the difference in the electron affinity of the Schottky metal 34 and semiconductor 21 at the barrier surface 22. The resulting depletion regions automatically exist under zero bias potential conditions. These depletion regions do not effect the electrical length, L1 of the conductive path between electrodes 24 and 26 but these regions do effect the depth of the conductive path. 
     The depths of the depletion regions can be further varied by varying the magnitude of a potential applied to the gate electrodes such as electrode 34, for instance. More specifically, a negative potential of sufficient magnitude applied to gate electrode 34 will cause the depletion region to extend by distance 61 down to the top surface 58 of semi-insulating substrate material 50 to form depletion region 60 which renders a portion of semiconductor material 21 non-conductive. The potential necessary to cause this occurrence is defined as the pinch off voltage (V p ). When pinched off, the resulting depletion in carriers causes a very high resistance region bounded by a line 60 in semiconductor material 21 between ohmic contacts 24 and 26 thereby rendering a portion of device 20 mostly non-conductive. 
     Alternatively, a more positive potential applied to contact 34, for instance, decreases the depth 52 of zero bias depletion region 54 thereby increasing the conductivity of the portion of the current path underlying gate electrode 34 between ohmic contacts 24 and 26, thereby rendering at least a portion of the device 20 more conductive. A similar description is also applicable to the operation of the other gate electrodes and underlying semiconductor material. 
     The pinch off voltage of the material is a function of the doping density of the semiconductor material and the depth of the active region. For GaAs MESFET technology, the voltage level, V p , can be expressed approximately as: ##EQU3## where D is the active semiconductor region depth, (eps) is the dielectric constant of the material and V bi  is the built-in potential of the rectifying contact which is typically about 0.8 volts. 
     For normal operating conditions, each of the gate electrodes will be biased at one of two voltage levels at a particular instant in time. One of these voltages levels corresponds to a digital &#34;1&#34;. When the gate electrode receives this bias level, the underlying semiconductor material can be in the &#34;on-state&#34;. Current can then flow in the semiconductor material beneath the rectifying electrode. For depletion mode Gallium Arsenide MESFET technology commonly used for MMIC circuits, this digital &#34;1&#34; voltage is preferably 0volts. The other voltage level corresponds to a digital &#34;0&#34;. If a gate eIectrode is at this bias level, the underlying semiconductor materials in the &#34;off-state&#34; and current cannot flow underneath the electrode. For depletion mode GaAs MESFET technology, this digital &#34;0&#34; voltage is equal to or more negative than the pinch off voltage, Vp. 
     Referring now to FIG. 4, one mode of operation of attenuator 20 will be explained. It is assumed that gate electrodes 34 and 36 are simultaneously receiving the digital &#34;0&#34; voltage which causes their respective depletion regions to have an approximate top shape as outlined by dashed lines 70 and 72. These regions also extend down to substrate 50, as previously explained. It is further assumed that the other gate electrodes 28, 30 and 32 are receiving the digital &#34;1&#34; control signals. Under these conditions the current flowing between electrodes 24 and 26 can be considered to encounter a plurality of differently valued series resistors which combine to provide a composite resistance. The electrical length of the first resistor, R1 is measured by line 76 and the width thereof is measured by line 78. Second resistor, R2 is joined to R1 at dotted line 77. The length of R2 is measured by line 79 and the width of R2 is measured by line 80 between dotted line 81 and side 27. The length of the third resistor, R3 is measured by line 82 between dotted line 81 and side 29, and the width of R3 is measured by line 84. The length of the next resistor, R4 is measured by line 86 between dotted lines 87 and 89, and the width is measured by line 88. The length of the final resistor, R5 is measured by line 90 and the width is again measured by line 78. The total resistance between electrodes 24 and 26, therefore, is equal to the sum of R1+R2+R3+R4+R5. Thus, by controlling the logic signal applied to the gate electrodes to be either a 0 or a 1, the effective electrical lengths encountered by the current flow between electrodes 24 and 26 can be tailored to provide different desired amounts of total resistance. The resistance of composite resistors can be calculated to a first order by using Equation (1). 
     Also, various gate electrodes can be connected together as indicated in FIG. 5 which shows a gate control line 100 interconnecting electrodes 32, 34 and 36 so that the portions of the semiconductor material underlying these electrodes are rendered simultaneously conductive or nonconductive. If a digital &#34;0&#34; is applied by control line 100 to electrodes 36, 32 and 34, the current generally follows the path indicated by line 102 of FIG. 5. Since path 102 is longer than the straight line path between conductors 24 and 26, path 102 results in increased PTB resistance. 
     FIG. 6 illustrates a top view of variable attenuator device 104 having gate electrodes 106, 108, 110, 112 and 114. Gate control line 116 interconnects gate electrodes 106, 110 and 114. The distances between these parallel gate electrodes varies. More specifically, the smallest distance is measured between electrodes 106 and 108 by line 120. The distance between electrodes 108 and 110 is greater as indicated by line 122 and the distance between electrodes 110 and 112 is still greater as measured by line 124. Finally, the distance between electrodes 112 and 114 has the greatest magnitude as indicated by line 126. Moreover, gate electrode 106 extends across less of the width of the semiconductor material than the other gate electrodes. The length of the gate electrodes can be adjusted to tailor the attenuation characteristic of the attenuators by varying the width of the conductive path around the electrode when the electrode receives a &#34;0&#34; to meet particular criteria. 
     FIG. 7 shows dimensions for, attenuator 130 which is similar to attenuator 20 of FIG. 4 except that the gate electrodes 28, 32 and 36 are interconnected by line 132. The resistance between input and output electrodes 24 and 26 corresponding to the indicated digital control signals, is provided by the following table: 
     
         ______________________________________LOGIC STATE (1 = 0 volts, 0 = -Vp)rho = 50 ohms/square(28,32,26)     34           30    Rtotal (ohms)______________________________________1         1            1      500         1            1     2500         0            1     5370         1            0     5370         0            0     8241         0            0     250 (approx.)______________________________________ 
    
     Since the channel portions underlying the gate electrodes of the described attenuators 20, 104 and 130 can be either completely pinched off or conductive, these devices then provide less intermodulation distortion than other types of attenuators utilizing FETs which are operated in partially pinched-off modes. Thus, attenuators 20, 104 and 132 do not require distortion compensation circuitry. Furthermore, the geometries of these attenuators are arranged to have a minimum of parasitic capacitance thereby facilitating the high speed operation for which GaAs MMIC circuits are well suited. 
     Digital control of attenuators 20, 104 and 130 eliminates the aforementioned problems associated with analog control. Also, these attenuators are capable of wideband operation and can be readily provided in monolithic form required by MMIC applications, for example. 
     While the invention has been particularly shown and described with reference to the preferred embodiments, those skilled in the art will understand that changes in form and detail may occur therein without departing from the scope of the present invention.