Abstract:
A vertical structure is formed upon a semiconductor substrate. The vertical structure comprises four dielectric layers parallel to a top surface of the semiconductor substrate and three conducting layers, one conducting layer between each vertically adjacent dielectric layer. A first FET (field effect transistor) and a third FET are arranged parallel to the top surface of the semiconductor and a second FET is arranged orthogonal to the top surface of the semiconductor. All three FETs are independently controllable. The first conducting layer is a gate electrode of the first FET; the second conducting layer is a gate electrode of the second FET, and the third conducting layer is the gate electrode of the third FET.

Description:
FIELD OF THE INVENTION 
       [0001]    This invention relates generally to Field Effect Transistors (FETs), and more particularly to vertically stacked FETs suitable for logic gate (e.g., NAND, NOR, AOI, OAI) configurations. 
       SUMMARY OF EMBODIMENTS OF THE INVENTION 
       [0002]    Semiconductor chips are expensive to manufacture. Therefore, it is important to place as much function as possible on a semiconductor chip of a given size. Engineers constantly strive to place logic gates as densely as possible. Embodiments of the current invention vertically stack Field Effect Transistors (FETs) in order to improve density. In particular, embodiments of the invention provide for stacking N-channel Field Effect Transistors (NFETs) and for stacking P-channel Field Effect Transistors (PFETs). The NFETs are independently controllable and can be used for an NFET portion of a NAND circuit, an AOI circuit or a NOR circuit. Likewise, the PFETs are independently controllable and can be used for a PFET portion of a NAND circuit or a NOR circuit. Conventional Complementary Metal Oxide Semiconductor (CMOS) logic has NFETs arranged side-by-side and PFETs also arranged side-by-side. 
         [0003]    Vertically stacked FETs are constructed on a semiconductor substrate. A first FET on the semiconductor substrate has a first source, a first drain, a first gate dielectric, a first body, and a first gate electrode. A second FET has a second source, a second drain, a second gate dielectric, a second body, and a second gate electrode. A third FET has a third drain, a third source, a third gate electrode, a third gate dielectric, and a third body. The second FET is oriented orthogonally to the first and third FET, but on the same vertical stack, that is, on a side of the stack. The first, second, and third gate electrodes may be connected to different logical signals. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  shows a stack having a silicon semiconductor substrate (P− silicon assumed). Alternating layers of dielectric material (HfO 2  used for exemplary purposes) and FET gate conductor material (“metal” used for exemplary purposes) are depicted. 
           [0005]      FIG. 2  shows a vertical structure etched from the stack of  FIG. 1 , in isometric style, further showing a gate area is formed on the vertical stack. The vertical structure is shown having “dogbone” ends suitable for etching and forming contacts with the FET gate electrodes. 
           [0006]      FIG. 3  shows the vertical structure of  FIG. 2  further covered in silicon dioxide. 
           [0007]      FIG. 4  shows the silicon dioxide of  FIG. 3  etched to expose a top of a top dielectric layer (HfO 2 ). A cross section AA is shown; cross section AA will be used in subsequent figures to show creation of FET devices. 
           [0008]      FIG. 5  shows the cross section AA identified in  FIG. 4 . A dielectric (SiO 2  shown) spacer has been conformally deposited. 
           [0009]      FIG. 6  shows the spacer after an anisotropic etch. Source and drain areas have been implanted. 
           [0010]      FIG. 7  shows a first growth of an epitaxial layer. The doping of the first epitaxial layer is similar to the doping of the source and drain area (i.e., if the source and drain areas are N+, then the first epitaxial layer is also N+). 
           [0011]      FIG. 8  shows an oxygen implant that creates an SiO 2  layer isolating a source (or drain) area from the first growth of epitaxial layer. A photoresist layer may be used to prevent SiO 2  formation over another source (or drain) area, as shown. 
           [0012]      FIG. 9  shows the structure of  FIG. 8  with photoresist removed. SiO 2  has been etched above the epitaxial area. A high-K dielectric (HfO 2  used for example) has been conformally deposited. 
           [0013]      FIG. 10  shows the structure of  FIG. 9  after anisotropic etching of the high-K dielectric and growth of a second epitaxial layer of opposite doping to the first epitaxial layer. 
           [0014]      FIG. 11  shows the structure of  FIG. 10  after further addition of a third epitaxial layer of similar doping to the first epitaxial layer and a fourth epitaxial layer of similar doping to the second epitaxial layer. 
           [0015]      FIG. 12  shows the hole of  FIG. 11  after planarization. 
           [0016]      FIG. 13  shows structure of  FIG. 12  after creation of a lined contact and contacts made to an exposed surface of the third epitaxial layer. 
           [0017]      FIG. 14A  shows a top view of the structure of  FIG. 13  to show contacts made to source and drain regions and to gate electrodes.  FIG. 14B  shows a side view to illustrate a “stair step” arrangement to contact gate electrodes. 
           [0018]      FIG. 15  shows, schematically, three NFETs connected in series. 
           [0019]      FIG. 16  shows schematically two NFETs in series and another NFET connected in parallel with the series connected two NFETs. 
           [0020]      FIG. 17  shows three NFETs connected in parallel. 
           [0021]      FIG. 18  shows an embodiment of the invention wherein PFETs are created and connected in series. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0022]    In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and within which are shown by way of illustration specific embodiments by which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the invention. 
         [0023]    Embodiments of the present invention provide for vertical structures of field effect transistors suitable for NAND NOR, and AOI logic gates. Detailed drawings and description are given for construction of N-channel Field Effect Transistors (NFETs); however, it will be clear that a similar process, with appropriate dopings, will create analogous PFET (P-channel Field Effect Transistors). 
         [0024]    With reference now to  FIG. 1 , a stack  10  comprises a silicon substrate  108 , shown as being doped P−, which forms a substrate for further processing of NFET transistors as will be explained below. It is understood that PFET transistors may be formed above an N− doped region, for example, an N-well in the silicon substrate  108 . Alternating layers of a dielectric material (HfO 2  shown for exemplary purposes) and conducting material suitable for gate electrode material (e.g., metal or polysilicon; “metal” used for exemplary purposes) are stacked above silicon substrate  108 . HfO 2    101 ,  102 ,  103 , and  104  are shown in  FIG. 1  as the dielectric layers. Metal  111  is layered between HfO 2    101  and HfO 2    102 ; Metal  112  is layered between HfO 2    102  and HfO 2    103 . Metal  113  is layered between HfO 2    103  and HfO 2    104 . HfO 2    101  and HfO 2    104  will form gate dielectrics for a first and a third NFET and therefore need to be of appropriate thickness for gate dielectric purposes. HfO 2    102  and HfO 2   103  electrically isolate metal  111  from metal  112  and metal  112  from metal  113 , respectively, and need to be of appropriate thickness for this purpose. 
         [0025]      FIG. 2  shows stack  10  after processing in a semiconductor fabrication facility to produce a vertical structure  100 . Vertical structure  100  is shown as having a “dog bone” shape. A middle area of vertical structure  100  is an area in which NFETs will be created. In the “dog bone” ends of vertical structure  100 , the orthogonal areas (portions) at the ends are for contacting the gate electrodes (metals  111 ,  112 ,  113 ). Although shown where all “dog bone” ends are vertically aligned, vertical structure  100  may have, e.g., lower levels extending further to facilitate contacting as shown in  FIG. 14A  and  FIG. 14B . The relatively wider, orthogonal, portions of the “dog bones” may provide space for dual contacts. Shapes other than “dog bones” are contemplated for dual contacts, for example, an “L” shape having a portion long enough to have a dual contact. An “L” having a shorter portion may be used if only a single contact is allowed in a particular technology. “Dog bone” ends need not be created at both ends of vertical structure  100 . “Dog bones” may not be needed at all if metals  111 ,  112 , and  113  are routed on those metal levels to signal sources desired for logical control (i.e., turning on/off) of the NFETs created. For example, metal  111  (or metal  112 ,  113 ), during processing in creation of vertical stack  100 , may be routed to such a signal source and therefore a “dog bone” and vias to metal  111 ,  112 ,  113  are not required. 
         [0026]      FIG. 3  shows the vertical structure  100  after further deposition of SIO 2    120 , or other suitable dielectric material, to cover vertical structure  100 . A “dog bone end”  320  is depicted. “Dog bone end”  320  is an end of a portion of vertical structure  100  suitable for making one or more contacts, as will be further described with reference to  FIGS. 14A and 14B . 
         [0027]      FIG. 4  shows the vertical structure  100  of  FIG. 3  after etching SiO 2    120  until a top surface of HfO 2    104  is exposed. Holes  121 A and  121 B (generically, “holes  121 ”) are etched in order to expose vertical surfaces of vertical structure  100  for subsequent processing as will be described.  FIG. 4  shows cross section AA which will be used in following figures. Cross section AA cuts through vertical structure  100  and holes  121  as depicted. 
         [0028]      FIG. 5  shows the structure of  FIG. 4  at cross section AA, after conformal deposition of a SiO 2  spacer  130 . 
         [0029]      FIG. 6  shows the structure of  FIG. 5  following an anisotropic etch of SiO 2  spacer  130 . The anisotropic etch bares a top surface of HfO 2    104  and a top surface of P− Si  108 . Source/drain regions  132  ( 132 A,  132 B) are implanted into P− Si  108 . At this stage of the process, source/drain regions  132  are the source/drains of a first NFET (See NFET N 1  in  FIG. 15 ); HfO 2    101  is a gate dielectric of the first NFET; metal  111  is a gate electrode of the first NFET. For NFETs, source/drain regions  132  are also called N+  132  for simplicity. 
         [0030]    Source/drain regions  132 A and  132 B are created by the same implant processing step and are generically called source/drain regions  132 . However, for clarity as to which source/drain region is intended, a suffix “A” is appended to  132  for the “right side” (in the drawing) source/drain region  132 , and a suffix “B” is appended to  132  for the “left side” source/drain region  132 . A similar convention is used hereinafter to designate “left side” and “right side” portions of a particular element. 
         [0031]      FIG. 7  shows the structure of  FIG. 6  with addition of a first epitaxial growth, N+ Epi  133  ( 133 A,  133 B), grown over source/drain regions  132 . Note the “right hand” and “left hand” “A”, “B” suffix convention. N+ Epi  133  has a doping similar to doping of source/drain regions  132 . That is, if source/drain regions  132  are doped “N”, N+ Epi  133  is also doped “N”, with appropriate concentration of dopants. 
         [0032]    While detail is given herein for creation of NFETs, it will be understood that PFETs may be created in a similar manner, for example starting with an N− Nwell in P− Si  108 , P+ implantation forming source/drain regions for a PFET, and P+ epitaxial growth over source/drain regions of the PFET. 
         [0033]      FIG. 8  shows the structure of  FIG. 7  with addition of photoresist  134  and an oxygen implant of suitable energy to create SiO 2    135 A over source/drain region  132 A. Photoresist  134  blocks the oxygen implant from forming a SiO 2    135 B over source/drain region  132 B. SiO 2    135 A electrically isolates source/drain region  132 A from an overlying N+ epi  133 A. Source/drain region  132 B remains in electrical connection with similarly doped overlying N+ epi  133 B. 
         [0034]      FIG. 9  shows the structure of  FIG. 8  with removal of SiO 2  spacer  130  above HfO 2    102 , followed by addition of a conformal deposition of HfO 2  spacer  138 . It is noted that removal of SiO2 spacer  130  may also etch a portion of SiO2  130  below a top surface of N+ Epi  132 ; however, that that occurs, the subsequent conformal deposition of HfO2 spacer  138  will fill in the portion removed. Note that, in an embodiment, this step is skipped, and SiO 2  spacer  130  is left intact. In this embodiment, gate dielectric for the second NFET (N 2  in  FIG. 13 ) will be SiO2 instead of HfO 2 . HfO 2  is a modern high-K dielectric, and steps to provide HfO 2  as gate dielectric for N 2  ( FIG. 15 ) are therefore explained above. 
         [0035]      FIG. 10  shows the structure of  FIG. 9  following an anisotropic etch of HfO 2  spacer  138 . Also, a second epitaxial growth, P− epi  136  ( 136 A,  136 B), is grown over N+ Epi  133  ( 133 A,  133 B). P− epi  136  is suitably doped to serve as a body of an NFET (N 2  in  FIG. 13 ). As with the previous step, this step may be skipped if SiO 2  spacer  130 B is to be used as gate dielectric for N 2  ( FIG. 15 ). 
         [0036]      FIG. 11  shows the structure of  FIG. 10  following growth of a third epitaxial growth, N+ Epi  137  ( 137 A,  137 B), over P− Epi  136 . N+ Epi  137  is grown to a height that extends above a top of HfO 2    104 , and will “bulge” over HfO 2    104  as depicted. A subsequent, fourth epitaxial growth, P− Epi  140  is grown over N+ Epi  137 . P− Epi  140  is grown thick enough to completely cover HfO 2    104  and is suitably doped to serve as a body of an NFET for which HfO 2    104  serves as a gate dielectric. 
         [0037]      FIG. 12  shows the structure of  FIG. 11 , after planarization that removes P− Epi  140  except for a portion of P− Epi  140  above HfO 2    104  and between N+ Epi  137 A and N+ Epi  137 B as shown. 
         [0038]      FIG. 13  shows the structure of  FIG. 12 , including a lined contact  150  and contacts  161  and  162 . Lined contact  150  is created by a silicon etch which etches through N+ Epi  137 A, P− Epi  136 A and N+ Epi  133 A, followed by a SiO 2  etch through SiO 2    135 A to N+  132 A. A SiO 2  deposition leaves SiO 2    151  around the sides and bottom of the hole created by the silicon etch and the SiO 2  etch. Then, an anisotropic etch removes the portion of the SiO 2  deposition at the bottom of the hole, exposing a portion of N+  132 A. A conductive fill  152 , such as doped polysilicon or a metal such as tungsten, fills the hole and makes contact with N+  132 . Conductive fill is electrically isolated from N+ Epi  133 A, P− Epi  136 A, and N+ Epi  137 A by SiO 2    151 . Contacts  161  and  162  are conventional contacts to top surfaces of N+ Epi  137 A and N+ Epi  137 B. 
         [0039]      FIG. 14A  shows a top view of the structure shown in  FIG. 13 . One or more contacts  162  are shown on the top surface of N+ Epi  137 B. In  FIG. 13 , contact  161  was shown “closer to the center of the drawing” than lined contact  150 , and, in an embodiment, contact  161  may be placed in such a position. However, to preserve space, in an embodiment, one or more contacts  161  may be alternated with lined contacts  150  as shown in  FIG. 14A . In  FIGS. 15 ,  16 ,  17 , and  18 , contacts  161  are shown as in  FIG. 13  in order to clearly show electrical connections.  FIG. 14A  also shows one embodiment for electrically connecting to metals  111 ,  112 , and  113 . As shown, the “dog bone” portion of metal  111  extends beyond the “dog bone” portion of metal  112 , which extends beyond the “dog bone” portion of metal  113 . That is, metals  111 ,  112 , and  113  are “stair stepped”. Etching through overlying material exposes the “dog bone” portions for making contacts (dual contacts are shown) to metal  111 ,  112  and  113 . As explained earlier, if metal  112 ,  112 , and/or  113  are routed on those metal levels to a source configured to logically drive the NFET gates created, no “dog bone” or contacts as shown are required.  FIG. 14A  shows “dog bone” ends at only one end of vertical structure  100 . 
         [0040]      FIG. 14B  shows a side view of the structure shown in  FIG. 13 , to more clearly show the “stair step” contacting scheme shown in top view  FIG. 14A . Contact  311  connects metal  111  to a signal  301  on a signal wiring level on a chip featuring the structure shown. Contact  312  connects metal  112  to a signal  302 . Contact  313  connects metal  113  to a signal  303 . Also shown is a “dog bone end”  320 . SiO 2    120  is shown surrounding the structure of  FIG. 14B , and SiO 2    120  is shown in  FIG. 14B  to include a SiO 2  area grown over the SiO 2  shown in  FIG. 4 ; it is well-known to grow SiO 2  over devices for isolation from signal wiring layers. Hole  121 A shows the portion of vertical structure  100  in which FET processing is accomplished. Hole  121 A was also shown in  FIG. 4 . Contacts  311 ,  312 ,  313  are created with conventional etching techniques. 
         [0041]      FIG. 15  shows the structure of  FIG. 13 , including an overlaid schematic of three NFETs (N 1 , N 2 , N 3 ) connected in series, as they would be in a 3-way NAND logic circuit. A drain of N 1  (N+  132 A) is connected through lined contact  150  ( FIG. 13 ) to an output  155 . A source of N 1  (N+  132 B) is connected to a drain of N 2  (N+ Epi  133 B). A source of N 2  (N+ Epi  137 B) is also a drain of N 3 . A source of N 3  (N+ Epi  137 A) is connected to contact  161 , which, as shown, is further connected to Gnd. Contact  162  in  FIG. 15  is not used and may be omitted. 
         [0042]    HfO 2   101  is a gate dielectric of N 1 ; metal  111  is a gate electrode of N 1 . P− Si  108  is a body of N 1 . 
         [0043]    HfO 2  spacer  138 B is a gate dielectric of N 2 . Metal  112  is a gate electrode of N 2 . P− Epi  138 B is a body of N 2 . 
         [0044]    HfO 2   104  is a gate dielectric of N 3 ; metal  113  is a gate electrode of N 3 ; P− Epi  140  ( FIG. 13 ) is a body of N 3 . 
         [0045]      FIG. 16  shows the structure of  FIG. 13  with three NFETs (N 1 , N 2 , N 3 ) connected as NFETs may be in an AOI structure. N 1  and N 2  are connected in series between output  155  and Gnd as shown. N 3  is connected between output  155  and Gnd as shown. 
         [0046]      FIG. 17  shows the structure of  FIG. 13 , further comprising a lined contact  150 B. N 1 , N 2 , and N 3  are connected in parallel between output  155  and Gnd as shown. Lined contact  150 B is created with a timed etch (no etch stop) to extend through N+ epi  137 B, P− Epi  136 B, and partway through N+ Epi  133 B. An SiO 2  lining is deposited in a hole created by the timed etch, and the SiO 2  lining at a bottom portion of the hole is removed in an anisotropic etch, exposing a portion of N+ Epi  133 B at the bottom of the hole. The hole is then filled with a conductive fill  152 , as was done with conductive fill  152  ( FIG. 13 ) in lined contact  150 A. Drains of N 1  and N 2  (N+  132 B, N+ Epi  133 B) are connected to output  155  through lined contact  150 B. A drain of N 3  (N+ Epi  137 A) is connected to output  155  via contact  161 . Sources of N 2  and N 3  (N+  137 B) are connected to Gnd through contact  162 . A source of N 1  (N+  132 A) is connected to Gnd through lined contact  150 A. 
         [0047]    As mentioned earlier, PFETs may be created using the same techniques described in detail for NFETs, only with appropriate dopings.  FIG. 18  shows three PFETs (P 1 , P 2 , P 3 ) connected in series between Vdd and an output  255 . Reference numbers are the same as used for NFETs, only are “200” numbers, rather than “100” numbers, for example HfO 2    201  in  FIG. 18  is analogous to HfO 2    101  in, e.g.,  FIG. 16 . In the case of the HfO 2  levels and metal levels in stack  100 , the HfO 2  levels and metal levels are in fact the same as are shown for the NFET devices. Implants and growth of epi layers, however, are analogous, but doped differently, in order to produce PFETs. 
         [0048]    In  FIG. 18 , a source (P+ Epi  237 A) of P 3  is connected to Vdd at contact  261 . A drain of P 3  (P+ Epi  237 B) is connected to a source of P 2  (also P+ Epi  237 B). A drain of P 2  (P+ Epi  233 B) is connected to a source of P 1  (P+  232 B). A drain of P 1  (P+  232 A) is connected through lined contact  250  to an output  255 . Other PFET connects suitable for NAND CMOS logic gates or AOI logic gates may be connected using the techniques taught with respect to NFETs earlier.