Abstract:
The invention relates to a circuit device, into which a first signal and a second signal are input, wherein a first switching array is provided, by means of which it is determined which of the two signals, is the first to change its state. The circuit device may also have a second switching array, which emits an output signal, which when the first signal first has changed its state, changes its state in reaction to a change in the state of the first signal, and, when the second signal first has changed its state, changes its state in reaction to a change in the state of the first signal.

Description:
CLAIM FOR PRIORITY  
         [0001]    This application claims the benefit of priority to German Application No. 103 20 793.7, filed in the German language on Apr. 30, 2003, the contents of which are hereby incorporated by reference.  
         TECHNICAL FIELD OF THE INVENTION  
         [0002]    The invention relates to a circuit device, in particular a latch or phase detector device according.  
         BACKGROUND OF THE INVENTION  
         [0003]    Conventional latch devices are for instance used in semi-conductor components (such as memory components, for instance DRAMs (DRAM=Dynamic Random Access Memory and/or Dynamic Read/Write Memory)) for the storage and/or interim storage of data, which can then be output again, for instance synchronously with a clock pulse (clk signal) used on the semi-conductor component.  
           [0004]    State-of-the-art latch devices may for instance consist of two transfer gates and four inverters.  
           [0005]    The input of the first transfer gate is connected to a data-input line, by means of which the data to be latched (by means of a corresponding data-input signal (data signal)) is input into the latch device. A first control connection of the first transfer gate is connected to a (first) clock line on which the clock pulse (clk signal) is present, and a further—inverse—control connection of the first transfer gate to a (further) clock line, on which a clock pulse (bclk signal), inverse to the clock pulse (clk signal) is present.  
           [0006]    The output of the first transfer gate is connected to the input of the first inverter. The output of the first inverter is connected to the input of the second transfer gate, and to the input of the second inverter, of which the output is back connected to the input of the first inverter.  
           [0007]    The (first) control connection of the second transfer gate is—correspondingly inverse as with the first transfer gate—connected to the above further inverse clock line (on which—as described above—the inverse clock pulse (bclk signal) is present), and the (further)—inverse—control connection of the second transfer gate is—again correspondingly inverse to the first transfer gate—connected to the first clock line (where —as described above—the clock pulse (clk signal) is present).  
           [0008]    The output of the second transfer gate is connected to the input of the third inverter. The output of the third inverter is connected to the input of the fourth inverter, of which the output is back connected to the input of the third inverter, as well as to a data output line, by means of which the data—in latched form—that has been input into the latch device (and/or the above data-input line) can be output again synchronously with the clock pulse (clk signal)(by means of a corresponding data output signal (ldata signal)).  
           [0009]    The data to be input into the latch device (data signal) must have been present in a stable state on the data in-put line for a predetermined time ahead of a corresponding (e.g. positive) flank of the clock pulse (clk signal) (and/or of a corresponding (e.g. negative) flank of the inverse clock pulse (bclk signal)), (the so-called “set-up” time (T setup ) to ensure fault-free latching of the data.  
           [0010]    In addition, to ensure fault-free latching of the data, it must also have been present in a stable state up to a pre-determined time after the corresponding (positive) flank of the clock pulse (clk signal) (and/or of the corresponding (negative) flank of the inverse clock pulse (bclk signal)) (the so-called “hold” time (T hold )).  
           [0011]    The “set-up” and “hold” times may—in total—be of a duration of ca. 50 to 200 picoseconds, which may be problematic, particularly at high frequencies and/or for the “critical path” that determines the efficiency of all the semi-conductor components.  
           [0012]    The above “set-up” and “hold” times could be reduced if it could be ascertained that the clock—and the inverse clock pulses (clk and bclk signals)—were completely complementary to one another (and that they would not change their states at times minimally varying from each other, from “high logic” to “low logic” (negative flank) and correspondingly inverted from “low logic” to “high logic” (positive flank).  
           [0013]    This goal is however not at all, or only partly (and unsatisfactorily) attainable with conventional latch devices, e.g. due to inaccuracies occurring in corresponding semi-conductor components during the manufacturing process.  
         SUMMARY OF THE INVENTION  
         [0014]    The intention relates to a circuit device, in particular a latch and phase detector device, in particular a latch device with which the “set-up” and/or “hold” time may be reduced in comparison with conventional latch devices. According to one embodiment of the invention, a circuit device is provided into which a first signal (data) and a second signal (clk) are input, wherein a first switching array is provided, with which it is determined which of the two signals (data, clk) is the first to change its state. Advantageously, furthermore, a second switching array provided, which emits an output signal (out, bout), which when the first signal (data) first changes its state, changes its state in reaction to a change in the state of the second signal (clk), and when the second signal (clk) first changes its state, changes its state in reaction to a change in the state of the first signal (data). 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    The invention is more closely described below with by use of exemplary embodiments and the accompanying drawings. In the drawings:  
         [0016]    [0016]FIG. 1 shows a schematic representation of a circuit device according to an embodiment example of the present invention.  
         [0017]    [0017]FIG. 2 a  shows a signal timing diagram to illustrate the chronological sequence of state changes of signals occurring in the circuit arrangement as in FIG. 1, where the data-input signal changes its state first, and is then followed by the clock pulse.  
         [0018]    [0018]FIG. 2 b  shows a signal timing diagram to illustrate the chronological sequence of state changes of signals occurring in the circuit arrangement as in FIG. 1, where the clock pulse changes its state first, and is then followed by the data-input signal.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]    [0019]FIG. 1 shows a schematic representation of a device  1  according to an embodiment example of the present invention.  
         [0020]    The circuit device  1  is incorporated into a semi-conductor component—e.g. based on CMOS technology—for instance a logic and/or memory component, such as a DRAM (DRAM=Dynamic Random Access Memory and/or dynamic read/write memory), in particular a DRAM memory component with double data rate (DDR-DRAM).  
         [0021]    The circuit device  1  may then for instance also be used correspondingly similar to conventional latch devices for the storage and/or interim storage of data in chronological relation to a clock pulse (clk signal) used in the semi-conductor component, and then to re-emit it.  
         [0022]    As FIG. 1 shows, the circuit device  1  has essentially three circuit sections,  1   a ,  1   b ,  1   c.    
         [0023]    The first and third circuit sections  1   a ,  1   c  are each formed by a—correspondingly connected—RS flip-flop  2   a ,  2   b.    
         [0024]    As FIG. 1 shows, in the present embodiment example the first RS flip-flop  2   a  has two NAND gates  3   a ,  3   b  (here: two 2-NAND gates  3   a ,  3   b ), and the second RS flip-flop  2   b  two NAND gates  4   a ,  4   b  (here: two 2-NAND gates  4   a ,  4   b ). In alternative embodiment examples not shown here, correspondingly inverse NOR gate-based RS flip-flop may e.g. also be used in the place of NAND gate-based RS flip-flop  2   a ,  2   b  (where required with the alternative use of a clock pulse (bclk signal), inverse in relation to the above clock pulse (clk signal).  
         [0025]    As seen in FIG. 1, the embodiment example shown here has a first input of the first NAND gate  3   a  of the first RS flip-flop  2   a  connected to a data input line  5 , with which the data to be latched is input into the circuit device  1  (by means of a corresponding data-input signal (data signal)).  
         [0026]    A first input of the second NAND gate  3   b  of the first RS flip-flop  2   a  is connected—by means of a line  6 —to a clock line  7 , through which the above clock pulse (clk signal) is input into the circuit device  1 .  
         [0027]    The output of the first NAND gate  3   a  of the first RS flip-flop  2   a  is back connected via a line  8 , together with a line  9  connected to it, to a second input of the second NAND gate  3   b  of the first RS flip-flop  2   a  so that a signal (dc signal) emitted at an output of the first NAND gate  3   a  of the first RS flip-flop  2   a , is fed to the second input of the second NAND gate  3   b  of the first RS flip-flop  2   a ).  
         [0028]    Correspondingly reversed, the output of the second NAND gate  3   b  of the first RS flip-flop  2   a —via a line  10 , and a line  11  connected to it—is back-connected to a second input of the first NAND gate  3   a  of the first RS flip-flop  2   a  (so that a signal (cd signal) emitted at the output of the second NAND gate  3   b  of the first RS flip-flop  2   a , is fed to the second input of the first NAND gate  3   a  of the first RS flip-flop  2   a ).  
         [0029]    As further shown in FIG. 1, the circuit device  1 —at the above second circuit section  1   b —has four further NAND gates  12   a ,  12   b ,  12   b ,  12   c  (or alternatively e.g.—correspondingly inverse—corresponding NOR gates), namely two 2-NAND gates  12   a ,  12   b , and two 3-NAND gates  12   c ,  12   d.    
         [0030]    The signal (dc signal) emitted at the output of the first NAND gate  3   a  of the first RS flip-flop  2   a  of the first circuit section la is fed—via line  8 —to a first input of the first NAND gate  12   a  of the second circuit section  1   b , and the signal (cd signal) emitted at the output of the second NAND gate  3   b  of the first RS flip-flop  2   a  of the first circuit section la is fed—via line  10 —to a first input of the second NAND gate  12   b  of the second circuit section  1   b.    
         [0031]    As further shown in FIG. 1, a signal (on signal) emitted at the output of the first NAND gate  12   a  of the second circuit section  1   b  is fed via a line  13  to a first input of the third NAND gate  12   c  (here: of the 3-NAND gate  12   c ) of the second circuit section.  
         [0032]    In corresponding fashion, a signal (bon signal) emitted at the output of the second NAND gate  12   b  of the second circuit section  1   b  is fed via a line  14  to a first input of the fourth NAND gate  12   d  (here: of the 3-NAND gate  12   d ) of the second circuit section  1   b.    
         [0033]    The clock pulse (clk signal) is further fed to second input of the third NAND gate  12   c  of the second circuit section  1   b , and/or to a second input of the fourth NAND gate  12   d  of the second circuit section  1   b —via a line  15 , which is connected to the clock-line  7  and via the lines  16  and/or  17 , connected to line  15 .  
         [0034]    The signal (en signal) emitted at the output of the third NAND gate  12   c  of the second circuit section is fed to a second input of the first NAND gate  12   a  of the second circuit section  1   b  via a line  18 , and a line  20  connected to it, and fed via a line  19 —connected to line  18 —to a third input of the fourth NAND gate  12   d  of the second circuit section  1   b.    
         [0035]    Correspondingly reversed, the signal (ben signal) emitted at the output of the fourth NAND gate  12   d  of the second circuit section  1   b  is fed to a second input of the second NAND gate  12   b  of the second circuit section lb via a line  21  and a line  22  connected to it, and—via a line  23  connected to line  21 —to a third input of the third NAND gate  12   c  of the second circuit section  1   b.    
         [0036]    As further shown in FIG. 1, the signal (en signal) emitted at the output of the third NAND gate  12   c  of the second circuit section  1   b  is fed—via the line  18 , and a line  24  connected to it—to a first input of the first NAND gate  4   a  of the third circuit section  1   c  (i.e. the first input of the second RS flip-flop  2   b ).  
         [0037]    Correspondingly the signal (ben signal) emitted at the output of the fourth NAND gate  12   d  of the second circuit section  1   b  is fed—via the line  21 , and a line  25  connected to it—to a first input of the second NAND gate  4   b  of the third circuit section lc (i.e. the second input of the second RS flip-flop  2   b ).  
         [0038]    The output of the first NAND gate  4   a  of the third circuit section  1   c  (and/or of the second RS flip-flop  2   b ) is back connected via a line  26 , and a line  27  connected to it, to a second input of the second NAND gate  4   b  of the second RS flip-flop  2   b  (so that a (data output) signal (out signal) emitted at the output of the first NAND gate  4   a  of the second RS flip-flop  2   b  is fed to the second input of the second NAND gate  4   b  of the second RS flip-flop  2   b ).  
         [0039]    Correspondingly reversed, the output of the second NAND gate  4   b  of the third circuit section  1   c  (and/or the second RS flip-flop  2   b ) is back connected—via a line  28 , and a line  29  connected to it—to a second input of the first NAND gate  4   a  of the second RS flip-flop  2   b  (so that a (data output) signal (bout signal) emitted at the output of the second NAND gate  4   b  of the second RS flip-flop  2   b  is fed to the second input of the first NAND gate  4   a  of the second RS flip-flop  2   b ).  
         [0040]    As further shown in FIG. 1, the data output signal (out signal) emitted at the output of the first NAND gate  4   a  of the second RS flip-flop  2   b  is fed via the above line  26 , and a data output-line  30  connected to it—to a (first) output of the circuit device  1 , and the (further, inverse) data output signal (bout signal) emitted at the output of the second NAND gate  4   b  of the second RS flip-flop  2   b  is fed—via the above line  28 , and a (further, inverse) data output-line  31  connected to it—to a (further, inverse) output of the circuit device  1 .  
         [0041]    Below, the operation of the circuit device  1  is more closely described with reference to FIG. 1 as well as to the signal timing diagram shown in FIG. 2 a  and  2   b , and in particular i) for the case where first the data-input signal (data signal), and then the clock pulse (clk signal) change their states (cf. FIG. 2 a ), and ii) for the case where first the clock pulse (clk signal), and then the data-input signal (data signal) change their states (cf. FIG. 2 b ).  
         [0042]    When—referring to FIG. 2 a —the data-input signal (data signal) present at the data input line  5  and fed to the first input of the first NAND gate  3   a  of the first RS flip flop  2   a , changes its state from “high logic” to “low logic” (while the clock pulse (clk signal) present at the clock-line  7  is in a “low logic” state), the signal (dc signal) emitted at the output of the first NAND gate  3   a  of the first RS flip flop  2   a  changes its state from “high logic” to “low logic” (whereas the signal (cd signal) emitted at the output of the second NAND gate  3   b  of the first RS flip flop  2   a  remains in a “high logic” state regardless of the state of the clock pulse (clk signal)).  
         [0043]    As a result of the change in the state of the dc signal, the signal (on signal) emitted at the output of the first NAND gate  12   a  of the second circuit section lb changes its state from “low logic” to “high logic”—the bon signal remains “low logic”.  
         [0044]    Due to the initially still “low logic” state of the clock pulse (clk signal) present at the second input of the third NAND gate  12   c  of the second circuit section  1   b , the signal  1  (en signal) emitted at the output of the third NAND gate  12   c  of the second circuit section  1   b ) at first remains “high logic”.  
         [0045]    When the data input signal (data-signal) then—e.g. a time period of Δt 2  after the clock signal (clk-signal)—changes its state from “low logic” to “high logic”, the signal (ben-signal) emitted at the output of the fourth NAND gate  12   d  of the second circuit section  1   b  changes its state from “high logic” to “low logic”.  
         [0046]    This change of the signal (en signal)—fed to the first input of the first NAND gate  4   a  of the second RS flip flop  2   b , from “high logic” to “low logic”, causes the data output signal (out signal) emitted at the output of the first NAND gate  4   a  of the second RS flip flop  2   b  —and therewith the (inverse) data output signal (bout signal) present at the (inverse) first output of the circuit device  1 —to change from a “low logic” to a “high logic” state. With the aid of the above (en signal, and/or ben signal) emitted at the outputs of the 3-NAND gates  12   c ,  12   d  of the second circuit section  1   b , and back-connected to the first and second 2-NAND gate signals  12   a ,  12   b  of the second circuit section, the first and/or second 2-NAND gate  12   a ,  12   b  are correspondingly blocked and/or deactivated (and only later activated or unblocked again), whereby it is ensured that the data output signal (out signal) retains its “high logic” state, at least until the next negative flank of the clock pulse (clk signal).  
         [0047]    In FIG. 2 b  a signal timing diagram is shown to illustrate the chronological sequence of the state changes of the signals occurring in the circuit device  1  as shown in FIG. 1, for the case where first the clock pulse (clk signal), and then the data input signal (data signal) change their states.  
         [0048]    When, according to FIG. 2 b , the clock pulse (clk signal)—present as described above at the clock line  7  and fed to the first input of the second NAND gate  3   b  of the first RS flip flop  2   a  —changes its state from “low logic” to “high logic” (at the continued “low logic” state of the data-input signal (data signal) present at the data input line  5 ), the signal (cd signal) emitted at the output of the second NAND gate  3   b  of the first RS flip flop  2   a  changes its state from “high logic” to “low logic” (whereas the signal (dc signal) emitted at the output of the first NAND gate  3   a  of the first RS flip flop  2   a  —irrespective of the state of the clock pulse (clk signal)—remains in a “high logic” state).  
         [0049]    As a result of the state change of the cd signal, the signal (bon signal) emitted at the output of the second NAND gate  12   b  of the second circuit section lb, changes its state from “low logic” to “high logic”; the on signal remains “low logic”.  
         [0050]    Due to the at first still “low logic” state of the data-input signal (data signal) present at the data input line  5 , the signal (ben signal) emitted at the output of the fourth NAND gate  12   d  of the second circuit section  1   b  at first remains in a “high logic” state.  
         [0051]    When the data-input signal (data signal) then changes its state from “low logic” to “high logic”, then—e.g. after a time period of Δt 2  after the clock pulse (clk signal). —the signal (ben signal) emitted at the output of the fourth NAND gate  12   d  of the second circuit section  1   b , changes its state from “high logic” to “low logic”.  
         [0052]    The changes in this signal (ben signal)—fed to the first input of the second NAND gate  4   b  of the second RS flip flop  2   b  —from “high logic” to “low logic” —cause the (inverse) data output signal (bout signal) emitted at the output of the second NAND gate  4   b  of the second RS flip flop  2   b  —and thereby at the (inverse) output of the circuit device  1 —to change over from a “low logic” to a “high logic” state.  
         [0053]    With the aid of the signals (en signal, and/or ben signal) emitted at the above outputs of the 3-NAND gate  12   c ,  12   d  of the second circuit section  1   b , and back-connected to the first and second 2-NAND gate  12   a ,  12   b , the first and/or second 2-NAND gate  12   a ,  12   b  of the second circuit section  1   b  is correspondingly blocked and/or deactivated (and later reactivated or unblocked again), whereby it is ensured that the data output signal (bout signal) maintains its “high logic” state at least until the next, negative flank of the clock pulse (clk signal).  
         [0054]    In the circuit device  1  shown in FIG. 1, the first circuit section  1   a  (here: the RS flip-flop  2   a ) essentially serves to determine, which of the two input signals fed to the circuit device  1 —the first data-input signal (data signal) fed to the NAND gate  3   a , or the clock pulse (clk signal) fed to the second NAND gate  3   b —is the first to change its state (“evaluation”).  
         [0055]    This takes place in that—as described above—the output of that NAND gate  3   a ,  3   b , to which that input signal (data-input signal (data signal), or clock pulse (clk signal)), which first changes its state (here: from “low logic” to “high logic”) is fed, changes to a “low logic” state (dc signal and/or cd signal), whereby the complementary output (cd signal and/or dc signal) is prevented from also changing to a “low logic” state.  
         [0056]    As only the two outputs of the first circuit section la (i.e. the output of the first NAND gate  3   a , or the output of the second NAND gate  3   b ) can find themselves in a “low logic” state, neither the output of the first NAND gate  12   a  of the second circuit section  1   b  (i.e. the on signal), nor the output of the second NAND gate  12   b  of the second circuit section  1   b  (i.e. the bon signal) can be in a “high logic” state in each case, while the clock pulse (clk signal) is “low logic”.  
         [0057]    After the state of the clock pulse (clk signal) has changed from “low logic” to “high logic”, the second circuit section  1   b  (and/or more correctly of that of the 3-NAND gates  12   c ,  12   d ) accordingly behaves like the first circuit section la (and/or the first RS flip-flop  2   a  formed by the 2-NAND gates  3   a ,  3   b ): the output of that 3-NAND gate  12   c ,  12   db , to which that input signal (on signal, or bon signal) is fed, which is the first to change its state, accordingly changes its state in such a way, that the complementary output in each case is also prevented from changing its state in a corresponding way (i.e. an “evaluation” —correspondingly similar to that in the first circuit section  1   a —takes place to determine which of the two signals (on signal, or bon signal) fed to the 3-NAND gates  12   c ,  12   d  is the first to change its state).  
         [0058]    In accordance with the above embodiments, and as with conventional latch devices, the circuit device  1  may be used for the permanent and/or temporary storage of data fed—with the aid of the data-input signal (data signal)—to the circuit device  1 , synchronously and/or in chronological relation to the clock pulse (clk signal) used in the semi-conductor component—and to re-emit it again.  
         [0059]    In this way the “set-up” and/or “hold” times (and/or times corresponding to these times)—that need to be maintained for the fault-free operation of the circuit device  1 —are kept substantially shorter in the circuit device  1  shown in FIG. 1, than in conventional latch devices (e.g. shorter than 50 or 40, in particular shorter than 30 picoseconds), and are essentially dependent on the switching resolution time of the first RS flip flop  2   a  (that may e.g. amount to 10-20 picoseconds).  
         [0060]    Apart from being able to be used as a latch device (and/or in addition to it), the circuit device  1  shown in FIG. 1 can e.g. also be used as a phase detector device, in particular to determine whether a first signal input at line  5 —corresponding to the above data input signal (data signal)—in terms of phase—precedes or follows a second signal corresponding to the above clock pulse and input at line  7 —(whereby line  5  then takes over the function of a first signal input line, and line  7  the function of a further signal input line).  
         [0061]    Reference Numbers  
         [0062]    [0062] 1  circuit device  
         [0063]    [0063] 1   a  circuit section  
         [0064]    [0064] 1   b  circuit section  
         [0065]    [0065] 1   c  circuit section  
         [0066]    [0066] 2   a  rs flip-flop  
         [0067]    [0067] 2   b  rs flip-flop  
         [0068]    [0068] 3   a  nand gate  
         [0069]    [0069] 3   b  nand gate  
         [0070]    [0070] 4   a  nand gate  
         [0071]    [0071] 4   b  nand gate  
         [0072]    [0072] 5  data input line  
         [0073]    [0073] 6  line  
         [0074]    [0074] 7  clock pulse line  
         [0075]    [0075] 8  line  
         [0076]    [0076] 9  line  
         [0077]    [0077] 10  line  
         [0078]    [0078] 11  line  
         [0079]    [0079] 12   a  nand gate  
         [0080]    [0080] 12   b  nand gate  
         [0081]    [0081] 12   c  nand gate  
         [0082]    [0082] 12   d  nand gate  
         [0083]    [0083] 13  line  
         [0084]    [0084] 14  line  
         [0085]    [0085] 15  line  
         [0086]    [0086] 16  line  
         [0087]    [0087] 17  line  
         [0088]    [0088] 18  line  
         [0089]    [0089] 19  line  
         [0090]    [0090] 20  line  
         [0091]    [0091] 21  line  
         [0092]    [0092] 22  line  
         [0093]    [0093] 23  line  
         [0094]    [0094] 24  line  
         [0095]    [0095] 25  line  
         [0096]    [0096] 26  line  
         [0097]    [0097] 27  line  
         [0098]    [0098] 28  line  
         [0099]    [0099] 29  line  
         [0100]    [0100] 30  data output line  
         [0101]    [0101] 31  data output line