Abstract:
A timing controller (TCON) for use in flat panel displays to dynamically tune the display parameters thereof. The TCON comprises a bus master coupled to a bus and a register for configuring the register with a default value, and a bus slave coupled to an external interface for input of a custom value to configure the register, thereby rendering display parameters dynamically tunable.

Description:
BACKGROUND  
       [0001]     The invention relates to a timing controller for use in a flat panel display, capable of tuning display parameters dynamically.  
         [0002]     Application Specific Integrated Circuit (ASIC) technology is widely applied in various system integrations. The major component controlling Liquid Crystal Display (LCD), a chip based on ASIC technology, is referred to as a timing controller (TCON).  
         [0003]      FIG. 1   a  is an architecture diagram of a conventional liquid crystal display. The liquid crystal display comprises a display panel  116  for image display, and a timing controller  100  controlling the display panel  116 . Digital input DATA_IN comprising image data and control signals is input externally to the timing controller  100 , and through data transformation therein, visual output is displayed on display panel  116  via row driver  112  and column driver  114 . While architecture varies between vendors, however, common display parameters are essential, comprising fast response time table, digital gamma table and temperature compensation table, configured to characterize relationships between the image data and visual output. Default parameters are predetermined at the manufacturing stage, and are stored in memory devices.  
         [0004]      FIG. 1   b  shows a timing controller  100  comprising a register  102 , a bus master  104 , and a bus  108 . The default parameters are stored in a memory  106  coupled to the bus  108 . The bus  108  conforms to standards such as Inter-IC bus ( 12 C) or Serial Peripheral Interface (SPI). The bus master  104  accesses memory  106  via bus  108  to read the default parameters therein, for storage in the register  102 . Based on the parameters stored in register  102 , the timing controller  100  transforms the image data into visual output for display on display panel  116  through control of row driver  112  and column driver  114 .  
         [0005]      FIG. 1   c  is a flowchart of a conventional display process. First in step S 110 , system power is switched on. In step S 120 , the bus master  104  reads default parameters from the memory  106  to initialize the timing controller  100 . Thereafter, in step S 130 , the initialized timing controller  100  transforms the digital input DATA_IN into visual output for display on display panel  116  via control of row driver  112  and column driver  114 .  
         [0006]     A timing controller is so uniquely manufactured that it is not applicable in LCDs having varied specifications. In addition, since parameters are predetermined and set in the memory  106  at the manufacturing stage, it is difficult to tune the parameters when necessary. Digital input DATA_IN may be adjusted to fine tune the visual output, however, the quality of adjusted digital input DATA_IN is reduced during the transformation. Therefore it is desirable to omit the effect of parameters or render the parameters dynamically tunable.  
       SUMMARY  
       [0007]     An embodiment provides a timing controller for use in a flat panel display. The timing controller comprises a register, a bus, a bus master and a bus slave. Parameters required for display are stored in the register. Custom parameters are input externally via the bus. Default parameters are written to the flat panel display at power-on by a bus master. At least one custom parameter is received by the bus slave via the bus and written to the register for display.  
         [0008]     The timing controller further comprises a memory coupled to the bus, storing the default parameters. The memory is an Electrically Erasable Programmable Read Only Memory (EEPROM) or a Flash ROM. The timing controller further comprises a switch coupled to the memory and the bus, and the switch is controlled by the bus slave. When a command is delivered from the external device to the bus slave, the bus slave activates the switch to provide the external device with access to the memory.  
         [0009]     Another embodiment provides a flat panel display comprising a timing controller described, and a panel. The panel is coupled to the timing controller for display of the processed image data output therefrom.  
         [0010]     A further embodiment provides an electronic device comprising a flat panel display described, and a power supply. The power supply is coupled to the flat panel display for supplying power needed by the electronic device. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     The following detailed description, given by way of example and not intended to limit the invention solely to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which:  
         [0012]      FIG. 1   a  shows the architecture of a conventional flat panel display;  
         [0013]      FIG. 1   b  shows the architecture of the internal interface of the conventional flat panel display;  
         [0014]      FIG. 1   c  is a flowchart of a conventional control method;  
         [0015]      FIG. 2   a  shows an embodiment of a flat panel display;  
         [0016]      FIG. 2   b  shows an embodiment of the internal interface of the flat panel display in  FIG. 2   a;    
         [0017]      FIG. 2   c  shows an embodiment of a control method; and  
         [0018]      FIG. 3  shows an embodiment of an electronic device. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]     A detailed description of the present invention is provided in the following.  
         [0020]      FIG. 2   a  shows an embodiment of the flat panel display comprising the bus master  104 , the memory  106 , the row driver  112 , the column driver  114 , and the display panel  116 . Here a timing controller  200  replaces the timing controller  100  applied in the conventional display of  FIG. 1   a , comprising a bus slave  202  controlling external data transfer. The timing controller  200  receives digital input DATA_IN, transforms the input to visual output based on parameters, and displays the visual output on the display panel  116  via control of row driver  112  and column driver  114 .  
         [0021]      FIG. 2   b  is an embodiment of the internal interface of the flat panel display in  FIG. 2   a . The bus master  104  reads the default parameters in the memory  106  via the bus  108  after the flat panel display is powered on, and writes to the register  102 . Thereafter, the bus master  104  can be disabled, being no longer necessary. The bus  108  connects the bus slave  202 , and comprises an external interface for an external device  204 . When the external device  204 , comprising custom parameters, is connected, the custom parameters are transferred through the bus  108  and the bus slave  202 , to the register  102  for display.  
         [0022]     The bus  108  can comply with standards, such as system management bus (SMBUS), Inter-IC bus ( 12 C) or Serial Peripheral Interface (SPI). The memory  106  can be EEPROM or FLASH. The parameters comprise a digital gamma table compensating and correcting brightness, a fast response table accelerating response time, and a temperature compensation table correcting environmental temperature effects. The external device  204  can be a PDA or a computer capable of transferring data via the bus  108 .  
         [0023]     The external device  204  can input custom parameters to the timing controller  200 , and deliver specific control signals to the bus slave  202 . For example, if gamma correction is undesired for previously corrected digital input DATA_IN, the external device  204  delivers a control signal to disable the digital gamma table in the timing controller  200 . In some cases, the bus slave  202  comprises a switch  206  controlling the bus  108  between the memory  106  and external device  204 . The default state of the switch  206  is off, thus only the bus master  104  can access the memory  106 . When the external device  204  is connected to the bus  108  and delivers a specific control signal, the bus slave  202  switches the switch  206  on in response to the control signal, such that data in the memory  106  is accessible to the external device  204  for various applications.  
         [0024]      FIG. 2   c  is a flowchart of the control process. In step S 210 , the system is powered on. In step S 220 , default parameters in the memory  106  are read and written to the register  102 , for display, by the bus master  104 . Once default parameters are completely read, the bus master  104  is disabled. Thereafter in step S 250 , the display panel  116  is activated under the control of timing controller  200 , and displays based on the parameters in register  102 . Unlike the conventional method, an external interface is provided in this embodiment, such that an external device can be connected to control the flat panel display. In step S 230 , the external device  204  is coupled to bus  108 , and transfers custom parameters to the bus slave  202 . In step S 240 , the bus slave  202  acts in response to the external device  204  to write the custom parameters to the register  102 , overwriting the default parameters as configured in step S 220 . Afterwards, in step S 250 , the timing controller  200  transforms the digital input DATA_IN into visual output, and drives the display panel  116 , via row driver  112  and column driver  114  to display. In addition, a switch  206  with default state off, is switched on in response to a control signal delivered from the external device  204  to the bus slave  202 , such that the external device  204  is able to access data in the memory  106  for further application.  
         [0025]      FIG. 3  is an embodiment of an electronic device  300  comprising the flat panel display described, and a power management module  118  providing DC voltage to the electronic device in response to control of the timing controller  200 . The electronic device  300  can be a pocket PC or cell phone with corresponding components known in the art, therefore detailed descriptions are not provided herein.  
         [0026]     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. Rather, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.