Abstract:
A method is disclosed for applying a first voltage to a back plate of a memory capacitor of a pixel to discharge the memory capacitor, pre-charging the memory capacitor in the pixel by applying the first voltage to a source of a pre-charge transistor while applying the first voltage to the back plate of the memory capacitor, and applying a second voltage to the back plate of the memory capacitor and the source of the pre-charge transistor, wherein the second voltage is at a higher potential than the first voltage to generate a negative gate-to-source voltage in the pre-charge transistor.

Description:
REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of U.S. Provisional Application No. 60/666,124, filed on Mar. 28, 2005. 
    
    
     TECHNICAL FIELD 
     The present invention relates generally to an image sensor and, more particularly, to a pixel structure used in an image sensor. 
     BACKGROUND 
     Solid-state image sensors have found widespread use in camera systems. The solid-state imager sensors in some camera systems are composed of a matrix of photosensitive elements in series with switching and amplifying elements. The photosensitive sensitive elements may be, for example, photoreceptors, photo-diodes, phototransistors, charge-coupled device (CCD) gate, or alike. Each photosensitive element receives an image of a portion of a scene being imaged. A photosensitive element along with its accompanying electronics is called a picture element or pixel. The image obtaining photosensitive elements produce an electrical signal indicative of the light intensity of the image. The electrical signal of a photosensitive element is typically a current, which is proportional to the amount of electromagnetic radiation (light) falling onto that photosensitive element. 
     Of the image sensors implemented in a complementary metal-oxide-semiconductor (CMOS)- or MOS-technology, image sensors with passive pixels and image sensors with active pixels are distinguished. The difference between these two types of pixel structures is that an active pixel amplifies the charge that is collect on its photosensitive element. A passive pixel does not perform signal amplification and requires a charge sensitive amplifier that is not integrated in the pixel. 
       FIG. 1A  illustrates one embodiment of a conventional pixel structure used within a synchronous shutter image sensor. A synchronous shutter image sensor is used to detect the signal of all the pixels within the array at (approximately) the same time. This is in contrast to an asynchronous shutter image sensor that may be implemented with a 3T (three transistor) or 4T (four transistor) pixel structure that does not include a sample and hold stage. Such an asynchronous shutter image sensor outputs the state of a pixel at the moment of read out. This gives movement artifacts because every pixel in the array is not sensing a scene at the same moment. 
     The pixel structure of  FIG. 1A  that is used in a synchronous shutter image sensor includes a light detecting stage and a sample and hold stage. The light detecting stage includes a photodiode, a reset transistor and a reset buffer (e.g., a unity gain amplifier). The sample and hold stage includes a sample transistor, one or more memory capacitors (represented by the capacitor C in  FIG. 1A ), a sample buffer and a multiplexer, i.e., switch or select transistor coupled to a column output of the pixel array. 
       FIG. 1B  illustrates one conventional circuit configuration of the synchronous pixel of  FIG. 1A . The reset transistor of the light detecting stage is used to reset the pixel to a high value, and then the voltage on the gate of the source follower transistor M 1  starts dropping due to the photocurrent generated in the photodiode. The source follower transistor M 1  operates as a unity gain amplifier to buffer the signal from the photodiode. The sample and hold (S&amp;H) stage of  FIG. 1B  “sample” loads the voltage signal of source follower transistor M 1 , through the sample transistor, on the memory capacitor (Cmem). The voltage signal from the source follower transistor MI will remain on the memory capacitor when the sample transistor is turned off. 
     Before that, however, the switch, or pre-charge, transistor briefly unloads the Cmem capacitor. The voltage (Vmem) applied to the back plate of Cmem may be a fixed voltage, but in practice, a varying voltage for Vmem may help to shift the voltage on the memory node, so as to drive the source follower transistor M 2  in a more suitable regime. A potential problem with the pixel structure illustrated in  FIG. 1B  is with respect to current leakage that may cause a loss of stored information. In particular, the sample capacitor Cmem charge may leak to ground (GND) through the pre-charge transistor. For the pixel shown in  FIG. 1B , when the pre-charge transistor is off, this means that the gate of the pre-charge transistor is at logical “0” (e.g., GND) and the gate-source voltage (V GS ) of the pre-charge transistor is zero. A CMOS process, utilizing metal-oxide-semiconductor field-effect-transistors (MOSFET), is typically used to implement pixel structures currently used in image sensors. With deep submicron CMOS technologies, the MOSFET drain current at V GS =0 is not really zero and, therefore, a significant current leakage (I off ) can occur when the pre-charge transistor is off that results in the memorized voltage on the sample, or memory, capacitor Cmem leaking away. Such leakage current I off  results in a loss of the stored information with even fA leakage potentially affecting the signal that is output to the column of the pixel array. As such, the pixel structure of  FIG. 1B  may not optimal for long (e.g., a fraction of a second or longer) memory times. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which: 
         FIG. 1A  illustrates one embodiment of a conventional pixel structure used within a synchronous shutter image sensor. 
         FIG. 1B  illustrates one conventional circuit configuration of the synchronous pixel of  FIG. 1A . 
         FIG. 2  illustrates an image sensor including a pixel according to one embodiment of the present invention. 
         FIG. 3  illustrates a pixel structure according to one embodiment of the present invention. 
         FIG. 4  is a timing diagram illustrating the timing corresponding to the operation of the pixel structure of  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION 
     A pixel structure having reduced leakage is described. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques are not shown in detail or are shown in block diagram form in order to avoid unnecessarily obscuring an understanding of this description. 
     Reference in the description to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment. Any of the signals provided over various buses described herein may be time multiplexed with other signals and provided over one or more common buses. Additionally, the interconnection between circuit components or blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be one or more single signal lines, and each of the single signal lines may alternatively be buses. 
       FIG. 2  illustrates one embodiment of an image sensor implementing the methods and apparatus described herein. Image sensor  1000  includes an imaging core  1010  and components associated with the operation of the imaging core. The imaging core  1010  includes a pixel matrix  1020  having an array of pixels (e.g., pixel  300 ) and the corresponding driving and sensing circuitry for the pixel matrix  1020 . The driving and sensing circuitry may include: one or more scanning registers  1035 ,  1030  in the X- and Y-direction in the form of shift registers or addressing registers; buffers/line drivers for the long reset and select lines; column amplifiers  1040  that may also contain fixed pattern noise (FPN) cancellation and double sampling circuitry; and analog multiplexer (mux)  1045  coupled to an output bus  1046 . FPN has the effect that there is non-uniformity in the response of the pixels in the array. Correction of this non-uniformity needs some type of calibration, for example, by multiplying or adding/subtracting the pixel&#39;s signals with a correction amount that is pixel dependent. Circuits and methods to cancel FPN may be referred to as correlated double sampling or offset compensation and are known in the art; accordingly, a detailed description is not provided. 
     The pixel matrix  1020  may be arranged in N rows of pixels by N columns of pixels (with N≧1), with each pixel (e.g., pixel  300 ) is composed of at least a photosensitive element and a readout switch (not shown). A pixel matrix is known in the art; accordingly, a more detailed description is not provided. 
     The Y-addressing scan register(s)  1030  addresses all pixels of a row (e.g., row  1022 ) of the pixel matrix  1020  to be read out, whereby all selected switching elements of pixels of the selected row are closed at the same time. Therefore, each of the selected pixels places a signal on a vertical output line (e.g., line  1023 ), where it is amplified in the column amplifiers  1040 . An X-addressing scan register(s)  1035  provides control signals to the analog multiplexer  1045  to place an output signal (amplified charges) of the column amplifiers  1045  onto output bus  1046 . The output bus  1046  may be coupled to a buffer  1048  that provides a buffered, analog output  1049  from the imaging core  1010 . 
     The output  1049  from the imaging core  1010  is coupled to an analog-to-digital converter (ADC)  1050  to convert the analog imaging core output  1049  into the digital domain. The ADC  1050  is coupled to a digital processing device  1060  to process the digital data received from the ADC  1050  (such processing may be referred to as imaging processing or post-processing). The digital processing device  1060  may include one or more general-purpose processing devices such as a microprocessor or central processing unit, a controller, or the like. Alternatively, digital processing device  1060  may include one or more special-purpose processing devices such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like. Digital processing device  1060  may also include any combination of a general-purpose processing device and a special-purpose processing device. 
     The digital processing device  1060  is coupled to an interface module  1070  that handles the information input/output (I/O) exchange with components external to the image sensor  1000  and takes care of other tasks such as protocols, handshaking, voltage conversions, etc. The interface module  1070  may be coupled to a sequencer  1080 . The sequencer  1080  may be coupled to one or more components in the image sensor  1000  such as the imaging core  1010 , digital processing device  1060 , and ADC  1050 . The sequencer  1080  may be a digital circuit that receives externally generated clock and control signals from the interface module  1070  and generates internal signals to drive circuitry in the imaging core  1010 , ADC  1050 , etc. In one embodiment, the voltage supplies that generate the control signals used to control the various components in the pixel structure of  FIG. 2  discussed below may be generated by drivers illustrated by control drivers block  1015 . In particular, control drivers  1015  may be coupled via control lines  1016  to the gates of the reset, sample and row select transistors in the pixel structure illustrated in  FIG. 3  below. Drivers and voltage supplies are known in the art; accordingly, a more detailed description is not provided. 
     It should be noted that the image sensor illustrated in  FIG. 2  is only an exemplary embodiment and an image sensor may have other configurations than that depicted in  FIG. 2 . For example, alternative embodiments of the image sensor  1000  may include one ADC  1050  for every pixel  300 , for every column (i.e., vertical output line  1023 ), or for a subset block of columns. Similarly, one or more other components within the image sensor  1000  may be duplicated and/or reconfigured for parallel or serial performance. For example, a fewer number of column amplifiers  1040  than pixel matrix columns may be used, with column outputs of the pixel matrix multiplexed into the column amplifiers. Similarly, the layout of the individual components within the image sensor  1000  may be modified to adapt to the number and type of components. In another embodiment, some of the operations performed by the image sensor  1000  may be performed in the digital domain instead of the analog domain, and vice versa. 
       FIG. 3  illustrates a pixel structure according to one embodiment of the present invention. In one embodiment, pixel  300  includes a light detecting stage  301  and a sample and hold stage  302 . The light detecting stage  301  includes a photodiode  305 , a reset transistor  310 , and a source follower transistor M 1   320 . In this embodiment, the sample and hold stage  302  includes a sample transistor  330 , a memory capacitor Cmem  350 , a pre-charge transistor  340 , and a source follower transistor M 2   360  that operates as a buffer, or unity gain amplifier. The pixel  300  also includes a row select transistor  370  coupled to a column output  380  (e.g., output line  1023 ) of the pixel matrix  1020 . 
     The reset transistor  310  of the light detecting stage  301  is used to reset the pixel to a high value using a voltage applied to gate  312 . The corresponding voltage (i.e., the voltage on gate  312  minus a gate-to-source threshold voltage V T  of reset transistor  310 ) applied to the gate  322  of the source follower transistor M 1  starts dropping due to the photocurrent generated in the photodiode  305 . The source follower transistor M 1   320  operates as a unity gain amplifier to buffer the signal from the photodiode  305 . The output (i.e., source) of transistor M 1   320  is coupled to the sample and hold stage  302 . The sample and hold stage  302  “sample” loads the voltage signal of source follower transistor M 1   320 , through the sample transistor  330 , on the front plate  351  of memory capacitor Cmem  350 . The voltage signal from the source  323  of the source follower transistor M 1   320  will remain on the memory capacitor  350  when the sample transistor  330  is turned off. In one exemplary embodiment, Cmem may have a value approximately in a range of 20 to 100 fF. Alternatively, other values of Cmem may be used. 
     Before sample loading, a pre-charge transistor  340  is used to briefly unload the memory capacitor Cmem  350 . The pre-charge transistor  340  is coupled between the source  333  of the sample transistor  330  and the back plate  352  of the memory capacitor  350 . A voltage (Vmem)  355  is applied to the back plate  352  of Cmem  350 . In one embodiment, Vmem may be a fixed voltage that is not zero. Alternatively, a varying voltage may be used to shift the voltage Vmem  355  on the memory node, so as to drive the source follower transistor M 2   360  in a more suitable regime. As a source follower induces a downward voltage shift of one Vth, the useful input range at the gate of a source follower (i.e., M 2   360 . The signal level that is at the output of M 1  is between (VDD−2*Vth) and zero (GND). As VDD is tends to become lower and lower in modern technologies, the following estimation may be made: VDD may be 1.8V, Vth may be 0.5V. Then, the output range of M 1  is between 0 and 0.8 (1.8−2*0.5), and the input range of M 2  is between 0.5 and 1.8. The overlap (i.e., the practical useful range) is thus from 0.5 to 0.8, which is very small. If we shift the M 1  output range at least 0.5V up (to 0.5-1.3, or higher), a much larger overlap of the ranges is created: the whole M 1  output range is now acceptable for M 2 . It should be noted that in other embodiments, the source follower transistor M 2   360  may not be used or, alternatively, a non-unity gain amplifier may be used. 
     In this embodiment, the pre-charge transistor  340  is a MOSFET with its source  343  coupled to the back plate  352  of the memory capacitor  350 . The pre-charge MOSFET  340  is operated in a fashion that it has a lower (i.e. negative) V GS  with respect to the low supply voltage VSS node (e.g., ground) of the pixel  300 . In this manner, the drain  344  current of the pre-charge MOSFET  340  is several orders of magnitude lower than with V GS =0. This is realized by coupling the source  343  of the pre-charge transistor  340  to a slightly positive voltage compare to the gate  342 . In one embodiment (not illustrated), this achieved by using a signal line that is coupled to the source  343  of the pre-charge transistor  340 . However, the use of an additional (i.e., not otherwise used by the pixel structure) interconnection may be expensive in terms of requiring more dies area in which the pixel is implement. In one embodiment, VSS node is configured to receive the low supply voltage from outside of the pixel structure through the substrate (which may constitute the backside of the photodiode and/or the bulk of the n-channel MOSFETS) via the substrate potential. Alternatively, VSS node may be configured to receive the low supply voltage through a dedicated signal trace. 
     In the embodiment illustrated in  FIG. 3 , in order to obtain such a slightly positive (higher potential relative to the low supply voltage) source voltage available in the pixel, it is shared from the voltage Vmem  355  applied to the back plate  352  of the memory capacitor Cmem  350 . More specifically, the source  343  of the pre-charge transistor  340  is coupled to Vmem  355  line that is coupled to the back plate of the memory capacitor Cmem  350 . When the “pre-charge” signal is made low (i.e. inactive), during most of the time, the voltage Vmem  355  is made high, corresponding to the positive (or higher potential) source voltage. Hence, V GS &lt;0 and the pre-charge transistor  340  is more off (i.e., less or substantially no leakage current through the pre-charge transistor). In one embodiment, for example, a memory voltage  355  is applied such that V GS  is approximately in a range of −0.3 to −0.4 volts. Alternatively, memory voltages may be used to generate other V GS  voltages. 
     In one embodiment, six transistors may be used to implement the pixel structure described in regards to  FIG. 3 . Alternatively, other numbers of transistors may be used. For example, in this embodiment, the source follower transistor M 1   320  and source follower transistor M 2   360  operate as buffers or unity gain amplifiers. In an alternative embodiment, one or both of the source follower transistors M 1  and M 2  may be replaced by amplifiers having multiple transistors and may be non-unity gain amplifiers. In one embodiment, the voltages applied to the gate  312  of reset transistor  310 , gate  322  of sample transistor  230 , gate  372  of row select transistor  270  and the voltage Vmem  355  applied to the back plate  352  of Cmem  350  may be generated by drivers  1015  of  FIG. 2 . 
       FIG. 4  is a timing diagram illustrating the timing corresponding to the operation of the pixel of  FIG. 3 . The timing diagram  400  illustrates the timing relationship and relative voltages between the control signal voltage  410  applied to the gate  342  of pre-charge transistor  340 ; the control signal voltage  420  applied to the gate  322  of the sample transistor  330 ; and the control signal voltage Vmem  355  applied to the back plate  352  of the memory capacitor  350 . In this embodiment, the analog memory of the pixel  300  (i.e., using Cmem) should sample the signal of an unbiased source follower (M 1 )  320 . Before the S&amp;H operation, the capacitor back plate  352  is brought to a low voltage v 1  (e.g., the low supply voltage such as ground or 0 volts) at time t 1 . The Cmem capacitor  350  is, first, briefly discharged to that same low voltage by applying a turn-on voltage v 3  to the gate  342  of pre-charge transistor  340  at time t 2 . After that, at time t 3 , a turn-on voltage v 4  is applied to the gate  322  of the sample transistor  330  (that is in series between the source follower transistor  320  and the capacitor  350 ) briefly lets the source follower transistor M 1   320  charge up the memory capacitor  350 . Then, at time t 4 , the capacitor back plate  352  is brought positive (e.g., 1 volt) to v 2  using Vmem  355 , so as to make the V GS  of the pre-charge transistor  340  negative. Thereby, the pre-charge transistor  340  shunts the memory capacitor  350 . It should be noted that the transistor turn-on voltages in relation to the pixel supply voltages would be readily apparent to one of ordinary skill in the art; accordingly, a more detailed discussion is not provided. 
     An advantage to the pixel structures discussed above in regards to  FIGS. 3 and 4  is that the hold time of the analog memory of pixel  300  may be improved by orders of magnitude over conventional pixel structures. In one embodiment, the pixel structure  300  discussed above in regards to  FIG. 3  may provide a compact solution that does not resorting to an extra component or signal line inside the pixel. The described pixel configurations also have the beneficial effect that the Cmem capacitor  350  can be implemented as a poly on diffusion capacitor whereby the back plate  351  is the diffusion. The signal plate is, thus, not light sensitive, which is important in image sensors. The pixel structures discussed above in regards to  FIGS. 3 and 4  may be used in image sensors requiring a high quality synchronous shutter. 
     As noted above, in an alternative embodiment, the pixel structure have other configurations to make V GS    341  of the pre-charge transistor  340  slightly negative with respect to the low supply voltage VSS (e.g., GND) of the pixel  300 , for example, a physical line (i.e., trace) may be routed to the source  343  of the pre-charge transistor  340 . 
     Although the low supply voltage VSS has been discussed at times in relation to a ground potential for ease of explanation, in alternative embodiment, other low supply voltage potentials may be used. 
     Another advantage to the pixel structure discussed herein is that there is a voltage level shift that brings the signal in a range that is more suitable for the source follower M 2   360 . 
     Embodiments of the present have been illustrated with MOS technology for ease of discussion. In alternative embodiments, other device types and process technologies may be used, for example, Bipolar and BiCMOS. It should be noted that the circuits described herein may be designed utilizing various voltages. 
     The image sensor and pixel structures discussed herein may be used in various applications including, but not limited to, a digital camera system, for example, for general-purpose photography (e.g., camera phone, still camera, video camera) or special-purpose photography (e.g., in automotive systems, hyperspectral imaging in space borne systems, etc). Alternatively, the image sensor and pixel structures discussed herein may be used in other types of applications, for example, machine and robotic vision, document scanning, microscopy, security, biometry, etc. 
     Although the present invention has been described with reference to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the invention as set forth in the claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.