Abstract:
Built-In Self-Testing of multiple scan chains (12 1  -12 n )can be accomplished by providing separate clock signals (CK 1  -CK n ) that are scheduled by a control circuit (22) so that each chain is clocked at its rated frequency.

Description:
TECHNICAL FIELD 
     This invention relates to a technique for operating a Built-InSelf Test Circuit having multiple clock regimes to permit each regime to be clocked at its rated operating speed. 
     BACKGROUND ART 
     Built-In Self-Testing (BIST) circuitry has been incorporated within integrated circuits (chips), circuit boards and entire systems to facilitate testing without the need for complex external test equipment. The presence of such BIST circuitry allows the host incorporating such circuitry to internally generate its own test vectors and to internally observe its own response signals to such test vectors. The only stimuli required by the BIST circuitry is an external clock signal to clock the circuitry at its appropriate operating speed. 
     For a host that has a single clock regime (i.e., the host operates at a single clock frequency), providing the appropriate clock signal to the BIST circuitry within the host is generally straightforward. However, some hosts have multiple clock regimes (i.e., such hosts require multiple clock signals). Accomplishing Built-In Self-Testing of a host that has multiple clock regimes can prove hazardous, in terms of damage to test data, if proper care is not taken. For instance, clocking a clock regime of a BIST circuit within a host at a rate higher than its maximum rate can distort or corrupt the BIST data. On the other hand, clocking the clock regime of the BIST circuit below its clock rate may not yield accurate test results. 
     Thus, there is a need for a scheme for clocking multiple clock-regimes within a BIST circuit. 
     BRIEF SUMMARY OF THE INVENTION 
     Briefly, in accordance with the invention, a method is proposed for clocking a BIST circuit having n separate clock regimes C 1 , C 2  . . . C n , (where n is an integer), each successive clock regime C i+1  having an associated clock frequency f i+1  that is less than the clock frequency f i  associated with the previous clock regime C i . The invention is practiced by clocking each of the clock regimes C 1  -C i  at with a clock signal CK i  at a frequency f i , while maintaining the clock regimes C i+1  -C n  constant, as i increases from 1 to n. Thus, for example, a BIST circuit having three clock regimes C 1 , C 2  and C 3  that operate at frequencies of 64 MHz, 32 MHz and 8 MHz, respectively, initially would have its clock regime C 1  clocked by a clock signal CK 1  at 64 MHz while the clock regimes C 2  and C 3  are kept constant. Thereafter, the clock regimes C 1  and C 2  are clocked by a clock signal CK 2  at 32 MHz while the clock regime C 3  is kept constant. Finally, the clock regimes C 1 , C 2  and C 3  are all clocked with a clock signal CK 3  at 8 MHz. By clocking the BIST circuit in this fashion, each clock regime is clocked at is rated clock frequency without incurring any harm to the clock regimes having a slower clock frequency. 
     In accordance with another aspect of the invention, it may be deskable, to the extent that there are conflicts between the clock regimes C 1  -C n , to sequentially clock each regime while holding the successive regimes constant. Thus, the clock regime C 1  would initially be clocked at frequency f i  while the regimes C 2  -C n  are held constant. Next, the clock regimes C 1  and C 2  would be clocked in sequence at frequencies f 1  and f 2 , respectively, while the remaining regimes are held constant. Thereafter, the clock regimes C 1 , C 2 , and C 3  would be clocked in sequence at frequencies f 1 , f 2  and f 3 , respectively, and so on until each of the clock regimes is sequentially clocked at its corresponding clock frequency. 
    
    
     BRIEF SUMMARY OF THE DRAWINGS 
     FIG. 1 shows a block schematic diagram of a multiple-clock regime scan-based BIST circuit that is clocked in accordance with the invention; 
     FIG. 2 shows a block schematic diagram of a control circuit associated with the circuit of FIG. 1; and 
     FIG. 3 shows a timing diagram of clock signals within the circuit of FIG. 1 when the clock regimes are sequentially clocked. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 illustrates a block schematic diagram of a BIST circuit 10 for incorporation with a host (not shown), such as an integrated circuit, a circuit board or an entire system. The BIST circuit 10 includes at least one, and preferably, a plurality of scan chains 12 1 , 12 2  . . . 12 n , where n is an integer&gt;0. In the illustrated embodiment, n=3 although it should be understood that a larger or smaller number of such chains may be present. Each of the scan chains 12 1  -12 n  comprises at least one, and a plurality of individual registers 14--14 serially coupled to each other. Each register 14 in each scan chain is connected to the host containing the BIST circuit 10 through a corresponding one of clock regime circuits 15 1  -15 n  so that the data value within the register is influenced by the operation of the host. In practice, each oft he clock regime circuits 15 1  -15 n  may comprise either a combinational or sequential circuit. 
     In addition to the scan chains 12 1  -12 n , the BIST circuit 10 includes a Linear Feedback Shift Register (LFSR) 16 for generating strings of test values for shifting into the scan chains. The BIST circuit 10 also includes a Multiple Input Shift Register (MISR) 18 that receives the strings of test values stored by of the scan chains 12 1  -12 n . The MISR 18 functions to compact or logically combine the strings of values from the scan chains 12 1  -12 n  to yield a reduced-length value string indicative of the entity tested by the BIST circuit 10. Although not shown, each of the scan chains 12 1  -12 n  could be provided with its own LFSR and MISR. 
     Each of the scan chains 12 1  -12 n , together with the associated one of its clock regime circuits 15 1  -15 n , operates a separate one clock frequencies f 1  -f n  such that f 1  &gt;f 2  &gt;f 3 . . . &gt;f n . Upon receipt of a corresponding one of clock signals CK 1  -CK n  (at corresponding frequencies f 1  -f n , respectively), each of the scan chains 12 1  -12 n  shifts in test values from the LFSK 16. At the completion of testing, the scan chains 12 1  -12 n  shift out their stored test values to the MISR 18. In the embodiment depicted in FIG. 1, the scan chains 12 1 , 12 2  and 12 n , are clocked with clock signals CK 1 , CK 2  and CK n  that have a frequency of 64 MHz, 32 MHz and 8 MHz, respectively, although it should be understood that different frequency clock signals may be readily employed. 
     Heretofore, clocking the scan chains 12 1  -12 n  at the appropriate clock frequencies f 1  -f n , respectively, has proved problematic. Clocking all of the scan chains 12 1  -12 n  at the lowest common frequency f n  will avoid damage to the logical values stored in the scan chains that would otherwise occur if any chain was clocked in excess of its rated clock frequency. However, this approach would not facilitate testing of the scan chains 12 1  -12 n-1  at their rated frequency. Clocking the scan chains 12 1  -12 n  at their rated clock frequencies f 1  -f n , respectively, simultaneously would likely give rise to conflicts that might adversely affect the information shifted out of one or more chains. 
     In accordance with the invention, a method is provided for scheduling the clocking of the scan chains 12 1  -12 n , to allow each chain to be clocked at its rated frequency while avoiding potential conflicts. In general terms, the clocking method of the present invention is practiced by clocking the scan chains 12 1  --12 i  at a clock frequency f i , while maintaining clock signal to the scan chains 12 i+1  -12 n  constant, for successive values of i. Thus, the scan chain 12 1  is initially clocked at its rated frequency f 1  while the clock signals supplied to the remaining scan chains 12 1  -12 n  are held at constant values. Thereafter, the scan chains 12 1  and 12 2  are clocked at a clock frequency f 2  while the clock signals supplied to the remaining scan chains 12 3  -12 n  are held constant. The scan chains 12 1  -12 i  are successively clocked in this manner as i increases monotonically from 1 until n at which time, the scan chains 12 1  -12 n  will all have been clocked at the clock frequency f n . 
     To facilitate scheduling in this manner, the BIST circuit 10 of FIG. 1 includes a clock generator circuit 21 for generating a set of clock signals CK1-CK n  each at a corresponding one of the rated clock frequencies f 1  -f n , associated with the scan chains 12 1  -12 n , respectively. The clock generator circuit 21 may comprise a single clock (not shown) together with appropriate divider circuits for yielding the clock signals CK1-CK n . Rather than provide a separate clock generator circuit for this purpose, the clock signals CK1-CK n  could be derived from the host. 
     The clock signals CK1-CK n , are appropriately supplied to the scan chains 12 1  -12 n  according to a prescribed schedule by a clock control circuit 22 whose details are shown in FIG. 2. Referring to FIG. 2, the control circuit 22 includes a clock multiplexer circuit 24, which, in the illustrated embodiment, comprises two three-input multiplexers 26 and 28, and a two-input multiplexer 30. (As will be appreciated, each clock regime will have its associated multiplexer within the clock multiplexer 24 so that a BIST circuit containing a larger number of clock regimes will have a greater number of multiplexers.) The multiplexer 26 is supplied at each of its three inputs 0, 1 and 2 with the clock signals CK 1 , CK 2  and CK n , respectively, generated by the clock generator circuit 21 of FIG. 1. The multiplexer 26 is controlled by a decoder 32, described hereinafter, so that during a first, second and third test intervals, the multiplexer passes a separate one of the clock signals CK 1 , CK 2  and CK n , respectively, to the scan chain 12 1 . In this way, the scan chain 12 1  is clocked at 64 MHz, 32 MHz and 8 MHz during the first, second and third test intervals, respectively. 
     The multiplexer 28 has its first and third inputs (0 and 2) supplied with the clock signals CK 2  and CK n , respectively, while the second multiplexer input (1) is grounded. Like the multiplexer 26, the multiplexer 28 is also controlled by the decoder 32. During the second and third test intervals, the decoder 32 causes the multiplexer 28 to pass the clock signals CK 2  and CK n  to the scan chains 12 1  and 12 n , respectively. However, during the first interval, the decoder 32 causes the multiplexer to pass the ground-level signal at its second input to the scan chain 12 2  so the frequency of the clock signal received by that during the first interval remains constant. 
     The multiplexer 30 has its first input (0) supplied with the clock signal CK n  from the clock generator circuit 21 while the second input of the multiplexer is grounded. Like the multiplexers 26 and 28, the multiplexer 30 is also controlled by the decoder 32. During the first and second test intervals, the decoder 32 controls the multiplexer 30 so that its output signal, representing the clock signal supplied to scan chain 12 n , remains constant. However, during the third test interval, the decoder 32 causes the multiplexer to pass the clock signal CK n  from the dock generator circuit 21 of FIG. 1 to the scan chain 12 n  so this scan chain is clocked at a frequency f n  (8 MHz). 
     As may be appreciated, the decoder 32 controls the multiplexers 26, 28 and 30 so that during the first interval, the scan chain 12 1  alone is docked by the signal CK 1 . During the second interval, the scan chains 12 1  and 12 2  are both clocked by the clock signal CK 2 . During the third interval, the scan chains 12 1  -12 n  are all clocked by the clock signal CK n . In this way, each scan chain is clocked at its rated frequency without adversely impacting the scan chains that operate at lower frequencies. 
     Referring to FIG. 2, the decoder 32 includes five two-input AND gates 34, 36, 38, 40 and 42 that produce control signals c 1 , c 2 , c 3 , c 4 , and c 5 , respectively, at their outputs. The control signals c 1  and c 2  from the AND gates 34 and 36, respectively, control the multiplexer 26. The control signals c 3  and c 4  from the AND gates 38 and 40, respectively, control the multiplexer 28. The control signal c 5  produced by the AND gate 42 controls the multiplexer 30. 
     The AND gates 34-42 each receive a signal RUNBIST at a first input. The RUNBIST signal transitions to an active high level when the BIST circuit of FIG. 1 becomes operative to test its host. The AND gate 34 receives at its second input the output of an AND gate 44 whose first and second inputs receive first and second output bits φ 1  and φ 2 , respectively, of a 2-bit domain counter 45. The counter 45, when triggered by a signal BCTR, generates a two-bit count: (0 0), (0 1), (1 0), (1 1) and so on until the counter is reset by a reset signal RESET. 
     The AND gate 36 that generates the control signal c 2  has its second input supplied with the output signal of an AND gate 46. The AND gate 46 receives the first bit φ 1  of the counter 45 at its first input and receives at its second input the second bit φ 2  of the counter 45 through a NOT gate 48. The AND gate 38 that generates the control signal c 3  receives the first counter bit φ 1  directly at its second input. The AND gate 40 that generates the control signal c 4  receives at its second input the output signal of an AND gate 50 supplied at its first input with the counter bit φ 1 , as inverted by a NOT gate 52. The second input of the AND gate 40 receives the second counter bit φ 2  directly. Lastly, the AND gate 42 that generates the control signal c 5  receives at its second input the output signal of an exclusive (XOR) gate 54 that receives the counter bits φ 1  and φ 2  at its first and second inputs, respectively. 
     The overall operation of the decoder 32 of FIG. 2 may best be understood from Table I which is a truth table for the various gates in the decoder for various counts of the domain counter 45. 
     
                       TABLE I______________________________________Domain                    Clock SignalsCounter                   Scan    Scan  ScanStates Decoder Outputs    Chain   Chain Chainφ.sub.1    φ.sub.2      c.sub.1             c.sub.2                  c.sub.3                       c.sub.4                            c.sub.5                                 12.sub.1                                       12.sub.2                                             12.sub.n______________________________________0   0      0      0    0    0    0    CK.sub.1                                       CK.sub.2                                             CK.sub.n0   1      0      0    0    1    1    CK.sub.1                                       0     01   0      0      1    1    0    1    CK.sub.2                                       CK.sub.2                                             01   1      1      0    1    0    0    CK.sub.n                                       CK.sub.n                                             CK.sub.n______________________________________ 
    
     As may be appreciated from Table I, during normal operation (i.e., during non-testing intervals), the bits φ 1  and φ 2  of the domain counter 45 are (0,0). Consequently, the control signals c 1  -c 5  are each low (zero), so the scan chains 12 1 , 12 2  and 12 n  receive the clock signals CK 1 , CK 2  and CK n , respectively. 
     Once the domain counter 45 generates its first count (0,1) (signifying the first test interval), the control signals c 4  and c 5  transition from a low to a high value (one). Consequently, the multiplexers 28 and 30 now both pass a ground-level clock signal to the scan chains 12 2  and 12 n , respectively. At this time, the control signals c 1  and c 2  remain low so the multiplexer 26 continues to pass the clock signal CK 1  to the scan chain 12 1 . 
     Upon the second count (1,0) of the domain counter 45 (signifying the second test interval), the control signals c 2 , and c 3  transition from a low value to a high value. At the same time the control signal c 4  become low while the control signal c 5  remains high. As a result, the multiplexers 26 and 28 now pass the clock signal CK 2  to scan chains 12 1  and 12 2 , respectively. The control signal c 5  still remains high at this time so the multiplexer 30 continues to pass a ground-level clock signal to the scan chain 12 n . 
     Upon the third count (1,1) of the domain counter 45 (signifying the third test interval), the control signals c 1  and c 3  become high while the control signals c 2  and c 5  become low. The control signal c 4  remains low at this time. Under these circumstances, the multiplexers 26, 28 and 30 pass the clock signal CK n , to the scan chains 12 1 , 12 2  and 12 n . 
     In the clocking scheme described above, no skew has been assumed between the clock signals CK 1  -CK n . In other words, the clock signals CK 1  -CK n  are presumed to be synchronized to each other. However, in practice, the clock signals CK 1  -CK n  may not be synchronized, and there may be a skew between them that may adversely affect clocking of the scan chains 12 1  -12 n . Referring now to FIG. 3, the problem of skew can be mitigated by generating the clock signals at least one cycle apart during the normal (test) mode, assuming that the skew between them is less than one clock cycle. However, during a scan mode, a common clock signal will typically be used to scan in data. 
     The foregoing describes a technique for clocking a multiple clock regime circuit wherein each successively larger groups of clock regimes are clocked at successively slower clock regimes such that each regime is docked at no higher than its rated clock frequency. 
     It is to be understood that the above-described embodiments are merely illustrative of the principles of the invention. Various modifications and changes may be made thereto by those skilled in the art which will embody the principles of the invention and fall within the spirit and scope thereof. For example, while only three separate clock regimes have been disclosed, it should be understood that the invention is equally used for BIST circuits that contains a large number of such clock domains.