Abstract:
A method and apparatus controls the read and write accesses of multi-level memory devices, chips, or modules in order to speed up the memory data transfer rate between a processing device and a memory device to increase the utilization of the data width of the memory cell array. Also, the present invention provides a method that is compatible with the structure of existing memory chips and modules.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    This invention relates to semiconductor memory devices, memory chips, memory modules, and memory controllers.  
           [0002]    Because of the physical structure, a memory cell array is organized as a large number of rows by a large number of columns. The maximum potential width for parallel data transfer equals the number of columns times the number of bit planes. For a 64 mega-bit memory chip organized as 8192 rows, 1024 columns, and 8 bits, the maximum data width is 8192 bits.  
           [0003]    However, due to the pin count limitation of semiconductor chips and modules, the actual data transfer width is set to be a much smaller number. The data input-output width for a memory chip is typically 1, 2, 4, 8, or 16 bits.  
           [0004]    Internally, many columns of a memory cell array are multiplexed together to form a memory input-output data bit line. In doing so, the speed of memory data transfer is limited to the width and frequency of the memory data line.  
           [0005]    For a memory chip with an 8192-row 1024-column 8-bit cell array, the 1024 columns are multiplexed into a 1-bit memory data line. The data width of the memory array is reduced by a factor of 1024.  
           [0006]    As the density of the semiconductor memory device increases, the size of the memory cell array increases as well. The data width reduction factor also becomes larger.  
           [0007]    The system functionality demands high-speed processing of a large amount of memory data. As the speed of the processing unit increases to a higher level, the limitation in memory data transfer rate becomes a severe speed bottleneck for a processing system.  
         BRIEF SUMMARY OF THE INVENTION  
         [0008]    This invention proposes a method and apparatus to control a memory subsystem that increases the speed of the memory data transfer.  
           [0009]    This invention provides a method to maximize the utilization of the speed and data width of the memory cell array.  
           [0010]    The present invention provides a method that adjusts the memory data transfer according to the operating condition of the memory devices.  
           [0011]    The present invention further provides a method that is compatible with the structure of existing memory chips and modules. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]    [0012]FIG. 1 is a diagram of a prior art memory chip.  
         [0013]    [0013]FIG. 2 is a diagram of a prior art data input-output unit in a memory chip.  
         [0014]    [0014]FIG. 3 is a diagram of a prior art memory module.  
         [0015]    [0015]FIG. 4 is a diagram of a multilevel memory chip.  
         [0016]    [0016]FIG. 5 is a diagram of a data input-output unit in a multilevel memory chip.  
         [0017]    [0017]FIG. 6 is a diagram of a data input-output formatting unit in a memory chip.  
         [0018]    [0018]FIG. 7 is a diagram of another data input-output formatting unit in a multilevel memory chip.  
         [0019]    [0019]FIG. 8 is a diagram of a prior art memory access system.  
         [0020]    [0020]FIG. 9 shows a preferred embodiment of the present invention for a multilevel memory access system using multilevel memory chips.  
         [0021]    [0021]FIG. 10 shows a preferred embodiment of the present invention for a binary memory access system using multilevel memory chips.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0022]    The present invention will be illustrated with some preferred embodiments.  
         [0023]    [0023]FIG. 1 is a diagram of a prior art memory chip. The memory device  101  contains a memory cell array  102 , a memory address row-decoding unit  103 , and a memory data input-output unit  104 . The memory data input-output unit  104  consists of a column multiplexing-distributing unit  105  and an input-output data-bit driving unit  106 .  
         [0024]    For a particular memory access, the address row-decoding unit  103  selects a memory row  107  in the memory cell array  102 . The selected data row signals are connected to the column multiplexing-distributing unit  105 . The selected signals are linked to the corresponding bit position in the input-output data-bit driving unit  106 .  
         [0025]    As an example, for the selected bit position, the data signals  108  are connected to the column multiplexing-distributing bit position  109 , which is further linked to the input-output data-bit driving bit position  110 .  
         [0026]    [0026]FIG. 2 is a diagram of a prior art data input-output block in a memory chip. The memory data input-output unit  201  consists of a column multiplexing-distributing unit  202  and an input-output data-bit driving unit  203 .  
         [0027]    For memory read access, the selected data signals on data lines  204  are sent to the column multiplexing-distributing unit  202 . The output signal on data line  205  is sent to the input-output data-bit driving unit  203 . The output signal further passes through an output signal driving circuit  206  to reach the input-output pad  207 .  
         [0028]    For memory write access, the input signal from the input-output pad  207  passes through an input signal receiving circuit  208  to data line  205 . The input signal is connected through the column multiplexing-distributing unit  202  to the appropriate memory column signal on data lines  204 .  
         [0029]    For illustration purpose, assume that the memory cell array contains 1024 columns. There are 1024 lines on the data lines  204 . The column multiplexing-distributing unit  202  reduces the data width to 1 bit on data line  205 .  
         [0030]    The data input-output signal on the input-output pad  207  is a binary signal with 2 signal states, a 0 state and a 1 state. The 0 state corresponds to a common voltage level. The 1 state corresponds to a single positive voltage level.  
         [0031]    [0031]FIG. 3 is a diagram of a prior art memory module. The memory module  301  receives address-control signals on a memory address-control bus  302 . The address-control signals select memory data from the memory device  303 . The selected memory data is placed on a device data port  304 . The memory data further passes through a connection element  305  to reach the memory data bus  306 . The combination of a memory device  303  and a connection element  305  constitutes a memory unit. This memory module contains a total of eight memory units.  
         [0032]    [0032]FIG. 4 is a diagram of a multilevel memory chip. The memory device  401  contains a memory cell array  402 , a memory address row-decoding unit  403 , and a memory data input-output unit  404 . The memory data input-output unit  404  consists of a data input-output formatting unit  405  and an input-output level-conversion unit  406 .  
         [0033]    For a particular memory access, the address unit  403  selects a memory row  407  in the memory cell array  402 . The selected data row signals are connected to the data input-output formatting unit  405 . The selected signals are linked to the corresponding bit position in the input-output level-conversion unit  406 .  
         [0034]    As an example, for the selected bit position, the selected data signals  408  are connected to the input-output formatting bit position  409 , which is further linked to the input-output level-conversion bit position  410 .  
         [0035]    [0035]FIG. 5 is a diagram of a data input-output unit in a multilevel memory chip. The memory data input-output unit  501  consists of a data input-output formatting unit  502  and an input-output level-conversion unit  503 .  
         [0036]    For memory read access, the selected data signals on data lines  504  are sent to the data input-output formatting unit  502 . The output signals on data lines  505  are sent to the input-output level-conversion unit  503 . The output signal further passes through an output signal level-conversion circuit  506  to reach the input-output pad  507 .  
         [0037]    For memory write access, the input signal from the input-output pad  507  passes through an input signal receiving circuit  508  to data lines  505 . The input signals are connected to the appropriate memory column signals on data lines  504 .  
         [0038]    For illustration purpose, assume that the memory cell array contains 1024 columns. There are 1024 lines on the data lines  504 . Also assume that we use a 16-level data signal on input-output pad  507  for memory data transfer.  
         [0039]    The data input-output formatting unit  502  reduces the data width to 4 bits on data lines  505 . The data input-output signal on the input-output pad  507  is a multi-state signal with 16 signal states. There are 16 voltage levels each defined as a range of signal voltage values.  
         [0040]    With a data input-output unit in FIG. 5, the memory data transfer rate for a memory system in FIG. 4 is increased by a factor of 4 compared to the memory data transfer rate for a memory system in FIG. 1.  
         [0041]    [0041]FIG. 6 is a diagram of a data input-output formatting unit in a memory chip. The selected data signals on data lines  602  are connected to input-output data lines  603  through the data formatting unit  601 .  
         [0042]    The data transfer is controlled by the address signals A 3  and A 2  on address lines  604 . The address signals are decoded in the address-decoding unit  605  into  4  enabling signals. These 4 enabling signals connect the selected data lines in data lines  602  to input-output data lines  603  through the data connection units  606 ,  607 ,  608 , and  609 .  
         [0043]    [0043]FIG. 7 is a diagram of another data input-output formatting unit in a multilevel memory chip. This input-output formatting unit supports variable-level memory data transfer to adapt to operational conditions. In this example, it supports 16-level, 4-level, and 2-level memory data formats. In the case of 2-level data format, it maintains the compatibility to the conventional binary memory data transfer.  
         [0044]    The selected data signals on data lines  702  are connected to input-output data lines  703  through the data formatting unit  701 . The data transfer is controlled by the address signals A 3 , A 2 , A 1 , and A 0  on address lines  704 . It is also controlled by data transfer mode-enabling signals  705 ,  707 , and  709 .  
         [0045]    For 16-level data transfer, data transfer mode-enabling signal  709  enables the decoding of the address signals A 3  and A 2  in the address-decoding unit  710  into  4  enabling signals. These 4 enabling signals connect the selected data lines in data lines  702  to input-output data lines  703  through the data connection units  711 ,  712 ,  713 , and  714 .  
         [0046]    For 4-level data transfer, data transfer mode-enabling signal  707  enables the decoding of the address signals A 3 , A 2  and A 1  in the address-decoding unit  708  into 8 enabling signals. These  8  enabling signals connect the selected data lines in data lines  702  to input-output data lines  703  through the data connection units  715 ,  716 ,  717 , and  718 .  
         [0047]    For 2-level binary data transfer, data transfer mode-enabling signal  705  enables the decoding of the address signals A 3 , A 2 , A 1  and A 0  in the address-decoding unit  706  into  16  enabling signals. These 16 enabling signals connect the selected data lines in data lines  702  to input-output data lines  703  through the data connection units  719 ,  720 ,  721 , and  722 .  
         [0048]    The data transfer mode-enabling signals  705 ,  707 , and  709  may be set by hardwire, logic, or programmable bit values.  
         [0049]    For the same memory device, the data transfer rates for a memory read operation and a memory write operation need not be at the same speed. They may be set to different data transfer modes to obtain the most effective data transfer under certain operating conditions.  
         [0050]    For the same memory device, the data transfer mode may also change dynamically over time to accommodate the operational need. For example, the data transfer mode may be set to binary mode initially. After an initialization process, it may then be set to a selected read transfer mode and a selected write transfer mode.  
         [0051]    The multilevel method is also applicable on the address-control signal lines. Binary and multilevel signals may be used on the address-control lines and data lines independently or simultaneously. These signals may also be asymmetric or variable with time.  
         [0052]    Multilevel memory chips may be used to construct binary memory modules for existing binary memory systems. Existing binary memory chips may also be used to construct multilevel memory modules in new multilevel memory systems.  
         [0053]    [0053]FIG. 8 is a diagram of a prior art memory access system. The memory access controller  801  generates address-control signals on a memory address-control bus  802 . The address-control signals select memory data from a binary memory device  803 . The selected binary memory data is placed on a binary device data bus  804 .  
         [0054]    [0054]FIG. 9 shows a preferred embodiment of the present invention for a multilevel memory access system using multilevel memory chips. The memory access controller  901  generates address-control signals on a memory address-control bus  902 . The address-control signals select memory data from a multilevel memory device  903 . The selected memory data is placed on a multilevel device data port  904 .  
         [0055]    [0055]FIG. 10 shows a preferred embodiment of the present invention for a binary memory access system using multilevel memory chips. The memory access controller  1001  generates address-control signals on a memory address-control bus  1002 . The address-control signals select memory data from a multilevel memory device  1003 . The selected multilevel memory data is placed on a multilevel device data port  1004 . A multilevel-to-binary signal converter  1005  transforms the multilevel memory data  1004  to binary memory data  1006 . The binary memory data further passes through a connection element  1007  to reach the binary memory data bus  1008 .