Abstract:
A sample-and-hold circuit is provided for an input voltage in response to a timing signal and outputting a holding voltage. The sample and hold circuit includes a plurality of switches, first and second capacitors, first and second differential input units, and an output unit. One of the switches which is controlled by a switching signal is used for preventing the voltage outputted by the output unit from being back to the inverting input terminal of the first differential input unit while the voltage of the input signal is being transferred to the first node. One of the switches which is controlled by the switching signal is used for preventing the voltage outputted by the output unit from being back to the inverting input terminal of the second differential input unit while the voltage of the input signal is being transferred to the second node.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates to a sample-and-hold circuit for an input voltage in response to a timing signal and outputting a holding voltage. More particularly, the invention relates to a sample-and-hold circuit which can be used as an analog driver application for a flat panel display.  
         [0003]     2. Description of Related Art  
         [0004]     A sample-and-hold circuit is arranged in the input section of an analog/digital (A/D) converter or another converting device. It samples the input voltage with prescribed timing, and then holds the sampled voltage until the end of the conversion operation by the converting device set in the next stage.  
         [0005]     The sample and hold circuit is used, for example, for a thin-film transistor driving circuit or the like of a liquid crystal panel.  FIG. 1  and  FIG. 2  are circuit diagrams showing examples of constructions of conventional sample and hold circuits. The sample and hold circuit  100  shown in  FIG. 1  is a circuit of the parallel 2-latch/1-buffer amplifier type disclosed in JP-B-6-54418. The circuit has an input terminal  101  to which an input voltage IN is supplied and a control terminal  102  to which a switching signal SW is supplied. Capacitors C 1  and C 2  for holding the input voltage IN are connected to the input terminal  101  through transmission gates (hereinafter, the transmission gate is referred to as “TG”) TG 1  and TG 2 , respectively. The capacitors C 1  and C 2  are connected to the input side of a buffer amplifier (hereinafter, also referred to as “AMP”)  110  through TG 3  and TG 4 , respectively. The output side of the AMP  110  is connected to an output terminal OUT. The switching signal SW of the control terminal  102  is supplied as a control signal to the TG 1  and TG 4 , and inverted by an inverter  103  and then supplied as a control signal to the TG  2  and TG 3 .  
         [0006]     According to such a sample and hold circuit  100 , when the switching signal SW is at the “H” level, the TG 1  and TG 4  are turned on and the TG 2  and TG 3  are turned off, so that the input voltage IN at the input terminal  101  is charged into the capacitor C 1  through the TG 1 . On the other hand, a voltage charged in the capacitor C 2  is supplied to the AMP  110  through the TG 4  and outputted as an output voltage OUT from the AMP  110  to the output terminal OUT.  
         [0007]     Subsequently, when the switching signal SW is set to the “L” level, the TG 1  and TG 4  are turned off and the TG 2  and TG 3  are turned on, so that the input voltage IN at the input terminal  101  is charged into the capacitor C 2  through the TG 2 . On the other hand, a voltage charged in the capacitor C 1  is supplied to the AMP  110  through the TG 3  and outputted as an output voltage OUT from the AMP  110  to the output terminal OUT.  
         [0008]     As mentioned above, the input voltage IN is alternately charged into the two capacitors C 1  and C 2  in response to the switching signal SW and the charged voltage is outputted as an output voltage OUT through the AMP  110 . However, this structure has a serious disadvantage and defects because CMOS switch has charge injection effect and the parasitic capacitance of AMP input transistor effect. During a period when TG 3  is turned ON, the equivalent holding capacitance is C 1 +C parasitic , but when the circuit is in a sampling phase, that is, TG 3  is turned OFF, the equivalent sample capacitance is C 1 . Different value of capacitance between the sample phase and the hold phase accompanying with the charge injection effect when TG 3  switch is turned OFF, the holding voltage will different from the input sampling voltage.  
         [0009]     Another conventional sample and hold circuit  200  is shown in  FIG. 2 , which is a circuit of the parallel 2-latch/2-buffer amplifier type disclosed in JP-A-11-249633 and constructed in a manner similar to that of  FIG. 2  except that the amplifier AMP  110  at the post stage of the TG 3  and TG 4  in  FIG. 1  is deleted and amplifiers (hereinafter, also referred to as “AMPs”)  210  and  220  are provided between the capacitors C 1  and C 2  and the TG 3  and TG 4 , respectively. According to such a sample and hold circuit  200 , when the switching signal SW is at the “H” level, the input voltage IN at the input terminal  201  is charged into the capacitor C 1  through the TG 1 . On the other hand, the voltage charged in the capacitor C 2  is supplied to the TG 4  through the AMP  220  and outputted as an output voltage to the output terminal OUT through the TG  4 .  
         [0010]     Subsequently, when the switching signal SW is set to the “L” level, the input voltage IN at the input terminal  201  is charged into the capacitor C 2  through the TG 2 . On the other hand, the voltage charged in the capacitor C 1  is supplied to the TG 3  through the AMP  210  and outputted as an output voltage to the output terminal OUT through the TG  3 . However, the conventional sample and hold circuit  200  has a problem of power consumption, which is a critical issue for analog type liquid crystal displays which are most used in portable devices.  
         [0011]     A further conventional sample and hold circuit  300  is shown in  FIG. 3A , which can solve the problem above by using 2 input stages and only one output stage. The sample and hold circuit  300  has an input terminal  301  to which the input voltage IN is applied and a control terminal  302  to which the switching signal SW is supplied, which is disclosed in U.S. Pat. No. 6,628,148. The input terminal  301  is connected to nodes N 1  and N 2  through the first switches (for example, TGs) TG 1  and TG 2 , respectively. The capacitors C 1  and C 2  to hold the input voltage IN are connected between the nodes N 1  and N 2  and a ground GND, respectively. Non-inverting input terminals (+) of differential input units  310  and  320  are connected to the nodes N 1  and N 2 , respectively. Each of the differential input units  310  and  320  has the same construction and outputs a voltage corresponding to a potential difference between the non-inverting input terminal and an inverting input terminal (−). For example, the differential input unit  310  has p-channel MOS transistors (hereinafter, also referred to as “PMOSs”)  312  and  314 . Gates of the PMOSs  312  and  314  constructs the non-inverting input terminal and the inverting input terminal, respectively. Sources of the PMOSs  312  and  314  of each are connected to a drain of a PMOS  316 . A source of the PMOS  316  is connected to a power potential VDD. A bias voltage VB is applied to a gate of the PMOS  316  so that a current flowing in the PMOS  316  is set to a constant value. Drains of the PMOSs  312  and  314  are connected to the grounding potential through an n-channel MOS transistor (hereinafter, referred to as “NMOS”)  317  and  318  respectively.  
         [0012]     By using the sample and hold circuit  300 , the power can be saved from only one output stage. But this topology has a serious problem. When the switching signal SW is at the “H” level, the TG 1  and TG 4  are turned on and the TG 2  and TG 3  are turned off, so that the output is driving by a holding voltage on the capacitor C 2 . Because the output voltage is different from the sampling voltage at the capacitor C 1 , therefore, the differential pair gate voltages are different. This will lead to a voltage spike occurs, which will couple from the parasitic capacitance C parasitic  to the holding capacitor C 1 . Then a large offset voltage occurs.  FIG. 3B  is a simulation result regarding the sample and hold circuit  300  of  FIG. 3A . It can be seen that a larger offset voltage of output occurs due to the problem of voltage spike, especially when voltage changes large during two phase like input from 0.5V to 4.5V.  
       SUMMARY OF THE INVENTION  
       [0013]     Therefore, one object of this present invention is to provide a sample-and-hold circuit for an input voltage in response to a timing signal and outputting a holding voltage, which the problem of the voltage spike will be eliminated. That is, no offset voltage is coupled from the parasitic capacitance. The sample-and-hold circuit which can be used as an analog driver application for a flat panel display.  
         [0014]     The above is a brief description of some deficiencies in the prior art and advantages of the present invention. Other features, advantages and embodiments of the invention will be apparent to those skilled in the art from the following description, accompanying drawings and appended claims. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]      FIG. 1  and  FIG. 2  are circuit diagrams showing examples of constructions of conventional sample and hold circuits.  
         [0016]      FIG. 3A  is a further conventional sample and hold circuit.  
         [0017]      FIG. 3B  is a simulation result regarding the sample and hold circuit of  FIG. 3A  further conventional sample and hold circuit.  
         [0018]      FIG. 4  is a circuit diagram of a sample and hold circuit showing a first embodiment of the invention.  
         [0019]      FIG. 5  is a circuit diagram of a sample and hold circuit showing a second embodiment of the invention.  
         [0020]      FIG. 6  is a circuit diagram of a sample and hold circuit showing a third embodiment of the invention.  
         [0021]      FIG. 7 ( a ) and  7 ( b ) are showing an analog type liquid crystal display driving method which uses the sample and hold circuit of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0022]     Before describing the preferred embodiments of load-balancing method for this present invention, several terms are defined as follows.  
         [0023]      FIG. 4  is a circuit diagram of a sample and hold circuit  400  showing a first embodiment of the invention and component elements similar to those in  FIG. 3  are designated by the same reference numerals. The sample and hold circuit  400  has an input terminal  401  to which an input voltage IN is applied and a control terminal  402  to which a switching signal SW is supplied. The input terminal  401  is connected to nodes N 1  and N 2  through switches, for example, transmission gates (hereinafter, the transmission gate is referred to as “TG”) TG 1  and TG 2 , respectively. The capacitors C 1  and C 2  to hold the input voltage IN are connected between the nodes N 1  and N 2  and a ground GND, respectively. Non-inverting input terminals (+) of differential input units  410  and  420  are connected to the nodes N 1  and N 2 , respectively. Each of the differential input units  410  and  420  outputs a voltage corresponding to a potential difference between the non-inverting input terminal and an inverting input terminal (−). Inverting input terminals (−) of differential input units  410  and  420  are connected to the nodes N 13  and N 14 , respectively, as shown in  FIG. 4 .  
         [0024]     For example, the differential input unit  410  has p-channel MOS (hereinafter, also referred to as “PMOS”) transistors  411  and  412 . Gates of the PMOS transistors  411  and  412  constructs the non-inverting input terminal and the inverting input terminal, respectively. Sources of the PMOS transistors  411  and  412  of the differential input unit  410  are connected to a drain of a PMOS transistor  415  through a node N 3 . A source of the PMOS transistor  415  is connected to a power potential VDD. A bias voltage VB is applied to a gate of the PMOS  415  so that a current flowing in the PMOS transistor  415  is set to a constant value.  
         [0025]     Drains of the PMOS transistors  411  and  412  of the differential input unit  410  are connected to the grounding potential GND through a node N 4  and an n-channel MOS (hereinafter, referred to “NMOS”) transistor  413 , and through a node N 5  and a NMOS transistor  414 , respectively. Gates of the NMOS transistors  413  and  414  are connected in common to the drain of the PMOS transistor  412 . The voltage corresponding to the potential difference between the non-inverting input terminal and the inverting input terminal is outputted from the drain of the PMOS transistor  411 .  
         [0026]     In the similar structure, the differential input unit  420  has p-channel MOS (hereinafter, also referred to as “PMOS”) transistors  421  and  422 . Gates of the PMOS transistors  421  and  422  constructs the non-inverting input terminal and the inverting input terminal, respectively. Sources of the PMOS transistors  421  and  422  of the differential input unit  420  are connected to a drain of a PMOS transistor  425  through a node N 8 . A source of the PMOS transistor  425  is connected to a power potential VDD. A bias voltage VB is applied to a gate of the PMOS transistor  425  so that a current flowing in the PMOS transistor  425  is set to a constant value.  
         [0027]     Drains of the PMOS transistors  421  and  422  of each of the differential input unit  420  are connected to the grounding potential GND through a node N 9  and n-channel MOS (hereinafter, referred to “NMOS”) transistor  423 , and through a node N 10  and a NMOS transistor  424 , respectively. Gates of the NMOS transistors  423  and  424  are connected in common to the drain of the PMOS transistor  422 . The voltage corresponding to the potential difference between the non-inverting input terminal and the inverting input terminal is outputted from the drain of the PMOS transistor  421 .  
         [0028]     Output terminals of the differential input units  410  and  420 , that is, the drains of the PMOS transistors  411  and  421  are respectively connected to N 15  in common through the switches (for example, TGs) TG 3  and TG 5 , respectively. A gate of an NMOS transistor  433  of an output unit  430  is connected to the node N 15 . A source and a drain of the NMOS transistor  433  are connected to the grounding potential GND and output terminal OUT, respectively. A PMOS transistor  431  is connected between the output terminal OUT and power potential VDD. The bias voltage VB is applied to a gate of the PMOS transistor  431 . A capacitor C 3  for correcting phase characteristics is connected between the drain and the gate of the NMOS transistor  433 . The transmission gates TG 1  and TG 4  are controlled by the switching signal SW and the transmission gates TG 2  and TG 3  are controlled by the inverted switching signal SW which is inverted by the an inverter  405 .  
         [0029]     In the preferred embodiment, several CMOS switches, for example, transmission gates TG 5 , TG 6 , TG 7  and TG 8  are incorporated in the sample and hold circuit  400 . The transmission gate TG 5  is incorporated between the nodes N 4  and N 5  and is controlled by the switching signal SW. The transmission gate TG 6  is incorporated between the nodes N 9  and N 10  and is controlled by the inverted switching signal SW. The transmission gate TG 7  is incorporated between the nodes N 13 , which is the inverting input terminal of the differential input unit  410 , and the output terminal OUT and is controlled by the inverted switching signal SW. The transmission gate TG 8  is incorporated between the nodes N 14 , which is the inverting input terminal of the differential input unit  420 , and the output terminal OUT and is controlled by the switching signal SW.  
         [0030]     The operation will now be described. When the switching signal SW is at the “H” level, the transmission gates TG 1 , TG 4 , TG 5 , TG 8  are turned ON and the other transmission gates TG 2 , TG 3 , TG 6  and TG 7  are turned OFF. Thus, the input voltage IN applied to the input terminal  401  is charged into the capacitor C 1  through the transmission gate TG 1  and supplied to the non-inverting input terminal of the differential input unit  410 . The capacitor C 1  is in a sampling phase. Since the output voltage at the output terminal OUT is applied to the inverting input terminal of the differential input unit  410  through transmission gate TG 7 , which is turn OFF, the inverting input terminal of the differential input unit  410  is blocked from the output voltage from the output terminal OUT. Therefore, the voltage spike is eliminated, no offset voltage is coupled from parasitic capacitance. However, since the transmission gate TG 3  is in the OFF state, it is not outputted to the node N 15 .  
         [0031]     Since the transmission gate TG 4  is turned on, the differential input unit  420  is connected to the output unit  430 . A voltage follower circuit having a voltage amplification factor  1  is constructed by both of the units  420  and  430 . Thus, the voltage charged in the capacitor C 2  is generated as an output voltage to the output terminal OUT. During the sampling phase on the capacitor C 1 , the transmission gate TG 5 , which is turned on by the switch signal SW, will connect the nodes N 4  and N 5 . The transmission gate TG 7 , which is turned off, will block the output voltage at the output terminal OUT being applied back to the gate of the PMOS transistor  412 . Therefore, the problem of the voltage spike will be eliminated. That is, no offset voltage is coupled from the parasitic capacitance.  
         [0032]     Subsequently, when the switching signal SW is set to “L”, the transmission gates TG 1 , TG 4 , TG 5 , TG 8  are turned OFF and the other transmission gates TG 2 , TG 3 , TG 6  and TG 7  are turned ON. Thus, the input voltage IN applied to the input terminal  401  is charged into the capacitor C 2  through the transmission gate TG 2  and supplied to the non-inverting input terminal of the differential input unit  420 . At this time, since the TG 4  is in the OFF state, the input voltage IN is not outputted to the output terminal OUT. On the other hand, since the TG 3  is turned on, the differential input unit  410  is connected to the output unit  430 , thereby constructing a voltage follower circuit. Thus, the voltage charged in the capacitor C 1  is outputted as an output voltage to the output terminal OUT.  
         [0033]     The transmission gate TG 6 , which is turned on by the inverted switch signal SW, will connect the nodes N 9  and N 1 . The transmission gate TG 8 , which is turned off, will block the output voltage at the output terminal OUT being applied back to the gate of the PMOS transistor  422 . Therefore, the problem of the voltage spike will be eliminated. That is, no offset voltage is coupled from the parasitic capacitance.  FIG. 5  is a circuit diagram of a sample and hold circuit  500  showing a second embodiment of the invention and component elements similar to those in  FIG. 4  are designated by the same reference numerals. The sample and hold circuit  500  has an input terminal  401  to which an input voltage IN is applied and a control terminal  402  to which a switching signal SW is supplied. The input terminal  401  is connected to nodes N 1  and N 2  through switches, for example, transmission gates TG 1  and TG 2 , respectively. The capacitors C 1  and C 2  to hold the input voltage IN are connected between the nodes N 1  and N 2  and a ground GND, respectively. Non-inverting input terminals (+) of differential input units  410  and  420  are connected to the nodes N 1  and N 2 , respectively. Each of the differential input units  410  and  420  outputs a voltage corresponding to a potential difference between the non-inverting input terminal and an inverting input terminal (−). Inverting input terminals (−) of differential input units  410  and  420  are connected to the nodes N 13  and N 14 , respectively, as shown in  FIG. 5 . The structures of the differential input units  410  and  420  are similar with these as shown in  FIG. 4  except for these transmission gates TG 5  and TG 6  incorporated in the sample and hold circuit  500 .In the embodiment, the transmission gate TG 5  is incorporated between the node N 1 , which is the non-inverting input terminal of the differential input unit  410 , and the node N 13 , which is the inverting input terminal of the differential input unit  410 , and is controlled by the switching signal SW. The transmission gate TG 6  is incorporated between the node N 2 , which is the non-inverting input terminal of the differential input unit  420 , and the node N 14 , which is the inverting input terminal of the differential input unit  420 , and is controlled by the inverted switching signal SW.  
         [0034]     The operation will now be described. When the switching signal SW is at the “H” level, the transmission gates TG 1 , TG 4 , TG 5 , TG 8  are turned ON and the other transmission gates TG 2 , TG 3 , TG 6  and TG 7  are turned OFF. Thus, the input voltage IN applied to the input terminal  401  is charged into the capacitor C 1  through the transmission gate TG 1  and supplied to the non-inverting input terminal of the differential input unit  410 . The capacitor C 1  is in a sampling phase. Since the output voltage at the output terminal OUT is applied to the inverting input terminal of the differential input unit  410  through transmission gate TG 7 , which is turn OFF, the inverting input terminal of the differential input unit  410  is blocked from the output voltage from the output terminal OUT. Therefore, the voltage spike is eliminated, no offset voltage is coupled from parasitic capacitance. However, since the transmission gate TG 3  is in the OFF state, it is not outputted to the node N 15 .  
         [0035]     Since the transmission gate TG 4  is turned on, the differential input unit  420  is connected to the output unit  430 . A voltage follower circuit having a voltage amplification factor  1  is constructed by both of the units  420  and  430 . Thus, the voltage charged in the capacitor C 2  is generated as an output voltage to the output terminal OUT. During the sampling phase on the capacitor C 1 , the transmission gate TG 5 , which is turned on by the switch signal SW, will connect the nodes N 1  and N 13 . That means that no voltage drop between the two ports of the transmission gate TG 5 , because the ideal infinite resistance seen into gates. The transmission gate TG 7 , which is turned off, will also block the output voltage at the output terminal OUT being applied back to the gate of the PMOS transistor  412 . Therefore, the problem of the voltage spike will be eliminated. That is, no offset voltage is coupled from the parasitic capacitance.  
         [0036]     Subsequently, when the switching signal SW is set to “L”, the transmission gates TG 1 , TG 4 , TG 5 , TG 8  are turned OFF and the other transmission gates TG 2 , TG 3 , TG 6  and TG 7  are turned ON. Thus, the input voltage IN applied to the input terminal  401  is charged into the capacitor C 2  through the transmission gate TG 2  and supplied to the non-inverting input terminal of the differential input unit  420 . At this time, since the TG 4  is in the OFF state, the input voltage IN is not outputted to the output terminal OUT. On the other hand, since the TG 3  is turned on, the differential input unit  410  is connected to the output unit  430 , thereby constructing a voltage follower circuit. Thus, the voltage charged in the capacitor C 1  is outputted as an output voltage to the output terminal OUT.  
         [0037]     The transmission gate TG 6 , which is turned on by the inverted switch signal SW, will connect the nodes N 2  and N 14 . That means that no voltage drop between the two ports of the transmission gate TG 6 , because the ideal infinite resistance seen into gates. The transmission gate TG 8 , which is turned off, will also block the output voltage at the output terminal OUT being applied back to the gate of the PMOS transistor  422 . Therefore, the problem of the voltage spike will be eliminated. That is, no offset voltage is coupled from the parasitic capacitance.  
         [0038]      FIG. 6  is a circuit diagram of a sample and hold circuit  600  showing a third embodiment of the invention and component elements similar to those in  FIG. 4  are designated by the same reference numerals. The sample and hold circuit  600  has an input terminal  401  to which an input voltage IN is applied and a control terminal  402  to which a switching signal SW is supplied. The input terminal  401  is connected to nodes N 1  and N 2  through switches, for example, transmission gates TG 1  and TG 2 , respectively. The capacitors C 1  and C 2  to hold the input voltage IN are connected between the nodes N 1  and N 2  and a ground GND, respectively. Non-inverting input terminals (+) of differential input units  410  and  420  are connected to the nodes N 1  and N 2 , respectively. Each of the differential input units  410  and  420  outputs a voltage corresponding to a potential difference between the non-inverting input terminal and an inverting input terminal (−). Inverting input terminals (−) of differential input units  410  and  420  are connected to the nodes N 13  and N 14 , respectively, as shown in  FIG. 6 . The structures of the differential input units  410  and  420  are similar with these as shown in  FIG. 4  except for these transmission gates TG 5  and TG 6  incorporated in the sample and hold circuit  600 .  
         [0039]     In the embodiment, the transmission gate TG 5  is incorporated between the input terminal  401  (to another input MOS transistor) and the node N 13 , which is the inverting input terminal of the differential input unit  410 , and is controlled by the switching signal SW. The transmission gate TG 6  is incorporated between the input terminal  401  and the node N 14 , which is the inverting input terminal of the differential input unit  420 , and is controlled by the inverted switching signal SW. The topology can avoid the charge injection which is induced from the transmission gates TG 5  and TG 6  as shown in the second embodiment. Because one port of the CMOS switches (for example, the transmission gates TG 5  and TG 6 ) is connected to a low impedance voltage source IN, therefore, most of the channel charges of the transmission gates TG 5  and TG 6  will inject into low impedance voltage source IN. A more correct voltage is outputted from the sample and hold circuit  600  to, for example, the panel loading of a flat panel display.  
         [0040]      FIG. 7 ( a ) and  7 ( b ) are showing an analog type liquid crystal display driving method which uses the sample and hold circuit of the present invention. A plurality of sample and hold circuits (which is denoted as “SH” in  FIG. 7 ( a )) of the present invention are connected to R, G, B analog signal inputs and a switch signal SW. Token as a sampling phase, which is controlled by the shift register  710 , the switch signal SW control switch two input stages, including the sampling phase and the holing phase. As shown in  FIG. 7 ( b ), a plurality of tokens, from token  1  to token n in the shift register  710 , are sequentially activated for sampling in the driving method.  
         [0041]     The above description provides a full and complete description of the preferred embodiments of the present invention. Various modifications, alternate construction, and equivalent may be made by those skilled in the art without changing the scope or spirit of the invention. Accordingly, the above description and illustrations should not be construed as limiting the scope of the invention which is defined by the following claims.