Abstract:
A class-G amplifier comprises first, second and third terminals connected to a load, first supply voltage (V 1 ) and second supply voltage (V 2 ), respectively, where V 2  &gt;V 1 . First (T 1 ) and second (T 2 ) transistors are series-connected between the first and third terminals with the collector of T 1  coupled via first diode (D 1 ) to the second terminal. A third emitter follower transistor (T 3 ) has a B/E junction coupled between a signal input terminal and base of T 1 . A first current source (5) couples the third terminal and third transistor. A driver circuit includes a first current path between the third terminal and emitter of T 3  comprising, in series, a second current source (7), a fourth transistor (T 5 ) and second diode (D 4 ). A second current path between a junction point (3) and common point (11) comprises, in series, third (D 2 ) and fourth (D 3 ) diodes and a third current source (8). Base of fourth transistor is connected to junction (9) and its collector is connected to third current source via fifth diode (D 5 ). A low input voltage cuts off second transistior so first transistor connected to second terminal. Above a given voltage, driver circuit turns second transistor on so first transistor connected to third terminal. The output (2) thereby attains a voltage equal to second supply voltage (V 2 ) minus one B/E voltage.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to an amplifier arrangement comprising: 
     a first transistor having an emitter which is coupled to a first terminal for connection to a load which is coupled to a reference point, and having a collector which is coupled by means of a first semiconductor junction to a second terminal for a first supply voltage, 
     a second transistor having a collector-emitter path which is connected in series with the collector-emitter path of the first transistor, and having a collector which is coupled to a third terminal for a second supply voltage which is higher than the first supply voltage, and 
     a third transistor arranged as an emitter-follower and having a base for receiving an input signal and having an emitter which is coupled to the base of the first transistor. 
     The invention also relates to a push-pull amplifier equipped with such an amplifier arrangement. 
     Such an amplifier arrangement of the class-G type may be employed as a power amplifier for audio signals. A class-G amplifier is to be understood to mean an amplifier in which the effective supply voltage increases in a number of steps depending on the input signal. This results in an amplifier having a high efficiency. 
     Such an amplifier arrangement is disclosed in U.S. Pat. No. 3,961,280. In this known arrangement the input signal is applied to the bases of the first transistor and the second transistor via a third transistor arranged as an emitter follower. For low input voltages the second transistor is cut off so that the first transistor is connected to the first supply voltage. If the input voltage becomes higher than the first supply voltage, the second transistor is turned on so that the first supply voltage is disconnected and the first transistor is connected to the second supply voltage. 
     When the second transistor does not conduct, the voltage across the base-emitter junction of this transistor is at the most equal to substantially the full first supply voltage. In order to preclude breakdown of the base-emitter junction as a result of this voltage, a diode is arranged in the base line of the second transistor. In order to prevent the first transistor from being bottomed and thereby producing distortion when the second transistor is not yet fully conductive, two series-connected diodes are arranged in the base line of the first transistor. 
     However, a drawback of these diodes is that they limit the swing of the output signal and, consequently, the efficiency of the amplifier arrangement. For the maximum output the voltage on the base of the third transistor is substantially equal to the second supply voltage. The voltage on the output is then equal to the second supply voltage minus the sum of the base-emitter voltage of the first transistor and the third transistor and the diode voltage across the two diodes arranged in the base line of the first transistor. 
       SUMMARY OF THE INVENTION 
     It is an object of the invention to provide a class-G-type amplifier arrangement which has an improved output-voltage swing in comparison with the known arrangement. In accordance with the invention an amplifier arrangement of the type defined in the opening paragraph is characterized in that 
     the third transistor is of a conductivity type opposite to that of the first transistor and the second transistor and its emitter is coupled to the third terminal by means of a first current source, 
     a first current path is arranged between the third terminal and an electrode of the third transistor which carries the input signal, which first current path comprises the series arrangement of at least a second current source, the emitter-collector path of a fourth transistor of the same conductivity type as the third transistor, and a second semiconductor junction, 
     the emitter of the fourth transistor is coupled to the base of the second transistor, 
     a second current path is arranged between the second terminal and the reference point and comprises the series arrangement of a third semiconductor junction, a fourth semiconductor junction and a third current source, 
     a point between the collector of the fourth transistor and the second semiconductor junction is connected to the third current source by means of a fifth semiconductor junction, and 
     the base of the fourth transistor is connected to a point between the third semiconductor junction and the fourth semiconductor junction. 
     In such an amplifier arrangement it is possible to drive the output to a voltage equal to the second supply voltage minus the sum of one base-emitter voltage and two saturation voltages, which yields a substantially improved output voltage swing and hence a substantially improved efficiency. The amplifier arrangement also has the advantage that it can be fully integrated. 
     In an amplifier arrangement in accordance with the invention, the first transistor and the second transistor are each preferably constituted by a Darlington pair. The maximum output voltage swing is then one base-emitter voltage lower than in the case of single first and second transistors. In this case the maximum output voltage swing can be increased by one base-emitter voltage by bootstrapping. In accordance with a further embodiment the amplifier arrangement may then be characterized in that the first current source and the second current source are connected to the third terminal by means of a first resistor and the first terminal is connected to that end of the first resistor which is not connected to the third terminal by means of a capacitor. This embodiment may be characterized in that the first current source and the second current source are constituted by a second resistor and a third resistor, respectively. 
     An amplifier arrangement in accordance with a further embodiment of the invention may be characterized in that the second semiconductor junction is the emitter-base junction of a sixth transistor arranged as an emitter follower. This precludes the occurrence of distortion as a result of a sudden decrease in input resistance of the arrangement when the second transistor is turned on. 
     An amplifier arrrangement in accordance with the invention is very suitable for use in a push-pull amplifier which comprises two complementary amplifier arrangements in which the emitters of the complementary first transistors are connected to a common first terminal for connection to a common load. This push-pull amplifier may be characterized further in that the third current sources of the two complementary amplifier arrangements are commoned to form one common current source and in that the collectors of the third transistors are coupled to the common first terminal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Embodiments of the invention will now be described in more detail, by way of example, with reference to the accompanying drawings, in which: 
     FIG. 1 is the basic diagram of an amplifier arrangement in accordance with the invention, 
     FIG. 2 shows a modification of the arrangement of FIG. 1, 
     FIG. 3 shows an extended version of the amplifier arrangement of FIG. 1, 
     FIG. 4 shows a push-pull amplifier in accordance with a first embodiment of the invention, 
     FIG. 5 shows a push-pull amplifier in accordance with a second embodiment of the invention, 
     FIG. 6 shows a push-pull amplifier in accordance with a third embodiment of the invention, 
     FIG. 7 shows a push-pull amplifier in accordance with a fourth embodiment of the invention, and 
     FIG. 8 shows the amplifier of FIG. 1 which uses FET transistors T 1  and T 2 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows the basic diagram of an amplifier arrangement in accordance with the invention. The arrangement comprises a first NPN transistor T 1 , whose emitter is connected to the output 2 to which a load R L  is connected. By means of a first diode D 1  the collector of the transistor T 1  is connected to a terminal 4 for a first supply voltage V 1 . The collector-emitter path of a second NPN transistor T 2  is arranged in series with the collector-emitter path of the transistor T 1  and the collector of this transistor T 2  is connected to a terminal 10 for a second supply voltage V 2  which is higher than the first supply voltage V 1 . The base of the transistor T 1  is connected to the emitter of a PNP transistor T 3 , arranged as an emitter follower. The emitter of this transistor is connected to the terminal 10 for the supply voltage V 2  by means of a first current source 5 supplying a current I 1 . The current source 5 comprises a PNP transistor T.sub. 6 whose base is at a reference voltage V R . The collector of the transistor T 3  is connected to the terminal 11 which is common to the first supply voltage V 1  and the second supply voltage V 2 . The input signal V i  is applied to the base 6 of the transistor T 3 . A first current path is arranged between the terminal 10 for the supply voltage V 2  and the emitter of the transistor T 3  and comprises the series arrangement of a second current source 7, the emitter-collector path of a PNP transistor T 5  and a second diode D 4 . The second current source supplies a current I 2  and comprises a PNP transistor T 4  whose base is at the reference voltage V R . The emitter of the transistor T 5  is connected to the base of the transistor T 2 . A second current path is arranged between the junction point 3 between the transistor T 1  and the transistor T 2  and the common terminal 11 and comprises the series arrangement of a third diode D 2 , a fourth diode D 3  and a third current source 8. The current I 3  carried by this current source is smaller than the current I 2  supplied by the current source 7. The base of the transistor T 5  is connected to the junction point 9 between the diodes D 2  and D 3  and its collector is connected to the current source 8 by means of a fifth diode D 5 . 
     The arrangement operates as follows. For low input voltages V i  the transistor T 3  receives the current I 1  from the current source 5 directly and the current I 2  from the current source 7 via the collector-emitter path of the transistor T 5  and the diode D 4 . If the base current of the transistor T 5  is ignored the current I 3  carried by the current source 8 is furnished by the first power supply voltage V 1  via the diodes D 1 , D 2  and D 3 . In this situation the diode D 5  is cut off. The voltage between the base and the emitter of the transistor T 2  is substantially O V because this voltage is equal to the difference between the base-emitter voltage of the transistor T 5  and the voltage across the diode D 2 . Consequently, the transistor T 2  is cut off so that for low input voltages the collector of the transistor T 1  is connected to the power supply voltage V 1  via the diode D 1 . The input signal V i  is applied to the base of the transistor T 1  via the emitter-follower transistor T 3 . This input signal V i  also appears on the anode of the diode D 5 . The voltage on the cathode of the diode D 5  is three diode voltages lower than the supply voltage V 1 . Therefore, the diode D 5  is turned on for a specific input voltage V i . A part of the input voltage V i  then appears on the cathode of the diode D 2 . As the input voltage V i  increases further the diode D 2  will become less conductive, so that the current for the current source 8 through the diode D 3  decreases and that through the diode D 5  increases. Above a specific input voltage the diode D 2  is turned off so that substantially the entire current I 3  flows through the diode D 5 . Then only the base current of the transistor T 5  flows through the diode D 3 . The voltage on the base of the transistor T.sub. 2 follows the voltage V i  via the base-emitter junction of the transistor T 5 , the diodes D 3 , D 5  and D 4 , and the base-emitter junction of the transistor T 3 . As this input voltage increases further the transistor T 2  is therefore turned on so that the voltage on the junction point 3 also increases. At a specific input voltage the diode D 1   is cut off so that the collector of the transistor T 1  is connected to the high supply voltage V 2  via the collectoremitter path of the transistor T 2 . As the input voltage V i  increases further the transistor T 4  will be bottomed, so that the voltage on the base of the transistor T 2  cannot increase any further. Subsequently, the transistor T 1  is bottomed and the diode D 4  is cut off. The entire current I 1  from the current source 5 then flows into the base of the transistor T 1  so that there is no current in the transistor T 3 . 
     The maximum output voltage is then reached. The voltage V O  on the output 2 is now equal to: 
     
         V.sub.OMAX =V.sub.2 -(V.sub.CEST4 +V.sub.BET2 +V.sub.CEST1) (1) 
    
     where 
     V CEST4  =the collector-emitter voltage of the transistor T 4  during saturation, 
     V CEST1  =the collector-emitter voltage of the transistor T 1  during saturation, and 
     V BET2  =the base-emitter voltage of the transistor T 2 . 
     As the voltage V CEST4  and V CEST1  are substantially 100 mV, it follows from the above equation that the output 2 can be driven to the value of the second supply voltage V 2  minus substantially one base-emitter voltage (≈0.6 V). As a result of this large output voltage swing the amplifier arrangement has a high efficiency. 
     FIG. 2 is a modification of the arrangement shown in FIG. 1 in which identical parts bear the same reference numerals as in FIG. 1. During the change-over from the first supply voltage V 1  to the second supply voltage V 2  the voltage between the collector and the base of the transistor T 1  in the arrangement shown in FIG. 1 is equal to one diode voltage, namely the sum of the voltages across the diodes D 4 , D 5 , D 3  and the base-emitter junctions of the transistors T 5  and T 2 . This means that during change-over to the second supply voltage V 2  the first transistor T 1  is not yet driven into full conduction. In the embodiment shown in Fig.2, the diode D 4  is replaced by the base-emitter junction of a transistor T 30 , which has its emitter connected to the collector of the ttansistor T 5 , its base to the base of the transistor T 3 , and its collector to the common terminal 11. During the change-over from the first supply voltage V 1  to the second supply voltage V 2  a voltage of zero volts appears between the collector and the base of the transistor T 1  so that change over is effected at the instant at which the transistor T 1  will be saturated. As a result of this, the transistor T 1  is driven over the entire range of the first supply voltage V 1 , which leads to an increased efficiency. Otherwise, the operation and the output voltage swing of the arrangement are the same as for the arrangement shown in FIG. 1. 
     The principle of two supply voltages as explained with reference to FIGS. 1 and 2 may be extended to an arbitrary number of supply voltages. Fig.3 shows an amplifier arrangement with three supply voltages, in which Figure identical parts bear the same reference numerals as in Fig.1. A transistor T 21  has its collector-emitter path connected in series with the collector-emitter path of the transistor T 2  and has its collector connected to a third supply voltage V 3 . The collector of the transistor T 2  is now connected to the second supply voltage V 2  via a diode D 21  and the current source 7 is connected to the third supply voltage V 3 . The driver circuit for the transistor T 21  is of the same type as that for the transistor T 2 . A current source 27 supplying a current I 20  is arranged between the third power supply voltage V 3  and the base of the transistor T 21 . This current source 27 comprises a transistor T 24 , whose base is at a reference voltage V R . The base of the transistor T 21  is connected to the base of the transistor T 2  by the series arrangement of the emitter-collector path of a transistor T 25  and a diode D 24 . The series arrangement of two diodes D 22 , D 23  and a current source 28 carrying a current I 23  is arranged between the junction point 33 between the emitter of the transistor T 21  and the collector of the transistor T 2  and the common terminal 11. The base of the transistor T 25  is connected to the junction point 29 between the diode D 22  and the diode D 23  and the collector of the transistor T 25  is connected to the current source 28 by means of a diode D 25 . 
     The operation of the circuit arrangement can be explained very simply by means of the principle described with reference to Fig.1. For low input voltages V i  the transistor T 1  is coupled to the first supply voltage V 1 . The transistors T 2  and T 21  and the diodes D 5  and D 25  are cut off. The current I 20  from the current source 27 flows to the emitter of the transistor T 5  via the emitter-collector path of the transistor T 25  and the diode D 24  and further to the emitter of the transistor T 3  via the emitter-collector path of the transistor T 5  and the diode D 4 . The current I 23  carried by the current source 28 is derived from the supply voltage V 2  via the diodes D 23 , D 22  and D 21 . At increasing input voltages V i  the transistor T 2  is driven into conduction and the first supply voltage V 1  is disconnected, as described with reference to Fig.1. At a further increase the transistor T 2  is driven further into conduction. Above a specific input voltage V i  the diode D 25  is turned on. As a result of this, the transistor T 21  is turned on and the diode D 22  is turned off, so that above a specific input voltage the second supply voltage V 2  is disconnected and the collector of the transistor T 1  is coupled to the third supply voltage V 3 . As the input voltage V i  increases further the transistor T 24  is bottomed. The voltage on the base of the transistor T 21  then cannot increase any further. If the input voltage V i  increases even further, the diode D 24  is cut off, after which the transistor T 2  is bottomed, in which situation the voltage on the base of the transistor T 2  can increase until the transistor T 4  is bottomed. Subsequently, the diode D 4  is cut off and the transistor T 1  is saturated. As a result of this, there is no current in the transistor T 3  so that the maximum output voltage is reached. The maximum voltage V 0  on the output 2 is then equal to: 
     
         V.sub.OMAX =V.sub.3 -(V.sub.CEST24 +V.sub.BET21 +V.sub.CEST2 +V.sub.CEST1) (2) 
    
     where 
     V CEST24  =the collector-emitter voltage of the transistor T 24  in the case of saturation. 
     It is to be noted that in the present embodiment the diode D 4  may be connected to the collector of the transistor T 5  instead of to the emitter. As a result of this, the change-over from the second supply voltage V 2  to the third supply voltage V 3  is effected at the instant at which the transistor T 2  is saturated, so that the transistor T 2  is driven to an optimum extent. 
     The amplifier arrangement in accordance with the invention is very suitable for use in a push-pull amplifier, of which FIG. 4 shows a first embodiment. The push-pull amplifier comprises an input stage, which in the present embodiment has its simplest form and comprises two transitors T 11  and T 12  arranged as a differential pair, whose common emitter terminal is connected to the positive second supply voltage +V by means of a current source comprising a transistor T 10  whose base is at a reference voltage V R . The input signal V ii  of the push-pull amplifier is applied between the bases of the transistors T 11  and T 12 . The collector of the transistor T 12  is connected directly to the output of the input stage and the collector of the transistor T 11  is connected to the said output by means of a current mirror comprising the transistors T 13  and T 14 , which output is connected to the input of a Miller stage. In the present example, the Miller stage comprises a transistor T 15 , whose emitter is connected to the negative supply voltage -V 2 . A frequency compensation capacitor C 1  is arranged between the collector and the base of the transistor T 15 . The collector of the transistor T 15  is connected to the positive supply voltage +V 2  by the series arrangement of two diodes D 6  and D 7  and a current source comprising the transistor T 9 , whose base is at a reference voltage V R . The output stage comprises two complementary circuits, which are each substantially identical to the circuit arrangement shown in FIG. 1. Therefore, identical parts bear the same reference numerals as in FIG. 1, the complementary parts being denoted by primes. The arrangement differs from that shown in FIG. 1 with respect to the following points. The transistor T 2  and the transistor T 8  are arranged as a Darlington pair, a resistor R 1  being arranged between the base and the emitter of the transistor T 2  to provide a rapid turn-off of the Darlington pair. A resistor or a diode may be arranged between the base and the emitter of the transistor T 8  for protection purposes, and in the case of a diode its forward direction should be opposite to that of the base-emitter junction of the transistor T 8 . Similarly, the transistor T 1  forms a Darlington pair with a transistor T 7 . The emitters of the complementary output transistor T 1  and T 1  &#39; are connected to the common output 2, to which the load R L  is connected. A resistor R 2  is arranged between the emitters of the transistors T 7  and T 7  &#39; and has the same function as the resistor R 1 . The current source 8 is common to the two complementary circuits. 
     The collectors of the transistors T 3  and T 3  &#39; are interconnected and are also connected to the output 2. It is to be noted that the collectors of the transistors T 3  and T 3  &#39; may alternatively be connected to the emitter of the transistor T 7  &#39; and the emitter of the transistor T 7 , respectively or, if resistors having low resistance values are arranged in the emitter lines of the transistors T 1  and T 1  &#39;, to the emitter of the transistor T 1  &#39; and the emitter of the transistor T 1 , respectively. The output signal of the Miller stage is applied to the bases of the transistors T 3  and T 3  &#39;. The diodes D 6  and D 7  between the bases of the transistors T 3  and T 3  &#39; provide a class-AB bias for the output stage. The push-pull principle is known per se and therefore will not be explained here. Since the transistor T 2  and the transistor T 8  are arranged as a Darlington pair, the maximum output voltage swing is now equal to: 
     
         V.sub.OMAX =+V.sub.2 -(V.sub.CEST4 +V.sub.BET8 +V.sub.BET2 +V.sub.CEST1) (3) 
    
     Consequently, the maximum output voltage is one baseemitter voltage lower than for the arrangement in FIG. 1. The minimum output voltage lies equally far above the negative supply voltage -V 2  as the maximum output voltage lies below the positive supply voltage +V 2 . 
     A second example of a push-pull amplifier in accordance with the invention is described with reference to FIG. 5. For simplicity only the output stage, which is relevant to the invention, is shown, and identical parts bear the same reference numerals as in FIG. 4. The emitters of the transistors T 4  and T 6  are connected to the terminal 10 for the supply voltage +V 2  by means of a resistor R 3 . A capacitor C 2  is arranged between the output 2 and the end 15 of the resistor R 3  which is not connected to the terminal 10. By means of the capacitor C 2  the output signal is boot-strapped so that the voltage on the collectors of the transistors T 4  and T 6  can be raised above the supply voltage +V 2 . As far as the operation of the arrangement is concerned this results in the transistor T 8 , instead of the transistor T 4 , being saturated when the transistors T 8  and T 2  are turned on as a result of an increasing input signal. The collector of the transistor T 8  is now connected to the supply voltage +V 2 , while as a result of bootstrapping the base of the transistor T 8  can be driven beyond this supply voltage. Therefore, the maximum output voltage becomes equal to: 
     
         V.sub.OMAX =V.sub.2 -(V.sub.CEST8 +V.sub.BET2 +V.sub.CEST1) (4) 
    
     where 
     V CEST8  =the collector-emitter voltage of the transistor 
     T 8  in the case of saturation. 
     Bootstrapping results in an increase of the maximum output voltage swing of the arrangement by one base-emitter voltage. It is to be noted that in the present embodiment the current-source transistor T 10  of the input stage (see FIG. 4) is connected directly to the positive second supply voltage +V 2  and that the emitters of the transistors T 13 , T 14  and T 15  are connected directly to the negative supply voltage -V 2 . 
     A third embodiment of a push-pull amplifier is described with reference to FIG. 6, in which identical parts bear the same reference numerals as in FIG. 5. In the present embodiment the current-source transistors T 4  and T 6  are replaced by a resistor R 4  and a resistor R 5 , respectively. As a result of bootstrapping the same signal voltage appears on the base of the transistor T 8  and on the cathode of the diode D 4  as on point 15. Consequently, a constant voltage is obtained across these resistors, so that the resistors R 4  and R 5  again operate as current sources. 
     FIG. 7 shows a push-pull amplifier in accordance with the fourth embodiment of the invention, and identical parts bear the same reference numerals as in FIG. 6. This embodiment differs from that shown in FIG. 6 in that the diode D 4  is replaced by an emitter-follower transistor T 16 , whose emitter is connected to the collector of the transistor T 5 , whose collector is connected to the negative supply voltage -V 2 , and whose base is connected to the emitter of the transistor T 3 . When, in the embodiment shown in FIG. 4, the transistors T 8 , T 2  are turned on the resistance at the emitter of the transistor T 3  decreases suddenly because the resistance which is seen at the base of the transistor T 8  is connected in parallel with the resistance which is seen at the base of the transistor T 7 . This results in a sudden decrease of the input resistance of the arrangement, which leads to distortion of the input signal. By replacing the diode D 4  by a transistor T 16 , the resistance which is connected in parallel with the input resistance of the transistor T 7  when the transistors T 8 , T 2  are turned on is increased by a factor equal to the currentgain factor of the transistor T 16 . Thus, when the transistors T 8 , T 2  are turned on the decrease in the input resisresistance of the transistor T 3  is substantially smaller, so that the resulting distortion is also reduced substantially. It is to be noted that the emitter-follower transistor T 16  may also be used in the embodiments shown in FIGS. 1, 2 and 3. 
     The invention is not limited to the embodiments shown. Within the scope of the invention many modifications will become obvious to those skilled in the art. For example, the diodes in the present embodiments may be replaced by diode-connected transistors. Further, all or some of the bipolar transistors in the arrangement, as shown, for example, in FIG. 8, may be replaced by MOS transistors, in which case &#34;emitter&#34;, &#34;collector&#34; and &#34;base&#34; should read: &#34;source&#34;, &#34;drain&#34; and &#34;gate&#34;, respectively. 
     Finally, it is to be noted that the embodiments shown in FIGS. 4, 5, 6 and 7 may also be equipped with the amplifier arrangement shown in FIG. 3.