Abstract:
An accelerated operating system can increase the data processing throughput of a data processor executing an application according to a sequential programming model. An application running on a main data processor is interfaced to an operating system which has been accelerated by distributing at least some of the operating system among a plurality of subordinate data processors which provide data processing support for the application running on the main data processor. The subordinate data processors can thus also provide operating system support for the application running on the main data processor. This decreases the processing burden on the main data processor, thereby increasing the main data processor&#39;s data processing throughput while executing the application.

Description:
CROSS-REFERENCE TO RELATED APPLICATION AND CLAIM OF PRIORITY  
       [0001]     The present invention claims the priority under 35 USC § 119(e) of the following co-pending U.S. Provisional Applications:  
         [0002]     1) U.S. Provisional Patent Application Ser. No. 60/575,589, entitled “DISTRIBUTION OF OPERATING SYSTEM FUNCTIONS IN THE ORION HIGH CAPACITY I/O PROCESSOR,” filed on May 27, 2004; and  
         [0003]     2) U.S. Provisional Patent Application Ser. No. 60/575,590 entitled “HIGH PERFORMANCE ASYMMETRIC MULTI-PROCESSOR WITH SEQUENTIAL PROGRAMMING MODEL,” filed May 27, 2004.  
         [0004]     The subject matter disclosed in each of Patent Application Ser. Nos. 60/575,589 and 60/575,590 is hereby incorporated by reference into the present disclosure as if fully set forth herein.  
     
    
     TECHNICAL FIELD OF THE INVENTION  
       [0005]     The invention relates generally to data processing and, more particularly, to increasing data processing throughput in a data processing architecture.  
       BACKGROUND OF THE INVENTION  
       [0006]     Various approaches have been used to increase data processing throughput in data processing architectures. These approaches are briefly described below.  
         [0007]     Vector computers and hardware use a pipelining approach, where the data is sequentially presented to a line of processing entities, called stages, where each processing entity performs a single or a small set of operations on each piece of data as it passes through. Data is fully processed only after it has passed through all stages. Thus, parallel processing occurs by having each processor perform the same operation on each piece of data flowing through it, where each stage of the pipeline operates simultaneously on different pieces of data. For example, Stage N operates on data i, Stage N-1 operates on data i+1, Stage N-2 operates on data i+2, and so on down to Stage 0. This is well suited to processing arrays.  
         [0008]     Superscalar computers, such as the Pentium Pro and the PowerPC, support a combination of vector and software pipelining, which amount to handling more than one instruction at a time by preloading the next instruction while operating on the current one and by using a fine grain scheduling technique along with instruction ordering techniques to parallelize loops such that one iteration of a loop can begin execution before the previous one completes.  
         [0009]     Automatic parallelism typically is achieved in compilers by parallelizing array operations either by parallelizing loops, in a manner similar to software pipelining, or by parallelizing intrinsically parallel array operations.  
         [0010]     It is simple to allow parallel processors to run different programs. Also, some classes of problems, such as code breaking programs and graphics rendering, can be easily separated to explore different portions of the solution space by allocating portions to each of the parallel processors.  
         [0011]     Some parallel computing approaches use a distributed cluster of machines that are autonomous computing nodes, each with its own memory, operating system, and disk space. These approaches also use message passing to coordinate the processing. An example of this is the Search for Extra-Terrestrial Intelligence (SETI) At Home project, where screen savers on home computers receive computational tasks over the internet and e-mail any interesting findings back to the main facility. There are two approaches to distributed cluster processing—each processor executing the same program on different sets of data and different processors executing different programs on different sets of data.  
         [0012]     Shared Memory Processors or Symmetric Multi-Processors (SMP) refer to single computers with multiple processors. The processors may run different programs or a single program can run in parallel across the processors. Parallelizing a single program requires special processing techniques, including message passing between the processors or use of shared memory to coordinate activities. Synchronization techniques are required to coordinate the asynchronous processors to maintain the logical dependence and required order of precedence.  
         [0013]     Another approach to parallel computing is the Single Instruction Multiple Data (SIMD) approach where one instruction unit runs a large array of processors in lock-step. The instruction unit controls the entire array by fetching each instruction and commanding each processor in the array to carry it out, each with its own data. This approach is implemented in supercomputers such as the Control Data Systems CDC 6600 and 7600 and in Cray supercomputers via a technique called vector processing.  
         [0014]     Another multi-processor architecture known as the Asymmetric Multi-Processor Operating System (“AsyMOS”) has been developed to exploit cost/performance advantages that accrue to small scale SMPs due to shared memory and packaging. In this architecture, the multiple processors are partitioned into three (3) types, applications processors, disk processors, and device processors, based on the end functionality that they will perform. By virtue of this partition, specific network and disk processing can be off-loaded from the applications processors that are running the main applications.  
         [0015]     The aforementioned vector processing and SIMD approaches are only applicable to certain kinds of problems, such as array processing. They work best if the problem is formulated in an appropriate manner, for example, by using vector algebra cronstructs. The SMP approach works best if different programs are run on different processors. If an application is not readily separated into different parts, then parallel processing may require special structuring of the problem, or the application may need to be written specifically for the parallel processing environment. This can entail the use of specific parallel processing code with message passing to coordinate the activities of the various processors as they operate in parallel.  
         [0016]     It is desirable in view of the foregoing to provide for increasing the data processing throughput of data processing architecture without requiring parallel processing techniques and their attendant difficulties.  
       SUMMARY OF THE INVENTION  
       [0017]     The present invention provides a data processing architecture with an accelerated operating system to increase the data processing throughput of an application executed according to a sequential programming model. An application running on a main data processor is interfaced to the operating system. By distributing at least some of the operating system among a plurality of subordinate data processors which provide data processing support for the application running on the main data processor, exemplary embodiments of the present invention permit the subordinate data processors to also provide operating system support for the application running on the main data processor. This off-loading of operating system functionality from the main data processor increases the data processing throughput of the main data processor.  
         [0018]     To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide an improved data processing apparatus. According to an advantageous embodiment of the present invention, the data processing apparatus comprises: 1) a main data processor capable of running an application; 2) a plurality of subordinate data processors which provide data processing support for the application running on the the main data processor; 3) a plurality of communication paths which respectively couple the subordinate data processors to the main data processor; and 4) an operating system, and an application interface which interfaces the application to the operating system, the application interface provided on the main data processor. At least some of the operating system is distributed among the subordinate data processors such that the subordinate data processors also provide operating system support for the application running on the main data processor.  
         [0019]     According to one embodiment of the present invention, the main data processor runs the application according to a sequential programming model.  
         [0020]     According to another embodiment of the present invention, the subordinate data processors provide the data processing support for the application running on the main data processor by inputting and outputting data from and to a site located physically separately from the data processing apparatus.  
         [0021]     According to still another embodiment of the present invention, the at least some of the operating system includes an operating system function that is accessed relatively frequently by the application running on the main data processor.  
         [0022]     According to yet another embodiment of the present invention, the operating system function includes one of an IP stack, a dispatcher, a scheduler, and a virtual memory paging function.  
         [0023]     According to a further embodiment of the present invention, the operating system is a Linux operating system.  
         [0024]     According to a still further embodiment of the present invention, the subordinate data processors execute program instructions to provide the data processing support.  
         [0025]     According to a yet further embodiment of the present invention, the application interface renders the distribution of the at least some of the operating system transparent to the application running on the main data processor.  
         [0026]     Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0027]     For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts:  
         [0028]      FIG. 1  illustrates a data processing architecture according to an exemplary embodiment of the invention;  
         [0029]      FIG. 2  illustrates the subordinate processors of  FIG. 1  according to an exemplary embodiment of the invention;  
         [0030]      FIG. 3  illustrates a detailed example of the data processing architecture of  FIG. 1  according to an exemplary embodiment of the invention;  
         [0031]      FIG. 4  illustrates the distributed operating system of  FIG. 1  in more detail according to an exemplary embodiment of the invention; and  
         [0032]      FIG. 5  illustrates an expanded data processing architecture according to an exemplary embodiment of the invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0033]      FIGS. 1 through 5 , discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged data processing architecture.  
         [0034]      FIG. 1  illustrates a data processing architecture according to an exemplary embodiment of the present invention. The data processing architecture  100  includes a main core processor  110 , a plurality of subordinate processors  130 , and memory  120 . The main core processor  110  is coupled by bus structure  140  for communication with the subordinate processors  130  and with memory  120 , and the subordinate processors  130  are also coupled by bus structure  140  for communication with memory  120 . The subordinate processors  130  are cooperable with the main core processor  110  and memory  120  to provide the data processing architecture  100  with channelized I/O as indicated by the multiple I/O channels illustrated generally at  135 . The architecture  100  also includes a distributed operating system  150 , which is described in more detail below.  
         [0035]      FIG. 2  is a simplified diagram illustrating the subordinate processors of  FIG. 1  according to an exemplary embodiment of the invention. The subordinate processor  200  of  FIG. 2  includes registers  210 , a program control unit  220 , an instruction execution unit  240 , and a memory interface  250 . The registers  210 , program control unit  220 , and memory interface  250  are connected to the bus structure  140  for communication with one another, and also with the main core processor  110  and memory  120  (see also  FIG. 1 ). The program control unit  220  appropriately loads instructions and data from memory  120  into the registers  210 .  
         [0036]     In an exemplary embodiment, a plurality of sets of registers at  210  may be used in order to implement a corresponding plurality of execution threads. In such a multiple thread embodiment, a multiplexer  230  is connected between the registers  210  and the instruction execution unit  240 , and the program control unit  220  controls the multiplexer  230  such that the registers associated with the desired thread are connected to the instruction execution unit  240 . In an alternate embodiment, only a single register set and a corresponding single execution thread may be implemented. In such an embodiment, the single register set can be connected directly to the instruction execution unit  240 , as indicated generally by broken line in  FIG. 2 .  
         [0037]     Under control of the program control unit  220 , the instruction execution unit  240  executes the instructions that it receives. Under control of the instruction execution unit  240 , the memory interface  250  reads data from memory  120  via bus structure  140  and outputs the data on I/O channel  260 . Also under control of the instruction execution unit  240 , the memory interface  250  receives data from the I/O channel  260 , and writes the received data into memory  120  via bus structure  140 . Each of the subordinate processors illustrated at  130  in  FIG. 1  implements an I/O channel, such as shown at  260  in  FIG. 2 , thereby providing the multiple-channel, or channelized, I/O  135  in  FIG. 1 .  
         [0038]      FIG. 3  illustrates a detailed example of the data processing architecture of  FIGS. 1 and 2  according to an exemplary embodiment of the invention. In the example of  FIG. 3 , the data processing architecture is utilized as a gateway or file server in a storage area network (SAN)  300 . The main core processor  110  is implemented as an X-SCALE processor in  FIG. 3 , and the subordinate processors  130  are implemented as microengines  130   a,    130   b,  etc. In an exemplary embodiment of the present invention, the X-SCALE processor and microengines are provided in a conventional network processor integrated circuit, such as IXP2800 chips commercially available from Intel Corporation. A single-chip network processor is indicated generally at  330  in  FIG. 3 .  
         [0039]     In  FIG. 3 , the memory  120  of  FIG. 1  includes RDRAM  310 , QDRAM  320  and scratchpad memory  321 . In an exemplary embodiment of the present invention, the scratchpad memory  321  is provided on-chip with the X-SCALE processor and the microengines.  
         [0040]     The data processing architecture  100  is interfaced to a data network  350  and storage arrays  360  and  370  via an ASIC  340  (or an FPGA), Ethernet interfaces  341  and  342 , SCSI interfaces  343   a  and  343   b,  and Fiber Channel (FC) interface  344 . The interfaces at  341 - 344  are well known in the art. The ASIC  340  is designed to interface between the channelized I/O  135  of the data processing architecture  100  and the various interfaces  341 - 344 . For example, in an embodiment which utilizes the IXP2800, the channelized I/O  135  is provided on the SPI-4 Phase 2 (SPI-4.2) I/O bus of the IXP2800. The ASIC  340  would thus interface to the SPI-4.2 bus and fan out the channelized I/O to the various external interfaces at  341 - 344 .  
         [0041]     The QDRAM  320  is used primarily to provide temporary storage of data that is being transferred either to the channelized I/O  135  from the RDRAM  310 , or from the channelized I/O  135  to the RDRAM  310 . A work list is also maintained in the RDRAM  310 . The X-SCALE processor  110  can write commands into this work list, and the microengines  130   a,    130   b,  etc. can access the commands and execute the functions specified by the commands. One embodiment of the present invention may utilize 1-2 megabytes of QDRAM and two (2) gigabytes of RDRAM. In an exemplary embodiment of the present invention, the QDRAM and RDRAM are both provided on a single printed circuit board, together with the single-chip network processor  330 .  
         [0042]     In an exemplary embodiment of the invention, the main core processor  110  stores commands in the work list of the RDRAM  310 . For example, the main core processor could store a plurality of commands which respectively correspond to a plurality of desired storage disk accesses. The commands can indicate, for example, what instructions to execute, where data is (or will be) stored in memory, etc. The subordinate processors, acting independently as they become free to support the main core processor, can retrieve commands from the work list and make disk storage accesses in parallel by using SCSI interfaces  343   a  and  343   b.    
         [0043]     For a write to disk storage, the subordinate processor transfers data from the RDRAM  310  out to the disk storage unit (e.g.  360 ). For a read from disk storage, the subordinate processor transfers data received from the disk storage unit into the RDRAM  310 . These data transfers can be accomplished by the memory interface  250  of  FIG. 2 , under control of the instruction execution unit  240  of  FIG. 2 . This distribution of instruction execution to support I/O processing avoids the bottlenecks that may occur in mainframe or supercomputer architectures, wherein all instructions that control channelized I/O are executed in a single central processor unit, rather than in the I/O channels themselves.  
         [0044]     Similar bottlenecks can of course also occur in conventional PC and other desktop architectures, where all I/O and data processing functionality is controlled by instruction execution performed in the central processing unit. In an exemplary embodiment of the present invention, the main core processor  110  can utilize the bus structure  140  to provide commands directly to the various subordinate processors.  
         [0045]      FIG. 4  illustrates the distributed operating system of  FIG. 1  in more detail according to an exemplary embodiment of the invention. As shown in  FIG. 4 , the main core processor  110  runs applications  410 , for example file server applications. These applications are supported by an operating system that is distributed into and among the subordinate processors  130 . In particular, the main core processor provides an application interface  420 , and may also provide some local operating system functionality  430 . However, the remainder of the operating system functionality is distributed among the subordinate processors  130 . This distribution of operating system functionality among the subordinate processors  130  is indicated generally by the remote operating system functions  450  in  FIG. 4 .  
         [0046]     In an exemplary embodiment of the present invention, the operating system is the well known Linux operating system, and the IP stack functionality of the Linux operating system is distributed into the subordinate processors  130  as a remote operating system function. The IP stack functionality uses a well-defined socket interface that can be easily relocated from the main processor into the subordinate processors  130 . As another example, the Linux scheduler functionality is relatively easy to move because it is triggered by a timer and every system call returns through the scheduler.  
         [0047]     In an exemplary embodiment of the present invention, the applications interface  420  makes the distribution of the operating system into the subordinate processors completely transparent to the applications  410 . Accordingly, the applications  410  can run without modification on the main core processor  110  in the same manner as if the entire operating system were implemented on the main core processor  110 .  
         [0048]     If the distributed operating system is used to handle I/O requests from the main core processor  110 , then the entire I/O process is rendered transparent to the application running on the main processor. More particularly, the application at  410  sees only the application interface  420 , and the fact that the subordinate processors  130  handle the I/O operation is transparent to the application running on the main core processor  110 . A typical disk storage read operation produces many interrupts before it is completed.  
         [0049]     However, by distributing into the subordinate processors the operating system functionality associated with disk storage accesses, the many interrupts are seen only by the subordinate processors, and are invisible to the application running on the main core processor. As far as the application running on the main core processor is concerned, the application simply provides a disk storage read request to the applications interface  420 , and this request results in a single interrupt, namely, an interrupt from the operating system indicating that the desired file is ready in RDRAM  310 .  
         [0050]     In an exemplary embodiment, operating system functions that are relatively slow, relatively frequently accessed, or both, can be distributed among the subordinate processors  130 , thereby off-loading from the main core processor  110  a relatively large processing burden, which in turn improves the data processing throughput that the main core processor can achieve while executing the application according to the sequential programming model.  
         [0051]      FIG. 5  illustrates an expanded data processing architecture according to an exemplary embodiment of the invention. In the expanded data processing architecture  500  of  FIG. 5 , a plurality of instances of the data processing architecture  100  described above relative to  FIGS. 1-3 , designated respectively as  100   a,    100   b,  . . .  100   c,  are interconnected by a bus structure  510 . In particular, the bus structure  510  interconnects the main core processors  110  of the respective data processing architectures  100   a,    100   b,  . . .  100   c.  The arrangement of  FIG. 5  thus results in an even higher performance architecture.  
         [0052]     Although the present invention has been described with an exemplary embodiment, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.