Abstract:
A power saving method applied to a central processing unit under a non-snooping sleeping state with a bus master request from a peripheral device is presented. In accordance with the present invention, first prohibit the central processing unit from fetching instruction. Then drive the central processing unit entering a snooping sleeping state and enabling the arbiter for transferring the bus master request to the central processing unit. After the central processing unit completes the bus master request, the arbiter is disabled and the central processing unit is driven to leave the snooping sleeping state and return back to the non-snooping sleeping state. Therefore, the power consumed by the central processing unit is reduced so as to save power.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a power saving method applied to a central processing unit and a system therefore, especially to a processing method for a central processing unit that is in a non-snooping sleeping state while receiving a bus master request from a peripheral device. 
   BACKGROUND OF THE INVENTION 
   Except petroleum, electric power is the most important power resource in daily life. Almost every household appliance requires electricity to operate, such as lighting, TV, air conditioner, etc. But before any breakthrough on exploring new power source that is more efficient and economic is made, the best measure is to reduce power consumption. For example, power consumption of desktops or notebooks is one of major concerns of R&amp;D staffs and users, especially for notebooks. Besides improvement of battery capacity, another way is to develop more power-saving notebooks. 
   To improve power efficiency, computer systems such as desktops or notebooks are provided with power management systems. The most commonly seen is ACPI (Advanced Configuration and Power Interface). The power states defined by the ACPI include: Global system state, Sleeping state, Device power state and Processor power state. Global system state defines the overall power state of the computer system. Sleeping state defines various power saving states when computer system has few loading. Device power state defines various power states of the peripheral devices in the computer system. Processor power state defines power levels of the CPU (central processing unit). There are four states defined in Processor power state: C 0 , C 1 , C 2  and C 3 . According to the working status of the CPU, the operating system drives the CPU to enter into the proper power state. 
   C 0  state is the normal processing state. In C 0  state, the CPU executes instructions in normal. C 1 , C 2 , and C 3  states are different levels of power-saving states, known as sleeping states. It takes the shortest time for the CPU to wake up from a halt state (C 1 ) and resume full performance to C 0  state. Different to C 1  state, C 2  state is more power saving and the CPU only executes part of functions in this state, such as snooping function. In C 2  state, the CPU can still snoop bus master requests and further process these requests so that the peripheral devices of the computer system can access data in the memory. In C 3  state, the CPU is almost turned off without any loading. Therefore it&#39;s the most power saving state. 
   Refer to  FIG. 1 , which illustrates a state transfer diagram of prior-art ACPI. When the CPU is in C 1 , C 2  or C 3  state and the system chip receives an interrupt from the peripheral device, the CPU returns back to C 0  state to process the interrupt. Moreover, when the CPU is in C 3  state, once the peripheral device issues a bus master request, the CPU also returns back to C 0  state to process the bus master request. That is because C 3  state is a sleeping state without snooping function. The CPU needs to wake up from C 3  state and return back to C 0  state for snooping events so as to process the bus master request. Otherwise, the peripheral devices can not access data inside the memory. 
   After the bus master request is completed, the CPU needs to stay in C 0  state until the conditions for entering C 3  state are satisfied. Then the operating system drives the CPU returning to C 3  state. However, while in C 2  state, the CPU is able to snoop the bus master request. Thus the conventional way of returning back to C 0  state for processing the bus master request makes the CPU consume more power. 
   SUMMARY OF THE INVENTION 
   Therefore the present invention provides a power saving method for a CPU. When the CPU is in a non-snooping sleeping state and the peripheral device issues a bus master request, the CPU is driven to wake up from the non-snooping sleeping state and enter a snooping sleeping state so that the CPU may snoop the bus master request and return to the non-snooping sleeping state after the request is completed. In such way power consumption of the CPU can be saved. 
   The present invention is applied to the condition that the CPU is under a non-snooping sleeping C 3  state and a peripheral device issues a bus master request. First, assert a stop signal to prohibit the CPU from fetching instructions. Then, assert a first control signal to drive the CPU waking up from C 3  state. Next a second control signal is asserted to drive the CPU entering to C 2  state that allows snooping and an arbiter is enabled for transferring the bus master request to the CPU. After the bus master request is completed, the arbiter is disabled and a third control signal is asserted to drive the CPU waking up from C 2  state. Then consequently assert a fourth control signal to drive the CPU back to C 3  state so as to save power. 
   After returning back to C 3  state, if the peripheral device issues an interrupt to the CPU, the CPU wakes up from C 3  state and enters to C 0  state to execute instructions by receiving a first control signal. And a resume signal is asserted to the CPU while the arbiter is enabled for transferring the interrupt to the CPU for processing. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The structure and the technical means adopted by the present invention to achieve the above and other objects can be best understood by referring to the following detailed description of the preferred embodiments and the accompanying drawings, wherein 
       FIG. 1  is a schematic state transfer diagram which depicts processor states of the Advanced Configuration and Power Interface of a prior art; 
       FIG. 2  is a block diagram of an embodiment in accordance with the present invention; 
       FIG. 3  is a flow chart of an embodiment in accordance with the present invention; and 
       FIG. 4  is a flow chart of another embodiment in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   The present invention relates to a power saving method for a CPU that is in C 3  state while receiving a bus master request. The present invention drives the CPU entering to C 2  state to snoop and process the bus master request. 
   Refer to  FIG. 2 , which illustrate a block diagram of an embodiment of the present invention. As shown in  FIG. 2 , the present invention includes a system chip  20  coupled to a CPU  10 . The system chip  20  includes an arbiter  23  and a power management unit  25 , and is further coupled to a system memory  30  and a peripheral device  35 . When the peripheral device  35  requests to read data from the system memory  30 , the peripheral device  35  will issue a bus master request to the system chip  20 . Then the system chip  20  will transfer the bus master request to the CPU  10  through the arbiter  23  for snooping and processing the request. The power management unit  25  of the system chip  20  is provided to issue control commands to the CPU  10  in order to drive the CPU  10  into different power states according to the working condition. 
   When the operating system detects that the CPU  10  has low work loading and the conditions for entering C 3  state is met, the operating system then drives the CPU  10  entering to C 3  state. In order to avoid the system chip  20  transferring the bus master request or the interrupt event to the CPU  10  through the arbiter  23  when the CPU  10  is in C 3  state, the operating system will drive the system chip  20  to disable the arbiter  23  until the CPU  10  leaves C 3  state. To control the arbiter  25 , the operating system will issue a control command to the system chip  10 . Then the system chip  20  transfers an I/O response to the CPU  10  and enables the arbiter  23  according to the control command. The CPU  10  will not fetch and execute the instruction of the operating system until receiving the I/O response. 
   As mentioned above, the CPU  10  has to wait a period of time till the conditions of entering C 3  state are met, then the CPU  10  is able to enter C 3  state. In the case that the CPU  10  completes the bus master request or the interrupt event and has nothing to do later, the CPU  10  must waste redundant time and power in C 0  state before returning to C 3  state. However, the CPU  10  is also able to snoop the bus master request in C 2  state. If the CPU  10  may jump from C 3  state to C 2  state to process the bus master request and return to C 3  state after the request is completed, power can be saved comparing to processing in C 0  state and waiting for returning to C 3  state. 
   Due to that the power management unit  25  of the system chip  20  allows the CPU  10  to transfer between C 0 /C 2  and C 0 /C 3  only, it is not possible to transfer between C 2 /C 3  directly. In order to make the CPU  10  transfer from C 3  to C 2  state, the CPU  10  must transit to C 0  state in transient. That is, the CPU  10  has to transit to C 0  state from C 3  state, then transit to C 2  state from C 0  state. In the same way, the CPU  10  returns to C 3  state from C 2  state transiting through C 0  state. Notice that the CPU  10  does not have to execute any instruction in C 0  state, which is only a transient state between C 2  and C 3  states. Therefore, the system chip  20  must prohibit the CPU  10  from fetching instruction and enable or disable the arbiter  23  correspondingly. 
   Provided with the facts, the system chip  20  in the present invention asserts a stop signal to the CPU  10  to prohibit the CPU  10  from fetching instruction before the CPU  10  transiting to C 0  state. Then the power management unit  25  of the system chip  20  drives the CPU  10  to enter to C 2  state for snooping the bus master request. After the request is completed, the power management unit  25  drives the CPU  10  to leave C 2  state and return to C 3  state transiting through C 0  state. When the system chip  20  receives an interrupt event, the system chip  20  asserts a resume signal and the CPU enters to C 0  state to fetch and execute instructions of the operating system. 
   A flowchart of an embodiment in the present invention is shown in  FIG. 3 . In step SO, the CPU  10  is in C 3  state and the arbiter  25  is disabled. Next refer to step S 1 , a peripheral device  35  issues the bus master request to the system chip  20 . In step S 2 , the system chip  20  asserts a stop signal to the CPU  10  to prohibit CPU  10  from fetching instructions. The system chip  20  and the CPU  10  of the present invention are disposed with corresponding pins. The system chip  20  asserts a high-level signal through its pin to the corresponding pin on the CPU  10  to represent the stop signal that prohibits the CPU  10  from fetching instructions. If a low-level signal is asserted from the system chip  20  to the CPU  10 , such case is a resume signal that allows the CPU  10  to fetch instructions again. 
   Then in step S 3 , a power management unit  25  of the system chip  20  asserts a first control signal to drive the CPU  10  leaving C 3  state and entering to C 0  state. Due to the stop signal asserted by the system chip  20  in step S 2 , although the CPU  10  is in C 0  state, instructions of the operating system will not be fetched or executed. Thus the system chip  20  is unable to enable the arbiter  23  and transfer the bus master request to the CPU  10 . 
   Next the power management unit  25  goes to step S 4 , asserting a second control signal to drive the CPU  10  leaving C 0  state and entering to C 2  state, which is provided with snooping function. After the CPU  10  entering to C 2  state, the system chip  20  automatically enables the arbiter  23  to transfer the bus master request to the CPU  10  for snooping. 
   When the system chip  20  detects that the CPU  10  has completed the bus master request, the system chip  20  will disable the arbiter  23  in step  5 . Next, as shown in step S 6 , the power management unit  25  of the system chip  20  asserts a third control signal to drive the CPU  10  leaving C 2  state and entering to C 0  state. Until now the CPU  10  will not fetch any instructions yet. 
   Refer to step S 7 , the system chip  20  asserts a fourth control signal to drive the CPU  10  leaving C 0  state and returning to C 3  state. At last, the system chip  20  goes to step S 8 , asserting a resume signal to the CPU  10  to recover the status of the CPU  10  as in step S 0 . Later, if the peripheral device  35  issues a bus master request again, repeat step S 2  to step S 8 . If the event that the system chip  20  receives is an interrupt, the CPU  10  needs to wake up from C 3  state and returns to normal processing state C 0  state to process the interrupt. Therefore the system chip  20  asserts a first control signal to drive the CPU  10  waking up from C 3  state and entering to C 0  state, and the arbiter  23  is enabled for transferring the interrupt to the CPU  10 . Then the CPU  10  may process the interrupt event. In this case no stop signal is asserted, therefore the CPU  10  will not be prohibited from fetching instructions of the operating system. 
   Refer to  FIG. 4  now. Different to the previous embodiment in  FIG. 3 , which goes to step S 8  in which the resume signal is asserted after the CPU  10  returns to C 3  state in step S 7 , the embodiment in  FIG. 4  will go to step S 9  to determine whether an interrupt event is presented after step S 7 . If the peripheral device  35  issues a bus master request again, repeat step S 3  to step S 7  to allow the CPU  10  snooping the request in C 2  state. If the peripheral device  35  issues an interrupt, the CPU  10  has to wake up from C 3  state and enter to C 0  state. The system chip  20  goes to step S 10 , asserting the first control signal to drive the CPU  10  leaving C 3  state and entering to C 0  state. Moreover, the system chip  20  then asserts the resume signal to the CPU  10  so as to allow the CPU  10  fetching instructions. Thus the CPU  10  will fetch and execute instructions of the operating system, and the system chip  20  will enable the arbiter  23  to transfer the interrupt to the CPU  10  for processing. 
   In summary, when the CPU is in the non-snooping C 3  state and the peripheral device issues the bus master request, a power saving method of the CPU in accordance with the present invention prohibits the CPU from fetching instructions, then drives the CPU waking up from C 3  state and entering to C 2  state that allows snooping function by transiting through C 0  state in between. Thus the CPU is able to snoop the bus master request. After the bus master request is completed, the CPU then returns from C 2  state to C 3  state by transiting through C 0  state. By driving the CPU leaving C 3  state to snoop the bus master request in C 2  state and then returning to the C 3  state, power can be saved in the present invention. 
   Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the present invention in its broader aspects is not limited to the specific details, and representative devices shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.