Abstract:
Micro-electromechanical systems (MEMS) pre-fabrication products and methods for forming MEMS devices using silicon-on-metal (SOM) wafers. An embodiment of a method may include the steps of bonding a patterned SOM wafer to a cover wafer, thinning the handle layer of the SOM wafer, selectively removing the exposed metal layer, and either continuing with final metallization or cover bonding to the back of the active layer.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    A method of producing microelectromechanical systems (MEMS) sensors and actuators which are built up by stacking single-crystalline layers of thicknesses less than the thickness of a standard silicon layer typically involves patterning, bonding, and thinning. The single-crystalline layer is supported by a sacrificial support wafer. The single-crystalline layer is patterned on the sacrificial wafer. The single-crystalline layer is then bonded to the device substrate wafer which is typically patterned with recesses, holes, and/or electrical traces. The sacrificial wafer is removed exposing the patterned single-crystalline patterned layer. More layers can be bonded and thinned using the same process as well as adding a cap wafer. This process may require an etch stop between the single-crystalline layer and the sacrificial wafer. The primary purpose of the etch stop may be to ease sacrificial wafer removal after bonding by providing a protection to the single-crystalline layer. The etch stop may also be used to ease patterning of the single-crystalline layer. Three methods used today are heavily doped epitaxial silicon layers, silicon-on-insulator (SOI), and thin wafer processing. Each of these processes have advantages and disadvantages in processing options (bonding and thinning), device geometry design rules, material constraints, and thermal limitations. 
         [0002]    U.S. Pat. No. 6,991,995 entitled “METHOD OF PRODUCING A SEMICONDUCTOR STRUCTURE HAVING AT LEAST ONE SUPPORT SUBSTRATE AND AN ULTRATHIN LAYER” issued to Aulnette et al. on Jan. 31, 2006, and herein incorporated by reference, discloses one method of producing ultrathin layers. 
         [0003]    New systems and methods are needed to address some of the above limitations, including the cost of using new sacrificial wafers each time the process is performed. 
       SUMMARY OF THE INVENTION 
       [0004]    The present invention includes a device and method for producing Micro-Electromechanical Systems (MEMS) devices using silicon on metal (SOM) wafers. An embodiment of a method includes bonding a patterned SOM wafer to a cover wafer, thinning the handle (or sacrificial) layer of the SOM wafer, selectively removing the exposed metal layer, and either continuing with final metallization or cover bonding to the back of the active layer. 
         [0005]    Further embodiments include creating an SOM wafer and patterning an SOM wafer. Patterning includes using the metal layer as a non-charging etch stop during plasma etching. 
         [0006]    In accordance with other aspects of the invention, thinning the handle layer includes using the metal layer as an etch stop. 
         [0007]    In accordance with still further aspects of the invention, the method includes the step of high temperature fusion bonding after the step of selectively removing the exposed metal layer. 
         [0008]    In accordance with other aspects of the invention, a first metallic layer is precipitated onto the first surface of a first substrate wafer with substantially planar first and second opposed surfaces. A handle layer is bonded to the first metallic layer to form a bonding layer in opposed relation to the first surface. Mechanical structures (e.g. beams and trenches) are fabricated into the first substrate wafer. A second substrate layer is bonded to the second substrate surface to form a substrate assembly. The bonding layer is dissolved and the handle layer is removed from the substrate assembly. 
         [0009]    Other aspects of the invention include using a perforated sacrificial wafer, which may be reused; using all metal or all polymer interlayers; and, bonding additional mechanism layers to the structure. 
         [0010]    As will be readily appreciated from the foregoing summary, the invention provides a system and method for using SOM wafers in the fabrication of MEMS devices having single-crystalline layers. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The preferred and alternative embodiments of the present invention are described in detail below with reference to the following drawings: 
           [0012]      FIGS. 1-5  are side views of various intermediate structures produced by a method according to the present invention; 
           [0013]      FIGS. 6A and 6B  are side and bottom views of an alternate embodiment of the structure of  FIG. 1 ; 
           [0014]      FIG. 7  is a side view of another alternate embodiment of the structure of  FIG. 1 ; 
           [0015]      FIG. 8  is a side view of the structure of  FIG. 5  that includes components applied according to an alternate embodiment of the present invention; 
           [0016]      FIG. 9  is a block diagram of a method according to the present invention; and 
           [0017]      FIG. 10  is a block diagram of an alternate method according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0018]      FIG. 1  shows a side cross-sectional view of a structure  18  that includes a mechanism wafer  20 , a metal layer  22 , a metal or polymer layer  24 , and a sacrificial (or handle) wafer  26 . The mechanism wafer  20  and sacrificial wafer  26  may be standard single side polished silicon wafers. The metal layer  22  is produced by metallizing a bottom face  28  of the mechanism wafer  20 , and the metal or polymer layer  24  is produced by metallizing or polymerizing a top face  30  of the sacrificial wafer  26 . The faces  28 ,  30  with attached layers  22 ,  24  are bonded to each other using various bonding methods; bonding methods include low temperature thermal compression bonding for a metal to metal bond. The mechanism wafer  20  is thinned to a desired thickness using, for example, lapping and polishing. 
         [0019]      FIG. 2  shows the structure of  FIG. 1  after etching the mechanism wafer  20  to form various components of a MEMS device. The mechanism wafer  20  is masked and etched to the metal layer  22  (which may function as an etch stop), after which the mask is removed. Etching may include, for example, wet chemical etching selective to metal such as etching in tetramethyl-ammonium-hydroxide (TMAH) solution or in hydrazine solution. Etching may further include, for example, plasma etching using flourine or chlorine radicals. Plasma etching may include Deep Reactive Ion Etching (DRIE) to fabricate high aspect ratio structures in silicon. In the latter, the metal layer does not only function as an etch stop layer but also prevents lateral etching of the structure known as “footing” or “notching”. 
         [0020]      FIG. 3  shows the structure of  FIG. 2  after bonding the mechanism wafer  20  to a patterned silicon device substrate wafer  32 . Bonding methods include low temperature, temporary silicon-to-silicon fusion bonding the mechanism wafer  20  to the device substrate wafer  32 . 
         [0021]      FIG. 4  shows the structure of  FIG. 3  after selective etching of the sacrificial wafer  26  to the metal or polymer layer  24 . Etching may be accomplished by using wet chemical solutions such as TMAH or hydrazine, or by using plasma etching with flourine or chlorine radicals DRIE. The metal or polymer layer  24  acts as an etch stop. Etching may include a normal silicon etch technique which stops on metal (wet or dry), or alternatively underetching the entire wafer  26  through perforations with a selective metal wet etch. 
         [0022]      FIG. 5  shows the structure of  FIG. 4  after removal of the metal and polymer layers  22 ,  24 . Removal may be accomplished by metal etching in acidic solutions and by polymer etching using a solvent or in a plasma with oxygen radicals. 
         [0023]      FIGS. 6A and 6B  show side cross-sectional and top views, respectively, of an embodiment of a perforated sacrificial wafer  34  of the present invention. This embodiment may be substituted for the structure of  FIG. 1 . The perforated wafer  34  may be perforated by etching holes and trenches using DRIE with flourine radicals. The perforated wafer  34  allows removal of the metal or polymer layer  24  without destruction of the wafer  34 . The layer  24  is removed by introducing etchant into the perforations of the wafer  34 . The etchant is chosen such that it will not etch the wafer  34 , but will etch the layer  24 . The wafer  34  is released upon removal of the layer  24 , and may be reused. 
         [0024]      FIG. 7  shows an alternate embodiment of the structure of  FIG. 1 . A layer  36  is either metal or polymer, and replaces the metal and metal or polymer layers  22 ,  24  of  FIG. 1 . 
         [0025]      FIG. 8  shows the structure of  FIG. 5  after an optional additional layer  38  has been added to the structure  18 . The layer  38  may be a capping wafer or an additional mechanism layer, or both, and may include silicon. Additional layers (not shown) may be attached. 
         [0026]      FIG. 9  is a block diagram of a method  40  according to the present invention. At a block  42 , a silicon-on-metal (SOM) wafer with an active layer, a sacrificial layer, a metal layer, and a metal or polymer layer is formed. At a block  44 , the active layer is patterned and etched to form MEMS components, and the internal metal layer may be used as an etch stop. At a block  46 , the patterned SOM wafer is bonded to a cover wafer. At a block  48 , the sacrificial layer of the SOM wafer is removed. Finally, at a block  50 , the metal layer and metal or polymer layer are selectively removed. 
         [0027]      FIG. 10  is a block diagram of an alternate method  52  according to the present invention. At a block  54 , a first substrate wafer is provided. At a block  56 , a first metallic layer is precipitated on a first surface of the substrate wafer. At a block  58 , a sacrificial layer is bonded to the first metallic layer. At a block  60 , structures such as beams and trenches are formed in the first substrate wafer. At a block  62 , a second substrate wafer (which may be patterned) is bonded to a second surface of the first substrate wafer. At a block  64 , the metallic layer is dissolved which releases the sacrificial layer. 
         [0028]    While the preferred embodiment of the invention has been illustrated and described, as noted above, many changes can be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is not limited by the disclosure of the preferred embodiment. Instead, the invention should be determined entirely by reference to the claims that follow.