Abstract:
A method for precise thinning to form a recess to a precise depth in a crystalline silicon layer, which can be used to form various devices, such as MOSFET devices, includes the following steps. Form a patterning mask with a window therethrough over the top surface of the silicon layer. Form an amorphized region in the top surface of the silicon layer below the window. Selectively etch away the amorphized region of the silicon layer to form a recess in the surface of the silicon layer, and remove the patterning mask In the case of an MOSFET device form a hard mask below the patterning mask with the window extending therethrough. Then create sidewall spacers in the window through the hard mask and form a gate electrode stack in the window. Then remove the hard mask and form the source/drain extensions, halos and regions plus silicide and complete the MOSFET device.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    This invention relates to methods of forming thinner silicon structures with precisely defined thicknesses in a thin silicon substrate, and more particularly to subtractive methods of thinning selected portions of a silicon structure.  
           [0002]    This invention provides a method for forming a structure with a precision recessed gate structure for an Ultra Thin (UT) silicon SOI device comprising a thin layer of doped silicon formed on the surface of a Buried OXide (BOX) layer. The method can also be used for precision thinning of selected regions of the top silicon layer on a Silicon-On-Insulator (SOI) wafer. This can be used to provide an optimal silicon thickness for each type of electronic device which is to be formed on the same wafer. For example, MOSFETS require thinner silicon than resistors or capacitors or diodes in order to achieve the best electrical characteristics.  
           [0003]    Scaling of SOI devices can be limited by the ability to thin the silicon. The silicon thickness must be thinned to achieve device performance targets, but simultaneously the silicide used to contact the source/drain region must be prevented from consuming the entire thickness of the silicon and as a result contacting the BOX layer. This is a significant problem because source/drain contact resistance increases very rapid as the silicide layer approaches the BOX layer.  
           [0004]    [0004]FIGS. 1A and 1B illustrates a possible approach to forming a raised source/drain structure that employs the option of forming raised source regions and drain regions (above the SOI structure) juxtaposed with the gate electrode stack of the MOSFET device by deposition of additional silicon adjacent to the gate electrode stack after formation thereof.  
           [0005]    In FIG. 1A, a MOSFET device  10  is shown in an intermediate stage of manufacture. The substrate  12  comprises a BOX layer upon which a thin doped silicon layer  14  has been formed to serve as the doped region in which the source/drain and channel of an FET device are to be formed. Above the center of the silicon layer  14 , a gate electrode stack comprising a gate oxide layer GOX, a polysilicon gate G and a silicide layer SCD have been patterned followed by formation of sidewall spacers on the sidewalls of the gate electrode stack ST.  
           [0006]    [0006]FIG. 1B shows the device  10  after the exposed surfaces of the thin silicon layer aside from the spacers SP has been coated with a thin epitaxial silicon layer  16  to form what will later be employed as raised source/drain regions by additional processing steps as will be well understood by those skilled in the art.  
           [0007]    The method of FIGS. 1A and 1B has significant issues with the selective epitaxy necessary to form the raised source drain. In the selective epitaxy process, silicon is deposited selectively only on exposed silicon surfaces and not on dielectric surfaces such as silicon dioxide isolation regions and silicon nitride spacers. This process is difficult to control because it relies on the balance between silicon deposition and etching in a chemical vapor deposition reactor. Even when acceptable deposition rates on silicon are achieved while simultaneously getting no significant deposition on the dielectric surfaces, the shapes of corners and edges of the silicon surfaces can be changed because of variations in the silicon growth/etch rates with crystallographic orientation. This leads to faceting of these edges resulting in unacceptable device structures. The process is also very sensitive to surface contamination and prior processing conditions during such commonly used process steps as ion implantation, reactive ion etching and wet chemical cleans and etches. The deposition rates are also affected by dopant species and concentration in the silicon surface layers. This can lead to different deposition thicknesses on nFETs and pFETs which is generally undesirable.  
           [0008]    Another option is recessing the gate. Such an approach is described by Morimoto et al. U.S. Pat. No. 6,492,696 entitled “Semiconductor Device And Process Of Manufacturing The Same”. Morimoto et al. describes use of a LOCOS process to form a recess of a controlled thickness. A LOCOS film is formed on the surface of exposed areas on the surface of a silicon layer of an SOI substrate. Then the LOCOS film is etched away, leaving a thinner channel region (a recessed channel region) where the LOCOS film has been etched away. Next, a metal film is formed on the entire surface of the substrate to form a silicide film. Since this method utilizes the SOI substrate by adjusting the thickness of the surface silicon layer, the depth of a source/drain region can be controlled, so a source/drain region of relatively large depth can be formed by a common step for forming the source/drain region. This LOCOS recessing process is problematic due to the control necessary in defining the silicon thickness below the gate electrode stack.  
         SUMMARY OF THE INVENTION  
         [0009]    An object of this invention is to provide a method of forming a precision recessed gate structure using selective Reactive Ion Etching (RIE) of regions in the silicon.  
           [0010]    In accordance with this invention, a method is provided for forming a precision recessed structure such as a gate structure by the process of forming an amorphized region in a silicon layer by ion implantation into the silicon layer. The following step is selective Reactive Ion Etching (RIE) of the amorphized region in the silicon to form the recess therein. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    The foregoing and other aspects and advantages of this invention are explained and described below with reference to the accompanying drawings, in which:  
         [0012]    [0012]FIGS. 1A and 1B illustrates a possible approach to forming a raised source/drain structure, which is inadequate to produce the required results.  
         [0013]    [0013]FIGS. 2A-2M illustrate the key steps of the process flow of one embodiment of this invention, which is employed to form a recessed gate MOSFET.  
         [0014]    [0014]FIGS. 3A-3C illustrate the key steps of the process flow of another embodiment of this invention, which is employed to form a recessed surface in a silicon layer. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0015]    The process flow of one embodiment of this invention, which is employed to form a recessed gate MOSFET is described below with reference to FIGS. 2A-2M. In accordance with the method of FIGS. 2A-2M, the structure of an MOSFET device  20  is defined in part by production of a precisely controlled gate recess  38  shown in FIG. 2C formed by the selective reactive ion etching of amorphized silicon formed by ion implantation.  
         [0016]    Form Masking Layers Over Silicon-on-Insulator (SOI) Layer  
         [0017]    Starting in FIG. 2A, the MOSFET device  10  is shown in an early stage of manufacture. The substrate  22  which has a planar upper surface comprises a BOX layer formed on a wafer (not shown for convenience of illustration). Above the BOX layer  22 , a conformal, planar, thin, p-doped crystalline silicon layer  24  has been formed to serve as the doped region in which the source/drain and channel of an FET device are to be formed. As will be well understood by those skilled in the art, the silicon layer  24  is lightly p-type doped before the start of processing. After the BOX layer  22  is formed and after the isolation processing (which is not discussed herein but which will be well understood by those skilled in the art), the nFET regions get a p-well implant and the pFET regions get a n-well implant to form p- and n-doped regions respectively, as will also be well understood by those skilled in the art.  
         [0018]    Above the thin doped, crystalline silicon layer  24 , a conformal, planar, hard mask layer  28  which can be silicon oxide has been formed and coated with a silicon nitride layer  30  which is a thin layer that is also sacrificial. A photoresist mask  32  with a gate opening  32  therethrough has been formed over the silicon nitride (nitride) cap layer  30  of silicon nitride (nitride) above the center of the device  20 . The mask  32  was formed by applying photoresist and exposing it using conventional pholithographic techniques. The photoresist mask  32  has been employed to etch a gate window  34  through the nitride layer  30  and the hard mask layer  28  down to the surface of the thin silicon layer  24 .  
         [0019]    Amorphize Exposed Area of Silicon-on-Insulator Layer  
         [0020]    In FIG. 2B, the device  20  of FIG. 2A is shown after ion implanting ions  361  through the window  34  into the surface of the thin crystalline silicon layer  24  amorphizing a specific thickness of the exposed portion of the thin crystalline silicon layer  24 . The thickness of the amorphized silicon layer  36  can be precisely tailored by changing the ion energy, dose or ion species of the ions  361  during performance of the ion implantation process. The preferred ions  361  are silicon or germanium. The implant is masked using a material for the hard mask layer  28 , such as silicon dioxide, silicon nitride or silicon oxynitride or a combination of these films which has been patterned using conventional lithography. If the structure to be built is a recessed channel MOSFET, the hard mask layer  28  and layer  30  will also act as the mandrel on which temporary or disposable spacers are formed. The thickness of the amorphous layer is determined by the energy of the implantation procedure. For example, TABLE I shows the amorphous layer thickness for several energies of germanium ions implanted to a dose of 5.0×10 14  ions/cm 2 .  
                           TABLE I                                   Energy (Kev)   Thickness (nm)                           10   19.0           15   24.0           20   28.5           25   32.0           30   38.0           35   42.5           40   49.3                      
 
         [0021]    Strip Photoresist Mask  
         [0022]    In FIG. 2C, the device  20  of FIG. 2B is shown after the preliminary steps of stripping away the photoresist mask  32   
         [0023]    Form Recess in Silicon-on-Insulator Layer with Selective Etch  
         [0024]    Referring again to FIG. 2C, the next step of a selective reactive ion etch (RIE) of the amorphized silicon layer  36  through the window  34  that has formed the recess  38 . The conditions used for this etch must be such that the differential etch rate of the amorphous silicon is approximately three (3) times greater than that of crystalline silicon. The differential etch rate provides a self-limiting etch which when combined with an interferometric endpoint system and the low etch rate allows the etch to precisely stop at the boundary between the implant damaged layer  36  and the crystalline substrate  24  therebelow and juxtaposed therewith laterally. The result is that window  34  has been expanded into a deeper window  34 ′ that reaches down to the newly exposed surface of the thin doped silicon p-layer  24  at the bottom of the recess  38 . A selective, low etch rate silicon etching process that can be used is based on using a mixture of hydrogen bromide (HBr) vapor with oxygen (O 2 ) gas in a diluent gas done in a decoupled plasma reactor. The operation regime employs a pressure range of 20-60 mT (milli-Torr); hydrogen bromide (HBr) vapor HBr flow in the range of 150-300 sccm and oxygen (O 2 ) flow 4-10 sccm. Helium is used as the diluent gas. The key to success of this etching process is the use of low bias power. The interferometric endpoint system is used to stop the etching process, precisely, just after the desired silicon thickness has been etched.  
         [0025]    Temporary Sidewall Spacer Formation  
         [0026]    [0026]FIG. 2D shows the device  20  of FIG. 2C after temporary (disposable) sidewall spacers  40  have been formed in the window  34 ′ reaching from the bottom of the recess  38  up alongside the walls of the mask layer  28  and the cap  30 . Silicon nitride, silicon dioxide, silicon oxynitrides or combinations of these films can be used to form the spacers  40  by CVD, PECVD or other deposition techniques.  
         [0027]    The following step is to etch back the spacers  40  partially by directional Reactive Ion Etching (RIE) to produce the configuration shown in FIG. 2D leaving the bottom of the recess  38  open down to the surface of the silicon recess  38  in the center of the widow  34 ′. The width of spacers  40  after etching should be from 10 nm to 75 nm.  
         [0028]    Gate Oxide Formation  
         [0029]    [0029]FIG. 2E shows the device  20  of FIG. 2D after formation of a gate oxide layer  42  on the surface of the silicon recess  38  in the center of the widow  34 ′. The gate oxide layer  42  can be a thermally grown silicon oxide or an oxynitride, with or without a pre-growth or post-growth nitridization treatment such as nitrogen ion implantation or plasma treatment. Post nitrogen treatment or post growth annealing can also be done. An alternative gate dielectric may be deposited such as a high permittivity (high-K) insulator by various techniques such as Atomic Layer Deposition (ALD) or CVD. Various pre-deposition and post-deposition treatments as described above for thermally grown silicon oxides can be applied to the high-K films also. Examples of high-K materials suitable for this application are HfO 2 , ZrO 2 , Ta 2 O 5 , SrTiO 3  and LaAlO 3 .  
         [0030]    Formation of Gate Electrode  
         [0031]    [0031]FIG. 2F shows the device  20  of FIG. 2E after formation of the gate electrode  44  by deposition of polysilicon into the window  34 ′ covering the gate oxide layer  42  and filling the space defined by the sidewall spacers  40 .  
         [0032]    Planarization of Gate Polysilicon  
         [0033]    [0033]FIG. 2F also shows the device after planarization of the top of the polysilicon, gate electrode  44  down to the level of the cap layer  30  by the well known process of Chemical-Mechanical Polishing (CMP).  
         [0034]    Removal of the Mandrel Material  
         [0035]    [0035]FIG. 2G shows the device  20  of FIG. 2F after removal of the mandrel material comprising the cap layer  30  and the hard mask  28  leaving the gate stack of the gate electrode  44  and the gate oxide  42  with the sidewall spacers  40  alone in the center of the doped, thin silicon layer  24  by a conventional selective etching process.  
         [0036]    Removal of Spacers  
         [0037]    [0037]FIG. 2H shows the device  20  of FIG. 2G after removal of the sidewall spacers  40  exposing the sidewalls of the gate stack (i.e. the sidewalls of the gate electrode  44  and the sidewalls of the gate oxide  42 ) in the center of the recess  38  with a gap between the outer walls of the recess  38  and the lateral walls of the gate oxide layer  42  and the lower outer edges of the gate electrode  44 .  
         [0038]    Gate Electrode Reoxidation  
         [0039]    [0039]FIG. 21 shows the device  20  of FIG. 2H after growth of a thin thermal oxide layer  46  on the exposed top and sidewall surfaces of the gate electrode  44 , which preferably has a thickness of from about 1 nm to about 5 nm.  
         [0040]    Form nFET Extension/Halo Mask  
         [0041]    Form a photolithograpic mask to cover all areas except where the nFET devices are to be formed.  
         [0042]    Implant nFET Extensions  
         [0043]    [0043]FIG. 2J shows the device  20  of FIG. 21 after an nFET extension implant with dopant  481  to form N-dopant regions  48  in the silicon layer  24  aside from that gate oxide layer  42  including the depressed regions of the recess  38 .  
                           TABLE II                                       nFET   Extension Implant               Low energy           Dopant   Arsenic           Energy   0.5 to 15 Kev           Dose   2E14/cm 2  to 2E15/cm 2             Angle   0 to 10 degrees C.                      
 
         [0044]    Perform nFET Halo Implant  
         [0045]    Then an nFET halo implant is performed using either boron or BF 2  in accordance with the parameters of either TABLE IIIA or TABLE IIIB to form p-doped halo regions (not shown) as will be well understood by those skilled in the art.  
                           TABLE IIIA                                       nFET   Halo Implant           Dopant   Boron           Energy   5 to 50 Kev           Dose   2E13/cm 2  to 2E14/cm 2             Angle   0 to 45 degrees                      
 
         [0046]    [0046]                           TABLE IIIB                                       nFET   Halo Implant           Dopant   BF 2             Energy   10 to 70 Kev;           Dose   2E13/cm 2  to 2E14/cm 2             Angle   0 to 45 degrees                        
         [0047]    Strip nFET Photoresist Mask.  
         [0048]    Then the nFET extension/halo mask is stripped away to prepare for the pFET implant process  
         [0049]    Form pFET Extension/Halo Mask  
         [0050]    Form a photolithograpic mask to cover all areas except where the pFET devices are to be formed. While these areas are not shown, since the features of the invention have been illustrated with respect to the nFET devices, the process is performed analogously as will be well understood by those skilled in the art.  
         [0051]    Implant pFET Extensions  
         [0052]    Perform a pFET extension implant with boron or BF 2  dopant in accordance with the parameters of either TABLE IVA or TABLE IVB below to form p-dopant regions (not shown) in the silicon layer  24  aside from the pFET gate oxide layer (not shown) of the pFET devices (not shown) including the depressed regions of the pFET recesses (not shown).  
                           TABLE IVA                                       pFET   Extension Implant           Dopant   Boron           Energy   0.2 to 10 Kev           Dose   2E14/cm 2  to 2E15/cm 2             Angle   0 to 10 degrees                      
 
         [0053]    [0053]                           TABLE IVB                                       pFET   Extension Implant           Dopant   BF 2             Energy   1 to 30 Kev           Dose   2E14/cm 2  to 2E15/cm 2             Angle   0 to 10 degrees                        
         [0054]    Perform pFET Halo Implant  
         [0055]    Then an pFET halo implant is performed in accordance with the parameters of either TABLE V to form p-doped halo regions (not shown) as will be well understood by those skilled in the art.  
                           TABLE V                                       pFET   Halo Implant           Dopant   Arsenic           Energy   20 to 100 Kev           Dose   2E13/cm 2  to 2E15/cm 2             Angle   0 to 45 degrees                      
 
         [0056]    Strip pFET Photoresist Mask.  
         [0057]    Then the pFET extension/halo mask is stripped away to prepare for Source/Drain formation process.  
         [0058]    Form Source/Drain Spacers  
         [0059]    [0059]FIG. 2K shows the device  20  of FIG. 2J after formation of the source/drain spacers  48  aside from the gate electrode stack ST on the sidewalls thereof. The spacers  48  are formed of an FET spacer material such as silicon nitride, silicon dioxide, silicon oxynitrides or a combination of these films. The spacers  48  can be formed by CVD, PECVD or other deposition techniques followed by directional RIE. The spacer width after etching should be from about 15 nm to about 80 nm.  
         [0060]    Form nFET Source/Drain Mask  
         [0061]    Form a photolithography to mask all areas except where the nFETs such as source/drain regions  52  in FIG. 2L are being formed.  
         [0062]    Perform nFET Source/Drain Implant  
         [0063]    [0063]FIG. 2L shows the device  20  of FIG. 2K during the next step of performing an nFET source/drain implant using the parameters in Table VIA or VIB below or a combination of the two.  
                           TABLE VIA                                       nFET   Source/Drain Implant           Dopant   Arsenic           Energy   5 to 50 Kev           Dose   1E15/cm 2  to 1E16/cm 2             Angle   0 to 10 degrees                      
 
         [0064]    [0064]                           TABLE VIB                                       nFET   Source/Drain Implant           Dopant   Phosphorous           Energy   2 to 20 Kev           Dose   1E15/cm 2  to 1E16/cm 2             Angle   0 to 10 degrees                        
         [0065]    Strip nFET Source/Drain Mask  
         [0066]    Next the nFET source/drain mask is stripped.  
         [0067]    Form pFET Source/Drain Mask  
         [0068]    Form a photolithography to mask all areas except where the pFETs are being formed.  
         [0069]    Perform pFET Source/Drain Implant  
         [0070]    The next step is to perform a pFET source/drain implant using the parameters in Table VIIA or VIIB below.  
                           TABLE VIIA                                       pFET   Source/Drain Implant           Dopant   Boron           Energy   3 to 15 Kev           Dose   1E15/cm 2  to 1E16/cm 2             Angle   0 to 10 degrees                      
 
         [0071]    [0071]                           TABLE VIIB                                   pFET   Source/Drain Implant                           Dopant   BF 2             Energy   10 to 50 Kev           Dose   1E15/cm 2  to 1E16/cm 2             Angle    0 to 10 degrees                        
         [0072]    Photoresist Strip  
         [0073]    Next the nFET source/drain mask is stripped  
         [0074]    Perform Source/Drain Anneal  
                           TABLE VIIIA                                   Source/Drain Anneal   Rapid Thermal Anneal (RTA)                           Temperature   800 to 1100 degrees C.           Time    0 to 60 seconds                      
 
         [0075]    [0075]                           TABLE VIIIB                                   Source/Drain Anneal   Conventional Anneal                           Temperature   850 to 1000 degrees C.           Time    2 to 30 minutes                        
         [0076]    Silicide Formation  
         [0077]    [0077]FIG. 2M shows the device  20  of FIG. 2L after formation of self-aligned silicide layer  54  on the source/drain  52  and polysilicon gate surfaces. Titanium, Cobalt, Nickel or other metals can be used to form the suicide.  
         [0078]    The basic MOSFET transistors are now formed.  
         [0079]    Any one of many contact and metallization schemes known to those skilled in the art of integrated circuit processing can now be used to produce the complete integrated circuit chip.  
         [0080]    Precision Thinning of Selected Region of SOI Wafers  
         [0081]    The process flow of a second embodiment of this invention, which is employed to perform thinning of selected regions of SOI wafers is described below with reference to FIGS. 3A-3C. In accordance with the method of FIGS. 3A-3C, the structure of a device  60 , e.g. a semiconductor chip, is defined in part by production of a precisely controlled gate recess  38  shown in FIG. 3C formed by the selective reactive ion etching of amorphized silicon formed by ion implantation.  
         [0082]    The precision thinning method described above can also be used to produce multiple thicknesses of silicon  24  on buried silicon oxide (BOX) layer  22 , i.e. SOI wafers, so that various electronic devices on the same device  60  can built with the optimal thickness for each device. A process flow for this structure is described below with reference to FIGS. 3A-3C.  
         [0083]    Amorphize Silicon Thickness in Selected Areas  
         [0084]    [0084]FIG. 3A shows an SOI device  60 , which comprises a BOX layer  22  on which a thin silicon layer  24  has been formed. A photoresist mask  32  has been formed on the left side of the device  60  leaving surface of the silicon on the right side exposed. The mask  32  is formed by applying photoresist and exposing it using conventional pholithographic techniques. In FIG. 3A, the exposed silicon is shown being amorphized by the process of ion implantation of ions  361  as described above to form amorphous silicon layer  36  on the right side of device  60 , aside from the mask  32 .  
         [0085]    [0085]FIG. 3B shows the device of FIG. 3A after a selective Reactive Ion Etch (RIE) of the amorphized layer  36  has been performed using the conditions described above to form a recess  38  with a controlled depth, as described above.  
         [0086]    [0086]FIG. 3C shows the device of FIG. 3B after the photoresist mask  32  has been stripped away leaving the device with the thinner silicon layer below the recess.  
         [0087]    The use is made of conventional microelectronic processing methods to form various electronic devices in the regions of silicon thinned to the optimal thickness for each type of device.  
         [0088]    While this invention has been described in terms of the above specific embodiment(s), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims, i.e. that changes can be made in form and detail, without departing from the spirit and scope of the invention. Accordingly all such changes come within the purview of the present invention and the invention encompasses the subject matter of the claims which follow.